Searched refs:_u (Results 1 – 25 of 88) sorted by relevance
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19 #define M33_ITM_STIM0_OFFSET _u(0x00000000)20 #define M33_ITM_STIM0_BITS _u(0xffffffff)21 #define M33_ITM_STIM0_RESET _u(0x00000000)27 #define M33_ITM_STIM0_STIMULUS_RESET _u(0x00000000)28 #define M33_ITM_STIM0_STIMULUS_BITS _u(0xffffffff)29 #define M33_ITM_STIM0_STIMULUS_MSB _u(31)30 #define M33_ITM_STIM0_STIMULUS_LSB _u(0)35 #define M33_ITM_STIM1_OFFSET _u(0x00000004)36 #define M33_ITM_STIM1_BITS _u(0xffffffff)37 #define M33_ITM_STIM1_RESET _u(0x00000000)[all …]
17 #define IO_QSPI_USBPHY_DP_STATUS_OFFSET _u(0x00000000)18 #define IO_QSPI_USBPHY_DP_STATUS_BITS _u(0x04022200)19 #define IO_QSPI_USBPHY_DP_STATUS_RESET _u(0x00000000)23 #define IO_QSPI_USBPHY_DP_STATUS_IRQTOPROC_RESET _u(0x0)24 #define IO_QSPI_USBPHY_DP_STATUS_IRQTOPROC_BITS _u(0x04000000)25 #define IO_QSPI_USBPHY_DP_STATUS_IRQTOPROC_MSB _u(26)26 #define IO_QSPI_USBPHY_DP_STATUS_IRQTOPROC_LSB _u(26)32 #define IO_QSPI_USBPHY_DP_STATUS_INFROMPAD_RESET _u(0x0)33 #define IO_QSPI_USBPHY_DP_STATUS_INFROMPAD_BITS _u(0x00020000)34 #define IO_QSPI_USBPHY_DP_STATUS_INFROMPAD_MSB _u(17)[all …]
19 #define RVCSR_MSTATUS_OFFSET _u(0x00000300)20 #define RVCSR_MSTATUS_BITS _u(0x00221888)21 #define RVCSR_MSTATUS_RESET _u(0x00001800)27 #define RVCSR_MSTATUS_TW_RESET _u(0x0)28 #define RVCSR_MSTATUS_TW_BITS _u(0x00200000)29 #define RVCSR_MSTATUS_TW_MSB _u(21)30 #define RVCSR_MSTATUS_TW_LSB _u(21)38 #define RVCSR_MSTATUS_MPRV_RESET _u(0x0)39 #define RVCSR_MSTATUS_MPRV_BITS _u(0x00020000)40 #define RVCSR_MSTATUS_MPRV_MSB _u(17)[all …]
22 #define DMA_CH0_READ_ADDR_OFFSET _u(0x00000000)23 #define DMA_CH0_READ_ADDR_BITS _u(0xffffffff)24 #define DMA_CH0_READ_ADDR_RESET _u(0x00000000)25 #define DMA_CH0_READ_ADDR_MSB _u(31)26 #define DMA_CH0_READ_ADDR_LSB _u(0)34 #define DMA_CH0_WRITE_ADDR_OFFSET _u(0x00000004)35 #define DMA_CH0_WRITE_ADDR_BITS _u(0xffffffff)36 #define DMA_CH0_WRITE_ADDR_RESET _u(0x00000000)37 #define DMA_CH0_WRITE_ADDR_MSB _u(31)38 #define DMA_CH0_WRITE_ADDR_LSB _u(0)[all …]
17 #define IO_BANK0_GPIO0_STATUS_OFFSET _u(0x00000000)18 #define IO_BANK0_GPIO0_STATUS_BITS _u(0x04022200)19 #define IO_BANK0_GPIO0_STATUS_RESET _u(0x00000000)23 #define IO_BANK0_GPIO0_STATUS_IRQTOPROC_RESET _u(0x0)24 #define IO_BANK0_GPIO0_STATUS_IRQTOPROC_BITS _u(0x04000000)25 #define IO_BANK0_GPIO0_STATUS_IRQTOPROC_MSB _u(26)26 #define IO_BANK0_GPIO0_STATUS_IRQTOPROC_LSB _u(26)32 #define IO_BANK0_GPIO0_STATUS_INFROMPAD_RESET _u(0x0)33 #define IO_BANK0_GPIO0_STATUS_INFROMPAD_BITS _u(0x00020000)34 #define IO_BANK0_GPIO0_STATUS_INFROMPAD_MSB _u(17)[all …]
20 #define PADS_BANK0_VOLTAGE_SELECT_OFFSET _u(0x00000000)21 #define PADS_BANK0_VOLTAGE_SELECT_BITS _u(0x00000001)22 #define PADS_BANK0_VOLTAGE_SELECT_RESET _u(0x00000000)23 #define PADS_BANK0_VOLTAGE_SELECT_MSB _u(0)24 #define PADS_BANK0_VOLTAGE_SELECT_LSB _u(0)26 #define PADS_BANK0_VOLTAGE_SELECT_VALUE_3V3 _u(0x0)27 #define PADS_BANK0_VOLTAGE_SELECT_VALUE_1V8 _u(0x1)30 #define PADS_BANK0_GPIO0_OFFSET _u(0x00000004)31 #define PADS_BANK0_GPIO0_BITS _u(0x000001ff)32 #define PADS_BANK0_GPIO0_RESET _u(0x00000116)[all …]
29 #define ACCESSCTRL_LOCK_OFFSET _u(0x00000000)30 #define ACCESSCTRL_LOCK_BITS _u(0x0000000f)31 #define ACCESSCTRL_LOCK_RESET _u(0x00000004)34 #define ACCESSCTRL_LOCK_DEBUG_RESET _u(0x0)35 #define ACCESSCTRL_LOCK_DEBUG_BITS _u(0x00000008)36 #define ACCESSCTRL_LOCK_DEBUG_MSB _u(3)37 #define ACCESSCTRL_LOCK_DEBUG_LSB _u(3)41 #define ACCESSCTRL_LOCK_DMA_RESET _u(0x1)42 #define ACCESSCTRL_LOCK_DMA_BITS _u(0x00000004)43 #define ACCESSCTRL_LOCK_DMA_MSB _u(2)[all …]
24 #define OTP_SW_LOCK0_OFFSET _u(0x00000000)25 #define OTP_SW_LOCK0_BITS _u(0x0000000f)26 #define OTP_SW_LOCK0_RESET _u(0x00000000)34 #define OTP_SW_LOCK0_NSEC_BITS _u(0x0000000c)35 #define OTP_SW_LOCK0_NSEC_MSB _u(3)36 #define OTP_SW_LOCK0_NSEC_LSB _u(2)38 #define OTP_SW_LOCK0_NSEC_VALUE_READ_WRITE _u(0x0)39 #define OTP_SW_LOCK0_NSEC_VALUE_READ_ONLY _u(0x1)40 #define OTP_SW_LOCK0_NSEC_VALUE_INACCESSIBLE _u(0x3)49 #define OTP_SW_LOCK0_SEC_BITS _u(0x00000003)[all …]
19 #define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_OFFSET _u(0x00000000)20 #define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BITS _u(0xffffffff)21 #define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_RESET _u(0x00000000)24 #define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_WVALUE_RESET _u(0x0000)25 #define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_WVALUE_BITS _u(0xffff0000)26 #define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_WVALUE_MSB _u(31)27 #define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_WVALUE_LSB _u(16)31 #define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BREQUEST_RESET _u(0x00)32 #define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BREQUEST_BITS _u(0x0000ff00)33 #define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BREQUEST_MSB _u(15)[all …]
100 #define I2C_IC_CON_OFFSET _u(0x00000000)101 #define I2C_IC_CON_BITS _u(0x000007ff)102 #define I2C_IC_CON_RESET _u(0x00000065)107 #define I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_RESET _u(0x0)108 #define I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_BITS _u(0x00000400)109 #define I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_MSB _u(10)110 #define I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_LSB _u(10)121 #define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_RESET _u(0x0)122 #define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_BITS _u(0x00000200)123 #define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_MSB _u(9)[all …]
23 #define SIO_CPUID_OFFSET _u(0x00000000)24 #define SIO_CPUID_BITS _u(0xffffffff)26 #define SIO_CPUID_MSB _u(31)27 #define SIO_CPUID_LSB _u(0)35 #define SIO_GPIO_IN_OFFSET _u(0x00000004)36 #define SIO_GPIO_IN_BITS _u(0xffffffff)37 #define SIO_GPIO_IN_RESET _u(0x00000000)38 #define SIO_GPIO_IN_MSB _u(31)39 #define SIO_GPIO_IN_LSB _u(0)47 #define SIO_GPIO_HI_IN_OFFSET _u(0x00000008)[all …]
19 #define PWM_CH0_CSR_OFFSET _u(0x00000000)20 #define PWM_CH0_CSR_BITS _u(0x000000ff)21 #define PWM_CH0_CSR_RESET _u(0x00000000)29 #define PWM_CH0_CSR_PH_ADV_RESET _u(0x0)30 #define PWM_CH0_CSR_PH_ADV_BITS _u(0x00000080)31 #define PWM_CH0_CSR_PH_ADV_MSB _u(7)32 #define PWM_CH0_CSR_PH_ADV_LSB _u(7)40 #define PWM_CH0_CSR_PH_RET_RESET _u(0x0)41 #define PWM_CH0_CSR_PH_RET_BITS _u(0x00000040)42 #define PWM_CH0_CSR_PH_RET_MSB _u(6)[all …]
19 #define USB_ADDR_ENDP_OFFSET _u(0x00000000)20 #define USB_ADDR_ENDP_BITS _u(0x000f007f)21 #define USB_ADDR_ENDP_RESET _u(0x00000000)25 #define USB_ADDR_ENDP_ENDPOINT_RESET _u(0x0)26 #define USB_ADDR_ENDP_ENDPOINT_BITS _u(0x000f0000)27 #define USB_ADDR_ENDP_ENDPOINT_MSB _u(19)28 #define USB_ADDR_ENDP_ENDPOINT_LSB _u(16)35 #define USB_ADDR_ENDP_ADDRESS_RESET _u(0x00)36 #define USB_ADDR_ENDP_ADDRESS_BITS _u(0x0000007f)37 #define USB_ADDR_ENDP_ADDRESS_MSB _u(6)[all …]
18 #define CLOCKS_CLK_GPOUT0_CTRL_OFFSET _u(0x00000000)19 #define CLOCKS_CLK_GPOUT0_CTRL_BITS _u(0x10131de0)20 #define CLOCKS_CLK_GPOUT0_CTRL_RESET _u(0x00000000)24 #define CLOCKS_CLK_GPOUT0_CTRL_ENABLED_RESET _u(0x0)25 #define CLOCKS_CLK_GPOUT0_CTRL_ENABLED_BITS _u(0x10000000)26 #define CLOCKS_CLK_GPOUT0_CTRL_ENABLED_MSB _u(28)27 #define CLOCKS_CLK_GPOUT0_CTRL_ENABLED_LSB _u(28)34 #define CLOCKS_CLK_GPOUT0_CTRL_NUDGE_RESET _u(0x0)35 #define CLOCKS_CLK_GPOUT0_CTRL_NUDGE_BITS _u(0x00100000)36 #define CLOCKS_CLK_GPOUT0_CTRL_NUDGE_MSB _u(20)[all …]
21 #define POWMAN_BADPASSWD_OFFSET _u(0x00000000)22 #define POWMAN_BADPASSWD_BITS _u(0x00000001)23 #define POWMAN_BADPASSWD_RESET _u(0x00000000)24 #define POWMAN_BADPASSWD_MSB _u(0)25 #define POWMAN_BADPASSWD_LSB _u(0)30 #define POWMAN_VREG_CTRL_OFFSET _u(0x00000004)31 #define POWMAN_VREG_CTRL_BITS _u(0x0000b170)32 #define POWMAN_VREG_CTRL_RESET _u(0x00008050)38 #define POWMAN_VREG_CTRL_RST_N_RESET _u(0x1)39 #define POWMAN_VREG_CTRL_RST_N_BITS _u(0x00008000)[all …]
18 #define CLOCKS_CLK_GPOUT0_CTRL_OFFSET _u(0x00000000)19 #define CLOCKS_CLK_GPOUT0_CTRL_BITS _u(0x00131de0)20 #define CLOCKS_CLK_GPOUT0_CTRL_RESET _u(0x00000000)26 #define CLOCKS_CLK_GPOUT0_CTRL_NUDGE_RESET _u(0x0)27 #define CLOCKS_CLK_GPOUT0_CTRL_NUDGE_BITS _u(0x00100000)28 #define CLOCKS_CLK_GPOUT0_CTRL_NUDGE_MSB _u(20)29 #define CLOCKS_CLK_GPOUT0_CTRL_NUDGE_LSB _u(20)36 #define CLOCKS_CLK_GPOUT0_CTRL_PHASE_RESET _u(0x0)37 #define CLOCKS_CLK_GPOUT0_CTRL_PHASE_BITS _u(0x00030000)38 #define CLOCKS_CLK_GPOUT0_CTRL_PHASE_MSB _u(17)[all …]
20 #define PADS_BANK0_VOLTAGE_SELECT_OFFSET _u(0x00000000)21 #define PADS_BANK0_VOLTAGE_SELECT_BITS _u(0x00000001)22 #define PADS_BANK0_VOLTAGE_SELECT_RESET _u(0x00000000)23 #define PADS_BANK0_VOLTAGE_SELECT_MSB _u(0)24 #define PADS_BANK0_VOLTAGE_SELECT_LSB _u(0)26 #define PADS_BANK0_VOLTAGE_SELECT_VALUE_3V3 _u(0x0)27 #define PADS_BANK0_VOLTAGE_SELECT_VALUE_1V8 _u(0x1)31 #define PADS_BANK0_GPIO0_OFFSET _u(0x00000004)32 #define PADS_BANK0_GPIO0_BITS _u(0x000000ff)33 #define PADS_BANK0_GPIO0_RESET _u(0x00000056)[all …]
18 #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OFFSET _u(0x00000000)19 #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_BITS _u(0x050a3300)20 #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_RESET _u(0x00000000)24 #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_RESET _u(0x0)25 #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_BITS _u(0x04000000)26 #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_MSB _u(26)27 #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_LSB _u(26)32 #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQFROMPAD_RESET _u(0x0)33 #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQFROMPAD_BITS _u(0x01000000)34 #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQFROMPAD_MSB _u(24)[all …]
19 #define PIO_CTRL_OFFSET _u(0x00000000)20 #define PIO_CTRL_BITS _u(0x00000fff)21 #define PIO_CTRL_RESET _u(0x00000000)42 #define PIO_CTRL_CLKDIV_RESTART_RESET _u(0x0)43 #define PIO_CTRL_CLKDIV_RESTART_BITS _u(0x00000f00)44 #define PIO_CTRL_CLKDIV_RESTART_MSB _u(11)45 #define PIO_CTRL_CLKDIV_RESTART_LSB _u(8)60 #define PIO_CTRL_SM_RESTART_RESET _u(0x0)61 #define PIO_CTRL_SM_RESTART_BITS _u(0x000000f0)62 #define PIO_CTRL_SM_RESTART_MSB _u(7)[all …]
18 #define IO_BANK0_GPIO0_STATUS_OFFSET _u(0x00000000)19 #define IO_BANK0_GPIO0_STATUS_BITS _u(0x050a3300)20 #define IO_BANK0_GPIO0_STATUS_RESET _u(0x00000000)24 #define IO_BANK0_GPIO0_STATUS_IRQTOPROC_RESET _u(0x0)25 #define IO_BANK0_GPIO0_STATUS_IRQTOPROC_BITS _u(0x04000000)26 #define IO_BANK0_GPIO0_STATUS_IRQTOPROC_MSB _u(26)27 #define IO_BANK0_GPIO0_STATUS_IRQTOPROC_LSB _u(26)32 #define IO_BANK0_GPIO0_STATUS_IRQFROMPAD_RESET _u(0x0)33 #define IO_BANK0_GPIO0_STATUS_IRQFROMPAD_BITS _u(0x01000000)34 #define IO_BANK0_GPIO0_STATUS_IRQFROMPAD_MSB _u(24)[all …]
23 #define SIO_CPUID_OFFSET _u(0x00000000)24 #define SIO_CPUID_BITS _u(0xffffffff)26 #define SIO_CPUID_MSB _u(31)27 #define SIO_CPUID_LSB _u(0)33 #define SIO_GPIO_IN_OFFSET _u(0x00000004)34 #define SIO_GPIO_IN_BITS _u(0x3fffffff)35 #define SIO_GPIO_IN_RESET _u(0x00000000)36 #define SIO_GPIO_IN_MSB _u(29)37 #define SIO_GPIO_IN_LSB _u(0)44 #define SIO_GPIO_HI_IN_OFFSET _u(0x00000008)[all …]
