1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT 2 3 /** 4 * Copyright (c) 2024 Raspberry Pi Ltd. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 // ============================================================================= 9 // Register block : PADS_BANK0 10 // Version : 1 11 // Bus type : apb 12 // ============================================================================= 13 #ifndef _HARDWARE_REGS_PADS_BANK0_H 14 #define _HARDWARE_REGS_PADS_BANK0_H 15 // ============================================================================= 16 // Register : PADS_BANK0_VOLTAGE_SELECT 17 // Description : Voltage select. Per bank control 18 // 0x0 -> Set voltage to 3.3V (DVDD >= 2V5) 19 // 0x1 -> Set voltage to 1.8V (DVDD <= 1V8) 20 #define PADS_BANK0_VOLTAGE_SELECT_OFFSET _u(0x00000000) 21 #define PADS_BANK0_VOLTAGE_SELECT_BITS _u(0x00000001) 22 #define PADS_BANK0_VOLTAGE_SELECT_RESET _u(0x00000000) 23 #define PADS_BANK0_VOLTAGE_SELECT_MSB _u(0) 24 #define PADS_BANK0_VOLTAGE_SELECT_LSB _u(0) 25 #define PADS_BANK0_VOLTAGE_SELECT_ACCESS "RW" 26 #define PADS_BANK0_VOLTAGE_SELECT_VALUE_3V3 _u(0x0) 27 #define PADS_BANK0_VOLTAGE_SELECT_VALUE_1V8 _u(0x1) 28 // ============================================================================= 29 // Register : PADS_BANK0_GPIO0 30 // Description : Pad control register 31 #define PADS_BANK0_GPIO0_OFFSET _u(0x00000004) 32 #define PADS_BANK0_GPIO0_BITS _u(0x000000ff) 33 #define PADS_BANK0_GPIO0_RESET _u(0x00000056) 34 // ----------------------------------------------------------------------------- 35 // Field : PADS_BANK0_GPIO0_OD 36 // Description : Output disable. Has priority over output enable from 37 // peripherals 38 #define PADS_BANK0_GPIO0_OD_RESET _u(0x0) 39 #define PADS_BANK0_GPIO0_OD_BITS _u(0x00000080) 40 #define PADS_BANK0_GPIO0_OD_MSB _u(7) 41 #define PADS_BANK0_GPIO0_OD_LSB _u(7) 42 #define PADS_BANK0_GPIO0_OD_ACCESS "RW" 43 // ----------------------------------------------------------------------------- 44 // Field : PADS_BANK0_GPIO0_IE 45 // Description : Input enable 46 #define PADS_BANK0_GPIO0_IE_RESET _u(0x1) 47 #define PADS_BANK0_GPIO0_IE_BITS _u(0x00000040) 48 #define PADS_BANK0_GPIO0_IE_MSB _u(6) 49 #define PADS_BANK0_GPIO0_IE_LSB _u(6) 50 #define PADS_BANK0_GPIO0_IE_ACCESS "RW" 51 // ----------------------------------------------------------------------------- 52 // Field : PADS_BANK0_GPIO0_DRIVE 53 // Description : Drive strength. 54 // 0x0 -> 2mA 55 // 0x1 -> 4mA 56 // 0x2 -> 8mA 57 // 0x3 -> 12mA 58 #define PADS_BANK0_GPIO0_DRIVE_RESET _u(0x1) 59 #define PADS_BANK0_GPIO0_DRIVE_BITS _u(0x00000030) 60 #define PADS_BANK0_GPIO0_DRIVE_MSB _u(5) 61 #define PADS_BANK0_GPIO0_DRIVE_LSB _u(4) 62 #define PADS_BANK0_GPIO0_DRIVE_ACCESS "RW" 63 #define PADS_BANK0_GPIO0_DRIVE_VALUE_2MA _u(0x0) 64 #define PADS_BANK0_GPIO0_DRIVE_VALUE_4MA _u(0x1) 65 #define PADS_BANK0_GPIO0_DRIVE_VALUE_8MA _u(0x2) 66 #define PADS_BANK0_GPIO0_DRIVE_VALUE_12MA _u(0x3) 67 // ----------------------------------------------------------------------------- 68 // Field : PADS_BANK0_GPIO0_PUE 69 // Description : Pull up enable 70 #define PADS_BANK0_GPIO0_PUE_RESET _u(0x0) 71 #define PADS_BANK0_GPIO0_PUE_BITS _u(0x00000008) 72 #define PADS_BANK0_GPIO0_PUE_MSB _u(3) 73 #define PADS_BANK0_GPIO0_PUE_LSB _u(3) 74 #define PADS_BANK0_GPIO0_PUE_ACCESS "RW" 75 // ----------------------------------------------------------------------------- 76 // Field : PADS_BANK0_GPIO0_PDE 77 // Description : Pull down enable 78 #define PADS_BANK0_GPIO0_PDE_RESET _u(0x1) 79 #define PADS_BANK0_GPIO0_PDE_BITS _u(0x00000004) 80 #define PADS_BANK0_GPIO0_PDE_MSB _u(2) 81 #define PADS_BANK0_GPIO0_PDE_LSB _u(2) 82 #define PADS_BANK0_GPIO0_PDE_ACCESS "RW" 83 // ----------------------------------------------------------------------------- 84 // Field : PADS_BANK0_GPIO0_SCHMITT 85 // Description : Enable schmitt trigger 86 #define PADS_BANK0_GPIO0_SCHMITT_RESET _u(0x1) 87 #define PADS_BANK0_GPIO0_SCHMITT_BITS _u(0x00000002) 88 #define PADS_BANK0_GPIO0_SCHMITT_MSB _u(1) 89 #define PADS_BANK0_GPIO0_SCHMITT_LSB _u(1) 90 #define PADS_BANK0_GPIO0_SCHMITT_ACCESS "RW" 91 // ----------------------------------------------------------------------------- 92 // Field : PADS_BANK0_GPIO0_SLEWFAST 93 // Description : Slew rate control. 1 = Fast, 0 = Slow 94 #define PADS_BANK0_GPIO0_SLEWFAST_RESET _u(0x0) 95 #define PADS_BANK0_GPIO0_SLEWFAST_BITS _u(0x00000001) 96 #define PADS_BANK0_GPIO0_SLEWFAST_MSB _u(0) 97 #define PADS_BANK0_GPIO0_SLEWFAST_LSB _u(0) 98 #define PADS_BANK0_GPIO0_SLEWFAST_ACCESS "RW" 99 // ============================================================================= 100 // Register : PADS_BANK0_GPIO1 101 // Description : Pad control register 102 #define PADS_BANK0_GPIO1_OFFSET _u(0x00000008) 103 #define PADS_BANK0_GPIO1_BITS _u(0x000000ff) 104 #define PADS_BANK0_GPIO1_RESET _u(0x00000056) 105 // ----------------------------------------------------------------------------- 106 // Field : PADS_BANK0_GPIO1_OD 107 // Description : Output disable. Has priority over output enable from 108 // peripherals 109 #define PADS_BANK0_GPIO1_OD_RESET _u(0x0) 110 #define PADS_BANK0_GPIO1_OD_BITS _u(0x00000080) 111 #define PADS_BANK0_GPIO1_OD_MSB _u(7) 112 #define PADS_BANK0_GPIO1_OD_LSB _u(7) 113 #define PADS_BANK0_GPIO1_OD_ACCESS "RW" 114 // ----------------------------------------------------------------------------- 115 // Field : PADS_BANK0_GPIO1_IE 116 // Description : Input enable 117 #define PADS_BANK0_GPIO1_IE_RESET _u(0x1) 118 #define PADS_BANK0_GPIO1_IE_BITS _u(0x00000040) 119 #define PADS_BANK0_GPIO1_IE_MSB _u(6) 120 #define PADS_BANK0_GPIO1_IE_LSB _u(6) 121 #define PADS_BANK0_GPIO1_IE_ACCESS "RW" 122 // ----------------------------------------------------------------------------- 123 // Field : PADS_BANK0_GPIO1_DRIVE 124 // Description : Drive strength. 125 // 0x0 -> 2mA 126 // 0x1 -> 4mA 127 // 0x2 -> 8mA 128 // 0x3 -> 12mA 129 #define PADS_BANK0_GPIO1_DRIVE_RESET _u(0x1) 130 #define PADS_BANK0_GPIO1_DRIVE_BITS _u(0x00000030) 131 #define PADS_BANK0_GPIO1_DRIVE_MSB _u(5) 132 #define PADS_BANK0_GPIO1_DRIVE_LSB _u(4) 133 #define PADS_BANK0_GPIO1_DRIVE_ACCESS "RW" 134 #define PADS_BANK0_GPIO1_DRIVE_VALUE_2MA _u(0x0) 135 #define PADS_BANK0_GPIO1_DRIVE_VALUE_4MA _u(0x1) 136 #define PADS_BANK0_GPIO1_DRIVE_VALUE_8MA _u(0x2) 137 #define PADS_BANK0_GPIO1_DRIVE_VALUE_12MA _u(0x3) 138 // ----------------------------------------------------------------------------- 139 // Field : PADS_BANK0_GPIO1_PUE 140 // Description : Pull up enable 141 #define PADS_BANK0_GPIO1_PUE_RESET _u(0x0) 142 #define PADS_BANK0_GPIO1_PUE_BITS _u(0x00000008) 143 #define PADS_BANK0_GPIO1_PUE_MSB _u(3) 144 #define PADS_BANK0_GPIO1_PUE_LSB _u(3) 145 #define PADS_BANK0_GPIO1_PUE_ACCESS "RW" 146 // ----------------------------------------------------------------------------- 147 // Field : PADS_BANK0_GPIO1_PDE 148 // Description : Pull down enable 149 #define PADS_BANK0_GPIO1_PDE_RESET _u(0x1) 150 #define PADS_BANK0_GPIO1_PDE_BITS _u(0x00000004) 151 #define PADS_BANK0_GPIO1_PDE_MSB _u(2) 152 #define PADS_BANK0_GPIO1_PDE_LSB _u(2) 153 #define PADS_BANK0_GPIO1_PDE_ACCESS "RW" 154 // ----------------------------------------------------------------------------- 155 // Field : PADS_BANK0_GPIO1_SCHMITT 156 // Description : Enable schmitt trigger 157 #define PADS_BANK0_GPIO1_SCHMITT_RESET _u(0x1) 158 #define PADS_BANK0_GPIO1_SCHMITT_BITS _u(0x00000002) 159 #define PADS_BANK0_GPIO1_SCHMITT_MSB _u(1) 160 #define PADS_BANK0_GPIO1_SCHMITT_LSB _u(1) 161 #define PADS_BANK0_GPIO1_SCHMITT_ACCESS "RW" 162 // ----------------------------------------------------------------------------- 163 // Field : PADS_BANK0_GPIO1_SLEWFAST 164 // Description : Slew rate control. 1 = Fast, 0 = Slow 165 #define PADS_BANK0_GPIO1_SLEWFAST_RESET _u(0x0) 166 #define PADS_BANK0_GPIO1_SLEWFAST_BITS _u(0x00000001) 167 #define PADS_BANK0_GPIO1_SLEWFAST_MSB _u(0) 168 #define PADS_BANK0_GPIO1_SLEWFAST_LSB _u(0) 169 #define PADS_BANK0_GPIO1_SLEWFAST_ACCESS "RW" 170 // ============================================================================= 171 // Register : PADS_BANK0_GPIO2 172 // Description : Pad control register 173 #define PADS_BANK0_GPIO2_OFFSET _u(0x0000000c) 174 #define PADS_BANK0_GPIO2_BITS _u(0x000000ff) 175 #define PADS_BANK0_GPIO2_RESET _u(0x00000056) 176 // ----------------------------------------------------------------------------- 177 // Field : PADS_BANK0_GPIO2_OD 178 // Description : Output disable. Has priority over output enable from 179 // peripherals 180 #define PADS_BANK0_GPIO2_OD_RESET _u(0x0) 181 #define PADS_BANK0_GPIO2_OD_BITS _u(0x00000080) 182 #define PADS_BANK0_GPIO2_OD_MSB _u(7) 183 #define PADS_BANK0_GPIO2_OD_LSB _u(7) 184 #define PADS_BANK0_GPIO2_OD_ACCESS "RW" 185 // ----------------------------------------------------------------------------- 186 // Field : PADS_BANK0_GPIO2_IE 187 // Description : Input enable 188 #define PADS_BANK0_GPIO2_IE_RESET _u(0x1) 189 #define PADS_BANK0_GPIO2_IE_BITS _u(0x00000040) 190 #define PADS_BANK0_GPIO2_IE_MSB _u(6) 191 #define PADS_BANK0_GPIO2_IE_LSB _u(6) 192 #define PADS_BANK0_GPIO2_IE_ACCESS "RW" 193 // ----------------------------------------------------------------------------- 194 // Field : PADS_BANK0_GPIO2_DRIVE 195 // Description : Drive strength. 196 // 0x0 -> 2mA 197 // 0x1 -> 4mA 198 // 0x2 -> 8mA 199 // 0x3 -> 12mA 200 #define PADS_BANK0_GPIO2_DRIVE_RESET _u(0x1) 201 #define PADS_BANK0_GPIO2_DRIVE_BITS _u(0x00000030) 202 #define PADS_BANK0_GPIO2_DRIVE_MSB _u(5) 203 #define PADS_BANK0_GPIO2_DRIVE_LSB _u(4) 204 #define PADS_BANK0_GPIO2_DRIVE_ACCESS "RW" 205 #define PADS_BANK0_GPIO2_DRIVE_VALUE_2MA _u(0x0) 206 #define PADS_BANK0_GPIO2_DRIVE_VALUE_4MA _u(0x1) 207 #define PADS_BANK0_GPIO2_DRIVE_VALUE_8MA _u(0x2) 208 #define PADS_BANK0_GPIO2_DRIVE_VALUE_12MA _u(0x3) 209 // ----------------------------------------------------------------------------- 210 // Field : PADS_BANK0_GPIO2_PUE 211 // Description : Pull up enable 212 #define PADS_BANK0_GPIO2_PUE_RESET _u(0x0) 213 #define PADS_BANK0_GPIO2_PUE_BITS _u(0x00000008) 214 #define PADS_BANK0_GPIO2_PUE_MSB _u(3) 215 #define PADS_BANK0_GPIO2_PUE_LSB _u(3) 216 #define PADS_BANK0_GPIO2_PUE_ACCESS "RW" 217 // ----------------------------------------------------------------------------- 218 // Field : PADS_BANK0_GPIO2_PDE 219 // Description : Pull down enable 220 #define PADS_BANK0_GPIO2_PDE_RESET _u(0x1) 221 #define PADS_BANK0_GPIO2_PDE_BITS _u(0x00000004) 222 #define PADS_BANK0_GPIO2_PDE_MSB _u(2) 223 #define PADS_BANK0_GPIO2_PDE_LSB _u(2) 224 #define PADS_BANK0_GPIO2_PDE_ACCESS "RW" 225 // ----------------------------------------------------------------------------- 226 // Field : PADS_BANK0_GPIO2_SCHMITT 227 // Description : Enable schmitt trigger 228 #define PADS_BANK0_GPIO2_SCHMITT_RESET _u(0x1) 229 #define PADS_BANK0_GPIO2_SCHMITT_BITS _u(0x00000002) 230 #define PADS_BANK0_GPIO2_SCHMITT_MSB _u(1) 231 #define PADS_BANK0_GPIO2_SCHMITT_LSB _u(1) 232 #define PADS_BANK0_GPIO2_SCHMITT_ACCESS "RW" 233 // ----------------------------------------------------------------------------- 234 // Field : PADS_BANK0_GPIO2_SLEWFAST 235 // Description : Slew rate control. 1 = Fast, 0 = Slow 236 #define PADS_BANK0_GPIO2_SLEWFAST_RESET _u(0x0) 237 #define PADS_BANK0_GPIO2_SLEWFAST_BITS _u(0x00000001) 238 #define PADS_BANK0_GPIO2_SLEWFAST_MSB _u(0) 239 #define PADS_BANK0_GPIO2_SLEWFAST_LSB _u(0) 240 #define PADS_BANK0_GPIO2_SLEWFAST_ACCESS "RW" 241 // ============================================================================= 242 // Register : PADS_BANK0_GPIO3 243 // Description : Pad control register 244 #define PADS_BANK0_GPIO3_OFFSET _u(0x00000010) 245 #define PADS_BANK0_GPIO3_BITS _u(0x000000ff) 246 #define PADS_BANK0_GPIO3_RESET _u(0x00000056) 247 // ----------------------------------------------------------------------------- 248 // Field : PADS_BANK0_GPIO3_OD 249 // Description : Output disable. Has priority over output enable from 250 // peripherals 251 #define PADS_BANK0_GPIO3_OD_RESET _u(0x0) 252 #define PADS_BANK0_GPIO3_OD_BITS _u(0x00000080) 253 #define PADS_BANK0_GPIO3_OD_MSB _u(7) 254 #define PADS_BANK0_GPIO3_OD_LSB _u(7) 255 #define PADS_BANK0_GPIO3_OD_ACCESS "RW" 256 // ----------------------------------------------------------------------------- 257 // Field : PADS_BANK0_GPIO3_IE 258 // Description : Input enable 259 #define PADS_BANK0_GPIO3_IE_RESET _u(0x1) 260 #define PADS_BANK0_GPIO3_IE_BITS _u(0x00000040) 261 #define PADS_BANK0_GPIO3_IE_MSB _u(6) 262 #define PADS_BANK0_GPIO3_IE_LSB _u(6) 263 #define PADS_BANK0_GPIO3_IE_ACCESS "RW" 264 // ----------------------------------------------------------------------------- 265 // Field : PADS_BANK0_GPIO3_DRIVE 266 // Description : Drive strength. 267 // 0x0 -> 2mA 268 // 0x1 -> 4mA 269 // 0x2 -> 8mA 270 // 0x3 -> 12mA 271 #define PADS_BANK0_GPIO3_DRIVE_RESET _u(0x1) 272 #define PADS_BANK0_GPIO3_DRIVE_BITS _u(0x00000030) 273 #define PADS_BANK0_GPIO3_DRIVE_MSB _u(5) 274 #define PADS_BANK0_GPIO3_DRIVE_LSB _u(4) 275 #define PADS_BANK0_GPIO3_DRIVE_ACCESS "RW" 276 #define PADS_BANK0_GPIO3_DRIVE_VALUE_2MA _u(0x0) 277 #define PADS_BANK0_GPIO3_DRIVE_VALUE_4MA _u(0x1) 278 #define PADS_BANK0_GPIO3_DRIVE_VALUE_8MA _u(0x2) 279 #define PADS_BANK0_GPIO3_DRIVE_VALUE_12MA _u(0x3) 280 // ----------------------------------------------------------------------------- 281 // Field : PADS_BANK0_GPIO3_PUE 282 // Description : Pull up enable 283 #define PADS_BANK0_GPIO3_PUE_RESET _u(0x0) 284 #define PADS_BANK0_GPIO3_PUE_BITS _u(0x00000008) 285 #define PADS_BANK0_GPIO3_PUE_MSB _u(3) 286 #define PADS_BANK0_GPIO3_PUE_LSB _u(3) 287 #define PADS_BANK0_GPIO3_PUE_ACCESS "RW" 288 // ----------------------------------------------------------------------------- 289 // Field : PADS_BANK0_GPIO3_PDE 290 // Description : Pull down enable 291 #define PADS_BANK0_GPIO3_PDE_RESET _u(0x1) 292 #define PADS_BANK0_GPIO3_PDE_BITS _u(0x00000004) 293 #define PADS_BANK0_GPIO3_PDE_MSB _u(2) 294 #define PADS_BANK0_GPIO3_PDE_LSB _u(2) 295 #define PADS_BANK0_GPIO3_PDE_ACCESS "RW" 296 // ----------------------------------------------------------------------------- 297 // Field : PADS_BANK0_GPIO3_SCHMITT 298 // Description : Enable schmitt trigger 299 #define PADS_BANK0_GPIO3_SCHMITT_RESET _u(0x1) 300 #define PADS_BANK0_GPIO3_SCHMITT_BITS _u(0x00000002) 301 #define PADS_BANK0_GPIO3_SCHMITT_MSB _u(1) 302 #define PADS_BANK0_GPIO3_SCHMITT_LSB _u(1) 303 #define PADS_BANK0_GPIO3_SCHMITT_ACCESS "RW" 304 // ----------------------------------------------------------------------------- 305 // Field : PADS_BANK0_GPIO3_SLEWFAST 306 // Description : Slew rate control. 1 = Fast, 0 = Slow 307 #define PADS_BANK0_GPIO3_SLEWFAST_RESET _u(0x0) 308 #define PADS_BANK0_GPIO3_SLEWFAST_BITS _u(0x00000001) 309 #define PADS_BANK0_GPIO3_SLEWFAST_MSB _u(0) 310 #define PADS_BANK0_GPIO3_SLEWFAST_LSB _u(0) 311 #define PADS_BANK0_GPIO3_SLEWFAST_ACCESS "RW" 312 // ============================================================================= 313 // Register : PADS_BANK0_GPIO4 314 // Description : Pad control register 315 #define PADS_BANK0_GPIO4_OFFSET _u(0x00000014) 316 #define PADS_BANK0_GPIO4_BITS _u(0x000000ff) 317 #define PADS_BANK0_GPIO4_RESET _u(0x00000056) 318 // ----------------------------------------------------------------------------- 319 // Field : PADS_BANK0_GPIO4_OD 320 // Description : Output disable. Has priority over output enable from 321 // peripherals 322 #define PADS_BANK0_GPIO4_OD_RESET _u(0x0) 323 #define PADS_BANK0_GPIO4_OD_BITS _u(0x00000080) 324 #define PADS_BANK0_GPIO4_OD_MSB _u(7) 325 #define PADS_BANK0_GPIO4_OD_LSB _u(7) 326 #define PADS_BANK0_GPIO4_OD_ACCESS "RW" 327 // ----------------------------------------------------------------------------- 328 // Field : PADS_BANK0_GPIO4_IE 329 // Description : Input enable 330 #define PADS_BANK0_GPIO4_IE_RESET _u(0x1) 331 #define PADS_BANK0_GPIO4_IE_BITS _u(0x00000040) 332 #define PADS_BANK0_GPIO4_IE_MSB _u(6) 333 #define PADS_BANK0_GPIO4_IE_LSB _u(6) 334 #define PADS_BANK0_GPIO4_IE_ACCESS "RW" 335 // ----------------------------------------------------------------------------- 336 // Field : PADS_BANK0_GPIO4_DRIVE 337 // Description : Drive strength. 338 // 0x0 -> 2mA 339 // 0x1 -> 4mA 340 // 0x2 -> 8mA 341 // 0x3 -> 12mA 342 #define PADS_BANK0_GPIO4_DRIVE_RESET _u(0x1) 343 #define PADS_BANK0_GPIO4_DRIVE_BITS _u(0x00000030) 344 #define PADS_BANK0_GPIO4_DRIVE_MSB _u(5) 345 #define PADS_BANK0_GPIO4_DRIVE_LSB _u(4) 346 #define PADS_BANK0_GPIO4_DRIVE_ACCESS "RW" 347 #define PADS_BANK0_GPIO4_DRIVE_VALUE_2MA _u(0x0) 348 #define PADS_BANK0_GPIO4_DRIVE_VALUE_4MA _u(0x1) 349 #define PADS_BANK0_GPIO4_DRIVE_VALUE_8MA _u(0x2) 350 #define PADS_BANK0_GPIO4_DRIVE_VALUE_12MA _u(0x3) 351 // ----------------------------------------------------------------------------- 352 // Field : PADS_BANK0_GPIO4_PUE 353 // Description : Pull up enable 354 #define PADS_BANK0_GPIO4_PUE_RESET _u(0x0) 355 #define PADS_BANK0_GPIO4_PUE_BITS _u(0x00000008) 356 #define PADS_BANK0_GPIO4_PUE_MSB _u(3) 357 #define PADS_BANK0_GPIO4_PUE_LSB _u(3) 358 #define PADS_BANK0_GPIO4_PUE_ACCESS "RW" 359 // ----------------------------------------------------------------------------- 360 // Field : PADS_BANK0_GPIO4_PDE 361 // Description : Pull down enable 362 #define PADS_BANK0_GPIO4_PDE_RESET _u(0x1) 363 #define PADS_BANK0_GPIO4_PDE_BITS _u(0x00000004) 364 #define PADS_BANK0_GPIO4_PDE_MSB _u(2) 365 #define PADS_BANK0_GPIO4_PDE_LSB _u(2) 366 #define PADS_BANK0_GPIO4_PDE_ACCESS "RW" 367 // ----------------------------------------------------------------------------- 368 // Field : PADS_BANK0_GPIO4_SCHMITT 369 // Description : Enable schmitt trigger 370 #define PADS_BANK0_GPIO4_SCHMITT_RESET _u(0x1) 371 #define PADS_BANK0_GPIO4_SCHMITT_BITS _u(0x00000002) 372 #define PADS_BANK0_GPIO4_SCHMITT_MSB _u(1) 373 #define PADS_BANK0_GPIO4_SCHMITT_LSB _u(1) 374 #define PADS_BANK0_GPIO4_SCHMITT_ACCESS "RW" 375 // ----------------------------------------------------------------------------- 376 // Field : PADS_BANK0_GPIO4_SLEWFAST 377 // Description : Slew rate control. 1 = Fast, 0 = Slow 378 #define PADS_BANK0_GPIO4_SLEWFAST_RESET _u(0x0) 379 #define PADS_BANK0_GPIO4_SLEWFAST_BITS _u(0x00000001) 380 #define PADS_BANK0_GPIO4_SLEWFAST_MSB _u(0) 381 #define PADS_BANK0_GPIO4_SLEWFAST_LSB _u(0) 382 #define PADS_BANK0_GPIO4_SLEWFAST_ACCESS "RW" 383 // ============================================================================= 384 // Register : PADS_BANK0_GPIO5 385 // Description : Pad control register 386 #define PADS_BANK0_GPIO5_OFFSET _u(0x00000018) 387 #define PADS_BANK0_GPIO5_BITS _u(0x000000ff) 388 #define PADS_BANK0_GPIO5_RESET _u(0x00000056) 389 // ----------------------------------------------------------------------------- 390 // Field : PADS_BANK0_GPIO5_OD 391 // Description : Output disable. Has priority over output enable from 392 // peripherals 393 #define PADS_BANK0_GPIO5_OD_RESET _u(0x0) 394 #define PADS_BANK0_GPIO5_OD_BITS _u(0x00000080) 395 #define PADS_BANK0_GPIO5_OD_MSB _u(7) 396 #define PADS_BANK0_GPIO5_OD_LSB _u(7) 397 #define PADS_BANK0_GPIO5_OD_ACCESS "RW" 398 // ----------------------------------------------------------------------------- 399 // Field : PADS_BANK0_GPIO5_IE 400 // Description : Input enable 401 #define PADS_BANK0_GPIO5_IE_RESET _u(0x1) 402 #define PADS_BANK0_GPIO5_IE_BITS _u(0x00000040) 403 #define PADS_BANK0_GPIO5_IE_MSB _u(6) 404 #define PADS_BANK0_GPIO5_IE_LSB _u(6) 405 #define PADS_BANK0_GPIO5_IE_ACCESS "RW" 406 // ----------------------------------------------------------------------------- 407 // Field : PADS_BANK0_GPIO5_DRIVE 408 // Description : Drive strength. 409 // 0x0 -> 2mA 410 // 0x1 -> 4mA 411 // 0x2 -> 8mA 412 // 0x3 -> 12mA 413 #define PADS_BANK0_GPIO5_DRIVE_RESET _u(0x1) 414 #define PADS_BANK0_GPIO5_DRIVE_BITS _u(0x00000030) 415 #define PADS_BANK0_GPIO5_DRIVE_MSB _u(5) 416 #define PADS_BANK0_GPIO5_DRIVE_LSB _u(4) 417 #define PADS_BANK0_GPIO5_DRIVE_ACCESS "RW" 418 #define PADS_BANK0_GPIO5_DRIVE_VALUE_2MA _u(0x0) 419 #define PADS_BANK0_GPIO5_DRIVE_VALUE_4MA _u(0x1) 420 #define PADS_BANK0_GPIO5_DRIVE_VALUE_8MA _u(0x2) 421 #define PADS_BANK0_GPIO5_DRIVE_VALUE_12MA _u(0x3) 422 // ----------------------------------------------------------------------------- 423 // Field : PADS_BANK0_GPIO5_PUE 424 // Description : Pull up enable 425 #define PADS_BANK0_GPIO5_PUE_RESET _u(0x0) 426 #define PADS_BANK0_GPIO5_PUE_BITS _u(0x00000008) 427 #define PADS_BANK0_GPIO5_PUE_MSB _u(3) 428 #define PADS_BANK0_GPIO5_PUE_LSB _u(3) 429 #define PADS_BANK0_GPIO5_PUE_ACCESS "RW" 430 // ----------------------------------------------------------------------------- 431 // Field : PADS_BANK0_GPIO5_PDE 432 // Description : Pull down enable 433 #define PADS_BANK0_GPIO5_PDE_RESET _u(0x1) 434 #define PADS_BANK0_GPIO5_PDE_BITS _u(0x00000004) 435 #define PADS_BANK0_GPIO5_PDE_MSB _u(2) 436 #define PADS_BANK0_GPIO5_PDE_LSB _u(2) 437 #define PADS_BANK0_GPIO5_PDE_ACCESS "RW" 438 // ----------------------------------------------------------------------------- 439 // Field : PADS_BANK0_GPIO5_SCHMITT 440 // Description : Enable schmitt trigger 441 #define PADS_BANK0_GPIO5_SCHMITT_RESET _u(0x1) 442 #define PADS_BANK0_GPIO5_SCHMITT_BITS _u(0x00000002) 443 #define PADS_BANK0_GPIO5_SCHMITT_MSB _u(1) 444 #define PADS_BANK0_GPIO5_SCHMITT_LSB _u(1) 445 #define PADS_BANK0_GPIO5_SCHMITT_ACCESS "RW" 446 // ----------------------------------------------------------------------------- 447 // Field : PADS_BANK0_GPIO5_SLEWFAST 448 // Description : Slew rate control. 1 = Fast, 0 = Slow 449 #define PADS_BANK0_GPIO5_SLEWFAST_RESET _u(0x0) 450 #define PADS_BANK0_GPIO5_SLEWFAST_BITS _u(0x00000001) 451 #define PADS_BANK0_GPIO5_SLEWFAST_MSB _u(0) 452 #define PADS_BANK0_GPIO5_SLEWFAST_LSB _u(0) 453 #define PADS_BANK0_GPIO5_SLEWFAST_ACCESS "RW" 454 // ============================================================================= 455 // Register : PADS_BANK0_GPIO6 456 // Description : Pad control register 457 #define PADS_BANK0_GPIO6_OFFSET _u(0x0000001c) 458 #define PADS_BANK0_GPIO6_BITS _u(0x000000ff) 459 #define PADS_BANK0_GPIO6_RESET _u(0x00000056) 460 // ----------------------------------------------------------------------------- 461 // Field : PADS_BANK0_GPIO6_OD 462 // Description : Output disable. Has priority over output enable from 463 // peripherals 464 #define PADS_BANK0_GPIO6_OD_RESET _u(0x0) 465 #define PADS_BANK0_GPIO6_OD_BITS _u(0x00000080) 466 #define PADS_BANK0_GPIO6_OD_MSB _u(7) 467 #define PADS_BANK0_GPIO6_OD_LSB _u(7) 468 #define PADS_BANK0_GPIO6_OD_ACCESS "RW" 469 // ----------------------------------------------------------------------------- 470 // Field : PADS_BANK0_GPIO6_IE 471 // Description : Input enable 472 #define PADS_BANK0_GPIO6_IE_RESET _u(0x1) 473 #define PADS_BANK0_GPIO6_IE_BITS _u(0x00000040) 474 #define PADS_BANK0_GPIO6_IE_MSB _u(6) 475 #define PADS_BANK0_GPIO6_IE_LSB _u(6) 476 #define PADS_BANK0_GPIO6_IE_ACCESS "RW" 477 // ----------------------------------------------------------------------------- 478 // Field : PADS_BANK0_GPIO6_DRIVE 479 // Description : Drive strength. 480 // 0x0 -> 2mA 481 // 0x1 -> 4mA 482 // 0x2 -> 8mA 483 // 0x3 -> 12mA 484 #define PADS_BANK0_GPIO6_DRIVE_RESET _u(0x1) 485 #define PADS_BANK0_GPIO6_DRIVE_BITS _u(0x00000030) 486 #define PADS_BANK0_GPIO6_DRIVE_MSB _u(5) 487 #define PADS_BANK0_GPIO6_DRIVE_LSB _u(4) 488 #define PADS_BANK0_GPIO6_DRIVE_ACCESS "RW" 489 #define PADS_BANK0_GPIO6_DRIVE_VALUE_2MA _u(0x0) 490 #define PADS_BANK0_GPIO6_DRIVE_VALUE_4MA _u(0x1) 491 #define PADS_BANK0_GPIO6_DRIVE_VALUE_8MA _u(0x2) 492 #define PADS_BANK0_GPIO6_DRIVE_VALUE_12MA _u(0x3) 493 // ----------------------------------------------------------------------------- 494 // Field : PADS_BANK0_GPIO6_PUE 495 // Description : Pull up enable 496 #define PADS_BANK0_GPIO6_PUE_RESET _u(0x0) 497 #define PADS_BANK0_GPIO6_PUE_BITS _u(0x00000008) 498 #define PADS_BANK0_GPIO6_PUE_MSB _u(3) 499 #define PADS_BANK0_GPIO6_PUE_LSB _u(3) 500 #define PADS_BANK0_GPIO6_PUE_ACCESS "RW" 501 // ----------------------------------------------------------------------------- 502 // Field : PADS_BANK0_GPIO6_PDE 503 // Description : Pull down enable 504 #define PADS_BANK0_GPIO6_PDE_RESET _u(0x1) 505 #define PADS_BANK0_GPIO6_PDE_BITS _u(0x00000004) 506 #define PADS_BANK0_GPIO6_PDE_MSB _u(2) 507 #define PADS_BANK0_GPIO6_PDE_LSB _u(2) 508 #define PADS_BANK0_GPIO6_PDE_ACCESS "RW" 509 // ----------------------------------------------------------------------------- 510 // Field : PADS_BANK0_GPIO6_SCHMITT 511 // Description : Enable schmitt trigger 512 #define PADS_BANK0_GPIO6_SCHMITT_RESET _u(0x1) 513 #define PADS_BANK0_GPIO6_SCHMITT_BITS _u(0x00000002) 514 #define PADS_BANK0_GPIO6_SCHMITT_MSB _u(1) 515 #define PADS_BANK0_GPIO6_SCHMITT_LSB _u(1) 516 #define PADS_BANK0_GPIO6_SCHMITT_ACCESS "RW" 517 // ----------------------------------------------------------------------------- 518 // Field : PADS_BANK0_GPIO6_SLEWFAST 519 // Description : Slew rate control. 1 = Fast, 0 = Slow 520 #define PADS_BANK0_GPIO6_SLEWFAST_RESET _u(0x0) 521 #define PADS_BANK0_GPIO6_SLEWFAST_BITS _u(0x00000001) 522 #define PADS_BANK0_GPIO6_SLEWFAST_MSB _u(0) 523 #define PADS_BANK0_GPIO6_SLEWFAST_LSB _u(0) 524 #define PADS_BANK0_GPIO6_SLEWFAST_ACCESS "RW" 525 // ============================================================================= 526 // Register : PADS_BANK0_GPIO7 527 // Description : Pad control register 528 #define PADS_BANK0_GPIO7_OFFSET _u(0x00000020) 529 #define PADS_BANK0_GPIO7_BITS _u(0x000000ff) 530 #define PADS_BANK0_GPIO7_RESET _u(0x00000056) 531 // ----------------------------------------------------------------------------- 532 // Field : PADS_BANK0_GPIO7_OD 533 // Description : Output disable. Has priority over output enable from 534 // peripherals 535 #define PADS_BANK0_GPIO7_OD_RESET _u(0x0) 536 #define PADS_BANK0_GPIO7_OD_BITS _u(0x00000080) 537 #define PADS_BANK0_GPIO7_OD_MSB _u(7) 538 #define PADS_BANK0_GPIO7_OD_LSB _u(7) 539 #define PADS_BANK0_GPIO7_OD_ACCESS "RW" 540 // ----------------------------------------------------------------------------- 541 // Field : PADS_BANK0_GPIO7_IE 542 // Description : Input enable 543 #define PADS_BANK0_GPIO7_IE_RESET _u(0x1) 544 #define PADS_BANK0_GPIO7_IE_BITS _u(0x00000040) 545 #define PADS_BANK0_GPIO7_IE_MSB _u(6) 546 #define PADS_BANK0_GPIO7_IE_LSB _u(6) 547 #define PADS_BANK0_GPIO7_IE_ACCESS "RW" 548 // ----------------------------------------------------------------------------- 549 // Field : PADS_BANK0_GPIO7_DRIVE 550 // Description : Drive strength. 551 // 0x0 -> 2mA 552 // 0x1 -> 4mA 553 // 0x2 -> 8mA 554 // 0x3 -> 12mA 555 #define PADS_BANK0_GPIO7_DRIVE_RESET _u(0x1) 556 #define PADS_BANK0_GPIO7_DRIVE_BITS _u(0x00000030) 557 #define PADS_BANK0_GPIO7_DRIVE_MSB _u(5) 558 #define PADS_BANK0_GPIO7_DRIVE_LSB _u(4) 559 #define PADS_BANK0_GPIO7_DRIVE_ACCESS "RW" 560 #define PADS_BANK0_GPIO7_DRIVE_VALUE_2MA _u(0x0) 561 #define PADS_BANK0_GPIO7_DRIVE_VALUE_4MA _u(0x1) 562 #define PADS_BANK0_GPIO7_DRIVE_VALUE_8MA _u(0x2) 563 #define PADS_BANK0_GPIO7_DRIVE_VALUE_12MA _u(0x3) 564 // ----------------------------------------------------------------------------- 565 // Field : PADS_BANK0_GPIO7_PUE 566 // Description : Pull up enable 567 #define PADS_BANK0_GPIO7_PUE_RESET _u(0x0) 568 #define PADS_BANK0_GPIO7_PUE_BITS _u(0x00000008) 569 #define PADS_BANK0_GPIO7_PUE_MSB _u(3) 570 #define PADS_BANK0_GPIO7_PUE_LSB _u(3) 571 #define PADS_BANK0_GPIO7_PUE_ACCESS "RW" 572 // ----------------------------------------------------------------------------- 573 // Field : PADS_BANK0_GPIO7_PDE 574 // Description : Pull down enable 575 #define PADS_BANK0_GPIO7_PDE_RESET _u(0x1) 576 #define PADS_BANK0_GPIO7_PDE_BITS _u(0x00000004) 577 #define PADS_BANK0_GPIO7_PDE_MSB _u(2) 578 #define PADS_BANK0_GPIO7_PDE_LSB _u(2) 579 #define PADS_BANK0_GPIO7_PDE_ACCESS "RW" 580 // ----------------------------------------------------------------------------- 581 // Field : PADS_BANK0_GPIO7_SCHMITT 582 // Description : Enable schmitt trigger 583 #define PADS_BANK0_GPIO7_SCHMITT_RESET _u(0x1) 584 #define PADS_BANK0_GPIO7_SCHMITT_BITS _u(0x00000002) 585 #define PADS_BANK0_GPIO7_SCHMITT_MSB _u(1) 586 #define PADS_BANK0_GPIO7_SCHMITT_LSB _u(1) 587 #define PADS_BANK0_GPIO7_SCHMITT_ACCESS "RW" 588 // ----------------------------------------------------------------------------- 589 // Field : PADS_BANK0_GPIO7_SLEWFAST 590 // Description : Slew rate control. 1 = Fast, 0 = Slow 591 #define PADS_BANK0_GPIO7_SLEWFAST_RESET _u(0x0) 592 #define PADS_BANK0_GPIO7_SLEWFAST_BITS _u(0x00000001) 593 #define PADS_BANK0_GPIO7_SLEWFAST_MSB _u(0) 594 #define PADS_BANK0_GPIO7_SLEWFAST_LSB _u(0) 595 #define PADS_BANK0_GPIO7_SLEWFAST_ACCESS "RW" 596 // ============================================================================= 597 // Register : PADS_BANK0_GPIO8 598 // Description : Pad control register 599 #define PADS_BANK0_GPIO8_OFFSET _u(0x00000024) 600 #define PADS_BANK0_GPIO8_BITS _u(0x000000ff) 601 #define PADS_BANK0_GPIO8_RESET _u(0x00000056) 602 // ----------------------------------------------------------------------------- 603 // Field : PADS_BANK0_GPIO8_OD 604 // Description : Output disable. Has priority over output enable from 605 // peripherals 606 #define PADS_BANK0_GPIO8_OD_RESET _u(0x0) 607 #define PADS_BANK0_GPIO8_OD_BITS _u(0x00000080) 608 #define PADS_BANK0_GPIO8_OD_MSB _u(7) 609 #define PADS_BANK0_GPIO8_OD_LSB _u(7) 610 #define PADS_BANK0_GPIO8_OD_ACCESS "RW" 611 // ----------------------------------------------------------------------------- 612 // Field : PADS_BANK0_GPIO8_IE 613 // Description : Input enable 614 #define PADS_BANK0_GPIO8_IE_RESET _u(0x1) 615 #define PADS_BANK0_GPIO8_IE_BITS _u(0x00000040) 616 #define PADS_BANK0_GPIO8_IE_MSB _u(6) 617 #define PADS_BANK0_GPIO8_IE_LSB _u(6) 618 #define PADS_BANK0_GPIO8_IE_ACCESS "RW" 619 // ----------------------------------------------------------------------------- 620 // Field : PADS_BANK0_GPIO8_DRIVE 621 // Description : Drive strength. 622 // 0x0 -> 2mA 623 // 0x1 -> 4mA 624 // 0x2 -> 8mA 625 // 0x3 -> 12mA 626 #define PADS_BANK0_GPIO8_DRIVE_RESET _u(0x1) 627 #define PADS_BANK0_GPIO8_DRIVE_BITS _u(0x00000030) 628 #define PADS_BANK0_GPIO8_DRIVE_MSB _u(5) 629 #define PADS_BANK0_GPIO8_DRIVE_LSB _u(4) 630 #define PADS_BANK0_GPIO8_DRIVE_ACCESS "RW" 631 #define PADS_BANK0_GPIO8_DRIVE_VALUE_2MA _u(0x0) 632 #define PADS_BANK0_GPIO8_DRIVE_VALUE_4MA _u(0x1) 633 #define PADS_BANK0_GPIO8_DRIVE_VALUE_8MA _u(0x2) 634 #define PADS_BANK0_GPIO8_DRIVE_VALUE_12MA _u(0x3) 635 // ----------------------------------------------------------------------------- 636 // Field : PADS_BANK0_GPIO8_PUE 637 // Description : Pull up enable 638 #define PADS_BANK0_GPIO8_PUE_RESET _u(0x0) 639 #define PADS_BANK0_GPIO8_PUE_BITS _u(0x00000008) 640 #define PADS_BANK0_GPIO8_PUE_MSB _u(3) 641 #define PADS_BANK0_GPIO8_PUE_LSB _u(3) 642 #define PADS_BANK0_GPIO8_PUE_ACCESS "RW" 643 // ----------------------------------------------------------------------------- 644 // Field : PADS_BANK0_GPIO8_PDE 645 // Description : Pull down enable 646 #define PADS_BANK0_GPIO8_PDE_RESET _u(0x1) 647 #define PADS_BANK0_GPIO8_PDE_BITS _u(0x00000004) 648 #define PADS_BANK0_GPIO8_PDE_MSB _u(2) 649 #define PADS_BANK0_GPIO8_PDE_LSB _u(2) 650 #define PADS_BANK0_GPIO8_PDE_ACCESS "RW" 651 // ----------------------------------------------------------------------------- 652 // Field : PADS_BANK0_GPIO8_SCHMITT 653 // Description : Enable schmitt trigger 654 #define PADS_BANK0_GPIO8_SCHMITT_RESET _u(0x1) 655 #define PADS_BANK0_GPIO8_SCHMITT_BITS _u(0x00000002) 656 #define PADS_BANK0_GPIO8_SCHMITT_MSB _u(1) 657 #define PADS_BANK0_GPIO8_SCHMITT_LSB _u(1) 658 #define PADS_BANK0_GPIO8_SCHMITT_ACCESS "RW" 659 // ----------------------------------------------------------------------------- 660 // Field : PADS_BANK0_GPIO8_SLEWFAST 661 // Description : Slew rate control. 1 = Fast, 0 = Slow 662 #define PADS_BANK0_GPIO8_SLEWFAST_RESET _u(0x0) 663 #define PADS_BANK0_GPIO8_SLEWFAST_BITS _u(0x00000001) 664 #define PADS_BANK0_GPIO8_SLEWFAST_MSB _u(0) 665 #define PADS_BANK0_GPIO8_SLEWFAST_LSB _u(0) 666 #define PADS_BANK0_GPIO8_SLEWFAST_ACCESS "RW" 667 // ============================================================================= 668 // Register : PADS_BANK0_GPIO9 669 // Description : Pad control register 670 #define PADS_BANK0_GPIO9_OFFSET _u(0x00000028) 671 #define PADS_BANK0_GPIO9_BITS _u(0x000000ff) 672 #define PADS_BANK0_GPIO9_RESET _u(0x00000056) 673 // ----------------------------------------------------------------------------- 674 // Field : PADS_BANK0_GPIO9_OD 675 // Description : Output disable. Has priority over output enable from 676 // peripherals 677 #define PADS_BANK0_GPIO9_OD_RESET _u(0x0) 678 #define PADS_BANK0_GPIO9_OD_BITS _u(0x00000080) 679 #define PADS_BANK0_GPIO9_OD_MSB _u(7) 680 #define PADS_BANK0_GPIO9_OD_LSB _u(7) 681 #define PADS_BANK0_GPIO9_OD_ACCESS "RW" 682 // ----------------------------------------------------------------------------- 683 // Field : PADS_BANK0_GPIO9_IE 684 // Description : Input enable 685 #define PADS_BANK0_GPIO9_IE_RESET _u(0x1) 686 #define PADS_BANK0_GPIO9_IE_BITS _u(0x00000040) 687 #define PADS_BANK0_GPIO9_IE_MSB _u(6) 688 #define PADS_BANK0_GPIO9_IE_LSB _u(6) 689 #define PADS_BANK0_GPIO9_IE_ACCESS "RW" 690 // ----------------------------------------------------------------------------- 691 // Field : PADS_BANK0_GPIO9_DRIVE 692 // Description : Drive strength. 693 // 0x0 -> 2mA 694 // 0x1 -> 4mA 695 // 0x2 -> 8mA 696 // 0x3 -> 12mA 697 #define PADS_BANK0_GPIO9_DRIVE_RESET _u(0x1) 698 #define PADS_BANK0_GPIO9_DRIVE_BITS _u(0x00000030) 699 #define PADS_BANK0_GPIO9_DRIVE_MSB _u(5) 700 #define PADS_BANK0_GPIO9_DRIVE_LSB _u(4) 701 #define PADS_BANK0_GPIO9_DRIVE_ACCESS "RW" 702 #define PADS_BANK0_GPIO9_DRIVE_VALUE_2MA _u(0x0) 703 #define PADS_BANK0_GPIO9_DRIVE_VALUE_4MA _u(0x1) 704 #define PADS_BANK0_GPIO9_DRIVE_VALUE_8MA _u(0x2) 705 #define PADS_BANK0_GPIO9_DRIVE_VALUE_12MA _u(0x3) 706 // ----------------------------------------------------------------------------- 707 // Field : PADS_BANK0_GPIO9_PUE 708 // Description : Pull up enable 709 #define PADS_BANK0_GPIO9_PUE_RESET _u(0x0) 710 #define PADS_BANK0_GPIO9_PUE_BITS _u(0x00000008) 711 #define PADS_BANK0_GPIO9_PUE_MSB _u(3) 712 #define PADS_BANK0_GPIO9_PUE_LSB _u(3) 713 #define PADS_BANK0_GPIO9_PUE_ACCESS "RW" 714 // ----------------------------------------------------------------------------- 715 // Field : PADS_BANK0_GPIO9_PDE 716 // Description : Pull down enable 717 #define PADS_BANK0_GPIO9_PDE_RESET _u(0x1) 718 #define PADS_BANK0_GPIO9_PDE_BITS _u(0x00000004) 719 #define PADS_BANK0_GPIO9_PDE_MSB _u(2) 720 #define PADS_BANK0_GPIO9_PDE_LSB _u(2) 721 #define PADS_BANK0_GPIO9_PDE_ACCESS "RW" 722 // ----------------------------------------------------------------------------- 723 // Field : PADS_BANK0_GPIO9_SCHMITT 724 // Description : Enable schmitt trigger 725 #define PADS_BANK0_GPIO9_SCHMITT_RESET _u(0x1) 726 #define PADS_BANK0_GPIO9_SCHMITT_BITS _u(0x00000002) 727 #define PADS_BANK0_GPIO9_SCHMITT_MSB _u(1) 728 #define PADS_BANK0_GPIO9_SCHMITT_LSB _u(1) 729 #define PADS_BANK0_GPIO9_SCHMITT_ACCESS "RW" 730 // ----------------------------------------------------------------------------- 731 // Field : PADS_BANK0_GPIO9_SLEWFAST 732 // Description : Slew rate control. 1 = Fast, 0 = Slow 733 #define PADS_BANK0_GPIO9_SLEWFAST_RESET _u(0x0) 734 #define PADS_BANK0_GPIO9_SLEWFAST_BITS _u(0x00000001) 735 #define PADS_BANK0_GPIO9_SLEWFAST_MSB _u(0) 736 #define PADS_BANK0_GPIO9_SLEWFAST_LSB _u(0) 737 #define PADS_BANK0_GPIO9_SLEWFAST_ACCESS "RW" 738 // ============================================================================= 739 // Register : PADS_BANK0_GPIO10 740 // Description : Pad control register 741 #define PADS_BANK0_GPIO10_OFFSET _u(0x0000002c) 742 #define PADS_BANK0_GPIO10_BITS _u(0x000000ff) 743 #define PADS_BANK0_GPIO10_RESET _u(0x00000056) 744 // ----------------------------------------------------------------------------- 745 // Field : PADS_BANK0_GPIO10_OD 746 // Description : Output disable. Has priority over output enable from 747 // peripherals 748 #define PADS_BANK0_GPIO10_OD_RESET _u(0x0) 749 #define PADS_BANK0_GPIO10_OD_BITS _u(0x00000080) 750 #define PADS_BANK0_GPIO10_OD_MSB _u(7) 751 #define PADS_BANK0_GPIO10_OD_LSB _u(7) 752 #define PADS_BANK0_GPIO10_OD_ACCESS "RW" 753 // ----------------------------------------------------------------------------- 754 // Field : PADS_BANK0_GPIO10_IE 755 // Description : Input enable 756 #define PADS_BANK0_GPIO10_IE_RESET _u(0x1) 757 #define PADS_BANK0_GPIO10_IE_BITS _u(0x00000040) 758 #define PADS_BANK0_GPIO10_IE_MSB _u(6) 759 #define PADS_BANK0_GPIO10_IE_LSB _u(6) 760 #define PADS_BANK0_GPIO10_IE_ACCESS "RW" 761 // ----------------------------------------------------------------------------- 762 // Field : PADS_BANK0_GPIO10_DRIVE 763 // Description : Drive strength. 764 // 0x0 -> 2mA 765 // 0x1 -> 4mA 766 // 0x2 -> 8mA 767 // 0x3 -> 12mA 768 #define PADS_BANK0_GPIO10_DRIVE_RESET _u(0x1) 769 #define PADS_BANK0_GPIO10_DRIVE_BITS _u(0x00000030) 770 #define PADS_BANK0_GPIO10_DRIVE_MSB _u(5) 771 #define PADS_BANK0_GPIO10_DRIVE_LSB _u(4) 772 #define PADS_BANK0_GPIO10_DRIVE_ACCESS "RW" 773 #define PADS_BANK0_GPIO10_DRIVE_VALUE_2MA _u(0x0) 774 #define PADS_BANK0_GPIO10_DRIVE_VALUE_4MA _u(0x1) 775 #define PADS_BANK0_GPIO10_DRIVE_VALUE_8MA _u(0x2) 776 #define PADS_BANK0_GPIO10_DRIVE_VALUE_12MA _u(0x3) 777 // ----------------------------------------------------------------------------- 778 // Field : PADS_BANK0_GPIO10_PUE 779 // Description : Pull up enable 780 #define PADS_BANK0_GPIO10_PUE_RESET _u(0x0) 781 #define PADS_BANK0_GPIO10_PUE_BITS _u(0x00000008) 782 #define PADS_BANK0_GPIO10_PUE_MSB _u(3) 783 #define PADS_BANK0_GPIO10_PUE_LSB _u(3) 784 #define PADS_BANK0_GPIO10_PUE_ACCESS "RW" 785 // ----------------------------------------------------------------------------- 786 // Field : PADS_BANK0_GPIO10_PDE 787 // Description : Pull down enable 788 #define PADS_BANK0_GPIO10_PDE_RESET _u(0x1) 789 #define PADS_BANK0_GPIO10_PDE_BITS _u(0x00000004) 790 #define PADS_BANK0_GPIO10_PDE_MSB _u(2) 791 #define PADS_BANK0_GPIO10_PDE_LSB _u(2) 792 #define PADS_BANK0_GPIO10_PDE_ACCESS "RW" 793 // ----------------------------------------------------------------------------- 794 // Field : PADS_BANK0_GPIO10_SCHMITT 795 // Description : Enable schmitt trigger 796 #define PADS_BANK0_GPIO10_SCHMITT_RESET _u(0x1) 797 #define PADS_BANK0_GPIO10_SCHMITT_BITS _u(0x00000002) 798 #define PADS_BANK0_GPIO10_SCHMITT_MSB _u(1) 799 #define PADS_BANK0_GPIO10_SCHMITT_LSB _u(1) 800 #define PADS_BANK0_GPIO10_SCHMITT_ACCESS "RW" 801 // ----------------------------------------------------------------------------- 802 // Field : PADS_BANK0_GPIO10_SLEWFAST 803 // Description : Slew rate control. 1 = Fast, 0 = Slow 804 #define PADS_BANK0_GPIO10_SLEWFAST_RESET _u(0x0) 805 #define PADS_BANK0_GPIO10_SLEWFAST_BITS _u(0x00000001) 806 #define PADS_BANK0_GPIO10_SLEWFAST_MSB _u(0) 807 #define PADS_BANK0_GPIO10_SLEWFAST_LSB _u(0) 808 #define PADS_BANK0_GPIO10_SLEWFAST_ACCESS "RW" 809 // ============================================================================= 810 // Register : PADS_BANK0_GPIO11 811 // Description : Pad control register 812 #define PADS_BANK0_GPIO11_OFFSET _u(0x00000030) 813 #define PADS_BANK0_GPIO11_BITS _u(0x000000ff) 814 #define PADS_BANK0_GPIO11_RESET _u(0x00000056) 815 // ----------------------------------------------------------------------------- 816 // Field : PADS_BANK0_GPIO11_OD 817 // Description : Output disable. Has priority over output enable from 818 // peripherals 819 #define PADS_BANK0_GPIO11_OD_RESET _u(0x0) 820 #define PADS_BANK0_GPIO11_OD_BITS _u(0x00000080) 821 #define PADS_BANK0_GPIO11_OD_MSB _u(7) 822 #define PADS_BANK0_GPIO11_OD_LSB _u(7) 823 #define PADS_BANK0_GPIO11_OD_ACCESS "RW" 824 // ----------------------------------------------------------------------------- 825 // Field : PADS_BANK0_GPIO11_IE 826 // Description : Input enable 827 #define PADS_BANK0_GPIO11_IE_RESET _u(0x1) 828 #define PADS_BANK0_GPIO11_IE_BITS _u(0x00000040) 829 #define PADS_BANK0_GPIO11_IE_MSB _u(6) 830 #define PADS_BANK0_GPIO11_IE_LSB _u(6) 831 #define PADS_BANK0_GPIO11_IE_ACCESS "RW" 832 // ----------------------------------------------------------------------------- 833 // Field : PADS_BANK0_GPIO11_DRIVE 834 // Description : Drive strength. 835 // 0x0 -> 2mA 836 // 0x1 -> 4mA 837 // 0x2 -> 8mA 838 // 0x3 -> 12mA 839 #define PADS_BANK0_GPIO11_DRIVE_RESET _u(0x1) 840 #define PADS_BANK0_GPIO11_DRIVE_BITS _u(0x00000030) 841 #define PADS_BANK0_GPIO11_DRIVE_MSB _u(5) 842 #define PADS_BANK0_GPIO11_DRIVE_LSB _u(4) 843 #define PADS_BANK0_GPIO11_DRIVE_ACCESS "RW" 844 #define PADS_BANK0_GPIO11_DRIVE_VALUE_2MA _u(0x0) 845 #define PADS_BANK0_GPIO11_DRIVE_VALUE_4MA _u(0x1) 846 #define PADS_BANK0_GPIO11_DRIVE_VALUE_8MA _u(0x2) 847 #define PADS_BANK0_GPIO11_DRIVE_VALUE_12MA _u(0x3) 848 // ----------------------------------------------------------------------------- 849 // Field : PADS_BANK0_GPIO11_PUE 850 // Description : Pull up enable 851 #define PADS_BANK0_GPIO11_PUE_RESET _u(0x0) 852 #define PADS_BANK0_GPIO11_PUE_BITS _u(0x00000008) 853 #define PADS_BANK0_GPIO11_PUE_MSB _u(3) 854 #define PADS_BANK0_GPIO11_PUE_LSB _u(3) 855 #define PADS_BANK0_GPIO11_PUE_ACCESS "RW" 856 // ----------------------------------------------------------------------------- 857 // Field : PADS_BANK0_GPIO11_PDE 858 // Description : Pull down enable 859 #define PADS_BANK0_GPIO11_PDE_RESET _u(0x1) 860 #define PADS_BANK0_GPIO11_PDE_BITS _u(0x00000004) 861 #define PADS_BANK0_GPIO11_PDE_MSB _u(2) 862 #define PADS_BANK0_GPIO11_PDE_LSB _u(2) 863 #define PADS_BANK0_GPIO11_PDE_ACCESS "RW" 864 // ----------------------------------------------------------------------------- 865 // Field : PADS_BANK0_GPIO11_SCHMITT 866 // Description : Enable schmitt trigger 867 #define PADS_BANK0_GPIO11_SCHMITT_RESET _u(0x1) 868 #define PADS_BANK0_GPIO11_SCHMITT_BITS _u(0x00000002) 869 #define PADS_BANK0_GPIO11_SCHMITT_MSB _u(1) 870 #define PADS_BANK0_GPIO11_SCHMITT_LSB _u(1) 871 #define PADS_BANK0_GPIO11_SCHMITT_ACCESS "RW" 872 // ----------------------------------------------------------------------------- 873 // Field : PADS_BANK0_GPIO11_SLEWFAST 874 // Description : Slew rate control. 1 = Fast, 0 = Slow 875 #define PADS_BANK0_GPIO11_SLEWFAST_RESET _u(0x0) 876 #define PADS_BANK0_GPIO11_SLEWFAST_BITS _u(0x00000001) 877 #define PADS_BANK0_GPIO11_SLEWFAST_MSB _u(0) 878 #define PADS_BANK0_GPIO11_SLEWFAST_LSB _u(0) 879 #define PADS_BANK0_GPIO11_SLEWFAST_ACCESS "RW" 880 // ============================================================================= 881 // Register : PADS_BANK0_GPIO12 882 // Description : Pad control register 883 #define PADS_BANK0_GPIO12_OFFSET _u(0x00000034) 884 #define PADS_BANK0_GPIO12_BITS _u(0x000000ff) 885 #define PADS_BANK0_GPIO12_RESET _u(0x00000056) 886 // ----------------------------------------------------------------------------- 887 // Field : PADS_BANK0_GPIO12_OD 888 // Description : Output disable. Has priority over output enable from 889 // peripherals 890 #define PADS_BANK0_GPIO12_OD_RESET _u(0x0) 891 #define PADS_BANK0_GPIO12_OD_BITS _u(0x00000080) 892 #define PADS_BANK0_GPIO12_OD_MSB _u(7) 893 #define PADS_BANK0_GPIO12_OD_LSB _u(7) 894 #define PADS_BANK0_GPIO12_OD_ACCESS "RW" 895 // ----------------------------------------------------------------------------- 896 // Field : PADS_BANK0_GPIO12_IE 897 // Description : Input enable 898 #define PADS_BANK0_GPIO12_IE_RESET _u(0x1) 899 #define PADS_BANK0_GPIO12_IE_BITS _u(0x00000040) 900 #define PADS_BANK0_GPIO12_IE_MSB _u(6) 901 #define PADS_BANK0_GPIO12_IE_LSB _u(6) 902 #define PADS_BANK0_GPIO12_IE_ACCESS "RW" 903 // ----------------------------------------------------------------------------- 904 // Field : PADS_BANK0_GPIO12_DRIVE 905 // Description : Drive strength. 906 // 0x0 -> 2mA 907 // 0x1 -> 4mA 908 // 0x2 -> 8mA 909 // 0x3 -> 12mA 910 #define PADS_BANK0_GPIO12_DRIVE_RESET _u(0x1) 911 #define PADS_BANK0_GPIO12_DRIVE_BITS _u(0x00000030) 912 #define PADS_BANK0_GPIO12_DRIVE_MSB _u(5) 913 #define PADS_BANK0_GPIO12_DRIVE_LSB _u(4) 914 #define PADS_BANK0_GPIO12_DRIVE_ACCESS "RW" 915 #define PADS_BANK0_GPIO12_DRIVE_VALUE_2MA _u(0x0) 916 #define PADS_BANK0_GPIO12_DRIVE_VALUE_4MA _u(0x1) 917 #define PADS_BANK0_GPIO12_DRIVE_VALUE_8MA _u(0x2) 918 #define PADS_BANK0_GPIO12_DRIVE_VALUE_12MA _u(0x3) 919 // ----------------------------------------------------------------------------- 920 // Field : PADS_BANK0_GPIO12_PUE 921 // Description : Pull up enable 922 #define PADS_BANK0_GPIO12_PUE_RESET _u(0x0) 923 #define PADS_BANK0_GPIO12_PUE_BITS _u(0x00000008) 924 #define PADS_BANK0_GPIO12_PUE_MSB _u(3) 925 #define PADS_BANK0_GPIO12_PUE_LSB _u(3) 926 #define PADS_BANK0_GPIO12_PUE_ACCESS "RW" 927 // ----------------------------------------------------------------------------- 928 // Field : PADS_BANK0_GPIO12_PDE 929 // Description : Pull down enable 930 #define PADS_BANK0_GPIO12_PDE_RESET _u(0x1) 931 #define PADS_BANK0_GPIO12_PDE_BITS _u(0x00000004) 932 #define PADS_BANK0_GPIO12_PDE_MSB _u(2) 933 #define PADS_BANK0_GPIO12_PDE_LSB _u(2) 934 #define PADS_BANK0_GPIO12_PDE_ACCESS "RW" 935 // ----------------------------------------------------------------------------- 936 // Field : PADS_BANK0_GPIO12_SCHMITT 937 // Description : Enable schmitt trigger 938 #define PADS_BANK0_GPIO12_SCHMITT_RESET _u(0x1) 939 #define PADS_BANK0_GPIO12_SCHMITT_BITS _u(0x00000002) 940 #define PADS_BANK0_GPIO12_SCHMITT_MSB _u(1) 941 #define PADS_BANK0_GPIO12_SCHMITT_LSB _u(1) 942 #define PADS_BANK0_GPIO12_SCHMITT_ACCESS "RW" 943 // ----------------------------------------------------------------------------- 944 // Field : PADS_BANK0_GPIO12_SLEWFAST 945 // Description : Slew rate control. 1 = Fast, 0 = Slow 946 #define PADS_BANK0_GPIO12_SLEWFAST_RESET _u(0x0) 947 #define PADS_BANK0_GPIO12_SLEWFAST_BITS _u(0x00000001) 948 #define PADS_BANK0_GPIO12_SLEWFAST_MSB _u(0) 949 #define PADS_BANK0_GPIO12_SLEWFAST_LSB _u(0) 950 #define PADS_BANK0_GPIO12_SLEWFAST_ACCESS "RW" 951 // ============================================================================= 952 // Register : PADS_BANK0_GPIO13 953 // Description : Pad control register 954 #define PADS_BANK0_GPIO13_OFFSET _u(0x00000038) 955 #define PADS_BANK0_GPIO13_BITS _u(0x000000ff) 956 #define PADS_BANK0_GPIO13_RESET _u(0x00000056) 957 // ----------------------------------------------------------------------------- 958 // Field : PADS_BANK0_GPIO13_OD 959 // Description : Output disable. Has priority over output enable from 960 // peripherals 961 #define PADS_BANK0_GPIO13_OD_RESET _u(0x0) 962 #define PADS_BANK0_GPIO13_OD_BITS _u(0x00000080) 963 #define PADS_BANK0_GPIO13_OD_MSB _u(7) 964 #define PADS_BANK0_GPIO13_OD_LSB _u(7) 965 #define PADS_BANK0_GPIO13_OD_ACCESS "RW" 966 // ----------------------------------------------------------------------------- 967 // Field : PADS_BANK0_GPIO13_IE 968 // Description : Input enable 969 #define PADS_BANK0_GPIO13_IE_RESET _u(0x1) 970 #define PADS_BANK0_GPIO13_IE_BITS _u(0x00000040) 971 #define PADS_BANK0_GPIO13_IE_MSB _u(6) 972 #define PADS_BANK0_GPIO13_IE_LSB _u(6) 973 #define PADS_BANK0_GPIO13_IE_ACCESS "RW" 974 // ----------------------------------------------------------------------------- 975 // Field : PADS_BANK0_GPIO13_DRIVE 976 // Description : Drive strength. 977 // 0x0 -> 2mA 978 // 0x1 -> 4mA 979 // 0x2 -> 8mA 980 // 0x3 -> 12mA 981 #define PADS_BANK0_GPIO13_DRIVE_RESET _u(0x1) 982 #define PADS_BANK0_GPIO13_DRIVE_BITS _u(0x00000030) 983 #define PADS_BANK0_GPIO13_DRIVE_MSB _u(5) 984 #define PADS_BANK0_GPIO13_DRIVE_LSB _u(4) 985 #define PADS_BANK0_GPIO13_DRIVE_ACCESS "RW" 986 #define PADS_BANK0_GPIO13_DRIVE_VALUE_2MA _u(0x0) 987 #define PADS_BANK0_GPIO13_DRIVE_VALUE_4MA _u(0x1) 988 #define PADS_BANK0_GPIO13_DRIVE_VALUE_8MA _u(0x2) 989 #define PADS_BANK0_GPIO13_DRIVE_VALUE_12MA _u(0x3) 990 // ----------------------------------------------------------------------------- 991 // Field : PADS_BANK0_GPIO13_PUE 992 // Description : Pull up enable 993 #define PADS_BANK0_GPIO13_PUE_RESET _u(0x0) 994 #define PADS_BANK0_GPIO13_PUE_BITS _u(0x00000008) 995 #define PADS_BANK0_GPIO13_PUE_MSB _u(3) 996 #define PADS_BANK0_GPIO13_PUE_LSB _u(3) 997 #define PADS_BANK0_GPIO13_PUE_ACCESS "RW" 998 // ----------------------------------------------------------------------------- 999 // Field : PADS_BANK0_GPIO13_PDE 1000 // Description : Pull down enable 1001 #define PADS_BANK0_GPIO13_PDE_RESET _u(0x1) 1002 #define PADS_BANK0_GPIO13_PDE_BITS _u(0x00000004) 1003 #define PADS_BANK0_GPIO13_PDE_MSB _u(2) 1004 #define PADS_BANK0_GPIO13_PDE_LSB _u(2) 1005 #define PADS_BANK0_GPIO13_PDE_ACCESS "RW" 1006 // ----------------------------------------------------------------------------- 1007 // Field : PADS_BANK0_GPIO13_SCHMITT 1008 // Description : Enable schmitt trigger 1009 #define PADS_BANK0_GPIO13_SCHMITT_RESET _u(0x1) 1010 #define PADS_BANK0_GPIO13_SCHMITT_BITS _u(0x00000002) 1011 #define PADS_BANK0_GPIO13_SCHMITT_MSB _u(1) 1012 #define PADS_BANK0_GPIO13_SCHMITT_LSB _u(1) 1013 #define PADS_BANK0_GPIO13_SCHMITT_ACCESS "RW" 1014 // ----------------------------------------------------------------------------- 1015 // Field : PADS_BANK0_GPIO13_SLEWFAST 1016 // Description : Slew rate control. 1 = Fast, 0 = Slow 1017 #define PADS_BANK0_GPIO13_SLEWFAST_RESET _u(0x0) 1018 #define PADS_BANK0_GPIO13_SLEWFAST_BITS _u(0x00000001) 1019 #define PADS_BANK0_GPIO13_SLEWFAST_MSB _u(0) 1020 #define PADS_BANK0_GPIO13_SLEWFAST_LSB _u(0) 1021 #define PADS_BANK0_GPIO13_SLEWFAST_ACCESS "RW" 1022 // ============================================================================= 1023 // Register : PADS_BANK0_GPIO14 1024 // Description : Pad control register 1025 #define PADS_BANK0_GPIO14_OFFSET _u(0x0000003c) 1026 #define PADS_BANK0_GPIO14_BITS _u(0x000000ff) 1027 #define PADS_BANK0_GPIO14_RESET _u(0x00000056) 1028 // ----------------------------------------------------------------------------- 1029 // Field : PADS_BANK0_GPIO14_OD 1030 // Description : Output disable. Has priority over output enable from 1031 // peripherals 1032 #define PADS_BANK0_GPIO14_OD_RESET _u(0x0) 1033 #define PADS_BANK0_GPIO14_OD_BITS _u(0x00000080) 1034 #define PADS_BANK0_GPIO14_OD_MSB _u(7) 1035 #define PADS_BANK0_GPIO14_OD_LSB _u(7) 1036 #define PADS_BANK0_GPIO14_OD_ACCESS "RW" 1037 // ----------------------------------------------------------------------------- 1038 // Field : PADS_BANK0_GPIO14_IE 1039 // Description : Input enable 1040 #define PADS_BANK0_GPIO14_IE_RESET _u(0x1) 1041 #define PADS_BANK0_GPIO14_IE_BITS _u(0x00000040) 1042 #define PADS_BANK0_GPIO14_IE_MSB _u(6) 1043 #define PADS_BANK0_GPIO14_IE_LSB _u(6) 1044 #define PADS_BANK0_GPIO14_IE_ACCESS "RW" 1045 // ----------------------------------------------------------------------------- 1046 // Field : PADS_BANK0_GPIO14_DRIVE 1047 // Description : Drive strength. 1048 // 0x0 -> 2mA 1049 // 0x1 -> 4mA 1050 // 0x2 -> 8mA 1051 // 0x3 -> 12mA 1052 #define PADS_BANK0_GPIO14_DRIVE_RESET _u(0x1) 1053 #define PADS_BANK0_GPIO14_DRIVE_BITS _u(0x00000030) 1054 #define PADS_BANK0_GPIO14_DRIVE_MSB _u(5) 1055 #define PADS_BANK0_GPIO14_DRIVE_LSB _u(4) 1056 #define PADS_BANK0_GPIO14_DRIVE_ACCESS "RW" 1057 #define PADS_BANK0_GPIO14_DRIVE_VALUE_2MA _u(0x0) 1058 #define PADS_BANK0_GPIO14_DRIVE_VALUE_4MA _u(0x1) 1059 #define PADS_BANK0_GPIO14_DRIVE_VALUE_8MA _u(0x2) 1060 #define PADS_BANK0_GPIO14_DRIVE_VALUE_12MA _u(0x3) 1061 // ----------------------------------------------------------------------------- 1062 // Field : PADS_BANK0_GPIO14_PUE 1063 // Description : Pull up enable 1064 #define PADS_BANK0_GPIO14_PUE_RESET _u(0x0) 1065 #define PADS_BANK0_GPIO14_PUE_BITS _u(0x00000008) 1066 #define PADS_BANK0_GPIO14_PUE_MSB _u(3) 1067 #define PADS_BANK0_GPIO14_PUE_LSB _u(3) 1068 #define PADS_BANK0_GPIO14_PUE_ACCESS "RW" 1069 // ----------------------------------------------------------------------------- 1070 // Field : PADS_BANK0_GPIO14_PDE 1071 // Description : Pull down enable 1072 #define PADS_BANK0_GPIO14_PDE_RESET _u(0x1) 1073 #define PADS_BANK0_GPIO14_PDE_BITS _u(0x00000004) 1074 #define PADS_BANK0_GPIO14_PDE_MSB _u(2) 1075 #define PADS_BANK0_GPIO14_PDE_LSB _u(2) 1076 #define PADS_BANK0_GPIO14_PDE_ACCESS "RW" 1077 // ----------------------------------------------------------------------------- 1078 // Field : PADS_BANK0_GPIO14_SCHMITT 1079 // Description : Enable schmitt trigger 1080 #define PADS_BANK0_GPIO14_SCHMITT_RESET _u(0x1) 1081 #define PADS_BANK0_GPIO14_SCHMITT_BITS _u(0x00000002) 1082 #define PADS_BANK0_GPIO14_SCHMITT_MSB _u(1) 1083 #define PADS_BANK0_GPIO14_SCHMITT_LSB _u(1) 1084 #define PADS_BANK0_GPIO14_SCHMITT_ACCESS "RW" 1085 // ----------------------------------------------------------------------------- 1086 // Field : PADS_BANK0_GPIO14_SLEWFAST 1087 // Description : Slew rate control. 1 = Fast, 0 = Slow 1088 #define PADS_BANK0_GPIO14_SLEWFAST_RESET _u(0x0) 1089 #define PADS_BANK0_GPIO14_SLEWFAST_BITS _u(0x00000001) 1090 #define PADS_BANK0_GPIO14_SLEWFAST_MSB _u(0) 1091 #define PADS_BANK0_GPIO14_SLEWFAST_LSB _u(0) 1092 #define PADS_BANK0_GPIO14_SLEWFAST_ACCESS "RW" 1093 // ============================================================================= 1094 // Register : PADS_BANK0_GPIO15 1095 // Description : Pad control register 1096 #define PADS_BANK0_GPIO15_OFFSET _u(0x00000040) 1097 #define PADS_BANK0_GPIO15_BITS _u(0x000000ff) 1098 #define PADS_BANK0_GPIO15_RESET _u(0x00000056) 1099 // ----------------------------------------------------------------------------- 1100 // Field : PADS_BANK0_GPIO15_OD 1101 // Description : Output disable. Has priority over output enable from 1102 // peripherals 1103 #define PADS_BANK0_GPIO15_OD_RESET _u(0x0) 1104 #define PADS_BANK0_GPIO15_OD_BITS _u(0x00000080) 1105 #define PADS_BANK0_GPIO15_OD_MSB _u(7) 1106 #define PADS_BANK0_GPIO15_OD_LSB _u(7) 1107 #define PADS_BANK0_GPIO15_OD_ACCESS "RW" 1108 // ----------------------------------------------------------------------------- 1109 // Field : PADS_BANK0_GPIO15_IE 1110 // Description : Input enable 1111 #define PADS_BANK0_GPIO15_IE_RESET _u(0x1) 1112 #define PADS_BANK0_GPIO15_IE_BITS _u(0x00000040) 1113 #define PADS_BANK0_GPIO15_IE_MSB _u(6) 1114 #define PADS_BANK0_GPIO15_IE_LSB _u(6) 1115 #define PADS_BANK0_GPIO15_IE_ACCESS "RW" 1116 // ----------------------------------------------------------------------------- 1117 // Field : PADS_BANK0_GPIO15_DRIVE 1118 // Description : Drive strength. 1119 // 0x0 -> 2mA 1120 // 0x1 -> 4mA 1121 // 0x2 -> 8mA 1122 // 0x3 -> 12mA 1123 #define PADS_BANK0_GPIO15_DRIVE_RESET _u(0x1) 1124 #define PADS_BANK0_GPIO15_DRIVE_BITS _u(0x00000030) 1125 #define PADS_BANK0_GPIO15_DRIVE_MSB _u(5) 1126 #define PADS_BANK0_GPIO15_DRIVE_LSB _u(4) 1127 #define PADS_BANK0_GPIO15_DRIVE_ACCESS "RW" 1128 #define PADS_BANK0_GPIO15_DRIVE_VALUE_2MA _u(0x0) 1129 #define PADS_BANK0_GPIO15_DRIVE_VALUE_4MA _u(0x1) 1130 #define PADS_BANK0_GPIO15_DRIVE_VALUE_8MA _u(0x2) 1131 #define PADS_BANK0_GPIO15_DRIVE_VALUE_12MA _u(0x3) 1132 // ----------------------------------------------------------------------------- 1133 // Field : PADS_BANK0_GPIO15_PUE 1134 // Description : Pull up enable 1135 #define PADS_BANK0_GPIO15_PUE_RESET _u(0x0) 1136 #define PADS_BANK0_GPIO15_PUE_BITS _u(0x00000008) 1137 #define PADS_BANK0_GPIO15_PUE_MSB _u(3) 1138 #define PADS_BANK0_GPIO15_PUE_LSB _u(3) 1139 #define PADS_BANK0_GPIO15_PUE_ACCESS "RW" 1140 // ----------------------------------------------------------------------------- 1141 // Field : PADS_BANK0_GPIO15_PDE 1142 // Description : Pull down enable 1143 #define PADS_BANK0_GPIO15_PDE_RESET _u(0x1) 1144 #define PADS_BANK0_GPIO15_PDE_BITS _u(0x00000004) 1145 #define PADS_BANK0_GPIO15_PDE_MSB _u(2) 1146 #define PADS_BANK0_GPIO15_PDE_LSB _u(2) 1147 #define PADS_BANK0_GPIO15_PDE_ACCESS "RW" 1148 // ----------------------------------------------------------------------------- 1149 // Field : PADS_BANK0_GPIO15_SCHMITT 1150 // Description : Enable schmitt trigger 1151 #define PADS_BANK0_GPIO15_SCHMITT_RESET _u(0x1) 1152 #define PADS_BANK0_GPIO15_SCHMITT_BITS _u(0x00000002) 1153 #define PADS_BANK0_GPIO15_SCHMITT_MSB _u(1) 1154 #define PADS_BANK0_GPIO15_SCHMITT_LSB _u(1) 1155 #define PADS_BANK0_GPIO15_SCHMITT_ACCESS "RW" 1156 // ----------------------------------------------------------------------------- 1157 // Field : PADS_BANK0_GPIO15_SLEWFAST 1158 // Description : Slew rate control. 1 = Fast, 0 = Slow 1159 #define PADS_BANK0_GPIO15_SLEWFAST_RESET _u(0x0) 1160 #define PADS_BANK0_GPIO15_SLEWFAST_BITS _u(0x00000001) 1161 #define PADS_BANK0_GPIO15_SLEWFAST_MSB _u(0) 1162 #define PADS_BANK0_GPIO15_SLEWFAST_LSB _u(0) 1163 #define PADS_BANK0_GPIO15_SLEWFAST_ACCESS "RW" 1164 // ============================================================================= 1165 // Register : PADS_BANK0_GPIO16 1166 // Description : Pad control register 1167 #define PADS_BANK0_GPIO16_OFFSET _u(0x00000044) 1168 #define PADS_BANK0_GPIO16_BITS _u(0x000000ff) 1169 #define PADS_BANK0_GPIO16_RESET _u(0x00000056) 1170 // ----------------------------------------------------------------------------- 1171 // Field : PADS_BANK0_GPIO16_OD 1172 // Description : Output disable. Has priority over output enable from 1173 // peripherals 1174 #define PADS_BANK0_GPIO16_OD_RESET _u(0x0) 1175 #define PADS_BANK0_GPIO16_OD_BITS _u(0x00000080) 1176 #define PADS_BANK0_GPIO16_OD_MSB _u(7) 1177 #define PADS_BANK0_GPIO16_OD_LSB _u(7) 1178 #define PADS_BANK0_GPIO16_OD_ACCESS "RW" 1179 // ----------------------------------------------------------------------------- 1180 // Field : PADS_BANK0_GPIO16_IE 1181 // Description : Input enable 1182 #define PADS_BANK0_GPIO16_IE_RESET _u(0x1) 1183 #define PADS_BANK0_GPIO16_IE_BITS _u(0x00000040) 1184 #define PADS_BANK0_GPIO16_IE_MSB _u(6) 1185 #define PADS_BANK0_GPIO16_IE_LSB _u(6) 1186 #define PADS_BANK0_GPIO16_IE_ACCESS "RW" 1187 // ----------------------------------------------------------------------------- 1188 // Field : PADS_BANK0_GPIO16_DRIVE 1189 // Description : Drive strength. 1190 // 0x0 -> 2mA 1191 // 0x1 -> 4mA 1192 // 0x2 -> 8mA 1193 // 0x3 -> 12mA 1194 #define PADS_BANK0_GPIO16_DRIVE_RESET _u(0x1) 1195 #define PADS_BANK0_GPIO16_DRIVE_BITS _u(0x00000030) 1196 #define PADS_BANK0_GPIO16_DRIVE_MSB _u(5) 1197 #define PADS_BANK0_GPIO16_DRIVE_LSB _u(4) 1198 #define PADS_BANK0_GPIO16_DRIVE_ACCESS "RW" 1199 #define PADS_BANK0_GPIO16_DRIVE_VALUE_2MA _u(0x0) 1200 #define PADS_BANK0_GPIO16_DRIVE_VALUE_4MA _u(0x1) 1201 #define PADS_BANK0_GPIO16_DRIVE_VALUE_8MA _u(0x2) 1202 #define PADS_BANK0_GPIO16_DRIVE_VALUE_12MA _u(0x3) 1203 // ----------------------------------------------------------------------------- 1204 // Field : PADS_BANK0_GPIO16_PUE 1205 // Description : Pull up enable 1206 #define PADS_BANK0_GPIO16_PUE_RESET _u(0x0) 1207 #define PADS_BANK0_GPIO16_PUE_BITS _u(0x00000008) 1208 #define PADS_BANK0_GPIO16_PUE_MSB _u(3) 1209 #define PADS_BANK0_GPIO16_PUE_LSB _u(3) 1210 #define PADS_BANK0_GPIO16_PUE_ACCESS "RW" 1211 // ----------------------------------------------------------------------------- 1212 // Field : PADS_BANK0_GPIO16_PDE 1213 // Description : Pull down enable 1214 #define PADS_BANK0_GPIO16_PDE_RESET _u(0x1) 1215 #define PADS_BANK0_GPIO16_PDE_BITS _u(0x00000004) 1216 #define PADS_BANK0_GPIO16_PDE_MSB _u(2) 1217 #define PADS_BANK0_GPIO16_PDE_LSB _u(2) 1218 #define PADS_BANK0_GPIO16_PDE_ACCESS "RW" 1219 // ----------------------------------------------------------------------------- 1220 // Field : PADS_BANK0_GPIO16_SCHMITT 1221 // Description : Enable schmitt trigger 1222 #define PADS_BANK0_GPIO16_SCHMITT_RESET _u(0x1) 1223 #define PADS_BANK0_GPIO16_SCHMITT_BITS _u(0x00000002) 1224 #define PADS_BANK0_GPIO16_SCHMITT_MSB _u(1) 1225 #define PADS_BANK0_GPIO16_SCHMITT_LSB _u(1) 1226 #define PADS_BANK0_GPIO16_SCHMITT_ACCESS "RW" 1227 // ----------------------------------------------------------------------------- 1228 // Field : PADS_BANK0_GPIO16_SLEWFAST 1229 // Description : Slew rate control. 1 = Fast, 0 = Slow 1230 #define PADS_BANK0_GPIO16_SLEWFAST_RESET _u(0x0) 1231 #define PADS_BANK0_GPIO16_SLEWFAST_BITS _u(0x00000001) 1232 #define PADS_BANK0_GPIO16_SLEWFAST_MSB _u(0) 1233 #define PADS_BANK0_GPIO16_SLEWFAST_LSB _u(0) 1234 #define PADS_BANK0_GPIO16_SLEWFAST_ACCESS "RW" 1235 // ============================================================================= 1236 // Register : PADS_BANK0_GPIO17 1237 // Description : Pad control register 1238 #define PADS_BANK0_GPIO17_OFFSET _u(0x00000048) 1239 #define PADS_BANK0_GPIO17_BITS _u(0x000000ff) 1240 #define PADS_BANK0_GPIO17_RESET _u(0x00000056) 1241 // ----------------------------------------------------------------------------- 1242 // Field : PADS_BANK0_GPIO17_OD 1243 // Description : Output disable. Has priority over output enable from 1244 // peripherals 1245 #define PADS_BANK0_GPIO17_OD_RESET _u(0x0) 1246 #define PADS_BANK0_GPIO17_OD_BITS _u(0x00000080) 1247 #define PADS_BANK0_GPIO17_OD_MSB _u(7) 1248 #define PADS_BANK0_GPIO17_OD_LSB _u(7) 1249 #define PADS_BANK0_GPIO17_OD_ACCESS "RW" 1250 // ----------------------------------------------------------------------------- 1251 // Field : PADS_BANK0_GPIO17_IE 1252 // Description : Input enable 1253 #define PADS_BANK0_GPIO17_IE_RESET _u(0x1) 1254 #define PADS_BANK0_GPIO17_IE_BITS _u(0x00000040) 1255 #define PADS_BANK0_GPIO17_IE_MSB _u(6) 1256 #define PADS_BANK0_GPIO17_IE_LSB _u(6) 1257 #define PADS_BANK0_GPIO17_IE_ACCESS "RW" 1258 // ----------------------------------------------------------------------------- 1259 // Field : PADS_BANK0_GPIO17_DRIVE 1260 // Description : Drive strength. 1261 // 0x0 -> 2mA 1262 // 0x1 -> 4mA 1263 // 0x2 -> 8mA 1264 // 0x3 -> 12mA 1265 #define PADS_BANK0_GPIO17_DRIVE_RESET _u(0x1) 1266 #define PADS_BANK0_GPIO17_DRIVE_BITS _u(0x00000030) 1267 #define PADS_BANK0_GPIO17_DRIVE_MSB _u(5) 1268 #define PADS_BANK0_GPIO17_DRIVE_LSB _u(4) 1269 #define PADS_BANK0_GPIO17_DRIVE_ACCESS "RW" 1270 #define PADS_BANK0_GPIO17_DRIVE_VALUE_2MA _u(0x0) 1271 #define PADS_BANK0_GPIO17_DRIVE_VALUE_4MA _u(0x1) 1272 #define PADS_BANK0_GPIO17_DRIVE_VALUE_8MA _u(0x2) 1273 #define PADS_BANK0_GPIO17_DRIVE_VALUE_12MA _u(0x3) 1274 // ----------------------------------------------------------------------------- 1275 // Field : PADS_BANK0_GPIO17_PUE 1276 // Description : Pull up enable 1277 #define PADS_BANK0_GPIO17_PUE_RESET _u(0x0) 1278 #define PADS_BANK0_GPIO17_PUE_BITS _u(0x00000008) 1279 #define PADS_BANK0_GPIO17_PUE_MSB _u(3) 1280 #define PADS_BANK0_GPIO17_PUE_LSB _u(3) 1281 #define PADS_BANK0_GPIO17_PUE_ACCESS "RW" 1282 // ----------------------------------------------------------------------------- 1283 // Field : PADS_BANK0_GPIO17_PDE 1284 // Description : Pull down enable 1285 #define PADS_BANK0_GPIO17_PDE_RESET _u(0x1) 1286 #define PADS_BANK0_GPIO17_PDE_BITS _u(0x00000004) 1287 #define PADS_BANK0_GPIO17_PDE_MSB _u(2) 1288 #define PADS_BANK0_GPIO17_PDE_LSB _u(2) 1289 #define PADS_BANK0_GPIO17_PDE_ACCESS "RW" 1290 // ----------------------------------------------------------------------------- 1291 // Field : PADS_BANK0_GPIO17_SCHMITT 1292 // Description : Enable schmitt trigger 1293 #define PADS_BANK0_GPIO17_SCHMITT_RESET _u(0x1) 1294 #define PADS_BANK0_GPIO17_SCHMITT_BITS _u(0x00000002) 1295 #define PADS_BANK0_GPIO17_SCHMITT_MSB _u(1) 1296 #define PADS_BANK0_GPIO17_SCHMITT_LSB _u(1) 1297 #define PADS_BANK0_GPIO17_SCHMITT_ACCESS "RW" 1298 // ----------------------------------------------------------------------------- 1299 // Field : PADS_BANK0_GPIO17_SLEWFAST 1300 // Description : Slew rate control. 1 = Fast, 0 = Slow 1301 #define PADS_BANK0_GPIO17_SLEWFAST_RESET _u(0x0) 1302 #define PADS_BANK0_GPIO17_SLEWFAST_BITS _u(0x00000001) 1303 #define PADS_BANK0_GPIO17_SLEWFAST_MSB _u(0) 1304 #define PADS_BANK0_GPIO17_SLEWFAST_LSB _u(0) 1305 #define PADS_BANK0_GPIO17_SLEWFAST_ACCESS "RW" 1306 // ============================================================================= 1307 // Register : PADS_BANK0_GPIO18 1308 // Description : Pad control register 1309 #define PADS_BANK0_GPIO18_OFFSET _u(0x0000004c) 1310 #define PADS_BANK0_GPIO18_BITS _u(0x000000ff) 1311 #define PADS_BANK0_GPIO18_RESET _u(0x00000056) 1312 // ----------------------------------------------------------------------------- 1313 // Field : PADS_BANK0_GPIO18_OD 1314 // Description : Output disable. Has priority over output enable from 1315 // peripherals 1316 #define PADS_BANK0_GPIO18_OD_RESET _u(0x0) 1317 #define PADS_BANK0_GPIO18_OD_BITS _u(0x00000080) 1318 #define PADS_BANK0_GPIO18_OD_MSB _u(7) 1319 #define PADS_BANK0_GPIO18_OD_LSB _u(7) 1320 #define PADS_BANK0_GPIO18_OD_ACCESS "RW" 1321 // ----------------------------------------------------------------------------- 1322 // Field : PADS_BANK0_GPIO18_IE 1323 // Description : Input enable 1324 #define PADS_BANK0_GPIO18_IE_RESET _u(0x1) 1325 #define PADS_BANK0_GPIO18_IE_BITS _u(0x00000040) 1326 #define PADS_BANK0_GPIO18_IE_MSB _u(6) 1327 #define PADS_BANK0_GPIO18_IE_LSB _u(6) 1328 #define PADS_BANK0_GPIO18_IE_ACCESS "RW" 1329 // ----------------------------------------------------------------------------- 1330 // Field : PADS_BANK0_GPIO18_DRIVE 1331 // Description : Drive strength. 1332 // 0x0 -> 2mA 1333 // 0x1 -> 4mA 1334 // 0x2 -> 8mA 1335 // 0x3 -> 12mA 1336 #define PADS_BANK0_GPIO18_DRIVE_RESET _u(0x1) 1337 #define PADS_BANK0_GPIO18_DRIVE_BITS _u(0x00000030) 1338 #define PADS_BANK0_GPIO18_DRIVE_MSB _u(5) 1339 #define PADS_BANK0_GPIO18_DRIVE_LSB _u(4) 1340 #define PADS_BANK0_GPIO18_DRIVE_ACCESS "RW" 1341 #define PADS_BANK0_GPIO18_DRIVE_VALUE_2MA _u(0x0) 1342 #define PADS_BANK0_GPIO18_DRIVE_VALUE_4MA _u(0x1) 1343 #define PADS_BANK0_GPIO18_DRIVE_VALUE_8MA _u(0x2) 1344 #define PADS_BANK0_GPIO18_DRIVE_VALUE_12MA _u(0x3) 1345 // ----------------------------------------------------------------------------- 1346 // Field : PADS_BANK0_GPIO18_PUE 1347 // Description : Pull up enable 1348 #define PADS_BANK0_GPIO18_PUE_RESET _u(0x0) 1349 #define PADS_BANK0_GPIO18_PUE_BITS _u(0x00000008) 1350 #define PADS_BANK0_GPIO18_PUE_MSB _u(3) 1351 #define PADS_BANK0_GPIO18_PUE_LSB _u(3) 1352 #define PADS_BANK0_GPIO18_PUE_ACCESS "RW" 1353 // ----------------------------------------------------------------------------- 1354 // Field : PADS_BANK0_GPIO18_PDE 1355 // Description : Pull down enable 1356 #define PADS_BANK0_GPIO18_PDE_RESET _u(0x1) 1357 #define PADS_BANK0_GPIO18_PDE_BITS _u(0x00000004) 1358 #define PADS_BANK0_GPIO18_PDE_MSB _u(2) 1359 #define PADS_BANK0_GPIO18_PDE_LSB _u(2) 1360 #define PADS_BANK0_GPIO18_PDE_ACCESS "RW" 1361 // ----------------------------------------------------------------------------- 1362 // Field : PADS_BANK0_GPIO18_SCHMITT 1363 // Description : Enable schmitt trigger 1364 #define PADS_BANK0_GPIO18_SCHMITT_RESET _u(0x1) 1365 #define PADS_BANK0_GPIO18_SCHMITT_BITS _u(0x00000002) 1366 #define PADS_BANK0_GPIO18_SCHMITT_MSB _u(1) 1367 #define PADS_BANK0_GPIO18_SCHMITT_LSB _u(1) 1368 #define PADS_BANK0_GPIO18_SCHMITT_ACCESS "RW" 1369 // ----------------------------------------------------------------------------- 1370 // Field : PADS_BANK0_GPIO18_SLEWFAST 1371 // Description : Slew rate control. 1 = Fast, 0 = Slow 1372 #define PADS_BANK0_GPIO18_SLEWFAST_RESET _u(0x0) 1373 #define PADS_BANK0_GPIO18_SLEWFAST_BITS _u(0x00000001) 1374 #define PADS_BANK0_GPIO18_SLEWFAST_MSB _u(0) 1375 #define PADS_BANK0_GPIO18_SLEWFAST_LSB _u(0) 1376 #define PADS_BANK0_GPIO18_SLEWFAST_ACCESS "RW" 1377 // ============================================================================= 1378 // Register : PADS_BANK0_GPIO19 1379 // Description : Pad control register 1380 #define PADS_BANK0_GPIO19_OFFSET _u(0x00000050) 1381 #define PADS_BANK0_GPIO19_BITS _u(0x000000ff) 1382 #define PADS_BANK0_GPIO19_RESET _u(0x00000056) 1383 // ----------------------------------------------------------------------------- 1384 // Field : PADS_BANK0_GPIO19_OD 1385 // Description : Output disable. Has priority over output enable from 1386 // peripherals 1387 #define PADS_BANK0_GPIO19_OD_RESET _u(0x0) 1388 #define PADS_BANK0_GPIO19_OD_BITS _u(0x00000080) 1389 #define PADS_BANK0_GPIO19_OD_MSB _u(7) 1390 #define PADS_BANK0_GPIO19_OD_LSB _u(7) 1391 #define PADS_BANK0_GPIO19_OD_ACCESS "RW" 1392 // ----------------------------------------------------------------------------- 1393 // Field : PADS_BANK0_GPIO19_IE 1394 // Description : Input enable 1395 #define PADS_BANK0_GPIO19_IE_RESET _u(0x1) 1396 #define PADS_BANK0_GPIO19_IE_BITS _u(0x00000040) 1397 #define PADS_BANK0_GPIO19_IE_MSB _u(6) 1398 #define PADS_BANK0_GPIO19_IE_LSB _u(6) 1399 #define PADS_BANK0_GPIO19_IE_ACCESS "RW" 1400 // ----------------------------------------------------------------------------- 1401 // Field : PADS_BANK0_GPIO19_DRIVE 1402 // Description : Drive strength. 1403 // 0x0 -> 2mA 1404 // 0x1 -> 4mA 1405 // 0x2 -> 8mA 1406 // 0x3 -> 12mA 1407 #define PADS_BANK0_GPIO19_DRIVE_RESET _u(0x1) 1408 #define PADS_BANK0_GPIO19_DRIVE_BITS _u(0x00000030) 1409 #define PADS_BANK0_GPIO19_DRIVE_MSB _u(5) 1410 #define PADS_BANK0_GPIO19_DRIVE_LSB _u(4) 1411 #define PADS_BANK0_GPIO19_DRIVE_ACCESS "RW" 1412 #define PADS_BANK0_GPIO19_DRIVE_VALUE_2MA _u(0x0) 1413 #define PADS_BANK0_GPIO19_DRIVE_VALUE_4MA _u(0x1) 1414 #define PADS_BANK0_GPIO19_DRIVE_VALUE_8MA _u(0x2) 1415 #define PADS_BANK0_GPIO19_DRIVE_VALUE_12MA _u(0x3) 1416 // ----------------------------------------------------------------------------- 1417 // Field : PADS_BANK0_GPIO19_PUE 1418 // Description : Pull up enable 1419 #define PADS_BANK0_GPIO19_PUE_RESET _u(0x0) 1420 #define PADS_BANK0_GPIO19_PUE_BITS _u(0x00000008) 1421 #define PADS_BANK0_GPIO19_PUE_MSB _u(3) 1422 #define PADS_BANK0_GPIO19_PUE_LSB _u(3) 1423 #define PADS_BANK0_GPIO19_PUE_ACCESS "RW" 1424 // ----------------------------------------------------------------------------- 1425 // Field : PADS_BANK0_GPIO19_PDE 1426 // Description : Pull down enable 1427 #define PADS_BANK0_GPIO19_PDE_RESET _u(0x1) 1428 #define PADS_BANK0_GPIO19_PDE_BITS _u(0x00000004) 1429 #define PADS_BANK0_GPIO19_PDE_MSB _u(2) 1430 #define PADS_BANK0_GPIO19_PDE_LSB _u(2) 1431 #define PADS_BANK0_GPIO19_PDE_ACCESS "RW" 1432 // ----------------------------------------------------------------------------- 1433 // Field : PADS_BANK0_GPIO19_SCHMITT 1434 // Description : Enable schmitt trigger 1435 #define PADS_BANK0_GPIO19_SCHMITT_RESET _u(0x1) 1436 #define PADS_BANK0_GPIO19_SCHMITT_BITS _u(0x00000002) 1437 #define PADS_BANK0_GPIO19_SCHMITT_MSB _u(1) 1438 #define PADS_BANK0_GPIO19_SCHMITT_LSB _u(1) 1439 #define PADS_BANK0_GPIO19_SCHMITT_ACCESS "RW" 1440 // ----------------------------------------------------------------------------- 1441 // Field : PADS_BANK0_GPIO19_SLEWFAST 1442 // Description : Slew rate control. 1 = Fast, 0 = Slow 1443 #define PADS_BANK0_GPIO19_SLEWFAST_RESET _u(0x0) 1444 #define PADS_BANK0_GPIO19_SLEWFAST_BITS _u(0x00000001) 1445 #define PADS_BANK0_GPIO19_SLEWFAST_MSB _u(0) 1446 #define PADS_BANK0_GPIO19_SLEWFAST_LSB _u(0) 1447 #define PADS_BANK0_GPIO19_SLEWFAST_ACCESS "RW" 1448 // ============================================================================= 1449 // Register : PADS_BANK0_GPIO20 1450 // Description : Pad control register 1451 #define PADS_BANK0_GPIO20_OFFSET _u(0x00000054) 1452 #define PADS_BANK0_GPIO20_BITS _u(0x000000ff) 1453 #define PADS_BANK0_GPIO20_RESET _u(0x00000056) 1454 // ----------------------------------------------------------------------------- 1455 // Field : PADS_BANK0_GPIO20_OD 1456 // Description : Output disable. Has priority over output enable from 1457 // peripherals 1458 #define PADS_BANK0_GPIO20_OD_RESET _u(0x0) 1459 #define PADS_BANK0_GPIO20_OD_BITS _u(0x00000080) 1460 #define PADS_BANK0_GPIO20_OD_MSB _u(7) 1461 #define PADS_BANK0_GPIO20_OD_LSB _u(7) 1462 #define PADS_BANK0_GPIO20_OD_ACCESS "RW" 1463 // ----------------------------------------------------------------------------- 1464 // Field : PADS_BANK0_GPIO20_IE 1465 // Description : Input enable 1466 #define PADS_BANK0_GPIO20_IE_RESET _u(0x1) 1467 #define PADS_BANK0_GPIO20_IE_BITS _u(0x00000040) 1468 #define PADS_BANK0_GPIO20_IE_MSB _u(6) 1469 #define PADS_BANK0_GPIO20_IE_LSB _u(6) 1470 #define PADS_BANK0_GPIO20_IE_ACCESS "RW" 1471 // ----------------------------------------------------------------------------- 1472 // Field : PADS_BANK0_GPIO20_DRIVE 1473 // Description : Drive strength. 1474 // 0x0 -> 2mA 1475 // 0x1 -> 4mA 1476 // 0x2 -> 8mA 1477 // 0x3 -> 12mA 1478 #define PADS_BANK0_GPIO20_DRIVE_RESET _u(0x1) 1479 #define PADS_BANK0_GPIO20_DRIVE_BITS _u(0x00000030) 1480 #define PADS_BANK0_GPIO20_DRIVE_MSB _u(5) 1481 #define PADS_BANK0_GPIO20_DRIVE_LSB _u(4) 1482 #define PADS_BANK0_GPIO20_DRIVE_ACCESS "RW" 1483 #define PADS_BANK0_GPIO20_DRIVE_VALUE_2MA _u(0x0) 1484 #define PADS_BANK0_GPIO20_DRIVE_VALUE_4MA _u(0x1) 1485 #define PADS_BANK0_GPIO20_DRIVE_VALUE_8MA _u(0x2) 1486 #define PADS_BANK0_GPIO20_DRIVE_VALUE_12MA _u(0x3) 1487 // ----------------------------------------------------------------------------- 1488 // Field : PADS_BANK0_GPIO20_PUE 1489 // Description : Pull up enable 1490 #define PADS_BANK0_GPIO20_PUE_RESET _u(0x0) 1491 #define PADS_BANK0_GPIO20_PUE_BITS _u(0x00000008) 1492 #define PADS_BANK0_GPIO20_PUE_MSB _u(3) 1493 #define PADS_BANK0_GPIO20_PUE_LSB _u(3) 1494 #define PADS_BANK0_GPIO20_PUE_ACCESS "RW" 1495 // ----------------------------------------------------------------------------- 1496 // Field : PADS_BANK0_GPIO20_PDE 1497 // Description : Pull down enable 1498 #define PADS_BANK0_GPIO20_PDE_RESET _u(0x1) 1499 #define PADS_BANK0_GPIO20_PDE_BITS _u(0x00000004) 1500 #define PADS_BANK0_GPIO20_PDE_MSB _u(2) 1501 #define PADS_BANK0_GPIO20_PDE_LSB _u(2) 1502 #define PADS_BANK0_GPIO20_PDE_ACCESS "RW" 1503 // ----------------------------------------------------------------------------- 1504 // Field : PADS_BANK0_GPIO20_SCHMITT 1505 // Description : Enable schmitt trigger 1506 #define PADS_BANK0_GPIO20_SCHMITT_RESET _u(0x1) 1507 #define PADS_BANK0_GPIO20_SCHMITT_BITS _u(0x00000002) 1508 #define PADS_BANK0_GPIO20_SCHMITT_MSB _u(1) 1509 #define PADS_BANK0_GPIO20_SCHMITT_LSB _u(1) 1510 #define PADS_BANK0_GPIO20_SCHMITT_ACCESS "RW" 1511 // ----------------------------------------------------------------------------- 1512 // Field : PADS_BANK0_GPIO20_SLEWFAST 1513 // Description : Slew rate control. 1 = Fast, 0 = Slow 1514 #define PADS_BANK0_GPIO20_SLEWFAST_RESET _u(0x0) 1515 #define PADS_BANK0_GPIO20_SLEWFAST_BITS _u(0x00000001) 1516 #define PADS_BANK0_GPIO20_SLEWFAST_MSB _u(0) 1517 #define PADS_BANK0_GPIO20_SLEWFAST_LSB _u(0) 1518 #define PADS_BANK0_GPIO20_SLEWFAST_ACCESS "RW" 1519 // ============================================================================= 1520 // Register : PADS_BANK0_GPIO21 1521 // Description : Pad control register 1522 #define PADS_BANK0_GPIO21_OFFSET _u(0x00000058) 1523 #define PADS_BANK0_GPIO21_BITS _u(0x000000ff) 1524 #define PADS_BANK0_GPIO21_RESET _u(0x00000056) 1525 // ----------------------------------------------------------------------------- 1526 // Field : PADS_BANK0_GPIO21_OD 1527 // Description : Output disable. Has priority over output enable from 1528 // peripherals 1529 #define PADS_BANK0_GPIO21_OD_RESET _u(0x0) 1530 #define PADS_BANK0_GPIO21_OD_BITS _u(0x00000080) 1531 #define PADS_BANK0_GPIO21_OD_MSB _u(7) 1532 #define PADS_BANK0_GPIO21_OD_LSB _u(7) 1533 #define PADS_BANK0_GPIO21_OD_ACCESS "RW" 1534 // ----------------------------------------------------------------------------- 1535 // Field : PADS_BANK0_GPIO21_IE 1536 // Description : Input enable 1537 #define PADS_BANK0_GPIO21_IE_RESET _u(0x1) 1538 #define PADS_BANK0_GPIO21_IE_BITS _u(0x00000040) 1539 #define PADS_BANK0_GPIO21_IE_MSB _u(6) 1540 #define PADS_BANK0_GPIO21_IE_LSB _u(6) 1541 #define PADS_BANK0_GPIO21_IE_ACCESS "RW" 1542 // ----------------------------------------------------------------------------- 1543 // Field : PADS_BANK0_GPIO21_DRIVE 1544 // Description : Drive strength. 1545 // 0x0 -> 2mA 1546 // 0x1 -> 4mA 1547 // 0x2 -> 8mA 1548 // 0x3 -> 12mA 1549 #define PADS_BANK0_GPIO21_DRIVE_RESET _u(0x1) 1550 #define PADS_BANK0_GPIO21_DRIVE_BITS _u(0x00000030) 1551 #define PADS_BANK0_GPIO21_DRIVE_MSB _u(5) 1552 #define PADS_BANK0_GPIO21_DRIVE_LSB _u(4) 1553 #define PADS_BANK0_GPIO21_DRIVE_ACCESS "RW" 1554 #define PADS_BANK0_GPIO21_DRIVE_VALUE_2MA _u(0x0) 1555 #define PADS_BANK0_GPIO21_DRIVE_VALUE_4MA _u(0x1) 1556 #define PADS_BANK0_GPIO21_DRIVE_VALUE_8MA _u(0x2) 1557 #define PADS_BANK0_GPIO21_DRIVE_VALUE_12MA _u(0x3) 1558 // ----------------------------------------------------------------------------- 1559 // Field : PADS_BANK0_GPIO21_PUE 1560 // Description : Pull up enable 1561 #define PADS_BANK0_GPIO21_PUE_RESET _u(0x0) 1562 #define PADS_BANK0_GPIO21_PUE_BITS _u(0x00000008) 1563 #define PADS_BANK0_GPIO21_PUE_MSB _u(3) 1564 #define PADS_BANK0_GPIO21_PUE_LSB _u(3) 1565 #define PADS_BANK0_GPIO21_PUE_ACCESS "RW" 1566 // ----------------------------------------------------------------------------- 1567 // Field : PADS_BANK0_GPIO21_PDE 1568 // Description : Pull down enable 1569 #define PADS_BANK0_GPIO21_PDE_RESET _u(0x1) 1570 #define PADS_BANK0_GPIO21_PDE_BITS _u(0x00000004) 1571 #define PADS_BANK0_GPIO21_PDE_MSB _u(2) 1572 #define PADS_BANK0_GPIO21_PDE_LSB _u(2) 1573 #define PADS_BANK0_GPIO21_PDE_ACCESS "RW" 1574 // ----------------------------------------------------------------------------- 1575 // Field : PADS_BANK0_GPIO21_SCHMITT 1576 // Description : Enable schmitt trigger 1577 #define PADS_BANK0_GPIO21_SCHMITT_RESET _u(0x1) 1578 #define PADS_BANK0_GPIO21_SCHMITT_BITS _u(0x00000002) 1579 #define PADS_BANK0_GPIO21_SCHMITT_MSB _u(1) 1580 #define PADS_BANK0_GPIO21_SCHMITT_LSB _u(1) 1581 #define PADS_BANK0_GPIO21_SCHMITT_ACCESS "RW" 1582 // ----------------------------------------------------------------------------- 1583 // Field : PADS_BANK0_GPIO21_SLEWFAST 1584 // Description : Slew rate control. 1 = Fast, 0 = Slow 1585 #define PADS_BANK0_GPIO21_SLEWFAST_RESET _u(0x0) 1586 #define PADS_BANK0_GPIO21_SLEWFAST_BITS _u(0x00000001) 1587 #define PADS_BANK0_GPIO21_SLEWFAST_MSB _u(0) 1588 #define PADS_BANK0_GPIO21_SLEWFAST_LSB _u(0) 1589 #define PADS_BANK0_GPIO21_SLEWFAST_ACCESS "RW" 1590 // ============================================================================= 1591 // Register : PADS_BANK0_GPIO22 1592 // Description : Pad control register 1593 #define PADS_BANK0_GPIO22_OFFSET _u(0x0000005c) 1594 #define PADS_BANK0_GPIO22_BITS _u(0x000000ff) 1595 #define PADS_BANK0_GPIO22_RESET _u(0x00000056) 1596 // ----------------------------------------------------------------------------- 1597 // Field : PADS_BANK0_GPIO22_OD 1598 // Description : Output disable. Has priority over output enable from 1599 // peripherals 1600 #define PADS_BANK0_GPIO22_OD_RESET _u(0x0) 1601 #define PADS_BANK0_GPIO22_OD_BITS _u(0x00000080) 1602 #define PADS_BANK0_GPIO22_OD_MSB _u(7) 1603 #define PADS_BANK0_GPIO22_OD_LSB _u(7) 1604 #define PADS_BANK0_GPIO22_OD_ACCESS "RW" 1605 // ----------------------------------------------------------------------------- 1606 // Field : PADS_BANK0_GPIO22_IE 1607 // Description : Input enable 1608 #define PADS_BANK0_GPIO22_IE_RESET _u(0x1) 1609 #define PADS_BANK0_GPIO22_IE_BITS _u(0x00000040) 1610 #define PADS_BANK0_GPIO22_IE_MSB _u(6) 1611 #define PADS_BANK0_GPIO22_IE_LSB _u(6) 1612 #define PADS_BANK0_GPIO22_IE_ACCESS "RW" 1613 // ----------------------------------------------------------------------------- 1614 // Field : PADS_BANK0_GPIO22_DRIVE 1615 // Description : Drive strength. 1616 // 0x0 -> 2mA 1617 // 0x1 -> 4mA 1618 // 0x2 -> 8mA 1619 // 0x3 -> 12mA 1620 #define PADS_BANK0_GPIO22_DRIVE_RESET _u(0x1) 1621 #define PADS_BANK0_GPIO22_DRIVE_BITS _u(0x00000030) 1622 #define PADS_BANK0_GPIO22_DRIVE_MSB _u(5) 1623 #define PADS_BANK0_GPIO22_DRIVE_LSB _u(4) 1624 #define PADS_BANK0_GPIO22_DRIVE_ACCESS "RW" 1625 #define PADS_BANK0_GPIO22_DRIVE_VALUE_2MA _u(0x0) 1626 #define PADS_BANK0_GPIO22_DRIVE_VALUE_4MA _u(0x1) 1627 #define PADS_BANK0_GPIO22_DRIVE_VALUE_8MA _u(0x2) 1628 #define PADS_BANK0_GPIO22_DRIVE_VALUE_12MA _u(0x3) 1629 // ----------------------------------------------------------------------------- 1630 // Field : PADS_BANK0_GPIO22_PUE 1631 // Description : Pull up enable 1632 #define PADS_BANK0_GPIO22_PUE_RESET _u(0x0) 1633 #define PADS_BANK0_GPIO22_PUE_BITS _u(0x00000008) 1634 #define PADS_BANK0_GPIO22_PUE_MSB _u(3) 1635 #define PADS_BANK0_GPIO22_PUE_LSB _u(3) 1636 #define PADS_BANK0_GPIO22_PUE_ACCESS "RW" 1637 // ----------------------------------------------------------------------------- 1638 // Field : PADS_BANK0_GPIO22_PDE 1639 // Description : Pull down enable 1640 #define PADS_BANK0_GPIO22_PDE_RESET _u(0x1) 1641 #define PADS_BANK0_GPIO22_PDE_BITS _u(0x00000004) 1642 #define PADS_BANK0_GPIO22_PDE_MSB _u(2) 1643 #define PADS_BANK0_GPIO22_PDE_LSB _u(2) 1644 #define PADS_BANK0_GPIO22_PDE_ACCESS "RW" 1645 // ----------------------------------------------------------------------------- 1646 // Field : PADS_BANK0_GPIO22_SCHMITT 1647 // Description : Enable schmitt trigger 1648 #define PADS_BANK0_GPIO22_SCHMITT_RESET _u(0x1) 1649 #define PADS_BANK0_GPIO22_SCHMITT_BITS _u(0x00000002) 1650 #define PADS_BANK0_GPIO22_SCHMITT_MSB _u(1) 1651 #define PADS_BANK0_GPIO22_SCHMITT_LSB _u(1) 1652 #define PADS_BANK0_GPIO22_SCHMITT_ACCESS "RW" 1653 // ----------------------------------------------------------------------------- 1654 // Field : PADS_BANK0_GPIO22_SLEWFAST 1655 // Description : Slew rate control. 1 = Fast, 0 = Slow 1656 #define PADS_BANK0_GPIO22_SLEWFAST_RESET _u(0x0) 1657 #define PADS_BANK0_GPIO22_SLEWFAST_BITS _u(0x00000001) 1658 #define PADS_BANK0_GPIO22_SLEWFAST_MSB _u(0) 1659 #define PADS_BANK0_GPIO22_SLEWFAST_LSB _u(0) 1660 #define PADS_BANK0_GPIO22_SLEWFAST_ACCESS "RW" 1661 // ============================================================================= 1662 // Register : PADS_BANK0_GPIO23 1663 // Description : Pad control register 1664 #define PADS_BANK0_GPIO23_OFFSET _u(0x00000060) 1665 #define PADS_BANK0_GPIO23_BITS _u(0x000000ff) 1666 #define PADS_BANK0_GPIO23_RESET _u(0x00000056) 1667 // ----------------------------------------------------------------------------- 1668 // Field : PADS_BANK0_GPIO23_OD 1669 // Description : Output disable. Has priority over output enable from 1670 // peripherals 1671 #define PADS_BANK0_GPIO23_OD_RESET _u(0x0) 1672 #define PADS_BANK0_GPIO23_OD_BITS _u(0x00000080) 1673 #define PADS_BANK0_GPIO23_OD_MSB _u(7) 1674 #define PADS_BANK0_GPIO23_OD_LSB _u(7) 1675 #define PADS_BANK0_GPIO23_OD_ACCESS "RW" 1676 // ----------------------------------------------------------------------------- 1677 // Field : PADS_BANK0_GPIO23_IE 1678 // Description : Input enable 1679 #define PADS_BANK0_GPIO23_IE_RESET _u(0x1) 1680 #define PADS_BANK0_GPIO23_IE_BITS _u(0x00000040) 1681 #define PADS_BANK0_GPIO23_IE_MSB _u(6) 1682 #define PADS_BANK0_GPIO23_IE_LSB _u(6) 1683 #define PADS_BANK0_GPIO23_IE_ACCESS "RW" 1684 // ----------------------------------------------------------------------------- 1685 // Field : PADS_BANK0_GPIO23_DRIVE 1686 // Description : Drive strength. 1687 // 0x0 -> 2mA 1688 // 0x1 -> 4mA 1689 // 0x2 -> 8mA 1690 // 0x3 -> 12mA 1691 #define PADS_BANK0_GPIO23_DRIVE_RESET _u(0x1) 1692 #define PADS_BANK0_GPIO23_DRIVE_BITS _u(0x00000030) 1693 #define PADS_BANK0_GPIO23_DRIVE_MSB _u(5) 1694 #define PADS_BANK0_GPIO23_DRIVE_LSB _u(4) 1695 #define PADS_BANK0_GPIO23_DRIVE_ACCESS "RW" 1696 #define PADS_BANK0_GPIO23_DRIVE_VALUE_2MA _u(0x0) 1697 #define PADS_BANK0_GPIO23_DRIVE_VALUE_4MA _u(0x1) 1698 #define PADS_BANK0_GPIO23_DRIVE_VALUE_8MA _u(0x2) 1699 #define PADS_BANK0_GPIO23_DRIVE_VALUE_12MA _u(0x3) 1700 // ----------------------------------------------------------------------------- 1701 // Field : PADS_BANK0_GPIO23_PUE 1702 // Description : Pull up enable 1703 #define PADS_BANK0_GPIO23_PUE_RESET _u(0x0) 1704 #define PADS_BANK0_GPIO23_PUE_BITS _u(0x00000008) 1705 #define PADS_BANK0_GPIO23_PUE_MSB _u(3) 1706 #define PADS_BANK0_GPIO23_PUE_LSB _u(3) 1707 #define PADS_BANK0_GPIO23_PUE_ACCESS "RW" 1708 // ----------------------------------------------------------------------------- 1709 // Field : PADS_BANK0_GPIO23_PDE 1710 // Description : Pull down enable 1711 #define PADS_BANK0_GPIO23_PDE_RESET _u(0x1) 1712 #define PADS_BANK0_GPIO23_PDE_BITS _u(0x00000004) 1713 #define PADS_BANK0_GPIO23_PDE_MSB _u(2) 1714 #define PADS_BANK0_GPIO23_PDE_LSB _u(2) 1715 #define PADS_BANK0_GPIO23_PDE_ACCESS "RW" 1716 // ----------------------------------------------------------------------------- 1717 // Field : PADS_BANK0_GPIO23_SCHMITT 1718 // Description : Enable schmitt trigger 1719 #define PADS_BANK0_GPIO23_SCHMITT_RESET _u(0x1) 1720 #define PADS_BANK0_GPIO23_SCHMITT_BITS _u(0x00000002) 1721 #define PADS_BANK0_GPIO23_SCHMITT_MSB _u(1) 1722 #define PADS_BANK0_GPIO23_SCHMITT_LSB _u(1) 1723 #define PADS_BANK0_GPIO23_SCHMITT_ACCESS "RW" 1724 // ----------------------------------------------------------------------------- 1725 // Field : PADS_BANK0_GPIO23_SLEWFAST 1726 // Description : Slew rate control. 1 = Fast, 0 = Slow 1727 #define PADS_BANK0_GPIO23_SLEWFAST_RESET _u(0x0) 1728 #define PADS_BANK0_GPIO23_SLEWFAST_BITS _u(0x00000001) 1729 #define PADS_BANK0_GPIO23_SLEWFAST_MSB _u(0) 1730 #define PADS_BANK0_GPIO23_SLEWFAST_LSB _u(0) 1731 #define PADS_BANK0_GPIO23_SLEWFAST_ACCESS "RW" 1732 // ============================================================================= 1733 // Register : PADS_BANK0_GPIO24 1734 // Description : Pad control register 1735 #define PADS_BANK0_GPIO24_OFFSET _u(0x00000064) 1736 #define PADS_BANK0_GPIO24_BITS _u(0x000000ff) 1737 #define PADS_BANK0_GPIO24_RESET _u(0x00000056) 1738 // ----------------------------------------------------------------------------- 1739 // Field : PADS_BANK0_GPIO24_OD 1740 // Description : Output disable. Has priority over output enable from 1741 // peripherals 1742 #define PADS_BANK0_GPIO24_OD_RESET _u(0x0) 1743 #define PADS_BANK0_GPIO24_OD_BITS _u(0x00000080) 1744 #define PADS_BANK0_GPIO24_OD_MSB _u(7) 1745 #define PADS_BANK0_GPIO24_OD_LSB _u(7) 1746 #define PADS_BANK0_GPIO24_OD_ACCESS "RW" 1747 // ----------------------------------------------------------------------------- 1748 // Field : PADS_BANK0_GPIO24_IE 1749 // Description : Input enable 1750 #define PADS_BANK0_GPIO24_IE_RESET _u(0x1) 1751 #define PADS_BANK0_GPIO24_IE_BITS _u(0x00000040) 1752 #define PADS_BANK0_GPIO24_IE_MSB _u(6) 1753 #define PADS_BANK0_GPIO24_IE_LSB _u(6) 1754 #define PADS_BANK0_GPIO24_IE_ACCESS "RW" 1755 // ----------------------------------------------------------------------------- 1756 // Field : PADS_BANK0_GPIO24_DRIVE 1757 // Description : Drive strength. 1758 // 0x0 -> 2mA 1759 // 0x1 -> 4mA 1760 // 0x2 -> 8mA 1761 // 0x3 -> 12mA 1762 #define PADS_BANK0_GPIO24_DRIVE_RESET _u(0x1) 1763 #define PADS_BANK0_GPIO24_DRIVE_BITS _u(0x00000030) 1764 #define PADS_BANK0_GPIO24_DRIVE_MSB _u(5) 1765 #define PADS_BANK0_GPIO24_DRIVE_LSB _u(4) 1766 #define PADS_BANK0_GPIO24_DRIVE_ACCESS "RW" 1767 #define PADS_BANK0_GPIO24_DRIVE_VALUE_2MA _u(0x0) 1768 #define PADS_BANK0_GPIO24_DRIVE_VALUE_4MA _u(0x1) 1769 #define PADS_BANK0_GPIO24_DRIVE_VALUE_8MA _u(0x2) 1770 #define PADS_BANK0_GPIO24_DRIVE_VALUE_12MA _u(0x3) 1771 // ----------------------------------------------------------------------------- 1772 // Field : PADS_BANK0_GPIO24_PUE 1773 // Description : Pull up enable 1774 #define PADS_BANK0_GPIO24_PUE_RESET _u(0x0) 1775 #define PADS_BANK0_GPIO24_PUE_BITS _u(0x00000008) 1776 #define PADS_BANK0_GPIO24_PUE_MSB _u(3) 1777 #define PADS_BANK0_GPIO24_PUE_LSB _u(3) 1778 #define PADS_BANK0_GPIO24_PUE_ACCESS "RW" 1779 // ----------------------------------------------------------------------------- 1780 // Field : PADS_BANK0_GPIO24_PDE 1781 // Description : Pull down enable 1782 #define PADS_BANK0_GPIO24_PDE_RESET _u(0x1) 1783 #define PADS_BANK0_GPIO24_PDE_BITS _u(0x00000004) 1784 #define PADS_BANK0_GPIO24_PDE_MSB _u(2) 1785 #define PADS_BANK0_GPIO24_PDE_LSB _u(2) 1786 #define PADS_BANK0_GPIO24_PDE_ACCESS "RW" 1787 // ----------------------------------------------------------------------------- 1788 // Field : PADS_BANK0_GPIO24_SCHMITT 1789 // Description : Enable schmitt trigger 1790 #define PADS_BANK0_GPIO24_SCHMITT_RESET _u(0x1) 1791 #define PADS_BANK0_GPIO24_SCHMITT_BITS _u(0x00000002) 1792 #define PADS_BANK0_GPIO24_SCHMITT_MSB _u(1) 1793 #define PADS_BANK0_GPIO24_SCHMITT_LSB _u(1) 1794 #define PADS_BANK0_GPIO24_SCHMITT_ACCESS "RW" 1795 // ----------------------------------------------------------------------------- 1796 // Field : PADS_BANK0_GPIO24_SLEWFAST 1797 // Description : Slew rate control. 1 = Fast, 0 = Slow 1798 #define PADS_BANK0_GPIO24_SLEWFAST_RESET _u(0x0) 1799 #define PADS_BANK0_GPIO24_SLEWFAST_BITS _u(0x00000001) 1800 #define PADS_BANK0_GPIO24_SLEWFAST_MSB _u(0) 1801 #define PADS_BANK0_GPIO24_SLEWFAST_LSB _u(0) 1802 #define PADS_BANK0_GPIO24_SLEWFAST_ACCESS "RW" 1803 // ============================================================================= 1804 // Register : PADS_BANK0_GPIO25 1805 // Description : Pad control register 1806 #define PADS_BANK0_GPIO25_OFFSET _u(0x00000068) 1807 #define PADS_BANK0_GPIO25_BITS _u(0x000000ff) 1808 #define PADS_BANK0_GPIO25_RESET _u(0x00000056) 1809 // ----------------------------------------------------------------------------- 1810 // Field : PADS_BANK0_GPIO25_OD 1811 // Description : Output disable. Has priority over output enable from 1812 // peripherals 1813 #define PADS_BANK0_GPIO25_OD_RESET _u(0x0) 1814 #define PADS_BANK0_GPIO25_OD_BITS _u(0x00000080) 1815 #define PADS_BANK0_GPIO25_OD_MSB _u(7) 1816 #define PADS_BANK0_GPIO25_OD_LSB _u(7) 1817 #define PADS_BANK0_GPIO25_OD_ACCESS "RW" 1818 // ----------------------------------------------------------------------------- 1819 // Field : PADS_BANK0_GPIO25_IE 1820 // Description : Input enable 1821 #define PADS_BANK0_GPIO25_IE_RESET _u(0x1) 1822 #define PADS_BANK0_GPIO25_IE_BITS _u(0x00000040) 1823 #define PADS_BANK0_GPIO25_IE_MSB _u(6) 1824 #define PADS_BANK0_GPIO25_IE_LSB _u(6) 1825 #define PADS_BANK0_GPIO25_IE_ACCESS "RW" 1826 // ----------------------------------------------------------------------------- 1827 // Field : PADS_BANK0_GPIO25_DRIVE 1828 // Description : Drive strength. 1829 // 0x0 -> 2mA 1830 // 0x1 -> 4mA 1831 // 0x2 -> 8mA 1832 // 0x3 -> 12mA 1833 #define PADS_BANK0_GPIO25_DRIVE_RESET _u(0x1) 1834 #define PADS_BANK0_GPIO25_DRIVE_BITS _u(0x00000030) 1835 #define PADS_BANK0_GPIO25_DRIVE_MSB _u(5) 1836 #define PADS_BANK0_GPIO25_DRIVE_LSB _u(4) 1837 #define PADS_BANK0_GPIO25_DRIVE_ACCESS "RW" 1838 #define PADS_BANK0_GPIO25_DRIVE_VALUE_2MA _u(0x0) 1839 #define PADS_BANK0_GPIO25_DRIVE_VALUE_4MA _u(0x1) 1840 #define PADS_BANK0_GPIO25_DRIVE_VALUE_8MA _u(0x2) 1841 #define PADS_BANK0_GPIO25_DRIVE_VALUE_12MA _u(0x3) 1842 // ----------------------------------------------------------------------------- 1843 // Field : PADS_BANK0_GPIO25_PUE 1844 // Description : Pull up enable 1845 #define PADS_BANK0_GPIO25_PUE_RESET _u(0x0) 1846 #define PADS_BANK0_GPIO25_PUE_BITS _u(0x00000008) 1847 #define PADS_BANK0_GPIO25_PUE_MSB _u(3) 1848 #define PADS_BANK0_GPIO25_PUE_LSB _u(3) 1849 #define PADS_BANK0_GPIO25_PUE_ACCESS "RW" 1850 // ----------------------------------------------------------------------------- 1851 // Field : PADS_BANK0_GPIO25_PDE 1852 // Description : Pull down enable 1853 #define PADS_BANK0_GPIO25_PDE_RESET _u(0x1) 1854 #define PADS_BANK0_GPIO25_PDE_BITS _u(0x00000004) 1855 #define PADS_BANK0_GPIO25_PDE_MSB _u(2) 1856 #define PADS_BANK0_GPIO25_PDE_LSB _u(2) 1857 #define PADS_BANK0_GPIO25_PDE_ACCESS "RW" 1858 // ----------------------------------------------------------------------------- 1859 // Field : PADS_BANK0_GPIO25_SCHMITT 1860 // Description : Enable schmitt trigger 1861 #define PADS_BANK0_GPIO25_SCHMITT_RESET _u(0x1) 1862 #define PADS_BANK0_GPIO25_SCHMITT_BITS _u(0x00000002) 1863 #define PADS_BANK0_GPIO25_SCHMITT_MSB _u(1) 1864 #define PADS_BANK0_GPIO25_SCHMITT_LSB _u(1) 1865 #define PADS_BANK0_GPIO25_SCHMITT_ACCESS "RW" 1866 // ----------------------------------------------------------------------------- 1867 // Field : PADS_BANK0_GPIO25_SLEWFAST 1868 // Description : Slew rate control. 1 = Fast, 0 = Slow 1869 #define PADS_BANK0_GPIO25_SLEWFAST_RESET _u(0x0) 1870 #define PADS_BANK0_GPIO25_SLEWFAST_BITS _u(0x00000001) 1871 #define PADS_BANK0_GPIO25_SLEWFAST_MSB _u(0) 1872 #define PADS_BANK0_GPIO25_SLEWFAST_LSB _u(0) 1873 #define PADS_BANK0_GPIO25_SLEWFAST_ACCESS "RW" 1874 // ============================================================================= 1875 // Register : PADS_BANK0_GPIO26 1876 // Description : Pad control register 1877 #define PADS_BANK0_GPIO26_OFFSET _u(0x0000006c) 1878 #define PADS_BANK0_GPIO26_BITS _u(0x000000ff) 1879 #define PADS_BANK0_GPIO26_RESET _u(0x00000056) 1880 // ----------------------------------------------------------------------------- 1881 // Field : PADS_BANK0_GPIO26_OD 1882 // Description : Output disable. Has priority over output enable from 1883 // peripherals 1884 #define PADS_BANK0_GPIO26_OD_RESET _u(0x0) 1885 #define PADS_BANK0_GPIO26_OD_BITS _u(0x00000080) 1886 #define PADS_BANK0_GPIO26_OD_MSB _u(7) 1887 #define PADS_BANK0_GPIO26_OD_LSB _u(7) 1888 #define PADS_BANK0_GPIO26_OD_ACCESS "RW" 1889 // ----------------------------------------------------------------------------- 1890 // Field : PADS_BANK0_GPIO26_IE 1891 // Description : Input enable 1892 #define PADS_BANK0_GPIO26_IE_RESET _u(0x1) 1893 #define PADS_BANK0_GPIO26_IE_BITS _u(0x00000040) 1894 #define PADS_BANK0_GPIO26_IE_MSB _u(6) 1895 #define PADS_BANK0_GPIO26_IE_LSB _u(6) 1896 #define PADS_BANK0_GPIO26_IE_ACCESS "RW" 1897 // ----------------------------------------------------------------------------- 1898 // Field : PADS_BANK0_GPIO26_DRIVE 1899 // Description : Drive strength. 1900 // 0x0 -> 2mA 1901 // 0x1 -> 4mA 1902 // 0x2 -> 8mA 1903 // 0x3 -> 12mA 1904 #define PADS_BANK0_GPIO26_DRIVE_RESET _u(0x1) 1905 #define PADS_BANK0_GPIO26_DRIVE_BITS _u(0x00000030) 1906 #define PADS_BANK0_GPIO26_DRIVE_MSB _u(5) 1907 #define PADS_BANK0_GPIO26_DRIVE_LSB _u(4) 1908 #define PADS_BANK0_GPIO26_DRIVE_ACCESS "RW" 1909 #define PADS_BANK0_GPIO26_DRIVE_VALUE_2MA _u(0x0) 1910 #define PADS_BANK0_GPIO26_DRIVE_VALUE_4MA _u(0x1) 1911 #define PADS_BANK0_GPIO26_DRIVE_VALUE_8MA _u(0x2) 1912 #define PADS_BANK0_GPIO26_DRIVE_VALUE_12MA _u(0x3) 1913 // ----------------------------------------------------------------------------- 1914 // Field : PADS_BANK0_GPIO26_PUE 1915 // Description : Pull up enable 1916 #define PADS_BANK0_GPIO26_PUE_RESET _u(0x0) 1917 #define PADS_BANK0_GPIO26_PUE_BITS _u(0x00000008) 1918 #define PADS_BANK0_GPIO26_PUE_MSB _u(3) 1919 #define PADS_BANK0_GPIO26_PUE_LSB _u(3) 1920 #define PADS_BANK0_GPIO26_PUE_ACCESS "RW" 1921 // ----------------------------------------------------------------------------- 1922 // Field : PADS_BANK0_GPIO26_PDE 1923 // Description : Pull down enable 1924 #define PADS_BANK0_GPIO26_PDE_RESET _u(0x1) 1925 #define PADS_BANK0_GPIO26_PDE_BITS _u(0x00000004) 1926 #define PADS_BANK0_GPIO26_PDE_MSB _u(2) 1927 #define PADS_BANK0_GPIO26_PDE_LSB _u(2) 1928 #define PADS_BANK0_GPIO26_PDE_ACCESS "RW" 1929 // ----------------------------------------------------------------------------- 1930 // Field : PADS_BANK0_GPIO26_SCHMITT 1931 // Description : Enable schmitt trigger 1932 #define PADS_BANK0_GPIO26_SCHMITT_RESET _u(0x1) 1933 #define PADS_BANK0_GPIO26_SCHMITT_BITS _u(0x00000002) 1934 #define PADS_BANK0_GPIO26_SCHMITT_MSB _u(1) 1935 #define PADS_BANK0_GPIO26_SCHMITT_LSB _u(1) 1936 #define PADS_BANK0_GPIO26_SCHMITT_ACCESS "RW" 1937 // ----------------------------------------------------------------------------- 1938 // Field : PADS_BANK0_GPIO26_SLEWFAST 1939 // Description : Slew rate control. 1 = Fast, 0 = Slow 1940 #define PADS_BANK0_GPIO26_SLEWFAST_RESET _u(0x0) 1941 #define PADS_BANK0_GPIO26_SLEWFAST_BITS _u(0x00000001) 1942 #define PADS_BANK0_GPIO26_SLEWFAST_MSB _u(0) 1943 #define PADS_BANK0_GPIO26_SLEWFAST_LSB _u(0) 1944 #define PADS_BANK0_GPIO26_SLEWFAST_ACCESS "RW" 1945 // ============================================================================= 1946 // Register : PADS_BANK0_GPIO27 1947 // Description : Pad control register 1948 #define PADS_BANK0_GPIO27_OFFSET _u(0x00000070) 1949 #define PADS_BANK0_GPIO27_BITS _u(0x000000ff) 1950 #define PADS_BANK0_GPIO27_RESET _u(0x00000056) 1951 // ----------------------------------------------------------------------------- 1952 // Field : PADS_BANK0_GPIO27_OD 1953 // Description : Output disable. Has priority over output enable from 1954 // peripherals 1955 #define PADS_BANK0_GPIO27_OD_RESET _u(0x0) 1956 #define PADS_BANK0_GPIO27_OD_BITS _u(0x00000080) 1957 #define PADS_BANK0_GPIO27_OD_MSB _u(7) 1958 #define PADS_BANK0_GPIO27_OD_LSB _u(7) 1959 #define PADS_BANK0_GPIO27_OD_ACCESS "RW" 1960 // ----------------------------------------------------------------------------- 1961 // Field : PADS_BANK0_GPIO27_IE 1962 // Description : Input enable 1963 #define PADS_BANK0_GPIO27_IE_RESET _u(0x1) 1964 #define PADS_BANK0_GPIO27_IE_BITS _u(0x00000040) 1965 #define PADS_BANK0_GPIO27_IE_MSB _u(6) 1966 #define PADS_BANK0_GPIO27_IE_LSB _u(6) 1967 #define PADS_BANK0_GPIO27_IE_ACCESS "RW" 1968 // ----------------------------------------------------------------------------- 1969 // Field : PADS_BANK0_GPIO27_DRIVE 1970 // Description : Drive strength. 1971 // 0x0 -> 2mA 1972 // 0x1 -> 4mA 1973 // 0x2 -> 8mA 1974 // 0x3 -> 12mA 1975 #define PADS_BANK0_GPIO27_DRIVE_RESET _u(0x1) 1976 #define PADS_BANK0_GPIO27_DRIVE_BITS _u(0x00000030) 1977 #define PADS_BANK0_GPIO27_DRIVE_MSB _u(5) 1978 #define PADS_BANK0_GPIO27_DRIVE_LSB _u(4) 1979 #define PADS_BANK0_GPIO27_DRIVE_ACCESS "RW" 1980 #define PADS_BANK0_GPIO27_DRIVE_VALUE_2MA _u(0x0) 1981 #define PADS_BANK0_GPIO27_DRIVE_VALUE_4MA _u(0x1) 1982 #define PADS_BANK0_GPIO27_DRIVE_VALUE_8MA _u(0x2) 1983 #define PADS_BANK0_GPIO27_DRIVE_VALUE_12MA _u(0x3) 1984 // ----------------------------------------------------------------------------- 1985 // Field : PADS_BANK0_GPIO27_PUE 1986 // Description : Pull up enable 1987 #define PADS_BANK0_GPIO27_PUE_RESET _u(0x0) 1988 #define PADS_BANK0_GPIO27_PUE_BITS _u(0x00000008) 1989 #define PADS_BANK0_GPIO27_PUE_MSB _u(3) 1990 #define PADS_BANK0_GPIO27_PUE_LSB _u(3) 1991 #define PADS_BANK0_GPIO27_PUE_ACCESS "RW" 1992 // ----------------------------------------------------------------------------- 1993 // Field : PADS_BANK0_GPIO27_PDE 1994 // Description : Pull down enable 1995 #define PADS_BANK0_GPIO27_PDE_RESET _u(0x1) 1996 #define PADS_BANK0_GPIO27_PDE_BITS _u(0x00000004) 1997 #define PADS_BANK0_GPIO27_PDE_MSB _u(2) 1998 #define PADS_BANK0_GPIO27_PDE_LSB _u(2) 1999 #define PADS_BANK0_GPIO27_PDE_ACCESS "RW" 2000 // ----------------------------------------------------------------------------- 2001 // Field : PADS_BANK0_GPIO27_SCHMITT 2002 // Description : Enable schmitt trigger 2003 #define PADS_BANK0_GPIO27_SCHMITT_RESET _u(0x1) 2004 #define PADS_BANK0_GPIO27_SCHMITT_BITS _u(0x00000002) 2005 #define PADS_BANK0_GPIO27_SCHMITT_MSB _u(1) 2006 #define PADS_BANK0_GPIO27_SCHMITT_LSB _u(1) 2007 #define PADS_BANK0_GPIO27_SCHMITT_ACCESS "RW" 2008 // ----------------------------------------------------------------------------- 2009 // Field : PADS_BANK0_GPIO27_SLEWFAST 2010 // Description : Slew rate control. 1 = Fast, 0 = Slow 2011 #define PADS_BANK0_GPIO27_SLEWFAST_RESET _u(0x0) 2012 #define PADS_BANK0_GPIO27_SLEWFAST_BITS _u(0x00000001) 2013 #define PADS_BANK0_GPIO27_SLEWFAST_MSB _u(0) 2014 #define PADS_BANK0_GPIO27_SLEWFAST_LSB _u(0) 2015 #define PADS_BANK0_GPIO27_SLEWFAST_ACCESS "RW" 2016 // ============================================================================= 2017 // Register : PADS_BANK0_GPIO28 2018 // Description : Pad control register 2019 #define PADS_BANK0_GPIO28_OFFSET _u(0x00000074) 2020 #define PADS_BANK0_GPIO28_BITS _u(0x000000ff) 2021 #define PADS_BANK0_GPIO28_RESET _u(0x00000056) 2022 // ----------------------------------------------------------------------------- 2023 // Field : PADS_BANK0_GPIO28_OD 2024 // Description : Output disable. Has priority over output enable from 2025 // peripherals 2026 #define PADS_BANK0_GPIO28_OD_RESET _u(0x0) 2027 #define PADS_BANK0_GPIO28_OD_BITS _u(0x00000080) 2028 #define PADS_BANK0_GPIO28_OD_MSB _u(7) 2029 #define PADS_BANK0_GPIO28_OD_LSB _u(7) 2030 #define PADS_BANK0_GPIO28_OD_ACCESS "RW" 2031 // ----------------------------------------------------------------------------- 2032 // Field : PADS_BANK0_GPIO28_IE 2033 // Description : Input enable 2034 #define PADS_BANK0_GPIO28_IE_RESET _u(0x1) 2035 #define PADS_BANK0_GPIO28_IE_BITS _u(0x00000040) 2036 #define PADS_BANK0_GPIO28_IE_MSB _u(6) 2037 #define PADS_BANK0_GPIO28_IE_LSB _u(6) 2038 #define PADS_BANK0_GPIO28_IE_ACCESS "RW" 2039 // ----------------------------------------------------------------------------- 2040 // Field : PADS_BANK0_GPIO28_DRIVE 2041 // Description : Drive strength. 2042 // 0x0 -> 2mA 2043 // 0x1 -> 4mA 2044 // 0x2 -> 8mA 2045 // 0x3 -> 12mA 2046 #define PADS_BANK0_GPIO28_DRIVE_RESET _u(0x1) 2047 #define PADS_BANK0_GPIO28_DRIVE_BITS _u(0x00000030) 2048 #define PADS_BANK0_GPIO28_DRIVE_MSB _u(5) 2049 #define PADS_BANK0_GPIO28_DRIVE_LSB _u(4) 2050 #define PADS_BANK0_GPIO28_DRIVE_ACCESS "RW" 2051 #define PADS_BANK0_GPIO28_DRIVE_VALUE_2MA _u(0x0) 2052 #define PADS_BANK0_GPIO28_DRIVE_VALUE_4MA _u(0x1) 2053 #define PADS_BANK0_GPIO28_DRIVE_VALUE_8MA _u(0x2) 2054 #define PADS_BANK0_GPIO28_DRIVE_VALUE_12MA _u(0x3) 2055 // ----------------------------------------------------------------------------- 2056 // Field : PADS_BANK0_GPIO28_PUE 2057 // Description : Pull up enable 2058 #define PADS_BANK0_GPIO28_PUE_RESET _u(0x0) 2059 #define PADS_BANK0_GPIO28_PUE_BITS _u(0x00000008) 2060 #define PADS_BANK0_GPIO28_PUE_MSB _u(3) 2061 #define PADS_BANK0_GPIO28_PUE_LSB _u(3) 2062 #define PADS_BANK0_GPIO28_PUE_ACCESS "RW" 2063 // ----------------------------------------------------------------------------- 2064 // Field : PADS_BANK0_GPIO28_PDE 2065 // Description : Pull down enable 2066 #define PADS_BANK0_GPIO28_PDE_RESET _u(0x1) 2067 #define PADS_BANK0_GPIO28_PDE_BITS _u(0x00000004) 2068 #define PADS_BANK0_GPIO28_PDE_MSB _u(2) 2069 #define PADS_BANK0_GPIO28_PDE_LSB _u(2) 2070 #define PADS_BANK0_GPIO28_PDE_ACCESS "RW" 2071 // ----------------------------------------------------------------------------- 2072 // Field : PADS_BANK0_GPIO28_SCHMITT 2073 // Description : Enable schmitt trigger 2074 #define PADS_BANK0_GPIO28_SCHMITT_RESET _u(0x1) 2075 #define PADS_BANK0_GPIO28_SCHMITT_BITS _u(0x00000002) 2076 #define PADS_BANK0_GPIO28_SCHMITT_MSB _u(1) 2077 #define PADS_BANK0_GPIO28_SCHMITT_LSB _u(1) 2078 #define PADS_BANK0_GPIO28_SCHMITT_ACCESS "RW" 2079 // ----------------------------------------------------------------------------- 2080 // Field : PADS_BANK0_GPIO28_SLEWFAST 2081 // Description : Slew rate control. 1 = Fast, 0 = Slow 2082 #define PADS_BANK0_GPIO28_SLEWFAST_RESET _u(0x0) 2083 #define PADS_BANK0_GPIO28_SLEWFAST_BITS _u(0x00000001) 2084 #define PADS_BANK0_GPIO28_SLEWFAST_MSB _u(0) 2085 #define PADS_BANK0_GPIO28_SLEWFAST_LSB _u(0) 2086 #define PADS_BANK0_GPIO28_SLEWFAST_ACCESS "RW" 2087 // ============================================================================= 2088 // Register : PADS_BANK0_GPIO29 2089 // Description : Pad control register 2090 #define PADS_BANK0_GPIO29_OFFSET _u(0x00000078) 2091 #define PADS_BANK0_GPIO29_BITS _u(0x000000ff) 2092 #define PADS_BANK0_GPIO29_RESET _u(0x00000056) 2093 // ----------------------------------------------------------------------------- 2094 // Field : PADS_BANK0_GPIO29_OD 2095 // Description : Output disable. Has priority over output enable from 2096 // peripherals 2097 #define PADS_BANK0_GPIO29_OD_RESET _u(0x0) 2098 #define PADS_BANK0_GPIO29_OD_BITS _u(0x00000080) 2099 #define PADS_BANK0_GPIO29_OD_MSB _u(7) 2100 #define PADS_BANK0_GPIO29_OD_LSB _u(7) 2101 #define PADS_BANK0_GPIO29_OD_ACCESS "RW" 2102 // ----------------------------------------------------------------------------- 2103 // Field : PADS_BANK0_GPIO29_IE 2104 // Description : Input enable 2105 #define PADS_BANK0_GPIO29_IE_RESET _u(0x1) 2106 #define PADS_BANK0_GPIO29_IE_BITS _u(0x00000040) 2107 #define PADS_BANK0_GPIO29_IE_MSB _u(6) 2108 #define PADS_BANK0_GPIO29_IE_LSB _u(6) 2109 #define PADS_BANK0_GPIO29_IE_ACCESS "RW" 2110 // ----------------------------------------------------------------------------- 2111 // Field : PADS_BANK0_GPIO29_DRIVE 2112 // Description : Drive strength. 2113 // 0x0 -> 2mA 2114 // 0x1 -> 4mA 2115 // 0x2 -> 8mA 2116 // 0x3 -> 12mA 2117 #define PADS_BANK0_GPIO29_DRIVE_RESET _u(0x1) 2118 #define PADS_BANK0_GPIO29_DRIVE_BITS _u(0x00000030) 2119 #define PADS_BANK0_GPIO29_DRIVE_MSB _u(5) 2120 #define PADS_BANK0_GPIO29_DRIVE_LSB _u(4) 2121 #define PADS_BANK0_GPIO29_DRIVE_ACCESS "RW" 2122 #define PADS_BANK0_GPIO29_DRIVE_VALUE_2MA _u(0x0) 2123 #define PADS_BANK0_GPIO29_DRIVE_VALUE_4MA _u(0x1) 2124 #define PADS_BANK0_GPIO29_DRIVE_VALUE_8MA _u(0x2) 2125 #define PADS_BANK0_GPIO29_DRIVE_VALUE_12MA _u(0x3) 2126 // ----------------------------------------------------------------------------- 2127 // Field : PADS_BANK0_GPIO29_PUE 2128 // Description : Pull up enable 2129 #define PADS_BANK0_GPIO29_PUE_RESET _u(0x0) 2130 #define PADS_BANK0_GPIO29_PUE_BITS _u(0x00000008) 2131 #define PADS_BANK0_GPIO29_PUE_MSB _u(3) 2132 #define PADS_BANK0_GPIO29_PUE_LSB _u(3) 2133 #define PADS_BANK0_GPIO29_PUE_ACCESS "RW" 2134 // ----------------------------------------------------------------------------- 2135 // Field : PADS_BANK0_GPIO29_PDE 2136 // Description : Pull down enable 2137 #define PADS_BANK0_GPIO29_PDE_RESET _u(0x1) 2138 #define PADS_BANK0_GPIO29_PDE_BITS _u(0x00000004) 2139 #define PADS_BANK0_GPIO29_PDE_MSB _u(2) 2140 #define PADS_BANK0_GPIO29_PDE_LSB _u(2) 2141 #define PADS_BANK0_GPIO29_PDE_ACCESS "RW" 2142 // ----------------------------------------------------------------------------- 2143 // Field : PADS_BANK0_GPIO29_SCHMITT 2144 // Description : Enable schmitt trigger 2145 #define PADS_BANK0_GPIO29_SCHMITT_RESET _u(0x1) 2146 #define PADS_BANK0_GPIO29_SCHMITT_BITS _u(0x00000002) 2147 #define PADS_BANK0_GPIO29_SCHMITT_MSB _u(1) 2148 #define PADS_BANK0_GPIO29_SCHMITT_LSB _u(1) 2149 #define PADS_BANK0_GPIO29_SCHMITT_ACCESS "RW" 2150 // ----------------------------------------------------------------------------- 2151 // Field : PADS_BANK0_GPIO29_SLEWFAST 2152 // Description : Slew rate control. 1 = Fast, 0 = Slow 2153 #define PADS_BANK0_GPIO29_SLEWFAST_RESET _u(0x0) 2154 #define PADS_BANK0_GPIO29_SLEWFAST_BITS _u(0x00000001) 2155 #define PADS_BANK0_GPIO29_SLEWFAST_MSB _u(0) 2156 #define PADS_BANK0_GPIO29_SLEWFAST_LSB _u(0) 2157 #define PADS_BANK0_GPIO29_SLEWFAST_ACCESS "RW" 2158 // ============================================================================= 2159 // Register : PADS_BANK0_SWCLK 2160 // Description : Pad control register 2161 #define PADS_BANK0_SWCLK_OFFSET _u(0x0000007c) 2162 #define PADS_BANK0_SWCLK_BITS _u(0x000000ff) 2163 #define PADS_BANK0_SWCLK_RESET _u(0x000000da) 2164 // ----------------------------------------------------------------------------- 2165 // Field : PADS_BANK0_SWCLK_OD 2166 // Description : Output disable. Has priority over output enable from 2167 // peripherals 2168 #define PADS_BANK0_SWCLK_OD_RESET _u(0x1) 2169 #define PADS_BANK0_SWCLK_OD_BITS _u(0x00000080) 2170 #define PADS_BANK0_SWCLK_OD_MSB _u(7) 2171 #define PADS_BANK0_SWCLK_OD_LSB _u(7) 2172 #define PADS_BANK0_SWCLK_OD_ACCESS "RW" 2173 // ----------------------------------------------------------------------------- 2174 // Field : PADS_BANK0_SWCLK_IE 2175 // Description : Input enable 2176 #define PADS_BANK0_SWCLK_IE_RESET _u(0x1) 2177 #define PADS_BANK0_SWCLK_IE_BITS _u(0x00000040) 2178 #define PADS_BANK0_SWCLK_IE_MSB _u(6) 2179 #define PADS_BANK0_SWCLK_IE_LSB _u(6) 2180 #define PADS_BANK0_SWCLK_IE_ACCESS "RW" 2181 // ----------------------------------------------------------------------------- 2182 // Field : PADS_BANK0_SWCLK_DRIVE 2183 // Description : Drive strength. 2184 // 0x0 -> 2mA 2185 // 0x1 -> 4mA 2186 // 0x2 -> 8mA 2187 // 0x3 -> 12mA 2188 #define PADS_BANK0_SWCLK_DRIVE_RESET _u(0x1) 2189 #define PADS_BANK0_SWCLK_DRIVE_BITS _u(0x00000030) 2190 #define PADS_BANK0_SWCLK_DRIVE_MSB _u(5) 2191 #define PADS_BANK0_SWCLK_DRIVE_LSB _u(4) 2192 #define PADS_BANK0_SWCLK_DRIVE_ACCESS "RW" 2193 #define PADS_BANK0_SWCLK_DRIVE_VALUE_2MA _u(0x0) 2194 #define PADS_BANK0_SWCLK_DRIVE_VALUE_4MA _u(0x1) 2195 #define PADS_BANK0_SWCLK_DRIVE_VALUE_8MA _u(0x2) 2196 #define PADS_BANK0_SWCLK_DRIVE_VALUE_12MA _u(0x3) 2197 // ----------------------------------------------------------------------------- 2198 // Field : PADS_BANK0_SWCLK_PUE 2199 // Description : Pull up enable 2200 #define PADS_BANK0_SWCLK_PUE_RESET _u(0x1) 2201 #define PADS_BANK0_SWCLK_PUE_BITS _u(0x00000008) 2202 #define PADS_BANK0_SWCLK_PUE_MSB _u(3) 2203 #define PADS_BANK0_SWCLK_PUE_LSB _u(3) 2204 #define PADS_BANK0_SWCLK_PUE_ACCESS "RW" 2205 // ----------------------------------------------------------------------------- 2206 // Field : PADS_BANK0_SWCLK_PDE 2207 // Description : Pull down enable 2208 #define PADS_BANK0_SWCLK_PDE_RESET _u(0x0) 2209 #define PADS_BANK0_SWCLK_PDE_BITS _u(0x00000004) 2210 #define PADS_BANK0_SWCLK_PDE_MSB _u(2) 2211 #define PADS_BANK0_SWCLK_PDE_LSB _u(2) 2212 #define PADS_BANK0_SWCLK_PDE_ACCESS "RW" 2213 // ----------------------------------------------------------------------------- 2214 // Field : PADS_BANK0_SWCLK_SCHMITT 2215 // Description : Enable schmitt trigger 2216 #define PADS_BANK0_SWCLK_SCHMITT_RESET _u(0x1) 2217 #define PADS_BANK0_SWCLK_SCHMITT_BITS _u(0x00000002) 2218 #define PADS_BANK0_SWCLK_SCHMITT_MSB _u(1) 2219 #define PADS_BANK0_SWCLK_SCHMITT_LSB _u(1) 2220 #define PADS_BANK0_SWCLK_SCHMITT_ACCESS "RW" 2221 // ----------------------------------------------------------------------------- 2222 // Field : PADS_BANK0_SWCLK_SLEWFAST 2223 // Description : Slew rate control. 1 = Fast, 0 = Slow 2224 #define PADS_BANK0_SWCLK_SLEWFAST_RESET _u(0x0) 2225 #define PADS_BANK0_SWCLK_SLEWFAST_BITS _u(0x00000001) 2226 #define PADS_BANK0_SWCLK_SLEWFAST_MSB _u(0) 2227 #define PADS_BANK0_SWCLK_SLEWFAST_LSB _u(0) 2228 #define PADS_BANK0_SWCLK_SLEWFAST_ACCESS "RW" 2229 // ============================================================================= 2230 // Register : PADS_BANK0_SWD 2231 // Description : Pad control register 2232 #define PADS_BANK0_SWD_OFFSET _u(0x00000080) 2233 #define PADS_BANK0_SWD_BITS _u(0x000000ff) 2234 #define PADS_BANK0_SWD_RESET _u(0x0000005a) 2235 // ----------------------------------------------------------------------------- 2236 // Field : PADS_BANK0_SWD_OD 2237 // Description : Output disable. Has priority over output enable from 2238 // peripherals 2239 #define PADS_BANK0_SWD_OD_RESET _u(0x0) 2240 #define PADS_BANK0_SWD_OD_BITS _u(0x00000080) 2241 #define PADS_BANK0_SWD_OD_MSB _u(7) 2242 #define PADS_BANK0_SWD_OD_LSB _u(7) 2243 #define PADS_BANK0_SWD_OD_ACCESS "RW" 2244 // ----------------------------------------------------------------------------- 2245 // Field : PADS_BANK0_SWD_IE 2246 // Description : Input enable 2247 #define PADS_BANK0_SWD_IE_RESET _u(0x1) 2248 #define PADS_BANK0_SWD_IE_BITS _u(0x00000040) 2249 #define PADS_BANK0_SWD_IE_MSB _u(6) 2250 #define PADS_BANK0_SWD_IE_LSB _u(6) 2251 #define PADS_BANK0_SWD_IE_ACCESS "RW" 2252 // ----------------------------------------------------------------------------- 2253 // Field : PADS_BANK0_SWD_DRIVE 2254 // Description : Drive strength. 2255 // 0x0 -> 2mA 2256 // 0x1 -> 4mA 2257 // 0x2 -> 8mA 2258 // 0x3 -> 12mA 2259 #define PADS_BANK0_SWD_DRIVE_RESET _u(0x1) 2260 #define PADS_BANK0_SWD_DRIVE_BITS _u(0x00000030) 2261 #define PADS_BANK0_SWD_DRIVE_MSB _u(5) 2262 #define PADS_BANK0_SWD_DRIVE_LSB _u(4) 2263 #define PADS_BANK0_SWD_DRIVE_ACCESS "RW" 2264 #define PADS_BANK0_SWD_DRIVE_VALUE_2MA _u(0x0) 2265 #define PADS_BANK0_SWD_DRIVE_VALUE_4MA _u(0x1) 2266 #define PADS_BANK0_SWD_DRIVE_VALUE_8MA _u(0x2) 2267 #define PADS_BANK0_SWD_DRIVE_VALUE_12MA _u(0x3) 2268 // ----------------------------------------------------------------------------- 2269 // Field : PADS_BANK0_SWD_PUE 2270 // Description : Pull up enable 2271 #define PADS_BANK0_SWD_PUE_RESET _u(0x1) 2272 #define PADS_BANK0_SWD_PUE_BITS _u(0x00000008) 2273 #define PADS_BANK0_SWD_PUE_MSB _u(3) 2274 #define PADS_BANK0_SWD_PUE_LSB _u(3) 2275 #define PADS_BANK0_SWD_PUE_ACCESS "RW" 2276 // ----------------------------------------------------------------------------- 2277 // Field : PADS_BANK0_SWD_PDE 2278 // Description : Pull down enable 2279 #define PADS_BANK0_SWD_PDE_RESET _u(0x0) 2280 #define PADS_BANK0_SWD_PDE_BITS _u(0x00000004) 2281 #define PADS_BANK0_SWD_PDE_MSB _u(2) 2282 #define PADS_BANK0_SWD_PDE_LSB _u(2) 2283 #define PADS_BANK0_SWD_PDE_ACCESS "RW" 2284 // ----------------------------------------------------------------------------- 2285 // Field : PADS_BANK0_SWD_SCHMITT 2286 // Description : Enable schmitt trigger 2287 #define PADS_BANK0_SWD_SCHMITT_RESET _u(0x1) 2288 #define PADS_BANK0_SWD_SCHMITT_BITS _u(0x00000002) 2289 #define PADS_BANK0_SWD_SCHMITT_MSB _u(1) 2290 #define PADS_BANK0_SWD_SCHMITT_LSB _u(1) 2291 #define PADS_BANK0_SWD_SCHMITT_ACCESS "RW" 2292 // ----------------------------------------------------------------------------- 2293 // Field : PADS_BANK0_SWD_SLEWFAST 2294 // Description : Slew rate control. 1 = Fast, 0 = Slow 2295 #define PADS_BANK0_SWD_SLEWFAST_RESET _u(0x0) 2296 #define PADS_BANK0_SWD_SLEWFAST_BITS _u(0x00000001) 2297 #define PADS_BANK0_SWD_SLEWFAST_MSB _u(0) 2298 #define PADS_BANK0_SWD_SLEWFAST_LSB _u(0) 2299 #define PADS_BANK0_SWD_SLEWFAST_ACCESS "RW" 2300 // ============================================================================= 2301 #endif // _HARDWARE_REGS_PADS_BANK0_H 2302 2303
