1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT 2 3 /** 4 * Copyright (c) 2024 Raspberry Pi Ltd. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 // ============================================================================= 9 // Register block : IO_BANK0 10 // Version : 1 11 // Bus type : apb 12 // ============================================================================= 13 #ifndef _HARDWARE_REGS_IO_BANK0_H 14 #define _HARDWARE_REGS_IO_BANK0_H 15 // ============================================================================= 16 // Register : IO_BANK0_GPIO0_STATUS 17 // Description : GPIO status 18 #define IO_BANK0_GPIO0_STATUS_OFFSET _u(0x00000000) 19 #define IO_BANK0_GPIO0_STATUS_BITS _u(0x050a3300) 20 #define IO_BANK0_GPIO0_STATUS_RESET _u(0x00000000) 21 // ----------------------------------------------------------------------------- 22 // Field : IO_BANK0_GPIO0_STATUS_IRQTOPROC 23 // Description : interrupt to processors, after override is applied 24 #define IO_BANK0_GPIO0_STATUS_IRQTOPROC_RESET _u(0x0) 25 #define IO_BANK0_GPIO0_STATUS_IRQTOPROC_BITS _u(0x04000000) 26 #define IO_BANK0_GPIO0_STATUS_IRQTOPROC_MSB _u(26) 27 #define IO_BANK0_GPIO0_STATUS_IRQTOPROC_LSB _u(26) 28 #define IO_BANK0_GPIO0_STATUS_IRQTOPROC_ACCESS "RO" 29 // ----------------------------------------------------------------------------- 30 // Field : IO_BANK0_GPIO0_STATUS_IRQFROMPAD 31 // Description : interrupt from pad before override is applied 32 #define IO_BANK0_GPIO0_STATUS_IRQFROMPAD_RESET _u(0x0) 33 #define IO_BANK0_GPIO0_STATUS_IRQFROMPAD_BITS _u(0x01000000) 34 #define IO_BANK0_GPIO0_STATUS_IRQFROMPAD_MSB _u(24) 35 #define IO_BANK0_GPIO0_STATUS_IRQFROMPAD_LSB _u(24) 36 #define IO_BANK0_GPIO0_STATUS_IRQFROMPAD_ACCESS "RO" 37 // ----------------------------------------------------------------------------- 38 // Field : IO_BANK0_GPIO0_STATUS_INTOPERI 39 // Description : input signal to peripheral, after override is applied 40 #define IO_BANK0_GPIO0_STATUS_INTOPERI_RESET _u(0x0) 41 #define IO_BANK0_GPIO0_STATUS_INTOPERI_BITS _u(0x00080000) 42 #define IO_BANK0_GPIO0_STATUS_INTOPERI_MSB _u(19) 43 #define IO_BANK0_GPIO0_STATUS_INTOPERI_LSB _u(19) 44 #define IO_BANK0_GPIO0_STATUS_INTOPERI_ACCESS "RO" 45 // ----------------------------------------------------------------------------- 46 // Field : IO_BANK0_GPIO0_STATUS_INFROMPAD 47 // Description : input signal from pad, before override is applied 48 #define IO_BANK0_GPIO0_STATUS_INFROMPAD_RESET _u(0x0) 49 #define IO_BANK0_GPIO0_STATUS_INFROMPAD_BITS _u(0x00020000) 50 #define IO_BANK0_GPIO0_STATUS_INFROMPAD_MSB _u(17) 51 #define IO_BANK0_GPIO0_STATUS_INFROMPAD_LSB _u(17) 52 #define IO_BANK0_GPIO0_STATUS_INFROMPAD_ACCESS "RO" 53 // ----------------------------------------------------------------------------- 54 // Field : IO_BANK0_GPIO0_STATUS_OETOPAD 55 // Description : output enable to pad after register override is applied 56 #define IO_BANK0_GPIO0_STATUS_OETOPAD_RESET _u(0x0) 57 #define IO_BANK0_GPIO0_STATUS_OETOPAD_BITS _u(0x00002000) 58 #define IO_BANK0_GPIO0_STATUS_OETOPAD_MSB _u(13) 59 #define IO_BANK0_GPIO0_STATUS_OETOPAD_LSB _u(13) 60 #define IO_BANK0_GPIO0_STATUS_OETOPAD_ACCESS "RO" 61 // ----------------------------------------------------------------------------- 62 // Field : IO_BANK0_GPIO0_STATUS_OEFROMPERI 63 // Description : output enable from selected peripheral, before register 64 // override is applied 65 #define IO_BANK0_GPIO0_STATUS_OEFROMPERI_RESET _u(0x0) 66 #define IO_BANK0_GPIO0_STATUS_OEFROMPERI_BITS _u(0x00001000) 67 #define IO_BANK0_GPIO0_STATUS_OEFROMPERI_MSB _u(12) 68 #define IO_BANK0_GPIO0_STATUS_OEFROMPERI_LSB _u(12) 69 #define IO_BANK0_GPIO0_STATUS_OEFROMPERI_ACCESS "RO" 70 // ----------------------------------------------------------------------------- 71 // Field : IO_BANK0_GPIO0_STATUS_OUTTOPAD 72 // Description : output signal to pad after register override is applied 73 #define IO_BANK0_GPIO0_STATUS_OUTTOPAD_RESET _u(0x0) 74 #define IO_BANK0_GPIO0_STATUS_OUTTOPAD_BITS _u(0x00000200) 75 #define IO_BANK0_GPIO0_STATUS_OUTTOPAD_MSB _u(9) 76 #define IO_BANK0_GPIO0_STATUS_OUTTOPAD_LSB _u(9) 77 #define IO_BANK0_GPIO0_STATUS_OUTTOPAD_ACCESS "RO" 78 // ----------------------------------------------------------------------------- 79 // Field : IO_BANK0_GPIO0_STATUS_OUTFROMPERI 80 // Description : output signal from selected peripheral, before register 81 // override is applied 82 #define IO_BANK0_GPIO0_STATUS_OUTFROMPERI_RESET _u(0x0) 83 #define IO_BANK0_GPIO0_STATUS_OUTFROMPERI_BITS _u(0x00000100) 84 #define IO_BANK0_GPIO0_STATUS_OUTFROMPERI_MSB _u(8) 85 #define IO_BANK0_GPIO0_STATUS_OUTFROMPERI_LSB _u(8) 86 #define IO_BANK0_GPIO0_STATUS_OUTFROMPERI_ACCESS "RO" 87 // ============================================================================= 88 // Register : IO_BANK0_GPIO0_CTRL 89 // Description : GPIO control including function select and overrides. 90 #define IO_BANK0_GPIO0_CTRL_OFFSET _u(0x00000004) 91 #define IO_BANK0_GPIO0_CTRL_BITS _u(0x3003331f) 92 #define IO_BANK0_GPIO0_CTRL_RESET _u(0x0000001f) 93 // ----------------------------------------------------------------------------- 94 // Field : IO_BANK0_GPIO0_CTRL_IRQOVER 95 // 0x0 -> don't invert the interrupt 96 // 0x1 -> invert the interrupt 97 // 0x2 -> drive interrupt low 98 // 0x3 -> drive interrupt high 99 #define IO_BANK0_GPIO0_CTRL_IRQOVER_RESET _u(0x0) 100 #define IO_BANK0_GPIO0_CTRL_IRQOVER_BITS _u(0x30000000) 101 #define IO_BANK0_GPIO0_CTRL_IRQOVER_MSB _u(29) 102 #define IO_BANK0_GPIO0_CTRL_IRQOVER_LSB _u(28) 103 #define IO_BANK0_GPIO0_CTRL_IRQOVER_ACCESS "RW" 104 #define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) 105 #define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_INVERT _u(0x1) 106 #define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_LOW _u(0x2) 107 #define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_HIGH _u(0x3) 108 // ----------------------------------------------------------------------------- 109 // Field : IO_BANK0_GPIO0_CTRL_INOVER 110 // 0x0 -> don't invert the peri input 111 // 0x1 -> invert the peri input 112 // 0x2 -> drive peri input low 113 // 0x3 -> drive peri input high 114 #define IO_BANK0_GPIO0_CTRL_INOVER_RESET _u(0x0) 115 #define IO_BANK0_GPIO0_CTRL_INOVER_BITS _u(0x00030000) 116 #define IO_BANK0_GPIO0_CTRL_INOVER_MSB _u(17) 117 #define IO_BANK0_GPIO0_CTRL_INOVER_LSB _u(16) 118 #define IO_BANK0_GPIO0_CTRL_INOVER_ACCESS "RW" 119 #define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_NORMAL _u(0x0) 120 #define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_INVERT _u(0x1) 121 #define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_LOW _u(0x2) 122 #define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_HIGH _u(0x3) 123 // ----------------------------------------------------------------------------- 124 // Field : IO_BANK0_GPIO0_CTRL_OEOVER 125 // 0x0 -> drive output enable from peripheral signal selected by funcsel 126 // 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel 127 // 0x2 -> disable output 128 // 0x3 -> enable output 129 #define IO_BANK0_GPIO0_CTRL_OEOVER_RESET _u(0x0) 130 #define IO_BANK0_GPIO0_CTRL_OEOVER_BITS _u(0x00003000) 131 #define IO_BANK0_GPIO0_CTRL_OEOVER_MSB _u(13) 132 #define IO_BANK0_GPIO0_CTRL_OEOVER_LSB _u(12) 133 #define IO_BANK0_GPIO0_CTRL_OEOVER_ACCESS "RW" 134 #define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_NORMAL _u(0x0) 135 #define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_INVERT _u(0x1) 136 #define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_DISABLE _u(0x2) 137 #define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_ENABLE _u(0x3) 138 // ----------------------------------------------------------------------------- 139 // Field : IO_BANK0_GPIO0_CTRL_OUTOVER 140 // 0x0 -> drive output from peripheral signal selected by funcsel 141 // 0x1 -> drive output from inverse of peripheral signal selected by funcsel 142 // 0x2 -> drive output low 143 // 0x3 -> drive output high 144 #define IO_BANK0_GPIO0_CTRL_OUTOVER_RESET _u(0x0) 145 #define IO_BANK0_GPIO0_CTRL_OUTOVER_BITS _u(0x00000300) 146 #define IO_BANK0_GPIO0_CTRL_OUTOVER_MSB _u(9) 147 #define IO_BANK0_GPIO0_CTRL_OUTOVER_LSB _u(8) 148 #define IO_BANK0_GPIO0_CTRL_OUTOVER_ACCESS "RW" 149 #define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) 150 #define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_INVERT _u(0x1) 151 #define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_LOW _u(0x2) 152 #define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_HIGH _u(0x3) 153 // ----------------------------------------------------------------------------- 154 // Field : IO_BANK0_GPIO0_CTRL_FUNCSEL 155 // Description : 0-31 -> selects pin function according to the gpio table 156 // 31 == NULL 157 // 0x00 -> jtag_tck 158 // 0x01 -> spi0_rx 159 // 0x02 -> uart0_tx 160 // 0x03 -> i2c0_sda 161 // 0x04 -> pwm_a_0 162 // 0x05 -> sio_0 163 // 0x06 -> pio0_0 164 // 0x07 -> pio1_0 165 // 0x09 -> usb_muxing_overcurr_detect 166 // 0x1f -> null 167 #define IO_BANK0_GPIO0_CTRL_FUNCSEL_RESET _u(0x1f) 168 #define IO_BANK0_GPIO0_CTRL_FUNCSEL_BITS _u(0x0000001f) 169 #define IO_BANK0_GPIO0_CTRL_FUNCSEL_MSB _u(4) 170 #define IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB _u(0) 171 #define IO_BANK0_GPIO0_CTRL_FUNCSEL_ACCESS "RW" 172 #define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_JTAG_TCK _u(0x00) 173 #define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_SPI0_RX _u(0x01) 174 #define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x02) 175 #define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) 176 #define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_PWM_A_0 _u(0x04) 177 #define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_SIO_0 _u(0x05) 178 #define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_PIO0_0 _u(0x06) 179 #define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_PIO1_0 _u(0x07) 180 #define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09) 181 #define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) 182 // ============================================================================= 183 // Register : IO_BANK0_GPIO1_STATUS 184 // Description : GPIO status 185 #define IO_BANK0_GPIO1_STATUS_OFFSET _u(0x00000008) 186 #define IO_BANK0_GPIO1_STATUS_BITS _u(0x050a3300) 187 #define IO_BANK0_GPIO1_STATUS_RESET _u(0x00000000) 188 // ----------------------------------------------------------------------------- 189 // Field : IO_BANK0_GPIO1_STATUS_IRQTOPROC 190 // Description : interrupt to processors, after override is applied 191 #define IO_BANK0_GPIO1_STATUS_IRQTOPROC_RESET _u(0x0) 192 #define IO_BANK0_GPIO1_STATUS_IRQTOPROC_BITS _u(0x04000000) 193 #define IO_BANK0_GPIO1_STATUS_IRQTOPROC_MSB _u(26) 194 #define IO_BANK0_GPIO1_STATUS_IRQTOPROC_LSB _u(26) 195 #define IO_BANK0_GPIO1_STATUS_IRQTOPROC_ACCESS "RO" 196 // ----------------------------------------------------------------------------- 197 // Field : IO_BANK0_GPIO1_STATUS_IRQFROMPAD 198 // Description : interrupt from pad before override is applied 199 #define IO_BANK0_GPIO1_STATUS_IRQFROMPAD_RESET _u(0x0) 200 #define IO_BANK0_GPIO1_STATUS_IRQFROMPAD_BITS _u(0x01000000) 201 #define IO_BANK0_GPIO1_STATUS_IRQFROMPAD_MSB _u(24) 202 #define IO_BANK0_GPIO1_STATUS_IRQFROMPAD_LSB _u(24) 203 #define IO_BANK0_GPIO1_STATUS_IRQFROMPAD_ACCESS "RO" 204 // ----------------------------------------------------------------------------- 205 // Field : IO_BANK0_GPIO1_STATUS_INTOPERI 206 // Description : input signal to peripheral, after override is applied 207 #define IO_BANK0_GPIO1_STATUS_INTOPERI_RESET _u(0x0) 208 #define IO_BANK0_GPIO1_STATUS_INTOPERI_BITS _u(0x00080000) 209 #define IO_BANK0_GPIO1_STATUS_INTOPERI_MSB _u(19) 210 #define IO_BANK0_GPIO1_STATUS_INTOPERI_LSB _u(19) 211 #define IO_BANK0_GPIO1_STATUS_INTOPERI_ACCESS "RO" 212 // ----------------------------------------------------------------------------- 213 // Field : IO_BANK0_GPIO1_STATUS_INFROMPAD 214 // Description : input signal from pad, before override is applied 215 #define IO_BANK0_GPIO1_STATUS_INFROMPAD_RESET _u(0x0) 216 #define IO_BANK0_GPIO1_STATUS_INFROMPAD_BITS _u(0x00020000) 217 #define IO_BANK0_GPIO1_STATUS_INFROMPAD_MSB _u(17) 218 #define IO_BANK0_GPIO1_STATUS_INFROMPAD_LSB _u(17) 219 #define IO_BANK0_GPIO1_STATUS_INFROMPAD_ACCESS "RO" 220 // ----------------------------------------------------------------------------- 221 // Field : IO_BANK0_GPIO1_STATUS_OETOPAD 222 // Description : output enable to pad after register override is applied 223 #define IO_BANK0_GPIO1_STATUS_OETOPAD_RESET _u(0x0) 224 #define IO_BANK0_GPIO1_STATUS_OETOPAD_BITS _u(0x00002000) 225 #define IO_BANK0_GPIO1_STATUS_OETOPAD_MSB _u(13) 226 #define IO_BANK0_GPIO1_STATUS_OETOPAD_LSB _u(13) 227 #define IO_BANK0_GPIO1_STATUS_OETOPAD_ACCESS "RO" 228 // ----------------------------------------------------------------------------- 229 // Field : IO_BANK0_GPIO1_STATUS_OEFROMPERI 230 // Description : output enable from selected peripheral, before register 231 // override is applied 232 #define IO_BANK0_GPIO1_STATUS_OEFROMPERI_RESET _u(0x0) 233 #define IO_BANK0_GPIO1_STATUS_OEFROMPERI_BITS _u(0x00001000) 234 #define IO_BANK0_GPIO1_STATUS_OEFROMPERI_MSB _u(12) 235 #define IO_BANK0_GPIO1_STATUS_OEFROMPERI_LSB _u(12) 236 #define IO_BANK0_GPIO1_STATUS_OEFROMPERI_ACCESS "RO" 237 // ----------------------------------------------------------------------------- 238 // Field : IO_BANK0_GPIO1_STATUS_OUTTOPAD 239 // Description : output signal to pad after register override is applied 240 #define IO_BANK0_GPIO1_STATUS_OUTTOPAD_RESET _u(0x0) 241 #define IO_BANK0_GPIO1_STATUS_OUTTOPAD_BITS _u(0x00000200) 242 #define IO_BANK0_GPIO1_STATUS_OUTTOPAD_MSB _u(9) 243 #define IO_BANK0_GPIO1_STATUS_OUTTOPAD_LSB _u(9) 244 #define IO_BANK0_GPIO1_STATUS_OUTTOPAD_ACCESS "RO" 245 // ----------------------------------------------------------------------------- 246 // Field : IO_BANK0_GPIO1_STATUS_OUTFROMPERI 247 // Description : output signal from selected peripheral, before register 248 // override is applied 249 #define IO_BANK0_GPIO1_STATUS_OUTFROMPERI_RESET _u(0x0) 250 #define IO_BANK0_GPIO1_STATUS_OUTFROMPERI_BITS _u(0x00000100) 251 #define IO_BANK0_GPIO1_STATUS_OUTFROMPERI_MSB _u(8) 252 #define IO_BANK0_GPIO1_STATUS_OUTFROMPERI_LSB _u(8) 253 #define IO_BANK0_GPIO1_STATUS_OUTFROMPERI_ACCESS "RO" 254 // ============================================================================= 255 // Register : IO_BANK0_GPIO1_CTRL 256 // Description : GPIO control including function select and overrides. 257 #define IO_BANK0_GPIO1_CTRL_OFFSET _u(0x0000000c) 258 #define IO_BANK0_GPIO1_CTRL_BITS _u(0x3003331f) 259 #define IO_BANK0_GPIO1_CTRL_RESET _u(0x0000001f) 260 // ----------------------------------------------------------------------------- 261 // Field : IO_BANK0_GPIO1_CTRL_IRQOVER 262 // 0x0 -> don't invert the interrupt 263 // 0x1 -> invert the interrupt 264 // 0x2 -> drive interrupt low 265 // 0x3 -> drive interrupt high 266 #define IO_BANK0_GPIO1_CTRL_IRQOVER_RESET _u(0x0) 267 #define IO_BANK0_GPIO1_CTRL_IRQOVER_BITS _u(0x30000000) 268 #define IO_BANK0_GPIO1_CTRL_IRQOVER_MSB _u(29) 269 #define IO_BANK0_GPIO1_CTRL_IRQOVER_LSB _u(28) 270 #define IO_BANK0_GPIO1_CTRL_IRQOVER_ACCESS "RW" 271 #define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) 272 #define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_INVERT _u(0x1) 273 #define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_LOW _u(0x2) 274 #define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_HIGH _u(0x3) 275 // ----------------------------------------------------------------------------- 276 // Field : IO_BANK0_GPIO1_CTRL_INOVER 277 // 0x0 -> don't invert the peri input 278 // 0x1 -> invert the peri input 279 // 0x2 -> drive peri input low 280 // 0x3 -> drive peri input high 281 #define IO_BANK0_GPIO1_CTRL_INOVER_RESET _u(0x0) 282 #define IO_BANK0_GPIO1_CTRL_INOVER_BITS _u(0x00030000) 283 #define IO_BANK0_GPIO1_CTRL_INOVER_MSB _u(17) 284 #define IO_BANK0_GPIO1_CTRL_INOVER_LSB _u(16) 285 #define IO_BANK0_GPIO1_CTRL_INOVER_ACCESS "RW" 286 #define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_NORMAL _u(0x0) 287 #define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_INVERT _u(0x1) 288 #define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_LOW _u(0x2) 289 #define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_HIGH _u(0x3) 290 // ----------------------------------------------------------------------------- 291 // Field : IO_BANK0_GPIO1_CTRL_OEOVER 292 // 0x0 -> drive output enable from peripheral signal selected by funcsel 293 // 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel 294 // 0x2 -> disable output 295 // 0x3 -> enable output 296 #define IO_BANK0_GPIO1_CTRL_OEOVER_RESET _u(0x0) 297 #define IO_BANK0_GPIO1_CTRL_OEOVER_BITS _u(0x00003000) 298 #define IO_BANK0_GPIO1_CTRL_OEOVER_MSB _u(13) 299 #define IO_BANK0_GPIO1_CTRL_OEOVER_LSB _u(12) 300 #define IO_BANK0_GPIO1_CTRL_OEOVER_ACCESS "RW" 301 #define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_NORMAL _u(0x0) 302 #define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_INVERT _u(0x1) 303 #define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_DISABLE _u(0x2) 304 #define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_ENABLE _u(0x3) 305 // ----------------------------------------------------------------------------- 306 // Field : IO_BANK0_GPIO1_CTRL_OUTOVER 307 // 0x0 -> drive output from peripheral signal selected by funcsel 308 // 0x1 -> drive output from inverse of peripheral signal selected by funcsel 309 // 0x2 -> drive output low 310 // 0x3 -> drive output high 311 #define IO_BANK0_GPIO1_CTRL_OUTOVER_RESET _u(0x0) 312 #define IO_BANK0_GPIO1_CTRL_OUTOVER_BITS _u(0x00000300) 313 #define IO_BANK0_GPIO1_CTRL_OUTOVER_MSB _u(9) 314 #define IO_BANK0_GPIO1_CTRL_OUTOVER_LSB _u(8) 315 #define IO_BANK0_GPIO1_CTRL_OUTOVER_ACCESS "RW" 316 #define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) 317 #define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_INVERT _u(0x1) 318 #define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_LOW _u(0x2) 319 #define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_HIGH _u(0x3) 320 // ----------------------------------------------------------------------------- 321 // Field : IO_BANK0_GPIO1_CTRL_FUNCSEL 322 // Description : 0-31 -> selects pin function according to the gpio table 323 // 31 == NULL 324 // 0x00 -> jtag_tms 325 // 0x01 -> spi0_ss_n 326 // 0x02 -> uart0_rx 327 // 0x03 -> i2c0_scl 328 // 0x04 -> pwm_b_0 329 // 0x05 -> sio_1 330 // 0x06 -> pio0_1 331 // 0x07 -> pio1_1 332 // 0x09 -> usb_muxing_vbus_detect 333 // 0x1f -> null 334 #define IO_BANK0_GPIO1_CTRL_FUNCSEL_RESET _u(0x1f) 335 #define IO_BANK0_GPIO1_CTRL_FUNCSEL_BITS _u(0x0000001f) 336 #define IO_BANK0_GPIO1_CTRL_FUNCSEL_MSB _u(4) 337 #define IO_BANK0_GPIO1_CTRL_FUNCSEL_LSB _u(0) 338 #define IO_BANK0_GPIO1_CTRL_FUNCSEL_ACCESS "RW" 339 #define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_JTAG_TMS _u(0x00) 340 #define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_SPI0_SS_N _u(0x01) 341 #define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x02) 342 #define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) 343 #define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_PWM_B_0 _u(0x04) 344 #define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_SIO_1 _u(0x05) 345 #define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_PIO0_1 _u(0x06) 346 #define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_PIO1_1 _u(0x07) 347 #define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09) 348 #define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) 349 // ============================================================================= 350 // Register : IO_BANK0_GPIO2_STATUS 351 // Description : GPIO status 352 #define IO_BANK0_GPIO2_STATUS_OFFSET _u(0x00000010) 353 #define IO_BANK0_GPIO2_STATUS_BITS _u(0x050a3300) 354 #define IO_BANK0_GPIO2_STATUS_RESET _u(0x00000000) 355 // ----------------------------------------------------------------------------- 356 // Field : IO_BANK0_GPIO2_STATUS_IRQTOPROC 357 // Description : interrupt to processors, after override is applied 358 #define IO_BANK0_GPIO2_STATUS_IRQTOPROC_RESET _u(0x0) 359 #define IO_BANK0_GPIO2_STATUS_IRQTOPROC_BITS _u(0x04000000) 360 #define IO_BANK0_GPIO2_STATUS_IRQTOPROC_MSB _u(26) 361 #define IO_BANK0_GPIO2_STATUS_IRQTOPROC_LSB _u(26) 362 #define IO_BANK0_GPIO2_STATUS_IRQTOPROC_ACCESS "RO" 363 // ----------------------------------------------------------------------------- 364 // Field : IO_BANK0_GPIO2_STATUS_IRQFROMPAD 365 // Description : interrupt from pad before override is applied 366 #define IO_BANK0_GPIO2_STATUS_IRQFROMPAD_RESET _u(0x0) 367 #define IO_BANK0_GPIO2_STATUS_IRQFROMPAD_BITS _u(0x01000000) 368 #define IO_BANK0_GPIO2_STATUS_IRQFROMPAD_MSB _u(24) 369 #define IO_BANK0_GPIO2_STATUS_IRQFROMPAD_LSB _u(24) 370 #define IO_BANK0_GPIO2_STATUS_IRQFROMPAD_ACCESS "RO" 371 // ----------------------------------------------------------------------------- 372 // Field : IO_BANK0_GPIO2_STATUS_INTOPERI 373 // Description : input signal to peripheral, after override is applied 374 #define IO_BANK0_GPIO2_STATUS_INTOPERI_RESET _u(0x0) 375 #define IO_BANK0_GPIO2_STATUS_INTOPERI_BITS _u(0x00080000) 376 #define IO_BANK0_GPIO2_STATUS_INTOPERI_MSB _u(19) 377 #define IO_BANK0_GPIO2_STATUS_INTOPERI_LSB _u(19) 378 #define IO_BANK0_GPIO2_STATUS_INTOPERI_ACCESS "RO" 379 // ----------------------------------------------------------------------------- 380 // Field : IO_BANK0_GPIO2_STATUS_INFROMPAD 381 // Description : input signal from pad, before override is applied 382 #define IO_BANK0_GPIO2_STATUS_INFROMPAD_RESET _u(0x0) 383 #define IO_BANK0_GPIO2_STATUS_INFROMPAD_BITS _u(0x00020000) 384 #define IO_BANK0_GPIO2_STATUS_INFROMPAD_MSB _u(17) 385 #define IO_BANK0_GPIO2_STATUS_INFROMPAD_LSB _u(17) 386 #define IO_BANK0_GPIO2_STATUS_INFROMPAD_ACCESS "RO" 387 // ----------------------------------------------------------------------------- 388 // Field : IO_BANK0_GPIO2_STATUS_OETOPAD 389 // Description : output enable to pad after register override is applied 390 #define IO_BANK0_GPIO2_STATUS_OETOPAD_RESET _u(0x0) 391 #define IO_BANK0_GPIO2_STATUS_OETOPAD_BITS _u(0x00002000) 392 #define IO_BANK0_GPIO2_STATUS_OETOPAD_MSB _u(13) 393 #define IO_BANK0_GPIO2_STATUS_OETOPAD_LSB _u(13) 394 #define IO_BANK0_GPIO2_STATUS_OETOPAD_ACCESS "RO" 395 // ----------------------------------------------------------------------------- 396 // Field : IO_BANK0_GPIO2_STATUS_OEFROMPERI 397 // Description : output enable from selected peripheral, before register 398 // override is applied 399 #define IO_BANK0_GPIO2_STATUS_OEFROMPERI_RESET _u(0x0) 400 #define IO_BANK0_GPIO2_STATUS_OEFROMPERI_BITS _u(0x00001000) 401 #define IO_BANK0_GPIO2_STATUS_OEFROMPERI_MSB _u(12) 402 #define IO_BANK0_GPIO2_STATUS_OEFROMPERI_LSB _u(12) 403 #define IO_BANK0_GPIO2_STATUS_OEFROMPERI_ACCESS "RO" 404 // ----------------------------------------------------------------------------- 405 // Field : IO_BANK0_GPIO2_STATUS_OUTTOPAD 406 // Description : output signal to pad after register override is applied 407 #define IO_BANK0_GPIO2_STATUS_OUTTOPAD_RESET _u(0x0) 408 #define IO_BANK0_GPIO2_STATUS_OUTTOPAD_BITS _u(0x00000200) 409 #define IO_BANK0_GPIO2_STATUS_OUTTOPAD_MSB _u(9) 410 #define IO_BANK0_GPIO2_STATUS_OUTTOPAD_LSB _u(9) 411 #define IO_BANK0_GPIO2_STATUS_OUTTOPAD_ACCESS "RO" 412 // ----------------------------------------------------------------------------- 413 // Field : IO_BANK0_GPIO2_STATUS_OUTFROMPERI 414 // Description : output signal from selected peripheral, before register 415 // override is applied 416 #define IO_BANK0_GPIO2_STATUS_OUTFROMPERI_RESET _u(0x0) 417 #define IO_BANK0_GPIO2_STATUS_OUTFROMPERI_BITS _u(0x00000100) 418 #define IO_BANK0_GPIO2_STATUS_OUTFROMPERI_MSB _u(8) 419 #define IO_BANK0_GPIO2_STATUS_OUTFROMPERI_LSB _u(8) 420 #define IO_BANK0_GPIO2_STATUS_OUTFROMPERI_ACCESS "RO" 421 // ============================================================================= 422 // Register : IO_BANK0_GPIO2_CTRL 423 // Description : GPIO control including function select and overrides. 424 #define IO_BANK0_GPIO2_CTRL_OFFSET _u(0x00000014) 425 #define IO_BANK0_GPIO2_CTRL_BITS _u(0x3003331f) 426 #define IO_BANK0_GPIO2_CTRL_RESET _u(0x0000001f) 427 // ----------------------------------------------------------------------------- 428 // Field : IO_BANK0_GPIO2_CTRL_IRQOVER 429 // 0x0 -> don't invert the interrupt 430 // 0x1 -> invert the interrupt 431 // 0x2 -> drive interrupt low 432 // 0x3 -> drive interrupt high 433 #define IO_BANK0_GPIO2_CTRL_IRQOVER_RESET _u(0x0) 434 #define IO_BANK0_GPIO2_CTRL_IRQOVER_BITS _u(0x30000000) 435 #define IO_BANK0_GPIO2_CTRL_IRQOVER_MSB _u(29) 436 #define IO_BANK0_GPIO2_CTRL_IRQOVER_LSB _u(28) 437 #define IO_BANK0_GPIO2_CTRL_IRQOVER_ACCESS "RW" 438 #define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) 439 #define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_INVERT _u(0x1) 440 #define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_LOW _u(0x2) 441 #define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_HIGH _u(0x3) 442 // ----------------------------------------------------------------------------- 443 // Field : IO_BANK0_GPIO2_CTRL_INOVER 444 // 0x0 -> don't invert the peri input 445 // 0x1 -> invert the peri input 446 // 0x2 -> drive peri input low 447 // 0x3 -> drive peri input high 448 #define IO_BANK0_GPIO2_CTRL_INOVER_RESET _u(0x0) 449 #define IO_BANK0_GPIO2_CTRL_INOVER_BITS _u(0x00030000) 450 #define IO_BANK0_GPIO2_CTRL_INOVER_MSB _u(17) 451 #define IO_BANK0_GPIO2_CTRL_INOVER_LSB _u(16) 452 #define IO_BANK0_GPIO2_CTRL_INOVER_ACCESS "RW" 453 #define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_NORMAL _u(0x0) 454 #define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_INVERT _u(0x1) 455 #define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_LOW _u(0x2) 456 #define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_HIGH _u(0x3) 457 // ----------------------------------------------------------------------------- 458 // Field : IO_BANK0_GPIO2_CTRL_OEOVER 459 // 0x0 -> drive output enable from peripheral signal selected by funcsel 460 // 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel 461 // 0x2 -> disable output 462 // 0x3 -> enable output 463 #define IO_BANK0_GPIO2_CTRL_OEOVER_RESET _u(0x0) 464 #define IO_BANK0_GPIO2_CTRL_OEOVER_BITS _u(0x00003000) 465 #define IO_BANK0_GPIO2_CTRL_OEOVER_MSB _u(13) 466 #define IO_BANK0_GPIO2_CTRL_OEOVER_LSB _u(12) 467 #define IO_BANK0_GPIO2_CTRL_OEOVER_ACCESS "RW" 468 #define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_NORMAL _u(0x0) 469 #define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_INVERT _u(0x1) 470 #define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_DISABLE _u(0x2) 471 #define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_ENABLE _u(0x3) 472 // ----------------------------------------------------------------------------- 473 // Field : IO_BANK0_GPIO2_CTRL_OUTOVER 474 // 0x0 -> drive output from peripheral signal selected by funcsel 475 // 0x1 -> drive output from inverse of peripheral signal selected by funcsel 476 // 0x2 -> drive output low 477 // 0x3 -> drive output high 478 #define IO_BANK0_GPIO2_CTRL_OUTOVER_RESET _u(0x0) 479 #define IO_BANK0_GPIO2_CTRL_OUTOVER_BITS _u(0x00000300) 480 #define IO_BANK0_GPIO2_CTRL_OUTOVER_MSB _u(9) 481 #define IO_BANK0_GPIO2_CTRL_OUTOVER_LSB _u(8) 482 #define IO_BANK0_GPIO2_CTRL_OUTOVER_ACCESS "RW" 483 #define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) 484 #define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_INVERT _u(0x1) 485 #define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_LOW _u(0x2) 486 #define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_HIGH _u(0x3) 487 // ----------------------------------------------------------------------------- 488 // Field : IO_BANK0_GPIO2_CTRL_FUNCSEL 489 // Description : 0-31 -> selects pin function according to the gpio table 490 // 31 == NULL 491 // 0x00 -> jtag_tdi 492 // 0x01 -> spi0_sclk 493 // 0x02 -> uart0_cts 494 // 0x03 -> i2c1_sda 495 // 0x04 -> pwm_a_1 496 // 0x05 -> sio_2 497 // 0x06 -> pio0_2 498 // 0x07 -> pio1_2 499 // 0x09 -> usb_muxing_vbus_en 500 // 0x1f -> null 501 #define IO_BANK0_GPIO2_CTRL_FUNCSEL_RESET _u(0x1f) 502 #define IO_BANK0_GPIO2_CTRL_FUNCSEL_BITS _u(0x0000001f) 503 #define IO_BANK0_GPIO2_CTRL_FUNCSEL_MSB _u(4) 504 #define IO_BANK0_GPIO2_CTRL_FUNCSEL_LSB _u(0) 505 #define IO_BANK0_GPIO2_CTRL_FUNCSEL_ACCESS "RW" 506 #define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_JTAG_TDI _u(0x00) 507 #define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_SPI0_SCLK _u(0x01) 508 #define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_UART0_CTS _u(0x02) 509 #define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) 510 #define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_PWM_A_1 _u(0x04) 511 #define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_SIO_2 _u(0x05) 512 #define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_PIO0_2 _u(0x06) 513 #define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_PIO1_2 _u(0x07) 514 #define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09) 515 #define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) 516 // ============================================================================= 517 // Register : IO_BANK0_GPIO3_STATUS 518 // Description : GPIO status 519 #define IO_BANK0_GPIO3_STATUS_OFFSET _u(0x00000018) 520 #define IO_BANK0_GPIO3_STATUS_BITS _u(0x050a3300) 521 #define IO_BANK0_GPIO3_STATUS_RESET _u(0x00000000) 522 // ----------------------------------------------------------------------------- 523 // Field : IO_BANK0_GPIO3_STATUS_IRQTOPROC 524 // Description : interrupt to processors, after override is applied 525 #define IO_BANK0_GPIO3_STATUS_IRQTOPROC_RESET _u(0x0) 526 #define IO_BANK0_GPIO3_STATUS_IRQTOPROC_BITS _u(0x04000000) 527 #define IO_BANK0_GPIO3_STATUS_IRQTOPROC_MSB _u(26) 528 #define IO_BANK0_GPIO3_STATUS_IRQTOPROC_LSB _u(26) 529 #define IO_BANK0_GPIO3_STATUS_IRQTOPROC_ACCESS "RO" 530 // ----------------------------------------------------------------------------- 531 // Field : IO_BANK0_GPIO3_STATUS_IRQFROMPAD 532 // Description : interrupt from pad before override is applied 533 #define IO_BANK0_GPIO3_STATUS_IRQFROMPAD_RESET _u(0x0) 534 #define IO_BANK0_GPIO3_STATUS_IRQFROMPAD_BITS _u(0x01000000) 535 #define IO_BANK0_GPIO3_STATUS_IRQFROMPAD_MSB _u(24) 536 #define IO_BANK0_GPIO3_STATUS_IRQFROMPAD_LSB _u(24) 537 #define IO_BANK0_GPIO3_STATUS_IRQFROMPAD_ACCESS "RO" 538 // ----------------------------------------------------------------------------- 539 // Field : IO_BANK0_GPIO3_STATUS_INTOPERI 540 // Description : input signal to peripheral, after override is applied 541 #define IO_BANK0_GPIO3_STATUS_INTOPERI_RESET _u(0x0) 542 #define IO_BANK0_GPIO3_STATUS_INTOPERI_BITS _u(0x00080000) 543 #define IO_BANK0_GPIO3_STATUS_INTOPERI_MSB _u(19) 544 #define IO_BANK0_GPIO3_STATUS_INTOPERI_LSB _u(19) 545 #define IO_BANK0_GPIO3_STATUS_INTOPERI_ACCESS "RO" 546 // ----------------------------------------------------------------------------- 547 // Field : IO_BANK0_GPIO3_STATUS_INFROMPAD 548 // Description : input signal from pad, before override is applied 549 #define IO_BANK0_GPIO3_STATUS_INFROMPAD_RESET _u(0x0) 550 #define IO_BANK0_GPIO3_STATUS_INFROMPAD_BITS _u(0x00020000) 551 #define IO_BANK0_GPIO3_STATUS_INFROMPAD_MSB _u(17) 552 #define IO_BANK0_GPIO3_STATUS_INFROMPAD_LSB _u(17) 553 #define IO_BANK0_GPIO3_STATUS_INFROMPAD_ACCESS "RO" 554 // ----------------------------------------------------------------------------- 555 // Field : IO_BANK0_GPIO3_STATUS_OETOPAD 556 // Description : output enable to pad after register override is applied 557 #define IO_BANK0_GPIO3_STATUS_OETOPAD_RESET _u(0x0) 558 #define IO_BANK0_GPIO3_STATUS_OETOPAD_BITS _u(0x00002000) 559 #define IO_BANK0_GPIO3_STATUS_OETOPAD_MSB _u(13) 560 #define IO_BANK0_GPIO3_STATUS_OETOPAD_LSB _u(13) 561 #define IO_BANK0_GPIO3_STATUS_OETOPAD_ACCESS "RO" 562 // ----------------------------------------------------------------------------- 563 // Field : IO_BANK0_GPIO3_STATUS_OEFROMPERI 564 // Description : output enable from selected peripheral, before register 565 // override is applied 566 #define IO_BANK0_GPIO3_STATUS_OEFROMPERI_RESET _u(0x0) 567 #define IO_BANK0_GPIO3_STATUS_OEFROMPERI_BITS _u(0x00001000) 568 #define IO_BANK0_GPIO3_STATUS_OEFROMPERI_MSB _u(12) 569 #define IO_BANK0_GPIO3_STATUS_OEFROMPERI_LSB _u(12) 570 #define IO_BANK0_GPIO3_STATUS_OEFROMPERI_ACCESS "RO" 571 // ----------------------------------------------------------------------------- 572 // Field : IO_BANK0_GPIO3_STATUS_OUTTOPAD 573 // Description : output signal to pad after register override is applied 574 #define IO_BANK0_GPIO3_STATUS_OUTTOPAD_RESET _u(0x0) 575 #define IO_BANK0_GPIO3_STATUS_OUTTOPAD_BITS _u(0x00000200) 576 #define IO_BANK0_GPIO3_STATUS_OUTTOPAD_MSB _u(9) 577 #define IO_BANK0_GPIO3_STATUS_OUTTOPAD_LSB _u(9) 578 #define IO_BANK0_GPIO3_STATUS_OUTTOPAD_ACCESS "RO" 579 // ----------------------------------------------------------------------------- 580 // Field : IO_BANK0_GPIO3_STATUS_OUTFROMPERI 581 // Description : output signal from selected peripheral, before register 582 // override is applied 583 #define IO_BANK0_GPIO3_STATUS_OUTFROMPERI_RESET _u(0x0) 584 #define IO_BANK0_GPIO3_STATUS_OUTFROMPERI_BITS _u(0x00000100) 585 #define IO_BANK0_GPIO3_STATUS_OUTFROMPERI_MSB _u(8) 586 #define IO_BANK0_GPIO3_STATUS_OUTFROMPERI_LSB _u(8) 587 #define IO_BANK0_GPIO3_STATUS_OUTFROMPERI_ACCESS "RO" 588 // ============================================================================= 589 // Register : IO_BANK0_GPIO3_CTRL 590 // Description : GPIO control including function select and overrides. 591 #define IO_BANK0_GPIO3_CTRL_OFFSET _u(0x0000001c) 592 #define IO_BANK0_GPIO3_CTRL_BITS _u(0x3003331f) 593 #define IO_BANK0_GPIO3_CTRL_RESET _u(0x0000001f) 594 // ----------------------------------------------------------------------------- 595 // Field : IO_BANK0_GPIO3_CTRL_IRQOVER 596 // 0x0 -> don't invert the interrupt 597 // 0x1 -> invert the interrupt 598 // 0x2 -> drive interrupt low 599 // 0x3 -> drive interrupt high 600 #define IO_BANK0_GPIO3_CTRL_IRQOVER_RESET _u(0x0) 601 #define IO_BANK0_GPIO3_CTRL_IRQOVER_BITS _u(0x30000000) 602 #define IO_BANK0_GPIO3_CTRL_IRQOVER_MSB _u(29) 603 #define IO_BANK0_GPIO3_CTRL_IRQOVER_LSB _u(28) 604 #define IO_BANK0_GPIO3_CTRL_IRQOVER_ACCESS "RW" 605 #define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) 606 #define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_INVERT _u(0x1) 607 #define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_LOW _u(0x2) 608 #define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_HIGH _u(0x3) 609 // ----------------------------------------------------------------------------- 610 // Field : IO_BANK0_GPIO3_CTRL_INOVER 611 // 0x0 -> don't invert the peri input 612 // 0x1 -> invert the peri input 613 // 0x2 -> drive peri input low 614 // 0x3 -> drive peri input high 615 #define IO_BANK0_GPIO3_CTRL_INOVER_RESET _u(0x0) 616 #define IO_BANK0_GPIO3_CTRL_INOVER_BITS _u(0x00030000) 617 #define IO_BANK0_GPIO3_CTRL_INOVER_MSB _u(17) 618 #define IO_BANK0_GPIO3_CTRL_INOVER_LSB _u(16) 619 #define IO_BANK0_GPIO3_CTRL_INOVER_ACCESS "RW" 620 #define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_NORMAL _u(0x0) 621 #define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_INVERT _u(0x1) 622 #define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_LOW _u(0x2) 623 #define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_HIGH _u(0x3) 624 // ----------------------------------------------------------------------------- 625 // Field : IO_BANK0_GPIO3_CTRL_OEOVER 626 // 0x0 -> drive output enable from peripheral signal selected by funcsel 627 // 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel 628 // 0x2 -> disable output 629 // 0x3 -> enable output 630 #define IO_BANK0_GPIO3_CTRL_OEOVER_RESET _u(0x0) 631 #define IO_BANK0_GPIO3_CTRL_OEOVER_BITS _u(0x00003000) 632 #define IO_BANK0_GPIO3_CTRL_OEOVER_MSB _u(13) 633 #define IO_BANK0_GPIO3_CTRL_OEOVER_LSB _u(12) 634 #define IO_BANK0_GPIO3_CTRL_OEOVER_ACCESS "RW" 635 #define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_NORMAL _u(0x0) 636 #define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_INVERT _u(0x1) 637 #define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_DISABLE _u(0x2) 638 #define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_ENABLE _u(0x3) 639 // ----------------------------------------------------------------------------- 640 // Field : IO_BANK0_GPIO3_CTRL_OUTOVER 641 // 0x0 -> drive output from peripheral signal selected by funcsel 642 // 0x1 -> drive output from inverse of peripheral signal selected by funcsel 643 // 0x2 -> drive output low 644 // 0x3 -> drive output high 645 #define IO_BANK0_GPIO3_CTRL_OUTOVER_RESET _u(0x0) 646 #define IO_BANK0_GPIO3_CTRL_OUTOVER_BITS _u(0x00000300) 647 #define IO_BANK0_GPIO3_CTRL_OUTOVER_MSB _u(9) 648 #define IO_BANK0_GPIO3_CTRL_OUTOVER_LSB _u(8) 649 #define IO_BANK0_GPIO3_CTRL_OUTOVER_ACCESS "RW" 650 #define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) 651 #define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_INVERT _u(0x1) 652 #define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_LOW _u(0x2) 653 #define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_HIGH _u(0x3) 654 // ----------------------------------------------------------------------------- 655 // Field : IO_BANK0_GPIO3_CTRL_FUNCSEL 656 // Description : 0-31 -> selects pin function according to the gpio table 657 // 31 == NULL 658 // 0x00 -> jtag_tdo 659 // 0x01 -> spi0_tx 660 // 0x02 -> uart0_rts 661 // 0x03 -> i2c1_scl 662 // 0x04 -> pwm_b_1 663 // 0x05 -> sio_3 664 // 0x06 -> pio0_3 665 // 0x07 -> pio1_3 666 // 0x09 -> usb_muxing_overcurr_detect 667 // 0x1f -> null 668 #define IO_BANK0_GPIO3_CTRL_FUNCSEL_RESET _u(0x1f) 669 #define IO_BANK0_GPIO3_CTRL_FUNCSEL_BITS _u(0x0000001f) 670 #define IO_BANK0_GPIO3_CTRL_FUNCSEL_MSB _u(4) 671 #define IO_BANK0_GPIO3_CTRL_FUNCSEL_LSB _u(0) 672 #define IO_BANK0_GPIO3_CTRL_FUNCSEL_ACCESS "RW" 673 #define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_JTAG_TDO _u(0x00) 674 #define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_SPI0_TX _u(0x01) 675 #define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_UART0_RTS _u(0x02) 676 #define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) 677 #define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_PWM_B_1 _u(0x04) 678 #define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_SIO_3 _u(0x05) 679 #define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_PIO0_3 _u(0x06) 680 #define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_PIO1_3 _u(0x07) 681 #define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09) 682 #define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) 683 // ============================================================================= 684 // Register : IO_BANK0_GPIO4_STATUS 685 // Description : GPIO status 686 #define IO_BANK0_GPIO4_STATUS_OFFSET _u(0x00000020) 687 #define IO_BANK0_GPIO4_STATUS_BITS _u(0x050a3300) 688 #define IO_BANK0_GPIO4_STATUS_RESET _u(0x00000000) 689 // ----------------------------------------------------------------------------- 690 // Field : IO_BANK0_GPIO4_STATUS_IRQTOPROC 691 // Description : interrupt to processors, after override is applied 692 #define IO_BANK0_GPIO4_STATUS_IRQTOPROC_RESET _u(0x0) 693 #define IO_BANK0_GPIO4_STATUS_IRQTOPROC_BITS _u(0x04000000) 694 #define IO_BANK0_GPIO4_STATUS_IRQTOPROC_MSB _u(26) 695 #define IO_BANK0_GPIO4_STATUS_IRQTOPROC_LSB _u(26) 696 #define IO_BANK0_GPIO4_STATUS_IRQTOPROC_ACCESS "RO" 697 // ----------------------------------------------------------------------------- 698 // Field : IO_BANK0_GPIO4_STATUS_IRQFROMPAD 699 // Description : interrupt from pad before override is applied 700 #define IO_BANK0_GPIO4_STATUS_IRQFROMPAD_RESET _u(0x0) 701 #define IO_BANK0_GPIO4_STATUS_IRQFROMPAD_BITS _u(0x01000000) 702 #define IO_BANK0_GPIO4_STATUS_IRQFROMPAD_MSB _u(24) 703 #define IO_BANK0_GPIO4_STATUS_IRQFROMPAD_LSB _u(24) 704 #define IO_BANK0_GPIO4_STATUS_IRQFROMPAD_ACCESS "RO" 705 // ----------------------------------------------------------------------------- 706 // Field : IO_BANK0_GPIO4_STATUS_INTOPERI 707 // Description : input signal to peripheral, after override is applied 708 #define IO_BANK0_GPIO4_STATUS_INTOPERI_RESET _u(0x0) 709 #define IO_BANK0_GPIO4_STATUS_INTOPERI_BITS _u(0x00080000) 710 #define IO_BANK0_GPIO4_STATUS_INTOPERI_MSB _u(19) 711 #define IO_BANK0_GPIO4_STATUS_INTOPERI_LSB _u(19) 712 #define IO_BANK0_GPIO4_STATUS_INTOPERI_ACCESS "RO" 713 // ----------------------------------------------------------------------------- 714 // Field : IO_BANK0_GPIO4_STATUS_INFROMPAD 715 // Description : input signal from pad, before override is applied 716 #define IO_BANK0_GPIO4_STATUS_INFROMPAD_RESET _u(0x0) 717 #define IO_BANK0_GPIO4_STATUS_INFROMPAD_BITS _u(0x00020000) 718 #define IO_BANK0_GPIO4_STATUS_INFROMPAD_MSB _u(17) 719 #define IO_BANK0_GPIO4_STATUS_INFROMPAD_LSB _u(17) 720 #define IO_BANK0_GPIO4_STATUS_INFROMPAD_ACCESS "RO" 721 // ----------------------------------------------------------------------------- 722 // Field : IO_BANK0_GPIO4_STATUS_OETOPAD 723 // Description : output enable to pad after register override is applied 724 #define IO_BANK0_GPIO4_STATUS_OETOPAD_RESET _u(0x0) 725 #define IO_BANK0_GPIO4_STATUS_OETOPAD_BITS _u(0x00002000) 726 #define IO_BANK0_GPIO4_STATUS_OETOPAD_MSB _u(13) 727 #define IO_BANK0_GPIO4_STATUS_OETOPAD_LSB _u(13) 728 #define IO_BANK0_GPIO4_STATUS_OETOPAD_ACCESS "RO" 729 // ----------------------------------------------------------------------------- 730 // Field : IO_BANK0_GPIO4_STATUS_OEFROMPERI 731 // Description : output enable from selected peripheral, before register 732 // override is applied 733 #define IO_BANK0_GPIO4_STATUS_OEFROMPERI_RESET _u(0x0) 734 #define IO_BANK0_GPIO4_STATUS_OEFROMPERI_BITS _u(0x00001000) 735 #define IO_BANK0_GPIO4_STATUS_OEFROMPERI_MSB _u(12) 736 #define IO_BANK0_GPIO4_STATUS_OEFROMPERI_LSB _u(12) 737 #define IO_BANK0_GPIO4_STATUS_OEFROMPERI_ACCESS "RO" 738 // ----------------------------------------------------------------------------- 739 // Field : IO_BANK0_GPIO4_STATUS_OUTTOPAD 740 // Description : output signal to pad after register override is applied 741 #define IO_BANK0_GPIO4_STATUS_OUTTOPAD_RESET _u(0x0) 742 #define IO_BANK0_GPIO4_STATUS_OUTTOPAD_BITS _u(0x00000200) 743 #define IO_BANK0_GPIO4_STATUS_OUTTOPAD_MSB _u(9) 744 #define IO_BANK0_GPIO4_STATUS_OUTTOPAD_LSB _u(9) 745 #define IO_BANK0_GPIO4_STATUS_OUTTOPAD_ACCESS "RO" 746 // ----------------------------------------------------------------------------- 747 // Field : IO_BANK0_GPIO4_STATUS_OUTFROMPERI 748 // Description : output signal from selected peripheral, before register 749 // override is applied 750 #define IO_BANK0_GPIO4_STATUS_OUTFROMPERI_RESET _u(0x0) 751 #define IO_BANK0_GPIO4_STATUS_OUTFROMPERI_BITS _u(0x00000100) 752 #define IO_BANK0_GPIO4_STATUS_OUTFROMPERI_MSB _u(8) 753 #define IO_BANK0_GPIO4_STATUS_OUTFROMPERI_LSB _u(8) 754 #define IO_BANK0_GPIO4_STATUS_OUTFROMPERI_ACCESS "RO" 755 // ============================================================================= 756 // Register : IO_BANK0_GPIO4_CTRL 757 // Description : GPIO control including function select and overrides. 758 #define IO_BANK0_GPIO4_CTRL_OFFSET _u(0x00000024) 759 #define IO_BANK0_GPIO4_CTRL_BITS _u(0x3003331f) 760 #define IO_BANK0_GPIO4_CTRL_RESET _u(0x0000001f) 761 // ----------------------------------------------------------------------------- 762 // Field : IO_BANK0_GPIO4_CTRL_IRQOVER 763 // 0x0 -> don't invert the interrupt 764 // 0x1 -> invert the interrupt 765 // 0x2 -> drive interrupt low 766 // 0x3 -> drive interrupt high 767 #define IO_BANK0_GPIO4_CTRL_IRQOVER_RESET _u(0x0) 768 #define IO_BANK0_GPIO4_CTRL_IRQOVER_BITS _u(0x30000000) 769 #define IO_BANK0_GPIO4_CTRL_IRQOVER_MSB _u(29) 770 #define IO_BANK0_GPIO4_CTRL_IRQOVER_LSB _u(28) 771 #define IO_BANK0_GPIO4_CTRL_IRQOVER_ACCESS "RW" 772 #define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) 773 #define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_INVERT _u(0x1) 774 #define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_LOW _u(0x2) 775 #define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_HIGH _u(0x3) 776 // ----------------------------------------------------------------------------- 777 // Field : IO_BANK0_GPIO4_CTRL_INOVER 778 // 0x0 -> don't invert the peri input 779 // 0x1 -> invert the peri input 780 // 0x2 -> drive peri input low 781 // 0x3 -> drive peri input high 782 #define IO_BANK0_GPIO4_CTRL_INOVER_RESET _u(0x0) 783 #define IO_BANK0_GPIO4_CTRL_INOVER_BITS _u(0x00030000) 784 #define IO_BANK0_GPIO4_CTRL_INOVER_MSB _u(17) 785 #define IO_BANK0_GPIO4_CTRL_INOVER_LSB _u(16) 786 #define IO_BANK0_GPIO4_CTRL_INOVER_ACCESS "RW" 787 #define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_NORMAL _u(0x0) 788 #define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_INVERT _u(0x1) 789 #define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_LOW _u(0x2) 790 #define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_HIGH _u(0x3) 791 // ----------------------------------------------------------------------------- 792 // Field : IO_BANK0_GPIO4_CTRL_OEOVER 793 // 0x0 -> drive output enable from peripheral signal selected by funcsel 794 // 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel 795 // 0x2 -> disable output 796 // 0x3 -> enable output 797 #define IO_BANK0_GPIO4_CTRL_OEOVER_RESET _u(0x0) 798 #define IO_BANK0_GPIO4_CTRL_OEOVER_BITS _u(0x00003000) 799 #define IO_BANK0_GPIO4_CTRL_OEOVER_MSB _u(13) 800 #define IO_BANK0_GPIO4_CTRL_OEOVER_LSB _u(12) 801 #define IO_BANK0_GPIO4_CTRL_OEOVER_ACCESS "RW" 802 #define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_NORMAL _u(0x0) 803 #define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_INVERT _u(0x1) 804 #define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_DISABLE _u(0x2) 805 #define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_ENABLE _u(0x3) 806 // ----------------------------------------------------------------------------- 807 // Field : IO_BANK0_GPIO4_CTRL_OUTOVER 808 // 0x0 -> drive output from peripheral signal selected by funcsel 809 // 0x1 -> drive output from inverse of peripheral signal selected by funcsel 810 // 0x2 -> drive output low 811 // 0x3 -> drive output high 812 #define IO_BANK0_GPIO4_CTRL_OUTOVER_RESET _u(0x0) 813 #define IO_BANK0_GPIO4_CTRL_OUTOVER_BITS _u(0x00000300) 814 #define IO_BANK0_GPIO4_CTRL_OUTOVER_MSB _u(9) 815 #define IO_BANK0_GPIO4_CTRL_OUTOVER_LSB _u(8) 816 #define IO_BANK0_GPIO4_CTRL_OUTOVER_ACCESS "RW" 817 #define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) 818 #define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_INVERT _u(0x1) 819 #define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_LOW _u(0x2) 820 #define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_HIGH _u(0x3) 821 // ----------------------------------------------------------------------------- 822 // Field : IO_BANK0_GPIO4_CTRL_FUNCSEL 823 // Description : 0-31 -> selects pin function according to the gpio table 824 // 31 == NULL 825 // 0x01 -> spi0_rx 826 // 0x02 -> uart1_tx 827 // 0x03 -> i2c0_sda 828 // 0x04 -> pwm_a_2 829 // 0x05 -> sio_4 830 // 0x06 -> pio0_4 831 // 0x07 -> pio1_4 832 // 0x09 -> usb_muxing_vbus_detect 833 // 0x1f -> null 834 #define IO_BANK0_GPIO4_CTRL_FUNCSEL_RESET _u(0x1f) 835 #define IO_BANK0_GPIO4_CTRL_FUNCSEL_BITS _u(0x0000001f) 836 #define IO_BANK0_GPIO4_CTRL_FUNCSEL_MSB _u(4) 837 #define IO_BANK0_GPIO4_CTRL_FUNCSEL_LSB _u(0) 838 #define IO_BANK0_GPIO4_CTRL_FUNCSEL_ACCESS "RW" 839 #define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_SPI0_RX _u(0x01) 840 #define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x02) 841 #define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) 842 #define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_PWM_A_2 _u(0x04) 843 #define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_SIO_4 _u(0x05) 844 #define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_PIO0_4 _u(0x06) 845 #define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_PIO1_4 _u(0x07) 846 #define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09) 847 #define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) 848 // ============================================================================= 849 // Register : IO_BANK0_GPIO5_STATUS 850 // Description : GPIO status 851 #define IO_BANK0_GPIO5_STATUS_OFFSET _u(0x00000028) 852 #define IO_BANK0_GPIO5_STATUS_BITS _u(0x050a3300) 853 #define IO_BANK0_GPIO5_STATUS_RESET _u(0x00000000) 854 // ----------------------------------------------------------------------------- 855 // Field : IO_BANK0_GPIO5_STATUS_IRQTOPROC 856 // Description : interrupt to processors, after override is applied 857 #define IO_BANK0_GPIO5_STATUS_IRQTOPROC_RESET _u(0x0) 858 #define IO_BANK0_GPIO5_STATUS_IRQTOPROC_BITS _u(0x04000000) 859 #define IO_BANK0_GPIO5_STATUS_IRQTOPROC_MSB _u(26) 860 #define IO_BANK0_GPIO5_STATUS_IRQTOPROC_LSB _u(26) 861 #define IO_BANK0_GPIO5_STATUS_IRQTOPROC_ACCESS "RO" 862 // ----------------------------------------------------------------------------- 863 // Field : IO_BANK0_GPIO5_STATUS_IRQFROMPAD 864 // Description : interrupt from pad before override is applied 865 #define IO_BANK0_GPIO5_STATUS_IRQFROMPAD_RESET _u(0x0) 866 #define IO_BANK0_GPIO5_STATUS_IRQFROMPAD_BITS _u(0x01000000) 867 #define IO_BANK0_GPIO5_STATUS_IRQFROMPAD_MSB _u(24) 868 #define IO_BANK0_GPIO5_STATUS_IRQFROMPAD_LSB _u(24) 869 #define IO_BANK0_GPIO5_STATUS_IRQFROMPAD_ACCESS "RO" 870 // ----------------------------------------------------------------------------- 871 // Field : IO_BANK0_GPIO5_STATUS_INTOPERI 872 // Description : input signal to peripheral, after override is applied 873 #define IO_BANK0_GPIO5_STATUS_INTOPERI_RESET _u(0x0) 874 #define IO_BANK0_GPIO5_STATUS_INTOPERI_BITS _u(0x00080000) 875 #define IO_BANK0_GPIO5_STATUS_INTOPERI_MSB _u(19) 876 #define IO_BANK0_GPIO5_STATUS_INTOPERI_LSB _u(19) 877 #define IO_BANK0_GPIO5_STATUS_INTOPERI_ACCESS "RO" 878 // ----------------------------------------------------------------------------- 879 // Field : IO_BANK0_GPIO5_STATUS_INFROMPAD 880 // Description : input signal from pad, before override is applied 881 #define IO_BANK0_GPIO5_STATUS_INFROMPAD_RESET _u(0x0) 882 #define IO_BANK0_GPIO5_STATUS_INFROMPAD_BITS _u(0x00020000) 883 #define IO_BANK0_GPIO5_STATUS_INFROMPAD_MSB _u(17) 884 #define IO_BANK0_GPIO5_STATUS_INFROMPAD_LSB _u(17) 885 #define IO_BANK0_GPIO5_STATUS_INFROMPAD_ACCESS "RO" 886 // ----------------------------------------------------------------------------- 887 // Field : IO_BANK0_GPIO5_STATUS_OETOPAD 888 // Description : output enable to pad after register override is applied 889 #define IO_BANK0_GPIO5_STATUS_OETOPAD_RESET _u(0x0) 890 #define IO_BANK0_GPIO5_STATUS_OETOPAD_BITS _u(0x00002000) 891 #define IO_BANK0_GPIO5_STATUS_OETOPAD_MSB _u(13) 892 #define IO_BANK0_GPIO5_STATUS_OETOPAD_LSB _u(13) 893 #define IO_BANK0_GPIO5_STATUS_OETOPAD_ACCESS "RO" 894 // ----------------------------------------------------------------------------- 895 // Field : IO_BANK0_GPIO5_STATUS_OEFROMPERI 896 // Description : output enable from selected peripheral, before register 897 // override is applied 898 #define IO_BANK0_GPIO5_STATUS_OEFROMPERI_RESET _u(0x0) 899 #define IO_BANK0_GPIO5_STATUS_OEFROMPERI_BITS _u(0x00001000) 900 #define IO_BANK0_GPIO5_STATUS_OEFROMPERI_MSB _u(12) 901 #define IO_BANK0_GPIO5_STATUS_OEFROMPERI_LSB _u(12) 902 #define IO_BANK0_GPIO5_STATUS_OEFROMPERI_ACCESS "RO" 903 // ----------------------------------------------------------------------------- 904 // Field : IO_BANK0_GPIO5_STATUS_OUTTOPAD 905 // Description : output signal to pad after register override is applied 906 #define IO_BANK0_GPIO5_STATUS_OUTTOPAD_RESET _u(0x0) 907 #define IO_BANK0_GPIO5_STATUS_OUTTOPAD_BITS _u(0x00000200) 908 #define IO_BANK0_GPIO5_STATUS_OUTTOPAD_MSB _u(9) 909 #define IO_BANK0_GPIO5_STATUS_OUTTOPAD_LSB _u(9) 910 #define IO_BANK0_GPIO5_STATUS_OUTTOPAD_ACCESS "RO" 911 // ----------------------------------------------------------------------------- 912 // Field : IO_BANK0_GPIO5_STATUS_OUTFROMPERI 913 // Description : output signal from selected peripheral, before register 914 // override is applied 915 #define IO_BANK0_GPIO5_STATUS_OUTFROMPERI_RESET _u(0x0) 916 #define IO_BANK0_GPIO5_STATUS_OUTFROMPERI_BITS _u(0x00000100) 917 #define IO_BANK0_GPIO5_STATUS_OUTFROMPERI_MSB _u(8) 918 #define IO_BANK0_GPIO5_STATUS_OUTFROMPERI_LSB _u(8) 919 #define IO_BANK0_GPIO5_STATUS_OUTFROMPERI_ACCESS "RO" 920 // ============================================================================= 921 // Register : IO_BANK0_GPIO5_CTRL 922 // Description : GPIO control including function select and overrides. 923 #define IO_BANK0_GPIO5_CTRL_OFFSET _u(0x0000002c) 924 #define IO_BANK0_GPIO5_CTRL_BITS _u(0x3003331f) 925 #define IO_BANK0_GPIO5_CTRL_RESET _u(0x0000001f) 926 // ----------------------------------------------------------------------------- 927 // Field : IO_BANK0_GPIO5_CTRL_IRQOVER 928 // 0x0 -> don't invert the interrupt 929 // 0x1 -> invert the interrupt 930 // 0x2 -> drive interrupt low 931 // 0x3 -> drive interrupt high 932 #define IO_BANK0_GPIO5_CTRL_IRQOVER_RESET _u(0x0) 933 #define IO_BANK0_GPIO5_CTRL_IRQOVER_BITS _u(0x30000000) 934 #define IO_BANK0_GPIO5_CTRL_IRQOVER_MSB _u(29) 935 #define IO_BANK0_GPIO5_CTRL_IRQOVER_LSB _u(28) 936 #define IO_BANK0_GPIO5_CTRL_IRQOVER_ACCESS "RW" 937 #define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) 938 #define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_INVERT _u(0x1) 939 #define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_LOW _u(0x2) 940 #define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_HIGH _u(0x3) 941 // ----------------------------------------------------------------------------- 942 // Field : IO_BANK0_GPIO5_CTRL_INOVER 943 // 0x0 -> don't invert the peri input 944 // 0x1 -> invert the peri input 945 // 0x2 -> drive peri input low 946 // 0x3 -> drive peri input high 947 #define IO_BANK0_GPIO5_CTRL_INOVER_RESET _u(0x0) 948 #define IO_BANK0_GPIO5_CTRL_INOVER_BITS _u(0x00030000) 949 #define IO_BANK0_GPIO5_CTRL_INOVER_MSB _u(17) 950 #define IO_BANK0_GPIO5_CTRL_INOVER_LSB _u(16) 951 #define IO_BANK0_GPIO5_CTRL_INOVER_ACCESS "RW" 952 #define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_NORMAL _u(0x0) 953 #define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_INVERT _u(0x1) 954 #define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_LOW _u(0x2) 955 #define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_HIGH _u(0x3) 956 // ----------------------------------------------------------------------------- 957 // Field : IO_BANK0_GPIO5_CTRL_OEOVER 958 // 0x0 -> drive output enable from peripheral signal selected by funcsel 959 // 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel 960 // 0x2 -> disable output 961 // 0x3 -> enable output 962 #define IO_BANK0_GPIO5_CTRL_OEOVER_RESET _u(0x0) 963 #define IO_BANK0_GPIO5_CTRL_OEOVER_BITS _u(0x00003000) 964 #define IO_BANK0_GPIO5_CTRL_OEOVER_MSB _u(13) 965 #define IO_BANK0_GPIO5_CTRL_OEOVER_LSB _u(12) 966 #define IO_BANK0_GPIO5_CTRL_OEOVER_ACCESS "RW" 967 #define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_NORMAL _u(0x0) 968 #define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_INVERT _u(0x1) 969 #define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_DISABLE _u(0x2) 970 #define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_ENABLE _u(0x3) 971 // ----------------------------------------------------------------------------- 972 // Field : IO_BANK0_GPIO5_CTRL_OUTOVER 973 // 0x0 -> drive output from peripheral signal selected by funcsel 974 // 0x1 -> drive output from inverse of peripheral signal selected by funcsel 975 // 0x2 -> drive output low 976 // 0x3 -> drive output high 977 #define IO_BANK0_GPIO5_CTRL_OUTOVER_RESET _u(0x0) 978 #define IO_BANK0_GPIO5_CTRL_OUTOVER_BITS _u(0x00000300) 979 #define IO_BANK0_GPIO5_CTRL_OUTOVER_MSB _u(9) 980 #define IO_BANK0_GPIO5_CTRL_OUTOVER_LSB _u(8) 981 #define IO_BANK0_GPIO5_CTRL_OUTOVER_ACCESS "RW" 982 #define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) 983 #define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_INVERT _u(0x1) 984 #define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_LOW _u(0x2) 985 #define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_HIGH _u(0x3) 986 // ----------------------------------------------------------------------------- 987 // Field : IO_BANK0_GPIO5_CTRL_FUNCSEL 988 // Description : 0-31 -> selects pin function according to the gpio table 989 // 31 == NULL 990 // 0x01 -> spi0_ss_n 991 // 0x02 -> uart1_rx 992 // 0x03 -> i2c0_scl 993 // 0x04 -> pwm_b_2 994 // 0x05 -> sio_5 995 // 0x06 -> pio0_5 996 // 0x07 -> pio1_5 997 // 0x09 -> usb_muxing_vbus_en 998 // 0x1f -> null 999 #define IO_BANK0_GPIO5_CTRL_FUNCSEL_RESET _u(0x1f) 1000 #define IO_BANK0_GPIO5_CTRL_FUNCSEL_BITS _u(0x0000001f) 1001 #define IO_BANK0_GPIO5_CTRL_FUNCSEL_MSB _u(4) 1002 #define IO_BANK0_GPIO5_CTRL_FUNCSEL_LSB _u(0) 1003 #define IO_BANK0_GPIO5_CTRL_FUNCSEL_ACCESS "RW" 1004 #define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_SPI0_SS_N _u(0x01) 1005 #define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x02) 1006 #define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) 1007 #define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_PWM_B_2 _u(0x04) 1008 #define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_SIO_5 _u(0x05) 1009 #define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_PIO0_5 _u(0x06) 1010 #define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_PIO1_5 _u(0x07) 1011 #define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09) 1012 #define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) 1013 // ============================================================================= 1014 // Register : IO_BANK0_GPIO6_STATUS 1015 // Description : GPIO status 1016 #define IO_BANK0_GPIO6_STATUS_OFFSET _u(0x00000030) 1017 #define IO_BANK0_GPIO6_STATUS_BITS _u(0x050a3300) 1018 #define IO_BANK0_GPIO6_STATUS_RESET _u(0x00000000) 1019 // ----------------------------------------------------------------------------- 1020 // Field : IO_BANK0_GPIO6_STATUS_IRQTOPROC 1021 // Description : interrupt to processors, after override is applied 1022 #define IO_BANK0_GPIO6_STATUS_IRQTOPROC_RESET _u(0x0) 1023 #define IO_BANK0_GPIO6_STATUS_IRQTOPROC_BITS _u(0x04000000) 1024 #define IO_BANK0_GPIO6_STATUS_IRQTOPROC_MSB _u(26) 1025 #define IO_BANK0_GPIO6_STATUS_IRQTOPROC_LSB _u(26) 1026 #define IO_BANK0_GPIO6_STATUS_IRQTOPROC_ACCESS "RO" 1027 // ----------------------------------------------------------------------------- 1028 // Field : IO_BANK0_GPIO6_STATUS_IRQFROMPAD 1029 // Description : interrupt from pad before override is applied 1030 #define IO_BANK0_GPIO6_STATUS_IRQFROMPAD_RESET _u(0x0) 1031 #define IO_BANK0_GPIO6_STATUS_IRQFROMPAD_BITS _u(0x01000000) 1032 #define IO_BANK0_GPIO6_STATUS_IRQFROMPAD_MSB _u(24) 1033 #define IO_BANK0_GPIO6_STATUS_IRQFROMPAD_LSB _u(24) 1034 #define IO_BANK0_GPIO6_STATUS_IRQFROMPAD_ACCESS "RO" 1035 // ----------------------------------------------------------------------------- 1036 // Field : IO_BANK0_GPIO6_STATUS_INTOPERI 1037 // Description : input signal to peripheral, after override is applied 1038 #define IO_BANK0_GPIO6_STATUS_INTOPERI_RESET _u(0x0) 1039 #define IO_BANK0_GPIO6_STATUS_INTOPERI_BITS _u(0x00080000) 1040 #define IO_BANK0_GPIO6_STATUS_INTOPERI_MSB _u(19) 1041 #define IO_BANK0_GPIO6_STATUS_INTOPERI_LSB _u(19) 1042 #define IO_BANK0_GPIO6_STATUS_INTOPERI_ACCESS "RO" 1043 // ----------------------------------------------------------------------------- 1044 // Field : IO_BANK0_GPIO6_STATUS_INFROMPAD 1045 // Description : input signal from pad, before override is applied 1046 #define IO_BANK0_GPIO6_STATUS_INFROMPAD_RESET _u(0x0) 1047 #define IO_BANK0_GPIO6_STATUS_INFROMPAD_BITS _u(0x00020000) 1048 #define IO_BANK0_GPIO6_STATUS_INFROMPAD_MSB _u(17) 1049 #define IO_BANK0_GPIO6_STATUS_INFROMPAD_LSB _u(17) 1050 #define IO_BANK0_GPIO6_STATUS_INFROMPAD_ACCESS "RO" 1051 // ----------------------------------------------------------------------------- 1052 // Field : IO_BANK0_GPIO6_STATUS_OETOPAD 1053 // Description : output enable to pad after register override is applied 1054 #define IO_BANK0_GPIO6_STATUS_OETOPAD_RESET _u(0x0) 1055 #define IO_BANK0_GPIO6_STATUS_OETOPAD_BITS _u(0x00002000) 1056 #define IO_BANK0_GPIO6_STATUS_OETOPAD_MSB _u(13) 1057 #define IO_BANK0_GPIO6_STATUS_OETOPAD_LSB _u(13) 1058 #define IO_BANK0_GPIO6_STATUS_OETOPAD_ACCESS "RO" 1059 // ----------------------------------------------------------------------------- 1060 // Field : IO_BANK0_GPIO6_STATUS_OEFROMPERI 1061 // Description : output enable from selected peripheral, before register 1062 // override is applied 1063 #define IO_BANK0_GPIO6_STATUS_OEFROMPERI_RESET _u(0x0) 1064 #define IO_BANK0_GPIO6_STATUS_OEFROMPERI_BITS _u(0x00001000) 1065 #define IO_BANK0_GPIO6_STATUS_OEFROMPERI_MSB _u(12) 1066 #define IO_BANK0_GPIO6_STATUS_OEFROMPERI_LSB _u(12) 1067 #define IO_BANK0_GPIO6_STATUS_OEFROMPERI_ACCESS "RO" 1068 // ----------------------------------------------------------------------------- 1069 // Field : IO_BANK0_GPIO6_STATUS_OUTTOPAD 1070 // Description : output signal to pad after register override is applied 1071 #define IO_BANK0_GPIO6_STATUS_OUTTOPAD_RESET _u(0x0) 1072 #define IO_BANK0_GPIO6_STATUS_OUTTOPAD_BITS _u(0x00000200) 1073 #define IO_BANK0_GPIO6_STATUS_OUTTOPAD_MSB _u(9) 1074 #define IO_BANK0_GPIO6_STATUS_OUTTOPAD_LSB _u(9) 1075 #define IO_BANK0_GPIO6_STATUS_OUTTOPAD_ACCESS "RO" 1076 // ----------------------------------------------------------------------------- 1077 // Field : IO_BANK0_GPIO6_STATUS_OUTFROMPERI 1078 // Description : output signal from selected peripheral, before register 1079 // override is applied 1080 #define IO_BANK0_GPIO6_STATUS_OUTFROMPERI_RESET _u(0x0) 1081 #define IO_BANK0_GPIO6_STATUS_OUTFROMPERI_BITS _u(0x00000100) 1082 #define IO_BANK0_GPIO6_STATUS_OUTFROMPERI_MSB _u(8) 1083 #define IO_BANK0_GPIO6_STATUS_OUTFROMPERI_LSB _u(8) 1084 #define IO_BANK0_GPIO6_STATUS_OUTFROMPERI_ACCESS "RO" 1085 // ============================================================================= 1086 // Register : IO_BANK0_GPIO6_CTRL 1087 // Description : GPIO control including function select and overrides. 1088 #define IO_BANK0_GPIO6_CTRL_OFFSET _u(0x00000034) 1089 #define IO_BANK0_GPIO6_CTRL_BITS _u(0x3003331f) 1090 #define IO_BANK0_GPIO6_CTRL_RESET _u(0x0000001f) 1091 // ----------------------------------------------------------------------------- 1092 // Field : IO_BANK0_GPIO6_CTRL_IRQOVER 1093 // 0x0 -> don't invert the interrupt 1094 // 0x1 -> invert the interrupt 1095 // 0x2 -> drive interrupt low 1096 // 0x3 -> drive interrupt high 1097 #define IO_BANK0_GPIO6_CTRL_IRQOVER_RESET _u(0x0) 1098 #define IO_BANK0_GPIO6_CTRL_IRQOVER_BITS _u(0x30000000) 1099 #define IO_BANK0_GPIO6_CTRL_IRQOVER_MSB _u(29) 1100 #define IO_BANK0_GPIO6_CTRL_IRQOVER_LSB _u(28) 1101 #define IO_BANK0_GPIO6_CTRL_IRQOVER_ACCESS "RW" 1102 #define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) 1103 #define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_INVERT _u(0x1) 1104 #define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_LOW _u(0x2) 1105 #define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_HIGH _u(0x3) 1106 // ----------------------------------------------------------------------------- 1107 // Field : IO_BANK0_GPIO6_CTRL_INOVER 1108 // 0x0 -> don't invert the peri input 1109 // 0x1 -> invert the peri input 1110 // 0x2 -> drive peri input low 1111 // 0x3 -> drive peri input high 1112 #define IO_BANK0_GPIO6_CTRL_INOVER_RESET _u(0x0) 1113 #define IO_BANK0_GPIO6_CTRL_INOVER_BITS _u(0x00030000) 1114 #define IO_BANK0_GPIO6_CTRL_INOVER_MSB _u(17) 1115 #define IO_BANK0_GPIO6_CTRL_INOVER_LSB _u(16) 1116 #define IO_BANK0_GPIO6_CTRL_INOVER_ACCESS "RW" 1117 #define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_NORMAL _u(0x0) 1118 #define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_INVERT _u(0x1) 1119 #define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_LOW _u(0x2) 1120 #define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_HIGH _u(0x3) 1121 // ----------------------------------------------------------------------------- 1122 // Field : IO_BANK0_GPIO6_CTRL_OEOVER 1123 // 0x0 -> drive output enable from peripheral signal selected by funcsel 1124 // 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel 1125 // 0x2 -> disable output 1126 // 0x3 -> enable output 1127 #define IO_BANK0_GPIO6_CTRL_OEOVER_RESET _u(0x0) 1128 #define IO_BANK0_GPIO6_CTRL_OEOVER_BITS _u(0x00003000) 1129 #define IO_BANK0_GPIO6_CTRL_OEOVER_MSB _u(13) 1130 #define IO_BANK0_GPIO6_CTRL_OEOVER_LSB _u(12) 1131 #define IO_BANK0_GPIO6_CTRL_OEOVER_ACCESS "RW" 1132 #define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_NORMAL _u(0x0) 1133 #define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_INVERT _u(0x1) 1134 #define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_DISABLE _u(0x2) 1135 #define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_ENABLE _u(0x3) 1136 // ----------------------------------------------------------------------------- 1137 // Field : IO_BANK0_GPIO6_CTRL_OUTOVER 1138 // 0x0 -> drive output from peripheral signal selected by funcsel 1139 // 0x1 -> drive output from inverse of peripheral signal selected by funcsel 1140 // 0x2 -> drive output low 1141 // 0x3 -> drive output high 1142 #define IO_BANK0_GPIO6_CTRL_OUTOVER_RESET _u(0x0) 1143 #define IO_BANK0_GPIO6_CTRL_OUTOVER_BITS _u(0x00000300) 1144 #define IO_BANK0_GPIO6_CTRL_OUTOVER_MSB _u(9) 1145 #define IO_BANK0_GPIO6_CTRL_OUTOVER_LSB _u(8) 1146 #define IO_BANK0_GPIO6_CTRL_OUTOVER_ACCESS "RW" 1147 #define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) 1148 #define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_INVERT _u(0x1) 1149 #define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_LOW _u(0x2) 1150 #define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_HIGH _u(0x3) 1151 // ----------------------------------------------------------------------------- 1152 // Field : IO_BANK0_GPIO6_CTRL_FUNCSEL 1153 // Description : 0-31 -> selects pin function according to the gpio table 1154 // 31 == NULL 1155 // 0x01 -> spi0_sclk 1156 // 0x02 -> uart1_cts 1157 // 0x03 -> i2c1_sda 1158 // 0x04 -> pwm_a_3 1159 // 0x05 -> sio_6 1160 // 0x06 -> pio0_6 1161 // 0x07 -> pio1_6 1162 // 0x08 -> usb_muxing_extphy_softcon 1163 // 0x09 -> usb_muxing_overcurr_detect 1164 // 0x1f -> null 1165 #define IO_BANK0_GPIO6_CTRL_FUNCSEL_RESET _u(0x1f) 1166 #define IO_BANK0_GPIO6_CTRL_FUNCSEL_BITS _u(0x0000001f) 1167 #define IO_BANK0_GPIO6_CTRL_FUNCSEL_MSB _u(4) 1168 #define IO_BANK0_GPIO6_CTRL_FUNCSEL_LSB _u(0) 1169 #define IO_BANK0_GPIO6_CTRL_FUNCSEL_ACCESS "RW" 1170 #define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_SPI0_SCLK _u(0x01) 1171 #define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_UART1_CTS _u(0x02) 1172 #define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) 1173 #define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_PWM_A_3 _u(0x04) 1174 #define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_SIO_6 _u(0x05) 1175 #define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_PIO0_6 _u(0x06) 1176 #define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_PIO1_6 _u(0x07) 1177 #define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_SOFTCON _u(0x08) 1178 #define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09) 1179 #define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) 1180 // ============================================================================= 1181 // Register : IO_BANK0_GPIO7_STATUS 1182 // Description : GPIO status 1183 #define IO_BANK0_GPIO7_STATUS_OFFSET _u(0x00000038) 1184 #define IO_BANK0_GPIO7_STATUS_BITS _u(0x050a3300) 1185 #define IO_BANK0_GPIO7_STATUS_RESET _u(0x00000000) 1186 // ----------------------------------------------------------------------------- 1187 // Field : IO_BANK0_GPIO7_STATUS_IRQTOPROC 1188 // Description : interrupt to processors, after override is applied 1189 #define IO_BANK0_GPIO7_STATUS_IRQTOPROC_RESET _u(0x0) 1190 #define IO_BANK0_GPIO7_STATUS_IRQTOPROC_BITS _u(0x04000000) 1191 #define IO_BANK0_GPIO7_STATUS_IRQTOPROC_MSB _u(26) 1192 #define IO_BANK0_GPIO7_STATUS_IRQTOPROC_LSB _u(26) 1193 #define IO_BANK0_GPIO7_STATUS_IRQTOPROC_ACCESS "RO" 1194 // ----------------------------------------------------------------------------- 1195 // Field : IO_BANK0_GPIO7_STATUS_IRQFROMPAD 1196 // Description : interrupt from pad before override is applied 1197 #define IO_BANK0_GPIO7_STATUS_IRQFROMPAD_RESET _u(0x0) 1198 #define IO_BANK0_GPIO7_STATUS_IRQFROMPAD_BITS _u(0x01000000) 1199 #define IO_BANK0_GPIO7_STATUS_IRQFROMPAD_MSB _u(24) 1200 #define IO_BANK0_GPIO7_STATUS_IRQFROMPAD_LSB _u(24) 1201 #define IO_BANK0_GPIO7_STATUS_IRQFROMPAD_ACCESS "RO" 1202 // ----------------------------------------------------------------------------- 1203 // Field : IO_BANK0_GPIO7_STATUS_INTOPERI 1204 // Description : input signal to peripheral, after override is applied 1205 #define IO_BANK0_GPIO7_STATUS_INTOPERI_RESET _u(0x0) 1206 #define IO_BANK0_GPIO7_STATUS_INTOPERI_BITS _u(0x00080000) 1207 #define IO_BANK0_GPIO7_STATUS_INTOPERI_MSB _u(19) 1208 #define IO_BANK0_GPIO7_STATUS_INTOPERI_LSB _u(19) 1209 #define IO_BANK0_GPIO7_STATUS_INTOPERI_ACCESS "RO" 1210 // ----------------------------------------------------------------------------- 1211 // Field : IO_BANK0_GPIO7_STATUS_INFROMPAD 1212 // Description : input signal from pad, before override is applied 1213 #define IO_BANK0_GPIO7_STATUS_INFROMPAD_RESET _u(0x0) 1214 #define IO_BANK0_GPIO7_STATUS_INFROMPAD_BITS _u(0x00020000) 1215 #define IO_BANK0_GPIO7_STATUS_INFROMPAD_MSB _u(17) 1216 #define IO_BANK0_GPIO7_STATUS_INFROMPAD_LSB _u(17) 1217 #define IO_BANK0_GPIO7_STATUS_INFROMPAD_ACCESS "RO" 1218 // ----------------------------------------------------------------------------- 1219 // Field : IO_BANK0_GPIO7_STATUS_OETOPAD 1220 // Description : output enable to pad after register override is applied 1221 #define IO_BANK0_GPIO7_STATUS_OETOPAD_RESET _u(0x0) 1222 #define IO_BANK0_GPIO7_STATUS_OETOPAD_BITS _u(0x00002000) 1223 #define IO_BANK0_GPIO7_STATUS_OETOPAD_MSB _u(13) 1224 #define IO_BANK0_GPIO7_STATUS_OETOPAD_LSB _u(13) 1225 #define IO_BANK0_GPIO7_STATUS_OETOPAD_ACCESS "RO" 1226 // ----------------------------------------------------------------------------- 1227 // Field : IO_BANK0_GPIO7_STATUS_OEFROMPERI 1228 // Description : output enable from selected peripheral, before register 1229 // override is applied 1230 #define IO_BANK0_GPIO7_STATUS_OEFROMPERI_RESET _u(0x0) 1231 #define IO_BANK0_GPIO7_STATUS_OEFROMPERI_BITS _u(0x00001000) 1232 #define IO_BANK0_GPIO7_STATUS_OEFROMPERI_MSB _u(12) 1233 #define IO_BANK0_GPIO7_STATUS_OEFROMPERI_LSB _u(12) 1234 #define IO_BANK0_GPIO7_STATUS_OEFROMPERI_ACCESS "RO" 1235 // ----------------------------------------------------------------------------- 1236 // Field : IO_BANK0_GPIO7_STATUS_OUTTOPAD 1237 // Description : output signal to pad after register override is applied 1238 #define IO_BANK0_GPIO7_STATUS_OUTTOPAD_RESET _u(0x0) 1239 #define IO_BANK0_GPIO7_STATUS_OUTTOPAD_BITS _u(0x00000200) 1240 #define IO_BANK0_GPIO7_STATUS_OUTTOPAD_MSB _u(9) 1241 #define IO_BANK0_GPIO7_STATUS_OUTTOPAD_LSB _u(9) 1242 #define IO_BANK0_GPIO7_STATUS_OUTTOPAD_ACCESS "RO" 1243 // ----------------------------------------------------------------------------- 1244 // Field : IO_BANK0_GPIO7_STATUS_OUTFROMPERI 1245 // Description : output signal from selected peripheral, before register 1246 // override is applied 1247 #define IO_BANK0_GPIO7_STATUS_OUTFROMPERI_RESET _u(0x0) 1248 #define IO_BANK0_GPIO7_STATUS_OUTFROMPERI_BITS _u(0x00000100) 1249 #define IO_BANK0_GPIO7_STATUS_OUTFROMPERI_MSB _u(8) 1250 #define IO_BANK0_GPIO7_STATUS_OUTFROMPERI_LSB _u(8) 1251 #define IO_BANK0_GPIO7_STATUS_OUTFROMPERI_ACCESS "RO" 1252 // ============================================================================= 1253 // Register : IO_BANK0_GPIO7_CTRL 1254 // Description : GPIO control including function select and overrides. 1255 #define IO_BANK0_GPIO7_CTRL_OFFSET _u(0x0000003c) 1256 #define IO_BANK0_GPIO7_CTRL_BITS _u(0x3003331f) 1257 #define IO_BANK0_GPIO7_CTRL_RESET _u(0x0000001f) 1258 // ----------------------------------------------------------------------------- 1259 // Field : IO_BANK0_GPIO7_CTRL_IRQOVER 1260 // 0x0 -> don't invert the interrupt 1261 // 0x1 -> invert the interrupt 1262 // 0x2 -> drive interrupt low 1263 // 0x3 -> drive interrupt high 1264 #define IO_BANK0_GPIO7_CTRL_IRQOVER_RESET _u(0x0) 1265 #define IO_BANK0_GPIO7_CTRL_IRQOVER_BITS _u(0x30000000) 1266 #define IO_BANK0_GPIO7_CTRL_IRQOVER_MSB _u(29) 1267 #define IO_BANK0_GPIO7_CTRL_IRQOVER_LSB _u(28) 1268 #define IO_BANK0_GPIO7_CTRL_IRQOVER_ACCESS "RW" 1269 #define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) 1270 #define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_INVERT _u(0x1) 1271 #define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_LOW _u(0x2) 1272 #define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_HIGH _u(0x3) 1273 // ----------------------------------------------------------------------------- 1274 // Field : IO_BANK0_GPIO7_CTRL_INOVER 1275 // 0x0 -> don't invert the peri input 1276 // 0x1 -> invert the peri input 1277 // 0x2 -> drive peri input low 1278 // 0x3 -> drive peri input high 1279 #define IO_BANK0_GPIO7_CTRL_INOVER_RESET _u(0x0) 1280 #define IO_BANK0_GPIO7_CTRL_INOVER_BITS _u(0x00030000) 1281 #define IO_BANK0_GPIO7_CTRL_INOVER_MSB _u(17) 1282 #define IO_BANK0_GPIO7_CTRL_INOVER_LSB _u(16) 1283 #define IO_BANK0_GPIO7_CTRL_INOVER_ACCESS "RW" 1284 #define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_NORMAL _u(0x0) 1285 #define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_INVERT _u(0x1) 1286 #define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_LOW _u(0x2) 1287 #define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_HIGH _u(0x3) 1288 // ----------------------------------------------------------------------------- 1289 // Field : IO_BANK0_GPIO7_CTRL_OEOVER 1290 // 0x0 -> drive output enable from peripheral signal selected by funcsel 1291 // 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel 1292 // 0x2 -> disable output 1293 // 0x3 -> enable output 1294 #define IO_BANK0_GPIO7_CTRL_OEOVER_RESET _u(0x0) 1295 #define IO_BANK0_GPIO7_CTRL_OEOVER_BITS _u(0x00003000) 1296 #define IO_BANK0_GPIO7_CTRL_OEOVER_MSB _u(13) 1297 #define IO_BANK0_GPIO7_CTRL_OEOVER_LSB _u(12) 1298 #define IO_BANK0_GPIO7_CTRL_OEOVER_ACCESS "RW" 1299 #define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_NORMAL _u(0x0) 1300 #define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_INVERT _u(0x1) 1301 #define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_DISABLE _u(0x2) 1302 #define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_ENABLE _u(0x3) 1303 // ----------------------------------------------------------------------------- 1304 // Field : IO_BANK0_GPIO7_CTRL_OUTOVER 1305 // 0x0 -> drive output from peripheral signal selected by funcsel 1306 // 0x1 -> drive output from inverse of peripheral signal selected by funcsel 1307 // 0x2 -> drive output low 1308 // 0x3 -> drive output high 1309 #define IO_BANK0_GPIO7_CTRL_OUTOVER_RESET _u(0x0) 1310 #define IO_BANK0_GPIO7_CTRL_OUTOVER_BITS _u(0x00000300) 1311 #define IO_BANK0_GPIO7_CTRL_OUTOVER_MSB _u(9) 1312 #define IO_BANK0_GPIO7_CTRL_OUTOVER_LSB _u(8) 1313 #define IO_BANK0_GPIO7_CTRL_OUTOVER_ACCESS "RW" 1314 #define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) 1315 #define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_INVERT _u(0x1) 1316 #define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_LOW _u(0x2) 1317 #define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_HIGH _u(0x3) 1318 // ----------------------------------------------------------------------------- 1319 // Field : IO_BANK0_GPIO7_CTRL_FUNCSEL 1320 // Description : 0-31 -> selects pin function according to the gpio table 1321 // 31 == NULL 1322 // 0x01 -> spi0_tx 1323 // 0x02 -> uart1_rts 1324 // 0x03 -> i2c1_scl 1325 // 0x04 -> pwm_b_3 1326 // 0x05 -> sio_7 1327 // 0x06 -> pio0_7 1328 // 0x07 -> pio1_7 1329 // 0x08 -> usb_muxing_extphy_oe_n 1330 // 0x09 -> usb_muxing_vbus_detect 1331 // 0x1f -> null 1332 #define IO_BANK0_GPIO7_CTRL_FUNCSEL_RESET _u(0x1f) 1333 #define IO_BANK0_GPIO7_CTRL_FUNCSEL_BITS _u(0x0000001f) 1334 #define IO_BANK0_GPIO7_CTRL_FUNCSEL_MSB _u(4) 1335 #define IO_BANK0_GPIO7_CTRL_FUNCSEL_LSB _u(0) 1336 #define IO_BANK0_GPIO7_CTRL_FUNCSEL_ACCESS "RW" 1337 #define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_SPI0_TX _u(0x01) 1338 #define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_UART1_RTS _u(0x02) 1339 #define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) 1340 #define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_PWM_B_3 _u(0x04) 1341 #define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_SIO_7 _u(0x05) 1342 #define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_PIO0_7 _u(0x06) 1343 #define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_PIO1_7 _u(0x07) 1344 #define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_OE_N _u(0x08) 1345 #define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09) 1346 #define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) 1347 // ============================================================================= 1348 // Register : IO_BANK0_GPIO8_STATUS 1349 // Description : GPIO status 1350 #define IO_BANK0_GPIO8_STATUS_OFFSET _u(0x00000040) 1351 #define IO_BANK0_GPIO8_STATUS_BITS _u(0x050a3300) 1352 #define IO_BANK0_GPIO8_STATUS_RESET _u(0x00000000) 1353 // ----------------------------------------------------------------------------- 1354 // Field : IO_BANK0_GPIO8_STATUS_IRQTOPROC 1355 // Description : interrupt to processors, after override is applied 1356 #define IO_BANK0_GPIO8_STATUS_IRQTOPROC_RESET _u(0x0) 1357 #define IO_BANK0_GPIO8_STATUS_IRQTOPROC_BITS _u(0x04000000) 1358 #define IO_BANK0_GPIO8_STATUS_IRQTOPROC_MSB _u(26) 1359 #define IO_BANK0_GPIO8_STATUS_IRQTOPROC_LSB _u(26) 1360 #define IO_BANK0_GPIO8_STATUS_IRQTOPROC_ACCESS "RO" 1361 // ----------------------------------------------------------------------------- 1362 // Field : IO_BANK0_GPIO8_STATUS_IRQFROMPAD 1363 // Description : interrupt from pad before override is applied 1364 #define IO_BANK0_GPIO8_STATUS_IRQFROMPAD_RESET _u(0x0) 1365 #define IO_BANK0_GPIO8_STATUS_IRQFROMPAD_BITS _u(0x01000000) 1366 #define IO_BANK0_GPIO8_STATUS_IRQFROMPAD_MSB _u(24) 1367 #define IO_BANK0_GPIO8_STATUS_IRQFROMPAD_LSB _u(24) 1368 #define IO_BANK0_GPIO8_STATUS_IRQFROMPAD_ACCESS "RO" 1369 // ----------------------------------------------------------------------------- 1370 // Field : IO_BANK0_GPIO8_STATUS_INTOPERI 1371 // Description : input signal to peripheral, after override is applied 1372 #define IO_BANK0_GPIO8_STATUS_INTOPERI_RESET _u(0x0) 1373 #define IO_BANK0_GPIO8_STATUS_INTOPERI_BITS _u(0x00080000) 1374 #define IO_BANK0_GPIO8_STATUS_INTOPERI_MSB _u(19) 1375 #define IO_BANK0_GPIO8_STATUS_INTOPERI_LSB _u(19) 1376 #define IO_BANK0_GPIO8_STATUS_INTOPERI_ACCESS "RO" 1377 // ----------------------------------------------------------------------------- 1378 // Field : IO_BANK0_GPIO8_STATUS_INFROMPAD 1379 // Description : input signal from pad, before override is applied 1380 #define IO_BANK0_GPIO8_STATUS_INFROMPAD_RESET _u(0x0) 1381 #define IO_BANK0_GPIO8_STATUS_INFROMPAD_BITS _u(0x00020000) 1382 #define IO_BANK0_GPIO8_STATUS_INFROMPAD_MSB _u(17) 1383 #define IO_BANK0_GPIO8_STATUS_INFROMPAD_LSB _u(17) 1384 #define IO_BANK0_GPIO8_STATUS_INFROMPAD_ACCESS "RO" 1385 // ----------------------------------------------------------------------------- 1386 // Field : IO_BANK0_GPIO8_STATUS_OETOPAD 1387 // Description : output enable to pad after register override is applied 1388 #define IO_BANK0_GPIO8_STATUS_OETOPAD_RESET _u(0x0) 1389 #define IO_BANK0_GPIO8_STATUS_OETOPAD_BITS _u(0x00002000) 1390 #define IO_BANK0_GPIO8_STATUS_OETOPAD_MSB _u(13) 1391 #define IO_BANK0_GPIO8_STATUS_OETOPAD_LSB _u(13) 1392 #define IO_BANK0_GPIO8_STATUS_OETOPAD_ACCESS "RO" 1393 // ----------------------------------------------------------------------------- 1394 // Field : IO_BANK0_GPIO8_STATUS_OEFROMPERI 1395 // Description : output enable from selected peripheral, before register 1396 // override is applied 1397 #define IO_BANK0_GPIO8_STATUS_OEFROMPERI_RESET _u(0x0) 1398 #define IO_BANK0_GPIO8_STATUS_OEFROMPERI_BITS _u(0x00001000) 1399 #define IO_BANK0_GPIO8_STATUS_OEFROMPERI_MSB _u(12) 1400 #define IO_BANK0_GPIO8_STATUS_OEFROMPERI_LSB _u(12) 1401 #define IO_BANK0_GPIO8_STATUS_OEFROMPERI_ACCESS "RO" 1402 // ----------------------------------------------------------------------------- 1403 // Field : IO_BANK0_GPIO8_STATUS_OUTTOPAD 1404 // Description : output signal to pad after register override is applied 1405 #define IO_BANK0_GPIO8_STATUS_OUTTOPAD_RESET _u(0x0) 1406 #define IO_BANK0_GPIO8_STATUS_OUTTOPAD_BITS _u(0x00000200) 1407 #define IO_BANK0_GPIO8_STATUS_OUTTOPAD_MSB _u(9) 1408 #define IO_BANK0_GPIO8_STATUS_OUTTOPAD_LSB _u(9) 1409 #define IO_BANK0_GPIO8_STATUS_OUTTOPAD_ACCESS "RO" 1410 // ----------------------------------------------------------------------------- 1411 // Field : IO_BANK0_GPIO8_STATUS_OUTFROMPERI 1412 // Description : output signal from selected peripheral, before register 1413 // override is applied 1414 #define IO_BANK0_GPIO8_STATUS_OUTFROMPERI_RESET _u(0x0) 1415 #define IO_BANK0_GPIO8_STATUS_OUTFROMPERI_BITS _u(0x00000100) 1416 #define IO_BANK0_GPIO8_STATUS_OUTFROMPERI_MSB _u(8) 1417 #define IO_BANK0_GPIO8_STATUS_OUTFROMPERI_LSB _u(8) 1418 #define IO_BANK0_GPIO8_STATUS_OUTFROMPERI_ACCESS "RO" 1419 // ============================================================================= 1420 // Register : IO_BANK0_GPIO8_CTRL 1421 // Description : GPIO control including function select and overrides. 1422 #define IO_BANK0_GPIO8_CTRL_OFFSET _u(0x00000044) 1423 #define IO_BANK0_GPIO8_CTRL_BITS _u(0x3003331f) 1424 #define IO_BANK0_GPIO8_CTRL_RESET _u(0x0000001f) 1425 // ----------------------------------------------------------------------------- 1426 // Field : IO_BANK0_GPIO8_CTRL_IRQOVER 1427 // 0x0 -> don't invert the interrupt 1428 // 0x1 -> invert the interrupt 1429 // 0x2 -> drive interrupt low 1430 // 0x3 -> drive interrupt high 1431 #define IO_BANK0_GPIO8_CTRL_IRQOVER_RESET _u(0x0) 1432 #define IO_BANK0_GPIO8_CTRL_IRQOVER_BITS _u(0x30000000) 1433 #define IO_BANK0_GPIO8_CTRL_IRQOVER_MSB _u(29) 1434 #define IO_BANK0_GPIO8_CTRL_IRQOVER_LSB _u(28) 1435 #define IO_BANK0_GPIO8_CTRL_IRQOVER_ACCESS "RW" 1436 #define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) 1437 #define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_INVERT _u(0x1) 1438 #define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_LOW _u(0x2) 1439 #define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_HIGH _u(0x3) 1440 // ----------------------------------------------------------------------------- 1441 // Field : IO_BANK0_GPIO8_CTRL_INOVER 1442 // 0x0 -> don't invert the peri input 1443 // 0x1 -> invert the peri input 1444 // 0x2 -> drive peri input low 1445 // 0x3 -> drive peri input high 1446 #define IO_BANK0_GPIO8_CTRL_INOVER_RESET _u(0x0) 1447 #define IO_BANK0_GPIO8_CTRL_INOVER_BITS _u(0x00030000) 1448 #define IO_BANK0_GPIO8_CTRL_INOVER_MSB _u(17) 1449 #define IO_BANK0_GPIO8_CTRL_INOVER_LSB _u(16) 1450 #define IO_BANK0_GPIO8_CTRL_INOVER_ACCESS "RW" 1451 #define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_NORMAL _u(0x0) 1452 #define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_INVERT _u(0x1) 1453 #define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_LOW _u(0x2) 1454 #define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_HIGH _u(0x3) 1455 // ----------------------------------------------------------------------------- 1456 // Field : IO_BANK0_GPIO8_CTRL_OEOVER 1457 // 0x0 -> drive output enable from peripheral signal selected by funcsel 1458 // 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel 1459 // 0x2 -> disable output 1460 // 0x3 -> enable output 1461 #define IO_BANK0_GPIO8_CTRL_OEOVER_RESET _u(0x0) 1462 #define IO_BANK0_GPIO8_CTRL_OEOVER_BITS _u(0x00003000) 1463 #define IO_BANK0_GPIO8_CTRL_OEOVER_MSB _u(13) 1464 #define IO_BANK0_GPIO8_CTRL_OEOVER_LSB _u(12) 1465 #define IO_BANK0_GPIO8_CTRL_OEOVER_ACCESS "RW" 1466 #define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_NORMAL _u(0x0) 1467 #define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_INVERT _u(0x1) 1468 #define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_DISABLE _u(0x2) 1469 #define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_ENABLE _u(0x3) 1470 // ----------------------------------------------------------------------------- 1471 // Field : IO_BANK0_GPIO8_CTRL_OUTOVER 1472 // 0x0 -> drive output from peripheral signal selected by funcsel 1473 // 0x1 -> drive output from inverse of peripheral signal selected by funcsel 1474 // 0x2 -> drive output low 1475 // 0x3 -> drive output high 1476 #define IO_BANK0_GPIO8_CTRL_OUTOVER_RESET _u(0x0) 1477 #define IO_BANK0_GPIO8_CTRL_OUTOVER_BITS _u(0x00000300) 1478 #define IO_BANK0_GPIO8_CTRL_OUTOVER_MSB _u(9) 1479 #define IO_BANK0_GPIO8_CTRL_OUTOVER_LSB _u(8) 1480 #define IO_BANK0_GPIO8_CTRL_OUTOVER_ACCESS "RW" 1481 #define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) 1482 #define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_INVERT _u(0x1) 1483 #define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_LOW _u(0x2) 1484 #define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_HIGH _u(0x3) 1485 // ----------------------------------------------------------------------------- 1486 // Field : IO_BANK0_GPIO8_CTRL_FUNCSEL 1487 // Description : 0-31 -> selects pin function according to the gpio table 1488 // 31 == NULL 1489 // 0x01 -> spi1_rx 1490 // 0x02 -> uart1_tx 1491 // 0x03 -> i2c0_sda 1492 // 0x04 -> pwm_a_4 1493 // 0x05 -> sio_8 1494 // 0x06 -> pio0_8 1495 // 0x07 -> pio1_8 1496 // 0x08 -> usb_muxing_extphy_rcv 1497 // 0x09 -> usb_muxing_vbus_en 1498 // 0x1f -> null 1499 #define IO_BANK0_GPIO8_CTRL_FUNCSEL_RESET _u(0x1f) 1500 #define IO_BANK0_GPIO8_CTRL_FUNCSEL_BITS _u(0x0000001f) 1501 #define IO_BANK0_GPIO8_CTRL_FUNCSEL_MSB _u(4) 1502 #define IO_BANK0_GPIO8_CTRL_FUNCSEL_LSB _u(0) 1503 #define IO_BANK0_GPIO8_CTRL_FUNCSEL_ACCESS "RW" 1504 #define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_SPI1_RX _u(0x01) 1505 #define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x02) 1506 #define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) 1507 #define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_PWM_A_4 _u(0x04) 1508 #define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_SIO_8 _u(0x05) 1509 #define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_PIO0_8 _u(0x06) 1510 #define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_PIO1_8 _u(0x07) 1511 #define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_RCV _u(0x08) 1512 #define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09) 1513 #define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) 1514 // ============================================================================= 1515 // Register : IO_BANK0_GPIO9_STATUS 1516 // Description : GPIO status 1517 #define IO_BANK0_GPIO9_STATUS_OFFSET _u(0x00000048) 1518 #define IO_BANK0_GPIO9_STATUS_BITS _u(0x050a3300) 1519 #define IO_BANK0_GPIO9_STATUS_RESET _u(0x00000000) 1520 // ----------------------------------------------------------------------------- 1521 // Field : IO_BANK0_GPIO9_STATUS_IRQTOPROC 1522 // Description : interrupt to processors, after override is applied 1523 #define IO_BANK0_GPIO9_STATUS_IRQTOPROC_RESET _u(0x0) 1524 #define IO_BANK0_GPIO9_STATUS_IRQTOPROC_BITS _u(0x04000000) 1525 #define IO_BANK0_GPIO9_STATUS_IRQTOPROC_MSB _u(26) 1526 #define IO_BANK0_GPIO9_STATUS_IRQTOPROC_LSB _u(26) 1527 #define IO_BANK0_GPIO9_STATUS_IRQTOPROC_ACCESS "RO" 1528 // ----------------------------------------------------------------------------- 1529 // Field : IO_BANK0_GPIO9_STATUS_IRQFROMPAD 1530 // Description : interrupt from pad before override is applied 1531 #define IO_BANK0_GPIO9_STATUS_IRQFROMPAD_RESET _u(0x0) 1532 #define IO_BANK0_GPIO9_STATUS_IRQFROMPAD_BITS _u(0x01000000) 1533 #define IO_BANK0_GPIO9_STATUS_IRQFROMPAD_MSB _u(24) 1534 #define IO_BANK0_GPIO9_STATUS_IRQFROMPAD_LSB _u(24) 1535 #define IO_BANK0_GPIO9_STATUS_IRQFROMPAD_ACCESS "RO" 1536 // ----------------------------------------------------------------------------- 1537 // Field : IO_BANK0_GPIO9_STATUS_INTOPERI 1538 // Description : input signal to peripheral, after override is applied 1539 #define IO_BANK0_GPIO9_STATUS_INTOPERI_RESET _u(0x0) 1540 #define IO_BANK0_GPIO9_STATUS_INTOPERI_BITS _u(0x00080000) 1541 #define IO_BANK0_GPIO9_STATUS_INTOPERI_MSB _u(19) 1542 #define IO_BANK0_GPIO9_STATUS_INTOPERI_LSB _u(19) 1543 #define IO_BANK0_GPIO9_STATUS_INTOPERI_ACCESS "RO" 1544 // ----------------------------------------------------------------------------- 1545 // Field : IO_BANK0_GPIO9_STATUS_INFROMPAD 1546 // Description : input signal from pad, before override is applied 1547 #define IO_BANK0_GPIO9_STATUS_INFROMPAD_RESET _u(0x0) 1548 #define IO_BANK0_GPIO9_STATUS_INFROMPAD_BITS _u(0x00020000) 1549 #define IO_BANK0_GPIO9_STATUS_INFROMPAD_MSB _u(17) 1550 #define IO_BANK0_GPIO9_STATUS_INFROMPAD_LSB _u(17) 1551 #define IO_BANK0_GPIO9_STATUS_INFROMPAD_ACCESS "RO" 1552 // ----------------------------------------------------------------------------- 1553 // Field : IO_BANK0_GPIO9_STATUS_OETOPAD 1554 // Description : output enable to pad after register override is applied 1555 #define IO_BANK0_GPIO9_STATUS_OETOPAD_RESET _u(0x0) 1556 #define IO_BANK0_GPIO9_STATUS_OETOPAD_BITS _u(0x00002000) 1557 #define IO_BANK0_GPIO9_STATUS_OETOPAD_MSB _u(13) 1558 #define IO_BANK0_GPIO9_STATUS_OETOPAD_LSB _u(13) 1559 #define IO_BANK0_GPIO9_STATUS_OETOPAD_ACCESS "RO" 1560 // ----------------------------------------------------------------------------- 1561 // Field : IO_BANK0_GPIO9_STATUS_OEFROMPERI 1562 // Description : output enable from selected peripheral, before register 1563 // override is applied 1564 #define IO_BANK0_GPIO9_STATUS_OEFROMPERI_RESET _u(0x0) 1565 #define IO_BANK0_GPIO9_STATUS_OEFROMPERI_BITS _u(0x00001000) 1566 #define IO_BANK0_GPIO9_STATUS_OEFROMPERI_MSB _u(12) 1567 #define IO_BANK0_GPIO9_STATUS_OEFROMPERI_LSB _u(12) 1568 #define IO_BANK0_GPIO9_STATUS_OEFROMPERI_ACCESS "RO" 1569 // ----------------------------------------------------------------------------- 1570 // Field : IO_BANK0_GPIO9_STATUS_OUTTOPAD 1571 // Description : output signal to pad after register override is applied 1572 #define IO_BANK0_GPIO9_STATUS_OUTTOPAD_RESET _u(0x0) 1573 #define IO_BANK0_GPIO9_STATUS_OUTTOPAD_BITS _u(0x00000200) 1574 #define IO_BANK0_GPIO9_STATUS_OUTTOPAD_MSB _u(9) 1575 #define IO_BANK0_GPIO9_STATUS_OUTTOPAD_LSB _u(9) 1576 #define IO_BANK0_GPIO9_STATUS_OUTTOPAD_ACCESS "RO" 1577 // ----------------------------------------------------------------------------- 1578 // Field : IO_BANK0_GPIO9_STATUS_OUTFROMPERI 1579 // Description : output signal from selected peripheral, before register 1580 // override is applied 1581 #define IO_BANK0_GPIO9_STATUS_OUTFROMPERI_RESET _u(0x0) 1582 #define IO_BANK0_GPIO9_STATUS_OUTFROMPERI_BITS _u(0x00000100) 1583 #define IO_BANK0_GPIO9_STATUS_OUTFROMPERI_MSB _u(8) 1584 #define IO_BANK0_GPIO9_STATUS_OUTFROMPERI_LSB _u(8) 1585 #define IO_BANK0_GPIO9_STATUS_OUTFROMPERI_ACCESS "RO" 1586 // ============================================================================= 1587 // Register : IO_BANK0_GPIO9_CTRL 1588 // Description : GPIO control including function select and overrides. 1589 #define IO_BANK0_GPIO9_CTRL_OFFSET _u(0x0000004c) 1590 #define IO_BANK0_GPIO9_CTRL_BITS _u(0x3003331f) 1591 #define IO_BANK0_GPIO9_CTRL_RESET _u(0x0000001f) 1592 // ----------------------------------------------------------------------------- 1593 // Field : IO_BANK0_GPIO9_CTRL_IRQOVER 1594 // 0x0 -> don't invert the interrupt 1595 // 0x1 -> invert the interrupt 1596 // 0x2 -> drive interrupt low 1597 // 0x3 -> drive interrupt high 1598 #define IO_BANK0_GPIO9_CTRL_IRQOVER_RESET _u(0x0) 1599 #define IO_BANK0_GPIO9_CTRL_IRQOVER_BITS _u(0x30000000) 1600 #define IO_BANK0_GPIO9_CTRL_IRQOVER_MSB _u(29) 1601 #define IO_BANK0_GPIO9_CTRL_IRQOVER_LSB _u(28) 1602 #define IO_BANK0_GPIO9_CTRL_IRQOVER_ACCESS "RW" 1603 #define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) 1604 #define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_INVERT _u(0x1) 1605 #define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_LOW _u(0x2) 1606 #define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_HIGH _u(0x3) 1607 // ----------------------------------------------------------------------------- 1608 // Field : IO_BANK0_GPIO9_CTRL_INOVER 1609 // 0x0 -> don't invert the peri input 1610 // 0x1 -> invert the peri input 1611 // 0x2 -> drive peri input low 1612 // 0x3 -> drive peri input high 1613 #define IO_BANK0_GPIO9_CTRL_INOVER_RESET _u(0x0) 1614 #define IO_BANK0_GPIO9_CTRL_INOVER_BITS _u(0x00030000) 1615 #define IO_BANK0_GPIO9_CTRL_INOVER_MSB _u(17) 1616 #define IO_BANK0_GPIO9_CTRL_INOVER_LSB _u(16) 1617 #define IO_BANK0_GPIO9_CTRL_INOVER_ACCESS "RW" 1618 #define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_NORMAL _u(0x0) 1619 #define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_INVERT _u(0x1) 1620 #define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_LOW _u(0x2) 1621 #define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_HIGH _u(0x3) 1622 // ----------------------------------------------------------------------------- 1623 // Field : IO_BANK0_GPIO9_CTRL_OEOVER 1624 // 0x0 -> drive output enable from peripheral signal selected by funcsel 1625 // 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel 1626 // 0x2 -> disable output 1627 // 0x3 -> enable output 1628 #define IO_BANK0_GPIO9_CTRL_OEOVER_RESET _u(0x0) 1629 #define IO_BANK0_GPIO9_CTRL_OEOVER_BITS _u(0x00003000) 1630 #define IO_BANK0_GPIO9_CTRL_OEOVER_MSB _u(13) 1631 #define IO_BANK0_GPIO9_CTRL_OEOVER_LSB _u(12) 1632 #define IO_BANK0_GPIO9_CTRL_OEOVER_ACCESS "RW" 1633 #define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_NORMAL _u(0x0) 1634 #define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_INVERT _u(0x1) 1635 #define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_DISABLE _u(0x2) 1636 #define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_ENABLE _u(0x3) 1637 // ----------------------------------------------------------------------------- 1638 // Field : IO_BANK0_GPIO9_CTRL_OUTOVER 1639 // 0x0 -> drive output from peripheral signal selected by funcsel 1640 // 0x1 -> drive output from inverse of peripheral signal selected by funcsel 1641 // 0x2 -> drive output low 1642 // 0x3 -> drive output high 1643 #define IO_BANK0_GPIO9_CTRL_OUTOVER_RESET _u(0x0) 1644 #define IO_BANK0_GPIO9_CTRL_OUTOVER_BITS _u(0x00000300) 1645 #define IO_BANK0_GPIO9_CTRL_OUTOVER_MSB _u(9) 1646 #define IO_BANK0_GPIO9_CTRL_OUTOVER_LSB _u(8) 1647 #define IO_BANK0_GPIO9_CTRL_OUTOVER_ACCESS "RW" 1648 #define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) 1649 #define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_INVERT _u(0x1) 1650 #define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_LOW _u(0x2) 1651 #define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_HIGH _u(0x3) 1652 // ----------------------------------------------------------------------------- 1653 // Field : IO_BANK0_GPIO9_CTRL_FUNCSEL 1654 // Description : 0-31 -> selects pin function according to the gpio table 1655 // 31 == NULL 1656 // 0x01 -> spi1_ss_n 1657 // 0x02 -> uart1_rx 1658 // 0x03 -> i2c0_scl 1659 // 0x04 -> pwm_b_4 1660 // 0x05 -> sio_9 1661 // 0x06 -> pio0_9 1662 // 0x07 -> pio1_9 1663 // 0x08 -> usb_muxing_extphy_vp 1664 // 0x09 -> usb_muxing_overcurr_detect 1665 // 0x1f -> null 1666 #define IO_BANK0_GPIO9_CTRL_FUNCSEL_RESET _u(0x1f) 1667 #define IO_BANK0_GPIO9_CTRL_FUNCSEL_BITS _u(0x0000001f) 1668 #define IO_BANK0_GPIO9_CTRL_FUNCSEL_MSB _u(4) 1669 #define IO_BANK0_GPIO9_CTRL_FUNCSEL_LSB _u(0) 1670 #define IO_BANK0_GPIO9_CTRL_FUNCSEL_ACCESS "RW" 1671 #define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_SPI1_SS_N _u(0x01) 1672 #define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x02) 1673 #define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) 1674 #define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_PWM_B_4 _u(0x04) 1675 #define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_SIO_9 _u(0x05) 1676 #define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_PIO0_9 _u(0x06) 1677 #define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_PIO1_9 _u(0x07) 1678 #define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_VP _u(0x08) 1679 #define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09) 1680 #define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) 1681 // ============================================================================= 1682 // Register : IO_BANK0_GPIO10_STATUS 1683 // Description : GPIO status 1684 #define IO_BANK0_GPIO10_STATUS_OFFSET _u(0x00000050) 1685 #define IO_BANK0_GPIO10_STATUS_BITS _u(0x050a3300) 1686 #define IO_BANK0_GPIO10_STATUS_RESET _u(0x00000000) 1687 // ----------------------------------------------------------------------------- 1688 // Field : IO_BANK0_GPIO10_STATUS_IRQTOPROC 1689 // Description : interrupt to processors, after override is applied 1690 #define IO_BANK0_GPIO10_STATUS_IRQTOPROC_RESET _u(0x0) 1691 #define IO_BANK0_GPIO10_STATUS_IRQTOPROC_BITS _u(0x04000000) 1692 #define IO_BANK0_GPIO10_STATUS_IRQTOPROC_MSB _u(26) 1693 #define IO_BANK0_GPIO10_STATUS_IRQTOPROC_LSB _u(26) 1694 #define IO_BANK0_GPIO10_STATUS_IRQTOPROC_ACCESS "RO" 1695 // ----------------------------------------------------------------------------- 1696 // Field : IO_BANK0_GPIO10_STATUS_IRQFROMPAD 1697 // Description : interrupt from pad before override is applied 1698 #define IO_BANK0_GPIO10_STATUS_IRQFROMPAD_RESET _u(0x0) 1699 #define IO_BANK0_GPIO10_STATUS_IRQFROMPAD_BITS _u(0x01000000) 1700 #define IO_BANK0_GPIO10_STATUS_IRQFROMPAD_MSB _u(24) 1701 #define IO_BANK0_GPIO10_STATUS_IRQFROMPAD_LSB _u(24) 1702 #define IO_BANK0_GPIO10_STATUS_IRQFROMPAD_ACCESS "RO" 1703 // ----------------------------------------------------------------------------- 1704 // Field : IO_BANK0_GPIO10_STATUS_INTOPERI 1705 // Description : input signal to peripheral, after override is applied 1706 #define IO_BANK0_GPIO10_STATUS_INTOPERI_RESET _u(0x0) 1707 #define IO_BANK0_GPIO10_STATUS_INTOPERI_BITS _u(0x00080000) 1708 #define IO_BANK0_GPIO10_STATUS_INTOPERI_MSB _u(19) 1709 #define IO_BANK0_GPIO10_STATUS_INTOPERI_LSB _u(19) 1710 #define IO_BANK0_GPIO10_STATUS_INTOPERI_ACCESS "RO" 1711 // ----------------------------------------------------------------------------- 1712 // Field : IO_BANK0_GPIO10_STATUS_INFROMPAD 1713 // Description : input signal from pad, before override is applied 1714 #define IO_BANK0_GPIO10_STATUS_INFROMPAD_RESET _u(0x0) 1715 #define IO_BANK0_GPIO10_STATUS_INFROMPAD_BITS _u(0x00020000) 1716 #define IO_BANK0_GPIO10_STATUS_INFROMPAD_MSB _u(17) 1717 #define IO_BANK0_GPIO10_STATUS_INFROMPAD_LSB _u(17) 1718 #define IO_BANK0_GPIO10_STATUS_INFROMPAD_ACCESS "RO" 1719 // ----------------------------------------------------------------------------- 1720 // Field : IO_BANK0_GPIO10_STATUS_OETOPAD 1721 // Description : output enable to pad after register override is applied 1722 #define IO_BANK0_GPIO10_STATUS_OETOPAD_RESET _u(0x0) 1723 #define IO_BANK0_GPIO10_STATUS_OETOPAD_BITS _u(0x00002000) 1724 #define IO_BANK0_GPIO10_STATUS_OETOPAD_MSB _u(13) 1725 #define IO_BANK0_GPIO10_STATUS_OETOPAD_LSB _u(13) 1726 #define IO_BANK0_GPIO10_STATUS_OETOPAD_ACCESS "RO" 1727 // ----------------------------------------------------------------------------- 1728 // Field : IO_BANK0_GPIO10_STATUS_OEFROMPERI 1729 // Description : output enable from selected peripheral, before register 1730 // override is applied 1731 #define IO_BANK0_GPIO10_STATUS_OEFROMPERI_RESET _u(0x0) 1732 #define IO_BANK0_GPIO10_STATUS_OEFROMPERI_BITS _u(0x00001000) 1733 #define IO_BANK0_GPIO10_STATUS_OEFROMPERI_MSB _u(12) 1734 #define IO_BANK0_GPIO10_STATUS_OEFROMPERI_LSB _u(12) 1735 #define IO_BANK0_GPIO10_STATUS_OEFROMPERI_ACCESS "RO" 1736 // ----------------------------------------------------------------------------- 1737 // Field : IO_BANK0_GPIO10_STATUS_OUTTOPAD 1738 // Description : output signal to pad after register override is applied 1739 #define IO_BANK0_GPIO10_STATUS_OUTTOPAD_RESET _u(0x0) 1740 #define IO_BANK0_GPIO10_STATUS_OUTTOPAD_BITS _u(0x00000200) 1741 #define IO_BANK0_GPIO10_STATUS_OUTTOPAD_MSB _u(9) 1742 #define IO_BANK0_GPIO10_STATUS_OUTTOPAD_LSB _u(9) 1743 #define IO_BANK0_GPIO10_STATUS_OUTTOPAD_ACCESS "RO" 1744 // ----------------------------------------------------------------------------- 1745 // Field : IO_BANK0_GPIO10_STATUS_OUTFROMPERI 1746 // Description : output signal from selected peripheral, before register 1747 // override is applied 1748 #define IO_BANK0_GPIO10_STATUS_OUTFROMPERI_RESET _u(0x0) 1749 #define IO_BANK0_GPIO10_STATUS_OUTFROMPERI_BITS _u(0x00000100) 1750 #define IO_BANK0_GPIO10_STATUS_OUTFROMPERI_MSB _u(8) 1751 #define IO_BANK0_GPIO10_STATUS_OUTFROMPERI_LSB _u(8) 1752 #define IO_BANK0_GPIO10_STATUS_OUTFROMPERI_ACCESS "RO" 1753 // ============================================================================= 1754 // Register : IO_BANK0_GPIO10_CTRL 1755 // Description : GPIO control including function select and overrides. 1756 #define IO_BANK0_GPIO10_CTRL_OFFSET _u(0x00000054) 1757 #define IO_BANK0_GPIO10_CTRL_BITS _u(0x3003331f) 1758 #define IO_BANK0_GPIO10_CTRL_RESET _u(0x0000001f) 1759 // ----------------------------------------------------------------------------- 1760 // Field : IO_BANK0_GPIO10_CTRL_IRQOVER 1761 // 0x0 -> don't invert the interrupt 1762 // 0x1 -> invert the interrupt 1763 // 0x2 -> drive interrupt low 1764 // 0x3 -> drive interrupt high 1765 #define IO_BANK0_GPIO10_CTRL_IRQOVER_RESET _u(0x0) 1766 #define IO_BANK0_GPIO10_CTRL_IRQOVER_BITS _u(0x30000000) 1767 #define IO_BANK0_GPIO10_CTRL_IRQOVER_MSB _u(29) 1768 #define IO_BANK0_GPIO10_CTRL_IRQOVER_LSB _u(28) 1769 #define IO_BANK0_GPIO10_CTRL_IRQOVER_ACCESS "RW" 1770 #define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) 1771 #define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_INVERT _u(0x1) 1772 #define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_LOW _u(0x2) 1773 #define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_HIGH _u(0x3) 1774 // ----------------------------------------------------------------------------- 1775 // Field : IO_BANK0_GPIO10_CTRL_INOVER 1776 // 0x0 -> don't invert the peri input 1777 // 0x1 -> invert the peri input 1778 // 0x2 -> drive peri input low 1779 // 0x3 -> drive peri input high 1780 #define IO_BANK0_GPIO10_CTRL_INOVER_RESET _u(0x0) 1781 #define IO_BANK0_GPIO10_CTRL_INOVER_BITS _u(0x00030000) 1782 #define IO_BANK0_GPIO10_CTRL_INOVER_MSB _u(17) 1783 #define IO_BANK0_GPIO10_CTRL_INOVER_LSB _u(16) 1784 #define IO_BANK0_GPIO10_CTRL_INOVER_ACCESS "RW" 1785 #define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_NORMAL _u(0x0) 1786 #define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_INVERT _u(0x1) 1787 #define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_LOW _u(0x2) 1788 #define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_HIGH _u(0x3) 1789 // ----------------------------------------------------------------------------- 1790 // Field : IO_BANK0_GPIO10_CTRL_OEOVER 1791 // 0x0 -> drive output enable from peripheral signal selected by funcsel 1792 // 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel 1793 // 0x2 -> disable output 1794 // 0x3 -> enable output 1795 #define IO_BANK0_GPIO10_CTRL_OEOVER_RESET _u(0x0) 1796 #define IO_BANK0_GPIO10_CTRL_OEOVER_BITS _u(0x00003000) 1797 #define IO_BANK0_GPIO10_CTRL_OEOVER_MSB _u(13) 1798 #define IO_BANK0_GPIO10_CTRL_OEOVER_LSB _u(12) 1799 #define IO_BANK0_GPIO10_CTRL_OEOVER_ACCESS "RW" 1800 #define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_NORMAL _u(0x0) 1801 #define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_INVERT _u(0x1) 1802 #define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_DISABLE _u(0x2) 1803 #define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_ENABLE _u(0x3) 1804 // ----------------------------------------------------------------------------- 1805 // Field : IO_BANK0_GPIO10_CTRL_OUTOVER 1806 // 0x0 -> drive output from peripheral signal selected by funcsel 1807 // 0x1 -> drive output from inverse of peripheral signal selected by funcsel 1808 // 0x2 -> drive output low 1809 // 0x3 -> drive output high 1810 #define IO_BANK0_GPIO10_CTRL_OUTOVER_RESET _u(0x0) 1811 #define IO_BANK0_GPIO10_CTRL_OUTOVER_BITS _u(0x00000300) 1812 #define IO_BANK0_GPIO10_CTRL_OUTOVER_MSB _u(9) 1813 #define IO_BANK0_GPIO10_CTRL_OUTOVER_LSB _u(8) 1814 #define IO_BANK0_GPIO10_CTRL_OUTOVER_ACCESS "RW" 1815 #define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) 1816 #define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_INVERT _u(0x1) 1817 #define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_LOW _u(0x2) 1818 #define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_HIGH _u(0x3) 1819 // ----------------------------------------------------------------------------- 1820 // Field : IO_BANK0_GPIO10_CTRL_FUNCSEL 1821 // Description : 0-31 -> selects pin function according to the gpio table 1822 // 31 == NULL 1823 // 0x01 -> spi1_sclk 1824 // 0x02 -> uart1_cts 1825 // 0x03 -> i2c1_sda 1826 // 0x04 -> pwm_a_5 1827 // 0x05 -> sio_10 1828 // 0x06 -> pio0_10 1829 // 0x07 -> pio1_10 1830 // 0x08 -> usb_muxing_extphy_vm 1831 // 0x09 -> usb_muxing_vbus_detect 1832 // 0x1f -> null 1833 #define IO_BANK0_GPIO10_CTRL_FUNCSEL_RESET _u(0x1f) 1834 #define IO_BANK0_GPIO10_CTRL_FUNCSEL_BITS _u(0x0000001f) 1835 #define IO_BANK0_GPIO10_CTRL_FUNCSEL_MSB _u(4) 1836 #define IO_BANK0_GPIO10_CTRL_FUNCSEL_LSB _u(0) 1837 #define IO_BANK0_GPIO10_CTRL_FUNCSEL_ACCESS "RW" 1838 #define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_SPI1_SCLK _u(0x01) 1839 #define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_UART1_CTS _u(0x02) 1840 #define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) 1841 #define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_PWM_A_5 _u(0x04) 1842 #define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_SIO_10 _u(0x05) 1843 #define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_PIO0_10 _u(0x06) 1844 #define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_PIO1_10 _u(0x07) 1845 #define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_VM _u(0x08) 1846 #define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09) 1847 #define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) 1848 // ============================================================================= 1849 // Register : IO_BANK0_GPIO11_STATUS 1850 // Description : GPIO status 1851 #define IO_BANK0_GPIO11_STATUS_OFFSET _u(0x00000058) 1852 #define IO_BANK0_GPIO11_STATUS_BITS _u(0x050a3300) 1853 #define IO_BANK0_GPIO11_STATUS_RESET _u(0x00000000) 1854 // ----------------------------------------------------------------------------- 1855 // Field : IO_BANK0_GPIO11_STATUS_IRQTOPROC 1856 // Description : interrupt to processors, after override is applied 1857 #define IO_BANK0_GPIO11_STATUS_IRQTOPROC_RESET _u(0x0) 1858 #define IO_BANK0_GPIO11_STATUS_IRQTOPROC_BITS _u(0x04000000) 1859 #define IO_BANK0_GPIO11_STATUS_IRQTOPROC_MSB _u(26) 1860 #define IO_BANK0_GPIO11_STATUS_IRQTOPROC_LSB _u(26) 1861 #define IO_BANK0_GPIO11_STATUS_IRQTOPROC_ACCESS "RO" 1862 // ----------------------------------------------------------------------------- 1863 // Field : IO_BANK0_GPIO11_STATUS_IRQFROMPAD 1864 // Description : interrupt from pad before override is applied 1865 #define IO_BANK0_GPIO11_STATUS_IRQFROMPAD_RESET _u(0x0) 1866 #define IO_BANK0_GPIO11_STATUS_IRQFROMPAD_BITS _u(0x01000000) 1867 #define IO_BANK0_GPIO11_STATUS_IRQFROMPAD_MSB _u(24) 1868 #define IO_BANK0_GPIO11_STATUS_IRQFROMPAD_LSB _u(24) 1869 #define IO_BANK0_GPIO11_STATUS_IRQFROMPAD_ACCESS "RO" 1870 // ----------------------------------------------------------------------------- 1871 // Field : IO_BANK0_GPIO11_STATUS_INTOPERI 1872 // Description : input signal to peripheral, after override is applied 1873 #define IO_BANK0_GPIO11_STATUS_INTOPERI_RESET _u(0x0) 1874 #define IO_BANK0_GPIO11_STATUS_INTOPERI_BITS _u(0x00080000) 1875 #define IO_BANK0_GPIO11_STATUS_INTOPERI_MSB _u(19) 1876 #define IO_BANK0_GPIO11_STATUS_INTOPERI_LSB _u(19) 1877 #define IO_BANK0_GPIO11_STATUS_INTOPERI_ACCESS "RO" 1878 // ----------------------------------------------------------------------------- 1879 // Field : IO_BANK0_GPIO11_STATUS_INFROMPAD 1880 // Description : input signal from pad, before override is applied 1881 #define IO_BANK0_GPIO11_STATUS_INFROMPAD_RESET _u(0x0) 1882 #define IO_BANK0_GPIO11_STATUS_INFROMPAD_BITS _u(0x00020000) 1883 #define IO_BANK0_GPIO11_STATUS_INFROMPAD_MSB _u(17) 1884 #define IO_BANK0_GPIO11_STATUS_INFROMPAD_LSB _u(17) 1885 #define IO_BANK0_GPIO11_STATUS_INFROMPAD_ACCESS "RO" 1886 // ----------------------------------------------------------------------------- 1887 // Field : IO_BANK0_GPIO11_STATUS_OETOPAD 1888 // Description : output enable to pad after register override is applied 1889 #define IO_BANK0_GPIO11_STATUS_OETOPAD_RESET _u(0x0) 1890 #define IO_BANK0_GPIO11_STATUS_OETOPAD_BITS _u(0x00002000) 1891 #define IO_BANK0_GPIO11_STATUS_OETOPAD_MSB _u(13) 1892 #define IO_BANK0_GPIO11_STATUS_OETOPAD_LSB _u(13) 1893 #define IO_BANK0_GPIO11_STATUS_OETOPAD_ACCESS "RO" 1894 // ----------------------------------------------------------------------------- 1895 // Field : IO_BANK0_GPIO11_STATUS_OEFROMPERI 1896 // Description : output enable from selected peripheral, before register 1897 // override is applied 1898 #define IO_BANK0_GPIO11_STATUS_OEFROMPERI_RESET _u(0x0) 1899 #define IO_BANK0_GPIO11_STATUS_OEFROMPERI_BITS _u(0x00001000) 1900 #define IO_BANK0_GPIO11_STATUS_OEFROMPERI_MSB _u(12) 1901 #define IO_BANK0_GPIO11_STATUS_OEFROMPERI_LSB _u(12) 1902 #define IO_BANK0_GPIO11_STATUS_OEFROMPERI_ACCESS "RO" 1903 // ----------------------------------------------------------------------------- 1904 // Field : IO_BANK0_GPIO11_STATUS_OUTTOPAD 1905 // Description : output signal to pad after register override is applied 1906 #define IO_BANK0_GPIO11_STATUS_OUTTOPAD_RESET _u(0x0) 1907 #define IO_BANK0_GPIO11_STATUS_OUTTOPAD_BITS _u(0x00000200) 1908 #define IO_BANK0_GPIO11_STATUS_OUTTOPAD_MSB _u(9) 1909 #define IO_BANK0_GPIO11_STATUS_OUTTOPAD_LSB _u(9) 1910 #define IO_BANK0_GPIO11_STATUS_OUTTOPAD_ACCESS "RO" 1911 // ----------------------------------------------------------------------------- 1912 // Field : IO_BANK0_GPIO11_STATUS_OUTFROMPERI 1913 // Description : output signal from selected peripheral, before register 1914 // override is applied 1915 #define IO_BANK0_GPIO11_STATUS_OUTFROMPERI_RESET _u(0x0) 1916 #define IO_BANK0_GPIO11_STATUS_OUTFROMPERI_BITS _u(0x00000100) 1917 #define IO_BANK0_GPIO11_STATUS_OUTFROMPERI_MSB _u(8) 1918 #define IO_BANK0_GPIO11_STATUS_OUTFROMPERI_LSB _u(8) 1919 #define IO_BANK0_GPIO11_STATUS_OUTFROMPERI_ACCESS "RO" 1920 // ============================================================================= 1921 // Register : IO_BANK0_GPIO11_CTRL 1922 // Description : GPIO control including function select and overrides. 1923 #define IO_BANK0_GPIO11_CTRL_OFFSET _u(0x0000005c) 1924 #define IO_BANK0_GPIO11_CTRL_BITS _u(0x3003331f) 1925 #define IO_BANK0_GPIO11_CTRL_RESET _u(0x0000001f) 1926 // ----------------------------------------------------------------------------- 1927 // Field : IO_BANK0_GPIO11_CTRL_IRQOVER 1928 // 0x0 -> don't invert the interrupt 1929 // 0x1 -> invert the interrupt 1930 // 0x2 -> drive interrupt low 1931 // 0x3 -> drive interrupt high 1932 #define IO_BANK0_GPIO11_CTRL_IRQOVER_RESET _u(0x0) 1933 #define IO_BANK0_GPIO11_CTRL_IRQOVER_BITS _u(0x30000000) 1934 #define IO_BANK0_GPIO11_CTRL_IRQOVER_MSB _u(29) 1935 #define IO_BANK0_GPIO11_CTRL_IRQOVER_LSB _u(28) 1936 #define IO_BANK0_GPIO11_CTRL_IRQOVER_ACCESS "RW" 1937 #define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) 1938 #define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_INVERT _u(0x1) 1939 #define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_LOW _u(0x2) 1940 #define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_HIGH _u(0x3) 1941 // ----------------------------------------------------------------------------- 1942 // Field : IO_BANK0_GPIO11_CTRL_INOVER 1943 // 0x0 -> don't invert the peri input 1944 // 0x1 -> invert the peri input 1945 // 0x2 -> drive peri input low 1946 // 0x3 -> drive peri input high 1947 #define IO_BANK0_GPIO11_CTRL_INOVER_RESET _u(0x0) 1948 #define IO_BANK0_GPIO11_CTRL_INOVER_BITS _u(0x00030000) 1949 #define IO_BANK0_GPIO11_CTRL_INOVER_MSB _u(17) 1950 #define IO_BANK0_GPIO11_CTRL_INOVER_LSB _u(16) 1951 #define IO_BANK0_GPIO11_CTRL_INOVER_ACCESS "RW" 1952 #define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_NORMAL _u(0x0) 1953 #define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_INVERT _u(0x1) 1954 #define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_LOW _u(0x2) 1955 #define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_HIGH _u(0x3) 1956 // ----------------------------------------------------------------------------- 1957 // Field : IO_BANK0_GPIO11_CTRL_OEOVER 1958 // 0x0 -> drive output enable from peripheral signal selected by funcsel 1959 // 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel 1960 // 0x2 -> disable output 1961 // 0x3 -> enable output 1962 #define IO_BANK0_GPIO11_CTRL_OEOVER_RESET _u(0x0) 1963 #define IO_BANK0_GPIO11_CTRL_OEOVER_BITS _u(0x00003000) 1964 #define IO_BANK0_GPIO11_CTRL_OEOVER_MSB _u(13) 1965 #define IO_BANK0_GPIO11_CTRL_OEOVER_LSB _u(12) 1966 #define IO_BANK0_GPIO11_CTRL_OEOVER_ACCESS "RW" 1967 #define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_NORMAL _u(0x0) 1968 #define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_INVERT _u(0x1) 1969 #define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_DISABLE _u(0x2) 1970 #define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_ENABLE _u(0x3) 1971 // ----------------------------------------------------------------------------- 1972 // Field : IO_BANK0_GPIO11_CTRL_OUTOVER 1973 // 0x0 -> drive output from peripheral signal selected by funcsel 1974 // 0x1 -> drive output from inverse of peripheral signal selected by funcsel 1975 // 0x2 -> drive output low 1976 // 0x3 -> drive output high 1977 #define IO_BANK0_GPIO11_CTRL_OUTOVER_RESET _u(0x0) 1978 #define IO_BANK0_GPIO11_CTRL_OUTOVER_BITS _u(0x00000300) 1979 #define IO_BANK0_GPIO11_CTRL_OUTOVER_MSB _u(9) 1980 #define IO_BANK0_GPIO11_CTRL_OUTOVER_LSB _u(8) 1981 #define IO_BANK0_GPIO11_CTRL_OUTOVER_ACCESS "RW" 1982 #define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) 1983 #define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_INVERT _u(0x1) 1984 #define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_LOW _u(0x2) 1985 #define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_HIGH _u(0x3) 1986 // ----------------------------------------------------------------------------- 1987 // Field : IO_BANK0_GPIO11_CTRL_FUNCSEL 1988 // Description : 0-31 -> selects pin function according to the gpio table 1989 // 31 == NULL 1990 // 0x01 -> spi1_tx 1991 // 0x02 -> uart1_rts 1992 // 0x03 -> i2c1_scl 1993 // 0x04 -> pwm_b_5 1994 // 0x05 -> sio_11 1995 // 0x06 -> pio0_11 1996 // 0x07 -> pio1_11 1997 // 0x08 -> usb_muxing_extphy_suspnd 1998 // 0x09 -> usb_muxing_vbus_en 1999 // 0x1f -> null 2000 #define IO_BANK0_GPIO11_CTRL_FUNCSEL_RESET _u(0x1f) 2001 #define IO_BANK0_GPIO11_CTRL_FUNCSEL_BITS _u(0x0000001f) 2002 #define IO_BANK0_GPIO11_CTRL_FUNCSEL_MSB _u(4) 2003 #define IO_BANK0_GPIO11_CTRL_FUNCSEL_LSB _u(0) 2004 #define IO_BANK0_GPIO11_CTRL_FUNCSEL_ACCESS "RW" 2005 #define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_SPI1_TX _u(0x01) 2006 #define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_UART1_RTS _u(0x02) 2007 #define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) 2008 #define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_PWM_B_5 _u(0x04) 2009 #define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_SIO_11 _u(0x05) 2010 #define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_PIO0_11 _u(0x06) 2011 #define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_PIO1_11 _u(0x07) 2012 #define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_SUSPND _u(0x08) 2013 #define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09) 2014 #define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) 2015 // ============================================================================= 2016 // Register : IO_BANK0_GPIO12_STATUS 2017 // Description : GPIO status 2018 #define IO_BANK0_GPIO12_STATUS_OFFSET _u(0x00000060) 2019 #define IO_BANK0_GPIO12_STATUS_BITS _u(0x050a3300) 2020 #define IO_BANK0_GPIO12_STATUS_RESET _u(0x00000000) 2021 // ----------------------------------------------------------------------------- 2022 // Field : IO_BANK0_GPIO12_STATUS_IRQTOPROC 2023 // Description : interrupt to processors, after override is applied 2024 #define IO_BANK0_GPIO12_STATUS_IRQTOPROC_RESET _u(0x0) 2025 #define IO_BANK0_GPIO12_STATUS_IRQTOPROC_BITS _u(0x04000000) 2026 #define IO_BANK0_GPIO12_STATUS_IRQTOPROC_MSB _u(26) 2027 #define IO_BANK0_GPIO12_STATUS_IRQTOPROC_LSB _u(26) 2028 #define IO_BANK0_GPIO12_STATUS_IRQTOPROC_ACCESS "RO" 2029 // ----------------------------------------------------------------------------- 2030 // Field : IO_BANK0_GPIO12_STATUS_IRQFROMPAD 2031 // Description : interrupt from pad before override is applied 2032 #define IO_BANK0_GPIO12_STATUS_IRQFROMPAD_RESET _u(0x0) 2033 #define IO_BANK0_GPIO12_STATUS_IRQFROMPAD_BITS _u(0x01000000) 2034 #define IO_BANK0_GPIO12_STATUS_IRQFROMPAD_MSB _u(24) 2035 #define IO_BANK0_GPIO12_STATUS_IRQFROMPAD_LSB _u(24) 2036 #define IO_BANK0_GPIO12_STATUS_IRQFROMPAD_ACCESS "RO" 2037 // ----------------------------------------------------------------------------- 2038 // Field : IO_BANK0_GPIO12_STATUS_INTOPERI 2039 // Description : input signal to peripheral, after override is applied 2040 #define IO_BANK0_GPIO12_STATUS_INTOPERI_RESET _u(0x0) 2041 #define IO_BANK0_GPIO12_STATUS_INTOPERI_BITS _u(0x00080000) 2042 #define IO_BANK0_GPIO12_STATUS_INTOPERI_MSB _u(19) 2043 #define IO_BANK0_GPIO12_STATUS_INTOPERI_LSB _u(19) 2044 #define IO_BANK0_GPIO12_STATUS_INTOPERI_ACCESS "RO" 2045 // ----------------------------------------------------------------------------- 2046 // Field : IO_BANK0_GPIO12_STATUS_INFROMPAD 2047 // Description : input signal from pad, before override is applied 2048 #define IO_BANK0_GPIO12_STATUS_INFROMPAD_RESET _u(0x0) 2049 #define IO_BANK0_GPIO12_STATUS_INFROMPAD_BITS _u(0x00020000) 2050 #define IO_BANK0_GPIO12_STATUS_INFROMPAD_MSB _u(17) 2051 #define IO_BANK0_GPIO12_STATUS_INFROMPAD_LSB _u(17) 2052 #define IO_BANK0_GPIO12_STATUS_INFROMPAD_ACCESS "RO" 2053 // ----------------------------------------------------------------------------- 2054 // Field : IO_BANK0_GPIO12_STATUS_OETOPAD 2055 // Description : output enable to pad after register override is applied 2056 #define IO_BANK0_GPIO12_STATUS_OETOPAD_RESET _u(0x0) 2057 #define IO_BANK0_GPIO12_STATUS_OETOPAD_BITS _u(0x00002000) 2058 #define IO_BANK0_GPIO12_STATUS_OETOPAD_MSB _u(13) 2059 #define IO_BANK0_GPIO12_STATUS_OETOPAD_LSB _u(13) 2060 #define IO_BANK0_GPIO12_STATUS_OETOPAD_ACCESS "RO" 2061 // ----------------------------------------------------------------------------- 2062 // Field : IO_BANK0_GPIO12_STATUS_OEFROMPERI 2063 // Description : output enable from selected peripheral, before register 2064 // override is applied 2065 #define IO_BANK0_GPIO12_STATUS_OEFROMPERI_RESET _u(0x0) 2066 #define IO_BANK0_GPIO12_STATUS_OEFROMPERI_BITS _u(0x00001000) 2067 #define IO_BANK0_GPIO12_STATUS_OEFROMPERI_MSB _u(12) 2068 #define IO_BANK0_GPIO12_STATUS_OEFROMPERI_LSB _u(12) 2069 #define IO_BANK0_GPIO12_STATUS_OEFROMPERI_ACCESS "RO" 2070 // ----------------------------------------------------------------------------- 2071 // Field : IO_BANK0_GPIO12_STATUS_OUTTOPAD 2072 // Description : output signal to pad after register override is applied 2073 #define IO_BANK0_GPIO12_STATUS_OUTTOPAD_RESET _u(0x0) 2074 #define IO_BANK0_GPIO12_STATUS_OUTTOPAD_BITS _u(0x00000200) 2075 #define IO_BANK0_GPIO12_STATUS_OUTTOPAD_MSB _u(9) 2076 #define IO_BANK0_GPIO12_STATUS_OUTTOPAD_LSB _u(9) 2077 #define IO_BANK0_GPIO12_STATUS_OUTTOPAD_ACCESS "RO" 2078 // ----------------------------------------------------------------------------- 2079 // Field : IO_BANK0_GPIO12_STATUS_OUTFROMPERI 2080 // Description : output signal from selected peripheral, before register 2081 // override is applied 2082 #define IO_BANK0_GPIO12_STATUS_OUTFROMPERI_RESET _u(0x0) 2083 #define IO_BANK0_GPIO12_STATUS_OUTFROMPERI_BITS _u(0x00000100) 2084 #define IO_BANK0_GPIO12_STATUS_OUTFROMPERI_MSB _u(8) 2085 #define IO_BANK0_GPIO12_STATUS_OUTFROMPERI_LSB _u(8) 2086 #define IO_BANK0_GPIO12_STATUS_OUTFROMPERI_ACCESS "RO" 2087 // ============================================================================= 2088 // Register : IO_BANK0_GPIO12_CTRL 2089 // Description : GPIO control including function select and overrides. 2090 #define IO_BANK0_GPIO12_CTRL_OFFSET _u(0x00000064) 2091 #define IO_BANK0_GPIO12_CTRL_BITS _u(0x3003331f) 2092 #define IO_BANK0_GPIO12_CTRL_RESET _u(0x0000001f) 2093 // ----------------------------------------------------------------------------- 2094 // Field : IO_BANK0_GPIO12_CTRL_IRQOVER 2095 // 0x0 -> don't invert the interrupt 2096 // 0x1 -> invert the interrupt 2097 // 0x2 -> drive interrupt low 2098 // 0x3 -> drive interrupt high 2099 #define IO_BANK0_GPIO12_CTRL_IRQOVER_RESET _u(0x0) 2100 #define IO_BANK0_GPIO12_CTRL_IRQOVER_BITS _u(0x30000000) 2101 #define IO_BANK0_GPIO12_CTRL_IRQOVER_MSB _u(29) 2102 #define IO_BANK0_GPIO12_CTRL_IRQOVER_LSB _u(28) 2103 #define IO_BANK0_GPIO12_CTRL_IRQOVER_ACCESS "RW" 2104 #define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) 2105 #define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_INVERT _u(0x1) 2106 #define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_LOW _u(0x2) 2107 #define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_HIGH _u(0x3) 2108 // ----------------------------------------------------------------------------- 2109 // Field : IO_BANK0_GPIO12_CTRL_INOVER 2110 // 0x0 -> don't invert the peri input 2111 // 0x1 -> invert the peri input 2112 // 0x2 -> drive peri input low 2113 // 0x3 -> drive peri input high 2114 #define IO_BANK0_GPIO12_CTRL_INOVER_RESET _u(0x0) 2115 #define IO_BANK0_GPIO12_CTRL_INOVER_BITS _u(0x00030000) 2116 #define IO_BANK0_GPIO12_CTRL_INOVER_MSB _u(17) 2117 #define IO_BANK0_GPIO12_CTRL_INOVER_LSB _u(16) 2118 #define IO_BANK0_GPIO12_CTRL_INOVER_ACCESS "RW" 2119 #define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_NORMAL _u(0x0) 2120 #define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_INVERT _u(0x1) 2121 #define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_LOW _u(0x2) 2122 #define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_HIGH _u(0x3) 2123 // ----------------------------------------------------------------------------- 2124 // Field : IO_BANK0_GPIO12_CTRL_OEOVER 2125 // 0x0 -> drive output enable from peripheral signal selected by funcsel 2126 // 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel 2127 // 0x2 -> disable output 2128 // 0x3 -> enable output 2129 #define IO_BANK0_GPIO12_CTRL_OEOVER_RESET _u(0x0) 2130 #define IO_BANK0_GPIO12_CTRL_OEOVER_BITS _u(0x00003000) 2131 #define IO_BANK0_GPIO12_CTRL_OEOVER_MSB _u(13) 2132 #define IO_BANK0_GPIO12_CTRL_OEOVER_LSB _u(12) 2133 #define IO_BANK0_GPIO12_CTRL_OEOVER_ACCESS "RW" 2134 #define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_NORMAL _u(0x0) 2135 #define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_INVERT _u(0x1) 2136 #define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_DISABLE _u(0x2) 2137 #define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_ENABLE _u(0x3) 2138 // ----------------------------------------------------------------------------- 2139 // Field : IO_BANK0_GPIO12_CTRL_OUTOVER 2140 // 0x0 -> drive output from peripheral signal selected by funcsel 2141 // 0x1 -> drive output from inverse of peripheral signal selected by funcsel 2142 // 0x2 -> drive output low 2143 // 0x3 -> drive output high 2144 #define IO_BANK0_GPIO12_CTRL_OUTOVER_RESET _u(0x0) 2145 #define IO_BANK0_GPIO12_CTRL_OUTOVER_BITS _u(0x00000300) 2146 #define IO_BANK0_GPIO12_CTRL_OUTOVER_MSB _u(9) 2147 #define IO_BANK0_GPIO12_CTRL_OUTOVER_LSB _u(8) 2148 #define IO_BANK0_GPIO12_CTRL_OUTOVER_ACCESS "RW" 2149 #define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) 2150 #define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_INVERT _u(0x1) 2151 #define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_LOW _u(0x2) 2152 #define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_HIGH _u(0x3) 2153 // ----------------------------------------------------------------------------- 2154 // Field : IO_BANK0_GPIO12_CTRL_FUNCSEL 2155 // Description : 0-31 -> selects pin function according to the gpio table 2156 // 31 == NULL 2157 // 0x01 -> spi1_rx 2158 // 0x02 -> uart0_tx 2159 // 0x03 -> i2c0_sda 2160 // 0x04 -> pwm_a_6 2161 // 0x05 -> sio_12 2162 // 0x06 -> pio0_12 2163 // 0x07 -> pio1_12 2164 // 0x08 -> usb_muxing_extphy_speed 2165 // 0x09 -> usb_muxing_overcurr_detect 2166 // 0x1f -> null 2167 #define IO_BANK0_GPIO12_CTRL_FUNCSEL_RESET _u(0x1f) 2168 #define IO_BANK0_GPIO12_CTRL_FUNCSEL_BITS _u(0x0000001f) 2169 #define IO_BANK0_GPIO12_CTRL_FUNCSEL_MSB _u(4) 2170 #define IO_BANK0_GPIO12_CTRL_FUNCSEL_LSB _u(0) 2171 #define IO_BANK0_GPIO12_CTRL_FUNCSEL_ACCESS "RW" 2172 #define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_SPI1_RX _u(0x01) 2173 #define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x02) 2174 #define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) 2175 #define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_PWM_A_6 _u(0x04) 2176 #define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_SIO_12 _u(0x05) 2177 #define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_PIO0_12 _u(0x06) 2178 #define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_PIO1_12 _u(0x07) 2179 #define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_SPEED _u(0x08) 2180 #define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09) 2181 #define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) 2182 // ============================================================================= 2183 // Register : IO_BANK0_GPIO13_STATUS 2184 // Description : GPIO status 2185 #define IO_BANK0_GPIO13_STATUS_OFFSET _u(0x00000068) 2186 #define IO_BANK0_GPIO13_STATUS_BITS _u(0x050a3300) 2187 #define IO_BANK0_GPIO13_STATUS_RESET _u(0x00000000) 2188 // ----------------------------------------------------------------------------- 2189 // Field : IO_BANK0_GPIO13_STATUS_IRQTOPROC 2190 // Description : interrupt to processors, after override is applied 2191 #define IO_BANK0_GPIO13_STATUS_IRQTOPROC_RESET _u(0x0) 2192 #define IO_BANK0_GPIO13_STATUS_IRQTOPROC_BITS _u(0x04000000) 2193 #define IO_BANK0_GPIO13_STATUS_IRQTOPROC_MSB _u(26) 2194 #define IO_BANK0_GPIO13_STATUS_IRQTOPROC_LSB _u(26) 2195 #define IO_BANK0_GPIO13_STATUS_IRQTOPROC_ACCESS "RO" 2196 // ----------------------------------------------------------------------------- 2197 // Field : IO_BANK0_GPIO13_STATUS_IRQFROMPAD 2198 // Description : interrupt from pad before override is applied 2199 #define IO_BANK0_GPIO13_STATUS_IRQFROMPAD_RESET _u(0x0) 2200 #define IO_BANK0_GPIO13_STATUS_IRQFROMPAD_BITS _u(0x01000000) 2201 #define IO_BANK0_GPIO13_STATUS_IRQFROMPAD_MSB _u(24) 2202 #define IO_BANK0_GPIO13_STATUS_IRQFROMPAD_LSB _u(24) 2203 #define IO_BANK0_GPIO13_STATUS_IRQFROMPAD_ACCESS "RO" 2204 // ----------------------------------------------------------------------------- 2205 // Field : IO_BANK0_GPIO13_STATUS_INTOPERI 2206 // Description : input signal to peripheral, after override is applied 2207 #define IO_BANK0_GPIO13_STATUS_INTOPERI_RESET _u(0x0) 2208 #define IO_BANK0_GPIO13_STATUS_INTOPERI_BITS _u(0x00080000) 2209 #define IO_BANK0_GPIO13_STATUS_INTOPERI_MSB _u(19) 2210 #define IO_BANK0_GPIO13_STATUS_INTOPERI_LSB _u(19) 2211 #define IO_BANK0_GPIO13_STATUS_INTOPERI_ACCESS "RO" 2212 // ----------------------------------------------------------------------------- 2213 // Field : IO_BANK0_GPIO13_STATUS_INFROMPAD 2214 // Description : input signal from pad, before override is applied 2215 #define IO_BANK0_GPIO13_STATUS_INFROMPAD_RESET _u(0x0) 2216 #define IO_BANK0_GPIO13_STATUS_INFROMPAD_BITS _u(0x00020000) 2217 #define IO_BANK0_GPIO13_STATUS_INFROMPAD_MSB _u(17) 2218 #define IO_BANK0_GPIO13_STATUS_INFROMPAD_LSB _u(17) 2219 #define IO_BANK0_GPIO13_STATUS_INFROMPAD_ACCESS "RO" 2220 // ----------------------------------------------------------------------------- 2221 // Field : IO_BANK0_GPIO13_STATUS_OETOPAD 2222 // Description : output enable to pad after register override is applied 2223 #define IO_BANK0_GPIO13_STATUS_OETOPAD_RESET _u(0x0) 2224 #define IO_BANK0_GPIO13_STATUS_OETOPAD_BITS _u(0x00002000) 2225 #define IO_BANK0_GPIO13_STATUS_OETOPAD_MSB _u(13) 2226 #define IO_BANK0_GPIO13_STATUS_OETOPAD_LSB _u(13) 2227 #define IO_BANK0_GPIO13_STATUS_OETOPAD_ACCESS "RO" 2228 // ----------------------------------------------------------------------------- 2229 // Field : IO_BANK0_GPIO13_STATUS_OEFROMPERI 2230 // Description : output enable from selected peripheral, before register 2231 // override is applied 2232 #define IO_BANK0_GPIO13_STATUS_OEFROMPERI_RESET _u(0x0) 2233 #define IO_BANK0_GPIO13_STATUS_OEFROMPERI_BITS _u(0x00001000) 2234 #define IO_BANK0_GPIO13_STATUS_OEFROMPERI_MSB _u(12) 2235 #define IO_BANK0_GPIO13_STATUS_OEFROMPERI_LSB _u(12) 2236 #define IO_BANK0_GPIO13_STATUS_OEFROMPERI_ACCESS "RO" 2237 // ----------------------------------------------------------------------------- 2238 // Field : IO_BANK0_GPIO13_STATUS_OUTTOPAD 2239 // Description : output signal to pad after register override is applied 2240 #define IO_BANK0_GPIO13_STATUS_OUTTOPAD_RESET _u(0x0) 2241 #define IO_BANK0_GPIO13_STATUS_OUTTOPAD_BITS _u(0x00000200) 2242 #define IO_BANK0_GPIO13_STATUS_OUTTOPAD_MSB _u(9) 2243 #define IO_BANK0_GPIO13_STATUS_OUTTOPAD_LSB _u(9) 2244 #define IO_BANK0_GPIO13_STATUS_OUTTOPAD_ACCESS "RO" 2245 // ----------------------------------------------------------------------------- 2246 // Field : IO_BANK0_GPIO13_STATUS_OUTFROMPERI 2247 // Description : output signal from selected peripheral, before register 2248 // override is applied 2249 #define IO_BANK0_GPIO13_STATUS_OUTFROMPERI_RESET _u(0x0) 2250 #define IO_BANK0_GPIO13_STATUS_OUTFROMPERI_BITS _u(0x00000100) 2251 #define IO_BANK0_GPIO13_STATUS_OUTFROMPERI_MSB _u(8) 2252 #define IO_BANK0_GPIO13_STATUS_OUTFROMPERI_LSB _u(8) 2253 #define IO_BANK0_GPIO13_STATUS_OUTFROMPERI_ACCESS "RO" 2254 // ============================================================================= 2255 // Register : IO_BANK0_GPIO13_CTRL 2256 // Description : GPIO control including function select and overrides. 2257 #define IO_BANK0_GPIO13_CTRL_OFFSET _u(0x0000006c) 2258 #define IO_BANK0_GPIO13_CTRL_BITS _u(0x3003331f) 2259 #define IO_BANK0_GPIO13_CTRL_RESET _u(0x0000001f) 2260 // ----------------------------------------------------------------------------- 2261 // Field : IO_BANK0_GPIO13_CTRL_IRQOVER 2262 // 0x0 -> don't invert the interrupt 2263 // 0x1 -> invert the interrupt 2264 // 0x2 -> drive interrupt low 2265 // 0x3 -> drive interrupt high 2266 #define IO_BANK0_GPIO13_CTRL_IRQOVER_RESET _u(0x0) 2267 #define IO_BANK0_GPIO13_CTRL_IRQOVER_BITS _u(0x30000000) 2268 #define IO_BANK0_GPIO13_CTRL_IRQOVER_MSB _u(29) 2269 #define IO_BANK0_GPIO13_CTRL_IRQOVER_LSB _u(28) 2270 #define IO_BANK0_GPIO13_CTRL_IRQOVER_ACCESS "RW" 2271 #define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) 2272 #define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_INVERT _u(0x1) 2273 #define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_LOW _u(0x2) 2274 #define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_HIGH _u(0x3) 2275 // ----------------------------------------------------------------------------- 2276 // Field : IO_BANK0_GPIO13_CTRL_INOVER 2277 // 0x0 -> don't invert the peri input 2278 // 0x1 -> invert the peri input 2279 // 0x2 -> drive peri input low 2280 // 0x3 -> drive peri input high 2281 #define IO_BANK0_GPIO13_CTRL_INOVER_RESET _u(0x0) 2282 #define IO_BANK0_GPIO13_CTRL_INOVER_BITS _u(0x00030000) 2283 #define IO_BANK0_GPIO13_CTRL_INOVER_MSB _u(17) 2284 #define IO_BANK0_GPIO13_CTRL_INOVER_LSB _u(16) 2285 #define IO_BANK0_GPIO13_CTRL_INOVER_ACCESS "RW" 2286 #define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_NORMAL _u(0x0) 2287 #define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_INVERT _u(0x1) 2288 #define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_LOW _u(0x2) 2289 #define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_HIGH _u(0x3) 2290 // ----------------------------------------------------------------------------- 2291 // Field : IO_BANK0_GPIO13_CTRL_OEOVER 2292 // 0x0 -> drive output enable from peripheral signal selected by funcsel 2293 // 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel 2294 // 0x2 -> disable output 2295 // 0x3 -> enable output 2296 #define IO_BANK0_GPIO13_CTRL_OEOVER_RESET _u(0x0) 2297 #define IO_BANK0_GPIO13_CTRL_OEOVER_BITS _u(0x00003000) 2298 #define IO_BANK0_GPIO13_CTRL_OEOVER_MSB _u(13) 2299 #define IO_BANK0_GPIO13_CTRL_OEOVER_LSB _u(12) 2300 #define IO_BANK0_GPIO13_CTRL_OEOVER_ACCESS "RW" 2301 #define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_NORMAL _u(0x0) 2302 #define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_INVERT _u(0x1) 2303 #define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_DISABLE _u(0x2) 2304 #define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_ENABLE _u(0x3) 2305 // ----------------------------------------------------------------------------- 2306 // Field : IO_BANK0_GPIO13_CTRL_OUTOVER 2307 // 0x0 -> drive output from peripheral signal selected by funcsel 2308 // 0x1 -> drive output from inverse of peripheral signal selected by funcsel 2309 // 0x2 -> drive output low 2310 // 0x3 -> drive output high 2311 #define IO_BANK0_GPIO13_CTRL_OUTOVER_RESET _u(0x0) 2312 #define IO_BANK0_GPIO13_CTRL_OUTOVER_BITS _u(0x00000300) 2313 #define IO_BANK0_GPIO13_CTRL_OUTOVER_MSB _u(9) 2314 #define IO_BANK0_GPIO13_CTRL_OUTOVER_LSB _u(8) 2315 #define IO_BANK0_GPIO13_CTRL_OUTOVER_ACCESS "RW" 2316 #define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) 2317 #define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_INVERT _u(0x1) 2318 #define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_LOW _u(0x2) 2319 #define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_HIGH _u(0x3) 2320 // ----------------------------------------------------------------------------- 2321 // Field : IO_BANK0_GPIO13_CTRL_FUNCSEL 2322 // Description : 0-31 -> selects pin function according to the gpio table 2323 // 31 == NULL 2324 // 0x01 -> spi1_ss_n 2325 // 0x02 -> uart0_rx 2326 // 0x03 -> i2c0_scl 2327 // 0x04 -> pwm_b_6 2328 // 0x05 -> sio_13 2329 // 0x06 -> pio0_13 2330 // 0x07 -> pio1_13 2331 // 0x08 -> usb_muxing_extphy_vpo 2332 // 0x09 -> usb_muxing_vbus_detect 2333 // 0x1f -> null 2334 #define IO_BANK0_GPIO13_CTRL_FUNCSEL_RESET _u(0x1f) 2335 #define IO_BANK0_GPIO13_CTRL_FUNCSEL_BITS _u(0x0000001f) 2336 #define IO_BANK0_GPIO13_CTRL_FUNCSEL_MSB _u(4) 2337 #define IO_BANK0_GPIO13_CTRL_FUNCSEL_LSB _u(0) 2338 #define IO_BANK0_GPIO13_CTRL_FUNCSEL_ACCESS "RW" 2339 #define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_SPI1_SS_N _u(0x01) 2340 #define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x02) 2341 #define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) 2342 #define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_PWM_B_6 _u(0x04) 2343 #define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_SIO_13 _u(0x05) 2344 #define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_PIO0_13 _u(0x06) 2345 #define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_PIO1_13 _u(0x07) 2346 #define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_VPO _u(0x08) 2347 #define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09) 2348 #define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) 2349 // ============================================================================= 2350 // Register : IO_BANK0_GPIO14_STATUS 2351 // Description : GPIO status 2352 #define IO_BANK0_GPIO14_STATUS_OFFSET _u(0x00000070) 2353 #define IO_BANK0_GPIO14_STATUS_BITS _u(0x050a3300) 2354 #define IO_BANK0_GPIO14_STATUS_RESET _u(0x00000000) 2355 // ----------------------------------------------------------------------------- 2356 // Field : IO_BANK0_GPIO14_STATUS_IRQTOPROC 2357 // Description : interrupt to processors, after override is applied 2358 #define IO_BANK0_GPIO14_STATUS_IRQTOPROC_RESET _u(0x0) 2359 #define IO_BANK0_GPIO14_STATUS_IRQTOPROC_BITS _u(0x04000000) 2360 #define IO_BANK0_GPIO14_STATUS_IRQTOPROC_MSB _u(26) 2361 #define IO_BANK0_GPIO14_STATUS_IRQTOPROC_LSB _u(26) 2362 #define IO_BANK0_GPIO14_STATUS_IRQTOPROC_ACCESS "RO" 2363 // ----------------------------------------------------------------------------- 2364 // Field : IO_BANK0_GPIO14_STATUS_IRQFROMPAD 2365 // Description : interrupt from pad before override is applied 2366 #define IO_BANK0_GPIO14_STATUS_IRQFROMPAD_RESET _u(0x0) 2367 #define IO_BANK0_GPIO14_STATUS_IRQFROMPAD_BITS _u(0x01000000) 2368 #define IO_BANK0_GPIO14_STATUS_IRQFROMPAD_MSB _u(24) 2369 #define IO_BANK0_GPIO14_STATUS_IRQFROMPAD_LSB _u(24) 2370 #define IO_BANK0_GPIO14_STATUS_IRQFROMPAD_ACCESS "RO" 2371 // ----------------------------------------------------------------------------- 2372 // Field : IO_BANK0_GPIO14_STATUS_INTOPERI 2373 // Description : input signal to peripheral, after override is applied 2374 #define IO_BANK0_GPIO14_STATUS_INTOPERI_RESET _u(0x0) 2375 #define IO_BANK0_GPIO14_STATUS_INTOPERI_BITS _u(0x00080000) 2376 #define IO_BANK0_GPIO14_STATUS_INTOPERI_MSB _u(19) 2377 #define IO_BANK0_GPIO14_STATUS_INTOPERI_LSB _u(19) 2378 #define IO_BANK0_GPIO14_STATUS_INTOPERI_ACCESS "RO" 2379 // ----------------------------------------------------------------------------- 2380 // Field : IO_BANK0_GPIO14_STATUS_INFROMPAD 2381 // Description : input signal from pad, before override is applied 2382 #define IO_BANK0_GPIO14_STATUS_INFROMPAD_RESET _u(0x0) 2383 #define IO_BANK0_GPIO14_STATUS_INFROMPAD_BITS _u(0x00020000) 2384 #define IO_BANK0_GPIO14_STATUS_INFROMPAD_MSB _u(17) 2385 #define IO_BANK0_GPIO14_STATUS_INFROMPAD_LSB _u(17) 2386 #define IO_BANK0_GPIO14_STATUS_INFROMPAD_ACCESS "RO" 2387 // ----------------------------------------------------------------------------- 2388 // Field : IO_BANK0_GPIO14_STATUS_OETOPAD 2389 // Description : output enable to pad after register override is applied 2390 #define IO_BANK0_GPIO14_STATUS_OETOPAD_RESET _u(0x0) 2391 #define IO_BANK0_GPIO14_STATUS_OETOPAD_BITS _u(0x00002000) 2392 #define IO_BANK0_GPIO14_STATUS_OETOPAD_MSB _u(13) 2393 #define IO_BANK0_GPIO14_STATUS_OETOPAD_LSB _u(13) 2394 #define IO_BANK0_GPIO14_STATUS_OETOPAD_ACCESS "RO" 2395 // ----------------------------------------------------------------------------- 2396 // Field : IO_BANK0_GPIO14_STATUS_OEFROMPERI 2397 // Description : output enable from selected peripheral, before register 2398 // override is applied 2399 #define IO_BANK0_GPIO14_STATUS_OEFROMPERI_RESET _u(0x0) 2400 #define IO_BANK0_GPIO14_STATUS_OEFROMPERI_BITS _u(0x00001000) 2401 #define IO_BANK0_GPIO14_STATUS_OEFROMPERI_MSB _u(12) 2402 #define IO_BANK0_GPIO14_STATUS_OEFROMPERI_LSB _u(12) 2403 #define IO_BANK0_GPIO14_STATUS_OEFROMPERI_ACCESS "RO" 2404 // ----------------------------------------------------------------------------- 2405 // Field : IO_BANK0_GPIO14_STATUS_OUTTOPAD 2406 // Description : output signal to pad after register override is applied 2407 #define IO_BANK0_GPIO14_STATUS_OUTTOPAD_RESET _u(0x0) 2408 #define IO_BANK0_GPIO14_STATUS_OUTTOPAD_BITS _u(0x00000200) 2409 #define IO_BANK0_GPIO14_STATUS_OUTTOPAD_MSB _u(9) 2410 #define IO_BANK0_GPIO14_STATUS_OUTTOPAD_LSB _u(9) 2411 #define IO_BANK0_GPIO14_STATUS_OUTTOPAD_ACCESS "RO" 2412 // ----------------------------------------------------------------------------- 2413 // Field : IO_BANK0_GPIO14_STATUS_OUTFROMPERI 2414 // Description : output signal from selected peripheral, before register 2415 // override is applied 2416 #define IO_BANK0_GPIO14_STATUS_OUTFROMPERI_RESET _u(0x0) 2417 #define IO_BANK0_GPIO14_STATUS_OUTFROMPERI_BITS _u(0x00000100) 2418 #define IO_BANK0_GPIO14_STATUS_OUTFROMPERI_MSB _u(8) 2419 #define IO_BANK0_GPIO14_STATUS_OUTFROMPERI_LSB _u(8) 2420 #define IO_BANK0_GPIO14_STATUS_OUTFROMPERI_ACCESS "RO" 2421 // ============================================================================= 2422 // Register : IO_BANK0_GPIO14_CTRL 2423 // Description : GPIO control including function select and overrides. 2424 #define IO_BANK0_GPIO14_CTRL_OFFSET _u(0x00000074) 2425 #define IO_BANK0_GPIO14_CTRL_BITS _u(0x3003331f) 2426 #define IO_BANK0_GPIO14_CTRL_RESET _u(0x0000001f) 2427 // ----------------------------------------------------------------------------- 2428 // Field : IO_BANK0_GPIO14_CTRL_IRQOVER 2429 // 0x0 -> don't invert the interrupt 2430 // 0x1 -> invert the interrupt 2431 // 0x2 -> drive interrupt low 2432 // 0x3 -> drive interrupt high 2433 #define IO_BANK0_GPIO14_CTRL_IRQOVER_RESET _u(0x0) 2434 #define IO_BANK0_GPIO14_CTRL_IRQOVER_BITS _u(0x30000000) 2435 #define IO_BANK0_GPIO14_CTRL_IRQOVER_MSB _u(29) 2436 #define IO_BANK0_GPIO14_CTRL_IRQOVER_LSB _u(28) 2437 #define IO_BANK0_GPIO14_CTRL_IRQOVER_ACCESS "RW" 2438 #define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) 2439 #define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_INVERT _u(0x1) 2440 #define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_LOW _u(0x2) 2441 #define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_HIGH _u(0x3) 2442 // ----------------------------------------------------------------------------- 2443 // Field : IO_BANK0_GPIO14_CTRL_INOVER 2444 // 0x0 -> don't invert the peri input 2445 // 0x1 -> invert the peri input 2446 // 0x2 -> drive peri input low 2447 // 0x3 -> drive peri input high 2448 #define IO_BANK0_GPIO14_CTRL_INOVER_RESET _u(0x0) 2449 #define IO_BANK0_GPIO14_CTRL_INOVER_BITS _u(0x00030000) 2450 #define IO_BANK0_GPIO14_CTRL_INOVER_MSB _u(17) 2451 #define IO_BANK0_GPIO14_CTRL_INOVER_LSB _u(16) 2452 #define IO_BANK0_GPIO14_CTRL_INOVER_ACCESS "RW" 2453 #define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_NORMAL _u(0x0) 2454 #define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_INVERT _u(0x1) 2455 #define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_LOW _u(0x2) 2456 #define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_HIGH _u(0x3) 2457 // ----------------------------------------------------------------------------- 2458 // Field : IO_BANK0_GPIO14_CTRL_OEOVER 2459 // 0x0 -> drive output enable from peripheral signal selected by funcsel 2460 // 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel 2461 // 0x2 -> disable output 2462 // 0x3 -> enable output 2463 #define IO_BANK0_GPIO14_CTRL_OEOVER_RESET _u(0x0) 2464 #define IO_BANK0_GPIO14_CTRL_OEOVER_BITS _u(0x00003000) 2465 #define IO_BANK0_GPIO14_CTRL_OEOVER_MSB _u(13) 2466 #define IO_BANK0_GPIO14_CTRL_OEOVER_LSB _u(12) 2467 #define IO_BANK0_GPIO14_CTRL_OEOVER_ACCESS "RW" 2468 #define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_NORMAL _u(0x0) 2469 #define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_INVERT _u(0x1) 2470 #define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_DISABLE _u(0x2) 2471 #define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_ENABLE _u(0x3) 2472 // ----------------------------------------------------------------------------- 2473 // Field : IO_BANK0_GPIO14_CTRL_OUTOVER 2474 // 0x0 -> drive output from peripheral signal selected by funcsel 2475 // 0x1 -> drive output from inverse of peripheral signal selected by funcsel 2476 // 0x2 -> drive output low 2477 // 0x3 -> drive output high 2478 #define IO_BANK0_GPIO14_CTRL_OUTOVER_RESET _u(0x0) 2479 #define IO_BANK0_GPIO14_CTRL_OUTOVER_BITS _u(0x00000300) 2480 #define IO_BANK0_GPIO14_CTRL_OUTOVER_MSB _u(9) 2481 #define IO_BANK0_GPIO14_CTRL_OUTOVER_LSB _u(8) 2482 #define IO_BANK0_GPIO14_CTRL_OUTOVER_ACCESS "RW" 2483 #define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) 2484 #define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_INVERT _u(0x1) 2485 #define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_LOW _u(0x2) 2486 #define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_HIGH _u(0x3) 2487 // ----------------------------------------------------------------------------- 2488 // Field : IO_BANK0_GPIO14_CTRL_FUNCSEL 2489 // Description : 0-31 -> selects pin function according to the gpio table 2490 // 31 == NULL 2491 // 0x01 -> spi1_sclk 2492 // 0x02 -> uart0_cts 2493 // 0x03 -> i2c1_sda 2494 // 0x04 -> pwm_a_7 2495 // 0x05 -> sio_14 2496 // 0x06 -> pio0_14 2497 // 0x07 -> pio1_14 2498 // 0x08 -> usb_muxing_extphy_vmo 2499 // 0x09 -> usb_muxing_vbus_en 2500 // 0x1f -> null 2501 #define IO_BANK0_GPIO14_CTRL_FUNCSEL_RESET _u(0x1f) 2502 #define IO_BANK0_GPIO14_CTRL_FUNCSEL_BITS _u(0x0000001f) 2503 #define IO_BANK0_GPIO14_CTRL_FUNCSEL_MSB _u(4) 2504 #define IO_BANK0_GPIO14_CTRL_FUNCSEL_LSB _u(0) 2505 #define IO_BANK0_GPIO14_CTRL_FUNCSEL_ACCESS "RW" 2506 #define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_SPI1_SCLK _u(0x01) 2507 #define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_UART0_CTS _u(0x02) 2508 #define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) 2509 #define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_PWM_A_7 _u(0x04) 2510 #define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_SIO_14 _u(0x05) 2511 #define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_PIO0_14 _u(0x06) 2512 #define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_PIO1_14 _u(0x07) 2513 #define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_VMO _u(0x08) 2514 #define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09) 2515 #define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) 2516 // ============================================================================= 2517 // Register : IO_BANK0_GPIO15_STATUS 2518 // Description : GPIO status 2519 #define IO_BANK0_GPIO15_STATUS_OFFSET _u(0x00000078) 2520 #define IO_BANK0_GPIO15_STATUS_BITS _u(0x050a3300) 2521 #define IO_BANK0_GPIO15_STATUS_RESET _u(0x00000000) 2522 // ----------------------------------------------------------------------------- 2523 // Field : IO_BANK0_GPIO15_STATUS_IRQTOPROC 2524 // Description : interrupt to processors, after override is applied 2525 #define IO_BANK0_GPIO15_STATUS_IRQTOPROC_RESET _u(0x0) 2526 #define IO_BANK0_GPIO15_STATUS_IRQTOPROC_BITS _u(0x04000000) 2527 #define IO_BANK0_GPIO15_STATUS_IRQTOPROC_MSB _u(26) 2528 #define IO_BANK0_GPIO15_STATUS_IRQTOPROC_LSB _u(26) 2529 #define IO_BANK0_GPIO15_STATUS_IRQTOPROC_ACCESS "RO" 2530 // ----------------------------------------------------------------------------- 2531 // Field : IO_BANK0_GPIO15_STATUS_IRQFROMPAD 2532 // Description : interrupt from pad before override is applied 2533 #define IO_BANK0_GPIO15_STATUS_IRQFROMPAD_RESET _u(0x0) 2534 #define IO_BANK0_GPIO15_STATUS_IRQFROMPAD_BITS _u(0x01000000) 2535 #define IO_BANK0_GPIO15_STATUS_IRQFROMPAD_MSB _u(24) 2536 #define IO_BANK0_GPIO15_STATUS_IRQFROMPAD_LSB _u(24) 2537 #define IO_BANK0_GPIO15_STATUS_IRQFROMPAD_ACCESS "RO" 2538 // ----------------------------------------------------------------------------- 2539 // Field : IO_BANK0_GPIO15_STATUS_INTOPERI 2540 // Description : input signal to peripheral, after override is applied 2541 #define IO_BANK0_GPIO15_STATUS_INTOPERI_RESET _u(0x0) 2542 #define IO_BANK0_GPIO15_STATUS_INTOPERI_BITS _u(0x00080000) 2543 #define IO_BANK0_GPIO15_STATUS_INTOPERI_MSB _u(19) 2544 #define IO_BANK0_GPIO15_STATUS_INTOPERI_LSB _u(19) 2545 #define IO_BANK0_GPIO15_STATUS_INTOPERI_ACCESS "RO" 2546 // ----------------------------------------------------------------------------- 2547 // Field : IO_BANK0_GPIO15_STATUS_INFROMPAD 2548 // Description : input signal from pad, before override is applied 2549 #define IO_BANK0_GPIO15_STATUS_INFROMPAD_RESET _u(0x0) 2550 #define IO_BANK0_GPIO15_STATUS_INFROMPAD_BITS _u(0x00020000) 2551 #define IO_BANK0_GPIO15_STATUS_INFROMPAD_MSB _u(17) 2552 #define IO_BANK0_GPIO15_STATUS_INFROMPAD_LSB _u(17) 2553 #define IO_BANK0_GPIO15_STATUS_INFROMPAD_ACCESS "RO" 2554 // ----------------------------------------------------------------------------- 2555 // Field : IO_BANK0_GPIO15_STATUS_OETOPAD 2556 // Description : output enable to pad after register override is applied 2557 #define IO_BANK0_GPIO15_STATUS_OETOPAD_RESET _u(0x0) 2558 #define IO_BANK0_GPIO15_STATUS_OETOPAD_BITS _u(0x00002000) 2559 #define IO_BANK0_GPIO15_STATUS_OETOPAD_MSB _u(13) 2560 #define IO_BANK0_GPIO15_STATUS_OETOPAD_LSB _u(13) 2561 #define IO_BANK0_GPIO15_STATUS_OETOPAD_ACCESS "RO" 2562 // ----------------------------------------------------------------------------- 2563 // Field : IO_BANK0_GPIO15_STATUS_OEFROMPERI 2564 // Description : output enable from selected peripheral, before register 2565 // override is applied 2566 #define IO_BANK0_GPIO15_STATUS_OEFROMPERI_RESET _u(0x0) 2567 #define IO_BANK0_GPIO15_STATUS_OEFROMPERI_BITS _u(0x00001000) 2568 #define IO_BANK0_GPIO15_STATUS_OEFROMPERI_MSB _u(12) 2569 #define IO_BANK0_GPIO15_STATUS_OEFROMPERI_LSB _u(12) 2570 #define IO_BANK0_GPIO15_STATUS_OEFROMPERI_ACCESS "RO" 2571 // ----------------------------------------------------------------------------- 2572 // Field : IO_BANK0_GPIO15_STATUS_OUTTOPAD 2573 // Description : output signal to pad after register override is applied 2574 #define IO_BANK0_GPIO15_STATUS_OUTTOPAD_RESET _u(0x0) 2575 #define IO_BANK0_GPIO15_STATUS_OUTTOPAD_BITS _u(0x00000200) 2576 #define IO_BANK0_GPIO15_STATUS_OUTTOPAD_MSB _u(9) 2577 #define IO_BANK0_GPIO15_STATUS_OUTTOPAD_LSB _u(9) 2578 #define IO_BANK0_GPIO15_STATUS_OUTTOPAD_ACCESS "RO" 2579 // ----------------------------------------------------------------------------- 2580 // Field : IO_BANK0_GPIO15_STATUS_OUTFROMPERI 2581 // Description : output signal from selected peripheral, before register 2582 // override is applied 2583 #define IO_BANK0_GPIO15_STATUS_OUTFROMPERI_RESET _u(0x0) 2584 #define IO_BANK0_GPIO15_STATUS_OUTFROMPERI_BITS _u(0x00000100) 2585 #define IO_BANK0_GPIO15_STATUS_OUTFROMPERI_MSB _u(8) 2586 #define IO_BANK0_GPIO15_STATUS_OUTFROMPERI_LSB _u(8) 2587 #define IO_BANK0_GPIO15_STATUS_OUTFROMPERI_ACCESS "RO" 2588 // ============================================================================= 2589 // Register : IO_BANK0_GPIO15_CTRL 2590 // Description : GPIO control including function select and overrides. 2591 #define IO_BANK0_GPIO15_CTRL_OFFSET _u(0x0000007c) 2592 #define IO_BANK0_GPIO15_CTRL_BITS _u(0x3003331f) 2593 #define IO_BANK0_GPIO15_CTRL_RESET _u(0x0000001f) 2594 // ----------------------------------------------------------------------------- 2595 // Field : IO_BANK0_GPIO15_CTRL_IRQOVER 2596 // 0x0 -> don't invert the interrupt 2597 // 0x1 -> invert the interrupt 2598 // 0x2 -> drive interrupt low 2599 // 0x3 -> drive interrupt high 2600 #define IO_BANK0_GPIO15_CTRL_IRQOVER_RESET _u(0x0) 2601 #define IO_BANK0_GPIO15_CTRL_IRQOVER_BITS _u(0x30000000) 2602 #define IO_BANK0_GPIO15_CTRL_IRQOVER_MSB _u(29) 2603 #define IO_BANK0_GPIO15_CTRL_IRQOVER_LSB _u(28) 2604 #define IO_BANK0_GPIO15_CTRL_IRQOVER_ACCESS "RW" 2605 #define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) 2606 #define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_INVERT _u(0x1) 2607 #define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_LOW _u(0x2) 2608 #define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_HIGH _u(0x3) 2609 // ----------------------------------------------------------------------------- 2610 // Field : IO_BANK0_GPIO15_CTRL_INOVER 2611 // 0x0 -> don't invert the peri input 2612 // 0x1 -> invert the peri input 2613 // 0x2 -> drive peri input low 2614 // 0x3 -> drive peri input high 2615 #define IO_BANK0_GPIO15_CTRL_INOVER_RESET _u(0x0) 2616 #define IO_BANK0_GPIO15_CTRL_INOVER_BITS _u(0x00030000) 2617 #define IO_BANK0_GPIO15_CTRL_INOVER_MSB _u(17) 2618 #define IO_BANK0_GPIO15_CTRL_INOVER_LSB _u(16) 2619 #define IO_BANK0_GPIO15_CTRL_INOVER_ACCESS "RW" 2620 #define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_NORMAL _u(0x0) 2621 #define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_INVERT _u(0x1) 2622 #define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_LOW _u(0x2) 2623 #define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_HIGH _u(0x3) 2624 // ----------------------------------------------------------------------------- 2625 // Field : IO_BANK0_GPIO15_CTRL_OEOVER 2626 // 0x0 -> drive output enable from peripheral signal selected by funcsel 2627 // 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel 2628 // 0x2 -> disable output 2629 // 0x3 -> enable output 2630 #define IO_BANK0_GPIO15_CTRL_OEOVER_RESET _u(0x0) 2631 #define IO_BANK0_GPIO15_CTRL_OEOVER_BITS _u(0x00003000) 2632 #define IO_BANK0_GPIO15_CTRL_OEOVER_MSB _u(13) 2633 #define IO_BANK0_GPIO15_CTRL_OEOVER_LSB _u(12) 2634 #define IO_BANK0_GPIO15_CTRL_OEOVER_ACCESS "RW" 2635 #define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_NORMAL _u(0x0) 2636 #define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_INVERT _u(0x1) 2637 #define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_DISABLE _u(0x2) 2638 #define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_ENABLE _u(0x3) 2639 // ----------------------------------------------------------------------------- 2640 // Field : IO_BANK0_GPIO15_CTRL_OUTOVER 2641 // 0x0 -> drive output from peripheral signal selected by funcsel 2642 // 0x1 -> drive output from inverse of peripheral signal selected by funcsel 2643 // 0x2 -> drive output low 2644 // 0x3 -> drive output high 2645 #define IO_BANK0_GPIO15_CTRL_OUTOVER_RESET _u(0x0) 2646 #define IO_BANK0_GPIO15_CTRL_OUTOVER_BITS _u(0x00000300) 2647 #define IO_BANK0_GPIO15_CTRL_OUTOVER_MSB _u(9) 2648 #define IO_BANK0_GPIO15_CTRL_OUTOVER_LSB _u(8) 2649 #define IO_BANK0_GPIO15_CTRL_OUTOVER_ACCESS "RW" 2650 #define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) 2651 #define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_INVERT _u(0x1) 2652 #define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_LOW _u(0x2) 2653 #define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_HIGH _u(0x3) 2654 // ----------------------------------------------------------------------------- 2655 // Field : IO_BANK0_GPIO15_CTRL_FUNCSEL 2656 // Description : 0-31 -> selects pin function according to the gpio table 2657 // 31 == NULL 2658 // 0x01 -> spi1_tx 2659 // 0x02 -> uart0_rts 2660 // 0x03 -> i2c1_scl 2661 // 0x04 -> pwm_b_7 2662 // 0x05 -> sio_15 2663 // 0x06 -> pio0_15 2664 // 0x07 -> pio1_15 2665 // 0x08 -> usb_muxing_digital_dp 2666 // 0x09 -> usb_muxing_overcurr_detect 2667 // 0x1f -> null 2668 #define IO_BANK0_GPIO15_CTRL_FUNCSEL_RESET _u(0x1f) 2669 #define IO_BANK0_GPIO15_CTRL_FUNCSEL_BITS _u(0x0000001f) 2670 #define IO_BANK0_GPIO15_CTRL_FUNCSEL_MSB _u(4) 2671 #define IO_BANK0_GPIO15_CTRL_FUNCSEL_LSB _u(0) 2672 #define IO_BANK0_GPIO15_CTRL_FUNCSEL_ACCESS "RW" 2673 #define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_SPI1_TX _u(0x01) 2674 #define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_UART0_RTS _u(0x02) 2675 #define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) 2676 #define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_PWM_B_7 _u(0x04) 2677 #define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_SIO_15 _u(0x05) 2678 #define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_PIO0_15 _u(0x06) 2679 #define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_PIO1_15 _u(0x07) 2680 #define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_USB_MUXING_DIGITAL_DP _u(0x08) 2681 #define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09) 2682 #define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) 2683 // ============================================================================= 2684 // Register : IO_BANK0_GPIO16_STATUS 2685 // Description : GPIO status 2686 #define IO_BANK0_GPIO16_STATUS_OFFSET _u(0x00000080) 2687 #define IO_BANK0_GPIO16_STATUS_BITS _u(0x050a3300) 2688 #define IO_BANK0_GPIO16_STATUS_RESET _u(0x00000000) 2689 // ----------------------------------------------------------------------------- 2690 // Field : IO_BANK0_GPIO16_STATUS_IRQTOPROC 2691 // Description : interrupt to processors, after override is applied 2692 #define IO_BANK0_GPIO16_STATUS_IRQTOPROC_RESET _u(0x0) 2693 #define IO_BANK0_GPIO16_STATUS_IRQTOPROC_BITS _u(0x04000000) 2694 #define IO_BANK0_GPIO16_STATUS_IRQTOPROC_MSB _u(26) 2695 #define IO_BANK0_GPIO16_STATUS_IRQTOPROC_LSB _u(26) 2696 #define IO_BANK0_GPIO16_STATUS_IRQTOPROC_ACCESS "RO" 2697 // ----------------------------------------------------------------------------- 2698 // Field : IO_BANK0_GPIO16_STATUS_IRQFROMPAD 2699 // Description : interrupt from pad before override is applied 2700 #define IO_BANK0_GPIO16_STATUS_IRQFROMPAD_RESET _u(0x0) 2701 #define IO_BANK0_GPIO16_STATUS_IRQFROMPAD_BITS _u(0x01000000) 2702 #define IO_BANK0_GPIO16_STATUS_IRQFROMPAD_MSB _u(24) 2703 #define IO_BANK0_GPIO16_STATUS_IRQFROMPAD_LSB _u(24) 2704 #define IO_BANK0_GPIO16_STATUS_IRQFROMPAD_ACCESS "RO" 2705 // ----------------------------------------------------------------------------- 2706 // Field : IO_BANK0_GPIO16_STATUS_INTOPERI 2707 // Description : input signal to peripheral, after override is applied 2708 #define IO_BANK0_GPIO16_STATUS_INTOPERI_RESET _u(0x0) 2709 #define IO_BANK0_GPIO16_STATUS_INTOPERI_BITS _u(0x00080000) 2710 #define IO_BANK0_GPIO16_STATUS_INTOPERI_MSB _u(19) 2711 #define IO_BANK0_GPIO16_STATUS_INTOPERI_LSB _u(19) 2712 #define IO_BANK0_GPIO16_STATUS_INTOPERI_ACCESS "RO" 2713 // ----------------------------------------------------------------------------- 2714 // Field : IO_BANK0_GPIO16_STATUS_INFROMPAD 2715 // Description : input signal from pad, before override is applied 2716 #define IO_BANK0_GPIO16_STATUS_INFROMPAD_RESET _u(0x0) 2717 #define IO_BANK0_GPIO16_STATUS_INFROMPAD_BITS _u(0x00020000) 2718 #define IO_BANK0_GPIO16_STATUS_INFROMPAD_MSB _u(17) 2719 #define IO_BANK0_GPIO16_STATUS_INFROMPAD_LSB _u(17) 2720 #define IO_BANK0_GPIO16_STATUS_INFROMPAD_ACCESS "RO" 2721 // ----------------------------------------------------------------------------- 2722 // Field : IO_BANK0_GPIO16_STATUS_OETOPAD 2723 // Description : output enable to pad after register override is applied 2724 #define IO_BANK0_GPIO16_STATUS_OETOPAD_RESET _u(0x0) 2725 #define IO_BANK0_GPIO16_STATUS_OETOPAD_BITS _u(0x00002000) 2726 #define IO_BANK0_GPIO16_STATUS_OETOPAD_MSB _u(13) 2727 #define IO_BANK0_GPIO16_STATUS_OETOPAD_LSB _u(13) 2728 #define IO_BANK0_GPIO16_STATUS_OETOPAD_ACCESS "RO" 2729 // ----------------------------------------------------------------------------- 2730 // Field : IO_BANK0_GPIO16_STATUS_OEFROMPERI 2731 // Description : output enable from selected peripheral, before register 2732 // override is applied 2733 #define IO_BANK0_GPIO16_STATUS_OEFROMPERI_RESET _u(0x0) 2734 #define IO_BANK0_GPIO16_STATUS_OEFROMPERI_BITS _u(0x00001000) 2735 #define IO_BANK0_GPIO16_STATUS_OEFROMPERI_MSB _u(12) 2736 #define IO_BANK0_GPIO16_STATUS_OEFROMPERI_LSB _u(12) 2737 #define IO_BANK0_GPIO16_STATUS_OEFROMPERI_ACCESS "RO" 2738 // ----------------------------------------------------------------------------- 2739 // Field : IO_BANK0_GPIO16_STATUS_OUTTOPAD 2740 // Description : output signal to pad after register override is applied 2741 #define IO_BANK0_GPIO16_STATUS_OUTTOPAD_RESET _u(0x0) 2742 #define IO_BANK0_GPIO16_STATUS_OUTTOPAD_BITS _u(0x00000200) 2743 #define IO_BANK0_GPIO16_STATUS_OUTTOPAD_MSB _u(9) 2744 #define IO_BANK0_GPIO16_STATUS_OUTTOPAD_LSB _u(9) 2745 #define IO_BANK0_GPIO16_STATUS_OUTTOPAD_ACCESS "RO" 2746 // ----------------------------------------------------------------------------- 2747 // Field : IO_BANK0_GPIO16_STATUS_OUTFROMPERI 2748 // Description : output signal from selected peripheral, before register 2749 // override is applied 2750 #define IO_BANK0_GPIO16_STATUS_OUTFROMPERI_RESET _u(0x0) 2751 #define IO_BANK0_GPIO16_STATUS_OUTFROMPERI_BITS _u(0x00000100) 2752 #define IO_BANK0_GPIO16_STATUS_OUTFROMPERI_MSB _u(8) 2753 #define IO_BANK0_GPIO16_STATUS_OUTFROMPERI_LSB _u(8) 2754 #define IO_BANK0_GPIO16_STATUS_OUTFROMPERI_ACCESS "RO" 2755 // ============================================================================= 2756 // Register : IO_BANK0_GPIO16_CTRL 2757 // Description : GPIO control including function select and overrides. 2758 #define IO_BANK0_GPIO16_CTRL_OFFSET _u(0x00000084) 2759 #define IO_BANK0_GPIO16_CTRL_BITS _u(0x3003331f) 2760 #define IO_BANK0_GPIO16_CTRL_RESET _u(0x0000001f) 2761 // ----------------------------------------------------------------------------- 2762 // Field : IO_BANK0_GPIO16_CTRL_IRQOVER 2763 // 0x0 -> don't invert the interrupt 2764 // 0x1 -> invert the interrupt 2765 // 0x2 -> drive interrupt low 2766 // 0x3 -> drive interrupt high 2767 #define IO_BANK0_GPIO16_CTRL_IRQOVER_RESET _u(0x0) 2768 #define IO_BANK0_GPIO16_CTRL_IRQOVER_BITS _u(0x30000000) 2769 #define IO_BANK0_GPIO16_CTRL_IRQOVER_MSB _u(29) 2770 #define IO_BANK0_GPIO16_CTRL_IRQOVER_LSB _u(28) 2771 #define IO_BANK0_GPIO16_CTRL_IRQOVER_ACCESS "RW" 2772 #define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) 2773 #define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_INVERT _u(0x1) 2774 #define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_LOW _u(0x2) 2775 #define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_HIGH _u(0x3) 2776 // ----------------------------------------------------------------------------- 2777 // Field : IO_BANK0_GPIO16_CTRL_INOVER 2778 // 0x0 -> don't invert the peri input 2779 // 0x1 -> invert the peri input 2780 // 0x2 -> drive peri input low 2781 // 0x3 -> drive peri input high 2782 #define IO_BANK0_GPIO16_CTRL_INOVER_RESET _u(0x0) 2783 #define IO_BANK0_GPIO16_CTRL_INOVER_BITS _u(0x00030000) 2784 #define IO_BANK0_GPIO16_CTRL_INOVER_MSB _u(17) 2785 #define IO_BANK0_GPIO16_CTRL_INOVER_LSB _u(16) 2786 #define IO_BANK0_GPIO16_CTRL_INOVER_ACCESS "RW" 2787 #define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_NORMAL _u(0x0) 2788 #define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_INVERT _u(0x1) 2789 #define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_LOW _u(0x2) 2790 #define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_HIGH _u(0x3) 2791 // ----------------------------------------------------------------------------- 2792 // Field : IO_BANK0_GPIO16_CTRL_OEOVER 2793 // 0x0 -> drive output enable from peripheral signal selected by funcsel 2794 // 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel 2795 // 0x2 -> disable output 2796 // 0x3 -> enable output 2797 #define IO_BANK0_GPIO16_CTRL_OEOVER_RESET _u(0x0) 2798 #define IO_BANK0_GPIO16_CTRL_OEOVER_BITS _u(0x00003000) 2799 #define IO_BANK0_GPIO16_CTRL_OEOVER_MSB _u(13) 2800 #define IO_BANK0_GPIO16_CTRL_OEOVER_LSB _u(12) 2801 #define IO_BANK0_GPIO16_CTRL_OEOVER_ACCESS "RW" 2802 #define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_NORMAL _u(0x0) 2803 #define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_INVERT _u(0x1) 2804 #define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_DISABLE _u(0x2) 2805 #define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_ENABLE _u(0x3) 2806 // ----------------------------------------------------------------------------- 2807 // Field : IO_BANK0_GPIO16_CTRL_OUTOVER 2808 // 0x0 -> drive output from peripheral signal selected by funcsel 2809 // 0x1 -> drive output from inverse of peripheral signal selected by funcsel 2810 // 0x2 -> drive output low 2811 // 0x3 -> drive output high 2812 #define IO_BANK0_GPIO16_CTRL_OUTOVER_RESET _u(0x0) 2813 #define IO_BANK0_GPIO16_CTRL_OUTOVER_BITS _u(0x00000300) 2814 #define IO_BANK0_GPIO16_CTRL_OUTOVER_MSB _u(9) 2815 #define IO_BANK0_GPIO16_CTRL_OUTOVER_LSB _u(8) 2816 #define IO_BANK0_GPIO16_CTRL_OUTOVER_ACCESS "RW" 2817 #define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) 2818 #define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_INVERT _u(0x1) 2819 #define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_LOW _u(0x2) 2820 #define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_HIGH _u(0x3) 2821 // ----------------------------------------------------------------------------- 2822 // Field : IO_BANK0_GPIO16_CTRL_FUNCSEL 2823 // Description : 0-31 -> selects pin function according to the gpio table 2824 // 31 == NULL 2825 // 0x01 -> spi0_rx 2826 // 0x02 -> uart0_tx 2827 // 0x03 -> i2c0_sda 2828 // 0x04 -> pwm_a_0 2829 // 0x05 -> sio_16 2830 // 0x06 -> pio0_16 2831 // 0x07 -> pio1_16 2832 // 0x08 -> usb_muxing_digital_dm 2833 // 0x09 -> usb_muxing_vbus_detect 2834 // 0x1f -> null 2835 #define IO_BANK0_GPIO16_CTRL_FUNCSEL_RESET _u(0x1f) 2836 #define IO_BANK0_GPIO16_CTRL_FUNCSEL_BITS _u(0x0000001f) 2837 #define IO_BANK0_GPIO16_CTRL_FUNCSEL_MSB _u(4) 2838 #define IO_BANK0_GPIO16_CTRL_FUNCSEL_LSB _u(0) 2839 #define IO_BANK0_GPIO16_CTRL_FUNCSEL_ACCESS "RW" 2840 #define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_SPI0_RX _u(0x01) 2841 #define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x02) 2842 #define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) 2843 #define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_PWM_A_0 _u(0x04) 2844 #define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_SIO_16 _u(0x05) 2845 #define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_PIO0_16 _u(0x06) 2846 #define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_PIO1_16 _u(0x07) 2847 #define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_USB_MUXING_DIGITAL_DM _u(0x08) 2848 #define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09) 2849 #define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) 2850 // ============================================================================= 2851 // Register : IO_BANK0_GPIO17_STATUS 2852 // Description : GPIO status 2853 #define IO_BANK0_GPIO17_STATUS_OFFSET _u(0x00000088) 2854 #define IO_BANK0_GPIO17_STATUS_BITS _u(0x050a3300) 2855 #define IO_BANK0_GPIO17_STATUS_RESET _u(0x00000000) 2856 // ----------------------------------------------------------------------------- 2857 // Field : IO_BANK0_GPIO17_STATUS_IRQTOPROC 2858 // Description : interrupt to processors, after override is applied 2859 #define IO_BANK0_GPIO17_STATUS_IRQTOPROC_RESET _u(0x0) 2860 #define IO_BANK0_GPIO17_STATUS_IRQTOPROC_BITS _u(0x04000000) 2861 #define IO_BANK0_GPIO17_STATUS_IRQTOPROC_MSB _u(26) 2862 #define IO_BANK0_GPIO17_STATUS_IRQTOPROC_LSB _u(26) 2863 #define IO_BANK0_GPIO17_STATUS_IRQTOPROC_ACCESS "RO" 2864 // ----------------------------------------------------------------------------- 2865 // Field : IO_BANK0_GPIO17_STATUS_IRQFROMPAD 2866 // Description : interrupt from pad before override is applied 2867 #define IO_BANK0_GPIO17_STATUS_IRQFROMPAD_RESET _u(0x0) 2868 #define IO_BANK0_GPIO17_STATUS_IRQFROMPAD_BITS _u(0x01000000) 2869 #define IO_BANK0_GPIO17_STATUS_IRQFROMPAD_MSB _u(24) 2870 #define IO_BANK0_GPIO17_STATUS_IRQFROMPAD_LSB _u(24) 2871 #define IO_BANK0_GPIO17_STATUS_IRQFROMPAD_ACCESS "RO" 2872 // ----------------------------------------------------------------------------- 2873 // Field : IO_BANK0_GPIO17_STATUS_INTOPERI 2874 // Description : input signal to peripheral, after override is applied 2875 #define IO_BANK0_GPIO17_STATUS_INTOPERI_RESET _u(0x0) 2876 #define IO_BANK0_GPIO17_STATUS_INTOPERI_BITS _u(0x00080000) 2877 #define IO_BANK0_GPIO17_STATUS_INTOPERI_MSB _u(19) 2878 #define IO_BANK0_GPIO17_STATUS_INTOPERI_LSB _u(19) 2879 #define IO_BANK0_GPIO17_STATUS_INTOPERI_ACCESS "RO" 2880 // ----------------------------------------------------------------------------- 2881 // Field : IO_BANK0_GPIO17_STATUS_INFROMPAD 2882 // Description : input signal from pad, before override is applied 2883 #define IO_BANK0_GPIO17_STATUS_INFROMPAD_RESET _u(0x0) 2884 #define IO_BANK0_GPIO17_STATUS_INFROMPAD_BITS _u(0x00020000) 2885 #define IO_BANK0_GPIO17_STATUS_INFROMPAD_MSB _u(17) 2886 #define IO_BANK0_GPIO17_STATUS_INFROMPAD_LSB _u(17) 2887 #define IO_BANK0_GPIO17_STATUS_INFROMPAD_ACCESS "RO" 2888 // ----------------------------------------------------------------------------- 2889 // Field : IO_BANK0_GPIO17_STATUS_OETOPAD 2890 // Description : output enable to pad after register override is applied 2891 #define IO_BANK0_GPIO17_STATUS_OETOPAD_RESET _u(0x0) 2892 #define IO_BANK0_GPIO17_STATUS_OETOPAD_BITS _u(0x00002000) 2893 #define IO_BANK0_GPIO17_STATUS_OETOPAD_MSB _u(13) 2894 #define IO_BANK0_GPIO17_STATUS_OETOPAD_LSB _u(13) 2895 #define IO_BANK0_GPIO17_STATUS_OETOPAD_ACCESS "RO" 2896 // ----------------------------------------------------------------------------- 2897 // Field : IO_BANK0_GPIO17_STATUS_OEFROMPERI 2898 // Description : output enable from selected peripheral, before register 2899 // override is applied 2900 #define IO_BANK0_GPIO17_STATUS_OEFROMPERI_RESET _u(0x0) 2901 #define IO_BANK0_GPIO17_STATUS_OEFROMPERI_BITS _u(0x00001000) 2902 #define IO_BANK0_GPIO17_STATUS_OEFROMPERI_MSB _u(12) 2903 #define IO_BANK0_GPIO17_STATUS_OEFROMPERI_LSB _u(12) 2904 #define IO_BANK0_GPIO17_STATUS_OEFROMPERI_ACCESS "RO" 2905 // ----------------------------------------------------------------------------- 2906 // Field : IO_BANK0_GPIO17_STATUS_OUTTOPAD 2907 // Description : output signal to pad after register override is applied 2908 #define IO_BANK0_GPIO17_STATUS_OUTTOPAD_RESET _u(0x0) 2909 #define IO_BANK0_GPIO17_STATUS_OUTTOPAD_BITS _u(0x00000200) 2910 #define IO_BANK0_GPIO17_STATUS_OUTTOPAD_MSB _u(9) 2911 #define IO_BANK0_GPIO17_STATUS_OUTTOPAD_LSB _u(9) 2912 #define IO_BANK0_GPIO17_STATUS_OUTTOPAD_ACCESS "RO" 2913 // ----------------------------------------------------------------------------- 2914 // Field : IO_BANK0_GPIO17_STATUS_OUTFROMPERI 2915 // Description : output signal from selected peripheral, before register 2916 // override is applied 2917 #define IO_BANK0_GPIO17_STATUS_OUTFROMPERI_RESET _u(0x0) 2918 #define IO_BANK0_GPIO17_STATUS_OUTFROMPERI_BITS _u(0x00000100) 2919 #define IO_BANK0_GPIO17_STATUS_OUTFROMPERI_MSB _u(8) 2920 #define IO_BANK0_GPIO17_STATUS_OUTFROMPERI_LSB _u(8) 2921 #define IO_BANK0_GPIO17_STATUS_OUTFROMPERI_ACCESS "RO" 2922 // ============================================================================= 2923 // Register : IO_BANK0_GPIO17_CTRL 2924 // Description : GPIO control including function select and overrides. 2925 #define IO_BANK0_GPIO17_CTRL_OFFSET _u(0x0000008c) 2926 #define IO_BANK0_GPIO17_CTRL_BITS _u(0x3003331f) 2927 #define IO_BANK0_GPIO17_CTRL_RESET _u(0x0000001f) 2928 // ----------------------------------------------------------------------------- 2929 // Field : IO_BANK0_GPIO17_CTRL_IRQOVER 2930 // 0x0 -> don't invert the interrupt 2931 // 0x1 -> invert the interrupt 2932 // 0x2 -> drive interrupt low 2933 // 0x3 -> drive interrupt high 2934 #define IO_BANK0_GPIO17_CTRL_IRQOVER_RESET _u(0x0) 2935 #define IO_BANK0_GPIO17_CTRL_IRQOVER_BITS _u(0x30000000) 2936 #define IO_BANK0_GPIO17_CTRL_IRQOVER_MSB _u(29) 2937 #define IO_BANK0_GPIO17_CTRL_IRQOVER_LSB _u(28) 2938 #define IO_BANK0_GPIO17_CTRL_IRQOVER_ACCESS "RW" 2939 #define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) 2940 #define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_INVERT _u(0x1) 2941 #define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_LOW _u(0x2) 2942 #define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_HIGH _u(0x3) 2943 // ----------------------------------------------------------------------------- 2944 // Field : IO_BANK0_GPIO17_CTRL_INOVER 2945 // 0x0 -> don't invert the peri input 2946 // 0x1 -> invert the peri input 2947 // 0x2 -> drive peri input low 2948 // 0x3 -> drive peri input high 2949 #define IO_BANK0_GPIO17_CTRL_INOVER_RESET _u(0x0) 2950 #define IO_BANK0_GPIO17_CTRL_INOVER_BITS _u(0x00030000) 2951 #define IO_BANK0_GPIO17_CTRL_INOVER_MSB _u(17) 2952 #define IO_BANK0_GPIO17_CTRL_INOVER_LSB _u(16) 2953 #define IO_BANK0_GPIO17_CTRL_INOVER_ACCESS "RW" 2954 #define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_NORMAL _u(0x0) 2955 #define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_INVERT _u(0x1) 2956 #define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_LOW _u(0x2) 2957 #define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_HIGH _u(0x3) 2958 // ----------------------------------------------------------------------------- 2959 // Field : IO_BANK0_GPIO17_CTRL_OEOVER 2960 // 0x0 -> drive output enable from peripheral signal selected by funcsel 2961 // 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel 2962 // 0x2 -> disable output 2963 // 0x3 -> enable output 2964 #define IO_BANK0_GPIO17_CTRL_OEOVER_RESET _u(0x0) 2965 #define IO_BANK0_GPIO17_CTRL_OEOVER_BITS _u(0x00003000) 2966 #define IO_BANK0_GPIO17_CTRL_OEOVER_MSB _u(13) 2967 #define IO_BANK0_GPIO17_CTRL_OEOVER_LSB _u(12) 2968 #define IO_BANK0_GPIO17_CTRL_OEOVER_ACCESS "RW" 2969 #define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_NORMAL _u(0x0) 2970 #define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_INVERT _u(0x1) 2971 #define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_DISABLE _u(0x2) 2972 #define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_ENABLE _u(0x3) 2973 // ----------------------------------------------------------------------------- 2974 // Field : IO_BANK0_GPIO17_CTRL_OUTOVER 2975 // 0x0 -> drive output from peripheral signal selected by funcsel 2976 // 0x1 -> drive output from inverse of peripheral signal selected by funcsel 2977 // 0x2 -> drive output low 2978 // 0x3 -> drive output high 2979 #define IO_BANK0_GPIO17_CTRL_OUTOVER_RESET _u(0x0) 2980 #define IO_BANK0_GPIO17_CTRL_OUTOVER_BITS _u(0x00000300) 2981 #define IO_BANK0_GPIO17_CTRL_OUTOVER_MSB _u(9) 2982 #define IO_BANK0_GPIO17_CTRL_OUTOVER_LSB _u(8) 2983 #define IO_BANK0_GPIO17_CTRL_OUTOVER_ACCESS "RW" 2984 #define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) 2985 #define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_INVERT _u(0x1) 2986 #define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_LOW _u(0x2) 2987 #define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_HIGH _u(0x3) 2988 // ----------------------------------------------------------------------------- 2989 // Field : IO_BANK0_GPIO17_CTRL_FUNCSEL 2990 // Description : 0-31 -> selects pin function according to the gpio table 2991 // 31 == NULL 2992 // 0x01 -> spi0_ss_n 2993 // 0x02 -> uart0_rx 2994 // 0x03 -> i2c0_scl 2995 // 0x04 -> pwm_b_0 2996 // 0x05 -> sio_17 2997 // 0x06 -> pio0_17 2998 // 0x07 -> pio1_17 2999 // 0x09 -> usb_muxing_vbus_en 3000 // 0x1f -> null 3001 #define IO_BANK0_GPIO17_CTRL_FUNCSEL_RESET _u(0x1f) 3002 #define IO_BANK0_GPIO17_CTRL_FUNCSEL_BITS _u(0x0000001f) 3003 #define IO_BANK0_GPIO17_CTRL_FUNCSEL_MSB _u(4) 3004 #define IO_BANK0_GPIO17_CTRL_FUNCSEL_LSB _u(0) 3005 #define IO_BANK0_GPIO17_CTRL_FUNCSEL_ACCESS "RW" 3006 #define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_SPI0_SS_N _u(0x01) 3007 #define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x02) 3008 #define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) 3009 #define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_PWM_B_0 _u(0x04) 3010 #define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_SIO_17 _u(0x05) 3011 #define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_PIO0_17 _u(0x06) 3012 #define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_PIO1_17 _u(0x07) 3013 #define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09) 3014 #define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) 3015 // ============================================================================= 3016 // Register : IO_BANK0_GPIO18_STATUS 3017 // Description : GPIO status 3018 #define IO_BANK0_GPIO18_STATUS_OFFSET _u(0x00000090) 3019 #define IO_BANK0_GPIO18_STATUS_BITS _u(0x050a3300) 3020 #define IO_BANK0_GPIO18_STATUS_RESET _u(0x00000000) 3021 // ----------------------------------------------------------------------------- 3022 // Field : IO_BANK0_GPIO18_STATUS_IRQTOPROC 3023 // Description : interrupt to processors, after override is applied 3024 #define IO_BANK0_GPIO18_STATUS_IRQTOPROC_RESET _u(0x0) 3025 #define IO_BANK0_GPIO18_STATUS_IRQTOPROC_BITS _u(0x04000000) 3026 #define IO_BANK0_GPIO18_STATUS_IRQTOPROC_MSB _u(26) 3027 #define IO_BANK0_GPIO18_STATUS_IRQTOPROC_LSB _u(26) 3028 #define IO_BANK0_GPIO18_STATUS_IRQTOPROC_ACCESS "RO" 3029 // ----------------------------------------------------------------------------- 3030 // Field : IO_BANK0_GPIO18_STATUS_IRQFROMPAD 3031 // Description : interrupt from pad before override is applied 3032 #define IO_BANK0_GPIO18_STATUS_IRQFROMPAD_RESET _u(0x0) 3033 #define IO_BANK0_GPIO18_STATUS_IRQFROMPAD_BITS _u(0x01000000) 3034 #define IO_BANK0_GPIO18_STATUS_IRQFROMPAD_MSB _u(24) 3035 #define IO_BANK0_GPIO18_STATUS_IRQFROMPAD_LSB _u(24) 3036 #define IO_BANK0_GPIO18_STATUS_IRQFROMPAD_ACCESS "RO" 3037 // ----------------------------------------------------------------------------- 3038 // Field : IO_BANK0_GPIO18_STATUS_INTOPERI 3039 // Description : input signal to peripheral, after override is applied 3040 #define IO_BANK0_GPIO18_STATUS_INTOPERI_RESET _u(0x0) 3041 #define IO_BANK0_GPIO18_STATUS_INTOPERI_BITS _u(0x00080000) 3042 #define IO_BANK0_GPIO18_STATUS_INTOPERI_MSB _u(19) 3043 #define IO_BANK0_GPIO18_STATUS_INTOPERI_LSB _u(19) 3044 #define IO_BANK0_GPIO18_STATUS_INTOPERI_ACCESS "RO" 3045 // ----------------------------------------------------------------------------- 3046 // Field : IO_BANK0_GPIO18_STATUS_INFROMPAD 3047 // Description : input signal from pad, before override is applied 3048 #define IO_BANK0_GPIO18_STATUS_INFROMPAD_RESET _u(0x0) 3049 #define IO_BANK0_GPIO18_STATUS_INFROMPAD_BITS _u(0x00020000) 3050 #define IO_BANK0_GPIO18_STATUS_INFROMPAD_MSB _u(17) 3051 #define IO_BANK0_GPIO18_STATUS_INFROMPAD_LSB _u(17) 3052 #define IO_BANK0_GPIO18_STATUS_INFROMPAD_ACCESS "RO" 3053 // ----------------------------------------------------------------------------- 3054 // Field : IO_BANK0_GPIO18_STATUS_OETOPAD 3055 // Description : output enable to pad after register override is applied 3056 #define IO_BANK0_GPIO18_STATUS_OETOPAD_RESET _u(0x0) 3057 #define IO_BANK0_GPIO18_STATUS_OETOPAD_BITS _u(0x00002000) 3058 #define IO_BANK0_GPIO18_STATUS_OETOPAD_MSB _u(13) 3059 #define IO_BANK0_GPIO18_STATUS_OETOPAD_LSB _u(13) 3060 #define IO_BANK0_GPIO18_STATUS_OETOPAD_ACCESS "RO" 3061 // ----------------------------------------------------------------------------- 3062 // Field : IO_BANK0_GPIO18_STATUS_OEFROMPERI 3063 // Description : output enable from selected peripheral, before register 3064 // override is applied 3065 #define IO_BANK0_GPIO18_STATUS_OEFROMPERI_RESET _u(0x0) 3066 #define IO_BANK0_GPIO18_STATUS_OEFROMPERI_BITS _u(0x00001000) 3067 #define IO_BANK0_GPIO18_STATUS_OEFROMPERI_MSB _u(12) 3068 #define IO_BANK0_GPIO18_STATUS_OEFROMPERI_LSB _u(12) 3069 #define IO_BANK0_GPIO18_STATUS_OEFROMPERI_ACCESS "RO" 3070 // ----------------------------------------------------------------------------- 3071 // Field : IO_BANK0_GPIO18_STATUS_OUTTOPAD 3072 // Description : output signal to pad after register override is applied 3073 #define IO_BANK0_GPIO18_STATUS_OUTTOPAD_RESET _u(0x0) 3074 #define IO_BANK0_GPIO18_STATUS_OUTTOPAD_BITS _u(0x00000200) 3075 #define IO_BANK0_GPIO18_STATUS_OUTTOPAD_MSB _u(9) 3076 #define IO_BANK0_GPIO18_STATUS_OUTTOPAD_LSB _u(9) 3077 #define IO_BANK0_GPIO18_STATUS_OUTTOPAD_ACCESS "RO" 3078 // ----------------------------------------------------------------------------- 3079 // Field : IO_BANK0_GPIO18_STATUS_OUTFROMPERI 3080 // Description : output signal from selected peripheral, before register 3081 // override is applied 3082 #define IO_BANK0_GPIO18_STATUS_OUTFROMPERI_RESET _u(0x0) 3083 #define IO_BANK0_GPIO18_STATUS_OUTFROMPERI_BITS _u(0x00000100) 3084 #define IO_BANK0_GPIO18_STATUS_OUTFROMPERI_MSB _u(8) 3085 #define IO_BANK0_GPIO18_STATUS_OUTFROMPERI_LSB _u(8) 3086 #define IO_BANK0_GPIO18_STATUS_OUTFROMPERI_ACCESS "RO" 3087 // ============================================================================= 3088 // Register : IO_BANK0_GPIO18_CTRL 3089 // Description : GPIO control including function select and overrides. 3090 #define IO_BANK0_GPIO18_CTRL_OFFSET _u(0x00000094) 3091 #define IO_BANK0_GPIO18_CTRL_BITS _u(0x3003331f) 3092 #define IO_BANK0_GPIO18_CTRL_RESET _u(0x0000001f) 3093 // ----------------------------------------------------------------------------- 3094 // Field : IO_BANK0_GPIO18_CTRL_IRQOVER 3095 // 0x0 -> don't invert the interrupt 3096 // 0x1 -> invert the interrupt 3097 // 0x2 -> drive interrupt low 3098 // 0x3 -> drive interrupt high 3099 #define IO_BANK0_GPIO18_CTRL_IRQOVER_RESET _u(0x0) 3100 #define IO_BANK0_GPIO18_CTRL_IRQOVER_BITS _u(0x30000000) 3101 #define IO_BANK0_GPIO18_CTRL_IRQOVER_MSB _u(29) 3102 #define IO_BANK0_GPIO18_CTRL_IRQOVER_LSB _u(28) 3103 #define IO_BANK0_GPIO18_CTRL_IRQOVER_ACCESS "RW" 3104 #define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) 3105 #define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_INVERT _u(0x1) 3106 #define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_LOW _u(0x2) 3107 #define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_HIGH _u(0x3) 3108 // ----------------------------------------------------------------------------- 3109 // Field : IO_BANK0_GPIO18_CTRL_INOVER 3110 // 0x0 -> don't invert the peri input 3111 // 0x1 -> invert the peri input 3112 // 0x2 -> drive peri input low 3113 // 0x3 -> drive peri input high 3114 #define IO_BANK0_GPIO18_CTRL_INOVER_RESET _u(0x0) 3115 #define IO_BANK0_GPIO18_CTRL_INOVER_BITS _u(0x00030000) 3116 #define IO_BANK0_GPIO18_CTRL_INOVER_MSB _u(17) 3117 #define IO_BANK0_GPIO18_CTRL_INOVER_LSB _u(16) 3118 #define IO_BANK0_GPIO18_CTRL_INOVER_ACCESS "RW" 3119 #define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_NORMAL _u(0x0) 3120 #define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_INVERT _u(0x1) 3121 #define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_LOW _u(0x2) 3122 #define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_HIGH _u(0x3) 3123 // ----------------------------------------------------------------------------- 3124 // Field : IO_BANK0_GPIO18_CTRL_OEOVER 3125 // 0x0 -> drive output enable from peripheral signal selected by funcsel 3126 // 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel 3127 // 0x2 -> disable output 3128 // 0x3 -> enable output 3129 #define IO_BANK0_GPIO18_CTRL_OEOVER_RESET _u(0x0) 3130 #define IO_BANK0_GPIO18_CTRL_OEOVER_BITS _u(0x00003000) 3131 #define IO_BANK0_GPIO18_CTRL_OEOVER_MSB _u(13) 3132 #define IO_BANK0_GPIO18_CTRL_OEOVER_LSB _u(12) 3133 #define IO_BANK0_GPIO18_CTRL_OEOVER_ACCESS "RW" 3134 #define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_NORMAL _u(0x0) 3135 #define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_INVERT _u(0x1) 3136 #define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_DISABLE _u(0x2) 3137 #define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_ENABLE _u(0x3) 3138 // ----------------------------------------------------------------------------- 3139 // Field : IO_BANK0_GPIO18_CTRL_OUTOVER 3140 // 0x0 -> drive output from peripheral signal selected by funcsel 3141 // 0x1 -> drive output from inverse of peripheral signal selected by funcsel 3142 // 0x2 -> drive output low 3143 // 0x3 -> drive output high 3144 #define IO_BANK0_GPIO18_CTRL_OUTOVER_RESET _u(0x0) 3145 #define IO_BANK0_GPIO18_CTRL_OUTOVER_BITS _u(0x00000300) 3146 #define IO_BANK0_GPIO18_CTRL_OUTOVER_MSB _u(9) 3147 #define IO_BANK0_GPIO18_CTRL_OUTOVER_LSB _u(8) 3148 #define IO_BANK0_GPIO18_CTRL_OUTOVER_ACCESS "RW" 3149 #define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) 3150 #define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_INVERT _u(0x1) 3151 #define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_LOW _u(0x2) 3152 #define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_HIGH _u(0x3) 3153 // ----------------------------------------------------------------------------- 3154 // Field : IO_BANK0_GPIO18_CTRL_FUNCSEL 3155 // Description : 0-31 -> selects pin function according to the gpio table 3156 // 31 == NULL 3157 // 0x01 -> spi0_sclk 3158 // 0x02 -> uart0_cts 3159 // 0x03 -> i2c1_sda 3160 // 0x04 -> pwm_a_1 3161 // 0x05 -> sio_18 3162 // 0x06 -> pio0_18 3163 // 0x07 -> pio1_18 3164 // 0x09 -> usb_muxing_overcurr_detect 3165 // 0x1f -> null 3166 #define IO_BANK0_GPIO18_CTRL_FUNCSEL_RESET _u(0x1f) 3167 #define IO_BANK0_GPIO18_CTRL_FUNCSEL_BITS _u(0x0000001f) 3168 #define IO_BANK0_GPIO18_CTRL_FUNCSEL_MSB _u(4) 3169 #define IO_BANK0_GPIO18_CTRL_FUNCSEL_LSB _u(0) 3170 #define IO_BANK0_GPIO18_CTRL_FUNCSEL_ACCESS "RW" 3171 #define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_SPI0_SCLK _u(0x01) 3172 #define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_UART0_CTS _u(0x02) 3173 #define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) 3174 #define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_PWM_A_1 _u(0x04) 3175 #define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_SIO_18 _u(0x05) 3176 #define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_PIO0_18 _u(0x06) 3177 #define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_PIO1_18 _u(0x07) 3178 #define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09) 3179 #define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) 3180 // ============================================================================= 3181 // Register : IO_BANK0_GPIO19_STATUS 3182 // Description : GPIO status 3183 #define IO_BANK0_GPIO19_STATUS_OFFSET _u(0x00000098) 3184 #define IO_BANK0_GPIO19_STATUS_BITS _u(0x050a3300) 3185 #define IO_BANK0_GPIO19_STATUS_RESET _u(0x00000000) 3186 // ----------------------------------------------------------------------------- 3187 // Field : IO_BANK0_GPIO19_STATUS_IRQTOPROC 3188 // Description : interrupt to processors, after override is applied 3189 #define IO_BANK0_GPIO19_STATUS_IRQTOPROC_RESET _u(0x0) 3190 #define IO_BANK0_GPIO19_STATUS_IRQTOPROC_BITS _u(0x04000000) 3191 #define IO_BANK0_GPIO19_STATUS_IRQTOPROC_MSB _u(26) 3192 #define IO_BANK0_GPIO19_STATUS_IRQTOPROC_LSB _u(26) 3193 #define IO_BANK0_GPIO19_STATUS_IRQTOPROC_ACCESS "RO" 3194 // ----------------------------------------------------------------------------- 3195 // Field : IO_BANK0_GPIO19_STATUS_IRQFROMPAD 3196 // Description : interrupt from pad before override is applied 3197 #define IO_BANK0_GPIO19_STATUS_IRQFROMPAD_RESET _u(0x0) 3198 #define IO_BANK0_GPIO19_STATUS_IRQFROMPAD_BITS _u(0x01000000) 3199 #define IO_BANK0_GPIO19_STATUS_IRQFROMPAD_MSB _u(24) 3200 #define IO_BANK0_GPIO19_STATUS_IRQFROMPAD_LSB _u(24) 3201 #define IO_BANK0_GPIO19_STATUS_IRQFROMPAD_ACCESS "RO" 3202 // ----------------------------------------------------------------------------- 3203 // Field : IO_BANK0_GPIO19_STATUS_INTOPERI 3204 // Description : input signal to peripheral, after override is applied 3205 #define IO_BANK0_GPIO19_STATUS_INTOPERI_RESET _u(0x0) 3206 #define IO_BANK0_GPIO19_STATUS_INTOPERI_BITS _u(0x00080000) 3207 #define IO_BANK0_GPIO19_STATUS_INTOPERI_MSB _u(19) 3208 #define IO_BANK0_GPIO19_STATUS_INTOPERI_LSB _u(19) 3209 #define IO_BANK0_GPIO19_STATUS_INTOPERI_ACCESS "RO" 3210 // ----------------------------------------------------------------------------- 3211 // Field : IO_BANK0_GPIO19_STATUS_INFROMPAD 3212 // Description : input signal from pad, before override is applied 3213 #define IO_BANK0_GPIO19_STATUS_INFROMPAD_RESET _u(0x0) 3214 #define IO_BANK0_GPIO19_STATUS_INFROMPAD_BITS _u(0x00020000) 3215 #define IO_BANK0_GPIO19_STATUS_INFROMPAD_MSB _u(17) 3216 #define IO_BANK0_GPIO19_STATUS_INFROMPAD_LSB _u(17) 3217 #define IO_BANK0_GPIO19_STATUS_INFROMPAD_ACCESS "RO" 3218 // ----------------------------------------------------------------------------- 3219 // Field : IO_BANK0_GPIO19_STATUS_OETOPAD 3220 // Description : output enable to pad after register override is applied 3221 #define IO_BANK0_GPIO19_STATUS_OETOPAD_RESET _u(0x0) 3222 #define IO_BANK0_GPIO19_STATUS_OETOPAD_BITS _u(0x00002000) 3223 #define IO_BANK0_GPIO19_STATUS_OETOPAD_MSB _u(13) 3224 #define IO_BANK0_GPIO19_STATUS_OETOPAD_LSB _u(13) 3225 #define IO_BANK0_GPIO19_STATUS_OETOPAD_ACCESS "RO" 3226 // ----------------------------------------------------------------------------- 3227 // Field : IO_BANK0_GPIO19_STATUS_OEFROMPERI 3228 // Description : output enable from selected peripheral, before register 3229 // override is applied 3230 #define IO_BANK0_GPIO19_STATUS_OEFROMPERI_RESET _u(0x0) 3231 #define IO_BANK0_GPIO19_STATUS_OEFROMPERI_BITS _u(0x00001000) 3232 #define IO_BANK0_GPIO19_STATUS_OEFROMPERI_MSB _u(12) 3233 #define IO_BANK0_GPIO19_STATUS_OEFROMPERI_LSB _u(12) 3234 #define IO_BANK0_GPIO19_STATUS_OEFROMPERI_ACCESS "RO" 3235 // ----------------------------------------------------------------------------- 3236 // Field : IO_BANK0_GPIO19_STATUS_OUTTOPAD 3237 // Description : output signal to pad after register override is applied 3238 #define IO_BANK0_GPIO19_STATUS_OUTTOPAD_RESET _u(0x0) 3239 #define IO_BANK0_GPIO19_STATUS_OUTTOPAD_BITS _u(0x00000200) 3240 #define IO_BANK0_GPIO19_STATUS_OUTTOPAD_MSB _u(9) 3241 #define IO_BANK0_GPIO19_STATUS_OUTTOPAD_LSB _u(9) 3242 #define IO_BANK0_GPIO19_STATUS_OUTTOPAD_ACCESS "RO" 3243 // ----------------------------------------------------------------------------- 3244 // Field : IO_BANK0_GPIO19_STATUS_OUTFROMPERI 3245 // Description : output signal from selected peripheral, before register 3246 // override is applied 3247 #define IO_BANK0_GPIO19_STATUS_OUTFROMPERI_RESET _u(0x0) 3248 #define IO_BANK0_GPIO19_STATUS_OUTFROMPERI_BITS _u(0x00000100) 3249 #define IO_BANK0_GPIO19_STATUS_OUTFROMPERI_MSB _u(8) 3250 #define IO_BANK0_GPIO19_STATUS_OUTFROMPERI_LSB _u(8) 3251 #define IO_BANK0_GPIO19_STATUS_OUTFROMPERI_ACCESS "RO" 3252 // ============================================================================= 3253 // Register : IO_BANK0_GPIO19_CTRL 3254 // Description : GPIO control including function select and overrides. 3255 #define IO_BANK0_GPIO19_CTRL_OFFSET _u(0x0000009c) 3256 #define IO_BANK0_GPIO19_CTRL_BITS _u(0x3003331f) 3257 #define IO_BANK0_GPIO19_CTRL_RESET _u(0x0000001f) 3258 // ----------------------------------------------------------------------------- 3259 // Field : IO_BANK0_GPIO19_CTRL_IRQOVER 3260 // 0x0 -> don't invert the interrupt 3261 // 0x1 -> invert the interrupt 3262 // 0x2 -> drive interrupt low 3263 // 0x3 -> drive interrupt high 3264 #define IO_BANK0_GPIO19_CTRL_IRQOVER_RESET _u(0x0) 3265 #define IO_BANK0_GPIO19_CTRL_IRQOVER_BITS _u(0x30000000) 3266 #define IO_BANK0_GPIO19_CTRL_IRQOVER_MSB _u(29) 3267 #define IO_BANK0_GPIO19_CTRL_IRQOVER_LSB _u(28) 3268 #define IO_BANK0_GPIO19_CTRL_IRQOVER_ACCESS "RW" 3269 #define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) 3270 #define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_INVERT _u(0x1) 3271 #define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_LOW _u(0x2) 3272 #define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_HIGH _u(0x3) 3273 // ----------------------------------------------------------------------------- 3274 // Field : IO_BANK0_GPIO19_CTRL_INOVER 3275 // 0x0 -> don't invert the peri input 3276 // 0x1 -> invert the peri input 3277 // 0x2 -> drive peri input low 3278 // 0x3 -> drive peri input high 3279 #define IO_BANK0_GPIO19_CTRL_INOVER_RESET _u(0x0) 3280 #define IO_BANK0_GPIO19_CTRL_INOVER_BITS _u(0x00030000) 3281 #define IO_BANK0_GPIO19_CTRL_INOVER_MSB _u(17) 3282 #define IO_BANK0_GPIO19_CTRL_INOVER_LSB _u(16) 3283 #define IO_BANK0_GPIO19_CTRL_INOVER_ACCESS "RW" 3284 #define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_NORMAL _u(0x0) 3285 #define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_INVERT _u(0x1) 3286 #define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_LOW _u(0x2) 3287 #define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_HIGH _u(0x3) 3288 // ----------------------------------------------------------------------------- 3289 // Field : IO_BANK0_GPIO19_CTRL_OEOVER 3290 // 0x0 -> drive output enable from peripheral signal selected by funcsel 3291 // 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel 3292 // 0x2 -> disable output 3293 // 0x3 -> enable output 3294 #define IO_BANK0_GPIO19_CTRL_OEOVER_RESET _u(0x0) 3295 #define IO_BANK0_GPIO19_CTRL_OEOVER_BITS _u(0x00003000) 3296 #define IO_BANK0_GPIO19_CTRL_OEOVER_MSB _u(13) 3297 #define IO_BANK0_GPIO19_CTRL_OEOVER_LSB _u(12) 3298 #define IO_BANK0_GPIO19_CTRL_OEOVER_ACCESS "RW" 3299 #define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_NORMAL _u(0x0) 3300 #define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_INVERT _u(0x1) 3301 #define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_DISABLE _u(0x2) 3302 #define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_ENABLE _u(0x3) 3303 // ----------------------------------------------------------------------------- 3304 // Field : IO_BANK0_GPIO19_CTRL_OUTOVER 3305 // 0x0 -> drive output from peripheral signal selected by funcsel 3306 // 0x1 -> drive output from inverse of peripheral signal selected by funcsel 3307 // 0x2 -> drive output low 3308 // 0x3 -> drive output high 3309 #define IO_BANK0_GPIO19_CTRL_OUTOVER_RESET _u(0x0) 3310 #define IO_BANK0_GPIO19_CTRL_OUTOVER_BITS _u(0x00000300) 3311 #define IO_BANK0_GPIO19_CTRL_OUTOVER_MSB _u(9) 3312 #define IO_BANK0_GPIO19_CTRL_OUTOVER_LSB _u(8) 3313 #define IO_BANK0_GPIO19_CTRL_OUTOVER_ACCESS "RW" 3314 #define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) 3315 #define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_INVERT _u(0x1) 3316 #define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_LOW _u(0x2) 3317 #define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_HIGH _u(0x3) 3318 // ----------------------------------------------------------------------------- 3319 // Field : IO_BANK0_GPIO19_CTRL_FUNCSEL 3320 // Description : 0-31 -> selects pin function according to the gpio table 3321 // 31 == NULL 3322 // 0x01 -> spi0_tx 3323 // 0x02 -> uart0_rts 3324 // 0x03 -> i2c1_scl 3325 // 0x04 -> pwm_b_1 3326 // 0x05 -> sio_19 3327 // 0x06 -> pio0_19 3328 // 0x07 -> pio1_19 3329 // 0x09 -> usb_muxing_vbus_detect 3330 // 0x1f -> null 3331 #define IO_BANK0_GPIO19_CTRL_FUNCSEL_RESET _u(0x1f) 3332 #define IO_BANK0_GPIO19_CTRL_FUNCSEL_BITS _u(0x0000001f) 3333 #define IO_BANK0_GPIO19_CTRL_FUNCSEL_MSB _u(4) 3334 #define IO_BANK0_GPIO19_CTRL_FUNCSEL_LSB _u(0) 3335 #define IO_BANK0_GPIO19_CTRL_FUNCSEL_ACCESS "RW" 3336 #define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_SPI0_TX _u(0x01) 3337 #define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_UART0_RTS _u(0x02) 3338 #define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) 3339 #define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_PWM_B_1 _u(0x04) 3340 #define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_SIO_19 _u(0x05) 3341 #define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_PIO0_19 _u(0x06) 3342 #define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_PIO1_19 _u(0x07) 3343 #define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09) 3344 #define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) 3345 // ============================================================================= 3346 // Register : IO_BANK0_GPIO20_STATUS 3347 // Description : GPIO status 3348 #define IO_BANK0_GPIO20_STATUS_OFFSET _u(0x000000a0) 3349 #define IO_BANK0_GPIO20_STATUS_BITS _u(0x050a3300) 3350 #define IO_BANK0_GPIO20_STATUS_RESET _u(0x00000000) 3351 // ----------------------------------------------------------------------------- 3352 // Field : IO_BANK0_GPIO20_STATUS_IRQTOPROC 3353 // Description : interrupt to processors, after override is applied 3354 #define IO_BANK0_GPIO20_STATUS_IRQTOPROC_RESET _u(0x0) 3355 #define IO_BANK0_GPIO20_STATUS_IRQTOPROC_BITS _u(0x04000000) 3356 #define IO_BANK0_GPIO20_STATUS_IRQTOPROC_MSB _u(26) 3357 #define IO_BANK0_GPIO20_STATUS_IRQTOPROC_LSB _u(26) 3358 #define IO_BANK0_GPIO20_STATUS_IRQTOPROC_ACCESS "RO" 3359 // ----------------------------------------------------------------------------- 3360 // Field : IO_BANK0_GPIO20_STATUS_IRQFROMPAD 3361 // Description : interrupt from pad before override is applied 3362 #define IO_BANK0_GPIO20_STATUS_IRQFROMPAD_RESET _u(0x0) 3363 #define IO_BANK0_GPIO20_STATUS_IRQFROMPAD_BITS _u(0x01000000) 3364 #define IO_BANK0_GPIO20_STATUS_IRQFROMPAD_MSB _u(24) 3365 #define IO_BANK0_GPIO20_STATUS_IRQFROMPAD_LSB _u(24) 3366 #define IO_BANK0_GPIO20_STATUS_IRQFROMPAD_ACCESS "RO" 3367 // ----------------------------------------------------------------------------- 3368 // Field : IO_BANK0_GPIO20_STATUS_INTOPERI 3369 // Description : input signal to peripheral, after override is applied 3370 #define IO_BANK0_GPIO20_STATUS_INTOPERI_RESET _u(0x0) 3371 #define IO_BANK0_GPIO20_STATUS_INTOPERI_BITS _u(0x00080000) 3372 #define IO_BANK0_GPIO20_STATUS_INTOPERI_MSB _u(19) 3373 #define IO_BANK0_GPIO20_STATUS_INTOPERI_LSB _u(19) 3374 #define IO_BANK0_GPIO20_STATUS_INTOPERI_ACCESS "RO" 3375 // ----------------------------------------------------------------------------- 3376 // Field : IO_BANK0_GPIO20_STATUS_INFROMPAD 3377 // Description : input signal from pad, before override is applied 3378 #define IO_BANK0_GPIO20_STATUS_INFROMPAD_RESET _u(0x0) 3379 #define IO_BANK0_GPIO20_STATUS_INFROMPAD_BITS _u(0x00020000) 3380 #define IO_BANK0_GPIO20_STATUS_INFROMPAD_MSB _u(17) 3381 #define IO_BANK0_GPIO20_STATUS_INFROMPAD_LSB _u(17) 3382 #define IO_BANK0_GPIO20_STATUS_INFROMPAD_ACCESS "RO" 3383 // ----------------------------------------------------------------------------- 3384 // Field : IO_BANK0_GPIO20_STATUS_OETOPAD 3385 // Description : output enable to pad after register override is applied 3386 #define IO_BANK0_GPIO20_STATUS_OETOPAD_RESET _u(0x0) 3387 #define IO_BANK0_GPIO20_STATUS_OETOPAD_BITS _u(0x00002000) 3388 #define IO_BANK0_GPIO20_STATUS_OETOPAD_MSB _u(13) 3389 #define IO_BANK0_GPIO20_STATUS_OETOPAD_LSB _u(13) 3390 #define IO_BANK0_GPIO20_STATUS_OETOPAD_ACCESS "RO" 3391 // ----------------------------------------------------------------------------- 3392 // Field : IO_BANK0_GPIO20_STATUS_OEFROMPERI 3393 // Description : output enable from selected peripheral, before register 3394 // override is applied 3395 #define IO_BANK0_GPIO20_STATUS_OEFROMPERI_RESET _u(0x0) 3396 #define IO_BANK0_GPIO20_STATUS_OEFROMPERI_BITS _u(0x00001000) 3397 #define IO_BANK0_GPIO20_STATUS_OEFROMPERI_MSB _u(12) 3398 #define IO_BANK0_GPIO20_STATUS_OEFROMPERI_LSB _u(12) 3399 #define IO_BANK0_GPIO20_STATUS_OEFROMPERI_ACCESS "RO" 3400 // ----------------------------------------------------------------------------- 3401 // Field : IO_BANK0_GPIO20_STATUS_OUTTOPAD 3402 // Description : output signal to pad after register override is applied 3403 #define IO_BANK0_GPIO20_STATUS_OUTTOPAD_RESET _u(0x0) 3404 #define IO_BANK0_GPIO20_STATUS_OUTTOPAD_BITS _u(0x00000200) 3405 #define IO_BANK0_GPIO20_STATUS_OUTTOPAD_MSB _u(9) 3406 #define IO_BANK0_GPIO20_STATUS_OUTTOPAD_LSB _u(9) 3407 #define IO_BANK0_GPIO20_STATUS_OUTTOPAD_ACCESS "RO" 3408 // ----------------------------------------------------------------------------- 3409 // Field : IO_BANK0_GPIO20_STATUS_OUTFROMPERI 3410 // Description : output signal from selected peripheral, before register 3411 // override is applied 3412 #define IO_BANK0_GPIO20_STATUS_OUTFROMPERI_RESET _u(0x0) 3413 #define IO_BANK0_GPIO20_STATUS_OUTFROMPERI_BITS _u(0x00000100) 3414 #define IO_BANK0_GPIO20_STATUS_OUTFROMPERI_MSB _u(8) 3415 #define IO_BANK0_GPIO20_STATUS_OUTFROMPERI_LSB _u(8) 3416 #define IO_BANK0_GPIO20_STATUS_OUTFROMPERI_ACCESS "RO" 3417 // ============================================================================= 3418 // Register : IO_BANK0_GPIO20_CTRL 3419 // Description : GPIO control including function select and overrides. 3420 #define IO_BANK0_GPIO20_CTRL_OFFSET _u(0x000000a4) 3421 #define IO_BANK0_GPIO20_CTRL_BITS _u(0x3003331f) 3422 #define IO_BANK0_GPIO20_CTRL_RESET _u(0x0000001f) 3423 // ----------------------------------------------------------------------------- 3424 // Field : IO_BANK0_GPIO20_CTRL_IRQOVER 3425 // 0x0 -> don't invert the interrupt 3426 // 0x1 -> invert the interrupt 3427 // 0x2 -> drive interrupt low 3428 // 0x3 -> drive interrupt high 3429 #define IO_BANK0_GPIO20_CTRL_IRQOVER_RESET _u(0x0) 3430 #define IO_BANK0_GPIO20_CTRL_IRQOVER_BITS _u(0x30000000) 3431 #define IO_BANK0_GPIO20_CTRL_IRQOVER_MSB _u(29) 3432 #define IO_BANK0_GPIO20_CTRL_IRQOVER_LSB _u(28) 3433 #define IO_BANK0_GPIO20_CTRL_IRQOVER_ACCESS "RW" 3434 #define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) 3435 #define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_INVERT _u(0x1) 3436 #define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_LOW _u(0x2) 3437 #define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_HIGH _u(0x3) 3438 // ----------------------------------------------------------------------------- 3439 // Field : IO_BANK0_GPIO20_CTRL_INOVER 3440 // 0x0 -> don't invert the peri input 3441 // 0x1 -> invert the peri input 3442 // 0x2 -> drive peri input low 3443 // 0x3 -> drive peri input high 3444 #define IO_BANK0_GPIO20_CTRL_INOVER_RESET _u(0x0) 3445 #define IO_BANK0_GPIO20_CTRL_INOVER_BITS _u(0x00030000) 3446 #define IO_BANK0_GPIO20_CTRL_INOVER_MSB _u(17) 3447 #define IO_BANK0_GPIO20_CTRL_INOVER_LSB _u(16) 3448 #define IO_BANK0_GPIO20_CTRL_INOVER_ACCESS "RW" 3449 #define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_NORMAL _u(0x0) 3450 #define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_INVERT _u(0x1) 3451 #define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_LOW _u(0x2) 3452 #define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_HIGH _u(0x3) 3453 // ----------------------------------------------------------------------------- 3454 // Field : IO_BANK0_GPIO20_CTRL_OEOVER 3455 // 0x0 -> drive output enable from peripheral signal selected by funcsel 3456 // 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel 3457 // 0x2 -> disable output 3458 // 0x3 -> enable output 3459 #define IO_BANK0_GPIO20_CTRL_OEOVER_RESET _u(0x0) 3460 #define IO_BANK0_GPIO20_CTRL_OEOVER_BITS _u(0x00003000) 3461 #define IO_BANK0_GPIO20_CTRL_OEOVER_MSB _u(13) 3462 #define IO_BANK0_GPIO20_CTRL_OEOVER_LSB _u(12) 3463 #define IO_BANK0_GPIO20_CTRL_OEOVER_ACCESS "RW" 3464 #define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_NORMAL _u(0x0) 3465 #define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_INVERT _u(0x1) 3466 #define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_DISABLE _u(0x2) 3467 #define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_ENABLE _u(0x3) 3468 // ----------------------------------------------------------------------------- 3469 // Field : IO_BANK0_GPIO20_CTRL_OUTOVER 3470 // 0x0 -> drive output from peripheral signal selected by funcsel 3471 // 0x1 -> drive output from inverse of peripheral signal selected by funcsel 3472 // 0x2 -> drive output low 3473 // 0x3 -> drive output high 3474 #define IO_BANK0_GPIO20_CTRL_OUTOVER_RESET _u(0x0) 3475 #define IO_BANK0_GPIO20_CTRL_OUTOVER_BITS _u(0x00000300) 3476 #define IO_BANK0_GPIO20_CTRL_OUTOVER_MSB _u(9) 3477 #define IO_BANK0_GPIO20_CTRL_OUTOVER_LSB _u(8) 3478 #define IO_BANK0_GPIO20_CTRL_OUTOVER_ACCESS "RW" 3479 #define IO_BANK0_GPIO20_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) 3480 #define IO_BANK0_GPIO20_CTRL_OUTOVER_VALUE_INVERT _u(0x1) 3481 #define IO_BANK0_GPIO20_CTRL_OUTOVER_VALUE_LOW _u(0x2) 3482 #define IO_BANK0_GPIO20_CTRL_OUTOVER_VALUE_HIGH _u(0x3) 3483 // ----------------------------------------------------------------------------- 3484 // Field : IO_BANK0_GPIO20_CTRL_FUNCSEL 3485 // Description : 0-31 -> selects pin function according to the gpio table 3486 // 31 == NULL 3487 // 0x01 -> spi0_rx 3488 // 0x02 -> uart1_tx 3489 // 0x03 -> i2c0_sda 3490 // 0x04 -> pwm_a_2 3491 // 0x05 -> sio_20 3492 // 0x06 -> pio0_20 3493 // 0x07 -> pio1_20 3494 // 0x08 -> clocks_gpin_0 3495 // 0x09 -> usb_muxing_vbus_en 3496 // 0x1f -> null 3497 #define IO_BANK0_GPIO20_CTRL_FUNCSEL_RESET _u(0x1f) 3498 #define IO_BANK0_GPIO20_CTRL_FUNCSEL_BITS _u(0x0000001f) 3499 #define IO_BANK0_GPIO20_CTRL_FUNCSEL_MSB _u(4) 3500 #define IO_BANK0_GPIO20_CTRL_FUNCSEL_LSB _u(0) 3501 #define IO_BANK0_GPIO20_CTRL_FUNCSEL_ACCESS "RW" 3502 #define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_SPI0_RX _u(0x01) 3503 #define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x02) 3504 #define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) 3505 #define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_PWM_A_2 _u(0x04) 3506 #define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_SIO_20 _u(0x05) 3507 #define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_PIO0_20 _u(0x06) 3508 #define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_PIO1_20 _u(0x07) 3509 #define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_CLOCKS_GPIN_0 _u(0x08) 3510 #define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09) 3511 #define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) 3512 // ============================================================================= 3513 // Register : IO_BANK0_GPIO21_STATUS 3514 // Description : GPIO status 3515 #define IO_BANK0_GPIO21_STATUS_OFFSET _u(0x000000a8) 3516 #define IO_BANK0_GPIO21_STATUS_BITS _u(0x050a3300) 3517 #define IO_BANK0_GPIO21_STATUS_RESET _u(0x00000000) 3518 // ----------------------------------------------------------------------------- 3519 // Field : IO_BANK0_GPIO21_STATUS_IRQTOPROC 3520 // Description : interrupt to processors, after override is applied 3521 #define IO_BANK0_GPIO21_STATUS_IRQTOPROC_RESET _u(0x0) 3522 #define IO_BANK0_GPIO21_STATUS_IRQTOPROC_BITS _u(0x04000000) 3523 #define IO_BANK0_GPIO21_STATUS_IRQTOPROC_MSB _u(26) 3524 #define IO_BANK0_GPIO21_STATUS_IRQTOPROC_LSB _u(26) 3525 #define IO_BANK0_GPIO21_STATUS_IRQTOPROC_ACCESS "RO" 3526 // ----------------------------------------------------------------------------- 3527 // Field : IO_BANK0_GPIO21_STATUS_IRQFROMPAD 3528 // Description : interrupt from pad before override is applied 3529 #define IO_BANK0_GPIO21_STATUS_IRQFROMPAD_RESET _u(0x0) 3530 #define IO_BANK0_GPIO21_STATUS_IRQFROMPAD_BITS _u(0x01000000) 3531 #define IO_BANK0_GPIO21_STATUS_IRQFROMPAD_MSB _u(24) 3532 #define IO_BANK0_GPIO21_STATUS_IRQFROMPAD_LSB _u(24) 3533 #define IO_BANK0_GPIO21_STATUS_IRQFROMPAD_ACCESS "RO" 3534 // ----------------------------------------------------------------------------- 3535 // Field : IO_BANK0_GPIO21_STATUS_INTOPERI 3536 // Description : input signal to peripheral, after override is applied 3537 #define IO_BANK0_GPIO21_STATUS_INTOPERI_RESET _u(0x0) 3538 #define IO_BANK0_GPIO21_STATUS_INTOPERI_BITS _u(0x00080000) 3539 #define IO_BANK0_GPIO21_STATUS_INTOPERI_MSB _u(19) 3540 #define IO_BANK0_GPIO21_STATUS_INTOPERI_LSB _u(19) 3541 #define IO_BANK0_GPIO21_STATUS_INTOPERI_ACCESS "RO" 3542 // ----------------------------------------------------------------------------- 3543 // Field : IO_BANK0_GPIO21_STATUS_INFROMPAD 3544 // Description : input signal from pad, before override is applied 3545 #define IO_BANK0_GPIO21_STATUS_INFROMPAD_RESET _u(0x0) 3546 #define IO_BANK0_GPIO21_STATUS_INFROMPAD_BITS _u(0x00020000) 3547 #define IO_BANK0_GPIO21_STATUS_INFROMPAD_MSB _u(17) 3548 #define IO_BANK0_GPIO21_STATUS_INFROMPAD_LSB _u(17) 3549 #define IO_BANK0_GPIO21_STATUS_INFROMPAD_ACCESS "RO" 3550 // ----------------------------------------------------------------------------- 3551 // Field : IO_BANK0_GPIO21_STATUS_OETOPAD 3552 // Description : output enable to pad after register override is applied 3553 #define IO_BANK0_GPIO21_STATUS_OETOPAD_RESET _u(0x0) 3554 #define IO_BANK0_GPIO21_STATUS_OETOPAD_BITS _u(0x00002000) 3555 #define IO_BANK0_GPIO21_STATUS_OETOPAD_MSB _u(13) 3556 #define IO_BANK0_GPIO21_STATUS_OETOPAD_LSB _u(13) 3557 #define IO_BANK0_GPIO21_STATUS_OETOPAD_ACCESS "RO" 3558 // ----------------------------------------------------------------------------- 3559 // Field : IO_BANK0_GPIO21_STATUS_OEFROMPERI 3560 // Description : output enable from selected peripheral, before register 3561 // override is applied 3562 #define IO_BANK0_GPIO21_STATUS_OEFROMPERI_RESET _u(0x0) 3563 #define IO_BANK0_GPIO21_STATUS_OEFROMPERI_BITS _u(0x00001000) 3564 #define IO_BANK0_GPIO21_STATUS_OEFROMPERI_MSB _u(12) 3565 #define IO_BANK0_GPIO21_STATUS_OEFROMPERI_LSB _u(12) 3566 #define IO_BANK0_GPIO21_STATUS_OEFROMPERI_ACCESS "RO" 3567 // ----------------------------------------------------------------------------- 3568 // Field : IO_BANK0_GPIO21_STATUS_OUTTOPAD 3569 // Description : output signal to pad after register override is applied 3570 #define IO_BANK0_GPIO21_STATUS_OUTTOPAD_RESET _u(0x0) 3571 #define IO_BANK0_GPIO21_STATUS_OUTTOPAD_BITS _u(0x00000200) 3572 #define IO_BANK0_GPIO21_STATUS_OUTTOPAD_MSB _u(9) 3573 #define IO_BANK0_GPIO21_STATUS_OUTTOPAD_LSB _u(9) 3574 #define IO_BANK0_GPIO21_STATUS_OUTTOPAD_ACCESS "RO" 3575 // ----------------------------------------------------------------------------- 3576 // Field : IO_BANK0_GPIO21_STATUS_OUTFROMPERI 3577 // Description : output signal from selected peripheral, before register 3578 // override is applied 3579 #define IO_BANK0_GPIO21_STATUS_OUTFROMPERI_RESET _u(0x0) 3580 #define IO_BANK0_GPIO21_STATUS_OUTFROMPERI_BITS _u(0x00000100) 3581 #define IO_BANK0_GPIO21_STATUS_OUTFROMPERI_MSB _u(8) 3582 #define IO_BANK0_GPIO21_STATUS_OUTFROMPERI_LSB _u(8) 3583 #define IO_BANK0_GPIO21_STATUS_OUTFROMPERI_ACCESS "RO" 3584 // ============================================================================= 3585 // Register : IO_BANK0_GPIO21_CTRL 3586 // Description : GPIO control including function select and overrides. 3587 #define IO_BANK0_GPIO21_CTRL_OFFSET _u(0x000000ac) 3588 #define IO_BANK0_GPIO21_CTRL_BITS _u(0x3003331f) 3589 #define IO_BANK0_GPIO21_CTRL_RESET _u(0x0000001f) 3590 // ----------------------------------------------------------------------------- 3591 // Field : IO_BANK0_GPIO21_CTRL_IRQOVER 3592 // 0x0 -> don't invert the interrupt 3593 // 0x1 -> invert the interrupt 3594 // 0x2 -> drive interrupt low 3595 // 0x3 -> drive interrupt high 3596 #define IO_BANK0_GPIO21_CTRL_IRQOVER_RESET _u(0x0) 3597 #define IO_BANK0_GPIO21_CTRL_IRQOVER_BITS _u(0x30000000) 3598 #define IO_BANK0_GPIO21_CTRL_IRQOVER_MSB _u(29) 3599 #define IO_BANK0_GPIO21_CTRL_IRQOVER_LSB _u(28) 3600 #define IO_BANK0_GPIO21_CTRL_IRQOVER_ACCESS "RW" 3601 #define IO_BANK0_GPIO21_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) 3602 #define IO_BANK0_GPIO21_CTRL_IRQOVER_VALUE_INVERT _u(0x1) 3603 #define IO_BANK0_GPIO21_CTRL_IRQOVER_VALUE_LOW _u(0x2) 3604 #define IO_BANK0_GPIO21_CTRL_IRQOVER_VALUE_HIGH _u(0x3) 3605 // ----------------------------------------------------------------------------- 3606 // Field : IO_BANK0_GPIO21_CTRL_INOVER 3607 // 0x0 -> don't invert the peri input 3608 // 0x1 -> invert the peri input 3609 // 0x2 -> drive peri input low 3610 // 0x3 -> drive peri input high 3611 #define IO_BANK0_GPIO21_CTRL_INOVER_RESET _u(0x0) 3612 #define IO_BANK0_GPIO21_CTRL_INOVER_BITS _u(0x00030000) 3613 #define IO_BANK0_GPIO21_CTRL_INOVER_MSB _u(17) 3614 #define IO_BANK0_GPIO21_CTRL_INOVER_LSB _u(16) 3615 #define IO_BANK0_GPIO21_CTRL_INOVER_ACCESS "RW" 3616 #define IO_BANK0_GPIO21_CTRL_INOVER_VALUE_NORMAL _u(0x0) 3617 #define IO_BANK0_GPIO21_CTRL_INOVER_VALUE_INVERT _u(0x1) 3618 #define IO_BANK0_GPIO21_CTRL_INOVER_VALUE_LOW _u(0x2) 3619 #define IO_BANK0_GPIO21_CTRL_INOVER_VALUE_HIGH _u(0x3) 3620 // ----------------------------------------------------------------------------- 3621 // Field : IO_BANK0_GPIO21_CTRL_OEOVER 3622 // 0x0 -> drive output enable from peripheral signal selected by funcsel 3623 // 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel 3624 // 0x2 -> disable output 3625 // 0x3 -> enable output 3626 #define IO_BANK0_GPIO21_CTRL_OEOVER_RESET _u(0x0) 3627 #define IO_BANK0_GPIO21_CTRL_OEOVER_BITS _u(0x00003000) 3628 #define IO_BANK0_GPIO21_CTRL_OEOVER_MSB _u(13) 3629 #define IO_BANK0_GPIO21_CTRL_OEOVER_LSB _u(12) 3630 #define IO_BANK0_GPIO21_CTRL_OEOVER_ACCESS "RW" 3631 #define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_NORMAL _u(0x0) 3632 #define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_INVERT _u(0x1) 3633 #define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_DISABLE _u(0x2) 3634 #define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_ENABLE _u(0x3) 3635 // ----------------------------------------------------------------------------- 3636 // Field : IO_BANK0_GPIO21_CTRL_OUTOVER 3637 // 0x0 -> drive output from peripheral signal selected by funcsel 3638 // 0x1 -> drive output from inverse of peripheral signal selected by funcsel 3639 // 0x2 -> drive output low 3640 // 0x3 -> drive output high 3641 #define IO_BANK0_GPIO21_CTRL_OUTOVER_RESET _u(0x0) 3642 #define IO_BANK0_GPIO21_CTRL_OUTOVER_BITS _u(0x00000300) 3643 #define IO_BANK0_GPIO21_CTRL_OUTOVER_MSB _u(9) 3644 #define IO_BANK0_GPIO21_CTRL_OUTOVER_LSB _u(8) 3645 #define IO_BANK0_GPIO21_CTRL_OUTOVER_ACCESS "RW" 3646 #define IO_BANK0_GPIO21_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) 3647 #define IO_BANK0_GPIO21_CTRL_OUTOVER_VALUE_INVERT _u(0x1) 3648 #define IO_BANK0_GPIO21_CTRL_OUTOVER_VALUE_LOW _u(0x2) 3649 #define IO_BANK0_GPIO21_CTRL_OUTOVER_VALUE_HIGH _u(0x3) 3650 // ----------------------------------------------------------------------------- 3651 // Field : IO_BANK0_GPIO21_CTRL_FUNCSEL 3652 // Description : 0-31 -> selects pin function according to the gpio table 3653 // 31 == NULL 3654 // 0x01 -> spi0_ss_n 3655 // 0x02 -> uart1_rx 3656 // 0x03 -> i2c0_scl 3657 // 0x04 -> pwm_b_2 3658 // 0x05 -> sio_21 3659 // 0x06 -> pio0_21 3660 // 0x07 -> pio1_21 3661 // 0x08 -> clocks_gpout_0 3662 // 0x09 -> usb_muxing_overcurr_detect 3663 // 0x1f -> null 3664 #define IO_BANK0_GPIO21_CTRL_FUNCSEL_RESET _u(0x1f) 3665 #define IO_BANK0_GPIO21_CTRL_FUNCSEL_BITS _u(0x0000001f) 3666 #define IO_BANK0_GPIO21_CTRL_FUNCSEL_MSB _u(4) 3667 #define IO_BANK0_GPIO21_CTRL_FUNCSEL_LSB _u(0) 3668 #define IO_BANK0_GPIO21_CTRL_FUNCSEL_ACCESS "RW" 3669 #define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_SPI0_SS_N _u(0x01) 3670 #define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x02) 3671 #define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) 3672 #define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_PWM_B_2 _u(0x04) 3673 #define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_SIO_21 _u(0x05) 3674 #define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_PIO0_21 _u(0x06) 3675 #define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_PIO1_21 _u(0x07) 3676 #define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_0 _u(0x08) 3677 #define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09) 3678 #define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) 3679 // ============================================================================= 3680 // Register : IO_BANK0_GPIO22_STATUS 3681 // Description : GPIO status 3682 #define IO_BANK0_GPIO22_STATUS_OFFSET _u(0x000000b0) 3683 #define IO_BANK0_GPIO22_STATUS_BITS _u(0x050a3300) 3684 #define IO_BANK0_GPIO22_STATUS_RESET _u(0x00000000) 3685 // ----------------------------------------------------------------------------- 3686 // Field : IO_BANK0_GPIO22_STATUS_IRQTOPROC 3687 // Description : interrupt to processors, after override is applied 3688 #define IO_BANK0_GPIO22_STATUS_IRQTOPROC_RESET _u(0x0) 3689 #define IO_BANK0_GPIO22_STATUS_IRQTOPROC_BITS _u(0x04000000) 3690 #define IO_BANK0_GPIO22_STATUS_IRQTOPROC_MSB _u(26) 3691 #define IO_BANK0_GPIO22_STATUS_IRQTOPROC_LSB _u(26) 3692 #define IO_BANK0_GPIO22_STATUS_IRQTOPROC_ACCESS "RO" 3693 // ----------------------------------------------------------------------------- 3694 // Field : IO_BANK0_GPIO22_STATUS_IRQFROMPAD 3695 // Description : interrupt from pad before override is applied 3696 #define IO_BANK0_GPIO22_STATUS_IRQFROMPAD_RESET _u(0x0) 3697 #define IO_BANK0_GPIO22_STATUS_IRQFROMPAD_BITS _u(0x01000000) 3698 #define IO_BANK0_GPIO22_STATUS_IRQFROMPAD_MSB _u(24) 3699 #define IO_BANK0_GPIO22_STATUS_IRQFROMPAD_LSB _u(24) 3700 #define IO_BANK0_GPIO22_STATUS_IRQFROMPAD_ACCESS "RO" 3701 // ----------------------------------------------------------------------------- 3702 // Field : IO_BANK0_GPIO22_STATUS_INTOPERI 3703 // Description : input signal to peripheral, after override is applied 3704 #define IO_BANK0_GPIO22_STATUS_INTOPERI_RESET _u(0x0) 3705 #define IO_BANK0_GPIO22_STATUS_INTOPERI_BITS _u(0x00080000) 3706 #define IO_BANK0_GPIO22_STATUS_INTOPERI_MSB _u(19) 3707 #define IO_BANK0_GPIO22_STATUS_INTOPERI_LSB _u(19) 3708 #define IO_BANK0_GPIO22_STATUS_INTOPERI_ACCESS "RO" 3709 // ----------------------------------------------------------------------------- 3710 // Field : IO_BANK0_GPIO22_STATUS_INFROMPAD 3711 // Description : input signal from pad, before override is applied 3712 #define IO_BANK0_GPIO22_STATUS_INFROMPAD_RESET _u(0x0) 3713 #define IO_BANK0_GPIO22_STATUS_INFROMPAD_BITS _u(0x00020000) 3714 #define IO_BANK0_GPIO22_STATUS_INFROMPAD_MSB _u(17) 3715 #define IO_BANK0_GPIO22_STATUS_INFROMPAD_LSB _u(17) 3716 #define IO_BANK0_GPIO22_STATUS_INFROMPAD_ACCESS "RO" 3717 // ----------------------------------------------------------------------------- 3718 // Field : IO_BANK0_GPIO22_STATUS_OETOPAD 3719 // Description : output enable to pad after register override is applied 3720 #define IO_BANK0_GPIO22_STATUS_OETOPAD_RESET _u(0x0) 3721 #define IO_BANK0_GPIO22_STATUS_OETOPAD_BITS _u(0x00002000) 3722 #define IO_BANK0_GPIO22_STATUS_OETOPAD_MSB _u(13) 3723 #define IO_BANK0_GPIO22_STATUS_OETOPAD_LSB _u(13) 3724 #define IO_BANK0_GPIO22_STATUS_OETOPAD_ACCESS "RO" 3725 // ----------------------------------------------------------------------------- 3726 // Field : IO_BANK0_GPIO22_STATUS_OEFROMPERI 3727 // Description : output enable from selected peripheral, before register 3728 // override is applied 3729 #define IO_BANK0_GPIO22_STATUS_OEFROMPERI_RESET _u(0x0) 3730 #define IO_BANK0_GPIO22_STATUS_OEFROMPERI_BITS _u(0x00001000) 3731 #define IO_BANK0_GPIO22_STATUS_OEFROMPERI_MSB _u(12) 3732 #define IO_BANK0_GPIO22_STATUS_OEFROMPERI_LSB _u(12) 3733 #define IO_BANK0_GPIO22_STATUS_OEFROMPERI_ACCESS "RO" 3734 // ----------------------------------------------------------------------------- 3735 // Field : IO_BANK0_GPIO22_STATUS_OUTTOPAD 3736 // Description : output signal to pad after register override is applied 3737 #define IO_BANK0_GPIO22_STATUS_OUTTOPAD_RESET _u(0x0) 3738 #define IO_BANK0_GPIO22_STATUS_OUTTOPAD_BITS _u(0x00000200) 3739 #define IO_BANK0_GPIO22_STATUS_OUTTOPAD_MSB _u(9) 3740 #define IO_BANK0_GPIO22_STATUS_OUTTOPAD_LSB _u(9) 3741 #define IO_BANK0_GPIO22_STATUS_OUTTOPAD_ACCESS "RO" 3742 // ----------------------------------------------------------------------------- 3743 // Field : IO_BANK0_GPIO22_STATUS_OUTFROMPERI 3744 // Description : output signal from selected peripheral, before register 3745 // override is applied 3746 #define IO_BANK0_GPIO22_STATUS_OUTFROMPERI_RESET _u(0x0) 3747 #define IO_BANK0_GPIO22_STATUS_OUTFROMPERI_BITS _u(0x00000100) 3748 #define IO_BANK0_GPIO22_STATUS_OUTFROMPERI_MSB _u(8) 3749 #define IO_BANK0_GPIO22_STATUS_OUTFROMPERI_LSB _u(8) 3750 #define IO_BANK0_GPIO22_STATUS_OUTFROMPERI_ACCESS "RO" 3751 // ============================================================================= 3752 // Register : IO_BANK0_GPIO22_CTRL 3753 // Description : GPIO control including function select and overrides. 3754 #define IO_BANK0_GPIO22_CTRL_OFFSET _u(0x000000b4) 3755 #define IO_BANK0_GPIO22_CTRL_BITS _u(0x3003331f) 3756 #define IO_BANK0_GPIO22_CTRL_RESET _u(0x0000001f) 3757 // ----------------------------------------------------------------------------- 3758 // Field : IO_BANK0_GPIO22_CTRL_IRQOVER 3759 // 0x0 -> don't invert the interrupt 3760 // 0x1 -> invert the interrupt 3761 // 0x2 -> drive interrupt low 3762 // 0x3 -> drive interrupt high 3763 #define IO_BANK0_GPIO22_CTRL_IRQOVER_RESET _u(0x0) 3764 #define IO_BANK0_GPIO22_CTRL_IRQOVER_BITS _u(0x30000000) 3765 #define IO_BANK0_GPIO22_CTRL_IRQOVER_MSB _u(29) 3766 #define IO_BANK0_GPIO22_CTRL_IRQOVER_LSB _u(28) 3767 #define IO_BANK0_GPIO22_CTRL_IRQOVER_ACCESS "RW" 3768 #define IO_BANK0_GPIO22_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) 3769 #define IO_BANK0_GPIO22_CTRL_IRQOVER_VALUE_INVERT _u(0x1) 3770 #define IO_BANK0_GPIO22_CTRL_IRQOVER_VALUE_LOW _u(0x2) 3771 #define IO_BANK0_GPIO22_CTRL_IRQOVER_VALUE_HIGH _u(0x3) 3772 // ----------------------------------------------------------------------------- 3773 // Field : IO_BANK0_GPIO22_CTRL_INOVER 3774 // 0x0 -> don't invert the peri input 3775 // 0x1 -> invert the peri input 3776 // 0x2 -> drive peri input low 3777 // 0x3 -> drive peri input high 3778 #define IO_BANK0_GPIO22_CTRL_INOVER_RESET _u(0x0) 3779 #define IO_BANK0_GPIO22_CTRL_INOVER_BITS _u(0x00030000) 3780 #define IO_BANK0_GPIO22_CTRL_INOVER_MSB _u(17) 3781 #define IO_BANK0_GPIO22_CTRL_INOVER_LSB _u(16) 3782 #define IO_BANK0_GPIO22_CTRL_INOVER_ACCESS "RW" 3783 #define IO_BANK0_GPIO22_CTRL_INOVER_VALUE_NORMAL _u(0x0) 3784 #define IO_BANK0_GPIO22_CTRL_INOVER_VALUE_INVERT _u(0x1) 3785 #define IO_BANK0_GPIO22_CTRL_INOVER_VALUE_LOW _u(0x2) 3786 #define IO_BANK0_GPIO22_CTRL_INOVER_VALUE_HIGH _u(0x3) 3787 // ----------------------------------------------------------------------------- 3788 // Field : IO_BANK0_GPIO22_CTRL_OEOVER 3789 // 0x0 -> drive output enable from peripheral signal selected by funcsel 3790 // 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel 3791 // 0x2 -> disable output 3792 // 0x3 -> enable output 3793 #define IO_BANK0_GPIO22_CTRL_OEOVER_RESET _u(0x0) 3794 #define IO_BANK0_GPIO22_CTRL_OEOVER_BITS _u(0x00003000) 3795 #define IO_BANK0_GPIO22_CTRL_OEOVER_MSB _u(13) 3796 #define IO_BANK0_GPIO22_CTRL_OEOVER_LSB _u(12) 3797 #define IO_BANK0_GPIO22_CTRL_OEOVER_ACCESS "RW" 3798 #define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_NORMAL _u(0x0) 3799 #define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_INVERT _u(0x1) 3800 #define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_DISABLE _u(0x2) 3801 #define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_ENABLE _u(0x3) 3802 // ----------------------------------------------------------------------------- 3803 // Field : IO_BANK0_GPIO22_CTRL_OUTOVER 3804 // 0x0 -> drive output from peripheral signal selected by funcsel 3805 // 0x1 -> drive output from inverse of peripheral signal selected by funcsel 3806 // 0x2 -> drive output low 3807 // 0x3 -> drive output high 3808 #define IO_BANK0_GPIO22_CTRL_OUTOVER_RESET _u(0x0) 3809 #define IO_BANK0_GPIO22_CTRL_OUTOVER_BITS _u(0x00000300) 3810 #define IO_BANK0_GPIO22_CTRL_OUTOVER_MSB _u(9) 3811 #define IO_BANK0_GPIO22_CTRL_OUTOVER_LSB _u(8) 3812 #define IO_BANK0_GPIO22_CTRL_OUTOVER_ACCESS "RW" 3813 #define IO_BANK0_GPIO22_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) 3814 #define IO_BANK0_GPIO22_CTRL_OUTOVER_VALUE_INVERT _u(0x1) 3815 #define IO_BANK0_GPIO22_CTRL_OUTOVER_VALUE_LOW _u(0x2) 3816 #define IO_BANK0_GPIO22_CTRL_OUTOVER_VALUE_HIGH _u(0x3) 3817 // ----------------------------------------------------------------------------- 3818 // Field : IO_BANK0_GPIO22_CTRL_FUNCSEL 3819 // Description : 0-31 -> selects pin function according to the gpio table 3820 // 31 == NULL 3821 // 0x01 -> spi0_sclk 3822 // 0x02 -> uart1_cts 3823 // 0x03 -> i2c1_sda 3824 // 0x04 -> pwm_a_3 3825 // 0x05 -> sio_22 3826 // 0x06 -> pio0_22 3827 // 0x07 -> pio1_22 3828 // 0x08 -> clocks_gpin_1 3829 // 0x09 -> usb_muxing_vbus_detect 3830 // 0x1f -> null 3831 #define IO_BANK0_GPIO22_CTRL_FUNCSEL_RESET _u(0x1f) 3832 #define IO_BANK0_GPIO22_CTRL_FUNCSEL_BITS _u(0x0000001f) 3833 #define IO_BANK0_GPIO22_CTRL_FUNCSEL_MSB _u(4) 3834 #define IO_BANK0_GPIO22_CTRL_FUNCSEL_LSB _u(0) 3835 #define IO_BANK0_GPIO22_CTRL_FUNCSEL_ACCESS "RW" 3836 #define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_SPI0_SCLK _u(0x01) 3837 #define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_UART1_CTS _u(0x02) 3838 #define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) 3839 #define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_PWM_A_3 _u(0x04) 3840 #define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_SIO_22 _u(0x05) 3841 #define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_PIO0_22 _u(0x06) 3842 #define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_PIO1_22 _u(0x07) 3843 #define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_CLOCKS_GPIN_1 _u(0x08) 3844 #define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09) 3845 #define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) 3846 // ============================================================================= 3847 // Register : IO_BANK0_GPIO23_STATUS 3848 // Description : GPIO status 3849 #define IO_BANK0_GPIO23_STATUS_OFFSET _u(0x000000b8) 3850 #define IO_BANK0_GPIO23_STATUS_BITS _u(0x050a3300) 3851 #define IO_BANK0_GPIO23_STATUS_RESET _u(0x00000000) 3852 // ----------------------------------------------------------------------------- 3853 // Field : IO_BANK0_GPIO23_STATUS_IRQTOPROC 3854 // Description : interrupt to processors, after override is applied 3855 #define IO_BANK0_GPIO23_STATUS_IRQTOPROC_RESET _u(0x0) 3856 #define IO_BANK0_GPIO23_STATUS_IRQTOPROC_BITS _u(0x04000000) 3857 #define IO_BANK0_GPIO23_STATUS_IRQTOPROC_MSB _u(26) 3858 #define IO_BANK0_GPIO23_STATUS_IRQTOPROC_LSB _u(26) 3859 #define IO_BANK0_GPIO23_STATUS_IRQTOPROC_ACCESS "RO" 3860 // ----------------------------------------------------------------------------- 3861 // Field : IO_BANK0_GPIO23_STATUS_IRQFROMPAD 3862 // Description : interrupt from pad before override is applied 3863 #define IO_BANK0_GPIO23_STATUS_IRQFROMPAD_RESET _u(0x0) 3864 #define IO_BANK0_GPIO23_STATUS_IRQFROMPAD_BITS _u(0x01000000) 3865 #define IO_BANK0_GPIO23_STATUS_IRQFROMPAD_MSB _u(24) 3866 #define IO_BANK0_GPIO23_STATUS_IRQFROMPAD_LSB _u(24) 3867 #define IO_BANK0_GPIO23_STATUS_IRQFROMPAD_ACCESS "RO" 3868 // ----------------------------------------------------------------------------- 3869 // Field : IO_BANK0_GPIO23_STATUS_INTOPERI 3870 // Description : input signal to peripheral, after override is applied 3871 #define IO_BANK0_GPIO23_STATUS_INTOPERI_RESET _u(0x0) 3872 #define IO_BANK0_GPIO23_STATUS_INTOPERI_BITS _u(0x00080000) 3873 #define IO_BANK0_GPIO23_STATUS_INTOPERI_MSB _u(19) 3874 #define IO_BANK0_GPIO23_STATUS_INTOPERI_LSB _u(19) 3875 #define IO_BANK0_GPIO23_STATUS_INTOPERI_ACCESS "RO" 3876 // ----------------------------------------------------------------------------- 3877 // Field : IO_BANK0_GPIO23_STATUS_INFROMPAD 3878 // Description : input signal from pad, before override is applied 3879 #define IO_BANK0_GPIO23_STATUS_INFROMPAD_RESET _u(0x0) 3880 #define IO_BANK0_GPIO23_STATUS_INFROMPAD_BITS _u(0x00020000) 3881 #define IO_BANK0_GPIO23_STATUS_INFROMPAD_MSB _u(17) 3882 #define IO_BANK0_GPIO23_STATUS_INFROMPAD_LSB _u(17) 3883 #define IO_BANK0_GPIO23_STATUS_INFROMPAD_ACCESS "RO" 3884 // ----------------------------------------------------------------------------- 3885 // Field : IO_BANK0_GPIO23_STATUS_OETOPAD 3886 // Description : output enable to pad after register override is applied 3887 #define IO_BANK0_GPIO23_STATUS_OETOPAD_RESET _u(0x0) 3888 #define IO_BANK0_GPIO23_STATUS_OETOPAD_BITS _u(0x00002000) 3889 #define IO_BANK0_GPIO23_STATUS_OETOPAD_MSB _u(13) 3890 #define IO_BANK0_GPIO23_STATUS_OETOPAD_LSB _u(13) 3891 #define IO_BANK0_GPIO23_STATUS_OETOPAD_ACCESS "RO" 3892 // ----------------------------------------------------------------------------- 3893 // Field : IO_BANK0_GPIO23_STATUS_OEFROMPERI 3894 // Description : output enable from selected peripheral, before register 3895 // override is applied 3896 #define IO_BANK0_GPIO23_STATUS_OEFROMPERI_RESET _u(0x0) 3897 #define IO_BANK0_GPIO23_STATUS_OEFROMPERI_BITS _u(0x00001000) 3898 #define IO_BANK0_GPIO23_STATUS_OEFROMPERI_MSB _u(12) 3899 #define IO_BANK0_GPIO23_STATUS_OEFROMPERI_LSB _u(12) 3900 #define IO_BANK0_GPIO23_STATUS_OEFROMPERI_ACCESS "RO" 3901 // ----------------------------------------------------------------------------- 3902 // Field : IO_BANK0_GPIO23_STATUS_OUTTOPAD 3903 // Description : output signal to pad after register override is applied 3904 #define IO_BANK0_GPIO23_STATUS_OUTTOPAD_RESET _u(0x0) 3905 #define IO_BANK0_GPIO23_STATUS_OUTTOPAD_BITS _u(0x00000200) 3906 #define IO_BANK0_GPIO23_STATUS_OUTTOPAD_MSB _u(9) 3907 #define IO_BANK0_GPIO23_STATUS_OUTTOPAD_LSB _u(9) 3908 #define IO_BANK0_GPIO23_STATUS_OUTTOPAD_ACCESS "RO" 3909 // ----------------------------------------------------------------------------- 3910 // Field : IO_BANK0_GPIO23_STATUS_OUTFROMPERI 3911 // Description : output signal from selected peripheral, before register 3912 // override is applied 3913 #define IO_BANK0_GPIO23_STATUS_OUTFROMPERI_RESET _u(0x0) 3914 #define IO_BANK0_GPIO23_STATUS_OUTFROMPERI_BITS _u(0x00000100) 3915 #define IO_BANK0_GPIO23_STATUS_OUTFROMPERI_MSB _u(8) 3916 #define IO_BANK0_GPIO23_STATUS_OUTFROMPERI_LSB _u(8) 3917 #define IO_BANK0_GPIO23_STATUS_OUTFROMPERI_ACCESS "RO" 3918 // ============================================================================= 3919 // Register : IO_BANK0_GPIO23_CTRL 3920 // Description : GPIO control including function select and overrides. 3921 #define IO_BANK0_GPIO23_CTRL_OFFSET _u(0x000000bc) 3922 #define IO_BANK0_GPIO23_CTRL_BITS _u(0x3003331f) 3923 #define IO_BANK0_GPIO23_CTRL_RESET _u(0x0000001f) 3924 // ----------------------------------------------------------------------------- 3925 // Field : IO_BANK0_GPIO23_CTRL_IRQOVER 3926 // 0x0 -> don't invert the interrupt 3927 // 0x1 -> invert the interrupt 3928 // 0x2 -> drive interrupt low 3929 // 0x3 -> drive interrupt high 3930 #define IO_BANK0_GPIO23_CTRL_IRQOVER_RESET _u(0x0) 3931 #define IO_BANK0_GPIO23_CTRL_IRQOVER_BITS _u(0x30000000) 3932 #define IO_BANK0_GPIO23_CTRL_IRQOVER_MSB _u(29) 3933 #define IO_BANK0_GPIO23_CTRL_IRQOVER_LSB _u(28) 3934 #define IO_BANK0_GPIO23_CTRL_IRQOVER_ACCESS "RW" 3935 #define IO_BANK0_GPIO23_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) 3936 #define IO_BANK0_GPIO23_CTRL_IRQOVER_VALUE_INVERT _u(0x1) 3937 #define IO_BANK0_GPIO23_CTRL_IRQOVER_VALUE_LOW _u(0x2) 3938 #define IO_BANK0_GPIO23_CTRL_IRQOVER_VALUE_HIGH _u(0x3) 3939 // ----------------------------------------------------------------------------- 3940 // Field : IO_BANK0_GPIO23_CTRL_INOVER 3941 // 0x0 -> don't invert the peri input 3942 // 0x1 -> invert the peri input 3943 // 0x2 -> drive peri input low 3944 // 0x3 -> drive peri input high 3945 #define IO_BANK0_GPIO23_CTRL_INOVER_RESET _u(0x0) 3946 #define IO_BANK0_GPIO23_CTRL_INOVER_BITS _u(0x00030000) 3947 #define IO_BANK0_GPIO23_CTRL_INOVER_MSB _u(17) 3948 #define IO_BANK0_GPIO23_CTRL_INOVER_LSB _u(16) 3949 #define IO_BANK0_GPIO23_CTRL_INOVER_ACCESS "RW" 3950 #define IO_BANK0_GPIO23_CTRL_INOVER_VALUE_NORMAL _u(0x0) 3951 #define IO_BANK0_GPIO23_CTRL_INOVER_VALUE_INVERT _u(0x1) 3952 #define IO_BANK0_GPIO23_CTRL_INOVER_VALUE_LOW _u(0x2) 3953 #define IO_BANK0_GPIO23_CTRL_INOVER_VALUE_HIGH _u(0x3) 3954 // ----------------------------------------------------------------------------- 3955 // Field : IO_BANK0_GPIO23_CTRL_OEOVER 3956 // 0x0 -> drive output enable from peripheral signal selected by funcsel 3957 // 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel 3958 // 0x2 -> disable output 3959 // 0x3 -> enable output 3960 #define IO_BANK0_GPIO23_CTRL_OEOVER_RESET _u(0x0) 3961 #define IO_BANK0_GPIO23_CTRL_OEOVER_BITS _u(0x00003000) 3962 #define IO_BANK0_GPIO23_CTRL_OEOVER_MSB _u(13) 3963 #define IO_BANK0_GPIO23_CTRL_OEOVER_LSB _u(12) 3964 #define IO_BANK0_GPIO23_CTRL_OEOVER_ACCESS "RW" 3965 #define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_NORMAL _u(0x0) 3966 #define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_INVERT _u(0x1) 3967 #define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_DISABLE _u(0x2) 3968 #define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_ENABLE _u(0x3) 3969 // ----------------------------------------------------------------------------- 3970 // Field : IO_BANK0_GPIO23_CTRL_OUTOVER 3971 // 0x0 -> drive output from peripheral signal selected by funcsel 3972 // 0x1 -> drive output from inverse of peripheral signal selected by funcsel 3973 // 0x2 -> drive output low 3974 // 0x3 -> drive output high 3975 #define IO_BANK0_GPIO23_CTRL_OUTOVER_RESET _u(0x0) 3976 #define IO_BANK0_GPIO23_CTRL_OUTOVER_BITS _u(0x00000300) 3977 #define IO_BANK0_GPIO23_CTRL_OUTOVER_MSB _u(9) 3978 #define IO_BANK0_GPIO23_CTRL_OUTOVER_LSB _u(8) 3979 #define IO_BANK0_GPIO23_CTRL_OUTOVER_ACCESS "RW" 3980 #define IO_BANK0_GPIO23_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) 3981 #define IO_BANK0_GPIO23_CTRL_OUTOVER_VALUE_INVERT _u(0x1) 3982 #define IO_BANK0_GPIO23_CTRL_OUTOVER_VALUE_LOW _u(0x2) 3983 #define IO_BANK0_GPIO23_CTRL_OUTOVER_VALUE_HIGH _u(0x3) 3984 // ----------------------------------------------------------------------------- 3985 // Field : IO_BANK0_GPIO23_CTRL_FUNCSEL 3986 // Description : 0-31 -> selects pin function according to the gpio table 3987 // 31 == NULL 3988 // 0x01 -> spi0_tx 3989 // 0x02 -> uart1_rts 3990 // 0x03 -> i2c1_scl 3991 // 0x04 -> pwm_b_3 3992 // 0x05 -> sio_23 3993 // 0x06 -> pio0_23 3994 // 0x07 -> pio1_23 3995 // 0x08 -> clocks_gpout_1 3996 // 0x09 -> usb_muxing_vbus_en 3997 // 0x1f -> null 3998 #define IO_BANK0_GPIO23_CTRL_FUNCSEL_RESET _u(0x1f) 3999 #define IO_BANK0_GPIO23_CTRL_FUNCSEL_BITS _u(0x0000001f) 4000 #define IO_BANK0_GPIO23_CTRL_FUNCSEL_MSB _u(4) 4001 #define IO_BANK0_GPIO23_CTRL_FUNCSEL_LSB _u(0) 4002 #define IO_BANK0_GPIO23_CTRL_FUNCSEL_ACCESS "RW" 4003 #define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_SPI0_TX _u(0x01) 4004 #define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_UART1_RTS _u(0x02) 4005 #define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) 4006 #define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_PWM_B_3 _u(0x04) 4007 #define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_SIO_23 _u(0x05) 4008 #define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_PIO0_23 _u(0x06) 4009 #define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_PIO1_23 _u(0x07) 4010 #define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_1 _u(0x08) 4011 #define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09) 4012 #define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) 4013 // ============================================================================= 4014 // Register : IO_BANK0_GPIO24_STATUS 4015 // Description : GPIO status 4016 #define IO_BANK0_GPIO24_STATUS_OFFSET _u(0x000000c0) 4017 #define IO_BANK0_GPIO24_STATUS_BITS _u(0x050a3300) 4018 #define IO_BANK0_GPIO24_STATUS_RESET _u(0x00000000) 4019 // ----------------------------------------------------------------------------- 4020 // Field : IO_BANK0_GPIO24_STATUS_IRQTOPROC 4021 // Description : interrupt to processors, after override is applied 4022 #define IO_BANK0_GPIO24_STATUS_IRQTOPROC_RESET _u(0x0) 4023 #define IO_BANK0_GPIO24_STATUS_IRQTOPROC_BITS _u(0x04000000) 4024 #define IO_BANK0_GPIO24_STATUS_IRQTOPROC_MSB _u(26) 4025 #define IO_BANK0_GPIO24_STATUS_IRQTOPROC_LSB _u(26) 4026 #define IO_BANK0_GPIO24_STATUS_IRQTOPROC_ACCESS "RO" 4027 // ----------------------------------------------------------------------------- 4028 // Field : IO_BANK0_GPIO24_STATUS_IRQFROMPAD 4029 // Description : interrupt from pad before override is applied 4030 #define IO_BANK0_GPIO24_STATUS_IRQFROMPAD_RESET _u(0x0) 4031 #define IO_BANK0_GPIO24_STATUS_IRQFROMPAD_BITS _u(0x01000000) 4032 #define IO_BANK0_GPIO24_STATUS_IRQFROMPAD_MSB _u(24) 4033 #define IO_BANK0_GPIO24_STATUS_IRQFROMPAD_LSB _u(24) 4034 #define IO_BANK0_GPIO24_STATUS_IRQFROMPAD_ACCESS "RO" 4035 // ----------------------------------------------------------------------------- 4036 // Field : IO_BANK0_GPIO24_STATUS_INTOPERI 4037 // Description : input signal to peripheral, after override is applied 4038 #define IO_BANK0_GPIO24_STATUS_INTOPERI_RESET _u(0x0) 4039 #define IO_BANK0_GPIO24_STATUS_INTOPERI_BITS _u(0x00080000) 4040 #define IO_BANK0_GPIO24_STATUS_INTOPERI_MSB _u(19) 4041 #define IO_BANK0_GPIO24_STATUS_INTOPERI_LSB _u(19) 4042 #define IO_BANK0_GPIO24_STATUS_INTOPERI_ACCESS "RO" 4043 // ----------------------------------------------------------------------------- 4044 // Field : IO_BANK0_GPIO24_STATUS_INFROMPAD 4045 // Description : input signal from pad, before override is applied 4046 #define IO_BANK0_GPIO24_STATUS_INFROMPAD_RESET _u(0x0) 4047 #define IO_BANK0_GPIO24_STATUS_INFROMPAD_BITS _u(0x00020000) 4048 #define IO_BANK0_GPIO24_STATUS_INFROMPAD_MSB _u(17) 4049 #define IO_BANK0_GPIO24_STATUS_INFROMPAD_LSB _u(17) 4050 #define IO_BANK0_GPIO24_STATUS_INFROMPAD_ACCESS "RO" 4051 // ----------------------------------------------------------------------------- 4052 // Field : IO_BANK0_GPIO24_STATUS_OETOPAD 4053 // Description : output enable to pad after register override is applied 4054 #define IO_BANK0_GPIO24_STATUS_OETOPAD_RESET _u(0x0) 4055 #define IO_BANK0_GPIO24_STATUS_OETOPAD_BITS _u(0x00002000) 4056 #define IO_BANK0_GPIO24_STATUS_OETOPAD_MSB _u(13) 4057 #define IO_BANK0_GPIO24_STATUS_OETOPAD_LSB _u(13) 4058 #define IO_BANK0_GPIO24_STATUS_OETOPAD_ACCESS "RO" 4059 // ----------------------------------------------------------------------------- 4060 // Field : IO_BANK0_GPIO24_STATUS_OEFROMPERI 4061 // Description : output enable from selected peripheral, before register 4062 // override is applied 4063 #define IO_BANK0_GPIO24_STATUS_OEFROMPERI_RESET _u(0x0) 4064 #define IO_BANK0_GPIO24_STATUS_OEFROMPERI_BITS _u(0x00001000) 4065 #define IO_BANK0_GPIO24_STATUS_OEFROMPERI_MSB _u(12) 4066 #define IO_BANK0_GPIO24_STATUS_OEFROMPERI_LSB _u(12) 4067 #define IO_BANK0_GPIO24_STATUS_OEFROMPERI_ACCESS "RO" 4068 // ----------------------------------------------------------------------------- 4069 // Field : IO_BANK0_GPIO24_STATUS_OUTTOPAD 4070 // Description : output signal to pad after register override is applied 4071 #define IO_BANK0_GPIO24_STATUS_OUTTOPAD_RESET _u(0x0) 4072 #define IO_BANK0_GPIO24_STATUS_OUTTOPAD_BITS _u(0x00000200) 4073 #define IO_BANK0_GPIO24_STATUS_OUTTOPAD_MSB _u(9) 4074 #define IO_BANK0_GPIO24_STATUS_OUTTOPAD_LSB _u(9) 4075 #define IO_BANK0_GPIO24_STATUS_OUTTOPAD_ACCESS "RO" 4076 // ----------------------------------------------------------------------------- 4077 // Field : IO_BANK0_GPIO24_STATUS_OUTFROMPERI 4078 // Description : output signal from selected peripheral, before register 4079 // override is applied 4080 #define IO_BANK0_GPIO24_STATUS_OUTFROMPERI_RESET _u(0x0) 4081 #define IO_BANK0_GPIO24_STATUS_OUTFROMPERI_BITS _u(0x00000100) 4082 #define IO_BANK0_GPIO24_STATUS_OUTFROMPERI_MSB _u(8) 4083 #define IO_BANK0_GPIO24_STATUS_OUTFROMPERI_LSB _u(8) 4084 #define IO_BANK0_GPIO24_STATUS_OUTFROMPERI_ACCESS "RO" 4085 // ============================================================================= 4086 // Register : IO_BANK0_GPIO24_CTRL 4087 // Description : GPIO control including function select and overrides. 4088 #define IO_BANK0_GPIO24_CTRL_OFFSET _u(0x000000c4) 4089 #define IO_BANK0_GPIO24_CTRL_BITS _u(0x3003331f) 4090 #define IO_BANK0_GPIO24_CTRL_RESET _u(0x0000001f) 4091 // ----------------------------------------------------------------------------- 4092 // Field : IO_BANK0_GPIO24_CTRL_IRQOVER 4093 // 0x0 -> don't invert the interrupt 4094 // 0x1 -> invert the interrupt 4095 // 0x2 -> drive interrupt low 4096 // 0x3 -> drive interrupt high 4097 #define IO_BANK0_GPIO24_CTRL_IRQOVER_RESET _u(0x0) 4098 #define IO_BANK0_GPIO24_CTRL_IRQOVER_BITS _u(0x30000000) 4099 #define IO_BANK0_GPIO24_CTRL_IRQOVER_MSB _u(29) 4100 #define IO_BANK0_GPIO24_CTRL_IRQOVER_LSB _u(28) 4101 #define IO_BANK0_GPIO24_CTRL_IRQOVER_ACCESS "RW" 4102 #define IO_BANK0_GPIO24_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) 4103 #define IO_BANK0_GPIO24_CTRL_IRQOVER_VALUE_INVERT _u(0x1) 4104 #define IO_BANK0_GPIO24_CTRL_IRQOVER_VALUE_LOW _u(0x2) 4105 #define IO_BANK0_GPIO24_CTRL_IRQOVER_VALUE_HIGH _u(0x3) 4106 // ----------------------------------------------------------------------------- 4107 // Field : IO_BANK0_GPIO24_CTRL_INOVER 4108 // 0x0 -> don't invert the peri input 4109 // 0x1 -> invert the peri input 4110 // 0x2 -> drive peri input low 4111 // 0x3 -> drive peri input high 4112 #define IO_BANK0_GPIO24_CTRL_INOVER_RESET _u(0x0) 4113 #define IO_BANK0_GPIO24_CTRL_INOVER_BITS _u(0x00030000) 4114 #define IO_BANK0_GPIO24_CTRL_INOVER_MSB _u(17) 4115 #define IO_BANK0_GPIO24_CTRL_INOVER_LSB _u(16) 4116 #define IO_BANK0_GPIO24_CTRL_INOVER_ACCESS "RW" 4117 #define IO_BANK0_GPIO24_CTRL_INOVER_VALUE_NORMAL _u(0x0) 4118 #define IO_BANK0_GPIO24_CTRL_INOVER_VALUE_INVERT _u(0x1) 4119 #define IO_BANK0_GPIO24_CTRL_INOVER_VALUE_LOW _u(0x2) 4120 #define IO_BANK0_GPIO24_CTRL_INOVER_VALUE_HIGH _u(0x3) 4121 // ----------------------------------------------------------------------------- 4122 // Field : IO_BANK0_GPIO24_CTRL_OEOVER 4123 // 0x0 -> drive output enable from peripheral signal selected by funcsel 4124 // 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel 4125 // 0x2 -> disable output 4126 // 0x3 -> enable output 4127 #define IO_BANK0_GPIO24_CTRL_OEOVER_RESET _u(0x0) 4128 #define IO_BANK0_GPIO24_CTRL_OEOVER_BITS _u(0x00003000) 4129 #define IO_BANK0_GPIO24_CTRL_OEOVER_MSB _u(13) 4130 #define IO_BANK0_GPIO24_CTRL_OEOVER_LSB _u(12) 4131 #define IO_BANK0_GPIO24_CTRL_OEOVER_ACCESS "RW" 4132 #define IO_BANK0_GPIO24_CTRL_OEOVER_VALUE_NORMAL _u(0x0) 4133 #define IO_BANK0_GPIO24_CTRL_OEOVER_VALUE_INVERT _u(0x1) 4134 #define IO_BANK0_GPIO24_CTRL_OEOVER_VALUE_DISABLE _u(0x2) 4135 #define IO_BANK0_GPIO24_CTRL_OEOVER_VALUE_ENABLE _u(0x3) 4136 // ----------------------------------------------------------------------------- 4137 // Field : IO_BANK0_GPIO24_CTRL_OUTOVER 4138 // 0x0 -> drive output from peripheral signal selected by funcsel 4139 // 0x1 -> drive output from inverse of peripheral signal selected by funcsel 4140 // 0x2 -> drive output low 4141 // 0x3 -> drive output high 4142 #define IO_BANK0_GPIO24_CTRL_OUTOVER_RESET _u(0x0) 4143 #define IO_BANK0_GPIO24_CTRL_OUTOVER_BITS _u(0x00000300) 4144 #define IO_BANK0_GPIO24_CTRL_OUTOVER_MSB _u(9) 4145 #define IO_BANK0_GPIO24_CTRL_OUTOVER_LSB _u(8) 4146 #define IO_BANK0_GPIO24_CTRL_OUTOVER_ACCESS "RW" 4147 #define IO_BANK0_GPIO24_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) 4148 #define IO_BANK0_GPIO24_CTRL_OUTOVER_VALUE_INVERT _u(0x1) 4149 #define IO_BANK0_GPIO24_CTRL_OUTOVER_VALUE_LOW _u(0x2) 4150 #define IO_BANK0_GPIO24_CTRL_OUTOVER_VALUE_HIGH _u(0x3) 4151 // ----------------------------------------------------------------------------- 4152 // Field : IO_BANK0_GPIO24_CTRL_FUNCSEL 4153 // Description : 0-31 -> selects pin function according to the gpio table 4154 // 31 == NULL 4155 // 0x01 -> spi1_rx 4156 // 0x02 -> uart1_tx 4157 // 0x03 -> i2c0_sda 4158 // 0x04 -> pwm_a_4 4159 // 0x05 -> sio_24 4160 // 0x06 -> pio0_24 4161 // 0x07 -> pio1_24 4162 // 0x08 -> clocks_gpout_2 4163 // 0x09 -> usb_muxing_overcurr_detect 4164 // 0x1f -> null 4165 #define IO_BANK0_GPIO24_CTRL_FUNCSEL_RESET _u(0x1f) 4166 #define IO_BANK0_GPIO24_CTRL_FUNCSEL_BITS _u(0x0000001f) 4167 #define IO_BANK0_GPIO24_CTRL_FUNCSEL_MSB _u(4) 4168 #define IO_BANK0_GPIO24_CTRL_FUNCSEL_LSB _u(0) 4169 #define IO_BANK0_GPIO24_CTRL_FUNCSEL_ACCESS "RW" 4170 #define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_SPI1_RX _u(0x01) 4171 #define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x02) 4172 #define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) 4173 #define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_PWM_A_4 _u(0x04) 4174 #define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_SIO_24 _u(0x05) 4175 #define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_PIO0_24 _u(0x06) 4176 #define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_PIO1_24 _u(0x07) 4177 #define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_2 _u(0x08) 4178 #define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09) 4179 #define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) 4180 // ============================================================================= 4181 // Register : IO_BANK0_GPIO25_STATUS 4182 // Description : GPIO status 4183 #define IO_BANK0_GPIO25_STATUS_OFFSET _u(0x000000c8) 4184 #define IO_BANK0_GPIO25_STATUS_BITS _u(0x050a3300) 4185 #define IO_BANK0_GPIO25_STATUS_RESET _u(0x00000000) 4186 // ----------------------------------------------------------------------------- 4187 // Field : IO_BANK0_GPIO25_STATUS_IRQTOPROC 4188 // Description : interrupt to processors, after override is applied 4189 #define IO_BANK0_GPIO25_STATUS_IRQTOPROC_RESET _u(0x0) 4190 #define IO_BANK0_GPIO25_STATUS_IRQTOPROC_BITS _u(0x04000000) 4191 #define IO_BANK0_GPIO25_STATUS_IRQTOPROC_MSB _u(26) 4192 #define IO_BANK0_GPIO25_STATUS_IRQTOPROC_LSB _u(26) 4193 #define IO_BANK0_GPIO25_STATUS_IRQTOPROC_ACCESS "RO" 4194 // ----------------------------------------------------------------------------- 4195 // Field : IO_BANK0_GPIO25_STATUS_IRQFROMPAD 4196 // Description : interrupt from pad before override is applied 4197 #define IO_BANK0_GPIO25_STATUS_IRQFROMPAD_RESET _u(0x0) 4198 #define IO_BANK0_GPIO25_STATUS_IRQFROMPAD_BITS _u(0x01000000) 4199 #define IO_BANK0_GPIO25_STATUS_IRQFROMPAD_MSB _u(24) 4200 #define IO_BANK0_GPIO25_STATUS_IRQFROMPAD_LSB _u(24) 4201 #define IO_BANK0_GPIO25_STATUS_IRQFROMPAD_ACCESS "RO" 4202 // ----------------------------------------------------------------------------- 4203 // Field : IO_BANK0_GPIO25_STATUS_INTOPERI 4204 // Description : input signal to peripheral, after override is applied 4205 #define IO_BANK0_GPIO25_STATUS_INTOPERI_RESET _u(0x0) 4206 #define IO_BANK0_GPIO25_STATUS_INTOPERI_BITS _u(0x00080000) 4207 #define IO_BANK0_GPIO25_STATUS_INTOPERI_MSB _u(19) 4208 #define IO_BANK0_GPIO25_STATUS_INTOPERI_LSB _u(19) 4209 #define IO_BANK0_GPIO25_STATUS_INTOPERI_ACCESS "RO" 4210 // ----------------------------------------------------------------------------- 4211 // Field : IO_BANK0_GPIO25_STATUS_INFROMPAD 4212 // Description : input signal from pad, before override is applied 4213 #define IO_BANK0_GPIO25_STATUS_INFROMPAD_RESET _u(0x0) 4214 #define IO_BANK0_GPIO25_STATUS_INFROMPAD_BITS _u(0x00020000) 4215 #define IO_BANK0_GPIO25_STATUS_INFROMPAD_MSB _u(17) 4216 #define IO_BANK0_GPIO25_STATUS_INFROMPAD_LSB _u(17) 4217 #define IO_BANK0_GPIO25_STATUS_INFROMPAD_ACCESS "RO" 4218 // ----------------------------------------------------------------------------- 4219 // Field : IO_BANK0_GPIO25_STATUS_OETOPAD 4220 // Description : output enable to pad after register override is applied 4221 #define IO_BANK0_GPIO25_STATUS_OETOPAD_RESET _u(0x0) 4222 #define IO_BANK0_GPIO25_STATUS_OETOPAD_BITS _u(0x00002000) 4223 #define IO_BANK0_GPIO25_STATUS_OETOPAD_MSB _u(13) 4224 #define IO_BANK0_GPIO25_STATUS_OETOPAD_LSB _u(13) 4225 #define IO_BANK0_GPIO25_STATUS_OETOPAD_ACCESS "RO" 4226 // ----------------------------------------------------------------------------- 4227 // Field : IO_BANK0_GPIO25_STATUS_OEFROMPERI 4228 // Description : output enable from selected peripheral, before register 4229 // override is applied 4230 #define IO_BANK0_GPIO25_STATUS_OEFROMPERI_RESET _u(0x0) 4231 #define IO_BANK0_GPIO25_STATUS_OEFROMPERI_BITS _u(0x00001000) 4232 #define IO_BANK0_GPIO25_STATUS_OEFROMPERI_MSB _u(12) 4233 #define IO_BANK0_GPIO25_STATUS_OEFROMPERI_LSB _u(12) 4234 #define IO_BANK0_GPIO25_STATUS_OEFROMPERI_ACCESS "RO" 4235 // ----------------------------------------------------------------------------- 4236 // Field : IO_BANK0_GPIO25_STATUS_OUTTOPAD 4237 // Description : output signal to pad after register override is applied 4238 #define IO_BANK0_GPIO25_STATUS_OUTTOPAD_RESET _u(0x0) 4239 #define IO_BANK0_GPIO25_STATUS_OUTTOPAD_BITS _u(0x00000200) 4240 #define IO_BANK0_GPIO25_STATUS_OUTTOPAD_MSB _u(9) 4241 #define IO_BANK0_GPIO25_STATUS_OUTTOPAD_LSB _u(9) 4242 #define IO_BANK0_GPIO25_STATUS_OUTTOPAD_ACCESS "RO" 4243 // ----------------------------------------------------------------------------- 4244 // Field : IO_BANK0_GPIO25_STATUS_OUTFROMPERI 4245 // Description : output signal from selected peripheral, before register 4246 // override is applied 4247 #define IO_BANK0_GPIO25_STATUS_OUTFROMPERI_RESET _u(0x0) 4248 #define IO_BANK0_GPIO25_STATUS_OUTFROMPERI_BITS _u(0x00000100) 4249 #define IO_BANK0_GPIO25_STATUS_OUTFROMPERI_MSB _u(8) 4250 #define IO_BANK0_GPIO25_STATUS_OUTFROMPERI_LSB _u(8) 4251 #define IO_BANK0_GPIO25_STATUS_OUTFROMPERI_ACCESS "RO" 4252 // ============================================================================= 4253 // Register : IO_BANK0_GPIO25_CTRL 4254 // Description : GPIO control including function select and overrides. 4255 #define IO_BANK0_GPIO25_CTRL_OFFSET _u(0x000000cc) 4256 #define IO_BANK0_GPIO25_CTRL_BITS _u(0x3003331f) 4257 #define IO_BANK0_GPIO25_CTRL_RESET _u(0x0000001f) 4258 // ----------------------------------------------------------------------------- 4259 // Field : IO_BANK0_GPIO25_CTRL_IRQOVER 4260 // 0x0 -> don't invert the interrupt 4261 // 0x1 -> invert the interrupt 4262 // 0x2 -> drive interrupt low 4263 // 0x3 -> drive interrupt high 4264 #define IO_BANK0_GPIO25_CTRL_IRQOVER_RESET _u(0x0) 4265 #define IO_BANK0_GPIO25_CTRL_IRQOVER_BITS _u(0x30000000) 4266 #define IO_BANK0_GPIO25_CTRL_IRQOVER_MSB _u(29) 4267 #define IO_BANK0_GPIO25_CTRL_IRQOVER_LSB _u(28) 4268 #define IO_BANK0_GPIO25_CTRL_IRQOVER_ACCESS "RW" 4269 #define IO_BANK0_GPIO25_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) 4270 #define IO_BANK0_GPIO25_CTRL_IRQOVER_VALUE_INVERT _u(0x1) 4271 #define IO_BANK0_GPIO25_CTRL_IRQOVER_VALUE_LOW _u(0x2) 4272 #define IO_BANK0_GPIO25_CTRL_IRQOVER_VALUE_HIGH _u(0x3) 4273 // ----------------------------------------------------------------------------- 4274 // Field : IO_BANK0_GPIO25_CTRL_INOVER 4275 // 0x0 -> don't invert the peri input 4276 // 0x1 -> invert the peri input 4277 // 0x2 -> drive peri input low 4278 // 0x3 -> drive peri input high 4279 #define IO_BANK0_GPIO25_CTRL_INOVER_RESET _u(0x0) 4280 #define IO_BANK0_GPIO25_CTRL_INOVER_BITS _u(0x00030000) 4281 #define IO_BANK0_GPIO25_CTRL_INOVER_MSB _u(17) 4282 #define IO_BANK0_GPIO25_CTRL_INOVER_LSB _u(16) 4283 #define IO_BANK0_GPIO25_CTRL_INOVER_ACCESS "RW" 4284 #define IO_BANK0_GPIO25_CTRL_INOVER_VALUE_NORMAL _u(0x0) 4285 #define IO_BANK0_GPIO25_CTRL_INOVER_VALUE_INVERT _u(0x1) 4286 #define IO_BANK0_GPIO25_CTRL_INOVER_VALUE_LOW _u(0x2) 4287 #define IO_BANK0_GPIO25_CTRL_INOVER_VALUE_HIGH _u(0x3) 4288 // ----------------------------------------------------------------------------- 4289 // Field : IO_BANK0_GPIO25_CTRL_OEOVER 4290 // 0x0 -> drive output enable from peripheral signal selected by funcsel 4291 // 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel 4292 // 0x2 -> disable output 4293 // 0x3 -> enable output 4294 #define IO_BANK0_GPIO25_CTRL_OEOVER_RESET _u(0x0) 4295 #define IO_BANK0_GPIO25_CTRL_OEOVER_BITS _u(0x00003000) 4296 #define IO_BANK0_GPIO25_CTRL_OEOVER_MSB _u(13) 4297 #define IO_BANK0_GPIO25_CTRL_OEOVER_LSB _u(12) 4298 #define IO_BANK0_GPIO25_CTRL_OEOVER_ACCESS "RW" 4299 #define IO_BANK0_GPIO25_CTRL_OEOVER_VALUE_NORMAL _u(0x0) 4300 #define IO_BANK0_GPIO25_CTRL_OEOVER_VALUE_INVERT _u(0x1) 4301 #define IO_BANK0_GPIO25_CTRL_OEOVER_VALUE_DISABLE _u(0x2) 4302 #define IO_BANK0_GPIO25_CTRL_OEOVER_VALUE_ENABLE _u(0x3) 4303 // ----------------------------------------------------------------------------- 4304 // Field : IO_BANK0_GPIO25_CTRL_OUTOVER 4305 // 0x0 -> drive output from peripheral signal selected by funcsel 4306 // 0x1 -> drive output from inverse of peripheral signal selected by funcsel 4307 // 0x2 -> drive output low 4308 // 0x3 -> drive output high 4309 #define IO_BANK0_GPIO25_CTRL_OUTOVER_RESET _u(0x0) 4310 #define IO_BANK0_GPIO25_CTRL_OUTOVER_BITS _u(0x00000300) 4311 #define IO_BANK0_GPIO25_CTRL_OUTOVER_MSB _u(9) 4312 #define IO_BANK0_GPIO25_CTRL_OUTOVER_LSB _u(8) 4313 #define IO_BANK0_GPIO25_CTRL_OUTOVER_ACCESS "RW" 4314 #define IO_BANK0_GPIO25_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) 4315 #define IO_BANK0_GPIO25_CTRL_OUTOVER_VALUE_INVERT _u(0x1) 4316 #define IO_BANK0_GPIO25_CTRL_OUTOVER_VALUE_LOW _u(0x2) 4317 #define IO_BANK0_GPIO25_CTRL_OUTOVER_VALUE_HIGH _u(0x3) 4318 // ----------------------------------------------------------------------------- 4319 // Field : IO_BANK0_GPIO25_CTRL_FUNCSEL 4320 // Description : 0-31 -> selects pin function according to the gpio table 4321 // 31 == NULL 4322 // 0x01 -> spi1_ss_n 4323 // 0x02 -> uart1_rx 4324 // 0x03 -> i2c0_scl 4325 // 0x04 -> pwm_b_4 4326 // 0x05 -> sio_25 4327 // 0x06 -> pio0_25 4328 // 0x07 -> pio1_25 4329 // 0x08 -> clocks_gpout_3 4330 // 0x09 -> usb_muxing_vbus_detect 4331 // 0x1f -> null 4332 #define IO_BANK0_GPIO25_CTRL_FUNCSEL_RESET _u(0x1f) 4333 #define IO_BANK0_GPIO25_CTRL_FUNCSEL_BITS _u(0x0000001f) 4334 #define IO_BANK0_GPIO25_CTRL_FUNCSEL_MSB _u(4) 4335 #define IO_BANK0_GPIO25_CTRL_FUNCSEL_LSB _u(0) 4336 #define IO_BANK0_GPIO25_CTRL_FUNCSEL_ACCESS "RW" 4337 #define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_SPI1_SS_N _u(0x01) 4338 #define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x02) 4339 #define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) 4340 #define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_PWM_B_4 _u(0x04) 4341 #define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_SIO_25 _u(0x05) 4342 #define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_PIO0_25 _u(0x06) 4343 #define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_PIO1_25 _u(0x07) 4344 #define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_3 _u(0x08) 4345 #define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09) 4346 #define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) 4347 // ============================================================================= 4348 // Register : IO_BANK0_GPIO26_STATUS 4349 // Description : GPIO status 4350 #define IO_BANK0_GPIO26_STATUS_OFFSET _u(0x000000d0) 4351 #define IO_BANK0_GPIO26_STATUS_BITS _u(0x050a3300) 4352 #define IO_BANK0_GPIO26_STATUS_RESET _u(0x00000000) 4353 // ----------------------------------------------------------------------------- 4354 // Field : IO_BANK0_GPIO26_STATUS_IRQTOPROC 4355 // Description : interrupt to processors, after override is applied 4356 #define IO_BANK0_GPIO26_STATUS_IRQTOPROC_RESET _u(0x0) 4357 #define IO_BANK0_GPIO26_STATUS_IRQTOPROC_BITS _u(0x04000000) 4358 #define IO_BANK0_GPIO26_STATUS_IRQTOPROC_MSB _u(26) 4359 #define IO_BANK0_GPIO26_STATUS_IRQTOPROC_LSB _u(26) 4360 #define IO_BANK0_GPIO26_STATUS_IRQTOPROC_ACCESS "RO" 4361 // ----------------------------------------------------------------------------- 4362 // Field : IO_BANK0_GPIO26_STATUS_IRQFROMPAD 4363 // Description : interrupt from pad before override is applied 4364 #define IO_BANK0_GPIO26_STATUS_IRQFROMPAD_RESET _u(0x0) 4365 #define IO_BANK0_GPIO26_STATUS_IRQFROMPAD_BITS _u(0x01000000) 4366 #define IO_BANK0_GPIO26_STATUS_IRQFROMPAD_MSB _u(24) 4367 #define IO_BANK0_GPIO26_STATUS_IRQFROMPAD_LSB _u(24) 4368 #define IO_BANK0_GPIO26_STATUS_IRQFROMPAD_ACCESS "RO" 4369 // ----------------------------------------------------------------------------- 4370 // Field : IO_BANK0_GPIO26_STATUS_INTOPERI 4371 // Description : input signal to peripheral, after override is applied 4372 #define IO_BANK0_GPIO26_STATUS_INTOPERI_RESET _u(0x0) 4373 #define IO_BANK0_GPIO26_STATUS_INTOPERI_BITS _u(0x00080000) 4374 #define IO_BANK0_GPIO26_STATUS_INTOPERI_MSB _u(19) 4375 #define IO_BANK0_GPIO26_STATUS_INTOPERI_LSB _u(19) 4376 #define IO_BANK0_GPIO26_STATUS_INTOPERI_ACCESS "RO" 4377 // ----------------------------------------------------------------------------- 4378 // Field : IO_BANK0_GPIO26_STATUS_INFROMPAD 4379 // Description : input signal from pad, before override is applied 4380 #define IO_BANK0_GPIO26_STATUS_INFROMPAD_RESET _u(0x0) 4381 #define IO_BANK0_GPIO26_STATUS_INFROMPAD_BITS _u(0x00020000) 4382 #define IO_BANK0_GPIO26_STATUS_INFROMPAD_MSB _u(17) 4383 #define IO_BANK0_GPIO26_STATUS_INFROMPAD_LSB _u(17) 4384 #define IO_BANK0_GPIO26_STATUS_INFROMPAD_ACCESS "RO" 4385 // ----------------------------------------------------------------------------- 4386 // Field : IO_BANK0_GPIO26_STATUS_OETOPAD 4387 // Description : output enable to pad after register override is applied 4388 #define IO_BANK0_GPIO26_STATUS_OETOPAD_RESET _u(0x0) 4389 #define IO_BANK0_GPIO26_STATUS_OETOPAD_BITS _u(0x00002000) 4390 #define IO_BANK0_GPIO26_STATUS_OETOPAD_MSB _u(13) 4391 #define IO_BANK0_GPIO26_STATUS_OETOPAD_LSB _u(13) 4392 #define IO_BANK0_GPIO26_STATUS_OETOPAD_ACCESS "RO" 4393 // ----------------------------------------------------------------------------- 4394 // Field : IO_BANK0_GPIO26_STATUS_OEFROMPERI 4395 // Description : output enable from selected peripheral, before register 4396 // override is applied 4397 #define IO_BANK0_GPIO26_STATUS_OEFROMPERI_RESET _u(0x0) 4398 #define IO_BANK0_GPIO26_STATUS_OEFROMPERI_BITS _u(0x00001000) 4399 #define IO_BANK0_GPIO26_STATUS_OEFROMPERI_MSB _u(12) 4400 #define IO_BANK0_GPIO26_STATUS_OEFROMPERI_LSB _u(12) 4401 #define IO_BANK0_GPIO26_STATUS_OEFROMPERI_ACCESS "RO" 4402 // ----------------------------------------------------------------------------- 4403 // Field : IO_BANK0_GPIO26_STATUS_OUTTOPAD 4404 // Description : output signal to pad after register override is applied 4405 #define IO_BANK0_GPIO26_STATUS_OUTTOPAD_RESET _u(0x0) 4406 #define IO_BANK0_GPIO26_STATUS_OUTTOPAD_BITS _u(0x00000200) 4407 #define IO_BANK0_GPIO26_STATUS_OUTTOPAD_MSB _u(9) 4408 #define IO_BANK0_GPIO26_STATUS_OUTTOPAD_LSB _u(9) 4409 #define IO_BANK0_GPIO26_STATUS_OUTTOPAD_ACCESS "RO" 4410 // ----------------------------------------------------------------------------- 4411 // Field : IO_BANK0_GPIO26_STATUS_OUTFROMPERI 4412 // Description : output signal from selected peripheral, before register 4413 // override is applied 4414 #define IO_BANK0_GPIO26_STATUS_OUTFROMPERI_RESET _u(0x0) 4415 #define IO_BANK0_GPIO26_STATUS_OUTFROMPERI_BITS _u(0x00000100) 4416 #define IO_BANK0_GPIO26_STATUS_OUTFROMPERI_MSB _u(8) 4417 #define IO_BANK0_GPIO26_STATUS_OUTFROMPERI_LSB _u(8) 4418 #define IO_BANK0_GPIO26_STATUS_OUTFROMPERI_ACCESS "RO" 4419 // ============================================================================= 4420 // Register : IO_BANK0_GPIO26_CTRL 4421 // Description : GPIO control including function select and overrides. 4422 #define IO_BANK0_GPIO26_CTRL_OFFSET _u(0x000000d4) 4423 #define IO_BANK0_GPIO26_CTRL_BITS _u(0x3003331f) 4424 #define IO_BANK0_GPIO26_CTRL_RESET _u(0x0000001f) 4425 // ----------------------------------------------------------------------------- 4426 // Field : IO_BANK0_GPIO26_CTRL_IRQOVER 4427 // 0x0 -> don't invert the interrupt 4428 // 0x1 -> invert the interrupt 4429 // 0x2 -> drive interrupt low 4430 // 0x3 -> drive interrupt high 4431 #define IO_BANK0_GPIO26_CTRL_IRQOVER_RESET _u(0x0) 4432 #define IO_BANK0_GPIO26_CTRL_IRQOVER_BITS _u(0x30000000) 4433 #define IO_BANK0_GPIO26_CTRL_IRQOVER_MSB _u(29) 4434 #define IO_BANK0_GPIO26_CTRL_IRQOVER_LSB _u(28) 4435 #define IO_BANK0_GPIO26_CTRL_IRQOVER_ACCESS "RW" 4436 #define IO_BANK0_GPIO26_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) 4437 #define IO_BANK0_GPIO26_CTRL_IRQOVER_VALUE_INVERT _u(0x1) 4438 #define IO_BANK0_GPIO26_CTRL_IRQOVER_VALUE_LOW _u(0x2) 4439 #define IO_BANK0_GPIO26_CTRL_IRQOVER_VALUE_HIGH _u(0x3) 4440 // ----------------------------------------------------------------------------- 4441 // Field : IO_BANK0_GPIO26_CTRL_INOVER 4442 // 0x0 -> don't invert the peri input 4443 // 0x1 -> invert the peri input 4444 // 0x2 -> drive peri input low 4445 // 0x3 -> drive peri input high 4446 #define IO_BANK0_GPIO26_CTRL_INOVER_RESET _u(0x0) 4447 #define IO_BANK0_GPIO26_CTRL_INOVER_BITS _u(0x00030000) 4448 #define IO_BANK0_GPIO26_CTRL_INOVER_MSB _u(17) 4449 #define IO_BANK0_GPIO26_CTRL_INOVER_LSB _u(16) 4450 #define IO_BANK0_GPIO26_CTRL_INOVER_ACCESS "RW" 4451 #define IO_BANK0_GPIO26_CTRL_INOVER_VALUE_NORMAL _u(0x0) 4452 #define IO_BANK0_GPIO26_CTRL_INOVER_VALUE_INVERT _u(0x1) 4453 #define IO_BANK0_GPIO26_CTRL_INOVER_VALUE_LOW _u(0x2) 4454 #define IO_BANK0_GPIO26_CTRL_INOVER_VALUE_HIGH _u(0x3) 4455 // ----------------------------------------------------------------------------- 4456 // Field : IO_BANK0_GPIO26_CTRL_OEOVER 4457 // 0x0 -> drive output enable from peripheral signal selected by funcsel 4458 // 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel 4459 // 0x2 -> disable output 4460 // 0x3 -> enable output 4461 #define IO_BANK0_GPIO26_CTRL_OEOVER_RESET _u(0x0) 4462 #define IO_BANK0_GPIO26_CTRL_OEOVER_BITS _u(0x00003000) 4463 #define IO_BANK0_GPIO26_CTRL_OEOVER_MSB _u(13) 4464 #define IO_BANK0_GPIO26_CTRL_OEOVER_LSB _u(12) 4465 #define IO_BANK0_GPIO26_CTRL_OEOVER_ACCESS "RW" 4466 #define IO_BANK0_GPIO26_CTRL_OEOVER_VALUE_NORMAL _u(0x0) 4467 #define IO_BANK0_GPIO26_CTRL_OEOVER_VALUE_INVERT _u(0x1) 4468 #define IO_BANK0_GPIO26_CTRL_OEOVER_VALUE_DISABLE _u(0x2) 4469 #define IO_BANK0_GPIO26_CTRL_OEOVER_VALUE_ENABLE _u(0x3) 4470 // ----------------------------------------------------------------------------- 4471 // Field : IO_BANK0_GPIO26_CTRL_OUTOVER 4472 // 0x0 -> drive output from peripheral signal selected by funcsel 4473 // 0x1 -> drive output from inverse of peripheral signal selected by funcsel 4474 // 0x2 -> drive output low 4475 // 0x3 -> drive output high 4476 #define IO_BANK0_GPIO26_CTRL_OUTOVER_RESET _u(0x0) 4477 #define IO_BANK0_GPIO26_CTRL_OUTOVER_BITS _u(0x00000300) 4478 #define IO_BANK0_GPIO26_CTRL_OUTOVER_MSB _u(9) 4479 #define IO_BANK0_GPIO26_CTRL_OUTOVER_LSB _u(8) 4480 #define IO_BANK0_GPIO26_CTRL_OUTOVER_ACCESS "RW" 4481 #define IO_BANK0_GPIO26_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) 4482 #define IO_BANK0_GPIO26_CTRL_OUTOVER_VALUE_INVERT _u(0x1) 4483 #define IO_BANK0_GPIO26_CTRL_OUTOVER_VALUE_LOW _u(0x2) 4484 #define IO_BANK0_GPIO26_CTRL_OUTOVER_VALUE_HIGH _u(0x3) 4485 // ----------------------------------------------------------------------------- 4486 // Field : IO_BANK0_GPIO26_CTRL_FUNCSEL 4487 // Description : 0-31 -> selects pin function according to the gpio table 4488 // 31 == NULL 4489 // 0x01 -> spi1_sclk 4490 // 0x02 -> uart1_cts 4491 // 0x03 -> i2c1_sda 4492 // 0x04 -> pwm_a_5 4493 // 0x05 -> sio_26 4494 // 0x06 -> pio0_26 4495 // 0x07 -> pio1_26 4496 // 0x09 -> usb_muxing_vbus_en 4497 // 0x1f -> null 4498 #define IO_BANK0_GPIO26_CTRL_FUNCSEL_RESET _u(0x1f) 4499 #define IO_BANK0_GPIO26_CTRL_FUNCSEL_BITS _u(0x0000001f) 4500 #define IO_BANK0_GPIO26_CTRL_FUNCSEL_MSB _u(4) 4501 #define IO_BANK0_GPIO26_CTRL_FUNCSEL_LSB _u(0) 4502 #define IO_BANK0_GPIO26_CTRL_FUNCSEL_ACCESS "RW" 4503 #define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_SPI1_SCLK _u(0x01) 4504 #define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_UART1_CTS _u(0x02) 4505 #define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) 4506 #define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_PWM_A_5 _u(0x04) 4507 #define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_SIO_26 _u(0x05) 4508 #define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_PIO0_26 _u(0x06) 4509 #define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_PIO1_26 _u(0x07) 4510 #define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09) 4511 #define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) 4512 // ============================================================================= 4513 // Register : IO_BANK0_GPIO27_STATUS 4514 // Description : GPIO status 4515 #define IO_BANK0_GPIO27_STATUS_OFFSET _u(0x000000d8) 4516 #define IO_BANK0_GPIO27_STATUS_BITS _u(0x050a3300) 4517 #define IO_BANK0_GPIO27_STATUS_RESET _u(0x00000000) 4518 // ----------------------------------------------------------------------------- 4519 // Field : IO_BANK0_GPIO27_STATUS_IRQTOPROC 4520 // Description : interrupt to processors, after override is applied 4521 #define IO_BANK0_GPIO27_STATUS_IRQTOPROC_RESET _u(0x0) 4522 #define IO_BANK0_GPIO27_STATUS_IRQTOPROC_BITS _u(0x04000000) 4523 #define IO_BANK0_GPIO27_STATUS_IRQTOPROC_MSB _u(26) 4524 #define IO_BANK0_GPIO27_STATUS_IRQTOPROC_LSB _u(26) 4525 #define IO_BANK0_GPIO27_STATUS_IRQTOPROC_ACCESS "RO" 4526 // ----------------------------------------------------------------------------- 4527 // Field : IO_BANK0_GPIO27_STATUS_IRQFROMPAD 4528 // Description : interrupt from pad before override is applied 4529 #define IO_BANK0_GPIO27_STATUS_IRQFROMPAD_RESET _u(0x0) 4530 #define IO_BANK0_GPIO27_STATUS_IRQFROMPAD_BITS _u(0x01000000) 4531 #define IO_BANK0_GPIO27_STATUS_IRQFROMPAD_MSB _u(24) 4532 #define IO_BANK0_GPIO27_STATUS_IRQFROMPAD_LSB _u(24) 4533 #define IO_BANK0_GPIO27_STATUS_IRQFROMPAD_ACCESS "RO" 4534 // ----------------------------------------------------------------------------- 4535 // Field : IO_BANK0_GPIO27_STATUS_INTOPERI 4536 // Description : input signal to peripheral, after override is applied 4537 #define IO_BANK0_GPIO27_STATUS_INTOPERI_RESET _u(0x0) 4538 #define IO_BANK0_GPIO27_STATUS_INTOPERI_BITS _u(0x00080000) 4539 #define IO_BANK0_GPIO27_STATUS_INTOPERI_MSB _u(19) 4540 #define IO_BANK0_GPIO27_STATUS_INTOPERI_LSB _u(19) 4541 #define IO_BANK0_GPIO27_STATUS_INTOPERI_ACCESS "RO" 4542 // ----------------------------------------------------------------------------- 4543 // Field : IO_BANK0_GPIO27_STATUS_INFROMPAD 4544 // Description : input signal from pad, before override is applied 4545 #define IO_BANK0_GPIO27_STATUS_INFROMPAD_RESET _u(0x0) 4546 #define IO_BANK0_GPIO27_STATUS_INFROMPAD_BITS _u(0x00020000) 4547 #define IO_BANK0_GPIO27_STATUS_INFROMPAD_MSB _u(17) 4548 #define IO_BANK0_GPIO27_STATUS_INFROMPAD_LSB _u(17) 4549 #define IO_BANK0_GPIO27_STATUS_INFROMPAD_ACCESS "RO" 4550 // ----------------------------------------------------------------------------- 4551 // Field : IO_BANK0_GPIO27_STATUS_OETOPAD 4552 // Description : output enable to pad after register override is applied 4553 #define IO_BANK0_GPIO27_STATUS_OETOPAD_RESET _u(0x0) 4554 #define IO_BANK0_GPIO27_STATUS_OETOPAD_BITS _u(0x00002000) 4555 #define IO_BANK0_GPIO27_STATUS_OETOPAD_MSB _u(13) 4556 #define IO_BANK0_GPIO27_STATUS_OETOPAD_LSB _u(13) 4557 #define IO_BANK0_GPIO27_STATUS_OETOPAD_ACCESS "RO" 4558 // ----------------------------------------------------------------------------- 4559 // Field : IO_BANK0_GPIO27_STATUS_OEFROMPERI 4560 // Description : output enable from selected peripheral, before register 4561 // override is applied 4562 #define IO_BANK0_GPIO27_STATUS_OEFROMPERI_RESET _u(0x0) 4563 #define IO_BANK0_GPIO27_STATUS_OEFROMPERI_BITS _u(0x00001000) 4564 #define IO_BANK0_GPIO27_STATUS_OEFROMPERI_MSB _u(12) 4565 #define IO_BANK0_GPIO27_STATUS_OEFROMPERI_LSB _u(12) 4566 #define IO_BANK0_GPIO27_STATUS_OEFROMPERI_ACCESS "RO" 4567 // ----------------------------------------------------------------------------- 4568 // Field : IO_BANK0_GPIO27_STATUS_OUTTOPAD 4569 // Description : output signal to pad after register override is applied 4570 #define IO_BANK0_GPIO27_STATUS_OUTTOPAD_RESET _u(0x0) 4571 #define IO_BANK0_GPIO27_STATUS_OUTTOPAD_BITS _u(0x00000200) 4572 #define IO_BANK0_GPIO27_STATUS_OUTTOPAD_MSB _u(9) 4573 #define IO_BANK0_GPIO27_STATUS_OUTTOPAD_LSB _u(9) 4574 #define IO_BANK0_GPIO27_STATUS_OUTTOPAD_ACCESS "RO" 4575 // ----------------------------------------------------------------------------- 4576 // Field : IO_BANK0_GPIO27_STATUS_OUTFROMPERI 4577 // Description : output signal from selected peripheral, before register 4578 // override is applied 4579 #define IO_BANK0_GPIO27_STATUS_OUTFROMPERI_RESET _u(0x0) 4580 #define IO_BANK0_GPIO27_STATUS_OUTFROMPERI_BITS _u(0x00000100) 4581 #define IO_BANK0_GPIO27_STATUS_OUTFROMPERI_MSB _u(8) 4582 #define IO_BANK0_GPIO27_STATUS_OUTFROMPERI_LSB _u(8) 4583 #define IO_BANK0_GPIO27_STATUS_OUTFROMPERI_ACCESS "RO" 4584 // ============================================================================= 4585 // Register : IO_BANK0_GPIO27_CTRL 4586 // Description : GPIO control including function select and overrides. 4587 #define IO_BANK0_GPIO27_CTRL_OFFSET _u(0x000000dc) 4588 #define IO_BANK0_GPIO27_CTRL_BITS _u(0x3003331f) 4589 #define IO_BANK0_GPIO27_CTRL_RESET _u(0x0000001f) 4590 // ----------------------------------------------------------------------------- 4591 // Field : IO_BANK0_GPIO27_CTRL_IRQOVER 4592 // 0x0 -> don't invert the interrupt 4593 // 0x1 -> invert the interrupt 4594 // 0x2 -> drive interrupt low 4595 // 0x3 -> drive interrupt high 4596 #define IO_BANK0_GPIO27_CTRL_IRQOVER_RESET _u(0x0) 4597 #define IO_BANK0_GPIO27_CTRL_IRQOVER_BITS _u(0x30000000) 4598 #define IO_BANK0_GPIO27_CTRL_IRQOVER_MSB _u(29) 4599 #define IO_BANK0_GPIO27_CTRL_IRQOVER_LSB _u(28) 4600 #define IO_BANK0_GPIO27_CTRL_IRQOVER_ACCESS "RW" 4601 #define IO_BANK0_GPIO27_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) 4602 #define IO_BANK0_GPIO27_CTRL_IRQOVER_VALUE_INVERT _u(0x1) 4603 #define IO_BANK0_GPIO27_CTRL_IRQOVER_VALUE_LOW _u(0x2) 4604 #define IO_BANK0_GPIO27_CTRL_IRQOVER_VALUE_HIGH _u(0x3) 4605 // ----------------------------------------------------------------------------- 4606 // Field : IO_BANK0_GPIO27_CTRL_INOVER 4607 // 0x0 -> don't invert the peri input 4608 // 0x1 -> invert the peri input 4609 // 0x2 -> drive peri input low 4610 // 0x3 -> drive peri input high 4611 #define IO_BANK0_GPIO27_CTRL_INOVER_RESET _u(0x0) 4612 #define IO_BANK0_GPIO27_CTRL_INOVER_BITS _u(0x00030000) 4613 #define IO_BANK0_GPIO27_CTRL_INOVER_MSB _u(17) 4614 #define IO_BANK0_GPIO27_CTRL_INOVER_LSB _u(16) 4615 #define IO_BANK0_GPIO27_CTRL_INOVER_ACCESS "RW" 4616 #define IO_BANK0_GPIO27_CTRL_INOVER_VALUE_NORMAL _u(0x0) 4617 #define IO_BANK0_GPIO27_CTRL_INOVER_VALUE_INVERT _u(0x1) 4618 #define IO_BANK0_GPIO27_CTRL_INOVER_VALUE_LOW _u(0x2) 4619 #define IO_BANK0_GPIO27_CTRL_INOVER_VALUE_HIGH _u(0x3) 4620 // ----------------------------------------------------------------------------- 4621 // Field : IO_BANK0_GPIO27_CTRL_OEOVER 4622 // 0x0 -> drive output enable from peripheral signal selected by funcsel 4623 // 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel 4624 // 0x2 -> disable output 4625 // 0x3 -> enable output 4626 #define IO_BANK0_GPIO27_CTRL_OEOVER_RESET _u(0x0) 4627 #define IO_BANK0_GPIO27_CTRL_OEOVER_BITS _u(0x00003000) 4628 #define IO_BANK0_GPIO27_CTRL_OEOVER_MSB _u(13) 4629 #define IO_BANK0_GPIO27_CTRL_OEOVER_LSB _u(12) 4630 #define IO_BANK0_GPIO27_CTRL_OEOVER_ACCESS "RW" 4631 #define IO_BANK0_GPIO27_CTRL_OEOVER_VALUE_NORMAL _u(0x0) 4632 #define IO_BANK0_GPIO27_CTRL_OEOVER_VALUE_INVERT _u(0x1) 4633 #define IO_BANK0_GPIO27_CTRL_OEOVER_VALUE_DISABLE _u(0x2) 4634 #define IO_BANK0_GPIO27_CTRL_OEOVER_VALUE_ENABLE _u(0x3) 4635 // ----------------------------------------------------------------------------- 4636 // Field : IO_BANK0_GPIO27_CTRL_OUTOVER 4637 // 0x0 -> drive output from peripheral signal selected by funcsel 4638 // 0x1 -> drive output from inverse of peripheral signal selected by funcsel 4639 // 0x2 -> drive output low 4640 // 0x3 -> drive output high 4641 #define IO_BANK0_GPIO27_CTRL_OUTOVER_RESET _u(0x0) 4642 #define IO_BANK0_GPIO27_CTRL_OUTOVER_BITS _u(0x00000300) 4643 #define IO_BANK0_GPIO27_CTRL_OUTOVER_MSB _u(9) 4644 #define IO_BANK0_GPIO27_CTRL_OUTOVER_LSB _u(8) 4645 #define IO_BANK0_GPIO27_CTRL_OUTOVER_ACCESS "RW" 4646 #define IO_BANK0_GPIO27_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) 4647 #define IO_BANK0_GPIO27_CTRL_OUTOVER_VALUE_INVERT _u(0x1) 4648 #define IO_BANK0_GPIO27_CTRL_OUTOVER_VALUE_LOW _u(0x2) 4649 #define IO_BANK0_GPIO27_CTRL_OUTOVER_VALUE_HIGH _u(0x3) 4650 // ----------------------------------------------------------------------------- 4651 // Field : IO_BANK0_GPIO27_CTRL_FUNCSEL 4652 // Description : 0-31 -> selects pin function according to the gpio table 4653 // 31 == NULL 4654 // 0x01 -> spi1_tx 4655 // 0x02 -> uart1_rts 4656 // 0x03 -> i2c1_scl 4657 // 0x04 -> pwm_b_5 4658 // 0x05 -> sio_27 4659 // 0x06 -> pio0_27 4660 // 0x07 -> pio1_27 4661 // 0x09 -> usb_muxing_overcurr_detect 4662 // 0x1f -> null 4663 #define IO_BANK0_GPIO27_CTRL_FUNCSEL_RESET _u(0x1f) 4664 #define IO_BANK0_GPIO27_CTRL_FUNCSEL_BITS _u(0x0000001f) 4665 #define IO_BANK0_GPIO27_CTRL_FUNCSEL_MSB _u(4) 4666 #define IO_BANK0_GPIO27_CTRL_FUNCSEL_LSB _u(0) 4667 #define IO_BANK0_GPIO27_CTRL_FUNCSEL_ACCESS "RW" 4668 #define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_SPI1_TX _u(0x01) 4669 #define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_UART1_RTS _u(0x02) 4670 #define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) 4671 #define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_PWM_B_5 _u(0x04) 4672 #define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_SIO_27 _u(0x05) 4673 #define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_PIO0_27 _u(0x06) 4674 #define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_PIO1_27 _u(0x07) 4675 #define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09) 4676 #define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) 4677 // ============================================================================= 4678 // Register : IO_BANK0_GPIO28_STATUS 4679 // Description : GPIO status 4680 #define IO_BANK0_GPIO28_STATUS_OFFSET _u(0x000000e0) 4681 #define IO_BANK0_GPIO28_STATUS_BITS _u(0x050a3300) 4682 #define IO_BANK0_GPIO28_STATUS_RESET _u(0x00000000) 4683 // ----------------------------------------------------------------------------- 4684 // Field : IO_BANK0_GPIO28_STATUS_IRQTOPROC 4685 // Description : interrupt to processors, after override is applied 4686 #define IO_BANK0_GPIO28_STATUS_IRQTOPROC_RESET _u(0x0) 4687 #define IO_BANK0_GPIO28_STATUS_IRQTOPROC_BITS _u(0x04000000) 4688 #define IO_BANK0_GPIO28_STATUS_IRQTOPROC_MSB _u(26) 4689 #define IO_BANK0_GPIO28_STATUS_IRQTOPROC_LSB _u(26) 4690 #define IO_BANK0_GPIO28_STATUS_IRQTOPROC_ACCESS "RO" 4691 // ----------------------------------------------------------------------------- 4692 // Field : IO_BANK0_GPIO28_STATUS_IRQFROMPAD 4693 // Description : interrupt from pad before override is applied 4694 #define IO_BANK0_GPIO28_STATUS_IRQFROMPAD_RESET _u(0x0) 4695 #define IO_BANK0_GPIO28_STATUS_IRQFROMPAD_BITS _u(0x01000000) 4696 #define IO_BANK0_GPIO28_STATUS_IRQFROMPAD_MSB _u(24) 4697 #define IO_BANK0_GPIO28_STATUS_IRQFROMPAD_LSB _u(24) 4698 #define IO_BANK0_GPIO28_STATUS_IRQFROMPAD_ACCESS "RO" 4699 // ----------------------------------------------------------------------------- 4700 // Field : IO_BANK0_GPIO28_STATUS_INTOPERI 4701 // Description : input signal to peripheral, after override is applied 4702 #define IO_BANK0_GPIO28_STATUS_INTOPERI_RESET _u(0x0) 4703 #define IO_BANK0_GPIO28_STATUS_INTOPERI_BITS _u(0x00080000) 4704 #define IO_BANK0_GPIO28_STATUS_INTOPERI_MSB _u(19) 4705 #define IO_BANK0_GPIO28_STATUS_INTOPERI_LSB _u(19) 4706 #define IO_BANK0_GPIO28_STATUS_INTOPERI_ACCESS "RO" 4707 // ----------------------------------------------------------------------------- 4708 // Field : IO_BANK0_GPIO28_STATUS_INFROMPAD 4709 // Description : input signal from pad, before override is applied 4710 #define IO_BANK0_GPIO28_STATUS_INFROMPAD_RESET _u(0x0) 4711 #define IO_BANK0_GPIO28_STATUS_INFROMPAD_BITS _u(0x00020000) 4712 #define IO_BANK0_GPIO28_STATUS_INFROMPAD_MSB _u(17) 4713 #define IO_BANK0_GPIO28_STATUS_INFROMPAD_LSB _u(17) 4714 #define IO_BANK0_GPIO28_STATUS_INFROMPAD_ACCESS "RO" 4715 // ----------------------------------------------------------------------------- 4716 // Field : IO_BANK0_GPIO28_STATUS_OETOPAD 4717 // Description : output enable to pad after register override is applied 4718 #define IO_BANK0_GPIO28_STATUS_OETOPAD_RESET _u(0x0) 4719 #define IO_BANK0_GPIO28_STATUS_OETOPAD_BITS _u(0x00002000) 4720 #define IO_BANK0_GPIO28_STATUS_OETOPAD_MSB _u(13) 4721 #define IO_BANK0_GPIO28_STATUS_OETOPAD_LSB _u(13) 4722 #define IO_BANK0_GPIO28_STATUS_OETOPAD_ACCESS "RO" 4723 // ----------------------------------------------------------------------------- 4724 // Field : IO_BANK0_GPIO28_STATUS_OEFROMPERI 4725 // Description : output enable from selected peripheral, before register 4726 // override is applied 4727 #define IO_BANK0_GPIO28_STATUS_OEFROMPERI_RESET _u(0x0) 4728 #define IO_BANK0_GPIO28_STATUS_OEFROMPERI_BITS _u(0x00001000) 4729 #define IO_BANK0_GPIO28_STATUS_OEFROMPERI_MSB _u(12) 4730 #define IO_BANK0_GPIO28_STATUS_OEFROMPERI_LSB _u(12) 4731 #define IO_BANK0_GPIO28_STATUS_OEFROMPERI_ACCESS "RO" 4732 // ----------------------------------------------------------------------------- 4733 // Field : IO_BANK0_GPIO28_STATUS_OUTTOPAD 4734 // Description : output signal to pad after register override is applied 4735 #define IO_BANK0_GPIO28_STATUS_OUTTOPAD_RESET _u(0x0) 4736 #define IO_BANK0_GPIO28_STATUS_OUTTOPAD_BITS _u(0x00000200) 4737 #define IO_BANK0_GPIO28_STATUS_OUTTOPAD_MSB _u(9) 4738 #define IO_BANK0_GPIO28_STATUS_OUTTOPAD_LSB _u(9) 4739 #define IO_BANK0_GPIO28_STATUS_OUTTOPAD_ACCESS "RO" 4740 // ----------------------------------------------------------------------------- 4741 // Field : IO_BANK0_GPIO28_STATUS_OUTFROMPERI 4742 // Description : output signal from selected peripheral, before register 4743 // override is applied 4744 #define IO_BANK0_GPIO28_STATUS_OUTFROMPERI_RESET _u(0x0) 4745 #define IO_BANK0_GPIO28_STATUS_OUTFROMPERI_BITS _u(0x00000100) 4746 #define IO_BANK0_GPIO28_STATUS_OUTFROMPERI_MSB _u(8) 4747 #define IO_BANK0_GPIO28_STATUS_OUTFROMPERI_LSB _u(8) 4748 #define IO_BANK0_GPIO28_STATUS_OUTFROMPERI_ACCESS "RO" 4749 // ============================================================================= 4750 // Register : IO_BANK0_GPIO28_CTRL 4751 // Description : GPIO control including function select and overrides. 4752 #define IO_BANK0_GPIO28_CTRL_OFFSET _u(0x000000e4) 4753 #define IO_BANK0_GPIO28_CTRL_BITS _u(0x3003331f) 4754 #define IO_BANK0_GPIO28_CTRL_RESET _u(0x0000001f) 4755 // ----------------------------------------------------------------------------- 4756 // Field : IO_BANK0_GPIO28_CTRL_IRQOVER 4757 // 0x0 -> don't invert the interrupt 4758 // 0x1 -> invert the interrupt 4759 // 0x2 -> drive interrupt low 4760 // 0x3 -> drive interrupt high 4761 #define IO_BANK0_GPIO28_CTRL_IRQOVER_RESET _u(0x0) 4762 #define IO_BANK0_GPIO28_CTRL_IRQOVER_BITS _u(0x30000000) 4763 #define IO_BANK0_GPIO28_CTRL_IRQOVER_MSB _u(29) 4764 #define IO_BANK0_GPIO28_CTRL_IRQOVER_LSB _u(28) 4765 #define IO_BANK0_GPIO28_CTRL_IRQOVER_ACCESS "RW" 4766 #define IO_BANK0_GPIO28_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) 4767 #define IO_BANK0_GPIO28_CTRL_IRQOVER_VALUE_INVERT _u(0x1) 4768 #define IO_BANK0_GPIO28_CTRL_IRQOVER_VALUE_LOW _u(0x2) 4769 #define IO_BANK0_GPIO28_CTRL_IRQOVER_VALUE_HIGH _u(0x3) 4770 // ----------------------------------------------------------------------------- 4771 // Field : IO_BANK0_GPIO28_CTRL_INOVER 4772 // 0x0 -> don't invert the peri input 4773 // 0x1 -> invert the peri input 4774 // 0x2 -> drive peri input low 4775 // 0x3 -> drive peri input high 4776 #define IO_BANK0_GPIO28_CTRL_INOVER_RESET _u(0x0) 4777 #define IO_BANK0_GPIO28_CTRL_INOVER_BITS _u(0x00030000) 4778 #define IO_BANK0_GPIO28_CTRL_INOVER_MSB _u(17) 4779 #define IO_BANK0_GPIO28_CTRL_INOVER_LSB _u(16) 4780 #define IO_BANK0_GPIO28_CTRL_INOVER_ACCESS "RW" 4781 #define IO_BANK0_GPIO28_CTRL_INOVER_VALUE_NORMAL _u(0x0) 4782 #define IO_BANK0_GPIO28_CTRL_INOVER_VALUE_INVERT _u(0x1) 4783 #define IO_BANK0_GPIO28_CTRL_INOVER_VALUE_LOW _u(0x2) 4784 #define IO_BANK0_GPIO28_CTRL_INOVER_VALUE_HIGH _u(0x3) 4785 // ----------------------------------------------------------------------------- 4786 // Field : IO_BANK0_GPIO28_CTRL_OEOVER 4787 // 0x0 -> drive output enable from peripheral signal selected by funcsel 4788 // 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel 4789 // 0x2 -> disable output 4790 // 0x3 -> enable output 4791 #define IO_BANK0_GPIO28_CTRL_OEOVER_RESET _u(0x0) 4792 #define IO_BANK0_GPIO28_CTRL_OEOVER_BITS _u(0x00003000) 4793 #define IO_BANK0_GPIO28_CTRL_OEOVER_MSB _u(13) 4794 #define IO_BANK0_GPIO28_CTRL_OEOVER_LSB _u(12) 4795 #define IO_BANK0_GPIO28_CTRL_OEOVER_ACCESS "RW" 4796 #define IO_BANK0_GPIO28_CTRL_OEOVER_VALUE_NORMAL _u(0x0) 4797 #define IO_BANK0_GPIO28_CTRL_OEOVER_VALUE_INVERT _u(0x1) 4798 #define IO_BANK0_GPIO28_CTRL_OEOVER_VALUE_DISABLE _u(0x2) 4799 #define IO_BANK0_GPIO28_CTRL_OEOVER_VALUE_ENABLE _u(0x3) 4800 // ----------------------------------------------------------------------------- 4801 // Field : IO_BANK0_GPIO28_CTRL_OUTOVER 4802 // 0x0 -> drive output from peripheral signal selected by funcsel 4803 // 0x1 -> drive output from inverse of peripheral signal selected by funcsel 4804 // 0x2 -> drive output low 4805 // 0x3 -> drive output high 4806 #define IO_BANK0_GPIO28_CTRL_OUTOVER_RESET _u(0x0) 4807 #define IO_BANK0_GPIO28_CTRL_OUTOVER_BITS _u(0x00000300) 4808 #define IO_BANK0_GPIO28_CTRL_OUTOVER_MSB _u(9) 4809 #define IO_BANK0_GPIO28_CTRL_OUTOVER_LSB _u(8) 4810 #define IO_BANK0_GPIO28_CTRL_OUTOVER_ACCESS "RW" 4811 #define IO_BANK0_GPIO28_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) 4812 #define IO_BANK0_GPIO28_CTRL_OUTOVER_VALUE_INVERT _u(0x1) 4813 #define IO_BANK0_GPIO28_CTRL_OUTOVER_VALUE_LOW _u(0x2) 4814 #define IO_BANK0_GPIO28_CTRL_OUTOVER_VALUE_HIGH _u(0x3) 4815 // ----------------------------------------------------------------------------- 4816 // Field : IO_BANK0_GPIO28_CTRL_FUNCSEL 4817 // Description : 0-31 -> selects pin function according to the gpio table 4818 // 31 == NULL 4819 // 0x01 -> spi1_rx 4820 // 0x02 -> uart0_tx 4821 // 0x03 -> i2c0_sda 4822 // 0x04 -> pwm_a_6 4823 // 0x05 -> sio_28 4824 // 0x06 -> pio0_28 4825 // 0x07 -> pio1_28 4826 // 0x09 -> usb_muxing_vbus_detect 4827 // 0x1f -> null 4828 #define IO_BANK0_GPIO28_CTRL_FUNCSEL_RESET _u(0x1f) 4829 #define IO_BANK0_GPIO28_CTRL_FUNCSEL_BITS _u(0x0000001f) 4830 #define IO_BANK0_GPIO28_CTRL_FUNCSEL_MSB _u(4) 4831 #define IO_BANK0_GPIO28_CTRL_FUNCSEL_LSB _u(0) 4832 #define IO_BANK0_GPIO28_CTRL_FUNCSEL_ACCESS "RW" 4833 #define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_SPI1_RX _u(0x01) 4834 #define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x02) 4835 #define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) 4836 #define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_PWM_A_6 _u(0x04) 4837 #define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_SIO_28 _u(0x05) 4838 #define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_PIO0_28 _u(0x06) 4839 #define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_PIO1_28 _u(0x07) 4840 #define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09) 4841 #define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) 4842 // ============================================================================= 4843 // Register : IO_BANK0_GPIO29_STATUS 4844 // Description : GPIO status 4845 #define IO_BANK0_GPIO29_STATUS_OFFSET _u(0x000000e8) 4846 #define IO_BANK0_GPIO29_STATUS_BITS _u(0x050a3300) 4847 #define IO_BANK0_GPIO29_STATUS_RESET _u(0x00000000) 4848 // ----------------------------------------------------------------------------- 4849 // Field : IO_BANK0_GPIO29_STATUS_IRQTOPROC 4850 // Description : interrupt to processors, after override is applied 4851 #define IO_BANK0_GPIO29_STATUS_IRQTOPROC_RESET _u(0x0) 4852 #define IO_BANK0_GPIO29_STATUS_IRQTOPROC_BITS _u(0x04000000) 4853 #define IO_BANK0_GPIO29_STATUS_IRQTOPROC_MSB _u(26) 4854 #define IO_BANK0_GPIO29_STATUS_IRQTOPROC_LSB _u(26) 4855 #define IO_BANK0_GPIO29_STATUS_IRQTOPROC_ACCESS "RO" 4856 // ----------------------------------------------------------------------------- 4857 // Field : IO_BANK0_GPIO29_STATUS_IRQFROMPAD 4858 // Description : interrupt from pad before override is applied 4859 #define IO_BANK0_GPIO29_STATUS_IRQFROMPAD_RESET _u(0x0) 4860 #define IO_BANK0_GPIO29_STATUS_IRQFROMPAD_BITS _u(0x01000000) 4861 #define IO_BANK0_GPIO29_STATUS_IRQFROMPAD_MSB _u(24) 4862 #define IO_BANK0_GPIO29_STATUS_IRQFROMPAD_LSB _u(24) 4863 #define IO_BANK0_GPIO29_STATUS_IRQFROMPAD_ACCESS "RO" 4864 // ----------------------------------------------------------------------------- 4865 // Field : IO_BANK0_GPIO29_STATUS_INTOPERI 4866 // Description : input signal to peripheral, after override is applied 4867 #define IO_BANK0_GPIO29_STATUS_INTOPERI_RESET _u(0x0) 4868 #define IO_BANK0_GPIO29_STATUS_INTOPERI_BITS _u(0x00080000) 4869 #define IO_BANK0_GPIO29_STATUS_INTOPERI_MSB _u(19) 4870 #define IO_BANK0_GPIO29_STATUS_INTOPERI_LSB _u(19) 4871 #define IO_BANK0_GPIO29_STATUS_INTOPERI_ACCESS "RO" 4872 // ----------------------------------------------------------------------------- 4873 // Field : IO_BANK0_GPIO29_STATUS_INFROMPAD 4874 // Description : input signal from pad, before override is applied 4875 #define IO_BANK0_GPIO29_STATUS_INFROMPAD_RESET _u(0x0) 4876 #define IO_BANK0_GPIO29_STATUS_INFROMPAD_BITS _u(0x00020000) 4877 #define IO_BANK0_GPIO29_STATUS_INFROMPAD_MSB _u(17) 4878 #define IO_BANK0_GPIO29_STATUS_INFROMPAD_LSB _u(17) 4879 #define IO_BANK0_GPIO29_STATUS_INFROMPAD_ACCESS "RO" 4880 // ----------------------------------------------------------------------------- 4881 // Field : IO_BANK0_GPIO29_STATUS_OETOPAD 4882 // Description : output enable to pad after register override is applied 4883 #define IO_BANK0_GPIO29_STATUS_OETOPAD_RESET _u(0x0) 4884 #define IO_BANK0_GPIO29_STATUS_OETOPAD_BITS _u(0x00002000) 4885 #define IO_BANK0_GPIO29_STATUS_OETOPAD_MSB _u(13) 4886 #define IO_BANK0_GPIO29_STATUS_OETOPAD_LSB _u(13) 4887 #define IO_BANK0_GPIO29_STATUS_OETOPAD_ACCESS "RO" 4888 // ----------------------------------------------------------------------------- 4889 // Field : IO_BANK0_GPIO29_STATUS_OEFROMPERI 4890 // Description : output enable from selected peripheral, before register 4891 // override is applied 4892 #define IO_BANK0_GPIO29_STATUS_OEFROMPERI_RESET _u(0x0) 4893 #define IO_BANK0_GPIO29_STATUS_OEFROMPERI_BITS _u(0x00001000) 4894 #define IO_BANK0_GPIO29_STATUS_OEFROMPERI_MSB _u(12) 4895 #define IO_BANK0_GPIO29_STATUS_OEFROMPERI_LSB _u(12) 4896 #define IO_BANK0_GPIO29_STATUS_OEFROMPERI_ACCESS "RO" 4897 // ----------------------------------------------------------------------------- 4898 // Field : IO_BANK0_GPIO29_STATUS_OUTTOPAD 4899 // Description : output signal to pad after register override is applied 4900 #define IO_BANK0_GPIO29_STATUS_OUTTOPAD_RESET _u(0x0) 4901 #define IO_BANK0_GPIO29_STATUS_OUTTOPAD_BITS _u(0x00000200) 4902 #define IO_BANK0_GPIO29_STATUS_OUTTOPAD_MSB _u(9) 4903 #define IO_BANK0_GPIO29_STATUS_OUTTOPAD_LSB _u(9) 4904 #define IO_BANK0_GPIO29_STATUS_OUTTOPAD_ACCESS "RO" 4905 // ----------------------------------------------------------------------------- 4906 // Field : IO_BANK0_GPIO29_STATUS_OUTFROMPERI 4907 // Description : output signal from selected peripheral, before register 4908 // override is applied 4909 #define IO_BANK0_GPIO29_STATUS_OUTFROMPERI_RESET _u(0x0) 4910 #define IO_BANK0_GPIO29_STATUS_OUTFROMPERI_BITS _u(0x00000100) 4911 #define IO_BANK0_GPIO29_STATUS_OUTFROMPERI_MSB _u(8) 4912 #define IO_BANK0_GPIO29_STATUS_OUTFROMPERI_LSB _u(8) 4913 #define IO_BANK0_GPIO29_STATUS_OUTFROMPERI_ACCESS "RO" 4914 // ============================================================================= 4915 // Register : IO_BANK0_GPIO29_CTRL 4916 // Description : GPIO control including function select and overrides. 4917 #define IO_BANK0_GPIO29_CTRL_OFFSET _u(0x000000ec) 4918 #define IO_BANK0_GPIO29_CTRL_BITS _u(0x3003331f) 4919 #define IO_BANK0_GPIO29_CTRL_RESET _u(0x0000001f) 4920 // ----------------------------------------------------------------------------- 4921 // Field : IO_BANK0_GPIO29_CTRL_IRQOVER 4922 // 0x0 -> don't invert the interrupt 4923 // 0x1 -> invert the interrupt 4924 // 0x2 -> drive interrupt low 4925 // 0x3 -> drive interrupt high 4926 #define IO_BANK0_GPIO29_CTRL_IRQOVER_RESET _u(0x0) 4927 #define IO_BANK0_GPIO29_CTRL_IRQOVER_BITS _u(0x30000000) 4928 #define IO_BANK0_GPIO29_CTRL_IRQOVER_MSB _u(29) 4929 #define IO_BANK0_GPIO29_CTRL_IRQOVER_LSB _u(28) 4930 #define IO_BANK0_GPIO29_CTRL_IRQOVER_ACCESS "RW" 4931 #define IO_BANK0_GPIO29_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) 4932 #define IO_BANK0_GPIO29_CTRL_IRQOVER_VALUE_INVERT _u(0x1) 4933 #define IO_BANK0_GPIO29_CTRL_IRQOVER_VALUE_LOW _u(0x2) 4934 #define IO_BANK0_GPIO29_CTRL_IRQOVER_VALUE_HIGH _u(0x3) 4935 // ----------------------------------------------------------------------------- 4936 // Field : IO_BANK0_GPIO29_CTRL_INOVER 4937 // 0x0 -> don't invert the peri input 4938 // 0x1 -> invert the peri input 4939 // 0x2 -> drive peri input low 4940 // 0x3 -> drive peri input high 4941 #define IO_BANK0_GPIO29_CTRL_INOVER_RESET _u(0x0) 4942 #define IO_BANK0_GPIO29_CTRL_INOVER_BITS _u(0x00030000) 4943 #define IO_BANK0_GPIO29_CTRL_INOVER_MSB _u(17) 4944 #define IO_BANK0_GPIO29_CTRL_INOVER_LSB _u(16) 4945 #define IO_BANK0_GPIO29_CTRL_INOVER_ACCESS "RW" 4946 #define IO_BANK0_GPIO29_CTRL_INOVER_VALUE_NORMAL _u(0x0) 4947 #define IO_BANK0_GPIO29_CTRL_INOVER_VALUE_INVERT _u(0x1) 4948 #define IO_BANK0_GPIO29_CTRL_INOVER_VALUE_LOW _u(0x2) 4949 #define IO_BANK0_GPIO29_CTRL_INOVER_VALUE_HIGH _u(0x3) 4950 // ----------------------------------------------------------------------------- 4951 // Field : IO_BANK0_GPIO29_CTRL_OEOVER 4952 // 0x0 -> drive output enable from peripheral signal selected by funcsel 4953 // 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel 4954 // 0x2 -> disable output 4955 // 0x3 -> enable output 4956 #define IO_BANK0_GPIO29_CTRL_OEOVER_RESET _u(0x0) 4957 #define IO_BANK0_GPIO29_CTRL_OEOVER_BITS _u(0x00003000) 4958 #define IO_BANK0_GPIO29_CTRL_OEOVER_MSB _u(13) 4959 #define IO_BANK0_GPIO29_CTRL_OEOVER_LSB _u(12) 4960 #define IO_BANK0_GPIO29_CTRL_OEOVER_ACCESS "RW" 4961 #define IO_BANK0_GPIO29_CTRL_OEOVER_VALUE_NORMAL _u(0x0) 4962 #define IO_BANK0_GPIO29_CTRL_OEOVER_VALUE_INVERT _u(0x1) 4963 #define IO_BANK0_GPIO29_CTRL_OEOVER_VALUE_DISABLE _u(0x2) 4964 #define IO_BANK0_GPIO29_CTRL_OEOVER_VALUE_ENABLE _u(0x3) 4965 // ----------------------------------------------------------------------------- 4966 // Field : IO_BANK0_GPIO29_CTRL_OUTOVER 4967 // 0x0 -> drive output from peripheral signal selected by funcsel 4968 // 0x1 -> drive output from inverse of peripheral signal selected by funcsel 4969 // 0x2 -> drive output low 4970 // 0x3 -> drive output high 4971 #define IO_BANK0_GPIO29_CTRL_OUTOVER_RESET _u(0x0) 4972 #define IO_BANK0_GPIO29_CTRL_OUTOVER_BITS _u(0x00000300) 4973 #define IO_BANK0_GPIO29_CTRL_OUTOVER_MSB _u(9) 4974 #define IO_BANK0_GPIO29_CTRL_OUTOVER_LSB _u(8) 4975 #define IO_BANK0_GPIO29_CTRL_OUTOVER_ACCESS "RW" 4976 #define IO_BANK0_GPIO29_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) 4977 #define IO_BANK0_GPIO29_CTRL_OUTOVER_VALUE_INVERT _u(0x1) 4978 #define IO_BANK0_GPIO29_CTRL_OUTOVER_VALUE_LOW _u(0x2) 4979 #define IO_BANK0_GPIO29_CTRL_OUTOVER_VALUE_HIGH _u(0x3) 4980 // ----------------------------------------------------------------------------- 4981 // Field : IO_BANK0_GPIO29_CTRL_FUNCSEL 4982 // Description : 0-31 -> selects pin function according to the gpio table 4983 // 31 == NULL 4984 // 0x01 -> spi1_ss_n 4985 // 0x02 -> uart0_rx 4986 // 0x03 -> i2c0_scl 4987 // 0x04 -> pwm_b_6 4988 // 0x05 -> sio_29 4989 // 0x06 -> pio0_29 4990 // 0x07 -> pio1_29 4991 // 0x09 -> usb_muxing_vbus_en 4992 // 0x1f -> null 4993 #define IO_BANK0_GPIO29_CTRL_FUNCSEL_RESET _u(0x1f) 4994 #define IO_BANK0_GPIO29_CTRL_FUNCSEL_BITS _u(0x0000001f) 4995 #define IO_BANK0_GPIO29_CTRL_FUNCSEL_MSB _u(4) 4996 #define IO_BANK0_GPIO29_CTRL_FUNCSEL_LSB _u(0) 4997 #define IO_BANK0_GPIO29_CTRL_FUNCSEL_ACCESS "RW" 4998 #define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_SPI1_SS_N _u(0x01) 4999 #define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x02) 5000 #define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) 5001 #define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_PWM_B_6 _u(0x04) 5002 #define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_SIO_29 _u(0x05) 5003 #define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_PIO0_29 _u(0x06) 5004 #define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_PIO1_29 _u(0x07) 5005 #define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09) 5006 #define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) 5007 // ============================================================================= 5008 // Register : IO_BANK0_INTR0 5009 // Description : Raw Interrupts 5010 #define IO_BANK0_INTR0_OFFSET _u(0x000000f0) 5011 #define IO_BANK0_INTR0_BITS _u(0xffffffff) 5012 #define IO_BANK0_INTR0_RESET _u(0x00000000) 5013 // ----------------------------------------------------------------------------- 5014 // Field : IO_BANK0_INTR0_GPIO7_EDGE_HIGH 5015 #define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_RESET _u(0x0) 5016 #define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) 5017 #define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_MSB _u(31) 5018 #define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_LSB _u(31) 5019 #define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_ACCESS "WC" 5020 // ----------------------------------------------------------------------------- 5021 // Field : IO_BANK0_INTR0_GPIO7_EDGE_LOW 5022 #define IO_BANK0_INTR0_GPIO7_EDGE_LOW_RESET _u(0x0) 5023 #define IO_BANK0_INTR0_GPIO7_EDGE_LOW_BITS _u(0x40000000) 5024 #define IO_BANK0_INTR0_GPIO7_EDGE_LOW_MSB _u(30) 5025 #define IO_BANK0_INTR0_GPIO7_EDGE_LOW_LSB _u(30) 5026 #define IO_BANK0_INTR0_GPIO7_EDGE_LOW_ACCESS "WC" 5027 // ----------------------------------------------------------------------------- 5028 // Field : IO_BANK0_INTR0_GPIO7_LEVEL_HIGH 5029 #define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_RESET _u(0x0) 5030 #define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) 5031 #define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_MSB _u(29) 5032 #define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_LSB _u(29) 5033 #define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_ACCESS "RO" 5034 // ----------------------------------------------------------------------------- 5035 // Field : IO_BANK0_INTR0_GPIO7_LEVEL_LOW 5036 #define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_RESET _u(0x0) 5037 #define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) 5038 #define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_MSB _u(28) 5039 #define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_LSB _u(28) 5040 #define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_ACCESS "RO" 5041 // ----------------------------------------------------------------------------- 5042 // Field : IO_BANK0_INTR0_GPIO6_EDGE_HIGH 5043 #define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_RESET _u(0x0) 5044 #define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) 5045 #define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_MSB _u(27) 5046 #define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_LSB _u(27) 5047 #define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_ACCESS "WC" 5048 // ----------------------------------------------------------------------------- 5049 // Field : IO_BANK0_INTR0_GPIO6_EDGE_LOW 5050 #define IO_BANK0_INTR0_GPIO6_EDGE_LOW_RESET _u(0x0) 5051 #define IO_BANK0_INTR0_GPIO6_EDGE_LOW_BITS _u(0x04000000) 5052 #define IO_BANK0_INTR0_GPIO6_EDGE_LOW_MSB _u(26) 5053 #define IO_BANK0_INTR0_GPIO6_EDGE_LOW_LSB _u(26) 5054 #define IO_BANK0_INTR0_GPIO6_EDGE_LOW_ACCESS "WC" 5055 // ----------------------------------------------------------------------------- 5056 // Field : IO_BANK0_INTR0_GPIO6_LEVEL_HIGH 5057 #define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_RESET _u(0x0) 5058 #define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) 5059 #define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_MSB _u(25) 5060 #define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_LSB _u(25) 5061 #define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_ACCESS "RO" 5062 // ----------------------------------------------------------------------------- 5063 // Field : IO_BANK0_INTR0_GPIO6_LEVEL_LOW 5064 #define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_RESET _u(0x0) 5065 #define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) 5066 #define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_MSB _u(24) 5067 #define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_LSB _u(24) 5068 #define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_ACCESS "RO" 5069 // ----------------------------------------------------------------------------- 5070 // Field : IO_BANK0_INTR0_GPIO5_EDGE_HIGH 5071 #define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_RESET _u(0x0) 5072 #define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) 5073 #define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_MSB _u(23) 5074 #define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_LSB _u(23) 5075 #define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_ACCESS "WC" 5076 // ----------------------------------------------------------------------------- 5077 // Field : IO_BANK0_INTR0_GPIO5_EDGE_LOW 5078 #define IO_BANK0_INTR0_GPIO5_EDGE_LOW_RESET _u(0x0) 5079 #define IO_BANK0_INTR0_GPIO5_EDGE_LOW_BITS _u(0x00400000) 5080 #define IO_BANK0_INTR0_GPIO5_EDGE_LOW_MSB _u(22) 5081 #define IO_BANK0_INTR0_GPIO5_EDGE_LOW_LSB _u(22) 5082 #define IO_BANK0_INTR0_GPIO5_EDGE_LOW_ACCESS "WC" 5083 // ----------------------------------------------------------------------------- 5084 // Field : IO_BANK0_INTR0_GPIO5_LEVEL_HIGH 5085 #define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_RESET _u(0x0) 5086 #define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) 5087 #define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_MSB _u(21) 5088 #define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_LSB _u(21) 5089 #define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_ACCESS "RO" 5090 // ----------------------------------------------------------------------------- 5091 // Field : IO_BANK0_INTR0_GPIO5_LEVEL_LOW 5092 #define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_RESET _u(0x0) 5093 #define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) 5094 #define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_MSB _u(20) 5095 #define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_LSB _u(20) 5096 #define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_ACCESS "RO" 5097 // ----------------------------------------------------------------------------- 5098 // Field : IO_BANK0_INTR0_GPIO4_EDGE_HIGH 5099 #define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_RESET _u(0x0) 5100 #define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) 5101 #define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_MSB _u(19) 5102 #define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_LSB _u(19) 5103 #define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_ACCESS "WC" 5104 // ----------------------------------------------------------------------------- 5105 // Field : IO_BANK0_INTR0_GPIO4_EDGE_LOW 5106 #define IO_BANK0_INTR0_GPIO4_EDGE_LOW_RESET _u(0x0) 5107 #define IO_BANK0_INTR0_GPIO4_EDGE_LOW_BITS _u(0x00040000) 5108 #define IO_BANK0_INTR0_GPIO4_EDGE_LOW_MSB _u(18) 5109 #define IO_BANK0_INTR0_GPIO4_EDGE_LOW_LSB _u(18) 5110 #define IO_BANK0_INTR0_GPIO4_EDGE_LOW_ACCESS "WC" 5111 // ----------------------------------------------------------------------------- 5112 // Field : IO_BANK0_INTR0_GPIO4_LEVEL_HIGH 5113 #define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_RESET _u(0x0) 5114 #define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) 5115 #define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_MSB _u(17) 5116 #define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_LSB _u(17) 5117 #define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_ACCESS "RO" 5118 // ----------------------------------------------------------------------------- 5119 // Field : IO_BANK0_INTR0_GPIO4_LEVEL_LOW 5120 #define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_RESET _u(0x0) 5121 #define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) 5122 #define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_MSB _u(16) 5123 #define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_LSB _u(16) 5124 #define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_ACCESS "RO" 5125 // ----------------------------------------------------------------------------- 5126 // Field : IO_BANK0_INTR0_GPIO3_EDGE_HIGH 5127 #define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_RESET _u(0x0) 5128 #define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) 5129 #define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_MSB _u(15) 5130 #define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_LSB _u(15) 5131 #define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_ACCESS "WC" 5132 // ----------------------------------------------------------------------------- 5133 // Field : IO_BANK0_INTR0_GPIO3_EDGE_LOW 5134 #define IO_BANK0_INTR0_GPIO3_EDGE_LOW_RESET _u(0x0) 5135 #define IO_BANK0_INTR0_GPIO3_EDGE_LOW_BITS _u(0x00004000) 5136 #define IO_BANK0_INTR0_GPIO3_EDGE_LOW_MSB _u(14) 5137 #define IO_BANK0_INTR0_GPIO3_EDGE_LOW_LSB _u(14) 5138 #define IO_BANK0_INTR0_GPIO3_EDGE_LOW_ACCESS "WC" 5139 // ----------------------------------------------------------------------------- 5140 // Field : IO_BANK0_INTR0_GPIO3_LEVEL_HIGH 5141 #define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_RESET _u(0x0) 5142 #define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) 5143 #define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_MSB _u(13) 5144 #define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_LSB _u(13) 5145 #define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_ACCESS "RO" 5146 // ----------------------------------------------------------------------------- 5147 // Field : IO_BANK0_INTR0_GPIO3_LEVEL_LOW 5148 #define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_RESET _u(0x0) 5149 #define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) 5150 #define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_MSB _u(12) 5151 #define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_LSB _u(12) 5152 #define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_ACCESS "RO" 5153 // ----------------------------------------------------------------------------- 5154 // Field : IO_BANK0_INTR0_GPIO2_EDGE_HIGH 5155 #define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_RESET _u(0x0) 5156 #define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) 5157 #define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_MSB _u(11) 5158 #define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_LSB _u(11) 5159 #define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_ACCESS "WC" 5160 // ----------------------------------------------------------------------------- 5161 // Field : IO_BANK0_INTR0_GPIO2_EDGE_LOW 5162 #define IO_BANK0_INTR0_GPIO2_EDGE_LOW_RESET _u(0x0) 5163 #define IO_BANK0_INTR0_GPIO2_EDGE_LOW_BITS _u(0x00000400) 5164 #define IO_BANK0_INTR0_GPIO2_EDGE_LOW_MSB _u(10) 5165 #define IO_BANK0_INTR0_GPIO2_EDGE_LOW_LSB _u(10) 5166 #define IO_BANK0_INTR0_GPIO2_EDGE_LOW_ACCESS "WC" 5167 // ----------------------------------------------------------------------------- 5168 // Field : IO_BANK0_INTR0_GPIO2_LEVEL_HIGH 5169 #define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_RESET _u(0x0) 5170 #define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) 5171 #define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_MSB _u(9) 5172 #define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_LSB _u(9) 5173 #define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_ACCESS "RO" 5174 // ----------------------------------------------------------------------------- 5175 // Field : IO_BANK0_INTR0_GPIO2_LEVEL_LOW 5176 #define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_RESET _u(0x0) 5177 #define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) 5178 #define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_MSB _u(8) 5179 #define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_LSB _u(8) 5180 #define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_ACCESS "RO" 5181 // ----------------------------------------------------------------------------- 5182 // Field : IO_BANK0_INTR0_GPIO1_EDGE_HIGH 5183 #define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_RESET _u(0x0) 5184 #define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) 5185 #define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_MSB _u(7) 5186 #define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_LSB _u(7) 5187 #define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_ACCESS "WC" 5188 // ----------------------------------------------------------------------------- 5189 // Field : IO_BANK0_INTR0_GPIO1_EDGE_LOW 5190 #define IO_BANK0_INTR0_GPIO1_EDGE_LOW_RESET _u(0x0) 5191 #define IO_BANK0_INTR0_GPIO1_EDGE_LOW_BITS _u(0x00000040) 5192 #define IO_BANK0_INTR0_GPIO1_EDGE_LOW_MSB _u(6) 5193 #define IO_BANK0_INTR0_GPIO1_EDGE_LOW_LSB _u(6) 5194 #define IO_BANK0_INTR0_GPIO1_EDGE_LOW_ACCESS "WC" 5195 // ----------------------------------------------------------------------------- 5196 // Field : IO_BANK0_INTR0_GPIO1_LEVEL_HIGH 5197 #define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_RESET _u(0x0) 5198 #define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) 5199 #define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_MSB _u(5) 5200 #define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_LSB _u(5) 5201 #define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_ACCESS "RO" 5202 // ----------------------------------------------------------------------------- 5203 // Field : IO_BANK0_INTR0_GPIO1_LEVEL_LOW 5204 #define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_RESET _u(0x0) 5205 #define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) 5206 #define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_MSB _u(4) 5207 #define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_LSB _u(4) 5208 #define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_ACCESS "RO" 5209 // ----------------------------------------------------------------------------- 5210 // Field : IO_BANK0_INTR0_GPIO0_EDGE_HIGH 5211 #define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_RESET _u(0x0) 5212 #define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) 5213 #define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_MSB _u(3) 5214 #define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_LSB _u(3) 5215 #define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_ACCESS "WC" 5216 // ----------------------------------------------------------------------------- 5217 // Field : IO_BANK0_INTR0_GPIO0_EDGE_LOW 5218 #define IO_BANK0_INTR0_GPIO0_EDGE_LOW_RESET _u(0x0) 5219 #define IO_BANK0_INTR0_GPIO0_EDGE_LOW_BITS _u(0x00000004) 5220 #define IO_BANK0_INTR0_GPIO0_EDGE_LOW_MSB _u(2) 5221 #define IO_BANK0_INTR0_GPIO0_EDGE_LOW_LSB _u(2) 5222 #define IO_BANK0_INTR0_GPIO0_EDGE_LOW_ACCESS "WC" 5223 // ----------------------------------------------------------------------------- 5224 // Field : IO_BANK0_INTR0_GPIO0_LEVEL_HIGH 5225 #define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_RESET _u(0x0) 5226 #define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) 5227 #define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_MSB _u(1) 5228 #define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_LSB _u(1) 5229 #define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_ACCESS "RO" 5230 // ----------------------------------------------------------------------------- 5231 // Field : IO_BANK0_INTR0_GPIO0_LEVEL_LOW 5232 #define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_RESET _u(0x0) 5233 #define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) 5234 #define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_MSB _u(0) 5235 #define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_LSB _u(0) 5236 #define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_ACCESS "RO" 5237 // ============================================================================= 5238 // Register : IO_BANK0_INTR1 5239 // Description : Raw Interrupts 5240 #define IO_BANK0_INTR1_OFFSET _u(0x000000f4) 5241 #define IO_BANK0_INTR1_BITS _u(0xffffffff) 5242 #define IO_BANK0_INTR1_RESET _u(0x00000000) 5243 // ----------------------------------------------------------------------------- 5244 // Field : IO_BANK0_INTR1_GPIO15_EDGE_HIGH 5245 #define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_RESET _u(0x0) 5246 #define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) 5247 #define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_MSB _u(31) 5248 #define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_LSB _u(31) 5249 #define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_ACCESS "WC" 5250 // ----------------------------------------------------------------------------- 5251 // Field : IO_BANK0_INTR1_GPIO15_EDGE_LOW 5252 #define IO_BANK0_INTR1_GPIO15_EDGE_LOW_RESET _u(0x0) 5253 #define IO_BANK0_INTR1_GPIO15_EDGE_LOW_BITS _u(0x40000000) 5254 #define IO_BANK0_INTR1_GPIO15_EDGE_LOW_MSB _u(30) 5255 #define IO_BANK0_INTR1_GPIO15_EDGE_LOW_LSB _u(30) 5256 #define IO_BANK0_INTR1_GPIO15_EDGE_LOW_ACCESS "WC" 5257 // ----------------------------------------------------------------------------- 5258 // Field : IO_BANK0_INTR1_GPIO15_LEVEL_HIGH 5259 #define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_RESET _u(0x0) 5260 #define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) 5261 #define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_MSB _u(29) 5262 #define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_LSB _u(29) 5263 #define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_ACCESS "RO" 5264 // ----------------------------------------------------------------------------- 5265 // Field : IO_BANK0_INTR1_GPIO15_LEVEL_LOW 5266 #define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_RESET _u(0x0) 5267 #define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) 5268 #define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_MSB _u(28) 5269 #define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_LSB _u(28) 5270 #define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_ACCESS "RO" 5271 // ----------------------------------------------------------------------------- 5272 // Field : IO_BANK0_INTR1_GPIO14_EDGE_HIGH 5273 #define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_RESET _u(0x0) 5274 #define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) 5275 #define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_MSB _u(27) 5276 #define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_LSB _u(27) 5277 #define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_ACCESS "WC" 5278 // ----------------------------------------------------------------------------- 5279 // Field : IO_BANK0_INTR1_GPIO14_EDGE_LOW 5280 #define IO_BANK0_INTR1_GPIO14_EDGE_LOW_RESET _u(0x0) 5281 #define IO_BANK0_INTR1_GPIO14_EDGE_LOW_BITS _u(0x04000000) 5282 #define IO_BANK0_INTR1_GPIO14_EDGE_LOW_MSB _u(26) 5283 #define IO_BANK0_INTR1_GPIO14_EDGE_LOW_LSB _u(26) 5284 #define IO_BANK0_INTR1_GPIO14_EDGE_LOW_ACCESS "WC" 5285 // ----------------------------------------------------------------------------- 5286 // Field : IO_BANK0_INTR1_GPIO14_LEVEL_HIGH 5287 #define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_RESET _u(0x0) 5288 #define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) 5289 #define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_MSB _u(25) 5290 #define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_LSB _u(25) 5291 #define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_ACCESS "RO" 5292 // ----------------------------------------------------------------------------- 5293 // Field : IO_BANK0_INTR1_GPIO14_LEVEL_LOW 5294 #define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_RESET _u(0x0) 5295 #define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) 5296 #define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_MSB _u(24) 5297 #define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_LSB _u(24) 5298 #define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_ACCESS "RO" 5299 // ----------------------------------------------------------------------------- 5300 // Field : IO_BANK0_INTR1_GPIO13_EDGE_HIGH 5301 #define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_RESET _u(0x0) 5302 #define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) 5303 #define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_MSB _u(23) 5304 #define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_LSB _u(23) 5305 #define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_ACCESS "WC" 5306 // ----------------------------------------------------------------------------- 5307 // Field : IO_BANK0_INTR1_GPIO13_EDGE_LOW 5308 #define IO_BANK0_INTR1_GPIO13_EDGE_LOW_RESET _u(0x0) 5309 #define IO_BANK0_INTR1_GPIO13_EDGE_LOW_BITS _u(0x00400000) 5310 #define IO_BANK0_INTR1_GPIO13_EDGE_LOW_MSB _u(22) 5311 #define IO_BANK0_INTR1_GPIO13_EDGE_LOW_LSB _u(22) 5312 #define IO_BANK0_INTR1_GPIO13_EDGE_LOW_ACCESS "WC" 5313 // ----------------------------------------------------------------------------- 5314 // Field : IO_BANK0_INTR1_GPIO13_LEVEL_HIGH 5315 #define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_RESET _u(0x0) 5316 #define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) 5317 #define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_MSB _u(21) 5318 #define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_LSB _u(21) 5319 #define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_ACCESS "RO" 5320 // ----------------------------------------------------------------------------- 5321 // Field : IO_BANK0_INTR1_GPIO13_LEVEL_LOW 5322 #define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_RESET _u(0x0) 5323 #define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) 5324 #define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_MSB _u(20) 5325 #define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_LSB _u(20) 5326 #define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_ACCESS "RO" 5327 // ----------------------------------------------------------------------------- 5328 // Field : IO_BANK0_INTR1_GPIO12_EDGE_HIGH 5329 #define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_RESET _u(0x0) 5330 #define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) 5331 #define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_MSB _u(19) 5332 #define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_LSB _u(19) 5333 #define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_ACCESS "WC" 5334 // ----------------------------------------------------------------------------- 5335 // Field : IO_BANK0_INTR1_GPIO12_EDGE_LOW 5336 #define IO_BANK0_INTR1_GPIO12_EDGE_LOW_RESET _u(0x0) 5337 #define IO_BANK0_INTR1_GPIO12_EDGE_LOW_BITS _u(0x00040000) 5338 #define IO_BANK0_INTR1_GPIO12_EDGE_LOW_MSB _u(18) 5339 #define IO_BANK0_INTR1_GPIO12_EDGE_LOW_LSB _u(18) 5340 #define IO_BANK0_INTR1_GPIO12_EDGE_LOW_ACCESS "WC" 5341 // ----------------------------------------------------------------------------- 5342 // Field : IO_BANK0_INTR1_GPIO12_LEVEL_HIGH 5343 #define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_RESET _u(0x0) 5344 #define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) 5345 #define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_MSB _u(17) 5346 #define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_LSB _u(17) 5347 #define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_ACCESS "RO" 5348 // ----------------------------------------------------------------------------- 5349 // Field : IO_BANK0_INTR1_GPIO12_LEVEL_LOW 5350 #define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_RESET _u(0x0) 5351 #define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) 5352 #define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_MSB _u(16) 5353 #define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_LSB _u(16) 5354 #define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_ACCESS "RO" 5355 // ----------------------------------------------------------------------------- 5356 // Field : IO_BANK0_INTR1_GPIO11_EDGE_HIGH 5357 #define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_RESET _u(0x0) 5358 #define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) 5359 #define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_MSB _u(15) 5360 #define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_LSB _u(15) 5361 #define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_ACCESS "WC" 5362 // ----------------------------------------------------------------------------- 5363 // Field : IO_BANK0_INTR1_GPIO11_EDGE_LOW 5364 #define IO_BANK0_INTR1_GPIO11_EDGE_LOW_RESET _u(0x0) 5365 #define IO_BANK0_INTR1_GPIO11_EDGE_LOW_BITS _u(0x00004000) 5366 #define IO_BANK0_INTR1_GPIO11_EDGE_LOW_MSB _u(14) 5367 #define IO_BANK0_INTR1_GPIO11_EDGE_LOW_LSB _u(14) 5368 #define IO_BANK0_INTR1_GPIO11_EDGE_LOW_ACCESS "WC" 5369 // ----------------------------------------------------------------------------- 5370 // Field : IO_BANK0_INTR1_GPIO11_LEVEL_HIGH 5371 #define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_RESET _u(0x0) 5372 #define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) 5373 #define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_MSB _u(13) 5374 #define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_LSB _u(13) 5375 #define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_ACCESS "RO" 5376 // ----------------------------------------------------------------------------- 5377 // Field : IO_BANK0_INTR1_GPIO11_LEVEL_LOW 5378 #define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_RESET _u(0x0) 5379 #define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) 5380 #define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_MSB _u(12) 5381 #define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_LSB _u(12) 5382 #define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_ACCESS "RO" 5383 // ----------------------------------------------------------------------------- 5384 // Field : IO_BANK0_INTR1_GPIO10_EDGE_HIGH 5385 #define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_RESET _u(0x0) 5386 #define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) 5387 #define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_MSB _u(11) 5388 #define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_LSB _u(11) 5389 #define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_ACCESS "WC" 5390 // ----------------------------------------------------------------------------- 5391 // Field : IO_BANK0_INTR1_GPIO10_EDGE_LOW 5392 #define IO_BANK0_INTR1_GPIO10_EDGE_LOW_RESET _u(0x0) 5393 #define IO_BANK0_INTR1_GPIO10_EDGE_LOW_BITS _u(0x00000400) 5394 #define IO_BANK0_INTR1_GPIO10_EDGE_LOW_MSB _u(10) 5395 #define IO_BANK0_INTR1_GPIO10_EDGE_LOW_LSB _u(10) 5396 #define IO_BANK0_INTR1_GPIO10_EDGE_LOW_ACCESS "WC" 5397 // ----------------------------------------------------------------------------- 5398 // Field : IO_BANK0_INTR1_GPIO10_LEVEL_HIGH 5399 #define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_RESET _u(0x0) 5400 #define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) 5401 #define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_MSB _u(9) 5402 #define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_LSB _u(9) 5403 #define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_ACCESS "RO" 5404 // ----------------------------------------------------------------------------- 5405 // Field : IO_BANK0_INTR1_GPIO10_LEVEL_LOW 5406 #define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_RESET _u(0x0) 5407 #define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) 5408 #define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_MSB _u(8) 5409 #define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_LSB _u(8) 5410 #define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_ACCESS "RO" 5411 // ----------------------------------------------------------------------------- 5412 // Field : IO_BANK0_INTR1_GPIO9_EDGE_HIGH 5413 #define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_RESET _u(0x0) 5414 #define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) 5415 #define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_MSB _u(7) 5416 #define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_LSB _u(7) 5417 #define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_ACCESS "WC" 5418 // ----------------------------------------------------------------------------- 5419 // Field : IO_BANK0_INTR1_GPIO9_EDGE_LOW 5420 #define IO_BANK0_INTR1_GPIO9_EDGE_LOW_RESET _u(0x0) 5421 #define IO_BANK0_INTR1_GPIO9_EDGE_LOW_BITS _u(0x00000040) 5422 #define IO_BANK0_INTR1_GPIO9_EDGE_LOW_MSB _u(6) 5423 #define IO_BANK0_INTR1_GPIO9_EDGE_LOW_LSB _u(6) 5424 #define IO_BANK0_INTR1_GPIO9_EDGE_LOW_ACCESS "WC" 5425 // ----------------------------------------------------------------------------- 5426 // Field : IO_BANK0_INTR1_GPIO9_LEVEL_HIGH 5427 #define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_RESET _u(0x0) 5428 #define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) 5429 #define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_MSB _u(5) 5430 #define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_LSB _u(5) 5431 #define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_ACCESS "RO" 5432 // ----------------------------------------------------------------------------- 5433 // Field : IO_BANK0_INTR1_GPIO9_LEVEL_LOW 5434 #define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_RESET _u(0x0) 5435 #define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) 5436 #define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_MSB _u(4) 5437 #define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_LSB _u(4) 5438 #define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_ACCESS "RO" 5439 // ----------------------------------------------------------------------------- 5440 // Field : IO_BANK0_INTR1_GPIO8_EDGE_HIGH 5441 #define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_RESET _u(0x0) 5442 #define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) 5443 #define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_MSB _u(3) 5444 #define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_LSB _u(3) 5445 #define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_ACCESS "WC" 5446 // ----------------------------------------------------------------------------- 5447 // Field : IO_BANK0_INTR1_GPIO8_EDGE_LOW 5448 #define IO_BANK0_INTR1_GPIO8_EDGE_LOW_RESET _u(0x0) 5449 #define IO_BANK0_INTR1_GPIO8_EDGE_LOW_BITS _u(0x00000004) 5450 #define IO_BANK0_INTR1_GPIO8_EDGE_LOW_MSB _u(2) 5451 #define IO_BANK0_INTR1_GPIO8_EDGE_LOW_LSB _u(2) 5452 #define IO_BANK0_INTR1_GPIO8_EDGE_LOW_ACCESS "WC" 5453 // ----------------------------------------------------------------------------- 5454 // Field : IO_BANK0_INTR1_GPIO8_LEVEL_HIGH 5455 #define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_RESET _u(0x0) 5456 #define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) 5457 #define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_MSB _u(1) 5458 #define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_LSB _u(1) 5459 #define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_ACCESS "RO" 5460 // ----------------------------------------------------------------------------- 5461 // Field : IO_BANK0_INTR1_GPIO8_LEVEL_LOW 5462 #define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_RESET _u(0x0) 5463 #define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) 5464 #define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_MSB _u(0) 5465 #define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_LSB _u(0) 5466 #define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_ACCESS "RO" 5467 // ============================================================================= 5468 // Register : IO_BANK0_INTR2 5469 // Description : Raw Interrupts 5470 #define IO_BANK0_INTR2_OFFSET _u(0x000000f8) 5471 #define IO_BANK0_INTR2_BITS _u(0xffffffff) 5472 #define IO_BANK0_INTR2_RESET _u(0x00000000) 5473 // ----------------------------------------------------------------------------- 5474 // Field : IO_BANK0_INTR2_GPIO23_EDGE_HIGH 5475 #define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_RESET _u(0x0) 5476 #define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) 5477 #define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_MSB _u(31) 5478 #define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_LSB _u(31) 5479 #define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_ACCESS "WC" 5480 // ----------------------------------------------------------------------------- 5481 // Field : IO_BANK0_INTR2_GPIO23_EDGE_LOW 5482 #define IO_BANK0_INTR2_GPIO23_EDGE_LOW_RESET _u(0x0) 5483 #define IO_BANK0_INTR2_GPIO23_EDGE_LOW_BITS _u(0x40000000) 5484 #define IO_BANK0_INTR2_GPIO23_EDGE_LOW_MSB _u(30) 5485 #define IO_BANK0_INTR2_GPIO23_EDGE_LOW_LSB _u(30) 5486 #define IO_BANK0_INTR2_GPIO23_EDGE_LOW_ACCESS "WC" 5487 // ----------------------------------------------------------------------------- 5488 // Field : IO_BANK0_INTR2_GPIO23_LEVEL_HIGH 5489 #define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_RESET _u(0x0) 5490 #define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) 5491 #define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_MSB _u(29) 5492 #define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_LSB _u(29) 5493 #define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_ACCESS "RO" 5494 // ----------------------------------------------------------------------------- 5495 // Field : IO_BANK0_INTR2_GPIO23_LEVEL_LOW 5496 #define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_RESET _u(0x0) 5497 #define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) 5498 #define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_MSB _u(28) 5499 #define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_LSB _u(28) 5500 #define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_ACCESS "RO" 5501 // ----------------------------------------------------------------------------- 5502 // Field : IO_BANK0_INTR2_GPIO22_EDGE_HIGH 5503 #define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_RESET _u(0x0) 5504 #define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) 5505 #define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_MSB _u(27) 5506 #define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_LSB _u(27) 5507 #define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_ACCESS "WC" 5508 // ----------------------------------------------------------------------------- 5509 // Field : IO_BANK0_INTR2_GPIO22_EDGE_LOW 5510 #define IO_BANK0_INTR2_GPIO22_EDGE_LOW_RESET _u(0x0) 5511 #define IO_BANK0_INTR2_GPIO22_EDGE_LOW_BITS _u(0x04000000) 5512 #define IO_BANK0_INTR2_GPIO22_EDGE_LOW_MSB _u(26) 5513 #define IO_BANK0_INTR2_GPIO22_EDGE_LOW_LSB _u(26) 5514 #define IO_BANK0_INTR2_GPIO22_EDGE_LOW_ACCESS "WC" 5515 // ----------------------------------------------------------------------------- 5516 // Field : IO_BANK0_INTR2_GPIO22_LEVEL_HIGH 5517 #define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_RESET _u(0x0) 5518 #define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) 5519 #define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_MSB _u(25) 5520 #define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_LSB _u(25) 5521 #define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_ACCESS "RO" 5522 // ----------------------------------------------------------------------------- 5523 // Field : IO_BANK0_INTR2_GPIO22_LEVEL_LOW 5524 #define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_RESET _u(0x0) 5525 #define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) 5526 #define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_MSB _u(24) 5527 #define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_LSB _u(24) 5528 #define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_ACCESS "RO" 5529 // ----------------------------------------------------------------------------- 5530 // Field : IO_BANK0_INTR2_GPIO21_EDGE_HIGH 5531 #define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_RESET _u(0x0) 5532 #define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) 5533 #define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_MSB _u(23) 5534 #define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_LSB _u(23) 5535 #define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_ACCESS "WC" 5536 // ----------------------------------------------------------------------------- 5537 // Field : IO_BANK0_INTR2_GPIO21_EDGE_LOW 5538 #define IO_BANK0_INTR2_GPIO21_EDGE_LOW_RESET _u(0x0) 5539 #define IO_BANK0_INTR2_GPIO21_EDGE_LOW_BITS _u(0x00400000) 5540 #define IO_BANK0_INTR2_GPIO21_EDGE_LOW_MSB _u(22) 5541 #define IO_BANK0_INTR2_GPIO21_EDGE_LOW_LSB _u(22) 5542 #define IO_BANK0_INTR2_GPIO21_EDGE_LOW_ACCESS "WC" 5543 // ----------------------------------------------------------------------------- 5544 // Field : IO_BANK0_INTR2_GPIO21_LEVEL_HIGH 5545 #define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_RESET _u(0x0) 5546 #define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) 5547 #define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_MSB _u(21) 5548 #define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_LSB _u(21) 5549 #define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_ACCESS "RO" 5550 // ----------------------------------------------------------------------------- 5551 // Field : IO_BANK0_INTR2_GPIO21_LEVEL_LOW 5552 #define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_RESET _u(0x0) 5553 #define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) 5554 #define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_MSB _u(20) 5555 #define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_LSB _u(20) 5556 #define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_ACCESS "RO" 5557 // ----------------------------------------------------------------------------- 5558 // Field : IO_BANK0_INTR2_GPIO20_EDGE_HIGH 5559 #define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_RESET _u(0x0) 5560 #define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) 5561 #define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_MSB _u(19) 5562 #define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_LSB _u(19) 5563 #define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_ACCESS "WC" 5564 // ----------------------------------------------------------------------------- 5565 // Field : IO_BANK0_INTR2_GPIO20_EDGE_LOW 5566 #define IO_BANK0_INTR2_GPIO20_EDGE_LOW_RESET _u(0x0) 5567 #define IO_BANK0_INTR2_GPIO20_EDGE_LOW_BITS _u(0x00040000) 5568 #define IO_BANK0_INTR2_GPIO20_EDGE_LOW_MSB _u(18) 5569 #define IO_BANK0_INTR2_GPIO20_EDGE_LOW_LSB _u(18) 5570 #define IO_BANK0_INTR2_GPIO20_EDGE_LOW_ACCESS "WC" 5571 // ----------------------------------------------------------------------------- 5572 // Field : IO_BANK0_INTR2_GPIO20_LEVEL_HIGH 5573 #define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_RESET _u(0x0) 5574 #define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) 5575 #define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_MSB _u(17) 5576 #define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_LSB _u(17) 5577 #define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_ACCESS "RO" 5578 // ----------------------------------------------------------------------------- 5579 // Field : IO_BANK0_INTR2_GPIO20_LEVEL_LOW 5580 #define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_RESET _u(0x0) 5581 #define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) 5582 #define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_MSB _u(16) 5583 #define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_LSB _u(16) 5584 #define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_ACCESS "RO" 5585 // ----------------------------------------------------------------------------- 5586 // Field : IO_BANK0_INTR2_GPIO19_EDGE_HIGH 5587 #define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_RESET _u(0x0) 5588 #define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) 5589 #define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_MSB _u(15) 5590 #define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_LSB _u(15) 5591 #define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_ACCESS "WC" 5592 // ----------------------------------------------------------------------------- 5593 // Field : IO_BANK0_INTR2_GPIO19_EDGE_LOW 5594 #define IO_BANK0_INTR2_GPIO19_EDGE_LOW_RESET _u(0x0) 5595 #define IO_BANK0_INTR2_GPIO19_EDGE_LOW_BITS _u(0x00004000) 5596 #define IO_BANK0_INTR2_GPIO19_EDGE_LOW_MSB _u(14) 5597 #define IO_BANK0_INTR2_GPIO19_EDGE_LOW_LSB _u(14) 5598 #define IO_BANK0_INTR2_GPIO19_EDGE_LOW_ACCESS "WC" 5599 // ----------------------------------------------------------------------------- 5600 // Field : IO_BANK0_INTR2_GPIO19_LEVEL_HIGH 5601 #define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_RESET _u(0x0) 5602 #define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) 5603 #define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_MSB _u(13) 5604 #define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_LSB _u(13) 5605 #define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_ACCESS "RO" 5606 // ----------------------------------------------------------------------------- 5607 // Field : IO_BANK0_INTR2_GPIO19_LEVEL_LOW 5608 #define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_RESET _u(0x0) 5609 #define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) 5610 #define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_MSB _u(12) 5611 #define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_LSB _u(12) 5612 #define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_ACCESS "RO" 5613 // ----------------------------------------------------------------------------- 5614 // Field : IO_BANK0_INTR2_GPIO18_EDGE_HIGH 5615 #define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_RESET _u(0x0) 5616 #define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) 5617 #define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_MSB _u(11) 5618 #define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_LSB _u(11) 5619 #define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_ACCESS "WC" 5620 // ----------------------------------------------------------------------------- 5621 // Field : IO_BANK0_INTR2_GPIO18_EDGE_LOW 5622 #define IO_BANK0_INTR2_GPIO18_EDGE_LOW_RESET _u(0x0) 5623 #define IO_BANK0_INTR2_GPIO18_EDGE_LOW_BITS _u(0x00000400) 5624 #define IO_BANK0_INTR2_GPIO18_EDGE_LOW_MSB _u(10) 5625 #define IO_BANK0_INTR2_GPIO18_EDGE_LOW_LSB _u(10) 5626 #define IO_BANK0_INTR2_GPIO18_EDGE_LOW_ACCESS "WC" 5627 // ----------------------------------------------------------------------------- 5628 // Field : IO_BANK0_INTR2_GPIO18_LEVEL_HIGH 5629 #define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_RESET _u(0x0) 5630 #define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) 5631 #define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_MSB _u(9) 5632 #define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_LSB _u(9) 5633 #define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_ACCESS "RO" 5634 // ----------------------------------------------------------------------------- 5635 // Field : IO_BANK0_INTR2_GPIO18_LEVEL_LOW 5636 #define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_RESET _u(0x0) 5637 #define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) 5638 #define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_MSB _u(8) 5639 #define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_LSB _u(8) 5640 #define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_ACCESS "RO" 5641 // ----------------------------------------------------------------------------- 5642 // Field : IO_BANK0_INTR2_GPIO17_EDGE_HIGH 5643 #define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_RESET _u(0x0) 5644 #define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) 5645 #define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_MSB _u(7) 5646 #define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_LSB _u(7) 5647 #define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_ACCESS "WC" 5648 // ----------------------------------------------------------------------------- 5649 // Field : IO_BANK0_INTR2_GPIO17_EDGE_LOW 5650 #define IO_BANK0_INTR2_GPIO17_EDGE_LOW_RESET _u(0x0) 5651 #define IO_BANK0_INTR2_GPIO17_EDGE_LOW_BITS _u(0x00000040) 5652 #define IO_BANK0_INTR2_GPIO17_EDGE_LOW_MSB _u(6) 5653 #define IO_BANK0_INTR2_GPIO17_EDGE_LOW_LSB _u(6) 5654 #define IO_BANK0_INTR2_GPIO17_EDGE_LOW_ACCESS "WC" 5655 // ----------------------------------------------------------------------------- 5656 // Field : IO_BANK0_INTR2_GPIO17_LEVEL_HIGH 5657 #define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_RESET _u(0x0) 5658 #define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) 5659 #define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_MSB _u(5) 5660 #define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_LSB _u(5) 5661 #define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_ACCESS "RO" 5662 // ----------------------------------------------------------------------------- 5663 // Field : IO_BANK0_INTR2_GPIO17_LEVEL_LOW 5664 #define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_RESET _u(0x0) 5665 #define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) 5666 #define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_MSB _u(4) 5667 #define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_LSB _u(4) 5668 #define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_ACCESS "RO" 5669 // ----------------------------------------------------------------------------- 5670 // Field : IO_BANK0_INTR2_GPIO16_EDGE_HIGH 5671 #define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_RESET _u(0x0) 5672 #define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) 5673 #define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_MSB _u(3) 5674 #define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_LSB _u(3) 5675 #define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_ACCESS "WC" 5676 // ----------------------------------------------------------------------------- 5677 // Field : IO_BANK0_INTR2_GPIO16_EDGE_LOW 5678 #define IO_BANK0_INTR2_GPIO16_EDGE_LOW_RESET _u(0x0) 5679 #define IO_BANK0_INTR2_GPIO16_EDGE_LOW_BITS _u(0x00000004) 5680 #define IO_BANK0_INTR2_GPIO16_EDGE_LOW_MSB _u(2) 5681 #define IO_BANK0_INTR2_GPIO16_EDGE_LOW_LSB _u(2) 5682 #define IO_BANK0_INTR2_GPIO16_EDGE_LOW_ACCESS "WC" 5683 // ----------------------------------------------------------------------------- 5684 // Field : IO_BANK0_INTR2_GPIO16_LEVEL_HIGH 5685 #define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_RESET _u(0x0) 5686 #define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) 5687 #define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_MSB _u(1) 5688 #define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_LSB _u(1) 5689 #define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_ACCESS "RO" 5690 // ----------------------------------------------------------------------------- 5691 // Field : IO_BANK0_INTR2_GPIO16_LEVEL_LOW 5692 #define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_RESET _u(0x0) 5693 #define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) 5694 #define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_MSB _u(0) 5695 #define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_LSB _u(0) 5696 #define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_ACCESS "RO" 5697 // ============================================================================= 5698 // Register : IO_BANK0_INTR3 5699 // Description : Raw Interrupts 5700 #define IO_BANK0_INTR3_OFFSET _u(0x000000fc) 5701 #define IO_BANK0_INTR3_BITS _u(0x00ffffff) 5702 #define IO_BANK0_INTR3_RESET _u(0x00000000) 5703 // ----------------------------------------------------------------------------- 5704 // Field : IO_BANK0_INTR3_GPIO29_EDGE_HIGH 5705 #define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_RESET _u(0x0) 5706 #define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) 5707 #define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_MSB _u(23) 5708 #define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_LSB _u(23) 5709 #define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_ACCESS "WC" 5710 // ----------------------------------------------------------------------------- 5711 // Field : IO_BANK0_INTR3_GPIO29_EDGE_LOW 5712 #define IO_BANK0_INTR3_GPIO29_EDGE_LOW_RESET _u(0x0) 5713 #define IO_BANK0_INTR3_GPIO29_EDGE_LOW_BITS _u(0x00400000) 5714 #define IO_BANK0_INTR3_GPIO29_EDGE_LOW_MSB _u(22) 5715 #define IO_BANK0_INTR3_GPIO29_EDGE_LOW_LSB _u(22) 5716 #define IO_BANK0_INTR3_GPIO29_EDGE_LOW_ACCESS "WC" 5717 // ----------------------------------------------------------------------------- 5718 // Field : IO_BANK0_INTR3_GPIO29_LEVEL_HIGH 5719 #define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_RESET _u(0x0) 5720 #define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) 5721 #define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_MSB _u(21) 5722 #define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_LSB _u(21) 5723 #define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_ACCESS "RO" 5724 // ----------------------------------------------------------------------------- 5725 // Field : IO_BANK0_INTR3_GPIO29_LEVEL_LOW 5726 #define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_RESET _u(0x0) 5727 #define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) 5728 #define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_MSB _u(20) 5729 #define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_LSB _u(20) 5730 #define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_ACCESS "RO" 5731 // ----------------------------------------------------------------------------- 5732 // Field : IO_BANK0_INTR3_GPIO28_EDGE_HIGH 5733 #define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_RESET _u(0x0) 5734 #define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) 5735 #define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_MSB _u(19) 5736 #define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_LSB _u(19) 5737 #define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_ACCESS "WC" 5738 // ----------------------------------------------------------------------------- 5739 // Field : IO_BANK0_INTR3_GPIO28_EDGE_LOW 5740 #define IO_BANK0_INTR3_GPIO28_EDGE_LOW_RESET _u(0x0) 5741 #define IO_BANK0_INTR3_GPIO28_EDGE_LOW_BITS _u(0x00040000) 5742 #define IO_BANK0_INTR3_GPIO28_EDGE_LOW_MSB _u(18) 5743 #define IO_BANK0_INTR3_GPIO28_EDGE_LOW_LSB _u(18) 5744 #define IO_BANK0_INTR3_GPIO28_EDGE_LOW_ACCESS "WC" 5745 // ----------------------------------------------------------------------------- 5746 // Field : IO_BANK0_INTR3_GPIO28_LEVEL_HIGH 5747 #define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_RESET _u(0x0) 5748 #define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) 5749 #define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_MSB _u(17) 5750 #define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_LSB _u(17) 5751 #define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_ACCESS "RO" 5752 // ----------------------------------------------------------------------------- 5753 // Field : IO_BANK0_INTR3_GPIO28_LEVEL_LOW 5754 #define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_RESET _u(0x0) 5755 #define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) 5756 #define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_MSB _u(16) 5757 #define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_LSB _u(16) 5758 #define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_ACCESS "RO" 5759 // ----------------------------------------------------------------------------- 5760 // Field : IO_BANK0_INTR3_GPIO27_EDGE_HIGH 5761 #define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_RESET _u(0x0) 5762 #define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) 5763 #define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_MSB _u(15) 5764 #define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_LSB _u(15) 5765 #define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_ACCESS "WC" 5766 // ----------------------------------------------------------------------------- 5767 // Field : IO_BANK0_INTR3_GPIO27_EDGE_LOW 5768 #define IO_BANK0_INTR3_GPIO27_EDGE_LOW_RESET _u(0x0) 5769 #define IO_BANK0_INTR3_GPIO27_EDGE_LOW_BITS _u(0x00004000) 5770 #define IO_BANK0_INTR3_GPIO27_EDGE_LOW_MSB _u(14) 5771 #define IO_BANK0_INTR3_GPIO27_EDGE_LOW_LSB _u(14) 5772 #define IO_BANK0_INTR3_GPIO27_EDGE_LOW_ACCESS "WC" 5773 // ----------------------------------------------------------------------------- 5774 // Field : IO_BANK0_INTR3_GPIO27_LEVEL_HIGH 5775 #define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_RESET _u(0x0) 5776 #define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) 5777 #define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_MSB _u(13) 5778 #define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_LSB _u(13) 5779 #define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_ACCESS "RO" 5780 // ----------------------------------------------------------------------------- 5781 // Field : IO_BANK0_INTR3_GPIO27_LEVEL_LOW 5782 #define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_RESET _u(0x0) 5783 #define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) 5784 #define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_MSB _u(12) 5785 #define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_LSB _u(12) 5786 #define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_ACCESS "RO" 5787 // ----------------------------------------------------------------------------- 5788 // Field : IO_BANK0_INTR3_GPIO26_EDGE_HIGH 5789 #define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_RESET _u(0x0) 5790 #define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) 5791 #define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_MSB _u(11) 5792 #define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_LSB _u(11) 5793 #define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_ACCESS "WC" 5794 // ----------------------------------------------------------------------------- 5795 // Field : IO_BANK0_INTR3_GPIO26_EDGE_LOW 5796 #define IO_BANK0_INTR3_GPIO26_EDGE_LOW_RESET _u(0x0) 5797 #define IO_BANK0_INTR3_GPIO26_EDGE_LOW_BITS _u(0x00000400) 5798 #define IO_BANK0_INTR3_GPIO26_EDGE_LOW_MSB _u(10) 5799 #define IO_BANK0_INTR3_GPIO26_EDGE_LOW_LSB _u(10) 5800 #define IO_BANK0_INTR3_GPIO26_EDGE_LOW_ACCESS "WC" 5801 // ----------------------------------------------------------------------------- 5802 // Field : IO_BANK0_INTR3_GPIO26_LEVEL_HIGH 5803 #define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_RESET _u(0x0) 5804 #define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) 5805 #define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_MSB _u(9) 5806 #define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_LSB _u(9) 5807 #define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_ACCESS "RO" 5808 // ----------------------------------------------------------------------------- 5809 // Field : IO_BANK0_INTR3_GPIO26_LEVEL_LOW 5810 #define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_RESET _u(0x0) 5811 #define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) 5812 #define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_MSB _u(8) 5813 #define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_LSB _u(8) 5814 #define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_ACCESS "RO" 5815 // ----------------------------------------------------------------------------- 5816 // Field : IO_BANK0_INTR3_GPIO25_EDGE_HIGH 5817 #define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_RESET _u(0x0) 5818 #define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) 5819 #define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_MSB _u(7) 5820 #define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_LSB _u(7) 5821 #define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_ACCESS "WC" 5822 // ----------------------------------------------------------------------------- 5823 // Field : IO_BANK0_INTR3_GPIO25_EDGE_LOW 5824 #define IO_BANK0_INTR3_GPIO25_EDGE_LOW_RESET _u(0x0) 5825 #define IO_BANK0_INTR3_GPIO25_EDGE_LOW_BITS _u(0x00000040) 5826 #define IO_BANK0_INTR3_GPIO25_EDGE_LOW_MSB _u(6) 5827 #define IO_BANK0_INTR3_GPIO25_EDGE_LOW_LSB _u(6) 5828 #define IO_BANK0_INTR3_GPIO25_EDGE_LOW_ACCESS "WC" 5829 // ----------------------------------------------------------------------------- 5830 // Field : IO_BANK0_INTR3_GPIO25_LEVEL_HIGH 5831 #define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_RESET _u(0x0) 5832 #define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) 5833 #define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_MSB _u(5) 5834 #define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_LSB _u(5) 5835 #define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_ACCESS "RO" 5836 // ----------------------------------------------------------------------------- 5837 // Field : IO_BANK0_INTR3_GPIO25_LEVEL_LOW 5838 #define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_RESET _u(0x0) 5839 #define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) 5840 #define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_MSB _u(4) 5841 #define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_LSB _u(4) 5842 #define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_ACCESS "RO" 5843 // ----------------------------------------------------------------------------- 5844 // Field : IO_BANK0_INTR3_GPIO24_EDGE_HIGH 5845 #define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_RESET _u(0x0) 5846 #define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) 5847 #define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_MSB _u(3) 5848 #define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_LSB _u(3) 5849 #define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_ACCESS "WC" 5850 // ----------------------------------------------------------------------------- 5851 // Field : IO_BANK0_INTR3_GPIO24_EDGE_LOW 5852 #define IO_BANK0_INTR3_GPIO24_EDGE_LOW_RESET _u(0x0) 5853 #define IO_BANK0_INTR3_GPIO24_EDGE_LOW_BITS _u(0x00000004) 5854 #define IO_BANK0_INTR3_GPIO24_EDGE_LOW_MSB _u(2) 5855 #define IO_BANK0_INTR3_GPIO24_EDGE_LOW_LSB _u(2) 5856 #define IO_BANK0_INTR3_GPIO24_EDGE_LOW_ACCESS "WC" 5857 // ----------------------------------------------------------------------------- 5858 // Field : IO_BANK0_INTR3_GPIO24_LEVEL_HIGH 5859 #define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_RESET _u(0x0) 5860 #define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) 5861 #define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_MSB _u(1) 5862 #define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_LSB _u(1) 5863 #define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_ACCESS "RO" 5864 // ----------------------------------------------------------------------------- 5865 // Field : IO_BANK0_INTR3_GPIO24_LEVEL_LOW 5866 #define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_RESET _u(0x0) 5867 #define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) 5868 #define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_MSB _u(0) 5869 #define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_LSB _u(0) 5870 #define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_ACCESS "RO" 5871 // ============================================================================= 5872 // Register : IO_BANK0_PROC0_INTE0 5873 // Description : Interrupt Enable for proc0 5874 #define IO_BANK0_PROC0_INTE0_OFFSET _u(0x00000100) 5875 #define IO_BANK0_PROC0_INTE0_BITS _u(0xffffffff) 5876 #define IO_BANK0_PROC0_INTE0_RESET _u(0x00000000) 5877 // ----------------------------------------------------------------------------- 5878 // Field : IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH 5879 #define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_RESET _u(0x0) 5880 #define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) 5881 #define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_MSB _u(31) 5882 #define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_LSB _u(31) 5883 #define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_ACCESS "RW" 5884 // ----------------------------------------------------------------------------- 5885 // Field : IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW 5886 #define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_RESET _u(0x0) 5887 #define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_BITS _u(0x40000000) 5888 #define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_MSB _u(30) 5889 #define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_LSB _u(30) 5890 #define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_ACCESS "RW" 5891 // ----------------------------------------------------------------------------- 5892 // Field : IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH 5893 #define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_RESET _u(0x0) 5894 #define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) 5895 #define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_MSB _u(29) 5896 #define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_LSB _u(29) 5897 #define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_ACCESS "RW" 5898 // ----------------------------------------------------------------------------- 5899 // Field : IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW 5900 #define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_RESET _u(0x0) 5901 #define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) 5902 #define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_MSB _u(28) 5903 #define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_LSB _u(28) 5904 #define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_ACCESS "RW" 5905 // ----------------------------------------------------------------------------- 5906 // Field : IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH 5907 #define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_RESET _u(0x0) 5908 #define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) 5909 #define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_MSB _u(27) 5910 #define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_LSB _u(27) 5911 #define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_ACCESS "RW" 5912 // ----------------------------------------------------------------------------- 5913 // Field : IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW 5914 #define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_RESET _u(0x0) 5915 #define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_BITS _u(0x04000000) 5916 #define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_MSB _u(26) 5917 #define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_LSB _u(26) 5918 #define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_ACCESS "RW" 5919 // ----------------------------------------------------------------------------- 5920 // Field : IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH 5921 #define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_RESET _u(0x0) 5922 #define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) 5923 #define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_MSB _u(25) 5924 #define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_LSB _u(25) 5925 #define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_ACCESS "RW" 5926 // ----------------------------------------------------------------------------- 5927 // Field : IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW 5928 #define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_RESET _u(0x0) 5929 #define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) 5930 #define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_MSB _u(24) 5931 #define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_LSB _u(24) 5932 #define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_ACCESS "RW" 5933 // ----------------------------------------------------------------------------- 5934 // Field : IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH 5935 #define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_RESET _u(0x0) 5936 #define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) 5937 #define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_MSB _u(23) 5938 #define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_LSB _u(23) 5939 #define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_ACCESS "RW" 5940 // ----------------------------------------------------------------------------- 5941 // Field : IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW 5942 #define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_RESET _u(0x0) 5943 #define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_BITS _u(0x00400000) 5944 #define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_MSB _u(22) 5945 #define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_LSB _u(22) 5946 #define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_ACCESS "RW" 5947 // ----------------------------------------------------------------------------- 5948 // Field : IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH 5949 #define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_RESET _u(0x0) 5950 #define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) 5951 #define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_MSB _u(21) 5952 #define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_LSB _u(21) 5953 #define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_ACCESS "RW" 5954 // ----------------------------------------------------------------------------- 5955 // Field : IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW 5956 #define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_RESET _u(0x0) 5957 #define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) 5958 #define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_MSB _u(20) 5959 #define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_LSB _u(20) 5960 #define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_ACCESS "RW" 5961 // ----------------------------------------------------------------------------- 5962 // Field : IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH 5963 #define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_RESET _u(0x0) 5964 #define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) 5965 #define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_MSB _u(19) 5966 #define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_LSB _u(19) 5967 #define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_ACCESS "RW" 5968 // ----------------------------------------------------------------------------- 5969 // Field : IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW 5970 #define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_RESET _u(0x0) 5971 #define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_BITS _u(0x00040000) 5972 #define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_MSB _u(18) 5973 #define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_LSB _u(18) 5974 #define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_ACCESS "RW" 5975 // ----------------------------------------------------------------------------- 5976 // Field : IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH 5977 #define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_RESET _u(0x0) 5978 #define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) 5979 #define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_MSB _u(17) 5980 #define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_LSB _u(17) 5981 #define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_ACCESS "RW" 5982 // ----------------------------------------------------------------------------- 5983 // Field : IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW 5984 #define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_RESET _u(0x0) 5985 #define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) 5986 #define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_MSB _u(16) 5987 #define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_LSB _u(16) 5988 #define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_ACCESS "RW" 5989 // ----------------------------------------------------------------------------- 5990 // Field : IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH 5991 #define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_RESET _u(0x0) 5992 #define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) 5993 #define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_MSB _u(15) 5994 #define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_LSB _u(15) 5995 #define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_ACCESS "RW" 5996 // ----------------------------------------------------------------------------- 5997 // Field : IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW 5998 #define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_RESET _u(0x0) 5999 #define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_BITS _u(0x00004000) 6000 #define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_MSB _u(14) 6001 #define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_LSB _u(14) 6002 #define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_ACCESS "RW" 6003 // ----------------------------------------------------------------------------- 6004 // Field : IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH 6005 #define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_RESET _u(0x0) 6006 #define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) 6007 #define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_MSB _u(13) 6008 #define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_LSB _u(13) 6009 #define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_ACCESS "RW" 6010 // ----------------------------------------------------------------------------- 6011 // Field : IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW 6012 #define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_RESET _u(0x0) 6013 #define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) 6014 #define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_MSB _u(12) 6015 #define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_LSB _u(12) 6016 #define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_ACCESS "RW" 6017 // ----------------------------------------------------------------------------- 6018 // Field : IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH 6019 #define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_RESET _u(0x0) 6020 #define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) 6021 #define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_MSB _u(11) 6022 #define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_LSB _u(11) 6023 #define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_ACCESS "RW" 6024 // ----------------------------------------------------------------------------- 6025 // Field : IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW 6026 #define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_RESET _u(0x0) 6027 #define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_BITS _u(0x00000400) 6028 #define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_MSB _u(10) 6029 #define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_LSB _u(10) 6030 #define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_ACCESS "RW" 6031 // ----------------------------------------------------------------------------- 6032 // Field : IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH 6033 #define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_RESET _u(0x0) 6034 #define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) 6035 #define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_MSB _u(9) 6036 #define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_LSB _u(9) 6037 #define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_ACCESS "RW" 6038 // ----------------------------------------------------------------------------- 6039 // Field : IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW 6040 #define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_RESET _u(0x0) 6041 #define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) 6042 #define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_MSB _u(8) 6043 #define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_LSB _u(8) 6044 #define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_ACCESS "RW" 6045 // ----------------------------------------------------------------------------- 6046 // Field : IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH 6047 #define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_RESET _u(0x0) 6048 #define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) 6049 #define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_MSB _u(7) 6050 #define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_LSB _u(7) 6051 #define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_ACCESS "RW" 6052 // ----------------------------------------------------------------------------- 6053 // Field : IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW 6054 #define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_RESET _u(0x0) 6055 #define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_BITS _u(0x00000040) 6056 #define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_MSB _u(6) 6057 #define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_LSB _u(6) 6058 #define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_ACCESS "RW" 6059 // ----------------------------------------------------------------------------- 6060 // Field : IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH 6061 #define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_RESET _u(0x0) 6062 #define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) 6063 #define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_MSB _u(5) 6064 #define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_LSB _u(5) 6065 #define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_ACCESS "RW" 6066 // ----------------------------------------------------------------------------- 6067 // Field : IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW 6068 #define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_RESET _u(0x0) 6069 #define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) 6070 #define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_MSB _u(4) 6071 #define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_LSB _u(4) 6072 #define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_ACCESS "RW" 6073 // ----------------------------------------------------------------------------- 6074 // Field : IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH 6075 #define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_RESET _u(0x0) 6076 #define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) 6077 #define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_MSB _u(3) 6078 #define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_LSB _u(3) 6079 #define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_ACCESS "RW" 6080 // ----------------------------------------------------------------------------- 6081 // Field : IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW 6082 #define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_RESET _u(0x0) 6083 #define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_BITS _u(0x00000004) 6084 #define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_MSB _u(2) 6085 #define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_LSB _u(2) 6086 #define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_ACCESS "RW" 6087 // ----------------------------------------------------------------------------- 6088 // Field : IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH 6089 #define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_RESET _u(0x0) 6090 #define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) 6091 #define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_MSB _u(1) 6092 #define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_LSB _u(1) 6093 #define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_ACCESS "RW" 6094 // ----------------------------------------------------------------------------- 6095 // Field : IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW 6096 #define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_RESET _u(0x0) 6097 #define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) 6098 #define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_MSB _u(0) 6099 #define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_LSB _u(0) 6100 #define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_ACCESS "RW" 6101 // ============================================================================= 6102 // Register : IO_BANK0_PROC0_INTE1 6103 // Description : Interrupt Enable for proc0 6104 #define IO_BANK0_PROC0_INTE1_OFFSET _u(0x00000104) 6105 #define IO_BANK0_PROC0_INTE1_BITS _u(0xffffffff) 6106 #define IO_BANK0_PROC0_INTE1_RESET _u(0x00000000) 6107 // ----------------------------------------------------------------------------- 6108 // Field : IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH 6109 #define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_RESET _u(0x0) 6110 #define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) 6111 #define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_MSB _u(31) 6112 #define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_LSB _u(31) 6113 #define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_ACCESS "RW" 6114 // ----------------------------------------------------------------------------- 6115 // Field : IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW 6116 #define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_RESET _u(0x0) 6117 #define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_BITS _u(0x40000000) 6118 #define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_MSB _u(30) 6119 #define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_LSB _u(30) 6120 #define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_ACCESS "RW" 6121 // ----------------------------------------------------------------------------- 6122 // Field : IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH 6123 #define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_RESET _u(0x0) 6124 #define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) 6125 #define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_MSB _u(29) 6126 #define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_LSB _u(29) 6127 #define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_ACCESS "RW" 6128 // ----------------------------------------------------------------------------- 6129 // Field : IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW 6130 #define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_RESET _u(0x0) 6131 #define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) 6132 #define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_MSB _u(28) 6133 #define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_LSB _u(28) 6134 #define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_ACCESS "RW" 6135 // ----------------------------------------------------------------------------- 6136 // Field : IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH 6137 #define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_RESET _u(0x0) 6138 #define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) 6139 #define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_MSB _u(27) 6140 #define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_LSB _u(27) 6141 #define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_ACCESS "RW" 6142 // ----------------------------------------------------------------------------- 6143 // Field : IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW 6144 #define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_RESET _u(0x0) 6145 #define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_BITS _u(0x04000000) 6146 #define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_MSB _u(26) 6147 #define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_LSB _u(26) 6148 #define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_ACCESS "RW" 6149 // ----------------------------------------------------------------------------- 6150 // Field : IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH 6151 #define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_RESET _u(0x0) 6152 #define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) 6153 #define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_MSB _u(25) 6154 #define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_LSB _u(25) 6155 #define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_ACCESS "RW" 6156 // ----------------------------------------------------------------------------- 6157 // Field : IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW 6158 #define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_RESET _u(0x0) 6159 #define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) 6160 #define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_MSB _u(24) 6161 #define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_LSB _u(24) 6162 #define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_ACCESS "RW" 6163 // ----------------------------------------------------------------------------- 6164 // Field : IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH 6165 #define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_RESET _u(0x0) 6166 #define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) 6167 #define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_MSB _u(23) 6168 #define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_LSB _u(23) 6169 #define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_ACCESS "RW" 6170 // ----------------------------------------------------------------------------- 6171 // Field : IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW 6172 #define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_RESET _u(0x0) 6173 #define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_BITS _u(0x00400000) 6174 #define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_MSB _u(22) 6175 #define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_LSB _u(22) 6176 #define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_ACCESS "RW" 6177 // ----------------------------------------------------------------------------- 6178 // Field : IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH 6179 #define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_RESET _u(0x0) 6180 #define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) 6181 #define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_MSB _u(21) 6182 #define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_LSB _u(21) 6183 #define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_ACCESS "RW" 6184 // ----------------------------------------------------------------------------- 6185 // Field : IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW 6186 #define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_RESET _u(0x0) 6187 #define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) 6188 #define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_MSB _u(20) 6189 #define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_LSB _u(20) 6190 #define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_ACCESS "RW" 6191 // ----------------------------------------------------------------------------- 6192 // Field : IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH 6193 #define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_RESET _u(0x0) 6194 #define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) 6195 #define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_MSB _u(19) 6196 #define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_LSB _u(19) 6197 #define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_ACCESS "RW" 6198 // ----------------------------------------------------------------------------- 6199 // Field : IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW 6200 #define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_RESET _u(0x0) 6201 #define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_BITS _u(0x00040000) 6202 #define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_MSB _u(18) 6203 #define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_LSB _u(18) 6204 #define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_ACCESS "RW" 6205 // ----------------------------------------------------------------------------- 6206 // Field : IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH 6207 #define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_RESET _u(0x0) 6208 #define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) 6209 #define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_MSB _u(17) 6210 #define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_LSB _u(17) 6211 #define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_ACCESS "RW" 6212 // ----------------------------------------------------------------------------- 6213 // Field : IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW 6214 #define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_RESET _u(0x0) 6215 #define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) 6216 #define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_MSB _u(16) 6217 #define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_LSB _u(16) 6218 #define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_ACCESS "RW" 6219 // ----------------------------------------------------------------------------- 6220 // Field : IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH 6221 #define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_RESET _u(0x0) 6222 #define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) 6223 #define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_MSB _u(15) 6224 #define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_LSB _u(15) 6225 #define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_ACCESS "RW" 6226 // ----------------------------------------------------------------------------- 6227 // Field : IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW 6228 #define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_RESET _u(0x0) 6229 #define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_BITS _u(0x00004000) 6230 #define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_MSB _u(14) 6231 #define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_LSB _u(14) 6232 #define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_ACCESS "RW" 6233 // ----------------------------------------------------------------------------- 6234 // Field : IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH 6235 #define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_RESET _u(0x0) 6236 #define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) 6237 #define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_MSB _u(13) 6238 #define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_LSB _u(13) 6239 #define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_ACCESS "RW" 6240 // ----------------------------------------------------------------------------- 6241 // Field : IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW 6242 #define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_RESET _u(0x0) 6243 #define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) 6244 #define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_MSB _u(12) 6245 #define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_LSB _u(12) 6246 #define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_ACCESS "RW" 6247 // ----------------------------------------------------------------------------- 6248 // Field : IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH 6249 #define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_RESET _u(0x0) 6250 #define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) 6251 #define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_MSB _u(11) 6252 #define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_LSB _u(11) 6253 #define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_ACCESS "RW" 6254 // ----------------------------------------------------------------------------- 6255 // Field : IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW 6256 #define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_RESET _u(0x0) 6257 #define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_BITS _u(0x00000400) 6258 #define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_MSB _u(10) 6259 #define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_LSB _u(10) 6260 #define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_ACCESS "RW" 6261 // ----------------------------------------------------------------------------- 6262 // Field : IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH 6263 #define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_RESET _u(0x0) 6264 #define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) 6265 #define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_MSB _u(9) 6266 #define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_LSB _u(9) 6267 #define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_ACCESS "RW" 6268 // ----------------------------------------------------------------------------- 6269 // Field : IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW 6270 #define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_RESET _u(0x0) 6271 #define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) 6272 #define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_MSB _u(8) 6273 #define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_LSB _u(8) 6274 #define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_ACCESS "RW" 6275 // ----------------------------------------------------------------------------- 6276 // Field : IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH 6277 #define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_RESET _u(0x0) 6278 #define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) 6279 #define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_MSB _u(7) 6280 #define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_LSB _u(7) 6281 #define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_ACCESS "RW" 6282 // ----------------------------------------------------------------------------- 6283 // Field : IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW 6284 #define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_RESET _u(0x0) 6285 #define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_BITS _u(0x00000040) 6286 #define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_MSB _u(6) 6287 #define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_LSB _u(6) 6288 #define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_ACCESS "RW" 6289 // ----------------------------------------------------------------------------- 6290 // Field : IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH 6291 #define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_RESET _u(0x0) 6292 #define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) 6293 #define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_MSB _u(5) 6294 #define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_LSB _u(5) 6295 #define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_ACCESS "RW" 6296 // ----------------------------------------------------------------------------- 6297 // Field : IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW 6298 #define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_RESET _u(0x0) 6299 #define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) 6300 #define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_MSB _u(4) 6301 #define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_LSB _u(4) 6302 #define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_ACCESS "RW" 6303 // ----------------------------------------------------------------------------- 6304 // Field : IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH 6305 #define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_RESET _u(0x0) 6306 #define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) 6307 #define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_MSB _u(3) 6308 #define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_LSB _u(3) 6309 #define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_ACCESS "RW" 6310 // ----------------------------------------------------------------------------- 6311 // Field : IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW 6312 #define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_RESET _u(0x0) 6313 #define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_BITS _u(0x00000004) 6314 #define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_MSB _u(2) 6315 #define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_LSB _u(2) 6316 #define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_ACCESS "RW" 6317 // ----------------------------------------------------------------------------- 6318 // Field : IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH 6319 #define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_RESET _u(0x0) 6320 #define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) 6321 #define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_MSB _u(1) 6322 #define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_LSB _u(1) 6323 #define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_ACCESS "RW" 6324 // ----------------------------------------------------------------------------- 6325 // Field : IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW 6326 #define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_RESET _u(0x0) 6327 #define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) 6328 #define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_MSB _u(0) 6329 #define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_LSB _u(0) 6330 #define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_ACCESS "RW" 6331 // ============================================================================= 6332 // Register : IO_BANK0_PROC0_INTE2 6333 // Description : Interrupt Enable for proc0 6334 #define IO_BANK0_PROC0_INTE2_OFFSET _u(0x00000108) 6335 #define IO_BANK0_PROC0_INTE2_BITS _u(0xffffffff) 6336 #define IO_BANK0_PROC0_INTE2_RESET _u(0x00000000) 6337 // ----------------------------------------------------------------------------- 6338 // Field : IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH 6339 #define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_RESET _u(0x0) 6340 #define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) 6341 #define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_MSB _u(31) 6342 #define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_LSB _u(31) 6343 #define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_ACCESS "RW" 6344 // ----------------------------------------------------------------------------- 6345 // Field : IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW 6346 #define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_RESET _u(0x0) 6347 #define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_BITS _u(0x40000000) 6348 #define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_MSB _u(30) 6349 #define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_LSB _u(30) 6350 #define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_ACCESS "RW" 6351 // ----------------------------------------------------------------------------- 6352 // Field : IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH 6353 #define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_RESET _u(0x0) 6354 #define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) 6355 #define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_MSB _u(29) 6356 #define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_LSB _u(29) 6357 #define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_ACCESS "RW" 6358 // ----------------------------------------------------------------------------- 6359 // Field : IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW 6360 #define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_RESET _u(0x0) 6361 #define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) 6362 #define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_MSB _u(28) 6363 #define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_LSB _u(28) 6364 #define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_ACCESS "RW" 6365 // ----------------------------------------------------------------------------- 6366 // Field : IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH 6367 #define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_RESET _u(0x0) 6368 #define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) 6369 #define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_MSB _u(27) 6370 #define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_LSB _u(27) 6371 #define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_ACCESS "RW" 6372 // ----------------------------------------------------------------------------- 6373 // Field : IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW 6374 #define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_RESET _u(0x0) 6375 #define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_BITS _u(0x04000000) 6376 #define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_MSB _u(26) 6377 #define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_LSB _u(26) 6378 #define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_ACCESS "RW" 6379 // ----------------------------------------------------------------------------- 6380 // Field : IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH 6381 #define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_RESET _u(0x0) 6382 #define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) 6383 #define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_MSB _u(25) 6384 #define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_LSB _u(25) 6385 #define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_ACCESS "RW" 6386 // ----------------------------------------------------------------------------- 6387 // Field : IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW 6388 #define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_RESET _u(0x0) 6389 #define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) 6390 #define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_MSB _u(24) 6391 #define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_LSB _u(24) 6392 #define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_ACCESS "RW" 6393 // ----------------------------------------------------------------------------- 6394 // Field : IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH 6395 #define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_RESET _u(0x0) 6396 #define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) 6397 #define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_MSB _u(23) 6398 #define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_LSB _u(23) 6399 #define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_ACCESS "RW" 6400 // ----------------------------------------------------------------------------- 6401 // Field : IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW 6402 #define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_RESET _u(0x0) 6403 #define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_BITS _u(0x00400000) 6404 #define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_MSB _u(22) 6405 #define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_LSB _u(22) 6406 #define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_ACCESS "RW" 6407 // ----------------------------------------------------------------------------- 6408 // Field : IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH 6409 #define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_RESET _u(0x0) 6410 #define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) 6411 #define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_MSB _u(21) 6412 #define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_LSB _u(21) 6413 #define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_ACCESS "RW" 6414 // ----------------------------------------------------------------------------- 6415 // Field : IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW 6416 #define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_RESET _u(0x0) 6417 #define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) 6418 #define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_MSB _u(20) 6419 #define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_LSB _u(20) 6420 #define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_ACCESS "RW" 6421 // ----------------------------------------------------------------------------- 6422 // Field : IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH 6423 #define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_RESET _u(0x0) 6424 #define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) 6425 #define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_MSB _u(19) 6426 #define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_LSB _u(19) 6427 #define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_ACCESS "RW" 6428 // ----------------------------------------------------------------------------- 6429 // Field : IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW 6430 #define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_RESET _u(0x0) 6431 #define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_BITS _u(0x00040000) 6432 #define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_MSB _u(18) 6433 #define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_LSB _u(18) 6434 #define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_ACCESS "RW" 6435 // ----------------------------------------------------------------------------- 6436 // Field : IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH 6437 #define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_RESET _u(0x0) 6438 #define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) 6439 #define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_MSB _u(17) 6440 #define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_LSB _u(17) 6441 #define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_ACCESS "RW" 6442 // ----------------------------------------------------------------------------- 6443 // Field : IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW 6444 #define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_RESET _u(0x0) 6445 #define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) 6446 #define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_MSB _u(16) 6447 #define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_LSB _u(16) 6448 #define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_ACCESS "RW" 6449 // ----------------------------------------------------------------------------- 6450 // Field : IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH 6451 #define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_RESET _u(0x0) 6452 #define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) 6453 #define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_MSB _u(15) 6454 #define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_LSB _u(15) 6455 #define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_ACCESS "RW" 6456 // ----------------------------------------------------------------------------- 6457 // Field : IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW 6458 #define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_RESET _u(0x0) 6459 #define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_BITS _u(0x00004000) 6460 #define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_MSB _u(14) 6461 #define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_LSB _u(14) 6462 #define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_ACCESS "RW" 6463 // ----------------------------------------------------------------------------- 6464 // Field : IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH 6465 #define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_RESET _u(0x0) 6466 #define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) 6467 #define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_MSB _u(13) 6468 #define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_LSB _u(13) 6469 #define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_ACCESS "RW" 6470 // ----------------------------------------------------------------------------- 6471 // Field : IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW 6472 #define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_RESET _u(0x0) 6473 #define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) 6474 #define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_MSB _u(12) 6475 #define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_LSB _u(12) 6476 #define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_ACCESS "RW" 6477 // ----------------------------------------------------------------------------- 6478 // Field : IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH 6479 #define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_RESET _u(0x0) 6480 #define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) 6481 #define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_MSB _u(11) 6482 #define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_LSB _u(11) 6483 #define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_ACCESS "RW" 6484 // ----------------------------------------------------------------------------- 6485 // Field : IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW 6486 #define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_RESET _u(0x0) 6487 #define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_BITS _u(0x00000400) 6488 #define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_MSB _u(10) 6489 #define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_LSB _u(10) 6490 #define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_ACCESS "RW" 6491 // ----------------------------------------------------------------------------- 6492 // Field : IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH 6493 #define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_RESET _u(0x0) 6494 #define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) 6495 #define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_MSB _u(9) 6496 #define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_LSB _u(9) 6497 #define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_ACCESS "RW" 6498 // ----------------------------------------------------------------------------- 6499 // Field : IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW 6500 #define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_RESET _u(0x0) 6501 #define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) 6502 #define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_MSB _u(8) 6503 #define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_LSB _u(8) 6504 #define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_ACCESS "RW" 6505 // ----------------------------------------------------------------------------- 6506 // Field : IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH 6507 #define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_RESET _u(0x0) 6508 #define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) 6509 #define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_MSB _u(7) 6510 #define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_LSB _u(7) 6511 #define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_ACCESS "RW" 6512 // ----------------------------------------------------------------------------- 6513 // Field : IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW 6514 #define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_RESET _u(0x0) 6515 #define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_BITS _u(0x00000040) 6516 #define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_MSB _u(6) 6517 #define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_LSB _u(6) 6518 #define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_ACCESS "RW" 6519 // ----------------------------------------------------------------------------- 6520 // Field : IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH 6521 #define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_RESET _u(0x0) 6522 #define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) 6523 #define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_MSB _u(5) 6524 #define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_LSB _u(5) 6525 #define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_ACCESS "RW" 6526 // ----------------------------------------------------------------------------- 6527 // Field : IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW 6528 #define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_RESET _u(0x0) 6529 #define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) 6530 #define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_MSB _u(4) 6531 #define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_LSB _u(4) 6532 #define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_ACCESS "RW" 6533 // ----------------------------------------------------------------------------- 6534 // Field : IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH 6535 #define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_RESET _u(0x0) 6536 #define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) 6537 #define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_MSB _u(3) 6538 #define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_LSB _u(3) 6539 #define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_ACCESS "RW" 6540 // ----------------------------------------------------------------------------- 6541 // Field : IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW 6542 #define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_RESET _u(0x0) 6543 #define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_BITS _u(0x00000004) 6544 #define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_MSB _u(2) 6545 #define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_LSB _u(2) 6546 #define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_ACCESS "RW" 6547 // ----------------------------------------------------------------------------- 6548 // Field : IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH 6549 #define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_RESET _u(0x0) 6550 #define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) 6551 #define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_MSB _u(1) 6552 #define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_LSB _u(1) 6553 #define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_ACCESS "RW" 6554 // ----------------------------------------------------------------------------- 6555 // Field : IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW 6556 #define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_RESET _u(0x0) 6557 #define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) 6558 #define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_MSB _u(0) 6559 #define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_LSB _u(0) 6560 #define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_ACCESS "RW" 6561 // ============================================================================= 6562 // Register : IO_BANK0_PROC0_INTE3 6563 // Description : Interrupt Enable for proc0 6564 #define IO_BANK0_PROC0_INTE3_OFFSET _u(0x0000010c) 6565 #define IO_BANK0_PROC0_INTE3_BITS _u(0x00ffffff) 6566 #define IO_BANK0_PROC0_INTE3_RESET _u(0x00000000) 6567 // ----------------------------------------------------------------------------- 6568 // Field : IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH 6569 #define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_RESET _u(0x0) 6570 #define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) 6571 #define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_MSB _u(23) 6572 #define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_LSB _u(23) 6573 #define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_ACCESS "RW" 6574 // ----------------------------------------------------------------------------- 6575 // Field : IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW 6576 #define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_RESET _u(0x0) 6577 #define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_BITS _u(0x00400000) 6578 #define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_MSB _u(22) 6579 #define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_LSB _u(22) 6580 #define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_ACCESS "RW" 6581 // ----------------------------------------------------------------------------- 6582 // Field : IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH 6583 #define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_RESET _u(0x0) 6584 #define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) 6585 #define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_MSB _u(21) 6586 #define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_LSB _u(21) 6587 #define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_ACCESS "RW" 6588 // ----------------------------------------------------------------------------- 6589 // Field : IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW 6590 #define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_RESET _u(0x0) 6591 #define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) 6592 #define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_MSB _u(20) 6593 #define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_LSB _u(20) 6594 #define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_ACCESS "RW" 6595 // ----------------------------------------------------------------------------- 6596 // Field : IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH 6597 #define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_RESET _u(0x0) 6598 #define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) 6599 #define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_MSB _u(19) 6600 #define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_LSB _u(19) 6601 #define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_ACCESS "RW" 6602 // ----------------------------------------------------------------------------- 6603 // Field : IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW 6604 #define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_RESET _u(0x0) 6605 #define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_BITS _u(0x00040000) 6606 #define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_MSB _u(18) 6607 #define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_LSB _u(18) 6608 #define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_ACCESS "RW" 6609 // ----------------------------------------------------------------------------- 6610 // Field : IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH 6611 #define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_RESET _u(0x0) 6612 #define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) 6613 #define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_MSB _u(17) 6614 #define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_LSB _u(17) 6615 #define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_ACCESS "RW" 6616 // ----------------------------------------------------------------------------- 6617 // Field : IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW 6618 #define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_RESET _u(0x0) 6619 #define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) 6620 #define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_MSB _u(16) 6621 #define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_LSB _u(16) 6622 #define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_ACCESS "RW" 6623 // ----------------------------------------------------------------------------- 6624 // Field : IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH 6625 #define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_RESET _u(0x0) 6626 #define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) 6627 #define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_MSB _u(15) 6628 #define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_LSB _u(15) 6629 #define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_ACCESS "RW" 6630 // ----------------------------------------------------------------------------- 6631 // Field : IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW 6632 #define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_RESET _u(0x0) 6633 #define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_BITS _u(0x00004000) 6634 #define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_MSB _u(14) 6635 #define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_LSB _u(14) 6636 #define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_ACCESS "RW" 6637 // ----------------------------------------------------------------------------- 6638 // Field : IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH 6639 #define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_RESET _u(0x0) 6640 #define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) 6641 #define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_MSB _u(13) 6642 #define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_LSB _u(13) 6643 #define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_ACCESS "RW" 6644 // ----------------------------------------------------------------------------- 6645 // Field : IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW 6646 #define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_RESET _u(0x0) 6647 #define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) 6648 #define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_MSB _u(12) 6649 #define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_LSB _u(12) 6650 #define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_ACCESS "RW" 6651 // ----------------------------------------------------------------------------- 6652 // Field : IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH 6653 #define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_RESET _u(0x0) 6654 #define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) 6655 #define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_MSB _u(11) 6656 #define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_LSB _u(11) 6657 #define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_ACCESS "RW" 6658 // ----------------------------------------------------------------------------- 6659 // Field : IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW 6660 #define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_RESET _u(0x0) 6661 #define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_BITS _u(0x00000400) 6662 #define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_MSB _u(10) 6663 #define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_LSB _u(10) 6664 #define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_ACCESS "RW" 6665 // ----------------------------------------------------------------------------- 6666 // Field : IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH 6667 #define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_RESET _u(0x0) 6668 #define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) 6669 #define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_MSB _u(9) 6670 #define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_LSB _u(9) 6671 #define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_ACCESS "RW" 6672 // ----------------------------------------------------------------------------- 6673 // Field : IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW 6674 #define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_RESET _u(0x0) 6675 #define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) 6676 #define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_MSB _u(8) 6677 #define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_LSB _u(8) 6678 #define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_ACCESS "RW" 6679 // ----------------------------------------------------------------------------- 6680 // Field : IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH 6681 #define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_RESET _u(0x0) 6682 #define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) 6683 #define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_MSB _u(7) 6684 #define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_LSB _u(7) 6685 #define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_ACCESS "RW" 6686 // ----------------------------------------------------------------------------- 6687 // Field : IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW 6688 #define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_RESET _u(0x0) 6689 #define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_BITS _u(0x00000040) 6690 #define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_MSB _u(6) 6691 #define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_LSB _u(6) 6692 #define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_ACCESS "RW" 6693 // ----------------------------------------------------------------------------- 6694 // Field : IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH 6695 #define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_RESET _u(0x0) 6696 #define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) 6697 #define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_MSB _u(5) 6698 #define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_LSB _u(5) 6699 #define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_ACCESS "RW" 6700 // ----------------------------------------------------------------------------- 6701 // Field : IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW 6702 #define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_RESET _u(0x0) 6703 #define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) 6704 #define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_MSB _u(4) 6705 #define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_LSB _u(4) 6706 #define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_ACCESS "RW" 6707 // ----------------------------------------------------------------------------- 6708 // Field : IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH 6709 #define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_RESET _u(0x0) 6710 #define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) 6711 #define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_MSB _u(3) 6712 #define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_LSB _u(3) 6713 #define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_ACCESS "RW" 6714 // ----------------------------------------------------------------------------- 6715 // Field : IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW 6716 #define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_RESET _u(0x0) 6717 #define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_BITS _u(0x00000004) 6718 #define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_MSB _u(2) 6719 #define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_LSB _u(2) 6720 #define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_ACCESS "RW" 6721 // ----------------------------------------------------------------------------- 6722 // Field : IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH 6723 #define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_RESET _u(0x0) 6724 #define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) 6725 #define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_MSB _u(1) 6726 #define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_LSB _u(1) 6727 #define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_ACCESS "RW" 6728 // ----------------------------------------------------------------------------- 6729 // Field : IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW 6730 #define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_RESET _u(0x0) 6731 #define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) 6732 #define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_MSB _u(0) 6733 #define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_LSB _u(0) 6734 #define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_ACCESS "RW" 6735 // ============================================================================= 6736 // Register : IO_BANK0_PROC0_INTF0 6737 // Description : Interrupt Force for proc0 6738 #define IO_BANK0_PROC0_INTF0_OFFSET _u(0x00000110) 6739 #define IO_BANK0_PROC0_INTF0_BITS _u(0xffffffff) 6740 #define IO_BANK0_PROC0_INTF0_RESET _u(0x00000000) 6741 // ----------------------------------------------------------------------------- 6742 // Field : IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH 6743 #define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_RESET _u(0x0) 6744 #define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) 6745 #define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_MSB _u(31) 6746 #define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_LSB _u(31) 6747 #define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_ACCESS "RW" 6748 // ----------------------------------------------------------------------------- 6749 // Field : IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW 6750 #define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_RESET _u(0x0) 6751 #define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_BITS _u(0x40000000) 6752 #define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_MSB _u(30) 6753 #define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_LSB _u(30) 6754 #define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_ACCESS "RW" 6755 // ----------------------------------------------------------------------------- 6756 // Field : IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH 6757 #define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_RESET _u(0x0) 6758 #define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) 6759 #define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_MSB _u(29) 6760 #define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_LSB _u(29) 6761 #define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_ACCESS "RW" 6762 // ----------------------------------------------------------------------------- 6763 // Field : IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW 6764 #define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_RESET _u(0x0) 6765 #define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) 6766 #define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_MSB _u(28) 6767 #define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_LSB _u(28) 6768 #define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_ACCESS "RW" 6769 // ----------------------------------------------------------------------------- 6770 // Field : IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH 6771 #define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_RESET _u(0x0) 6772 #define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) 6773 #define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_MSB _u(27) 6774 #define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_LSB _u(27) 6775 #define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_ACCESS "RW" 6776 // ----------------------------------------------------------------------------- 6777 // Field : IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW 6778 #define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_RESET _u(0x0) 6779 #define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_BITS _u(0x04000000) 6780 #define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_MSB _u(26) 6781 #define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_LSB _u(26) 6782 #define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_ACCESS "RW" 6783 // ----------------------------------------------------------------------------- 6784 // Field : IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH 6785 #define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_RESET _u(0x0) 6786 #define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) 6787 #define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_MSB _u(25) 6788 #define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_LSB _u(25) 6789 #define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_ACCESS "RW" 6790 // ----------------------------------------------------------------------------- 6791 // Field : IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW 6792 #define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_RESET _u(0x0) 6793 #define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) 6794 #define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_MSB _u(24) 6795 #define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_LSB _u(24) 6796 #define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_ACCESS "RW" 6797 // ----------------------------------------------------------------------------- 6798 // Field : IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH 6799 #define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_RESET _u(0x0) 6800 #define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) 6801 #define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_MSB _u(23) 6802 #define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_LSB _u(23) 6803 #define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_ACCESS "RW" 6804 // ----------------------------------------------------------------------------- 6805 // Field : IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW 6806 #define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_RESET _u(0x0) 6807 #define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_BITS _u(0x00400000) 6808 #define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_MSB _u(22) 6809 #define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_LSB _u(22) 6810 #define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_ACCESS "RW" 6811 // ----------------------------------------------------------------------------- 6812 // Field : IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH 6813 #define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_RESET _u(0x0) 6814 #define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) 6815 #define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_MSB _u(21) 6816 #define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_LSB _u(21) 6817 #define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_ACCESS "RW" 6818 // ----------------------------------------------------------------------------- 6819 // Field : IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW 6820 #define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_RESET _u(0x0) 6821 #define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) 6822 #define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_MSB _u(20) 6823 #define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_LSB _u(20) 6824 #define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_ACCESS "RW" 6825 // ----------------------------------------------------------------------------- 6826 // Field : IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH 6827 #define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_RESET _u(0x0) 6828 #define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) 6829 #define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_MSB _u(19) 6830 #define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_LSB _u(19) 6831 #define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_ACCESS "RW" 6832 // ----------------------------------------------------------------------------- 6833 // Field : IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW 6834 #define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_RESET _u(0x0) 6835 #define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_BITS _u(0x00040000) 6836 #define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_MSB _u(18) 6837 #define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_LSB _u(18) 6838 #define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_ACCESS "RW" 6839 // ----------------------------------------------------------------------------- 6840 // Field : IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH 6841 #define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_RESET _u(0x0) 6842 #define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) 6843 #define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_MSB _u(17) 6844 #define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_LSB _u(17) 6845 #define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_ACCESS "RW" 6846 // ----------------------------------------------------------------------------- 6847 // Field : IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW 6848 #define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_RESET _u(0x0) 6849 #define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) 6850 #define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_MSB _u(16) 6851 #define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_LSB _u(16) 6852 #define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_ACCESS "RW" 6853 // ----------------------------------------------------------------------------- 6854 // Field : IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH 6855 #define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_RESET _u(0x0) 6856 #define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) 6857 #define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_MSB _u(15) 6858 #define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_LSB _u(15) 6859 #define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_ACCESS "RW" 6860 // ----------------------------------------------------------------------------- 6861 // Field : IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW 6862 #define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_RESET _u(0x0) 6863 #define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_BITS _u(0x00004000) 6864 #define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_MSB _u(14) 6865 #define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_LSB _u(14) 6866 #define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_ACCESS "RW" 6867 // ----------------------------------------------------------------------------- 6868 // Field : IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH 6869 #define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_RESET _u(0x0) 6870 #define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) 6871 #define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_MSB _u(13) 6872 #define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_LSB _u(13) 6873 #define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_ACCESS "RW" 6874 // ----------------------------------------------------------------------------- 6875 // Field : IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW 6876 #define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_RESET _u(0x0) 6877 #define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) 6878 #define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_MSB _u(12) 6879 #define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_LSB _u(12) 6880 #define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_ACCESS "RW" 6881 // ----------------------------------------------------------------------------- 6882 // Field : IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH 6883 #define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_RESET _u(0x0) 6884 #define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) 6885 #define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_MSB _u(11) 6886 #define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_LSB _u(11) 6887 #define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_ACCESS "RW" 6888 // ----------------------------------------------------------------------------- 6889 // Field : IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW 6890 #define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_RESET _u(0x0) 6891 #define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_BITS _u(0x00000400) 6892 #define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_MSB _u(10) 6893 #define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_LSB _u(10) 6894 #define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_ACCESS "RW" 6895 // ----------------------------------------------------------------------------- 6896 // Field : IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH 6897 #define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_RESET _u(0x0) 6898 #define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) 6899 #define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_MSB _u(9) 6900 #define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_LSB _u(9) 6901 #define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_ACCESS "RW" 6902 // ----------------------------------------------------------------------------- 6903 // Field : IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW 6904 #define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_RESET _u(0x0) 6905 #define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) 6906 #define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_MSB _u(8) 6907 #define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_LSB _u(8) 6908 #define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_ACCESS "RW" 6909 // ----------------------------------------------------------------------------- 6910 // Field : IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH 6911 #define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_RESET _u(0x0) 6912 #define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) 6913 #define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_MSB _u(7) 6914 #define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_LSB _u(7) 6915 #define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_ACCESS "RW" 6916 // ----------------------------------------------------------------------------- 6917 // Field : IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW 6918 #define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_RESET _u(0x0) 6919 #define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_BITS _u(0x00000040) 6920 #define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_MSB _u(6) 6921 #define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_LSB _u(6) 6922 #define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_ACCESS "RW" 6923 // ----------------------------------------------------------------------------- 6924 // Field : IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH 6925 #define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_RESET _u(0x0) 6926 #define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) 6927 #define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_MSB _u(5) 6928 #define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_LSB _u(5) 6929 #define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_ACCESS "RW" 6930 // ----------------------------------------------------------------------------- 6931 // Field : IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW 6932 #define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_RESET _u(0x0) 6933 #define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) 6934 #define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_MSB _u(4) 6935 #define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_LSB _u(4) 6936 #define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_ACCESS "RW" 6937 // ----------------------------------------------------------------------------- 6938 // Field : IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH 6939 #define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_RESET _u(0x0) 6940 #define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) 6941 #define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_MSB _u(3) 6942 #define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_LSB _u(3) 6943 #define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_ACCESS "RW" 6944 // ----------------------------------------------------------------------------- 6945 // Field : IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW 6946 #define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_RESET _u(0x0) 6947 #define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_BITS _u(0x00000004) 6948 #define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_MSB _u(2) 6949 #define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_LSB _u(2) 6950 #define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_ACCESS "RW" 6951 // ----------------------------------------------------------------------------- 6952 // Field : IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH 6953 #define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_RESET _u(0x0) 6954 #define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) 6955 #define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_MSB _u(1) 6956 #define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_LSB _u(1) 6957 #define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_ACCESS "RW" 6958 // ----------------------------------------------------------------------------- 6959 // Field : IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW 6960 #define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_RESET _u(0x0) 6961 #define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) 6962 #define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_MSB _u(0) 6963 #define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_LSB _u(0) 6964 #define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_ACCESS "RW" 6965 // ============================================================================= 6966 // Register : IO_BANK0_PROC0_INTF1 6967 // Description : Interrupt Force for proc0 6968 #define IO_BANK0_PROC0_INTF1_OFFSET _u(0x00000114) 6969 #define IO_BANK0_PROC0_INTF1_BITS _u(0xffffffff) 6970 #define IO_BANK0_PROC0_INTF1_RESET _u(0x00000000) 6971 // ----------------------------------------------------------------------------- 6972 // Field : IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH 6973 #define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_RESET _u(0x0) 6974 #define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) 6975 #define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_MSB _u(31) 6976 #define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_LSB _u(31) 6977 #define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_ACCESS "RW" 6978 // ----------------------------------------------------------------------------- 6979 // Field : IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW 6980 #define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_RESET _u(0x0) 6981 #define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_BITS _u(0x40000000) 6982 #define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_MSB _u(30) 6983 #define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_LSB _u(30) 6984 #define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_ACCESS "RW" 6985 // ----------------------------------------------------------------------------- 6986 // Field : IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH 6987 #define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_RESET _u(0x0) 6988 #define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) 6989 #define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_MSB _u(29) 6990 #define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_LSB _u(29) 6991 #define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_ACCESS "RW" 6992 // ----------------------------------------------------------------------------- 6993 // Field : IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW 6994 #define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_RESET _u(0x0) 6995 #define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) 6996 #define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_MSB _u(28) 6997 #define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_LSB _u(28) 6998 #define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_ACCESS "RW" 6999 // ----------------------------------------------------------------------------- 7000 // Field : IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH 7001 #define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_RESET _u(0x0) 7002 #define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) 7003 #define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_MSB _u(27) 7004 #define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_LSB _u(27) 7005 #define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_ACCESS "RW" 7006 // ----------------------------------------------------------------------------- 7007 // Field : IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW 7008 #define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_RESET _u(0x0) 7009 #define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_BITS _u(0x04000000) 7010 #define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_MSB _u(26) 7011 #define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_LSB _u(26) 7012 #define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_ACCESS "RW" 7013 // ----------------------------------------------------------------------------- 7014 // Field : IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH 7015 #define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_RESET _u(0x0) 7016 #define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) 7017 #define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_MSB _u(25) 7018 #define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_LSB _u(25) 7019 #define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_ACCESS "RW" 7020 // ----------------------------------------------------------------------------- 7021 // Field : IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW 7022 #define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_RESET _u(0x0) 7023 #define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) 7024 #define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_MSB _u(24) 7025 #define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_LSB _u(24) 7026 #define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_ACCESS "RW" 7027 // ----------------------------------------------------------------------------- 7028 // Field : IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH 7029 #define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_RESET _u(0x0) 7030 #define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) 7031 #define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_MSB _u(23) 7032 #define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_LSB _u(23) 7033 #define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_ACCESS "RW" 7034 // ----------------------------------------------------------------------------- 7035 // Field : IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW 7036 #define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_RESET _u(0x0) 7037 #define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_BITS _u(0x00400000) 7038 #define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_MSB _u(22) 7039 #define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_LSB _u(22) 7040 #define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_ACCESS "RW" 7041 // ----------------------------------------------------------------------------- 7042 // Field : IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH 7043 #define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_RESET _u(0x0) 7044 #define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) 7045 #define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_MSB _u(21) 7046 #define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_LSB _u(21) 7047 #define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_ACCESS "RW" 7048 // ----------------------------------------------------------------------------- 7049 // Field : IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW 7050 #define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_RESET _u(0x0) 7051 #define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) 7052 #define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_MSB _u(20) 7053 #define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_LSB _u(20) 7054 #define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_ACCESS "RW" 7055 // ----------------------------------------------------------------------------- 7056 // Field : IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH 7057 #define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_RESET _u(0x0) 7058 #define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) 7059 #define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_MSB _u(19) 7060 #define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_LSB _u(19) 7061 #define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_ACCESS "RW" 7062 // ----------------------------------------------------------------------------- 7063 // Field : IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW 7064 #define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_RESET _u(0x0) 7065 #define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_BITS _u(0x00040000) 7066 #define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_MSB _u(18) 7067 #define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_LSB _u(18) 7068 #define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_ACCESS "RW" 7069 // ----------------------------------------------------------------------------- 7070 // Field : IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH 7071 #define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_RESET _u(0x0) 7072 #define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) 7073 #define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_MSB _u(17) 7074 #define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_LSB _u(17) 7075 #define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_ACCESS "RW" 7076 // ----------------------------------------------------------------------------- 7077 // Field : IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW 7078 #define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_RESET _u(0x0) 7079 #define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) 7080 #define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_MSB _u(16) 7081 #define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_LSB _u(16) 7082 #define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_ACCESS "RW" 7083 // ----------------------------------------------------------------------------- 7084 // Field : IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH 7085 #define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_RESET _u(0x0) 7086 #define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) 7087 #define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_MSB _u(15) 7088 #define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_LSB _u(15) 7089 #define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_ACCESS "RW" 7090 // ----------------------------------------------------------------------------- 7091 // Field : IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW 7092 #define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_RESET _u(0x0) 7093 #define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_BITS _u(0x00004000) 7094 #define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_MSB _u(14) 7095 #define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_LSB _u(14) 7096 #define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_ACCESS "RW" 7097 // ----------------------------------------------------------------------------- 7098 // Field : IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH 7099 #define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_RESET _u(0x0) 7100 #define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) 7101 #define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_MSB _u(13) 7102 #define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_LSB _u(13) 7103 #define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_ACCESS "RW" 7104 // ----------------------------------------------------------------------------- 7105 // Field : IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW 7106 #define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_RESET _u(0x0) 7107 #define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) 7108 #define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_MSB _u(12) 7109 #define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_LSB _u(12) 7110 #define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_ACCESS "RW" 7111 // ----------------------------------------------------------------------------- 7112 // Field : IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH 7113 #define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_RESET _u(0x0) 7114 #define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) 7115 #define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_MSB _u(11) 7116 #define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_LSB _u(11) 7117 #define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_ACCESS "RW" 7118 // ----------------------------------------------------------------------------- 7119 // Field : IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW 7120 #define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_RESET _u(0x0) 7121 #define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_BITS _u(0x00000400) 7122 #define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_MSB _u(10) 7123 #define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_LSB _u(10) 7124 #define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_ACCESS "RW" 7125 // ----------------------------------------------------------------------------- 7126 // Field : IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH 7127 #define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_RESET _u(0x0) 7128 #define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) 7129 #define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_MSB _u(9) 7130 #define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_LSB _u(9) 7131 #define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_ACCESS "RW" 7132 // ----------------------------------------------------------------------------- 7133 // Field : IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW 7134 #define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_RESET _u(0x0) 7135 #define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) 7136 #define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_MSB _u(8) 7137 #define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_LSB _u(8) 7138 #define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_ACCESS "RW" 7139 // ----------------------------------------------------------------------------- 7140 // Field : IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH 7141 #define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_RESET _u(0x0) 7142 #define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) 7143 #define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_MSB _u(7) 7144 #define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_LSB _u(7) 7145 #define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_ACCESS "RW" 7146 // ----------------------------------------------------------------------------- 7147 // Field : IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW 7148 #define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_RESET _u(0x0) 7149 #define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_BITS _u(0x00000040) 7150 #define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_MSB _u(6) 7151 #define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_LSB _u(6) 7152 #define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_ACCESS "RW" 7153 // ----------------------------------------------------------------------------- 7154 // Field : IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH 7155 #define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_RESET _u(0x0) 7156 #define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) 7157 #define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_MSB _u(5) 7158 #define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_LSB _u(5) 7159 #define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_ACCESS "RW" 7160 // ----------------------------------------------------------------------------- 7161 // Field : IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW 7162 #define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_RESET _u(0x0) 7163 #define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) 7164 #define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_MSB _u(4) 7165 #define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_LSB _u(4) 7166 #define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_ACCESS "RW" 7167 // ----------------------------------------------------------------------------- 7168 // Field : IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH 7169 #define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_RESET _u(0x0) 7170 #define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) 7171 #define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_MSB _u(3) 7172 #define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_LSB _u(3) 7173 #define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_ACCESS "RW" 7174 // ----------------------------------------------------------------------------- 7175 // Field : IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW 7176 #define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_RESET _u(0x0) 7177 #define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_BITS _u(0x00000004) 7178 #define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_MSB _u(2) 7179 #define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_LSB _u(2) 7180 #define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_ACCESS "RW" 7181 // ----------------------------------------------------------------------------- 7182 // Field : IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH 7183 #define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_RESET _u(0x0) 7184 #define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) 7185 #define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_MSB _u(1) 7186 #define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_LSB _u(1) 7187 #define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_ACCESS "RW" 7188 // ----------------------------------------------------------------------------- 7189 // Field : IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW 7190 #define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_RESET _u(0x0) 7191 #define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) 7192 #define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_MSB _u(0) 7193 #define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_LSB _u(0) 7194 #define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_ACCESS "RW" 7195 // ============================================================================= 7196 // Register : IO_BANK0_PROC0_INTF2 7197 // Description : Interrupt Force for proc0 7198 #define IO_BANK0_PROC0_INTF2_OFFSET _u(0x00000118) 7199 #define IO_BANK0_PROC0_INTF2_BITS _u(0xffffffff) 7200 #define IO_BANK0_PROC0_INTF2_RESET _u(0x00000000) 7201 // ----------------------------------------------------------------------------- 7202 // Field : IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH 7203 #define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_RESET _u(0x0) 7204 #define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) 7205 #define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_MSB _u(31) 7206 #define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_LSB _u(31) 7207 #define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_ACCESS "RW" 7208 // ----------------------------------------------------------------------------- 7209 // Field : IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW 7210 #define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_RESET _u(0x0) 7211 #define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_BITS _u(0x40000000) 7212 #define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_MSB _u(30) 7213 #define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_LSB _u(30) 7214 #define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_ACCESS "RW" 7215 // ----------------------------------------------------------------------------- 7216 // Field : IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH 7217 #define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_RESET _u(0x0) 7218 #define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) 7219 #define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_MSB _u(29) 7220 #define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_LSB _u(29) 7221 #define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_ACCESS "RW" 7222 // ----------------------------------------------------------------------------- 7223 // Field : IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW 7224 #define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_RESET _u(0x0) 7225 #define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) 7226 #define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_MSB _u(28) 7227 #define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_LSB _u(28) 7228 #define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_ACCESS "RW" 7229 // ----------------------------------------------------------------------------- 7230 // Field : IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH 7231 #define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_RESET _u(0x0) 7232 #define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) 7233 #define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_MSB _u(27) 7234 #define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_LSB _u(27) 7235 #define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_ACCESS "RW" 7236 // ----------------------------------------------------------------------------- 7237 // Field : IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW 7238 #define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_RESET _u(0x0) 7239 #define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_BITS _u(0x04000000) 7240 #define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_MSB _u(26) 7241 #define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_LSB _u(26) 7242 #define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_ACCESS "RW" 7243 // ----------------------------------------------------------------------------- 7244 // Field : IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH 7245 #define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_RESET _u(0x0) 7246 #define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) 7247 #define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_MSB _u(25) 7248 #define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_LSB _u(25) 7249 #define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_ACCESS "RW" 7250 // ----------------------------------------------------------------------------- 7251 // Field : IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW 7252 #define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_RESET _u(0x0) 7253 #define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) 7254 #define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_MSB _u(24) 7255 #define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_LSB _u(24) 7256 #define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_ACCESS "RW" 7257 // ----------------------------------------------------------------------------- 7258 // Field : IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH 7259 #define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_RESET _u(0x0) 7260 #define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) 7261 #define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_MSB _u(23) 7262 #define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_LSB _u(23) 7263 #define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_ACCESS "RW" 7264 // ----------------------------------------------------------------------------- 7265 // Field : IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW 7266 #define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_RESET _u(0x0) 7267 #define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_BITS _u(0x00400000) 7268 #define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_MSB _u(22) 7269 #define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_LSB _u(22) 7270 #define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_ACCESS "RW" 7271 // ----------------------------------------------------------------------------- 7272 // Field : IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH 7273 #define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_RESET _u(0x0) 7274 #define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) 7275 #define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_MSB _u(21) 7276 #define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_LSB _u(21) 7277 #define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_ACCESS "RW" 7278 // ----------------------------------------------------------------------------- 7279 // Field : IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW 7280 #define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_RESET _u(0x0) 7281 #define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) 7282 #define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_MSB _u(20) 7283 #define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_LSB _u(20) 7284 #define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_ACCESS "RW" 7285 // ----------------------------------------------------------------------------- 7286 // Field : IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH 7287 #define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_RESET _u(0x0) 7288 #define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) 7289 #define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_MSB _u(19) 7290 #define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_LSB _u(19) 7291 #define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_ACCESS "RW" 7292 // ----------------------------------------------------------------------------- 7293 // Field : IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW 7294 #define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_RESET _u(0x0) 7295 #define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_BITS _u(0x00040000) 7296 #define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_MSB _u(18) 7297 #define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_LSB _u(18) 7298 #define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_ACCESS "RW" 7299 // ----------------------------------------------------------------------------- 7300 // Field : IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH 7301 #define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_RESET _u(0x0) 7302 #define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) 7303 #define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_MSB _u(17) 7304 #define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_LSB _u(17) 7305 #define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_ACCESS "RW" 7306 // ----------------------------------------------------------------------------- 7307 // Field : IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW 7308 #define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_RESET _u(0x0) 7309 #define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) 7310 #define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_MSB _u(16) 7311 #define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_LSB _u(16) 7312 #define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_ACCESS "RW" 7313 // ----------------------------------------------------------------------------- 7314 // Field : IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH 7315 #define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_RESET _u(0x0) 7316 #define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) 7317 #define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_MSB _u(15) 7318 #define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_LSB _u(15) 7319 #define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_ACCESS "RW" 7320 // ----------------------------------------------------------------------------- 7321 // Field : IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW 7322 #define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_RESET _u(0x0) 7323 #define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_BITS _u(0x00004000) 7324 #define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_MSB _u(14) 7325 #define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_LSB _u(14) 7326 #define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_ACCESS "RW" 7327 // ----------------------------------------------------------------------------- 7328 // Field : IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH 7329 #define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_RESET _u(0x0) 7330 #define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) 7331 #define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_MSB _u(13) 7332 #define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_LSB _u(13) 7333 #define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_ACCESS "RW" 7334 // ----------------------------------------------------------------------------- 7335 // Field : IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW 7336 #define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_RESET _u(0x0) 7337 #define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) 7338 #define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_MSB _u(12) 7339 #define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_LSB _u(12) 7340 #define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_ACCESS "RW" 7341 // ----------------------------------------------------------------------------- 7342 // Field : IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH 7343 #define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_RESET _u(0x0) 7344 #define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) 7345 #define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_MSB _u(11) 7346 #define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_LSB _u(11) 7347 #define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_ACCESS "RW" 7348 // ----------------------------------------------------------------------------- 7349 // Field : IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW 7350 #define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_RESET _u(0x0) 7351 #define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_BITS _u(0x00000400) 7352 #define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_MSB _u(10) 7353 #define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_LSB _u(10) 7354 #define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_ACCESS "RW" 7355 // ----------------------------------------------------------------------------- 7356 // Field : IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH 7357 #define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_RESET _u(0x0) 7358 #define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) 7359 #define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_MSB _u(9) 7360 #define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_LSB _u(9) 7361 #define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_ACCESS "RW" 7362 // ----------------------------------------------------------------------------- 7363 // Field : IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW 7364 #define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_RESET _u(0x0) 7365 #define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) 7366 #define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_MSB _u(8) 7367 #define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_LSB _u(8) 7368 #define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_ACCESS "RW" 7369 // ----------------------------------------------------------------------------- 7370 // Field : IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH 7371 #define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_RESET _u(0x0) 7372 #define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) 7373 #define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_MSB _u(7) 7374 #define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_LSB _u(7) 7375 #define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_ACCESS "RW" 7376 // ----------------------------------------------------------------------------- 7377 // Field : IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW 7378 #define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_RESET _u(0x0) 7379 #define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_BITS _u(0x00000040) 7380 #define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_MSB _u(6) 7381 #define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_LSB _u(6) 7382 #define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_ACCESS "RW" 7383 // ----------------------------------------------------------------------------- 7384 // Field : IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH 7385 #define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_RESET _u(0x0) 7386 #define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) 7387 #define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_MSB _u(5) 7388 #define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_LSB _u(5) 7389 #define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_ACCESS "RW" 7390 // ----------------------------------------------------------------------------- 7391 // Field : IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW 7392 #define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_RESET _u(0x0) 7393 #define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) 7394 #define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_MSB _u(4) 7395 #define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_LSB _u(4) 7396 #define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_ACCESS "RW" 7397 // ----------------------------------------------------------------------------- 7398 // Field : IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH 7399 #define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_RESET _u(0x0) 7400 #define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) 7401 #define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_MSB _u(3) 7402 #define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_LSB _u(3) 7403 #define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_ACCESS "RW" 7404 // ----------------------------------------------------------------------------- 7405 // Field : IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW 7406 #define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_RESET _u(0x0) 7407 #define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_BITS _u(0x00000004) 7408 #define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_MSB _u(2) 7409 #define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_LSB _u(2) 7410 #define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_ACCESS "RW" 7411 // ----------------------------------------------------------------------------- 7412 // Field : IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH 7413 #define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_RESET _u(0x0) 7414 #define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) 7415 #define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_MSB _u(1) 7416 #define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_LSB _u(1) 7417 #define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_ACCESS "RW" 7418 // ----------------------------------------------------------------------------- 7419 // Field : IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW 7420 #define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_RESET _u(0x0) 7421 #define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) 7422 #define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_MSB _u(0) 7423 #define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_LSB _u(0) 7424 #define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_ACCESS "RW" 7425 // ============================================================================= 7426 // Register : IO_BANK0_PROC0_INTF3 7427 // Description : Interrupt Force for proc0 7428 #define IO_BANK0_PROC0_INTF3_OFFSET _u(0x0000011c) 7429 #define IO_BANK0_PROC0_INTF3_BITS _u(0x00ffffff) 7430 #define IO_BANK0_PROC0_INTF3_RESET _u(0x00000000) 7431 // ----------------------------------------------------------------------------- 7432 // Field : IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH 7433 #define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_RESET _u(0x0) 7434 #define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) 7435 #define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_MSB _u(23) 7436 #define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_LSB _u(23) 7437 #define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_ACCESS "RW" 7438 // ----------------------------------------------------------------------------- 7439 // Field : IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW 7440 #define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_RESET _u(0x0) 7441 #define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_BITS _u(0x00400000) 7442 #define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_MSB _u(22) 7443 #define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_LSB _u(22) 7444 #define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_ACCESS "RW" 7445 // ----------------------------------------------------------------------------- 7446 // Field : IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH 7447 #define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_RESET _u(0x0) 7448 #define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) 7449 #define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_MSB _u(21) 7450 #define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_LSB _u(21) 7451 #define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_ACCESS "RW" 7452 // ----------------------------------------------------------------------------- 7453 // Field : IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW 7454 #define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_RESET _u(0x0) 7455 #define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) 7456 #define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_MSB _u(20) 7457 #define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_LSB _u(20) 7458 #define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_ACCESS "RW" 7459 // ----------------------------------------------------------------------------- 7460 // Field : IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH 7461 #define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_RESET _u(0x0) 7462 #define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) 7463 #define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_MSB _u(19) 7464 #define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_LSB _u(19) 7465 #define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_ACCESS "RW" 7466 // ----------------------------------------------------------------------------- 7467 // Field : IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW 7468 #define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_RESET _u(0x0) 7469 #define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_BITS _u(0x00040000) 7470 #define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_MSB _u(18) 7471 #define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_LSB _u(18) 7472 #define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_ACCESS "RW" 7473 // ----------------------------------------------------------------------------- 7474 // Field : IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH 7475 #define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_RESET _u(0x0) 7476 #define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) 7477 #define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_MSB _u(17) 7478 #define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_LSB _u(17) 7479 #define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_ACCESS "RW" 7480 // ----------------------------------------------------------------------------- 7481 // Field : IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW 7482 #define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_RESET _u(0x0) 7483 #define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) 7484 #define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_MSB _u(16) 7485 #define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_LSB _u(16) 7486 #define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_ACCESS "RW" 7487 // ----------------------------------------------------------------------------- 7488 // Field : IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH 7489 #define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_RESET _u(0x0) 7490 #define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) 7491 #define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_MSB _u(15) 7492 #define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_LSB _u(15) 7493 #define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_ACCESS "RW" 7494 // ----------------------------------------------------------------------------- 7495 // Field : IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW 7496 #define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_RESET _u(0x0) 7497 #define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_BITS _u(0x00004000) 7498 #define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_MSB _u(14) 7499 #define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_LSB _u(14) 7500 #define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_ACCESS "RW" 7501 // ----------------------------------------------------------------------------- 7502 // Field : IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH 7503 #define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_RESET _u(0x0) 7504 #define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) 7505 #define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_MSB _u(13) 7506 #define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_LSB _u(13) 7507 #define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_ACCESS "RW" 7508 // ----------------------------------------------------------------------------- 7509 // Field : IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW 7510 #define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_RESET _u(0x0) 7511 #define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) 7512 #define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_MSB _u(12) 7513 #define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_LSB _u(12) 7514 #define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_ACCESS "RW" 7515 // ----------------------------------------------------------------------------- 7516 // Field : IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH 7517 #define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_RESET _u(0x0) 7518 #define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) 7519 #define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_MSB _u(11) 7520 #define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_LSB _u(11) 7521 #define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_ACCESS "RW" 7522 // ----------------------------------------------------------------------------- 7523 // Field : IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW 7524 #define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_RESET _u(0x0) 7525 #define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_BITS _u(0x00000400) 7526 #define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_MSB _u(10) 7527 #define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_LSB _u(10) 7528 #define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_ACCESS "RW" 7529 // ----------------------------------------------------------------------------- 7530 // Field : IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH 7531 #define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_RESET _u(0x0) 7532 #define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) 7533 #define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_MSB _u(9) 7534 #define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_LSB _u(9) 7535 #define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_ACCESS "RW" 7536 // ----------------------------------------------------------------------------- 7537 // Field : IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW 7538 #define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_RESET _u(0x0) 7539 #define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) 7540 #define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_MSB _u(8) 7541 #define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_LSB _u(8) 7542 #define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_ACCESS "RW" 7543 // ----------------------------------------------------------------------------- 7544 // Field : IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH 7545 #define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_RESET _u(0x0) 7546 #define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) 7547 #define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_MSB _u(7) 7548 #define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_LSB _u(7) 7549 #define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_ACCESS "RW" 7550 // ----------------------------------------------------------------------------- 7551 // Field : IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW 7552 #define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_RESET _u(0x0) 7553 #define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_BITS _u(0x00000040) 7554 #define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_MSB _u(6) 7555 #define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_LSB _u(6) 7556 #define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_ACCESS "RW" 7557 // ----------------------------------------------------------------------------- 7558 // Field : IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH 7559 #define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_RESET _u(0x0) 7560 #define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) 7561 #define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_MSB _u(5) 7562 #define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_LSB _u(5) 7563 #define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_ACCESS "RW" 7564 // ----------------------------------------------------------------------------- 7565 // Field : IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW 7566 #define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_RESET _u(0x0) 7567 #define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) 7568 #define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_MSB _u(4) 7569 #define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_LSB _u(4) 7570 #define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_ACCESS "RW" 7571 // ----------------------------------------------------------------------------- 7572 // Field : IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH 7573 #define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_RESET _u(0x0) 7574 #define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) 7575 #define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_MSB _u(3) 7576 #define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_LSB _u(3) 7577 #define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_ACCESS "RW" 7578 // ----------------------------------------------------------------------------- 7579 // Field : IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW 7580 #define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_RESET _u(0x0) 7581 #define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_BITS _u(0x00000004) 7582 #define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_MSB _u(2) 7583 #define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_LSB _u(2) 7584 #define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_ACCESS "RW" 7585 // ----------------------------------------------------------------------------- 7586 // Field : IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH 7587 #define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_RESET _u(0x0) 7588 #define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) 7589 #define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_MSB _u(1) 7590 #define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_LSB _u(1) 7591 #define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_ACCESS "RW" 7592 // ----------------------------------------------------------------------------- 7593 // Field : IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW 7594 #define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_RESET _u(0x0) 7595 #define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) 7596 #define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_MSB _u(0) 7597 #define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_LSB _u(0) 7598 #define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_ACCESS "RW" 7599 // ============================================================================= 7600 // Register : IO_BANK0_PROC0_INTS0 7601 // Description : Interrupt status after masking & forcing for proc0 7602 #define IO_BANK0_PROC0_INTS0_OFFSET _u(0x00000120) 7603 #define IO_BANK0_PROC0_INTS0_BITS _u(0xffffffff) 7604 #define IO_BANK0_PROC0_INTS0_RESET _u(0x00000000) 7605 // ----------------------------------------------------------------------------- 7606 // Field : IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH 7607 #define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_RESET _u(0x0) 7608 #define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) 7609 #define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_MSB _u(31) 7610 #define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_LSB _u(31) 7611 #define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_ACCESS "RO" 7612 // ----------------------------------------------------------------------------- 7613 // Field : IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW 7614 #define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_RESET _u(0x0) 7615 #define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_BITS _u(0x40000000) 7616 #define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_MSB _u(30) 7617 #define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_LSB _u(30) 7618 #define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_ACCESS "RO" 7619 // ----------------------------------------------------------------------------- 7620 // Field : IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH 7621 #define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_RESET _u(0x0) 7622 #define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) 7623 #define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_MSB _u(29) 7624 #define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_LSB _u(29) 7625 #define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_ACCESS "RO" 7626 // ----------------------------------------------------------------------------- 7627 // Field : IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW 7628 #define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_RESET _u(0x0) 7629 #define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) 7630 #define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_MSB _u(28) 7631 #define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_LSB _u(28) 7632 #define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_ACCESS "RO" 7633 // ----------------------------------------------------------------------------- 7634 // Field : IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH 7635 #define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_RESET _u(0x0) 7636 #define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) 7637 #define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_MSB _u(27) 7638 #define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_LSB _u(27) 7639 #define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_ACCESS "RO" 7640 // ----------------------------------------------------------------------------- 7641 // Field : IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW 7642 #define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_RESET _u(0x0) 7643 #define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_BITS _u(0x04000000) 7644 #define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_MSB _u(26) 7645 #define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_LSB _u(26) 7646 #define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_ACCESS "RO" 7647 // ----------------------------------------------------------------------------- 7648 // Field : IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH 7649 #define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_RESET _u(0x0) 7650 #define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) 7651 #define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_MSB _u(25) 7652 #define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_LSB _u(25) 7653 #define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_ACCESS "RO" 7654 // ----------------------------------------------------------------------------- 7655 // Field : IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW 7656 #define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_RESET _u(0x0) 7657 #define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) 7658 #define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_MSB _u(24) 7659 #define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_LSB _u(24) 7660 #define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_ACCESS "RO" 7661 // ----------------------------------------------------------------------------- 7662 // Field : IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH 7663 #define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_RESET _u(0x0) 7664 #define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) 7665 #define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_MSB _u(23) 7666 #define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_LSB _u(23) 7667 #define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_ACCESS "RO" 7668 // ----------------------------------------------------------------------------- 7669 // Field : IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW 7670 #define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_RESET _u(0x0) 7671 #define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_BITS _u(0x00400000) 7672 #define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_MSB _u(22) 7673 #define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_LSB _u(22) 7674 #define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_ACCESS "RO" 7675 // ----------------------------------------------------------------------------- 7676 // Field : IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH 7677 #define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_RESET _u(0x0) 7678 #define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) 7679 #define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_MSB _u(21) 7680 #define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_LSB _u(21) 7681 #define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_ACCESS "RO" 7682 // ----------------------------------------------------------------------------- 7683 // Field : IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW 7684 #define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_RESET _u(0x0) 7685 #define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) 7686 #define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_MSB _u(20) 7687 #define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_LSB _u(20) 7688 #define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_ACCESS "RO" 7689 // ----------------------------------------------------------------------------- 7690 // Field : IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH 7691 #define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_RESET _u(0x0) 7692 #define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) 7693 #define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_MSB _u(19) 7694 #define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_LSB _u(19) 7695 #define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_ACCESS "RO" 7696 // ----------------------------------------------------------------------------- 7697 // Field : IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW 7698 #define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_RESET _u(0x0) 7699 #define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_BITS _u(0x00040000) 7700 #define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_MSB _u(18) 7701 #define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_LSB _u(18) 7702 #define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_ACCESS "RO" 7703 // ----------------------------------------------------------------------------- 7704 // Field : IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH 7705 #define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_RESET _u(0x0) 7706 #define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) 7707 #define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_MSB _u(17) 7708 #define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_LSB _u(17) 7709 #define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_ACCESS "RO" 7710 // ----------------------------------------------------------------------------- 7711 // Field : IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW 7712 #define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_RESET _u(0x0) 7713 #define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) 7714 #define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_MSB _u(16) 7715 #define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_LSB _u(16) 7716 #define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_ACCESS "RO" 7717 // ----------------------------------------------------------------------------- 7718 // Field : IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH 7719 #define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_RESET _u(0x0) 7720 #define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) 7721 #define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_MSB _u(15) 7722 #define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_LSB _u(15) 7723 #define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_ACCESS "RO" 7724 // ----------------------------------------------------------------------------- 7725 // Field : IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW 7726 #define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_RESET _u(0x0) 7727 #define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_BITS _u(0x00004000) 7728 #define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_MSB _u(14) 7729 #define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_LSB _u(14) 7730 #define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_ACCESS "RO" 7731 // ----------------------------------------------------------------------------- 7732 // Field : IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH 7733 #define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_RESET _u(0x0) 7734 #define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) 7735 #define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_MSB _u(13) 7736 #define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_LSB _u(13) 7737 #define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_ACCESS "RO" 7738 // ----------------------------------------------------------------------------- 7739 // Field : IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW 7740 #define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_RESET _u(0x0) 7741 #define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) 7742 #define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_MSB _u(12) 7743 #define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_LSB _u(12) 7744 #define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_ACCESS "RO" 7745 // ----------------------------------------------------------------------------- 7746 // Field : IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH 7747 #define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_RESET _u(0x0) 7748 #define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) 7749 #define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_MSB _u(11) 7750 #define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_LSB _u(11) 7751 #define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_ACCESS "RO" 7752 // ----------------------------------------------------------------------------- 7753 // Field : IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW 7754 #define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_RESET _u(0x0) 7755 #define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_BITS _u(0x00000400) 7756 #define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_MSB _u(10) 7757 #define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_LSB _u(10) 7758 #define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_ACCESS "RO" 7759 // ----------------------------------------------------------------------------- 7760 // Field : IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH 7761 #define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_RESET _u(0x0) 7762 #define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) 7763 #define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_MSB _u(9) 7764 #define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_LSB _u(9) 7765 #define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_ACCESS "RO" 7766 // ----------------------------------------------------------------------------- 7767 // Field : IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW 7768 #define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_RESET _u(0x0) 7769 #define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) 7770 #define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_MSB _u(8) 7771 #define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_LSB _u(8) 7772 #define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_ACCESS "RO" 7773 // ----------------------------------------------------------------------------- 7774 // Field : IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH 7775 #define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_RESET _u(0x0) 7776 #define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) 7777 #define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_MSB _u(7) 7778 #define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_LSB _u(7) 7779 #define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_ACCESS "RO" 7780 // ----------------------------------------------------------------------------- 7781 // Field : IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW 7782 #define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_RESET _u(0x0) 7783 #define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_BITS _u(0x00000040) 7784 #define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_MSB _u(6) 7785 #define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_LSB _u(6) 7786 #define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_ACCESS "RO" 7787 // ----------------------------------------------------------------------------- 7788 // Field : IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH 7789 #define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_RESET _u(0x0) 7790 #define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) 7791 #define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_MSB _u(5) 7792 #define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_LSB _u(5) 7793 #define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_ACCESS "RO" 7794 // ----------------------------------------------------------------------------- 7795 // Field : IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW 7796 #define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_RESET _u(0x0) 7797 #define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) 7798 #define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_MSB _u(4) 7799 #define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_LSB _u(4) 7800 #define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_ACCESS "RO" 7801 // ----------------------------------------------------------------------------- 7802 // Field : IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH 7803 #define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_RESET _u(0x0) 7804 #define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) 7805 #define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_MSB _u(3) 7806 #define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_LSB _u(3) 7807 #define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_ACCESS "RO" 7808 // ----------------------------------------------------------------------------- 7809 // Field : IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW 7810 #define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_RESET _u(0x0) 7811 #define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_BITS _u(0x00000004) 7812 #define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_MSB _u(2) 7813 #define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_LSB _u(2) 7814 #define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_ACCESS "RO" 7815 // ----------------------------------------------------------------------------- 7816 // Field : IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH 7817 #define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_RESET _u(0x0) 7818 #define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) 7819 #define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_MSB _u(1) 7820 #define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_LSB _u(1) 7821 #define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_ACCESS "RO" 7822 // ----------------------------------------------------------------------------- 7823 // Field : IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW 7824 #define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_RESET _u(0x0) 7825 #define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) 7826 #define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_MSB _u(0) 7827 #define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_LSB _u(0) 7828 #define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_ACCESS "RO" 7829 // ============================================================================= 7830 // Register : IO_BANK0_PROC0_INTS1 7831 // Description : Interrupt status after masking & forcing for proc0 7832 #define IO_BANK0_PROC0_INTS1_OFFSET _u(0x00000124) 7833 #define IO_BANK0_PROC0_INTS1_BITS _u(0xffffffff) 7834 #define IO_BANK0_PROC0_INTS1_RESET _u(0x00000000) 7835 // ----------------------------------------------------------------------------- 7836 // Field : IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH 7837 #define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_RESET _u(0x0) 7838 #define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) 7839 #define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_MSB _u(31) 7840 #define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_LSB _u(31) 7841 #define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_ACCESS "RO" 7842 // ----------------------------------------------------------------------------- 7843 // Field : IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW 7844 #define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_RESET _u(0x0) 7845 #define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_BITS _u(0x40000000) 7846 #define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_MSB _u(30) 7847 #define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_LSB _u(30) 7848 #define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_ACCESS "RO" 7849 // ----------------------------------------------------------------------------- 7850 // Field : IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH 7851 #define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_RESET _u(0x0) 7852 #define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) 7853 #define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_MSB _u(29) 7854 #define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_LSB _u(29) 7855 #define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_ACCESS "RO" 7856 // ----------------------------------------------------------------------------- 7857 // Field : IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW 7858 #define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_RESET _u(0x0) 7859 #define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) 7860 #define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_MSB _u(28) 7861 #define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_LSB _u(28) 7862 #define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_ACCESS "RO" 7863 // ----------------------------------------------------------------------------- 7864 // Field : IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH 7865 #define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_RESET _u(0x0) 7866 #define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) 7867 #define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_MSB _u(27) 7868 #define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_LSB _u(27) 7869 #define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_ACCESS "RO" 7870 // ----------------------------------------------------------------------------- 7871 // Field : IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW 7872 #define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_RESET _u(0x0) 7873 #define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_BITS _u(0x04000000) 7874 #define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_MSB _u(26) 7875 #define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_LSB _u(26) 7876 #define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_ACCESS "RO" 7877 // ----------------------------------------------------------------------------- 7878 // Field : IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH 7879 #define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_RESET _u(0x0) 7880 #define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) 7881 #define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_MSB _u(25) 7882 #define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_LSB _u(25) 7883 #define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_ACCESS "RO" 7884 // ----------------------------------------------------------------------------- 7885 // Field : IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW 7886 #define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_RESET _u(0x0) 7887 #define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) 7888 #define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_MSB _u(24) 7889 #define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_LSB _u(24) 7890 #define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_ACCESS "RO" 7891 // ----------------------------------------------------------------------------- 7892 // Field : IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH 7893 #define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_RESET _u(0x0) 7894 #define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) 7895 #define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_MSB _u(23) 7896 #define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_LSB _u(23) 7897 #define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_ACCESS "RO" 7898 // ----------------------------------------------------------------------------- 7899 // Field : IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW 7900 #define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_RESET _u(0x0) 7901 #define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_BITS _u(0x00400000) 7902 #define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_MSB _u(22) 7903 #define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_LSB _u(22) 7904 #define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_ACCESS "RO" 7905 // ----------------------------------------------------------------------------- 7906 // Field : IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH 7907 #define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_RESET _u(0x0) 7908 #define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) 7909 #define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_MSB _u(21) 7910 #define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_LSB _u(21) 7911 #define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_ACCESS "RO" 7912 // ----------------------------------------------------------------------------- 7913 // Field : IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW 7914 #define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_RESET _u(0x0) 7915 #define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) 7916 #define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_MSB _u(20) 7917 #define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_LSB _u(20) 7918 #define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_ACCESS "RO" 7919 // ----------------------------------------------------------------------------- 7920 // Field : IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH 7921 #define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_RESET _u(0x0) 7922 #define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) 7923 #define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_MSB _u(19) 7924 #define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_LSB _u(19) 7925 #define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_ACCESS "RO" 7926 // ----------------------------------------------------------------------------- 7927 // Field : IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW 7928 #define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_RESET _u(0x0) 7929 #define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_BITS _u(0x00040000) 7930 #define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_MSB _u(18) 7931 #define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_LSB _u(18) 7932 #define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_ACCESS "RO" 7933 // ----------------------------------------------------------------------------- 7934 // Field : IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH 7935 #define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_RESET _u(0x0) 7936 #define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) 7937 #define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_MSB _u(17) 7938 #define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_LSB _u(17) 7939 #define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_ACCESS "RO" 7940 // ----------------------------------------------------------------------------- 7941 // Field : IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW 7942 #define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_RESET _u(0x0) 7943 #define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) 7944 #define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_MSB _u(16) 7945 #define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_LSB _u(16) 7946 #define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_ACCESS "RO" 7947 // ----------------------------------------------------------------------------- 7948 // Field : IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH 7949 #define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_RESET _u(0x0) 7950 #define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) 7951 #define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_MSB _u(15) 7952 #define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_LSB _u(15) 7953 #define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_ACCESS "RO" 7954 // ----------------------------------------------------------------------------- 7955 // Field : IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW 7956 #define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_RESET _u(0x0) 7957 #define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_BITS _u(0x00004000) 7958 #define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_MSB _u(14) 7959 #define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_LSB _u(14) 7960 #define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_ACCESS "RO" 7961 // ----------------------------------------------------------------------------- 7962 // Field : IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH 7963 #define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_RESET _u(0x0) 7964 #define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) 7965 #define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_MSB _u(13) 7966 #define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_LSB _u(13) 7967 #define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_ACCESS "RO" 7968 // ----------------------------------------------------------------------------- 7969 // Field : IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW 7970 #define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_RESET _u(0x0) 7971 #define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) 7972 #define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_MSB _u(12) 7973 #define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_LSB _u(12) 7974 #define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_ACCESS "RO" 7975 // ----------------------------------------------------------------------------- 7976 // Field : IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH 7977 #define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_RESET _u(0x0) 7978 #define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) 7979 #define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_MSB _u(11) 7980 #define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_LSB _u(11) 7981 #define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_ACCESS "RO" 7982 // ----------------------------------------------------------------------------- 7983 // Field : IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW 7984 #define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_RESET _u(0x0) 7985 #define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_BITS _u(0x00000400) 7986 #define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_MSB _u(10) 7987 #define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_LSB _u(10) 7988 #define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_ACCESS "RO" 7989 // ----------------------------------------------------------------------------- 7990 // Field : IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH 7991 #define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_RESET _u(0x0) 7992 #define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) 7993 #define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_MSB _u(9) 7994 #define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_LSB _u(9) 7995 #define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_ACCESS "RO" 7996 // ----------------------------------------------------------------------------- 7997 // Field : IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW 7998 #define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_RESET _u(0x0) 7999 #define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) 8000 #define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_MSB _u(8) 8001 #define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_LSB _u(8) 8002 #define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_ACCESS "RO" 8003 // ----------------------------------------------------------------------------- 8004 // Field : IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH 8005 #define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_RESET _u(0x0) 8006 #define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) 8007 #define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_MSB _u(7) 8008 #define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_LSB _u(7) 8009 #define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_ACCESS "RO" 8010 // ----------------------------------------------------------------------------- 8011 // Field : IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW 8012 #define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_RESET _u(0x0) 8013 #define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_BITS _u(0x00000040) 8014 #define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_MSB _u(6) 8015 #define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_LSB _u(6) 8016 #define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_ACCESS "RO" 8017 // ----------------------------------------------------------------------------- 8018 // Field : IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH 8019 #define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_RESET _u(0x0) 8020 #define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) 8021 #define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_MSB _u(5) 8022 #define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_LSB _u(5) 8023 #define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_ACCESS "RO" 8024 // ----------------------------------------------------------------------------- 8025 // Field : IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW 8026 #define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_RESET _u(0x0) 8027 #define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) 8028 #define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_MSB _u(4) 8029 #define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_LSB _u(4) 8030 #define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_ACCESS "RO" 8031 // ----------------------------------------------------------------------------- 8032 // Field : IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH 8033 #define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_RESET _u(0x0) 8034 #define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) 8035 #define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_MSB _u(3) 8036 #define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_LSB _u(3) 8037 #define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_ACCESS "RO" 8038 // ----------------------------------------------------------------------------- 8039 // Field : IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW 8040 #define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_RESET _u(0x0) 8041 #define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_BITS _u(0x00000004) 8042 #define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_MSB _u(2) 8043 #define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_LSB _u(2) 8044 #define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_ACCESS "RO" 8045 // ----------------------------------------------------------------------------- 8046 // Field : IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH 8047 #define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_RESET _u(0x0) 8048 #define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) 8049 #define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_MSB _u(1) 8050 #define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_LSB _u(1) 8051 #define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_ACCESS "RO" 8052 // ----------------------------------------------------------------------------- 8053 // Field : IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW 8054 #define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_RESET _u(0x0) 8055 #define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) 8056 #define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_MSB _u(0) 8057 #define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_LSB _u(0) 8058 #define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_ACCESS "RO" 8059 // ============================================================================= 8060 // Register : IO_BANK0_PROC0_INTS2 8061 // Description : Interrupt status after masking & forcing for proc0 8062 #define IO_BANK0_PROC0_INTS2_OFFSET _u(0x00000128) 8063 #define IO_BANK0_PROC0_INTS2_BITS _u(0xffffffff) 8064 #define IO_BANK0_PROC0_INTS2_RESET _u(0x00000000) 8065 // ----------------------------------------------------------------------------- 8066 // Field : IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH 8067 #define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_RESET _u(0x0) 8068 #define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) 8069 #define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_MSB _u(31) 8070 #define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_LSB _u(31) 8071 #define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_ACCESS "RO" 8072 // ----------------------------------------------------------------------------- 8073 // Field : IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW 8074 #define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_RESET _u(0x0) 8075 #define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_BITS _u(0x40000000) 8076 #define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_MSB _u(30) 8077 #define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_LSB _u(30) 8078 #define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_ACCESS "RO" 8079 // ----------------------------------------------------------------------------- 8080 // Field : IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH 8081 #define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_RESET _u(0x0) 8082 #define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) 8083 #define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_MSB _u(29) 8084 #define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_LSB _u(29) 8085 #define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_ACCESS "RO" 8086 // ----------------------------------------------------------------------------- 8087 // Field : IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW 8088 #define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_RESET _u(0x0) 8089 #define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) 8090 #define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_MSB _u(28) 8091 #define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_LSB _u(28) 8092 #define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_ACCESS "RO" 8093 // ----------------------------------------------------------------------------- 8094 // Field : IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH 8095 #define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_RESET _u(0x0) 8096 #define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) 8097 #define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_MSB _u(27) 8098 #define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_LSB _u(27) 8099 #define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_ACCESS "RO" 8100 // ----------------------------------------------------------------------------- 8101 // Field : IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW 8102 #define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_RESET _u(0x0) 8103 #define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_BITS _u(0x04000000) 8104 #define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_MSB _u(26) 8105 #define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_LSB _u(26) 8106 #define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_ACCESS "RO" 8107 // ----------------------------------------------------------------------------- 8108 // Field : IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH 8109 #define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_RESET _u(0x0) 8110 #define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) 8111 #define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_MSB _u(25) 8112 #define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_LSB _u(25) 8113 #define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_ACCESS "RO" 8114 // ----------------------------------------------------------------------------- 8115 // Field : IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW 8116 #define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_RESET _u(0x0) 8117 #define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) 8118 #define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_MSB _u(24) 8119 #define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_LSB _u(24) 8120 #define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_ACCESS "RO" 8121 // ----------------------------------------------------------------------------- 8122 // Field : IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH 8123 #define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_RESET _u(0x0) 8124 #define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) 8125 #define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_MSB _u(23) 8126 #define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_LSB _u(23) 8127 #define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_ACCESS "RO" 8128 // ----------------------------------------------------------------------------- 8129 // Field : IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW 8130 #define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_RESET _u(0x0) 8131 #define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_BITS _u(0x00400000) 8132 #define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_MSB _u(22) 8133 #define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_LSB _u(22) 8134 #define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_ACCESS "RO" 8135 // ----------------------------------------------------------------------------- 8136 // Field : IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH 8137 #define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_RESET _u(0x0) 8138 #define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) 8139 #define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_MSB _u(21) 8140 #define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_LSB _u(21) 8141 #define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_ACCESS "RO" 8142 // ----------------------------------------------------------------------------- 8143 // Field : IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW 8144 #define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_RESET _u(0x0) 8145 #define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) 8146 #define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_MSB _u(20) 8147 #define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_LSB _u(20) 8148 #define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_ACCESS "RO" 8149 // ----------------------------------------------------------------------------- 8150 // Field : IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH 8151 #define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_RESET _u(0x0) 8152 #define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) 8153 #define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_MSB _u(19) 8154 #define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_LSB _u(19) 8155 #define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_ACCESS "RO" 8156 // ----------------------------------------------------------------------------- 8157 // Field : IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW 8158 #define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_RESET _u(0x0) 8159 #define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_BITS _u(0x00040000) 8160 #define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_MSB _u(18) 8161 #define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_LSB _u(18) 8162 #define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_ACCESS "RO" 8163 // ----------------------------------------------------------------------------- 8164 // Field : IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH 8165 #define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_RESET _u(0x0) 8166 #define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) 8167 #define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_MSB _u(17) 8168 #define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_LSB _u(17) 8169 #define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_ACCESS "RO" 8170 // ----------------------------------------------------------------------------- 8171 // Field : IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW 8172 #define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_RESET _u(0x0) 8173 #define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) 8174 #define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_MSB _u(16) 8175 #define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_LSB _u(16) 8176 #define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_ACCESS "RO" 8177 // ----------------------------------------------------------------------------- 8178 // Field : IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH 8179 #define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_RESET _u(0x0) 8180 #define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) 8181 #define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_MSB _u(15) 8182 #define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_LSB _u(15) 8183 #define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_ACCESS "RO" 8184 // ----------------------------------------------------------------------------- 8185 // Field : IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW 8186 #define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_RESET _u(0x0) 8187 #define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_BITS _u(0x00004000) 8188 #define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_MSB _u(14) 8189 #define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_LSB _u(14) 8190 #define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_ACCESS "RO" 8191 // ----------------------------------------------------------------------------- 8192 // Field : IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH 8193 #define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_RESET _u(0x0) 8194 #define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) 8195 #define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_MSB _u(13) 8196 #define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_LSB _u(13) 8197 #define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_ACCESS "RO" 8198 // ----------------------------------------------------------------------------- 8199 // Field : IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW 8200 #define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_RESET _u(0x0) 8201 #define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) 8202 #define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_MSB _u(12) 8203 #define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_LSB _u(12) 8204 #define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_ACCESS "RO" 8205 // ----------------------------------------------------------------------------- 8206 // Field : IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH 8207 #define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_RESET _u(0x0) 8208 #define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) 8209 #define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_MSB _u(11) 8210 #define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_LSB _u(11) 8211 #define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_ACCESS "RO" 8212 // ----------------------------------------------------------------------------- 8213 // Field : IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW 8214 #define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_RESET _u(0x0) 8215 #define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_BITS _u(0x00000400) 8216 #define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_MSB _u(10) 8217 #define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_LSB _u(10) 8218 #define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_ACCESS "RO" 8219 // ----------------------------------------------------------------------------- 8220 // Field : IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH 8221 #define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_RESET _u(0x0) 8222 #define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) 8223 #define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_MSB _u(9) 8224 #define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_LSB _u(9) 8225 #define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_ACCESS "RO" 8226 // ----------------------------------------------------------------------------- 8227 // Field : IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW 8228 #define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_RESET _u(0x0) 8229 #define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) 8230 #define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_MSB _u(8) 8231 #define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_LSB _u(8) 8232 #define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_ACCESS "RO" 8233 // ----------------------------------------------------------------------------- 8234 // Field : IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH 8235 #define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_RESET _u(0x0) 8236 #define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) 8237 #define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_MSB _u(7) 8238 #define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_LSB _u(7) 8239 #define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_ACCESS "RO" 8240 // ----------------------------------------------------------------------------- 8241 // Field : IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW 8242 #define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_RESET _u(0x0) 8243 #define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_BITS _u(0x00000040) 8244 #define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_MSB _u(6) 8245 #define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_LSB _u(6) 8246 #define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_ACCESS "RO" 8247 // ----------------------------------------------------------------------------- 8248 // Field : IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH 8249 #define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_RESET _u(0x0) 8250 #define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) 8251 #define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_MSB _u(5) 8252 #define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_LSB _u(5) 8253 #define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_ACCESS "RO" 8254 // ----------------------------------------------------------------------------- 8255 // Field : IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW 8256 #define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_RESET _u(0x0) 8257 #define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) 8258 #define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_MSB _u(4) 8259 #define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_LSB _u(4) 8260 #define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_ACCESS "RO" 8261 // ----------------------------------------------------------------------------- 8262 // Field : IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH 8263 #define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_RESET _u(0x0) 8264 #define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) 8265 #define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_MSB _u(3) 8266 #define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_LSB _u(3) 8267 #define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_ACCESS "RO" 8268 // ----------------------------------------------------------------------------- 8269 // Field : IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW 8270 #define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_RESET _u(0x0) 8271 #define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_BITS _u(0x00000004) 8272 #define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_MSB _u(2) 8273 #define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_LSB _u(2) 8274 #define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_ACCESS "RO" 8275 // ----------------------------------------------------------------------------- 8276 // Field : IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH 8277 #define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_RESET _u(0x0) 8278 #define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) 8279 #define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_MSB _u(1) 8280 #define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_LSB _u(1) 8281 #define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_ACCESS "RO" 8282 // ----------------------------------------------------------------------------- 8283 // Field : IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW 8284 #define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_RESET _u(0x0) 8285 #define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) 8286 #define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_MSB _u(0) 8287 #define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_LSB _u(0) 8288 #define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_ACCESS "RO" 8289 // ============================================================================= 8290 // Register : IO_BANK0_PROC0_INTS3 8291 // Description : Interrupt status after masking & forcing for proc0 8292 #define IO_BANK0_PROC0_INTS3_OFFSET _u(0x0000012c) 8293 #define IO_BANK0_PROC0_INTS3_BITS _u(0x00ffffff) 8294 #define IO_BANK0_PROC0_INTS3_RESET _u(0x00000000) 8295 // ----------------------------------------------------------------------------- 8296 // Field : IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH 8297 #define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_RESET _u(0x0) 8298 #define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) 8299 #define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_MSB _u(23) 8300 #define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_LSB _u(23) 8301 #define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_ACCESS "RO" 8302 // ----------------------------------------------------------------------------- 8303 // Field : IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW 8304 #define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_RESET _u(0x0) 8305 #define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_BITS _u(0x00400000) 8306 #define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_MSB _u(22) 8307 #define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_LSB _u(22) 8308 #define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_ACCESS "RO" 8309 // ----------------------------------------------------------------------------- 8310 // Field : IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH 8311 #define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_RESET _u(0x0) 8312 #define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) 8313 #define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_MSB _u(21) 8314 #define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_LSB _u(21) 8315 #define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_ACCESS "RO" 8316 // ----------------------------------------------------------------------------- 8317 // Field : IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW 8318 #define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_RESET _u(0x0) 8319 #define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) 8320 #define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_MSB _u(20) 8321 #define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_LSB _u(20) 8322 #define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_ACCESS "RO" 8323 // ----------------------------------------------------------------------------- 8324 // Field : IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH 8325 #define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_RESET _u(0x0) 8326 #define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) 8327 #define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_MSB _u(19) 8328 #define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_LSB _u(19) 8329 #define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_ACCESS "RO" 8330 // ----------------------------------------------------------------------------- 8331 // Field : IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW 8332 #define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_RESET _u(0x0) 8333 #define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_BITS _u(0x00040000) 8334 #define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_MSB _u(18) 8335 #define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_LSB _u(18) 8336 #define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_ACCESS "RO" 8337 // ----------------------------------------------------------------------------- 8338 // Field : IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH 8339 #define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_RESET _u(0x0) 8340 #define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) 8341 #define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_MSB _u(17) 8342 #define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_LSB _u(17) 8343 #define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_ACCESS "RO" 8344 // ----------------------------------------------------------------------------- 8345 // Field : IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW 8346 #define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_RESET _u(0x0) 8347 #define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) 8348 #define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_MSB _u(16) 8349 #define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_LSB _u(16) 8350 #define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_ACCESS "RO" 8351 // ----------------------------------------------------------------------------- 8352 // Field : IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH 8353 #define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_RESET _u(0x0) 8354 #define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) 8355 #define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_MSB _u(15) 8356 #define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_LSB _u(15) 8357 #define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_ACCESS "RO" 8358 // ----------------------------------------------------------------------------- 8359 // Field : IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW 8360 #define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_RESET _u(0x0) 8361 #define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_BITS _u(0x00004000) 8362 #define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_MSB _u(14) 8363 #define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_LSB _u(14) 8364 #define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_ACCESS "RO" 8365 // ----------------------------------------------------------------------------- 8366 // Field : IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH 8367 #define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_RESET _u(0x0) 8368 #define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) 8369 #define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_MSB _u(13) 8370 #define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_LSB _u(13) 8371 #define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_ACCESS "RO" 8372 // ----------------------------------------------------------------------------- 8373 // Field : IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW 8374 #define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_RESET _u(0x0) 8375 #define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) 8376 #define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_MSB _u(12) 8377 #define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_LSB _u(12) 8378 #define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_ACCESS "RO" 8379 // ----------------------------------------------------------------------------- 8380 // Field : IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH 8381 #define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_RESET _u(0x0) 8382 #define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) 8383 #define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_MSB _u(11) 8384 #define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_LSB _u(11) 8385 #define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_ACCESS "RO" 8386 // ----------------------------------------------------------------------------- 8387 // Field : IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW 8388 #define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_RESET _u(0x0) 8389 #define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_BITS _u(0x00000400) 8390 #define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_MSB _u(10) 8391 #define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_LSB _u(10) 8392 #define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_ACCESS "RO" 8393 // ----------------------------------------------------------------------------- 8394 // Field : IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH 8395 #define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_RESET _u(0x0) 8396 #define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) 8397 #define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_MSB _u(9) 8398 #define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_LSB _u(9) 8399 #define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_ACCESS "RO" 8400 // ----------------------------------------------------------------------------- 8401 // Field : IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW 8402 #define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_RESET _u(0x0) 8403 #define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) 8404 #define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_MSB _u(8) 8405 #define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_LSB _u(8) 8406 #define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_ACCESS "RO" 8407 // ----------------------------------------------------------------------------- 8408 // Field : IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH 8409 #define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_RESET _u(0x0) 8410 #define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) 8411 #define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_MSB _u(7) 8412 #define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_LSB _u(7) 8413 #define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_ACCESS "RO" 8414 // ----------------------------------------------------------------------------- 8415 // Field : IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW 8416 #define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_RESET _u(0x0) 8417 #define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_BITS _u(0x00000040) 8418 #define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_MSB _u(6) 8419 #define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_LSB _u(6) 8420 #define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_ACCESS "RO" 8421 // ----------------------------------------------------------------------------- 8422 // Field : IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH 8423 #define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_RESET _u(0x0) 8424 #define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) 8425 #define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_MSB _u(5) 8426 #define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_LSB _u(5) 8427 #define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_ACCESS "RO" 8428 // ----------------------------------------------------------------------------- 8429 // Field : IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW 8430 #define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_RESET _u(0x0) 8431 #define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) 8432 #define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_MSB _u(4) 8433 #define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_LSB _u(4) 8434 #define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_ACCESS "RO" 8435 // ----------------------------------------------------------------------------- 8436 // Field : IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH 8437 #define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_RESET _u(0x0) 8438 #define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) 8439 #define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_MSB _u(3) 8440 #define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_LSB _u(3) 8441 #define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_ACCESS "RO" 8442 // ----------------------------------------------------------------------------- 8443 // Field : IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW 8444 #define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_RESET _u(0x0) 8445 #define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_BITS _u(0x00000004) 8446 #define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_MSB _u(2) 8447 #define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_LSB _u(2) 8448 #define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_ACCESS "RO" 8449 // ----------------------------------------------------------------------------- 8450 // Field : IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH 8451 #define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_RESET _u(0x0) 8452 #define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) 8453 #define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_MSB _u(1) 8454 #define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_LSB _u(1) 8455 #define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_ACCESS "RO" 8456 // ----------------------------------------------------------------------------- 8457 // Field : IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW 8458 #define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_RESET _u(0x0) 8459 #define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) 8460 #define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_MSB _u(0) 8461 #define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_LSB _u(0) 8462 #define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_ACCESS "RO" 8463 // ============================================================================= 8464 // Register : IO_BANK0_PROC1_INTE0 8465 // Description : Interrupt Enable for proc1 8466 #define IO_BANK0_PROC1_INTE0_OFFSET _u(0x00000130) 8467 #define IO_BANK0_PROC1_INTE0_BITS _u(0xffffffff) 8468 #define IO_BANK0_PROC1_INTE0_RESET _u(0x00000000) 8469 // ----------------------------------------------------------------------------- 8470 // Field : IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH 8471 #define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_RESET _u(0x0) 8472 #define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) 8473 #define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_MSB _u(31) 8474 #define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_LSB _u(31) 8475 #define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_ACCESS "RW" 8476 // ----------------------------------------------------------------------------- 8477 // Field : IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW 8478 #define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_RESET _u(0x0) 8479 #define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_BITS _u(0x40000000) 8480 #define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_MSB _u(30) 8481 #define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_LSB _u(30) 8482 #define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_ACCESS "RW" 8483 // ----------------------------------------------------------------------------- 8484 // Field : IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH 8485 #define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_RESET _u(0x0) 8486 #define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) 8487 #define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_MSB _u(29) 8488 #define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_LSB _u(29) 8489 #define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_ACCESS "RW" 8490 // ----------------------------------------------------------------------------- 8491 // Field : IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW 8492 #define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_RESET _u(0x0) 8493 #define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) 8494 #define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_MSB _u(28) 8495 #define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_LSB _u(28) 8496 #define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_ACCESS "RW" 8497 // ----------------------------------------------------------------------------- 8498 // Field : IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH 8499 #define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_RESET _u(0x0) 8500 #define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) 8501 #define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_MSB _u(27) 8502 #define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_LSB _u(27) 8503 #define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_ACCESS "RW" 8504 // ----------------------------------------------------------------------------- 8505 // Field : IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW 8506 #define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_RESET _u(0x0) 8507 #define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_BITS _u(0x04000000) 8508 #define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_MSB _u(26) 8509 #define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_LSB _u(26) 8510 #define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_ACCESS "RW" 8511 // ----------------------------------------------------------------------------- 8512 // Field : IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH 8513 #define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_RESET _u(0x0) 8514 #define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) 8515 #define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_MSB _u(25) 8516 #define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_LSB _u(25) 8517 #define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_ACCESS "RW" 8518 // ----------------------------------------------------------------------------- 8519 // Field : IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW 8520 #define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_RESET _u(0x0) 8521 #define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) 8522 #define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_MSB _u(24) 8523 #define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_LSB _u(24) 8524 #define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_ACCESS "RW" 8525 // ----------------------------------------------------------------------------- 8526 // Field : IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH 8527 #define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_RESET _u(0x0) 8528 #define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) 8529 #define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_MSB _u(23) 8530 #define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_LSB _u(23) 8531 #define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_ACCESS "RW" 8532 // ----------------------------------------------------------------------------- 8533 // Field : IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW 8534 #define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_RESET _u(0x0) 8535 #define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_BITS _u(0x00400000) 8536 #define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_MSB _u(22) 8537 #define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_LSB _u(22) 8538 #define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_ACCESS "RW" 8539 // ----------------------------------------------------------------------------- 8540 // Field : IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH 8541 #define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_RESET _u(0x0) 8542 #define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) 8543 #define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_MSB _u(21) 8544 #define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_LSB _u(21) 8545 #define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_ACCESS "RW" 8546 // ----------------------------------------------------------------------------- 8547 // Field : IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW 8548 #define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_RESET _u(0x0) 8549 #define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) 8550 #define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_MSB _u(20) 8551 #define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_LSB _u(20) 8552 #define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_ACCESS "RW" 8553 // ----------------------------------------------------------------------------- 8554 // Field : IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH 8555 #define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_RESET _u(0x0) 8556 #define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) 8557 #define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_MSB _u(19) 8558 #define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_LSB _u(19) 8559 #define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_ACCESS "RW" 8560 // ----------------------------------------------------------------------------- 8561 // Field : IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW 8562 #define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_RESET _u(0x0) 8563 #define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_BITS _u(0x00040000) 8564 #define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_MSB _u(18) 8565 #define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_LSB _u(18) 8566 #define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_ACCESS "RW" 8567 // ----------------------------------------------------------------------------- 8568 // Field : IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH 8569 #define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_RESET _u(0x0) 8570 #define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) 8571 #define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_MSB _u(17) 8572 #define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_LSB _u(17) 8573 #define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_ACCESS "RW" 8574 // ----------------------------------------------------------------------------- 8575 // Field : IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW 8576 #define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_RESET _u(0x0) 8577 #define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) 8578 #define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_MSB _u(16) 8579 #define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_LSB _u(16) 8580 #define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_ACCESS "RW" 8581 // ----------------------------------------------------------------------------- 8582 // Field : IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH 8583 #define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_RESET _u(0x0) 8584 #define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) 8585 #define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_MSB _u(15) 8586 #define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_LSB _u(15) 8587 #define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_ACCESS "RW" 8588 // ----------------------------------------------------------------------------- 8589 // Field : IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW 8590 #define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_RESET _u(0x0) 8591 #define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_BITS _u(0x00004000) 8592 #define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_MSB _u(14) 8593 #define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_LSB _u(14) 8594 #define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_ACCESS "RW" 8595 // ----------------------------------------------------------------------------- 8596 // Field : IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH 8597 #define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_RESET _u(0x0) 8598 #define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) 8599 #define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_MSB _u(13) 8600 #define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_LSB _u(13) 8601 #define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_ACCESS "RW" 8602 // ----------------------------------------------------------------------------- 8603 // Field : IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW 8604 #define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_RESET _u(0x0) 8605 #define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) 8606 #define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_MSB _u(12) 8607 #define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_LSB _u(12) 8608 #define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_ACCESS "RW" 8609 // ----------------------------------------------------------------------------- 8610 // Field : IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH 8611 #define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_RESET _u(0x0) 8612 #define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) 8613 #define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_MSB _u(11) 8614 #define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_LSB _u(11) 8615 #define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_ACCESS "RW" 8616 // ----------------------------------------------------------------------------- 8617 // Field : IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW 8618 #define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_RESET _u(0x0) 8619 #define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_BITS _u(0x00000400) 8620 #define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_MSB _u(10) 8621 #define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_LSB _u(10) 8622 #define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_ACCESS "RW" 8623 // ----------------------------------------------------------------------------- 8624 // Field : IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH 8625 #define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_RESET _u(0x0) 8626 #define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) 8627 #define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_MSB _u(9) 8628 #define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_LSB _u(9) 8629 #define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_ACCESS "RW" 8630 // ----------------------------------------------------------------------------- 8631 // Field : IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW 8632 #define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_RESET _u(0x0) 8633 #define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) 8634 #define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_MSB _u(8) 8635 #define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_LSB _u(8) 8636 #define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_ACCESS "RW" 8637 // ----------------------------------------------------------------------------- 8638 // Field : IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH 8639 #define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_RESET _u(0x0) 8640 #define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) 8641 #define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_MSB _u(7) 8642 #define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_LSB _u(7) 8643 #define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_ACCESS "RW" 8644 // ----------------------------------------------------------------------------- 8645 // Field : IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW 8646 #define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_RESET _u(0x0) 8647 #define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_BITS _u(0x00000040) 8648 #define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_MSB _u(6) 8649 #define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_LSB _u(6) 8650 #define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_ACCESS "RW" 8651 // ----------------------------------------------------------------------------- 8652 // Field : IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH 8653 #define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_RESET _u(0x0) 8654 #define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) 8655 #define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_MSB _u(5) 8656 #define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_LSB _u(5) 8657 #define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_ACCESS "RW" 8658 // ----------------------------------------------------------------------------- 8659 // Field : IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW 8660 #define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_RESET _u(0x0) 8661 #define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) 8662 #define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_MSB _u(4) 8663 #define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_LSB _u(4) 8664 #define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_ACCESS "RW" 8665 // ----------------------------------------------------------------------------- 8666 // Field : IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH 8667 #define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_RESET _u(0x0) 8668 #define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) 8669 #define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_MSB _u(3) 8670 #define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_LSB _u(3) 8671 #define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_ACCESS "RW" 8672 // ----------------------------------------------------------------------------- 8673 // Field : IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW 8674 #define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_RESET _u(0x0) 8675 #define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_BITS _u(0x00000004) 8676 #define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_MSB _u(2) 8677 #define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_LSB _u(2) 8678 #define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_ACCESS "RW" 8679 // ----------------------------------------------------------------------------- 8680 // Field : IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH 8681 #define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_RESET _u(0x0) 8682 #define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) 8683 #define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_MSB _u(1) 8684 #define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_LSB _u(1) 8685 #define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_ACCESS "RW" 8686 // ----------------------------------------------------------------------------- 8687 // Field : IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW 8688 #define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_RESET _u(0x0) 8689 #define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) 8690 #define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_MSB _u(0) 8691 #define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_LSB _u(0) 8692 #define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_ACCESS "RW" 8693 // ============================================================================= 8694 // Register : IO_BANK0_PROC1_INTE1 8695 // Description : Interrupt Enable for proc1 8696 #define IO_BANK0_PROC1_INTE1_OFFSET _u(0x00000134) 8697 #define IO_BANK0_PROC1_INTE1_BITS _u(0xffffffff) 8698 #define IO_BANK0_PROC1_INTE1_RESET _u(0x00000000) 8699 // ----------------------------------------------------------------------------- 8700 // Field : IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH 8701 #define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_RESET _u(0x0) 8702 #define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) 8703 #define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_MSB _u(31) 8704 #define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_LSB _u(31) 8705 #define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_ACCESS "RW" 8706 // ----------------------------------------------------------------------------- 8707 // Field : IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW 8708 #define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_RESET _u(0x0) 8709 #define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_BITS _u(0x40000000) 8710 #define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_MSB _u(30) 8711 #define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_LSB _u(30) 8712 #define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_ACCESS "RW" 8713 // ----------------------------------------------------------------------------- 8714 // Field : IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH 8715 #define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_RESET _u(0x0) 8716 #define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) 8717 #define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_MSB _u(29) 8718 #define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_LSB _u(29) 8719 #define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_ACCESS "RW" 8720 // ----------------------------------------------------------------------------- 8721 // Field : IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW 8722 #define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_RESET _u(0x0) 8723 #define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) 8724 #define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_MSB _u(28) 8725 #define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_LSB _u(28) 8726 #define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_ACCESS "RW" 8727 // ----------------------------------------------------------------------------- 8728 // Field : IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH 8729 #define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_RESET _u(0x0) 8730 #define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) 8731 #define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_MSB _u(27) 8732 #define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_LSB _u(27) 8733 #define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_ACCESS "RW" 8734 // ----------------------------------------------------------------------------- 8735 // Field : IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW 8736 #define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_RESET _u(0x0) 8737 #define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_BITS _u(0x04000000) 8738 #define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_MSB _u(26) 8739 #define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_LSB _u(26) 8740 #define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_ACCESS "RW" 8741 // ----------------------------------------------------------------------------- 8742 // Field : IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH 8743 #define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_RESET _u(0x0) 8744 #define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) 8745 #define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_MSB _u(25) 8746 #define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_LSB _u(25) 8747 #define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_ACCESS "RW" 8748 // ----------------------------------------------------------------------------- 8749 // Field : IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW 8750 #define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_RESET _u(0x0) 8751 #define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) 8752 #define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_MSB _u(24) 8753 #define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_LSB _u(24) 8754 #define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_ACCESS "RW" 8755 // ----------------------------------------------------------------------------- 8756 // Field : IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH 8757 #define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_RESET _u(0x0) 8758 #define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) 8759 #define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_MSB _u(23) 8760 #define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_LSB _u(23) 8761 #define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_ACCESS "RW" 8762 // ----------------------------------------------------------------------------- 8763 // Field : IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW 8764 #define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_RESET _u(0x0) 8765 #define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_BITS _u(0x00400000) 8766 #define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_MSB _u(22) 8767 #define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_LSB _u(22) 8768 #define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_ACCESS "RW" 8769 // ----------------------------------------------------------------------------- 8770 // Field : IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH 8771 #define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_RESET _u(0x0) 8772 #define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) 8773 #define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_MSB _u(21) 8774 #define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_LSB _u(21) 8775 #define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_ACCESS "RW" 8776 // ----------------------------------------------------------------------------- 8777 // Field : IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW 8778 #define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_RESET _u(0x0) 8779 #define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) 8780 #define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_MSB _u(20) 8781 #define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_LSB _u(20) 8782 #define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_ACCESS "RW" 8783 // ----------------------------------------------------------------------------- 8784 // Field : IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH 8785 #define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_RESET _u(0x0) 8786 #define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) 8787 #define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_MSB _u(19) 8788 #define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_LSB _u(19) 8789 #define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_ACCESS "RW" 8790 // ----------------------------------------------------------------------------- 8791 // Field : IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW 8792 #define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_RESET _u(0x0) 8793 #define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_BITS _u(0x00040000) 8794 #define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_MSB _u(18) 8795 #define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_LSB _u(18) 8796 #define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_ACCESS "RW" 8797 // ----------------------------------------------------------------------------- 8798 // Field : IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH 8799 #define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_RESET _u(0x0) 8800 #define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) 8801 #define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_MSB _u(17) 8802 #define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_LSB _u(17) 8803 #define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_ACCESS "RW" 8804 // ----------------------------------------------------------------------------- 8805 // Field : IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW 8806 #define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_RESET _u(0x0) 8807 #define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) 8808 #define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_MSB _u(16) 8809 #define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_LSB _u(16) 8810 #define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_ACCESS "RW" 8811 // ----------------------------------------------------------------------------- 8812 // Field : IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH 8813 #define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_RESET _u(0x0) 8814 #define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) 8815 #define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_MSB _u(15) 8816 #define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_LSB _u(15) 8817 #define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_ACCESS "RW" 8818 // ----------------------------------------------------------------------------- 8819 // Field : IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW 8820 #define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_RESET _u(0x0) 8821 #define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_BITS _u(0x00004000) 8822 #define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_MSB _u(14) 8823 #define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_LSB _u(14) 8824 #define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_ACCESS "RW" 8825 // ----------------------------------------------------------------------------- 8826 // Field : IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH 8827 #define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_RESET _u(0x0) 8828 #define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) 8829 #define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_MSB _u(13) 8830 #define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_LSB _u(13) 8831 #define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_ACCESS "RW" 8832 // ----------------------------------------------------------------------------- 8833 // Field : IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW 8834 #define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_RESET _u(0x0) 8835 #define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) 8836 #define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_MSB _u(12) 8837 #define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_LSB _u(12) 8838 #define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_ACCESS "RW" 8839 // ----------------------------------------------------------------------------- 8840 // Field : IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH 8841 #define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_RESET _u(0x0) 8842 #define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) 8843 #define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_MSB _u(11) 8844 #define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_LSB _u(11) 8845 #define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_ACCESS "RW" 8846 // ----------------------------------------------------------------------------- 8847 // Field : IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW 8848 #define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_RESET _u(0x0) 8849 #define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_BITS _u(0x00000400) 8850 #define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_MSB _u(10) 8851 #define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_LSB _u(10) 8852 #define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_ACCESS "RW" 8853 // ----------------------------------------------------------------------------- 8854 // Field : IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH 8855 #define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_RESET _u(0x0) 8856 #define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) 8857 #define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_MSB _u(9) 8858 #define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_LSB _u(9) 8859 #define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_ACCESS "RW" 8860 // ----------------------------------------------------------------------------- 8861 // Field : IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW 8862 #define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_RESET _u(0x0) 8863 #define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) 8864 #define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_MSB _u(8) 8865 #define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_LSB _u(8) 8866 #define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_ACCESS "RW" 8867 // ----------------------------------------------------------------------------- 8868 // Field : IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH 8869 #define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_RESET _u(0x0) 8870 #define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) 8871 #define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_MSB _u(7) 8872 #define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_LSB _u(7) 8873 #define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_ACCESS "RW" 8874 // ----------------------------------------------------------------------------- 8875 // Field : IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW 8876 #define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_RESET _u(0x0) 8877 #define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_BITS _u(0x00000040) 8878 #define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_MSB _u(6) 8879 #define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_LSB _u(6) 8880 #define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_ACCESS "RW" 8881 // ----------------------------------------------------------------------------- 8882 // Field : IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH 8883 #define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_RESET _u(0x0) 8884 #define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) 8885 #define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_MSB _u(5) 8886 #define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_LSB _u(5) 8887 #define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_ACCESS "RW" 8888 // ----------------------------------------------------------------------------- 8889 // Field : IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW 8890 #define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_RESET _u(0x0) 8891 #define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) 8892 #define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_MSB _u(4) 8893 #define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_LSB _u(4) 8894 #define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_ACCESS "RW" 8895 // ----------------------------------------------------------------------------- 8896 // Field : IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH 8897 #define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_RESET _u(0x0) 8898 #define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) 8899 #define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_MSB _u(3) 8900 #define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_LSB _u(3) 8901 #define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_ACCESS "RW" 8902 // ----------------------------------------------------------------------------- 8903 // Field : IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW 8904 #define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_RESET _u(0x0) 8905 #define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_BITS _u(0x00000004) 8906 #define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_MSB _u(2) 8907 #define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_LSB _u(2) 8908 #define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_ACCESS "RW" 8909 // ----------------------------------------------------------------------------- 8910 // Field : IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH 8911 #define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_RESET _u(0x0) 8912 #define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) 8913 #define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_MSB _u(1) 8914 #define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_LSB _u(1) 8915 #define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_ACCESS "RW" 8916 // ----------------------------------------------------------------------------- 8917 // Field : IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW 8918 #define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_RESET _u(0x0) 8919 #define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) 8920 #define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_MSB _u(0) 8921 #define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_LSB _u(0) 8922 #define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_ACCESS "RW" 8923 // ============================================================================= 8924 // Register : IO_BANK0_PROC1_INTE2 8925 // Description : Interrupt Enable for proc1 8926 #define IO_BANK0_PROC1_INTE2_OFFSET _u(0x00000138) 8927 #define IO_BANK0_PROC1_INTE2_BITS _u(0xffffffff) 8928 #define IO_BANK0_PROC1_INTE2_RESET _u(0x00000000) 8929 // ----------------------------------------------------------------------------- 8930 // Field : IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH 8931 #define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_RESET _u(0x0) 8932 #define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) 8933 #define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_MSB _u(31) 8934 #define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_LSB _u(31) 8935 #define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_ACCESS "RW" 8936 // ----------------------------------------------------------------------------- 8937 // Field : IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW 8938 #define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_RESET _u(0x0) 8939 #define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_BITS _u(0x40000000) 8940 #define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_MSB _u(30) 8941 #define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_LSB _u(30) 8942 #define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_ACCESS "RW" 8943 // ----------------------------------------------------------------------------- 8944 // Field : IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH 8945 #define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_RESET _u(0x0) 8946 #define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) 8947 #define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_MSB _u(29) 8948 #define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_LSB _u(29) 8949 #define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_ACCESS "RW" 8950 // ----------------------------------------------------------------------------- 8951 // Field : IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW 8952 #define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_RESET _u(0x0) 8953 #define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) 8954 #define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_MSB _u(28) 8955 #define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_LSB _u(28) 8956 #define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_ACCESS "RW" 8957 // ----------------------------------------------------------------------------- 8958 // Field : IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH 8959 #define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_RESET _u(0x0) 8960 #define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) 8961 #define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_MSB _u(27) 8962 #define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_LSB _u(27) 8963 #define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_ACCESS "RW" 8964 // ----------------------------------------------------------------------------- 8965 // Field : IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW 8966 #define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_RESET _u(0x0) 8967 #define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_BITS _u(0x04000000) 8968 #define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_MSB _u(26) 8969 #define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_LSB _u(26) 8970 #define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_ACCESS "RW" 8971 // ----------------------------------------------------------------------------- 8972 // Field : IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH 8973 #define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_RESET _u(0x0) 8974 #define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) 8975 #define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_MSB _u(25) 8976 #define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_LSB _u(25) 8977 #define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_ACCESS "RW" 8978 // ----------------------------------------------------------------------------- 8979 // Field : IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW 8980 #define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_RESET _u(0x0) 8981 #define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) 8982 #define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_MSB _u(24) 8983 #define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_LSB _u(24) 8984 #define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_ACCESS "RW" 8985 // ----------------------------------------------------------------------------- 8986 // Field : IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH 8987 #define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_RESET _u(0x0) 8988 #define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) 8989 #define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_MSB _u(23) 8990 #define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_LSB _u(23) 8991 #define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_ACCESS "RW" 8992 // ----------------------------------------------------------------------------- 8993 // Field : IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW 8994 #define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_RESET _u(0x0) 8995 #define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_BITS _u(0x00400000) 8996 #define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_MSB _u(22) 8997 #define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_LSB _u(22) 8998 #define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_ACCESS "RW" 8999 // ----------------------------------------------------------------------------- 9000 // Field : IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH 9001 #define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_RESET _u(0x0) 9002 #define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) 9003 #define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_MSB _u(21) 9004 #define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_LSB _u(21) 9005 #define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_ACCESS "RW" 9006 // ----------------------------------------------------------------------------- 9007 // Field : IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW 9008 #define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_RESET _u(0x0) 9009 #define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) 9010 #define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_MSB _u(20) 9011 #define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_LSB _u(20) 9012 #define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_ACCESS "RW" 9013 // ----------------------------------------------------------------------------- 9014 // Field : IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH 9015 #define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_RESET _u(0x0) 9016 #define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) 9017 #define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_MSB _u(19) 9018 #define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_LSB _u(19) 9019 #define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_ACCESS "RW" 9020 // ----------------------------------------------------------------------------- 9021 // Field : IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW 9022 #define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_RESET _u(0x0) 9023 #define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_BITS _u(0x00040000) 9024 #define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_MSB _u(18) 9025 #define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_LSB _u(18) 9026 #define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_ACCESS "RW" 9027 // ----------------------------------------------------------------------------- 9028 // Field : IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH 9029 #define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_RESET _u(0x0) 9030 #define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) 9031 #define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_MSB _u(17) 9032 #define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_LSB _u(17) 9033 #define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_ACCESS "RW" 9034 // ----------------------------------------------------------------------------- 9035 // Field : IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW 9036 #define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_RESET _u(0x0) 9037 #define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) 9038 #define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_MSB _u(16) 9039 #define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_LSB _u(16) 9040 #define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_ACCESS "RW" 9041 // ----------------------------------------------------------------------------- 9042 // Field : IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH 9043 #define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_RESET _u(0x0) 9044 #define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) 9045 #define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_MSB _u(15) 9046 #define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_LSB _u(15) 9047 #define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_ACCESS "RW" 9048 // ----------------------------------------------------------------------------- 9049 // Field : IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW 9050 #define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_RESET _u(0x0) 9051 #define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_BITS _u(0x00004000) 9052 #define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_MSB _u(14) 9053 #define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_LSB _u(14) 9054 #define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_ACCESS "RW" 9055 // ----------------------------------------------------------------------------- 9056 // Field : IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH 9057 #define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_RESET _u(0x0) 9058 #define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) 9059 #define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_MSB _u(13) 9060 #define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_LSB _u(13) 9061 #define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_ACCESS "RW" 9062 // ----------------------------------------------------------------------------- 9063 // Field : IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW 9064 #define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_RESET _u(0x0) 9065 #define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) 9066 #define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_MSB _u(12) 9067 #define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_LSB _u(12) 9068 #define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_ACCESS "RW" 9069 // ----------------------------------------------------------------------------- 9070 // Field : IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH 9071 #define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_RESET _u(0x0) 9072 #define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) 9073 #define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_MSB _u(11) 9074 #define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_LSB _u(11) 9075 #define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_ACCESS "RW" 9076 // ----------------------------------------------------------------------------- 9077 // Field : IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW 9078 #define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_RESET _u(0x0) 9079 #define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_BITS _u(0x00000400) 9080 #define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_MSB _u(10) 9081 #define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_LSB _u(10) 9082 #define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_ACCESS "RW" 9083 // ----------------------------------------------------------------------------- 9084 // Field : IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH 9085 #define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_RESET _u(0x0) 9086 #define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) 9087 #define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_MSB _u(9) 9088 #define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_LSB _u(9) 9089 #define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_ACCESS "RW" 9090 // ----------------------------------------------------------------------------- 9091 // Field : IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW 9092 #define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_RESET _u(0x0) 9093 #define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) 9094 #define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_MSB _u(8) 9095 #define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_LSB _u(8) 9096 #define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_ACCESS "RW" 9097 // ----------------------------------------------------------------------------- 9098 // Field : IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH 9099 #define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_RESET _u(0x0) 9100 #define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) 9101 #define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_MSB _u(7) 9102 #define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_LSB _u(7) 9103 #define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_ACCESS "RW" 9104 // ----------------------------------------------------------------------------- 9105 // Field : IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW 9106 #define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_RESET _u(0x0) 9107 #define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_BITS _u(0x00000040) 9108 #define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_MSB _u(6) 9109 #define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_LSB _u(6) 9110 #define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_ACCESS "RW" 9111 // ----------------------------------------------------------------------------- 9112 // Field : IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH 9113 #define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_RESET _u(0x0) 9114 #define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) 9115 #define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_MSB _u(5) 9116 #define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_LSB _u(5) 9117 #define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_ACCESS "RW" 9118 // ----------------------------------------------------------------------------- 9119 // Field : IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW 9120 #define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_RESET _u(0x0) 9121 #define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) 9122 #define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_MSB _u(4) 9123 #define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_LSB _u(4) 9124 #define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_ACCESS "RW" 9125 // ----------------------------------------------------------------------------- 9126 // Field : IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH 9127 #define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_RESET _u(0x0) 9128 #define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) 9129 #define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_MSB _u(3) 9130 #define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_LSB _u(3) 9131 #define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_ACCESS "RW" 9132 // ----------------------------------------------------------------------------- 9133 // Field : IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW 9134 #define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_RESET _u(0x0) 9135 #define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_BITS _u(0x00000004) 9136 #define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_MSB _u(2) 9137 #define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_LSB _u(2) 9138 #define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_ACCESS "RW" 9139 // ----------------------------------------------------------------------------- 9140 // Field : IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH 9141 #define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_RESET _u(0x0) 9142 #define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) 9143 #define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_MSB _u(1) 9144 #define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_LSB _u(1) 9145 #define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_ACCESS "RW" 9146 // ----------------------------------------------------------------------------- 9147 // Field : IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW 9148 #define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_RESET _u(0x0) 9149 #define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) 9150 #define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_MSB _u(0) 9151 #define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_LSB _u(0) 9152 #define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_ACCESS "RW" 9153 // ============================================================================= 9154 // Register : IO_BANK0_PROC1_INTE3 9155 // Description : Interrupt Enable for proc1 9156 #define IO_BANK0_PROC1_INTE3_OFFSET _u(0x0000013c) 9157 #define IO_BANK0_PROC1_INTE3_BITS _u(0x00ffffff) 9158 #define IO_BANK0_PROC1_INTE3_RESET _u(0x00000000) 9159 // ----------------------------------------------------------------------------- 9160 // Field : IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH 9161 #define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_RESET _u(0x0) 9162 #define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) 9163 #define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_MSB _u(23) 9164 #define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_LSB _u(23) 9165 #define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_ACCESS "RW" 9166 // ----------------------------------------------------------------------------- 9167 // Field : IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW 9168 #define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_RESET _u(0x0) 9169 #define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_BITS _u(0x00400000) 9170 #define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_MSB _u(22) 9171 #define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_LSB _u(22) 9172 #define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_ACCESS "RW" 9173 // ----------------------------------------------------------------------------- 9174 // Field : IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH 9175 #define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_RESET _u(0x0) 9176 #define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) 9177 #define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_MSB _u(21) 9178 #define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_LSB _u(21) 9179 #define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_ACCESS "RW" 9180 // ----------------------------------------------------------------------------- 9181 // Field : IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW 9182 #define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_RESET _u(0x0) 9183 #define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) 9184 #define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_MSB _u(20) 9185 #define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_LSB _u(20) 9186 #define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_ACCESS "RW" 9187 // ----------------------------------------------------------------------------- 9188 // Field : IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH 9189 #define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_RESET _u(0x0) 9190 #define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) 9191 #define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_MSB _u(19) 9192 #define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_LSB _u(19) 9193 #define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_ACCESS "RW" 9194 // ----------------------------------------------------------------------------- 9195 // Field : IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW 9196 #define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_RESET _u(0x0) 9197 #define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_BITS _u(0x00040000) 9198 #define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_MSB _u(18) 9199 #define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_LSB _u(18) 9200 #define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_ACCESS "RW" 9201 // ----------------------------------------------------------------------------- 9202 // Field : IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH 9203 #define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_RESET _u(0x0) 9204 #define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) 9205 #define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_MSB _u(17) 9206 #define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_LSB _u(17) 9207 #define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_ACCESS "RW" 9208 // ----------------------------------------------------------------------------- 9209 // Field : IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW 9210 #define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_RESET _u(0x0) 9211 #define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) 9212 #define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_MSB _u(16) 9213 #define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_LSB _u(16) 9214 #define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_ACCESS "RW" 9215 // ----------------------------------------------------------------------------- 9216 // Field : IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH 9217 #define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_RESET _u(0x0) 9218 #define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) 9219 #define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_MSB _u(15) 9220 #define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_LSB _u(15) 9221 #define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_ACCESS "RW" 9222 // ----------------------------------------------------------------------------- 9223 // Field : IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW 9224 #define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_RESET _u(0x0) 9225 #define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_BITS _u(0x00004000) 9226 #define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_MSB _u(14) 9227 #define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_LSB _u(14) 9228 #define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_ACCESS "RW" 9229 // ----------------------------------------------------------------------------- 9230 // Field : IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH 9231 #define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_RESET _u(0x0) 9232 #define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) 9233 #define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_MSB _u(13) 9234 #define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_LSB _u(13) 9235 #define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_ACCESS "RW" 9236 // ----------------------------------------------------------------------------- 9237 // Field : IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW 9238 #define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_RESET _u(0x0) 9239 #define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) 9240 #define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_MSB _u(12) 9241 #define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_LSB _u(12) 9242 #define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_ACCESS "RW" 9243 // ----------------------------------------------------------------------------- 9244 // Field : IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH 9245 #define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_RESET _u(0x0) 9246 #define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) 9247 #define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_MSB _u(11) 9248 #define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_LSB _u(11) 9249 #define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_ACCESS "RW" 9250 // ----------------------------------------------------------------------------- 9251 // Field : IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW 9252 #define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_RESET _u(0x0) 9253 #define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_BITS _u(0x00000400) 9254 #define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_MSB _u(10) 9255 #define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_LSB _u(10) 9256 #define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_ACCESS "RW" 9257 // ----------------------------------------------------------------------------- 9258 // Field : IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH 9259 #define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_RESET _u(0x0) 9260 #define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) 9261 #define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_MSB _u(9) 9262 #define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_LSB _u(9) 9263 #define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_ACCESS "RW" 9264 // ----------------------------------------------------------------------------- 9265 // Field : IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW 9266 #define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_RESET _u(0x0) 9267 #define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) 9268 #define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_MSB _u(8) 9269 #define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_LSB _u(8) 9270 #define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_ACCESS "RW" 9271 // ----------------------------------------------------------------------------- 9272 // Field : IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH 9273 #define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_RESET _u(0x0) 9274 #define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) 9275 #define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_MSB _u(7) 9276 #define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_LSB _u(7) 9277 #define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_ACCESS "RW" 9278 // ----------------------------------------------------------------------------- 9279 // Field : IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW 9280 #define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_RESET _u(0x0) 9281 #define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_BITS _u(0x00000040) 9282 #define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_MSB _u(6) 9283 #define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_LSB _u(6) 9284 #define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_ACCESS "RW" 9285 // ----------------------------------------------------------------------------- 9286 // Field : IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH 9287 #define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_RESET _u(0x0) 9288 #define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) 9289 #define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_MSB _u(5) 9290 #define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_LSB _u(5) 9291 #define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_ACCESS "RW" 9292 // ----------------------------------------------------------------------------- 9293 // Field : IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW 9294 #define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_RESET _u(0x0) 9295 #define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) 9296 #define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_MSB _u(4) 9297 #define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_LSB _u(4) 9298 #define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_ACCESS "RW" 9299 // ----------------------------------------------------------------------------- 9300 // Field : IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH 9301 #define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_RESET _u(0x0) 9302 #define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) 9303 #define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_MSB _u(3) 9304 #define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_LSB _u(3) 9305 #define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_ACCESS "RW" 9306 // ----------------------------------------------------------------------------- 9307 // Field : IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW 9308 #define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_RESET _u(0x0) 9309 #define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_BITS _u(0x00000004) 9310 #define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_MSB _u(2) 9311 #define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_LSB _u(2) 9312 #define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_ACCESS "RW" 9313 // ----------------------------------------------------------------------------- 9314 // Field : IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH 9315 #define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_RESET _u(0x0) 9316 #define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) 9317 #define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_MSB _u(1) 9318 #define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_LSB _u(1) 9319 #define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_ACCESS "RW" 9320 // ----------------------------------------------------------------------------- 9321 // Field : IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW 9322 #define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_RESET _u(0x0) 9323 #define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) 9324 #define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_MSB _u(0) 9325 #define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_LSB _u(0) 9326 #define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_ACCESS "RW" 9327 // ============================================================================= 9328 // Register : IO_BANK0_PROC1_INTF0 9329 // Description : Interrupt Force for proc1 9330 #define IO_BANK0_PROC1_INTF0_OFFSET _u(0x00000140) 9331 #define IO_BANK0_PROC1_INTF0_BITS _u(0xffffffff) 9332 #define IO_BANK0_PROC1_INTF0_RESET _u(0x00000000) 9333 // ----------------------------------------------------------------------------- 9334 // Field : IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH 9335 #define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_RESET _u(0x0) 9336 #define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) 9337 #define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_MSB _u(31) 9338 #define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_LSB _u(31) 9339 #define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_ACCESS "RW" 9340 // ----------------------------------------------------------------------------- 9341 // Field : IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW 9342 #define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_RESET _u(0x0) 9343 #define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_BITS _u(0x40000000) 9344 #define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_MSB _u(30) 9345 #define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_LSB _u(30) 9346 #define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_ACCESS "RW" 9347 // ----------------------------------------------------------------------------- 9348 // Field : IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH 9349 #define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_RESET _u(0x0) 9350 #define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) 9351 #define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_MSB _u(29) 9352 #define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_LSB _u(29) 9353 #define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_ACCESS "RW" 9354 // ----------------------------------------------------------------------------- 9355 // Field : IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW 9356 #define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_RESET _u(0x0) 9357 #define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) 9358 #define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_MSB _u(28) 9359 #define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_LSB _u(28) 9360 #define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_ACCESS "RW" 9361 // ----------------------------------------------------------------------------- 9362 // Field : IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH 9363 #define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_RESET _u(0x0) 9364 #define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) 9365 #define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_MSB _u(27) 9366 #define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_LSB _u(27) 9367 #define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_ACCESS "RW" 9368 // ----------------------------------------------------------------------------- 9369 // Field : IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW 9370 #define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_RESET _u(0x0) 9371 #define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_BITS _u(0x04000000) 9372 #define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_MSB _u(26) 9373 #define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_LSB _u(26) 9374 #define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_ACCESS "RW" 9375 // ----------------------------------------------------------------------------- 9376 // Field : IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH 9377 #define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_RESET _u(0x0) 9378 #define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) 9379 #define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_MSB _u(25) 9380 #define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_LSB _u(25) 9381 #define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_ACCESS "RW" 9382 // ----------------------------------------------------------------------------- 9383 // Field : IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW 9384 #define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_RESET _u(0x0) 9385 #define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) 9386 #define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_MSB _u(24) 9387 #define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_LSB _u(24) 9388 #define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_ACCESS "RW" 9389 // ----------------------------------------------------------------------------- 9390 // Field : IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH 9391 #define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_RESET _u(0x0) 9392 #define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) 9393 #define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_MSB _u(23) 9394 #define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_LSB _u(23) 9395 #define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_ACCESS "RW" 9396 // ----------------------------------------------------------------------------- 9397 // Field : IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW 9398 #define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_RESET _u(0x0) 9399 #define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_BITS _u(0x00400000) 9400 #define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_MSB _u(22) 9401 #define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_LSB _u(22) 9402 #define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_ACCESS "RW" 9403 // ----------------------------------------------------------------------------- 9404 // Field : IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH 9405 #define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_RESET _u(0x0) 9406 #define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) 9407 #define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_MSB _u(21) 9408 #define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_LSB _u(21) 9409 #define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_ACCESS "RW" 9410 // ----------------------------------------------------------------------------- 9411 // Field : IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW 9412 #define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_RESET _u(0x0) 9413 #define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) 9414 #define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_MSB _u(20) 9415 #define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_LSB _u(20) 9416 #define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_ACCESS "RW" 9417 // ----------------------------------------------------------------------------- 9418 // Field : IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH 9419 #define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_RESET _u(0x0) 9420 #define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) 9421 #define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_MSB _u(19) 9422 #define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_LSB _u(19) 9423 #define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_ACCESS "RW" 9424 // ----------------------------------------------------------------------------- 9425 // Field : IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW 9426 #define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_RESET _u(0x0) 9427 #define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_BITS _u(0x00040000) 9428 #define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_MSB _u(18) 9429 #define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_LSB _u(18) 9430 #define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_ACCESS "RW" 9431 // ----------------------------------------------------------------------------- 9432 // Field : IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH 9433 #define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_RESET _u(0x0) 9434 #define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) 9435 #define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_MSB _u(17) 9436 #define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_LSB _u(17) 9437 #define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_ACCESS "RW" 9438 // ----------------------------------------------------------------------------- 9439 // Field : IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW 9440 #define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_RESET _u(0x0) 9441 #define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) 9442 #define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_MSB _u(16) 9443 #define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_LSB _u(16) 9444 #define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_ACCESS "RW" 9445 // ----------------------------------------------------------------------------- 9446 // Field : IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH 9447 #define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_RESET _u(0x0) 9448 #define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) 9449 #define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_MSB _u(15) 9450 #define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_LSB _u(15) 9451 #define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_ACCESS "RW" 9452 // ----------------------------------------------------------------------------- 9453 // Field : IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW 9454 #define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_RESET _u(0x0) 9455 #define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_BITS _u(0x00004000) 9456 #define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_MSB _u(14) 9457 #define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_LSB _u(14) 9458 #define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_ACCESS "RW" 9459 // ----------------------------------------------------------------------------- 9460 // Field : IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH 9461 #define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_RESET _u(0x0) 9462 #define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) 9463 #define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_MSB _u(13) 9464 #define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_LSB _u(13) 9465 #define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_ACCESS "RW" 9466 // ----------------------------------------------------------------------------- 9467 // Field : IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW 9468 #define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_RESET _u(0x0) 9469 #define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) 9470 #define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_MSB _u(12) 9471 #define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_LSB _u(12) 9472 #define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_ACCESS "RW" 9473 // ----------------------------------------------------------------------------- 9474 // Field : IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH 9475 #define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_RESET _u(0x0) 9476 #define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) 9477 #define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_MSB _u(11) 9478 #define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_LSB _u(11) 9479 #define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_ACCESS "RW" 9480 // ----------------------------------------------------------------------------- 9481 // Field : IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW 9482 #define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_RESET _u(0x0) 9483 #define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_BITS _u(0x00000400) 9484 #define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_MSB _u(10) 9485 #define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_LSB _u(10) 9486 #define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_ACCESS "RW" 9487 // ----------------------------------------------------------------------------- 9488 // Field : IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH 9489 #define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_RESET _u(0x0) 9490 #define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) 9491 #define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_MSB _u(9) 9492 #define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_LSB _u(9) 9493 #define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_ACCESS "RW" 9494 // ----------------------------------------------------------------------------- 9495 // Field : IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW 9496 #define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_RESET _u(0x0) 9497 #define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) 9498 #define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_MSB _u(8) 9499 #define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_LSB _u(8) 9500 #define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_ACCESS "RW" 9501 // ----------------------------------------------------------------------------- 9502 // Field : IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH 9503 #define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_RESET _u(0x0) 9504 #define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) 9505 #define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_MSB _u(7) 9506 #define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_LSB _u(7) 9507 #define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_ACCESS "RW" 9508 // ----------------------------------------------------------------------------- 9509 // Field : IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW 9510 #define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_RESET _u(0x0) 9511 #define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_BITS _u(0x00000040) 9512 #define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_MSB _u(6) 9513 #define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_LSB _u(6) 9514 #define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_ACCESS "RW" 9515 // ----------------------------------------------------------------------------- 9516 // Field : IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH 9517 #define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_RESET _u(0x0) 9518 #define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) 9519 #define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_MSB _u(5) 9520 #define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_LSB _u(5) 9521 #define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_ACCESS "RW" 9522 // ----------------------------------------------------------------------------- 9523 // Field : IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW 9524 #define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_RESET _u(0x0) 9525 #define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) 9526 #define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_MSB _u(4) 9527 #define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_LSB _u(4) 9528 #define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_ACCESS "RW" 9529 // ----------------------------------------------------------------------------- 9530 // Field : IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH 9531 #define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_RESET _u(0x0) 9532 #define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) 9533 #define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_MSB _u(3) 9534 #define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_LSB _u(3) 9535 #define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_ACCESS "RW" 9536 // ----------------------------------------------------------------------------- 9537 // Field : IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW 9538 #define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_RESET _u(0x0) 9539 #define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_BITS _u(0x00000004) 9540 #define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_MSB _u(2) 9541 #define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_LSB _u(2) 9542 #define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_ACCESS "RW" 9543 // ----------------------------------------------------------------------------- 9544 // Field : IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH 9545 #define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_RESET _u(0x0) 9546 #define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) 9547 #define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_MSB _u(1) 9548 #define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_LSB _u(1) 9549 #define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_ACCESS "RW" 9550 // ----------------------------------------------------------------------------- 9551 // Field : IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW 9552 #define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_RESET _u(0x0) 9553 #define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) 9554 #define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_MSB _u(0) 9555 #define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_LSB _u(0) 9556 #define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_ACCESS "RW" 9557 // ============================================================================= 9558 // Register : IO_BANK0_PROC1_INTF1 9559 // Description : Interrupt Force for proc1 9560 #define IO_BANK0_PROC1_INTF1_OFFSET _u(0x00000144) 9561 #define IO_BANK0_PROC1_INTF1_BITS _u(0xffffffff) 9562 #define IO_BANK0_PROC1_INTF1_RESET _u(0x00000000) 9563 // ----------------------------------------------------------------------------- 9564 // Field : IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH 9565 #define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_RESET _u(0x0) 9566 #define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) 9567 #define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_MSB _u(31) 9568 #define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_LSB _u(31) 9569 #define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_ACCESS "RW" 9570 // ----------------------------------------------------------------------------- 9571 // Field : IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW 9572 #define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_RESET _u(0x0) 9573 #define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_BITS _u(0x40000000) 9574 #define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_MSB _u(30) 9575 #define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_LSB _u(30) 9576 #define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_ACCESS "RW" 9577 // ----------------------------------------------------------------------------- 9578 // Field : IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH 9579 #define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_RESET _u(0x0) 9580 #define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) 9581 #define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_MSB _u(29) 9582 #define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_LSB _u(29) 9583 #define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_ACCESS "RW" 9584 // ----------------------------------------------------------------------------- 9585 // Field : IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW 9586 #define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_RESET _u(0x0) 9587 #define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) 9588 #define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_MSB _u(28) 9589 #define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_LSB _u(28) 9590 #define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_ACCESS "RW" 9591 // ----------------------------------------------------------------------------- 9592 // Field : IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH 9593 #define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_RESET _u(0x0) 9594 #define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) 9595 #define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_MSB _u(27) 9596 #define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_LSB _u(27) 9597 #define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_ACCESS "RW" 9598 // ----------------------------------------------------------------------------- 9599 // Field : IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW 9600 #define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_RESET _u(0x0) 9601 #define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_BITS _u(0x04000000) 9602 #define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_MSB _u(26) 9603 #define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_LSB _u(26) 9604 #define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_ACCESS "RW" 9605 // ----------------------------------------------------------------------------- 9606 // Field : IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH 9607 #define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_RESET _u(0x0) 9608 #define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) 9609 #define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_MSB _u(25) 9610 #define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_LSB _u(25) 9611 #define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_ACCESS "RW" 9612 // ----------------------------------------------------------------------------- 9613 // Field : IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW 9614 #define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_RESET _u(0x0) 9615 #define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) 9616 #define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_MSB _u(24) 9617 #define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_LSB _u(24) 9618 #define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_ACCESS "RW" 9619 // ----------------------------------------------------------------------------- 9620 // Field : IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH 9621 #define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_RESET _u(0x0) 9622 #define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) 9623 #define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_MSB _u(23) 9624 #define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_LSB _u(23) 9625 #define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_ACCESS "RW" 9626 // ----------------------------------------------------------------------------- 9627 // Field : IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW 9628 #define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_RESET _u(0x0) 9629 #define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_BITS _u(0x00400000) 9630 #define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_MSB _u(22) 9631 #define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_LSB _u(22) 9632 #define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_ACCESS "RW" 9633 // ----------------------------------------------------------------------------- 9634 // Field : IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH 9635 #define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_RESET _u(0x0) 9636 #define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) 9637 #define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_MSB _u(21) 9638 #define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_LSB _u(21) 9639 #define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_ACCESS "RW" 9640 // ----------------------------------------------------------------------------- 9641 // Field : IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW 9642 #define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_RESET _u(0x0) 9643 #define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) 9644 #define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_MSB _u(20) 9645 #define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_LSB _u(20) 9646 #define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_ACCESS "RW" 9647 // ----------------------------------------------------------------------------- 9648 // Field : IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH 9649 #define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_RESET _u(0x0) 9650 #define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) 9651 #define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_MSB _u(19) 9652 #define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_LSB _u(19) 9653 #define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_ACCESS "RW" 9654 // ----------------------------------------------------------------------------- 9655 // Field : IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW 9656 #define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_RESET _u(0x0) 9657 #define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_BITS _u(0x00040000) 9658 #define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_MSB _u(18) 9659 #define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_LSB _u(18) 9660 #define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_ACCESS "RW" 9661 // ----------------------------------------------------------------------------- 9662 // Field : IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH 9663 #define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_RESET _u(0x0) 9664 #define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) 9665 #define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_MSB _u(17) 9666 #define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_LSB _u(17) 9667 #define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_ACCESS "RW" 9668 // ----------------------------------------------------------------------------- 9669 // Field : IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW 9670 #define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_RESET _u(0x0) 9671 #define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) 9672 #define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_MSB _u(16) 9673 #define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_LSB _u(16) 9674 #define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_ACCESS "RW" 9675 // ----------------------------------------------------------------------------- 9676 // Field : IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH 9677 #define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_RESET _u(0x0) 9678 #define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) 9679 #define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_MSB _u(15) 9680 #define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_LSB _u(15) 9681 #define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_ACCESS "RW" 9682 // ----------------------------------------------------------------------------- 9683 // Field : IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW 9684 #define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_RESET _u(0x0) 9685 #define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_BITS _u(0x00004000) 9686 #define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_MSB _u(14) 9687 #define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_LSB _u(14) 9688 #define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_ACCESS "RW" 9689 // ----------------------------------------------------------------------------- 9690 // Field : IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH 9691 #define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_RESET _u(0x0) 9692 #define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) 9693 #define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_MSB _u(13) 9694 #define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_LSB _u(13) 9695 #define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_ACCESS "RW" 9696 // ----------------------------------------------------------------------------- 9697 // Field : IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW 9698 #define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_RESET _u(0x0) 9699 #define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) 9700 #define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_MSB _u(12) 9701 #define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_LSB _u(12) 9702 #define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_ACCESS "RW" 9703 // ----------------------------------------------------------------------------- 9704 // Field : IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH 9705 #define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_RESET _u(0x0) 9706 #define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) 9707 #define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_MSB _u(11) 9708 #define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_LSB _u(11) 9709 #define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_ACCESS "RW" 9710 // ----------------------------------------------------------------------------- 9711 // Field : IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW 9712 #define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_RESET _u(0x0) 9713 #define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_BITS _u(0x00000400) 9714 #define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_MSB _u(10) 9715 #define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_LSB _u(10) 9716 #define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_ACCESS "RW" 9717 // ----------------------------------------------------------------------------- 9718 // Field : IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH 9719 #define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_RESET _u(0x0) 9720 #define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) 9721 #define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_MSB _u(9) 9722 #define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_LSB _u(9) 9723 #define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_ACCESS "RW" 9724 // ----------------------------------------------------------------------------- 9725 // Field : IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW 9726 #define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_RESET _u(0x0) 9727 #define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) 9728 #define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_MSB _u(8) 9729 #define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_LSB _u(8) 9730 #define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_ACCESS "RW" 9731 // ----------------------------------------------------------------------------- 9732 // Field : IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH 9733 #define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_RESET _u(0x0) 9734 #define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) 9735 #define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_MSB _u(7) 9736 #define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_LSB _u(7) 9737 #define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_ACCESS "RW" 9738 // ----------------------------------------------------------------------------- 9739 // Field : IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW 9740 #define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_RESET _u(0x0) 9741 #define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_BITS _u(0x00000040) 9742 #define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_MSB _u(6) 9743 #define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_LSB _u(6) 9744 #define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_ACCESS "RW" 9745 // ----------------------------------------------------------------------------- 9746 // Field : IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH 9747 #define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_RESET _u(0x0) 9748 #define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) 9749 #define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_MSB _u(5) 9750 #define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_LSB _u(5) 9751 #define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_ACCESS "RW" 9752 // ----------------------------------------------------------------------------- 9753 // Field : IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW 9754 #define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_RESET _u(0x0) 9755 #define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) 9756 #define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_MSB _u(4) 9757 #define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_LSB _u(4) 9758 #define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_ACCESS "RW" 9759 // ----------------------------------------------------------------------------- 9760 // Field : IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH 9761 #define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_RESET _u(0x0) 9762 #define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) 9763 #define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_MSB _u(3) 9764 #define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_LSB _u(3) 9765 #define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_ACCESS "RW" 9766 // ----------------------------------------------------------------------------- 9767 // Field : IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW 9768 #define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_RESET _u(0x0) 9769 #define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_BITS _u(0x00000004) 9770 #define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_MSB _u(2) 9771 #define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_LSB _u(2) 9772 #define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_ACCESS "RW" 9773 // ----------------------------------------------------------------------------- 9774 // Field : IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH 9775 #define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_RESET _u(0x0) 9776 #define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) 9777 #define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_MSB _u(1) 9778 #define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_LSB _u(1) 9779 #define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_ACCESS "RW" 9780 // ----------------------------------------------------------------------------- 9781 // Field : IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW 9782 #define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_RESET _u(0x0) 9783 #define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) 9784 #define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_MSB _u(0) 9785 #define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_LSB _u(0) 9786 #define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_ACCESS "RW" 9787 // ============================================================================= 9788 // Register : IO_BANK0_PROC1_INTF2 9789 // Description : Interrupt Force for proc1 9790 #define IO_BANK0_PROC1_INTF2_OFFSET _u(0x00000148) 9791 #define IO_BANK0_PROC1_INTF2_BITS _u(0xffffffff) 9792 #define IO_BANK0_PROC1_INTF2_RESET _u(0x00000000) 9793 // ----------------------------------------------------------------------------- 9794 // Field : IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH 9795 #define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_RESET _u(0x0) 9796 #define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) 9797 #define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_MSB _u(31) 9798 #define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_LSB _u(31) 9799 #define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_ACCESS "RW" 9800 // ----------------------------------------------------------------------------- 9801 // Field : IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW 9802 #define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_RESET _u(0x0) 9803 #define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_BITS _u(0x40000000) 9804 #define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_MSB _u(30) 9805 #define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_LSB _u(30) 9806 #define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_ACCESS "RW" 9807 // ----------------------------------------------------------------------------- 9808 // Field : IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH 9809 #define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_RESET _u(0x0) 9810 #define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) 9811 #define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_MSB _u(29) 9812 #define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_LSB _u(29) 9813 #define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_ACCESS "RW" 9814 // ----------------------------------------------------------------------------- 9815 // Field : IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW 9816 #define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_RESET _u(0x0) 9817 #define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) 9818 #define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_MSB _u(28) 9819 #define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_LSB _u(28) 9820 #define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_ACCESS "RW" 9821 // ----------------------------------------------------------------------------- 9822 // Field : IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH 9823 #define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_RESET _u(0x0) 9824 #define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) 9825 #define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_MSB _u(27) 9826 #define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_LSB _u(27) 9827 #define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_ACCESS "RW" 9828 // ----------------------------------------------------------------------------- 9829 // Field : IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW 9830 #define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_RESET _u(0x0) 9831 #define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_BITS _u(0x04000000) 9832 #define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_MSB _u(26) 9833 #define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_LSB _u(26) 9834 #define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_ACCESS "RW" 9835 // ----------------------------------------------------------------------------- 9836 // Field : IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH 9837 #define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_RESET _u(0x0) 9838 #define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) 9839 #define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_MSB _u(25) 9840 #define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_LSB _u(25) 9841 #define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_ACCESS "RW" 9842 // ----------------------------------------------------------------------------- 9843 // Field : IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW 9844 #define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_RESET _u(0x0) 9845 #define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) 9846 #define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_MSB _u(24) 9847 #define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_LSB _u(24) 9848 #define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_ACCESS "RW" 9849 // ----------------------------------------------------------------------------- 9850 // Field : IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH 9851 #define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_RESET _u(0x0) 9852 #define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) 9853 #define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_MSB _u(23) 9854 #define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_LSB _u(23) 9855 #define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_ACCESS "RW" 9856 // ----------------------------------------------------------------------------- 9857 // Field : IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW 9858 #define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_RESET _u(0x0) 9859 #define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_BITS _u(0x00400000) 9860 #define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_MSB _u(22) 9861 #define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_LSB _u(22) 9862 #define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_ACCESS "RW" 9863 // ----------------------------------------------------------------------------- 9864 // Field : IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH 9865 #define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_RESET _u(0x0) 9866 #define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) 9867 #define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_MSB _u(21) 9868 #define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_LSB _u(21) 9869 #define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_ACCESS "RW" 9870 // ----------------------------------------------------------------------------- 9871 // Field : IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW 9872 #define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_RESET _u(0x0) 9873 #define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) 9874 #define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_MSB _u(20) 9875 #define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_LSB _u(20) 9876 #define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_ACCESS "RW" 9877 // ----------------------------------------------------------------------------- 9878 // Field : IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH 9879 #define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_RESET _u(0x0) 9880 #define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) 9881 #define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_MSB _u(19) 9882 #define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_LSB _u(19) 9883 #define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_ACCESS "RW" 9884 // ----------------------------------------------------------------------------- 9885 // Field : IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW 9886 #define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_RESET _u(0x0) 9887 #define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_BITS _u(0x00040000) 9888 #define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_MSB _u(18) 9889 #define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_LSB _u(18) 9890 #define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_ACCESS "RW" 9891 // ----------------------------------------------------------------------------- 9892 // Field : IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH 9893 #define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_RESET _u(0x0) 9894 #define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) 9895 #define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_MSB _u(17) 9896 #define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_LSB _u(17) 9897 #define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_ACCESS "RW" 9898 // ----------------------------------------------------------------------------- 9899 // Field : IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW 9900 #define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_RESET _u(0x0) 9901 #define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) 9902 #define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_MSB _u(16) 9903 #define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_LSB _u(16) 9904 #define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_ACCESS "RW" 9905 // ----------------------------------------------------------------------------- 9906 // Field : IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH 9907 #define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_RESET _u(0x0) 9908 #define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) 9909 #define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_MSB _u(15) 9910 #define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_LSB _u(15) 9911 #define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_ACCESS "RW" 9912 // ----------------------------------------------------------------------------- 9913 // Field : IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW 9914 #define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_RESET _u(0x0) 9915 #define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_BITS _u(0x00004000) 9916 #define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_MSB _u(14) 9917 #define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_LSB _u(14) 9918 #define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_ACCESS "RW" 9919 // ----------------------------------------------------------------------------- 9920 // Field : IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH 9921 #define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_RESET _u(0x0) 9922 #define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) 9923 #define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_MSB _u(13) 9924 #define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_LSB _u(13) 9925 #define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_ACCESS "RW" 9926 // ----------------------------------------------------------------------------- 9927 // Field : IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW 9928 #define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_RESET _u(0x0) 9929 #define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) 9930 #define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_MSB _u(12) 9931 #define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_LSB _u(12) 9932 #define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_ACCESS "RW" 9933 // ----------------------------------------------------------------------------- 9934 // Field : IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH 9935 #define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_RESET _u(0x0) 9936 #define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) 9937 #define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_MSB _u(11) 9938 #define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_LSB _u(11) 9939 #define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_ACCESS "RW" 9940 // ----------------------------------------------------------------------------- 9941 // Field : IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW 9942 #define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_RESET _u(0x0) 9943 #define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_BITS _u(0x00000400) 9944 #define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_MSB _u(10) 9945 #define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_LSB _u(10) 9946 #define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_ACCESS "RW" 9947 // ----------------------------------------------------------------------------- 9948 // Field : IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH 9949 #define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_RESET _u(0x0) 9950 #define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) 9951 #define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_MSB _u(9) 9952 #define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_LSB _u(9) 9953 #define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_ACCESS "RW" 9954 // ----------------------------------------------------------------------------- 9955 // Field : IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW 9956 #define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_RESET _u(0x0) 9957 #define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) 9958 #define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_MSB _u(8) 9959 #define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_LSB _u(8) 9960 #define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_ACCESS "RW" 9961 // ----------------------------------------------------------------------------- 9962 // Field : IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH 9963 #define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_RESET _u(0x0) 9964 #define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) 9965 #define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_MSB _u(7) 9966 #define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_LSB _u(7) 9967 #define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_ACCESS "RW" 9968 // ----------------------------------------------------------------------------- 9969 // Field : IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW 9970 #define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_RESET _u(0x0) 9971 #define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_BITS _u(0x00000040) 9972 #define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_MSB _u(6) 9973 #define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_LSB _u(6) 9974 #define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_ACCESS "RW" 9975 // ----------------------------------------------------------------------------- 9976 // Field : IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH 9977 #define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_RESET _u(0x0) 9978 #define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) 9979 #define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_MSB _u(5) 9980 #define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_LSB _u(5) 9981 #define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_ACCESS "RW" 9982 // ----------------------------------------------------------------------------- 9983 // Field : IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW 9984 #define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_RESET _u(0x0) 9985 #define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) 9986 #define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_MSB _u(4) 9987 #define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_LSB _u(4) 9988 #define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_ACCESS "RW" 9989 // ----------------------------------------------------------------------------- 9990 // Field : IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH 9991 #define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_RESET _u(0x0) 9992 #define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) 9993 #define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_MSB _u(3) 9994 #define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_LSB _u(3) 9995 #define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_ACCESS "RW" 9996 // ----------------------------------------------------------------------------- 9997 // Field : IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW 9998 #define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_RESET _u(0x0) 9999 #define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_BITS _u(0x00000004) 10000 #define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_MSB _u(2) 10001 #define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_LSB _u(2) 10002 #define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_ACCESS "RW" 10003 // ----------------------------------------------------------------------------- 10004 // Field : IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH 10005 #define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_RESET _u(0x0) 10006 #define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) 10007 #define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_MSB _u(1) 10008 #define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_LSB _u(1) 10009 #define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_ACCESS "RW" 10010 // ----------------------------------------------------------------------------- 10011 // Field : IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW 10012 #define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_RESET _u(0x0) 10013 #define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) 10014 #define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_MSB _u(0) 10015 #define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_LSB _u(0) 10016 #define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_ACCESS "RW" 10017 // ============================================================================= 10018 // Register : IO_BANK0_PROC1_INTF3 10019 // Description : Interrupt Force for proc1 10020 #define IO_BANK0_PROC1_INTF3_OFFSET _u(0x0000014c) 10021 #define IO_BANK0_PROC1_INTF3_BITS _u(0x00ffffff) 10022 #define IO_BANK0_PROC1_INTF3_RESET _u(0x00000000) 10023 // ----------------------------------------------------------------------------- 10024 // Field : IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH 10025 #define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_RESET _u(0x0) 10026 #define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) 10027 #define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_MSB _u(23) 10028 #define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_LSB _u(23) 10029 #define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_ACCESS "RW" 10030 // ----------------------------------------------------------------------------- 10031 // Field : IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW 10032 #define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_RESET _u(0x0) 10033 #define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_BITS _u(0x00400000) 10034 #define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_MSB _u(22) 10035 #define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_LSB _u(22) 10036 #define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_ACCESS "RW" 10037 // ----------------------------------------------------------------------------- 10038 // Field : IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH 10039 #define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_RESET _u(0x0) 10040 #define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) 10041 #define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_MSB _u(21) 10042 #define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_LSB _u(21) 10043 #define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_ACCESS "RW" 10044 // ----------------------------------------------------------------------------- 10045 // Field : IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW 10046 #define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_RESET _u(0x0) 10047 #define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) 10048 #define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_MSB _u(20) 10049 #define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_LSB _u(20) 10050 #define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_ACCESS "RW" 10051 // ----------------------------------------------------------------------------- 10052 // Field : IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH 10053 #define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_RESET _u(0x0) 10054 #define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) 10055 #define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_MSB _u(19) 10056 #define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_LSB _u(19) 10057 #define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_ACCESS "RW" 10058 // ----------------------------------------------------------------------------- 10059 // Field : IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW 10060 #define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_RESET _u(0x0) 10061 #define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_BITS _u(0x00040000) 10062 #define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_MSB _u(18) 10063 #define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_LSB _u(18) 10064 #define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_ACCESS "RW" 10065 // ----------------------------------------------------------------------------- 10066 // Field : IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH 10067 #define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_RESET _u(0x0) 10068 #define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) 10069 #define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_MSB _u(17) 10070 #define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_LSB _u(17) 10071 #define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_ACCESS "RW" 10072 // ----------------------------------------------------------------------------- 10073 // Field : IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW 10074 #define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_RESET _u(0x0) 10075 #define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) 10076 #define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_MSB _u(16) 10077 #define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_LSB _u(16) 10078 #define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_ACCESS "RW" 10079 // ----------------------------------------------------------------------------- 10080 // Field : IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH 10081 #define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_RESET _u(0x0) 10082 #define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) 10083 #define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_MSB _u(15) 10084 #define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_LSB _u(15) 10085 #define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_ACCESS "RW" 10086 // ----------------------------------------------------------------------------- 10087 // Field : IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW 10088 #define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_RESET _u(0x0) 10089 #define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_BITS _u(0x00004000) 10090 #define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_MSB _u(14) 10091 #define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_LSB _u(14) 10092 #define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_ACCESS "RW" 10093 // ----------------------------------------------------------------------------- 10094 // Field : IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH 10095 #define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_RESET _u(0x0) 10096 #define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) 10097 #define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_MSB _u(13) 10098 #define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_LSB _u(13) 10099 #define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_ACCESS "RW" 10100 // ----------------------------------------------------------------------------- 10101 // Field : IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW 10102 #define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_RESET _u(0x0) 10103 #define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) 10104 #define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_MSB _u(12) 10105 #define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_LSB _u(12) 10106 #define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_ACCESS "RW" 10107 // ----------------------------------------------------------------------------- 10108 // Field : IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH 10109 #define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_RESET _u(0x0) 10110 #define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) 10111 #define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_MSB _u(11) 10112 #define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_LSB _u(11) 10113 #define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_ACCESS "RW" 10114 // ----------------------------------------------------------------------------- 10115 // Field : IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW 10116 #define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_RESET _u(0x0) 10117 #define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_BITS _u(0x00000400) 10118 #define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_MSB _u(10) 10119 #define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_LSB _u(10) 10120 #define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_ACCESS "RW" 10121 // ----------------------------------------------------------------------------- 10122 // Field : IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH 10123 #define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_RESET _u(0x0) 10124 #define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) 10125 #define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_MSB _u(9) 10126 #define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_LSB _u(9) 10127 #define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_ACCESS "RW" 10128 // ----------------------------------------------------------------------------- 10129 // Field : IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW 10130 #define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_RESET _u(0x0) 10131 #define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) 10132 #define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_MSB _u(8) 10133 #define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_LSB _u(8) 10134 #define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_ACCESS "RW" 10135 // ----------------------------------------------------------------------------- 10136 // Field : IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH 10137 #define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_RESET _u(0x0) 10138 #define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) 10139 #define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_MSB _u(7) 10140 #define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_LSB _u(7) 10141 #define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_ACCESS "RW" 10142 // ----------------------------------------------------------------------------- 10143 // Field : IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW 10144 #define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_RESET _u(0x0) 10145 #define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_BITS _u(0x00000040) 10146 #define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_MSB _u(6) 10147 #define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_LSB _u(6) 10148 #define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_ACCESS "RW" 10149 // ----------------------------------------------------------------------------- 10150 // Field : IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH 10151 #define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_RESET _u(0x0) 10152 #define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) 10153 #define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_MSB _u(5) 10154 #define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_LSB _u(5) 10155 #define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_ACCESS "RW" 10156 // ----------------------------------------------------------------------------- 10157 // Field : IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW 10158 #define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_RESET _u(0x0) 10159 #define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) 10160 #define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_MSB _u(4) 10161 #define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_LSB _u(4) 10162 #define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_ACCESS "RW" 10163 // ----------------------------------------------------------------------------- 10164 // Field : IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH 10165 #define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_RESET _u(0x0) 10166 #define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) 10167 #define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_MSB _u(3) 10168 #define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_LSB _u(3) 10169 #define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_ACCESS "RW" 10170 // ----------------------------------------------------------------------------- 10171 // Field : IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW 10172 #define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_RESET _u(0x0) 10173 #define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_BITS _u(0x00000004) 10174 #define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_MSB _u(2) 10175 #define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_LSB _u(2) 10176 #define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_ACCESS "RW" 10177 // ----------------------------------------------------------------------------- 10178 // Field : IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH 10179 #define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_RESET _u(0x0) 10180 #define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) 10181 #define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_MSB _u(1) 10182 #define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_LSB _u(1) 10183 #define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_ACCESS "RW" 10184 // ----------------------------------------------------------------------------- 10185 // Field : IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW 10186 #define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_RESET _u(0x0) 10187 #define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) 10188 #define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_MSB _u(0) 10189 #define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_LSB _u(0) 10190 #define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_ACCESS "RW" 10191 // ============================================================================= 10192 // Register : IO_BANK0_PROC1_INTS0 10193 // Description : Interrupt status after masking & forcing for proc1 10194 #define IO_BANK0_PROC1_INTS0_OFFSET _u(0x00000150) 10195 #define IO_BANK0_PROC1_INTS0_BITS _u(0xffffffff) 10196 #define IO_BANK0_PROC1_INTS0_RESET _u(0x00000000) 10197 // ----------------------------------------------------------------------------- 10198 // Field : IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH 10199 #define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_RESET _u(0x0) 10200 #define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) 10201 #define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_MSB _u(31) 10202 #define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_LSB _u(31) 10203 #define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_ACCESS "RO" 10204 // ----------------------------------------------------------------------------- 10205 // Field : IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW 10206 #define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_RESET _u(0x0) 10207 #define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_BITS _u(0x40000000) 10208 #define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_MSB _u(30) 10209 #define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_LSB _u(30) 10210 #define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_ACCESS "RO" 10211 // ----------------------------------------------------------------------------- 10212 // Field : IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH 10213 #define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_RESET _u(0x0) 10214 #define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) 10215 #define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_MSB _u(29) 10216 #define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_LSB _u(29) 10217 #define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_ACCESS "RO" 10218 // ----------------------------------------------------------------------------- 10219 // Field : IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW 10220 #define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_RESET _u(0x0) 10221 #define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) 10222 #define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_MSB _u(28) 10223 #define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_LSB _u(28) 10224 #define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_ACCESS "RO" 10225 // ----------------------------------------------------------------------------- 10226 // Field : IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH 10227 #define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_RESET _u(0x0) 10228 #define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) 10229 #define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_MSB _u(27) 10230 #define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_LSB _u(27) 10231 #define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_ACCESS "RO" 10232 // ----------------------------------------------------------------------------- 10233 // Field : IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW 10234 #define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_RESET _u(0x0) 10235 #define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_BITS _u(0x04000000) 10236 #define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_MSB _u(26) 10237 #define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_LSB _u(26) 10238 #define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_ACCESS "RO" 10239 // ----------------------------------------------------------------------------- 10240 // Field : IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH 10241 #define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_RESET _u(0x0) 10242 #define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) 10243 #define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_MSB _u(25) 10244 #define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_LSB _u(25) 10245 #define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_ACCESS "RO" 10246 // ----------------------------------------------------------------------------- 10247 // Field : IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW 10248 #define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_RESET _u(0x0) 10249 #define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) 10250 #define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_MSB _u(24) 10251 #define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_LSB _u(24) 10252 #define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_ACCESS "RO" 10253 // ----------------------------------------------------------------------------- 10254 // Field : IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH 10255 #define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_RESET _u(0x0) 10256 #define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) 10257 #define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_MSB _u(23) 10258 #define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_LSB _u(23) 10259 #define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_ACCESS "RO" 10260 // ----------------------------------------------------------------------------- 10261 // Field : IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW 10262 #define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_RESET _u(0x0) 10263 #define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_BITS _u(0x00400000) 10264 #define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_MSB _u(22) 10265 #define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_LSB _u(22) 10266 #define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_ACCESS "RO" 10267 // ----------------------------------------------------------------------------- 10268 // Field : IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH 10269 #define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_RESET _u(0x0) 10270 #define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) 10271 #define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_MSB _u(21) 10272 #define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_LSB _u(21) 10273 #define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_ACCESS "RO" 10274 // ----------------------------------------------------------------------------- 10275 // Field : IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW 10276 #define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_RESET _u(0x0) 10277 #define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) 10278 #define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_MSB _u(20) 10279 #define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_LSB _u(20) 10280 #define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_ACCESS "RO" 10281 // ----------------------------------------------------------------------------- 10282 // Field : IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH 10283 #define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_RESET _u(0x0) 10284 #define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) 10285 #define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_MSB _u(19) 10286 #define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_LSB _u(19) 10287 #define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_ACCESS "RO" 10288 // ----------------------------------------------------------------------------- 10289 // Field : IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW 10290 #define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_RESET _u(0x0) 10291 #define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_BITS _u(0x00040000) 10292 #define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_MSB _u(18) 10293 #define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_LSB _u(18) 10294 #define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_ACCESS "RO" 10295 // ----------------------------------------------------------------------------- 10296 // Field : IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH 10297 #define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_RESET _u(0x0) 10298 #define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) 10299 #define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_MSB _u(17) 10300 #define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_LSB _u(17) 10301 #define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_ACCESS "RO" 10302 // ----------------------------------------------------------------------------- 10303 // Field : IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW 10304 #define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_RESET _u(0x0) 10305 #define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) 10306 #define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_MSB _u(16) 10307 #define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_LSB _u(16) 10308 #define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_ACCESS "RO" 10309 // ----------------------------------------------------------------------------- 10310 // Field : IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH 10311 #define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_RESET _u(0x0) 10312 #define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) 10313 #define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_MSB _u(15) 10314 #define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_LSB _u(15) 10315 #define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_ACCESS "RO" 10316 // ----------------------------------------------------------------------------- 10317 // Field : IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW 10318 #define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_RESET _u(0x0) 10319 #define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_BITS _u(0x00004000) 10320 #define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_MSB _u(14) 10321 #define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_LSB _u(14) 10322 #define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_ACCESS "RO" 10323 // ----------------------------------------------------------------------------- 10324 // Field : IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH 10325 #define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_RESET _u(0x0) 10326 #define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) 10327 #define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_MSB _u(13) 10328 #define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_LSB _u(13) 10329 #define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_ACCESS "RO" 10330 // ----------------------------------------------------------------------------- 10331 // Field : IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW 10332 #define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_RESET _u(0x0) 10333 #define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) 10334 #define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_MSB _u(12) 10335 #define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_LSB _u(12) 10336 #define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_ACCESS "RO" 10337 // ----------------------------------------------------------------------------- 10338 // Field : IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH 10339 #define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_RESET _u(0x0) 10340 #define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) 10341 #define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_MSB _u(11) 10342 #define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_LSB _u(11) 10343 #define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_ACCESS "RO" 10344 // ----------------------------------------------------------------------------- 10345 // Field : IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW 10346 #define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_RESET _u(0x0) 10347 #define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_BITS _u(0x00000400) 10348 #define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_MSB _u(10) 10349 #define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_LSB _u(10) 10350 #define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_ACCESS "RO" 10351 // ----------------------------------------------------------------------------- 10352 // Field : IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH 10353 #define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_RESET _u(0x0) 10354 #define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) 10355 #define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_MSB _u(9) 10356 #define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_LSB _u(9) 10357 #define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_ACCESS "RO" 10358 // ----------------------------------------------------------------------------- 10359 // Field : IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW 10360 #define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_RESET _u(0x0) 10361 #define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) 10362 #define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_MSB _u(8) 10363 #define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_LSB _u(8) 10364 #define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_ACCESS "RO" 10365 // ----------------------------------------------------------------------------- 10366 // Field : IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH 10367 #define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_RESET _u(0x0) 10368 #define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) 10369 #define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_MSB _u(7) 10370 #define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_LSB _u(7) 10371 #define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_ACCESS "RO" 10372 // ----------------------------------------------------------------------------- 10373 // Field : IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW 10374 #define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_RESET _u(0x0) 10375 #define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_BITS _u(0x00000040) 10376 #define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_MSB _u(6) 10377 #define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_LSB _u(6) 10378 #define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_ACCESS "RO" 10379 // ----------------------------------------------------------------------------- 10380 // Field : IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH 10381 #define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_RESET _u(0x0) 10382 #define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) 10383 #define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_MSB _u(5) 10384 #define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_LSB _u(5) 10385 #define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_ACCESS "RO" 10386 // ----------------------------------------------------------------------------- 10387 // Field : IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW 10388 #define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_RESET _u(0x0) 10389 #define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) 10390 #define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_MSB _u(4) 10391 #define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_LSB _u(4) 10392 #define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_ACCESS "RO" 10393 // ----------------------------------------------------------------------------- 10394 // Field : IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH 10395 #define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_RESET _u(0x0) 10396 #define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) 10397 #define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_MSB _u(3) 10398 #define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_LSB _u(3) 10399 #define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_ACCESS "RO" 10400 // ----------------------------------------------------------------------------- 10401 // Field : IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW 10402 #define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_RESET _u(0x0) 10403 #define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_BITS _u(0x00000004) 10404 #define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_MSB _u(2) 10405 #define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_LSB _u(2) 10406 #define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_ACCESS "RO" 10407 // ----------------------------------------------------------------------------- 10408 // Field : IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH 10409 #define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_RESET _u(0x0) 10410 #define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) 10411 #define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_MSB _u(1) 10412 #define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_LSB _u(1) 10413 #define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_ACCESS "RO" 10414 // ----------------------------------------------------------------------------- 10415 // Field : IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW 10416 #define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_RESET _u(0x0) 10417 #define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) 10418 #define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_MSB _u(0) 10419 #define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_LSB _u(0) 10420 #define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_ACCESS "RO" 10421 // ============================================================================= 10422 // Register : IO_BANK0_PROC1_INTS1 10423 // Description : Interrupt status after masking & forcing for proc1 10424 #define IO_BANK0_PROC1_INTS1_OFFSET _u(0x00000154) 10425 #define IO_BANK0_PROC1_INTS1_BITS _u(0xffffffff) 10426 #define IO_BANK0_PROC1_INTS1_RESET _u(0x00000000) 10427 // ----------------------------------------------------------------------------- 10428 // Field : IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH 10429 #define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_RESET _u(0x0) 10430 #define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) 10431 #define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_MSB _u(31) 10432 #define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_LSB _u(31) 10433 #define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_ACCESS "RO" 10434 // ----------------------------------------------------------------------------- 10435 // Field : IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW 10436 #define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_RESET _u(0x0) 10437 #define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_BITS _u(0x40000000) 10438 #define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_MSB _u(30) 10439 #define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_LSB _u(30) 10440 #define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_ACCESS "RO" 10441 // ----------------------------------------------------------------------------- 10442 // Field : IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH 10443 #define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_RESET _u(0x0) 10444 #define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) 10445 #define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_MSB _u(29) 10446 #define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_LSB _u(29) 10447 #define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_ACCESS "RO" 10448 // ----------------------------------------------------------------------------- 10449 // Field : IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW 10450 #define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_RESET _u(0x0) 10451 #define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) 10452 #define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_MSB _u(28) 10453 #define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_LSB _u(28) 10454 #define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_ACCESS "RO" 10455 // ----------------------------------------------------------------------------- 10456 // Field : IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH 10457 #define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_RESET _u(0x0) 10458 #define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) 10459 #define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_MSB _u(27) 10460 #define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_LSB _u(27) 10461 #define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_ACCESS "RO" 10462 // ----------------------------------------------------------------------------- 10463 // Field : IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW 10464 #define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_RESET _u(0x0) 10465 #define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_BITS _u(0x04000000) 10466 #define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_MSB _u(26) 10467 #define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_LSB _u(26) 10468 #define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_ACCESS "RO" 10469 // ----------------------------------------------------------------------------- 10470 // Field : IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH 10471 #define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_RESET _u(0x0) 10472 #define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) 10473 #define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_MSB _u(25) 10474 #define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_LSB _u(25) 10475 #define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_ACCESS "RO" 10476 // ----------------------------------------------------------------------------- 10477 // Field : IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW 10478 #define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_RESET _u(0x0) 10479 #define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) 10480 #define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_MSB _u(24) 10481 #define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_LSB _u(24) 10482 #define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_ACCESS "RO" 10483 // ----------------------------------------------------------------------------- 10484 // Field : IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH 10485 #define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_RESET _u(0x0) 10486 #define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) 10487 #define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_MSB _u(23) 10488 #define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_LSB _u(23) 10489 #define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_ACCESS "RO" 10490 // ----------------------------------------------------------------------------- 10491 // Field : IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW 10492 #define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_RESET _u(0x0) 10493 #define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_BITS _u(0x00400000) 10494 #define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_MSB _u(22) 10495 #define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_LSB _u(22) 10496 #define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_ACCESS "RO" 10497 // ----------------------------------------------------------------------------- 10498 // Field : IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH 10499 #define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_RESET _u(0x0) 10500 #define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) 10501 #define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_MSB _u(21) 10502 #define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_LSB _u(21) 10503 #define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_ACCESS "RO" 10504 // ----------------------------------------------------------------------------- 10505 // Field : IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW 10506 #define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_RESET _u(0x0) 10507 #define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) 10508 #define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_MSB _u(20) 10509 #define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_LSB _u(20) 10510 #define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_ACCESS "RO" 10511 // ----------------------------------------------------------------------------- 10512 // Field : IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH 10513 #define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_RESET _u(0x0) 10514 #define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) 10515 #define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_MSB _u(19) 10516 #define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_LSB _u(19) 10517 #define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_ACCESS "RO" 10518 // ----------------------------------------------------------------------------- 10519 // Field : IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW 10520 #define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_RESET _u(0x0) 10521 #define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_BITS _u(0x00040000) 10522 #define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_MSB _u(18) 10523 #define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_LSB _u(18) 10524 #define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_ACCESS "RO" 10525 // ----------------------------------------------------------------------------- 10526 // Field : IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH 10527 #define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_RESET _u(0x0) 10528 #define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) 10529 #define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_MSB _u(17) 10530 #define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_LSB _u(17) 10531 #define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_ACCESS "RO" 10532 // ----------------------------------------------------------------------------- 10533 // Field : IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW 10534 #define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_RESET _u(0x0) 10535 #define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) 10536 #define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_MSB _u(16) 10537 #define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_LSB _u(16) 10538 #define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_ACCESS "RO" 10539 // ----------------------------------------------------------------------------- 10540 // Field : IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH 10541 #define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_RESET _u(0x0) 10542 #define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) 10543 #define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_MSB _u(15) 10544 #define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_LSB _u(15) 10545 #define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_ACCESS "RO" 10546 // ----------------------------------------------------------------------------- 10547 // Field : IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW 10548 #define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_RESET _u(0x0) 10549 #define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_BITS _u(0x00004000) 10550 #define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_MSB _u(14) 10551 #define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_LSB _u(14) 10552 #define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_ACCESS "RO" 10553 // ----------------------------------------------------------------------------- 10554 // Field : IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH 10555 #define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_RESET _u(0x0) 10556 #define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) 10557 #define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_MSB _u(13) 10558 #define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_LSB _u(13) 10559 #define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_ACCESS "RO" 10560 // ----------------------------------------------------------------------------- 10561 // Field : IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW 10562 #define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_RESET _u(0x0) 10563 #define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) 10564 #define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_MSB _u(12) 10565 #define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_LSB _u(12) 10566 #define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_ACCESS "RO" 10567 // ----------------------------------------------------------------------------- 10568 // Field : IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH 10569 #define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_RESET _u(0x0) 10570 #define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) 10571 #define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_MSB _u(11) 10572 #define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_LSB _u(11) 10573 #define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_ACCESS "RO" 10574 // ----------------------------------------------------------------------------- 10575 // Field : IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW 10576 #define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_RESET _u(0x0) 10577 #define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_BITS _u(0x00000400) 10578 #define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_MSB _u(10) 10579 #define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_LSB _u(10) 10580 #define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_ACCESS "RO" 10581 // ----------------------------------------------------------------------------- 10582 // Field : IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH 10583 #define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_RESET _u(0x0) 10584 #define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) 10585 #define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_MSB _u(9) 10586 #define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_LSB _u(9) 10587 #define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_ACCESS "RO" 10588 // ----------------------------------------------------------------------------- 10589 // Field : IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW 10590 #define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_RESET _u(0x0) 10591 #define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) 10592 #define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_MSB _u(8) 10593 #define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_LSB _u(8) 10594 #define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_ACCESS "RO" 10595 // ----------------------------------------------------------------------------- 10596 // Field : IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH 10597 #define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_RESET _u(0x0) 10598 #define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) 10599 #define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_MSB _u(7) 10600 #define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_LSB _u(7) 10601 #define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_ACCESS "RO" 10602 // ----------------------------------------------------------------------------- 10603 // Field : IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW 10604 #define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_RESET _u(0x0) 10605 #define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_BITS _u(0x00000040) 10606 #define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_MSB _u(6) 10607 #define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_LSB _u(6) 10608 #define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_ACCESS "RO" 10609 // ----------------------------------------------------------------------------- 10610 // Field : IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH 10611 #define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_RESET _u(0x0) 10612 #define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) 10613 #define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_MSB _u(5) 10614 #define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_LSB _u(5) 10615 #define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_ACCESS "RO" 10616 // ----------------------------------------------------------------------------- 10617 // Field : IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW 10618 #define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_RESET _u(0x0) 10619 #define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) 10620 #define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_MSB _u(4) 10621 #define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_LSB _u(4) 10622 #define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_ACCESS "RO" 10623 // ----------------------------------------------------------------------------- 10624 // Field : IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH 10625 #define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_RESET _u(0x0) 10626 #define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) 10627 #define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_MSB _u(3) 10628 #define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_LSB _u(3) 10629 #define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_ACCESS "RO" 10630 // ----------------------------------------------------------------------------- 10631 // Field : IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW 10632 #define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_RESET _u(0x0) 10633 #define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_BITS _u(0x00000004) 10634 #define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_MSB _u(2) 10635 #define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_LSB _u(2) 10636 #define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_ACCESS "RO" 10637 // ----------------------------------------------------------------------------- 10638 // Field : IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH 10639 #define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_RESET _u(0x0) 10640 #define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) 10641 #define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_MSB _u(1) 10642 #define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_LSB _u(1) 10643 #define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_ACCESS "RO" 10644 // ----------------------------------------------------------------------------- 10645 // Field : IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW 10646 #define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_RESET _u(0x0) 10647 #define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) 10648 #define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_MSB _u(0) 10649 #define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_LSB _u(0) 10650 #define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_ACCESS "RO" 10651 // ============================================================================= 10652 // Register : IO_BANK0_PROC1_INTS2 10653 // Description : Interrupt status after masking & forcing for proc1 10654 #define IO_BANK0_PROC1_INTS2_OFFSET _u(0x00000158) 10655 #define IO_BANK0_PROC1_INTS2_BITS _u(0xffffffff) 10656 #define IO_BANK0_PROC1_INTS2_RESET _u(0x00000000) 10657 // ----------------------------------------------------------------------------- 10658 // Field : IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH 10659 #define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_RESET _u(0x0) 10660 #define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) 10661 #define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_MSB _u(31) 10662 #define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_LSB _u(31) 10663 #define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_ACCESS "RO" 10664 // ----------------------------------------------------------------------------- 10665 // Field : IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW 10666 #define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_RESET _u(0x0) 10667 #define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_BITS _u(0x40000000) 10668 #define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_MSB _u(30) 10669 #define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_LSB _u(30) 10670 #define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_ACCESS "RO" 10671 // ----------------------------------------------------------------------------- 10672 // Field : IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH 10673 #define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_RESET _u(0x0) 10674 #define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) 10675 #define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_MSB _u(29) 10676 #define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_LSB _u(29) 10677 #define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_ACCESS "RO" 10678 // ----------------------------------------------------------------------------- 10679 // Field : IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW 10680 #define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_RESET _u(0x0) 10681 #define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) 10682 #define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_MSB _u(28) 10683 #define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_LSB _u(28) 10684 #define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_ACCESS "RO" 10685 // ----------------------------------------------------------------------------- 10686 // Field : IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH 10687 #define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_RESET _u(0x0) 10688 #define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) 10689 #define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_MSB _u(27) 10690 #define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_LSB _u(27) 10691 #define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_ACCESS "RO" 10692 // ----------------------------------------------------------------------------- 10693 // Field : IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW 10694 #define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_RESET _u(0x0) 10695 #define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_BITS _u(0x04000000) 10696 #define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_MSB _u(26) 10697 #define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_LSB _u(26) 10698 #define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_ACCESS "RO" 10699 // ----------------------------------------------------------------------------- 10700 // Field : IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH 10701 #define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_RESET _u(0x0) 10702 #define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) 10703 #define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_MSB _u(25) 10704 #define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_LSB _u(25) 10705 #define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_ACCESS "RO" 10706 // ----------------------------------------------------------------------------- 10707 // Field : IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW 10708 #define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_RESET _u(0x0) 10709 #define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) 10710 #define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_MSB _u(24) 10711 #define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_LSB _u(24) 10712 #define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_ACCESS "RO" 10713 // ----------------------------------------------------------------------------- 10714 // Field : IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH 10715 #define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_RESET _u(0x0) 10716 #define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) 10717 #define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_MSB _u(23) 10718 #define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_LSB _u(23) 10719 #define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_ACCESS "RO" 10720 // ----------------------------------------------------------------------------- 10721 // Field : IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW 10722 #define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_RESET _u(0x0) 10723 #define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_BITS _u(0x00400000) 10724 #define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_MSB _u(22) 10725 #define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_LSB _u(22) 10726 #define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_ACCESS "RO" 10727 // ----------------------------------------------------------------------------- 10728 // Field : IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH 10729 #define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_RESET _u(0x0) 10730 #define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) 10731 #define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_MSB _u(21) 10732 #define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_LSB _u(21) 10733 #define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_ACCESS "RO" 10734 // ----------------------------------------------------------------------------- 10735 // Field : IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW 10736 #define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_RESET _u(0x0) 10737 #define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) 10738 #define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_MSB _u(20) 10739 #define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_LSB _u(20) 10740 #define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_ACCESS "RO" 10741 // ----------------------------------------------------------------------------- 10742 // Field : IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH 10743 #define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_RESET _u(0x0) 10744 #define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) 10745 #define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_MSB _u(19) 10746 #define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_LSB _u(19) 10747 #define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_ACCESS "RO" 10748 // ----------------------------------------------------------------------------- 10749 // Field : IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW 10750 #define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_RESET _u(0x0) 10751 #define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_BITS _u(0x00040000) 10752 #define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_MSB _u(18) 10753 #define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_LSB _u(18) 10754 #define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_ACCESS "RO" 10755 // ----------------------------------------------------------------------------- 10756 // Field : IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH 10757 #define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_RESET _u(0x0) 10758 #define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) 10759 #define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_MSB _u(17) 10760 #define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_LSB _u(17) 10761 #define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_ACCESS "RO" 10762 // ----------------------------------------------------------------------------- 10763 // Field : IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW 10764 #define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_RESET _u(0x0) 10765 #define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) 10766 #define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_MSB _u(16) 10767 #define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_LSB _u(16) 10768 #define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_ACCESS "RO" 10769 // ----------------------------------------------------------------------------- 10770 // Field : IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH 10771 #define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_RESET _u(0x0) 10772 #define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) 10773 #define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_MSB _u(15) 10774 #define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_LSB _u(15) 10775 #define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_ACCESS "RO" 10776 // ----------------------------------------------------------------------------- 10777 // Field : IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW 10778 #define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_RESET _u(0x0) 10779 #define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_BITS _u(0x00004000) 10780 #define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_MSB _u(14) 10781 #define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_LSB _u(14) 10782 #define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_ACCESS "RO" 10783 // ----------------------------------------------------------------------------- 10784 // Field : IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH 10785 #define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_RESET _u(0x0) 10786 #define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) 10787 #define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_MSB _u(13) 10788 #define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_LSB _u(13) 10789 #define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_ACCESS "RO" 10790 // ----------------------------------------------------------------------------- 10791 // Field : IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW 10792 #define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_RESET _u(0x0) 10793 #define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) 10794 #define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_MSB _u(12) 10795 #define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_LSB _u(12) 10796 #define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_ACCESS "RO" 10797 // ----------------------------------------------------------------------------- 10798 // Field : IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH 10799 #define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_RESET _u(0x0) 10800 #define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) 10801 #define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_MSB _u(11) 10802 #define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_LSB _u(11) 10803 #define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_ACCESS "RO" 10804 // ----------------------------------------------------------------------------- 10805 // Field : IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW 10806 #define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_RESET _u(0x0) 10807 #define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_BITS _u(0x00000400) 10808 #define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_MSB _u(10) 10809 #define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_LSB _u(10) 10810 #define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_ACCESS "RO" 10811 // ----------------------------------------------------------------------------- 10812 // Field : IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH 10813 #define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_RESET _u(0x0) 10814 #define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) 10815 #define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_MSB _u(9) 10816 #define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_LSB _u(9) 10817 #define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_ACCESS "RO" 10818 // ----------------------------------------------------------------------------- 10819 // Field : IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW 10820 #define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_RESET _u(0x0) 10821 #define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) 10822 #define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_MSB _u(8) 10823 #define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_LSB _u(8) 10824 #define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_ACCESS "RO" 10825 // ----------------------------------------------------------------------------- 10826 // Field : IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH 10827 #define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_RESET _u(0x0) 10828 #define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) 10829 #define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_MSB _u(7) 10830 #define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_LSB _u(7) 10831 #define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_ACCESS "RO" 10832 // ----------------------------------------------------------------------------- 10833 // Field : IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW 10834 #define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_RESET _u(0x0) 10835 #define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_BITS _u(0x00000040) 10836 #define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_MSB _u(6) 10837 #define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_LSB _u(6) 10838 #define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_ACCESS "RO" 10839 // ----------------------------------------------------------------------------- 10840 // Field : IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH 10841 #define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_RESET _u(0x0) 10842 #define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) 10843 #define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_MSB _u(5) 10844 #define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_LSB _u(5) 10845 #define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_ACCESS "RO" 10846 // ----------------------------------------------------------------------------- 10847 // Field : IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW 10848 #define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_RESET _u(0x0) 10849 #define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) 10850 #define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_MSB _u(4) 10851 #define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_LSB _u(4) 10852 #define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_ACCESS "RO" 10853 // ----------------------------------------------------------------------------- 10854 // Field : IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH 10855 #define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_RESET _u(0x0) 10856 #define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) 10857 #define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_MSB _u(3) 10858 #define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_LSB _u(3) 10859 #define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_ACCESS "RO" 10860 // ----------------------------------------------------------------------------- 10861 // Field : IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW 10862 #define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_RESET _u(0x0) 10863 #define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_BITS _u(0x00000004) 10864 #define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_MSB _u(2) 10865 #define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_LSB _u(2) 10866 #define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_ACCESS "RO" 10867 // ----------------------------------------------------------------------------- 10868 // Field : IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH 10869 #define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_RESET _u(0x0) 10870 #define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) 10871 #define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_MSB _u(1) 10872 #define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_LSB _u(1) 10873 #define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_ACCESS "RO" 10874 // ----------------------------------------------------------------------------- 10875 // Field : IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW 10876 #define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_RESET _u(0x0) 10877 #define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) 10878 #define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_MSB _u(0) 10879 #define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_LSB _u(0) 10880 #define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_ACCESS "RO" 10881 // ============================================================================= 10882 // Register : IO_BANK0_PROC1_INTS3 10883 // Description : Interrupt status after masking & forcing for proc1 10884 #define IO_BANK0_PROC1_INTS3_OFFSET _u(0x0000015c) 10885 #define IO_BANK0_PROC1_INTS3_BITS _u(0x00ffffff) 10886 #define IO_BANK0_PROC1_INTS3_RESET _u(0x00000000) 10887 // ----------------------------------------------------------------------------- 10888 // Field : IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH 10889 #define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_RESET _u(0x0) 10890 #define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) 10891 #define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_MSB _u(23) 10892 #define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_LSB _u(23) 10893 #define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_ACCESS "RO" 10894 // ----------------------------------------------------------------------------- 10895 // Field : IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW 10896 #define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_RESET _u(0x0) 10897 #define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_BITS _u(0x00400000) 10898 #define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_MSB _u(22) 10899 #define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_LSB _u(22) 10900 #define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_ACCESS "RO" 10901 // ----------------------------------------------------------------------------- 10902 // Field : IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH 10903 #define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_RESET _u(0x0) 10904 #define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) 10905 #define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_MSB _u(21) 10906 #define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_LSB _u(21) 10907 #define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_ACCESS "RO" 10908 // ----------------------------------------------------------------------------- 10909 // Field : IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW 10910 #define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_RESET _u(0x0) 10911 #define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) 10912 #define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_MSB _u(20) 10913 #define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_LSB _u(20) 10914 #define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_ACCESS "RO" 10915 // ----------------------------------------------------------------------------- 10916 // Field : IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH 10917 #define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_RESET _u(0x0) 10918 #define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) 10919 #define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_MSB _u(19) 10920 #define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_LSB _u(19) 10921 #define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_ACCESS "RO" 10922 // ----------------------------------------------------------------------------- 10923 // Field : IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW 10924 #define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_RESET _u(0x0) 10925 #define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_BITS _u(0x00040000) 10926 #define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_MSB _u(18) 10927 #define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_LSB _u(18) 10928 #define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_ACCESS "RO" 10929 // ----------------------------------------------------------------------------- 10930 // Field : IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH 10931 #define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_RESET _u(0x0) 10932 #define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) 10933 #define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_MSB _u(17) 10934 #define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_LSB _u(17) 10935 #define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_ACCESS "RO" 10936 // ----------------------------------------------------------------------------- 10937 // Field : IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW 10938 #define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_RESET _u(0x0) 10939 #define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) 10940 #define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_MSB _u(16) 10941 #define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_LSB _u(16) 10942 #define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_ACCESS "RO" 10943 // ----------------------------------------------------------------------------- 10944 // Field : IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH 10945 #define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_RESET _u(0x0) 10946 #define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) 10947 #define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_MSB _u(15) 10948 #define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_LSB _u(15) 10949 #define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_ACCESS "RO" 10950 // ----------------------------------------------------------------------------- 10951 // Field : IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW 10952 #define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_RESET _u(0x0) 10953 #define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_BITS _u(0x00004000) 10954 #define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_MSB _u(14) 10955 #define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_LSB _u(14) 10956 #define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_ACCESS "RO" 10957 // ----------------------------------------------------------------------------- 10958 // Field : IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH 10959 #define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_RESET _u(0x0) 10960 #define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) 10961 #define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_MSB _u(13) 10962 #define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_LSB _u(13) 10963 #define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_ACCESS "RO" 10964 // ----------------------------------------------------------------------------- 10965 // Field : IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW 10966 #define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_RESET _u(0x0) 10967 #define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) 10968 #define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_MSB _u(12) 10969 #define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_LSB _u(12) 10970 #define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_ACCESS "RO" 10971 // ----------------------------------------------------------------------------- 10972 // Field : IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH 10973 #define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_RESET _u(0x0) 10974 #define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) 10975 #define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_MSB _u(11) 10976 #define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_LSB _u(11) 10977 #define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_ACCESS "RO" 10978 // ----------------------------------------------------------------------------- 10979 // Field : IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW 10980 #define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_RESET _u(0x0) 10981 #define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_BITS _u(0x00000400) 10982 #define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_MSB _u(10) 10983 #define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_LSB _u(10) 10984 #define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_ACCESS "RO" 10985 // ----------------------------------------------------------------------------- 10986 // Field : IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH 10987 #define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_RESET _u(0x0) 10988 #define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) 10989 #define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_MSB _u(9) 10990 #define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_LSB _u(9) 10991 #define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_ACCESS "RO" 10992 // ----------------------------------------------------------------------------- 10993 // Field : IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW 10994 #define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_RESET _u(0x0) 10995 #define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) 10996 #define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_MSB _u(8) 10997 #define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_LSB _u(8) 10998 #define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_ACCESS "RO" 10999 // ----------------------------------------------------------------------------- 11000 // Field : IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH 11001 #define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_RESET _u(0x0) 11002 #define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) 11003 #define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_MSB _u(7) 11004 #define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_LSB _u(7) 11005 #define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_ACCESS "RO" 11006 // ----------------------------------------------------------------------------- 11007 // Field : IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW 11008 #define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_RESET _u(0x0) 11009 #define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_BITS _u(0x00000040) 11010 #define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_MSB _u(6) 11011 #define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_LSB _u(6) 11012 #define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_ACCESS "RO" 11013 // ----------------------------------------------------------------------------- 11014 // Field : IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH 11015 #define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_RESET _u(0x0) 11016 #define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) 11017 #define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_MSB _u(5) 11018 #define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_LSB _u(5) 11019 #define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_ACCESS "RO" 11020 // ----------------------------------------------------------------------------- 11021 // Field : IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW 11022 #define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_RESET _u(0x0) 11023 #define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) 11024 #define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_MSB _u(4) 11025 #define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_LSB _u(4) 11026 #define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_ACCESS "RO" 11027 // ----------------------------------------------------------------------------- 11028 // Field : IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH 11029 #define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_RESET _u(0x0) 11030 #define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) 11031 #define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_MSB _u(3) 11032 #define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_LSB _u(3) 11033 #define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_ACCESS "RO" 11034 // ----------------------------------------------------------------------------- 11035 // Field : IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW 11036 #define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_RESET _u(0x0) 11037 #define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_BITS _u(0x00000004) 11038 #define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_MSB _u(2) 11039 #define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_LSB _u(2) 11040 #define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_ACCESS "RO" 11041 // ----------------------------------------------------------------------------- 11042 // Field : IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH 11043 #define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_RESET _u(0x0) 11044 #define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) 11045 #define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_MSB _u(1) 11046 #define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_LSB _u(1) 11047 #define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_ACCESS "RO" 11048 // ----------------------------------------------------------------------------- 11049 // Field : IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW 11050 #define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_RESET _u(0x0) 11051 #define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) 11052 #define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_MSB _u(0) 11053 #define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_LSB _u(0) 11054 #define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_ACCESS "RO" 11055 // ============================================================================= 11056 // Register : IO_BANK0_DORMANT_WAKE_INTE0 11057 // Description : Interrupt Enable for dormant_wake 11058 #define IO_BANK0_DORMANT_WAKE_INTE0_OFFSET _u(0x00000160) 11059 #define IO_BANK0_DORMANT_WAKE_INTE0_BITS _u(0xffffffff) 11060 #define IO_BANK0_DORMANT_WAKE_INTE0_RESET _u(0x00000000) 11061 // ----------------------------------------------------------------------------- 11062 // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH 11063 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_RESET _u(0x0) 11064 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) 11065 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_MSB _u(31) 11066 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_LSB _u(31) 11067 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_ACCESS "RW" 11068 // ----------------------------------------------------------------------------- 11069 // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW 11070 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_RESET _u(0x0) 11071 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_BITS _u(0x40000000) 11072 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_MSB _u(30) 11073 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_LSB _u(30) 11074 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_ACCESS "RW" 11075 // ----------------------------------------------------------------------------- 11076 // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH 11077 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_RESET _u(0x0) 11078 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) 11079 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_MSB _u(29) 11080 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_LSB _u(29) 11081 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_ACCESS "RW" 11082 // ----------------------------------------------------------------------------- 11083 // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW 11084 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_RESET _u(0x0) 11085 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) 11086 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_MSB _u(28) 11087 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_LSB _u(28) 11088 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_ACCESS "RW" 11089 // ----------------------------------------------------------------------------- 11090 // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH 11091 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_RESET _u(0x0) 11092 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) 11093 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_MSB _u(27) 11094 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_LSB _u(27) 11095 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_ACCESS "RW" 11096 // ----------------------------------------------------------------------------- 11097 // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW 11098 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_RESET _u(0x0) 11099 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_BITS _u(0x04000000) 11100 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_MSB _u(26) 11101 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_LSB _u(26) 11102 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_ACCESS "RW" 11103 // ----------------------------------------------------------------------------- 11104 // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH 11105 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_RESET _u(0x0) 11106 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) 11107 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_MSB _u(25) 11108 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_LSB _u(25) 11109 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_ACCESS "RW" 11110 // ----------------------------------------------------------------------------- 11111 // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW 11112 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_RESET _u(0x0) 11113 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) 11114 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_MSB _u(24) 11115 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_LSB _u(24) 11116 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_ACCESS "RW" 11117 // ----------------------------------------------------------------------------- 11118 // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH 11119 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_RESET _u(0x0) 11120 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) 11121 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_MSB _u(23) 11122 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_LSB _u(23) 11123 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_ACCESS "RW" 11124 // ----------------------------------------------------------------------------- 11125 // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW 11126 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_RESET _u(0x0) 11127 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_BITS _u(0x00400000) 11128 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_MSB _u(22) 11129 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_LSB _u(22) 11130 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_ACCESS "RW" 11131 // ----------------------------------------------------------------------------- 11132 // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH 11133 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_RESET _u(0x0) 11134 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) 11135 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_MSB _u(21) 11136 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_LSB _u(21) 11137 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_ACCESS "RW" 11138 // ----------------------------------------------------------------------------- 11139 // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW 11140 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_RESET _u(0x0) 11141 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) 11142 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_MSB _u(20) 11143 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_LSB _u(20) 11144 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_ACCESS "RW" 11145 // ----------------------------------------------------------------------------- 11146 // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH 11147 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_RESET _u(0x0) 11148 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) 11149 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_MSB _u(19) 11150 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_LSB _u(19) 11151 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_ACCESS "RW" 11152 // ----------------------------------------------------------------------------- 11153 // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW 11154 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_RESET _u(0x0) 11155 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_BITS _u(0x00040000) 11156 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_MSB _u(18) 11157 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_LSB _u(18) 11158 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_ACCESS "RW" 11159 // ----------------------------------------------------------------------------- 11160 // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH 11161 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_RESET _u(0x0) 11162 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) 11163 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_MSB _u(17) 11164 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_LSB _u(17) 11165 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_ACCESS "RW" 11166 // ----------------------------------------------------------------------------- 11167 // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW 11168 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_RESET _u(0x0) 11169 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) 11170 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_MSB _u(16) 11171 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_LSB _u(16) 11172 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_ACCESS "RW" 11173 // ----------------------------------------------------------------------------- 11174 // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH 11175 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_RESET _u(0x0) 11176 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) 11177 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_MSB _u(15) 11178 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_LSB _u(15) 11179 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_ACCESS "RW" 11180 // ----------------------------------------------------------------------------- 11181 // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW 11182 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_RESET _u(0x0) 11183 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_BITS _u(0x00004000) 11184 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_MSB _u(14) 11185 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_LSB _u(14) 11186 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_ACCESS "RW" 11187 // ----------------------------------------------------------------------------- 11188 // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH 11189 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_RESET _u(0x0) 11190 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) 11191 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_MSB _u(13) 11192 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_LSB _u(13) 11193 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_ACCESS "RW" 11194 // ----------------------------------------------------------------------------- 11195 // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW 11196 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_RESET _u(0x0) 11197 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) 11198 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_MSB _u(12) 11199 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_LSB _u(12) 11200 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_ACCESS "RW" 11201 // ----------------------------------------------------------------------------- 11202 // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH 11203 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_RESET _u(0x0) 11204 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) 11205 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_MSB _u(11) 11206 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_LSB _u(11) 11207 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_ACCESS "RW" 11208 // ----------------------------------------------------------------------------- 11209 // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW 11210 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_RESET _u(0x0) 11211 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_BITS _u(0x00000400) 11212 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_MSB _u(10) 11213 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_LSB _u(10) 11214 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_ACCESS "RW" 11215 // ----------------------------------------------------------------------------- 11216 // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH 11217 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_RESET _u(0x0) 11218 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) 11219 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_MSB _u(9) 11220 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_LSB _u(9) 11221 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_ACCESS "RW" 11222 // ----------------------------------------------------------------------------- 11223 // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW 11224 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_RESET _u(0x0) 11225 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) 11226 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_MSB _u(8) 11227 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_LSB _u(8) 11228 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_ACCESS "RW" 11229 // ----------------------------------------------------------------------------- 11230 // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH 11231 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_RESET _u(0x0) 11232 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) 11233 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_MSB _u(7) 11234 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_LSB _u(7) 11235 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_ACCESS "RW" 11236 // ----------------------------------------------------------------------------- 11237 // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW 11238 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_RESET _u(0x0) 11239 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_BITS _u(0x00000040) 11240 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_MSB _u(6) 11241 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_LSB _u(6) 11242 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_ACCESS "RW" 11243 // ----------------------------------------------------------------------------- 11244 // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH 11245 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_RESET _u(0x0) 11246 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) 11247 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_MSB _u(5) 11248 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_LSB _u(5) 11249 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_ACCESS "RW" 11250 // ----------------------------------------------------------------------------- 11251 // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW 11252 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_RESET _u(0x0) 11253 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) 11254 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_MSB _u(4) 11255 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_LSB _u(4) 11256 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_ACCESS "RW" 11257 // ----------------------------------------------------------------------------- 11258 // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH 11259 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_RESET _u(0x0) 11260 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) 11261 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_MSB _u(3) 11262 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_LSB _u(3) 11263 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_ACCESS "RW" 11264 // ----------------------------------------------------------------------------- 11265 // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW 11266 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_RESET _u(0x0) 11267 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_BITS _u(0x00000004) 11268 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_MSB _u(2) 11269 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_LSB _u(2) 11270 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_ACCESS "RW" 11271 // ----------------------------------------------------------------------------- 11272 // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH 11273 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_RESET _u(0x0) 11274 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) 11275 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_MSB _u(1) 11276 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_LSB _u(1) 11277 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_ACCESS "RW" 11278 // ----------------------------------------------------------------------------- 11279 // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW 11280 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_RESET _u(0x0) 11281 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) 11282 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_MSB _u(0) 11283 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_LSB _u(0) 11284 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_ACCESS "RW" 11285 // ============================================================================= 11286 // Register : IO_BANK0_DORMANT_WAKE_INTE1 11287 // Description : Interrupt Enable for dormant_wake 11288 #define IO_BANK0_DORMANT_WAKE_INTE1_OFFSET _u(0x00000164) 11289 #define IO_BANK0_DORMANT_WAKE_INTE1_BITS _u(0xffffffff) 11290 #define IO_BANK0_DORMANT_WAKE_INTE1_RESET _u(0x00000000) 11291 // ----------------------------------------------------------------------------- 11292 // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH 11293 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_RESET _u(0x0) 11294 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) 11295 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_MSB _u(31) 11296 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_LSB _u(31) 11297 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_ACCESS "RW" 11298 // ----------------------------------------------------------------------------- 11299 // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW 11300 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_RESET _u(0x0) 11301 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_BITS _u(0x40000000) 11302 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_MSB _u(30) 11303 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_LSB _u(30) 11304 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_ACCESS "RW" 11305 // ----------------------------------------------------------------------------- 11306 // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH 11307 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_RESET _u(0x0) 11308 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) 11309 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_MSB _u(29) 11310 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_LSB _u(29) 11311 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_ACCESS "RW" 11312 // ----------------------------------------------------------------------------- 11313 // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW 11314 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_RESET _u(0x0) 11315 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) 11316 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_MSB _u(28) 11317 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_LSB _u(28) 11318 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_ACCESS "RW" 11319 // ----------------------------------------------------------------------------- 11320 // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH 11321 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_RESET _u(0x0) 11322 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) 11323 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_MSB _u(27) 11324 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_LSB _u(27) 11325 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_ACCESS "RW" 11326 // ----------------------------------------------------------------------------- 11327 // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW 11328 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_RESET _u(0x0) 11329 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_BITS _u(0x04000000) 11330 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_MSB _u(26) 11331 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_LSB _u(26) 11332 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_ACCESS "RW" 11333 // ----------------------------------------------------------------------------- 11334 // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH 11335 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_RESET _u(0x0) 11336 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) 11337 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_MSB _u(25) 11338 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_LSB _u(25) 11339 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_ACCESS "RW" 11340 // ----------------------------------------------------------------------------- 11341 // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW 11342 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_RESET _u(0x0) 11343 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) 11344 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_MSB _u(24) 11345 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_LSB _u(24) 11346 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_ACCESS "RW" 11347 // ----------------------------------------------------------------------------- 11348 // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH 11349 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_RESET _u(0x0) 11350 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) 11351 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_MSB _u(23) 11352 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_LSB _u(23) 11353 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_ACCESS "RW" 11354 // ----------------------------------------------------------------------------- 11355 // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW 11356 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_RESET _u(0x0) 11357 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_BITS _u(0x00400000) 11358 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_MSB _u(22) 11359 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_LSB _u(22) 11360 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_ACCESS "RW" 11361 // ----------------------------------------------------------------------------- 11362 // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH 11363 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_RESET _u(0x0) 11364 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) 11365 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_MSB _u(21) 11366 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_LSB _u(21) 11367 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_ACCESS "RW" 11368 // ----------------------------------------------------------------------------- 11369 // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW 11370 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_RESET _u(0x0) 11371 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) 11372 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_MSB _u(20) 11373 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_LSB _u(20) 11374 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_ACCESS "RW" 11375 // ----------------------------------------------------------------------------- 11376 // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH 11377 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_RESET _u(0x0) 11378 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) 11379 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_MSB _u(19) 11380 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_LSB _u(19) 11381 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_ACCESS "RW" 11382 // ----------------------------------------------------------------------------- 11383 // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW 11384 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_RESET _u(0x0) 11385 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_BITS _u(0x00040000) 11386 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_MSB _u(18) 11387 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_LSB _u(18) 11388 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_ACCESS "RW" 11389 // ----------------------------------------------------------------------------- 11390 // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH 11391 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_RESET _u(0x0) 11392 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) 11393 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_MSB _u(17) 11394 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_LSB _u(17) 11395 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_ACCESS "RW" 11396 // ----------------------------------------------------------------------------- 11397 // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW 11398 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_RESET _u(0x0) 11399 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) 11400 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_MSB _u(16) 11401 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_LSB _u(16) 11402 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_ACCESS "RW" 11403 // ----------------------------------------------------------------------------- 11404 // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH 11405 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_RESET _u(0x0) 11406 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) 11407 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_MSB _u(15) 11408 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_LSB _u(15) 11409 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_ACCESS "RW" 11410 // ----------------------------------------------------------------------------- 11411 // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW 11412 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_RESET _u(0x0) 11413 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_BITS _u(0x00004000) 11414 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_MSB _u(14) 11415 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_LSB _u(14) 11416 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_ACCESS "RW" 11417 // ----------------------------------------------------------------------------- 11418 // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH 11419 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_RESET _u(0x0) 11420 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) 11421 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_MSB _u(13) 11422 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_LSB _u(13) 11423 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_ACCESS "RW" 11424 // ----------------------------------------------------------------------------- 11425 // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW 11426 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_RESET _u(0x0) 11427 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) 11428 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_MSB _u(12) 11429 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_LSB _u(12) 11430 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_ACCESS "RW" 11431 // ----------------------------------------------------------------------------- 11432 // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH 11433 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_RESET _u(0x0) 11434 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) 11435 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_MSB _u(11) 11436 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_LSB _u(11) 11437 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_ACCESS "RW" 11438 // ----------------------------------------------------------------------------- 11439 // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW 11440 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_RESET _u(0x0) 11441 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_BITS _u(0x00000400) 11442 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_MSB _u(10) 11443 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_LSB _u(10) 11444 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_ACCESS "RW" 11445 // ----------------------------------------------------------------------------- 11446 // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH 11447 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_RESET _u(0x0) 11448 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) 11449 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_MSB _u(9) 11450 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_LSB _u(9) 11451 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_ACCESS "RW" 11452 // ----------------------------------------------------------------------------- 11453 // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW 11454 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_RESET _u(0x0) 11455 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) 11456 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_MSB _u(8) 11457 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_LSB _u(8) 11458 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_ACCESS "RW" 11459 // ----------------------------------------------------------------------------- 11460 // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH 11461 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_RESET _u(0x0) 11462 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) 11463 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_MSB _u(7) 11464 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_LSB _u(7) 11465 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_ACCESS "RW" 11466 // ----------------------------------------------------------------------------- 11467 // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW 11468 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_RESET _u(0x0) 11469 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_BITS _u(0x00000040) 11470 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_MSB _u(6) 11471 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_LSB _u(6) 11472 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_ACCESS "RW" 11473 // ----------------------------------------------------------------------------- 11474 // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH 11475 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_RESET _u(0x0) 11476 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) 11477 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_MSB _u(5) 11478 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_LSB _u(5) 11479 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_ACCESS "RW" 11480 // ----------------------------------------------------------------------------- 11481 // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW 11482 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_RESET _u(0x0) 11483 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) 11484 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_MSB _u(4) 11485 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_LSB _u(4) 11486 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_ACCESS "RW" 11487 // ----------------------------------------------------------------------------- 11488 // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH 11489 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_RESET _u(0x0) 11490 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) 11491 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_MSB _u(3) 11492 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_LSB _u(3) 11493 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_ACCESS "RW" 11494 // ----------------------------------------------------------------------------- 11495 // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW 11496 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_RESET _u(0x0) 11497 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_BITS _u(0x00000004) 11498 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_MSB _u(2) 11499 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_LSB _u(2) 11500 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_ACCESS "RW" 11501 // ----------------------------------------------------------------------------- 11502 // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH 11503 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_RESET _u(0x0) 11504 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) 11505 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_MSB _u(1) 11506 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_LSB _u(1) 11507 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_ACCESS "RW" 11508 // ----------------------------------------------------------------------------- 11509 // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW 11510 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_RESET _u(0x0) 11511 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) 11512 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_MSB _u(0) 11513 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_LSB _u(0) 11514 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_ACCESS "RW" 11515 // ============================================================================= 11516 // Register : IO_BANK0_DORMANT_WAKE_INTE2 11517 // Description : Interrupt Enable for dormant_wake 11518 #define IO_BANK0_DORMANT_WAKE_INTE2_OFFSET _u(0x00000168) 11519 #define IO_BANK0_DORMANT_WAKE_INTE2_BITS _u(0xffffffff) 11520 #define IO_BANK0_DORMANT_WAKE_INTE2_RESET _u(0x00000000) 11521 // ----------------------------------------------------------------------------- 11522 // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH 11523 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_RESET _u(0x0) 11524 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) 11525 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_MSB _u(31) 11526 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_LSB _u(31) 11527 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_ACCESS "RW" 11528 // ----------------------------------------------------------------------------- 11529 // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW 11530 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_RESET _u(0x0) 11531 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_BITS _u(0x40000000) 11532 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_MSB _u(30) 11533 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_LSB _u(30) 11534 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_ACCESS "RW" 11535 // ----------------------------------------------------------------------------- 11536 // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH 11537 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_RESET _u(0x0) 11538 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) 11539 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_MSB _u(29) 11540 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_LSB _u(29) 11541 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_ACCESS "RW" 11542 // ----------------------------------------------------------------------------- 11543 // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW 11544 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_RESET _u(0x0) 11545 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) 11546 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_MSB _u(28) 11547 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_LSB _u(28) 11548 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_ACCESS "RW" 11549 // ----------------------------------------------------------------------------- 11550 // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH 11551 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_RESET _u(0x0) 11552 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) 11553 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_MSB _u(27) 11554 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_LSB _u(27) 11555 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_ACCESS "RW" 11556 // ----------------------------------------------------------------------------- 11557 // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW 11558 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_RESET _u(0x0) 11559 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_BITS _u(0x04000000) 11560 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_MSB _u(26) 11561 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_LSB _u(26) 11562 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_ACCESS "RW" 11563 // ----------------------------------------------------------------------------- 11564 // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH 11565 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_RESET _u(0x0) 11566 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) 11567 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_MSB _u(25) 11568 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_LSB _u(25) 11569 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_ACCESS "RW" 11570 // ----------------------------------------------------------------------------- 11571 // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW 11572 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_RESET _u(0x0) 11573 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) 11574 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_MSB _u(24) 11575 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_LSB _u(24) 11576 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_ACCESS "RW" 11577 // ----------------------------------------------------------------------------- 11578 // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH 11579 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_RESET _u(0x0) 11580 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) 11581 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_MSB _u(23) 11582 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_LSB _u(23) 11583 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_ACCESS "RW" 11584 // ----------------------------------------------------------------------------- 11585 // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW 11586 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_RESET _u(0x0) 11587 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_BITS _u(0x00400000) 11588 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_MSB _u(22) 11589 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_LSB _u(22) 11590 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_ACCESS "RW" 11591 // ----------------------------------------------------------------------------- 11592 // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH 11593 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_RESET _u(0x0) 11594 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) 11595 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_MSB _u(21) 11596 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_LSB _u(21) 11597 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_ACCESS "RW" 11598 // ----------------------------------------------------------------------------- 11599 // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW 11600 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_RESET _u(0x0) 11601 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) 11602 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_MSB _u(20) 11603 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_LSB _u(20) 11604 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_ACCESS "RW" 11605 // ----------------------------------------------------------------------------- 11606 // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH 11607 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_RESET _u(0x0) 11608 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) 11609 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_MSB _u(19) 11610 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_LSB _u(19) 11611 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_ACCESS "RW" 11612 // ----------------------------------------------------------------------------- 11613 // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW 11614 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_RESET _u(0x0) 11615 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_BITS _u(0x00040000) 11616 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_MSB _u(18) 11617 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_LSB _u(18) 11618 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_ACCESS "RW" 11619 // ----------------------------------------------------------------------------- 11620 // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH 11621 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_RESET _u(0x0) 11622 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) 11623 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_MSB _u(17) 11624 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_LSB _u(17) 11625 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_ACCESS "RW" 11626 // ----------------------------------------------------------------------------- 11627 // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW 11628 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_RESET _u(0x0) 11629 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) 11630 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_MSB _u(16) 11631 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_LSB _u(16) 11632 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_ACCESS "RW" 11633 // ----------------------------------------------------------------------------- 11634 // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH 11635 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_RESET _u(0x0) 11636 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) 11637 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_MSB _u(15) 11638 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_LSB _u(15) 11639 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_ACCESS "RW" 11640 // ----------------------------------------------------------------------------- 11641 // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW 11642 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_RESET _u(0x0) 11643 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_BITS _u(0x00004000) 11644 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_MSB _u(14) 11645 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_LSB _u(14) 11646 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_ACCESS "RW" 11647 // ----------------------------------------------------------------------------- 11648 // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH 11649 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_RESET _u(0x0) 11650 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) 11651 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_MSB _u(13) 11652 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_LSB _u(13) 11653 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_ACCESS "RW" 11654 // ----------------------------------------------------------------------------- 11655 // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW 11656 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_RESET _u(0x0) 11657 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) 11658 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_MSB _u(12) 11659 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_LSB _u(12) 11660 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_ACCESS "RW" 11661 // ----------------------------------------------------------------------------- 11662 // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH 11663 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_RESET _u(0x0) 11664 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) 11665 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_MSB _u(11) 11666 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_LSB _u(11) 11667 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_ACCESS "RW" 11668 // ----------------------------------------------------------------------------- 11669 // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW 11670 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_RESET _u(0x0) 11671 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_BITS _u(0x00000400) 11672 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_MSB _u(10) 11673 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_LSB _u(10) 11674 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_ACCESS "RW" 11675 // ----------------------------------------------------------------------------- 11676 // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH 11677 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_RESET _u(0x0) 11678 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) 11679 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_MSB _u(9) 11680 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_LSB _u(9) 11681 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_ACCESS "RW" 11682 // ----------------------------------------------------------------------------- 11683 // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW 11684 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_RESET _u(0x0) 11685 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) 11686 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_MSB _u(8) 11687 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_LSB _u(8) 11688 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_ACCESS "RW" 11689 // ----------------------------------------------------------------------------- 11690 // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH 11691 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_RESET _u(0x0) 11692 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) 11693 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_MSB _u(7) 11694 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_LSB _u(7) 11695 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_ACCESS "RW" 11696 // ----------------------------------------------------------------------------- 11697 // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW 11698 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_RESET _u(0x0) 11699 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_BITS _u(0x00000040) 11700 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_MSB _u(6) 11701 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_LSB _u(6) 11702 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_ACCESS "RW" 11703 // ----------------------------------------------------------------------------- 11704 // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH 11705 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_RESET _u(0x0) 11706 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) 11707 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_MSB _u(5) 11708 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_LSB _u(5) 11709 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_ACCESS "RW" 11710 // ----------------------------------------------------------------------------- 11711 // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW 11712 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_RESET _u(0x0) 11713 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) 11714 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_MSB _u(4) 11715 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_LSB _u(4) 11716 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_ACCESS "RW" 11717 // ----------------------------------------------------------------------------- 11718 // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH 11719 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_RESET _u(0x0) 11720 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) 11721 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_MSB _u(3) 11722 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_LSB _u(3) 11723 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_ACCESS "RW" 11724 // ----------------------------------------------------------------------------- 11725 // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW 11726 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_RESET _u(0x0) 11727 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_BITS _u(0x00000004) 11728 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_MSB _u(2) 11729 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_LSB _u(2) 11730 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_ACCESS "RW" 11731 // ----------------------------------------------------------------------------- 11732 // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH 11733 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_RESET _u(0x0) 11734 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) 11735 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_MSB _u(1) 11736 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_LSB _u(1) 11737 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_ACCESS "RW" 11738 // ----------------------------------------------------------------------------- 11739 // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW 11740 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_RESET _u(0x0) 11741 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) 11742 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_MSB _u(0) 11743 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_LSB _u(0) 11744 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_ACCESS "RW" 11745 // ============================================================================= 11746 // Register : IO_BANK0_DORMANT_WAKE_INTE3 11747 // Description : Interrupt Enable for dormant_wake 11748 #define IO_BANK0_DORMANT_WAKE_INTE3_OFFSET _u(0x0000016c) 11749 #define IO_BANK0_DORMANT_WAKE_INTE3_BITS _u(0x00ffffff) 11750 #define IO_BANK0_DORMANT_WAKE_INTE3_RESET _u(0x00000000) 11751 // ----------------------------------------------------------------------------- 11752 // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH 11753 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_RESET _u(0x0) 11754 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) 11755 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_MSB _u(23) 11756 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_LSB _u(23) 11757 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_ACCESS "RW" 11758 // ----------------------------------------------------------------------------- 11759 // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW 11760 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_RESET _u(0x0) 11761 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_BITS _u(0x00400000) 11762 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_MSB _u(22) 11763 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_LSB _u(22) 11764 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_ACCESS "RW" 11765 // ----------------------------------------------------------------------------- 11766 // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH 11767 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_RESET _u(0x0) 11768 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) 11769 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_MSB _u(21) 11770 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_LSB _u(21) 11771 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_ACCESS "RW" 11772 // ----------------------------------------------------------------------------- 11773 // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW 11774 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_RESET _u(0x0) 11775 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) 11776 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_MSB _u(20) 11777 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_LSB _u(20) 11778 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_ACCESS "RW" 11779 // ----------------------------------------------------------------------------- 11780 // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH 11781 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_RESET _u(0x0) 11782 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) 11783 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_MSB _u(19) 11784 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_LSB _u(19) 11785 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_ACCESS "RW" 11786 // ----------------------------------------------------------------------------- 11787 // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW 11788 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_RESET _u(0x0) 11789 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_BITS _u(0x00040000) 11790 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_MSB _u(18) 11791 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_LSB _u(18) 11792 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_ACCESS "RW" 11793 // ----------------------------------------------------------------------------- 11794 // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH 11795 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_RESET _u(0x0) 11796 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) 11797 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_MSB _u(17) 11798 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_LSB _u(17) 11799 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_ACCESS "RW" 11800 // ----------------------------------------------------------------------------- 11801 // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW 11802 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_RESET _u(0x0) 11803 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) 11804 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_MSB _u(16) 11805 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_LSB _u(16) 11806 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_ACCESS "RW" 11807 // ----------------------------------------------------------------------------- 11808 // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH 11809 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_RESET _u(0x0) 11810 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) 11811 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_MSB _u(15) 11812 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_LSB _u(15) 11813 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_ACCESS "RW" 11814 // ----------------------------------------------------------------------------- 11815 // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW 11816 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_RESET _u(0x0) 11817 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_BITS _u(0x00004000) 11818 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_MSB _u(14) 11819 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_LSB _u(14) 11820 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_ACCESS "RW" 11821 // ----------------------------------------------------------------------------- 11822 // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH 11823 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_RESET _u(0x0) 11824 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) 11825 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_MSB _u(13) 11826 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_LSB _u(13) 11827 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_ACCESS "RW" 11828 // ----------------------------------------------------------------------------- 11829 // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW 11830 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_RESET _u(0x0) 11831 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) 11832 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_MSB _u(12) 11833 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_LSB _u(12) 11834 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_ACCESS "RW" 11835 // ----------------------------------------------------------------------------- 11836 // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH 11837 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_RESET _u(0x0) 11838 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) 11839 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_MSB _u(11) 11840 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_LSB _u(11) 11841 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_ACCESS "RW" 11842 // ----------------------------------------------------------------------------- 11843 // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW 11844 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_RESET _u(0x0) 11845 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_BITS _u(0x00000400) 11846 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_MSB _u(10) 11847 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_LSB _u(10) 11848 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_ACCESS "RW" 11849 // ----------------------------------------------------------------------------- 11850 // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH 11851 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_RESET _u(0x0) 11852 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) 11853 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_MSB _u(9) 11854 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_LSB _u(9) 11855 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_ACCESS "RW" 11856 // ----------------------------------------------------------------------------- 11857 // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW 11858 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_RESET _u(0x0) 11859 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) 11860 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_MSB _u(8) 11861 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_LSB _u(8) 11862 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_ACCESS "RW" 11863 // ----------------------------------------------------------------------------- 11864 // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH 11865 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_RESET _u(0x0) 11866 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) 11867 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_MSB _u(7) 11868 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_LSB _u(7) 11869 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_ACCESS "RW" 11870 // ----------------------------------------------------------------------------- 11871 // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW 11872 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_RESET _u(0x0) 11873 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_BITS _u(0x00000040) 11874 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_MSB _u(6) 11875 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_LSB _u(6) 11876 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_ACCESS "RW" 11877 // ----------------------------------------------------------------------------- 11878 // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH 11879 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_RESET _u(0x0) 11880 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) 11881 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_MSB _u(5) 11882 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_LSB _u(5) 11883 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_ACCESS "RW" 11884 // ----------------------------------------------------------------------------- 11885 // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW 11886 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_RESET _u(0x0) 11887 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) 11888 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_MSB _u(4) 11889 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_LSB _u(4) 11890 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_ACCESS "RW" 11891 // ----------------------------------------------------------------------------- 11892 // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH 11893 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_RESET _u(0x0) 11894 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) 11895 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_MSB _u(3) 11896 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_LSB _u(3) 11897 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_ACCESS "RW" 11898 // ----------------------------------------------------------------------------- 11899 // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW 11900 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_RESET _u(0x0) 11901 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_BITS _u(0x00000004) 11902 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_MSB _u(2) 11903 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_LSB _u(2) 11904 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_ACCESS "RW" 11905 // ----------------------------------------------------------------------------- 11906 // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH 11907 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_RESET _u(0x0) 11908 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) 11909 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_MSB _u(1) 11910 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_LSB _u(1) 11911 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_ACCESS "RW" 11912 // ----------------------------------------------------------------------------- 11913 // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW 11914 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_RESET _u(0x0) 11915 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) 11916 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_MSB _u(0) 11917 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_LSB _u(0) 11918 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_ACCESS "RW" 11919 // ============================================================================= 11920 // Register : IO_BANK0_DORMANT_WAKE_INTF0 11921 // Description : Interrupt Force for dormant_wake 11922 #define IO_BANK0_DORMANT_WAKE_INTF0_OFFSET _u(0x00000170) 11923 #define IO_BANK0_DORMANT_WAKE_INTF0_BITS _u(0xffffffff) 11924 #define IO_BANK0_DORMANT_WAKE_INTF0_RESET _u(0x00000000) 11925 // ----------------------------------------------------------------------------- 11926 // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH 11927 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_RESET _u(0x0) 11928 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) 11929 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_MSB _u(31) 11930 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_LSB _u(31) 11931 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_ACCESS "RW" 11932 // ----------------------------------------------------------------------------- 11933 // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW 11934 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_RESET _u(0x0) 11935 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_BITS _u(0x40000000) 11936 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_MSB _u(30) 11937 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_LSB _u(30) 11938 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_ACCESS "RW" 11939 // ----------------------------------------------------------------------------- 11940 // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH 11941 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_RESET _u(0x0) 11942 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) 11943 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_MSB _u(29) 11944 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_LSB _u(29) 11945 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_ACCESS "RW" 11946 // ----------------------------------------------------------------------------- 11947 // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW 11948 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_RESET _u(0x0) 11949 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) 11950 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_MSB _u(28) 11951 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_LSB _u(28) 11952 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_ACCESS "RW" 11953 // ----------------------------------------------------------------------------- 11954 // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH 11955 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_RESET _u(0x0) 11956 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) 11957 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_MSB _u(27) 11958 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_LSB _u(27) 11959 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_ACCESS "RW" 11960 // ----------------------------------------------------------------------------- 11961 // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW 11962 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_RESET _u(0x0) 11963 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_BITS _u(0x04000000) 11964 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_MSB _u(26) 11965 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_LSB _u(26) 11966 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_ACCESS "RW" 11967 // ----------------------------------------------------------------------------- 11968 // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH 11969 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_RESET _u(0x0) 11970 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) 11971 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_MSB _u(25) 11972 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_LSB _u(25) 11973 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_ACCESS "RW" 11974 // ----------------------------------------------------------------------------- 11975 // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW 11976 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_RESET _u(0x0) 11977 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) 11978 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_MSB _u(24) 11979 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_LSB _u(24) 11980 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_ACCESS "RW" 11981 // ----------------------------------------------------------------------------- 11982 // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH 11983 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_RESET _u(0x0) 11984 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) 11985 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_MSB _u(23) 11986 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_LSB _u(23) 11987 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_ACCESS "RW" 11988 // ----------------------------------------------------------------------------- 11989 // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW 11990 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_RESET _u(0x0) 11991 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_BITS _u(0x00400000) 11992 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_MSB _u(22) 11993 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_LSB _u(22) 11994 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_ACCESS "RW" 11995 // ----------------------------------------------------------------------------- 11996 // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH 11997 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_RESET _u(0x0) 11998 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) 11999 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_MSB _u(21) 12000 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_LSB _u(21) 12001 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_ACCESS "RW" 12002 // ----------------------------------------------------------------------------- 12003 // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW 12004 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_RESET _u(0x0) 12005 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) 12006 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_MSB _u(20) 12007 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_LSB _u(20) 12008 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_ACCESS "RW" 12009 // ----------------------------------------------------------------------------- 12010 // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH 12011 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_RESET _u(0x0) 12012 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) 12013 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_MSB _u(19) 12014 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_LSB _u(19) 12015 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_ACCESS "RW" 12016 // ----------------------------------------------------------------------------- 12017 // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW 12018 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_RESET _u(0x0) 12019 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_BITS _u(0x00040000) 12020 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_MSB _u(18) 12021 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_LSB _u(18) 12022 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_ACCESS "RW" 12023 // ----------------------------------------------------------------------------- 12024 // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH 12025 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_RESET _u(0x0) 12026 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) 12027 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_MSB _u(17) 12028 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_LSB _u(17) 12029 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_ACCESS "RW" 12030 // ----------------------------------------------------------------------------- 12031 // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW 12032 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_RESET _u(0x0) 12033 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) 12034 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_MSB _u(16) 12035 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_LSB _u(16) 12036 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_ACCESS "RW" 12037 // ----------------------------------------------------------------------------- 12038 // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH 12039 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_RESET _u(0x0) 12040 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) 12041 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_MSB _u(15) 12042 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_LSB _u(15) 12043 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_ACCESS "RW" 12044 // ----------------------------------------------------------------------------- 12045 // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW 12046 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_RESET _u(0x0) 12047 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_BITS _u(0x00004000) 12048 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_MSB _u(14) 12049 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_LSB _u(14) 12050 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_ACCESS "RW" 12051 // ----------------------------------------------------------------------------- 12052 // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH 12053 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_RESET _u(0x0) 12054 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) 12055 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_MSB _u(13) 12056 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_LSB _u(13) 12057 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_ACCESS "RW" 12058 // ----------------------------------------------------------------------------- 12059 // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW 12060 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_RESET _u(0x0) 12061 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) 12062 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_MSB _u(12) 12063 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_LSB _u(12) 12064 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_ACCESS "RW" 12065 // ----------------------------------------------------------------------------- 12066 // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH 12067 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_RESET _u(0x0) 12068 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) 12069 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_MSB _u(11) 12070 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_LSB _u(11) 12071 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_ACCESS "RW" 12072 // ----------------------------------------------------------------------------- 12073 // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW 12074 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_RESET _u(0x0) 12075 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_BITS _u(0x00000400) 12076 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_MSB _u(10) 12077 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_LSB _u(10) 12078 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_ACCESS "RW" 12079 // ----------------------------------------------------------------------------- 12080 // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH 12081 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_RESET _u(0x0) 12082 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) 12083 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_MSB _u(9) 12084 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_LSB _u(9) 12085 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_ACCESS "RW" 12086 // ----------------------------------------------------------------------------- 12087 // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW 12088 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_RESET _u(0x0) 12089 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) 12090 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_MSB _u(8) 12091 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_LSB _u(8) 12092 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_ACCESS "RW" 12093 // ----------------------------------------------------------------------------- 12094 // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH 12095 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_RESET _u(0x0) 12096 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) 12097 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_MSB _u(7) 12098 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_LSB _u(7) 12099 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_ACCESS "RW" 12100 // ----------------------------------------------------------------------------- 12101 // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW 12102 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_RESET _u(0x0) 12103 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_BITS _u(0x00000040) 12104 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_MSB _u(6) 12105 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_LSB _u(6) 12106 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_ACCESS "RW" 12107 // ----------------------------------------------------------------------------- 12108 // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH 12109 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_RESET _u(0x0) 12110 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) 12111 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_MSB _u(5) 12112 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_LSB _u(5) 12113 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_ACCESS "RW" 12114 // ----------------------------------------------------------------------------- 12115 // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW 12116 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_RESET _u(0x0) 12117 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) 12118 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_MSB _u(4) 12119 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_LSB _u(4) 12120 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_ACCESS "RW" 12121 // ----------------------------------------------------------------------------- 12122 // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH 12123 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_RESET _u(0x0) 12124 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) 12125 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_MSB _u(3) 12126 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_LSB _u(3) 12127 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_ACCESS "RW" 12128 // ----------------------------------------------------------------------------- 12129 // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW 12130 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_RESET _u(0x0) 12131 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_BITS _u(0x00000004) 12132 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_MSB _u(2) 12133 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_LSB _u(2) 12134 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_ACCESS "RW" 12135 // ----------------------------------------------------------------------------- 12136 // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH 12137 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_RESET _u(0x0) 12138 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) 12139 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_MSB _u(1) 12140 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_LSB _u(1) 12141 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_ACCESS "RW" 12142 // ----------------------------------------------------------------------------- 12143 // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW 12144 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_RESET _u(0x0) 12145 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) 12146 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_MSB _u(0) 12147 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_LSB _u(0) 12148 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_ACCESS "RW" 12149 // ============================================================================= 12150 // Register : IO_BANK0_DORMANT_WAKE_INTF1 12151 // Description : Interrupt Force for dormant_wake 12152 #define IO_BANK0_DORMANT_WAKE_INTF1_OFFSET _u(0x00000174) 12153 #define IO_BANK0_DORMANT_WAKE_INTF1_BITS _u(0xffffffff) 12154 #define IO_BANK0_DORMANT_WAKE_INTF1_RESET _u(0x00000000) 12155 // ----------------------------------------------------------------------------- 12156 // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH 12157 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_RESET _u(0x0) 12158 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) 12159 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_MSB _u(31) 12160 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_LSB _u(31) 12161 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_ACCESS "RW" 12162 // ----------------------------------------------------------------------------- 12163 // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW 12164 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_RESET _u(0x0) 12165 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_BITS _u(0x40000000) 12166 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_MSB _u(30) 12167 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_LSB _u(30) 12168 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_ACCESS "RW" 12169 // ----------------------------------------------------------------------------- 12170 // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH 12171 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_RESET _u(0x0) 12172 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) 12173 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_MSB _u(29) 12174 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_LSB _u(29) 12175 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_ACCESS "RW" 12176 // ----------------------------------------------------------------------------- 12177 // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW 12178 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_RESET _u(0x0) 12179 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) 12180 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_MSB _u(28) 12181 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_LSB _u(28) 12182 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_ACCESS "RW" 12183 // ----------------------------------------------------------------------------- 12184 // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH 12185 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_RESET _u(0x0) 12186 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) 12187 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_MSB _u(27) 12188 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_LSB _u(27) 12189 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_ACCESS "RW" 12190 // ----------------------------------------------------------------------------- 12191 // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW 12192 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_RESET _u(0x0) 12193 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_BITS _u(0x04000000) 12194 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_MSB _u(26) 12195 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_LSB _u(26) 12196 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_ACCESS "RW" 12197 // ----------------------------------------------------------------------------- 12198 // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH 12199 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_RESET _u(0x0) 12200 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) 12201 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_MSB _u(25) 12202 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_LSB _u(25) 12203 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_ACCESS "RW" 12204 // ----------------------------------------------------------------------------- 12205 // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW 12206 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_RESET _u(0x0) 12207 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) 12208 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_MSB _u(24) 12209 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_LSB _u(24) 12210 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_ACCESS "RW" 12211 // ----------------------------------------------------------------------------- 12212 // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH 12213 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_RESET _u(0x0) 12214 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) 12215 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_MSB _u(23) 12216 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_LSB _u(23) 12217 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_ACCESS "RW" 12218 // ----------------------------------------------------------------------------- 12219 // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW 12220 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_RESET _u(0x0) 12221 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_BITS _u(0x00400000) 12222 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_MSB _u(22) 12223 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_LSB _u(22) 12224 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_ACCESS "RW" 12225 // ----------------------------------------------------------------------------- 12226 // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH 12227 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_RESET _u(0x0) 12228 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) 12229 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_MSB _u(21) 12230 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_LSB _u(21) 12231 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_ACCESS "RW" 12232 // ----------------------------------------------------------------------------- 12233 // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW 12234 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_RESET _u(0x0) 12235 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) 12236 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_MSB _u(20) 12237 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_LSB _u(20) 12238 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_ACCESS "RW" 12239 // ----------------------------------------------------------------------------- 12240 // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH 12241 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_RESET _u(0x0) 12242 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) 12243 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_MSB _u(19) 12244 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_LSB _u(19) 12245 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_ACCESS "RW" 12246 // ----------------------------------------------------------------------------- 12247 // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW 12248 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_RESET _u(0x0) 12249 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_BITS _u(0x00040000) 12250 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_MSB _u(18) 12251 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_LSB _u(18) 12252 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_ACCESS "RW" 12253 // ----------------------------------------------------------------------------- 12254 // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH 12255 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_RESET _u(0x0) 12256 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) 12257 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_MSB _u(17) 12258 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_LSB _u(17) 12259 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_ACCESS "RW" 12260 // ----------------------------------------------------------------------------- 12261 // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW 12262 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_RESET _u(0x0) 12263 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) 12264 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_MSB _u(16) 12265 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_LSB _u(16) 12266 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_ACCESS "RW" 12267 // ----------------------------------------------------------------------------- 12268 // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH 12269 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_RESET _u(0x0) 12270 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) 12271 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_MSB _u(15) 12272 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_LSB _u(15) 12273 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_ACCESS "RW" 12274 // ----------------------------------------------------------------------------- 12275 // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW 12276 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_RESET _u(0x0) 12277 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_BITS _u(0x00004000) 12278 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_MSB _u(14) 12279 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_LSB _u(14) 12280 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_ACCESS "RW" 12281 // ----------------------------------------------------------------------------- 12282 // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH 12283 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_RESET _u(0x0) 12284 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) 12285 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_MSB _u(13) 12286 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_LSB _u(13) 12287 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_ACCESS "RW" 12288 // ----------------------------------------------------------------------------- 12289 // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW 12290 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_RESET _u(0x0) 12291 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) 12292 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_MSB _u(12) 12293 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_LSB _u(12) 12294 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_ACCESS "RW" 12295 // ----------------------------------------------------------------------------- 12296 // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH 12297 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_RESET _u(0x0) 12298 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) 12299 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_MSB _u(11) 12300 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_LSB _u(11) 12301 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_ACCESS "RW" 12302 // ----------------------------------------------------------------------------- 12303 // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW 12304 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_RESET _u(0x0) 12305 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_BITS _u(0x00000400) 12306 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_MSB _u(10) 12307 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_LSB _u(10) 12308 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_ACCESS "RW" 12309 // ----------------------------------------------------------------------------- 12310 // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH 12311 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_RESET _u(0x0) 12312 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) 12313 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_MSB _u(9) 12314 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_LSB _u(9) 12315 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_ACCESS "RW" 12316 // ----------------------------------------------------------------------------- 12317 // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW 12318 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_RESET _u(0x0) 12319 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) 12320 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_MSB _u(8) 12321 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_LSB _u(8) 12322 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_ACCESS "RW" 12323 // ----------------------------------------------------------------------------- 12324 // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH 12325 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_RESET _u(0x0) 12326 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) 12327 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_MSB _u(7) 12328 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_LSB _u(7) 12329 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_ACCESS "RW" 12330 // ----------------------------------------------------------------------------- 12331 // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW 12332 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_RESET _u(0x0) 12333 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_BITS _u(0x00000040) 12334 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_MSB _u(6) 12335 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_LSB _u(6) 12336 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_ACCESS "RW" 12337 // ----------------------------------------------------------------------------- 12338 // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH 12339 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_RESET _u(0x0) 12340 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) 12341 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_MSB _u(5) 12342 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_LSB _u(5) 12343 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_ACCESS "RW" 12344 // ----------------------------------------------------------------------------- 12345 // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW 12346 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_RESET _u(0x0) 12347 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) 12348 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_MSB _u(4) 12349 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_LSB _u(4) 12350 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_ACCESS "RW" 12351 // ----------------------------------------------------------------------------- 12352 // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH 12353 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_RESET _u(0x0) 12354 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) 12355 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_MSB _u(3) 12356 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_LSB _u(3) 12357 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_ACCESS "RW" 12358 // ----------------------------------------------------------------------------- 12359 // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW 12360 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_RESET _u(0x0) 12361 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_BITS _u(0x00000004) 12362 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_MSB _u(2) 12363 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_LSB _u(2) 12364 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_ACCESS "RW" 12365 // ----------------------------------------------------------------------------- 12366 // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH 12367 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_RESET _u(0x0) 12368 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) 12369 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_MSB _u(1) 12370 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_LSB _u(1) 12371 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_ACCESS "RW" 12372 // ----------------------------------------------------------------------------- 12373 // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW 12374 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_RESET _u(0x0) 12375 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) 12376 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_MSB _u(0) 12377 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_LSB _u(0) 12378 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_ACCESS "RW" 12379 // ============================================================================= 12380 // Register : IO_BANK0_DORMANT_WAKE_INTF2 12381 // Description : Interrupt Force for dormant_wake 12382 #define IO_BANK0_DORMANT_WAKE_INTF2_OFFSET _u(0x00000178) 12383 #define IO_BANK0_DORMANT_WAKE_INTF2_BITS _u(0xffffffff) 12384 #define IO_BANK0_DORMANT_WAKE_INTF2_RESET _u(0x00000000) 12385 // ----------------------------------------------------------------------------- 12386 // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH 12387 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_RESET _u(0x0) 12388 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) 12389 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_MSB _u(31) 12390 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_LSB _u(31) 12391 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_ACCESS "RW" 12392 // ----------------------------------------------------------------------------- 12393 // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW 12394 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_RESET _u(0x0) 12395 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_BITS _u(0x40000000) 12396 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_MSB _u(30) 12397 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_LSB _u(30) 12398 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_ACCESS "RW" 12399 // ----------------------------------------------------------------------------- 12400 // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH 12401 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_RESET _u(0x0) 12402 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) 12403 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_MSB _u(29) 12404 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_LSB _u(29) 12405 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_ACCESS "RW" 12406 // ----------------------------------------------------------------------------- 12407 // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW 12408 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_RESET _u(0x0) 12409 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) 12410 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_MSB _u(28) 12411 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_LSB _u(28) 12412 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_ACCESS "RW" 12413 // ----------------------------------------------------------------------------- 12414 // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH 12415 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_RESET _u(0x0) 12416 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) 12417 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_MSB _u(27) 12418 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_LSB _u(27) 12419 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_ACCESS "RW" 12420 // ----------------------------------------------------------------------------- 12421 // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW 12422 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_RESET _u(0x0) 12423 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_BITS _u(0x04000000) 12424 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_MSB _u(26) 12425 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_LSB _u(26) 12426 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_ACCESS "RW" 12427 // ----------------------------------------------------------------------------- 12428 // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH 12429 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_RESET _u(0x0) 12430 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) 12431 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_MSB _u(25) 12432 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_LSB _u(25) 12433 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_ACCESS "RW" 12434 // ----------------------------------------------------------------------------- 12435 // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW 12436 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_RESET _u(0x0) 12437 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) 12438 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_MSB _u(24) 12439 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_LSB _u(24) 12440 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_ACCESS "RW" 12441 // ----------------------------------------------------------------------------- 12442 // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH 12443 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_RESET _u(0x0) 12444 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) 12445 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_MSB _u(23) 12446 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_LSB _u(23) 12447 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_ACCESS "RW" 12448 // ----------------------------------------------------------------------------- 12449 // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW 12450 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_RESET _u(0x0) 12451 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_BITS _u(0x00400000) 12452 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_MSB _u(22) 12453 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_LSB _u(22) 12454 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_ACCESS "RW" 12455 // ----------------------------------------------------------------------------- 12456 // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH 12457 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_RESET _u(0x0) 12458 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) 12459 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_MSB _u(21) 12460 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_LSB _u(21) 12461 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_ACCESS "RW" 12462 // ----------------------------------------------------------------------------- 12463 // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW 12464 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_RESET _u(0x0) 12465 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) 12466 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_MSB _u(20) 12467 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_LSB _u(20) 12468 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_ACCESS "RW" 12469 // ----------------------------------------------------------------------------- 12470 // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH 12471 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_RESET _u(0x0) 12472 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) 12473 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_MSB _u(19) 12474 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_LSB _u(19) 12475 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_ACCESS "RW" 12476 // ----------------------------------------------------------------------------- 12477 // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW 12478 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_RESET _u(0x0) 12479 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_BITS _u(0x00040000) 12480 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_MSB _u(18) 12481 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_LSB _u(18) 12482 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_ACCESS "RW" 12483 // ----------------------------------------------------------------------------- 12484 // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH 12485 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_RESET _u(0x0) 12486 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) 12487 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_MSB _u(17) 12488 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_LSB _u(17) 12489 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_ACCESS "RW" 12490 // ----------------------------------------------------------------------------- 12491 // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW 12492 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_RESET _u(0x0) 12493 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) 12494 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_MSB _u(16) 12495 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_LSB _u(16) 12496 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_ACCESS "RW" 12497 // ----------------------------------------------------------------------------- 12498 // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH 12499 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_RESET _u(0x0) 12500 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) 12501 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_MSB _u(15) 12502 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_LSB _u(15) 12503 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_ACCESS "RW" 12504 // ----------------------------------------------------------------------------- 12505 // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW 12506 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_RESET _u(0x0) 12507 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_BITS _u(0x00004000) 12508 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_MSB _u(14) 12509 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_LSB _u(14) 12510 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_ACCESS "RW" 12511 // ----------------------------------------------------------------------------- 12512 // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH 12513 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_RESET _u(0x0) 12514 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) 12515 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_MSB _u(13) 12516 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_LSB _u(13) 12517 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_ACCESS "RW" 12518 // ----------------------------------------------------------------------------- 12519 // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW 12520 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_RESET _u(0x0) 12521 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) 12522 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_MSB _u(12) 12523 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_LSB _u(12) 12524 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_ACCESS "RW" 12525 // ----------------------------------------------------------------------------- 12526 // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH 12527 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_RESET _u(0x0) 12528 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) 12529 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_MSB _u(11) 12530 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_LSB _u(11) 12531 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_ACCESS "RW" 12532 // ----------------------------------------------------------------------------- 12533 // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW 12534 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_RESET _u(0x0) 12535 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_BITS _u(0x00000400) 12536 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_MSB _u(10) 12537 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_LSB _u(10) 12538 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_ACCESS "RW" 12539 // ----------------------------------------------------------------------------- 12540 // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH 12541 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_RESET _u(0x0) 12542 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) 12543 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_MSB _u(9) 12544 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_LSB _u(9) 12545 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_ACCESS "RW" 12546 // ----------------------------------------------------------------------------- 12547 // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW 12548 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_RESET _u(0x0) 12549 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) 12550 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_MSB _u(8) 12551 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_LSB _u(8) 12552 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_ACCESS "RW" 12553 // ----------------------------------------------------------------------------- 12554 // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH 12555 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_RESET _u(0x0) 12556 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) 12557 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_MSB _u(7) 12558 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_LSB _u(7) 12559 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_ACCESS "RW" 12560 // ----------------------------------------------------------------------------- 12561 // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW 12562 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_RESET _u(0x0) 12563 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_BITS _u(0x00000040) 12564 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_MSB _u(6) 12565 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_LSB _u(6) 12566 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_ACCESS "RW" 12567 // ----------------------------------------------------------------------------- 12568 // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH 12569 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_RESET _u(0x0) 12570 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) 12571 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_MSB _u(5) 12572 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_LSB _u(5) 12573 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_ACCESS "RW" 12574 // ----------------------------------------------------------------------------- 12575 // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW 12576 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_RESET _u(0x0) 12577 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) 12578 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_MSB _u(4) 12579 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_LSB _u(4) 12580 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_ACCESS "RW" 12581 // ----------------------------------------------------------------------------- 12582 // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH 12583 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_RESET _u(0x0) 12584 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) 12585 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_MSB _u(3) 12586 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_LSB _u(3) 12587 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_ACCESS "RW" 12588 // ----------------------------------------------------------------------------- 12589 // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW 12590 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_RESET _u(0x0) 12591 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_BITS _u(0x00000004) 12592 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_MSB _u(2) 12593 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_LSB _u(2) 12594 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_ACCESS "RW" 12595 // ----------------------------------------------------------------------------- 12596 // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH 12597 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_RESET _u(0x0) 12598 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) 12599 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_MSB _u(1) 12600 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_LSB _u(1) 12601 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_ACCESS "RW" 12602 // ----------------------------------------------------------------------------- 12603 // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW 12604 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_RESET _u(0x0) 12605 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) 12606 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_MSB _u(0) 12607 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_LSB _u(0) 12608 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_ACCESS "RW" 12609 // ============================================================================= 12610 // Register : IO_BANK0_DORMANT_WAKE_INTF3 12611 // Description : Interrupt Force for dormant_wake 12612 #define IO_BANK0_DORMANT_WAKE_INTF3_OFFSET _u(0x0000017c) 12613 #define IO_BANK0_DORMANT_WAKE_INTF3_BITS _u(0x00ffffff) 12614 #define IO_BANK0_DORMANT_WAKE_INTF3_RESET _u(0x00000000) 12615 // ----------------------------------------------------------------------------- 12616 // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH 12617 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_RESET _u(0x0) 12618 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) 12619 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_MSB _u(23) 12620 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_LSB _u(23) 12621 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_ACCESS "RW" 12622 // ----------------------------------------------------------------------------- 12623 // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW 12624 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_RESET _u(0x0) 12625 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_BITS _u(0x00400000) 12626 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_MSB _u(22) 12627 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_LSB _u(22) 12628 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_ACCESS "RW" 12629 // ----------------------------------------------------------------------------- 12630 // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH 12631 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_RESET _u(0x0) 12632 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) 12633 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_MSB _u(21) 12634 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_LSB _u(21) 12635 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_ACCESS "RW" 12636 // ----------------------------------------------------------------------------- 12637 // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW 12638 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_RESET _u(0x0) 12639 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) 12640 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_MSB _u(20) 12641 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_LSB _u(20) 12642 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_ACCESS "RW" 12643 // ----------------------------------------------------------------------------- 12644 // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH 12645 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_RESET _u(0x0) 12646 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) 12647 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_MSB _u(19) 12648 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_LSB _u(19) 12649 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_ACCESS "RW" 12650 // ----------------------------------------------------------------------------- 12651 // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW 12652 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_RESET _u(0x0) 12653 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_BITS _u(0x00040000) 12654 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_MSB _u(18) 12655 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_LSB _u(18) 12656 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_ACCESS "RW" 12657 // ----------------------------------------------------------------------------- 12658 // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH 12659 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_RESET _u(0x0) 12660 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) 12661 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_MSB _u(17) 12662 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_LSB _u(17) 12663 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_ACCESS "RW" 12664 // ----------------------------------------------------------------------------- 12665 // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW 12666 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_RESET _u(0x0) 12667 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) 12668 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_MSB _u(16) 12669 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_LSB _u(16) 12670 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_ACCESS "RW" 12671 // ----------------------------------------------------------------------------- 12672 // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH 12673 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_RESET _u(0x0) 12674 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) 12675 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_MSB _u(15) 12676 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_LSB _u(15) 12677 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_ACCESS "RW" 12678 // ----------------------------------------------------------------------------- 12679 // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW 12680 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_RESET _u(0x0) 12681 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_BITS _u(0x00004000) 12682 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_MSB _u(14) 12683 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_LSB _u(14) 12684 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_ACCESS "RW" 12685 // ----------------------------------------------------------------------------- 12686 // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH 12687 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_RESET _u(0x0) 12688 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) 12689 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_MSB _u(13) 12690 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_LSB _u(13) 12691 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_ACCESS "RW" 12692 // ----------------------------------------------------------------------------- 12693 // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW 12694 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_RESET _u(0x0) 12695 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) 12696 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_MSB _u(12) 12697 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_LSB _u(12) 12698 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_ACCESS "RW" 12699 // ----------------------------------------------------------------------------- 12700 // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH 12701 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_RESET _u(0x0) 12702 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) 12703 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_MSB _u(11) 12704 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_LSB _u(11) 12705 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_ACCESS "RW" 12706 // ----------------------------------------------------------------------------- 12707 // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW 12708 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_RESET _u(0x0) 12709 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_BITS _u(0x00000400) 12710 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_MSB _u(10) 12711 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_LSB _u(10) 12712 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_ACCESS "RW" 12713 // ----------------------------------------------------------------------------- 12714 // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH 12715 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_RESET _u(0x0) 12716 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) 12717 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_MSB _u(9) 12718 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_LSB _u(9) 12719 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_ACCESS "RW" 12720 // ----------------------------------------------------------------------------- 12721 // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW 12722 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_RESET _u(0x0) 12723 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) 12724 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_MSB _u(8) 12725 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_LSB _u(8) 12726 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_ACCESS "RW" 12727 // ----------------------------------------------------------------------------- 12728 // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH 12729 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_RESET _u(0x0) 12730 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) 12731 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_MSB _u(7) 12732 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_LSB _u(7) 12733 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_ACCESS "RW" 12734 // ----------------------------------------------------------------------------- 12735 // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW 12736 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_RESET _u(0x0) 12737 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_BITS _u(0x00000040) 12738 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_MSB _u(6) 12739 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_LSB _u(6) 12740 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_ACCESS "RW" 12741 // ----------------------------------------------------------------------------- 12742 // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH 12743 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_RESET _u(0x0) 12744 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) 12745 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_MSB _u(5) 12746 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_LSB _u(5) 12747 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_ACCESS "RW" 12748 // ----------------------------------------------------------------------------- 12749 // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW 12750 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_RESET _u(0x0) 12751 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) 12752 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_MSB _u(4) 12753 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_LSB _u(4) 12754 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_ACCESS "RW" 12755 // ----------------------------------------------------------------------------- 12756 // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH 12757 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_RESET _u(0x0) 12758 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) 12759 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_MSB _u(3) 12760 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_LSB _u(3) 12761 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_ACCESS "RW" 12762 // ----------------------------------------------------------------------------- 12763 // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW 12764 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_RESET _u(0x0) 12765 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_BITS _u(0x00000004) 12766 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_MSB _u(2) 12767 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_LSB _u(2) 12768 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_ACCESS "RW" 12769 // ----------------------------------------------------------------------------- 12770 // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH 12771 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_RESET _u(0x0) 12772 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) 12773 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_MSB _u(1) 12774 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_LSB _u(1) 12775 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_ACCESS "RW" 12776 // ----------------------------------------------------------------------------- 12777 // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW 12778 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_RESET _u(0x0) 12779 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) 12780 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_MSB _u(0) 12781 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_LSB _u(0) 12782 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_ACCESS "RW" 12783 // ============================================================================= 12784 // Register : IO_BANK0_DORMANT_WAKE_INTS0 12785 // Description : Interrupt status after masking & forcing for dormant_wake 12786 #define IO_BANK0_DORMANT_WAKE_INTS0_OFFSET _u(0x00000180) 12787 #define IO_BANK0_DORMANT_WAKE_INTS0_BITS _u(0xffffffff) 12788 #define IO_BANK0_DORMANT_WAKE_INTS0_RESET _u(0x00000000) 12789 // ----------------------------------------------------------------------------- 12790 // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH 12791 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_RESET _u(0x0) 12792 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) 12793 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_MSB _u(31) 12794 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_LSB _u(31) 12795 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_ACCESS "RO" 12796 // ----------------------------------------------------------------------------- 12797 // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW 12798 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_RESET _u(0x0) 12799 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_BITS _u(0x40000000) 12800 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_MSB _u(30) 12801 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_LSB _u(30) 12802 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_ACCESS "RO" 12803 // ----------------------------------------------------------------------------- 12804 // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH 12805 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_RESET _u(0x0) 12806 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) 12807 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_MSB _u(29) 12808 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_LSB _u(29) 12809 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_ACCESS "RO" 12810 // ----------------------------------------------------------------------------- 12811 // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW 12812 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_RESET _u(0x0) 12813 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) 12814 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_MSB _u(28) 12815 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_LSB _u(28) 12816 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_ACCESS "RO" 12817 // ----------------------------------------------------------------------------- 12818 // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH 12819 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_RESET _u(0x0) 12820 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) 12821 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_MSB _u(27) 12822 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_LSB _u(27) 12823 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_ACCESS "RO" 12824 // ----------------------------------------------------------------------------- 12825 // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW 12826 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_RESET _u(0x0) 12827 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_BITS _u(0x04000000) 12828 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_MSB _u(26) 12829 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_LSB _u(26) 12830 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_ACCESS "RO" 12831 // ----------------------------------------------------------------------------- 12832 // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH 12833 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_RESET _u(0x0) 12834 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) 12835 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_MSB _u(25) 12836 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_LSB _u(25) 12837 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_ACCESS "RO" 12838 // ----------------------------------------------------------------------------- 12839 // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW 12840 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_RESET _u(0x0) 12841 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) 12842 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_MSB _u(24) 12843 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_LSB _u(24) 12844 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_ACCESS "RO" 12845 // ----------------------------------------------------------------------------- 12846 // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH 12847 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_RESET _u(0x0) 12848 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) 12849 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_MSB _u(23) 12850 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_LSB _u(23) 12851 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_ACCESS "RO" 12852 // ----------------------------------------------------------------------------- 12853 // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW 12854 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_RESET _u(0x0) 12855 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_BITS _u(0x00400000) 12856 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_MSB _u(22) 12857 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_LSB _u(22) 12858 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_ACCESS "RO" 12859 // ----------------------------------------------------------------------------- 12860 // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH 12861 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_RESET _u(0x0) 12862 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) 12863 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_MSB _u(21) 12864 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_LSB _u(21) 12865 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_ACCESS "RO" 12866 // ----------------------------------------------------------------------------- 12867 // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW 12868 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_RESET _u(0x0) 12869 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) 12870 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_MSB _u(20) 12871 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_LSB _u(20) 12872 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_ACCESS "RO" 12873 // ----------------------------------------------------------------------------- 12874 // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH 12875 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_RESET _u(0x0) 12876 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) 12877 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_MSB _u(19) 12878 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_LSB _u(19) 12879 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_ACCESS "RO" 12880 // ----------------------------------------------------------------------------- 12881 // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW 12882 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_RESET _u(0x0) 12883 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_BITS _u(0x00040000) 12884 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_MSB _u(18) 12885 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_LSB _u(18) 12886 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_ACCESS "RO" 12887 // ----------------------------------------------------------------------------- 12888 // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH 12889 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_RESET _u(0x0) 12890 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) 12891 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_MSB _u(17) 12892 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_LSB _u(17) 12893 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_ACCESS "RO" 12894 // ----------------------------------------------------------------------------- 12895 // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW 12896 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_RESET _u(0x0) 12897 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) 12898 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_MSB _u(16) 12899 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_LSB _u(16) 12900 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_ACCESS "RO" 12901 // ----------------------------------------------------------------------------- 12902 // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH 12903 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_RESET _u(0x0) 12904 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) 12905 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_MSB _u(15) 12906 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_LSB _u(15) 12907 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_ACCESS "RO" 12908 // ----------------------------------------------------------------------------- 12909 // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW 12910 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_RESET _u(0x0) 12911 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_BITS _u(0x00004000) 12912 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_MSB _u(14) 12913 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_LSB _u(14) 12914 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_ACCESS "RO" 12915 // ----------------------------------------------------------------------------- 12916 // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH 12917 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_RESET _u(0x0) 12918 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) 12919 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_MSB _u(13) 12920 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_LSB _u(13) 12921 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_ACCESS "RO" 12922 // ----------------------------------------------------------------------------- 12923 // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW 12924 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_RESET _u(0x0) 12925 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) 12926 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_MSB _u(12) 12927 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_LSB _u(12) 12928 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_ACCESS "RO" 12929 // ----------------------------------------------------------------------------- 12930 // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH 12931 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_RESET _u(0x0) 12932 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) 12933 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_MSB _u(11) 12934 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_LSB _u(11) 12935 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_ACCESS "RO" 12936 // ----------------------------------------------------------------------------- 12937 // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW 12938 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_RESET _u(0x0) 12939 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_BITS _u(0x00000400) 12940 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_MSB _u(10) 12941 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_LSB _u(10) 12942 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_ACCESS "RO" 12943 // ----------------------------------------------------------------------------- 12944 // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH 12945 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_RESET _u(0x0) 12946 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) 12947 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_MSB _u(9) 12948 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_LSB _u(9) 12949 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_ACCESS "RO" 12950 // ----------------------------------------------------------------------------- 12951 // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW 12952 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_RESET _u(0x0) 12953 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) 12954 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_MSB _u(8) 12955 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_LSB _u(8) 12956 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_ACCESS "RO" 12957 // ----------------------------------------------------------------------------- 12958 // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH 12959 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_RESET _u(0x0) 12960 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) 12961 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_MSB _u(7) 12962 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_LSB _u(7) 12963 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_ACCESS "RO" 12964 // ----------------------------------------------------------------------------- 12965 // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW 12966 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_RESET _u(0x0) 12967 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_BITS _u(0x00000040) 12968 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_MSB _u(6) 12969 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_LSB _u(6) 12970 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_ACCESS "RO" 12971 // ----------------------------------------------------------------------------- 12972 // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH 12973 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_RESET _u(0x0) 12974 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) 12975 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_MSB _u(5) 12976 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_LSB _u(5) 12977 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_ACCESS "RO" 12978 // ----------------------------------------------------------------------------- 12979 // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW 12980 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_RESET _u(0x0) 12981 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) 12982 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_MSB _u(4) 12983 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_LSB _u(4) 12984 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_ACCESS "RO" 12985 // ----------------------------------------------------------------------------- 12986 // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH 12987 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_RESET _u(0x0) 12988 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) 12989 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_MSB _u(3) 12990 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_LSB _u(3) 12991 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_ACCESS "RO" 12992 // ----------------------------------------------------------------------------- 12993 // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW 12994 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_RESET _u(0x0) 12995 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_BITS _u(0x00000004) 12996 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_MSB _u(2) 12997 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_LSB _u(2) 12998 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_ACCESS "RO" 12999 // ----------------------------------------------------------------------------- 13000 // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH 13001 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_RESET _u(0x0) 13002 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) 13003 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_MSB _u(1) 13004 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_LSB _u(1) 13005 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_ACCESS "RO" 13006 // ----------------------------------------------------------------------------- 13007 // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW 13008 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_RESET _u(0x0) 13009 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) 13010 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_MSB _u(0) 13011 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_LSB _u(0) 13012 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_ACCESS "RO" 13013 // ============================================================================= 13014 // Register : IO_BANK0_DORMANT_WAKE_INTS1 13015 // Description : Interrupt status after masking & forcing for dormant_wake 13016 #define IO_BANK0_DORMANT_WAKE_INTS1_OFFSET _u(0x00000184) 13017 #define IO_BANK0_DORMANT_WAKE_INTS1_BITS _u(0xffffffff) 13018 #define IO_BANK0_DORMANT_WAKE_INTS1_RESET _u(0x00000000) 13019 // ----------------------------------------------------------------------------- 13020 // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH 13021 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_RESET _u(0x0) 13022 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) 13023 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_MSB _u(31) 13024 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_LSB _u(31) 13025 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_ACCESS "RO" 13026 // ----------------------------------------------------------------------------- 13027 // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW 13028 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_RESET _u(0x0) 13029 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_BITS _u(0x40000000) 13030 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_MSB _u(30) 13031 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_LSB _u(30) 13032 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_ACCESS "RO" 13033 // ----------------------------------------------------------------------------- 13034 // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH 13035 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_RESET _u(0x0) 13036 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) 13037 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_MSB _u(29) 13038 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_LSB _u(29) 13039 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_ACCESS "RO" 13040 // ----------------------------------------------------------------------------- 13041 // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW 13042 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_RESET _u(0x0) 13043 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) 13044 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_MSB _u(28) 13045 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_LSB _u(28) 13046 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_ACCESS "RO" 13047 // ----------------------------------------------------------------------------- 13048 // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH 13049 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_RESET _u(0x0) 13050 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) 13051 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_MSB _u(27) 13052 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_LSB _u(27) 13053 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_ACCESS "RO" 13054 // ----------------------------------------------------------------------------- 13055 // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW 13056 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_RESET _u(0x0) 13057 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_BITS _u(0x04000000) 13058 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_MSB _u(26) 13059 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_LSB _u(26) 13060 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_ACCESS "RO" 13061 // ----------------------------------------------------------------------------- 13062 // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH 13063 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_RESET _u(0x0) 13064 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) 13065 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_MSB _u(25) 13066 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_LSB _u(25) 13067 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_ACCESS "RO" 13068 // ----------------------------------------------------------------------------- 13069 // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW 13070 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_RESET _u(0x0) 13071 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) 13072 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_MSB _u(24) 13073 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_LSB _u(24) 13074 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_ACCESS "RO" 13075 // ----------------------------------------------------------------------------- 13076 // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH 13077 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_RESET _u(0x0) 13078 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) 13079 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_MSB _u(23) 13080 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_LSB _u(23) 13081 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_ACCESS "RO" 13082 // ----------------------------------------------------------------------------- 13083 // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW 13084 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_RESET _u(0x0) 13085 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_BITS _u(0x00400000) 13086 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_MSB _u(22) 13087 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_LSB _u(22) 13088 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_ACCESS "RO" 13089 // ----------------------------------------------------------------------------- 13090 // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH 13091 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_RESET _u(0x0) 13092 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) 13093 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_MSB _u(21) 13094 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_LSB _u(21) 13095 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_ACCESS "RO" 13096 // ----------------------------------------------------------------------------- 13097 // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW 13098 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_RESET _u(0x0) 13099 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) 13100 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_MSB _u(20) 13101 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_LSB _u(20) 13102 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_ACCESS "RO" 13103 // ----------------------------------------------------------------------------- 13104 // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH 13105 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_RESET _u(0x0) 13106 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) 13107 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_MSB _u(19) 13108 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_LSB _u(19) 13109 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_ACCESS "RO" 13110 // ----------------------------------------------------------------------------- 13111 // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW 13112 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_RESET _u(0x0) 13113 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_BITS _u(0x00040000) 13114 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_MSB _u(18) 13115 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_LSB _u(18) 13116 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_ACCESS "RO" 13117 // ----------------------------------------------------------------------------- 13118 // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH 13119 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_RESET _u(0x0) 13120 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) 13121 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_MSB _u(17) 13122 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_LSB _u(17) 13123 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_ACCESS "RO" 13124 // ----------------------------------------------------------------------------- 13125 // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW 13126 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_RESET _u(0x0) 13127 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) 13128 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_MSB _u(16) 13129 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_LSB _u(16) 13130 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_ACCESS "RO" 13131 // ----------------------------------------------------------------------------- 13132 // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH 13133 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_RESET _u(0x0) 13134 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) 13135 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_MSB _u(15) 13136 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_LSB _u(15) 13137 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_ACCESS "RO" 13138 // ----------------------------------------------------------------------------- 13139 // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW 13140 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_RESET _u(0x0) 13141 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_BITS _u(0x00004000) 13142 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_MSB _u(14) 13143 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_LSB _u(14) 13144 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_ACCESS "RO" 13145 // ----------------------------------------------------------------------------- 13146 // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH 13147 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_RESET _u(0x0) 13148 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) 13149 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_MSB _u(13) 13150 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_LSB _u(13) 13151 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_ACCESS "RO" 13152 // ----------------------------------------------------------------------------- 13153 // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW 13154 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_RESET _u(0x0) 13155 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) 13156 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_MSB _u(12) 13157 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_LSB _u(12) 13158 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_ACCESS "RO" 13159 // ----------------------------------------------------------------------------- 13160 // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH 13161 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_RESET _u(0x0) 13162 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) 13163 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_MSB _u(11) 13164 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_LSB _u(11) 13165 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_ACCESS "RO" 13166 // ----------------------------------------------------------------------------- 13167 // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW 13168 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_RESET _u(0x0) 13169 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_BITS _u(0x00000400) 13170 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_MSB _u(10) 13171 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_LSB _u(10) 13172 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_ACCESS "RO" 13173 // ----------------------------------------------------------------------------- 13174 // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH 13175 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_RESET _u(0x0) 13176 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) 13177 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_MSB _u(9) 13178 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_LSB _u(9) 13179 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_ACCESS "RO" 13180 // ----------------------------------------------------------------------------- 13181 // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW 13182 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_RESET _u(0x0) 13183 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) 13184 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_MSB _u(8) 13185 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_LSB _u(8) 13186 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_ACCESS "RO" 13187 // ----------------------------------------------------------------------------- 13188 // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH 13189 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_RESET _u(0x0) 13190 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) 13191 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_MSB _u(7) 13192 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_LSB _u(7) 13193 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_ACCESS "RO" 13194 // ----------------------------------------------------------------------------- 13195 // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW 13196 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_RESET _u(0x0) 13197 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_BITS _u(0x00000040) 13198 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_MSB _u(6) 13199 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_LSB _u(6) 13200 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_ACCESS "RO" 13201 // ----------------------------------------------------------------------------- 13202 // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH 13203 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_RESET _u(0x0) 13204 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) 13205 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_MSB _u(5) 13206 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_LSB _u(5) 13207 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_ACCESS "RO" 13208 // ----------------------------------------------------------------------------- 13209 // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW 13210 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_RESET _u(0x0) 13211 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) 13212 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_MSB _u(4) 13213 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_LSB _u(4) 13214 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_ACCESS "RO" 13215 // ----------------------------------------------------------------------------- 13216 // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH 13217 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_RESET _u(0x0) 13218 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) 13219 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_MSB _u(3) 13220 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_LSB _u(3) 13221 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_ACCESS "RO" 13222 // ----------------------------------------------------------------------------- 13223 // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW 13224 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_RESET _u(0x0) 13225 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_BITS _u(0x00000004) 13226 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_MSB _u(2) 13227 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_LSB _u(2) 13228 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_ACCESS "RO" 13229 // ----------------------------------------------------------------------------- 13230 // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH 13231 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_RESET _u(0x0) 13232 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) 13233 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_MSB _u(1) 13234 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_LSB _u(1) 13235 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_ACCESS "RO" 13236 // ----------------------------------------------------------------------------- 13237 // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW 13238 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_RESET _u(0x0) 13239 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) 13240 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_MSB _u(0) 13241 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_LSB _u(0) 13242 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_ACCESS "RO" 13243 // ============================================================================= 13244 // Register : IO_BANK0_DORMANT_WAKE_INTS2 13245 // Description : Interrupt status after masking & forcing for dormant_wake 13246 #define IO_BANK0_DORMANT_WAKE_INTS2_OFFSET _u(0x00000188) 13247 #define IO_BANK0_DORMANT_WAKE_INTS2_BITS _u(0xffffffff) 13248 #define IO_BANK0_DORMANT_WAKE_INTS2_RESET _u(0x00000000) 13249 // ----------------------------------------------------------------------------- 13250 // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH 13251 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_RESET _u(0x0) 13252 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) 13253 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_MSB _u(31) 13254 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_LSB _u(31) 13255 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_ACCESS "RO" 13256 // ----------------------------------------------------------------------------- 13257 // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW 13258 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_RESET _u(0x0) 13259 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_BITS _u(0x40000000) 13260 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_MSB _u(30) 13261 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_LSB _u(30) 13262 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_ACCESS "RO" 13263 // ----------------------------------------------------------------------------- 13264 // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH 13265 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_RESET _u(0x0) 13266 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) 13267 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_MSB _u(29) 13268 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_LSB _u(29) 13269 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_ACCESS "RO" 13270 // ----------------------------------------------------------------------------- 13271 // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW 13272 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_RESET _u(0x0) 13273 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) 13274 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_MSB _u(28) 13275 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_LSB _u(28) 13276 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_ACCESS "RO" 13277 // ----------------------------------------------------------------------------- 13278 // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH 13279 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_RESET _u(0x0) 13280 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) 13281 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_MSB _u(27) 13282 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_LSB _u(27) 13283 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_ACCESS "RO" 13284 // ----------------------------------------------------------------------------- 13285 // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW 13286 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_RESET _u(0x0) 13287 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_BITS _u(0x04000000) 13288 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_MSB _u(26) 13289 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_LSB _u(26) 13290 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_ACCESS "RO" 13291 // ----------------------------------------------------------------------------- 13292 // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH 13293 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_RESET _u(0x0) 13294 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) 13295 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_MSB _u(25) 13296 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_LSB _u(25) 13297 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_ACCESS "RO" 13298 // ----------------------------------------------------------------------------- 13299 // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW 13300 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_RESET _u(0x0) 13301 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) 13302 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_MSB _u(24) 13303 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_LSB _u(24) 13304 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_ACCESS "RO" 13305 // ----------------------------------------------------------------------------- 13306 // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH 13307 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_RESET _u(0x0) 13308 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) 13309 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_MSB _u(23) 13310 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_LSB _u(23) 13311 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_ACCESS "RO" 13312 // ----------------------------------------------------------------------------- 13313 // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW 13314 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_RESET _u(0x0) 13315 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_BITS _u(0x00400000) 13316 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_MSB _u(22) 13317 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_LSB _u(22) 13318 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_ACCESS "RO" 13319 // ----------------------------------------------------------------------------- 13320 // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH 13321 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_RESET _u(0x0) 13322 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) 13323 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_MSB _u(21) 13324 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_LSB _u(21) 13325 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_ACCESS "RO" 13326 // ----------------------------------------------------------------------------- 13327 // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW 13328 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_RESET _u(0x0) 13329 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) 13330 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_MSB _u(20) 13331 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_LSB _u(20) 13332 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_ACCESS "RO" 13333 // ----------------------------------------------------------------------------- 13334 // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH 13335 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_RESET _u(0x0) 13336 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) 13337 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_MSB _u(19) 13338 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_LSB _u(19) 13339 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_ACCESS "RO" 13340 // ----------------------------------------------------------------------------- 13341 // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW 13342 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_RESET _u(0x0) 13343 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_BITS _u(0x00040000) 13344 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_MSB _u(18) 13345 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_LSB _u(18) 13346 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_ACCESS "RO" 13347 // ----------------------------------------------------------------------------- 13348 // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH 13349 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_RESET _u(0x0) 13350 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) 13351 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_MSB _u(17) 13352 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_LSB _u(17) 13353 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_ACCESS "RO" 13354 // ----------------------------------------------------------------------------- 13355 // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW 13356 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_RESET _u(0x0) 13357 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) 13358 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_MSB _u(16) 13359 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_LSB _u(16) 13360 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_ACCESS "RO" 13361 // ----------------------------------------------------------------------------- 13362 // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH 13363 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_RESET _u(0x0) 13364 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) 13365 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_MSB _u(15) 13366 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_LSB _u(15) 13367 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_ACCESS "RO" 13368 // ----------------------------------------------------------------------------- 13369 // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW 13370 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_RESET _u(0x0) 13371 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_BITS _u(0x00004000) 13372 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_MSB _u(14) 13373 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_LSB _u(14) 13374 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_ACCESS "RO" 13375 // ----------------------------------------------------------------------------- 13376 // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH 13377 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_RESET _u(0x0) 13378 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) 13379 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_MSB _u(13) 13380 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_LSB _u(13) 13381 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_ACCESS "RO" 13382 // ----------------------------------------------------------------------------- 13383 // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW 13384 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_RESET _u(0x0) 13385 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) 13386 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_MSB _u(12) 13387 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_LSB _u(12) 13388 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_ACCESS "RO" 13389 // ----------------------------------------------------------------------------- 13390 // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH 13391 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_RESET _u(0x0) 13392 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) 13393 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_MSB _u(11) 13394 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_LSB _u(11) 13395 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_ACCESS "RO" 13396 // ----------------------------------------------------------------------------- 13397 // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW 13398 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_RESET _u(0x0) 13399 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_BITS _u(0x00000400) 13400 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_MSB _u(10) 13401 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_LSB _u(10) 13402 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_ACCESS "RO" 13403 // ----------------------------------------------------------------------------- 13404 // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH 13405 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_RESET _u(0x0) 13406 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) 13407 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_MSB _u(9) 13408 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_LSB _u(9) 13409 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_ACCESS "RO" 13410 // ----------------------------------------------------------------------------- 13411 // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW 13412 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_RESET _u(0x0) 13413 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) 13414 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_MSB _u(8) 13415 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_LSB _u(8) 13416 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_ACCESS "RO" 13417 // ----------------------------------------------------------------------------- 13418 // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH 13419 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_RESET _u(0x0) 13420 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) 13421 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_MSB _u(7) 13422 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_LSB _u(7) 13423 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_ACCESS "RO" 13424 // ----------------------------------------------------------------------------- 13425 // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW 13426 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_RESET _u(0x0) 13427 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_BITS _u(0x00000040) 13428 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_MSB _u(6) 13429 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_LSB _u(6) 13430 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_ACCESS "RO" 13431 // ----------------------------------------------------------------------------- 13432 // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH 13433 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_RESET _u(0x0) 13434 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) 13435 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_MSB _u(5) 13436 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_LSB _u(5) 13437 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_ACCESS "RO" 13438 // ----------------------------------------------------------------------------- 13439 // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW 13440 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_RESET _u(0x0) 13441 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) 13442 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_MSB _u(4) 13443 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_LSB _u(4) 13444 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_ACCESS "RO" 13445 // ----------------------------------------------------------------------------- 13446 // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH 13447 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_RESET _u(0x0) 13448 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) 13449 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_MSB _u(3) 13450 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_LSB _u(3) 13451 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_ACCESS "RO" 13452 // ----------------------------------------------------------------------------- 13453 // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW 13454 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_RESET _u(0x0) 13455 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_BITS _u(0x00000004) 13456 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_MSB _u(2) 13457 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_LSB _u(2) 13458 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_ACCESS "RO" 13459 // ----------------------------------------------------------------------------- 13460 // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH 13461 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_RESET _u(0x0) 13462 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) 13463 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_MSB _u(1) 13464 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_LSB _u(1) 13465 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_ACCESS "RO" 13466 // ----------------------------------------------------------------------------- 13467 // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW 13468 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_RESET _u(0x0) 13469 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) 13470 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_MSB _u(0) 13471 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_LSB _u(0) 13472 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_ACCESS "RO" 13473 // ============================================================================= 13474 // Register : IO_BANK0_DORMANT_WAKE_INTS3 13475 // Description : Interrupt status after masking & forcing for dormant_wake 13476 #define IO_BANK0_DORMANT_WAKE_INTS3_OFFSET _u(0x0000018c) 13477 #define IO_BANK0_DORMANT_WAKE_INTS3_BITS _u(0x00ffffff) 13478 #define IO_BANK0_DORMANT_WAKE_INTS3_RESET _u(0x00000000) 13479 // ----------------------------------------------------------------------------- 13480 // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH 13481 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_RESET _u(0x0) 13482 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) 13483 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_MSB _u(23) 13484 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_LSB _u(23) 13485 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_ACCESS "RO" 13486 // ----------------------------------------------------------------------------- 13487 // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW 13488 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_RESET _u(0x0) 13489 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_BITS _u(0x00400000) 13490 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_MSB _u(22) 13491 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_LSB _u(22) 13492 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_ACCESS "RO" 13493 // ----------------------------------------------------------------------------- 13494 // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH 13495 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_RESET _u(0x0) 13496 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) 13497 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_MSB _u(21) 13498 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_LSB _u(21) 13499 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_ACCESS "RO" 13500 // ----------------------------------------------------------------------------- 13501 // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW 13502 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_RESET _u(0x0) 13503 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) 13504 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_MSB _u(20) 13505 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_LSB _u(20) 13506 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_ACCESS "RO" 13507 // ----------------------------------------------------------------------------- 13508 // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH 13509 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_RESET _u(0x0) 13510 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) 13511 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_MSB _u(19) 13512 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_LSB _u(19) 13513 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_ACCESS "RO" 13514 // ----------------------------------------------------------------------------- 13515 // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW 13516 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_RESET _u(0x0) 13517 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_BITS _u(0x00040000) 13518 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_MSB _u(18) 13519 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_LSB _u(18) 13520 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_ACCESS "RO" 13521 // ----------------------------------------------------------------------------- 13522 // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH 13523 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_RESET _u(0x0) 13524 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) 13525 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_MSB _u(17) 13526 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_LSB _u(17) 13527 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_ACCESS "RO" 13528 // ----------------------------------------------------------------------------- 13529 // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW 13530 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_RESET _u(0x0) 13531 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) 13532 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_MSB _u(16) 13533 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_LSB _u(16) 13534 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_ACCESS "RO" 13535 // ----------------------------------------------------------------------------- 13536 // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH 13537 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_RESET _u(0x0) 13538 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) 13539 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_MSB _u(15) 13540 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_LSB _u(15) 13541 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_ACCESS "RO" 13542 // ----------------------------------------------------------------------------- 13543 // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW 13544 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_RESET _u(0x0) 13545 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_BITS _u(0x00004000) 13546 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_MSB _u(14) 13547 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_LSB _u(14) 13548 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_ACCESS "RO" 13549 // ----------------------------------------------------------------------------- 13550 // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH 13551 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_RESET _u(0x0) 13552 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) 13553 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_MSB _u(13) 13554 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_LSB _u(13) 13555 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_ACCESS "RO" 13556 // ----------------------------------------------------------------------------- 13557 // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW 13558 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_RESET _u(0x0) 13559 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) 13560 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_MSB _u(12) 13561 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_LSB _u(12) 13562 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_ACCESS "RO" 13563 // ----------------------------------------------------------------------------- 13564 // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH 13565 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_RESET _u(0x0) 13566 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) 13567 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_MSB _u(11) 13568 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_LSB _u(11) 13569 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_ACCESS "RO" 13570 // ----------------------------------------------------------------------------- 13571 // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW 13572 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_RESET _u(0x0) 13573 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_BITS _u(0x00000400) 13574 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_MSB _u(10) 13575 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_LSB _u(10) 13576 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_ACCESS "RO" 13577 // ----------------------------------------------------------------------------- 13578 // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH 13579 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_RESET _u(0x0) 13580 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) 13581 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_MSB _u(9) 13582 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_LSB _u(9) 13583 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_ACCESS "RO" 13584 // ----------------------------------------------------------------------------- 13585 // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW 13586 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_RESET _u(0x0) 13587 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) 13588 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_MSB _u(8) 13589 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_LSB _u(8) 13590 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_ACCESS "RO" 13591 // ----------------------------------------------------------------------------- 13592 // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH 13593 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_RESET _u(0x0) 13594 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) 13595 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_MSB _u(7) 13596 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_LSB _u(7) 13597 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_ACCESS "RO" 13598 // ----------------------------------------------------------------------------- 13599 // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW 13600 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_RESET _u(0x0) 13601 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_BITS _u(0x00000040) 13602 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_MSB _u(6) 13603 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_LSB _u(6) 13604 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_ACCESS "RO" 13605 // ----------------------------------------------------------------------------- 13606 // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH 13607 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_RESET _u(0x0) 13608 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) 13609 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_MSB _u(5) 13610 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_LSB _u(5) 13611 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_ACCESS "RO" 13612 // ----------------------------------------------------------------------------- 13613 // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW 13614 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_RESET _u(0x0) 13615 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) 13616 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_MSB _u(4) 13617 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_LSB _u(4) 13618 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_ACCESS "RO" 13619 // ----------------------------------------------------------------------------- 13620 // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH 13621 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_RESET _u(0x0) 13622 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) 13623 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_MSB _u(3) 13624 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_LSB _u(3) 13625 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_ACCESS "RO" 13626 // ----------------------------------------------------------------------------- 13627 // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW 13628 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_RESET _u(0x0) 13629 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_BITS _u(0x00000004) 13630 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_MSB _u(2) 13631 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_LSB _u(2) 13632 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_ACCESS "RO" 13633 // ----------------------------------------------------------------------------- 13634 // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH 13635 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_RESET _u(0x0) 13636 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) 13637 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_MSB _u(1) 13638 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_LSB _u(1) 13639 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_ACCESS "RO" 13640 // ----------------------------------------------------------------------------- 13641 // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW 13642 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_RESET _u(0x0) 13643 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) 13644 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_MSB _u(0) 13645 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_LSB _u(0) 13646 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_ACCESS "RO" 13647 // ============================================================================= 13648 #endif // _HARDWARE_REGS_IO_BANK0_H 13649 13650