1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
2 
3 /**
4  * Copyright (c) 2024 Raspberry Pi Ltd.
5  *
6  * SPDX-License-Identifier: BSD-3-Clause
7  */
8 // =============================================================================
9 // Register block : IO_QSPI
10 // Version        : 1
11 // Bus type       : apb
12 // =============================================================================
13 #ifndef _HARDWARE_REGS_IO_QSPI_H
14 #define _HARDWARE_REGS_IO_QSPI_H
15 // =============================================================================
16 // Register    : IO_QSPI_GPIO_QSPI_SCLK_STATUS
17 // Description : GPIO status
18 #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OFFSET _u(0x00000000)
19 #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_BITS   _u(0x050a3300)
20 #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_RESET  _u(0x00000000)
21 // -----------------------------------------------------------------------------
22 // Field       : IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC
23 // Description : interrupt to processors, after override is applied
24 #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_RESET  _u(0x0)
25 #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_BITS   _u(0x04000000)
26 #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_MSB    _u(26)
27 #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_LSB    _u(26)
28 #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_ACCESS "RO"
29 // -----------------------------------------------------------------------------
30 // Field       : IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQFROMPAD
31 // Description : interrupt from pad before override is applied
32 #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQFROMPAD_RESET  _u(0x0)
33 #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQFROMPAD_BITS   _u(0x01000000)
34 #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQFROMPAD_MSB    _u(24)
35 #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQFROMPAD_LSB    _u(24)
36 #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQFROMPAD_ACCESS "RO"
37 // -----------------------------------------------------------------------------
38 // Field       : IO_QSPI_GPIO_QSPI_SCLK_STATUS_INTOPERI
39 // Description : input signal to peripheral, after override is applied
40 #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INTOPERI_RESET  _u(0x0)
41 #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INTOPERI_BITS   _u(0x00080000)
42 #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INTOPERI_MSB    _u(19)
43 #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INTOPERI_LSB    _u(19)
44 #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INTOPERI_ACCESS "RO"
45 // -----------------------------------------------------------------------------
46 // Field       : IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD
47 // Description : input signal from pad, before override is applied
48 #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD_RESET  _u(0x0)
49 #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD_BITS   _u(0x00020000)
50 #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD_MSB    _u(17)
51 #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD_LSB    _u(17)
52 #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD_ACCESS "RO"
53 // -----------------------------------------------------------------------------
54 // Field       : IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD
55 // Description : output enable to pad after register override is applied
56 #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD_RESET  _u(0x0)
57 #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD_BITS   _u(0x00002000)
58 #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD_MSB    _u(13)
59 #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD_LSB    _u(13)
60 #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD_ACCESS "RO"
61 // -----------------------------------------------------------------------------
62 // Field       : IO_QSPI_GPIO_QSPI_SCLK_STATUS_OEFROMPERI
63 // Description : output enable from selected peripheral, before register
64 //               override is applied
65 #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OEFROMPERI_RESET  _u(0x0)
66 #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OEFROMPERI_BITS   _u(0x00001000)
67 #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OEFROMPERI_MSB    _u(12)
68 #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OEFROMPERI_LSB    _u(12)
69 #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OEFROMPERI_ACCESS "RO"
70 // -----------------------------------------------------------------------------
71 // Field       : IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD
72 // Description : output signal to pad after register override is applied
73 #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD_RESET  _u(0x0)
74 #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD_BITS   _u(0x00000200)
75 #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD_MSB    _u(9)
76 #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD_LSB    _u(9)
77 #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD_ACCESS "RO"
78 // -----------------------------------------------------------------------------
79 // Field       : IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTFROMPERI
80 // Description : output signal from selected peripheral, before register
81 //               override is applied
82 #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTFROMPERI_RESET  _u(0x0)
83 #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTFROMPERI_BITS   _u(0x00000100)
84 #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTFROMPERI_MSB    _u(8)
85 #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTFROMPERI_LSB    _u(8)
86 #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTFROMPERI_ACCESS "RO"
87 // =============================================================================
88 // Register    : IO_QSPI_GPIO_QSPI_SCLK_CTRL
89 // Description : GPIO control including function select and overrides.
90 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OFFSET _u(0x00000004)
91 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_BITS   _u(0x3003331f)
92 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_RESET  _u(0x0000001f)
93 // -----------------------------------------------------------------------------
94 // Field       : IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER
95 //               0x0 -> don't invert the interrupt
96 //               0x1 -> invert the interrupt
97 //               0x2 -> drive interrupt low
98 //               0x3 -> drive interrupt high
99 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_RESET  _u(0x0)
100 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_BITS   _u(0x30000000)
101 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_MSB    _u(29)
102 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_LSB    _u(28)
103 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_ACCESS "RW"
104 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
105 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
106 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_VALUE_LOW _u(0x2)
107 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
108 // -----------------------------------------------------------------------------
109 // Field       : IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER
110 //               0x0 -> don't invert the peri input
111 //               0x1 -> invert the peri input
112 //               0x2 -> drive peri input low
113 //               0x3 -> drive peri input high
114 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_RESET  _u(0x0)
115 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_BITS   _u(0x00030000)
116 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_MSB    _u(17)
117 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_LSB    _u(16)
118 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_ACCESS "RW"
119 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_VALUE_NORMAL _u(0x0)
120 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_VALUE_INVERT _u(0x1)
121 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_VALUE_LOW _u(0x2)
122 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_VALUE_HIGH _u(0x3)
123 // -----------------------------------------------------------------------------
124 // Field       : IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER
125 //               0x0 -> drive output enable from peripheral signal selected by funcsel
126 //               0x1 -> drive output enable from inverse of peripheral signal selected by funcsel
127 //               0x2 -> disable output
128 //               0x3 -> enable output
129 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_RESET  _u(0x0)
130 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_BITS   _u(0x00003000)
131 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_MSB    _u(13)
132 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_LSB    _u(12)
133 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_ACCESS "RW"
134 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
135 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_VALUE_INVERT _u(0x1)
136 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
137 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
138 // -----------------------------------------------------------------------------
139 // Field       : IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER
140 //               0x0 -> drive output from peripheral signal selected by funcsel
141 //               0x1 -> drive output from inverse of peripheral signal selected by funcsel
142 //               0x2 -> drive output low
143 //               0x3 -> drive output high
144 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_RESET  _u(0x0)
145 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_BITS   _u(0x00000300)
146 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_MSB    _u(9)
147 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_LSB    _u(8)
148 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_ACCESS "RW"
149 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
150 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
151 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_VALUE_LOW _u(0x2)
152 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
153 // -----------------------------------------------------------------------------
154 // Field       : IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL
155 // Description : 0-31 -> selects pin function according to the gpio table
156 //               31 == NULL
157 //               0x00 -> xip_sclk
158 //               0x05 -> sio_30
159 //               0x1f -> null
160 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_RESET  _u(0x1f)
161 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_BITS   _u(0x0000001f)
162 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_MSB    _u(4)
163 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_LSB    _u(0)
164 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_ACCESS "RW"
165 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_VALUE_XIP_SCLK _u(0x00)
166 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_VALUE_SIO_30 _u(0x05)
167 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
168 // =============================================================================
169 // Register    : IO_QSPI_GPIO_QSPI_SS_STATUS
170 // Description : GPIO status
171 #define IO_QSPI_GPIO_QSPI_SS_STATUS_OFFSET _u(0x00000008)
172 #define IO_QSPI_GPIO_QSPI_SS_STATUS_BITS   _u(0x050a3300)
173 #define IO_QSPI_GPIO_QSPI_SS_STATUS_RESET  _u(0x00000000)
174 // -----------------------------------------------------------------------------
175 // Field       : IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC
176 // Description : interrupt to processors, after override is applied
177 #define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC_RESET  _u(0x0)
178 #define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC_BITS   _u(0x04000000)
179 #define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC_MSB    _u(26)
180 #define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC_LSB    _u(26)
181 #define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC_ACCESS "RO"
182 // -----------------------------------------------------------------------------
183 // Field       : IO_QSPI_GPIO_QSPI_SS_STATUS_IRQFROMPAD
184 // Description : interrupt from pad before override is applied
185 #define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQFROMPAD_RESET  _u(0x0)
186 #define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQFROMPAD_BITS   _u(0x01000000)
187 #define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQFROMPAD_MSB    _u(24)
188 #define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQFROMPAD_LSB    _u(24)
189 #define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQFROMPAD_ACCESS "RO"
190 // -----------------------------------------------------------------------------
191 // Field       : IO_QSPI_GPIO_QSPI_SS_STATUS_INTOPERI
192 // Description : input signal to peripheral, after override is applied
193 #define IO_QSPI_GPIO_QSPI_SS_STATUS_INTOPERI_RESET  _u(0x0)
194 #define IO_QSPI_GPIO_QSPI_SS_STATUS_INTOPERI_BITS   _u(0x00080000)
195 #define IO_QSPI_GPIO_QSPI_SS_STATUS_INTOPERI_MSB    _u(19)
196 #define IO_QSPI_GPIO_QSPI_SS_STATUS_INTOPERI_LSB    _u(19)
197 #define IO_QSPI_GPIO_QSPI_SS_STATUS_INTOPERI_ACCESS "RO"
198 // -----------------------------------------------------------------------------
199 // Field       : IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD
200 // Description : input signal from pad, before override is applied
201 #define IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD_RESET  _u(0x0)
202 #define IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD_BITS   _u(0x00020000)
203 #define IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD_MSB    _u(17)
204 #define IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD_LSB    _u(17)
205 #define IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD_ACCESS "RO"
206 // -----------------------------------------------------------------------------
207 // Field       : IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD
208 // Description : output enable to pad after register override is applied
209 #define IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD_RESET  _u(0x0)
210 #define IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD_BITS   _u(0x00002000)
211 #define IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD_MSB    _u(13)
212 #define IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD_LSB    _u(13)
213 #define IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD_ACCESS "RO"
214 // -----------------------------------------------------------------------------
215 // Field       : IO_QSPI_GPIO_QSPI_SS_STATUS_OEFROMPERI
216 // Description : output enable from selected peripheral, before register
217 //               override is applied
218 #define IO_QSPI_GPIO_QSPI_SS_STATUS_OEFROMPERI_RESET  _u(0x0)
219 #define IO_QSPI_GPIO_QSPI_SS_STATUS_OEFROMPERI_BITS   _u(0x00001000)
220 #define IO_QSPI_GPIO_QSPI_SS_STATUS_OEFROMPERI_MSB    _u(12)
221 #define IO_QSPI_GPIO_QSPI_SS_STATUS_OEFROMPERI_LSB    _u(12)
222 #define IO_QSPI_GPIO_QSPI_SS_STATUS_OEFROMPERI_ACCESS "RO"
223 // -----------------------------------------------------------------------------
224 // Field       : IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD
225 // Description : output signal to pad after register override is applied
226 #define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD_RESET  _u(0x0)
227 #define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD_BITS   _u(0x00000200)
228 #define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD_MSB    _u(9)
229 #define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD_LSB    _u(9)
230 #define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD_ACCESS "RO"
231 // -----------------------------------------------------------------------------
232 // Field       : IO_QSPI_GPIO_QSPI_SS_STATUS_OUTFROMPERI
233 // Description : output signal from selected peripheral, before register
234 //               override is applied
235 #define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTFROMPERI_RESET  _u(0x0)
236 #define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTFROMPERI_BITS   _u(0x00000100)
237 #define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTFROMPERI_MSB    _u(8)
238 #define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTFROMPERI_LSB    _u(8)
239 #define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTFROMPERI_ACCESS "RO"
240 // =============================================================================
241 // Register    : IO_QSPI_GPIO_QSPI_SS_CTRL
242 // Description : GPIO control including function select and overrides.
243 #define IO_QSPI_GPIO_QSPI_SS_CTRL_OFFSET _u(0x0000000c)
244 #define IO_QSPI_GPIO_QSPI_SS_CTRL_BITS   _u(0x3003331f)
245 #define IO_QSPI_GPIO_QSPI_SS_CTRL_RESET  _u(0x0000001f)
246 // -----------------------------------------------------------------------------
247 // Field       : IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER
248 //               0x0 -> don't invert the interrupt
249 //               0x1 -> invert the interrupt
250 //               0x2 -> drive interrupt low
251 //               0x3 -> drive interrupt high
252 #define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_RESET  _u(0x0)
253 #define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_BITS   _u(0x30000000)
254 #define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_MSB    _u(29)
255 #define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_LSB    _u(28)
256 #define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_ACCESS "RW"
257 #define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
258 #define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
259 #define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_VALUE_LOW _u(0x2)
260 #define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
261 // -----------------------------------------------------------------------------
262 // Field       : IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER
263 //               0x0 -> don't invert the peri input
264 //               0x1 -> invert the peri input
265 //               0x2 -> drive peri input low
266 //               0x3 -> drive peri input high
267 #define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_RESET  _u(0x0)
268 #define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_BITS   _u(0x00030000)
269 #define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_MSB    _u(17)
270 #define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_LSB    _u(16)
271 #define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_ACCESS "RW"
272 #define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_VALUE_NORMAL _u(0x0)
273 #define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_VALUE_INVERT _u(0x1)
274 #define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_VALUE_LOW _u(0x2)
275 #define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_VALUE_HIGH _u(0x3)
276 // -----------------------------------------------------------------------------
277 // Field       : IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER
278 //               0x0 -> drive output enable from peripheral signal selected by funcsel
279 //               0x1 -> drive output enable from inverse of peripheral signal selected by funcsel
280 //               0x2 -> disable output
281 //               0x3 -> enable output
282 #define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_RESET  _u(0x0)
283 #define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_BITS   _u(0x00003000)
284 #define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_MSB    _u(13)
285 #define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_LSB    _u(12)
286 #define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_ACCESS "RW"
287 #define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
288 #define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_VALUE_INVERT _u(0x1)
289 #define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
290 #define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
291 // -----------------------------------------------------------------------------
292 // Field       : IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER
293 //               0x0 -> drive output from peripheral signal selected by funcsel
294 //               0x1 -> drive output from inverse of peripheral signal selected by funcsel
295 //               0x2 -> drive output low
296 //               0x3 -> drive output high
297 #define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_RESET  _u(0x0)
298 #define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_BITS   _u(0x00000300)
299 #define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_MSB    _u(9)
300 #define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_LSB    _u(8)
301 #define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_ACCESS "RW"
302 #define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
303 #define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
304 #define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_LOW _u(0x2)
305 #define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
306 // -----------------------------------------------------------------------------
307 // Field       : IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL
308 // Description : 0-31 -> selects pin function according to the gpio table
309 //               31 == NULL
310 //               0x00 -> xip_ss_n
311 //               0x05 -> sio_31
312 //               0x1f -> null
313 #define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_RESET  _u(0x1f)
314 #define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_BITS   _u(0x0000001f)
315 #define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_MSB    _u(4)
316 #define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_LSB    _u(0)
317 #define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_ACCESS "RW"
318 #define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_VALUE_XIP_SS_N _u(0x00)
319 #define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_VALUE_SIO_31 _u(0x05)
320 #define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
321 // =============================================================================
322 // Register    : IO_QSPI_GPIO_QSPI_SD0_STATUS
323 // Description : GPIO status
324 #define IO_QSPI_GPIO_QSPI_SD0_STATUS_OFFSET _u(0x00000010)
325 #define IO_QSPI_GPIO_QSPI_SD0_STATUS_BITS   _u(0x050a3300)
326 #define IO_QSPI_GPIO_QSPI_SD0_STATUS_RESET  _u(0x00000000)
327 // -----------------------------------------------------------------------------
328 // Field       : IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC
329 // Description : interrupt to processors, after override is applied
330 #define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC_RESET  _u(0x0)
331 #define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC_BITS   _u(0x04000000)
332 #define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC_MSB    _u(26)
333 #define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC_LSB    _u(26)
334 #define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC_ACCESS "RO"
335 // -----------------------------------------------------------------------------
336 // Field       : IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQFROMPAD
337 // Description : interrupt from pad before override is applied
338 #define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQFROMPAD_RESET  _u(0x0)
339 #define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQFROMPAD_BITS   _u(0x01000000)
340 #define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQFROMPAD_MSB    _u(24)
341 #define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQFROMPAD_LSB    _u(24)
342 #define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQFROMPAD_ACCESS "RO"
343 // -----------------------------------------------------------------------------
344 // Field       : IO_QSPI_GPIO_QSPI_SD0_STATUS_INTOPERI
345 // Description : input signal to peripheral, after override is applied
346 #define IO_QSPI_GPIO_QSPI_SD0_STATUS_INTOPERI_RESET  _u(0x0)
347 #define IO_QSPI_GPIO_QSPI_SD0_STATUS_INTOPERI_BITS   _u(0x00080000)
348 #define IO_QSPI_GPIO_QSPI_SD0_STATUS_INTOPERI_MSB    _u(19)
349 #define IO_QSPI_GPIO_QSPI_SD0_STATUS_INTOPERI_LSB    _u(19)
350 #define IO_QSPI_GPIO_QSPI_SD0_STATUS_INTOPERI_ACCESS "RO"
351 // -----------------------------------------------------------------------------
352 // Field       : IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD
353 // Description : input signal from pad, before override is applied
354 #define IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD_RESET  _u(0x0)
355 #define IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD_BITS   _u(0x00020000)
356 #define IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD_MSB    _u(17)
357 #define IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD_LSB    _u(17)
358 #define IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD_ACCESS "RO"
359 // -----------------------------------------------------------------------------
360 // Field       : IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD
361 // Description : output enable to pad after register override is applied
362 #define IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD_RESET  _u(0x0)
363 #define IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD_BITS   _u(0x00002000)
364 #define IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD_MSB    _u(13)
365 #define IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD_LSB    _u(13)
366 #define IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD_ACCESS "RO"
367 // -----------------------------------------------------------------------------
368 // Field       : IO_QSPI_GPIO_QSPI_SD0_STATUS_OEFROMPERI
369 // Description : output enable from selected peripheral, before register
370 //               override is applied
371 #define IO_QSPI_GPIO_QSPI_SD0_STATUS_OEFROMPERI_RESET  _u(0x0)
372 #define IO_QSPI_GPIO_QSPI_SD0_STATUS_OEFROMPERI_BITS   _u(0x00001000)
373 #define IO_QSPI_GPIO_QSPI_SD0_STATUS_OEFROMPERI_MSB    _u(12)
374 #define IO_QSPI_GPIO_QSPI_SD0_STATUS_OEFROMPERI_LSB    _u(12)
375 #define IO_QSPI_GPIO_QSPI_SD0_STATUS_OEFROMPERI_ACCESS "RO"
376 // -----------------------------------------------------------------------------
377 // Field       : IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD
378 // Description : output signal to pad after register override is applied
379 #define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD_RESET  _u(0x0)
380 #define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD_BITS   _u(0x00000200)
381 #define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD_MSB    _u(9)
382 #define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD_LSB    _u(9)
383 #define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD_ACCESS "RO"
384 // -----------------------------------------------------------------------------
385 // Field       : IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTFROMPERI
386 // Description : output signal from selected peripheral, before register
387 //               override is applied
388 #define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTFROMPERI_RESET  _u(0x0)
389 #define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTFROMPERI_BITS   _u(0x00000100)
390 #define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTFROMPERI_MSB    _u(8)
391 #define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTFROMPERI_LSB    _u(8)
392 #define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTFROMPERI_ACCESS "RO"
393 // =============================================================================
394 // Register    : IO_QSPI_GPIO_QSPI_SD0_CTRL
395 // Description : GPIO control including function select and overrides.
396 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_OFFSET _u(0x00000014)
397 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_BITS   _u(0x3003331f)
398 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_RESET  _u(0x0000001f)
399 // -----------------------------------------------------------------------------
400 // Field       : IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER
401 //               0x0 -> don't invert the interrupt
402 //               0x1 -> invert the interrupt
403 //               0x2 -> drive interrupt low
404 //               0x3 -> drive interrupt high
405 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_RESET  _u(0x0)
406 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_BITS   _u(0x30000000)
407 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_MSB    _u(29)
408 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_LSB    _u(28)
409 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_ACCESS "RW"
410 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
411 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
412 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_VALUE_LOW _u(0x2)
413 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
414 // -----------------------------------------------------------------------------
415 // Field       : IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER
416 //               0x0 -> don't invert the peri input
417 //               0x1 -> invert the peri input
418 //               0x2 -> drive peri input low
419 //               0x3 -> drive peri input high
420 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_RESET  _u(0x0)
421 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_BITS   _u(0x00030000)
422 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_MSB    _u(17)
423 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_LSB    _u(16)
424 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_ACCESS "RW"
425 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_VALUE_NORMAL _u(0x0)
426 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_VALUE_INVERT _u(0x1)
427 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_VALUE_LOW _u(0x2)
428 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_VALUE_HIGH _u(0x3)
429 // -----------------------------------------------------------------------------
430 // Field       : IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER
431 //               0x0 -> drive output enable from peripheral signal selected by funcsel
432 //               0x1 -> drive output enable from inverse of peripheral signal selected by funcsel
433 //               0x2 -> disable output
434 //               0x3 -> enable output
435 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_RESET  _u(0x0)
436 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_BITS   _u(0x00003000)
437 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_MSB    _u(13)
438 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_LSB    _u(12)
439 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_ACCESS "RW"
440 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
441 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_VALUE_INVERT _u(0x1)
442 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
443 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
444 // -----------------------------------------------------------------------------
445 // Field       : IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER
446 //               0x0 -> drive output from peripheral signal selected by funcsel
447 //               0x1 -> drive output from inverse of peripheral signal selected by funcsel
448 //               0x2 -> drive output low
449 //               0x3 -> drive output high
450 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_RESET  _u(0x0)
451 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_BITS   _u(0x00000300)
452 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_MSB    _u(9)
453 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_LSB    _u(8)
454 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_ACCESS "RW"
455 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
456 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
457 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_VALUE_LOW _u(0x2)
458 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
459 // -----------------------------------------------------------------------------
460 // Field       : IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL
461 // Description : 0-31 -> selects pin function according to the gpio table
462 //               31 == NULL
463 //               0x00 -> xip_sd0
464 //               0x05 -> sio_32
465 //               0x1f -> null
466 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_RESET  _u(0x1f)
467 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_BITS   _u(0x0000001f)
468 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_MSB    _u(4)
469 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_LSB    _u(0)
470 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_ACCESS "RW"
471 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_VALUE_XIP_SD0 _u(0x00)
472 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_VALUE_SIO_32 _u(0x05)
473 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
474 // =============================================================================
475 // Register    : IO_QSPI_GPIO_QSPI_SD1_STATUS
476 // Description : GPIO status
477 #define IO_QSPI_GPIO_QSPI_SD1_STATUS_OFFSET _u(0x00000018)
478 #define IO_QSPI_GPIO_QSPI_SD1_STATUS_BITS   _u(0x050a3300)
479 #define IO_QSPI_GPIO_QSPI_SD1_STATUS_RESET  _u(0x00000000)
480 // -----------------------------------------------------------------------------
481 // Field       : IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC
482 // Description : interrupt to processors, after override is applied
483 #define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC_RESET  _u(0x0)
484 #define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC_BITS   _u(0x04000000)
485 #define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC_MSB    _u(26)
486 #define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC_LSB    _u(26)
487 #define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC_ACCESS "RO"
488 // -----------------------------------------------------------------------------
489 // Field       : IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQFROMPAD
490 // Description : interrupt from pad before override is applied
491 #define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQFROMPAD_RESET  _u(0x0)
492 #define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQFROMPAD_BITS   _u(0x01000000)
493 #define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQFROMPAD_MSB    _u(24)
494 #define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQFROMPAD_LSB    _u(24)
495 #define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQFROMPAD_ACCESS "RO"
496 // -----------------------------------------------------------------------------
497 // Field       : IO_QSPI_GPIO_QSPI_SD1_STATUS_INTOPERI
498 // Description : input signal to peripheral, after override is applied
499 #define IO_QSPI_GPIO_QSPI_SD1_STATUS_INTOPERI_RESET  _u(0x0)
500 #define IO_QSPI_GPIO_QSPI_SD1_STATUS_INTOPERI_BITS   _u(0x00080000)
501 #define IO_QSPI_GPIO_QSPI_SD1_STATUS_INTOPERI_MSB    _u(19)
502 #define IO_QSPI_GPIO_QSPI_SD1_STATUS_INTOPERI_LSB    _u(19)
503 #define IO_QSPI_GPIO_QSPI_SD1_STATUS_INTOPERI_ACCESS "RO"
504 // -----------------------------------------------------------------------------
505 // Field       : IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD
506 // Description : input signal from pad, before override is applied
507 #define IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD_RESET  _u(0x0)
508 #define IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD_BITS   _u(0x00020000)
509 #define IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD_MSB    _u(17)
510 #define IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD_LSB    _u(17)
511 #define IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD_ACCESS "RO"
512 // -----------------------------------------------------------------------------
513 // Field       : IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD
514 // Description : output enable to pad after register override is applied
515 #define IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD_RESET  _u(0x0)
516 #define IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD_BITS   _u(0x00002000)
517 #define IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD_MSB    _u(13)
518 #define IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD_LSB    _u(13)
519 #define IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD_ACCESS "RO"
520 // -----------------------------------------------------------------------------
521 // Field       : IO_QSPI_GPIO_QSPI_SD1_STATUS_OEFROMPERI
522 // Description : output enable from selected peripheral, before register
523 //               override is applied
524 #define IO_QSPI_GPIO_QSPI_SD1_STATUS_OEFROMPERI_RESET  _u(0x0)
525 #define IO_QSPI_GPIO_QSPI_SD1_STATUS_OEFROMPERI_BITS   _u(0x00001000)
526 #define IO_QSPI_GPIO_QSPI_SD1_STATUS_OEFROMPERI_MSB    _u(12)
527 #define IO_QSPI_GPIO_QSPI_SD1_STATUS_OEFROMPERI_LSB    _u(12)
528 #define IO_QSPI_GPIO_QSPI_SD1_STATUS_OEFROMPERI_ACCESS "RO"
529 // -----------------------------------------------------------------------------
530 // Field       : IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD
531 // Description : output signal to pad after register override is applied
532 #define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD_RESET  _u(0x0)
533 #define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD_BITS   _u(0x00000200)
534 #define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD_MSB    _u(9)
535 #define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD_LSB    _u(9)
536 #define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD_ACCESS "RO"
537 // -----------------------------------------------------------------------------
538 // Field       : IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTFROMPERI
539 // Description : output signal from selected peripheral, before register
540 //               override is applied
541 #define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTFROMPERI_RESET  _u(0x0)
542 #define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTFROMPERI_BITS   _u(0x00000100)
543 #define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTFROMPERI_MSB    _u(8)
544 #define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTFROMPERI_LSB    _u(8)
545 #define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTFROMPERI_ACCESS "RO"
546 // =============================================================================
547 // Register    : IO_QSPI_GPIO_QSPI_SD1_CTRL
548 // Description : GPIO control including function select and overrides.
549 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_OFFSET _u(0x0000001c)
550 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_BITS   _u(0x3003331f)
551 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_RESET  _u(0x0000001f)
552 // -----------------------------------------------------------------------------
553 // Field       : IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER
554 //               0x0 -> don't invert the interrupt
555 //               0x1 -> invert the interrupt
556 //               0x2 -> drive interrupt low
557 //               0x3 -> drive interrupt high
558 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_RESET  _u(0x0)
559 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_BITS   _u(0x30000000)
560 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_MSB    _u(29)
561 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_LSB    _u(28)
562 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_ACCESS "RW"
563 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
564 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
565 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_VALUE_LOW _u(0x2)
566 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
567 // -----------------------------------------------------------------------------
568 // Field       : IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER
569 //               0x0 -> don't invert the peri input
570 //               0x1 -> invert the peri input
571 //               0x2 -> drive peri input low
572 //               0x3 -> drive peri input high
573 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_RESET  _u(0x0)
574 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_BITS   _u(0x00030000)
575 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_MSB    _u(17)
576 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_LSB    _u(16)
577 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_ACCESS "RW"
578 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_VALUE_NORMAL _u(0x0)
579 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_VALUE_INVERT _u(0x1)
580 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_VALUE_LOW _u(0x2)
581 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_VALUE_HIGH _u(0x3)
582 // -----------------------------------------------------------------------------
583 // Field       : IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER
584 //               0x0 -> drive output enable from peripheral signal selected by funcsel
585 //               0x1 -> drive output enable from inverse of peripheral signal selected by funcsel
586 //               0x2 -> disable output
587 //               0x3 -> enable output
588 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_RESET  _u(0x0)
589 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_BITS   _u(0x00003000)
590 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_MSB    _u(13)
591 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_LSB    _u(12)
592 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_ACCESS "RW"
593 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
594 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_VALUE_INVERT _u(0x1)
595 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
596 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
597 // -----------------------------------------------------------------------------
598 // Field       : IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER
599 //               0x0 -> drive output from peripheral signal selected by funcsel
600 //               0x1 -> drive output from inverse of peripheral signal selected by funcsel
601 //               0x2 -> drive output low
602 //               0x3 -> drive output high
603 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_RESET  _u(0x0)
604 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_BITS   _u(0x00000300)
605 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_MSB    _u(9)
606 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_LSB    _u(8)
607 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_ACCESS "RW"
608 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
609 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
610 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_VALUE_LOW _u(0x2)
611 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
612 // -----------------------------------------------------------------------------
613 // Field       : IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL
614 // Description : 0-31 -> selects pin function according to the gpio table
615 //               31 == NULL
616 //               0x00 -> xip_sd1
617 //               0x05 -> sio_33
618 //               0x1f -> null
619 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_RESET  _u(0x1f)
620 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_BITS   _u(0x0000001f)
621 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_MSB    _u(4)
622 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_LSB    _u(0)
623 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_ACCESS "RW"
624 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_VALUE_XIP_SD1 _u(0x00)
625 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_VALUE_SIO_33 _u(0x05)
626 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
627 // =============================================================================
628 // Register    : IO_QSPI_GPIO_QSPI_SD2_STATUS
629 // Description : GPIO status
630 #define IO_QSPI_GPIO_QSPI_SD2_STATUS_OFFSET _u(0x00000020)
631 #define IO_QSPI_GPIO_QSPI_SD2_STATUS_BITS   _u(0x050a3300)
632 #define IO_QSPI_GPIO_QSPI_SD2_STATUS_RESET  _u(0x00000000)
633 // -----------------------------------------------------------------------------
634 // Field       : IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC
635 // Description : interrupt to processors, after override is applied
636 #define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC_RESET  _u(0x0)
637 #define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC_BITS   _u(0x04000000)
638 #define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC_MSB    _u(26)
639 #define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC_LSB    _u(26)
640 #define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC_ACCESS "RO"
641 // -----------------------------------------------------------------------------
642 // Field       : IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQFROMPAD
643 // Description : interrupt from pad before override is applied
644 #define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQFROMPAD_RESET  _u(0x0)
645 #define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQFROMPAD_BITS   _u(0x01000000)
646 #define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQFROMPAD_MSB    _u(24)
647 #define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQFROMPAD_LSB    _u(24)
648 #define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQFROMPAD_ACCESS "RO"
649 // -----------------------------------------------------------------------------
650 // Field       : IO_QSPI_GPIO_QSPI_SD2_STATUS_INTOPERI
651 // Description : input signal to peripheral, after override is applied
652 #define IO_QSPI_GPIO_QSPI_SD2_STATUS_INTOPERI_RESET  _u(0x0)
653 #define IO_QSPI_GPIO_QSPI_SD2_STATUS_INTOPERI_BITS   _u(0x00080000)
654 #define IO_QSPI_GPIO_QSPI_SD2_STATUS_INTOPERI_MSB    _u(19)
655 #define IO_QSPI_GPIO_QSPI_SD2_STATUS_INTOPERI_LSB    _u(19)
656 #define IO_QSPI_GPIO_QSPI_SD2_STATUS_INTOPERI_ACCESS "RO"
657 // -----------------------------------------------------------------------------
658 // Field       : IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD
659 // Description : input signal from pad, before override is applied
660 #define IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD_RESET  _u(0x0)
661 #define IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD_BITS   _u(0x00020000)
662 #define IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD_MSB    _u(17)
663 #define IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD_LSB    _u(17)
664 #define IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD_ACCESS "RO"
665 // -----------------------------------------------------------------------------
666 // Field       : IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD
667 // Description : output enable to pad after register override is applied
668 #define IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD_RESET  _u(0x0)
669 #define IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD_BITS   _u(0x00002000)
670 #define IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD_MSB    _u(13)
671 #define IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD_LSB    _u(13)
672 #define IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD_ACCESS "RO"
673 // -----------------------------------------------------------------------------
674 // Field       : IO_QSPI_GPIO_QSPI_SD2_STATUS_OEFROMPERI
675 // Description : output enable from selected peripheral, before register
676 //               override is applied
677 #define IO_QSPI_GPIO_QSPI_SD2_STATUS_OEFROMPERI_RESET  _u(0x0)
678 #define IO_QSPI_GPIO_QSPI_SD2_STATUS_OEFROMPERI_BITS   _u(0x00001000)
679 #define IO_QSPI_GPIO_QSPI_SD2_STATUS_OEFROMPERI_MSB    _u(12)
680 #define IO_QSPI_GPIO_QSPI_SD2_STATUS_OEFROMPERI_LSB    _u(12)
681 #define IO_QSPI_GPIO_QSPI_SD2_STATUS_OEFROMPERI_ACCESS "RO"
682 // -----------------------------------------------------------------------------
683 // Field       : IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD
684 // Description : output signal to pad after register override is applied
685 #define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD_RESET  _u(0x0)
686 #define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD_BITS   _u(0x00000200)
687 #define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD_MSB    _u(9)
688 #define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD_LSB    _u(9)
689 #define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD_ACCESS "RO"
690 // -----------------------------------------------------------------------------
691 // Field       : IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTFROMPERI
692 // Description : output signal from selected peripheral, before register
693 //               override is applied
694 #define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTFROMPERI_RESET  _u(0x0)
695 #define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTFROMPERI_BITS   _u(0x00000100)
696 #define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTFROMPERI_MSB    _u(8)
697 #define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTFROMPERI_LSB    _u(8)
698 #define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTFROMPERI_ACCESS "RO"
699 // =============================================================================
700 // Register    : IO_QSPI_GPIO_QSPI_SD2_CTRL
701 // Description : GPIO control including function select and overrides.
702 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_OFFSET _u(0x00000024)
703 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_BITS   _u(0x3003331f)
704 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_RESET  _u(0x0000001f)
705 // -----------------------------------------------------------------------------
706 // Field       : IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER
707 //               0x0 -> don't invert the interrupt
708 //               0x1 -> invert the interrupt
709 //               0x2 -> drive interrupt low
710 //               0x3 -> drive interrupt high
711 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_RESET  _u(0x0)
712 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_BITS   _u(0x30000000)
713 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_MSB    _u(29)
714 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_LSB    _u(28)
715 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_ACCESS "RW"
716 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
717 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
718 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_VALUE_LOW _u(0x2)
719 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
720 // -----------------------------------------------------------------------------
721 // Field       : IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER
722 //               0x0 -> don't invert the peri input
723 //               0x1 -> invert the peri input
724 //               0x2 -> drive peri input low
725 //               0x3 -> drive peri input high
726 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_RESET  _u(0x0)
727 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_BITS   _u(0x00030000)
728 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_MSB    _u(17)
729 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_LSB    _u(16)
730 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_ACCESS "RW"
731 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_VALUE_NORMAL _u(0x0)
732 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_VALUE_INVERT _u(0x1)
733 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_VALUE_LOW _u(0x2)
734 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_VALUE_HIGH _u(0x3)
735 // -----------------------------------------------------------------------------
736 // Field       : IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER
737 //               0x0 -> drive output enable from peripheral signal selected by funcsel
738 //               0x1 -> drive output enable from inverse of peripheral signal selected by funcsel
739 //               0x2 -> disable output
740 //               0x3 -> enable output
741 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_RESET  _u(0x0)
742 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_BITS   _u(0x00003000)
743 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_MSB    _u(13)
744 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_LSB    _u(12)
745 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_ACCESS "RW"
746 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
747 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_VALUE_INVERT _u(0x1)
748 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
749 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
750 // -----------------------------------------------------------------------------
751 // Field       : IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER
752 //               0x0 -> drive output from peripheral signal selected by funcsel
753 //               0x1 -> drive output from inverse of peripheral signal selected by funcsel
754 //               0x2 -> drive output low
755 //               0x3 -> drive output high
756 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_RESET  _u(0x0)
757 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_BITS   _u(0x00000300)
758 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_MSB    _u(9)
759 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_LSB    _u(8)
760 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_ACCESS "RW"
761 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
762 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
763 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_VALUE_LOW _u(0x2)
764 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
765 // -----------------------------------------------------------------------------
766 // Field       : IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL
767 // Description : 0-31 -> selects pin function according to the gpio table
768 //               31 == NULL
769 //               0x00 -> xip_sd2
770 //               0x05 -> sio_34
771 //               0x1f -> null
772 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_RESET  _u(0x1f)
773 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_BITS   _u(0x0000001f)
774 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_MSB    _u(4)
775 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_LSB    _u(0)
776 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_ACCESS "RW"
777 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_VALUE_XIP_SD2 _u(0x00)
778 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_VALUE_SIO_34 _u(0x05)
779 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
780 // =============================================================================
781 // Register    : IO_QSPI_GPIO_QSPI_SD3_STATUS
782 // Description : GPIO status
783 #define IO_QSPI_GPIO_QSPI_SD3_STATUS_OFFSET _u(0x00000028)
784 #define IO_QSPI_GPIO_QSPI_SD3_STATUS_BITS   _u(0x050a3300)
785 #define IO_QSPI_GPIO_QSPI_SD3_STATUS_RESET  _u(0x00000000)
786 // -----------------------------------------------------------------------------
787 // Field       : IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC
788 // Description : interrupt to processors, after override is applied
789 #define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC_RESET  _u(0x0)
790 #define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC_BITS   _u(0x04000000)
791 #define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC_MSB    _u(26)
792 #define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC_LSB    _u(26)
793 #define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC_ACCESS "RO"
794 // -----------------------------------------------------------------------------
795 // Field       : IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQFROMPAD
796 // Description : interrupt from pad before override is applied
797 #define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQFROMPAD_RESET  _u(0x0)
798 #define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQFROMPAD_BITS   _u(0x01000000)
799 #define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQFROMPAD_MSB    _u(24)
800 #define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQFROMPAD_LSB    _u(24)
801 #define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQFROMPAD_ACCESS "RO"
802 // -----------------------------------------------------------------------------
803 // Field       : IO_QSPI_GPIO_QSPI_SD3_STATUS_INTOPERI
804 // Description : input signal to peripheral, after override is applied
805 #define IO_QSPI_GPIO_QSPI_SD3_STATUS_INTOPERI_RESET  _u(0x0)
806 #define IO_QSPI_GPIO_QSPI_SD3_STATUS_INTOPERI_BITS   _u(0x00080000)
807 #define IO_QSPI_GPIO_QSPI_SD3_STATUS_INTOPERI_MSB    _u(19)
808 #define IO_QSPI_GPIO_QSPI_SD3_STATUS_INTOPERI_LSB    _u(19)
809 #define IO_QSPI_GPIO_QSPI_SD3_STATUS_INTOPERI_ACCESS "RO"
810 // -----------------------------------------------------------------------------
811 // Field       : IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD
812 // Description : input signal from pad, before override is applied
813 #define IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD_RESET  _u(0x0)
814 #define IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD_BITS   _u(0x00020000)
815 #define IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD_MSB    _u(17)
816 #define IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD_LSB    _u(17)
817 #define IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD_ACCESS "RO"
818 // -----------------------------------------------------------------------------
819 // Field       : IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD
820 // Description : output enable to pad after register override is applied
821 #define IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD_RESET  _u(0x0)
822 #define IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD_BITS   _u(0x00002000)
823 #define IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD_MSB    _u(13)
824 #define IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD_LSB    _u(13)
825 #define IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD_ACCESS "RO"
826 // -----------------------------------------------------------------------------
827 // Field       : IO_QSPI_GPIO_QSPI_SD3_STATUS_OEFROMPERI
828 // Description : output enable from selected peripheral, before register
829 //               override is applied
830 #define IO_QSPI_GPIO_QSPI_SD3_STATUS_OEFROMPERI_RESET  _u(0x0)
831 #define IO_QSPI_GPIO_QSPI_SD3_STATUS_OEFROMPERI_BITS   _u(0x00001000)
832 #define IO_QSPI_GPIO_QSPI_SD3_STATUS_OEFROMPERI_MSB    _u(12)
833 #define IO_QSPI_GPIO_QSPI_SD3_STATUS_OEFROMPERI_LSB    _u(12)
834 #define IO_QSPI_GPIO_QSPI_SD3_STATUS_OEFROMPERI_ACCESS "RO"
835 // -----------------------------------------------------------------------------
836 // Field       : IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD
837 // Description : output signal to pad after register override is applied
838 #define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD_RESET  _u(0x0)
839 #define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD_BITS   _u(0x00000200)
840 #define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD_MSB    _u(9)
841 #define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD_LSB    _u(9)
842 #define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD_ACCESS "RO"
843 // -----------------------------------------------------------------------------
844 // Field       : IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTFROMPERI
845 // Description : output signal from selected peripheral, before register
846 //               override is applied
847 #define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTFROMPERI_RESET  _u(0x0)
848 #define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTFROMPERI_BITS   _u(0x00000100)
849 #define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTFROMPERI_MSB    _u(8)
850 #define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTFROMPERI_LSB    _u(8)
851 #define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTFROMPERI_ACCESS "RO"
852 // =============================================================================
853 // Register    : IO_QSPI_GPIO_QSPI_SD3_CTRL
854 // Description : GPIO control including function select and overrides.
855 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_OFFSET _u(0x0000002c)
856 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_BITS   _u(0x3003331f)
857 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_RESET  _u(0x0000001f)
858 // -----------------------------------------------------------------------------
859 // Field       : IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER
860 //               0x0 -> don't invert the interrupt
861 //               0x1 -> invert the interrupt
862 //               0x2 -> drive interrupt low
863 //               0x3 -> drive interrupt high
864 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_RESET  _u(0x0)
865 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_BITS   _u(0x30000000)
866 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_MSB    _u(29)
867 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_LSB    _u(28)
868 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_ACCESS "RW"
869 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
870 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
871 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_VALUE_LOW _u(0x2)
872 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
873 // -----------------------------------------------------------------------------
874 // Field       : IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER
875 //               0x0 -> don't invert the peri input
876 //               0x1 -> invert the peri input
877 //               0x2 -> drive peri input low
878 //               0x3 -> drive peri input high
879 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_RESET  _u(0x0)
880 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_BITS   _u(0x00030000)
881 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_MSB    _u(17)
882 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_LSB    _u(16)
883 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_ACCESS "RW"
884 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_VALUE_NORMAL _u(0x0)
885 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_VALUE_INVERT _u(0x1)
886 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_VALUE_LOW _u(0x2)
887 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_VALUE_HIGH _u(0x3)
888 // -----------------------------------------------------------------------------
889 // Field       : IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER
890 //               0x0 -> drive output enable from peripheral signal selected by funcsel
891 //               0x1 -> drive output enable from inverse of peripheral signal selected by funcsel
892 //               0x2 -> disable output
893 //               0x3 -> enable output
894 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_RESET  _u(0x0)
895 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_BITS   _u(0x00003000)
896 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_MSB    _u(13)
897 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_LSB    _u(12)
898 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_ACCESS "RW"
899 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
900 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_VALUE_INVERT _u(0x1)
901 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
902 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
903 // -----------------------------------------------------------------------------
904 // Field       : IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER
905 //               0x0 -> drive output from peripheral signal selected by funcsel
906 //               0x1 -> drive output from inverse of peripheral signal selected by funcsel
907 //               0x2 -> drive output low
908 //               0x3 -> drive output high
909 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_RESET  _u(0x0)
910 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_BITS   _u(0x00000300)
911 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_MSB    _u(9)
912 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_LSB    _u(8)
913 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_ACCESS "RW"
914 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
915 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
916 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_VALUE_LOW _u(0x2)
917 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
918 // -----------------------------------------------------------------------------
919 // Field       : IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL
920 // Description : 0-31 -> selects pin function according to the gpio table
921 //               31 == NULL
922 //               0x00 -> xip_sd3
923 //               0x05 -> sio_35
924 //               0x1f -> null
925 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_RESET  _u(0x1f)
926 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_BITS   _u(0x0000001f)
927 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_MSB    _u(4)
928 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_LSB    _u(0)
929 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_ACCESS "RW"
930 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_VALUE_XIP_SD3 _u(0x00)
931 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_VALUE_SIO_35 _u(0x05)
932 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
933 // =============================================================================
934 // Register    : IO_QSPI_INTR
935 // Description : Raw Interrupts
936 #define IO_QSPI_INTR_OFFSET _u(0x00000030)
937 #define IO_QSPI_INTR_BITS   _u(0x00ffffff)
938 #define IO_QSPI_INTR_RESET  _u(0x00000000)
939 // -----------------------------------------------------------------------------
940 // Field       : IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH
941 #define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_RESET  _u(0x0)
942 #define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_BITS   _u(0x00800000)
943 #define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_MSB    _u(23)
944 #define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_LSB    _u(23)
945 #define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "WC"
946 // -----------------------------------------------------------------------------
947 // Field       : IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW
948 #define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_RESET  _u(0x0)
949 #define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_BITS   _u(0x00400000)
950 #define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_MSB    _u(22)
951 #define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_LSB    _u(22)
952 #define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "WC"
953 // -----------------------------------------------------------------------------
954 // Field       : IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH
955 #define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_RESET  _u(0x0)
956 #define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_BITS   _u(0x00200000)
957 #define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_MSB    _u(21)
958 #define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_LSB    _u(21)
959 #define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RO"
960 // -----------------------------------------------------------------------------
961 // Field       : IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW
962 #define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_RESET  _u(0x0)
963 #define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_BITS   _u(0x00100000)
964 #define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_MSB    _u(20)
965 #define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_LSB    _u(20)
966 #define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RO"
967 // -----------------------------------------------------------------------------
968 // Field       : IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH
969 #define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_RESET  _u(0x0)
970 #define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_BITS   _u(0x00080000)
971 #define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_MSB    _u(19)
972 #define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_LSB    _u(19)
973 #define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "WC"
974 // -----------------------------------------------------------------------------
975 // Field       : IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW
976 #define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_RESET  _u(0x0)
977 #define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_BITS   _u(0x00040000)
978 #define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_MSB    _u(18)
979 #define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_LSB    _u(18)
980 #define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "WC"
981 // -----------------------------------------------------------------------------
982 // Field       : IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH
983 #define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_RESET  _u(0x0)
984 #define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_BITS   _u(0x00020000)
985 #define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_MSB    _u(17)
986 #define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_LSB    _u(17)
987 #define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RO"
988 // -----------------------------------------------------------------------------
989 // Field       : IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW
990 #define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_RESET  _u(0x0)
991 #define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_BITS   _u(0x00010000)
992 #define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_MSB    _u(16)
993 #define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_LSB    _u(16)
994 #define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RO"
995 // -----------------------------------------------------------------------------
996 // Field       : IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH
997 #define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_RESET  _u(0x0)
998 #define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_BITS   _u(0x00008000)
999 #define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_MSB    _u(15)
1000 #define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_LSB    _u(15)
1001 #define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "WC"
1002 // -----------------------------------------------------------------------------
1003 // Field       : IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW
1004 #define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_RESET  _u(0x0)
1005 #define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_BITS   _u(0x00004000)
1006 #define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_MSB    _u(14)
1007 #define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_LSB    _u(14)
1008 #define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "WC"
1009 // -----------------------------------------------------------------------------
1010 // Field       : IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH
1011 #define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_RESET  _u(0x0)
1012 #define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_BITS   _u(0x00002000)
1013 #define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_MSB    _u(13)
1014 #define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_LSB    _u(13)
1015 #define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RO"
1016 // -----------------------------------------------------------------------------
1017 // Field       : IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW
1018 #define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_RESET  _u(0x0)
1019 #define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_BITS   _u(0x00001000)
1020 #define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_MSB    _u(12)
1021 #define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_LSB    _u(12)
1022 #define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RO"
1023 // -----------------------------------------------------------------------------
1024 // Field       : IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH
1025 #define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_RESET  _u(0x0)
1026 #define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_BITS   _u(0x00000800)
1027 #define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_MSB    _u(11)
1028 #define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_LSB    _u(11)
1029 #define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "WC"
1030 // -----------------------------------------------------------------------------
1031 // Field       : IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW
1032 #define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_RESET  _u(0x0)
1033 #define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_BITS   _u(0x00000400)
1034 #define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_MSB    _u(10)
1035 #define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_LSB    _u(10)
1036 #define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "WC"
1037 // -----------------------------------------------------------------------------
1038 // Field       : IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH
1039 #define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_RESET  _u(0x0)
1040 #define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_BITS   _u(0x00000200)
1041 #define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_MSB    _u(9)
1042 #define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_LSB    _u(9)
1043 #define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RO"
1044 // -----------------------------------------------------------------------------
1045 // Field       : IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW
1046 #define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_RESET  _u(0x0)
1047 #define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_BITS   _u(0x00000100)
1048 #define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_MSB    _u(8)
1049 #define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_LSB    _u(8)
1050 #define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RO"
1051 // -----------------------------------------------------------------------------
1052 // Field       : IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH
1053 #define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_RESET  _u(0x0)
1054 #define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_BITS   _u(0x00000080)
1055 #define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_MSB    _u(7)
1056 #define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_LSB    _u(7)
1057 #define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "WC"
1058 // -----------------------------------------------------------------------------
1059 // Field       : IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW
1060 #define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_RESET  _u(0x0)
1061 #define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_BITS   _u(0x00000040)
1062 #define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_MSB    _u(6)
1063 #define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_LSB    _u(6)
1064 #define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_ACCESS "WC"
1065 // -----------------------------------------------------------------------------
1066 // Field       : IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH
1067 #define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_RESET  _u(0x0)
1068 #define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_BITS   _u(0x00000020)
1069 #define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_MSB    _u(5)
1070 #define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_LSB    _u(5)
1071 #define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RO"
1072 // -----------------------------------------------------------------------------
1073 // Field       : IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW
1074 #define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_RESET  _u(0x0)
1075 #define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_BITS   _u(0x00000010)
1076 #define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_MSB    _u(4)
1077 #define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_LSB    _u(4)
1078 #define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RO"
1079 // -----------------------------------------------------------------------------
1080 // Field       : IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH
1081 #define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_RESET  _u(0x0)
1082 #define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_BITS   _u(0x00000008)
1083 #define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_MSB    _u(3)
1084 #define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_LSB    _u(3)
1085 #define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "WC"
1086 // -----------------------------------------------------------------------------
1087 // Field       : IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW
1088 #define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_RESET  _u(0x0)
1089 #define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_BITS   _u(0x00000004)
1090 #define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_MSB    _u(2)
1091 #define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_LSB    _u(2)
1092 #define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "WC"
1093 // -----------------------------------------------------------------------------
1094 // Field       : IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH
1095 #define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET  _u(0x0)
1096 #define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS   _u(0x00000002)
1097 #define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB    _u(1)
1098 #define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB    _u(1)
1099 #define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RO"
1100 // -----------------------------------------------------------------------------
1101 // Field       : IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW
1102 #define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_RESET  _u(0x0)
1103 #define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_BITS   _u(0x00000001)
1104 #define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_MSB    _u(0)
1105 #define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_LSB    _u(0)
1106 #define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RO"
1107 // =============================================================================
1108 // Register    : IO_QSPI_PROC0_INTE
1109 // Description : Interrupt Enable for proc0
1110 #define IO_QSPI_PROC0_INTE_OFFSET _u(0x00000034)
1111 #define IO_QSPI_PROC0_INTE_BITS   _u(0x00ffffff)
1112 #define IO_QSPI_PROC0_INTE_RESET  _u(0x00000000)
1113 // -----------------------------------------------------------------------------
1114 // Field       : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH
1115 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_RESET  _u(0x0)
1116 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_BITS   _u(0x00800000)
1117 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_MSB    _u(23)
1118 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_LSB    _u(23)
1119 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW"
1120 // -----------------------------------------------------------------------------
1121 // Field       : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW
1122 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_RESET  _u(0x0)
1123 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_BITS   _u(0x00400000)
1124 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_MSB    _u(22)
1125 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_LSB    _u(22)
1126 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW"
1127 // -----------------------------------------------------------------------------
1128 // Field       : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH
1129 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_RESET  _u(0x0)
1130 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_BITS   _u(0x00200000)
1131 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_MSB    _u(21)
1132 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_LSB    _u(21)
1133 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW"
1134 // -----------------------------------------------------------------------------
1135 // Field       : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW
1136 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_RESET  _u(0x0)
1137 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_BITS   _u(0x00100000)
1138 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_MSB    _u(20)
1139 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_LSB    _u(20)
1140 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW"
1141 // -----------------------------------------------------------------------------
1142 // Field       : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH
1143 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_RESET  _u(0x0)
1144 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_BITS   _u(0x00080000)
1145 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_MSB    _u(19)
1146 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_LSB    _u(19)
1147 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW"
1148 // -----------------------------------------------------------------------------
1149 // Field       : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW
1150 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_RESET  _u(0x0)
1151 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_BITS   _u(0x00040000)
1152 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_MSB    _u(18)
1153 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_LSB    _u(18)
1154 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW"
1155 // -----------------------------------------------------------------------------
1156 // Field       : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH
1157 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_RESET  _u(0x0)
1158 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_BITS   _u(0x00020000)
1159 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_MSB    _u(17)
1160 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_LSB    _u(17)
1161 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW"
1162 // -----------------------------------------------------------------------------
1163 // Field       : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW
1164 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_RESET  _u(0x0)
1165 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_BITS   _u(0x00010000)
1166 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_MSB    _u(16)
1167 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_LSB    _u(16)
1168 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW"
1169 // -----------------------------------------------------------------------------
1170 // Field       : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH
1171 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_RESET  _u(0x0)
1172 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_BITS   _u(0x00008000)
1173 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_MSB    _u(15)
1174 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_LSB    _u(15)
1175 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW"
1176 // -----------------------------------------------------------------------------
1177 // Field       : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW
1178 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_RESET  _u(0x0)
1179 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_BITS   _u(0x00004000)
1180 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_MSB    _u(14)
1181 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_LSB    _u(14)
1182 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW"
1183 // -----------------------------------------------------------------------------
1184 // Field       : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH
1185 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_RESET  _u(0x0)
1186 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_BITS   _u(0x00002000)
1187 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_MSB    _u(13)
1188 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_LSB    _u(13)
1189 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW"
1190 // -----------------------------------------------------------------------------
1191 // Field       : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW
1192 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_RESET  _u(0x0)
1193 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_BITS   _u(0x00001000)
1194 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_MSB    _u(12)
1195 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_LSB    _u(12)
1196 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW"
1197 // -----------------------------------------------------------------------------
1198 // Field       : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH
1199 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_RESET  _u(0x0)
1200 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_BITS   _u(0x00000800)
1201 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_MSB    _u(11)
1202 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_LSB    _u(11)
1203 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW"
1204 // -----------------------------------------------------------------------------
1205 // Field       : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW
1206 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_RESET  _u(0x0)
1207 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_BITS   _u(0x00000400)
1208 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_MSB    _u(10)
1209 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_LSB    _u(10)
1210 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW"
1211 // -----------------------------------------------------------------------------
1212 // Field       : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH
1213 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_RESET  _u(0x0)
1214 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_BITS   _u(0x00000200)
1215 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_MSB    _u(9)
1216 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_LSB    _u(9)
1217 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW"
1218 // -----------------------------------------------------------------------------
1219 // Field       : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW
1220 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_RESET  _u(0x0)
1221 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_BITS   _u(0x00000100)
1222 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_MSB    _u(8)
1223 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_LSB    _u(8)
1224 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW"
1225 // -----------------------------------------------------------------------------
1226 // Field       : IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH
1227 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_RESET  _u(0x0)
1228 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_BITS   _u(0x00000080)
1229 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_MSB    _u(7)
1230 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_LSB    _u(7)
1231 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW"
1232 // -----------------------------------------------------------------------------
1233 // Field       : IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW
1234 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_RESET  _u(0x0)
1235 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_BITS   _u(0x00000040)
1236 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_MSB    _u(6)
1237 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_LSB    _u(6)
1238 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW"
1239 // -----------------------------------------------------------------------------
1240 // Field       : IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH
1241 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_RESET  _u(0x0)
1242 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_BITS   _u(0x00000020)
1243 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_MSB    _u(5)
1244 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_LSB    _u(5)
1245 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW"
1246 // -----------------------------------------------------------------------------
1247 // Field       : IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW
1248 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_RESET  _u(0x0)
1249 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_BITS   _u(0x00000010)
1250 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_MSB    _u(4)
1251 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_LSB    _u(4)
1252 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW"
1253 // -----------------------------------------------------------------------------
1254 // Field       : IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH
1255 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_RESET  _u(0x0)
1256 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_BITS   _u(0x00000008)
1257 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_MSB    _u(3)
1258 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_LSB    _u(3)
1259 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW"
1260 // -----------------------------------------------------------------------------
1261 // Field       : IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW
1262 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_RESET  _u(0x0)
1263 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_BITS   _u(0x00000004)
1264 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_MSB    _u(2)
1265 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_LSB    _u(2)
1266 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW"
1267 // -----------------------------------------------------------------------------
1268 // Field       : IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH
1269 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET  _u(0x0)
1270 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS   _u(0x00000002)
1271 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB    _u(1)
1272 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB    _u(1)
1273 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW"
1274 // -----------------------------------------------------------------------------
1275 // Field       : IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW
1276 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_RESET  _u(0x0)
1277 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_BITS   _u(0x00000001)
1278 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_MSB    _u(0)
1279 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_LSB    _u(0)
1280 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RW"
1281 // =============================================================================
1282 // Register    : IO_QSPI_PROC0_INTF
1283 // Description : Interrupt Force for proc0
1284 #define IO_QSPI_PROC0_INTF_OFFSET _u(0x00000038)
1285 #define IO_QSPI_PROC0_INTF_BITS   _u(0x00ffffff)
1286 #define IO_QSPI_PROC0_INTF_RESET  _u(0x00000000)
1287 // -----------------------------------------------------------------------------
1288 // Field       : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH
1289 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_RESET  _u(0x0)
1290 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_BITS   _u(0x00800000)
1291 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_MSB    _u(23)
1292 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_LSB    _u(23)
1293 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW"
1294 // -----------------------------------------------------------------------------
1295 // Field       : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW
1296 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_RESET  _u(0x0)
1297 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_BITS   _u(0x00400000)
1298 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_MSB    _u(22)
1299 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_LSB    _u(22)
1300 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW"
1301 // -----------------------------------------------------------------------------
1302 // Field       : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH
1303 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_RESET  _u(0x0)
1304 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_BITS   _u(0x00200000)
1305 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_MSB    _u(21)
1306 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_LSB    _u(21)
1307 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW"
1308 // -----------------------------------------------------------------------------
1309 // Field       : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW
1310 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_RESET  _u(0x0)
1311 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_BITS   _u(0x00100000)
1312 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_MSB    _u(20)
1313 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_LSB    _u(20)
1314 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW"
1315 // -----------------------------------------------------------------------------
1316 // Field       : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH
1317 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_RESET  _u(0x0)
1318 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_BITS   _u(0x00080000)
1319 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_MSB    _u(19)
1320 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_LSB    _u(19)
1321 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW"
1322 // -----------------------------------------------------------------------------
1323 // Field       : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW
1324 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_RESET  _u(0x0)
1325 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_BITS   _u(0x00040000)
1326 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_MSB    _u(18)
1327 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_LSB    _u(18)
1328 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW"
1329 // -----------------------------------------------------------------------------
1330 // Field       : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH
1331 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_RESET  _u(0x0)
1332 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_BITS   _u(0x00020000)
1333 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_MSB    _u(17)
1334 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_LSB    _u(17)
1335 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW"
1336 // -----------------------------------------------------------------------------
1337 // Field       : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW
1338 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_RESET  _u(0x0)
1339 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_BITS   _u(0x00010000)
1340 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_MSB    _u(16)
1341 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_LSB    _u(16)
1342 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW"
1343 // -----------------------------------------------------------------------------
1344 // Field       : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH
1345 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_RESET  _u(0x0)
1346 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_BITS   _u(0x00008000)
1347 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_MSB    _u(15)
1348 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_LSB    _u(15)
1349 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW"
1350 // -----------------------------------------------------------------------------
1351 // Field       : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW
1352 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_RESET  _u(0x0)
1353 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_BITS   _u(0x00004000)
1354 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_MSB    _u(14)
1355 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_LSB    _u(14)
1356 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW"
1357 // -----------------------------------------------------------------------------
1358 // Field       : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH
1359 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_RESET  _u(0x0)
1360 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_BITS   _u(0x00002000)
1361 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_MSB    _u(13)
1362 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_LSB    _u(13)
1363 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW"
1364 // -----------------------------------------------------------------------------
1365 // Field       : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW
1366 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_RESET  _u(0x0)
1367 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_BITS   _u(0x00001000)
1368 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_MSB    _u(12)
1369 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_LSB    _u(12)
1370 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW"
1371 // -----------------------------------------------------------------------------
1372 // Field       : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH
1373 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_RESET  _u(0x0)
1374 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_BITS   _u(0x00000800)
1375 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_MSB    _u(11)
1376 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_LSB    _u(11)
1377 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW"
1378 // -----------------------------------------------------------------------------
1379 // Field       : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW
1380 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_RESET  _u(0x0)
1381 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_BITS   _u(0x00000400)
1382 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_MSB    _u(10)
1383 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_LSB    _u(10)
1384 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW"
1385 // -----------------------------------------------------------------------------
1386 // Field       : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH
1387 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_RESET  _u(0x0)
1388 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_BITS   _u(0x00000200)
1389 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_MSB    _u(9)
1390 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_LSB    _u(9)
1391 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW"
1392 // -----------------------------------------------------------------------------
1393 // Field       : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW
1394 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_RESET  _u(0x0)
1395 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_BITS   _u(0x00000100)
1396 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_MSB    _u(8)
1397 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_LSB    _u(8)
1398 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW"
1399 // -----------------------------------------------------------------------------
1400 // Field       : IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH
1401 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_RESET  _u(0x0)
1402 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_BITS   _u(0x00000080)
1403 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_MSB    _u(7)
1404 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_LSB    _u(7)
1405 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW"
1406 // -----------------------------------------------------------------------------
1407 // Field       : IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW
1408 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_RESET  _u(0x0)
1409 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_BITS   _u(0x00000040)
1410 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_MSB    _u(6)
1411 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_LSB    _u(6)
1412 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW"
1413 // -----------------------------------------------------------------------------
1414 // Field       : IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH
1415 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_RESET  _u(0x0)
1416 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_BITS   _u(0x00000020)
1417 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_MSB    _u(5)
1418 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_LSB    _u(5)
1419 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW"
1420 // -----------------------------------------------------------------------------
1421 // Field       : IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW
1422 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_RESET  _u(0x0)
1423 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_BITS   _u(0x00000010)
1424 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_MSB    _u(4)
1425 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_LSB    _u(4)
1426 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW"
1427 // -----------------------------------------------------------------------------
1428 // Field       : IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH
1429 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_RESET  _u(0x0)
1430 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_BITS   _u(0x00000008)
1431 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_MSB    _u(3)
1432 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_LSB    _u(3)
1433 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW"
1434 // -----------------------------------------------------------------------------
1435 // Field       : IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW
1436 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_RESET  _u(0x0)
1437 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_BITS   _u(0x00000004)
1438 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_MSB    _u(2)
1439 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_LSB    _u(2)
1440 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW"
1441 // -----------------------------------------------------------------------------
1442 // Field       : IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH
1443 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET  _u(0x0)
1444 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS   _u(0x00000002)
1445 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB    _u(1)
1446 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB    _u(1)
1447 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW"
1448 // -----------------------------------------------------------------------------
1449 // Field       : IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW
1450 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_RESET  _u(0x0)
1451 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_BITS   _u(0x00000001)
1452 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_MSB    _u(0)
1453 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_LSB    _u(0)
1454 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RW"
1455 // =============================================================================
1456 // Register    : IO_QSPI_PROC0_INTS
1457 // Description : Interrupt status after masking & forcing for proc0
1458 #define IO_QSPI_PROC0_INTS_OFFSET _u(0x0000003c)
1459 #define IO_QSPI_PROC0_INTS_BITS   _u(0x00ffffff)
1460 #define IO_QSPI_PROC0_INTS_RESET  _u(0x00000000)
1461 // -----------------------------------------------------------------------------
1462 // Field       : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH
1463 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_RESET  _u(0x0)
1464 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_BITS   _u(0x00800000)
1465 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_MSB    _u(23)
1466 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_LSB    _u(23)
1467 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RO"
1468 // -----------------------------------------------------------------------------
1469 // Field       : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW
1470 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_RESET  _u(0x0)
1471 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_BITS   _u(0x00400000)
1472 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_MSB    _u(22)
1473 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_LSB    _u(22)
1474 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RO"
1475 // -----------------------------------------------------------------------------
1476 // Field       : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH
1477 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_RESET  _u(0x0)
1478 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_BITS   _u(0x00200000)
1479 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_MSB    _u(21)
1480 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_LSB    _u(21)
1481 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RO"
1482 // -----------------------------------------------------------------------------
1483 // Field       : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW
1484 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_RESET  _u(0x0)
1485 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_BITS   _u(0x00100000)
1486 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_MSB    _u(20)
1487 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_LSB    _u(20)
1488 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RO"
1489 // -----------------------------------------------------------------------------
1490 // Field       : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH
1491 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_RESET  _u(0x0)
1492 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_BITS   _u(0x00080000)
1493 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_MSB    _u(19)
1494 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_LSB    _u(19)
1495 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RO"
1496 // -----------------------------------------------------------------------------
1497 // Field       : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW
1498 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_RESET  _u(0x0)
1499 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_BITS   _u(0x00040000)
1500 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_MSB    _u(18)
1501 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_LSB    _u(18)
1502 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RO"
1503 // -----------------------------------------------------------------------------
1504 // Field       : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH
1505 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_RESET  _u(0x0)
1506 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_BITS   _u(0x00020000)
1507 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_MSB    _u(17)
1508 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_LSB    _u(17)
1509 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RO"
1510 // -----------------------------------------------------------------------------
1511 // Field       : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW
1512 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_RESET  _u(0x0)
1513 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_BITS   _u(0x00010000)
1514 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_MSB    _u(16)
1515 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_LSB    _u(16)
1516 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RO"
1517 // -----------------------------------------------------------------------------
1518 // Field       : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH
1519 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_RESET  _u(0x0)
1520 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_BITS   _u(0x00008000)
1521 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_MSB    _u(15)
1522 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_LSB    _u(15)
1523 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RO"
1524 // -----------------------------------------------------------------------------
1525 // Field       : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW
1526 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_RESET  _u(0x0)
1527 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_BITS   _u(0x00004000)
1528 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_MSB    _u(14)
1529 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_LSB    _u(14)
1530 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RO"
1531 // -----------------------------------------------------------------------------
1532 // Field       : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH
1533 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_RESET  _u(0x0)
1534 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_BITS   _u(0x00002000)
1535 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_MSB    _u(13)
1536 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_LSB    _u(13)
1537 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RO"
1538 // -----------------------------------------------------------------------------
1539 // Field       : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW
1540 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_RESET  _u(0x0)
1541 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_BITS   _u(0x00001000)
1542 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_MSB    _u(12)
1543 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_LSB    _u(12)
1544 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RO"
1545 // -----------------------------------------------------------------------------
1546 // Field       : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH
1547 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_RESET  _u(0x0)
1548 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_BITS   _u(0x00000800)
1549 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_MSB    _u(11)
1550 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_LSB    _u(11)
1551 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RO"
1552 // -----------------------------------------------------------------------------
1553 // Field       : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW
1554 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_RESET  _u(0x0)
1555 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_BITS   _u(0x00000400)
1556 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_MSB    _u(10)
1557 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_LSB    _u(10)
1558 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RO"
1559 // -----------------------------------------------------------------------------
1560 // Field       : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH
1561 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_RESET  _u(0x0)
1562 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_BITS   _u(0x00000200)
1563 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_MSB    _u(9)
1564 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_LSB    _u(9)
1565 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RO"
1566 // -----------------------------------------------------------------------------
1567 // Field       : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW
1568 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_RESET  _u(0x0)
1569 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_BITS   _u(0x00000100)
1570 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_MSB    _u(8)
1571 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_LSB    _u(8)
1572 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RO"
1573 // -----------------------------------------------------------------------------
1574 // Field       : IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH
1575 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_RESET  _u(0x0)
1576 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_BITS   _u(0x00000080)
1577 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_MSB    _u(7)
1578 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_LSB    _u(7)
1579 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RO"
1580 // -----------------------------------------------------------------------------
1581 // Field       : IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW
1582 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_RESET  _u(0x0)
1583 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_BITS   _u(0x00000040)
1584 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_MSB    _u(6)
1585 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_LSB    _u(6)
1586 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RO"
1587 // -----------------------------------------------------------------------------
1588 // Field       : IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH
1589 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_RESET  _u(0x0)
1590 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_BITS   _u(0x00000020)
1591 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_MSB    _u(5)
1592 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_LSB    _u(5)
1593 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RO"
1594 // -----------------------------------------------------------------------------
1595 // Field       : IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW
1596 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_RESET  _u(0x0)
1597 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_BITS   _u(0x00000010)
1598 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_MSB    _u(4)
1599 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_LSB    _u(4)
1600 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RO"
1601 // -----------------------------------------------------------------------------
1602 // Field       : IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH
1603 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_RESET  _u(0x0)
1604 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_BITS   _u(0x00000008)
1605 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_MSB    _u(3)
1606 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_LSB    _u(3)
1607 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RO"
1608 // -----------------------------------------------------------------------------
1609 // Field       : IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW
1610 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_RESET  _u(0x0)
1611 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_BITS   _u(0x00000004)
1612 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_MSB    _u(2)
1613 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_LSB    _u(2)
1614 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RO"
1615 // -----------------------------------------------------------------------------
1616 // Field       : IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH
1617 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET  _u(0x0)
1618 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS   _u(0x00000002)
1619 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB    _u(1)
1620 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB    _u(1)
1621 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RO"
1622 // -----------------------------------------------------------------------------
1623 // Field       : IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW
1624 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_RESET  _u(0x0)
1625 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_BITS   _u(0x00000001)
1626 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_MSB    _u(0)
1627 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_LSB    _u(0)
1628 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RO"
1629 // =============================================================================
1630 // Register    : IO_QSPI_PROC1_INTE
1631 // Description : Interrupt Enable for proc1
1632 #define IO_QSPI_PROC1_INTE_OFFSET _u(0x00000040)
1633 #define IO_QSPI_PROC1_INTE_BITS   _u(0x00ffffff)
1634 #define IO_QSPI_PROC1_INTE_RESET  _u(0x00000000)
1635 // -----------------------------------------------------------------------------
1636 // Field       : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH
1637 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_RESET  _u(0x0)
1638 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_BITS   _u(0x00800000)
1639 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_MSB    _u(23)
1640 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_LSB    _u(23)
1641 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW"
1642 // -----------------------------------------------------------------------------
1643 // Field       : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW
1644 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_RESET  _u(0x0)
1645 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_BITS   _u(0x00400000)
1646 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_MSB    _u(22)
1647 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_LSB    _u(22)
1648 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW"
1649 // -----------------------------------------------------------------------------
1650 // Field       : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH
1651 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_RESET  _u(0x0)
1652 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_BITS   _u(0x00200000)
1653 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_MSB    _u(21)
1654 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_LSB    _u(21)
1655 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW"
1656 // -----------------------------------------------------------------------------
1657 // Field       : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW
1658 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_RESET  _u(0x0)
1659 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_BITS   _u(0x00100000)
1660 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_MSB    _u(20)
1661 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_LSB    _u(20)
1662 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW"
1663 // -----------------------------------------------------------------------------
1664 // Field       : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH
1665 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_RESET  _u(0x0)
1666 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_BITS   _u(0x00080000)
1667 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_MSB    _u(19)
1668 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_LSB    _u(19)
1669 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW"
1670 // -----------------------------------------------------------------------------
1671 // Field       : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW
1672 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_RESET  _u(0x0)
1673 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_BITS   _u(0x00040000)
1674 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_MSB    _u(18)
1675 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_LSB    _u(18)
1676 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW"
1677 // -----------------------------------------------------------------------------
1678 // Field       : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH
1679 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_RESET  _u(0x0)
1680 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_BITS   _u(0x00020000)
1681 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_MSB    _u(17)
1682 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_LSB    _u(17)
1683 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW"
1684 // -----------------------------------------------------------------------------
1685 // Field       : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW
1686 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_RESET  _u(0x0)
1687 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_BITS   _u(0x00010000)
1688 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_MSB    _u(16)
1689 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_LSB    _u(16)
1690 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW"
1691 // -----------------------------------------------------------------------------
1692 // Field       : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH
1693 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_RESET  _u(0x0)
1694 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_BITS   _u(0x00008000)
1695 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_MSB    _u(15)
1696 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_LSB    _u(15)
1697 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW"
1698 // -----------------------------------------------------------------------------
1699 // Field       : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW
1700 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_RESET  _u(0x0)
1701 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_BITS   _u(0x00004000)
1702 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_MSB    _u(14)
1703 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_LSB    _u(14)
1704 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW"
1705 // -----------------------------------------------------------------------------
1706 // Field       : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH
1707 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_RESET  _u(0x0)
1708 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_BITS   _u(0x00002000)
1709 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_MSB    _u(13)
1710 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_LSB    _u(13)
1711 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW"
1712 // -----------------------------------------------------------------------------
1713 // Field       : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW
1714 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_RESET  _u(0x0)
1715 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_BITS   _u(0x00001000)
1716 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_MSB    _u(12)
1717 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_LSB    _u(12)
1718 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW"
1719 // -----------------------------------------------------------------------------
1720 // Field       : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH
1721 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_RESET  _u(0x0)
1722 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_BITS   _u(0x00000800)
1723 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_MSB    _u(11)
1724 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_LSB    _u(11)
1725 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW"
1726 // -----------------------------------------------------------------------------
1727 // Field       : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW
1728 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_RESET  _u(0x0)
1729 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_BITS   _u(0x00000400)
1730 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_MSB    _u(10)
1731 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_LSB    _u(10)
1732 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW"
1733 // -----------------------------------------------------------------------------
1734 // Field       : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH
1735 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_RESET  _u(0x0)
1736 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_BITS   _u(0x00000200)
1737 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_MSB    _u(9)
1738 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_LSB    _u(9)
1739 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW"
1740 // -----------------------------------------------------------------------------
1741 // Field       : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW
1742 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_RESET  _u(0x0)
1743 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_BITS   _u(0x00000100)
1744 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_MSB    _u(8)
1745 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_LSB    _u(8)
1746 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW"
1747 // -----------------------------------------------------------------------------
1748 // Field       : IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH
1749 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_RESET  _u(0x0)
1750 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_BITS   _u(0x00000080)
1751 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_MSB    _u(7)
1752 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_LSB    _u(7)
1753 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW"
1754 // -----------------------------------------------------------------------------
1755 // Field       : IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW
1756 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_RESET  _u(0x0)
1757 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_BITS   _u(0x00000040)
1758 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_MSB    _u(6)
1759 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_LSB    _u(6)
1760 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW"
1761 // -----------------------------------------------------------------------------
1762 // Field       : IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH
1763 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_RESET  _u(0x0)
1764 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_BITS   _u(0x00000020)
1765 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_MSB    _u(5)
1766 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_LSB    _u(5)
1767 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW"
1768 // -----------------------------------------------------------------------------
1769 // Field       : IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW
1770 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_RESET  _u(0x0)
1771 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_BITS   _u(0x00000010)
1772 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_MSB    _u(4)
1773 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_LSB    _u(4)
1774 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW"
1775 // -----------------------------------------------------------------------------
1776 // Field       : IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH
1777 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_RESET  _u(0x0)
1778 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_BITS   _u(0x00000008)
1779 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_MSB    _u(3)
1780 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_LSB    _u(3)
1781 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW"
1782 // -----------------------------------------------------------------------------
1783 // Field       : IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW
1784 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_RESET  _u(0x0)
1785 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_BITS   _u(0x00000004)
1786 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_MSB    _u(2)
1787 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_LSB    _u(2)
1788 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW"
1789 // -----------------------------------------------------------------------------
1790 // Field       : IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH
1791 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET  _u(0x0)
1792 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS   _u(0x00000002)
1793 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB    _u(1)
1794 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB    _u(1)
1795 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW"
1796 // -----------------------------------------------------------------------------
1797 // Field       : IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW
1798 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_RESET  _u(0x0)
1799 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_BITS   _u(0x00000001)
1800 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_MSB    _u(0)
1801 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_LSB    _u(0)
1802 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RW"
1803 // =============================================================================
1804 // Register    : IO_QSPI_PROC1_INTF
1805 // Description : Interrupt Force for proc1
1806 #define IO_QSPI_PROC1_INTF_OFFSET _u(0x00000044)
1807 #define IO_QSPI_PROC1_INTF_BITS   _u(0x00ffffff)
1808 #define IO_QSPI_PROC1_INTF_RESET  _u(0x00000000)
1809 // -----------------------------------------------------------------------------
1810 // Field       : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH
1811 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_RESET  _u(0x0)
1812 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_BITS   _u(0x00800000)
1813 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_MSB    _u(23)
1814 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_LSB    _u(23)
1815 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW"
1816 // -----------------------------------------------------------------------------
1817 // Field       : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW
1818 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_RESET  _u(0x0)
1819 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_BITS   _u(0x00400000)
1820 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_MSB    _u(22)
1821 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_LSB    _u(22)
1822 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW"
1823 // -----------------------------------------------------------------------------
1824 // Field       : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH
1825 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_RESET  _u(0x0)
1826 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_BITS   _u(0x00200000)
1827 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_MSB    _u(21)
1828 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_LSB    _u(21)
1829 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW"
1830 // -----------------------------------------------------------------------------
1831 // Field       : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW
1832 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_RESET  _u(0x0)
1833 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_BITS   _u(0x00100000)
1834 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_MSB    _u(20)
1835 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_LSB    _u(20)
1836 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW"
1837 // -----------------------------------------------------------------------------
1838 // Field       : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH
1839 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_RESET  _u(0x0)
1840 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_BITS   _u(0x00080000)
1841 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_MSB    _u(19)
1842 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_LSB    _u(19)
1843 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW"
1844 // -----------------------------------------------------------------------------
1845 // Field       : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW
1846 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_RESET  _u(0x0)
1847 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_BITS   _u(0x00040000)
1848 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_MSB    _u(18)
1849 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_LSB    _u(18)
1850 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW"
1851 // -----------------------------------------------------------------------------
1852 // Field       : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH
1853 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_RESET  _u(0x0)
1854 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_BITS   _u(0x00020000)
1855 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_MSB    _u(17)
1856 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_LSB    _u(17)
1857 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW"
1858 // -----------------------------------------------------------------------------
1859 // Field       : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW
1860 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_RESET  _u(0x0)
1861 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_BITS   _u(0x00010000)
1862 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_MSB    _u(16)
1863 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_LSB    _u(16)
1864 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW"
1865 // -----------------------------------------------------------------------------
1866 // Field       : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH
1867 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_RESET  _u(0x0)
1868 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_BITS   _u(0x00008000)
1869 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_MSB    _u(15)
1870 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_LSB    _u(15)
1871 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW"
1872 // -----------------------------------------------------------------------------
1873 // Field       : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW
1874 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_RESET  _u(0x0)
1875 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_BITS   _u(0x00004000)
1876 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_MSB    _u(14)
1877 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_LSB    _u(14)
1878 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW"
1879 // -----------------------------------------------------------------------------
1880 // Field       : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH
1881 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_RESET  _u(0x0)
1882 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_BITS   _u(0x00002000)
1883 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_MSB    _u(13)
1884 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_LSB    _u(13)
1885 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW"
1886 // -----------------------------------------------------------------------------
1887 // Field       : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW
1888 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_RESET  _u(0x0)
1889 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_BITS   _u(0x00001000)
1890 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_MSB    _u(12)
1891 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_LSB    _u(12)
1892 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW"
1893 // -----------------------------------------------------------------------------
1894 // Field       : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH
1895 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_RESET  _u(0x0)
1896 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_BITS   _u(0x00000800)
1897 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_MSB    _u(11)
1898 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_LSB    _u(11)
1899 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW"
1900 // -----------------------------------------------------------------------------
1901 // Field       : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW
1902 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_RESET  _u(0x0)
1903 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_BITS   _u(0x00000400)
1904 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_MSB    _u(10)
1905 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_LSB    _u(10)
1906 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW"
1907 // -----------------------------------------------------------------------------
1908 // Field       : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH
1909 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_RESET  _u(0x0)
1910 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_BITS   _u(0x00000200)
1911 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_MSB    _u(9)
1912 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_LSB    _u(9)
1913 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW"
1914 // -----------------------------------------------------------------------------
1915 // Field       : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW
1916 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_RESET  _u(0x0)
1917 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_BITS   _u(0x00000100)
1918 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_MSB    _u(8)
1919 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_LSB    _u(8)
1920 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW"
1921 // -----------------------------------------------------------------------------
1922 // Field       : IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH
1923 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_RESET  _u(0x0)
1924 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_BITS   _u(0x00000080)
1925 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_MSB    _u(7)
1926 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_LSB    _u(7)
1927 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW"
1928 // -----------------------------------------------------------------------------
1929 // Field       : IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW
1930 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_RESET  _u(0x0)
1931 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_BITS   _u(0x00000040)
1932 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_MSB    _u(6)
1933 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_LSB    _u(6)
1934 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW"
1935 // -----------------------------------------------------------------------------
1936 // Field       : IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH
1937 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_RESET  _u(0x0)
1938 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_BITS   _u(0x00000020)
1939 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_MSB    _u(5)
1940 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_LSB    _u(5)
1941 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW"
1942 // -----------------------------------------------------------------------------
1943 // Field       : IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW
1944 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_RESET  _u(0x0)
1945 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_BITS   _u(0x00000010)
1946 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_MSB    _u(4)
1947 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_LSB    _u(4)
1948 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW"
1949 // -----------------------------------------------------------------------------
1950 // Field       : IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH
1951 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_RESET  _u(0x0)
1952 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_BITS   _u(0x00000008)
1953 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_MSB    _u(3)
1954 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_LSB    _u(3)
1955 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW"
1956 // -----------------------------------------------------------------------------
1957 // Field       : IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW
1958 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_RESET  _u(0x0)
1959 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_BITS   _u(0x00000004)
1960 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_MSB    _u(2)
1961 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_LSB    _u(2)
1962 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW"
1963 // -----------------------------------------------------------------------------
1964 // Field       : IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH
1965 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET  _u(0x0)
1966 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS   _u(0x00000002)
1967 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB    _u(1)
1968 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB    _u(1)
1969 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW"
1970 // -----------------------------------------------------------------------------
1971 // Field       : IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW
1972 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_RESET  _u(0x0)
1973 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_BITS   _u(0x00000001)
1974 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_MSB    _u(0)
1975 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_LSB    _u(0)
1976 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RW"
1977 // =============================================================================
1978 // Register    : IO_QSPI_PROC1_INTS
1979 // Description : Interrupt status after masking & forcing for proc1
1980 #define IO_QSPI_PROC1_INTS_OFFSET _u(0x00000048)
1981 #define IO_QSPI_PROC1_INTS_BITS   _u(0x00ffffff)
1982 #define IO_QSPI_PROC1_INTS_RESET  _u(0x00000000)
1983 // -----------------------------------------------------------------------------
1984 // Field       : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH
1985 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_RESET  _u(0x0)
1986 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_BITS   _u(0x00800000)
1987 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_MSB    _u(23)
1988 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_LSB    _u(23)
1989 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RO"
1990 // -----------------------------------------------------------------------------
1991 // Field       : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW
1992 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_RESET  _u(0x0)
1993 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_BITS   _u(0x00400000)
1994 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_MSB    _u(22)
1995 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_LSB    _u(22)
1996 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RO"
1997 // -----------------------------------------------------------------------------
1998 // Field       : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH
1999 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_RESET  _u(0x0)
2000 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_BITS   _u(0x00200000)
2001 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_MSB    _u(21)
2002 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_LSB    _u(21)
2003 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RO"
2004 // -----------------------------------------------------------------------------
2005 // Field       : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW
2006 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_RESET  _u(0x0)
2007 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_BITS   _u(0x00100000)
2008 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_MSB    _u(20)
2009 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_LSB    _u(20)
2010 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RO"
2011 // -----------------------------------------------------------------------------
2012 // Field       : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH
2013 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_RESET  _u(0x0)
2014 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_BITS   _u(0x00080000)
2015 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_MSB    _u(19)
2016 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_LSB    _u(19)
2017 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RO"
2018 // -----------------------------------------------------------------------------
2019 // Field       : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW
2020 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_RESET  _u(0x0)
2021 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_BITS   _u(0x00040000)
2022 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_MSB    _u(18)
2023 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_LSB    _u(18)
2024 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RO"
2025 // -----------------------------------------------------------------------------
2026 // Field       : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH
2027 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_RESET  _u(0x0)
2028 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_BITS   _u(0x00020000)
2029 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_MSB    _u(17)
2030 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_LSB    _u(17)
2031 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RO"
2032 // -----------------------------------------------------------------------------
2033 // Field       : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW
2034 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_RESET  _u(0x0)
2035 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_BITS   _u(0x00010000)
2036 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_MSB    _u(16)
2037 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_LSB    _u(16)
2038 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RO"
2039 // -----------------------------------------------------------------------------
2040 // Field       : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH
2041 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_RESET  _u(0x0)
2042 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_BITS   _u(0x00008000)
2043 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_MSB    _u(15)
2044 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_LSB    _u(15)
2045 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RO"
2046 // -----------------------------------------------------------------------------
2047 // Field       : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW
2048 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_RESET  _u(0x0)
2049 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_BITS   _u(0x00004000)
2050 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_MSB    _u(14)
2051 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_LSB    _u(14)
2052 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RO"
2053 // -----------------------------------------------------------------------------
2054 // Field       : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH
2055 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_RESET  _u(0x0)
2056 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_BITS   _u(0x00002000)
2057 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_MSB    _u(13)
2058 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_LSB    _u(13)
2059 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RO"
2060 // -----------------------------------------------------------------------------
2061 // Field       : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW
2062 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_RESET  _u(0x0)
2063 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_BITS   _u(0x00001000)
2064 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_MSB    _u(12)
2065 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_LSB    _u(12)
2066 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RO"
2067 // -----------------------------------------------------------------------------
2068 // Field       : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH
2069 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_RESET  _u(0x0)
2070 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_BITS   _u(0x00000800)
2071 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_MSB    _u(11)
2072 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_LSB    _u(11)
2073 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RO"
2074 // -----------------------------------------------------------------------------
2075 // Field       : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW
2076 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_RESET  _u(0x0)
2077 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_BITS   _u(0x00000400)
2078 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_MSB    _u(10)
2079 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_LSB    _u(10)
2080 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RO"
2081 // -----------------------------------------------------------------------------
2082 // Field       : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH
2083 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_RESET  _u(0x0)
2084 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_BITS   _u(0x00000200)
2085 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_MSB    _u(9)
2086 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_LSB    _u(9)
2087 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RO"
2088 // -----------------------------------------------------------------------------
2089 // Field       : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW
2090 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_RESET  _u(0x0)
2091 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_BITS   _u(0x00000100)
2092 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_MSB    _u(8)
2093 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_LSB    _u(8)
2094 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RO"
2095 // -----------------------------------------------------------------------------
2096 // Field       : IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH
2097 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_RESET  _u(0x0)
2098 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_BITS   _u(0x00000080)
2099 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_MSB    _u(7)
2100 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_LSB    _u(7)
2101 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RO"
2102 // -----------------------------------------------------------------------------
2103 // Field       : IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW
2104 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_RESET  _u(0x0)
2105 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_BITS   _u(0x00000040)
2106 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_MSB    _u(6)
2107 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_LSB    _u(6)
2108 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RO"
2109 // -----------------------------------------------------------------------------
2110 // Field       : IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH
2111 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_RESET  _u(0x0)
2112 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_BITS   _u(0x00000020)
2113 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_MSB    _u(5)
2114 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_LSB    _u(5)
2115 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RO"
2116 // -----------------------------------------------------------------------------
2117 // Field       : IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW
2118 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_RESET  _u(0x0)
2119 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_BITS   _u(0x00000010)
2120 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_MSB    _u(4)
2121 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_LSB    _u(4)
2122 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RO"
2123 // -----------------------------------------------------------------------------
2124 // Field       : IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH
2125 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_RESET  _u(0x0)
2126 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_BITS   _u(0x00000008)
2127 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_MSB    _u(3)
2128 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_LSB    _u(3)
2129 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RO"
2130 // -----------------------------------------------------------------------------
2131 // Field       : IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW
2132 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_RESET  _u(0x0)
2133 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_BITS   _u(0x00000004)
2134 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_MSB    _u(2)
2135 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_LSB    _u(2)
2136 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RO"
2137 // -----------------------------------------------------------------------------
2138 // Field       : IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH
2139 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET  _u(0x0)
2140 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS   _u(0x00000002)
2141 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB    _u(1)
2142 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB    _u(1)
2143 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RO"
2144 // -----------------------------------------------------------------------------
2145 // Field       : IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW
2146 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_RESET  _u(0x0)
2147 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_BITS   _u(0x00000001)
2148 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_MSB    _u(0)
2149 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_LSB    _u(0)
2150 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RO"
2151 // =============================================================================
2152 // Register    : IO_QSPI_DORMANT_WAKE_INTE
2153 // Description : Interrupt Enable for dormant_wake
2154 #define IO_QSPI_DORMANT_WAKE_INTE_OFFSET _u(0x0000004c)
2155 #define IO_QSPI_DORMANT_WAKE_INTE_BITS   _u(0x00ffffff)
2156 #define IO_QSPI_DORMANT_WAKE_INTE_RESET  _u(0x00000000)
2157 // -----------------------------------------------------------------------------
2158 // Field       : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH
2159 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_RESET  _u(0x0)
2160 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_BITS   _u(0x00800000)
2161 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_MSB    _u(23)
2162 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_LSB    _u(23)
2163 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW"
2164 // -----------------------------------------------------------------------------
2165 // Field       : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW
2166 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_RESET  _u(0x0)
2167 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_BITS   _u(0x00400000)
2168 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_MSB    _u(22)
2169 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_LSB    _u(22)
2170 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW"
2171 // -----------------------------------------------------------------------------
2172 // Field       : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH
2173 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_RESET  _u(0x0)
2174 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_BITS   _u(0x00200000)
2175 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_MSB    _u(21)
2176 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_LSB    _u(21)
2177 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW"
2178 // -----------------------------------------------------------------------------
2179 // Field       : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW
2180 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_RESET  _u(0x0)
2181 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_BITS   _u(0x00100000)
2182 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_MSB    _u(20)
2183 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_LSB    _u(20)
2184 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW"
2185 // -----------------------------------------------------------------------------
2186 // Field       : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH
2187 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_RESET  _u(0x0)
2188 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_BITS   _u(0x00080000)
2189 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_MSB    _u(19)
2190 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_LSB    _u(19)
2191 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW"
2192 // -----------------------------------------------------------------------------
2193 // Field       : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW
2194 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_RESET  _u(0x0)
2195 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_BITS   _u(0x00040000)
2196 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_MSB    _u(18)
2197 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_LSB    _u(18)
2198 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW"
2199 // -----------------------------------------------------------------------------
2200 // Field       : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH
2201 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_RESET  _u(0x0)
2202 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_BITS   _u(0x00020000)
2203 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_MSB    _u(17)
2204 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_LSB    _u(17)
2205 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW"
2206 // -----------------------------------------------------------------------------
2207 // Field       : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW
2208 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_RESET  _u(0x0)
2209 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_BITS   _u(0x00010000)
2210 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_MSB    _u(16)
2211 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_LSB    _u(16)
2212 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW"
2213 // -----------------------------------------------------------------------------
2214 // Field       : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH
2215 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_RESET  _u(0x0)
2216 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_BITS   _u(0x00008000)
2217 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_MSB    _u(15)
2218 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_LSB    _u(15)
2219 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW"
2220 // -----------------------------------------------------------------------------
2221 // Field       : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW
2222 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_RESET  _u(0x0)
2223 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_BITS   _u(0x00004000)
2224 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_MSB    _u(14)
2225 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_LSB    _u(14)
2226 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW"
2227 // -----------------------------------------------------------------------------
2228 // Field       : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH
2229 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_RESET  _u(0x0)
2230 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_BITS   _u(0x00002000)
2231 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_MSB    _u(13)
2232 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_LSB    _u(13)
2233 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW"
2234 // -----------------------------------------------------------------------------
2235 // Field       : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW
2236 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_RESET  _u(0x0)
2237 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_BITS   _u(0x00001000)
2238 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_MSB    _u(12)
2239 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_LSB    _u(12)
2240 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW"
2241 // -----------------------------------------------------------------------------
2242 // Field       : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH
2243 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_RESET  _u(0x0)
2244 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_BITS   _u(0x00000800)
2245 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_MSB    _u(11)
2246 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_LSB    _u(11)
2247 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW"
2248 // -----------------------------------------------------------------------------
2249 // Field       : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW
2250 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_RESET  _u(0x0)
2251 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_BITS   _u(0x00000400)
2252 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_MSB    _u(10)
2253 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_LSB    _u(10)
2254 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW"
2255 // -----------------------------------------------------------------------------
2256 // Field       : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH
2257 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_RESET  _u(0x0)
2258 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_BITS   _u(0x00000200)
2259 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_MSB    _u(9)
2260 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_LSB    _u(9)
2261 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW"
2262 // -----------------------------------------------------------------------------
2263 // Field       : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW
2264 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_RESET  _u(0x0)
2265 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_BITS   _u(0x00000100)
2266 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_MSB    _u(8)
2267 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_LSB    _u(8)
2268 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW"
2269 // -----------------------------------------------------------------------------
2270 // Field       : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH
2271 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_RESET  _u(0x0)
2272 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_BITS   _u(0x00000080)
2273 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_MSB    _u(7)
2274 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_LSB    _u(7)
2275 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW"
2276 // -----------------------------------------------------------------------------
2277 // Field       : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW
2278 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_RESET  _u(0x0)
2279 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_BITS   _u(0x00000040)
2280 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_MSB    _u(6)
2281 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_LSB    _u(6)
2282 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW"
2283 // -----------------------------------------------------------------------------
2284 // Field       : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH
2285 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_RESET  _u(0x0)
2286 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_BITS   _u(0x00000020)
2287 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_MSB    _u(5)
2288 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_LSB    _u(5)
2289 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW"
2290 // -----------------------------------------------------------------------------
2291 // Field       : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW
2292 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_RESET  _u(0x0)
2293 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_BITS   _u(0x00000010)
2294 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_MSB    _u(4)
2295 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_LSB    _u(4)
2296 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW"
2297 // -----------------------------------------------------------------------------
2298 // Field       : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH
2299 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_RESET  _u(0x0)
2300 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_BITS   _u(0x00000008)
2301 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_MSB    _u(3)
2302 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_LSB    _u(3)
2303 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW"
2304 // -----------------------------------------------------------------------------
2305 // Field       : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW
2306 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_RESET  _u(0x0)
2307 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_BITS   _u(0x00000004)
2308 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_MSB    _u(2)
2309 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_LSB    _u(2)
2310 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW"
2311 // -----------------------------------------------------------------------------
2312 // Field       : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH
2313 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET  _u(0x0)
2314 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS   _u(0x00000002)
2315 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB    _u(1)
2316 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB    _u(1)
2317 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW"
2318 // -----------------------------------------------------------------------------
2319 // Field       : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW
2320 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_RESET  _u(0x0)
2321 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_BITS   _u(0x00000001)
2322 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_MSB    _u(0)
2323 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_LSB    _u(0)
2324 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RW"
2325 // =============================================================================
2326 // Register    : IO_QSPI_DORMANT_WAKE_INTF
2327 // Description : Interrupt Force for dormant_wake
2328 #define IO_QSPI_DORMANT_WAKE_INTF_OFFSET _u(0x00000050)
2329 #define IO_QSPI_DORMANT_WAKE_INTF_BITS   _u(0x00ffffff)
2330 #define IO_QSPI_DORMANT_WAKE_INTF_RESET  _u(0x00000000)
2331 // -----------------------------------------------------------------------------
2332 // Field       : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH
2333 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_RESET  _u(0x0)
2334 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_BITS   _u(0x00800000)
2335 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_MSB    _u(23)
2336 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_LSB    _u(23)
2337 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW"
2338 // -----------------------------------------------------------------------------
2339 // Field       : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW
2340 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_RESET  _u(0x0)
2341 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_BITS   _u(0x00400000)
2342 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_MSB    _u(22)
2343 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_LSB    _u(22)
2344 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW"
2345 // -----------------------------------------------------------------------------
2346 // Field       : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH
2347 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_RESET  _u(0x0)
2348 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_BITS   _u(0x00200000)
2349 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_MSB    _u(21)
2350 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_LSB    _u(21)
2351 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW"
2352 // -----------------------------------------------------------------------------
2353 // Field       : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW
2354 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_RESET  _u(0x0)
2355 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_BITS   _u(0x00100000)
2356 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_MSB    _u(20)
2357 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_LSB    _u(20)
2358 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW"
2359 // -----------------------------------------------------------------------------
2360 // Field       : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH
2361 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_RESET  _u(0x0)
2362 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_BITS   _u(0x00080000)
2363 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_MSB    _u(19)
2364 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_LSB    _u(19)
2365 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW"
2366 // -----------------------------------------------------------------------------
2367 // Field       : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW
2368 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_RESET  _u(0x0)
2369 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_BITS   _u(0x00040000)
2370 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_MSB    _u(18)
2371 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_LSB    _u(18)
2372 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW"
2373 // -----------------------------------------------------------------------------
2374 // Field       : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH
2375 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_RESET  _u(0x0)
2376 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_BITS   _u(0x00020000)
2377 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_MSB    _u(17)
2378 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_LSB    _u(17)
2379 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW"
2380 // -----------------------------------------------------------------------------
2381 // Field       : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW
2382 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_RESET  _u(0x0)
2383 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_BITS   _u(0x00010000)
2384 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_MSB    _u(16)
2385 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_LSB    _u(16)
2386 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW"
2387 // -----------------------------------------------------------------------------
2388 // Field       : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH
2389 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_RESET  _u(0x0)
2390 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_BITS   _u(0x00008000)
2391 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_MSB    _u(15)
2392 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_LSB    _u(15)
2393 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW"
2394 // -----------------------------------------------------------------------------
2395 // Field       : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW
2396 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_RESET  _u(0x0)
2397 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_BITS   _u(0x00004000)
2398 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_MSB    _u(14)
2399 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_LSB    _u(14)
2400 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW"
2401 // -----------------------------------------------------------------------------
2402 // Field       : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH
2403 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_RESET  _u(0x0)
2404 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_BITS   _u(0x00002000)
2405 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_MSB    _u(13)
2406 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_LSB    _u(13)
2407 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW"
2408 // -----------------------------------------------------------------------------
2409 // Field       : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW
2410 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_RESET  _u(0x0)
2411 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_BITS   _u(0x00001000)
2412 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_MSB    _u(12)
2413 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_LSB    _u(12)
2414 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW"
2415 // -----------------------------------------------------------------------------
2416 // Field       : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH
2417 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_RESET  _u(0x0)
2418 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_BITS   _u(0x00000800)
2419 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_MSB    _u(11)
2420 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_LSB    _u(11)
2421 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW"
2422 // -----------------------------------------------------------------------------
2423 // Field       : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW
2424 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_RESET  _u(0x0)
2425 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_BITS   _u(0x00000400)
2426 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_MSB    _u(10)
2427 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_LSB    _u(10)
2428 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW"
2429 // -----------------------------------------------------------------------------
2430 // Field       : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH
2431 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_RESET  _u(0x0)
2432 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_BITS   _u(0x00000200)
2433 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_MSB    _u(9)
2434 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_LSB    _u(9)
2435 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW"
2436 // -----------------------------------------------------------------------------
2437 // Field       : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW
2438 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_RESET  _u(0x0)
2439 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_BITS   _u(0x00000100)
2440 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_MSB    _u(8)
2441 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_LSB    _u(8)
2442 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW"
2443 // -----------------------------------------------------------------------------
2444 // Field       : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH
2445 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_RESET  _u(0x0)
2446 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_BITS   _u(0x00000080)
2447 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_MSB    _u(7)
2448 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_LSB    _u(7)
2449 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW"
2450 // -----------------------------------------------------------------------------
2451 // Field       : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW
2452 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_RESET  _u(0x0)
2453 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_BITS   _u(0x00000040)
2454 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_MSB    _u(6)
2455 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_LSB    _u(6)
2456 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW"
2457 // -----------------------------------------------------------------------------
2458 // Field       : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH
2459 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_RESET  _u(0x0)
2460 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_BITS   _u(0x00000020)
2461 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_MSB    _u(5)
2462 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_LSB    _u(5)
2463 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW"
2464 // -----------------------------------------------------------------------------
2465 // Field       : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW
2466 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_RESET  _u(0x0)
2467 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_BITS   _u(0x00000010)
2468 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_MSB    _u(4)
2469 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_LSB    _u(4)
2470 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW"
2471 // -----------------------------------------------------------------------------
2472 // Field       : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH
2473 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_RESET  _u(0x0)
2474 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_BITS   _u(0x00000008)
2475 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_MSB    _u(3)
2476 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_LSB    _u(3)
2477 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW"
2478 // -----------------------------------------------------------------------------
2479 // Field       : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW
2480 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_RESET  _u(0x0)
2481 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_BITS   _u(0x00000004)
2482 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_MSB    _u(2)
2483 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_LSB    _u(2)
2484 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW"
2485 // -----------------------------------------------------------------------------
2486 // Field       : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH
2487 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET  _u(0x0)
2488 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS   _u(0x00000002)
2489 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB    _u(1)
2490 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB    _u(1)
2491 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW"
2492 // -----------------------------------------------------------------------------
2493 // Field       : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW
2494 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_RESET  _u(0x0)
2495 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_BITS   _u(0x00000001)
2496 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_MSB    _u(0)
2497 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_LSB    _u(0)
2498 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RW"
2499 // =============================================================================
2500 // Register    : IO_QSPI_DORMANT_WAKE_INTS
2501 // Description : Interrupt status after masking & forcing for dormant_wake
2502 #define IO_QSPI_DORMANT_WAKE_INTS_OFFSET _u(0x00000054)
2503 #define IO_QSPI_DORMANT_WAKE_INTS_BITS   _u(0x00ffffff)
2504 #define IO_QSPI_DORMANT_WAKE_INTS_RESET  _u(0x00000000)
2505 // -----------------------------------------------------------------------------
2506 // Field       : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH
2507 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_RESET  _u(0x0)
2508 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_BITS   _u(0x00800000)
2509 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_MSB    _u(23)
2510 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_LSB    _u(23)
2511 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RO"
2512 // -----------------------------------------------------------------------------
2513 // Field       : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW
2514 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_RESET  _u(0x0)
2515 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_BITS   _u(0x00400000)
2516 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_MSB    _u(22)
2517 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_LSB    _u(22)
2518 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RO"
2519 // -----------------------------------------------------------------------------
2520 // Field       : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH
2521 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_RESET  _u(0x0)
2522 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_BITS   _u(0x00200000)
2523 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_MSB    _u(21)
2524 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_LSB    _u(21)
2525 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RO"
2526 // -----------------------------------------------------------------------------
2527 // Field       : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW
2528 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_RESET  _u(0x0)
2529 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_BITS   _u(0x00100000)
2530 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_MSB    _u(20)
2531 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_LSB    _u(20)
2532 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RO"
2533 // -----------------------------------------------------------------------------
2534 // Field       : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH
2535 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_RESET  _u(0x0)
2536 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_BITS   _u(0x00080000)
2537 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_MSB    _u(19)
2538 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_LSB    _u(19)
2539 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RO"
2540 // -----------------------------------------------------------------------------
2541 // Field       : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW
2542 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_RESET  _u(0x0)
2543 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_BITS   _u(0x00040000)
2544 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_MSB    _u(18)
2545 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_LSB    _u(18)
2546 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RO"
2547 // -----------------------------------------------------------------------------
2548 // Field       : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH
2549 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_RESET  _u(0x0)
2550 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_BITS   _u(0x00020000)
2551 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_MSB    _u(17)
2552 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_LSB    _u(17)
2553 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RO"
2554 // -----------------------------------------------------------------------------
2555 // Field       : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW
2556 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_RESET  _u(0x0)
2557 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_BITS   _u(0x00010000)
2558 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_MSB    _u(16)
2559 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_LSB    _u(16)
2560 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RO"
2561 // -----------------------------------------------------------------------------
2562 // Field       : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH
2563 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_RESET  _u(0x0)
2564 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_BITS   _u(0x00008000)
2565 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_MSB    _u(15)
2566 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_LSB    _u(15)
2567 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RO"
2568 // -----------------------------------------------------------------------------
2569 // Field       : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW
2570 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_RESET  _u(0x0)
2571 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_BITS   _u(0x00004000)
2572 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_MSB    _u(14)
2573 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_LSB    _u(14)
2574 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RO"
2575 // -----------------------------------------------------------------------------
2576 // Field       : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH
2577 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_RESET  _u(0x0)
2578 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_BITS   _u(0x00002000)
2579 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_MSB    _u(13)
2580 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_LSB    _u(13)
2581 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RO"
2582 // -----------------------------------------------------------------------------
2583 // Field       : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW
2584 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_RESET  _u(0x0)
2585 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_BITS   _u(0x00001000)
2586 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_MSB    _u(12)
2587 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_LSB    _u(12)
2588 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RO"
2589 // -----------------------------------------------------------------------------
2590 // Field       : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH
2591 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_RESET  _u(0x0)
2592 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_BITS   _u(0x00000800)
2593 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_MSB    _u(11)
2594 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_LSB    _u(11)
2595 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RO"
2596 // -----------------------------------------------------------------------------
2597 // Field       : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW
2598 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_RESET  _u(0x0)
2599 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_BITS   _u(0x00000400)
2600 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_MSB    _u(10)
2601 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_LSB    _u(10)
2602 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RO"
2603 // -----------------------------------------------------------------------------
2604 // Field       : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH
2605 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_RESET  _u(0x0)
2606 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_BITS   _u(0x00000200)
2607 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_MSB    _u(9)
2608 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_LSB    _u(9)
2609 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RO"
2610 // -----------------------------------------------------------------------------
2611 // Field       : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW
2612 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_RESET  _u(0x0)
2613 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_BITS   _u(0x00000100)
2614 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_MSB    _u(8)
2615 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_LSB    _u(8)
2616 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RO"
2617 // -----------------------------------------------------------------------------
2618 // Field       : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH
2619 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_RESET  _u(0x0)
2620 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_BITS   _u(0x00000080)
2621 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_MSB    _u(7)
2622 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_LSB    _u(7)
2623 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RO"
2624 // -----------------------------------------------------------------------------
2625 // Field       : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW
2626 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_RESET  _u(0x0)
2627 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_BITS   _u(0x00000040)
2628 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_MSB    _u(6)
2629 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_LSB    _u(6)
2630 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RO"
2631 // -----------------------------------------------------------------------------
2632 // Field       : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH
2633 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_RESET  _u(0x0)
2634 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_BITS   _u(0x00000020)
2635 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_MSB    _u(5)
2636 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_LSB    _u(5)
2637 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RO"
2638 // -----------------------------------------------------------------------------
2639 // Field       : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW
2640 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_RESET  _u(0x0)
2641 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_BITS   _u(0x00000010)
2642 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_MSB    _u(4)
2643 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_LSB    _u(4)
2644 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RO"
2645 // -----------------------------------------------------------------------------
2646 // Field       : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH
2647 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_RESET  _u(0x0)
2648 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_BITS   _u(0x00000008)
2649 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_MSB    _u(3)
2650 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_LSB    _u(3)
2651 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RO"
2652 // -----------------------------------------------------------------------------
2653 // Field       : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW
2654 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_RESET  _u(0x0)
2655 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_BITS   _u(0x00000004)
2656 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_MSB    _u(2)
2657 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_LSB    _u(2)
2658 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RO"
2659 // -----------------------------------------------------------------------------
2660 // Field       : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH
2661 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET  _u(0x0)
2662 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS   _u(0x00000002)
2663 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB    _u(1)
2664 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB    _u(1)
2665 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RO"
2666 // -----------------------------------------------------------------------------
2667 // Field       : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW
2668 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_RESET  _u(0x0)
2669 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_BITS   _u(0x00000001)
2670 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_MSB    _u(0)
2671 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_LSB    _u(0)
2672 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RO"
2673 // =============================================================================
2674 #endif // _HARDWARE_REGS_IO_QSPI_H
2675 
2676