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Searched refs:LOWPWR_CTRL (Results 1 – 25 of 35) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1021/drivers/
Dfsl_clock.c194 while ((XTALOSC24M->LOWPWR_CTRL & XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK) == 0UL) in CLOCK_InitExternalClk()
241 XTALOSC24M->LOWPWR_CTRL |= XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK; in CLOCK_InitRcOsc24M()
249 XTALOSC24M->LOWPWR_CTRL &= ~XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK; in CLOCK_DeinitRcOsc24M()
Dfsl_clock.h1350 …return ((XTALOSC24M->LOWPWR_CTRL & (uint32_t)XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK) != 0UL) ? 240000… in CLOCK_GetOscFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1024/drivers/
Dfsl_clock.c194 while ((XTALOSC24M->LOWPWR_CTRL & XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK) == 0UL) in CLOCK_InitExternalClk()
241 XTALOSC24M->LOWPWR_CTRL |= XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK; in CLOCK_InitRcOsc24M()
249 XTALOSC24M->LOWPWR_CTRL &= ~XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK; in CLOCK_DeinitRcOsc24M()
Dfsl_clock.h1356 …return ((XTALOSC24M->LOWPWR_CTRL & (uint32_t)XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK) != 0UL) ? 240000… in CLOCK_GetOscFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1011/drivers/
Dfsl_clock.c261 while ((XTALOSC24M->LOWPWR_CTRL & XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK) == 0UL) in CLOCK_InitExternalClk()
308 XTALOSC24M->LOWPWR_CTRL |= XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK; in CLOCK_InitRcOsc24M()
316 XTALOSC24M->LOWPWR_CTRL &= ~XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK; in CLOCK_DeinitRcOsc24M()
Dfsl_clock.h1131 …return ((XTALOSC24M->LOWPWR_CTRL & (uint32_t)XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK) != 0UL) ? 240000… in CLOCK_GetOscFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1015/drivers/
Dfsl_clock.c195 while ((XTALOSC24M->LOWPWR_CTRL & XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK) == 0UL) in CLOCK_InitExternalClk()
242 XTALOSC24M->LOWPWR_CTRL |= XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK; in CLOCK_InitRcOsc24M()
250 XTALOSC24M->LOWPWR_CTRL &= ~XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK; in CLOCK_DeinitRcOsc24M()
Dfsl_clock.h1198 …return ((XTALOSC24M->LOWPWR_CTRL & (uint32_t)XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK) != 0UL) ? 240000… in CLOCK_GetOscFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1041/drivers/
Dfsl_clock.c196 while ((XTALOSC24M->LOWPWR_CTRL & XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK) == 0U) in CLOCK_InitExternalClk()
243 XTALOSC24M->LOWPWR_CTRL |= XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK; in CLOCK_InitRcOsc24M()
251 XTALOSC24M->LOWPWR_CTRL &= ~XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK; in CLOCK_DeinitRcOsc24M()
Dfsl_clock.h1500 …return ((XTALOSC24M->LOWPWR_CTRL & XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK) != 0UL) ? 24000000UL : g_x… in CLOCK_GetOscFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1042/drivers/
Dfsl_clock.c196 while ((XTALOSC24M->LOWPWR_CTRL & XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK) == 0U) in CLOCK_InitExternalClk()
243 XTALOSC24M->LOWPWR_CTRL |= XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK; in CLOCK_InitRcOsc24M()
251 XTALOSC24M->LOWPWR_CTRL &= ~XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK; in CLOCK_DeinitRcOsc24M()
Dfsl_clock.h1500 …return ((XTALOSC24M->LOWPWR_CTRL & XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK) != 0UL) ? 24000000UL : g_x… in CLOCK_GetOscFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1061/drivers/
Dfsl_clock.c196 while ((XTALOSC24M->LOWPWR_CTRL & XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK) == 0U) in CLOCK_InitExternalClk()
243 XTALOSC24M->LOWPWR_CTRL |= XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK; in CLOCK_InitRcOsc24M()
251 XTALOSC24M->LOWPWR_CTRL &= ~XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK; in CLOCK_DeinitRcOsc24M()
Dfsl_clock.h1549 …return ((XTALOSC24M->LOWPWR_CTRL & XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK) != 0UL) ? 24000000UL : g_x… in CLOCK_GetOscFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1051/drivers/
Dfsl_clock.c196 while ((XTALOSC24M->LOWPWR_CTRL & XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK) == 0U) in CLOCK_InitExternalClk()
243 XTALOSC24M->LOWPWR_CTRL |= XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK; in CLOCK_InitRcOsc24M()
251 XTALOSC24M->LOWPWR_CTRL &= ~XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK; in CLOCK_DeinitRcOsc24M()
Dfsl_clock.h1518 …return ((XTALOSC24M->LOWPWR_CTRL & XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK) != 0UL) ? 24000000UL : g_x… in CLOCK_GetOscFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1052/drivers/
Dfsl_clock.c195 while ((XTALOSC24M->LOWPWR_CTRL & XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK) == 0U) in CLOCK_InitExternalClk()
242 XTALOSC24M->LOWPWR_CTRL |= XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK; in CLOCK_InitRcOsc24M()
250 XTALOSC24M->LOWPWR_CTRL &= ~XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK; in CLOCK_DeinitRcOsc24M()
Dfsl_clock.h1517 …return ((XTALOSC24M->LOWPWR_CTRL & XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK) != 0UL) ? 24000000UL : g_x… in CLOCK_GetOscFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1062/drivers/
Dfsl_clock.c196 while ((XTALOSC24M->LOWPWR_CTRL & XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK) == 0U) in CLOCK_InitExternalClk()
243 XTALOSC24M->LOWPWR_CTRL |= XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK; in CLOCK_InitRcOsc24M()
251 XTALOSC24M->LOWPWR_CTRL &= ~XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK; in CLOCK_DeinitRcOsc24M()
Dfsl_clock.h1548 …return ((XTALOSC24M->LOWPWR_CTRL & XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK) != 0UL) ? 24000000UL : g_x… in CLOCK_GetOscFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1064/drivers/
Dfsl_clock.c196 while ((XTALOSC24M->LOWPWR_CTRL & XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK) == 0U) in CLOCK_InitExternalClk()
243 XTALOSC24M->LOWPWR_CTRL |= XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK; in CLOCK_InitRcOsc24M()
251 XTALOSC24M->LOWPWR_CTRL &= ~XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK; in CLOCK_DeinitRcOsc24M()
Dfsl_clock.h1549 …return ((XTALOSC24M->LOWPWR_CTRL & XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK) != 0UL) ? 24000000UL : g_x… in CLOCK_GetOscFreq()
/hal_nxp-latest/imx/devices/MCIMX6X/
DMCIMX6X_M4.h39837 …__IO uint32_t LOWPWR_CTRL; /**< XTAL OSC (LP) Control Register, offset… member
39867 #define XTALOSC24M_LOWPWR_CTRL_REG(base) ((base)->LOWPWR_CTRL)
/hal_nxp-latest/imx/devices/MCIMX7D/
DMCIMX7D_M4.h32340 …__IO uint32_t LOWPWR_CTRL; /**< Anadig Low Power Control Register, off… member
32376 #define PMU_LOWPWR_CTRL_REG(base) ((base)->LOWPWR_CTRL)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1011/
DMIMXRT1011.h34976 …__IO uint32_t LOWPWR_CTRL; /**< XTAL OSC (LP) Control Register, offset: 0x27… member

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