1 /*
2 * Copyright 2018 -2021, 2024 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #ifndef _FSL_CLOCK_H_
9 #define _FSL_CLOCK_H_
10
11 #include "fsl_common.h"
12
13 /*! @addtogroup clock */
14 /*! @{ */
15
16 /*! @file */
17
18 /*******************************************************************************
19 * Configurations
20 ******************************************************************************/
21
22 /*! @brief Configure whether driver controls clock
23 *
24 * When set to 0, peripheral drivers will enable clock in initialize function
25 * and disable clock in de-initialize function. When set to 1, peripheral
26 * driver will not control the clock, application could control the clock out of
27 * the driver.
28 *
29 * @note All drivers share this feature switcher. If it is set to 1, application
30 * should handle clock enable and disable for all drivers.
31 */
32 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL))
33 #define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0
34 #endif
35
36 /*******************************************************************************
37 * Definitions
38 ******************************************************************************/
39
40 /*! @name Driver version */
41 /*@{*/
42 /*! @brief CLOCK driver version 2.5.3. */
43 #define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 5, 3))
44
45 /* Definition for delay API in clock driver, users can redefine it to the real application. */
46 #ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
47 #define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (600000000UL)
48 #endif
49
50 /* analog pll definition */
51 #define CCM_ANALOG_PLL_BYPASS_SHIFT (16U)
52 #define CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK (0xC000U)
53 #define CCM_ANALOG_PLL_BYPASS_CLK_SRC_SHIFT (14U)
54
55 /*@}*/
56
57 /*!
58 * @brief CCM registers offset.
59 */
60 #define CCSR_OFFSET 0x0C
61 #define CBCDR_OFFSET 0x14
62 #define CBCMR_OFFSET 0x18
63 #define CSCMR1_OFFSET 0x1C
64 #define CSCMR2_OFFSET 0x20
65 #define CSCDR1_OFFSET 0x24
66 #define CDCDR_OFFSET 0x30
67 #define CSCDR2_OFFSET 0x38
68 #define CSCDR3_OFFSET 0x3C
69 #define CACRR_OFFSET 0x10
70 #define CS1CDR_OFFSET 0x28
71 #define CS2CDR_OFFSET 0x2C
72
73 /*!
74 * @brief CCM Analog registers offset.
75 */
76 #define PLL_ARM_OFFSET 0x00
77 #define PLL_SYS_OFFSET 0x30
78 #define PLL_USB1_OFFSET 0x10
79 #define PLL_AUDIO_OFFSET 0x70
80 #define PLL_VIDEO_OFFSET 0xA0
81 #define PLL_ENET_OFFSET 0xE0
82 #define PLL_USB2_OFFSET 0x20
83
84 #define CCM_TUPLE(reg, shift, mask, busyShift) \
85 (int)(((reg)&0xFFU) | ((shift) << 8U) | ((((mask) >> (shift)) & 0x1FFFU) << 13U) | ((busyShift) << 26U))
86 #define CCM_TUPLE_REG(base, tuple) (*((volatile uint32_t *)(((uint32_t)(base)) + ((uint32_t)(tuple)&0xFFU))))
87 #define CCM_TUPLE_SHIFT(tuple) ((((uint32_t)tuple) >> 8U) & 0x1FU)
88 #define CCM_TUPLE_MASK(tuple) \
89 ((uint32_t)((((uint32_t)(tuple) >> 13U) & 0x1FFFU) << (((((uint32_t)tuple) >> 8U) & 0x1FU))))
90 #define CCM_TUPLE_BUSY_SHIFT(tuple) ((((uint32_t)tuple) >> 26U) & 0x3FU)
91
92 #define CCM_NO_BUSY_WAIT (0x20U)
93
94 /*!
95 * @brief CCM ANALOG tuple macros to map corresponding registers and bit fields.
96 */
97 #define CCM_ANALOG_TUPLE(reg, shift) ((((reg)&0xFFFU) << 16U) | (shift))
98 #define CCM_ANALOG_TUPLE_SHIFT(tuple) (((uint32_t)tuple) & 0x1FU)
99 #define CCM_ANALOG_TUPLE_REG_OFF(base, tuple, off) \
100 (*((volatile uint32_t *)((uint32_t)(base) + (((uint32_t)(tuple) >> 16U) & 0xFFFU) + (off))))
101 #define CCM_ANALOG_TUPLE_REG(base, tuple) CCM_ANALOG_TUPLE_REG_OFF(base, tuple, 0U)
102
103 /* Definition for ERRATA 50235 check */
104 #if (defined(FSL_FEATURE_CCM_HAS_ERRATA_50235) && FSL_FEATURE_CCM_HAS_ERRATA_50235)
105 #define CAN_CLOCK_CHECK_NO_AFFECTS \
106 ((CCM_CSCMR2_CAN_CLK_SEL(2U) != (CCM->CSCMR2 & CCM_CSCMR2_CAN_CLK_SEL_MASK)) || \
107 (CCM_CCGR5_CG12(0) != (CCM->CCGR5 & CCM_CCGR5_CG12_MASK)))
108 #endif /* FSL_FEATURE_CCM_HAS_ERRATA_50235 */
109
110 /*!
111 * @brief clock1PN frequency.
112 */
113 #define CLKPN_FREQ 0U
114
115 /*! @brief External XTAL (24M OSC/SYSOSC) clock frequency.
116 *
117 * The XTAL (24M OSC/SYSOSC) clock frequency in Hz, when the clock is setup, use the
118 * function CLOCK_SetXtalFreq to set the value in to clock driver. For example,
119 * if XTAL is 24MHz,
120 * @code
121 * CLOCK_InitExternalClk(false);
122 * CLOCK_SetXtalFreq(240000000);
123 * @endcode
124 */
125 extern volatile uint32_t g_xtalFreq;
126
127 /*! @brief External RTC XTAL (32K OSC) clock frequency.
128 *
129 * The RTC XTAL (32K OSC) clock frequency in Hz, when the clock is setup, use the
130 * function CLOCK_SetRtcXtalFreq to set the value in to clock driver.
131 */
132 extern volatile uint32_t g_rtcXtalFreq;
133
134 /* For compatible with other platforms */
135 #define CLOCK_SetXtal0Freq CLOCK_SetXtalFreq
136 #define CLOCK_SetXtal32Freq CLOCK_SetRtcXtalFreq
137
138 /*! @brief Clock ip name array for ADC. */
139 #define ADC_CLOCKS \
140 { \
141 kCLOCK_IpInvalid, kCLOCK_Adc1, kCLOCK_Adc2 \
142 }
143
144 /*! @brief Clock ip name array for AOI. */
145 #define AOI_CLOCKS \
146 { \
147 kCLOCK_IpInvalid, kCLOCK_Aoi1, kCLOCK_Aoi2 \
148 }
149
150 /*! @brief Clock ip name array for BEE. */
151 #define BEE_CLOCKS \
152 { \
153 kCLOCK_Bee \
154 }
155
156 /*! @brief Clock ip name array for CMP. */
157 #define CMP_CLOCKS \
158 { \
159 kCLOCK_IpInvalid, kCLOCK_Acmp1, kCLOCK_Acmp2, kCLOCK_Acmp3, kCLOCK_Acmp4 \
160 }
161
162 /*! @brief Clock ip name array for CSI. */
163 #define CSI_CLOCKS \
164 { \
165 kCLOCK_Csi \
166 }
167
168 /*! @brief Clock ip name array for DCDC. */
169 #define DCDC_CLOCKS \
170 { \
171 kCLOCK_Dcdc \
172 }
173
174 /*! @brief Clock ip name array for DCP. */
175 #define DCP_CLOCKS \
176 { \
177 kCLOCK_Dcp \
178 }
179
180 /*! @brief Clock ip name array for DMAMUX_CLOCKS. */
181 #define DMAMUX_CLOCKS \
182 { \
183 kCLOCK_Dma \
184 }
185
186 /*! @brief Clock ip name array for DMA. */
187 #define EDMA_CLOCKS \
188 { \
189 kCLOCK_Dma \
190 }
191
192 /*! @brief Clock ip name array for ENC. */
193 #define ENC_CLOCKS \
194 { \
195 kCLOCK_IpInvalid, kCLOCK_Enc1, kCLOCK_Enc2, kCLOCK_Enc3, kCLOCK_Enc4 \
196 }
197
198 /*! @brief Clock ip name array for ENET. */
199 #define ENET_CLOCKS \
200 { \
201 kCLOCK_Enet, kCLOCK_IpInvalid, kCLOCK_Enet2 \
202 }
203
204 /*! @brief Clock ip name array for EWM. */
205 #define EWM_CLOCKS \
206 { \
207 kCLOCK_Ewm0 \
208 }
209
210 /*! @brief Clock ip name array for FLEXCAN. */
211 #define FLEXCAN_CLOCKS \
212 { \
213 kCLOCK_IpInvalid, kCLOCK_Can1, kCLOCK_Can2, kCLOCK_Can3 \
214 }
215
216 /*! @brief Clock ip name array for FLEXCAN Peripheral clock. */
217 #define FLEXCAN_PERIPH_CLOCKS \
218 { \
219 kCLOCK_IpInvalid, kCLOCK_Can1S, kCLOCK_Can2S, kCLOCK_Can3S \
220 }
221
222 /*! @brief Clock ip name array for FLEXIO. */
223 #define FLEXIO_CLOCKS \
224 { \
225 kCLOCK_IpInvalid, kCLOCK_Flexio1, kCLOCK_Flexio2, kCLOCK_Flexio3 \
226 }
227
228 /*! @brief Clock ip name array for FLEXRAM. */
229 #define FLEXRAM_CLOCKS \
230 { \
231 kCLOCK_FlexRam \
232 }
233
234 /*! @brief Clock ip name array for FLEXSPI. */
235 #define FLEXSPI_CLOCKS \
236 { \
237 kCLOCK_FlexSpi, kCLOCK_IpInvalid, kCLOCK_FlexSpi2 \
238 }
239
240 /*! @brief Clock ip name array for FLEXSPI EXSC. */
241 #define FLEXSPI_EXSC_CLOCKS \
242 { \
243 kCLOCK_FlexSpiExsc \
244 }
245
246 /*! @brief Clock ip name array for GPIO. */
247 #define GPIO_CLOCKS \
248 { \
249 kCLOCK_IpInvalid, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3, kCLOCK_Gpio4, kCLOCK_Gpio5 \
250 }
251
252 /*! @brief Clock ip name array for GPT. */
253 #define GPT_CLOCKS \
254 { \
255 kCLOCK_IpInvalid, kCLOCK_Gpt1, kCLOCK_Gpt2 \
256 }
257
258 /*! @brief Clock ip name array for KPP. */
259 #define KPP_CLOCKS \
260 { \
261 kCLOCK_Kpp \
262 }
263
264 /*! @brief Clock ip name array for LCDIF. */
265 #define LCDIF_CLOCKS \
266 { \
267 kCLOCK_Lcd \
268 }
269
270 /*! @brief Clock ip name array for LCDIF PIXEL. */
271 #define LCDIF_PERIPH_CLOCKS \
272 { \
273 kCLOCK_LcdPixel \
274 }
275
276 /*! @brief Clock ip name array for LPI2C. */
277 #define LPI2C_CLOCKS \
278 { \
279 kCLOCK_IpInvalid, kCLOCK_Lpi2c1, kCLOCK_Lpi2c2, kCLOCK_Lpi2c3, kCLOCK_Lpi2c4 \
280 }
281
282 /*! @brief Clock ip name array for LPSPI. */
283 #define LPSPI_CLOCKS \
284 { \
285 kCLOCK_IpInvalid, kCLOCK_Lpspi1, kCLOCK_Lpspi2, kCLOCK_Lpspi3, kCLOCK_Lpspi4 \
286 }
287
288 /*! @brief Clock ip name array for LPUART. */
289 #define LPUART_CLOCKS \
290 { \
291 kCLOCK_IpInvalid, kCLOCK_Lpuart1, kCLOCK_Lpuart2, kCLOCK_Lpuart3, kCLOCK_Lpuart4, kCLOCK_Lpuart5, \
292 kCLOCK_Lpuart6, kCLOCK_Lpuart7, kCLOCK_Lpuart8 \
293 }
294
295 /*! @brief Clock ip name array for MQS. */
296 #define MQS_CLOCKS \
297 { \
298 kCLOCK_Mqs \
299 }
300
301 /*! @brief Clock ip name array for OCRAM EXSC. */
302 #define OCRAM_EXSC_CLOCKS \
303 { \
304 kCLOCK_OcramExsc \
305 }
306
307 /*! @brief Clock ip name array for PIT. */
308 #define PIT_CLOCKS \
309 { \
310 kCLOCK_Pit \
311 }
312
313 /*! @brief Clock ip name array for PWM. */
314 #define PWM_CLOCKS \
315 { \
316 {kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid}, \
317 {kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1}, \
318 {kCLOCK_Pwm2, kCLOCK_Pwm2, kCLOCK_Pwm2, kCLOCK_Pwm2}, \
319 {kCLOCK_Pwm3, kCLOCK_Pwm3, kCLOCK_Pwm3, kCLOCK_Pwm3}, \
320 { \
321 kCLOCK_Pwm4, kCLOCK_Pwm4, kCLOCK_Pwm4, kCLOCK_Pwm4 \
322 } \
323 }
324
325 /*! @brief Clock ip name array for PXP. */
326 #define PXP_CLOCKS \
327 { \
328 kCLOCK_Pxp \
329 }
330
331 /*! @brief Clock ip name array for RTWDOG. */
332 #define RTWDOG_CLOCKS \
333 { \
334 kCLOCK_Wdog3 \
335 }
336
337 /*! @brief Clock ip name array for SAI. */
338 #define SAI_CLOCKS \
339 { \
340 kCLOCK_IpInvalid, kCLOCK_Sai1, kCLOCK_Sai2, kCLOCK_Sai3 \
341 }
342
343 /*! @brief Clock ip name array for SEMC. */
344 #define SEMC_CLOCKS \
345 { \
346 kCLOCK_Semc \
347 }
348
349 /*! @brief Clock ip name array for SEMC EXSC. */
350 #define SEMC_EXSC_CLOCKS \
351 { \
352 kCLOCK_SemcExsc \
353 }
354
355 /*! @brief Clock ip name array for QTIMER. */
356 #define TMR_CLOCKS \
357 { \
358 kCLOCK_IpInvalid, kCLOCK_Timer1, kCLOCK_Timer2, kCLOCK_Timer3, kCLOCK_Timer4 \
359 }
360
361 /*! @brief Clock ip name array for TRNG. */
362 #define TRNG_CLOCKS \
363 { \
364 kCLOCK_Trng \
365 }
366
367 /*! @brief Clock ip name array for TSC. */
368 #define TSC_CLOCKS \
369 { \
370 kCLOCK_Tsc \
371 }
372
373 /*! @brief Clock ip name array for WDOG. */
374 #define WDOG_CLOCKS \
375 { \
376 kCLOCK_IpInvalid, kCLOCK_Wdog1, kCLOCK_Wdog2 \
377 }
378
379 /*! @brief Clock ip name array for USDHC. */
380 #define USDHC_CLOCKS \
381 { \
382 kCLOCK_IpInvalid, kCLOCK_Usdhc1, kCLOCK_Usdhc2 \
383 }
384
385 /*! @brief Clock ip name array for SPDIF. */
386 #define SPDIF_CLOCKS \
387 { \
388 kCLOCK_Spdif \
389 }
390
391 /*! @brief Clock ip name array for XBARA. */
392 #define XBARA_CLOCKS \
393 { \
394 kCLOCK_IpInvalid, kCLOCK_Xbar1 \
395 }
396
397 /*! @brief Clock ip name array for XBARB. */
398 #define XBARB_CLOCKS \
399 { \
400 kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_Xbar2, kCLOCK_Xbar3 \
401 }
402
403 #define CLOCK_SOURCE_NONE (0xFFU)
404
405 #define CLOCK_ROOT_SOUCE \
406 { \
407 {kCLOCK_SysPllPfd2Clk, kCLOCK_SysPllPfd0Clk, kCLOCK_NoneName, \
408 kCLOCK_NoneName, kCLOCK_NoneName, kCLOCK_NoneName}, /* USDHC1 Clock Root. */ \
409 {kCLOCK_SysPllPfd2Clk, kCLOCK_SysPllPfd0Clk, kCLOCK_NoneName, \
410 kCLOCK_NoneName, kCLOCK_NoneName, kCLOCK_NoneName}, /* USDHC2 Clock Root. */ \
411 {kCLOCK_SemcClk, kCLOCK_Usb1SwClk, kCLOCK_SysPllPfd2Clk, \
412 kCLOCK_Usb1PllPfd0Clk, kCLOCK_NoneName, kCLOCK_NoneName}, /* FLEXSPI Clock Root. */ \
413 {kCLOCK_SysPllPfd2Clk, kCLOCK_Usb1PllPfd0Clk, kCLOCK_Usb1PllPfd1Clk, \
414 kCLOCK_SysPllClk, kCLOCK_NoneName, kCLOCK_NoneName}, /* FLEXSPI2 Clock Root. */ \
415 {kCLOCK_OscClk, kCLOCK_SysPllPfd2Clk, kCLOCK_Usb1Sw120MClk, \
416 kCLOCK_Usb1PllPfd1Clk, kCLOCK_NoneName, kCLOCK_NoneName}, /* CSI Clock Root. */ \
417 {kCLOCK_Usb1PllPfd1Clk, kCLOCK_Usb1PllPfd0Clk, kCLOCK_SysPllClk, \
418 kCLOCK_SysPllPfd2Clk, kCLOCK_NoneName, kCLOCK_NoneName}, /* LPSPI Clock Root. */ \
419 {kCLOCK_SysPllClk, kCLOCK_SysPllPfd2Clk, kCLOCK_SysPllPfd0Clk, \
420 kCLOCK_SysPllPfd1Clk, kCLOCK_NoneName, kCLOCK_NoneName}, /* TRACE Clock Root */ \
421 {kCLOCK_Usb1PllPfd2Clk, kCLOCK_VideoPllClk, kCLOCK_AudioPllClk, \
422 kCLOCK_NoneName, kCLOCK_NoneName, kCLOCK_NoneName}, /* SAI1 Clock Root */ \
423 {kCLOCK_Usb1PllPfd2Clk, kCLOCK_VideoPllClk, kCLOCK_AudioPllClk, \
424 kCLOCK_NoneName, kCLOCK_NoneName, kCLOCK_NoneName}, /* SAI2 Clock Root */ \
425 {kCLOCK_Usb1PllPfd2Clk, kCLOCK_VideoPllClk, kCLOCK_AudioPllClk, \
426 kCLOCK_NoneName, kCLOCK_NoneName, kCLOCK_NoneName}, /* SAI3 Clock Root */ \
427 {kCLOCK_Usb1Sw60MClk, kCLOCK_OscClk, kCLOCK_NoneName, \
428 kCLOCK_NoneName, kCLOCK_NoneName, kCLOCK_NoneName}, /* LPI2C Clock Root */ \
429 {kCLOCK_Usb1Sw60MClk, kCLOCK_OscClk, kCLOCK_Usb1Sw80MClk, \
430 kCLOCK_NoneName, kCLOCK_NoneName, kCLOCK_NoneName}, /* CAN Clock Root. */ \
431 {kCLOCK_Usb1Sw80MClk, kCLOCK_OscClk, kCLOCK_NoneName, \
432 kCLOCK_NoneName, kCLOCK_NoneName, kCLOCK_NoneName}, /* UART Clock Root */ \
433 {kCLOCK_SysPllClk, kCLOCK_Usb1PllPfd3Clk, kCLOCK_VideoPllClk, \
434 kCLOCK_SysPllPfd0Clk, kCLOCK_SysPllPfd1Clk, kCLOCK_Usb1PllPfd1Clk}, /* LCDIF Clock Root */ \
435 {kCLOCK_AudioPllClk, kCLOCK_Usb1PllPfd2Clk, kCLOCK_VideoPllClk, \
436 kCLOCK_Usb1SwClk, kCLOCK_NoneName, kCLOCK_NoneName}, /* SPDIF0 Clock Root */ \
437 {kCLOCK_AudioPllClk, kCLOCK_Usb1PllPfd2Clk, kCLOCK_VideoPllClk, \
438 kCLOCK_Usb1SwClk, kCLOCK_NoneName, kCLOCK_NoneName}, /* FLEXIO1 Clock Root */ \
439 {kCLOCK_AudioPllClk, kCLOCK_Usb1PllPfd2Clk, kCLOCK_VideoPllClk, \
440 kCLOCK_Usb1PllClk, kCLOCK_NoneName, kCLOCK_NoneName}, /* FLEXIO2 Clock ROOT */ \
441 }
442
443 #define CLOCK_ROOT_MUX_TUPLE \
444 { \
445 kCLOCK_Usdhc1Mux, kCLOCK_Usdhc2Mux, kCLOCK_FlexspiMux, kCLOCK_Flexspi2Mux, kCLOCK_CsiMux, kCLOCK_LpspiMux, \
446 kCLOCK_TraceMux, kCLOCK_Sai1Mux, kCLOCK_Sai2Mux, kCLOCK_Sai3Mux, kCLOCK_Lpi2cMux, kCLOCK_CanMux, \
447 kCLOCK_UartMux, kCLOCK_LcdifPreMux, kCLOCK_SpdifMux, kCLOCK_Flexio1Mux, kCLOCK_Flexio2Mux, \
448 }
449
450 #define CLOCK_ROOT_NONE_PRE_DIV 0UL
451
452 #define CLOCK_ROOT_DIV_TUPLE \
453 { \
454 {kCLOCK_NonePreDiv, kCLOCK_Usdhc1Div}, {kCLOCK_NonePreDiv, kCLOCK_Usdhc2Div}, \
455 {kCLOCK_NonePreDiv, kCLOCK_FlexspiDiv}, {kCLOCK_NonePreDiv, kCLOCK_Flexspi2Div}, \
456 {kCLOCK_NonePreDiv, kCLOCK_CsiDiv}, {kCLOCK_NonePreDiv, kCLOCK_LpspiDiv}, \
457 {kCLOCK_NonePreDiv, kCLOCK_TraceDiv}, {kCLOCK_Sai1PreDiv, kCLOCK_Sai1Div}, \
458 {kCLOCK_Sai2PreDiv, kCLOCK_Sai2Div}, {kCLOCK_Sai3PreDiv, kCLOCK_Sai3Div}, \
459 {kCLOCK_NonePreDiv, kCLOCK_Lpi2cDiv}, {kCLOCK_NonePreDiv, kCLOCK_CanDiv}, \
460 {kCLOCK_NonePreDiv, kCLOCK_UartDiv}, {kCLOCK_LcdifPreDiv, kCLOCK_LcdifDiv}, \
461 {kCLOCK_Spdif0PreDiv, kCLOCK_Spdif0Div}, {kCLOCK_Flexio1PreDiv, kCLOCK_Flexio1Div}, \
462 {kCLOCK_Flexio2PreDiv, kCLOCK_Flexio2Div}, \
463 }
464
465 /*! @brief Clock name used to get clock frequency. */
466 typedef enum _clock_name
467 {
468 kCLOCK_CpuClk = 0x0U, /*!< CPU clock */
469 kCLOCK_AhbClk = 0x1U, /*!< AHB clock */
470 kCLOCK_SemcClk = 0x2U, /*!< SEMC clock */
471 kCLOCK_IpgClk = 0x3U, /*!< IPG clock */
472 kCLOCK_PerClk = 0x4U, /*!< PER clock */
473
474 kCLOCK_OscClk = 0x5U, /*!< OSC clock selected by PMU_LOWPWR_CTRL[OSC_SEL]. */
475 kCLOCK_RtcClk = 0x6U, /*!< RTC clock. (RTCCLK) */
476
477 kCLOCK_ArmPllClk = 0x7U, /*!< ARMPLLCLK. */
478
479 kCLOCK_Usb1PllClk = 0x8U, /*!< USB1PLLCLK. */
480 kCLOCK_Usb1PllPfd0Clk = 0x9U, /*!< USB1PLLPDF0CLK. */
481 kCLOCK_Usb1PllPfd1Clk = 0xAU, /*!< USB1PLLPFD1CLK. */
482 kCLOCK_Usb1PllPfd2Clk = 0xBU, /*!< USB1PLLPFD2CLK. */
483 kCLOCK_Usb1PllPfd3Clk = 0xCU, /*!< USB1PLLPFD3CLK. */
484 kCLOCK_Usb1SwClk = 0x18U, /*!< USB1PLLSWCLK */
485 kCLOCK_Usb1Sw120MClk = 0x19U, /*!< USB1PLLSw120MCLK */
486 kCLOCK_Usb1Sw60MClk = 0x1AU, /*!< USB1PLLSw60MCLK */
487 kCLOCK_Usb1Sw80MClk = 0x1BU, /*!< USB1PLLSw80MCLK */
488
489 kCLOCK_Usb2PllClk = 0xDU, /*!< USB2PLLCLK. */
490
491 kCLOCK_SysPllClk = 0xEU, /*!< SYSPLLCLK. */
492 kCLOCK_SysPllPfd0Clk = 0xFU, /*!< SYSPLLPDF0CLK. */
493 kCLOCK_SysPllPfd1Clk = 0x10U, /*!< SYSPLLPFD1CLK. */
494 kCLOCK_SysPllPfd2Clk = 0x11U, /*!< SYSPLLPFD2CLK. */
495 kCLOCK_SysPllPfd3Clk = 0x12U, /*!< SYSPLLPFD3CLK. */
496
497 kCLOCK_EnetPll0Clk = 0x13U, /*!< Enet PLLCLK ref_enetpll0. */
498 kCLOCK_EnetPll1Clk = 0x14U, /*!< Enet PLLCLK ref_enetpll1. */
499 kCLOCK_EnetPll2Clk = 0x15U, /*!< Enet PLLCLK ref_enetpll2. */
500
501 kCLOCK_AudioPllClk = 0x16U, /*!< Audio PLLCLK. */
502 kCLOCK_VideoPllClk = 0x17U, /*!< Video PLLCLK. */
503
504 kCLOCK_NoneName = CLOCK_SOURCE_NONE, /*!< None Clock Name. */
505 } clock_name_t;
506
507 #define kCLOCK_CoreSysClk kCLOCK_CpuClk /*!< For compatible with other platforms without CCM. */
508 #define CLOCK_GetCoreSysClkFreq CLOCK_GetCpuClkFreq /*!< For compatible with other platforms without CCM. */
509
510 /*!
511 * @brief CCM CCGR gate control for each module independently.
512 */
513 typedef enum _clock_ip_name
514 {
515 kCLOCK_IpInvalid = -1,
516
517 /* CCM CCGR0 */
518 kCLOCK_Aips_tz1 = (0U << 8U) | CCM_CCGR0_CG0_SHIFT, /*!< CCGR0, CG0 */
519 kCLOCK_Aips_tz2 = (0U << 8U) | CCM_CCGR0_CG1_SHIFT, /*!< CCGR0, CG1 */
520 kCLOCK_Mqs = (0U << 8U) | CCM_CCGR0_CG2_SHIFT, /*!< CCGR0, CG2 */
521 kCLOCK_FlexSpiExsc = (0U << 8U) | CCM_CCGR0_CG3_SHIFT, /*!< CCGR0, CG3 */
522 kCLOCK_Sim_M_Main = (0U << 8U) | CCM_CCGR0_CG4_SHIFT, /*!< CCGR0, CG4 */
523 kCLOCK_Dcp = (0U << 8U) | CCM_CCGR0_CG5_SHIFT, /*!< CCGR0, CG5 */
524 kCLOCK_Lpuart3 = (0U << 8U) | CCM_CCGR0_CG6_SHIFT, /*!< CCGR0, CG6 */
525 kCLOCK_Can1 = (0U << 8U) | CCM_CCGR0_CG7_SHIFT, /*!< CCGR0, CG7 */
526 kCLOCK_Can1S = (0U << 8U) | CCM_CCGR0_CG8_SHIFT, /*!< CCGR0, CG8 */
527 kCLOCK_Can2 = (0U << 8U) | CCM_CCGR0_CG9_SHIFT, /*!< CCGR0, CG9 */
528 kCLOCK_Can2S = (0U << 8U) | CCM_CCGR0_CG10_SHIFT, /*!< CCGR0, CG10 */
529 kCLOCK_Trace = (0U << 8U) | CCM_CCGR0_CG11_SHIFT, /*!< CCGR0, CG11 */
530 kCLOCK_Gpt2 = (0U << 8U) | CCM_CCGR0_CG12_SHIFT, /*!< CCGR0, CG12 */
531 kCLOCK_Gpt2S = (0U << 8U) | CCM_CCGR0_CG13_SHIFT, /*!< CCGR0, CG13 */
532 kCLOCK_Lpuart2 = (0U << 8U) | CCM_CCGR0_CG14_SHIFT, /*!< CCGR0, CG14 */
533 kCLOCK_Gpio2 = (0U << 8U) | CCM_CCGR0_CG15_SHIFT, /*!< CCGR0, CG15 */
534
535 /* CCM CCGR1 */
536 kCLOCK_Lpspi1 = (1U << 8U) | CCM_CCGR1_CG0_SHIFT, /*!< CCGR1, CG0 */
537 kCLOCK_Lpspi2 = (1U << 8U) | CCM_CCGR1_CG1_SHIFT, /*!< CCGR1, CG1 */
538 kCLOCK_Lpspi3 = (1U << 8U) | CCM_CCGR1_CG2_SHIFT, /*!< CCGR1, CG2 */
539 kCLOCK_Lpspi4 = (1U << 8U) | CCM_CCGR1_CG3_SHIFT, /*!< CCGR1, CG3 */
540 kCLOCK_Adc2 = (1U << 8U) | CCM_CCGR1_CG4_SHIFT, /*!< CCGR1, CG4 */
541 kCLOCK_Enet = (1U << 8U) | CCM_CCGR1_CG5_SHIFT, /*!< CCGR1, CG5 */
542 kCLOCK_Pit = (1U << 8U) | CCM_CCGR1_CG6_SHIFT, /*!< CCGR1, CG6 */
543 kCLOCK_Aoi2 = (1U << 8U) | CCM_CCGR1_CG7_SHIFT, /*!< CCGR1, CG7 */
544 kCLOCK_Adc1 = (1U << 8U) | CCM_CCGR1_CG8_SHIFT, /*!< CCGR1, CG8 */
545 kCLOCK_SemcExsc = (1U << 8U) | CCM_CCGR1_CG9_SHIFT, /*!< CCGR1, CG9 */
546 kCLOCK_Gpt1 = (1U << 8U) | CCM_CCGR1_CG10_SHIFT, /*!< CCGR1, CG10 */
547 kCLOCK_Gpt1S = (1U << 8U) | CCM_CCGR1_CG11_SHIFT, /*!< CCGR1, CG11 */
548 kCLOCK_Lpuart4 = (1U << 8U) | CCM_CCGR1_CG12_SHIFT, /*!< CCGR1, CG12 */
549 kCLOCK_Gpio1 = (1U << 8U) | CCM_CCGR1_CG13_SHIFT, /*!< CCGR1, CG13 */
550 kCLOCK_Csu = (1U << 8U) | CCM_CCGR1_CG14_SHIFT, /*!< CCGR1, CG14 */
551 kCLOCK_Gpio5 = (1U << 8U) | CCM_CCGR1_CG15_SHIFT, /*!< CCGR1, CG15 */
552
553 /* CCM CCGR2 */
554 kCLOCK_OcramExsc = (2U << 8U) | CCM_CCGR2_CG0_SHIFT, /*!< CCGR2, CG0 */
555 kCLOCK_Csi = (2U << 8U) | CCM_CCGR2_CG1_SHIFT, /*!< CCGR2, CG1 */
556 kCLOCK_IomuxcSnvs = (2U << 8U) | CCM_CCGR2_CG2_SHIFT, /*!< CCGR2, CG2 */
557 kCLOCK_Lpi2c1 = (2U << 8U) | CCM_CCGR2_CG3_SHIFT, /*!< CCGR2, CG3 */
558 kCLOCK_Lpi2c2 = (2U << 8U) | CCM_CCGR2_CG4_SHIFT, /*!< CCGR2, CG4 */
559 kCLOCK_Lpi2c3 = (2U << 8U) | CCM_CCGR2_CG5_SHIFT, /*!< CCGR2, CG5 */
560 kCLOCK_Ocotp = (2U << 8U) | CCM_CCGR2_CG6_SHIFT, /*!< CCGR2, CG6 */
561 kCLOCK_Xbar3 = (2U << 8U) | CCM_CCGR2_CG7_SHIFT, /*!< CCGR2, CG7 */
562 kCLOCK_Ipmux1 = (2U << 8U) | CCM_CCGR2_CG8_SHIFT, /*!< CCGR2, CG8 */
563 kCLOCK_Ipmux2 = (2U << 8U) | CCM_CCGR2_CG9_SHIFT, /*!< CCGR2, CG9 */
564 kCLOCK_Ipmux3 = (2U << 8U) | CCM_CCGR2_CG10_SHIFT, /*!< CCGR2, CG10 */
565 kCLOCK_Xbar1 = (2U << 8U) | CCM_CCGR2_CG11_SHIFT, /*!< CCGR2, CG11 */
566 kCLOCK_Xbar2 = (2U << 8U) | CCM_CCGR2_CG12_SHIFT, /*!< CCGR2, CG12 */
567 kCLOCK_Gpio3 = (2U << 8U) | CCM_CCGR2_CG13_SHIFT, /*!< CCGR2, CG13 */
568 kCLOCK_Lcd = (2U << 8U) | CCM_CCGR2_CG14_SHIFT, /*!< CCGR2, CG14 */
569 kCLOCK_Pxp = (2U << 8U) | CCM_CCGR2_CG15_SHIFT, /*!< CCGR2, CG15 */
570
571 /* CCM CCGR3 */
572 kCLOCK_Flexio2 = (3U << 8U) | CCM_CCGR3_CG0_SHIFT, /*!< CCGR3, CG0 */
573 kCLOCK_Lpuart5 = (3U << 8U) | CCM_CCGR3_CG1_SHIFT, /*!< CCGR3, CG1 */
574 kCLOCK_Semc = (3U << 8U) | CCM_CCGR3_CG2_SHIFT, /*!< CCGR3, CG2 */
575 kCLOCK_Lpuart6 = (3U << 8U) | CCM_CCGR3_CG3_SHIFT, /*!< CCGR3, CG3 */
576 kCLOCK_Aoi1 = (3U << 8U) | CCM_CCGR3_CG4_SHIFT, /*!< CCGR3, CG4 */
577 kCLOCK_LcdPixel = (3U << 8U) | CCM_CCGR3_CG5_SHIFT, /*!< CCGR3, CG5 */
578 kCLOCK_Gpio4 = (3U << 8U) | CCM_CCGR3_CG6_SHIFT, /*!< CCGR3, CG6 */
579 kCLOCK_Ewm0 = (3U << 8U) | CCM_CCGR3_CG7_SHIFT, /*!< CCGR3, CG7 */
580 kCLOCK_Wdog1 = (3U << 8U) | CCM_CCGR3_CG8_SHIFT, /*!< CCGR3, CG8 */
581 kCLOCK_FlexRam = (3U << 8U) | CCM_CCGR3_CG9_SHIFT, /*!< CCGR3, CG9 */
582 kCLOCK_Acmp1 = (3U << 8U) | CCM_CCGR3_CG10_SHIFT, /*!< CCGR3, CG10 */
583 kCLOCK_Acmp2 = (3U << 8U) | CCM_CCGR3_CG11_SHIFT, /*!< CCGR3, CG11 */
584 kCLOCK_Acmp3 = (3U << 8U) | CCM_CCGR3_CG12_SHIFT, /*!< CCGR3, CG12 */
585 kCLOCK_Acmp4 = (3U << 8U) | CCM_CCGR3_CG13_SHIFT, /*!< CCGR3, CG13 */
586 kCLOCK_Ocram = (3U << 8U) | CCM_CCGR3_CG14_SHIFT, /*!< CCGR3, CG14 */
587 kCLOCK_IomuxcSnvsGpr = (3U << 8U) | CCM_CCGR3_CG15_SHIFT, /*!< CCGR3, CG15 */
588
589 /* CCM CCGR4 */
590 kCLOCK_Iomuxc = (4U << 8U) | CCM_CCGR4_CG1_SHIFT, /*!< CCGR4, CG1 */
591 kCLOCK_IomuxcGpr = (4U << 8U) | CCM_CCGR4_CG2_SHIFT, /*!< CCGR4, CG2 */
592 kCLOCK_Bee = (4U << 8U) | CCM_CCGR4_CG3_SHIFT, /*!< CCGR4, CG3 */
593 kCLOCK_SimM7 = (4U << 8U) | CCM_CCGR4_CG4_SHIFT, /*!< CCGR4, CG4 */
594 kCLOCK_Tsc = (4U << 8U) | CCM_CCGR4_CG5_SHIFT, /*!< CCGR4, CG5 */
595 kCLOCK_SimM = (4U << 8U) | CCM_CCGR4_CG6_SHIFT, /*!< CCGR4, CG6 */
596 kCLOCK_SimEms = (4U << 8U) | CCM_CCGR4_CG7_SHIFT, /*!< CCGR4, CG7 */
597 kCLOCK_Pwm1 = (4U << 8U) | CCM_CCGR4_CG8_SHIFT, /*!< CCGR4, CG8 */
598 kCLOCK_Pwm2 = (4U << 8U) | CCM_CCGR4_CG9_SHIFT, /*!< CCGR4, CG9 */
599 kCLOCK_Pwm3 = (4U << 8U) | CCM_CCGR4_CG10_SHIFT, /*!< CCGR4, CG10 */
600 kCLOCK_Pwm4 = (4U << 8U) | CCM_CCGR4_CG11_SHIFT, /*!< CCGR4, CG11 */
601 kCLOCK_Enc1 = (4U << 8U) | CCM_CCGR4_CG12_SHIFT, /*!< CCGR4, CG12 */
602 kCLOCK_Enc2 = (4U << 8U) | CCM_CCGR4_CG13_SHIFT, /*!< CCGR4, CG13 */
603 kCLOCK_Enc3 = (4U << 8U) | CCM_CCGR4_CG14_SHIFT, /*!< CCGR4, CG14 */
604 kCLOCK_Enc4 = (4U << 8U) | CCM_CCGR4_CG15_SHIFT, /*!< CCGR4, CG15 */
605
606 /* CCM CCGR5 */
607 kCLOCK_Rom = (5U << 8U) | CCM_CCGR5_CG0_SHIFT, /*!< CCGR5, CG0 */
608 kCLOCK_Flexio1 = (5U << 8U) | CCM_CCGR5_CG1_SHIFT, /*!< CCGR5, CG1 */
609 kCLOCK_Wdog3 = (5U << 8U) | CCM_CCGR5_CG2_SHIFT, /*!< CCGR5, CG2 */
610 kCLOCK_Dma = (5U << 8U) | CCM_CCGR5_CG3_SHIFT, /*!< CCGR5, CG3 */
611 kCLOCK_Kpp = (5U << 8U) | CCM_CCGR5_CG4_SHIFT, /*!< CCGR5, CG4 */
612 kCLOCK_Wdog2 = (5U << 8U) | CCM_CCGR5_CG5_SHIFT, /*!< CCGR5, CG5 */
613 kCLOCK_Aips_tz4 = (5U << 8U) | CCM_CCGR5_CG6_SHIFT, /*!< CCGR5, CG6 */
614 kCLOCK_Spdif = (5U << 8U) | CCM_CCGR5_CG7_SHIFT, /*!< CCGR5, CG7 */
615 kCLOCK_SimMain = (5U << 8U) | CCM_CCGR5_CG8_SHIFT, /*!< CCGR5, CG8 */
616 kCLOCK_Sai1 = (5U << 8U) | CCM_CCGR5_CG9_SHIFT, /*!< CCGR5, CG9 */
617 kCLOCK_Sai2 = (5U << 8U) | CCM_CCGR5_CG10_SHIFT, /*!< CCGR5, CG10 */
618 kCLOCK_Sai3 = (5U << 8U) | CCM_CCGR5_CG11_SHIFT, /*!< CCGR5, CG11 */
619 kCLOCK_Lpuart1 = (5U << 8U) | CCM_CCGR5_CG12_SHIFT, /*!< CCGR5, CG12 */
620 kCLOCK_Lpuart7 = (5U << 8U) | CCM_CCGR5_CG13_SHIFT, /*!< CCGR5, CG13 */
621 kCLOCK_SnvsHp = (5U << 8U) | CCM_CCGR5_CG14_SHIFT, /*!< CCGR5, CG14 */
622 kCLOCK_SnvsLp = (5U << 8U) | CCM_CCGR5_CG15_SHIFT, /*!< CCGR5, CG15 */
623
624 /* CCM CCGR6 */
625 kCLOCK_UsbOh3 = (6U << 8U) | CCM_CCGR6_CG0_SHIFT, /*!< CCGR6, CG0 */
626 kCLOCK_Usdhc1 = (6U << 8U) | CCM_CCGR6_CG1_SHIFT, /*!< CCGR6, CG1 */
627 kCLOCK_Usdhc2 = (6U << 8U) | CCM_CCGR6_CG2_SHIFT, /*!< CCGR6, CG2 */
628 kCLOCK_Dcdc = (6U << 8U) | CCM_CCGR6_CG3_SHIFT, /*!< CCGR6, CG3 */
629 kCLOCK_Ipmux4 = (6U << 8U) | CCM_CCGR6_CG4_SHIFT, /*!< CCGR6, CG4 */
630 kCLOCK_FlexSpi = (6U << 8U) | CCM_CCGR6_CG5_SHIFT, /*!< CCGR6, CG5 */
631 kCLOCK_Trng = (6U << 8U) | CCM_CCGR6_CG6_SHIFT, /*!< CCGR6, CG6 */
632 kCLOCK_Lpuart8 = (6U << 8U) | CCM_CCGR6_CG7_SHIFT, /*!< CCGR6, CG7 */
633 kCLOCK_Timer4 = (6U << 8U) | CCM_CCGR6_CG8_SHIFT, /*!< CCGR6, CG8 */
634 kCLOCK_Aips_tz3 = (6U << 8U) | CCM_CCGR6_CG9_SHIFT, /*!< CCGR6, CG9 */
635 kCLOCK_SimPer = (6U << 8U) | CCM_CCGR6_CG10_SHIFT, /*!< CCGR6, CG10 */
636 kCLOCK_Anadig = (6U << 8U) | CCM_CCGR6_CG11_SHIFT, /*!< CCGR6, CG11 */
637 kCLOCK_Lpi2c4 = (6U << 8U) | CCM_CCGR6_CG12_SHIFT, /*!< CCGR6, CG12 */
638 kCLOCK_Timer1 = (6U << 8U) | CCM_CCGR6_CG13_SHIFT, /*!< CCGR6, CG13 */
639 kCLOCK_Timer2 = (6U << 8U) | CCM_CCGR6_CG14_SHIFT, /*!< CCGR6, CG14 */
640 kCLOCK_Timer3 = (6U << 8U) | CCM_CCGR6_CG15_SHIFT, /*!< CCGR6, CG15 */
641
642 /* CCM CCGR7 */
643 kCLOCK_Enet2 = (7U << 8U) | CCM_CCGR7_CG0_SHIFT, /*!< CCGR7, CG0 */
644 kCLOCK_FlexSpi2 = (7U << 8U) | CCM_CCGR7_CG1_SHIFT, /*!< CCGR7, CG1 */
645 kCLOCK_Axbs_l = (7U << 8U) | CCM_CCGR7_CG2_SHIFT, /*!< CCGR7, CG2 */
646 kCLOCK_Can3 = (7U << 8U) | CCM_CCGR7_CG3_SHIFT, /*!< CCGR7, CG3 */
647 kCLOCK_Can3S = (7U << 8U) | CCM_CCGR7_CG4_SHIFT, /*!< CCGR7, CG4 */
648 kCLOCK_Aips_lite = (7U << 8U) | CCM_CCGR7_CG5_SHIFT, /*!< CCGR7, CG5 */
649 kCLOCK_Flexio3 = (7U << 8U) | CCM_CCGR7_CG6_SHIFT, /*!< CCGR7, CG6 */
650
651 } clock_ip_name_t;
652
653 /*! @brief OSC 24M sorce select */
654 typedef enum _clock_osc
655 {
656 kCLOCK_RcOsc = 0U, /*!< On chip OSC. */
657 kCLOCK_XtalOsc = 1U, /*!< 24M Xtal OSC */
658 } clock_osc_t;
659
660 /*! @brief Clock gate value */
661 typedef enum _clock_gate_value
662 {
663 kCLOCK_ClockNotNeeded = 0U, /*!< Clock is off during all modes. */
664 kCLOCK_ClockNeededRun = 1U, /*!< Clock is on in run mode, but off in WAIT and STOP modes */
665 kCLOCK_ClockNeededRunWait = 3U, /*!< Clock is on during all modes, except STOP mode */
666 } clock_gate_value_t;
667
668 /*! @brief System clock mode */
669 typedef enum _clock_mode_t
670 {
671 kCLOCK_ModeRun = 0U, /*!< Remain in run mode. */
672 kCLOCK_ModeWait = 1U, /*!< Transfer to wait mode. */
673 kCLOCK_ModeStop = 2U, /*!< Transfer to stop mode. */
674 } clock_mode_t;
675
676 /*!
677 * @brief MUX control names for clock mux setting.
678 *
679 * These constants define the mux control names for clock mux setting.\n
680 * - 0:7: REG offset to CCM_BASE in bytes.
681 * - 8:15: Root clock setting bit field shift.
682 * - 16:31: Root clock setting bit field width.
683 */
684 typedef enum _clock_mux
685 {
686 kCLOCK_Pll3SwMux = CCM_TUPLE(CCSR_OFFSET,
687 CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT,
688 CCM_CCSR_PLL3_SW_CLK_SEL_MASK,
689 CCM_NO_BUSY_WAIT), /*!< pll3_sw_clk mux name */
690
691 kCLOCK_PeriphMux = CCM_TUPLE(CBCDR_OFFSET,
692 CCM_CBCDR_PERIPH_CLK_SEL_SHIFT,
693 CCM_CBCDR_PERIPH_CLK_SEL_MASK,
694 CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT), /*!< periph mux name */
695 kCLOCK_SemcAltMux = CCM_TUPLE(CBCDR_OFFSET,
696 CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT,
697 CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK,
698 CCM_NO_BUSY_WAIT), /*!< semc mux name */
699 kCLOCK_SemcMux = CCM_TUPLE(CBCDR_OFFSET,
700 CCM_CBCDR_SEMC_CLK_SEL_SHIFT,
701 CCM_CBCDR_SEMC_CLK_SEL_MASK,
702 CCM_NO_BUSY_WAIT), /*!< semc mux name */
703
704 kCLOCK_PrePeriphMux = CCM_TUPLE(CBCMR_OFFSET,
705 CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT,
706 CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK,
707 CCM_NO_BUSY_WAIT), /*!< pre-periph mux name */
708 kCLOCK_TraceMux = CCM_TUPLE(CBCMR_OFFSET,
709 CCM_CBCMR_TRACE_CLK_SEL_SHIFT,
710 CCM_CBCMR_TRACE_CLK_SEL_MASK,
711 CCM_NO_BUSY_WAIT), /*!< trace mux name */
712 kCLOCK_PeriphClk2Mux = CCM_TUPLE(CBCMR_OFFSET,
713 CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT,
714 CCM_CBCMR_PERIPH_CLK2_SEL_MASK,
715 CCM_NO_BUSY_WAIT), /*!< periph clock2 mux name */
716 kCLOCK_Flexspi2Mux = CCM_TUPLE(CBCMR_OFFSET,
717 CCM_CBCMR_FLEXSPI2_CLK_SEL_SHIFT,
718 CCM_CBCMR_FLEXSPI2_CLK_SEL_MASK,
719 CCM_NO_BUSY_WAIT), /*!< flexspi2 mux name */
720 kCLOCK_LpspiMux = CCM_TUPLE(CBCMR_OFFSET,
721 CCM_CBCMR_LPSPI_CLK_SEL_SHIFT,
722 CCM_CBCMR_LPSPI_CLK_SEL_MASK,
723 CCM_NO_BUSY_WAIT), /*!< lpspi mux name */
724
725 kCLOCK_FlexspiMux = CCM_TUPLE(CSCMR1_OFFSET,
726 CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT,
727 CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK,
728 CCM_NO_BUSY_WAIT), /*!< flexspi mux name */
729 kCLOCK_Usdhc2Mux = CCM_TUPLE(CSCMR1_OFFSET,
730 CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT,
731 CCM_CSCMR1_USDHC2_CLK_SEL_MASK,
732 CCM_NO_BUSY_WAIT), /*!< usdhc2 mux name */
733 kCLOCK_Usdhc1Mux = CCM_TUPLE(CSCMR1_OFFSET,
734 CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT,
735 CCM_CSCMR1_USDHC1_CLK_SEL_MASK,
736 CCM_NO_BUSY_WAIT), /*!< usdhc1 mux name */
737 kCLOCK_Sai3Mux = CCM_TUPLE(CSCMR1_OFFSET,
738 CCM_CSCMR1_SAI3_CLK_SEL_SHIFT,
739 CCM_CSCMR1_SAI3_CLK_SEL_MASK,
740 CCM_NO_BUSY_WAIT), /*!< sai3 mux name */
741 kCLOCK_Sai2Mux = CCM_TUPLE(CSCMR1_OFFSET,
742 CCM_CSCMR1_SAI2_CLK_SEL_SHIFT,
743 CCM_CSCMR1_SAI2_CLK_SEL_MASK,
744 CCM_NO_BUSY_WAIT), /*!< sai2 mux name */
745 kCLOCK_Sai1Mux = CCM_TUPLE(CSCMR1_OFFSET,
746 CCM_CSCMR1_SAI1_CLK_SEL_SHIFT,
747 CCM_CSCMR1_SAI1_CLK_SEL_MASK,
748 CCM_NO_BUSY_WAIT), /*!< sai1 mux name */
749 kCLOCK_PerclkMux = CCM_TUPLE(CSCMR1_OFFSET,
750 CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT,
751 CCM_CSCMR1_PERCLK_CLK_SEL_MASK,
752 CCM_NO_BUSY_WAIT), /*!< perclk mux name */
753
754 kCLOCK_Flexio2Mux = CCM_TUPLE(CSCMR2_OFFSET,
755 CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT,
756 CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK,
757 CCM_NO_BUSY_WAIT), /*!< flexio2 mux name */
758 kCLOCK_CanMux = CCM_TUPLE(CSCMR2_OFFSET,
759 CCM_CSCMR2_CAN_CLK_SEL_SHIFT,
760 CCM_CSCMR2_CAN_CLK_SEL_MASK,
761 CCM_NO_BUSY_WAIT), /*!< can mux name */
762
763 kCLOCK_UartMux = CCM_TUPLE(CSCDR1_OFFSET,
764 CCM_CSCDR1_UART_CLK_SEL_SHIFT,
765 CCM_CSCDR1_UART_CLK_SEL_MASK,
766 CCM_NO_BUSY_WAIT), /*!< uart mux name */
767
768 kCLOCK_SpdifMux = CCM_TUPLE(CDCDR_OFFSET,
769 CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT,
770 CCM_CDCDR_SPDIF0_CLK_SEL_MASK,
771 CCM_NO_BUSY_WAIT), /*!< spdif mux name */
772 kCLOCK_Flexio1Mux = CCM_TUPLE(CDCDR_OFFSET,
773 CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT,
774 CCM_CDCDR_FLEXIO1_CLK_SEL_MASK,
775 CCM_NO_BUSY_WAIT), /*!< flexio1 mux name */
776
777 kCLOCK_Lpi2cMux = CCM_TUPLE(CSCDR2_OFFSET,
778 CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT,
779 CCM_CSCDR2_LPI2C_CLK_SEL_MASK,
780 CCM_NO_BUSY_WAIT), /*!< lpi2c mux name */
781 kCLOCK_LcdifPreMux = CCM_TUPLE(CSCDR2_OFFSET,
782 CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT,
783 CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK,
784 CCM_NO_BUSY_WAIT), /*!< lcdif pre mux name */
785
786 kCLOCK_CsiMux = CCM_TUPLE(CSCDR3_OFFSET,
787 CCM_CSCDR3_CSI_CLK_SEL_SHIFT,
788 CCM_CSCDR3_CSI_CLK_SEL_MASK,
789 CCM_NO_BUSY_WAIT), /*!< csi mux name */
790 } clock_mux_t;
791
792 /*!
793 * @brief DIV control names for clock div setting.
794 *
795 * These constants define div control names for clock div setting.\n
796 * - 0:7: REG offset to CCM_BASE in bytes.
797 * - 8:15: Root clock setting bit field shift.
798 * - 16:31: Root clock setting bit field width.
799 */
800 typedef enum _clock_div
801 {
802 kCLOCK_ArmDiv = CCM_TUPLE(CACRR_OFFSET,
803 CCM_CACRR_ARM_PODF_SHIFT,
804 CCM_CACRR_ARM_PODF_MASK,
805 CCM_CDHIPR_ARM_PODF_BUSY_SHIFT), /*!< core div name */
806
807 kCLOCK_PeriphClk2Div = CCM_TUPLE(CBCDR_OFFSET,
808 CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT,
809 CCM_CBCDR_PERIPH_CLK2_PODF_MASK,
810 CCM_NO_BUSY_WAIT), /*!< periph clock2 div name */
811 kCLOCK_SemcDiv = CCM_TUPLE(CBCDR_OFFSET,
812 CCM_CBCDR_SEMC_PODF_SHIFT,
813 CCM_CBCDR_SEMC_PODF_MASK,
814 CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT), /*!< semc div name */
815 kCLOCK_AhbDiv = CCM_TUPLE(CBCDR_OFFSET,
816 CCM_CBCDR_AHB_PODF_SHIFT,
817 CCM_CBCDR_AHB_PODF_MASK,
818 CCM_CDHIPR_AHB_PODF_BUSY_SHIFT), /*!< ahb div name */
819 kCLOCK_IpgDiv = CCM_TUPLE(
820 CBCDR_OFFSET, CCM_CBCDR_IPG_PODF_SHIFT, CCM_CBCDR_IPG_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< ipg div name */
821
822 kCLOCK_Flexspi2Div = CCM_TUPLE(CBCMR_OFFSET,
823 CCM_CBCMR_FLEXSPI2_PODF_SHIFT,
824 CCM_CBCMR_FLEXSPI2_PODF_MASK,
825 CCM_NO_BUSY_WAIT), /*!< flexspi2 div name */
826 kCLOCK_LpspiDiv = CCM_TUPLE(
827 CBCMR_OFFSET, CCM_CBCMR_LPSPI_PODF_SHIFT, CCM_CBCMR_LPSPI_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< lpspi div name */
828 kCLOCK_LcdifDiv = CCM_TUPLE(
829 CBCMR_OFFSET, CCM_CBCMR_LCDIF_PODF_SHIFT, CCM_CBCMR_LCDIF_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< lcdif div name */
830
831 kCLOCK_FlexspiDiv = CCM_TUPLE(CSCMR1_OFFSET,
832 CCM_CSCMR1_FLEXSPI_PODF_SHIFT,
833 CCM_CSCMR1_FLEXSPI_PODF_MASK,
834 CCM_NO_BUSY_WAIT), /*!< flexspi div name */
835 kCLOCK_PerclkDiv = CCM_TUPLE(CSCMR1_OFFSET,
836 CCM_CSCMR1_PERCLK_PODF_SHIFT,
837 CCM_CSCMR1_PERCLK_PODF_MASK,
838 CCM_NO_BUSY_WAIT), /*!< perclk div name */
839
840 kCLOCK_CanDiv = CCM_TUPLE(CSCMR2_OFFSET,
841 CCM_CSCMR2_CAN_CLK_PODF_SHIFT,
842 CCM_CSCMR2_CAN_CLK_PODF_MASK,
843 CCM_NO_BUSY_WAIT), /*!< can div name */
844
845 kCLOCK_TraceDiv = CCM_TUPLE(CSCDR1_OFFSET,
846 CCM_CSCDR1_TRACE_PODF_SHIFT,
847 CCM_CSCDR1_TRACE_PODF_MASK,
848 CCM_NO_BUSY_WAIT), /*!< trace div name */
849 kCLOCK_Usdhc2Div = CCM_TUPLE(CSCDR1_OFFSET,
850 CCM_CSCDR1_USDHC2_PODF_SHIFT,
851 CCM_CSCDR1_USDHC2_PODF_MASK,
852 CCM_NO_BUSY_WAIT), /*!< usdhc2 div name */
853 kCLOCK_Usdhc1Div = CCM_TUPLE(CSCDR1_OFFSET,
854 CCM_CSCDR1_USDHC1_PODF_SHIFT,
855 CCM_CSCDR1_USDHC1_PODF_MASK,
856 CCM_NO_BUSY_WAIT), /*!< usdhc1 div name */
857 kCLOCK_UartDiv = CCM_TUPLE(CSCDR1_OFFSET,
858 CCM_CSCDR1_UART_CLK_PODF_SHIFT,
859 CCM_CSCDR1_UART_CLK_PODF_MASK,
860 CCM_NO_BUSY_WAIT), /*!< uart div name */
861
862 kCLOCK_Flexio2Div = CCM_TUPLE(CS1CDR_OFFSET,
863 CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT,
864 CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK,
865 CCM_NO_BUSY_WAIT), /*!< flexio2 pre div name */
866 kCLOCK_Sai3PreDiv = CCM_TUPLE(CS1CDR_OFFSET,
867 CCM_CS1CDR_SAI3_CLK_PRED_SHIFT,
868 CCM_CS1CDR_SAI3_CLK_PRED_MASK,
869 CCM_NO_BUSY_WAIT), /*!< sai3 pre div name */
870 kCLOCK_Sai3Div = CCM_TUPLE(CS1CDR_OFFSET,
871 CCM_CS1CDR_SAI3_CLK_PODF_SHIFT,
872 CCM_CS1CDR_SAI3_CLK_PODF_MASK,
873 CCM_NO_BUSY_WAIT), /*!< sai3 div name */
874 kCLOCK_Flexio2PreDiv = CCM_TUPLE(CS1CDR_OFFSET,
875 CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT,
876 CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK,
877 CCM_NO_BUSY_WAIT), /*!< sai3 pre div name */
878 kCLOCK_Sai1PreDiv = CCM_TUPLE(CS1CDR_OFFSET,
879 CCM_CS1CDR_SAI1_CLK_PRED_SHIFT,
880 CCM_CS1CDR_SAI1_CLK_PRED_MASK,
881 CCM_NO_BUSY_WAIT), /*!< sai1 pre div name */
882 kCLOCK_Sai1Div = CCM_TUPLE(CS1CDR_OFFSET,
883 CCM_CS1CDR_SAI1_CLK_PODF_SHIFT,
884 CCM_CS1CDR_SAI1_CLK_PODF_MASK,
885 CCM_NO_BUSY_WAIT), /*!< sai1 div name */
886
887 kCLOCK_Sai2PreDiv = CCM_TUPLE(CS2CDR_OFFSET,
888 CCM_CS2CDR_SAI2_CLK_PRED_SHIFT,
889 CCM_CS2CDR_SAI2_CLK_PRED_MASK,
890 CCM_NO_BUSY_WAIT), /*!< sai2 pre div name */
891 kCLOCK_Sai2Div = CCM_TUPLE(CS2CDR_OFFSET,
892 CCM_CS2CDR_SAI2_CLK_PODF_SHIFT,
893 CCM_CS2CDR_SAI2_CLK_PODF_MASK,
894 CCM_NO_BUSY_WAIT), /*!< sai2 div name */
895
896 kCLOCK_Spdif0PreDiv = CCM_TUPLE(CDCDR_OFFSET,
897 CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT,
898 CCM_CDCDR_SPDIF0_CLK_PRED_MASK,
899 CCM_NO_BUSY_WAIT), /*!< spdif pre div name */
900 kCLOCK_Spdif0Div = CCM_TUPLE(CDCDR_OFFSET,
901 CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT,
902 CCM_CDCDR_SPDIF0_CLK_PODF_MASK,
903 CCM_NO_BUSY_WAIT), /*!< spdif div name */
904 kCLOCK_Flexio1PreDiv = CCM_TUPLE(CDCDR_OFFSET,
905 CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT,
906 CCM_CDCDR_FLEXIO1_CLK_PRED_MASK,
907 CCM_NO_BUSY_WAIT), /*!< flexio1 pre div name */
908 kCLOCK_Flexio1Div = CCM_TUPLE(CDCDR_OFFSET,
909 CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT,
910 CCM_CDCDR_FLEXIO1_CLK_PODF_MASK,
911 CCM_NO_BUSY_WAIT), /*!< flexio1 div name */
912
913 kCLOCK_Lpi2cDiv = CCM_TUPLE(CSCDR2_OFFSET,
914 CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT,
915 CCM_CSCDR2_LPI2C_CLK_PODF_MASK,
916 CCM_NO_BUSY_WAIT), /*!< lpi2c div name */
917 kCLOCK_LcdifPreDiv = CCM_TUPLE(CSCDR2_OFFSET,
918 CCM_CSCDR2_LCDIF_PRED_SHIFT,
919 CCM_CSCDR2_LCDIF_PRED_MASK,
920 CCM_NO_BUSY_WAIT), /*!< lcdif pre div name */
921
922 kCLOCK_CsiDiv = CCM_TUPLE(
923 CSCDR3_OFFSET, CCM_CSCDR3_CSI_PODF_SHIFT, CCM_CSCDR3_CSI_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< csi div name */
924
925 kCLOCK_NonePreDiv = CLOCK_ROOT_NONE_PRE_DIV, /*!< None Pre div. */
926 } clock_div_t;
927
928 /*!
929 * @brief Clock divider value.
930 */
931 typedef enum
932 {
933 kCLOCK_ArmDivBy1 = 0, /*!< ARM clock divider set to divided by 1. */
934 kCLOCK_ArmDivBy2 = 1, /*!< ARM clock divider set to divided by 2. */
935 kCLOCK_ArmDivBy3 = 2, /*!< ARM clock divider set to divided by 3. */
936 kCLOCK_ArmDivBy4 = 3, /*!< ARM clock divider set to divided by 4. */
937 kCLOCK_ArmDivBy5 = 4, /*!< ARM clock divider set to divided by 5. */
938 kCLOCK_ArmDivBy6 = 5, /*!< ARM clock divider set to divided by 6. */
939 kCLOCK_ArmDivBy7 = 6, /*!< ARM clock divider set to divided by 7. */
940 kCLOCK_ArmDivBy8 = 7, /*!< ARM clock divider set to divided by 8. */
941
942 kCLOCK_PeriphClk2DivBy1 = 0, /*!< PeriphClk2 divider set to divided by 1. */
943 kCLOCK_PeriphClk2DivBy2 = 1, /*!< PeriphClk2 divider set to divided by 2. */
944 kCLOCK_PeriphClk2DivBy3 = 2, /*!< PeriphClk2 divider set to divided by 3. */
945 kCLOCK_PeriphClk2DivBy4 = 3, /*!< PeriphClk2 divider set to divided by 4. */
946 kCLOCK_PeriphClk2DivBy5 = 4, /*!< PeriphClk2 divider set to divided by 5. */
947 kCLOCK_PeriphClk2DivBy6 = 5, /*!< PeriphClk2 divider set to divided by 6. */
948 kCLOCK_PeriphClk2DivBy7 = 6, /*!< PeriphClk2 divider set to divided by 7. */
949 kCLOCK_PeriphClk2DivBy8 = 7, /*!< PeriphClk2 divider set to divided by 8. */
950
951 kCLOCK_SemcDivBy1 = 0, /*!< SEMC clock divider set to divided by 1. */
952 kCLOCK_SemcDivBy2 = 1, /*!< SEMC clock divider set to divided by 2. */
953 kCLOCK_SemcDivBy3 = 2, /*!< SEMC clock divider set to divided by 3. */
954 kCLOCK_SemcDivBy4 = 3, /*!< SEMC clock divider set to divided by 4. */
955 kCLOCK_SemcDivBy5 = 4, /*!< SEMC clock divider set to divided by 5. */
956 kCLOCK_SemcDivBy6 = 5, /*!< SEMC clock divider set to divided by 6. */
957 kCLOCK_SemcDivBy7 = 6, /*!< SEMC clock divider set to divided by 7. */
958 kCLOCK_SemcDivBy8 = 7, /*!< SEMC clock divider set to divided by 8. */
959
960 kCLOCK_AhbDivBy1 = 0, /*!< AHB clock divider set to divided by 1. */
961 kCLOCK_AhbDivBy2 = 1, /*!< AHB clock divider set to divided by 2. */
962 kCLOCK_AhbDivBy3 = 2, /*!< AHB clock divider set to divided by 3. */
963 kCLOCK_AhbDivBy4 = 3, /*!< AHB clock divider set to divided by 4. */
964 kCLOCK_AhbDivBy5 = 4, /*!< AHB clock divider set to divided by 5. */
965 kCLOCK_AhbDivBy6 = 5, /*!< AHB clock divider set to divided by 6. */
966 kCLOCK_AhbDivBy7 = 6, /*!< AHB clock divider set to divided by 7. */
967 kCLOCK_AhbDivBy8 = 7, /*!< AHB clock divider set to divided by 8. */
968
969 kCLOCK_IpgDivBy1 = 0, /*!< IPG clock divider set to divided by 1. */
970 kCLOCK_IpgDivBy2 = 1, /*!< IPG clock divider set to divided by 2. */
971 kCLOCK_IpgDivBy3 = 2, /*!< IPG clock divider set to divided by 3. */
972 kCLOCK_IpgDivBy4 = 3, /*!< IPG clock divider set to divided by 4. */
973
974 kCLOCK_Flexspi2DivBy1 = 0, /*!< Flexspi2 divider set to divided by 1. */
975 kCLOCK_Flexspi2DivBy2 = 1, /*!< Flexspi2 divider set to divided by 2. */
976 kCLOCK_Flexspi2DivBy3 = 2, /*!< Flexspi2 divider set to divided by 3. */
977 kCLOCK_Flexspi2DivBy4 = 3, /*!< Flexspi2 divider set to divided by 4. */
978 kCLOCK_Flexspi2DivBy5 = 4, /*!< Flexspi2 divider set to divided by 5. */
979 kCLOCK_Flexspi2DivBy6 = 5, /*!< Flexspi2 divider set to divided by 6. */
980 kCLOCK_Flexspi2DivBy7 = 6, /*!< Flexspi2 divider set to divided by 7. */
981 kCLOCK_Flexspi2DivBy8 = 7, /*!< Flexspi2 divider set to divided by 8. */
982
983 kCLOCK_LpspiDivBy1 = 0, /*!< Lpspi divider set to divided by 1. */
984 kCLOCK_LpspiDivBy2 = 1, /*!< Lpspi divider set to divided by 2. */
985 kCLOCK_LpspiDivBy3 = 2, /*!< Lpspi divider set to divided by 3. */
986 kCLOCK_LpspiDivBy4 = 3, /*!< Lpspi divider set to divided by 4. */
987 kCLOCK_LpspiDivBy5 = 4, /*!< Lpspi divider set to divided by 5. */
988 kCLOCK_LpspiDivBy6 = 5, /*!< Lpspi divider set to divided by 6. */
989 kCLOCK_LpspiDivBy7 = 6, /*!< Lpspi divider set to divided by 7. */
990 kCLOCK_LpspiDivBy8 = 7, /*!< Lpspi divider set to divided by 8. */
991
992 kCLOCK_LcdifDivBy1 = 0, /*!< Lcdif divider set to divided by 1. */
993 kCLOCK_LcdifDivBy2 = 1, /*!< Lcdif divider set to divided by 2. */
994 kCLOCK_LcdifDivBy3 = 2, /*!< Lcdif divider set to divided by 3. */
995 kCLOCK_LcdifDivBy4 = 3, /*!< Lcdif divider set to divided by 4. */
996 kCLOCK_LcdifDivBy5 = 4, /*!< Lcdif divider set to divided by 5. */
997 kCLOCK_LcdifDivBy6 = 5, /*!< Lcdif divider set to divided by 6. */
998 kCLOCK_LcdifDivBy7 = 6, /*!< Lcdif divider set to divided by 7. */
999 kCLOCK_LcdifDivBy8 = 7, /*!< Lcdif divider set to divided by 8. */
1000
1001 kCLOCK_FlexspiDivBy1 = 0, /*!< Flexspi divider set to divided by 1. */
1002 kCLOCK_FlexspiDivBy2 = 1, /*!< Flexspi divider set to divided by 2. */
1003 kCLOCK_FlexspiDivBy3 = 2, /*!< Flexspi divider set to divided by 3. */
1004 kCLOCK_FlexspiDivBy4 = 3, /*!< Flexspi divider set to divided by 4. */
1005 kCLOCK_FlexspiDivBy5 = 4, /*!< Flexspi divider set to divided by 5. */
1006 kCLOCK_FlexspiDivBy6 = 5, /*!< Flexspi divider set to divided by 6. */
1007 kCLOCK_FlexspiDivBy7 = 6, /*!< Flexspi divider set to divided by 7. */
1008 kCLOCK_FlexspiDivBy8 = 7, /*!< Flexspi divider set to divided by 8. */
1009
1010 kCLOCK_TraceDivBy1 = 0, /*!< Trace divider set to divided by 1. */
1011 kCLOCK_TraceDivBy2 = 1, /*!< Trace divider set to divided by 2. */
1012 kCLOCK_TraceDivBy3 = 2, /*!< Trace divider set to divided by 3. */
1013 kCLOCK_TraceDivBy4 = 3, /*!< Trace divider set to divided by 4. */
1014
1015 kCLOCK_Usdhc2DivBy1 = 0, /*!< Usdhc2 divider set to divided by 1. */
1016 kCLOCK_Usdhc2DivBy2 = 1, /*!< Usdhc2 divider set to divided by 2. */
1017 kCLOCK_Usdhc2DivBy3 = 2, /*!< Usdhc2 divider set to divided by 3. */
1018 kCLOCK_Usdhc2DivBy4 = 3, /*!< Usdhc2 divider set to divided by 4. */
1019 kCLOCK_Usdhc2DivBy5 = 4, /*!< Usdhc2 divider set to divided by 5. */
1020 kCLOCK_Usdhc2DivBy6 = 5, /*!< Usdhc2 divider set to divided by 6. */
1021 kCLOCK_Usdhc2DivBy7 = 6, /*!< Usdhc2 divider set to divided by 7. */
1022 kCLOCK_Usdhc2DivBy8 = 7, /*!< Usdhc2 divider set to divided by 8. */
1023
1024 kCLOCK_Usdhc1DivBy1 = 0, /*!< Usdhc1 divider set to divided by 1. */
1025 kCLOCK_Usdhc1DivBy2 = 1, /*!< Usdhc1 divider set to divided by 2. */
1026 kCLOCK_Usdhc1DivBy3 = 2, /*!< Usdhc1 divider set to divided by 3. */
1027 kCLOCK_Usdhc1DivBy4 = 3, /*!< Usdhc1 divider set to divided by 4. */
1028 kCLOCK_Usdhc1DivBy5 = 4, /*!< Usdhc1 divider set to divided by 5. */
1029 kCLOCK_Usdhc1DivBy6 = 5, /*!< Usdhc1 divider set to divided by 6. */
1030 kCLOCK_Usdhc1DivBy7 = 6, /*!< Usdhc1 divider set to divided by 7. */
1031 kCLOCK_Usdhc1DivBy8 = 7, /*!< Usdhc1 divider set to divided by 8. */
1032
1033 kCLOCK_Flexio2DivBy1 = 0, /*!< Flexio2 divider set to divided by 1. */
1034 kCLOCK_Flexio2DivBy2 = 1, /*!< Flexio2 divider set to divided by 2. */
1035 kCLOCK_Flexio2DivBy3 = 2, /*!< Flexio2 divider set to divided by 3. */
1036 kCLOCK_Flexio2DivBy4 = 3, /*!< Flexio2 divider set to divided by 4. */
1037 kCLOCK_Flexio2DivBy5 = 4, /*!< Flexio2 divider set to divided by 5. */
1038 kCLOCK_Flexio2DivBy6 = 5, /*!< Flexio2 divider set to divided by 6. */
1039 kCLOCK_Flexio2DivBy7 = 6, /*!< Flexio2 divider set to divided by 7. */
1040 kCLOCK_Flexio2DivBy8 = 7, /*!< Flexio2 divider set to divided by 8. */
1041
1042 kCLOCK_Sai3PreDivBy1 = 0, /*!< Sai3Pre divider set to divided by 1. */
1043 kCLOCK_Sai3PreDivBy2 = 1, /*!< Sai3Pre divider set to divided by 2. */
1044 kCLOCK_Sai3PreDivBy3 = 2, /*!< Sai3Pre divider set to divided by 3. */
1045 kCLOCK_Sai3PreDivBy4 = 3, /*!< Sai3Pre divider set to divided by 4. */
1046 kCLOCK_Sai3PreDivBy5 = 4, /*!< Sai3Pre divider set to divided by 5. */
1047 kCLOCK_Sai3PreDivBy6 = 5, /*!< Sai3Pre divider set to divided by 6. */
1048 kCLOCK_Sai3PreDivBy7 = 6, /*!< Sai3Pre divider set to divided by 7. */
1049 kCLOCK_Sai3PreDivBy8 = 7, /*!< Sai3Pre divider set to divided by 8. */
1050
1051 kCLOCK_Flexio2PreDivBy1 = 0, /*!< Flexio2Pre divider set to divided by 1. */
1052 kCLOCK_Flexio2PreDivBy2 = 1, /*!< Flexio2Pre divider set to divided by 2. */
1053 kCLOCK_Flexio2PreDivBy3 = 2, /*!< Flexio2Pre divider set to divided by 3. */
1054 kCLOCK_Flexio2PreDivBy4 = 3, /*!< Flexio2Pre divider set to divided by 4. */
1055 kCLOCK_Flexio2PreDivBy5 = 4, /*!< Flexio2Pre divider set to divided by 5. */
1056 kCLOCK_Flexio2PreDivBy6 = 5, /*!< Flexio2Pre divider set to divided by 6. */
1057 kCLOCK_Flexio2PreDivBy7 = 6, /*!< Flexio2Pre divider set to divided by 7. */
1058 kCLOCK_Flexio2PreDivBy8 = 7, /*!< Flexio2Pre divider set to divided by 8. */
1059
1060 kCLOCK_Sai1PreDivBy1 = 0, /*!< Sai1Pre divider set to divided by 1. */
1061 kCLOCK_Sai1PreDivBy2 = 1, /*!< Sai1Pre divider set to divided by 2. */
1062 kCLOCK_Sai1PreDivBy3 = 2, /*!< Sai1Pre divider set to divided by 3. */
1063 kCLOCK_Sai1PreDivBy4 = 3, /*!< Sai1Pre divider set to divided by 4. */
1064 kCLOCK_Sai1PreDivBy5 = 4, /*!< Sai1Pre divider set to divided by 5. */
1065 kCLOCK_Sai1PreDivBy6 = 5, /*!< Sai1Pre divider set to divided by 6. */
1066 kCLOCK_Sai1PreDivBy7 = 6, /*!< Sai1Pre divider set to divided by 7. */
1067 kCLOCK_Sai1PreDivBy8 = 7, /*!< Sai1Pre divider set to divided by 8. */
1068
1069 kCLOCK_Sai2PreDivBy1 = 0, /*!< Sai2Pre divider set to divided by 1. */
1070 kCLOCK_Sai2PreDivBy2 = 1, /*!< Sai2Pre divider set to divided by 2. */
1071 kCLOCK_Sai2PreDivBy3 = 2, /*!< Sai2Pre divider set to divided by 3. */
1072 kCLOCK_Sai2PreDivBy4 = 3, /*!< Sai2Pre divider set to divided by 4. */
1073 kCLOCK_Sai2PreDivBy5 = 4, /*!< Sai2Pre divider set to divided by 5. */
1074 kCLOCK_Sai2PreDivBy6 = 5, /*!< Sai2Pre divider set to divided by 6. */
1075 kCLOCK_Sai2PreDivBy7 = 6, /*!< Sai2Pre divider set to divided by 7. */
1076 kCLOCK_Sai2PreDivBy8 = 7, /*!< Sai2Pre divider set to divided by 8. */
1077
1078 kCLOCK_Spdif0PreDivBy1 = 0, /*!< Spdif0Pre divider set to divided by 1. */
1079 kCLOCK_Spdif0PreDivBy2 = 1, /*!< Spdif0Pre divider set to divided by 2. */
1080 kCLOCK_Spdif0PreDivBy3 = 2, /*!< Spdif0Pre divider set to divided by 3. */
1081 kCLOCK_Spdif0PreDivBy4 = 3, /*!< Spdif0Pre divider set to divided by 4. */
1082 kCLOCK_Spdif0PreDivBy5 = 4, /*!< Spdif0Pre divider set to divided by 5. */
1083 kCLOCK_Spdif0PreDivBy6 = 5, /*!< Spdif0Pre divider set to divided by 6. */
1084 kCLOCK_Spdif0PreDivBy7 = 6, /*!< Spdif0Pre divider set to divided by 7. */
1085 kCLOCK_Spdif0PreDivBy8 = 7, /*!< Spdif0Pre divider set to divided by 8. */
1086
1087 kCLOCK_Spdif0DivBy1 = 0, /*!< Spdif0 divider set to divided by 1. */
1088 kCLOCK_Spdif0DivBy2 = 1, /*!< Spdif0 divider set to divided by 2. */
1089 kCLOCK_Spdif0DivBy3 = 2, /*!< Spdif0 divider set to divided by 3. */
1090 kCLOCK_Spdif0DivBy4 = 3, /*!< Spdif0 divider set to divided by 4. */
1091 kCLOCK_Spdif0DivBy5 = 4, /*!< Spdif0 divider set to divided by 5. */
1092 kCLOCK_Spdif0DivBy6 = 5, /*!< Spdif0 divider set to divided by 6. */
1093 kCLOCK_Spdif0DivBy7 = 6, /*!< Spdif0 divider set to divided by 7. */
1094 kCLOCK_Spdif0DivBy8 = 7, /*!< Spdif0 divider set to divided by 8. */
1095
1096 kCLOCK_Flexio1PreDivBy1 = 0, /*!< Flexio1Pre divider set to divided by 1. */
1097 kCLOCK_Flexio1PreDivBy2 = 1, /*!< Flexio1Pre divider set to divided by 2. */
1098 kCLOCK_Flexio1PreDivBy3 = 2, /*!< Flexio1Pre divider set to divided by 3. */
1099 kCLOCK_Flexio1PreDivBy8 = 7, /*!< Flexio1Pre divider set to divided by 8. */
1100
1101 kCLOCK_Flexio1DivBy1 = 0, /*!< Flexio1 divider set to divided by 1. */
1102 kCLOCK_Flexio1DivBy2 = 1, /*!< Flexio1 divider set to divided by 2. */
1103 kCLOCK_Flexio1DivBy3 = 2, /*!< Flexio1 divider set to divided by 3. */
1104 kCLOCK_Flexio1DivBy4 = 3, /*!< Flexio1 divider set to divided by 4. */
1105 kCLOCK_Flexio1DivBy5 = 4, /*!< Flexio1 divider set to divided by 5. */
1106 kCLOCK_Flexio1DivBy6 = 5, /*!< Flexio1 divider set to divided by 6. */
1107 kCLOCK_Flexio1DivBy7 = 6, /*!< Flexio1 divider set to divided by 7. */
1108 kCLOCK_Flexio1DivBy8 = 7, /*!< Flexio1 divider set to divided by 8. */
1109
1110 kCLOCK_LcdifPreDivBy1 = 0, /*!< LcdifPre divider set to divided by 1. */
1111 kCLOCK_LcdifPreDivBy2 = 1, /*!< LcdifPre divider set to divided by 2. */
1112 kCLOCK_LcdifPreDivBy3 = 2, /*!< LcdifPre divider set to divided by 3. */
1113 kCLOCK_LcdifPreDivBy4 = 3, /*!< LcdifPre divider set to divided by 4. */
1114 kCLOCK_LcdifPreDivBy5 = 4, /*!< LcdifPre divider set to divided by 5. */
1115 kCLOCK_LcdifPreDivBy6 = 5, /*!< LcdifPre divider set to divided by 6. */
1116 kCLOCK_LcdifPreDivBy7 = 6, /*!< LcdifPre divider set to divided by 7. */
1117 kCLOCK_LcdifPreDivBy8 = 7, /*!< LcdifPre divider set to divided by 8. */
1118
1119 kCLOCK_CsiDivBy1 = 0, /*!< Csi divider set to divided by 1. */
1120 kCLOCK_CsiDivBy2 = 1, /*!< Csi divider set to divided by 2. */
1121 kCLOCK_CsiDivBy3 = 2, /*!< Csi divider set to divided by 3. */
1122 kCLOCK_CsiDivBy4 = 3, /*!< Csi divider set to divided by 4. */
1123 kCLOCK_CsiDivBy5 = 4, /*!< Csi divider set to divided by 5. */
1124 kCLOCK_CsiDivBy6 = 5, /*!< Csi divider set to divided by 6. */
1125 kCLOCK_CsiDivBy7 = 6, /*!< Csi divider set to divided by 7. */
1126 kCLOCK_CsiDivBy8 = 7, /*!< Csi divider set to divided by 8. */
1127
1128 /* Only kCLOCK_PerClk, kCLOCK_Lpi2cDiv, kCLOCK_CanDiv, kCLOCK_UartDiv, kCLOCK_Sai1Div,
1129 * kCLOCK_Sai2Div, kCLOCK_Sai3Div can use these.
1130 */
1131 kCLOCK_MiscDivBy1 = 0 , /*!< Misc divider like LPI2C set to divided by 1 . */
1132 kCLOCK_MiscDivBy2 = 1 , /*!< Misc divider like LPI2C set to divided by 2 . */
1133 kCLOCK_MiscDivBy3 = 2 , /*!< Misc divider like LPI2C set to divided by 3 . */
1134 kCLOCK_MiscDivBy4 = 3 , /*!< Misc divider like LPI2C set to divided by 4 . */
1135 kCLOCK_MiscDivBy5 = 4 , /*!< Misc divider like LPI2C set to divided by 5 . */
1136 kCLOCK_MiscDivBy6 = 5 , /*!< Misc divider like LPI2C set to divided by 6 . */
1137 kCLOCK_MiscDivBy7 = 6 , /*!< Misc divider like LPI2C set to divided by 7 . */
1138 kCLOCK_MiscDivBy8 = 7 , /*!< Misc divider like LPI2C set to divided by 8 . */
1139 kCLOCK_MiscDivBy9 = 8 , /*!< Misc divider like LPI2C set to divided by 9 . */
1140 kCLOCK_MiscDivBy10 = 9 , /*!< Misc divider like LPI2C set to divided by 10. */
1141 kCLOCK_MiscDivBy11 = 10, /*!< Misc divider like LPI2C set to divided by 11. */
1142 kCLOCK_MiscDivBy12 = 11, /*!< Misc divider like LPI2C set to divided by 12. */
1143 kCLOCK_MiscDivBy13 = 12, /*!< Misc divider like LPI2C set to divided by 13. */
1144 kCLOCK_MiscDivBy14 = 13, /*!< Misc divider like LPI2C set to divided by 14. */
1145 kCLOCK_MiscDivBy15 = 14, /*!< Misc divider like LPI2C set to divided by 15. */
1146 kCLOCK_MiscDivBy16 = 15, /*!< Misc divider like LPI2C set to divided by 16. */
1147 kCLOCK_MiscDivBy17 = 16, /*!< Misc divider like LPI2C set to divided by 17. */
1148 kCLOCK_MiscDivBy18 = 17, /*!< Misc divider like LPI2C set to divided by 18. */
1149 kCLOCK_MiscDivBy19 = 18, /*!< Misc divider like LPI2C set to divided by 19. */
1150 kCLOCK_MiscDivBy20 = 19, /*!< Misc divider like LPI2C set to divided by 20. */
1151 kCLOCK_MiscDivBy21 = 20, /*!< Misc divider like LPI2C set to divided by 21. */
1152 kCLOCK_MiscDivBy22 = 21, /*!< Misc divider like LPI2C set to divided by 22. */
1153 kCLOCK_MiscDivBy23 = 22, /*!< Misc divider like LPI2C set to divided by 23. */
1154 kCLOCK_MiscDivBy24 = 23, /*!< Misc divider like LPI2C set to divided by 24. */
1155 kCLOCK_MiscDivBy25 = 24, /*!< Misc divider like LPI2C set to divided by 25. */
1156 kCLOCK_MiscDivBy26 = 25, /*!< Misc divider like LPI2C set to divided by 26. */
1157 kCLOCK_MiscDivBy27 = 26, /*!< Misc divider like LPI2C set to divided by 27. */
1158 kCLOCK_MiscDivBy28 = 27, /*!< Misc divider like LPI2C set to divided by 28. */
1159 kCLOCK_MiscDivBy29 = 28, /*!< Misc divider like LPI2C set to divided by 29. */
1160 kCLOCK_MiscDivBy30 = 29, /*!< Misc divider like LPI2C set to divided by 30. */
1161 kCLOCK_MiscDivBy31 = 30, /*!< Misc divider like LPI2C set to divided by 31. */
1162 kCLOCK_MiscDivBy32 = 31, /*!< Misc divider like LPI2C set to divided by 32. */
1163 kCLOCK_MiscDivBy33 = 32, /*!< Misc divider like LPI2C set to divided by 33. */
1164 kCLOCK_MiscDivBy34 = 33, /*!< Misc divider like LPI2C set to divided by 34. */
1165 kCLOCK_MiscDivBy35 = 34, /*!< Misc divider like LPI2C set to divided by 35. */
1166 kCLOCK_MiscDivBy36 = 35, /*!< Misc divider like LPI2C set to divided by 36. */
1167 kCLOCK_MiscDivBy37 = 36, /*!< Misc divider like LPI2C set to divided by 37. */
1168 kCLOCK_MiscDivBy38 = 37, /*!< Misc divider like LPI2C set to divided by 38. */
1169 kCLOCK_MiscDivBy39 = 38, /*!< Misc divider like LPI2C set to divided by 39. */
1170 kCLOCK_MiscDivBy40 = 39, /*!< Misc divider like LPI2C set to divided by 40. */
1171 kCLOCK_MiscDivBy41 = 40, /*!< Misc divider like LPI2C set to divided by 41. */
1172 kCLOCK_MiscDivBy42 = 41, /*!< Misc divider like LPI2C set to divided by 42. */
1173 kCLOCK_MiscDivBy43 = 42, /*!< Misc divider like LPI2C set to divided by 43. */
1174 kCLOCK_MiscDivBy44 = 43, /*!< Misc divider like LPI2C set to divided by 44. */
1175 kCLOCK_MiscDivBy45 = 44, /*!< Misc divider like LPI2C set to divided by 45. */
1176 kCLOCK_MiscDivBy46 = 45, /*!< Misc divider like LPI2C set to divided by 46. */
1177 kCLOCK_MiscDivBy47 = 46, /*!< Misc divider like LPI2C set to divided by 47. */
1178 kCLOCK_MiscDivBy48 = 47, /*!< Misc divider like LPI2C set to divided by 48. */
1179 kCLOCK_MiscDivBy49 = 48, /*!< Misc divider like LPI2C set to divided by 49. */
1180 kCLOCK_MiscDivBy50 = 49, /*!< Misc divider like LPI2C set to divided by 50. */
1181 kCLOCK_MiscDivBy51 = 50, /*!< Misc divider like LPI2C set to divided by 51. */
1182 kCLOCK_MiscDivBy52 = 51, /*!< Misc divider like LPI2C set to divided by 52. */
1183 kCLOCK_MiscDivBy53 = 52, /*!< Misc divider like LPI2C set to divided by 53. */
1184 kCLOCK_MiscDivBy54 = 53, /*!< Misc divider like LPI2C set to divided by 54. */
1185 kCLOCK_MiscDivBy55 = 54, /*!< Misc divider like LPI2C set to divided by 55. */
1186 kCLOCK_MiscDivBy56 = 55, /*!< Misc divider like LPI2C set to divided by 56. */
1187 kCLOCK_MiscDivBy57 = 56, /*!< Misc divider like LPI2C set to divided by 57. */
1188 kCLOCK_MiscDivBy58 = 57, /*!< Misc divider like LPI2C set to divided by 58. */
1189 kCLOCK_MiscDivBy59 = 58, /*!< Misc divider like LPI2C set to divided by 59. */
1190 kCLOCK_MiscDivBy60 = 59, /*!< Misc divider like LPI2C set to divided by 60. */
1191 kCLOCK_MiscDivBy61 = 60, /*!< Misc divider like LPI2C set to divided by 61. */
1192 kCLOCK_MiscDivBy62 = 61, /*!< Misc divider like LPI2C set to divided by 62. */
1193 kCLOCK_MiscDivBy63 = 62, /*!< Misc divider like LPI2C set to divided by 63. */
1194 kCLOCK_MiscDivBy64 = 63, /*!< Misc divider like LPI2C set to divided by 64. */
1195 } clock_div_value_t;
1196
1197 /*! @brief USB clock source definition. */
1198 typedef enum _clock_usb_src
1199 {
1200 kCLOCK_Usb480M = 0, /*!< Use 480M. */
1201 kCLOCK_UsbSrcUnused = (int)0xFFFFFFFFU, /*!< Used when the function does not
1202 care the clock source. */
1203 } clock_usb_src_t;
1204
1205 /*! @brief Source of the USB HS PHY. */
1206 typedef enum _clock_usb_phy_src
1207 {
1208 kCLOCK_Usbphy480M = 0, /*!< Use 480M. */
1209 } clock_usb_phy_src_t;
1210
1211 /*!@brief PLL clock source, bypass cloco source also */
1212 enum _clock_pll_clk_src
1213 {
1214 kCLOCK_PllClkSrc24M = 0U, /*!< Pll clock source 24M */
1215 kCLOCK_PllSrcClkPN = 1U, /*!< Pll clock source CLK1_P and CLK1_N */
1216 };
1217
1218 /*! @brief PLL configuration for ARM */
1219 typedef struct _clock_arm_pll_config
1220 {
1221 uint32_t loopDivider; /*!< PLL loop divider. Valid range for divider value: 54-108. Fout=Fin*loopDivider/2. */
1222 uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */
1223 } clock_arm_pll_config_t;
1224
1225 /*! @brief PLL configuration for USB */
1226 typedef struct _clock_usb_pll_config
1227 {
1228 uint8_t loopDivider; /*!< PLL loop divider.
1229 0 - Fout=Fref*20;
1230 1 - Fout=Fref*22 */
1231 uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */
1232
1233 } clock_usb_pll_config_t;
1234
1235 /*! @brief PLL configuration for System */
1236 typedef struct _clock_sys_pll_config
1237 {
1238 uint8_t loopDivider; /*!< PLL loop divider. Intended to be 1 (528M).
1239 0 - Fout=Fref*20;
1240 1 - Fout=Fref*22 */
1241 uint32_t numerator; /*!< 30 bit numerator of fractional loop divider.*/
1242 uint32_t denominator; /*!< 30 bit denominator of fractional loop divider */
1243 uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */
1244 uint16_t ss_stop; /*!< Stop value to get frequency change. */
1245 uint8_t ss_enable; /*!< Enable spread spectrum modulation */
1246 uint16_t ss_step; /*!< Step value to get frequency change step. */
1247 } clock_sys_pll_config_t;
1248
1249 /*! @brief PLL configuration for AUDIO and VIDEO */
1250 typedef struct _clock_audio_pll_config
1251 {
1252 uint8_t loopDivider; /*!< PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. */
1253 uint8_t postDivider; /*!< Divider after the PLL, should only be 1, 2, 4, 8, 16. */
1254 uint32_t numerator; /*!< 30 bit numerator of fractional loop divider.*/
1255 uint32_t denominator; /*!< 30 bit denominator of fractional loop divider */
1256 uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */
1257 } clock_audio_pll_config_t;
1258
1259 /*! @brief PLL configuration for AUDIO and VIDEO */
1260 typedef struct _clock_video_pll_config
1261 {
1262 uint8_t loopDivider; /*!< PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. */
1263 uint8_t postDivider; /*!< Divider after the PLL, should only be 1, 2, 4, 8, 16. */
1264 uint32_t numerator; /*!< 30 bit numerator of fractional loop divider.*/
1265 uint32_t denominator; /*!< 30 bit denominator of fractional loop divider */
1266 uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */
1267
1268 } clock_video_pll_config_t;
1269
1270 /*! @brief PLL configuration for ENET */
1271 typedef struct _clock_enet_pll_config
1272 {
1273 bool enableClkOutput; /*!< Power on and enable PLL clock output for ENET0 (ref_enetpll0). */
1274 bool enableClkOutput25M; /*!< Power on and enable PLL clock output for ENET2 (ref_enetpll2). */
1275 uint8_t loopDivider; /*!< Controls the frequency of the ENET0 reference clock.
1276 b00 25MHz
1277 b01 50MHz
1278 b10 100MHz (not 50% duty cycle)
1279 b11 125MHz */
1280 uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */
1281 bool enableClkOutput1; /*!< Power on and enable PLL clock output for ENET1 (ref_enetpll1). */
1282 uint8_t loopDivider1; /*!< Controls the frequency of the ENET1 reference clock.
1283 b00 25MHz
1284 b01 50MHz
1285 b10 100MHz (not 50% duty cycle)
1286 b11 125MHz */
1287 } clock_enet_pll_config_t;
1288
1289 /*! @brief PLL name */
1290 typedef enum _clock_pll
1291 {
1292 kCLOCK_PllArm = CCM_ANALOG_TUPLE(PLL_ARM_OFFSET, CCM_ANALOG_PLL_ARM_ENABLE_SHIFT), /*!< PLL ARM */
1293 kCLOCK_PllSys = CCM_ANALOG_TUPLE(PLL_SYS_OFFSET, CCM_ANALOG_PLL_SYS_ENABLE_SHIFT), /*!< PLL SYS */
1294 kCLOCK_PllUsb1 = CCM_ANALOG_TUPLE(PLL_USB1_OFFSET, CCM_ANALOG_PLL_USB1_ENABLE_SHIFT), /*!< PLL USB1 */
1295 kCLOCK_PllAudio = CCM_ANALOG_TUPLE(PLL_AUDIO_OFFSET, CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT), /*!< PLL Audio */
1296 kCLOCK_PllVideo = CCM_ANALOG_TUPLE(PLL_VIDEO_OFFSET, CCM_ANALOG_PLL_VIDEO_ENABLE_SHIFT), /*!< PLL Video */
1297
1298 kCLOCK_PllEnet = CCM_ANALOG_TUPLE(PLL_ENET_OFFSET, CCM_ANALOG_PLL_ENET_ENABLE_SHIFT), /*!< PLL Enet0 */
1299 kCLOCK_PllEnet2 = CCM_ANALOG_TUPLE(PLL_ENET_OFFSET, CCM_ANALOG_PLL_ENET_ENET2_REF_EN_SHIFT), /*!< PLL Enet1 */
1300 kCLOCK_PllEnet25M = CCM_ANALOG_TUPLE(PLL_ENET_OFFSET, CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT), /*!< PLL Enet2 */
1301
1302 kCLOCK_PllUsb2 = CCM_ANALOG_TUPLE(PLL_USB2_OFFSET, CCM_ANALOG_PLL_USB2_ENABLE_SHIFT), /*!< PLL USB2 */
1303
1304 } clock_pll_t;
1305
1306 /*! @brief PLL PFD name */
1307 typedef enum _clock_pfd
1308 {
1309 kCLOCK_Pfd0 = 0U, /*!< PLL PFD0 */
1310 kCLOCK_Pfd1 = 1U, /*!< PLL PFD1 */
1311 kCLOCK_Pfd2 = 2U, /*!< PLL PFD2 */
1312 kCLOCK_Pfd3 = 3U, /*!< PLL PFD3 */
1313 } clock_pfd_t;
1314
1315 /*!
1316 * @brief The enumerater of clock output1's clock source, such as USB1 PLL, SYS PLL and so on.
1317 */
1318 typedef enum _clock_output1_selection
1319 {
1320 kCLOCK_OutputPllUsb1 = 0U, /*!< Selects USB1 PLL clock(Divided by 2) output. */
1321 kCLOCK_OutputPllSys = 1U, /*!< Selects SYS PLL clock(Divided by 2) output. */
1322 kCLOCK_OutputPllVideo = 3U, /*!< Selects Video PLL clock(Divided by 2) output. */
1323 kCLOCK_OutputSemcClk = 5U, /*!< Selects semc clock root output. */
1324 kCLOCK_OutputLcdifPixClk = 0xAU, /*!< Selects Lcdif pix clock root output. */
1325 kCLOCK_OutputAhbClk = 0xBU, /*!< Selects AHB clock root output. */
1326 kCLOCK_OutputIpgClk = 0xCU, /*!< Selects IPG clock root output. */
1327 kCLOCK_OutputPerClk = 0xDU, /*!< Selects PERCLK clock root output. */
1328 kCLOCK_OutputCkilSyncClk = 0xEU, /*!< Selects Ckil clock root output. */
1329 kCLOCK_OutputPll4MainClk = 0xFU, /*!< Selects PLL4 main clock output. */
1330 kCLOCK_DisableClockOutput1 = 0x10U, /*!< Disables CLKO1. */
1331 } clock_output1_selection_t;
1332
1333 /*!
1334 * @brief The enumerater of clock output2's clock source, such as USDHC1 clock root, LPI2C clock root and so on.
1335 *
1336 */
1337 typedef enum _clock_output2_selection
1338 {
1339 kCLOCK_OutputUsdhc1Clk = 3U, /*!< Selects USDHC1 clock root output. */
1340 kCLOCK_OutputLpi2cClk = 6U, /*!< Selects LPI2C clock root output. */
1341 kCLOCK_OutputCsiClk = 0xBU, /*!< Selects CSI clock root output. */
1342 kCLOCK_OutputOscClk = 0xEU, /*!< Selects OSC output. */
1343 kCLOCK_OutputUsdhc2Clk = 0x11U, /*!< Selects USDHC2 clock root output. */
1344 kCLOCK_OutputSai1Clk = 0x12U, /*!< Selects SAI1 clock root output. */
1345 kCLOCK_OutputSai2Clk = 0x13U, /*!< Selects SAI2 clock root output. */
1346 kCLOCK_OutputSai3Clk = 0x14U, /*!< Selects SAI3 clock root output. */
1347 kCLOCK_OutputCanClk = 0x17U, /*!< Selects CAN clock root output. */
1348 kCLOCK_OutputFlexspiClk = 0x1BU, /*!< Selects FLEXSPI clock root output. */
1349 kCLOCK_OutputUartClk = 0x1CU, /*!< Selects UART clock root output. */
1350 kCLOCK_OutputSpdif0Clk = 0x1DU, /*!< Selects SPDIF0 clock root output. */
1351 kCLOCK_DisableClockOutput2 = 0x1FU, /*!< Disables CLKO2. */
1352 } clock_output2_selection_t;
1353
1354 /*!
1355 * @brief The enumerator of clock output's divider.
1356 */
1357 typedef enum _clock_output_divider
1358 {
1359 kCLOCK_DivideBy1 = 0U, /*!< Output clock divided by 1. */
1360 kCLOCK_DivideBy2, /*!< Output clock divided by 2. */
1361 kCLOCK_DivideBy3, /*!< Output clock divided by 3. */
1362 kCLOCK_DivideBy4, /*!< Output clock divided by 4. */
1363 kCLOCK_DivideBy5, /*!< Output clock divided by 5. */
1364 kCLOCK_DivideBy6, /*!< Output clock divided by 6. */
1365 kCLOCK_DivideBy7, /*!< Output clock divided by 7. */
1366 kCLOCK_DivideBy8, /*!< Output clock divided by 8. */
1367 } clock_output_divider_t;
1368
1369 /*!
1370 * @brief The enumerator of clock root.
1371 */
1372 typedef enum _clock_root
1373 {
1374 kCLOCK_Usdhc1ClkRoot = 0U, /*!< USDHC1 clock root. */
1375 kCLOCK_Usdhc2ClkRoot, /*!< USDHC2 clock root. */
1376 kCLOCK_FlexspiClkRoot, /*!< FLEXSPI clock root. */
1377 kCLOCK_Flexspi2ClkRoot, /*!< FLEXSPI2 clock root. */
1378 kCLOCK_CsiClkRoot, /*!< CSI clock root. */
1379 kCLOCK_LpspiClkRoot, /*!< LPSPI clock root. */
1380 kCLOCK_TraceClkRoot, /*!< Trace clock root. */
1381 kCLOCK_Sai1ClkRoot, /*!< SAI1 clock root. */
1382 kCLOCK_Sai2ClkRoot, /*!< SAI2 clock root. */
1383 kCLOCK_Sai3ClkRoot, /*!< SAI3 clock root. */
1384 kCLOCK_Lpi2cClkRoot, /*!< LPI2C clock root. */
1385 kCLOCK_CanClkRoot, /*!< CAN clock root. */
1386 kCLOCK_UartClkRoot, /*!< UART clock root. */
1387 kCLOCK_LcdifClkRoot, /*!< LCD clock root. */
1388 kCLOCK_SpdifClkRoot, /*!< SPDIF clock root. */
1389 kCLOCK_Flexio1ClkRoot, /*!< FLEXIO1 clock root. */
1390 kCLOCK_Flexio2ClkRoot, /*!< FLEXIO2 clock root. */
1391 } clock_root_t;
1392
1393 /*******************************************************************************
1394 * API
1395 ******************************************************************************/
1396
1397 #if defined(__cplusplus)
1398 extern "C" {
1399 #endif /* __cplusplus */
1400
1401 /*!
1402 * @brief Set CCM MUX node to certain value.
1403 *
1404 * @param mux Which mux node to set, see \ref clock_mux_t.
1405 * @param value Clock mux value to set, different mux has different value range.
1406 */
CLOCK_SetMux(clock_mux_t mux,uint32_t value)1407 static inline void CLOCK_SetMux(clock_mux_t mux, uint32_t value)
1408 {
1409 uint32_t busyShift;
1410
1411 busyShift = (uint32_t)CCM_TUPLE_BUSY_SHIFT(mux);
1412 CCM_TUPLE_REG(CCM, mux) = (CCM_TUPLE_REG(CCM, mux) & (~CCM_TUPLE_MASK(mux))) |
1413 (((uint32_t)((value) << CCM_TUPLE_SHIFT(mux))) & CCM_TUPLE_MASK(mux));
1414
1415 assert(busyShift <= CCM_NO_BUSY_WAIT);
1416
1417 /* Clock switch need Handshake? */
1418 if (CCM_NO_BUSY_WAIT != busyShift)
1419 {
1420 /* Wait until CCM internal handshake finish. */
1421 while ((CCM->CDHIPR & ((1UL << busyShift))) != 0UL)
1422 {
1423 }
1424 }
1425 }
1426
1427 /*!
1428 * @brief Get CCM MUX value.
1429 *
1430 * @param mux Which mux node to get, see \ref clock_mux_t.
1431 * @return Clock mux value.
1432 */
CLOCK_GetMux(clock_mux_t mux)1433 static inline uint32_t CLOCK_GetMux(clock_mux_t mux)
1434 {
1435 return (((uint32_t)(CCM_TUPLE_REG(CCM, mux) & CCM_TUPLE_MASK(mux))) >> CCM_TUPLE_SHIFT(mux));
1436 }
1437
1438 /*!
1439 * @brief Set clock divider value.
1440 *
1441 * Example, set the ARM clock divider to divide by 2:
1442 * @code
1443 CLOCK_SetDiv(kCLOCK_ArmDiv, kCLOCK_ArmDivBy2);
1444 @endcode
1445 *
1446 * Example, set the LPI2C clock divider to divide by 5.
1447 * @code
1448 CLOCK_SetDiv(kCLOCK_Lpi2cDiv, kCLOCK_MiscDivBy5);
1449 @endcode
1450 *
1451 * Only @ref kCLOCK_PerClk, @ref kCLOCK_Lpi2cDiv, @ref kCLOCK_CanDiv, @ref kCLOCK_UartDiv, @ref kCLOCK_Sai1Div,
1452 * @ref kCLOCK_Sai2Div, @ref kCLOCK_Sai3Div can use the divider kCLOCK_MiscDivByxxx.
1453 *
1454 * @param divider Which divider node to set.
1455 * @param value Clock div value to set, different divider has different value range. See @ref clock_div_value_t
1456 * for details.
1457 * Divided clock frequency = Undivided clock frequency / (value + 1)
1458 */
CLOCK_SetDiv(clock_div_t divider,uint32_t value)1459 static inline void CLOCK_SetDiv(clock_div_t divider, uint32_t value)
1460 {
1461 uint32_t busyShift;
1462
1463 busyShift = CCM_TUPLE_BUSY_SHIFT(divider);
1464 CCM_TUPLE_REG(CCM, divider) = (CCM_TUPLE_REG(CCM, divider) & (~CCM_TUPLE_MASK(divider))) |
1465 (((uint32_t)((value) << CCM_TUPLE_SHIFT(divider))) & CCM_TUPLE_MASK(divider));
1466
1467 assert(busyShift <= CCM_NO_BUSY_WAIT);
1468
1469 /* Clock switch need Handshake? */
1470 if (CCM_NO_BUSY_WAIT != busyShift)
1471 {
1472 /* Wait until CCM internal handshake finish. */
1473 while ((CCM->CDHIPR & ((uint32_t)(1UL << busyShift))) != 0UL)
1474 {
1475 }
1476 }
1477 }
1478
1479 /*!
1480 * @brief Get CCM DIV node value.
1481 *
1482 * @param divider Which div node to get, see \ref clock_div_t.
1483 */
CLOCK_GetDiv(clock_div_t divider)1484 static inline uint32_t CLOCK_GetDiv(clock_div_t divider)
1485 {
1486 return ((uint32_t)(CCM_TUPLE_REG(CCM, divider) & CCM_TUPLE_MASK(divider)) >> CCM_TUPLE_SHIFT(divider));
1487 }
1488
1489 /*!
1490 * @brief Control the clock gate for specific IP.
1491 *
1492 * @param name Which clock to enable, see \ref clock_ip_name_t.
1493 * @param value Clock gate value to set, see \ref clock_gate_value_t.
1494 */
CLOCK_ControlGate(clock_ip_name_t name,clock_gate_value_t value)1495 static inline void CLOCK_ControlGate(clock_ip_name_t name, clock_gate_value_t value)
1496 {
1497 uint32_t index = ((uint32_t)name) >> 8U;
1498 uint32_t shift = ((uint32_t)name) & 0x1FU;
1499 volatile uint32_t *reg;
1500
1501 assert(index <= 7UL);
1502
1503 reg = (volatile uint32_t *)(&(((volatile uint32_t *)&CCM->CCGR0)[index]));
1504 SDK_ATOMIC_LOCAL_CLEAR_AND_SET(reg, (3UL << shift), (((uint32_t)value) << shift));
1505 }
1506
1507 /*!
1508 * @brief Enable the clock for specific IP.
1509 *
1510 * @param name Which clock to enable, see \ref clock_ip_name_t.
1511 */
CLOCK_EnableClock(clock_ip_name_t name)1512 static inline void CLOCK_EnableClock(clock_ip_name_t name)
1513 {
1514 CLOCK_ControlGate(name, kCLOCK_ClockNeededRunWait);
1515 }
1516
1517 /*!
1518 * @brief Disable the clock for specific IP.
1519 *
1520 * @param name Which clock to disable, see \ref clock_ip_name_t.
1521 */
CLOCK_DisableClock(clock_ip_name_t name)1522 static inline void CLOCK_DisableClock(clock_ip_name_t name)
1523 {
1524 CLOCK_ControlGate(name, kCLOCK_ClockNotNeeded);
1525 }
1526
1527 /*!
1528 * @brief Setting the low power mode that system will enter on next assertion of dsm_request signal.
1529 *
1530 * @param mode Which mode to enter, see \ref clock_mode_t.
1531 */
CLOCK_SetMode(clock_mode_t mode)1532 static inline void CLOCK_SetMode(clock_mode_t mode)
1533 {
1534 CCM->CLPCR = (CCM->CLPCR & ~CCM_CLPCR_LPM_MASK) | CCM_CLPCR_LPM((uint32_t)mode);
1535 }
1536
1537 /*!
1538 * @brief Gets the OSC clock frequency.
1539 *
1540 * This function will return the external XTAL OSC frequency if it is selected as the source of OSC,
1541 * otherwise internal 24MHz RC OSC frequency will be returned.
1542 *
1543 * @param osc OSC type to get frequency.
1544 *
1545 * @return Clock frequency; If the clock is invalid, returns 0.
1546 */
CLOCK_GetOscFreq(void)1547 static inline uint32_t CLOCK_GetOscFreq(void)
1548 {
1549 return ((XTALOSC24M->LOWPWR_CTRL & XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK) != 0UL) ? 24000000UL : g_xtalFreq;
1550 }
1551
1552 /*!
1553 * @brief Gets the AHB clock frequency.
1554 *
1555 * @return The AHB clock frequency value in hertz.
1556 */
1557 uint32_t CLOCK_GetAhbFreq(void);
1558
1559 /*!
1560 * @brief Gets the SEMC clock frequency.
1561 *
1562 * @return The SEMC clock frequency value in hertz.
1563 */
1564 uint32_t CLOCK_GetSemcFreq(void);
1565
1566 /*!
1567 * @brief Gets the IPG clock frequency.
1568 *
1569 * @return The IPG clock frequency value in hertz.
1570 */
1571 uint32_t CLOCK_GetIpgFreq(void);
1572
1573 /*!
1574 * @brief Gets the PER clock frequency.
1575 *
1576 * @return The PER clock frequency value in hertz.
1577 */
1578 uint32_t CLOCK_GetPerClkFreq(void);
1579
1580 /*!
1581 * @brief Gets the clock frequency for a specific clock name.
1582 *
1583 * This function checks the current clock configurations and then calculates
1584 * the clock frequency for a specific clock name defined in clock_name_t.
1585 *
1586 * @param clockName Clock names defined in clock_name_t
1587 * @return Clock frequency value in hertz
1588 */
1589 uint32_t CLOCK_GetFreq(clock_name_t name);
1590
1591 /*!
1592 * @brief Get the CCM CPU/core/system frequency.
1593 *
1594 * @return Clock frequency; If the clock is invalid, returns 0.
1595 */
CLOCK_GetCpuClkFreq(void)1596 static inline uint32_t CLOCK_GetCpuClkFreq(void)
1597 {
1598 return CLOCK_GetFreq(kCLOCK_CpuClk);
1599 }
1600
1601 /*!
1602 * @brief Gets the frequency of selected clock root.
1603 *
1604 * @param clockRoot The clock root used to get the frequency, please refer to @ref clock_root_t.
1605 * @return The frequency of selected clock root.
1606 */
1607 uint32_t CLOCK_GetClockRootFreq(clock_root_t clockRoot);
1608
1609 /*!
1610 * @name OSC operations
1611 * @{
1612 */
1613
1614 /*!
1615 * @brief Initialize the external 24MHz clock.
1616 *
1617 * This function supports two modes:
1618 * 1. Use external crystal oscillator.
1619 * 2. Bypass the external crystal oscillator, using input source clock directly.
1620 *
1621 * After this function, please call @ref CLOCK_SetXtal0Freq to inform clock driver
1622 * the external clock frequency.
1623 *
1624 * @param bypassXtalOsc Pass in true to bypass the external crystal oscillator.
1625 * @note This device does not support bypass external crystal oscillator, so
1626 * the input parameter should always be false.
1627 */
1628 void CLOCK_InitExternalClk(bool bypassXtalOsc);
1629
1630 /*!
1631 * @brief Deinitialize the external 24MHz clock.
1632 *
1633 * This function disables the external 24MHz clock.
1634 *
1635 * After this function, please call @ref CLOCK_SetXtal0Freq to set external clock
1636 * frequency to 0.
1637 */
1638 void CLOCK_DeinitExternalClk(void);
1639
1640 /*!
1641 * @brief Switch the OSC.
1642 *
1643 * This function switches the OSC source for SoC.
1644 *
1645 * @param osc OSC source to switch to.
1646 */
1647 void CLOCK_SwitchOsc(clock_osc_t osc);
1648
1649 /*!
1650 * @brief Gets the RTC clock frequency.
1651 *
1652 * @return Clock frequency; If the clock is invalid, returns 0.
1653 */
CLOCK_GetRtcFreq(void)1654 static inline uint32_t CLOCK_GetRtcFreq(void)
1655 {
1656 return 32768U;
1657 }
1658
1659 /*!
1660 * @brief Set the XTAL (24M OSC) frequency based on board setting.
1661 *
1662 * @param freq The XTAL input clock frequency in Hz.
1663 */
CLOCK_SetXtalFreq(uint32_t freq)1664 static inline void CLOCK_SetXtalFreq(uint32_t freq)
1665 {
1666 g_xtalFreq = freq;
1667 }
1668
1669 /*!
1670 * @brief Set the RTC XTAL (32K OSC) frequency based on board setting.
1671 *
1672 * @param freq The RTC XTAL input clock frequency in Hz.
1673 */
CLOCK_SetRtcXtalFreq(uint32_t freq)1674 static inline void CLOCK_SetRtcXtalFreq(uint32_t freq)
1675 {
1676 g_rtcXtalFreq = freq;
1677 }
1678
1679 /*!
1680 * @brief Initialize the RC oscillator 24MHz clock.
1681 */
1682 void CLOCK_InitRcOsc24M(void);
1683
1684 /*!
1685 * @brief Power down the RCOSC 24M clock.
1686 */
1687 void CLOCK_DeinitRcOsc24M(void);
1688 /* @} */
1689
1690 /*! @brief Enable USB HS clock.
1691 *
1692 * This function only enables the access to USB HS prepheral, upper layer
1693 * should first call the @ref CLOCK_EnableUsbhs0PhyPllClock to enable the PHY
1694 * clock to use USB HS.
1695 *
1696 * @param src USB HS does not care about the clock source, here must be @ref kCLOCK_UsbSrcUnused.
1697 * @param freq USB HS does not care about the clock source, so this parameter is ignored.
1698 * @retval true The clock is set successfully.
1699 * @retval false The clock source is invalid to get proper USB HS clock.
1700 */
1701 bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq);
1702
1703 /*! @brief Enable USB HS clock.
1704 *
1705 * This function only enables the access to USB HS prepheral, upper layer
1706 * should first call the @ref CLOCK_EnableUsbhs0PhyPllClock to enable the PHY
1707 * clock to use USB HS.
1708 *
1709 * @param src USB HS does not care about the clock source, here must be @ref kCLOCK_UsbSrcUnused.
1710 * @param freq USB HS does not care about the clock source, so this parameter is ignored.
1711 * @retval true The clock is set successfully.
1712 * @retval false The clock source is invalid to get proper USB HS clock.
1713 */
1714 bool CLOCK_EnableUsbhs1Clock(clock_usb_src_t src, uint32_t freq);
1715
1716 /* @} */
1717
1718 /*!
1719 * @name PLL/PFD operations
1720 * @{
1721 */
1722 /*!
1723 * @brief PLL bypass setting
1724 *
1725 * @param base CCM_ANALOG base pointer.
1726 * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration)
1727 * @param bypass Bypass the PLL.
1728 * - true: Bypass the PLL.
1729 * - false:Not bypass the PLL.
1730 */
CLOCK_SetPllBypass(CCM_ANALOG_Type * base,clock_pll_t pll,bool bypass)1731 static inline void CLOCK_SetPllBypass(CCM_ANALOG_Type *base, clock_pll_t pll, bool bypass)
1732 {
1733 if (bypass)
1734 {
1735 CCM_ANALOG_TUPLE_REG_OFF(base, pll, 4U) = 1UL << CCM_ANALOG_PLL_BYPASS_SHIFT;
1736 }
1737 else
1738 {
1739 CCM_ANALOG_TUPLE_REG_OFF(base, pll, 8U) = 1UL << CCM_ANALOG_PLL_BYPASS_SHIFT;
1740 }
1741 }
1742
1743 /*!
1744 * @brief Check if PLL is bypassed
1745 *
1746 * @param base CCM_ANALOG base pointer.
1747 * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration)
1748 * @return PLL bypass status.
1749 * - true: The PLL is bypassed.
1750 * - false: The PLL is not bypassed.
1751 */
CLOCK_IsPllBypassed(CCM_ANALOG_Type * base,clock_pll_t pll)1752 static inline bool CLOCK_IsPllBypassed(CCM_ANALOG_Type *base, clock_pll_t pll)
1753 {
1754 return (bool)(CCM_ANALOG_TUPLE_REG(base, pll) & (1UL << CCM_ANALOG_PLL_BYPASS_SHIFT));
1755 }
1756
1757 /*!
1758 * @brief Check if PLL is enabled
1759 *
1760 * @param base CCM_ANALOG base pointer.
1761 * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration)
1762 * @return PLL bypass status.
1763 * - true: The PLL is enabled.
1764 * - false: The PLL is not enabled.
1765 */
CLOCK_IsPllEnabled(CCM_ANALOG_Type * base,clock_pll_t pll)1766 static inline bool CLOCK_IsPllEnabled(CCM_ANALOG_Type *base, clock_pll_t pll)
1767 {
1768 return ((CCM_ANALOG_TUPLE_REG(base, pll) & (1UL << CCM_ANALOG_TUPLE_SHIFT(pll))) != 0U);
1769 }
1770
1771 /*!
1772 * @brief PLL bypass clock source setting.
1773 * Note: change the bypass clock source also change the pll reference clock source.
1774 *
1775 * @param base CCM_ANALOG base pointer.
1776 * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration)
1777 * @param src Bypass clock source, reference _clock_pll_bypass_clk_src.
1778 */
CLOCK_SetPllBypassRefClkSrc(CCM_ANALOG_Type * base,clock_pll_t pll,uint32_t src)1779 static inline void CLOCK_SetPllBypassRefClkSrc(CCM_ANALOG_Type *base, clock_pll_t pll, uint32_t src)
1780 {
1781 CCM_ANALOG_TUPLE_REG(base, pll) |= (CCM_ANALOG_TUPLE_REG(base, pll) & (~CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK)) | src;
1782 }
1783
1784 /*!
1785 * @brief Get PLL bypass clock value, it is PLL reference clock actually.
1786 * If CLOCK1_P,CLOCK1_N is choose as the pll bypass clock source, please implement the CLKPN_FREQ define, otherwise 0
1787 * will be returned.
1788 * @param base CCM_ANALOG base pointer.
1789 * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration)
1790 * @retval bypass reference clock frequency value.
1791 */
CLOCK_GetPllBypassRefClk(CCM_ANALOG_Type * base,clock_pll_t pll)1792 static inline uint32_t CLOCK_GetPllBypassRefClk(CCM_ANALOG_Type *base, clock_pll_t pll)
1793 {
1794 return (((CCM_ANALOG_TUPLE_REG(base, pll) & CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK) >>
1795 CCM_ANALOG_PLL_BYPASS_CLK_SRC_SHIFT) == (uint32_t)kCLOCK_PllClkSrc24M) ?
1796 CLOCK_GetOscFreq() :
1797 CLKPN_FREQ;
1798 }
1799
1800 /*!
1801 * @brief Initialize the ARM PLL.
1802 *
1803 * This function initialize the ARM PLL with specific settings
1804 *
1805 * @param config configuration to set to PLL.
1806 */
1807 void CLOCK_InitArmPll(const clock_arm_pll_config_t *config);
1808
1809 /*!
1810 * @brief De-initialize the ARM PLL.
1811 */
1812 void CLOCK_DeinitArmPll(void);
1813
1814 /*!
1815 * @brief Initialize the System PLL.
1816 *
1817 * This function initializes the System PLL with specific settings
1818 *
1819 * @param config Configuration to set to PLL.
1820 */
1821 void CLOCK_InitSysPll(const clock_sys_pll_config_t *config);
1822
1823 /*!
1824 * @brief De-initialize the System PLL.
1825 */
1826 void CLOCK_DeinitSysPll(void);
1827
1828 /*!
1829 * @brief Initialize the USB1 PLL.
1830 *
1831 * This function initializes the USB1 PLL with specific settings
1832 *
1833 * @param config Configuration to set to PLL.
1834 */
1835 void CLOCK_InitUsb1Pll(const clock_usb_pll_config_t *config);
1836
1837 /*!
1838 * @brief Deinitialize the USB1 PLL.
1839 */
1840 void CLOCK_DeinitUsb1Pll(void);
1841
1842 /*!
1843 * @brief Initialize the USB2 PLL.
1844 *
1845 * This function initializes the USB2 PLL with specific settings
1846 *
1847 * @param config Configuration to set to PLL.
1848 */
1849 void CLOCK_InitUsb2Pll(const clock_usb_pll_config_t *config);
1850
1851 /*!
1852 * @brief Deinitialize the USB2 PLL.
1853 */
1854 void CLOCK_DeinitUsb2Pll(void);
1855
1856 /*!
1857 * @brief Initializes the Audio PLL.
1858 *
1859 * This function initializes the Audio PLL with specific settings
1860 *
1861 * @param config Configuration to set to PLL.
1862 */
1863 void CLOCK_InitAudioPll(const clock_audio_pll_config_t *config);
1864
1865 /*!
1866 * @brief De-initialize the Audio PLL.
1867 */
1868 void CLOCK_DeinitAudioPll(void);
1869
1870 /*!
1871 * @brief Initialize the video PLL.
1872 *
1873 * This function configures the Video PLL with specific settings
1874 *
1875 * @param config configuration to set to PLL.
1876 */
1877 void CLOCK_InitVideoPll(const clock_video_pll_config_t *config);
1878
1879 /*!
1880 * @brief De-initialize the Video PLL.
1881 */
1882 void CLOCK_DeinitVideoPll(void);
1883 /*!
1884 * @brief Initialize the ENET PLL.
1885 *
1886 * This function initializes the ENET PLL with specific settings.
1887 *
1888 * @param config Configuration to set to PLL.
1889 */
1890 void CLOCK_InitEnetPll(const clock_enet_pll_config_t *config);
1891
1892 /*!
1893 * @brief Deinitialize the ENET PLL.
1894 *
1895 * This function disables the ENET PLL.
1896 */
1897 void CLOCK_DeinitEnetPll(void);
1898
1899 /*!
1900 * @brief Get current PLL output frequency.
1901 *
1902 * This function get current output frequency of specific PLL
1903 *
1904 * @param pll pll name to get frequency.
1905 * @return The PLL output frequency in hertz.
1906 */
1907 uint32_t CLOCK_GetPllFreq(clock_pll_t pll);
1908
1909 /*!
1910 * @brief Initialize the System PLL PFD.
1911 *
1912 * This function initializes the System PLL PFD. During new value setting,
1913 * the clock output is disabled to prevent glitch.
1914 *
1915 * @param pfd Which PFD clock to enable.
1916 * @param pfdFrac The PFD FRAC value.
1917 * @note It is recommended that PFD settings are kept between 12-35.
1918 */
1919 void CLOCK_InitSysPfd(clock_pfd_t pfd, uint8_t pfdFrac);
1920
1921 /*!
1922 * @brief De-initialize the System PLL PFD.
1923 *
1924 * This function disables the System PLL PFD.
1925 *
1926 * @param pfd Which PFD clock to disable.
1927 */
1928 void CLOCK_DeinitSysPfd(clock_pfd_t pfd);
1929
1930 /*!
1931 * @brief Check if Sys PFD is enabled
1932 *
1933 * @param pfd PFD control name
1934 * @return PFD bypass status.
1935 * - true: power on.
1936 * - false: power off.
1937 */
1938 bool CLOCK_IsSysPfdEnabled(clock_pfd_t pfd);
1939
1940 /*!
1941 * @brief Initialize the USB1 PLL PFD.
1942 *
1943 * This function initializes the USB1 PLL PFD. During new value setting,
1944 * the clock output is disabled to prevent glitch.
1945 *
1946 * @param pfd Which PFD clock to enable.
1947 * @param pfdFrac The PFD FRAC value.
1948 * @note It is recommended that PFD settings are kept between 12-35.
1949 */
1950 void CLOCK_InitUsb1Pfd(clock_pfd_t pfd, uint8_t pfdFrac);
1951
1952 /*!
1953 * @brief De-initialize the USB1 PLL PFD.
1954 *
1955 * This function disables the USB1 PLL PFD.
1956 *
1957 * @param pfd Which PFD clock to disable.
1958 */
1959 void CLOCK_DeinitUsb1Pfd(clock_pfd_t pfd);
1960
1961 /*!
1962 * @brief Check if Usb1 PFD is enabled
1963 *
1964 * @param pfd PFD control name.
1965 * @return PFD bypass status.
1966 * - true: power on.
1967 * - false: power off.
1968 */
1969 bool CLOCK_IsUsb1PfdEnabled(clock_pfd_t pfd);
1970
1971 /*!
1972 * @brief Get current System PLL PFD output frequency.
1973 *
1974 * This function get current output frequency of specific System PLL PFD
1975 *
1976 * @param pfd pfd name to get frequency.
1977 * @return The PFD output frequency in hertz.
1978 */
1979 uint32_t CLOCK_GetSysPfdFreq(clock_pfd_t pfd);
1980
1981 /*!
1982 * @brief Get current USB1 PLL PFD output frequency.
1983 *
1984 * This function get current output frequency of specific USB1 PLL PFD
1985 *
1986 * @param pfd pfd name to get frequency.
1987 * @return The PFD output frequency in hertz.
1988 */
1989 uint32_t CLOCK_GetUsb1PfdFreq(clock_pfd_t pfd);
1990
1991 /*! @brief Enable USB HS PHY PLL clock.
1992 *
1993 * This function enables the internal 480MHz USB PHY PLL clock.
1994 *
1995 * @param src USB HS PHY PLL clock source.
1996 * @param freq The frequency specified by src.
1997 * @retval true The clock is set successfully.
1998 * @retval false The clock source is invalid to get proper USB HS clock.
1999 */
2000 bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq);
2001
2002 /*! @brief Disable USB HS PHY PLL clock.
2003 *
2004 * This function disables USB HS PHY PLL clock.
2005 */
2006 void CLOCK_DisableUsbhs0PhyPllClock(void);
2007
2008 /*! @brief Enable USB HS PHY PLL clock.
2009 *
2010 * This function enables the internal 480MHz USB PHY PLL clock.
2011 *
2012 * @param src USB HS PHY PLL clock source.
2013 * @param freq The frequency specified by src.
2014 * @retval true The clock is set successfully.
2015 * @retval false The clock source is invalid to get proper USB HS clock.
2016 */
2017 bool CLOCK_EnableUsbhs1PhyPllClock(clock_usb_phy_src_t src, uint32_t freq);
2018
2019 /*! @brief Disable USB HS PHY PLL clock.
2020 *
2021 * This function disables USB HS PHY PLL clock.
2022 */
2023 void CLOCK_DisableUsbhs1PhyPllClock(void);
2024
2025 /* @} */
2026
2027 /*!
2028 * @name Clock Output Inferfaces
2029 * @{
2030 */
2031
2032 /*!
2033 * @brief Set the clock source and the divider of the clock output1.
2034 *
2035 * @param selection The clock source to be output, please refer to @ref clock_output1_selection_t.
2036 * @param divider The divider of the output clock signal, please refer to @ref clock_output_divider_t.
2037 */
2038 void CLOCK_SetClockOutput1(clock_output1_selection_t selection, clock_output_divider_t divider);
2039
2040 /*!
2041 * @brief Set the clock source and the divider of the clock output2.
2042 *
2043 * @param selection The clock source to be output, please refer to @ref clock_output2_selection_t.
2044 * @param divider The divider of the output clock signal, please refer to @ref clock_output_divider_t.
2045 */
2046 void CLOCK_SetClockOutput2(clock_output2_selection_t selection, clock_output_divider_t divider);
2047
2048 /*!
2049 * @brief Get the frequency of clock output1 clock signal.
2050 *
2051 * @return The frequency of clock output1 clock signal.
2052 */
2053 uint32_t CLOCK_GetClockOutCLKO1Freq(void);
2054
2055 /*!
2056 * @brief Get the frequency of clock output2 clock signal.
2057 *
2058 * @return The frequency of clock output2 clock signal.
2059 */
2060 uint32_t CLOCK_GetClockOutClkO2Freq(void);
2061
2062 /*! @} */
2063
2064 #if defined(__cplusplus)
2065 }
2066 #endif /* __cplusplus */
2067
2068 /*! @} */
2069
2070 #endif /* _FSL_CLOCK_H_ */
2071
