1 /*
2 * Copyright 2020 - 2021, 2024 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #ifndef _FSL_CLOCK_H_
9 #define _FSL_CLOCK_H_
10
11 #include "fsl_common.h"
12
13 /*! @addtogroup clock */
14 /*! @{ */
15
16 /*! @file */
17
18 /*******************************************************************************
19 * Configurations
20 ******************************************************************************/
21
22 /*! @brief Configure whether driver controls clock
23 *
24 * When set to 0, peripheral drivers will enable clock in initialize function
25 * and disable clock in de-initialize function. When set to 1, peripheral
26 * driver will not control the clock, application could control the clock out of
27 * the driver.
28 *
29 * @note All drivers share this feature switcher. If it is set to 1, application
30 * should handle clock enable and disable for all drivers.
31 */
32 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL))
33 #define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0
34 #endif
35
36 /*******************************************************************************
37 * Definitions
38 ******************************************************************************/
39
40 /*! @name Driver version */
41 /*@{*/
42 /*! @brief CLOCK driver version 2.5.3. */
43 #define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 5, 3))
44
45 /* Definition for delay API in clock driver, users can redefine it to the real application. */
46 #ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
47 #define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (500000000UL)
48 #endif
49
50 /* analog pll definition */
51 #define CCM_ANALOG_PLL_BYPASS_SHIFT (16U)
52 #define CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK (0xC000U)
53 #define CCM_ANALOG_PLL_BYPASS_CLK_SRC_SHIFT (14U)
54
55 /*@}*/
56
57 /*!
58 * @brief CCM registers offset.
59 */
60 #define CCSR_OFFSET 0x0C
61 #define CBCDR_OFFSET 0x14
62 #define CBCMR_OFFSET 0x18
63 #define CSCMR1_OFFSET 0x1C
64 #define CSCMR2_OFFSET 0x20
65 #define CSCDR1_OFFSET 0x24
66 #define CDCDR_OFFSET 0x30
67 #define CSCDR2_OFFSET 0x38
68 #define CACRR_OFFSET 0x10
69 #define CS1CDR_OFFSET 0x28
70 #define CS2CDR_OFFSET 0x2C
71
72 /*!
73 * @brief CCM Analog registers offset.
74 */
75 #define PLL_SYS_OFFSET 0x30
76 #define PLL_USB1_OFFSET 0x10
77 #define PLL_AUDIO_OFFSET 0x70
78 #define PLL_ENET_OFFSET 0xE0
79
80 #define CCM_TUPLE(reg, shift, mask, busyShift) \
81 (int)(((reg)&0xFFU) | ((shift) << 8U) | ((((mask) >> (shift)) & 0x1FFFU) << 13U) | ((busyShift) << 26U))
82 #define CCM_TUPLE_REG(base, tuple) (*((volatile uint32_t *)(((uint32_t)(base)) + (((uint32_t)tuple) & 0xFFU))))
83 #define CCM_TUPLE_SHIFT(tuple) ((((uint32_t)tuple) >> 8U) & 0x1FU)
84 #define CCM_TUPLE_MASK(tuple) \
85 ((uint32_t)(((((uint32_t)tuple) >> 13U) & 0x1FFFU) << (((((uint32_t)tuple) >> 8U) & 0x1FU))))
86 #define CCM_TUPLE_BUSY_SHIFT(tuple) ((((uint32_t)tuple) >> 26U) & 0x3FU)
87
88 #define CCM_NO_BUSY_WAIT (0x20U)
89
90 /*!
91 * @brief CCM ANALOG tuple macros to map corresponding registers and bit fields.
92 */
93 #define CCM_ANALOG_TUPLE(reg, shift) ((((reg)&0xFFFU) << 16U) | (shift))
94 #define CCM_ANALOG_TUPLE_SHIFT(tuple) (((uint32_t)(tuple)) & 0x1FU)
95 #define CCM_ANALOG_TUPLE_REG_OFF(base, tuple, off) \
96 (*((volatile uint32_t *)((uint32_t)(base) + (((uint32_t)(tuple) >> 16U) & 0xFFFU) + (off))))
97 #define CCM_ANALOG_TUPLE_REG(base, tuple) CCM_ANALOG_TUPLE_REG_OFF(base, tuple, 0U)
98
99 #define CCM_ANALOG_PLL_BYPASS_SHIFT (16U)
100 #define CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK (0xC000U)
101 #define CCM_ANALOG_PLL_BYPASS_CLK_SRC_SHIFT (14U)
102
103 /* Definition for delay API in clock driver, users can redefine it to the real application. */
104 #ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
105 #define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (500000000UL)
106 #endif
107
108 /* Definition for ERRATA 50235 check */
109 #if (defined(FSL_FEATURE_CCM_HAS_ERRATA_50235) && FSL_FEATURE_CCM_HAS_ERRATA_50235)
110 #define CAN_CLOCK_CHECK_NO_AFFECTS \
111 ((CCM_CSCMR2_CAN_CLK_SEL(2U) != (CCM->CSCMR2 & CCM_CSCMR2_CAN_CLK_SEL_MASK)) || \
112 (CCM_CCGR5_CG12(0) != (CCM->CCGR5 & CCM_CCGR5_CG12_MASK)))
113 #endif /* FSL_FEATURE_CCM_HAS_ERRATA_50235 */
114 /*!
115 * @brief clock1PN frequency.
116 */
117 #define CLKPN_FREQ 0U
118
119 /*! @brief External XTAL (24M OSC/SYSOSC) clock frequency.
120 *
121 * The XTAL (24M OSC/SYSOSC) clock frequency in Hz, when the clock is setup, use the
122 * function CLOCK_SetXtalFreq to set the value in to clock driver. For example,
123 * if XTAL is 24MHz,
124 * @code
125 * CLOCK_InitExternalClk(false);
126 * CLOCK_SetXtalFreq(240000000);
127 * @endcode
128 */
129 extern volatile uint32_t g_xtalFreq;
130
131 /*! @brief External RTC XTAL (32K OSC) clock frequency.
132 *
133 * The RTC XTAL (32K OSC) clock frequency in Hz, when the clock is setup, use the
134 * function CLOCK_SetRtcXtalFreq to set the value in to clock driver.
135 */
136 extern volatile uint32_t g_rtcXtalFreq;
137
138 /* For compatible with other platforms */
139 #define CLOCK_SetXtal0Freq CLOCK_SetXtalFreq
140 #define CLOCK_SetXtal32Freq CLOCK_SetRtcXtalFreq
141
142 /*! @brief Clock ip name array for ADC. */
143 #define ADC_CLOCKS \
144 { \
145 kCLOCK_IpInvalid, kCLOCK_Adc1, kCLOCK_Adc2 \
146 }
147
148 /*! @brief Clock ip name array for AOI. */
149 #define AOI_CLOCKS \
150 { \
151 kCLOCK_Aoi \
152 }
153
154 /*! @brief Clock ip name array for BEE. */
155 #define BEE_CLOCKS \
156 { \
157 kCLOCK_Bee \
158 }
159
160 /*! @brief Clock ip name array for CMP. */
161 #define CMP_CLOCKS \
162 { \
163 kCLOCK_IpInvalid, kCLOCK_Acmp1, kCLOCK_Acmp2, kCLOCK_Acmp3, kCLOCK_Acmp4 \
164 }
165
166 /*! @brief Clock ip name array for DCDC. */
167 #define DCDC_CLOCKS \
168 { \
169 kCLOCK_Dcdc \
170 }
171
172 /*! @brief Clock ip name array for DCP. */
173 #define DCP_CLOCKS \
174 { \
175 kCLOCK_Dcp \
176 }
177
178 /*! @brief Clock ip name array for DMAMUX_CLOCKS. */
179 #define DMAMUX_CLOCKS \
180 { \
181 kCLOCK_Dma \
182 }
183
184 /*! @brief Clock ip name array for DMA. */
185 #define EDMA_CLOCKS \
186 { \
187 kCLOCK_Dma \
188 }
189
190 /*! @brief Clock ip name array for ENC. */
191 #define ENC_CLOCKS \
192 { \
193 kCLOCK_IpInvalid, kCLOCK_Enc1, kCLOCK_Enc2 \
194 }
195
196 /*! @brief Clock ip name array for ENET. */
197 #define ENET_CLOCKS \
198 { \
199 kCLOCK_Enet \
200 }
201
202 /*! @brief Clock ip name array for EWM. */
203 #define EWM_CLOCKS \
204 { \
205 kCLOCK_Ewm0 \
206 }
207
208 /*! @brief Clock ip name array for FLEXCAN. */
209 #define FLEXCAN_CLOCKS \
210 { \
211 kCLOCK_IpInvalid, kCLOCK_Can1, kCLOCK_Can2 \
212 }
213
214 /*! @brief Clock ip name array for FLEXCAN Peripheral clock. */
215 #define FLEXCAN_PERIPH_CLOCKS \
216 { \
217 kCLOCK_IpInvalid, kCLOCK_Can1S, kCLOCK_Can2S \
218 }
219
220 /*! @brief Clock ip name array for FLEXIO. */
221 #define FLEXIO_CLOCKS \
222 { \
223 kCLOCK_IpInvalid, kCLOCK_Flexio1 \
224 }
225
226 /*! @brief Clock ip name array for FLEXRAM. */
227 #define FLEXRAM_CLOCKS \
228 { \
229 kCLOCK_FlexRam \
230 }
231
232 /*! @brief Clock ip name array for FLEXSPI. */
233 #define FLEXSPI_CLOCKS \
234 { \
235 kCLOCK_FlexSpi \
236 }
237
238 /*! @brief Clock ip name array for FLEXSPI EXSC. */
239 #define FLEXSPI_EXSC_CLOCKS \
240 { \
241 kCLOCK_FlexSpiExsc \
242 }
243
244 /*! @brief Clock ip name array for GPIO. */
245 #define GPIO_CLOCKS \
246 { \
247 kCLOCK_IpInvalid, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3, kCLOCK_IpInvalid, kCLOCK_Gpio5 \
248 }
249
250 /*! @brief Clock ip name array for GPT. */
251 #define GPT_CLOCKS \
252 { \
253 kCLOCK_IpInvalid, kCLOCK_Gpt1, kCLOCK_Gpt2 \
254 }
255
256 /*! @brief Clock ip name array for KPP. */
257 #define KPP_CLOCKS \
258 { \
259 kCLOCK_Kpp \
260 }
261
262 /*! @brief Clock ip name array for LPI2C. */
263 #define LPI2C_CLOCKS \
264 { \
265 kCLOCK_IpInvalid, kCLOCK_Lpi2c1, kCLOCK_Lpi2c2, kCLOCK_Lpi2c3, kCLOCK_Lpi2c4 \
266 }
267
268 /*! @brief Clock ip name array for LPSPI. */
269 #define LPSPI_CLOCKS \
270 { \
271 kCLOCK_IpInvalid, kCLOCK_Lpspi1, kCLOCK_Lpspi2, kCLOCK_Lpspi3, kCLOCK_Lpspi4 \
272 }
273
274 /*! @brief Clock ip name array for LPUART. */
275 #define LPUART_CLOCKS \
276 { \
277 kCLOCK_IpInvalid, kCLOCK_Lpuart1, kCLOCK_Lpuart2, kCLOCK_Lpuart3, kCLOCK_Lpuart4, kCLOCK_Lpuart5, \
278 kCLOCK_Lpuart6, kCLOCK_Lpuart7, kCLOCK_Lpuart8 \
279 }
280
281 /*! @brief Clock ip name array for OCRAM EXSC. */
282 #define OCRAM_EXSC_CLOCKS \
283 { \
284 kCLOCK_OcramExsc \
285 }
286
287 /*! @brief Clock ip name array for PIT. */
288 #define PIT_CLOCKS \
289 { \
290 kCLOCK_Pit \
291 }
292
293 /*! @brief Clock ip name array for PWM. */
294 #define PWM_CLOCKS \
295 { \
296 {kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid}, \
297 {kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1}, \
298 { \
299 kCLOCK_Pwm2, kCLOCK_Pwm2, kCLOCK_Pwm2, kCLOCK_Pwm2 \
300 } \
301 }
302
303 /*! @brief Clock ip name array for RTWDOG. */
304 #define RTWDOG_CLOCKS \
305 { \
306 kCLOCK_Wdog3 \
307 }
308
309 /*! @brief Clock ip name array for SAI. */
310 #define SAI_CLOCKS \
311 { \
312 kCLOCK_IpInvalid, kCLOCK_Sai1, kCLOCK_Sai2, kCLOCK_Sai3 \
313 }
314
315 /*! @brief Clock ip name array for SEMC. */
316 #define SEMC_CLOCKS \
317 { \
318 kCLOCK_Semc \
319 }
320
321 /*! @brief Clock ip name array for SEMC EXSC. */
322 #define SEMC_EXSC_CLOCKS \
323 { \
324 kCLOCK_SemcExsc \
325 }
326
327 /*! @brief Clock ip name array for QTIMER. */
328 #define TMR_CLOCKS \
329 { \
330 kCLOCK_IpInvalid, kCLOCK_Timer1, kCLOCK_Timer2 \
331 }
332
333 /*! @brief Clock ip name array for TRNG. */
334 #define TRNG_CLOCKS \
335 { \
336 kCLOCK_Trng \
337 }
338
339 /*! @brief Clock ip name array for WDOG. */
340 #define WDOG_CLOCKS \
341 { \
342 kCLOCK_IpInvalid, kCLOCK_Wdog1, kCLOCK_Wdog2 \
343 }
344
345 /*! @brief Clock ip name array for USDHC. */
346 #define USDHC_CLOCKS \
347 { \
348 kCLOCK_IpInvalid, kCLOCK_Usdhc1, kCLOCK_Usdhc2 \
349 }
350
351 /*! @brief Clock ip name array for SPDIF. */
352 #define SPDIF_CLOCKS \
353 { \
354 kCLOCK_Spdif \
355 }
356
357 /*! @brief Clock ip name array for XBARA. */
358 #define XBARA_CLOCKS \
359 { \
360 kCLOCK_Xbar1 \
361 }
362
363 /*! @brief Clock ip name array for XBARB. */
364 #define XBARB_CLOCKS \
365 { \
366 kCLOCK_Xbar2 \
367 }
368
369 #define CLOCK_SOURCE_NONE (0xFFU)
370
371 #define CLOCK_ROOT_SOUCE \
372 { \
373 {kCLOCK_SysPllPfd2Clk, kCLOCK_SysPllPfd0Clk, kCLOCK_NoneName, kCLOCK_NoneName}, /*!< USDHC1 clock root. */ \
374 {kCLOCK_SysPllPfd2Clk, kCLOCK_SysPllPfd0Clk, kCLOCK_NoneName, kCLOCK_NoneName}, /*!< USDHC2 clock root. */ \
375 {kCLOCK_SemcClk, kCLOCK_Usb1SwClk, kCLOCK_SysPllPfd2Clk, \
376 kCLOCK_Usb1PllPfd0Clk}, /*!< FLEXSPI clock root. */ \
377 {kCLOCK_Usb1PllPfd1Clk, kCLOCK_Usb1PllPfd0Clk, kCLOCK_SysPllClk, \
378 kCLOCK_SysPllPfd2Clk}, /*!< LPSPI clock root. */ \
379 {kCLOCK_SysPllClk, kCLOCK_SysPllPfd2Clk, kCLOCK_SysPllPfd0Clk, \
380 kCLOCK_SysPllPfd1Clk}, /*!< Trace clock root. */ \
381 {kCLOCK_Usb1PllPfd2Clk, kCLOCK_NoneName, kCLOCK_AudioPllClk, kCLOCK_NoneName}, /*!< SAI1 clock root. */ \
382 {kCLOCK_Usb1PllPfd2Clk, kCLOCK_NoneName, kCLOCK_AudioPllClk, kCLOCK_NoneName}, /*!< SAI2 clock root. */ \
383 {kCLOCK_Usb1PllPfd2Clk, kCLOCK_NoneName, kCLOCK_AudioPllClk, kCLOCK_NoneName}, /*!< SAI3 clock root. */ \
384 {kCLOCK_Usb1Sw60MClk, kCLOCK_OscClk, kCLOCK_NoneName, kCLOCK_NoneName}, /*!< LPI2C clock root. */ \
385 {kCLOCK_Usb1Sw60MClk, kCLOCK_OscClk, kCLOCK_Usb1Sw80MClk, kCLOCK_NoneName}, /*!< CAN clock root. */ \
386 {kCLOCK_Usb1Sw80MClk, kCLOCK_OscClk, kCLOCK_NoneName, kCLOCK_NoneName}, /*!< UART clock root. */ \
387 {kCLOCK_AudioPllClk, kCLOCK_Usb1PllPfd2Clk, kCLOCK_NoneName, kCLOCK_Usb1SwClk}, /*!< SPDIF clock root. */ \
388 { \
389 kCLOCK_AudioPllClk, \
390 kCLOCK_Usb1PllPfd2Clk, \
391 kCLOCK_NoneName, \
392 kCLOCK_Usb1SwClk, \
393 }, /*!< FLEXIO1 clock root. */ \
394 }
395
396 #define CLOCK_ROOT_MUX_TUPLE \
397 { \
398 kCLOCK_Usdhc1Mux, kCLOCK_Usdhc2Mux, kCLOCK_FlexspiMux, kCLOCK_LpspiMux, kCLOCK_TraceMux, kCLOCK_Sai1Mux, \
399 kCLOCK_Sai2Mux, kCLOCK_Sai3Mux, kCLOCK_Lpi2cMux, kCLOCK_CanMux, kCLOCK_UartMux, kCLOCK_SpdifMux, \
400 kCLOCK_Flexio1Mux, \
401 }
402
403 #define CLOCK_ROOT_NONE_PRE_DIV 0UL
404
405 #define CLOCK_ROOT_DIV_TUPLE \
406 { \
407 {kCLOCK_NonePreDiv, kCLOCK_Usdhc1Div}, /*!< USDHC1 clock root. */ \
408 {kCLOCK_NonePreDiv, kCLOCK_Usdhc2Div}, /*!< USDHC2 clock root. */ \
409 {kCLOCK_NonePreDiv, kCLOCK_FlexspiDiv}, /*!< FLEXSPI clock root. */ \
410 {kCLOCK_NonePreDiv, kCLOCK_LpspiDiv}, /*!< LPSPI clock root. */ \
411 {kCLOCK_NonePreDiv, kCLOCK_TraceDiv}, /*!< Trace clock root. */ \
412 {kCLOCK_Sai1PreDiv, kCLOCK_Sai1Div}, /*!< SAI1 clock root. */ \
413 {kCLOCK_Sai2PreDiv, kCLOCK_Sai2Div}, /*!< SAI2 clock root. */ \
414 {kCLOCK_Sai3PreDiv, kCLOCK_Sai3Div}, /*!< SAI3 clock root. */ \
415 {kCLOCK_NonePreDiv, kCLOCK_Lpi2cDiv}, /*!< LPI2C clock root. */ \
416 {kCLOCK_NonePreDiv, kCLOCK_CanDiv}, /*!< CAN clock root. */ \
417 {kCLOCK_NonePreDiv, kCLOCK_UartDiv}, /*!< UART clock root. */ \
418 {kCLOCK_Spdif0PreDiv, kCLOCK_Spdif0Div}, /*!< SPDIF clock root. */ \
419 {kCLOCK_Flexio1PreDiv, kCLOCK_Flexio1Div}, /*!< FLEXIO1 clock root. */ \
420 }
421
422 /*! @brief Clock name used to get clock frequency. */
423 typedef enum _clock_name
424 {
425 kCLOCK_CpuClk = 0x0U, /*!< CPU clock */
426 kCLOCK_AhbClk = 0x1U, /*!< AHB clock */
427 kCLOCK_SemcClk = 0x2U, /*!< SEMC clock */
428 kCLOCK_IpgClk = 0x3U, /*!< IPG clock */
429 kCLOCK_PerClk = 0x4U, /*!< PER clock */
430
431 kCLOCK_OscClk = 0x5U, /*!< OSC clock selected by PMU_LOWPWR_CTRL[OSC_SEL]. */
432 kCLOCK_RtcClk = 0x6U, /*!< RTC clock. (RTCCLK) */
433
434 kCLOCK_Usb1PllClk = 0x7U, /*!< USB1PLLCLK. */
435 kCLOCK_Usb1PllPfd0Clk = 0x8U, /*!< USB1PLLPDF0CLK. */
436 kCLOCK_Usb1PllPfd1Clk = 0x9U, /*!< USB1PLLPFD1CLK. */
437 kCLOCK_Usb1PllPfd2Clk = 0xAU, /*!< USB1PLLPFD2CLK. */
438 kCLOCK_Usb1PllPfd3Clk = 0xBU, /*!< USB1PLLPFD3CLK. */
439 kCLOCK_Usb1SwClk = 0x15U, /*!< USB1PLLSWCLK */
440 kCLOCK_Usb1Sw60MClk = 0x16U, /*!< USB1PLLSw60MCLK */
441 kCLOCK_Usb1Sw80MClk = 0x1BU, /*!< USB1PLLSw80MCLK */
442
443 kCLOCK_SysPllClk = 0xCU, /*!< SYSPLLCLK. */
444 kCLOCK_SysPllPfd0Clk = 0xDU, /*!< SYSPLLPDF0CLK. */
445 kCLOCK_SysPllPfd1Clk = 0xEU, /*!< SYSPLLPFD1CLK. */
446 kCLOCK_SysPllPfd2Clk = 0xFU, /*!< SYSPLLPFD2CLK. */
447 kCLOCK_SysPllPfd3Clk = 0x10U, /*!< SYSPLLPFD3CLK. */
448
449 kCLOCK_EnetPllClk = 0x11U, /*!< Enet PLLCLK ref_enetpll. */
450 kCLOCK_EnetPll25MClk = 0x12U, /*!< Enet PLLCLK ref_enetpll25M. */
451 kCLOCK_EnetPll500MClk = 0x13U, /*!< Enet PLLCLK ref_enetpll500M. */
452
453 kCLOCK_AudioPllClk = 0x14U, /*!< Audio PLLCLK. */
454
455 kCLOCK_NoneName = CLOCK_SOURCE_NONE, /*!< None Clock Name. */
456 } clock_name_t;
457
458 #define kCLOCK_CoreSysClk kCLOCK_CpuClk /*!< For compatible with other platforms without CCM. */
459 #define CLOCK_GetCoreSysClkFreq CLOCK_GetCpuClkFreq /*!< For compatible with other platforms without CCM. */
460
461 /*!
462 * @brief CCM CCGR gate control for each module independently.
463 */
464 typedef enum _clock_ip_name
465 {
466 kCLOCK_IpInvalid = -1,
467
468 /* CCM CCGR0 */
469 kCLOCK_Aips_tz1 = (0U << 8U) | CCM_CCGR0_CG0_SHIFT, /*!< CCGR0, CG0 */
470 kCLOCK_Aips_tz2 = (0U << 8U) | CCM_CCGR0_CG1_SHIFT, /*!< CCGR0, CG1 */
471 kCLOCK_Mqs = (0U << 8U) | CCM_CCGR0_CG2_SHIFT, /*!< CCGR0, CG2, Reserved */
472 kCLOCK_FlexSpiExsc = (0U << 8U) | CCM_CCGR0_CG3_SHIFT, /*!< CCGR0, CG3 */
473 kCLOCK_Sim_m_clk_r = (0U << 8U) | CCM_CCGR0_CG4_SHIFT, /*!< CCGR0, CG4 */
474 kCLOCK_Dcp = (0U << 8U) | CCM_CCGR0_CG5_SHIFT, /*!< CCGR0, CG5 */
475 kCLOCK_Lpuart3 = (0U << 8U) | CCM_CCGR0_CG6_SHIFT, /*!< CCGR0, CG6 */
476 kCLOCK_Can1 = (0U << 8U) | CCM_CCGR0_CG7_SHIFT, /*!< CCGR0, CG7 */
477 kCLOCK_Can1S = (0U << 8U) | CCM_CCGR0_CG8_SHIFT, /*!< CCGR0, CG8 */
478 kCLOCK_Can2 = (0U << 8U) | CCM_CCGR0_CG9_SHIFT, /*!< CCGR0, CG9 */
479 kCLOCK_Can2S = (0U << 8U) | CCM_CCGR0_CG10_SHIFT, /*!< CCGR0, CG10 */
480 kCLOCK_Trace = (0U << 8U) | CCM_CCGR0_CG11_SHIFT, /*!< CCGR0, CG11 */
481 kCLOCK_Gpt2 = (0U << 8U) | CCM_CCGR0_CG12_SHIFT, /*!< CCGR0, CG12 */
482 kCLOCK_Gpt2S = (0U << 8U) | CCM_CCGR0_CG13_SHIFT, /*!< CCGR0, CG13 */
483 kCLOCK_Lpuart2 = (0U << 8U) | CCM_CCGR0_CG14_SHIFT, /*!< CCGR0, CG14 */
484 kCLOCK_Gpio2 = (0U << 8U) | CCM_CCGR0_CG15_SHIFT, /*!< CCGR0, CG15 */
485
486 /* CCM CCGR1 */
487 kCLOCK_Lpspi1 = (1U << 8U) | CCM_CCGR1_CG0_SHIFT, /*!< CCGR1, CG0 */
488 kCLOCK_Lpspi2 = (1U << 8U) | CCM_CCGR1_CG1_SHIFT, /*!< CCGR1, CG1 */
489 kCLOCK_Lpspi3 = (1U << 8U) | CCM_CCGR1_CG2_SHIFT, /*!< CCGR1, CG2 */
490 kCLOCK_Lpspi4 = (1U << 8U) | CCM_CCGR1_CG3_SHIFT, /*!< CCGR1, CG3 */
491 kCLOCK_Adc2 = (1U << 8U) | CCM_CCGR1_CG4_SHIFT, /*!< CCGR1, CG4 */
492 kCLOCK_Enet = (1U << 8U) | CCM_CCGR1_CG5_SHIFT, /*!< CCGR1, CG5 */
493 kCLOCK_Pit = (1U << 8U) | CCM_CCGR1_CG6_SHIFT, /*!< CCGR1, CG6 */
494 kCLOCK_Adc1 = (1U << 8U) | CCM_CCGR1_CG8_SHIFT, /*!< CCGR1, CG8 */
495 kCLOCK_SemcExsc = (1U << 8U) | CCM_CCGR1_CG9_SHIFT, /*!< CCGR1, CG9 */
496 kCLOCK_Gpt1 = (1U << 8U) | CCM_CCGR1_CG10_SHIFT, /*!< CCGR1, CG10 */
497 kCLOCK_Gpt1S = (1U << 8U) | CCM_CCGR1_CG11_SHIFT, /*!< CCGR1, CG11 */
498 kCLOCK_Lpuart4 = (1U << 8U) | CCM_CCGR1_CG12_SHIFT, /*!< CCGR1, CG12 */
499 kCLOCK_Gpio1 = (1U << 8U) | CCM_CCGR1_CG13_SHIFT, /*!< CCGR1, CG13 */
500 kCLOCK_Csu = (1U << 8U) | CCM_CCGR1_CG14_SHIFT, /*!< CCGR1, CG14 */
501 kCLOCK_Gpio5 = (1U << 8U) | CCM_CCGR1_CG15_SHIFT, /*!< CCGR1, CG15 */
502
503 /* CCM CCGR2 */
504 kCLOCK_OcramExsc = (2U << 8U) | CCM_CCGR2_CG0_SHIFT, /*!< CCGR2, CG0 */
505 kCLOCK_IomuxcSnvs = (2U << 8U) | CCM_CCGR2_CG2_SHIFT, /*!< CCGR2, CG2 */
506 kCLOCK_Lpi2c1 = (2U << 8U) | CCM_CCGR2_CG3_SHIFT, /*!< CCGR2, CG3 */
507 kCLOCK_Lpi2c2 = (2U << 8U) | CCM_CCGR2_CG4_SHIFT, /*!< CCGR2, CG4 */
508 kCLOCK_Lpi2c3 = (2U << 8U) | CCM_CCGR2_CG5_SHIFT, /*!< CCGR2, CG5 */
509 kCLOCK_Ocotp = (2U << 8U) | CCM_CCGR2_CG6_SHIFT, /*!< CCGR2, CG6 */
510 kCLOCK_Xbar1 = (2U << 8U) | CCM_CCGR2_CG11_SHIFT, /*!< CCGR2, CG11 */
511 kCLOCK_Xbar2 = (2U << 8U) | CCM_CCGR2_CG12_SHIFT, /*!< CCGR2, CG12 */
512 kCLOCK_Gpio3 = (2U << 8U) | CCM_CCGR2_CG13_SHIFT, /*!< CCGR2, CG13 */
513
514 /* CCM CCGR3 */
515 kCLOCK_Lpuart5 = (3U << 8U) | CCM_CCGR3_CG1_SHIFT, /*!< CCGR3, CG1 */
516 kCLOCK_Semc = (3U << 8U) | CCM_CCGR3_CG2_SHIFT, /*!< CCGR3, CG2 */
517 kCLOCK_Lpuart6 = (3U << 8U) | CCM_CCGR3_CG3_SHIFT, /*!< CCGR3, CG3 */
518 kCLOCK_Aoi = (3U << 8U) | CCM_CCGR3_CG4_SHIFT, /*!< CCGR3, CG4 */
519 kCLOCK_Ewm0 = (3U << 8U) | CCM_CCGR3_CG7_SHIFT, /*!< CCGR3, CG7 */
520 kCLOCK_Wdog1 = (3U << 8U) | CCM_CCGR3_CG8_SHIFT, /*!< CCGR3, CG8 */
521 kCLOCK_FlexRam = (3U << 8U) | CCM_CCGR3_CG9_SHIFT, /*!< CCGR3, CG9 */
522 kCLOCK_Acmp1 = (3U << 8U) | CCM_CCGR3_CG10_SHIFT, /*!< CCGR3, CG10 */
523 kCLOCK_Acmp2 = (3U << 8U) | CCM_CCGR3_CG11_SHIFT, /*!< CCGR3, CG11 */
524 kCLOCK_Acmp3 = (3U << 8U) | CCM_CCGR3_CG12_SHIFT, /*!< CCGR3, CG12 */
525 kCLOCK_Acmp4 = (3U << 8U) | CCM_CCGR3_CG13_SHIFT, /*!< CCGR3, CG13 */
526 kCLOCK_IomuxcSnvsGpr = (3U << 8U) | CCM_CCGR3_CG15_SHIFT, /*!< CCGR3, CG15 */
527
528 /* CCM CCGR4 */
529 kCLOCK_Sim_m7_clk_r = (4U << 8U) | CCM_CCGR4_CG0_SHIFT, /*!< CCGR4, CG0 */
530 kCLOCK_Iomuxc = (4U << 8U) | CCM_CCGR4_CG1_SHIFT, /*!< CCGR4, CG1 */
531 kCLOCK_IomuxcGpr = (4U << 8U) | CCM_CCGR4_CG2_SHIFT, /*!< CCGR4, CG2 */
532 kCLOCK_Bee = (4U << 8U) | CCM_CCGR4_CG3_SHIFT, /*!< CCGR4, CG3 */
533 kCLOCK_SimM7 = (4U << 8U) | CCM_CCGR4_CG4_SHIFT, /*!< CCGR4, CG4 */
534 kCLOCK_Tsc = (4U << 8U) | CCM_CCGR4_CG5_SHIFT, /*!< CCGR4, CG5, Reserved */
535 kCLOCK_SimM = (4U << 8U) | CCM_CCGR4_CG6_SHIFT, /*!< CCGR4, CG6 */
536 kCLOCK_SimEms = (4U << 8U) | CCM_CCGR4_CG7_SHIFT, /*!< CCGR4, CG7 */
537 kCLOCK_Pwm1 = (4U << 8U) | CCM_CCGR4_CG8_SHIFT, /*!< CCGR4, CG8 */
538 kCLOCK_Pwm2 = (4U << 8U) | CCM_CCGR4_CG9_SHIFT, /*!< CCGR4, CG9 */
539 kCLOCK_Enc1 = (4U << 8U) | CCM_CCGR4_CG12_SHIFT, /*!< CCGR4, CG12 */
540 kCLOCK_Enc2 = (4U << 8U) | CCM_CCGR4_CG13_SHIFT, /*!< CCGR4, CG13 */
541
542 /* CCM CCGR5 */
543 kCLOCK_Rom = (5U << 8U) | CCM_CCGR5_CG0_SHIFT, /*!< CCGR5, CG0 */
544 kCLOCK_Flexio1 = (5U << 8U) | CCM_CCGR5_CG1_SHIFT, /*!< CCGR5, CG1 */
545 kCLOCK_Wdog3 = (5U << 8U) | CCM_CCGR5_CG2_SHIFT, /*!< CCGR5, CG2 */
546 kCLOCK_Dma = (5U << 8U) | CCM_CCGR5_CG3_SHIFT, /*!< CCGR5, CG3 */
547 kCLOCK_Kpp = (5U << 8U) | CCM_CCGR5_CG4_SHIFT, /*!< CCGR5, CG4 */
548 kCLOCK_Wdog2 = (5U << 8U) | CCM_CCGR5_CG5_SHIFT, /*!< CCGR5, CG5 */
549 kCLOCK_Aips_tz4 = (5U << 8U) | CCM_CCGR5_CG6_SHIFT, /*!< CCGR5, CG6 */
550 kCLOCK_Spdif = (5U << 8U) | CCM_CCGR5_CG7_SHIFT, /*!< CCGR5, CG7 */
551 kCLOCK_Sai1 = (5U << 8U) | CCM_CCGR5_CG9_SHIFT, /*!< CCGR5, CG9 */
552 kCLOCK_Sai2 = (5U << 8U) | CCM_CCGR5_CG10_SHIFT, /*!< CCGR5, CG10 */
553 kCLOCK_Sai3 = (5U << 8U) | CCM_CCGR5_CG11_SHIFT, /*!< CCGR5, CG11 */
554 kCLOCK_Lpuart1 = (5U << 8U) | CCM_CCGR5_CG12_SHIFT, /*!< CCGR5, CG12 */
555 kCLOCK_Lpuart7 = (5U << 8U) | CCM_CCGR5_CG13_SHIFT, /*!< CCGR5, CG13 */
556 kCLOCK_SnvsHp = (5U << 8U) | CCM_CCGR5_CG14_SHIFT, /*!< CCGR5, CG14 */
557 kCLOCK_SnvsLp = (5U << 8U) | CCM_CCGR5_CG15_SHIFT, /*!< CCGR5, CG15 */
558
559 /* CCM CCGR6 */
560 kCLOCK_UsbOh3 = (6U << 8U) | CCM_CCGR6_CG0_SHIFT, /*!< CCGR6, CG0 */
561 kCLOCK_Usdhc1 = (6U << 8U) | CCM_CCGR6_CG1_SHIFT, /*!< CCGR6, CG1 */
562 kCLOCK_Usdhc2 = (6U << 8U) | CCM_CCGR6_CG2_SHIFT, /*!< CCGR6, CG2 */
563 kCLOCK_Dcdc = (6U << 8U) | CCM_CCGR6_CG3_SHIFT, /*!< CCGR6, CG3 */
564 kCLOCK_Ipmux4 = (6U << 8U) | CCM_CCGR6_CG4_SHIFT, /*!< CCGR6, CG4 */
565 kCLOCK_FlexSpi = (6U << 8U) | CCM_CCGR6_CG5_SHIFT, /*!< CCGR6, CG5 */
566 kCLOCK_Trng = (6U << 8U) | CCM_CCGR6_CG6_SHIFT, /*!< CCGR6, CG6 */
567 kCLOCK_Lpuart8 = (6U << 8U) | CCM_CCGR6_CG7_SHIFT, /*!< CCGR6, CG7 */
568 kCLOCK_Timer4 = (6U << 8U) | CCM_CCGR6_CG8_SHIFT, /*!< CCGR6, CG8 */
569 kCLOCK_Aips_tz3 = (6U << 8U) | CCM_CCGR6_CG9_SHIFT, /*!< CCGR6, CG9 */
570 kCLOCK_SimPer = (6U << 8U) | CCM_CCGR6_CG10_SHIFT, /*!< CCGR6, CG10 */
571 kCLOCK_Anadig = (6U << 8U) | CCM_CCGR6_CG11_SHIFT, /*!< CCGR6, CG11 */
572 kCLOCK_Lpi2c4 = (6U << 8U) | CCM_CCGR6_CG12_SHIFT, /*!< CCGR6, CG12 */
573 kCLOCK_Timer1 = (6U << 8U) | CCM_CCGR6_CG13_SHIFT, /*!< CCGR6, CG13 */
574 kCLOCK_Timer2 = (6U << 8U) | CCM_CCGR6_CG14_SHIFT, /*!< CCGR6, CG14 */
575
576 } clock_ip_name_t;
577
578 /*! @brief OSC 24M sorce select */
579 typedef enum _clock_osc
580 {
581 kCLOCK_RcOsc = 0U, /*!< On chip OSC. */
582 kCLOCK_XtalOsc = 1U, /*!< 24M Xtal OSC */
583 } clock_osc_t;
584
585 /*! @brief Clock gate value */
586 typedef enum _clock_gate_value
587 {
588 kCLOCK_ClockNotNeeded = 0U, /*!< Clock is off during all modes. */
589 kCLOCK_ClockNeededRun = 1U, /*!< Clock is on in run mode, but off in WAIT and STOP modes */
590 kCLOCK_ClockNeededRunWait = 3U, /*!< Clock is on during all modes, except STOP mode */
591 } clock_gate_value_t;
592
593 /*! @brief System clock mode */
594 typedef enum _clock_mode_t
595 {
596 kCLOCK_ModeRun = 0U, /*!< Remain in run mode. */
597 kCLOCK_ModeWait = 1U, /*!< Transfer to wait mode. */
598 kCLOCK_ModeStop = 2U, /*!< Transfer to stop mode. */
599 } clock_mode_t;
600
601 /*!
602 * @brief MUX control names for clock mux setting.
603 *
604 * These constants define the mux control names for clock mux setting.\n
605 * - 0:7: REG offset to CCM_BASE in bytes.
606 * - 8:15: Root clock setting bit field shift.
607 * - 16:31: Root clock setting bit field width.
608 */
609 typedef enum _clock_mux
610 {
611 kCLOCK_Pll3SwMux = CCM_TUPLE(CCSR_OFFSET,
612 CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT,
613 CCM_CCSR_PLL3_SW_CLK_SEL_MASK,
614 CCM_NO_BUSY_WAIT), /*!< pll3_sw_clk mux name */
615
616 kCLOCK_PeriphMux = CCM_TUPLE(CBCDR_OFFSET,
617 CCM_CBCDR_PERIPH_CLK_SEL_SHIFT,
618 CCM_CBCDR_PERIPH_CLK_SEL_MASK,
619 CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT), /*!< periph mux name */
620 kCLOCK_SemcAltMux = CCM_TUPLE(CBCDR_OFFSET,
621 CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT,
622 CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK,
623 CCM_NO_BUSY_WAIT), /*!< semc mux name */
624 kCLOCK_SemcMux = CCM_TUPLE(CBCDR_OFFSET,
625 CCM_CBCDR_SEMC_CLK_SEL_SHIFT,
626 CCM_CBCDR_SEMC_CLK_SEL_MASK,
627 CCM_NO_BUSY_WAIT), /*!< semc mux name */
628
629 kCLOCK_PrePeriphMux = CCM_TUPLE(CBCMR_OFFSET,
630 CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT,
631 CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK,
632 CCM_NO_BUSY_WAIT), /*!< pre-periph mux name */
633 kCLOCK_TraceMux = CCM_TUPLE(CBCMR_OFFSET,
634 CCM_CBCMR_TRACE_CLK_SEL_SHIFT,
635 CCM_CBCMR_TRACE_CLK_SEL_MASK,
636 CCM_NO_BUSY_WAIT), /*!< trace mux name */
637 kCLOCK_PeriphClk2Mux = CCM_TUPLE(CBCMR_OFFSET,
638 CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT,
639 CCM_CBCMR_PERIPH_CLK2_SEL_MASK,
640 CCM_NO_BUSY_WAIT), /*!< periph clock2 mux name */
641 kCLOCK_LpspiMux = CCM_TUPLE(CBCMR_OFFSET,
642 CCM_CBCMR_LPSPI_CLK_SEL_SHIFT,
643 CCM_CBCMR_LPSPI_CLK_SEL_MASK,
644 CCM_NO_BUSY_WAIT), /*!< lpspi mux name */
645
646 kCLOCK_FlexspiMux = CCM_TUPLE(CSCMR1_OFFSET,
647 CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT,
648 CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK,
649 CCM_NO_BUSY_WAIT), /*!< flexspi mux name */
650 kCLOCK_Usdhc2Mux = CCM_TUPLE(CSCMR1_OFFSET,
651 CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT,
652 CCM_CSCMR1_USDHC2_CLK_SEL_MASK,
653 CCM_NO_BUSY_WAIT), /*!< usdhc2 mux name */
654 kCLOCK_Usdhc1Mux = CCM_TUPLE(CSCMR1_OFFSET,
655 CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT,
656 CCM_CSCMR1_USDHC1_CLK_SEL_MASK,
657 CCM_NO_BUSY_WAIT), /*!< usdhc1 mux name */
658 kCLOCK_Sai3Mux = CCM_TUPLE(CSCMR1_OFFSET,
659 CCM_CSCMR1_SAI3_CLK_SEL_SHIFT,
660 CCM_CSCMR1_SAI3_CLK_SEL_MASK,
661 CCM_NO_BUSY_WAIT), /*!< sai3 mux name */
662 kCLOCK_Sai2Mux = CCM_TUPLE(CSCMR1_OFFSET,
663 CCM_CSCMR1_SAI2_CLK_SEL_SHIFT,
664 CCM_CSCMR1_SAI2_CLK_SEL_MASK,
665 CCM_NO_BUSY_WAIT), /*!< sai2 mux name */
666 kCLOCK_Sai1Mux = CCM_TUPLE(CSCMR1_OFFSET,
667 CCM_CSCMR1_SAI1_CLK_SEL_SHIFT,
668 CCM_CSCMR1_SAI1_CLK_SEL_MASK,
669 CCM_NO_BUSY_WAIT), /*!< sai1 mux name */
670 kCLOCK_PerclkMux = CCM_TUPLE(CSCMR1_OFFSET,
671 CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT,
672 CCM_CSCMR1_PERCLK_CLK_SEL_MASK,
673 CCM_NO_BUSY_WAIT), /*!< perclk mux name */
674
675 kCLOCK_Flexio1Mux = CCM_TUPLE(CSCMR2_OFFSET,
676 CCM_CSCMR2_FLEXIO1_CLK_SEL_SHIFT,
677 CCM_CSCMR2_FLEXIO1_CLK_SEL_MASK,
678 CCM_NO_BUSY_WAIT), /*!< flexio1 mux name */
679 kCLOCK_CanMux = CCM_TUPLE(CSCMR2_OFFSET,
680 CCM_CSCMR2_CAN_CLK_SEL_SHIFT,
681 CCM_CSCMR2_CAN_CLK_SEL_MASK,
682 CCM_NO_BUSY_WAIT), /*!< can mux name */
683
684 kCLOCK_UartMux = CCM_TUPLE(CSCDR1_OFFSET,
685 CCM_CSCDR1_UART_CLK_SEL_SHIFT,
686 CCM_CSCDR1_UART_CLK_SEL_MASK,
687 CCM_NO_BUSY_WAIT), /*!< uart mux name */
688
689 kCLOCK_SpdifMux = CCM_TUPLE(CDCDR_OFFSET,
690 CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT,
691 CCM_CDCDR_SPDIF0_CLK_SEL_MASK,
692 CCM_NO_BUSY_WAIT), /*!< spdif mux name */
693
694 kCLOCK_Lpi2cMux = CCM_TUPLE(CSCDR2_OFFSET,
695 CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT,
696 CCM_CSCDR2_LPI2C_CLK_SEL_MASK,
697 CCM_NO_BUSY_WAIT), /*!< lpi2c mux name */
698 } clock_mux_t;
699
700 /*!
701 * @brief DIV control names for clock div setting.
702 *
703 * These constants define div control names for clock div setting.\n
704 * - 0:7: REG offset to CCM_BASE in bytes.
705 * - 8:15: Root clock setting bit field shift.
706 * - 16:31: Root clock setting bit field width.
707 */
708 typedef enum _clock_div
709 {
710 kCLOCK_ArmDiv = CCM_TUPLE(CACRR_OFFSET,
711 CCM_CACRR_ARM_PODF_SHIFT,
712 CCM_CACRR_ARM_PODF_MASK,
713 CCM_CDHIPR_ARM_PODF_BUSY_SHIFT), /*!< core div name */
714
715 kCLOCK_PeriphClk2Div = CCM_TUPLE(CBCDR_OFFSET,
716 CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT,
717 CCM_CBCDR_PERIPH_CLK2_PODF_MASK,
718 CCM_NO_BUSY_WAIT), /*!< periph clock2 div name */
719 kCLOCK_SemcDiv = CCM_TUPLE(CBCDR_OFFSET,
720 CCM_CBCDR_SEMC_PODF_SHIFT,
721 CCM_CBCDR_SEMC_PODF_MASK,
722 CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT), /*!< semc div name */
723 kCLOCK_AhbDiv = CCM_TUPLE(CBCDR_OFFSET,
724 CCM_CBCDR_AHB_PODF_SHIFT,
725 CCM_CBCDR_AHB_PODF_MASK,
726 CCM_CDHIPR_AHB_PODF_BUSY_SHIFT), /*!< ahb div name */
727 kCLOCK_IpgDiv = CCM_TUPLE(
728 CBCDR_OFFSET, CCM_CBCDR_IPG_PODF_SHIFT, CCM_CBCDR_IPG_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< ipg div name */
729
730 kCLOCK_LpspiDiv = CCM_TUPLE(
731 CBCMR_OFFSET, CCM_CBCMR_LPSPI_PODF_SHIFT, CCM_CBCMR_LPSPI_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< lpspi div name */
732
733 kCLOCK_FlexspiDiv = CCM_TUPLE(CSCMR1_OFFSET,
734 CCM_CSCMR1_FLEXSPI_PODF_SHIFT,
735 CCM_CSCMR1_FLEXSPI_PODF_MASK,
736 CCM_NO_BUSY_WAIT), /*!< flexspi div name */
737 kCLOCK_PerclkDiv = CCM_TUPLE(CSCMR1_OFFSET,
738 CCM_CSCMR1_PERCLK_PODF_SHIFT,
739 CCM_CSCMR1_PERCLK_PODF_MASK,
740 CCM_NO_BUSY_WAIT), /*!< perclk div name */
741
742 kCLOCK_CanDiv = CCM_TUPLE(CSCMR2_OFFSET,
743 CCM_CSCMR2_CAN_CLK_PODF_SHIFT,
744 CCM_CSCMR2_CAN_CLK_PODF_MASK,
745 CCM_NO_BUSY_WAIT), /*!< can div name */
746
747 kCLOCK_TraceDiv = CCM_TUPLE(CSCDR1_OFFSET,
748 CCM_CSCDR1_TRACE_PODF_SHIFT,
749 CCM_CSCDR1_TRACE_PODF_MASK,
750 CCM_NO_BUSY_WAIT), /*!< trace div name */
751 kCLOCK_Usdhc2Div = CCM_TUPLE(CSCDR1_OFFSET,
752 CCM_CSCDR1_USDHC2_PODF_SHIFT,
753 CCM_CSCDR1_USDHC2_PODF_MASK,
754 CCM_NO_BUSY_WAIT), /*!< usdhc2 div name */
755 kCLOCK_Usdhc1Div = CCM_TUPLE(CSCDR1_OFFSET,
756 CCM_CSCDR1_USDHC1_PODF_SHIFT,
757 CCM_CSCDR1_USDHC1_PODF_MASK,
758 CCM_NO_BUSY_WAIT), /*!< usdhc1 div name */
759 kCLOCK_UartDiv = CCM_TUPLE(CSCDR1_OFFSET,
760 CCM_CSCDR1_UART_CLK_PODF_SHIFT,
761 CCM_CSCDR1_UART_CLK_PODF_MASK,
762 CCM_NO_BUSY_WAIT), /*!< uart div name */
763
764 kCLOCK_Flexio1Div = CCM_TUPLE(CS1CDR_OFFSET,
765 CCM_CS1CDR_FLEXIO1_CLK_PODF_SHIFT,
766 CCM_CS1CDR_FLEXIO1_CLK_PODF_MASK,
767 CCM_NO_BUSY_WAIT), /*!< flexio1 pre div name */
768 kCLOCK_Sai3PreDiv = CCM_TUPLE(CS1CDR_OFFSET,
769 CCM_CS1CDR_SAI3_CLK_PRED_SHIFT,
770 CCM_CS1CDR_SAI3_CLK_PRED_MASK,
771 CCM_NO_BUSY_WAIT), /*!< sai3 pre div name */
772 kCLOCK_Sai3Div = CCM_TUPLE(CS1CDR_OFFSET,
773 CCM_CS1CDR_SAI3_CLK_PODF_SHIFT,
774 CCM_CS1CDR_SAI3_CLK_PODF_MASK,
775 CCM_NO_BUSY_WAIT), /*!< sai3 div name */
776 kCLOCK_Flexio1PreDiv = CCM_TUPLE(CS1CDR_OFFSET,
777 CCM_CS1CDR_FLEXIO1_CLK_PRED_SHIFT,
778 CCM_CS1CDR_FLEXIO1_CLK_PRED_MASK,
779 CCM_NO_BUSY_WAIT), /*!< flexio1 pre div name */
780 kCLOCK_Sai1PreDiv = CCM_TUPLE(CS1CDR_OFFSET,
781 CCM_CS1CDR_SAI1_CLK_PRED_SHIFT,
782 CCM_CS1CDR_SAI1_CLK_PRED_MASK,
783 CCM_NO_BUSY_WAIT), /*!< sai1 pre div name */
784 kCLOCK_Sai1Div = CCM_TUPLE(CS1CDR_OFFSET,
785 CCM_CS1CDR_SAI1_CLK_PODF_SHIFT,
786 CCM_CS1CDR_SAI1_CLK_PODF_MASK,
787 CCM_NO_BUSY_WAIT), /*!< sai1 div name */
788
789 kCLOCK_Sai2PreDiv = CCM_TUPLE(CS2CDR_OFFSET,
790 CCM_CS2CDR_SAI2_CLK_PRED_SHIFT,
791 CCM_CS2CDR_SAI2_CLK_PRED_MASK,
792 CCM_NO_BUSY_WAIT), /*!< sai2 pre div name */
793 kCLOCK_Sai2Div = CCM_TUPLE(CS2CDR_OFFSET,
794 CCM_CS2CDR_SAI2_CLK_PODF_SHIFT,
795 CCM_CS2CDR_SAI2_CLK_PODF_MASK,
796 CCM_NO_BUSY_WAIT), /*!< sai2 pre div name */
797
798 kCLOCK_Spdif0PreDiv = CCM_TUPLE(CDCDR_OFFSET,
799 CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT,
800 CCM_CDCDR_SPDIF0_CLK_PRED_MASK,
801 CCM_NO_BUSY_WAIT), /*!< spdif pre div name */
802 kCLOCK_Spdif0Div = CCM_TUPLE(CDCDR_OFFSET,
803 CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT,
804 CCM_CDCDR_SPDIF0_CLK_PODF_MASK,
805 CCM_NO_BUSY_WAIT), /*!< spdif div name */
806
807 kCLOCK_Lpi2cDiv = CCM_TUPLE(CSCDR2_OFFSET,
808 CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT,
809 CCM_CSCDR2_LPI2C_CLK_PODF_MASK,
810 CCM_NO_BUSY_WAIT), /*!< lpi2c div name */
811 kCLOCK_NonePreDiv = CLOCK_ROOT_NONE_PRE_DIV, /*!< None Pre div. */
812 } clock_div_t;
813
814 /*!
815 * @brief Clock divider value.
816 */
817 typedef enum _clock_div_value
818 {
819 kCLOCK_ArmDivBy1 = 0, /*!< ARM clock divider set to divided by 1. */
820 kCLOCK_ArmDivBy2 = 1, /*!< ARM clock divider set to divided by 2. */
821 kCLOCK_ArmDivBy3 = 2, /*!< ARM clock divider set to divided by 3. */
822 kCLOCK_ArmDivBy4 = 3, /*!< ARM clock divider set to divided by 4. */
823 kCLOCK_ArmDivBy5 = 4, /*!< ARM clock divider set to divided by 5. */
824 kCLOCK_ArmDivBy6 = 5, /*!< ARM clock divider set to divided by 6. */
825 kCLOCK_ArmDivBy7 = 6, /*!< ARM clock divider set to divided by 7. */
826 kCLOCK_ArmDivBy8 = 7, /*!< ARM clock divider set to divided by 8. */
827
828 kCLOCK_PeriphClk2DivBy1 = 0, /*!< PeriphClk2 divider set to divided by 1. */
829 kCLOCK_PeriphClk2DivBy2 = 1, /*!< PeriphClk2 divider set to divided by 2. */
830 kCLOCK_PeriphClk2DivBy3 = 2, /*!< PeriphClk2 divider set to divided by 3. */
831 kCLOCK_PeriphClk2DivBy4 = 3, /*!< PeriphClk2 divider set to divided by 4. */
832 kCLOCK_PeriphClk2DivBy5 = 4, /*!< PeriphClk2 divider set to divided by 5. */
833 kCLOCK_PeriphClk2DivBy6 = 5, /*!< PeriphClk2 divider set to divided by 6. */
834 kCLOCK_PeriphClk2DivBy7 = 6, /*!< PeriphClk2 divider set to divided by 7. */
835 kCLOCK_PeriphClk2DivBy8 = 7, /*!< PeriphClk2 divider set to divided by 8. */
836
837 kCLOCK_SemcDivBy1 = 0, /*!< SEMC divider set to divided by 1. */
838 kCLOCK_SemcDivBy2 = 1, /*!< SEMC divider set to divided by 2. */
839 kCLOCK_SemcDivBy3 = 2, /*!< SEMC divider set to divided by 3. */
840 kCLOCK_SemcDivBy4 = 3, /*!< SEMC divider set to divided by 4. */
841 kCLOCK_SemcDivBy5 = 4, /*!< SEMC divider set to divided by 5. */
842 kCLOCK_SemcDivBy6 = 5, /*!< SEMC divider set to divided by 6. */
843 kCLOCK_SemcDivBy7 = 6, /*!< SEMC divider set to divided by 7. */
844 kCLOCK_SemcDivBy8 = 7, /*!< SEMC divider set to divided by 8. */
845
846 kCLOCK_AhbDivBy1 = 0, /*!< AHB divider set to divided by 1. */
847 kCLOCK_AhbDivBy2 = 1, /*!< AHB divider set to divided by 2. */
848 kCLOCK_AhbDivBy3 = 2, /*!< AHB divider set to divided by 3. */
849 kCLOCK_AhbDivBy4 = 3, /*!< AHB divider set to divided by 4. */
850 kCLOCK_AhbDivBy5 = 4, /*!< AHB divider set to divided by 5. */
851 kCLOCK_AhbDivBy6 = 5, /*!< AHB divider set to divided by 6. */
852 kCLOCK_AhbDivBy7 = 6, /*!< AHB divider set to divided by 7. */
853 kCLOCK_AhbDivBy8 = 7, /*!< AHB divider set to divided by 8. */
854
855 kCLOCK_IpgDivBy1 = 0, /*!< Ipg divider set to divided by 1. */
856 kCLOCK_IpgDivBy2 = 1, /*!< Ipg divider set to divided by 2. */
857 kCLOCK_IpgDivBy3 = 2, /*!< Ipg divider set to divided by 3. */
858 kCLOCK_IpgDivBy4 = 3, /*!< Ipg divider set to divided by 4. */
859
860 kCLOCK_LpspiDivBy1 = 0, /*!< LPSPI divider set to divided by 1. */
861 kCLOCK_LpspiDivBy2 = 1, /*!< LPSPI divider set to divided by 2. */
862 kCLOCK_LpspiDivBy3 = 2, /*!< LPSPI divider set to divided by 3. */
863 kCLOCK_LpspiDivBy4 = 3, /*!< LPSPI divider set to divided by 4. */
864 kCLOCK_LpspiDivBy5 = 4, /*!< LPSPI divider set to divided by 5. */
865 kCLOCK_LpspiDivBy6 = 5, /*!< LPSPI divider set to divided by 6. */
866 kCLOCK_LpspiDivBy7 = 6, /*!< LPSPI divider set to divided by 7. */
867 kCLOCK_LpspiDivBy8 = 7, /*!< LPSPI divider set to divided by 8. */
868
869 kCLOCK_FlexspiDivBy1 = 0, /*!< FLEXSPI divider set to divided by 1. */
870 kCLOCK_FlexspiDivBy2 = 1, /*!< FLEXSPI divider set to divided by 2. */
871 kCLOCK_FlexspiDivBy3 = 2, /*!< FLEXSPI divider set to divided by 3. */
872 kCLOCK_FlexspiDivBy4 = 3, /*!< FLEXSPI divider set to divided by 4. */
873 kCLOCK_FlexspiDivBy5 = 4, /*!< FLEXSPI divider set to divided by 5. */
874 kCLOCK_FlexspiDivBy6 = 5, /*!< FLEXSPI divider set to divided by 6. */
875 kCLOCK_FlexspiDivBy7 = 6, /*!< FLEXSPI divider set to divided by 7. */
876 kCLOCK_FlexspiDivBy8 = 7, /*!< FLEXSPI divider set to divided by 8. */
877
878 kCLOCK_TraceDivBy1 = 0, /*!< TRACE divider set to divided by 1. */
879 kCLOCK_TraceDivBy2 = 1, /*!< TRACE divider set to divided by 2. */
880 kCLOCK_TraceDivBy3 = 2, /*!< TRACE divider set to divided by 3. */
881 kCLOCK_TraceDivBy4 = 3, /*!< TRACE divider set to divided by 4. */
882
883 kCLOCK_Usdhc2DivBy1 = 0, /*!< USDHC2 divider set to divided by 1. */
884 kCLOCK_Usdhc2DivBy2 = 1, /*!< USDHC2 divider set to divided by 2. */
885 kCLOCK_Usdhc2DivBy3 = 2, /*!< USDHC2 divider set to divided by 3. */
886 kCLOCK_Usdhc2DivBy4 = 3, /*!< USDHC2 divider set to divided by 4. */
887 kCLOCK_Usdhc2DivBy5 = 4, /*!< USDHC2 divider set to divided by 5. */
888 kCLOCK_Usdhc2DivBy6 = 5, /*!< USDHC2 divider set to divided by 6. */
889 kCLOCK_Usdhc2DivBy7 = 6, /*!< USDHC2 divider set to divided by 7. */
890 kCLOCK_Usdhc2DivBy8 = 7, /*!< USDHC2 divider set to divided by 8. */
891
892 kCLOCK_Usdhc1DivBy1 = 0, /*!< USDHC1 divider set to divided by 1. */
893 kCLOCK_Usdhc1DivBy2 = 1, /*!< USDHC1 divider set to divided by 2. */
894 kCLOCK_Usdhc1DivBy3 = 2, /*!< USDHC1 divider set to divided by 3. */
895 kCLOCK_Usdhc1DivBy4 = 3, /*!< USDHC1 divider set to divided by 4. */
896 kCLOCK_Usdhc1DivBy5 = 4, /*!< USDHC1 divider set to divided by 5. */
897 kCLOCK_Usdhc1DivBy6 = 5, /*!< USDHC1 divider set to divided by 6. */
898 kCLOCK_Usdhc1DivBy7 = 6, /*!< USDHC1 divider set to divided by 7. */
899 kCLOCK_Usdhc1DivBy8 = 7, /*!< USDHC1 divider set to divided by 8. */
900
901 kCLOCK_Flexio1DivBy1 = 0, /*!< Flexio1 divider set to divided by 1. */
902 kCLOCK_Flexio1DivBy2 = 1, /*!< Flexio1 divider set to divided by 2. */
903 kCLOCK_Flexio1DivBy3 = 2, /*!< Flexio1 divider set to divided by 3. */
904 kCLOCK_Flexio1DivBy4 = 3, /*!< Flexio1 divider set to divided by 4. */
905 kCLOCK_Flexio1DivBy5 = 4, /*!< Flexio1 divider set to divided by 5. */
906 kCLOCK_Flexio1DivBy6 = 5, /*!< Flexio1 divider set to divided by 6. */
907 kCLOCK_Flexio1DivBy7 = 6, /*!< Flexio1 divider set to divided by 7. */
908 kCLOCK_Flexio1DivBy8 = 7, /*!< Flexio1 divider set to divided by 8. */
909
910 kCLOCK_Sai3PreDivBy1 = 0, /*!< SAI3ClkPred divider set to divided by 1. */
911 kCLOCK_Sai3PreDivBy2 = 1, /*!< SAI3ClkPred divider set to divided by 2. */
912 kCLOCK_Sai3PreDivBy3 = 2, /*!< SAI3ClkPred divider set to divided by 3. */
913 kCLOCK_Sai3PreDivBy4 = 3, /*!< SAI3ClkPred divider set to divided by 4. */
914 kCLOCK_Sai3PreDivBy5 = 4, /*!< SAI3ClkPred divider set to divided by 5. */
915 kCLOCK_Sai3PreDivBy6 = 5, /*!< SAI3ClkPred divider set to divided by 6. */
916 kCLOCK_Sai3PreDivBy7 = 6, /*!< SAI3ClkPred divider set to divided by 7. */
917 kCLOCK_Sai3PreDivBy8 = 7, /*!< SAI3ClkPred divider set to divided by 8. */
918
919 kCLOCK_Flexio1PreDivBy1 = 0, /*!< Flexio1 pred divider set to divided by 1. */
920 kCLOCK_Flexio1PreDivBy2 = 1, /*!< Flexio1 pred divider set to divided by 2. */
921 kCLOCK_Flexio1PreDivBy3 = 2, /*!< Flexio1 pred divider set to divided by 3. */
922 kCLOCK_Flexio1PreDivBy4 = 3, /*!< Flexio1 pred divider set to divided by 4. */
923 kCLOCK_Flexio1PreDivBy5 = 4, /*!< Flexio1 pred divider set to divided by 5. */
924 kCLOCK_Flexio1PreDivBy6 = 5, /*!< Flexio1 pred divider set to divided by 6. */
925 kCLOCK_Flexio1PreDivBy7 = 6, /*!< Flexio1 pred divider set to divided by 7. */
926 kCLOCK_Flexio1PreDivBy8 = 7, /*!< Flexio1 pred divider set to divided by 8. */
927
928 kCLOCK_Sai1PreDivBy1 = 0, /*!< SAI1 pred divider set to divided by 1. */
929 kCLOCK_Sai1PreDivBy2 = 1, /*!< SAI1 pred divider set to divided by 2. */
930 kCLOCK_Sai1PreDivBy3 = 2, /*!< SAI1 pred divider set to divided by 3. */
931 kCLOCK_Sai1PreDivBy4 = 3, /*!< SAI1 pred divider set to divided by 4. */
932 kCLOCK_Sai1PreDivBy5 = 4, /*!< SAI1 pred divider set to divided by 5. */
933 kCLOCK_Sai1PreDivBy6 = 5, /*!< SAI1 pred divider set to divided by 6. */
934 kCLOCK_Sai1PreDivBy7 = 6, /*!< SAI1 pred divider set to divided by 7. */
935 kCLOCK_Sai1PreDivBy8 = 7, /*!< SAI1 pred divider set to divided by 8. */
936
937 kCLOCK_Sai2PreDivBy1 = 0, /*!< SAI2ClkPred divider set to divided by 1. */
938 kCLOCK_Sai2PreDivBy2 = 1, /*!< SAI2ClkPred divider set to divided by 2. */
939 kCLOCK_Sai2PreDivBy3 = 2, /*!< SAI2ClkPred divider set to divided by 3. */
940 kCLOCK_Sai2PreDivBy4 = 3, /*!< SAI2ClkPred divider set to divided by 4. */
941 kCLOCK_Sai2PreDivBy5 = 4, /*!< SAI2ClkPred divider set to divided by 5. */
942 kCLOCK_Sai2PreDivBy6 = 5, /*!< SAI2ClkPred divider set to divided by 6. */
943 kCLOCK_Sai2PreDivBy7 = 6, /*!< SAI2ClkPred divider set to divided by 7. */
944 kCLOCK_Sai2PreDivBy8 = 7, /*!< SAI2ClkPred divider set to divided by 8. */
945
946 kCLOCK_Spdif0PreDivBy1 = 0, /*!< SPDIF0ClkPred divider set to divided by 1. */
947 kCLOCK_Spdif0PreDivBy2 = 1, /*!< SPDIF0ClkPred divider set to divided by 2. */
948 kCLOCK_Spdif0PreDivBy3 = 2, /*!< SPDIF0ClkPred divider set to divided by 3. */
949 kCLOCK_Spdif0PreDivBy4 = 3, /*!< SPDIF0ClkPred divider set to divided by 4. */
950 kCLOCK_Spdif0PreDivBy5 = 4, /*!< SPDIF0ClkPred divider set to divided by 5. */
951 kCLOCK_Spdif0PreDivBy6 = 5, /*!< SPDIF0ClkPred divider set to divided by 6. */
952 kCLOCK_Spdif0PreDivBy7 = 6, /*!< SPDIF0ClkPred divider set to divided by 7. */
953 kCLOCK_Spdif0PreDivBy8 = 7, /*!< SPDIF0ClkPred divider set to divided by 8. */
954
955 kCLOCK_Spdif0DivBy1 = 0, /*!< SPDIF0ClkPodf divider set to divided by 1. */
956 kCLOCK_Spdif0DivBy2 = 1, /*!< SPDIF0ClkPodf divider set to divided by 2. */
957 kCLOCK_Spdif0DivBy3 = 2, /*!< SPDIF0ClkPodf divider set to divided by 3. */
958 kCLOCK_Spdif0DivBy4 = 3, /*!< SPDIF0ClkPodf divider set to divided by 4. */
959 kCLOCK_Spdif0DivBy5 = 4, /*!< SPDIF0ClkPodf divider set to divided by 5. */
960 kCLOCK_Spdif0DivBy6 = 5, /*!< SPDIF0ClkPodf divider set to divided by 6. */
961 kCLOCK_Spdif0DivBy7 = 6, /*!< SPDIF0ClkPodf divider set to divided by 7. */
962 kCLOCK_Spdif0DivBy8 = 7, /*!< SPDIF0ClkPodf divider set to divided by 8. */
963
964 /* Only kCLOCK_PerclkDiv, kCLOCK_CanDiv,kCLOCK_UartDiv, kCLOCK_Sai3Div, kCLOCK_Sai1Div,
965 * kCLOCK_Sai2Div, kCLOCK_Lpi2cDiv can use these.*/
966 kCLOCK_MiscDivBy1 = 0, /*!< Misc divider like LPI2C set to divided by 1. */
967 kCLOCK_MiscDivBy2 = 1, /*!< Misc divider like LPI2C set to divided by 2. */
968 kCLOCK_MiscDivBy3 = 2, /*!< Misc divider like LPI2C set to divided by 3. */
969 kCLOCK_MiscDivBy4 = 3, /*!< Misc divider like LPI2C set to divided by 4. */
970 kCLOCK_MiscDivBy5 = 4, /*!< Misc divider like LPI2C set to divided by 5. */
971 kCLOCK_MiscDivBy6 = 5, /*!< Misc divider like LPI2C set to divided by 6. */
972 kCLOCK_MiscDivBy7 = 6, /*!< Misc divider like LPI2C set to divided by 7. */
973 kCLOCK_MiscDivBy8 = 7, /*!< Misc divider like LPI2C set to divided by 8. */
974 kCLOCK_MiscDivBy9 = 8, /*!< Misc divider like LPI2C set to divided by 9. */
975 kCLOCK_MiscDivBy10 = 9, /*!< Misc divider like LPI2C set to divided by 10. */
976 kCLOCK_MiscDivBy11 = 10, /*!< Misc divider like LPI2C set to divided by 11. */
977 kCLOCK_MiscDivBy12 = 11, /*!< Misc divider like LPI2C set to divided by 12. */
978 kCLOCK_MiscDivBy13 = 12, /*!< Misc divider like LPI2C set to divided by 13. */
979 kCLOCK_MiscDivBy14 = 13, /*!< Misc divider like LPI2C set to divided by 14. */
980 kCLOCK_MiscDivBy15 = 14, /*!< Misc divider like LPI2C set to divided by 15. */
981 kCLOCK_MiscDivBy16 = 15, /*!< Misc divider like LPI2C set to divided by 16. */
982 kCLOCK_MiscDivBy17 = 16, /*!< Misc divider like LPI2C set to divided by 17. */
983 kCLOCK_MiscDivBy18 = 17, /*!< Misc divider like LPI2C set to divided by 18. */
984 kCLOCK_MiscDivBy19 = 18, /*!< Misc divider like LPI2C set to divided by 19. */
985 kCLOCK_MiscDivBy20 = 19, /*!< Misc divider like LPI2C set to divided by 20. */
986 kCLOCK_MiscDivBy21 = 20, /*!< Misc divider like LPI2C set to divided by 21. */
987 kCLOCK_MiscDivBy22 = 21, /*!< Misc divider like LPI2C set to divided by 22. */
988 kCLOCK_MiscDivBy23 = 22, /*!< Misc divider like LPI2C set to divided by 23. */
989 kCLOCK_MiscDivBy24 = 23, /*!< Misc divider like LPI2C set to divided by 24. */
990 kCLOCK_MiscDivBy25 = 24, /*!< Misc divider like LPI2C set to divided by 25. */
991 kCLOCK_MiscDivBy26 = 25, /*!< Misc divider like LPI2C set to divided by 26. */
992 kCLOCK_MiscDivBy27 = 26, /*!< Misc divider like LPI2C set to divided by 27. */
993 kCLOCK_MiscDivBy28 = 27, /*!< Misc divider like LPI2C set to divided by 28. */
994 kCLOCK_MiscDivBy29 = 28, /*!< Misc divider like LPI2C set to divided by 29. */
995 kCLOCK_MiscDivBy30 = 29, /*!< Misc divider like LPI2C set to divided by 30. */
996 kCLOCK_MiscDivBy31 = 30, /*!< Misc divider like LPI2C set to divided by 31. */
997 kCLOCK_MiscDivBy32 = 31, /*!< Misc divider like LPI2C set to divided by 32. */
998 kCLOCK_MiscDivBy33 = 32, /*!< Misc divider like LPI2C set to divided by 33. */
999 kCLOCK_MiscDivBy34 = 33, /*!< Misc divider like LPI2C set to divided by 34. */
1000 kCLOCK_MiscDivBy35 = 34, /*!< Misc divider like LPI2C set to divided by 35. */
1001 kCLOCK_MiscDivBy36 = 35, /*!< Misc divider like LPI2C set to divided by 36. */
1002 kCLOCK_MiscDivBy37 = 36, /*!< Misc divider like LPI2C set to divided by 37. */
1003 kCLOCK_MiscDivBy38 = 37, /*!< Misc divider like LPI2C set to divided by 38. */
1004 kCLOCK_MiscDivBy39 = 38, /*!< Misc divider like LPI2C set to divided by 39. */
1005 kCLOCK_MiscDivBy40 = 39, /*!< Misc divider like LPI2C set to divided by 40. */
1006 kCLOCK_MiscDivBy41 = 40, /*!< Misc divider like LPI2C set to divided by 41. */
1007 kCLOCK_MiscDivBy42 = 41, /*!< Misc divider like LPI2C set to divided by 42. */
1008 kCLOCK_MiscDivBy43 = 42, /*!< Misc divider like LPI2C set to divided by 43. */
1009 kCLOCK_MiscDivBy44 = 43, /*!< Misc divider like LPI2C set to divided by 44. */
1010 kCLOCK_MiscDivBy45 = 44, /*!< Misc divider like LPI2C set to divided by 45. */
1011 kCLOCK_MiscDivBy46 = 45, /*!< Misc divider like LPI2C set to divided by 46. */
1012 kCLOCK_MiscDivBy47 = 46, /*!< Misc divider like LPI2C set to divided by 47. */
1013 kCLOCK_MiscDivBy48 = 47, /*!< Misc divider like LPI2C set to divided by 48. */
1014 kCLOCK_MiscDivBy49 = 48, /*!< Misc divider like LPI2C set to divided by 49. */
1015 kCLOCK_MiscDivBy50 = 49, /*!< Misc divider like LPI2C set to divided by 50. */
1016 kCLOCK_MiscDivBy51 = 50, /*!< Misc divider like LPI2C set to divided by 51. */
1017 kCLOCK_MiscDivBy52 = 51, /*!< Misc divider like LPI2C set to divided by 52. */
1018 kCLOCK_MiscDivBy53 = 52, /*!< Misc divider like LPI2C set to divided by 53. */
1019 kCLOCK_MiscDivBy54 = 53, /*!< Misc divider like LPI2C set to divided by 54. */
1020 kCLOCK_MiscDivBy55 = 54, /*!< Misc divider like LPI2C set to divided by 55. */
1021 kCLOCK_MiscDivBy56 = 55, /*!< Misc divider like LPI2C set to divided by 56. */
1022 kCLOCK_MiscDivBy57 = 56, /*!< Misc divider like LPI2C set to divided by 57. */
1023 kCLOCK_MiscDivBy58 = 57, /*!< Misc divider like LPI2C set to divided by 58. */
1024 kCLOCK_MiscDivBy59 = 58, /*!< Misc divider like LPI2C set to divided by 59. */
1025 kCLOCK_MiscDivBy60 = 59, /*!< Misc divider like LPI2C set to divided by 60. */
1026 kCLOCK_MiscDivBy61 = 60, /*!< Misc divider like LPI2C set to divided by 61. */
1027 kCLOCK_MiscDivBy62 = 61, /*!< Misc divider like LPI2C set to divided by 62. */
1028 kCLOCK_MiscDivBy63 = 62, /*!< Misc divider like LPI2C set to divided by 63. */
1029 kCLOCK_MiscDivBy64 = 63, /*!< Misc divider like LPI2C set to divided by 64. */
1030 } clock_div_value_t;
1031
1032 /*! @brief USB clock source definition. */
1033 typedef enum _clock_usb_src
1034 {
1035 kCLOCK_Usb480M = 0, /*!< Use 480M. */
1036 kCLOCK_UsbSrcUnused = (int)0xFFFFFFFFU, /*!< Used when the function does not
1037 care the clock source. */
1038 } clock_usb_src_t;
1039
1040 /*! @brief Source of the USB HS PHY. */
1041 typedef enum _clock_usb_phy_src
1042 {
1043 kCLOCK_Usbphy480M = 0, /*!< Use 480M. */
1044 } clock_usb_phy_src_t;
1045
1046 /*!@brief PLL clock source, bypass cloco source also */
1047 enum _clock_pll_clk_src
1048 {
1049 kCLOCK_PllClkSrc24M = 0U, /*!< Pll clock source 24M */
1050 kCLOCK_PllSrcClkPN = 1U, /*!< Pll clock source CLK1_P and CLK1_N */
1051 };
1052
1053 /*! @brief PLL configuration for USB */
1054 typedef struct _clock_usb_pll_config
1055 {
1056 uint8_t loopDivider; /*!< PLL loop divider.
1057 0 - Fout=Fref*20;
1058 1 - Fout=Fref*22 */
1059 uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */
1060
1061 } clock_usb_pll_config_t;
1062
1063 /*! @brief PLL configuration for System */
1064 typedef struct _clock_sys_pll_config
1065 {
1066 uint8_t loopDivider; /*!< PLL loop divider. Intended to be 1 (528M).
1067 0 - Fout=Fref*20;
1068 1 - Fout=Fref*22 */
1069 uint32_t numerator; /*!< 30 bit numerator of fractional loop divider.*/
1070 uint32_t denominator; /*!< 30 bit denominator of fractional loop divider */
1071 uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */
1072 uint16_t ss_stop; /*!< Stop value to get frequency change. */
1073 uint8_t ss_enable; /*!< Enable spread spectrum modulation */
1074 uint16_t ss_step; /*!< Step value to get frequency change step. */
1075
1076 } clock_sys_pll_config_t;
1077
1078 /*! @brief PLL configuration for AUDIO and VIDEO */
1079 typedef struct _clock_audio_pll_config
1080 {
1081 uint8_t loopDivider; /*!< PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. */
1082 uint8_t postDivider; /*!< Divider after the PLL, should only be 1, 2, 4, 8, 16. */
1083 uint32_t numerator; /*!< 30 bit numerator of fractional loop divider.*/
1084 uint32_t denominator; /*!< 30 bit denominator of fractional loop divider */
1085 uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */
1086 } clock_audio_pll_config_t;
1087
1088 /*! @brief PLL configuration for ENET */
1089 typedef struct _clock_enet_pll_config
1090 {
1091 bool enableClkOutput; /*!< Power on and enable PLL clock output for ENET0 (ref_enetpll0). */
1092
1093 bool enableClkOutput500M; /*!< Power on and enable PLL clock output for ENET (ref_enetpll500M). */
1094
1095 bool enableClkOutput25M; /*!< Power on and enable PLL clock output for ENET1 (ref_enetpll1). */
1096 uint8_t loopDivider; /*!< Controls the frequency of the ENET0 reference clock.
1097 b00 25MHz
1098 b01 50MHz
1099 b10 100MHz (not 50% duty cycle)
1100 b11 125MHz */
1101 uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */
1102
1103 } clock_enet_pll_config_t;
1104
1105 /*! @brief PLL name */
1106 typedef enum _clock_pll
1107 {
1108 kCLOCK_PllSys = CCM_ANALOG_TUPLE(PLL_SYS_OFFSET, CCM_ANALOG_PLL_SYS_ENABLE_SHIFT), /*!< PLL SYS */
1109 kCLOCK_PllUsb1 = CCM_ANALOG_TUPLE(PLL_USB1_OFFSET, CCM_ANALOG_PLL_USB1_ENABLE_SHIFT), /*!< PLL USB1 */
1110 kCLOCK_PllAudio = CCM_ANALOG_TUPLE(PLL_AUDIO_OFFSET, CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT), /*!< PLL Audio */
1111
1112 kCLOCK_PllEnet = CCM_ANALOG_TUPLE(PLL_ENET_OFFSET, CCM_ANALOG_PLL_ENET_ENABLE_SHIFT), /*!< PLL Enet0 */
1113
1114 kCLOCK_PllEnet500M = CCM_ANALOG_TUPLE(PLL_ENET_OFFSET, CCM_ANALOG_PLL_ENET_ENET_500M_REF_EN_SHIFT), /*!< PLL ENET */
1115
1116 kCLOCK_PllEnet25M = CCM_ANALOG_TUPLE(PLL_ENET_OFFSET, CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT), /*!< PLL Enet1 */
1117
1118 } clock_pll_t;
1119
1120 /*! @brief PLL PFD name */
1121 typedef enum _clock_pfd
1122 {
1123 kCLOCK_Pfd0 = 0U, /*!< PLL PFD0 */
1124 kCLOCK_Pfd1 = 1U, /*!< PLL PFD1 */
1125 kCLOCK_Pfd2 = 2U, /*!< PLL PFD2 */
1126 kCLOCK_Pfd3 = 3U, /*!< PLL PFD3 */
1127 } clock_pfd_t;
1128
1129 /*!
1130 * @brief The enumerater of clock output1's clock source, such as USB1 PLL, SYS PLL and so on.
1131 */
1132 typedef enum _clock_output1_selection
1133 {
1134 kCLOCK_OutputPllUsb1Sw = 0U, /*!< Selects USB1 PLL SW clock(Divided by 2) output. */
1135 kCLOCK_OutputPllSys = 1U, /*!< Selects SYS PLL clock(Divided by 2) output. */
1136 kCLOCK_OutputPllENET500M = 2U, /*!< Selects ENET PLL clock(Divided by 2) output. */
1137 kCLOCK_OutputSemcClk = 5U, /*!< Selects semc clock root output. */
1138 kCLOCK_OutputAhbClk = 0xBU, /*!< Selects AHB clock root output. */
1139 kCLOCK_OutputIpgClk = 0xCU, /*!< Selects IPG clock root output. */
1140 kCLOCK_OutputPerClk = 0xDU, /*!< Selects PERCLK clock root output. */
1141 kCLOCK_OutputPll4MainClk = 0xFU, /*!< Selects PLL4 main clock output. */
1142 kCLOCK_DisableClockOutput1 = 0x10U, /*!< Disables CLKO1. */
1143 } clock_output1_selection_t;
1144
1145 /*!
1146 * @brief The enumerater of clock output2's clock source, such as USDHC1 clock root, LPI2C clock root and so on.
1147 *
1148 */
1149 typedef enum _clock_output2_selection
1150 {
1151 kCLOCK_OutputUsdhc1Clk = 3U, /*!< Selects USDHC1 clock root output. */
1152 kCLOCK_OutputLpi2cClk = 6U, /*!< Selects LPI2C clock root output. */
1153 kCLOCK_OutputOscClk = 0xEU, /*!< Selects OSC output. */
1154 kCLOCK_OutputLpspiClk = 0x10U, /*!< Selects LPSPI clock root output. */
1155 kCLOCK_OutputUsdhc2Clk = 0x11U, /*!< Selects USDHC2 clock root output. */
1156 kCLOCK_OutputSai1Clk = 0x12U, /*!< Selects SAI1 clock root output. */
1157 kCLOCK_OutputSai2Clk = 0x13U, /*!< Selects SAI2 clock root output. */
1158 kCLOCK_OutputSai3Clk = 0x14U, /*!< Selects SAI3 clock root output. */
1159 kCLOCK_OutputTraceClk = 0x16U, /*!< Selects Trace clock root output. */
1160 kCLOCK_OutputCanClk = 0x17U, /*!< Selects CAN clock root output. */
1161 kCLOCK_OutputFlexspiClk = 0x1BU, /*!< Selects FLEXSPI clock root output. */
1162 kCLOCK_OutputUartClk = 0x1CU, /*!< Selects UART clock root output. */
1163 kCLOCK_OutputSpdif0Clk = 0x1DU, /*!< Selects SPDIF0 clock root output. */
1164 kCLOCK_DisableClockOutput2 = 0x1FU, /*!< Disables CLKO2. */
1165 } clock_output2_selection_t;
1166
1167 /*!
1168 * @brief The enumerator of clock output's divider.
1169 */
1170 typedef enum _clock_output_divider
1171 {
1172 kCLOCK_DivideBy1 = 0U, /*!< Output clock divided by 1. */
1173 kCLOCK_DivideBy2, /*!< Output clock divided by 2. */
1174 kCLOCK_DivideBy3, /*!< Output clock divided by 3. */
1175 kCLOCK_DivideBy4, /*!< Output clock divided by 4. */
1176 kCLOCK_DivideBy5, /*!< Output clock divided by 5. */
1177 kCLOCK_DivideBy6, /*!< Output clock divided by 6. */
1178 kCLOCK_DivideBy7, /*!< Output clock divided by 7. */
1179 kCLOCK_DivideBy8, /*!< Output clock divided by 8. */
1180 } clock_output_divider_t;
1181
1182 /*!
1183 * @brief The enumerator of clock root.
1184 */
1185 typedef enum _clock_root
1186 {
1187 kCLOCK_Usdhc1ClkRoot = 0U, /*!< USDHC1 clock root. */
1188 kCLOCK_Usdhc2ClkRoot, /*!< USDHC2 clock root. */
1189 kCLOCK_FlexspiClkRoot, /*!< FLEXSPI clock root. */
1190 kCLOCK_LpspiClkRoot, /*!< LPSPI clock root. */
1191 kCLOCK_TraceClkRoot, /*!< Trace clock root. */
1192 kCLOCK_Sai1ClkRoot, /*!< SAI1 clock root. */
1193 kCLOCK_Sai2ClkRoot, /*!< SAI2 clock root. */
1194 kCLOCK_Sai3ClkRoot, /*!< SAI3 clock root. */
1195 kCLOCK_Lpi2cClkRoot, /*!< LPI2C clock root. */
1196 kCLOCK_CanClkRoot, /*!< CAN clock root. */
1197 kCLOCK_UartClkRoot, /*!< UART clock root. */
1198 kCLOCK_SpdifClkRoot, /*!< SPDIF clock root. */
1199 kCLOCK_Flexio1ClkRoot, /*!< FLEXIO1 clock root. */
1200 } clock_root_t;
1201
1202 /*******************************************************************************
1203 * API
1204 ******************************************************************************/
1205
1206 #if defined(__cplusplus)
1207 extern "C" {
1208 #endif /* __cplusplus */
1209
1210 /*!
1211 * @brief Set CCM MUX node to certain value.
1212 *
1213 * @param mux Which mux node to set, see \ref clock_mux_t.
1214 * @param value Clock mux value to set, different mux has different value range.
1215 */
CLOCK_SetMux(clock_mux_t mux,uint32_t value)1216 static inline void CLOCK_SetMux(clock_mux_t mux, uint32_t value)
1217 {
1218 uint32_t busyShift;
1219
1220 busyShift = CCM_TUPLE_BUSY_SHIFT(mux);
1221 CCM_TUPLE_REG(CCM, mux) = (CCM_TUPLE_REG(CCM, mux) & (~CCM_TUPLE_MASK(mux))) |
1222 (((uint32_t)((value) << CCM_TUPLE_SHIFT(mux))) & CCM_TUPLE_MASK(mux));
1223
1224 assert(busyShift <= CCM_NO_BUSY_WAIT);
1225
1226 /* Clock switch need Handshake? */
1227 if (CCM_NO_BUSY_WAIT != busyShift)
1228 {
1229 /* Wait until CCM internal handshake finish. */
1230 while ((CCM->CDHIPR & (1UL << busyShift)) != 0UL)
1231 {
1232 }
1233 }
1234 }
1235
1236 /*!
1237 * @brief Get CCM MUX value.
1238 *
1239 * @param mux Which mux node to get, see \ref clock_mux_t.
1240 * @return Clock mux value.
1241 */
CLOCK_GetMux(clock_mux_t mux)1242 static inline uint32_t CLOCK_GetMux(clock_mux_t mux)
1243 {
1244 return (CCM_TUPLE_REG(CCM, mux) & CCM_TUPLE_MASK(mux)) >> CCM_TUPLE_SHIFT(mux);
1245 }
1246
1247 /*!
1248 * @brief Set clock divider value.
1249 *
1250 * Example, set the ARM clock divider to divide by 2:
1251 * @code
1252 CLOCK_SetDiv(kCLOCK_ArmDiv, kCLOCK_ArmDivBy2);
1253 @endcode
1254 *
1255 * Example, set the LPI2C clock divider to divide by 5.
1256 * @code
1257 CLOCK_SetDiv(kCLOCK_Lpi2cDiv, kCLOCK_MiscDivBy5);
1258 @endcode
1259 *
1260 * Only @ref kCLOCK_PerclkDiv, @ref kCLOCK_CanDiv,@ref kCLOCK_UartDiv, @ref kCLOCK_Sai3Div,
1261 * @ref kCLOCK_Sai1Div, @ref kCLOCK_Sai2Div, @ref kCLOCK_Lpi2cDiv can use the divider kCLOCK_MiscDivByxxx.
1262 *
1263 * @param divider Which divider node to set.
1264 * @param value Clock div value to set, different divider has different value range. See @ref clock_div_value_t
1265 * for details.
1266 * Divided clock frequency = Undivided clock frequency / (value + 1)
1267 */
CLOCK_SetDiv(clock_div_t divider,uint32_t value)1268 static inline void CLOCK_SetDiv(clock_div_t divider, uint32_t value)
1269 {
1270 uint32_t busyShift;
1271
1272 busyShift = CCM_TUPLE_BUSY_SHIFT((uint32_t)divider);
1273 CCM_TUPLE_REG(CCM, divider) = (CCM_TUPLE_REG(CCM, divider) & (~CCM_TUPLE_MASK(divider))) |
1274 (((uint32_t)((value) << CCM_TUPLE_SHIFT(divider))) & CCM_TUPLE_MASK(divider));
1275
1276 assert(busyShift <= CCM_NO_BUSY_WAIT);
1277
1278 /* Clock switch need Handshake? */
1279 if (CCM_NO_BUSY_WAIT != busyShift)
1280 {
1281 /* Wait until CCM internal handshake finish. */
1282 while ((CCM->CDHIPR & (1UL << busyShift)) != 0UL)
1283 {
1284 }
1285 }
1286 }
1287
1288 /*!
1289 * @brief Get CCM DIV node value.
1290 *
1291 * @param divider Which div node to get, see \ref clock_div_t.
1292 */
CLOCK_GetDiv(clock_div_t divider)1293 static inline uint32_t CLOCK_GetDiv(clock_div_t divider)
1294 {
1295 return ((CCM_TUPLE_REG(CCM, divider) & CCM_TUPLE_MASK(divider)) >> CCM_TUPLE_SHIFT(divider));
1296 }
1297
1298 /*!
1299 * @brief Control the clock gate for specific IP.
1300 *
1301 * @param name Which clock to enable, see \ref clock_ip_name_t.
1302 * @param value Clock gate value to set, see \ref clock_gate_value_t.
1303 */
CLOCK_ControlGate(clock_ip_name_t name,clock_gate_value_t value)1304 static inline void CLOCK_ControlGate(clock_ip_name_t name, clock_gate_value_t value)
1305 {
1306 uint32_t index = ((uint32_t)name) >> 8U;
1307 uint32_t shift = ((uint32_t)name) & 0x1FU;
1308 volatile uint32_t *reg;
1309
1310 assert(index <= 6UL);
1311
1312 reg = (volatile uint32_t *)((uint32_t)((volatile uint32_t *)&CCM->CCGR0) + sizeof(volatile uint32_t *) * index);
1313 SDK_ATOMIC_LOCAL_CLEAR_AND_SET(reg, (3UL << shift), (((uint32_t)value) << shift));
1314 }
1315
1316 /*!
1317 * @brief Enable the clock for specific IP.
1318 *
1319 * @param name Which clock to enable, see \ref clock_ip_name_t.
1320 */
CLOCK_EnableClock(clock_ip_name_t name)1321 static inline void CLOCK_EnableClock(clock_ip_name_t name)
1322 {
1323 CLOCK_ControlGate(name, kCLOCK_ClockNeededRunWait);
1324 }
1325
1326 /*!
1327 * @brief Disable the clock for specific IP.
1328 *
1329 * @param name Which clock to disable, see \ref clock_ip_name_t.
1330 */
CLOCK_DisableClock(clock_ip_name_t name)1331 static inline void CLOCK_DisableClock(clock_ip_name_t name)
1332 {
1333 CLOCK_ControlGate(name, kCLOCK_ClockNotNeeded);
1334 }
1335
1336 /*!
1337 * @brief Setting the low power mode that system will enter on next assertion of dsm_request signal.
1338 *
1339 * @param mode Which mode to enter, see \ref clock_mode_t.
1340 */
CLOCK_SetMode(clock_mode_t mode)1341 static inline void CLOCK_SetMode(clock_mode_t mode)
1342 {
1343 CCM->CLPCR = (CCM->CLPCR & ~CCM_CLPCR_LPM_MASK) | CCM_CLPCR_LPM((uint32_t)mode);
1344 }
1345
1346 /*!
1347 * @brief Gets the OSC clock frequency.
1348 *
1349 * This function will return the external XTAL OSC frequency if it is selected as the source of OSC,
1350 * otherwise internal 24MHz RC OSC frequency will be returned.
1351 *
1352 * @return Clock frequency; If the clock is invalid, returns 0.
1353 */
CLOCK_GetOscFreq(void)1354 static inline uint32_t CLOCK_GetOscFreq(void)
1355 {
1356 return ((XTALOSC24M->LOWPWR_CTRL & (uint32_t)XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK) != 0UL) ? 24000000UL : g_xtalFreq;
1357 }
1358
1359 /*!
1360 * @brief Gets the AHB clock frequency.
1361 *
1362 * @return The AHB clock frequency value in hertz.
1363 */
1364 uint32_t CLOCK_GetAhbFreq(void);
1365
1366 /*!
1367 * @brief Gets the SEMC clock frequency.
1368 *
1369 * @return The SEMC clock frequency value in hertz.
1370 */
1371 uint32_t CLOCK_GetSemcFreq(void);
1372
1373 /*!
1374 * @brief Gets the IPG clock frequency.
1375 *
1376 * @return The IPG clock frequency value in hertz.
1377 */
1378 uint32_t CLOCK_GetIpgFreq(void);
1379
1380 /*!
1381 * @brief Gets the PER clock frequency.
1382 *
1383 * @return The PER clock frequency value in hertz.
1384 */
1385 uint32_t CLOCK_GetPerClkFreq(void);
1386
1387 /*!
1388 * @brief Gets the clock frequency for a specific clock name.
1389 *
1390 * This function checks the current clock configurations and then calculates
1391 * the clock frequency for a specific clock name defined in clock_name_t.
1392 *
1393 * @param name Clock names defined in clock_name_t
1394 * @return Clock frequency value in hertz
1395 */
1396 uint32_t CLOCK_GetFreq(clock_name_t name);
1397
1398 /*!
1399 * @brief Get the CCM CPU/core/system frequency.
1400 *
1401 * @return Clock frequency; If the clock is invalid, returns 0.
1402 */
CLOCK_GetCpuClkFreq(void)1403 static inline uint32_t CLOCK_GetCpuClkFreq(void)
1404 {
1405 return CLOCK_GetFreq(kCLOCK_CpuClk);
1406 }
1407
1408 /*!
1409 * @brief Gets the frequency of selected clock root.
1410 *
1411 * @param clockRoot The clock root used to get the frequency, please refer to @ref clock_root_t.
1412 * @return The frequency of selected clock root.
1413 */
1414 uint32_t CLOCK_GetClockRootFreq(clock_root_t clockRoot);
1415
1416 /*!
1417 * @name OSC operations
1418 * @{
1419 */
1420
1421 /*!
1422 * @brief Initialize the external 24MHz clock.
1423 *
1424 * This function supports two modes:
1425 * 1. Use external crystal oscillator.
1426 * 2. Bypass the external crystal oscillator, using input source clock directly.
1427 *
1428 * After this function, please call CLOCK_SetXtal0Freq to inform clock driver
1429 * the external clock frequency.
1430 *
1431 * @param bypassXtalOsc Pass in true to bypass the external crystal oscillator.
1432 * @note This device does not support bypass external crystal oscillator, so
1433 * the input parameter should always be false.
1434 */
1435 void CLOCK_InitExternalClk(bool bypassXtalOsc);
1436
1437 /*!
1438 * @brief Deinitialize the external 24MHz clock.
1439 *
1440 * This function disables the external 24MHz clock.
1441 *
1442 * After this function, please call CLOCK_SetXtal0Freq to set external clock
1443 * frequency to 0.
1444 */
1445 void CLOCK_DeinitExternalClk(void);
1446
1447 /*!
1448 * @brief Switch the OSC.
1449 *
1450 * This function switches the OSC source for SoC.
1451 *
1452 * @param osc OSC source to switch to.
1453 */
1454 void CLOCK_SwitchOsc(clock_osc_t osc);
1455
1456 /*!
1457 * @brief Gets the RTC clock frequency.
1458 *
1459 * @return Clock frequency; If the clock is invalid, returns 0.
1460 */
CLOCK_GetRtcFreq(void)1461 static inline uint32_t CLOCK_GetRtcFreq(void)
1462 {
1463 return 32768U;
1464 }
1465
1466 /*!
1467 * @brief Set the XTAL (24M OSC) frequency based on board setting.
1468 *
1469 * @param freq The XTAL input clock frequency in Hz.
1470 */
CLOCK_SetXtalFreq(uint32_t freq)1471 static inline void CLOCK_SetXtalFreq(uint32_t freq)
1472 {
1473 g_xtalFreq = freq;
1474 }
1475
1476 /*!
1477 * @brief Set the RTC XTAL (32K OSC) frequency based on board setting.
1478 *
1479 * @param freq The RTC XTAL input clock frequency in Hz.
1480 */
CLOCK_SetRtcXtalFreq(uint32_t freq)1481 static inline void CLOCK_SetRtcXtalFreq(uint32_t freq)
1482 {
1483 g_rtcXtalFreq = freq;
1484 }
1485
1486 /*!
1487 * @brief Initialize the RC oscillator 24MHz clock.
1488 */
1489 void CLOCK_InitRcOsc24M(void);
1490
1491 /*!
1492 * @brief Power down the RCOSC 24M clock.
1493 */
1494 void CLOCK_DeinitRcOsc24M(void);
1495 /* @} */
1496
1497 /*! @brief Enable USB HS clock.
1498 *
1499 * This function only enables the access to USB HS prepheral, upper layer
1500 * should first call the CLOCK_EnableUsbhs0PhyPllClock to enable the PHY
1501 * clock to use USB HS.
1502 *
1503 * @param src USB HS does not care about the clock source, here must be @ref kCLOCK_UsbSrcUnused.
1504 * @param freq USB HS does not care about the clock source, so this parameter is ignored.
1505 * @retval true The clock is set successfully.
1506 * @retval false The clock source is invalid to get proper USB HS clock.
1507 */
1508 bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq);
1509
1510 /* @} */
1511
1512 /*!
1513 * @name PLL/PFD operations
1514 * @{
1515 */
1516 /*!
1517 * @brief PLL bypass setting
1518 *
1519 * @param base CCM_ANALOG base pointer.
1520 * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration)
1521 * @param bypass Bypass the PLL.
1522 * - true: Bypass the PLL.
1523 * - false:Not bypass the PLL.
1524 */
CLOCK_SetPllBypass(CCM_ANALOG_Type * base,clock_pll_t pll,bool bypass)1525 static inline void CLOCK_SetPllBypass(CCM_ANALOG_Type *base, clock_pll_t pll, bool bypass)
1526 {
1527 if (bypass)
1528 {
1529 CCM_ANALOG_TUPLE_REG_OFF(base, pll, 4U) = 1UL << CCM_ANALOG_PLL_BYPASS_SHIFT;
1530 }
1531 else
1532 {
1533 CCM_ANALOG_TUPLE_REG_OFF(base, pll, 8U) = 1UL << CCM_ANALOG_PLL_BYPASS_SHIFT;
1534 }
1535 }
1536
1537 /*!
1538 * @brief Check if PLL is bypassed
1539 *
1540 * @param base CCM_ANALOG base pointer.
1541 * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration)
1542 * @return PLL bypass status.
1543 * - true: The PLL is bypassed.
1544 * - false: The PLL is not bypassed.
1545 */
CLOCK_IsPllBypassed(CCM_ANALOG_Type * base,clock_pll_t pll)1546 static inline bool CLOCK_IsPllBypassed(CCM_ANALOG_Type *base, clock_pll_t pll)
1547 {
1548 return (bool)(CCM_ANALOG_TUPLE_REG(base, pll) & (1UL << CCM_ANALOG_PLL_BYPASS_SHIFT));
1549 }
1550
1551 /*!
1552 * @brief Check if PLL is enabled
1553 *
1554 * @param base CCM_ANALOG base pointer.
1555 * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration)
1556 * @return PLL bypass status.
1557 * - true: The PLL is enabled.
1558 * - false: The PLL is not enabled.
1559 */
CLOCK_IsPllEnabled(CCM_ANALOG_Type * base,clock_pll_t pll)1560 static inline bool CLOCK_IsPllEnabled(CCM_ANALOG_Type *base, clock_pll_t pll)
1561 {
1562 return (bool)(CCM_ANALOG_TUPLE_REG(base, pll) & (1UL << CCM_ANALOG_TUPLE_SHIFT(pll)));
1563 }
1564
1565 /*!
1566 * @brief PLL bypass clock source setting.
1567 * Note: change the bypass clock source also change the pll reference clock source.
1568 *
1569 * @param base CCM_ANALOG base pointer.
1570 * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration)
1571 * @param src Bypass clock source, reference _clock_pll_bypass_clk_src.
1572 */
CLOCK_SetPllBypassRefClkSrc(CCM_ANALOG_Type * base,clock_pll_t pll,uint32_t src)1573 static inline void CLOCK_SetPllBypassRefClkSrc(CCM_ANALOG_Type *base, clock_pll_t pll, uint32_t src)
1574 {
1575 CCM_ANALOG_TUPLE_REG(base, pll) |= (CCM_ANALOG_TUPLE_REG(base, pll) & (~CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK)) | src;
1576 }
1577
1578 /*!
1579 * @brief Get PLL bypass clock value, it is PLL reference clock actually.
1580 * If CLOCK1_P,CLOCK1_N is choose as the pll bypass clock source, please implement the CLKPN_FREQ define, otherwise 0
1581 * will be returned.
1582 * @param base CCM_ANALOG base pointer.
1583 * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration)
1584 * @retval bypass reference clock frequency value.
1585 */
CLOCK_GetPllBypassRefClk(CCM_ANALOG_Type * base,clock_pll_t pll)1586 static inline uint32_t CLOCK_GetPllBypassRefClk(CCM_ANALOG_Type *base, clock_pll_t pll)
1587 {
1588 return ((((uint32_t)(CCM_ANALOG_TUPLE_REG(base, pll) & CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK)) >>
1589 CCM_ANALOG_PLL_BYPASS_CLK_SRC_SHIFT) == (uint32_t)kCLOCK_PllClkSrc24M) ?
1590 CLOCK_GetOscFreq() :
1591 CLKPN_FREQ;
1592 }
1593
1594 /*!
1595 * @brief Initialize the System PLL.
1596 *
1597 * This function initializes the System PLL with specific settings
1598 *
1599 * @param config Configuration to set to PLL.
1600 */
1601 void CLOCK_InitSysPll(const clock_sys_pll_config_t *config);
1602
1603 /*!
1604 * @brief De-initialize the System PLL.
1605 */
1606 void CLOCK_DeinitSysPll(void);
1607
1608 /*!
1609 * @brief Initialize the USB1 PLL.
1610 *
1611 * This function initializes the USB1 PLL with specific settings
1612 *
1613 * @param config Configuration to set to PLL.
1614 */
1615 void CLOCK_InitUsb1Pll(const clock_usb_pll_config_t *config);
1616
1617 /*!
1618 * @brief Deinitialize the USB1 PLL.
1619 */
1620 void CLOCK_DeinitUsb1Pll(void);
1621
1622 /*!
1623 * @brief Initializes the Audio PLL.
1624 *
1625 * This function initializes the Audio PLL with specific settings
1626 *
1627 * @param config Configuration to set to PLL.
1628 */
1629 void CLOCK_InitAudioPll(const clock_audio_pll_config_t *config);
1630
1631 /*!
1632 * @brief De-initialize the Audio PLL.
1633 */
1634 void CLOCK_DeinitAudioPll(void);
1635
1636 /*!
1637 * @brief Initialize the ENET PLL.
1638 *
1639 * This function initializes the ENET PLL with specific settings.
1640 *
1641 * @param config Configuration to set to PLL.
1642 */
1643 void CLOCK_InitEnetPll(const clock_enet_pll_config_t *config);
1644
1645 /*!
1646 * @brief Deinitialize the ENET PLL.
1647 *
1648 * This function disables the ENET PLL.
1649 */
1650 void CLOCK_DeinitEnetPll(void);
1651
1652 /*!
1653 * @brief Get current PLL output frequency.
1654 *
1655 * This function get current output frequency of specific PLL
1656 *
1657 * @param pll pll name to get frequency.
1658 * @return The PLL output frequency in hertz.
1659 */
1660 uint32_t CLOCK_GetPllFreq(clock_pll_t pll);
1661
1662 /*!
1663 * @brief Initialize the System PLL PFD.
1664 *
1665 * This function initializes the System PLL PFD. During new value setting,
1666 * the clock output is disabled to prevent glitch.
1667 *
1668 * @param pfd Which PFD clock to enable.
1669 * @param pfdFrac The PFD FRAC value.
1670 * @note It is recommended that PFD settings are kept between 12-35.
1671 */
1672 void CLOCK_InitSysPfd(clock_pfd_t pfd, uint8_t pfdFrac);
1673
1674 /*!
1675 * @brief De-initialize the System PLL PFD.
1676 *
1677 * This function disables the System PLL PFD.
1678 *
1679 * @param pfd Which PFD clock to disable.
1680 */
1681 void CLOCK_DeinitSysPfd(clock_pfd_t pfd);
1682
1683 /*!
1684 * @brief Check if Sys PFD is enabled
1685 *
1686 * @param pfd PFD control name
1687 * @return PFD bypass status.
1688 * - true: power on.
1689 * - false: power off.
1690 */
1691 bool CLOCK_IsSysPfdEnabled(clock_pfd_t pfd);
1692
1693 /*!
1694 * @brief Initialize the USB1 PLL PFD.
1695 *
1696 * This function initializes the USB1 PLL PFD. During new value setting,
1697 * the clock output is disabled to prevent glitch.
1698 *
1699 * @param pfd Which PFD clock to enable.
1700 * @param pfdFrac The PFD FRAC value.
1701 * @note It is recommended that PFD settings are kept between 12-35.
1702 */
1703 void CLOCK_InitUsb1Pfd(clock_pfd_t pfd, uint8_t pfdFrac);
1704
1705 /*!
1706 * @brief De-initialize the USB1 PLL PFD.
1707 *
1708 * This function disables the USB1 PLL PFD.
1709 *
1710 * @param pfd Which PFD clock to disable.
1711 */
1712 void CLOCK_DeinitUsb1Pfd(clock_pfd_t pfd);
1713
1714 /*!
1715 * @brief Check if Usb1 PFD is enabled
1716 *
1717 * @param pfd PFD control name.
1718 * @return PFD bypass status.
1719 * - true: power on.
1720 * - false: power off.
1721 */
1722 bool CLOCK_IsUsb1PfdEnabled(clock_pfd_t pfd);
1723
1724 /*!
1725 * @brief Get current System PLL PFD output frequency.
1726 *
1727 * This function get current output frequency of specific System PLL PFD
1728 *
1729 * @param pfd pfd name to get frequency.
1730 * @return The PFD output frequency in hertz.
1731 */
1732 uint32_t CLOCK_GetSysPfdFreq(clock_pfd_t pfd);
1733
1734 /*!
1735 * @brief Get current USB1 PLL PFD output frequency.
1736 *
1737 * This function get current output frequency of specific USB1 PLL PFD
1738 *
1739 * @param pfd pfd name to get frequency.
1740 * @return The PFD output frequency in hertz.
1741 */
1742 uint32_t CLOCK_GetUsb1PfdFreq(clock_pfd_t pfd);
1743
1744 /*! @brief Enable USB HS PHY PLL clock.
1745 *
1746 * This function enables the internal 480MHz USB PHY PLL clock.
1747 *
1748 * @param src USB HS PHY PLL clock source.
1749 * @param freq The frequency specified by src.
1750 * @retval true The clock is set successfully.
1751 * @retval false The clock source is invalid to get proper USB HS clock.
1752 */
1753 bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq);
1754
1755 /*! @brief Disable USB HS PHY PLL clock.
1756 *
1757 * This function disables USB HS PHY PLL clock.
1758 */
1759 void CLOCK_DisableUsbhs0PhyPllClock(void);
1760
1761 /* @} */
1762
1763 /*!
1764 * @name Clock Output Inferfaces
1765 * @{
1766 */
1767
1768 /*!
1769 * @brief Set the clock source and the divider of the clock output1.
1770 *
1771 * @param selection The clock source to be output, please refer to @ref clock_output1_selection_t.
1772 * @param divider The divider of the output clock signal, please refer to @ref clock_output_divider_t.
1773 */
1774 void CLOCK_SetClockOutput1(clock_output1_selection_t selection, clock_output_divider_t divider);
1775
1776 /*!
1777 * @brief Set the clock source and the divider of the clock output2.
1778 *
1779 * @param selection The clock source to be output, please refer to @ref clock_output2_selection_t.
1780 * @param divider The divider of the output clock signal, please refer to @ref clock_output_divider_t.
1781 */
1782 void CLOCK_SetClockOutput2(clock_output2_selection_t selection, clock_output_divider_t divider);
1783
1784 /*!
1785 * @brief Get the frequency of clock output1 clock signal.
1786 *
1787 * @return The frequency of clock output1 clock signal.
1788 */
1789 uint32_t CLOCK_GetClockOutCLKO1Freq(void);
1790
1791 /*!
1792 * @brief Get the frequency of clock output2 clock signal.
1793 *
1794 * @return The frequency of clock output2 clock signal.
1795 */
1796 uint32_t CLOCK_GetClockOutClkO2Freq(void);
1797
1798 /*! @} */
1799
1800 #if defined(__cplusplus)
1801 }
1802 #endif /* __cplusplus */
1803
1804 /*! @} */
1805
1806 #endif /* _FSL_CLOCK_H_ */
1807
