1 /*
2 * Copyright 2019 - 2021, 2024 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #ifndef _FSL_CLOCK_H_
9 #define _FSL_CLOCK_H_
10
11 #include "fsl_common.h"
12
13 /*! @addtogroup clock */
14 /*! @{ */
15
16 /*! @file */
17
18 /*******************************************************************************
19 * Configurations
20 ******************************************************************************/
21
22 /*! @brief Configure whether driver controls clock
23 *
24 * When set to 0, peripheral drivers will enable clock in initialize function
25 * and disable clock in de-initialize function. When set to 1, peripheral
26 * driver will not control the clock, application could control the clock out of
27 * the driver.
28 *
29 * @note All drivers share this feature switcher. If it is set to 1, application
30 * should handle clock enable and disable for all drivers.
31 */
32 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL))
33 #define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0
34 #endif
35
36 /*******************************************************************************
37 * Definitions
38 ******************************************************************************/
39
40 /*! @name Driver version */
41 /*@{*/
42 /*! @brief CLOCK driver version 2.5.3. */
43 #define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 5, 3))
44
45 /* analog pll definition */
46 #define CCM_ANALOG_PLL_BYPASS_SHIFT (16U)
47 #define CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK (0xC000U)
48 #define CCM_ANALOG_PLL_BYPASS_CLK_SRC_SHIFT (14U)
49
50 /* Definition for delay API in clock driver, users can redefine it to the real application. */
51 #ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
52 #define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (500000000UL)
53 #endif
54
55 /*@}*/
56
57 /*!
58 * @brief CCM registers offset.
59 */
60 #define CCSR_OFFSET 0x0C
61 #define CBCDR_OFFSET 0x14
62 #define CBCMR_OFFSET 0x18
63 #define CSCMR1_OFFSET 0x1C
64 #define CSCMR2_OFFSET 0x20
65 #define CSCDR1_OFFSET 0x24
66 #define CDCDR_OFFSET 0x30
67 #define CSCDR2_OFFSET 0x38
68 #define CS1CDR_OFFSET 0x28
69
70 /*!
71 * @brief CCM Analog registers offset.
72 */
73 #define PLL_SYS_OFFSET 0x30
74 #define PLL_USB1_OFFSET 0x10
75 #define PLL_AUDIO_OFFSET 0x70
76 #define PLL_ENET_OFFSET 0xE0
77
78 #define CCM_TUPLE(reg, shift, mask, busyShift) \
79 (int)(((reg)&0xFFU) | ((shift) << 8U) | ((((mask) >> (shift)) & 0x1FFFU) << 13U) | ((busyShift) << 26U))
80 #define CCM_TUPLE_REG(base, tuple) (*((volatile uint32_t *)(((uint32_t)(base)) + (((uint32_t)tuple) & 0xFFU))))
81 #define CCM_TUPLE_SHIFT(tuple) ((((uint32_t)tuple) >> 8U) & 0x1FU)
82 #define CCM_TUPLE_MASK(tuple) \
83 ((uint32_t)(((((uint32_t)tuple) >> 13U) & 0x1FFFU) << (((((uint32_t)tuple) >> 8U) & 0x1FU))))
84 #define CCM_TUPLE_BUSY_SHIFT(tuple) ((((uint32_t)tuple) >> 26U) & 0x3FU)
85
86 #define CCM_NO_BUSY_WAIT (0x20U)
87
88 /*!
89 * @brief CCM ANALOG tuple macros to map corresponding registers and bit fields.
90 */
91 #define CCM_ANALOG_TUPLE(reg, shift) ((((reg)&0xFFFU) << 16U) | (shift))
92 #define CCM_ANALOG_TUPLE_SHIFT(tuple) (((uint32_t)(tuple)) & 0x1FU)
93 #define CCM_ANALOG_TUPLE_REG_OFF(base, tuple, off) \
94 (*((volatile uint32_t *)((uint32_t)(base) + (((uint32_t)(tuple) >> 16U) & 0xFFFU) + (off))))
95 #define CCM_ANALOG_TUPLE_REG(base, tuple) CCM_ANALOG_TUPLE_REG_OFF(base, tuple, 0U)
96
97 #define CCM_ANALOG_PLL_BYPASS_SHIFT (16U)
98 #define CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK (0xC000U)
99 #define CCM_ANALOG_PLL_BYPASS_CLK_SRC_SHIFT (14U)
100
101 /*!
102 * @brief clock1PN frequency.
103 */
104 #define CLKPN_FREQ 0U
105
106 /*! @brief External XTAL (24M OSC/SYSOSC) clock frequency.
107 *
108 * The XTAL (24M OSC/SYSOSC) clock frequency in Hz, when the clock is setup, use the
109 * function CLOCK_SetXtalFreq to set the value in to clock driver. For example,
110 * if XTAL is 24MHz,
111 * @code
112 * CLOCK_InitExternalClk(false);
113 * CLOCK_SetXtalFreq(240000000);
114 * @endcode
115 */
116 extern volatile uint32_t g_xtalFreq;
117
118 /*! @brief External RTC XTAL (32K OSC) clock frequency.
119 *
120 * The RTC XTAL (32K OSC) clock frequency in Hz, when the clock is setup, use the
121 * function CLOCK_SetRtcXtalFreq to set the value in to clock driver.
122 */
123 extern volatile uint32_t g_rtcXtalFreq;
124
125 /* For compatible with other platforms */
126 #define CLOCK_SetXtal0Freq CLOCK_SetXtalFreq
127 #define CLOCK_SetXtal32Freq CLOCK_SetRtcXtalFreq
128
129 /*! @brief Clock ip name array for ADC. */
130 #define ADC_CLOCKS \
131 { \
132 kCLOCK_IpInvalid, kCLOCK_Adc1 \
133 }
134
135 /*! @brief Clock ip name array for AOI. */
136 #define AOI_CLOCKS \
137 { \
138 kCLOCK_Aoi \
139 }
140
141 /*! @brief Clock ip name array for DCDC. */
142 #define DCDC_CLOCKS \
143 { \
144 kCLOCK_Dcdc \
145 }
146
147 /*! @brief Clock ip name array for DCP. */
148 #define DCP_CLOCKS \
149 { \
150 kCLOCK_Dcp \
151 }
152
153 /*! @brief Clock ip name array for DMAMUX_CLOCKS. */
154 #define DMAMUX_CLOCKS \
155 { \
156 kCLOCK_Dma \
157 }
158
159 /*! @brief Clock ip name array for DMA. */
160 #define EDMA_CLOCKS \
161 { \
162 kCLOCK_Dma \
163 }
164
165 /*! @brief Clock ip name array for EWM. */
166 #define EWM_CLOCKS \
167 { \
168 kCLOCK_Ewm0 \
169 }
170
171 /*! @brief Clock ip name array for FLEXIO. */
172 #define FLEXIO_CLOCKS \
173 { \
174 kCLOCK_IpInvalid, kCLOCK_Flexio1 \
175 }
176
177 /*! @brief Clock ip name array for FLEXRAM. */
178 #define FLEXRAM_CLOCKS \
179 { \
180 kCLOCK_FlexRam \
181 }
182
183 /*! @brief Clock ip name array for FLEXSPI. */
184 #define FLEXSPI_CLOCKS \
185 { \
186 kCLOCK_FlexSpi \
187 }
188
189 /*! @brief Clock ip name array for GPIO. */
190 #define GPIO_CLOCKS \
191 { \
192 kCLOCK_IpInvalid, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_Gpio5 \
193 }
194
195 /*! @brief Clock ip name array for GPT. */
196 #define GPT_CLOCKS \
197 { \
198 kCLOCK_IpInvalid, kCLOCK_Gpt1, kCLOCK_Gpt2 \
199 }
200
201 /*! @brief Clock ip name array for KPP. */
202 #define KPP_CLOCKS \
203 { \
204 kCLOCK_Kpp \
205 }
206
207 /*! @brief Clock ip name array for LPI2C. */
208 #define LPI2C_CLOCKS \
209 { \
210 kCLOCK_IpInvalid, kCLOCK_Lpi2c1, kCLOCK_Lpi2c2 \
211 }
212
213 /*! @brief Clock ip name array for LPSPI. */
214 #define LPSPI_CLOCKS \
215 { \
216 kCLOCK_IpInvalid, kCLOCK_Lpspi1, kCLOCK_Lpspi2 \
217 }
218
219 /*! @brief Clock ip name array for LPUART. */
220 #define LPUART_CLOCKS \
221 { \
222 kCLOCK_IpInvalid, kCLOCK_Lpuart1, kCLOCK_Lpuart2, kCLOCK_Lpuart3, kCLOCK_Lpuart4 \
223 }
224
225 /*! @brief Clock ip name array for OCRAM EXSC. */
226 #define OCRAM_EXSC_CLOCKS \
227 { \
228 kCLOCK_OcramExsc \
229 }
230
231 /*! @brief Clock ip name array for PIT. */
232 #define PIT_CLOCKS \
233 { \
234 kCLOCK_Pit \
235 }
236
237 /*! @brief Clock ip name array for PWM. */
238 #define PWM_CLOCKS \
239 { \
240 {kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid}, \
241 { \
242 kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1 \
243 } \
244 }
245
246 /*! @brief Clock ip name array for RTWDOG. */
247 #define RTWDOG_CLOCKS \
248 { \
249 kCLOCK_Wdog3 \
250 }
251
252 /*! @brief Clock ip name array for SAI. */
253 #define SAI_CLOCKS \
254 { \
255 kCLOCK_IpInvalid, kCLOCK_Sai1, kCLOCK_IpInvalid, kCLOCK_Sai3 \
256 }
257
258 /*! @brief Clock ip name array for TRNG. */
259 #define TRNG_CLOCKS \
260 { \
261 kCLOCK_Trng \
262 }
263
264 /*! @brief Clock ip name array for WDOG. */
265 #define WDOG_CLOCKS \
266 { \
267 kCLOCK_IpInvalid, kCLOCK_Wdog1, kCLOCK_Wdog2 \
268 }
269
270 /*! @brief Clock ip name array for SPDIF. */
271 #define SPDIF_CLOCKS \
272 { \
273 kCLOCK_Spdif \
274 }
275
276 /*! @brief Clock ip name array for XBARA. */
277 #define XBARA_CLOCKS \
278 { \
279 kCLOCK_Xbar1 \
280 }
281
282 #define CLOCK_SOURCE_NONE (0xFFU)
283
284 #define CLOCK_ROOT_SOUCE \
285 { \
286 {kCLOCK_FlexspiSel, kCLOCK_PeriphClk2, kCLOCK_NoneName, kCLOCK_NoneName}, /*!< FLEXSPI clock root */ \
287 {kCLOCK_Usb1PllPfd1Clk, kCLOCK_Usb1PllPfd0Clk, kCLOCK_SysPllClk, \
288 kCLOCK_SysPllPfd2Clk}, /*!< LPSPI clock root. */ \
289 {kCLOCK_SysPllClk, kCLOCK_SysPllPfd2Clk, kCLOCK_SysPllPfd0Clk, \
290 kCLOCK_SysPllPfd1Clk}, /*!< Trace clock root. */ \
291 {kCLOCK_Usb1PllPfd2Clk, kCLOCK_Usb1SwClk, kCLOCK_AudioPllClk, kCLOCK_NoneName}, /*!< SAI1 clock root. */ \
292 {kCLOCK_Usb1PllPfd2Clk, kCLOCK_Usb1SwClk, kCLOCK_AudioPllClk, kCLOCK_NoneName}, /*!< SAI3 clock root. */ \
293 {kCLOCK_Usb1Sw60MClk, kCLOCK_OscClk, kCLOCK_NoneName, kCLOCK_NoneName}, /*!< LPI2C clock root. */ \
294 {kCLOCK_Usb1Sw80MClk, kCLOCK_OscClk, kCLOCK_PerClk, kCLOCK_NoneName}, /*!< UART clock root. */ \
295 {kCLOCK_AudioPllClk, kCLOCK_Usb1PllPfd2Clk, kCLOCK_NoneName, kCLOCK_Usb1SwClk}, /*!< SPDIF clock root. */ \
296 {kCLOCK_AudioPllClk, kCLOCK_Usb1PllPfd2Clk, kCLOCK_SysPllClk, \
297 kCLOCK_Usb1SwClk}, /*!< FLEXIO1 clock root. */ \
298 }
299
300 #define CLOCK_ROOT_MUX_TUPLE \
301 { \
302 kCLOCK_FlexspiSrcMux, kCLOCK_LpspiMux, kCLOCK_TraceMux, kCLOCK_Sai1Mux, kCLOCK_Sai3Mux, kCLOCK_Lpi2cMux, \
303 kCLOCK_UartMux, kCLOCK_SpdifMux, kCLOCK_Flexio1Mux, \
304 }
305
306 #define CLOCK_ROOT_NONE_PRE_DIV 0UL
307
308 #define CLOCK_ROOT_DIV_TUPLE \
309 { \
310 {kCLOCK_NonePreDiv, kCLOCK_FlexspiDiv}, /*!< FLEXSPI clock root */ \
311 {kCLOCK_NonePreDiv, kCLOCK_LpspiDiv}, /*!< LPSPI clock root. */ \
312 {kCLOCK_NonePreDiv, kCLOCK_TraceDiv}, /*!< Trace clock root. */ \
313 {kCLOCK_Sai1PreDiv, kCLOCK_Sai1Div}, /*!< SAI1 clock root. */ \
314 {kCLOCK_Sai3PreDiv, kCLOCK_Sai3Div}, /*!< SAI3 clock root. */ \
315 {kCLOCK_NonePreDiv, kCLOCK_Lpi2cDiv}, /*!< LPI2C clock root. */ \
316 {kCLOCK_NonePreDiv, kCLOCK_UartDiv}, /*!< UART clock root. */ \
317 {kCLOCK_Spdif0PreDiv, kCLOCK_Spdif0Div}, /*!< SPDIF clock root. */ \
318 {kCLOCK_Flexio1PreDiv, kCLOCK_Flexio1Div}, /*!< FLEXIO1 clock root. */ \
319 }
320
321 /*! @brief Clock name used to get clock frequency. */
322 typedef enum _clock_name
323 {
324 kCLOCK_CpuClk = 0x0U, /*!< CPU clock */
325 kCLOCK_CoreClk = 0x1U, /*!< CORE clock */
326 kCLOCK_IpgClk = 0x2U, /*!< IPG clock */
327 kCLOCK_PerClk = 0x3U, /*!< PER clock */
328
329 kCLOCK_OscClk = 0x4U, /*!< OSC clock selected by PMU_LOWPWR_CTRL[OSC_SEL]. */
330 kCLOCK_RtcClk = 0x5U, /*!< RTC clock. (RTCCLK) */
331
332 kCLOCK_Usb1PllClk = 0x6U, /*!< USB1PLLCLK. */
333 kCLOCK_Usb1PllPfd0Clk = 0x7U, /*!< USB1PLLPDF0CLK. */
334 kCLOCK_Usb1PllPfd1Clk = 0x8U, /*!< USB1PLLPFD1CLK. */
335 kCLOCK_Usb1PllPfd2Clk = 0x9U, /*!< USB1PLLPFD2CLK. */
336 kCLOCK_Usb1PllPfd3Clk = 0xAU, /*!< USB1PLLPFD3CLK. */
337 kCLOCK_Usb1SwClk = 0x12U, /*!< USB1PLLSWCLK */
338 kCLOCK_Usb1Sw60MClk = 0x13U, /*!< USB1PLLSw60MCLK */
339 kCLOCK_Usb1Sw80MClk = 0x14U, /*!< USB1PLLSw80MCLK */
340
341 kCLOCK_SysPllClk = 0xBU, /*!< SYSPLLCLK. */
342 kCLOCK_SysPllPfd0Clk = 0xCU, /*!< SYSPLLPDF0CLK. */
343 kCLOCK_SysPllPfd1Clk = 0xDU, /*!< SYSPLLPFD1CLK. */
344 kCLOCK_SysPllPfd2Clk = 0xEU, /*!< SYSPLLPFD2CLK. */
345 kCLOCK_SysPllPfd3Clk = 0xFU, /*!< SYSPLLPFD3CLK. */
346
347 kCLOCK_EnetPll500MClk = 0x10U, /*!< Enet PLLCLK ref_enetpll500M. */
348
349 kCLOCK_AudioPllClk = 0x11U, /*!< Audio PLLCLK. */
350
351 kCLOCK_PeriphClk2 = 0x15U, /*!< Periph CLK2 selection. */
352 kCLOCK_FlexspiSel = 0x16U, /*!< Flexspi selection. */
353 kCLOCK_NoneName = CLOCK_SOURCE_NONE, /*!< None Clock Name. */
354 } clock_name_t;
355
356 #define kCLOCK_CoreSysClk kCLOCK_CpuClk /*!< For compatible with other platforms without CCM. */
357 #define CLOCK_GetCoreSysClkFreq CLOCK_GetCpuClkFreq /*!< For compatible with other platforms without CCM. */
358
359 /*!
360 * @brief CCM CCGR gate control for each module independently.
361 */
362 typedef enum _clock_ip_name
363 {
364 kCLOCK_IpInvalid = -1,
365
366 /* CCM CCGR0 */
367 kCLOCK_Aips_tz1 = (0U << 8U) | CCM_CCGR0_CG0_SHIFT, /*!< CCGR0, CG0 */
368 kCLOCK_Aips_tz2 = (0U << 8U) | CCM_CCGR0_CG1_SHIFT, /*!< CCGR0, CG1 */
369 kCLOCK_Mqs = (0U << 8U) | CCM_CCGR0_CG2_SHIFT, /*!< CCGR0, CG2 */
370 kCLOCK_FlexSpiExsc = (0U << 8U) | CCM_CCGR0_CG3_SHIFT, /*!< CCGR0, CG3 */
371 kCLOCK_Sim_m_clk_r = (0U << 8U) | CCM_CCGR0_CG4_SHIFT, /*!< CCGR0, CG4 */
372 kCLOCK_Dcp = (0U << 8U) | CCM_CCGR0_CG5_SHIFT, /*!< CCGR0, CG5 */
373 kCLOCK_Lpuart3 = (0U << 8U) | CCM_CCGR0_CG6_SHIFT, /*!< CCGR0, CG6 */
374 kCLOCK_Trace = (0U << 8U) | CCM_CCGR0_CG11_SHIFT, /*!< CCGR0, CG11 */
375 kCLOCK_Gpt2 = (0U << 8U) | CCM_CCGR0_CG12_SHIFT, /*!< CCGR0, CG12 */
376 kCLOCK_Gpt2S = (0U << 8U) | CCM_CCGR0_CG13_SHIFT, /*!< CCGR0, CG13 */
377 kCLOCK_Lpuart2 = (0U << 8U) | CCM_CCGR0_CG14_SHIFT, /*!< CCGR0, CG14 */
378 kCLOCK_Gpio2 = (0U << 8U) | CCM_CCGR0_CG15_SHIFT, /*!< CCGR0, CG15 */
379
380 /* CCM CCGR1 */
381 kCLOCK_Lpspi1 = (1U << 8U) | CCM_CCGR1_CG0_SHIFT, /*!< CCGR1, CG0 */
382 kCLOCK_Lpspi2 = (1U << 8U) | CCM_CCGR1_CG1_SHIFT, /*!< CCGR1, CG1 */
383 kCLOCK_Pit = (1U << 8U) | CCM_CCGR1_CG6_SHIFT, /*!< CCGR1, CG6 */
384 kCLOCK_Adc1 = (1U << 8U) | CCM_CCGR1_CG8_SHIFT, /*!< CCGR1, CG8 */
385 kCLOCK_Gpt1 = (1U << 8U) | CCM_CCGR1_CG10_SHIFT, /*!< CCGR1, CG10 */
386 kCLOCK_Gpt1S = (1U << 8U) | CCM_CCGR1_CG11_SHIFT, /*!< CCGR1, CG11 */
387 kCLOCK_Lpuart4 = (1U << 8U) | CCM_CCGR1_CG12_SHIFT, /*!< CCGR1, CG12 */
388 kCLOCK_Gpio1 = (1U << 8U) | CCM_CCGR1_CG13_SHIFT, /*!< CCGR1, CG13 */
389 kCLOCK_Csu = (1U << 8U) | CCM_CCGR1_CG14_SHIFT, /*!< CCGR1, CG14 */
390 kCLOCK_Gpio5 = (1U << 8U) | CCM_CCGR1_CG15_SHIFT, /*!< CCGR1, CG15 */
391
392 /* CCM CCGR2 */
393 kCLOCK_OcramExsc = (2U << 8U) | CCM_CCGR2_CG0_SHIFT, /*!< CCGR2, CG0 */
394 kCLOCK_IomuxcSnvs = (2U << 8U) | CCM_CCGR2_CG2_SHIFT, /*!< CCGR2, CG2 */
395 kCLOCK_Lpi2c1 = (2U << 8U) | CCM_CCGR2_CG3_SHIFT, /*!< CCGR2, CG3 */
396 kCLOCK_Lpi2c2 = (2U << 8U) | CCM_CCGR2_CG4_SHIFT, /*!< CCGR2, CG4 */
397 kCLOCK_Ocotp = (2U << 8U) | CCM_CCGR2_CG6_SHIFT, /*!< CCGR2, CG6 */
398 kCLOCK_Xbar1 = (2U << 8U) | CCM_CCGR2_CG11_SHIFT, /*!< CCGR2, CG11 */
399
400 /* CCM CCGR3 */
401 kCLOCK_Aoi = (3U << 8U) | CCM_CCGR3_CG4_SHIFT, /*!< CCGR3, CG4 */
402 kCLOCK_Ewm0 = (3U << 8U) | CCM_CCGR3_CG7_SHIFT, /*!< CCGR3, CG7 */
403 kCLOCK_Wdog1 = (3U << 8U) | CCM_CCGR3_CG8_SHIFT, /*!< CCGR3, CG8 */
404 kCLOCK_FlexRam = (3U << 8U) | CCM_CCGR3_CG9_SHIFT, /*!< CCGR3, CG9 */
405 kCLOCK_IomuxcSnvsGpr = (3U << 8U) | CCM_CCGR3_CG15_SHIFT, /*!< CCGR3, CG15 */
406
407 /* CCM CCGR4 */
408 kCLOCK_Sim_m7_clk_r = (4U << 8U) | CCM_CCGR4_CG0_SHIFT, /*!< CCGR4, CG0 */
409 kCLOCK_Iomuxc = (4U << 8U) | CCM_CCGR4_CG1_SHIFT, /*!< CCGR4, CG1 */
410 kCLOCK_IomuxcGpr = (4U << 8U) | CCM_CCGR4_CG2_SHIFT, /*!< CCGR4, CG2 */
411 kCLOCK_SimM7 = (4U << 8U) | CCM_CCGR4_CG4_SHIFT, /*!< CCGR4, CG4 */
412 kCLOCK_SimM = (4U << 8U) | CCM_CCGR4_CG6_SHIFT, /*!< CCGR4, CG6 */
413 kCLOCK_SimEms = (4U << 8U) | CCM_CCGR4_CG7_SHIFT, /*!< CCGR4, CG7 */
414 kCLOCK_Pwm1 = (4U << 8U) | CCM_CCGR4_CG8_SHIFT, /*!< CCGR4, CG8 */
415 kCLOCK_Dma_ps = (4U << 8U) | CCM_CCGR4_CG15_SHIFT, /*!< CCGR4, CG15, */
416
417 /* CCM CCGR5 */
418 kCLOCK_Rom = (5U << 8U) | CCM_CCGR5_CG0_SHIFT, /*!< CCGR5, CG0 */
419 kCLOCK_Flexio1 = (5U << 8U) | CCM_CCGR5_CG1_SHIFT, /*!< CCGR5, CG1 */
420 kCLOCK_Wdog3 = (5U << 8U) | CCM_CCGR5_CG2_SHIFT, /*!< CCGR5, CG2 */
421 kCLOCK_Dma = (5U << 8U) | CCM_CCGR5_CG3_SHIFT, /*!< CCGR5, CG3 */
422 kCLOCK_Kpp = (5U << 8U) | CCM_CCGR5_CG4_SHIFT, /*!< CCGR5, CG4 */
423 kCLOCK_Wdog2 = (5U << 8U) | CCM_CCGR5_CG5_SHIFT, /*!< CCGR5, CG5 */
424 kCLOCK_Spdif = (5U << 8U) | CCM_CCGR5_CG7_SHIFT, /*!< CCGR5, CG7 */
425 kCLOCK_Sai1 = (5U << 8U) | CCM_CCGR5_CG9_SHIFT, /*!< CCGR5, CG9 */
426 kCLOCK_Sai3 = (5U << 8U) | CCM_CCGR5_CG11_SHIFT, /*!< CCGR5, CG11 */
427 kCLOCK_Lpuart1 = (5U << 8U) | CCM_CCGR5_CG12_SHIFT, /*!< CCGR5, CG12 */
428 kCLOCK_SnvsHp = (5U << 8U) | CCM_CCGR5_CG14_SHIFT, /*!< CCGR5, CG14 */
429 kCLOCK_SnvsLp = (5U << 8U) | CCM_CCGR5_CG15_SHIFT, /*!< CCGR5, CG15 */
430
431 /* CCM CCGR6 */
432 kCLOCK_UsbOh3 = (6U << 8U) | CCM_CCGR6_CG0_SHIFT, /*!< CCGR6, CG0 */
433 kCLOCK_Dcdc = (6U << 8U) | CCM_CCGR6_CG3_SHIFT, /*!< CCGR6, CG3 */
434 kCLOCK_FlexSpi = (6U << 8U) | CCM_CCGR6_CG5_SHIFT, /*!< CCGR6, CG5 */
435 kCLOCK_Trng = (6U << 8U) | CCM_CCGR6_CG6_SHIFT, /*!< CCGR6, CG6 */
436 kCLOCK_SimPer = (6U << 8U) | CCM_CCGR6_CG10_SHIFT, /*!< CCGR6, CG10 */
437 kCLOCK_Anadig = (6U << 8U) | CCM_CCGR6_CG11_SHIFT, /*!< CCGR6, CG11 */
438
439 } clock_ip_name_t;
440
441 /*! @brief OSC 24M sorce select */
442 typedef enum _clock_osc
443 {
444 kCLOCK_RcOsc = 0U, /*!< On chip OSC. */
445 kCLOCK_XtalOsc = 1U, /*!< 24M Xtal OSC */
446 } clock_osc_t;
447
448 /*! @brief Clock gate value */
449 typedef enum _clock_gate_value
450 {
451 kCLOCK_ClockNotNeeded = 0U, /*!< Clock is off during all modes. */
452 kCLOCK_ClockNeededRun = 1U, /*!< Clock is on in run mode, but off in WAIT and STOP modes */
453 kCLOCK_ClockNeededRunWait = 3U, /*!< Clock is on during all modes, except STOP mode */
454 } clock_gate_value_t;
455
456 /*! @brief System clock mode */
457 typedef enum _clock_mode_t
458 {
459 kCLOCK_ModeRun = 0U, /*!< Remain in run mode. */
460 kCLOCK_ModeWait = 1U, /*!< Transfer to wait mode. */
461 kCLOCK_ModeStop = 2U, /*!< Transfer to stop mode. */
462 } clock_mode_t;
463
464 /*!
465 * @brief MUX control names for clock mux setting.
466 *
467 * These constants define the mux control names for clock mux setting.\n
468 * - 0:7: REG offset to CCM_BASE in bytes.
469 * - 8:15: Root clock setting bit field shift.
470 * - 16:31: Root clock setting bit field width.
471 */
472 typedef enum _clock_mux
473 {
474 kCLOCK_Pll3SwMux = CCM_TUPLE(CCSR_OFFSET,
475 CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT,
476 CCM_CCSR_PLL3_SW_CLK_SEL_MASK,
477 CCM_NO_BUSY_WAIT), /*!< pll3_sw_clk mux name */
478
479 kCLOCK_PeriphMux = CCM_TUPLE(CBCDR_OFFSET,
480 CCM_CBCDR_PERIPH_CLK_SEL_SHIFT,
481 CCM_CBCDR_PERIPH_CLK_SEL_MASK,
482 CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT), /*!< periph mux name */
483
484 kCLOCK_PrePeriphMux = CCM_TUPLE(CBCMR_OFFSET,
485 CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT,
486 CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK,
487 CCM_NO_BUSY_WAIT), /*!< pre-periph mux name */
488 kCLOCK_TraceMux = CCM_TUPLE(CBCMR_OFFSET,
489 CCM_CBCMR_TRACE_CLK_SEL_SHIFT,
490 CCM_CBCMR_TRACE_CLK_SEL_MASK,
491 CCM_NO_BUSY_WAIT), /*!< trace mux name */
492 kCLOCK_PeriphClk2Mux = CCM_TUPLE(CBCMR_OFFSET,
493 CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT,
494 CCM_CBCMR_PERIPH_CLK2_SEL_MASK,
495 CCM_NO_BUSY_WAIT), /*!< periph clock2 mux name */
496 kCLOCK_LpspiMux = CCM_TUPLE(CBCMR_OFFSET,
497 CCM_CBCMR_LPSPI_CLK_SEL_SHIFT,
498 CCM_CBCMR_LPSPI_CLK_SEL_MASK,
499 CCM_NO_BUSY_WAIT), /*!< lpspi mux name */
500
501 kCLOCK_FlexspiMux = CCM_TUPLE(CSCMR1_OFFSET,
502 CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT,
503 CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK,
504 CCM_NO_BUSY_WAIT), /*!< flexspi mux name */
505 kCLOCK_FlexspiSrcMux = CCM_TUPLE(CSCMR1_OFFSET,
506 CCM_CSCMR1_FLEXSPI_CLK_SRC_SHIFT,
507 CCM_CSCMR1_FLEXSPI_CLK_SRC_MASK,
508 CCM_NO_BUSY_WAIT), /*!< flexspi SRC mux name */
509 kCLOCK_Sai3Mux = CCM_TUPLE(CSCMR1_OFFSET,
510 CCM_CSCMR1_SAI3_CLK_SEL_SHIFT,
511 CCM_CSCMR1_SAI3_CLK_SEL_MASK,
512 CCM_NO_BUSY_WAIT), /*!< sai3 mux name */
513 kCLOCK_Sai1Mux = CCM_TUPLE(CSCMR1_OFFSET,
514 CCM_CSCMR1_SAI1_CLK_SEL_SHIFT,
515 CCM_CSCMR1_SAI1_CLK_SEL_MASK,
516 CCM_NO_BUSY_WAIT), /*!< sai1 mux name */
517 kCLOCK_PerclkMux = CCM_TUPLE(CSCMR1_OFFSET,
518 CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT,
519 CCM_CSCMR1_PERCLK_CLK_SEL_MASK,
520 CCM_NO_BUSY_WAIT), /*!< perclk mux name */
521
522 kCLOCK_Flexio1Mux = CCM_TUPLE(CSCMR2_OFFSET,
523 CCM_CSCMR2_FLEXIO1_CLK_SEL_SHIFT,
524 CCM_CSCMR2_FLEXIO1_CLK_SEL_MASK,
525 CCM_NO_BUSY_WAIT), /*!< flexio1 mux name */
526
527 kCLOCK_UartMux = CCM_TUPLE(CSCDR1_OFFSET,
528 CCM_CSCDR1_UART_CLK_SEL_SHIFT,
529 CCM_CSCDR1_UART_CLK_SEL_MASK,
530 CCM_NO_BUSY_WAIT), /*!< uart mux name */
531
532 kCLOCK_SpdifMux = CCM_TUPLE(CDCDR_OFFSET,
533 CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT,
534 CCM_CDCDR_SPDIF0_CLK_SEL_MASK,
535 CCM_NO_BUSY_WAIT), /*!< spdif mux name */
536
537 kCLOCK_Lpi2cMux = CCM_TUPLE(CSCDR2_OFFSET,
538 CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT,
539 CCM_CSCDR2_LPI2C_CLK_SEL_MASK,
540 CCM_NO_BUSY_WAIT), /*!< lpi2c mux name */
541 } clock_mux_t;
542
543 /*!
544 * @brief DIV control names for clock div setting.
545 *
546 * These constants define div control names for clock div setting.\n
547 * - 0:7: REG offset to CCM_BASE in bytes.
548 * - 8:15: Root clock setting bit field shift.
549 * - 16:31: Root clock setting bit field width.
550 */
551 typedef enum _clock_div
552 {
553 kCLOCK_AhbDiv = CCM_TUPLE(CBCDR_OFFSET,
554 CCM_CBCDR_AHB_PODF_SHIFT,
555 CCM_CBCDR_AHB_PODF_MASK,
556 CCM_CDHIPR_AHB_PODF_BUSY_SHIFT), /*!< ahb div name */
557 kCLOCK_IpgDiv = CCM_TUPLE(
558 CBCDR_OFFSET, CCM_CBCDR_IPG_PODF_SHIFT, CCM_CBCDR_IPG_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< ipg div name */
559
560 kCLOCK_LpspiDiv = CCM_TUPLE(
561 CBCMR_OFFSET, CCM_CBCMR_LPSPI_PODF_SHIFT, CCM_CBCMR_LPSPI_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< lpspi div name */
562
563 kCLOCK_FlexspiDiv = CCM_TUPLE(CSCMR1_OFFSET,
564 CCM_CSCMR1_FLEXSPI_PODF_SHIFT,
565 CCM_CSCMR1_FLEXSPI_PODF_MASK,
566 CCM_NO_BUSY_WAIT), /*!< flexspi div name */
567 kCLOCK_PerclkDiv = CCM_TUPLE(CSCMR1_OFFSET,
568 CCM_CSCMR1_PERCLK_PODF_SHIFT,
569 CCM_CSCMR1_PERCLK_PODF_MASK,
570 CCM_NO_BUSY_WAIT), /*!< perclk div name */
571 kCLOCK_AdcDiv = CCM_TUPLE(CSCMR2_OFFSET,
572 CCM_CSCMR2_ADC_ACLK_PODF_SHIFT,
573 CCM_CSCMR2_ADC_ACLK_PODF_MASK,
574 CCM_NO_BUSY_WAIT), /*!< adc name */
575
576 kCLOCK_TraceDiv = CCM_TUPLE(CSCDR1_OFFSET,
577 CCM_CSCDR1_TRACE_PODF_SHIFT,
578 CCM_CSCDR1_TRACE_PODF_MASK,
579 CCM_NO_BUSY_WAIT), /*!< trace div name */
580 kCLOCK_UartDiv = CCM_TUPLE(CSCDR1_OFFSET,
581 CCM_CSCDR1_UART_CLK_PODF_SHIFT,
582 CCM_CSCDR1_UART_CLK_PODF_MASK,
583 CCM_NO_BUSY_WAIT), /*!< uart div name */
584
585 kCLOCK_Flexio1Div = CCM_TUPLE(CS1CDR_OFFSET,
586 CCM_CS1CDR_FLEXIO1_CLK_PODF_SHIFT,
587 CCM_CS1CDR_FLEXIO1_CLK_PODF_MASK,
588 CCM_NO_BUSY_WAIT), /*!< flexio1 pre div name */
589 kCLOCK_Sai3PreDiv = CCM_TUPLE(CS1CDR_OFFSET,
590 CCM_CS1CDR_SAI3_CLK_PRED_SHIFT,
591 CCM_CS1CDR_SAI3_CLK_PRED_MASK,
592 CCM_NO_BUSY_WAIT), /*!< sai3 pre div name */
593 kCLOCK_Sai3Div = CCM_TUPLE(CS1CDR_OFFSET,
594 CCM_CS1CDR_SAI3_CLK_PODF_SHIFT,
595 CCM_CS1CDR_SAI3_CLK_PODF_MASK,
596 CCM_NO_BUSY_WAIT), /*!< sai3 div name */
597 kCLOCK_Flexio1PreDiv = CCM_TUPLE(CS1CDR_OFFSET,
598 CCM_CS1CDR_FLEXIO1_CLK_PRED_SHIFT,
599 CCM_CS1CDR_FLEXIO1_CLK_PRED_MASK,
600 CCM_NO_BUSY_WAIT), /*!< flexio1 pre div name */
601 kCLOCK_Sai1PreDiv = CCM_TUPLE(CS1CDR_OFFSET,
602 CCM_CS1CDR_SAI1_CLK_PRED_SHIFT,
603 CCM_CS1CDR_SAI1_CLK_PRED_MASK,
604 CCM_NO_BUSY_WAIT), /*!< sai1 pre div name */
605 kCLOCK_Sai1Div = CCM_TUPLE(CS1CDR_OFFSET,
606 CCM_CS1CDR_SAI1_CLK_PODF_SHIFT,
607 CCM_CS1CDR_SAI1_CLK_PODF_MASK,
608 CCM_NO_BUSY_WAIT), /*!< sai1 div name */
609
610 kCLOCK_Spdif0PreDiv = CCM_TUPLE(CDCDR_OFFSET,
611 CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT,
612 CCM_CDCDR_SPDIF0_CLK_PRED_MASK,
613 CCM_NO_BUSY_WAIT), /*!< spdif pre div name */
614 kCLOCK_Spdif0Div = CCM_TUPLE(CDCDR_OFFSET,
615 CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT,
616 CCM_CDCDR_SPDIF0_CLK_PODF_MASK,
617 CCM_NO_BUSY_WAIT), /*!< spdif div name */
618
619 kCLOCK_Lpi2cDiv = CCM_TUPLE(CSCDR2_OFFSET,
620 CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT,
621 CCM_CSCDR2_LPI2C_CLK_PODF_MASK,
622 CCM_NO_BUSY_WAIT), /*!< lpi2c div name */
623 kCLOCK_NonePreDiv = CLOCK_ROOT_NONE_PRE_DIV, /*!< None Pre div. */
624 } clock_div_t;
625
626 /*!
627 * @brief Clock divider value.
628 */
629 typedef enum _clock_div_value
630 {
631 kCLOCK_AhbDivBy1 = 0, /*!< Ahb clock divider set to divided by 1. */
632 kCLOCK_AhbDivBy2 = 1, /*!< Ahb clock divider set to divided by 2. */
633 kCLOCK_AhbDivBy3 = 2, /*!< Ahb clock divider set to divided by 3. */
634 kCLOCK_AhbDivBy4 = 3, /*!< Ahb clock divider set to divided by 4. */
635 kCLOCK_AhbDivBy5 = 4, /*!< Ahb clock divider set to divided by 5. */
636 kCLOCK_AhbDivBy6 = 5, /*!< Ahb clock divider set to divided by 6. */
637 kCLOCK_AhbDivBy7 = 6, /*!< Ahb clock divider set to divided by 7. */
638 kCLOCK_AhbDivBy8 = 7, /*!< Ahb clock divider set to divided by 8. */
639
640 kCLOCK_IpgDivBy1 = 0, /*!< ipg clock divider set to divided by 1. */
641 kCLOCK_IpgDivBy2 = 1, /*!< ipg clock divider set to divided by 2. */
642 kCLOCK_IpgDivBy3 = 2, /*!< ipg clock divider set to divided by 3. */
643 kCLOCK_IpgDivBy4 = 3, /*!< ipg clock divider set to divided by 4. */
644
645 kCLOCK_LpspiDivBy1 = 0, /*!< lpspi clock divider set to divided by 1. */
646 kCLOCK_LpspiDivBy2 = 1, /*!< lpspi clock divider set to divided by 2. */
647 kCLOCK_LpspiDivBy3 = 2, /*!< lpspi clock divider set to divided by 3. */
648 kCLOCK_LpspiDivBy4 = 3, /*!< lpspi clock divider set to divided by 4. */
649 kCLOCK_LpspiDivBy5 = 4, /*!< lpspi clock divider set to divided by 5. */
650 kCLOCK_LpspiDivBy6 = 5, /*!< lpspi clock divider set to divided by 6. */
651 kCLOCK_LpspiDivBy7 = 6, /*!< lpspi clock divider set to divided by 7. */
652 kCLOCK_LpspiDivBy8 = 7, /*!< lpspi clock divider set to divided by 8. */
653 kCLOCK_LpspiDivBy9 = 8, /*!< lpspi clock divider set to divided by 9. */
654 kCLOCK_LpspiDivBy10 = 9, /*!< lpspi clock divider set to divided by 10. */
655 kCLOCK_LpspiDivBy11 = 10, /*!< lpspi clock divider set to divided by 11. */
656 kCLOCK_LpspiDivBy12 = 11, /*!< lpspi clock divider set to divided by 12. */
657 kCLOCK_LpspiDivBy13 = 12, /*!< lpspi clock divider set to divided by 13. */
658 kCLOCK_LpspiDivBy14 = 13, /*!< lpspi clock divider set to divided by 14. */
659 kCLOCK_LpspiDivBy15 = 14, /*!< lpspi clock divider set to divided by 15. */
660 kCLOCK_LpspiDivBy16 = 15, /*!< lpspi clock divider set to divided by 16. */
661
662 kCLOCK_FlexspiDivBy1 = 0, /*!< flexspi clock divider set to divided by 1. */
663 kCLOCK_FlexspiDivBy2 = 1, /*!< flexspi clock divider set to divided by 2. */
664 kCLOCK_FlexspiDivBy3 = 2, /*!< flexspi clock divider set to divided by 3. */
665 kCLOCK_FlexspiDivBy4 = 3, /*!< flexspi clock divider set to divided by 4. */
666 kCLOCK_FlexspiDivBy5 = 4, /*!< flexspi clock divider set to divided by 5. */
667 kCLOCK_FlexspiDivBy6 = 5, /*!< flexspi clock divider set to divided by 6. */
668 kCLOCK_FlexspiDivBy7 = 6, /*!< flexspi clock divider set to divided by 7. */
669 kCLOCK_FlexspiDivBy8 = 7, /*!< flexspi clock divider set to divided by 8. */
670
671 kCLOCK_AdcDivBy8 = 7, /*!< adc clock divider set to divided by 8. */
672 kCLOCK_AdcDivBy12 = 11, /*!< adc clock divider set to divided by 12. */
673 kCLOCK_AdcDivBy16 = 15, /*!< adc clock divider set to divided by 16. */
674
675 kCLOCK_TraceDivBy1 = 0, /*!< trace clock divider set to divided by 1. */
676 kCLOCK_TraceDivBy2 = 1, /*!< trace clock divider set to divided by 2. */
677 kCLOCK_TraceDivBy3 = 2, /*!< trace clock divider set to divided by 3. */
678 kCLOCK_TraceDivBy4 = 3, /*!< trace clock divider set to divided by 4. */
679 kCLOCK_TraceDivBy5 = 4, /*!< trace clock divider set to divided by 5. */
680 kCLOCK_TraceDivBy6 = 5, /*!< trace clock divider set to divided by 6. */
681 kCLOCK_TraceDivBy7 = 6, /*!< trace clock divider set to divided by 7. */
682 kCLOCK_TraceDivBy8 = 7, /*!< trace clock divider set to divided by 8. */
683 kCLOCK_TraceDivBy9 = 8, /*!< trace clock divider set to divided by 9. */
684 kCLOCK_TraceDivBy10 = 9, /*!< trace clock divider set to divided by 10. */
685 kCLOCK_TraceDivBy11 = 10, /*!< trace clock divider set to divided by 11. */
686 kCLOCK_TraceDivBy12 = 11, /*!< trace clock divider set to divided by 12. */
687 kCLOCK_TraceDivBy13 = 12, /*!< trace clock divider set to divided by 13. */
688 kCLOCK_TraceDivBy14 = 13, /*!< trace clock divider set to divided by 14. */
689 kCLOCK_TraceDivBy15 = 14, /*!< trace clock divider set to divided by 15. */
690 kCLOCK_TraceDivBy16 = 15, /*!< trace clock divider set to divided by 16. */
691
692 kCLOCK_Flexio1DivBy1 = 0, /*!< flexio1 clock divider set to divided by 1. */
693 kCLOCK_Flexio1DivBy2 = 1, /*!< flexio1 clock divider set to divided by 2. */
694 kCLOCK_Flexio1DivBy3 = 2, /*!< flexio1 clock divider set to divided by 3. */
695 kCLOCK_Flexio1DivBy4 = 3, /*!< flexio1 clock divider set to divided by 4. */
696 kCLOCK_Flexio1DivBy5 = 4, /*!< flexio1 clock divider set to divided by 5. */
697 kCLOCK_Flexio1DivBy6 = 5, /*!< flexio1 clock divider set to divided by 6. */
698 kCLOCK_Flexio1DivBy7 = 6, /*!< flexio1 clock divider set to divided by 7. */
699 kCLOCK_Flexio1DivBy8 = 7, /*!< flexio1 clock divider set to divided by 8. */
700 kCLOCK_Flexio1DivBy9 = 8, /*!< flexio1 clock divider set to divided by 9. */
701 kCLOCK_Flexio1DivBy10 = 9, /*!< flexio1 clock divider set to divided by 10. */
702 kCLOCK_Flexio1DivBy11 = 10, /*!< flexio1 clock divider set to divided by 11. */
703 kCLOCK_Flexio1DivBy12 = 11, /*!< flexio1 clock divider set to divided by 12. */
704 kCLOCK_Flexio1DivBy13 = 12, /*!< flexio1 clock divider set to divided by 13. */
705 kCLOCK_Flexio1DivBy14 = 13, /*!< flexio1 clock divider set to divided by 14. */
706 kCLOCK_Flexio1DivBy15 = 14, /*!< flexio1 clock divider set to divided by 15. */
707 kCLOCK_Flexio1DivBy16 = 15, /*!< flexio1 clock divider set to divided by 16. */
708
709 kCLOCK_Sai3PreDivBy1 = 0, /*!< sai3 pre clock divider set to divided by 1. */
710 kCLOCK_Sai3PreDivBy2 = 1, /*!< sai3 pre clock divider set to divided by 2. */
711 kCLOCK_Sai3PreDivBy3 = 2, /*!< sai3 pre clock divider set to divided by 3. */
712 kCLOCK_Sai3PreDivBy4 = 3, /*!< sai3 pre clock divider set to divided by 4. */
713 kCLOCK_Sai3PreDivBy5 = 4, /*!< sai3 pre clock divider set to divided by 5. */
714 kCLOCK_Sai3PreDivBy6 = 5, /*!< sai3 pre clock divider set to divided by 6. */
715 kCLOCK_Sai3PreDivBy7 = 6, /*!< sai3 pre clock divider set to divided by 7. */
716 kCLOCK_Sai3PreDivBy8 = 7, /*!< sai3 pre clock divider set to divided by 8. */
717
718 kCLOCK_Flexio1PreDivBy1 = 0, /*!< flexio1 pre clock divider set to divided by 1. */
719 kCLOCK_Flexio1PreDivBy2 = 1, /*!< flexio1 pre clock divider set to divided by 2. */
720 kCLOCK_Flexio1PreDivBy3 = 2, /*!< flexio1 pre clock divider set to divided by 3. */
721 kCLOCK_Flexio1PreDivBy4 = 3, /*!< flexio1 pre clock divider set to divided by 4. */
722 kCLOCK_Flexio1PreDivBy5 = 4, /*!< flexio1 pre clock divider set to divided by 5. */
723 kCLOCK_Flexio1PreDivBy6 = 5, /*!< flexio1 pre clock divider set to divided by 6. */
724 kCLOCK_Flexio1PreDivBy7 = 6, /*!< flexio1 pre clock divider set to divided by 7. */
725 kCLOCK_Flexio1PreDivBy8 = 7, /*!< flexio1 pre clock divider set to divided by 8. */
726
727 kCLOCK_Sai1PreDivBy1 = 0, /*!< sai1 pre clock divider set to divided by 1. */
728 kCLOCK_Sai1PreDivBy2 = 1, /*!< sai1 pre clock divider set to divided by 2. */
729 kCLOCK_Sai1PreDivBy3 = 2, /*!< sai1 pre clock divider set to divided by 3. */
730 kCLOCK_Sai1PreDivBy4 = 3, /*!< sai1 pre clock divider set to divided by 4. */
731 kCLOCK_Sai1PreDivBy5 = 4, /*!< sai1 pre clock divider set to divided by 5. */
732 kCLOCK_Sai1PreDivBy6 = 5, /*!< sai1 pre clock divider set to divided by 6. */
733 kCLOCK_Sai1PreDivBy7 = 6, /*!< sai1 pre clock divider set to divided by 7. */
734 kCLOCK_Sai1PreDivBy8 = 7, /*!< sai1 pre clock divider set to divided by 8. */
735
736 kCLOCK_Spdif0PreDivBy1 = 0, /*!< spdif pre clock divider set to divided by 1. */
737 kCLOCK_Spdif0PreDivBy2 = 1, /*!< spdif pre clock divider set to divided by 2. */
738 kCLOCK_Spdif0PreDivBy3 = 2, /*!< spdif pre clock divider set to divided by 3. */
739 kCLOCK_Spdif0PreDivBy4 = 3, /*!< spdif pre clock divider set to divided by 4. */
740 kCLOCK_Spdif0PreDivBy5 = 4, /*!< spdif pre clock divider set to divided by 5. */
741 kCLOCK_Spdif0PreDivBy6 = 5, /*!< spdif pre clock divider set to divided by 6. */
742 kCLOCK_Spdif0PreDivBy7 = 6, /*!< spdif pre clock divider set to divided by 7. */
743 kCLOCK_Spdif0PreDivBy8 = 7, /*!< spdif pre clock divider set to divided by 8. */
744
745 kCLOCK_Spdif0DivBy1 = 0, /*!< spdif clock divider set to divided by 1. */
746 kCLOCK_Spdif0DivBy2 = 1, /*!< spdif clock divider set to divided by 2. */
747 kCLOCK_Spdif0DivBy3 = 2, /*!< spdif clock divider set to divided by 3. */
748 kCLOCK_Spdif0DivBy4 = 3, /*!< spdif clock divider set to divided by 4. */
749 kCLOCK_Spdif0DivBy5 = 4, /*!< spdif clock divider set to divided by 5. */
750 kCLOCK_Spdif0DivBy6 = 5, /*!< spdif clock divider set to divided by 6. */
751 kCLOCK_Spdif0DivBy7 = 6, /*!< spdif clock divider set to divided by 7. */
752 kCLOCK_Spdif0DivBy8 = 7, /*!< spdif clock divider set to divided by 8. */
753
754 /* Only kCLOCK_PerclkDiv, kCLOCK_UartDiv, kCLOCK_Sai3Div,
755 *kCLOCK_Sai1Div, kCLOCK_Lpi2cDiv can use these.*/
756 kCLOCK_MiscDivBy1 = 0, /*!< Misc divider like LPI2C set to divided by 1. */
757 kCLOCK_MiscDivBy2 = 1, /*!< Misc divider like LPI2C set to divided by 2. */
758 kCLOCK_MiscDivBy3 = 2, /*!< Misc divider like LPI2C set to divided by 3. */
759 kCLOCK_MiscDivBy4 = 3, /*!< Misc divider like LPI2C set to divided by 4. */
760 kCLOCK_MiscDivBy5 = 4, /*!< Misc divider like LPI2C set to divided by 5. */
761 kCLOCK_MiscDivBy6 = 5, /*!< Misc divider like LPI2C set to divided by 6. */
762 kCLOCK_MiscDivBy7 = 6, /*!< Misc divider like LPI2C set to divided by 7. */
763 kCLOCK_MiscDivBy8 = 7, /*!< Misc divider like LPI2C set to divided by 8. */
764 kCLOCK_MiscDivBy9 = 8, /*!< Misc divider like LPI2C set to divided by 9. */
765 kCLOCK_MiscDivBy10 = 9, /*!< Misc divider like LPI2C set to divided by 10. */
766 kCLOCK_MiscDivBy11 = 10, /*!< Misc divider like LPI2C set to divided by 11. */
767 kCLOCK_MiscDivBy12 = 11, /*!< Misc divider like LPI2C set to divided by 12. */
768 kCLOCK_MiscDivBy13 = 12, /*!< Misc divider like LPI2C set to divided by 13. */
769 kCLOCK_MiscDivBy14 = 13, /*!< Misc divider like LPI2C set to divided by 14. */
770 kCLOCK_MiscDivBy15 = 14, /*!< Misc divider like LPI2C set to divided by 15. */
771 kCLOCK_MiscDivBy16 = 15, /*!< Misc divider like LPI2C set to divided by 16. */
772 kCLOCK_MiscDivBy17 = 16, /*!< Misc divider like LPI2C set to divided by 17. */
773 kCLOCK_MiscDivBy18 = 17, /*!< Misc divider like LPI2C set to divided by 18. */
774 kCLOCK_MiscDivBy19 = 18, /*!< Misc divider like LPI2C set to divided by 19. */
775 kCLOCK_MiscDivBy20 = 19, /*!< Misc divider like LPI2C set to divided by 20. */
776 kCLOCK_MiscDivBy21 = 20, /*!< Misc divider like LPI2C set to divided by 21. */
777 kCLOCK_MiscDivBy22 = 21, /*!< Misc divider like LPI2C set to divided by 22. */
778 kCLOCK_MiscDivBy23 = 22, /*!< Misc divider like LPI2C set to divided by 23. */
779 kCLOCK_MiscDivBy24 = 23, /*!< Misc divider like LPI2C set to divided by 24. */
780 kCLOCK_MiscDivBy25 = 24, /*!< Misc divider like LPI2C set to divided by 25. */
781 kCLOCK_MiscDivBy26 = 25, /*!< Misc divider like LPI2C set to divided by 26. */
782 kCLOCK_MiscDivBy27 = 26, /*!< Misc divider like LPI2C set to divided by 27. */
783 kCLOCK_MiscDivBy28 = 27, /*!< Misc divider like LPI2C set to divided by 28. */
784 kCLOCK_MiscDivBy29 = 28, /*!< Misc divider like LPI2C set to divided by 29. */
785 kCLOCK_MiscDivBy30 = 29, /*!< Misc divider like LPI2C set to divided by 30. */
786 kCLOCK_MiscDivBy31 = 30, /*!< Misc divider like LPI2C set to divided by 31. */
787 kCLOCK_MiscDivBy32 = 31, /*!< Misc divider like LPI2C set to divided by 32. */
788 kCLOCK_MiscDivBy33 = 32, /*!< Misc divider like LPI2C set to divided by 33. */
789 kCLOCK_MiscDivBy34 = 33, /*!< Misc divider like LPI2C set to divided by 34. */
790 kCLOCK_MiscDivBy35 = 34, /*!< Misc divider like LPI2C set to divided by 35. */
791 kCLOCK_MiscDivBy36 = 35, /*!< Misc divider like LPI2C set to divided by 36. */
792 kCLOCK_MiscDivBy37 = 36, /*!< Misc divider like LPI2C set to divided by 37. */
793 kCLOCK_MiscDivBy38 = 37, /*!< Misc divider like LPI2C set to divided by 38. */
794 kCLOCK_MiscDivBy39 = 38, /*!< Misc divider like LPI2C set to divided by 39. */
795 kCLOCK_MiscDivBy40 = 39, /*!< Misc divider like LPI2C set to divided by 40. */
796 kCLOCK_MiscDivBy41 = 40, /*!< Misc divider like LPI2C set to divided by 41. */
797 kCLOCK_MiscDivBy42 = 41, /*!< Misc divider like LPI2C set to divided by 42. */
798 kCLOCK_MiscDivBy43 = 42, /*!< Misc divider like LPI2C set to divided by 43. */
799 kCLOCK_MiscDivBy44 = 43, /*!< Misc divider like LPI2C set to divided by 44. */
800 kCLOCK_MiscDivBy45 = 44, /*!< Misc divider like LPI2C set to divided by 45. */
801 kCLOCK_MiscDivBy46 = 45, /*!< Misc divider like LPI2C set to divided by 46. */
802 kCLOCK_MiscDivBy47 = 46, /*!< Misc divider like LPI2C set to divided by 47. */
803 kCLOCK_MiscDivBy48 = 47, /*!< Misc divider like LPI2C set to divided by 48. */
804 kCLOCK_MiscDivBy49 = 48, /*!< Misc divider like LPI2C set to divided by 49. */
805 kCLOCK_MiscDivBy50 = 49, /*!< Misc divider like LPI2C set to divided by 50. */
806 kCLOCK_MiscDivBy51 = 50, /*!< Misc divider like LPI2C set to divided by 51. */
807 kCLOCK_MiscDivBy52 = 51, /*!< Misc divider like LPI2C set to divided by 52. */
808 kCLOCK_MiscDivBy53 = 52, /*!< Misc divider like LPI2C set to divided by 53. */
809 kCLOCK_MiscDivBy54 = 53, /*!< Misc divider like LPI2C set to divided by 54. */
810 kCLOCK_MiscDivBy55 = 54, /*!< Misc divider like LPI2C set to divided by 55. */
811 kCLOCK_MiscDivBy56 = 55, /*!< Misc divider like LPI2C set to divided by 56. */
812 kCLOCK_MiscDivBy57 = 56, /*!< Misc divider like LPI2C set to divided by 57. */
813 kCLOCK_MiscDivBy58 = 57, /*!< Misc divider like LPI2C set to divided by 58. */
814 kCLOCK_MiscDivBy59 = 58, /*!< Misc divider like LPI2C set to divided by 59. */
815 kCLOCK_MiscDivBy60 = 59, /*!< Misc divider like LPI2C set to divided by 60. */
816 kCLOCK_MiscDivBy61 = 60, /*!< Misc divider like LPI2C set to divided by 61. */
817 kCLOCK_MiscDivBy62 = 61, /*!< Misc divider like LPI2C set to divided by 62. */
818 kCLOCK_MiscDivBy63 = 62, /*!< Misc divider like LPI2C set to divided by 63. */
819 kCLOCK_MiscDivBy64 = 63, /*!< Misc divider like LPI2C set to divided by 64. */
820 } clock_div_value_t;
821
822 /*! @brief USB clock source definition. */
823 typedef enum _clock_usb_src
824 {
825 kCLOCK_Usb480M = 0, /*!< Use 480M. */
826 kCLOCK_UsbSrcUnused = (int)0xFFFFFFFFU, /*!< Used when the function does not
827 care the clock source. */
828 } clock_usb_src_t;
829
830 /*! @brief Source of the USB HS PHY. */
831 typedef enum _clock_usb_phy_src
832 {
833 kCLOCK_Usbphy480M = 0, /*!< Use 480M. */
834 } clock_usb_phy_src_t;
835
836 /*!@brief PLL clock source, bypass cloco source also */
837 enum _clock_pll_clk_src
838 {
839 kCLOCK_PllClkSrc24M = 0U, /*!< Pll clock source 24M */
840 kCLOCK_PllSrcClkPN = 1U, /*!< Pll clock source CLK1_P and CLK1_N */
841 };
842
843 /*! @brief PLL configuration for USB */
844 typedef struct _clock_usb_pll_config
845 {
846 uint8_t loopDivider; /*!< PLL loop divider.
847 0 - Fout=Fref*20;
848 1 - Fout=Fref*22 */
849 uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */
850
851 } clock_usb_pll_config_t;
852
853 /*! @brief PLL configuration for System */
854 typedef struct _clock_sys_pll_config
855 {
856 uint8_t loopDivider; /*!< PLL loop divider. Intended to be 1 (528M).
857 0 - Fout=Fref*20;
858 1 - Fout=Fref*22 */
859 uint32_t numerator; /*!< 30 bit numerator of fractional loop divider.*/
860 uint32_t denominator; /*!< 30 bit denominator of fractional loop divider */
861 uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */
862 uint16_t ss_stop; /*!< Stop value to get frequency change. */
863 uint8_t ss_enable; /*!< Enable spread spectrum modulation */
864 uint16_t ss_step; /*!< Step value to get frequency change step. */
865
866 } clock_sys_pll_config_t;
867
868 /*! @brief PLL configuration for AUDIO and VIDEO */
869 typedef struct _clock_audio_pll_config
870 {
871 uint8_t loopDivider; /*!< PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. */
872 uint8_t postDivider; /*!< Divider after the PLL, should only be 1, 2, 4, 8, 16. */
873 uint32_t numerator; /*!< 30 bit numerator of fractional loop divider.*/
874 uint32_t denominator; /*!< 30 bit denominator of fractional loop divider */
875 uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */
876 } clock_audio_pll_config_t;
877
878 /*! @brief PLL configuration for ENET */
879 typedef struct _clock_enet_pll_config
880 {
881 bool enableClkOutput; /*!< Power on and enable PLL clock output for ENET0 (ref_enetpll0). */
882
883 bool enableClkOutput500M; /*!< Power on and enable PLL clock output for ENET (ref_enetpll500M). */
884
885 bool enableClkOutput25M; /*!< Power on and enable PLL clock output for ENET1 (ref_enetpll1). */
886 uint8_t loopDivider; /*!< Controls the frequency of the ENET0 reference clock.
887 b00 25MHz
888 b01 50MHz
889 b10 100MHz (not 50% duty cycle)
890 b11 125MHz */
891 uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */
892
893 } clock_enet_pll_config_t;
894
895 /*! @brief PLL name */
896 typedef enum _clock_pll
897 {
898 kCLOCK_PllSys = CCM_ANALOG_TUPLE(PLL_SYS_OFFSET, CCM_ANALOG_PLL_SYS_ENABLE_SHIFT), /*!< PLL SYS */
899 kCLOCK_PllUsb1 = CCM_ANALOG_TUPLE(PLL_USB1_OFFSET, CCM_ANALOG_PLL_USB1_ENABLE_SHIFT), /*!< PLL USB1 */
900 kCLOCK_PllAudio = CCM_ANALOG_TUPLE(PLL_AUDIO_OFFSET, CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT), /*!< PLL Audio */
901 kCLOCK_PllEnet500M = CCM_ANALOG_TUPLE(PLL_ENET_OFFSET, CCM_ANALOG_PLL_ENET_ENET_500M_REF_EN_SHIFT), /*!< PLL ENET */
902 } clock_pll_t;
903
904 /*! @brief PLL PFD name */
905 typedef enum _clock_pfd
906 {
907 kCLOCK_Pfd0 = 0U, /*!< PLL PFD0 */
908 kCLOCK_Pfd1 = 1U, /*!< PLL PFD1 */
909 kCLOCK_Pfd2 = 2U, /*!< PLL PFD2 */
910 kCLOCK_Pfd3 = 3U, /*!< PLL PFD3 */
911 } clock_pfd_t;
912
913 /*!
914 * @brief The enumerater of clock output1's clock source, such as USB1 PLL, SYS PLL and so on.
915 */
916 typedef enum _clock_output1_selection
917 {
918 kCLOCK_OutputPllUsb1Sw = 0U, /*!< Selects USB1 PLL SW clock(Divided by 2) output. */
919 kCLOCK_OutputPllSys = 1U, /*!< Selects SYS PLL clock(Divided by 2) output. */
920 kCLOCK_OutputPllENET = 2U, /*!< Selects ENET PLL clock(Divided by 2) output. */
921 kCLOCK_OutputCoreClk = 0xBU, /*!< Selects Core clock root output. */
922 kCLOCK_OutputIpgClk = 0xCU, /*!< Selects IPG clock root output. */
923 kCLOCK_OutputPerClk = 0xDU, /*!< Selects PERCLK clock root output. */
924 kCLOCK_OutputPll4MainClk = 0xFU, /*!< Selects PLL4 main clock output. */
925 kCLOCK_DisableClockOutput1 = 0x10U, /*!< Disables CLKO1. */
926 } clock_output1_selection_t;
927
928 /*!
929 * @brief The enumerater of clock output2's clock source, such as USDHC1 clock root, LPI2C clock root and so on.
930 *
931 */
932 typedef enum _clock_output2_selection
933 {
934 kCLOCK_OutputLpi2cClk = 6U, /*!< Selects LPI2C clock root output. */
935 kCLOCK_OutputOscClk = 0xEU, /*!< Selects OSC output. */
936 kCLOCK_OutputLpspiClk = 0x10U, /*!< Selects LPSPI clock root output. */
937 kCLOCK_OutputSai1Clk = 0x12U, /*!< Selects SAI1 clock root output. */
938 kCLOCK_OutputSai3Clk = 0x14U, /*!< Selects SAI3 clock root output. */
939 kCLOCK_OutputTraceClk = 0x16U, /*!< Selects Trace clock root output. */
940 kCLOCK_OutputFlexspiClk = 0x1BU, /*!< Selects FLEXSPI clock root output. */
941 kCLOCK_OutputUartClk = 0x1CU, /*!< Selects UART clock root output. */
942 kCLOCK_OutputSpdif0Clk = 0x1DU, /*!< Selects SPDIF0 clock root output. */
943 kCLOCK_DisableClockOutput2 = 0x1FU, /*!< Disables CLKO2. */
944 } clock_output2_selection_t;
945
946 /*!
947 * @brief The enumerator of clock output's divider.
948 */
949 typedef enum _clock_output_divider
950 {
951 kCLOCK_DivideBy1 = 0U, /*!< Output clock divided by 1. */
952 kCLOCK_DivideBy2, /*!< Output clock divided by 2. */
953 kCLOCK_DivideBy3, /*!< Output clock divided by 3. */
954 kCLOCK_DivideBy4, /*!< Output clock divided by 4. */
955 kCLOCK_DivideBy5, /*!< Output clock divided by 5. */
956 kCLOCK_DivideBy6, /*!< Output clock divided by 6. */
957 kCLOCK_DivideBy7, /*!< Output clock divided by 7. */
958 kCLOCK_DivideBy8, /*!< Output clock divided by 8. */
959 } clock_output_divider_t;
960
961 /*!
962 * @brief The enumerator of clock root.
963 */
964 typedef enum _clock_root
965 {
966 kCLOCK_FlexspiClkRoot = 0U, /*!< FLEXSPI clock root. */
967 kCLOCK_LpspiClkRoot, /*!< LPSPI clock root. */
968 kCLOCK_TraceClkRoot, /*!< Trace clock root. */
969 kCLOCK_Sai1ClkRoot, /*!< SAI1 clock root. */
970 kCLOCK_Sai3ClkRoot, /*!< SAI3 clock root. */
971 kCLOCK_Lpi2cClkRoot, /*!< LPI2C clock root. */
972 kCLOCK_UartClkRoot, /*!< UART clock root. */
973 kCLOCK_SpdifClkRoot, /*!< SPDIF clock root. */
974 kCLOCK_Flexio1ClkRoot, /*!< FLEXIO1 clock root. */
975 } clock_root_t;
976
977 /*******************************************************************************
978 * API
979 ******************************************************************************/
980
981 #if defined(__cplusplus)
982 extern "C" {
983 #endif /* __cplusplus */
984
985 /*!
986 * @brief Set CCM MUX node to certain value.
987 *
988 * @param mux Which mux node to set, see \ref clock_mux_t.
989 * @param value Clock mux value to set, different mux has different value range.
990 */
CLOCK_SetMux(clock_mux_t mux,uint32_t value)991 static inline void CLOCK_SetMux(clock_mux_t mux, uint32_t value)
992 {
993 uint32_t busyShift;
994
995 busyShift = CCM_TUPLE_BUSY_SHIFT(mux);
996 CCM_TUPLE_REG(CCM, mux) = (CCM_TUPLE_REG(CCM, mux) & (~CCM_TUPLE_MASK(mux))) |
997 (((uint32_t)((value) << CCM_TUPLE_SHIFT(mux))) & CCM_TUPLE_MASK(mux));
998
999 assert(busyShift <= CCM_NO_BUSY_WAIT);
1000
1001 /* Clock switch need Handshake? */
1002 if (CCM_NO_BUSY_WAIT != busyShift)
1003 {
1004 /* Wait until CCM internal handshake finish. */
1005 while ((CCM->CDHIPR & (1UL << busyShift)) != 0UL)
1006 {
1007 }
1008 }
1009 }
1010
1011 /*!
1012 * @brief Get CCM MUX value.
1013 *
1014 * @param mux Which mux node to get, see \ref clock_mux_t.
1015 * @return Clock mux value.
1016 */
CLOCK_GetMux(clock_mux_t mux)1017 static inline uint32_t CLOCK_GetMux(clock_mux_t mux)
1018 {
1019 return (CCM_TUPLE_REG(CCM, mux) & CCM_TUPLE_MASK(mux)) >> CCM_TUPLE_SHIFT(mux);
1020 }
1021
1022 /*!
1023 * @brief Set clock divider value.
1024 *
1025 * Example, set the ARM clock divider to divide by 2:
1026 * @code
1027 CLOCK_SetDiv(kCLOCK_ArmDiv, kCLOCK_ArmDivBy2);
1028 @endcode
1029 *
1030 * Example, set the LPI2C clock divider to divide by 5.
1031 * @code
1032 CLOCK_SetDiv(kCLOCK_Lpi2cDiv, kCLOCK_MiscDivBy5);
1033 @endcode
1034 *
1035 * Only @ref kCLOCK_PerclkDiv, @ref kCLOCK_UartDiv, @ref kCLOCK_Sai3Div, @ref kCLOCK_Sai1Div,
1036 * @ref kCLOCK_Lpi2cDiv can use the divider kCLOCK_MiscDivByxxx.
1037 *
1038 * @param divider Which divider node to set.
1039 * @param value Clock div value to set, different divider has different value range. See @ref clock_div_value_t
1040 * for details.
1041 * Divided clock frequency = Undivided clock frequency / (value + 1)
1042 */
CLOCK_SetDiv(clock_div_t divider,uint32_t value)1043 static inline void CLOCK_SetDiv(clock_div_t divider, uint32_t value)
1044 {
1045 uint32_t busyShift;
1046
1047 busyShift = CCM_TUPLE_BUSY_SHIFT((uint32_t)divider);
1048 CCM_TUPLE_REG(CCM, divider) = (CCM_TUPLE_REG(CCM, divider) & (~CCM_TUPLE_MASK(divider))) |
1049 (((uint32_t)((value) << CCM_TUPLE_SHIFT(divider))) & CCM_TUPLE_MASK(divider));
1050
1051 assert(busyShift <= CCM_NO_BUSY_WAIT);
1052
1053 /* Clock switch need Handshake? */
1054 if (CCM_NO_BUSY_WAIT != busyShift)
1055 {
1056 /* Wait until CCM internal handshake finish. */
1057 while ((CCM->CDHIPR & (1UL << busyShift)) != 0UL)
1058 {
1059 }
1060 }
1061 }
1062
1063 /*!
1064 * @brief Get CCM DIV node value.
1065 *
1066 * @param divider Which div node to get, see \ref clock_div_t.
1067 */
CLOCK_GetDiv(clock_div_t divider)1068 static inline uint32_t CLOCK_GetDiv(clock_div_t divider)
1069 {
1070 return ((CCM_TUPLE_REG(CCM, divider) & CCM_TUPLE_MASK(divider)) >> CCM_TUPLE_SHIFT(divider));
1071 }
1072
1073 /*!
1074 * @brief Control the clock gate for specific IP.
1075 *
1076 * @param name Which clock to enable, see \ref clock_ip_name_t.
1077 * @param value Clock gate value to set, see \ref clock_gate_value_t.
1078 */
CLOCK_ControlGate(clock_ip_name_t name,clock_gate_value_t value)1079 static inline void CLOCK_ControlGate(clock_ip_name_t name, clock_gate_value_t value)
1080 {
1081 uint32_t index = ((uint32_t)name) >> 8U;
1082 uint32_t shift = ((uint32_t)name) & 0x1FU;
1083 volatile uint32_t *reg;
1084
1085 assert(index <= 6UL);
1086
1087 reg = (volatile uint32_t *)(&(((volatile uint32_t *)&CCM->CCGR0)[index]));
1088 SDK_ATOMIC_LOCAL_CLEAR_AND_SET(reg, (3UL << shift), (((uint32_t)value) << shift));
1089 }
1090
1091 /*!
1092 * @brief Enable the clock for specific IP.
1093 *
1094 * @param name Which clock to enable, see \ref clock_ip_name_t.
1095 */
CLOCK_EnableClock(clock_ip_name_t name)1096 static inline void CLOCK_EnableClock(clock_ip_name_t name)
1097 {
1098 CLOCK_ControlGate(name, kCLOCK_ClockNeededRunWait);
1099 }
1100
1101 /*!
1102 * @brief Disable the clock for specific IP.
1103 *
1104 * @param name Which clock to disable, see \ref clock_ip_name_t.
1105 */
CLOCK_DisableClock(clock_ip_name_t name)1106 static inline void CLOCK_DisableClock(clock_ip_name_t name)
1107 {
1108 CLOCK_ControlGate(name, kCLOCK_ClockNotNeeded);
1109 }
1110
1111 /*!
1112 * @brief Setting the low power mode that system will enter on next assertion of dsm_request signal.
1113 *
1114 * @param mode Which mode to enter, see \ref clock_mode_t.
1115 */
CLOCK_SetMode(clock_mode_t mode)1116 static inline void CLOCK_SetMode(clock_mode_t mode)
1117 {
1118 CCM->CLPCR = (CCM->CLPCR & ~CCM_CLPCR_LPM_MASK) | CCM_CLPCR_LPM((uint32_t)mode);
1119 }
1120
1121 /*!
1122 * @brief Gets the OSC clock frequency.
1123 *
1124 * This function will return the external XTAL OSC frequency if it is selected as the source of OSC,
1125 * otherwise internal 24MHz RC OSC frequency will be returned.
1126 *
1127 * @return Clock frequency; If the clock is invalid, returns 0.
1128 */
CLOCK_GetOscFreq(void)1129 static inline uint32_t CLOCK_GetOscFreq(void)
1130 {
1131 return ((XTALOSC24M->LOWPWR_CTRL & (uint32_t)XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK) != 0UL) ? 24000000UL : g_xtalFreq;
1132 }
1133
1134 /*!
1135 * @brief Gets the CORE clock frequency.
1136 *
1137 * @return The CORE clock frequency value in hertz.
1138 */
1139 uint32_t CLOCK_GetCoreFreq(void);
1140
1141 /*!
1142 * @brief Gets the IPG clock frequency.
1143 *
1144 * @return The IPG clock frequency value in hertz.
1145 */
1146 uint32_t CLOCK_GetIpgFreq(void);
1147
1148 /*!
1149 * @brief Gets the PER clock frequency.
1150 *
1151 * @return The PER clock frequency value in hertz.
1152 */
1153 uint32_t CLOCK_GetPerClkFreq(void);
1154
1155 /*!
1156 * @brief Gets the clock frequency for a specific clock name.
1157 *
1158 * This function checks the current clock configurations and then calculates
1159 * the clock frequency for a specific clock name defined in clock_name_t.
1160 *
1161 * @param name Clock names defined in clock_name_t
1162 * @return Clock frequency value in hertz
1163 */
1164 uint32_t CLOCK_GetFreq(clock_name_t name);
1165
1166 /*!
1167 * @brief Get the CCM CPU/core/system frequency.
1168 *
1169 * @return Clock frequency; If the clock is invalid, returns 0.
1170 */
CLOCK_GetCpuClkFreq(void)1171 static inline uint32_t CLOCK_GetCpuClkFreq(void)
1172 {
1173 return CLOCK_GetFreq(kCLOCK_CpuClk);
1174 }
1175
1176 /*!
1177 * @brief Gets the frequency of selected clock root.
1178 *
1179 * @param clockRoot The clock root used to get the frequency, please refer to @ref clock_root_t.
1180 * @return The frequency of selected clock root.
1181 */
1182 uint32_t CLOCK_GetClockRootFreq(clock_root_t clockRoot);
1183
1184 /*!
1185 * @name OSC operations
1186 * @{
1187 */
1188
1189 /*!
1190 * @brief Initialize the external 24MHz clock.
1191 *
1192 * This function supports two modes:
1193 * 1. Use external crystal oscillator.
1194 * 2. Bypass the external crystal oscillator, using input source clock directly.
1195 *
1196 * After this function, please call CLOCK_SetXtal0Freq to inform clock driver
1197 * the external clock frequency.
1198 *
1199 * @param bypassXtalOsc Pass in true to bypass the external crystal oscillator.
1200 * @note This device does not support bypass external crystal oscillator, so
1201 * the input parameter should always be false.
1202 */
1203 void CLOCK_InitExternalClk(bool bypassXtalOsc);
1204
1205 /*!
1206 * @brief Deinitialize the external 24MHz clock.
1207 *
1208 * This function disables the external 24MHz clock.
1209 *
1210 * After this function, please call CLOCK_SetXtal0Freq to set external clock
1211 * frequency to 0.
1212 */
1213 void CLOCK_DeinitExternalClk(void);
1214
1215 /*!
1216 * @brief Switch the OSC.
1217 *
1218 * This function switches the OSC source for SoC.
1219 *
1220 * @param osc OSC source to switch to.
1221 */
1222 void CLOCK_SwitchOsc(clock_osc_t osc);
1223
1224 /*!
1225 * @brief Gets the RTC clock frequency.
1226 *
1227 * @return Clock frequency; If the clock is invalid, returns 0.
1228 */
CLOCK_GetRtcFreq(void)1229 static inline uint32_t CLOCK_GetRtcFreq(void)
1230 {
1231 return 32768U;
1232 }
1233
1234 /*!
1235 * @brief Set the XTAL (24M OSC) frequency based on board setting.
1236 *
1237 * @param freq The XTAL input clock frequency in Hz.
1238 */
CLOCK_SetXtalFreq(uint32_t freq)1239 static inline void CLOCK_SetXtalFreq(uint32_t freq)
1240 {
1241 g_xtalFreq = freq;
1242 }
1243
1244 /*!
1245 * @brief Set the RTC XTAL (32K OSC) frequency based on board setting.
1246 *
1247 * @param freq The RTC XTAL input clock frequency in Hz.
1248 */
CLOCK_SetRtcXtalFreq(uint32_t freq)1249 static inline void CLOCK_SetRtcXtalFreq(uint32_t freq)
1250 {
1251 g_rtcXtalFreq = freq;
1252 }
1253
1254 /*!
1255 * @brief Initialize the RC oscillator 24MHz clock.
1256 */
1257 void CLOCK_InitRcOsc24M(void);
1258
1259 /*!
1260 * @brief Power down the RCOSC 24M clock.
1261 */
1262 void CLOCK_DeinitRcOsc24M(void);
1263 /* @} */
1264
1265 /*! @brief Enable USB HS clock.
1266 *
1267 * This function only enables the access to USB HS prepheral, upper layer
1268 * should first call the CLOCK_EnableUsbhs0PhyPllClock to enable the PHY
1269 * clock to use USB HS.
1270 *
1271 * @param src USB HS does not care about the clock source, here must be @ref kCLOCK_UsbSrcUnused.
1272 * @param freq USB HS does not care about the clock source, so this parameter is ignored.
1273 * @retval true The clock is set successfully.
1274 * @retval false The clock source is invalid to get proper USB HS clock.
1275 */
1276 bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq);
1277
1278 /* @} */
1279
1280 /*!
1281 * @name PLL/PFD operations
1282 * @{
1283 */
1284 /*!
1285 * @brief PLL bypass setting
1286 *
1287 * @param base CCM_ANALOG base pointer.
1288 * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration)
1289 * @param bypass Bypass the PLL.
1290 * - true: Bypass the PLL.
1291 * - false:Not bypass the PLL.
1292 */
CLOCK_SetPllBypass(CCM_ANALOG_Type * base,clock_pll_t pll,bool bypass)1293 static inline void CLOCK_SetPllBypass(CCM_ANALOG_Type *base, clock_pll_t pll, bool bypass)
1294 {
1295 if (bypass)
1296 {
1297 CCM_ANALOG_TUPLE_REG_OFF(base, pll, 4U) = 1UL << CCM_ANALOG_PLL_BYPASS_SHIFT;
1298 }
1299 else
1300 {
1301 CCM_ANALOG_TUPLE_REG_OFF(base, pll, 8U) = 1UL << CCM_ANALOG_PLL_BYPASS_SHIFT;
1302 }
1303 }
1304
1305 /*!
1306 * @brief Check if PLL is bypassed
1307 *
1308 * @param base CCM_ANALOG base pointer.
1309 * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration)
1310 * @return PLL bypass status.
1311 * - true: The PLL is bypassed.
1312 * - false: The PLL is not bypassed.
1313 */
CLOCK_IsPllBypassed(CCM_ANALOG_Type * base,clock_pll_t pll)1314 static inline bool CLOCK_IsPllBypassed(CCM_ANALOG_Type *base, clock_pll_t pll)
1315 {
1316 return (bool)(CCM_ANALOG_TUPLE_REG(base, pll) & (1UL << CCM_ANALOG_PLL_BYPASS_SHIFT));
1317 }
1318
1319 /*!
1320 * @brief Check if PLL is enabled
1321 *
1322 * @param base CCM_ANALOG base pointer.
1323 * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration)
1324 * @return PLL bypass status.
1325 * - true: The PLL is enabled.
1326 * - false: The PLL is not enabled.
1327 */
CLOCK_IsPllEnabled(CCM_ANALOG_Type * base,clock_pll_t pll)1328 static inline bool CLOCK_IsPllEnabled(CCM_ANALOG_Type *base, clock_pll_t pll)
1329 {
1330 return (bool)(CCM_ANALOG_TUPLE_REG(base, pll) & (1UL << CCM_ANALOG_TUPLE_SHIFT(pll)));
1331 }
1332
1333 /*!
1334 * @brief PLL bypass clock source setting.
1335 * Note: change the bypass clock source also change the pll reference clock source.
1336 *
1337 * @param base CCM_ANALOG base pointer.
1338 * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration)
1339 * @param src Bypass clock source, reference _clock_pll_bypass_clk_src.
1340 */
CLOCK_SetPllBypassRefClkSrc(CCM_ANALOG_Type * base,clock_pll_t pll,uint32_t src)1341 static inline void CLOCK_SetPllBypassRefClkSrc(CCM_ANALOG_Type *base, clock_pll_t pll, uint32_t src)
1342 {
1343 CCM_ANALOG_TUPLE_REG(base, pll) |= (CCM_ANALOG_TUPLE_REG(base, pll) & (~CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK)) | src;
1344 }
1345
1346 /*!
1347 * @brief Get PLL bypass clock value, it is PLL reference clock actually.
1348 * If CLOCK1_P,CLOCK1_N is choose as the pll bypass clock source, please implement the CLKPN_FREQ define, otherwise 0
1349 * will be returned.
1350 * @param base CCM_ANALOG base pointer.
1351 * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration)
1352 * @retval bypass reference clock frequency value.
1353 */
CLOCK_GetPllBypassRefClk(CCM_ANALOG_Type * base,clock_pll_t pll)1354 static inline uint32_t CLOCK_GetPllBypassRefClk(CCM_ANALOG_Type *base, clock_pll_t pll)
1355 {
1356 return ((((uint32_t)(CCM_ANALOG_TUPLE_REG(base, pll) & CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK)) >>
1357 CCM_ANALOG_PLL_BYPASS_CLK_SRC_SHIFT) == (uint32_t)kCLOCK_PllClkSrc24M) ?
1358 CLOCK_GetOscFreq() :
1359 CLKPN_FREQ;
1360 }
1361
1362 /*!
1363 * @brief Initialize the System PLL.
1364 *
1365 * This function initializes the System PLL with specific settings
1366 *
1367 * @param config Configuration to set to PLL.
1368 */
1369 void CLOCK_InitSysPll(const clock_sys_pll_config_t *config);
1370
1371 /*!
1372 * @brief De-initialize the System PLL.
1373 */
1374 void CLOCK_DeinitSysPll(void);
1375
1376 /*!
1377 * @brief Initialize the USB1 PLL.
1378 *
1379 * This function initializes the USB1 PLL with specific settings
1380 *
1381 * @param config Configuration to set to PLL.
1382 */
1383 void CLOCK_InitUsb1Pll(const clock_usb_pll_config_t *config);
1384
1385 /*!
1386 * @brief Deinitialize the USB1 PLL.
1387 */
1388 void CLOCK_DeinitUsb1Pll(void);
1389
1390 /*!
1391 * @brief Initializes the Audio PLL.
1392 *
1393 * This function initializes the Audio PLL with specific settings
1394 *
1395 * @param config Configuration to set to PLL.
1396 */
1397 void CLOCK_InitAudioPll(const clock_audio_pll_config_t *config);
1398
1399 /*!
1400 * @brief De-initialize the Audio PLL.
1401 */
1402 void CLOCK_DeinitAudioPll(void);
1403
1404 /*!
1405 * @brief Initialize the ENET PLL.
1406 *
1407 * This function initializes the ENET PLL with specific settings.
1408 *
1409 * @param config Configuration to set to PLL.
1410 */
1411 void CLOCK_InitEnetPll(const clock_enet_pll_config_t *config);
1412
1413 /*!
1414 * @brief Deinitialize the ENET PLL.
1415 *
1416 * This function disables the ENET PLL.
1417 */
1418 void CLOCK_DeinitEnetPll(void);
1419
1420 /*!
1421 * @brief Get current PLL output frequency.
1422 *
1423 * This function get current output frequency of specific PLL
1424 *
1425 * @param pll pll name to get frequency.
1426 * @return The PLL output frequency in hertz.
1427 */
1428 uint32_t CLOCK_GetPllFreq(clock_pll_t pll);
1429
1430 /*!
1431 * @brief Initialize the System PLL PFD.
1432 *
1433 * This function initializes the System PLL PFD. During new value setting,
1434 * the clock output is disabled to prevent glitch.
1435 *
1436 * @param pfd Which PFD clock to enable.
1437 * @param pfdFrac The PFD FRAC value.
1438 * @note It is recommended that PFD settings are kept between 12-35.
1439 */
1440 void CLOCK_InitSysPfd(clock_pfd_t pfd, uint8_t pfdFrac);
1441
1442 /*!
1443 * @brief De-initialize the System PLL PFD.
1444 *
1445 * This function disables the System PLL PFD.
1446 *
1447 * @param pfd Which PFD clock to disable.
1448 */
1449 void CLOCK_DeinitSysPfd(clock_pfd_t pfd);
1450
1451 /*!
1452 * @brief Check if Sys PFD is enabled
1453 *
1454 * @param pfd PFD control name
1455 * @return PFD bypass status.
1456 * - true: power on.
1457 * - false: power off.
1458 */
1459 bool CLOCK_IsSysPfdEnabled(clock_pfd_t pfd);
1460
1461 /*!
1462 * @brief Initialize the USB1 PLL PFD.
1463 *
1464 * This function initializes the USB1 PLL PFD. During new value setting,
1465 * the clock output is disabled to prevent glitch.
1466 *
1467 * @param pfd Which PFD clock to enable.
1468 * @param pfdFrac The PFD FRAC value.
1469 * @note It is recommended that PFD settings are kept between 12-35.
1470 */
1471 void CLOCK_InitUsb1Pfd(clock_pfd_t pfd, uint8_t pfdFrac);
1472
1473 /*!
1474 * @brief De-initialize the USB1 PLL PFD.
1475 *
1476 * This function disables the USB1 PLL PFD.
1477 *
1478 * @param pfd Which PFD clock to disable.
1479 */
1480 void CLOCK_DeinitUsb1Pfd(clock_pfd_t pfd);
1481
1482 /*!
1483 * @brief Check if Usb1 PFD is enabled
1484 *
1485 * @param pfd PFD control name.
1486 * @return PFD bypass status.
1487 * - true: power on.
1488 * - false: power off.
1489 */
1490 bool CLOCK_IsUsb1PfdEnabled(clock_pfd_t pfd);
1491
1492 /*!
1493 * @brief Get current System PLL PFD output frequency.
1494 *
1495 * This function get current output frequency of specific System PLL PFD
1496 *
1497 * @param pfd pfd name to get frequency.
1498 * @return The PFD output frequency in hertz.
1499 */
1500 uint32_t CLOCK_GetSysPfdFreq(clock_pfd_t pfd);
1501
1502 /*!
1503 * @brief Get current USB1 PLL PFD output frequency.
1504 *
1505 * This function get current output frequency of specific USB1 PLL PFD
1506 *
1507 * @param pfd pfd name to get frequency.
1508 * @return The PFD output frequency in hertz.
1509 */
1510 uint32_t CLOCK_GetUsb1PfdFreq(clock_pfd_t pfd);
1511
1512 /*! @brief Enable USB HS PHY PLL clock.
1513 *
1514 * This function enables the internal 480MHz USB PHY PLL clock.
1515 *
1516 * @param src USB HS PHY PLL clock source.
1517 * @param freq The frequency specified by src.
1518 * @retval true The clock is set successfully.
1519 * @retval false The clock source is invalid to get proper USB HS clock.
1520 */
1521 bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq);
1522
1523 /*! @brief Disable USB HS PHY PLL clock.
1524 *
1525 * This function disables USB HS PHY PLL clock.
1526 */
1527 void CLOCK_DisableUsbhs0PhyPllClock(void);
1528
1529 /* @} */
1530
1531 /*!
1532 * @name Clock Output Inferfaces
1533 * @{
1534 */
1535
1536 /*!
1537 * @brief Set the clock source and the divider of the clock output1.
1538 *
1539 * @param selection The clock source to be output, please refer to @ref clock_output1_selection_t.
1540 * @param divider The divider of the output clock signal, please refer to @ref clock_output_divider_t.
1541 */
1542 void CLOCK_SetClockOutput1(clock_output1_selection_t selection, clock_output_divider_t divider);
1543
1544 /*!
1545 * @brief Set the clock source and the divider of the clock output2.
1546 *
1547 * @param selection The clock source to be output, please refer to @ref clock_output2_selection_t.
1548 * @param divider The divider of the output clock signal, please refer to @ref clock_output_divider_t.
1549 */
1550 void CLOCK_SetClockOutput2(clock_output2_selection_t selection, clock_output_divider_t divider);
1551
1552 /*!
1553 * @brief Get the frequency of clock output1 clock signal.
1554 *
1555 * @return The frequency of clock output1 clock signal.
1556 */
1557 uint32_t CLOCK_GetClockOutCLKO1Freq(void);
1558
1559 /*!
1560 * @brief Get the frequency of clock output2 clock signal.
1561 *
1562 * @return The frequency of clock output2 clock signal.
1563 */
1564 uint32_t CLOCK_GetClockOutClkO2Freq(void);
1565
1566 /*! @} */
1567
1568 #if defined(__cplusplus)
1569 }
1570 #endif /* __cplusplus */
1571
1572 /*! @} */
1573
1574 #endif /* _FSL_CLOCK_H_ */
1575
