| /hal_nxp-latest/mcux/mcux-sdk/drivers/mailbox/ |
| D | fsl_mailbox.h | 150 base->MBOXIRQ[cpu_id].IRQ = mboxData; in MAILBOX_SetValue()
174 return base->MBOXIRQ[cpu_id].IRQ; in MAILBOX_GetValue()
242 base->MBOXIRQ[id].IRQ = mboxData; in MAILBOX_SetValue()
256 return base->MBOXIRQ[id].IRQ; in MAILBOX_GetValue()
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/irq/ |
| D | Kconfig | 12 bool "IRQ Driver"
15 IRQ Driver
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| D | driver_irq.cmake | 1 #Description: IRQ Driver; user_visible: True
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/epdc/ |
| D | fsl_epdc.h | 543 return (uint16_t)((base->IRQ.RW >> 12U) | (base->STATUS.RW & 0xFU)); in EPDC_GetStatusFlags()
554 base->IRQ.CLR = ((uint32_t)statusFlags << 12U); in EPDC_ClearStatusFlags()
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/pxp/ |
| D | fsl_pxp.h | 1300 status |= (base->IRQ >> 16U | base->IRQ << 16U); in PXP_GetStatusFlags()
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MKE02Z4/ |
| D | all_lib_device.cmake | 160 # # description: IRQ Driver
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| D | MKE02Z4.h | 3409 #define IRQ ((IRQ_Type *)IRQ_BASE) macro
3413 #define IRQ_BASE_PTRS { IRQ }
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| /hal_nxp-latest/s32/drivers/s32ze/BaseNXP/header/ |
| D | S32Z2_PSI5_S.h | 112 } IRQ[PSI5_S_IRQ_COUNT]; member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MKE04Z4/ |
| D | MKE04Z4.h | 3337 #define IRQ ((IRQ_Type *)IRQ_BASE) macro
3341 #define IRQ_BASE_PTRS { IRQ }
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| /hal_nxp-latest/mcux/mcux-sdk/components/power_manager/ |
| D | README.md | 371 …source callback if it has been registered. Likely to be called from Wake-Up Unit IRQ Handler.
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MKE04Z1284/ |
| D | MKE04Z1284.h | 3379 #define IRQ ((IRQ_Type *)IRQ_BASE) macro
3383 #define IRQ_BASE_PTRS { IRQ }
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MKE06Z4/ |
| D | MKE06Z4.h | 3379 #define IRQ ((IRQ_Type *)IRQ_BASE) macro
3383 #define IRQ_BASE_PTRS { IRQ }
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| /hal_nxp-latest/mcux/mcux-sdk/devices/LPC54114/ |
| D | LPC54114_cm0plus.h | 4769 …__IO uint32_t IRQ; /**< Interrupt request register for the Cortex-M0… member
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| D | LPC54114_cm4.h | 4780 …__IO uint32_t IRQ; /**< Interrupt request register for the Cortex-M0… member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/LPC54113/ |
| D | LPC54113.h | 4781 …__IO uint32_t IRQ; /**< Interrupt request register for the Cortex-M0… member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S66/ |
| D | LPC55S66_cm33_core1.h | 13266 …__IO uint32_t IRQ; /**< Interrupt request register for the Cortex-M0… member
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| D | LPC55S66_cm33_core0.h | 13266 …__IO uint32_t IRQ; /**< Interrupt request register for the Cortex-M0… member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S69/ |
| D | LPC55S69_cm33_core1.h | 13265 …__IO uint32_t IRQ; /**< Interrupt request register for the Cortex-M0… member
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| D | LPC55S69_cm33_core0.h | 13265 …__IO uint32_t IRQ; /**< Interrupt request register for the Cortex-M0… member
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| /hal_nxp-latest/imx/devices/MCIMX7D/ |
| D | MCIMX7D_M4.h | 14508 …__IO uint32_t IRQ; /**< EPDC Interrupt Register, offset: 0x420… member
14792 #define EPDC_IRQ_REG(base) ((base)->IRQ)
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/ |
| D | MCXN546_cm33_core0.h | 51819 …__IO uint32_t IRQ; /**< Cortex-M33 (CPU0) Interrupt..CoolFlux (CPU1)… member
|
| D | MCXN546_cm33_core1.h | 51819 …__IO uint32_t IRQ; /**< Cortex-M33 (CPU0) Interrupt..CoolFlux (CPU1)… member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/ |
| D | MCXN547_cm33_core0.h | 51819 …__IO uint32_t IRQ; /**< Cortex-M33 (CPU0) Interrupt..CoolFlux (CPU1)… member
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| D | MCXN547_cm33_core1.h | 51819 …__IO uint32_t IRQ; /**< Cortex-M33 (CPU0) Interrupt..CoolFlux (CPU1)… member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/ |
| D | MCXN947_cm33_core1.h | 52300 …__IO uint32_t IRQ; /**< Cortex-M33 (CPU0) Interrupt..CoolFlux (CPU1)… member
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