1 /* 2 ** ################################################################### 3 ** Processors: LPC54114J256BD64_cm4 4 ** LPC54114J256UK49_cm4 5 ** 6 ** Compilers: GNU C Compiler 7 ** IAR ANSI C/C++ Compiler for ARM 8 ** Keil ARM C/C++ Compiler 9 ** MCUXpresso Compiler 10 ** 11 ** Reference manual: LPC5411x User manual Rev. 1.1 25 May 2016 12 ** Version: rev. 1.0, 2016-04-29 13 ** Build: b200304 14 ** 15 ** Abstract: 16 ** CMSIS Peripheral Access Layer for LPC54114_cm4 17 ** 18 ** Copyright 1997-2016 Freescale Semiconductor, Inc. 19 ** Copyright 2016-2020 NXP 20 ** All rights reserved. 21 ** 22 ** SPDX-License-Identifier: BSD-3-Clause 23 ** 24 ** http: www.nxp.com 25 ** mail: support@nxp.com 26 ** 27 ** Revisions: 28 ** - rev. 1.0 (2016-04-29) 29 ** Initial version. 30 ** 31 ** ################################################################### 32 */ 33 34 /*! 35 * @file LPC54114_cm4.h 36 * @version 1.0 37 * @date 2016-04-29 38 * @brief CMSIS Peripheral Access Layer for LPC54114_cm4 39 * 40 * CMSIS Peripheral Access Layer for LPC54114_cm4 41 */ 42 43 #ifndef _LPC54114_CM4_H_ 44 #define _LPC54114_CM4_H_ /**< Symbol preventing repeated inclusion */ 45 46 /** Memory map major version (memory maps with equal major version number are 47 * compatible) */ 48 #define MCU_MEM_MAP_VERSION 0x0100U 49 /** Memory map minor version */ 50 #define MCU_MEM_MAP_VERSION_MINOR 0x0000U 51 52 53 /* ---------------------------------------------------------------------------- 54 -- Interrupt vector numbers 55 ---------------------------------------------------------------------------- */ 56 57 /*! 58 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers 59 * @{ 60 */ 61 62 /** Interrupt Number Definitions */ 63 #define NUMBER_OF_INT_VECTORS 56 /**< Number of interrupts in the Vector table */ 64 65 typedef enum IRQn { 66 /* Auxiliary constants */ 67 NotAvail_IRQn = -128, /**< Not available device specific interrupt */ 68 69 /* Core interrupts */ 70 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ 71 HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */ 72 MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */ 73 BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */ 74 UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */ 75 SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */ 76 DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */ 77 PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */ 78 SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */ 79 80 /* Device specific interrupts */ 81 WDT_BOD_IRQn = 0, /**< Windowed watchdog timer, Brownout detect */ 82 DMA0_IRQn = 1, /**< DMA controller */ 83 GINT0_IRQn = 2, /**< GPIO group 0 */ 84 GINT1_IRQn = 3, /**< GPIO group 1 */ 85 PIN_INT0_IRQn = 4, /**< Pin interrupt 0 or pattern match engine slice 0 */ 86 PIN_INT1_IRQn = 5, /**< Pin interrupt 1or pattern match engine slice 1 */ 87 PIN_INT2_IRQn = 6, /**< Pin interrupt 2 or pattern match engine slice 2 */ 88 PIN_INT3_IRQn = 7, /**< Pin interrupt 3 or pattern match engine slice 3 */ 89 UTICK0_IRQn = 8, /**< Micro-tick Timer */ 90 MRT0_IRQn = 9, /**< Multi-rate timer */ 91 CTIMER0_IRQn = 10, /**< Standard counter/timer CTIMER0 */ 92 CTIMER1_IRQn = 11, /**< Standard counter/timer CTIMER1 */ 93 SCT0_IRQn = 12, /**< SCTimer/PWM */ 94 CTIMER3_IRQn = 13, /**< Standard counter/timer CTIMER3 */ 95 FLEXCOMM0_IRQn = 14, /**< Flexcomm Interface 0 (USART, SPI, I2C) */ 96 FLEXCOMM1_IRQn = 15, /**< Flexcomm Interface 1 (USART, SPI, I2C) */ 97 FLEXCOMM2_IRQn = 16, /**< Flexcomm Interface 2 (USART, SPI, I2C) */ 98 FLEXCOMM3_IRQn = 17, /**< Flexcomm Interface 3 (USART, SPI, I2C) */ 99 FLEXCOMM4_IRQn = 18, /**< Flexcomm Interface 4 (USART, SPI, I2C) */ 100 FLEXCOMM5_IRQn = 19, /**< Flexcomm Interface 5 (USART, SPI, I2C) */ 101 FLEXCOMM6_IRQn = 20, /**< Flexcomm Interface 6 (USART, SPI, I2C, I2S) */ 102 FLEXCOMM7_IRQn = 21, /**< Flexcomm Interface 7 (USART, SPI, I2C, I2S) */ 103 ADC0_SEQA_IRQn = 22, /**< ADC0 sequence A completion. */ 104 ADC0_SEQB_IRQn = 23, /**< ADC0 sequence B completion. */ 105 ADC0_THCMP_IRQn = 24, /**< ADC0 threshold compare and error. */ 106 DMIC0_IRQn = 25, /**< Digital microphone and DMIC subsystem */ 107 HWVAD0_IRQn = 26, /**< Hardware Voice Activity Detector */ 108 USB0_NEEDCLK_IRQn = 27, /**< USB Activity Wake-up Interrupt */ 109 USB0_IRQn = 28, /**< USB device */ 110 RTC_IRQn = 29, /**< RTC alarm and wake-up interrupts */ 111 IOH_IRQn = 30, /**< IOH */ 112 MAILBOX_IRQn = 31, /**< Mailbox interrupt (present on selected devices) */ 113 PIN_INT4_IRQn = 32, /**< Pin interrupt 4 or pattern match engine slice 4 int */ 114 PIN_INT5_IRQn = 33, /**< Pin interrupt 5 or pattern match engine slice 5 int */ 115 PIN_INT6_IRQn = 34, /**< Pin interrupt 6 or pattern match engine slice 6 int */ 116 PIN_INT7_IRQn = 35, /**< Pin interrupt 7 or pattern match engine slice 7 int */ 117 CTIMER2_IRQn = 36, /**< Standard counter/timer CTIMER2 */ 118 CTIMER4_IRQn = 37, /**< Standard counter/timer CTIMER4 */ 119 Reserved54_IRQn = 38, /**< Reserved interrupt */ 120 SPIFI0_IRQn = 39 /**< SPI flash interface */ 121 } IRQn_Type; 122 123 /*! 124 * @} 125 */ /* end of group Interrupt_vector_numbers */ 126 127 128 /* ---------------------------------------------------------------------------- 129 -- Cortex M4 Core Configuration 130 ---------------------------------------------------------------------------- */ 131 132 /*! 133 * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration 134 * @{ 135 */ 136 137 #define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */ 138 #define __NVIC_PRIO_BITS 3 /**< Number of priority bits implemented in the NVIC */ 139 #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ 140 #define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ 141 142 #include "core_cm4.h" /* Core Peripheral Access Layer */ 143 #include "system_LPC54114_cm4.h" /* Device specific configuration file */ 144 145 /*! 146 * @} 147 */ /* end of group Cortex_Core_Configuration */ 148 149 150 /* ---------------------------------------------------------------------------- 151 -- Device Peripheral Access Layer 152 ---------------------------------------------------------------------------- */ 153 154 /*! 155 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer 156 * @{ 157 */ 158 159 160 /* 161 ** Start of section using anonymous unions 162 */ 163 164 #if defined(__ARMCC_VERSION) 165 #if (__ARMCC_VERSION >= 6010050) 166 #pragma clang diagnostic push 167 #else 168 #pragma push 169 #pragma anon_unions 170 #endif 171 #elif defined(__GNUC__) 172 /* anonymous unions are enabled by default */ 173 #elif defined(__IAR_SYSTEMS_ICC__) 174 #pragma language=extended 175 #else 176 #error Not supported compiler type 177 #endif 178 179 /* ---------------------------------------------------------------------------- 180 -- ADC Peripheral Access Layer 181 ---------------------------------------------------------------------------- */ 182 183 /*! 184 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer 185 * @{ 186 */ 187 188 /** ADC - Register Layout Typedef */ 189 typedef struct { 190 __IO uint32_t CTRL; /**< ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls., offset: 0x0 */ 191 __IO uint32_t INSEL; /**< Input Select. Allows selection of the temperature sensor as an alternate input to ADC channel 0., offset: 0x4 */ 192 __IO uint32_t SEQ_CTRL[2]; /**< ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n., array offset: 0x8, array step: 0x4 */ 193 __I uint32_t SEQ_GDAT[2]; /**< ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n., array offset: 0x10, array step: 0x4 */ 194 uint8_t RESERVED_0[8]; 195 __I uint32_t DAT[12]; /**< ADC Channel 0 Data register. This register contains the result of the most recent conversion completed on channel 0., array offset: 0x20, array step: 0x4 */ 196 __IO uint32_t THR0_LOW; /**< ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0., offset: 0x50 */ 197 __IO uint32_t THR1_LOW; /**< ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1., offset: 0x54 */ 198 __IO uint32_t THR0_HIGH; /**< ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0., offset: 0x58 */ 199 __IO uint32_t THR1_HIGH; /**< ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1., offset: 0x5C */ 200 __IO uint32_t CHAN_THRSEL; /**< ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel, offset: 0x60 */ 201 __IO uint32_t INTEN; /**< ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated., offset: 0x64 */ 202 __IO uint32_t FLAGS; /**< ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers)., offset: 0x68 */ 203 __IO uint32_t STARTUP; /**< ADC Startup register., offset: 0x6C */ 204 __IO uint32_t CALIB; /**< ADC Calibration register., offset: 0x70 */ 205 } ADC_Type; 206 207 /* ---------------------------------------------------------------------------- 208 -- ADC Register Masks 209 ---------------------------------------------------------------------------- */ 210 211 /*! 212 * @addtogroup ADC_Register_Masks ADC Register Masks 213 * @{ 214 */ 215 216 /*! @name CTRL - ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls. */ 217 /*! @{ */ 218 #define ADC_CTRL_CLKDIV_MASK (0xFFU) 219 #define ADC_CTRL_CLKDIV_SHIFT (0U) 220 /*! CLKDIV - In synchronous mode only, the system clock is divided by this value plus one to produce 221 * the clock for the ADC converter, which should be less than or equal to 72 MHz. Typically, 222 * software should program the smallest value in this field that yields this maximum clock rate or 223 * slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may 224 * be desirable. This field is ignored in the asynchronous operating mode. 225 */ 226 #define ADC_CTRL_CLKDIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CLKDIV_SHIFT)) & ADC_CTRL_CLKDIV_MASK) 227 #define ADC_CTRL_ASYNMODE_MASK (0x100U) 228 #define ADC_CTRL_ASYNMODE_SHIFT (8U) 229 /*! ASYNMODE - Select clock mode. 230 * 0b0..Synchronous mode. The ADC clock is derived from the system clock based on the divide value selected in 231 * the CLKDIV field. The ADC clock will be started in a controlled fashion in response to a trigger to 232 * eliminate any uncertainty in the launching of an ADC conversion in response to any synchronous (on-chip) trigger. 233 * In Synchronous mode with the SYNCBYPASS bit (in a sequence control register) set, sampling of the ADC 234 * input and start of conversion will initiate 2 system clocks after the leading edge of a (synchronous) trigger 235 * pulse. 236 * 0b1..Asynchronous mode. The ADC clock is based on the output of the ADC clock divider ADCCLKSEL in the SYSCON block. 237 */ 238 #define ADC_CTRL_ASYNMODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ASYNMODE_SHIFT)) & ADC_CTRL_ASYNMODE_MASK) 239 #define ADC_CTRL_RESOL_MASK (0x600U) 240 #define ADC_CTRL_RESOL_SHIFT (9U) 241 /*! RESOL - The number of bits of ADC resolution. Accuracy can be reduced to achieve higher 242 * conversion rates. A single conversion (including one conversion in a burst or sequence) requires the 243 * selected number of bits of resolution plus 3 ADC clocks. This field must only be altered when 244 * the ADC is fully idle. Changing it during any kind of ADC operation may have unpredictable 245 * results. ADC clock frequencies for various resolutions must not exceed: - 5x the system clock rate 246 * for 12-bit resolution - 4.3x the system clock rate for 10-bit resolution - 3.6x the system 247 * clock for 8-bit resolution - 3x the bus clock rate for 6-bit resolution 248 * 0b00..6-bit resolution. An ADC conversion requires 9 ADC clocks, plus any clocks specified by the TSAMP field. 249 * 0b01..8-bit resolution. An ADC conversion requires 11 ADC clocks, plus any clocks specified by the TSAMP field. 250 * 0b10..10-bit resolution. An ADC conversion requires 13 ADC clocks, plus any clocks specified by the TSAMP field. 251 * 0b11..12-bit resolution. An ADC conversion requires 15 ADC clocks, plus any clocks specified by the TSAMP field. 252 */ 253 #define ADC_CTRL_RESOL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RESOL_SHIFT)) & ADC_CTRL_RESOL_MASK) 254 #define ADC_CTRL_BYPASSCAL_MASK (0x800U) 255 #define ADC_CTRL_BYPASSCAL_SHIFT (11U) 256 /*! BYPASSCAL - Bypass Calibration. This bit may be set to avoid the need to calibrate if offset 257 * error is not a concern in the application. 258 * 0b0..Calibrate. The stored calibration value will be applied to the ADC during conversions to compensated for 259 * offset error. A calibration cycle must be performed each time the chip is powered-up. Re-calibration may 260 * be warranted periodically - especially if operating conditions have changed. 261 * 0b1..Bypass calibration. Calibration is not utilized. Less time is required when enabling the ADC - 262 * particularly following chip power-up. Attempts to launch a calibration cycle are blocked when this bit is set. 263 */ 264 #define ADC_CTRL_BYPASSCAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_BYPASSCAL_SHIFT)) & ADC_CTRL_BYPASSCAL_MASK) 265 #define ADC_CTRL_TSAMP_MASK (0x7000U) 266 #define ADC_CTRL_TSAMP_SHIFT (12U) 267 /*! TSAMP - Sample Time. The default sampling period (TSAMP = '000') at the start of each conversion 268 * is 2.5 ADC clock periods. Depending on a variety of factors, including operating conditions 269 * and the output impedance of the analog source, longer sampling times may be required. See 270 * Section 28.7.10. The TSAMP field specifies the number of additional ADC clock cycles, from zero to 271 * seven, by which the sample period will be extended. The total conversion time will increase by 272 * the same number of clocks. 000 - The sample period will be the default 2.5 ADC clocks. A 273 * complete conversion with 12-bits of accuracy will require 15 clocks. 001- The sample period will 274 * be extended by one ADC clock to a total of 3.5 clock periods. A complete 12-bit conversion will 275 * require 16 clocks. 010 - The sample period will be extended by two clocks to 4.5 ADC clock 276 * cycles. A complete 12-bit conversion will require 17 ADC clocks. 111 - The sample period will be 277 * extended by seven clocks to 9.5 ADC clock cycles. A complete 12-bit conversion will require 278 * 22 ADC clocks. 279 */ 280 #define ADC_CTRL_TSAMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_TSAMP_SHIFT)) & ADC_CTRL_TSAMP_MASK) 281 /*! @} */ 282 283 /*! @name INSEL - Input Select. Allows selection of the temperature sensor as an alternate input to ADC channel 0. */ 284 /*! @{ */ 285 #define ADC_INSEL_SEL_MASK (0x3U) 286 #define ADC_INSEL_SEL_SHIFT (0U) 287 /*! SEL - Selects the input source for channel 0. All other values are reserved. 288 * 0b00..ADC0_IN0 function. 289 * 0b11..Internal temperature sensor. 290 */ 291 #define ADC_INSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_INSEL_SEL_SHIFT)) & ADC_INSEL_SEL_MASK) 292 /*! @} */ 293 294 /*! @name SEQ_CTRL - ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n. */ 295 /*! @{ */ 296 #define ADC_SEQ_CTRL_CHANNELS_MASK (0xFFFU) 297 #define ADC_SEQ_CTRL_CHANNELS_SHIFT (0U) 298 /*! CHANNELS - Selects which one or more of the ADC channels will be sampled and converted when this 299 * sequence is launched. A 1 in any bit of this field will cause the corresponding channel to be 300 * included in the conversion sequence, where bit 0 corresponds to channel 0, bit 1 to channel 1 301 * and so forth. When this conversion sequence is triggered, either by a hardware trigger or via 302 * software command, ADC conversions will be performed on each enabled channel, in sequence, 303 * beginning with the lowest-ordered channel. This field can ONLY be changed while SEQA_ENA (bit 31) 304 * is LOW. It is allowed to change this field and set bit 31 in the same write. 305 */ 306 #define ADC_SEQ_CTRL_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_CHANNELS_SHIFT)) & ADC_SEQ_CTRL_CHANNELS_MASK) 307 #define ADC_SEQ_CTRL_TRIGGER_MASK (0x3F000U) 308 #define ADC_SEQ_CTRL_TRIGGER_SHIFT (12U) 309 /*! TRIGGER - Selects which of the available hardware trigger sources will cause this conversion 310 * sequence to be initiated. Program the trigger input number in this field. See Table 476. In order 311 * to avoid generating a spurious trigger, it is recommended writing to this field only when 312 * SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write. 313 */ 314 #define ADC_SEQ_CTRL_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_TRIGGER_SHIFT)) & ADC_SEQ_CTRL_TRIGGER_MASK) 315 #define ADC_SEQ_CTRL_TRIGPOL_MASK (0x40000U) 316 #define ADC_SEQ_CTRL_TRIGPOL_SHIFT (18U) 317 /*! TRIGPOL - Select the polarity of the selected input trigger for this conversion sequence. In 318 * order to avoid generating a spurious trigger, it is recommended writing to this field only when 319 * SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write. 320 * 0b0..Negative edge. A negative edge launches the conversion sequence on the selected trigger input. 321 * 0b1..Positive edge. A positive edge launches the conversion sequence on the selected trigger input. 322 */ 323 #define ADC_SEQ_CTRL_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_TRIGPOL_SHIFT)) & ADC_SEQ_CTRL_TRIGPOL_MASK) 324 #define ADC_SEQ_CTRL_SYNCBYPASS_MASK (0x80000U) 325 #define ADC_SEQ_CTRL_SYNCBYPASS_SHIFT (19U) 326 /*! SYNCBYPASS - Setting this bit allows the hardware trigger input to bypass synchronization 327 * flip-flop stages and therefore shorten the time between the trigger input signal and the start of a 328 * conversion. There are slightly different criteria for whether or not this bit can be set 329 * depending on the clock operating mode: Synchronous mode (the ASYNMODE in the CTRL register = 0): 330 * Synchronization may be bypassed (this bit may be set) if the selected trigger source is already 331 * synchronous with the main system clock (eg. coming from an on-chip, system-clock-based timer). 332 * Whether this bit is set or not, a trigger pulse must be maintained for at least one system 333 * clock period. Asynchronous mode (the ASYNMODE in the CTRL register = 1): Synchronization may be 334 * bypassed (this bit may be set) if it is certain that the duration of a trigger input pulse 335 * will be at least one cycle of the ADC clock (regardless of whether the trigger comes from and 336 * on-chip or off-chip source). If this bit is NOT set, the trigger pulse must at least be 337 * maintained for one system clock period. 338 * 0b0..Enable trigger synchronization. The hardware trigger bypass is not enabled. 339 * 0b1..Bypass trigger synchronization. The hardware trigger bypass is enabled. 340 */ 341 #define ADC_SEQ_CTRL_SYNCBYPASS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SYNCBYPASS_SHIFT)) & ADC_SEQ_CTRL_SYNCBYPASS_MASK) 342 #define ADC_SEQ_CTRL_START_MASK (0x4000000U) 343 #define ADC_SEQ_CTRL_START_SHIFT (26U) 344 /*! START - Writing a 1 to this field will launch one pass through this conversion sequence. The 345 * behavior will be identical to a sequence triggered by a hardware trigger. Do not write 1 to this 346 * bit if the BURST bit is set. This bit is only set to a 1 momentarily when written to launch a 347 * conversion sequence. It will consequently always read back as a zero. 348 */ 349 #define ADC_SEQ_CTRL_START(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_START_SHIFT)) & ADC_SEQ_CTRL_START_MASK) 350 #define ADC_SEQ_CTRL_BURST_MASK (0x8000000U) 351 #define ADC_SEQ_CTRL_BURST_SHIFT (27U) 352 /*! BURST - Writing a 1 to this bit will cause this conversion sequence to be continuously cycled 353 * through. Other sequence A triggers will be ignored while this bit is set. Repeated conversions 354 * can be halted by clearing this bit. The sequence currently in progress will be completed before 355 * conversions are terminated. Note that a new sequence could begin just before BURST is cleared. 356 */ 357 #define ADC_SEQ_CTRL_BURST(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_BURST_SHIFT)) & ADC_SEQ_CTRL_BURST_MASK) 358 #define ADC_SEQ_CTRL_SINGLESTEP_MASK (0x10000000U) 359 #define ADC_SEQ_CTRL_SINGLESTEP_SHIFT (28U) 360 /*! SINGLESTEP - When this bit is set, a hardware trigger or a write to the START bit will launch a 361 * single conversion on the next channel in the sequence instead of the default response of 362 * launching an entire sequence of conversions. Once all of the channels comprising a sequence have 363 * been converted, a subsequent trigger will repeat the sequence beginning with the first enabled 364 * channel. Interrupt generation will still occur either after each individual conversion or at 365 * the end of the entire sequence, depending on the state of the MODE bit. 366 */ 367 #define ADC_SEQ_CTRL_SINGLESTEP(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SINGLESTEP_SHIFT)) & ADC_SEQ_CTRL_SINGLESTEP_MASK) 368 #define ADC_SEQ_CTRL_LOWPRIO_MASK (0x20000000U) 369 #define ADC_SEQ_CTRL_LOWPRIO_SHIFT (29U) 370 /*! LOWPRIO - Set priority for sequence A. 371 * 0b0..Low priority. Any B trigger which occurs while an A conversion sequence is active will be ignored and lost. 372 * 0b1..High priority. Setting this bit to a 1 will permit any enabled B sequence trigger (including a B sequence 373 * software start) to immediately interrupt sequence A and launch a B sequence in it's place. The conversion 374 * currently in progress will be terminated. The A sequence that was interrupted will automatically resume 375 * after the B sequence completes. The channel whose conversion was terminated will be re-sampled and the 376 * conversion sequence will resume from that point. 377 */ 378 #define ADC_SEQ_CTRL_LOWPRIO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_LOWPRIO_SHIFT)) & ADC_SEQ_CTRL_LOWPRIO_MASK) 379 #define ADC_SEQ_CTRL_MODE_MASK (0x40000000U) 380 #define ADC_SEQ_CTRL_MODE_SHIFT (30U) 381 /*! MODE - Indicates whether the primary method for retrieving conversion results for this sequence 382 * will be accomplished via reading the global data register (SEQA_GDAT) at the end of each 383 * conversion, or the individual channel result registers at the end of the entire sequence. Impacts 384 * when conversion-complete interrupt/DMA trigger for sequence-A will be generated and which 385 * overrun conditions contribute to an overrun interrupt as described below. 386 * 0b0..End of conversion. The sequence A interrupt/DMA trigger will be set at the end of each individual ADC 387 * conversion performed under sequence A. This flag will mirror the DATAVALID bit in the SEQA_GDAT register. The 388 * OVERRUN bit in the SEQA_GDAT register will contribute to generation of an overrun interrupt/DMA trigger 389 * if enabled. 390 * 0b1..End of sequence. The sequence A interrupt/DMA trigger will be set when the entire set of sequence-A 391 * conversions completes. This flag will need to be explicitly cleared by software or by the DMA-clear signal in 392 * this mode. The OVERRUN bit in the SEQA_GDAT register will NOT contribute to generation of an overrun 393 * interrupt/DMA trigger since it is assumed this register may not be utilized in this mode. 394 */ 395 #define ADC_SEQ_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_MODE_SHIFT)) & ADC_SEQ_CTRL_MODE_MASK) 396 #define ADC_SEQ_CTRL_SEQ_ENA_MASK (0x80000000U) 397 #define ADC_SEQ_CTRL_SEQ_ENA_SHIFT (31U) 398 /*! SEQ_ENA - Sequence Enable. In order to avoid spuriously triggering the sequence, care should be 399 * taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE state 400 * (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be triggered 401 * immediately upon being enabled. In order to avoid spuriously triggering the sequence, care 402 * should be taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE 403 * state (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be 404 * triggered immediately upon being enabled. 405 * 0b0..Disabled. Sequence n is disabled. Sequence n triggers are ignored. If this bit is cleared while sequence 406 * n is in progress, the sequence will be halted at the end of the current conversion. After the sequence is 407 * re-enabled, a new trigger will be required to restart the sequence beginning with the next enabled channel. 408 * 0b1..Enabled. Sequence n is enabled. 409 */ 410 #define ADC_SEQ_CTRL_SEQ_ENA(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SEQ_ENA_SHIFT)) & ADC_SEQ_CTRL_SEQ_ENA_MASK) 411 /*! @} */ 412 413 /* The count of ADC_SEQ_CTRL */ 414 #define ADC_SEQ_CTRL_COUNT (2U) 415 416 /*! @name SEQ_GDAT - ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n. */ 417 /*! @{ */ 418 #define ADC_SEQ_GDAT_RESULT_MASK (0xFFF0U) 419 #define ADC_SEQ_GDAT_RESULT_SHIFT (4U) 420 /*! RESULT - This field contains the 12-bit ADC conversion result from the most recent conversion 421 * performed under conversion sequence associated with this register. The result is a binary 422 * fraction representing the voltage on the currently-selected input channel as it falls within the 423 * range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less 424 * than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input 425 * was close to, equal to, or greater than that on VREFP. DATAVALID = 1 indicates that this 426 * result has not yet been read. 427 */ 428 #define ADC_SEQ_GDAT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_RESULT_SHIFT)) & ADC_SEQ_GDAT_RESULT_MASK) 429 #define ADC_SEQ_GDAT_THCMPRANGE_MASK (0x30000U) 430 #define ADC_SEQ_GDAT_THCMPRANGE_SHIFT (16U) 431 /*! THCMPRANGE - Indicates whether the result of the last conversion performed was above, below or 432 * within the range established by the designated threshold comparison registers (THRn_LOW and 433 * THRn_HIGH). 434 */ 435 #define ADC_SEQ_GDAT_THCMPRANGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_THCMPRANGE_SHIFT)) & ADC_SEQ_GDAT_THCMPRANGE_MASK) 436 #define ADC_SEQ_GDAT_THCMPCROSS_MASK (0xC0000U) 437 #define ADC_SEQ_GDAT_THCMPCROSS_SHIFT (18U) 438 /*! THCMPCROSS - Indicates whether the result of the last conversion performed represented a 439 * crossing of the threshold level established by the designated LOW threshold comparison register 440 * (THRn_LOW) and, if so, in what direction the crossing occurred. 441 */ 442 #define ADC_SEQ_GDAT_THCMPCROSS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_THCMPCROSS_SHIFT)) & ADC_SEQ_GDAT_THCMPCROSS_MASK) 443 #define ADC_SEQ_GDAT_CHN_MASK (0x3C000000U) 444 #define ADC_SEQ_GDAT_CHN_SHIFT (26U) 445 /*! CHN - These bits contain the channel from which the RESULT bits were converted (e.g. 0000 446 * identifies channel 0, 0001 channel 1, etc.). 447 */ 448 #define ADC_SEQ_GDAT_CHN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_CHN_SHIFT)) & ADC_SEQ_GDAT_CHN_MASK) 449 #define ADC_SEQ_GDAT_OVERRUN_MASK (0x40000000U) 450 #define ADC_SEQ_GDAT_OVERRUN_SHIFT (30U) 451 /*! OVERRUN - This bit is set if a new conversion result is loaded into the RESULT field before a 452 * previous result has been read - i.e. while the DATAVALID bit is set. This bit is cleared, along 453 * with the DATAVALID bit, whenever this register is read. This bit will contribute to an overrun 454 * interrupt/DMA trigger if the MODE bit (in SEQAA_CTRL) for the corresponding sequence is set 455 * to '0' (and if the overrun interrupt is enabled). 456 */ 457 #define ADC_SEQ_GDAT_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_OVERRUN_SHIFT)) & ADC_SEQ_GDAT_OVERRUN_MASK) 458 #define ADC_SEQ_GDAT_DATAVALID_MASK (0x80000000U) 459 #define ADC_SEQ_GDAT_DATAVALID_SHIFT (31U) 460 /*! DATAVALID - This bit is set to '1' at the end of each conversion when a new result is loaded 461 * into the RESULT field. It is cleared whenever this register is read. This bit will cause a 462 * conversion-complete interrupt for the corresponding sequence if the MODE bit (in SEQA_CTRL) for that 463 * sequence is set to 0 (and if the interrupt is enabled). 464 */ 465 #define ADC_SEQ_GDAT_DATAVALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_DATAVALID_SHIFT)) & ADC_SEQ_GDAT_DATAVALID_MASK) 466 /*! @} */ 467 468 /* The count of ADC_SEQ_GDAT */ 469 #define ADC_SEQ_GDAT_COUNT (2U) 470 471 /*! @name DAT - ADC Channel 0 Data register. This register contains the result of the most recent conversion completed on channel 0. */ 472 /*! @{ */ 473 #define ADC_DAT_RESULT_MASK (0xFFF0U) 474 #define ADC_DAT_RESULT_SHIFT (4U) 475 /*! RESULT - This field contains the 12-bit ADC conversion result from the last conversion performed 476 * on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, 477 * as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on 478 * the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that 479 * the voltage on the input was close to, equal to, or greater than that on VREFP. 480 */ 481 #define ADC_DAT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_RESULT_SHIFT)) & ADC_DAT_RESULT_MASK) 482 #define ADC_DAT_THCMPRANGE_MASK (0x30000U) 483 #define ADC_DAT_THCMPRANGE_SHIFT (16U) 484 /*! THCMPRANGE - Threshold Range Comparison result. 0x0 = In Range: The last completed conversion 485 * was greater than or equal to the value programmed into the designated LOW threshold register 486 * (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold 487 * register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value 488 * programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last 489 * completed conversion was greater than the value programmed into the designated HIGH threshold 490 * register (THRn_HIGH). 0x3 = Reserved. 491 */ 492 #define ADC_DAT_THCMPRANGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_THCMPRANGE_SHIFT)) & ADC_DAT_THCMPRANGE_MASK) 493 #define ADC_DAT_THCMPCROSS_MASK (0xC0000U) 494 #define ADC_DAT_THCMPCROSS_SHIFT (18U) 495 /*! THCMPCROSS - Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The 496 * most recent completed conversion on this channel had the same relationship (above or below) to 497 * the threshold value established by the designated LOW threshold register (THRn_LOW) as did the 498 * previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing 499 * Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the 500 * previous sample on this channel was above the threshold value established by the designated LOW 501 * threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward 502 * Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred 503 * - i.e. the previous sample on this channel was below the threshold value established by the 504 * designated LOW threshold register (THRn_LOW) and the current sample is above that threshold. 505 */ 506 #define ADC_DAT_THCMPCROSS(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_THCMPCROSS_SHIFT)) & ADC_DAT_THCMPCROSS_MASK) 507 #define ADC_DAT_CHANNEL_MASK (0x3C000000U) 508 #define ADC_DAT_CHANNEL_SHIFT (26U) 509 /*! CHANNEL - This field is hard-coded to contain the channel number that this particular register 510 * relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 511 * register, etc) 512 */ 513 #define ADC_DAT_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_CHANNEL_SHIFT)) & ADC_DAT_CHANNEL_MASK) 514 #define ADC_DAT_OVERRUN_MASK (0x40000000U) 515 #define ADC_DAT_OVERRUN_SHIFT (30U) 516 /*! OVERRUN - This bit will be set to a 1 if a new conversion on this channel completes and 517 * overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit 518 * is set. This bit is cleared, along with the DONE bit, whenever this register is read or when 519 * the data related to this channel is read from either of the global SEQn_GDAT registers. This 520 * bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if 521 * the overrun interrupt is enabled. While it is allowed to include the same channels in both 522 * conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the 523 * data registers associated with any of the channels that are shared between the two sequences. Any 524 * erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled. 525 */ 526 #define ADC_DAT_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_OVERRUN_SHIFT)) & ADC_DAT_OVERRUN_MASK) 527 #define ADC_DAT_DATAVALID_MASK (0x80000000U) 528 #define ADC_DAT_DATAVALID_SHIFT (31U) 529 /*! DATAVALID - This bit is set to 1 when an ADC conversion on this channel completes. This bit is 530 * cleared whenever this register is read or when the data related to this channel is read from 531 * either of the global SEQn_GDAT registers. While it is allowed to include the same channels in 532 * both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in 533 * the data registers associated with any of the channels that are shared between the two 534 * sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled. 535 */ 536 #define ADC_DAT_DATAVALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_DATAVALID_SHIFT)) & ADC_DAT_DATAVALID_MASK) 537 /*! @} */ 538 539 /* The count of ADC_DAT */ 540 #define ADC_DAT_COUNT (12U) 541 542 /*! @name THR0_LOW - ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0. */ 543 /*! @{ */ 544 #define ADC_THR0_LOW_THRLOW_MASK (0xFFF0U) 545 #define ADC_THR0_LOW_THRLOW_SHIFT (4U) 546 /*! THRLOW - Low threshold value against which ADC results will be compared 547 */ 548 #define ADC_THR0_LOW_THRLOW(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR0_LOW_THRLOW_SHIFT)) & ADC_THR0_LOW_THRLOW_MASK) 549 /*! @} */ 550 551 /*! @name THR1_LOW - ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1. */ 552 /*! @{ */ 553 #define ADC_THR1_LOW_THRLOW_MASK (0xFFF0U) 554 #define ADC_THR1_LOW_THRLOW_SHIFT (4U) 555 /*! THRLOW - Low threshold value against which ADC results will be compared 556 */ 557 #define ADC_THR1_LOW_THRLOW(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR1_LOW_THRLOW_SHIFT)) & ADC_THR1_LOW_THRLOW_MASK) 558 /*! @} */ 559 560 /*! @name THR0_HIGH - ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0. */ 561 /*! @{ */ 562 #define ADC_THR0_HIGH_THRHIGH_MASK (0xFFF0U) 563 #define ADC_THR0_HIGH_THRHIGH_SHIFT (4U) 564 /*! THRHIGH - High threshold value against which ADC results will be compared 565 */ 566 #define ADC_THR0_HIGH_THRHIGH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR0_HIGH_THRHIGH_SHIFT)) & ADC_THR0_HIGH_THRHIGH_MASK) 567 /*! @} */ 568 569 /*! @name THR1_HIGH - ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1. */ 570 /*! @{ */ 571 #define ADC_THR1_HIGH_THRHIGH_MASK (0xFFF0U) 572 #define ADC_THR1_HIGH_THRHIGH_SHIFT (4U) 573 /*! THRHIGH - High threshold value against which ADC results will be compared 574 */ 575 #define ADC_THR1_HIGH_THRHIGH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR1_HIGH_THRHIGH_SHIFT)) & ADC_THR1_HIGH_THRHIGH_MASK) 576 /*! @} */ 577 578 /*! @name CHAN_THRSEL - ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel */ 579 /*! @{ */ 580 #define ADC_CHAN_THRSEL_CH0_THRSEL_MASK (0x1U) 581 #define ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT (0U) 582 /*! CH0_THRSEL - Threshold select for channel 0. 583 * 0b0..Threshold 0. Results for this channel will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers. 584 * 0b1..Threshold 1. Results for this channel will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers. 585 */ 586 #define ADC_CHAN_THRSEL_CH0_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH0_THRSEL_MASK) 587 #define ADC_CHAN_THRSEL_CH1_THRSEL_MASK (0x2U) 588 #define ADC_CHAN_THRSEL_CH1_THRSEL_SHIFT (1U) 589 /*! CH1_THRSEL - Threshold select for channel 1. See description for channel 0. 590 */ 591 #define ADC_CHAN_THRSEL_CH1_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH1_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH1_THRSEL_MASK) 592 #define ADC_CHAN_THRSEL_CH2_THRSEL_MASK (0x4U) 593 #define ADC_CHAN_THRSEL_CH2_THRSEL_SHIFT (2U) 594 /*! CH2_THRSEL - Threshold select for channel 2. See description for channel 0. 595 */ 596 #define ADC_CHAN_THRSEL_CH2_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH2_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH2_THRSEL_MASK) 597 #define ADC_CHAN_THRSEL_CH3_THRSEL_MASK (0x8U) 598 #define ADC_CHAN_THRSEL_CH3_THRSEL_SHIFT (3U) 599 /*! CH3_THRSEL - Threshold select for channel 3. See description for channel 0. 600 */ 601 #define ADC_CHAN_THRSEL_CH3_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH3_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH3_THRSEL_MASK) 602 #define ADC_CHAN_THRSEL_CH4_THRSEL_MASK (0x10U) 603 #define ADC_CHAN_THRSEL_CH4_THRSEL_SHIFT (4U) 604 /*! CH4_THRSEL - Threshold select for channel 4. See description for channel 0. 605 */ 606 #define ADC_CHAN_THRSEL_CH4_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH4_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH4_THRSEL_MASK) 607 #define ADC_CHAN_THRSEL_CH5_THRSEL_MASK (0x20U) 608 #define ADC_CHAN_THRSEL_CH5_THRSEL_SHIFT (5U) 609 /*! CH5_THRSEL - Threshold select for channel 5. See description for channel 0. 610 */ 611 #define ADC_CHAN_THRSEL_CH5_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH5_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH5_THRSEL_MASK) 612 #define ADC_CHAN_THRSEL_CH6_THRSEL_MASK (0x40U) 613 #define ADC_CHAN_THRSEL_CH6_THRSEL_SHIFT (6U) 614 /*! CH6_THRSEL - Threshold select for channel 6. See description for channel 0. 615 */ 616 #define ADC_CHAN_THRSEL_CH6_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH6_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH6_THRSEL_MASK) 617 #define ADC_CHAN_THRSEL_CH7_THRSEL_MASK (0x80U) 618 #define ADC_CHAN_THRSEL_CH7_THRSEL_SHIFT (7U) 619 /*! CH7_THRSEL - Threshold select for channel 7. See description for channel 0. 620 */ 621 #define ADC_CHAN_THRSEL_CH7_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH7_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH7_THRSEL_MASK) 622 #define ADC_CHAN_THRSEL_CH8_THRSEL_MASK (0x100U) 623 #define ADC_CHAN_THRSEL_CH8_THRSEL_SHIFT (8U) 624 /*! CH8_THRSEL - Threshold select for channel 8. See description for channel 0. 625 */ 626 #define ADC_CHAN_THRSEL_CH8_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH8_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH8_THRSEL_MASK) 627 #define ADC_CHAN_THRSEL_CH9_THRSEL_MASK (0x200U) 628 #define ADC_CHAN_THRSEL_CH9_THRSEL_SHIFT (9U) 629 /*! CH9_THRSEL - Threshold select for channel 9. See description for channel 0. 630 */ 631 #define ADC_CHAN_THRSEL_CH9_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH9_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH9_THRSEL_MASK) 632 #define ADC_CHAN_THRSEL_CH10_THRSEL_MASK (0x400U) 633 #define ADC_CHAN_THRSEL_CH10_THRSEL_SHIFT (10U) 634 /*! CH10_THRSEL - Threshold select for channel 10. See description for channel 0. 635 */ 636 #define ADC_CHAN_THRSEL_CH10_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH10_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH10_THRSEL_MASK) 637 #define ADC_CHAN_THRSEL_CH11_THRSEL_MASK (0x800U) 638 #define ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT (11U) 639 /*! CH11_THRSEL - Threshold select for channel 11. See description for channel 0. 640 */ 641 #define ADC_CHAN_THRSEL_CH11_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH11_THRSEL_MASK) 642 /*! @} */ 643 644 /*! @name INTEN - ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated. */ 645 /*! @{ */ 646 #define ADC_INTEN_SEQA_INTEN_MASK (0x1U) 647 #define ADC_INTEN_SEQA_INTEN_SHIFT (0U) 648 /*! SEQA_INTEN - Sequence A interrupt enable. 649 * 0b0..Disabled. The sequence A interrupt/DMA trigger is disabled. 650 * 0b1..Enabled. The sequence A interrupt/DMA trigger is enabled and will be asserted either upon completion of 651 * each individual conversion performed as part of sequence A, or upon completion of the entire A sequence of 652 * conversions, depending on the MODE bit in the SEQA_CTRL register. 653 */ 654 #define ADC_INTEN_SEQA_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_SEQA_INTEN_SHIFT)) & ADC_INTEN_SEQA_INTEN_MASK) 655 #define ADC_INTEN_SEQB_INTEN_MASK (0x2U) 656 #define ADC_INTEN_SEQB_INTEN_SHIFT (1U) 657 /*! SEQB_INTEN - Sequence B interrupt enable. 658 * 0b0..Disabled. The sequence B interrupt/DMA trigger is disabled. 659 * 0b1..Enabled. The sequence B interrupt/DMA trigger is enabled and will be asserted either upon completion of 660 * each individual conversion performed as part of sequence B, or upon completion of the entire B sequence of 661 * conversions, depending on the MODE bit in the SEQB_CTRL register. 662 */ 663 #define ADC_INTEN_SEQB_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_SEQB_INTEN_SHIFT)) & ADC_INTEN_SEQB_INTEN_MASK) 664 #define ADC_INTEN_OVR_INTEN_MASK (0x4U) 665 #define ADC_INTEN_OVR_INTEN_SHIFT (2U) 666 /*! OVR_INTEN - Overrun interrupt enable. 667 * 0b0..Disabled. The overrun interrupt is disabled. 668 * 0b1..Enabled. The overrun interrupt is enabled. Detection of an overrun condition on any of the 12 channel 669 * data registers will cause an overrun interrupt/DMA trigger. In addition, if the MODE bit for a particular 670 * sequence is 0, then an overrun in the global data register for that sequence will also cause this 671 * interrupt/DMA trigger to be asserted. 672 */ 673 #define ADC_INTEN_OVR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_OVR_INTEN_SHIFT)) & ADC_INTEN_OVR_INTEN_MASK) 674 #define ADC_INTEN_ADCMPINTEN0_MASK (0x18U) 675 #define ADC_INTEN_ADCMPINTEN0_SHIFT (3U) 676 /*! ADCMPINTEN0 - Threshold comparison interrupt enable for channel 0. 677 * 0b00..Disabled. 678 * 0b01..Outside threshold. 679 * 0b10..Crossing threshold. 680 * 0b11..Reserved 681 */ 682 #define ADC_INTEN_ADCMPINTEN0(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN0_SHIFT)) & ADC_INTEN_ADCMPINTEN0_MASK) 683 #define ADC_INTEN_ADCMPINTEN1_MASK (0x60U) 684 #define ADC_INTEN_ADCMPINTEN1_SHIFT (5U) 685 /*! ADCMPINTEN1 - Channel 1 threshold comparison interrupt enable. See description for channel 0. 686 */ 687 #define ADC_INTEN_ADCMPINTEN1(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN1_SHIFT)) & ADC_INTEN_ADCMPINTEN1_MASK) 688 #define ADC_INTEN_ADCMPINTEN2_MASK (0x180U) 689 #define ADC_INTEN_ADCMPINTEN2_SHIFT (7U) 690 /*! ADCMPINTEN2 - Channel 2 threshold comparison interrupt enable. See description for channel 0. 691 */ 692 #define ADC_INTEN_ADCMPINTEN2(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN2_SHIFT)) & ADC_INTEN_ADCMPINTEN2_MASK) 693 #define ADC_INTEN_ADCMPINTEN3_MASK (0x600U) 694 #define ADC_INTEN_ADCMPINTEN3_SHIFT (9U) 695 /*! ADCMPINTEN3 - Channel 3 threshold comparison interrupt enable. See description for channel 0. 696 */ 697 #define ADC_INTEN_ADCMPINTEN3(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN3_SHIFT)) & ADC_INTEN_ADCMPINTEN3_MASK) 698 #define ADC_INTEN_ADCMPINTEN4_MASK (0x1800U) 699 #define ADC_INTEN_ADCMPINTEN4_SHIFT (11U) 700 /*! ADCMPINTEN4 - Channel 4 threshold comparison interrupt enable. See description for channel 0. 701 */ 702 #define ADC_INTEN_ADCMPINTEN4(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN4_SHIFT)) & ADC_INTEN_ADCMPINTEN4_MASK) 703 #define ADC_INTEN_ADCMPINTEN5_MASK (0x6000U) 704 #define ADC_INTEN_ADCMPINTEN5_SHIFT (13U) 705 /*! ADCMPINTEN5 - Channel 5 threshold comparison interrupt enable. See description for channel 0. 706 */ 707 #define ADC_INTEN_ADCMPINTEN5(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN5_SHIFT)) & ADC_INTEN_ADCMPINTEN5_MASK) 708 #define ADC_INTEN_ADCMPINTEN6_MASK (0x18000U) 709 #define ADC_INTEN_ADCMPINTEN6_SHIFT (15U) 710 /*! ADCMPINTEN6 - Channel 6 threshold comparison interrupt enable. See description for channel 0. 711 */ 712 #define ADC_INTEN_ADCMPINTEN6(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN6_SHIFT)) & ADC_INTEN_ADCMPINTEN6_MASK) 713 #define ADC_INTEN_ADCMPINTEN7_MASK (0x60000U) 714 #define ADC_INTEN_ADCMPINTEN7_SHIFT (17U) 715 /*! ADCMPINTEN7 - Channel 7 threshold comparison interrupt enable. See description for channel 0. 716 */ 717 #define ADC_INTEN_ADCMPINTEN7(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN7_SHIFT)) & ADC_INTEN_ADCMPINTEN7_MASK) 718 #define ADC_INTEN_ADCMPINTEN8_MASK (0x180000U) 719 #define ADC_INTEN_ADCMPINTEN8_SHIFT (19U) 720 /*! ADCMPINTEN8 - Channel 8 threshold comparison interrupt enable. See description for channel 0. 721 */ 722 #define ADC_INTEN_ADCMPINTEN8(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN8_SHIFT)) & ADC_INTEN_ADCMPINTEN8_MASK) 723 #define ADC_INTEN_ADCMPINTEN9_MASK (0x600000U) 724 #define ADC_INTEN_ADCMPINTEN9_SHIFT (21U) 725 /*! ADCMPINTEN9 - Channel 9 threshold comparison interrupt enable. See description for channel 0. 726 */ 727 #define ADC_INTEN_ADCMPINTEN9(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN9_SHIFT)) & ADC_INTEN_ADCMPINTEN9_MASK) 728 #define ADC_INTEN_ADCMPINTEN10_MASK (0x1800000U) 729 #define ADC_INTEN_ADCMPINTEN10_SHIFT (23U) 730 /*! ADCMPINTEN10 - Channel 10 threshold comparison interrupt enable. See description for channel 0. 731 */ 732 #define ADC_INTEN_ADCMPINTEN10(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN10_SHIFT)) & ADC_INTEN_ADCMPINTEN10_MASK) 733 #define ADC_INTEN_ADCMPINTEN11_MASK (0x6000000U) 734 #define ADC_INTEN_ADCMPINTEN11_SHIFT (25U) 735 /*! ADCMPINTEN11 - Channel 21 threshold comparison interrupt enable. See description for channel 0. 736 */ 737 #define ADC_INTEN_ADCMPINTEN11(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN11_SHIFT)) & ADC_INTEN_ADCMPINTEN11_MASK) 738 /*! @} */ 739 740 /*! @name FLAGS - ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers). */ 741 /*! @{ */ 742 #define ADC_FLAGS_THCMP0_MASK (0x1U) 743 #define ADC_FLAGS_THCMP0_SHIFT (0U) 744 /*! THCMP0 - Threshold comparison event on Channel 0. Set to 1 upon either an out-of-range result or 745 * a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by 746 * writing a 1. 747 */ 748 #define ADC_FLAGS_THCMP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP0_SHIFT)) & ADC_FLAGS_THCMP0_MASK) 749 #define ADC_FLAGS_THCMP1_MASK (0x2U) 750 #define ADC_FLAGS_THCMP1_SHIFT (1U) 751 /*! THCMP1 - Threshold comparison event on Channel 1. See description for channel 0. 752 */ 753 #define ADC_FLAGS_THCMP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP1_SHIFT)) & ADC_FLAGS_THCMP1_MASK) 754 #define ADC_FLAGS_THCMP2_MASK (0x4U) 755 #define ADC_FLAGS_THCMP2_SHIFT (2U) 756 /*! THCMP2 - Threshold comparison event on Channel 2. See description for channel 0. 757 */ 758 #define ADC_FLAGS_THCMP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP2_SHIFT)) & ADC_FLAGS_THCMP2_MASK) 759 #define ADC_FLAGS_THCMP3_MASK (0x8U) 760 #define ADC_FLAGS_THCMP3_SHIFT (3U) 761 /*! THCMP3 - Threshold comparison event on Channel 3. See description for channel 0. 762 */ 763 #define ADC_FLAGS_THCMP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP3_SHIFT)) & ADC_FLAGS_THCMP3_MASK) 764 #define ADC_FLAGS_THCMP4_MASK (0x10U) 765 #define ADC_FLAGS_THCMP4_SHIFT (4U) 766 /*! THCMP4 - Threshold comparison event on Channel 4. See description for channel 0. 767 */ 768 #define ADC_FLAGS_THCMP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP4_SHIFT)) & ADC_FLAGS_THCMP4_MASK) 769 #define ADC_FLAGS_THCMP5_MASK (0x20U) 770 #define ADC_FLAGS_THCMP5_SHIFT (5U) 771 /*! THCMP5 - Threshold comparison event on Channel 5. See description for channel 0. 772 */ 773 #define ADC_FLAGS_THCMP5(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP5_SHIFT)) & ADC_FLAGS_THCMP5_MASK) 774 #define ADC_FLAGS_THCMP6_MASK (0x40U) 775 #define ADC_FLAGS_THCMP6_SHIFT (6U) 776 /*! THCMP6 - Threshold comparison event on Channel 6. See description for channel 0. 777 */ 778 #define ADC_FLAGS_THCMP6(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP6_SHIFT)) & ADC_FLAGS_THCMP6_MASK) 779 #define ADC_FLAGS_THCMP7_MASK (0x80U) 780 #define ADC_FLAGS_THCMP7_SHIFT (7U) 781 /*! THCMP7 - Threshold comparison event on Channel 7. See description for channel 0. 782 */ 783 #define ADC_FLAGS_THCMP7(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP7_SHIFT)) & ADC_FLAGS_THCMP7_MASK) 784 #define ADC_FLAGS_THCMP8_MASK (0x100U) 785 #define ADC_FLAGS_THCMP8_SHIFT (8U) 786 /*! THCMP8 - Threshold comparison event on Channel 8. See description for channel 0. 787 */ 788 #define ADC_FLAGS_THCMP8(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP8_SHIFT)) & ADC_FLAGS_THCMP8_MASK) 789 #define ADC_FLAGS_THCMP9_MASK (0x200U) 790 #define ADC_FLAGS_THCMP9_SHIFT (9U) 791 /*! THCMP9 - Threshold comparison event on Channel 9. See description for channel 0. 792 */ 793 #define ADC_FLAGS_THCMP9(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP9_SHIFT)) & ADC_FLAGS_THCMP9_MASK) 794 #define ADC_FLAGS_THCMP10_MASK (0x400U) 795 #define ADC_FLAGS_THCMP10_SHIFT (10U) 796 /*! THCMP10 - Threshold comparison event on Channel 10. See description for channel 0. 797 */ 798 #define ADC_FLAGS_THCMP10(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP10_SHIFT)) & ADC_FLAGS_THCMP10_MASK) 799 #define ADC_FLAGS_THCMP11_MASK (0x800U) 800 #define ADC_FLAGS_THCMP11_SHIFT (11U) 801 /*! THCMP11 - Threshold comparison event on Channel 11. See description for channel 0. 802 */ 803 #define ADC_FLAGS_THCMP11(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP11_SHIFT)) & ADC_FLAGS_THCMP11_MASK) 804 #define ADC_FLAGS_OVERRUN0_MASK (0x1000U) 805 #define ADC_FLAGS_OVERRUN0_SHIFT (12U) 806 /*! OVERRUN0 - Mirrors the OVERRRUN status flag from the result register for ADC channel 0 807 */ 808 #define ADC_FLAGS_OVERRUN0(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN0_SHIFT)) & ADC_FLAGS_OVERRUN0_MASK) 809 #define ADC_FLAGS_OVERRUN1_MASK (0x2000U) 810 #define ADC_FLAGS_OVERRUN1_SHIFT (13U) 811 /*! OVERRUN1 - Mirrors the OVERRRUN status flag from the result register for ADC channel 1 812 */ 813 #define ADC_FLAGS_OVERRUN1(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN1_SHIFT)) & ADC_FLAGS_OVERRUN1_MASK) 814 #define ADC_FLAGS_OVERRUN2_MASK (0x4000U) 815 #define ADC_FLAGS_OVERRUN2_SHIFT (14U) 816 /*! OVERRUN2 - Mirrors the OVERRRUN status flag from the result register for ADC channel 2 817 */ 818 #define ADC_FLAGS_OVERRUN2(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN2_SHIFT)) & ADC_FLAGS_OVERRUN2_MASK) 819 #define ADC_FLAGS_OVERRUN3_MASK (0x8000U) 820 #define ADC_FLAGS_OVERRUN3_SHIFT (15U) 821 /*! OVERRUN3 - Mirrors the OVERRRUN status flag from the result register for ADC channel 3 822 */ 823 #define ADC_FLAGS_OVERRUN3(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN3_SHIFT)) & ADC_FLAGS_OVERRUN3_MASK) 824 #define ADC_FLAGS_OVERRUN4_MASK (0x10000U) 825 #define ADC_FLAGS_OVERRUN4_SHIFT (16U) 826 /*! OVERRUN4 - Mirrors the OVERRRUN status flag from the result register for ADC channel 4 827 */ 828 #define ADC_FLAGS_OVERRUN4(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN4_SHIFT)) & ADC_FLAGS_OVERRUN4_MASK) 829 #define ADC_FLAGS_OVERRUN5_MASK (0x20000U) 830 #define ADC_FLAGS_OVERRUN5_SHIFT (17U) 831 /*! OVERRUN5 - Mirrors the OVERRRUN status flag from the result register for ADC channel 5 832 */ 833 #define ADC_FLAGS_OVERRUN5(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN5_SHIFT)) & ADC_FLAGS_OVERRUN5_MASK) 834 #define ADC_FLAGS_OVERRUN6_MASK (0x40000U) 835 #define ADC_FLAGS_OVERRUN6_SHIFT (18U) 836 /*! OVERRUN6 - Mirrors the OVERRRUN status flag from the result register for ADC channel 6 837 */ 838 #define ADC_FLAGS_OVERRUN6(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN6_SHIFT)) & ADC_FLAGS_OVERRUN6_MASK) 839 #define ADC_FLAGS_OVERRUN7_MASK (0x80000U) 840 #define ADC_FLAGS_OVERRUN7_SHIFT (19U) 841 /*! OVERRUN7 - Mirrors the OVERRRUN status flag from the result register for ADC channel 7 842 */ 843 #define ADC_FLAGS_OVERRUN7(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN7_SHIFT)) & ADC_FLAGS_OVERRUN7_MASK) 844 #define ADC_FLAGS_OVERRUN8_MASK (0x100000U) 845 #define ADC_FLAGS_OVERRUN8_SHIFT (20U) 846 /*! OVERRUN8 - Mirrors the OVERRRUN status flag from the result register for ADC channel 8 847 */ 848 #define ADC_FLAGS_OVERRUN8(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN8_SHIFT)) & ADC_FLAGS_OVERRUN8_MASK) 849 #define ADC_FLAGS_OVERRUN9_MASK (0x200000U) 850 #define ADC_FLAGS_OVERRUN9_SHIFT (21U) 851 /*! OVERRUN9 - Mirrors the OVERRRUN status flag from the result register for ADC channel 9 852 */ 853 #define ADC_FLAGS_OVERRUN9(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN9_SHIFT)) & ADC_FLAGS_OVERRUN9_MASK) 854 #define ADC_FLAGS_OVERRUN10_MASK (0x400000U) 855 #define ADC_FLAGS_OVERRUN10_SHIFT (22U) 856 /*! OVERRUN10 - Mirrors the OVERRRUN status flag from the result register for ADC channel 10 857 */ 858 #define ADC_FLAGS_OVERRUN10(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN10_SHIFT)) & ADC_FLAGS_OVERRUN10_MASK) 859 #define ADC_FLAGS_OVERRUN11_MASK (0x800000U) 860 #define ADC_FLAGS_OVERRUN11_SHIFT (23U) 861 /*! OVERRUN11 - Mirrors the OVERRRUN status flag from the result register for ADC channel 11 862 */ 863 #define ADC_FLAGS_OVERRUN11(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN11_SHIFT)) & ADC_FLAGS_OVERRUN11_MASK) 864 #define ADC_FLAGS_SEQA_OVR_MASK (0x1000000U) 865 #define ADC_FLAGS_SEQA_OVR_SHIFT (24U) 866 /*! SEQA_OVR - Mirrors the global OVERRUN status flag in the SEQA_GDAT register 867 */ 868 #define ADC_FLAGS_SEQA_OVR(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQA_OVR_SHIFT)) & ADC_FLAGS_SEQA_OVR_MASK) 869 #define ADC_FLAGS_SEQB_OVR_MASK (0x2000000U) 870 #define ADC_FLAGS_SEQB_OVR_SHIFT (25U) 871 /*! SEQB_OVR - Mirrors the global OVERRUN status flag in the SEQB_GDAT register 872 */ 873 #define ADC_FLAGS_SEQB_OVR(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQB_OVR_SHIFT)) & ADC_FLAGS_SEQB_OVR_MASK) 874 #define ADC_FLAGS_SEQA_INT_MASK (0x10000000U) 875 #define ADC_FLAGS_SEQA_INT_SHIFT (28U) 876 /*! SEQA_INT - Sequence A interrupt/DMA trigger. If the MODE bit in the SEQA_CTRL register is 0, 877 * this flag will mirror the DATAVALID bit in the sequence A global data register (SEQA_GDAT), which 878 * is set at the end of every ADC conversion performed as part of sequence A. It will be cleared 879 * automatically when the SEQA_GDAT register is read. If the MODE bit in the SEQA_CTRL register 880 * is 1, this flag will be set upon completion of an entire A sequence. In this case it must be 881 * cleared by writing a 1 to this SEQA_INT bit. This interrupt must be enabled in the INTEN 882 * register. 883 */ 884 #define ADC_FLAGS_SEQA_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQA_INT_SHIFT)) & ADC_FLAGS_SEQA_INT_MASK) 885 #define ADC_FLAGS_SEQB_INT_MASK (0x20000000U) 886 #define ADC_FLAGS_SEQB_INT_SHIFT (29U) 887 /*! SEQB_INT - Sequence A interrupt/DMA trigger. If the MODE bit in the SEQB_CTRL register is 0, 888 * this flag will mirror the DATAVALID bit in the sequence A global data register (SEQB_GDAT), which 889 * is set at the end of every ADC conversion performed as part of sequence B. It will be cleared 890 * automatically when the SEQB_GDAT register is read. If the MODE bit in the SEQB_CTRL register 891 * is 1, this flag will be set upon completion of an entire B sequence. In this case it must be 892 * cleared by writing a 1 to this SEQB_INT bit. This interrupt must be enabled in the INTEN 893 * register. 894 */ 895 #define ADC_FLAGS_SEQB_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQB_INT_SHIFT)) & ADC_FLAGS_SEQB_INT_MASK) 896 #define ADC_FLAGS_THCMP_INT_MASK (0x40000000U) 897 #define ADC_FLAGS_THCMP_INT_SHIFT (30U) 898 /*! THCMP_INT - Threshold Comparison Interrupt. This bit will be set if any of the THCMP flags in 899 * the lower bits of this register are set to 1 (due to an enabled out-of-range or 900 * threshold-crossing event on any channel). Each type of threshold comparison interrupt on each channel must be 901 * individually enabled in the INTEN register to cause this interrupt. This bit will be cleared 902 * when all of the individual threshold flags are cleared via writing 1s to those bits. 903 */ 904 #define ADC_FLAGS_THCMP_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP_INT_SHIFT)) & ADC_FLAGS_THCMP_INT_MASK) 905 #define ADC_FLAGS_OVR_INT_MASK (0x80000000U) 906 #define ADC_FLAGS_OVR_INT_SHIFT (31U) 907 /*! OVR_INT - Overrun Interrupt flag. Any overrun bit in any of the individual channel data 908 * registers will cause this interrupt. In addition, if the MODE bit in either of the SEQn_CTRL registers 909 * is 0 then the OVERRUN bit in the corresponding SEQn_GDAT register will also cause this 910 * interrupt. This interrupt must be enabled in the INTEN register. This bit will be cleared when all 911 * of the individual overrun bits have been cleared via reading the corresponding data registers. 912 */ 913 #define ADC_FLAGS_OVR_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVR_INT_SHIFT)) & ADC_FLAGS_OVR_INT_MASK) 914 /*! @} */ 915 916 /*! @name STARTUP - ADC Startup register. */ 917 /*! @{ */ 918 #define ADC_STARTUP_ADC_ENA_MASK (0x1U) 919 #define ADC_STARTUP_ADC_ENA_SHIFT (0U) 920 /*! ADC_ENA - ADC Enable bit. This bit can only be set to a 1 by software. It is cleared 921 * automatically whenever the ADC is powered down. This bit must not be set until at least 10 microseconds 922 * after the ADC is powered up (typically by altering a system-level ADC power control bit). 923 */ 924 #define ADC_STARTUP_ADC_ENA(x) (((uint32_t)(((uint32_t)(x)) << ADC_STARTUP_ADC_ENA_SHIFT)) & ADC_STARTUP_ADC_ENA_MASK) 925 #define ADC_STARTUP_ADC_INIT_MASK (0x2U) 926 #define ADC_STARTUP_ADC_INIT_SHIFT (1U) 927 /*! ADC_INIT - ADC Initialization. After enabling the ADC (setting the ADC_ENA bit), the API routine 928 * will EITHER set this bit or the CALIB bit in the CALIB register, depending on whether or not 929 * calibration is required. Setting this bit will launch the 'dummy' conversion cycle that is 930 * required if a calibration is not performed. It will also reload the stored calibration value from 931 * a previous calibration unless the BYPASSCAL bit is set. This bit should only be set AFTER the 932 * ADC_ENA bit is set and after the CALIREQD bit is tested to determine whether a calibration or 933 * an ADC dummy conversion cycle is required. It should not be set during the same write that 934 * sets the ADC_ENA bit. This bit can only be set to a '1' by software. It is cleared automatically 935 * when the 'dummy' conversion cycle completes. 936 */ 937 #define ADC_STARTUP_ADC_INIT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STARTUP_ADC_INIT_SHIFT)) & ADC_STARTUP_ADC_INIT_MASK) 938 /*! @} */ 939 940 /*! @name CALIB - ADC Calibration register. */ 941 /*! @{ */ 942 #define ADC_CALIB_CALIB_MASK (0x1U) 943 #define ADC_CALIB_CALIB_SHIFT (0U) 944 /*! CALIB - Calibration request. Setting this bit will launch an ADC calibration cycle. This bit can 945 * only be set to a '1' by software. It is cleared automatically when the calibration cycle 946 * completes. 947 */ 948 #define ADC_CALIB_CALIB(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALIB_SHIFT)) & ADC_CALIB_CALIB_MASK) 949 #define ADC_CALIB_CALREQD_MASK (0x2U) 950 #define ADC_CALIB_CALREQD_SHIFT (1U) 951 /*! CALREQD - Calibration required. This read-only bit indicates if calibration is required when 952 * enabling the ADC. CALREQD will be '1' if no calibration has been run since the chip was 953 * powered-up and if the BYPASSCAL bit in the CTRL register is low. Software will test this bit to 954 * determine whether to initiate a calibration cycle or whether to set the ADC_INIT bit (in the STARTUP 955 * register) to launch the ADC initialization process which includes a 'dummy' conversion cycle. 956 * Note: A 'dummy' conversion cycle requires approximately 6 ADC clocks as opposed to 81 clocks 957 * required for calibration. 958 */ 959 #define ADC_CALIB_CALREQD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALREQD_SHIFT)) & ADC_CALIB_CALREQD_MASK) 960 #define ADC_CALIB_CALVALUE_MASK (0x1FCU) 961 #define ADC_CALIB_CALVALUE_SHIFT (2U) 962 /*! CALVALUE - Calibration Value. This read-only field displays the calibration value established 963 * during last calibration cycle. This value is not typically of any use to the user. 964 */ 965 #define ADC_CALIB_CALVALUE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALVALUE_SHIFT)) & ADC_CALIB_CALVALUE_MASK) 966 /*! @} */ 967 968 969 /*! 970 * @} 971 */ /* end of group ADC_Register_Masks */ 972 973 974 /* ADC - Peripheral instance base addresses */ 975 /** Peripheral ADC0 base address */ 976 #define ADC0_BASE (0x400A0000u) 977 /** Peripheral ADC0 base pointer */ 978 #define ADC0 ((ADC_Type *)ADC0_BASE) 979 /** Array initializer of ADC peripheral base addresses */ 980 #define ADC_BASE_ADDRS { ADC0_BASE } 981 /** Array initializer of ADC peripheral base pointers */ 982 #define ADC_BASE_PTRS { ADC0 } 983 /** Interrupt vectors for the ADC peripheral type */ 984 #define ADC_SEQ_IRQS { ADC0_SEQA_IRQn, ADC0_SEQB_IRQn } 985 #define ADC_THCMP_IRQS { ADC0_THCMP_IRQn } 986 987 /*! 988 * @} 989 */ /* end of group ADC_Peripheral_Access_Layer */ 990 991 992 /* ---------------------------------------------------------------------------- 993 -- ASYNC_SYSCON Peripheral Access Layer 994 ---------------------------------------------------------------------------- */ 995 996 /*! 997 * @addtogroup ASYNC_SYSCON_Peripheral_Access_Layer ASYNC_SYSCON Peripheral Access Layer 998 * @{ 999 */ 1000 1001 /** ASYNC_SYSCON - Register Layout Typedef */ 1002 typedef struct { 1003 __IO uint32_t ASYNCPRESETCTRL; /**< Async peripheral reset control, offset: 0x0 */ 1004 __O uint32_t ASYNCPRESETCTRLSET; /**< Set bits in ASYNCPRESETCTRL, offset: 0x4 */ 1005 __O uint32_t ASYNCPRESETCTRLCLR; /**< Clear bits in ASYNCPRESETCTRL, offset: 0x8 */ 1006 uint8_t RESERVED_0[4]; 1007 __IO uint32_t ASYNCAPBCLKCTRL; /**< Async peripheral clock control, offset: 0x10 */ 1008 __O uint32_t ASYNCAPBCLKCTRLSET; /**< Set bits in ASYNCAPBCLKCTRL, offset: 0x14 */ 1009 __O uint32_t ASYNCAPBCLKCTRLCLR; /**< Clear bits in ASYNCAPBCLKCTRL, offset: 0x18 */ 1010 uint8_t RESERVED_1[4]; 1011 __IO uint32_t ASYNCAPBCLKSELA; /**< Async APB clock source select A, offset: 0x20 */ 1012 } ASYNC_SYSCON_Type; 1013 1014 /* ---------------------------------------------------------------------------- 1015 -- ASYNC_SYSCON Register Masks 1016 ---------------------------------------------------------------------------- */ 1017 1018 /*! 1019 * @addtogroup ASYNC_SYSCON_Register_Masks ASYNC_SYSCON Register Masks 1020 * @{ 1021 */ 1022 1023 /*! @name ASYNCPRESETCTRL - Async peripheral reset control */ 1024 /*! @{ */ 1025 #define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_MASK (0x2000U) 1026 #define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_SHIFT (13U) 1027 /*! CTIMER3 - Standard counter/timer CTIMER3 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 1028 */ 1029 #define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_MASK) 1030 #define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_MASK (0x4000U) 1031 #define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_SHIFT (14U) 1032 /*! CTIMER4 - Standard counter/timer CTIMER4 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 1033 */ 1034 #define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_MASK) 1035 /*! @} */ 1036 1037 /*! @name ASYNCPRESETCTRLSET - Set bits in ASYNCPRESETCTRL */ 1038 /*! @{ */ 1039 #define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_MASK (0xFFFFFFFFU) 1040 #define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_SHIFT (0U) 1041 /*! ARST_SET - Writing ones to this register sets the corresponding bit or bits in the 1042 * ASYNCPRESETCTRL register, if they are implemented. Bits that do not correspond to defined bits in 1043 * ASYNCPRESETCTRL are reserved and only zeroes should be written to them. 1044 */ 1045 #define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_MASK) 1046 /*! @} */ 1047 1048 /*! @name ASYNCPRESETCTRLCLR - Clear bits in ASYNCPRESETCTRL */ 1049 /*! @{ */ 1050 #define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_MASK (0xFFFFFFFFU) 1051 #define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_SHIFT (0U) 1052 /*! ARST_CLR - Writing ones to this register clears the corresponding bit or bits in the 1053 * ASYNCPRESETCTRL register, if they are implemented. Bits that do not correspond to defined bits in 1054 * ASYNCPRESETCTRL are reserved and only zeroes should be written to them. 1055 */ 1056 #define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_MASK) 1057 /*! @} */ 1058 1059 /*! @name ASYNCAPBCLKCTRL - Async peripheral clock control */ 1060 /*! @{ */ 1061 #define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_MASK (0x2000U) 1062 #define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_SHIFT (13U) 1063 /*! CTIMER3 - Controls the clock for CTIMER3. 0 = Disable; 1 = Enable. 1064 */ 1065 #define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_MASK) 1066 #define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_MASK (0x4000U) 1067 #define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_SHIFT (14U) 1068 /*! CTIMER4 - Controls the clock for CTIMER4. 0 = Disable; 1 = Enable. 1069 */ 1070 #define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_MASK) 1071 /*! @} */ 1072 1073 /*! @name ASYNCAPBCLKCTRLSET - Set bits in ASYNCAPBCLKCTRL */ 1074 /*! @{ */ 1075 #define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_MASK (0xFFFFFFFFU) 1076 #define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_SHIFT (0U) 1077 /*! ACLK_SET - Writing ones to this register sets the corresponding bit or bits in the 1078 * ASYNCAPBCLKCTRL register, if they are implemented. Bits that do not correspond to defined bits in 1079 * ASYNCPRESETCTRL are reserved and only zeroes should be written to them. 1080 */ 1081 #define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_MASK) 1082 /*! @} */ 1083 1084 /*! @name ASYNCAPBCLKCTRLCLR - Clear bits in ASYNCAPBCLKCTRL */ 1085 /*! @{ */ 1086 #define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_MASK (0xFFFFFFFFU) 1087 #define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_SHIFT (0U) 1088 /*! ACLK_CLR - Writing ones to this register clears the corresponding bit or bits in the 1089 * ASYNCAPBCLKCTRL register, if they are implemented. Bits that do not correspond to defined bits in 1090 * ASYNCAPBCLKCTRL are reserved and only zeroes should be written to them. 1091 */ 1092 #define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_MASK) 1093 /*! @} */ 1094 1095 /*! @name ASYNCAPBCLKSELA - Async APB clock source select A */ 1096 /*! @{ */ 1097 #define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_MASK (0x3U) 1098 #define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_SHIFT (0U) 1099 /*! SEL - Clock source for asynchronous clock source selector A 1100 * 0b00..Main clock 1101 * 0b01..FRO 12 MHz 1102 * 0b10..Reserved setting 1103 * 0b11..Reserved setting 1104 */ 1105 #define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_MASK) 1106 /*! @} */ 1107 1108 1109 /*! 1110 * @} 1111 */ /* end of group ASYNC_SYSCON_Register_Masks */ 1112 1113 1114 /* ASYNC_SYSCON - Peripheral instance base addresses */ 1115 /** Peripheral ASYNC_SYSCON base address */ 1116 #define ASYNC_SYSCON_BASE (0x40040000u) 1117 /** Peripheral ASYNC_SYSCON base pointer */ 1118 #define ASYNC_SYSCON ((ASYNC_SYSCON_Type *)ASYNC_SYSCON_BASE) 1119 /** Array initializer of ASYNC_SYSCON peripheral base addresses */ 1120 #define ASYNC_SYSCON_BASE_ADDRS { ASYNC_SYSCON_BASE } 1121 /** Array initializer of ASYNC_SYSCON peripheral base pointers */ 1122 #define ASYNC_SYSCON_BASE_PTRS { ASYNC_SYSCON } 1123 1124 /*! 1125 * @} 1126 */ /* end of group ASYNC_SYSCON_Peripheral_Access_Layer */ 1127 1128 1129 /* ---------------------------------------------------------------------------- 1130 -- CRC Peripheral Access Layer 1131 ---------------------------------------------------------------------------- */ 1132 1133 /*! 1134 * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer 1135 * @{ 1136 */ 1137 1138 /** CRC - Register Layout Typedef */ 1139 typedef struct { 1140 __IO uint32_t MODE; /**< CRC mode register, offset: 0x0 */ 1141 __IO uint32_t SEED; /**< CRC seed register, offset: 0x4 */ 1142 union { /* offset: 0x8 */ 1143 __I uint32_t SUM; /**< CRC checksum register, offset: 0x8 */ 1144 __O uint32_t WR_DATA; /**< CRC data register, offset: 0x8 */ 1145 }; 1146 } CRC_Type; 1147 1148 /* ---------------------------------------------------------------------------- 1149 -- CRC Register Masks 1150 ---------------------------------------------------------------------------- */ 1151 1152 /*! 1153 * @addtogroup CRC_Register_Masks CRC Register Masks 1154 * @{ 1155 */ 1156 1157 /*! @name MODE - CRC mode register */ 1158 /*! @{ */ 1159 #define CRC_MODE_CRC_POLY_MASK (0x3U) 1160 #define CRC_MODE_CRC_POLY_SHIFT (0U) 1161 /*! CRC_POLY - CRC polynomial: 1X = CRC-32 polynomial 01 = CRC-16 polynomial 00 = CRC-CCITT polynomial 1162 */ 1163 #define CRC_MODE_CRC_POLY(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CRC_POLY_SHIFT)) & CRC_MODE_CRC_POLY_MASK) 1164 #define CRC_MODE_BIT_RVS_WR_MASK (0x4U) 1165 #define CRC_MODE_BIT_RVS_WR_SHIFT (2U) 1166 /*! BIT_RVS_WR - Data bit order: 1 = Bit order reverse for CRC_WR_DATA (per byte) 0 = No bit order reverse for CRC_WR_DATA (per byte) 1167 */ 1168 #define CRC_MODE_BIT_RVS_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_WR_SHIFT)) & CRC_MODE_BIT_RVS_WR_MASK) 1169 #define CRC_MODE_CMPL_WR_MASK (0x8U) 1170 #define CRC_MODE_CMPL_WR_SHIFT (3U) 1171 /*! CMPL_WR - Data complement: 1 = 1's complement for CRC_WR_DATA 0 = No 1's complement for CRC_WR_DATA 1172 */ 1173 #define CRC_MODE_CMPL_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_WR_SHIFT)) & CRC_MODE_CMPL_WR_MASK) 1174 #define CRC_MODE_BIT_RVS_SUM_MASK (0x10U) 1175 #define CRC_MODE_BIT_RVS_SUM_SHIFT (4U) 1176 /*! BIT_RVS_SUM - CRC sum bit order: 1 = Bit order reverse for CRC_SUM 0 = No bit order reverse for CRC_SUM 1177 */ 1178 #define CRC_MODE_BIT_RVS_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_SUM_SHIFT)) & CRC_MODE_BIT_RVS_SUM_MASK) 1179 #define CRC_MODE_CMPL_SUM_MASK (0x20U) 1180 #define CRC_MODE_CMPL_SUM_SHIFT (5U) 1181 /*! CMPL_SUM - CRC sum complement: 1 = 1's complement for CRC_SUM 0 = No 1's complement for CRC_SUM 1182 */ 1183 #define CRC_MODE_CMPL_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_SUM_SHIFT)) & CRC_MODE_CMPL_SUM_MASK) 1184 /*! @} */ 1185 1186 /*! @name SEED - CRC seed register */ 1187 /*! @{ */ 1188 #define CRC_SEED_CRC_SEED_MASK (0xFFFFFFFFU) 1189 #define CRC_SEED_CRC_SEED_SHIFT (0U) 1190 /*! CRC_SEED - A write access to this register will load CRC seed value to CRC_SUM register with 1191 * selected bit order and 1's complement pre-processes. A write access to this register will 1192 * overrule the CRC calculation in progresses. 1193 */ 1194 #define CRC_SEED_CRC_SEED(x) (((uint32_t)(((uint32_t)(x)) << CRC_SEED_CRC_SEED_SHIFT)) & CRC_SEED_CRC_SEED_MASK) 1195 /*! @} */ 1196 1197 /*! @name SUM - CRC checksum register */ 1198 /*! @{ */ 1199 #define CRC_SUM_CRC_SUM_MASK (0xFFFFFFFFU) 1200 #define CRC_SUM_CRC_SUM_SHIFT (0U) 1201 /*! CRC_SUM - The most recent CRC sum can be read through this register with selected bit order and 1's complement post-processes. 1202 */ 1203 #define CRC_SUM_CRC_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_SUM_CRC_SUM_SHIFT)) & CRC_SUM_CRC_SUM_MASK) 1204 /*! @} */ 1205 1206 /*! @name WR_DATA - CRC data register */ 1207 /*! @{ */ 1208 #define CRC_WR_DATA_CRC_WR_DATA_MASK (0xFFFFFFFFU) 1209 #define CRC_WR_DATA_CRC_WR_DATA_SHIFT (0U) 1210 /*! CRC_WR_DATA - Data written to this register will be taken to perform CRC calculation with 1211 * selected bit order and 1's complement pre-process. Any write size 8, 16 or 32-bit are allowed and 1212 * accept back-to-back transactions. 1213 */ 1214 #define CRC_WR_DATA_CRC_WR_DATA(x) (((uint32_t)(((uint32_t)(x)) << CRC_WR_DATA_CRC_WR_DATA_SHIFT)) & CRC_WR_DATA_CRC_WR_DATA_MASK) 1215 /*! @} */ 1216 1217 1218 /*! 1219 * @} 1220 */ /* end of group CRC_Register_Masks */ 1221 1222 1223 /* CRC - Peripheral instance base addresses */ 1224 /** Peripheral CRC_ENGINE base address */ 1225 #define CRC_ENGINE_BASE (0x40095000u) 1226 /** Peripheral CRC_ENGINE base pointer */ 1227 #define CRC_ENGINE ((CRC_Type *)CRC_ENGINE_BASE) 1228 /** Array initializer of CRC peripheral base addresses */ 1229 #define CRC_BASE_ADDRS { CRC_ENGINE_BASE } 1230 /** Array initializer of CRC peripheral base pointers */ 1231 #define CRC_BASE_PTRS { CRC_ENGINE } 1232 1233 /*! 1234 * @} 1235 */ /* end of group CRC_Peripheral_Access_Layer */ 1236 1237 1238 /* ---------------------------------------------------------------------------- 1239 -- CTIMER Peripheral Access Layer 1240 ---------------------------------------------------------------------------- */ 1241 1242 /*! 1243 * @addtogroup CTIMER_Peripheral_Access_Layer CTIMER Peripheral Access Layer 1244 * @{ 1245 */ 1246 1247 /** CTIMER - Register Layout Typedef */ 1248 typedef struct { 1249 __IO uint32_t IR; /**< Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending., offset: 0x0 */ 1250 __IO uint32_t TCR; /**< Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR., offset: 0x4 */ 1251 __IO uint32_t TC; /**< Timer Counter. The 32 bit TC is incremented every PR+1 cycles of the APB bus clock. The TC is controlled through the TCR., offset: 0x8 */ 1252 __IO uint32_t PR; /**< Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC., offset: 0xC */ 1253 __IO uint32_t PC; /**< Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface., offset: 0x10 */ 1254 __IO uint32_t MCR; /**< Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs., offset: 0x14 */ 1255 __IO uint32_t MR[4]; /**< Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC., array offset: 0x18, array step: 0x4 */ 1256 __IO uint32_t CCR; /**< Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place., offset: 0x28 */ 1257 __I uint32_t CR[4]; /**< Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input., array offset: 0x2C, array step: 0x4 */ 1258 __IO uint32_t EMR; /**< External Match Register. The EMR controls the match function and the external match pins., offset: 0x3C */ 1259 uint8_t RESERVED_0[48]; 1260 __IO uint32_t CTCR; /**< Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting., offset: 0x70 */ 1261 __IO uint32_t PWMC; /**< PWM Control Register. The PWMCON enables PWM mode for the external match pins., offset: 0x74 */ 1262 } CTIMER_Type; 1263 1264 /* ---------------------------------------------------------------------------- 1265 -- CTIMER Register Masks 1266 ---------------------------------------------------------------------------- */ 1267 1268 /*! 1269 * @addtogroup CTIMER_Register_Masks CTIMER Register Masks 1270 * @{ 1271 */ 1272 1273 /*! @name IR - Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */ 1274 /*! @{ */ 1275 #define CTIMER_IR_MR0INT_MASK (0x1U) 1276 #define CTIMER_IR_MR0INT_SHIFT (0U) 1277 /*! MR0INT - Interrupt flag for match channel 0. 1278 */ 1279 #define CTIMER_IR_MR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR0INT_SHIFT)) & CTIMER_IR_MR0INT_MASK) 1280 #define CTIMER_IR_MR1INT_MASK (0x2U) 1281 #define CTIMER_IR_MR1INT_SHIFT (1U) 1282 /*! MR1INT - Interrupt flag for match channel 1. 1283 */ 1284 #define CTIMER_IR_MR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR1INT_SHIFT)) & CTIMER_IR_MR1INT_MASK) 1285 #define CTIMER_IR_MR2INT_MASK (0x4U) 1286 #define CTIMER_IR_MR2INT_SHIFT (2U) 1287 /*! MR2INT - Interrupt flag for match channel 2. 1288 */ 1289 #define CTIMER_IR_MR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR2INT_SHIFT)) & CTIMER_IR_MR2INT_MASK) 1290 #define CTIMER_IR_MR3INT_MASK (0x8U) 1291 #define CTIMER_IR_MR3INT_SHIFT (3U) 1292 /*! MR3INT - Interrupt flag for match channel 3. 1293 */ 1294 #define CTIMER_IR_MR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR3INT_SHIFT)) & CTIMER_IR_MR3INT_MASK) 1295 #define CTIMER_IR_CR0INT_MASK (0x10U) 1296 #define CTIMER_IR_CR0INT_SHIFT (4U) 1297 /*! CR0INT - Interrupt flag for capture channel 0 event. 1298 */ 1299 #define CTIMER_IR_CR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR0INT_SHIFT)) & CTIMER_IR_CR0INT_MASK) 1300 #define CTIMER_IR_CR1INT_MASK (0x20U) 1301 #define CTIMER_IR_CR1INT_SHIFT (5U) 1302 /*! CR1INT - Interrupt flag for capture channel 1 event. 1303 */ 1304 #define CTIMER_IR_CR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR1INT_SHIFT)) & CTIMER_IR_CR1INT_MASK) 1305 #define CTIMER_IR_CR2INT_MASK (0x40U) 1306 #define CTIMER_IR_CR2INT_SHIFT (6U) 1307 /*! CR2INT - Interrupt flag for capture channel 2 event. 1308 */ 1309 #define CTIMER_IR_CR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR2INT_SHIFT)) & CTIMER_IR_CR2INT_MASK) 1310 #define CTIMER_IR_CR3INT_MASK (0x80U) 1311 #define CTIMER_IR_CR3INT_SHIFT (7U) 1312 /*! CR3INT - Interrupt flag for capture channel 3 event. 1313 */ 1314 #define CTIMER_IR_CR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR3INT_SHIFT)) & CTIMER_IR_CR3INT_MASK) 1315 /*! @} */ 1316 1317 /*! @name TCR - Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */ 1318 /*! @{ */ 1319 #define CTIMER_TCR_CEN_MASK (0x1U) 1320 #define CTIMER_TCR_CEN_SHIFT (0U) 1321 /*! CEN - Counter enable. 1322 * 0b0..Disabled.The counters are disabled. 1323 * 0b1..Enabled. The Timer Counter and Prescale Counter are enabled. 1324 */ 1325 #define CTIMER_TCR_CEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CEN_SHIFT)) & CTIMER_TCR_CEN_MASK) 1326 #define CTIMER_TCR_CRST_MASK (0x2U) 1327 #define CTIMER_TCR_CRST_SHIFT (1U) 1328 /*! CRST - Counter reset. 1329 * 0b0..Disabled. Do nothing. 1330 * 0b1..Enabled. The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of 1331 * the APB bus clock. The counters remain reset until TCR[1] is returned to zero. 1332 */ 1333 #define CTIMER_TCR_CRST(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CRST_SHIFT)) & CTIMER_TCR_CRST_MASK) 1334 /*! @} */ 1335 1336 /*! @name TC - Timer Counter. The 32 bit TC is incremented every PR+1 cycles of the APB bus clock. The TC is controlled through the TCR. */ 1337 /*! @{ */ 1338 #define CTIMER_TC_TCVAL_MASK (0xFFFFFFFFU) 1339 #define CTIMER_TC_TCVAL_SHIFT (0U) 1340 /*! TCVAL - Timer counter value. 1341 */ 1342 #define CTIMER_TC_TCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TC_TCVAL_SHIFT)) & CTIMER_TC_TCVAL_MASK) 1343 /*! @} */ 1344 1345 /*! @name PR - Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC. */ 1346 /*! @{ */ 1347 #define CTIMER_PR_PRVAL_MASK (0xFFFFFFFFU) 1348 #define CTIMER_PR_PRVAL_SHIFT (0U) 1349 /*! PRVAL - Prescale counter value. 1350 */ 1351 #define CTIMER_PR_PRVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PR_PRVAL_SHIFT)) & CTIMER_PR_PRVAL_MASK) 1352 /*! @} */ 1353 1354 /*! @name PC - Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */ 1355 /*! @{ */ 1356 #define CTIMER_PC_PCVAL_MASK (0xFFFFFFFFU) 1357 #define CTIMER_PC_PCVAL_SHIFT (0U) 1358 /*! PCVAL - Prescale counter value. 1359 */ 1360 #define CTIMER_PC_PCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PC_PCVAL_SHIFT)) & CTIMER_PC_PCVAL_MASK) 1361 /*! @} */ 1362 1363 /*! @name MCR - Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */ 1364 /*! @{ */ 1365 #define CTIMER_MCR_MR0I_MASK (0x1U) 1366 #define CTIMER_MCR_MR0I_SHIFT (0U) 1367 /*! MR0I - Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. 0 = disabled. 1 = enabled. 1368 */ 1369 #define CTIMER_MCR_MR0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK) 1370 #define CTIMER_MCR_MR0R_MASK (0x2U) 1371 #define CTIMER_MCR_MR0R_SHIFT (1U) 1372 /*! MR0R - Reset on MR0: the TC will be reset if MR0 matches it. 0 = disabled. 1 = enabled. 1373 */ 1374 #define CTIMER_MCR_MR0R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0R_SHIFT)) & CTIMER_MCR_MR0R_MASK) 1375 #define CTIMER_MCR_MR0S_MASK (0x4U) 1376 #define CTIMER_MCR_MR0S_SHIFT (2U) 1377 /*! MR0S - Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. 0 = disabled. 1 = enabled. 1378 */ 1379 #define CTIMER_MCR_MR0S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0S_SHIFT)) & CTIMER_MCR_MR0S_MASK) 1380 #define CTIMER_MCR_MR1I_MASK (0x8U) 1381 #define CTIMER_MCR_MR1I_SHIFT (3U) 1382 /*! MR1I - Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. 0 = 1383 * disabled. 1 = enabled. 0 = disabled. 1 = enabled. 1384 */ 1385 #define CTIMER_MCR_MR1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1I_SHIFT)) & CTIMER_MCR_MR1I_MASK) 1386 #define CTIMER_MCR_MR1R_MASK (0x10U) 1387 #define CTIMER_MCR_MR1R_SHIFT (4U) 1388 /*! MR1R - Reset on MR1: the TC will be reset if MR1 matches it. 0 = disabled. 1 = enabled. 1389 */ 1390 #define CTIMER_MCR_MR1R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1R_SHIFT)) & CTIMER_MCR_MR1R_MASK) 1391 #define CTIMER_MCR_MR1S_MASK (0x20U) 1392 #define CTIMER_MCR_MR1S_SHIFT (5U) 1393 /*! MR1S - Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. 0 = disabled. 1 = enabled. 1394 */ 1395 #define CTIMER_MCR_MR1S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1S_SHIFT)) & CTIMER_MCR_MR1S_MASK) 1396 #define CTIMER_MCR_MR2I_MASK (0x40U) 1397 #define CTIMER_MCR_MR2I_SHIFT (6U) 1398 /*! MR2I - Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. 0 = disabled. 1 = enabled. 1399 */ 1400 #define CTIMER_MCR_MR2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2I_SHIFT)) & CTIMER_MCR_MR2I_MASK) 1401 #define CTIMER_MCR_MR2R_MASK (0x80U) 1402 #define CTIMER_MCR_MR2R_SHIFT (7U) 1403 /*! MR2R - Reset on MR2: the TC will be reset if MR2 matches it. 0 = disabled. 1 = enabled. 1404 */ 1405 #define CTIMER_MCR_MR2R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2R_SHIFT)) & CTIMER_MCR_MR2R_MASK) 1406 #define CTIMER_MCR_MR2S_MASK (0x100U) 1407 #define CTIMER_MCR_MR2S_SHIFT (8U) 1408 /*! MR2S - Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. 0 = disabled. 1 = enabled. 1409 */ 1410 #define CTIMER_MCR_MR2S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2S_SHIFT)) & CTIMER_MCR_MR2S_MASK) 1411 #define CTIMER_MCR_MR3I_MASK (0x200U) 1412 #define CTIMER_MCR_MR3I_SHIFT (9U) 1413 /*! MR3I - Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. 0 = disabled. 1 = enabled. 1414 */ 1415 #define CTIMER_MCR_MR3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3I_SHIFT)) & CTIMER_MCR_MR3I_MASK) 1416 #define CTIMER_MCR_MR3R_MASK (0x400U) 1417 #define CTIMER_MCR_MR3R_SHIFT (10U) 1418 /*! MR3R - Reset on MR3: the TC will be reset if MR3 matches it. 0 = disabled. 1 = enabled. 1419 */ 1420 #define CTIMER_MCR_MR3R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3R_SHIFT)) & CTIMER_MCR_MR3R_MASK) 1421 #define CTIMER_MCR_MR3S_MASK (0x800U) 1422 #define CTIMER_MCR_MR3S_SHIFT (11U) 1423 /*! MR3S - Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. 0 = disabled. 1 = enabled. 1424 */ 1425 #define CTIMER_MCR_MR3S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3S_SHIFT)) & CTIMER_MCR_MR3S_MASK) 1426 /*! @} */ 1427 1428 /*! @name MR - Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */ 1429 /*! @{ */ 1430 #define CTIMER_MR_MATCH_MASK (0xFFFFFFFFU) 1431 #define CTIMER_MR_MATCH_SHIFT (0U) 1432 /*! MATCH - Timer counter match value. 1433 */ 1434 #define CTIMER_MR_MATCH(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MR_MATCH_SHIFT)) & CTIMER_MR_MATCH_MASK) 1435 /*! @} */ 1436 1437 /* The count of CTIMER_MR */ 1438 #define CTIMER_MR_COUNT (4U) 1439 1440 /*! @name CCR - Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */ 1441 /*! @{ */ 1442 #define CTIMER_CCR_CAP0RE_MASK (0x1U) 1443 #define CTIMER_CCR_CAP0RE_SHIFT (0U) 1444 /*! CAP0RE - Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with 1445 * the contents of TC. 0 = disabled. 1 = enabled. 1446 */ 1447 #define CTIMER_CCR_CAP0RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0RE_SHIFT)) & CTIMER_CCR_CAP0RE_MASK) 1448 #define CTIMER_CCR_CAP0FE_MASK (0x2U) 1449 #define CTIMER_CCR_CAP0FE_SHIFT (1U) 1450 /*! CAP0FE - Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with 1451 * the contents of TC. 0 = disabled. 1 = enabled. 1452 */ 1453 #define CTIMER_CCR_CAP0FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0FE_SHIFT)) & CTIMER_CCR_CAP0FE_MASK) 1454 #define CTIMER_CCR_CAP0I_MASK (0x4U) 1455 #define CTIMER_CCR_CAP0I_SHIFT (2U) 1456 /*! CAP0I - Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt. 1457 */ 1458 #define CTIMER_CCR_CAP0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK) 1459 #define CTIMER_CCR_CAP1RE_MASK (0x8U) 1460 #define CTIMER_CCR_CAP1RE_SHIFT (3U) 1461 /*! CAP1RE - Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with 1462 * the contents of TC. 0 = disabled. 1 = enabled. 1463 */ 1464 #define CTIMER_CCR_CAP1RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1RE_SHIFT)) & CTIMER_CCR_CAP1RE_MASK) 1465 #define CTIMER_CCR_CAP1FE_MASK (0x10U) 1466 #define CTIMER_CCR_CAP1FE_SHIFT (4U) 1467 /*! CAP1FE - Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with 1468 * the contents of TC. 0 = disabled. 1 = enabled. 1469 */ 1470 #define CTIMER_CCR_CAP1FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1FE_SHIFT)) & CTIMER_CCR_CAP1FE_MASK) 1471 #define CTIMER_CCR_CAP1I_MASK (0x20U) 1472 #define CTIMER_CCR_CAP1I_SHIFT (5U) 1473 /*! CAP1I - Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt. 1474 */ 1475 #define CTIMER_CCR_CAP1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1I_SHIFT)) & CTIMER_CCR_CAP1I_MASK) 1476 #define CTIMER_CCR_CAP2RE_MASK (0x40U) 1477 #define CTIMER_CCR_CAP2RE_SHIFT (6U) 1478 /*! CAP2RE - Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with 1479 * the contents of TC. 0 = disabled. 1 = enabled. 1480 */ 1481 #define CTIMER_CCR_CAP2RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2RE_SHIFT)) & CTIMER_CCR_CAP2RE_MASK) 1482 #define CTIMER_CCR_CAP2FE_MASK (0x80U) 1483 #define CTIMER_CCR_CAP2FE_SHIFT (7U) 1484 /*! CAP2FE - Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with 1485 * the contents of TC. 0 = disabled. 1 = enabled. 1486 */ 1487 #define CTIMER_CCR_CAP2FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2FE_SHIFT)) & CTIMER_CCR_CAP2FE_MASK) 1488 #define CTIMER_CCR_CAP2I_MASK (0x100U) 1489 #define CTIMER_CCR_CAP2I_SHIFT (8U) 1490 /*! CAP2I - Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt. 1491 */ 1492 #define CTIMER_CCR_CAP2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2I_SHIFT)) & CTIMER_CCR_CAP2I_MASK) 1493 #define CTIMER_CCR_CAP3RE_MASK (0x200U) 1494 #define CTIMER_CCR_CAP3RE_SHIFT (9U) 1495 /*! CAP3RE - Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with 1496 * the contents of TC. 0 = disabled. 1 = enabled. 1497 */ 1498 #define CTIMER_CCR_CAP3RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3RE_SHIFT)) & CTIMER_CCR_CAP3RE_MASK) 1499 #define CTIMER_CCR_CAP3FE_MASK (0x400U) 1500 #define CTIMER_CCR_CAP3FE_SHIFT (10U) 1501 /*! CAP3FE - Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with 1502 * the contents of TC. 0 = disabled. 1 = enabled. 1503 */ 1504 #define CTIMER_CCR_CAP3FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3FE_SHIFT)) & CTIMER_CCR_CAP3FE_MASK) 1505 #define CTIMER_CCR_CAP3I_MASK (0x800U) 1506 #define CTIMER_CCR_CAP3I_SHIFT (11U) 1507 /*! CAP3I - Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt. 1508 */ 1509 #define CTIMER_CCR_CAP3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3I_SHIFT)) & CTIMER_CCR_CAP3I_MASK) 1510 /*! @} */ 1511 1512 /*! @name CR - Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input. */ 1513 /*! @{ */ 1514 #define CTIMER_CR_CAP_MASK (0xFFFFFFFFU) 1515 #define CTIMER_CR_CAP_SHIFT (0U) 1516 /*! CAP - Timer counter capture value. 1517 */ 1518 #define CTIMER_CR_CAP(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CR_CAP_SHIFT)) & CTIMER_CR_CAP_MASK) 1519 /*! @} */ 1520 1521 /* The count of CTIMER_CR */ 1522 #define CTIMER_CR_COUNT (4U) 1523 1524 /*! @name EMR - External Match Register. The EMR controls the match function and the external match pins. */ 1525 /*! @{ */ 1526 #define CTIMER_EMR_EM0_MASK (0x1U) 1527 #define CTIMER_EMR_EM0_SHIFT (0U) 1528 /*! EM0 - External Match 0. This bit reflects the state of output MAT0, whether or not this output 1529 * is connected to a pin. When a match occurs between the TC and MR0, this bit can either toggle, 1530 * go LOW, go HIGH, or do nothing, as selected by EMR[5:4]. This bit is driven to the MAT pins if 1531 * the match function is selected via IOCON. 0 = LOW. 1 = HIGH. 1532 */ 1533 #define CTIMER_EMR_EM0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM0_SHIFT)) & CTIMER_EMR_EM0_MASK) 1534 #define CTIMER_EMR_EM1_MASK (0x2U) 1535 #define CTIMER_EMR_EM1_SHIFT (1U) 1536 /*! EM1 - External Match 1. This bit reflects the state of output MAT1, whether or not this output 1537 * is connected to a pin. When a match occurs between the TC and MR1, this bit can either toggle, 1538 * go LOW, go HIGH, or do nothing, as selected by EMR[7:6]. This bit is driven to the MAT pins if 1539 * the match function is selected via IOCON. 0 = LOW. 1 = HIGH. 1540 */ 1541 #define CTIMER_EMR_EM1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM1_SHIFT)) & CTIMER_EMR_EM1_MASK) 1542 #define CTIMER_EMR_EM2_MASK (0x4U) 1543 #define CTIMER_EMR_EM2_SHIFT (2U) 1544 /*! EM2 - External Match 2. This bit reflects the state of output MAT2, whether or not this output 1545 * is connected to a pin. When a match occurs between the TC and MR2, this bit can either toggle, 1546 * go LOW, go HIGH, or do nothing, as selected by EMR[9:8]. This bit is driven to the MAT pins if 1547 * the match function is selected via IOCON. 0 = LOW. 1 = HIGH. 1548 */ 1549 #define CTIMER_EMR_EM2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM2_SHIFT)) & CTIMER_EMR_EM2_MASK) 1550 #define CTIMER_EMR_EM3_MASK (0x8U) 1551 #define CTIMER_EMR_EM3_SHIFT (3U) 1552 /*! EM3 - External Match 3. This bit reflects the state of output MAT3, whether or not this output 1553 * is connected to a pin. When a match occurs between the TC and MR3, this bit can either toggle, 1554 * go LOW, go HIGH, or do nothing, as selected by MR[11:10]. This bit is driven to the MAT pins 1555 * if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. 1556 */ 1557 #define CTIMER_EMR_EM3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM3_SHIFT)) & CTIMER_EMR_EM3_MASK) 1558 #define CTIMER_EMR_EMC0_MASK (0x30U) 1559 #define CTIMER_EMR_EMC0_SHIFT (4U) 1560 /*! EMC0 - External Match Control 0. Determines the functionality of External Match 0. 1561 * 0b00..Do Nothing. 1562 * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT0 pin is LOW if pinned out). 1563 * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT0 pin is HIGH if pinned out). 1564 * 0b11..Toggle. Toggle the corresponding External Match bit/output. 1565 */ 1566 #define CTIMER_EMR_EMC0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC0_SHIFT)) & CTIMER_EMR_EMC0_MASK) 1567 #define CTIMER_EMR_EMC1_MASK (0xC0U) 1568 #define CTIMER_EMR_EMC1_SHIFT (6U) 1569 /*! EMC1 - External Match Control 1. Determines the functionality of External Match 1. 1570 * 0b00..Do Nothing. 1571 * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT1 pin is LOW if pinned out). 1572 * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT1 pin is HIGH if pinned out). 1573 * 0b11..Toggle. Toggle the corresponding External Match bit/output. 1574 */ 1575 #define CTIMER_EMR_EMC1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC1_SHIFT)) & CTIMER_EMR_EMC1_MASK) 1576 #define CTIMER_EMR_EMC2_MASK (0x300U) 1577 #define CTIMER_EMR_EMC2_SHIFT (8U) 1578 /*! EMC2 - External Match Control 2. Determines the functionality of External Match 2. 1579 * 0b00..Do Nothing. 1580 * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT2 pin is LOW if pinned out). 1581 * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT2 pin is HIGH if pinned out). 1582 * 0b11..Toggle. Toggle the corresponding External Match bit/output. 1583 */ 1584 #define CTIMER_EMR_EMC2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC2_SHIFT)) & CTIMER_EMR_EMC2_MASK) 1585 #define CTIMER_EMR_EMC3_MASK (0xC00U) 1586 #define CTIMER_EMR_EMC3_SHIFT (10U) 1587 /*! EMC3 - External Match Control 3. Determines the functionality of External Match 3. 1588 * 0b00..Do Nothing. 1589 * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT3 pin is LOW if pinned out). 1590 * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT3 pin is HIGH if pinned out). 1591 * 0b11..Toggle. Toggle the corresponding External Match bit/output. 1592 */ 1593 #define CTIMER_EMR_EMC3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC3_SHIFT)) & CTIMER_EMR_EMC3_MASK) 1594 /*! @} */ 1595 1596 /*! @name CTCR - Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */ 1597 /*! @{ */ 1598 #define CTIMER_CTCR_CTMODE_MASK (0x3U) 1599 #define CTIMER_CTCR_CTMODE_SHIFT (0U) 1600 /*! CTMODE - Counter/Timer Mode This field selects which rising APB bus clock edges can increment 1601 * Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC 1602 * is incremented when the Prescale Counter matches the Prescale Register. 1603 * 0b00..Timer Mode. Incremented every rising APB bus clock edge. 1604 * 0b01..Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2. 1605 * 0b10..Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2. 1606 * 0b11..Counter Mode dual edge. TC is incremented on both edges on the CAP input selected by bits 3:2. 1607 */ 1608 #define CTIMER_CTCR_CTMODE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CTMODE_SHIFT)) & CTIMER_CTCR_CTMODE_MASK) 1609 #define CTIMER_CTCR_CINSEL_MASK (0xCU) 1610 #define CTIMER_CTCR_CINSEL_SHIFT (2U) 1611 /*! CINSEL - Count Input Select When bits 1:0 in this register are not 00, these bits select which 1612 * CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input 1613 * in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be 1614 * programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the 1615 * same timer. 1616 * 0b00..Channel 0. CAPn.0 for CTIMERn 1617 * 0b01..Channel 1. CAPn.1 for CTIMERn 1618 * 0b10..Channel 2. CAPn.2 for CTIMERn 1619 * 0b11..Channel 3. CAPn.3 for CTIMERn 1620 */ 1621 #define CTIMER_CTCR_CINSEL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CINSEL_SHIFT)) & CTIMER_CTCR_CINSEL_MASK) 1622 #define CTIMER_CTCR_ENCC_MASK (0x10U) 1623 #define CTIMER_CTCR_ENCC_SHIFT (4U) 1624 /*! ENCC - Setting this bit to 1 enables clearing of the timer and the prescaler when the 1625 * capture-edge event specified in bits 7:5 occurs. 1626 */ 1627 #define CTIMER_CTCR_ENCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_ENCC_SHIFT)) & CTIMER_CTCR_ENCC_MASK) 1628 #define CTIMER_CTCR_SELCC_MASK (0xE0U) 1629 #define CTIMER_CTCR_SELCC_SHIFT (5U) 1630 /*! SELCC - Edge select. When bit 4 is 1, these bits select which capture input edge will cause the 1631 * timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 1632 * 0x3 and 0x6 to 0x7 are reserved. 1633 * 0b000..Channel 0 Rising Edge. Rising edge of the signal on capture channel 0 clears the timer (if bit 4 is set). 1634 * 0b001..Channel 0 Falling Edge. Falling edge of the signal on capture channel 0 clears the timer (if bit 4 is set). 1635 * 0b010..Channel 1 Rising Edge. Rising edge of the signal on capture channel 1 clears the timer (if bit 4 is set). 1636 * 0b011..Channel 1 Falling Edge. Falling edge of the signal on capture channel 1 clears the timer (if bit 4 is set). 1637 * 0b100..Channel 2 Rising Edge. Rising edge of the signal on capture channel 2 clears the timer (if bit 4 is set). 1638 * 0b101..Channel 2 Falling Edge. Falling edge of the signal on capture channel 2 clears the timer (if bit 4 is set). 1639 */ 1640 #define CTIMER_CTCR_SELCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_SELCC_SHIFT)) & CTIMER_CTCR_SELCC_MASK) 1641 /*! @} */ 1642 1643 /*! @name PWMC - PWM Control Register. The PWMCON enables PWM mode for the external match pins. */ 1644 /*! @{ */ 1645 #define CTIMER_PWMC_PWMEN0_MASK (0x1U) 1646 #define CTIMER_PWMC_PWMEN0_SHIFT (0U) 1647 /*! PWMEN0 - PWM mode enable for channel0. 1648 * 0b0..Match. CTIMERn_MAT0 is controlled by EM0. 1649 * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT0. 1650 */ 1651 #define CTIMER_PWMC_PWMEN0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN0_SHIFT)) & CTIMER_PWMC_PWMEN0_MASK) 1652 #define CTIMER_PWMC_PWMEN1_MASK (0x2U) 1653 #define CTIMER_PWMC_PWMEN1_SHIFT (1U) 1654 /*! PWMEN1 - PWM mode enable for channel1. 1655 * 0b0..Match. CTIMERn_MAT01 is controlled by EM1. 1656 * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT1. 1657 */ 1658 #define CTIMER_PWMC_PWMEN1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN1_SHIFT)) & CTIMER_PWMC_PWMEN1_MASK) 1659 #define CTIMER_PWMC_PWMEN2_MASK (0x4U) 1660 #define CTIMER_PWMC_PWMEN2_SHIFT (2U) 1661 /*! PWMEN2 - PWM mode enable for channel2. 1662 * 0b0..Match. CTIMERn_MAT2 is controlled by EM2. 1663 * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT2. 1664 */ 1665 #define CTIMER_PWMC_PWMEN2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN2_SHIFT)) & CTIMER_PWMC_PWMEN2_MASK) 1666 #define CTIMER_PWMC_PWMEN3_MASK (0x8U) 1667 #define CTIMER_PWMC_PWMEN3_SHIFT (3U) 1668 /*! PWMEN3 - PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle. 1669 * 0b0..Match. CTIMERn_MAT3 is controlled by EM3. 1670 * 0b1..PWM. PWM mode is enabled for CT132Bn_MAT3. 1671 */ 1672 #define CTIMER_PWMC_PWMEN3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN3_SHIFT)) & CTIMER_PWMC_PWMEN3_MASK) 1673 /*! @} */ 1674 1675 1676 /*! 1677 * @} 1678 */ /* end of group CTIMER_Register_Masks */ 1679 1680 1681 /* CTIMER - Peripheral instance base addresses */ 1682 /** Peripheral CTIMER0 base address */ 1683 #define CTIMER0_BASE (0x40008000u) 1684 /** Peripheral CTIMER0 base pointer */ 1685 #define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) 1686 /** Peripheral CTIMER1 base address */ 1687 #define CTIMER1_BASE (0x40009000u) 1688 /** Peripheral CTIMER1 base pointer */ 1689 #define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) 1690 /** Peripheral CTIMER2 base address */ 1691 #define CTIMER2_BASE (0x40028000u) 1692 /** Peripheral CTIMER2 base pointer */ 1693 #define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) 1694 /** Peripheral CTIMER3 base address */ 1695 #define CTIMER3_BASE (0x40048000u) 1696 /** Peripheral CTIMER3 base pointer */ 1697 #define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) 1698 /** Peripheral CTIMER4 base address */ 1699 #define CTIMER4_BASE (0x40049000u) 1700 /** Peripheral CTIMER4 base pointer */ 1701 #define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) 1702 /** Array initializer of CTIMER peripheral base addresses */ 1703 #define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } 1704 /** Array initializer of CTIMER peripheral base pointers */ 1705 #define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } 1706 /** Interrupt vectors for the CTIMER peripheral type */ 1707 #define CTIMER_IRQS { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn, CTIMER4_IRQn } 1708 1709 /*! 1710 * @} 1711 */ /* end of group CTIMER_Peripheral_Access_Layer */ 1712 1713 1714 /* ---------------------------------------------------------------------------- 1715 -- DMA Peripheral Access Layer 1716 ---------------------------------------------------------------------------- */ 1717 1718 /*! 1719 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer 1720 * @{ 1721 */ 1722 1723 /** DMA - Register Layout Typedef */ 1724 typedef struct { 1725 __IO uint32_t CTRL; /**< DMA control., offset: 0x0 */ 1726 __I uint32_t INTSTAT; /**< Interrupt status., offset: 0x4 */ 1727 __IO uint32_t SRAMBASE; /**< SRAM address of the channel configuration table., offset: 0x8 */ 1728 uint8_t RESERVED_0[20]; 1729 struct { /* offset: 0x20, array step: 0x5C */ 1730 __IO uint32_t ENABLESET; /**< Channel Enable read and Set for all DMA channels., array offset: 0x20, array step: 0x5C */ 1731 uint8_t RESERVED_0[4]; 1732 __O uint32_t ENABLECLR; /**< Channel Enable Clear for all DMA channels., array offset: 0x28, array step: 0x5C */ 1733 uint8_t RESERVED_1[4]; 1734 __I uint32_t ACTIVE; /**< Channel Active status for all DMA channels., array offset: 0x30, array step: 0x5C */ 1735 uint8_t RESERVED_2[4]; 1736 __I uint32_t BUSY; /**< Channel Busy status for all DMA channels., array offset: 0x38, array step: 0x5C */ 1737 uint8_t RESERVED_3[4]; 1738 __IO uint32_t ERRINT; /**< Error Interrupt status for all DMA channels., array offset: 0x40, array step: 0x5C */ 1739 uint8_t RESERVED_4[4]; 1740 __IO uint32_t INTENSET; /**< Interrupt Enable read and Set for all DMA channels., array offset: 0x48, array step: 0x5C */ 1741 uint8_t RESERVED_5[4]; 1742 __O uint32_t INTENCLR; /**< Interrupt Enable Clear for all DMA channels., array offset: 0x50, array step: 0x5C */ 1743 uint8_t RESERVED_6[4]; 1744 __IO uint32_t INTA; /**< Interrupt A status for all DMA channels., array offset: 0x58, array step: 0x5C */ 1745 uint8_t RESERVED_7[4]; 1746 __IO uint32_t INTB; /**< Interrupt B status for all DMA channels., array offset: 0x60, array step: 0x5C */ 1747 uint8_t RESERVED_8[4]; 1748 __O uint32_t SETVALID; /**< Set ValidPending control bits for all DMA channels., array offset: 0x68, array step: 0x5C */ 1749 uint8_t RESERVED_9[4]; 1750 __O uint32_t SETTRIG; /**< Set Trigger control bits for all DMA channels., array offset: 0x70, array step: 0x5C */ 1751 uint8_t RESERVED_10[4]; 1752 __O uint32_t ABORT; /**< Channel Abort control for all DMA channels., array offset: 0x78, array step: 0x5C */ 1753 } COMMON[1]; 1754 uint8_t RESERVED_1[900]; 1755 struct { /* offset: 0x400, array step: 0x10 */ 1756 __IO uint32_t CFG; /**< Configuration register for DMA channel ., array offset: 0x400, array step: 0x10 */ 1757 __I uint32_t CTLSTAT; /**< Control and status register for DMA channel ., array offset: 0x404, array step: 0x10 */ 1758 __IO uint32_t XFERCFG; /**< Transfer configuration register for DMA channel ., array offset: 0x408, array step: 0x10 */ 1759 uint8_t RESERVED_0[4]; 1760 } CHANNEL[20]; 1761 } DMA_Type; 1762 1763 /* ---------------------------------------------------------------------------- 1764 -- DMA Register Masks 1765 ---------------------------------------------------------------------------- */ 1766 1767 /*! 1768 * @addtogroup DMA_Register_Masks DMA Register Masks 1769 * @{ 1770 */ 1771 1772 /*! @name CTRL - DMA control. */ 1773 /*! @{ */ 1774 #define DMA_CTRL_ENABLE_MASK (0x1U) 1775 #define DMA_CTRL_ENABLE_SHIFT (0U) 1776 /*! ENABLE - DMA controller master enable. 1777 * 0b0..Disabled. The DMA controller is disabled. This clears any triggers that were asserted at the point when 1778 * disabled, but does not prevent re-triggering when the DMA controller is re-enabled. 1779 * 0b1..Enabled. The DMA controller is enabled. 1780 */ 1781 #define DMA_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CTRL_ENABLE_SHIFT)) & DMA_CTRL_ENABLE_MASK) 1782 /*! @} */ 1783 1784 /*! @name INTSTAT - Interrupt status. */ 1785 /*! @{ */ 1786 #define DMA_INTSTAT_ACTIVEINT_MASK (0x2U) 1787 #define DMA_INTSTAT_ACTIVEINT_SHIFT (1U) 1788 /*! ACTIVEINT - Summarizes whether any enabled interrupts (other than error interrupts) are pending. 1789 * 0b0..Not pending. No enabled interrupts are pending. 1790 * 0b1..Pending. At least one enabled interrupt is pending. 1791 */ 1792 #define DMA_INTSTAT_ACTIVEINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEINT_SHIFT)) & DMA_INTSTAT_ACTIVEINT_MASK) 1793 #define DMA_INTSTAT_ACTIVEERRINT_MASK (0x4U) 1794 #define DMA_INTSTAT_ACTIVEERRINT_SHIFT (2U) 1795 /*! ACTIVEERRINT - Summarizes whether any error interrupts are pending. 1796 * 0b0..Not pending. No error interrupts are pending. 1797 * 0b1..Pending. At least one error interrupt is pending. 1798 */ 1799 #define DMA_INTSTAT_ACTIVEERRINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEERRINT_SHIFT)) & DMA_INTSTAT_ACTIVEERRINT_MASK) 1800 /*! @} */ 1801 1802 /*! @name SRAMBASE - SRAM address of the channel configuration table. */ 1803 /*! @{ */ 1804 #define DMA_SRAMBASE_OFFSET_MASK (0xFFFFFE00U) 1805 #define DMA_SRAMBASE_OFFSET_SHIFT (9U) 1806 /*! OFFSET - Address bits 31:9 of the beginning of the DMA descriptor table. For 18 channels, the 1807 * table must begin on a 512 byte boundary. 1808 */ 1809 #define DMA_SRAMBASE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DMA_SRAMBASE_OFFSET_SHIFT)) & DMA_SRAMBASE_OFFSET_MASK) 1810 /*! @} */ 1811 1812 /*! @name COMMON_ENABLESET - Channel Enable read and Set for all DMA channels. */ 1813 /*! @{ */ 1814 #define DMA_COMMON_ENABLESET_ENA_MASK (0xFFFFFFFFU) 1815 #define DMA_COMMON_ENABLESET_ENA_SHIFT (0U) 1816 /*! ENA - Enable for DMA channels. Bit n enables or disables DMA channel n. The number of bits = 1817 * number of DMA channels in this device. Other bits are reserved. 0 = disabled. 1 = enabled. 1818 */ 1819 #define DMA_COMMON_ENABLESET_ENA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENA_SHIFT)) & DMA_COMMON_ENABLESET_ENA_MASK) 1820 /*! @} */ 1821 1822 /* The count of DMA_COMMON_ENABLESET */ 1823 #define DMA_COMMON_ENABLESET_COUNT (1U) 1824 1825 /*! @name COMMON_ENABLECLR - Channel Enable Clear for all DMA channels. */ 1826 /*! @{ */ 1827 #define DMA_COMMON_ENABLECLR_CLR_MASK (0xFFFFFFFFU) 1828 #define DMA_COMMON_ENABLECLR_CLR_SHIFT (0U) 1829 /*! CLR - Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears 1830 * the channel enable bit n. The number of bits = number of DMA channels in this device. Other bits 1831 * are reserved. 1832 */ 1833 #define DMA_COMMON_ENABLECLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR_SHIFT)) & DMA_COMMON_ENABLECLR_CLR_MASK) 1834 /*! @} */ 1835 1836 /* The count of DMA_COMMON_ENABLECLR */ 1837 #define DMA_COMMON_ENABLECLR_COUNT (1U) 1838 1839 /*! @name COMMON_ACTIVE - Channel Active status for all DMA channels. */ 1840 /*! @{ */ 1841 #define DMA_COMMON_ACTIVE_ACT_MASK (0xFFFFFFFFU) 1842 #define DMA_COMMON_ACTIVE_ACT_SHIFT (0U) 1843 /*! ACT - Active flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = 1844 * number of DMA channels in this device. Other bits are reserved. 0 = not active. 1 = active. 1845 */ 1846 #define DMA_COMMON_ACTIVE_ACT(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACT_SHIFT)) & DMA_COMMON_ACTIVE_ACT_MASK) 1847 /*! @} */ 1848 1849 /* The count of DMA_COMMON_ACTIVE */ 1850 #define DMA_COMMON_ACTIVE_COUNT (1U) 1851 1852 /*! @name COMMON_BUSY - Channel Busy status for all DMA channels. */ 1853 /*! @{ */ 1854 #define DMA_COMMON_BUSY_BSY_MASK (0xFFFFFFFFU) 1855 #define DMA_COMMON_BUSY_BSY_SHIFT (0U) 1856 /*! BSY - Busy flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = 1857 * number of DMA channels in this device. Other bits are reserved. 0 = not busy. 1 = busy. 1858 */ 1859 #define DMA_COMMON_BUSY_BSY(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BSY_SHIFT)) & DMA_COMMON_BUSY_BSY_MASK) 1860 /*! @} */ 1861 1862 /* The count of DMA_COMMON_BUSY */ 1863 #define DMA_COMMON_BUSY_COUNT (1U) 1864 1865 /*! @name COMMON_ERRINT - Error Interrupt status for all DMA channels. */ 1866 /*! @{ */ 1867 #define DMA_COMMON_ERRINT_ERR_MASK (0xFFFFFFFFU) 1868 #define DMA_COMMON_ERRINT_ERR_SHIFT (0U) 1869 /*! ERR - Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. The number of 1870 * bits = number of DMA channels in this device. Other bits are reserved. 0 = error interrupt is 1871 * not active. 1 = error interrupt is active. 1872 */ 1873 #define DMA_COMMON_ERRINT_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR_SHIFT)) & DMA_COMMON_ERRINT_ERR_MASK) 1874 /*! @} */ 1875 1876 /* The count of DMA_COMMON_ERRINT */ 1877 #define DMA_COMMON_ERRINT_COUNT (1U) 1878 1879 /*! @name COMMON_INTENSET - Interrupt Enable read and Set for all DMA channels. */ 1880 /*! @{ */ 1881 #define DMA_COMMON_INTENSET_INTEN_MASK (0xFFFFFFFFU) 1882 #define DMA_COMMON_INTENSET_INTEN_SHIFT (0U) 1883 /*! INTEN - Interrupt Enable read and set for DMA channel n. Bit n corresponds to DMA channel n. The 1884 * number of bits = number of DMA channels in this device. Other bits are reserved. 0 = 1885 * interrupt for DMA channel is disabled. 1 = interrupt for DMA channel is enabled. 1886 */ 1887 #define DMA_COMMON_INTENSET_INTEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN_SHIFT)) & DMA_COMMON_INTENSET_INTEN_MASK) 1888 /*! @} */ 1889 1890 /* The count of DMA_COMMON_INTENSET */ 1891 #define DMA_COMMON_INTENSET_COUNT (1U) 1892 1893 /*! @name COMMON_INTENCLR - Interrupt Enable Clear for all DMA channels. */ 1894 /*! @{ */ 1895 #define DMA_COMMON_INTENCLR_CLR_MASK (0xFFFFFFFFU) 1896 #define DMA_COMMON_INTENCLR_CLR_SHIFT (0U) 1897 /*! CLR - Writing ones to this register clears corresponding bits in the INTENSET0. Bit n 1898 * corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are 1899 * reserved. 1900 */ 1901 #define DMA_COMMON_INTENCLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR_SHIFT)) & DMA_COMMON_INTENCLR_CLR_MASK) 1902 /*! @} */ 1903 1904 /* The count of DMA_COMMON_INTENCLR */ 1905 #define DMA_COMMON_INTENCLR_COUNT (1U) 1906 1907 /*! @name COMMON_INTA - Interrupt A status for all DMA channels. */ 1908 /*! @{ */ 1909 #define DMA_COMMON_INTA_IA_MASK (0xFFFFFFFFU) 1910 #define DMA_COMMON_INTA_IA_SHIFT (0U) 1911 /*! IA - Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. The number of 1912 * bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel 1913 * interrupt A is not active. 1 = the DMA channel interrupt A is active. 1914 */ 1915 #define DMA_COMMON_INTA_IA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_IA_SHIFT)) & DMA_COMMON_INTA_IA_MASK) 1916 /*! @} */ 1917 1918 /* The count of DMA_COMMON_INTA */ 1919 #define DMA_COMMON_INTA_COUNT (1U) 1920 1921 /*! @name COMMON_INTB - Interrupt B status for all DMA channels. */ 1922 /*! @{ */ 1923 #define DMA_COMMON_INTB_IB_MASK (0xFFFFFFFFU) 1924 #define DMA_COMMON_INTB_IB_SHIFT (0U) 1925 /*! IB - Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. The number of 1926 * bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel 1927 * interrupt B is not active. 1 = the DMA channel interrupt B is active. 1928 */ 1929 #define DMA_COMMON_INTB_IB(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_IB_SHIFT)) & DMA_COMMON_INTB_IB_MASK) 1930 /*! @} */ 1931 1932 /* The count of DMA_COMMON_INTB */ 1933 #define DMA_COMMON_INTB_COUNT (1U) 1934 1935 /*! @name COMMON_SETVALID - Set ValidPending control bits for all DMA channels. */ 1936 /*! @{ */ 1937 #define DMA_COMMON_SETVALID_SV_MASK (0xFFFFFFFFU) 1938 #define DMA_COMMON_SETVALID_SV_SHIFT (0U) 1939 /*! SV - SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. The number of bits 1940 * = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the 1941 * VALIDPENDING control bit for DMA channel n 1942 */ 1943 #define DMA_COMMON_SETVALID_SV(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SV_SHIFT)) & DMA_COMMON_SETVALID_SV_MASK) 1944 /*! @} */ 1945 1946 /* The count of DMA_COMMON_SETVALID */ 1947 #define DMA_COMMON_SETVALID_COUNT (1U) 1948 1949 /*! @name COMMON_SETTRIG - Set Trigger control bits for all DMA channels. */ 1950 /*! @{ */ 1951 #define DMA_COMMON_SETTRIG_TRIG_MASK (0xFFFFFFFFU) 1952 #define DMA_COMMON_SETTRIG_TRIG_SHIFT (0U) 1953 /*! TRIG - Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. The number 1954 * of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = 1955 * sets the TRIG bit for DMA channel n. 1956 */ 1957 #define DMA_COMMON_SETTRIG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_TRIG_SHIFT)) & DMA_COMMON_SETTRIG_TRIG_MASK) 1958 /*! @} */ 1959 1960 /* The count of DMA_COMMON_SETTRIG */ 1961 #define DMA_COMMON_SETTRIG_COUNT (1U) 1962 1963 /*! @name COMMON_ABORT - Channel Abort control for all DMA channels. */ 1964 /*! @{ */ 1965 #define DMA_COMMON_ABORT_ABORTCTRL_MASK (0xFFFFFFFFU) 1966 #define DMA_COMMON_ABORT_ABORTCTRL_SHIFT (0U) 1967 /*! ABORTCTRL - Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1968 * 1 = aborts DMA operations on channel n. 1969 */ 1970 #define DMA_COMMON_ABORT_ABORTCTRL(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORTCTRL_SHIFT)) & DMA_COMMON_ABORT_ABORTCTRL_MASK) 1971 /*! @} */ 1972 1973 /* The count of DMA_COMMON_ABORT */ 1974 #define DMA_COMMON_ABORT_COUNT (1U) 1975 1976 /*! @name CHANNEL_CFG - Configuration register for DMA channel . */ 1977 /*! @{ */ 1978 #define DMA_CHANNEL_CFG_PERIPHREQEN_MASK (0x1U) 1979 #define DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT (0U) 1980 /*! PERIPHREQEN - Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory 1981 * move, any peripheral DMA request associated with that channel can be disabled to prevent any 1982 * interaction between the peripheral and the DMA controller. 1983 * 0b0..Disabled. Peripheral DMA requests are disabled. 1984 * 0b1..Enabled. Peripheral DMA requests are enabled. 1985 */ 1986 #define DMA_CHANNEL_CFG_PERIPHREQEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT)) & DMA_CHANNEL_CFG_PERIPHREQEN_MASK) 1987 #define DMA_CHANNEL_CFG_HWTRIGEN_MASK (0x2U) 1988 #define DMA_CHANNEL_CFG_HWTRIGEN_SHIFT (1U) 1989 /*! HWTRIGEN - Hardware Triggering Enable for this channel. 1990 * 0b0..Disabled. Hardware triggering is not used. 1991 * 0b1..Enabled. Use hardware triggering. 1992 */ 1993 #define DMA_CHANNEL_CFG_HWTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_HWTRIGEN_SHIFT)) & DMA_CHANNEL_CFG_HWTRIGEN_MASK) 1994 #define DMA_CHANNEL_CFG_TRIGPOL_MASK (0x10U) 1995 #define DMA_CHANNEL_CFG_TRIGPOL_SHIFT (4U) 1996 /*! TRIGPOL - Trigger Polarity. Selects the polarity of a hardware trigger for this channel. 1997 * 0b0..Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE. 1998 * 0b1..Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE. 1999 */ 2000 #define DMA_CHANNEL_CFG_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGPOL_SHIFT)) & DMA_CHANNEL_CFG_TRIGPOL_MASK) 2001 #define DMA_CHANNEL_CFG_TRIGTYPE_MASK (0x20U) 2002 #define DMA_CHANNEL_CFG_TRIGTYPE_SHIFT (5U) 2003 /*! TRIGTYPE - Trigger Type. Selects hardware trigger as edge triggered or level triggered. 2004 * 0b0..Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger. 2005 * 0b1..Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 2006 * 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the 2007 * trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger 2008 * is, again, asserted. However, the transfer will not be paused until any remaining transfers within the 2009 * current BURSTPOWER length are completed. 2010 */ 2011 #define DMA_CHANNEL_CFG_TRIGTYPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGTYPE_SHIFT)) & DMA_CHANNEL_CFG_TRIGTYPE_MASK) 2012 #define DMA_CHANNEL_CFG_TRIGBURST_MASK (0x40U) 2013 #define DMA_CHANNEL_CFG_TRIGBURST_SHIFT (6U) 2014 /*! TRIGBURST - Trigger Burst. Selects whether hardware triggers cause a single or burst transfer. 2015 * 0b0..Single transfer. Hardware trigger causes a single transfer. 2016 * 0b1..Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a 2017 * burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a 2018 * hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is 2019 * complete. 2020 */ 2021 #define DMA_CHANNEL_CFG_TRIGBURST(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGBURST_SHIFT)) & DMA_CHANNEL_CFG_TRIGBURST_MASK) 2022 #define DMA_CHANNEL_CFG_BURSTPOWER_MASK (0xF00U) 2023 #define DMA_CHANNEL_CFG_BURSTPOWER_SHIFT (8U) 2024 /*! BURSTPOWER - Burst Power is used in two ways. It always selects the address wrap size when 2025 * SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). 2026 * When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many 2027 * transfers are performed for each DMA trigger. This can be used, for example, with peripherals that 2028 * contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: 2029 * Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = 2030 * 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The 2031 * total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even 2032 * multiple of the burst size. 2033 */ 2034 #define DMA_CHANNEL_CFG_BURSTPOWER(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_BURSTPOWER_SHIFT)) & DMA_CHANNEL_CFG_BURSTPOWER_MASK) 2035 #define DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK (0x4000U) 2036 #define DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT (14U) 2037 /*! SRCBURSTWRAP - Source Burst Wrap. When enabled, the source data address for the DMA is 2038 * 'wrapped', meaning that the source address range for each burst will be the same. As an example, this 2039 * could be used to read several sequential registers from a peripheral for each DMA burst, 2040 * reading the same registers again for each burst. 2041 * 0b0..Disabled. Source burst wrapping is not enabled for this DMA channel. 2042 * 0b1..Enabled. Source burst wrapping is enabled for this DMA channel. 2043 */ 2044 #define DMA_CHANNEL_CFG_SRCBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK) 2045 #define DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK (0x8000U) 2046 #define DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT (15U) 2047 /*! DSTBURSTWRAP - Destination Burst Wrap. When enabled, the destination data address for the DMA is 2048 * 'wrapped', meaning that the destination address range for each burst will be the same. As an 2049 * example, this could be used to write several sequential registers to a peripheral for each DMA 2050 * burst, writing the same registers again for each burst. 2051 * 0b0..Disabled. Destination burst wrapping is not enabled for this DMA channel. 2052 * 0b1..Enabled. Destination burst wrapping is enabled for this DMA channel. 2053 */ 2054 #define DMA_CHANNEL_CFG_DSTBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK) 2055 #define DMA_CHANNEL_CFG_CHPRIORITY_MASK (0x70000U) 2056 #define DMA_CHANNEL_CFG_CHPRIORITY_SHIFT (16U) 2057 /*! CHPRIORITY - Priority of this channel when multiple DMA requests are pending. Eight priority 2058 * levels are supported: 0x0 = highest priority. 0x7 = lowest priority. 2059 */ 2060 #define DMA_CHANNEL_CFG_CHPRIORITY(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_CHPRIORITY_SHIFT)) & DMA_CHANNEL_CFG_CHPRIORITY_MASK) 2061 /*! @} */ 2062 2063 /* The count of DMA_CHANNEL_CFG */ 2064 #define DMA_CHANNEL_CFG_COUNT (20U) 2065 2066 /*! @name CHANNEL_CTLSTAT - Control and status register for DMA channel . */ 2067 /*! @{ */ 2068 #define DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK (0x1U) 2069 #define DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT (0U) 2070 /*! VALIDPENDING - Valid pending flag for this channel. This bit is set when a 1 is written to the 2071 * corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel. 2072 * 0b0..No effect. No effect on DMA operation. 2073 * 0b1..Valid pending. 2074 */ 2075 #define DMA_CHANNEL_CTLSTAT_VALIDPENDING(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT)) & DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK) 2076 #define DMA_CHANNEL_CTLSTAT_TRIG_MASK (0x4U) 2077 #define DMA_CHANNEL_CTLSTAT_TRIG_SHIFT (2U) 2078 /*! TRIG - Trigger flag. Indicates that the trigger for this channel is currently set. This bit is 2079 * cleared at the end of an entire transfer or upon reload when CLRTRIG = 1. 2080 * 0b0..Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out. 2081 * 0b1..Triggered. The trigger for this DMA channel is set. DMA operations will be carried out. 2082 */ 2083 #define DMA_CHANNEL_CTLSTAT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_TRIG_SHIFT)) & DMA_CHANNEL_CTLSTAT_TRIG_MASK) 2084 /*! @} */ 2085 2086 /* The count of DMA_CHANNEL_CTLSTAT */ 2087 #define DMA_CHANNEL_CTLSTAT_COUNT (20U) 2088 2089 /*! @name CHANNEL_XFERCFG - Transfer configuration register for DMA channel . */ 2090 /*! @{ */ 2091 #define DMA_CHANNEL_XFERCFG_CFGVALID_MASK (0x1U) 2092 #define DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT (0U) 2093 /*! CFGVALID - Configuration Valid flag. This bit indicates whether the current channel descriptor 2094 * is valid and can potentially be acted upon, if all other activation criteria are fulfilled. 2095 * 0b0..Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting. 2096 * 0b1..Valid. The current channel descriptor is considered valid. 2097 */ 2098 #define DMA_CHANNEL_XFERCFG_CFGVALID(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT)) & DMA_CHANNEL_XFERCFG_CFGVALID_MASK) 2099 #define DMA_CHANNEL_XFERCFG_RELOAD_MASK (0x2U) 2100 #define DMA_CHANNEL_XFERCFG_RELOAD_SHIFT (1U) 2101 /*! RELOAD - Indicates whether the channel's control structure will be reloaded when the current 2102 * descriptor is exhausted. Reloading allows ping-pong and linked transfers. 2103 * 0b0..Disabled. Do not reload the channels' control structure when the current descriptor is exhausted. 2104 * 0b1..Enabled. Reload the channels' control structure when the current descriptor is exhausted. 2105 */ 2106 #define DMA_CHANNEL_XFERCFG_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_RELOAD_SHIFT)) & DMA_CHANNEL_XFERCFG_RELOAD_MASK) 2107 #define DMA_CHANNEL_XFERCFG_SWTRIG_MASK (0x4U) 2108 #define DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT (2U) 2109 /*! SWTRIG - Software Trigger. 2110 * 0b0..Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by 2111 * the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel. 2112 * 0b1..Set. When written by software, the trigger for this channel is set immediately. This feature should not 2113 * be used with level triggering when TRIGBURST = 0. 2114 */ 2115 #define DMA_CHANNEL_XFERCFG_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_SWTRIG_MASK) 2116 #define DMA_CHANNEL_XFERCFG_CLRTRIG_MASK (0x8U) 2117 #define DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT (3U) 2118 /*! CLRTRIG - Clear Trigger. 2119 * 0b0..Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started. 2120 * 0b1..Cleared. The trigger is cleared when this descriptor is exhausted 2121 */ 2122 #define DMA_CHANNEL_XFERCFG_CLRTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_CLRTRIG_MASK) 2123 #define DMA_CHANNEL_XFERCFG_SETINTA_MASK (0x10U) 2124 #define DMA_CHANNEL_XFERCFG_SETINTA_SHIFT (4U) 2125 /*! SETINTA - Set Interrupt flag A for this channel. There is no hardware distinction between 2126 * interrupt A and B. They can be used by software to assist with more complex descriptor usage. By 2127 * convention, interrupt A may be used when only one interrupt flag is needed. 2128 * 0b0..No effect. 2129 * 0b1..Set. The INTA flag for this channel will be set when the current descriptor is exhausted. 2130 */ 2131 #define DMA_CHANNEL_XFERCFG_SETINTA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTA_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTA_MASK) 2132 #define DMA_CHANNEL_XFERCFG_SETINTB_MASK (0x20U) 2133 #define DMA_CHANNEL_XFERCFG_SETINTB_SHIFT (5U) 2134 /*! SETINTB - Set Interrupt flag B for this channel. There is no hardware distinction between 2135 * interrupt A and B. They can be used by software to assist with more complex descriptor usage. By 2136 * convention, interrupt A may be used when only one interrupt flag is needed. 2137 * 0b0..No effect. 2138 * 0b1..Set. The INTB flag for this channel will be set when the current descriptor is exhausted. 2139 */ 2140 #define DMA_CHANNEL_XFERCFG_SETINTB(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTB_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTB_MASK) 2141 #define DMA_CHANNEL_XFERCFG_WIDTH_MASK (0x300U) 2142 #define DMA_CHANNEL_XFERCFG_WIDTH_SHIFT (8U) 2143 /*! WIDTH - Transfer width used for this DMA channel. 2144 * 0b00..8-bit. 8-bit transfers are performed (8-bit source reads and destination writes). 2145 * 0b01..16-bit. 6-bit transfers are performed (16-bit source reads and destination writes). 2146 * 0b10..32-bit. 32-bit transfers are performed (32-bit source reads and destination writes). 2147 * 0b11..Reserved. Reserved setting, do not use. 2148 */ 2149 #define DMA_CHANNEL_XFERCFG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_WIDTH_SHIFT)) & DMA_CHANNEL_XFERCFG_WIDTH_MASK) 2150 #define DMA_CHANNEL_XFERCFG_SRCINC_MASK (0x3000U) 2151 #define DMA_CHANNEL_XFERCFG_SRCINC_SHIFT (12U) 2152 /*! SRCINC - Determines whether the source address is incremented for each DMA transfer. 2153 * 0b00..No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device. 2154 * 0b01..1 x width. The source address is incremented by the amount specified by Width for each transfer. This is 2155 * the usual case when the source is memory. 2156 * 0b10..2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer. 2157 * 0b11..4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer. 2158 */ 2159 #define DMA_CHANNEL_XFERCFG_SRCINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SRCINC_SHIFT)) & DMA_CHANNEL_XFERCFG_SRCINC_MASK) 2160 #define DMA_CHANNEL_XFERCFG_DSTINC_MASK (0xC000U) 2161 #define DMA_CHANNEL_XFERCFG_DSTINC_SHIFT (14U) 2162 /*! DSTINC - Determines whether the destination address is incremented for each DMA transfer. 2163 * 0b00..No increment. The destination address is not incremented for each transfer. This is the usual case when 2164 * the destination is a peripheral device. 2165 * 0b01..1 x width. The destination address is incremented by the amount specified by Width for each transfer. 2166 * This is the usual case when the destination is memory. 2167 * 0b10..2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer. 2168 * 0b11..4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer. 2169 */ 2170 #define DMA_CHANNEL_XFERCFG_DSTINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_DSTINC_SHIFT)) & DMA_CHANNEL_XFERCFG_DSTINC_MASK) 2171 #define DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK (0x3FF0000U) 2172 #define DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT (16U) 2173 /*! XFERCOUNT - Total number of transfers to be performed, minus 1 encoded. The number of bytes 2174 * transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller 2175 * uses this bit field during transfer to count down. Hence, it cannot be used by software to read 2176 * back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 2177 * transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of 2178 * 1,024 transfers will be performed. 2179 */ 2180 #define DMA_CHANNEL_XFERCFG_XFERCOUNT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT)) & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) 2181 /*! @} */ 2182 2183 /* The count of DMA_CHANNEL_XFERCFG */ 2184 #define DMA_CHANNEL_XFERCFG_COUNT (20U) 2185 2186 2187 /*! 2188 * @} 2189 */ /* end of group DMA_Register_Masks */ 2190 2191 2192 /* DMA - Peripheral instance base addresses */ 2193 /** Peripheral DMA0 base address */ 2194 #define DMA0_BASE (0x40082000u) 2195 /** Peripheral DMA0 base pointer */ 2196 #define DMA0 ((DMA_Type *)DMA0_BASE) 2197 /** Array initializer of DMA peripheral base addresses */ 2198 #define DMA_BASE_ADDRS { DMA0_BASE } 2199 /** Array initializer of DMA peripheral base pointers */ 2200 #define DMA_BASE_PTRS { DMA0 } 2201 /** Interrupt vectors for the DMA peripheral type */ 2202 #define DMA_IRQS { DMA0_IRQn } 2203 2204 /*! 2205 * @} 2206 */ /* end of group DMA_Peripheral_Access_Layer */ 2207 2208 2209 /* ---------------------------------------------------------------------------- 2210 -- DMIC Peripheral Access Layer 2211 ---------------------------------------------------------------------------- */ 2212 2213 /*! 2214 * @addtogroup DMIC_Peripheral_Access_Layer DMIC Peripheral Access Layer 2215 * @{ 2216 */ 2217 2218 /** DMIC - Register Layout Typedef */ 2219 typedef struct { 2220 struct { /* offset: 0x0, array step: 0x100 */ 2221 __IO uint32_t OSR; /**< Oversample Rate register 0, array offset: 0x0, array step: 0x100 */ 2222 __IO uint32_t DIVHFCLK; /**< DMIC Clock Register 0, array offset: 0x4, array step: 0x100 */ 2223 __IO uint32_t PREAC2FSCOEF; /**< Pre-Emphasis Filter Coefficient for 2 FS register, array offset: 0x8, array step: 0x100 */ 2224 __IO uint32_t PREAC4FSCOEF; /**< Pre-Emphasis Filter Coefficient for 4 FS register, array offset: 0xC, array step: 0x100 */ 2225 __IO uint32_t GAINSHIFT; /**< Decimator Gain Shift register, array offset: 0x10, array step: 0x100 */ 2226 uint8_t RESERVED_0[108]; 2227 __IO uint32_t FIFO_CTRL; /**< FIFO Control register 0, array offset: 0x80, array step: 0x100 */ 2228 __IO uint32_t FIFO_STATUS; /**< FIFO Status register 0, array offset: 0x84, array step: 0x100 */ 2229 __IO uint32_t FIFO_DATA; /**< FIFO Data Register 0, array offset: 0x88, array step: 0x100 */ 2230 __IO uint32_t PHY_CTRL; /**< PDM Source Configuration register 0, array offset: 0x8C, array step: 0x100 */ 2231 __IO uint32_t DC_CTRL; /**< DC Control register 0, array offset: 0x90, array step: 0x100 */ 2232 uint8_t RESERVED_1[108]; 2233 } CHANNEL[2]; 2234 uint8_t RESERVED_0[3328]; 2235 __IO uint32_t CHANEN; /**< Channel Enable register, offset: 0xF00 */ 2236 uint8_t RESERVED_1[8]; 2237 __IO uint32_t IOCFG; /**< I/O Configuration register, offset: 0xF0C */ 2238 __IO uint32_t USE2FS; /**< Use 2FS register, offset: 0xF10 */ 2239 uint8_t RESERVED_2[108]; 2240 __IO uint32_t HWVADGAIN; /**< HWVAD input gain register, offset: 0xF80 */ 2241 __IO uint32_t HWVADHPFS; /**< HWVAD filter control register, offset: 0xF84 */ 2242 __IO uint32_t HWVADST10; /**< HWVAD control register, offset: 0xF88 */ 2243 __IO uint32_t HWVADRSTT; /**< HWVAD filter reset register, offset: 0xF8C */ 2244 __IO uint32_t HWVADTHGN; /**< HWVAD noise estimator gain register, offset: 0xF90 */ 2245 __IO uint32_t HWVADTHGS; /**< HWVAD signal estimator gain register, offset: 0xF94 */ 2246 __I uint32_t HWVADLOWZ; /**< HWVAD noise envelope estimator register, offset: 0xF98 */ 2247 uint8_t RESERVED_3[96]; 2248 __I uint32_t ID; /**< Module Identification register, offset: 0xFFC */ 2249 } DMIC_Type; 2250 2251 /* ---------------------------------------------------------------------------- 2252 -- DMIC Register Masks 2253 ---------------------------------------------------------------------------- */ 2254 2255 /*! 2256 * @addtogroup DMIC_Register_Masks DMIC Register Masks 2257 * @{ 2258 */ 2259 2260 /*! @name CHANNEL_OSR - Oversample Rate register 0 */ 2261 /*! @{ */ 2262 #define DMIC_CHANNEL_OSR_OSR_MASK (0xFFU) 2263 #define DMIC_CHANNEL_OSR_OSR_SHIFT (0U) 2264 /*! OSR - Selects the oversample rate for the related input channel. 2265 */ 2266 #define DMIC_CHANNEL_OSR_OSR(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_OSR_OSR_SHIFT)) & DMIC_CHANNEL_OSR_OSR_MASK) 2267 /*! @} */ 2268 2269 /* The count of DMIC_CHANNEL_OSR */ 2270 #define DMIC_CHANNEL_OSR_COUNT (2U) 2271 2272 /*! @name CHANNEL_DIVHFCLK - DMIC Clock Register 0 */ 2273 /*! @{ */ 2274 #define DMIC_CHANNEL_DIVHFCLK_PDMDIV_MASK (0xFU) 2275 #define DMIC_CHANNEL_DIVHFCLK_PDMDIV_SHIFT (0U) 2276 /*! PDMDIV - PDM clock divider value. 0 = divide by 1 1 = divide by 2 2 = divide by 3 3 = divide by 2277 * 4 4 = divide by 6 5 = divide by 8 6 = divide by 12 7 = divide by 16 8 = divide by 24 9 = 2278 * divide by 32 10 = divide by 48 11 = divide by 64 12 = divide by 96 13 = divide by 128 others = 2279 * reserved. 2280 */ 2281 #define DMIC_CHANNEL_DIVHFCLK_PDMDIV(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DIVHFCLK_PDMDIV_SHIFT)) & DMIC_CHANNEL_DIVHFCLK_PDMDIV_MASK) 2282 /*! @} */ 2283 2284 /* The count of DMIC_CHANNEL_DIVHFCLK */ 2285 #define DMIC_CHANNEL_DIVHFCLK_COUNT (2U) 2286 2287 /*! @name CHANNEL_PREAC2FSCOEF - Pre-Emphasis Filter Coefficient for 2 FS register */ 2288 /*! @{ */ 2289 #define DMIC_CHANNEL_PREAC2FSCOEF_COMP_MASK (0x3U) 2290 #define DMIC_CHANNEL_PREAC2FSCOEF_COMP_SHIFT (0U) 2291 /*! COMP - Pre-emphasis filer coefficient for 2 FS mode. 0 = Compensation = 0 1 = Compensation = 16 2292 * 2 = Compensation = 15 3 = Compensation = 13 2293 */ 2294 #define DMIC_CHANNEL_PREAC2FSCOEF_COMP(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PREAC2FSCOEF_COMP_SHIFT)) & DMIC_CHANNEL_PREAC2FSCOEF_COMP_MASK) 2295 /*! @} */ 2296 2297 /* The count of DMIC_CHANNEL_PREAC2FSCOEF */ 2298 #define DMIC_CHANNEL_PREAC2FSCOEF_COUNT (2U) 2299 2300 /*! @name CHANNEL_PREAC4FSCOEF - Pre-Emphasis Filter Coefficient for 4 FS register */ 2301 /*! @{ */ 2302 #define DMIC_CHANNEL_PREAC4FSCOEF_COMP_MASK (0x3U) 2303 #define DMIC_CHANNEL_PREAC4FSCOEF_COMP_SHIFT (0U) 2304 /*! COMP - Pre-emphasis filer coefficient for 4 FS mode. 0 = Compensation = 0 1 = Compensation = 16 2305 * 2 = Compensation = 15 3 = Compensation = 13 2306 */ 2307 #define DMIC_CHANNEL_PREAC4FSCOEF_COMP(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PREAC4FSCOEF_COMP_SHIFT)) & DMIC_CHANNEL_PREAC4FSCOEF_COMP_MASK) 2308 /*! @} */ 2309 2310 /* The count of DMIC_CHANNEL_PREAC4FSCOEF */ 2311 #define DMIC_CHANNEL_PREAC4FSCOEF_COUNT (2U) 2312 2313 /*! @name CHANNEL_GAINSHIFT - Decimator Gain Shift register */ 2314 /*! @{ */ 2315 #define DMIC_CHANNEL_GAINSHIFT_GAIN_MASK (0x3FU) 2316 #define DMIC_CHANNEL_GAINSHIFT_GAIN_SHIFT (0U) 2317 /*! GAIN - Gain control, as a positive or negative (two's complement) number of bits to shift. 2318 */ 2319 #define DMIC_CHANNEL_GAINSHIFT_GAIN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_GAINSHIFT_GAIN_SHIFT)) & DMIC_CHANNEL_GAINSHIFT_GAIN_MASK) 2320 /*! @} */ 2321 2322 /* The count of DMIC_CHANNEL_GAINSHIFT */ 2323 #define DMIC_CHANNEL_GAINSHIFT_COUNT (2U) 2324 2325 /*! @name CHANNEL_FIFO_CTRL - FIFO Control register 0 */ 2326 /*! @{ */ 2327 #define DMIC_CHANNEL_FIFO_CTRL_ENABLE_MASK (0x1U) 2328 #define DMIC_CHANNEL_FIFO_CTRL_ENABLE_SHIFT (0U) 2329 /*! ENABLE - FIFO enable. 2330 * 0b0..FIFO is not enabled. Enabling a DMIC channel with the FIFO disabled could be useful while data is being 2331 * streamed to the I2S, or in order to avoid a filter settling delay when a channel is re-enabled after a 2332 * period when the data was not needed. 2333 * 0b1..FIFO is enabled. The FIFO must be enabled in order for the CPU or DMA to read data from the DMIC via the FIFODATA register. 2334 */ 2335 #define DMIC_CHANNEL_FIFO_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_ENABLE_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_ENABLE_MASK) 2336 #define DMIC_CHANNEL_FIFO_CTRL_RESETN_MASK (0x2U) 2337 #define DMIC_CHANNEL_FIFO_CTRL_RESETN_SHIFT (1U) 2338 /*! RESETN - FIFO reset. 2339 * 0b0..Reset the FIFO. 2340 * 0b1..Normal operation 2341 */ 2342 #define DMIC_CHANNEL_FIFO_CTRL_RESETN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_RESETN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_RESETN_MASK) 2343 #define DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK (0x4U) 2344 #define DMIC_CHANNEL_FIFO_CTRL_INTEN_SHIFT (2U) 2345 /*! INTEN - Interrupt enable. 2346 * 0b0..FIFO level interrupts are not enabled. 2347 * 0b1..FIFO level interrupts are enabled. 2348 */ 2349 #define DMIC_CHANNEL_FIFO_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_INTEN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK) 2350 #define DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK (0x8U) 2351 #define DMIC_CHANNEL_FIFO_CTRL_DMAEN_SHIFT (3U) 2352 /*! DMAEN - DMA enable 2353 * 0b0..DMA requests are not enabled. 2354 * 0b1..DMA requests based on FIFO level are enabled. 2355 */ 2356 #define DMIC_CHANNEL_FIFO_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_DMAEN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK) 2357 #define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_MASK (0x1F0000U) 2358 #define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_SHIFT (16U) 2359 /*! TRIGLVL - FIFO trigger level. Selects the data trigger level for interrupt or DMA operation. If 2360 * enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then 2361 * return to the reduced power mode See Section 4.5.66 'Hardware Wake-up control register'. 0 = 2362 * trigger when the FIFO has received one entry (is no longer empty). 1 = trigger when the FIFO has 2363 * received two entries. 15 = trigger when the FIFO has received 16 entries (has become full). 2364 */ 2365 #define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_MASK) 2366 /*! @} */ 2367 2368 /* The count of DMIC_CHANNEL_FIFO_CTRL */ 2369 #define DMIC_CHANNEL_FIFO_CTRL_COUNT (2U) 2370 2371 /*! @name CHANNEL_FIFO_STATUS - FIFO Status register 0 */ 2372 /*! @{ */ 2373 #define DMIC_CHANNEL_FIFO_STATUS_INT_MASK (0x1U) 2374 #define DMIC_CHANNEL_FIFO_STATUS_INT_SHIFT (0U) 2375 /*! INT - Interrupt flag. Asserted when FIFO data reaches the level specified in the FIFOCTRL 2376 * register. Writing a one to this bit clears the flag. Remark: note that the bus clock to the DMIC 2377 * subsystem must be running in order for an interrupt to occur. 2378 */ 2379 #define DMIC_CHANNEL_FIFO_STATUS_INT(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_INT_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_INT_MASK) 2380 #define DMIC_CHANNEL_FIFO_STATUS_OVERRUN_MASK (0x2U) 2381 #define DMIC_CHANNEL_FIFO_STATUS_OVERRUN_SHIFT (1U) 2382 /*! OVERRUN - Overrun flag. Indicates that a FIFO overflow has occurred at some point. Writing a one 2383 * to this bit clears the flag. This flag does not cause an interrupt. 2384 */ 2385 #define DMIC_CHANNEL_FIFO_STATUS_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_OVERRUN_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_OVERRUN_MASK) 2386 #define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_MASK (0x4U) 2387 #define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_SHIFT (2U) 2388 /*! UNDERRUN - Underrun flag. Indicates that a FIFO underflow has occurred at some point. Writing a one to this bit clears the flag. 2389 */ 2390 #define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_MASK) 2391 /*! @} */ 2392 2393 /* The count of DMIC_CHANNEL_FIFO_STATUS */ 2394 #define DMIC_CHANNEL_FIFO_STATUS_COUNT (2U) 2395 2396 /*! @name CHANNEL_FIFO_DATA - FIFO Data Register 0 */ 2397 /*! @{ */ 2398 #define DMIC_CHANNEL_FIFO_DATA_DATA_MASK (0xFFFFFFU) 2399 #define DMIC_CHANNEL_FIFO_DATA_DATA_SHIFT (0U) 2400 /*! DATA - Data from the top of the input filter FIFO. 2401 */ 2402 #define DMIC_CHANNEL_FIFO_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_DATA_DATA_SHIFT)) & DMIC_CHANNEL_FIFO_DATA_DATA_MASK) 2403 /*! @} */ 2404 2405 /* The count of DMIC_CHANNEL_FIFO_DATA */ 2406 #define DMIC_CHANNEL_FIFO_DATA_COUNT (2U) 2407 2408 /*! @name CHANNEL_PHY_CTRL - PDM Source Configuration register 0 */ 2409 /*! @{ */ 2410 #define DMIC_CHANNEL_PHY_CTRL_PHY_FALL_MASK (0x1U) 2411 #define DMIC_CHANNEL_PHY_CTRL_PHY_FALL_SHIFT (0U) 2412 /*! PHY_FALL - Capture PDM_DATA 2413 * 0b0..Capture PDM_DATA on the rising edge of PDM_CLK. 2414 * 0b1..Capture PDM_DATA on the falling edge of PDM_CLK. 2415 */ 2416 #define DMIC_CHANNEL_PHY_CTRL_PHY_FALL(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PHY_CTRL_PHY_FALL_SHIFT)) & DMIC_CHANNEL_PHY_CTRL_PHY_FALL_MASK) 2417 #define DMIC_CHANNEL_PHY_CTRL_PHY_HALF_MASK (0x2U) 2418 #define DMIC_CHANNEL_PHY_CTRL_PHY_HALF_SHIFT (1U) 2419 /*! PHY_HALF - Half rate sampling 2420 * 0b0..Standard half rate sampling. The clock to the DMIC is sent at the same rate as the decimator is providing. 2421 * 0b1..Use half rate sampling. The clock to the DMIC is sent at half the rate as the decimator is providing. 2422 */ 2423 #define DMIC_CHANNEL_PHY_CTRL_PHY_HALF(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PHY_CTRL_PHY_HALF_SHIFT)) & DMIC_CHANNEL_PHY_CTRL_PHY_HALF_MASK) 2424 /*! @} */ 2425 2426 /* The count of DMIC_CHANNEL_PHY_CTRL */ 2427 #define DMIC_CHANNEL_PHY_CTRL_COUNT (2U) 2428 2429 /*! @name CHANNEL_DC_CTRL - DC Control register 0 */ 2430 /*! @{ */ 2431 #define DMIC_CHANNEL_DC_CTRL_DCPOLE_MASK (0x3U) 2432 #define DMIC_CHANNEL_DC_CTRL_DCPOLE_SHIFT (0U) 2433 /*! DCPOLE - DC block filter 2434 * 0b00..Flat response, no filter. 2435 * 0b01..155 Hz. 2436 * 0b10..78 Hz. 2437 * 0b11..39 Hz 2438 */ 2439 #define DMIC_CHANNEL_DC_CTRL_DCPOLE(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_DCPOLE_SHIFT)) & DMIC_CHANNEL_DC_CTRL_DCPOLE_MASK) 2440 #define DMIC_CHANNEL_DC_CTRL_DCGAIN_MASK (0xF0U) 2441 #define DMIC_CHANNEL_DC_CTRL_DCGAIN_SHIFT (4U) 2442 /*! DCGAIN - Fine gain adjustment in the form of a number of bits to downshift. 2443 */ 2444 #define DMIC_CHANNEL_DC_CTRL_DCGAIN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_DCGAIN_SHIFT)) & DMIC_CHANNEL_DC_CTRL_DCGAIN_MASK) 2445 #define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_MASK (0x100U) 2446 #define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_SHIFT (8U) 2447 /*! SATURATEAT16BIT - Selects 16-bit saturation. 2448 * 0b0..Results roll over if out range and do not saturate. 2449 * 0b1..If the result overflows, it saturates at 0xFFFF for positive overflow and 0x8000 for negative overflow. 2450 */ 2451 #define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_SHIFT)) & DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_MASK) 2452 /*! @} */ 2453 2454 /* The count of DMIC_CHANNEL_DC_CTRL */ 2455 #define DMIC_CHANNEL_DC_CTRL_COUNT (2U) 2456 2457 /*! @name CHANEN - Channel Enable register */ 2458 /*! @{ */ 2459 #define DMIC_CHANEN_EN_CH0_MASK (0x1U) 2460 #define DMIC_CHANEN_EN_CH0_SHIFT (0U) 2461 /*! EN_CH0 - Enable channel 0. When 1, PDM channel 0 is enabled. 2462 */ 2463 #define DMIC_CHANEN_EN_CH0(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH0_SHIFT)) & DMIC_CHANEN_EN_CH0_MASK) 2464 #define DMIC_CHANEN_EN_CH1_MASK (0x2U) 2465 #define DMIC_CHANEN_EN_CH1_SHIFT (1U) 2466 /*! EN_CH1 - Enable channel 1. When 1, PDM channel 1 is enabled. 2467 */ 2468 #define DMIC_CHANEN_EN_CH1(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH1_SHIFT)) & DMIC_CHANEN_EN_CH1_MASK) 2469 /*! @} */ 2470 2471 /*! @name IOCFG - I/O Configuration register */ 2472 /*! @{ */ 2473 #define DMIC_IOCFG_CLK_BYPASS0_MASK (0x1U) 2474 #define DMIC_IOCFG_CLK_BYPASS0_SHIFT (0U) 2475 /*! CLK_BYPASS0 - Bypass CLK0. When 1, PDM_DATA1 becomes the clock for PDM channel 0. This provides 2476 * for the possibility of an external codec taking over the PDM bus. 2477 */ 2478 #define DMIC_IOCFG_CLK_BYPASS0(x) (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_CLK_BYPASS0_SHIFT)) & DMIC_IOCFG_CLK_BYPASS0_MASK) 2479 #define DMIC_IOCFG_CLK_BYPASS1_MASK (0x2U) 2480 #define DMIC_IOCFG_CLK_BYPASS1_SHIFT (1U) 2481 /*! CLK_BYPASS1 - Bypass CLK1. When 1, PDM_DATA1 becomes the clock for PDM channel 1. This provides 2482 * for the possibility of an external codec taking over the PDM bus. 2483 */ 2484 #define DMIC_IOCFG_CLK_BYPASS1(x) (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_CLK_BYPASS1_SHIFT)) & DMIC_IOCFG_CLK_BYPASS1_MASK) 2485 #define DMIC_IOCFG_STEREO_DATA0_MASK (0x4U) 2486 #define DMIC_IOCFG_STEREO_DATA0_SHIFT (2U) 2487 /*! STEREO_DATA0 - Stereo PDM select. When 1, PDM_DATA0 is routed to both PDM channels in a 2488 * configuration that supports a single stereo digital microphone. 2489 */ 2490 #define DMIC_IOCFG_STEREO_DATA0(x) (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_STEREO_DATA0_SHIFT)) & DMIC_IOCFG_STEREO_DATA0_MASK) 2491 /*! @} */ 2492 2493 /*! @name USE2FS - Use 2FS register */ 2494 /*! @{ */ 2495 #define DMIC_USE2FS_USE2FS_MASK (0x1U) 2496 #define DMIC_USE2FS_USE2FS_SHIFT (0U) 2497 /*! USE2FS - Use 2FS register 2498 * 0b0..Use 1FS output for PCM data. 2499 * 0b1..Use 2FS output for PCM data. 2500 */ 2501 #define DMIC_USE2FS_USE2FS(x) (((uint32_t)(((uint32_t)(x)) << DMIC_USE2FS_USE2FS_SHIFT)) & DMIC_USE2FS_USE2FS_MASK) 2502 /*! @} */ 2503 2504 /*! @name HWVADGAIN - HWVAD input gain register */ 2505 /*! @{ */ 2506 #define DMIC_HWVADGAIN_INPUTGAIN_MASK (0xFU) 2507 #define DMIC_HWVADGAIN_INPUTGAIN_SHIFT (0U) 2508 /*! INPUTGAIN - Shift value for input bits 0x00 -10 bits 0x01 -8 bits 0x02 -6 bits 0x03 -4 bits 0x04 2509 * -2 bits 0x05 0 bits (default) 0x06 +2 bits 0x07 +4 bits 0x08 +6 bits 0x09 +8 bits 0x0A +10 2510 * bits 0x0B +12 bits 0x0C +14 bits 0x0D to 0x0F Reserved. 2511 */ 2512 #define DMIC_HWVADGAIN_INPUTGAIN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADGAIN_INPUTGAIN_SHIFT)) & DMIC_HWVADGAIN_INPUTGAIN_MASK) 2513 /*! @} */ 2514 2515 /*! @name HWVADHPFS - HWVAD filter control register */ 2516 /*! @{ */ 2517 #define DMIC_HWVADHPFS_HPFS_MASK (0x3U) 2518 #define DMIC_HWVADHPFS_HPFS_SHIFT (0U) 2519 /*! HPFS - High pass filter 2520 * 0b00..First filter by-pass. 2521 * 0b01..High pass filter with -3dB cut-off at 1750Hz. 2522 * 0b10..High pass filter with -3dB cut-off at 215Hz. 2523 * 0b11..Reserved. 2524 */ 2525 #define DMIC_HWVADHPFS_HPFS(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADHPFS_HPFS_SHIFT)) & DMIC_HWVADHPFS_HPFS_MASK) 2526 /*! @} */ 2527 2528 /*! @name HWVADST10 - HWVAD control register */ 2529 /*! @{ */ 2530 #define DMIC_HWVADST10_ST10_MASK (0x1U) 2531 #define DMIC_HWVADST10_ST10_SHIFT (0U) 2532 /*! ST10 - Stage 0 2533 * 0b0..Normal operation, waiting for HWVAD trigger event (stage 0). 2534 * 0b1..Reset internal interrupt flag by writing a '1' pulse. 2535 */ 2536 #define DMIC_HWVADST10_ST10(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADST10_ST10_SHIFT)) & DMIC_HWVADST10_ST10_MASK) 2537 /*! @} */ 2538 2539 /*! @name HWVADRSTT - HWVAD filter reset register */ 2540 /*! @{ */ 2541 #define DMIC_HWVADRSTT_RSTT_MASK (0x1U) 2542 #define DMIC_HWVADRSTT_RSTT_SHIFT (0U) 2543 /*! RSTT - Writing a 1 resets all filter values 2544 */ 2545 #define DMIC_HWVADRSTT_RSTT(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADRSTT_RSTT_SHIFT)) & DMIC_HWVADRSTT_RSTT_MASK) 2546 /*! @} */ 2547 2548 /*! @name HWVADTHGN - HWVAD noise estimator gain register */ 2549 /*! @{ */ 2550 #define DMIC_HWVADTHGN_THGN_MASK (0xFU) 2551 #define DMIC_HWVADTHGN_THGN_SHIFT (0U) 2552 /*! THGN - Gain value for the noise estimator. Values 0 to 14. 0 corresponds to a gain of 1. 2553 */ 2554 #define DMIC_HWVADTHGN_THGN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADTHGN_THGN_SHIFT)) & DMIC_HWVADTHGN_THGN_MASK) 2555 /*! @} */ 2556 2557 /*! @name HWVADTHGS - HWVAD signal estimator gain register */ 2558 /*! @{ */ 2559 #define DMIC_HWVADTHGS_THGS_MASK (0xFU) 2560 #define DMIC_HWVADTHGS_THGS_SHIFT (0U) 2561 /*! THGS - Gain value for the signal estimator. Values 0 to 14. 0 corresponds to a gain of 1. 2562 */ 2563 #define DMIC_HWVADTHGS_THGS(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADTHGS_THGS_SHIFT)) & DMIC_HWVADTHGS_THGS_MASK) 2564 /*! @} */ 2565 2566 /*! @name HWVADLOWZ - HWVAD noise envelope estimator register */ 2567 /*! @{ */ 2568 #define DMIC_HWVADLOWZ_LOWZ_MASK (0xFFFFU) 2569 #define DMIC_HWVADLOWZ_LOWZ_SHIFT (0U) 2570 /*! LOWZ - Noise envelope estimator value. 2571 */ 2572 #define DMIC_HWVADLOWZ_LOWZ(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADLOWZ_LOWZ_SHIFT)) & DMIC_HWVADLOWZ_LOWZ_MASK) 2573 /*! @} */ 2574 2575 /*! @name ID - Module Identification register */ 2576 /*! @{ */ 2577 #define DMIC_ID_ID_MASK (0xFFFFFFFFU) 2578 #define DMIC_ID_ID_SHIFT (0U) 2579 /*! ID - Indicates module ID and the number of channels in this DMIC interface. 2580 */ 2581 #define DMIC_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << DMIC_ID_ID_SHIFT)) & DMIC_ID_ID_MASK) 2582 /*! @} */ 2583 2584 2585 /*! 2586 * @} 2587 */ /* end of group DMIC_Register_Masks */ 2588 2589 2590 /* DMIC - Peripheral instance base addresses */ 2591 /** Peripheral DMIC0 base address */ 2592 #define DMIC0_BASE (0x40090000u) 2593 /** Peripheral DMIC0 base pointer */ 2594 #define DMIC0 ((DMIC_Type *)DMIC0_BASE) 2595 /** Array initializer of DMIC peripheral base addresses */ 2596 #define DMIC_BASE_ADDRS { DMIC0_BASE } 2597 /** Array initializer of DMIC peripheral base pointers */ 2598 #define DMIC_BASE_PTRS { DMIC0 } 2599 /** Interrupt vectors for the DMIC peripheral type */ 2600 #define DMIC_IRQS { DMIC0_IRQn } 2601 #define DMIC_HWVAD_IRQS { HWVAD0_IRQn } 2602 2603 /*! 2604 * @} 2605 */ /* end of group DMIC_Peripheral_Access_Layer */ 2606 2607 2608 /* ---------------------------------------------------------------------------- 2609 -- FLEXCOMM Peripheral Access Layer 2610 ---------------------------------------------------------------------------- */ 2611 2612 /*! 2613 * @addtogroup FLEXCOMM_Peripheral_Access_Layer FLEXCOMM Peripheral Access Layer 2614 * @{ 2615 */ 2616 2617 /** FLEXCOMM - Register Layout Typedef */ 2618 typedef struct { 2619 uint8_t RESERVED_0[4088]; 2620 __IO uint32_t PSELID; /**< Peripheral Select and Flexcomm ID register., offset: 0xFF8 */ 2621 __I uint32_t PID; /**< Peripheral identification register., offset: 0xFFC */ 2622 } FLEXCOMM_Type; 2623 2624 /* ---------------------------------------------------------------------------- 2625 -- FLEXCOMM Register Masks 2626 ---------------------------------------------------------------------------- */ 2627 2628 /*! 2629 * @addtogroup FLEXCOMM_Register_Masks FLEXCOMM Register Masks 2630 * @{ 2631 */ 2632 2633 /*! @name PSELID - Peripheral Select and Flexcomm ID register. */ 2634 /*! @{ */ 2635 #define FLEXCOMM_PSELID_PERSEL_MASK (0x7U) 2636 #define FLEXCOMM_PSELID_PERSEL_SHIFT (0U) 2637 /*! PERSEL - Peripheral Select. This field is writable by software. 2638 * 0b000..No peripheral selected. 2639 * 0b001..USART function selected. 2640 * 0b010..SPI function selected. 2641 * 0b011..I2C function selected. 2642 * 0b100..I2S transmit function selected. 2643 * 0b101..I2S receive function selected. 2644 * 0b110..Reserved 2645 * 0b111..Reserved 2646 */ 2647 #define FLEXCOMM_PSELID_PERSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_PERSEL_SHIFT)) & FLEXCOMM_PSELID_PERSEL_MASK) 2648 #define FLEXCOMM_PSELID_LOCK_MASK (0x8U) 2649 #define FLEXCOMM_PSELID_LOCK_SHIFT (3U) 2650 /*! LOCK - Lock the peripheral select. This field is writable by software. 2651 * 0b0..Peripheral select can be changed by software. 2652 * 0b1..Peripheral select is locked and cannot be changed until this Flexcomm or the entire device is reset. 2653 */ 2654 #define FLEXCOMM_PSELID_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_LOCK_SHIFT)) & FLEXCOMM_PSELID_LOCK_MASK) 2655 #define FLEXCOMM_PSELID_USARTPRESENT_MASK (0x10U) 2656 #define FLEXCOMM_PSELID_USARTPRESENT_SHIFT (4U) 2657 /*! USARTPRESENT - USART present indicator. This field is Read-only. 2658 * 0b0..This Flexcomm does not include the USART function. 2659 * 0b1..This Flexcomm includes the USART function. 2660 */ 2661 #define FLEXCOMM_PSELID_USARTPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_USARTPRESENT_SHIFT)) & FLEXCOMM_PSELID_USARTPRESENT_MASK) 2662 #define FLEXCOMM_PSELID_SPIPRESENT_MASK (0x20U) 2663 #define FLEXCOMM_PSELID_SPIPRESENT_SHIFT (5U) 2664 /*! SPIPRESENT - SPI present indicator. This field is Read-only. 2665 * 0b0..This Flexcomm does not include the SPI function. 2666 * 0b1..This Flexcomm includes the SPI function. 2667 */ 2668 #define FLEXCOMM_PSELID_SPIPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_SPIPRESENT_SHIFT)) & FLEXCOMM_PSELID_SPIPRESENT_MASK) 2669 #define FLEXCOMM_PSELID_I2CPRESENT_MASK (0x40U) 2670 #define FLEXCOMM_PSELID_I2CPRESENT_SHIFT (6U) 2671 /*! I2CPRESENT - I2C present indicator. This field is Read-only. 2672 * 0b0..This Flexcomm does not include the I2C function. 2673 * 0b1..This Flexcomm includes the I2C function. 2674 */ 2675 #define FLEXCOMM_PSELID_I2CPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2CPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2CPRESENT_MASK) 2676 #define FLEXCOMM_PSELID_I2SPRESENT_MASK (0x80U) 2677 #define FLEXCOMM_PSELID_I2SPRESENT_SHIFT (7U) 2678 /*! I2SPRESENT - I 2S present indicator. This field is Read-only. 2679 * 0b0..This Flexcomm does not include the I2S function. 2680 * 0b1..This Flexcomm includes the I2S function. 2681 */ 2682 #define FLEXCOMM_PSELID_I2SPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2SPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2SPRESENT_MASK) 2683 #define FLEXCOMM_PSELID_ID_MASK (0xFFFFF000U) 2684 #define FLEXCOMM_PSELID_ID_SHIFT (12U) 2685 /*! ID - Flexcomm ID. 2686 */ 2687 #define FLEXCOMM_PSELID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_ID_SHIFT)) & FLEXCOMM_PSELID_ID_MASK) 2688 /*! @} */ 2689 2690 /*! @name PID - Peripheral identification register. */ 2691 /*! @{ */ 2692 #define FLEXCOMM_PID_Minor_Rev_MASK (0xF00U) 2693 #define FLEXCOMM_PID_Minor_Rev_SHIFT (8U) 2694 /*! Minor_Rev - Minor revision of module implementation. 2695 */ 2696 #define FLEXCOMM_PID_Minor_Rev(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Minor_Rev_SHIFT)) & FLEXCOMM_PID_Minor_Rev_MASK) 2697 #define FLEXCOMM_PID_Major_Rev_MASK (0xF000U) 2698 #define FLEXCOMM_PID_Major_Rev_SHIFT (12U) 2699 /*! Major_Rev - Major revision of module implementation. 2700 */ 2701 #define FLEXCOMM_PID_Major_Rev(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Major_Rev_SHIFT)) & FLEXCOMM_PID_Major_Rev_MASK) 2702 #define FLEXCOMM_PID_ID_MASK (0xFFFF0000U) 2703 #define FLEXCOMM_PID_ID_SHIFT (16U) 2704 /*! ID - Module identifier for the selected function. 2705 */ 2706 #define FLEXCOMM_PID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_ID_SHIFT)) & FLEXCOMM_PID_ID_MASK) 2707 /*! @} */ 2708 2709 2710 /*! 2711 * @} 2712 */ /* end of group FLEXCOMM_Register_Masks */ 2713 2714 2715 /* FLEXCOMM - Peripheral instance base addresses */ 2716 /** Peripheral FLEXCOMM0 base address */ 2717 #define FLEXCOMM0_BASE (0x40086000u) 2718 /** Peripheral FLEXCOMM0 base pointer */ 2719 #define FLEXCOMM0 ((FLEXCOMM_Type *)FLEXCOMM0_BASE) 2720 /** Peripheral FLEXCOMM1 base address */ 2721 #define FLEXCOMM1_BASE (0x40087000u) 2722 /** Peripheral FLEXCOMM1 base pointer */ 2723 #define FLEXCOMM1 ((FLEXCOMM_Type *)FLEXCOMM1_BASE) 2724 /** Peripheral FLEXCOMM2 base address */ 2725 #define FLEXCOMM2_BASE (0x40088000u) 2726 /** Peripheral FLEXCOMM2 base pointer */ 2727 #define FLEXCOMM2 ((FLEXCOMM_Type *)FLEXCOMM2_BASE) 2728 /** Peripheral FLEXCOMM3 base address */ 2729 #define FLEXCOMM3_BASE (0x40089000u) 2730 /** Peripheral FLEXCOMM3 base pointer */ 2731 #define FLEXCOMM3 ((FLEXCOMM_Type *)FLEXCOMM3_BASE) 2732 /** Peripheral FLEXCOMM4 base address */ 2733 #define FLEXCOMM4_BASE (0x4008A000u) 2734 /** Peripheral FLEXCOMM4 base pointer */ 2735 #define FLEXCOMM4 ((FLEXCOMM_Type *)FLEXCOMM4_BASE) 2736 /** Peripheral FLEXCOMM5 base address */ 2737 #define FLEXCOMM5_BASE (0x40096000u) 2738 /** Peripheral FLEXCOMM5 base pointer */ 2739 #define FLEXCOMM5 ((FLEXCOMM_Type *)FLEXCOMM5_BASE) 2740 /** Peripheral FLEXCOMM6 base address */ 2741 #define FLEXCOMM6_BASE (0x40097000u) 2742 /** Peripheral FLEXCOMM6 base pointer */ 2743 #define FLEXCOMM6 ((FLEXCOMM_Type *)FLEXCOMM6_BASE) 2744 /** Peripheral FLEXCOMM7 base address */ 2745 #define FLEXCOMM7_BASE (0x40098000u) 2746 /** Peripheral FLEXCOMM7 base pointer */ 2747 #define FLEXCOMM7 ((FLEXCOMM_Type *)FLEXCOMM7_BASE) 2748 /** Array initializer of FLEXCOMM peripheral base addresses */ 2749 #define FLEXCOMM_BASE_ADDRS { FLEXCOMM0_BASE, FLEXCOMM1_BASE, FLEXCOMM2_BASE, FLEXCOMM3_BASE, FLEXCOMM4_BASE, FLEXCOMM5_BASE, FLEXCOMM6_BASE, FLEXCOMM7_BASE } 2750 /** Array initializer of FLEXCOMM peripheral base pointers */ 2751 #define FLEXCOMM_BASE_PTRS { FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7 } 2752 /** Interrupt vectors for the FLEXCOMM peripheral type */ 2753 #define FLEXCOMM_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } 2754 2755 /*! 2756 * @} 2757 */ /* end of group FLEXCOMM_Peripheral_Access_Layer */ 2758 2759 2760 /* ---------------------------------------------------------------------------- 2761 -- GINT Peripheral Access Layer 2762 ---------------------------------------------------------------------------- */ 2763 2764 /*! 2765 * @addtogroup GINT_Peripheral_Access_Layer GINT Peripheral Access Layer 2766 * @{ 2767 */ 2768 2769 /** GINT - Register Layout Typedef */ 2770 typedef struct { 2771 __IO uint32_t CTRL; /**< GPIO grouped interrupt control register, offset: 0x0 */ 2772 uint8_t RESERVED_0[28]; 2773 __IO uint32_t PORT_POL[2]; /**< GPIO grouped interrupt port 0 polarity register, array offset: 0x20, array step: 0x4 */ 2774 uint8_t RESERVED_1[24]; 2775 __IO uint32_t PORT_ENA[2]; /**< GPIO grouped interrupt port 0 enable register, array offset: 0x40, array step: 0x4 */ 2776 } GINT_Type; 2777 2778 /* ---------------------------------------------------------------------------- 2779 -- GINT Register Masks 2780 ---------------------------------------------------------------------------- */ 2781 2782 /*! 2783 * @addtogroup GINT_Register_Masks GINT Register Masks 2784 * @{ 2785 */ 2786 2787 /*! @name CTRL - GPIO grouped interrupt control register */ 2788 /*! @{ */ 2789 #define GINT_CTRL_INT_MASK (0x1U) 2790 #define GINT_CTRL_INT_SHIFT (0U) 2791 /*! INT - Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect. 2792 * 0b0..No request. No interrupt request is pending. 2793 * 0b1..Request active. Interrupt request is active. 2794 */ 2795 #define GINT_CTRL_INT(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_INT_SHIFT)) & GINT_CTRL_INT_MASK) 2796 #define GINT_CTRL_COMB_MASK (0x2U) 2797 #define GINT_CTRL_COMB_SHIFT (1U) 2798 /*! COMB - Combine enabled inputs for group interrupt 2799 * 0b0..Or. OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity). 2800 * 0b1..And. AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity). 2801 */ 2802 #define GINT_CTRL_COMB(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_COMB_SHIFT)) & GINT_CTRL_COMB_MASK) 2803 #define GINT_CTRL_TRIG_MASK (0x4U) 2804 #define GINT_CTRL_TRIG_SHIFT (2U) 2805 /*! TRIG - Group interrupt trigger 2806 * 0b0..Edge-triggered. 2807 * 0b1..Level-triggered. 2808 */ 2809 #define GINT_CTRL_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_TRIG_SHIFT)) & GINT_CTRL_TRIG_MASK) 2810 /*! @} */ 2811 2812 /*! @name PORT_POL - GPIO grouped interrupt port 0 polarity register */ 2813 /*! @{ */ 2814 #define GINT_PORT_POL_POL_MASK (0xFFFFFFFFU) 2815 #define GINT_PORT_POL_POL_SHIFT (0U) 2816 /*! POL - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n 2817 * of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to 2818 * the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin 2819 * contributes to the group interrupt. 2820 */ 2821 #define GINT_PORT_POL_POL(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL_SHIFT)) & GINT_PORT_POL_POL_MASK) 2822 /*! @} */ 2823 2824 /* The count of GINT_PORT_POL */ 2825 #define GINT_PORT_POL_COUNT (2U) 2826 2827 /*! @name PORT_ENA - GPIO grouped interrupt port 0 enable register */ 2828 /*! @{ */ 2829 #define GINT_PORT_ENA_ENA_MASK (0xFFFFFFFFU) 2830 #define GINT_PORT_ENA_ENA_SHIFT (0U) 2831 /*! ENA - Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the 2832 * port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is 2833 * enabled and contributes to the grouped interrupt. 2834 */ 2835 #define GINT_PORT_ENA_ENA(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA_SHIFT)) & GINT_PORT_ENA_ENA_MASK) 2836 /*! @} */ 2837 2838 /* The count of GINT_PORT_ENA */ 2839 #define GINT_PORT_ENA_COUNT (2U) 2840 2841 2842 /*! 2843 * @} 2844 */ /* end of group GINT_Register_Masks */ 2845 2846 2847 /* GINT - Peripheral instance base addresses */ 2848 /** Peripheral GINT0 base address */ 2849 #define GINT0_BASE (0x40002000u) 2850 /** Peripheral GINT0 base pointer */ 2851 #define GINT0 ((GINT_Type *)GINT0_BASE) 2852 /** Peripheral GINT1 base address */ 2853 #define GINT1_BASE (0x40003000u) 2854 /** Peripheral GINT1 base pointer */ 2855 #define GINT1 ((GINT_Type *)GINT1_BASE) 2856 /** Array initializer of GINT peripheral base addresses */ 2857 #define GINT_BASE_ADDRS { GINT0_BASE, GINT1_BASE } 2858 /** Array initializer of GINT peripheral base pointers */ 2859 #define GINT_BASE_PTRS { GINT0, GINT1 } 2860 /** Interrupt vectors for the GINT peripheral type */ 2861 #define GINT_IRQS { GINT0_IRQn, GINT1_IRQn } 2862 2863 /*! 2864 * @} 2865 */ /* end of group GINT_Peripheral_Access_Layer */ 2866 2867 2868 /* ---------------------------------------------------------------------------- 2869 -- GPIO Peripheral Access Layer 2870 ---------------------------------------------------------------------------- */ 2871 2872 /*! 2873 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer 2874 * @{ 2875 */ 2876 2877 /** GPIO - Register Layout Typedef */ 2878 typedef struct { 2879 __IO uint8_t B[2][32]; /**< Byte pin registers for all port 0 and 1 GPIO pins, array offset: 0x0, array step: index*0x20, index2*0x1 */ 2880 uint8_t RESERVED_0[4032]; 2881 __IO uint32_t W[2][32]; /**< Word pin registers for all port 0 and 1 GPIO pins, array offset: 0x1000, array step: index*0x80, index2*0x4 */ 2882 uint8_t RESERVED_1[3840]; 2883 __IO uint32_t DIR[2]; /**< Direction registers, array offset: 0x2000, array step: 0x4 */ 2884 uint8_t RESERVED_2[120]; 2885 __IO uint32_t MASK[2]; /**< Mask register, array offset: 0x2080, array step: 0x4 */ 2886 uint8_t RESERVED_3[120]; 2887 __IO uint32_t PIN[2]; /**< Port pin register, array offset: 0x2100, array step: 0x4 */ 2888 uint8_t RESERVED_4[120]; 2889 __IO uint32_t MPIN[2]; /**< Masked port register, array offset: 0x2180, array step: 0x4 */ 2890 uint8_t RESERVED_5[120]; 2891 __IO uint32_t SET[2]; /**< Write: Set register for port Read: output bits for port, array offset: 0x2200, array step: 0x4 */ 2892 uint8_t RESERVED_6[120]; 2893 __O uint32_t CLR[2]; /**< Clear port, array offset: 0x2280, array step: 0x4 */ 2894 uint8_t RESERVED_7[120]; 2895 __O uint32_t NOT[2]; /**< Toggle port, array offset: 0x2300, array step: 0x4 */ 2896 uint8_t RESERVED_8[120]; 2897 __O uint32_t DIRSET[2]; /**< Set pin direction bits for port, array offset: 0x2380, array step: 0x4 */ 2898 uint8_t RESERVED_9[120]; 2899 __O uint32_t DIRCLR[2]; /**< Clear pin direction bits for port, array offset: 0x2400, array step: 0x4 */ 2900 uint8_t RESERVED_10[120]; 2901 __O uint32_t DIRNOT[2]; /**< Toggle pin direction bits for port, array offset: 0x2480, array step: 0x4 */ 2902 } GPIO_Type; 2903 2904 /* ---------------------------------------------------------------------------- 2905 -- GPIO Register Masks 2906 ---------------------------------------------------------------------------- */ 2907 2908 /*! 2909 * @addtogroup GPIO_Register_Masks GPIO Register Masks 2910 * @{ 2911 */ 2912 2913 /*! @name B - Byte pin registers for all port 0 and 1 GPIO pins */ 2914 /*! @{ */ 2915 #define GPIO_B_PBYTE_MASK (0x1U) 2916 #define GPIO_B_PBYTE_SHIFT (0U) 2917 /*! PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, 2918 * except that pins configured as analog I/O always read as 0. One register for each port pin. 2919 * Supported pins depends on the specific device and package. Write: loads the pin's output bit. 2920 * One register for each port pin. Supported pins depends on the specific device and package. 2921 */ 2922 #define GPIO_B_PBYTE(x) (((uint8_t)(((uint8_t)(x)) << GPIO_B_PBYTE_SHIFT)) & GPIO_B_PBYTE_MASK) 2923 /*! @} */ 2924 2925 /* The count of GPIO_B */ 2926 #define GPIO_B_COUNT (2U) 2927 2928 /* The count of GPIO_B */ 2929 #define GPIO_B_COUNT2 (32U) 2930 2931 /*! @name W - Word pin registers for all port 0 and 1 GPIO pins */ 2932 /*! @{ */ 2933 #define GPIO_W_PWORD_MASK (0xFFFFFFFFU) 2934 #define GPIO_W_PWORD_SHIFT (0U) 2935 /*! PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is 2936 * HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be 2937 * read. Writing any value other than 0 will set the output bit. One register for each port pin. 2938 * Supported pins depends on the specific device and package. 2939 */ 2940 #define GPIO_W_PWORD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_W_PWORD_SHIFT)) & GPIO_W_PWORD_MASK) 2941 /*! @} */ 2942 2943 /* The count of GPIO_W */ 2944 #define GPIO_W_COUNT (2U) 2945 2946 /* The count of GPIO_W */ 2947 #define GPIO_W_COUNT2 (32U) 2948 2949 /*! @name DIR - Direction registers */ 2950 /*! @{ */ 2951 #define GPIO_DIR_DIRP_MASK (0xFFFFFFFFU) 2952 #define GPIO_DIR_DIRP_SHIFT (0U) 2953 /*! DIRP - Selects pin direction for pin PIOm_n (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported 2954 * pins depends on the specific device and package. 0 = input. 1 = output. 2955 */ 2956 #define GPIO_DIR_DIRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP_SHIFT)) & GPIO_DIR_DIRP_MASK) 2957 /*! @} */ 2958 2959 /* The count of GPIO_DIR */ 2960 #define GPIO_DIR_COUNT (2U) 2961 2962 /*! @name MASK - Mask register */ 2963 /*! @{ */ 2964 #define GPIO_MASK_MASKP_MASK (0xFFFFFFFFU) 2965 #define GPIO_MASK_MASKP_SHIFT (0U) 2966 /*! MASKP - Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = 2967 * PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = 2968 * Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit 2969 * not affected. 2970 */ 2971 #define GPIO_MASK_MASKP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP_SHIFT)) & GPIO_MASK_MASKP_MASK) 2972 /*! @} */ 2973 2974 /* The count of GPIO_MASK */ 2975 #define GPIO_MASK_COUNT (2U) 2976 2977 /*! @name PIN - Port pin register */ 2978 /*! @{ */ 2979 #define GPIO_PIN_PORT_MASK (0xFFFFFFFFU) 2980 #define GPIO_PIN_PORT_SHIFT (0U) 2981 /*! PORT - Reads pin states or loads output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported 2982 * pins depends on the specific device and package. 0 = Read: pin is low; write: clear output bit. 2983 * 1 = Read: pin is high; write: set output bit. 2984 */ 2985 #define GPIO_PIN_PORT(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT_SHIFT)) & GPIO_PIN_PORT_MASK) 2986 /*! @} */ 2987 2988 /* The count of GPIO_PIN */ 2989 #define GPIO_PIN_COUNT (2U) 2990 2991 /*! @name MPIN - Masked port register */ 2992 /*! @{ */ 2993 #define GPIO_MPIN_MPORTP_MASK (0xFFFFFFFFU) 2994 #define GPIO_MPIN_MPORTP_SHIFT (0U) 2995 /*! MPORTP - Masked port register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on 2996 * the specific device and package. 0 = Read: pin is LOW and/or the corresponding bit in the MASK 2997 * register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 2998 * = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit 2999 * if the corresponding bit in the MASK register is 0. 3000 */ 3001 #define GPIO_MPIN_MPORTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP_SHIFT)) & GPIO_MPIN_MPORTP_MASK) 3002 /*! @} */ 3003 3004 /* The count of GPIO_MPIN */ 3005 #define GPIO_MPIN_COUNT (2U) 3006 3007 /*! @name SET - Write: Set register for port Read: output bits for port */ 3008 /*! @{ */ 3009 #define GPIO_SET_SETP_MASK (0xFFFFFFFFU) 3010 #define GPIO_SET_SETP_SHIFT (0U) 3011 /*! SETP - Read or set output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on 3012 * the specific device and package. 0 = Read: output bit: write: no operation. 1 = Read: output 3013 * bit; write: set output bit. 3014 */ 3015 #define GPIO_SET_SETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_SET_SETP_SHIFT)) & GPIO_SET_SETP_MASK) 3016 /*! @} */ 3017 3018 /* The count of GPIO_SET */ 3019 #define GPIO_SET_COUNT (2U) 3020 3021 /*! @name CLR - Clear port */ 3022 /*! @{ */ 3023 #define GPIO_CLR_CLRP_MASK (0xFFFFFFFFU) 3024 #define GPIO_CLR_CLRP_SHIFT (0U) 3025 /*! CLRP - Clear output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the 3026 * specific device and package. 0 = No operation. 1 = Clear output bit. 3027 */ 3028 #define GPIO_CLR_CLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP_SHIFT)) & GPIO_CLR_CLRP_MASK) 3029 /*! @} */ 3030 3031 /* The count of GPIO_CLR */ 3032 #define GPIO_CLR_COUNT (2U) 3033 3034 /*! @name NOT - Toggle port */ 3035 /*! @{ */ 3036 #define GPIO_NOT_NOTP_MASK (0xFFFFFFFFU) 3037 #define GPIO_NOT_NOTP_SHIFT (0U) 3038 /*! NOTP - Toggle output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the 3039 * specific device and package. 0 = no operation. 1 = Toggle output bit. 3040 */ 3041 #define GPIO_NOT_NOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP_SHIFT)) & GPIO_NOT_NOTP_MASK) 3042 /*! @} */ 3043 3044 /* The count of GPIO_NOT */ 3045 #define GPIO_NOT_COUNT (2U) 3046 3047 /*! @name DIRSET - Set pin direction bits for port */ 3048 /*! @{ */ 3049 #define GPIO_DIRSET_DIRSETP_MASK (0x1FFFFFFFU) 3050 #define GPIO_DIRSET_DIRSETP_SHIFT (0U) 3051 /*! DIRSETP - Set direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on 3052 * the specific device and package. 0 = No operation. 1 = Set direction bit. 3053 */ 3054 #define GPIO_DIRSET_DIRSETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP_SHIFT)) & GPIO_DIRSET_DIRSETP_MASK) 3055 /*! @} */ 3056 3057 /* The count of GPIO_DIRSET */ 3058 #define GPIO_DIRSET_COUNT (2U) 3059 3060 /*! @name DIRCLR - Clear pin direction bits for port */ 3061 /*! @{ */ 3062 #define GPIO_DIRCLR_DIRCLRP_MASK (0x1FFFFFFFU) 3063 #define GPIO_DIRCLR_DIRCLRP_SHIFT (0U) 3064 /*! DIRCLRP - Clear direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on 3065 * the specific device and package. 0 = No operation. 1 = Clear direction bit. 3066 */ 3067 #define GPIO_DIRCLR_DIRCLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP_SHIFT)) & GPIO_DIRCLR_DIRCLRP_MASK) 3068 /*! @} */ 3069 3070 /* The count of GPIO_DIRCLR */ 3071 #define GPIO_DIRCLR_COUNT (2U) 3072 3073 /*! @name DIRNOT - Toggle pin direction bits for port */ 3074 /*! @{ */ 3075 #define GPIO_DIRNOT_DIRNOTP_MASK (0x1FFFFFFFU) 3076 #define GPIO_DIRNOT_DIRNOTP_SHIFT (0U) 3077 /*! DIRNOTP - Toggle direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends 3078 * on the specific device and package. 0 = no operation. 1 = Toggle direction bit. 3079 */ 3080 #define GPIO_DIRNOT_DIRNOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRNOT_DIRNOTP_SHIFT)) & GPIO_DIRNOT_DIRNOTP_MASK) 3081 /*! @} */ 3082 3083 /* The count of GPIO_DIRNOT */ 3084 #define GPIO_DIRNOT_COUNT (2U) 3085 3086 3087 /*! 3088 * @} 3089 */ /* end of group GPIO_Register_Masks */ 3090 3091 3092 /* GPIO - Peripheral instance base addresses */ 3093 /** Peripheral GPIO base address */ 3094 #define GPIO_BASE (0x4008C000u) 3095 /** Peripheral GPIO base pointer */ 3096 #define GPIO ((GPIO_Type *)GPIO_BASE) 3097 /** Array initializer of GPIO peripheral base addresses */ 3098 #define GPIO_BASE_ADDRS { GPIO_BASE } 3099 /** Array initializer of GPIO peripheral base pointers */ 3100 #define GPIO_BASE_PTRS { GPIO } 3101 3102 /*! 3103 * @} 3104 */ /* end of group GPIO_Peripheral_Access_Layer */ 3105 3106 3107 /* ---------------------------------------------------------------------------- 3108 -- I2C Peripheral Access Layer 3109 ---------------------------------------------------------------------------- */ 3110 3111 /*! 3112 * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer 3113 * @{ 3114 */ 3115 3116 /** I2C - Register Layout Typedef */ 3117 typedef struct { 3118 uint8_t RESERVED_0[2048]; 3119 __IO uint32_t CFG; /**< Configuration for shared functions., offset: 0x800 */ 3120 __IO uint32_t STAT; /**< Status register for Master, Slave, and Monitor functions., offset: 0x804 */ 3121 __IO uint32_t INTENSET; /**< Interrupt Enable Set and read register., offset: 0x808 */ 3122 __O uint32_t INTENCLR; /**< Interrupt Enable Clear register., offset: 0x80C */ 3123 __IO uint32_t TIMEOUT; /**< Time-out value register., offset: 0x810 */ 3124 __IO uint32_t CLKDIV; /**< Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function., offset: 0x814 */ 3125 __I uint32_t INTSTAT; /**< Interrupt Status register for Master, Slave, and Monitor functions., offset: 0x818 */ 3126 uint8_t RESERVED_1[4]; 3127 __IO uint32_t MSTCTL; /**< Master control register., offset: 0x820 */ 3128 __IO uint32_t MSTTIME; /**< Master timing configuration., offset: 0x824 */ 3129 __IO uint32_t MSTDAT; /**< Combined Master receiver and transmitter data register., offset: 0x828 */ 3130 uint8_t RESERVED_2[20]; 3131 __IO uint32_t SLVCTL; /**< Slave control register., offset: 0x840 */ 3132 __IO uint32_t SLVDAT; /**< Combined Slave receiver and transmitter data register., offset: 0x844 */ 3133 __IO uint32_t SLVADR[4]; /**< Slave address register., array offset: 0x848, array step: 0x4 */ 3134 __IO uint32_t SLVQUAL0; /**< Slave Qualification for address 0., offset: 0x858 */ 3135 uint8_t RESERVED_3[36]; 3136 __I uint32_t MONRXDAT; /**< Monitor receiver data register., offset: 0x880 */ 3137 } I2C_Type; 3138 3139 /* ---------------------------------------------------------------------------- 3140 -- I2C Register Masks 3141 ---------------------------------------------------------------------------- */ 3142 3143 /*! 3144 * @addtogroup I2C_Register_Masks I2C Register Masks 3145 * @{ 3146 */ 3147 3148 /*! @name CFG - Configuration for shared functions. */ 3149 /*! @{ */ 3150 #define I2C_CFG_MSTEN_MASK (0x1U) 3151 #define I2C_CFG_MSTEN_SHIFT (0U) 3152 /*! MSTEN - Master Enable. When disabled, configurations settings for the Master function are not 3153 * changed, but the Master function is internally reset. 3154 * 0b0..Disabled. The I2C Master function is disabled. 3155 * 0b1..Enabled. The I2C Master function is enabled. 3156 */ 3157 #define I2C_CFG_MSTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MSTEN_SHIFT)) & I2C_CFG_MSTEN_MASK) 3158 #define I2C_CFG_SLVEN_MASK (0x2U) 3159 #define I2C_CFG_SLVEN_SHIFT (1U) 3160 /*! SLVEN - Slave Enable. When disabled, configurations settings for the Slave function are not 3161 * changed, but the Slave function is internally reset. 3162 * 0b0..Disabled. The I2C slave function is disabled. 3163 * 0b1..Enabled. The I2C slave function is enabled. 3164 */ 3165 #define I2C_CFG_SLVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_SLVEN_SHIFT)) & I2C_CFG_SLVEN_MASK) 3166 #define I2C_CFG_MONEN_MASK (0x4U) 3167 #define I2C_CFG_MONEN_SHIFT (2U) 3168 /*! MONEN - Monitor Enable. When disabled, configurations settings for the Monitor function are not 3169 * changed, but the Monitor function is internally reset. 3170 * 0b0..Disabled. The I2C Monitor function is disabled. 3171 * 0b1..Enabled. The I2C Monitor function is enabled. 3172 */ 3173 #define I2C_CFG_MONEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONEN_SHIFT)) & I2C_CFG_MONEN_MASK) 3174 #define I2C_CFG_TIMEOUTEN_MASK (0x8U) 3175 #define I2C_CFG_TIMEOUTEN_SHIFT (3U) 3176 /*! TIMEOUTEN - I2C bus Time-out Enable. When disabled, the time-out function is internally reset. 3177 * 0b0..Disabled. Time-out function is disabled. 3178 * 0b1..Enabled. Time-out function is enabled. Both types of time-out flags will be generated and will cause 3179 * interrupts if they are enabled. Typically, only one time-out will be used in a system. 3180 */ 3181 #define I2C_CFG_TIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_TIMEOUTEN_SHIFT)) & I2C_CFG_TIMEOUTEN_MASK) 3182 #define I2C_CFG_MONCLKSTR_MASK (0x10U) 3183 #define I2C_CFG_MONCLKSTR_SHIFT (4U) 3184 /*! MONCLKSTR - Monitor function Clock Stretching. 3185 * 0b0..Disabled. The Monitor function will not perform clock stretching. Software or DMA may not always be able 3186 * to read data provided by the Monitor function before it is overwritten. This mode may be used when 3187 * non-invasive monitoring is critical. 3188 * 0b1..Enabled. The Monitor function will perform clock stretching in order to ensure that software or DMA can 3189 * read all incoming data supplied by the Monitor function. 3190 */ 3191 #define I2C_CFG_MONCLKSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONCLKSTR_SHIFT)) & I2C_CFG_MONCLKSTR_MASK) 3192 #define I2C_CFG_HSCAPABLE_MASK (0x20U) 3193 #define I2C_CFG_HSCAPABLE_SHIFT (5U) 3194 /*! HSCAPABLE - High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive 3195 * and filter, as well as the timing for certain I2C signalling, enabling High-speed mode applies 3196 * to all functions: Master, Slave, and Monitor. 3197 * 0b0..Fast-mode plus. The I 2C interface will support Standard-mode, Fast-mode, and Fast-mode Plus, to the 3198 * extent that the pin electronics support these modes. Any changes that need to be made to the pin controls, 3199 * such as changing the drive strength or filtering, must be made by software via the IOCON register associated 3200 * with each I2C pin, 3201 * 0b1..High-speed. In addition to Standard-mode, Fast-mode, and Fast-mode Plus, the I 2C interface will support 3202 * High-speed mode to the extent that the pin electronics support these modes. See Section 25.7.2.2 for more 3203 * information. 3204 */ 3205 #define I2C_CFG_HSCAPABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_HSCAPABLE_SHIFT)) & I2C_CFG_HSCAPABLE_MASK) 3206 /*! @} */ 3207 3208 /*! @name STAT - Status register for Master, Slave, and Monitor functions. */ 3209 /*! @{ */ 3210 #define I2C_STAT_MSTPENDING_MASK (0x1U) 3211 #define I2C_STAT_MSTPENDING_SHIFT (0U) 3212 /*! MSTPENDING - Master Pending. Indicates that the Master is waiting to continue communication on 3213 * the I2C-bus (pending) or is idle. When the master is pending, the MSTSTATE bits indicate what 3214 * type of software service if any the master expects. This flag will cause an interrupt when set 3215 * if, enabled via the INTENSET register. The MSTPENDING flag is not set when the DMA is handling 3216 * an event (if the MSTDMA bit in the MSTCTL register is set). If the master is in the idle 3217 * state, and no communication is needed, mask this interrupt. 3218 * 0b0..In progress. Communication is in progress and the Master function is busy and cannot currently accept a command. 3219 * 0b1..Pending. The Master function needs software service or is in the idle state. If the master is not in the 3220 * idle state, it is waiting to receive or transmit data or the NACK bit. 3221 */ 3222 #define I2C_STAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTPENDING_SHIFT)) & I2C_STAT_MSTPENDING_MASK) 3223 #define I2C_STAT_MSTSTATE_MASK (0xEU) 3224 #define I2C_STAT_MSTSTATE_SHIFT (1U) 3225 /*! MSTSTATE - Master State code. The master state code reflects the master state when the 3226 * MSTPENDING bit is set, that is the master is pending or in the idle state. Each value of this field 3227 * indicates a specific required service for the Master function. All other values are reserved. See 3228 * Table 400 for details of state values and appropriate responses. 3229 * 0b000..Idle. The Master function is available to be used for a new transaction. 3230 * 0b001..Receive ready. Received data available (Master Receiver mode). Address plus Read was previously sent and Acknowledged by slave. 3231 * 0b010..Transmit ready. Data can be transmitted (Master Transmitter mode). Address plus Write was previously sent and Acknowledged by slave. 3232 * 0b011..NACK Address. Slave NACKed address. 3233 * 0b100..NACK Data. Slave NACKed transmitted data. 3234 */ 3235 #define I2C_STAT_MSTSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTATE_SHIFT)) & I2C_STAT_MSTSTATE_MASK) 3236 #define I2C_STAT_MSTARBLOSS_MASK (0x10U) 3237 #define I2C_STAT_MSTARBLOSS_SHIFT (4U) 3238 /*! MSTARBLOSS - Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to 3239 * this bit. It is also cleared automatically a 1 is written to MSTCONTINUE. 3240 * 0b0..No Arbitration Loss has occurred. 3241 * 0b1..Arbitration loss. The Master function has experienced an Arbitration Loss. At this point, the Master 3242 * function has already stopped driving the bus and gone to an idle state. Software can respond by doing nothing, 3243 * or by sending a Start in order to attempt to gain control of the bus when it next becomes idle. 3244 */ 3245 #define I2C_STAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTARBLOSS_SHIFT)) & I2C_STAT_MSTARBLOSS_MASK) 3246 #define I2C_STAT_MSTSTSTPERR_MASK (0x40U) 3247 #define I2C_STAT_MSTSTSTPERR_SHIFT (6U) 3248 /*! MSTSTSTPERR - Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to 3249 * this bit. It is also cleared automatically a 1 is written to MSTCONTINUE. 3250 * 0b0..No Start/Stop Error has occurred. 3251 * 0b1..The Master function has experienced a Start/Stop Error. A Start or Stop was detected at a time when it is 3252 * not allowed by the I2C specification. The Master interface has stopped driving the bus and gone to an 3253 * idle state, no action is required. A request for a Start could be made, or software could attempt to insure 3254 * that the bus has not stalled. 3255 */ 3256 #define I2C_STAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTSTPERR_SHIFT)) & I2C_STAT_MSTSTSTPERR_MASK) 3257 #define I2C_STAT_SLVPENDING_MASK (0x100U) 3258 #define I2C_STAT_SLVPENDING_SHIFT (8U) 3259 /*! SLVPENDING - Slave Pending. Indicates that the Slave function is waiting to continue 3260 * communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if 3261 * enabled via INTENSET. The SLVPENDING flag is not set when the DMA is handling an event (if the 3262 * SLVDMA bit in the SLVCTL register is set). The SLVPENDING flag is read-only and is 3263 * automatically cleared when a 1 is written to the SLVCONTINUE bit in the SLVCTL register. The point in time 3264 * when SlvPending is set depends on whether the I2C interface is in HSCAPABLE mode. See Section 3265 * 25.7.2.2.2. When the I2C interface is configured to be HSCAPABLE, HS master codes are 3266 * detected automatically. Due to the requirements of the HS I2C specification, slave addresses must 3267 * also be detected automatically, since the address must be acknowledged before the clock can be 3268 * stretched. 3269 * 0b0..In progress. The Slave function does not currently need service. 3270 * 0b1..Pending. The Slave function needs service. Information on what is needed can be found in the adjacent SLVSTATE field. 3271 */ 3272 #define I2C_STAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVPENDING_SHIFT)) & I2C_STAT_SLVPENDING_MASK) 3273 #define I2C_STAT_SLVSTATE_MASK (0x600U) 3274 #define I2C_STAT_SLVSTATE_SHIFT (9U) 3275 /*! SLVSTATE - Slave State code. Each value of this field indicates a specific required service for 3276 * the Slave function. All other values are reserved. See Table 401 for state values and actions. 3277 * note that the occurrence of some states and how they are handled are affected by DMA mode and 3278 * Automatic Operation modes. 3279 * 0b00..Slave address. Address plus R/W received. At least one of the four slave addresses has been matched by hardware. 3280 * 0b01..Slave receive. Received data is available (Slave Receiver mode). 3281 * 0b10..Slave transmit. Data can be transmitted (Slave Transmitter mode). 3282 */ 3283 #define I2C_STAT_SLVSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSTATE_SHIFT)) & I2C_STAT_SLVSTATE_MASK) 3284 #define I2C_STAT_SLVNOTSTR_MASK (0x800U) 3285 #define I2C_STAT_SLVNOTSTR_SHIFT (11U) 3286 /*! SLVNOTSTR - Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. 3287 * This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave 3288 * operation. This read-only flag reflects the slave function status in real time. 3289 * 0b0..Stretching. The slave function is currently stretching the I2C bus clock. Deep-Sleep or Power-down mode cannot be entered at this time. 3290 * 0b1..Not stretching. The slave function is not currently stretching the I 2C bus clock. Deep-sleep or 3291 * Power-down mode could be entered at this time. 3292 */ 3293 #define I2C_STAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVNOTSTR_SHIFT)) & I2C_STAT_SLVNOTSTR_MASK) 3294 #define I2C_STAT_SLVIDX_MASK (0x3000U) 3295 #define I2C_STAT_SLVIDX_SHIFT (12U) 3296 /*! SLVIDX - Slave address match Index. This field is valid when the I2C slave function has been 3297 * selected by receiving an address that matches one of the slave addresses defined by any enabled 3298 * slave address registers, and provides an identification of the address that was matched. It is 3299 * possible that more than one address could be matched, but only one match can be reported here. 3300 * 0b00..Address 0. Slave address 0 was matched. 3301 * 0b01..Address 1. Slave address 1 was matched. 3302 * 0b10..Address 2. Slave address 2 was matched. 3303 * 0b11..Address 3. Slave address 3 was matched. 3304 */ 3305 #define I2C_STAT_SLVIDX(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVIDX_SHIFT)) & I2C_STAT_SLVIDX_MASK) 3306 #define I2C_STAT_SLVSEL_MASK (0x4000U) 3307 #define I2C_STAT_SLVSEL_SHIFT (14U) 3308 /*! SLVSEL - Slave selected flag. SLVSEL is set after an address match when software tells the Slave 3309 * function to acknowledge the address, or when the address has been automatically acknowledged. 3310 * It is cleared when another address cycle presents an address that does not match an enabled 3311 * address on the Slave function, when slave software decides to NACK a matched address, when 3312 * there is a Stop detected on the bus, when the master NACKs slave data, and in some combinations of 3313 * Automatic Operation. SLVSEL is not cleared if software NACKs data. 3314 * 0b0..Not selected. The Slave function is not currently selected. 3315 * 0b1..Selected. The Slave function is currently selected. 3316 */ 3317 #define I2C_STAT_SLVSEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSEL_SHIFT)) & I2C_STAT_SLVSEL_MASK) 3318 #define I2C_STAT_SLVDESEL_MASK (0x8000U) 3319 #define I2C_STAT_SLVDESEL_SHIFT (15U) 3320 /*! SLVDESEL - Slave Deselected flag. This flag will cause an interrupt when set if enabled via 3321 * INTENSET. This flag can be cleared by writing a 1 to this bit. 3322 * 0b0..Not deselected. The Slave function has not become deselected. This does not mean that it is currently 3323 * selected. That information can be found in the SLVSEL flag. 3324 * 0b1..Deselected. The Slave function has become deselected. This is specifically caused by the SLVSEL flag 3325 * changing from 1 to 0. See the description of SLVSEL for details on when that event occurs. 3326 */ 3327 #define I2C_STAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVDESEL_SHIFT)) & I2C_STAT_SLVDESEL_MASK) 3328 #define I2C_STAT_MONRDY_MASK (0x10000U) 3329 #define I2C_STAT_MONRDY_SHIFT (16U) 3330 /*! MONRDY - Monitor Ready. This flag is cleared when the MONRXDAT register is read. 3331 * 0b0..No data. The Monitor function does not currently have data available. 3332 * 0b1..Data waiting. The Monitor function has data waiting to be read. 3333 */ 3334 #define I2C_STAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONRDY_SHIFT)) & I2C_STAT_MONRDY_MASK) 3335 #define I2C_STAT_MONOV_MASK (0x20000U) 3336 #define I2C_STAT_MONOV_SHIFT (17U) 3337 /*! MONOV - Monitor Overflow flag. 3338 * 0b0..No overrun. Monitor data has not overrun. 3339 * 0b1..Overrun. A Monitor data overrun has occurred. This can only happen when Monitor clock stretching not 3340 * enabled via the MONCLKSTR bit in the CFG register. Writing 1 to this bit clears the flag. 3341 */ 3342 #define I2C_STAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONOV_SHIFT)) & I2C_STAT_MONOV_MASK) 3343 #define I2C_STAT_MONACTIVE_MASK (0x40000U) 3344 #define I2C_STAT_MONACTIVE_SHIFT (18U) 3345 /*! MONACTIVE - Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to 3346 * be active. Active is defined here as when some Master is on the bus: a bus Start has occurred 3347 * more recently than a bus Stop. 3348 * 0b0..Inactive. The Monitor function considers the I2C bus to be inactive. 3349 * 0b1..Active. The Monitor function considers the I2C bus to be active. 3350 */ 3351 #define I2C_STAT_MONACTIVE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONACTIVE_SHIFT)) & I2C_STAT_MONACTIVE_MASK) 3352 #define I2C_STAT_MONIDLE_MASK (0x80000U) 3353 #define I2C_STAT_MONIDLE_SHIFT (19U) 3354 /*! MONIDLE - Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change 3355 * from active to inactive. This can be used by software to decide when to process data 3356 * accumulated by the Monitor function. This flag will cause an interrupt when set if enabled via the 3357 * INTENSET register. The flag can be cleared by writing a 1 to this bit. 3358 * 0b0..Not idle. The I2C bus is not idle, or this flag has been cleared by software. 3359 * 0b1..Idle. The I2C bus has gone idle at least once since the last time this flag was cleared by software. 3360 */ 3361 #define I2C_STAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONIDLE_SHIFT)) & I2C_STAT_MONIDLE_MASK) 3362 #define I2C_STAT_EVENTTIMEOUT_MASK (0x1000000U) 3363 #define I2C_STAT_EVENTTIMEOUT_SHIFT (24U) 3364 /*! EVENTTIMEOUT - Event Time-out Interrupt flag. Indicates when the time between events has been 3365 * longer than the time specified by the TIMEOUT register. Events include Start, Stop, and clock 3366 * edges. The flag is cleared by writing a 1 to this bit. No time-out is created when the I2C-bus 3367 * is idle. 3368 * 0b0..No time-out. I2C bus events have not caused a time-out. 3369 * 0b1..Event time-out. The time between I2C bus events has been longer than the time specified by the TIMEOUT register. 3370 */ 3371 #define I2C_STAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_EVENTTIMEOUT_SHIFT)) & I2C_STAT_EVENTTIMEOUT_MASK) 3372 #define I2C_STAT_SCLTIMEOUT_MASK (0x2000000U) 3373 #define I2C_STAT_SCLTIMEOUT_SHIFT (25U) 3374 /*! SCLTIMEOUT - SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the 3375 * time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit. 3376 * 0b0..No time-out. SCL low time has not caused a time-out. 3377 * 0b1..Time-out. SCL low time has caused a time-out. 3378 */ 3379 #define I2C_STAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SCLTIMEOUT_SHIFT)) & I2C_STAT_SCLTIMEOUT_MASK) 3380 /*! @} */ 3381 3382 /*! @name INTENSET - Interrupt Enable Set and read register. */ 3383 /*! @{ */ 3384 #define I2C_INTENSET_MSTPENDINGEN_MASK (0x1U) 3385 #define I2C_INTENSET_MSTPENDINGEN_SHIFT (0U) 3386 /*! MSTPENDINGEN - Master Pending interrupt Enable. 3387 * 0b0..Disabled. The MstPending interrupt is disabled. 3388 * 0b1..Enabled. The MstPending interrupt is enabled. 3389 */ 3390 #define I2C_INTENSET_MSTPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTPENDINGEN_SHIFT)) & I2C_INTENSET_MSTPENDINGEN_MASK) 3391 #define I2C_INTENSET_MSTARBLOSSEN_MASK (0x10U) 3392 #define I2C_INTENSET_MSTARBLOSSEN_SHIFT (4U) 3393 /*! MSTARBLOSSEN - Master Arbitration Loss interrupt Enable. 3394 * 0b0..Disabled. The MstArbLoss interrupt is disabled. 3395 * 0b1..Enabled. The MstArbLoss interrupt is enabled. 3396 */ 3397 #define I2C_INTENSET_MSTARBLOSSEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTARBLOSSEN_SHIFT)) & I2C_INTENSET_MSTARBLOSSEN_MASK) 3398 #define I2C_INTENSET_MSTSTSTPERREN_MASK (0x40U) 3399 #define I2C_INTENSET_MSTSTSTPERREN_SHIFT (6U) 3400 /*! MSTSTSTPERREN - Master Start/Stop Error interrupt Enable. 3401 * 0b0..Disabled. The MstStStpErr interrupt is disabled. 3402 * 0b1..Enabled. The MstStStpErr interrupt is enabled. 3403 */ 3404 #define I2C_INTENSET_MSTSTSTPERREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTSTSTPERREN_SHIFT)) & I2C_INTENSET_MSTSTSTPERREN_MASK) 3405 #define I2C_INTENSET_SLVPENDINGEN_MASK (0x100U) 3406 #define I2C_INTENSET_SLVPENDINGEN_SHIFT (8U) 3407 /*! SLVPENDINGEN - Slave Pending interrupt Enable. 3408 * 0b0..Disabled. The SlvPending interrupt is disabled. 3409 * 0b1..Enabled. The SlvPending interrupt is enabled. 3410 */ 3411 #define I2C_INTENSET_SLVPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVPENDINGEN_SHIFT)) & I2C_INTENSET_SLVPENDINGEN_MASK) 3412 #define I2C_INTENSET_SLVNOTSTREN_MASK (0x800U) 3413 #define I2C_INTENSET_SLVNOTSTREN_SHIFT (11U) 3414 /*! SLVNOTSTREN - Slave Not Stretching interrupt Enable. 3415 * 0b0..Disabled. The SlvNotStr interrupt is disabled. 3416 * 0b1..Enabled. The SlvNotStr interrupt is enabled. 3417 */ 3418 #define I2C_INTENSET_SLVNOTSTREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVNOTSTREN_SHIFT)) & I2C_INTENSET_SLVNOTSTREN_MASK) 3419 #define I2C_INTENSET_SLVDESELEN_MASK (0x8000U) 3420 #define I2C_INTENSET_SLVDESELEN_SHIFT (15U) 3421 /*! SLVDESELEN - Slave Deselect interrupt Enable. 3422 * 0b0..Disabled. The SlvDeSel interrupt is disabled. 3423 * 0b1..Enabled. The SlvDeSel interrupt is enabled. 3424 */ 3425 #define I2C_INTENSET_SLVDESELEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVDESELEN_SHIFT)) & I2C_INTENSET_SLVDESELEN_MASK) 3426 #define I2C_INTENSET_MONRDYEN_MASK (0x10000U) 3427 #define I2C_INTENSET_MONRDYEN_SHIFT (16U) 3428 /*! MONRDYEN - Monitor data Ready interrupt Enable. 3429 * 0b0..Disabled. The MonRdy interrupt is disabled. 3430 * 0b1..Enabled. The MonRdy interrupt is enabled. 3431 */ 3432 #define I2C_INTENSET_MONRDYEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONRDYEN_SHIFT)) & I2C_INTENSET_MONRDYEN_MASK) 3433 #define I2C_INTENSET_MONOVEN_MASK (0x20000U) 3434 #define I2C_INTENSET_MONOVEN_SHIFT (17U) 3435 /*! MONOVEN - Monitor Overrun interrupt Enable. 3436 * 0b0..Disabled. The MonOv interrupt is disabled. 3437 * 0b1..Enabled. The MonOv interrupt is enabled. 3438 */ 3439 #define I2C_INTENSET_MONOVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONOVEN_SHIFT)) & I2C_INTENSET_MONOVEN_MASK) 3440 #define I2C_INTENSET_MONIDLEEN_MASK (0x80000U) 3441 #define I2C_INTENSET_MONIDLEEN_SHIFT (19U) 3442 /*! MONIDLEEN - Monitor Idle interrupt Enable. 3443 * 0b0..Disabled. The MonIdle interrupt is disabled. 3444 * 0b1..Enabled. The MonIdle interrupt is enabled. 3445 */ 3446 #define I2C_INTENSET_MONIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONIDLEEN_SHIFT)) & I2C_INTENSET_MONIDLEEN_MASK) 3447 #define I2C_INTENSET_EVENTTIMEOUTEN_MASK (0x1000000U) 3448 #define I2C_INTENSET_EVENTTIMEOUTEN_SHIFT (24U) 3449 /*! EVENTTIMEOUTEN - Event time-out interrupt Enable. 3450 * 0b0..Disabled. The Event time-out interrupt is disabled. 3451 * 0b1..Enabled. The Event time-out interrupt is enabled. 3452 */ 3453 #define I2C_INTENSET_EVENTTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_EVENTTIMEOUTEN_SHIFT)) & I2C_INTENSET_EVENTTIMEOUTEN_MASK) 3454 #define I2C_INTENSET_SCLTIMEOUTEN_MASK (0x2000000U) 3455 #define I2C_INTENSET_SCLTIMEOUTEN_SHIFT (25U) 3456 /*! SCLTIMEOUTEN - SCL time-out interrupt Enable. 3457 * 0b0..Disabled. The SCL time-out interrupt is disabled. 3458 * 0b1..Enabled. The SCL time-out interrupt is enabled. 3459 */ 3460 #define I2C_INTENSET_SCLTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SCLTIMEOUTEN_SHIFT)) & I2C_INTENSET_SCLTIMEOUTEN_MASK) 3461 /*! @} */ 3462 3463 /*! @name INTENCLR - Interrupt Enable Clear register. */ 3464 /*! @{ */ 3465 #define I2C_INTENCLR_MSTPENDINGCLR_MASK (0x1U) 3466 #define I2C_INTENCLR_MSTPENDINGCLR_SHIFT (0U) 3467 /*! MSTPENDINGCLR - Master Pending interrupt clear. Writing 1 to this bit clears the corresponding 3468 * bit in the INTENSET register if implemented. 3469 */ 3470 #define I2C_INTENCLR_MSTPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTPENDINGCLR_SHIFT)) & I2C_INTENCLR_MSTPENDINGCLR_MASK) 3471 #define I2C_INTENCLR_MSTARBLOSSCLR_MASK (0x10U) 3472 #define I2C_INTENCLR_MSTARBLOSSCLR_SHIFT (4U) 3473 /*! MSTARBLOSSCLR - Master Arbitration Loss interrupt clear. 3474 */ 3475 #define I2C_INTENCLR_MSTARBLOSSCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTARBLOSSCLR_SHIFT)) & I2C_INTENCLR_MSTARBLOSSCLR_MASK) 3476 #define I2C_INTENCLR_MSTSTSTPERRCLR_MASK (0x40U) 3477 #define I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT (6U) 3478 /*! MSTSTSTPERRCLR - Master Start/Stop Error interrupt clear. 3479 */ 3480 #define I2C_INTENCLR_MSTSTSTPERRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT)) & I2C_INTENCLR_MSTSTSTPERRCLR_MASK) 3481 #define I2C_INTENCLR_SLVPENDINGCLR_MASK (0x100U) 3482 #define I2C_INTENCLR_SLVPENDINGCLR_SHIFT (8U) 3483 /*! SLVPENDINGCLR - Slave Pending interrupt clear. 3484 */ 3485 #define I2C_INTENCLR_SLVPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVPENDINGCLR_SHIFT)) & I2C_INTENCLR_SLVPENDINGCLR_MASK) 3486 #define I2C_INTENCLR_SLVNOTSTRCLR_MASK (0x800U) 3487 #define I2C_INTENCLR_SLVNOTSTRCLR_SHIFT (11U) 3488 /*! SLVNOTSTRCLR - Slave Not Stretching interrupt clear. 3489 */ 3490 #define I2C_INTENCLR_SLVNOTSTRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVNOTSTRCLR_SHIFT)) & I2C_INTENCLR_SLVNOTSTRCLR_MASK) 3491 #define I2C_INTENCLR_SLVDESELCLR_MASK (0x8000U) 3492 #define I2C_INTENCLR_SLVDESELCLR_SHIFT (15U) 3493 /*! SLVDESELCLR - Slave Deselect interrupt clear. 3494 */ 3495 #define I2C_INTENCLR_SLVDESELCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVDESELCLR_SHIFT)) & I2C_INTENCLR_SLVDESELCLR_MASK) 3496 #define I2C_INTENCLR_MONRDYCLR_MASK (0x10000U) 3497 #define I2C_INTENCLR_MONRDYCLR_SHIFT (16U) 3498 /*! MONRDYCLR - Monitor data Ready interrupt clear. 3499 */ 3500 #define I2C_INTENCLR_MONRDYCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONRDYCLR_SHIFT)) & I2C_INTENCLR_MONRDYCLR_MASK) 3501 #define I2C_INTENCLR_MONOVCLR_MASK (0x20000U) 3502 #define I2C_INTENCLR_MONOVCLR_SHIFT (17U) 3503 /*! MONOVCLR - Monitor Overrun interrupt clear. 3504 */ 3505 #define I2C_INTENCLR_MONOVCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONOVCLR_SHIFT)) & I2C_INTENCLR_MONOVCLR_MASK) 3506 #define I2C_INTENCLR_MONIDLECLR_MASK (0x80000U) 3507 #define I2C_INTENCLR_MONIDLECLR_SHIFT (19U) 3508 /*! MONIDLECLR - Monitor Idle interrupt clear. 3509 */ 3510 #define I2C_INTENCLR_MONIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONIDLECLR_SHIFT)) & I2C_INTENCLR_MONIDLECLR_MASK) 3511 #define I2C_INTENCLR_EVENTTIMEOUTCLR_MASK (0x1000000U) 3512 #define I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT (24U) 3513 /*! EVENTTIMEOUTCLR - Event time-out interrupt clear. 3514 */ 3515 #define I2C_INTENCLR_EVENTTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_EVENTTIMEOUTCLR_MASK) 3516 #define I2C_INTENCLR_SCLTIMEOUTCLR_MASK (0x2000000U) 3517 #define I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT (25U) 3518 /*! SCLTIMEOUTCLR - SCL time-out interrupt clear. 3519 */ 3520 #define I2C_INTENCLR_SCLTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_SCLTIMEOUTCLR_MASK) 3521 /*! @} */ 3522 3523 /*! @name TIMEOUT - Time-out value register. */ 3524 /*! @{ */ 3525 #define I2C_TIMEOUT_TOMIN_MASK (0xFU) 3526 #define I2C_TIMEOUT_TOMIN_SHIFT (0U) 3527 /*! TOMIN - Time-out time value, bottom four bits. These are hard-wired to 0xF. This gives a minimum 3528 * time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks. 3529 */ 3530 #define I2C_TIMEOUT_TOMIN(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TOMIN_SHIFT)) & I2C_TIMEOUT_TOMIN_MASK) 3531 #define I2C_TIMEOUT_TO_MASK (0xFFF0U) 3532 #define I2C_TIMEOUT_TO_SHIFT (4U) 3533 /*! TO - Time-out time value. Specifies the time-out interval value in increments of 16 I 2C 3534 * function clocks, as defined by the CLKDIV register. To change this value while I2C is in operation, 3535 * disable all time-outs, write a new value to TIMEOUT, then re-enable time-outs. 0x000 = A 3536 * time-out will occur after 16 counts of the I2C function clock. 0x001 = A time-out will occur after 3537 * 32 counts of the I2C function clock. 0xFFF = A time-out will occur after 65,536 counts of the 3538 * I2C function clock. 3539 */ 3540 #define I2C_TIMEOUT_TO(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TO_SHIFT)) & I2C_TIMEOUT_TO_MASK) 3541 /*! @} */ 3542 3543 /*! @name CLKDIV - Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function. */ 3544 /*! @{ */ 3545 #define I2C_CLKDIV_DIVVAL_MASK (0xFFFFU) 3546 #define I2C_CLKDIV_DIVVAL_SHIFT (0U) 3547 /*! DIVVAL - This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that 3548 * need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = 3549 * FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3 before use. 0xFFFF = FCLK is 3550 * divided by 65,536 before use. 3551 */ 3552 #define I2C_CLKDIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << I2C_CLKDIV_DIVVAL_SHIFT)) & I2C_CLKDIV_DIVVAL_MASK) 3553 /*! @} */ 3554 3555 /*! @name INTSTAT - Interrupt Status register for Master, Slave, and Monitor functions. */ 3556 /*! @{ */ 3557 #define I2C_INTSTAT_MSTPENDING_MASK (0x1U) 3558 #define I2C_INTSTAT_MSTPENDING_SHIFT (0U) 3559 /*! MSTPENDING - Master Pending. 3560 */ 3561 #define I2C_INTSTAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTPENDING_SHIFT)) & I2C_INTSTAT_MSTPENDING_MASK) 3562 #define I2C_INTSTAT_MSTARBLOSS_MASK (0x10U) 3563 #define I2C_INTSTAT_MSTARBLOSS_SHIFT (4U) 3564 /*! MSTARBLOSS - Master Arbitration Loss flag. 3565 */ 3566 #define I2C_INTSTAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTARBLOSS_SHIFT)) & I2C_INTSTAT_MSTARBLOSS_MASK) 3567 #define I2C_INTSTAT_MSTSTSTPERR_MASK (0x40U) 3568 #define I2C_INTSTAT_MSTSTSTPERR_SHIFT (6U) 3569 /*! MSTSTSTPERR - Master Start/Stop Error flag. 3570 */ 3571 #define I2C_INTSTAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTSTSTPERR_SHIFT)) & I2C_INTSTAT_MSTSTSTPERR_MASK) 3572 #define I2C_INTSTAT_SLVPENDING_MASK (0x100U) 3573 #define I2C_INTSTAT_SLVPENDING_SHIFT (8U) 3574 /*! SLVPENDING - Slave Pending. 3575 */ 3576 #define I2C_INTSTAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVPENDING_SHIFT)) & I2C_INTSTAT_SLVPENDING_MASK) 3577 #define I2C_INTSTAT_SLVNOTSTR_MASK (0x800U) 3578 #define I2C_INTSTAT_SLVNOTSTR_SHIFT (11U) 3579 /*! SLVNOTSTR - Slave Not Stretching status. 3580 */ 3581 #define I2C_INTSTAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVNOTSTR_SHIFT)) & I2C_INTSTAT_SLVNOTSTR_MASK) 3582 #define I2C_INTSTAT_SLVDESEL_MASK (0x8000U) 3583 #define I2C_INTSTAT_SLVDESEL_SHIFT (15U) 3584 /*! SLVDESEL - Slave Deselected flag. 3585 */ 3586 #define I2C_INTSTAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVDESEL_SHIFT)) & I2C_INTSTAT_SLVDESEL_MASK) 3587 #define I2C_INTSTAT_MONRDY_MASK (0x10000U) 3588 #define I2C_INTSTAT_MONRDY_SHIFT (16U) 3589 /*! MONRDY - Monitor Ready. 3590 */ 3591 #define I2C_INTSTAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONRDY_SHIFT)) & I2C_INTSTAT_MONRDY_MASK) 3592 #define I2C_INTSTAT_MONOV_MASK (0x20000U) 3593 #define I2C_INTSTAT_MONOV_SHIFT (17U) 3594 /*! MONOV - Monitor Overflow flag. 3595 */ 3596 #define I2C_INTSTAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONOV_SHIFT)) & I2C_INTSTAT_MONOV_MASK) 3597 #define I2C_INTSTAT_MONIDLE_MASK (0x80000U) 3598 #define I2C_INTSTAT_MONIDLE_SHIFT (19U) 3599 /*! MONIDLE - Monitor Idle flag. 3600 */ 3601 #define I2C_INTSTAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONIDLE_SHIFT)) & I2C_INTSTAT_MONIDLE_MASK) 3602 #define I2C_INTSTAT_EVENTTIMEOUT_MASK (0x1000000U) 3603 #define I2C_INTSTAT_EVENTTIMEOUT_SHIFT (24U) 3604 /*! EVENTTIMEOUT - Event time-out Interrupt flag. 3605 */ 3606 #define I2C_INTSTAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_EVENTTIMEOUT_SHIFT)) & I2C_INTSTAT_EVENTTIMEOUT_MASK) 3607 #define I2C_INTSTAT_SCLTIMEOUT_MASK (0x2000000U) 3608 #define I2C_INTSTAT_SCLTIMEOUT_SHIFT (25U) 3609 /*! SCLTIMEOUT - SCL time-out Interrupt flag. 3610 */ 3611 #define I2C_INTSTAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SCLTIMEOUT_SHIFT)) & I2C_INTSTAT_SCLTIMEOUT_MASK) 3612 /*! @} */ 3613 3614 /*! @name MSTCTL - Master control register. */ 3615 /*! @{ */ 3616 #define I2C_MSTCTL_MSTCONTINUE_MASK (0x1U) 3617 #define I2C_MSTCTL_MSTCONTINUE_SHIFT (0U) 3618 /*! MSTCONTINUE - Master Continue. This bit is write-only. 3619 * 0b0..No effect. 3620 * 0b1..Continue. Informs the Master function to continue to the next operation. This must done after writing 3621 * transmit data, reading received data, or any other housekeeping related to the next bus operation. 3622 */ 3623 #define I2C_MSTCTL_MSTCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTCONTINUE_SHIFT)) & I2C_MSTCTL_MSTCONTINUE_MASK) 3624 #define I2C_MSTCTL_MSTSTART_MASK (0x2U) 3625 #define I2C_MSTCTL_MSTSTART_SHIFT (1U) 3626 /*! MSTSTART - Master Start control. This bit is write-only. 3627 * 0b0..No effect. 3628 * 0b1..Start. A Start will be generated on the I2C bus at the next allowed time. 3629 */ 3630 #define I2C_MSTCTL_MSTSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTART_SHIFT)) & I2C_MSTCTL_MSTSTART_MASK) 3631 #define I2C_MSTCTL_MSTSTOP_MASK (0x4U) 3632 #define I2C_MSTCTL_MSTSTOP_SHIFT (2U) 3633 /*! MSTSTOP - Master Stop control. This bit is write-only. 3634 * 0b0..No effect. 3635 * 0b1..Stop. A Stop will be generated on the I2C bus at the next allowed time, preceded by a NACK to the slave 3636 * if the master is receiving data from the slave (Master Receiver mode). 3637 */ 3638 #define I2C_MSTCTL_MSTSTOP(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTOP_SHIFT)) & I2C_MSTCTL_MSTSTOP_MASK) 3639 #define I2C_MSTCTL_MSTDMA_MASK (0x8U) 3640 #define I2C_MSTCTL_MSTDMA_SHIFT (3U) 3641 /*! MSTDMA - Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type 3642 * operations such as Start, address, Stop, and address match must always be done with software, 3643 * typically via an interrupt. Address acknowledgement must also be done by software except when 3644 * the I2C is configured to be HSCAPABLE (and address acknowledgement is handled entirely by 3645 * hardware) or when Automatic Operation is enabled. When a DMA data transfer is complete, MSTDMA 3646 * must be cleared prior to beginning the next operation, typically a Start or Stop.This bit is 3647 * read/write. 3648 * 0b0..Disable. No DMA requests are generated for master operation. 3649 * 0b1..Enable. A DMA request is generated for I2C master data operations. When this I2C master is generating 3650 * Acknowledge bits in Master Receiver mode, the acknowledge is generated automatically. 3651 */ 3652 #define I2C_MSTCTL_MSTDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTDMA_SHIFT)) & I2C_MSTCTL_MSTDMA_MASK) 3653 /*! @} */ 3654 3655 /*! @name MSTTIME - Master timing configuration. */ 3656 /*! @{ */ 3657 #define I2C_MSTTIME_MSTSCLLOW_MASK (0x7U) 3658 #define I2C_MSTTIME_MSTSCLLOW_SHIFT (0U) 3659 /*! MSTSCLLOW - Master SCL Low time. Specifies the minimum low time that will be asserted by this 3660 * master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This 3661 * corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters 3662 * tBUF and tSU;STA have the same values and are also controlled by MSTSCLLOW. 3663 * 0b000..2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider. 3664 * 0b001..3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider. 3665 * 0b010..4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider. 3666 * 0b011..5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider. 3667 * 0b100..6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider. 3668 * 0b101..7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider. 3669 * 0b110..8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider. 3670 * 0b111..9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider. 3671 */ 3672 #define I2C_MSTTIME_MSTSCLLOW(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLLOW_SHIFT)) & I2C_MSTTIME_MSTSCLLOW_MASK) 3673 #define I2C_MSTTIME_MSTSCLHIGH_MASK (0x70U) 3674 #define I2C_MSTTIME_MSTSCLHIGH_SHIFT (4U) 3675 /*! MSTSCLHIGH - Master SCL High time. Specifies the minimum high time that will be asserted by this 3676 * master on SCL. Other masters in a multi-master system could shorten this time. This 3677 * corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters 3678 * tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH. 3679 * 0b000..2 clocks. Minimum SCL high time is 2 clock of the I2C clock pre-divider. 3680 * 0b001..3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider . 3681 * 0b010..4 clocks. Minimum SCL high time is 4 clock of the I2C clock pre-divider. 3682 * 0b011..5 clocks. Minimum SCL high time is 5 clock of the I2C clock pre-divider. 3683 * 0b100..6 clocks. Minimum SCL high time is 6 clock of the I2C clock pre-divider. 3684 * 0b101..7 clocks. Minimum SCL high time is 7 clock of the I2C clock pre-divider. 3685 * 0b110..8 clocks. Minimum SCL high time is 8 clock of the I2C clock pre-divider. 3686 * 0b111..9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider. 3687 */ 3688 #define I2C_MSTTIME_MSTSCLHIGH(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLHIGH_SHIFT)) & I2C_MSTTIME_MSTSCLHIGH_MASK) 3689 /*! @} */ 3690 3691 /*! @name MSTDAT - Combined Master receiver and transmitter data register. */ 3692 /*! @{ */ 3693 #define I2C_MSTDAT_DATA_MASK (0xFFU) 3694 #define I2C_MSTDAT_DATA_SHIFT (0U) 3695 /*! DATA - Master function data register. Read: read the most recently received data for the Master 3696 * function. Write: transmit data using the Master function. 3697 */ 3698 #define I2C_MSTDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTDAT_DATA_SHIFT)) & I2C_MSTDAT_DATA_MASK) 3699 /*! @} */ 3700 3701 /*! @name SLVCTL - Slave control register. */ 3702 /*! @{ */ 3703 #define I2C_SLVCTL_SLVCONTINUE_MASK (0x1U) 3704 #define I2C_SLVCTL_SLVCONTINUE_SHIFT (0U) 3705 /*! SLVCONTINUE - Slave Continue. 3706 * 0b0..No effect. 3707 * 0b1..Continue. Informs the Slave function to continue to the next operation, by clearing the SLVPENDING flag 3708 * in the STAT register. This must be done after writing transmit data, reading received data, or any other 3709 * housekeeping related to the next bus operation. Automatic Operation has different requirements. SLVCONTINUE 3710 * should not be set unless SLVPENDING = 1. 3711 */ 3712 #define I2C_SLVCTL_SLVCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVCONTINUE_SHIFT)) & I2C_SLVCTL_SLVCONTINUE_MASK) 3713 #define I2C_SLVCTL_SLVNACK_MASK (0x2U) 3714 #define I2C_SLVCTL_SLVNACK_SHIFT (1U) 3715 /*! SLVNACK - Slave NACK. 3716 * 0b0..No effect. 3717 * 0b1..NACK. Causes the Slave function to NACK the master when the slave is receiving data from the master (Slave Receiver mode). 3718 */ 3719 #define I2C_SLVCTL_SLVNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVNACK_SHIFT)) & I2C_SLVCTL_SLVNACK_MASK) 3720 #define I2C_SLVCTL_SLVDMA_MASK (0x8U) 3721 #define I2C_SLVCTL_SLVDMA_SHIFT (3U) 3722 /*! SLVDMA - Slave DMA enable. 3723 * 0b0..Disabled. No DMA requests are issued for Slave mode operation. 3724 * 0b1..Enabled. DMA requests are issued for I2C slave data transmission and reception. 3725 */ 3726 #define I2C_SLVCTL_SLVDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVDMA_SHIFT)) & I2C_SLVCTL_SLVDMA_MASK) 3727 #define I2C_SLVCTL_AUTOACK_MASK (0x100U) 3728 #define I2C_SLVCTL_AUTOACK_SHIFT (8U) 3729 /*! AUTOACK - Automatic Acknowledge.When this bit is set, it will cause an I2C header which matches 3730 * SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA 3731 * to allow processing of the data without intervention. If this bit is clear and a header 3732 * matches SLVADR0, the behavior is controlled by AUTONACK in the SLVADR0 register: allowing NACK or 3733 * interrupt. 3734 * 0b0..Normal, non-automatic operation. If AUTONACK = 0, an SlvPending interrupt is generated when a matching 3735 * address is received. If AUTONACK = 1, received addresses are NACKed (ignored). 3736 * 0b1..A header with matching SLVADR0 and matching direction as set by AUTOMATCHREAD will be ACKed immediately, 3737 * allowing the master to move on to the data bytes. If the address matches SLVADR0, but the direction does 3738 * not match AUTOMATCHREAD, the behavior will depend on the AUTONACK bit in the SLVADR0 register: if AUTONACK 3739 * is set, then it will be Nacked; else if AUTONACK is clear, then a SlvPending interrupt is generated. 3740 */ 3741 #define I2C_SLVCTL_AUTOACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOACK_SHIFT)) & I2C_SLVCTL_AUTOACK_MASK) 3742 #define I2C_SLVCTL_AUTOMATCHREAD_MASK (0x200U) 3743 #define I2C_SLVCTL_AUTOMATCHREAD_SHIFT (9U) 3744 /*! AUTOMATCHREAD - When AUTOACK is set, this bit controls whether it matches a read or write 3745 * request on the next header with an address matching SLVADR0. Since DMA needs to be configured to 3746 * match the transfer direction, the direction needs to be specified. This bit allows a direction to 3747 * be chosen for the next operation. 3748 * 0b0..The expected next operation in Automatic Mode is an I2C write. 3749 * 0b1..The expected next operation in Automatic Mode is an I2C read. 3750 */ 3751 #define I2C_SLVCTL_AUTOMATCHREAD(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOMATCHREAD_SHIFT)) & I2C_SLVCTL_AUTOMATCHREAD_MASK) 3752 /*! @} */ 3753 3754 /*! @name SLVDAT - Combined Slave receiver and transmitter data register. */ 3755 /*! @{ */ 3756 #define I2C_SLVDAT_DATA_MASK (0xFFU) 3757 #define I2C_SLVDAT_DATA_SHIFT (0U) 3758 /*! DATA - Slave function data register. Read: read the most recently received data for the Slave 3759 * function. Write: transmit data using the Slave function. 3760 */ 3761 #define I2C_SLVDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVDAT_DATA_SHIFT)) & I2C_SLVDAT_DATA_MASK) 3762 /*! @} */ 3763 3764 /*! @name SLVADR - Slave address register. */ 3765 /*! @{ */ 3766 #define I2C_SLVADR_SADISABLE_MASK (0x1U) 3767 #define I2C_SLVADR_SADISABLE_SHIFT (0U) 3768 /*! SADISABLE - Slave Address n Disable. 3769 * 0b0..Enabled. Slave Address n is enabled. 3770 * 0b1..Ignored Slave Address n is ignored. 3771 */ 3772 #define I2C_SLVADR_SADISABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SADISABLE_SHIFT)) & I2C_SLVADR_SADISABLE_MASK) 3773 #define I2C_SLVADR_SLVADR_MASK (0xFEU) 3774 #define I2C_SLVADR_SLVADR_SHIFT (1U) 3775 /*! SLVADR - Slave Address. Seven bit slave address that is compared to received addresses if enabled. 3776 */ 3777 #define I2C_SLVADR_SLVADR(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SLVADR_SHIFT)) & I2C_SLVADR_SLVADR_MASK) 3778 #define I2C_SLVADR_AUTONACK_MASK (0x8000U) 3779 #define I2C_SLVADR_AUTONACK_SHIFT (15U) 3780 /*! AUTONACK - Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD, allows 3781 * software to ignore I2C traffic while handling previous I2C data or other operations. 3782 * 0b0..Normal operation, matching I2C addresses are not ignored. 3783 * 0b1..Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is set, it matches 3784 * SLVADRn, and AUTOMATCHREAD matches the direction. 3785 */ 3786 #define I2C_SLVADR_AUTONACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_AUTONACK_SHIFT)) & I2C_SLVADR_AUTONACK_MASK) 3787 /*! @} */ 3788 3789 /* The count of I2C_SLVADR */ 3790 #define I2C_SLVADR_COUNT (4U) 3791 3792 /*! @name SLVQUAL0 - Slave Qualification for address 0. */ 3793 /*! @{ */ 3794 #define I2C_SLVQUAL0_QUALMODE0_MASK (0x1U) 3795 #define I2C_SLVQUAL0_QUALMODE0_SHIFT (0U) 3796 /*! QUALMODE0 - Qualify mode for slave address 0. 3797 * 0b0..Mask. The SLVQUAL0 field is used as a logical mask for matching address 0. 3798 * 0b1..Extend. The SLVQUAL0 field is used to extend address 0 matching in a range of addresses. 3799 */ 3800 #define I2C_SLVQUAL0_QUALMODE0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_QUALMODE0_SHIFT)) & I2C_SLVQUAL0_QUALMODE0_MASK) 3801 #define I2C_SLVQUAL0_SLVQUAL0_MASK (0xFEU) 3802 #define I2C_SLVQUAL0_SLVQUAL0_SHIFT (1U) 3803 /*! SLVQUAL0 - Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to 3804 * be used as-is, assuming that it is enabled. If QUALMODE0 = 0, any bit in this field which is 3805 * set to 1 will cause an automatic match of the corresponding bit of the received address when it 3806 * is compared to the SLVADR0 register. If QUALMODE0 = 1, an address range is matched for 3807 * address 0. This range extends from the value defined by SLVADR0 to the address defined by SLVQUAL0 3808 * (address matches when SLVADR0[7:1] <= received address <= SLVQUAL0[7:1]). 3809 */ 3810 #define I2C_SLVQUAL0_SLVQUAL0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_SLVQUAL0_SHIFT)) & I2C_SLVQUAL0_SLVQUAL0_MASK) 3811 /*! @} */ 3812 3813 /*! @name MONRXDAT - Monitor receiver data register. */ 3814 /*! @{ */ 3815 #define I2C_MONRXDAT_MONRXDAT_MASK (0xFFU) 3816 #define I2C_MONRXDAT_MONRXDAT_SHIFT (0U) 3817 /*! MONRXDAT - Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins. 3818 */ 3819 #define I2C_MONRXDAT_MONRXDAT(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRXDAT_SHIFT)) & I2C_MONRXDAT_MONRXDAT_MASK) 3820 #define I2C_MONRXDAT_MONSTART_MASK (0x100U) 3821 #define I2C_MONRXDAT_MONSTART_SHIFT (8U) 3822 /*! MONSTART - Monitor Received Start. 3823 * 0b0..No start detected. The Monitor function has not detected a Start event on the I2C bus. 3824 * 0b1..Start detected. The Monitor function has detected a Start event on the I2C bus. 3825 */ 3826 #define I2C_MONRXDAT_MONSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONSTART_SHIFT)) & I2C_MONRXDAT_MONSTART_MASK) 3827 #define I2C_MONRXDAT_MONRESTART_MASK (0x200U) 3828 #define I2C_MONRXDAT_MONRESTART_SHIFT (9U) 3829 /*! MONRESTART - Monitor Received Repeated Start. 3830 * 0b0..No repeated start detected. The Monitor function has not detected a Repeated Start event on the I2C bus. 3831 * 0b1..Repeated start detected. The Monitor function has detected a Repeated Start event on the I2C bus. 3832 */ 3833 #define I2C_MONRXDAT_MONRESTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRESTART_SHIFT)) & I2C_MONRXDAT_MONRESTART_MASK) 3834 #define I2C_MONRXDAT_MONNACK_MASK (0x400U) 3835 #define I2C_MONRXDAT_MONNACK_SHIFT (10U) 3836 /*! MONNACK - Monitor Received NACK. 3837 * 0b0..Acknowledged. The data currently being provided by the Monitor function was acknowledged by at least one master or slave receiver. 3838 * 0b1..Not acknowledged. The data currently being provided by the Monitor function was not acknowledged by any receiver. 3839 */ 3840 #define I2C_MONRXDAT_MONNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONNACK_SHIFT)) & I2C_MONRXDAT_MONNACK_MASK) 3841 /*! @} */ 3842 3843 3844 /*! 3845 * @} 3846 */ /* end of group I2C_Register_Masks */ 3847 3848 3849 /* I2C - Peripheral instance base addresses */ 3850 /** Peripheral I2C0 base address */ 3851 #define I2C0_BASE (0x40086000u) 3852 /** Peripheral I2C0 base pointer */ 3853 #define I2C0 ((I2C_Type *)I2C0_BASE) 3854 /** Peripheral I2C1 base address */ 3855 #define I2C1_BASE (0x40087000u) 3856 /** Peripheral I2C1 base pointer */ 3857 #define I2C1 ((I2C_Type *)I2C1_BASE) 3858 /** Peripheral I2C2 base address */ 3859 #define I2C2_BASE (0x40088000u) 3860 /** Peripheral I2C2 base pointer */ 3861 #define I2C2 ((I2C_Type *)I2C2_BASE) 3862 /** Peripheral I2C3 base address */ 3863 #define I2C3_BASE (0x40089000u) 3864 /** Peripheral I2C3 base pointer */ 3865 #define I2C3 ((I2C_Type *)I2C3_BASE) 3866 /** Peripheral I2C4 base address */ 3867 #define I2C4_BASE (0x4008A000u) 3868 /** Peripheral I2C4 base pointer */ 3869 #define I2C4 ((I2C_Type *)I2C4_BASE) 3870 /** Peripheral I2C5 base address */ 3871 #define I2C5_BASE (0x40096000u) 3872 /** Peripheral I2C5 base pointer */ 3873 #define I2C5 ((I2C_Type *)I2C5_BASE) 3874 /** Peripheral I2C6 base address */ 3875 #define I2C6_BASE (0x40097000u) 3876 /** Peripheral I2C6 base pointer */ 3877 #define I2C6 ((I2C_Type *)I2C6_BASE) 3878 /** Peripheral I2C7 base address */ 3879 #define I2C7_BASE (0x40098000u) 3880 /** Peripheral I2C7 base pointer */ 3881 #define I2C7 ((I2C_Type *)I2C7_BASE) 3882 /** Array initializer of I2C peripheral base addresses */ 3883 #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE, I2C5_BASE, I2C6_BASE, I2C7_BASE } 3884 /** Array initializer of I2C peripheral base pointers */ 3885 #define I2C_BASE_PTRS { I2C0, I2C1, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7 } 3886 /** Interrupt vectors for the I2C peripheral type */ 3887 #define I2C_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } 3888 3889 /*! 3890 * @} 3891 */ /* end of group I2C_Peripheral_Access_Layer */ 3892 3893 3894 /* ---------------------------------------------------------------------------- 3895 -- I2S Peripheral Access Layer 3896 ---------------------------------------------------------------------------- */ 3897 3898 /*! 3899 * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer 3900 * @{ 3901 */ 3902 3903 /** I2S - Register Layout Typedef */ 3904 typedef struct { 3905 uint8_t RESERVED_0[3072]; 3906 __IO uint32_t CFG1; /**< Configuration register 1 for the primary channel pair., offset: 0xC00 */ 3907 __IO uint32_t CFG2; /**< Configuration register 2 for the primary channel pair., offset: 0xC04 */ 3908 __IO uint32_t STAT; /**< Status register for the primary channel pair., offset: 0xC08 */ 3909 uint8_t RESERVED_1[16]; 3910 __IO uint32_t DIV; /**< Clock divider, used by all channel pairs., offset: 0xC1C */ 3911 uint8_t RESERVED_2[480]; 3912 __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */ 3913 __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ 3914 __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */ 3915 uint8_t RESERVED_3[4]; 3916 __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */ 3917 __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */ 3918 __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */ 3919 uint8_t RESERVED_4[4]; 3920 __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ 3921 __O uint32_t FIFOWR48H; /**< FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE24 */ 3922 uint8_t RESERVED_5[8]; 3923 __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */ 3924 __I uint32_t FIFORD48H; /**< FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE34 */ 3925 uint8_t RESERVED_6[8]; 3926 __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */ 3927 __I uint32_t FIFORD48HNOPOP; /**< FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE44 */ 3928 } I2S_Type; 3929 3930 /* ---------------------------------------------------------------------------- 3931 -- I2S Register Masks 3932 ---------------------------------------------------------------------------- */ 3933 3934 /*! 3935 * @addtogroup I2S_Register_Masks I2S Register Masks 3936 * @{ 3937 */ 3938 3939 /*! @name CFG1 - Configuration register 1 for the primary channel pair. */ 3940 /*! @{ */ 3941 #define I2S_CFG1_MAINENABLE_MASK (0x1U) 3942 #define I2S_CFG1_MAINENABLE_SHIFT (0U) 3943 /*! MAINENABLE - Main enable for I 2S function in this Flexcomm 3944 * 0b0..All I 2S channel pairs in this Flexcomm are disabled and the internal state machines, counters, and flags 3945 * are reset. No other channel pairs can be enabled. 3946 * 0b1..This I 2S channel pair is enabled. Other channel pairs in this Flexcomm may be enabled in their individual PAIRENABLE bits. 3947 */ 3948 #define I2S_CFG1_MAINENABLE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MAINENABLE_SHIFT)) & I2S_CFG1_MAINENABLE_MASK) 3949 #define I2S_CFG1_DATAPAUSE_MASK (0x2U) 3950 #define I2S_CFG1_DATAPAUSE_SHIFT (1U) 3951 /*! DATAPAUSE - Data flow Pause. Allows pausing data flow between the I2S serializer/deserializer 3952 * and the FIFO. This could be done in order to change streams, or while restarting after a data 3953 * underflow or overflow. When paused, FIFO operations can be done without corrupting data that is 3954 * in the process of being sent or received. Once a data pause has been requested, the interface 3955 * may need to complete sending data that was in progress before interrupting the flow of data. 3956 * Software must check that the pause is actually in effect before taking action. This is done by 3957 * monitoring the DATAPAUSED flag in the STAT register. When DATAPAUSE is cleared, data transfer 3958 * will resume at the beginning of the next frame. 3959 * 0b0..Normal operation, or resuming normal operation at the next frame if the I2S has already been paused. 3960 * 0b1..A pause in the data flow is being requested. It is in effect when DATAPAUSED in STAT = 1. 3961 */ 3962 #define I2S_CFG1_DATAPAUSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATAPAUSE_SHIFT)) & I2S_CFG1_DATAPAUSE_MASK) 3963 #define I2S_CFG1_PAIRCOUNT_MASK (0xCU) 3964 #define I2S_CFG1_PAIRCOUNT_SHIFT (2U) 3965 /*! PAIRCOUNT - Provides the number of I2S channel pairs in this Flexcomm This is a read-only field 3966 * whose value may be different in other Flexcomms. 00 = there is 1 I2S channel pair in this 3967 * Flexcomm. 01 = there are 2 I2S channel pairs in this Flexcomm. 10 = there are 3 I2S channel pairs 3968 * in this Flexcomm. 11 = there are 4 I2S channel pairs in this Flexcomm. 3969 * 0b00..1 I2S channel pairs in this flexcomm 3970 * 0b01..2 I2S channel pairs in this flexcomm 3971 * 0b10..3 I2S channel pairs in this flexcomm 3972 * 0b11..4 I2S channel pairs in this flexcomm 3973 */ 3974 #define I2S_CFG1_PAIRCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_PAIRCOUNT_SHIFT)) & I2S_CFG1_PAIRCOUNT_MASK) 3975 #define I2S_CFG1_MSTSLVCFG_MASK (0x30U) 3976 #define I2S_CFG1_MSTSLVCFG_SHIFT (4U) 3977 /*! MSTSLVCFG - Master / slave configuration selection, determining how SCK and WS are used by all channel pairs in this Flexcomm. 3978 * 0b00..Normal slave mode, the default mode. SCK and WS are received from a master and used to transmit or receive data. 3979 * 0b01..WS synchronized master. WS is received from another master and used to synchronize the generation of 3980 * SCK, when divided from the Flexcomm function clock. 3981 * 0b10..Master using an existing SCK. SCK is received and used directly to generate WS, as well as transmitting or receiving data. 3982 * 0b11..Normal master mode. SCK and WS are generated so they can be sent to one or more slave devices. 3983 */ 3984 #define I2S_CFG1_MSTSLVCFG(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MSTSLVCFG_SHIFT)) & I2S_CFG1_MSTSLVCFG_MASK) 3985 #define I2S_CFG1_MODE_MASK (0xC0U) 3986 #define I2S_CFG1_MODE_SHIFT (6U) 3987 /*! MODE - Selects the basic I2S operating mode. Other configurations modify this to obtain all 3988 * supported cases. See Formats and modes for examples. 3989 * 0b00..I2S mode a.k.a. 'classic' mode. WS has a 50% duty cycle, with (for each enabled channel pair) one piece 3990 * of left channel data occurring during the first phase, and one pieces of right channel data occurring 3991 * during the second phase. In this mode, the data region begins one clock after the leading WS edge for the 3992 * frame. For a 50% WS duty cycle, FRAMELEN must define an even number of I2S clocks for the frame. If 3993 * FRAMELEN defines an odd number of clocks per frame, the extra clock will occur on the right. 3994 * 0b01..DSP mode where WS has a 50% duty cycle. See remark for mode 0. 3995 * 0b10..DSP mode where WS has a one clock long pulse at the beginning of each data frame. 3996 * 0b11..DSP mode where WS has a one data slot long pulse at the beginning of each data frame. 3997 */ 3998 #define I2S_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MODE_SHIFT)) & I2S_CFG1_MODE_MASK) 3999 #define I2S_CFG1_RIGHTLOW_MASK (0x100U) 4000 #define I2S_CFG1_RIGHTLOW_SHIFT (8U) 4001 /*! RIGHTLOW - Right channel data is in the Low portion of FIFO data. Essentially, this swaps left 4002 * and right channel data as it is transferred to or from the FIFO. This bit is not used if the 4003 * data width is greater than 24 bits or if PDMDATA = 1. Note that if the ONECHANNEL field (bit 10 4004 * of this register) = 1, the one channel to be used is the nominally the left channel. POSITION 4005 * can still place that data in the frame where right channel data is normally located. if all 4006 * enabled channel pairs have ONECHANNEL = 1, then RIGHTLOW = 1 is not allowed. 4007 * 0b0..The right channel is taken from the high part of the FIFO data. For example, when data is 16 bits, FIFO 4008 * bits 31:16 are used for the right channel. 4009 * 0b1..The right channel is taken from the low part of the FIFO data. For example, when data is 16 bits, FIFO 4010 * bits 15:0 are used for the right channel. 4011 */ 4012 #define I2S_CFG1_RIGHTLOW(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_RIGHTLOW_SHIFT)) & I2S_CFG1_RIGHTLOW_MASK) 4013 #define I2S_CFG1_LEFTJUST_MASK (0x200U) 4014 #define I2S_CFG1_LEFTJUST_SHIFT (9U) 4015 /*! LEFTJUST - Left Justify data. 4016 * 0b0..Data is transferred between the FIFO and the I2S serializer/deserializer right justified, i.e. starting 4017 * from bit 0 and continuing to the position defined by DATALEN. This would correspond to right justified data 4018 * in the stream on the data bus. 4019 * 0b1..Data is transferred between the FIFO and the I2S serializer/deserializer left justified, i.e. starting 4020 * from the MSB of the FIFO entry and continuing for the number of bits defined by DATALEN. This would 4021 * correspond to left justified data in the stream on the data bus. 4022 */ 4023 #define I2S_CFG1_LEFTJUST(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_LEFTJUST_SHIFT)) & I2S_CFG1_LEFTJUST_MASK) 4024 #define I2S_CFG1_ONECHANNEL_MASK (0x400U) 4025 #define I2S_CFG1_ONECHANNEL_SHIFT (10U) 4026 /*! ONECHANNEL - Single channel mode. Applies to both transmit and receive. This configuration bit 4027 * applies only to the first I2S channel pair. Other channel pairs may select this mode 4028 * independently in their separate CFG1 registers. 4029 * 0b0..I2S data for this channel pair is treated as left and right channels. 4030 * 0b1..I2S data for this channel pair is treated as a single channel, functionally the left channel for this 4031 * pair. In mode 0 only, the right side of the frame begins at POSITION = 0x100. This is because mode 0 makes a 4032 * clear distinction between the left and right sides of the frame. When ONECHANNEL = 1, the single channel 4033 * of data may be placed on the right by setting POSITION to 0x100 + the data position within the right side 4034 * (e.g. 0x108 would place data starting at the 8th clock after the middle of the frame). In other modes, data 4035 * for the single channel of data is placed at the clock defined by POSITION. 4036 */ 4037 #define I2S_CFG1_ONECHANNEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_ONECHANNEL_SHIFT)) & I2S_CFG1_ONECHANNEL_MASK) 4038 #define I2S_CFG1_PDMDATA_MASK (0x800U) 4039 #define I2S_CFG1_PDMDATA_SHIFT (11U) 4040 /*! PDMDATA - PDM Data selection. This bit controls the data source for I2S transmit, and cannot be 4041 * set in Rx mode. This bit only has an effect if the device the Flexcomm resides in includes a 4042 * D-Mic subsystem. For the LPC5411x, this bit applies only to Flexcomm 7. 4043 * 0b0..Normal operation, data is transferred to or from the Flexcomm FIFO. 4044 * 0b1..The data source is the D-Mic subsystem. When PDMDATA = 1, only the primary channel pair can be used in 4045 * this Flexcomm. If ONECHANNEL = 1, only the PDM left data is used. the WS rate must match the Fs (sample 4046 * rate) of the D-Mic decimator. A rate mismatch will at some point cause the I2S to overrun or underrun. 4047 */ 4048 #define I2S_CFG1_PDMDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_PDMDATA_SHIFT)) & I2S_CFG1_PDMDATA_MASK) 4049 #define I2S_CFG1_SCK_POL_MASK (0x1000U) 4050 #define I2S_CFG1_SCK_POL_SHIFT (12U) 4051 /*! SCK_POL - SCK polarity. 4052 * 0b0..Data is launched on SCK falling edges and sampled on SCK rising edges (standard for I2S). 4053 * 0b1..Data is launched on SCK rising edges and sampled on SCK falling edges. 4054 */ 4055 #define I2S_CFG1_SCK_POL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_SCK_POL_SHIFT)) & I2S_CFG1_SCK_POL_MASK) 4056 #define I2S_CFG1_WS_POL_MASK (0x2000U) 4057 #define I2S_CFG1_WS_POL_SHIFT (13U) 4058 /*! WS_POL - WS polarity. 4059 * 0b0..Data frames begin at a falling edge of WS (standard for classic I2S). 4060 * 0b1..WS is inverted, resulting in a data frame beginning at a rising edge of WS (standard for most 'non-classic' variations of I2S). 4061 */ 4062 #define I2S_CFG1_WS_POL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_WS_POL_SHIFT)) & I2S_CFG1_WS_POL_MASK) 4063 #define I2S_CFG1_DATALEN_MASK (0x1F0000U) 4064 #define I2S_CFG1_DATALEN_SHIFT (16U) 4065 /*! DATALEN - Data Length, minus 1 encoded, defines the number of data bits to be transmitted or 4066 * received for all I2S channel pairs in this Flexcomm. Note that data is only driven to or received 4067 * from SDA for the number of bits defined by DATALEN. DATALEN is also used in these ways by the 4068 * I2S: Determines the size of data transfers between the FIFO and the I2S 4069 * serializer/deserializer. See FIFO buffer configurations and usage In mode 1, 2, and 3, determines the location of 4070 * right data following left data in the frame. In mode 3 (where WS has a one data slot long pulse 4071 * at the beginning of each data frame) determines the duration of the WS pulse. Values: 0x00 to 4072 * 0x02 = not supported 0x03 = data is 4 bits in length 0x04 = data is 5 bits in length 0x1F = 4073 * data is 32 bits in length 4074 */ 4075 #define I2S_CFG1_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATALEN_SHIFT)) & I2S_CFG1_DATALEN_MASK) 4076 /*! @} */ 4077 4078 /*! @name CFG2 - Configuration register 2 for the primary channel pair. */ 4079 /*! @{ */ 4080 #define I2S_CFG2_FRAMELEN_MASK (0x1FFU) 4081 #define I2S_CFG2_FRAMELEN_SHIFT (0U) 4082 /*! FRAMELEN - Frame Length, minus 1 encoded, defines the number of clocks and data bits in the 4083 * frames that this channel pair participates in. See Frame format. 0x000 to 0x002 = not supported 4084 * 0x003 = frame is 4 bits in total length 0x004 = frame is 5 bits in total length 0x1FF = frame is 4085 * 512 bits in total length if FRAMELEN is an defines an odd length frame (e.g. 33 clocks) in 4086 * mode 0 or 1, the extra clock appears in the right half. When MODE = 3, FRAMELEN must be larger 4087 * than DATALEN in order for the WS pulse to be generated correctly. 4088 */ 4089 #define I2S_CFG2_FRAMELEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_FRAMELEN_SHIFT)) & I2S_CFG2_FRAMELEN_MASK) 4090 #define I2S_CFG2_POSITION_MASK (0x1FF0000U) 4091 #define I2S_CFG2_POSITION_SHIFT (16U) 4092 /*! POSITION - Data Position. Defines the location within the frame of the data for this channel 4093 * pair. POSITION + DATALEN must be less than FRAMELEN. See Frame format. When MODE = 0, POSITION 4094 * defines the location of data in both the left phase and right phase, starting one clock after 4095 * the WS edge. In other modes, POSITION defines the location of data within the entire frame. 4096 * ONECHANNEL = 1 while MODE = 0 is a special case, see the description of ONECHANNEL. The 4097 * combination of DATALEN and the POSITION fields of all channel pairs must be made such that the channels 4098 * do not overlap within the frame. 0x000 = data begins at bit position 0 (the first bit 4099 * position) within the frame or WS phase. 0x001 = data begins at bit position 1 within the frame or WS 4100 * phase. 0x002 = data begins at bit position 2 within the frame or WS phase. 4101 */ 4102 #define I2S_CFG2_POSITION(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_POSITION_SHIFT)) & I2S_CFG2_POSITION_MASK) 4103 /*! @} */ 4104 4105 /*! @name STAT - Status register for the primary channel pair. */ 4106 /*! @{ */ 4107 #define I2S_STAT_BUSY_MASK (0x1U) 4108 #define I2S_STAT_BUSY_SHIFT (0U) 4109 /*! BUSY - Busy status for the primary channel pair. Other BUSY flags may be found in the STAT register for each channel pair. 4110 * 0b0..The transmitter/receiver for channel pair is currently idle. 4111 * 0b1..The transmitter/receiver for channel pair is currently processing data. 4112 */ 4113 #define I2S_STAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_BUSY_SHIFT)) & I2S_STAT_BUSY_MASK) 4114 #define I2S_STAT_SLVFRMERR_MASK (0x2U) 4115 #define I2S_STAT_SLVFRMERR_SHIFT (1U) 4116 /*! SLVFRMERR - Slave Frame Error flag. This applies when at least one channel pair is operating as 4117 * a slave. An error indicates that the incoming WS signal did not transition as expected due to 4118 * a mismatch between FRAMELEN and the actual incoming I2S stream. 4119 * 0b0..No error has been recorded. 4120 * 0b1..An error has been recorded for some channel pair that is operating in slave mode. ERROR is cleared by writing a 1 to this bit position. 4121 */ 4122 #define I2S_STAT_SLVFRMERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_SLVFRMERR_SHIFT)) & I2S_STAT_SLVFRMERR_MASK) 4123 #define I2S_STAT_LR_MASK (0x4U) 4124 #define I2S_STAT_LR_SHIFT (2U) 4125 /*! LR - Left/Right indication. This flag is considered to be a debugging aid and is not expected to 4126 * be used by an I2S driver. Valid when one channel pair is busy. Indicates left or right data 4127 * being processed for the currently busy channel pair. 4128 * 0b0..Left channel. 4129 * 0b1..Right channel. 4130 */ 4131 #define I2S_STAT_LR(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_LR_SHIFT)) & I2S_STAT_LR_MASK) 4132 #define I2S_STAT_DATAPAUSED_MASK (0x8U) 4133 #define I2S_STAT_DATAPAUSED_SHIFT (3U) 4134 /*! DATAPAUSED - Data Paused status flag. Applies to all I2S channels 4135 * 0b0..Data is not currently paused. A data pause may have been requested but is not yet in force, waiting for 4136 * an allowed pause point. Refer to the description of the DATAPAUSE control bit in the CFG1 register. 4137 * 0b1..A data pause has been requested and is now in force. 4138 */ 4139 #define I2S_STAT_DATAPAUSED(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_DATAPAUSED_SHIFT)) & I2S_STAT_DATAPAUSED_MASK) 4140 /*! @} */ 4141 4142 /*! @name DIV - Clock divider, used by all channel pairs. */ 4143 /*! @{ */ 4144 #define I2S_DIV_DIV_MASK (0xFFFU) 4145 #define I2S_DIV_DIV_SHIFT (0U) 4146 /*! DIV - This field controls how this I2S block uses the Flexcomm function clock. 0x000 = The 4147 * Flexcomm function clock is used directly. 0x001 = The Flexcomm function clock is divided by 2. 4148 * 0x002 = The Flexcomm function clock is divided by 3. 0xFFF = The Flexcomm function clock is 4149 * divided by 4,096. 4150 */ 4151 #define I2S_DIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_DIV_DIV_SHIFT)) & I2S_DIV_DIV_MASK) 4152 /*! @} */ 4153 4154 /*! @name FIFOCFG - FIFO configuration and enable register. */ 4155 /*! @{ */ 4156 #define I2S_FIFOCFG_ENABLETX_MASK (0x1U) 4157 #define I2S_FIFOCFG_ENABLETX_SHIFT (0U) 4158 /*! ENABLETX - Enable the transmit FIFO. 4159 * 0b0..The transmit FIFO is not enabled. 4160 * 0b1..The transmit FIFO is enabled. 4161 */ 4162 #define I2S_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLETX_SHIFT)) & I2S_FIFOCFG_ENABLETX_MASK) 4163 #define I2S_FIFOCFG_ENABLERX_MASK (0x2U) 4164 #define I2S_FIFOCFG_ENABLERX_SHIFT (1U) 4165 /*! ENABLERX - Enable the receive FIFO. 4166 * 0b0..The receive FIFO is not enabled. 4167 * 0b1..The receive FIFO is enabled. 4168 */ 4169 #define I2S_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLERX_SHIFT)) & I2S_FIFOCFG_ENABLERX_MASK) 4170 #define I2S_FIFOCFG_TXI2SSE0_MASK (0x4U) 4171 #define I2S_FIFOCFG_TXI2SSE0_SHIFT (2U) 4172 /*! TXI2SSE0 - Transmit I2S empty 0. Determines the value sent by the I2S in transmit mode if the TX 4173 * FIFO becomes empty. This value is sent repeatedly until the I2S is paused, the error is 4174 * cleared, new data is provided, and the I2S is un-paused. 4175 * 0b0..If the TX FIFO becomes empty, the last value is sent. This setting may be used when the data length is 24 4176 * bits or less, or when MONO = 1 for this channel pair. 4177 * 0b1..If the TX FIFO becomes empty, 0 is sent. Use if the data length is greater than 24 bits or if zero fill is preferred. 4178 */ 4179 #define I2S_FIFOCFG_TXI2SSE0(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_TXI2SSE0_SHIFT)) & I2S_FIFOCFG_TXI2SSE0_MASK) 4180 #define I2S_FIFOCFG_PACK48_MASK (0x8U) 4181 #define I2S_FIFOCFG_PACK48_SHIFT (3U) 4182 /*! PACK48 - Packing format for 48-bit data. This relates to how data is entered into or taken from the FIFO by software or DMA. 4183 * 0b0..48-bit I2S FIFO entries are handled as all 24-bit values. 4184 * 0b1..48-bit I2S FIFO entries are handled as alternating 32-bit and 16-bit values. 4185 */ 4186 #define I2S_FIFOCFG_PACK48(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_PACK48_SHIFT)) & I2S_FIFOCFG_PACK48_MASK) 4187 #define I2S_FIFOCFG_SIZE_MASK (0x30U) 4188 #define I2S_FIFOCFG_SIZE_SHIFT (4U) 4189 /*! SIZE - FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 4190 * entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART. 4191 */ 4192 #define I2S_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_SIZE_SHIFT)) & I2S_FIFOCFG_SIZE_MASK) 4193 #define I2S_FIFOCFG_DMATX_MASK (0x1000U) 4194 #define I2S_FIFOCFG_DMATX_SHIFT (12U) 4195 /*! DMATX - DMA configuration for transmit. 4196 * 0b0..DMA is not used for the transmit function. 4197 * 0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. 4198 */ 4199 #define I2S_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMATX_SHIFT)) & I2S_FIFOCFG_DMATX_MASK) 4200 #define I2S_FIFOCFG_DMARX_MASK (0x2000U) 4201 #define I2S_FIFOCFG_DMARX_SHIFT (13U) 4202 /*! DMARX - DMA configuration for receive. 4203 * 0b0..DMA is not used for the receive function. 4204 * 0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. 4205 */ 4206 #define I2S_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMARX_SHIFT)) & I2S_FIFOCFG_DMARX_MASK) 4207 #define I2S_FIFOCFG_WAKETX_MASK (0x4000U) 4208 #define I2S_FIFOCFG_WAKETX_SHIFT (14U) 4209 /*! WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power 4210 * modes (up to power-down, as long as the peripheral function works in that power mode) without 4211 * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The 4212 * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware 4213 * Wake-up control register. 4214 * 0b0..Only enabled interrupts will wake up the device form reduced power modes. 4215 * 0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in 4216 * FIFOTRIG, even when the TXLVL interrupt is not enabled. 4217 */ 4218 #define I2S_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKETX_SHIFT)) & I2S_FIFOCFG_WAKETX_MASK) 4219 #define I2S_FIFOCFG_WAKERX_MASK (0x8000U) 4220 #define I2S_FIFOCFG_WAKERX_SHIFT (15U) 4221 /*! WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power 4222 * modes (up to power-down, as long as the peripheral function works in that power mode) without 4223 * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The 4224 * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware 4225 * Wake-up control register. 4226 * 0b0..Only enabled interrupts will wake up the device form reduced power modes. 4227 * 0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in 4228 * FIFOTRIG, even when the RXLVL interrupt is not enabled. 4229 */ 4230 #define I2S_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKERX_SHIFT)) & I2S_FIFOCFG_WAKERX_MASK) 4231 #define I2S_FIFOCFG_EMPTYTX_MASK (0x10000U) 4232 #define I2S_FIFOCFG_EMPTYTX_SHIFT (16U) 4233 /*! EMPTYTX - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied. 4234 */ 4235 #define I2S_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYTX_SHIFT)) & I2S_FIFOCFG_EMPTYTX_MASK) 4236 #define I2S_FIFOCFG_EMPTYRX_MASK (0x20000U) 4237 #define I2S_FIFOCFG_EMPTYRX_SHIFT (17U) 4238 /*! EMPTYRX - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied. 4239 */ 4240 #define I2S_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYRX_SHIFT)) & I2S_FIFOCFG_EMPTYRX_MASK) 4241 #define I2S_FIFOCFG_POPDBG_MASK (0x40000U) 4242 #define I2S_FIFOCFG_POPDBG_SHIFT (18U) 4243 /*! POPDBG - Pop FIFO for debug reads. 4244 * 0b0..Debug reads of the FIFO do not pop the FIFO. 4245 * 0b1..A debug read will cause the FIFO to pop. 4246 */ 4247 #define I2S_FIFOCFG_POPDBG(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_POPDBG_SHIFT)) & I2S_FIFOCFG_POPDBG_MASK) 4248 /*! @} */ 4249 4250 /*! @name FIFOSTAT - FIFO status register. */ 4251 /*! @{ */ 4252 #define I2S_FIFOSTAT_TXERR_MASK (0x1U) 4253 #define I2S_FIFOSTAT_TXERR_SHIFT (0U) 4254 /*! TXERR - TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow 4255 * caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is 4256 * needed. Cleared by writing a 1 to this bit. 4257 */ 4258 #define I2S_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXERR_SHIFT)) & I2S_FIFOSTAT_TXERR_MASK) 4259 #define I2S_FIFOSTAT_RXERR_MASK (0x2U) 4260 #define I2S_FIFOSTAT_RXERR_SHIFT (1U) 4261 /*! RXERR - RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA 4262 * not emptying the FIFO fast enough. Cleared by writing a 1 to this bit. 4263 */ 4264 #define I2S_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXERR_SHIFT)) & I2S_FIFOSTAT_RXERR_MASK) 4265 #define I2S_FIFOSTAT_PERINT_MASK (0x8U) 4266 #define I2S_FIFOSTAT_PERINT_SHIFT (3U) 4267 /*! PERINT - Peripheral interrupt. When 1, this indicates that the peripheral function has asserted 4268 * an interrupt. The details can be found by reading the peripheral's STAT register. 4269 */ 4270 #define I2S_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_PERINT_SHIFT)) & I2S_FIFOSTAT_PERINT_MASK) 4271 #define I2S_FIFOSTAT_TXEMPTY_MASK (0x10U) 4272 #define I2S_FIFOSTAT_TXEMPTY_SHIFT (4U) 4273 /*! TXEMPTY - Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data. 4274 */ 4275 #define I2S_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXEMPTY_SHIFT)) & I2S_FIFOSTAT_TXEMPTY_MASK) 4276 #define I2S_FIFOSTAT_TXNOTFULL_MASK (0x20U) 4277 #define I2S_FIFOSTAT_TXNOTFULL_SHIFT (5U) 4278 /*! TXNOTFULL - Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be 4279 * written. When 0, the transmit FIFO is full and another write would cause it to overflow. 4280 */ 4281 #define I2S_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXNOTFULL_SHIFT)) & I2S_FIFOSTAT_TXNOTFULL_MASK) 4282 #define I2S_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) 4283 #define I2S_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) 4284 /*! RXNOTEMPTY - Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty. 4285 */ 4286 #define I2S_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXNOTEMPTY_SHIFT)) & I2S_FIFOSTAT_RXNOTEMPTY_MASK) 4287 #define I2S_FIFOSTAT_RXFULL_MASK (0x80U) 4288 #define I2S_FIFOSTAT_RXFULL_SHIFT (7U) 4289 /*! RXFULL - Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to 4290 * prevent the peripheral from causing an overflow. 4291 */ 4292 #define I2S_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXFULL_SHIFT)) & I2S_FIFOSTAT_RXFULL_MASK) 4293 #define I2S_FIFOSTAT_TXLVL_MASK (0x1F00U) 4294 #define I2S_FIFOSTAT_TXLVL_SHIFT (8U) 4295 /*! TXLVL - Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY 4296 * and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at 4297 * the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be 4298 * 0. 4299 */ 4300 #define I2S_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXLVL_SHIFT)) & I2S_FIFOSTAT_TXLVL_MASK) 4301 #define I2S_FIFOSTAT_RXLVL_MASK (0x1F0000U) 4302 #define I2S_FIFOSTAT_RXLVL_SHIFT (16U) 4303 /*! RXLVL - Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and 4304 * RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the 4305 * point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be 4306 * 1. 4307 */ 4308 #define I2S_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXLVL_SHIFT)) & I2S_FIFOSTAT_RXLVL_MASK) 4309 /*! @} */ 4310 4311 /*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ 4312 /*! @{ */ 4313 #define I2S_FIFOTRIG_TXLVLENA_MASK (0x1U) 4314 #define I2S_FIFOTRIG_TXLVLENA_SHIFT (0U) 4315 /*! TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled 4316 * in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set. 4317 * 0b0..Transmit FIFO level does not generate a FIFO level trigger. 4318 * 0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. 4319 */ 4320 #define I2S_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVLENA_SHIFT)) & I2S_FIFOTRIG_TXLVLENA_MASK) 4321 #define I2S_FIFOTRIG_RXLVLENA_MASK (0x2U) 4322 #define I2S_FIFOTRIG_RXLVLENA_SHIFT (1U) 4323 /*! RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled 4324 * in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. 4325 * 0b0..Receive FIFO level does not generate a FIFO level trigger. 4326 * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. 4327 */ 4328 #define I2S_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVLENA_SHIFT)) & I2S_FIFOTRIG_RXLVLENA_MASK) 4329 #define I2S_FIFOTRIG_TXLVL_MASK (0xF00U) 4330 #define I2S_FIFOTRIG_TXLVL_SHIFT (8U) 4331 /*! TXLVL - Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled 4332 * to do so, the FIFO level can wake up the device just enough to perform DMA, then return to 4333 * the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO 4334 * becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX 4335 * FIFO level decreases to 15 entries (is no longer full). 4336 */ 4337 #define I2S_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVL_SHIFT)) & I2S_FIFOTRIG_TXLVL_MASK) 4338 #define I2S_FIFOTRIG_RXLVL_MASK (0xF0000U) 4339 #define I2S_FIFOTRIG_RXLVL_SHIFT (16U) 4340 /*! RXLVL - Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data 4341 * is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level 4342 * can wake up the device just enough to perform DMA, then return to the reduced power mode. See 4343 * Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no 4344 * longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX 4345 * FIFO has received 16 entries (has become full). 4346 */ 4347 #define I2S_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVL_SHIFT)) & I2S_FIFOTRIG_RXLVL_MASK) 4348 /*! @} */ 4349 4350 /*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ 4351 /*! @{ */ 4352 #define I2S_FIFOINTENSET_TXERR_MASK (0x1U) 4353 #define I2S_FIFOINTENSET_TXERR_SHIFT (0U) 4354 /*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. 4355 * 0b0..No interrupt will be generated for a transmit error. 4356 * 0b1..An interrupt will be generated when a transmit error occurs. 4357 */ 4358 #define I2S_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXERR_SHIFT)) & I2S_FIFOINTENSET_TXERR_MASK) 4359 #define I2S_FIFOINTENSET_RXERR_MASK (0x2U) 4360 #define I2S_FIFOINTENSET_RXERR_SHIFT (1U) 4361 /*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. 4362 * 0b0..No interrupt will be generated for a receive error. 4363 * 0b1..An interrupt will be generated when a receive error occurs. 4364 */ 4365 #define I2S_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXERR_SHIFT)) & I2S_FIFOINTENSET_RXERR_MASK) 4366 #define I2S_FIFOINTENSET_TXLVL_MASK (0x4U) 4367 #define I2S_FIFOINTENSET_TXLVL_SHIFT (2U) 4368 /*! TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level 4369 * specified by the TXLVL field in the FIFOTRIG register. 4370 * 0b0..No interrupt will be generated based on the TX FIFO level. 4371 * 0b1..If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases 4372 * to the level specified by TXLVL in the FIFOTRIG register. 4373 */ 4374 #define I2S_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXLVL_SHIFT)) & I2S_FIFOINTENSET_TXLVL_MASK) 4375 #define I2S_FIFOINTENSET_RXLVL_MASK (0x8U) 4376 #define I2S_FIFOINTENSET_RXLVL_SHIFT (3U) 4377 /*! RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level 4378 * specified by the TXLVL field in the FIFOTRIG register. 4379 * 0b0..No interrupt will be generated based on the RX FIFO level. 4380 * 0b1..If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level 4381 * increases to the level specified by RXLVL in the FIFOTRIG register. 4382 */ 4383 #define I2S_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXLVL_SHIFT)) & I2S_FIFOINTENSET_RXLVL_MASK) 4384 /*! @} */ 4385 4386 /*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ 4387 /*! @{ */ 4388 #define I2S_FIFOINTENCLR_TXERR_MASK (0x1U) 4389 #define I2S_FIFOINTENCLR_TXERR_SHIFT (0U) 4390 /*! TXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. 4391 */ 4392 #define I2S_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXERR_SHIFT)) & I2S_FIFOINTENCLR_TXERR_MASK) 4393 #define I2S_FIFOINTENCLR_RXERR_MASK (0x2U) 4394 #define I2S_FIFOINTENCLR_RXERR_SHIFT (1U) 4395 /*! RXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. 4396 */ 4397 #define I2S_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXERR_SHIFT)) & I2S_FIFOINTENCLR_RXERR_MASK) 4398 #define I2S_FIFOINTENCLR_TXLVL_MASK (0x4U) 4399 #define I2S_FIFOINTENCLR_TXLVL_SHIFT (2U) 4400 /*! TXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. 4401 */ 4402 #define I2S_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXLVL_SHIFT)) & I2S_FIFOINTENCLR_TXLVL_MASK) 4403 #define I2S_FIFOINTENCLR_RXLVL_MASK (0x8U) 4404 #define I2S_FIFOINTENCLR_RXLVL_SHIFT (3U) 4405 /*! RXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. 4406 */ 4407 #define I2S_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXLVL_SHIFT)) & I2S_FIFOINTENCLR_RXLVL_MASK) 4408 /*! @} */ 4409 4410 /*! @name FIFOINTSTAT - FIFO interrupt status register. */ 4411 /*! @{ */ 4412 #define I2S_FIFOINTSTAT_TXERR_MASK (0x1U) 4413 #define I2S_FIFOINTSTAT_TXERR_SHIFT (0U) 4414 /*! TXERR - TX FIFO error. 4415 */ 4416 #define I2S_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXERR_SHIFT)) & I2S_FIFOINTSTAT_TXERR_MASK) 4417 #define I2S_FIFOINTSTAT_RXERR_MASK (0x2U) 4418 #define I2S_FIFOINTSTAT_RXERR_SHIFT (1U) 4419 /*! RXERR - RX FIFO error. 4420 */ 4421 #define I2S_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXERR_SHIFT)) & I2S_FIFOINTSTAT_RXERR_MASK) 4422 #define I2S_FIFOINTSTAT_TXLVL_MASK (0x4U) 4423 #define I2S_FIFOINTSTAT_TXLVL_SHIFT (2U) 4424 /*! TXLVL - Transmit FIFO level interrupt. 4425 */ 4426 #define I2S_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXLVL_SHIFT)) & I2S_FIFOINTSTAT_TXLVL_MASK) 4427 #define I2S_FIFOINTSTAT_RXLVL_MASK (0x8U) 4428 #define I2S_FIFOINTSTAT_RXLVL_SHIFT (3U) 4429 /*! RXLVL - Receive FIFO level interrupt. 4430 */ 4431 #define I2S_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXLVL_SHIFT)) & I2S_FIFOINTSTAT_RXLVL_MASK) 4432 #define I2S_FIFOINTSTAT_PERINT_MASK (0x10U) 4433 #define I2S_FIFOINTSTAT_PERINT_SHIFT (4U) 4434 /*! PERINT - Peripheral interrupt. 4435 */ 4436 #define I2S_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_PERINT_SHIFT)) & I2S_FIFOINTSTAT_PERINT_MASK) 4437 /*! @} */ 4438 4439 /*! @name FIFOWR - FIFO write data. */ 4440 /*! @{ */ 4441 #define I2S_FIFOWR_TXDATA_MASK (0xFFFFFFFFU) 4442 #define I2S_FIFOWR_TXDATA_SHIFT (0U) 4443 /*! TXDATA - Transmit data to the FIFO. The number of bits used depends on configuration details. 4444 */ 4445 #define I2S_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR_TXDATA_SHIFT)) & I2S_FIFOWR_TXDATA_MASK) 4446 /*! @} */ 4447 4448 /*! @name FIFOWR48H - FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ 4449 /*! @{ */ 4450 #define I2S_FIFOWR48H_TXDATA_MASK (0xFFFFFFU) 4451 #define I2S_FIFOWR48H_TXDATA_SHIFT (0U) 4452 /*! TXDATA - Transmit data to the FIFO. Whether this register is used and the number of bits used depends on configuration details. 4453 */ 4454 #define I2S_FIFOWR48H_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR48H_TXDATA_SHIFT)) & I2S_FIFOWR48H_TXDATA_MASK) 4455 /*! @} */ 4456 4457 /*! @name FIFORD - FIFO read data. */ 4458 /*! @{ */ 4459 #define I2S_FIFORD_RXDATA_MASK (0xFFFFFFFFU) 4460 #define I2S_FIFORD_RXDATA_SHIFT (0U) 4461 /*! RXDATA - Received data from the FIFO. The number of bits used depends on configuration details. 4462 */ 4463 #define I2S_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD_RXDATA_SHIFT)) & I2S_FIFORD_RXDATA_MASK) 4464 /*! @} */ 4465 4466 /*! @name FIFORD48H - FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ 4467 /*! @{ */ 4468 #define I2S_FIFORD48H_RXDATA_MASK (0xFFFFFFU) 4469 #define I2S_FIFORD48H_RXDATA_SHIFT (0U) 4470 /*! RXDATA - Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details. 4471 */ 4472 #define I2S_FIFORD48H_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48H_RXDATA_SHIFT)) & I2S_FIFORD48H_RXDATA_MASK) 4473 /*! @} */ 4474 4475 /*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ 4476 /*! @{ */ 4477 #define I2S_FIFORDNOPOP_RXDATA_MASK (0xFFFFFFFFU) 4478 #define I2S_FIFORDNOPOP_RXDATA_SHIFT (0U) 4479 /*! RXDATA - Received data from the FIFO. 4480 */ 4481 #define I2S_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORDNOPOP_RXDATA_SHIFT)) & I2S_FIFORDNOPOP_RXDATA_MASK) 4482 /*! @} */ 4483 4484 /*! @name FIFORD48HNOPOP - FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ 4485 /*! @{ */ 4486 #define I2S_FIFORD48HNOPOP_RXDATA_MASK (0xFFFFFFU) 4487 #define I2S_FIFORD48HNOPOP_RXDATA_SHIFT (0U) 4488 /*! RXDATA - Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details. 4489 */ 4490 #define I2S_FIFORD48HNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48HNOPOP_RXDATA_SHIFT)) & I2S_FIFORD48HNOPOP_RXDATA_MASK) 4491 /*! @} */ 4492 4493 4494 /*! 4495 * @} 4496 */ /* end of group I2S_Register_Masks */ 4497 4498 4499 /* I2S - Peripheral instance base addresses */ 4500 /** Peripheral I2S0 base address */ 4501 #define I2S0_BASE (0x40097000u) 4502 /** Peripheral I2S0 base pointer */ 4503 #define I2S0 ((I2S_Type *)I2S0_BASE) 4504 /** Peripheral I2S1 base address */ 4505 #define I2S1_BASE (0x40098000u) 4506 /** Peripheral I2S1 base pointer */ 4507 #define I2S1 ((I2S_Type *)I2S1_BASE) 4508 /** Array initializer of I2S peripheral base addresses */ 4509 #define I2S_BASE_ADDRS { I2S0_BASE, I2S1_BASE } 4510 /** Array initializer of I2S peripheral base pointers */ 4511 #define I2S_BASE_PTRS { I2S0, I2S1 } 4512 /** Interrupt vectors for the I2S peripheral type */ 4513 #define I2S_IRQS { FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } 4514 4515 /*! 4516 * @} 4517 */ /* end of group I2S_Peripheral_Access_Layer */ 4518 4519 4520 /* ---------------------------------------------------------------------------- 4521 -- INPUTMUX Peripheral Access Layer 4522 ---------------------------------------------------------------------------- */ 4523 4524 /*! 4525 * @addtogroup INPUTMUX_Peripheral_Access_Layer INPUTMUX Peripheral Access Layer 4526 * @{ 4527 */ 4528 4529 /** INPUTMUX - Register Layout Typedef */ 4530 typedef struct { 4531 uint8_t RESERVED_0[192]; 4532 __IO uint32_t PINTSEL[8]; /**< Pin interrupt select register, array offset: 0xC0, array step: 0x4 */ 4533 __IO uint32_t DMA_ITRIG_INMUX[22]; /**< Trigger select register for DMA channel, array offset: 0xE0, array step: 0x4 */ 4534 uint8_t RESERVED_1[40]; 4535 __IO uint32_t DMA_OTRIG_INMUX[4]; /**< DMA output trigger selection to become DMA trigger, array offset: 0x160, array step: 0x4 */ 4536 uint8_t RESERVED_2[16]; 4537 __IO uint32_t FREQMEAS_REF; /**< Selection for frequency measurement reference clock, offset: 0x180 */ 4538 __IO uint32_t FREQMEAS_TARGET; /**< Selection for frequency measurement target clock, offset: 0x184 */ 4539 } INPUTMUX_Type; 4540 4541 /* ---------------------------------------------------------------------------- 4542 -- INPUTMUX Register Masks 4543 ---------------------------------------------------------------------------- */ 4544 4545 /*! 4546 * @addtogroup INPUTMUX_Register_Masks INPUTMUX Register Masks 4547 * @{ 4548 */ 4549 4550 /*! @name PINTSEL - Pin interrupt select register */ 4551 /*! @{ */ 4552 #define INPUTMUX_PINTSEL_INTPIN_MASK (0xFFU) 4553 #define INPUTMUX_PINTSEL_INTPIN_SHIFT (0U) 4554 /*! INTPIN - Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO1_31 correspond to numbers 0 to 63). 4555 */ 4556 #define INPUTMUX_PINTSEL_INTPIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PINTSEL_INTPIN_SHIFT)) & INPUTMUX_PINTSEL_INTPIN_MASK) 4557 /*! @} */ 4558 4559 /* The count of INPUTMUX_PINTSEL */ 4560 #define INPUTMUX_PINTSEL_COUNT (8U) 4561 4562 /*! @name DMA_ITRIG_INMUX - Trigger select register for DMA channel */ 4563 /*! @{ */ 4564 #define INPUTMUX_DMA_ITRIG_INMUX_INP_MASK (0x1FU) 4565 #define INPUTMUX_DMA_ITRIG_INMUX_INP_SHIFT (0U) 4566 /*! INP - Trigger input number (decimal value) for DMA channel n (n = 0 to 21). 0 = ADC0 Sequence A 4567 * interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4 = 4568 * Timer CTIMER0 Match 0 5 = Timer CTIMER0 Match 1 6 = Timer CTIMER1 Match 0 7 = Timer CTIMER2 Match 4569 * 0 8 = Timer CTIMER2 Match 1 9 = Timer CTIMER3 Match 0 10 = Timer CTIMER4 Match 0 11 = Timer 4570 * CTIMER4 Match 1 12 = Pin interrupt 0 13 = Pin interrupt 1 14 = Pin interrupt 2 15 = Pin 4571 * interrupt 3 16 = DMA output trigger mux 0 17 = DMA output trigger mux 1 18 = DMA output trigger mux 2 4572 * 19 = DMA output trigger mux 3 4573 */ 4574 #define INPUTMUX_DMA_ITRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA_ITRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA_ITRIG_INMUX_INP_MASK) 4575 /*! @} */ 4576 4577 /* The count of INPUTMUX_DMA_ITRIG_INMUX */ 4578 #define INPUTMUX_DMA_ITRIG_INMUX_COUNT (22U) 4579 4580 /*! @name DMA_OTRIG_INMUX - DMA output trigger selection to become DMA trigger */ 4581 /*! @{ */ 4582 #define INPUTMUX_DMA_OTRIG_INMUX_INP_MASK (0x1FU) 4583 #define INPUTMUX_DMA_OTRIG_INMUX_INP_SHIFT (0U) 4584 /*! INP - DMA trigger output number (decimal value) for DMA channel n (n = 0 to 19). 4585 */ 4586 #define INPUTMUX_DMA_OTRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA_OTRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA_OTRIG_INMUX_INP_MASK) 4587 /*! @} */ 4588 4589 /* The count of INPUTMUX_DMA_OTRIG_INMUX */ 4590 #define INPUTMUX_DMA_OTRIG_INMUX_COUNT (4U) 4591 4592 /*! @name FREQMEAS_REF - Selection for frequency measurement reference clock */ 4593 /*! @{ */ 4594 #define INPUTMUX_FREQMEAS_REF_CLKIN_MASK (0x1FU) 4595 #define INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT (0U) 4596 /*! CLKIN - Clock source number (decimal value) for frequency measure function target clock: 0 = 4597 * CLK_IN 1 = FRO 12 MHz oscillator 2 = Watchdog oscillator 3 = 32 kHz RTC oscillator 4 = Main clock 4598 * (see Section 4.5.23) 5 = PIO0_4 6 = PIO0_20 7 = PIO0_24 8 = PIO1_4 4599 */ 4600 #define INPUTMUX_FREQMEAS_REF_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_REF_CLKIN_MASK) 4601 /*! @} */ 4602 4603 /*! @name FREQMEAS_TARGET - Selection for frequency measurement target clock */ 4604 /*! @{ */ 4605 #define INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK (0x1FU) 4606 #define INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT (0U) 4607 /*! CLKIN - Clock source number (decimal value) for frequency measure function target clock: 0 = 4608 * CLK_IN 1 = FRO 12 MHz oscillator 2 = Watchdog oscillator 3 = 32 kHz RTC oscillator 4 = Main clock 4609 * (see Section 4.5.23) 5 = PIO0_4 6 = PIO0_20 7 = PIO0_24 8 = PIO1_4 4610 */ 4611 #define INPUTMUX_FREQMEAS_TARGET_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK) 4612 /*! @} */ 4613 4614 4615 /*! 4616 * @} 4617 */ /* end of group INPUTMUX_Register_Masks */ 4618 4619 4620 /* INPUTMUX - Peripheral instance base addresses */ 4621 /** Peripheral INPUTMUX base address */ 4622 #define INPUTMUX_BASE (0x40005000u) 4623 /** Peripheral INPUTMUX base pointer */ 4624 #define INPUTMUX ((INPUTMUX_Type *)INPUTMUX_BASE) 4625 /** Array initializer of INPUTMUX peripheral base addresses */ 4626 #define INPUTMUX_BASE_ADDRS { INPUTMUX_BASE } 4627 /** Array initializer of INPUTMUX peripheral base pointers */ 4628 #define INPUTMUX_BASE_PTRS { INPUTMUX } 4629 4630 /*! 4631 * @} 4632 */ /* end of group INPUTMUX_Peripheral_Access_Layer */ 4633 4634 4635 /* ---------------------------------------------------------------------------- 4636 -- IOCON Peripheral Access Layer 4637 ---------------------------------------------------------------------------- */ 4638 4639 /*! 4640 * @addtogroup IOCON_Peripheral_Access_Layer IOCON Peripheral Access Layer 4641 * @{ 4642 */ 4643 4644 /** IOCON - Register Layout Typedef */ 4645 typedef struct { 4646 __IO uint32_t PIO[2][32]; /**< Digital I/O control for port 0 pins PIO0_0..Digital I/O control for port 1 pins PIO1_31, array offset: 0x0, array step: index*0x80, index2*0x4 */ 4647 } IOCON_Type; 4648 4649 /* ---------------------------------------------------------------------------- 4650 -- IOCON Register Masks 4651 ---------------------------------------------------------------------------- */ 4652 4653 /*! 4654 * @addtogroup IOCON_Register_Masks IOCON Register Masks 4655 * @{ 4656 */ 4657 4658 /*! @name PIO - Digital I/O control for port 0 pins PIO0_0..Digital I/O control for port 1 pins PIO1_31 */ 4659 /*! @{ */ 4660 #define IOCON_PIO_FUNC_MASK (0x7U) 4661 #define IOCON_PIO_FUNC_SHIFT (0U) 4662 /*! FUNC - Selects pin function. 4663 * 0b000..Alternative connection 0. 4664 * 0b001..Alternative connection 1. 4665 * 0b010..Alternative connection 2. 4666 * 0b011..Alternative connection 3. 4667 * 0b100..Alternative connection 4. 4668 * 0b101..Alternative connection 5. 4669 * 0b110..Alternative connection 6. 4670 * 0b111..Alternative connection 7. 4671 */ 4672 #define IOCON_PIO_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FUNC_SHIFT)) & IOCON_PIO_FUNC_MASK) 4673 #define IOCON_PIO_MODE_MASK (0x18U) 4674 #define IOCON_PIO_MODE_SHIFT (3U) 4675 /*! MODE - Selects function mode (on-chip pull-up/pull-down resistor control). 4676 * 0b00..Inactive. Inactive (no pull-down/pull-up resistor enabled). 4677 * 0b01..Pull-down. Pull-down resistor enabled. 4678 * 0b10..Pull-up. Pull-up resistor enabled. 4679 * 0b11..Repeater. Repeater mode. 4680 */ 4681 #define IOCON_PIO_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_MODE_SHIFT)) & IOCON_PIO_MODE_MASK) 4682 #define IOCON_PIO_I2CSLEW_MASK (0x20U) 4683 #define IOCON_PIO_I2CSLEW_SHIFT (5U) 4684 /*! I2CSLEW - Controls slew rate of I2C pad. 4685 * 0b0..I2C mode. 4686 * 0b1..GPIO mode. 4687 */ 4688 #define IOCON_PIO_I2CSLEW(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CSLEW_SHIFT)) & IOCON_PIO_I2CSLEW_MASK) 4689 #define IOCON_PIO_INVERT_MASK (0x40U) 4690 #define IOCON_PIO_INVERT_SHIFT (6U) 4691 /*! INVERT - Input polarity. 4692 * 0b0..Disabled. Input function is not inverted. 4693 * 0b1..Enabled. Input is function inverted. 4694 */ 4695 #define IOCON_PIO_INVERT(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_INVERT_SHIFT)) & IOCON_PIO_INVERT_MASK) 4696 #define IOCON_PIO_DIGIMODE_MASK (0x80U) 4697 #define IOCON_PIO_DIGIMODE_SHIFT (7U) 4698 /*! DIGIMODE - Select Analog/Digital mode. 4699 * 0b0..Analog mode. 4700 * 0b1..Digital mode. 4701 */ 4702 #define IOCON_PIO_DIGIMODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_DIGIMODE_SHIFT)) & IOCON_PIO_DIGIMODE_MASK) 4703 #define IOCON_PIO_FILTEROFF_MASK (0x100U) 4704 #define IOCON_PIO_FILTEROFF_SHIFT (8U) 4705 /*! FILTEROFF - Controls input glitch filter. 4706 * 0b0..Filter enabled. Noise pulses below approximately 10 ns are filtered out. 4707 * 0b1..Filter disabled. No input filtering is done. 4708 */ 4709 #define IOCON_PIO_FILTEROFF(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FILTEROFF_SHIFT)) & IOCON_PIO_FILTEROFF_MASK) 4710 #define IOCON_PIO_I2CDRIVE_MASK (0x200U) 4711 #define IOCON_PIO_I2CDRIVE_SHIFT (9U) 4712 /*! I2CDRIVE - Controls the current sink capability of the pin. 4713 * 0b0..Low drive. Output drive sink is 4 mA. This is sufficient for standard and fast mode I2C. 4714 * 0b1..High drive. Output drive sink is 20 mA. This is needed for Fast Mode Plus I 2C. Refer to the appropriate 4715 * specific device data sheet for details. 4716 */ 4717 #define IOCON_PIO_I2CDRIVE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CDRIVE_SHIFT)) & IOCON_PIO_I2CDRIVE_MASK) 4718 #define IOCON_PIO_SLEW_MASK (0x200U) 4719 #define IOCON_PIO_SLEW_SHIFT (9U) 4720 /*! SLEW - Driver slew rate. 4721 * 0b0..Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 4722 * 0b1..Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 4723 */ 4724 #define IOCON_PIO_SLEW(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_SLEW_SHIFT)) & IOCON_PIO_SLEW_MASK) 4725 #define IOCON_PIO_I2CFILTER_MASK (0x400U) 4726 #define IOCON_PIO_I2CFILTER_SHIFT (10U) 4727 /*! I2CFILTER - Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation. 4728 * 0b0..Enabled. I2C 50 ns glitch filter enabled. 4729 * 0b1..Disabled. I2C 50 ns glitch filter disabled. 4730 */ 4731 #define IOCON_PIO_I2CFILTER(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CFILTER_SHIFT)) & IOCON_PIO_I2CFILTER_MASK) 4732 #define IOCON_PIO_OD_MASK (0x400U) 4733 #define IOCON_PIO_OD_SHIFT (10U) 4734 /*! OD - Controls open-drain mode. 4735 * 0b0..Normal. Normal push-pull output 4736 * 0b1..Open-drain. Simulated open-drain output (high drive disabled). 4737 */ 4738 #define IOCON_PIO_OD(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_OD_SHIFT)) & IOCON_PIO_OD_MASK) 4739 /*! @} */ 4740 4741 /* The count of IOCON_PIO */ 4742 #define IOCON_PIO_COUNT (2U) 4743 4744 /* The count of IOCON_PIO */ 4745 #define IOCON_PIO_COUNT2 (32U) 4746 4747 4748 /*! 4749 * @} 4750 */ /* end of group IOCON_Register_Masks */ 4751 4752 4753 /* IOCON - Peripheral instance base addresses */ 4754 /** Peripheral IOCON base address */ 4755 #define IOCON_BASE (0x40001000u) 4756 /** Peripheral IOCON base pointer */ 4757 #define IOCON ((IOCON_Type *)IOCON_BASE) 4758 /** Array initializer of IOCON peripheral base addresses */ 4759 #define IOCON_BASE_ADDRS { IOCON_BASE } 4760 /** Array initializer of IOCON peripheral base pointers */ 4761 #define IOCON_BASE_PTRS { IOCON } 4762 4763 /*! 4764 * @} 4765 */ /* end of group IOCON_Peripheral_Access_Layer */ 4766 4767 4768 /* ---------------------------------------------------------------------------- 4769 -- MAILBOX Peripheral Access Layer 4770 ---------------------------------------------------------------------------- */ 4771 4772 /*! 4773 * @addtogroup MAILBOX_Peripheral_Access_Layer MAILBOX Peripheral Access Layer 4774 * @{ 4775 */ 4776 4777 /** MAILBOX - Register Layout Typedef */ 4778 typedef struct { 4779 struct { /* offset: 0x0, array step: 0x10 */ 4780 __IO uint32_t IRQ; /**< Interrupt request register for the Cortex-M0+ CPU., array offset: 0x0, array step: 0x10 */ 4781 __O uint32_t IRQSET; /**< Set bits in IRQ0, array offset: 0x4, array step: 0x10 */ 4782 __O uint32_t IRQCLR; /**< Clear bits in IRQ0, array offset: 0x8, array step: 0x10 */ 4783 uint8_t RESERVED_0[4]; 4784 } MBOXIRQ[2]; 4785 uint8_t RESERVED_0[216]; 4786 __IO uint32_t MUTEX; /**< Mutual exclusion register[1], offset: 0xF8 */ 4787 } MAILBOX_Type; 4788 4789 /* ---------------------------------------------------------------------------- 4790 -- MAILBOX Register Masks 4791 ---------------------------------------------------------------------------- */ 4792 4793 /*! 4794 * @addtogroup MAILBOX_Register_Masks MAILBOX Register Masks 4795 * @{ 4796 */ 4797 4798 /*! @name MBOXIRQ_IRQ - Interrupt request register for the Cortex-M0+ CPU. */ 4799 /*! @{ */ 4800 #define MAILBOX_MBOXIRQ_IRQ_INTREQ_MASK (0xFFFFFFFFU) 4801 #define MAILBOX_MBOXIRQ_IRQ_INTREQ_SHIFT (0U) 4802 /*! INTREQ - If any bit is set, an interrupt request is sent to the Cortex-M0+ interrupt controller. 4803 */ 4804 #define MAILBOX_MBOXIRQ_IRQ_INTREQ(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MBOXIRQ_IRQ_INTREQ_SHIFT)) & MAILBOX_MBOXIRQ_IRQ_INTREQ_MASK) 4805 /*! @} */ 4806 4807 /* The count of MAILBOX_MBOXIRQ_IRQ */ 4808 #define MAILBOX_MBOXIRQ_IRQ_COUNT (2U) 4809 4810 /*! @name MBOXIRQ_IRQSET - Set bits in IRQ0 */ 4811 /*! @{ */ 4812 #define MAILBOX_MBOXIRQ_IRQSET_INTREQSET_MASK (0xFFFFFFFFU) 4813 #define MAILBOX_MBOXIRQ_IRQSET_INTREQSET_SHIFT (0U) 4814 /*! INTREQSET - Writing 1 sets the corresponding bit in the IRQ0 register. 4815 */ 4816 #define MAILBOX_MBOXIRQ_IRQSET_INTREQSET(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MBOXIRQ_IRQSET_INTREQSET_SHIFT)) & MAILBOX_MBOXIRQ_IRQSET_INTREQSET_MASK) 4817 /*! @} */ 4818 4819 /* The count of MAILBOX_MBOXIRQ_IRQSET */ 4820 #define MAILBOX_MBOXIRQ_IRQSET_COUNT (2U) 4821 4822 /*! @name MBOXIRQ_IRQCLR - Clear bits in IRQ0 */ 4823 /*! @{ */ 4824 #define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_MASK (0xFFFFFFFFU) 4825 #define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_SHIFT (0U) 4826 /*! INTREQCLR - Writing 1 clears the corresponding bit in the IRQ0 register. 4827 */ 4828 #define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_SHIFT)) & MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_MASK) 4829 /*! @} */ 4830 4831 /* The count of MAILBOX_MBOXIRQ_IRQCLR */ 4832 #define MAILBOX_MBOXIRQ_IRQCLR_COUNT (2U) 4833 4834 /*! @name MUTEX - Mutual exclusion register[1] */ 4835 /*! @{ */ 4836 #define MAILBOX_MUTEX_EX_MASK (0x1U) 4837 #define MAILBOX_MUTEX_EX_SHIFT (0U) 4838 /*! EX - Cleared when read, set when written. See usage description above. 4839 */ 4840 #define MAILBOX_MUTEX_EX(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MUTEX_EX_SHIFT)) & MAILBOX_MUTEX_EX_MASK) 4841 /*! @} */ 4842 4843 4844 /*! 4845 * @} 4846 */ /* end of group MAILBOX_Register_Masks */ 4847 4848 4849 /* MAILBOX - Peripheral instance base addresses */ 4850 /** Peripheral MAILBOX base address */ 4851 #define MAILBOX_BASE (0x4008B000u) 4852 /** Peripheral MAILBOX base pointer */ 4853 #define MAILBOX ((MAILBOX_Type *)MAILBOX_BASE) 4854 /** Array initializer of MAILBOX peripheral base addresses */ 4855 #define MAILBOX_BASE_ADDRS { MAILBOX_BASE } 4856 /** Array initializer of MAILBOX peripheral base pointers */ 4857 #define MAILBOX_BASE_PTRS { MAILBOX } 4858 /** Interrupt vectors for the MAILBOX peripheral type */ 4859 #define MAILBOX_IRQS { MAILBOX_IRQn } 4860 4861 /*! 4862 * @} 4863 */ /* end of group MAILBOX_Peripheral_Access_Layer */ 4864 4865 4866 /* ---------------------------------------------------------------------------- 4867 -- MRT Peripheral Access Layer 4868 ---------------------------------------------------------------------------- */ 4869 4870 /*! 4871 * @addtogroup MRT_Peripheral_Access_Layer MRT Peripheral Access Layer 4872 * @{ 4873 */ 4874 4875 /** MRT - Register Layout Typedef */ 4876 typedef struct { 4877 struct { /* offset: 0x0, array step: 0x10 */ 4878 __IO uint32_t INTVAL; /**< MRT Time interval value register. This value is loaded into the TIMER register., array offset: 0x0, array step: 0x10 */ 4879 __I uint32_t TIMER; /**< MRT Timer register. This register reads the value of the down-counter., array offset: 0x4, array step: 0x10 */ 4880 __IO uint32_t CTRL; /**< MRT Control register. This register controls the MRT modes., array offset: 0x8, array step: 0x10 */ 4881 __IO uint32_t STAT; /**< MRT Status register., array offset: 0xC, array step: 0x10 */ 4882 } CHANNEL[4]; 4883 uint8_t RESERVED_0[176]; 4884 __IO uint32_t MODCFG; /**< Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature., offset: 0xF0 */ 4885 __I uint32_t IDLE_CH; /**< Idle channel register. This register returns the number of the first idle channel., offset: 0xF4 */ 4886 __IO uint32_t IRQ_FLAG; /**< Global interrupt flag register, offset: 0xF8 */ 4887 } MRT_Type; 4888 4889 /* ---------------------------------------------------------------------------- 4890 -- MRT Register Masks 4891 ---------------------------------------------------------------------------- */ 4892 4893 /*! 4894 * @addtogroup MRT_Register_Masks MRT Register Masks 4895 * @{ 4896 */ 4897 4898 /*! @name CHANNEL_INTVAL - MRT Time interval value register. This value is loaded into the TIMER register. */ 4899 /*! @{ */ 4900 #define MRT_CHANNEL_INTVAL_IVALUE_MASK (0xFFFFFFU) 4901 #define MRT_CHANNEL_INTVAL_IVALUE_SHIFT (0U) 4902 /*! IVALUE - Time interval load value. This value is loaded into the TIMERn register and the MRT 4903 * channel n starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to 4904 * this bit field starts the timer immediately. If the timer is running, writing a zero to this 4905 * bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer 4906 * stops at the end of the time interval. 4907 */ 4908 #define MRT_CHANNEL_INTVAL_IVALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_IVALUE_SHIFT)) & MRT_CHANNEL_INTVAL_IVALUE_MASK) 4909 #define MRT_CHANNEL_INTVAL_LOAD_MASK (0x80000000U) 4910 #define MRT_CHANNEL_INTVAL_LOAD_SHIFT (31U) 4911 /*! LOAD - Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. 4912 * This bit is write-only. Reading this bit always returns 0. 4913 * 0b0..No force load. The load from the INTVALn register to the TIMERn register is processed at the end of the 4914 * time interval if the repeat mode is selected. 4915 * 0b1..Force load. The INTVALn interval value IVALUE -1 is immediately loaded into the TIMERn register while TIMERn is running. 4916 */ 4917 #define MRT_CHANNEL_INTVAL_LOAD(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_LOAD_SHIFT)) & MRT_CHANNEL_INTVAL_LOAD_MASK) 4918 /*! @} */ 4919 4920 /* The count of MRT_CHANNEL_INTVAL */ 4921 #define MRT_CHANNEL_INTVAL_COUNT (4U) 4922 4923 /*! @name CHANNEL_TIMER - MRT Timer register. This register reads the value of the down-counter. */ 4924 /*! @{ */ 4925 #define MRT_CHANNEL_TIMER_VALUE_MASK (0xFFFFFFU) 4926 #define MRT_CHANNEL_TIMER_VALUE_SHIFT (0U) 4927 /*! VALUE - Holds the current timer value of the down-counter. The initial value of the TIMERn 4928 * register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval 4929 * or immediately in the following cases: INTVALn register is updated in the idle state. INTVALn 4930 * register is updated with LOAD = 1. When the timer is in idle state, reading this bit fields 4931 * returns -1 (0x00FF FFFF). 4932 */ 4933 #define MRT_CHANNEL_TIMER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_TIMER_VALUE_SHIFT)) & MRT_CHANNEL_TIMER_VALUE_MASK) 4934 /*! @} */ 4935 4936 /* The count of MRT_CHANNEL_TIMER */ 4937 #define MRT_CHANNEL_TIMER_COUNT (4U) 4938 4939 /*! @name CHANNEL_CTRL - MRT Control register. This register controls the MRT modes. */ 4940 /*! @{ */ 4941 #define MRT_CHANNEL_CTRL_INTEN_MASK (0x1U) 4942 #define MRT_CHANNEL_CTRL_INTEN_SHIFT (0U) 4943 /*! INTEN - Enable the TIMERn interrupt. 4944 * 0b0..Disabled. TIMERn interrupt is disabled. 4945 * 0b1..Enabled. TIMERn interrupt is enabled. 4946 */ 4947 #define MRT_CHANNEL_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_INTEN_SHIFT)) & MRT_CHANNEL_CTRL_INTEN_MASK) 4948 #define MRT_CHANNEL_CTRL_MODE_MASK (0x6U) 4949 #define MRT_CHANNEL_CTRL_MODE_SHIFT (1U) 4950 /*! MODE - Selects timer mode. 4951 * 0b00..Repeat interrupt mode. 4952 * 0b01..One-shot interrupt mode. 4953 * 0b10..One-shot stall mode. 4954 * 0b11..Reserved. 4955 */ 4956 #define MRT_CHANNEL_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_MODE_SHIFT)) & MRT_CHANNEL_CTRL_MODE_MASK) 4957 /*! @} */ 4958 4959 /* The count of MRT_CHANNEL_CTRL */ 4960 #define MRT_CHANNEL_CTRL_COUNT (4U) 4961 4962 /*! @name CHANNEL_STAT - MRT Status register. */ 4963 /*! @{ */ 4964 #define MRT_CHANNEL_STAT_INTFLAG_MASK (0x1U) 4965 #define MRT_CHANNEL_STAT_INTFLAG_SHIFT (0U) 4966 /*! INTFLAG - Monitors the interrupt flag. 4967 * 0b0..No pending interrupt. Writing a zero is equivalent to no operation. 4968 * 0b1..Pending interrupt. The interrupt is pending because TIMERn has reached the end of the time interval. If 4969 * the INTEN bit in the CONTROLn is also set to 1, the interrupt for timer channel n and the global interrupt 4970 * are raised. Writing a 1 to this bit clears the interrupt request. 4971 */ 4972 #define MRT_CHANNEL_STAT_INTFLAG(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INTFLAG_SHIFT)) & MRT_CHANNEL_STAT_INTFLAG_MASK) 4973 #define MRT_CHANNEL_STAT_RUN_MASK (0x2U) 4974 #define MRT_CHANNEL_STAT_RUN_SHIFT (1U) 4975 /*! RUN - Indicates the state of TIMERn. This bit is read-only. 4976 * 0b0..Idle state. TIMERn is stopped. 4977 * 0b1..Running. TIMERn is running. 4978 */ 4979 #define MRT_CHANNEL_STAT_RUN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_RUN_SHIFT)) & MRT_CHANNEL_STAT_RUN_MASK) 4980 #define MRT_CHANNEL_STAT_INUSE_MASK (0x4U) 4981 #define MRT_CHANNEL_STAT_INUSE_SHIFT (2U) 4982 /*! INUSE - Channel In Use flag. Operating details depend on the MULTITASK bit in the MODCFG 4983 * register, and affects the use of IDLE_CH. See Idle channel register for details of the two operating 4984 * modes. 4985 * 0b0..This channel is not in use. 4986 * 0b1..This channel is in use. 4987 */ 4988 #define MRT_CHANNEL_STAT_INUSE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INUSE_SHIFT)) & MRT_CHANNEL_STAT_INUSE_MASK) 4989 /*! @} */ 4990 4991 /* The count of MRT_CHANNEL_STAT */ 4992 #define MRT_CHANNEL_STAT_COUNT (4U) 4993 4994 /*! @name MODCFG - Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature. */ 4995 /*! @{ */ 4996 #define MRT_MODCFG_NOC_MASK (0xFU) 4997 #define MRT_MODCFG_NOC_SHIFT (0U) 4998 /*! NOC - Identifies the number of channels in this MRT.(4 channels on this device.) 4999 */ 5000 #define MRT_MODCFG_NOC(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOC_SHIFT)) & MRT_MODCFG_NOC_MASK) 5001 #define MRT_MODCFG_NOB_MASK (0x1F0U) 5002 #define MRT_MODCFG_NOB_SHIFT (4U) 5003 /*! NOB - Identifies the number of timer bits in this MRT. (24 bits wide on this device.) 5004 */ 5005 #define MRT_MODCFG_NOB(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOB_SHIFT)) & MRT_MODCFG_NOB_MASK) 5006 #define MRT_MODCFG_MULTITASK_MASK (0x80000000U) 5007 #define MRT_MODCFG_MULTITASK_SHIFT (31U) 5008 /*! MULTITASK - Selects the operating mode for the INUSE flags and the IDLE_CH register. 5009 * 0b0..Hardware status mode. In this mode, the INUSE(n) flags for all channels are reset. 5010 * 0b1..Multi-task mode. 5011 */ 5012 #define MRT_MODCFG_MULTITASK(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_MULTITASK_SHIFT)) & MRT_MODCFG_MULTITASK_MASK) 5013 /*! @} */ 5014 5015 /*! @name IDLE_CH - Idle channel register. This register returns the number of the first idle channel. */ 5016 /*! @{ */ 5017 #define MRT_IDLE_CH_CHAN_MASK (0xF0U) 5018 #define MRT_IDLE_CH_CHAN_SHIFT (4U) 5019 /*! CHAN - Idle channel. Reading the CHAN bits, returns the lowest idle timer channel. The number is 5020 * positioned such that it can be used as an offset from the MRT base address in order to access 5021 * the registers for the allocated channel. If all timer channels are running, CHAN = 0xF. See 5022 * text above for more details. 5023 */ 5024 #define MRT_IDLE_CH_CHAN(x) (((uint32_t)(((uint32_t)(x)) << MRT_IDLE_CH_CHAN_SHIFT)) & MRT_IDLE_CH_CHAN_MASK) 5025 /*! @} */ 5026 5027 /*! @name IRQ_FLAG - Global interrupt flag register */ 5028 /*! @{ */ 5029 #define MRT_IRQ_FLAG_GFLAG0_MASK (0x1U) 5030 #define MRT_IRQ_FLAG_GFLAG0_SHIFT (0U) 5031 /*! GFLAG0 - Monitors the interrupt flag of TIMER0. 5032 * 0b0..No pending interrupt. Writing a zero is equivalent to no operation. 5033 * 0b1..Pending interrupt. The interrupt is pending because TIMER0 has reached the end of the time interval. If 5034 * the INTEN bit in the CONTROL0 register is also set to 1, the interrupt for timer channel 0 and the global 5035 * interrupt are raised. Writing a 1 to this bit clears the interrupt request. 5036 */ 5037 #define MRT_IRQ_FLAG_GFLAG0(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG0_SHIFT)) & MRT_IRQ_FLAG_GFLAG0_MASK) 5038 #define MRT_IRQ_FLAG_GFLAG1_MASK (0x2U) 5039 #define MRT_IRQ_FLAG_GFLAG1_SHIFT (1U) 5040 /*! GFLAG1 - Monitors the interrupt flag of TIMER1. See description of channel 0. 5041 */ 5042 #define MRT_IRQ_FLAG_GFLAG1(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG1_SHIFT)) & MRT_IRQ_FLAG_GFLAG1_MASK) 5043 #define MRT_IRQ_FLAG_GFLAG2_MASK (0x4U) 5044 #define MRT_IRQ_FLAG_GFLAG2_SHIFT (2U) 5045 /*! GFLAG2 - Monitors the interrupt flag of TIMER2. See description of channel 0. 5046 */ 5047 #define MRT_IRQ_FLAG_GFLAG2(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG2_SHIFT)) & MRT_IRQ_FLAG_GFLAG2_MASK) 5048 #define MRT_IRQ_FLAG_GFLAG3_MASK (0x8U) 5049 #define MRT_IRQ_FLAG_GFLAG3_SHIFT (3U) 5050 /*! GFLAG3 - Monitors the interrupt flag of TIMER3. See description of channel 0. 5051 */ 5052 #define MRT_IRQ_FLAG_GFLAG3(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG3_SHIFT)) & MRT_IRQ_FLAG_GFLAG3_MASK) 5053 /*! @} */ 5054 5055 5056 /*! 5057 * @} 5058 */ /* end of group MRT_Register_Masks */ 5059 5060 5061 /* MRT - Peripheral instance base addresses */ 5062 /** Peripheral MRT0 base address */ 5063 #define MRT0_BASE (0x4000D000u) 5064 /** Peripheral MRT0 base pointer */ 5065 #define MRT0 ((MRT_Type *)MRT0_BASE) 5066 /** Array initializer of MRT peripheral base addresses */ 5067 #define MRT_BASE_ADDRS { MRT0_BASE } 5068 /** Array initializer of MRT peripheral base pointers */ 5069 #define MRT_BASE_PTRS { MRT0 } 5070 /** Interrupt vectors for the MRT peripheral type */ 5071 #define MRT_IRQS { MRT0_IRQn } 5072 5073 /*! 5074 * @} 5075 */ /* end of group MRT_Peripheral_Access_Layer */ 5076 5077 5078 /* ---------------------------------------------------------------------------- 5079 -- PINT Peripheral Access Layer 5080 ---------------------------------------------------------------------------- */ 5081 5082 /*! 5083 * @addtogroup PINT_Peripheral_Access_Layer PINT Peripheral Access Layer 5084 * @{ 5085 */ 5086 5087 /** PINT - Register Layout Typedef */ 5088 typedef struct { 5089 __IO uint32_t ISEL; /**< Pin Interrupt Mode register, offset: 0x0 */ 5090 __IO uint32_t IENR; /**< Pin interrupt level or rising edge interrupt enable register, offset: 0x4 */ 5091 __O uint32_t SIENR; /**< Pin interrupt level or rising edge interrupt set register, offset: 0x8 */ 5092 __O uint32_t CIENR; /**< Pin interrupt level (rising edge interrupt) clear register, offset: 0xC */ 5093 __IO uint32_t IENF; /**< Pin interrupt active level or falling edge interrupt enable register, offset: 0x10 */ 5094 __O uint32_t SIENF; /**< Pin interrupt active level or falling edge interrupt set register, offset: 0x14 */ 5095 __O uint32_t CIENF; /**< Pin interrupt active level or falling edge interrupt clear register, offset: 0x18 */ 5096 __IO uint32_t RISE; /**< Pin interrupt rising edge register, offset: 0x1C */ 5097 __IO uint32_t FALL; /**< Pin interrupt falling edge register, offset: 0x20 */ 5098 __IO uint32_t IST; /**< Pin interrupt status register, offset: 0x24 */ 5099 __IO uint32_t PMCTRL; /**< Pattern match interrupt control register, offset: 0x28 */ 5100 __IO uint32_t PMSRC; /**< Pattern match interrupt bit-slice source register, offset: 0x2C */ 5101 __IO uint32_t PMCFG; /**< Pattern match interrupt bit slice configuration register, offset: 0x30 */ 5102 } PINT_Type; 5103 5104 /* ---------------------------------------------------------------------------- 5105 -- PINT Register Masks 5106 ---------------------------------------------------------------------------- */ 5107 5108 /*! 5109 * @addtogroup PINT_Register_Masks PINT Register Masks 5110 * @{ 5111 */ 5112 5113 /*! @name ISEL - Pin Interrupt Mode register */ 5114 /*! @{ */ 5115 #define PINT_ISEL_PMODE_MASK (0xFFU) 5116 #define PINT_ISEL_PMODE_SHIFT (0U) 5117 /*! PMODE - Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt 5118 * selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive 5119 */ 5120 #define PINT_ISEL_PMODE(x) (((uint32_t)(((uint32_t)(x)) << PINT_ISEL_PMODE_SHIFT)) & PINT_ISEL_PMODE_MASK) 5121 /*! @} */ 5122 5123 /*! @name IENR - Pin interrupt level or rising edge interrupt enable register */ 5124 /*! @{ */ 5125 #define PINT_IENR_ENRL_MASK (0xFFU) 5126 #define PINT_IENR_ENRL_SHIFT (0U) 5127 /*! ENRL - Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the 5128 * pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable 5129 * rising edge or level interrupt. 5130 */ 5131 #define PINT_IENR_ENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENR_ENRL_SHIFT)) & PINT_IENR_ENRL_MASK) 5132 /*! @} */ 5133 5134 /*! @name SIENR - Pin interrupt level or rising edge interrupt set register */ 5135 /*! @{ */ 5136 #define PINT_SIENR_SETENRL_MASK (0xFFU) 5137 #define PINT_SIENR_SETENRL_SHIFT (0U) 5138 /*! SETENRL - Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n 5139 * sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt. 5140 */ 5141 #define PINT_SIENR_SETENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENR_SETENRL_SHIFT)) & PINT_SIENR_SETENRL_MASK) 5142 /*! @} */ 5143 5144 /*! @name CIENR - Pin interrupt level (rising edge interrupt) clear register */ 5145 /*! @{ */ 5146 #define PINT_CIENR_CENRL_MASK (0xFFU) 5147 #define PINT_CIENR_CENRL_SHIFT (0U) 5148 /*! CENRL - Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit 5149 * n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level 5150 * interrupt. 5151 */ 5152 #define PINT_CIENR_CENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENR_CENRL_SHIFT)) & PINT_CIENR_CENRL_MASK) 5153 /*! @} */ 5154 5155 /*! @name IENF - Pin interrupt active level or falling edge interrupt enable register */ 5156 /*! @{ */ 5157 #define PINT_IENF_ENAF_MASK (0xFFU) 5158 #define PINT_IENF_ENAF_SHIFT (0U) 5159 /*! ENAF - Enables the falling edge or configures the active level interrupt for each pin interrupt. 5160 * Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt 5161 * or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active 5162 * interrupt level HIGH. 5163 */ 5164 #define PINT_IENF_ENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENF_ENAF_SHIFT)) & PINT_IENF_ENAF_MASK) 5165 /*! @} */ 5166 5167 /*! @name SIENF - Pin interrupt active level or falling edge interrupt set register */ 5168 /*! @{ */ 5169 #define PINT_SIENF_SETENAF_MASK (0xFFU) 5170 #define PINT_SIENF_SETENAF_SHIFT (0U) 5171 /*! SETENAF - Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n 5172 * sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable 5173 * falling edge interrupt. 5174 */ 5175 #define PINT_SIENF_SETENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENF_SETENAF_SHIFT)) & PINT_SIENF_SETENAF_MASK) 5176 /*! @} */ 5177 5178 /*! @name CIENF - Pin interrupt active level or falling edge interrupt clear register */ 5179 /*! @{ */ 5180 #define PINT_CIENF_CENAF_MASK (0xFFU) 5181 #define PINT_CIENF_CENAF_SHIFT (0U) 5182 /*! CENAF - Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n 5183 * clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or 5184 * falling edge interrupt disabled. 5185 */ 5186 #define PINT_CIENF_CENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENF_CENAF_SHIFT)) & PINT_CIENF_CENAF_MASK) 5187 /*! @} */ 5188 5189 /*! @name RISE - Pin interrupt rising edge register */ 5190 /*! @{ */ 5191 #define PINT_RISE_RDET_MASK (0xFFU) 5192 #define PINT_RISE_RDET_SHIFT (0U) 5193 /*! RDET - Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 5194 * 0: No rising edge has been detected on this pin since Reset or the last time a one was written 5195 * to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the 5196 * last time a one was written to this bit. Write 1: clear rising edge detection for this pin. 5197 */ 5198 #define PINT_RISE_RDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_RISE_RDET_SHIFT)) & PINT_RISE_RDET_MASK) 5199 /*! @} */ 5200 5201 /*! @name FALL - Pin interrupt falling edge register */ 5202 /*! @{ */ 5203 #define PINT_FALL_FDET_MASK (0xFFU) 5204 #define PINT_FALL_FDET_SHIFT (0U) 5205 /*! FDET - Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 5206 * 0: No falling edge has been detected on this pin since Reset or the last time a one was 5207 * written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or 5208 * the last time a one was written to this bit. Write 1: clear falling edge detection for this 5209 * pin. 5210 */ 5211 #define PINT_FALL_FDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_FALL_FDET_SHIFT)) & PINT_FALL_FDET_MASK) 5212 /*! @} */ 5213 5214 /*! @name IST - Pin interrupt status register */ 5215 /*! @{ */ 5216 #define PINT_IST_PSTAT_MASK (0xFFU) 5217 #define PINT_IST_PSTAT_SHIFT (0U) 5218 /*! PSTAT - Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts 5219 * the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for 5220 * this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this 5221 * interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. 5222 * Write 1 (level-sensitive): switch the active level for this pin (in the IENF register). 5223 */ 5224 #define PINT_IST_PSTAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_IST_PSTAT_SHIFT)) & PINT_IST_PSTAT_MASK) 5225 /*! @} */ 5226 5227 /*! @name PMCTRL - Pattern match interrupt control register */ 5228 /*! @{ */ 5229 #define PINT_PMCTRL_SEL_PMATCH_MASK (0x1U) 5230 #define PINT_PMCTRL_SEL_PMATCH_SHIFT (0U) 5231 /*! SEL_PMATCH - Specifies whether the 8 pin interrupts are controlled by the pin interrupt function or by the pattern match function. 5232 * 0b0..Pin interrupt. Interrupts are driven in response to the standard pin interrupt function. 5233 * 0b1..Pattern match. Interrupts are driven in response to pattern matches. 5234 */ 5235 #define PINT_PMCTRL_SEL_PMATCH(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_SEL_PMATCH_SHIFT)) & PINT_PMCTRL_SEL_PMATCH_MASK) 5236 #define PINT_PMCTRL_ENA_RXEV_MASK (0x2U) 5237 #define PINT_PMCTRL_ENA_RXEV_SHIFT (1U) 5238 /*! ENA_RXEV - Enables the RXEV output to the CPU and/or to a GPIO output when the specified boolean expression evaluates to true. 5239 * 0b0..Disabled. RXEV output to the CPU is disabled. 5240 * 0b1..Enabled. RXEV output to the CPU is enabled. 5241 */ 5242 #define PINT_PMCTRL_ENA_RXEV(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_ENA_RXEV_SHIFT)) & PINT_PMCTRL_ENA_RXEV_MASK) 5243 #define PINT_PMCTRL_PMAT_MASK (0xFF000000U) 5244 #define PINT_PMCTRL_PMAT_SHIFT (24U) 5245 /*! PMAT - This field displays the current state of pattern matches. A 1 in any bit of this field 5246 * indicates that the corresponding product term is matched by the current state of the appropriate 5247 * inputs. 5248 */ 5249 #define PINT_PMCTRL_PMAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_PMAT_SHIFT)) & PINT_PMCTRL_PMAT_MASK) 5250 /*! @} */ 5251 5252 /*! @name PMSRC - Pattern match interrupt bit-slice source register */ 5253 /*! @{ */ 5254 #define PINT_PMSRC_SRC0_MASK (0x700U) 5255 #define PINT_PMSRC_SRC0_SHIFT (8U) 5256 /*! SRC0 - Selects the input source for bit slice 0 5257 * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 0. 5258 * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 0. 5259 * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 0. 5260 * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 0. 5261 * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 0. 5262 * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 0. 5263 * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 0. 5264 * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 0. 5265 */ 5266 #define PINT_PMSRC_SRC0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC0_SHIFT)) & PINT_PMSRC_SRC0_MASK) 5267 #define PINT_PMSRC_SRC1_MASK (0x3800U) 5268 #define PINT_PMSRC_SRC1_SHIFT (11U) 5269 /*! SRC1 - Selects the input source for bit slice 1 5270 * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 1. 5271 * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 1. 5272 * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 1. 5273 * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 1. 5274 * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 1. 5275 * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 1. 5276 * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 1. 5277 * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 1. 5278 */ 5279 #define PINT_PMSRC_SRC1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC1_SHIFT)) & PINT_PMSRC_SRC1_MASK) 5280 #define PINT_PMSRC_SRC2_MASK (0x1C000U) 5281 #define PINT_PMSRC_SRC2_SHIFT (14U) 5282 /*! SRC2 - Selects the input source for bit slice 2 5283 * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 2. 5284 * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 2. 5285 * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 2. 5286 * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 2. 5287 * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 2. 5288 * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 2. 5289 * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 2. 5290 * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 2. 5291 */ 5292 #define PINT_PMSRC_SRC2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC2_SHIFT)) & PINT_PMSRC_SRC2_MASK) 5293 #define PINT_PMSRC_SRC3_MASK (0xE0000U) 5294 #define PINT_PMSRC_SRC3_SHIFT (17U) 5295 /*! SRC3 - Selects the input source for bit slice 3 5296 * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 3. 5297 * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 3. 5298 * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 3. 5299 * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 3. 5300 * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 3. 5301 * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 3. 5302 * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 3. 5303 * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 3. 5304 */ 5305 #define PINT_PMSRC_SRC3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC3_SHIFT)) & PINT_PMSRC_SRC3_MASK) 5306 #define PINT_PMSRC_SRC4_MASK (0x700000U) 5307 #define PINT_PMSRC_SRC4_SHIFT (20U) 5308 /*! SRC4 - Selects the input source for bit slice 4 5309 * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 4. 5310 * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 4. 5311 * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 4. 5312 * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 4. 5313 * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 4. 5314 * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 4. 5315 * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 4. 5316 * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 4. 5317 */ 5318 #define PINT_PMSRC_SRC4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC4_SHIFT)) & PINT_PMSRC_SRC4_MASK) 5319 #define PINT_PMSRC_SRC5_MASK (0x3800000U) 5320 #define PINT_PMSRC_SRC5_SHIFT (23U) 5321 /*! SRC5 - Selects the input source for bit slice 5 5322 * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 5. 5323 * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 5. 5324 * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 5. 5325 * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 5. 5326 * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 5. 5327 * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 5. 5328 * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 5. 5329 * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 5. 5330 */ 5331 #define PINT_PMSRC_SRC5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC5_SHIFT)) & PINT_PMSRC_SRC5_MASK) 5332 #define PINT_PMSRC_SRC6_MASK (0x1C000000U) 5333 #define PINT_PMSRC_SRC6_SHIFT (26U) 5334 /*! SRC6 - Selects the input source for bit slice 6 5335 * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 6. 5336 * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 6. 5337 * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 6. 5338 * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 6. 5339 * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 6. 5340 * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 6. 5341 * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 6. 5342 * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 6. 5343 */ 5344 #define PINT_PMSRC_SRC6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC6_SHIFT)) & PINT_PMSRC_SRC6_MASK) 5345 #define PINT_PMSRC_SRC7_MASK (0xE0000000U) 5346 #define PINT_PMSRC_SRC7_SHIFT (29U) 5347 /*! SRC7 - Selects the input source for bit slice 7 5348 * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 7. 5349 * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 7. 5350 * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 7. 5351 * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 7. 5352 * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 7. 5353 * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 7. 5354 * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 7. 5355 * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 7. 5356 */ 5357 #define PINT_PMSRC_SRC7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC7_SHIFT)) & PINT_PMSRC_SRC7_MASK) 5358 /*! @} */ 5359 5360 /*! @name PMCFG - Pattern match interrupt bit slice configuration register */ 5361 /*! @{ */ 5362 #define PINT_PMCFG_PROD_ENDPTS0_MASK (0x1U) 5363 #define PINT_PMCFG_PROD_ENDPTS0_SHIFT (0U) 5364 /*! PROD_ENDPTS0 - Determines whether slice 0 is an endpoint. 5365 * 0b0..No effect. Slice 0 is not an endpoint. 5366 * 0b1..endpoint. Slice 0 is the endpoint of a product term (minterm). Pin interrupt 0 in the NVIC is raised if the minterm evaluates as true. 5367 */ 5368 #define PINT_PMCFG_PROD_ENDPTS0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS0_SHIFT)) & PINT_PMCFG_PROD_ENDPTS0_MASK) 5369 #define PINT_PMCFG_PROD_ENDPTS1_MASK (0x2U) 5370 #define PINT_PMCFG_PROD_ENDPTS1_SHIFT (1U) 5371 /*! PROD_ENDPTS1 - Determines whether slice 1 is an endpoint. 5372 * 0b0..No effect. Slice 1 is not an endpoint. 5373 * 0b1..endpoint. Slice 1 is the endpoint of a product term (minterm). Pin interrupt 1 in the NVIC is raised if the minterm evaluates as true. 5374 */ 5375 #define PINT_PMCFG_PROD_ENDPTS1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS1_SHIFT)) & PINT_PMCFG_PROD_ENDPTS1_MASK) 5376 #define PINT_PMCFG_PROD_ENDPTS2_MASK (0x4U) 5377 #define PINT_PMCFG_PROD_ENDPTS2_SHIFT (2U) 5378 /*! PROD_ENDPTS2 - Determines whether slice 2 is an endpoint. 5379 * 0b0..No effect. Slice 2 is not an endpoint. 5380 * 0b1..endpoint. Slice 2 is the endpoint of a product term (minterm). Pin interrupt 2 in the NVIC is raised if the minterm evaluates as true. 5381 */ 5382 #define PINT_PMCFG_PROD_ENDPTS2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS2_SHIFT)) & PINT_PMCFG_PROD_ENDPTS2_MASK) 5383 #define PINT_PMCFG_PROD_ENDPTS3_MASK (0x8U) 5384 #define PINT_PMCFG_PROD_ENDPTS3_SHIFT (3U) 5385 /*! PROD_ENDPTS3 - Determines whether slice 3 is an endpoint. 5386 * 0b0..No effect. Slice 3 is not an endpoint. 5387 * 0b1..endpoint. Slice 3 is the endpoint of a product term (minterm). Pin interrupt 3 in the NVIC is raised if the minterm evaluates as true. 5388 */ 5389 #define PINT_PMCFG_PROD_ENDPTS3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS3_SHIFT)) & PINT_PMCFG_PROD_ENDPTS3_MASK) 5390 #define PINT_PMCFG_PROD_ENDPTS4_MASK (0x10U) 5391 #define PINT_PMCFG_PROD_ENDPTS4_SHIFT (4U) 5392 /*! PROD_ENDPTS4 - Determines whether slice 4 is an endpoint. 5393 * 0b0..No effect. Slice 4 is not an endpoint. 5394 * 0b1..endpoint. Slice 4 is the endpoint of a product term (minterm). Pin interrupt 4 in the NVIC is raised if the minterm evaluates as true. 5395 */ 5396 #define PINT_PMCFG_PROD_ENDPTS4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS4_SHIFT)) & PINT_PMCFG_PROD_ENDPTS4_MASK) 5397 #define PINT_PMCFG_PROD_ENDPTS5_MASK (0x20U) 5398 #define PINT_PMCFG_PROD_ENDPTS5_SHIFT (5U) 5399 /*! PROD_ENDPTS5 - Determines whether slice 5 is an endpoint. 5400 * 0b0..No effect. Slice 5 is not an endpoint. 5401 * 0b1..endpoint. Slice 5 is the endpoint of a product term (minterm). Pin interrupt 5 in the NVIC is raised if the minterm evaluates as true. 5402 */ 5403 #define PINT_PMCFG_PROD_ENDPTS5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS5_SHIFT)) & PINT_PMCFG_PROD_ENDPTS5_MASK) 5404 #define PINT_PMCFG_PROD_ENDPTS6_MASK (0x40U) 5405 #define PINT_PMCFG_PROD_ENDPTS6_SHIFT (6U) 5406 /*! PROD_ENDPTS6 - Determines whether slice 6 is an endpoint. 5407 * 0b0..No effect. Slice 6 is not an endpoint. 5408 * 0b1..endpoint. Slice 6 is the endpoint of a product term (minterm). Pin interrupt 6 in the NVIC is raised if the minterm evaluates as true. 5409 */ 5410 #define PINT_PMCFG_PROD_ENDPTS6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS6_SHIFT)) & PINT_PMCFG_PROD_ENDPTS6_MASK) 5411 #define PINT_PMCFG_CFG0_MASK (0x700U) 5412 #define PINT_PMCFG_CFG0_SHIFT (8U) 5413 /*! CFG0 - Specifies the match contribution condition for bit slice 0. 5414 * 0b000..Constant HIGH. This bit slice always contributes to a product term match. 5415 * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last 5416 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the 5417 * PMSRC registers are written to. 5418 * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last 5419 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the 5420 * PMSRC registers are written to. 5421 * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input 5422 * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only 5423 * cleared when the PMCFG or the PMSRC registers are written to. 5424 * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 5425 * 0b101..Low level. Match occurs when there is a low level on the specified input. 5426 * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). 5427 * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or 5428 * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit 5429 * is cleared after one clock cycle. 5430 */ 5431 #define PINT_PMCFG_CFG0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG0_SHIFT)) & PINT_PMCFG_CFG0_MASK) 5432 #define PINT_PMCFG_CFG1_MASK (0x3800U) 5433 #define PINT_PMCFG_CFG1_SHIFT (11U) 5434 /*! CFG1 - Specifies the match contribution condition for bit slice 1. 5435 * 0b000..Constant HIGH. This bit slice always contributes to a product term match. 5436 * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last 5437 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the 5438 * PMSRC registers are written to. 5439 * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last 5440 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the 5441 * PMSRC registers are written to. 5442 * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input 5443 * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only 5444 * cleared when the PMCFG or the PMSRC registers are written to. 5445 * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 5446 * 0b101..Low level. Match occurs when there is a low level on the specified input. 5447 * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). 5448 * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or 5449 * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit 5450 * is cleared after one clock cycle. 5451 */ 5452 #define PINT_PMCFG_CFG1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG1_SHIFT)) & PINT_PMCFG_CFG1_MASK) 5453 #define PINT_PMCFG_CFG2_MASK (0x1C000U) 5454 #define PINT_PMCFG_CFG2_SHIFT (14U) 5455 /*! CFG2 - Specifies the match contribution condition for bit slice 2. 5456 * 0b000..Constant HIGH. This bit slice always contributes to a product term match. 5457 * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last 5458 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the 5459 * PMSRC registers are written to. 5460 * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last 5461 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the 5462 * PMSRC registers are written to. 5463 * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input 5464 * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only 5465 * cleared when the PMCFG or the PMSRC registers are written to. 5466 * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 5467 * 0b101..Low level. Match occurs when there is a low level on the specified input. 5468 * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). 5469 * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or 5470 * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit 5471 * is cleared after one clock cycle. 5472 */ 5473 #define PINT_PMCFG_CFG2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG2_SHIFT)) & PINT_PMCFG_CFG2_MASK) 5474 #define PINT_PMCFG_CFG3_MASK (0xE0000U) 5475 #define PINT_PMCFG_CFG3_SHIFT (17U) 5476 /*! CFG3 - Specifies the match contribution condition for bit slice 3. 5477 * 0b000..Constant HIGH. This bit slice always contributes to a product term match. 5478 * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last 5479 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the 5480 * PMSRC registers are written to. 5481 * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last 5482 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the 5483 * PMSRC registers are written to. 5484 * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input 5485 * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only 5486 * cleared when the PMCFG or the PMSRC registers are written to. 5487 * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 5488 * 0b101..Low level. Match occurs when there is a low level on the specified input. 5489 * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). 5490 * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or 5491 * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit 5492 * is cleared after one clock cycle. 5493 */ 5494 #define PINT_PMCFG_CFG3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG3_SHIFT)) & PINT_PMCFG_CFG3_MASK) 5495 #define PINT_PMCFG_CFG4_MASK (0x700000U) 5496 #define PINT_PMCFG_CFG4_SHIFT (20U) 5497 /*! CFG4 - Specifies the match contribution condition for bit slice 4. 5498 * 0b000..Constant HIGH. This bit slice always contributes to a product term match. 5499 * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last 5500 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the 5501 * PMSRC registers are written to. 5502 * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last 5503 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the 5504 * PMSRC registers are written to. 5505 * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input 5506 * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only 5507 * cleared when the PMCFG or the PMSRC registers are written to. 5508 * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 5509 * 0b101..Low level. Match occurs when there is a low level on the specified input. 5510 * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). 5511 * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or 5512 * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit 5513 * is cleared after one clock cycle. 5514 */ 5515 #define PINT_PMCFG_CFG4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG4_SHIFT)) & PINT_PMCFG_CFG4_MASK) 5516 #define PINT_PMCFG_CFG5_MASK (0x3800000U) 5517 #define PINT_PMCFG_CFG5_SHIFT (23U) 5518 /*! CFG5 - Specifies the match contribution condition for bit slice 5. 5519 * 0b000..Constant HIGH. This bit slice always contributes to a product term match. 5520 * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last 5521 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the 5522 * PMSRC registers are written to. 5523 * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last 5524 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the 5525 * PMSRC registers are written to. 5526 * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input 5527 * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only 5528 * cleared when the PMCFG or the PMSRC registers are written to. 5529 * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 5530 * 0b101..Low level. Match occurs when there is a low level on the specified input. 5531 * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). 5532 * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or 5533 * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit 5534 * is cleared after one clock cycle. 5535 */ 5536 #define PINT_PMCFG_CFG5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG5_SHIFT)) & PINT_PMCFG_CFG5_MASK) 5537 #define PINT_PMCFG_CFG6_MASK (0x1C000000U) 5538 #define PINT_PMCFG_CFG6_SHIFT (26U) 5539 /*! CFG6 - Specifies the match contribution condition for bit slice 6. 5540 * 0b000..Constant HIGH. This bit slice always contributes to a product term match. 5541 * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last 5542 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the 5543 * PMSRC registers are written to. 5544 * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last 5545 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the 5546 * PMSRC registers are written to. 5547 * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input 5548 * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only 5549 * cleared when the PMCFG or the PMSRC registers are written to. 5550 * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 5551 * 0b101..Low level. Match occurs when there is a low level on the specified input. 5552 * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). 5553 * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or 5554 * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit 5555 * is cleared after one clock cycle. 5556 */ 5557 #define PINT_PMCFG_CFG6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG6_SHIFT)) & PINT_PMCFG_CFG6_MASK) 5558 #define PINT_PMCFG_CFG7_MASK (0xE0000000U) 5559 #define PINT_PMCFG_CFG7_SHIFT (29U) 5560 /*! CFG7 - Specifies the match contribution condition for bit slice 7. 5561 * 0b000..Constant HIGH. This bit slice always contributes to a product term match. 5562 * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last 5563 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the 5564 * PMSRC registers are written to. 5565 * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last 5566 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the 5567 * PMSRC registers are written to. 5568 * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input 5569 * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only 5570 * cleared when the PMCFG or the PMSRC registers are written to. 5571 * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 5572 * 0b101..Low level. Match occurs when there is a low level on the specified input. 5573 * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). 5574 * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or 5575 * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit 5576 * is cleared after one clock cycle. 5577 */ 5578 #define PINT_PMCFG_CFG7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG7_SHIFT)) & PINT_PMCFG_CFG7_MASK) 5579 /*! @} */ 5580 5581 5582 /*! 5583 * @} 5584 */ /* end of group PINT_Register_Masks */ 5585 5586 5587 /* PINT - Peripheral instance base addresses */ 5588 /** Peripheral PINT base address */ 5589 #define PINT_BASE (0x40004000u) 5590 /** Peripheral PINT base pointer */ 5591 #define PINT ((PINT_Type *)PINT_BASE) 5592 /** Array initializer of PINT peripheral base addresses */ 5593 #define PINT_BASE_ADDRS { PINT_BASE } 5594 /** Array initializer of PINT peripheral base pointers */ 5595 #define PINT_BASE_PTRS { PINT } 5596 /** Interrupt vectors for the PINT peripheral type */ 5597 #define PINT_IRQS { PIN_INT0_IRQn, PIN_INT1_IRQn, PIN_INT2_IRQn, PIN_INT3_IRQn, PIN_INT4_IRQn, PIN_INT5_IRQn, PIN_INT6_IRQn, PIN_INT7_IRQn } 5598 5599 /*! 5600 * @} 5601 */ /* end of group PINT_Peripheral_Access_Layer */ 5602 5603 5604 /* ---------------------------------------------------------------------------- 5605 -- RTC Peripheral Access Layer 5606 ---------------------------------------------------------------------------- */ 5607 5608 /*! 5609 * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer 5610 * @{ 5611 */ 5612 5613 /** RTC - Register Layout Typedef */ 5614 typedef struct { 5615 __IO uint32_t CTRL; /**< RTC control register, offset: 0x0 */ 5616 __IO uint32_t MATCH; /**< RTC match register, offset: 0x4 */ 5617 __IO uint32_t COUNT; /**< RTC counter register, offset: 0x8 */ 5618 __IO uint32_t WAKE; /**< High-resolution/wake-up timer control register, offset: 0xC */ 5619 } RTC_Type; 5620 5621 /* ---------------------------------------------------------------------------- 5622 -- RTC Register Masks 5623 ---------------------------------------------------------------------------- */ 5624 5625 /*! 5626 * @addtogroup RTC_Register_Masks RTC Register Masks 5627 * @{ 5628 */ 5629 5630 /*! @name CTRL - RTC control register */ 5631 /*! @{ */ 5632 #define RTC_CTRL_SWRESET_MASK (0x1U) 5633 #define RTC_CTRL_SWRESET_SHIFT (0U) 5634 /*! SWRESET - Software reset control 5635 * 0b0..Not in reset. The RTC is not held in reset. This bit must be cleared prior to configuring or initiating any operation of the RTC. 5636 * 0b1..In reset. The RTC is held in reset. All register bits within the RTC will be forced to their reset value 5637 * except the OFD bit. This bit must be cleared before writing to any register in the RTC - including writes 5638 * to set any of the other bits within this register. Do not attempt to write to any bits of this register at 5639 * the same time that the reset bit is being cleared. 5640 */ 5641 #define RTC_CTRL_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_SWRESET_SHIFT)) & RTC_CTRL_SWRESET_MASK) 5642 #define RTC_CTRL_ALARM1HZ_MASK (0x4U) 5643 #define RTC_CTRL_ALARM1HZ_SHIFT (2U) 5644 /*! ALARM1HZ - RTC 1 Hz timer alarm flag status. 5645 * 0b0..No match. No match has occurred on the 1 Hz RTC timer. Writing a 0 has no effect. 5646 * 0b1..Match. A match condition has occurred on the 1 Hz RTC timer. This flag generates an RTC alarm interrupt 5647 * request RTC_ALARM which can also wake up the part from any low power mode. Writing a 1 clears this bit. 5648 */ 5649 #define RTC_CTRL_ALARM1HZ(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARM1HZ_SHIFT)) & RTC_CTRL_ALARM1HZ_MASK) 5650 #define RTC_CTRL_WAKE1KHZ_MASK (0x8U) 5651 #define RTC_CTRL_WAKE1KHZ_SHIFT (3U) 5652 /*! WAKE1KHZ - RTC 1 kHz timer wake-up flag status. 5653 * 0b0..Run. The RTC 1 kHz timer is running. Writing a 0 has no effect. 5654 * 0b1..Time-out. The 1 kHz high-resolution/wake-up timer has timed out. This flag generates an RTC wake-up 5655 * interrupt request RTC-WAKE which can also wake up the part from any low power mode. Writing a 1 clears this bit. 5656 */ 5657 #define RTC_CTRL_WAKE1KHZ(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKE1KHZ_SHIFT)) & RTC_CTRL_WAKE1KHZ_MASK) 5658 #define RTC_CTRL_ALARMDPD_EN_MASK (0x10U) 5659 #define RTC_CTRL_ALARMDPD_EN_SHIFT (4U) 5660 /*! ALARMDPD_EN - RTC 1 Hz timer alarm enable for Deep power-down. 5661 * 0b0..Disable. A match on the 1 Hz RTC timer will not bring the part out of Deep power-down mode. 5662 * 0b1..Enable. A match on the 1 Hz RTC timer bring the part out of Deep power-down mode. 5663 */ 5664 #define RTC_CTRL_ALARMDPD_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARMDPD_EN_SHIFT)) & RTC_CTRL_ALARMDPD_EN_MASK) 5665 #define RTC_CTRL_WAKEDPD_EN_MASK (0x20U) 5666 #define RTC_CTRL_WAKEDPD_EN_SHIFT (5U) 5667 /*! WAKEDPD_EN - RTC 1 kHz timer wake-up enable for Deep power-down. 5668 * 0b0..Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode. 5669 * 0b1..Enable. A match on the 1 kHz RTC timer bring the part out of Deep power-down mode. 5670 */ 5671 #define RTC_CTRL_WAKEDPD_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKEDPD_EN_SHIFT)) & RTC_CTRL_WAKEDPD_EN_MASK) 5672 #define RTC_CTRL_RTC1KHZ_EN_MASK (0x40U) 5673 #define RTC_CTRL_RTC1KHZ_EN_SHIFT (6U) 5674 /*! RTC1KHZ_EN - RTC 1 kHz clock enable. This bit can be set to 0 to conserve power if the 1 kHz 5675 * timer is not used. This bit has no effect when the RTC is disabled (bit 7 of this register is 0). 5676 * 0b0..Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode. 5677 * 0b1..Enable. The 1 kHz RTC timer is enabled. 5678 */ 5679 #define RTC_CTRL_RTC1KHZ_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC1KHZ_EN_SHIFT)) & RTC_CTRL_RTC1KHZ_EN_MASK) 5680 #define RTC_CTRL_RTC_EN_MASK (0x80U) 5681 #define RTC_CTRL_RTC_EN_SHIFT (7U) 5682 /*! RTC_EN - RTC enable. 5683 * 0b0..Disable. The RTC 1 Hz and 1 kHz clocks are shut down and the RTC operation is disabled. This bit should 5684 * be 0 when writing to load a value in the RTC counter register. 5685 * 0b1..Enable. The 1 Hz RTC clock is running and RTC operation is enabled. This bit must be set to initiate 5686 * operation of the RTC. The first clock to the RTC counter occurs 1 s after this bit is set. To also enable the 5687 * high-resolution, 1 kHz clock, set bit 6 in this register. 5688 */ 5689 #define RTC_CTRL_RTC_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_EN_SHIFT)) & RTC_CTRL_RTC_EN_MASK) 5690 #define RTC_CTRL_RTC_OSC_PD_MASK (0x100U) 5691 #define RTC_CTRL_RTC_OSC_PD_SHIFT (8U) 5692 /*! RTC_OSC_PD - RTC oscillator power-down control. 5693 * 0b0..See RTC_OSC_BYPASS 5694 * 0b1..RTC oscillator is powered-down. 5695 */ 5696 #define RTC_CTRL_RTC_OSC_PD(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_OSC_PD_SHIFT)) & RTC_CTRL_RTC_OSC_PD_MASK) 5697 #define RTC_CTRL_RTC_OSC_BYPASS_MASK (0x200U) 5698 #define RTC_CTRL_RTC_OSC_BYPASS_SHIFT (9U) 5699 /*! RTC_OSC_BYPASS - RTC oscillator bypass control. 5700 * 0b0..RTC oscillator is in normal crystal oscillation mode. 5701 * 0b1..RTC oscillator is bypassed. RTCXIN may be driven by an external clock. 5702 */ 5703 #define RTC_CTRL_RTC_OSC_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_OSC_BYPASS_SHIFT)) & RTC_CTRL_RTC_OSC_BYPASS_MASK) 5704 /*! @} */ 5705 5706 /*! @name MATCH - RTC match register */ 5707 /*! @{ */ 5708 #define RTC_MATCH_MATVAL_MASK (0xFFFFFFFFU) 5709 #define RTC_MATCH_MATVAL_SHIFT (0U) 5710 /*! MATVAL - Contains the match value against which the 1 Hz RTC timer will be compared to set the 5711 * alarm flag RTC_ALARM and generate an alarm interrupt/wake-up if enabled. 5712 */ 5713 #define RTC_MATCH_MATVAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_MATCH_MATVAL_SHIFT)) & RTC_MATCH_MATVAL_MASK) 5714 /*! @} */ 5715 5716 /*! @name COUNT - RTC counter register */ 5717 /*! @{ */ 5718 #define RTC_COUNT_VAL_MASK (0xFFFFFFFFU) 5719 #define RTC_COUNT_VAL_SHIFT (0U) 5720 /*! VAL - A read reflects the current value of the main, 1 Hz RTC timer. A write loads a new initial 5721 * value into the timer. The RTC counter will count up continuously at a 1 Hz rate once the RTC 5722 * Software Reset is removed (by clearing bit 0 of the CTRL register). Only write to this 5723 * register when the RTC_EN bit in the RTC CTRL Register is 0. The counter increments one second after 5724 * the RTC_EN bit is set. 5725 */ 5726 #define RTC_COUNT_VAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_COUNT_VAL_SHIFT)) & RTC_COUNT_VAL_MASK) 5727 /*! @} */ 5728 5729 /*! @name WAKE - High-resolution/wake-up timer control register */ 5730 /*! @{ */ 5731 #define RTC_WAKE_VAL_MASK (0xFFFFU) 5732 #define RTC_WAKE_VAL_SHIFT (0U) 5733 /*! VAL - A read reflects the current value of the high-resolution/wake-up timer. A write pre-loads 5734 * a start count value into the wake-up timer and initializes a count-down sequence. Do not write 5735 * to this register while counting is in progress. 5736 */ 5737 #define RTC_WAKE_VAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_VAL_SHIFT)) & RTC_WAKE_VAL_MASK) 5738 /*! @} */ 5739 5740 5741 /*! 5742 * @} 5743 */ /* end of group RTC_Register_Masks */ 5744 5745 5746 /* RTC - Peripheral instance base addresses */ 5747 /** Peripheral RTC base address */ 5748 #define RTC_BASE (0x4002C000u) 5749 /** Peripheral RTC base pointer */ 5750 #define RTC ((RTC_Type *)RTC_BASE) 5751 /** Array initializer of RTC peripheral base addresses */ 5752 #define RTC_BASE_ADDRS { RTC_BASE } 5753 /** Array initializer of RTC peripheral base pointers */ 5754 #define RTC_BASE_PTRS { RTC } 5755 /** Interrupt vectors for the RTC peripheral type */ 5756 #define RTC_IRQS { RTC_IRQn } 5757 5758 /*! 5759 * @} 5760 */ /* end of group RTC_Peripheral_Access_Layer */ 5761 5762 5763 /* ---------------------------------------------------------------------------- 5764 -- SCT Peripheral Access Layer 5765 ---------------------------------------------------------------------------- */ 5766 5767 /*! 5768 * @addtogroup SCT_Peripheral_Access_Layer SCT Peripheral Access Layer 5769 * @{ 5770 */ 5771 5772 /** SCT - Register Layout Typedef */ 5773 typedef struct { 5774 __IO uint32_t CONFIG; /**< SCT configuration register, offset: 0x0 */ 5775 union { /* offset: 0x4 */ 5776 struct { /* offset: 0x4 */ 5777 __IO uint16_t CTRLL; /**< SCT_CTRLL register, offset: 0x4 */ 5778 __IO uint16_t CTRLH; /**< SCT_CTRLH register, offset: 0x6 */ 5779 } CTRL_ACCESS16BIT; 5780 __IO uint32_t CTRL; /**< SCT control register, offset: 0x4 */ 5781 }; 5782 union { /* offset: 0x8 */ 5783 struct { /* offset: 0x8 */ 5784 __IO uint16_t LIMITL; /**< SCT_LIMITL register, offset: 0x8 */ 5785 __IO uint16_t LIMITH; /**< SCT_LIMITH register, offset: 0xA */ 5786 } LIMIT_ACCESS16BIT; 5787 __IO uint32_t LIMIT; /**< SCT limit event select register, offset: 0x8 */ 5788 }; 5789 union { /* offset: 0xC */ 5790 struct { /* offset: 0xC */ 5791 __IO uint16_t HALTL; /**< SCT_HALTL register, offset: 0xC */ 5792 __IO uint16_t HALTH; /**< SCT_HALTH register, offset: 0xE */ 5793 } HALT_ACCESS16BIT; 5794 __IO uint32_t HALT; /**< SCT halt event select register, offset: 0xC */ 5795 }; 5796 union { /* offset: 0x10 */ 5797 struct { /* offset: 0x10 */ 5798 __IO uint16_t STOPL; /**< SCT_STOPL register, offset: 0x10 */ 5799 __IO uint16_t STOPH; /**< SCT_STOPH register, offset: 0x12 */ 5800 } STOP_ACCESS16BIT; 5801 __IO uint32_t STOP; /**< SCT stop event select register, offset: 0x10 */ 5802 }; 5803 union { /* offset: 0x14 */ 5804 struct { /* offset: 0x14 */ 5805 __IO uint16_t STARTL; /**< SCT_STARTL register, offset: 0x14 */ 5806 __IO uint16_t STARTH; /**< SCT_STARTH register, offset: 0x16 */ 5807 } START_ACCESS16BIT; 5808 __IO uint32_t START; /**< SCT start event select register, offset: 0x14 */ 5809 }; 5810 uint8_t RESERVED_0[40]; 5811 union { /* offset: 0x40 */ 5812 struct { /* offset: 0x40 */ 5813 __IO uint16_t COUNTL; /**< SCT_COUNTL register, offset: 0x40 */ 5814 __IO uint16_t COUNTH; /**< SCT_COUNTH register, offset: 0x42 */ 5815 } COUNT_ACCESS16BIT; 5816 __IO uint32_t COUNT; /**< SCT counter register, offset: 0x40 */ 5817 }; 5818 union { /* offset: 0x44 */ 5819 struct { /* offset: 0x44 */ 5820 __IO uint16_t STATEL; /**< SCT_STATEL register, offset: 0x44 */ 5821 __IO uint16_t STATEH; /**< SCT_STATEH register, offset: 0x46 */ 5822 } STATE_ACCESS16BIT; 5823 __IO uint32_t STATE; /**< SCT state register, offset: 0x44 */ 5824 }; 5825 __I uint32_t INPUT; /**< SCT input register, offset: 0x48 */ 5826 union { /* offset: 0x4C */ 5827 struct { /* offset: 0x4C */ 5828 __IO uint16_t REGMODEL; /**< SCT_REGMODEL register, offset: 0x4C */ 5829 __IO uint16_t REGMODEH; /**< SCT_REGMODEH register, offset: 0x4E */ 5830 } REGMODE_ACCESS16BIT; 5831 __IO uint32_t REGMODE; /**< SCT match/capture mode register, offset: 0x4C */ 5832 }; 5833 __IO uint32_t OUTPUT; /**< SCT output register, offset: 0x50 */ 5834 __IO uint32_t OUTPUTDIRCTRL; /**< SCT output counter direction control register, offset: 0x54 */ 5835 __IO uint32_t RES; /**< SCT conflict resolution register, offset: 0x58 */ 5836 __IO uint32_t DMAREQ0; /**< SCT DMA request 0 register, offset: 0x5C */ 5837 __IO uint32_t DMAREQ1; /**< SCT DMA request 1 register, offset: 0x60 */ 5838 uint8_t RESERVED_1[140]; 5839 __IO uint32_t EVEN; /**< SCT event interrupt enable register, offset: 0xF0 */ 5840 __IO uint32_t EVFLAG; /**< SCT event flag register, offset: 0xF4 */ 5841 __IO uint32_t CONEN; /**< SCT conflict interrupt enable register, offset: 0xF8 */ 5842 __IO uint32_t CONFLAG; /**< SCT conflict flag register, offset: 0xFC */ 5843 union { /* offset: 0x100 */ 5844 union { /* offset: 0x100, array step: 0x4 */ 5845 struct { /* offset: 0x100, array step: 0x4 */ 5846 __IO uint16_t CAPL; /**< SCT_CAPL register, array offset: 0x100, array step: 0x4 */ 5847 __IO uint16_t CAPH; /**< SCT_CAPH register, array offset: 0x102, array step: 0x4 */ 5848 } CAP_ACCESS16BIT[10]; 5849 __IO uint32_t CAP[10]; /**< SCT capture register of capture channel, array offset: 0x100, array step: 0x4 */ 5850 }; 5851 union { /* offset: 0x100, array step: 0x4 */ 5852 struct { /* offset: 0x100, array step: 0x4 */ 5853 __IO uint16_t MATCHL; /**< SCT_MATCHL register, array offset: 0x100, array step: 0x4 */ 5854 __IO uint16_t MATCHH; /**< SCT_MATCHH register, array offset: 0x102, array step: 0x4 */ 5855 } MATCH_ACCESS16BIT[10]; 5856 __IO uint32_t MATCH[10]; /**< SCT match value register of match channels, array offset: 0x100, array step: 0x4 */ 5857 }; 5858 }; 5859 uint8_t RESERVED_2[216]; 5860 union { /* offset: 0x200 */ 5861 union { /* offset: 0x200, array step: 0x4 */ 5862 struct { /* offset: 0x200, array step: 0x4 */ 5863 __IO uint16_t CAPCTRLL; /**< SCT_CAPCTRLL register, array offset: 0x200, array step: 0x4 */ 5864 __IO uint16_t CAPCTRLH; /**< SCT_CAPCTRLH register, array offset: 0x202, array step: 0x4 */ 5865 } CAPCTRL_ACCESS16BIT[10]; 5866 __IO uint32_t CAPCTRL[10]; /**< SCT capture control register, array offset: 0x200, array step: 0x4 */ 5867 }; 5868 union { /* offset: 0x200, array step: 0x4 */ 5869 struct { /* offset: 0x200, array step: 0x4 */ 5870 __IO uint16_t MATCHRELL; /**< SCT_MATCHRELL register, array offset: 0x200, array step: 0x4 */ 5871 __IO uint16_t MATCHRELH; /**< SCT_MATCHRELH register, array offset: 0x202, array step: 0x4 */ 5872 } MATCHREL_ACCESS16BIT[10]; 5873 __IO uint32_t MATCHREL[10]; /**< SCT match reload value register, array offset: 0x200, array step: 0x4 */ 5874 }; 5875 }; 5876 uint8_t RESERVED_3[216]; 5877 struct { /* offset: 0x300, array step: 0x8 */ 5878 __IO uint32_t STATE; /**< SCT event state register 0, array offset: 0x300, array step: 0x8 */ 5879 __IO uint32_t CTRL; /**< SCT event control register 0, array offset: 0x304, array step: 0x8 */ 5880 } EV[10]; 5881 uint8_t RESERVED_4[432]; 5882 struct { /* offset: 0x500, array step: 0x8 */ 5883 __IO uint32_t SET; /**< SCT output 0 set register, array offset: 0x500, array step: 0x8 */ 5884 __IO uint32_t CLR; /**< SCT output 0 clear register, array offset: 0x504, array step: 0x8 */ 5885 } OUT[8]; 5886 } SCT_Type; 5887 5888 /* ---------------------------------------------------------------------------- 5889 -- SCT Register Masks 5890 ---------------------------------------------------------------------------- */ 5891 5892 /*! 5893 * @addtogroup SCT_Register_Masks SCT Register Masks 5894 * @{ 5895 */ 5896 5897 /*! @name CONFIG - SCT configuration register */ 5898 /*! @{ */ 5899 #define SCT_CONFIG_UNIFY_MASK (0x1U) 5900 #define SCT_CONFIG_UNIFY_SHIFT (0U) 5901 /*! UNIFY - SCT operation 5902 * 0b0..The SCT operates as two 16-bit counters named COUNTER_L and COUNTER_H. 5903 * 0b1..The SCT operates as a unified 32-bit counter. 5904 */ 5905 #define SCT_CONFIG_UNIFY(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_UNIFY_SHIFT)) & SCT_CONFIG_UNIFY_MASK) 5906 #define SCT_CONFIG_CLKMODE_MASK (0x6U) 5907 #define SCT_CONFIG_CLKMODE_SHIFT (1U) 5908 /*! CLKMODE - SCT clock mode 5909 * 0b00..System Clock Mode. The system clock clocks the entire SCT module including the counter(s) and counter prescalers. 5910 * 0b01..Sampled System Clock Mode. The system clock clocks the SCT module, but the counter and prescalers are 5911 * only enabled to count when the designated edge is detected on the input selected by the CKSEL field. The 5912 * minimum pulse width on the selected clock-gate input is 1 bus clock period. This mode is the 5913 * high-performance, sampled-clock mode. 5914 * 0b10..SCT Input Clock Mode. The input/edge selected by the CKSEL field clocks the SCT module, including the 5915 * counters and prescalers, after first being synchronized to the system clock. The minimum pulse width on the 5916 * clock input is 1 bus clock period. This mode is the low-power, sampled-clock mode. 5917 * 0b11..Asynchronous Mode. The entire SCT module is clocked directly by the input/edge selected by the CKSEL 5918 * field. In this mode, the SCT outputs are switched synchronously to the SCT input clock - not the system 5919 * clock. The input clock rate must be at least half the system clock rate and can be the same or faster than 5920 * the system clock. 5921 */ 5922 #define SCT_CONFIG_CLKMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CLKMODE_SHIFT)) & SCT_CONFIG_CLKMODE_MASK) 5923 #define SCT_CONFIG_CKSEL_MASK (0x78U) 5924 #define SCT_CONFIG_CKSEL_SHIFT (3U) 5925 /*! CKSEL - SCT clock select. The specific functionality of the designated input/edge is dependent 5926 * on the CLKMODE bit selection in this register. 5927 * 0b0000..Rising edges on input 0. 5928 * 0b0001..Falling edges on input 0. 5929 * 0b0010..Rising edges on input 1. 5930 * 0b0011..Falling edges on input 1. 5931 * 0b0100..Rising edges on input 2. 5932 * 0b0101..Falling edges on input 2. 5933 * 0b0110..Rising edges on input 3. 5934 * 0b0111..Falling edges on input 3. 5935 * 0b1000..Rising edges on input 4. 5936 * 0b1001..Falling edges on input 4. 5937 * 0b1010..Rising edges on input 5. 5938 * 0b1011..Falling edges on input 5. 5939 * 0b1100..Rising edges on input 6. 5940 * 0b1101..Falling edges on input 6. 5941 * 0b1110..Rising edges on input 7. 5942 * 0b1111..Falling edges on input 7. 5943 */ 5944 #define SCT_CONFIG_CKSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CKSEL_SHIFT)) & SCT_CONFIG_CKSEL_MASK) 5945 #define SCT_CONFIG_NORELOAD_L_MASK (0x80U) 5946 #define SCT_CONFIG_NORELOAD_L_SHIFT (7U) 5947 /*! NORELOAD_L - A 1 in this bit prevents the lower match registers from being reloaded from their 5948 * respective reload registers. Setting this bit eliminates the need to write to the reload 5949 * registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at any 5950 * time. This bit applies to both the higher and lower registers when the UNIFY bit is set. 5951 */ 5952 #define SCT_CONFIG_NORELOAD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_L_SHIFT)) & SCT_CONFIG_NORELOAD_L_MASK) 5953 #define SCT_CONFIG_NORELOAD_H_MASK (0x100U) 5954 #define SCT_CONFIG_NORELOAD_H_SHIFT (8U) 5955 /*! NORELOAD_H - A 1 in this bit prevents the higher match registers from being reloaded from their 5956 * respective reload registers. Setting this bit eliminates the need to write to the reload 5957 * registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at 5958 * any time. This bit is not used when the UNIFY bit is set. 5959 */ 5960 #define SCT_CONFIG_NORELOAD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_H_SHIFT)) & SCT_CONFIG_NORELOAD_H_MASK) 5961 #define SCT_CONFIG_INSYNC_MASK (0x1E00U) 5962 #define SCT_CONFIG_INSYNC_SHIFT (9U) 5963 /*! INSYNC - Synchronization for input N (bit 9 = input 0, bit 10 = input 1,, bit 12 = input 3); all 5964 * other bits are reserved. A 1 in one of these bits subjects the corresponding input to 5965 * synchronization to the SCT clock, before it is used to create an event. If an input is known to 5966 * already be synchronous to the SCT clock, this bit may be set to 0 for faster input response. (Note: 5967 * The SCT clock is the system clock for CKMODEs 0-2. It is the selected, asynchronous SCT input 5968 * clock for CKMODE3). Note that the INSYNC field only affects inputs used for event generation. 5969 * It does not apply to the clock input specified in the CKSEL field. 5970 */ 5971 #define SCT_CONFIG_INSYNC(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_INSYNC_SHIFT)) & SCT_CONFIG_INSYNC_MASK) 5972 #define SCT_CONFIG_AUTOLIMIT_L_MASK (0x20000U) 5973 #define SCT_CONFIG_AUTOLIMIT_L_SHIFT (17U) 5974 /*! AUTOLIMIT_L - A one in this bit causes a match on match register 0 to be treated as a de-facto 5975 * LIMIT condition without the need to define an associated event. As with any LIMIT event, this 5976 * automatic limit causes the counter to be cleared to zero in unidirectional mode or to change 5977 * the direction of count in bi-directional mode. Software can write to set or clear this bit at 5978 * any time. This bit applies to both the higher and lower registers when the UNIFY bit is set. 5979 */ 5980 #define SCT_CONFIG_AUTOLIMIT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_L_SHIFT)) & SCT_CONFIG_AUTOLIMIT_L_MASK) 5981 #define SCT_CONFIG_AUTOLIMIT_H_MASK (0x40000U) 5982 #define SCT_CONFIG_AUTOLIMIT_H_SHIFT (18U) 5983 /*! AUTOLIMIT_H - A one in this bit will cause a match on match register 0 to be treated as a 5984 * de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, 5985 * this automatic limit causes the counter to be cleared to zero in unidirectional mode or to 5986 * change the direction of count in bi-directional mode. Software can write to set or clear this bit 5987 * at any time. This bit is not used when the UNIFY bit is set. 5988 */ 5989 #define SCT_CONFIG_AUTOLIMIT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_H_SHIFT)) & SCT_CONFIG_AUTOLIMIT_H_MASK) 5990 /*! @} */ 5991 5992 /*! @name CTRLL - SCT_CTRLL register */ 5993 /*! @{ */ 5994 #define SCT_CTRLL_DOWN_L_MASK (0x1U) 5995 #define SCT_CTRLL_DOWN_L_SHIFT (0U) 5996 /*! DOWN_L - This bit is 1 when the L or unified counter is counting down. Hardware sets this bit 5997 * when the counter is counting up, counter limit occurs, and BIDIR = 1.Hardware clears this bit 5998 * when the counter is counting down and a limit condition occurs or when the counter reaches 0. 5999 */ 6000 #define SCT_CTRLL_DOWN_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_DOWN_L_SHIFT)) & SCT_CTRLL_DOWN_L_MASK) 6001 #define SCT_CTRLL_STOP_L_MASK (0x2U) 6002 #define SCT_CTRLL_STOP_L_SHIFT (1U) 6003 /*! STOP_L - When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events 6004 * related to the counter can occur. If a designated start event occurs, this bit is cleared and 6005 * counting resumes. 6006 */ 6007 #define SCT_CTRLL_STOP_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_STOP_L_SHIFT)) & SCT_CTRLL_STOP_L_MASK) 6008 #define SCT_CTRLL_HALT_L_MASK (0x4U) 6009 #define SCT_CTRLL_HALT_L_SHIFT (2U) 6010 /*! HALT_L - When this bit is 1, the L or unified counter does not run and no events can occur. A 6011 * reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. It is possible to 6012 * remove the halt condition while keeping the SCT in the stop condition (not running) with a 6013 * single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set, 6014 * only software can clear this bit to restore counter operation. This bit is set on reset. 6015 */ 6016 #define SCT_CTRLL_HALT_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_HALT_L_SHIFT)) & SCT_CTRLL_HALT_L_MASK) 6017 #define SCT_CTRLL_CLRCTR_L_MASK (0x8U) 6018 #define SCT_CTRLL_CLRCTR_L_SHIFT (3U) 6019 /*! CLRCTR_L - Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0. 6020 */ 6021 #define SCT_CTRLL_CLRCTR_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_CLRCTR_L_SHIFT)) & SCT_CTRLL_CLRCTR_L_MASK) 6022 #define SCT_CTRLL_BIDIR_L_MASK (0x10U) 6023 #define SCT_CTRLL_BIDIR_L_SHIFT (4U) 6024 /*! BIDIR_L - L or unified counter direction select 6025 * 0b0..Up. The counter counts up to a limit condition, then is cleared to zero. 6026 * 0b1..Up-down. The counter counts up to a limit, then counts down to a limit condition or to 0. 6027 */ 6028 #define SCT_CTRLL_BIDIR_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_BIDIR_L_SHIFT)) & SCT_CTRLL_BIDIR_L_MASK) 6029 #define SCT_CTRLL_PRE_L_MASK (0x1FE0U) 6030 #define SCT_CTRLL_PRE_L_SHIFT (5U) 6031 /*! PRE_L - Specifies the factor by which the SCT clock is prescaled to produce the L or unified 6032 * counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1. 6033 * Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. 6034 */ 6035 #define SCT_CTRLL_PRE_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_PRE_L_SHIFT)) & SCT_CTRLL_PRE_L_MASK) 6036 /*! @} */ 6037 6038 /*! @name CTRLH - SCT_CTRLH register */ 6039 /*! @{ */ 6040 #define SCT_CTRLH_DOWN_H_MASK (0x1U) 6041 #define SCT_CTRLH_DOWN_H_SHIFT (0U) 6042 /*! DOWN_H - This bit is 1 when the H counter is counting down. Hardware sets this bit when the 6043 * counter is counting, a counter limit condition occurs, and BIDIR is 1. Hardware clears this bit 6044 * when the counter is counting down and a limit condition occurs or when the counter reaches 0. 6045 */ 6046 #define SCT_CTRLH_DOWN_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_DOWN_H_SHIFT)) & SCT_CTRLH_DOWN_H_MASK) 6047 #define SCT_CTRLH_STOP_H_MASK (0x2U) 6048 #define SCT_CTRLH_STOP_H_SHIFT (1U) 6049 /*! STOP_H - When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related to 6050 * the counter can occur. If such an event matches the mask in the Start register, this bit is 6051 * cleared and counting resumes. 6052 */ 6053 #define SCT_CTRLH_STOP_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_STOP_H_SHIFT)) & SCT_CTRLH_STOP_H_MASK) 6054 #define SCT_CTRLH_HALT_H_MASK (0x4U) 6055 #define SCT_CTRLH_HALT_H_SHIFT (2U) 6056 /*! HALT_H - When this bit is 1, the H counter does not run and no events can occur. A reset sets 6057 * this bit. When the HALT_H bit is one, the STOP_H bit is cleared. It is possible to remove the 6058 * halt condition while keeping the SCT in the stop condition (not running) with a single write to 6059 * this register to simultaneously clear the HALT bit and set the STOP bit. Once set, this bit 6060 * can only be cleared by software to restore counter operation. This bit is set on reset. 6061 */ 6062 #define SCT_CTRLH_HALT_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_HALT_H_SHIFT)) & SCT_CTRLH_HALT_H_MASK) 6063 #define SCT_CTRLH_CLRCTR_H_MASK (0x8U) 6064 #define SCT_CTRLH_CLRCTR_H_SHIFT (3U) 6065 /*! CLRCTR_H - Writing a 1 to this bit clears the H counter. This bit always reads as 0. 6066 */ 6067 #define SCT_CTRLH_CLRCTR_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_CLRCTR_H_SHIFT)) & SCT_CTRLH_CLRCTR_H_MASK) 6068 #define SCT_CTRLH_BIDIR_H_MASK (0x10U) 6069 #define SCT_CTRLH_BIDIR_H_SHIFT (4U) 6070 /*! BIDIR_H - Direction select 6071 * 0b0..The H counter counts up to its limit condition, then is cleared to zero. 6072 * 0b1..The H counter counts up to its limit, then counts down to a limit condition or to 0. 6073 */ 6074 #define SCT_CTRLH_BIDIR_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_BIDIR_H_SHIFT)) & SCT_CTRLH_BIDIR_H_MASK) 6075 #define SCT_CTRLH_PRE_H_MASK (0x1FE0U) 6076 #define SCT_CTRLH_PRE_H_SHIFT (5U) 6077 /*! PRE_H - Specifies the factor by which the SCT clock is prescaled to produce the H counter clock. 6078 * The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the 6079 * counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. 6080 */ 6081 #define SCT_CTRLH_PRE_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_PRE_H_SHIFT)) & SCT_CTRLH_PRE_H_MASK) 6082 /*! @} */ 6083 6084 /*! @name CTRL - SCT control register */ 6085 /*! @{ */ 6086 #define SCT_CTRL_DOWN_L_MASK (0x1U) 6087 #define SCT_CTRL_DOWN_L_SHIFT (0U) 6088 /*! DOWN_L - This bit is 1 when the L or unified counter is counting down. Hardware sets this bit 6089 * when the counter is counting up, counter limit occurs, and BIDIR = 1.Hardware clears this bit 6090 * when the counter is counting down and a limit condition occurs or when the counter reaches 0. 6091 */ 6092 #define SCT_CTRL_DOWN_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_L_SHIFT)) & SCT_CTRL_DOWN_L_MASK) 6093 #define SCT_CTRL_STOP_L_MASK (0x2U) 6094 #define SCT_CTRL_STOP_L_SHIFT (1U) 6095 /*! STOP_L - When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events 6096 * related to the counter can occur. If a designated start event occurs, this bit is cleared and 6097 * counting resumes. 6098 */ 6099 #define SCT_CTRL_STOP_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_L_SHIFT)) & SCT_CTRL_STOP_L_MASK) 6100 #define SCT_CTRL_HALT_L_MASK (0x4U) 6101 #define SCT_CTRL_HALT_L_SHIFT (2U) 6102 /*! HALT_L - When this bit is 1, the L or unified counter does not run and no events can occur. A 6103 * reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. It is possible to 6104 * remove the halt condition while keeping the SCT in the stop condition (not running) with a 6105 * single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set, 6106 * only software can clear this bit to restore counter operation. This bit is set on reset. 6107 */ 6108 #define SCT_CTRL_HALT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_L_SHIFT)) & SCT_CTRL_HALT_L_MASK) 6109 #define SCT_CTRL_CLRCTR_L_MASK (0x8U) 6110 #define SCT_CTRL_CLRCTR_L_SHIFT (3U) 6111 /*! CLRCTR_L - Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0. 6112 */ 6113 #define SCT_CTRL_CLRCTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_L_SHIFT)) & SCT_CTRL_CLRCTR_L_MASK) 6114 #define SCT_CTRL_BIDIR_L_MASK (0x10U) 6115 #define SCT_CTRL_BIDIR_L_SHIFT (4U) 6116 /*! BIDIR_L - L or unified counter direction select 6117 * 0b0..Up. The counter counts up to a limit condition, then is cleared to zero. 6118 * 0b1..Up-down. The counter counts up to a limit, then counts down to a limit condition or to 0. 6119 */ 6120 #define SCT_CTRL_BIDIR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_L_SHIFT)) & SCT_CTRL_BIDIR_L_MASK) 6121 #define SCT_CTRL_PRE_L_MASK (0x1FE0U) 6122 #define SCT_CTRL_PRE_L_SHIFT (5U) 6123 /*! PRE_L - Specifies the factor by which the SCT clock is prescaled to produce the L or unified 6124 * counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1. 6125 * Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. 6126 */ 6127 #define SCT_CTRL_PRE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_L_SHIFT)) & SCT_CTRL_PRE_L_MASK) 6128 #define SCT_CTRL_DOWN_H_MASK (0x10000U) 6129 #define SCT_CTRL_DOWN_H_SHIFT (16U) 6130 /*! DOWN_H - This bit is 1 when the H counter is counting down. Hardware sets this bit when the 6131 * counter is counting, a counter limit condition occurs, and BIDIR is 1. Hardware clears this bit 6132 * when the counter is counting down and a limit condition occurs or when the counter reaches 0. 6133 */ 6134 #define SCT_CTRL_DOWN_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_H_SHIFT)) & SCT_CTRL_DOWN_H_MASK) 6135 #define SCT_CTRL_STOP_H_MASK (0x20000U) 6136 #define SCT_CTRL_STOP_H_SHIFT (17U) 6137 /*! STOP_H - When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related to 6138 * the counter can occur. If such an event matches the mask in the Start register, this bit is 6139 * cleared and counting resumes. 6140 */ 6141 #define SCT_CTRL_STOP_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_H_SHIFT)) & SCT_CTRL_STOP_H_MASK) 6142 #define SCT_CTRL_HALT_H_MASK (0x40000U) 6143 #define SCT_CTRL_HALT_H_SHIFT (18U) 6144 /*! HALT_H - When this bit is 1, the H counter does not run and no events can occur. A reset sets 6145 * this bit. When the HALT_H bit is one, the STOP_H bit is cleared. It is possible to remove the 6146 * halt condition while keeping the SCT in the stop condition (not running) with a single write to 6147 * this register to simultaneously clear the HALT bit and set the STOP bit. Once set, this bit 6148 * can only be cleared by software to restore counter operation. This bit is set on reset. 6149 */ 6150 #define SCT_CTRL_HALT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_H_SHIFT)) & SCT_CTRL_HALT_H_MASK) 6151 #define SCT_CTRL_CLRCTR_H_MASK (0x80000U) 6152 #define SCT_CTRL_CLRCTR_H_SHIFT (19U) 6153 /*! CLRCTR_H - Writing a 1 to this bit clears the H counter. This bit always reads as 0. 6154 */ 6155 #define SCT_CTRL_CLRCTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_H_SHIFT)) & SCT_CTRL_CLRCTR_H_MASK) 6156 #define SCT_CTRL_BIDIR_H_MASK (0x100000U) 6157 #define SCT_CTRL_BIDIR_H_SHIFT (20U) 6158 /*! BIDIR_H - Direction select 6159 * 0b0..The H counter counts up to its limit condition, then is cleared to zero. 6160 * 0b1..The H counter counts up to its limit, then counts down to a limit condition or to 0. 6161 */ 6162 #define SCT_CTRL_BIDIR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_H_SHIFT)) & SCT_CTRL_BIDIR_H_MASK) 6163 #define SCT_CTRL_PRE_H_MASK (0x1FE00000U) 6164 #define SCT_CTRL_PRE_H_SHIFT (21U) 6165 /*! PRE_H - Specifies the factor by which the SCT clock is prescaled to produce the H counter clock. 6166 * The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the 6167 * counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. 6168 */ 6169 #define SCT_CTRL_PRE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_H_SHIFT)) & SCT_CTRL_PRE_H_MASK) 6170 /*! @} */ 6171 6172 /*! @name LIMITL - SCT_LIMITL register */ 6173 /*! @{ */ 6174 #define SCT_LIMITL_LIMITL_MASK (0xFFFFU) 6175 #define SCT_LIMITL_LIMITL_SHIFT (0U) 6176 #define SCT_LIMITL_LIMITL(x) (((uint16_t)(((uint16_t)(x)) << SCT_LIMITL_LIMITL_SHIFT)) & SCT_LIMITL_LIMITL_MASK) 6177 /*! @} */ 6178 6179 /*! @name LIMITH - SCT_LIMITH register */ 6180 /*! @{ */ 6181 #define SCT_LIMITH_LIMITH_MASK (0xFFFFU) 6182 #define SCT_LIMITH_LIMITH_SHIFT (0U) 6183 #define SCT_LIMITH_LIMITH(x) (((uint16_t)(((uint16_t)(x)) << SCT_LIMITH_LIMITH_SHIFT)) & SCT_LIMITH_LIMITH_MASK) 6184 /*! @} */ 6185 6186 /*! @name LIMIT - SCT limit event select register */ 6187 /*! @{ */ 6188 #define SCT_LIMIT_LIMMSK_L_MASK (0xFFFFU) 6189 #define SCT_LIMIT_LIMMSK_L_SHIFT (0U) 6190 /*! LIMMSK_L - If bit n is one, event n is used as a counter limit for the L or unified counter 6191 * (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. 6192 */ 6193 #define SCT_LIMIT_LIMMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_L_SHIFT)) & SCT_LIMIT_LIMMSK_L_MASK) 6194 #define SCT_LIMIT_LIMMSK_H_MASK (0xFFFF0000U) 6195 #define SCT_LIMIT_LIMMSK_H_SHIFT (16U) 6196 /*! LIMMSK_H - If bit n is one, event n is used as a counter limit for the H counter (event 0 = bit 6197 * 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT. 6198 */ 6199 #define SCT_LIMIT_LIMMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_H_SHIFT)) & SCT_LIMIT_LIMMSK_H_MASK) 6200 /*! @} */ 6201 6202 /*! @name HALTL - SCT_HALTL register */ 6203 /*! @{ */ 6204 #define SCT_HALTL_HALTL_MASK (0xFFFFU) 6205 #define SCT_HALTL_HALTL_SHIFT (0U) 6206 #define SCT_HALTL_HALTL(x) (((uint16_t)(((uint16_t)(x)) << SCT_HALTL_HALTL_SHIFT)) & SCT_HALTL_HALTL_MASK) 6207 /*! @} */ 6208 6209 /*! @name HALTH - SCT_HALTH register */ 6210 /*! @{ */ 6211 #define SCT_HALTH_HALTH_MASK (0xFFFFU) 6212 #define SCT_HALTH_HALTH_SHIFT (0U) 6213 #define SCT_HALTH_HALTH(x) (((uint16_t)(((uint16_t)(x)) << SCT_HALTH_HALTH_SHIFT)) & SCT_HALTH_HALTH_MASK) 6214 /*! @} */ 6215 6216 /*! @name HALT - SCT halt event select register */ 6217 /*! @{ */ 6218 #define SCT_HALT_HALTMSK_L_MASK (0xFFFFU) 6219 #define SCT_HALT_HALTMSK_L_SHIFT (0U) 6220 /*! HALTMSK_L - If bit n is one, event n sets the HALT_L bit in the CTRL register (event 0 = bit 0, 6221 * event 1 = bit 1, etc.). The number of bits = number of events in this SCT. 6222 */ 6223 #define SCT_HALT_HALTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_L_SHIFT)) & SCT_HALT_HALTMSK_L_MASK) 6224 #define SCT_HALT_HALTMSK_H_MASK (0xFFFF0000U) 6225 #define SCT_HALT_HALTMSK_H_SHIFT (16U) 6226 /*! HALTMSK_H - If bit n is one, event n sets the HALT_H bit in the CTRL register (event 0 = bit 16, 6227 * event 1 = bit 17, etc.). The number of bits = number of events in this SCT. 6228 */ 6229 #define SCT_HALT_HALTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_H_SHIFT)) & SCT_HALT_HALTMSK_H_MASK) 6230 /*! @} */ 6231 6232 /*! @name STOPL - SCT_STOPL register */ 6233 /*! @{ */ 6234 #define SCT_STOPL_STOPL_MASK (0xFFFFU) 6235 #define SCT_STOPL_STOPL_SHIFT (0U) 6236 #define SCT_STOPL_STOPL(x) (((uint16_t)(((uint16_t)(x)) << SCT_STOPL_STOPL_SHIFT)) & SCT_STOPL_STOPL_MASK) 6237 /*! @} */ 6238 6239 /*! @name STOPH - SCT_STOPH register */ 6240 /*! @{ */ 6241 #define SCT_STOPH_STOPH_MASK (0xFFFFU) 6242 #define SCT_STOPH_STOPH_SHIFT (0U) 6243 #define SCT_STOPH_STOPH(x) (((uint16_t)(((uint16_t)(x)) << SCT_STOPH_STOPH_SHIFT)) & SCT_STOPH_STOPH_MASK) 6244 /*! @} */ 6245 6246 /*! @name STOP - SCT stop event select register */ 6247 /*! @{ */ 6248 #define SCT_STOP_STOPMSK_L_MASK (0xFFFFU) 6249 #define SCT_STOP_STOPMSK_L_SHIFT (0U) 6250 /*! STOPMSK_L - If bit n is one, event n sets the STOP_L bit in the CTRL register (event 0 = bit 0, 6251 * event 1 = bit 1, etc.). The number of bits = number of events in this SCT. 6252 */ 6253 #define SCT_STOP_STOPMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_L_SHIFT)) & SCT_STOP_STOPMSK_L_MASK) 6254 #define SCT_STOP_STOPMSK_H_MASK (0xFFFF0000U) 6255 #define SCT_STOP_STOPMSK_H_SHIFT (16U) 6256 /*! STOPMSK_H - If bit n is one, event n sets the STOP_H bit in the CTRL register (event 0 = bit 16, 6257 * event 1 = bit 17, etc.). The number of bits = number of events in this SCT. 6258 */ 6259 #define SCT_STOP_STOPMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_H_SHIFT)) & SCT_STOP_STOPMSK_H_MASK) 6260 /*! @} */ 6261 6262 /*! @name STARTL - SCT_STARTL register */ 6263 /*! @{ */ 6264 #define SCT_STARTL_STARTL_MASK (0xFFFFU) 6265 #define SCT_STARTL_STARTL_SHIFT (0U) 6266 #define SCT_STARTL_STARTL(x) (((uint16_t)(((uint16_t)(x)) << SCT_STARTL_STARTL_SHIFT)) & SCT_STARTL_STARTL_MASK) 6267 /*! @} */ 6268 6269 /*! @name STARTH - SCT_STARTH register */ 6270 /*! @{ */ 6271 #define SCT_STARTH_STARTH_MASK (0xFFFFU) 6272 #define SCT_STARTH_STARTH_SHIFT (0U) 6273 #define SCT_STARTH_STARTH(x) (((uint16_t)(((uint16_t)(x)) << SCT_STARTH_STARTH_SHIFT)) & SCT_STARTH_STARTH_MASK) 6274 /*! @} */ 6275 6276 /*! @name START - SCT start event select register */ 6277 /*! @{ */ 6278 #define SCT_START_STARTMSK_L_MASK (0xFFFFU) 6279 #define SCT_START_STARTMSK_L_SHIFT (0U) 6280 /*! STARTMSK_L - If bit n is one, event n clears the STOP_L bit in the CTRL register (event 0 = bit 6281 * 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. 6282 */ 6283 #define SCT_START_STARTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_L_SHIFT)) & SCT_START_STARTMSK_L_MASK) 6284 #define SCT_START_STARTMSK_H_MASK (0xFFFF0000U) 6285 #define SCT_START_STARTMSK_H_SHIFT (16U) 6286 /*! STARTMSK_H - If bit n is one, event n clears the STOP_H bit in the CTRL register (event 0 = bit 6287 * 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT. 6288 */ 6289 #define SCT_START_STARTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_H_SHIFT)) & SCT_START_STARTMSK_H_MASK) 6290 /*! @} */ 6291 6292 /*! @name COUNTL - SCT_COUNTL register */ 6293 /*! @{ */ 6294 #define SCT_COUNTL_COUNTL_MASK (0xFFFFU) 6295 #define SCT_COUNTL_COUNTL_SHIFT (0U) 6296 #define SCT_COUNTL_COUNTL(x) (((uint16_t)(((uint16_t)(x)) << SCT_COUNTL_COUNTL_SHIFT)) & SCT_COUNTL_COUNTL_MASK) 6297 /*! @} */ 6298 6299 /*! @name COUNTH - SCT_COUNTH register */ 6300 /*! @{ */ 6301 #define SCT_COUNTH_COUNTH_MASK (0xFFFFU) 6302 #define SCT_COUNTH_COUNTH_SHIFT (0U) 6303 #define SCT_COUNTH_COUNTH(x) (((uint16_t)(((uint16_t)(x)) << SCT_COUNTH_COUNTH_SHIFT)) & SCT_COUNTH_COUNTH_MASK) 6304 /*! @} */ 6305 6306 /*! @name COUNT - SCT counter register */ 6307 /*! @{ */ 6308 #define SCT_COUNT_CTR_L_MASK (0xFFFFU) 6309 #define SCT_COUNT_CTR_L_SHIFT (0U) 6310 /*! CTR_L - When UNIFY = 0, read or write the 16-bit L counter value. When UNIFY = 1, read or write 6311 * the lower 16 bits of the 32-bit unified counter. 6312 */ 6313 #define SCT_COUNT_CTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_L_SHIFT)) & SCT_COUNT_CTR_L_MASK) 6314 #define SCT_COUNT_CTR_H_MASK (0xFFFF0000U) 6315 #define SCT_COUNT_CTR_H_SHIFT (16U) 6316 /*! CTR_H - When UNIFY = 0, read or write the 16-bit H counter value. When UNIFY = 1, read or write 6317 * the upper 16 bits of the 32-bit unified counter. 6318 */ 6319 #define SCT_COUNT_CTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_H_SHIFT)) & SCT_COUNT_CTR_H_MASK) 6320 /*! @} */ 6321 6322 /*! @name STATEL - SCT_STATEL register */ 6323 /*! @{ */ 6324 #define SCT_STATEL_STATEL_MASK (0xFFFFU) 6325 #define SCT_STATEL_STATEL_SHIFT (0U) 6326 #define SCT_STATEL_STATEL(x) (((uint16_t)(((uint16_t)(x)) << SCT_STATEL_STATEL_SHIFT)) & SCT_STATEL_STATEL_MASK) 6327 /*! @} */ 6328 6329 /*! @name STATEH - SCT_STATEH register */ 6330 /*! @{ */ 6331 #define SCT_STATEH_STATEH_MASK (0xFFFFU) 6332 #define SCT_STATEH_STATEH_SHIFT (0U) 6333 #define SCT_STATEH_STATEH(x) (((uint16_t)(((uint16_t)(x)) << SCT_STATEH_STATEH_SHIFT)) & SCT_STATEH_STATEH_MASK) 6334 /*! @} */ 6335 6336 /*! @name STATE - SCT state register */ 6337 /*! @{ */ 6338 #define SCT_STATE_STATE_L_MASK (0x1FU) 6339 #define SCT_STATE_STATE_L_SHIFT (0U) 6340 /*! STATE_L - State variable. 6341 */ 6342 #define SCT_STATE_STATE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_L_SHIFT)) & SCT_STATE_STATE_L_MASK) 6343 #define SCT_STATE_STATE_H_MASK (0x1F0000U) 6344 #define SCT_STATE_STATE_H_SHIFT (16U) 6345 /*! STATE_H - State variable. 6346 */ 6347 #define SCT_STATE_STATE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_H_SHIFT)) & SCT_STATE_STATE_H_MASK) 6348 /*! @} */ 6349 6350 /*! @name INPUT - SCT input register */ 6351 /*! @{ */ 6352 #define SCT_INPUT_AIN0_MASK (0x1U) 6353 #define SCT_INPUT_AIN0_SHIFT (0U) 6354 /*! AIN0 - Input 0 state. Input 0 state on the last SCT clock edge. 6355 */ 6356 #define SCT_INPUT_AIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN0_SHIFT)) & SCT_INPUT_AIN0_MASK) 6357 #define SCT_INPUT_AIN1_MASK (0x2U) 6358 #define SCT_INPUT_AIN1_SHIFT (1U) 6359 /*! AIN1 - Input 1 state. Input 1 state on the last SCT clock edge. 6360 */ 6361 #define SCT_INPUT_AIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN1_SHIFT)) & SCT_INPUT_AIN1_MASK) 6362 #define SCT_INPUT_AIN2_MASK (0x4U) 6363 #define SCT_INPUT_AIN2_SHIFT (2U) 6364 /*! AIN2 - Input 2 state. Input 2 state on the last SCT clock edge. 6365 */ 6366 #define SCT_INPUT_AIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN2_SHIFT)) & SCT_INPUT_AIN2_MASK) 6367 #define SCT_INPUT_AIN3_MASK (0x8U) 6368 #define SCT_INPUT_AIN3_SHIFT (3U) 6369 /*! AIN3 - Input 3 state. Input 3 state on the last SCT clock edge. 6370 */ 6371 #define SCT_INPUT_AIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN3_SHIFT)) & SCT_INPUT_AIN3_MASK) 6372 #define SCT_INPUT_AIN4_MASK (0x10U) 6373 #define SCT_INPUT_AIN4_SHIFT (4U) 6374 /*! AIN4 - Input 4 state. Input 4 state on the last SCT clock edge. 6375 */ 6376 #define SCT_INPUT_AIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN4_SHIFT)) & SCT_INPUT_AIN4_MASK) 6377 #define SCT_INPUT_AIN5_MASK (0x20U) 6378 #define SCT_INPUT_AIN5_SHIFT (5U) 6379 /*! AIN5 - Input 5 state. Input 5 state on the last SCT clock edge. 6380 */ 6381 #define SCT_INPUT_AIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN5_SHIFT)) & SCT_INPUT_AIN5_MASK) 6382 #define SCT_INPUT_AIN6_MASK (0x40U) 6383 #define SCT_INPUT_AIN6_SHIFT (6U) 6384 /*! AIN6 - Input 6 state. Input 6 state on the last SCT clock edge. 6385 */ 6386 #define SCT_INPUT_AIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN6_SHIFT)) & SCT_INPUT_AIN6_MASK) 6387 #define SCT_INPUT_AIN7_MASK (0x80U) 6388 #define SCT_INPUT_AIN7_SHIFT (7U) 6389 /*! AIN7 - Input 7 state. Input 7 state on the last SCT clock edge. 6390 */ 6391 #define SCT_INPUT_AIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN7_SHIFT)) & SCT_INPUT_AIN7_MASK) 6392 #define SCT_INPUT_AIN8_MASK (0x100U) 6393 #define SCT_INPUT_AIN8_SHIFT (8U) 6394 /*! AIN8 - Input 8 state. Input 8 state on the last SCT clock edge. 6395 */ 6396 #define SCT_INPUT_AIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN8_SHIFT)) & SCT_INPUT_AIN8_MASK) 6397 #define SCT_INPUT_AIN9_MASK (0x200U) 6398 #define SCT_INPUT_AIN9_SHIFT (9U) 6399 /*! AIN9 - Input 9 state. Input 9 state on the last SCT clock edge. 6400 */ 6401 #define SCT_INPUT_AIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN9_SHIFT)) & SCT_INPUT_AIN9_MASK) 6402 #define SCT_INPUT_AIN10_MASK (0x400U) 6403 #define SCT_INPUT_AIN10_SHIFT (10U) 6404 /*! AIN10 - Input 10 state. Input 10 state on the last SCT clock edge. 6405 */ 6406 #define SCT_INPUT_AIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN10_SHIFT)) & SCT_INPUT_AIN10_MASK) 6407 #define SCT_INPUT_AIN11_MASK (0x800U) 6408 #define SCT_INPUT_AIN11_SHIFT (11U) 6409 /*! AIN11 - Input 11 state. Input 11 state on the last SCT clock edge. 6410 */ 6411 #define SCT_INPUT_AIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN11_SHIFT)) & SCT_INPUT_AIN11_MASK) 6412 #define SCT_INPUT_AIN12_MASK (0x1000U) 6413 #define SCT_INPUT_AIN12_SHIFT (12U) 6414 /*! AIN12 - Input 12 state. Input 12 state on the last SCT clock edge. 6415 */ 6416 #define SCT_INPUT_AIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN12_SHIFT)) & SCT_INPUT_AIN12_MASK) 6417 #define SCT_INPUT_AIN13_MASK (0x2000U) 6418 #define SCT_INPUT_AIN13_SHIFT (13U) 6419 /*! AIN13 - Input 13 state. Input 13 state on the last SCT clock edge. 6420 */ 6421 #define SCT_INPUT_AIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN13_SHIFT)) & SCT_INPUT_AIN13_MASK) 6422 #define SCT_INPUT_AIN14_MASK (0x4000U) 6423 #define SCT_INPUT_AIN14_SHIFT (14U) 6424 /*! AIN14 - Input 14 state. Input 14 state on the last SCT clock edge. 6425 */ 6426 #define SCT_INPUT_AIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN14_SHIFT)) & SCT_INPUT_AIN14_MASK) 6427 #define SCT_INPUT_AIN15_MASK (0x8000U) 6428 #define SCT_INPUT_AIN15_SHIFT (15U) 6429 /*! AIN15 - Input 15 state. Input 15 state on the last SCT clock edge. 6430 */ 6431 #define SCT_INPUT_AIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN15_SHIFT)) & SCT_INPUT_AIN15_MASK) 6432 #define SCT_INPUT_SIN0_MASK (0x10000U) 6433 #define SCT_INPUT_SIN0_SHIFT (16U) 6434 /*! SIN0 - Input 0 state. Input 0 state following the synchronization specified by INSYNC. 6435 */ 6436 #define SCT_INPUT_SIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN0_SHIFT)) & SCT_INPUT_SIN0_MASK) 6437 #define SCT_INPUT_SIN1_MASK (0x20000U) 6438 #define SCT_INPUT_SIN1_SHIFT (17U) 6439 /*! SIN1 - Input 1 state. Input 1 state following the synchronization specified by INSYNC. 6440 */ 6441 #define SCT_INPUT_SIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN1_SHIFT)) & SCT_INPUT_SIN1_MASK) 6442 #define SCT_INPUT_SIN2_MASK (0x40000U) 6443 #define SCT_INPUT_SIN2_SHIFT (18U) 6444 /*! SIN2 - Input 2 state. Input 2 state following the synchronization specified by INSYNC. 6445 */ 6446 #define SCT_INPUT_SIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN2_SHIFT)) & SCT_INPUT_SIN2_MASK) 6447 #define SCT_INPUT_SIN3_MASK (0x80000U) 6448 #define SCT_INPUT_SIN3_SHIFT (19U) 6449 /*! SIN3 - Input 3 state. Input 3 state following the synchronization specified by INSYNC. 6450 */ 6451 #define SCT_INPUT_SIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN3_SHIFT)) & SCT_INPUT_SIN3_MASK) 6452 #define SCT_INPUT_SIN4_MASK (0x100000U) 6453 #define SCT_INPUT_SIN4_SHIFT (20U) 6454 /*! SIN4 - Input 4 state. Input 4 state following the synchronization specified by INSYNC. 6455 */ 6456 #define SCT_INPUT_SIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN4_SHIFT)) & SCT_INPUT_SIN4_MASK) 6457 #define SCT_INPUT_SIN5_MASK (0x200000U) 6458 #define SCT_INPUT_SIN5_SHIFT (21U) 6459 /*! SIN5 - Input 5 state. Input 5 state following the synchronization specified by INSYNC. 6460 */ 6461 #define SCT_INPUT_SIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN5_SHIFT)) & SCT_INPUT_SIN5_MASK) 6462 #define SCT_INPUT_SIN6_MASK (0x400000U) 6463 #define SCT_INPUT_SIN6_SHIFT (22U) 6464 /*! SIN6 - Input 6 state. Input 6 state following the synchronization specified by INSYNC. 6465 */ 6466 #define SCT_INPUT_SIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN6_SHIFT)) & SCT_INPUT_SIN6_MASK) 6467 #define SCT_INPUT_SIN7_MASK (0x800000U) 6468 #define SCT_INPUT_SIN7_SHIFT (23U) 6469 /*! SIN7 - Input 7 state. Input 7 state following the synchronization specified by INSYNC. 6470 */ 6471 #define SCT_INPUT_SIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN7_SHIFT)) & SCT_INPUT_SIN7_MASK) 6472 #define SCT_INPUT_SIN8_MASK (0x1000000U) 6473 #define SCT_INPUT_SIN8_SHIFT (24U) 6474 /*! SIN8 - Input 8 state. Input 8 state following the synchronization specified by INSYNC. 6475 */ 6476 #define SCT_INPUT_SIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN8_SHIFT)) & SCT_INPUT_SIN8_MASK) 6477 #define SCT_INPUT_SIN9_MASK (0x2000000U) 6478 #define SCT_INPUT_SIN9_SHIFT (25U) 6479 /*! SIN9 - Input 9 state. Input 9 state following the synchronization specified by INSYNC. 6480 */ 6481 #define SCT_INPUT_SIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN9_SHIFT)) & SCT_INPUT_SIN9_MASK) 6482 #define SCT_INPUT_SIN10_MASK (0x4000000U) 6483 #define SCT_INPUT_SIN10_SHIFT (26U) 6484 /*! SIN10 - Input 10 state. Input 10 state following the synchronization specified by INSYNC. 6485 */ 6486 #define SCT_INPUT_SIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN10_SHIFT)) & SCT_INPUT_SIN10_MASK) 6487 #define SCT_INPUT_SIN11_MASK (0x8000000U) 6488 #define SCT_INPUT_SIN11_SHIFT (27U) 6489 /*! SIN11 - Input 11 state. Input 11 state following the synchronization specified by INSYNC. 6490 */ 6491 #define SCT_INPUT_SIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN11_SHIFT)) & SCT_INPUT_SIN11_MASK) 6492 #define SCT_INPUT_SIN12_MASK (0x10000000U) 6493 #define SCT_INPUT_SIN12_SHIFT (28U) 6494 /*! SIN12 - Input 12 state. Input 12 state following the synchronization specified by INSYNC. 6495 */ 6496 #define SCT_INPUT_SIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN12_SHIFT)) & SCT_INPUT_SIN12_MASK) 6497 #define SCT_INPUT_SIN13_MASK (0x20000000U) 6498 #define SCT_INPUT_SIN13_SHIFT (29U) 6499 /*! SIN13 - Input 13 state. Input 13 state following the synchronization specified by INSYNC. 6500 */ 6501 #define SCT_INPUT_SIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN13_SHIFT)) & SCT_INPUT_SIN13_MASK) 6502 #define SCT_INPUT_SIN14_MASK (0x40000000U) 6503 #define SCT_INPUT_SIN14_SHIFT (30U) 6504 /*! SIN14 - Input 14 state. Input 14 state following the synchronization specified by INSYNC. 6505 */ 6506 #define SCT_INPUT_SIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN14_SHIFT)) & SCT_INPUT_SIN14_MASK) 6507 #define SCT_INPUT_SIN15_MASK (0x80000000U) 6508 #define SCT_INPUT_SIN15_SHIFT (31U) 6509 /*! SIN15 - Input 15 state. Input 15 state following the synchronization specified by INSYNC. 6510 */ 6511 #define SCT_INPUT_SIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN15_SHIFT)) & SCT_INPUT_SIN15_MASK) 6512 /*! @} */ 6513 6514 /*! @name REGMODEL - SCT_REGMODEL register */ 6515 /*! @{ */ 6516 #define SCT_REGMODEL_REGMODEL_MASK (0xFFFFU) 6517 #define SCT_REGMODEL_REGMODEL_SHIFT (0U) 6518 #define SCT_REGMODEL_REGMODEL(x) (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEL_REGMODEL_SHIFT)) & SCT_REGMODEL_REGMODEL_MASK) 6519 /*! @} */ 6520 6521 /*! @name REGMODEH - SCT_REGMODEH register */ 6522 /*! @{ */ 6523 #define SCT_REGMODEH_REGMODEH_MASK (0xFFFFU) 6524 #define SCT_REGMODEH_REGMODEH_SHIFT (0U) 6525 #define SCT_REGMODEH_REGMODEH(x) (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEH_REGMODEH_SHIFT)) & SCT_REGMODEH_REGMODEH_MASK) 6526 /*! @} */ 6527 6528 /*! @name REGMODE - SCT match/capture mode register */ 6529 /*! @{ */ 6530 #define SCT_REGMODE_REGMOD_L_MASK (0xFFFFU) 6531 #define SCT_REGMODE_REGMOD_L_SHIFT (0U) 6532 /*! REGMOD_L - Each bit controls one match/capture register (register 0 = bit 0, register 1 = bit 1, 6533 * etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as 6534 * match register. 1 = register operates as capture register. 6535 */ 6536 #define SCT_REGMODE_REGMOD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L_SHIFT)) & SCT_REGMODE_REGMOD_L_MASK) 6537 #define SCT_REGMODE_REGMOD_H_MASK (0xFFFF0000U) 6538 #define SCT_REGMODE_REGMOD_H_SHIFT (16U) 6539 /*! REGMOD_H - Each bit controls one match/capture register (register 0 = bit 16, register 1 = bit 6540 * 17, etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as 6541 * match registers. 1 = register operates as capture registers. 6542 */ 6543 #define SCT_REGMODE_REGMOD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H_SHIFT)) & SCT_REGMODE_REGMOD_H_MASK) 6544 /*! @} */ 6545 6546 /*! @name OUTPUT - SCT output register */ 6547 /*! @{ */ 6548 #define SCT_OUTPUT_OUT_MASK (0xFFFFU) 6549 #define SCT_OUTPUT_OUT_SHIFT (0U) 6550 /*! OUT - Writing a 1 to bit n forces the corresponding output HIGH. Writing a 0 forces the 6551 * corresponding output LOW (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of 6552 * outputs in this SCT. 6553 */ 6554 #define SCT_OUTPUT_OUT(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT_SHIFT)) & SCT_OUTPUT_OUT_MASK) 6555 /*! @} */ 6556 6557 /*! @name OUTPUTDIRCTRL - SCT output counter direction control register */ 6558 /*! @{ */ 6559 #define SCT_OUTPUTDIRCTRL_SETCLR0_MASK (0x3U) 6560 #define SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT (0U) 6561 /*! SETCLR0 - Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value. 6562 * 0b00..Set and clear do not depend on the direction of any counter. 6563 * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. 6564 * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 6565 */ 6566 #define SCT_OUTPUTDIRCTRL_SETCLR0(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR0_MASK) 6567 #define SCT_OUTPUTDIRCTRL_SETCLR1_MASK (0xCU) 6568 #define SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT (2U) 6569 /*! SETCLR1 - Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value. 6570 * 0b00..Set and clear do not depend on the direction of any counter. 6571 * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. 6572 * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 6573 */ 6574 #define SCT_OUTPUTDIRCTRL_SETCLR1(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR1_MASK) 6575 #define SCT_OUTPUTDIRCTRL_SETCLR2_MASK (0x30U) 6576 #define SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT (4U) 6577 /*! SETCLR2 - Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value. 6578 * 0b00..Set and clear do not depend on the direction of any counter. 6579 * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. 6580 * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 6581 */ 6582 #define SCT_OUTPUTDIRCTRL_SETCLR2(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR2_MASK) 6583 #define SCT_OUTPUTDIRCTRL_SETCLR3_MASK (0xC0U) 6584 #define SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT (6U) 6585 /*! SETCLR3 - Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value. 6586 * 0b00..Set and clear do not depend on the direction of any counter. 6587 * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. 6588 * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 6589 */ 6590 #define SCT_OUTPUTDIRCTRL_SETCLR3(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR3_MASK) 6591 #define SCT_OUTPUTDIRCTRL_SETCLR4_MASK (0x300U) 6592 #define SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT (8U) 6593 /*! SETCLR4 - Set/clear operation on output 4. Value 0x3 is reserved. Do not program this value. 6594 * 0b00..Set and clear do not depend on the direction of any counter. 6595 * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. 6596 * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 6597 */ 6598 #define SCT_OUTPUTDIRCTRL_SETCLR4(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR4_MASK) 6599 #define SCT_OUTPUTDIRCTRL_SETCLR5_MASK (0xC00U) 6600 #define SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT (10U) 6601 /*! SETCLR5 - Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value. 6602 * 0b00..Set and clear do not depend on the direction of any counter. 6603 * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. 6604 * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 6605 */ 6606 #define SCT_OUTPUTDIRCTRL_SETCLR5(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR5_MASK) 6607 #define SCT_OUTPUTDIRCTRL_SETCLR6_MASK (0x3000U) 6608 #define SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT (12U) 6609 /*! SETCLR6 - Set/clear operation on output 6. Value 0x3 is reserved. Do not program this value. 6610 * 0b00..Set and clear do not depend on the direction of any counter. 6611 * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. 6612 * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 6613 */ 6614 #define SCT_OUTPUTDIRCTRL_SETCLR6(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR6_MASK) 6615 #define SCT_OUTPUTDIRCTRL_SETCLR7_MASK (0xC000U) 6616 #define SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT (14U) 6617 /*! SETCLR7 - Set/clear operation on output 7. Value 0x3 is reserved. Do not program this value. 6618 * 0b00..Set and clear do not depend on the direction of any counter. 6619 * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. 6620 * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 6621 */ 6622 #define SCT_OUTPUTDIRCTRL_SETCLR7(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR7_MASK) 6623 #define SCT_OUTPUTDIRCTRL_SETCLR8_MASK (0x30000U) 6624 #define SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT (16U) 6625 /*! SETCLR8 - Set/clear operation on output 8. Value 0x3 is reserved. Do not program this value. 6626 * 0b00..Set and clear do not depend on the direction of any counter. 6627 * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. 6628 * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 6629 */ 6630 #define SCT_OUTPUTDIRCTRL_SETCLR8(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR8_MASK) 6631 #define SCT_OUTPUTDIRCTRL_SETCLR9_MASK (0xC0000U) 6632 #define SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT (18U) 6633 /*! SETCLR9 - Set/clear operation on output 9. Value 0x3 is reserved. Do not program this value. 6634 * 0b00..Set and clear do not depend on the direction of any counter. 6635 * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. 6636 * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 6637 */ 6638 #define SCT_OUTPUTDIRCTRL_SETCLR9(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR9_MASK) 6639 #define SCT_OUTPUTDIRCTRL_SETCLR10_MASK (0x300000U) 6640 #define SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT (20U) 6641 /*! SETCLR10 - Set/clear operation on output 10. Value 0x3 is reserved. Do not program this value. 6642 * 0b00..Set and clear do not depend on the direction of any counter. 6643 * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. 6644 * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 6645 */ 6646 #define SCT_OUTPUTDIRCTRL_SETCLR10(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR10_MASK) 6647 #define SCT_OUTPUTDIRCTRL_SETCLR11_MASK (0xC00000U) 6648 #define SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT (22U) 6649 /*! SETCLR11 - Set/clear operation on output 11. Value 0x3 is reserved. Do not program this value. 6650 * 0b00..Set and clear do not depend on the direction of any counter. 6651 * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. 6652 * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 6653 */ 6654 #define SCT_OUTPUTDIRCTRL_SETCLR11(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR11_MASK) 6655 #define SCT_OUTPUTDIRCTRL_SETCLR12_MASK (0x3000000U) 6656 #define SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT (24U) 6657 /*! SETCLR12 - Set/clear operation on output 12. Value 0x3 is reserved. Do not program this value. 6658 * 0b00..Set and clear do not depend on the direction of any counter. 6659 * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. 6660 * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 6661 */ 6662 #define SCT_OUTPUTDIRCTRL_SETCLR12(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR12_MASK) 6663 #define SCT_OUTPUTDIRCTRL_SETCLR13_MASK (0xC000000U) 6664 #define SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT (26U) 6665 /*! SETCLR13 - Set/clear operation on output 13. Value 0x3 is reserved. Do not program this value. 6666 * 0b00..Set and clear do not depend on the direction of any counter. 6667 * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. 6668 * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 6669 */ 6670 #define SCT_OUTPUTDIRCTRL_SETCLR13(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR13_MASK) 6671 #define SCT_OUTPUTDIRCTRL_SETCLR14_MASK (0x30000000U) 6672 #define SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT (28U) 6673 /*! SETCLR14 - Set/clear operation on output 14. Value 0x3 is reserved. Do not program this value. 6674 * 0b00..Set and clear do not depend on the direction of any counter. 6675 * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. 6676 * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 6677 */ 6678 #define SCT_OUTPUTDIRCTRL_SETCLR14(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR14_MASK) 6679 #define SCT_OUTPUTDIRCTRL_SETCLR15_MASK (0xC0000000U) 6680 #define SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT (30U) 6681 /*! SETCLR15 - Set/clear operation on output 15. Value 0x3 is reserved. Do not program this value. 6682 * 0b00..Set and clear do not depend on the direction of any counter. 6683 * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. 6684 * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 6685 */ 6686 #define SCT_OUTPUTDIRCTRL_SETCLR15(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR15_MASK) 6687 /*! @} */ 6688 6689 /*! @name RES - SCT conflict resolution register */ 6690 /*! @{ */ 6691 #define SCT_RES_O0RES_MASK (0x3U) 6692 #define SCT_RES_O0RES_SHIFT (0U) 6693 /*! O0RES - Effect of simultaneous set and clear on output 0. 6694 * 0b00..No change. 6695 * 0b01..Set output (or clear based on the SETCLR0 field in the OUTPUTDIRCTRL register). 6696 * 0b10..Clear output (or set based on the SETCLR0 field). 6697 * 0b11..Toggle output. 6698 */ 6699 #define SCT_RES_O0RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O0RES_SHIFT)) & SCT_RES_O0RES_MASK) 6700 #define SCT_RES_O1RES_MASK (0xCU) 6701 #define SCT_RES_O1RES_SHIFT (2U) 6702 /*! O1RES - Effect of simultaneous set and clear on output 1. 6703 * 0b00..No change. 6704 * 0b01..Set output (or clear based on the SETCLR1 field in the OUTPUTDIRCTRL register). 6705 * 0b10..Clear output (or set based on the SETCLR1 field). 6706 * 0b11..Toggle output. 6707 */ 6708 #define SCT_RES_O1RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O1RES_SHIFT)) & SCT_RES_O1RES_MASK) 6709 #define SCT_RES_O2RES_MASK (0x30U) 6710 #define SCT_RES_O2RES_SHIFT (4U) 6711 /*! O2RES - Effect of simultaneous set and clear on output 2. 6712 * 0b00..No change. 6713 * 0b01..Set output (or clear based on the SETCLR2 field in the OUTPUTDIRCTRL register). 6714 * 0b10..Clear output n (or set based on the SETCLR2 field). 6715 * 0b11..Toggle output. 6716 */ 6717 #define SCT_RES_O2RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O2RES_SHIFT)) & SCT_RES_O2RES_MASK) 6718 #define SCT_RES_O3RES_MASK (0xC0U) 6719 #define SCT_RES_O3RES_SHIFT (6U) 6720 /*! O3RES - Effect of simultaneous set and clear on output 3. 6721 * 0b00..No change. 6722 * 0b01..Set output (or clear based on the SETCLR3 field in the OUTPUTDIRCTRL register). 6723 * 0b10..Clear output (or set based on the SETCLR3 field). 6724 * 0b11..Toggle output. 6725 */ 6726 #define SCT_RES_O3RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O3RES_SHIFT)) & SCT_RES_O3RES_MASK) 6727 #define SCT_RES_O4RES_MASK (0x300U) 6728 #define SCT_RES_O4RES_SHIFT (8U) 6729 /*! O4RES - Effect of simultaneous set and clear on output 4. 6730 * 0b00..No change. 6731 * 0b01..Set output (or clear based on the SETCLR4 field in the OUTPUTDIRCTRL register). 6732 * 0b10..Clear output (or set based on the SETCLR4 field). 6733 * 0b11..Toggle output. 6734 */ 6735 #define SCT_RES_O4RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O4RES_SHIFT)) & SCT_RES_O4RES_MASK) 6736 #define SCT_RES_O5RES_MASK (0xC00U) 6737 #define SCT_RES_O5RES_SHIFT (10U) 6738 /*! O5RES - Effect of simultaneous set and clear on output 5. 6739 * 0b00..No change. 6740 * 0b01..Set output (or clear based on the SETCLR5 field in the OUTPUTDIRCTRL register). 6741 * 0b10..Clear output (or set based on the SETCLR5 field). 6742 * 0b11..Toggle output. 6743 */ 6744 #define SCT_RES_O5RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O5RES_SHIFT)) & SCT_RES_O5RES_MASK) 6745 #define SCT_RES_O6RES_MASK (0x3000U) 6746 #define SCT_RES_O6RES_SHIFT (12U) 6747 /*! O6RES - Effect of simultaneous set and clear on output 6. 6748 * 0b00..No change. 6749 * 0b01..Set output (or clear based on the SETCLR6 field in the OUTPUTDIRCTRL register). 6750 * 0b10..Clear output (or set based on the SETCLR6 field). 6751 * 0b11..Toggle output. 6752 */ 6753 #define SCT_RES_O6RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O6RES_SHIFT)) & SCT_RES_O6RES_MASK) 6754 #define SCT_RES_O7RES_MASK (0xC000U) 6755 #define SCT_RES_O7RES_SHIFT (14U) 6756 /*! O7RES - Effect of simultaneous set and clear on output 7. 6757 * 0b00..No change. 6758 * 0b01..Set output (or clear based on the SETCLR7 field in the OUTPUTDIRCTRL register). 6759 * 0b10..Clear output n (or set based on the SETCLR7 field). 6760 * 0b11..Toggle output. 6761 */ 6762 #define SCT_RES_O7RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O7RES_SHIFT)) & SCT_RES_O7RES_MASK) 6763 #define SCT_RES_O8RES_MASK (0x30000U) 6764 #define SCT_RES_O8RES_SHIFT (16U) 6765 /*! O8RES - Effect of simultaneous set and clear on output 8. 6766 * 0b00..No change. 6767 * 0b01..Set output (or clear based on the SETCLR8 field in the OUTPUTDIRCTRL register). 6768 * 0b10..Clear output (or set based on the SETCLR8 field). 6769 * 0b11..Toggle output. 6770 */ 6771 #define SCT_RES_O8RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O8RES_SHIFT)) & SCT_RES_O8RES_MASK) 6772 #define SCT_RES_O9RES_MASK (0xC0000U) 6773 #define SCT_RES_O9RES_SHIFT (18U) 6774 /*! O9RES - Effect of simultaneous set and clear on output 9. 6775 * 0b00..No change. 6776 * 0b01..Set output (or clear based on the SETCLR9 field in the OUTPUTDIRCTRL register). 6777 * 0b10..Clear output (or set based on the SETCLR9 field). 6778 * 0b11..Toggle output. 6779 */ 6780 #define SCT_RES_O9RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O9RES_SHIFT)) & SCT_RES_O9RES_MASK) 6781 #define SCT_RES_O10RES_MASK (0x300000U) 6782 #define SCT_RES_O10RES_SHIFT (20U) 6783 /*! O10RES - Effect of simultaneous set and clear on output 10. 6784 * 0b00..No change. 6785 * 0b01..Set output (or clear based on the SETCLR10 field in the OUTPUTDIRCTRL register). 6786 * 0b10..Clear output (or set based on the SETCLR10 field). 6787 * 0b11..Toggle output. 6788 */ 6789 #define SCT_RES_O10RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O10RES_SHIFT)) & SCT_RES_O10RES_MASK) 6790 #define SCT_RES_O11RES_MASK (0xC00000U) 6791 #define SCT_RES_O11RES_SHIFT (22U) 6792 /*! O11RES - Effect of simultaneous set and clear on output 11. 6793 * 0b00..No change. 6794 * 0b01..Set output (or clear based on the SETCLR11 field in the OUTPUTDIRCTRL register). 6795 * 0b10..Clear output (or set based on the SETCLR11 field). 6796 * 0b11..Toggle output. 6797 */ 6798 #define SCT_RES_O11RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O11RES_SHIFT)) & SCT_RES_O11RES_MASK) 6799 #define SCT_RES_O12RES_MASK (0x3000000U) 6800 #define SCT_RES_O12RES_SHIFT (24U) 6801 /*! O12RES - Effect of simultaneous set and clear on output 12. 6802 * 0b00..No change. 6803 * 0b01..Set output (or clear based on the SETCLR12 field in the OUTPUTDIRCTRL register). 6804 * 0b10..Clear output (or set based on the SETCLR12 field). 6805 * 0b11..Toggle output. 6806 */ 6807 #define SCT_RES_O12RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O12RES_SHIFT)) & SCT_RES_O12RES_MASK) 6808 #define SCT_RES_O13RES_MASK (0xC000000U) 6809 #define SCT_RES_O13RES_SHIFT (26U) 6810 /*! O13RES - Effect of simultaneous set and clear on output 13. 6811 * 0b00..No change. 6812 * 0b01..Set output (or clear based on the SETCLR13 field in the OUTPUTDIRCTRL register). 6813 * 0b10..Clear output (or set based on the SETCLR13 field). 6814 * 0b11..Toggle output. 6815 */ 6816 #define SCT_RES_O13RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O13RES_SHIFT)) & SCT_RES_O13RES_MASK) 6817 #define SCT_RES_O14RES_MASK (0x30000000U) 6818 #define SCT_RES_O14RES_SHIFT (28U) 6819 /*! O14RES - Effect of simultaneous set and clear on output 14. 6820 * 0b00..No change. 6821 * 0b01..Set output (or clear based on the SETCLR14 field in the OUTPUTDIRCTRL register). 6822 * 0b10..Clear output (or set based on the SETCLR14 field). 6823 * 0b11..Toggle output. 6824 */ 6825 #define SCT_RES_O14RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O14RES_SHIFT)) & SCT_RES_O14RES_MASK) 6826 #define SCT_RES_O15RES_MASK (0xC0000000U) 6827 #define SCT_RES_O15RES_SHIFT (30U) 6828 /*! O15RES - Effect of simultaneous set and clear on output 15. 6829 * 0b00..No change. 6830 * 0b01..Set output (or clear based on the SETCLR15 field in the OUTPUTDIRCTRL register). 6831 * 0b10..Clear output (or set based on the SETCLR15 field). 6832 * 0b11..Toggle output. 6833 */ 6834 #define SCT_RES_O15RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O15RES_SHIFT)) & SCT_RES_O15RES_MASK) 6835 /*! @} */ 6836 6837 /*! @name DMAREQ0 - SCT DMA request 0 register */ 6838 /*! @{ */ 6839 #define SCT_DMAREQ0_DEV_0_MASK (0xFFFFU) 6840 #define SCT_DMAREQ0_DEV_0_SHIFT (0U) 6841 /*! DEV_0 - If bit n is one, event n triggers DMA request 0 (event 0 = bit 0, event 1 = bit 1, 6842 * etc.). The number of bits = number of events in this SCT. 6843 */ 6844 #define SCT_DMAREQ0_DEV_0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_0_SHIFT)) & SCT_DMAREQ0_DEV_0_MASK) 6845 #define SCT_DMAREQ0_DRL0_MASK (0x40000000U) 6846 #define SCT_DMAREQ0_DRL0_SHIFT (30U) 6847 /*! DRL0 - A 1 in this bit triggers DMA request 0 when it loads the MATCH_L/Unified registers from the RELOAD_L/Unified registers. 6848 */ 6849 #define SCT_DMAREQ0_DRL0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DRL0_SHIFT)) & SCT_DMAREQ0_DRL0_MASK) 6850 #define SCT_DMAREQ0_DRQ0_MASK (0x80000000U) 6851 #define SCT_DMAREQ0_DRQ0_SHIFT (31U) 6852 /*! DRQ0 - This read-only bit indicates the state of DMA Request 0. Note that if the related DMA 6853 * channel is enabled and properly set up, it is unlikely that software will see this flag, it will 6854 * be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA 6855 * setup. 6856 */ 6857 #define SCT_DMAREQ0_DRQ0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DRQ0_SHIFT)) & SCT_DMAREQ0_DRQ0_MASK) 6858 /*! @} */ 6859 6860 /*! @name DMAREQ1 - SCT DMA request 1 register */ 6861 /*! @{ */ 6862 #define SCT_DMAREQ1_DEV_1_MASK (0xFFFFU) 6863 #define SCT_DMAREQ1_DEV_1_SHIFT (0U) 6864 /*! DEV_1 - If bit n is one, event n triggers DMA request 1 (event 0 = bit 0, event 1 = bit 1, 6865 * etc.). The number of bits = number of events in this SCT. 6866 */ 6867 #define SCT_DMAREQ1_DEV_1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_1_SHIFT)) & SCT_DMAREQ1_DEV_1_MASK) 6868 #define SCT_DMAREQ1_DRL1_MASK (0x40000000U) 6869 #define SCT_DMAREQ1_DRL1_SHIFT (30U) 6870 /*! DRL1 - A 1 in this bit triggers DMA request 1 when it loads the Match L/Unified registers from the Reload L/Unified registers. 6871 */ 6872 #define SCT_DMAREQ1_DRL1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DRL1_SHIFT)) & SCT_DMAREQ1_DRL1_MASK) 6873 #define SCT_DMAREQ1_DRQ1_MASK (0x80000000U) 6874 #define SCT_DMAREQ1_DRQ1_SHIFT (31U) 6875 /*! DRQ1 - This read-only bit indicates the state of DMA Request 1. Note that if the related DMA 6876 * channel is enabled and properly set up, it is unlikely that software will see this flag, it will 6877 * be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA 6878 * setup. 6879 */ 6880 #define SCT_DMAREQ1_DRQ1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DRQ1_SHIFT)) & SCT_DMAREQ1_DRQ1_MASK) 6881 /*! @} */ 6882 6883 /*! @name EVEN - SCT event interrupt enable register */ 6884 /*! @{ */ 6885 #define SCT_EVEN_IEN_MASK (0xFFFFU) 6886 #define SCT_EVEN_IEN_SHIFT (0U) 6887 /*! IEN - The SCT requests an interrupt when bit n of this register and the event flag register are 6888 * both one (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in 6889 * this SCT. 6890 */ 6891 #define SCT_EVEN_IEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN_SHIFT)) & SCT_EVEN_IEN_MASK) 6892 /*! @} */ 6893 6894 /*! @name EVFLAG - SCT event flag register */ 6895 /*! @{ */ 6896 #define SCT_EVFLAG_FLAG_MASK (0xFFFFU) 6897 #define SCT_EVFLAG_FLAG_SHIFT (0U) 6898 /*! FLAG - Bit n is one if event n has occurred since reset or a 1 was last written to this bit 6899 * (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. 6900 */ 6901 #define SCT_EVFLAG_FLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG_SHIFT)) & SCT_EVFLAG_FLAG_MASK) 6902 /*! @} */ 6903 6904 /*! @name CONEN - SCT conflict interrupt enable register */ 6905 /*! @{ */ 6906 #define SCT_CONEN_NCEN_MASK (0xFFFFU) 6907 #define SCT_CONEN_NCEN_SHIFT (0U) 6908 /*! NCEN - The SCT requests an interrupt when bit n of this register and the SCT conflict flag 6909 * register are both one (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of 6910 * outputs in this SCT. 6911 */ 6912 #define SCT_CONEN_NCEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN_SHIFT)) & SCT_CONEN_NCEN_MASK) 6913 /*! @} */ 6914 6915 /*! @name CONFLAG - SCT conflict flag register */ 6916 /*! @{ */ 6917 #define SCT_CONFLAG_NCFLAG_MASK (0xFFFFU) 6918 #define SCT_CONFLAG_NCFLAG_SHIFT (0U) 6919 /*! NCFLAG - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was 6920 * last written to this bit (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = 6921 * number of outputs in this SCT. 6922 */ 6923 #define SCT_CONFLAG_NCFLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG_SHIFT)) & SCT_CONFLAG_NCFLAG_MASK) 6924 #define SCT_CONFLAG_BUSERRL_MASK (0x40000000U) 6925 #define SCT_CONFLAG_BUSERRL_SHIFT (30U) 6926 /*! BUSERRL - The most recent bus error from this SCT involved writing CTR L/Unified, STATE 6927 * L/Unified, MATCH L/Unified, or the Output register when the L/U counter was not halted. A word write 6928 * to certain L and H registers can be half successful and half unsuccessful. 6929 */ 6930 #define SCT_CONFLAG_BUSERRL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRL_SHIFT)) & SCT_CONFLAG_BUSERRL_MASK) 6931 #define SCT_CONFLAG_BUSERRH_MASK (0x80000000U) 6932 #define SCT_CONFLAG_BUSERRH_SHIFT (31U) 6933 /*! BUSERRH - The most recent bus error from this SCT involved writing CTR H, STATE H, MATCH H, or 6934 * the Output register when the H counter was not halted. 6935 */ 6936 #define SCT_CONFLAG_BUSERRH(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRH_SHIFT)) & SCT_CONFLAG_BUSERRH_MASK) 6937 /*! @} */ 6938 6939 /*! @name CAPL - SCT_CAPL register */ 6940 /*! @{ */ 6941 #define SCT_CAPL_CAPL_MASK (0xFFFFU) 6942 #define SCT_CAPL_CAPL_SHIFT (0U) 6943 #define SCT_CAPL_CAPL(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPL_CAPL_SHIFT)) & SCT_CAPL_CAPL_MASK) 6944 /*! @} */ 6945 6946 /* The count of SCT_CAPL */ 6947 #define SCT_CAPL_COUNT (10U) 6948 6949 /*! @name CAPH - SCT_CAPH register */ 6950 /*! @{ */ 6951 #define SCT_CAPH_CAPH_MASK (0xFFFFU) 6952 #define SCT_CAPH_CAPH_SHIFT (0U) 6953 #define SCT_CAPH_CAPH(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPH_CAPH_SHIFT)) & SCT_CAPH_CAPH_MASK) 6954 /*! @} */ 6955 6956 /* The count of SCT_CAPH */ 6957 #define SCT_CAPH_COUNT (10U) 6958 6959 /*! @name CAP - SCT capture register of capture channel */ 6960 /*! @{ */ 6961 #define SCT_CAP_CAPn_L_MASK (0xFFFFU) 6962 #define SCT_CAP_CAPn_L_SHIFT (0U) 6963 /*! CAPn_L - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. 6964 * When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last 6965 * captured. 6966 */ 6967 #define SCT_CAP_CAPn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAP_CAPn_L_SHIFT)) & SCT_CAP_CAPn_L_MASK) 6968 #define SCT_CAP_CAPn_H_MASK (0xFFFF0000U) 6969 #define SCT_CAP_CAPn_H_SHIFT (16U) 6970 /*! CAPn_H - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. 6971 * When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last 6972 * captured. 6973 */ 6974 #define SCT_CAP_CAPn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAP_CAPn_H_SHIFT)) & SCT_CAP_CAPn_H_MASK) 6975 /*! @} */ 6976 6977 /* The count of SCT_CAP */ 6978 #define SCT_CAP_COUNT (10U) 6979 6980 /*! @name MATCHL - SCT_MATCHL register */ 6981 /*! @{ */ 6982 #define SCT_MATCHL_MATCHL_MASK (0xFFFFU) 6983 #define SCT_MATCHL_MATCHL_SHIFT (0U) 6984 #define SCT_MATCHL_MATCHL(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHL_MATCHL_SHIFT)) & SCT_MATCHL_MATCHL_MASK) 6985 /*! @} */ 6986 6987 /* The count of SCT_MATCHL */ 6988 #define SCT_MATCHL_COUNT (10U) 6989 6990 /*! @name MATCHH - SCT_MATCHH register */ 6991 /*! @{ */ 6992 #define SCT_MATCHH_MATCHH_MASK (0xFFFFU) 6993 #define SCT_MATCHH_MATCHH_SHIFT (0U) 6994 #define SCT_MATCHH_MATCHH(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHH_MATCHH_SHIFT)) & SCT_MATCHH_MATCHH_MASK) 6995 /*! @} */ 6996 6997 /* The count of SCT_MATCHH */ 6998 #define SCT_MATCHH_COUNT (10U) 6999 7000 /*! @name MATCH - SCT match value register of match channels */ 7001 /*! @{ */ 7002 #define SCT_MATCH_MATCHn_L_MASK (0xFFFFU) 7003 #define SCT_MATCH_MATCHn_L_SHIFT (0U) 7004 /*! MATCHn_L - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When 7005 * UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified 7006 * counter. 7007 */ 7008 #define SCT_MATCH_MATCHn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCH_MATCHn_L_SHIFT)) & SCT_MATCH_MATCHn_L_MASK) 7009 #define SCT_MATCH_MATCHn_H_MASK (0xFFFF0000U) 7010 #define SCT_MATCH_MATCHn_H_SHIFT (16U) 7011 /*! MATCHn_H - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When 7012 * UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified 7013 * counter. 7014 */ 7015 #define SCT_MATCH_MATCHn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCH_MATCHn_H_SHIFT)) & SCT_MATCH_MATCHn_H_MASK) 7016 /*! @} */ 7017 7018 /* The count of SCT_MATCH */ 7019 #define SCT_MATCH_COUNT (10U) 7020 7021 /*! @name CAPCTRLL - SCT_CAPCTRLL register */ 7022 /*! @{ */ 7023 #define SCT_CAPCTRLL_CAPCTRLL_MASK (0xFFFFU) 7024 #define SCT_CAPCTRLL_CAPCTRLL_SHIFT (0U) 7025 #define SCT_CAPCTRLL_CAPCTRLL(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPCTRLL_CAPCTRLL_SHIFT)) & SCT_CAPCTRLL_CAPCTRLL_MASK) 7026 /*! @} */ 7027 7028 /* The count of SCT_CAPCTRLL */ 7029 #define SCT_CAPCTRLL_COUNT (10U) 7030 7031 /*! @name CAPCTRLH - SCT_CAPCTRLH register */ 7032 /*! @{ */ 7033 #define SCT_CAPCTRLH_CAPCTRLH_MASK (0xFFFFU) 7034 #define SCT_CAPCTRLH_CAPCTRLH_SHIFT (0U) 7035 #define SCT_CAPCTRLH_CAPCTRLH(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPCTRLH_CAPCTRLH_SHIFT)) & SCT_CAPCTRLH_CAPCTRLH_MASK) 7036 /*! @} */ 7037 7038 /* The count of SCT_CAPCTRLH */ 7039 #define SCT_CAPCTRLH_COUNT (10U) 7040 7041 /*! @name CAPCTRL - SCT capture control register */ 7042 /*! @{ */ 7043 #define SCT_CAPCTRL_CAPCONn_L_MASK (0xFFFFU) 7044 #define SCT_CAPCTRL_CAPCONn_L_SHIFT (0U) 7045 /*! CAPCONn_L - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) 7046 * register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of 7047 * match/captures in this SCT. 7048 */ 7049 #define SCT_CAPCTRL_CAPCONn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAPCTRL_CAPCONn_L_SHIFT)) & SCT_CAPCTRL_CAPCONn_L_MASK) 7050 #define SCT_CAPCTRL_CAPCONn_H_MASK (0xFFFF0000U) 7051 #define SCT_CAPCTRL_CAPCONn_H_SHIFT (16U) 7052 /*! CAPCONn_H - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 7053 * 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. 7054 */ 7055 #define SCT_CAPCTRL_CAPCONn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAPCTRL_CAPCONn_H_SHIFT)) & SCT_CAPCTRL_CAPCONn_H_MASK) 7056 /*! @} */ 7057 7058 /* The count of SCT_CAPCTRL */ 7059 #define SCT_CAPCTRL_COUNT (10U) 7060 7061 /*! @name MATCHRELL - SCT_MATCHRELL register */ 7062 /*! @{ */ 7063 #define SCT_MATCHRELL_MATCHRELL_MASK (0xFFFFU) 7064 #define SCT_MATCHRELL_MATCHRELL_SHIFT (0U) 7065 #define SCT_MATCHRELL_MATCHRELL(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHRELL_MATCHRELL_SHIFT)) & SCT_MATCHRELL_MATCHRELL_MASK) 7066 /*! @} */ 7067 7068 /* The count of SCT_MATCHRELL */ 7069 #define SCT_MATCHRELL_COUNT (10U) 7070 7071 /*! @name MATCHRELH - SCT_MATCHRELH register */ 7072 /*! @{ */ 7073 #define SCT_MATCHRELH_MATCHRELH_MASK (0xFFFFU) 7074 #define SCT_MATCHRELH_MATCHRELH_SHIFT (0U) 7075 #define SCT_MATCHRELH_MATCHRELH(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHRELH_MATCHRELH_SHIFT)) & SCT_MATCHRELH_MATCHRELH_MASK) 7076 /*! @} */ 7077 7078 /* The count of SCT_MATCHRELH */ 7079 #define SCT_MATCHRELH_COUNT (10U) 7080 7081 /*! @name MATCHREL - SCT match reload value register */ 7082 /*! @{ */ 7083 #define SCT_MATCHREL_RELOADn_L_MASK (0xFFFFU) 7084 #define SCT_MATCHREL_RELOADn_L_SHIFT (0U) 7085 /*! RELOADn_L - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. 7086 * When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn 7087 * register. 7088 */ 7089 #define SCT_MATCHREL_RELOADn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCHREL_RELOADn_L_SHIFT)) & SCT_MATCHREL_RELOADn_L_MASK) 7090 #define SCT_MATCHREL_RELOADn_H_MASK (0xFFFF0000U) 7091 #define SCT_MATCHREL_RELOADn_H_SHIFT (16U) 7092 /*! RELOADn_H - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When 7093 * UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn 7094 * register. 7095 */ 7096 #define SCT_MATCHREL_RELOADn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCHREL_RELOADn_H_SHIFT)) & SCT_MATCHREL_RELOADn_H_MASK) 7097 /*! @} */ 7098 7099 /* The count of SCT_MATCHREL */ 7100 #define SCT_MATCHREL_COUNT (10U) 7101 7102 /*! @name EV_STATE - SCT event state register 0 */ 7103 /*! @{ */ 7104 #define SCT_EV_STATE_STATEMSKn_MASK (0xFFFFU) 7105 #define SCT_EV_STATE_STATEMSKn_SHIFT (0U) 7106 /*! STATEMSKn - If bit m is one, event n happens in state m of the counter selected by the HEVENT 7107 * bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of 7108 * bits = number of states in this SCT. 7109 */ 7110 #define SCT_EV_STATE_STATEMSKn(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_STATE_STATEMSKn_SHIFT)) & SCT_EV_STATE_STATEMSKn_MASK) 7111 /*! @} */ 7112 7113 /* The count of SCT_EV_STATE */ 7114 #define SCT_EV_STATE_COUNT (10U) 7115 7116 /*! @name EV_CTRL - SCT event control register 0 */ 7117 /*! @{ */ 7118 #define SCT_EV_CTRL_MATCHSEL_MASK (0xFU) 7119 #define SCT_EV_CTRL_MATCHSEL_SHIFT (0U) 7120 /*! MATCHSEL - Selects the Match register associated with this event (if any). A match can occur 7121 * only when the counter selected by the HEVENT bit is running. 7122 */ 7123 #define SCT_EV_CTRL_MATCHSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_MATCHSEL_SHIFT)) & SCT_EV_CTRL_MATCHSEL_MASK) 7124 #define SCT_EV_CTRL_HEVENT_MASK (0x10U) 7125 #define SCT_EV_CTRL_HEVENT_SHIFT (4U) 7126 /*! HEVENT - Select L/H counter. Do not set this bit if UNIFY = 1. 7127 * 0b0..Selects the L state and the L match register selected by MATCHSEL. 7128 * 0b1..Selects the H state and the H match register selected by MATCHSEL. 7129 */ 7130 #define SCT_EV_CTRL_HEVENT(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_HEVENT_SHIFT)) & SCT_EV_CTRL_HEVENT_MASK) 7131 #define SCT_EV_CTRL_OUTSEL_MASK (0x20U) 7132 #define SCT_EV_CTRL_OUTSEL_SHIFT (5U) 7133 /*! OUTSEL - Input/output select 7134 * 0b0..Selects the inputs selected by IOSEL. 7135 * 0b1..Selects the outputs selected by IOSEL. 7136 */ 7137 #define SCT_EV_CTRL_OUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_OUTSEL_SHIFT)) & SCT_EV_CTRL_OUTSEL_MASK) 7138 #define SCT_EV_CTRL_IOSEL_MASK (0x3C0U) 7139 #define SCT_EV_CTRL_IOSEL_SHIFT (6U) 7140 /*! IOSEL - Selects the input or output signal number associated with this event (if any). Do not 7141 * select an input in this register if CKMODE is 1x. In this case the clock input is an implicit 7142 * ingredient of every event. 7143 */ 7144 #define SCT_EV_CTRL_IOSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_IOSEL_SHIFT)) & SCT_EV_CTRL_IOSEL_MASK) 7145 #define SCT_EV_CTRL_IOCOND_MASK (0xC00U) 7146 #define SCT_EV_CTRL_IOCOND_SHIFT (10U) 7147 /*! IOCOND - Selects the I/O condition for event n. (The detection of edges on outputs lag the 7148 * conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state 7149 * detection, an input must have a minimum pulse width of at least one SCT clock period . 7150 * 0b00..LOW 7151 * 0b01..Rise 7152 * 0b10..Fall 7153 * 0b11..HIGH 7154 */ 7155 #define SCT_EV_CTRL_IOCOND(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_IOCOND_SHIFT)) & SCT_EV_CTRL_IOCOND_MASK) 7156 #define SCT_EV_CTRL_COMBMODE_MASK (0x3000U) 7157 #define SCT_EV_CTRL_COMBMODE_SHIFT (12U) 7158 /*! COMBMODE - Selects how the specified match and I/O condition are used and combined. 7159 * 0b00..OR. The event occurs when either the specified match or I/O condition occurs. 7160 * 0b01..MATCH. Uses the specified match only. 7161 * 0b10..IO. Uses the specified I/O condition only. 7162 * 0b11..AND. The event occurs when the specified match and I/O condition occur simultaneously. 7163 */ 7164 #define SCT_EV_CTRL_COMBMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_COMBMODE_SHIFT)) & SCT_EV_CTRL_COMBMODE_MASK) 7165 #define SCT_EV_CTRL_STATELD_MASK (0x4000U) 7166 #define SCT_EV_CTRL_STATELD_SHIFT (14U) 7167 /*! STATELD - This bit controls how the STATEV value modifies the state selected by HEVENT when this 7168 * event is the highest-numbered event occurring for that state. 7169 * 0b0..STATEV value is added into STATE (the carry-out is ignored). 7170 * 0b1..STATEV value is loaded into STATE. 7171 */ 7172 #define SCT_EV_CTRL_STATELD(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_STATELD_SHIFT)) & SCT_EV_CTRL_STATELD_MASK) 7173 #define SCT_EV_CTRL_STATEV_MASK (0xF8000U) 7174 #define SCT_EV_CTRL_STATEV_SHIFT (15U) 7175 /*! STATEV - This value is loaded into or added to the state selected by HEVENT, depending on 7176 * STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and 7177 * STATEV are both zero, there is no change to the STATE value. 7178 */ 7179 #define SCT_EV_CTRL_STATEV(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_STATEV_SHIFT)) & SCT_EV_CTRL_STATEV_MASK) 7180 #define SCT_EV_CTRL_MATCHMEM_MASK (0x100000U) 7181 #define SCT_EV_CTRL_MATCHMEM_SHIFT (20U) 7182 /*! MATCHMEM - If this bit is one and the COMBMODE field specifies a match component to the 7183 * triggering of this event, then a match is considered to be active whenever the counter value is 7184 * GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR 7185 * EQUAL TO the match value when counting down. If this bit is zero, a match is only be active 7186 * during the cycle when the counter is equal to the match value. 7187 */ 7188 #define SCT_EV_CTRL_MATCHMEM(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_MATCHMEM_SHIFT)) & SCT_EV_CTRL_MATCHMEM_MASK) 7189 #define SCT_EV_CTRL_DIRECTION_MASK (0x600000U) 7190 #define SCT_EV_CTRL_DIRECTION_SHIFT (21U) 7191 /*! DIRECTION - Direction qualifier for event generation. This field only applies when the counters 7192 * are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved. 7193 * 0b00..Direction independent. This event is triggered regardless of the count direction. 7194 * 0b01..Counting up. This event is triggered only during up-counting when BIDIR = 1. 7195 * 0b10..Counting down. This event is triggered only during down-counting when BIDIR = 1. 7196 */ 7197 #define SCT_EV_CTRL_DIRECTION(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_DIRECTION_SHIFT)) & SCT_EV_CTRL_DIRECTION_MASK) 7198 /*! @} */ 7199 7200 /* The count of SCT_EV_CTRL */ 7201 #define SCT_EV_CTRL_COUNT (10U) 7202 7203 /*! @name OUT_SET - SCT output 0 set register */ 7204 /*! @{ */ 7205 #define SCT_OUT_SET_SET_MASK (0xFFFFU) 7206 #define SCT_OUT_SET_SET_SHIFT (0U) 7207 /*! SET - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output 7208 * 0 = bit 0, output 1 = bit 1, etc. The number of bits = number of events in this SCT. When the 7209 * counter is used in bi-directional mode, it is possible to reverse the action specified by the 7210 * output set and clear registers when counting down, See the OUTPUTCTRL register. 7211 */ 7212 #define SCT_OUT_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_SET_SET_SHIFT)) & SCT_OUT_SET_SET_MASK) 7213 /*! @} */ 7214 7215 /* The count of SCT_OUT_SET */ 7216 #define SCT_OUT_SET_COUNT (8U) 7217 7218 /*! @name OUT_CLR - SCT output 0 clear register */ 7219 /*! @{ */ 7220 #define SCT_OUT_CLR_CLR_MASK (0xFFFFU) 7221 #define SCT_OUT_CLR_CLR_SHIFT (0U) 7222 /*! CLR - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 7223 * = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT. When the 7224 * counter is used in bi-directional mode, it is possible to reverse the action specified by the 7225 * output set and clear registers when counting down, See the OUTPUTCTRL register. 7226 */ 7227 #define SCT_OUT_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_CLR_CLR_SHIFT)) & SCT_OUT_CLR_CLR_MASK) 7228 /*! @} */ 7229 7230 /* The count of SCT_OUT_CLR */ 7231 #define SCT_OUT_CLR_COUNT (8U) 7232 7233 7234 /*! 7235 * @} 7236 */ /* end of group SCT_Register_Masks */ 7237 7238 7239 /* SCT - Peripheral instance base addresses */ 7240 /** Peripheral SCT0 base address */ 7241 #define SCT0_BASE (0x40085000u) 7242 /** Peripheral SCT0 base pointer */ 7243 #define SCT0 ((SCT_Type *)SCT0_BASE) 7244 /** Array initializer of SCT peripheral base addresses */ 7245 #define SCT_BASE_ADDRS { SCT0_BASE } 7246 /** Array initializer of SCT peripheral base pointers */ 7247 #define SCT_BASE_PTRS { SCT0 } 7248 /** Interrupt vectors for the SCT peripheral type */ 7249 #define SCT_IRQS { SCT0_IRQn } 7250 7251 /*! 7252 * @} 7253 */ /* end of group SCT_Peripheral_Access_Layer */ 7254 7255 7256 /* ---------------------------------------------------------------------------- 7257 -- SPI Peripheral Access Layer 7258 ---------------------------------------------------------------------------- */ 7259 7260 /*! 7261 * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer 7262 * @{ 7263 */ 7264 7265 /** SPI - Register Layout Typedef */ 7266 typedef struct { 7267 uint8_t RESERVED_0[1024]; 7268 __IO uint32_t CFG; /**< SPI Configuration register, offset: 0x400 */ 7269 __IO uint32_t DLY; /**< SPI Delay register, offset: 0x404 */ 7270 __IO uint32_t STAT; /**< SPI Status. Some status flags can be cleared by writing a 1 to that bit position., offset: 0x408 */ 7271 __IO uint32_t INTENSET; /**< SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0x40C */ 7272 __O uint32_t INTENCLR; /**< SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared., offset: 0x410 */ 7273 uint8_t RESERVED_1[16]; 7274 __IO uint32_t DIV; /**< SPI clock Divider, offset: 0x424 */ 7275 __I uint32_t INTSTAT; /**< SPI Interrupt Status, offset: 0x428 */ 7276 uint8_t RESERVED_2[2516]; 7277 __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */ 7278 __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ 7279 __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */ 7280 uint8_t RESERVED_3[4]; 7281 __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */ 7282 __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */ 7283 __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */ 7284 uint8_t RESERVED_4[4]; 7285 __IO uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ 7286 uint8_t RESERVED_5[12]; 7287 __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */ 7288 uint8_t RESERVED_6[12]; 7289 __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */ 7290 } SPI_Type; 7291 7292 /* ---------------------------------------------------------------------------- 7293 -- SPI Register Masks 7294 ---------------------------------------------------------------------------- */ 7295 7296 /*! 7297 * @addtogroup SPI_Register_Masks SPI Register Masks 7298 * @{ 7299 */ 7300 7301 /*! @name CFG - SPI Configuration register */ 7302 /*! @{ */ 7303 #define SPI_CFG_ENABLE_MASK (0x1U) 7304 #define SPI_CFG_ENABLE_SHIFT (0U) 7305 /*! ENABLE - SPI enable. 7306 * 0b0..Disabled. The SPI is disabled and the internal state machine and counters are reset. 7307 * 0b1..Enabled. The SPI is enabled for operation. 7308 */ 7309 #define SPI_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_ENABLE_SHIFT)) & SPI_CFG_ENABLE_MASK) 7310 #define SPI_CFG_MASTER_MASK (0x4U) 7311 #define SPI_CFG_MASTER_SHIFT (2U) 7312 /*! MASTER - Master mode select. 7313 * 0b0..Slave mode. The SPI will operate in slave mode. SCK, MOSI, and the SSEL signals are inputs, MISO is an output. 7314 * 0b1..Master mode. The SPI will operate in master mode. SCK, MOSI, and the SSEL signals are outputs, MISO is an input. 7315 */ 7316 #define SPI_CFG_MASTER(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_MASTER_SHIFT)) & SPI_CFG_MASTER_MASK) 7317 #define SPI_CFG_LSBF_MASK (0x8U) 7318 #define SPI_CFG_LSBF_SHIFT (3U) 7319 /*! LSBF - LSB First mode enable. 7320 * 0b0..Standard. Data is transmitted and received in standard MSB first order. 7321 * 0b1..Reverse. Data is transmitted and received in reverse order (LSB first). 7322 */ 7323 #define SPI_CFG_LSBF(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LSBF_SHIFT)) & SPI_CFG_LSBF_MASK) 7324 #define SPI_CFG_CPHA_MASK (0x10U) 7325 #define SPI_CFG_CPHA_SHIFT (4U) 7326 /*! CPHA - Clock Phase select. 7327 * 0b0..Change. The SPI captures serial data on the first clock transition of the transfer (when the clock 7328 * changes away from the rest state). Data is changed on the following edge. 7329 * 0b1..Capture. The SPI changes serial data on the first clock transition of the transfer (when the clock 7330 * changes away from the rest state). Data is captured on the following edge. 7331 */ 7332 #define SPI_CFG_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPHA_SHIFT)) & SPI_CFG_CPHA_MASK) 7333 #define SPI_CFG_CPOL_MASK (0x20U) 7334 #define SPI_CFG_CPOL_SHIFT (5U) 7335 /*! CPOL - Clock Polarity select. 7336 * 0b0..Low. The rest state of the clock (between transfers) is low. 7337 * 0b1..High. The rest state of the clock (between transfers) is high. 7338 */ 7339 #define SPI_CFG_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPOL_SHIFT)) & SPI_CFG_CPOL_MASK) 7340 #define SPI_CFG_LOOP_MASK (0x80U) 7341 #define SPI_CFG_LOOP_SHIFT (7U) 7342 /*! LOOP - Loopback mode enable. Loopback mode applies only to Master mode, and connects transmit 7343 * and receive data connected together to allow simple software testing. 7344 * 0b0..Disabled. 7345 * 0b1..Enabled. 7346 */ 7347 #define SPI_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LOOP_SHIFT)) & SPI_CFG_LOOP_MASK) 7348 #define SPI_CFG_SPOL0_MASK (0x100U) 7349 #define SPI_CFG_SPOL0_SHIFT (8U) 7350 /*! SPOL0 - SSEL0 Polarity select. 7351 * 0b0..Low. The SSEL0 pin is active low. 7352 * 0b1..High. The SSEL0 pin is active high. 7353 */ 7354 #define SPI_CFG_SPOL0(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL0_SHIFT)) & SPI_CFG_SPOL0_MASK) 7355 #define SPI_CFG_SPOL1_MASK (0x200U) 7356 #define SPI_CFG_SPOL1_SHIFT (9U) 7357 /*! SPOL1 - SSEL1 Polarity select. 7358 * 0b0..Low. The SSEL1 pin is active low. 7359 * 0b1..High. The SSEL1 pin is active high. 7360 */ 7361 #define SPI_CFG_SPOL1(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL1_SHIFT)) & SPI_CFG_SPOL1_MASK) 7362 #define SPI_CFG_SPOL2_MASK (0x400U) 7363 #define SPI_CFG_SPOL2_SHIFT (10U) 7364 /*! SPOL2 - SSEL2 Polarity select. 7365 * 0b0..Low. The SSEL2 pin is active low. 7366 * 0b1..High. The SSEL2 pin is active high. 7367 */ 7368 #define SPI_CFG_SPOL2(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL2_SHIFT)) & SPI_CFG_SPOL2_MASK) 7369 #define SPI_CFG_SPOL3_MASK (0x800U) 7370 #define SPI_CFG_SPOL3_SHIFT (11U) 7371 /*! SPOL3 - SSEL3 Polarity select. 7372 * 0b0..Low. The SSEL3 pin is active low. 7373 * 0b1..High. The SSEL3 pin is active high. 7374 */ 7375 #define SPI_CFG_SPOL3(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL3_SHIFT)) & SPI_CFG_SPOL3_MASK) 7376 /*! @} */ 7377 7378 /*! @name DLY - SPI Delay register */ 7379 /*! @{ */ 7380 #define SPI_DLY_PRE_DELAY_MASK (0xFU) 7381 #define SPI_DLY_PRE_DELAY_SHIFT (0U) 7382 /*! PRE_DELAY - Controls the amount of time between SSEL assertion and the beginning of a data 7383 * transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This 7384 * is not considered part of the pre-delay. 0x0 = No additional time is inserted. 0x1 = 1 SPI 7385 * clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are 7386 * inserted. 7387 */ 7388 #define SPI_DLY_PRE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_PRE_DELAY_SHIFT)) & SPI_DLY_PRE_DELAY_MASK) 7389 #define SPI_DLY_POST_DELAY_MASK (0xF0U) 7390 #define SPI_DLY_POST_DELAY_SHIFT (4U) 7391 /*! POST_DELAY - Controls the amount of time between the end of a data transfer and SSEL 7392 * deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock 7393 * times are inserted. 0xF = 15 SPI clock times are inserted. 7394 */ 7395 #define SPI_DLY_POST_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_POST_DELAY_SHIFT)) & SPI_DLY_POST_DELAY_MASK) 7396 #define SPI_DLY_FRAME_DELAY_MASK (0xF00U) 7397 #define SPI_DLY_FRAME_DELAY_SHIFT (8U) 7398 /*! FRAME_DELAY - If the EOF flag is set, controls the minimum amount of time between the current 7399 * frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 7400 * = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock 7401 * times are inserted. 7402 */ 7403 #define SPI_DLY_FRAME_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_FRAME_DELAY_SHIFT)) & SPI_DLY_FRAME_DELAY_MASK) 7404 #define SPI_DLY_TRANSFER_DELAY_MASK (0xF000U) 7405 #define SPI_DLY_TRANSFER_DELAY_SHIFT (12U) 7406 /*! TRANSFER_DELAY - Controls the minimum amount of time that the SSEL is deasserted between 7407 * transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 7408 * = The minimum time that SSEL is deasserted is 2 SPI clock times. 0x2 = The minimum time that 7409 * SSEL is deasserted is 3 SPI clock times. 0xF = The minimum time that SSEL is deasserted is 16 7410 * SPI clock times. 7411 */ 7412 #define SPI_DLY_TRANSFER_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_TRANSFER_DELAY_SHIFT)) & SPI_DLY_TRANSFER_DELAY_MASK) 7413 /*! @} */ 7414 7415 /*! @name STAT - SPI Status. Some status flags can be cleared by writing a 1 to that bit position. */ 7416 /*! @{ */ 7417 #define SPI_STAT_SSA_MASK (0x10U) 7418 #define SPI_STAT_SSA_SHIFT (4U) 7419 /*! SSA - Slave Select Assert. This flag is set whenever any slave select transitions from 7420 * deasserted to asserted, in both master and slave modes. This allows determining when the SPI 7421 * transmit/receive functions become busy, and allows waking up the device from reduced power modes when a 7422 * slave mode access begins. This flag is cleared by software. 7423 */ 7424 #define SPI_STAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSA_SHIFT)) & SPI_STAT_SSA_MASK) 7425 #define SPI_STAT_SSD_MASK (0x20U) 7426 #define SPI_STAT_SSD_SHIFT (5U) 7427 /*! SSD - Slave Select Deassert. This flag is set whenever any asserted slave selects transition to 7428 * deasserted, in both master and slave modes. This allows determining when the SPI 7429 * transmit/receive functions become idle. This flag is cleared by software. 7430 */ 7431 #define SPI_STAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSD_SHIFT)) & SPI_STAT_SSD_MASK) 7432 #define SPI_STAT_STALLED_MASK (0x40U) 7433 #define SPI_STAT_STALLED_SHIFT (6U) 7434 /*! STALLED - Stalled status flag. This indicates whether the SPI is currently in a stall condition. 7435 */ 7436 #define SPI_STAT_STALLED(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_STALLED_SHIFT)) & SPI_STAT_STALLED_MASK) 7437 #define SPI_STAT_ENDTRANSFER_MASK (0x80U) 7438 #define SPI_STAT_ENDTRANSFER_SHIFT (7U) 7439 /*! ENDTRANSFER - End Transfer control bit. Software can set this bit to force an end to the current 7440 * transfer when the transmitter finishes any activity already in progress, as if the EOT flag 7441 * had been set prior to the last transmission. This capability is included to support cases where 7442 * it is not known when transmit data is written that it will be the end of a transfer. The bit 7443 * is cleared when the transmitter becomes idle as the transfer comes to an end. Forcing an end 7444 * of transfer in this manner causes any specified FRAME_DELAY and TRANSFER_DELAY to be inserted. 7445 */ 7446 #define SPI_STAT_ENDTRANSFER(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_ENDTRANSFER_SHIFT)) & SPI_STAT_ENDTRANSFER_MASK) 7447 #define SPI_STAT_MSTIDLE_MASK (0x100U) 7448 #define SPI_STAT_MSTIDLE_SHIFT (8U) 7449 /*! MSTIDLE - Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. 7450 * This means that the transmit holding register is empty and the transmitter is not in the 7451 * process of sending data. 7452 */ 7453 #define SPI_STAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_MSTIDLE_SHIFT)) & SPI_STAT_MSTIDLE_MASK) 7454 /*! @} */ 7455 7456 /*! @name INTENSET - SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */ 7457 /*! @{ */ 7458 #define SPI_INTENSET_SSAEN_MASK (0x10U) 7459 #define SPI_INTENSET_SSAEN_SHIFT (4U) 7460 /*! SSAEN - Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted. 7461 * 0b0..Disabled. No interrupt will be generated when any Slave Select transitions from deasserted to asserted. 7462 * 0b1..Enabled. An interrupt will be generated when any Slave Select transitions from deasserted to asserted. 7463 */ 7464 #define SPI_INTENSET_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSAEN_SHIFT)) & SPI_INTENSET_SSAEN_MASK) 7465 #define SPI_INTENSET_SSDEN_MASK (0x20U) 7466 #define SPI_INTENSET_SSDEN_SHIFT (5U) 7467 /*! SSDEN - Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted. 7468 * 0b0..Disabled. No interrupt will be generated when all asserted Slave Selects transition to deasserted. 7469 * 0b1..Enabled. An interrupt will be generated when all asserted Slave Selects transition to deasserted. 7470 */ 7471 #define SPI_INTENSET_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSDEN_SHIFT)) & SPI_INTENSET_SSDEN_MASK) 7472 #define SPI_INTENSET_MSTIDLEEN_MASK (0x100U) 7473 #define SPI_INTENSET_MSTIDLEEN_SHIFT (8U) 7474 /*! MSTIDLEEN - Master idle interrupt enable. 7475 * 0b0..No interrupt will be generated when the SPI master function is idle. 7476 * 0b1..An interrupt will be generated when the SPI master function is fully idle. 7477 */ 7478 #define SPI_INTENSET_MSTIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_MSTIDLEEN_SHIFT)) & SPI_INTENSET_MSTIDLEEN_MASK) 7479 /*! @} */ 7480 7481 /*! @name INTENCLR - SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared. */ 7482 /*! @{ */ 7483 #define SPI_INTENCLR_SSAEN_MASK (0x10U) 7484 #define SPI_INTENCLR_SSAEN_SHIFT (4U) 7485 /*! SSAEN - Writing 1 clears the corresponding bit in the INTENSET register. 7486 */ 7487 #define SPI_INTENCLR_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSAEN_SHIFT)) & SPI_INTENCLR_SSAEN_MASK) 7488 #define SPI_INTENCLR_SSDEN_MASK (0x20U) 7489 #define SPI_INTENCLR_SSDEN_SHIFT (5U) 7490 /*! SSDEN - Writing 1 clears the corresponding bit in the INTENSET register. 7491 */ 7492 #define SPI_INTENCLR_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSDEN_SHIFT)) & SPI_INTENCLR_SSDEN_MASK) 7493 #define SPI_INTENCLR_MSTIDLE_MASK (0x100U) 7494 #define SPI_INTENCLR_MSTIDLE_SHIFT (8U) 7495 /*! MSTIDLE - Writing 1 clears the corresponding bit in the INTENSET register. 7496 */ 7497 #define SPI_INTENCLR_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_MSTIDLE_SHIFT)) & SPI_INTENCLR_MSTIDLE_MASK) 7498 /*! @} */ 7499 7500 /*! @name DIV - SPI clock Divider */ 7501 /*! @{ */ 7502 #define SPI_DIV_DIVVAL_MASK (0xFFFFU) 7503 #define SPI_DIV_DIVVAL_SHIFT (0U) 7504 /*! DIVVAL - Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the 7505 * SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1, 7506 * the value 1 results in FCLK/2, up to the maximum possible divide value of 0xFFFF, which results 7507 * in FCLK/65536. 7508 */ 7509 #define SPI_DIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << SPI_DIV_DIVVAL_SHIFT)) & SPI_DIV_DIVVAL_MASK) 7510 /*! @} */ 7511 7512 /*! @name INTSTAT - SPI Interrupt Status */ 7513 /*! @{ */ 7514 #define SPI_INTSTAT_SSA_MASK (0x10U) 7515 #define SPI_INTSTAT_SSA_SHIFT (4U) 7516 /*! SSA - Slave Select Assert. 7517 */ 7518 #define SPI_INTSTAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSA_SHIFT)) & SPI_INTSTAT_SSA_MASK) 7519 #define SPI_INTSTAT_SSD_MASK (0x20U) 7520 #define SPI_INTSTAT_SSD_SHIFT (5U) 7521 /*! SSD - Slave Select Deassert. 7522 */ 7523 #define SPI_INTSTAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSD_SHIFT)) & SPI_INTSTAT_SSD_MASK) 7524 #define SPI_INTSTAT_MSTIDLE_MASK (0x100U) 7525 #define SPI_INTSTAT_MSTIDLE_SHIFT (8U) 7526 /*! MSTIDLE - Master Idle status flag. 7527 */ 7528 #define SPI_INTSTAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_MSTIDLE_SHIFT)) & SPI_INTSTAT_MSTIDLE_MASK) 7529 /*! @} */ 7530 7531 /*! @name FIFOCFG - FIFO configuration and enable register. */ 7532 /*! @{ */ 7533 #define SPI_FIFOCFG_ENABLETX_MASK (0x1U) 7534 #define SPI_FIFOCFG_ENABLETX_SHIFT (0U) 7535 /*! ENABLETX - Enable the transmit FIFO. 7536 * 0b0..The transmit FIFO is not enabled. 7537 * 0b1..The transmit FIFO is enabled. 7538 */ 7539 #define SPI_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLETX_SHIFT)) & SPI_FIFOCFG_ENABLETX_MASK) 7540 #define SPI_FIFOCFG_ENABLERX_MASK (0x2U) 7541 #define SPI_FIFOCFG_ENABLERX_SHIFT (1U) 7542 /*! ENABLERX - Enable the receive FIFO. 7543 * 0b0..The receive FIFO is not enabled. 7544 * 0b1..The receive FIFO is enabled. 7545 */ 7546 #define SPI_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLERX_SHIFT)) & SPI_FIFOCFG_ENABLERX_MASK) 7547 #define SPI_FIFOCFG_SIZE_MASK (0x30U) 7548 #define SPI_FIFOCFG_SIZE_SHIFT (4U) 7549 /*! SIZE - FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 7550 * entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART. 7551 */ 7552 #define SPI_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_SIZE_SHIFT)) & SPI_FIFOCFG_SIZE_MASK) 7553 #define SPI_FIFOCFG_DMATX_MASK (0x1000U) 7554 #define SPI_FIFOCFG_DMATX_SHIFT (12U) 7555 /*! DMATX - DMA configuration for transmit. 7556 * 0b0..DMA is not used for the transmit function. 7557 * 0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. 7558 */ 7559 #define SPI_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMATX_SHIFT)) & SPI_FIFOCFG_DMATX_MASK) 7560 #define SPI_FIFOCFG_DMARX_MASK (0x2000U) 7561 #define SPI_FIFOCFG_DMARX_SHIFT (13U) 7562 /*! DMARX - DMA configuration for receive. 7563 * 0b0..DMA is not used for the receive function. 7564 * 0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. 7565 */ 7566 #define SPI_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMARX_SHIFT)) & SPI_FIFOCFG_DMARX_MASK) 7567 #define SPI_FIFOCFG_WAKETX_MASK (0x4000U) 7568 #define SPI_FIFOCFG_WAKETX_SHIFT (14U) 7569 /*! WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power 7570 * modes (up to power-down, as long as the peripheral function works in that power mode) without 7571 * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The 7572 * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware 7573 * Wake-up control register. 7574 * 0b0..Only enabled interrupts will wake up the device form reduced power modes. 7575 * 0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in 7576 * FIFOTRIG, even when the TXLVL interrupt is not enabled. 7577 */ 7578 #define SPI_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKETX_SHIFT)) & SPI_FIFOCFG_WAKETX_MASK) 7579 #define SPI_FIFOCFG_WAKERX_MASK (0x8000U) 7580 #define SPI_FIFOCFG_WAKERX_SHIFT (15U) 7581 /*! WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power 7582 * modes (up to power-down, as long as the peripheral function works in that power mode) without 7583 * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The 7584 * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware 7585 * Wake-up control register. 7586 * 0b0..Only enabled interrupts will wake up the device form reduced power modes. 7587 * 0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in 7588 * FIFOTRIG, even when the RXLVL interrupt is not enabled. 7589 */ 7590 #define SPI_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKERX_SHIFT)) & SPI_FIFOCFG_WAKERX_MASK) 7591 #define SPI_FIFOCFG_EMPTYTX_MASK (0x10000U) 7592 #define SPI_FIFOCFG_EMPTYTX_SHIFT (16U) 7593 /*! EMPTYTX - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied. 7594 */ 7595 #define SPI_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYTX_SHIFT)) & SPI_FIFOCFG_EMPTYTX_MASK) 7596 #define SPI_FIFOCFG_EMPTYRX_MASK (0x20000U) 7597 #define SPI_FIFOCFG_EMPTYRX_SHIFT (17U) 7598 /*! EMPTYRX - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied. 7599 */ 7600 #define SPI_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYRX_SHIFT)) & SPI_FIFOCFG_EMPTYRX_MASK) 7601 /*! @} */ 7602 7603 /*! @name FIFOSTAT - FIFO status register. */ 7604 /*! @{ */ 7605 #define SPI_FIFOSTAT_TXERR_MASK (0x1U) 7606 #define SPI_FIFOSTAT_TXERR_SHIFT (0U) 7607 /*! TXERR - TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow 7608 * caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is 7609 * needed. Cleared by writing a 1 to this bit. 7610 */ 7611 #define SPI_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXERR_SHIFT)) & SPI_FIFOSTAT_TXERR_MASK) 7612 #define SPI_FIFOSTAT_RXERR_MASK (0x2U) 7613 #define SPI_FIFOSTAT_RXERR_SHIFT (1U) 7614 /*! RXERR - RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA 7615 * not emptying the FIFO fast enough. Cleared by writing a 1 to this bit. 7616 */ 7617 #define SPI_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXERR_SHIFT)) & SPI_FIFOSTAT_RXERR_MASK) 7618 #define SPI_FIFOSTAT_PERINT_MASK (0x8U) 7619 #define SPI_FIFOSTAT_PERINT_SHIFT (3U) 7620 /*! PERINT - Peripheral interrupt. When 1, this indicates that the peripheral function has asserted 7621 * an interrupt. The details can be found by reading the peripheral's STAT register. 7622 */ 7623 #define SPI_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_PERINT_SHIFT)) & SPI_FIFOSTAT_PERINT_MASK) 7624 #define SPI_FIFOSTAT_TXEMPTY_MASK (0x10U) 7625 #define SPI_FIFOSTAT_TXEMPTY_SHIFT (4U) 7626 /*! TXEMPTY - Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data. 7627 */ 7628 #define SPI_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXEMPTY_SHIFT)) & SPI_FIFOSTAT_TXEMPTY_MASK) 7629 #define SPI_FIFOSTAT_TXNOTFULL_MASK (0x20U) 7630 #define SPI_FIFOSTAT_TXNOTFULL_SHIFT (5U) 7631 /*! TXNOTFULL - Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be 7632 * written. When 0, the transmit FIFO is full and another write would cause it to overflow. 7633 */ 7634 #define SPI_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXNOTFULL_SHIFT)) & SPI_FIFOSTAT_TXNOTFULL_MASK) 7635 #define SPI_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) 7636 #define SPI_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) 7637 /*! RXNOTEMPTY - Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty. 7638 */ 7639 #define SPI_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXNOTEMPTY_SHIFT)) & SPI_FIFOSTAT_RXNOTEMPTY_MASK) 7640 #define SPI_FIFOSTAT_RXFULL_MASK (0x80U) 7641 #define SPI_FIFOSTAT_RXFULL_SHIFT (7U) 7642 /*! RXFULL - Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to 7643 * prevent the peripheral from causing an overflow. 7644 */ 7645 #define SPI_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXFULL_SHIFT)) & SPI_FIFOSTAT_RXFULL_MASK) 7646 #define SPI_FIFOSTAT_TXLVL_MASK (0x1F00U) 7647 #define SPI_FIFOSTAT_TXLVL_SHIFT (8U) 7648 /*! TXLVL - Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY 7649 * and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at 7650 * the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be 7651 * 0. 7652 */ 7653 #define SPI_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXLVL_SHIFT)) & SPI_FIFOSTAT_TXLVL_MASK) 7654 #define SPI_FIFOSTAT_RXLVL_MASK (0x1F0000U) 7655 #define SPI_FIFOSTAT_RXLVL_SHIFT (16U) 7656 /*! RXLVL - Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and 7657 * RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the 7658 * point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be 7659 * 1. 7660 */ 7661 #define SPI_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXLVL_SHIFT)) & SPI_FIFOSTAT_RXLVL_MASK) 7662 /*! @} */ 7663 7664 /*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ 7665 /*! @{ */ 7666 #define SPI_FIFOTRIG_TXLVLENA_MASK (0x1U) 7667 #define SPI_FIFOTRIG_TXLVLENA_SHIFT (0U) 7668 /*! TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled 7669 * in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set. 7670 * 0b0..Transmit FIFO level does not generate a FIFO level trigger. 7671 * 0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. 7672 */ 7673 #define SPI_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVLENA_SHIFT)) & SPI_FIFOTRIG_TXLVLENA_MASK) 7674 #define SPI_FIFOTRIG_RXLVLENA_MASK (0x2U) 7675 #define SPI_FIFOTRIG_RXLVLENA_SHIFT (1U) 7676 /*! RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled 7677 * in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. 7678 * 0b0..Receive FIFO level does not generate a FIFO level trigger. 7679 * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. 7680 */ 7681 #define SPI_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVLENA_SHIFT)) & SPI_FIFOTRIG_RXLVLENA_MASK) 7682 #define SPI_FIFOTRIG_TXLVL_MASK (0xF00U) 7683 #define SPI_FIFOTRIG_TXLVL_SHIFT (8U) 7684 /*! TXLVL - Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled 7685 * to do so, the FIFO level can wake up the device just enough to perform DMA, then return to 7686 * the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO 7687 * becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX 7688 * FIFO level decreases to 15 entries (is no longer full). 7689 */ 7690 #define SPI_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVL_SHIFT)) & SPI_FIFOTRIG_TXLVL_MASK) 7691 #define SPI_FIFOTRIG_RXLVL_MASK (0xF0000U) 7692 #define SPI_FIFOTRIG_RXLVL_SHIFT (16U) 7693 /*! RXLVL - Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data 7694 * is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level 7695 * can wake up the device just enough to perform DMA, then return to the reduced power mode. See 7696 * Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no 7697 * longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX 7698 * FIFO has received 16 entries (has become full). 7699 */ 7700 #define SPI_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVL_SHIFT)) & SPI_FIFOTRIG_RXLVL_MASK) 7701 /*! @} */ 7702 7703 /*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ 7704 /*! @{ */ 7705 #define SPI_FIFOINTENSET_TXERR_MASK (0x1U) 7706 #define SPI_FIFOINTENSET_TXERR_SHIFT (0U) 7707 /*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. 7708 * 0b0..No interrupt will be generated for a transmit error. 7709 * 0b1..An interrupt will be generated when a transmit error occurs. 7710 */ 7711 #define SPI_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXERR_SHIFT)) & SPI_FIFOINTENSET_TXERR_MASK) 7712 #define SPI_FIFOINTENSET_RXERR_MASK (0x2U) 7713 #define SPI_FIFOINTENSET_RXERR_SHIFT (1U) 7714 /*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. 7715 * 0b0..No interrupt will be generated for a receive error. 7716 * 0b1..An interrupt will be generated when a receive error occurs. 7717 */ 7718 #define SPI_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXERR_SHIFT)) & SPI_FIFOINTENSET_RXERR_MASK) 7719 #define SPI_FIFOINTENSET_TXLVL_MASK (0x4U) 7720 #define SPI_FIFOINTENSET_TXLVL_SHIFT (2U) 7721 /*! TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level 7722 * specified by the TXLVL field in the FIFOTRIG register. 7723 * 0b0..No interrupt will be generated based on the TX FIFO level. 7724 * 0b1..If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases 7725 * to the level specified by TXLVL in the FIFOTRIG register. 7726 */ 7727 #define SPI_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXLVL_SHIFT)) & SPI_FIFOINTENSET_TXLVL_MASK) 7728 #define SPI_FIFOINTENSET_RXLVL_MASK (0x8U) 7729 #define SPI_FIFOINTENSET_RXLVL_SHIFT (3U) 7730 /*! RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level 7731 * specified by the TXLVL field in the FIFOTRIG register. 7732 * 0b0..No interrupt will be generated based on the RX FIFO level. 7733 * 0b1..If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level 7734 * increases to the level specified by RXLVL in the FIFOTRIG register. 7735 */ 7736 #define SPI_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXLVL_SHIFT)) & SPI_FIFOINTENSET_RXLVL_MASK) 7737 /*! @} */ 7738 7739 /*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ 7740 /*! @{ */ 7741 #define SPI_FIFOINTENCLR_TXERR_MASK (0x1U) 7742 #define SPI_FIFOINTENCLR_TXERR_SHIFT (0U) 7743 /*! TXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. 7744 */ 7745 #define SPI_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXERR_SHIFT)) & SPI_FIFOINTENCLR_TXERR_MASK) 7746 #define SPI_FIFOINTENCLR_RXERR_MASK (0x2U) 7747 #define SPI_FIFOINTENCLR_RXERR_SHIFT (1U) 7748 /*! RXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. 7749 */ 7750 #define SPI_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXERR_SHIFT)) & SPI_FIFOINTENCLR_RXERR_MASK) 7751 #define SPI_FIFOINTENCLR_TXLVL_MASK (0x4U) 7752 #define SPI_FIFOINTENCLR_TXLVL_SHIFT (2U) 7753 /*! TXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. 7754 */ 7755 #define SPI_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXLVL_SHIFT)) & SPI_FIFOINTENCLR_TXLVL_MASK) 7756 #define SPI_FIFOINTENCLR_RXLVL_MASK (0x8U) 7757 #define SPI_FIFOINTENCLR_RXLVL_SHIFT (3U) 7758 /*! RXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. 7759 */ 7760 #define SPI_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXLVL_SHIFT)) & SPI_FIFOINTENCLR_RXLVL_MASK) 7761 /*! @} */ 7762 7763 /*! @name FIFOINTSTAT - FIFO interrupt status register. */ 7764 /*! @{ */ 7765 #define SPI_FIFOINTSTAT_TXERR_MASK (0x1U) 7766 #define SPI_FIFOINTSTAT_TXERR_SHIFT (0U) 7767 /*! TXERR - TX FIFO error. 7768 */ 7769 #define SPI_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXERR_SHIFT)) & SPI_FIFOINTSTAT_TXERR_MASK) 7770 #define SPI_FIFOINTSTAT_RXERR_MASK (0x2U) 7771 #define SPI_FIFOINTSTAT_RXERR_SHIFT (1U) 7772 /*! RXERR - RX FIFO error. 7773 */ 7774 #define SPI_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXERR_SHIFT)) & SPI_FIFOINTSTAT_RXERR_MASK) 7775 #define SPI_FIFOINTSTAT_TXLVL_MASK (0x4U) 7776 #define SPI_FIFOINTSTAT_TXLVL_SHIFT (2U) 7777 /*! TXLVL - Transmit FIFO level interrupt. 7778 */ 7779 #define SPI_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXLVL_SHIFT)) & SPI_FIFOINTSTAT_TXLVL_MASK) 7780 #define SPI_FIFOINTSTAT_RXLVL_MASK (0x8U) 7781 #define SPI_FIFOINTSTAT_RXLVL_SHIFT (3U) 7782 /*! RXLVL - Receive FIFO level interrupt. 7783 */ 7784 #define SPI_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXLVL_SHIFT)) & SPI_FIFOINTSTAT_RXLVL_MASK) 7785 #define SPI_FIFOINTSTAT_PERINT_MASK (0x10U) 7786 #define SPI_FIFOINTSTAT_PERINT_SHIFT (4U) 7787 /*! PERINT - Peripheral interrupt. 7788 */ 7789 #define SPI_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_PERINT_SHIFT)) & SPI_FIFOINTSTAT_PERINT_MASK) 7790 /*! @} */ 7791 7792 /*! @name FIFOWR - FIFO write data. */ 7793 /*! @{ */ 7794 #define SPI_FIFOWR_TXDATA_MASK (0xFFFFU) 7795 #define SPI_FIFOWR_TXDATA_SHIFT (0U) 7796 /*! TXDATA - Transmit data to the FIFO. 7797 */ 7798 #define SPI_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXDATA_SHIFT)) & SPI_FIFOWR_TXDATA_MASK) 7799 #define SPI_FIFOWR_TXSSEL0_N_MASK (0x10000U) 7800 #define SPI_FIFOWR_TXSSEL0_N_SHIFT (16U) 7801 /*! TXSSEL0_N - Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default. 7802 * 0b0..SSEL0 asserted. 7803 * 0b1..SSEL0 not asserted. 7804 */ 7805 #define SPI_FIFOWR_TXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL0_N_SHIFT)) & SPI_FIFOWR_TXSSEL0_N_MASK) 7806 #define SPI_FIFOWR_TXSSEL1_N_MASK (0x20000U) 7807 #define SPI_FIFOWR_TXSSEL1_N_SHIFT (17U) 7808 /*! TXSSEL1_N - Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default. 7809 * 0b0..SSEL1 asserted. 7810 * 0b1..SSEL1 not asserted. 7811 */ 7812 #define SPI_FIFOWR_TXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL1_N_SHIFT)) & SPI_FIFOWR_TXSSEL1_N_MASK) 7813 #define SPI_FIFOWR_TXSSEL2_N_MASK (0x40000U) 7814 #define SPI_FIFOWR_TXSSEL2_N_SHIFT (18U) 7815 /*! TXSSEL2_N - Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default. 7816 * 0b0..SSEL2 asserted. 7817 * 0b1..SSEL2 not asserted. 7818 */ 7819 #define SPI_FIFOWR_TXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL2_N_SHIFT)) & SPI_FIFOWR_TXSSEL2_N_MASK) 7820 #define SPI_FIFOWR_TXSSEL3_N_MASK (0x80000U) 7821 #define SPI_FIFOWR_TXSSEL3_N_SHIFT (19U) 7822 /*! TXSSEL3_N - Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default. 7823 * 0b0..SSEL3 asserted. 7824 * 0b1..SSEL3 not asserted. 7825 */ 7826 #define SPI_FIFOWR_TXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL3_N_SHIFT)) & SPI_FIFOWR_TXSSEL3_N_MASK) 7827 #define SPI_FIFOWR_EOT_MASK (0x100000U) 7828 #define SPI_FIFOWR_EOT_SHIFT (20U) 7829 /*! EOT - End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain 7830 * so far at least the time specified by the Transfer_delay value in the DLY register. 7831 * 0b0..SSEL not deasserted. This piece of data is not treated as the end of a transfer. SSEL will not be deasserted at the end of this data. 7832 * 0b1..SSEL deasserted. This piece of data is treated as the end of a transfer. SSEL will be deasserted at the end of this piece of data. 7833 */ 7834 #define SPI_FIFOWR_EOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOT_SHIFT)) & SPI_FIFOWR_EOT_MASK) 7835 #define SPI_FIFOWR_EOF_MASK (0x200000U) 7836 #define SPI_FIFOWR_EOF_SHIFT (21U) 7837 /*! EOF - End of frame. Between frames, a delay may be inserted, as defined by the Frame_delay value 7838 * in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay 7839 * value = 0. This control can be used as part of the support for frame lengths greater than 16 7840 * bits. 7841 * 0b0..Data not EOF. This piece of data transmitted is not treated as the end of a frame. 7842 * 0b1..Data EOF. This piece of data is treated as the end of a frame, causing the Frame_delay time to be 7843 * inserted before subsequent data is transmitted. 7844 */ 7845 #define SPI_FIFOWR_EOF(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOF_SHIFT)) & SPI_FIFOWR_EOF_MASK) 7846 #define SPI_FIFOWR_RXIGNORE_MASK (0x400000U) 7847 #define SPI_FIFOWR_RXIGNORE_SHIFT (22U) 7848 /*! RXIGNORE - Receive Ignore. This allows data to be transmitted using the SPI without the need to 7849 * read unneeded data from the receiver. Setting this bit simplifies the transmit process and can 7850 * be used with the DMA. 7851 * 0b0..Read received data. Received data must be read in order to allow transmission to progress. SPI transmit 7852 * will halt when the receive data FIFO is full. In slave mode, an overrun error will occur if received data 7853 * is not read before new data is received. 7854 * 0b1..Ignore received data. Received data is ignored, allowing transmission without reading unneeded received 7855 * data. No receiver flags are generated. 7856 */ 7857 #define SPI_FIFOWR_RXIGNORE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_RXIGNORE_SHIFT)) & SPI_FIFOWR_RXIGNORE_MASK) 7858 #define SPI_FIFOWR_LEN_MASK (0xF000000U) 7859 #define SPI_FIFOWR_LEN_SHIFT (24U) 7860 /*! LEN - Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths 7861 * greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 7862 * 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5 bits in length. 0xF = Data 7863 * transfer is 16 bits in length. 7864 */ 7865 #define SPI_FIFOWR_LEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_LEN_SHIFT)) & SPI_FIFOWR_LEN_MASK) 7866 /*! @} */ 7867 7868 /*! @name FIFORD - FIFO read data. */ 7869 /*! @{ */ 7870 #define SPI_FIFORD_RXDATA_MASK (0xFFFFU) 7871 #define SPI_FIFORD_RXDATA_SHIFT (0U) 7872 /*! RXDATA - Received data from the FIFO. 7873 */ 7874 #define SPI_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXDATA_SHIFT)) & SPI_FIFORD_RXDATA_MASK) 7875 #define SPI_FIFORD_RXSSEL0_N_MASK (0x10000U) 7876 #define SPI_FIFORD_RXSSEL0_N_SHIFT (16U) 7877 /*! RXSSEL0_N - Slave Select for receive. This field allows the state of the SSEL0 pin to be saved 7878 * along with received data. The value will reflect the SSEL0 pin for both master and slave 7879 * operation. A zero indicates that a slave select is active. The actual polarity of each slave select 7880 * pin is configured by the related SPOL bit in CFG. 7881 */ 7882 #define SPI_FIFORD_RXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL0_N_SHIFT)) & SPI_FIFORD_RXSSEL0_N_MASK) 7883 #define SPI_FIFORD_RXSSEL1_N_MASK (0x20000U) 7884 #define SPI_FIFORD_RXSSEL1_N_SHIFT (17U) 7885 /*! RXSSEL1_N - Slave Select for receive. This field allows the state of the SSEL1 pin to be saved 7886 * along with received data. The value will reflect the SSEL1 pin for both master and slave 7887 * operation. A zero indicates that a slave select is active. The actual polarity of each slave select 7888 * pin is configured by the related SPOL bit in CFG. 7889 */ 7890 #define SPI_FIFORD_RXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL1_N_SHIFT)) & SPI_FIFORD_RXSSEL1_N_MASK) 7891 #define SPI_FIFORD_RXSSEL2_N_MASK (0x40000U) 7892 #define SPI_FIFORD_RXSSEL2_N_SHIFT (18U) 7893 /*! RXSSEL2_N - Slave Select for receive. This field allows the state of the SSEL2 pin to be saved 7894 * along with received data. The value will reflect the SSEL2 pin for both master and slave 7895 * operation. A zero indicates that a slave select is active. The actual polarity of each slave select 7896 * pin is configured by the related SPOL bit in CFG. 7897 */ 7898 #define SPI_FIFORD_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL2_N_SHIFT)) & SPI_FIFORD_RXSSEL2_N_MASK) 7899 #define SPI_FIFORD_RXSSEL3_N_MASK (0x80000U) 7900 #define SPI_FIFORD_RXSSEL3_N_SHIFT (19U) 7901 /*! RXSSEL3_N - Slave Select for receive. This field allows the state of the SSEL3 pin to be saved 7902 * along with received data. The value will reflect the SSEL3 pin for both master and slave 7903 * operation. A zero indicates that a slave select is active. The actual polarity of each slave select 7904 * pin is configured by the related SPOL bit in CFG. 7905 */ 7906 #define SPI_FIFORD_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL3_N_SHIFT)) & SPI_FIFORD_RXSSEL3_N_MASK) 7907 #define SPI_FIFORD_SOT_MASK (0x100000U) 7908 #define SPI_FIFORD_SOT_SHIFT (20U) 7909 /*! SOT - Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went 7910 * from deasserted to asserted (i.e., any previous transfer has ended). This information can be 7911 * used to identify the first piece of data in cases where the transfer length is greater than 16 7912 * bits. 7913 */ 7914 #define SPI_FIFORD_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_SOT_SHIFT)) & SPI_FIFORD_SOT_MASK) 7915 /*! @} */ 7916 7917 /*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ 7918 /*! @{ */ 7919 #define SPI_FIFORDNOPOP_RXDATA_MASK (0xFFFFU) 7920 #define SPI_FIFORDNOPOP_RXDATA_SHIFT (0U) 7921 /*! RXDATA - Received data from the FIFO. 7922 */ 7923 #define SPI_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXDATA_SHIFT)) & SPI_FIFORDNOPOP_RXDATA_MASK) 7924 #define SPI_FIFORDNOPOP_RXSSEL0_N_MASK (0x10000U) 7925 #define SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT (16U) 7926 /*! RXSSEL0_N - Slave Select for receive. 7927 */ 7928 #define SPI_FIFORDNOPOP_RXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL0_N_MASK) 7929 #define SPI_FIFORDNOPOP_RXSSEL1_N_MASK (0x20000U) 7930 #define SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT (17U) 7931 /*! RXSSEL1_N - Slave Select for receive. 7932 */ 7933 #define SPI_FIFORDNOPOP_RXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL1_N_MASK) 7934 #define SPI_FIFORDNOPOP_RXSSEL2_N_MASK (0x40000U) 7935 #define SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT (18U) 7936 /*! RXSSEL2_N - Slave Select for receive. 7937 */ 7938 #define SPI_FIFORDNOPOP_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL2_N_MASK) 7939 #define SPI_FIFORDNOPOP_RXSSEL3_N_MASK (0x80000U) 7940 #define SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT (19U) 7941 /*! RXSSEL3_N - Slave Select for receive. 7942 */ 7943 #define SPI_FIFORDNOPOP_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL3_N_MASK) 7944 #define SPI_FIFORDNOPOP_SOT_MASK (0x100000U) 7945 #define SPI_FIFORDNOPOP_SOT_SHIFT (20U) 7946 /*! SOT - Start of transfer flag. 7947 */ 7948 #define SPI_FIFORDNOPOP_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_SOT_SHIFT)) & SPI_FIFORDNOPOP_SOT_MASK) 7949 /*! @} */ 7950 7951 7952 /*! 7953 * @} 7954 */ /* end of group SPI_Register_Masks */ 7955 7956 7957 /* SPI - Peripheral instance base addresses */ 7958 /** Peripheral SPI0 base address */ 7959 #define SPI0_BASE (0x40086000u) 7960 /** Peripheral SPI0 base pointer */ 7961 #define SPI0 ((SPI_Type *)SPI0_BASE) 7962 /** Peripheral SPI1 base address */ 7963 #define SPI1_BASE (0x40087000u) 7964 /** Peripheral SPI1 base pointer */ 7965 #define SPI1 ((SPI_Type *)SPI1_BASE) 7966 /** Peripheral SPI2 base address */ 7967 #define SPI2_BASE (0x40088000u) 7968 /** Peripheral SPI2 base pointer */ 7969 #define SPI2 ((SPI_Type *)SPI2_BASE) 7970 /** Peripheral SPI3 base address */ 7971 #define SPI3_BASE (0x40089000u) 7972 /** Peripheral SPI3 base pointer */ 7973 #define SPI3 ((SPI_Type *)SPI3_BASE) 7974 /** Peripheral SPI4 base address */ 7975 #define SPI4_BASE (0x4008A000u) 7976 /** Peripheral SPI4 base pointer */ 7977 #define SPI4 ((SPI_Type *)SPI4_BASE) 7978 /** Peripheral SPI5 base address */ 7979 #define SPI5_BASE (0x40096000u) 7980 /** Peripheral SPI5 base pointer */ 7981 #define SPI5 ((SPI_Type *)SPI5_BASE) 7982 /** Peripheral SPI6 base address */ 7983 #define SPI6_BASE (0x40097000u) 7984 /** Peripheral SPI6 base pointer */ 7985 #define SPI6 ((SPI_Type *)SPI6_BASE) 7986 /** Peripheral SPI7 base address */ 7987 #define SPI7_BASE (0x40098000u) 7988 /** Peripheral SPI7 base pointer */ 7989 #define SPI7 ((SPI_Type *)SPI7_BASE) 7990 /** Array initializer of SPI peripheral base addresses */ 7991 #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI2_BASE, SPI3_BASE, SPI4_BASE, SPI5_BASE, SPI6_BASE, SPI7_BASE } 7992 /** Array initializer of SPI peripheral base pointers */ 7993 #define SPI_BASE_PTRS { SPI0, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SPI7 } 7994 /** Interrupt vectors for the SPI peripheral type */ 7995 #define SPI_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } 7996 7997 /*! 7998 * @} 7999 */ /* end of group SPI_Peripheral_Access_Layer */ 8000 8001 8002 /* ---------------------------------------------------------------------------- 8003 -- SPIFI Peripheral Access Layer 8004 ---------------------------------------------------------------------------- */ 8005 8006 /*! 8007 * @addtogroup SPIFI_Peripheral_Access_Layer SPIFI Peripheral Access Layer 8008 * @{ 8009 */ 8010 8011 /** SPIFI - Register Layout Typedef */ 8012 typedef struct { 8013 __IO uint32_t CTRL; /**< SPIFI control register, offset: 0x0 */ 8014 __IO uint32_t CMD; /**< SPIFI command register, offset: 0x4 */ 8015 __IO uint32_t ADDR; /**< SPIFI address register, offset: 0x8 */ 8016 __IO uint32_t IDATA; /**< SPIFI intermediate data register, offset: 0xC */ 8017 __IO uint32_t CLIMIT; /**< SPIFI limit register, offset: 0x10 */ 8018 __IO uint32_t DATA; /**< SPIFI data register, offset: 0x14 */ 8019 __IO uint32_t MCMD; /**< SPIFI memory command register, offset: 0x18 */ 8020 __IO uint32_t STAT; /**< SPIFI status register, offset: 0x1C */ 8021 } SPIFI_Type; 8022 8023 /* ---------------------------------------------------------------------------- 8024 -- SPIFI Register Masks 8025 ---------------------------------------------------------------------------- */ 8026 8027 /*! 8028 * @addtogroup SPIFI_Register_Masks SPIFI Register Masks 8029 * @{ 8030 */ 8031 8032 /*! @name CTRL - SPIFI control register */ 8033 /*! @{ */ 8034 #define SPIFI_CTRL_TIMEOUT_MASK (0xFFFFU) 8035 #define SPIFI_CTRL_TIMEOUT_SHIFT (0U) 8036 /*! TIMEOUT - This field contains the number of serial clock periods without the processor reading 8037 * data in memory mode, which will cause the SPIFI hardware to terminate the command by driving 8038 * the CS pin high and negating the CMD bit in the Status register. (This allows the flash memory 8039 * to enter a lower-power state.) If the processor reads data from the flash region after a 8040 * time-out, the command in the Memory Command Register is issued again. 8041 */ 8042 #define SPIFI_CTRL_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_TIMEOUT_SHIFT)) & SPIFI_CTRL_TIMEOUT_MASK) 8043 #define SPIFI_CTRL_CSHIGH_MASK (0xF0000U) 8044 #define SPIFI_CTRL_CSHIGH_SHIFT (16U) 8045 /*! CSHIGH - This field controls the minimum CS high time, expressed as a number of serial clock periods minus one. 8046 */ 8047 #define SPIFI_CTRL_CSHIGH(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_CSHIGH_SHIFT)) & SPIFI_CTRL_CSHIGH_MASK) 8048 #define SPIFI_CTRL_D_PRFTCH_DIS_MASK (0x200000U) 8049 #define SPIFI_CTRL_D_PRFTCH_DIS_SHIFT (21U) 8050 /*! D_PRFTCH_DIS - This bit allows conditioning of memory mode prefetches based on the AHB HPROT 8051 * (instruction/data) access information. A 1 in this register means that the SPIFI will not attempt 8052 * a speculative prefetch when it encounters data accesses. 8053 */ 8054 #define SPIFI_CTRL_D_PRFTCH_DIS(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_D_PRFTCH_DIS_SHIFT)) & SPIFI_CTRL_D_PRFTCH_DIS_MASK) 8055 #define SPIFI_CTRL_INTEN_MASK (0x400000U) 8056 #define SPIFI_CTRL_INTEN_SHIFT (22U) 8057 /*! INTEN - If this bit is 1 when a command ends, the SPIFI will assert its interrupt request 8058 * output. See INTRQ in the status register for further details. 8059 */ 8060 #define SPIFI_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_INTEN_SHIFT)) & SPIFI_CTRL_INTEN_MASK) 8061 #define SPIFI_CTRL_MODE3_MASK (0x800000U) 8062 #define SPIFI_CTRL_MODE3_SHIFT (23U) 8063 /*! MODE3 - SPI Mode 3 select. 8064 * 0b0..SCK LOW. The SPIFI drives SCK low after the rising edge at which the last bit of each command is 8065 * captured, and keeps it low while CS is HIGH. 8066 * 0b1..SCK HIGH. the SPIFI keeps SCK high after the rising edge for the last bit of each command and while CS is 8067 * HIGH, and drives it low after it drives CS LOW. (Known serial flash devices can handle either mode, but 8068 * some devices may require a particular mode for proper operation.) MODE3, RFCLK, and FBCLK should not all be 8069 * 1, because in this case there is no final falling edge on SCK on which to sample the last data bit of the 8070 * frame. 8071 */ 8072 #define SPIFI_CTRL_MODE3(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_MODE3_SHIFT)) & SPIFI_CTRL_MODE3_MASK) 8073 #define SPIFI_CTRL_PRFTCH_DIS_MASK (0x8000000U) 8074 #define SPIFI_CTRL_PRFTCH_DIS_SHIFT (27U) 8075 /*! PRFTCH_DIS - Cache prefetching enable. The SPIFI includes an internal cache. A 1 in this bit disables prefetching of cache lines. 8076 * 0b0..Enable. Cache prefetching enabled. 8077 * 0b1..Disable. Disables prefetching of cache lines. 8078 */ 8079 #define SPIFI_CTRL_PRFTCH_DIS(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_PRFTCH_DIS_SHIFT)) & SPIFI_CTRL_PRFTCH_DIS_MASK) 8080 #define SPIFI_CTRL_DUAL_MASK (0x10000000U) 8081 #define SPIFI_CTRL_DUAL_SHIFT (28U) 8082 /*! DUAL - Select dual protocol. 8083 * 0b0..Quad protocol. This protocol uses IO3:0. 8084 * 0b1..Dual protocol. This protocol uses IO1:0. 8085 */ 8086 #define SPIFI_CTRL_DUAL(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_DUAL_SHIFT)) & SPIFI_CTRL_DUAL_MASK) 8087 #define SPIFI_CTRL_RFCLK_MASK (0x20000000U) 8088 #define SPIFI_CTRL_RFCLK_SHIFT (29U) 8089 /*! RFCLK - Select active clock edge for input data. 8090 * 0b0..Rising edge. Read data is sampled on rising edges on the clock, as in classic SPI operation. 8091 * 0b1..Falling edge. Read data is sampled on falling edges of the clock, allowing a full serial clock of of time 8092 * in order to maximize the serial clock frequency. MODE3, RFCLK, and FBCLK should not all be 1, because in 8093 * this case there is no final falling edge on SCK on which to sample the last data bit of the frame. 8094 */ 8095 #define SPIFI_CTRL_RFCLK(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_RFCLK_SHIFT)) & SPIFI_CTRL_RFCLK_MASK) 8096 #define SPIFI_CTRL_FBCLK_MASK (0x40000000U) 8097 #define SPIFI_CTRL_FBCLK_SHIFT (30U) 8098 /*! FBCLK - Feedback clock select. 8099 * 0b0..Internal clock. The SPIFI samples read data using an internal clock. 8100 * 0b1..Feedback clock. Read data is sampled using a feedback clock from the SCK pin. This allows slightly more 8101 * time for each received bit. MODE3, RFCLK, and FBCLK should not all be 1, because in this case there is no 8102 * final falling edge on SCK on which to sample the last data bit of the frame. 8103 */ 8104 #define SPIFI_CTRL_FBCLK(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_FBCLK_SHIFT)) & SPIFI_CTRL_FBCLK_MASK) 8105 #define SPIFI_CTRL_DMAEN_MASK (0x80000000U) 8106 #define SPIFI_CTRL_DMAEN_SHIFT (31U) 8107 /*! DMAEN - A 1 in this bit enables the DMA Request output from the SPIFI. Set this bit only when a 8108 * DMA channel is used to transfer data in peripheral mode. Do not set this bit when a DMA 8109 * channel is used for memory-to-memory transfers from the SPIFI memory area. DMAEN should only be used 8110 * in Command mode. 8111 */ 8112 #define SPIFI_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_DMAEN_SHIFT)) & SPIFI_CTRL_DMAEN_MASK) 8113 /*! @} */ 8114 8115 /*! @name CMD - SPIFI command register */ 8116 /*! @{ */ 8117 #define SPIFI_CMD_DATALEN_MASK (0x3FFFU) 8118 #define SPIFI_CMD_DATALEN_SHIFT (0U) 8119 /*! DATALEN - Except when the POLL bit in this register is 1, this field controls how many data 8120 * bytes are in the command. 0 indicates that the command does not contain a data field. 8121 */ 8122 #define SPIFI_CMD_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_DATALEN_SHIFT)) & SPIFI_CMD_DATALEN_MASK) 8123 #define SPIFI_CMD_POLL_MASK (0x4000U) 8124 #define SPIFI_CMD_POLL_SHIFT (14U) 8125 /*! POLL - This bit should be written as 1 only with an opcode that a) contains an input data field, 8126 * and b) causes the serial flash device to return byte status repetitively (e.g., a Read Status 8127 * command). When this bit is 1, the SPIFI hardware continues to read bytes until the test 8128 * specified by the DATALEN field is met. The hardware tests the bit in each status byte selected by 8129 * DATALEN bits 2:0, until a bit is found that is equal to DATALEN bit 3. When the test succeeds, 8130 * the SPIFI captures the byte that meets this test so that it can be read from the Data 8131 * Register, and terminates the command by raising CS. The end-of-command interrupt can be enabled to 8132 * inform software when this occurs 8133 */ 8134 #define SPIFI_CMD_POLL(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_POLL_SHIFT)) & SPIFI_CMD_POLL_MASK) 8135 #define SPIFI_CMD_DOUT_MASK (0x8000U) 8136 #define SPIFI_CMD_DOUT_SHIFT (15U) 8137 /*! DOUT - If the DATALEN field is not zero, this bit controls the direction of the data: 8138 * 0b0..Input from serial flash. 8139 * 0b1..Output to serial flash. 8140 */ 8141 #define SPIFI_CMD_DOUT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_DOUT_SHIFT)) & SPIFI_CMD_DOUT_MASK) 8142 #define SPIFI_CMD_INTLEN_MASK (0x70000U) 8143 #define SPIFI_CMD_INTLEN_SHIFT (16U) 8144 /*! INTLEN - This field controls how many intermediate bytes precede the data. (Each such byte may 8145 * require 8 or 2 SCK cycles, depending on whether the intermediate field is in serial, 2-bit, or 8146 * 4-bit format.) Intermediate bytes are output by the SPIFI, and include post-address control 8147 * information, dummy and delay bytes. See the description of the Intermediate Data register for 8148 * the contents of such bytes. 8149 */ 8150 #define SPIFI_CMD_INTLEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_INTLEN_SHIFT)) & SPIFI_CMD_INTLEN_MASK) 8151 #define SPIFI_CMD_FIELDFORM_MASK (0x180000U) 8152 #define SPIFI_CMD_FIELDFORM_SHIFT (19U) 8153 /*! FIELDFORM - This field controls how the fields of the command are sent. 8154 * 0b00..All serial. All fields of the command are serial. 8155 * 0b01..Quad/dual data. Data field is quad/dual, other fields are serial. 8156 * 0b10..Serial opcode. Opcode field is serial. Other fields are quad/dual. 8157 * 0b11..All quad/dual. All fields of the command are in quad/dual format. 8158 */ 8159 #define SPIFI_CMD_FIELDFORM(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_FIELDFORM_SHIFT)) & SPIFI_CMD_FIELDFORM_MASK) 8160 #define SPIFI_CMD_FRAMEFORM_MASK (0xE00000U) 8161 #define SPIFI_CMD_FRAMEFORM_SHIFT (21U) 8162 /*! FRAMEFORM - This field controls the opcode and address fields. 8163 * 0b000..Reserved. 8164 * 0b001..Opcode. Opcode only, no address. 8165 * 0b010..Opcode one byte. Opcode, least significant byte of address. 8166 * 0b011..Opcode two bytes. Opcode, two least significant bytes of address. 8167 * 0b100..Opcode three bytes. Opcode, three least significant bytes of address. 8168 * 0b101..Opcode four bytes. Opcode, 4 bytes of address. 8169 * 0b110..No opcode three bytes. No opcode, 3 least significant bytes of address. 8170 * 0b111..No opcode four bytes. No opcode, 4 bytes of address. 8171 */ 8172 #define SPIFI_CMD_FRAMEFORM(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_FRAMEFORM_SHIFT)) & SPIFI_CMD_FRAMEFORM_MASK) 8173 #define SPIFI_CMD_OPCODE_MASK (0xFF000000U) 8174 #define SPIFI_CMD_OPCODE_SHIFT (24U) 8175 /*! OPCODE - The opcode of the command (not used for some FRAMEFORM values). 8176 */ 8177 #define SPIFI_CMD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_OPCODE_SHIFT)) & SPIFI_CMD_OPCODE_MASK) 8178 /*! @} */ 8179 8180 /*! @name ADDR - SPIFI address register */ 8181 /*! @{ */ 8182 #define SPIFI_ADDR_ADDRESS_MASK (0xFFFFFFFFU) 8183 #define SPIFI_ADDR_ADDRESS_SHIFT (0U) 8184 /*! ADDRESS - Address. 8185 */ 8186 #define SPIFI_ADDR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_ADDR_ADDRESS_SHIFT)) & SPIFI_ADDR_ADDRESS_MASK) 8187 /*! @} */ 8188 8189 /*! @name IDATA - SPIFI intermediate data register */ 8190 /*! @{ */ 8191 #define SPIFI_IDATA_IDATA_MASK (0xFFFFFFFFU) 8192 #define SPIFI_IDATA_IDATA_SHIFT (0U) 8193 /*! IDATA - Value of intermediate bytes. 8194 */ 8195 #define SPIFI_IDATA_IDATA(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_IDATA_IDATA_SHIFT)) & SPIFI_IDATA_IDATA_MASK) 8196 /*! @} */ 8197 8198 /*! @name CLIMIT - SPIFI limit register */ 8199 /*! @{ */ 8200 #define SPIFI_CLIMIT_CLIMIT_MASK (0xFFFFFFFFU) 8201 #define SPIFI_CLIMIT_CLIMIT_SHIFT (0U) 8202 /*! CLIMIT - Zero-based upper limit of cacheable memory 8203 */ 8204 #define SPIFI_CLIMIT_CLIMIT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CLIMIT_CLIMIT_SHIFT)) & SPIFI_CLIMIT_CLIMIT_MASK) 8205 /*! @} */ 8206 8207 /*! @name DATA - SPIFI data register */ 8208 /*! @{ */ 8209 #define SPIFI_DATA_DATA_MASK (0xFFFFFFFFU) 8210 #define SPIFI_DATA_DATA_SHIFT (0U) 8211 /*! DATA - Input or output data 8212 */ 8213 #define SPIFI_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_DATA_DATA_SHIFT)) & SPIFI_DATA_DATA_MASK) 8214 /*! @} */ 8215 8216 /*! @name MCMD - SPIFI memory command register */ 8217 /*! @{ */ 8218 #define SPIFI_MCMD_POLL_MASK (0x4000U) 8219 #define SPIFI_MCMD_POLL_SHIFT (14U) 8220 /*! POLL - This bit should be written as 0. 8221 */ 8222 #define SPIFI_MCMD_POLL(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_POLL_SHIFT)) & SPIFI_MCMD_POLL_MASK) 8223 #define SPIFI_MCMD_DOUT_MASK (0x8000U) 8224 #define SPIFI_MCMD_DOUT_SHIFT (15U) 8225 /*! DOUT - This bit should be written as 0. 8226 */ 8227 #define SPIFI_MCMD_DOUT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_DOUT_SHIFT)) & SPIFI_MCMD_DOUT_MASK) 8228 #define SPIFI_MCMD_INTLEN_MASK (0x70000U) 8229 #define SPIFI_MCMD_INTLEN_SHIFT (16U) 8230 /*! INTLEN - This field controls how many intermediate bytes precede the data. (Each such byte may 8231 * require 8 or 2 SCK cycles, depending on whether the intermediate field is in serial, 2-bit, or 8232 * 4-bit format.) Intermediate bytes are output by the SPIFI, and include post-address control 8233 * information, dummy and delay bytes. See the description of the Intermediate Data register for 8234 * the contents of such bytes. 8235 */ 8236 #define SPIFI_MCMD_INTLEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_INTLEN_SHIFT)) & SPIFI_MCMD_INTLEN_MASK) 8237 #define SPIFI_MCMD_FIELDFORM_MASK (0x180000U) 8238 #define SPIFI_MCMD_FIELDFORM_SHIFT (19U) 8239 /*! FIELDFORM - This field controls how the fields of the command are sent. 8240 * 0b00..All serial. All fields of the command are serial. 8241 * 0b01..Quad/dual data. Data field is quad/dual, other fields are serial. 8242 * 0b10..Serial opcode. Opcode field is serial. Other fields are quad/dual. 8243 * 0b11..All quad/dual. All fields of the command are in quad/dual format. 8244 */ 8245 #define SPIFI_MCMD_FIELDFORM(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_FIELDFORM_SHIFT)) & SPIFI_MCMD_FIELDFORM_MASK) 8246 #define SPIFI_MCMD_FRAMEFORM_MASK (0xE00000U) 8247 #define SPIFI_MCMD_FRAMEFORM_SHIFT (21U) 8248 /*! FRAMEFORM - This field controls the opcode and address fields. 8249 * 0b000..Reserved. 8250 * 0b001..Opcode. Opcode only, no address. 8251 * 0b010..Opcode one byte. Opcode, least-significant byte of address. 8252 * 0b011..Opcode two bytes. Opcode, 2 least-significant bytes of address. 8253 * 0b100..Opcode three bytes. Opcode, 3 least-significant bytes of address. 8254 * 0b101..Opcode four bytes. Opcode, 4 bytes of address. 8255 * 0b110..No opcode three bytes. No opcode, 3 least-significant bytes of address. 8256 * 0b111..No opcode, 4 bytes of address. 8257 */ 8258 #define SPIFI_MCMD_FRAMEFORM(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_FRAMEFORM_SHIFT)) & SPIFI_MCMD_FRAMEFORM_MASK) 8259 #define SPIFI_MCMD_OPCODE_MASK (0xFF000000U) 8260 #define SPIFI_MCMD_OPCODE_SHIFT (24U) 8261 /*! OPCODE - The opcode of the command (not used for some FRAMEFORM values). 8262 */ 8263 #define SPIFI_MCMD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_OPCODE_SHIFT)) & SPIFI_MCMD_OPCODE_MASK) 8264 /*! @} */ 8265 8266 /*! @name STAT - SPIFI status register */ 8267 /*! @{ */ 8268 #define SPIFI_STAT_MCINIT_MASK (0x1U) 8269 #define SPIFI_STAT_MCINIT_SHIFT (0U) 8270 /*! MCINIT - This bit is set when software successfully writes the Memory Command register, and is 8271 * cleared by Reset or by writing a 1 to the RESET bit in this register. 8272 */ 8273 #define SPIFI_STAT_MCINIT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_MCINIT_SHIFT)) & SPIFI_STAT_MCINIT_MASK) 8274 #define SPIFI_STAT_CMD_MASK (0x2U) 8275 #define SPIFI_STAT_CMD_SHIFT (1U) 8276 /*! CMD - This bit is 1 when the Command register is written. It is cleared by a hardware reset, a 8277 * write to the RESET bit in this register, or the deassertion of CS which indicates that the 8278 * command has completed communication with the SPI Flash. 8279 */ 8280 #define SPIFI_STAT_CMD(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_CMD_SHIFT)) & SPIFI_STAT_CMD_MASK) 8281 #define SPIFI_STAT_RESET_MASK (0x10U) 8282 #define SPIFI_STAT_RESET_SHIFT (4U) 8283 /*! RESET - Write a 1 to this bit to abort a current command or memory mode. This bit is cleared 8284 * when the hardware is ready for a new command to be written to the Command register. 8285 */ 8286 #define SPIFI_STAT_RESET(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_RESET_SHIFT)) & SPIFI_STAT_RESET_MASK) 8287 #define SPIFI_STAT_INTRQ_MASK (0x20U) 8288 #define SPIFI_STAT_INTRQ_SHIFT (5U) 8289 /*! INTRQ - This bit reflects the SPIFI interrupt request. Write a 1 to this bit to clear it. This 8290 * bit is set when a CMD was previously 1 and has been cleared due to the deassertion of CS. 8291 */ 8292 #define SPIFI_STAT_INTRQ(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_INTRQ_SHIFT)) & SPIFI_STAT_INTRQ_MASK) 8293 #define SPIFI_STAT_VERSION_MASK (0xFF000000U) 8294 #define SPIFI_STAT_VERSION_SHIFT (24U) 8295 /*! VERSION - - 8296 */ 8297 #define SPIFI_STAT_VERSION(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_VERSION_SHIFT)) & SPIFI_STAT_VERSION_MASK) 8298 /*! @} */ 8299 8300 8301 /*! 8302 * @} 8303 */ /* end of group SPIFI_Register_Masks */ 8304 8305 8306 /* SPIFI - Peripheral instance base addresses */ 8307 /** Peripheral SPIFI0 base address */ 8308 #define SPIFI0_BASE (0x40080000u) 8309 /** Peripheral SPIFI0 base pointer */ 8310 #define SPIFI0 ((SPIFI_Type *)SPIFI0_BASE) 8311 /** Array initializer of SPIFI peripheral base addresses */ 8312 #define SPIFI_BASE_ADDRS { SPIFI0_BASE } 8313 /** Array initializer of SPIFI peripheral base pointers */ 8314 #define SPIFI_BASE_PTRS { SPIFI0 } 8315 /** Interrupt vectors for the SPIFI peripheral type */ 8316 #define SPIFI_IRQS { SPIFI0_IRQn } 8317 8318 /*! 8319 * @} 8320 */ /* end of group SPIFI_Peripheral_Access_Layer */ 8321 8322 8323 /* ---------------------------------------------------------------------------- 8324 -- SYSCON Peripheral Access Layer 8325 ---------------------------------------------------------------------------- */ 8326 8327 /*! 8328 * @addtogroup SYSCON_Peripheral_Access_Layer SYSCON Peripheral Access Layer 8329 * @{ 8330 */ 8331 8332 /** SYSCON - Register Layout Typedef */ 8333 typedef struct { 8334 uint32_t SYSMEMREMAP; /**< System Remap register, offset: 0x0 */ 8335 uint8_t RESERVED_0[12]; 8336 __IO uint32_t AHBMATPRIO; /**< AHB multilayer matrix priority control, offset: 0x10 */ 8337 uint8_t RESERVED_1[44]; 8338 __IO uint32_t SYSTCKCAL; /**< System tick counter calibration, offset: 0x40 */ 8339 uint8_t RESERVED_2[4]; 8340 __IO uint32_t NMISRC; /**< NMI Source Select, offset: 0x48 */ 8341 __IO uint32_t ASYNCAPBCTRL; /**< Asynchronous APB Control, offset: 0x4C */ 8342 uint8_t RESERVED_3[112]; 8343 __I uint32_t PIOPORCAP[2]; /**< POR captured value of port n, array offset: 0xC0, array step: 0x4 */ 8344 uint8_t RESERVED_4[8]; 8345 __I uint32_t PIORESCAP[2]; /**< Reset captured value of port n, array offset: 0xD0, array step: 0x4 */ 8346 uint8_t RESERVED_5[40]; 8347 __IO uint32_t PRESETCTRL[2]; /**< Peripheral reset control n, array offset: 0x100, array step: 0x4 */ 8348 uint8_t RESERVED_6[24]; 8349 __O uint32_t PRESETCTRLSET[2]; /**< Set bits in PRESETCTRLn, array offset: 0x120, array step: 0x4 */ 8350 uint8_t RESERVED_7[24]; 8351 __O uint32_t PRESETCTRLCLR[2]; /**< Clear bits in PRESETCTRLn, array offset: 0x140, array step: 0x4 */ 8352 uint8_t RESERVED_8[168]; 8353 __IO uint32_t SYSRSTSTAT; /**< System reset status register, offset: 0x1F0 */ 8354 uint8_t RESERVED_9[12]; 8355 __IO uint32_t AHBCLKCTRL[2]; /**< AHB Clock control n, array offset: 0x200, array step: 0x4 */ 8356 uint8_t RESERVED_10[24]; 8357 __O uint32_t AHBCLKCTRLSET[2]; /**< Set bits in AHBCLKCTRLn, array offset: 0x220, array step: 0x4 */ 8358 uint8_t RESERVED_11[24]; 8359 __O uint32_t AHBCLKCTRLCLR[2]; /**< Clear bits in AHBCLKCTRLn, array offset: 0x240, array step: 0x4 */ 8360 uint8_t RESERVED_12[56]; 8361 __IO uint32_t MAINCLKSELA; /**< Main clock source select A, offset: 0x280 */ 8362 __IO uint32_t MAINCLKSELB; /**< Main clock source select B, offset: 0x284 */ 8363 __IO uint32_t CLKOUTSELA; /**< CLKOUT clock source select A, offset: 0x288 */ 8364 uint8_t RESERVED_13[4]; 8365 __IO uint32_t SYSPLLCLKSEL; /**< PLL clock source select, offset: 0x290 */ 8366 uint8_t RESERVED_14[12]; 8367 __IO uint32_t SPIFICLKSEL; /**< SPIFI clock source select, offset: 0x2A0 */ 8368 __IO uint32_t ADCCLKSEL; /**< ADC clock source select, offset: 0x2A4 */ 8369 __IO uint32_t USBCLKSEL; /**< USB clock source select, offset: 0x2A8 */ 8370 uint8_t RESERVED_15[4]; 8371 __IO uint32_t FXCOMCLKSEL[8]; /**< Flexcomm 0 clock source select, array offset: 0x2B0, array step: 0x4 */ 8372 uint8_t RESERVED_16[16]; 8373 __IO uint32_t MCLKCLKSEL; /**< MCLK clock source select, offset: 0x2E0 */ 8374 uint8_t RESERVED_17[4]; 8375 __IO uint32_t FRGCLKSEL; /**< Fractional Rate Generator clock source select, offset: 0x2E8 */ 8376 __IO uint32_t DMICCLKSEL; /**< Digital microphone (D-Mic) subsystem clock select, offset: 0x2EC */ 8377 uint8_t RESERVED_18[16]; 8378 __IO uint32_t SYSTICKCLKDIV; /**< SYSTICK clock divider, offset: 0x300 */ 8379 __IO uint32_t TRACECLKDIV; /**< Trace clock divider, offset: 0x304 */ 8380 uint8_t RESERVED_19[120]; 8381 __IO uint32_t AHBCLKDIV; /**< AHB clock divider, offset: 0x380 */ 8382 __IO uint32_t CLKOUTDIV; /**< CLKOUT clock divider, offset: 0x384 */ 8383 uint8_t RESERVED_20[8]; 8384 __IO uint32_t SPIFICLKDIV; /**< SPIFI clock divider, offset: 0x390 */ 8385 __IO uint32_t ADCCLKDIV; /**< ADC clock divider, offset: 0x394 */ 8386 __IO uint32_t USBCLKDIV; /**< USB clock divider, offset: 0x398 */ 8387 uint8_t RESERVED_21[4]; 8388 __IO uint32_t FRGCTRL; /**< Fractional rate divider, offset: 0x3A0 */ 8389 uint8_t RESERVED_22[4]; 8390 __IO uint32_t DMICCLKDIV; /**< DMIC clock divider, offset: 0x3A8 */ 8391 __IO uint32_t MCLKDIV; /**< I2S MCLK clock divider, offset: 0x3AC */ 8392 uint8_t RESERVED_23[80]; 8393 __IO uint32_t FLASHCFG; /**< Flash wait states configuration, offset: 0x400 */ 8394 uint8_t RESERVED_24[8]; 8395 __IO uint32_t USBCLKCTRL; /**< USB clock control, offset: 0x40C */ 8396 __IO uint32_t USBCLKSTAT; /**< USB clock status, offset: 0x410 */ 8397 uint8_t RESERVED_25[4]; 8398 __IO uint32_t FREQMECTRL; /**< Frequency measure register, offset: 0x418 */ 8399 uint8_t RESERVED_26[4]; 8400 __IO uint32_t MCLKIO; /**< MCLK input/output control, offset: 0x420 */ 8401 uint8_t RESERVED_27[220]; 8402 __IO uint32_t FROCTRL; /**< FRO oscillator control, offset: 0x500 */ 8403 uint8_t RESERVED_28[4]; 8404 __IO uint32_t WDTOSCCTRL; /**< Watchdog oscillator control, offset: 0x508 */ 8405 __IO uint32_t RTCOSCCTRL; /**< RTC oscillator 32 kHz output control, offset: 0x50C */ 8406 uint8_t RESERVED_29[112]; 8407 __IO uint32_t SYSPLLCTRL; /**< PLL control, offset: 0x580 */ 8408 __I uint32_t SYSPLLSTAT; /**< PLL status, offset: 0x584 */ 8409 __IO uint32_t SYSPLLNDEC; /**< PLL N decoder, offset: 0x588 */ 8410 __IO uint32_t SYSPLLPDEC; /**< PLL P decoder, offset: 0x58C */ 8411 __IO uint32_t SYSPLLSSCTRL0; /**< PLL spread spectrum control 0, offset: 0x590 */ 8412 __IO uint32_t SYSPLLSSCTRL1; /**< PLL spread spectrum control 1, offset: 0x594 */ 8413 uint8_t RESERVED_30[104]; 8414 __IO uint32_t PDSLEEPCFG[2]; /**< Sleep configuration register n, array offset: 0x600, array step: 0x4 */ 8415 uint8_t RESERVED_31[8]; 8416 __IO uint32_t PDRUNCFG[2]; /**< Power configuration register n, array offset: 0x610, array step: 0x4 */ 8417 uint8_t RESERVED_32[8]; 8418 __O uint32_t PDRUNCFGSET[2]; /**< Set bits in PDRUNCFGn, array offset: 0x620, array step: 0x4 */ 8419 uint8_t RESERVED_33[8]; 8420 __O uint32_t PDRUNCFGCLR[2]; /**< Clear bits in PDRUNCFGn, array offset: 0x630, array step: 0x4 */ 8421 uint8_t RESERVED_34[72]; 8422 __IO uint32_t STARTERP[2]; /**< Start logic n wake-up enable register, array offset: 0x680, array step: 0x4 */ 8423 uint8_t RESERVED_35[24]; 8424 __O uint32_t STARTERSET[2]; /**< Set bits in STARTERn, array offset: 0x6A0, array step: 0x4 */ 8425 uint8_t RESERVED_36[24]; 8426 __O uint32_t STARTERCLR[2]; /**< Clear bits in STARTERn, array offset: 0x6C0, array step: 0x4 */ 8427 uint8_t RESERVED_37[184]; 8428 __IO uint32_t HWWAKE; /**< Configures special cases of hardware wake-up, offset: 0x780 */ 8429 uint8_t RESERVED_38[124]; 8430 __IO uint32_t CPUCTRL; /**< CPU Control for multiple processors, offset: 0x800 */ 8431 __IO uint32_t CPBOOT; /**< Coprocessor Boot Address, offset: 0x804 */ 8432 __IO uint32_t CPSTACK; /**< Coprocessor Stack Address, offset: 0x808 */ 8433 __I uint32_t CPSTAT; /**< Coprocessor Status, offset: 0x80C */ 8434 uint8_t RESERVED_39[1524]; 8435 __IO uint32_t AUTOCGOR; /**< Auto Clock-Gate Override Register, offset: 0xE04 */ 8436 uint8_t RESERVED_40[492]; 8437 __I uint32_t JTAGIDCODE; /**< JTAG ID code register, offset: 0xFF4 */ 8438 __I uint32_t DEVICE_ID0; /**< Part ID register, offset: 0xFF8 */ 8439 __I uint32_t DEVICE_ID1; /**< Boot ROM and die revision register, offset: 0xFFC */ 8440 uint8_t RESERVED_41[127044]; 8441 __IO uint32_t BODCTRL; /**< Brown-Out Detect control, offset: 0x20044 */ 8442 } SYSCON_Type; 8443 8444 /* ---------------------------------------------------------------------------- 8445 -- SYSCON Register Masks 8446 ---------------------------------------------------------------------------- */ 8447 8448 /*! 8449 * @addtogroup SYSCON_Register_Masks SYSCON Register Masks 8450 * @{ 8451 */ 8452 8453 /*! @name AHBMATPRIO - AHB multilayer matrix priority control */ 8454 /*! @{ */ 8455 #define SYSCON_AHBMATPRIO_PRI_ICODE_MASK (0x3U) 8456 #define SYSCON_AHBMATPRIO_PRI_ICODE_SHIFT (0U) 8457 /*! PRI_ICODE - Cortex-M4 I-Code bus priority. Should typically be lower than PRI_DCODE for best operation. 8458 */ 8459 #define SYSCON_AHBMATPRIO_PRI_ICODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_ICODE_SHIFT)) & SYSCON_AHBMATPRIO_PRI_ICODE_MASK) 8460 #define SYSCON_AHBMATPRIO_PRI_DCODE_MASK (0xCU) 8461 #define SYSCON_AHBMATPRIO_PRI_DCODE_SHIFT (2U) 8462 /*! PRI_DCODE - Cortex M4 D-Code bus priority. 8463 */ 8464 #define SYSCON_AHBMATPRIO_PRI_DCODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_DCODE_SHIFT)) & SYSCON_AHBMATPRIO_PRI_DCODE_MASK) 8465 #define SYSCON_AHBMATPRIO_PRI_SYS_MASK (0x30U) 8466 #define SYSCON_AHBMATPRIO_PRI_SYS_SHIFT (4U) 8467 /*! PRI_SYS - Cortex M4 System bus priority. 8468 */ 8469 #define SYSCON_AHBMATPRIO_PRI_SYS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SYS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SYS_MASK) 8470 #define SYSCON_AHBMATPRIO_PRI_M0_MASK (0xC0U) 8471 #define SYSCON_AHBMATPRIO_PRI_M0_SHIFT (6U) 8472 /*! PRI_M0 - Cortex-M0+ bus priority. Present on selected devices. 8473 */ 8474 #define SYSCON_AHBMATPRIO_PRI_M0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_M0_SHIFT)) & SYSCON_AHBMATPRIO_PRI_M0_MASK) 8475 #define SYSCON_AHBMATPRIO_PRI_USB_MASK (0x300U) 8476 #define SYSCON_AHBMATPRIO_PRI_USB_SHIFT (8U) 8477 /*! PRI_USB - USB interface priority. 8478 */ 8479 #define SYSCON_AHBMATPRIO_PRI_USB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB_MASK) 8480 #define SYSCON_AHBMATPRIO_PRI_DMA_MASK (0xC00U) 8481 #define SYSCON_AHBMATPRIO_PRI_DMA_SHIFT (10U) 8482 /*! PRI_DMA - DMA controller priority. 8483 */ 8484 #define SYSCON_AHBMATPRIO_PRI_DMA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_DMA_SHIFT)) & SYSCON_AHBMATPRIO_PRI_DMA_MASK) 8485 /*! @} */ 8486 8487 /*! @name SYSTCKCAL - System tick counter calibration */ 8488 /*! @{ */ 8489 #define SYSCON_SYSTCKCAL_CAL_MASK (0xFFFFFFU) 8490 #define SYSCON_SYSTCKCAL_CAL_SHIFT (0U) 8491 /*! CAL - System tick timer calibration value. 8492 */ 8493 #define SYSCON_SYSTCKCAL_CAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTCKCAL_CAL_SHIFT)) & SYSCON_SYSTCKCAL_CAL_MASK) 8494 #define SYSCON_SYSTCKCAL_SKEW_MASK (0x1000000U) 8495 #define SYSCON_SYSTCKCAL_SKEW_SHIFT (24U) 8496 /*! SKEW - Initial value for the Systick timer. 8497 */ 8498 #define SYSCON_SYSTCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTCKCAL_SKEW_SHIFT)) & SYSCON_SYSTCKCAL_SKEW_MASK) 8499 #define SYSCON_SYSTCKCAL_NOREF_MASK (0x2000000U) 8500 #define SYSCON_SYSTCKCAL_NOREF_SHIFT (25U) 8501 /*! NOREF - Initial value for the Systick timer. 8502 */ 8503 #define SYSCON_SYSTCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTCKCAL_NOREF_SHIFT)) & SYSCON_SYSTCKCAL_NOREF_MASK) 8504 /*! @} */ 8505 8506 /*! @name NMISRC - NMI Source Select */ 8507 /*! @{ */ 8508 #define SYSCON_NMISRC_IRQM4_MASK (0x3FU) 8509 #define SYSCON_NMISRC_IRQM4_SHIFT (0U) 8510 /*! IRQM4 - The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the Cortex-M4, if enabled by NMIENM4. 8511 */ 8512 #define SYSCON_NMISRC_IRQM4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQM4_SHIFT)) & SYSCON_NMISRC_IRQM4_MASK) 8513 #define SYSCON_NMISRC_IRQM0_MASK (0x3F00U) 8514 #define SYSCON_NMISRC_IRQM0_SHIFT (8U) 8515 /*! IRQM0 - The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the 8516 * Cortex-M0+, if enabled by NMIENM0. Present on selected devices. 8517 */ 8518 #define SYSCON_NMISRC_IRQM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQM0_SHIFT)) & SYSCON_NMISRC_IRQM0_MASK) 8519 #define SYSCON_NMISRC_NMIENM0_MASK (0x40000000U) 8520 #define SYSCON_NMISRC_NMIENM0_SHIFT (30U) 8521 /*! NMIENM0 - Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQM0. Present on selected devices. 8522 */ 8523 #define SYSCON_NMISRC_NMIENM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENM0_SHIFT)) & SYSCON_NMISRC_NMIENM0_MASK) 8524 #define SYSCON_NMISRC_NMIENM4_MASK (0x80000000U) 8525 #define SYSCON_NMISRC_NMIENM4_SHIFT (31U) 8526 /*! NMIENM4 - Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQM4. 8527 */ 8528 #define SYSCON_NMISRC_NMIENM4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENM4_SHIFT)) & SYSCON_NMISRC_NMIENM4_MASK) 8529 /*! @} */ 8530 8531 /*! @name ASYNCAPBCTRL - Asynchronous APB Control */ 8532 /*! @{ */ 8533 #define SYSCON_ASYNCAPBCTRL_ENABLE_MASK (0x1U) 8534 #define SYSCON_ASYNCAPBCTRL_ENABLE_SHIFT (0U) 8535 /*! ENABLE - Enables the asynchronous APB bridge and subsystem. 8536 * 0b0..Disabled. Asynchronous APB bridge is disabled. 8537 * 0b1..Enabled. Asynchronous APB bridge is enabled. 8538 */ 8539 #define SYSCON_ASYNCAPBCTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ASYNCAPBCTRL_ENABLE_SHIFT)) & SYSCON_ASYNCAPBCTRL_ENABLE_MASK) 8540 /*! @} */ 8541 8542 /*! @name PIOPORCAP - POR captured value of port n */ 8543 /*! @{ */ 8544 #define SYSCON_PIOPORCAP_PIOPORCAP_MASK (0xFFFFFFFFU) 8545 #define SYSCON_PIOPORCAP_PIOPORCAP_SHIFT (0U) 8546 /*! PIOPORCAP - State of PIOn_31 through PIOn_0 at power-on reset 8547 */ 8548 #define SYSCON_PIOPORCAP_PIOPORCAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PIOPORCAP_PIOPORCAP_SHIFT)) & SYSCON_PIOPORCAP_PIOPORCAP_MASK) 8549 /*! @} */ 8550 8551 /* The count of SYSCON_PIOPORCAP */ 8552 #define SYSCON_PIOPORCAP_COUNT (2U) 8553 8554 /*! @name PIORESCAP - Reset captured value of port n */ 8555 /*! @{ */ 8556 #define SYSCON_PIORESCAP_PIORESCAP_MASK (0xFFFFFFFFU) 8557 #define SYSCON_PIORESCAP_PIORESCAP_SHIFT (0U) 8558 /*! PIORESCAP - State of PIOn_31 through PIOn_0 for resets other than POR. 8559 */ 8560 #define SYSCON_PIORESCAP_PIORESCAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PIORESCAP_PIORESCAP_SHIFT)) & SYSCON_PIORESCAP_PIORESCAP_MASK) 8561 /*! @} */ 8562 8563 /* The count of SYSCON_PIORESCAP */ 8564 #define SYSCON_PIORESCAP_COUNT (2U) 8565 8566 /*! @name PRESETCTRL - Peripheral reset control n */ 8567 /*! @{ */ 8568 #define SYSCON_PRESETCTRL_MRT0_RST_MASK (0x1U) 8569 #define SYSCON_PRESETCTRL_MRT0_RST_SHIFT (0U) 8570 /*! MRT0_RST - Multi-rate timer (MRT0) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 8571 */ 8572 #define SYSCON_PRESETCTRL_MRT0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_MRT0_RST_SHIFT)) & SYSCON_PRESETCTRL_MRT0_RST_MASK) 8573 #define SYSCON_PRESETCTRL_SCT0_RST_MASK (0x4U) 8574 #define SYSCON_PRESETCTRL_SCT0_RST_SHIFT (2U) 8575 /*! SCT0_RST - State configurable timer 0 (SCT0) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 8576 */ 8577 #define SYSCON_PRESETCTRL_SCT0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SCT0_RST_SHIFT)) & SYSCON_PRESETCTRL_SCT0_RST_MASK) 8578 #define SYSCON_PRESETCTRL_FLASH_RST_MASK (0x80U) 8579 #define SYSCON_PRESETCTRL_FLASH_RST_SHIFT (7U) 8580 /*! FLASH_RST - Flash controller reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 8581 */ 8582 #define SYSCON_PRESETCTRL_FLASH_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FLASH_RST_SHIFT)) & SYSCON_PRESETCTRL_FLASH_RST_MASK) 8583 #define SYSCON_PRESETCTRL_FMC_RST_MASK (0x100U) 8584 #define SYSCON_PRESETCTRL_FMC_RST_SHIFT (8U) 8585 /*! FMC_RST - Flash accelerator reset control. Note that the FMC must not be reset while executing 8586 * from flash, and must be reconfigured after reset. 0 = Clear reset to this function. 1 = Assert 8587 * reset to this function. 8588 */ 8589 #define SYSCON_PRESETCTRL_FMC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FMC_RST_SHIFT)) & SYSCON_PRESETCTRL_FMC_RST_MASK) 8590 #define SYSCON_PRESETCTRL_UTICK0_RST_MASK (0x400U) 8591 #define SYSCON_PRESETCTRL_UTICK0_RST_SHIFT (10U) 8592 /*! UTICK0_RST - Micro-tick Timer reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 8593 */ 8594 #define SYSCON_PRESETCTRL_UTICK0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_UTICK0_RST_SHIFT)) & SYSCON_PRESETCTRL_UTICK0_RST_MASK) 8595 #define SYSCON_PRESETCTRL_FC0_RST_MASK (0x800U) 8596 #define SYSCON_PRESETCTRL_FC0_RST_SHIFT (11U) 8597 /*! FC0_RST - Flexcomm 0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 8598 */ 8599 #define SYSCON_PRESETCTRL_FC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC0_RST_SHIFT)) & SYSCON_PRESETCTRL_FC0_RST_MASK) 8600 #define SYSCON_PRESETCTRL_MUX_RST_MASK (0x800U) 8601 #define SYSCON_PRESETCTRL_MUX_RST_SHIFT (11U) 8602 /*! MUX_RST - Input mux reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 8603 */ 8604 #define SYSCON_PRESETCTRL_MUX_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_MUX_RST_SHIFT)) & SYSCON_PRESETCTRL_MUX_RST_MASK) 8605 #define SYSCON_PRESETCTRL_FC1_RST_MASK (0x1000U) 8606 #define SYSCON_PRESETCTRL_FC1_RST_SHIFT (12U) 8607 /*! FC1_RST - Flexcomm 1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 8608 */ 8609 #define SYSCON_PRESETCTRL_FC1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC1_RST_SHIFT)) & SYSCON_PRESETCTRL_FC1_RST_MASK) 8610 #define SYSCON_PRESETCTRL_FC2_RST_MASK (0x2000U) 8611 #define SYSCON_PRESETCTRL_FC2_RST_SHIFT (13U) 8612 /*! FC2_RST - Flexcomm 2 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 8613 */ 8614 #define SYSCON_PRESETCTRL_FC2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC2_RST_SHIFT)) & SYSCON_PRESETCTRL_FC2_RST_MASK) 8615 #define SYSCON_PRESETCTRL_IOCON_RST_MASK (0x2000U) 8616 #define SYSCON_PRESETCTRL_IOCON_RST_SHIFT (13U) 8617 /*! IOCON_RST - IOCON reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 8618 */ 8619 #define SYSCON_PRESETCTRL_IOCON_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_IOCON_RST_SHIFT)) & SYSCON_PRESETCTRL_IOCON_RST_MASK) 8620 #define SYSCON_PRESETCTRL_FC3_RST_MASK (0x4000U) 8621 #define SYSCON_PRESETCTRL_FC3_RST_SHIFT (14U) 8622 /*! FC3_RST - Flexcomm 3 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 8623 */ 8624 #define SYSCON_PRESETCTRL_FC3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC3_RST_SHIFT)) & SYSCON_PRESETCTRL_FC3_RST_MASK) 8625 #define SYSCON_PRESETCTRL_GPIO0_RST_MASK (0x4000U) 8626 #define SYSCON_PRESETCTRL_GPIO0_RST_SHIFT (14U) 8627 /*! GPIO0_RST - GPIO0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 8628 */ 8629 #define SYSCON_PRESETCTRL_GPIO0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO0_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO0_RST_MASK) 8630 #define SYSCON_PRESETCTRL_FC4_RST_MASK (0x8000U) 8631 #define SYSCON_PRESETCTRL_FC4_RST_SHIFT (15U) 8632 /*! FC4_RST - Flexcomm 4 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 8633 */ 8634 #define SYSCON_PRESETCTRL_FC4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC4_RST_SHIFT)) & SYSCON_PRESETCTRL_FC4_RST_MASK) 8635 #define SYSCON_PRESETCTRL_GPIO1_RST_MASK (0x8000U) 8636 #define SYSCON_PRESETCTRL_GPIO1_RST_SHIFT (15U) 8637 /*! GPIO1_RST - GPIO1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 8638 */ 8639 #define SYSCON_PRESETCTRL_GPIO1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO1_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO1_RST_MASK) 8640 #define SYSCON_PRESETCTRL_FC5_RST_MASK (0x10000U) 8641 #define SYSCON_PRESETCTRL_FC5_RST_SHIFT (16U) 8642 /*! FC5_RST - Flexcomm 5 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 8643 */ 8644 #define SYSCON_PRESETCTRL_FC5_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC5_RST_SHIFT)) & SYSCON_PRESETCTRL_FC5_RST_MASK) 8645 #define SYSCON_PRESETCTRL_FC6_RST_MASK (0x20000U) 8646 #define SYSCON_PRESETCTRL_FC6_RST_SHIFT (17U) 8647 /*! FC6_RST - Flexcomm 6 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 8648 */ 8649 #define SYSCON_PRESETCTRL_FC6_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC6_RST_SHIFT)) & SYSCON_PRESETCTRL_FC6_RST_MASK) 8650 #define SYSCON_PRESETCTRL_FC7_RST_MASK (0x40000U) 8651 #define SYSCON_PRESETCTRL_FC7_RST_SHIFT (18U) 8652 /*! FC7_RST - Flexcomm 7 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 8653 */ 8654 #define SYSCON_PRESETCTRL_FC7_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC7_RST_SHIFT)) & SYSCON_PRESETCTRL_FC7_RST_MASK) 8655 #define SYSCON_PRESETCTRL_PINT_RST_MASK (0x40000U) 8656 #define SYSCON_PRESETCTRL_PINT_RST_SHIFT (18U) 8657 /*! PINT_RST - Pin interrupt (PINT) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 8658 */ 8659 #define SYSCON_PRESETCTRL_PINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_PINT_RST_SHIFT)) & SYSCON_PRESETCTRL_PINT_RST_MASK) 8660 #define SYSCON_PRESETCTRL_DMIC0_RST_MASK (0x80000U) 8661 #define SYSCON_PRESETCTRL_DMIC0_RST_SHIFT (19U) 8662 /*! DMIC0_RST - Digital microphone interface reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 8663 */ 8664 #define SYSCON_PRESETCTRL_DMIC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_DMIC0_RST_SHIFT)) & SYSCON_PRESETCTRL_DMIC0_RST_MASK) 8665 #define SYSCON_PRESETCTRL_GINT_RST_MASK (0x80000U) 8666 #define SYSCON_PRESETCTRL_GINT_RST_SHIFT (19U) 8667 /*! GINT_RST - Grouped interrupt (GINT) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 8668 */ 8669 #define SYSCON_PRESETCTRL_GINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GINT_RST_SHIFT)) & SYSCON_PRESETCTRL_GINT_RST_MASK) 8670 #define SYSCON_PRESETCTRL_DMA0_RST_MASK (0x100000U) 8671 #define SYSCON_PRESETCTRL_DMA0_RST_SHIFT (20U) 8672 /*! DMA0_RST - DMA0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 8673 */ 8674 #define SYSCON_PRESETCTRL_DMA0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_DMA0_RST_SHIFT)) & SYSCON_PRESETCTRL_DMA0_RST_MASK) 8675 #define SYSCON_PRESETCTRL_CRC_RST_MASK (0x200000U) 8676 #define SYSCON_PRESETCTRL_CRC_RST_SHIFT (21U) 8677 /*! CRC_RST - CRC generator reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 8678 */ 8679 #define SYSCON_PRESETCTRL_CRC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CRC_RST_SHIFT)) & SYSCON_PRESETCTRL_CRC_RST_MASK) 8680 #define SYSCON_PRESETCTRL_CTIMER2_RST_MASK (0x400000U) 8681 #define SYSCON_PRESETCTRL_CTIMER2_RST_SHIFT (22U) 8682 /*! CTIMER2_RST - CTIMER2 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function 8683 */ 8684 #define SYSCON_PRESETCTRL_CTIMER2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CTIMER2_RST_SHIFT)) & SYSCON_PRESETCTRL_CTIMER2_RST_MASK) 8685 #define SYSCON_PRESETCTRL_WWDT_RST_MASK (0x400000U) 8686 #define SYSCON_PRESETCTRL_WWDT_RST_SHIFT (22U) 8687 /*! WWDT_RST - Watchdog timer reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 8688 */ 8689 #define SYSCON_PRESETCTRL_WWDT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_WWDT_RST_SHIFT)) & SYSCON_PRESETCTRL_WWDT_RST_MASK) 8690 #define SYSCON_PRESETCTRL_USB0_RST_MASK (0x2000000U) 8691 #define SYSCON_PRESETCTRL_USB0_RST_SHIFT (25U) 8692 /*! USB0_RST - USB0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 8693 */ 8694 #define SYSCON_PRESETCTRL_USB0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB0_RST_SHIFT)) & SYSCON_PRESETCTRL_USB0_RST_MASK) 8695 #define SYSCON_PRESETCTRL_CTIMER0_RST_MASK (0x4000000U) 8696 #define SYSCON_PRESETCTRL_CTIMER0_RST_SHIFT (26U) 8697 /*! CTIMER0_RST - CTIMER0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 8698 */ 8699 #define SYSCON_PRESETCTRL_CTIMER0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CTIMER0_RST_SHIFT)) & SYSCON_PRESETCTRL_CTIMER0_RST_MASK) 8700 #define SYSCON_PRESETCTRL_ADC0_RST_MASK (0x8000000U) 8701 #define SYSCON_PRESETCTRL_ADC0_RST_SHIFT (27U) 8702 /*! ADC0_RST - ADC0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 8703 */ 8704 #define SYSCON_PRESETCTRL_ADC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_ADC0_RST_SHIFT)) & SYSCON_PRESETCTRL_ADC0_RST_MASK) 8705 #define SYSCON_PRESETCTRL_CTIMER1_RST_MASK (0x8000000U) 8706 #define SYSCON_PRESETCTRL_CTIMER1_RST_SHIFT (27U) 8707 /*! CTIMER1_RST - CTIMER1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 8708 */ 8709 #define SYSCON_PRESETCTRL_CTIMER1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CTIMER1_RST_SHIFT)) & SYSCON_PRESETCTRL_CTIMER1_RST_MASK) 8710 /*! @} */ 8711 8712 /* The count of SYSCON_PRESETCTRL */ 8713 #define SYSCON_PRESETCTRL_COUNT (2U) 8714 8715 /*! @name PRESETCTRLSET - Set bits in PRESETCTRLn */ 8716 /*! @{ */ 8717 #define SYSCON_PRESETCTRLSET_RST_SET_MASK (0xFFFFFFFFU) 8718 #define SYSCON_PRESETCTRLSET_RST_SET_SHIFT (0U) 8719 /*! RST_SET - Writing ones to this register sets the corresponding bit or bits in the PRESETCTRLn 8720 * register, if they are implemented. Bits that do not correspond to defined bits in PRESETCTRLn 8721 * are reserved and only zeroes should be written to them. 8722 */ 8723 #define SYSCON_PRESETCTRLSET_RST_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLSET_RST_SET_SHIFT)) & SYSCON_PRESETCTRLSET_RST_SET_MASK) 8724 /*! @} */ 8725 8726 /* The count of SYSCON_PRESETCTRLSET */ 8727 #define SYSCON_PRESETCTRLSET_COUNT (2U) 8728 8729 /*! @name PRESETCTRLCLR - Clear bits in PRESETCTRLn */ 8730 /*! @{ */ 8731 #define SYSCON_PRESETCTRLCLR_RST_CLR_MASK (0xFFFFFFFFU) 8732 #define SYSCON_PRESETCTRLCLR_RST_CLR_SHIFT (0U) 8733 /*! RST_CLR - Writing ones to this register clears the corresponding bit or bits in the PRESETCTRLn 8734 * register, if they are implemented. Bits that do not correspond to defined bits in PRESETCTRLn 8735 * are reserved and only zeroes should be written to them. 8736 */ 8737 #define SYSCON_PRESETCTRLCLR_RST_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLCLR_RST_CLR_SHIFT)) & SYSCON_PRESETCTRLCLR_RST_CLR_MASK) 8738 /*! @} */ 8739 8740 /* The count of SYSCON_PRESETCTRLCLR */ 8741 #define SYSCON_PRESETCTRLCLR_COUNT (2U) 8742 8743 /*! @name SYSRSTSTAT - System reset status register */ 8744 /*! @{ */ 8745 #define SYSCON_SYSRSTSTAT_POR_MASK (0x1U) 8746 #define SYSCON_SYSRSTSTAT_POR_SHIFT (0U) 8747 /*! POR - POR reset status 8748 * 0b0..No POR detected 8749 * 0b1..POR detected. Writing a one clears this reset. 8750 */ 8751 #define SYSCON_SYSRSTSTAT_POR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_POR_SHIFT)) & SYSCON_SYSRSTSTAT_POR_MASK) 8752 #define SYSCON_SYSRSTSTAT_EXTRST_MASK (0x2U) 8753 #define SYSCON_SYSRSTSTAT_EXTRST_SHIFT (1U) 8754 /*! EXTRST - Status of the external RESET pin. External reset status 8755 * 0b0..No reset event detected. 8756 * 0b1..Reset detected. Writing a one clears this reset. 8757 */ 8758 #define SYSCON_SYSRSTSTAT_EXTRST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_EXTRST_SHIFT)) & SYSCON_SYSRSTSTAT_EXTRST_MASK) 8759 #define SYSCON_SYSRSTSTAT_WDT_MASK (0x4U) 8760 #define SYSCON_SYSRSTSTAT_WDT_SHIFT (2U) 8761 /*! WDT - Status of the Watchdog reset 8762 * 0b0..No WDT reset detected 8763 * 0b1..WDT reset detected. Writing a one clears this reset. 8764 */ 8765 #define SYSCON_SYSRSTSTAT_WDT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_WDT_SHIFT)) & SYSCON_SYSRSTSTAT_WDT_MASK) 8766 #define SYSCON_SYSRSTSTAT_BOD_MASK (0x8U) 8767 #define SYSCON_SYSRSTSTAT_BOD_SHIFT (3U) 8768 /*! BOD - Status of the Brown-out detect reset 8769 * 0b0..No BOD reset detected 8770 * 0b1..BOD reset detected. Writing a one clears this reset. 8771 */ 8772 #define SYSCON_SYSRSTSTAT_BOD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_BOD_SHIFT)) & SYSCON_SYSRSTSTAT_BOD_MASK) 8773 #define SYSCON_SYSRSTSTAT_SYSRST_MASK (0x10U) 8774 #define SYSCON_SYSRSTSTAT_SYSRST_SHIFT (4U) 8775 /*! SYSRST - Status of the software system reset 8776 * 0b0..No System reset detected 8777 * 0b1..System reset detected. Writing a one clears this reset. 8778 */ 8779 #define SYSCON_SYSRSTSTAT_SYSRST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_SYSRST_SHIFT)) & SYSCON_SYSRSTSTAT_SYSRST_MASK) 8780 /*! @} */ 8781 8782 /*! @name AHBCLKCTRL - AHB Clock control n */ 8783 /*! @{ */ 8784 #define SYSCON_AHBCLKCTRL_MRT0_MASK (0x1U) 8785 #define SYSCON_AHBCLKCTRL_MRT0_SHIFT (0U) 8786 /*! MRT0 - Enables the clock for the Multi-Rate Timer. 0 = Disable; 1 = Enable. 8787 */ 8788 #define SYSCON_AHBCLKCTRL_MRT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_MRT0_SHIFT)) & SYSCON_AHBCLKCTRL_MRT0_MASK) 8789 #define SYSCON_AHBCLKCTRL_ROM_MASK (0x2U) 8790 #define SYSCON_AHBCLKCTRL_ROM_SHIFT (1U) 8791 /*! ROM - Enables the clock for the Boot ROM. 0 = Disable; 1 = Enable. 8792 */ 8793 #define SYSCON_AHBCLKCTRL_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_ROM_SHIFT)) & SYSCON_AHBCLKCTRL_ROM_MASK) 8794 #define SYSCON_AHBCLKCTRL_SCT0_MASK (0x4U) 8795 #define SYSCON_AHBCLKCTRL_SCT0_SHIFT (2U) 8796 /*! SCT0 - Enables the clock for SCT0. 0 = Disable; 1 = Enable. 8797 */ 8798 #define SYSCON_AHBCLKCTRL_SCT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SCT0_SHIFT)) & SYSCON_AHBCLKCTRL_SCT0_MASK) 8799 #define SYSCON_AHBCLKCTRL_SRAM1_MASK (0x8U) 8800 #define SYSCON_AHBCLKCTRL_SRAM1_SHIFT (3U) 8801 /*! SRAM1 - Enables the clock for SRAM1. 0 = Disable; 1 = Enable. 8802 */ 8803 #define SYSCON_AHBCLKCTRL_SRAM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SRAM1_SHIFT)) & SYSCON_AHBCLKCTRL_SRAM1_MASK) 8804 #define SYSCON_AHBCLKCTRL_SRAM2_MASK (0x10U) 8805 #define SYSCON_AHBCLKCTRL_SRAM2_SHIFT (4U) 8806 /*! SRAM2 - Enables the clock for SRAM2. 0 = Disable; 1 = Enable. 8807 */ 8808 #define SYSCON_AHBCLKCTRL_SRAM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SRAM2_SHIFT)) & SYSCON_AHBCLKCTRL_SRAM2_MASK) 8809 #define SYSCON_AHBCLKCTRL_FLASH_MASK (0x80U) 8810 #define SYSCON_AHBCLKCTRL_FLASH_SHIFT (7U) 8811 /*! FLASH - Enables the clock for the flash controller. 0 = Disable; 1 = Enable. This clock is 8812 * needed for flash programming, not for flash read. 8813 */ 8814 #define SYSCON_AHBCLKCTRL_FLASH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLASH_SHIFT)) & SYSCON_AHBCLKCTRL_FLASH_MASK) 8815 #define SYSCON_AHBCLKCTRL_FMC_MASK (0x100U) 8816 #define SYSCON_AHBCLKCTRL_FMC_SHIFT (8U) 8817 /*! FMC - Enables the clock for the Flash accelerator. 0 = Disable; 1 = Enable. This clock is needed if the flash is being read. 8818 */ 8819 #define SYSCON_AHBCLKCTRL_FMC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FMC_SHIFT)) & SYSCON_AHBCLKCTRL_FMC_MASK) 8820 #define SYSCON_AHBCLKCTRL_UTICK0_MASK (0x400U) 8821 #define SYSCON_AHBCLKCTRL_UTICK0_SHIFT (10U) 8822 /*! UTICK0 - Enables the clock for the Micro-tick Timer. 0 = Disable; 1 = Enable. 8823 */ 8824 #define SYSCON_AHBCLKCTRL_UTICK0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_UTICK0_SHIFT)) & SYSCON_AHBCLKCTRL_UTICK0_MASK) 8825 #define SYSCON_AHBCLKCTRL_FLEXCOMM0_MASK (0x800U) 8826 #define SYSCON_AHBCLKCTRL_FLEXCOMM0_SHIFT (11U) 8827 /*! FLEXCOMM0 - Enables the clock for Flexcomm 0. 0 = Disable; 1 = Enable. 8828 */ 8829 #define SYSCON_AHBCLKCTRL_FLEXCOMM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM0_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM0_MASK) 8830 #define SYSCON_AHBCLKCTRL_INPUTMUX_MASK (0x800U) 8831 #define SYSCON_AHBCLKCTRL_INPUTMUX_SHIFT (11U) 8832 /*! INPUTMUX - Enables the clock for the input muxes. 0 = Disable; 1 = Enable. 8833 */ 8834 #define SYSCON_AHBCLKCTRL_INPUTMUX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_INPUTMUX_SHIFT)) & SYSCON_AHBCLKCTRL_INPUTMUX_MASK) 8835 #define SYSCON_AHBCLKCTRL_FLEXCOMM1_MASK (0x1000U) 8836 #define SYSCON_AHBCLKCTRL_FLEXCOMM1_SHIFT (12U) 8837 /*! FLEXCOMM1 - Enables the clock for Flexcomm 1. 0 = Disable; 1 = Enable. 8838 */ 8839 #define SYSCON_AHBCLKCTRL_FLEXCOMM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM1_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM1_MASK) 8840 #define SYSCON_AHBCLKCTRL_FLEXCOMM2_MASK (0x2000U) 8841 #define SYSCON_AHBCLKCTRL_FLEXCOMM2_SHIFT (13U) 8842 /*! FLEXCOMM2 - Enables the clock for Flexcomm 2. 0 = Disable; 1 = Enable. 8843 */ 8844 #define SYSCON_AHBCLKCTRL_FLEXCOMM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM2_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM2_MASK) 8845 #define SYSCON_AHBCLKCTRL_IOCON_MASK (0x2000U) 8846 #define SYSCON_AHBCLKCTRL_IOCON_SHIFT (13U) 8847 /*! IOCON - Enables the clock for the IOCON block. 0 = Disable; 1 = Enable. 8848 */ 8849 #define SYSCON_AHBCLKCTRL_IOCON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_IOCON_SHIFT)) & SYSCON_AHBCLKCTRL_IOCON_MASK) 8850 #define SYSCON_AHBCLKCTRL_FLEXCOMM3_MASK (0x4000U) 8851 #define SYSCON_AHBCLKCTRL_FLEXCOMM3_SHIFT (14U) 8852 /*! FLEXCOMM3 - Enables the clock for Flexcomm 3. 0 = Disable; 1 = Enable. 8853 */ 8854 #define SYSCON_AHBCLKCTRL_FLEXCOMM3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM3_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM3_MASK) 8855 #define SYSCON_AHBCLKCTRL_GPIO0_MASK (0x4000U) 8856 #define SYSCON_AHBCLKCTRL_GPIO0_SHIFT (14U) 8857 /*! GPIO0 - Enables the clock for the GPIO0 port registers. 0 = Disable; 1 = Enable. 8858 */ 8859 #define SYSCON_AHBCLKCTRL_GPIO0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO0_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO0_MASK) 8860 #define SYSCON_AHBCLKCTRL_FLEXCOMM4_MASK (0x8000U) 8861 #define SYSCON_AHBCLKCTRL_FLEXCOMM4_SHIFT (15U) 8862 /*! FLEXCOMM4 - Enables the clock for Flexcomm 4. 0 = Disable; 1 = Enable. 8863 */ 8864 #define SYSCON_AHBCLKCTRL_FLEXCOMM4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM4_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM4_MASK) 8865 #define SYSCON_AHBCLKCTRL_GPIO1_MASK (0x8000U) 8866 #define SYSCON_AHBCLKCTRL_GPIO1_SHIFT (15U) 8867 /*! GPIO1 - Enables the clock for the GPIO1 port registers. 0 = Disable; 1 = Enable. 8868 */ 8869 #define SYSCON_AHBCLKCTRL_GPIO1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO1_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO1_MASK) 8870 #define SYSCON_AHBCLKCTRL_FLEXCOMM5_MASK (0x10000U) 8871 #define SYSCON_AHBCLKCTRL_FLEXCOMM5_SHIFT (16U) 8872 /*! FLEXCOMM5 - Enables the clock for Flexcomm 5. 0 = Disable; 1 = Enable. 8873 */ 8874 #define SYSCON_AHBCLKCTRL_FLEXCOMM5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM5_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM5_MASK) 8875 #define SYSCON_AHBCLKCTRL_FLEXCOMM6_MASK (0x20000U) 8876 #define SYSCON_AHBCLKCTRL_FLEXCOMM6_SHIFT (17U) 8877 /*! FLEXCOMM6 - Enables the clock for Flexcomm 6. 0 = Disable; 1 = Enable. 8878 */ 8879 #define SYSCON_AHBCLKCTRL_FLEXCOMM6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM6_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM6_MASK) 8880 #define SYSCON_AHBCLKCTRL_FLEXCOMM7_MASK (0x40000U) 8881 #define SYSCON_AHBCLKCTRL_FLEXCOMM7_SHIFT (18U) 8882 /*! FLEXCOMM7 - Enables the clock for Flexcomm 7. 0 = Disable; 1 = Enable. 8883 */ 8884 #define SYSCON_AHBCLKCTRL_FLEXCOMM7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM7_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM7_MASK) 8885 #define SYSCON_AHBCLKCTRL_PINT_MASK (0x40000U) 8886 #define SYSCON_AHBCLKCTRL_PINT_SHIFT (18U) 8887 /*! PINT - Enables the clock for the pin interrupt block.0 = Disable; 1 = Enable. 8888 */ 8889 #define SYSCON_AHBCLKCTRL_PINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_PINT_SHIFT)) & SYSCON_AHBCLKCTRL_PINT_MASK) 8890 #define SYSCON_AHBCLKCTRL_DMIC0_MASK (0x80000U) 8891 #define SYSCON_AHBCLKCTRL_DMIC0_SHIFT (19U) 8892 /*! DMIC0 - Enables the clock for the digital microphone interface. 0 = Disable; 1 = Enable. 8893 */ 8894 #define SYSCON_AHBCLKCTRL_DMIC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_DMIC0_SHIFT)) & SYSCON_AHBCLKCTRL_DMIC0_MASK) 8895 #define SYSCON_AHBCLKCTRL_GINT_MASK (0x80000U) 8896 #define SYSCON_AHBCLKCTRL_GINT_SHIFT (19U) 8897 /*! GINT - Enables the clock for the grouped pin interrupt block. 0 = Disable; 1 = Enable. 8898 */ 8899 #define SYSCON_AHBCLKCTRL_GINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GINT_SHIFT)) & SYSCON_AHBCLKCTRL_GINT_MASK) 8900 #define SYSCON_AHBCLKCTRL_DMA0_MASK (0x100000U) 8901 #define SYSCON_AHBCLKCTRL_DMA0_SHIFT (20U) 8902 /*! DMA0 - Enables the clock for the DMA0 controller. 0 = Disable; 1 = Enable. 8903 */ 8904 #define SYSCON_AHBCLKCTRL_DMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_DMA0_SHIFT)) & SYSCON_AHBCLKCTRL_DMA0_MASK) 8905 #define SYSCON_AHBCLKCTRL_CRC_MASK (0x200000U) 8906 #define SYSCON_AHBCLKCTRL_CRC_SHIFT (21U) 8907 /*! CRC - Enables the clock for the CRC engine. 0 = Disable; 1 = Enable. 8908 */ 8909 #define SYSCON_AHBCLKCTRL_CRC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CRC_SHIFT)) & SYSCON_AHBCLKCTRL_CRC_MASK) 8910 #define SYSCON_AHBCLKCTRL_CTIMER2_MASK (0x400000U) 8911 #define SYSCON_AHBCLKCTRL_CTIMER2_SHIFT (22U) 8912 /*! CTIMER2 - Enables the clock for CTIMER 2. 0 = Disable; 1 = Enable. 8913 */ 8914 #define SYSCON_AHBCLKCTRL_CTIMER2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CTIMER2_SHIFT)) & SYSCON_AHBCLKCTRL_CTIMER2_MASK) 8915 #define SYSCON_AHBCLKCTRL_WWDT_MASK (0x400000U) 8916 #define SYSCON_AHBCLKCTRL_WWDT_SHIFT (22U) 8917 /*! WWDT - Enables the clock for the Watchdog Timer. 0 = Disable; 1 = Enable. 8918 */ 8919 #define SYSCON_AHBCLKCTRL_WWDT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_WWDT_SHIFT)) & SYSCON_AHBCLKCTRL_WWDT_MASK) 8920 #define SYSCON_AHBCLKCTRL_RTC_MASK (0x800000U) 8921 #define SYSCON_AHBCLKCTRL_RTC_SHIFT (23U) 8922 /*! RTC - Enables the bus clock for the RTC. 0 = Disable; 1 = Enable. 8923 */ 8924 #define SYSCON_AHBCLKCTRL_RTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_RTC_SHIFT)) & SYSCON_AHBCLKCTRL_RTC_MASK) 8925 #define SYSCON_AHBCLKCTRL_USB0_MASK (0x2000000U) 8926 #define SYSCON_AHBCLKCTRL_USB0_SHIFT (25U) 8927 /*! USB0 - Enables the clock for the USB0 interface. 0 = Disable; 1 = Enable. 8928 */ 8929 #define SYSCON_AHBCLKCTRL_USB0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB0_SHIFT)) & SYSCON_AHBCLKCTRL_USB0_MASK) 8930 #define SYSCON_AHBCLKCTRL_CTIMER0_MASK (0x4000000U) 8931 #define SYSCON_AHBCLKCTRL_CTIMER0_SHIFT (26U) 8932 /*! CTIMER0 - Enables the clock for timer CTIMER0. 0 = Disable; 1 = Enable. 8933 */ 8934 #define SYSCON_AHBCLKCTRL_CTIMER0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CTIMER0_SHIFT)) & SYSCON_AHBCLKCTRL_CTIMER0_MASK) 8935 #define SYSCON_AHBCLKCTRL_MAILBOX_MASK (0x4000000U) 8936 #define SYSCON_AHBCLKCTRL_MAILBOX_SHIFT (26U) 8937 /*! MAILBOX - Enables the clock for the Mailbox. 0 = Disable; 1 = Enable. Present on selected devices 8938 */ 8939 #define SYSCON_AHBCLKCTRL_MAILBOX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_MAILBOX_SHIFT)) & SYSCON_AHBCLKCTRL_MAILBOX_MASK) 8940 #define SYSCON_AHBCLKCTRL_ADC0_MASK (0x8000000U) 8941 #define SYSCON_AHBCLKCTRL_ADC0_SHIFT (27U) 8942 /*! ADC0 - Enables the clock for the ADC0 register interface. 0 = Disable; 1 = Enable. 8943 */ 8944 #define SYSCON_AHBCLKCTRL_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_ADC0_SHIFT)) & SYSCON_AHBCLKCTRL_ADC0_MASK) 8945 #define SYSCON_AHBCLKCTRL_CTIMER1_MASK (0x8000000U) 8946 #define SYSCON_AHBCLKCTRL_CTIMER1_SHIFT (27U) 8947 /*! CTIMER1 - Enables the clock for timer CTIMER1. 0 = Disable; 1 = Enable. 8948 */ 8949 #define SYSCON_AHBCLKCTRL_CTIMER1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CTIMER1_SHIFT)) & SYSCON_AHBCLKCTRL_CTIMER1_MASK) 8950 /*! @} */ 8951 8952 /* The count of SYSCON_AHBCLKCTRL */ 8953 #define SYSCON_AHBCLKCTRL_COUNT (2U) 8954 8955 /*! @name AHBCLKCTRLSET - Set bits in AHBCLKCTRLn */ 8956 /*! @{ */ 8957 #define SYSCON_AHBCLKCTRLSET_CLK_SET_MASK (0xFFFFFFFFU) 8958 #define SYSCON_AHBCLKCTRLSET_CLK_SET_SHIFT (0U) 8959 /*! CLK_SET - Writing ones to this register sets the corresponding bit or bits in the AHBCLKCTRLn 8960 * register, if they are implemented. Bits that do not correspond to defined bits in AHBCLKCTRLn 8961 * are reserved and only zeroes should be written to them. 8962 */ 8963 #define SYSCON_AHBCLKCTRLSET_CLK_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLSET_CLK_SET_SHIFT)) & SYSCON_AHBCLKCTRLSET_CLK_SET_MASK) 8964 /*! @} */ 8965 8966 /* The count of SYSCON_AHBCLKCTRLSET */ 8967 #define SYSCON_AHBCLKCTRLSET_COUNT (2U) 8968 8969 /*! @name AHBCLKCTRLCLR - Clear bits in AHBCLKCTRLn */ 8970 /*! @{ */ 8971 #define SYSCON_AHBCLKCTRLCLR_CLK_CLR_MASK (0xFFFFFFFFU) 8972 #define SYSCON_AHBCLKCTRLCLR_CLK_CLR_SHIFT (0U) 8973 /*! CLK_CLR - Writing ones to this register clears the corresponding bit or bits in the AHBCLKCTRLn 8974 * register, if they are implemented. Bits that do not correspond to defined bits in AHBCLKCTRLn 8975 * are reserved and only zeroes should be written to them. 8976 */ 8977 #define SYSCON_AHBCLKCTRLCLR_CLK_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLCLR_CLK_CLR_SHIFT)) & SYSCON_AHBCLKCTRLCLR_CLK_CLR_MASK) 8978 /*! @} */ 8979 8980 /* The count of SYSCON_AHBCLKCTRLCLR */ 8981 #define SYSCON_AHBCLKCTRLCLR_COUNT (2U) 8982 8983 /*! @name MAINCLKSELA - Main clock source select A */ 8984 /*! @{ */ 8985 #define SYSCON_MAINCLKSELA_SEL_MASK (0x3U) 8986 #define SYSCON_MAINCLKSELA_SEL_SHIFT (0U) 8987 /*! SEL - Clock source for main clock source selector A 8988 * 0b00..FRO 12 MHz (fro_12m) 8989 * 0b01..CLKIN (clk_in) 8990 * 0b10..Watchdog oscillator (wdt_clk) 8991 * 0b11..FRO 96 or 48 MHz (fro_hf) 8992 */ 8993 #define SYSCON_MAINCLKSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELA_SEL_SHIFT)) & SYSCON_MAINCLKSELA_SEL_MASK) 8994 /*! @} */ 8995 8996 /*! @name MAINCLKSELB - Main clock source select B */ 8997 /*! @{ */ 8998 #define SYSCON_MAINCLKSELB_SEL_MASK (0x3U) 8999 #define SYSCON_MAINCLKSELB_SEL_SHIFT (0U) 9000 /*! SEL - Clock source for main clock source selector B. Selects the clock source for the main clock. 9001 * 0b00..MAINCLKSELA. Use the clock source selected in MAINCLKSELA register. 9002 * 0b01..Reserved setting 9003 * 0b10..System PLL output (pll_clk) 9004 * 0b11..RTC oscillator 32 kHz output (32k_clk) 9005 */ 9006 #define SYSCON_MAINCLKSELB_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELB_SEL_SHIFT)) & SYSCON_MAINCLKSELB_SEL_MASK) 9007 /*! @} */ 9008 9009 /*! @name CLKOUTSELA - CLKOUT clock source select A */ 9010 /*! @{ */ 9011 #define SYSCON_CLKOUTSELA_SEL_MASK (0x7U) 9012 #define SYSCON_CLKOUTSELA_SEL_SHIFT (0U) 9013 /*! SEL - CLKOUT clock source selection 9014 * 0b000..Main clock (main_clk) 9015 * 0b001..CLKIN (clk_in) 9016 * 0b010..Watchdog oscillator (wdt_clk) 9017 * 0b011..FRO 96 or 48 MHz (fro_hf) 9018 * 0b100..PLL output (pll_clk) 9019 * 0b101..FRO 12 MHz (fro_12m) 9020 * 0b110..RTC oscillator 32 kHz output (32k_clk) 9021 * 0b111..None, this may be selected in order to reduce power when no output is needed. 9022 */ 9023 #define SYSCON_CLKOUTSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTSELA_SEL_SHIFT)) & SYSCON_CLKOUTSELA_SEL_MASK) 9024 /*! @} */ 9025 9026 /*! @name SYSPLLCLKSEL - PLL clock source select */ 9027 /*! @{ */ 9028 #define SYSCON_SYSPLLCLKSEL_SEL_MASK (0x7U) 9029 #define SYSCON_SYSPLLCLKSEL_SEL_SHIFT (0U) 9030 /*! SEL - System PLL clock source selection 9031 * 0b000..FRO 12 MHz (fro_12m) 9032 * 0b001..CLKIN (clk_in) 9033 * 0b010..Watchdog oscillator (wdt_clk) 9034 * 0b011..RTC 32 kHz clock (32k_clk) 9035 * 0b111..None, this may be selected in order to reduce power when no output is needed. 9036 */ 9037 #define SYSCON_SYSPLLCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCLKSEL_SEL_SHIFT)) & SYSCON_SYSPLLCLKSEL_SEL_MASK) 9038 /*! @} */ 9039 9040 /*! @name SPIFICLKSEL - SPIFI clock source select */ 9041 /*! @{ */ 9042 #define SYSCON_SPIFICLKSEL_SEL_MASK (0x7U) 9043 #define SYSCON_SPIFICLKSEL_SEL_SHIFT (0U) 9044 /*! SEL - System PLL clock source selection 9045 * 0b000..Main clock (main_clk) 9046 * 0b001..System PLL output (pll_clk) 9047 * 0b011..FRO 96 or 48 MHz (fro_hf) 9048 * 0b111..None, this may be selected in order to reduce power when no output is needed. 9049 */ 9050 #define SYSCON_SPIFICLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKSEL_SEL_SHIFT)) & SYSCON_SPIFICLKSEL_SEL_MASK) 9051 /*! @} */ 9052 9053 /*! @name ADCCLKSEL - ADC clock source select */ 9054 /*! @{ */ 9055 #define SYSCON_ADCCLKSEL_SEL_MASK (0x7U) 9056 #define SYSCON_ADCCLKSEL_SEL_SHIFT (0U) 9057 /*! SEL - ADC clock source selection 9058 * 0b000..Main clock (main_clk) 9059 * 0b001..System PLL output (pll_clk) 9060 * 0b010..FRO 96 or 48 MHz (fro_hf) 9061 * 0b111..None, this may be selected in order to reduce power when no output is needed. 9062 */ 9063 #define SYSCON_ADCCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKSEL_SEL_SHIFT)) & SYSCON_ADCCLKSEL_SEL_MASK) 9064 /*! @} */ 9065 9066 /*! @name USBCLKSEL - USB clock source select */ 9067 /*! @{ */ 9068 #define SYSCON_USBCLKSEL_SEL_MASK (0x7U) 9069 #define SYSCON_USBCLKSEL_SEL_SHIFT (0U) 9070 /*! SEL - USB device clock source selection 9071 * 0b000..FRO 96 or 48 MHz (fro_hf) 9072 * 0b001..System PLL output (pll_clk) 9073 * 0b010..Main clock (main_clk) 9074 * 0b111..None, this may be selected in order to reduce power when no output is needed. 9075 */ 9076 #define SYSCON_USBCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBCLKSEL_SEL_SHIFT)) & SYSCON_USBCLKSEL_SEL_MASK) 9077 /*! @} */ 9078 9079 /*! @name FXCOMCLKSEL - Flexcomm 0 clock source select */ 9080 /*! @{ */ 9081 #define SYSCON_FXCOMCLKSEL_SEL_MASK (0x7U) 9082 #define SYSCON_FXCOMCLKSEL_SEL_SHIFT (0U) 9083 /*! SEL - Flexcomm clock source selection. One per Flexcomm. 9084 * 0b000..FRO 12 MHz (fro_12m) 9085 * 0b001..FRO 96 or 48 MHz (fro_hf) 9086 * 0b010..System PLL output (pll_clk) 9087 * 0b011..MCLK pin input, when selected in IOCON (mclk_in) 9088 * 0b100..FRG clock, the output of the fractional rate generator (frg_clk) 9089 * 0b111..None, this may be selected in order to reduce power when no output is needed. 9090 */ 9091 #define SYSCON_FXCOMCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FXCOMCLKSEL_SEL_SHIFT)) & SYSCON_FXCOMCLKSEL_SEL_MASK) 9092 /*! @} */ 9093 9094 /* The count of SYSCON_FXCOMCLKSEL */ 9095 #define SYSCON_FXCOMCLKSEL_COUNT (8U) 9096 9097 /*! @name MCLKCLKSEL - MCLK clock source select */ 9098 /*! @{ */ 9099 #define SYSCON_MCLKCLKSEL_SEL_MASK (0x7U) 9100 #define SYSCON_MCLKCLKSEL_SEL_SHIFT (0U) 9101 /*! SEL - MCLK source select. This may be used by Flexcomms that support I2S, and/or by the digital microphone subsystem. 9102 * 0b000..FRO 96 or 48 MHz (fro_hf) 9103 * 0b001..System PLL output (pll_clk) 9104 * 0b010..Main clock (main_clk) 9105 * 0b111..None, this may be selected in order to reduce power when no output is needed. 9106 */ 9107 #define SYSCON_MCLKCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKCLKSEL_SEL_SHIFT)) & SYSCON_MCLKCLKSEL_SEL_MASK) 9108 /*! @} */ 9109 9110 /*! @name FRGCLKSEL - Fractional Rate Generator clock source select */ 9111 /*! @{ */ 9112 #define SYSCON_FRGCLKSEL_SEL_MASK (0x7U) 9113 #define SYSCON_FRGCLKSEL_SEL_SHIFT (0U) 9114 /*! SEL - Fractional Rate Generator clock source select. 9115 * 0b000..Main clock (main_clk) 9116 * 0b001..System PLL output (pll_clk) 9117 * 0b010..FRO 12 MHz (fro_12m) 9118 * 0b011..FRO 96 or 48 MHz (fro_hf) 9119 * 0b111..None, this may be selected in order to reduce power when no output is needed. 9120 */ 9121 #define SYSCON_FRGCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FRGCLKSEL_SEL_SHIFT)) & SYSCON_FRGCLKSEL_SEL_MASK) 9122 /*! @} */ 9123 9124 /*! @name DMICCLKSEL - Digital microphone (D-Mic) subsystem clock select */ 9125 /*! @{ */ 9126 #define SYSCON_DMICCLKSEL_SEL_MASK (0x7U) 9127 #define SYSCON_DMICCLKSEL_SEL_SHIFT (0U) 9128 /*! SEL - D-Mic subsystem clock source select. 9129 * 0b000..FRO 12 MHz (fro_12m) 9130 * 0b001..FRO 96 or 48 MHz (fro_hf) 9131 * 0b010..System PLL output (pll_clk) 9132 * 0b011..MCLK pin input, when selected in IOCON (mclk_in) 9133 * 0b100..Main clock (main_clk) 9134 * 0b101..Watchdog oscillator (wdt_clk) 9135 * 0b110..Reserved setting 9136 * 0b111..None, this may be selected in order to reduce power when no output is needed. 9137 */ 9138 #define SYSCON_DMICCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKSEL_SEL_SHIFT)) & SYSCON_DMICCLKSEL_SEL_MASK) 9139 /*! @} */ 9140 9141 /*! @name SYSTICKCLKDIV - SYSTICK clock divider */ 9142 /*! @{ */ 9143 #define SYSCON_SYSTICKCLKDIV_DIV_MASK (0xFFU) 9144 #define SYSCON_SYSTICKCLKDIV_DIV_SHIFT (0U) 9145 /*! DIV - Clock divider value. 0: Divide by 1 up to 255: Divide by 256. 9146 */ 9147 #define SYSCON_SYSTICKCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_DIV_SHIFT)) & SYSCON_SYSTICKCLKDIV_DIV_MASK) 9148 #define SYSCON_SYSTICKCLKDIV_RESET_MASK (0x20000000U) 9149 #define SYSCON_SYSTICKCLKDIV_RESET_SHIFT (29U) 9150 /*! RESET - Resets the divider counter. Can be used to make sure a new divider value is used right 9151 * away rather than completing the previous count. 9152 */ 9153 #define SYSCON_SYSTICKCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_RESET_SHIFT)) & SYSCON_SYSTICKCLKDIV_RESET_MASK) 9154 #define SYSCON_SYSTICKCLKDIV_HALT_MASK (0x40000000U) 9155 #define SYSCON_SYSTICKCLKDIV_HALT_SHIFT (30U) 9156 /*! HALT - Halts the divider counter. The intent is to allow the divider clock source to be changed 9157 * without the risk of a glitch at the output. 9158 */ 9159 #define SYSCON_SYSTICKCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_HALT_SHIFT)) & SYSCON_SYSTICKCLKDIV_HALT_MASK) 9160 /*! @} */ 9161 9162 /*! @name TRACECLKDIV - Trace clock divider */ 9163 /*! @{ */ 9164 #define SYSCON_TRACECLKDIV_DIV_MASK (0xFFU) 9165 #define SYSCON_TRACECLKDIV_DIV_SHIFT (0U) 9166 /*! DIV - Clock divider value. 0: Divide by 1 up to 255: Divide by 256. 9167 */ 9168 #define SYSCON_TRACECLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_DIV_SHIFT)) & SYSCON_TRACECLKDIV_DIV_MASK) 9169 #define SYSCON_TRACECLKDIV_RESET_MASK (0x20000000U) 9170 #define SYSCON_TRACECLKDIV_RESET_SHIFT (29U) 9171 /*! RESET - Resets the divider counter. Can be used to make sure a new divider value is used right 9172 * away rather than completing the previous count. 9173 */ 9174 #define SYSCON_TRACECLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_RESET_SHIFT)) & SYSCON_TRACECLKDIV_RESET_MASK) 9175 #define SYSCON_TRACECLKDIV_HALT_MASK (0x40000000U) 9176 #define SYSCON_TRACECLKDIV_HALT_SHIFT (30U) 9177 /*! HALT - Halts the divider counter. The intent is to allow the divider clock source to be changed 9178 * without the risk of a glitch at the output. 9179 */ 9180 #define SYSCON_TRACECLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_HALT_SHIFT)) & SYSCON_TRACECLKDIV_HALT_MASK) 9181 /*! @} */ 9182 9183 /*! @name AHBCLKDIV - AHB clock divider */ 9184 /*! @{ */ 9185 #define SYSCON_AHBCLKDIV_DIV_MASK (0xFFU) 9186 #define SYSCON_AHBCLKDIV_DIV_SHIFT (0U) 9187 /*! DIV - Clock divider value. 0: Divide by 1 up to 255: Divide by 256. 9188 */ 9189 #define SYSCON_AHBCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_DIV_SHIFT)) & SYSCON_AHBCLKDIV_DIV_MASK) 9190 #define SYSCON_AHBCLKDIV_RESET_MASK (0x20000000U) 9191 #define SYSCON_AHBCLKDIV_RESET_SHIFT (29U) 9192 /*! RESET - Resets the divider counter. Can be used to make sure a new divider value is used right 9193 * away rather than completing the previous count. 9194 */ 9195 #define SYSCON_AHBCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_RESET_SHIFT)) & SYSCON_AHBCLKDIV_RESET_MASK) 9196 #define SYSCON_AHBCLKDIV_HALT_MASK (0x40000000U) 9197 #define SYSCON_AHBCLKDIV_HALT_SHIFT (30U) 9198 /*! HALT - Halts the divider counter. The intent is to allow the divider clock source to be changed 9199 * without the risk of a glitch at the output. 9200 */ 9201 #define SYSCON_AHBCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_HALT_SHIFT)) & SYSCON_AHBCLKDIV_HALT_MASK) 9202 /*! @} */ 9203 9204 /*! @name CLKOUTDIV - CLKOUT clock divider */ 9205 /*! @{ */ 9206 #define SYSCON_CLKOUTDIV_DIV_MASK (0xFFU) 9207 #define SYSCON_CLKOUTDIV_DIV_SHIFT (0U) 9208 /*! DIV - Clock divider value. 0: Divide by 1 up to 255: Divide by 256. 9209 */ 9210 #define SYSCON_CLKOUTDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_DIV_SHIFT)) & SYSCON_CLKOUTDIV_DIV_MASK) 9211 #define SYSCON_CLKOUTDIV_RESET_MASK (0x20000000U) 9212 #define SYSCON_CLKOUTDIV_RESET_SHIFT (29U) 9213 /*! RESET - Resets the divider counter. Can be used to make sure a new divider value is used right 9214 * away rather than completing the previous count. 9215 */ 9216 #define SYSCON_CLKOUTDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_RESET_SHIFT)) & SYSCON_CLKOUTDIV_RESET_MASK) 9217 #define SYSCON_CLKOUTDIV_HALT_MASK (0x40000000U) 9218 #define SYSCON_CLKOUTDIV_HALT_SHIFT (30U) 9219 /*! HALT - Halts the divider counter. The intent is to allow the divider clock source to be changed 9220 * without the risk of a glitch at the output. 9221 */ 9222 #define SYSCON_CLKOUTDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_HALT_SHIFT)) & SYSCON_CLKOUTDIV_HALT_MASK) 9223 /*! @} */ 9224 9225 /*! @name SPIFICLKDIV - SPIFI clock divider */ 9226 /*! @{ */ 9227 #define SYSCON_SPIFICLKDIV_DIV_MASK (0xFFU) 9228 #define SYSCON_SPIFICLKDIV_DIV_SHIFT (0U) 9229 /*! DIV - Clock divider value. 0: Divide by 1 up to 255: Divide by 256. 9230 */ 9231 #define SYSCON_SPIFICLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_DIV_SHIFT)) & SYSCON_SPIFICLKDIV_DIV_MASK) 9232 #define SYSCON_SPIFICLKDIV_RESET_MASK (0x20000000U) 9233 #define SYSCON_SPIFICLKDIV_RESET_SHIFT (29U) 9234 /*! RESET - Resets the divider counter. Can be used to make sure a new divider value is used right 9235 * away rather than completing the previous count. 9236 */ 9237 #define SYSCON_SPIFICLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_RESET_SHIFT)) & SYSCON_SPIFICLKDIV_RESET_MASK) 9238 #define SYSCON_SPIFICLKDIV_HALT_MASK (0x40000000U) 9239 #define SYSCON_SPIFICLKDIV_HALT_SHIFT (30U) 9240 /*! HALT - Halts the divider counter. The intent is to allow the divider clock source to be changed 9241 * without the risk of a glitch at the output. 9242 */ 9243 #define SYSCON_SPIFICLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_HALT_SHIFT)) & SYSCON_SPIFICLKDIV_HALT_MASK) 9244 /*! @} */ 9245 9246 /*! @name ADCCLKDIV - ADC clock divider */ 9247 /*! @{ */ 9248 #define SYSCON_ADCCLKDIV_DIV_MASK (0xFFU) 9249 #define SYSCON_ADCCLKDIV_DIV_SHIFT (0U) 9250 /*! DIV - Clock divider value. 0: Divide by 1 up to 255: Divide by 256. 9251 */ 9252 #define SYSCON_ADCCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_DIV_SHIFT)) & SYSCON_ADCCLKDIV_DIV_MASK) 9253 #define SYSCON_ADCCLKDIV_RESET_MASK (0x20000000U) 9254 #define SYSCON_ADCCLKDIV_RESET_SHIFT (29U) 9255 /*! RESET - Resets the divider counter. Can be used to make sure a new divider value is used right 9256 * away rather than completing the previous count. 9257 */ 9258 #define SYSCON_ADCCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_RESET_SHIFT)) & SYSCON_ADCCLKDIV_RESET_MASK) 9259 #define SYSCON_ADCCLKDIV_HALT_MASK (0x40000000U) 9260 #define SYSCON_ADCCLKDIV_HALT_SHIFT (30U) 9261 /*! HALT - Halts the divider counter. The intent is to allow the divider clock source to be changed 9262 * without the risk of a glitch at the output. 9263 */ 9264 #define SYSCON_ADCCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_HALT_SHIFT)) & SYSCON_ADCCLKDIV_HALT_MASK) 9265 /*! @} */ 9266 9267 /*! @name USBCLKDIV - USB clock divider */ 9268 /*! @{ */ 9269 #define SYSCON_USBCLKDIV_DIV_MASK (0xFFU) 9270 #define SYSCON_USBCLKDIV_DIV_SHIFT (0U) 9271 /*! DIV - Clock divider value. 0: Divide by 1 up to 255: Divide by 256. 9272 */ 9273 #define SYSCON_USBCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBCLKDIV_DIV_SHIFT)) & SYSCON_USBCLKDIV_DIV_MASK) 9274 #define SYSCON_USBCLKDIV_RESET_MASK (0x20000000U) 9275 #define SYSCON_USBCLKDIV_RESET_SHIFT (29U) 9276 /*! RESET - Resets the divider counter. Can be used to make sure a new divider value is used right 9277 * away rather than completing the previous count. 9278 */ 9279 #define SYSCON_USBCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBCLKDIV_RESET_SHIFT)) & SYSCON_USBCLKDIV_RESET_MASK) 9280 #define SYSCON_USBCLKDIV_HALT_MASK (0x40000000U) 9281 #define SYSCON_USBCLKDIV_HALT_SHIFT (30U) 9282 /*! HALT - Halts the divider counter. The intent is to allow the divider clock source to be changed 9283 * without the risk of a glitch at the output. 9284 */ 9285 #define SYSCON_USBCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBCLKDIV_HALT_SHIFT)) & SYSCON_USBCLKDIV_HALT_MASK) 9286 /*! @} */ 9287 9288 /*! @name FRGCTRL - Fractional rate divider */ 9289 /*! @{ */ 9290 #define SYSCON_FRGCTRL_DIV_MASK (0xFFU) 9291 #define SYSCON_FRGCTRL_DIV_SHIFT (0U) 9292 /*! DIV - Denominator of the fractional divider. DIV is equal to the programmed value +1. Always set 9293 * to 0xFF to use with the fractional baud rate generator. 9294 */ 9295 #define SYSCON_FRGCTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FRGCTRL_DIV_SHIFT)) & SYSCON_FRGCTRL_DIV_MASK) 9296 #define SYSCON_FRGCTRL_MULT_MASK (0xFF00U) 9297 #define SYSCON_FRGCTRL_MULT_SHIFT (8U) 9298 /*! MULT - Numerator of the fractional divider. MULT is equal to the programmed value. 9299 */ 9300 #define SYSCON_FRGCTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FRGCTRL_MULT_SHIFT)) & SYSCON_FRGCTRL_MULT_MASK) 9301 /*! @} */ 9302 9303 /*! @name DMICCLKDIV - DMIC clock divider */ 9304 /*! @{ */ 9305 #define SYSCON_DMICCLKDIV_DIV_MASK (0xFFU) 9306 #define SYSCON_DMICCLKDIV_DIV_SHIFT (0U) 9307 /*! DIV - Clock divider value. 0: Divide by 1 up to 255: Divide by 256. 9308 */ 9309 #define SYSCON_DMICCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKDIV_DIV_SHIFT)) & SYSCON_DMICCLKDIV_DIV_MASK) 9310 #define SYSCON_DMICCLKDIV_RESET_MASK (0x20000000U) 9311 #define SYSCON_DMICCLKDIV_RESET_SHIFT (29U) 9312 /*! RESET - Resets the divider counter. Can be used to make sure a new divider value is used right 9313 * away rather than completing the previous count. 9314 */ 9315 #define SYSCON_DMICCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKDIV_RESET_SHIFT)) & SYSCON_DMICCLKDIV_RESET_MASK) 9316 #define SYSCON_DMICCLKDIV_HALT_MASK (0x40000000U) 9317 #define SYSCON_DMICCLKDIV_HALT_SHIFT (30U) 9318 /*! HALT - Halts the divider counter. The intent is to allow the divider clock source to be changed 9319 * without the risk of a glitch at the output. 9320 */ 9321 #define SYSCON_DMICCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKDIV_HALT_SHIFT)) & SYSCON_DMICCLKDIV_HALT_MASK) 9322 /*! @} */ 9323 9324 /*! @name MCLKDIV - I2S MCLK clock divider */ 9325 /*! @{ */ 9326 #define SYSCON_MCLKDIV_DIV_MASK (0xFFU) 9327 #define SYSCON_MCLKDIV_DIV_SHIFT (0U) 9328 /*! DIV - Clock divider value. 0: Divide by 1 up to 255: Divide by 256. 9329 */ 9330 #define SYSCON_MCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_DIV_SHIFT)) & SYSCON_MCLKDIV_DIV_MASK) 9331 #define SYSCON_MCLKDIV_RESET_MASK (0x20000000U) 9332 #define SYSCON_MCLKDIV_RESET_SHIFT (29U) 9333 /*! RESET - Resets the divider counter. Can be used to make sure a new divider value is used right 9334 * away rather than completing the previous count. 9335 */ 9336 #define SYSCON_MCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_RESET_SHIFT)) & SYSCON_MCLKDIV_RESET_MASK) 9337 #define SYSCON_MCLKDIV_HALT_MASK (0x40000000U) 9338 #define SYSCON_MCLKDIV_HALT_SHIFT (30U) 9339 /*! HALT - Halts the divider counter. The intent is to allow the divider clock source to be changed 9340 * without the risk of a glitch at the output. 9341 */ 9342 #define SYSCON_MCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_HALT_SHIFT)) & SYSCON_MCLKDIV_HALT_MASK) 9343 /*! @} */ 9344 9345 /*! @name FLASHCFG - Flash wait states configuration */ 9346 /*! @{ */ 9347 #define SYSCON_FLASHCFG_FETCHCFG_MASK (0x3U) 9348 #define SYSCON_FLASHCFG_FETCHCFG_SHIFT (0U) 9349 /*! FETCHCFG - Instruction fetch configuration. This field determines how flash accelerator buffers are used for instruction fetches. 9350 * 0b00..Instruction fetches from flash are not buffered. Every fetch request from the CPU results in a read of 9351 * the flash memory. This setting may use significantly more power than when buffering is enabled. 9352 * 0b01..One buffer is used for all instruction fetches. 9353 * 0b10..All buffers may be used for instruction fetches. 9354 * 0b11..Reserved setting, do not use. 9355 */ 9356 #define SYSCON_FLASHCFG_FETCHCFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_FETCHCFG_SHIFT)) & SYSCON_FLASHCFG_FETCHCFG_MASK) 9357 #define SYSCON_FLASHCFG_DATACFG_MASK (0xCU) 9358 #define SYSCON_FLASHCFG_DATACFG_SHIFT (2U) 9359 /*! DATACFG - Data read configuration. This field determines how flash accelerator buffers are used for data accesses. 9360 * 0b00..Data accesses from flash are not buffered. Every data access from the CPU results in a read of the flash memory. 9361 * 0b01..One buffer is used for all data accesses. 9362 * 0b10..All buffers may be used for data accesses. 9363 * 0b11..Reserved setting, do not use. 9364 */ 9365 #define SYSCON_FLASHCFG_DATACFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_DATACFG_SHIFT)) & SYSCON_FLASHCFG_DATACFG_MASK) 9366 #define SYSCON_FLASHCFG_ACCEL_MASK (0x10U) 9367 #define SYSCON_FLASHCFG_ACCEL_SHIFT (4U) 9368 /*! ACCEL - Acceleration enable. 9369 * 0b0..Flash acceleration is disabled. Every flash read (including those fulfilled from a buffer) takes FLASHTIM 9370 * + 1 system clocks. This allows more determinism at a cost of performance. 9371 * 0b1..Flash acceleration is enabled. Performance is enhanced, dependent on other FLASHCFG settings. 9372 */ 9373 #define SYSCON_FLASHCFG_ACCEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_ACCEL_SHIFT)) & SYSCON_FLASHCFG_ACCEL_MASK) 9374 #define SYSCON_FLASHCFG_PREFEN_MASK (0x20U) 9375 #define SYSCON_FLASHCFG_PREFEN_SHIFT (5U) 9376 /*! PREFEN - Prefetch enable. 9377 * 0b0..No instruction prefetch is performed. 9378 * 0b1..If the FETCHCFG field is not 0, the next flash line following the current execution address is 9379 * automatically prefetched if it is not already buffered. 9380 */ 9381 #define SYSCON_FLASHCFG_PREFEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_PREFEN_SHIFT)) & SYSCON_FLASHCFG_PREFEN_MASK) 9382 #define SYSCON_FLASHCFG_PREFOVR_MASK (0x40U) 9383 #define SYSCON_FLASHCFG_PREFOVR_SHIFT (6U) 9384 /*! PREFOVR - Prefetch override. This bit only applies when PREFEN = 1 and a buffered instruction is 9385 * completing for which the next flash line is not already buffered or being prefetched. 9386 * 0b0..Any previously initiated prefetch will be completed. 9387 * 0b1..Any previously initiated prefetch will be aborted, and the next flash line following the current 9388 * execution address will be prefetched if not already buffered. 9389 */ 9390 #define SYSCON_FLASHCFG_PREFOVR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_PREFOVR_SHIFT)) & SYSCON_FLASHCFG_PREFOVR_MASK) 9391 #define SYSCON_FLASHCFG_FLASHTIM_MASK (0xF000U) 9392 #define SYSCON_FLASHCFG_FLASHTIM_SHIFT (12U) 9393 /*! FLASHTIM - Flash memory access time. The number of system clocks used for flash accesses is equal to FLASHTIM +1. 9394 * 0b0000..1 system clock flash access time (for system clock rates up to 12 MHz). 9395 * 0b0001..2 system clocks flash access time (for system clock rates up to 30 MHz). 9396 * 0b0010..3 system clocks flash access time (for system clock rates up to 60 MHz). 9397 * 0b0011..4 system clocks flash access time (for system clock rates up to 85 MHz). 9398 * 0b0100..5 system clocks flash access time (for system clock rates up to 100 MHz). 9399 */ 9400 #define SYSCON_FLASHCFG_FLASHTIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_FLASHTIM_SHIFT)) & SYSCON_FLASHCFG_FLASHTIM_MASK) 9401 /*! @} */ 9402 9403 /*! @name USBCLKCTRL - USB clock control */ 9404 /*! @{ */ 9405 #define SYSCON_USBCLKCTRL_POL_CLK_MASK (0x2U) 9406 #define SYSCON_USBCLKCTRL_POL_CLK_SHIFT (1U) 9407 /*! POL_CLK - USB_NEED_CLK polarity for triggering the USB wake-up interrupt 9408 * 0b0..Falling edge of the USB_NEED_CLK triggers the USB wake-up (default). 9409 * 0b1..Rising edge of the USB_NEED_CLK triggers the USB wake-up. 9410 */ 9411 #define SYSCON_USBCLKCTRL_POL_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBCLKCTRL_POL_CLK_SHIFT)) & SYSCON_USBCLKCTRL_POL_CLK_MASK) 9412 /*! @} */ 9413 9414 /*! @name USBCLKSTAT - USB clock status */ 9415 /*! @{ */ 9416 #define SYSCON_USBCLKSTAT_NEED_CLKST_MASK (0x1U) 9417 #define SYSCON_USBCLKSTAT_NEED_CLKST_SHIFT (0U) 9418 /*! NEED_CLKST - USB_NEED_CLK signal status 9419 * 0b0..Low 9420 * 0b1..High 9421 */ 9422 #define SYSCON_USBCLKSTAT_NEED_CLKST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBCLKSTAT_NEED_CLKST_SHIFT)) & SYSCON_USBCLKSTAT_NEED_CLKST_MASK) 9423 /*! @} */ 9424 9425 /*! @name FREQMECTRL - Frequency measure register */ 9426 /*! @{ */ 9427 #define SYSCON_FREQMECTRL_CAPVAL_MASK (0x3FFFU) 9428 #define SYSCON_FREQMECTRL_CAPVAL_SHIFT (0U) 9429 /*! CAPVAL - Stores the capture result which is used to calculate the frequency of the target clock. This field is read-only. 9430 */ 9431 #define SYSCON_FREQMECTRL_CAPVAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FREQMECTRL_CAPVAL_SHIFT)) & SYSCON_FREQMECTRL_CAPVAL_MASK) 9432 #define SYSCON_FREQMECTRL_PROG_MASK (0x80000000U) 9433 #define SYSCON_FREQMECTRL_PROG_SHIFT (31U) 9434 /*! PROG - Set this bit to one to initiate a frequency measurement cycle. Hardware clears this bit 9435 * when the measurement cycle has completed and there is valid capture data in the CAPVAL field 9436 * (bits 13:0). 9437 */ 9438 #define SYSCON_FREQMECTRL_PROG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FREQMECTRL_PROG_SHIFT)) & SYSCON_FREQMECTRL_PROG_MASK) 9439 /*! @} */ 9440 9441 /*! @name MCLKIO - MCLK input/output control */ 9442 /*! @{ */ 9443 #define SYSCON_MCLKIO_DIR_MASK (0x1U) 9444 #define SYSCON_MCLKIO_DIR_SHIFT (0U) 9445 /*! DIR - MCLK direction control. 9446 * 0b0..The MCLK function is an input. 9447 * 0b1..The MCLK function is an output. 9448 */ 9449 #define SYSCON_MCLKIO_DIR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKIO_DIR_SHIFT)) & SYSCON_MCLKIO_DIR_MASK) 9450 /*! @} */ 9451 9452 /*! @name FROCTRL - FRO oscillator control */ 9453 /*! @{ */ 9454 #define SYSCON_FROCTRL_TRIM_MASK (0x3FFFU) 9455 #define SYSCON_FROCTRL_TRIM_SHIFT (0U) 9456 /*! TRIM - This value is factory trimmed to account for bias and temperature compensation. The value 9457 * should not be changed by software. Also see the WRTRIM bit description. 9458 */ 9459 #define SYSCON_FROCTRL_TRIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_TRIM_SHIFT)) & SYSCON_FROCTRL_TRIM_MASK) 9460 #define SYSCON_FROCTRL_SEL_MASK (0x4000U) 9461 #define SYSCON_FROCTRL_SEL_SHIFT (14U) 9462 /*! SEL - Select the fro_hf output frequency. This bit can only be changed by software when the 9463 * WRTRIM bit = 1. Note that the factory trim values are for the 96 MHz FRO only. 9464 * 0b0..48 MHz 9465 * 0b1..96 MHz 9466 */ 9467 #define SYSCON_FROCTRL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_SEL_SHIFT)) & SYSCON_FROCTRL_SEL_MASK) 9468 #define SYSCON_FROCTRL_FREQTRIM_MASK (0xFF0000U) 9469 #define SYSCON_FROCTRL_FREQTRIM_SHIFT (16U) 9470 /*! FREQTRIM - Frequency trim. Boot code configures this to a device-specific factory trim value for 9471 * the 96 MHz FRO. If USBCLKADJ = 1, this field is read-only and provides the value resulting 9472 * from USB rate adjustment. See the USBMODCFG flag regarding reading this field. Application code 9473 * may adjust this field when USBCLKADJ = 0. A single step of FREQTRIM is roughly equivalent to 9474 * 0.1% of the selected FRO frequency. 9475 */ 9476 #define SYSCON_FROCTRL_FREQTRIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_FREQTRIM_SHIFT)) & SYSCON_FROCTRL_FREQTRIM_MASK) 9477 #define SYSCON_FROCTRL_USBCLKADJ_MASK (0x1000000U) 9478 #define SYSCON_FROCTRL_USBCLKADJ_SHIFT (24U) 9479 /*! USBCLKADJ - USB clock adjust mode. 9480 * 0b0..Normal operation. 9481 * 0b1..Automatic USB rate adjustment mode. If the USB FS device peripheral is enabled and connected to a USB 9482 * host, it provides clock adjustment information to the FRO based on SOF packets. USB rate adjustment requires 9483 * a number of cycles to take place. the USBMODCHG bit (see below) indicates when initial adjustment is 9484 * complete, and when later adjustments are in progress. software must not alter TRIM and FREQTRIM while USBCLKADJ 9485 * = 1. see USBCLKADJ usage notes below this table. 9486 */ 9487 #define SYSCON_FROCTRL_USBCLKADJ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_USBCLKADJ_SHIFT)) & SYSCON_FROCTRL_USBCLKADJ_MASK) 9488 #define SYSCON_FROCTRL_USBMODCHG_MASK (0x2000000U) 9489 #define SYSCON_FROCTRL_USBMODCHG_SHIFT (25U) 9490 /*! USBMODCHG - USB Mode value Change flag. When 1, indicates that the USB trim is currently being 9491 * updated (or is still starting up) and software should wait to read FREQTRIM. Update occurs at 9492 * most once per millisecond. 9493 */ 9494 #define SYSCON_FROCTRL_USBMODCHG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_USBMODCHG_SHIFT)) & SYSCON_FROCTRL_USBMODCHG_MASK) 9495 #define SYSCON_FROCTRL_HSPDCLK_MASK (0x40000000U) 9496 #define SYSCON_FROCTRL_HSPDCLK_SHIFT (30U) 9497 /*! HSPDCLK - High speed clock disable. Allows disabling the highs-speed FRO output if it is not needed. 9498 * 0b0..The high-speed FRO output is disabled. 9499 * 0b1..The selected high-speed FRO output (48 MHz or 96 MHz) is enabled. 9500 */ 9501 #define SYSCON_FROCTRL_HSPDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_HSPDCLK_SHIFT)) & SYSCON_FROCTRL_HSPDCLK_MASK) 9502 #define SYSCON_FROCTRL_WRTRIM_MASK (0x80000000U) 9503 #define SYSCON_FROCTRL_WRTRIM_SHIFT (31U) 9504 /*! WRTRIM - Write Trim value. Must be written to 1 to modify the SEL or TRIM fields, during the 9505 * same write. This bit always reads as 0. 9506 */ 9507 #define SYSCON_FROCTRL_WRTRIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_WRTRIM_SHIFT)) & SYSCON_FROCTRL_WRTRIM_MASK) 9508 /*! @} */ 9509 9510 /*! @name WDTOSCCTRL - Watchdog oscillator control */ 9511 /*! @{ */ 9512 #define SYSCON_WDTOSCCTRL_DIVSEL_MASK (0x1FU) 9513 #define SYSCON_WDTOSCCTRL_DIVSEL_SHIFT (0U) 9514 /*! DIVSEL - Divider select. Selects the value of the divider that adjusts the output of the 9515 * oscillator. 0x00 = divide by 2 0x01 = divide by 4 0x02 = divide by 6 up to 0x1E = divide by 62 0x1F = 9516 * divide by 64 9517 */ 9518 #define SYSCON_WDTOSCCTRL_DIVSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTOSCCTRL_DIVSEL_SHIFT)) & SYSCON_WDTOSCCTRL_DIVSEL_MASK) 9519 #define SYSCON_WDTOSCCTRL_FREQSEL_MASK (0x3E0U) 9520 #define SYSCON_WDTOSCCTRL_FREQSEL_SHIFT (5U) 9521 /*! FREQSEL - Frequency select. Selects the frequency of the oscillator. 0x00 = invalid setting when 9522 * watchdog oscillator is running 0x01 = 0.4 MHz 0x02 = 0.6 MHz 0x03 = 0.75 MHz 0x04 = 0.9 MHz 9523 * 0x05 = 1.0 MHz 0x06 = 1.2 MHz 0x07 = 1.3 MHz 0x08 = 1.4 MHz 0x09 = 1.5 MHz 0x0A = 1.6 MHz 0x0B 9524 * = 1.7 MHz 0x0C = 1.8 MHz 0x0D = 1.9 MHz 0x0E = 2.0 MHz 0x0F = 2.05 MHz 0x10 = 2.1 MHz 0x11 = 9525 * 2.2 MHz 0x12 = 2.25 MHz 0x13 = 2.3 MHz 0x14 = 2.4 MHz 0x15 = 2.45 MHz 0x16 = 2.5 MHz 0x17 = 2.6 9526 * MHz 0x18 = 2.65 MHz 0x19 = 2.7 MHz 0x1A = 2.8 MHz 0x1B = 2.85 MHz 0x1C = 2.9 MHz 0x1D = 2.95 9527 * MHz 0x1E = 3.0 MHz 0x1F = 3.05 MHz 9528 */ 9529 #define SYSCON_WDTOSCCTRL_FREQSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT)) & SYSCON_WDTOSCCTRL_FREQSEL_MASK) 9530 /*! @} */ 9531 9532 /*! @name RTCOSCCTRL - RTC oscillator 32 kHz output control */ 9533 /*! @{ */ 9534 #define SYSCON_RTCOSCCTRL_EN_MASK (0x1U) 9535 #define SYSCON_RTCOSCCTRL_EN_SHIFT (0U) 9536 /*! EN - RTC 32 kHz clock enable. 9537 * 0b0..Disabled. RTC clock off. 9538 * 0b1..Enabled. RTC clock on. 9539 */ 9540 #define SYSCON_RTCOSCCTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_RTCOSCCTRL_EN_SHIFT)) & SYSCON_RTCOSCCTRL_EN_MASK) 9541 /*! @} */ 9542 9543 /*! @name SYSPLLCTRL - PLL control */ 9544 /*! @{ */ 9545 #define SYSCON_SYSPLLCTRL_SELR_MASK (0xFU) 9546 #define SYSCON_SYSPLLCTRL_SELR_SHIFT (0U) 9547 /*! SELR - Bandwidth select R value 9548 */ 9549 #define SYSCON_SYSPLLCTRL_SELR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_SELR_SHIFT)) & SYSCON_SYSPLLCTRL_SELR_MASK) 9550 #define SYSCON_SYSPLLCTRL_SELI_MASK (0x3F0U) 9551 #define SYSCON_SYSPLLCTRL_SELI_SHIFT (4U) 9552 /*! SELI - Bandwidth select I value. 9553 */ 9554 #define SYSCON_SYSPLLCTRL_SELI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_SELI_SHIFT)) & SYSCON_SYSPLLCTRL_SELI_MASK) 9555 #define SYSCON_SYSPLLCTRL_SELP_MASK (0x7C00U) 9556 #define SYSCON_SYSPLLCTRL_SELP_SHIFT (10U) 9557 /*! SELP - Bandwidth select P value 9558 */ 9559 #define SYSCON_SYSPLLCTRL_SELP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_SELP_SHIFT)) & SYSCON_SYSPLLCTRL_SELP_MASK) 9560 #define SYSCON_SYSPLLCTRL_BYPASS_MASK (0x8000U) 9561 #define SYSCON_SYSPLLCTRL_BYPASS_SHIFT (15U) 9562 /*! BYPASS - PLL bypass control. 9563 * 0b0..Bypass disabled. PLL CCO is sent to the PLL post-dividers. 9564 * 0b1..Bypass enabled. PLL input clock is sent directly to the PLL output (default). 9565 */ 9566 #define SYSCON_SYSPLLCTRL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_BYPASS_SHIFT)) & SYSCON_SYSPLLCTRL_BYPASS_MASK) 9567 #define SYSCON_SYSPLLCTRL_BYPASSCCODIV2_MASK (0x10000U) 9568 #define SYSCON_SYSPLLCTRL_BYPASSCCODIV2_SHIFT (16U) 9569 /*! BYPASSCCODIV2 - Bypass feedback clock divide by 2. 9570 * 0b0..Divide by 2. The CCO feedback clock is divided by 2 in addition to the programmed M divide. 9571 * 0b1..Bypass. The CCO feedback clock is divided only by the programmed M divide. 9572 */ 9573 #define SYSCON_SYSPLLCTRL_BYPASSCCODIV2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_BYPASSCCODIV2_SHIFT)) & SYSCON_SYSPLLCTRL_BYPASSCCODIV2_MASK) 9574 #define SYSCON_SYSPLLCTRL_UPLIMOFF_MASK (0x20000U) 9575 #define SYSCON_SYSPLLCTRL_UPLIMOFF_SHIFT (17U) 9576 /*! UPLIMOFF - Disable upper frequency limiter. 9577 * 0b0..Normal mode. 9578 * 0b1..Upper frequency limiter disabled. 9579 */ 9580 #define SYSCON_SYSPLLCTRL_UPLIMOFF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_UPLIMOFF_SHIFT)) & SYSCON_SYSPLLCTRL_UPLIMOFF_MASK) 9581 #define SYSCON_SYSPLLCTRL_BANDSEL_MASK (0x40000U) 9582 #define SYSCON_SYSPLLCTRL_BANDSEL_SHIFT (18U) 9583 /*! BANDSEL - PLL filter control. Set this bit to one when the spread spectrum controller is 9584 * disabled or at low frequencies. For spread spectrum mode: SEL_EXT = 0, BANDSEL = 0, and UPLIMOFF = 1. 9585 * 0b0..SSCG control. The PLL filter uses the parameters derived from the spread spectrum controller. 9586 * 0b1..MDEC control. The PLL filter uses the programmable fields SELP, SELR, and SELI in this register to control the filter constants. 9587 */ 9588 #define SYSCON_SYSPLLCTRL_BANDSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_BANDSEL_SHIFT)) & SYSCON_SYSPLLCTRL_BANDSEL_MASK) 9589 #define SYSCON_SYSPLLCTRL_DIRECTI_MASK (0x80000U) 9590 #define SYSCON_SYSPLLCTRL_DIRECTI_SHIFT (19U) 9591 /*! DIRECTI - PLL0 direct input enable 9592 * 0b0..Disabled. The PLL input divider (N divider) output is used to drive the PLL CCO. 9593 * 0b1..Enabled. The PLL input divider (N divider) is bypassed. the PLL input clock is used directly to drive the PLL CCO input. 9594 */ 9595 #define SYSCON_SYSPLLCTRL_DIRECTI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_DIRECTI_SHIFT)) & SYSCON_SYSPLLCTRL_DIRECTI_MASK) 9596 #define SYSCON_SYSPLLCTRL_DIRECTO_MASK (0x100000U) 9597 #define SYSCON_SYSPLLCTRL_DIRECTO_SHIFT (20U) 9598 /*! DIRECTO - PLL0 direct output enable. 9599 * 0b0..Disabled. The PLL output divider (P divider) is used to create the PLL output. 9600 * 0b1..Enabled. The PLL output divider (P divider) is bypassed, the PLL CCO output is used as the PLL output. 9601 */ 9602 #define SYSCON_SYSPLLCTRL_DIRECTO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_DIRECTO_SHIFT)) & SYSCON_SYSPLLCTRL_DIRECTO_MASK) 9603 /*! @} */ 9604 9605 /*! @name SYSPLLSTAT - PLL status */ 9606 /*! @{ */ 9607 #define SYSCON_SYSPLLSTAT_LOCK_MASK (0x1U) 9608 #define SYSCON_SYSPLLSTAT_LOCK_SHIFT (0U) 9609 /*! LOCK - PLL0 lock indicator 9610 */ 9611 #define SYSCON_SYSPLLSTAT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSTAT_LOCK_SHIFT)) & SYSCON_SYSPLLSTAT_LOCK_MASK) 9612 /*! @} */ 9613 9614 /*! @name SYSPLLNDEC - PLL N decoder */ 9615 /*! @{ */ 9616 #define SYSCON_SYSPLLNDEC_NDEC_MASK (0x3FFU) 9617 #define SYSCON_SYSPLLNDEC_NDEC_SHIFT (0U) 9618 /*! NDEC - Decoded N-divider coefficient value. 9619 */ 9620 #define SYSCON_SYSPLLNDEC_NDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLNDEC_NDEC_SHIFT)) & SYSCON_SYSPLLNDEC_NDEC_MASK) 9621 #define SYSCON_SYSPLLNDEC_NREQ_MASK (0x400U) 9622 #define SYSCON_SYSPLLNDEC_NREQ_SHIFT (10U) 9623 /*! NREQ - NDEC reload request. When a 1 is written to this bit, the NDEC value is loaded into the 9624 * PLL. Must be cleared by software for any subsequent load, or the PLL can be powered down and 9625 * back up via the PDEN_SYS_PLL bit in the PDRUNCFG register if the NDEC value is changed. 9626 */ 9627 #define SYSCON_SYSPLLNDEC_NREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLNDEC_NREQ_SHIFT)) & SYSCON_SYSPLLNDEC_NREQ_MASK) 9628 /*! @} */ 9629 9630 /*! @name SYSPLLPDEC - PLL P decoder */ 9631 /*! @{ */ 9632 #define SYSCON_SYSPLLPDEC_PDEC_MASK (0x7FU) 9633 #define SYSCON_SYSPLLPDEC_PDEC_SHIFT (0U) 9634 /*! PDEC - Decoded P-divider coefficient value. 9635 */ 9636 #define SYSCON_SYSPLLPDEC_PDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLPDEC_PDEC_SHIFT)) & SYSCON_SYSPLLPDEC_PDEC_MASK) 9637 #define SYSCON_SYSPLLPDEC_PREQ_MASK (0x80U) 9638 #define SYSCON_SYSPLLPDEC_PREQ_SHIFT (7U) 9639 /*! PREQ - PDEC reload request. When a 1 is written to this bit, the PDEC value is loaded into the 9640 * PLL. Must be cleared by software for any subsequent load, or the PLL can be powered down and 9641 * back up via the PDEN_SYS_PLL bit in the PDRUNCFG register if the PDEC value is changed. 9642 */ 9643 #define SYSCON_SYSPLLPDEC_PREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLPDEC_PREQ_SHIFT)) & SYSCON_SYSPLLPDEC_PREQ_MASK) 9644 /*! @} */ 9645 9646 /*! @name SYSPLLSSCTRL0 - PLL spread spectrum control 0 */ 9647 /*! @{ */ 9648 #define SYSCON_SYSPLLSSCTRL0_MDEC_MASK (0x1FFFFU) 9649 #define SYSCON_SYSPLLSSCTRL0_MDEC_SHIFT (0U) 9650 /*! MDEC - Decoded M-divider coefficient value. 9651 */ 9652 #define SYSCON_SYSPLLSSCTRL0_MDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL0_MDEC_SHIFT)) & SYSCON_SYSPLLSSCTRL0_MDEC_MASK) 9653 #define SYSCON_SYSPLLSSCTRL0_MREQ_MASK (0x20000U) 9654 #define SYSCON_SYSPLLSSCTRL0_MREQ_SHIFT (17U) 9655 /*! MREQ - MDEC reload request. When a 1 is written to this bit, the MDEC value is loaded into the 9656 * PLL. Must be cleared by software for any subsequent load, or the PLL can be powered down and 9657 * back up via the PDEN_SYS_PLL bit in the PDRUNCFG register if the MDEC value is changed. 9658 */ 9659 #define SYSCON_SYSPLLSSCTRL0_MREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL0_MREQ_SHIFT)) & SYSCON_SYSPLLSSCTRL0_MREQ_MASK) 9660 #define SYSCON_SYSPLLSSCTRL0_SEL_EXT_MASK (0x40000U) 9661 #define SYSCON_SYSPLLSSCTRL0_SEL_EXT_SHIFT (18U) 9662 /*! SEL_EXT - Select spread spectrum mode. Selects the source of the feedback divider value. For 9663 * normal mode, this must be the value from the MDEC field in this register. For spread spectrum 9664 * mode: SEL_EXT = 0, BANDSEL = 0, and UPLIMOFF = 1. 9665 */ 9666 #define SYSCON_SYSPLLSSCTRL0_SEL_EXT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL0_SEL_EXT_SHIFT)) & SYSCON_SYSPLLSSCTRL0_SEL_EXT_MASK) 9667 /*! @} */ 9668 9669 /*! @name SYSPLLSSCTRL1 - PLL spread spectrum control 1 */ 9670 /*! @{ */ 9671 #define SYSCON_SYSPLLSSCTRL1_MD_MASK (0x7FFFFU) 9672 #define SYSCON_SYSPLLSSCTRL1_MD_SHIFT (0U) 9673 /*! MD - M- divider value with fraction. MD[18:11]: integer portion of the feedback divider value. 9674 * MD[10:0]: fractional portion of the feedback divider value. In fractional mode, fcco = (2 - 9675 * BYPASSCCODIV2) x (MD x 2^-11) x Fref 9676 */ 9677 #define SYSCON_SYSPLLSSCTRL1_MD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL1_MD_SHIFT)) & SYSCON_SYSPLLSSCTRL1_MD_MASK) 9678 #define SYSCON_SYSPLLSSCTRL1_MDREQ_MASK (0x80000U) 9679 #define SYSCON_SYSPLLSSCTRL1_MDREQ_SHIFT (19U) 9680 /*! MDREQ - MD reload request. When a 1 is written to this bit, the MD value is loaded into the PLL. 9681 * This bit is cleared when the load is complete 9682 */ 9683 #define SYSCON_SYSPLLSSCTRL1_MDREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL1_MDREQ_SHIFT)) & SYSCON_SYSPLLSSCTRL1_MDREQ_MASK) 9684 #define SYSCON_SYSPLLSSCTRL1_MF_MASK (0x700000U) 9685 #define SYSCON_SYSPLLSSCTRL1_MF_SHIFT (20U) 9686 /*! MF - Programmable modulation frequency fm = Fref/Nss with Fref = Fin/N 0b000 => Nss = 512 (fm _ 9687 * 3.9 - 7.8 kHz) 0b001 => Nss _ 384 (fm _ 5.2 - 10.4 kHz) 0b010 => Nss = 256 (fm _ 7.8 - 15.6 9688 * kHz) 0b011 => Nss = 128 (fm _ 15.6 - 31.3 kHz) 0b100 => Nss = 64 (fm _ 32.3 - 64.5 kHz) 0b101 => 9689 * Nss = 32 (fm _ 62.5- 125 kHz) 0b110 => Nss _ 24 (fm _ 83.3- 166.6 kHz) 0b111 => Nss = 16 (fm 9690 * _ 125- 250 kHz) 9691 */ 9692 #define SYSCON_SYSPLLSSCTRL1_MF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL1_MF_SHIFT)) & SYSCON_SYSPLLSSCTRL1_MF_MASK) 9693 #define SYSCON_SYSPLLSSCTRL1_MR_MASK (0x3800000U) 9694 #define SYSCON_SYSPLLSSCTRL1_MR_SHIFT (23U) 9695 /*! MR - Programmable frequency modulation depth. 0 = no spread. _fmodpk-pk = Fref x k/Fcco = 9696 * k/MDdec 0b000 -> k = 0 (no spread spectrum) 0b001 => k _ 1 0b010 => k _ 1.5 0b011 => k _ 2 0b100 => 9697 * k _ 3 0b101 => k _ 4 0b110 => k _ 6 0b111 => k _ 8 9698 */ 9699 #define SYSCON_SYSPLLSSCTRL1_MR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL1_MR_SHIFT)) & SYSCON_SYSPLLSSCTRL1_MR_MASK) 9700 #define SYSCON_SYSPLLSSCTRL1_MC_MASK (0xC000000U) 9701 #define SYSCON_SYSPLLSSCTRL1_MC_SHIFT (26U) 9702 /*! MC - Modulation waveform control. 0 = no compensation. Compensation for low pass filtering of 9703 * the PLL to get a triangular modulation at the output of the PLL, giving a flat frequency 9704 * spectrum. 0b00 => no compensation 0b10 => recommended setting 0b11 => max. compensation 9705 */ 9706 #define SYSCON_SYSPLLSSCTRL1_MC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL1_MC_SHIFT)) & SYSCON_SYSPLLSSCTRL1_MC_MASK) 9707 #define SYSCON_SYSPLLSSCTRL1_PD_MASK (0x10000000U) 9708 #define SYSCON_SYSPLLSSCTRL1_PD_SHIFT (28U) 9709 /*! PD - Spread spectrum power-down. 9710 * 0b0..Enabled. Spread spectrum controller is enabled 9711 * 0b1..Disabled. Spread spectrum controller is disabled. 9712 */ 9713 #define SYSCON_SYSPLLSSCTRL1_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL1_PD_SHIFT)) & SYSCON_SYSPLLSSCTRL1_PD_MASK) 9714 #define SYSCON_SYSPLLSSCTRL1_DITHER_MASK (0x20000000U) 9715 #define SYSCON_SYSPLLSSCTRL1_DITHER_SHIFT (29U) 9716 /*! DITHER - Select modulation frequency. 9717 * 0b0..Fixed. Fixed modulation frequency. 9718 * 0b1..Dither. Randomly dither between two modulation frequencies. 9719 */ 9720 #define SYSCON_SYSPLLSSCTRL1_DITHER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL1_DITHER_SHIFT)) & SYSCON_SYSPLLSSCTRL1_DITHER_MASK) 9721 /*! @} */ 9722 9723 /*! @name PDSLEEPCFG - Sleep configuration register n */ 9724 /*! @{ */ 9725 #define SYSCON_PDSLEEPCFG_PD_SLEEP_MASK (0xFFFFFFFFU) 9726 #define SYSCON_PDSLEEPCFG_PD_SLEEP_SHIFT (0U) 9727 /*! PD_SLEEP - See bit descriptions in the PDRUNCFGn register. 9728 */ 9729 #define SYSCON_PDSLEEPCFG_PD_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PD_SLEEP_SHIFT)) & SYSCON_PDSLEEPCFG_PD_SLEEP_MASK) 9730 /*! @} */ 9731 9732 /* The count of SYSCON_PDSLEEPCFG */ 9733 #define SYSCON_PDSLEEPCFG_COUNT (2U) 9734 9735 /*! @name PDRUNCFG - Power configuration register n */ 9736 /*! @{ */ 9737 #define SYSCON_PDRUNCFG_PDEN_FRO_MASK (0x10U) 9738 #define SYSCON_PDRUNCFG_PDEN_FRO_SHIFT (4U) 9739 /*! PDEN_FRO - FRO oscillator. 0 = Powered; 1 = Powered down. 9740 */ 9741 #define SYSCON_PDRUNCFG_PDEN_FRO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_FRO_SHIFT)) & SYSCON_PDRUNCFG_PDEN_FRO_MASK) 9742 #define SYSCON_PDRUNCFG_PD_FLASH_MASK (0x20U) 9743 #define SYSCON_PDRUNCFG_PD_FLASH_SHIFT (5U) 9744 /*! PD_FLASH - Part of flash power control. 9745 */ 9746 #define SYSCON_PDRUNCFG_PD_FLASH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PD_FLASH_SHIFT)) & SYSCON_PDRUNCFG_PD_FLASH_MASK) 9747 #define SYSCON_PDRUNCFG_PDEN_TS_MASK (0x40U) 9748 #define SYSCON_PDRUNCFG_PDEN_TS_SHIFT (6U) 9749 /*! PDEN_TS - Temp sensor. 0 = Powered; 1 = Powered down. 9750 */ 9751 #define SYSCON_PDRUNCFG_PDEN_TS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_TS_SHIFT)) & SYSCON_PDRUNCFG_PDEN_TS_MASK) 9752 #define SYSCON_PDRUNCFG_PDEN_BOD_RST_MASK (0x80U) 9753 #define SYSCON_PDRUNCFG_PDEN_BOD_RST_SHIFT (7U) 9754 /*! PDEN_BOD_RST - Brown-out Detect reset. 0 = Powered; 1 = Powered down. 9755 */ 9756 #define SYSCON_PDRUNCFG_PDEN_BOD_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_BOD_RST_SHIFT)) & SYSCON_PDRUNCFG_PDEN_BOD_RST_MASK) 9757 #define SYSCON_PDRUNCFG_PDEN_BOD_INTR_MASK (0x100U) 9758 #define SYSCON_PDRUNCFG_PDEN_BOD_INTR_SHIFT (8U) 9759 /*! PDEN_BOD_INTR - Brown-out Detect interrupt. 0 = Powered; 1 = Powered down. 9760 */ 9761 #define SYSCON_PDRUNCFG_PDEN_BOD_INTR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_BOD_INTR_SHIFT)) & SYSCON_PDRUNCFG_PDEN_BOD_INTR_MASK) 9762 #define SYSCON_PDRUNCFG_PDEN_ADC0_MASK (0x400U) 9763 #define SYSCON_PDRUNCFG_PDEN_ADC0_SHIFT (10U) 9764 /*! PDEN_ADC0 - ADC0. 0 = Powered; 1 = Powered down. 9765 */ 9766 #define SYSCON_PDRUNCFG_PDEN_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_ADC0_SHIFT)) & SYSCON_PDRUNCFG_PDEN_ADC0_MASK) 9767 #define SYSCON_PDRUNCFG_PD_VDDFLASH_MASK (0x800U) 9768 #define SYSCON_PDRUNCFG_PD_VDDFLASH_SHIFT (11U) 9769 /*! PD_VDDFLASH - Part of flash power control. 9770 */ 9771 #define SYSCON_PDRUNCFG_PD_VDDFLASH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PD_VDDFLASH_SHIFT)) & SYSCON_PDRUNCFG_PD_VDDFLASH_MASK) 9772 #define SYSCON_PDRUNCFG_LP_VDDFLASH_MASK (0x1000U) 9773 #define SYSCON_PDRUNCFG_LP_VDDFLASH_SHIFT (12U) 9774 /*! LP_VDDFLASH - Part of flash power control. 9775 */ 9776 #define SYSCON_PDRUNCFG_LP_VDDFLASH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_LP_VDDFLASH_SHIFT)) & SYSCON_PDRUNCFG_LP_VDDFLASH_MASK) 9777 #define SYSCON_PDRUNCFG_PDEN_SRAM0_MASK (0x2000U) 9778 #define SYSCON_PDRUNCFG_PDEN_SRAM0_SHIFT (13U) 9779 /*! PDEN_SRAM0 - SRAM0. 0 = Powered; 1 = Powered down. 9780 */ 9781 #define SYSCON_PDRUNCFG_PDEN_SRAM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SRAM0_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SRAM0_MASK) 9782 #define SYSCON_PDRUNCFG_PDEN_SRAM1_MASK (0x4000U) 9783 #define SYSCON_PDRUNCFG_PDEN_SRAM1_SHIFT (14U) 9784 /*! PDEN_SRAM1 - SRAM1. 0 = Powered; 1 = Powered down. 9785 */ 9786 #define SYSCON_PDRUNCFG_PDEN_SRAM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SRAM1_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SRAM1_MASK) 9787 #define SYSCON_PDRUNCFG_PDEN_SRAM2_MASK (0x8000U) 9788 #define SYSCON_PDRUNCFG_PDEN_SRAM2_SHIFT (15U) 9789 /*! PDEN_SRAM2 - SRAM2. 0 = Powered; 1 = Powered down. 9790 */ 9791 #define SYSCON_PDRUNCFG_PDEN_SRAM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SRAM2_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SRAM2_MASK) 9792 #define SYSCON_PDRUNCFG_PDEN_SRAMX_MASK (0x10000U) 9793 #define SYSCON_PDRUNCFG_PDEN_SRAMX_SHIFT (16U) 9794 /*! PDEN_SRAMX - SRAMX. 0 = Powered; 1 = Powered down. 9795 */ 9796 #define SYSCON_PDRUNCFG_PDEN_SRAMX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SRAMX_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SRAMX_MASK) 9797 #define SYSCON_PDRUNCFG_PDEN_ROM_MASK (0x20000U) 9798 #define SYSCON_PDRUNCFG_PDEN_ROM_SHIFT (17U) 9799 /*! PDEN_ROM - ROM. 0 = Powered; 1 = Powered down. 9800 */ 9801 #define SYSCON_PDRUNCFG_PDEN_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_ROM_SHIFT)) & SYSCON_PDRUNCFG_PDEN_ROM_MASK) 9802 #define SYSCON_PDRUNCFG_PD_VDDHV_ENA_MASK (0x40000U) 9803 #define SYSCON_PDRUNCFG_PD_VDDHV_ENA_SHIFT (18U) 9804 /*! PD_VDDHV_ENA - Part of flash power control. 9805 */ 9806 #define SYSCON_PDRUNCFG_PD_VDDHV_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PD_VDDHV_ENA_SHIFT)) & SYSCON_PDRUNCFG_PD_VDDHV_ENA_MASK) 9807 #define SYSCON_PDRUNCFG_PDEN_VDDA_MASK (0x80000U) 9808 #define SYSCON_PDRUNCFG_PDEN_VDDA_SHIFT (19U) 9809 /*! PDEN_VDDA - Vdda to the ADC, must be enabled for the ADC to work. Also see bit 23. 0 = Powered; 1 = Powered down. 9810 */ 9811 #define SYSCON_PDRUNCFG_PDEN_VDDA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VDDA_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VDDA_MASK) 9812 #define SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK (0x100000U) 9813 #define SYSCON_PDRUNCFG_PDEN_WDT_OSC_SHIFT (20U) 9814 /*! PDEN_WDT_OSC - Watchdog oscillator. 0 = Powered; 1 = Powered down. 9815 */ 9816 #define SYSCON_PDRUNCFG_PDEN_WDT_OSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_WDT_OSC_SHIFT)) & SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK) 9817 #define SYSCON_PDRUNCFG_PDEN_USB_PHY_MASK (0x200000U) 9818 #define SYSCON_PDRUNCFG_PDEN_USB_PHY_SHIFT (21U) 9819 /*! PDEN_USB_PHY - USB pin interface. 0 = Powered; 1 = Powered down. 9820 */ 9821 #define SYSCON_PDRUNCFG_PDEN_USB_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_USB_PHY_SHIFT)) & SYSCON_PDRUNCFG_PDEN_USB_PHY_MASK) 9822 #define SYSCON_PDRUNCFG_PDEN_SYS_PLL_MASK (0x400000U) 9823 #define SYSCON_PDRUNCFG_PDEN_SYS_PLL_SHIFT (22U) 9824 /*! PDEN_SYS_PLL - PLL0. 0 = Powered; 1 = Powered down. 9825 */ 9826 #define SYSCON_PDRUNCFG_PDEN_SYS_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SYS_PLL_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SYS_PLL_MASK) 9827 #define SYSCON_PDRUNCFG_PDEN_VREFP_MASK (0x800000U) 9828 #define SYSCON_PDRUNCFG_PDEN_VREFP_SHIFT (23U) 9829 /*! PDEN_VREFP - Vrefp to the ADC, must be enabled for the ADC to work. Also see bit 19. 0 = Powered; 1 = Powered down. 9830 */ 9831 #define SYSCON_PDRUNCFG_PDEN_VREFP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VREFP_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VREFP_MASK) 9832 #define SYSCON_PDRUNCFG_PD_FLASH_BG_MASK (0x2000000U) 9833 #define SYSCON_PDRUNCFG_PD_FLASH_BG_SHIFT (25U) 9834 /*! PD_FLASH_BG - Part of flash power control. 9835 */ 9836 #define SYSCON_PDRUNCFG_PD_FLASH_BG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PD_FLASH_BG_SHIFT)) & SYSCON_PDRUNCFG_PD_FLASH_BG_MASK) 9837 #define SYSCON_PDRUNCFG_PD_ALT_FLASH_IBG_MASK (0x10000000U) 9838 #define SYSCON_PDRUNCFG_PD_ALT_FLASH_IBG_SHIFT (28U) 9839 /*! PD_ALT_FLASH_IBG - Part of flash power control. 9840 */ 9841 #define SYSCON_PDRUNCFG_PD_ALT_FLASH_IBG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PD_ALT_FLASH_IBG_SHIFT)) & SYSCON_PDRUNCFG_PD_ALT_FLASH_IBG_MASK) 9842 #define SYSCON_PDRUNCFG_SEL_ALT_FLASH_IBG_MASK (0x20000000U) 9843 #define SYSCON_PDRUNCFG_SEL_ALT_FLASH_IBG_SHIFT (29U) 9844 /*! SEL_ALT_FLASH_IBG - Part of flash power control. 9845 */ 9846 #define SYSCON_PDRUNCFG_SEL_ALT_FLASH_IBG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_SEL_ALT_FLASH_IBG_SHIFT)) & SYSCON_PDRUNCFG_SEL_ALT_FLASH_IBG_MASK) 9847 /*! @} */ 9848 9849 /* The count of SYSCON_PDRUNCFG */ 9850 #define SYSCON_PDRUNCFG_COUNT (2U) 9851 9852 /*! @name PDRUNCFGSET - Set bits in PDRUNCFGn */ 9853 /*! @{ */ 9854 #define SYSCON_PDRUNCFGSET_PD_SET_MASK (0xFFFFFFFFU) 9855 #define SYSCON_PDRUNCFGSET_PD_SET_SHIFT (0U) 9856 /*! PD_SET - Writing ones to this register sets the corresponding bit or bits in the PDRUNCFG 9857 * register, if they are implemented. Bits that do not correspond to defined bits in PDRUNCFG are 9858 * reserved and only zeroes should be written to them. 9859 */ 9860 #define SYSCON_PDRUNCFGSET_PD_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PD_SET_SHIFT)) & SYSCON_PDRUNCFGSET_PD_SET_MASK) 9861 /*! @} */ 9862 9863 /* The count of SYSCON_PDRUNCFGSET */ 9864 #define SYSCON_PDRUNCFGSET_COUNT (2U) 9865 9866 /*! @name PDRUNCFGCLR - Clear bits in PDRUNCFGn */ 9867 /*! @{ */ 9868 #define SYSCON_PDRUNCFGCLR_PD_CLR_MASK (0xFFFFFFFFU) 9869 #define SYSCON_PDRUNCFGCLR_PD_CLR_SHIFT (0U) 9870 /*! PD_CLR - Writing ones to this register clears the corresponding bit or bits in the PDRUNCFG 9871 * register, if they are implemented. Bits that do not correspond to defined bits in PDRUNCFG are 9872 * reserved and only zeroes should be written to them. 9873 */ 9874 #define SYSCON_PDRUNCFGCLR_PD_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PD_CLR_SHIFT)) & SYSCON_PDRUNCFGCLR_PD_CLR_MASK) 9875 /*! @} */ 9876 9877 /* The count of SYSCON_PDRUNCFGCLR */ 9878 #define SYSCON_PDRUNCFGCLR_COUNT (2U) 9879 9880 /*! @name STARTERP - Start logic n wake-up enable register */ 9881 /*! @{ */ 9882 #define SYSCON_STARTERP_PINT4_MASK (0x1U) 9883 #define SYSCON_STARTERP_PINT4_SHIFT (0U) 9884 /*! PINT4 - GPIO pin interrupt 4 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern match. 9885 */ 9886 #define SYSCON_STARTERP_PINT4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_PINT4_SHIFT)) & SYSCON_STARTERP_PINT4_MASK) 9887 #define SYSCON_STARTERP_WDT_BOD_MASK (0x1U) 9888 #define SYSCON_STARTERP_WDT_BOD_SHIFT (0U) 9889 /*! WDT_BOD - WWDT and BOD interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. 9890 */ 9891 #define SYSCON_STARTERP_WDT_BOD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_WDT_BOD_SHIFT)) & SYSCON_STARTERP_WDT_BOD_MASK) 9892 #define SYSCON_STARTERP_DMA0_MASK (0x2U) 9893 #define SYSCON_STARTERP_DMA0_SHIFT (1U) 9894 /*! DMA0 - DMA0 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Typically used in sleep mode 9895 * only since the peripheral clock must be running for it to function. 9896 */ 9897 #define SYSCON_STARTERP_DMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_DMA0_SHIFT)) & SYSCON_STARTERP_DMA0_MASK) 9898 #define SYSCON_STARTERP_PINT5_MASK (0x2U) 9899 #define SYSCON_STARTERP_PINT5_SHIFT (1U) 9900 /*! PINT5 - GPIO pin interrupt 5 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern match. 9901 */ 9902 #define SYSCON_STARTERP_PINT5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_PINT5_SHIFT)) & SYSCON_STARTERP_PINT5_MASK) 9903 #define SYSCON_STARTERP_GINT0_MASK (0x4U) 9904 #define SYSCON_STARTERP_GINT0_SHIFT (2U) 9905 /*! GINT0 - Group interrupt 0 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. 9906 */ 9907 #define SYSCON_STARTERP_GINT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_GINT0_SHIFT)) & SYSCON_STARTERP_GINT0_MASK) 9908 #define SYSCON_STARTERP_PINT6_MASK (0x4U) 9909 #define SYSCON_STARTERP_PINT6_SHIFT (2U) 9910 /*! PINT6 - GPIO pin interrupt 6 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern match. 9911 */ 9912 #define SYSCON_STARTERP_PINT6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_PINT6_SHIFT)) & SYSCON_STARTERP_PINT6_MASK) 9913 #define SYSCON_STARTERP_GINT1_MASK (0x8U) 9914 #define SYSCON_STARTERP_GINT1_SHIFT (3U) 9915 /*! GINT1 - Group interrupt 1 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. 9916 */ 9917 #define SYSCON_STARTERP_GINT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_GINT1_SHIFT)) & SYSCON_STARTERP_GINT1_MASK) 9918 #define SYSCON_STARTERP_PINT7_MASK (0x8U) 9919 #define SYSCON_STARTERP_PINT7_SHIFT (3U) 9920 /*! PINT7 - GPIO pin interrupt 7 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern match. 9921 */ 9922 #define SYSCON_STARTERP_PINT7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_PINT7_SHIFT)) & SYSCON_STARTERP_PINT7_MASK) 9923 #define SYSCON_STARTERP_CTIMER2_MASK (0x10U) 9924 #define SYSCON_STARTERP_CTIMER2_SHIFT (4U) 9925 /*! CTIMER2 - Standard counter/timer CTIMER2 wake-up. 0 = Wake-up disabled. 1 = Wake-up 9926 * enabled.Typically used in sleep mode only since the peripheral clock must be running for it to function. 9927 */ 9928 #define SYSCON_STARTERP_CTIMER2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_CTIMER2_SHIFT)) & SYSCON_STARTERP_CTIMER2_MASK) 9929 #define SYSCON_STARTERP_PIN_INT0_MASK (0x10U) 9930 #define SYSCON_STARTERP_PIN_INT0_SHIFT (4U) 9931 /*! PIN_INT0 - GPIO pin interrupt 0 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern match. 9932 */ 9933 #define SYSCON_STARTERP_PIN_INT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_PIN_INT0_SHIFT)) & SYSCON_STARTERP_PIN_INT0_MASK) 9934 #define SYSCON_STARTERP_CTIMER4_MASK (0x20U) 9935 #define SYSCON_STARTERP_CTIMER4_SHIFT (5U) 9936 /*! CTIMER4 - Standard counter/timer CTIMER4 wake-up. 0 = Wake-up disabled. 1 = Wake-up 9937 * enabled.Typically used in sleep mode only since the peripheral clock must be running for it to function. 9938 */ 9939 #define SYSCON_STARTERP_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_CTIMER4_SHIFT)) & SYSCON_STARTERP_CTIMER4_MASK) 9940 #define SYSCON_STARTERP_PIN_INT1_MASK (0x20U) 9941 #define SYSCON_STARTERP_PIN_INT1_SHIFT (5U) 9942 /*! PIN_INT1 - GPIO pin interrupt 1 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern match. 9943 */ 9944 #define SYSCON_STARTERP_PIN_INT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_PIN_INT1_SHIFT)) & SYSCON_STARTERP_PIN_INT1_MASK) 9945 #define SYSCON_STARTERP_PIN_INT2_MASK (0x40U) 9946 #define SYSCON_STARTERP_PIN_INT2_SHIFT (6U) 9947 /*! PIN_INT2 - GPIO pin interrupt 2 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern match. 9948 */ 9949 #define SYSCON_STARTERP_PIN_INT2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_PIN_INT2_SHIFT)) & SYSCON_STARTERP_PIN_INT2_MASK) 9950 #define SYSCON_STARTERP_PIN_INT3_MASK (0x80U) 9951 #define SYSCON_STARTERP_PIN_INT3_SHIFT (7U) 9952 /*! PIN_INT3 - GPIO pin interrupt 3 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern match. 9953 */ 9954 #define SYSCON_STARTERP_PIN_INT3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_PIN_INT3_SHIFT)) & SYSCON_STARTERP_PIN_INT3_MASK) 9955 #define SYSCON_STARTERP_UTICK0_MASK (0x100U) 9956 #define SYSCON_STARTERP_UTICK0_SHIFT (8U) 9957 /*! UTICK0 - Micro-tick Timer wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. 9958 */ 9959 #define SYSCON_STARTERP_UTICK0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_UTICK0_SHIFT)) & SYSCON_STARTERP_UTICK0_MASK) 9960 #define SYSCON_STARTERP_MRT0_MASK (0x200U) 9961 #define SYSCON_STARTERP_MRT0_SHIFT (9U) 9962 /*! MRT0 - Multi-Rate Timer wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Typically used in 9963 * sleep mode only since the peripheral clock must be running for it to function. 9964 */ 9965 #define SYSCON_STARTERP_MRT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_MRT0_SHIFT)) & SYSCON_STARTERP_MRT0_MASK) 9966 #define SYSCON_STARTERP_CTIMER0_MASK (0x400U) 9967 #define SYSCON_STARTERP_CTIMER0_SHIFT (10U) 9968 /*! CTIMER0 - Standard counter/timer CTIMER0 wake-up. 0 = Wake-up disabled. 1 = Wake-up 9969 * enabled.Typically used in sleep mode only since the peripheral clock must be running for it to function. 9970 */ 9971 #define SYSCON_STARTERP_CTIMER0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_CTIMER0_SHIFT)) & SYSCON_STARTERP_CTIMER0_MASK) 9972 #define SYSCON_STARTERP_CTIMER1_MASK (0x800U) 9973 #define SYSCON_STARTERP_CTIMER1_SHIFT (11U) 9974 /*! CTIMER1 - Standard counter/timer CTIMER1 wake-up. 0 = Wake-up disabled. 1 = Wake-up 9975 * enabled.Typically used in sleep mode only since the peripheral clock must be running for it to function. 9976 */ 9977 #define SYSCON_STARTERP_CTIMER1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_CTIMER1_SHIFT)) & SYSCON_STARTERP_CTIMER1_MASK) 9978 #define SYSCON_STARTERP_SCT0_MASK (0x1000U) 9979 #define SYSCON_STARTERP_SCT0_SHIFT (12U) 9980 /*! SCT0 - SCT0 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.Typically used in sleep mode only 9981 * since the peripheral clock must be running for it to function. 9982 */ 9983 #define SYSCON_STARTERP_SCT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_SCT0_SHIFT)) & SYSCON_STARTERP_SCT0_MASK) 9984 #define SYSCON_STARTERP_CTIMER3_MASK (0x2000U) 9985 #define SYSCON_STARTERP_CTIMER3_SHIFT (13U) 9986 /*! CTIMER3 - Standard counter/timer CTIMER3 wake-up. 0 = Wake-up disabled. 1 = Wake-up 9987 * enabled.Typically used in sleep mode only since the peripheral clock must be running for it to function. 9988 */ 9989 #define SYSCON_STARTERP_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_CTIMER3_SHIFT)) & SYSCON_STARTERP_CTIMER3_MASK) 9990 #define SYSCON_STARTERP_FLEXCOMM0_MASK (0x4000U) 9991 #define SYSCON_STARTERP_FLEXCOMM0_SHIFT (14U) 9992 /*! FLEXCOMM0 - Flexcomm0 peripheral interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. 9993 */ 9994 #define SYSCON_STARTERP_FLEXCOMM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_FLEXCOMM0_SHIFT)) & SYSCON_STARTERP_FLEXCOMM0_MASK) 9995 #define SYSCON_STARTERP_FLEXCOMM1_MASK (0x8000U) 9996 #define SYSCON_STARTERP_FLEXCOMM1_SHIFT (15U) 9997 /*! FLEXCOMM1 - Flexcomm1 peripheral interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. 9998 */ 9999 #define SYSCON_STARTERP_FLEXCOMM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_FLEXCOMM1_SHIFT)) & SYSCON_STARTERP_FLEXCOMM1_MASK) 10000 #define SYSCON_STARTERP_FLEXCOMM2_MASK (0x10000U) 10001 #define SYSCON_STARTERP_FLEXCOMM2_SHIFT (16U) 10002 /*! FLEXCOMM2 - Flexcomm2 peripheral interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. 10003 */ 10004 #define SYSCON_STARTERP_FLEXCOMM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_FLEXCOMM2_SHIFT)) & SYSCON_STARTERP_FLEXCOMM2_MASK) 10005 #define SYSCON_STARTERP_FLEXCOMM3_MASK (0x20000U) 10006 #define SYSCON_STARTERP_FLEXCOMM3_SHIFT (17U) 10007 /*! FLEXCOMM3 - Flexcomm3 peripheral interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. 10008 */ 10009 #define SYSCON_STARTERP_FLEXCOMM3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_FLEXCOMM3_SHIFT)) & SYSCON_STARTERP_FLEXCOMM3_MASK) 10010 #define SYSCON_STARTERP_FLEXCOMM4_MASK (0x40000U) 10011 #define SYSCON_STARTERP_FLEXCOMM4_SHIFT (18U) 10012 /*! FLEXCOMM4 - Flexcomm4 peripheral interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. 10013 */ 10014 #define SYSCON_STARTERP_FLEXCOMM4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_FLEXCOMM4_SHIFT)) & SYSCON_STARTERP_FLEXCOMM4_MASK) 10015 #define SYSCON_STARTERP_FLEXCOMM5_MASK (0x80000U) 10016 #define SYSCON_STARTERP_FLEXCOMM5_SHIFT (19U) 10017 /*! FLEXCOMM5 - Flexcomm5 peripheral interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. 10018 */ 10019 #define SYSCON_STARTERP_FLEXCOMM5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_FLEXCOMM5_SHIFT)) & SYSCON_STARTERP_FLEXCOMM5_MASK) 10020 #define SYSCON_STARTERP_FLEXCOMM6_MASK (0x100000U) 10021 #define SYSCON_STARTERP_FLEXCOMM6_SHIFT (20U) 10022 /*! FLEXCOMM6 - Flexcomm6 peripheral interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. 10023 */ 10024 #define SYSCON_STARTERP_FLEXCOMM6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_FLEXCOMM6_SHIFT)) & SYSCON_STARTERP_FLEXCOMM6_MASK) 10025 #define SYSCON_STARTERP_FLEXCOMM7_MASK (0x200000U) 10026 #define SYSCON_STARTERP_FLEXCOMM7_SHIFT (21U) 10027 /*! FLEXCOMM7 - Flexcomm7 peripheral interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. 10028 */ 10029 #define SYSCON_STARTERP_FLEXCOMM7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_FLEXCOMM7_SHIFT)) & SYSCON_STARTERP_FLEXCOMM7_MASK) 10030 #define SYSCON_STARTERP_ADC0_SEQA_MASK (0x400000U) 10031 #define SYSCON_STARTERP_ADC0_SEQA_SHIFT (22U) 10032 /*! ADC0_SEQA - ADC0 sequence A interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up 10033 * enabled.Typically used in sleep mode only since the peripheral clock must be running for it to function. 10034 */ 10035 #define SYSCON_STARTERP_ADC0_SEQA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_ADC0_SEQA_SHIFT)) & SYSCON_STARTERP_ADC0_SEQA_MASK) 10036 #define SYSCON_STARTERP_ADC0_SEQB_MASK (0x800000U) 10037 #define SYSCON_STARTERP_ADC0_SEQB_SHIFT (23U) 10038 /*! ADC0_SEQB - ADC0 sequence B interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up 10039 * enabled.Typically used in sleep mode only since the peripheral clock must be running for it to function. 10040 */ 10041 #define SYSCON_STARTERP_ADC0_SEQB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_ADC0_SEQB_SHIFT)) & SYSCON_STARTERP_ADC0_SEQB_MASK) 10042 #define SYSCON_STARTERP_ADC0_THCMP_MASK (0x1000000U) 10043 #define SYSCON_STARTERP_ADC0_THCMP_SHIFT (24U) 10044 /*! ADC0_THCMP - ADC0 threshold and error interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up 10045 * enabled.Typically used in sleep mode only since the peripheral clock must be running for it to 10046 * function. 10047 */ 10048 #define SYSCON_STARTERP_ADC0_THCMP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_ADC0_THCMP_SHIFT)) & SYSCON_STARTERP_ADC0_THCMP_MASK) 10049 #define SYSCON_STARTERP_DMIC0_MASK (0x2000000U) 10050 #define SYSCON_STARTERP_DMIC0_SHIFT (25U) 10051 /*! DMIC0 - Digital microphone interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. 10052 */ 10053 #define SYSCON_STARTERP_DMIC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_DMIC0_SHIFT)) & SYSCON_STARTERP_DMIC0_MASK) 10054 #define SYSCON_STARTERP_USB0_NEEDCLK_MASK (0x8000000U) 10055 #define SYSCON_STARTERP_USB0_NEEDCLK_SHIFT (27U) 10056 /*! USB0_NEEDCLK - USB0 activity interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. 10057 */ 10058 #define SYSCON_STARTERP_USB0_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_USB0_NEEDCLK_SHIFT)) & SYSCON_STARTERP_USB0_NEEDCLK_MASK) 10059 #define SYSCON_STARTERP_USB0_MASK (0x10000000U) 10060 #define SYSCON_STARTERP_USB0_SHIFT (28U) 10061 /*! USB0 - USB0 function interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. 10062 */ 10063 #define SYSCON_STARTERP_USB0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_USB0_SHIFT)) & SYSCON_STARTERP_USB0_MASK) 10064 #define SYSCON_STARTERP_RTC_MASK (0x20000000U) 10065 #define SYSCON_STARTERP_RTC_SHIFT (29U) 10066 /*! RTC - RTC interrupt alarm and wake-up timer. 0 = Wake-up disabled. 1 = Wake-up enabled. 10067 */ 10068 #define SYSCON_STARTERP_RTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_RTC_SHIFT)) & SYSCON_STARTERP_RTC_MASK) 10069 #define SYSCON_STARTERP_MAILBOX_MASK (0x80000000U) 10070 #define SYSCON_STARTERP_MAILBOX_SHIFT (31U) 10071 /*! MAILBOX - Mailbox interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.At least one CPU 10072 * must be running in order for a mailbox interrupt to occur. Present on selected devices. 10073 */ 10074 #define SYSCON_STARTERP_MAILBOX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_MAILBOX_SHIFT)) & SYSCON_STARTERP_MAILBOX_MASK) 10075 /*! @} */ 10076 10077 /* The count of SYSCON_STARTERP */ 10078 #define SYSCON_STARTERP_COUNT (2U) 10079 10080 /*! @name STARTERSET - Set bits in STARTERn */ 10081 /*! @{ */ 10082 #define SYSCON_STARTERSET_START_SET_MASK (0xFFFFFFFFU) 10083 #define SYSCON_STARTERSET_START_SET_SHIFT (0U) 10084 /*! START_SET - Writing ones to this register sets the corresponding bit or bits in the STARTERn 10085 * register, if they are implemented. Bits that do not correspond to defined bits in STARTERn are 10086 * reserved and only zeroes should be written to them. 10087 */ 10088 #define SYSCON_STARTERSET_START_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_START_SET_SHIFT)) & SYSCON_STARTERSET_START_SET_MASK) 10089 /*! @} */ 10090 10091 /* The count of SYSCON_STARTERSET */ 10092 #define SYSCON_STARTERSET_COUNT (2U) 10093 10094 /*! @name STARTERCLR - Clear bits in STARTERn */ 10095 /*! @{ */ 10096 #define SYSCON_STARTERCLR_START_CLR_MASK (0xFFFFFFFFU) 10097 #define SYSCON_STARTERCLR_START_CLR_SHIFT (0U) 10098 /*! START_CLR - Writing ones to this register clears the corresponding bit or bits in the STARTERn 10099 * register, if they are implemented. Bits that do not correspond to defined bits in STARTERn are 10100 * reserved and only zeroes should be written to them. 10101 */ 10102 #define SYSCON_STARTERCLR_START_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_START_CLR_SHIFT)) & SYSCON_STARTERCLR_START_CLR_MASK) 10103 /*! @} */ 10104 10105 /* The count of SYSCON_STARTERCLR */ 10106 #define SYSCON_STARTERCLR_COUNT (2U) 10107 10108 /*! @name HWWAKE - Configures special cases of hardware wake-up */ 10109 /*! @{ */ 10110 #define SYSCON_HWWAKE_FORCEWAKE_MASK (0x1U) 10111 #define SYSCON_HWWAKE_FORCEWAKE_SHIFT (0U) 10112 /*! FORCEWAKE - Force peripheral clocking to stay on during Deep Sleep and Power-down modes. When 1, 10113 * clocking to peripherals is prevented from being shut down when the CPU enters Deep Sleep and 10114 * Power-down modes. This is intended to allow a coprocessor to continue operating while the main 10115 * CPU(s) are shut down. 10116 */ 10117 #define SYSCON_HWWAKE_FORCEWAKE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_FORCEWAKE_SHIFT)) & SYSCON_HWWAKE_FORCEWAKE_MASK) 10118 #define SYSCON_HWWAKE_FCWAKE_MASK (0x2U) 10119 #define SYSCON_HWWAKE_FCWAKE_SHIFT (1U) 10120 /*! FCWAKE - Wake for Flexcomms. When 1, any Flexcomm FIFO reaching the level specified by its own 10121 * TXLVL will cause peripheral clocking to wake up temporarily while the related status is 10122 * asserted. 10123 */ 10124 #define SYSCON_HWWAKE_FCWAKE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_FCWAKE_SHIFT)) & SYSCON_HWWAKE_FCWAKE_MASK) 10125 #define SYSCON_HWWAKE_WAKEDMIC_MASK (0x4U) 10126 #define SYSCON_HWWAKE_WAKEDMIC_SHIFT (2U) 10127 /*! WAKEDMIC - Wake for Digital Microphone. When 1, the digital microphone input FIFO reaching the 10128 * level specified by TRIGLVL of either channel will cause peripheral clocking to wake up 10129 * temporarily while the related status is asserted. 10130 */ 10131 #define SYSCON_HWWAKE_WAKEDMIC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_WAKEDMIC_SHIFT)) & SYSCON_HWWAKE_WAKEDMIC_MASK) 10132 #define SYSCON_HWWAKE_WAKEDMA_MASK (0x8U) 10133 #define SYSCON_HWWAKE_WAKEDMA_SHIFT (3U) 10134 /*! WAKEDMA - Wake for DMA. When 1, DMA being busy will cause peripheral clocking to remain running 10135 * until DMA completes. This is generally used in conjunction with bit 1 and/or 2 in order to 10136 * prevent peripheral clocking from being shut down as soon as the cause of wake-up is cleared, but 10137 * before DMA has completed its related activity. 10138 */ 10139 #define SYSCON_HWWAKE_WAKEDMA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_WAKEDMA_SHIFT)) & SYSCON_HWWAKE_WAKEDMA_MASK) 10140 /*! @} */ 10141 10142 /*! @name CPUCTRL - CPU Control for multiple processors */ 10143 /*! @{ */ 10144 #define SYSCON_CPUCTRL_MASTERCPU_MASK (0x1U) 10145 #define SYSCON_CPUCTRL_MASTERCPU_SHIFT (0U) 10146 /*! MASTERCPU - Indicates which CPU is considered the master. This is factory set assign the 10147 * Cortex-M4 as the master. The master CPU cannot have its clock turned off via the related CMnCLKEN bit 10148 * or be reset via the related CMxRSTEN in this register. The slave CPU wakes up briefly 10149 * following device reset, then goes back to sleep until activated by the master CPU. 10150 * 0b0..M0+. Cortex-M0+ is the master CPU. 10151 * 0b1..M4. Cortex-M4 is the master CPU. 10152 */ 10153 #define SYSCON_CPUCTRL_MASTERCPU(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_MASTERCPU_SHIFT)) & SYSCON_CPUCTRL_MASTERCPU_MASK) 10154 #define SYSCON_CPUCTRL_CM4CLKEN_MASK (0x4U) 10155 #define SYSCON_CPUCTRL_CM4CLKEN_SHIFT (2U) 10156 /*! CM4CLKEN - Cortex-M4 clock enable 10157 * 0b0..Disabled. The Cortex-M4 clock is not enabled 10158 * 0b1..Enabled. The Cortex-M4 clock is enabled. 10159 */ 10160 #define SYSCON_CPUCTRL_CM4CLKEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_CM4CLKEN_SHIFT)) & SYSCON_CPUCTRL_CM4CLKEN_MASK) 10161 #define SYSCON_CPUCTRL_CM0CLKEN_MASK (0x8U) 10162 #define SYSCON_CPUCTRL_CM0CLKEN_SHIFT (3U) 10163 /*! CM0CLKEN - Cortex-M0+ clock enable 10164 * 0b0..Disabled. The Cortex-M0+ clock is not enabled. 10165 * 0b1..Enabled. The Cortex-M0+ clock is enabled. 10166 */ 10167 #define SYSCON_CPUCTRL_CM0CLKEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_CM0CLKEN_SHIFT)) & SYSCON_CPUCTRL_CM0CLKEN_MASK) 10168 #define SYSCON_CPUCTRL_CM4RSTEN_MASK (0x10U) 10169 #define SYSCON_CPUCTRL_CM4RSTEN_SHIFT (4U) 10170 /*! CM4RSTEN - Cortex-M4 reset. 10171 * 0b0..Disabled. The Cortex-M4 is not being reset. 10172 * 0b1..Enabled. The Cortex-M4 is being reset. 10173 */ 10174 #define SYSCON_CPUCTRL_CM4RSTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_CM4RSTEN_SHIFT)) & SYSCON_CPUCTRL_CM4RSTEN_MASK) 10175 #define SYSCON_CPUCTRL_CM0RSTEN_MASK (0x20U) 10176 #define SYSCON_CPUCTRL_CM0RSTEN_SHIFT (5U) 10177 /*! CM0RSTEN - Cortex-M0+ reset. 10178 * 0b0..Disabled. The Cortex-M0+ is not being reset. 10179 * 0b1..Enabled. The Cortex-M0+ is being reset. 10180 */ 10181 #define SYSCON_CPUCTRL_CM0RSTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_CM0RSTEN_SHIFT)) & SYSCON_CPUCTRL_CM0RSTEN_MASK) 10182 #define SYSCON_CPUCTRL_POWERCPU_MASK (0x40U) 10183 #define SYSCON_CPUCTRL_POWERCPU_SHIFT (6U) 10184 /*! POWERCPU - Identifies the owner of reduced power mode control: which CPU can cause the device to 10185 * enter Deep Sleep, Power-down, and Deep Power-down modes. 10186 * 0b0..M0+. Cortex-M0+ is the owner of reduced power mode control. 10187 * 0b1..M4. Cortex-M4 is the owner of reduced power mode control. 10188 */ 10189 #define SYSCON_CPUCTRL_POWERCPU(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_POWERCPU_SHIFT)) & SYSCON_CPUCTRL_POWERCPU_MASK) 10190 /*! @} */ 10191 10192 /*! @name CPBOOT - Coprocessor Boot Address */ 10193 /*! @{ */ 10194 #define SYSCON_CPBOOT_BOOTADDR_MASK (0xFFFFFFFFU) 10195 #define SYSCON_CPBOOT_BOOTADDR_SHIFT (0U) 10196 /*! BOOTADDR - Slave processor boot address 10197 */ 10198 #define SYSCON_CPBOOT_BOOTADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPBOOT_BOOTADDR_SHIFT)) & SYSCON_CPBOOT_BOOTADDR_MASK) 10199 /*! @} */ 10200 10201 /*! @name CPSTACK - Coprocessor Stack Address */ 10202 /*! @{ */ 10203 #define SYSCON_CPSTACK_STACKADDR_MASK (0xFFFFFFFFU) 10204 #define SYSCON_CPSTACK_STACKADDR_SHIFT (0U) 10205 /*! STACKADDR - Slave processor stack address 10206 */ 10207 #define SYSCON_CPSTACK_STACKADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTACK_STACKADDR_SHIFT)) & SYSCON_CPSTACK_STACKADDR_MASK) 10208 /*! @} */ 10209 10210 /*! @name CPSTAT - Coprocessor Status */ 10211 /*! @{ */ 10212 #define SYSCON_CPSTAT_CM4SLEEPING_MASK (0x1U) 10213 #define SYSCON_CPSTAT_CM4SLEEPING_SHIFT (0U) 10214 /*! CM4SLEEPING - When 1, the Cortex-M4 CPU is sleeping 10215 */ 10216 #define SYSCON_CPSTAT_CM4SLEEPING(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CM4SLEEPING_SHIFT)) & SYSCON_CPSTAT_CM4SLEEPING_MASK) 10217 #define SYSCON_CPSTAT_CM0SLEEPING_MASK (0x2U) 10218 #define SYSCON_CPSTAT_CM0SLEEPING_SHIFT (1U) 10219 /*! CM0SLEEPING - When 1, the Cortex-M0+ CPU is sleeping 10220 */ 10221 #define SYSCON_CPSTAT_CM0SLEEPING(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CM0SLEEPING_SHIFT)) & SYSCON_CPSTAT_CM0SLEEPING_MASK) 10222 #define SYSCON_CPSTAT_CM4LOCKUP_MASK (0x4U) 10223 #define SYSCON_CPSTAT_CM4LOCKUP_SHIFT (2U) 10224 /*! CM4LOCKUP - When 1, the Cortex-M4 CPU is in lockup 10225 */ 10226 #define SYSCON_CPSTAT_CM4LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CM4LOCKUP_SHIFT)) & SYSCON_CPSTAT_CM4LOCKUP_MASK) 10227 #define SYSCON_CPSTAT_CM0LOCKUP_MASK (0x8U) 10228 #define SYSCON_CPSTAT_CM0LOCKUP_SHIFT (3U) 10229 /*! CM0LOCKUP - When 1, the Cortex-M0+ CPU is in lockup. 10230 */ 10231 #define SYSCON_CPSTAT_CM0LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CM0LOCKUP_SHIFT)) & SYSCON_CPSTAT_CM0LOCKUP_MASK) 10232 /*! @} */ 10233 10234 /*! @name AUTOCGOR - Auto Clock-Gate Override Register */ 10235 /*! @{ */ 10236 #define SYSCON_AUTOCGOR_RAM0X_MASK (0x2U) 10237 #define SYSCON_AUTOCGOR_RAM0X_SHIFT (1U) 10238 /*! RAM0X - When 1, automatic clock gating for RAMX and RAM0 are turned off. 10239 */ 10240 #define SYSCON_AUTOCGOR_RAM0X(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCGOR_RAM0X_SHIFT)) & SYSCON_AUTOCGOR_RAM0X_MASK) 10241 #define SYSCON_AUTOCGOR_RAM1_MASK (0x4U) 10242 #define SYSCON_AUTOCGOR_RAM1_SHIFT (2U) 10243 /*! RAM1 - When 1, automatic clock gating for RAM1 is turned off. 10244 */ 10245 #define SYSCON_AUTOCGOR_RAM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCGOR_RAM1_SHIFT)) & SYSCON_AUTOCGOR_RAM1_MASK) 10246 #define SYSCON_AUTOCGOR_RAM2_MASK (0x8U) 10247 #define SYSCON_AUTOCGOR_RAM2_SHIFT (3U) 10248 /*! RAM2 - When 1, automatic clock gating for RAM2 is turned off. 10249 */ 10250 #define SYSCON_AUTOCGOR_RAM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCGOR_RAM2_SHIFT)) & SYSCON_AUTOCGOR_RAM2_MASK) 10251 /*! @} */ 10252 10253 /*! @name JTAGIDCODE - JTAG ID code register */ 10254 /*! @{ */ 10255 #define SYSCON_JTAGIDCODE_JTAGID_MASK (0xFFFFFFFFU) 10256 #define SYSCON_JTAGIDCODE_JTAGID_SHIFT (0U) 10257 /*! JTAGID - JTAG ID code. 10258 */ 10259 #define SYSCON_JTAGIDCODE_JTAGID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_JTAGIDCODE_JTAGID_SHIFT)) & SYSCON_JTAGIDCODE_JTAGID_MASK) 10260 /*! @} */ 10261 10262 /*! @name DEVICE_ID0 - Part ID register */ 10263 /*! @{ */ 10264 #define SYSCON_DEVICE_ID0_PARTID_MASK (0xFFFFFFFFU) 10265 #define SYSCON_DEVICE_ID0_PARTID_SHIFT (0U) 10266 /*! PARTID - Part ID 10267 */ 10268 #define SYSCON_DEVICE_ID0_PARTID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_PARTID_SHIFT)) & SYSCON_DEVICE_ID0_PARTID_MASK) 10269 /*! @} */ 10270 10271 /*! @name DEVICE_ID1 - Boot ROM and die revision register */ 10272 /*! @{ */ 10273 #define SYSCON_DEVICE_ID1_REVID_MASK (0xFFFFFFFFU) 10274 #define SYSCON_DEVICE_ID1_REVID_SHIFT (0U) 10275 /*! REVID - Revision. 10276 */ 10277 #define SYSCON_DEVICE_ID1_REVID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID1_REVID_SHIFT)) & SYSCON_DEVICE_ID1_REVID_MASK) 10278 /*! @} */ 10279 10280 /*! @name BODCTRL - Brown-Out Detect control */ 10281 /*! @{ */ 10282 #define SYSCON_BODCTRL_BODRSTLEV_MASK (0x3U) 10283 #define SYSCON_BODCTRL_BODRSTLEV_SHIFT (0U) 10284 /*! BODRSTLEV - BOD reset level 10285 * 0b00..Level 0: 1.5 V 10286 * 0b01..Level 1: 1.85 V 10287 * 0b10..Level 2: 2.0 V 10288 * 0b11..Level 3: 2.3 V 10289 */ 10290 #define SYSCON_BODCTRL_BODRSTLEV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODRSTLEV_SHIFT)) & SYSCON_BODCTRL_BODRSTLEV_MASK) 10291 #define SYSCON_BODCTRL_BODRSTENA_MASK (0x4U) 10292 #define SYSCON_BODCTRL_BODRSTENA_SHIFT (2U) 10293 /*! BODRSTENA - BOD reset enable 10294 * 0b0..Disable reset function. 10295 * 0b1..Enable reset function. 10296 */ 10297 #define SYSCON_BODCTRL_BODRSTENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODRSTENA_SHIFT)) & SYSCON_BODCTRL_BODRSTENA_MASK) 10298 #define SYSCON_BODCTRL_BODINTLEV_MASK (0x18U) 10299 #define SYSCON_BODCTRL_BODINTLEV_SHIFT (3U) 10300 /*! BODINTLEV - BOD interrupt level 10301 * 0b00..Level 0: 2.05 V 10302 * 0b01..Level 1: 2.45 V 10303 * 0b10..Level 2: 2.75 V 10304 * 0b11..Level 3: 3.05 V 10305 */ 10306 #define SYSCON_BODCTRL_BODINTLEV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODINTLEV_SHIFT)) & SYSCON_BODCTRL_BODINTLEV_MASK) 10307 #define SYSCON_BODCTRL_BODINTENA_MASK (0x20U) 10308 #define SYSCON_BODCTRL_BODINTENA_SHIFT (5U) 10309 /*! BODINTENA - BOD interrupt enable 10310 * 0b0..Disable interrupt function. 10311 * 0b1..Enable interrupt function. 10312 */ 10313 #define SYSCON_BODCTRL_BODINTENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODINTENA_SHIFT)) & SYSCON_BODCTRL_BODINTENA_MASK) 10314 #define SYSCON_BODCTRL_BODRSTSTAT_MASK (0x40U) 10315 #define SYSCON_BODCTRL_BODRSTSTAT_SHIFT (6U) 10316 /*! BODRSTSTAT - BOD reset status. When 1, a BOD reset has occurred. Cleared by writing 1 to this bit. 10317 */ 10318 #define SYSCON_BODCTRL_BODRSTSTAT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODRSTSTAT_SHIFT)) & SYSCON_BODCTRL_BODRSTSTAT_MASK) 10319 #define SYSCON_BODCTRL_BODINTSTAT_MASK (0x80U) 10320 #define SYSCON_BODCTRL_BODINTSTAT_SHIFT (7U) 10321 /*! BODINTSTAT - BOD interrupt status. When 1, a BOD interrupt has occurred. Cleared by writing 1 to this bit. 10322 */ 10323 #define SYSCON_BODCTRL_BODINTSTAT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODINTSTAT_SHIFT)) & SYSCON_BODCTRL_BODINTSTAT_MASK) 10324 /*! @} */ 10325 10326 10327 /*! 10328 * @} 10329 */ /* end of group SYSCON_Register_Masks */ 10330 10331 10332 /* SYSCON - Peripheral instance base addresses */ 10333 /** Peripheral SYSCON base address */ 10334 #define SYSCON_BASE (0x40000000u) 10335 /** Peripheral SYSCON base pointer */ 10336 #define SYSCON ((SYSCON_Type *)SYSCON_BASE) 10337 /** Array initializer of SYSCON peripheral base addresses */ 10338 #define SYSCON_BASE_ADDRS { SYSCON_BASE } 10339 /** Array initializer of SYSCON peripheral base pointers */ 10340 #define SYSCON_BASE_PTRS { SYSCON } 10341 10342 /*! 10343 * @} 10344 */ /* end of group SYSCON_Peripheral_Access_Layer */ 10345 10346 10347 /* ---------------------------------------------------------------------------- 10348 -- USART Peripheral Access Layer 10349 ---------------------------------------------------------------------------- */ 10350 10351 /*! 10352 * @addtogroup USART_Peripheral_Access_Layer USART Peripheral Access Layer 10353 * @{ 10354 */ 10355 10356 /** USART - Register Layout Typedef */ 10357 typedef struct { 10358 __IO uint32_t CFG; /**< USART Configuration register. Basic USART configuration settings that typically are not changed during operation., offset: 0x0 */ 10359 __IO uint32_t CTL; /**< USART Control register. USART control settings that are more likely to change during operation., offset: 0x4 */ 10360 __IO uint32_t STAT; /**< USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them., offset: 0x8 */ 10361 __IO uint32_t INTENSET; /**< Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0xC */ 10362 __O uint32_t INTENCLR; /**< Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared., offset: 0x10 */ 10363 uint8_t RESERVED_0[12]; 10364 __IO uint32_t BRG; /**< Baud Rate Generator register. 16-bit integer baud rate divisor value., offset: 0x20 */ 10365 __I uint32_t INTSTAT; /**< Interrupt status register. Reflects interrupts that are currently enabled., offset: 0x24 */ 10366 __IO uint32_t OSR; /**< Oversample selection register for asynchronous communication., offset: 0x28 */ 10367 __IO uint32_t ADDR; /**< Address register for automatic address matching., offset: 0x2C */ 10368 uint8_t RESERVED_1[3536]; 10369 __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */ 10370 __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ 10371 __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */ 10372 uint8_t RESERVED_2[4]; 10373 __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */ 10374 __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */ 10375 __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */ 10376 uint8_t RESERVED_3[4]; 10377 __IO uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ 10378 uint8_t RESERVED_4[12]; 10379 __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */ 10380 uint8_t RESERVED_5[12]; 10381 __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */ 10382 } USART_Type; 10383 10384 /* ---------------------------------------------------------------------------- 10385 -- USART Register Masks 10386 ---------------------------------------------------------------------------- */ 10387 10388 /*! 10389 * @addtogroup USART_Register_Masks USART Register Masks 10390 * @{ 10391 */ 10392 10393 /*! @name CFG - USART Configuration register. Basic USART configuration settings that typically are not changed during operation. */ 10394 /*! @{ */ 10395 #define USART_CFG_ENABLE_MASK (0x1U) 10396 #define USART_CFG_ENABLE_SHIFT (0U) 10397 /*! ENABLE - USART Enable. 10398 * 0b0..Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, 10399 * all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control 10400 * bits remain unchanged. When re-enabled, the USART will immediately be ready to transmit because the 10401 * transmitter has been reset and is therefore available. 10402 * 0b1..Enabled. The USART is enabled for operation. 10403 */ 10404 #define USART_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_ENABLE_SHIFT)) & USART_CFG_ENABLE_MASK) 10405 #define USART_CFG_DATALEN_MASK (0xCU) 10406 #define USART_CFG_DATALEN_SHIFT (2U) 10407 /*! DATALEN - Selects the data size for the USART. 10408 * 0b00..7 bit Data length. 10409 * 0b01..8 bit Data length. 10410 * 0b10..9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTL register. 10411 * 0b11..Reserved. 10412 */ 10413 #define USART_CFG_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_DATALEN_SHIFT)) & USART_CFG_DATALEN_MASK) 10414 #define USART_CFG_PARITYSEL_MASK (0x30U) 10415 #define USART_CFG_PARITYSEL_SHIFT (4U) 10416 /*! PARITYSEL - Selects what type of parity is used by the USART. 10417 * 0b00..No parity. 10418 * 0b01..Reserved. 10419 * 0b10..Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, 10420 * and the number of 1s in a received character is expected to be even. 10421 * 0b11..Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, 10422 * and the number of 1s in a received character is expected to be odd. 10423 */ 10424 #define USART_CFG_PARITYSEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_PARITYSEL_SHIFT)) & USART_CFG_PARITYSEL_MASK) 10425 #define USART_CFG_STOPLEN_MASK (0x40U) 10426 #define USART_CFG_STOPLEN_SHIFT (6U) 10427 /*! STOPLEN - Number of stop bits appended to transmitted data. Only a single stop bit is required for received data. 10428 * 0b0..1 stop bit. 10429 * 0b1..2 stop bits. This setting should only be used for asynchronous communication. 10430 */ 10431 #define USART_CFG_STOPLEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_STOPLEN_SHIFT)) & USART_CFG_STOPLEN_MASK) 10432 #define USART_CFG_MODE32K_MASK (0x80U) 10433 #define USART_CFG_MODE32K_SHIFT (7U) 10434 /*! MODE32K - Selects standard or 32 kHz clocking mode. 10435 * 0b0..Disabled. USART uses standard clocking. 10436 * 0b1..Enabled. USART uses the 32 kHz clock from the RTC oscillator as the clock source to the BRG, and uses a special bit clocking scheme. 10437 */ 10438 #define USART_CFG_MODE32K(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_MODE32K_SHIFT)) & USART_CFG_MODE32K_MASK) 10439 #define USART_CFG_LINMODE_MASK (0x100U) 10440 #define USART_CFG_LINMODE_SHIFT (8U) 10441 /*! LINMODE - LIN break mode enable. 10442 * 0b0..Disabled. Break detect and generate is configured for normal operation. 10443 * 0b1..Enabled. Break detect and generate is configured for LIN bus operation. 10444 */ 10445 #define USART_CFG_LINMODE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LINMODE_SHIFT)) & USART_CFG_LINMODE_MASK) 10446 #define USART_CFG_CTSEN_MASK (0x200U) 10447 #define USART_CFG_CTSEN_SHIFT (9U) 10448 /*! CTSEN - CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input 10449 * pin, or from the USART's own RTS if loopback mode is enabled. 10450 * 0b0..No flow control. The transmitter does not receive any automatic flow control signal. 10451 * 0b1..Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes. 10452 */ 10453 #define USART_CFG_CTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CTSEN_SHIFT)) & USART_CFG_CTSEN_MASK) 10454 #define USART_CFG_SYNCEN_MASK (0x800U) 10455 #define USART_CFG_SYNCEN_SHIFT (11U) 10456 /*! SYNCEN - Selects synchronous or asynchronous operation. 10457 * 0b0..Asynchronous mode. 10458 * 0b1..Synchronous mode. 10459 */ 10460 #define USART_CFG_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCEN_SHIFT)) & USART_CFG_SYNCEN_MASK) 10461 #define USART_CFG_CLKPOL_MASK (0x1000U) 10462 #define USART_CFG_CLKPOL_SHIFT (12U) 10463 /*! CLKPOL - Selects the clock polarity and sampling edge of received data in synchronous mode. 10464 * 0b0..Falling edge. Un_RXD is sampled on the falling edge of SCLK. 10465 * 0b1..Rising edge. Un_RXD is sampled on the rising edge of SCLK. 10466 */ 10467 #define USART_CFG_CLKPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CLKPOL_SHIFT)) & USART_CFG_CLKPOL_MASK) 10468 #define USART_CFG_SYNCMST_MASK (0x4000U) 10469 #define USART_CFG_SYNCMST_SHIFT (14U) 10470 /*! SYNCMST - Synchronous mode Master select. 10471 * 0b0..Slave. When synchronous mode is enabled, the USART is a slave. 10472 * 0b1..Master. When synchronous mode is enabled, the USART is a master. 10473 */ 10474 #define USART_CFG_SYNCMST(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCMST_SHIFT)) & USART_CFG_SYNCMST_MASK) 10475 #define USART_CFG_LOOP_MASK (0x8000U) 10476 #define USART_CFG_LOOP_SHIFT (15U) 10477 /*! LOOP - Selects data loopback mode. 10478 * 0b0..Normal operation. 10479 * 0b1..Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial 10480 * data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD 10481 * and Un_RTS activity will also appear on external pins if these functions are configured to appear on device 10482 * pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN. 10483 */ 10484 #define USART_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LOOP_SHIFT)) & USART_CFG_LOOP_MASK) 10485 #define USART_CFG_IOMODE_MASK (0x10000U) 10486 #define USART_CFG_IOMODE_SHIFT (16U) 10487 /*! IOMODE - I/O output mode. 10488 * 0b0..Standard. USART output and input operate in standard fashion. 10489 * 0b1..IrDA. USART output and input operate in IrDA mode. 10490 */ 10491 #define USART_CFG_IOMODE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_IOMODE_SHIFT)) & USART_CFG_IOMODE_MASK) 10492 #define USART_CFG_OETA_MASK (0x40000U) 10493 #define USART_CFG_OETA_SHIFT (18U) 10494 /*! OETA - Output Enable Turnaround time enable for RS-485 operation. 10495 * 0b0..Disabled. If selected by OESEL, the Output Enable signal deasserted at the end of the last stop bit of a transmission. 10496 * 0b1..Enabled. If selected by OESEL, the Output Enable signal remains asserted for one character time after the 10497 * end of the last stop bit of a transmission. OE will also remain asserted if another transmit begins 10498 * before it is deasserted. 10499 */ 10500 #define USART_CFG_OETA(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OETA_SHIFT)) & USART_CFG_OETA_MASK) 10501 #define USART_CFG_AUTOADDR_MASK (0x80000U) 10502 #define USART_CFG_AUTOADDR_SHIFT (19U) 10503 /*! AUTOADDR - Automatic Address matching enable. 10504 * 0b0..Disabled. When addressing is enabled by ADDRDET, address matching is done by software. This provides the 10505 * possibility of versatile addressing (e.g. respond to more than one address). 10506 * 0b1..Enabled. When addressing is enabled by ADDRDET, address matching is done by hardware, using the value in 10507 * the ADDR register as the address to match. 10508 */ 10509 #define USART_CFG_AUTOADDR(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_AUTOADDR_SHIFT)) & USART_CFG_AUTOADDR_MASK) 10510 #define USART_CFG_OESEL_MASK (0x100000U) 10511 #define USART_CFG_OESEL_SHIFT (20U) 10512 /*! OESEL - Output Enable Select. 10513 * 0b0..Standard. The RTS signal is used as the standard flow control function. 10514 * 0b1..RS-485. The RTS signal configured to provide an output enable signal to control an RS-485 transceiver. 10515 */ 10516 #define USART_CFG_OESEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OESEL_SHIFT)) & USART_CFG_OESEL_MASK) 10517 #define USART_CFG_OEPOL_MASK (0x200000U) 10518 #define USART_CFG_OEPOL_SHIFT (21U) 10519 /*! OEPOL - Output Enable Polarity. 10520 * 0b0..Low. If selected by OESEL, the output enable is active low. 10521 * 0b1..High. If selected by OESEL, the output enable is active high. 10522 */ 10523 #define USART_CFG_OEPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OEPOL_SHIFT)) & USART_CFG_OEPOL_MASK) 10524 #define USART_CFG_RXPOL_MASK (0x400000U) 10525 #define USART_CFG_RXPOL_SHIFT (22U) 10526 /*! RXPOL - Receive data polarity. 10527 * 0b0..Standard. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1, start 10528 * bit is 0, data is not inverted, and the stop bit is 1. 10529 * 0b1..Inverted. The RX signal is inverted before being used by the USART. This means that the RX rest value is 10530 * 0, start bit is 1, data is inverted, and the stop bit is 0. 10531 */ 10532 #define USART_CFG_RXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_RXPOL_SHIFT)) & USART_CFG_RXPOL_MASK) 10533 #define USART_CFG_TXPOL_MASK (0x800000U) 10534 #define USART_CFG_TXPOL_SHIFT (23U) 10535 /*! TXPOL - Transmit data polarity. 10536 * 0b0..Standard. The TX signal is sent out without change. This means that the TX rest value is 1, start bit is 10537 * 0, data is not inverted, and the stop bit is 1. 10538 * 0b1..Inverted. The TX signal is inverted by the USART before being sent out. This means that the TX rest value 10539 * is 0, start bit is 1, data is inverted, and the stop bit is 0. 10540 */ 10541 #define USART_CFG_TXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_TXPOL_SHIFT)) & USART_CFG_TXPOL_MASK) 10542 /*! @} */ 10543 10544 /*! @name CTL - USART Control register. USART control settings that are more likely to change during operation. */ 10545 /*! @{ */ 10546 #define USART_CTL_TXBRKEN_MASK (0x2U) 10547 #define USART_CTL_TXBRKEN_SHIFT (1U) 10548 /*! TXBRKEN - Break Enable. 10549 * 0b0..Normal operation. 10550 * 0b1..Continuous break. Continuous break is sent immediately when this bit is set, and remains until this bit 10551 * is cleared. A break may be sent without danger of corrupting any currently transmitting character if the 10552 * transmitter is first disabled (TXDIS in CTL is set) and then waiting for the transmitter to be disabled 10553 * (TXDISINT in STAT = 1) before writing 1 to TXBRKEN. 10554 */ 10555 #define USART_CTL_TXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXBRKEN_SHIFT)) & USART_CTL_TXBRKEN_MASK) 10556 #define USART_CTL_ADDRDET_MASK (0x4U) 10557 #define USART_CTL_ADDRDET_SHIFT (2U) 10558 /*! ADDRDET - Enable address detect mode. 10559 * 0b0..Disabled. The USART presents all incoming data. 10560 * 0b1..Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data 10561 * (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally, 10562 * generating a received data interrupt. Software can then check the data to see if this is an address that 10563 * should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled 10564 * normally. 10565 */ 10566 #define USART_CTL_ADDRDET(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_ADDRDET_SHIFT)) & USART_CTL_ADDRDET_MASK) 10567 #define USART_CTL_TXDIS_MASK (0x40U) 10568 #define USART_CTL_TXDIS_SHIFT (6U) 10569 /*! TXDIS - Transmit Disable. 10570 * 0b0..Not disabled. USART transmitter is not disabled. 10571 * 0b1..Disabled. USART transmitter is disabled after any character currently being transmitted is complete. This 10572 * feature can be used to facilitate software flow control. 10573 */ 10574 #define USART_CTL_TXDIS(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXDIS_SHIFT)) & USART_CTL_TXDIS_MASK) 10575 #define USART_CTL_CC_MASK (0x100U) 10576 #define USART_CTL_CC_SHIFT (8U) 10577 /*! CC - Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode. 10578 * 0b0..Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to 10579 * complete a character that is being received. 10580 * 0b1..Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on 10581 * Un_RxD independently from transmission on Un_TXD). 10582 */ 10583 #define USART_CTL_CC(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CC_SHIFT)) & USART_CTL_CC_MASK) 10584 #define USART_CTL_CLRCCONRX_MASK (0x200U) 10585 #define USART_CTL_CLRCCONRX_SHIFT (9U) 10586 /*! CLRCCONRX - Clear Continuous Clock. 10587 * 0b0..No effect. No effect on the CC bit. 10588 * 0b1..Auto-clear. The CC bit is automatically cleared when a complete character has been received. This bit is cleared at the same time. 10589 */ 10590 #define USART_CTL_CLRCCONRX(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CLRCCONRX_SHIFT)) & USART_CTL_CLRCCONRX_MASK) 10591 #define USART_CTL_AUTOBAUD_MASK (0x10000U) 10592 #define USART_CTL_AUTOBAUD_SHIFT (16U) 10593 /*! AUTOBAUD - Autobaud enable. 10594 * 0b0..Disabled. USART is in normal operating mode. 10595 * 0b1..Enabled. USART is in autobaud mode. This bit should only be set when the USART receiver is idle. The 10596 * first start bit of RX is measured and used the update the BRG register to match the received data rate. 10597 * AUTOBAUD is cleared once this process is complete, or if there is an AERR. 10598 */ 10599 #define USART_CTL_AUTOBAUD(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_AUTOBAUD_SHIFT)) & USART_CTL_AUTOBAUD_MASK) 10600 /*! @} */ 10601 10602 /*! @name STAT - USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them. */ 10603 /*! @{ */ 10604 #define USART_STAT_RXIDLE_MASK (0x2U) 10605 #define USART_STAT_RXIDLE_SHIFT (1U) 10606 /*! RXIDLE - Receiver Idle. When 0, indicates that the receiver is currently in the process of 10607 * receiving data. When 1, indicates that the receiver is not currently in the process of receiving 10608 * data. 10609 */ 10610 #define USART_STAT_RXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXIDLE_SHIFT)) & USART_STAT_RXIDLE_MASK) 10611 #define USART_STAT_TXIDLE_MASK (0x8U) 10612 #define USART_STAT_TXIDLE_SHIFT (3U) 10613 /*! TXIDLE - Transmitter Idle. When 0, indicates that the transmitter is currently in the process of 10614 * sending data.When 1, indicate that the transmitter is not currently in the process of sending 10615 * data. 10616 */ 10617 #define USART_STAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXIDLE_SHIFT)) & USART_STAT_TXIDLE_MASK) 10618 #define USART_STAT_CTS_MASK (0x10U) 10619 #define USART_STAT_CTS_SHIFT (4U) 10620 /*! CTS - This bit reflects the current state of the CTS signal, regardless of the setting of the 10621 * CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode 10622 * is enabled. 10623 */ 10624 #define USART_STAT_CTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_CTS_SHIFT)) & USART_STAT_CTS_MASK) 10625 #define USART_STAT_DELTACTS_MASK (0x20U) 10626 #define USART_STAT_DELTACTS_SHIFT (5U) 10627 /*! DELTACTS - This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software. 10628 */ 10629 #define USART_STAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTACTS_SHIFT)) & USART_STAT_DELTACTS_MASK) 10630 #define USART_STAT_TXDISSTAT_MASK (0x40U) 10631 #define USART_STAT_TXDISSTAT_SHIFT (6U) 10632 /*! TXDISSTAT - Transmitter Disabled Status flag. When 1, this bit indicates that the USART 10633 * transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1). 10634 */ 10635 #define USART_STAT_TXDISSTAT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXDISSTAT_SHIFT)) & USART_STAT_TXDISSTAT_MASK) 10636 #define USART_STAT_RXBRK_MASK (0x400U) 10637 #define USART_STAT_RXBRK_SHIFT (10U) 10638 /*! RXBRK - Received Break. This bit reflects the current state of the receiver break detection 10639 * logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also 10640 * be set when this condition occurs because the stop bit(s) for the character would be missing. 10641 * RXBRK is cleared when the Un_RXD pin goes high. 10642 */ 10643 #define USART_STAT_RXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXBRK_SHIFT)) & USART_STAT_RXBRK_MASK) 10644 #define USART_STAT_DELTARXBRK_MASK (0x800U) 10645 #define USART_STAT_DELTARXBRK_SHIFT (11U) 10646 /*! DELTARXBRK - This bit is set when a change in the state of receiver break detection occurs. Cleared by software. 10647 */ 10648 #define USART_STAT_DELTARXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTARXBRK_SHIFT)) & USART_STAT_DELTARXBRK_MASK) 10649 #define USART_STAT_START_MASK (0x1000U) 10650 #define USART_STAT_START_SHIFT (12U) 10651 /*! START - This bit is set when a start is detected on the receiver input. Its purpose is primarily 10652 * to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. 10653 * Cleared by software. 10654 */ 10655 #define USART_STAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_START_SHIFT)) & USART_STAT_START_MASK) 10656 #define USART_STAT_FRAMERRINT_MASK (0x2000U) 10657 #define USART_STAT_FRAMERRINT_SHIFT (13U) 10658 /*! FRAMERRINT - Framing Error interrupt flag. This flag is set when a character is received with a 10659 * missing stop bit at the expected location. This could be an indication of a baud rate or 10660 * configuration mismatch with the transmitting source. 10661 */ 10662 #define USART_STAT_FRAMERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_FRAMERRINT_SHIFT)) & USART_STAT_FRAMERRINT_MASK) 10663 #define USART_STAT_PARITYERRINT_MASK (0x4000U) 10664 #define USART_STAT_PARITYERRINT_SHIFT (14U) 10665 /*! PARITYERRINT - Parity Error interrupt flag. This flag is set when a parity error is detected in a received character. 10666 */ 10667 #define USART_STAT_PARITYERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_PARITYERRINT_SHIFT)) & USART_STAT_PARITYERRINT_MASK) 10668 #define USART_STAT_RXNOISEINT_MASK (0x8000U) 10669 #define USART_STAT_RXNOISEINT_SHIFT (15U) 10670 /*! RXNOISEINT - Received Noise interrupt flag. Three samples of received data are taken in order to 10671 * determine the value of each received data bit, except in synchronous mode. This acts as a 10672 * noise filter if one sample disagrees. This flag is set when a received data bit contains one 10673 * disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or 10674 * loss of synchronization during data reception. 10675 */ 10676 #define USART_STAT_RXNOISEINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXNOISEINT_SHIFT)) & USART_STAT_RXNOISEINT_MASK) 10677 #define USART_STAT_ABERR_MASK (0x10000U) 10678 #define USART_STAT_ABERR_SHIFT (16U) 10679 /*! ABERR - Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the 10680 * end of the start bit that is being measured, essentially an auto baud time-out. 10681 */ 10682 #define USART_STAT_ABERR(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_ABERR_SHIFT)) & USART_STAT_ABERR_MASK) 10683 /*! @} */ 10684 10685 /*! @name INTENSET - Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */ 10686 /*! @{ */ 10687 #define USART_INTENSET_TXIDLEEN_MASK (0x8U) 10688 #define USART_INTENSET_TXIDLEEN_SHIFT (3U) 10689 /*! TXIDLEEN - When 1, enables an interrupt when the transmitter becomes idle (TXIDLE = 1). 10690 */ 10691 #define USART_INTENSET_TXIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXIDLEEN_SHIFT)) & USART_INTENSET_TXIDLEEN_MASK) 10692 #define USART_INTENSET_DELTACTSEN_MASK (0x20U) 10693 #define USART_INTENSET_DELTACTSEN_SHIFT (5U) 10694 /*! DELTACTSEN - When 1, enables an interrupt when there is a change in the state of the CTS input. 10695 */ 10696 #define USART_INTENSET_DELTACTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTACTSEN_SHIFT)) & USART_INTENSET_DELTACTSEN_MASK) 10697 #define USART_INTENSET_TXDISEN_MASK (0x40U) 10698 #define USART_INTENSET_TXDISEN_SHIFT (6U) 10699 /*! TXDISEN - When 1, enables an interrupt when the transmitter is fully disabled as indicated by 10700 * the TXDISINT flag in STAT. See description of the TXDISINT bit for details. 10701 */ 10702 #define USART_INTENSET_TXDISEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXDISEN_SHIFT)) & USART_INTENSET_TXDISEN_MASK) 10703 #define USART_INTENSET_DELTARXBRKEN_MASK (0x800U) 10704 #define USART_INTENSET_DELTARXBRKEN_SHIFT (11U) 10705 /*! DELTARXBRKEN - When 1, enables an interrupt when a change of state has occurred in the detection 10706 * of a received break condition (break condition asserted or deasserted). 10707 */ 10708 #define USART_INTENSET_DELTARXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTARXBRKEN_SHIFT)) & USART_INTENSET_DELTARXBRKEN_MASK) 10709 #define USART_INTENSET_STARTEN_MASK (0x1000U) 10710 #define USART_INTENSET_STARTEN_SHIFT (12U) 10711 /*! STARTEN - When 1, enables an interrupt when a received start bit has been detected. 10712 */ 10713 #define USART_INTENSET_STARTEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_STARTEN_SHIFT)) & USART_INTENSET_STARTEN_MASK) 10714 #define USART_INTENSET_FRAMERREN_MASK (0x2000U) 10715 #define USART_INTENSET_FRAMERREN_SHIFT (13U) 10716 /*! FRAMERREN - When 1, enables an interrupt when a framing error has been detected. 10717 */ 10718 #define USART_INTENSET_FRAMERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_FRAMERREN_SHIFT)) & USART_INTENSET_FRAMERREN_MASK) 10719 #define USART_INTENSET_PARITYERREN_MASK (0x4000U) 10720 #define USART_INTENSET_PARITYERREN_SHIFT (14U) 10721 /*! PARITYERREN - When 1, enables an interrupt when a parity error has been detected. 10722 */ 10723 #define USART_INTENSET_PARITYERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_PARITYERREN_SHIFT)) & USART_INTENSET_PARITYERREN_MASK) 10724 #define USART_INTENSET_RXNOISEEN_MASK (0x8000U) 10725 #define USART_INTENSET_RXNOISEEN_SHIFT (15U) 10726 /*! RXNOISEEN - When 1, enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354. 10727 */ 10728 #define USART_INTENSET_RXNOISEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_RXNOISEEN_SHIFT)) & USART_INTENSET_RXNOISEEN_MASK) 10729 #define USART_INTENSET_ABERREN_MASK (0x10000U) 10730 #define USART_INTENSET_ABERREN_SHIFT (16U) 10731 /*! ABERREN - When 1, enables an interrupt when an auto baud error occurs. 10732 */ 10733 #define USART_INTENSET_ABERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_ABERREN_SHIFT)) & USART_INTENSET_ABERREN_MASK) 10734 /*! @} */ 10735 10736 /*! @name INTENCLR - Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared. */ 10737 /*! @{ */ 10738 #define USART_INTENCLR_TXIDLECLR_MASK (0x8U) 10739 #define USART_INTENCLR_TXIDLECLR_SHIFT (3U) 10740 /*! TXIDLECLR - Writing 1 clears the corresponding bit in the INTENSET register. 10741 */ 10742 #define USART_INTENCLR_TXIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXIDLECLR_SHIFT)) & USART_INTENCLR_TXIDLECLR_MASK) 10743 #define USART_INTENCLR_DELTACTSCLR_MASK (0x20U) 10744 #define USART_INTENCLR_DELTACTSCLR_SHIFT (5U) 10745 /*! DELTACTSCLR - Writing 1 clears the corresponding bit in the INTENSET register. 10746 */ 10747 #define USART_INTENCLR_DELTACTSCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTACTSCLR_SHIFT)) & USART_INTENCLR_DELTACTSCLR_MASK) 10748 #define USART_INTENCLR_TXDISCLR_MASK (0x40U) 10749 #define USART_INTENCLR_TXDISCLR_SHIFT (6U) 10750 /*! TXDISCLR - Writing 1 clears the corresponding bit in the INTENSET register. 10751 */ 10752 #define USART_INTENCLR_TXDISCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXDISCLR_SHIFT)) & USART_INTENCLR_TXDISCLR_MASK) 10753 #define USART_INTENCLR_DELTARXBRKCLR_MASK (0x800U) 10754 #define USART_INTENCLR_DELTARXBRKCLR_SHIFT (11U) 10755 /*! DELTARXBRKCLR - Writing 1 clears the corresponding bit in the INTENSET register. 10756 */ 10757 #define USART_INTENCLR_DELTARXBRKCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTARXBRKCLR_SHIFT)) & USART_INTENCLR_DELTARXBRKCLR_MASK) 10758 #define USART_INTENCLR_STARTCLR_MASK (0x1000U) 10759 #define USART_INTENCLR_STARTCLR_SHIFT (12U) 10760 /*! STARTCLR - Writing 1 clears the corresponding bit in the INTENSET register. 10761 */ 10762 #define USART_INTENCLR_STARTCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_STARTCLR_SHIFT)) & USART_INTENCLR_STARTCLR_MASK) 10763 #define USART_INTENCLR_FRAMERRCLR_MASK (0x2000U) 10764 #define USART_INTENCLR_FRAMERRCLR_SHIFT (13U) 10765 /*! FRAMERRCLR - Writing 1 clears the corresponding bit in the INTENSET register. 10766 */ 10767 #define USART_INTENCLR_FRAMERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_FRAMERRCLR_SHIFT)) & USART_INTENCLR_FRAMERRCLR_MASK) 10768 #define USART_INTENCLR_PARITYERRCLR_MASK (0x4000U) 10769 #define USART_INTENCLR_PARITYERRCLR_SHIFT (14U) 10770 /*! PARITYERRCLR - Writing 1 clears the corresponding bit in the INTENSET register. 10771 */ 10772 #define USART_INTENCLR_PARITYERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_PARITYERRCLR_SHIFT)) & USART_INTENCLR_PARITYERRCLR_MASK) 10773 #define USART_INTENCLR_RXNOISECLR_MASK (0x8000U) 10774 #define USART_INTENCLR_RXNOISECLR_SHIFT (15U) 10775 /*! RXNOISECLR - Writing 1 clears the corresponding bit in the INTENSET register. 10776 */ 10777 #define USART_INTENCLR_RXNOISECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_RXNOISECLR_SHIFT)) & USART_INTENCLR_RXNOISECLR_MASK) 10778 #define USART_INTENCLR_ABERRCLR_MASK (0x10000U) 10779 #define USART_INTENCLR_ABERRCLR_SHIFT (16U) 10780 /*! ABERRCLR - Writing 1 clears the corresponding bit in the INTENSET register. 10781 */ 10782 #define USART_INTENCLR_ABERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_ABERRCLR_SHIFT)) & USART_INTENCLR_ABERRCLR_MASK) 10783 /*! @} */ 10784 10785 /*! @name BRG - Baud Rate Generator register. 16-bit integer baud rate divisor value. */ 10786 /*! @{ */ 10787 #define USART_BRG_BRGVAL_MASK (0xFFFFU) 10788 #define USART_BRG_BRGVAL_SHIFT (0U) 10789 /*! BRGVAL - This value is used to divide the USART input clock to determine the baud rate, based on 10790 * the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is 10791 * divided by 2 before use by the USART function. 2 = FCLK is divided by 3 before use by the USART 10792 * function. 0xFFFF = FCLK is divided by 65,536 before use by the USART function. 10793 */ 10794 #define USART_BRG_BRGVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_BRG_BRGVAL_SHIFT)) & USART_BRG_BRGVAL_MASK) 10795 /*! @} */ 10796 10797 /*! @name INTSTAT - Interrupt status register. Reflects interrupts that are currently enabled. */ 10798 /*! @{ */ 10799 #define USART_INTSTAT_TXIDLE_MASK (0x8U) 10800 #define USART_INTSTAT_TXIDLE_SHIFT (3U) 10801 /*! TXIDLE - Transmitter Idle status. 10802 */ 10803 #define USART_INTSTAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXIDLE_SHIFT)) & USART_INTSTAT_TXIDLE_MASK) 10804 #define USART_INTSTAT_DELTACTS_MASK (0x20U) 10805 #define USART_INTSTAT_DELTACTS_SHIFT (5U) 10806 /*! DELTACTS - This bit is set when a change in the state of the CTS input is detected. 10807 */ 10808 #define USART_INTSTAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTACTS_SHIFT)) & USART_INTSTAT_DELTACTS_MASK) 10809 #define USART_INTSTAT_TXDISINT_MASK (0x40U) 10810 #define USART_INTSTAT_TXDISINT_SHIFT (6U) 10811 /*! TXDISINT - Transmitter Disabled Interrupt flag. 10812 */ 10813 #define USART_INTSTAT_TXDISINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXDISINT_SHIFT)) & USART_INTSTAT_TXDISINT_MASK) 10814 #define USART_INTSTAT_DELTARXBRK_MASK (0x800U) 10815 #define USART_INTSTAT_DELTARXBRK_SHIFT (11U) 10816 /*! DELTARXBRK - This bit is set when a change in the state of receiver break detection occurs. 10817 */ 10818 #define USART_INTSTAT_DELTARXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTARXBRK_SHIFT)) & USART_INTSTAT_DELTARXBRK_MASK) 10819 #define USART_INTSTAT_START_MASK (0x1000U) 10820 #define USART_INTSTAT_START_SHIFT (12U) 10821 /*! START - This bit is set when a start is detected on the receiver input. 10822 */ 10823 #define USART_INTSTAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_START_SHIFT)) & USART_INTSTAT_START_MASK) 10824 #define USART_INTSTAT_FRAMERRINT_MASK (0x2000U) 10825 #define USART_INTSTAT_FRAMERRINT_SHIFT (13U) 10826 /*! FRAMERRINT - Framing Error interrupt flag. 10827 */ 10828 #define USART_INTSTAT_FRAMERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_FRAMERRINT_SHIFT)) & USART_INTSTAT_FRAMERRINT_MASK) 10829 #define USART_INTSTAT_PARITYERRINT_MASK (0x4000U) 10830 #define USART_INTSTAT_PARITYERRINT_SHIFT (14U) 10831 /*! PARITYERRINT - Parity Error interrupt flag. 10832 */ 10833 #define USART_INTSTAT_PARITYERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_PARITYERRINT_SHIFT)) & USART_INTSTAT_PARITYERRINT_MASK) 10834 #define USART_INTSTAT_RXNOISEINT_MASK (0x8000U) 10835 #define USART_INTSTAT_RXNOISEINT_SHIFT (15U) 10836 /*! RXNOISEINT - Received Noise interrupt flag. 10837 */ 10838 #define USART_INTSTAT_RXNOISEINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_RXNOISEINT_SHIFT)) & USART_INTSTAT_RXNOISEINT_MASK) 10839 #define USART_INTSTAT_ABERRINT_MASK (0x10000U) 10840 #define USART_INTSTAT_ABERRINT_SHIFT (16U) 10841 /*! ABERRINT - Auto baud Error Interrupt flag. 10842 */ 10843 #define USART_INTSTAT_ABERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_ABERRINT_SHIFT)) & USART_INTSTAT_ABERRINT_MASK) 10844 /*! @} */ 10845 10846 /*! @name OSR - Oversample selection register for asynchronous communication. */ 10847 /*! @{ */ 10848 #define USART_OSR_OSRVAL_MASK (0xFU) 10849 #define USART_OSR_OSRVAL_SHIFT (0U) 10850 /*! OSRVAL - Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to 10851 * transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive 10852 * each data bit. 0xF= 16 function clocks are used to transmit and receive each data bit. 10853 */ 10854 #define USART_OSR_OSRVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_OSR_OSRVAL_SHIFT)) & USART_OSR_OSRVAL_MASK) 10855 /*! @} */ 10856 10857 /*! @name ADDR - Address register for automatic address matching. */ 10858 /*! @{ */ 10859 #define USART_ADDR_ADDRESS_MASK (0xFFU) 10860 #define USART_ADDR_ADDRESS_SHIFT (0U) 10861 /*! ADDRESS - 8-bit address used with automatic address matching. Used when address detection is 10862 * enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1). 10863 */ 10864 #define USART_ADDR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << USART_ADDR_ADDRESS_SHIFT)) & USART_ADDR_ADDRESS_MASK) 10865 /*! @} */ 10866 10867 /*! @name FIFOCFG - FIFO configuration and enable register. */ 10868 /*! @{ */ 10869 #define USART_FIFOCFG_ENABLETX_MASK (0x1U) 10870 #define USART_FIFOCFG_ENABLETX_SHIFT (0U) 10871 /*! ENABLETX - Enable the transmit FIFO. 10872 * 0b0..The transmit FIFO is not enabled. 10873 * 0b1..The transmit FIFO is enabled. 10874 */ 10875 #define USART_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLETX_SHIFT)) & USART_FIFOCFG_ENABLETX_MASK) 10876 #define USART_FIFOCFG_ENABLERX_MASK (0x2U) 10877 #define USART_FIFOCFG_ENABLERX_SHIFT (1U) 10878 /*! ENABLERX - Enable the receive FIFO. 10879 * 0b0..The receive FIFO is not enabled. 10880 * 0b1..The receive FIFO is enabled. 10881 */ 10882 #define USART_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLERX_SHIFT)) & USART_FIFOCFG_ENABLERX_MASK) 10883 #define USART_FIFOCFG_SIZE_MASK (0x30U) 10884 #define USART_FIFOCFG_SIZE_SHIFT (4U) 10885 /*! SIZE - FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 10886 * entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART. 10887 */ 10888 #define USART_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_SIZE_SHIFT)) & USART_FIFOCFG_SIZE_MASK) 10889 #define USART_FIFOCFG_DMATX_MASK (0x1000U) 10890 #define USART_FIFOCFG_DMATX_SHIFT (12U) 10891 /*! DMATX - DMA configuration for transmit. 10892 * 0b0..DMA is not used for the transmit function. 10893 * 0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. 10894 */ 10895 #define USART_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMATX_SHIFT)) & USART_FIFOCFG_DMATX_MASK) 10896 #define USART_FIFOCFG_DMARX_MASK (0x2000U) 10897 #define USART_FIFOCFG_DMARX_SHIFT (13U) 10898 /*! DMARX - DMA configuration for receive. 10899 * 0b0..DMA is not used for the receive function. 10900 * 0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. 10901 */ 10902 #define USART_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMARX_SHIFT)) & USART_FIFOCFG_DMARX_MASK) 10903 #define USART_FIFOCFG_WAKETX_MASK (0x4000U) 10904 #define USART_FIFOCFG_WAKETX_SHIFT (14U) 10905 /*! WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power 10906 * modes (up to power-down, as long as the peripheral function works in that power mode) without 10907 * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The 10908 * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware 10909 * Wake-up control register. 10910 * 0b0..Only enabled interrupts will wake up the device form reduced power modes. 10911 * 0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in 10912 * FIFOTRIG, even when the TXLVL interrupt is not enabled. 10913 */ 10914 #define USART_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKETX_SHIFT)) & USART_FIFOCFG_WAKETX_MASK) 10915 #define USART_FIFOCFG_WAKERX_MASK (0x8000U) 10916 #define USART_FIFOCFG_WAKERX_SHIFT (15U) 10917 /*! WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power 10918 * modes (up to power-down, as long as the peripheral function works in that power mode) without 10919 * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The 10920 * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware 10921 * Wake-up control register. 10922 * 0b0..Only enabled interrupts will wake up the device form reduced power modes. 10923 * 0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in 10924 * FIFOTRIG, even when the RXLVL interrupt is not enabled. 10925 */ 10926 #define USART_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKERX_SHIFT)) & USART_FIFOCFG_WAKERX_MASK) 10927 #define USART_FIFOCFG_EMPTYTX_MASK (0x10000U) 10928 #define USART_FIFOCFG_EMPTYTX_SHIFT (16U) 10929 /*! EMPTYTX - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied. 10930 */ 10931 #define USART_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYTX_SHIFT)) & USART_FIFOCFG_EMPTYTX_MASK) 10932 #define USART_FIFOCFG_EMPTYRX_MASK (0x20000U) 10933 #define USART_FIFOCFG_EMPTYRX_SHIFT (17U) 10934 /*! EMPTYRX - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied. 10935 */ 10936 #define USART_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYRX_SHIFT)) & USART_FIFOCFG_EMPTYRX_MASK) 10937 /*! @} */ 10938 10939 /*! @name FIFOSTAT - FIFO status register. */ 10940 /*! @{ */ 10941 #define USART_FIFOSTAT_TXERR_MASK (0x1U) 10942 #define USART_FIFOSTAT_TXERR_SHIFT (0U) 10943 /*! TXERR - TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow 10944 * caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is 10945 * needed. Cleared by writing a 1 to this bit. 10946 */ 10947 #define USART_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXERR_SHIFT)) & USART_FIFOSTAT_TXERR_MASK) 10948 #define USART_FIFOSTAT_RXERR_MASK (0x2U) 10949 #define USART_FIFOSTAT_RXERR_SHIFT (1U) 10950 /*! RXERR - RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA 10951 * not emptying the FIFO fast enough. Cleared by writing a 1 to this bit. 10952 */ 10953 #define USART_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXERR_SHIFT)) & USART_FIFOSTAT_RXERR_MASK) 10954 #define USART_FIFOSTAT_PERINT_MASK (0x8U) 10955 #define USART_FIFOSTAT_PERINT_SHIFT (3U) 10956 /*! PERINT - Peripheral interrupt. When 1, this indicates that the peripheral function has asserted 10957 * an interrupt. The details can be found by reading the peripheral's STAT register. 10958 */ 10959 #define USART_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_PERINT_SHIFT)) & USART_FIFOSTAT_PERINT_MASK) 10960 #define USART_FIFOSTAT_TXEMPTY_MASK (0x10U) 10961 #define USART_FIFOSTAT_TXEMPTY_SHIFT (4U) 10962 /*! TXEMPTY - Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data. 10963 */ 10964 #define USART_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXEMPTY_SHIFT)) & USART_FIFOSTAT_TXEMPTY_MASK) 10965 #define USART_FIFOSTAT_TXNOTFULL_MASK (0x20U) 10966 #define USART_FIFOSTAT_TXNOTFULL_SHIFT (5U) 10967 /*! TXNOTFULL - Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be 10968 * written. When 0, the transmit FIFO is full and another write would cause it to overflow. 10969 */ 10970 #define USART_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXNOTFULL_SHIFT)) & USART_FIFOSTAT_TXNOTFULL_MASK) 10971 #define USART_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) 10972 #define USART_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) 10973 /*! RXNOTEMPTY - Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty. 10974 */ 10975 #define USART_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXNOTEMPTY_SHIFT)) & USART_FIFOSTAT_RXNOTEMPTY_MASK) 10976 #define USART_FIFOSTAT_RXFULL_MASK (0x80U) 10977 #define USART_FIFOSTAT_RXFULL_SHIFT (7U) 10978 /*! RXFULL - Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to 10979 * prevent the peripheral from causing an overflow. 10980 */ 10981 #define USART_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXFULL_SHIFT)) & USART_FIFOSTAT_RXFULL_MASK) 10982 #define USART_FIFOSTAT_TXLVL_MASK (0x1F00U) 10983 #define USART_FIFOSTAT_TXLVL_SHIFT (8U) 10984 /*! TXLVL - Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY 10985 * and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at 10986 * the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be 10987 * 0. 10988 */ 10989 #define USART_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXLVL_SHIFT)) & USART_FIFOSTAT_TXLVL_MASK) 10990 #define USART_FIFOSTAT_RXLVL_MASK (0x1F0000U) 10991 #define USART_FIFOSTAT_RXLVL_SHIFT (16U) 10992 /*! RXLVL - Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and 10993 * RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the 10994 * point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be 10995 * 1. 10996 */ 10997 #define USART_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXLVL_SHIFT)) & USART_FIFOSTAT_RXLVL_MASK) 10998 /*! @} */ 10999 11000 /*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ 11001 /*! @{ */ 11002 #define USART_FIFOTRIG_TXLVLENA_MASK (0x1U) 11003 #define USART_FIFOTRIG_TXLVLENA_SHIFT (0U) 11004 /*! TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled 11005 * in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set. 11006 * 0b0..Transmit FIFO level does not generate a FIFO level trigger. 11007 * 0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. 11008 */ 11009 #define USART_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVLENA_SHIFT)) & USART_FIFOTRIG_TXLVLENA_MASK) 11010 #define USART_FIFOTRIG_RXLVLENA_MASK (0x2U) 11011 #define USART_FIFOTRIG_RXLVLENA_SHIFT (1U) 11012 /*! RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled 11013 * in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. 11014 * 0b0..Receive FIFO level does not generate a FIFO level trigger. 11015 * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. 11016 */ 11017 #define USART_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVLENA_SHIFT)) & USART_FIFOTRIG_RXLVLENA_MASK) 11018 #define USART_FIFOTRIG_TXLVL_MASK (0xF00U) 11019 #define USART_FIFOTRIG_TXLVL_SHIFT (8U) 11020 /*! TXLVL - Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled 11021 * to do so, the FIFO level can wake up the device just enough to perform DMA, then return to 11022 * the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO 11023 * becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX 11024 * FIFO level decreases to 15 entries (is no longer full). 11025 */ 11026 #define USART_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVL_SHIFT)) & USART_FIFOTRIG_TXLVL_MASK) 11027 #define USART_FIFOTRIG_RXLVL_MASK (0xF0000U) 11028 #define USART_FIFOTRIG_RXLVL_SHIFT (16U) 11029 /*! RXLVL - Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data 11030 * is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level 11031 * can wake up the device just enough to perform DMA, then return to the reduced power mode. See 11032 * Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no 11033 * longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX 11034 * FIFO has received 16 entries (has become full). 11035 */ 11036 #define USART_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVL_SHIFT)) & USART_FIFOTRIG_RXLVL_MASK) 11037 /*! @} */ 11038 11039 /*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ 11040 /*! @{ */ 11041 #define USART_FIFOINTENSET_TXERR_MASK (0x1U) 11042 #define USART_FIFOINTENSET_TXERR_SHIFT (0U) 11043 /*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. 11044 * 0b0..No interrupt will be generated for a transmit error. 11045 * 0b1..An interrupt will be generated when a transmit error occurs. 11046 */ 11047 #define USART_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXERR_SHIFT)) & USART_FIFOINTENSET_TXERR_MASK) 11048 #define USART_FIFOINTENSET_RXERR_MASK (0x2U) 11049 #define USART_FIFOINTENSET_RXERR_SHIFT (1U) 11050 /*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. 11051 * 0b0..No interrupt will be generated for a receive error. 11052 * 0b1..An interrupt will be generated when a receive error occurs. 11053 */ 11054 #define USART_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXERR_SHIFT)) & USART_FIFOINTENSET_RXERR_MASK) 11055 #define USART_FIFOINTENSET_TXLVL_MASK (0x4U) 11056 #define USART_FIFOINTENSET_TXLVL_SHIFT (2U) 11057 /*! TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level 11058 * specified by the TXLVL field in the FIFOTRIG register. 11059 * 0b0..No interrupt will be generated based on the TX FIFO level. 11060 * 0b1..If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases 11061 * to the level specified by TXLVL in the FIFOTRIG register. 11062 */ 11063 #define USART_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXLVL_SHIFT)) & USART_FIFOINTENSET_TXLVL_MASK) 11064 #define USART_FIFOINTENSET_RXLVL_MASK (0x8U) 11065 #define USART_FIFOINTENSET_RXLVL_SHIFT (3U) 11066 /*! RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level 11067 * specified by the TXLVL field in the FIFOTRIG register. 11068 * 0b0..No interrupt will be generated based on the RX FIFO level. 11069 * 0b1..If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level 11070 * increases to the level specified by RXLVL in the FIFOTRIG register. 11071 */ 11072 #define USART_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXLVL_SHIFT)) & USART_FIFOINTENSET_RXLVL_MASK) 11073 /*! @} */ 11074 11075 /*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ 11076 /*! @{ */ 11077 #define USART_FIFOINTENCLR_TXERR_MASK (0x1U) 11078 #define USART_FIFOINTENCLR_TXERR_SHIFT (0U) 11079 /*! TXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. 11080 */ 11081 #define USART_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXERR_SHIFT)) & USART_FIFOINTENCLR_TXERR_MASK) 11082 #define USART_FIFOINTENCLR_RXERR_MASK (0x2U) 11083 #define USART_FIFOINTENCLR_RXERR_SHIFT (1U) 11084 /*! RXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. 11085 */ 11086 #define USART_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXERR_SHIFT)) & USART_FIFOINTENCLR_RXERR_MASK) 11087 #define USART_FIFOINTENCLR_TXLVL_MASK (0x4U) 11088 #define USART_FIFOINTENCLR_TXLVL_SHIFT (2U) 11089 /*! TXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. 11090 */ 11091 #define USART_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXLVL_SHIFT)) & USART_FIFOINTENCLR_TXLVL_MASK) 11092 #define USART_FIFOINTENCLR_RXLVL_MASK (0x8U) 11093 #define USART_FIFOINTENCLR_RXLVL_SHIFT (3U) 11094 /*! RXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. 11095 */ 11096 #define USART_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXLVL_SHIFT)) & USART_FIFOINTENCLR_RXLVL_MASK) 11097 /*! @} */ 11098 11099 /*! @name FIFOINTSTAT - FIFO interrupt status register. */ 11100 /*! @{ */ 11101 #define USART_FIFOINTSTAT_TXERR_MASK (0x1U) 11102 #define USART_FIFOINTSTAT_TXERR_SHIFT (0U) 11103 /*! TXERR - TX FIFO error. 11104 */ 11105 #define USART_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXERR_SHIFT)) & USART_FIFOINTSTAT_TXERR_MASK) 11106 #define USART_FIFOINTSTAT_RXERR_MASK (0x2U) 11107 #define USART_FIFOINTSTAT_RXERR_SHIFT (1U) 11108 /*! RXERR - RX FIFO error. 11109 */ 11110 #define USART_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXERR_SHIFT)) & USART_FIFOINTSTAT_RXERR_MASK) 11111 #define USART_FIFOINTSTAT_TXLVL_MASK (0x4U) 11112 #define USART_FIFOINTSTAT_TXLVL_SHIFT (2U) 11113 /*! TXLVL - Transmit FIFO level interrupt. 11114 */ 11115 #define USART_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXLVL_SHIFT)) & USART_FIFOINTSTAT_TXLVL_MASK) 11116 #define USART_FIFOINTSTAT_RXLVL_MASK (0x8U) 11117 #define USART_FIFOINTSTAT_RXLVL_SHIFT (3U) 11118 /*! RXLVL - Receive FIFO level interrupt. 11119 */ 11120 #define USART_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXLVL_SHIFT)) & USART_FIFOINTSTAT_RXLVL_MASK) 11121 #define USART_FIFOINTSTAT_PERINT_MASK (0x10U) 11122 #define USART_FIFOINTSTAT_PERINT_SHIFT (4U) 11123 /*! PERINT - Peripheral interrupt. 11124 */ 11125 #define USART_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_PERINT_SHIFT)) & USART_FIFOINTSTAT_PERINT_MASK) 11126 /*! @} */ 11127 11128 /*! @name FIFOWR - FIFO write data. */ 11129 /*! @{ */ 11130 #define USART_FIFOWR_TXDATA_MASK (0x1FFU) 11131 #define USART_FIFOWR_TXDATA_SHIFT (0U) 11132 /*! TXDATA - Transmit data to the FIFO. 11133 */ 11134 #define USART_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOWR_TXDATA_SHIFT)) & USART_FIFOWR_TXDATA_MASK) 11135 /*! @} */ 11136 11137 /*! @name FIFORD - FIFO read data. */ 11138 /*! @{ */ 11139 #define USART_FIFORD_RXDATA_MASK (0x1FFU) 11140 #define USART_FIFORD_RXDATA_SHIFT (0U) 11141 /*! RXDATA - Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings. 11142 */ 11143 #define USART_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXDATA_SHIFT)) & USART_FIFORD_RXDATA_MASK) 11144 #define USART_FIFORD_FRAMERR_MASK (0x2000U) 11145 #define USART_FIFORD_FRAMERR_SHIFT (13U) 11146 /*! FRAMERR - Framing Error status flag. This bit reflects the status for the data it is read along 11147 * with from the FIFO, and indicates that the character was received with a missing stop bit at 11148 * the expected location. This could be an indication of a baud rate or configuration mismatch 11149 * with the transmitting source. 11150 */ 11151 #define USART_FIFORD_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_FRAMERR_SHIFT)) & USART_FIFORD_FRAMERR_MASK) 11152 #define USART_FIFORD_PARITYERR_MASK (0x4000U) 11153 #define USART_FIFORD_PARITYERR_SHIFT (14U) 11154 /*! PARITYERR - Parity Error status flag. This bit reflects the status for the data it is read along 11155 * with from the FIFO. This bit will be set when a parity error is detected in a received 11156 * character. 11157 */ 11158 #define USART_FIFORD_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_PARITYERR_SHIFT)) & USART_FIFORD_PARITYERR_MASK) 11159 #define USART_FIFORD_RXNOISE_MASK (0x8000U) 11160 #define USART_FIFORD_RXNOISE_SHIFT (15U) 11161 /*! RXNOISE - Received Noise flag. See description of the RxNoiseInt bit in Table 354. 11162 */ 11163 #define USART_FIFORD_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXNOISE_SHIFT)) & USART_FIFORD_RXNOISE_MASK) 11164 /*! @} */ 11165 11166 /*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ 11167 /*! @{ */ 11168 #define USART_FIFORDNOPOP_RXDATA_MASK (0x1FFU) 11169 #define USART_FIFORDNOPOP_RXDATA_SHIFT (0U) 11170 /*! RXDATA - Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings. 11171 */ 11172 #define USART_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXDATA_SHIFT)) & USART_FIFORDNOPOP_RXDATA_MASK) 11173 #define USART_FIFORDNOPOP_FRAMERR_MASK (0x2000U) 11174 #define USART_FIFORDNOPOP_FRAMERR_SHIFT (13U) 11175 /*! FRAMERR - Framing Error status flag. This bit reflects the status for the data it is read along 11176 * with from the FIFO, and indicates that the character was received with a missing stop bit at 11177 * the expected location. This could be an indication of a baud rate or configuration mismatch 11178 * with the transmitting source. 11179 */ 11180 #define USART_FIFORDNOPOP_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_FRAMERR_SHIFT)) & USART_FIFORDNOPOP_FRAMERR_MASK) 11181 #define USART_FIFORDNOPOP_PARITYERR_MASK (0x4000U) 11182 #define USART_FIFORDNOPOP_PARITYERR_SHIFT (14U) 11183 /*! PARITYERR - Parity Error status flag. This bit reflects the status for the data it is read along 11184 * with from the FIFO. This bit will be set when a parity error is detected in a received 11185 * character. 11186 */ 11187 #define USART_FIFORDNOPOP_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_PARITYERR_SHIFT)) & USART_FIFORDNOPOP_PARITYERR_MASK) 11188 #define USART_FIFORDNOPOP_RXNOISE_MASK (0x8000U) 11189 #define USART_FIFORDNOPOP_RXNOISE_SHIFT (15U) 11190 /*! RXNOISE - Received Noise flag. See description of the RxNoiseInt bit in Table 354. 11191 */ 11192 #define USART_FIFORDNOPOP_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXNOISE_SHIFT)) & USART_FIFORDNOPOP_RXNOISE_MASK) 11193 /*! @} */ 11194 11195 11196 /*! 11197 * @} 11198 */ /* end of group USART_Register_Masks */ 11199 11200 11201 /* USART - Peripheral instance base addresses */ 11202 /** Peripheral USART0 base address */ 11203 #define USART0_BASE (0x40086000u) 11204 /** Peripheral USART0 base pointer */ 11205 #define USART0 ((USART_Type *)USART0_BASE) 11206 /** Peripheral USART1 base address */ 11207 #define USART1_BASE (0x40087000u) 11208 /** Peripheral USART1 base pointer */ 11209 #define USART1 ((USART_Type *)USART1_BASE) 11210 /** Peripheral USART2 base address */ 11211 #define USART2_BASE (0x40088000u) 11212 /** Peripheral USART2 base pointer */ 11213 #define USART2 ((USART_Type *)USART2_BASE) 11214 /** Peripheral USART3 base address */ 11215 #define USART3_BASE (0x40089000u) 11216 /** Peripheral USART3 base pointer */ 11217 #define USART3 ((USART_Type *)USART3_BASE) 11218 /** Peripheral USART4 base address */ 11219 #define USART4_BASE (0x4008A000u) 11220 /** Peripheral USART4 base pointer */ 11221 #define USART4 ((USART_Type *)USART4_BASE) 11222 /** Peripheral USART5 base address */ 11223 #define USART5_BASE (0x40096000u) 11224 /** Peripheral USART5 base pointer */ 11225 #define USART5 ((USART_Type *)USART5_BASE) 11226 /** Peripheral USART6 base address */ 11227 #define USART6_BASE (0x40097000u) 11228 /** Peripheral USART6 base pointer */ 11229 #define USART6 ((USART_Type *)USART6_BASE) 11230 /** Peripheral USART7 base address */ 11231 #define USART7_BASE (0x40098000u) 11232 /** Peripheral USART7 base pointer */ 11233 #define USART7 ((USART_Type *)USART7_BASE) 11234 /** Array initializer of USART peripheral base addresses */ 11235 #define USART_BASE_ADDRS { USART0_BASE, USART1_BASE, USART2_BASE, USART3_BASE, USART4_BASE, USART5_BASE, USART6_BASE, USART7_BASE } 11236 /** Array initializer of USART peripheral base pointers */ 11237 #define USART_BASE_PTRS { USART0, USART1, USART2, USART3, USART4, USART5, USART6, USART7 } 11238 /** Interrupt vectors for the USART peripheral type */ 11239 #define USART_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } 11240 11241 /*! 11242 * @} 11243 */ /* end of group USART_Peripheral_Access_Layer */ 11244 11245 11246 /* ---------------------------------------------------------------------------- 11247 -- USB Peripheral Access Layer 11248 ---------------------------------------------------------------------------- */ 11249 11250 /*! 11251 * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer 11252 * @{ 11253 */ 11254 11255 /** USB - Register Layout Typedef */ 11256 typedef struct { 11257 __IO uint32_t DEVCMDSTAT; /**< USB Device Command/Status register, offset: 0x0 */ 11258 __IO uint32_t INFO; /**< USB Info register, offset: 0x4 */ 11259 __IO uint32_t EPLISTSTART; /**< USB EP Command/Status List start address, offset: 0x8 */ 11260 __IO uint32_t DATABUFSTART; /**< USB Data buffer start address, offset: 0xC */ 11261 __IO uint32_t LPM; /**< USB Link Power Management register, offset: 0x10 */ 11262 __IO uint32_t EPSKIP; /**< USB Endpoint skip, offset: 0x14 */ 11263 __IO uint32_t EPINUSE; /**< USB Endpoint Buffer in use, offset: 0x18 */ 11264 __IO uint32_t EPBUFCFG; /**< USB Endpoint Buffer Configuration register, offset: 0x1C */ 11265 __IO uint32_t INTSTAT; /**< USB interrupt status register, offset: 0x20 */ 11266 __IO uint32_t INTEN; /**< USB interrupt enable register, offset: 0x24 */ 11267 __IO uint32_t INTSETSTAT; /**< USB set interrupt status register, offset: 0x28 */ 11268 uint8_t RESERVED_0[8]; 11269 __I uint32_t EPTOGGLE; /**< USB Endpoint toggle register, offset: 0x34 */ 11270 } USB_Type; 11271 11272 /* ---------------------------------------------------------------------------- 11273 -- USB Register Masks 11274 ---------------------------------------------------------------------------- */ 11275 11276 /*! 11277 * @addtogroup USB_Register_Masks USB Register Masks 11278 * @{ 11279 */ 11280 11281 /*! @name DEVCMDSTAT - USB Device Command/Status register */ 11282 /*! @{ */ 11283 #define USB_DEVCMDSTAT_DEV_ADDR_MASK (0x7FU) 11284 #define USB_DEVCMDSTAT_DEV_ADDR_SHIFT (0U) 11285 /*! DEV_ADDR - USB device address. After bus reset, the address is reset to 0x00. If the enable bit 11286 * is set, the device will respond on packets for function address DEV_ADDR. When receiving a 11287 * SetAddress Control Request from the USB host, software must program the new address before 11288 * completing the status phase of the SetAddress Control Request. 11289 */ 11290 #define USB_DEVCMDSTAT_DEV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_ADDR_SHIFT)) & USB_DEVCMDSTAT_DEV_ADDR_MASK) 11291 #define USB_DEVCMDSTAT_DEV_EN_MASK (0x80U) 11292 #define USB_DEVCMDSTAT_DEV_EN_SHIFT (7U) 11293 /*! DEV_EN - USB device enable. If this bit is set, the HW will start responding on packets for function address DEV_ADDR. 11294 */ 11295 #define USB_DEVCMDSTAT_DEV_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_EN_SHIFT)) & USB_DEVCMDSTAT_DEV_EN_MASK) 11296 #define USB_DEVCMDSTAT_SETUP_MASK (0x100U) 11297 #define USB_DEVCMDSTAT_SETUP_SHIFT (8U) 11298 /*! SETUP - SETUP token received. If a SETUP token is received and acknowledged by the device, this 11299 * bit is set. As long as this bit is set all received IN and OUT tokens will be NAKed by HW. SW 11300 * must clear this bit by writing a one. If this bit is zero, HW will handle the tokens to the 11301 * CTRL EP0 as indicated by the CTRL EP0 IN and OUT data information programmed by SW. 11302 */ 11303 #define USB_DEVCMDSTAT_SETUP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_SETUP_SHIFT)) & USB_DEVCMDSTAT_SETUP_MASK) 11304 #define USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK (0x200U) 11305 #define USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT (9U) 11306 /*! FORCE_NEEDCLK - Forces the NEEDCLK output to always be on: 11307 * 0b0..USB_NEEDCLK has normal function. 11308 * 0b1..USB_NEEDCLK always 1. Clock will not be stopped in case of suspend. 11309 */ 11310 #define USB_DEVCMDSTAT_FORCE_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT)) & USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK) 11311 #define USB_DEVCMDSTAT_LPM_SUP_MASK (0x800U) 11312 #define USB_DEVCMDSTAT_LPM_SUP_SHIFT (11U) 11313 /*! LPM_SUP - LPM Supported: 11314 * 0b0..LPM not supported. 11315 * 0b1..LPM supported. 11316 */ 11317 #define USB_DEVCMDSTAT_LPM_SUP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUP_SHIFT)) & USB_DEVCMDSTAT_LPM_SUP_MASK) 11318 #define USB_DEVCMDSTAT_INTONNAK_AO_MASK (0x1000U) 11319 #define USB_DEVCMDSTAT_INTONNAK_AO_SHIFT (12U) 11320 /*! INTONNAK_AO - Interrupt on NAK for interrupt and bulk OUT EP 11321 * 0b0..Only acknowledged packets generate an interrupt 11322 * 0b1..Both acknowledged and NAKed packets generate interrupts. 11323 */ 11324 #define USB_DEVCMDSTAT_INTONNAK_AO(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AO_MASK) 11325 #define USB_DEVCMDSTAT_INTONNAK_AI_MASK (0x2000U) 11326 #define USB_DEVCMDSTAT_INTONNAK_AI_SHIFT (13U) 11327 /*! INTONNAK_AI - Interrupt on NAK for interrupt and bulk IN EP 11328 * 0b0..Only acknowledged packets generate an interrupt 11329 * 0b1..Both acknowledged and NAKed packets generate interrupts. 11330 */ 11331 #define USB_DEVCMDSTAT_INTONNAK_AI(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AI_MASK) 11332 #define USB_DEVCMDSTAT_INTONNAK_CO_MASK (0x4000U) 11333 #define USB_DEVCMDSTAT_INTONNAK_CO_SHIFT (14U) 11334 /*! INTONNAK_CO - Interrupt on NAK for control OUT EP 11335 * 0b0..Only acknowledged packets generate an interrupt 11336 * 0b1..Both acknowledged and NAKed packets generate interrupts. 11337 */ 11338 #define USB_DEVCMDSTAT_INTONNAK_CO(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CO_MASK) 11339 #define USB_DEVCMDSTAT_INTONNAK_CI_MASK (0x8000U) 11340 #define USB_DEVCMDSTAT_INTONNAK_CI_SHIFT (15U) 11341 /*! INTONNAK_CI - Interrupt on NAK for control IN EP 11342 * 0b0..Only acknowledged packets generate an interrupt 11343 * 0b1..Both acknowledged and NAKed packets generate interrupts. 11344 */ 11345 #define USB_DEVCMDSTAT_INTONNAK_CI(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CI_MASK) 11346 #define USB_DEVCMDSTAT_DCON_MASK (0x10000U) 11347 #define USB_DEVCMDSTAT_DCON_SHIFT (16U) 11348 /*! DCON - Device status - connect. The connect bit must be set by SW to indicate that the device 11349 * must signal a connect. The pull-up resistor on USB_DP will be enabled when this bit is set and 11350 * the VBUSDEBOUNCED bit is one. 11351 */ 11352 #define USB_DEVCMDSTAT_DCON(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_SHIFT)) & USB_DEVCMDSTAT_DCON_MASK) 11353 #define USB_DEVCMDSTAT_DSUS_MASK (0x20000U) 11354 #define USB_DEVCMDSTAT_DSUS_SHIFT (17U) 11355 /*! DSUS - Device status - suspend. The suspend bit indicates the current suspend state. It is set 11356 * to 1 when the device hasn't seen any activity on its upstream port for more than 3 11357 * milliseconds. It is reset to 0 on any activity. When the device is suspended (Suspend bit DSUS = 1) and 11358 * the software writes a 0 to it, the device will generate a remote wake-up. This will only happen 11359 * when the device is connected (Connect bit = 1). When the device is not connected or not 11360 * suspended, a writing a 0 has no effect. Writing a 1 never has an effect. 11361 */ 11362 #define USB_DEVCMDSTAT_DSUS(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_SHIFT)) & USB_DEVCMDSTAT_DSUS_MASK) 11363 #define USB_DEVCMDSTAT_LPM_SUS_MASK (0x80000U) 11364 #define USB_DEVCMDSTAT_LPM_SUS_SHIFT (19U) 11365 /*! LPM_SUS - Device status - LPM Suspend. This bit represents the current LPM suspend state. It is 11366 * set to 1 by HW when the device has acknowledged the LPM request from the USB host and the 11367 * Token Retry Time of 10 ms has elapsed. When the device is in the LPM suspended state (LPM suspend 11368 * bit = 1) and the software writes a zero to this bit, the device will generate a remote 11369 * walk-up. Software can only write a zero to this bit when the LPM_REWP bit is set to 1. HW resets this 11370 * bit when it receives a host initiated resume. HW only updates the LPM_SUS bit when the 11371 * LPM_SUPP bit is equal to one. 11372 */ 11373 #define USB_DEVCMDSTAT_LPM_SUS(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUS_SHIFT)) & USB_DEVCMDSTAT_LPM_SUS_MASK) 11374 #define USB_DEVCMDSTAT_LPM_REWP_MASK (0x100000U) 11375 #define USB_DEVCMDSTAT_LPM_REWP_SHIFT (20U) 11376 /*! LPM_REWP - LPM Remote Wake-up Enabled by USB host. HW sets this bit to one when the bRemoteWake 11377 * bit in the LPM extended token is set to 1. HW will reset this bit to 0 when it receives the 11378 * host initiated LPM resume, when a remote wake-up is sent by the device or when a USB bus reset 11379 * is received. Software can use this bit to check if the remote wake-up feature is enabled by the 11380 * host for the LPM transaction. 11381 */ 11382 #define USB_DEVCMDSTAT_LPM_REWP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_REWP_SHIFT)) & USB_DEVCMDSTAT_LPM_REWP_MASK) 11383 #define USB_DEVCMDSTAT_DCON_C_MASK (0x1000000U) 11384 #define USB_DEVCMDSTAT_DCON_C_SHIFT (24U) 11385 /*! DCON_C - Device status - connect change. The Connect Change bit is set when the device's pull-up 11386 * resistor is disconnected because VBus disappeared. The bit is reset by writing a one to it. 11387 */ 11388 #define USB_DEVCMDSTAT_DCON_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_C_SHIFT)) & USB_DEVCMDSTAT_DCON_C_MASK) 11389 #define USB_DEVCMDSTAT_DSUS_C_MASK (0x2000000U) 11390 #define USB_DEVCMDSTAT_DSUS_C_SHIFT (25U) 11391 /*! DSUS_C - Device status - suspend change. The suspend change bit is set to 1 when the suspend bit 11392 * toggles. The suspend bit can toggle because: - The device goes in the suspended state - The 11393 * device is disconnected - The device receives resume signaling on its upstream port. The bit is 11394 * reset by writing a one to it. 11395 */ 11396 #define USB_DEVCMDSTAT_DSUS_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_C_SHIFT)) & USB_DEVCMDSTAT_DSUS_C_MASK) 11397 #define USB_DEVCMDSTAT_DRES_C_MASK (0x4000000U) 11398 #define USB_DEVCMDSTAT_DRES_C_SHIFT (26U) 11399 /*! DRES_C - Device status - reset change. This bit is set when the device received a bus reset. On 11400 * a bus reset the device will automatically go to the default state (unconfigured and responding 11401 * to address 0). The bit is reset by writing a one to it. 11402 */ 11403 #define USB_DEVCMDSTAT_DRES_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DRES_C_SHIFT)) & USB_DEVCMDSTAT_DRES_C_MASK) 11404 #define USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK (0x10000000U) 11405 #define USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT (28U) 11406 /*! VBUSDEBOUNCED - This bit indicates if Vbus is detected or not. The bit raises immediately when 11407 * Vbus becomes high. It drops to zero if Vbus is low for at least 3 ms. If this bit is high and 11408 * the DCon bit is set, the HW will enable the pull-up resistor to signal a connect. 11409 */ 11410 #define USB_DEVCMDSTAT_VBUSDEBOUNCED(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT)) & USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK) 11411 /*! @} */ 11412 11413 /*! @name INFO - USB Info register */ 11414 /*! @{ */ 11415 #define USB_INFO_FRAME_NR_MASK (0x7FFU) 11416 #define USB_INFO_FRAME_NR_SHIFT (0U) 11417 /*! FRAME_NR - Frame number. This contains the frame number of the last successfully received SOF. 11418 * In case no SOF was received by the device at the beginning of a frame, the frame number 11419 * returned is that of the last successfully received SOF. In case the SOF frame number contained a CRC 11420 * error, the frame number returned will be the corrupted frame number as received by the device. 11421 */ 11422 #define USB_INFO_FRAME_NR(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_FRAME_NR_SHIFT)) & USB_INFO_FRAME_NR_MASK) 11423 #define USB_INFO_ERR_CODE_MASK (0x7800U) 11424 #define USB_INFO_ERR_CODE_SHIFT (11U) 11425 /*! ERR_CODE - The error code which last occurred: 11426 * 0b0000..No error 11427 * 0b0001..PID encoding error 11428 * 0b0010..PID unknown 11429 * 0b0011..Packet unexpected 11430 * 0b0100..Token CRC error 11431 * 0b0101..Data CRC error 11432 * 0b0110..Time out 11433 * 0b0111..Babble 11434 * 0b1000..Truncated EOP 11435 * 0b1001..Sent/Received NAK 11436 * 0b1010..Sent Stall 11437 * 0b1011..Overrun 11438 * 0b1100..Sent empty packet 11439 * 0b1101..Bitstuff error 11440 * 0b1110..Sync error 11441 * 0b1111..Wrong data toggle 11442 */ 11443 #define USB_INFO_ERR_CODE(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_ERR_CODE_SHIFT)) & USB_INFO_ERR_CODE_MASK) 11444 /*! @} */ 11445 11446 /*! @name EPLISTSTART - USB EP Command/Status List start address */ 11447 /*! @{ */ 11448 #define USB_EPLISTSTART_EP_LIST_MASK (0xFFFFFF00U) 11449 #define USB_EPLISTSTART_EP_LIST_SHIFT (8U) 11450 /*! EP_LIST - Start address of the USB EP Command/Status List. 11451 */ 11452 #define USB_EPLISTSTART_EP_LIST(x) (((uint32_t)(((uint32_t)(x)) << USB_EPLISTSTART_EP_LIST_SHIFT)) & USB_EPLISTSTART_EP_LIST_MASK) 11453 /*! @} */ 11454 11455 /*! @name DATABUFSTART - USB Data buffer start address */ 11456 /*! @{ */ 11457 #define USB_DATABUFSTART_DA_BUF_MASK (0xFFC00000U) 11458 #define USB_DATABUFSTART_DA_BUF_SHIFT (22U) 11459 /*! DA_BUF - Start address of the buffer pointer page where all endpoint data buffers are located. 11460 */ 11461 #define USB_DATABUFSTART_DA_BUF(x) (((uint32_t)(((uint32_t)(x)) << USB_DATABUFSTART_DA_BUF_SHIFT)) & USB_DATABUFSTART_DA_BUF_MASK) 11462 /*! @} */ 11463 11464 /*! @name LPM - USB Link Power Management register */ 11465 /*! @{ */ 11466 #define USB_LPM_HIRD_HW_MASK (0xFU) 11467 #define USB_LPM_HIRD_HW_SHIFT (0U) 11468 /*! HIRD_HW - Host Initiated Resume Duration - HW. This is the HIRD value from the last received LPM token 11469 */ 11470 #define USB_LPM_HIRD_HW(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_HW_SHIFT)) & USB_LPM_HIRD_HW_MASK) 11471 #define USB_LPM_HIRD_SW_MASK (0xF0U) 11472 #define USB_LPM_HIRD_SW_SHIFT (4U) 11473 /*! HIRD_SW - Host Initiated Resume Duration - SW. This is the time duration required by the USB 11474 * device system to come out of LPM initiated suspend after receiving the host initiated LPM resume. 11475 */ 11476 #define USB_LPM_HIRD_SW(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_SW_SHIFT)) & USB_LPM_HIRD_SW_MASK) 11477 #define USB_LPM_DATA_PENDING_MASK (0x100U) 11478 #define USB_LPM_DATA_PENDING_SHIFT (8U) 11479 /*! DATA_PENDING - As long as this bit is set to one and LPM supported bit is set to one, HW will 11480 * return a NYET handshake on every LPM token it receives. If LPM supported bit is set to one and 11481 * this bit is zero, HW will return an ACK handshake on every LPM token it receives. If SW has 11482 * still data pending and LPM is supported, it must set this bit to 1. 11483 */ 11484 #define USB_LPM_DATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_DATA_PENDING_SHIFT)) & USB_LPM_DATA_PENDING_MASK) 11485 /*! @} */ 11486 11487 /*! @name EPSKIP - USB Endpoint skip */ 11488 /*! @{ */ 11489 #define USB_EPSKIP_SKIP_MASK (0x3FFFFFFFU) 11490 #define USB_EPSKIP_SKIP_SHIFT (0U) 11491 /*! SKIP - Endpoint skip: Writing 1 to one of these bits, will indicate to HW that it must 11492 * deactivate the buffer assigned to this endpoint and return control back to software. When HW has 11493 * deactivated the endpoint, it will clear this bit, but it will not modify the EPINUSE bit. An 11494 * interrupt will be generated when the Active bit goes from 1 to 0. Note: In case of double-buffering, 11495 * HW will only clear the Active bit of the buffer indicated by the EPINUSE bit. 11496 */ 11497 #define USB_EPSKIP_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USB_EPSKIP_SKIP_SHIFT)) & USB_EPSKIP_SKIP_MASK) 11498 /*! @} */ 11499 11500 /*! @name EPINUSE - USB Endpoint Buffer in use */ 11501 /*! @{ */ 11502 #define USB_EPINUSE_BUF_MASK (0x3FCU) 11503 #define USB_EPINUSE_BUF_SHIFT (2U) 11504 /*! BUF - Buffer in use: This register has one bit per physical endpoint. 0: HW is accessing buffer 11505 * 0. 1: HW is accessing buffer 1. 11506 */ 11507 #define USB_EPINUSE_BUF(x) (((uint32_t)(((uint32_t)(x)) << USB_EPINUSE_BUF_SHIFT)) & USB_EPINUSE_BUF_MASK) 11508 /*! @} */ 11509 11510 /*! @name EPBUFCFG - USB Endpoint Buffer Configuration register */ 11511 /*! @{ */ 11512 #define USB_EPBUFCFG_BUF_SB_MASK (0x3FCU) 11513 #define USB_EPBUFCFG_BUF_SB_SHIFT (2U) 11514 /*! BUF_SB - Buffer usage: This register has one bit per physical endpoint. 0: Single-buffer. 1: 11515 * Double-buffer. If the bit is set to single-buffer (0), it will not toggle the corresponding 11516 * EPINUSE bit when it clears the active bit. If the bit is set to double-buffer (1), HW will toggle 11517 * the EPINUSE bit when it clears the Active bit for the buffer. 11518 */ 11519 #define USB_EPBUFCFG_BUF_SB(x) (((uint32_t)(((uint32_t)(x)) << USB_EPBUFCFG_BUF_SB_SHIFT)) & USB_EPBUFCFG_BUF_SB_MASK) 11520 /*! @} */ 11521 11522 /*! @name INTSTAT - USB interrupt status register */ 11523 /*! @{ */ 11524 #define USB_INTSTAT_EP0OUT_MASK (0x1U) 11525 #define USB_INTSTAT_EP0OUT_SHIFT (0U) 11526 /*! EP0OUT - Interrupt status register bit for the Control EP0 OUT direction. This bit will be set 11527 * if NBytes transitions to zero or the skip bit is set by software or a SETUP packet is 11528 * successfully received for the control EP0. If the IntOnNAK_CO is set, this bit will also be set when a 11529 * NAK is transmitted for the Control EP0 OUT direction. Software can clear this bit by writing a 11530 * one to it. 11531 */ 11532 #define USB_INTSTAT_EP0OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0OUT_SHIFT)) & USB_INTSTAT_EP0OUT_MASK) 11533 #define USB_INTSTAT_EP0IN_MASK (0x2U) 11534 #define USB_INTSTAT_EP0IN_SHIFT (1U) 11535 /*! EP0IN - Interrupt status register bit for the Control EP0 IN direction. This bit will be set if 11536 * NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_CI is set, this 11537 * bit will also be set when a NAK is transmitted for the Control EP0 IN direction. Software can 11538 * clear this bit by writing a one to it. 11539 */ 11540 #define USB_INTSTAT_EP0IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0IN_SHIFT)) & USB_INTSTAT_EP0IN_MASK) 11541 #define USB_INTSTAT_EP1OUT_MASK (0x4U) 11542 #define USB_INTSTAT_EP1OUT_SHIFT (2U) 11543 /*! EP1OUT - Interrupt status register bit for the EP1 OUT direction. This bit will be set if the 11544 * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes 11545 * transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be 11546 * set when a NAK is transmitted for the EP1 OUT direction. Software can clear this bit by 11547 * writing a one to it. 11548 */ 11549 #define USB_INTSTAT_EP1OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1OUT_SHIFT)) & USB_INTSTAT_EP1OUT_MASK) 11550 #define USB_INTSTAT_EP1IN_MASK (0x8U) 11551 #define USB_INTSTAT_EP1IN_SHIFT (3U) 11552 /*! EP1IN - Interrupt status register bit for the EP1 IN direction. This bit will be set if the 11553 * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions 11554 * to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be 11555 * set when a NAK is transmitted for the EP1 IN direction. Software can clear this bit by writing 11556 * a one to it. 11557 */ 11558 #define USB_INTSTAT_EP1IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1IN_SHIFT)) & USB_INTSTAT_EP1IN_MASK) 11559 #define USB_INTSTAT_EP2OUT_MASK (0x10U) 11560 #define USB_INTSTAT_EP2OUT_SHIFT (4U) 11561 /*! EP2OUT - Interrupt status register bit for the EP2 OUT direction. This bit will be set if the 11562 * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes 11563 * transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be 11564 * set when a NAK is transmitted for the EP2 OUT direction. Software can clear this bit by 11565 * writing a one to it. 11566 */ 11567 #define USB_INTSTAT_EP2OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2OUT_SHIFT)) & USB_INTSTAT_EP2OUT_MASK) 11568 #define USB_INTSTAT_EP2IN_MASK (0x20U) 11569 #define USB_INTSTAT_EP2IN_SHIFT (5U) 11570 /*! EP2IN - Interrupt status register bit for the EP2 IN direction. This bit will be set if the 11571 * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions 11572 * to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be 11573 * set when a NAK is transmitted for the EP2 IN direction. Software can clear this bit by writing 11574 * a one to it. 11575 */ 11576 #define USB_INTSTAT_EP2IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2IN_SHIFT)) & USB_INTSTAT_EP2IN_MASK) 11577 #define USB_INTSTAT_EP3OUT_MASK (0x40U) 11578 #define USB_INTSTAT_EP3OUT_SHIFT (6U) 11579 /*! EP3OUT - Interrupt status register bit for the EP3 OUT direction. This bit will be set if the 11580 * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes 11581 * transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be 11582 * set when a NAK is transmitted for the EP3 OUT direction. Software can clear this bit by 11583 * writing a one to it. 11584 */ 11585 #define USB_INTSTAT_EP3OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3OUT_SHIFT)) & USB_INTSTAT_EP3OUT_MASK) 11586 #define USB_INTSTAT_EP3IN_MASK (0x80U) 11587 #define USB_INTSTAT_EP3IN_SHIFT (7U) 11588 /*! EP3IN - Interrupt status register bit for the EP3 IN direction. This bit will be set if the 11589 * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions 11590 * to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be 11591 * set when a NAK is transmitted for the EP3 IN direction. Software can clear this bit by writing 11592 * a one to it. 11593 */ 11594 #define USB_INTSTAT_EP3IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3IN_SHIFT)) & USB_INTSTAT_EP3IN_MASK) 11595 #define USB_INTSTAT_EP4OUT_MASK (0x100U) 11596 #define USB_INTSTAT_EP4OUT_SHIFT (8U) 11597 /*! EP4OUT - Interrupt status register bit for the EP4 OUT direction. This bit will be set if the 11598 * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes 11599 * transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be 11600 * set when a NAK is transmitted for the EP4 OUT direction. Software can clear this bit by 11601 * writing a one to it. 11602 */ 11603 #define USB_INTSTAT_EP4OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4OUT_SHIFT)) & USB_INTSTAT_EP4OUT_MASK) 11604 #define USB_INTSTAT_EP4IN_MASK (0x200U) 11605 #define USB_INTSTAT_EP4IN_SHIFT (9U) 11606 /*! EP4IN - Interrupt status register bit for the EP4 IN direction. This bit will be set if the 11607 * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions 11608 * to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be 11609 * set when a NAK is transmitted for the EP4 IN direction. Software can clear this bit by writing 11610 * a one to it. 11611 */ 11612 #define USB_INTSTAT_EP4IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4IN_SHIFT)) & USB_INTSTAT_EP4IN_MASK) 11613 #define USB_INTSTAT_FRAME_INT_MASK (0x40000000U) 11614 #define USB_INTSTAT_FRAME_INT_SHIFT (30U) 11615 /*! FRAME_INT - Frame interrupt. This bit is set to one every millisecond when the VbusDebounced bit 11616 * and the DCON bit are set. This bit can be used by software when handling isochronous 11617 * endpoints. Software can clear this bit by writing a one to it. 11618 */ 11619 #define USB_INTSTAT_FRAME_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_FRAME_INT_SHIFT)) & USB_INTSTAT_FRAME_INT_MASK) 11620 #define USB_INTSTAT_DEV_INT_MASK (0x80000000U) 11621 #define USB_INTSTAT_DEV_INT_SHIFT (31U) 11622 /*! DEV_INT - Device status interrupt. This bit is set by HW when one of the bits in the Device 11623 * Status Change register are set. Software can clear this bit by writing a one to it. 11624 */ 11625 #define USB_INTSTAT_DEV_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_DEV_INT_SHIFT)) & USB_INTSTAT_DEV_INT_MASK) 11626 /*! @} */ 11627 11628 /*! @name INTEN - USB interrupt enable register */ 11629 /*! @{ */ 11630 #define USB_INTEN_EP_INT_EN_MASK (0x3FFU) 11631 #define USB_INTEN_EP_INT_EN_SHIFT (0U) 11632 /*! EP_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW 11633 * interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing 11634 * bit. 11635 */ 11636 #define USB_INTEN_EP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_EP_INT_EN_SHIFT)) & USB_INTEN_EP_INT_EN_MASK) 11637 #define USB_INTEN_FRAME_INT_EN_MASK (0x40000000U) 11638 #define USB_INTEN_FRAME_INT_EN_SHIFT (30U) 11639 /*! FRAME_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW 11640 * interrupt is generated on the interrupt line indicated by the corresponding USB interrupt 11641 * routing bit. 11642 */ 11643 #define USB_INTEN_FRAME_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_FRAME_INT_EN_SHIFT)) & USB_INTEN_FRAME_INT_EN_MASK) 11644 #define USB_INTEN_DEV_INT_EN_MASK (0x80000000U) 11645 #define USB_INTEN_DEV_INT_EN_SHIFT (31U) 11646 /*! DEV_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW 11647 * interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing 11648 * bit. 11649 */ 11650 #define USB_INTEN_DEV_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_DEV_INT_EN_SHIFT)) & USB_INTEN_DEV_INT_EN_MASK) 11651 /*! @} */ 11652 11653 /*! @name INTSETSTAT - USB set interrupt status register */ 11654 /*! @{ */ 11655 #define USB_INTSETSTAT_EP_SET_INT_MASK (0x3FFU) 11656 #define USB_INTSETSTAT_EP_SET_INT_SHIFT (0U) 11657 /*! EP_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt 11658 * status bit is set. When this register is read, the same value as the USB interrupt status register 11659 * is returned. 11660 */ 11661 #define USB_INTSETSTAT_EP_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_EP_SET_INT_SHIFT)) & USB_INTSETSTAT_EP_SET_INT_MASK) 11662 #define USB_INTSETSTAT_FRAME_SET_INT_MASK (0x40000000U) 11663 #define USB_INTSETSTAT_FRAME_SET_INT_SHIFT (30U) 11664 /*! FRAME_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt 11665 * status bit is set. When this register is read, the same value as the USB interrupt status 11666 * register is returned. 11667 */ 11668 #define USB_INTSETSTAT_FRAME_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_FRAME_SET_INT_SHIFT)) & USB_INTSETSTAT_FRAME_SET_INT_MASK) 11669 #define USB_INTSETSTAT_DEV_SET_INT_MASK (0x80000000U) 11670 #define USB_INTSETSTAT_DEV_SET_INT_SHIFT (31U) 11671 /*! DEV_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt 11672 * status bit is set. When this register is read, the same value as the USB interrupt status 11673 * register is returned. 11674 */ 11675 #define USB_INTSETSTAT_DEV_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_DEV_SET_INT_SHIFT)) & USB_INTSETSTAT_DEV_SET_INT_MASK) 11676 /*! @} */ 11677 11678 /*! @name EPTOGGLE - USB Endpoint toggle register */ 11679 /*! @{ */ 11680 #define USB_EPTOGGLE_TOGGLE_MASK (0x3FFU) 11681 #define USB_EPTOGGLE_TOGGLE_SHIFT (0U) 11682 /*! TOGGLE - Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint. 11683 */ 11684 #define USB_EPTOGGLE_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << USB_EPTOGGLE_TOGGLE_SHIFT)) & USB_EPTOGGLE_TOGGLE_MASK) 11685 /*! @} */ 11686 11687 11688 /*! 11689 * @} 11690 */ /* end of group USB_Register_Masks */ 11691 11692 11693 /* USB - Peripheral instance base addresses */ 11694 /** Peripheral USB0 base address */ 11695 #define USB0_BASE (0x40084000u) 11696 /** Peripheral USB0 base pointer */ 11697 #define USB0 ((USB_Type *)USB0_BASE) 11698 /** Array initializer of USB peripheral base addresses */ 11699 #define USB_BASE_ADDRS { USB0_BASE } 11700 /** Array initializer of USB peripheral base pointers */ 11701 #define USB_BASE_PTRS { USB0 } 11702 /** Interrupt vectors for the USB peripheral type */ 11703 #define USB_IRQS { USB0_IRQn } 11704 #define USB_NEEDCLK_IRQS { USB0_NEEDCLK_IRQn } 11705 11706 /*! 11707 * @} 11708 */ /* end of group USB_Peripheral_Access_Layer */ 11709 11710 11711 /* ---------------------------------------------------------------------------- 11712 -- UTICK Peripheral Access Layer 11713 ---------------------------------------------------------------------------- */ 11714 11715 /*! 11716 * @addtogroup UTICK_Peripheral_Access_Layer UTICK Peripheral Access Layer 11717 * @{ 11718 */ 11719 11720 /** UTICK - Register Layout Typedef */ 11721 typedef struct { 11722 __IO uint32_t CTRL; /**< Control register., offset: 0x0 */ 11723 __IO uint32_t STAT; /**< Status register., offset: 0x4 */ 11724 __IO uint32_t CFG; /**< Capture configuration register., offset: 0x8 */ 11725 __O uint32_t CAPCLR; /**< Capture clear register., offset: 0xC */ 11726 __I uint32_t CAP[4]; /**< Capture register ., array offset: 0x10, array step: 0x4 */ 11727 } UTICK_Type; 11728 11729 /* ---------------------------------------------------------------------------- 11730 -- UTICK Register Masks 11731 ---------------------------------------------------------------------------- */ 11732 11733 /*! 11734 * @addtogroup UTICK_Register_Masks UTICK Register Masks 11735 * @{ 11736 */ 11737 11738 /*! @name CTRL - Control register. */ 11739 /*! @{ */ 11740 #define UTICK_CTRL_DELAYVAL_MASK (0x7FFFFFFFU) 11741 #define UTICK_CTRL_DELAYVAL_SHIFT (0U) 11742 /*! DELAYVAL - Tick interval value. The delay will be equal to DELAYVAL + 1 periods of the timer 11743 * clock. The minimum usable value is 1, for a delay of 2 timer clocks. A value of 0 stops the timer. 11744 */ 11745 #define UTICK_CTRL_DELAYVAL(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_DELAYVAL_SHIFT)) & UTICK_CTRL_DELAYVAL_MASK) 11746 #define UTICK_CTRL_REPEAT_MASK (0x80000000U) 11747 #define UTICK_CTRL_REPEAT_SHIFT (31U) 11748 /*! REPEAT - Repeat delay. 0 = One-time delay. 1 = Delay repeats continuously. 11749 */ 11750 #define UTICK_CTRL_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_REPEAT_SHIFT)) & UTICK_CTRL_REPEAT_MASK) 11751 /*! @} */ 11752 11753 /*! @name STAT - Status register. */ 11754 /*! @{ */ 11755 #define UTICK_STAT_INTR_MASK (0x1U) 11756 #define UTICK_STAT_INTR_SHIFT (0U) 11757 /*! INTR - Interrupt flag. 0 = No interrupt is pending. 1 = An interrupt is pending. A write of any 11758 * value to this register clears this flag. 11759 */ 11760 #define UTICK_STAT_INTR(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_INTR_SHIFT)) & UTICK_STAT_INTR_MASK) 11761 #define UTICK_STAT_ACTIVE_MASK (0x2U) 11762 #define UTICK_STAT_ACTIVE_SHIFT (1U) 11763 /*! ACTIVE - Active flag. 0 = The Micro-Tick Timer is stopped. 1 = The Micro-Tick Timer is currently active. 11764 */ 11765 #define UTICK_STAT_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_ACTIVE_SHIFT)) & UTICK_STAT_ACTIVE_MASK) 11766 /*! @} */ 11767 11768 /*! @name CFG - Capture configuration register. */ 11769 /*! @{ */ 11770 #define UTICK_CFG_CAPEN0_MASK (0x1U) 11771 #define UTICK_CFG_CAPEN0_SHIFT (0U) 11772 /*! CAPEN0 - Enable Capture 0. 1 = Enabled, 0 = Disabled. 11773 */ 11774 #define UTICK_CFG_CAPEN0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN0_SHIFT)) & UTICK_CFG_CAPEN0_MASK) 11775 #define UTICK_CFG_CAPEN1_MASK (0x2U) 11776 #define UTICK_CFG_CAPEN1_SHIFT (1U) 11777 /*! CAPEN1 - Enable Capture 1. 1 = Enabled, 0 = Disabled. 11778 */ 11779 #define UTICK_CFG_CAPEN1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN1_SHIFT)) & UTICK_CFG_CAPEN1_MASK) 11780 #define UTICK_CFG_CAPEN2_MASK (0x4U) 11781 #define UTICK_CFG_CAPEN2_SHIFT (2U) 11782 /*! CAPEN2 - Enable Capture 2. 1 = Enabled, 0 = Disabled. 11783 */ 11784 #define UTICK_CFG_CAPEN2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN2_SHIFT)) & UTICK_CFG_CAPEN2_MASK) 11785 #define UTICK_CFG_CAPEN3_MASK (0x8U) 11786 #define UTICK_CFG_CAPEN3_SHIFT (3U) 11787 /*! CAPEN3 - Enable Capture 3. 1 = Enabled, 0 = Disabled. 11788 */ 11789 #define UTICK_CFG_CAPEN3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN3_SHIFT)) & UTICK_CFG_CAPEN3_MASK) 11790 #define UTICK_CFG_CAPPOL0_MASK (0x100U) 11791 #define UTICK_CFG_CAPPOL0_SHIFT (8U) 11792 /*! CAPPOL0 - Capture Polarity 0. 0 = Positive edge capture, 1 = Negative edge capture. 11793 */ 11794 #define UTICK_CFG_CAPPOL0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL0_SHIFT)) & UTICK_CFG_CAPPOL0_MASK) 11795 #define UTICK_CFG_CAPPOL1_MASK (0x200U) 11796 #define UTICK_CFG_CAPPOL1_SHIFT (9U) 11797 /*! CAPPOL1 - Capture Polarity 1. 0 = Positive edge capture, 1 = Negative edge capture. 11798 */ 11799 #define UTICK_CFG_CAPPOL1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL1_SHIFT)) & UTICK_CFG_CAPPOL1_MASK) 11800 #define UTICK_CFG_CAPPOL2_MASK (0x400U) 11801 #define UTICK_CFG_CAPPOL2_SHIFT (10U) 11802 /*! CAPPOL2 - Capture Polarity 2. 0 = Positive edge capture, 1 = Negative edge capture. 11803 */ 11804 #define UTICK_CFG_CAPPOL2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL2_SHIFT)) & UTICK_CFG_CAPPOL2_MASK) 11805 #define UTICK_CFG_CAPPOL3_MASK (0x800U) 11806 #define UTICK_CFG_CAPPOL3_SHIFT (11U) 11807 /*! CAPPOL3 - Capture Polarity 3. 0 = Positive edge capture, 1 = Negative edge capture. 11808 */ 11809 #define UTICK_CFG_CAPPOL3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL3_SHIFT)) & UTICK_CFG_CAPPOL3_MASK) 11810 /*! @} */ 11811 11812 /*! @name CAPCLR - Capture clear register. */ 11813 /*! @{ */ 11814 #define UTICK_CAPCLR_CAPCLR0_MASK (0x1U) 11815 #define UTICK_CAPCLR_CAPCLR0_SHIFT (0U) 11816 /*! CAPCLR0 - Clear capture 0. Writing 1 to this bit clears the CAP0 register value. 11817 */ 11818 #define UTICK_CAPCLR_CAPCLR0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR0_SHIFT)) & UTICK_CAPCLR_CAPCLR0_MASK) 11819 #define UTICK_CAPCLR_CAPCLR1_MASK (0x2U) 11820 #define UTICK_CAPCLR_CAPCLR1_SHIFT (1U) 11821 /*! CAPCLR1 - Clear capture 1. Writing 1 to this bit clears the CAP1 register value. 11822 */ 11823 #define UTICK_CAPCLR_CAPCLR1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR1_SHIFT)) & UTICK_CAPCLR_CAPCLR1_MASK) 11824 #define UTICK_CAPCLR_CAPCLR2_MASK (0x4U) 11825 #define UTICK_CAPCLR_CAPCLR2_SHIFT (2U) 11826 /*! CAPCLR2 - Clear capture 2. Writing 1 to this bit clears the CAP2 register value. 11827 */ 11828 #define UTICK_CAPCLR_CAPCLR2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR2_SHIFT)) & UTICK_CAPCLR_CAPCLR2_MASK) 11829 #define UTICK_CAPCLR_CAPCLR3_MASK (0x8U) 11830 #define UTICK_CAPCLR_CAPCLR3_SHIFT (3U) 11831 /*! CAPCLR3 - Clear capture 3. Writing 1 to this bit clears the CAP3 register value. 11832 */ 11833 #define UTICK_CAPCLR_CAPCLR3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR3_SHIFT)) & UTICK_CAPCLR_CAPCLR3_MASK) 11834 /*! @} */ 11835 11836 /*! @name CAP - Capture register . */ 11837 /*! @{ */ 11838 #define UTICK_CAP_CAP_VALUE_MASK (0x7FFFFFFFU) 11839 #define UTICK_CAP_CAP_VALUE_SHIFT (0U) 11840 /*! CAP_VALUE - Capture value for the related capture event (UTICK_CAPn. Note: the value is 1 lower 11841 * than the actual value of the Micro-tick Timer at the moment of the capture event. 11842 */ 11843 #define UTICK_CAP_CAP_VALUE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_CAP_VALUE_SHIFT)) & UTICK_CAP_CAP_VALUE_MASK) 11844 #define UTICK_CAP_VALID_MASK (0x80000000U) 11845 #define UTICK_CAP_VALID_SHIFT (31U) 11846 /*! VALID - Capture Valid. When 1, a value has been captured based on a transition of the related 11847 * UTICK_CAPn pin. Cleared by writing to the related bit in the CAPCLR register. 11848 */ 11849 #define UTICK_CAP_VALID(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_VALID_SHIFT)) & UTICK_CAP_VALID_MASK) 11850 /*! @} */ 11851 11852 /* The count of UTICK_CAP */ 11853 #define UTICK_CAP_COUNT (4U) 11854 11855 11856 /*! 11857 * @} 11858 */ /* end of group UTICK_Register_Masks */ 11859 11860 11861 /* UTICK - Peripheral instance base addresses */ 11862 /** Peripheral UTICK0 base address */ 11863 #define UTICK0_BASE (0x4000E000u) 11864 /** Peripheral UTICK0 base pointer */ 11865 #define UTICK0 ((UTICK_Type *)UTICK0_BASE) 11866 /** Array initializer of UTICK peripheral base addresses */ 11867 #define UTICK_BASE_ADDRS { UTICK0_BASE } 11868 /** Array initializer of UTICK peripheral base pointers */ 11869 #define UTICK_BASE_PTRS { UTICK0 } 11870 /** Interrupt vectors for the UTICK peripheral type */ 11871 #define UTICK_IRQS { UTICK0_IRQn } 11872 11873 /*! 11874 * @} 11875 */ /* end of group UTICK_Peripheral_Access_Layer */ 11876 11877 11878 /* ---------------------------------------------------------------------------- 11879 -- WWDT Peripheral Access Layer 11880 ---------------------------------------------------------------------------- */ 11881 11882 /*! 11883 * @addtogroup WWDT_Peripheral_Access_Layer WWDT Peripheral Access Layer 11884 * @{ 11885 */ 11886 11887 /** WWDT - Register Layout Typedef */ 11888 typedef struct { 11889 __IO uint32_t MOD; /**< Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer., offset: 0x0 */ 11890 __IO uint32_t TC; /**< Watchdog timer constant register. This 24-bit register determines the time-out value., offset: 0x4 */ 11891 __O uint32_t FEED; /**< Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC., offset: 0x8 */ 11892 __I uint32_t TV; /**< Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer., offset: 0xC */ 11893 uint8_t RESERVED_0[4]; 11894 __IO uint32_t WARNINT; /**< Watchdog Warning Interrupt compare value., offset: 0x14 */ 11895 __IO uint32_t WINDOW; /**< Watchdog Window compare value., offset: 0x18 */ 11896 } WWDT_Type; 11897 11898 /* ---------------------------------------------------------------------------- 11899 -- WWDT Register Masks 11900 ---------------------------------------------------------------------------- */ 11901 11902 /*! 11903 * @addtogroup WWDT_Register_Masks WWDT Register Masks 11904 * @{ 11905 */ 11906 11907 /*! @name MOD - Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */ 11908 /*! @{ */ 11909 #define WWDT_MOD_WDEN_MASK (0x1U) 11910 #define WWDT_MOD_WDEN_SHIFT (0U) 11911 /*! WDEN - Watchdog enable bit. Once this bit is set to one and a watchdog feed is performed, the 11912 * watchdog timer will run permanently. 11913 * 0b0..Stop. The watchdog timer is stopped. 11914 * 0b1..Run. The watchdog timer is running. 11915 */ 11916 #define WWDT_MOD_WDEN(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDEN_SHIFT)) & WWDT_MOD_WDEN_MASK) 11917 #define WWDT_MOD_WDRESET_MASK (0x2U) 11918 #define WWDT_MOD_WDRESET_SHIFT (1U) 11919 /*! WDRESET - Watchdog reset enable bit. Once this bit has been written with a 1 it cannot be re-written with a 0. 11920 * 0b0..Interrupt. A watchdog time-out will not cause a chip reset. 11921 * 0b1..Reset. A watchdog time-out will cause a chip reset. 11922 */ 11923 #define WWDT_MOD_WDRESET(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDRESET_SHIFT)) & WWDT_MOD_WDRESET_MASK) 11924 #define WWDT_MOD_WDTOF_MASK (0x4U) 11925 #define WWDT_MOD_WDTOF_SHIFT (2U) 11926 /*! WDTOF - Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by 11927 * events associated with WDPROTECT. Cleared by software writing a 0 to this bit position. Causes a 11928 * chip reset if WDRESET = 1. 11929 */ 11930 #define WWDT_MOD_WDTOF(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDTOF_SHIFT)) & WWDT_MOD_WDTOF_MASK) 11931 #define WWDT_MOD_WDINT_MASK (0x8U) 11932 #define WWDT_MOD_WDINT_SHIFT (3U) 11933 /*! WDINT - Warning interrupt flag. Set when the timer is at or below the value in WDWARNINT. 11934 * Cleared by software writing a 1 to this bit position. Note that this bit cannot be cleared while the 11935 * WARNINT value is equal to the value of the TV register. This can occur if the value of 11936 * WARNINT is 0 and the WDRESET bit is 0 when TV decrements to 0. 11937 */ 11938 #define WWDT_MOD_WDINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDINT_SHIFT)) & WWDT_MOD_WDINT_MASK) 11939 #define WWDT_MOD_WDPROTECT_MASK (0x10U) 11940 #define WWDT_MOD_WDPROTECT_SHIFT (4U) 11941 /*! WDPROTECT - Watchdog update mode. This bit can be set once by software and is only cleared by a reset. 11942 * 0b0..Flexible. The watchdog time-out value (TC) can be changed at any time. 11943 * 0b1..Threshold. The watchdog time-out value (TC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW. 11944 */ 11945 #define WWDT_MOD_WDPROTECT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDPROTECT_SHIFT)) & WWDT_MOD_WDPROTECT_MASK) 11946 #define WWDT_MOD_LOCK_MASK (0x20U) 11947 #define WWDT_MOD_LOCK_SHIFT (5U) 11948 /*! LOCK - Once this bit is set to one and a watchdog feed is performed, disabling or powering down 11949 * the watchdog oscillator is prevented by hardware. This bit can be set once by software and is 11950 * only cleared by any reset. 11951 */ 11952 #define WWDT_MOD_LOCK(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_LOCK_SHIFT)) & WWDT_MOD_LOCK_MASK) 11953 /*! @} */ 11954 11955 /*! @name TC - Watchdog timer constant register. This 24-bit register determines the time-out value. */ 11956 /*! @{ */ 11957 #define WWDT_TC_COUNT_MASK (0xFFFFFFU) 11958 #define WWDT_TC_COUNT_SHIFT (0U) 11959 /*! COUNT - Watchdog time-out value. 11960 */ 11961 #define WWDT_TC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TC_COUNT_SHIFT)) & WWDT_TC_COUNT_MASK) 11962 /*! @} */ 11963 11964 /*! @name FEED - Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC. */ 11965 /*! @{ */ 11966 #define WWDT_FEED_FEED_MASK (0xFFU) 11967 #define WWDT_FEED_FEED_SHIFT (0U) 11968 /*! FEED - Feed value should be 0xAA followed by 0x55. 11969 */ 11970 #define WWDT_FEED_FEED(x) (((uint32_t)(((uint32_t)(x)) << WWDT_FEED_FEED_SHIFT)) & WWDT_FEED_FEED_MASK) 11971 /*! @} */ 11972 11973 /*! @name TV - Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer. */ 11974 /*! @{ */ 11975 #define WWDT_TV_COUNT_MASK (0xFFFFFFU) 11976 #define WWDT_TV_COUNT_SHIFT (0U) 11977 /*! COUNT - Counter timer value. 11978 */ 11979 #define WWDT_TV_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TV_COUNT_SHIFT)) & WWDT_TV_COUNT_MASK) 11980 /*! @} */ 11981 11982 /*! @name WARNINT - Watchdog Warning Interrupt compare value. */ 11983 /*! @{ */ 11984 #define WWDT_WARNINT_WARNINT_MASK (0x3FFU) 11985 #define WWDT_WARNINT_WARNINT_SHIFT (0U) 11986 /*! WARNINT - Watchdog warning interrupt compare value. 11987 */ 11988 #define WWDT_WARNINT_WARNINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WARNINT_WARNINT_SHIFT)) & WWDT_WARNINT_WARNINT_MASK) 11989 /*! @} */ 11990 11991 /*! @name WINDOW - Watchdog Window compare value. */ 11992 /*! @{ */ 11993 #define WWDT_WINDOW_WINDOW_MASK (0xFFFFFFU) 11994 #define WWDT_WINDOW_WINDOW_SHIFT (0U) 11995 /*! WINDOW - Watchdog window value. 11996 */ 11997 #define WWDT_WINDOW_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WINDOW_WINDOW_SHIFT)) & WWDT_WINDOW_WINDOW_MASK) 11998 /*! @} */ 11999 12000 12001 /*! 12002 * @} 12003 */ /* end of group WWDT_Register_Masks */ 12004 12005 12006 /* WWDT - Peripheral instance base addresses */ 12007 /** Peripheral WWDT base address */ 12008 #define WWDT_BASE (0x4000C000u) 12009 /** Peripheral WWDT base pointer */ 12010 #define WWDT ((WWDT_Type *)WWDT_BASE) 12011 /** Array initializer of WWDT peripheral base addresses */ 12012 #define WWDT_BASE_ADDRS { WWDT_BASE } 12013 /** Array initializer of WWDT peripheral base pointers */ 12014 #define WWDT_BASE_PTRS { WWDT } 12015 /** Interrupt vectors for the WWDT peripheral type */ 12016 #define WWDT_IRQS { WDT_BOD_IRQn } 12017 12018 /*! 12019 * @} 12020 */ /* end of group WWDT_Peripheral_Access_Layer */ 12021 12022 12023 /* 12024 ** End of section using anonymous unions 12025 */ 12026 12027 #if defined(__ARMCC_VERSION) 12028 #if (__ARMCC_VERSION >= 6010050) 12029 #pragma clang diagnostic pop 12030 #else 12031 #pragma pop 12032 #endif 12033 #elif defined(__GNUC__) 12034 /* leave anonymous unions enabled */ 12035 #elif defined(__IAR_SYSTEMS_ICC__) 12036 #pragma language=default 12037 #else 12038 #error Not supported compiler type 12039 #endif 12040 12041 /*! 12042 * @} 12043 */ /* end of group Peripheral_access_layer */ 12044 12045 12046 /* ---------------------------------------------------------------------------- 12047 -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). 12048 ---------------------------------------------------------------------------- */ 12049 12050 /*! 12051 * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). 12052 * @{ 12053 */ 12054 12055 #if defined(__ARMCC_VERSION) 12056 #if (__ARMCC_VERSION >= 6010050) 12057 #pragma clang system_header 12058 #endif 12059 #elif defined(__IAR_SYSTEMS_ICC__) 12060 #pragma system_include 12061 #endif 12062 12063 /** 12064 * @brief Mask and left-shift a bit field value for use in a register bit range. 12065 * @param field Name of the register bit field. 12066 * @param value Value of the bit field. 12067 * @return Masked and shifted value. 12068 */ 12069 #define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) 12070 /** 12071 * @brief Mask and right-shift a register value to extract a bit field value. 12072 * @param field Name of the register bit field. 12073 * @param value Value of the register. 12074 * @return Masked and shifted bit field value. 12075 */ 12076 #define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) 12077 12078 /*! 12079 * @} 12080 */ /* end of group Bit_Field_Generic_Macros */ 12081 12082 12083 /* ---------------------------------------------------------------------------- 12084 -- SDK Compatibility 12085 ---------------------------------------------------------------------------- */ 12086 12087 /*! 12088 * @addtogroup SDK_Compatibility_Symbols SDK Compatibility 12089 * @{ 12090 */ 12091 12092 /* No SDK compatibility issues. */ 12093 12094 /*! 12095 * @} 12096 */ /* end of group SDK_Compatibility_Symbols */ 12097 12098 12099 #endif /* _LPC54114_CM4_H_ */ 12100 12101
