1 /*
2 ** ###################################################################
3 **     Processors:          MCXN547VDF_cm33_core0
4 **                          MCXN547VNL_cm33_core0
5 **
6 **     Compilers:           GNU C Compiler
7 **                          IAR ANSI C/C++ Compiler for ARM
8 **                          Keil ARM C/C++ Compiler
9 **                          MCUXpresso Compiler
10 **
11 **     Reference manual:    MCXNx4x Reference Manual
12 **     Version:             rev. 2.0, 2023-02-01
13 **     Build:               b240510
14 **
15 **     Abstract:
16 **         CMSIS Peripheral Access Layer for MCXN547_cm33_core0
17 **
18 **     Copyright 1997-2016 Freescale Semiconductor, Inc.
19 **     Copyright 2016-2024 NXP
20 **     SPDX-License-Identifier: BSD-3-Clause
21 **
22 **     http:                 www.nxp.com
23 **     mail:                 support@nxp.com
24 **
25 **     Revisions:
26 **     - rev. 1.0 (2022-10-01)
27 **         Initial version
28 **     - rev. 2.0 (2023-02-01)
29 **         Initial version based on Rev. 2 Draft B
30 **
31 ** ###################################################################
32 */
33 
34 /*!
35  * @file MCXN547_cm33_core0.h
36  * @version 2.0
37  * @date 2023-02-01
38  * @brief CMSIS Peripheral Access Layer for MCXN547_cm33_core0
39  *
40  * CMSIS Peripheral Access Layer for MCXN547_cm33_core0
41  */
42 
43 #if !defined(MCXN547_CM33_CORE0_H_)
44 #define MCXN547_CM33_CORE0_H_                    /**< Symbol preventing repeated inclusion */
45 
46 /** Memory map major version (memory maps with equal major version number are
47  * compatible) */
48 #define MCU_MEM_MAP_VERSION 0x0200U
49 /** Memory map minor version */
50 #define MCU_MEM_MAP_VERSION_MINOR 0x0000U
51 
52 
53 /* ----------------------------------------------------------------------------
54    -- Interrupt vector numbers
55    ---------------------------------------------------------------------------- */
56 
57 /*!
58  * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
59  * @{
60  */
61 
62 /** Interrupt Number Definitions */
63 #define NUMBER_OF_INT_VECTORS 172                /**< Number of interrupts in the Vector table */
64 
65 typedef enum IRQn {
66   /* Auxiliary constants */
67   NotAvail_IRQn                = -128,             /**< Not available device specific interrupt */
68 
69   /* Core interrupts */
70   NonMaskableInt_IRQn          = -14,              /**< Non Maskable Interrupt */
71   HardFault_IRQn               = -13,              /**< Cortex-M33 SV Hard Fault Interrupt */
72   MemoryManagement_IRQn        = -12,              /**< Cortex-M33 Memory Management Interrupt */
73   BusFault_IRQn                = -11,              /**< Cortex-M33 Bus Fault Interrupt */
74   UsageFault_IRQn              = -10,              /**< Cortex-M33 Usage Fault Interrupt */
75   SecureFault_IRQn             = -9,               /**< Cortex-M33 Secure Fault Interrupt */
76   SVCall_IRQn                  = -5,               /**< Cortex-M33 SV Call Interrupt */
77   DebugMonitor_IRQn            = -4,               /**< Cortex-M33 Debug Monitor Interrupt */
78   PendSV_IRQn                  = -2,               /**< Cortex-M33 Pend SV Interrupt */
79   SysTick_IRQn                 = -1,               /**< Cortex-M33 System Tick Interrupt */
80 
81   /* Device specific interrupts */
82   OR_IRQn                      = 0,                /**< OR IRQ */
83   EDMA_0_CH0_IRQn              = 1,                /**< eDMA_0_CH0 error or transfer complete */
84   EDMA_0_CH1_IRQn              = 2,                /**< eDMA_0_CH1 error or transfer complete */
85   EDMA_0_CH2_IRQn              = 3,                /**< eDMA_0_CH2 error or transfer complete */
86   EDMA_0_CH3_IRQn              = 4,                /**< eDMA_0_CH3 error or transfer complete */
87   EDMA_0_CH4_IRQn              = 5,                /**< eDMA_0_CH4 error or transfer complete */
88   EDMA_0_CH5_IRQn              = 6,                /**< eDMA_0_CH5 error or transfer complete */
89   EDMA_0_CH6_IRQn              = 7,                /**< eDMA_0_CH6 error or transfer complete */
90   EDMA_0_CH7_IRQn              = 8,                /**< eDMA_0_CH7 error or transfer complete */
91   EDMA_0_CH8_IRQn              = 9,                /**< eDMA_0_CH8 error or transfer complete */
92   EDMA_0_CH9_IRQn              = 10,               /**< eDMA_0_CH9 error or transfer complete */
93   EDMA_0_CH10_IRQn             = 11,               /**< eDMA_0_CH10 error or transfer complete */
94   EDMA_0_CH11_IRQn             = 12,               /**< eDMA_0_CH11 error or transfer complete */
95   EDMA_0_CH12_IRQn             = 13,               /**< eDMA_0_CH12 error or transfer complete */
96   EDMA_0_CH13_IRQn             = 14,               /**< eDMA_0_CH13 error or transfer complete */
97   EDMA_0_CH14_IRQn             = 15,               /**< eDMA_0_CH14 error or transfer complete */
98   EDMA_0_CH15_IRQn             = 16,               /**< eDMA_0_CH15 error or transfer complete */
99   GPIO00_IRQn                  = 17,               /**< GPIO0 interrupt 0 */
100   GPIO01_IRQn                  = 18,               /**< GPIO0 interrupt 1 */
101   GPIO10_IRQn                  = 19,               /**< GPIO1 interrupt 0 */
102   GPIO11_IRQn                  = 20,               /**< GPIO1 interrupt 1 */
103   GPIO20_IRQn                  = 21,               /**< GPIO2 interrupt 0 */
104   GPIO21_IRQn                  = 22,               /**< GPIO2 interrupt 1 */
105   GPIO30_IRQn                  = 23,               /**< GPIO3 interrupt 0 */
106   GPIO31_IRQn                  = 24,               /**< GPIO3 interrupt 1 */
107   GPIO40_IRQn                  = 25,               /**< GPIO4 interrupt 0 */
108   GPIO41_IRQn                  = 26,               /**< GPIO4 interrupt 1 */
109   GPIO50_IRQn                  = 27,               /**< GPIO5 interrupt 0 */
110   GPIO51_IRQn                  = 28,               /**< GPIO5 interrupt 1 */
111   UTICK0_IRQn                  = 29,               /**< Micro-Tick Timer interrupt */
112   MRT0_IRQn                    = 30,               /**< Multi-Rate Timer interrupt */
113   CTIMER0_IRQn                 = 31,               /**< Standard counter/timer 0 interrupt */
114   CTIMER1_IRQn                 = 32,               /**< Standard counter/timer 1 interrupt */
115   SCT0_IRQn                    = 33,               /**< SCTimer/PWM interrupt */
116   CTIMER2_IRQn                 = 34,               /**< Standard counter/timer 2 interrupt */
117   LP_FLEXCOMM0_IRQn            = 35,               /**< LP_FLEXCOMM0 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */
118   LP_FLEXCOMM1_IRQn            = 36,               /**< LP_FLEXCOMM1 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */
119   LP_FLEXCOMM2_IRQn            = 37,               /**< LP_FLEXCOMM2 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */
120   LP_FLEXCOMM3_IRQn            = 38,               /**< LP_FLEXCOMM3 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */
121   LP_FLEXCOMM4_IRQn            = 39,               /**< LP_FLEXCOMM4 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */
122   LP_FLEXCOMM5_IRQn            = 40,               /**< LP_FLEXCOMM5 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */
123   LP_FLEXCOMM6_IRQn            = 41,               /**< LP_FLEXCOMM6 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */
124   LP_FLEXCOMM7_IRQn            = 42,               /**< LP_FLEXCOMM7 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */
125   LP_FLEXCOMM8_IRQn            = 43,               /**< LP_FLEXCOMM8 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */
126   LP_FLEXCOMM9_IRQn            = 44,               /**< LP_FLEXCOMM9 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */
127   ADC0_IRQn                    = 45,               /**< Analog-to-Digital Converter 0 - General Purpose interrupt */
128   ADC1_IRQn                    = 46,               /**< Analog-to-Digital Converter 1 - General Purpose interrupt */
129   PINT0_IRQn                   = 47,               /**< Pin Interrupt Pattern Match Interrupt */
130   PDM_EVENT_IRQn               = 48,               /**< Microphone Interface interrupt */
131   Reserved65_IRQn              = 49,               /**< Reserved interrupt */
132   USB0_FS_IRQn                 = 50,               /**< Universal Serial Bus - Full Speed interrupt */
133   USB0_DCD_IRQn                = 51,               /**< Universal Serial Bus - Device Charge Detect interrupt */
134   RTC_IRQn                     = 52,               /**< RTC Subsystem interrupt (RTC interrupt or Wake timer interrupt) */
135   SMARTDMA_IRQn                = 53,               /**< SmartDMA_IRQ */
136   MAILBOX_IRQn                 = 54,               /**< Inter-CPU Mailbox interrupt0 for CPU0 Inter-CPU Mailbox interrupt1 for CPU1 */
137   CTIMER3_IRQn                 = 55,               /**< Standard counter/timer 3 interrupt */
138   CTIMER4_IRQn                 = 56,               /**< Standard counter/timer 4 interrupt */
139   OS_EVENT_IRQn                = 57,               /**< OS event timer interrupt */
140   FLEXSPI0_IRQn                = 58,               /**< Flexible Serial Peripheral Interface interrupt */
141   SAI0_IRQn                    = 59,               /**< Serial Audio Interface 0 interrupt */
142   SAI1_IRQn                    = 60,               /**< Serial Audio Interface 1 interrupt */
143   USDHC0_IRQn                  = 61,               /**< Ultra Secured Digital Host Controller interrupt */
144   CAN0_IRQn                    = 62,               /**< Controller Area Network 0 interrupt */
145   Reserved79_IRQn              = 63,               /**< Reserved interrupt */
146   Reserved80_IRQn              = 64,               /**< Reserved interrupt */
147   Reserved81_IRQn              = 65,               /**< Reserved interrupt */
148   USB1_HS_PHY_IRQn             = 66,               /**< USBHS DCD or USBHS Phy interrupt */
149   USB1_HS_IRQn                 = 67,               /**< USB High Speed OTG Controller interrupt  */
150   SEC_HYPERVISOR_CALL_IRQn     = 68,               /**< AHB Secure Controller hypervisor call interrupt */
151   Reserved85_IRQn              = 69,               /**< Reserved interrupt */
152   PLU_IRQn                     = 70,               /**< Programmable Logic Unit interrupt */
153   Freqme_IRQn                  = 71,               /**< Frequency Measurement interrupt */
154   SEC_VIO_IRQn                 = 72,               /**< Secure violation interrupt (Memory Block Checker interrupt or secure AHB matrix violation interrupt) */
155   ELS_IRQn                     = 73,               /**< ELS interrupt */
156   PKC_IRQn                     = 74,               /**< PKC interrupt */
157   PUF_IRQn                     = 75,               /**< Physical Unclonable Function interrupt */
158   PQ_IRQn                      = 76,               /**< Power Quad interrupt */
159   EDMA_1_CH0_IRQn              = 77,               /**< eDMA_1_CH0 error or transfer complete */
160   EDMA_1_CH1_IRQn              = 78,               /**< eDMA_1_CH1 error or transfer complete */
161   EDMA_1_CH2_IRQn              = 79,               /**< eDMA_1_CH2 error or transfer complete */
162   EDMA_1_CH3_IRQn              = 80,               /**< eDMA_1_CH3 error or transfer complete */
163   EDMA_1_CH4_IRQn              = 81,               /**< eDMA_1_CH4 error or transfer complete */
164   EDMA_1_CH5_IRQn              = 82,               /**< eDMA_1_CH5 error or transfer complete */
165   EDMA_1_CH6_IRQn              = 83,               /**< eDMA_1_CH6 error or transfer complete */
166   EDMA_1_CH7_IRQn              = 84,               /**< eDMA_1_CH7 error or transfer complete */
167   EDMA_1_CH8_IRQn              = 85,               /**< eDMA_1_CH8 error or transfer complete */
168   EDMA_1_CH9_IRQn              = 86,               /**< eDMA_1_CH9 error or transfer complete */
169   EDMA_1_CH10_IRQn             = 87,               /**< eDMA_1_CH10 error or transfer complete */
170   EDMA_1_CH11_IRQn             = 88,               /**< eDMA_1_CH11 error or transfer complete */
171   EDMA_1_CH12_IRQn             = 89,               /**< eDMA_1_CH12 error or transfer complete */
172   EDMA_1_CH13_IRQn             = 90,               /**< eDMA_1_CH13 error or transfer complete */
173   EDMA_1_CH14_IRQn             = 91,               /**< eDMA_1_CH14 error or transfer complete */
174   EDMA_1_CH15_IRQn             = 92,               /**< eDMA_1_CH15 error or transfer complete */
175   CDOG0_IRQn                   = 93,               /**< Code Watchdog Timer 0 interrupt */
176   CDOG1_IRQn                   = 94,               /**< Code Watchdog Timer 1 interrupt */
177   I3C0_IRQn                    = 95,               /**< Improved Inter Integrated Circuit interrupt 0 */
178   I3C1_IRQn                    = 96,               /**< Improved Inter Integrated Circuit interrupt 1 */
179   NPU_IRQn                     = 97,               /**< NPU interrupt */
180   GDET_IRQn                    = 98,               /**< Digital Glitch Detect 0 interrupt  or Digital Glitch Detect 1 interrupt */
181   VBAT0_IRQn                   = 99,               /**< VBAT interrupt( VBAT interrupt or digital tamper interrupt) */
182   EWM0_IRQn                    = 100,              /**< External Watchdog Monitor interrupt */
183   TSI_END_OF_SCAN_IRQn         = 101,              /**< TSI End of Scan interrupt */
184   TSI_OUT_OF_SCAN_IRQn         = 102,              /**< TSI Out of Scan interrupt */
185   EMVSIM0_IRQn                 = 103,              /**< EMVSIM0 interrupt */
186   EMVSIM1_IRQn                 = 104,              /**< EMVSIM1 interrupt */
187   FLEXIO_IRQn                  = 105,              /**< Flexible Input/Output interrupt */
188   DAC0_IRQn                    = 106,              /**< Digital-to-Analog Converter 0 - General Purpose interrupt */
189   Reserved123_IRQn             = 107,              /**< Reserved interrupt */
190   Reserved124_IRQn             = 108,              /**< Reserved interrupt */
191   HSCMP0_IRQn                  = 109,              /**< High-Speed comparator0 interrupt */
192   HSCMP1_IRQn                  = 110,              /**< High-Speed comparator1 interrupt */
193   Reserved127_IRQn             = 111,              /**< Reserved interrupt */
194   FLEXPWM0_RELOAD_ERROR_IRQn   = 112,              /**< FlexPWM0_reload_error interrupt */
195   FLEXPWM0_FAULT_IRQn          = 113,              /**< FlexPWM0_fault interrupt */
196   FLEXPWM0_SUBMODULE0_IRQn     = 114,              /**< FlexPWM0 Submodule 0 capture/compare/reload interrupt */
197   FLEXPWM0_SUBMODULE1_IRQn     = 115,              /**< FlexPWM0 Submodule 1 capture/compare/reload interrupt */
198   FLEXPWM0_SUBMODULE2_IRQn     = 116,              /**< FlexPWM0 Submodule 2 capture/compare/reload interrupt */
199   FLEXPWM0_SUBMODULE3_IRQn     = 117,              /**< FlexPWM0 Submodule 3 capture/compare/reload interrupt */
200   Reserved134_IRQn             = 118,              /**< Reserved interrupt */
201   Reserved135_IRQn             = 119,              /**< Reserved interrupt */
202   Reserved136_IRQn             = 120,              /**< Reserved interrupt */
203   Reserved137_IRQn             = 121,              /**< Reserved interrupt */
204   Reserved138_IRQn             = 122,              /**< Reserved interrupt */
205   Reserved139_IRQn             = 123,              /**< Reserved interrupt */
206   QDC0_COMPARE_IRQn            = 124,              /**< QDC0_Compare interrupt */
207   QDC0_HOME_IRQn               = 125,              /**< QDC0_Home interrupt */
208   QDC0_WDG_SAB_IRQn            = 126,              /**< QDC0_WDG_IRQ/SAB interrupt */
209   QDC0_IDX_IRQn                = 127,              /**< QDC0_IDX interrupt */
210   QDC1_COMPARE_IRQn            = 128,              /**< QDC1_Compare interrupt */
211   QDC1_HOME_IRQn               = 129,              /**< QDC1_Home interrupt */
212   QDC1_WDG_SAB_IRQn            = 130,              /**< QDC1_WDG_IRQ/SAB interrupt */
213   QDC1_IDX_IRQn                = 131,              /**< QDC1_IDX interrupt */
214   ITRC0_IRQn                   = 132,              /**< Intrusion and Tamper Response Controller interrupt */
215   BSP32_IRQn                   = 133,              /**< CoolFlux BSP32 interrupt */
216   ELS_ERR_IRQn                 = 134,              /**< ELS error interrupt */
217   PKC_ERR_IRQn                 = 135,              /**< PKC error interrupt */
218   ERM_SINGLE_BIT_ERROR_IRQn    = 136,              /**< ERM Single Bit error interrupt */
219   ERM_MULTI_BIT_ERROR_IRQn     = 137,              /**< ERM Multi Bit error interrupt */
220   FMU0_IRQn                    = 138,              /**< Flash Management Unit interrupt */
221   ETHERNET_IRQn                = 139,              /**< Ethernet QoS interrupt */
222   ETHERNET_PMT_IRQn            = 140,              /**< Ethernet QoS power management interrupt */
223   ETHERNET_MACLP_IRQn          = 141,              /**< Ethernet QoS MAC interrupt */
224   Reserved158_IRQn             = 142,              /**< Reserved interrupt */
225   LPTMR0_IRQn                  = 143,              /**< Low Power Timer 0 interrupt */
226   LPTMR1_IRQn                  = 144,              /**< Low Power Timer 1 interrupt */
227   SCG_IRQn                     = 145,              /**< System Clock Generator interrupt */
228   SPC_IRQn                     = 146,              /**< System Power Controller interrupt */
229   WUU_IRQn                     = 147,              /**< Wake Up Unit interrupt */
230   PORT_EFT_IRQn                = 148,              /**< PORT0~5 EFT interrupt */
231   ETB0_IRQn                    = 149,              /**< ETB counter expires interrupt */
232   Reserved166_IRQn             = 150,              /**< Reserved interrupt */
233   Reserved167_IRQn             = 151,              /**< Reserved interrupt */
234   WWDT0_IRQn                   = 152,              /**< Windowed Watchdog Timer 0 interrupt */
235   WWDT1_IRQn                   = 153,              /**< Windowed Watchdog Timer 1 interrupt */
236   CMC0_IRQn                    = 154,              /**< Core Mode Controller interrupt */
237   CTI0_IRQn                    = 155               /**< Cross Trigger Interface interrupt */
238 } IRQn_Type;
239 
240 /*!
241  * @}
242  */ /* end of group Interrupt_vector_numbers */
243 
244 
245 /* ----------------------------------------------------------------------------
246    -- Cortex M33 Core Configuration
247    ---------------------------------------------------------------------------- */
248 
249 /*!
250  * @addtogroup Cortex_Core_Configuration Cortex M33 Core Configuration
251  * @{
252  */
253 
254 #define __MPU_PRESENT                  1         /**< Defines if an MPU is present or not */
255 #define __NVIC_PRIO_BITS               3         /**< Number of priority bits implemented in the NVIC */
256 #define __Vendor_SysTickConfig         0         /**< Vendor specific implementation of SysTickConfig is defined */
257 #define __FPU_PRESENT                  1         /**< Defines if an FPU is present or not */
258 #define __DSP_PRESENT                  1         /**< Defines if Armv8-M Mainline core supports DSP instructions */
259 #define __SAUREGION_PRESENT            1         /**< Defines if an SAU is present or not */
260 
261 #include "core_cm33.h"                 /* Core Peripheral Access Layer */
262 #include "system_MCXN547_cm33_core0.h" /* Device specific configuration file */
263 
264 /*!
265  * @}
266  */ /* end of group Cortex_Core_Configuration */
267 
268 
269 /* ----------------------------------------------------------------------------
270    -- Mapping Information
271    ---------------------------------------------------------------------------- */
272 
273 /*!
274  * @addtogroup Mapping_Information Mapping Information
275  * @{
276  */
277 
278 /** Mapping Information */
279 /*!
280  * @addtogroup dma_request
281  * @{
282  */
283 
284 /*******************************************************************************
285  * Definitions
286  ******************************************************************************/
287 
288 /*!
289  * @brief Structure for the DMA hardware request
290  *
291  * Defines the structure for the DMA hardware request collections. The user can configure the
292  * hardware request to trigger the DMA transfer accordingly. The index
293  * of the hardware request varies according  to the to SoC.
294  */
295 typedef enum _dma_request_source
296 {
297     kDma0RequestMuxFlexSpi0Rx       = 1U,          /**< FlexSPI0 Receive event */
298     kDma1RequestMuxFlexSpi0Rx       = 1U,          /**< FlexSPI0 Receive event */
299     kDma0RequestMuxFlexSpi0Tx       = 2U,          /**< FlexSPI0 Transmit event */
300     kDma1RequestMuxFlexSpi0Tx       = 2U,          /**< FlexSPI0 Transmit event */
301     kDma0RequestMuxPinInt0          = 3U,          /**< PINT0 INT0 */
302     kDma1RequestMuxPinInt0          = 3U,          /**< PINT0 INT0 */
303     kDma0RequestMuxPinInt1          = 4U,          /**< PINT0 INT1 */
304     kDma1RequestMuxPinInt1          = 4U,          /**< PINT0 INT1 */
305     kDma0RequestMuxPinInt2          = 5U,          /**< PINT0 INT2 */
306     kDma1RequestMuxPinInt2          = 5U,          /**< PINT0 INT2 */
307     kDma0RequestMuxPinInt3          = 6U,          /**< PINT0 INT3 */
308     kDma1RequestMuxPinInt3          = 6U,          /**< PINT0 INT3 */
309     kDma0RequestMuxCtimer0M0        = 7U,          /**< CTIMER0 Match channel 0 request */
310     kDma1RequestMuxCtimer0M0        = 7U,          /**< CTIMER0 Match channel 0 request */
311     kDma0RequestMuxCtimer0M1        = 8U,          /**< CTIMER0 Match channel 1 request */
312     kDma1RequestMuxCtimer0M1        = 8U,          /**< CTIMER0 Match channel 1 request */
313     kDma0RequestMuxCtimer1M0        = 9U,          /**< CTIMER1 Match channel 0 request */
314     kDma1RequestMuxCtimer1M0        = 9U,          /**< CTIMER1 Match channel 0 request */
315     kDma0RequestMuxCtimer1M1        = 10U,         /**< CTIMER1 Match channel 1 request */
316     kDma1RequestMuxCtimer1M1        = 10U,         /**< CTIMER1 Match channel 1 request */
317     kDma0RequestMuxCtimer2M0        = 11U,         /**< CTIMER2 Match channel 0 request */
318     kDma1RequestMuxCtimer2M0        = 11U,         /**< CTIMER2 Match channel 0 request */
319     kDma0RequestMuxCtimer2M1        = 12U,         /**< CTIMER2 Match channel 1 request */
320     kDma1RequestMuxCtimer2M1        = 12U,         /**< CTIMER2 Match channel 1 request */
321     kDma0RequestMuxCtimer3M0        = 13U,         /**< CTIMER3 Match channel 0 request */
322     kDma1RequestMuxCtimer3M0        = 13U,         /**< CTIMER3 Match channel 0 request */
323     kDma0RequestMuxCtimer3M1        = 14U,         /**< CTIMER3 Match channel 1 request */
324     kDma1RequestMuxCtimer3M1        = 14U,         /**< CTIMER3 Match channel 1 request */
325     kDma0RequestMuxCtimer4M0        = 15U,         /**< CTIMER4 Match channel 0 request */
326     kDma1RequestMuxCtimer4M0        = 15U,         /**< CTIMER4 Match channel 0 request */
327     kDma0RequestMuxCtimer4M1        = 16U,         /**< CTIMER4 Match channel 1 request */
328     kDma1RequestMuxCtimer4M1        = 16U,         /**< CTIMER4 Match channel 1 request */
329     kDma0RequestMuxWuu0             = 17U,         /**< WUU0 Wake up event */
330     kDma1RequestMuxWuu0             = 17U,         /**< WUU0 Wake up event */
331     kDma0RequestMuxMicfil0FifoRequest = 18U,       /**< MICFIL0 FIFO_request */
332     kDma1RequestMuxMicfil0FifoRequest = 18U,       /**< MICFIL0 FIFO_request */
333     kDma0RequestMuxSct0Dma0         = 19U,         /**< SCT0 DMA0 */
334     kDma1RequestMuxSct0Dma0         = 19U,         /**< SCT0 DMA0 */
335     kDma0RequestMuxSct0Dma1         = 20U,         /**< SCT0 DMA1 */
336     kDma1RequestMuxSct0Dma1         = 20U,         /**< SCT0 DMA1 */
337     kDma0RequestMuxAdc0FifoARequest = 21U,         /**< ADC0 FIFO A request */
338     kDma1RequestMuxAdc0FifoARequest = 21U,         /**< ADC0 FIFO A request */
339     kDma0RequestMuxAdc0FifoBRequest = 22U,         /**< ADC0 FIFO B request */
340     kDma1RequestMuxAdc0FifoBRequest = 22U,         /**< ADC0 FIFO B request */
341     kDma0RequestMuxAdc1FifoARequest = 23U,         /**< ADC1 FIFO A request */
342     kDma1RequestMuxAdc1FifoARequest = 23U,         /**< ADC1 FIFO A request */
343     kDma0RequestMuxAdc1FifoBRequest = 24U,         /**< ADC1 FIFO B request */
344     kDma1RequestMuxAdc1FifoBRequest = 24U,         /**< ADC1 FIFO B request */
345     kDma0RequestMuxDac0FifoRequest  = 25U,         /**< DAC0 FIFO_request */
346     kDma1RequestMuxDac0FifoRequest  = 25U,         /**< DAC0 FIFO_request */
347     kDma0RequestMuxHsCmp0DmaRequest = 28U,         /**< CMP0 DMA_request */
348     kDma1RequestMuxHsCmp0DmaRequest = 28U,         /**< CMP0 DMA_request */
349     kDma0RequestMuxHsCmp1DmaRequest = 29U,         /**< CMP1 DMA_request */
350     kDma1RequestMuxHsCmp1DmaRequest = 29U,         /**< CMP1 DMA_request */
351     kDma0RequestMuxEvtg0Out0A       = 31U,         /**< EVTG0 OUT0A */
352     kDma1RequestMuxEvtg0Out0A       = 31U,         /**< EVTG0 OUT0A */
353     kDma0RequestMuxEvtg0Out0B       = 32U,         /**< EVTG0 OUT0B */
354     kDma1RequestMuxEvtg0Out0B       = 32U,         /**< EVTG0 OUT0B */
355     kDma0RequestMuxEvtg0Out1A       = 33U,         /**< EVTG0 OUT1A */
356     kDma1RequestMuxEvtg0Out1A       = 33U,         /**< EVTG0 OUT1A */
357     kDma0RequestMuxEvtg0Out1B       = 34U,         /**< EVTG0 OUT1B */
358     kDma1RequestMuxEvtg0Out1B       = 34U,         /**< EVTG0 OUT1B */
359     kDma0RequestMuxEvtg0Out2A       = 35U,         /**< EVTG0 OUT2A */
360     kDma1RequestMuxEvtg0Out2A       = 35U,         /**< EVTG0 OUT2A */
361     kDma0RequestMuxEvtg0Out2B       = 36U,         /**< EVTG0 OUT2B */
362     kDma1RequestMuxEvtg0Out2B       = 36U,         /**< EVTG0 OUT2B */
363     kDma0RequestMuxEvtg0Out3A       = 37U,         /**< EVTG0 OUT3A */
364     kDma1RequestMuxEvtg0Out3A       = 37U,         /**< EVTG0 OUT3A */
365     kDma0RequestMuxEvtg0Out3B       = 38U,         /**< EVTG0 OUT3B */
366     kDma1RequestMuxEvtg0Out3B       = 38U,         /**< EVTG0 OUT3B */
367     kDma0RequestMuxFlexPwm0ReqCapt0 = 39U,         /**< PWM0 capture0 request */
368     kDma1RequestMuxFlexPwm0ReqCapt0 = 39U,         /**< PWM0 capture0 request */
369     kDma0RequestMuxFlexPwm0ReqCapt1 = 40U,         /**< PWM0 capture1 request */
370     kDma1RequestMuxFlexPwm0ReqCapt1 = 40U,         /**< PWM0 capture1 request */
371     kDma0RequestMuxFlexPwm0ReqCapt2 = 41U,         /**< PWM0 capture2 request */
372     kDma1RequestMuxFlexPwm0ReqCapt2 = 41U,         /**< PWM0 capture2 request */
373     kDma0RequestMuxFlexPwm0ReqCapt3 = 42U,         /**< PWM0 capture3 request */
374     kDma1RequestMuxFlexPwm0ReqCapt3 = 42U,         /**< PWM0 capture3 request */
375     kDma0RequestMuxFlexPwm0ReqVal0  = 43U,         /**< PWM0 value0 request */
376     kDma1RequestMuxFlexPwm0ReqVal0  = 43U,         /**< PWM0 value0 request */
377     kDma0RequestMuxFlexPwm0ReqVal1  = 44U,         /**< PWM0 value1 request */
378     kDma1RequestMuxFlexPwm0ReqVal1  = 44U,         /**< PWM0 value1 request */
379     kDma0RequestMuxFlexPwm0ReqVal2  = 45U,         /**< PWM0 value2 request */
380     kDma1RequestMuxFlexPwm0ReqVal2  = 45U,         /**< PWM0 value2 request */
381     kDma0RequestMuxFlexPwm0ReqVal3  = 46U,         /**< PWM0 value3 request */
382     kDma1RequestMuxFlexPwm0ReqVal3  = 46U,         /**< PWM0 value3 request */
383     kDma0RequestMuxLptmr0           = 57U,         /**< LPTMR0 Counter match event */
384     kDma1RequestMuxLptmr0           = 57U,         /**< LPTMR0 Counter match event */
385     kDma0RequestMuxLptmr1           = 58U,         /**< LPTMR1 Counter match event */
386     kDma1RequestMuxLptmr1           = 58U,         /**< LPTMR1 Counter match event */
387     kDma0RequestMuxFlexCan0DmaRequest = 59U,       /**< CAN0 DMA request */
388     kDma1RequestMuxFlexCan0DmaRequest = 59U,       /**< CAN0 DMA request */
389     kDma0RequestMuxFlexIO0ShiftRegister0Request = 61U, /**< FlexIO0 Shifter0 Status DMA request OR Timer0 Status DMA request */
390     kDma1RequestMuxFlexIO0ShiftRegister0Request = 61U, /**< FlexIO0 Shifter0 Status DMA request OR Timer0 Status DMA request */
391     kDma0RequestMuxFlexIO0ShiftRegister1Request = 62U, /**< FlexIO0 Shifter1 Status DMA request OR Timer1 Status DMA request */
392     kDma1RequestMuxFlexIO0ShiftRegister1Request = 62U, /**< FlexIO0 Shifter1 Status DMA request OR Timer1 Status DMA request */
393     kDma0RequestMuxFlexIO0ShiftRegister2Request = 63U, /**< FlexIO0 Shifter2 Status DMA request OR Timer2 Status DMA request */
394     kDma1RequestMuxFlexIO0ShiftRegister2Request = 63U, /**< FlexIO0 Shifter2 Status DMA request OR Timer2 Status DMA request */
395     kDma0RequestMuxFlexIO0ShiftRegister3Request = 64U, /**< FlexIO0 Shifter3 Status DMA request OR Timer3 Status DMA request */
396     kDma1RequestMuxFlexIO0ShiftRegister3Request = 64U, /**< FlexIO0 Shifter3 Status DMA request OR Timer3 Status DMA request */
397     kDma0RequestMuxFlexIO0ShiftRegister4Request = 65U, /**< FlexIO0 Shifter4 Status DMA request OR Timer4 Status DMA request */
398     kDma1RequestMuxFlexIO0ShiftRegister4Request = 65U, /**< FlexIO0 Shifter4 Status DMA request OR Timer4 Status DMA request */
399     kDma0RequestMuxFlexIO0ShiftRegister5Request = 66U, /**< FlexIO0 Shifter5 Status DMA request OR Timer5 Status DMA request */
400     kDma1RequestMuxFlexIO0ShiftRegister5Request = 66U, /**< FlexIO0 Shifter5 Status DMA request OR Timer5 Status DMA request */
401     kDma0RequestMuxFlexIO0ShiftRegister6Request = 67U, /**< FlexIO0 Shifter6 Status DMA request OR Timer6 Status DMA request */
402     kDma1RequestMuxFlexIO0ShiftRegister6Request = 67U, /**< FlexIO0 Shifter6 Status DMA request OR Timer6 Status DMA request */
403     kDma0RequestMuxFlexIO0ShiftRegister7Request = 68U, /**< FlexIO0 Shifter7 Status DMA request OR Timer7 Status DMA request */
404     kDma1RequestMuxFlexIO0ShiftRegister7Request = 68U, /**< FlexIO0 Shifter7 Status DMA request OR Timer7 Status DMA request */
405     kDma0RequestMuxLpFlexcomm0Rx    = 69U,         /**< LP_FLEXCOMM0 Receive request */
406     kDma1RequestMuxLpFlexcomm0Rx    = 69U,         /**< LP_FLEXCOMM0 Receive request */
407     kDma0RequestMuxLpFlexcomm0Tx    = 70U,         /**< LP_FLEXCOMM0 Transmit request */
408     kDma1RequestMuxLpFlexcomm0Tx    = 70U,         /**< LP_FLEXCOMM0 Transmit request */
409     kDma0RequestMuxLpFlexcomm1Rx    = 71U,         /**< LP_FLEXCOMM1 Receive request */
410     kDma1RequestMuxLpFlexcomm1Rx    = 71U,         /**< LP_FLEXCOMM1 Receive request */
411     kDma0RequestMuxLpFlexcomm1Tx    = 72U,         /**< LP_FLEXCOMM1 Transmit request */
412     kDma1RequestMuxLpFlexcomm1Tx    = 72U,         /**< LP_FLEXCOMM1 Transmit request */
413     kDma0RequestMuxLpFlexcomm2Rx    = 73U,         /**< LP_FLEXCOMM2 Receive request */
414     kDma1RequestMuxLpFlexcomm2Rx    = 73U,         /**< LP_FLEXCOMM2 Receive request */
415     kDma0RequestMuxLpFlexcomm2Tx    = 74U,         /**< LP_FLEXCOMM2 Transmit request */
416     kDma1RequestMuxLpFlexcomm2Tx    = 74U,         /**< LP_FLEXCOMM2 Transmit request */
417     kDma0RequestMuxLpFlexcomm3Rx    = 75U,         /**< LP_FLEXCOMM3 Receive request */
418     kDma1RequestMuxLpFlexcomm3Rx    = 75U,         /**< LP_FLEXCOMM3 Receive request */
419     kDma0RequestMuxLpFlexcomm3Tx    = 76U,         /**< LP_FLEXCOMM3 Transmit request */
420     kDma1RequestMuxLpFlexcomm3Tx    = 76U,         /**< LP_FLEXCOMM3 Transmit request */
421     kDma0RequestMuxLpFlexcomm4Rx    = 77U,         /**< LP_FLEXCOMM4 Receive request */
422     kDma1RequestMuxLpFlexcomm4Rx    = 77U,         /**< LP_FLEXCOMM4 Receive request */
423     kDma0RequestMuxLpFlexcomm4Tx    = 78U,         /**< LP_FLEXCOMM4 Transmit request */
424     kDma1RequestMuxLpFlexcomm4Tx    = 78U,         /**< LP_FLEXCOMM4 Transmit request */
425     kDma0RequestMuxLpFlexcomm5Rx    = 79U,         /**< LP_FLEXCOMM5 Receive request */
426     kDma1RequestMuxLpFlexcomm5Rx    = 79U,         /**< LP_FLEXCOMM5 Receive request */
427     kDma0RequestMuxLpFlexcomm5Tx    = 80U,         /**< LP_FLEXCOMM5 Transmit request */
428     kDma1RequestMuxLpFlexcomm5Tx    = 80U,         /**< LP_FLEXCOMM5 Transmit request */
429     kDma0RequestMuxLpFlexcomm6Rx    = 81U,         /**< LP_FLEXCOMM6 Receive request */
430     kDma1RequestMuxLpFlexcomm6Rx    = 81U,         /**< LP_FLEXCOMM6 Receive request */
431     kDma0RequestMuxLpFlexcomm6Tx    = 82U,         /**< LP_FLEXCOMM6 Transmit request */
432     kDma1RequestMuxLpFlexcomm6Tx    = 82U,         /**< LP_FLEXCOMM6 Transmit request */
433     kDma0RequestMuxLpFlexcomm7Rx    = 83U,         /**< LP_FLEXCOMM7 Receive request */
434     kDma1RequestMuxLpFlexcomm7Rx    = 83U,         /**< LP_FLEXCOMM7 Receive request */
435     kDma0RequestMuxLpFlexcomm7Tx    = 84U,         /**< LP_FLEXCOMM7 Transmit request */
436     kDma1RequestMuxLpFlexcomm7Tx    = 84U,         /**< LP_FLEXCOMM7 Transmit request */
437     kDma0RequestMuxLpFlexcomm8Rx    = 85U,         /**< LP_FLEXCOMM8 Receive request */
438     kDma1RequestMuxLpFlexcomm8Rx    = 85U,         /**< LP_FLEXCOMM8 Receive request */
439     kDma0RequestMuxLpFlexcomm8Tx    = 86U,         /**< LP_FLEXCOMM8 Transmit request */
440     kDma1RequestMuxLpFlexcomm8Tx    = 86U,         /**< LP_FLEXCOMM8 Transmit request */
441     kDma0RequestMuxLpFlexcomm9Rx    = 87U,         /**< LP_FLEXCOMM9 Receive request */
442     kDma1RequestMuxLpFlexcomm9Rx    = 87U,         /**< LP_FLEXCOMM9 Receive request */
443     kDma0RequestMuxLpFlexcomm9Tx    = 88U,         /**< LP_FLEXCOMM9 Transmit request */
444     kDma1RequestMuxLpFlexcomm9Tx    = 88U,         /**< LP_FLEXCOMM9 Transmit request */
445     kDma0RequestMuxEmvSim0Rx        = 91U,         /**< EMVSIM0 Receive request */
446     kDma1RequestMuxEmvSim0Rx        = 91U,         /**< EMVSIM0 Receive request */
447     kDma0RequestMuxEmvSim0Tx        = 92U,         /**< EMVSIM0 Transmit request */
448     kDma1RequestMuxEmvSim0Tx        = 92U,         /**< EMVSIM0 Transmit request */
449     kDma0RequestMuxEmvSim1Rx        = 93U,         /**< EMVSIM1 Receive request */
450     kDma1RequestMuxEmvSim1Rx        = 93U,         /**< EMVSIM1 Receive request */
451     kDma0RequestMuxEmvSim1Tx        = 94U,         /**< EMVSIM1 Transmit request */
452     kDma1RequestMuxEmvSim1Tx        = 94U,         /**< EMVSIM1 Transmit request */
453     kDma0RequestMuxI3c0Rx           = 95U,         /**< I3C0 Receive request */
454     kDma1RequestMuxI3c0Rx           = 95U,         /**< I3C0 Receive request */
455     kDma0RequestMuxI3c0Tx           = 96U,         /**< I3C0 Transmit request */
456     kDma1RequestMuxI3c0Tx           = 96U,         /**< I3C0 Transmit request */
457     kDma0RequestMuxI3c1Rx           = 97U,         /**< I3C1 Receive request */
458     kDma1RequestMuxI3c1Rx           = 97U,         /**< I3C1 Receive request */
459     kDma0RequestMuxI3c1Tx           = 98U,         /**< I3C1 Transmit request */
460     kDma1RequestMuxI3c1Tx           = 98U,         /**< I3C1 Transmit request */
461     kDma0RequestMuxSai0Rx           = 99U,         /**< SAI0 Receive request */
462     kDma1RequestMuxSai0Rx           = 99U,         /**< SAI0 Receive request */
463     kDma0RequestMuxSai0Tx           = 100U,        /**< SAI0 Transmit request */
464     kDma1RequestMuxSai0Tx           = 100U,        /**< SAI0 Transmit request */
465     kDma0RequestMuxSai1Rx           = 101U,        /**< SAI1 Receive request */
466     kDma1RequestMuxSai1Rx           = 101U,        /**< SAI1 Receive request */
467     kDma0RequestMuxSai1Tx           = 102U,        /**< SAI1 Transmit request */
468     kDma1RequestMuxSai1Tx           = 102U,        /**< SAI1 Transmit request */
469     kDma0RequestMuxGpio0PinEventRequest0 = 108U,   /**< GPIO0 Pin event request 0 */
470     kDma1RequestMuxGpio0PinEventRequest0 = 108U,   /**< GPIO0 Pin event request 0 */
471     kDma0RequestMuxGpio0PinEventRequest1 = 109U,   /**< GPIO0 Pin event request 1 */
472     kDma1RequestMuxGpio0PinEventRequest1 = 109U,   /**< GPIO0 Pin event request 1 */
473     kDma0RequestMuxGpio1PinEventRequest0 = 110U,   /**< GPIO1 Pin event request 0 */
474     kDma1RequestMuxGpio1PinEventRequest0 = 110U,   /**< GPIO1 Pin event request 0 */
475     kDma0RequestMuxGpio1PinEventRequest1 = 111U,   /**< GPIO1 Pin event request 1 */
476     kDma1RequestMuxGpio1PinEventRequest1 = 111U,   /**< GPIO1 Pin event request 1 */
477     kDma0RequestMuxGpio2PinEventRequest0 = 112U,   /**< GPIO2 Pin event request 0 */
478     kDma1RequestMuxGpio2PinEventRequest0 = 112U,   /**< GPIO2 Pin event request 0 */
479     kDma0RequestMuxGpio2PinEventRequest1 = 113U,   /**< GPIO2 Pin event request 1 */
480     kDma1RequestMuxGpio2PinEventRequest1 = 113U,   /**< GPIO2 Pin event request 1 */
481     kDma0RequestMuxGpio3PinEventRequest0 = 114U,   /**< GPIO3 Pin event request 0 */
482     kDma1RequestMuxGpio3PinEventRequest0 = 114U,   /**< GPIO3 Pin event request 0 */
483     kDma0RequestMuxGpio3PinEventRequest1 = 115U,   /**< GPIO3 Pin event request 1 */
484     kDma1RequestMuxGpio3PinEventRequest1 = 115U,   /**< GPIO3 Pin event request 1 */
485     kDma0RequestMuxGpio4PinEventRequest0 = 116U,   /**< GPIO4 Pin event request 0 */
486     kDma1RequestMuxGpio4PinEventRequest0 = 116U,   /**< GPIO4 Pin event request 0 */
487     kDma0RequestMuxGpio4PinEventRequest1 = 117U,   /**< GPIO4 Pin event request 1 */
488     kDma1RequestMuxGpio4PinEventRequest1 = 117U,   /**< GPIO4 Pin event request 1 */
489     kDma0RequestMuxGpio5PinEventRequest0 = 118U,   /**< GPIO5 Pin event request 0 */
490     kDma1RequestMuxGpio5PinEventRequest0 = 118U,   /**< GPIO5 Pin event request 0 */
491     kDma0RequestMuxGpio5PinEventRequest1 = 119U,   /**< GPIO5 Pin event request 1 */
492     kDma1RequestMuxGpio5PinEventRequest1 = 119U,   /**< GPIO5 Pin event request 1 */
493     kDma0RequestMuxTsi0EndOfScan    = 120U,        /**< TSI0 End of Scan */
494     kDma1RequestMuxTsi0EndOfScan    = 120U,        /**< TSI0 End of Scan */
495     kDma0RequestMuxTsi0OutOfRange   = 121U,        /**< TSI0 Out of Range */
496     kDma1RequestMuxTsi0OutOfRange   = 121U,        /**< TSI0 Out of Range */
497 } dma_request_source_t;
498 
499 /* @} */
500 
501 /*!
502  * @addtogroup eim_memory_channel
503  * @{
504  */
505 
506 /*******************************************************************************
507  * Definitions
508  ******************************************************************************/
509 
510 /*!
511  * @brief Structure for the eim_memory_channel
512  *
513  * Defines the structure for the EIM resource collections.
514  */
515 
516 typedef enum _eim_memory_channel
517 {
518     kEIM_MemoryChannelRAMX          = 0U,          /**< Memory RAMX */
519     kEIM_MemoryChannelRAMA          = 1U,          /**< Memory RAMA  */
520     kEIM_MemoryChannelRAMB          = 2U,          /**< Memory RAMB */
521     kEIM_MemoryChannelRAMC          = 3U,          /**< Memory RAMC */
522     kEIM_MemoryChannelRAMD          = 4U,          /**< Memory RAMD */
523     kEIM_MemoryChannelRAME          = 5U,          /**< Memory RAME */
524     kEIM_MemoryChannelRAMF          = 6U,          /**< Memory RAMF */
525     kEIM_MemoryChannelLPCACRAM      = 7U,          /**< Memory LPCACRAM */
526     kEIM_MemoryChannelPKCRAM        = 8U,          /**< Memory PKCRAM */
527 } eim_memory_channel_t;
528 
529 /* @} */
530 
531 /*!
532  * @addtogroup eim_error_injection_channel_enable
533  * @{
534  */
535 
536 /*******************************************************************************
537  * Definitions
538  ******************************************************************************/
539 
540 /*!
541  * @brief Structure for the eim_error_injection_channel_enable
542  *
543  * Defines the structure for the EIM error injection resource collections.
544  */
545 
546 typedef enum _eim_error_injection_channel_enable
547 {
548     kEIM_MemoryChannelRAMXEnable    = 0x80000000U, /**< Memory channel 0(RAMX) error injection enable */
549     kEIM_MemoryChannelRAMAEnable    = 0x40000000U, /**< Memory channel 1(RAMA) error injection enable  */
550     kEIM_MemoryChannelRAMBEnable    = 0x20000000U, /**< Memory channel 2(RAMB) error injection enable */
551     kEIM_MemoryChannelRAMCEnable    = 0x10000000U, /**< Memory channel 3(RAMC) error injection enable */
552     kEIM_MemoryChannelRAMDEnable    = 0x8000000U,  /**< Memory channel 4(RAMD) error injection enable */
553     kEIM_MemoryChannelRAMEEnable    = 0x4000000U,  /**< Memory channel 5(RAME) error injection enable */
554     kEIM_MemoryChannelRAMFEnable    = 0x2000000U,  /**< Memory channel 6(RAMF) error injection enable */
555     kEIM_MemoryChannelLPCACRAMEnable = 0x1000000U, /**< Memory channel 7(LPCACRAM) error injection enable */
556     kEIM_MemoryChannelPKCRAMEnable  = 0x800000U,   /**< Memory channel 8(PKCRAM) error injection enable */
557 } eim_error_injection_channel_enable_t;
558 
559 /* @} */
560 
561 /*!
562  * @addtogroup erm_memory_channel
563  * @{
564  */
565 
566 /*******************************************************************************
567  * Definitions
568  ******************************************************************************/
569 
570 /*!
571  * @brief Structure for the erm_memory_channel
572  *
573  * Defines the structure for the ERM resource collections.
574  */
575 
576 typedef enum _erm_memory_channel
577 {
578     kERM_MemoryChannelRAMX          = 0U,          /**< Memory RAMX */
579     kERM_MemoryChannelRAMA          = 1U,          /**< Memory RAMA  */
580     kERM_MemoryChannelRAMB          = 2U,          /**< Memory RAMB */
581     kERM_MemoryChannelRAMC          = 3U,          /**< Memory RAMC */
582     kERM_MemoryChannelRAMD          = 4U,          /**< Memory RAMD */
583     kERM_MemoryChannelRAME          = 5U,          /**< Memory RAME */
584     kERM_MemoryChannelRAMF          = 6U,          /**< Memory RAMF */
585     kERM_MemoryChannelLPCACRAM      = 7U,          /**< Memory LPCACRAM */
586     kERM_MemoryChannelPKCRAM        = 8U,          /**< Memory PKCRAM */
587     kERM_MemoryChannelFLASH         = 9U,          /**< Memory FLASH */
588 } erm_memory_channel_t;
589 
590 /* @} */
591 
592 
593 /*!
594  * @}
595  */ /* end of group Mapping_Information */
596 
597 
598 /* ----------------------------------------------------------------------------
599    -- Device Peripheral Access Layer
600    ---------------------------------------------------------------------------- */
601 
602 /*!
603  * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
604  * @{
605  */
606 
607 
608 /*
609 ** Start of section using anonymous unions
610 */
611 
612 #if defined(__ARMCC_VERSION)
613   #if (__ARMCC_VERSION >= 6010050)
614     #pragma clang diagnostic push
615   #else
616     #pragma push
617     #pragma anon_unions
618   #endif
619 #elif defined(__GNUC__)
620   /* anonymous unions are enabled by default */
621 #elif defined(__IAR_SYSTEMS_ICC__)
622   #pragma language=extended
623 #else
624   #error Not supported compiler type
625 #endif
626 
627 /* ----------------------------------------------------------------------------
628    -- ADC Peripheral Access Layer
629    ---------------------------------------------------------------------------- */
630 
631 /*!
632  * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
633  * @{
634  */
635 
636 /** ADC - Register Layout Typedef */
637 typedef struct {
638   __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
639   __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
640        uint8_t RESERVED_0[8];
641   __IO uint32_t CTRL;                              /**< Control Register, offset: 0x10 */
642   __IO uint32_t STAT;                              /**< Status Register, offset: 0x14 */
643   __IO uint32_t IE;                                /**< Interrupt Enable Register, offset: 0x18 */
644   __IO uint32_t DE;                                /**< DMA Enable Register, offset: 0x1C */
645   __IO uint32_t CFG;                               /**< Configuration Register, offset: 0x20 */
646   __IO uint32_t PAUSE;                             /**< Pause Register, offset: 0x24 */
647        uint8_t RESERVED_1[12];
648   __O  uint32_t SWTRIG;                            /**< Software Trigger Register, offset: 0x34 */
649   __IO uint32_t TSTAT;                             /**< Trigger Status Register, offset: 0x38 */
650        uint8_t RESERVED_2[4];
651   __IO uint32_t OFSTRIM;                           /**< Offset Trim Register, offset: 0x40 */
652        uint8_t RESERVED_3[92];
653   __IO uint32_t TCTRL[4];                          /**< Trigger Control Register, array offset: 0xA0, array step: 0x4 */
654        uint8_t RESERVED_4[48];
655   __IO uint32_t FCTRL[2];                          /**< FIFO Control Register, array offset: 0xE0, array step: 0x4 */
656        uint8_t RESERVED_5[8];
657   __I  uint32_t GCC[2];                            /**< Gain Calibration Control, array offset: 0xF0, array step: 0x4 */
658   __IO uint32_t GCR[2];                            /**< Gain Calculation Result, array offset: 0xF8, array step: 0x4 */
659   struct {                                         /* offset: 0x100, array step: 0x8 */
660     __IO uint32_t CMDL;                              /**< Command Low Buffer Register, array offset: 0x100, array step: 0x8 */
661     __IO uint32_t CMDH;                              /**< Command High Buffer Register, array offset: 0x104, array step: 0x8 */
662   } CMD[15];
663        uint8_t RESERVED_6[136];
664   __IO uint32_t CV[15];                            /**< Compare Value Register, array offset: 0x200, array step: 0x4 */
665        uint8_t RESERVED_7[196];
666   __I  uint32_t RESFIFO[2];                        /**< Data Result FIFO Register, array offset: 0x300, array step: 0x4 */
667        uint8_t RESERVED_8[248];
668   __IO uint32_t CAL_GAR[33];                       /**< Calibration General A-Side Registers, array offset: 0x400, array step: 0x4 */
669        uint8_t RESERVED_9[124];
670   __IO uint32_t CAL_GBR[33];                       /**< Calibration General B-Side Registers, array offset: 0x500, array step: 0x4 */
671 } ADC_Type;
672 
673 /* ----------------------------------------------------------------------------
674    -- ADC Register Masks
675    ---------------------------------------------------------------------------- */
676 
677 /*!
678  * @addtogroup ADC_Register_Masks ADC Register Masks
679  * @{
680  */
681 
682 /*! @name VERID - Version ID Register */
683 /*! @{ */
684 
685 #define ADC_VERID_RES_MASK                       (0x1U)
686 #define ADC_VERID_RES_SHIFT                      (0U)
687 /*! RES - Resolution
688  *  0b0..Up to 13-bit differential or 12-bit single-ended resolution supported.
689  *  0b1..Up to 16-bit differential or 16-bit single-ended resolution supported. CMDLn[MODE] available for
690  *       selecting the resolution of conversions for the associated command.
691  */
692 #define ADC_VERID_RES(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_VERID_RES_SHIFT)) & ADC_VERID_RES_MASK)
693 
694 #define ADC_VERID_DIFFEN_MASK                    (0x2U)
695 #define ADC_VERID_DIFFEN_SHIFT                   (1U)
696 /*! DIFFEN - Differential Supported
697  *  0b0..Not supported
698  *  0b1..Supported. CMDLn[CTYPE] controls fields implemented.
699  */
700 #define ADC_VERID_DIFFEN(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_VERID_DIFFEN_SHIFT)) & ADC_VERID_DIFFEN_MASK)
701 
702 #define ADC_VERID_MVI_MASK                       (0x8U)
703 #define ADC_VERID_MVI_SHIFT                      (3U)
704 /*! MVI - Multiple Vref Implemented
705  *  0b0..Single VREFH input supported.
706  *  0b1..Multiple VREFH inputs supported.
707  */
708 #define ADC_VERID_MVI(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MVI_SHIFT)) & ADC_VERID_MVI_MASK)
709 
710 #define ADC_VERID_CSW_MASK                       (0x70U)
711 #define ADC_VERID_CSW_SHIFT                      (4U)
712 /*! CSW - Channel Scale Width
713  *  0b000..Not supported.
714  *  0b001..Supported with one-bit CSCALE control field.
715  *  0b110..Supported with six-bit CSCALE control field.
716  */
717 #define ADC_VERID_CSW(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CSW_SHIFT)) & ADC_VERID_CSW_MASK)
718 
719 #define ADC_VERID_VR1RNGI_MASK                   (0x100U)
720 #define ADC_VERID_VR1RNGI_SHIFT                  (8U)
721 /*! VR1RNGI - Voltage Reference 1 Range Control Bit Implemented
722  *  0b0..Range control not required.
723  *  0b1..Range control required.
724  */
725 #define ADC_VERID_VR1RNGI(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_VERID_VR1RNGI_SHIFT)) & ADC_VERID_VR1RNGI_MASK)
726 
727 #define ADC_VERID_IADCKI_MASK                    (0x200U)
728 #define ADC_VERID_IADCKI_SHIFT                   (9U)
729 /*! IADCKI - Internal ADC Clock Implemented
730  *  0b0..Not implemented
731  *  0b1..Implemented
732  */
733 #define ADC_VERID_IADCKI(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_VERID_IADCKI_SHIFT)) & ADC_VERID_IADCKI_MASK)
734 
735 #define ADC_VERID_CALOFSI_MASK                   (0x400U)
736 #define ADC_VERID_CALOFSI_SHIFT                  (10U)
737 /*! CALOFSI - Calibration Function Implemented
738  *  0b0..Not implemented
739  *  0b1..Implemented
740  */
741 #define ADC_VERID_CALOFSI(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CALOFSI_SHIFT)) & ADC_VERID_CALOFSI_MASK)
742 
743 #define ADC_VERID_NUM_SEC_MASK                   (0x800U)
744 #define ADC_VERID_NUM_SEC_SHIFT                  (11U)
745 /*! NUM_SEC - Number of Single-Ended Outputs Supported
746  *  0b0..One
747  *  0b1..Two
748  */
749 #define ADC_VERID_NUM_SEC(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_SEC_SHIFT)) & ADC_VERID_NUM_SEC_MASK)
750 
751 #define ADC_VERID_NUM_FIFO_MASK                  (0x7000U)
752 #define ADC_VERID_NUM_FIFO_SHIFT                 (12U)
753 /*! NUM_FIFO - Number of FIFOs
754  *  0b000..N/A
755  *  0b001..One
756  *  0b010..Two
757  *  0b011..Three
758  *  0b100..Four
759  */
760 #define ADC_VERID_NUM_FIFO(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_FIFO_SHIFT)) & ADC_VERID_NUM_FIFO_MASK)
761 
762 #define ADC_VERID_MINOR_MASK                     (0xFF0000U)
763 #define ADC_VERID_MINOR_SHIFT                    (16U)
764 /*! MINOR - Minor Version Number */
765 #define ADC_VERID_MINOR(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MINOR_SHIFT)) & ADC_VERID_MINOR_MASK)
766 
767 #define ADC_VERID_MAJOR_MASK                     (0xFF000000U)
768 #define ADC_VERID_MAJOR_SHIFT                    (24U)
769 /*! MAJOR - Major Version Number */
770 #define ADC_VERID_MAJOR(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MAJOR_SHIFT)) & ADC_VERID_MAJOR_MASK)
771 /*! @} */
772 
773 /*! @name PARAM - Parameter Register */
774 /*! @{ */
775 
776 #define ADC_PARAM_TRIG_NUM_MASK                  (0xFFU)
777 #define ADC_PARAM_TRIG_NUM_SHIFT                 (0U)
778 /*! TRIG_NUM - Trigger Number */
779 #define ADC_PARAM_TRIG_NUM(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_TRIG_NUM_SHIFT)) & ADC_PARAM_TRIG_NUM_MASK)
780 
781 #define ADC_PARAM_FIFOSIZE_MASK                  (0xFF00U)
782 #define ADC_PARAM_FIFOSIZE_SHIFT                 (8U)
783 /*! FIFOSIZE - Result FIFO Depth
784  *  0b00000001..2
785  *  0b00000100..4
786  *  0b00001000..8
787  *  0b00010000..16
788  *  0b00100000..32
789  *  0b01000000..64
790  */
791 #define ADC_PARAM_FIFOSIZE(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_FIFOSIZE_SHIFT)) & ADC_PARAM_FIFOSIZE_MASK)
792 
793 #define ADC_PARAM_CV_NUM_MASK                    (0xFF0000U)
794 #define ADC_PARAM_CV_NUM_SHIFT                   (16U)
795 /*! CV_NUM - Compare Value Number */
796 #define ADC_PARAM_CV_NUM(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CV_NUM_SHIFT)) & ADC_PARAM_CV_NUM_MASK)
797 
798 #define ADC_PARAM_CMD_NUM_MASK                   (0xFF000000U)
799 #define ADC_PARAM_CMD_NUM_SHIFT                  (24U)
800 /*! CMD_NUM - Command Buffer Number */
801 #define ADC_PARAM_CMD_NUM(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CMD_NUM_SHIFT)) & ADC_PARAM_CMD_NUM_MASK)
802 /*! @} */
803 
804 /*! @name CTRL - Control Register */
805 /*! @{ */
806 
807 #define ADC_CTRL_ADCEN_MASK                      (0x1U)
808 #define ADC_CTRL_ADCEN_SHIFT                     (0U)
809 /*! ADCEN - ADC Enable
810  *  0b0..Disabled
811  *  0b1..Enabled
812  */
813 #define ADC_CTRL_ADCEN(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ADCEN_SHIFT)) & ADC_CTRL_ADCEN_MASK)
814 
815 #define ADC_CTRL_RST_MASK                        (0x2U)
816 #define ADC_CTRL_RST_SHIFT                       (1U)
817 /*! RST - Software Reset
818  *  0b0..ADC logic is not reset.
819  *  0b1..ADC logic is reset.
820  */
821 #define ADC_CTRL_RST(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RST_SHIFT)) & ADC_CTRL_RST_MASK)
822 
823 #define ADC_CTRL_DOZEN_MASK                      (0x4U)
824 #define ADC_CTRL_DOZEN_SHIFT                     (2U)
825 /*! DOZEN - Doze Enable
826  *  0b0..ADC is enabled in low-power mode.
827  *  0b1..ADC is disabled in low-power mode.
828  */
829 #define ADC_CTRL_DOZEN(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_DOZEN_SHIFT)) & ADC_CTRL_DOZEN_MASK)
830 
831 #define ADC_CTRL_CAL_REQ_MASK                    (0x8U)
832 #define ADC_CTRL_CAL_REQ_SHIFT                   (3U)
833 /*! CAL_REQ - Auto-Calibration Request
834  *  0b0..No request made.
835  *  0b1..Request has been made.
836  */
837 #define ADC_CTRL_CAL_REQ(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CAL_REQ_SHIFT)) & ADC_CTRL_CAL_REQ_MASK)
838 
839 #define ADC_CTRL_CALOFS_MASK                     (0x10U)
840 #define ADC_CTRL_CALOFS_SHIFT                    (4U)
841 /*! CALOFS - Offset Calibration Request
842  *  0b0..Calibration function disabled
843  *  0b1..Request for offset calibration function
844  */
845 #define ADC_CTRL_CALOFS(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CALOFS_SHIFT)) & ADC_CTRL_CALOFS_MASK)
846 
847 #define ADC_CTRL_RSTFIFO0_MASK                   (0x100U)
848 #define ADC_CTRL_RSTFIFO0_SHIFT                  (8U)
849 /*! RSTFIFO0 - Reset FIFO 0
850  *  0b0..No effect.
851  *  0b1..FIFO 0 is reset.
852  */
853 #define ADC_CTRL_RSTFIFO0(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO0_SHIFT)) & ADC_CTRL_RSTFIFO0_MASK)
854 
855 #define ADC_CTRL_RSTFIFO1_MASK                   (0x200U)
856 #define ADC_CTRL_RSTFIFO1_SHIFT                  (9U)
857 /*! RSTFIFO1 - Reset FIFO 1
858  *  0b0..No effect.
859  *  0b1..FIFO 1 is reset.
860  */
861 #define ADC_CTRL_RSTFIFO1(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO1_SHIFT)) & ADC_CTRL_RSTFIFO1_MASK)
862 
863 #define ADC_CTRL_CAL_AVGS_MASK                   (0xF0000U)
864 #define ADC_CTRL_CAL_AVGS_SHIFT                  (16U)
865 /*! CAL_AVGS - Auto-Calibration Averages
866  *  0b0000..Single conversion.
867  *  0b0001..2 conversions averaged.
868  *  0b0010..4 conversions averaged.
869  *  0b0011..8 conversions averaged.
870  *  0b0100..16 conversions averaged.
871  *  0b0101..32 conversions averaged.
872  *  0b0110..64 conversions averaged.
873  *  0b0111..128 conversions averaged.
874  *  0b1000..256 conversions averaged.
875  *  0b1001..512 conversions averaged.
876  *  0b1010..1024 conversions averaged.
877  */
878 #define ADC_CTRL_CAL_AVGS(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CAL_AVGS_SHIFT)) & ADC_CTRL_CAL_AVGS_MASK)
879 /*! @} */
880 
881 /*! @name STAT - Status Register */
882 /*! @{ */
883 
884 #define ADC_STAT_RDY0_MASK                       (0x1U)
885 #define ADC_STAT_RDY0_SHIFT                      (0U)
886 /*! RDY0 - Result FIFO 0 Ready Flag
887  *  0b0..Not above watermark
888  *  0b1..Above watermark
889  */
890 #define ADC_STAT_RDY0(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY0_SHIFT)) & ADC_STAT_RDY0_MASK)
891 
892 #define ADC_STAT_FOF0_MASK                       (0x2U)
893 #define ADC_STAT_FOF0_SHIFT                      (1U)
894 /*! FOF0 - Result FIFO 0 Overflow Flag
895  *  0b0..No result FIFO 0 overflow has occurred since the last time that the flag was cleared.
896  *  0b1..At least one result FIFO 0 overflow has occurred since the last time that the flag was cleared.
897  */
898 #define ADC_STAT_FOF0(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF0_SHIFT)) & ADC_STAT_FOF0_MASK)
899 
900 #define ADC_STAT_RDY1_MASK                       (0x4U)
901 #define ADC_STAT_RDY1_SHIFT                      (2U)
902 /*! RDY1 - Result FIFO1 Ready Flag
903  *  0b0..Not above watermark
904  *  0b1..Above watermark
905  */
906 #define ADC_STAT_RDY1(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY1_SHIFT)) & ADC_STAT_RDY1_MASK)
907 
908 #define ADC_STAT_FOF1_MASK                       (0x8U)
909 #define ADC_STAT_FOF1_SHIFT                      (3U)
910 /*! FOF1 - Result FIFO1 Overflow Flag
911  *  0b0..No result FIFO1 overflow has occurred since the last time that the flag was cleared.
912  *  0b1..At least one result FIFO1 overflow has occurred since the last time that the flag was cleared.
913  */
914 #define ADC_STAT_FOF1(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF1_SHIFT)) & ADC_STAT_FOF1_MASK)
915 
916 #define ADC_STAT_TEXC_INT_MASK                   (0x100U)
917 #define ADC_STAT_TEXC_INT_SHIFT                  (8U)
918 /*! TEXC_INT - Interrupt Flag For High-Priority Trigger Exception
919  *  0b0..No trigger exceptions have occurred.
920  *  0b1..A trigger exception has occurred and is pending acknowledgment.
921  */
922 #define ADC_STAT_TEXC_INT(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TEXC_INT_SHIFT)) & ADC_STAT_TEXC_INT_MASK)
923 
924 #define ADC_STAT_TCOMP_INT_MASK                  (0x200U)
925 #define ADC_STAT_TCOMP_INT_SHIFT                 (9U)
926 /*! TCOMP_INT - Interrupt Flag For Trigger Completion
927  *  0b0..Either IE[TCOMP_IE] = 0, or no trigger sequences have run to completion.
928  *  0b1..Trigger sequence has been completed and all data is stored in the associated FIFO.
929  */
930 #define ADC_STAT_TCOMP_INT(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TCOMP_INT_SHIFT)) & ADC_STAT_TCOMP_INT_MASK)
931 
932 #define ADC_STAT_CAL_RDY_MASK                    (0x400U)
933 #define ADC_STAT_CAL_RDY_SHIFT                   (10U)
934 /*! CAL_RDY - Calibration Ready
935  *  0b0..Calibration is incomplete or has not been run.
936  *  0b1..ADC is calibrated.
937  */
938 #define ADC_STAT_CAL_RDY(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CAL_RDY_SHIFT)) & ADC_STAT_CAL_RDY_MASK)
939 
940 #define ADC_STAT_ADC_ACTIVE_MASK                 (0x800U)
941 #define ADC_STAT_ADC_ACTIVE_SHIFT                (11U)
942 /*! ADC_ACTIVE - ADC Active
943  *  0b0..ADC is idle. There are no pending triggers to service and no active commands are being processed.
944  *  0b1..ADC is processing a conversion, running through the power-up delay, or servicing a trigger.
945  */
946 #define ADC_STAT_ADC_ACTIVE(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_STAT_ADC_ACTIVE_SHIFT)) & ADC_STAT_ADC_ACTIVE_MASK)
947 
948 #define ADC_STAT_TRGACT_MASK                     (0x30000U)
949 #define ADC_STAT_TRGACT_SHIFT                    (16U)
950 /*! TRGACT - Trigger Active
951  *  0b00..Command (sequence) associated with Trigger 0 currently being executed.
952  *  0b01..Command (sequence) associated with Trigger 1 currently being executed.
953  *  0b10..Command (sequence) associated with Trigger 2 currently being executed.
954  *  0b11..Command (sequence) associated with Trigger 3 currently being executed.
955  */
956 #define ADC_STAT_TRGACT(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TRGACT_SHIFT)) & ADC_STAT_TRGACT_MASK)
957 
958 #define ADC_STAT_CMDACT_MASK                     (0xF000000U)
959 #define ADC_STAT_CMDACT_SHIFT                    (24U)
960 /*! CMDACT - Command Active
961  *  0b0000..No command currently in progress.
962  *  0b0001..Command 1 currently being executed.
963  *  0b0010..Command 2 currently being executed.
964  *  0b0011-0b1111..Associated command number currently being executed.
965  */
966 #define ADC_STAT_CMDACT(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CMDACT_SHIFT)) & ADC_STAT_CMDACT_MASK)
967 /*! @} */
968 
969 /*! @name IE - Interrupt Enable Register */
970 /*! @{ */
971 
972 #define ADC_IE_FWMIE0_MASK                       (0x1U)
973 #define ADC_IE_FWMIE0_SHIFT                      (0U)
974 /*! FWMIE0 - FIFO 0 Watermark Interrupt Enable
975  *  0b0..Disabled
976  *  0b1..Enabled
977  */
978 #define ADC_IE_FWMIE0(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE0_SHIFT)) & ADC_IE_FWMIE0_MASK)
979 
980 #define ADC_IE_FOFIE0_MASK                       (0x2U)
981 #define ADC_IE_FOFIE0_SHIFT                      (1U)
982 /*! FOFIE0 - Result FIFO 0 Overflow Interrupt Enable
983  *  0b0..Disabled
984  *  0b1..Enabled
985  */
986 #define ADC_IE_FOFIE0(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE0_SHIFT)) & ADC_IE_FOFIE0_MASK)
987 
988 #define ADC_IE_FWMIE1_MASK                       (0x4U)
989 #define ADC_IE_FWMIE1_SHIFT                      (2U)
990 /*! FWMIE1 - FIFO1 Watermark Interrupt Enable
991  *  0b0..Disabled
992  *  0b1..Enabled
993  */
994 #define ADC_IE_FWMIE1(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE1_SHIFT)) & ADC_IE_FWMIE1_MASK)
995 
996 #define ADC_IE_FOFIE1_MASK                       (0x8U)
997 #define ADC_IE_FOFIE1_SHIFT                      (3U)
998 /*! FOFIE1 - Result FIFO1 Overflow Interrupt Enable
999  *  0b0..Disabled
1000  *  0b1..Enabled
1001  */
1002 #define ADC_IE_FOFIE1(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE1_SHIFT)) & ADC_IE_FOFIE1_MASK)
1003 
1004 #define ADC_IE_TEXC_IE_MASK                      (0x100U)
1005 #define ADC_IE_TEXC_IE_SHIFT                     (8U)
1006 /*! TEXC_IE - Trigger Exception Interrupt Enable
1007  *  0b0..Disabled
1008  *  0b1..Enabled
1009  */
1010 #define ADC_IE_TEXC_IE(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_IE_TEXC_IE_SHIFT)) & ADC_IE_TEXC_IE_MASK)
1011 
1012 #define ADC_IE_TCOMP_IE_MASK                     (0xF0000U)
1013 #define ADC_IE_TCOMP_IE_SHIFT                    (16U)
1014 /*! TCOMP_IE - Trigger Completion Interrupt Enable
1015  *  0b0000..All disabled
1016  *  0b0001..Trigger completion interrupts are enabled for trigger source 0 only.
1017  *  0b0010..Trigger completion interrupts are enabled for trigger source 1 only.
1018  *  0b0011-0b1110..Associated trigger completion interrupts are enabled.
1019  *  0b1111..All enabled
1020  */
1021 #define ADC_IE_TCOMP_IE(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_IE_TCOMP_IE_SHIFT)) & ADC_IE_TCOMP_IE_MASK)
1022 /*! @} */
1023 
1024 /*! @name DE - DMA Enable Register */
1025 /*! @{ */
1026 
1027 #define ADC_DE_FWMDE0_MASK                       (0x1U)
1028 #define ADC_DE_FWMDE0_SHIFT                      (0U)
1029 /*! FWMDE0 - FIFO 0 Watermark DMA Enable
1030  *  0b0..Disabled
1031  *  0b1..Enabled
1032  */
1033 #define ADC_DE_FWMDE0(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE0_SHIFT)) & ADC_DE_FWMDE0_MASK)
1034 
1035 #define ADC_DE_FWMDE1_MASK                       (0x2U)
1036 #define ADC_DE_FWMDE1_SHIFT                      (1U)
1037 /*! FWMDE1 - FIFO1 Watermark DMA Enable
1038  *  0b0..Disabled
1039  *  0b1..Enabled
1040  */
1041 #define ADC_DE_FWMDE1(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE1_SHIFT)) & ADC_DE_FWMDE1_MASK)
1042 /*! @} */
1043 
1044 /*! @name CFG - Configuration Register */
1045 /*! @{ */
1046 
1047 #define ADC_CFG_TPRICTRL_MASK                    (0x3U)
1048 #define ADC_CFG_TPRICTRL_SHIFT                   (0U)
1049 /*! TPRICTRL - ADC Trigger Priority Control
1050  *  0b00..Current conversion is aborted and the new command specified by the trigger is started.
1051  *  0b01..Current command is stopped after completing the current conversion. If averaging is enabled, the
1052  *        averaging loop is completed. CMDHn[LOOP] is ignored and the higher-priority trigger is serviced.
1053  *  0b10..Current command is completed (averaging, looping, compare) before servicing the higher-priority trigger.
1054  *  0b11..
1055  */
1056 #define ADC_CFG_TPRICTRL(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TPRICTRL_SHIFT)) & ADC_CFG_TPRICTRL_MASK)
1057 
1058 #define ADC_CFG_PWRSEL_MASK                      (0x30U)
1059 #define ADC_CFG_PWRSEL_SHIFT                     (4U)
1060 /*! PWRSEL - Power Configuration Select
1061  *  0b0x..Low power
1062  *  0b1x..High power
1063  */
1064 #define ADC_CFG_PWRSEL(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWRSEL_SHIFT)) & ADC_CFG_PWRSEL_MASK)
1065 
1066 #define ADC_CFG_REFSEL_MASK                      (0xC0U)
1067 #define ADC_CFG_REFSEL_SHIFT                     (6U)
1068 /*! REFSEL - Voltage Reference Selection
1069  *  0b00..Option 1
1070  *  0b01..Option 2
1071  *  0b10..Option 3
1072  *  0b11..
1073  */
1074 #define ADC_CFG_REFSEL(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK)
1075 
1076 #define ADC_CFG_TRES_MASK                        (0x100U)
1077 #define ADC_CFG_TRES_SHIFT                       (8U)
1078 /*! TRES - Trigger Resume Enable
1079  *  0b0..Not automatically resumed or restarted
1080  *  0b1..Automatically resumed or restarted
1081  */
1082 #define ADC_CFG_TRES(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TRES_SHIFT)) & ADC_CFG_TRES_MASK)
1083 
1084 #define ADC_CFG_TCMDRES_MASK                     (0x200U)
1085 #define ADC_CFG_TCMDRES_SHIFT                    (9U)
1086 /*! TCMDRES - Trigger Command Resume
1087  *  0b0..Trigger sequence automatically restarted.
1088  *  0b1..Trigger sequence resumed from the command that was executed prior to the exception.
1089  */
1090 #define ADC_CFG_TCMDRES(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TCMDRES_SHIFT)) & ADC_CFG_TCMDRES_MASK)
1091 
1092 #define ADC_CFG_HPT_EXDI_MASK                    (0x400U)
1093 #define ADC_CFG_HPT_EXDI_SHIFT                   (10U)
1094 /*! HPT_EXDI - High-Priority Trigger Exception Disable
1095  *  0b0..Enabled
1096  *  0b1..Disabled
1097  */
1098 #define ADC_CFG_HPT_EXDI(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_CFG_HPT_EXDI_SHIFT)) & ADC_CFG_HPT_EXDI_MASK)
1099 
1100 #define ADC_CFG_PUDLY_MASK                       (0xFF0000U)
1101 #define ADC_CFG_PUDLY_SHIFT                      (16U)
1102 /*! PUDLY - Power-up Delay */
1103 #define ADC_CFG_PUDLY(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PUDLY_SHIFT)) & ADC_CFG_PUDLY_MASK)
1104 
1105 #define ADC_CFG_PWREN_MASK                       (0x10000000U)
1106 #define ADC_CFG_PWREN_SHIFT                      (28U)
1107 /*! PWREN - ADC Analog Pre-Enable
1108  *  0b0..ADC analog circuits are only enabled while conversions are active. Analog startup delays affect performance.
1109  *  0b1..ADC analog circuits are pre-enabled and ready to execute conversions without startup delays, at the cost
1110  *       of higher DC current consumption. A single power-up delay (CFG[PUDLY]) is executed immediately once PWREN
1111  *       is set. No detected triggers begin ADC operation until the power-up delay time has passed. After this
1112  *       initial delay expires, the analog circuits remain pre-enabled, and no additional delays are executed.
1113  */
1114 #define ADC_CFG_PWREN(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWREN_SHIFT)) & ADC_CFG_PWREN_MASK)
1115 /*! @} */
1116 
1117 /*! @name PAUSE - Pause Register */
1118 /*! @{ */
1119 
1120 #define ADC_PAUSE_PAUSEDLY_MASK                  (0x1FFU)
1121 #define ADC_PAUSE_PAUSEDLY_SHIFT                 (0U)
1122 /*! PAUSEDLY - Pause Delay */
1123 #define ADC_PAUSE_PAUSEDLY(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEDLY_SHIFT)) & ADC_PAUSE_PAUSEDLY_MASK)
1124 
1125 #define ADC_PAUSE_PAUSEEN_MASK                   (0x80000000U)
1126 #define ADC_PAUSE_PAUSEEN_SHIFT                  (31U)
1127 /*! PAUSEEN - Pause Enable
1128  *  0b0..Disabled
1129  *  0b1..Enabled
1130  */
1131 #define ADC_PAUSE_PAUSEEN(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEEN_SHIFT)) & ADC_PAUSE_PAUSEEN_MASK)
1132 /*! @} */
1133 
1134 /*! @name SWTRIG - Software Trigger Register */
1135 /*! @{ */
1136 
1137 #define ADC_SWTRIG_SWT0_MASK                     (0x1U)
1138 #define ADC_SWTRIG_SWT0_SHIFT                    (0U)
1139 /*! SWT0 - Software Trigger 0
1140  *  0b0..No trigger 0 event generated.
1141  *  0b1..Trigger 0 event generated.
1142  */
1143 #define ADC_SWTRIG_SWT0(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT0_SHIFT)) & ADC_SWTRIG_SWT0_MASK)
1144 
1145 #define ADC_SWTRIG_SWT1_MASK                     (0x2U)
1146 #define ADC_SWTRIG_SWT1_SHIFT                    (1U)
1147 /*! SWT1 - Software Trigger 1
1148  *  0b0..No trigger 1 event generated.
1149  *  0b1..Trigger 1 event generated.
1150  */
1151 #define ADC_SWTRIG_SWT1(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT1_SHIFT)) & ADC_SWTRIG_SWT1_MASK)
1152 
1153 #define ADC_SWTRIG_SWT2_MASK                     (0x4U)
1154 #define ADC_SWTRIG_SWT2_SHIFT                    (2U)
1155 /*! SWT2 - Software Trigger 2
1156  *  0b0..No trigger 2 event generated.
1157  *  0b1..Trigger 2 event generated.
1158  */
1159 #define ADC_SWTRIG_SWT2(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT2_SHIFT)) & ADC_SWTRIG_SWT2_MASK)
1160 
1161 #define ADC_SWTRIG_SWT3_MASK                     (0x8U)
1162 #define ADC_SWTRIG_SWT3_SHIFT                    (3U)
1163 /*! SWT3 - Software Trigger 3
1164  *  0b0..No trigger 3 event generated.
1165  *  0b1..Trigger 3 event generated.
1166  */
1167 #define ADC_SWTRIG_SWT3(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT3_SHIFT)) & ADC_SWTRIG_SWT3_MASK)
1168 /*! @} */
1169 
1170 /*! @name TSTAT - Trigger Status Register */
1171 /*! @{ */
1172 
1173 #define ADC_TSTAT_TEXC_NUM_MASK                  (0xFU)
1174 #define ADC_TSTAT_TEXC_NUM_SHIFT                 (0U)
1175 /*! TEXC_NUM - Trigger Exception Number
1176  *  0b0000..No triggers have been interrupted by a high-priority exception.
1177  *  0b0001..Trigger 0 has been interrupted by a high-priority exception.
1178  *  0b0010..Trigger 1 has been interrupted by a high-priority exception.
1179  *  0b0011-0b1110..Associated trigger sequence has interrupted by a high-priority exception.
1180  *  0b1111..Every trigger sequence has been interrupted by a high-priority exception.
1181  */
1182 #define ADC_TSTAT_TEXC_NUM(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TEXC_NUM_SHIFT)) & ADC_TSTAT_TEXC_NUM_MASK)
1183 
1184 #define ADC_TSTAT_TCOMP_FLAG_MASK                (0xF0000U)
1185 #define ADC_TSTAT_TCOMP_FLAG_SHIFT               (16U)
1186 /*! TCOMP_FLAG - Trigger Completion Flag
1187  *  0b0000..No triggers have been completed. Trigger completion interrupts are disabled.
1188  *  0b0001..Trigger 0 has been completed and trigger 0 has enabled completion interrupts.
1189  *  0b0010..Trigger 1 has been completed and trigger 1 has enabled completion interrupts.
1190  *  0b0011-0b1110..Associated trigger sequence has completed and has enabled completion interrupts.
1191  *  0b1111..Every trigger sequence has been completed and every trigger has enabled completion interrupts.
1192  */
1193 #define ADC_TSTAT_TCOMP_FLAG(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TCOMP_FLAG_SHIFT)) & ADC_TSTAT_TCOMP_FLAG_MASK)
1194 /*! @} */
1195 
1196 /*! @name OFSTRIM - Offset Trim Register */
1197 /*! @{ */
1198 
1199 #define ADC_OFSTRIM_OFSTRIM_A_MASK               (0x1FU)
1200 #define ADC_OFSTRIM_OFSTRIM_A_SHIFT              (0U)
1201 /*! OFSTRIM_A - Trim for Offset */
1202 #define ADC_OFSTRIM_OFSTRIM_A(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM_OFSTRIM_A_SHIFT)) & ADC_OFSTRIM_OFSTRIM_A_MASK)
1203 
1204 #define ADC_OFSTRIM_OFSTRIM_B_MASK               (0x1F0000U)
1205 #define ADC_OFSTRIM_OFSTRIM_B_SHIFT              (16U)
1206 /*! OFSTRIM_B - Trim for Offset */
1207 #define ADC_OFSTRIM_OFSTRIM_B(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM_OFSTRIM_B_SHIFT)) & ADC_OFSTRIM_OFSTRIM_B_MASK)
1208 /*! @} */
1209 
1210 /*! @name TCTRL - Trigger Control Register */
1211 /*! @{ */
1212 
1213 #define ADC_TCTRL_HTEN_MASK                      (0x1U)
1214 #define ADC_TCTRL_HTEN_SHIFT                     (0U)
1215 /*! HTEN - Trigger Enable
1216  *  0b0..Disabled
1217  *  0b1..Enabled
1218  */
1219 #define ADC_TCTRL_HTEN(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_HTEN_SHIFT)) & ADC_TCTRL_HTEN_MASK)
1220 
1221 #define ADC_TCTRL_FIFO_SEL_A_MASK                (0x2U)
1222 #define ADC_TCTRL_FIFO_SEL_A_SHIFT               (1U)
1223 /*! FIFO_SEL_A - SAR Result Destination for Channel A
1224  *  0b0..FIFO 0
1225  *  0b1..FIFO 1
1226  */
1227 #define ADC_TCTRL_FIFO_SEL_A(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_FIFO_SEL_A_SHIFT)) & ADC_TCTRL_FIFO_SEL_A_MASK)
1228 
1229 #define ADC_TCTRL_FIFO_SEL_B_MASK                (0x4U)
1230 #define ADC_TCTRL_FIFO_SEL_B_SHIFT               (2U)
1231 /*! FIFO_SEL_B - SAR Result Destination for Channel B
1232  *  0b0..FIFO 0
1233  *  0b1..FIFO 1
1234  */
1235 #define ADC_TCTRL_FIFO_SEL_B(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_FIFO_SEL_B_SHIFT)) & ADC_TCTRL_FIFO_SEL_B_MASK)
1236 
1237 #define ADC_TCTRL_TPRI_MASK                      (0x300U)
1238 #define ADC_TCTRL_TPRI_SHIFT                     (8U)
1239 /*! TPRI - Trigger Priority Setting
1240  *  0b00..Highest priority, Level 1
1241  *  0b01-0b10..Set to corresponding priority level.
1242  *  0b11..Lowest priority, Level 4
1243  */
1244 #define ADC_TCTRL_TPRI(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TPRI_SHIFT)) & ADC_TCTRL_TPRI_MASK)
1245 
1246 #define ADC_TCTRL_RSYNC_MASK                     (0x8000U)
1247 #define ADC_TCTRL_RSYNC_SHIFT                    (15U)
1248 /*! RSYNC - Trigger Resync
1249  *  0b0..Disable
1250  *  0b1..Enable
1251  */
1252 #define ADC_TCTRL_RSYNC(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_RSYNC_SHIFT)) & ADC_TCTRL_RSYNC_MASK)
1253 
1254 #define ADC_TCTRL_TDLY_MASK                      (0xF0000U)
1255 #define ADC_TCTRL_TDLY_SHIFT                     (16U)
1256 /*! TDLY - Trigger Delay Select */
1257 #define ADC_TCTRL_TDLY(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TDLY_SHIFT)) & ADC_TCTRL_TDLY_MASK)
1258 
1259 #define ADC_TCTRL_TCMD_MASK                      (0xF000000U)
1260 #define ADC_TCTRL_TCMD_SHIFT                     (24U)
1261 /*! TCMD - Trigger Command Select
1262  *  0b0000..Not a valid selection from the command buffer. Trigger event is ignored.
1263  *  0b0001..CMD1
1264  *  0b0010-0b1110..Corresponding CMD is executed
1265  *  0b1111..CMD15
1266  */
1267 #define ADC_TCTRL_TCMD(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TCMD_SHIFT)) & ADC_TCTRL_TCMD_MASK)
1268 /*! @} */
1269 
1270 /* The count of ADC_TCTRL */
1271 #define ADC_TCTRL_COUNT                          (4U)
1272 
1273 /*! @name FCTRL - FIFO Control Register */
1274 /*! @{ */
1275 
1276 #define ADC_FCTRL_FCOUNT_MASK                    (0x1FU)
1277 #define ADC_FCTRL_FCOUNT_SHIFT                   (0U)
1278 /*! FCOUNT - Result FIFO Counter */
1279 #define ADC_FCTRL_FCOUNT(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FCOUNT_SHIFT)) & ADC_FCTRL_FCOUNT_MASK)
1280 
1281 #define ADC_FCTRL_FWMARK_MASK                    (0xF0000U)
1282 #define ADC_FCTRL_FWMARK_SHIFT                   (16U)
1283 /*! FWMARK - Watermark Level Selection */
1284 #define ADC_FCTRL_FWMARK(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FWMARK_SHIFT)) & ADC_FCTRL_FWMARK_MASK)
1285 /*! @} */
1286 
1287 /* The count of ADC_FCTRL */
1288 #define ADC_FCTRL_COUNT                          (2U)
1289 
1290 /*! @name GCC - Gain Calibration Control */
1291 /*! @{ */
1292 
1293 #define ADC_GCC_GAIN_CAL_MASK                    (0xFFFFU)
1294 #define ADC_GCC_GAIN_CAL_SHIFT                   (0U)
1295 /*! GAIN_CAL - Gain Calibration Value */
1296 #define ADC_GCC_GAIN_CAL(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_GCC_GAIN_CAL_SHIFT)) & ADC_GCC_GAIN_CAL_MASK)
1297 
1298 #define ADC_GCC_RDY_MASK                         (0x1000000U)
1299 #define ADC_GCC_RDY_SHIFT                        (24U)
1300 /*! RDY - Gain Calibration Value Valid
1301  *  0b0..Invalid
1302  *  0b1..Valid
1303  */
1304 #define ADC_GCC_RDY(x)                           (((uint32_t)(((uint32_t)(x)) << ADC_GCC_RDY_SHIFT)) & ADC_GCC_RDY_MASK)
1305 /*! @} */
1306 
1307 /* The count of ADC_GCC */
1308 #define ADC_GCC_COUNT                            (2U)
1309 
1310 /*! @name GCR - Gain Calculation Result */
1311 /*! @{ */
1312 
1313 #define ADC_GCR_GCALR_MASK                       (0xFFFFU)
1314 #define ADC_GCR_GCALR_SHIFT                      (0U)
1315 /*! GCALR - Gain Calculation Result */
1316 #define ADC_GCR_GCALR(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_GCR_GCALR_SHIFT)) & ADC_GCR_GCALR_MASK)
1317 
1318 #define ADC_GCR_RDY_MASK                         (0x1000000U)
1319 #define ADC_GCR_RDY_SHIFT                        (24U)
1320 /*! RDY - Gain Calculation Ready
1321  *  0b0..Invalid
1322  *  0b1..Valid
1323  */
1324 #define ADC_GCR_RDY(x)                           (((uint32_t)(((uint32_t)(x)) << ADC_GCR_RDY_SHIFT)) & ADC_GCR_RDY_MASK)
1325 /*! @} */
1326 
1327 /* The count of ADC_GCR */
1328 #define ADC_GCR_COUNT                            (2U)
1329 
1330 /*! @name CMDL - Command Low Buffer Register */
1331 /*! @{ */
1332 
1333 #define ADC_CMDL_ADCH_MASK                       (0x1FU)
1334 #define ADC_CMDL_ADCH_SHIFT                      (0U)
1335 /*! ADCH - Input Channel Select
1336  *  0b00000..CH0A or CH0B or CH0A/CH0B pair.
1337  *  0b00001..CH1A or CH1B or CH1A/CH1B pair.
1338  *  0b00010..CH2A or CH2B or CH2A/CH2B pair.
1339  *  0b00011..CH3A or CH3B or CH3A/CH3B pair.
1340  *  0b00100-0b11101..Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
1341  *  0b11110..CH30A or CH30B or CH30A/CH30B pair.
1342  *  0b11111..CH31A or CH31B or CH31A/CH31B pair.
1343  */
1344 #define ADC_CMDL_ADCH(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ADCH_SHIFT)) & ADC_CMDL_ADCH_MASK)
1345 
1346 #define ADC_CMDL_CTYPE_MASK                      (0x60U)
1347 #define ADC_CMDL_CTYPE_SHIFT                     (5U)
1348 /*! CTYPE - Conversion Type
1349  *  0b00..Single-Ended mode. Only A-side channel is converted.
1350  *  0b01..Single-Ended mode. Only B-side channel is converted.
1351  *  0b10..Differential mode. A-B.
1352  *  0b11..Dual-Single-Ended mode. Both A-side and B-side channels are converted independently.
1353  */
1354 #define ADC_CMDL_CTYPE(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_CTYPE_SHIFT)) & ADC_CMDL_CTYPE_MASK)
1355 
1356 #define ADC_CMDL_MODE_MASK                       (0x80U)
1357 #define ADC_CMDL_MODE_SHIFT                      (7U)
1358 /*! MODE - Select Resolution of Conversions
1359  *  0b0..Standard resolution. Single-ended 12-bit conversion; differential 13-bit conversion with 2's complement output.
1360  *  0b1..High resolution. Single-ended 16-bit conversion; differential 16-bit conversion with 2's complement output.
1361  */
1362 #define ADC_CMDL_MODE(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_MODE_SHIFT)) & ADC_CMDL_MODE_MASK)
1363 
1364 #define ADC_CMDL_ALTB_ADCH_MASK                  (0x1F0000U)
1365 #define ADC_CMDL_ALTB_ADCH_SHIFT                 (16U)
1366 /*! ALTB_ADCH - Alternate Channel B Input Channel Select
1367  *  0b00000..Select CH0B
1368  *  0b00001..Select CH1B
1369  *  0b00010..Select CH2B
1370  *  0b00011..Select CH3B
1371  *  0b00100-0b11101..Select corresponding channel CHnB
1372  *  0b11110..Select CH30B
1373  *  0b11111..Select CH31B
1374  */
1375 #define ADC_CMDL_ALTB_ADCH(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ALTB_ADCH_SHIFT)) & ADC_CMDL_ALTB_ADCH_MASK)
1376 
1377 #define ADC_CMDL_ALTBEN_MASK                     (0x200000U)
1378 #define ADC_CMDL_ALTBEN_SHIFT                    (21U)
1379 /*! ALTBEN - Alternate Channel B Select Enable
1380  *  0b0..ALTBEN_ADCH disabled. Channel-A and Channel-B inputs are selected based on ADCH settings.
1381  *  0b1..ALTBEN_ADCH enabled. Channel-A inputs are selected by ADCH setting and Channel-B inputs are selected by ALTB_ADCH setting.
1382  */
1383 #define ADC_CMDL_ALTBEN(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ALTBEN_SHIFT)) & ADC_CMDL_ALTBEN_MASK)
1384 /*! @} */
1385 
1386 /* The count of ADC_CMDL */
1387 #define ADC_CMDL_COUNT                           (15U)
1388 
1389 /*! @name CMDH - Command High Buffer Register */
1390 /*! @{ */
1391 
1392 #define ADC_CMDH_CMPEN_MASK                      (0x3U)
1393 #define ADC_CMDH_CMPEN_SHIFT                     (0U)
1394 /*! CMPEN - Compare Function Enable
1395  *  0b00..Disabled
1396  *  0b01..
1397  *  0b10..Enabled. Store on true.
1398  *  0b11..Enabled. Repeat channel acquisition (sample, convert, and compare) until true.
1399  */
1400 #define ADC_CMDH_CMPEN(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_CMPEN_SHIFT)) & ADC_CMDH_CMPEN_MASK)
1401 
1402 #define ADC_CMDH_WAIT_TRIG_MASK                  (0x4U)
1403 #define ADC_CMDH_WAIT_TRIG_SHIFT                 (2U)
1404 /*! WAIT_TRIG - Wait for Trigger Assertion Before Execution
1405  *  0b0..Command executes automatically.
1406  *  0b1..Active trigger must be asserted again before executing this command.
1407  */
1408 #define ADC_CMDH_WAIT_TRIG(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_WAIT_TRIG_SHIFT)) & ADC_CMDH_WAIT_TRIG_MASK)
1409 
1410 #define ADC_CMDH_LWI_MASK                        (0x80U)
1411 #define ADC_CMDH_LWI_SHIFT                       (7U)
1412 /*! LWI - Loop with Increment
1413  *  0b0..Disabled
1414  *  0b1..Enabled
1415  */
1416 #define ADC_CMDH_LWI(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LWI_SHIFT)) & ADC_CMDH_LWI_MASK)
1417 
1418 #define ADC_CMDH_STS_MASK                        (0x700U)
1419 #define ADC_CMDH_STS_SHIFT                       (8U)
1420 /*! STS - Sample Time Select
1421  *  0b000..Minimum sample time of 3.5 ADCK cycles.
1422  *  0b001..5.5 ADCK cycles
1423  *  0b010..7.5 ADCK cycles
1424  *  0b011..11.5 ADCK cycles
1425  *  0b100..19.5 ADCK cycles
1426  *  0b101..35.5 ADCK cycles
1427  *  0b110..67.5 ADCK cycles
1428  *  0b111..131.5 ADCK cycles
1429  */
1430 #define ADC_CMDH_STS(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_STS_SHIFT)) & ADC_CMDH_STS_MASK)
1431 
1432 #define ADC_CMDH_AVGS_MASK                       (0xF000U)
1433 #define ADC_CMDH_AVGS_SHIFT                      (12U)
1434 /*! AVGS - Hardware Average Select
1435  *  0b0000..Single conversion
1436  *  0b0001..2
1437  *  0b0010..4
1438  *  0b0011..8
1439  *  0b0100..16
1440  *  0b0101..32
1441  *  0b0110..64
1442  *  0b0111..128
1443  *  0b1000..256
1444  *  0b1001..512
1445  *  0b1010..1024
1446  */
1447 #define ADC_CMDH_AVGS(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_AVGS_SHIFT)) & ADC_CMDH_AVGS_MASK)
1448 
1449 #define ADC_CMDH_LOOP_MASK                       (0xF0000U)
1450 #define ADC_CMDH_LOOP_SHIFT                      (16U)
1451 /*! LOOP - Loop Count Select
1452  *  0b0000..Looping not enabled. Command executes one time.
1453  *  0b0001..Loop one time. Command executes two times.
1454  *  0b0010..Loop two times. Command executes three times.
1455  *  0b0011-0b1110..Loop corresponding number of times. Command executes LOOP + 1 times.
1456  *  0b1111..Loop 15 times. Command executes 16 times.
1457  */
1458 #define ADC_CMDH_LOOP(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LOOP_SHIFT)) & ADC_CMDH_LOOP_MASK)
1459 
1460 #define ADC_CMDH_NEXT_MASK                       (0xF000000U)
1461 #define ADC_CMDH_NEXT_SHIFT                      (24U)
1462 /*! NEXT - Next Command Select
1463  *  0b0000..No next command defined. Terminate conversions at completion of current command. If lower priority
1464  *          trigger pending, begin command associated with lower priority trigger.
1465  *  0b0001..CMD1
1466  *  0b0010-0b1110..Select corresponding CMD command buffer register as next command
1467  *  0b1111..CMD15
1468  */
1469 #define ADC_CMDH_NEXT(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_NEXT_SHIFT)) & ADC_CMDH_NEXT_MASK)
1470 /*! @} */
1471 
1472 /* The count of ADC_CMDH */
1473 #define ADC_CMDH_COUNT                           (15U)
1474 
1475 /*! @name CV - Compare Value Register */
1476 /*! @{ */
1477 
1478 #define ADC_CV_CVL_MASK                          (0xFFFFU)
1479 #define ADC_CV_CVL_SHIFT                         (0U)
1480 /*! CVL - Compare Value Low */
1481 #define ADC_CV_CVL(x)                            (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVL_SHIFT)) & ADC_CV_CVL_MASK)
1482 
1483 #define ADC_CV_CVH_MASK                          (0xFFFF0000U)
1484 #define ADC_CV_CVH_SHIFT                         (16U)
1485 /*! CVH - Compare Value High */
1486 #define ADC_CV_CVH(x)                            (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVH_SHIFT)) & ADC_CV_CVH_MASK)
1487 /*! @} */
1488 
1489 /* The count of ADC_CV */
1490 #define ADC_CV_COUNT                             (15U)
1491 
1492 /*! @name RESFIFO - Data Result FIFO Register */
1493 /*! @{ */
1494 
1495 #define ADC_RESFIFO_D_MASK                       (0xFFFFU)
1496 #define ADC_RESFIFO_D_SHIFT                      (0U)
1497 /*! D - Data Result */
1498 #define ADC_RESFIFO_D(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_D_SHIFT)) & ADC_RESFIFO_D_MASK)
1499 
1500 #define ADC_RESFIFO_TSRC_MASK                    (0x30000U)
1501 #define ADC_RESFIFO_TSRC_SHIFT                   (16U)
1502 /*! TSRC - Trigger Source
1503  *  0b00..Trigger source 0
1504  *  0b01..Trigger source 1
1505  *  0b10..Trigger source 2
1506  *  0b11..Trigger source 3
1507  */
1508 #define ADC_RESFIFO_TSRC(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_TSRC_SHIFT)) & ADC_RESFIFO_TSRC_MASK)
1509 
1510 #define ADC_RESFIFO_LOOPCNT_MASK                 (0xF00000U)
1511 #define ADC_RESFIFO_LOOPCNT_SHIFT                (20U)
1512 /*! LOOPCNT - Loop Count Value
1513  *  0b0000..Result is from initial conversion in command.
1514  *  0b0001..Result is from second conversion in command.
1515  *  0b0010-0b1110..Result is from (LOOPCNT + 1) conversion in command.
1516  *  0b1111..Result is from 16th conversion in command.
1517  */
1518 #define ADC_RESFIFO_LOOPCNT(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_LOOPCNT_SHIFT)) & ADC_RESFIFO_LOOPCNT_MASK)
1519 
1520 #define ADC_RESFIFO_CMDSRC_MASK                  (0xF000000U)
1521 #define ADC_RESFIFO_CMDSRC_SHIFT                 (24U)
1522 /*! CMDSRC - Command Buffer Source
1523  *  0b0000..Not a valid value CMDSRC value for a data word in RESFIFO. 0h is only found in the initial FIFO state,
1524  *          prior to the storage of an ADC conversion result into a RESFIFO buffer.
1525  *  0b0001..CMD1
1526  *  0b0010-0b1110..Corresponding command buffer used as control settings for this conversion.
1527  *  0b1111..CMD15
1528  */
1529 #define ADC_RESFIFO_CMDSRC(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_CMDSRC_SHIFT)) & ADC_RESFIFO_CMDSRC_MASK)
1530 
1531 #define ADC_RESFIFO_VALID_MASK                   (0x80000000U)
1532 #define ADC_RESFIFO_VALID_SHIFT                  (31U)
1533 /*! VALID - FIFO Entry is Valid
1534  *  0b0..FIFO is empty. Discard any read from RESFIFO.
1535  *  0b1..FIFO contains data. FIFO record read from RESFIFO is valid.
1536  */
1537 #define ADC_RESFIFO_VALID(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_VALID_SHIFT)) & ADC_RESFIFO_VALID_MASK)
1538 /*! @} */
1539 
1540 /* The count of ADC_RESFIFO */
1541 #define ADC_RESFIFO_COUNT                        (2U)
1542 
1543 /*! @name CAL_GAR - Calibration General A-Side Registers */
1544 /*! @{ */
1545 
1546 #define ADC_CAL_GAR_CAL_GAR_VAL_MASK             (0xFFFFU)  /* Merged from fields with different position or width, of widths (11, 12, 13, 14, 15, 16), largest definition used */
1547 #define ADC_CAL_GAR_CAL_GAR_VAL_SHIFT            (0U)
1548 /*! CAL_GAR_VAL - Calibration General A Side Register Element */
1549 #define ADC_CAL_GAR_CAL_GAR_VAL(x)               (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR_CAL_GAR_VAL_MASK)  /* Merged from fields with different position or width, of widths (11, 12, 13, 14, 15, 16), largest definition used */
1550 /*! @} */
1551 
1552 /* The count of ADC_CAL_GAR */
1553 #define ADC_CAL_GAR_COUNT                        (33U)
1554 
1555 /*! @name CAL_GBR - Calibration General B-Side Registers */
1556 /*! @{ */
1557 
1558 #define ADC_CAL_GBR_CAL_GBR_VAL_MASK             (0xFFFFU)  /* Merged from fields with different position or width, of widths (11, 12, 13, 14, 15, 16), largest definition used */
1559 #define ADC_CAL_GBR_CAL_GBR_VAL_SHIFT            (0U)
1560 /*! CAL_GBR_VAL - Calibration General B Side Register Element */
1561 #define ADC_CAL_GBR_CAL_GBR_VAL(x)               (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR_CAL_GBR_VAL_MASK)  /* Merged from fields with different position or width, of widths (11, 12, 13, 14, 15, 16), largest definition used */
1562 /*! @} */
1563 
1564 /* The count of ADC_CAL_GBR */
1565 #define ADC_CAL_GBR_COUNT                        (33U)
1566 
1567 
1568 /*!
1569  * @}
1570  */ /* end of group ADC_Register_Masks */
1571 
1572 
1573 /* ADC - Peripheral instance base addresses */
1574 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
1575   /** Peripheral ADC0 base address */
1576   #define ADC0_BASE                                (0x5010D000u)
1577   /** Peripheral ADC0 base address */
1578   #define ADC0_BASE_NS                             (0x4010D000u)
1579   /** Peripheral ADC0 base pointer */
1580   #define ADC0                                     ((ADC_Type *)ADC0_BASE)
1581   /** Peripheral ADC0 base pointer */
1582   #define ADC0_NS                                  ((ADC_Type *)ADC0_BASE_NS)
1583   /** Peripheral ADC1 base address */
1584   #define ADC1_BASE                                (0x5010E000u)
1585   /** Peripheral ADC1 base address */
1586   #define ADC1_BASE_NS                             (0x4010E000u)
1587   /** Peripheral ADC1 base pointer */
1588   #define ADC1                                     ((ADC_Type *)ADC1_BASE)
1589   /** Peripheral ADC1 base pointer */
1590   #define ADC1_NS                                  ((ADC_Type *)ADC1_BASE_NS)
1591   /** Array initializer of ADC peripheral base addresses */
1592   #define ADC_BASE_ADDRS                           { ADC0_BASE, ADC1_BASE }
1593   /** Array initializer of ADC peripheral base pointers */
1594   #define ADC_BASE_PTRS                            { ADC0, ADC1 }
1595   /** Array initializer of ADC peripheral base addresses */
1596   #define ADC_BASE_ADDRS_NS                        { ADC0_BASE_NS, ADC1_BASE_NS }
1597   /** Array initializer of ADC peripheral base pointers */
1598   #define ADC_BASE_PTRS_NS                         { ADC0_NS, ADC1_NS }
1599 #else
1600   /** Peripheral ADC0 base address */
1601   #define ADC0_BASE                                (0x4010D000u)
1602   /** Peripheral ADC0 base pointer */
1603   #define ADC0                                     ((ADC_Type *)ADC0_BASE)
1604   /** Peripheral ADC1 base address */
1605   #define ADC1_BASE                                (0x4010E000u)
1606   /** Peripheral ADC1 base pointer */
1607   #define ADC1                                     ((ADC_Type *)ADC1_BASE)
1608   /** Array initializer of ADC peripheral base addresses */
1609   #define ADC_BASE_ADDRS                           { ADC0_BASE, ADC1_BASE }
1610   /** Array initializer of ADC peripheral base pointers */
1611   #define ADC_BASE_PTRS                            { ADC0, ADC1 }
1612 #endif
1613 /** Interrupt vectors for the ADC peripheral type */
1614 #define ADC_IRQS                                 { ADC0_IRQn, ADC1_IRQn }
1615 
1616 /*!
1617  * @}
1618  */ /* end of group ADC_Peripheral_Access_Layer */
1619 
1620 
1621 /* ----------------------------------------------------------------------------
1622    -- AHBSC Peripheral Access Layer
1623    ---------------------------------------------------------------------------- */
1624 
1625 /*!
1626  * @addtogroup AHBSC_Peripheral_Access_Layer AHBSC Peripheral Access Layer
1627  * @{
1628  */
1629 
1630 /** AHBSC - Register Layout Typedef */
1631 typedef struct {
1632        uint8_t RESERVED_0[16];
1633   __IO uint32_t FLASH00_MEM_RULE[4];               /**< Flash Memory Rule, array offset: 0x10, array step: 0x4 */
1634   __IO uint32_t FLASH01_MEM_RULE[4];               /**< Flash Memory Rule, array offset: 0x20, array step: 0x4 */
1635   __IO uint32_t FLASH02_MEM_RULE;                  /**< Flash Memory Rule, offset: 0x30 */
1636        uint8_t RESERVED_1[12];
1637   __IO uint32_t FLASH03_MEM_RULE;                  /**< Flash Memory Rule, offset: 0x40 */
1638        uint8_t RESERVED_2[28];
1639   __IO uint32_t ROM_MEM_RULE[4];                   /**< ROM Memory Rule, array offset: 0x60, array step: 0x4 */
1640        uint8_t RESERVED_3[16];
1641   __IO uint32_t RAMX_MEM_RULE[3];                  /**< RAMX Memory Rule, array offset: 0x80, array step: 0x4 */
1642        uint8_t RESERVED_4[20];
1643   __IO uint32_t RAMA_MEM_RULE;                     /**< RAMA Memory Rule 0, offset: 0xA0 */
1644        uint8_t RESERVED_5[28];
1645   __IO uint32_t RAMB_MEM_RULE;                     /**< RAMB Memory Rule, offset: 0xC0 */
1646        uint8_t RESERVED_6[28];
1647   __IO uint32_t RAMC_MEM_RULE[2];                  /**< RAMC Memory Rule, array offset: 0xE0, array step: 0x4 */
1648        uint8_t RESERVED_7[24];
1649   __IO uint32_t RAMD_MEM_RULE[2];                  /**< RAMD Memory Rule, array offset: 0x100, array step: 0x4 */
1650        uint8_t RESERVED_8[24];
1651   __IO uint32_t RAME_MEM_RULE[2];                  /**< RAME Memory Rule, array offset: 0x120, array step: 0x4 */
1652        uint8_t RESERVED_9[24];
1653   __IO uint32_t RAMF_MEM_RULE[2];                  /**< RAMF Memory Rule, array offset: 0x140, array step: 0x4 */
1654        uint8_t RESERVED_10[24];
1655   __IO uint32_t RAMG_MEM_RULE[2];                  /**< RAMG Memory Rule, array offset: 0x160, array step: 0x4 */
1656        uint8_t RESERVED_11[24];
1657   __IO uint32_t RAMH_MEM_RULE;                     /**< RAMH Memory Rule, offset: 0x180 */
1658        uint8_t RESERVED_12[28];
1659   __IO uint32_t APB_PERIPHERAL_GROUP0_MEM_RULE0;   /**< APB Bridge Group 0 Memory Rule 0, offset: 0x1A0 */
1660   __IO uint32_t APB_PERIPHERAL_GROUP0_MEM_RULE1;   /**< APB Bridge Group 0 Memory Rule 1, offset: 0x1A4 */
1661   __IO uint32_t APB_PERIPHERAL_GROUP0_MEM_RULE2;   /**< APB Bridge Group 0 Rule 2, offset: 0x1A8 */
1662   __IO uint32_t APB_PERIPHERAL_GROUP0_MEM_RULE3;   /**< APB Bridge Group 0 Memory Rule 3, offset: 0x1AC */
1663   __IO uint32_t APB_PERIPHERAL_GROUP1_MEM_RULE0;   /**< APB Bridge Group 1 Memory Rule 0, offset: 0x1B0 */
1664   __IO uint32_t APB_PERIPHERAL_GROUP1_MEM_RULE1;   /**< APB Bridge Group 1 Memory Rule 1, offset: 0x1B4 */
1665        uint8_t RESERVED_13[4];
1666   __IO uint32_t APB_PERIPHERAL_GROUP1_MEM_RULE2;   /**< APB Bridge Group 1 Memory Rule 2, offset: 0x1BC */
1667   __IO uint32_t AIPS_BRIDGE_GROUP0_MEM_RULE0;      /**< AIPS Bridge Group 0 Memory Rule 0, offset: 0x1C0 */
1668   __IO uint32_t AIPS_BRIDGE_GROUP0_MEM_RULE1;      /**< AIPS Bridge Group 0 Memory Rule 1, offset: 0x1C4 */
1669   __IO uint32_t AIPS_BRIDGE_GROUP0_MEM_RULE2;      /**< AIPS Bridge Group 0 Memory Rule 2, offset: 0x1C8 */
1670   __IO uint32_t AIPS_BRIDGE_GROUP0_MEM_RULE3;      /**< AIPS Bridge Group 0 Memory Rule 3, offset: 0x1CC */
1671   __IO uint32_t AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0; /**< AHB Peripheral 0 Slave Port 12 Slave Rule 0, offset: 0x1D0 */
1672   __IO uint32_t AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1; /**< AHB Peripheral 0 Slave Port 12 Slave Rule 1, offset: 0x1D4 */
1673   __IO uint32_t AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE2; /**< AHB Peripheral 0 Slave Port 12 Slave Rule 2, offset: 0x1D8 */
1674        uint8_t RESERVED_14[4];
1675   __IO uint32_t AIPS_BRIDGE_GROUP1_MEM_RULE0;      /**< AIPS Bridge Group 1 Rule 0, offset: 0x1E0 */
1676   __IO uint32_t AIPS_BRIDGE_GROUP1_MEM_RULE1;      /**< AIPS Bridge Group 1 Rule 1, offset: 0x1E4 */
1677        uint8_t RESERVED_15[8];
1678   __IO uint32_t AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0; /**< AHB Peripheral 1 Slave Port 13 Slave Rule 0, offset: 0x1F0 */
1679   __IO uint32_t AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1; /**< AHB Peripheral 1 Slave Port 13 Slave Rule 1, offset: 0x1F4 */
1680   __IO uint32_t AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE2; /**< AHB Peripheral 1 Slave Port 13 Slave Rule 2, offset: 0x1F8 */
1681        uint8_t RESERVED_16[4];
1682   __IO uint32_t AIPS_BRIDGE_GROUP2_MEM_RULE0;      /**< AIPS Bridge Group 2 Rule 0, offset: 0x200 */
1683   __IO uint32_t AIPS_BRIDGE_GROUP2_MEM_RULE1;      /**< AIPS Bridge Group 2 Memory Rule 1, offset: 0x204 */
1684        uint8_t RESERVED_17[24];
1685   __IO uint32_t AIPS_BRIDGE_GROUP3_MEM_RULE0;      /**< AIPS Bridge Group 3 Rule 0, offset: 0x220 */
1686   __IO uint32_t AIPS_BRIDGE_GROUP3_MEM_RULE1;      /**< AIPS Bridge Group 3 Memory Rule 1, offset: 0x224 */
1687   __IO uint32_t AIPS_BRIDGE_GROUP3_MEM_RULE2;      /**< AIPS Bridge Group 3 Rule 2, offset: 0x228 */
1688   __IO uint32_t AIPS_BRIDGE_GROUP3_MEM_RULE3;      /**< AIPS Bridge Group 3 Rule 3, offset: 0x22C */
1689        uint8_t RESERVED_18[16];
1690   __IO uint32_t AIPS_BRIDGE_GROUP4_MEM_RULE0;      /**< AIPS Bridge Group 4 Rule 0, offset: 0x240 */
1691   __IO uint32_t AIPS_BRIDGE_GROUP4_MEM_RULE1;      /**< AIPS Bridge Group 4 Rule 1, offset: 0x244 */
1692   __IO uint32_t AIPS_BRIDGE_GROUP4_MEM_RULE2;      /**< AIPS Bridge Group 4 Rule 2, offset: 0x248 */
1693   __IO uint32_t AIPS_BRIDGE_GROUP4_MEM_RULE3;      /**< AIPS Bridge Group 4 Rule 3, offset: 0x24C */
1694   __IO uint32_t AHB_SECURE_CTRL_PERIPHERAL_RULE0;  /**< AHB Secure Control Peripheral Rule 0, offset: 0x250 */
1695        uint8_t RESERVED_19[28];
1696   __IO uint32_t FLEXSPI0_REGION0_MEM_RULE[4];      /**< FLEXSPI0 Region 0 Memory Rule, array offset: 0x270, array step: 0x4 */
1697   struct {                                         /* offset: 0x280, array step: 0x10 */
1698     __IO uint32_t FLEXSPI0_REGION_MEM_RULE0;         /**< FLEXSPI0 Region 1 Memory Rule 0..FLEXSPI0 Region 6 Memory Rule 0, array offset: 0x280, array step: 0x10 */
1699          uint8_t RESERVED_0[12];
1700   } FLEXSPI0_REGION1_6_MEM_RULE[6];
1701   __IO uint32_t FLEXSPI0_REGION7_MEM_RULE[4];      /**< FLEXSPI0 Region 7 Memory Rule, array offset: 0x2E0, array step: 0x4 */
1702   struct {                                         /* offset: 0x2F0, array step: 0x10 */
1703     __IO uint32_t FLEXSPI0_REGION_MEM_RULE0;         /**< FLEXSPI0 Region 8 Memory Rule 0..FLEXSPI0 Region 13 Memory Rule 0, array offset: 0x2F0, array step: 0x10 */
1704          uint8_t RESERVED_0[12];
1705   } FLEXSPI0_REGION8_13_MEM_RULE[6];
1706        uint8_t RESERVED_20[2736];
1707   __I  uint32_t SEC_VIO_ADDR[32];                  /**< Security Violation Address, array offset: 0xE00, array step: 0x4 */
1708   __I  uint32_t SEC_VIO_MISC_INFO[32];             /**< Security Violation Miscellaneous Information at Address, array offset: 0xE80, array step: 0x4 */
1709   __IO uint32_t SEC_VIO_INFO_VALID;                /**< Security Violation Info Validity for Address, offset: 0xF00 */
1710        uint8_t RESERVED_21[124];
1711   __IO uint32_t SEC_GPIO_MASK[2];                  /**< GPIO Mask for Port 0..GPIO Mask for Port 1, array offset: 0xF80, array step: 0x4 */
1712        uint8_t RESERVED_22[16];
1713   __IO uint32_t SEC_CPU1_INT_MASK0;                /**< Secure Interrupt Mask 0 for CPU1, offset: 0xF98 */
1714   __IO uint32_t SEC_CPU1_INT_MASK1;                /**< Secure Interrupt Mask 1 for CPU1, offset: 0xF9C */
1715   __IO uint32_t SEC_CPU1_INT_MASK2;                /**< Secure Interrupt Mask 2 for CPU1, offset: 0xFA0 */
1716   __IO uint32_t SEC_CPU1_INT_MASK3;                /**< Secure Interrupt Mask 3 for CPU1, offset: 0xFA4 */
1717   __IO uint32_t SEC_CPU1_INT_MASK4;                /**< Secure Interrupt Mask 4 for CPU1, offset: 0xFA8 */
1718        uint8_t RESERVED_23[16];
1719   __IO uint32_t SEC_GP_REG_LOCK;                   /**< Secure Mask Lock, offset: 0xFBC */
1720        uint8_t RESERVED_24[16];
1721   __IO uint32_t MASTER_SEC_LEVEL;                  /**< Master Secure Level, offset: 0xFD0 */
1722   __IO uint32_t MASTER_SEC_ANTI_POL_REG;           /**< Master Secure Level, offset: 0xFD4 */
1723        uint8_t RESERVED_25[20];
1724   __IO uint32_t CPU0_LOCK_REG;                     /**< Miscellaneous CPU0 Control Signals, offset: 0xFEC */
1725   __IO uint32_t CPU1_LOCK_REG;                     /**< Miscellaneous CPU1 Control Signals, offset: 0xFF0 */
1726        uint8_t RESERVED_26[4];
1727   __IO uint32_t MISC_CTRL_DP_REG;                  /**< Secure Control Duplicate, offset: 0xFF8 */
1728   __IO uint32_t MISC_CTRL_REG;                     /**< Secure Control, offset: 0xFFC */
1729 } AHBSC_Type;
1730 
1731 /* ----------------------------------------------------------------------------
1732    -- AHBSC Register Masks
1733    ---------------------------------------------------------------------------- */
1734 
1735 /*!
1736  * @addtogroup AHBSC_Register_Masks AHBSC Register Masks
1737  * @{
1738  */
1739 
1740 /*! @name FLASH00_MEM_RULE - Flash Memory Rule */
1741 /*! @{ */
1742 
1743 #define AHBSC_FLASH00_MEM_RULE_RULE0_MASK        (0x3U)
1744 #define AHBSC_FLASH00_MEM_RULE_RULE0_SHIFT       (0U)
1745 /*! RULE0 - Rule 0
1746  *  0b00..Non-secure and non-privilege user access allowed
1747  *  0b01..Non-secure and privilege access allowed
1748  *  0b10..Secure and non-privilege user access allowed
1749  *  0b11..Secure and privilege user access allowed
1750  */
1751 #define AHBSC_FLASH00_MEM_RULE_RULE0(x)          (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH00_MEM_RULE_RULE0_SHIFT)) & AHBSC_FLASH00_MEM_RULE_RULE0_MASK)
1752 
1753 #define AHBSC_FLASH00_MEM_RULE_RULE1_MASK        (0x30U)
1754 #define AHBSC_FLASH00_MEM_RULE_RULE1_SHIFT       (4U)
1755 /*! RULE1 - Rule 1
1756  *  0b00..Non-secure and non-privilege user access allowed
1757  *  0b01..Non-secure and privilege access allowed
1758  *  0b10..Secure and non-privilege user access allowed
1759  *  0b11..Secure and privilege user access allowed
1760  */
1761 #define AHBSC_FLASH00_MEM_RULE_RULE1(x)          (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH00_MEM_RULE_RULE1_SHIFT)) & AHBSC_FLASH00_MEM_RULE_RULE1_MASK)
1762 
1763 #define AHBSC_FLASH00_MEM_RULE_RULE2_MASK        (0x300U)
1764 #define AHBSC_FLASH00_MEM_RULE_RULE2_SHIFT       (8U)
1765 /*! RULE2 - Rule 2
1766  *  0b00..Non-secure and non-privilege user access allowed
1767  *  0b01..Non-secure and privilege access allowed
1768  *  0b10..Secure and non-privilege user access allowed
1769  *  0b11..Secure and privilege user access allowed
1770  */
1771 #define AHBSC_FLASH00_MEM_RULE_RULE2(x)          (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH00_MEM_RULE_RULE2_SHIFT)) & AHBSC_FLASH00_MEM_RULE_RULE2_MASK)
1772 
1773 #define AHBSC_FLASH00_MEM_RULE_RULE3_MASK        (0x3000U)
1774 #define AHBSC_FLASH00_MEM_RULE_RULE3_SHIFT       (12U)
1775 /*! RULE3 - Rule 3
1776  *  0b00..Non-secure and non-privilege user access allowed
1777  *  0b01..Non-secure and privilege access allowed
1778  *  0b10..Secure and non-privilege user access allowed
1779  *  0b11..Secure and privilege user access allowed
1780  */
1781 #define AHBSC_FLASH00_MEM_RULE_RULE3(x)          (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH00_MEM_RULE_RULE3_SHIFT)) & AHBSC_FLASH00_MEM_RULE_RULE3_MASK)
1782 
1783 #define AHBSC_FLASH00_MEM_RULE_RULE4_MASK        (0x30000U)
1784 #define AHBSC_FLASH00_MEM_RULE_RULE4_SHIFT       (16U)
1785 /*! RULE4 - Rule 4
1786  *  0b00..Non-secure and non-privilege user access allowed
1787  *  0b01..Non-secure and privilege access allowed
1788  *  0b10..Secure and non-privilege user access allowed
1789  *  0b11..Secure and privilege user access allowed
1790  */
1791 #define AHBSC_FLASH00_MEM_RULE_RULE4(x)          (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH00_MEM_RULE_RULE4_SHIFT)) & AHBSC_FLASH00_MEM_RULE_RULE4_MASK)
1792 
1793 #define AHBSC_FLASH00_MEM_RULE_RULE5_MASK        (0x300000U)
1794 #define AHBSC_FLASH00_MEM_RULE_RULE5_SHIFT       (20U)
1795 /*! RULE5 - Rule 5
1796  *  0b00..Non-secure and non-privilege user access allowed
1797  *  0b01..Non-secure and privilege access allowed
1798  *  0b10..Secure and non-privilege user access allowed
1799  *  0b11..Secure and privilege user access allowed
1800  */
1801 #define AHBSC_FLASH00_MEM_RULE_RULE5(x)          (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH00_MEM_RULE_RULE5_SHIFT)) & AHBSC_FLASH00_MEM_RULE_RULE5_MASK)
1802 
1803 #define AHBSC_FLASH00_MEM_RULE_RULE6_MASK        (0x3000000U)
1804 #define AHBSC_FLASH00_MEM_RULE_RULE6_SHIFT       (24U)
1805 /*! RULE6 - Rule 6
1806  *  0b00..Non-secure and non-privilege user access allowed
1807  *  0b01..Non-secure and privilege access allowed
1808  *  0b10..Secure and non-privilege user access allowed
1809  *  0b11..Secure and privilege user access allowed
1810  */
1811 #define AHBSC_FLASH00_MEM_RULE_RULE6(x)          (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH00_MEM_RULE_RULE6_SHIFT)) & AHBSC_FLASH00_MEM_RULE_RULE6_MASK)
1812 
1813 #define AHBSC_FLASH00_MEM_RULE_RULE7_MASK        (0x30000000U)
1814 #define AHBSC_FLASH00_MEM_RULE_RULE7_SHIFT       (28U)
1815 /*! RULE7 - Rule 7
1816  *  0b00..Non-secure and non-privilege user access allowed
1817  *  0b01..Non-secure and privilege access allowed
1818  *  0b10..Secure and non-privilege user access allowed
1819  *  0b11..Secure and privilege user access allowed
1820  */
1821 #define AHBSC_FLASH00_MEM_RULE_RULE7(x)          (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH00_MEM_RULE_RULE7_SHIFT)) & AHBSC_FLASH00_MEM_RULE_RULE7_MASK)
1822 /*! @} */
1823 
1824 /* The count of AHBSC_FLASH00_MEM_RULE */
1825 #define AHBSC_FLASH00_MEM_RULE_COUNT             (4U)
1826 
1827 /*! @name FLASH01_MEM_RULE - Flash Memory Rule */
1828 /*! @{ */
1829 
1830 #define AHBSC_FLASH01_MEM_RULE_RULE0_MASK        (0x3U)
1831 #define AHBSC_FLASH01_MEM_RULE_RULE0_SHIFT       (0U)
1832 /*! RULE0 - Rule 0
1833  *  0b00..Non-secure and non-privilege user access allowed
1834  *  0b01..Non-secure and privilege access allowed
1835  *  0b10..Secure and non-privilege user access allowed
1836  *  0b11..Secure and privilege user access allowed
1837  */
1838 #define AHBSC_FLASH01_MEM_RULE_RULE0(x)          (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH01_MEM_RULE_RULE0_SHIFT)) & AHBSC_FLASH01_MEM_RULE_RULE0_MASK)
1839 
1840 #define AHBSC_FLASH01_MEM_RULE_RULE1_MASK        (0x30U)
1841 #define AHBSC_FLASH01_MEM_RULE_RULE1_SHIFT       (4U)
1842 /*! RULE1 - Rule 1
1843  *  0b00..Non-secure and non-privilege user access allowed
1844  *  0b01..Non-secure and privilege access allowed
1845  *  0b10..Secure and non-privilege user access allowed
1846  *  0b11..Secure and privilege user access allowed
1847  */
1848 #define AHBSC_FLASH01_MEM_RULE_RULE1(x)          (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH01_MEM_RULE_RULE1_SHIFT)) & AHBSC_FLASH01_MEM_RULE_RULE1_MASK)
1849 
1850 #define AHBSC_FLASH01_MEM_RULE_RULE2_MASK        (0x300U)
1851 #define AHBSC_FLASH01_MEM_RULE_RULE2_SHIFT       (8U)
1852 /*! RULE2 - Rule 2
1853  *  0b00..Non-secure and non-privilege user access allowed
1854  *  0b01..Non-secure and privilege access allowed
1855  *  0b10..Secure and non-privilege user access allowed
1856  *  0b11..Secure and privilege user access allowed
1857  */
1858 #define AHBSC_FLASH01_MEM_RULE_RULE2(x)          (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH01_MEM_RULE_RULE2_SHIFT)) & AHBSC_FLASH01_MEM_RULE_RULE2_MASK)
1859 
1860 #define AHBSC_FLASH01_MEM_RULE_RULE3_MASK        (0x3000U)
1861 #define AHBSC_FLASH01_MEM_RULE_RULE3_SHIFT       (12U)
1862 /*! RULE3 - Rule 3
1863  *  0b00..Non-secure and non-privilege user access allowed
1864  *  0b01..Non-secure and privilege access allowed
1865  *  0b10..Secure and non-privilege user access allowed
1866  *  0b11..Secure and privilege user access allowed
1867  */
1868 #define AHBSC_FLASH01_MEM_RULE_RULE3(x)          (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH01_MEM_RULE_RULE3_SHIFT)) & AHBSC_FLASH01_MEM_RULE_RULE3_MASK)
1869 
1870 #define AHBSC_FLASH01_MEM_RULE_RULE4_MASK        (0x30000U)
1871 #define AHBSC_FLASH01_MEM_RULE_RULE4_SHIFT       (16U)
1872 /*! RULE4 - Rule 4
1873  *  0b00..Non-secure and non-privilege user access allowed
1874  *  0b01..Non-secure and privilege access allowed
1875  *  0b10..Secure and non-privilege user access allowed
1876  *  0b11..Secure and privilege user access allowed
1877  */
1878 #define AHBSC_FLASH01_MEM_RULE_RULE4(x)          (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH01_MEM_RULE_RULE4_SHIFT)) & AHBSC_FLASH01_MEM_RULE_RULE4_MASK)
1879 
1880 #define AHBSC_FLASH01_MEM_RULE_RULE5_MASK        (0x300000U)
1881 #define AHBSC_FLASH01_MEM_RULE_RULE5_SHIFT       (20U)
1882 /*! RULE5 - Rule 5
1883  *  0b00..Non-secure and non-privilege user access allowed
1884  *  0b01..Non-secure and privilege access allowed
1885  *  0b10..Secure and non-privilege user access allowed
1886  *  0b11..Secure and privilege user access allowed
1887  */
1888 #define AHBSC_FLASH01_MEM_RULE_RULE5(x)          (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH01_MEM_RULE_RULE5_SHIFT)) & AHBSC_FLASH01_MEM_RULE_RULE5_MASK)
1889 
1890 #define AHBSC_FLASH01_MEM_RULE_RULE6_MASK        (0x3000000U)
1891 #define AHBSC_FLASH01_MEM_RULE_RULE6_SHIFT       (24U)
1892 /*! RULE6 - Rule 6
1893  *  0b00..Non-secure and non-privilege user access allowed
1894  *  0b01..Non-secure and privilege access allowed
1895  *  0b10..Secure and non-privilege user access allowed
1896  *  0b11..Secure and privilege user access allowed
1897  */
1898 #define AHBSC_FLASH01_MEM_RULE_RULE6(x)          (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH01_MEM_RULE_RULE6_SHIFT)) & AHBSC_FLASH01_MEM_RULE_RULE6_MASK)
1899 
1900 #define AHBSC_FLASH01_MEM_RULE_RULE7_MASK        (0x30000000U)
1901 #define AHBSC_FLASH01_MEM_RULE_RULE7_SHIFT       (28U)
1902 /*! RULE7 - Rule 7
1903  *  0b00..Non-secure and non-privilege user access allowed
1904  *  0b01..Non-secure and privilege access allowed
1905  *  0b10..Secure and non-privilege user access allowed
1906  *  0b11..Secure and privilege user access allowed
1907  */
1908 #define AHBSC_FLASH01_MEM_RULE_RULE7(x)          (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH01_MEM_RULE_RULE7_SHIFT)) & AHBSC_FLASH01_MEM_RULE_RULE7_MASK)
1909 /*! @} */
1910 
1911 /* The count of AHBSC_FLASH01_MEM_RULE */
1912 #define AHBSC_FLASH01_MEM_RULE_COUNT             (4U)
1913 
1914 /*! @name FLASH02_MEM_RULE - Flash Memory Rule */
1915 /*! @{ */
1916 
1917 #define AHBSC_FLASH02_MEM_RULE_RULE0_MASK        (0x3U)
1918 #define AHBSC_FLASH02_MEM_RULE_RULE0_SHIFT       (0U)
1919 /*! RULE0 - Rule 0
1920  *  0b00..Non-secure and non-privilege user access allowed
1921  *  0b01..Non-secure and privilege access allowed
1922  *  0b10..Secure and non-privilege user access allowed
1923  *  0b11..Secure and privilege user access allowed
1924  */
1925 #define AHBSC_FLASH02_MEM_RULE_RULE0(x)          (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH02_MEM_RULE_RULE0_SHIFT)) & AHBSC_FLASH02_MEM_RULE_RULE0_MASK)
1926 
1927 #define AHBSC_FLASH02_MEM_RULE_RULE1_MASK        (0x30U)
1928 #define AHBSC_FLASH02_MEM_RULE_RULE1_SHIFT       (4U)
1929 /*! RULE1 - Rule 1
1930  *  0b00..Non-secure and non-privilege user access allowed
1931  *  0b01..Non-secure and privilege access allowed
1932  *  0b10..Secure and non-privilege user access allowed
1933  *  0b11..Secure and privilege user access allowed
1934  */
1935 #define AHBSC_FLASH02_MEM_RULE_RULE1(x)          (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH02_MEM_RULE_RULE1_SHIFT)) & AHBSC_FLASH02_MEM_RULE_RULE1_MASK)
1936 
1937 #define AHBSC_FLASH02_MEM_RULE_RULE2_MASK        (0x300U)
1938 #define AHBSC_FLASH02_MEM_RULE_RULE2_SHIFT       (8U)
1939 /*! RULE2 - Rule 2
1940  *  0b00..Non-secure and non-privilege user access allowed
1941  *  0b01..Non-secure and privilege access allowed
1942  *  0b10..Secure and non-privilege user access allowed
1943  *  0b11..Secure and privilege user access allowed
1944  */
1945 #define AHBSC_FLASH02_MEM_RULE_RULE2(x)          (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH02_MEM_RULE_RULE2_SHIFT)) & AHBSC_FLASH02_MEM_RULE_RULE2_MASK)
1946 
1947 #define AHBSC_FLASH02_MEM_RULE_RULE3_MASK        (0x3000U)
1948 #define AHBSC_FLASH02_MEM_RULE_RULE3_SHIFT       (12U)
1949 /*! RULE3 - Rule 3
1950  *  0b00..Non-secure and non-privilege user access allowed
1951  *  0b01..Non-secure and privilege access allowed
1952  *  0b10..Secure and non-privilege user access allowed
1953  *  0b11..Secure and privilege user access allowed
1954  */
1955 #define AHBSC_FLASH02_MEM_RULE_RULE3(x)          (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH02_MEM_RULE_RULE3_SHIFT)) & AHBSC_FLASH02_MEM_RULE_RULE3_MASK)
1956 /*! @} */
1957 
1958 /*! @name FLASH03_MEM_RULE - Flash Memory Rule */
1959 /*! @{ */
1960 
1961 #define AHBSC_FLASH03_MEM_RULE_RULE0_MASK        (0x3U)
1962 #define AHBSC_FLASH03_MEM_RULE_RULE0_SHIFT       (0U)
1963 /*! RULE0 - Rule 0
1964  *  0b00..Non-secure and non-privilege user access allowed
1965  *  0b01..Non-secure and privilege access allowed
1966  *  0b10..Secure and non-privilege user access allowed
1967  *  0b11..Secure and privilege user access allowed
1968  */
1969 #define AHBSC_FLASH03_MEM_RULE_RULE0(x)          (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH03_MEM_RULE_RULE0_SHIFT)) & AHBSC_FLASH03_MEM_RULE_RULE0_MASK)
1970 
1971 #define AHBSC_FLASH03_MEM_RULE_RULE1_MASK        (0x30U)
1972 #define AHBSC_FLASH03_MEM_RULE_RULE1_SHIFT       (4U)
1973 /*! RULE1 - Rule 1
1974  *  0b00..Non-secure and non-privilege user access allowed
1975  *  0b01..Non-secure and privilege access allowed
1976  *  0b10..Secure and non-privilege user access allowed
1977  *  0b11..Secure and privilege user access allowed
1978  */
1979 #define AHBSC_FLASH03_MEM_RULE_RULE1(x)          (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH03_MEM_RULE_RULE1_SHIFT)) & AHBSC_FLASH03_MEM_RULE_RULE1_MASK)
1980 
1981 #define AHBSC_FLASH03_MEM_RULE_RULE2_MASK        (0x300U)
1982 #define AHBSC_FLASH03_MEM_RULE_RULE2_SHIFT       (8U)
1983 /*! RULE2 - Rule 2
1984  *  0b00..Non-secure and non-privilege user access allowed
1985  *  0b01..Non-secure and privilege access allowed
1986  *  0b10..Secure and non-privilege user access allowed
1987  *  0b11..Secure and privilege user access allowed
1988  */
1989 #define AHBSC_FLASH03_MEM_RULE_RULE2(x)          (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH03_MEM_RULE_RULE2_SHIFT)) & AHBSC_FLASH03_MEM_RULE_RULE2_MASK)
1990 
1991 #define AHBSC_FLASH03_MEM_RULE_RULE3_MASK        (0x3000U)
1992 #define AHBSC_FLASH03_MEM_RULE_RULE3_SHIFT       (12U)
1993 /*! RULE3 - Rule 3
1994  *  0b00..Non-secure and non-privilege user access allowed
1995  *  0b01..Non-secure and privilege access allowed
1996  *  0b10..Secure and non-privilege user access allowed
1997  *  0b11..Secure and privilege user access allowed
1998  */
1999 #define AHBSC_FLASH03_MEM_RULE_RULE3(x)          (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH03_MEM_RULE_RULE3_SHIFT)) & AHBSC_FLASH03_MEM_RULE_RULE3_MASK)
2000 
2001 #define AHBSC_FLASH03_MEM_RULE_RULE4_MASK        (0x30000U)
2002 #define AHBSC_FLASH03_MEM_RULE_RULE4_SHIFT       (16U)
2003 /*! RULE4 - Rule 4
2004  *  0b00..Non-secure and non-privilege user access allowed
2005  *  0b01..Non-secure and privilege access allowed
2006  *  0b10..Secure and non-privilege user access allowed
2007  *  0b11..Secure and privilege user access allowed
2008  */
2009 #define AHBSC_FLASH03_MEM_RULE_RULE4(x)          (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH03_MEM_RULE_RULE4_SHIFT)) & AHBSC_FLASH03_MEM_RULE_RULE4_MASK)
2010 
2011 #define AHBSC_FLASH03_MEM_RULE_RULE5_MASK        (0x300000U)
2012 #define AHBSC_FLASH03_MEM_RULE_RULE5_SHIFT       (20U)
2013 /*! RULE5 - Rule 5
2014  *  0b00..Non-secure and non-privilege user access allowed
2015  *  0b01..Non-secure and privilege access allowed
2016  *  0b10..Secure and non-privilege user access allowed
2017  *  0b11..Secure and privilege user access allowed
2018  */
2019 #define AHBSC_FLASH03_MEM_RULE_RULE5(x)          (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH03_MEM_RULE_RULE5_SHIFT)) & AHBSC_FLASH03_MEM_RULE_RULE5_MASK)
2020 
2021 #define AHBSC_FLASH03_MEM_RULE_RULE6_MASK        (0x3000000U)
2022 #define AHBSC_FLASH03_MEM_RULE_RULE6_SHIFT       (24U)
2023 /*! RULE6 - Rule 6
2024  *  0b00..Non-secure and non-privilege user access allowed
2025  *  0b01..Non-secure and privilege access allowed
2026  *  0b10..Secure and non-privilege user access allowed
2027  *  0b11..Secure and privilege user access allowed
2028  */
2029 #define AHBSC_FLASH03_MEM_RULE_RULE6(x)          (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH03_MEM_RULE_RULE6_SHIFT)) & AHBSC_FLASH03_MEM_RULE_RULE6_MASK)
2030 
2031 #define AHBSC_FLASH03_MEM_RULE_RULE7_MASK        (0x30000000U)
2032 #define AHBSC_FLASH03_MEM_RULE_RULE7_SHIFT       (28U)
2033 /*! RULE7 - Rule 7
2034  *  0b00..Non-secure and non-privilege user access allowed
2035  *  0b01..Non-secure and privilege access allowed
2036  *  0b10..Secure and non-privilege user access allowed
2037  *  0b11..Secure and privilege user access allowed
2038  */
2039 #define AHBSC_FLASH03_MEM_RULE_RULE7(x)          (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH03_MEM_RULE_RULE7_SHIFT)) & AHBSC_FLASH03_MEM_RULE_RULE7_MASK)
2040 /*! @} */
2041 
2042 /*! @name ROM_MEM_RULE - ROM Memory Rule */
2043 /*! @{ */
2044 
2045 #define AHBSC_ROM_MEM_RULE_RULE0_MASK            (0x3U)
2046 #define AHBSC_ROM_MEM_RULE_RULE0_SHIFT           (0U)
2047 /*! RULE0 - Rule 0
2048  *  0b00..Non-secure and non-privilege user access allowed
2049  *  0b01..Non-secure and privilege access allowed
2050  *  0b10..Secure and non-privilege user access allowed
2051  *  0b11..Secure and privilege user access allowed
2052  */
2053 #define AHBSC_ROM_MEM_RULE_RULE0(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC_ROM_MEM_RULE_RULE0_SHIFT)) & AHBSC_ROM_MEM_RULE_RULE0_MASK)
2054 
2055 #define AHBSC_ROM_MEM_RULE_RULE1_MASK            (0x30U)
2056 #define AHBSC_ROM_MEM_RULE_RULE1_SHIFT           (4U)
2057 /*! RULE1 - Rule 1
2058  *  0b00..Non-secure and non-privilege user access allowed
2059  *  0b01..Non-secure and privilege access allowed
2060  *  0b10..Secure and non-privilege user access allowed
2061  *  0b11..Secure and privilege user access allowed
2062  */
2063 #define AHBSC_ROM_MEM_RULE_RULE1(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC_ROM_MEM_RULE_RULE1_SHIFT)) & AHBSC_ROM_MEM_RULE_RULE1_MASK)
2064 
2065 #define AHBSC_ROM_MEM_RULE_RULE2_MASK            (0x300U)
2066 #define AHBSC_ROM_MEM_RULE_RULE2_SHIFT           (8U)
2067 /*! RULE2 - Rule 2
2068  *  0b00..Non-secure and non-privilege user access allowed
2069  *  0b01..Non-secure and privilege access allowed
2070  *  0b10..Secure and non-privilege user access allowed
2071  *  0b11..Secure and privilege user access allowed
2072  */
2073 #define AHBSC_ROM_MEM_RULE_RULE2(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC_ROM_MEM_RULE_RULE2_SHIFT)) & AHBSC_ROM_MEM_RULE_RULE2_MASK)
2074 
2075 #define AHBSC_ROM_MEM_RULE_RULE3_MASK            (0x3000U)
2076 #define AHBSC_ROM_MEM_RULE_RULE3_SHIFT           (12U)
2077 /*! RULE3 - Rule 3
2078  *  0b00..Non-secure and non-privilege user access allowed
2079  *  0b01..Non-secure and privilege access allowed
2080  *  0b10..Secure and non-privilege user access allowed
2081  *  0b11..Secure and privilege user access allowed
2082  */
2083 #define AHBSC_ROM_MEM_RULE_RULE3(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC_ROM_MEM_RULE_RULE3_SHIFT)) & AHBSC_ROM_MEM_RULE_RULE3_MASK)
2084 
2085 #define AHBSC_ROM_MEM_RULE_RULE4_MASK            (0x30000U)
2086 #define AHBSC_ROM_MEM_RULE_RULE4_SHIFT           (16U)
2087 /*! RULE4 - Rule 4
2088  *  0b00..Non-secure and non-privilege user access allowed
2089  *  0b01..Non-secure and privilege access allowed
2090  *  0b10..Secure and non-privilege user access allowed
2091  *  0b11..Secure and privilege user access allowed
2092  */
2093 #define AHBSC_ROM_MEM_RULE_RULE4(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC_ROM_MEM_RULE_RULE4_SHIFT)) & AHBSC_ROM_MEM_RULE_RULE4_MASK)
2094 
2095 #define AHBSC_ROM_MEM_RULE_RULE5_MASK            (0x300000U)
2096 #define AHBSC_ROM_MEM_RULE_RULE5_SHIFT           (20U)
2097 /*! RULE5 - Rule 5
2098  *  0b00..Non-secure and non-privilege user access allowed
2099  *  0b01..Non-secure and privilege access allowed
2100  *  0b10..Secure and non-privilege user access allowed
2101  *  0b11..Secure and privilege user access allowed
2102  */
2103 #define AHBSC_ROM_MEM_RULE_RULE5(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC_ROM_MEM_RULE_RULE5_SHIFT)) & AHBSC_ROM_MEM_RULE_RULE5_MASK)
2104 
2105 #define AHBSC_ROM_MEM_RULE_RULE6_MASK            (0x3000000U)
2106 #define AHBSC_ROM_MEM_RULE_RULE6_SHIFT           (24U)
2107 /*! RULE6 - Rule 6
2108  *  0b00..Non-secure and non-privilege user access allowed
2109  *  0b01..Non-secure and privilege access allowed
2110  *  0b10..Secure and non-privilege user access allowed
2111  *  0b11..Secure and privilege user access allowed
2112  */
2113 #define AHBSC_ROM_MEM_RULE_RULE6(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC_ROM_MEM_RULE_RULE6_SHIFT)) & AHBSC_ROM_MEM_RULE_RULE6_MASK)
2114 
2115 #define AHBSC_ROM_MEM_RULE_RULE7_MASK            (0x30000000U)
2116 #define AHBSC_ROM_MEM_RULE_RULE7_SHIFT           (28U)
2117 /*! RULE7 - Rule 7
2118  *  0b00..Non-secure and non-privilege user access allowed
2119  *  0b01..Non-secure and privilege access allowed
2120  *  0b10..Secure and non-privilege user access allowed
2121  *  0b11..Secure and privilege user access allowed
2122  */
2123 #define AHBSC_ROM_MEM_RULE_RULE7(x)              (((uint32_t)(((uint32_t)(x)) << AHBSC_ROM_MEM_RULE_RULE7_SHIFT)) & AHBSC_ROM_MEM_RULE_RULE7_MASK)
2124 /*! @} */
2125 
2126 /* The count of AHBSC_ROM_MEM_RULE */
2127 #define AHBSC_ROM_MEM_RULE_COUNT                 (4U)
2128 
2129 /*! @name RAMX_MEM_RULE0_RAMX_MEM_RULE - RAMX Memory Rule */
2130 /*! @{ */
2131 
2132 #define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE0_MASK (0x3U)
2133 #define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE0_SHIFT (0U)
2134 /*! RULE0 - Rule 0
2135  *  0b00..Non-secure and non-privilege user access allowed
2136  *  0b01..Non-secure and privilege access allowed
2137  *  0b10..Secure and non-privilege user access allowed
2138  *  0b11..Secure and privilege user access allowed
2139  */
2140 #define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE0_SHIFT)) & AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE0_MASK)
2141 
2142 #define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE1_MASK (0x30U)
2143 #define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE1_SHIFT (4U)
2144 /*! RULE1 - Rule 1
2145  *  0b00..Non-secure and non-privilege user access allowed
2146  *  0b01..Non-secure and privilege access allowed
2147  *  0b10..Secure and non-privilege user access allowed
2148  *  0b11..Secure and privilege user access allowed
2149  */
2150 #define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE1_SHIFT)) & AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE1_MASK)
2151 
2152 #define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE2_MASK (0x300U)
2153 #define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE2_SHIFT (8U)
2154 /*! RULE2 - Rule 2
2155  *  0b00..Non-secure and non-privilege user access allowed
2156  *  0b01..Non-secure and privilege access allowed
2157  *  0b10..Secure and non-privilege user access allowed
2158  *  0b11..Secure and privilege user access allowed
2159  */
2160 #define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE2_SHIFT)) & AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE2_MASK)
2161 
2162 #define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE3_MASK (0x3000U)
2163 #define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE3_SHIFT (12U)
2164 /*! RULE3 - Rule 3
2165  *  0b00..Non-secure and non-privilege user access allowed
2166  *  0b01..Non-secure and privilege access allowed
2167  *  0b10..Secure and non-privilege user access allowed
2168  *  0b11..Secure and privilege user access allowed
2169  */
2170 #define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE3_SHIFT)) & AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE3_MASK)
2171 
2172 #define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE4_MASK (0x30000U)
2173 #define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE4_SHIFT (16U)
2174 /*! RULE4 - Rule 4
2175  *  0b00..Non-secure and non-privilege user access allowed
2176  *  0b01..Non-secure and privilege access allowed
2177  *  0b10..Secure and non-privilege user access allowed
2178  *  0b11..Secure and privilege user access allowed
2179  */
2180 #define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE4_SHIFT)) & AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE4_MASK)
2181 
2182 #define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE5_MASK (0x300000U)
2183 #define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE5_SHIFT (20U)
2184 /*! RULE5 - Rule 5
2185  *  0b00..Non-secure and non-privilege user access allowed
2186  *  0b01..Non-secure and privilege access allowed
2187  *  0b10..Secure and non-privilege user access allowed
2188  *  0b11..Secure and privilege user access allowed
2189  */
2190 #define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE5_SHIFT)) & AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE5_MASK)
2191 
2192 #define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE6_MASK (0x3000000U)
2193 #define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE6_SHIFT (24U)
2194 /*! RULE6 - Rule 6
2195  *  0b00..Non-secure and non-privilege user access allowed
2196  *  0b01..Non-secure and privilege access allowed
2197  *  0b10..Secure and non-privilege user access allowed
2198  *  0b11..Secure and privilege user access allowed
2199  */
2200 #define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE6_SHIFT)) & AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE6_MASK)
2201 
2202 #define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE7_MASK (0x30000000U)
2203 #define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE7_SHIFT (28U)
2204 /*! RULE7 - Rule 7
2205  *  0b00..Non-secure and non-privilege user access allowed
2206  *  0b01..Non-secure and privilege access allowed
2207  *  0b10..Secure and non-privilege user access allowed
2208  *  0b11..Secure and privilege user access allowed
2209  */
2210 #define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE7_SHIFT)) & AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE7_MASK)
2211 /*! @} */
2212 
2213 /* The count of AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE */
2214 #define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_COUNT (3U)
2215 
2216 /*! @name RAMA_MEM_RULE - RAMA Memory Rule 0 */
2217 /*! @{ */
2218 
2219 #define AHBSC_RAMA_MEM_RULE_RULE0_MASK           (0x3U)
2220 #define AHBSC_RAMA_MEM_RULE_RULE0_SHIFT          (0U)
2221 /*! RULE0 - Rule 0
2222  *  0b00..Non-secure and non-privilege user access allowed
2223  *  0b01..Non-secure and privilege access allowed
2224  *  0b10..Secure and non-privilege user access allowed
2225  *  0b11..Secure and privilege user access allowed
2226  */
2227 #define AHBSC_RAMA_MEM_RULE_RULE0(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMA_MEM_RULE_RULE0_SHIFT)) & AHBSC_RAMA_MEM_RULE_RULE0_MASK)
2228 
2229 #define AHBSC_RAMA_MEM_RULE_RULE1_MASK           (0x30U)
2230 #define AHBSC_RAMA_MEM_RULE_RULE1_SHIFT          (4U)
2231 /*! RULE1 - Rule 1
2232  *  0b00..Non-secure and non-privilege user access allowed
2233  *  0b01..Non-secure and privilege access allowed
2234  *  0b10..Secure and non-privilege user access allowed
2235  *  0b11..Secure and privilege user access allowed
2236  */
2237 #define AHBSC_RAMA_MEM_RULE_RULE1(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMA_MEM_RULE_RULE1_SHIFT)) & AHBSC_RAMA_MEM_RULE_RULE1_MASK)
2238 
2239 #define AHBSC_RAMA_MEM_RULE_RULE2_MASK           (0x300U)
2240 #define AHBSC_RAMA_MEM_RULE_RULE2_SHIFT          (8U)
2241 /*! RULE2 - Rule 2
2242  *  0b00..Non-secure and non-privilege user access allowed
2243  *  0b01..Non-secure and privilege access allowed
2244  *  0b10..Secure and non-privilege user access allowed
2245  *  0b11..Secure and privilege user access allowed
2246  */
2247 #define AHBSC_RAMA_MEM_RULE_RULE2(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMA_MEM_RULE_RULE2_SHIFT)) & AHBSC_RAMA_MEM_RULE_RULE2_MASK)
2248 
2249 #define AHBSC_RAMA_MEM_RULE_RULE3_MASK           (0x3000U)
2250 #define AHBSC_RAMA_MEM_RULE_RULE3_SHIFT          (12U)
2251 /*! RULE3 - Rule 3
2252  *  0b00..Non-secure and non-privilege user access allowed
2253  *  0b01..Non-secure and privilege access allowed
2254  *  0b10..Secure and non-privilege user access allowed
2255  *  0b11..Secure and privilege user access allowed
2256  */
2257 #define AHBSC_RAMA_MEM_RULE_RULE3(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMA_MEM_RULE_RULE3_SHIFT)) & AHBSC_RAMA_MEM_RULE_RULE3_MASK)
2258 
2259 #define AHBSC_RAMA_MEM_RULE_RULE4_MASK           (0x30000U)
2260 #define AHBSC_RAMA_MEM_RULE_RULE4_SHIFT          (16U)
2261 /*! RULE4 - Rule 4
2262  *  0b00..Non-secure and non-privilege user access allowed
2263  *  0b01..Non-secure and privilege access allowed
2264  *  0b10..Secure and non-privilege user access allowed
2265  *  0b11..Secure and privilege user access allowed
2266  */
2267 #define AHBSC_RAMA_MEM_RULE_RULE4(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMA_MEM_RULE_RULE4_SHIFT)) & AHBSC_RAMA_MEM_RULE_RULE4_MASK)
2268 
2269 #define AHBSC_RAMA_MEM_RULE_RULE5_MASK           (0x300000U)
2270 #define AHBSC_RAMA_MEM_RULE_RULE5_SHIFT          (20U)
2271 /*! RULE5 - Rule 5
2272  *  0b00..Non-secure and non-privilege user access allowed
2273  *  0b01..Non-secure and privilege access allowed
2274  *  0b10..Secure and non-privilege user access allowed
2275  *  0b11..Secure and privilege user access allowed
2276  */
2277 #define AHBSC_RAMA_MEM_RULE_RULE5(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMA_MEM_RULE_RULE5_SHIFT)) & AHBSC_RAMA_MEM_RULE_RULE5_MASK)
2278 
2279 #define AHBSC_RAMA_MEM_RULE_RULE6_MASK           (0x3000000U)
2280 #define AHBSC_RAMA_MEM_RULE_RULE6_SHIFT          (24U)
2281 /*! RULE6 - Rule 6
2282  *  0b00..Non-secure and non-privilege user access allowed
2283  *  0b01..Non-secure and privilege access allowed
2284  *  0b10..Secure and non-privilege user access allowed
2285  *  0b11..Secure and privilege user access allowed
2286  */
2287 #define AHBSC_RAMA_MEM_RULE_RULE6(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMA_MEM_RULE_RULE6_SHIFT)) & AHBSC_RAMA_MEM_RULE_RULE6_MASK)
2288 
2289 #define AHBSC_RAMA_MEM_RULE_RULE7_MASK           (0x30000000U)
2290 #define AHBSC_RAMA_MEM_RULE_RULE7_SHIFT          (28U)
2291 /*! RULE7 - Rule 7
2292  *  0b00..Non-secure and non-privilege user access allowed
2293  *  0b01..Non-secure and privilege access allowed
2294  *  0b10..Secure and non-privilege user access allowed
2295  *  0b11..Secure and privilege user access allowed
2296  */
2297 #define AHBSC_RAMA_MEM_RULE_RULE7(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMA_MEM_RULE_RULE7_SHIFT)) & AHBSC_RAMA_MEM_RULE_RULE7_MASK)
2298 /*! @} */
2299 
2300 /*! @name RAMB_MEM_RULE - RAMB Memory Rule */
2301 /*! @{ */
2302 
2303 #define AHBSC_RAMB_MEM_RULE_RULE0_MASK           (0x3U)
2304 #define AHBSC_RAMB_MEM_RULE_RULE0_SHIFT          (0U)
2305 /*! RULE0 - Rule 0
2306  *  0b00..Non-secure and non-privilege user access allowed
2307  *  0b01..Non-secure and privilege access allowed
2308  *  0b10..Secure and non-privilege user access allowed
2309  *  0b11..Secure and privilege user access allowed
2310  */
2311 #define AHBSC_RAMB_MEM_RULE_RULE0(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMB_MEM_RULE_RULE0_SHIFT)) & AHBSC_RAMB_MEM_RULE_RULE0_MASK)
2312 
2313 #define AHBSC_RAMB_MEM_RULE_RULE1_MASK           (0x30U)
2314 #define AHBSC_RAMB_MEM_RULE_RULE1_SHIFT          (4U)
2315 /*! RULE1 - Rule 1
2316  *  0b00..Non-secure and non-privilege user access allowed
2317  *  0b01..Non-secure and privilege access allowed
2318  *  0b10..Secure and non-privilege user access allowed
2319  *  0b11..Secure and privilege user access allowed
2320  */
2321 #define AHBSC_RAMB_MEM_RULE_RULE1(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMB_MEM_RULE_RULE1_SHIFT)) & AHBSC_RAMB_MEM_RULE_RULE1_MASK)
2322 
2323 #define AHBSC_RAMB_MEM_RULE_RULE2_MASK           (0x300U)
2324 #define AHBSC_RAMB_MEM_RULE_RULE2_SHIFT          (8U)
2325 /*! RULE2 - Rule 2
2326  *  0b00..Non-secure and non-privilege user access allowed
2327  *  0b01..Non-secure and privilege access allowed
2328  *  0b10..Secure and non-privilege user access allowed
2329  *  0b11..Secure and privilege user access allowed
2330  */
2331 #define AHBSC_RAMB_MEM_RULE_RULE2(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMB_MEM_RULE_RULE2_SHIFT)) & AHBSC_RAMB_MEM_RULE_RULE2_MASK)
2332 
2333 #define AHBSC_RAMB_MEM_RULE_RULE3_MASK           (0x3000U)
2334 #define AHBSC_RAMB_MEM_RULE_RULE3_SHIFT          (12U)
2335 /*! RULE3 - Rule 3
2336  *  0b00..Non-secure and non-privilege user access allowed
2337  *  0b01..Non-secure and privilege access allowed
2338  *  0b10..Secure and non-privilege user access allowed
2339  *  0b11..Secure and privilege user access allowed
2340  */
2341 #define AHBSC_RAMB_MEM_RULE_RULE3(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMB_MEM_RULE_RULE3_SHIFT)) & AHBSC_RAMB_MEM_RULE_RULE3_MASK)
2342 
2343 #define AHBSC_RAMB_MEM_RULE_RULE4_MASK           (0x30000U)
2344 #define AHBSC_RAMB_MEM_RULE_RULE4_SHIFT          (16U)
2345 /*! RULE4 - Rule 4
2346  *  0b00..Non-secure and non-privilege user access allowed
2347  *  0b01..Non-secure and privilege access allowed
2348  *  0b10..Secure and non-privilege user access allowed
2349  *  0b11..Secure and privilege user access allowed
2350  */
2351 #define AHBSC_RAMB_MEM_RULE_RULE4(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMB_MEM_RULE_RULE4_SHIFT)) & AHBSC_RAMB_MEM_RULE_RULE4_MASK)
2352 
2353 #define AHBSC_RAMB_MEM_RULE_RULE5_MASK           (0x300000U)
2354 #define AHBSC_RAMB_MEM_RULE_RULE5_SHIFT          (20U)
2355 /*! RULE5 - Rule 5
2356  *  0b00..Non-secure and non-privilege user access allowed
2357  *  0b01..Non-secure and privilege access allowed
2358  *  0b10..Secure and non-privilege user access allowed
2359  *  0b11..Secure and privilege user access allowed
2360  */
2361 #define AHBSC_RAMB_MEM_RULE_RULE5(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMB_MEM_RULE_RULE5_SHIFT)) & AHBSC_RAMB_MEM_RULE_RULE5_MASK)
2362 
2363 #define AHBSC_RAMB_MEM_RULE_RULE6_MASK           (0x3000000U)
2364 #define AHBSC_RAMB_MEM_RULE_RULE6_SHIFT          (24U)
2365 /*! RULE6 - Rule 6
2366  *  0b00..Non-secure and non-privilege user access allowed
2367  *  0b01..Non-secure and privilege access allowed
2368  *  0b10..Secure and non-privilege user access allowed
2369  *  0b11..Secure and privilege user access allowed
2370  */
2371 #define AHBSC_RAMB_MEM_RULE_RULE6(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMB_MEM_RULE_RULE6_SHIFT)) & AHBSC_RAMB_MEM_RULE_RULE6_MASK)
2372 
2373 #define AHBSC_RAMB_MEM_RULE_RULE7_MASK           (0x30000000U)
2374 #define AHBSC_RAMB_MEM_RULE_RULE7_SHIFT          (28U)
2375 /*! RULE7 - Rule 7
2376  *  0b00..Non-secure and non-privilege user access allowed
2377  *  0b01..Non-secure and privilege access allowed
2378  *  0b10..Secure and non-privilege user access allowed
2379  *  0b11..Secure and privilege user access allowed
2380  */
2381 #define AHBSC_RAMB_MEM_RULE_RULE7(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMB_MEM_RULE_RULE7_SHIFT)) & AHBSC_RAMB_MEM_RULE_RULE7_MASK)
2382 /*! @} */
2383 
2384 /*! @name RAMC_MEM_RULE - RAMC Memory Rule */
2385 /*! @{ */
2386 
2387 #define AHBSC_RAMC_MEM_RULE_RULE0_MASK           (0x3U)
2388 #define AHBSC_RAMC_MEM_RULE_RULE0_SHIFT          (0U)
2389 /*! RULE0 - Rule 0
2390  *  0b00..Non-secure and non-privilege user access allowed
2391  *  0b01..Non-secure and privilege access allowed
2392  *  0b10..Secure and non-privilege user access allowed
2393  *  0b11..Secure and privilege user access allowed
2394  */
2395 #define AHBSC_RAMC_MEM_RULE_RULE0(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMC_MEM_RULE_RULE0_SHIFT)) & AHBSC_RAMC_MEM_RULE_RULE0_MASK)
2396 
2397 #define AHBSC_RAMC_MEM_RULE_RULE1_MASK           (0x30U)
2398 #define AHBSC_RAMC_MEM_RULE_RULE1_SHIFT          (4U)
2399 /*! RULE1 - Rule 1
2400  *  0b00..Non-secure and non-privilege user access allowed
2401  *  0b01..Non-secure and privilege access allowed
2402  *  0b10..Secure and non-privilege user access allowed
2403  *  0b11..Secure and privilege user access allowed
2404  */
2405 #define AHBSC_RAMC_MEM_RULE_RULE1(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMC_MEM_RULE_RULE1_SHIFT)) & AHBSC_RAMC_MEM_RULE_RULE1_MASK)
2406 
2407 #define AHBSC_RAMC_MEM_RULE_RULE2_MASK           (0x300U)
2408 #define AHBSC_RAMC_MEM_RULE_RULE2_SHIFT          (8U)
2409 /*! RULE2 - Rule 2
2410  *  0b00..Non-secure and non-privilege user access allowed
2411  *  0b01..Non-secure and privilege access allowed
2412  *  0b10..Secure and non-privilege user access allowed
2413  *  0b11..Secure and privilege user access allowed
2414  */
2415 #define AHBSC_RAMC_MEM_RULE_RULE2(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMC_MEM_RULE_RULE2_SHIFT)) & AHBSC_RAMC_MEM_RULE_RULE2_MASK)
2416 
2417 #define AHBSC_RAMC_MEM_RULE_RULE3_MASK           (0x3000U)
2418 #define AHBSC_RAMC_MEM_RULE_RULE3_SHIFT          (12U)
2419 /*! RULE3 - Rule 3
2420  *  0b00..Non-secure and non-privilege user access allowed
2421  *  0b01..Non-secure and privilege access allowed
2422  *  0b10..Secure and non-privilege user access allowed
2423  *  0b11..Secure and privilege user access allowed
2424  */
2425 #define AHBSC_RAMC_MEM_RULE_RULE3(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMC_MEM_RULE_RULE3_SHIFT)) & AHBSC_RAMC_MEM_RULE_RULE3_MASK)
2426 
2427 #define AHBSC_RAMC_MEM_RULE_RULE4_MASK           (0x30000U)
2428 #define AHBSC_RAMC_MEM_RULE_RULE4_SHIFT          (16U)
2429 /*! RULE4 - Rule 4
2430  *  0b00..Non-secure and non-privilege user access allowed
2431  *  0b01..Non-secure and privilege access allowed
2432  *  0b10..Secure and non-privilege user access allowed
2433  *  0b11..Secure and privilege user access allowed
2434  */
2435 #define AHBSC_RAMC_MEM_RULE_RULE4(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMC_MEM_RULE_RULE4_SHIFT)) & AHBSC_RAMC_MEM_RULE_RULE4_MASK)
2436 
2437 #define AHBSC_RAMC_MEM_RULE_RULE5_MASK           (0x300000U)
2438 #define AHBSC_RAMC_MEM_RULE_RULE5_SHIFT          (20U)
2439 /*! RULE5 - Rule 5
2440  *  0b00..Non-secure and non-privilege user access allowed
2441  *  0b01..Non-secure and privilege access allowed
2442  *  0b10..Secure and non-privilege user access allowed
2443  *  0b11..Secure and privilege user access allowed
2444  */
2445 #define AHBSC_RAMC_MEM_RULE_RULE5(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMC_MEM_RULE_RULE5_SHIFT)) & AHBSC_RAMC_MEM_RULE_RULE5_MASK)
2446 
2447 #define AHBSC_RAMC_MEM_RULE_RULE6_MASK           (0x3000000U)
2448 #define AHBSC_RAMC_MEM_RULE_RULE6_SHIFT          (24U)
2449 /*! RULE6 - Rule 6
2450  *  0b00..Non-secure and non-privilege user access allowed
2451  *  0b01..Non-secure and privilege access allowed
2452  *  0b10..Secure and non-privilege user access allowed
2453  *  0b11..Secure and privilege user access allowed
2454  */
2455 #define AHBSC_RAMC_MEM_RULE_RULE6(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMC_MEM_RULE_RULE6_SHIFT)) & AHBSC_RAMC_MEM_RULE_RULE6_MASK)
2456 
2457 #define AHBSC_RAMC_MEM_RULE_RULE7_MASK           (0x30000000U)
2458 #define AHBSC_RAMC_MEM_RULE_RULE7_SHIFT          (28U)
2459 /*! RULE7 - Rule 7
2460  *  0b00..Non-secure and non-privilege user access allowed
2461  *  0b01..Non-secure and privilege access allowed
2462  *  0b10..Secure and non-privilege user access allowed
2463  *  0b11..Secure and privilege user access allowed
2464  */
2465 #define AHBSC_RAMC_MEM_RULE_RULE7(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMC_MEM_RULE_RULE7_SHIFT)) & AHBSC_RAMC_MEM_RULE_RULE7_MASK)
2466 /*! @} */
2467 
2468 /* The count of AHBSC_RAMC_MEM_RULE */
2469 #define AHBSC_RAMC_MEM_RULE_COUNT                (2U)
2470 
2471 /*! @name RAMD_MEM_RULE - RAMD Memory Rule */
2472 /*! @{ */
2473 
2474 #define AHBSC_RAMD_MEM_RULE_RULE0_MASK           (0x3U)
2475 #define AHBSC_RAMD_MEM_RULE_RULE0_SHIFT          (0U)
2476 /*! RULE0 - Rule 0
2477  *  0b00..Non-secure and non-privilege user access allowed
2478  *  0b01..Non-secure and privilege access allowed
2479  *  0b10..Secure and non-privilege user access allowed
2480  *  0b11..Secure and privilege user access allowed
2481  */
2482 #define AHBSC_RAMD_MEM_RULE_RULE0(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMD_MEM_RULE_RULE0_SHIFT)) & AHBSC_RAMD_MEM_RULE_RULE0_MASK)
2483 
2484 #define AHBSC_RAMD_MEM_RULE_RULE1_MASK           (0x30U)
2485 #define AHBSC_RAMD_MEM_RULE_RULE1_SHIFT          (4U)
2486 /*! RULE1 - Rule 1
2487  *  0b00..Non-secure and non-privilege user access allowed
2488  *  0b01..Non-secure and privilege access allowed
2489  *  0b10..Secure and non-privilege user access allowed
2490  *  0b11..Secure and privilege user access allowed
2491  */
2492 #define AHBSC_RAMD_MEM_RULE_RULE1(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMD_MEM_RULE_RULE1_SHIFT)) & AHBSC_RAMD_MEM_RULE_RULE1_MASK)
2493 
2494 #define AHBSC_RAMD_MEM_RULE_RULE2_MASK           (0x300U)
2495 #define AHBSC_RAMD_MEM_RULE_RULE2_SHIFT          (8U)
2496 /*! RULE2 - Rule 2
2497  *  0b00..Non-secure and non-privilege user access allowed
2498  *  0b01..Non-secure and privilege access allowed
2499  *  0b10..Secure and non-privilege user access allowed
2500  *  0b11..Secure and privilege user access allowed
2501  */
2502 #define AHBSC_RAMD_MEM_RULE_RULE2(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMD_MEM_RULE_RULE2_SHIFT)) & AHBSC_RAMD_MEM_RULE_RULE2_MASK)
2503 
2504 #define AHBSC_RAMD_MEM_RULE_RULE3_MASK           (0x3000U)
2505 #define AHBSC_RAMD_MEM_RULE_RULE3_SHIFT          (12U)
2506 /*! RULE3 - Rule 3
2507  *  0b00..Non-secure and non-privilege user access allowed
2508  *  0b01..Non-secure and privilege access allowed
2509  *  0b10..Secure and non-privilege user access allowed
2510  *  0b11..Secure and privilege user access allowed
2511  */
2512 #define AHBSC_RAMD_MEM_RULE_RULE3(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMD_MEM_RULE_RULE3_SHIFT)) & AHBSC_RAMD_MEM_RULE_RULE3_MASK)
2513 
2514 #define AHBSC_RAMD_MEM_RULE_RULE4_MASK           (0x30000U)
2515 #define AHBSC_RAMD_MEM_RULE_RULE4_SHIFT          (16U)
2516 /*! RULE4 - Rule 4
2517  *  0b00..Non-secure and non-privilege user access allowed
2518  *  0b01..Non-secure and privilege access allowed
2519  *  0b10..Secure and non-privilege user access allowed
2520  *  0b11..Secure and privilege user access allowed
2521  */
2522 #define AHBSC_RAMD_MEM_RULE_RULE4(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMD_MEM_RULE_RULE4_SHIFT)) & AHBSC_RAMD_MEM_RULE_RULE4_MASK)
2523 
2524 #define AHBSC_RAMD_MEM_RULE_RULE5_MASK           (0x300000U)
2525 #define AHBSC_RAMD_MEM_RULE_RULE5_SHIFT          (20U)
2526 /*! RULE5 - Rule 5
2527  *  0b00..Non-secure and non-privilege user access allowed
2528  *  0b01..Non-secure and privilege access allowed
2529  *  0b10..Secure and non-privilege user access allowed
2530  *  0b11..Secure and privilege user access allowed
2531  */
2532 #define AHBSC_RAMD_MEM_RULE_RULE5(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMD_MEM_RULE_RULE5_SHIFT)) & AHBSC_RAMD_MEM_RULE_RULE5_MASK)
2533 
2534 #define AHBSC_RAMD_MEM_RULE_RULE6_MASK           (0x3000000U)
2535 #define AHBSC_RAMD_MEM_RULE_RULE6_SHIFT          (24U)
2536 /*! RULE6 - Rule 6
2537  *  0b00..Non-secure and non-privilege user access allowed
2538  *  0b01..Non-secure and privilege access allowed
2539  *  0b10..Secure and non-privilege user access allowed
2540  *  0b11..Secure and privilege user access allowed
2541  */
2542 #define AHBSC_RAMD_MEM_RULE_RULE6(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMD_MEM_RULE_RULE6_SHIFT)) & AHBSC_RAMD_MEM_RULE_RULE6_MASK)
2543 
2544 #define AHBSC_RAMD_MEM_RULE_RULE7_MASK           (0x30000000U)
2545 #define AHBSC_RAMD_MEM_RULE_RULE7_SHIFT          (28U)
2546 /*! RULE7 - Rule 7
2547  *  0b00..Non-secure and non-privilege user access allowed
2548  *  0b01..Non-secure and privilege access allowed
2549  *  0b10..Secure and non-privilege user access allowed
2550  *  0b11..Secure and privilege user access allowed
2551  */
2552 #define AHBSC_RAMD_MEM_RULE_RULE7(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMD_MEM_RULE_RULE7_SHIFT)) & AHBSC_RAMD_MEM_RULE_RULE7_MASK)
2553 /*! @} */
2554 
2555 /* The count of AHBSC_RAMD_MEM_RULE */
2556 #define AHBSC_RAMD_MEM_RULE_COUNT                (2U)
2557 
2558 /*! @name RAME_MEM_RULE - RAME Memory Rule */
2559 /*! @{ */
2560 
2561 #define AHBSC_RAME_MEM_RULE_RULE0_MASK           (0x3U)
2562 #define AHBSC_RAME_MEM_RULE_RULE0_SHIFT          (0U)
2563 /*! RULE0 - Rule 0
2564  *  0b00..Non-secure and non-privilege user access allowed
2565  *  0b01..Non-secure and privilege access allowed
2566  *  0b10..Secure and non-privilege user access allowed
2567  *  0b11..Secure and privilege user access allowed
2568  */
2569 #define AHBSC_RAME_MEM_RULE_RULE0(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC_RAME_MEM_RULE_RULE0_SHIFT)) & AHBSC_RAME_MEM_RULE_RULE0_MASK)
2570 
2571 #define AHBSC_RAME_MEM_RULE_RULE1_MASK           (0x30U)
2572 #define AHBSC_RAME_MEM_RULE_RULE1_SHIFT          (4U)
2573 /*! RULE1 - Rule 1
2574  *  0b00..Non-secure and non-privilege user access allowed
2575  *  0b01..Non-secure and privilege access allowed
2576  *  0b10..Secure and non-privilege user access allowed
2577  *  0b11..Secure and privilege user access allowed
2578  */
2579 #define AHBSC_RAME_MEM_RULE_RULE1(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC_RAME_MEM_RULE_RULE1_SHIFT)) & AHBSC_RAME_MEM_RULE_RULE1_MASK)
2580 
2581 #define AHBSC_RAME_MEM_RULE_RULE2_MASK           (0x300U)
2582 #define AHBSC_RAME_MEM_RULE_RULE2_SHIFT          (8U)
2583 /*! RULE2 - Rule 2
2584  *  0b00..Non-secure and non-privilege user access allowed
2585  *  0b01..Non-secure and privilege access allowed
2586  *  0b10..Secure and non-privilege user access allowed
2587  *  0b11..Secure and privilege user access allowed
2588  */
2589 #define AHBSC_RAME_MEM_RULE_RULE2(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC_RAME_MEM_RULE_RULE2_SHIFT)) & AHBSC_RAME_MEM_RULE_RULE2_MASK)
2590 
2591 #define AHBSC_RAME_MEM_RULE_RULE3_MASK           (0x3000U)
2592 #define AHBSC_RAME_MEM_RULE_RULE3_SHIFT          (12U)
2593 /*! RULE3 - Rule 3
2594  *  0b00..Non-secure and non-privilege user access allowed
2595  *  0b01..Non-secure and privilege access allowed
2596  *  0b10..Secure and non-privilege user access allowed
2597  *  0b11..Secure and privilege user access allowed
2598  */
2599 #define AHBSC_RAME_MEM_RULE_RULE3(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC_RAME_MEM_RULE_RULE3_SHIFT)) & AHBSC_RAME_MEM_RULE_RULE3_MASK)
2600 
2601 #define AHBSC_RAME_MEM_RULE_RULE4_MASK           (0x30000U)
2602 #define AHBSC_RAME_MEM_RULE_RULE4_SHIFT          (16U)
2603 /*! RULE4 - Rule 4
2604  *  0b00..Non-secure and non-privilege user access allowed
2605  *  0b01..Non-secure and privilege access allowed
2606  *  0b10..Secure and non-privilege user access allowed
2607  *  0b11..Secure and privilege user access allowed
2608  */
2609 #define AHBSC_RAME_MEM_RULE_RULE4(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC_RAME_MEM_RULE_RULE4_SHIFT)) & AHBSC_RAME_MEM_RULE_RULE4_MASK)
2610 
2611 #define AHBSC_RAME_MEM_RULE_RULE5_MASK           (0x300000U)
2612 #define AHBSC_RAME_MEM_RULE_RULE5_SHIFT          (20U)
2613 /*! RULE5 - Rule 5
2614  *  0b00..Non-secure and non-privilege user access allowed
2615  *  0b01..Non-secure and privilege access allowed
2616  *  0b10..Secure and non-privilege user access allowed
2617  *  0b11..Secure and privilege user access allowed
2618  */
2619 #define AHBSC_RAME_MEM_RULE_RULE5(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC_RAME_MEM_RULE_RULE5_SHIFT)) & AHBSC_RAME_MEM_RULE_RULE5_MASK)
2620 
2621 #define AHBSC_RAME_MEM_RULE_RULE6_MASK           (0x3000000U)
2622 #define AHBSC_RAME_MEM_RULE_RULE6_SHIFT          (24U)
2623 /*! RULE6 - Rule 6
2624  *  0b00..Non-secure and non-privilege user access allowed
2625  *  0b01..Non-secure and privilege access allowed
2626  *  0b10..Secure and non-privilege user access allowed
2627  *  0b11..Secure and privilege user access allowed
2628  */
2629 #define AHBSC_RAME_MEM_RULE_RULE6(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC_RAME_MEM_RULE_RULE6_SHIFT)) & AHBSC_RAME_MEM_RULE_RULE6_MASK)
2630 
2631 #define AHBSC_RAME_MEM_RULE_RULE7_MASK           (0x30000000U)
2632 #define AHBSC_RAME_MEM_RULE_RULE7_SHIFT          (28U)
2633 /*! RULE7 - Rule 7
2634  *  0b00..Non-secure and non-privilege user access allowed
2635  *  0b01..Non-secure and privilege access allowed
2636  *  0b10..Secure and non-privilege user access allowed
2637  *  0b11..Secure and privilege user access allowed
2638  */
2639 #define AHBSC_RAME_MEM_RULE_RULE7(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC_RAME_MEM_RULE_RULE7_SHIFT)) & AHBSC_RAME_MEM_RULE_RULE7_MASK)
2640 /*! @} */
2641 
2642 /* The count of AHBSC_RAME_MEM_RULE */
2643 #define AHBSC_RAME_MEM_RULE_COUNT                (2U)
2644 
2645 /*! @name RAMF_MEM_RULE - RAMF Memory Rule */
2646 /*! @{ */
2647 
2648 #define AHBSC_RAMF_MEM_RULE_RULE0_MASK           (0x3U)
2649 #define AHBSC_RAMF_MEM_RULE_RULE0_SHIFT          (0U)
2650 /*! RULE0 - Rule 0
2651  *  0b00..Non-secure and non-privilege user access allowed
2652  *  0b01..Non-secure and privilege access allowed
2653  *  0b10..Secure and non-privilege user access allowed
2654  *  0b11..Secure and privilege user access allowed
2655  */
2656 #define AHBSC_RAMF_MEM_RULE_RULE0(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMF_MEM_RULE_RULE0_SHIFT)) & AHBSC_RAMF_MEM_RULE_RULE0_MASK)
2657 
2658 #define AHBSC_RAMF_MEM_RULE_RULE1_MASK           (0x30U)
2659 #define AHBSC_RAMF_MEM_RULE_RULE1_SHIFT          (4U)
2660 /*! RULE1 - Rule 1
2661  *  0b00..Non-secure and non-privilege user access allowed
2662  *  0b01..Non-secure and privilege access allowed
2663  *  0b10..Secure and non-privilege user access allowed
2664  *  0b11..Secure and privilege user access allowed
2665  */
2666 #define AHBSC_RAMF_MEM_RULE_RULE1(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMF_MEM_RULE_RULE1_SHIFT)) & AHBSC_RAMF_MEM_RULE_RULE1_MASK)
2667 
2668 #define AHBSC_RAMF_MEM_RULE_RULE2_MASK           (0x300U)
2669 #define AHBSC_RAMF_MEM_RULE_RULE2_SHIFT          (8U)
2670 /*! RULE2 - Rule 2
2671  *  0b00..Non-secure and non-privilege user access allowed
2672  *  0b01..Non-secure and privilege access allowed
2673  *  0b10..Secure and non-privilege user access allowed
2674  *  0b11..Secure and privilege user access allowed
2675  */
2676 #define AHBSC_RAMF_MEM_RULE_RULE2(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMF_MEM_RULE_RULE2_SHIFT)) & AHBSC_RAMF_MEM_RULE_RULE2_MASK)
2677 
2678 #define AHBSC_RAMF_MEM_RULE_RULE3_MASK           (0x3000U)
2679 #define AHBSC_RAMF_MEM_RULE_RULE3_SHIFT          (12U)
2680 /*! RULE3 - Rule 3
2681  *  0b00..Non-secure and non-privilege user access allowed
2682  *  0b01..Non-secure and privilege access allowed
2683  *  0b10..Secure and non-privilege user access allowed
2684  *  0b11..Secure and privilege user access allowed
2685  */
2686 #define AHBSC_RAMF_MEM_RULE_RULE3(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMF_MEM_RULE_RULE3_SHIFT)) & AHBSC_RAMF_MEM_RULE_RULE3_MASK)
2687 
2688 #define AHBSC_RAMF_MEM_RULE_RULE4_MASK           (0x30000U)
2689 #define AHBSC_RAMF_MEM_RULE_RULE4_SHIFT          (16U)
2690 /*! RULE4 - Rule 4
2691  *  0b00..Non-secure and non-privilege user access allowed
2692  *  0b01..Non-secure and privilege access allowed
2693  *  0b10..Secure and non-privilege user access allowed
2694  *  0b11..Secure and privilege user access allowed
2695  */
2696 #define AHBSC_RAMF_MEM_RULE_RULE4(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMF_MEM_RULE_RULE4_SHIFT)) & AHBSC_RAMF_MEM_RULE_RULE4_MASK)
2697 
2698 #define AHBSC_RAMF_MEM_RULE_RULE5_MASK           (0x300000U)
2699 #define AHBSC_RAMF_MEM_RULE_RULE5_SHIFT          (20U)
2700 /*! RULE5 - Rule 5
2701  *  0b00..Non-secure and non-privilege user access allowed
2702  *  0b01..Non-secure and privilege access allowed
2703  *  0b10..Secure and non-privilege user access allowed
2704  *  0b11..Secure and privilege user access allowed
2705  */
2706 #define AHBSC_RAMF_MEM_RULE_RULE5(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMF_MEM_RULE_RULE5_SHIFT)) & AHBSC_RAMF_MEM_RULE_RULE5_MASK)
2707 
2708 #define AHBSC_RAMF_MEM_RULE_RULE6_MASK           (0x3000000U)
2709 #define AHBSC_RAMF_MEM_RULE_RULE6_SHIFT          (24U)
2710 /*! RULE6 - Rule 6
2711  *  0b00..Non-secure and non-privilege user access allowed
2712  *  0b01..Non-secure and privilege access allowed
2713  *  0b10..Secure and non-privilege user access allowed
2714  *  0b11..Secure and privilege user access allowed
2715  */
2716 #define AHBSC_RAMF_MEM_RULE_RULE6(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMF_MEM_RULE_RULE6_SHIFT)) & AHBSC_RAMF_MEM_RULE_RULE6_MASK)
2717 
2718 #define AHBSC_RAMF_MEM_RULE_RULE7_MASK           (0x30000000U)
2719 #define AHBSC_RAMF_MEM_RULE_RULE7_SHIFT          (28U)
2720 /*! RULE7 - Rule 7
2721  *  0b00..Non-secure and non-privilege user access allowed
2722  *  0b01..Non-secure and privilege access allowed
2723  *  0b10..Secure and non-privilege user access allowed
2724  *  0b11..Secure and privilege user access allowed
2725  */
2726 #define AHBSC_RAMF_MEM_RULE_RULE7(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMF_MEM_RULE_RULE7_SHIFT)) & AHBSC_RAMF_MEM_RULE_RULE7_MASK)
2727 /*! @} */
2728 
2729 /* The count of AHBSC_RAMF_MEM_RULE */
2730 #define AHBSC_RAMF_MEM_RULE_COUNT                (2U)
2731 
2732 /*! @name RAMG_MEM_RULE - RAMG Memory Rule */
2733 /*! @{ */
2734 
2735 #define AHBSC_RAMG_MEM_RULE_RULE0_MASK           (0x3U)
2736 #define AHBSC_RAMG_MEM_RULE_RULE0_SHIFT          (0U)
2737 /*! RULE0 - Rule 0
2738  *  0b00..Non-secure and non-privilege user access allowed
2739  *  0b01..Non-secure and privilege access allowed
2740  *  0b10..Secure and non-privilege user access allowed
2741  *  0b11..Secure and privilege user access allowed
2742  */
2743 #define AHBSC_RAMG_MEM_RULE_RULE0(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMG_MEM_RULE_RULE0_SHIFT)) & AHBSC_RAMG_MEM_RULE_RULE0_MASK)
2744 
2745 #define AHBSC_RAMG_MEM_RULE_RULE1_MASK           (0x30U)
2746 #define AHBSC_RAMG_MEM_RULE_RULE1_SHIFT          (4U)
2747 /*! RULE1 - Rule 1
2748  *  0b00..Non-secure and non-privilege user access allowed
2749  *  0b01..Non-secure and privilege access allowed
2750  *  0b10..Secure and non-privilege user access allowed
2751  *  0b11..Secure and privilege user access allowed
2752  */
2753 #define AHBSC_RAMG_MEM_RULE_RULE1(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMG_MEM_RULE_RULE1_SHIFT)) & AHBSC_RAMG_MEM_RULE_RULE1_MASK)
2754 
2755 #define AHBSC_RAMG_MEM_RULE_RULE2_MASK           (0x300U)
2756 #define AHBSC_RAMG_MEM_RULE_RULE2_SHIFT          (8U)
2757 /*! RULE2 - Rule 2
2758  *  0b00..Non-secure and non-privilege user access allowed
2759  *  0b01..Non-secure and privilege access allowed
2760  *  0b10..Secure and non-privilege user access allowed
2761  *  0b11..Secure and privilege user access allowed
2762  */
2763 #define AHBSC_RAMG_MEM_RULE_RULE2(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMG_MEM_RULE_RULE2_SHIFT)) & AHBSC_RAMG_MEM_RULE_RULE2_MASK)
2764 
2765 #define AHBSC_RAMG_MEM_RULE_RULE3_MASK           (0x3000U)
2766 #define AHBSC_RAMG_MEM_RULE_RULE3_SHIFT          (12U)
2767 /*! RULE3 - Rule 3
2768  *  0b00..Non-secure and non-privilege user access allowed
2769  *  0b01..Non-secure and privilege access allowed
2770  *  0b10..Secure and non-privilege user access allowed
2771  *  0b11..Secure and privilege user access allowed
2772  */
2773 #define AHBSC_RAMG_MEM_RULE_RULE3(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMG_MEM_RULE_RULE3_SHIFT)) & AHBSC_RAMG_MEM_RULE_RULE3_MASK)
2774 
2775 #define AHBSC_RAMG_MEM_RULE_RULE4_MASK           (0x30000U)
2776 #define AHBSC_RAMG_MEM_RULE_RULE4_SHIFT          (16U)
2777 /*! RULE4 - Rule 4
2778  *  0b00..Non-secure and non-privilege user access allowed
2779  *  0b01..Non-secure and privilege access allowed
2780  *  0b10..Secure and non-privilege user access allowed
2781  *  0b11..Secure and privilege user access allowed
2782  */
2783 #define AHBSC_RAMG_MEM_RULE_RULE4(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMG_MEM_RULE_RULE4_SHIFT)) & AHBSC_RAMG_MEM_RULE_RULE4_MASK)
2784 
2785 #define AHBSC_RAMG_MEM_RULE_RULE5_MASK           (0x300000U)
2786 #define AHBSC_RAMG_MEM_RULE_RULE5_SHIFT          (20U)
2787 /*! RULE5 - Rule 5
2788  *  0b00..Non-secure and non-privilege user access allowed
2789  *  0b01..Non-secure and privilege access allowed
2790  *  0b10..Secure and non-privilege user access allowed
2791  *  0b11..Secure and privilege user access allowed
2792  */
2793 #define AHBSC_RAMG_MEM_RULE_RULE5(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMG_MEM_RULE_RULE5_SHIFT)) & AHBSC_RAMG_MEM_RULE_RULE5_MASK)
2794 
2795 #define AHBSC_RAMG_MEM_RULE_RULE6_MASK           (0x3000000U)
2796 #define AHBSC_RAMG_MEM_RULE_RULE6_SHIFT          (24U)
2797 /*! RULE6 - Rule 6
2798  *  0b00..Non-secure and non-privilege user access allowed
2799  *  0b01..Non-secure and privilege access allowed
2800  *  0b10..Secure and non-privilege user access allowed
2801  *  0b11..Secure and privilege user access allowed
2802  */
2803 #define AHBSC_RAMG_MEM_RULE_RULE6(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMG_MEM_RULE_RULE6_SHIFT)) & AHBSC_RAMG_MEM_RULE_RULE6_MASK)
2804 
2805 #define AHBSC_RAMG_MEM_RULE_RULE7_MASK           (0x30000000U)
2806 #define AHBSC_RAMG_MEM_RULE_RULE7_SHIFT          (28U)
2807 /*! RULE7 - Rule 7
2808  *  0b00..Non-secure and non-privilege user access allowed
2809  *  0b01..Non-secure and privilege access allowed
2810  *  0b10..Secure and non-privilege user access allowed
2811  *  0b11..Secure and privilege user access allowed
2812  */
2813 #define AHBSC_RAMG_MEM_RULE_RULE7(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMG_MEM_RULE_RULE7_SHIFT)) & AHBSC_RAMG_MEM_RULE_RULE7_MASK)
2814 /*! @} */
2815 
2816 /* The count of AHBSC_RAMG_MEM_RULE */
2817 #define AHBSC_RAMG_MEM_RULE_COUNT                (2U)
2818 
2819 /*! @name RAMH_MEM_RULE - RAMH Memory Rule */
2820 /*! @{ */
2821 
2822 #define AHBSC_RAMH_MEM_RULE_RULE0_MASK           (0x3U)
2823 #define AHBSC_RAMH_MEM_RULE_RULE0_SHIFT          (0U)
2824 /*! RULE0 - Rule 0
2825  *  0b00..Non-secure and non-privilege user access allowed
2826  *  0b01..Non-secure and privilege access allowed
2827  *  0b10..Secure and non-privilege user access allowed
2828  *  0b11..Secure and privilege user access allowed
2829  */
2830 #define AHBSC_RAMH_MEM_RULE_RULE0(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMH_MEM_RULE_RULE0_SHIFT)) & AHBSC_RAMH_MEM_RULE_RULE0_MASK)
2831 
2832 #define AHBSC_RAMH_MEM_RULE_RULE1_MASK           (0x30U)
2833 #define AHBSC_RAMH_MEM_RULE_RULE1_SHIFT          (4U)
2834 /*! RULE1 - Rule 1
2835  *  0b00..Non-secure and non-privilege user access allowed
2836  *  0b01..Non-secure and privilege access allowed
2837  *  0b10..Secure and non-privilege user access allowed
2838  *  0b11..Secure and privilege user access allowed
2839  */
2840 #define AHBSC_RAMH_MEM_RULE_RULE1(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMH_MEM_RULE_RULE1_SHIFT)) & AHBSC_RAMH_MEM_RULE_RULE1_MASK)
2841 
2842 #define AHBSC_RAMH_MEM_RULE_RULE2_MASK           (0x300U)
2843 #define AHBSC_RAMH_MEM_RULE_RULE2_SHIFT          (8U)
2844 /*! RULE2 - Rule 2
2845  *  0b00..Non-secure and non-privilege user access allowed
2846  *  0b01..Non-secure and privilege access allowed
2847  *  0b10..Secure and non-privilege user access allowed
2848  *  0b11..Secure and privilege user access allowed
2849  */
2850 #define AHBSC_RAMH_MEM_RULE_RULE2(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMH_MEM_RULE_RULE2_SHIFT)) & AHBSC_RAMH_MEM_RULE_RULE2_MASK)
2851 
2852 #define AHBSC_RAMH_MEM_RULE_RULE3_MASK           (0x3000U)
2853 #define AHBSC_RAMH_MEM_RULE_RULE3_SHIFT          (12U)
2854 /*! RULE3 - Rule 3
2855  *  0b00..Non-secure and non-privilege user access allowed
2856  *  0b01..Non-secure and privilege access allowed
2857  *  0b10..Secure and non-privilege user access allowed
2858  *  0b11..Secure and privilege user access allowed
2859  */
2860 #define AHBSC_RAMH_MEM_RULE_RULE3(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMH_MEM_RULE_RULE3_SHIFT)) & AHBSC_RAMH_MEM_RULE_RULE3_MASK)
2861 
2862 #define AHBSC_RAMH_MEM_RULE_RULE4_MASK           (0x30000U)
2863 #define AHBSC_RAMH_MEM_RULE_RULE4_SHIFT          (16U)
2864 /*! RULE4 - Rule 4
2865  *  0b00..Non-secure and non-privilege user access allowed
2866  *  0b01..Non-secure and privilege access allowed
2867  *  0b10..Secure and non-privilege user access allowed
2868  *  0b11..Secure and privilege user access allowed
2869  */
2870 #define AHBSC_RAMH_MEM_RULE_RULE4(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMH_MEM_RULE_RULE4_SHIFT)) & AHBSC_RAMH_MEM_RULE_RULE4_MASK)
2871 
2872 #define AHBSC_RAMH_MEM_RULE_RULE5_MASK           (0x300000U)
2873 #define AHBSC_RAMH_MEM_RULE_RULE5_SHIFT          (20U)
2874 /*! RULE5 - Rule 5
2875  *  0b00..Non-secure and non-privilege user access allowed
2876  *  0b01..Non-secure and privilege access allowed
2877  *  0b10..Secure and non-privilege user access allowed
2878  *  0b11..Secure and privilege user access allowed
2879  */
2880 #define AHBSC_RAMH_MEM_RULE_RULE5(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMH_MEM_RULE_RULE5_SHIFT)) & AHBSC_RAMH_MEM_RULE_RULE5_MASK)
2881 
2882 #define AHBSC_RAMH_MEM_RULE_RULE6_MASK           (0x3000000U)
2883 #define AHBSC_RAMH_MEM_RULE_RULE6_SHIFT          (24U)
2884 /*! RULE6 - Rule 6
2885  *  0b00..Non-secure and non-privilege user access allowed
2886  *  0b01..Non-secure and privilege access allowed
2887  *  0b10..Secure and non-privilege user access allowed
2888  *  0b11..Secure and privilege user access allowed
2889  */
2890 #define AHBSC_RAMH_MEM_RULE_RULE6(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMH_MEM_RULE_RULE6_SHIFT)) & AHBSC_RAMH_MEM_RULE_RULE6_MASK)
2891 
2892 #define AHBSC_RAMH_MEM_RULE_RULE7_MASK           (0x30000000U)
2893 #define AHBSC_RAMH_MEM_RULE_RULE7_SHIFT          (28U)
2894 /*! RULE7 - Rule 7
2895  *  0b00..Non-secure and non-privilege user access allowed
2896  *  0b01..Non-secure and privilege access allowed
2897  *  0b10..Secure and non-privilege user access allowed
2898  *  0b11..Secure and privilege user access allowed
2899  */
2900 #define AHBSC_RAMH_MEM_RULE_RULE7(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMH_MEM_RULE_RULE7_SHIFT)) & AHBSC_RAMH_MEM_RULE_RULE7_MASK)
2901 /*! @} */
2902 
2903 /*! @name APB_PERIPHERAL_GROUP0_MEM_RULE0 - APB Bridge Group 0 Memory Rule 0 */
2904 /*! @{ */
2905 
2906 #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_SYSCON_MASK (0x3U)
2907 #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_SYSCON_SHIFT (0U)
2908 /*! SYSCON - SYSCON
2909  *  0b00..Non-secure and non-privilege user access allowed
2910  *  0b01..Non-secure and privilege access allowed
2911  *  0b10..Secure and non-privilege user access allowed
2912  *  0b11..Secure and privilege user access allowed
2913  */
2914 #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_SYSCON(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_SYSCON_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_SYSCON_MASK)
2915 
2916 #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_PINT0_MASK (0x30000U)
2917 #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_PINT0_SHIFT (16U)
2918 /*! PINT0 - PINT0
2919  *  0b00..Non-secure and non-privilege user access allowed
2920  *  0b01..Non-secure and privilege access allowed
2921  *  0b10..Secure and non-privilege user access allowed
2922  *  0b11..Secure and privilege user access allowed
2923  */
2924 #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_PINT0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_PINT0_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_PINT0_MASK)
2925 
2926 #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_INPUTMUX_MASK (0x3000000U)
2927 #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_INPUTMUX_SHIFT (24U)
2928 /*! INPUTMUX - INPUTMUX
2929  *  0b00..Non-secure and non-privilege user access allowed
2930  *  0b01..Non-secure and privilege access allowed
2931  *  0b10..Secure and non-privilege user access allowed
2932  *  0b11..Secure and privilege user access allowed
2933  */
2934 #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_INPUTMUX(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_INPUTMUX_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_INPUTMUX_MASK)
2935 /*! @} */
2936 
2937 /*! @name APB_PERIPHERAL_GROUP0_MEM_RULE1 - APB Bridge Group 0 Memory Rule 1 */
2938 /*! @{ */
2939 
2940 #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER0_MASK (0x30000U)
2941 #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER0_SHIFT (16U)
2942 /*! CTIMER0 - CTIMER0
2943  *  0b00..Non-secure and non-privilege user access allowed
2944  *  0b01..Non-secure and privilege access allowed
2945  *  0b10..Secure and non-privilege user access allowed
2946  *  0b11..Secure and privilege user access allowed
2947  */
2948 #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER0_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER0_MASK)
2949 
2950 #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER1_MASK (0x300000U)
2951 #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER1_SHIFT (20U)
2952 /*! CTIMER1 - CTIMER1
2953  *  0b00..Non-secure and non-privilege user access allowed
2954  *  0b01..Non-secure and privilege access allowed
2955  *  0b10..Secure and non-privilege user access allowed
2956  *  0b11..Secure and privilege user access allowed
2957  */
2958 #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER1_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER1_MASK)
2959 
2960 #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER2_MASK (0x3000000U)
2961 #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER2_SHIFT (24U)
2962 /*! CTIMER2 - CTIMER2
2963  *  0b00..Non-secure and non-privilege user access allowed
2964  *  0b01..Non-secure and privilege access allowed
2965  *  0b10..Secure and non-privilege user access allowed
2966  *  0b11..Secure and privilege user access allowed
2967  */
2968 #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER2_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER2_MASK)
2969 
2970 #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER3_MASK (0x30000000U)
2971 #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER3_SHIFT (28U)
2972 /*! CTIMER3 - CTIMER3
2973  *  0b00..Non-secure and non-privilege user access allowed
2974  *  0b01..Non-secure and privilege access allowed
2975  *  0b10..Secure and non-privilege user access allowed
2976  *  0b11..Secure and privilege user access allowed
2977  */
2978 #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER3_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER3_MASK)
2979 /*! @} */
2980 
2981 /*! @name APB_PERIPHERAL_GROUP0_MEM_RULE2 - APB Bridge Group 0 Rule 2 */
2982 /*! @{ */
2983 
2984 #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_CTIMER4_MASK (0x3U)
2985 #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_CTIMER4_SHIFT (0U)
2986 /*! CTIMER4 - CTIMER4
2987  *  0b00..Non-secure and non-privilege user access allowed
2988  *  0b01..Non-secure and privilege access allowed
2989  *  0b10..Secure and non-privilege user access allowed
2990  *  0b11..Secure and privilege user access allowed
2991  */
2992 #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_CTIMER4_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_CTIMER4_MASK)
2993 
2994 #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_FREQME0_MASK (0x30U)
2995 #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_FREQME0_SHIFT (4U)
2996 /*! FREQME0 - FREQME0
2997  *  0b00..Non-secure and non-privilege user access allowed
2998  *  0b01..Non-secure and privilege access allowed
2999  *  0b10..Secure and non-privilege user access allowed
3000  *  0b11..Secure and privilege user access allowed
3001  */
3002 #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_FREQME0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_FREQME0_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_FREQME0_MASK)
3003 
3004 #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_UTCIK0_MASK (0x300U)
3005 #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_UTCIK0_SHIFT (8U)
3006 /*! UTCIK0 - UTCIK0
3007  *  0b00..Non-secure and non-privilege user access allowed
3008  *  0b01..Non-secure and privilege access allowed
3009  *  0b10..Secure and non-privilege user access allowed
3010  *  0b11..Secure and privilege user access allowed
3011  */
3012 #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_UTCIK0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_UTCIK0_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_UTCIK0_MASK)
3013 
3014 #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_MRT0_MASK (0x3000U)
3015 #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_MRT0_SHIFT (12U)
3016 /*! MRT0 - MRT0
3017  *  0b00..Non-secure and non-privilege user access allowed
3018  *  0b01..Non-secure and privilege access allowed
3019  *  0b10..Secure and non-privilege user access allowed
3020  *  0b11..Secure and privilege user access allowed
3021  */
3022 #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_MRT0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_MRT0_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_MRT0_MASK)
3023 
3024 #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_OSTIMER0_MASK (0x30000U)
3025 #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_OSTIMER0_SHIFT (16U)
3026 /*! OSTIMER0 - OSTIMER0
3027  *  0b00..Non-secure and non-privilege user access allowed
3028  *  0b01..Non-secure and privilege access allowed
3029  *  0b10..Secure and non-privilege user access allowed
3030  *  0b11..Secure and privilege user access allowed
3031  */
3032 #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_OSTIMER0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_OSTIMER0_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_OSTIMER0_MASK)
3033 
3034 #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_WWDT0_MASK (0x3000000U)
3035 #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_WWDT0_SHIFT (24U)
3036 /*! WWDT0 - WWDT0
3037  *  0b00..Non-secure and non-privilege user access allowed
3038  *  0b01..Non-secure and privilege access allowed
3039  *  0b10..Secure and non-privilege user access allowed
3040  *  0b11..Secure and privilege user access allowed
3041  */
3042 #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_WWDT0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_WWDT0_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_WWDT0_MASK)
3043 
3044 #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_WWDT1_MASK (0x30000000U)
3045 #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_WWDT1_SHIFT (28U)
3046 /*! WWDT1 - WWDT1
3047  *  0b00..Non-secure and non-privilege user access allowed
3048  *  0b01..Non-secure and privilege access allowed
3049  *  0b10..Secure and non-privilege user access allowed
3050  *  0b11..Secure and privilege user access allowed
3051  */
3052 #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_WWDT1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_WWDT1_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_WWDT1_MASK)
3053 /*! @} */
3054 
3055 /*! @name APB_PERIPHERAL_GROUP0_MEM_RULE3 - APB Bridge Group 0 Memory Rule 3 */
3056 /*! @{ */
3057 
3058 #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE3_CACHE64_POLSEL0_MASK (0x3000U)
3059 #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE3_CACHE64_POLSEL0_SHIFT (12U)
3060 /*! CACHE64_POLSEL0 - CACHE64_POLSEL0
3061  *  0b00..Non-secure and non-privilege user access allowed
3062  *  0b01..Non-secure and privilege access allowed
3063  *  0b10..Secure and non-privilege user access allowed
3064  *  0b11..Secure and privilege user access allowed
3065  */
3066 #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE3_CACHE64_POLSEL0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE3_CACHE64_POLSEL0_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE3_CACHE64_POLSEL0_MASK)
3067 /*! @} */
3068 
3069 /*! @name APB_PERIPHERAL_GROUP1_MEM_RULE0 - APB Bridge Group 1 Memory Rule 0 */
3070 /*! @{ */
3071 
3072 #define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_I3C0_MASK (0x30U)
3073 #define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_I3C0_SHIFT (4U)
3074 /*! I3C0 - I3C0
3075  *  0b00..Non-secure and non-privilege user access allowed
3076  *  0b01..Non-secure and privilege access allowed
3077  *  0b10..Secure and non-privilege user access allowed
3078  *  0b11..Secure and privilege user access allowed
3079  */
3080 #define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_I3C0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_I3C0_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_I3C0_MASK)
3081 
3082 #define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_I3C1_MASK (0x300U)
3083 #define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_I3C1_SHIFT (8U)
3084 /*! I3C1 - I3C1
3085  *  0b00..Non-secure and non-privilege user access allowed
3086  *  0b01..Non-secure and privilege access allowed
3087  *  0b10..Secure and non-privilege user access allowed
3088  *  0b11..Secure and privilege user access allowed
3089  */
3090 #define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_I3C1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_I3C1_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_I3C1_MASK)
3091 
3092 #define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_GDET_MASK (0x300000U)
3093 #define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_GDET_SHIFT (20U)
3094 /*! GDET - GDET
3095  *  0b00..Non-secure and non-privilege user access allowed
3096  *  0b01..Non-secure and privilege access allowed
3097  *  0b10..Secure and non-privilege user access allowed
3098  *  0b11..Secure and privilege user access allowed
3099  */
3100 #define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_GDET(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_GDET_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_GDET_MASK)
3101 
3102 #define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_ITRC_MASK (0x3000000U)
3103 #define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_ITRC_SHIFT (24U)
3104 /*! ITRC - ITRC
3105  *  0b00..Non-secure and non-privilege user access allowed
3106  *  0b01..Non-secure and privilege access allowed
3107  *  0b10..Secure and non-privilege user access allowed
3108  *  0b11..Secure and privilege user access allowed
3109  */
3110 #define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_ITRC(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_ITRC_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_ITRC_MASK)
3111 /*! @} */
3112 
3113 /*! @name APB_PERIPHERAL_GROUP1_MEM_RULE1 - APB Bridge Group 1 Memory Rule 1 */
3114 /*! @{ */
3115 
3116 #define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PKC_MASK (0x3000U)
3117 #define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PKC_SHIFT (12U)
3118 /*! PKC - PKC
3119  *  0b00..Non-secure and non-privilege user access allowed
3120  *  0b01..Non-secure and privilege access allowed
3121  *  0b10..Secure and non-privilege user access allowed
3122  *  0b11..Secure and privilege user access allowed
3123  */
3124 #define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PKC(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PKC_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PKC_MASK)
3125 
3126 #define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS0_MASK (0x30000U)
3127 #define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS0_SHIFT (16U)
3128 /*! PUF_ALIAS0 - PUF_ALIAS0
3129  *  0b00..Non-secure and non-privilege user access allowed
3130  *  0b01..Non-secure and privilege access allowed
3131  *  0b10..Secure and non-privilege user access allowed
3132  *  0b11..Secure and privilege user access allowed
3133  */
3134 #define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS0_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS0_MASK)
3135 
3136 #define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS1_MASK (0x300000U)
3137 #define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS1_SHIFT (20U)
3138 /*! PUF_ALIAS1 - PUF_ALIAS1
3139  *  0b00..Non-secure and non-privilege user access allowed
3140  *  0b01..Non-secure and privilege access allowed
3141  *  0b10..Secure and non-privilege user access allowed
3142  *  0b11..Secure and privilege user access allowed
3143  */
3144 #define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS1_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS1_MASK)
3145 
3146 #define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS2_MASK (0x3000000U)
3147 #define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS2_SHIFT (24U)
3148 /*! PUF_ALIAS2 - PUF_ALIAS2
3149  *  0b00..Non-secure and non-privilege user access allowed
3150  *  0b01..Non-secure and privilege access allowed
3151  *  0b10..Secure and non-privilege user access allowed
3152  *  0b11..Secure and privilege user access allowed
3153  */
3154 #define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS2_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS2_MASK)
3155 
3156 #define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS3_MASK (0x30000000U)
3157 #define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS3_SHIFT (28U)
3158 /*! PUF_ALIAS3 - PUF_ALIAS3
3159  *  0b00..Non-secure and non-privilege user access allowed
3160  *  0b01..Non-secure and privilege access allowed
3161  *  0b10..Secure and non-privilege user access allowed
3162  *  0b11..Secure and privilege user access allowed
3163  */
3164 #define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS3_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS3_MASK)
3165 /*! @} */
3166 
3167 /*! @name APB_PERIPHERAL_GROUP1_MEM_RULE2 - APB Bridge Group 1 Memory Rule 2 */
3168 /*! @{ */
3169 
3170 #define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE2_SM3_MASK (0x30U)
3171 #define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE2_SM3_SHIFT (4U)
3172 /*! SM3 - SM3
3173  *  0b00..Non-secure and non-privilege user access allowed
3174  *  0b01..Non-secure and privilege access allowed
3175  *  0b10..Secure and non-privilege user access allowed
3176  *  0b11..Secure and privilege user access allowed
3177  */
3178 #define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE2_SM3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE2_SM3_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE2_SM3_MASK)
3179 
3180 #define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE2_COOLFLUX_MASK (0x300U)
3181 #define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE2_COOLFLUX_SHIFT (8U)
3182 /*! COOLFLUX - COOLFLUX
3183  *  0b00..Non-secure and non-privilege user access allowed
3184  *  0b01..Non-secure and privilege access allowed
3185  *  0b10..Secure and non-privilege user access allowed
3186  *  0b11..Secure and privilege user access allowed
3187  */
3188 #define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE2_COOLFLUX(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE2_COOLFLUX_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE2_COOLFLUX_MASK)
3189 
3190 #define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE2_SMARTDMA_MASK (0x3000U)
3191 #define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE2_SMARTDMA_SHIFT (12U)
3192 /*! SMARTDMA - SmartDMA
3193  *  0b00..Non-secure and non-privilege user access allowed
3194  *  0b01..Non-secure and privilege access allowed
3195  *  0b10..Secure and non-privilege user access allowed
3196  *  0b11..Secure and privilege user access allowed
3197  */
3198 #define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE2_SMARTDMA(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE2_SMARTDMA_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE2_SMARTDMA_MASK)
3199 
3200 #define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE2_PLU_MASK (0x30000U)
3201 #define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE2_PLU_SHIFT (16U)
3202 /*! PLU - PLU
3203  *  0b00..Non-secure and non-privilege user access allowed
3204  *  0b01..Non-secure and privilege access allowed
3205  *  0b10..Secure and non-privilege user access allowed
3206  *  0b11..Secure and privilege user access allowed
3207  */
3208 #define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE2_PLU(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE2_PLU_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE2_PLU_MASK)
3209 /*! @} */
3210 
3211 /*! @name AIPS_BRIDGE_GROUP0_MEM_RULE0 - AIPS Bridge Group 0 Memory Rule 0 */
3212 /*! @{ */
3213 
3214 #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_GPIO5_ALIAS0_MASK (0x3U)
3215 #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_GPIO5_ALIAS0_SHIFT (0U)
3216 /*! GPIO5_ALIAS0 - GPIO5_ALIAS0
3217  *  0b00..Non-secure and non-privilege user access allowed
3218  *  0b01..Non-secure and privilege access allowed
3219  *  0b10..Secure and non-privilege user access allowed
3220  *  0b11..Secure and privilege user access allowed
3221  */
3222 #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_GPIO5_ALIAS0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_GPIO5_ALIAS0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_GPIO5_ALIAS0_MASK)
3223 
3224 #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_GPIO5_ALIAS1_MASK (0x30U)
3225 #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_GPIO5_ALIAS1_SHIFT (4U)
3226 /*! GPIO5_ALIAS1 - GPIO5_ALIAS2
3227  *  0b00..Non-secure and non-privilege user access allowed
3228  *  0b01..Non-secure and privilege access allowed
3229  *  0b10..Secure and non-privilege user access allowed
3230  *  0b11..Secure and privilege user access allowed
3231  */
3232 #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_GPIO5_ALIAS1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_GPIO5_ALIAS1_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_GPIO5_ALIAS1_MASK)
3233 
3234 #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_PORT5_MASK (0x300U)
3235 #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_PORT5_SHIFT (8U)
3236 /*! PORT5 - PORT5
3237  *  0b00..Non-secure and non-privilege user access allowed
3238  *  0b01..Non-secure and privilege access allowed
3239  *  0b10..Secure and non-privilege user access allowed
3240  *  0b11..Secure and privilege user access allowed
3241  */
3242 #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_PORT5(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_PORT5_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_PORT5_MASK)
3243 
3244 #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_FMU0_MASK (0x3000U)
3245 #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_FMU0_SHIFT (12U)
3246 /*! FMU0 - FMU0
3247  *  0b00..Non-secure and non-privilege user access allowed
3248  *  0b01..Non-secure and privilege access allowed
3249  *  0b10..Secure and non-privilege user access allowed
3250  *  0b11..Secure and privilege user access allowed
3251  */
3252 #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_FMU0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_FMU0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_FMU0_MASK)
3253 
3254 #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_SCG0_MASK (0x30000U)
3255 #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_SCG0_SHIFT (16U)
3256 /*! SCG0 - SCG0
3257  *  0b00..Non-secure and non-privilege user access allowed
3258  *  0b01..Non-secure and privilege access allowed
3259  *  0b10..Secure and non-privilege user access allowed
3260  *  0b11..Secure and privilege user access allowed
3261  */
3262 #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_SCG0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_SCG0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_SCG0_MASK)
3263 
3264 #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_SPC0_MASK (0x300000U)
3265 #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_SPC0_SHIFT (20U)
3266 /*! SPC0 - SPC0
3267  *  0b00..Non-secure and non-privilege user access allowed
3268  *  0b01..Non-secure and privilege access allowed
3269  *  0b10..Secure and non-privilege user access allowed
3270  *  0b11..Secure and privilege user access allowed
3271  */
3272 #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_SPC0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_SPC0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_SPC0_MASK)
3273 
3274 #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_WUU0_MASK (0x3000000U)
3275 #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_WUU0_SHIFT (24U)
3276 /*! WUU0 - WUU0
3277  *  0b00..Non-secure and non-privilege user access allowed
3278  *  0b01..Non-secure and privilege access allowed
3279  *  0b10..Secure and non-privilege user access allowed
3280  *  0b11..Secure and privilege user access allowed
3281  */
3282 #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_WUU0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_WUU0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_WUU0_MASK)
3283 
3284 #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_TRO0_MASK (0x30000000U)
3285 #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_TRO0_SHIFT (28U)
3286 /*! TRO0 - TRO0
3287  *  0b00..Non-secure and non-privilege user access allowed
3288  *  0b01..Non-secure and privilege access allowed
3289  *  0b10..Secure and non-privilege user access allowed
3290  *  0b11..Secure and privilege user access allowed
3291  */
3292 #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_TRO0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_TRO0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_TRO0_MASK)
3293 /*! @} */
3294 
3295 /*! @name AIPS_BRIDGE_GROUP0_MEM_RULE1 - AIPS Bridge Group 0 Memory Rule 1 */
3296 /*! @{ */
3297 
3298 #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_LPTMR0_MASK (0x300U)
3299 #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_LPTMR0_SHIFT (8U)
3300 /*! LPTMR0 - LPTMR0
3301  *  0b00..Non-secure and non-privilege user access allowed
3302  *  0b01..Non-secure and privilege access allowed
3303  *  0b10..Secure and non-privilege user access allowed
3304  *  0b11..Secure and privilege user access allowed
3305  */
3306 #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_LPTMR0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_LPTMR0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_LPTMR0_MASK)
3307 
3308 #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_LPTMR1_MASK (0x3000U)
3309 #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_LPTMR1_SHIFT (12U)
3310 /*! LPTMR1 - LPTMR1
3311  *  0b00..Non-secure and non-privilege user access allowed
3312  *  0b01..Non-secure and privilege access allowed
3313  *  0b10..Secure and non-privilege user access allowed
3314  *  0b11..Secure and privilege user access allowed
3315  */
3316 #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_LPTMR1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_LPTMR1_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_LPTMR1_MASK)
3317 
3318 #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_RTC_MASK (0x30000U)
3319 #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_RTC_SHIFT (16U)
3320 /*! RTC - RTC
3321  *  0b00..Non-secure and non-privilege user access allowed
3322  *  0b01..Non-secure and privilege access allowed
3323  *  0b10..Secure and non-privilege user access allowed
3324  *  0b11..Secure and privilege user access allowed
3325  */
3326 #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_RTC(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_RTC_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_RTC_MASK)
3327 
3328 #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_FMU_TEST_MASK (0x3000000U)
3329 #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_FMU_TEST_SHIFT (24U)
3330 /*! FMU_TEST - FMU_TEST
3331  *  0b00..Non-secure and non-privilege user access allowed
3332  *  0b01..Non-secure and privilege access allowed
3333  *  0b10..Secure and non-privilege user access allowed
3334  *  0b11..Secure and privilege user access allowed
3335  */
3336 #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_FMU_TEST(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_FMU_TEST_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_FMU_TEST_MASK)
3337 /*! @} */
3338 
3339 /*! @name AIPS_BRIDGE_GROUP0_MEM_RULE2 - AIPS Bridge Group 0 Memory Rule 2 */
3340 /*! @{ */
3341 
3342 #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_TSI_MASK (0x3U)
3343 #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_TSI_SHIFT (0U)
3344 /*! TSI - TSI
3345  *  0b00..Non-secure and non-privilege user access allowed
3346  *  0b01..Non-secure and privilege access allowed
3347  *  0b10..Secure and non-privilege user access allowed
3348  *  0b11..Secure and privilege user access allowed
3349  */
3350 #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_TSI(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_TSI_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_TSI_MASK)
3351 
3352 #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_CMP0_MASK (0x30U)
3353 #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_CMP0_SHIFT (4U)
3354 /*! CMP0 - CMP0
3355  *  0b00..Non-secure and non-privilege user access allowed
3356  *  0b01..Non-secure and privilege access allowed
3357  *  0b10..Secure and non-privilege user access allowed
3358  *  0b11..Secure and privilege user access allowed
3359  */
3360 #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_CMP0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_CMP0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_CMP0_MASK)
3361 
3362 #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_CMP1_MASK (0x300U)
3363 #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_CMP1_SHIFT (8U)
3364 /*! CMP1 - CMP1
3365  *  0b00..Non-secure and non-privilege user access allowed
3366  *  0b01..Non-secure and privilege access allowed
3367  *  0b10..Secure and non-privilege user access allowed
3368  *  0b11..Secure and privilege user access allowed
3369  */
3370 #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_CMP1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_CMP1_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_CMP1_MASK)
3371 
3372 #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_CMP2_MASK (0x3000U)
3373 #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_CMP2_SHIFT (12U)
3374 /*! CMP2 - CMP2
3375  *  0b00..Non-secure and non-privilege user access allowed
3376  *  0b01..Non-secure and privilege access allowed
3377  *  0b10..Secure and non-privilege user access allowed
3378  *  0b11..Secure and privilege user access allowed
3379  */
3380 #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_CMP2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_CMP2_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_CMP2_MASK)
3381 
3382 #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_MASK (0x30000U)
3383 #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_SHIFT (16U)
3384 /*! ELS - ELS
3385  *  0b00..Non-secure and non-privilege user access allowed
3386  *  0b01..Non-secure and privilege access allowed
3387  *  0b10..Secure and non-privilege user access allowed
3388  *  0b11..Secure and privilege user access allowed
3389  */
3390 #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_MASK)
3391 
3392 #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_ALIAS1_MASK (0x300000U)
3393 #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_ALIAS1_SHIFT (20U)
3394 /*! ELS_ALIAS1 - ELS_ALIAS1
3395  *  0b00..Non-secure and non-privilege user access allowed
3396  *  0b01..Non-secure and privilege access allowed
3397  *  0b10..Secure and non-privilege user access allowed
3398  *  0b11..Secure and privilege user access allowed
3399  */
3400 #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_ALIAS1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_ALIAS1_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_ALIAS1_MASK)
3401 
3402 #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_ALIAS2_MASK (0x3000000U)
3403 #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_ALIAS2_SHIFT (24U)
3404 /*! ELS_ALIAS2 - ELS_ALIAS2
3405  *  0b00..Non-secure and non-privilege user access allowed
3406  *  0b01..Non-secure and privilege access allowed
3407  *  0b10..Secure and non-privilege user access allowed
3408  *  0b11..Secure and privilege user access allowed
3409  */
3410 #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_ALIAS2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_ALIAS2_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_ALIAS2_MASK)
3411 
3412 #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_ALIAS3_MASK (0x30000000U)
3413 #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_ALIAS3_SHIFT (28U)
3414 /*! ELS_ALIAS3 - ELS_ALIAS3
3415  *  0b00..Non-secure and non-privilege user access allowed
3416  *  0b01..Non-secure and privilege access allowed
3417  *  0b10..Secure and non-privilege user access allowed
3418  *  0b11..Secure and privilege user access allowed
3419  */
3420 #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_ALIAS3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_ALIAS3_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_ALIAS3_MASK)
3421 /*! @} */
3422 
3423 /*! @name AIPS_BRIDGE_GROUP0_MEM_RULE3 - AIPS Bridge Group 0 Memory Rule 3 */
3424 /*! @{ */
3425 
3426 #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_DIGTMP_MASK (0x3U)
3427 #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_DIGTMP_SHIFT (0U)
3428 /*! DIGTMP - DIGTMP
3429  *  0b00..Non-secure and non-privilege user access allowed
3430  *  0b01..Non-secure and privilege access allowed
3431  *  0b10..Secure and non-privilege user access allowed
3432  *  0b11..Secure and privilege user access allowed
3433  */
3434 #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_DIGTMP(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_DIGTMP_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_DIGTMP_MASK)
3435 
3436 #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_VBAT_MASK (0x30U)
3437 #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_VBAT_SHIFT (4U)
3438 /*! VBAT - VBAT
3439  *  0b00..Non-secure and non-privilege user access allowed
3440  *  0b01..Non-secure and privilege access allowed
3441  *  0b10..Secure and non-privilege user access allowed
3442  *  0b11..Secure and privilege user access allowed
3443  */
3444 #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_VBAT(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_VBAT_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_VBAT_MASK)
3445 
3446 #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_TRNG_MASK (0x300U)
3447 #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_TRNG_SHIFT (8U)
3448 /*! TRNG - TRNG
3449  *  0b00..Non-secure and non-privilege user access allowed
3450  *  0b01..Non-secure and privilege access allowed
3451  *  0b10..Secure and non-privilege user access allowed
3452  *  0b11..Secure and privilege user access allowed
3453  */
3454 #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_TRNG(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_TRNG_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_TRNG_MASK)
3455 
3456 #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_EIM0_MASK (0x3000U)
3457 #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_EIM0_SHIFT (12U)
3458 /*! EIM0 - EIM0
3459  *  0b00..Non-secure and non-privilege user access allowed
3460  *  0b01..Non-secure and privilege access allowed
3461  *  0b10..Secure and non-privilege user access allowed
3462  *  0b11..Secure and privilege user access allowed
3463  */
3464 #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_EIM0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_EIM0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_EIM0_MASK)
3465 
3466 #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_ERM0_MASK (0x30000U)
3467 #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_ERM0_SHIFT (16U)
3468 /*! ERM0 - ERM0
3469  *  0b00..Non-secure and non-privilege user access allowed
3470  *  0b01..Non-secure and privilege access allowed
3471  *  0b10..Secure and non-privilege user access allowed
3472  *  0b11..Secure and privilege user access allowed
3473  */
3474 #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_ERM0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_ERM0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_ERM0_MASK)
3475 
3476 #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_INTM0_MASK (0x300000U)
3477 #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_INTM0_SHIFT (20U)
3478 /*! INTM0 - INTM0
3479  *  0b00..Non-secure and non-privilege user access allowed
3480  *  0b01..Non-secure and privilege access allowed
3481  *  0b10..Secure and non-privilege user access allowed
3482  *  0b11..Secure and privilege user access allowed
3483  */
3484 #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_INTM0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_INTM0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_INTM0_MASK)
3485 /*! @} */
3486 
3487 /*! @name AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0 - AHB Peripheral 0 Slave Port 12 Slave Rule 0 */
3488 /*! @{ */
3489 
3490 #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_EDMA0_CH15_MASK (0x30U)
3491 #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_EDMA0_CH15_SHIFT (4U)
3492 /*! eDMA0_CH15 - eDMA0_CH15
3493  *  0b00..Non-secure and non-privilege user access allowed
3494  *  0b01..Non-secure and privilege access allowed
3495  *  0b10..Secure and non-privilege user access allowed
3496  *  0b11..Secure and privilege user access allowed
3497  */
3498 #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_EDMA0_CH15(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_EDMA0_CH15_SHIFT)) & AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_EDMA0_CH15_MASK)
3499 
3500 #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_SCT0_MASK (0x300U)
3501 #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_SCT0_SHIFT (8U)
3502 /*! SCT0 - SCT0
3503  *  0b00..Non-secure and non-privilege user access allowed
3504  *  0b01..Non-secure and privilege access allowed
3505  *  0b10..Secure and non-privilege user access allowed
3506  *  0b11..Secure and privilege user access allowed
3507  */
3508 #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_SCT0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_SCT0_SHIFT)) & AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_SCT0_MASK)
3509 
3510 #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM0_MASK (0x3000U)
3511 #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM0_SHIFT (12U)
3512 /*! LP_FLEXCOMM0 - LP_FLEXCOMM0
3513  *  0b00..Non-secure and non-privilege user access allowed
3514  *  0b01..Non-secure and privilege access allowed
3515  *  0b10..Secure and non-privilege user access allowed
3516  *  0b11..Secure and privilege user access allowed
3517  */
3518 #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM0_SHIFT)) & AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM0_MASK)
3519 
3520 #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM1_MASK (0x30000U)
3521 #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM1_SHIFT (16U)
3522 /*! LP_FLEXCOMM1 - LP_FLEXCOMM1
3523  *  0b00..Non-secure and non-privilege user access allowed
3524  *  0b01..Non-secure and privilege access allowed
3525  *  0b10..Secure and non-privilege user access allowed
3526  *  0b11..Secure and privilege user access allowed
3527  */
3528 #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM1_SHIFT)) & AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM1_MASK)
3529 
3530 #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM2_MASK (0x300000U)
3531 #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM2_SHIFT (20U)
3532 /*! LP_FLEXCOMM2 - LP_FLEXCOMM2
3533  *  0b00..Non-secure and non-privilege user access allowed
3534  *  0b01..Non-secure and privilege access allowed
3535  *  0b10..Secure and non-privilege user access allowed
3536  *  0b11..Secure and privilege user access allowed
3537  */
3538 #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM2_SHIFT)) & AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM2_MASK)
3539 
3540 #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM3_MASK (0x3000000U)
3541 #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM3_SHIFT (24U)
3542 /*! LP_FLEXCOMM3 - LP_FLEXCOMM3
3543  *  0b00..Non-secure and non-privilege user access allowed
3544  *  0b01..Non-secure and privilege access allowed
3545  *  0b10..Secure and non-privilege user access allowed
3546  *  0b11..Secure and privilege user access allowed
3547  */
3548 #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM3_SHIFT)) & AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM3_MASK)
3549 
3550 #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_GPIO0_ALIAS0_MASK (0x30000000U)
3551 #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_GPIO0_ALIAS0_SHIFT (28U)
3552 /*! GPIO0_ALIAS0 - GPIO0_ALIAS0
3553  *  0b00..Non-secure and non-privilege user access allowed
3554  *  0b01..Non-secure and privilege access allowed
3555  *  0b10..Secure and non-privilege user access allowed
3556  *  0b11..Secure and privilege user access allowed
3557  */
3558 #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_GPIO0_ALIAS0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_GPIO0_ALIAS0_SHIFT)) & AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_GPIO0_ALIAS0_MASK)
3559 /*! @} */
3560 
3561 /*! @name AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1 - AHB Peripheral 0 Slave Port 12 Slave Rule 1 */
3562 /*! @{ */
3563 
3564 #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO0_ALIAS1_MASK (0x3U)
3565 #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO0_ALIAS1_SHIFT (0U)
3566 /*! GPIO0_ALIAS1 - GPIO0_ALIAS1
3567  *  0b00..Non-secure and non-privilege user access allowed
3568  *  0b01..Non-secure and privilege access allowed
3569  *  0b10..Secure and non-privilege user access allowed
3570  *  0b11..Secure and privilege user access allowed
3571  */
3572 #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO0_ALIAS1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO0_ALIAS1_SHIFT)) & AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO0_ALIAS1_MASK)
3573 
3574 #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO1_ALIAS0_MASK (0x30U)
3575 #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO1_ALIAS0_SHIFT (4U)
3576 /*! GPIO1_ALIAS0 - GPIO1_ALIAS0
3577  *  0b00..Non-secure and non-privilege user access allowed
3578  *  0b01..Non-secure and privilege access allowed
3579  *  0b10..Secure and non-privilege user access allowed
3580  *  0b11..Secure and privilege user access allowed
3581  */
3582 #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO1_ALIAS0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO1_ALIAS0_SHIFT)) & AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO1_ALIAS0_MASK)
3583 
3584 #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO1_ALIAS1_MASK (0x300U)
3585 #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO1_ALIAS1_SHIFT (8U)
3586 /*! GPIO1_ALIAS1 - GPIO1_ALIAS1
3587  *  0b00..Non-secure and non-privilege user access allowed
3588  *  0b01..Non-secure and privilege access allowed
3589  *  0b10..Secure and non-privilege user access allowed
3590  *  0b11..Secure and privilege user access allowed
3591  */
3592 #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO1_ALIAS1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO1_ALIAS1_SHIFT)) & AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO1_ALIAS1_MASK)
3593 
3594 #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO2_ALIAS0_MASK (0x3000U)
3595 #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO2_ALIAS0_SHIFT (12U)
3596 /*! GPIO2_ALIAS0 - GPIO2_ALIAS0
3597  *  0b00..Non-secure and non-privilege user access allowed
3598  *  0b01..Non-secure and privilege access allowed
3599  *  0b10..Secure and non-privilege user access allowed
3600  *  0b11..Secure and privilege user access allowed
3601  */
3602 #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO2_ALIAS0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO2_ALIAS0_SHIFT)) & AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO2_ALIAS0_MASK)
3603 
3604 #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO2_ALIAS1_MASK (0x30000U)
3605 #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO2_ALIAS1_SHIFT (16U)
3606 /*! GPIO2_ALIAS1 - GPIO2_ALIAS1
3607  *  0b00..Non-secure and non-privilege user access allowed
3608  *  0b01..Non-secure and privilege access allowed
3609  *  0b10..Secure and non-privilege user access allowed
3610  *  0b11..Secure and privilege user access allowed
3611  */
3612 #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO2_ALIAS1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO2_ALIAS1_SHIFT)) & AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO2_ALIAS1_MASK)
3613 
3614 #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO3_ALIAS0_MASK (0x300000U)
3615 #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO3_ALIAS0_SHIFT (20U)
3616 /*! GPIO3_ALIAS0 - GPIO3_ALIAS0
3617  *  0b00..Non-secure and non-privilege user access allowed
3618  *  0b01..Non-secure and privilege access allowed
3619  *  0b10..Secure and non-privilege user access allowed
3620  *  0b11..Secure and privilege user access allowed
3621  */
3622 #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO3_ALIAS0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO3_ALIAS0_SHIFT)) & AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO3_ALIAS0_MASK)
3623 
3624 #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO3_ALIAS1_MASK (0x3000000U)
3625 #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO3_ALIAS1_SHIFT (24U)
3626 /*! GPIO3_ALIAS1 - GPIO3_ALIAS1
3627  *  0b00..Non-secure and non-privilege user access allowed
3628  *  0b01..Non-secure and privilege access allowed
3629  *  0b10..Secure and non-privilege user access allowed
3630  *  0b11..Secure and privilege user access allowed
3631  */
3632 #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO3_ALIAS1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO3_ALIAS1_SHIFT)) & AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO3_ALIAS1_MASK)
3633 
3634 #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO4_ALIAS0_MASK (0x30000000U)
3635 #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO4_ALIAS0_SHIFT (28U)
3636 /*! GPIO4_ALIAS0 - GPIO4_ALIAS0
3637  *  0b00..Non-secure and non-privilege user access allowed
3638  *  0b01..Non-secure and privilege access allowed
3639  *  0b10..Secure and non-privilege user access allowed
3640  *  0b11..Secure and privilege user access allowed
3641  */
3642 #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO4_ALIAS0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO4_ALIAS0_SHIFT)) & AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO4_ALIAS0_MASK)
3643 /*! @} */
3644 
3645 /*! @name AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE2 - AHB Peripheral 0 Slave Port 12 Slave Rule 2 */
3646 /*! @{ */
3647 
3648 #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE2_GPIO4_ALIAS1_MASK (0x3U)
3649 #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE2_GPIO4_ALIAS1_SHIFT (0U)
3650 /*! GPIO4_ALIAS1 - GPIO4_ALIAS1
3651  *  0b00..Non-secure and non-privilege user access allowed
3652  *  0b01..Non-secure and privilege access allowed
3653  *  0b10..Secure and non-privilege user access allowed
3654  *  0b11..Secure and privilege user access allowed
3655  */
3656 #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE2_GPIO4_ALIAS1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE2_GPIO4_ALIAS1_SHIFT)) & AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE2_GPIO4_ALIAS1_MASK)
3657 /*! @} */
3658 
3659 /*! @name AIPS_BRIDGE_GROUP1_MEM_RULE0 - AIPS Bridge Group 1 Rule 0 */
3660 /*! @{ */
3661 
3662 #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_MP_MASK (0x3U)
3663 #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_MP_SHIFT (0U)
3664 /*! eDMA0_MP - eDMA0_MP
3665  *  0b00..Non-secure and non-privilege user access allowed
3666  *  0b01..Non-secure and privilege access allowed
3667  *  0b10..Secure and non-privilege user access allowed
3668  *  0b11..Secure and privilege user access allowed
3669  */
3670 #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_MP(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_MP_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_MP_MASK)
3671 
3672 #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH0_MASK (0x30U)
3673 #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH0_SHIFT (4U)
3674 /*! eDMA0_CH0 - eDMA0_CH0
3675  *  0b00..Non-secure and non-privilege user access allowed
3676  *  0b01..Non-secure and privilege access allowed
3677  *  0b10..Secure and non-privilege user access allowed
3678  *  0b11..Secure and privilege user access allowed
3679  */
3680 #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH0_MASK)
3681 
3682 #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH1_MASK (0x300U)
3683 #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH1_SHIFT (8U)
3684 /*! eDMA0_CH1 - eDMA0_CH1
3685  *  0b00..Non-secure and non-privilege user access allowed
3686  *  0b01..Non-secure and privilege access allowed
3687  *  0b10..Secure and non-privilege user access allowed
3688  *  0b11..Secure and privilege user access allowed
3689  */
3690 #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH1_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH1_MASK)
3691 
3692 #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH2_MASK (0x3000U)
3693 #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH2_SHIFT (12U)
3694 /*! eDMA0_CH2 - eDMA0_CH2
3695  *  0b00..Non-secure and non-privilege user access allowed
3696  *  0b01..Non-secure and privilege access allowed
3697  *  0b10..Secure and non-privilege user access allowed
3698  *  0b11..Secure and privilege user access allowed
3699  */
3700 #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH2_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH2_MASK)
3701 
3702 #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH3_MASK (0x30000U)
3703 #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH3_SHIFT (16U)
3704 /*! eDMA0_CH3 - FLEXSPI0 Registers
3705  *  0b00..Non-secure and non-privilege user access allowed
3706  *  0b01..Non-secure and privilege access allowed
3707  *  0b10..Secure and non-privilege user access allowed
3708  *  0b11..Secure and privilege user access allowed
3709  */
3710 #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH3_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH3_MASK)
3711 
3712 #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH4_MASK (0x300000U)
3713 #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH4_SHIFT (20U)
3714 /*! eDMA0_CH4 - eDMA0_CH4
3715  *  0b00..Non-secure and non-privilege user access allowed
3716  *  0b01..Non-secure and privilege access allowed
3717  *  0b10..Secure and non-privilege user access allowed
3718  *  0b11..Secure and privilege user access allowed
3719  */
3720 #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH4_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH4_MASK)
3721 
3722 #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH5_MASK (0x3000000U)
3723 #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH5_SHIFT (24U)
3724 /*! eDMA0_CH5 - eDMA0_CH5
3725  *  0b00..Non-secure and non-privilege user access allowed
3726  *  0b01..Non-secure and privilege access allowed
3727  *  0b10..Secure and non-privilege user access allowed
3728  *  0b11..Secure and privilege user access allowed
3729  */
3730 #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH5(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH5_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH5_MASK)
3731 
3732 #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH6_MASK (0x30000000U)
3733 #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH6_SHIFT (28U)
3734 /*! eDMA0_CH6 - eDMA0_CH6
3735  *  0b00..Non-secure and non-privilege user access allowed
3736  *  0b01..Non-secure and privilege access allowed
3737  *  0b10..Secure and non-privilege user access allowed
3738  *  0b11..Secure and privilege user access allowed
3739  */
3740 #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH6(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH6_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH6_MASK)
3741 /*! @} */
3742 
3743 /*! @name AIPS_BRIDGE_GROUP1_MEM_RULE1 - AIPS Bridge Group 1 Rule 1 */
3744 /*! @{ */
3745 
3746 #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH7_MASK (0x3U)
3747 #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH7_SHIFT (0U)
3748 /*! eDMA0_CH7 - eDMA0_CH7
3749  *  0b00..Non-secure and non-privilege user access allowed
3750  *  0b01..Non-secure and privilege access allowed
3751  *  0b10..Secure and non-privilege user access allowed
3752  *  0b11..Secure and privilege user access allowed
3753  */
3754 #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH7(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH7_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH7_MASK)
3755 
3756 #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH8_MASK (0x30U)
3757 #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH8_SHIFT (4U)
3758 /*! eDMA0_CH8 - eDMA0_CH8
3759  *  0b00..Non-secure and non-privilege user access allowed
3760  *  0b01..Non-secure and privilege access allowed
3761  *  0b10..Secure and non-privilege user access allowed
3762  *  0b11..Secure and privilege user access allowed
3763  */
3764 #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH8(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH8_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH8_MASK)
3765 
3766 #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH9_MASK (0x300U)
3767 #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH9_SHIFT (8U)
3768 /*! eDMA0_CH9 - eDMA0_CH9
3769  *  0b00..Non-secure and non-privilege user access allowed
3770  *  0b01..Non-secure and privilege access allowed
3771  *  0b10..Secure and non-privilege user access allowed
3772  *  0b11..Secure and privilege user access allowed
3773  */
3774 #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH9(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH9_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH9_MASK)
3775 
3776 #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH10_MASK (0x3000U)
3777 #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH10_SHIFT (12U)
3778 /*! eDMA0_CH10 - eDMA0_CH10
3779  *  0b00..Non-secure and non-privilege user access allowed
3780  *  0b01..Non-secure and privilege access allowed
3781  *  0b10..Secure and non-privilege user access allowed
3782  *  0b11..Secure and privilege user access allowed
3783  */
3784 #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH10(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH10_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH10_MASK)
3785 
3786 #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH11_MASK (0x30000U)
3787 #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH11_SHIFT (16U)
3788 /*! eDMA0_CH11 - FLEXSPI0
3789  *  0b00..Non-secure and non-privilege user access allowed
3790  *  0b01..Non-secure and privilege access allowed
3791  *  0b10..Secure and non-privilege user access allowed
3792  *  0b11..Secure and privilege user access allowed
3793  */
3794 #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH11(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH11_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH11_MASK)
3795 
3796 #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH12_MASK (0x300000U)
3797 #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH12_SHIFT (20U)
3798 /*! eDMA0_CH12 - eDMA0_CH12
3799  *  0b00..Non-secure and non-privilege user access allowed
3800  *  0b01..Non-secure and privilege access allowed
3801  *  0b10..Secure and non-privilege user access allowed
3802  *  0b11..Secure and privilege user access allowed
3803  */
3804 #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH12(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH12_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH12_MASK)
3805 
3806 #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH13_MASK (0x3000000U)
3807 #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH13_SHIFT (24U)
3808 /*! eDMA0_CH13 - eDMA0_CH13
3809  *  0b00..Non-secure and non-privilege user access allowed
3810  *  0b01..Non-secure and privilege access allowed
3811  *  0b10..Secure and non-privilege user access allowed
3812  *  0b11..Secure and privilege user access allowed
3813  */
3814 #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH13(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH13_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH13_MASK)
3815 
3816 #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH14_MASK (0x30000000U)
3817 #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH14_SHIFT (28U)
3818 /*! eDMA0_CH14 - eDMA0_CH14
3819  *  0b00..Non-secure and non-privilege user access allowed
3820  *  0b01..Non-secure and privilege access allowed
3821  *  0b10..Secure and non-privilege user access allowed
3822  *  0b11..Secure and privilege user access allowed
3823  */
3824 #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH14(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH14_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH14_MASK)
3825 /*! @} */
3826 
3827 /*! @name AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0 - AHB Peripheral 1 Slave Port 13 Slave Rule 0 */
3828 /*! @{ */
3829 
3830 #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_EDMA1_CH15_MASK (0x30U)
3831 #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_EDMA1_CH15_SHIFT (4U)
3832 /*! eDMA1_CH15 - eDMA1_CH15
3833  *  0b00..Non-secure and non-privilege user access allowed
3834  *  0b01..Non-secure and privilege access allowed
3835  *  0b10..Secure and non-privilege user access allowed
3836  *  0b11..Secure and privilege user access allowed
3837  */
3838 #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_EDMA1_CH15(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_EDMA1_CH15_SHIFT)) & AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_EDMA1_CH15_MASK)
3839 
3840 #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_SEMA42_MASK (0x300U)
3841 #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_SEMA42_SHIFT (8U)
3842 /*! SEMA42 - SEMA42
3843  *  0b00..Non-secure and non-privilege user access allowed
3844  *  0b01..Non-secure and privilege access allowed
3845  *  0b10..Secure and non-privilege user access allowed
3846  *  0b11..Secure and privilege user access allowed
3847  */
3848 #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_SEMA42(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_SEMA42_SHIFT)) & AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_SEMA42_MASK)
3849 
3850 #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_MAILBOX_MASK (0x3000U)
3851 #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_MAILBOX_SHIFT (12U)
3852 /*! MAILBOX - MAILBOX
3853  *  0b00..Non-secure and non-privilege user access allowed
3854  *  0b01..Non-secure and privilege access allowed
3855  *  0b10..Secure and non-privilege user access allowed
3856  *  0b11..Secure and privilege user access allowed
3857  */
3858 #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_MAILBOX(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_MAILBOX_SHIFT)) & AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_MAILBOX_MASK)
3859 
3860 #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_PKC_RAM_MASK (0x30000U)
3861 #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_PKC_RAM_SHIFT (16U)
3862 /*! PKC_RAM - PKC_RAM
3863  *  0b00..Non-secure and non-privilege user access allowed
3864  *  0b01..Non-secure and privilege access allowed
3865  *  0b10..Secure and non-privilege user access allowed
3866  *  0b11..Secure and privilege user access allowed
3867  */
3868 #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_PKC_RAM(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_PKC_RAM_SHIFT)) & AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_PKC_RAM_MASK)
3869 
3870 #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_FLEXCOMM4_MASK (0x300000U)
3871 #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_FLEXCOMM4_SHIFT (20U)
3872 /*! FLEXCOMM4 - FLEXCOMM4
3873  *  0b00..Non-secure and non-privilege user access allowed
3874  *  0b01..Non-secure and privilege access allowed
3875  *  0b10..Secure and non-privilege user access allowed
3876  *  0b11..Secure and privilege user access allowed
3877  */
3878 #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_FLEXCOMM4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_FLEXCOMM4_SHIFT)) & AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_FLEXCOMM4_MASK)
3879 
3880 #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_FLEXCOMM5_MASK (0x3000000U)
3881 #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_FLEXCOMM5_SHIFT (24U)
3882 /*! FLEXCOMM5 - FLEXCOMM5
3883  *  0b00..Non-secure and non-privilege user access allowed
3884  *  0b01..Non-secure and privilege access allowed
3885  *  0b10..Secure and non-privilege user access allowed
3886  *  0b11..Secure and privilege user access allowed
3887  */
3888 #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_FLEXCOMM5(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_FLEXCOMM5_SHIFT)) & AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_FLEXCOMM5_MASK)
3889 
3890 #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_FLEXCOMM6_MASK (0x30000000U)
3891 #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_FLEXCOMM6_SHIFT (28U)
3892 /*! FLEXCOMM6 - FLEXCOMM6
3893  *  0b00..Non-secure and non-privilege user access allowed
3894  *  0b01..Non-secure and privilege access allowed
3895  *  0b10..Secure and non-privilege user access allowed
3896  *  0b11..Secure and privilege user access allowed
3897  */
3898 #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_FLEXCOMM6(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_FLEXCOMM6_SHIFT)) & AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_FLEXCOMM6_MASK)
3899 /*! @} */
3900 
3901 /*! @name AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1 - AHB Peripheral 1 Slave Port 13 Slave Rule 1 */
3902 /*! @{ */
3903 
3904 #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_FLEXCOMM7_MASK (0x3U)
3905 #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_FLEXCOMM7_SHIFT (0U)
3906 /*! FLEXCOMM7 - FLEXCOMM7
3907  *  0b00..Non-secure and non-privilege user access allowed
3908  *  0b01..Non-secure and privilege access allowed
3909  *  0b10..Secure and non-privilege user access allowed
3910  *  0b11..Secure and privilege user access allowed
3911  */
3912 #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_FLEXCOMM7(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_FLEXCOMM7_SHIFT)) & AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_FLEXCOMM7_MASK)
3913 
3914 #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_FLEXCOMM8_MASK (0x30U)
3915 #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_FLEXCOMM8_SHIFT (4U)
3916 /*! FLEXCOMM8 - FLEXCOMM8
3917  *  0b00..Non-secure and non-privilege user access allowed
3918  *  0b01..Non-secure and privilege access allowed
3919  *  0b10..Secure and non-privilege user access allowed
3920  *  0b11..Secure and privilege user access allowed
3921  */
3922 #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_FLEXCOMM8(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_FLEXCOMM8_SHIFT)) & AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_FLEXCOMM8_MASK)
3923 
3924 #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_FLEXCOMM9_MASK (0x300U)
3925 #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_FLEXCOMM9_SHIFT (8U)
3926 /*! FLEXCOMM9 - FLEXCOMM9
3927  *  0b00..Non-secure and non-privilege user access allowed
3928  *  0b01..Non-secure and privilege access allowed
3929  *  0b10..Secure and non-privilege user access allowed
3930  *  0b11..Secure and privilege user access allowed
3931  */
3932 #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_FLEXCOMM9(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_FLEXCOMM9_SHIFT)) & AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_FLEXCOMM9_MASK)
3933 
3934 #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_USB_FS_OTG_RAM_MASK (0x3000U)
3935 #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_USB_FS_OTG_RAM_SHIFT (12U)
3936 /*! USB_FS_OTG_RAM - USB FS OTG RAM
3937  *  0b00..Non-secure and non-privilege user access allowed
3938  *  0b01..Non-secure and privilege access allowed
3939  *  0b10..Secure and non-privilege user access allowed
3940  *  0b11..Secure and privilege user access allowed
3941  */
3942 #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_USB_FS_OTG_RAM(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_USB_FS_OTG_RAM_SHIFT)) & AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_USB_FS_OTG_RAM_MASK)
3943 
3944 #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_CDOG0_MASK (0x30000U)
3945 #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_CDOG0_SHIFT (16U)
3946 /*! CDOG0 - CDOG0
3947  *  0b00..Non-secure and non-privilege user access allowed
3948  *  0b01..Non-secure and privilege access allowed
3949  *  0b10..Secure and non-privilege user access allowed
3950  *  0b11..Secure and privilege user access allowed
3951  */
3952 #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_CDOG0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_CDOG0_SHIFT)) & AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_CDOG0_MASK)
3953 
3954 #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_CDOG1_MASK (0x300000U)
3955 #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_CDOG1_SHIFT (20U)
3956 /*! CDOG1 - CDOG1
3957  *  0b00..Non-secure and non-privilege user access allowed
3958  *  0b01..Non-secure and privilege access allowed
3959  *  0b10..Secure and non-privilege user access allowed
3960  *  0b11..Secure and privilege user access allowed
3961  */
3962 #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_CDOG1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_CDOG1_SHIFT)) & AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_CDOG1_MASK)
3963 
3964 #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_DEBUG_MAILBOX_MASK (0x3000000U)
3965 #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_DEBUG_MAILBOX_SHIFT (24U)
3966 /*! DEBUG_MAILBOX - DEBUG_MAILBOX
3967  *  0b00..Non-secure and non-privilege user access allowed
3968  *  0b01..Non-secure and privilege access allowed
3969  *  0b10..Secure and non-privilege user access allowed
3970  *  0b11..Secure and privilege user access allowed
3971  */
3972 #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_DEBUG_MAILBOX(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_DEBUG_MAILBOX_SHIFT)) & AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_DEBUG_MAILBOX_MASK)
3973 
3974 #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_NPU_MASK (0x30000000U)
3975 #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_NPU_SHIFT (28U)
3976 /*! NPU - NPU
3977  *  0b00..Non-secure and non-privilege user access allowed
3978  *  0b01..Non-secure and privilege access allowed
3979  *  0b10..Secure and non-privilege user access allowed
3980  *  0b11..Secure and privilege user access allowed
3981  */
3982 #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_NPU(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_NPU_SHIFT)) & AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_NPU_MASK)
3983 /*! @} */
3984 
3985 /*! @name AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE2 - AHB Peripheral 1 Slave Port 13 Slave Rule 2 */
3986 /*! @{ */
3987 
3988 #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE2_POWERQUAD_MASK (0x3U)
3989 #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE2_POWERQUAD_SHIFT (0U)
3990 /*! POWERQUAD - POWERQUAD
3991  *  0b00..Non-secure and non-privilege user access allowed
3992  *  0b01..Non-secure and privilege access allowed
3993  *  0b10..Secure and non-privilege user access allowed
3994  *  0b11..Secure and privilege user access allowed
3995  */
3996 #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE2_POWERQUAD(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE2_POWERQUAD_SHIFT)) & AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE2_POWERQUAD_MASK)
3997 /*! @} */
3998 
3999 /*! @name AIPS_BRIDGE_GROUP2_MEM_RULE0 - AIPS Bridge Group 2 Rule 0 */
4000 /*! @{ */
4001 
4002 #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_MP_MASK (0x3U)
4003 #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_MP_SHIFT (0U)
4004 /*! eDMA1_MP - eDMA1_MP
4005  *  0b00..Non-secure and non-privilege user access allowed
4006  *  0b01..Non-secure and privilege access allowed
4007  *  0b10..Secure and non-privilege user access allowed
4008  *  0b11..Secure and privilege user access allowed
4009  */
4010 #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_MP(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_MP_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_MP_MASK)
4011 
4012 #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH0_MASK (0x30U)
4013 #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH0_SHIFT (4U)
4014 /*! eDMA1_CH0 - eDMA1_CH0
4015  *  0b00..Non-secure and non-privilege user access allowed
4016  *  0b01..Non-secure and privilege access allowed
4017  *  0b10..Secure and non-privilege user access allowed
4018  *  0b11..Secure and privilege user access allowed
4019  */
4020 #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH0_MASK)
4021 
4022 #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH1_MASK (0x300U)
4023 #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH1_SHIFT (8U)
4024 /*! eDMA1_CH1 - eDMA1_CH1
4025  *  0b00..Non-secure and non-privilege user access allowed
4026  *  0b01..Non-secure and privilege access allowed
4027  *  0b10..Secure and non-privilege user access allowed
4028  *  0b11..Secure and privilege user access allowed
4029  */
4030 #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH1_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH1_MASK)
4031 
4032 #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH2_MASK (0x3000U)
4033 #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH2_SHIFT (12U)
4034 /*! eDMA1_CH2 - eDMA1_CH2
4035  *  0b00..Non-secure and non-privilege user access allowed
4036  *  0b01..Non-secure and privilege access allowed
4037  *  0b10..Secure and non-privilege user access allowed
4038  *  0b11..Secure and privilege user access allowed
4039  */
4040 #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH2_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH2_MASK)
4041 
4042 #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH3_MASK (0x30000U)
4043 #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH3_SHIFT (16U)
4044 /*! eDMA1_CH3 - eDMA1_CH3
4045  *  0b00..Non-secure and non-privilege user access allowed
4046  *  0b01..Non-secure and privilege access allowed
4047  *  0b10..Secure and non-privilege user access allowed
4048  *  0b11..Secure and privilege user access allowed
4049  */
4050 #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH3_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH3_MASK)
4051 
4052 #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH4_MASK (0x300000U)
4053 #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH4_SHIFT (20U)
4054 /*! eDMA1_CH4 - eDMA1_CH4
4055  *  0b00..Non-secure and non-privilege user access allowed
4056  *  0b01..Non-secure and privilege access allowed
4057  *  0b10..Secure and non-privilege user access allowed
4058  *  0b11..Secure and privilege user access allowed
4059  */
4060 #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH4_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH4_MASK)
4061 
4062 #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH5_MASK (0x3000000U)
4063 #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH5_SHIFT (24U)
4064 /*! eDMA1_CH5 - eDMA1_CH5
4065  *  0b00..Non-secure and non-privilege user access allowed
4066  *  0b01..Non-secure and privilege access allowed
4067  *  0b10..Secure and non-privilege user access allowed
4068  *  0b11..Secure and privilege user access allowed
4069  */
4070 #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH5(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH5_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH5_MASK)
4071 
4072 #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH6_MASK (0x30000000U)
4073 #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH6_SHIFT (28U)
4074 /*! eDMA1_CH6 - eDMA1_CH6
4075  *  0b00..Non-secure and non-privilege user access allowed
4076  *  0b01..Non-secure and privilege access allowed
4077  *  0b10..Secure and non-privilege user access allowed
4078  *  0b11..Secure and privilege user access allowed
4079  */
4080 #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH6(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH6_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH6_MASK)
4081 /*! @} */
4082 
4083 /*! @name AIPS_BRIDGE_GROUP2_MEM_RULE1 - AIPS Bridge Group 2 Memory Rule 1 */
4084 /*! @{ */
4085 
4086 #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH7_MASK (0x3U)
4087 #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH7_SHIFT (0U)
4088 /*! eDMA1_CH7 - eDMA1_CH7
4089  *  0b00..Non-secure and non-privilege user access allowed
4090  *  0b01..Non-secure and privilege access allowed
4091  *  0b10..Secure and non-privilege user access allowed
4092  *  0b11..Secure and privilege user access allowed
4093  */
4094 #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH7(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH7_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH7_MASK)
4095 
4096 #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH8_MASK (0x30U)
4097 #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH8_SHIFT (4U)
4098 /*! eDMA1_CH8 - eDMA1_CH8
4099  *  0b00..Non-secure and non-privilege user access allowed
4100  *  0b01..Non-secure and privilege access allowed
4101  *  0b10..Secure and non-privilege user access allowed
4102  *  0b11..Secure and privilege user access allowed
4103  */
4104 #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH8(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH8_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH8_MASK)
4105 
4106 #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH9_MASK (0x300U)
4107 #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH9_SHIFT (8U)
4108 /*! eDMA1_CH9 - eDMA1_CH9
4109  *  0b00..Non-secure and non-privilege user access allowed
4110  *  0b01..Non-secure and privilege access allowed
4111  *  0b10..Secure and non-privilege user access allowed
4112  *  0b11..Secure and privilege user access allowed
4113  */
4114 #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH9(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH9_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH9_MASK)
4115 
4116 #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH10_MASK (0x3000U)
4117 #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH10_SHIFT (12U)
4118 /*! eDMA1_CH10 - eDMA1_CH10
4119  *  0b00..Non-secure and non-privilege user access allowed
4120  *  0b01..Non-secure and privilege access allowed
4121  *  0b10..Secure and non-privilege user access allowed
4122  *  0b11..Secure and privilege user access allowed
4123  */
4124 #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH10(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH10_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH10_MASK)
4125 
4126 #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH11_MASK (0x30000U)
4127 #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH11_SHIFT (16U)
4128 /*! eDMA1_CH11 - eDMA1_CH11
4129  *  0b00..Non-secure and non-privilege user access allowed
4130  *  0b01..Non-secure and privilege access allowed
4131  *  0b10..Secure and non-privilege user access allowed
4132  *  0b11..Secure and privilege user access allowed
4133  */
4134 #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH11(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH11_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH11_MASK)
4135 
4136 #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH12_MASK (0x300000U)
4137 #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH12_SHIFT (20U)
4138 /*! eDMA1_CH12 - eDMA1_CH12
4139  *  0b00..Non-secure and non-privilege user access allowed
4140  *  0b01..Non-secure and privilege access allowed
4141  *  0b10..Secure and non-privilege user access allowed
4142  *  0b11..Secure and privilege user access allowed
4143  */
4144 #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH12(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH12_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH12_MASK)
4145 
4146 #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH13_MASK (0x3000000U)
4147 #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH13_SHIFT (24U)
4148 /*! eDMA1_CH13 - eDMA1_CH13
4149  *  0b00..Non-secure and non-privilege user access allowed
4150  *  0b01..Non-secure and privilege access allowed
4151  *  0b10..Secure and non-privilege user access allowed
4152  *  0b11..Secure and privilege user access allowed
4153  */
4154 #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH13(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH13_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH13_MASK)
4155 
4156 #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH14_MASK (0x30000000U)
4157 #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH14_SHIFT (28U)
4158 /*! eDMA1_CH14 - eDMA1_CH14
4159  *  0b00..Non-secure and non-privilege user access allowed
4160  *  0b01..Non-secure and privilege access allowed
4161  *  0b10..Secure and non-privilege user access allowed
4162  *  0b11..Secure and privilege user access allowed
4163  */
4164 #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH14(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH14_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH14_MASK)
4165 /*! @} */
4166 
4167 /*! @name AIPS_BRIDGE_GROUP3_MEM_RULE0 - AIPS Bridge Group 3 Rule 0 */
4168 /*! @{ */
4169 
4170 #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_EWM0_MASK (0x3U)
4171 #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_EWM0_SHIFT (0U)
4172 /*! EWM0 - EWM0
4173  *  0b00..Non-secure and non-privilege user access allowed
4174  *  0b01..Non-secure and privilege access allowed
4175  *  0b10..Secure and non-privilege user access allowed
4176  *  0b11..Secure and privilege user access allowed
4177  */
4178 #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_EWM0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_EWM0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_EWM0_MASK)
4179 
4180 #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_LPCAC_MASK (0x30U)
4181 #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_LPCAC_SHIFT (4U)
4182 /*! LPCAC - LPCAC
4183  *  0b00..Non-secure and non-privilege user access allowed
4184  *  0b01..Non-secure and privilege access allowed
4185  *  0b10..Secure and non-privilege user access allowed
4186  *  0b11..Secure and privilege user access allowed
4187  */
4188 #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_LPCAC(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_LPCAC_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_LPCAC_MASK)
4189 
4190 #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_FLEXSPI_CMX_MASK (0x300U)
4191 #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_FLEXSPI_CMX_SHIFT (8U)
4192 /*! FLEXSPI_CMX - FLEXSPI_CMX
4193  *  0b00..Non-secure and non-privilege user access allowed
4194  *  0b01..Non-secure and privilege access allowed
4195  *  0b10..Secure and non-privilege user access allowed
4196  *  0b11..Secure and privilege user access allowed
4197  */
4198 #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_FLEXSPI_CMX(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_FLEXSPI_CMX_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_FLEXSPI_CMX_MASK)
4199 
4200 #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_SFA_MASK (0x300000U)
4201 #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_SFA_SHIFT (20U)
4202 /*! SFA - SFA
4203  *  0b00..Non-secure and non-privilege user access allowed
4204  *  0b01..Non-secure and privilege access allowed
4205  *  0b10..Secure and non-privilege user access allowed
4206  *  0b11..Secure and privilege user access allowed
4207  */
4208 #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_SFA(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_SFA_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_SFA_MASK)
4209 
4210 #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_MBC_MASK (0x30000000U)
4211 #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_MBC_SHIFT (28U)
4212 /*! MBC - MBC
4213  *  0b00..Non-secure and non-privilege user access allowed
4214  *  0b01..Non-secure and privilege access allowed
4215  *  0b10..Secure and non-privilege user access allowed
4216  *  0b11..Secure and privilege user access allowed
4217  */
4218 #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_MBC(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_MBC_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_MBC_MASK)
4219 /*! @} */
4220 
4221 /*! @name AIPS_BRIDGE_GROUP3_MEM_RULE1 - AIPS Bridge Group 3 Memory Rule 1 */
4222 /*! @{ */
4223 
4224 #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_FLEXSPI_MASK (0x3U)
4225 #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_FLEXSPI_SHIFT (0U)
4226 /*! FLEXSPI - FLEXSPI
4227  *  0b00..Non-secure and non-privilege user access allowed
4228  *  0b01..Non-secure and privilege access allowed
4229  *  0b10..Secure and non-privilege user access allowed
4230  *  0b11..Secure and privilege user access allowed
4231  */
4232 #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_FLEXSPI(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_FLEXSPI_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_FLEXSPI_MASK)
4233 
4234 #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_OTPC_MASK (0x30U)
4235 #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_OTPC_SHIFT (4U)
4236 /*! OTPC - OTPC
4237  *  0b00..Non-secure and non-privilege user access allowed
4238  *  0b01..Non-secure and privilege access allowed
4239  *  0b10..Secure and non-privilege user access allowed
4240  *  0b11..Secure and privilege user access allowed
4241  */
4242 #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_OTPC(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_OTPC_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_OTPC_MASK)
4243 
4244 #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_CRC_MASK (0x3000U)
4245 #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_CRC_SHIFT (12U)
4246 /*! CRC - CRC
4247  *  0b00..Non-secure and non-privilege user access allowed
4248  *  0b01..Non-secure and privilege access allowed
4249  *  0b10..Secure and non-privilege user access allowed
4250  *  0b11..Secure and privilege user access allowed
4251  */
4252 #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_CRC(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_CRC_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_CRC_MASK)
4253 
4254 #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_NPX_MASK (0x30000U)
4255 #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_NPX_SHIFT (16U)
4256 /*! NPX - NPX
4257  *  0b00..Non-secure and non-privilege user access allowed
4258  *  0b01..Non-secure and privilege access allowed
4259  *  0b10..Secure and non-privilege user access allowed
4260  *  0b11..Secure and privilege user access allowed
4261  */
4262 #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_NPX(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_NPX_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_NPX_MASK)
4263 
4264 #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_PWM_MASK (0x3000000U)
4265 #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_PWM_SHIFT (24U)
4266 /*! PWM - PWM
4267  *  0b00..Non-secure and non-privilege user access allowed
4268  *  0b01..Non-secure and privilege access allowed
4269  *  0b10..Secure and non-privilege user access allowed
4270  *  0b11..Secure and privilege user access allowed
4271  */
4272 #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_PWM(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_PWM_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_PWM_MASK)
4273 
4274 #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_ENC_MASK (0x30000000U)
4275 #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_ENC_SHIFT (28U)
4276 /*! ENC - ENC
4277  *  0b00..Non-secure and non-privilege user access allowed
4278  *  0b01..Non-secure and privilege access allowed
4279  *  0b10..Secure and non-privilege user access allowed
4280  *  0b11..Secure and privilege user access allowed
4281  */
4282 #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_ENC(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_ENC_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_ENC_MASK)
4283 /*! @} */
4284 
4285 /*! @name AIPS_BRIDGE_GROUP3_MEM_RULE2 - AIPS Bridge Group 3 Rule 2 */
4286 /*! @{ */
4287 
4288 #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_PWM1_MASK (0x3U)
4289 #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_PWM1_SHIFT (0U)
4290 /*! PWM1 - PWM1
4291  *  0b00..Non-secure and non-privilege user access allowed
4292  *  0b01..Non-secure and privilege access allowed
4293  *  0b10..Secure and non-privilege user access allowed
4294  *  0b11..Secure and privilege user access allowed
4295  */
4296 #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_PWM1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_PWM1_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_PWM1_MASK)
4297 
4298 #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_ENC1_MASK (0x30U)
4299 #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_ENC1_SHIFT (4U)
4300 /*! ENC1 - ENC1
4301  *  0b00..Non-secure and non-privilege user access allowed
4302  *  0b01..Non-secure and privilege access allowed
4303  *  0b10..Secure and non-privilege user access allowed
4304  *  0b11..Secure and privilege user access allowed
4305  */
4306 #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_ENC1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_ENC1_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_ENC1_MASK)
4307 
4308 #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_EVTG_MASK (0x300U)
4309 #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_EVTG_SHIFT (8U)
4310 /*! EVTG - EVTG
4311  *  0b00..Non-secure and non-privilege user access allowed
4312  *  0b01..Non-secure and privilege access allowed
4313  *  0b10..Secure and non-privilege user access allowed
4314  *  0b11..Secure and privilege user access allowed
4315  */
4316 #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_EVTG(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_EVTG_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_EVTG_MASK)
4317 
4318 #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE0_MASK (0x30000U)
4319 #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE0_SHIFT (16U)
4320 /*! CAN0_RULE0 - CAN0 RULE0
4321  *  0b00..Non-secure and non-privilege user access allowed
4322  *  0b01..Non-secure and privilege access allowed
4323  *  0b10..Secure and non-privilege user access allowed
4324  *  0b11..Secure and privilege user access allowed
4325  */
4326 #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE0_MASK)
4327 
4328 #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE1_MASK (0x300000U)
4329 #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE1_SHIFT (20U)
4330 /*! CAN0_RULE1 - CAN0 RULE1
4331  *  0b00..Non-secure and non-privilege user access allowed
4332  *  0b01..Non-secure and privilege access allowed
4333  *  0b10..Secure and non-privilege user access allowed
4334  *  0b11..Secure and privilege user access allowed
4335  */
4336 #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE1_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE1_MASK)
4337 
4338 #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE2_MASK (0x3000000U)
4339 #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE2_SHIFT (24U)
4340 /*! CAN0_RULE2 - CAN0 RULE2
4341  *  0b00..Non-secure and non-privilege user access allowed
4342  *  0b01..Non-secure and privilege access allowed
4343  *  0b10..Secure and non-privilege user access allowed
4344  *  0b11..Secure and privilege user access allowed
4345  */
4346 #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE2_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE2_MASK)
4347 
4348 #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE3_MASK (0x30000000U)
4349 #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE3_SHIFT (28U)
4350 /*! CAN0_RULE3 - CAN0 RULE3
4351  *  0b00..Non-secure and non-privilege user access allowed
4352  *  0b01..Non-secure and privilege access allowed
4353  *  0b10..Secure and non-privilege user access allowed
4354  *  0b11..Secure and privilege user access allowed
4355  */
4356 #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE3_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE3_MASK)
4357 /*! @} */
4358 
4359 /*! @name AIPS_BRIDGE_GROUP3_MEM_RULE3 - AIPS Bridge Group 3 Rule 3 */
4360 /*! @{ */
4361 
4362 #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE0_MASK (0x3U)
4363 #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE0_SHIFT (0U)
4364 /*! CAN1_RULE0 - CAN1 RULE0
4365  *  0b00..Non-secure and non-privilege user access allowed
4366  *  0b01..Non-secure and privilege access allowed
4367  *  0b10..Secure and non-privilege user access allowed
4368  *  0b11..Secure and privilege user access allowed
4369  */
4370 #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE0_MASK)
4371 
4372 #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE1_MASK (0x30U)
4373 #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE1_SHIFT (4U)
4374 /*! CAN1_RULE1 - CAN1 RULE1
4375  *  0b00..Non-secure and non-privilege user access allowed
4376  *  0b01..Non-secure and privilege access allowed
4377  *  0b10..Secure and non-privilege user access allowed
4378  *  0b11..Secure and privilege user access allowed
4379  */
4380 #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE1_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE1_MASK)
4381 
4382 #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE2_MASK (0x300U)
4383 #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE2_SHIFT (8U)
4384 /*! CAN1_RULE2 - CAN1 RULE2
4385  *  0b00..Non-secure and non-privilege user access allowed
4386  *  0b01..Non-secure and privilege access allowed
4387  *  0b10..Secure and non-privilege user access allowed
4388  *  0b11..Secure and privilege user access allowed
4389  */
4390 #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE2_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE2_MASK)
4391 
4392 #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE3_MASK (0x3000U)
4393 #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE3_SHIFT (12U)
4394 /*! CAN1_RULE3 - CAN1 RULE3
4395  *  0b00..Non-secure and non-privilege user access allowed
4396  *  0b01..Non-secure and privilege access allowed
4397  *  0b10..Secure and non-privilege user access allowed
4398  *  0b11..Secure and privilege user access allowed
4399  */
4400 #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE3_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE3_MASK)
4401 
4402 #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_USBDCD_MASK (0x30000U)
4403 #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_USBDCD_SHIFT (16U)
4404 /*! USBDCD - USBDCD
4405  *  0b00..Non-secure and non-privilege user access allowed
4406  *  0b01..Non-secure and privilege access allowed
4407  *  0b10..Secure and non-privilege user access allowed
4408  *  0b11..Secure and privilege user access allowed
4409  */
4410 #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_USBDCD(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_USBDCD_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_USBDCD_MASK)
4411 
4412 #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_USBFS_MASK (0x300000U)
4413 #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_USBFS_SHIFT (20U)
4414 /*! USBFS - USBFS
4415  *  0b00..Non-secure and non-privilege user access allowed
4416  *  0b01..Non-secure and privilege access allowed
4417  *  0b10..Secure and non-privilege user access allowed
4418  *  0b11..Secure and privilege user access allowed
4419  */
4420 #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_USBFS(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_USBFS_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_USBFS_MASK)
4421 /*! @} */
4422 
4423 /*! @name AIPS_BRIDGE_GROUP4_MEM_RULE0 - AIPS Bridge Group 4 Rule 0 */
4424 /*! @{ */
4425 
4426 #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_ENET_MASK (0xFU)
4427 #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_ENET_SHIFT (0U)
4428 /*! ENET - ENET
4429  *  0b0000..Non-secure and non-privilege user access allowed
4430  *  0b0001..Non-secure and privilege access allowed
4431  *  0b0010..Secure and non-privilege user access allowed
4432  *  0b0011..Secure and privilege user access allowed
4433  */
4434 #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_ENET(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_ENET_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_ENET_MASK)
4435 
4436 #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_EMVSIM0_MASK (0x3000U)
4437 #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_EMVSIM0_SHIFT (12U)
4438 /*! EMVSIM0 - EMVSIM0
4439  *  0b00..Non-secure and non-privilege user access allowed
4440  *  0b01..Non-secure and privilege access allowed
4441  *  0b10..Secure and non-privilege user access allowed
4442  *  0b11..Secure and privilege user access allowed
4443  */
4444 #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_EMVSIM0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_EMVSIM0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_EMVSIM0_MASK)
4445 
4446 #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_EMVSIM1_MASK (0x30000U)
4447 #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_EMVSIM1_SHIFT (16U)
4448 /*! EMVSIM1 - EMVSIM1
4449  *  0b00..Non-secure and non-privilege user access allowed
4450  *  0b01..Non-secure and privilege access allowed
4451  *  0b10..Secure and non-privilege user access allowed
4452  *  0b11..Secure and privilege user access allowed
4453  */
4454 #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_EMVSIM1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_EMVSIM1_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_EMVSIM1_MASK)
4455 
4456 #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_FLEXIO_MASK (0x300000U)
4457 #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_FLEXIO_SHIFT (20U)
4458 /*! FLEXIO - FLEXIO
4459  *  0b00..Non-secure and non-privilege user access allowed
4460  *  0b01..Non-secure and privilege access allowed
4461  *  0b10..Secure and non-privilege user access allowed
4462  *  0b11..Secure and privilege user access allowed
4463  */
4464 #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_FLEXIO(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_FLEXIO_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_FLEXIO_MASK)
4465 
4466 #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_SAI0_MASK (0x3000000U)
4467 #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_SAI0_SHIFT (24U)
4468 /*! SAI0 - SAI0
4469  *  0b00..Non-secure and non-privilege user access allowed
4470  *  0b01..Non-secure and privilege access allowed
4471  *  0b10..Secure and non-privilege user access allowed
4472  *  0b11..Secure and privilege user access allowed
4473  */
4474 #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_SAI0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_SAI0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_SAI0_MASK)
4475 
4476 #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_SAI1_MASK (0x30000000U)
4477 #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_SAI1_SHIFT (28U)
4478 /*! SAI1 - SAI1
4479  *  0b00..Non-secure and non-privilege user access allowed
4480  *  0b01..Non-secure and privilege access allowed
4481  *  0b10..Secure and non-privilege user access allowed
4482  *  0b11..Secure and privilege user access allowed
4483  */
4484 #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_SAI1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_SAI1_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_SAI1_MASK)
4485 /*! @} */
4486 
4487 /*! @name AIPS_BRIDGE_GROUP4_MEM_RULE1 - AIPS Bridge Group 4 Rule 1 */
4488 /*! @{ */
4489 
4490 #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_SINC0_MASK (0x3U)
4491 #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_SINC0_SHIFT (0U)
4492 /*! SINC0 - SINC0
4493  *  0b00..Non-secure and non-privilege user access allowed
4494  *  0b01..Non-secure and privilege access allowed
4495  *  0b10..Secure and non-privilege user access allowed
4496  *  0b11..Secure and privilege user access allowed
4497  */
4498 #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_SINC0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_SINC0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_SINC0_MASK)
4499 
4500 #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_USDHC0_MASK (0x30U)
4501 #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_USDHC0_SHIFT (4U)
4502 /*! uSDHC0 - uSDHC0
4503  *  0b00..Non-secure and non-privilege user access allowed
4504  *  0b01..Non-secure and privilege access allowed
4505  *  0b10..Secure and non-privilege user access allowed
4506  *  0b11..Secure and privilege user access allowed
4507  */
4508 #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_USDHC0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_USDHC0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_USDHC0_MASK)
4509 
4510 #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_USBHSPHY_MASK (0x300U)
4511 #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_USBHSPHY_SHIFT (8U)
4512 /*! USBHSPHY - USBHSPHY
4513  *  0b00..Non-secure and non-privilege user access allowed
4514  *  0b01..Non-secure and privilege access allowed
4515  *  0b10..Secure and non-privilege user access allowed
4516  *  0b11..Secure and privilege user access allowed
4517  */
4518 #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_USBHSPHY(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_USBHSPHY_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_USBHSPHY_MASK)
4519 
4520 #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_USBHS_MASK (0x3000U)
4521 #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_USBHS_SHIFT (12U)
4522 /*! USBHS - USBHS
4523  *  0b00..Non-secure and non-privilege user access allowed
4524  *  0b01..Non-secure and privilege access allowed
4525  *  0b10..Secure and non-privilege user access allowed
4526  *  0b11..Secure and privilege user access allowed
4527  */
4528 #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_USBHS(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_USBHS_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_USBHS_MASK)
4529 
4530 #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_MICD_MASK (0x30000U)
4531 #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_MICD_SHIFT (16U)
4532 /*! MICD - MICD
4533  *  0b00..Non-secure and non-privilege user access allowed
4534  *  0b01..Non-secure and privilege access allowed
4535  *  0b10..Secure and non-privilege user access allowed
4536  *  0b11..Secure and privilege user access allowed
4537  */
4538 #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_MICD(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_MICD_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_MICD_MASK)
4539 
4540 #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_ADC0_MASK (0x300000U)
4541 #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_ADC0_SHIFT (20U)
4542 /*! ADC0 - ADC0
4543  *  0b00..Non-secure and non-privilege user access allowed
4544  *  0b01..Non-secure and privilege access allowed
4545  *  0b10..Secure and non-privilege user access allowed
4546  *  0b11..Secure and privilege user access allowed
4547  */
4548 #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_ADC0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_ADC0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_ADC0_MASK)
4549 
4550 #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_ADC1_MASK (0x3000000U)
4551 #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_ADC1_SHIFT (24U)
4552 /*! ADC1 - ADC1
4553  *  0b00..Non-secure and non-privilege user access allowed
4554  *  0b01..Non-secure and privilege access allowed
4555  *  0b10..Secure and non-privilege user access allowed
4556  *  0b11..Secure and privilege user access allowed
4557  */
4558 #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_ADC1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_ADC1_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_ADC1_MASK)
4559 
4560 #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_DAC0_MASK (0x30000000U)
4561 #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_DAC0_SHIFT (28U)
4562 /*! DAC0 - DAC0
4563  *  0b00..Non-secure and non-privilege user access allowed
4564  *  0b01..Non-secure and privilege access allowed
4565  *  0b10..Secure and non-privilege user access allowed
4566  *  0b11..Secure and privilege user access allowed
4567  */
4568 #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_DAC0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_DAC0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_DAC0_MASK)
4569 /*! @} */
4570 
4571 /*! @name AIPS_BRIDGE_GROUP4_MEM_RULE2 - AIPS Bridge Group 4 Rule 2 */
4572 /*! @{ */
4573 
4574 #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_OPAMP0_MASK (0x3U)
4575 #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_OPAMP0_SHIFT (0U)
4576 /*! OPAMP0 - OPAMP0
4577  *  0b00..Non-secure and non-privilege user access allowed
4578  *  0b01..Non-secure and privilege access allowed
4579  *  0b10..Secure and non-privilege user access allowed
4580  *  0b11..Secure and privilege user access allowed
4581  */
4582 #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_OPAMP0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_OPAMP0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_OPAMP0_MASK)
4583 
4584 #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_VREF_MASK (0x30U)
4585 #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_VREF_SHIFT (4U)
4586 /*! VREF - VREF
4587  *  0b00..Non-secure and non-privilege user access allowed
4588  *  0b01..Non-secure and privilege access allowed
4589  *  0b10..Secure and non-privilege user access allowed
4590  *  0b11..Secure and privilege user access allowed
4591  */
4592 #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_VREF(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_VREF_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_VREF_MASK)
4593 
4594 #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_DAC_MASK (0x300U)
4595 #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_DAC_SHIFT (8U)
4596 /*! DAC - DAC
4597  *  0b00..Non-secure and non-privilege user access allowed
4598  *  0b01..Non-secure and privilege access allowed
4599  *  0b10..Secure and non-privilege user access allowed
4600  *  0b11..Secure and privilege user access allowed
4601  */
4602 #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_DAC(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_DAC_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_DAC_MASK)
4603 
4604 #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_OPAMP1_MASK (0x3000U)
4605 #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_OPAMP1_SHIFT (12U)
4606 /*! OPAMP1 - OPAMP1
4607  *  0b00..Non-secure and non-privilege user access allowed
4608  *  0b01..Non-secure and privilege access allowed
4609  *  0b10..Secure and non-privilege user access allowed
4610  *  0b11..Secure and privilege user access allowed
4611  */
4612 #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_OPAMP1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_OPAMP1_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_OPAMP1_MASK)
4613 
4614 #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_HPDAC0_MASK (0x30000U)
4615 #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_HPDAC0_SHIFT (16U)
4616 /*! HPDAC0 - HPDAC0
4617  *  0b00..Non-secure and non-privilege user access allowed
4618  *  0b01..Non-secure and privilege access allowed
4619  *  0b10..Secure and non-privilege user access allowed
4620  *  0b11..Secure and privilege user access allowed
4621  */
4622 #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_HPDAC0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_HPDAC0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_HPDAC0_MASK)
4623 
4624 #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_OPAMP2_MASK (0x300000U)
4625 #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_OPAMP2_SHIFT (20U)
4626 /*! OPAMP2 - OPAMP2
4627  *  0b00..Non-secure and non-privilege user access allowed
4628  *  0b01..Non-secure and privilege access allowed
4629  *  0b10..Secure and non-privilege user access allowed
4630  *  0b11..Secure and privilege user access allowed
4631  */
4632 #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_OPAMP2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_OPAMP2_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_OPAMP2_MASK)
4633 
4634 #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_PORT0_MASK (0x3000000U)
4635 #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_PORT0_SHIFT (24U)
4636 /*! PORT0 - PORT0
4637  *  0b00..Non-secure and non-privilege user access allowed
4638  *  0b01..Non-secure and privilege access allowed
4639  *  0b10..Secure and non-privilege user access allowed
4640  *  0b11..Secure and privilege user access allowed
4641  */
4642 #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_PORT0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_PORT0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_PORT0_MASK)
4643 
4644 #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_PORT1_MASK (0x30000000U)
4645 #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_PORT1_SHIFT (28U)
4646 /*! PORT1 - PORT1
4647  *  0b00..Non-secure and non-privilege user access allowed
4648  *  0b01..Non-secure and privilege access allowed
4649  *  0b10..Secure and non-privilege user access allowed
4650  *  0b11..Secure and privilege user access allowed
4651  */
4652 #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_PORT1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_PORT1_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_PORT1_MASK)
4653 /*! @} */
4654 
4655 /*! @name AIPS_BRIDGE_GROUP4_MEM_RULE3 - AIPS Bridge Group 4 Rule 3 */
4656 /*! @{ */
4657 
4658 #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_PORT2_MASK (0x3U)
4659 #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_PORT2_SHIFT (0U)
4660 /*! PORT2 - PORT2
4661  *  0b00..Non-secure and non-privilege user access allowed
4662  *  0b01..Non-secure and privilege access allowed
4663  *  0b10..Secure and non-privilege user access allowed
4664  *  0b11..Secure and privilege user access allowed
4665  */
4666 #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_PORT2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_PORT2_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_PORT2_MASK)
4667 
4668 #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_PORT3_MASK (0x30U)
4669 #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_PORT3_SHIFT (4U)
4670 /*! PORT3 - PORT3
4671  *  0b00..Non-secure and non-privilege user access allowed
4672  *  0b01..Non-secure and privilege access allowed
4673  *  0b10..Secure and non-privilege user access allowed
4674  *  0b11..Secure and privilege user access allowed
4675  */
4676 #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_PORT3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_PORT3_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_PORT3_MASK)
4677 
4678 #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_PORT4_MASK (0x300U)
4679 #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_PORT4_SHIFT (8U)
4680 /*! PORT4 - PORT4
4681  *  0b00..Non-secure and non-privilege user access allowed
4682  *  0b01..Non-secure and privilege access allowed
4683  *  0b10..Secure and non-privilege user access allowed
4684  *  0b11..Secure and privilege user access allowed
4685  */
4686 #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_PORT4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_PORT4_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_PORT4_MASK)
4687 
4688 #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_MTR0_MASK (0x3000000U)
4689 #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_MTR0_SHIFT (24U)
4690 /*! MTR0 - MTR0
4691  *  0b00..Non-secure and non-privilege user access allowed
4692  *  0b01..Non-secure and privilege access allowed
4693  *  0b10..Secure and non-privilege user access allowed
4694  *  0b11..Secure and privilege user access allowed
4695  */
4696 #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_MTR0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_MTR0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_MTR0_MASK)
4697 
4698 #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_ATX0_MASK (0x30000000U)
4699 #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_ATX0_SHIFT (28U)
4700 /*! ATX0 - ATX0
4701  *  0b00..Non-secure and non-privilege user access allowed
4702  *  0b01..Non-secure and privilege access allowed
4703  *  0b10..Secure and non-privilege user access allowed
4704  *  0b11..Secure and privilege user access allowed
4705  */
4706 #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_ATX0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_ATX0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_ATX0_MASK)
4707 /*! @} */
4708 
4709 /*! @name AHB_SECURE_CTRL_PERIPHERAL_RULE0 - AHB Secure Control Peripheral Rule 0 */
4710 /*! @{ */
4711 
4712 #define AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE0_MASK (0x3U)
4713 #define AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE0_SHIFT (0U)
4714 /*! RULE0 - Rule 0
4715  *  0b00..Non-secure and non-privilege user access allowed
4716  *  0b01..Non-secure and privilege access allowed
4717  *  0b10..Secure and non-privilege user access allowed
4718  *  0b11..Secure and privilege user access allowed
4719  */
4720 #define AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE0_SHIFT)) & AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE0_MASK)
4721 
4722 #define AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE1_MASK (0x30U)
4723 #define AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE1_SHIFT (4U)
4724 /*! RULE1 - Rule 1
4725  *  0b00..Non-secure and non-privilege user access allowed
4726  *  0b01..Non-secure and privilege access allowed
4727  *  0b10..Secure and non-privilege user access allowed
4728  *  0b11..Secure and privilege user access allowed
4729  */
4730 #define AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE1_SHIFT)) & AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE1_MASK)
4731 
4732 #define AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE2_MASK (0x300U)
4733 #define AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE2_SHIFT (8U)
4734 /*! RULE2 - Rule 2
4735  *  0b00..Non-secure and non-privilege user access allowed
4736  *  0b01..Non-secure and privilege access allowed
4737  *  0b10..Secure and non-privilege user access allowed
4738  *  0b11..Secure and privilege user access allowed
4739  */
4740 #define AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE2_SHIFT)) & AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE2_MASK)
4741 
4742 #define AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE3_MASK (0x3000U)
4743 #define AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE3_SHIFT (12U)
4744 /*! RULE3 - Rule 3
4745  *  0b00..Non-secure and non-privilege user access allowed
4746  *  0b01..Non-secure and privilege access allowed
4747  *  0b10..Secure and non-privilege user access allowed
4748  *  0b11..Secure and privilege user access allowed
4749  */
4750 #define AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE3_SHIFT)) & AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE3_MASK)
4751 /*! @} */
4752 
4753 /*! @name FLEXSPI0_REGION0_MEM_RULE - FLEXSPI0 Region 0 Memory Rule */
4754 /*! @{ */
4755 
4756 #define AHBSC_FLEXSPI0_REGION0_MEM_RULE_RULE0_MASK (0x3U)
4757 #define AHBSC_FLEXSPI0_REGION0_MEM_RULE_RULE0_SHIFT (0U)
4758 /*! RULE0 - Rule 0
4759  *  0b00..Non-secure and non-privilege user access allowed
4760  *  0b01..Non-secure and privilege access allowed
4761  *  0b10..Secure and non-privilege user access allowed
4762  *  0b11..Secure and privilege user access allowed
4763  */
4764 #define AHBSC_FLEXSPI0_REGION0_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLEXSPI0_REGION0_MEM_RULE_RULE0_SHIFT)) & AHBSC_FLEXSPI0_REGION0_MEM_RULE_RULE0_MASK)
4765 
4766 #define AHBSC_FLEXSPI0_REGION0_MEM_RULE_RULE1_MASK (0x30U)
4767 #define AHBSC_FLEXSPI0_REGION0_MEM_RULE_RULE1_SHIFT (4U)
4768 /*! RULE1 - Rule 1
4769  *  0b00..Non-secure and non-privilege user access allowed
4770  *  0b01..Non-secure and privilege access allowed
4771  *  0b10..Secure and non-privilege user access allowed
4772  *  0b11..Secure and privilege user access allowed
4773  */
4774 #define AHBSC_FLEXSPI0_REGION0_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLEXSPI0_REGION0_MEM_RULE_RULE1_SHIFT)) & AHBSC_FLEXSPI0_REGION0_MEM_RULE_RULE1_MASK)
4775 
4776 #define AHBSC_FLEXSPI0_REGION0_MEM_RULE_RULE2_MASK (0x300U)
4777 #define AHBSC_FLEXSPI0_REGION0_MEM_RULE_RULE2_SHIFT (8U)
4778 /*! RULE2 - Rule 2
4779  *  0b00..Non-secure and non-privilege user access allowed
4780  *  0b01..Non-secure and privilege access allowed
4781  *  0b10..Secure and non-privilege user access allowed
4782  *  0b11..Secure and privilege user access allowed
4783  */
4784 #define AHBSC_FLEXSPI0_REGION0_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLEXSPI0_REGION0_MEM_RULE_RULE2_SHIFT)) & AHBSC_FLEXSPI0_REGION0_MEM_RULE_RULE2_MASK)
4785 
4786 #define AHBSC_FLEXSPI0_REGION0_MEM_RULE_RULE3_MASK (0x3000U)
4787 #define AHBSC_FLEXSPI0_REGION0_MEM_RULE_RULE3_SHIFT (12U)
4788 /*! RULE3 - Rule 3
4789  *  0b00..Non-secure and non-privilege user access allowed
4790  *  0b01..Non-secure and privilege access allowed
4791  *  0b10..Secure and non-privilege user access allowed
4792  *  0b11..Secure and privilege user access allowed
4793  */
4794 #define AHBSC_FLEXSPI0_REGION0_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLEXSPI0_REGION0_MEM_RULE_RULE3_SHIFT)) & AHBSC_FLEXSPI0_REGION0_MEM_RULE_RULE3_MASK)
4795 
4796 #define AHBSC_FLEXSPI0_REGION0_MEM_RULE_RULE4_MASK (0x30000U)
4797 #define AHBSC_FLEXSPI0_REGION0_MEM_RULE_RULE4_SHIFT (16U)
4798 /*! RULE4 - Rule 4
4799  *  0b00..Non-secure and non-privilege user access allowed
4800  *  0b01..Non-secure and privilege access allowed
4801  *  0b10..Secure and non-privilege user access allowed
4802  *  0b11..Secure and privilege user access allowed
4803  */
4804 #define AHBSC_FLEXSPI0_REGION0_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLEXSPI0_REGION0_MEM_RULE_RULE4_SHIFT)) & AHBSC_FLEXSPI0_REGION0_MEM_RULE_RULE4_MASK)
4805 
4806 #define AHBSC_FLEXSPI0_REGION0_MEM_RULE_RULE5_MASK (0x300000U)
4807 #define AHBSC_FLEXSPI0_REGION0_MEM_RULE_RULE5_SHIFT (20U)
4808 /*! RULE5 - Rule 5
4809  *  0b00..Non-secure and non-privilege user access allowed
4810  *  0b01..Non-secure and privilege access allowed
4811  *  0b10..Secure and non-privilege user access allowed
4812  *  0b11..Secure and privilege user access allowed
4813  */
4814 #define AHBSC_FLEXSPI0_REGION0_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLEXSPI0_REGION0_MEM_RULE_RULE5_SHIFT)) & AHBSC_FLEXSPI0_REGION0_MEM_RULE_RULE5_MASK)
4815 
4816 #define AHBSC_FLEXSPI0_REGION0_MEM_RULE_RULE6_MASK (0x3000000U)
4817 #define AHBSC_FLEXSPI0_REGION0_MEM_RULE_RULE6_SHIFT (24U)
4818 /*! RULE6 - Rule 6
4819  *  0b00..Non-secure and non-privilege user access allowed
4820  *  0b01..Non-secure and privilege access allowed
4821  *  0b10..Secure and non-privilege user access allowed
4822  *  0b11..Secure and privilege user access allowed
4823  */
4824 #define AHBSC_FLEXSPI0_REGION0_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLEXSPI0_REGION0_MEM_RULE_RULE6_SHIFT)) & AHBSC_FLEXSPI0_REGION0_MEM_RULE_RULE6_MASK)
4825 
4826 #define AHBSC_FLEXSPI0_REGION0_MEM_RULE_RULE7_MASK (0x30000000U)
4827 #define AHBSC_FLEXSPI0_REGION0_MEM_RULE_RULE7_SHIFT (28U)
4828 /*! RULE7 - Rule 7
4829  *  0b00..Non-secure and non-privilege user access allowed
4830  *  0b01..Non-secure and privilege access allowed
4831  *  0b10..Secure and non-privilege user access allowed
4832  *  0b11..Secure and privilege user access allowed
4833  */
4834 #define AHBSC_FLEXSPI0_REGION0_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLEXSPI0_REGION0_MEM_RULE_RULE7_SHIFT)) & AHBSC_FLEXSPI0_REGION0_MEM_RULE_RULE7_MASK)
4835 /*! @} */
4836 
4837 /* The count of AHBSC_FLEXSPI0_REGION0_MEM_RULE */
4838 #define AHBSC_FLEXSPI0_REGION0_MEM_RULE_COUNT    (4U)
4839 
4840 /*! @name FLEXSPI0_REGION1_6_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0 - FLEXSPI0 Region 1 Memory Rule 0..FLEXSPI0 Region 6 Memory Rule 0 */
4841 /*! @{ */
4842 
4843 #define AHBSC_FLEXSPI0_REGION1_6_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE0_MASK (0x3U)
4844 #define AHBSC_FLEXSPI0_REGION1_6_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE0_SHIFT (0U)
4845 /*! RULE0 - Rule 0
4846  *  0b00..Non-secure and non-privilege user access allowed
4847  *  0b01..Non-secure and privilege access allowed
4848  *  0b10..Secure and non-privilege user access allowed
4849  *  0b11..Secure and privilege user access allowed
4850  */
4851 #define AHBSC_FLEXSPI0_REGION1_6_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLEXSPI0_REGION1_6_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE0_SHIFT)) & AHBSC_FLEXSPI0_REGION1_6_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE0_MASK)
4852 
4853 #define AHBSC_FLEXSPI0_REGION1_6_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE1_MASK (0x30U)
4854 #define AHBSC_FLEXSPI0_REGION1_6_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE1_SHIFT (4U)
4855 /*! RULE1 - Rule 1
4856  *  0b00..Non-secure and non-privilege user access allowed
4857  *  0b01..Non-secure and privilege access allowed
4858  *  0b10..Secure and non-privilege user access allowed
4859  *  0b11..Secure and privilege user access allowed
4860  */
4861 #define AHBSC_FLEXSPI0_REGION1_6_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLEXSPI0_REGION1_6_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE1_SHIFT)) & AHBSC_FLEXSPI0_REGION1_6_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE1_MASK)
4862 
4863 #define AHBSC_FLEXSPI0_REGION1_6_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE2_MASK (0x300U)
4864 #define AHBSC_FLEXSPI0_REGION1_6_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE2_SHIFT (8U)
4865 /*! RULE2 - Rule 2
4866  *  0b00..Non-secure and non-privilege user access allowed
4867  *  0b01..Non-secure and privilege access allowed
4868  *  0b10..Secure and non-privilege user access allowed
4869  *  0b11..Secure and privilege user access allowed
4870  */
4871 #define AHBSC_FLEXSPI0_REGION1_6_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLEXSPI0_REGION1_6_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE2_SHIFT)) & AHBSC_FLEXSPI0_REGION1_6_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE2_MASK)
4872 
4873 #define AHBSC_FLEXSPI0_REGION1_6_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE3_MASK (0x3000U)
4874 #define AHBSC_FLEXSPI0_REGION1_6_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE3_SHIFT (12U)
4875 /*! RULE3 - Rule 3
4876  *  0b00..Non-secure and non-privilege user access allowed
4877  *  0b01..Non-secure and privilege access allowed
4878  *  0b10..Secure and non-privilege user access allowed
4879  *  0b11..Secure and privilege user access allowed
4880  */
4881 #define AHBSC_FLEXSPI0_REGION1_6_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLEXSPI0_REGION1_6_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE3_SHIFT)) & AHBSC_FLEXSPI0_REGION1_6_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE3_MASK)
4882 
4883 #define AHBSC_FLEXSPI0_REGION1_6_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE4_MASK (0x30000U)
4884 #define AHBSC_FLEXSPI0_REGION1_6_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE4_SHIFT (16U)
4885 /*! RULE4 - Rule 4
4886  *  0b00..Non-secure and non-privilege user access allowed
4887  *  0b01..Non-secure and privilege access allowed
4888  *  0b10..Secure and non-privilege user access allowed
4889  *  0b11..Secure and privilege user access allowed
4890  */
4891 #define AHBSC_FLEXSPI0_REGION1_6_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLEXSPI0_REGION1_6_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE4_SHIFT)) & AHBSC_FLEXSPI0_REGION1_6_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE4_MASK)
4892 
4893 #define AHBSC_FLEXSPI0_REGION1_6_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE5_MASK (0x300000U)
4894 #define AHBSC_FLEXSPI0_REGION1_6_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE5_SHIFT (20U)
4895 /*! RULE5 - Rule 5
4896  *  0b00..Non-secure and non-privilege user access allowed
4897  *  0b01..Non-secure and privilege access allowed
4898  *  0b10..Secure and non-privilege user access allowed
4899  *  0b11..Secure and privilege user access allowed
4900  */
4901 #define AHBSC_FLEXSPI0_REGION1_6_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLEXSPI0_REGION1_6_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE5_SHIFT)) & AHBSC_FLEXSPI0_REGION1_6_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE5_MASK)
4902 /*! @} */
4903 
4904 /* The count of AHBSC_FLEXSPI0_REGION1_6_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0 */
4905 #define AHBSC_FLEXSPI0_REGION1_6_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_COUNT (6U)
4906 
4907 /*! @name FLEXSPI0_REGION7_MEM_RULE - FLEXSPI0 Region 7 Memory Rule */
4908 /*! @{ */
4909 
4910 #define AHBSC_FLEXSPI0_REGION7_MEM_RULE_RULE0_MASK (0x3U)
4911 #define AHBSC_FLEXSPI0_REGION7_MEM_RULE_RULE0_SHIFT (0U)
4912 /*! RULE0 - Rule 0
4913  *  0b00..Non-secure and non-privilege user access allowed
4914  *  0b01..Non-secure and privilege access allowed
4915  *  0b10..Secure and non-privilege user access allowed
4916  *  0b11..Secure and privilege user access allowed
4917  */
4918 #define AHBSC_FLEXSPI0_REGION7_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLEXSPI0_REGION7_MEM_RULE_RULE0_SHIFT)) & AHBSC_FLEXSPI0_REGION7_MEM_RULE_RULE0_MASK)
4919 
4920 #define AHBSC_FLEXSPI0_REGION7_MEM_RULE_RULE1_MASK (0x30U)
4921 #define AHBSC_FLEXSPI0_REGION7_MEM_RULE_RULE1_SHIFT (4U)
4922 /*! RULE1 - Rule 1
4923  *  0b00..Non-secure and non-privilege user access allowed
4924  *  0b01..Non-secure and privilege access allowed
4925  *  0b10..Secure and non-privilege user access allowed
4926  *  0b11..Secure and privilege user access allowed
4927  */
4928 #define AHBSC_FLEXSPI0_REGION7_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLEXSPI0_REGION7_MEM_RULE_RULE1_SHIFT)) & AHBSC_FLEXSPI0_REGION7_MEM_RULE_RULE1_MASK)
4929 
4930 #define AHBSC_FLEXSPI0_REGION7_MEM_RULE_RULE2_MASK (0x300U)
4931 #define AHBSC_FLEXSPI0_REGION7_MEM_RULE_RULE2_SHIFT (8U)
4932 /*! RULE2 - Rule 2
4933  *  0b00..Non-secure and non-privilege user access allowed
4934  *  0b01..Non-secure and privilege access allowed
4935  *  0b10..Secure and non-privilege user access allowed
4936  *  0b11..Secure and privilege user access allowed
4937  */
4938 #define AHBSC_FLEXSPI0_REGION7_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLEXSPI0_REGION7_MEM_RULE_RULE2_SHIFT)) & AHBSC_FLEXSPI0_REGION7_MEM_RULE_RULE2_MASK)
4939 
4940 #define AHBSC_FLEXSPI0_REGION7_MEM_RULE_RULE3_MASK (0x3000U)
4941 #define AHBSC_FLEXSPI0_REGION7_MEM_RULE_RULE3_SHIFT (12U)
4942 /*! RULE3 - Rule 3
4943  *  0b00..Non-secure and non-privilege user access allowed
4944  *  0b01..Non-secure and privilege access allowed
4945  *  0b10..Secure and non-privilege user access allowed
4946  *  0b11..Secure and privilege user access allowed
4947  */
4948 #define AHBSC_FLEXSPI0_REGION7_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLEXSPI0_REGION7_MEM_RULE_RULE3_SHIFT)) & AHBSC_FLEXSPI0_REGION7_MEM_RULE_RULE3_MASK)
4949 
4950 #define AHBSC_FLEXSPI0_REGION7_MEM_RULE_RULE4_MASK (0x30000U)
4951 #define AHBSC_FLEXSPI0_REGION7_MEM_RULE_RULE4_SHIFT (16U)
4952 /*! RULE4 - Rule 4
4953  *  0b00..Non-secure and non-privilege user access allowed
4954  *  0b01..Non-secure and privilege access allowed
4955  *  0b10..Secure and non-privilege user access allowed
4956  *  0b11..Secure and privilege user access allowed
4957  */
4958 #define AHBSC_FLEXSPI0_REGION7_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLEXSPI0_REGION7_MEM_RULE_RULE4_SHIFT)) & AHBSC_FLEXSPI0_REGION7_MEM_RULE_RULE4_MASK)
4959 
4960 #define AHBSC_FLEXSPI0_REGION7_MEM_RULE_RULE5_MASK (0x300000U)
4961 #define AHBSC_FLEXSPI0_REGION7_MEM_RULE_RULE5_SHIFT (20U)
4962 /*! RULE5 - Rule 5
4963  *  0b00..Non-secure and non-privilege user access allowed
4964  *  0b01..Non-secure and privilege access allowed
4965  *  0b10..Secure and non-privilege user access allowed
4966  *  0b11..Secure and privilege user access allowed
4967  */
4968 #define AHBSC_FLEXSPI0_REGION7_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLEXSPI0_REGION7_MEM_RULE_RULE5_SHIFT)) & AHBSC_FLEXSPI0_REGION7_MEM_RULE_RULE5_MASK)
4969 
4970 #define AHBSC_FLEXSPI0_REGION7_MEM_RULE_RULE6_MASK (0x3000000U)
4971 #define AHBSC_FLEXSPI0_REGION7_MEM_RULE_RULE6_SHIFT (24U)
4972 /*! RULE6 - Rule 6
4973  *  0b00..Non-secure and non-privilege user access allowed
4974  *  0b01..Non-secure and privilege access allowed
4975  *  0b10..Secure and non-privilege user access allowed
4976  *  0b11..Secure and privilege user access allowed
4977  */
4978 #define AHBSC_FLEXSPI0_REGION7_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLEXSPI0_REGION7_MEM_RULE_RULE6_SHIFT)) & AHBSC_FLEXSPI0_REGION7_MEM_RULE_RULE6_MASK)
4979 
4980 #define AHBSC_FLEXSPI0_REGION7_MEM_RULE_RULE7_MASK (0x30000000U)
4981 #define AHBSC_FLEXSPI0_REGION7_MEM_RULE_RULE7_SHIFT (28U)
4982 /*! RULE7 - Rule 7
4983  *  0b00..Non-secure and non-privilege user access allowed
4984  *  0b01..Non-secure and privilege access allowed
4985  *  0b10..Secure and non-privilege user access allowed
4986  *  0b11..Secure and privilege user access allowed
4987  */
4988 #define AHBSC_FLEXSPI0_REGION7_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLEXSPI0_REGION7_MEM_RULE_RULE7_SHIFT)) & AHBSC_FLEXSPI0_REGION7_MEM_RULE_RULE7_MASK)
4989 /*! @} */
4990 
4991 /* The count of AHBSC_FLEXSPI0_REGION7_MEM_RULE */
4992 #define AHBSC_FLEXSPI0_REGION7_MEM_RULE_COUNT    (4U)
4993 
4994 /*! @name FLEXSPI0_REGION8_13_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0 - FLEXSPI0 Region 8 Memory Rule 0..FLEXSPI0 Region 13 Memory Rule 0 */
4995 /*! @{ */
4996 
4997 #define AHBSC_FLEXSPI0_REGION8_13_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE0_MASK (0x3U)
4998 #define AHBSC_FLEXSPI0_REGION8_13_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE0_SHIFT (0U)
4999 /*! RULE0 - Rule 0
5000  *  0b00..Non-secure and non-privilege user access allowed
5001  *  0b01..Non-secure and privilege access allowed
5002  *  0b10..Secure and non-privilege user access allowed
5003  *  0b11..Secure and privilege user access allowed
5004  */
5005 #define AHBSC_FLEXSPI0_REGION8_13_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLEXSPI0_REGION8_13_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE0_SHIFT)) & AHBSC_FLEXSPI0_REGION8_13_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE0_MASK)
5006 
5007 #define AHBSC_FLEXSPI0_REGION8_13_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE1_MASK (0x30U)
5008 #define AHBSC_FLEXSPI0_REGION8_13_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE1_SHIFT (4U)
5009 /*! RULE1 - Rule 1
5010  *  0b00..Non-secure and non-privilege user access allowed
5011  *  0b01..Non-secure and privilege access allowed
5012  *  0b10..Secure and non-privilege user access allowed
5013  *  0b11..Secure and privilege user access allowed
5014  */
5015 #define AHBSC_FLEXSPI0_REGION8_13_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLEXSPI0_REGION8_13_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE1_SHIFT)) & AHBSC_FLEXSPI0_REGION8_13_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE1_MASK)
5016 
5017 #define AHBSC_FLEXSPI0_REGION8_13_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE2_MASK (0x300U)
5018 #define AHBSC_FLEXSPI0_REGION8_13_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE2_SHIFT (8U)
5019 /*! RULE2 - Rule 2
5020  *  0b00..Non-secure and non-privilege user access allowed
5021  *  0b01..Non-secure and privilege access allowed
5022  *  0b10..Secure and non-privilege user access allowed
5023  *  0b11..Secure and privilege user access allowed
5024  */
5025 #define AHBSC_FLEXSPI0_REGION8_13_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLEXSPI0_REGION8_13_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE2_SHIFT)) & AHBSC_FLEXSPI0_REGION8_13_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE2_MASK)
5026 
5027 #define AHBSC_FLEXSPI0_REGION8_13_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE3_MASK (0x3000U)
5028 #define AHBSC_FLEXSPI0_REGION8_13_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE3_SHIFT (12U)
5029 /*! RULE3 - Rule 3
5030  *  0b00..Non-secure and non-privilege user access allowed
5031  *  0b01..Non-secure and privilege access allowed
5032  *  0b10..Secure and non-privilege user access allowed
5033  *  0b11..Secure and privilege user access allowed
5034  */
5035 #define AHBSC_FLEXSPI0_REGION8_13_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLEXSPI0_REGION8_13_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE3_SHIFT)) & AHBSC_FLEXSPI0_REGION8_13_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE3_MASK)
5036 
5037 #define AHBSC_FLEXSPI0_REGION8_13_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE4_MASK (0x30000U)
5038 #define AHBSC_FLEXSPI0_REGION8_13_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE4_SHIFT (16U)
5039 /*! RULE4 - Rule 4
5040  *  0b00..Non-secure and non-privilege user access allowed
5041  *  0b01..Non-secure and privilege access allowed
5042  *  0b10..Secure and non-privilege user access allowed
5043  *  0b11..Secure and privilege user access allowed
5044  */
5045 #define AHBSC_FLEXSPI0_REGION8_13_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLEXSPI0_REGION8_13_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE4_SHIFT)) & AHBSC_FLEXSPI0_REGION8_13_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE4_MASK)
5046 
5047 #define AHBSC_FLEXSPI0_REGION8_13_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE5_MASK (0x300000U)
5048 #define AHBSC_FLEXSPI0_REGION8_13_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE5_SHIFT (20U)
5049 /*! RULE5 - Rule 5
5050  *  0b00..Non-secure and non-privilege user access allowed
5051  *  0b01..Non-secure and privilege access allowed
5052  *  0b10..Secure and non-privilege user access allowed
5053  *  0b11..Secure and privilege user access allowed
5054  */
5055 #define AHBSC_FLEXSPI0_REGION8_13_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLEXSPI0_REGION8_13_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE5_SHIFT)) & AHBSC_FLEXSPI0_REGION8_13_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE5_MASK)
5056 /*! @} */
5057 
5058 /* The count of AHBSC_FLEXSPI0_REGION8_13_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0 */
5059 #define AHBSC_FLEXSPI0_REGION8_13_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_COUNT (6U)
5060 
5061 /*! @name SEC_VIO_ADDRN_SEC_VIO_ADDR - Security Violation Address */
5062 /*! @{ */
5063 
5064 #define AHBSC_SEC_VIO_ADDRN_SEC_VIO_ADDR_SEC_VIO_ADDR_MASK (0xFFFFFFFFU)
5065 #define AHBSC_SEC_VIO_ADDRN_SEC_VIO_ADDR_SEC_VIO_ADDR_SHIFT (0U)
5066 /*! SEC_VIO_ADDR - Security violation address for AHB layer a reset value 0 */
5067 #define AHBSC_SEC_VIO_ADDRN_SEC_VIO_ADDR_SEC_VIO_ADDR(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_ADDRN_SEC_VIO_ADDR_SEC_VIO_ADDR_SHIFT)) & AHBSC_SEC_VIO_ADDRN_SEC_VIO_ADDR_SEC_VIO_ADDR_MASK)
5068 /*! @} */
5069 
5070 /* The count of AHBSC_SEC_VIO_ADDRN_SEC_VIO_ADDR */
5071 #define AHBSC_SEC_VIO_ADDRN_SEC_VIO_ADDR_COUNT   (32U)
5072 
5073 /*! @name SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO - Security Violation Miscellaneous Information at Address */
5074 /*! @{ */
5075 
5076 #define AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_MASK (0x1U)
5077 #define AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_SHIFT (0U)
5078 /*! SEC_VIO_INFO_WRITE - Security violation access read/write indicator
5079  *  0b0..Read access
5080  *  0b1..Write access
5081  */
5082 #define AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_SHIFT)) & AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_MASK)
5083 
5084 #define AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_MASK (0x2U)
5085 #define AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_SHIFT (1U)
5086 /*! SEC_VIO_INFO_DATA_ACCESS - Security Violation Info Data Access
5087  *  0b0..Code
5088  *  0b1..Data
5089  */
5090 #define AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_SHIFT)) & AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_MASK)
5091 
5092 #define AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_MASK (0xF0U)
5093 #define AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_SHIFT (4U)
5094 /*! SEC_VIO_INFO_MASTER_SEC_LEVEL - Security Violation Info Master Security Level */
5095 #define AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_SHIFT)) & AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_MASK)
5096 
5097 #define AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_MASK (0x1F00U)
5098 #define AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SHIFT (8U)
5099 /*! SEC_VIO_INFO_MASTER - Security violation master number
5100  *  0b00000..M33 Code
5101  *  0b00001..M33 System
5102  *  0b00010..CPU1 (Mirco-CM33) Code
5103  *  0b00011..SMARTDMA Instruction
5104  *  0b00100..CPU1 (Mirco-CM33) system
5105  *  0b00101..SMARTDMA Data
5106  *  0b00110..eDMA0
5107  *  0b00111..eDMA1
5108  *  0b01000..PKC
5109  *  0b01001..ELS S50
5110  *  0b01010..PKC M0
5111  *  0b01011..NPU Operands
5112  *  0b01100..DSP Instruction
5113  *  0b01101..DSPX
5114  *  0b01110..DSPY
5115  *  0b10000..NPU Data
5116  *  0b10001..USB FS
5117  *  0b10010..Ethernet
5118  *  0b10011..USB HS
5119  *  0b10100..uSDHC
5120  */
5121 #define AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SHIFT)) & AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_MASK)
5122 /*! @} */
5123 
5124 /* The count of AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO */
5125 #define AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_COUNT (32U)
5126 
5127 /*! @name SEC_VIO_INFO_VALID - Security Violation Info Validity for Address */
5128 /*! @{ */
5129 
5130 #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_MASK (0x1U)
5131 #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_SHIFT (0U)
5132 /*! VIO_INFO_VALID0 - Violation information valid flag for AHB port 0
5133  *  0b0..Not valid
5134  *  0b1..Valid
5135  */
5136 #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_MASK)
5137 
5138 #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_MASK (0x2U)
5139 #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_SHIFT (1U)
5140 /*! VIO_INFO_VALID1 - Violation information valid flag for AHB port 1
5141  *  0b0..Not valid
5142  *  0b1..Valid
5143  */
5144 #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_MASK)
5145 
5146 #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_MASK (0x4U)
5147 #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_SHIFT (2U)
5148 /*! VIO_INFO_VALID2 - Violation information valid flag for AHB port 2
5149  *  0b0..Not valid
5150  *  0b1..Valid
5151  */
5152 #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_MASK)
5153 
5154 #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_MASK (0x8U)
5155 #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_SHIFT (3U)
5156 /*! VIO_INFO_VALID3 - Violation information valid flag for AHB port 3
5157  *  0b0..Not valid
5158  *  0b1..Valid
5159  */
5160 #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_MASK)
5161 
5162 #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_MASK (0x10U)
5163 #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_SHIFT (4U)
5164 /*! VIO_INFO_VALID4 - Violation information valid flag for AHB port 4
5165  *  0b0..Not valid
5166  *  0b1..Valid
5167  */
5168 #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_MASK)
5169 
5170 #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_MASK (0x20U)
5171 #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_SHIFT (5U)
5172 /*! VIO_INFO_VALID5 - Violation information valid flag for AHB port 5
5173  *  0b0..Not valid
5174  *  0b1..Valid
5175  */
5176 #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID5(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_MASK)
5177 
5178 #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_MASK (0x40U)
5179 #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_SHIFT (6U)
5180 /*! VIO_INFO_VALID6 - Violation information valid flag for AHB port 6
5181  *  0b0..Not valid
5182  *  0b1..Valid
5183  */
5184 #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID6(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_MASK)
5185 
5186 #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_MASK (0x80U)
5187 #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_SHIFT (7U)
5188 /*! VIO_INFO_VALID7 - Violation information valid flag for AHB port 7
5189  *  0b0..Not valid
5190  *  0b1..Valid
5191  */
5192 #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID7(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_MASK)
5193 
5194 #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_MASK (0x100U)
5195 #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_SHIFT (8U)
5196 /*! VIO_INFO_VALID8 - Violation information valid flag for AHB port 8
5197  *  0b0..Not valid
5198  *  0b1..Valid
5199  */
5200 #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID8(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_MASK)
5201 
5202 #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_MASK (0x200U)
5203 #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_SHIFT (9U)
5204 /*! VIO_INFO_VALID9 - Violation information valid flag for AHB port 9
5205  *  0b0..Not valid
5206  *  0b1..Valid
5207  */
5208 #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID9(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_MASK)
5209 
5210 #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_MASK (0x400U)
5211 #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_SHIFT (10U)
5212 /*! VIO_INFO_VALID10 - Violation information valid flag for AHB port 10
5213  *  0b0..Not valid
5214  *  0b1..Valid
5215  */
5216 #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID10(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_MASK)
5217 
5218 #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_MASK (0x800U)
5219 #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_SHIFT (11U)
5220 /*! VIO_INFO_VALID11 - Violation information valid flag for AHB port 11
5221  *  0b0..Not valid
5222  *  0b1..Valid
5223  */
5224 #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID11(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_MASK)
5225 
5226 #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID12_MASK (0x1000U)
5227 #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID12_SHIFT (12U)
5228 /*! VIO_INFO_VALID12 - Violation information valid flag for AHB port 12
5229  *  0b0..Not valid
5230  *  0b1..Valid
5231  */
5232 #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID12(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID12_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID12_MASK)
5233 
5234 #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID13_MASK (0x2000U)
5235 #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID13_SHIFT (13U)
5236 /*! VIO_INFO_VALID13 - Violation information valid flag for AHB port 13
5237  *  0b0..Not valid
5238  *  0b1..Valid
5239  */
5240 #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID13(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID13_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID13_MASK)
5241 
5242 #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID14_MASK (0x4000U)
5243 #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID14_SHIFT (14U)
5244 /*! VIO_INFO_VALID14 - Violation information valid flag for AHB port 14
5245  *  0b0..Not valid
5246  *  0b1..Valid
5247  */
5248 #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID14(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID14_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID14_MASK)
5249 
5250 #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID15_MASK (0x8000U)
5251 #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID15_SHIFT (15U)
5252 /*! VIO_INFO_VALID15 - Violation information valid flag for AHB port 15
5253  *  0b0..Not valid
5254  *  0b1..Valid
5255  */
5256 #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID15(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID15_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID15_MASK)
5257 
5258 #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID16_MASK (0x10000U)
5259 #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID16_SHIFT (16U)
5260 /*! VIO_INFO_VALID16 - Violation information valid flag for AHB port 16
5261  *  0b0..Not valid
5262  *  0b1..Valid
5263  */
5264 #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID16(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID16_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID16_MASK)
5265 
5266 #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID17_MASK (0x20000U)
5267 #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID17_SHIFT (17U)
5268 /*! VIO_INFO_VALID17 - Violation information valid flag for AHB port 17
5269  *  0b0..Not valid
5270  *  0b1..Valid
5271  */
5272 #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID17(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID17_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID17_MASK)
5273 
5274 #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID18_MASK (0x40000U)
5275 #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID18_SHIFT (18U)
5276 /*! VIO_INFO_VALID18 - Violation information valid flag for AHB port 18
5277  *  0b0..Not valid
5278  *  0b1..Valid
5279  */
5280 #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID18(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID18_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID18_MASK)
5281 /*! @} */
5282 
5283 /*! @name SEC_GPIO_MASKN_SEC_GPIO_MASK - GPIO Mask for Port 0..GPIO Mask for Port 1 */
5284 /*! @{ */
5285 
5286 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN0_SEC_MASK_MASK (0x1U)
5287 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN0_SEC_MASK_SHIFT (0U)
5288 /*! PIO0_PIN0_SEC_MASK - Mask bit
5289  *  0b0..Masked
5290  *  0b1..Not masked
5291  */
5292 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN0_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN0_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN0_SEC_MASK_MASK)
5293 
5294 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN0_SEC_MASK_MASK (0x1U)
5295 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN0_SEC_MASK_SHIFT (0U)
5296 /*! PIO1_PIN0_SEC_MASK - Mask bit
5297  *  0b0..Masked
5298  *  0b1..Not masked
5299  */
5300 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN0_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN0_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN0_SEC_MASK_MASK)
5301 
5302 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN1_SEC_MASK_MASK (0x2U)
5303 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN1_SEC_MASK_SHIFT (1U)
5304 /*! PIO0_PIN1_SEC_MASK - Mask bit
5305  *  0b0..Masked
5306  *  0b1..Not masked
5307  */
5308 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN1_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN1_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN1_SEC_MASK_MASK)
5309 
5310 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN1_SEC_MASK_MASK (0x2U)
5311 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN1_SEC_MASK_SHIFT (1U)
5312 /*! PIO1_PIN1_SEC_MASK - Mask bit
5313  *  0b0..Masked
5314  *  0b1..Not masked
5315  */
5316 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN1_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN1_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN1_SEC_MASK_MASK)
5317 
5318 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN2_SEC_MASK_MASK (0x4U)
5319 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN2_SEC_MASK_SHIFT (2U)
5320 /*! PIO0_PIN2_SEC_MASK - Mask bit
5321  *  0b0..Masked
5322  *  0b1..Not masked
5323  */
5324 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN2_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN2_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN2_SEC_MASK_MASK)
5325 
5326 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN2_SEC_MASK_MASK (0x4U)
5327 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN2_SEC_MASK_SHIFT (2U)
5328 /*! PIO1_PIN2_SEC_MASK - Mask bit
5329  *  0b0..Masked
5330  *  0b1..Not masked
5331  */
5332 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN2_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN2_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN2_SEC_MASK_MASK)
5333 
5334 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN3_SEC_MASK_MASK (0x8U)
5335 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN3_SEC_MASK_SHIFT (3U)
5336 /*! PIO0_PIN3_SEC_MASK - Mask bit
5337  *  0b0..Masked
5338  *  0b1..Not masked
5339  */
5340 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN3_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN3_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN3_SEC_MASK_MASK)
5341 
5342 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN3_SEC_MASK_MASK (0x8U)
5343 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN3_SEC_MASK_SHIFT (3U)
5344 /*! PIO1_PIN3_SEC_MASK - Mask bit
5345  *  0b0..Masked
5346  *  0b1..Not masked
5347  */
5348 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN3_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN3_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN3_SEC_MASK_MASK)
5349 
5350 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN4_SEC_MASK_MASK (0x10U)
5351 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN4_SEC_MASK_SHIFT (4U)
5352 /*! PIO0_PIN4_SEC_MASK - Mask bit
5353  *  0b0..Masked
5354  *  0b1..Not masked
5355  */
5356 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN4_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN4_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN4_SEC_MASK_MASK)
5357 
5358 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN4_SEC_MASK_MASK (0x10U)
5359 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN4_SEC_MASK_SHIFT (4U)
5360 /*! PIO1_PIN4_SEC_MASK - Mask bit
5361  *  0b0..Masked
5362  *  0b1..Not masked
5363  */
5364 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN4_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN4_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN4_SEC_MASK_MASK)
5365 
5366 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN5_SEC_MASK_MASK (0x20U)
5367 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN5_SEC_MASK_SHIFT (5U)
5368 /*! PIO0_PIN5_SEC_MASK - Mask bit
5369  *  0b0..Masked
5370  *  0b1..Not masked
5371  */
5372 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN5_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN5_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN5_SEC_MASK_MASK)
5373 
5374 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN5_SEC_MASK_MASK (0x20U)
5375 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN5_SEC_MASK_SHIFT (5U)
5376 /*! PIO1_PIN5_SEC_MASK - Mask bit
5377  *  0b0..Masked
5378  *  0b1..Not masked
5379  */
5380 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN5_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN5_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN5_SEC_MASK_MASK)
5381 
5382 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN6_SEC_MASK_MASK (0x40U)
5383 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN6_SEC_MASK_SHIFT (6U)
5384 /*! PIO0_PIN6_SEC_MASK - Mask bit
5385  *  0b0..Masked
5386  *  0b1..Not masked
5387  */
5388 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN6_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN6_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN6_SEC_MASK_MASK)
5389 
5390 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN6_SEC_MASK_MASK (0x40U)
5391 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN6_SEC_MASK_SHIFT (6U)
5392 /*! PIO1_PIN6_SEC_MASK - Mask bit
5393  *  0b0..Masked
5394  *  0b1..Not masked
5395  */
5396 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN6_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN6_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN6_SEC_MASK_MASK)
5397 
5398 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN7_SEC_MASK_MASK (0x80U)
5399 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN7_SEC_MASK_SHIFT (7U)
5400 /*! PIO0_PIN7_SEC_MASK - Mask bit
5401  *  0b0..Masked
5402  *  0b1..Not masked
5403  */
5404 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN7_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN7_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN7_SEC_MASK_MASK)
5405 
5406 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN7_SEC_MASK_MASK (0x80U)
5407 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN7_SEC_MASK_SHIFT (7U)
5408 /*! PIO1_PIN7_SEC_MASK - Mask bit
5409  *  0b0..Masked
5410  *  0b1..Not masked
5411  */
5412 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN7_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN7_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN7_SEC_MASK_MASK)
5413 
5414 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN8_SEC_MASK_MASK (0x100U)
5415 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN8_SEC_MASK_SHIFT (8U)
5416 /*! PIO0_PIN8_SEC_MASK - Mask bit
5417  *  0b0..Masked
5418  *  0b1..Not masked
5419  */
5420 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN8_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN8_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN8_SEC_MASK_MASK)
5421 
5422 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN8_SEC_MASK_MASK (0x100U)
5423 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN8_SEC_MASK_SHIFT (8U)
5424 /*! PIO1_PIN8_SEC_MASK - Mask bit
5425  *  0b0..Masked
5426  *  0b1..Not masked
5427  */
5428 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN8_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN8_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN8_SEC_MASK_MASK)
5429 
5430 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN9_SEC_MASK_MASK (0x200U)
5431 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN9_SEC_MASK_SHIFT (9U)
5432 /*! PIO0_PIN9_SEC_MASK - Mask bit
5433  *  0b0..Masked
5434  *  0b1..Not masked
5435  */
5436 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN9_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN9_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN9_SEC_MASK_MASK)
5437 
5438 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN9_SEC_MASK_MASK (0x200U)
5439 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN9_SEC_MASK_SHIFT (9U)
5440 /*! PIO1_PIN9_SEC_MASK - Mask bit
5441  *  0b0..Masked
5442  *  0b1..Not masked
5443  */
5444 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN9_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN9_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN9_SEC_MASK_MASK)
5445 
5446 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN10_SEC_MASK_MASK (0x400U)
5447 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN10_SEC_MASK_SHIFT (10U)
5448 /*! PIO0_PIN10_SEC_MASK - Mask bit
5449  *  0b0..Masked
5450  *  0b1..Not masked
5451  */
5452 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN10_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN10_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN10_SEC_MASK_MASK)
5453 
5454 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN10_SEC_MASK_MASK (0x400U)
5455 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN10_SEC_MASK_SHIFT (10U)
5456 /*! PIO1_PIN10_SEC_MASK - Mask bit
5457  *  0b0..Masked
5458  *  0b1..Not masked
5459  */
5460 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN10_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN10_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN10_SEC_MASK_MASK)
5461 
5462 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN11_SEC_MASK_MASK (0x800U)
5463 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN11_SEC_MASK_SHIFT (11U)
5464 /*! PIO0_PIN11_SEC_MASK - Mask bit
5465  *  0b0..Masked
5466  *  0b1..Not masked
5467  */
5468 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN11_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN11_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN11_SEC_MASK_MASK)
5469 
5470 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN11_SEC_MASK_MASK (0x800U)
5471 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN11_SEC_MASK_SHIFT (11U)
5472 /*! PIO1_PIN11_SEC_MASK - Mask bit
5473  *  0b0..Masked
5474  *  0b1..Not masked
5475  */
5476 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN11_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN11_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN11_SEC_MASK_MASK)
5477 
5478 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN12_SEC_MASK_MASK (0x1000U)
5479 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN12_SEC_MASK_SHIFT (12U)
5480 /*! PIO0_PIN12_SEC_MASK - Mask bit
5481  *  0b0..Masked
5482  *  0b1..Not masked
5483  */
5484 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN12_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN12_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN12_SEC_MASK_MASK)
5485 
5486 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN12_SEC_MASK_MASK (0x1000U)
5487 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN12_SEC_MASK_SHIFT (12U)
5488 /*! PIO1_PIN12_SEC_MASK - Mask bit
5489  *  0b0..Masked
5490  *  0b1..Not masked
5491  */
5492 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN12_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN12_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN12_SEC_MASK_MASK)
5493 
5494 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN13_SEC_MASK_MASK (0x2000U)
5495 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN13_SEC_MASK_SHIFT (13U)
5496 /*! PIO0_PIN13_SEC_MASK - Mask bit
5497  *  0b0..Masked
5498  *  0b1..Not masked
5499  */
5500 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN13_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN13_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN13_SEC_MASK_MASK)
5501 
5502 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN13_SEC_MASK_MASK (0x2000U)
5503 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN13_SEC_MASK_SHIFT (13U)
5504 /*! PIO1_PIN13_SEC_MASK - Mask bit
5505  *  0b0..Masked
5506  *  0b1..Not masked
5507  */
5508 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN13_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN13_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN13_SEC_MASK_MASK)
5509 
5510 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN14_SEC_MASK_MASK (0x4000U)
5511 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN14_SEC_MASK_SHIFT (14U)
5512 /*! PIO0_PIN14_SEC_MASK - Mask bit
5513  *  0b0..Masked
5514  *  0b1..Not masked
5515  */
5516 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN14_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN14_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN14_SEC_MASK_MASK)
5517 
5518 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN14_SEC_MASK_MASK (0x4000U)
5519 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN14_SEC_MASK_SHIFT (14U)
5520 /*! PIO1_PIN14_SEC_MASK - Mask bit
5521  *  0b0..Masked
5522  *  0b1..Not masked
5523  */
5524 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN14_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN14_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN14_SEC_MASK_MASK)
5525 
5526 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN15_SEC_MASK_MASK (0x8000U)
5527 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN15_SEC_MASK_SHIFT (15U)
5528 /*! PIO0_PIN15_SEC_MASK - Mask bit
5529  *  0b0..Masked
5530  *  0b1..Not masked
5531  */
5532 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN15_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN15_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN15_SEC_MASK_MASK)
5533 
5534 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN15_SEC_MASK_MASK (0x8000U)
5535 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN15_SEC_MASK_SHIFT (15U)
5536 /*! PIO1_PIN15_SEC_MASK - Mask bit
5537  *  0b0..Masked
5538  *  0b1..Not masked
5539  */
5540 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN15_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN15_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN15_SEC_MASK_MASK)
5541 
5542 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN16_SEC_MASK_MASK (0x10000U)
5543 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN16_SEC_MASK_SHIFT (16U)
5544 /*! PIO0_PIN16_SEC_MASK - Mask bit
5545  *  0b0..Masked
5546  *  0b1..Not masked
5547  */
5548 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN16_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN16_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN16_SEC_MASK_MASK)
5549 
5550 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN16_SEC_MASK_MASK (0x10000U)
5551 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN16_SEC_MASK_SHIFT (16U)
5552 /*! PIO1_PIN16_SEC_MASK - Mask bit
5553  *  0b0..Masked
5554  *  0b1..Not masked
5555  */
5556 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN16_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN16_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN16_SEC_MASK_MASK)
5557 
5558 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN17_SEC_MASK_MASK (0x20000U)
5559 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN17_SEC_MASK_SHIFT (17U)
5560 /*! PIO0_PIN17_SEC_MASK - Mask bit
5561  *  0b0..Masked
5562  *  0b1..Not masked
5563  */
5564 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN17_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN17_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN17_SEC_MASK_MASK)
5565 
5566 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN17_SEC_MASK_MASK (0x20000U)
5567 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN17_SEC_MASK_SHIFT (17U)
5568 /*! PIO1_PIN17_SEC_MASK - Mask bit
5569  *  0b0..Masked
5570  *  0b1..Not masked
5571  */
5572 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN17_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN17_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN17_SEC_MASK_MASK)
5573 
5574 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN18_SEC_MASK_MASK (0x40000U)
5575 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN18_SEC_MASK_SHIFT (18U)
5576 /*! PIO0_PIN18_SEC_MASK - Mask bit
5577  *  0b0..Masked
5578  *  0b1..Not masked
5579  */
5580 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN18_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN18_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN18_SEC_MASK_MASK)
5581 
5582 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN18_SEC_MASK_MASK (0x40000U)
5583 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN18_SEC_MASK_SHIFT (18U)
5584 /*! PIO1_PIN18_SEC_MASK - Mask bit
5585  *  0b0..Masked
5586  *  0b1..Not masked
5587  */
5588 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN18_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN18_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN18_SEC_MASK_MASK)
5589 
5590 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN19_SEC_MASK_MASK (0x80000U)
5591 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN19_SEC_MASK_SHIFT (19U)
5592 /*! PIO0_PIN19_SEC_MASK - Mask bit
5593  *  0b0..Masked
5594  *  0b1..Not masked
5595  */
5596 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN19_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN19_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN19_SEC_MASK_MASK)
5597 
5598 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN19_SEC_MASK_MASK (0x80000U)
5599 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN19_SEC_MASK_SHIFT (19U)
5600 /*! PIO1_PIN19_SEC_MASK - Mask bit
5601  *  0b0..Masked
5602  *  0b1..Not masked
5603  */
5604 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN19_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN19_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN19_SEC_MASK_MASK)
5605 
5606 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN20_SEC_MASK_MASK (0x100000U)
5607 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN20_SEC_MASK_SHIFT (20U)
5608 /*! PIO0_PIN20_SEC_MASK - Mask bit
5609  *  0b0..Masked
5610  *  0b1..Not masked
5611  */
5612 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN20_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN20_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN20_SEC_MASK_MASK)
5613 
5614 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN20_SEC_MASK_MASK (0x100000U)
5615 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN20_SEC_MASK_SHIFT (20U)
5616 /*! PIO1_PIN20_SEC_MASK - Mask bit
5617  *  0b0..Masked
5618  *  0b1..Not masked
5619  */
5620 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN20_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN20_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN20_SEC_MASK_MASK)
5621 
5622 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN21_SEC_MASK_MASK (0x200000U)
5623 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN21_SEC_MASK_SHIFT (21U)
5624 /*! PIO0_PIN21_SEC_MASK - Mask bit
5625  *  0b0..Masked
5626  *  0b1..Not masked
5627  */
5628 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN21_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN21_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN21_SEC_MASK_MASK)
5629 
5630 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN21_SEC_MASK_MASK (0x200000U)
5631 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN21_SEC_MASK_SHIFT (21U)
5632 /*! PIO1_PIN21_SEC_MASK - Mask bit
5633  *  0b0..Masked
5634  *  0b1..Not masked
5635  */
5636 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN21_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN21_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN21_SEC_MASK_MASK)
5637 
5638 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN22_SEC_MASK_MASK (0x400000U)
5639 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN22_SEC_MASK_SHIFT (22U)
5640 /*! PIO0_PIN22_SEC_MASK - Mask bit
5641  *  0b0..Masked
5642  *  0b1..Not masked
5643  */
5644 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN22_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN22_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN22_SEC_MASK_MASK)
5645 
5646 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN22_SEC_MASK_MASK (0x400000U)
5647 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN22_SEC_MASK_SHIFT (22U)
5648 /*! PIO1_PIN22_SEC_MASK - Mask bit
5649  *  0b0..Masked
5650  *  0b1..Not masked
5651  */
5652 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN22_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN22_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN22_SEC_MASK_MASK)
5653 
5654 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN23_SEC_MASK_MASK (0x800000U)
5655 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN23_SEC_MASK_SHIFT (23U)
5656 /*! PIO0_PIN23_SEC_MASK - Mask bit
5657  *  0b0..Masked
5658  *  0b1..Not masked
5659  */
5660 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN23_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN23_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN23_SEC_MASK_MASK)
5661 
5662 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN23_SEC_MASK_MASK (0x800000U)
5663 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN23_SEC_MASK_SHIFT (23U)
5664 /*! PIO1_PIN23_SEC_MASK - Mask bit
5665  *  0b0..Masked
5666  *  0b1..Not masked
5667  */
5668 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN23_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN23_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN23_SEC_MASK_MASK)
5669 
5670 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN24_SEC_MASK_MASK (0x1000000U)
5671 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN24_SEC_MASK_SHIFT (24U)
5672 /*! PIO0_PIN24_SEC_MASK - Mask bit
5673  *  0b0..Masked
5674  *  0b1..Not masked
5675  */
5676 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN24_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN24_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN24_SEC_MASK_MASK)
5677 
5678 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN24_SEC_MASK_MASK (0x1000000U)
5679 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN24_SEC_MASK_SHIFT (24U)
5680 /*! PIO1_PIN24_SEC_MASK - Mask bit
5681  *  0b0..Masked
5682  *  0b1..Not masked
5683  */
5684 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN24_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN24_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN24_SEC_MASK_MASK)
5685 
5686 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN25_SEC_MASK_MASK (0x2000000U)
5687 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN25_SEC_MASK_SHIFT (25U)
5688 /*! PIO0_PIN25_SEC_MASK - Mask bit
5689  *  0b0..Masked
5690  *  0b1..Not masked
5691  */
5692 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN25_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN25_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN25_SEC_MASK_MASK)
5693 
5694 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN25_SEC_MASK_MASK (0x2000000U)
5695 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN25_SEC_MASK_SHIFT (25U)
5696 /*! PIO1_PIN25_SEC_MASK - Mask bit
5697  *  0b0..Masked
5698  *  0b1..Not masked
5699  */
5700 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN25_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN25_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN25_SEC_MASK_MASK)
5701 
5702 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN26_SEC_MASK_MASK (0x4000000U)
5703 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN26_SEC_MASK_SHIFT (26U)
5704 /*! PIO0_PIN26_SEC_MASK - Mask bit
5705  *  0b0..Masked
5706  *  0b1..Not masked
5707  */
5708 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN26_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN26_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN26_SEC_MASK_MASK)
5709 
5710 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN26_SEC_MASK_MASK (0x4000000U)
5711 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN26_SEC_MASK_SHIFT (26U)
5712 /*! PIO1_PIN26_SEC_MASK - Mask bit
5713  *  0b0..Masked
5714  *  0b1..Not masked
5715  */
5716 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN26_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN26_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN26_SEC_MASK_MASK)
5717 
5718 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN27_SEC_MASK_MASK (0x8000000U)
5719 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN27_SEC_MASK_SHIFT (27U)
5720 /*! PIO0_PIN27_SEC_MASK - Mask bit
5721  *  0b0..Masked
5722  *  0b1..Not masked
5723  */
5724 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN27_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN27_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN27_SEC_MASK_MASK)
5725 
5726 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN27_SEC_MASK_MASK (0x8000000U)
5727 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN27_SEC_MASK_SHIFT (27U)
5728 /*! PIO1_PIN27_SEC_MASK - Mask bit
5729  *  0b0..Masked
5730  *  0b1..Not masked
5731  */
5732 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN27_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN27_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN27_SEC_MASK_MASK)
5733 
5734 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN28_SEC_MASK_MASK (0x10000000U)
5735 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN28_SEC_MASK_SHIFT (28U)
5736 /*! PIO0_PIN28_SEC_MASK - Mask bit
5737  *  0b0..Masked
5738  *  0b1..Not masked
5739  */
5740 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN28_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN28_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN28_SEC_MASK_MASK)
5741 
5742 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN28_SEC_MASK_MASK (0x10000000U)
5743 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN28_SEC_MASK_SHIFT (28U)
5744 /*! PIO1_PIN28_SEC_MASK - Mask bit
5745  *  0b0..Masked
5746  *  0b1..Not masked
5747  */
5748 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN28_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN28_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN28_SEC_MASK_MASK)
5749 
5750 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN29_SEC_MASK_MASK (0x20000000U)
5751 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN29_SEC_MASK_SHIFT (29U)
5752 /*! PIO0_PIN29_SEC_MASK - Mask bit
5753  *  0b0..Masked
5754  *  0b1..Not masked
5755  */
5756 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN29_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN29_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN29_SEC_MASK_MASK)
5757 
5758 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN29_SEC_MASK_MASK (0x20000000U)
5759 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN29_SEC_MASK_SHIFT (29U)
5760 /*! PIO1_PIN29_SEC_MASK - Mask bit
5761  *  0b0..Masked
5762  *  0b1..Not masked
5763  */
5764 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN29_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN29_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN29_SEC_MASK_MASK)
5765 
5766 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN30_SEC_MASK_MASK (0x40000000U)
5767 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN30_SEC_MASK_SHIFT (30U)
5768 /*! PIO0_PIN30_SEC_MASK - Mask bit
5769  *  0b0..Masked
5770  *  0b1..Not masked
5771  */
5772 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN30_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN30_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN30_SEC_MASK_MASK)
5773 
5774 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN30_SEC_MASK_MASK (0x40000000U)
5775 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN30_SEC_MASK_SHIFT (30U)
5776 /*! PIO1_PIN30_SEC_MASK - Mask bit
5777  *  0b0..Masked
5778  *  0b1..Not masked
5779  */
5780 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN30_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN30_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN30_SEC_MASK_MASK)
5781 
5782 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN31_SEC_MASK_MASK (0x80000000U)
5783 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN31_SEC_MASK_SHIFT (31U)
5784 /*! PIO0_PIN31_SEC_MASK - Mask bit
5785  *  0b0..Masked
5786  *  0b1..Not masked
5787  */
5788 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN31_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN31_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN31_SEC_MASK_MASK)
5789 
5790 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN31_SEC_MASK_MASK (0x80000000U)
5791 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN31_SEC_MASK_SHIFT (31U)
5792 /*! PIO1_PIN31_SEC_MASK - Mask bit
5793  *  0b0..Masked
5794  *  0b1..Not masked
5795  */
5796 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN31_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN31_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN31_SEC_MASK_MASK)
5797 /*! @} */
5798 
5799 /* The count of AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK */
5800 #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_COUNT (2U)
5801 
5802 /*! @name SEC_CPU1_INT_MASK0 - Secure Interrupt Mask 0 for CPU1 */
5803 /*! @{ */
5804 
5805 #define AHBSC_SEC_CPU1_INT_MASK0_INT0_MASK_MASK  (0x1U)
5806 #define AHBSC_SEC_CPU1_INT_MASK0_INT0_MASK_SHIFT (0U)
5807 /*! INT0_MASK - Mask bit
5808  *  0b0..Masked
5809  *  0b1..Not masked
5810  */
5811 #define AHBSC_SEC_CPU1_INT_MASK0_INT0_MASK(x)    (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK0_INT0_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK0_INT0_MASK_MASK)
5812 
5813 #define AHBSC_SEC_CPU1_INT_MASK0_INT1_MASK_MASK  (0x2U)
5814 #define AHBSC_SEC_CPU1_INT_MASK0_INT1_MASK_SHIFT (1U)
5815 /*! INT1_MASK - Mask bit
5816  *  0b0..Masked
5817  *  0b1..Not masked
5818  */
5819 #define AHBSC_SEC_CPU1_INT_MASK0_INT1_MASK(x)    (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK0_INT1_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK0_INT1_MASK_MASK)
5820 
5821 #define AHBSC_SEC_CPU1_INT_MASK0_INT2_MASK_MASK  (0x4U)
5822 #define AHBSC_SEC_CPU1_INT_MASK0_INT2_MASK_SHIFT (2U)
5823 /*! INT2_MASK - Mask bit
5824  *  0b0..Masked
5825  *  0b1..Not masked
5826  */
5827 #define AHBSC_SEC_CPU1_INT_MASK0_INT2_MASK(x)    (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK0_INT2_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK0_INT2_MASK_MASK)
5828 
5829 #define AHBSC_SEC_CPU1_INT_MASK0_INT3_MASK_MASK  (0x8U)
5830 #define AHBSC_SEC_CPU1_INT_MASK0_INT3_MASK_SHIFT (3U)
5831 /*! INT3_MASK - Mask bit
5832  *  0b0..Masked
5833  *  0b1..Not masked
5834  */
5835 #define AHBSC_SEC_CPU1_INT_MASK0_INT3_MASK(x)    (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK0_INT3_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK0_INT3_MASK_MASK)
5836 
5837 #define AHBSC_SEC_CPU1_INT_MASK0_INT4_MASK_MASK  (0x10U)
5838 #define AHBSC_SEC_CPU1_INT_MASK0_INT4_MASK_SHIFT (4U)
5839 /*! INT4_MASK - Mask bit
5840  *  0b0..Masked
5841  *  0b1..Not masked
5842  */
5843 #define AHBSC_SEC_CPU1_INT_MASK0_INT4_MASK(x)    (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK0_INT4_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK0_INT4_MASK_MASK)
5844 
5845 #define AHBSC_SEC_CPU1_INT_MASK0_INT5_MASK_MASK  (0x20U)
5846 #define AHBSC_SEC_CPU1_INT_MASK0_INT5_MASK_SHIFT (5U)
5847 /*! INT5_MASK - Mask bit
5848  *  0b0..Masked
5849  *  0b1..Not masked
5850  */
5851 #define AHBSC_SEC_CPU1_INT_MASK0_INT5_MASK(x)    (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK0_INT5_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK0_INT5_MASK_MASK)
5852 
5853 #define AHBSC_SEC_CPU1_INT_MASK0_INT6_MASK_MASK  (0x40U)
5854 #define AHBSC_SEC_CPU1_INT_MASK0_INT6_MASK_SHIFT (6U)
5855 /*! INT6_MASK - Mask bit
5856  *  0b0..Masked
5857  *  0b1..Not masked
5858  */
5859 #define AHBSC_SEC_CPU1_INT_MASK0_INT6_MASK(x)    (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK0_INT6_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK0_INT6_MASK_MASK)
5860 
5861 #define AHBSC_SEC_CPU1_INT_MASK0_INT7_MASK_MASK  (0x80U)
5862 #define AHBSC_SEC_CPU1_INT_MASK0_INT7_MASK_SHIFT (7U)
5863 /*! INT7_MASK - Mask bit
5864  *  0b0..Masked
5865  *  0b1..Not masked
5866  */
5867 #define AHBSC_SEC_CPU1_INT_MASK0_INT7_MASK(x)    (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK0_INT7_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK0_INT7_MASK_MASK)
5868 
5869 #define AHBSC_SEC_CPU1_INT_MASK0_INT8_MASK_MASK  (0x100U)
5870 #define AHBSC_SEC_CPU1_INT_MASK0_INT8_MASK_SHIFT (8U)
5871 /*! INT8_MASK - Mask bit
5872  *  0b0..Masked
5873  *  0b1..Not masked
5874  */
5875 #define AHBSC_SEC_CPU1_INT_MASK0_INT8_MASK(x)    (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK0_INT8_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK0_INT8_MASK_MASK)
5876 
5877 #define AHBSC_SEC_CPU1_INT_MASK0_INT9_MASK_MASK  (0x200U)
5878 #define AHBSC_SEC_CPU1_INT_MASK0_INT9_MASK_SHIFT (9U)
5879 /*! INT9_MASK - Mask bit
5880  *  0b0..Masked
5881  *  0b1..Not masked
5882  */
5883 #define AHBSC_SEC_CPU1_INT_MASK0_INT9_MASK(x)    (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK0_INT9_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK0_INT9_MASK_MASK)
5884 
5885 #define AHBSC_SEC_CPU1_INT_MASK0_INT10_MASK_MASK (0x400U)
5886 #define AHBSC_SEC_CPU1_INT_MASK0_INT10_MASK_SHIFT (10U)
5887 /*! INT10_MASK - Mask bit
5888  *  0b0..Masked
5889  *  0b1..Not masked
5890  */
5891 #define AHBSC_SEC_CPU1_INT_MASK0_INT10_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK0_INT10_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK0_INT10_MASK_MASK)
5892 
5893 #define AHBSC_SEC_CPU1_INT_MASK0_INT11_MASK_MASK (0x800U)
5894 #define AHBSC_SEC_CPU1_INT_MASK0_INT11_MASK_SHIFT (11U)
5895 /*! INT11_MASK - Mask bit
5896  *  0b0..Masked
5897  *  0b1..Not masked
5898  */
5899 #define AHBSC_SEC_CPU1_INT_MASK0_INT11_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK0_INT11_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK0_INT11_MASK_MASK)
5900 
5901 #define AHBSC_SEC_CPU1_INT_MASK0_INT12_MASK_MASK (0x1000U)
5902 #define AHBSC_SEC_CPU1_INT_MASK0_INT12_MASK_SHIFT (12U)
5903 /*! INT12_MASK - Mask bit
5904  *  0b0..Masked
5905  *  0b1..Not masked
5906  */
5907 #define AHBSC_SEC_CPU1_INT_MASK0_INT12_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK0_INT12_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK0_INT12_MASK_MASK)
5908 
5909 #define AHBSC_SEC_CPU1_INT_MASK0_INT13_MASK_MASK (0x2000U)
5910 #define AHBSC_SEC_CPU1_INT_MASK0_INT13_MASK_SHIFT (13U)
5911 /*! INT13_MASK - Mask bit
5912  *  0b0..Masked
5913  *  0b1..Not masked
5914  */
5915 #define AHBSC_SEC_CPU1_INT_MASK0_INT13_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK0_INT13_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK0_INT13_MASK_MASK)
5916 
5917 #define AHBSC_SEC_CPU1_INT_MASK0_INT14_MASK_MASK (0x4000U)
5918 #define AHBSC_SEC_CPU1_INT_MASK0_INT14_MASK_SHIFT (14U)
5919 /*! INT14_MASK - Mask bit
5920  *  0b0..Masked
5921  *  0b1..Not masked
5922  */
5923 #define AHBSC_SEC_CPU1_INT_MASK0_INT14_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK0_INT14_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK0_INT14_MASK_MASK)
5924 
5925 #define AHBSC_SEC_CPU1_INT_MASK0_INT15_MASK_MASK (0x8000U)
5926 #define AHBSC_SEC_CPU1_INT_MASK0_INT15_MASK_SHIFT (15U)
5927 /*! INT15_MASK - Mask bit
5928  *  0b0..Masked
5929  *  0b1..Not masked
5930  */
5931 #define AHBSC_SEC_CPU1_INT_MASK0_INT15_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK0_INT15_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK0_INT15_MASK_MASK)
5932 
5933 #define AHBSC_SEC_CPU1_INT_MASK0_INT16_MASK_MASK (0x10000U)
5934 #define AHBSC_SEC_CPU1_INT_MASK0_INT16_MASK_SHIFT (16U)
5935 /*! INT16_MASK - Mask bit
5936  *  0b0..Masked
5937  *  0b1..Not masked
5938  */
5939 #define AHBSC_SEC_CPU1_INT_MASK0_INT16_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK0_INT16_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK0_INT16_MASK_MASK)
5940 
5941 #define AHBSC_SEC_CPU1_INT_MASK0_INT17_MASK_MASK (0x20000U)
5942 #define AHBSC_SEC_CPU1_INT_MASK0_INT17_MASK_SHIFT (17U)
5943 /*! INT17_MASK - Mask bit
5944  *  0b0..Masked
5945  *  0b1..Not masked
5946  */
5947 #define AHBSC_SEC_CPU1_INT_MASK0_INT17_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK0_INT17_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK0_INT17_MASK_MASK)
5948 
5949 #define AHBSC_SEC_CPU1_INT_MASK0_INT18_MASK_MASK (0x40000U)
5950 #define AHBSC_SEC_CPU1_INT_MASK0_INT18_MASK_SHIFT (18U)
5951 /*! INT18_MASK - Mask bit
5952  *  0b0..Masked
5953  *  0b1..Not masked
5954  */
5955 #define AHBSC_SEC_CPU1_INT_MASK0_INT18_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK0_INT18_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK0_INT18_MASK_MASK)
5956 
5957 #define AHBSC_SEC_CPU1_INT_MASK0_INT19_MASK_MASK (0x80000U)
5958 #define AHBSC_SEC_CPU1_INT_MASK0_INT19_MASK_SHIFT (19U)
5959 /*! INT19_MASK - Mask bit
5960  *  0b0..Masked
5961  *  0b1..Not masked
5962  */
5963 #define AHBSC_SEC_CPU1_INT_MASK0_INT19_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK0_INT19_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK0_INT19_MASK_MASK)
5964 
5965 #define AHBSC_SEC_CPU1_INT_MASK0_INT20_MASK_MASK (0x100000U)
5966 #define AHBSC_SEC_CPU1_INT_MASK0_INT20_MASK_SHIFT (20U)
5967 /*! INT20_MASK - Mask bit
5968  *  0b0..Masked
5969  *  0b1..Not masked
5970  */
5971 #define AHBSC_SEC_CPU1_INT_MASK0_INT20_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK0_INT20_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK0_INT20_MASK_MASK)
5972 
5973 #define AHBSC_SEC_CPU1_INT_MASK0_INT21_MASK_MASK (0x200000U)
5974 #define AHBSC_SEC_CPU1_INT_MASK0_INT21_MASK_SHIFT (21U)
5975 /*! INT21_MASK - Mask bit
5976  *  0b0..Masked
5977  *  0b1..Not masked
5978  */
5979 #define AHBSC_SEC_CPU1_INT_MASK0_INT21_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK0_INT21_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK0_INT21_MASK_MASK)
5980 
5981 #define AHBSC_SEC_CPU1_INT_MASK0_INT22_MASK_MASK (0x400000U)
5982 #define AHBSC_SEC_CPU1_INT_MASK0_INT22_MASK_SHIFT (22U)
5983 /*! INT22_MASK - Mask bit
5984  *  0b0..Masked
5985  *  0b1..Not masked
5986  */
5987 #define AHBSC_SEC_CPU1_INT_MASK0_INT22_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK0_INT22_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK0_INT22_MASK_MASK)
5988 
5989 #define AHBSC_SEC_CPU1_INT_MASK0_INT23_MASK_MASK (0x800000U)
5990 #define AHBSC_SEC_CPU1_INT_MASK0_INT23_MASK_SHIFT (23U)
5991 /*! INT23_MASK - Mask bit
5992  *  0b0..Masked
5993  *  0b1..Not masked
5994  */
5995 #define AHBSC_SEC_CPU1_INT_MASK0_INT23_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK0_INT23_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK0_INT23_MASK_MASK)
5996 
5997 #define AHBSC_SEC_CPU1_INT_MASK0_INT24_MASK_MASK (0x1000000U)
5998 #define AHBSC_SEC_CPU1_INT_MASK0_INT24_MASK_SHIFT (24U)
5999 /*! INT24_MASK - Mask bit
6000  *  0b0..Masked
6001  *  0b1..Not masked
6002  */
6003 #define AHBSC_SEC_CPU1_INT_MASK0_INT24_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK0_INT24_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK0_INT24_MASK_MASK)
6004 
6005 #define AHBSC_SEC_CPU1_INT_MASK0_INT25_MASK_MASK (0x2000000U)
6006 #define AHBSC_SEC_CPU1_INT_MASK0_INT25_MASK_SHIFT (25U)
6007 /*! INT25_MASK - Mask bit
6008  *  0b0..Masked
6009  *  0b1..Not masked
6010  */
6011 #define AHBSC_SEC_CPU1_INT_MASK0_INT25_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK0_INT25_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK0_INT25_MASK_MASK)
6012 
6013 #define AHBSC_SEC_CPU1_INT_MASK0_INT26_MASK_MASK (0x4000000U)
6014 #define AHBSC_SEC_CPU1_INT_MASK0_INT26_MASK_SHIFT (26U)
6015 /*! INT26_MASK - Mask bit
6016  *  0b0..Masked
6017  *  0b1..Not masked
6018  */
6019 #define AHBSC_SEC_CPU1_INT_MASK0_INT26_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK0_INT26_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK0_INT26_MASK_MASK)
6020 
6021 #define AHBSC_SEC_CPU1_INT_MASK0_INT27_MASK_MASK (0x8000000U)
6022 #define AHBSC_SEC_CPU1_INT_MASK0_INT27_MASK_SHIFT (27U)
6023 /*! INT27_MASK - Mask bit
6024  *  0b0..Masked
6025  *  0b1..Not masked
6026  */
6027 #define AHBSC_SEC_CPU1_INT_MASK0_INT27_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK0_INT27_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK0_INT27_MASK_MASK)
6028 
6029 #define AHBSC_SEC_CPU1_INT_MASK0_INT28_MASK_MASK (0x10000000U)
6030 #define AHBSC_SEC_CPU1_INT_MASK0_INT28_MASK_SHIFT (28U)
6031 /*! INT28_MASK - Mask bit
6032  *  0b0..Masked
6033  *  0b1..Not masked
6034  */
6035 #define AHBSC_SEC_CPU1_INT_MASK0_INT28_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK0_INT28_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK0_INT28_MASK_MASK)
6036 
6037 #define AHBSC_SEC_CPU1_INT_MASK0_INT29_MASK_MASK (0x20000000U)
6038 #define AHBSC_SEC_CPU1_INT_MASK0_INT29_MASK_SHIFT (29U)
6039 /*! INT29_MASK - Mask bit
6040  *  0b0..Masked
6041  *  0b1..Not masked
6042  */
6043 #define AHBSC_SEC_CPU1_INT_MASK0_INT29_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK0_INT29_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK0_INT29_MASK_MASK)
6044 
6045 #define AHBSC_SEC_CPU1_INT_MASK0_INT30_MASK_MASK (0x40000000U)
6046 #define AHBSC_SEC_CPU1_INT_MASK0_INT30_MASK_SHIFT (30U)
6047 /*! INT30_MASK - Mask bit
6048  *  0b0..Masked
6049  *  0b1..Not masked
6050  */
6051 #define AHBSC_SEC_CPU1_INT_MASK0_INT30_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK0_INT30_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK0_INT30_MASK_MASK)
6052 
6053 #define AHBSC_SEC_CPU1_INT_MASK0_INT31_MASK_MASK (0x80000000U)
6054 #define AHBSC_SEC_CPU1_INT_MASK0_INT31_MASK_SHIFT (31U)
6055 /*! INT31_MASK - Mask bit
6056  *  0b0..Masked
6057  *  0b1..Not masked
6058  */
6059 #define AHBSC_SEC_CPU1_INT_MASK0_INT31_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK0_INT31_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK0_INT31_MASK_MASK)
6060 /*! @} */
6061 
6062 /*! @name SEC_CPU1_INT_MASK1 - Secure Interrupt Mask 1 for CPU1 */
6063 /*! @{ */
6064 
6065 #define AHBSC_SEC_CPU1_INT_MASK1_INT32_MASK_MASK (0x1U)
6066 #define AHBSC_SEC_CPU1_INT_MASK1_INT32_MASK_SHIFT (0U)
6067 /*! INT32_MASK - Mask bit
6068  *  0b0..Masked
6069  *  0b1..Not masked
6070  */
6071 #define AHBSC_SEC_CPU1_INT_MASK1_INT32_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK1_INT32_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK1_INT32_MASK_MASK)
6072 
6073 #define AHBSC_SEC_CPU1_INT_MASK1_INT33_MASK_MASK (0x2U)
6074 #define AHBSC_SEC_CPU1_INT_MASK1_INT33_MASK_SHIFT (1U)
6075 /*! INT33_MASK - Mask bit
6076  *  0b0..Masked
6077  *  0b1..Not masked
6078  */
6079 #define AHBSC_SEC_CPU1_INT_MASK1_INT33_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK1_INT33_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK1_INT33_MASK_MASK)
6080 
6081 #define AHBSC_SEC_CPU1_INT_MASK1_INT34_MASK_MASK (0x4U)
6082 #define AHBSC_SEC_CPU1_INT_MASK1_INT34_MASK_SHIFT (2U)
6083 /*! INT34_MASK - Mask bit
6084  *  0b0..Masked
6085  *  0b1..Not masked
6086  */
6087 #define AHBSC_SEC_CPU1_INT_MASK1_INT34_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK1_INT34_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK1_INT34_MASK_MASK)
6088 
6089 #define AHBSC_SEC_CPU1_INT_MASK1_INT35_MASK_MASK (0x8U)
6090 #define AHBSC_SEC_CPU1_INT_MASK1_INT35_MASK_SHIFT (3U)
6091 /*! INT35_MASK - Mask bit
6092  *  0b0..Masked
6093  *  0b1..Not masked
6094  */
6095 #define AHBSC_SEC_CPU1_INT_MASK1_INT35_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK1_INT35_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK1_INT35_MASK_MASK)
6096 
6097 #define AHBSC_SEC_CPU1_INT_MASK1_INT36_MASK_MASK (0x10U)
6098 #define AHBSC_SEC_CPU1_INT_MASK1_INT36_MASK_SHIFT (4U)
6099 /*! INT36_MASK - Mask bit
6100  *  0b0..Masked
6101  *  0b1..Not masked
6102  */
6103 #define AHBSC_SEC_CPU1_INT_MASK1_INT36_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK1_INT36_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK1_INT36_MASK_MASK)
6104 
6105 #define AHBSC_SEC_CPU1_INT_MASK1_INT37_MASK_MASK (0x20U)
6106 #define AHBSC_SEC_CPU1_INT_MASK1_INT37_MASK_SHIFT (5U)
6107 /*! INT37_MASK - Mask bit
6108  *  0b0..Masked
6109  *  0b1..Not masked
6110  */
6111 #define AHBSC_SEC_CPU1_INT_MASK1_INT37_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK1_INT37_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK1_INT37_MASK_MASK)
6112 
6113 #define AHBSC_SEC_CPU1_INT_MASK1_INT38_MASK_MASK (0x40U)
6114 #define AHBSC_SEC_CPU1_INT_MASK1_INT38_MASK_SHIFT (6U)
6115 /*! INT38_MASK - Mask bit
6116  *  0b0..Masked
6117  *  0b1..Not masked
6118  */
6119 #define AHBSC_SEC_CPU1_INT_MASK1_INT38_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK1_INT38_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK1_INT38_MASK_MASK)
6120 
6121 #define AHBSC_SEC_CPU1_INT_MASK1_INT39_MASK_MASK (0x80U)
6122 #define AHBSC_SEC_CPU1_INT_MASK1_INT39_MASK_SHIFT (7U)
6123 /*! INT39_MASK - Mask bit
6124  *  0b0..Masked
6125  *  0b1..Not masked
6126  */
6127 #define AHBSC_SEC_CPU1_INT_MASK1_INT39_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK1_INT39_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK1_INT39_MASK_MASK)
6128 
6129 #define AHBSC_SEC_CPU1_INT_MASK1_INT40_MASK_MASK (0x100U)
6130 #define AHBSC_SEC_CPU1_INT_MASK1_INT40_MASK_SHIFT (8U)
6131 /*! INT40_MASK - Mask bit
6132  *  0b0..Masked
6133  *  0b1..Not masked
6134  */
6135 #define AHBSC_SEC_CPU1_INT_MASK1_INT40_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK1_INT40_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK1_INT40_MASK_MASK)
6136 
6137 #define AHBSC_SEC_CPU1_INT_MASK1_INT41_MASK_MASK (0x200U)
6138 #define AHBSC_SEC_CPU1_INT_MASK1_INT41_MASK_SHIFT (9U)
6139 /*! INT41_MASK - Mask bit
6140  *  0b0..Masked
6141  *  0b1..Not masked
6142  */
6143 #define AHBSC_SEC_CPU1_INT_MASK1_INT41_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK1_INT41_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK1_INT41_MASK_MASK)
6144 
6145 #define AHBSC_SEC_CPU1_INT_MASK1_INT42_MASK_MASK (0x400U)
6146 #define AHBSC_SEC_CPU1_INT_MASK1_INT42_MASK_SHIFT (10U)
6147 /*! INT42_MASK - Mask bit
6148  *  0b0..Masked
6149  *  0b1..Not masked
6150  */
6151 #define AHBSC_SEC_CPU1_INT_MASK1_INT42_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK1_INT42_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK1_INT42_MASK_MASK)
6152 
6153 #define AHBSC_SEC_CPU1_INT_MASK1_INT43_MASK_MASK (0x800U)
6154 #define AHBSC_SEC_CPU1_INT_MASK1_INT43_MASK_SHIFT (11U)
6155 /*! INT43_MASK - Mask bit
6156  *  0b0..Masked
6157  *  0b1..Not masked
6158  */
6159 #define AHBSC_SEC_CPU1_INT_MASK1_INT43_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK1_INT43_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK1_INT43_MASK_MASK)
6160 
6161 #define AHBSC_SEC_CPU1_INT_MASK1_INT44_MASK_MASK (0x1000U)
6162 #define AHBSC_SEC_CPU1_INT_MASK1_INT44_MASK_SHIFT (12U)
6163 /*! INT44_MASK - Mask bit
6164  *  0b0..Masked
6165  *  0b1..Not masked
6166  */
6167 #define AHBSC_SEC_CPU1_INT_MASK1_INT44_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK1_INT44_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK1_INT44_MASK_MASK)
6168 
6169 #define AHBSC_SEC_CPU1_INT_MASK1_INT45_MASK_MASK (0x2000U)
6170 #define AHBSC_SEC_CPU1_INT_MASK1_INT45_MASK_SHIFT (13U)
6171 /*! INT45_MASK - Mask bit
6172  *  0b0..Masked
6173  *  0b1..Not masked
6174  */
6175 #define AHBSC_SEC_CPU1_INT_MASK1_INT45_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK1_INT45_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK1_INT45_MASK_MASK)
6176 
6177 #define AHBSC_SEC_CPU1_INT_MASK1_INT46_MASK_MASK (0x4000U)
6178 #define AHBSC_SEC_CPU1_INT_MASK1_INT46_MASK_SHIFT (14U)
6179 /*! INT46_MASK - Mask bit
6180  *  0b0..Masked
6181  *  0b1..Not masked
6182  */
6183 #define AHBSC_SEC_CPU1_INT_MASK1_INT46_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK1_INT46_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK1_INT46_MASK_MASK)
6184 
6185 #define AHBSC_SEC_CPU1_INT_MASK1_INT47_MASK_MASK (0x8000U)
6186 #define AHBSC_SEC_CPU1_INT_MASK1_INT47_MASK_SHIFT (15U)
6187 /*! INT47_MASK - Mask bit
6188  *  0b0..Masked
6189  *  0b1..Not masked
6190  */
6191 #define AHBSC_SEC_CPU1_INT_MASK1_INT47_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK1_INT47_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK1_INT47_MASK_MASK)
6192 
6193 #define AHBSC_SEC_CPU1_INT_MASK1_INT48_MASK_MASK (0x10000U)
6194 #define AHBSC_SEC_CPU1_INT_MASK1_INT48_MASK_SHIFT (16U)
6195 /*! INT48_MASK - Mask bit
6196  *  0b0..Masked
6197  *  0b1..Not masked
6198  */
6199 #define AHBSC_SEC_CPU1_INT_MASK1_INT48_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK1_INT48_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK1_INT48_MASK_MASK)
6200 
6201 #define AHBSC_SEC_CPU1_INT_MASK1_INT49_MASK_MASK (0x20000U)
6202 #define AHBSC_SEC_CPU1_INT_MASK1_INT49_MASK_SHIFT (17U)
6203 /*! INT49_MASK - Mask bit
6204  *  0b0..Masked
6205  *  0b1..Not masked
6206  */
6207 #define AHBSC_SEC_CPU1_INT_MASK1_INT49_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK1_INT49_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK1_INT49_MASK_MASK)
6208 
6209 #define AHBSC_SEC_CPU1_INT_MASK1_INT50_MASK_MASK (0x40000U)
6210 #define AHBSC_SEC_CPU1_INT_MASK1_INT50_MASK_SHIFT (18U)
6211 /*! INT50_MASK - Mask bit
6212  *  0b0..Masked
6213  *  0b1..Not masked
6214  */
6215 #define AHBSC_SEC_CPU1_INT_MASK1_INT50_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK1_INT50_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK1_INT50_MASK_MASK)
6216 
6217 #define AHBSC_SEC_CPU1_INT_MASK1_INT51_MASK_MASK (0x80000U)
6218 #define AHBSC_SEC_CPU1_INT_MASK1_INT51_MASK_SHIFT (19U)
6219 /*! INT51_MASK - Mask bit
6220  *  0b0..Masked
6221  *  0b1..Not masked
6222  */
6223 #define AHBSC_SEC_CPU1_INT_MASK1_INT51_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK1_INT51_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK1_INT51_MASK_MASK)
6224 
6225 #define AHBSC_SEC_CPU1_INT_MASK1_INT52_MASK_MASK (0x100000U)
6226 #define AHBSC_SEC_CPU1_INT_MASK1_INT52_MASK_SHIFT (20U)
6227 /*! INT52_MASK - Mask bit
6228  *  0b0..Masked
6229  *  0b1..Not masked
6230  */
6231 #define AHBSC_SEC_CPU1_INT_MASK1_INT52_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK1_INT52_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK1_INT52_MASK_MASK)
6232 
6233 #define AHBSC_SEC_CPU1_INT_MASK1_INT53_MASK_MASK (0x200000U)
6234 #define AHBSC_SEC_CPU1_INT_MASK1_INT53_MASK_SHIFT (21U)
6235 /*! INT53_MASK - Mask bit
6236  *  0b0..Masked
6237  *  0b1..Not masked
6238  */
6239 #define AHBSC_SEC_CPU1_INT_MASK1_INT53_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK1_INT53_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK1_INT53_MASK_MASK)
6240 
6241 #define AHBSC_SEC_CPU1_INT_MASK1_INT54_MASK_MASK (0x400000U)
6242 #define AHBSC_SEC_CPU1_INT_MASK1_INT54_MASK_SHIFT (22U)
6243 /*! INT54_MASK - Mask bit
6244  *  0b0..Masked
6245  *  0b1..Not masked
6246  */
6247 #define AHBSC_SEC_CPU1_INT_MASK1_INT54_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK1_INT54_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK1_INT54_MASK_MASK)
6248 
6249 #define AHBSC_SEC_CPU1_INT_MASK1_INT55_MASK_MASK (0x800000U)
6250 #define AHBSC_SEC_CPU1_INT_MASK1_INT55_MASK_SHIFT (23U)
6251 /*! INT55_MASK - Mask bit
6252  *  0b0..Masked
6253  *  0b1..Not masked
6254  */
6255 #define AHBSC_SEC_CPU1_INT_MASK1_INT55_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK1_INT55_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK1_INT55_MASK_MASK)
6256 
6257 #define AHBSC_SEC_CPU1_INT_MASK1_INT56_MASK_MASK (0x1000000U)
6258 #define AHBSC_SEC_CPU1_INT_MASK1_INT56_MASK_SHIFT (24U)
6259 /*! INT56_MASK - Mask bit
6260  *  0b0..Masked
6261  *  0b1..Not masked
6262  */
6263 #define AHBSC_SEC_CPU1_INT_MASK1_INT56_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK1_INT56_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK1_INT56_MASK_MASK)
6264 
6265 #define AHBSC_SEC_CPU1_INT_MASK1_INT57_MASK_MASK (0x2000000U)
6266 #define AHBSC_SEC_CPU1_INT_MASK1_INT57_MASK_SHIFT (25U)
6267 /*! INT57_MASK - Mask bit
6268  *  0b0..Masked
6269  *  0b1..Not masked
6270  */
6271 #define AHBSC_SEC_CPU1_INT_MASK1_INT57_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK1_INT57_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK1_INT57_MASK_MASK)
6272 
6273 #define AHBSC_SEC_CPU1_INT_MASK1_INT58_MASK_MASK (0x4000000U)
6274 #define AHBSC_SEC_CPU1_INT_MASK1_INT58_MASK_SHIFT (26U)
6275 /*! INT58_MASK - Mask bit
6276  *  0b0..Masked
6277  *  0b1..Not masked
6278  */
6279 #define AHBSC_SEC_CPU1_INT_MASK1_INT58_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK1_INT58_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK1_INT58_MASK_MASK)
6280 
6281 #define AHBSC_SEC_CPU1_INT_MASK1_INT59_MASK_MASK (0x8000000U)
6282 #define AHBSC_SEC_CPU1_INT_MASK1_INT59_MASK_SHIFT (27U)
6283 /*! INT59_MASK - Mask bit
6284  *  0b0..Masked
6285  *  0b1..Not masked
6286  */
6287 #define AHBSC_SEC_CPU1_INT_MASK1_INT59_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK1_INT59_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK1_INT59_MASK_MASK)
6288 
6289 #define AHBSC_SEC_CPU1_INT_MASK1_INT60_MASK_MASK (0x10000000U)
6290 #define AHBSC_SEC_CPU1_INT_MASK1_INT60_MASK_SHIFT (28U)
6291 /*! INT60_MASK - Mask bit
6292  *  0b0..Masked
6293  *  0b1..Not masked
6294  */
6295 #define AHBSC_SEC_CPU1_INT_MASK1_INT60_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK1_INT60_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK1_INT60_MASK_MASK)
6296 
6297 #define AHBSC_SEC_CPU1_INT_MASK1_INT61_MASK_MASK (0x20000000U)
6298 #define AHBSC_SEC_CPU1_INT_MASK1_INT61_MASK_SHIFT (29U)
6299 /*! INT61_MASK - Mask bit
6300  *  0b0..Masked
6301  *  0b1..Not masked
6302  */
6303 #define AHBSC_SEC_CPU1_INT_MASK1_INT61_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK1_INT61_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK1_INT61_MASK_MASK)
6304 
6305 #define AHBSC_SEC_CPU1_INT_MASK1_INT62_MASK_MASK (0x40000000U)
6306 #define AHBSC_SEC_CPU1_INT_MASK1_INT62_MASK_SHIFT (30U)
6307 /*! INT62_MASK - Mask bit
6308  *  0b0..Masked
6309  *  0b1..Not masked
6310  */
6311 #define AHBSC_SEC_CPU1_INT_MASK1_INT62_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK1_INT62_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK1_INT62_MASK_MASK)
6312 
6313 #define AHBSC_SEC_CPU1_INT_MASK1_INT63_MASK_MASK (0x80000000U)
6314 #define AHBSC_SEC_CPU1_INT_MASK1_INT63_MASK_SHIFT (31U)
6315 /*! INT63_MASK - Mask bit
6316  *  0b0..Masked
6317  *  0b1..Not masked
6318  */
6319 #define AHBSC_SEC_CPU1_INT_MASK1_INT63_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK1_INT63_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK1_INT63_MASK_MASK)
6320 /*! @} */
6321 
6322 /*! @name SEC_CPU1_INT_MASK2 - Secure Interrupt Mask 2 for CPU1 */
6323 /*! @{ */
6324 
6325 #define AHBSC_SEC_CPU1_INT_MASK2_INT64_MASK_MASK (0x1U)
6326 #define AHBSC_SEC_CPU1_INT_MASK2_INT64_MASK_SHIFT (0U)
6327 /*! INT64_MASK - Mask bit
6328  *  0b0..Masked
6329  *  0b1..Not masked
6330  */
6331 #define AHBSC_SEC_CPU1_INT_MASK2_INT64_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK2_INT64_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK2_INT64_MASK_MASK)
6332 
6333 #define AHBSC_SEC_CPU1_INT_MASK2_INT65_MASK_MASK (0x2U)
6334 #define AHBSC_SEC_CPU1_INT_MASK2_INT65_MASK_SHIFT (1U)
6335 /*! INT65_MASK - Mask bit
6336  *  0b0..Masked
6337  *  0b1..Not masked
6338  */
6339 #define AHBSC_SEC_CPU1_INT_MASK2_INT65_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK2_INT65_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK2_INT65_MASK_MASK)
6340 
6341 #define AHBSC_SEC_CPU1_INT_MASK2_INT66_MASK_MASK (0x4U)
6342 #define AHBSC_SEC_CPU1_INT_MASK2_INT66_MASK_SHIFT (2U)
6343 /*! INT66_MASK - Mask bit
6344  *  0b0..Masked
6345  *  0b1..Not masked
6346  */
6347 #define AHBSC_SEC_CPU1_INT_MASK2_INT66_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK2_INT66_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK2_INT66_MASK_MASK)
6348 
6349 #define AHBSC_SEC_CPU1_INT_MASK2_INT67_MASK_MASK (0x8U)
6350 #define AHBSC_SEC_CPU1_INT_MASK2_INT67_MASK_SHIFT (3U)
6351 /*! INT67_MASK - Mask bit
6352  *  0b0..Masked
6353  *  0b1..Not masked
6354  */
6355 #define AHBSC_SEC_CPU1_INT_MASK2_INT67_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK2_INT67_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK2_INT67_MASK_MASK)
6356 
6357 #define AHBSC_SEC_CPU1_INT_MASK2_INT68_MASK_MASK (0x10U)
6358 #define AHBSC_SEC_CPU1_INT_MASK2_INT68_MASK_SHIFT (4U)
6359 /*! INT68_MASK - Mask bit
6360  *  0b0..Masked
6361  *  0b1..Not masked
6362  */
6363 #define AHBSC_SEC_CPU1_INT_MASK2_INT68_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK2_INT68_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK2_INT68_MASK_MASK)
6364 
6365 #define AHBSC_SEC_CPU1_INT_MASK2_INT69_MASK_MASK (0x20U)
6366 #define AHBSC_SEC_CPU1_INT_MASK2_INT69_MASK_SHIFT (5U)
6367 /*! INT69_MASK - Mask bit
6368  *  0b0..Masked
6369  *  0b1..Not masked
6370  */
6371 #define AHBSC_SEC_CPU1_INT_MASK2_INT69_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK2_INT69_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK2_INT69_MASK_MASK)
6372 
6373 #define AHBSC_SEC_CPU1_INT_MASK2_INT70_MASK_MASK (0x40U)
6374 #define AHBSC_SEC_CPU1_INT_MASK2_INT70_MASK_SHIFT (6U)
6375 /*! INT70_MASK - Mask bit
6376  *  0b0..Masked
6377  *  0b1..Not masked
6378  */
6379 #define AHBSC_SEC_CPU1_INT_MASK2_INT70_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK2_INT70_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK2_INT70_MASK_MASK)
6380 
6381 #define AHBSC_SEC_CPU1_INT_MASK2_INT71_MASK_MASK (0x80U)
6382 #define AHBSC_SEC_CPU1_INT_MASK2_INT71_MASK_SHIFT (7U)
6383 /*! INT71_MASK - Mask bit
6384  *  0b0..Masked
6385  *  0b1..Not masked
6386  */
6387 #define AHBSC_SEC_CPU1_INT_MASK2_INT71_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK2_INT71_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK2_INT71_MASK_MASK)
6388 
6389 #define AHBSC_SEC_CPU1_INT_MASK2_INT72_MASK_MASK (0x100U)
6390 #define AHBSC_SEC_CPU1_INT_MASK2_INT72_MASK_SHIFT (8U)
6391 /*! INT72_MASK - Mask bit
6392  *  0b0..Masked
6393  *  0b1..Not masked
6394  */
6395 #define AHBSC_SEC_CPU1_INT_MASK2_INT72_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK2_INT72_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK2_INT72_MASK_MASK)
6396 
6397 #define AHBSC_SEC_CPU1_INT_MASK2_INT73_MASK_MASK (0x200U)
6398 #define AHBSC_SEC_CPU1_INT_MASK2_INT73_MASK_SHIFT (9U)
6399 /*! INT73_MASK - Mask bit
6400  *  0b0..Masked
6401  *  0b1..Not masked
6402  */
6403 #define AHBSC_SEC_CPU1_INT_MASK2_INT73_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK2_INT73_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK2_INT73_MASK_MASK)
6404 
6405 #define AHBSC_SEC_CPU1_INT_MASK2_INT74_MASK_MASK (0x400U)
6406 #define AHBSC_SEC_CPU1_INT_MASK2_INT74_MASK_SHIFT (10U)
6407 /*! INT74_MASK - Mask bit
6408  *  0b0..Masked
6409  *  0b1..Not masked
6410  */
6411 #define AHBSC_SEC_CPU1_INT_MASK2_INT74_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK2_INT74_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK2_INT74_MASK_MASK)
6412 
6413 #define AHBSC_SEC_CPU1_INT_MASK2_INT75_MASK_MASK (0x800U)
6414 #define AHBSC_SEC_CPU1_INT_MASK2_INT75_MASK_SHIFT (11U)
6415 /*! INT75_MASK - Mask bit
6416  *  0b0..Masked
6417  *  0b1..Not masked
6418  */
6419 #define AHBSC_SEC_CPU1_INT_MASK2_INT75_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK2_INT75_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK2_INT75_MASK_MASK)
6420 
6421 #define AHBSC_SEC_CPU1_INT_MASK2_INT76_MASK_MASK (0x1000U)
6422 #define AHBSC_SEC_CPU1_INT_MASK2_INT76_MASK_SHIFT (12U)
6423 /*! INT76_MASK - Mask bit
6424  *  0b0..Masked
6425  *  0b1..Not masked
6426  */
6427 #define AHBSC_SEC_CPU1_INT_MASK2_INT76_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK2_INT76_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK2_INT76_MASK_MASK)
6428 
6429 #define AHBSC_SEC_CPU1_INT_MASK2_INT77_MASK_MASK (0x2000U)
6430 #define AHBSC_SEC_CPU1_INT_MASK2_INT77_MASK_SHIFT (13U)
6431 /*! INT77_MASK - Mask bit
6432  *  0b0..Masked
6433  *  0b1..Not masked
6434  */
6435 #define AHBSC_SEC_CPU1_INT_MASK2_INT77_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK2_INT77_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK2_INT77_MASK_MASK)
6436 
6437 #define AHBSC_SEC_CPU1_INT_MASK2_INT78_MASK_MASK (0x4000U)
6438 #define AHBSC_SEC_CPU1_INT_MASK2_INT78_MASK_SHIFT (14U)
6439 /*! INT78_MASK - Mask bit
6440  *  0b0..Masked
6441  *  0b1..Not masked
6442  */
6443 #define AHBSC_SEC_CPU1_INT_MASK2_INT78_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK2_INT78_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK2_INT78_MASK_MASK)
6444 
6445 #define AHBSC_SEC_CPU1_INT_MASK2_INT79_MASK_MASK (0x8000U)
6446 #define AHBSC_SEC_CPU1_INT_MASK2_INT79_MASK_SHIFT (15U)
6447 /*! INT79_MASK - Mask bit
6448  *  0b0..Masked
6449  *  0b1..Not masked
6450  */
6451 #define AHBSC_SEC_CPU1_INT_MASK2_INT79_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK2_INT79_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK2_INT79_MASK_MASK)
6452 
6453 #define AHBSC_SEC_CPU1_INT_MASK2_INT80_MASK_MASK (0x10000U)
6454 #define AHBSC_SEC_CPU1_INT_MASK2_INT80_MASK_SHIFT (16U)
6455 /*! INT80_MASK - Mask bit
6456  *  0b0..Masked
6457  *  0b1..Not masked
6458  */
6459 #define AHBSC_SEC_CPU1_INT_MASK2_INT80_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK2_INT80_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK2_INT80_MASK_MASK)
6460 
6461 #define AHBSC_SEC_CPU1_INT_MASK2_INT81_MASK_MASK (0x20000U)
6462 #define AHBSC_SEC_CPU1_INT_MASK2_INT81_MASK_SHIFT (17U)
6463 /*! INT81_MASK - Mask bit
6464  *  0b0..Masked
6465  *  0b1..Not masked
6466  */
6467 #define AHBSC_SEC_CPU1_INT_MASK2_INT81_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK2_INT81_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK2_INT81_MASK_MASK)
6468 
6469 #define AHBSC_SEC_CPU1_INT_MASK2_INT82_MASK_MASK (0x40000U)
6470 #define AHBSC_SEC_CPU1_INT_MASK2_INT82_MASK_SHIFT (18U)
6471 /*! INT82_MASK - Mask bit
6472  *  0b0..Masked
6473  *  0b1..Not masked
6474  */
6475 #define AHBSC_SEC_CPU1_INT_MASK2_INT82_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK2_INT82_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK2_INT82_MASK_MASK)
6476 
6477 #define AHBSC_SEC_CPU1_INT_MASK2_INT83_MASK_MASK (0x80000U)
6478 #define AHBSC_SEC_CPU1_INT_MASK2_INT83_MASK_SHIFT (19U)
6479 /*! INT83_MASK - Mask bit
6480  *  0b0..Masked
6481  *  0b1..Not masked
6482  */
6483 #define AHBSC_SEC_CPU1_INT_MASK2_INT83_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK2_INT83_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK2_INT83_MASK_MASK)
6484 
6485 #define AHBSC_SEC_CPU1_INT_MASK2_INT84_MASK_MASK (0x100000U)
6486 #define AHBSC_SEC_CPU1_INT_MASK2_INT84_MASK_SHIFT (20U)
6487 /*! INT84_MASK - Mask bit
6488  *  0b0..Masked
6489  *  0b1..Not masked
6490  */
6491 #define AHBSC_SEC_CPU1_INT_MASK2_INT84_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK2_INT84_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK2_INT84_MASK_MASK)
6492 
6493 #define AHBSC_SEC_CPU1_INT_MASK2_INT85_MASK_MASK (0x200000U)
6494 #define AHBSC_SEC_CPU1_INT_MASK2_INT85_MASK_SHIFT (21U)
6495 /*! INT85_MASK - Mask bit
6496  *  0b0..Masked
6497  *  0b1..Not masked
6498  */
6499 #define AHBSC_SEC_CPU1_INT_MASK2_INT85_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK2_INT85_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK2_INT85_MASK_MASK)
6500 
6501 #define AHBSC_SEC_CPU1_INT_MASK2_INT86_MASK_MASK (0x400000U)
6502 #define AHBSC_SEC_CPU1_INT_MASK2_INT86_MASK_SHIFT (22U)
6503 /*! INT86_MASK - Mask bit
6504  *  0b0..Masked
6505  *  0b1..Not masked
6506  */
6507 #define AHBSC_SEC_CPU1_INT_MASK2_INT86_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK2_INT86_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK2_INT86_MASK_MASK)
6508 
6509 #define AHBSC_SEC_CPU1_INT_MASK2_INT87_MASK_MASK (0x800000U)
6510 #define AHBSC_SEC_CPU1_INT_MASK2_INT87_MASK_SHIFT (23U)
6511 /*! INT87_MASK - Mask bit
6512  *  0b0..Masked
6513  *  0b1..Not masked
6514  */
6515 #define AHBSC_SEC_CPU1_INT_MASK2_INT87_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK2_INT87_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK2_INT87_MASK_MASK)
6516 
6517 #define AHBSC_SEC_CPU1_INT_MASK2_INT88_MASK_MASK (0x1000000U)
6518 #define AHBSC_SEC_CPU1_INT_MASK2_INT88_MASK_SHIFT (24U)
6519 /*! INT88_MASK - Mask bit
6520  *  0b0..Masked
6521  *  0b1..Not masked
6522  */
6523 #define AHBSC_SEC_CPU1_INT_MASK2_INT88_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK2_INT88_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK2_INT88_MASK_MASK)
6524 
6525 #define AHBSC_SEC_CPU1_INT_MASK2_INT89_MASK_MASK (0x2000000U)
6526 #define AHBSC_SEC_CPU1_INT_MASK2_INT89_MASK_SHIFT (25U)
6527 /*! INT89_MASK - Mask bit
6528  *  0b0..Masked
6529  *  0b1..Not masked
6530  */
6531 #define AHBSC_SEC_CPU1_INT_MASK2_INT89_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK2_INT89_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK2_INT89_MASK_MASK)
6532 
6533 #define AHBSC_SEC_CPU1_INT_MASK2_INT90_MASK_MASK (0x4000000U)
6534 #define AHBSC_SEC_CPU1_INT_MASK2_INT90_MASK_SHIFT (26U)
6535 /*! INT90_MASK - Mask bit
6536  *  0b0..Masked
6537  *  0b1..Not masked
6538  */
6539 #define AHBSC_SEC_CPU1_INT_MASK2_INT90_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK2_INT90_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK2_INT90_MASK_MASK)
6540 
6541 #define AHBSC_SEC_CPU1_INT_MASK2_INT91_MASK_MASK (0x8000000U)
6542 #define AHBSC_SEC_CPU1_INT_MASK2_INT91_MASK_SHIFT (27U)
6543 /*! INT91_MASK - Mask bit
6544  *  0b0..Masked
6545  *  0b1..Not masked
6546  */
6547 #define AHBSC_SEC_CPU1_INT_MASK2_INT91_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK2_INT91_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK2_INT91_MASK_MASK)
6548 
6549 #define AHBSC_SEC_CPU1_INT_MASK2_INT92_MASK_MASK (0x10000000U)
6550 #define AHBSC_SEC_CPU1_INT_MASK2_INT92_MASK_SHIFT (28U)
6551 /*! INT92_MASK - Mask bit
6552  *  0b0..Masked
6553  *  0b1..Not masked
6554  */
6555 #define AHBSC_SEC_CPU1_INT_MASK2_INT92_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK2_INT92_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK2_INT92_MASK_MASK)
6556 
6557 #define AHBSC_SEC_CPU1_INT_MASK2_INT93_MASK_MASK (0x20000000U)
6558 #define AHBSC_SEC_CPU1_INT_MASK2_INT93_MASK_SHIFT (29U)
6559 /*! INT93_MASK - Mask bit
6560  *  0b0..Masked
6561  *  0b1..Not masked
6562  */
6563 #define AHBSC_SEC_CPU1_INT_MASK2_INT93_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK2_INT93_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK2_INT93_MASK_MASK)
6564 
6565 #define AHBSC_SEC_CPU1_INT_MASK2_INT94_MASK_MASK (0x40000000U)
6566 #define AHBSC_SEC_CPU1_INT_MASK2_INT94_MASK_SHIFT (30U)
6567 /*! INT94_MASK - Mask bit
6568  *  0b0..Masked
6569  *  0b1..Not masked
6570  */
6571 #define AHBSC_SEC_CPU1_INT_MASK2_INT94_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK2_INT94_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK2_INT94_MASK_MASK)
6572 
6573 #define AHBSC_SEC_CPU1_INT_MASK2_INT95_MASK_MASK (0x80000000U)
6574 #define AHBSC_SEC_CPU1_INT_MASK2_INT95_MASK_SHIFT (31U)
6575 /*! INT95_MASK - Mask bit
6576  *  0b0..Masked
6577  *  0b1..Not masked
6578  */
6579 #define AHBSC_SEC_CPU1_INT_MASK2_INT95_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK2_INT95_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK2_INT95_MASK_MASK)
6580 /*! @} */
6581 
6582 /*! @name SEC_CPU1_INT_MASK3 - Secure Interrupt Mask 3 for CPU1 */
6583 /*! @{ */
6584 
6585 #define AHBSC_SEC_CPU1_INT_MASK3_INT96_MASK_MASK (0x1U)
6586 #define AHBSC_SEC_CPU1_INT_MASK3_INT96_MASK_SHIFT (0U)
6587 /*! INT96_MASK - Mask bit
6588  *  0b0..Masked
6589  *  0b1..Not masked
6590  */
6591 #define AHBSC_SEC_CPU1_INT_MASK3_INT96_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK3_INT96_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK3_INT96_MASK_MASK)
6592 
6593 #define AHBSC_SEC_CPU1_INT_MASK3_INT97_MASK_MASK (0x2U)
6594 #define AHBSC_SEC_CPU1_INT_MASK3_INT97_MASK_SHIFT (1U)
6595 /*! INT97_MASK - Mask bit
6596  *  0b0..Masked
6597  *  0b1..Not masked
6598  */
6599 #define AHBSC_SEC_CPU1_INT_MASK3_INT97_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK3_INT97_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK3_INT97_MASK_MASK)
6600 
6601 #define AHBSC_SEC_CPU1_INT_MASK3_INT98_MASK_MASK (0x4U)
6602 #define AHBSC_SEC_CPU1_INT_MASK3_INT98_MASK_SHIFT (2U)
6603 /*! INT98_MASK - Mask bit
6604  *  0b0..Masked
6605  *  0b1..Not masked
6606  */
6607 #define AHBSC_SEC_CPU1_INT_MASK3_INT98_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK3_INT98_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK3_INT98_MASK_MASK)
6608 
6609 #define AHBSC_SEC_CPU1_INT_MASK3_INT99_MASK_MASK (0x8U)
6610 #define AHBSC_SEC_CPU1_INT_MASK3_INT99_MASK_SHIFT (3U)
6611 /*! INT99_MASK - Mask bit
6612  *  0b0..Masked
6613  *  0b1..Not masked
6614  */
6615 #define AHBSC_SEC_CPU1_INT_MASK3_INT99_MASK(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK3_INT99_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK3_INT99_MASK_MASK)
6616 
6617 #define AHBSC_SEC_CPU1_INT_MASK3_INT100_MASK_MASK (0x10U)
6618 #define AHBSC_SEC_CPU1_INT_MASK3_INT100_MASK_SHIFT (4U)
6619 /*! INT100_MASK - Mask bit
6620  *  0b0..Masked
6621  *  0b1..Not masked
6622  */
6623 #define AHBSC_SEC_CPU1_INT_MASK3_INT100_MASK(x)  (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK3_INT100_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK3_INT100_MASK_MASK)
6624 
6625 #define AHBSC_SEC_CPU1_INT_MASK3_INT101_MASK_MASK (0x20U)
6626 #define AHBSC_SEC_CPU1_INT_MASK3_INT101_MASK_SHIFT (5U)
6627 /*! INT101_MASK - Mask bit
6628  *  0b0..Masked
6629  *  0b1..Not masked
6630  */
6631 #define AHBSC_SEC_CPU1_INT_MASK3_INT101_MASK(x)  (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK3_INT101_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK3_INT101_MASK_MASK)
6632 
6633 #define AHBSC_SEC_CPU1_INT_MASK3_INT102_MASK_MASK (0x40U)
6634 #define AHBSC_SEC_CPU1_INT_MASK3_INT102_MASK_SHIFT (6U)
6635 /*! INT102_MASK - Mask bit
6636  *  0b0..Masked
6637  *  0b1..Not masked
6638  */
6639 #define AHBSC_SEC_CPU1_INT_MASK3_INT102_MASK(x)  (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK3_INT102_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK3_INT102_MASK_MASK)
6640 
6641 #define AHBSC_SEC_CPU1_INT_MASK3_INT103_MASK_MASK (0x80U)
6642 #define AHBSC_SEC_CPU1_INT_MASK3_INT103_MASK_SHIFT (7U)
6643 /*! INT103_MASK - Mask bit
6644  *  0b0..Masked
6645  *  0b1..Not masked
6646  */
6647 #define AHBSC_SEC_CPU1_INT_MASK3_INT103_MASK(x)  (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK3_INT103_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK3_INT103_MASK_MASK)
6648 
6649 #define AHBSC_SEC_CPU1_INT_MASK3_INT104_MASK_MASK (0x100U)
6650 #define AHBSC_SEC_CPU1_INT_MASK3_INT104_MASK_SHIFT (8U)
6651 /*! INT104_MASK - Mask bit
6652  *  0b0..Masked
6653  *  0b1..Not masked
6654  */
6655 #define AHBSC_SEC_CPU1_INT_MASK3_INT104_MASK(x)  (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK3_INT104_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK3_INT104_MASK_MASK)
6656 
6657 #define AHBSC_SEC_CPU1_INT_MASK3_INT105_MASK_MASK (0x200U)
6658 #define AHBSC_SEC_CPU1_INT_MASK3_INT105_MASK_SHIFT (9U)
6659 /*! INT105_MASK - Mask bit
6660  *  0b0..Masked
6661  *  0b1..Not masked
6662  */
6663 #define AHBSC_SEC_CPU1_INT_MASK3_INT105_MASK(x)  (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK3_INT105_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK3_INT105_MASK_MASK)
6664 
6665 #define AHBSC_SEC_CPU1_INT_MASK3_INT106_MASK_MASK (0x400U)
6666 #define AHBSC_SEC_CPU1_INT_MASK3_INT106_MASK_SHIFT (10U)
6667 /*! INT106_MASK - Mask bit
6668  *  0b0..Masked
6669  *  0b1..Not masked
6670  */
6671 #define AHBSC_SEC_CPU1_INT_MASK3_INT106_MASK(x)  (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK3_INT106_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK3_INT106_MASK_MASK)
6672 
6673 #define AHBSC_SEC_CPU1_INT_MASK3_INT107_MASK_MASK (0x800U)
6674 #define AHBSC_SEC_CPU1_INT_MASK3_INT107_MASK_SHIFT (11U)
6675 /*! INT107_MASK - Mask bit
6676  *  0b0..Masked
6677  *  0b1..Not masked
6678  */
6679 #define AHBSC_SEC_CPU1_INT_MASK3_INT107_MASK(x)  (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK3_INT107_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK3_INT107_MASK_MASK)
6680 
6681 #define AHBSC_SEC_CPU1_INT_MASK3_INT108_MASK_MASK (0x1000U)
6682 #define AHBSC_SEC_CPU1_INT_MASK3_INT108_MASK_SHIFT (12U)
6683 /*! INT108_MASK - Mask bit
6684  *  0b0..Masked
6685  *  0b1..Not masked
6686  */
6687 #define AHBSC_SEC_CPU1_INT_MASK3_INT108_MASK(x)  (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK3_INT108_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK3_INT108_MASK_MASK)
6688 
6689 #define AHBSC_SEC_CPU1_INT_MASK3_INT109_MASK_MASK (0x2000U)
6690 #define AHBSC_SEC_CPU1_INT_MASK3_INT109_MASK_SHIFT (13U)
6691 /*! INT109_MASK - Mask bit
6692  *  0b0..Masked
6693  *  0b1..Not masked
6694  */
6695 #define AHBSC_SEC_CPU1_INT_MASK3_INT109_MASK(x)  (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK3_INT109_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK3_INT109_MASK_MASK)
6696 
6697 #define AHBSC_SEC_CPU1_INT_MASK3_INT110_MASK_MASK (0x4000U)
6698 #define AHBSC_SEC_CPU1_INT_MASK3_INT110_MASK_SHIFT (14U)
6699 /*! INT110_MASK - Mask bit
6700  *  0b0..Masked
6701  *  0b1..Not masked
6702  */
6703 #define AHBSC_SEC_CPU1_INT_MASK3_INT110_MASK(x)  (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK3_INT110_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK3_INT110_MASK_MASK)
6704 
6705 #define AHBSC_SEC_CPU1_INT_MASK3_INT111_MASK_MASK (0x8000U)
6706 #define AHBSC_SEC_CPU1_INT_MASK3_INT111_MASK_SHIFT (15U)
6707 /*! INT111_MASK - Mask bit
6708  *  0b0..Masked
6709  *  0b1..Not masked
6710  */
6711 #define AHBSC_SEC_CPU1_INT_MASK3_INT111_MASK(x)  (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK3_INT111_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK3_INT111_MASK_MASK)
6712 
6713 #define AHBSC_SEC_CPU1_INT_MASK3_INT112_MASK_MASK (0x10000U)
6714 #define AHBSC_SEC_CPU1_INT_MASK3_INT112_MASK_SHIFT (16U)
6715 /*! INT112_MASK - Mask bit
6716  *  0b0..Masked
6717  *  0b1..Not masked
6718  */
6719 #define AHBSC_SEC_CPU1_INT_MASK3_INT112_MASK(x)  (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK3_INT112_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK3_INT112_MASK_MASK)
6720 
6721 #define AHBSC_SEC_CPU1_INT_MASK3_INT113_MASK_MASK (0x20000U)
6722 #define AHBSC_SEC_CPU1_INT_MASK3_INT113_MASK_SHIFT (17U)
6723 /*! INT113_MASK - Mask bit
6724  *  0b0..Masked
6725  *  0b1..Not masked
6726  */
6727 #define AHBSC_SEC_CPU1_INT_MASK3_INT113_MASK(x)  (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK3_INT113_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK3_INT113_MASK_MASK)
6728 
6729 #define AHBSC_SEC_CPU1_INT_MASK3_INT114_MASK_MASK (0x40000U)
6730 #define AHBSC_SEC_CPU1_INT_MASK3_INT114_MASK_SHIFT (18U)
6731 /*! INT114_MASK - Mask bit
6732  *  0b0..Masked
6733  *  0b1..Not masked
6734  */
6735 #define AHBSC_SEC_CPU1_INT_MASK3_INT114_MASK(x)  (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK3_INT114_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK3_INT114_MASK_MASK)
6736 
6737 #define AHBSC_SEC_CPU1_INT_MASK3_INT115_MASK_MASK (0x80000U)
6738 #define AHBSC_SEC_CPU1_INT_MASK3_INT115_MASK_SHIFT (19U)
6739 /*! INT115_MASK - Mask bit
6740  *  0b0..Masked
6741  *  0b1..Not masked
6742  */
6743 #define AHBSC_SEC_CPU1_INT_MASK3_INT115_MASK(x)  (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK3_INT115_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK3_INT115_MASK_MASK)
6744 
6745 #define AHBSC_SEC_CPU1_INT_MASK3_INT116_MASK_MASK (0x100000U)
6746 #define AHBSC_SEC_CPU1_INT_MASK3_INT116_MASK_SHIFT (20U)
6747 /*! INT116_MASK - Mask bit
6748  *  0b0..Masked
6749  *  0b1..Not masked
6750  */
6751 #define AHBSC_SEC_CPU1_INT_MASK3_INT116_MASK(x)  (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK3_INT116_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK3_INT116_MASK_MASK)
6752 
6753 #define AHBSC_SEC_CPU1_INT_MASK3_INT117_MASK_MASK (0x200000U)
6754 #define AHBSC_SEC_CPU1_INT_MASK3_INT117_MASK_SHIFT (21U)
6755 /*! INT117_MASK - Mask bit
6756  *  0b0..Masked
6757  *  0b1..Not masked
6758  */
6759 #define AHBSC_SEC_CPU1_INT_MASK3_INT117_MASK(x)  (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK3_INT117_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK3_INT117_MASK_MASK)
6760 
6761 #define AHBSC_SEC_CPU1_INT_MASK3_INT118_MASK_MASK (0x400000U)
6762 #define AHBSC_SEC_CPU1_INT_MASK3_INT118_MASK_SHIFT (22U)
6763 /*! INT118_MASK - Mask bit
6764  *  0b0..Masked
6765  *  0b1..Not masked
6766  */
6767 #define AHBSC_SEC_CPU1_INT_MASK3_INT118_MASK(x)  (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK3_INT118_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK3_INT118_MASK_MASK)
6768 
6769 #define AHBSC_SEC_CPU1_INT_MASK3_INT119_MASK_MASK (0x800000U)
6770 #define AHBSC_SEC_CPU1_INT_MASK3_INT119_MASK_SHIFT (23U)
6771 /*! INT119_MASK - Mask bit
6772  *  0b0..Masked
6773  *  0b1..Not masked
6774  */
6775 #define AHBSC_SEC_CPU1_INT_MASK3_INT119_MASK(x)  (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK3_INT119_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK3_INT119_MASK_MASK)
6776 
6777 #define AHBSC_SEC_CPU1_INT_MASK3_INT120_MASK_MASK (0x1000000U)
6778 #define AHBSC_SEC_CPU1_INT_MASK3_INT120_MASK_SHIFT (24U)
6779 /*! INT120_MASK - Mask bit
6780  *  0b0..Masked
6781  *  0b1..Not masked
6782  */
6783 #define AHBSC_SEC_CPU1_INT_MASK3_INT120_MASK(x)  (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK3_INT120_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK3_INT120_MASK_MASK)
6784 
6785 #define AHBSC_SEC_CPU1_INT_MASK3_INT121_MASK_MASK (0x2000000U)
6786 #define AHBSC_SEC_CPU1_INT_MASK3_INT121_MASK_SHIFT (25U)
6787 /*! INT121_MASK - Mask bit
6788  *  0b0..Masked
6789  *  0b1..Not masked
6790  */
6791 #define AHBSC_SEC_CPU1_INT_MASK3_INT121_MASK(x)  (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK3_INT121_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK3_INT121_MASK_MASK)
6792 
6793 #define AHBSC_SEC_CPU1_INT_MASK3_INT122_MASK_MASK (0x4000000U)
6794 #define AHBSC_SEC_CPU1_INT_MASK3_INT122_MASK_SHIFT (26U)
6795 /*! INT122_MASK - Mask bit
6796  *  0b0..Masked
6797  *  0b1..Not masked
6798  */
6799 #define AHBSC_SEC_CPU1_INT_MASK3_INT122_MASK(x)  (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK3_INT122_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK3_INT122_MASK_MASK)
6800 
6801 #define AHBSC_SEC_CPU1_INT_MASK3_INT123_MASK_MASK (0x8000000U)
6802 #define AHBSC_SEC_CPU1_INT_MASK3_INT123_MASK_SHIFT (27U)
6803 /*! INT123_MASK - Mask bit
6804  *  0b0..Masked
6805  *  0b1..Not masked
6806  */
6807 #define AHBSC_SEC_CPU1_INT_MASK3_INT123_MASK(x)  (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK3_INT123_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK3_INT123_MASK_MASK)
6808 
6809 #define AHBSC_SEC_CPU1_INT_MASK3_INT124_MASK_MASK (0x10000000U)
6810 #define AHBSC_SEC_CPU1_INT_MASK3_INT124_MASK_SHIFT (28U)
6811 /*! INT124_MASK - Mask bit
6812  *  0b0..Masked
6813  *  0b1..Not masked
6814  */
6815 #define AHBSC_SEC_CPU1_INT_MASK3_INT124_MASK(x)  (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK3_INT124_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK3_INT124_MASK_MASK)
6816 
6817 #define AHBSC_SEC_CPU1_INT_MASK3_INT125_MASK_MASK (0x20000000U)
6818 #define AHBSC_SEC_CPU1_INT_MASK3_INT125_MASK_SHIFT (29U)
6819 /*! INT125_MASK - Mask bit
6820  *  0b0..Masked
6821  *  0b1..Not masked
6822  */
6823 #define AHBSC_SEC_CPU1_INT_MASK3_INT125_MASK(x)  (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK3_INT125_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK3_INT125_MASK_MASK)
6824 
6825 #define AHBSC_SEC_CPU1_INT_MASK3_INT126_MASK_MASK (0x40000000U)
6826 #define AHBSC_SEC_CPU1_INT_MASK3_INT126_MASK_SHIFT (30U)
6827 /*! INT126_MASK - Mask bit
6828  *  0b0..Masked
6829  *  0b1..Not masked
6830  */
6831 #define AHBSC_SEC_CPU1_INT_MASK3_INT126_MASK(x)  (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK3_INT126_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK3_INT126_MASK_MASK)
6832 
6833 #define AHBSC_SEC_CPU1_INT_MASK3_INT127_MASK_MASK (0x80000000U)
6834 #define AHBSC_SEC_CPU1_INT_MASK3_INT127_MASK_SHIFT (31U)
6835 /*! INT127_MASK - Mask bit
6836  *  0b0..Masked
6837  *  0b1..Not masked
6838  */
6839 #define AHBSC_SEC_CPU1_INT_MASK3_INT127_MASK(x)  (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK3_INT127_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK3_INT127_MASK_MASK)
6840 /*! @} */
6841 
6842 /*! @name SEC_CPU1_INT_MASK4 - Secure Interrupt Mask 4 for CPU1 */
6843 /*! @{ */
6844 
6845 #define AHBSC_SEC_CPU1_INT_MASK4_INT128_MASK_MASK (0x1U)
6846 #define AHBSC_SEC_CPU1_INT_MASK4_INT128_MASK_SHIFT (0U)
6847 /*! INT128_MASK - Mask bit
6848  *  0b0..Masked
6849  *  0b1..Not masked
6850  */
6851 #define AHBSC_SEC_CPU1_INT_MASK4_INT128_MASK(x)  (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK4_INT128_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK4_INT128_MASK_MASK)
6852 
6853 #define AHBSC_SEC_CPU1_INT_MASK4_INT129_MASK_MASK (0x2U)
6854 #define AHBSC_SEC_CPU1_INT_MASK4_INT129_MASK_SHIFT (1U)
6855 /*! INT129_MASK - Mask bit
6856  *  0b0..Masked
6857  *  0b1..Not masked
6858  */
6859 #define AHBSC_SEC_CPU1_INT_MASK4_INT129_MASK(x)  (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK4_INT129_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK4_INT129_MASK_MASK)
6860 
6861 #define AHBSC_SEC_CPU1_INT_MASK4_INT130_MASK_MASK (0x4U)
6862 #define AHBSC_SEC_CPU1_INT_MASK4_INT130_MASK_SHIFT (2U)
6863 /*! INT130_MASK - Mask bit
6864  *  0b0..Masked
6865  *  0b1..Not masked
6866  */
6867 #define AHBSC_SEC_CPU1_INT_MASK4_INT130_MASK(x)  (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK4_INT130_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK4_INT130_MASK_MASK)
6868 
6869 #define AHBSC_SEC_CPU1_INT_MASK4_INT131_MASK_MASK (0x8U)
6870 #define AHBSC_SEC_CPU1_INT_MASK4_INT131_MASK_SHIFT (3U)
6871 /*! INT131_MASK - Mask bit
6872  *  0b0..Masked
6873  *  0b1..Not masked
6874  */
6875 #define AHBSC_SEC_CPU1_INT_MASK4_INT131_MASK(x)  (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK4_INT131_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK4_INT131_MASK_MASK)
6876 
6877 #define AHBSC_SEC_CPU1_INT_MASK4_INT132_MASK_MASK (0x10U)
6878 #define AHBSC_SEC_CPU1_INT_MASK4_INT132_MASK_SHIFT (4U)
6879 /*! INT132_MASK - Mask bit
6880  *  0b0..Masked
6881  *  0b1..Not masked
6882  */
6883 #define AHBSC_SEC_CPU1_INT_MASK4_INT132_MASK(x)  (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK4_INT132_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK4_INT132_MASK_MASK)
6884 
6885 #define AHBSC_SEC_CPU1_INT_MASK4_INT133_MASK_MASK (0x20U)
6886 #define AHBSC_SEC_CPU1_INT_MASK4_INT133_MASK_SHIFT (5U)
6887 /*! INT133_MASK - Mask bit
6888  *  0b0..Masked
6889  *  0b1..Not masked
6890  */
6891 #define AHBSC_SEC_CPU1_INT_MASK4_INT133_MASK(x)  (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK4_INT133_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK4_INT133_MASK_MASK)
6892 
6893 #define AHBSC_SEC_CPU1_INT_MASK4_INT134_MASK_MASK (0x40U)
6894 #define AHBSC_SEC_CPU1_INT_MASK4_INT134_MASK_SHIFT (6U)
6895 /*! INT134_MASK - Mask bit
6896  *  0b0..Masked
6897  *  0b1..Not masked
6898  */
6899 #define AHBSC_SEC_CPU1_INT_MASK4_INT134_MASK(x)  (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK4_INT134_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK4_INT134_MASK_MASK)
6900 
6901 #define AHBSC_SEC_CPU1_INT_MASK4_INT135_MASK_MASK (0x80U)
6902 #define AHBSC_SEC_CPU1_INT_MASK4_INT135_MASK_SHIFT (7U)
6903 /*! INT135_MASK - Mask bit
6904  *  0b0..Masked
6905  *  0b1..Not masked
6906  */
6907 #define AHBSC_SEC_CPU1_INT_MASK4_INT135_MASK(x)  (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK4_INT135_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK4_INT135_MASK_MASK)
6908 
6909 #define AHBSC_SEC_CPU1_INT_MASK4_INT136_MASK_MASK (0x100U)
6910 #define AHBSC_SEC_CPU1_INT_MASK4_INT136_MASK_SHIFT (8U)
6911 /*! INT136_MASK - Mask bit
6912  *  0b0..Masked
6913  *  0b1..Not masked
6914  */
6915 #define AHBSC_SEC_CPU1_INT_MASK4_INT136_MASK(x)  (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK4_INT136_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK4_INT136_MASK_MASK)
6916 
6917 #define AHBSC_SEC_CPU1_INT_MASK4_INT137_MASK_MASK (0x200U)
6918 #define AHBSC_SEC_CPU1_INT_MASK4_INT137_MASK_SHIFT (9U)
6919 /*! INT137_MASK - Mask bit
6920  *  0b0..Masked
6921  *  0b1..Not masked
6922  */
6923 #define AHBSC_SEC_CPU1_INT_MASK4_INT137_MASK(x)  (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK4_INT137_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK4_INT137_MASK_MASK)
6924 
6925 #define AHBSC_SEC_CPU1_INT_MASK4_INT138_MASK_MASK (0x400U)
6926 #define AHBSC_SEC_CPU1_INT_MASK4_INT138_MASK_SHIFT (10U)
6927 /*! INT138_MASK - Mask bit
6928  *  0b0..Masked
6929  *  0b1..Not masked
6930  */
6931 #define AHBSC_SEC_CPU1_INT_MASK4_INT138_MASK(x)  (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK4_INT138_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK4_INT138_MASK_MASK)
6932 
6933 #define AHBSC_SEC_CPU1_INT_MASK4_INT139_MASK_MASK (0x800U)
6934 #define AHBSC_SEC_CPU1_INT_MASK4_INT139_MASK_SHIFT (11U)
6935 /*! INT139_MASK - Mask bit
6936  *  0b0..Masked
6937  *  0b1..Not masked
6938  */
6939 #define AHBSC_SEC_CPU1_INT_MASK4_INT139_MASK(x)  (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK4_INT139_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK4_INT139_MASK_MASK)
6940 
6941 #define AHBSC_SEC_CPU1_INT_MASK4_INT140_MASK_MASK (0x1000U)
6942 #define AHBSC_SEC_CPU1_INT_MASK4_INT140_MASK_SHIFT (12U)
6943 /*! INT140_MASK - Mask bit
6944  *  0b0..Masked
6945  *  0b1..Not masked
6946  */
6947 #define AHBSC_SEC_CPU1_INT_MASK4_INT140_MASK(x)  (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK4_INT140_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK4_INT140_MASK_MASK)
6948 
6949 #define AHBSC_SEC_CPU1_INT_MASK4_INT141_MASK_MASK (0x2000U)
6950 #define AHBSC_SEC_CPU1_INT_MASK4_INT141_MASK_SHIFT (13U)
6951 /*! INT141_MASK - Mask bit
6952  *  0b0..Masked
6953  *  0b1..Not masked
6954  */
6955 #define AHBSC_SEC_CPU1_INT_MASK4_INT141_MASK(x)  (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK4_INT141_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK4_INT141_MASK_MASK)
6956 
6957 #define AHBSC_SEC_CPU1_INT_MASK4_INT142_MASK_MASK (0x4000U)
6958 #define AHBSC_SEC_CPU1_INT_MASK4_INT142_MASK_SHIFT (14U)
6959 /*! INT142_MASK - Mask bit
6960  *  0b0..Masked
6961  *  0b1..Not masked
6962  */
6963 #define AHBSC_SEC_CPU1_INT_MASK4_INT142_MASK(x)  (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK4_INT142_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK4_INT142_MASK_MASK)
6964 
6965 #define AHBSC_SEC_CPU1_INT_MASK4_INT143_MASK_MASK (0x8000U)
6966 #define AHBSC_SEC_CPU1_INT_MASK4_INT143_MASK_SHIFT (15U)
6967 /*! INT143_MASK - Mask bit
6968  *  0b0..Masked
6969  *  0b1..Not masked
6970  */
6971 #define AHBSC_SEC_CPU1_INT_MASK4_INT143_MASK(x)  (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK4_INT143_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK4_INT143_MASK_MASK)
6972 
6973 #define AHBSC_SEC_CPU1_INT_MASK4_INT144_MASK_MASK (0x10000U)
6974 #define AHBSC_SEC_CPU1_INT_MASK4_INT144_MASK_SHIFT (16U)
6975 /*! INT144_MASK - Mask bit
6976  *  0b0..Masked
6977  *  0b1..Not masked
6978  */
6979 #define AHBSC_SEC_CPU1_INT_MASK4_INT144_MASK(x)  (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK4_INT144_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK4_INT144_MASK_MASK)
6980 
6981 #define AHBSC_SEC_CPU1_INT_MASK4_INT145_MASK_MASK (0x20000U)
6982 #define AHBSC_SEC_CPU1_INT_MASK4_INT145_MASK_SHIFT (17U)
6983 /*! INT145_MASK - Mask bit
6984  *  0b0..Masked
6985  *  0b1..Not masked
6986  */
6987 #define AHBSC_SEC_CPU1_INT_MASK4_INT145_MASK(x)  (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK4_INT145_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK4_INT145_MASK_MASK)
6988 
6989 #define AHBSC_SEC_CPU1_INT_MASK4_INT146_MASK_MASK (0x40000U)
6990 #define AHBSC_SEC_CPU1_INT_MASK4_INT146_MASK_SHIFT (18U)
6991 /*! INT146_MASK - Mask bit
6992  *  0b0..Masked
6993  *  0b1..Not masked
6994  */
6995 #define AHBSC_SEC_CPU1_INT_MASK4_INT146_MASK(x)  (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK4_INT146_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK4_INT146_MASK_MASK)
6996 
6997 #define AHBSC_SEC_CPU1_INT_MASK4_INT147_MASK_MASK (0x80000U)
6998 #define AHBSC_SEC_CPU1_INT_MASK4_INT147_MASK_SHIFT (19U)
6999 /*! INT147_MASK - Mask bit
7000  *  0b0..Masked
7001  *  0b1..Not masked
7002  */
7003 #define AHBSC_SEC_CPU1_INT_MASK4_INT147_MASK(x)  (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK4_INT147_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK4_INT147_MASK_MASK)
7004 
7005 #define AHBSC_SEC_CPU1_INT_MASK4_INT148_MASK_MASK (0x100000U)
7006 #define AHBSC_SEC_CPU1_INT_MASK4_INT148_MASK_SHIFT (20U)
7007 /*! INT148_MASK - Mask bit
7008  *  0b0..Masked
7009  *  0b1..Not masked
7010  */
7011 #define AHBSC_SEC_CPU1_INT_MASK4_INT148_MASK(x)  (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK4_INT148_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK4_INT148_MASK_MASK)
7012 
7013 #define AHBSC_SEC_CPU1_INT_MASK4_INT149_MASK_MASK (0x200000U)
7014 #define AHBSC_SEC_CPU1_INT_MASK4_INT149_MASK_SHIFT (21U)
7015 /*! INT149_MASK - Mask bit
7016  *  0b0..Masked
7017  *  0b1..Not masked
7018  */
7019 #define AHBSC_SEC_CPU1_INT_MASK4_INT149_MASK(x)  (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK4_INT149_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK4_INT149_MASK_MASK)
7020 
7021 #define AHBSC_SEC_CPU1_INT_MASK4_INT150_MASK_MASK (0x400000U)
7022 #define AHBSC_SEC_CPU1_INT_MASK4_INT150_MASK_SHIFT (22U)
7023 /*! INT150_MASK - Mask bit
7024  *  0b0..Masked
7025  *  0b1..Not masked
7026  */
7027 #define AHBSC_SEC_CPU1_INT_MASK4_INT150_MASK(x)  (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK4_INT150_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK4_INT150_MASK_MASK)
7028 
7029 #define AHBSC_SEC_CPU1_INT_MASK4_INT151_MASK_MASK (0x800000U)
7030 #define AHBSC_SEC_CPU1_INT_MASK4_INT151_MASK_SHIFT (23U)
7031 /*! INT151_MASK - Mask bit
7032  *  0b0..Masked
7033  *  0b1..Not masked
7034  */
7035 #define AHBSC_SEC_CPU1_INT_MASK4_INT151_MASK(x)  (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK4_INT151_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK4_INT151_MASK_MASK)
7036 
7037 #define AHBSC_SEC_CPU1_INT_MASK4_INT152_MASK_MASK (0x1000000U)
7038 #define AHBSC_SEC_CPU1_INT_MASK4_INT152_MASK_SHIFT (24U)
7039 /*! INT152_MASK - Mask bit
7040  *  0b0..Masked
7041  *  0b1..Not masked
7042  */
7043 #define AHBSC_SEC_CPU1_INT_MASK4_INT152_MASK(x)  (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK4_INT152_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK4_INT152_MASK_MASK)
7044 
7045 #define AHBSC_SEC_CPU1_INT_MASK4_INT153_MASK_MASK (0x2000000U)
7046 #define AHBSC_SEC_CPU1_INT_MASK4_INT153_MASK_SHIFT (25U)
7047 /*! INT153_MASK - Mask bit
7048  *  0b0..Masked
7049  *  0b1..Not masked
7050  */
7051 #define AHBSC_SEC_CPU1_INT_MASK4_INT153_MASK(x)  (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK4_INT153_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK4_INT153_MASK_MASK)
7052 
7053 #define AHBSC_SEC_CPU1_INT_MASK4_INT154_MASK_MASK (0x4000000U)
7054 #define AHBSC_SEC_CPU1_INT_MASK4_INT154_MASK_SHIFT (26U)
7055 /*! INT154_MASK - Mask bit
7056  *  0b0..Masked
7057  *  0b1..Not masked
7058  */
7059 #define AHBSC_SEC_CPU1_INT_MASK4_INT154_MASK(x)  (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK4_INT154_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK4_INT154_MASK_MASK)
7060 
7061 #define AHBSC_SEC_CPU1_INT_MASK4_INT155_MASK_MASK (0x8000000U)
7062 #define AHBSC_SEC_CPU1_INT_MASK4_INT155_MASK_SHIFT (27U)
7063 /*! INT155_MASK - Mask bit
7064  *  0b0..Masked
7065  *  0b1..Not masked
7066  */
7067 #define AHBSC_SEC_CPU1_INT_MASK4_INT155_MASK(x)  (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK4_INT155_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK4_INT155_MASK_MASK)
7068 
7069 #define AHBSC_SEC_CPU1_INT_MASK4_INT156_MASK_MASK (0x10000000U)
7070 #define AHBSC_SEC_CPU1_INT_MASK4_INT156_MASK_SHIFT (28U)
7071 /*! INT156_MASK - Mask bit
7072  *  0b0..Masked
7073  *  0b1..Not masked
7074  */
7075 #define AHBSC_SEC_CPU1_INT_MASK4_INT156_MASK(x)  (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK4_INT156_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK4_INT156_MASK_MASK)
7076 
7077 #define AHBSC_SEC_CPU1_INT_MASK4_INT157_MASK_MASK (0x20000000U)
7078 #define AHBSC_SEC_CPU1_INT_MASK4_INT157_MASK_SHIFT (29U)
7079 /*! INT157_MASK - Mask bit
7080  *  0b0..Masked
7081  *  0b1..Not masked
7082  */
7083 #define AHBSC_SEC_CPU1_INT_MASK4_INT157_MASK(x)  (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK4_INT157_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK4_INT157_MASK_MASK)
7084 
7085 #define AHBSC_SEC_CPU1_INT_MASK4_INT158_MASK_MASK (0x40000000U)
7086 #define AHBSC_SEC_CPU1_INT_MASK4_INT158_MASK_SHIFT (30U)
7087 /*! INT158_MASK - Mask bit
7088  *  0b0..Masked
7089  *  0b1..Not masked
7090  */
7091 #define AHBSC_SEC_CPU1_INT_MASK4_INT158_MASK(x)  (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK4_INT158_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK4_INT158_MASK_MASK)
7092 
7093 #define AHBSC_SEC_CPU1_INT_MASK4_INT159_MASK_MASK (0x80000000U)
7094 #define AHBSC_SEC_CPU1_INT_MASK4_INT159_MASK_SHIFT (31U)
7095 /*! INT159_MASK - Mask bit
7096  *  0b0..Masked
7097  *  0b1..Not masked
7098  */
7099 #define AHBSC_SEC_CPU1_INT_MASK4_INT159_MASK(x)  (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK4_INT159_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK4_INT159_MASK_MASK)
7100 /*! @} */
7101 
7102 /*! @name SEC_GP_REG_LOCK - Secure Mask Lock */
7103 /*! @{ */
7104 
7105 #define AHBSC_SEC_GP_REG_LOCK_SEC_GPIO_MASK0_LOCK_MASK (0x3U)
7106 #define AHBSC_SEC_GP_REG_LOCK_SEC_GPIO_MASK0_LOCK_SHIFT (0U)
7107 /*! SEC_GPIO_MASK0_LOCK - Secure GPIO _MASK0 Lock
7108  *  0b00..Reserved
7109  *  0b01..SEC_GPIO_MASK0 cannot be written
7110  *  0b10..SEC_GPIO_MASK0 can be written
7111  *  0b11..Reserved
7112  */
7113 #define AHBSC_SEC_GP_REG_LOCK_SEC_GPIO_MASK0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GP_REG_LOCK_SEC_GPIO_MASK0_LOCK_SHIFT)) & AHBSC_SEC_GP_REG_LOCK_SEC_GPIO_MASK0_LOCK_MASK)
7114 
7115 #define AHBSC_SEC_GP_REG_LOCK_SEC_GPIO_MASK1_LOCK_MASK (0xCU)
7116 #define AHBSC_SEC_GP_REG_LOCK_SEC_GPIO_MASK1_LOCK_SHIFT (2U)
7117 /*! SEC_GPIO_MASK1_LOCK - Secure GPIO _MASK1 Lock
7118  *  0b00..Reserved
7119  *  0b01..SEC_GPIO_MASK1 cannot be written
7120  *  0b10..SEC_GPIO_MASK1 can be written
7121  *  0b11..Reserved
7122  */
7123 #define AHBSC_SEC_GP_REG_LOCK_SEC_GPIO_MASK1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GP_REG_LOCK_SEC_GPIO_MASK1_LOCK_SHIFT)) & AHBSC_SEC_GP_REG_LOCK_SEC_GPIO_MASK1_LOCK_MASK)
7124 
7125 #define AHBSC_SEC_GP_REG_LOCK_SEC_CPU1_INT_MASK0_LOCK_MASK (0x3000U)
7126 #define AHBSC_SEC_GP_REG_LOCK_SEC_CPU1_INT_MASK0_LOCK_SHIFT (12U)
7127 /*! SEC_CPU1_INT_MASK0_LOCK - SEC_CPU1_INT_MASK0 Lock
7128  *  0b00..Reserved
7129  *  0b01..SEC_GPIO_MASK0 cannot be written
7130  *  0b10..SEC_GPIO_MASK0 can be written
7131  *  0b11..Reserved
7132  */
7133 #define AHBSC_SEC_GP_REG_LOCK_SEC_CPU1_INT_MASK0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GP_REG_LOCK_SEC_CPU1_INT_MASK0_LOCK_SHIFT)) & AHBSC_SEC_GP_REG_LOCK_SEC_CPU1_INT_MASK0_LOCK_MASK)
7134 
7135 #define AHBSC_SEC_GP_REG_LOCK_SEC_CPU1_INT_MASK1_LOCK_MASK (0xC000U)
7136 #define AHBSC_SEC_GP_REG_LOCK_SEC_CPU1_INT_MASK1_LOCK_SHIFT (14U)
7137 /*! SEC_CPU1_INT_MASK1_LOCK - SEC_CPU1_INT_MASK1 Lock
7138  *  0b00..Reserved
7139  *  0b01..SEC_GPIO_MASK1 cannot be written
7140  *  0b10..SEC_GPIO_MASK1 can be written
7141  *  0b11..Reserved
7142  */
7143 #define AHBSC_SEC_GP_REG_LOCK_SEC_CPU1_INT_MASK1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GP_REG_LOCK_SEC_CPU1_INT_MASK1_LOCK_SHIFT)) & AHBSC_SEC_GP_REG_LOCK_SEC_CPU1_INT_MASK1_LOCK_MASK)
7144 
7145 #define AHBSC_SEC_GP_REG_LOCK_SEC_CPU1_INT_MASK2_LOCK_MASK (0x30000U)
7146 #define AHBSC_SEC_GP_REG_LOCK_SEC_CPU1_INT_MASK2_LOCK_SHIFT (16U)
7147 /*! SEC_CPU1_INT_MASK2_LOCK - SEC_CPU1_INT_MASK2 Lock
7148  *  0b00..Reserved
7149  *  0b01..SEC_CPU1_INT_MASK2 cannot be written
7150  *  0b10..SEC_CPU1_INT_MASK2 can be written
7151  *  0b11..Reserved
7152  */
7153 #define AHBSC_SEC_GP_REG_LOCK_SEC_CPU1_INT_MASK2_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GP_REG_LOCK_SEC_CPU1_INT_MASK2_LOCK_SHIFT)) & AHBSC_SEC_GP_REG_LOCK_SEC_CPU1_INT_MASK2_LOCK_MASK)
7154 
7155 #define AHBSC_SEC_GP_REG_LOCK_SEC_CPU1_INT_MASK3_LOCK_MASK (0xC0000U)
7156 #define AHBSC_SEC_GP_REG_LOCK_SEC_CPU1_INT_MASK3_LOCK_SHIFT (18U)
7157 /*! SEC_CPU1_INT_MASK3_LOCK - SEC_CPU1_INT_MASK3 Lock
7158  *  0b00..Reserved
7159  *  0b01..SEC_CPU1_INT_MASK3 cannot be written
7160  *  0b10..SEC_CPU1_INT_MASK3 can be written
7161  *  0b11..Reserved
7162  */
7163 #define AHBSC_SEC_GP_REG_LOCK_SEC_CPU1_INT_MASK3_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GP_REG_LOCK_SEC_CPU1_INT_MASK3_LOCK_SHIFT)) & AHBSC_SEC_GP_REG_LOCK_SEC_CPU1_INT_MASK3_LOCK_MASK)
7164 
7165 #define AHBSC_SEC_GP_REG_LOCK_SEC_CPU1_INT_MASK4_LOCK_MASK (0x300000U)
7166 #define AHBSC_SEC_GP_REG_LOCK_SEC_CPU1_INT_MASK4_LOCK_SHIFT (20U)
7167 /*! SEC_CPU1_INT_MASK4_LOCK - SEC_CPU1_INT_MASK4 Lock
7168  *  0b00..Reserved
7169  *  0b01..SEC_CPU1_INT_MASK4 cannot be written
7170  *  0b10..SEC_CPU1_INT_MASK4 can be written
7171  *  0b11..Reserved
7172  */
7173 #define AHBSC_SEC_GP_REG_LOCK_SEC_CPU1_INT_MASK4_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GP_REG_LOCK_SEC_CPU1_INT_MASK4_LOCK_SHIFT)) & AHBSC_SEC_GP_REG_LOCK_SEC_CPU1_INT_MASK4_LOCK_MASK)
7174 /*! @} */
7175 
7176 /*! @name MASTER_SEC_LEVEL - Master Secure Level */
7177 /*! @{ */
7178 
7179 #define AHBSC_MASTER_SEC_LEVEL_CPU1_MASK         (0xCU)
7180 #define AHBSC_MASTER_SEC_LEVEL_CPU1_SHIFT        (2U)
7181 /*! CPU1 - CPU1
7182  *  0b00..Non-secure and non-privileged Master
7183  *  0b01..Non-secure and privileged Master
7184  *  0b10..Secure and non-privileged Master
7185  *  0b11..Secure and privileged Master
7186  */
7187 #define AHBSC_MASTER_SEC_LEVEL_CPU1(x)           (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_LEVEL_CPU1_SHIFT)) & AHBSC_MASTER_SEC_LEVEL_CPU1_MASK)
7188 
7189 #define AHBSC_MASTER_SEC_LEVEL_SMARTDMA_MASK     (0x30U)
7190 #define AHBSC_MASTER_SEC_LEVEL_SMARTDMA_SHIFT    (4U)
7191 /*! SMARTDMA - SMARTDMA Data
7192  *  0b00..Non-secure and non-privileged Master
7193  *  0b01..Non-secure and privileged Master
7194  *  0b10..Secure and non-privileged Master
7195  *  0b11..Secure and privileged Master
7196  */
7197 #define AHBSC_MASTER_SEC_LEVEL_SMARTDMA(x)       (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_LEVEL_SMARTDMA_SHIFT)) & AHBSC_MASTER_SEC_LEVEL_SMARTDMA_MASK)
7198 
7199 #define AHBSC_MASTER_SEC_LEVEL_EDMA0_MASK        (0xC0U)
7200 #define AHBSC_MASTER_SEC_LEVEL_EDMA0_SHIFT       (6U)
7201 /*! eDMA0 - eDMA0
7202  *  0b00..Non-secure and non-privileged Master
7203  *  0b01..Non-secure and privileged Master
7204  *  0b10..Secure and non-privileged Master
7205  *  0b11..Secure and privileged Master
7206  */
7207 #define AHBSC_MASTER_SEC_LEVEL_EDMA0(x)          (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_LEVEL_EDMA0_SHIFT)) & AHBSC_MASTER_SEC_LEVEL_EDMA0_MASK)
7208 
7209 #define AHBSC_MASTER_SEC_LEVEL_EDMA1_MASK        (0x300U)
7210 #define AHBSC_MASTER_SEC_LEVEL_EDMA1_SHIFT       (8U)
7211 /*! eDMA1 - eDMA1
7212  *  0b00..Non-secure and non-privileged Master
7213  *  0b01..Non-secure and privileged Master
7214  *  0b10..Secure and non-privileged Master
7215  *  0b11..Secure and privileged Master
7216  */
7217 #define AHBSC_MASTER_SEC_LEVEL_EDMA1(x)          (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_LEVEL_EDMA1_SHIFT)) & AHBSC_MASTER_SEC_LEVEL_EDMA1_MASK)
7218 
7219 #define AHBSC_MASTER_SEC_LEVEL_PKC_MASK          (0xC00U)
7220 #define AHBSC_MASTER_SEC_LEVEL_PKC_SHIFT         (10U)
7221 /*! PKC - PKC
7222  *  0b00..Non-secure and non-privileged Master
7223  *  0b01..Non-secure and privileged Master
7224  *  0b10..Secure and non-privileged Master
7225  *  0b11..Secure and privileged Master
7226  */
7227 #define AHBSC_MASTER_SEC_LEVEL_PKC(x)            (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_LEVEL_PKC_SHIFT)) & AHBSC_MASTER_SEC_LEVEL_PKC_MASK)
7228 
7229 #define AHBSC_MASTER_SEC_LEVEL_PQ_MASK           (0xC000U)
7230 #define AHBSC_MASTER_SEC_LEVEL_PQ_SHIFT          (14U)
7231 /*! PQ - PowerQuad
7232  *  0b00..Non-secure and non-privileged Master
7233  *  0b01..Non-secure and privileged Master
7234  *  0b10..Secure and non-privileged Master
7235  *  0b11..Secure and privileged Master
7236  */
7237 #define AHBSC_MASTER_SEC_LEVEL_PQ(x)             (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_LEVEL_PQ_SHIFT)) & AHBSC_MASTER_SEC_LEVEL_PQ_MASK)
7238 
7239 #define AHBSC_MASTER_SEC_LEVEL_NPUO_MASK         (0x30000U)
7240 #define AHBSC_MASTER_SEC_LEVEL_NPUO_SHIFT        (16U)
7241 /*! NPUO - NPU Operands
7242  *  0b00..Non-secure and non-privileged Master
7243  *  0b01..Non-secure and privileged Master
7244  *  0b10..Secure and non-privileged Master
7245  *  0b11..Secure and privileged Master
7246  */
7247 #define AHBSC_MASTER_SEC_LEVEL_NPUO(x)           (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_LEVEL_NPUO_SHIFT)) & AHBSC_MASTER_SEC_LEVEL_NPUO_MASK)
7248 
7249 #define AHBSC_MASTER_SEC_LEVEL_COOLFLUXI_MASK    (0xC0000U)
7250 #define AHBSC_MASTER_SEC_LEVEL_COOLFLUXI_SHIFT   (18U)
7251 /*! COOLFLUXI - Coolflux Instruction
7252  *  0b00..Non-secure and non-privileged Master
7253  *  0b01..Non-secure and privileged Master
7254  *  0b10..Secure and non-privileged Master
7255  *  0b11..Secure and privileged Master
7256  */
7257 #define AHBSC_MASTER_SEC_LEVEL_COOLFLUXI(x)      (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_LEVEL_COOLFLUXI_SHIFT)) & AHBSC_MASTER_SEC_LEVEL_COOLFLUXI_MASK)
7258 
7259 #define AHBSC_MASTER_SEC_LEVEL_USB_FS_MASK       (0xC00000U)
7260 #define AHBSC_MASTER_SEC_LEVEL_USB_FS_SHIFT      (22U)
7261 /*! USB_FS - USB_FS
7262  *  0b00..Non-secure and non-privileged Master
7263  *  0b01..Non-secure and privileged Master
7264  *  0b10..Secure and non-privileged Master
7265  *  0b11..Secure and privileged Master
7266  */
7267 #define AHBSC_MASTER_SEC_LEVEL_USB_FS(x)         (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_LEVEL_USB_FS_SHIFT)) & AHBSC_MASTER_SEC_LEVEL_USB_FS_MASK)
7268 
7269 #define AHBSC_MASTER_SEC_LEVEL_ETHERNET_MASK     (0x3000000U)
7270 #define AHBSC_MASTER_SEC_LEVEL_ETHERNET_SHIFT    (24U)
7271 /*! ETHERNET - Ethernet
7272  *  0b00..Non-secure and non-privileged Master
7273  *  0b01..Non-secure and privileged Master
7274  *  0b10..Secure and non-privileged Master
7275  *  0b11..Secure and privileged Master
7276  */
7277 #define AHBSC_MASTER_SEC_LEVEL_ETHERNET(x)       (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_LEVEL_ETHERNET_SHIFT)) & AHBSC_MASTER_SEC_LEVEL_ETHERNET_MASK)
7278 
7279 #define AHBSC_MASTER_SEC_LEVEL_USB_HS_MASK       (0xC000000U)
7280 #define AHBSC_MASTER_SEC_LEVEL_USB_HS_SHIFT      (26U)
7281 /*! USB_HS - USB HS
7282  *  0b00..Non-secure and non-privileged Master
7283  *  0b01..Non-secure and privileged Master
7284  *  0b10..Secure and non-privileged Master
7285  *  0b11..Secure and privileged Master
7286  */
7287 #define AHBSC_MASTER_SEC_LEVEL_USB_HS(x)         (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_LEVEL_USB_HS_SHIFT)) & AHBSC_MASTER_SEC_LEVEL_USB_HS_MASK)
7288 
7289 #define AHBSC_MASTER_SEC_LEVEL_USDHC_MASK        (0x30000000U)
7290 #define AHBSC_MASTER_SEC_LEVEL_USDHC_SHIFT       (28U)
7291 /*! USDHC - uSDHC
7292  *  0b00..Non-secure and non-privileged Master
7293  *  0b01..Non-secure and privileged Master
7294  *  0b10..Secure and non-privileged Master
7295  *  0b11..Secure and privileged Master
7296  */
7297 #define AHBSC_MASTER_SEC_LEVEL_USDHC(x)          (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_LEVEL_USDHC_SHIFT)) & AHBSC_MASTER_SEC_LEVEL_USDHC_MASK)
7298 
7299 #define AHBSC_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_MASK (0xC0000000U)
7300 #define AHBSC_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_SHIFT (30U)
7301 /*! MASTER_SEC_LEVEL_LOCK - Master SEC Level Lock
7302  *  0b00..Reserved
7303  *  0b01..MASTER_SEC_LEVEL_LOCK cannot be written
7304  *  0b10..MASTER_SEC_LEVEL_LOCK can be written
7305  *  0b11..Reserved
7306  */
7307 #define AHBSC_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_SHIFT)) & AHBSC_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_MASK)
7308 /*! @} */
7309 
7310 /*! @name MASTER_SEC_ANTI_POL_REG - Master Secure Level */
7311 /*! @{ */
7312 
7313 #define AHBSC_MASTER_SEC_ANTI_POL_REG_CPU1_MASK  (0xCU)
7314 #define AHBSC_MASTER_SEC_ANTI_POL_REG_CPU1_SHIFT (2U)
7315 /*! CPU1 - CPU1
7316  *  0b00..Secure and privileged Master
7317  *  0b01..Secure and non-privileged Master
7318  *  0b10..Non-secure and privileged Master
7319  *  0b11..Non-secure and non-privileged Master
7320  */
7321 #define AHBSC_MASTER_SEC_ANTI_POL_REG_CPU1(x)    (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_ANTI_POL_REG_CPU1_SHIFT)) & AHBSC_MASTER_SEC_ANTI_POL_REG_CPU1_MASK)
7322 
7323 #define AHBSC_MASTER_SEC_ANTI_POL_REG_SMARTDMA_MASK (0x30U)
7324 #define AHBSC_MASTER_SEC_ANTI_POL_REG_SMARTDMA_SHIFT (4U)
7325 /*! SMARTDMA - SMARTDMA Data
7326  *  0b00..Secure and privileged Master
7327  *  0b01..Secure and non-privileged Master
7328  *  0b10..Non-secure and privileged Master
7329  *  0b11..Non-secure and non-privileged Master
7330  */
7331 #define AHBSC_MASTER_SEC_ANTI_POL_REG_SMARTDMA(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_ANTI_POL_REG_SMARTDMA_SHIFT)) & AHBSC_MASTER_SEC_ANTI_POL_REG_SMARTDMA_MASK)
7332 
7333 #define AHBSC_MASTER_SEC_ANTI_POL_REG_EDMA0_MASK (0xC0U)
7334 #define AHBSC_MASTER_SEC_ANTI_POL_REG_EDMA0_SHIFT (6U)
7335 /*! eDMA0 - eDMA0
7336  *  0b00..Secure and privileged Master
7337  *  0b01..Secure and non-privileged Master
7338  *  0b10..Non-secure and privileged Master
7339  *  0b11..Non-secure and non-privileged Master
7340  */
7341 #define AHBSC_MASTER_SEC_ANTI_POL_REG_EDMA0(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_ANTI_POL_REG_EDMA0_SHIFT)) & AHBSC_MASTER_SEC_ANTI_POL_REG_EDMA0_MASK)
7342 
7343 #define AHBSC_MASTER_SEC_ANTI_POL_REG_EDMA1_MASK (0x300U)
7344 #define AHBSC_MASTER_SEC_ANTI_POL_REG_EDMA1_SHIFT (8U)
7345 /*! eDMA1 - eDMA1
7346  *  0b00..Secure and privileged Master
7347  *  0b01..Secure and non-privileged Master
7348  *  0b10..Non-secure and privileged Master
7349  *  0b11..Non-secure and non-privileged Master
7350  */
7351 #define AHBSC_MASTER_SEC_ANTI_POL_REG_EDMA1(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_ANTI_POL_REG_EDMA1_SHIFT)) & AHBSC_MASTER_SEC_ANTI_POL_REG_EDMA1_MASK)
7352 
7353 #define AHBSC_MASTER_SEC_ANTI_POL_REG_PKC_MASK   (0xC00U)
7354 #define AHBSC_MASTER_SEC_ANTI_POL_REG_PKC_SHIFT  (10U)
7355 /*! PKC - PKC
7356  *  0b00..Secure and privileged Master
7357  *  0b01..Secure and non-privileged Master
7358  *  0b10..Non-secure and privileged Master
7359  *  0b11..Non-secure and non-privileged Master
7360  */
7361 #define AHBSC_MASTER_SEC_ANTI_POL_REG_PKC(x)     (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_ANTI_POL_REG_PKC_SHIFT)) & AHBSC_MASTER_SEC_ANTI_POL_REG_PKC_MASK)
7362 
7363 #define AHBSC_MASTER_SEC_ANTI_POL_REG_PQ_MASK    (0xC000U)
7364 #define AHBSC_MASTER_SEC_ANTI_POL_REG_PQ_SHIFT   (14U)
7365 /*! PQ - PowerQuad
7366  *  0b00..Secure and privileged Master
7367  *  0b01..Secure and non-privileged Master
7368  *  0b10..Non-secure and privileged Master
7369  *  0b11..Non-secure and non-privileged Master
7370  */
7371 #define AHBSC_MASTER_SEC_ANTI_POL_REG_PQ(x)      (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_ANTI_POL_REG_PQ_SHIFT)) & AHBSC_MASTER_SEC_ANTI_POL_REG_PQ_MASK)
7372 
7373 #define AHBSC_MASTER_SEC_ANTI_POL_REG_NPUO_MASK  (0x30000U)
7374 #define AHBSC_MASTER_SEC_ANTI_POL_REG_NPUO_SHIFT (16U)
7375 /*! NPUO - NPU Operands
7376  *  0b00..Secure and privileged Master
7377  *  0b01..Secure and non-privileged Master
7378  *  0b10..Non-secure and privileged Master
7379  *  0b11..Non-secure and non-privileged Master
7380  */
7381 #define AHBSC_MASTER_SEC_ANTI_POL_REG_NPUO(x)    (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_ANTI_POL_REG_NPUO_SHIFT)) & AHBSC_MASTER_SEC_ANTI_POL_REG_NPUO_MASK)
7382 
7383 #define AHBSC_MASTER_SEC_ANTI_POL_REG_COOLFLUXI_MASK (0xC0000U)
7384 #define AHBSC_MASTER_SEC_ANTI_POL_REG_COOLFLUXI_SHIFT (18U)
7385 /*! COOLFLUXI - Coolflux Instruction
7386  *  0b00..Secure and privileged Master
7387  *  0b01..Secure and non-privileged Master
7388  *  0b10..Non-secure and privileged Master
7389  *  0b11..Non-secure and non-privileged Master
7390  */
7391 #define AHBSC_MASTER_SEC_ANTI_POL_REG_COOLFLUXI(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_ANTI_POL_REG_COOLFLUXI_SHIFT)) & AHBSC_MASTER_SEC_ANTI_POL_REG_COOLFLUXI_MASK)
7392 
7393 #define AHBSC_MASTER_SEC_ANTI_POL_REG_USB_FS_MASK (0xC00000U)
7394 #define AHBSC_MASTER_SEC_ANTI_POL_REG_USB_FS_SHIFT (22U)
7395 /*! USB_FS - USB_FS
7396  *  0b00..Secure and privileged Master
7397  *  0b01..Secure and non-privileged Master
7398  *  0b10..Non-secure and privileged Master
7399  *  0b11..Non-secure and non-privileged Master
7400  */
7401 #define AHBSC_MASTER_SEC_ANTI_POL_REG_USB_FS(x)  (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_ANTI_POL_REG_USB_FS_SHIFT)) & AHBSC_MASTER_SEC_ANTI_POL_REG_USB_FS_MASK)
7402 
7403 #define AHBSC_MASTER_SEC_ANTI_POL_REG_ETHERNET_MASK (0x3000000U)
7404 #define AHBSC_MASTER_SEC_ANTI_POL_REG_ETHERNET_SHIFT (24U)
7405 /*! ETHERNET - Ethernet
7406  *  0b00..Secure and privileged Master
7407  *  0b01..Secure and non-privileged Master
7408  *  0b10..Non-secure and privileged Master
7409  *  0b11..Non-secure and non-privileged Master
7410  */
7411 #define AHBSC_MASTER_SEC_ANTI_POL_REG_ETHERNET(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_ANTI_POL_REG_ETHERNET_SHIFT)) & AHBSC_MASTER_SEC_ANTI_POL_REG_ETHERNET_MASK)
7412 
7413 #define AHBSC_MASTER_SEC_ANTI_POL_REG_USB_HS_MASK (0xC000000U)
7414 #define AHBSC_MASTER_SEC_ANTI_POL_REG_USB_HS_SHIFT (26U)
7415 /*! USB_HS - USB HS
7416  *  0b00..Secure and privileged Master
7417  *  0b01..Secure and non-privileged Master
7418  *  0b10..Non-secure and privileged Master
7419  *  0b11..Non-secure and non-privileged Master
7420  */
7421 #define AHBSC_MASTER_SEC_ANTI_POL_REG_USB_HS(x)  (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_ANTI_POL_REG_USB_HS_SHIFT)) & AHBSC_MASTER_SEC_ANTI_POL_REG_USB_HS_MASK)
7422 
7423 #define AHBSC_MASTER_SEC_ANTI_POL_REG_USDHC_MASK (0x30000000U)
7424 #define AHBSC_MASTER_SEC_ANTI_POL_REG_USDHC_SHIFT (28U)
7425 /*! USDHC - uSDHC
7426  *  0b00..Secure and privileged Master
7427  *  0b01..Secure and non-privileged Master
7428  *  0b10..Non-secure and privileged Master
7429  *  0b11..Non-secure and non-privileged Master
7430  */
7431 #define AHBSC_MASTER_SEC_ANTI_POL_REG_USDHC(x)   (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_ANTI_POL_REG_USDHC_SHIFT)) & AHBSC_MASTER_SEC_ANTI_POL_REG_USDHC_MASK)
7432 
7433 #define AHBSC_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_MASK (0xC0000000U)
7434 #define AHBSC_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_SHIFT (30U)
7435 /*! MASTER_SEC_LEVEL_ANTIPOL_LOCK - Master SEC Level Antipol Lock
7436  *  0b00..Reserved
7437  *  0b01..MASTER_SEC_LEVEL_LOCK cannot be written
7438  *  0b10..MASTER_SEC_LEVEL_LOCK can be written
7439  *  0b11..Reserved
7440  */
7441 #define AHBSC_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_SHIFT)) & AHBSC_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_MASK)
7442 /*! @} */
7443 
7444 /*! @name CPU0_LOCK_REG - Miscellaneous CPU0 Control Signals */
7445 /*! @{ */
7446 
7447 #define AHBSC_CPU0_LOCK_REG_LOCK_NS_VTOR_MASK    (0x3U)
7448 #define AHBSC_CPU0_LOCK_REG_LOCK_NS_VTOR_SHIFT   (0U)
7449 /*! LOCK_NS_VTOR - LOCK_NS_VTOR
7450  *  0b00..Reserved
7451  *  0b01..CM33 (CPU0) LOCKNSVTOR is 1
7452  *  0b10..CM33 (CPU0) LOCKNSVTOR is 0
7453  *  0b11..Reserved
7454  */
7455 #define AHBSC_CPU0_LOCK_REG_LOCK_NS_VTOR(x)      (((uint32_t)(((uint32_t)(x)) << AHBSC_CPU0_LOCK_REG_LOCK_NS_VTOR_SHIFT)) & AHBSC_CPU0_LOCK_REG_LOCK_NS_VTOR_MASK)
7456 
7457 #define AHBSC_CPU0_LOCK_REG_LOCK_NS_MPU_MASK     (0xCU)
7458 #define AHBSC_CPU0_LOCK_REG_LOCK_NS_MPU_SHIFT    (2U)
7459 /*! LOCK_NS_MPU - LOCK_NS_MPU
7460  *  0b00..Reserved
7461  *  0b01..CM33 (CPU0) LOCK_NS_MPU is 1
7462  *  0b10..CM33 (CPU0) LOCK_NS_MPU is 0
7463  *  0b11..Reserved
7464  */
7465 #define AHBSC_CPU0_LOCK_REG_LOCK_NS_MPU(x)       (((uint32_t)(((uint32_t)(x)) << AHBSC_CPU0_LOCK_REG_LOCK_NS_MPU_SHIFT)) & AHBSC_CPU0_LOCK_REG_LOCK_NS_MPU_MASK)
7466 
7467 #define AHBSC_CPU0_LOCK_REG_LOCK_S_VTAIRCR_MASK  (0x30U)
7468 #define AHBSC_CPU0_LOCK_REG_LOCK_S_VTAIRCR_SHIFT (4U)
7469 /*! LOCK_S_VTAIRCR - LOCK_S_VTAIRCR
7470  *  0b00..Reserved
7471  *  0b01..CM33 (CPU0) LOCK_S_VTAIRCR is 1
7472  *  0b10..CM33 (CPU0) LOCK_S_VTAIRCR is 0
7473  *  0b11..Reserved
7474  */
7475 #define AHBSC_CPU0_LOCK_REG_LOCK_S_VTAIRCR(x)    (((uint32_t)(((uint32_t)(x)) << AHBSC_CPU0_LOCK_REG_LOCK_S_VTAIRCR_SHIFT)) & AHBSC_CPU0_LOCK_REG_LOCK_S_VTAIRCR_MASK)
7476 
7477 #define AHBSC_CPU0_LOCK_REG_LOCK_S_MPU_MASK      (0xC0U)
7478 #define AHBSC_CPU0_LOCK_REG_LOCK_S_MPU_SHIFT     (6U)
7479 /*! LOCK_S_MPU - LOCK_S_MPU
7480  *  0b00..Reserved
7481  *  0b01..CM33 (CPU0) LOCK_S_MPU is 1
7482  *  0b10..CM33 (CPU0) LOCK_S_MPU is 0
7483  *  0b11..Reserved
7484  */
7485 #define AHBSC_CPU0_LOCK_REG_LOCK_S_MPU(x)        (((uint32_t)(((uint32_t)(x)) << AHBSC_CPU0_LOCK_REG_LOCK_S_MPU_SHIFT)) & AHBSC_CPU0_LOCK_REG_LOCK_S_MPU_MASK)
7486 
7487 #define AHBSC_CPU0_LOCK_REG_LOCK_SAU_MASK        (0x300U)
7488 #define AHBSC_CPU0_LOCK_REG_LOCK_SAU_SHIFT       (8U)
7489 /*! LOCK_SAU - LOCK_SAU
7490  *  0b00..Reserved
7491  *  0b01..CM33 (CPU0) LOCK_SAU is 1
7492  *  0b10..CM33 (CPU0) LOCK_SAU is 0
7493  *  0b11..Reserved
7494  */
7495 #define AHBSC_CPU0_LOCK_REG_LOCK_SAU(x)          (((uint32_t)(((uint32_t)(x)) << AHBSC_CPU0_LOCK_REG_LOCK_SAU_SHIFT)) & AHBSC_CPU0_LOCK_REG_LOCK_SAU_MASK)
7496 
7497 #define AHBSC_CPU0_LOCK_REG_CM33_LOCK_REG_LOCK_MASK (0xC0000000U)
7498 #define AHBSC_CPU0_LOCK_REG_CM33_LOCK_REG_LOCK_SHIFT (30U)
7499 /*! CM33_LOCK_REG_LOCK - CM33_LOCK_REG_LOCK
7500  *  0b00..Reserved
7501  *  0b01..CM33_LOCK_REG_LOCK is 1
7502  *  0b10..CM33_LOCK_REG_LOCK is 0
7503  *  0b11..Reserved
7504  */
7505 #define AHBSC_CPU0_LOCK_REG_CM33_LOCK_REG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_CPU0_LOCK_REG_CM33_LOCK_REG_LOCK_SHIFT)) & AHBSC_CPU0_LOCK_REG_CM33_LOCK_REG_LOCK_MASK)
7506 /*! @} */
7507 
7508 /*! @name CPU1_LOCK_REG - Miscellaneous CPU1 Control Signals */
7509 /*! @{ */
7510 
7511 #define AHBSC_CPU1_LOCK_REG_LOCK_NS_VTOR_MASK    (0x3U)
7512 #define AHBSC_CPU1_LOCK_REG_LOCK_NS_VTOR_SHIFT   (0U)
7513 /*! LOCK_NS_VTOR - LOCK_NS_VTOR
7514  *  0b00..Reserved
7515  *  0b01..CM33 (CPU0) LOCKNSVTOR is 1
7516  *  0b10..CM33 (CPU0) LOCKNSVTOR is 0
7517  *  0b11..Reserved
7518  */
7519 #define AHBSC_CPU1_LOCK_REG_LOCK_NS_VTOR(x)      (((uint32_t)(((uint32_t)(x)) << AHBSC_CPU1_LOCK_REG_LOCK_NS_VTOR_SHIFT)) & AHBSC_CPU1_LOCK_REG_LOCK_NS_VTOR_MASK)
7520 
7521 #define AHBSC_CPU1_LOCK_REG_LOCK_NS_MPU_MASK     (0xCU)
7522 #define AHBSC_CPU1_LOCK_REG_LOCK_NS_MPU_SHIFT    (2U)
7523 /*! LOCK_NS_MPU - LOCK_NS_MPU
7524  *  0b00..Reserved
7525  *  0b01..CM33 (CPU0) LOCK_NS_MPU is 1
7526  *  0b10..CM33 (CPU0) LOCK_NS_MPU is 0
7527  *  0b11..Reserved
7528  */
7529 #define AHBSC_CPU1_LOCK_REG_LOCK_NS_MPU(x)       (((uint32_t)(((uint32_t)(x)) << AHBSC_CPU1_LOCK_REG_LOCK_NS_MPU_SHIFT)) & AHBSC_CPU1_LOCK_REG_LOCK_NS_MPU_MASK)
7530 /*! @} */
7531 
7532 /*! @name MISC_CTRL_DP_REG - Secure Control Duplicate */
7533 /*! @{ */
7534 
7535 #define AHBSC_MISC_CTRL_DP_REG_WRITE_LOCK_MASK   (0x3U)
7536 #define AHBSC_MISC_CTRL_DP_REG_WRITE_LOCK_SHIFT  (0U)
7537 /*! WRITE_LOCK - Write Lock
7538  *  0b00..Reserved
7539  *  0b01..Writes to this register and to the Memory and Peripheral RULE registers are not allowed
7540  *  0b10..Writes to this register and to the Memory and Peripheral RULE registers are allowed
7541  *  0b11..Reserved
7542  */
7543 #define AHBSC_MISC_CTRL_DP_REG_WRITE_LOCK(x)     (((uint32_t)(((uint32_t)(x)) << AHBSC_MISC_CTRL_DP_REG_WRITE_LOCK_SHIFT)) & AHBSC_MISC_CTRL_DP_REG_WRITE_LOCK_MASK)
7544 
7545 #define AHBSC_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_MASK (0xCU)
7546 #define AHBSC_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_SHIFT (2U)
7547 /*! ENABLE_SECURE_CHECKING - Enable Secure Checking
7548  *  0b00..Reserved
7549  *  0b01..Enables secure checking. Violation can be detected when the security level of a transaction does not
7550  *        meet the security rule of the slave or memory to be accessed.
7551  *  0b10..Disables secure checking. Even if the security level of a transaction does not conform to the security
7552  *        rule of the slave or memory, it will not be detected as a violation.
7553  *  0b11..Reserved
7554  */
7555 #define AHBSC_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_SHIFT)) & AHBSC_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_MASK)
7556 
7557 #define AHBSC_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_MASK (0x30U)
7558 #define AHBSC_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_SHIFT (4U)
7559 /*! ENABLE_S_PRIV_CHECK - Enable Secure Privilege Checking
7560  *  0b00..Reserved
7561  *  0b01..Enables the privilege checking of secure mode access.
7562  *  0b10..Disables the privilege checking of secure mode access.
7563  *  0b11..Reserved
7564  */
7565 #define AHBSC_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_SHIFT)) & AHBSC_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_MASK)
7566 
7567 #define AHBSC_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_MASK (0xC0U)
7568 #define AHBSC_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_SHIFT (6U)
7569 /*! ENABLE_NS_PRIV_CHECK - Enable Non-Secure Privilege Checking
7570  *  0b00..Reserved
7571  *  0b01..Enables the privilege checking of non-secure mode access.
7572  *  0b10..Disables the privilege checking of non-secure mode access.
7573  *  0b11..Reserved
7574  */
7575 #define AHBSC_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_SHIFT)) & AHBSC_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_MASK)
7576 
7577 #define AHBSC_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_MASK (0x300U)
7578 #define AHBSC_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_SHIFT (8U)
7579 /*! DISABLE_VIOLATION_ABORT - Disable Violation Abort
7580  *  0b00..Reserved
7581  *  0b01..The violation detected by the secure checker will not cause an abort, but a secure_violation_irq
7582  *        (interrupt request) will still be asserted and serviced by ISR.
7583  *  0b10..The violation detected by the secure checker will cause an abort.
7584  *  0b11..Reserved
7585  */
7586 #define AHBSC_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_SHIFT)) & AHBSC_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_MASK)
7587 
7588 #define AHBSC_MISC_CTRL_DP_REG_DISABLE_STRICT_MODE_MASK (0xC00U)
7589 #define AHBSC_MISC_CTRL_DP_REG_DISABLE_STRICT_MODE_SHIFT (10U)
7590 /*! DISABLE_STRICT_MODE - Disable Strict Mode
7591  *  0b00..Reserved
7592  *  0b01..Master can access memories and peripherals at the same level or below that level.
7593  *  0b10..Master can access memories and peripherals at same level only
7594  *  0b11..Reserved
7595  */
7596 #define AHBSC_MISC_CTRL_DP_REG_DISABLE_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MISC_CTRL_DP_REG_DISABLE_STRICT_MODE_SHIFT)) & AHBSC_MISC_CTRL_DP_REG_DISABLE_STRICT_MODE_MASK)
7597 
7598 #define AHBSC_MISC_CTRL_DP_REG_IDAU_ALL_NS_MASK  (0xC000U)
7599 #define AHBSC_MISC_CTRL_DP_REG_IDAU_ALL_NS_SHIFT (14U)
7600 /*! IDAU_ALL_NS - IDAU All Non-Secure
7601  *  0b00..Reserved
7602  *  0b01..IDAU is disabled, which means that all memories are attributed as non-secure memory.
7603  *  0b10..IDAU is enabled (restrictive mode)
7604  *  0b11..Reserved
7605  */
7606 #define AHBSC_MISC_CTRL_DP_REG_IDAU_ALL_NS(x)    (((uint32_t)(((uint32_t)(x)) << AHBSC_MISC_CTRL_DP_REG_IDAU_ALL_NS_SHIFT)) & AHBSC_MISC_CTRL_DP_REG_IDAU_ALL_NS_MASK)
7607 /*! @} */
7608 
7609 /*! @name MISC_CTRL_REG - Secure Control */
7610 /*! @{ */
7611 
7612 #define AHBSC_MISC_CTRL_REG_WRITE_LOCK_MASK      (0x3U)
7613 #define AHBSC_MISC_CTRL_REG_WRITE_LOCK_SHIFT     (0U)
7614 /*! WRITE_LOCK - Write Lock
7615  *  0b00..Reserved
7616  *  0b01..Writes to this register and to the Memory and Peripheral RULE registers are not allowed
7617  *  0b10..Writes to this register and to the Memory and Peripheral RULE registers are allowed
7618  *  0b11..Reserved
7619  */
7620 #define AHBSC_MISC_CTRL_REG_WRITE_LOCK(x)        (((uint32_t)(((uint32_t)(x)) << AHBSC_MISC_CTRL_REG_WRITE_LOCK_SHIFT)) & AHBSC_MISC_CTRL_REG_WRITE_LOCK_MASK)
7621 
7622 #define AHBSC_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_MASK (0xCU)
7623 #define AHBSC_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_SHIFT (2U)
7624 /*! ENABLE_SECURE_CHECKING - Enable Secure Checking
7625  *  0b00..Reserved
7626  *  0b01..Enables secure checking. Violation can be detected when the security level of a transaction does not
7627  *        meet the security rule of the slave or memory to be accessed.
7628  *  0b10..Disables secure checking. Even if the security level of a transaction does not conform to the security
7629  *        rule of the slave or memory, it will not be detected as a violation.
7630  *  0b11..Reserved
7631  */
7632 #define AHBSC_MISC_CTRL_REG_ENABLE_SECURE_CHECKING(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_SHIFT)) & AHBSC_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_MASK)
7633 
7634 #define AHBSC_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_MASK (0x30U)
7635 #define AHBSC_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_SHIFT (4U)
7636 /*! ENABLE_S_PRIV_CHECK - Enable Secure Privilege Checking
7637  *  0b00..Reserved
7638  *  0b01..Enables privilege checking of secure mode access.
7639  *  0b10..Disables privilege checking of secure mode access.
7640  *  0b11..Reserved
7641  */
7642 #define AHBSC_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_SHIFT)) & AHBSC_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_MASK)
7643 
7644 #define AHBSC_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_MASK (0xC0U)
7645 #define AHBSC_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_SHIFT (6U)
7646 /*! ENABLE_NS_PRIV_CHECK - Enable Non-Secure Privilege Checking
7647  *  0b00..Reserved
7648  *  0b01..Enables privilege checking of non-secure mode access.
7649  *  0b10..Disables privilege checking of non-secure mode access is disabled.
7650  *  0b11..Reserved
7651  */
7652 #define AHBSC_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_SHIFT)) & AHBSC_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_MASK)
7653 
7654 #define AHBSC_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_MASK (0x300U)
7655 #define AHBSC_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_SHIFT (8U)
7656 /*! DISABLE_VIOLATION_ABORT - Disable Violation Abort
7657  *  0b00..Reserved
7658  *  0b01..The violation detected by the secure checker will not cause an abort, but a secure_violation_irq
7659  *        (interrupt request) will still be asserted and serviced by ISR.
7660  *  0b10..The violation detected by the secure checker will cause an abort.
7661  *  0b11..Reserved
7662  */
7663 #define AHBSC_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_SHIFT)) & AHBSC_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_MASK)
7664 
7665 #define AHBSC_MISC_CTRL_REG_DISABLE_STRICT_MODE_MASK (0xC00U)
7666 #define AHBSC_MISC_CTRL_REG_DISABLE_STRICT_MODE_SHIFT (10U)
7667 /*! DISABLE_STRICT_MODE - Disable Strict Mode
7668  *  0b00..Reserved
7669  *  0b01..Master strict mode is on and can access memories and peripherals at the same level or below that level
7670  *  0b10..Master strict mode is disabled and can access memories and peripherals at same level only
7671  *  0b11..Reserved
7672  */
7673 #define AHBSC_MISC_CTRL_REG_DISABLE_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MISC_CTRL_REG_DISABLE_STRICT_MODE_SHIFT)) & AHBSC_MISC_CTRL_REG_DISABLE_STRICT_MODE_MASK)
7674 
7675 #define AHBSC_MISC_CTRL_REG_IDAU_ALL_NS_MASK     (0xC000U)
7676 #define AHBSC_MISC_CTRL_REG_IDAU_ALL_NS_SHIFT    (14U)
7677 /*! IDAU_ALL_NS - IDAU All Non-Secure
7678  *  0b00..Reserved
7679  *  0b01..IDAU is disabled, which means that all memories are attributed as non-secure memory.
7680  *  0b10..IDAU is enabled (restrictive mode)
7681  *  0b11..Reserved
7682  */
7683 #define AHBSC_MISC_CTRL_REG_IDAU_ALL_NS(x)       (((uint32_t)(((uint32_t)(x)) << AHBSC_MISC_CTRL_REG_IDAU_ALL_NS_SHIFT)) & AHBSC_MISC_CTRL_REG_IDAU_ALL_NS_MASK)
7684 /*! @} */
7685 
7686 
7687 /*!
7688  * @}
7689  */ /* end of group AHBSC_Register_Masks */
7690 
7691 
7692 /* AHBSC - Peripheral instance base addresses */
7693 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
7694   /** Peripheral AHBSC base address */
7695   #define AHBSC_BASE                               (0x50120000u)
7696   /** Peripheral AHBSC base address */
7697   #define AHBSC_BASE_NS                            (0x40120000u)
7698   /** Peripheral AHBSC base pointer */
7699   #define AHBSC                                    ((AHBSC_Type *)AHBSC_BASE)
7700   /** Peripheral AHBSC base pointer */
7701   #define AHBSC_NS                                 ((AHBSC_Type *)AHBSC_BASE_NS)
7702   /** Peripheral AHBSC_ALIAS1 base address */
7703   #define AHBSC_ALIAS1_BASE                        (0x50121000u)
7704   /** Peripheral AHBSC_ALIAS1 base address */
7705   #define AHBSC_ALIAS1_BASE_NS                     (0x40121000u)
7706   /** Peripheral AHBSC_ALIAS1 base pointer */
7707   #define AHBSC_ALIAS1                             ((AHBSC_Type *)AHBSC_ALIAS1_BASE)
7708   /** Peripheral AHBSC_ALIAS1 base pointer */
7709   #define AHBSC_ALIAS1_NS                          ((AHBSC_Type *)AHBSC_ALIAS1_BASE_NS)
7710   /** Peripheral AHBSC_ALIAS2 base address */
7711   #define AHBSC_ALIAS2_BASE                        (0x50122000u)
7712   /** Peripheral AHBSC_ALIAS2 base address */
7713   #define AHBSC_ALIAS2_BASE_NS                     (0x40122000u)
7714   /** Peripheral AHBSC_ALIAS2 base pointer */
7715   #define AHBSC_ALIAS2                             ((AHBSC_Type *)AHBSC_ALIAS2_BASE)
7716   /** Peripheral AHBSC_ALIAS2 base pointer */
7717   #define AHBSC_ALIAS2_NS                          ((AHBSC_Type *)AHBSC_ALIAS2_BASE_NS)
7718   /** Peripheral AHBSC_ALIAS3 base address */
7719   #define AHBSC_ALIAS3_BASE                        (0x50123000u)
7720   /** Peripheral AHBSC_ALIAS3 base address */
7721   #define AHBSC_ALIAS3_BASE_NS                     (0x40123000u)
7722   /** Peripheral AHBSC_ALIAS3 base pointer */
7723   #define AHBSC_ALIAS3                             ((AHBSC_Type *)AHBSC_ALIAS3_BASE)
7724   /** Peripheral AHBSC_ALIAS3 base pointer */
7725   #define AHBSC_ALIAS3_NS                          ((AHBSC_Type *)AHBSC_ALIAS3_BASE_NS)
7726   /** Array initializer of AHBSC peripheral base addresses */
7727   #define AHBSC_BASE_ADDRS                         { AHBSC_BASE, AHBSC_ALIAS1_BASE, AHBSC_ALIAS2_BASE, AHBSC_ALIAS3_BASE }
7728   /** Array initializer of AHBSC peripheral base pointers */
7729   #define AHBSC_BASE_PTRS                          { AHBSC, AHBSC_ALIAS1, AHBSC_ALIAS2, AHBSC_ALIAS3 }
7730   /** Array initializer of AHBSC peripheral base addresses */
7731   #define AHBSC_BASE_ADDRS_NS                      { AHBSC_BASE_NS, AHBSC_ALIAS1_BASE_NS, AHBSC_ALIAS2_BASE_NS, AHBSC_ALIAS3_BASE_NS }
7732   /** Array initializer of AHBSC peripheral base pointers */
7733   #define AHBSC_BASE_PTRS_NS                       { AHBSC_NS, AHBSC_ALIAS1_NS, AHBSC_ALIAS2_NS, AHBSC_ALIAS3_NS }
7734 #else
7735   /** Peripheral AHBSC base address */
7736   #define AHBSC_BASE                               (0x40120000u)
7737   /** Peripheral AHBSC base pointer */
7738   #define AHBSC                                    ((AHBSC_Type *)AHBSC_BASE)
7739   /** Peripheral AHBSC_ALIAS1 base address */
7740   #define AHBSC_ALIAS1_BASE                        (0x40121000u)
7741   /** Peripheral AHBSC_ALIAS1 base pointer */
7742   #define AHBSC_ALIAS1                             ((AHBSC_Type *)AHBSC_ALIAS1_BASE)
7743   /** Peripheral AHBSC_ALIAS2 base address */
7744   #define AHBSC_ALIAS2_BASE                        (0x40122000u)
7745   /** Peripheral AHBSC_ALIAS2 base pointer */
7746   #define AHBSC_ALIAS2                             ((AHBSC_Type *)AHBSC_ALIAS2_BASE)
7747   /** Peripheral AHBSC_ALIAS3 base address */
7748   #define AHBSC_ALIAS3_BASE                        (0x40123000u)
7749   /** Peripheral AHBSC_ALIAS3 base pointer */
7750   #define AHBSC_ALIAS3                             ((AHBSC_Type *)AHBSC_ALIAS3_BASE)
7751   /** Array initializer of AHBSC peripheral base addresses */
7752   #define AHBSC_BASE_ADDRS                         { AHBSC_BASE, AHBSC_ALIAS1_BASE, AHBSC_ALIAS2_BASE, AHBSC_ALIAS3_BASE }
7753   /** Array initializer of AHBSC peripheral base pointers */
7754   #define AHBSC_BASE_PTRS                          { AHBSC, AHBSC_ALIAS1, AHBSC_ALIAS2, AHBSC_ALIAS3 }
7755 #endif
7756 
7757 /*!
7758  * @}
7759  */ /* end of group AHBSC_Peripheral_Access_Layer */
7760 
7761 
7762 /* ----------------------------------------------------------------------------
7763    -- BSP32 Peripheral Access Layer
7764    ---------------------------------------------------------------------------- */
7765 
7766 /*!
7767  * @addtogroup BSP32_Peripheral_Access_Layer BSP32 Peripheral Access Layer
7768  * @{
7769  */
7770 
7771 /** BSP32 - Register Layout Typedef */
7772 typedef struct {
7773   __IO uint32_t OFFSET_PMEM;                       /**< Offset address register for program memory, offset: 0x0 */
7774   __IO uint32_t OFFSET_XMEM;                       /**< Offset address register for X-data memory, offset: 0x4 */
7775   __IO uint32_t OFFSET_YMEM;                       /**< Offset address register for Y-data memory, offset: 0x8 */
7776   __IO uint32_t OFFSET_MAILBOX;                    /**< Offset address register for mailbox peripheral, offset: 0xC */
7777   __O  uint32_t INTERRUPTS_EXTERNAL;               /**< External interrupt register, offset: 0x10 */
7778   __IO uint32_t INTERRUPTS_STATUS;                 /**< Interrupt status register, offset: 0x14 */
7779   __IO uint32_t CF_GATING_OVERRIDE;                /**< CoolFlux BSP32 gating override, offset: 0x18 */
7780   __IO uint32_t IVT_OFFSET;                        /**< CoolFlux BSP32 IVT offset register, offset: 0x1C */
7781   __I  uint32_t SLEEP_MODE;                        /**< CoolFlux BSP32 sleep mode register, offset: 0x20 */
7782   __IO uint32_t IVT0;                              /**< CoolFlux BSP32 IVT register 0 content, offset: 0x24 */
7783   __IO uint32_t IVT1;                              /**< CoolFlux BSP32 IVT register 1 content, offset: 0x28 */
7784   __IO uint32_t IVT2;                              /**< CoolFlux BSP32 IVT register 2 content, offset: 0x2C */
7785   __IO uint32_t IVT3;                              /**< CoolFlux BSP32 IVT register 3 content, offset: 0x30 */
7786   __IO uint32_t IVT_DISABLE;                       /**< CoolFlux BSP32 IVT disable register, offset: 0x34 */
7787 } BSP32_Type;
7788 
7789 /* ----------------------------------------------------------------------------
7790    -- BSP32 Register Masks
7791    ---------------------------------------------------------------------------- */
7792 
7793 /*!
7794  * @addtogroup BSP32_Register_Masks BSP32 Register Masks
7795  * @{
7796  */
7797 
7798 /*! @name OFFSET_PMEM - Offset address register for program memory */
7799 /*! @{ */
7800 
7801 #define BSP32_OFFSET_PMEM_VAL_MASK               (0x3FU)
7802 #define BSP32_OFFSET_PMEM_VAL_SHIFT              (0U)
7803 /*! val - Offset address register for program memory */
7804 #define BSP32_OFFSET_PMEM_VAL(x)                 (((uint32_t)(((uint32_t)(x)) << BSP32_OFFSET_PMEM_VAL_SHIFT)) & BSP32_OFFSET_PMEM_VAL_MASK)
7805 /*! @} */
7806 
7807 /*! @name OFFSET_XMEM - Offset address register for X-data memory */
7808 /*! @{ */
7809 
7810 #define BSP32_OFFSET_XMEM_VAL_MASK               (0xFFU)
7811 #define BSP32_OFFSET_XMEM_VAL_SHIFT              (0U)
7812 /*! val - Offset address register for X-data memory */
7813 #define BSP32_OFFSET_XMEM_VAL(x)                 (((uint32_t)(((uint32_t)(x)) << BSP32_OFFSET_XMEM_VAL_SHIFT)) & BSP32_OFFSET_XMEM_VAL_MASK)
7814 /*! @} */
7815 
7816 /*! @name OFFSET_YMEM - Offset address register for Y-data memory */
7817 /*! @{ */
7818 
7819 #define BSP32_OFFSET_YMEM_VAL_MASK               (0xFFU)
7820 #define BSP32_OFFSET_YMEM_VAL_SHIFT              (0U)
7821 /*! val - Offset address register for Y-data memory */
7822 #define BSP32_OFFSET_YMEM_VAL(x)                 (((uint32_t)(((uint32_t)(x)) << BSP32_OFFSET_YMEM_VAL_SHIFT)) & BSP32_OFFSET_YMEM_VAL_MASK)
7823 /*! @} */
7824 
7825 /*! @name OFFSET_MAILBOX - Offset address register for mailbox peripheral */
7826 /*! @{ */
7827 
7828 #define BSP32_OFFSET_MAILBOX_VAL_MASK            (0xFFFFFFU)
7829 #define BSP32_OFFSET_MAILBOX_VAL_SHIFT           (0U)
7830 /*! val - Offset address register for mailbox peripheral */
7831 #define BSP32_OFFSET_MAILBOX_VAL(x)              (((uint32_t)(((uint32_t)(x)) << BSP32_OFFSET_MAILBOX_VAL_SHIFT)) & BSP32_OFFSET_MAILBOX_VAL_MASK)
7832 /*! @} */
7833 
7834 /*! @name INTERRUPTS_EXTERNAL - External interrupt register */
7835 /*! @{ */
7836 
7837 #define BSP32_INTERRUPTS_EXTERNAL_VAL_MASK       (0xFFFFFFFFU)
7838 #define BSP32_INTERRUPTS_EXTERNAL_VAL_SHIFT      (0U)
7839 /*! val - External interrupt register */
7840 #define BSP32_INTERRUPTS_EXTERNAL_VAL(x)         (((uint32_t)(((uint32_t)(x)) << BSP32_INTERRUPTS_EXTERNAL_VAL_SHIFT)) & BSP32_INTERRUPTS_EXTERNAL_VAL_MASK)
7841 /*! @} */
7842 
7843 /*! @name INTERRUPTS_STATUS - Interrupt status register */
7844 /*! @{ */
7845 
7846 #define BSP32_INTERRUPTS_STATUS_VAL_MASK         (0x1U)
7847 #define BSP32_INTERRUPTS_STATUS_VAL_SHIFT        (0U)
7848 /*! val - Interrupt status register */
7849 #define BSP32_INTERRUPTS_STATUS_VAL(x)           (((uint32_t)(((uint32_t)(x)) << BSP32_INTERRUPTS_STATUS_VAL_SHIFT)) & BSP32_INTERRUPTS_STATUS_VAL_MASK)
7850 /*! @} */
7851 
7852 /*! @name CF_GATING_OVERRIDE - CoolFlux BSP32 gating override */
7853 /*! @{ */
7854 
7855 #define BSP32_CF_GATING_OVERRIDE_VAL_MASK        (0x1U)
7856 #define BSP32_CF_GATING_OVERRIDE_VAL_SHIFT       (0U)
7857 /*! val - CoolFlux BSP32 gating override */
7858 #define BSP32_CF_GATING_OVERRIDE_VAL(x)          (((uint32_t)(((uint32_t)(x)) << BSP32_CF_GATING_OVERRIDE_VAL_SHIFT)) & BSP32_CF_GATING_OVERRIDE_VAL_MASK)
7859 /*! @} */
7860 
7861 /*! @name IVT_OFFSET - CoolFlux BSP32 IVT offset register */
7862 /*! @{ */
7863 
7864 #define BSP32_IVT_OFFSET_VAL_MASK                (0xFFFFFFU)
7865 #define BSP32_IVT_OFFSET_VAL_SHIFT               (0U)
7866 /*! val - CoolFlux BSP32 IVT offset register */
7867 #define BSP32_IVT_OFFSET_VAL(x)                  (((uint32_t)(((uint32_t)(x)) << BSP32_IVT_OFFSET_VAL_SHIFT)) & BSP32_IVT_OFFSET_VAL_MASK)
7868 /*! @} */
7869 
7870 /*! @name SLEEP_MODE - CoolFlux BSP32 sleep mode register */
7871 /*! @{ */
7872 
7873 #define BSP32_SLEEP_MODE_VAL_MASK                (0x1U)
7874 #define BSP32_SLEEP_MODE_VAL_SHIFT               (0U)
7875 /*! val - CoolFlux BSP32 sleep mode register */
7876 #define BSP32_SLEEP_MODE_VAL(x)                  (((uint32_t)(((uint32_t)(x)) << BSP32_SLEEP_MODE_VAL_SHIFT)) & BSP32_SLEEP_MODE_VAL_MASK)
7877 /*! @} */
7878 
7879 /*! @name IVT0 - CoolFlux BSP32 IVT register 0 content */
7880 /*! @{ */
7881 
7882 #define BSP32_IVT0_VAL_MASK                      (0xFFFFFFU)
7883 #define BSP32_IVT0_VAL_SHIFT                     (0U)
7884 /*! val - CoolFlux BSP32 IVT register 0 content */
7885 #define BSP32_IVT0_VAL(x)                        (((uint32_t)(((uint32_t)(x)) << BSP32_IVT0_VAL_SHIFT)) & BSP32_IVT0_VAL_MASK)
7886 /*! @} */
7887 
7888 /*! @name IVT1 - CoolFlux BSP32 IVT register 1 content */
7889 /*! @{ */
7890 
7891 #define BSP32_IVT1_VAL_MASK                      (0xFFFFFFU)
7892 #define BSP32_IVT1_VAL_SHIFT                     (0U)
7893 /*! val - CoolFlux BSP32 IVT register 1 content */
7894 #define BSP32_IVT1_VAL(x)                        (((uint32_t)(((uint32_t)(x)) << BSP32_IVT1_VAL_SHIFT)) & BSP32_IVT1_VAL_MASK)
7895 /*! @} */
7896 
7897 /*! @name IVT2 - CoolFlux BSP32 IVT register 2 content */
7898 /*! @{ */
7899 
7900 #define BSP32_IVT2_VAL_MASK                      (0xFFFFFFU)
7901 #define BSP32_IVT2_VAL_SHIFT                     (0U)
7902 /*! val - CoolFlux BSP32 IVT register 2 content */
7903 #define BSP32_IVT2_VAL(x)                        (((uint32_t)(((uint32_t)(x)) << BSP32_IVT2_VAL_SHIFT)) & BSP32_IVT2_VAL_MASK)
7904 /*! @} */
7905 
7906 /*! @name IVT3 - CoolFlux BSP32 IVT register 3 content */
7907 /*! @{ */
7908 
7909 #define BSP32_IVT3_VAL_MASK                      (0xFFFFFFU)
7910 #define BSP32_IVT3_VAL_SHIFT                     (0U)
7911 /*! val - CoolFlux BSP32 IVT register 3 content */
7912 #define BSP32_IVT3_VAL(x)                        (((uint32_t)(((uint32_t)(x)) << BSP32_IVT3_VAL_SHIFT)) & BSP32_IVT3_VAL_MASK)
7913 /*! @} */
7914 
7915 /*! @name IVT_DISABLE - CoolFlux BSP32 IVT disable register */
7916 /*! @{ */
7917 
7918 #define BSP32_IVT_DISABLE_VAL_MASK               (0x1U)
7919 #define BSP32_IVT_DISABLE_VAL_SHIFT              (0U)
7920 /*! val - CoolFlux BSP32 IVT disable register */
7921 #define BSP32_IVT_DISABLE_VAL(x)                 (((uint32_t)(((uint32_t)(x)) << BSP32_IVT_DISABLE_VAL_SHIFT)) & BSP32_IVT_DISABLE_VAL_MASK)
7922 /*! @} */
7923 
7924 
7925 /*!
7926  * @}
7927  */ /* end of group BSP32_Register_Masks */
7928 
7929 
7930 /* BSP32 - Peripheral instance base addresses */
7931 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
7932   /** Peripheral BSP32_0 base address */
7933   #define BSP32_0_BASE                             (0x50032000u)
7934   /** Peripheral BSP32_0 base address */
7935   #define BSP32_0_BASE_NS                          (0x40032000u)
7936   /** Peripheral BSP32_0 base pointer */
7937   #define BSP32_0                                  ((BSP32_Type *)BSP32_0_BASE)
7938   /** Peripheral BSP32_0 base pointer */
7939   #define BSP32_0_NS                               ((BSP32_Type *)BSP32_0_BASE_NS)
7940   /** Array initializer of BSP32 peripheral base addresses */
7941   #define BSP32_BASE_ADDRS                         { BSP32_0_BASE }
7942   /** Array initializer of BSP32 peripheral base pointers */
7943   #define BSP32_BASE_PTRS                          { BSP32_0 }
7944   /** Array initializer of BSP32 peripheral base addresses */
7945   #define BSP32_BASE_ADDRS_NS                      { BSP32_0_BASE_NS }
7946   /** Array initializer of BSP32 peripheral base pointers */
7947   #define BSP32_BASE_PTRS_NS                       { BSP32_0_NS }
7948 #else
7949   /** Peripheral BSP32_0 base address */
7950   #define BSP32_0_BASE                             (0x40032000u)
7951   /** Peripheral BSP32_0 base pointer */
7952   #define BSP32_0                                  ((BSP32_Type *)BSP32_0_BASE)
7953   /** Array initializer of BSP32 peripheral base addresses */
7954   #define BSP32_BASE_ADDRS                         { BSP32_0_BASE }
7955   /** Array initializer of BSP32 peripheral base pointers */
7956   #define BSP32_BASE_PTRS                          { BSP32_0 }
7957 #endif
7958 
7959 /*!
7960  * @}
7961  */ /* end of group BSP32_Peripheral_Access_Layer */
7962 
7963 
7964 /* ----------------------------------------------------------------------------
7965    -- CACHE64_CTRL Peripheral Access Layer
7966    ---------------------------------------------------------------------------- */
7967 
7968 /*!
7969  * @addtogroup CACHE64_CTRL_Peripheral_Access_Layer CACHE64_CTRL Peripheral Access Layer
7970  * @{
7971  */
7972 
7973 /** CACHE64_CTRL - Register Layout Typedef */
7974 typedef struct {
7975        uint8_t RESERVED_0[2048];
7976   __IO uint32_t CCR;                               /**< Cache Control, offset: 0x800 */
7977   __IO uint32_t CLCR;                              /**< Cache Line Control, offset: 0x804 */
7978   __IO uint32_t CSAR;                              /**< Cache Search Address, offset: 0x808 */
7979   __IO uint32_t CCVR;                              /**< Cache Read/Write Value, offset: 0x80C */
7980 } CACHE64_CTRL_Type;
7981 
7982 /* ----------------------------------------------------------------------------
7983    -- CACHE64_CTRL Register Masks
7984    ---------------------------------------------------------------------------- */
7985 
7986 /*!
7987  * @addtogroup CACHE64_CTRL_Register_Masks CACHE64_CTRL Register Masks
7988  * @{
7989  */
7990 
7991 /*! @name CCR - Cache Control */
7992 /*! @{ */
7993 
7994 #define CACHE64_CTRL_CCR_ENCACHE_MASK            (0x1U)
7995 #define CACHE64_CTRL_CCR_ENCACHE_SHIFT           (0U)
7996 /*! ENCACHE - Cache Enable
7997  *  0b0..Disables
7998  *  0b1..Enables
7999  */
8000 #define CACHE64_CTRL_CCR_ENCACHE(x)              (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_ENCACHE_SHIFT)) & CACHE64_CTRL_CCR_ENCACHE_MASK)
8001 
8002 #define CACHE64_CTRL_CCR_ENWRBUF_MASK            (0x2U)
8003 #define CACHE64_CTRL_CCR_ENWRBUF_SHIFT           (1U)
8004 /*! ENWRBUF - Enable Write Buffer
8005  *  0b0..Disables
8006  *  0b1..Enables
8007  */
8008 #define CACHE64_CTRL_CCR_ENWRBUF(x)              (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_ENWRBUF_SHIFT)) & CACHE64_CTRL_CCR_ENWRBUF_MASK)
8009 
8010 #define CACHE64_CTRL_CCR_FRCWT_MASK              (0x4U)
8011 #define CACHE64_CTRL_CCR_FRCWT_SHIFT             (2U)
8012 /*! FRCWT - Force Write Through Mode
8013  *  0b0..Does not force
8014  *  0b1..Force
8015  */
8016 #define CACHE64_CTRL_CCR_FRCWT(x)                (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_FRCWT_SHIFT)) & CACHE64_CTRL_CCR_FRCWT_MASK)
8017 
8018 #define CACHE64_CTRL_CCR_FRCNOALLC_MASK          (0x8U)
8019 #define CACHE64_CTRL_CCR_FRCNOALLC_SHIFT         (3U)
8020 /*! FRCNOALLC - Forces No Allocation On Cache Misses
8021  *  0b0..Allocation on cache misses
8022  *  0b1..Forces no allocation on cache misses (FRCWT must be asserted)
8023  */
8024 #define CACHE64_CTRL_CCR_FRCNOALLC(x)            (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_FRCNOALLC_SHIFT)) & CACHE64_CTRL_CCR_FRCNOALLC_MASK)
8025 
8026 #define CACHE64_CTRL_CCR_INVW0_MASK              (0x1000000U)
8027 #define CACHE64_CTRL_CCR_INVW0_SHIFT             (24U)
8028 /*! INVW0 - Invalidate Way 0
8029  *  0b0..No operation
8030  *  0b1..Invalidates all lines in way 0
8031  */
8032 #define CACHE64_CTRL_CCR_INVW0(x)                (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_INVW0_SHIFT)) & CACHE64_CTRL_CCR_INVW0_MASK)
8033 
8034 #define CACHE64_CTRL_CCR_PUSHW0_MASK             (0x2000000U)
8035 #define CACHE64_CTRL_CCR_PUSHW0_SHIFT            (25U)
8036 /*! PUSHW0 - Push Way 0
8037  *  0b0..No operation
8038  *  0b1..Push all modified lines in way 0
8039  */
8040 #define CACHE64_CTRL_CCR_PUSHW0(x)               (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_PUSHW0_SHIFT)) & CACHE64_CTRL_CCR_PUSHW0_MASK)
8041 
8042 #define CACHE64_CTRL_CCR_INVW1_MASK              (0x4000000U)
8043 #define CACHE64_CTRL_CCR_INVW1_SHIFT             (26U)
8044 /*! INVW1 - Invalidate Way 1
8045  *  0b0..No operation
8046  *  0b1..Invalidates all lines in way 1
8047  */
8048 #define CACHE64_CTRL_CCR_INVW1(x)                (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_INVW1_SHIFT)) & CACHE64_CTRL_CCR_INVW1_MASK)
8049 
8050 #define CACHE64_CTRL_CCR_PUSHW1_MASK             (0x8000000U)
8051 #define CACHE64_CTRL_CCR_PUSHW1_SHIFT            (27U)
8052 /*! PUSHW1 - Push Way 1
8053  *  0b0..No operation
8054  *  0b1..Push all modified lines in way 1
8055  */
8056 #define CACHE64_CTRL_CCR_PUSHW1(x)               (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_PUSHW1_SHIFT)) & CACHE64_CTRL_CCR_PUSHW1_MASK)
8057 
8058 #define CACHE64_CTRL_CCR_GO_MASK                 (0x80000000U)
8059 #define CACHE64_CTRL_CCR_GO_SHIFT                (31U)
8060 /*! GO - Initiate Cache Command
8061  *  0b0..Write: no effect; Read: no cache command active
8062  *  0b1..Write: initiates cache command; Read: cache command active
8063  */
8064 #define CACHE64_CTRL_CCR_GO(x)                   (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_GO_SHIFT)) & CACHE64_CTRL_CCR_GO_MASK)
8065 /*! @} */
8066 
8067 /*! @name CLCR - Cache Line Control */
8068 /*! @{ */
8069 
8070 #define CACHE64_CTRL_CLCR_LGO_MASK               (0x1U)
8071 #define CACHE64_CTRL_CLCR_LGO_SHIFT              (0U)
8072 /*! LGO - Initiate Cache Line Command
8073  *  0b0..Write: no effect; Read: no line command active
8074  *  0b1..Write: initiate line command; Read: line command active
8075  */
8076 #define CACHE64_CTRL_CLCR_LGO(x)                 (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LGO_SHIFT)) & CACHE64_CTRL_CLCR_LGO_MASK)
8077 
8078 #define CACHE64_CTRL_CLCR_CACHEADDR_MASK         (0x1FFCU)
8079 #define CACHE64_CTRL_CLCR_CACHEADDR_SHIFT        (2U)
8080 /*! CACHEADDR - Cache Address */
8081 #define CACHE64_CTRL_CLCR_CACHEADDR(x)           (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_CACHEADDR_SHIFT)) & CACHE64_CTRL_CLCR_CACHEADDR_MASK)
8082 
8083 #define CACHE64_CTRL_CLCR_WSEL_MASK              (0x4000U)
8084 #define CACHE64_CTRL_CLCR_WSEL_SHIFT             (14U)
8085 /*! WSEL - Way Select
8086  *  0b0..Way 0
8087  *  0b1..Way 1
8088  */
8089 #define CACHE64_CTRL_CLCR_WSEL(x)                (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_WSEL_SHIFT)) & CACHE64_CTRL_CLCR_WSEL_MASK)
8090 
8091 #define CACHE64_CTRL_CLCR_TDSEL_MASK             (0x10000U)
8092 #define CACHE64_CTRL_CLCR_TDSEL_SHIFT            (16U)
8093 /*! TDSEL - Tag Or Data Select
8094  *  0b0..Data
8095  *  0b1..Tag
8096  */
8097 #define CACHE64_CTRL_CLCR_TDSEL(x)               (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_TDSEL_SHIFT)) & CACHE64_CTRL_CLCR_TDSEL_MASK)
8098 
8099 #define CACHE64_CTRL_CLCR_LCIVB_MASK             (0x100000U)
8100 #define CACHE64_CTRL_CLCR_LCIVB_SHIFT            (20U)
8101 /*! LCIVB - Line Command Initial Valid Bit
8102  *  0b0..Initial state 0
8103  *  0b1..Initial state 1
8104  */
8105 #define CACHE64_CTRL_CLCR_LCIVB(x)               (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LCIVB_SHIFT)) & CACHE64_CTRL_CLCR_LCIVB_MASK)
8106 
8107 #define CACHE64_CTRL_CLCR_LCIMB_MASK             (0x200000U)
8108 #define CACHE64_CTRL_CLCR_LCIMB_SHIFT            (21U)
8109 /*! LCIMB - Line Command Initial Modified Bit
8110  *  0b0..Initial state 0
8111  *  0b1..Initial state 1
8112  */
8113 #define CACHE64_CTRL_CLCR_LCIMB(x)               (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LCIMB_SHIFT)) & CACHE64_CTRL_CLCR_LCIMB_MASK)
8114 
8115 #define CACHE64_CTRL_CLCR_LCWAY_MASK             (0x400000U)
8116 #define CACHE64_CTRL_CLCR_LCWAY_SHIFT            (22U)
8117 /*! LCWAY - Line Command Way
8118  *  0b0..Way 0
8119  *  0b1..Way 1
8120  */
8121 #define CACHE64_CTRL_CLCR_LCWAY(x)               (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LCWAY_SHIFT)) & CACHE64_CTRL_CLCR_LCWAY_MASK)
8122 
8123 #define CACHE64_CTRL_CLCR_LCMD_MASK              (0x3000000U)
8124 #define CACHE64_CTRL_CLCR_LCMD_SHIFT             (24U)
8125 /*! LCMD - Line Command
8126  *  0b00..Search and read or write
8127  *  0b01..Invalidate
8128  *  0b10..Push
8129  *  0b11..Clear
8130  */
8131 #define CACHE64_CTRL_CLCR_LCMD(x)                (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LCMD_SHIFT)) & CACHE64_CTRL_CLCR_LCMD_MASK)
8132 
8133 #define CACHE64_CTRL_CLCR_LADSEL_MASK            (0x4000000U)
8134 #define CACHE64_CTRL_CLCR_LADSEL_SHIFT           (26U)
8135 /*! LADSEL - Line Address Select
8136  *  0b0..Cache
8137  *  0b1..Physical
8138  */
8139 #define CACHE64_CTRL_CLCR_LADSEL(x)              (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LADSEL_SHIFT)) & CACHE64_CTRL_CLCR_LADSEL_MASK)
8140 
8141 #define CACHE64_CTRL_CLCR_LACC_MASK              (0x8000000U)
8142 #define CACHE64_CTRL_CLCR_LACC_SHIFT             (27U)
8143 /*! LACC - Line Access Type
8144  *  0b0..Read
8145  *  0b1..Write
8146  */
8147 #define CACHE64_CTRL_CLCR_LACC(x)                (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LACC_SHIFT)) & CACHE64_CTRL_CLCR_LACC_MASK)
8148 /*! @} */
8149 
8150 /*! @name CSAR - Cache Search Address */
8151 /*! @{ */
8152 
8153 #define CACHE64_CTRL_CSAR_LGO_MASK               (0x1U)
8154 #define CACHE64_CTRL_CSAR_LGO_SHIFT              (0U)
8155 /*! LGO - Initiate Cache Line Command
8156  *  0b0..Write: no effect; Read: no line command active
8157  *  0b1..Write: initiate line command; Read: line command active
8158  */
8159 #define CACHE64_CTRL_CSAR_LGO(x)                 (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CSAR_LGO_SHIFT)) & CACHE64_CTRL_CSAR_LGO_MASK)
8160 
8161 #define CACHE64_CTRL_CSAR_PHYADDR_MASK           (0xFFFFFFFEU)
8162 #define CACHE64_CTRL_CSAR_PHYADDR_SHIFT          (1U)
8163 /*! PHYADDR - Physical Address */
8164 #define CACHE64_CTRL_CSAR_PHYADDR(x)             (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CSAR_PHYADDR_SHIFT)) & CACHE64_CTRL_CSAR_PHYADDR_MASK)
8165 /*! @} */
8166 
8167 /*! @name CCVR - Cache Read/Write Value */
8168 /*! @{ */
8169 
8170 #define CACHE64_CTRL_CCVR_DATA_MASK              (0xFFFFFFFFU)
8171 #define CACHE64_CTRL_CCVR_DATA_SHIFT             (0U)
8172 /*! DATA - Cache Read/Write Data */
8173 #define CACHE64_CTRL_CCVR_DATA(x)                (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCVR_DATA_SHIFT)) & CACHE64_CTRL_CCVR_DATA_MASK)
8174 /*! @} */
8175 
8176 
8177 /*!
8178  * @}
8179  */ /* end of group CACHE64_CTRL_Register_Masks */
8180 
8181 
8182 /* CACHE64_CTRL - Peripheral instance base addresses */
8183 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
8184   /** Peripheral CACHE64_CTRL0 base address */
8185   #define CACHE64_CTRL0_BASE                       (0x5001B000u)
8186   /** Peripheral CACHE64_CTRL0 base address */
8187   #define CACHE64_CTRL0_BASE_NS                    (0x4001B000u)
8188   /** Peripheral CACHE64_CTRL0 base pointer */
8189   #define CACHE64_CTRL0                            ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE)
8190   /** Peripheral CACHE64_CTRL0 base pointer */
8191   #define CACHE64_CTRL0_NS                         ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE_NS)
8192   /** Array initializer of CACHE64_CTRL peripheral base addresses */
8193   #define CACHE64_CTRL_BASE_ADDRS                  { CACHE64_CTRL0_BASE }
8194   /** Array initializer of CACHE64_CTRL peripheral base pointers */
8195   #define CACHE64_CTRL_BASE_PTRS                   { CACHE64_CTRL0 }
8196   /** Array initializer of CACHE64_CTRL peripheral base addresses */
8197   #define CACHE64_CTRL_BASE_ADDRS_NS               { CACHE64_CTRL0_BASE_NS }
8198   /** Array initializer of CACHE64_CTRL peripheral base pointers */
8199   #define CACHE64_CTRL_BASE_PTRS_NS                { CACHE64_CTRL0_NS }
8200 #else
8201   /** Peripheral CACHE64_CTRL0 base address */
8202   #define CACHE64_CTRL0_BASE                       (0x4001B000u)
8203   /** Peripheral CACHE64_CTRL0 base pointer */
8204   #define CACHE64_CTRL0                            ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE)
8205   /** Array initializer of CACHE64_CTRL peripheral base addresses */
8206   #define CACHE64_CTRL_BASE_ADDRS                  { CACHE64_CTRL0_BASE }
8207   /** Array initializer of CACHE64_CTRL peripheral base pointers */
8208   #define CACHE64_CTRL_BASE_PTRS                   { CACHE64_CTRL0 }
8209 #endif
8210 /** CACHE64_CTRL physical memory base alias count */
8211  #define CACHE64_CTRL_PHYMEM_BASE_ALIAS_COUNT     (3)
8212 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
8213 /** CACHE64_CTRL physical memory base address */
8214  #define CACHE64_CTRL_PHYMEM_BASES                { {0x18000000u, 0x90000000u, 0xB0000000u} }
8215 /** CACHE64_CTRL physical memory size */
8216  #define CACHE64_CTRL_PHYMEM_SIZES                { {0x08000000u, 0x10000000u, 0x10000000u} }
8217 /** CACHE64_CTRL physical memory base address */
8218  #define CACHE64_CTRL_PHYMEM_BASES_NS             { {0x08000000u, 0x80000000u, 0xA0000000u} }
8219 /** CACHE64_CTRL physical memory size */
8220  #define CACHE64_CTRL_PHYMEM_SIZES_NS             { {0x08000000u, 0x10000000u, 0x10000000u} }
8221 #else
8222 /** CACHE64_CTRL physical memory base address */
8223  #define CACHE64_CTRL_PHYMEM_BASES                { {0x08000000u, 0x80000000u, 0xA0000000u} }
8224 /** CACHE64_CTRL physical memory size */
8225  #define CACHE64_CTRL_PHYMEM_SIZES                { {0x08000000u, 0x10000000u, 0x10000000u} }
8226 #endif
8227 /* Backward compatibility */
8228 
8229 
8230 /*!
8231  * @}
8232  */ /* end of group CACHE64_CTRL_Peripheral_Access_Layer */
8233 
8234 
8235 /* ----------------------------------------------------------------------------
8236    -- CACHE64_POLSEL Peripheral Access Layer
8237    ---------------------------------------------------------------------------- */
8238 
8239 /*!
8240  * @addtogroup CACHE64_POLSEL_Peripheral_Access_Layer CACHE64_POLSEL Peripheral Access Layer
8241  * @{
8242  */
8243 
8244 /** CACHE64_POLSEL - Register Layout Typedef */
8245 typedef struct {
8246        uint8_t RESERVED_0[20];
8247   __IO uint32_t REG0_TOP;                          /**< Region 0 Top Boundary, offset: 0x14 */
8248   __IO uint32_t REG1_TOP;                          /**< Region 1 Top Boundary, offset: 0x18 */
8249   __IO uint32_t POLSEL;                            /**< Policy Select, offset: 0x1C */
8250 } CACHE64_POLSEL_Type;
8251 
8252 /* ----------------------------------------------------------------------------
8253    -- CACHE64_POLSEL Register Masks
8254    ---------------------------------------------------------------------------- */
8255 
8256 /*!
8257  * @addtogroup CACHE64_POLSEL_Register_Masks CACHE64_POLSEL Register Masks
8258  * @{
8259  */
8260 
8261 /*! @name REG0_TOP - Region 0 Top Boundary */
8262 /*! @{ */
8263 
8264 #define CACHE64_POLSEL_REG0_TOP_REG0_TOP_MASK    (0x1FFFFC00U)
8265 #define CACHE64_POLSEL_REG0_TOP_REG0_TOP_SHIFT   (10U)
8266 /*! REG0_TOP - Upper Limit Of Region 0 */
8267 #define CACHE64_POLSEL_REG0_TOP_REG0_TOP(x)      (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_REG0_TOP_REG0_TOP_SHIFT)) & CACHE64_POLSEL_REG0_TOP_REG0_TOP_MASK)
8268 /*! @} */
8269 
8270 /*! @name REG1_TOP - Region 1 Top Boundary */
8271 /*! @{ */
8272 
8273 #define CACHE64_POLSEL_REG1_TOP_REG1_TOP_MASK    (0x1FFFFC00U)
8274 #define CACHE64_POLSEL_REG1_TOP_REG1_TOP_SHIFT   (10U)
8275 /*! REG1_TOP - Upper Limit Of Region 1 */
8276 #define CACHE64_POLSEL_REG1_TOP_REG1_TOP(x)      (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_REG1_TOP_REG1_TOP_SHIFT)) & CACHE64_POLSEL_REG1_TOP_REG1_TOP_MASK)
8277 /*! @} */
8278 
8279 /*! @name POLSEL - Policy Select */
8280 /*! @{ */
8281 
8282 #define CACHE64_POLSEL_POLSEL_REG0_POLICY_MASK   (0x3U)
8283 #define CACHE64_POLSEL_POLSEL_REG0_POLICY_SHIFT  (0U)
8284 /*! REG0_POLICY - Policy Select For Region 0
8285  *  0b00..Noncacheable
8286  *  0b01..Write-through
8287  *  0b10..Write-back
8288  *  0b11..Invalid
8289  */
8290 #define CACHE64_POLSEL_POLSEL_REG0_POLICY(x)     (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_POLSEL_REG0_POLICY_SHIFT)) & CACHE64_POLSEL_POLSEL_REG0_POLICY_MASK)
8291 
8292 #define CACHE64_POLSEL_POLSEL_REG1_POLICY_MASK   (0xCU)
8293 #define CACHE64_POLSEL_POLSEL_REG1_POLICY_SHIFT  (2U)
8294 /*! REG1_POLICY - Policy Select For Region 1
8295  *  0b00..Noncacheable
8296  *  0b01..Write-through
8297  *  0b10..Write-back
8298  *  0b11..Invalid
8299  */
8300 #define CACHE64_POLSEL_POLSEL_REG1_POLICY(x)     (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_POLSEL_REG1_POLICY_SHIFT)) & CACHE64_POLSEL_POLSEL_REG1_POLICY_MASK)
8301 
8302 #define CACHE64_POLSEL_POLSEL_REG2_POLICY_MASK   (0x30U)
8303 #define CACHE64_POLSEL_POLSEL_REG2_POLICY_SHIFT  (4U)
8304 /*! REG2_POLICY - Policy Select For Region 2
8305  *  0b00..Noncacheable
8306  *  0b01..Write-through
8307  *  0b10..Write-back
8308  *  0b11..Invalid
8309  */
8310 #define CACHE64_POLSEL_POLSEL_REG2_POLICY(x)     (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_POLSEL_REG2_POLICY_SHIFT)) & CACHE64_POLSEL_POLSEL_REG2_POLICY_MASK)
8311 /*! @} */
8312 
8313 
8314 /*!
8315  * @}
8316  */ /* end of group CACHE64_POLSEL_Register_Masks */
8317 
8318 
8319 /* CACHE64_POLSEL - Peripheral instance base addresses */
8320 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
8321   /** Peripheral CACHE64_POLSEL0 base address */
8322   #define CACHE64_POLSEL0_BASE                     (0x5001B000u)
8323   /** Peripheral CACHE64_POLSEL0 base address */
8324   #define CACHE64_POLSEL0_BASE_NS                  (0x4001B000u)
8325   /** Peripheral CACHE64_POLSEL0 base pointer */
8326   #define CACHE64_POLSEL0                          ((CACHE64_POLSEL_Type *)CACHE64_POLSEL0_BASE)
8327   /** Peripheral CACHE64_POLSEL0 base pointer */
8328   #define CACHE64_POLSEL0_NS                       ((CACHE64_POLSEL_Type *)CACHE64_POLSEL0_BASE_NS)
8329   /** Array initializer of CACHE64_POLSEL peripheral base addresses */
8330   #define CACHE64_POLSEL_BASE_ADDRS                { CACHE64_POLSEL0_BASE }
8331   /** Array initializer of CACHE64_POLSEL peripheral base pointers */
8332   #define CACHE64_POLSEL_BASE_PTRS                 { CACHE64_POLSEL0 }
8333   /** Array initializer of CACHE64_POLSEL peripheral base addresses */
8334   #define CACHE64_POLSEL_BASE_ADDRS_NS             { CACHE64_POLSEL0_BASE_NS }
8335   /** Array initializer of CACHE64_POLSEL peripheral base pointers */
8336   #define CACHE64_POLSEL_BASE_PTRS_NS              { CACHE64_POLSEL0_NS }
8337 #else
8338   /** Peripheral CACHE64_POLSEL0 base address */
8339   #define CACHE64_POLSEL0_BASE                     (0x4001B000u)
8340   /** Peripheral CACHE64_POLSEL0 base pointer */
8341   #define CACHE64_POLSEL0                          ((CACHE64_POLSEL_Type *)CACHE64_POLSEL0_BASE)
8342   /** Array initializer of CACHE64_POLSEL peripheral base addresses */
8343   #define CACHE64_POLSEL_BASE_ADDRS                { CACHE64_POLSEL0_BASE }
8344   /** Array initializer of CACHE64_POLSEL peripheral base pointers */
8345   #define CACHE64_POLSEL_BASE_PTRS                 { CACHE64_POLSEL0 }
8346 #endif
8347 
8348 /*!
8349  * @}
8350  */ /* end of group CACHE64_POLSEL_Peripheral_Access_Layer */
8351 
8352 
8353 /* ----------------------------------------------------------------------------
8354    -- CAN Peripheral Access Layer
8355    ---------------------------------------------------------------------------- */
8356 
8357 /*!
8358  * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer
8359  * @{
8360  */
8361 
8362 /** CAN - Register Layout Typedef */
8363 typedef struct {
8364   __IO uint32_t MCR;                               /**< Module Configuration, offset: 0x0 */
8365   __IO uint32_t CTRL1;                             /**< Control 1, offset: 0x4 */
8366   __IO uint32_t TIMER;                             /**< Free-Running Timer, offset: 0x8 */
8367        uint8_t RESERVED_0[4];
8368   __IO uint32_t RXMGMASK;                          /**< RX Message Buffers Global Mask, offset: 0x10 */
8369   __IO uint32_t RX14MASK;                          /**< Receive 14 Mask, offset: 0x14 */
8370   __IO uint32_t RX15MASK;                          /**< Receive 15 Mask, offset: 0x18 */
8371   __IO uint32_t ECR;                               /**< Error Counter, offset: 0x1C */
8372   __IO uint32_t ESR1;                              /**< Error and Status 1, offset: 0x20 */
8373        uint8_t RESERVED_1[4];
8374   __IO uint32_t IMASK1;                            /**< Interrupt Masks 1, offset: 0x28 */
8375        uint8_t RESERVED_2[4];
8376   __IO uint32_t IFLAG1;                            /**< Interrupt Flags 1, offset: 0x30 */
8377   __IO uint32_t CTRL2;                             /**< Control 2, offset: 0x34 */
8378   __I  uint32_t ESR2;                              /**< Error and Status 2, offset: 0x38 */
8379        uint8_t RESERVED_3[8];
8380   __I  uint32_t CRCR;                              /**< Cyclic Redundancy Check, offset: 0x44 */
8381   __IO uint32_t RXFGMASK;                          /**< Legacy RX FIFO Global Mask, offset: 0x48 */
8382   __I  uint32_t RXFIR;                             /**< Legacy RX FIFO Information, offset: 0x4C */
8383   __IO uint32_t CBT;                               /**< CAN Bit Timing, offset: 0x50 */
8384        uint8_t RESERVED_4[44];
8385   union {                                          /* offset: 0x80 */
8386     struct {                                         /* offset: 0x80, array step: 0x10 */
8387       __IO uint32_t CS;                                /**< Message Buffer 0 CS Register..Message Buffer 31 CS Register, array offset: 0x80, array step: 0x10 */
8388       __IO uint32_t ID;                                /**< Message Buffer 0 ID Register..Message Buffer 31 ID Register, array offset: 0x84, array step: 0x10 */
8389       __IO uint32_t WORD[2];                           /**< Message Buffer 0 WORD_8B Register..Message Buffer 31 WORD_8B Register, array offset: 0x88, array step: index*0x10, index2*0x4 */
8390     } MB_8B[32];
8391     struct {                                         /* offset: 0x80, array step: 0x18 */
8392       __IO uint32_t CS;                                /**< Message Buffer 0 CS Register..Message Buffer 20 CS Register, array offset: 0x80, array step: 0x18 */
8393       __IO uint32_t ID;                                /**< Message Buffer 0 ID Register..Message Buffer 20 ID Register, array offset: 0x84, array step: 0x18 */
8394       __IO uint32_t WORD[4];                           /**< Message Buffer 0 WORD_16B Register..Message Buffer 20 WORD_16B Register, array offset: 0x88, array step: index*0x18, index2*0x4 */
8395     } MB_16B[21];
8396     struct {                                         /* offset: 0x80, array step: 0x28 */
8397       __IO uint32_t CS;                                /**< Message Buffer 0 CS Register..Message Buffer 11 CS Register, array offset: 0x80, array step: 0x28 */
8398       __IO uint32_t ID;                                /**< Message Buffer 0 ID Register..Message Buffer 11 ID Register, array offset: 0x84, array step: 0x28 */
8399       __IO uint32_t WORD[8];                           /**< Message Buffer 0 WORD_32B Register..Message Buffer 11 WORD_32B Register, array offset: 0x88, array step: index*0x28, index2*0x4 */
8400     } MB_32B[12];
8401     struct {                                         /* offset: 0x80, array step: 0x48 */
8402       __IO uint32_t CS;                                /**< Message Buffer 0 CS Register..Message Buffer 6 CS Register, array offset: 0x80, array step: 0x48 */
8403       __IO uint32_t ID;                                /**< Message Buffer 0 ID Register..Message Buffer 6 ID Register, array offset: 0x84, array step: 0x48 */
8404       __IO uint32_t WORD[16];                          /**< Message Buffer 0 WORD_64B Register..Message Buffer 6 WORD_64B Register, array offset: 0x88, array step: index*0x48, index2*0x4 */
8405     } MB_64B[7];
8406     struct {                                         /* offset: 0x80, array step: 0x10 */
8407       __IO uint32_t CS;                                /**< Message Buffer 0 CS Register..Message Buffer 31 CS Register, array offset: 0x80, array step: 0x10 */
8408       __IO uint32_t ID;                                /**< Message Buffer 0 ID Register..Message Buffer 31 ID Register, array offset: 0x84, array step: 0x10 */
8409       __IO uint32_t WORD0;                             /**< Message Buffer 0 WORD0 Register..Message Buffer 31 WORD0 Register, array offset: 0x88, array step: 0x10 */
8410       __IO uint32_t WORD1;                             /**< Message Buffer 0 WORD1 Register..Message Buffer 31 WORD1 Register, array offset: 0x8C, array step: 0x10 */
8411     } MB[32];
8412   };
8413        uint8_t RESERVED_5[1536];
8414   __IO uint32_t RXIMR[32];                         /**< Receive Individual Mask, array offset: 0x880, array step: 0x4 */
8415        uint8_t RESERVED_6[512];
8416   __IO uint32_t CTRL1_PN;                          /**< Pretended Networking Control 1, offset: 0xB00 */
8417   __IO uint32_t CTRL2_PN;                          /**< Pretended Networking Control 2, offset: 0xB04 */
8418   __IO uint32_t WU_MTC;                            /**< Pretended Networking Wake-Up Match, offset: 0xB08 */
8419   __IO uint32_t FLT_ID1;                           /**< Pretended Networking ID Filter 1, offset: 0xB0C */
8420   __IO uint32_t FLT_DLC;                           /**< Pretended Networking Data Length Code (DLC) Filter, offset: 0xB10 */
8421   __IO uint32_t PL1_LO;                            /**< Pretended Networking Payload Low Filter 1, offset: 0xB14 */
8422   __IO uint32_t PL1_HI;                            /**< Pretended Networking Payload High Filter 1, offset: 0xB18 */
8423   __IO uint32_t FLT_ID2_IDMASK;                    /**< Pretended Networking ID Filter 2 or ID Mask, offset: 0xB1C */
8424   __IO uint32_t PL2_PLMASK_LO;                     /**< Pretended Networking Payload Low Filter 2 and Payload Low Mask, offset: 0xB20 */
8425   __IO uint32_t PL2_PLMASK_HI;                     /**< Pretended Networking Payload High Filter 2 and Payload High Mask, offset: 0xB24 */
8426        uint8_t RESERVED_7[24];
8427   struct {                                         /* offset: 0xB40, array step: 0x10 */
8428     __I  uint32_t CS;                                /**< Wake-Up Message Buffer, array offset: 0xB40, array step: 0x10 */
8429     __I  uint32_t ID;                                /**< Wake-Up Message Buffer for ID, array offset: 0xB44, array step: 0x10 */
8430     __I  uint32_t D03;                               /**< Wake-Up Message Buffer for Data 0-3, array offset: 0xB48, array step: 0x10 */
8431     __I  uint32_t D47;                               /**< Wake-Up Message Buffer Register Data 4-7, array offset: 0xB4C, array step: 0x10 */
8432   } WMB[4];
8433        uint8_t RESERVED_8[112];
8434   __IO uint32_t EPRS;                              /**< Enhanced CAN Bit Timing Prescalers, offset: 0xBF0 */
8435   __IO uint32_t ENCBT;                             /**< Enhanced Nominal CAN Bit Timing, offset: 0xBF4 */
8436   __IO uint32_t EDCBT;                             /**< Enhanced Data Phase CAN Bit Timing, offset: 0xBF8 */
8437   __IO uint32_t ETDC;                              /**< Enhanced Transceiver Delay Compensation, offset: 0xBFC */
8438   __IO uint32_t FDCTRL;                            /**< CAN FD Control, offset: 0xC00 */
8439   __IO uint32_t FDCBT;                             /**< CAN FD Bit Timing, offset: 0xC04 */
8440   __I  uint32_t FDCRC;                             /**< CAN FD CRC, offset: 0xC08 */
8441   __IO uint32_t ERFCR;                             /**< Enhanced RX FIFO Control, offset: 0xC0C */
8442   __IO uint32_t ERFIER;                            /**< Enhanced RX FIFO Interrupt Enable, offset: 0xC10 */
8443   __IO uint32_t ERFSR;                             /**< Enhanced RX FIFO Status, offset: 0xC14 */
8444        uint8_t RESERVED_9[9192];
8445   __IO uint32_t ERFFEL[32];                        /**< Enhanced RX FIFO Filter Element, array offset: 0x3000, array step: 0x4 */
8446 } CAN_Type;
8447 
8448 /* ----------------------------------------------------------------------------
8449    -- CAN Register Masks
8450    ---------------------------------------------------------------------------- */
8451 
8452 /*!
8453  * @addtogroup CAN_Register_Masks CAN Register Masks
8454  * @{
8455  */
8456 
8457 /*! @name MCR - Module Configuration */
8458 /*! @{ */
8459 
8460 #define CAN_MCR_MAXMB_MASK                       (0x7FU)
8461 #define CAN_MCR_MAXMB_SHIFT                      (0U)
8462 /*! MAXMB - Number of the Last Message Buffer */
8463 #define CAN_MCR_MAXMB(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK)
8464 
8465 #define CAN_MCR_IDAM_MASK                        (0x300U)
8466 #define CAN_MCR_IDAM_SHIFT                       (8U)
8467 /*! IDAM - ID Acceptance Mode
8468  *  0b00..Format A: One full ID (standard and extended) per ID filter table element.
8469  *  0b01..Format B: Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID filter table element.
8470  *  0b10..Format C: Four partial 8-bit standard IDs per ID filter table element.
8471  *  0b11..Format D: All frames rejected.
8472  */
8473 #define CAN_MCR_IDAM(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK)
8474 
8475 #define CAN_MCR_FDEN_MASK                        (0x800U)
8476 #define CAN_MCR_FDEN_SHIFT                       (11U)
8477 /*! FDEN - CAN FD Operation Enable
8478  *  0b1..Enable
8479  *  0b0..Disable
8480  */
8481 #define CAN_MCR_FDEN(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FDEN_SHIFT)) & CAN_MCR_FDEN_MASK)
8482 
8483 #define CAN_MCR_AEN_MASK                         (0x1000U)
8484 #define CAN_MCR_AEN_SHIFT                        (12U)
8485 /*! AEN - Abort Enable
8486  *  0b0..Disabled
8487  *  0b1..Enabled
8488  */
8489 #define CAN_MCR_AEN(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK)
8490 
8491 #define CAN_MCR_LPRIOEN_MASK                     (0x2000U)
8492 #define CAN_MCR_LPRIOEN_SHIFT                    (13U)
8493 /*! LPRIOEN - Local Priority Enable
8494  *  0b0..Disable
8495  *  0b1..Enable
8496  */
8497 #define CAN_MCR_LPRIOEN(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK)
8498 
8499 #define CAN_MCR_PNET_EN_MASK                     (0x4000U)
8500 #define CAN_MCR_PNET_EN_SHIFT                    (14U)
8501 /*! PNET_EN - Pretended Networking Enable
8502  *  0b0..Disable
8503  *  0b1..Enable
8504  */
8505 #define CAN_MCR_PNET_EN(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_MCR_PNET_EN_SHIFT)) & CAN_MCR_PNET_EN_MASK)
8506 
8507 #define CAN_MCR_DMA_MASK                         (0x8000U)
8508 #define CAN_MCR_DMA_SHIFT                        (15U)
8509 /*! DMA - DMA Enable
8510  *  0b0..Disable
8511  *  0b1..Enable
8512  */
8513 #define CAN_MCR_DMA(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DMA_SHIFT)) & CAN_MCR_DMA_MASK)
8514 
8515 #define CAN_MCR_IRMQ_MASK                        (0x10000U)
8516 #define CAN_MCR_IRMQ_SHIFT                       (16U)
8517 /*! IRMQ - Individual RX Masking and Queue Enable
8518  *  0b0..Disable
8519  *  0b1..Enable
8520  */
8521 #define CAN_MCR_IRMQ(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK)
8522 
8523 #define CAN_MCR_SRXDIS_MASK                      (0x20000U)
8524 #define CAN_MCR_SRXDIS_SHIFT                     (17U)
8525 /*! SRXDIS - Self-Reception Disable
8526  *  0b0..Enable
8527  *  0b1..Disable
8528  */
8529 #define CAN_MCR_SRXDIS(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK)
8530 
8531 #define CAN_MCR_WAKSRC_MASK                      (0x80000U)
8532 #define CAN_MCR_WAKSRC_SHIFT                     (19U)
8533 /*! WAKSRC - Wake-Up Source
8534  *  0b0..No filter applied
8535  *  0b1..Filter applied
8536  */
8537 #define CAN_MCR_WAKSRC(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK)
8538 
8539 #define CAN_MCR_LPMACK_MASK                      (0x100000U)
8540 #define CAN_MCR_LPMACK_SHIFT                     (20U)
8541 /*! LPMACK - Low-Power Mode Acknowledge
8542  *  0b0..Not in a low-power mode
8543  *  0b1..In a low-power mode
8544  */
8545 #define CAN_MCR_LPMACK(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK)
8546 
8547 #define CAN_MCR_WRNEN_MASK                       (0x200000U)
8548 #define CAN_MCR_WRNEN_SHIFT                      (21U)
8549 /*! WRNEN - Warning Interrupt Enable
8550  *  0b0..Disable
8551  *  0b1..Enable
8552  */
8553 #define CAN_MCR_WRNEN(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK)
8554 
8555 #define CAN_MCR_SLFWAK_MASK                      (0x400000U)
8556 #define CAN_MCR_SLFWAK_SHIFT                     (22U)
8557 /*! SLFWAK - Self Wake-up
8558  *  0b0..Disable
8559  *  0b1..Enable
8560  */
8561 #define CAN_MCR_SLFWAK(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK)
8562 
8563 #define CAN_MCR_FRZACK_MASK                      (0x1000000U)
8564 #define CAN_MCR_FRZACK_SHIFT                     (24U)
8565 /*! FRZACK - Freeze Mode Acknowledge
8566  *  0b0..Not in Freeze mode, prescaler running.
8567  *  0b1..In Freeze mode, prescaler stopped.
8568  */
8569 #define CAN_MCR_FRZACK(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK)
8570 
8571 #define CAN_MCR_SOFTRST_MASK                     (0x2000000U)
8572 #define CAN_MCR_SOFTRST_SHIFT                    (25U)
8573 /*! SOFTRST - Soft Reset
8574  *  0b0..No reset
8575  *  0b1..Soft reset affects reset registers
8576  */
8577 #define CAN_MCR_SOFTRST(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK)
8578 
8579 #define CAN_MCR_WAKMSK_MASK                      (0x4000000U)
8580 #define CAN_MCR_WAKMSK_SHIFT                     (26U)
8581 /*! WAKMSK - Wake-up Interrupt Mask
8582  *  0b0..Disabled
8583  *  0b1..Enabled
8584  */
8585 #define CAN_MCR_WAKMSK(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK)
8586 
8587 #define CAN_MCR_NOTRDY_MASK                      (0x8000000U)
8588 #define CAN_MCR_NOTRDY_SHIFT                     (27U)
8589 /*! NOTRDY - FlexCAN Not Ready
8590  *  0b0..FlexCAN is in Normal mode, Listen-Only mode, or Loopback mode.
8591  *  0b1..FlexCAN is in Disable mode, Stop mode, or Freeze mode.
8592  */
8593 #define CAN_MCR_NOTRDY(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK)
8594 
8595 #define CAN_MCR_HALT_MASK                        (0x10000000U)
8596 #define CAN_MCR_HALT_SHIFT                       (28U)
8597 /*! HALT - Halt FlexCAN
8598  *  0b0..No request
8599  *  0b1..Enter Freeze mode, if MCR[FRZ] = 1.
8600  */
8601 #define CAN_MCR_HALT(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK)
8602 
8603 #define CAN_MCR_RFEN_MASK                        (0x20000000U)
8604 #define CAN_MCR_RFEN_SHIFT                       (29U)
8605 /*! RFEN - Legacy RX FIFO Enable
8606  *  0b0..Disable
8607  *  0b1..Enable
8608  */
8609 #define CAN_MCR_RFEN(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK)
8610 
8611 #define CAN_MCR_FRZ_MASK                         (0x40000000U)
8612 #define CAN_MCR_FRZ_SHIFT                        (30U)
8613 /*! FRZ - Freeze Enable
8614  *  0b0..Disable
8615  *  0b1..Enable
8616  */
8617 #define CAN_MCR_FRZ(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK)
8618 
8619 #define CAN_MCR_MDIS_MASK                        (0x80000000U)
8620 #define CAN_MCR_MDIS_SHIFT                       (31U)
8621 /*! MDIS - Module Disable
8622  *  0b0..Enable
8623  *  0b1..Disable
8624  */
8625 #define CAN_MCR_MDIS(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK)
8626 /*! @} */
8627 
8628 /*! @name CTRL1 - Control 1 */
8629 /*! @{ */
8630 
8631 #define CAN_CTRL1_PROPSEG_MASK                   (0x7U)
8632 #define CAN_CTRL1_PROPSEG_SHIFT                  (0U)
8633 /*! PROPSEG - Propagation Segment */
8634 #define CAN_CTRL1_PROPSEG(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK)
8635 
8636 #define CAN_CTRL1_LOM_MASK                       (0x8U)
8637 #define CAN_CTRL1_LOM_SHIFT                      (3U)
8638 /*! LOM - Listen-Only Mode
8639  *  0b0..Listen-Only mode is deactivated.
8640  *  0b1..FlexCAN module operates in Listen-Only mode.
8641  */
8642 #define CAN_CTRL1_LOM(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK)
8643 
8644 #define CAN_CTRL1_LBUF_MASK                      (0x10U)
8645 #define CAN_CTRL1_LBUF_SHIFT                     (4U)
8646 /*! LBUF - Lowest Buffer Transmitted First
8647  *  0b0..Buffer with highest priority is transmitted first.
8648  *  0b1..Lowest number buffer is transmitted first.
8649  */
8650 #define CAN_CTRL1_LBUF(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK)
8651 
8652 #define CAN_CTRL1_TSYN_MASK                      (0x20U)
8653 #define CAN_CTRL1_TSYN_SHIFT                     (5U)
8654 /*! TSYN - Timer Sync
8655  *  0b0..Disable
8656  *  0b1..Enable
8657  */
8658 #define CAN_CTRL1_TSYN(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK)
8659 
8660 #define CAN_CTRL1_BOFFREC_MASK                   (0x40U)
8661 #define CAN_CTRL1_BOFFREC_SHIFT                  (6U)
8662 /*! BOFFREC - Bus Off Recovery
8663  *  0b0..Enabled
8664  *  0b1..Disabled
8665  */
8666 #define CAN_CTRL1_BOFFREC(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK)
8667 
8668 #define CAN_CTRL1_SMP_MASK                       (0x80U)
8669 #define CAN_CTRL1_SMP_SHIFT                      (7U)
8670 /*! SMP - CAN Bit Sampling
8671  *  0b0..One sample is used to determine the bit value.
8672  *  0b1..Three samples are used to determine the value of the received bit: the regular one (sample point) and two
8673  *       preceding samples. A majority rule is used.
8674  */
8675 #define CAN_CTRL1_SMP(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK)
8676 
8677 #define CAN_CTRL1_RWRNMSK_MASK                   (0x400U)
8678 #define CAN_CTRL1_RWRNMSK_SHIFT                  (10U)
8679 /*! RWRNMSK - RX Warning Interrupt Mask
8680  *  0b0..Disabled
8681  *  0b1..Enabled
8682  */
8683 #define CAN_CTRL1_RWRNMSK(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK)
8684 
8685 #define CAN_CTRL1_TWRNMSK_MASK                   (0x800U)
8686 #define CAN_CTRL1_TWRNMSK_SHIFT                  (11U)
8687 /*! TWRNMSK - TX Warning Interrupt Mask
8688  *  0b0..Disabled
8689  *  0b1..Enabled
8690  */
8691 #define CAN_CTRL1_TWRNMSK(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK)
8692 
8693 #define CAN_CTRL1_LPB_MASK                       (0x1000U)
8694 #define CAN_CTRL1_LPB_SHIFT                      (12U)
8695 /*! LPB - Loopback Mode
8696  *  0b0..Disabled
8697  *  0b1..Enabled
8698  */
8699 #define CAN_CTRL1_LPB(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK)
8700 
8701 #define CAN_CTRL1_ERRMSK_MASK                    (0x4000U)
8702 #define CAN_CTRL1_ERRMSK_SHIFT                   (14U)
8703 /*! ERRMSK - Error Interrupt Mask
8704  *  0b0..Interrupt disabled
8705  *  0b1..Interrupt enabled
8706  */
8707 #define CAN_CTRL1_ERRMSK(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK)
8708 
8709 #define CAN_CTRL1_BOFFMSK_MASK                   (0x8000U)
8710 #define CAN_CTRL1_BOFFMSK_SHIFT                  (15U)
8711 /*! BOFFMSK - Bus Off Interrupt Mask
8712  *  0b0..Interrupt disabled
8713  *  0b1..Interrupt enabled
8714  */
8715 #define CAN_CTRL1_BOFFMSK(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK)
8716 
8717 #define CAN_CTRL1_PSEG2_MASK                     (0x70000U)
8718 #define CAN_CTRL1_PSEG2_SHIFT                    (16U)
8719 /*! PSEG2 - Phase Segment 2 */
8720 #define CAN_CTRL1_PSEG2(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK)
8721 
8722 #define CAN_CTRL1_PSEG1_MASK                     (0x380000U)
8723 #define CAN_CTRL1_PSEG1_SHIFT                    (19U)
8724 /*! PSEG1 - Phase Segment 1 */
8725 #define CAN_CTRL1_PSEG1(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK)
8726 
8727 #define CAN_CTRL1_RJW_MASK                       (0xC00000U)
8728 #define CAN_CTRL1_RJW_SHIFT                      (22U)
8729 /*! RJW - Resync Jump Width */
8730 #define CAN_CTRL1_RJW(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK)
8731 
8732 #define CAN_CTRL1_PRESDIV_MASK                   (0xFF000000U)
8733 #define CAN_CTRL1_PRESDIV_SHIFT                  (24U)
8734 /*! PRESDIV - Prescaler Division Factor */
8735 #define CAN_CTRL1_PRESDIV(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK)
8736 /*! @} */
8737 
8738 /*! @name TIMER - Free-Running Timer */
8739 /*! @{ */
8740 
8741 #define CAN_TIMER_TIMER_MASK                     (0xFFFFU)
8742 #define CAN_TIMER_TIMER_SHIFT                    (0U)
8743 /*! TIMER - Timer Value */
8744 #define CAN_TIMER_TIMER(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK)
8745 /*! @} */
8746 
8747 /*! @name RXMGMASK - RX Message Buffers Global Mask */
8748 /*! @{ */
8749 
8750 #define CAN_RXMGMASK_MG_MASK                     (0xFFFFFFFFU)
8751 #define CAN_RXMGMASK_MG_SHIFT                    (0U)
8752 /*! MG - Global Mask for RX Message Buffers */
8753 #define CAN_RXMGMASK_MG(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK)
8754 /*! @} */
8755 
8756 /*! @name RX14MASK - Receive 14 Mask */
8757 /*! @{ */
8758 
8759 #define CAN_RX14MASK_RX14M_MASK                  (0xFFFFFFFFU)
8760 #define CAN_RX14MASK_RX14M_SHIFT                 (0U)
8761 /*! RX14M - RX Buffer 14 Mask Bits */
8762 #define CAN_RX14MASK_RX14M(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK)
8763 /*! @} */
8764 
8765 /*! @name RX15MASK - Receive 15 Mask */
8766 /*! @{ */
8767 
8768 #define CAN_RX15MASK_RX15M_MASK                  (0xFFFFFFFFU)
8769 #define CAN_RX15MASK_RX15M_SHIFT                 (0U)
8770 /*! RX15M - RX Buffer 15 Mask Bits */
8771 #define CAN_RX15MASK_RX15M(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK)
8772 /*! @} */
8773 
8774 /*! @name ECR - Error Counter */
8775 /*! @{ */
8776 
8777 #define CAN_ECR_TXERRCNT_MASK                    (0xFFU)
8778 #define CAN_ECR_TXERRCNT_SHIFT                   (0U)
8779 /*! TXERRCNT - Transmit Error Counter */
8780 #define CAN_ECR_TXERRCNT(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_SHIFT)) & CAN_ECR_TXERRCNT_MASK)
8781 
8782 #define CAN_ECR_RXERRCNT_MASK                    (0xFF00U)
8783 #define CAN_ECR_RXERRCNT_SHIFT                   (8U)
8784 /*! RXERRCNT - Receive Error Counter */
8785 #define CAN_ECR_RXERRCNT(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_SHIFT)) & CAN_ECR_RXERRCNT_MASK)
8786 
8787 #define CAN_ECR_TXERRCNT_FAST_MASK               (0xFF0000U)
8788 #define CAN_ECR_TXERRCNT_FAST_SHIFT              (16U)
8789 /*! TXERRCNT_FAST - Transmit Error Counter for Fast Bits */
8790 #define CAN_ECR_TXERRCNT_FAST(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_FAST_SHIFT)) & CAN_ECR_TXERRCNT_FAST_MASK)
8791 
8792 #define CAN_ECR_RXERRCNT_FAST_MASK               (0xFF000000U)
8793 #define CAN_ECR_RXERRCNT_FAST_SHIFT              (24U)
8794 /*! RXERRCNT_FAST - Receive Error Counter for Fast Bits */
8795 #define CAN_ECR_RXERRCNT_FAST(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_FAST_SHIFT)) & CAN_ECR_RXERRCNT_FAST_MASK)
8796 /*! @} */
8797 
8798 /*! @name ESR1 - Error and Status 1 */
8799 /*! @{ */
8800 
8801 #define CAN_ESR1_WAKINT_MASK                     (0x1U)
8802 #define CAN_ESR1_WAKINT_SHIFT                    (0U)
8803 /*! WAKINT - Wake-up Interrupt Flag
8804  *  0b0..No such occurrence.
8805  *  0b1..Indicates that a recessive-to-dominant transition was received on the CAN bus.
8806  */
8807 #define CAN_ESR1_WAKINT(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK)
8808 
8809 #define CAN_ESR1_ERRINT_MASK                     (0x2U)
8810 #define CAN_ESR1_ERRINT_SHIFT                    (1U)
8811 /*! ERRINT - Error Interrupt Flag
8812  *  0b0..No such occurrence.
8813  *  0b1..Indicates setting of any error flag in the Error and Status register.
8814  */
8815 #define CAN_ESR1_ERRINT(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK)
8816 
8817 #define CAN_ESR1_BOFFINT_MASK                    (0x4U)
8818 #define CAN_ESR1_BOFFINT_SHIFT                   (2U)
8819 /*! BOFFINT - Bus Off Interrupt Flag
8820  *  0b0..No such occurrence.
8821  *  0b1..FlexCAN module entered Bus Off state.
8822  */
8823 #define CAN_ESR1_BOFFINT(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK)
8824 
8825 #define CAN_ESR1_RX_MASK                         (0x8U)
8826 #define CAN_ESR1_RX_SHIFT                        (3U)
8827 /*! RX - FlexCAN in Reception Flag
8828  *  0b0..Not receiving
8829  *  0b1..Receiving
8830  */
8831 #define CAN_ESR1_RX(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK)
8832 
8833 #define CAN_ESR1_FLTCONF_MASK                    (0x30U)
8834 #define CAN_ESR1_FLTCONF_SHIFT                   (4U)
8835 /*! FLTCONF - Fault Confinement State
8836  *  0b00..Error Active
8837  *  0b01..Error Passive
8838  *  0b1x..Bus Off
8839  */
8840 #define CAN_ESR1_FLTCONF(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK)
8841 
8842 #define CAN_ESR1_TX_MASK                         (0x40U)
8843 #define CAN_ESR1_TX_SHIFT                        (6U)
8844 /*! TX - FlexCAN In Transmission
8845  *  0b0..Not transmitting
8846  *  0b1..Transmitting
8847  */
8848 #define CAN_ESR1_TX(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK)
8849 
8850 #define CAN_ESR1_IDLE_MASK                       (0x80U)
8851 #define CAN_ESR1_IDLE_SHIFT                      (7U)
8852 /*! IDLE - Idle
8853  *  0b0..Not IDLE
8854  *  0b1..IDLE
8855  */
8856 #define CAN_ESR1_IDLE(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK)
8857 
8858 #define CAN_ESR1_RXWRN_MASK                      (0x100U)
8859 #define CAN_ESR1_RXWRN_SHIFT                     (8U)
8860 /*! RXWRN - RX Error Warning Flag
8861  *  0b0..No such occurrence.
8862  *  0b1..RXERRCNT is greater than or equal to 96.
8863  */
8864 #define CAN_ESR1_RXWRN(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK)
8865 
8866 #define CAN_ESR1_TXWRN_MASK                      (0x200U)
8867 #define CAN_ESR1_TXWRN_SHIFT                     (9U)
8868 /*! TXWRN - TX Error Warning Flag
8869  *  0b0..No such occurrence.
8870  *  0b1..TXERRCNT is 96 or greater.
8871  */
8872 #define CAN_ESR1_TXWRN(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK)
8873 
8874 #define CAN_ESR1_STFERR_MASK                     (0x400U)
8875 #define CAN_ESR1_STFERR_SHIFT                    (10U)
8876 /*! STFERR - Stuffing Error Flag
8877  *  0b0..No error
8878  *  0b1..Error occurred since last read of this register.
8879  */
8880 #define CAN_ESR1_STFERR(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK)
8881 
8882 #define CAN_ESR1_FRMERR_MASK                     (0x800U)
8883 #define CAN_ESR1_FRMERR_SHIFT                    (11U)
8884 /*! FRMERR - Form Error Flag
8885  *  0b0..No error
8886  *  0b1..Error occurred since last read of this register.
8887  */
8888 #define CAN_ESR1_FRMERR(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK)
8889 
8890 #define CAN_ESR1_CRCERR_MASK                     (0x1000U)
8891 #define CAN_ESR1_CRCERR_SHIFT                    (12U)
8892 /*! CRCERR - Cyclic Redundancy Check Error Flag
8893  *  0b0..No error
8894  *  0b1..Error occurred since last read of this register.
8895  */
8896 #define CAN_ESR1_CRCERR(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK)
8897 
8898 #define CAN_ESR1_ACKERR_MASK                     (0x2000U)
8899 #define CAN_ESR1_ACKERR_SHIFT                    (13U)
8900 /*! ACKERR - Acknowledge Error Flag
8901  *  0b0..No error
8902  *  0b1..Error occurred since last read of this register.
8903  */
8904 #define CAN_ESR1_ACKERR(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK)
8905 
8906 #define CAN_ESR1_BIT0ERR_MASK                    (0x4000U)
8907 #define CAN_ESR1_BIT0ERR_SHIFT                   (14U)
8908 /*! BIT0ERR - Bit0 Error Flag
8909  *  0b0..No such occurrence.
8910  *  0b1..At least one bit sent as dominant is received as recessive.
8911  */
8912 #define CAN_ESR1_BIT0ERR(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK)
8913 
8914 #define CAN_ESR1_BIT1ERR_MASK                    (0x8000U)
8915 #define CAN_ESR1_BIT1ERR_SHIFT                   (15U)
8916 /*! BIT1ERR - Bit1 Error Flag
8917  *  0b0..No such occurrence.
8918  *  0b1..At least one bit sent as recessive is received as dominant.
8919  */
8920 #define CAN_ESR1_BIT1ERR(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK)
8921 
8922 #define CAN_ESR1_RWRNINT_MASK                    (0x10000U)
8923 #define CAN_ESR1_RWRNINT_SHIFT                   (16U)
8924 /*! RWRNINT - RX Warning Interrupt Flag
8925  *  0b0..No such occurrence
8926  *  0b1..RX error counter changed from less than 96 to greater than or equal to 96.
8927  */
8928 #define CAN_ESR1_RWRNINT(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK)
8929 
8930 #define CAN_ESR1_TWRNINT_MASK                    (0x20000U)
8931 #define CAN_ESR1_TWRNINT_SHIFT                   (17U)
8932 /*! TWRNINT - TX Warning Interrupt Flag
8933  *  0b0..No such occurrence
8934  *  0b1..TX error counter changed from less than 96 to greater than or equal to 96.
8935  */
8936 #define CAN_ESR1_TWRNINT(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK)
8937 
8938 #define CAN_ESR1_SYNCH_MASK                      (0x40000U)
8939 #define CAN_ESR1_SYNCH_SHIFT                     (18U)
8940 /*! SYNCH - CAN Synchronization Status Flag
8941  *  0b0..Not synchronized
8942  *  0b1..Synchronized
8943  */
8944 #define CAN_ESR1_SYNCH(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK)
8945 
8946 #define CAN_ESR1_BOFFDONEINT_MASK                (0x80000U)
8947 #define CAN_ESR1_BOFFDONEINT_SHIFT               (19U)
8948 /*! BOFFDONEINT - Bus Off Done Interrupt Flag
8949  *  0b0..No such occurrence
8950  *  0b1..FlexCAN module has completed Bus Off process.
8951  */
8952 #define CAN_ESR1_BOFFDONEINT(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFDONEINT_SHIFT)) & CAN_ESR1_BOFFDONEINT_MASK)
8953 
8954 #define CAN_ESR1_ERRINT_FAST_MASK                (0x100000U)
8955 #define CAN_ESR1_ERRINT_FAST_SHIFT               (20U)
8956 /*! ERRINT_FAST - Fast Error Interrupt Flag
8957  *  0b0..No such occurrence.
8958  *  0b1..Error flag set in the data phase of CAN FD frames that have BRS = 1.
8959  */
8960 #define CAN_ESR1_ERRINT_FAST(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_FAST_SHIFT)) & CAN_ESR1_ERRINT_FAST_MASK)
8961 
8962 #define CAN_ESR1_ERROVR_MASK                     (0x200000U)
8963 #define CAN_ESR1_ERROVR_SHIFT                    (21U)
8964 /*! ERROVR - Error Overrun Flag
8965  *  0b0..No overrun
8966  *  0b1..Overrun
8967  */
8968 #define CAN_ESR1_ERROVR(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERROVR_SHIFT)) & CAN_ESR1_ERROVR_MASK)
8969 
8970 #define CAN_ESR1_STFERR_FAST_MASK                (0x4000000U)
8971 #define CAN_ESR1_STFERR_FAST_SHIFT               (26U)
8972 /*! STFERR_FAST - Fast Stuffing Error Flag
8973  *  0b0..No such occurrence.
8974  *  0b1..A stuffing error occurred since last read of this register.
8975  */
8976 #define CAN_ESR1_STFERR_FAST(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_FAST_SHIFT)) & CAN_ESR1_STFERR_FAST_MASK)
8977 
8978 #define CAN_ESR1_FRMERR_FAST_MASK                (0x8000000U)
8979 #define CAN_ESR1_FRMERR_FAST_SHIFT               (27U)
8980 /*! FRMERR_FAST - Fast Form Error Flag
8981  *  0b0..No such occurrence.
8982  *  0b1..A form error occurred since last read of this register.
8983  */
8984 #define CAN_ESR1_FRMERR_FAST(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_FAST_SHIFT)) & CAN_ESR1_FRMERR_FAST_MASK)
8985 
8986 #define CAN_ESR1_CRCERR_FAST_MASK                (0x10000000U)
8987 #define CAN_ESR1_CRCERR_FAST_SHIFT               (28U)
8988 /*! CRCERR_FAST - Fast Cyclic Redundancy Check Error Flag
8989  *  0b0..No such occurrence.
8990  *  0b1..A CRC error occurred since last read of this register.
8991  */
8992 #define CAN_ESR1_CRCERR_FAST(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_FAST_SHIFT)) & CAN_ESR1_CRCERR_FAST_MASK)
8993 
8994 #define CAN_ESR1_BIT0ERR_FAST_MASK               (0x40000000U)
8995 #define CAN_ESR1_BIT0ERR_FAST_SHIFT              (30U)
8996 /*! BIT0ERR_FAST - Fast Bit0 Error Flag
8997  *  0b0..No such occurrence.
8998  *  0b1..At least one bit transmitted as dominant is received as recessive.
8999  */
9000 #define CAN_ESR1_BIT0ERR_FAST(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_FAST_SHIFT)) & CAN_ESR1_BIT0ERR_FAST_MASK)
9001 
9002 #define CAN_ESR1_BIT1ERR_FAST_MASK               (0x80000000U)
9003 #define CAN_ESR1_BIT1ERR_FAST_SHIFT              (31U)
9004 /*! BIT1ERR_FAST - Fast Bit1 Error Flag
9005  *  0b0..No such occurrence.
9006  *  0b1..At least one bit transmitted as recessive is received as dominant.
9007  */
9008 #define CAN_ESR1_BIT1ERR_FAST(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_FAST_SHIFT)) & CAN_ESR1_BIT1ERR_FAST_MASK)
9009 /*! @} */
9010 
9011 /*! @name IMASK1 - Interrupt Masks 1 */
9012 /*! @{ */
9013 
9014 #define CAN_IMASK1_BUF31TO0M_MASK                (0xFFFFFFFFU)
9015 #define CAN_IMASK1_BUF31TO0M_SHIFT               (0U)
9016 /*! BUF31TO0M - Buffer MBi Mask */
9017 #define CAN_IMASK1_BUF31TO0M(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUF31TO0M_SHIFT)) & CAN_IMASK1_BUF31TO0M_MASK)
9018 /*! @} */
9019 
9020 /*! @name IFLAG1 - Interrupt Flags 1 */
9021 /*! @{ */
9022 
9023 #define CAN_IFLAG1_BUF0I_MASK                    (0x1U)
9024 #define CAN_IFLAG1_BUF0I_SHIFT                   (0U)
9025 /*! BUF0I - Buffer MB0 Interrupt or Clear Legacy FIFO bit
9026  *  0b0..MB0 has no occurrence of successfully completed transmission or reception.
9027  *  0b1..MB0 has successfully completed transmission or reception.
9028  */
9029 #define CAN_IFLAG1_BUF0I(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF0I_SHIFT)) & CAN_IFLAG1_BUF0I_MASK)
9030 
9031 #define CAN_IFLAG1_BUF4TO1I_MASK                 (0x1EU)
9032 #define CAN_IFLAG1_BUF4TO1I_SHIFT                (1U)
9033 /*! BUF4TO1I - Buffer MBi Interrupt or Reserved */
9034 #define CAN_IFLAG1_BUF4TO1I(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO1I_SHIFT)) & CAN_IFLAG1_BUF4TO1I_MASK)
9035 
9036 #define CAN_IFLAG1_BUF5I_MASK                    (0x20U)
9037 #define CAN_IFLAG1_BUF5I_SHIFT                   (5U)
9038 /*! BUF5I - Buffer MB5 Interrupt or Frames available in Legacy RX FIFO
9039  *  0b0..No occurrence of completed transmission or reception, or no frames available
9040  *  0b1..MB5 completed transmission or reception, or frames available
9041  */
9042 #define CAN_IFLAG1_BUF5I(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK)
9043 
9044 #define CAN_IFLAG1_BUF6I_MASK                    (0x40U)
9045 #define CAN_IFLAG1_BUF6I_SHIFT                   (6U)
9046 /*! BUF6I - Buffer MB6 Interrupt or Legacy RX FIFO Warning
9047  *  0b0..No occurrence of MB6 completing transmission or reception, or FIFO not almost full.
9048  *  0b1..MB6 completed transmission or reception, or FIFO almost full.
9049  */
9050 #define CAN_IFLAG1_BUF6I(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK)
9051 
9052 #define CAN_IFLAG1_BUF7I_MASK                    (0x80U)
9053 #define CAN_IFLAG1_BUF7I_SHIFT                   (7U)
9054 /*! BUF7I - Buffer MB7 Interrupt or Legacy RX FIFO Overflow
9055  *  0b0..No occurrence of MB7 completing transmission or reception, or no FIFO overflow.
9056  *  0b1..MB7 completed transmission or reception, or FIFO overflow.
9057  */
9058 #define CAN_IFLAG1_BUF7I(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK)
9059 
9060 #define CAN_IFLAG1_BUF31TO8I_MASK                (0xFFFFFF00U)
9061 #define CAN_IFLAG1_BUF31TO8I_SHIFT               (8U)
9062 /*! BUF31TO8I - Buffer MBi Interrupt */
9063 #define CAN_IFLAG1_BUF31TO8I(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK)
9064 /*! @} */
9065 
9066 /*! @name CTRL2 - Control 2 */
9067 /*! @{ */
9068 
9069 #define CAN_CTRL2_EDFLTDIS_MASK                  (0x800U)
9070 #define CAN_CTRL2_EDFLTDIS_SHIFT                 (11U)
9071 /*! EDFLTDIS - Edge Filter Disable
9072  *  0b0..Enabled
9073  *  0b1..Disabled
9074  */
9075 #define CAN_CTRL2_EDFLTDIS(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EDFLTDIS_SHIFT)) & CAN_CTRL2_EDFLTDIS_MASK)
9076 
9077 #define CAN_CTRL2_ISOCANFDEN_MASK                (0x1000U)
9078 #define CAN_CTRL2_ISOCANFDEN_SHIFT               (12U)
9079 /*! ISOCANFDEN - ISO CAN FD Enable
9080  *  0b0..Disable
9081  *  0b1..Enable
9082  */
9083 #define CAN_CTRL2_ISOCANFDEN(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ISOCANFDEN_SHIFT)) & CAN_CTRL2_ISOCANFDEN_MASK)
9084 
9085 #define CAN_CTRL2_BTE_MASK                       (0x2000U)
9086 #define CAN_CTRL2_BTE_SHIFT                      (13U)
9087 /*! BTE - Bit Timing Expansion Enable
9088  *  0b0..Disable
9089  *  0b1..Enable
9090  */
9091 #define CAN_CTRL2_BTE(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_BTE_SHIFT)) & CAN_CTRL2_BTE_MASK)
9092 
9093 #define CAN_CTRL2_PREXCEN_MASK                   (0x4000U)
9094 #define CAN_CTRL2_PREXCEN_SHIFT                  (14U)
9095 /*! PREXCEN - Protocol Exception Enable
9096  *  0b0..Disabled
9097  *  0b1..Enabled
9098  */
9099 #define CAN_CTRL2_PREXCEN(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_PREXCEN_SHIFT)) & CAN_CTRL2_PREXCEN_MASK)
9100 
9101 #define CAN_CTRL2_EACEN_MASK                     (0x10000U)
9102 #define CAN_CTRL2_EACEN_SHIFT                    (16U)
9103 /*! EACEN - Entire Frame Arbitration Field Comparison Enable for RX Message Buffers
9104  *  0b0..Disable
9105  *  0b1..Enable
9106  */
9107 #define CAN_CTRL2_EACEN(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK)
9108 
9109 #define CAN_CTRL2_RRS_MASK                       (0x20000U)
9110 #define CAN_CTRL2_RRS_SHIFT                      (17U)
9111 /*! RRS - Remote Request Storing
9112  *  0b0..Generated
9113  *  0b1..Stored
9114  */
9115 #define CAN_CTRL2_RRS(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK)
9116 
9117 #define CAN_CTRL2_MRP_MASK                       (0x40000U)
9118 #define CAN_CTRL2_MRP_SHIFT                      (18U)
9119 /*! MRP - Message Buffers Reception Priority
9120  *  0b0..Matching starts from Legacy RX FIFO or Enhanced RX FIFO and continues on message buffers.
9121  *  0b1..Matching starts from message buffers and continues on Legacy RX FIFO or Enhanced RX FIFO.
9122  */
9123 #define CAN_CTRL2_MRP(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK)
9124 
9125 #define CAN_CTRL2_TASD_MASK                      (0xF80000U)
9126 #define CAN_CTRL2_TASD_SHIFT                     (19U)
9127 /*! TASD - Transmission Arbitration Start Delay */
9128 #define CAN_CTRL2_TASD(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK)
9129 
9130 #define CAN_CTRL2_RFFN_MASK                      (0xF000000U)
9131 #define CAN_CTRL2_RFFN_SHIFT                     (24U)
9132 /*! RFFN - Number of Legacy Receive FIFO Filters */
9133 #define CAN_CTRL2_RFFN(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK)
9134 
9135 #define CAN_CTRL2_BOFFDONEMSK_MASK               (0x40000000U)
9136 #define CAN_CTRL2_BOFFDONEMSK_SHIFT              (30U)
9137 /*! BOFFDONEMSK - Bus Off Done Interrupt Mask
9138  *  0b0..Disable
9139  *  0b1..Enable
9140  */
9141 #define CAN_CTRL2_BOFFDONEMSK(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_BOFFDONEMSK_SHIFT)) & CAN_CTRL2_BOFFDONEMSK_MASK)
9142 
9143 #define CAN_CTRL2_ERRMSK_FAST_MASK               (0x80000000U)
9144 #define CAN_CTRL2_ERRMSK_FAST_SHIFT              (31U)
9145 /*! ERRMSK_FAST - Error Interrupt Mask for Errors Detected in the Data Phase of Fast CAN FD Frames
9146  *  0b0..Disable
9147  *  0b1..Enable
9148  */
9149 #define CAN_CTRL2_ERRMSK_FAST(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ERRMSK_FAST_SHIFT)) & CAN_CTRL2_ERRMSK_FAST_MASK)
9150 /*! @} */
9151 
9152 /*! @name ESR2 - Error and Status 2 */
9153 /*! @{ */
9154 
9155 #define CAN_ESR2_IMB_MASK                        (0x2000U)
9156 #define CAN_ESR2_IMB_SHIFT                       (13U)
9157 /*! IMB - Inactive Message Buffer
9158  *  0b0..Message buffer indicated by ESR2[LPTM] is not inactive.
9159  *  0b1..At least one message buffer is inactive.
9160  */
9161 #define CAN_ESR2_IMB(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK)
9162 
9163 #define CAN_ESR2_VPS_MASK                        (0x4000U)
9164 #define CAN_ESR2_VPS_SHIFT                       (14U)
9165 /*! VPS - Valid Priority Status
9166  *  0b0..Invalid
9167  *  0b1..Valid
9168  */
9169 #define CAN_ESR2_VPS(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK)
9170 
9171 #define CAN_ESR2_LPTM_MASK                       (0x7F0000U)
9172 #define CAN_ESR2_LPTM_SHIFT                      (16U)
9173 /*! LPTM - Lowest Priority TX Message Buffer */
9174 #define CAN_ESR2_LPTM(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK)
9175 /*! @} */
9176 
9177 /*! @name CRCR - Cyclic Redundancy Check */
9178 /*! @{ */
9179 
9180 #define CAN_CRCR_TXCRC_MASK                      (0x7FFFU)
9181 #define CAN_CRCR_TXCRC_SHIFT                     (0U)
9182 /*! TXCRC - Transmitted CRC value */
9183 #define CAN_CRCR_TXCRC(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK)
9184 
9185 #define CAN_CRCR_MBCRC_MASK                      (0x7F0000U)
9186 #define CAN_CRCR_MBCRC_SHIFT                     (16U)
9187 /*! MBCRC - CRC Message Buffer */
9188 #define CAN_CRCR_MBCRC(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK)
9189 /*! @} */
9190 
9191 /*! @name RXFGMASK - Legacy RX FIFO Global Mask */
9192 /*! @{ */
9193 
9194 #define CAN_RXFGMASK_FGM_MASK                    (0xFFFFFFFFU)
9195 #define CAN_RXFGMASK_FGM_SHIFT                   (0U)
9196 /*! FGM - Legacy RX FIFO Global Mask Bits */
9197 #define CAN_RXFGMASK_FGM(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK)
9198 /*! @} */
9199 
9200 /*! @name RXFIR - Legacy RX FIFO Information */
9201 /*! @{ */
9202 
9203 #define CAN_RXFIR_IDHIT_MASK                     (0x1FFU)
9204 #define CAN_RXFIR_IDHIT_SHIFT                    (0U)
9205 /*! IDHIT - Identifier Acceptance Filter Hit Indicator */
9206 #define CAN_RXFIR_IDHIT(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK)
9207 /*! @} */
9208 
9209 /*! @name CBT - CAN Bit Timing */
9210 /*! @{ */
9211 
9212 #define CAN_CBT_EPSEG2_MASK                      (0x1FU)
9213 #define CAN_CBT_EPSEG2_SHIFT                     (0U)
9214 /*! EPSEG2 - Extended Phase Segment 2 */
9215 #define CAN_CBT_EPSEG2(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG2_SHIFT)) & CAN_CBT_EPSEG2_MASK)
9216 
9217 #define CAN_CBT_EPSEG1_MASK                      (0x3E0U)
9218 #define CAN_CBT_EPSEG1_SHIFT                     (5U)
9219 /*! EPSEG1 - Extended Phase Segment 1 */
9220 #define CAN_CBT_EPSEG1(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG1_SHIFT)) & CAN_CBT_EPSEG1_MASK)
9221 
9222 #define CAN_CBT_EPROPSEG_MASK                    (0xFC00U)
9223 #define CAN_CBT_EPROPSEG_SHIFT                   (10U)
9224 /*! EPROPSEG - Extended Propagation Segment */
9225 #define CAN_CBT_EPROPSEG(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPROPSEG_SHIFT)) & CAN_CBT_EPROPSEG_MASK)
9226 
9227 #define CAN_CBT_ERJW_MASK                        (0x1F0000U)
9228 #define CAN_CBT_ERJW_SHIFT                       (16U)
9229 /*! ERJW - Extended Resync Jump Width */
9230 #define CAN_CBT_ERJW(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_CBT_ERJW_SHIFT)) & CAN_CBT_ERJW_MASK)
9231 
9232 #define CAN_CBT_EPRESDIV_MASK                    (0x7FE00000U)
9233 #define CAN_CBT_EPRESDIV_SHIFT                   (21U)
9234 /*! EPRESDIV - Extended Prescaler Division Factor */
9235 #define CAN_CBT_EPRESDIV(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPRESDIV_SHIFT)) & CAN_CBT_EPRESDIV_MASK)
9236 
9237 #define CAN_CBT_BTF_MASK                         (0x80000000U)
9238 #define CAN_CBT_BTF_SHIFT                        (31U)
9239 /*! BTF - Bit Timing Format Enable
9240  *  0b0..Disable
9241  *  0b1..Enable
9242  */
9243 #define CAN_CBT_BTF(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_CBT_BTF_SHIFT)) & CAN_CBT_BTF_MASK)
9244 /*! @} */
9245 
9246 /* The count of CAN_CS */
9247 #define CAN_CS_COUNT_MB8B                        (32U)
9248 
9249 /* The count of CAN_ID */
9250 #define CAN_ID_COUNT_MB8B                        (32U)
9251 
9252 /* The count of CAN_WORD */
9253 #define CAN_WORD_COUNT_MB8B                      (32U)
9254 
9255 /* The count of CAN_WORD */
9256 #define CAN_WORD_COUNT_MB8B2                     (2U)
9257 
9258 /* The count of CAN_CS */
9259 #define CAN_CS_COUNT_MB16B                       (21U)
9260 
9261 /* The count of CAN_ID */
9262 #define CAN_ID_COUNT_MB16B                       (21U)
9263 
9264 /* The count of CAN_WORD */
9265 #define CAN_WORD_COUNT_MB16B                     (21U)
9266 
9267 /* The count of CAN_WORD */
9268 #define CAN_WORD_COUNT_MB16B2                    (4U)
9269 
9270 /* The count of CAN_CS */
9271 #define CAN_CS_COUNT_MB32B                       (12U)
9272 
9273 /* The count of CAN_ID */
9274 #define CAN_ID_COUNT_MB32B                       (12U)
9275 
9276 /* The count of CAN_WORD */
9277 #define CAN_WORD_COUNT_MB32B                     (12U)
9278 
9279 /* The count of CAN_WORD */
9280 #define CAN_WORD_COUNT_MB32B2                    (8U)
9281 
9282 /*! @name CS - Message Buffer 0 CS Register..Message Buffer 6 CS Register */
9283 /*! @{ */
9284 
9285 #define CAN_CS_TIME_STAMP_MASK                   (0xFFFFU)
9286 #define CAN_CS_TIME_STAMP_SHIFT                  (0U)
9287 /*! TIME_STAMP - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running
9288  *    Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field
9289  *    appears on the CAN bus.
9290  */
9291 #define CAN_CS_TIME_STAMP(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK)
9292 
9293 #define CAN_CS_DLC_MASK                          (0xF0000U)
9294 #define CAN_CS_DLC_SHIFT                         (16U)
9295 /*! DLC - Length of the data to be stored/transmitted. */
9296 #define CAN_CS_DLC(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK)
9297 
9298 #define CAN_CS_RTR_MASK                          (0x100000U)
9299 #define CAN_CS_RTR_SHIFT                         (20U)
9300 /*! RTR - Remote Transmission Request. One/zero for remote/data frame. */
9301 #define CAN_CS_RTR(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK)
9302 
9303 #define CAN_CS_IDE_MASK                          (0x200000U)
9304 #define CAN_CS_IDE_SHIFT                         (21U)
9305 /*! IDE - ID Extended. One/zero for extended/standard format frame. */
9306 #define CAN_CS_IDE(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK)
9307 
9308 #define CAN_CS_SRR_MASK                          (0x400000U)
9309 #define CAN_CS_SRR_SHIFT                         (22U)
9310 /*! SRR - Substitute Remote Request. Contains a fixed recessive bit. */
9311 #define CAN_CS_SRR(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK)
9312 
9313 #define CAN_CS_CODE_MASK                         (0xF000000U)
9314 #define CAN_CS_CODE_SHIFT                        (24U)
9315 /*! CODE - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by
9316  *    the FlexCAN module itself, as part of the message buffer matching and arbitration process.
9317  */
9318 #define CAN_CS_CODE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK)
9319 
9320 #define CAN_CS_ESI_MASK                          (0x20000000U)
9321 #define CAN_CS_ESI_SHIFT                         (29U)
9322 /*! ESI - Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */
9323 #define CAN_CS_ESI(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_ESI_SHIFT)) & CAN_CS_ESI_MASK)
9324 
9325 #define CAN_CS_BRS_MASK                          (0x40000000U)
9326 #define CAN_CS_BRS_SHIFT                         (30U)
9327 /*! BRS - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */
9328 #define CAN_CS_BRS(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_BRS_SHIFT)) & CAN_CS_BRS_MASK)
9329 
9330 #define CAN_CS_EDL_MASK                          (0x80000000U)
9331 #define CAN_CS_EDL_SHIFT                         (31U)
9332 /*! EDL - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames.
9333  *    The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.
9334  */
9335 #define CAN_CS_EDL(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_EDL_SHIFT)) & CAN_CS_EDL_MASK)
9336 /*! @} */
9337 
9338 /* The count of CAN_CS */
9339 #define CAN_CS_COUNT_MB64B                       (7U)
9340 
9341 /*! @name ID - Message Buffer 0 ID Register..Message Buffer 6 ID Register */
9342 /*! @{ */
9343 
9344 #define CAN_ID_EXT_MASK                          (0x3FFFFU)
9345 #define CAN_ID_EXT_SHIFT                         (0U)
9346 /*! EXT - Contains extended (LOW word) identifier of message buffer. */
9347 #define CAN_ID_EXT(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK)
9348 
9349 #define CAN_ID_STD_MASK                          (0x1FFC0000U)
9350 #define CAN_ID_STD_SHIFT                         (18U)
9351 /*! STD - Contains standard/extended (HIGH word) identifier of message buffer. */
9352 #define CAN_ID_STD(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK)
9353 
9354 #define CAN_ID_PRIO_MASK                         (0xE0000000U)
9355 #define CAN_ID_PRIO_SHIFT                        (29U)
9356 /*! PRIO - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only
9357  *    makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular
9358  *    ID to define the transmission priority.
9359  */
9360 #define CAN_ID_PRIO(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK)
9361 /*! @} */
9362 
9363 /* The count of CAN_ID */
9364 #define CAN_ID_COUNT_MB64B                       (7U)
9365 
9366 /*! @name WORD - Message Buffer 0 WORD_64B Register..Message Buffer 6 WORD_64B Register */
9367 /*! @{ */
9368 
9369 #define CAN_WORD_DATA_BYTE_3_MASK                (0xFFU)
9370 #define CAN_WORD_DATA_BYTE_3_SHIFT               (0U)
9371 /*! DATA_BYTE_3 - Data byte 0 of Rx/Tx frame. */
9372 #define CAN_WORD_DATA_BYTE_3(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_3_SHIFT)) & CAN_WORD_DATA_BYTE_3_MASK)
9373 
9374 #define CAN_WORD_DATA_BYTE_7_MASK                (0xFFU)
9375 #define CAN_WORD_DATA_BYTE_7_SHIFT               (0U)
9376 /*! DATA_BYTE_7 - Data byte 0 of Rx/Tx frame. */
9377 #define CAN_WORD_DATA_BYTE_7(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_7_SHIFT)) & CAN_WORD_DATA_BYTE_7_MASK)
9378 
9379 #define CAN_WORD_DATA_BYTE_11_MASK               (0xFFU)
9380 #define CAN_WORD_DATA_BYTE_11_SHIFT              (0U)
9381 /*! DATA_BYTE_11 - Data byte 0 of Rx/Tx frame. */
9382 #define CAN_WORD_DATA_BYTE_11(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_11_SHIFT)) & CAN_WORD_DATA_BYTE_11_MASK)
9383 
9384 #define CAN_WORD_DATA_BYTE_15_MASK               (0xFFU)
9385 #define CAN_WORD_DATA_BYTE_15_SHIFT              (0U)
9386 /*! DATA_BYTE_15 - Data byte 0 of Rx/Tx frame. */
9387 #define CAN_WORD_DATA_BYTE_15(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_15_SHIFT)) & CAN_WORD_DATA_BYTE_15_MASK)
9388 
9389 #define CAN_WORD_DATA_BYTE_19_MASK               (0xFFU)
9390 #define CAN_WORD_DATA_BYTE_19_SHIFT              (0U)
9391 /*! DATA_BYTE_19 - Data byte 0 of Rx/Tx frame. */
9392 #define CAN_WORD_DATA_BYTE_19(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_19_SHIFT)) & CAN_WORD_DATA_BYTE_19_MASK)
9393 
9394 #define CAN_WORD_DATA_BYTE_23_MASK               (0xFFU)
9395 #define CAN_WORD_DATA_BYTE_23_SHIFT              (0U)
9396 /*! DATA_BYTE_23 - Data byte 0 of Rx/Tx frame. */
9397 #define CAN_WORD_DATA_BYTE_23(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_23_SHIFT)) & CAN_WORD_DATA_BYTE_23_MASK)
9398 
9399 #define CAN_WORD_DATA_BYTE_27_MASK               (0xFFU)
9400 #define CAN_WORD_DATA_BYTE_27_SHIFT              (0U)
9401 /*! DATA_BYTE_27 - Data byte 0 of Rx/Tx frame. */
9402 #define CAN_WORD_DATA_BYTE_27(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_27_SHIFT)) & CAN_WORD_DATA_BYTE_27_MASK)
9403 
9404 #define CAN_WORD_DATA_BYTE_31_MASK               (0xFFU)
9405 #define CAN_WORD_DATA_BYTE_31_SHIFT              (0U)
9406 /*! DATA_BYTE_31 - Data byte 0 of Rx/Tx frame. */
9407 #define CAN_WORD_DATA_BYTE_31(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_31_SHIFT)) & CAN_WORD_DATA_BYTE_31_MASK)
9408 
9409 #define CAN_WORD_DATA_BYTE_35_MASK               (0xFFU)
9410 #define CAN_WORD_DATA_BYTE_35_SHIFT              (0U)
9411 /*! DATA_BYTE_35 - Data byte 0 of Rx/Tx frame. */
9412 #define CAN_WORD_DATA_BYTE_35(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_35_SHIFT)) & CAN_WORD_DATA_BYTE_35_MASK)
9413 
9414 #define CAN_WORD_DATA_BYTE_39_MASK               (0xFFU)
9415 #define CAN_WORD_DATA_BYTE_39_SHIFT              (0U)
9416 /*! DATA_BYTE_39 - Data byte 0 of Rx/Tx frame. */
9417 #define CAN_WORD_DATA_BYTE_39(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_39_SHIFT)) & CAN_WORD_DATA_BYTE_39_MASK)
9418 
9419 #define CAN_WORD_DATA_BYTE_43_MASK               (0xFFU)
9420 #define CAN_WORD_DATA_BYTE_43_SHIFT              (0U)
9421 /*! DATA_BYTE_43 - Data byte 0 of Rx/Tx frame. */
9422 #define CAN_WORD_DATA_BYTE_43(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_43_SHIFT)) & CAN_WORD_DATA_BYTE_43_MASK)
9423 
9424 #define CAN_WORD_DATA_BYTE_47_MASK               (0xFFU)
9425 #define CAN_WORD_DATA_BYTE_47_SHIFT              (0U)
9426 /*! DATA_BYTE_47 - Data byte 0 of Rx/Tx frame. */
9427 #define CAN_WORD_DATA_BYTE_47(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_47_SHIFT)) & CAN_WORD_DATA_BYTE_47_MASK)
9428 
9429 #define CAN_WORD_DATA_BYTE_51_MASK               (0xFFU)
9430 #define CAN_WORD_DATA_BYTE_51_SHIFT              (0U)
9431 /*! DATA_BYTE_51 - Data byte 0 of Rx/Tx frame. */
9432 #define CAN_WORD_DATA_BYTE_51(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_51_SHIFT)) & CAN_WORD_DATA_BYTE_51_MASK)
9433 
9434 #define CAN_WORD_DATA_BYTE_55_MASK               (0xFFU)
9435 #define CAN_WORD_DATA_BYTE_55_SHIFT              (0U)
9436 /*! DATA_BYTE_55 - Data byte 0 of Rx/Tx frame. */
9437 #define CAN_WORD_DATA_BYTE_55(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_55_SHIFT)) & CAN_WORD_DATA_BYTE_55_MASK)
9438 
9439 #define CAN_WORD_DATA_BYTE_59_MASK               (0xFFU)
9440 #define CAN_WORD_DATA_BYTE_59_SHIFT              (0U)
9441 /*! DATA_BYTE_59 - Data byte 0 of Rx/Tx frame. */
9442 #define CAN_WORD_DATA_BYTE_59(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_59_SHIFT)) & CAN_WORD_DATA_BYTE_59_MASK)
9443 
9444 #define CAN_WORD_DATA_BYTE_63_MASK               (0xFFU)
9445 #define CAN_WORD_DATA_BYTE_63_SHIFT              (0U)
9446 /*! DATA_BYTE_63 - Data byte 0 of Rx/Tx frame. */
9447 #define CAN_WORD_DATA_BYTE_63(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_63_SHIFT)) & CAN_WORD_DATA_BYTE_63_MASK)
9448 
9449 #define CAN_WORD_DATA_BYTE_2_MASK                (0xFF00U)
9450 #define CAN_WORD_DATA_BYTE_2_SHIFT               (8U)
9451 /*! DATA_BYTE_2 - Data byte 1 of Rx/Tx frame. */
9452 #define CAN_WORD_DATA_BYTE_2(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_2_SHIFT)) & CAN_WORD_DATA_BYTE_2_MASK)
9453 
9454 #define CAN_WORD_DATA_BYTE_6_MASK                (0xFF00U)
9455 #define CAN_WORD_DATA_BYTE_6_SHIFT               (8U)
9456 /*! DATA_BYTE_6 - Data byte 1 of Rx/Tx frame. */
9457 #define CAN_WORD_DATA_BYTE_6(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_6_SHIFT)) & CAN_WORD_DATA_BYTE_6_MASK)
9458 
9459 #define CAN_WORD_DATA_BYTE_10_MASK               (0xFF00U)
9460 #define CAN_WORD_DATA_BYTE_10_SHIFT              (8U)
9461 /*! DATA_BYTE_10 - Data byte 1 of Rx/Tx frame. */
9462 #define CAN_WORD_DATA_BYTE_10(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_10_SHIFT)) & CAN_WORD_DATA_BYTE_10_MASK)
9463 
9464 #define CAN_WORD_DATA_BYTE_14_MASK               (0xFF00U)
9465 #define CAN_WORD_DATA_BYTE_14_SHIFT              (8U)
9466 /*! DATA_BYTE_14 - Data byte 1 of Rx/Tx frame. */
9467 #define CAN_WORD_DATA_BYTE_14(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_14_SHIFT)) & CAN_WORD_DATA_BYTE_14_MASK)
9468 
9469 #define CAN_WORD_DATA_BYTE_18_MASK               (0xFF00U)
9470 #define CAN_WORD_DATA_BYTE_18_SHIFT              (8U)
9471 /*! DATA_BYTE_18 - Data byte 1 of Rx/Tx frame. */
9472 #define CAN_WORD_DATA_BYTE_18(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_18_SHIFT)) & CAN_WORD_DATA_BYTE_18_MASK)
9473 
9474 #define CAN_WORD_DATA_BYTE_22_MASK               (0xFF00U)
9475 #define CAN_WORD_DATA_BYTE_22_SHIFT              (8U)
9476 /*! DATA_BYTE_22 - Data byte 1 of Rx/Tx frame. */
9477 #define CAN_WORD_DATA_BYTE_22(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_22_SHIFT)) & CAN_WORD_DATA_BYTE_22_MASK)
9478 
9479 #define CAN_WORD_DATA_BYTE_26_MASK               (0xFF00U)
9480 #define CAN_WORD_DATA_BYTE_26_SHIFT              (8U)
9481 /*! DATA_BYTE_26 - Data byte 1 of Rx/Tx frame. */
9482 #define CAN_WORD_DATA_BYTE_26(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_26_SHIFT)) & CAN_WORD_DATA_BYTE_26_MASK)
9483 
9484 #define CAN_WORD_DATA_BYTE_30_MASK               (0xFF00U)
9485 #define CAN_WORD_DATA_BYTE_30_SHIFT              (8U)
9486 /*! DATA_BYTE_30 - Data byte 1 of Rx/Tx frame. */
9487 #define CAN_WORD_DATA_BYTE_30(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_30_SHIFT)) & CAN_WORD_DATA_BYTE_30_MASK)
9488 
9489 #define CAN_WORD_DATA_BYTE_34_MASK               (0xFF00U)
9490 #define CAN_WORD_DATA_BYTE_34_SHIFT              (8U)
9491 /*! DATA_BYTE_34 - Data byte 1 of Rx/Tx frame. */
9492 #define CAN_WORD_DATA_BYTE_34(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_34_SHIFT)) & CAN_WORD_DATA_BYTE_34_MASK)
9493 
9494 #define CAN_WORD_DATA_BYTE_38_MASK               (0xFF00U)
9495 #define CAN_WORD_DATA_BYTE_38_SHIFT              (8U)
9496 /*! DATA_BYTE_38 - Data byte 1 of Rx/Tx frame. */
9497 #define CAN_WORD_DATA_BYTE_38(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_38_SHIFT)) & CAN_WORD_DATA_BYTE_38_MASK)
9498 
9499 #define CAN_WORD_DATA_BYTE_42_MASK               (0xFF00U)
9500 #define CAN_WORD_DATA_BYTE_42_SHIFT              (8U)
9501 /*! DATA_BYTE_42 - Data byte 1 of Rx/Tx frame. */
9502 #define CAN_WORD_DATA_BYTE_42(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_42_SHIFT)) & CAN_WORD_DATA_BYTE_42_MASK)
9503 
9504 #define CAN_WORD_DATA_BYTE_46_MASK               (0xFF00U)
9505 #define CAN_WORD_DATA_BYTE_46_SHIFT              (8U)
9506 /*! DATA_BYTE_46 - Data byte 1 of Rx/Tx frame. */
9507 #define CAN_WORD_DATA_BYTE_46(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_46_SHIFT)) & CAN_WORD_DATA_BYTE_46_MASK)
9508 
9509 #define CAN_WORD_DATA_BYTE_50_MASK               (0xFF00U)
9510 #define CAN_WORD_DATA_BYTE_50_SHIFT              (8U)
9511 /*! DATA_BYTE_50 - Data byte 1 of Rx/Tx frame. */
9512 #define CAN_WORD_DATA_BYTE_50(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_50_SHIFT)) & CAN_WORD_DATA_BYTE_50_MASK)
9513 
9514 #define CAN_WORD_DATA_BYTE_54_MASK               (0xFF00U)
9515 #define CAN_WORD_DATA_BYTE_54_SHIFT              (8U)
9516 /*! DATA_BYTE_54 - Data byte 1 of Rx/Tx frame. */
9517 #define CAN_WORD_DATA_BYTE_54(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_54_SHIFT)) & CAN_WORD_DATA_BYTE_54_MASK)
9518 
9519 #define CAN_WORD_DATA_BYTE_58_MASK               (0xFF00U)
9520 #define CAN_WORD_DATA_BYTE_58_SHIFT              (8U)
9521 /*! DATA_BYTE_58 - Data byte 1 of Rx/Tx frame. */
9522 #define CAN_WORD_DATA_BYTE_58(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_58_SHIFT)) & CAN_WORD_DATA_BYTE_58_MASK)
9523 
9524 #define CAN_WORD_DATA_BYTE_62_MASK               (0xFF00U)
9525 #define CAN_WORD_DATA_BYTE_62_SHIFT              (8U)
9526 /*! DATA_BYTE_62 - Data byte 1 of Rx/Tx frame. */
9527 #define CAN_WORD_DATA_BYTE_62(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_62_SHIFT)) & CAN_WORD_DATA_BYTE_62_MASK)
9528 
9529 #define CAN_WORD_DATA_BYTE_1_MASK                (0xFF0000U)
9530 #define CAN_WORD_DATA_BYTE_1_SHIFT               (16U)
9531 /*! DATA_BYTE_1 - Data byte 2 of Rx/Tx frame. */
9532 #define CAN_WORD_DATA_BYTE_1(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_1_SHIFT)) & CAN_WORD_DATA_BYTE_1_MASK)
9533 
9534 #define CAN_WORD_DATA_BYTE_5_MASK                (0xFF0000U)
9535 #define CAN_WORD_DATA_BYTE_5_SHIFT               (16U)
9536 /*! DATA_BYTE_5 - Data byte 2 of Rx/Tx frame. */
9537 #define CAN_WORD_DATA_BYTE_5(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_5_SHIFT)) & CAN_WORD_DATA_BYTE_5_MASK)
9538 
9539 #define CAN_WORD_DATA_BYTE_9_MASK                (0xFF0000U)
9540 #define CAN_WORD_DATA_BYTE_9_SHIFT               (16U)
9541 /*! DATA_BYTE_9 - Data byte 2 of Rx/Tx frame. */
9542 #define CAN_WORD_DATA_BYTE_9(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_9_SHIFT)) & CAN_WORD_DATA_BYTE_9_MASK)
9543 
9544 #define CAN_WORD_DATA_BYTE_13_MASK               (0xFF0000U)
9545 #define CAN_WORD_DATA_BYTE_13_SHIFT              (16U)
9546 /*! DATA_BYTE_13 - Data byte 2 of Rx/Tx frame. */
9547 #define CAN_WORD_DATA_BYTE_13(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_13_SHIFT)) & CAN_WORD_DATA_BYTE_13_MASK)
9548 
9549 #define CAN_WORD_DATA_BYTE_17_MASK               (0xFF0000U)
9550 #define CAN_WORD_DATA_BYTE_17_SHIFT              (16U)
9551 /*! DATA_BYTE_17 - Data byte 2 of Rx/Tx frame. */
9552 #define CAN_WORD_DATA_BYTE_17(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_17_SHIFT)) & CAN_WORD_DATA_BYTE_17_MASK)
9553 
9554 #define CAN_WORD_DATA_BYTE_21_MASK               (0xFF0000U)
9555 #define CAN_WORD_DATA_BYTE_21_SHIFT              (16U)
9556 /*! DATA_BYTE_21 - Data byte 2 of Rx/Tx frame. */
9557 #define CAN_WORD_DATA_BYTE_21(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_21_SHIFT)) & CAN_WORD_DATA_BYTE_21_MASK)
9558 
9559 #define CAN_WORD_DATA_BYTE_25_MASK               (0xFF0000U)
9560 #define CAN_WORD_DATA_BYTE_25_SHIFT              (16U)
9561 /*! DATA_BYTE_25 - Data byte 2 of Rx/Tx frame. */
9562 #define CAN_WORD_DATA_BYTE_25(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_25_SHIFT)) & CAN_WORD_DATA_BYTE_25_MASK)
9563 
9564 #define CAN_WORD_DATA_BYTE_29_MASK               (0xFF0000U)
9565 #define CAN_WORD_DATA_BYTE_29_SHIFT              (16U)
9566 /*! DATA_BYTE_29 - Data byte 2 of Rx/Tx frame. */
9567 #define CAN_WORD_DATA_BYTE_29(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_29_SHIFT)) & CAN_WORD_DATA_BYTE_29_MASK)
9568 
9569 #define CAN_WORD_DATA_BYTE_33_MASK               (0xFF0000U)
9570 #define CAN_WORD_DATA_BYTE_33_SHIFT              (16U)
9571 /*! DATA_BYTE_33 - Data byte 2 of Rx/Tx frame. */
9572 #define CAN_WORD_DATA_BYTE_33(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_33_SHIFT)) & CAN_WORD_DATA_BYTE_33_MASK)
9573 
9574 #define CAN_WORD_DATA_BYTE_37_MASK               (0xFF0000U)
9575 #define CAN_WORD_DATA_BYTE_37_SHIFT              (16U)
9576 /*! DATA_BYTE_37 - Data byte 2 of Rx/Tx frame. */
9577 #define CAN_WORD_DATA_BYTE_37(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_37_SHIFT)) & CAN_WORD_DATA_BYTE_37_MASK)
9578 
9579 #define CAN_WORD_DATA_BYTE_41_MASK               (0xFF0000U)
9580 #define CAN_WORD_DATA_BYTE_41_SHIFT              (16U)
9581 /*! DATA_BYTE_41 - Data byte 2 of Rx/Tx frame. */
9582 #define CAN_WORD_DATA_BYTE_41(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_41_SHIFT)) & CAN_WORD_DATA_BYTE_41_MASK)
9583 
9584 #define CAN_WORD_DATA_BYTE_45_MASK               (0xFF0000U)
9585 #define CAN_WORD_DATA_BYTE_45_SHIFT              (16U)
9586 /*! DATA_BYTE_45 - Data byte 2 of Rx/Tx frame. */
9587 #define CAN_WORD_DATA_BYTE_45(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_45_SHIFT)) & CAN_WORD_DATA_BYTE_45_MASK)
9588 
9589 #define CAN_WORD_DATA_BYTE_49_MASK               (0xFF0000U)
9590 #define CAN_WORD_DATA_BYTE_49_SHIFT              (16U)
9591 /*! DATA_BYTE_49 - Data byte 2 of Rx/Tx frame. */
9592 #define CAN_WORD_DATA_BYTE_49(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_49_SHIFT)) & CAN_WORD_DATA_BYTE_49_MASK)
9593 
9594 #define CAN_WORD_DATA_BYTE_53_MASK               (0xFF0000U)
9595 #define CAN_WORD_DATA_BYTE_53_SHIFT              (16U)
9596 /*! DATA_BYTE_53 - Data byte 2 of Rx/Tx frame. */
9597 #define CAN_WORD_DATA_BYTE_53(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_53_SHIFT)) & CAN_WORD_DATA_BYTE_53_MASK)
9598 
9599 #define CAN_WORD_DATA_BYTE_57_MASK               (0xFF0000U)
9600 #define CAN_WORD_DATA_BYTE_57_SHIFT              (16U)
9601 /*! DATA_BYTE_57 - Data byte 2 of Rx/Tx frame. */
9602 #define CAN_WORD_DATA_BYTE_57(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_57_SHIFT)) & CAN_WORD_DATA_BYTE_57_MASK)
9603 
9604 #define CAN_WORD_DATA_BYTE_61_MASK               (0xFF0000U)
9605 #define CAN_WORD_DATA_BYTE_61_SHIFT              (16U)
9606 /*! DATA_BYTE_61 - Data byte 2 of Rx/Tx frame. */
9607 #define CAN_WORD_DATA_BYTE_61(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_61_SHIFT)) & CAN_WORD_DATA_BYTE_61_MASK)
9608 
9609 #define CAN_WORD_DATA_BYTE_0_MASK                (0xFF000000U)
9610 #define CAN_WORD_DATA_BYTE_0_SHIFT               (24U)
9611 /*! DATA_BYTE_0 - Data byte 3 of Rx/Tx frame. */
9612 #define CAN_WORD_DATA_BYTE_0(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_0_SHIFT)) & CAN_WORD_DATA_BYTE_0_MASK)
9613 
9614 #define CAN_WORD_DATA_BYTE_4_MASK                (0xFF000000U)
9615 #define CAN_WORD_DATA_BYTE_4_SHIFT               (24U)
9616 /*! DATA_BYTE_4 - Data byte 3 of Rx/Tx frame. */
9617 #define CAN_WORD_DATA_BYTE_4(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_4_SHIFT)) & CAN_WORD_DATA_BYTE_4_MASK)
9618 
9619 #define CAN_WORD_DATA_BYTE_8_MASK                (0xFF000000U)
9620 #define CAN_WORD_DATA_BYTE_8_SHIFT               (24U)
9621 /*! DATA_BYTE_8 - Data byte 3 of Rx/Tx frame. */
9622 #define CAN_WORD_DATA_BYTE_8(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_8_SHIFT)) & CAN_WORD_DATA_BYTE_8_MASK)
9623 
9624 #define CAN_WORD_DATA_BYTE_12_MASK               (0xFF000000U)
9625 #define CAN_WORD_DATA_BYTE_12_SHIFT              (24U)
9626 /*! DATA_BYTE_12 - Data byte 3 of Rx/Tx frame. */
9627 #define CAN_WORD_DATA_BYTE_12(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_12_SHIFT)) & CAN_WORD_DATA_BYTE_12_MASK)
9628 
9629 #define CAN_WORD_DATA_BYTE_16_MASK               (0xFF000000U)
9630 #define CAN_WORD_DATA_BYTE_16_SHIFT              (24U)
9631 /*! DATA_BYTE_16 - Data byte 3 of Rx/Tx frame. */
9632 #define CAN_WORD_DATA_BYTE_16(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_16_SHIFT)) & CAN_WORD_DATA_BYTE_16_MASK)
9633 
9634 #define CAN_WORD_DATA_BYTE_20_MASK               (0xFF000000U)
9635 #define CAN_WORD_DATA_BYTE_20_SHIFT              (24U)
9636 /*! DATA_BYTE_20 - Data byte 3 of Rx/Tx frame. */
9637 #define CAN_WORD_DATA_BYTE_20(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_20_SHIFT)) & CAN_WORD_DATA_BYTE_20_MASK)
9638 
9639 #define CAN_WORD_DATA_BYTE_24_MASK               (0xFF000000U)
9640 #define CAN_WORD_DATA_BYTE_24_SHIFT              (24U)
9641 /*! DATA_BYTE_24 - Data byte 3 of Rx/Tx frame. */
9642 #define CAN_WORD_DATA_BYTE_24(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_24_SHIFT)) & CAN_WORD_DATA_BYTE_24_MASK)
9643 
9644 #define CAN_WORD_DATA_BYTE_28_MASK               (0xFF000000U)
9645 #define CAN_WORD_DATA_BYTE_28_SHIFT              (24U)
9646 /*! DATA_BYTE_28 - Data byte 3 of Rx/Tx frame. */
9647 #define CAN_WORD_DATA_BYTE_28(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_28_SHIFT)) & CAN_WORD_DATA_BYTE_28_MASK)
9648 
9649 #define CAN_WORD_DATA_BYTE_32_MASK               (0xFF000000U)
9650 #define CAN_WORD_DATA_BYTE_32_SHIFT              (24U)
9651 /*! DATA_BYTE_32 - Data byte 3 of Rx/Tx frame. */
9652 #define CAN_WORD_DATA_BYTE_32(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_32_SHIFT)) & CAN_WORD_DATA_BYTE_32_MASK)
9653 
9654 #define CAN_WORD_DATA_BYTE_36_MASK               (0xFF000000U)
9655 #define CAN_WORD_DATA_BYTE_36_SHIFT              (24U)
9656 /*! DATA_BYTE_36 - Data byte 3 of Rx/Tx frame. */
9657 #define CAN_WORD_DATA_BYTE_36(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_36_SHIFT)) & CAN_WORD_DATA_BYTE_36_MASK)
9658 
9659 #define CAN_WORD_DATA_BYTE_40_MASK               (0xFF000000U)
9660 #define CAN_WORD_DATA_BYTE_40_SHIFT              (24U)
9661 /*! DATA_BYTE_40 - Data byte 3 of Rx/Tx frame. */
9662 #define CAN_WORD_DATA_BYTE_40(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_40_SHIFT)) & CAN_WORD_DATA_BYTE_40_MASK)
9663 
9664 #define CAN_WORD_DATA_BYTE_44_MASK               (0xFF000000U)
9665 #define CAN_WORD_DATA_BYTE_44_SHIFT              (24U)
9666 /*! DATA_BYTE_44 - Data byte 3 of Rx/Tx frame. */
9667 #define CAN_WORD_DATA_BYTE_44(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_44_SHIFT)) & CAN_WORD_DATA_BYTE_44_MASK)
9668 
9669 #define CAN_WORD_DATA_BYTE_48_MASK               (0xFF000000U)
9670 #define CAN_WORD_DATA_BYTE_48_SHIFT              (24U)
9671 /*! DATA_BYTE_48 - Data byte 3 of Rx/Tx frame. */
9672 #define CAN_WORD_DATA_BYTE_48(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_48_SHIFT)) & CAN_WORD_DATA_BYTE_48_MASK)
9673 
9674 #define CAN_WORD_DATA_BYTE_52_MASK               (0xFF000000U)
9675 #define CAN_WORD_DATA_BYTE_52_SHIFT              (24U)
9676 /*! DATA_BYTE_52 - Data byte 3 of Rx/Tx frame. */
9677 #define CAN_WORD_DATA_BYTE_52(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_52_SHIFT)) & CAN_WORD_DATA_BYTE_52_MASK)
9678 
9679 #define CAN_WORD_DATA_BYTE_56_MASK               (0xFF000000U)
9680 #define CAN_WORD_DATA_BYTE_56_SHIFT              (24U)
9681 /*! DATA_BYTE_56 - Data byte 3 of Rx/Tx frame. */
9682 #define CAN_WORD_DATA_BYTE_56(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_56_SHIFT)) & CAN_WORD_DATA_BYTE_56_MASK)
9683 
9684 #define CAN_WORD_DATA_BYTE_60_MASK               (0xFF000000U)
9685 #define CAN_WORD_DATA_BYTE_60_SHIFT              (24U)
9686 /*! DATA_BYTE_60 - Data byte 3 of Rx/Tx frame. */
9687 #define CAN_WORD_DATA_BYTE_60(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_60_SHIFT)) & CAN_WORD_DATA_BYTE_60_MASK)
9688 /*! @} */
9689 
9690 /* The count of CAN_WORD */
9691 #define CAN_WORD_COUNT_MB64B                     (7U)
9692 
9693 /* The count of CAN_WORD */
9694 #define CAN_WORD_COUNT_MB64B2                    (16U)
9695 
9696 /* The count of CAN_CS */
9697 #define CAN_CS_COUNT                             (32U)
9698 
9699 /* The count of CAN_ID */
9700 #define CAN_ID_COUNT                             (32U)
9701 
9702 /*! @name WORD0 - Message Buffer 0 WORD0 Register..Message Buffer 31 WORD0 Register */
9703 /*! @{ */
9704 
9705 #define CAN_WORD0_DATA_BYTE_3_MASK               (0xFFU)
9706 #define CAN_WORD0_DATA_BYTE_3_SHIFT              (0U)
9707 /*! DATA_BYTE_3 - Data byte 0 of Rx/Tx frame. */
9708 #define CAN_WORD0_DATA_BYTE_3(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK)
9709 
9710 #define CAN_WORD0_DATA_BYTE_2_MASK               (0xFF00U)
9711 #define CAN_WORD0_DATA_BYTE_2_SHIFT              (8U)
9712 /*! DATA_BYTE_2 - Data byte 1 of Rx/Tx frame. */
9713 #define CAN_WORD0_DATA_BYTE_2(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK)
9714 
9715 #define CAN_WORD0_DATA_BYTE_1_MASK               (0xFF0000U)
9716 #define CAN_WORD0_DATA_BYTE_1_SHIFT              (16U)
9717 /*! DATA_BYTE_1 - Data byte 2 of Rx/Tx frame. */
9718 #define CAN_WORD0_DATA_BYTE_1(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK)
9719 
9720 #define CAN_WORD0_DATA_BYTE_0_MASK               (0xFF000000U)
9721 #define CAN_WORD0_DATA_BYTE_0_SHIFT              (24U)
9722 /*! DATA_BYTE_0 - Data byte 3 of Rx/Tx frame. */
9723 #define CAN_WORD0_DATA_BYTE_0(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK)
9724 /*! @} */
9725 
9726 /* The count of CAN_WORD0 */
9727 #define CAN_WORD0_COUNT                          (32U)
9728 
9729 /*! @name WORD1 - Message Buffer 0 WORD1 Register..Message Buffer 31 WORD1 Register */
9730 /*! @{ */
9731 
9732 #define CAN_WORD1_DATA_BYTE_7_MASK               (0xFFU)
9733 #define CAN_WORD1_DATA_BYTE_7_SHIFT              (0U)
9734 /*! DATA_BYTE_7 - Data byte 0 of Rx/Tx frame. */
9735 #define CAN_WORD1_DATA_BYTE_7(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK)
9736 
9737 #define CAN_WORD1_DATA_BYTE_6_MASK               (0xFF00U)
9738 #define CAN_WORD1_DATA_BYTE_6_SHIFT              (8U)
9739 /*! DATA_BYTE_6 - Data byte 1 of Rx/Tx frame. */
9740 #define CAN_WORD1_DATA_BYTE_6(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK)
9741 
9742 #define CAN_WORD1_DATA_BYTE_5_MASK               (0xFF0000U)
9743 #define CAN_WORD1_DATA_BYTE_5_SHIFT              (16U)
9744 /*! DATA_BYTE_5 - Data byte 2 of Rx/Tx frame. */
9745 #define CAN_WORD1_DATA_BYTE_5(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK)
9746 
9747 #define CAN_WORD1_DATA_BYTE_4_MASK               (0xFF000000U)
9748 #define CAN_WORD1_DATA_BYTE_4_SHIFT              (24U)
9749 /*! DATA_BYTE_4 - Data byte 3 of Rx/Tx frame. */
9750 #define CAN_WORD1_DATA_BYTE_4(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK)
9751 /*! @} */
9752 
9753 /* The count of CAN_WORD1 */
9754 #define CAN_WORD1_COUNT                          (32U)
9755 
9756 /*! @name RXIMR - Receive Individual Mask */
9757 /*! @{ */
9758 
9759 #define CAN_RXIMR_MI_MASK                        (0xFFFFFFFFU)
9760 #define CAN_RXIMR_MI_SHIFT                       (0U)
9761 /*! MI - Individual Mask Bits */
9762 #define CAN_RXIMR_MI(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK)
9763 /*! @} */
9764 
9765 /* The count of CAN_RXIMR */
9766 #define CAN_RXIMR_COUNT                          (32U)
9767 
9768 /*! @name CTRL1_PN - Pretended Networking Control 1 */
9769 /*! @{ */
9770 
9771 #define CAN_CTRL1_PN_FCS_MASK                    (0x3U)
9772 #define CAN_CTRL1_PN_FCS_SHIFT                   (0U)
9773 /*! FCS - Filtering Combination Selection
9774  *  0b00..Message ID filtering only
9775  *  0b01..Message ID filtering and payload filtering
9776  *  0b10..Message ID filtering occurring a specified number of times
9777  *  0b11..Message ID filtering and payload filtering a specified number of times
9778  */
9779 #define CAN_CTRL1_PN_FCS(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_FCS_SHIFT)) & CAN_CTRL1_PN_FCS_MASK)
9780 
9781 #define CAN_CTRL1_PN_IDFS_MASK                   (0xCU)
9782 #define CAN_CTRL1_PN_IDFS_SHIFT                  (2U)
9783 /*! IDFS - ID Filtering Selection
9784  *  0b00..Match ID contents to an exact target value
9785  *  0b01..Match an ID value greater than or equal to a specified target value
9786  *  0b10..Match an ID value smaller than or equal to a specified target value
9787  *  0b11..Match an ID value within a range of values, inclusive
9788  */
9789 #define CAN_CTRL1_PN_IDFS(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_IDFS_SHIFT)) & CAN_CTRL1_PN_IDFS_MASK)
9790 
9791 #define CAN_CTRL1_PN_PLFS_MASK                   (0x30U)
9792 #define CAN_CTRL1_PN_PLFS_SHIFT                  (4U)
9793 /*! PLFS - Payload Filtering Selection
9794  *  0b00..Match payload contents to an exact target value
9795  *  0b01..Match a payload value greater than or equal to a specified target value
9796  *  0b10..Match a payload value smaller than or equal to a specified target value
9797  *  0b11..Match upon a payload value within a range of values, inclusive
9798  */
9799 #define CAN_CTRL1_PN_PLFS(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_PLFS_SHIFT)) & CAN_CTRL1_PN_PLFS_MASK)
9800 
9801 #define CAN_CTRL1_PN_NMATCH_MASK                 (0xFF00U)
9802 #define CAN_CTRL1_PN_NMATCH_SHIFT                (8U)
9803 /*! NMATCH - Number of Messages Matching the Same Filtering Criteria
9804  *  0b00000001..Once
9805  *  0b00000010..Twice
9806  *  0b11111111..255 times
9807  */
9808 #define CAN_CTRL1_PN_NMATCH(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_NMATCH_SHIFT)) & CAN_CTRL1_PN_NMATCH_MASK)
9809 
9810 #define CAN_CTRL1_PN_WUMF_MSK_MASK               (0x10000U)
9811 #define CAN_CTRL1_PN_WUMF_MSK_SHIFT              (16U)
9812 /*! WUMF_MSK - Wake-up by Matching Flag Mask
9813  *  0b0..Disable
9814  *  0b1..Enable
9815  */
9816 #define CAN_CTRL1_PN_WUMF_MSK(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_WUMF_MSK_SHIFT)) & CAN_CTRL1_PN_WUMF_MSK_MASK)
9817 
9818 #define CAN_CTRL1_PN_WTOF_MSK_MASK               (0x20000U)
9819 #define CAN_CTRL1_PN_WTOF_MSK_SHIFT              (17U)
9820 /*! WTOF_MSK - Wake-up by Timeout Flag Mask
9821  *  0b0..Disable
9822  *  0b1..Enable
9823  */
9824 #define CAN_CTRL1_PN_WTOF_MSK(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_WTOF_MSK_SHIFT)) & CAN_CTRL1_PN_WTOF_MSK_MASK)
9825 /*! @} */
9826 
9827 /*! @name CTRL2_PN - Pretended Networking Control 2 */
9828 /*! @{ */
9829 
9830 #define CAN_CTRL2_PN_MATCHTO_MASK                (0xFFFFU)
9831 #define CAN_CTRL2_PN_MATCHTO_SHIFT               (0U)
9832 /*! MATCHTO - Timeout for No Message Matching the Filtering Criteria */
9833 #define CAN_CTRL2_PN_MATCHTO(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_PN_MATCHTO_SHIFT)) & CAN_CTRL2_PN_MATCHTO_MASK)
9834 /*! @} */
9835 
9836 /*! @name WU_MTC - Pretended Networking Wake-Up Match */
9837 /*! @{ */
9838 
9839 #define CAN_WU_MTC_MCOUNTER_MASK                 (0xFF00U)
9840 #define CAN_WU_MTC_MCOUNTER_SHIFT                (8U)
9841 /*! MCOUNTER - Number of Matches in Pretended Networking */
9842 #define CAN_WU_MTC_MCOUNTER(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_WU_MTC_MCOUNTER_SHIFT)) & CAN_WU_MTC_MCOUNTER_MASK)
9843 
9844 #define CAN_WU_MTC_WUMF_MASK                     (0x10000U)
9845 #define CAN_WU_MTC_WUMF_SHIFT                    (16U)
9846 /*! WUMF - Wake-up by Match Flag
9847  *  0b0..No event detected
9848  *  0b1..Event detected
9849  */
9850 #define CAN_WU_MTC_WUMF(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_WU_MTC_WUMF_SHIFT)) & CAN_WU_MTC_WUMF_MASK)
9851 
9852 #define CAN_WU_MTC_WTOF_MASK                     (0x20000U)
9853 #define CAN_WU_MTC_WTOF_SHIFT                    (17U)
9854 /*! WTOF - Wake-up by Timeout Flag Bit
9855  *  0b0..No event detected
9856  *  0b1..Event detected
9857  */
9858 #define CAN_WU_MTC_WTOF(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_WU_MTC_WTOF_SHIFT)) & CAN_WU_MTC_WTOF_MASK)
9859 /*! @} */
9860 
9861 /*! @name FLT_ID1 - Pretended Networking ID Filter 1 */
9862 /*! @{ */
9863 
9864 #define CAN_FLT_ID1_FLT_ID1_MASK                 (0x1FFFFFFFU)
9865 #define CAN_FLT_ID1_FLT_ID1_SHIFT                (0U)
9866 /*! FLT_ID1 - ID Filter 1 for Pretended Networking filtering */
9867 #define CAN_FLT_ID1_FLT_ID1(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID1_FLT_ID1_SHIFT)) & CAN_FLT_ID1_FLT_ID1_MASK)
9868 
9869 #define CAN_FLT_ID1_FLT_RTR_MASK                 (0x20000000U)
9870 #define CAN_FLT_ID1_FLT_RTR_SHIFT                (29U)
9871 /*! FLT_RTR - Remote Transmission Request Filter
9872  *  0b0..Reject remote frame (accept data frame)
9873  *  0b1..Accept remote frame
9874  */
9875 #define CAN_FLT_ID1_FLT_RTR(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID1_FLT_RTR_SHIFT)) & CAN_FLT_ID1_FLT_RTR_MASK)
9876 
9877 #define CAN_FLT_ID1_FLT_IDE_MASK                 (0x40000000U)
9878 #define CAN_FLT_ID1_FLT_IDE_SHIFT                (30U)
9879 /*! FLT_IDE - ID Extended Filter
9880  *  0b0..Standard
9881  *  0b1..Extended
9882  */
9883 #define CAN_FLT_ID1_FLT_IDE(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID1_FLT_IDE_SHIFT)) & CAN_FLT_ID1_FLT_IDE_MASK)
9884 /*! @} */
9885 
9886 /*! @name FLT_DLC - Pretended Networking Data Length Code (DLC) Filter */
9887 /*! @{ */
9888 
9889 #define CAN_FLT_DLC_FLT_DLC_HI_MASK              (0xFU)
9890 #define CAN_FLT_DLC_FLT_DLC_HI_SHIFT             (0U)
9891 /*! FLT_DLC_HI - Upper Limit for Length of Data Bytes Filter */
9892 #define CAN_FLT_DLC_FLT_DLC_HI(x)                (((uint32_t)(((uint32_t)(x)) << CAN_FLT_DLC_FLT_DLC_HI_SHIFT)) & CAN_FLT_DLC_FLT_DLC_HI_MASK)
9893 
9894 #define CAN_FLT_DLC_FLT_DLC_LO_MASK              (0xF0000U)
9895 #define CAN_FLT_DLC_FLT_DLC_LO_SHIFT             (16U)
9896 /*! FLT_DLC_LO - Lower Limit for Length of Data Bytes Filter */
9897 #define CAN_FLT_DLC_FLT_DLC_LO(x)                (((uint32_t)(((uint32_t)(x)) << CAN_FLT_DLC_FLT_DLC_LO_SHIFT)) & CAN_FLT_DLC_FLT_DLC_LO_MASK)
9898 /*! @} */
9899 
9900 /*! @name PL1_LO - Pretended Networking Payload Low Filter 1 */
9901 /*! @{ */
9902 
9903 #define CAN_PL1_LO_Data_byte_3_MASK              (0xFFU)
9904 #define CAN_PL1_LO_Data_byte_3_SHIFT             (0U)
9905 /*! Data_byte_3 - Data byte 3 */
9906 #define CAN_PL1_LO_Data_byte_3(x)                (((uint32_t)(((uint32_t)(x)) << CAN_PL1_LO_Data_byte_3_SHIFT)) & CAN_PL1_LO_Data_byte_3_MASK)
9907 
9908 #define CAN_PL1_LO_Data_byte_2_MASK              (0xFF00U)
9909 #define CAN_PL1_LO_Data_byte_2_SHIFT             (8U)
9910 /*! Data_byte_2 - Data byte 2 */
9911 #define CAN_PL1_LO_Data_byte_2(x)                (((uint32_t)(((uint32_t)(x)) << CAN_PL1_LO_Data_byte_2_SHIFT)) & CAN_PL1_LO_Data_byte_2_MASK)
9912 
9913 #define CAN_PL1_LO_Data_byte_1_MASK              (0xFF0000U)
9914 #define CAN_PL1_LO_Data_byte_1_SHIFT             (16U)
9915 /*! Data_byte_1 - Data byte 1 */
9916 #define CAN_PL1_LO_Data_byte_1(x)                (((uint32_t)(((uint32_t)(x)) << CAN_PL1_LO_Data_byte_1_SHIFT)) & CAN_PL1_LO_Data_byte_1_MASK)
9917 
9918 #define CAN_PL1_LO_Data_byte_0_MASK              (0xFF000000U)
9919 #define CAN_PL1_LO_Data_byte_0_SHIFT             (24U)
9920 /*! Data_byte_0 - Data byte 0 */
9921 #define CAN_PL1_LO_Data_byte_0(x)                (((uint32_t)(((uint32_t)(x)) << CAN_PL1_LO_Data_byte_0_SHIFT)) & CAN_PL1_LO_Data_byte_0_MASK)
9922 /*! @} */
9923 
9924 /*! @name PL1_HI - Pretended Networking Payload High Filter 1 */
9925 /*! @{ */
9926 
9927 #define CAN_PL1_HI_Data_byte_7_MASK              (0xFFU)
9928 #define CAN_PL1_HI_Data_byte_7_SHIFT             (0U)
9929 /*! Data_byte_7 - Data byte 7 */
9930 #define CAN_PL1_HI_Data_byte_7(x)                (((uint32_t)(((uint32_t)(x)) << CAN_PL1_HI_Data_byte_7_SHIFT)) & CAN_PL1_HI_Data_byte_7_MASK)
9931 
9932 #define CAN_PL1_HI_Data_byte_6_MASK              (0xFF00U)
9933 #define CAN_PL1_HI_Data_byte_6_SHIFT             (8U)
9934 /*! Data_byte_6 - Data byte 6 */
9935 #define CAN_PL1_HI_Data_byte_6(x)                (((uint32_t)(((uint32_t)(x)) << CAN_PL1_HI_Data_byte_6_SHIFT)) & CAN_PL1_HI_Data_byte_6_MASK)
9936 
9937 #define CAN_PL1_HI_Data_byte_5_MASK              (0xFF0000U)
9938 #define CAN_PL1_HI_Data_byte_5_SHIFT             (16U)
9939 /*! Data_byte_5 - Data byte 5 */
9940 #define CAN_PL1_HI_Data_byte_5(x)                (((uint32_t)(((uint32_t)(x)) << CAN_PL1_HI_Data_byte_5_SHIFT)) & CAN_PL1_HI_Data_byte_5_MASK)
9941 
9942 #define CAN_PL1_HI_Data_byte_4_MASK              (0xFF000000U)
9943 #define CAN_PL1_HI_Data_byte_4_SHIFT             (24U)
9944 /*! Data_byte_4 - Data byte 4 */
9945 #define CAN_PL1_HI_Data_byte_4(x)                (((uint32_t)(((uint32_t)(x)) << CAN_PL1_HI_Data_byte_4_SHIFT)) & CAN_PL1_HI_Data_byte_4_MASK)
9946 /*! @} */
9947 
9948 /*! @name FLT_ID2_IDMASK - Pretended Networking ID Filter 2 or ID Mask */
9949 /*! @{ */
9950 
9951 #define CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_MASK   (0x1FFFFFFFU)
9952 #define CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_SHIFT  (0U)
9953 /*! FLT_ID2_IDMASK - ID Filter 2 for Pretended Networking Filtering or ID Mask Bits for Pretended Networking ID Filtering */
9954 #define CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK(x)     (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_SHIFT)) & CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_MASK)
9955 
9956 #define CAN_FLT_ID2_IDMASK_RTR_MSK_MASK          (0x20000000U)
9957 #define CAN_FLT_ID2_IDMASK_RTR_MSK_SHIFT         (29U)
9958 /*! RTR_MSK - Remote Transmission Request Mask
9959  *  0b0..The corresponding bit in the filter is "don't care."
9960  *  0b1..The corresponding bit in the filter is checked.
9961  */
9962 #define CAN_FLT_ID2_IDMASK_RTR_MSK(x)            (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID2_IDMASK_RTR_MSK_SHIFT)) & CAN_FLT_ID2_IDMASK_RTR_MSK_MASK)
9963 
9964 #define CAN_FLT_ID2_IDMASK_IDE_MSK_MASK          (0x40000000U)
9965 #define CAN_FLT_ID2_IDMASK_IDE_MSK_SHIFT         (30U)
9966 /*! IDE_MSK - ID Extended Mask
9967  *  0b0..The corresponding bit in the filter is "don't care."
9968  *  0b1..The corresponding bit in the filter is checked.
9969  */
9970 #define CAN_FLT_ID2_IDMASK_IDE_MSK(x)            (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID2_IDMASK_IDE_MSK_SHIFT)) & CAN_FLT_ID2_IDMASK_IDE_MSK_MASK)
9971 /*! @} */
9972 
9973 /*! @name PL2_PLMASK_LO - Pretended Networking Payload Low Filter 2 and Payload Low Mask */
9974 /*! @{ */
9975 
9976 #define CAN_PL2_PLMASK_LO_Data_byte_3_MASK       (0xFFU)
9977 #define CAN_PL2_PLMASK_LO_Data_byte_3_SHIFT      (0U)
9978 /*! Data_byte_3 - Data Byte 3 */
9979 #define CAN_PL2_PLMASK_LO_Data_byte_3(x)         (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_LO_Data_byte_3_SHIFT)) & CAN_PL2_PLMASK_LO_Data_byte_3_MASK)
9980 
9981 #define CAN_PL2_PLMASK_LO_Data_byte_2_MASK       (0xFF00U)
9982 #define CAN_PL2_PLMASK_LO_Data_byte_2_SHIFT      (8U)
9983 /*! Data_byte_2 - Data Byte 2 */
9984 #define CAN_PL2_PLMASK_LO_Data_byte_2(x)         (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_LO_Data_byte_2_SHIFT)) & CAN_PL2_PLMASK_LO_Data_byte_2_MASK)
9985 
9986 #define CAN_PL2_PLMASK_LO_Data_byte_1_MASK       (0xFF0000U)
9987 #define CAN_PL2_PLMASK_LO_Data_byte_1_SHIFT      (16U)
9988 /*! Data_byte_1 - Data Byte 1 */
9989 #define CAN_PL2_PLMASK_LO_Data_byte_1(x)         (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_LO_Data_byte_1_SHIFT)) & CAN_PL2_PLMASK_LO_Data_byte_1_MASK)
9990 
9991 #define CAN_PL2_PLMASK_LO_Data_byte_0_MASK       (0xFF000000U)
9992 #define CAN_PL2_PLMASK_LO_Data_byte_0_SHIFT      (24U)
9993 /*! Data_byte_0 - Data Byte 0 */
9994 #define CAN_PL2_PLMASK_LO_Data_byte_0(x)         (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_LO_Data_byte_0_SHIFT)) & CAN_PL2_PLMASK_LO_Data_byte_0_MASK)
9995 /*! @} */
9996 
9997 /*! @name PL2_PLMASK_HI - Pretended Networking Payload High Filter 2 and Payload High Mask */
9998 /*! @{ */
9999 
10000 #define CAN_PL2_PLMASK_HI_Data_byte_7_MASK       (0xFFU)
10001 #define CAN_PL2_PLMASK_HI_Data_byte_7_SHIFT      (0U)
10002 /*! Data_byte_7 - Data Byte 7 */
10003 #define CAN_PL2_PLMASK_HI_Data_byte_7(x)         (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_HI_Data_byte_7_SHIFT)) & CAN_PL2_PLMASK_HI_Data_byte_7_MASK)
10004 
10005 #define CAN_PL2_PLMASK_HI_Data_byte_6_MASK       (0xFF00U)
10006 #define CAN_PL2_PLMASK_HI_Data_byte_6_SHIFT      (8U)
10007 /*! Data_byte_6 - Data Byte 6 */
10008 #define CAN_PL2_PLMASK_HI_Data_byte_6(x)         (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_HI_Data_byte_6_SHIFT)) & CAN_PL2_PLMASK_HI_Data_byte_6_MASK)
10009 
10010 #define CAN_PL2_PLMASK_HI_Data_byte_5_MASK       (0xFF0000U)
10011 #define CAN_PL2_PLMASK_HI_Data_byte_5_SHIFT      (16U)
10012 /*! Data_byte_5 - Data Byte 5 */
10013 #define CAN_PL2_PLMASK_HI_Data_byte_5(x)         (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_HI_Data_byte_5_SHIFT)) & CAN_PL2_PLMASK_HI_Data_byte_5_MASK)
10014 
10015 #define CAN_PL2_PLMASK_HI_Data_byte_4_MASK       (0xFF000000U)
10016 #define CAN_PL2_PLMASK_HI_Data_byte_4_SHIFT      (24U)
10017 /*! Data_byte_4 - Data Byte 4 */
10018 #define CAN_PL2_PLMASK_HI_Data_byte_4(x)         (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_HI_Data_byte_4_SHIFT)) & CAN_PL2_PLMASK_HI_Data_byte_4_MASK)
10019 /*! @} */
10020 
10021 /*! @name WMB_CS - Wake-Up Message Buffer */
10022 /*! @{ */
10023 
10024 #define CAN_WMB_CS_DLC_MASK                      (0xF0000U)
10025 #define CAN_WMB_CS_DLC_SHIFT                     (16U)
10026 /*! DLC - Length of Data in Bytes */
10027 #define CAN_WMB_CS_DLC(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_WMB_CS_DLC_SHIFT)) & CAN_WMB_CS_DLC_MASK)
10028 
10029 #define CAN_WMB_CS_RTR_MASK                      (0x100000U)
10030 #define CAN_WMB_CS_RTR_SHIFT                     (20U)
10031 /*! RTR - Remote Transmission Request
10032  *  0b0..Data
10033  *  0b1..Remote
10034  */
10035 #define CAN_WMB_CS_RTR(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_WMB_CS_RTR_SHIFT)) & CAN_WMB_CS_RTR_MASK)
10036 
10037 #define CAN_WMB_CS_IDE_MASK                      (0x200000U)
10038 #define CAN_WMB_CS_IDE_SHIFT                     (21U)
10039 /*! IDE - ID Extended Bit
10040  *  0b0..Standard
10041  *  0b1..Extended
10042  */
10043 #define CAN_WMB_CS_IDE(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_WMB_CS_IDE_SHIFT)) & CAN_WMB_CS_IDE_MASK)
10044 
10045 #define CAN_WMB_CS_SRR_MASK                      (0x400000U)
10046 #define CAN_WMB_CS_SRR_SHIFT                     (22U)
10047 /*! SRR - Substitute Remote Request
10048  *  0b0..Dominant
10049  *  0b1..Recessive
10050  */
10051 #define CAN_WMB_CS_SRR(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_WMB_CS_SRR_SHIFT)) & CAN_WMB_CS_SRR_MASK)
10052 /*! @} */
10053 
10054 /* The count of CAN_WMB_CS */
10055 #define CAN_WMB_CS_COUNT                         (4U)
10056 
10057 /*! @name WMB_ID - Wake-Up Message Buffer for ID */
10058 /*! @{ */
10059 
10060 #define CAN_WMB_ID_ID_MASK                       (0x1FFFFFFFU)
10061 #define CAN_WMB_ID_ID_SHIFT                      (0U)
10062 /*! ID - Received ID in Pretended Networking Mode */
10063 #define CAN_WMB_ID_ID(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_WMB_ID_ID_SHIFT)) & CAN_WMB_ID_ID_MASK)
10064 /*! @} */
10065 
10066 /* The count of CAN_WMB_ID */
10067 #define CAN_WMB_ID_COUNT                         (4U)
10068 
10069 /*! @name WMB_D03 - Wake-Up Message Buffer for Data 0-3 */
10070 /*! @{ */
10071 
10072 #define CAN_WMB_D03_Data_byte_3_MASK             (0xFFU)
10073 #define CAN_WMB_D03_Data_byte_3_SHIFT            (0U)
10074 /*! Data_byte_3 - Data Byte 3 */
10075 #define CAN_WMB_D03_Data_byte_3(x)               (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D03_Data_byte_3_SHIFT)) & CAN_WMB_D03_Data_byte_3_MASK)
10076 
10077 #define CAN_WMB_D03_Data_byte_2_MASK             (0xFF00U)
10078 #define CAN_WMB_D03_Data_byte_2_SHIFT            (8U)
10079 /*! Data_byte_2 - Data Byte 2 */
10080 #define CAN_WMB_D03_Data_byte_2(x)               (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D03_Data_byte_2_SHIFT)) & CAN_WMB_D03_Data_byte_2_MASK)
10081 
10082 #define CAN_WMB_D03_Data_byte_1_MASK             (0xFF0000U)
10083 #define CAN_WMB_D03_Data_byte_1_SHIFT            (16U)
10084 /*! Data_byte_1 - Data Byte 1 */
10085 #define CAN_WMB_D03_Data_byte_1(x)               (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D03_Data_byte_1_SHIFT)) & CAN_WMB_D03_Data_byte_1_MASK)
10086 
10087 #define CAN_WMB_D03_Data_byte_0_MASK             (0xFF000000U)
10088 #define CAN_WMB_D03_Data_byte_0_SHIFT            (24U)
10089 /*! Data_byte_0 - Data Byte 0 */
10090 #define CAN_WMB_D03_Data_byte_0(x)               (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D03_Data_byte_0_SHIFT)) & CAN_WMB_D03_Data_byte_0_MASK)
10091 /*! @} */
10092 
10093 /* The count of CAN_WMB_D03 */
10094 #define CAN_WMB_D03_COUNT                        (4U)
10095 
10096 /*! @name WMB_D47 - Wake-Up Message Buffer Register Data 4-7 */
10097 /*! @{ */
10098 
10099 #define CAN_WMB_D47_Data_byte_7_MASK             (0xFFU)
10100 #define CAN_WMB_D47_Data_byte_7_SHIFT            (0U)
10101 /*! Data_byte_7 - Data Byte 7 */
10102 #define CAN_WMB_D47_Data_byte_7(x)               (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D47_Data_byte_7_SHIFT)) & CAN_WMB_D47_Data_byte_7_MASK)
10103 
10104 #define CAN_WMB_D47_Data_byte_6_MASK             (0xFF00U)
10105 #define CAN_WMB_D47_Data_byte_6_SHIFT            (8U)
10106 /*! Data_byte_6 - Data Byte 6 */
10107 #define CAN_WMB_D47_Data_byte_6(x)               (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D47_Data_byte_6_SHIFT)) & CAN_WMB_D47_Data_byte_6_MASK)
10108 
10109 #define CAN_WMB_D47_Data_byte_5_MASK             (0xFF0000U)
10110 #define CAN_WMB_D47_Data_byte_5_SHIFT            (16U)
10111 /*! Data_byte_5 - Data Byte 5 */
10112 #define CAN_WMB_D47_Data_byte_5(x)               (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D47_Data_byte_5_SHIFT)) & CAN_WMB_D47_Data_byte_5_MASK)
10113 
10114 #define CAN_WMB_D47_Data_byte_4_MASK             (0xFF000000U)
10115 #define CAN_WMB_D47_Data_byte_4_SHIFT            (24U)
10116 /*! Data_byte_4 - Data Byte 4 */
10117 #define CAN_WMB_D47_Data_byte_4(x)               (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D47_Data_byte_4_SHIFT)) & CAN_WMB_D47_Data_byte_4_MASK)
10118 /*! @} */
10119 
10120 /* The count of CAN_WMB_D47 */
10121 #define CAN_WMB_D47_COUNT                        (4U)
10122 
10123 /*! @name EPRS - Enhanced CAN Bit Timing Prescalers */
10124 /*! @{ */
10125 
10126 #define CAN_EPRS_ENPRESDIV_MASK                  (0x3FFU)
10127 #define CAN_EPRS_ENPRESDIV_SHIFT                 (0U)
10128 /*! ENPRESDIV - Extended Nominal Prescaler Division Factor */
10129 #define CAN_EPRS_ENPRESDIV(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_EPRS_ENPRESDIV_SHIFT)) & CAN_EPRS_ENPRESDIV_MASK)
10130 
10131 #define CAN_EPRS_EDPRESDIV_MASK                  (0x3FF0000U)
10132 #define CAN_EPRS_EDPRESDIV_SHIFT                 (16U)
10133 /*! EDPRESDIV - Extended Data Phase Prescaler Division Factor */
10134 #define CAN_EPRS_EDPRESDIV(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_EPRS_EDPRESDIV_SHIFT)) & CAN_EPRS_EDPRESDIV_MASK)
10135 /*! @} */
10136 
10137 /*! @name ENCBT - Enhanced Nominal CAN Bit Timing */
10138 /*! @{ */
10139 
10140 #define CAN_ENCBT_NTSEG1_MASK                    (0xFFU)
10141 #define CAN_ENCBT_NTSEG1_SHIFT                   (0U)
10142 /*! NTSEG1 - Nominal Time Segment 1 */
10143 #define CAN_ENCBT_NTSEG1(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ENCBT_NTSEG1_SHIFT)) & CAN_ENCBT_NTSEG1_MASK)
10144 
10145 #define CAN_ENCBT_NTSEG2_MASK                    (0x7F000U)
10146 #define CAN_ENCBT_NTSEG2_SHIFT                   (12U)
10147 /*! NTSEG2 - Nominal Time Segment 2 */
10148 #define CAN_ENCBT_NTSEG2(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ENCBT_NTSEG2_SHIFT)) & CAN_ENCBT_NTSEG2_MASK)
10149 
10150 #define CAN_ENCBT_NRJW_MASK                      (0x1FC00000U)
10151 #define CAN_ENCBT_NRJW_SHIFT                     (22U)
10152 /*! NRJW - Nominal Resynchronization Jump Width */
10153 #define CAN_ENCBT_NRJW(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ENCBT_NRJW_SHIFT)) & CAN_ENCBT_NRJW_MASK)
10154 /*! @} */
10155 
10156 /*! @name EDCBT - Enhanced Data Phase CAN Bit Timing */
10157 /*! @{ */
10158 
10159 #define CAN_EDCBT_DTSEG1_MASK                    (0x1FU)
10160 #define CAN_EDCBT_DTSEG1_SHIFT                   (0U)
10161 /*! DTSEG1 - Data Phase Segment 1 */
10162 #define CAN_EDCBT_DTSEG1(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_EDCBT_DTSEG1_SHIFT)) & CAN_EDCBT_DTSEG1_MASK)
10163 
10164 #define CAN_EDCBT_DTSEG2_MASK                    (0xF000U)
10165 #define CAN_EDCBT_DTSEG2_SHIFT                   (12U)
10166 /*! DTSEG2 - Data Phase Time Segment 2 */
10167 #define CAN_EDCBT_DTSEG2(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_EDCBT_DTSEG2_SHIFT)) & CAN_EDCBT_DTSEG2_MASK)
10168 
10169 #define CAN_EDCBT_DRJW_MASK                      (0x3C00000U)
10170 #define CAN_EDCBT_DRJW_SHIFT                     (22U)
10171 /*! DRJW - Data Phase Resynchronization Jump Width */
10172 #define CAN_EDCBT_DRJW(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_EDCBT_DRJW_SHIFT)) & CAN_EDCBT_DRJW_MASK)
10173 /*! @} */
10174 
10175 /*! @name ETDC - Enhanced Transceiver Delay Compensation */
10176 /*! @{ */
10177 
10178 #define CAN_ETDC_ETDCVAL_MASK                    (0xFFU)
10179 #define CAN_ETDC_ETDCVAL_SHIFT                   (0U)
10180 /*! ETDCVAL - Enhanced Transceiver Delay Compensation Value */
10181 #define CAN_ETDC_ETDCVAL(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_ETDCVAL_SHIFT)) & CAN_ETDC_ETDCVAL_MASK)
10182 
10183 #define CAN_ETDC_ETDCFAIL_MASK                   (0x8000U)
10184 #define CAN_ETDC_ETDCFAIL_SHIFT                  (15U)
10185 /*! ETDCFAIL - Transceiver Delay Compensation Fail
10186  *  0b0..In range
10187  *  0b1..Out of range
10188  */
10189 #define CAN_ETDC_ETDCFAIL(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_ETDCFAIL_SHIFT)) & CAN_ETDC_ETDCFAIL_MASK)
10190 
10191 #define CAN_ETDC_ETDCOFF_MASK                    (0x7F0000U)
10192 #define CAN_ETDC_ETDCOFF_SHIFT                   (16U)
10193 /*! ETDCOFF - Enhanced Transceiver Delay Compensation Offset */
10194 #define CAN_ETDC_ETDCOFF(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_ETDCOFF_SHIFT)) & CAN_ETDC_ETDCOFF_MASK)
10195 
10196 #define CAN_ETDC_TDMDIS_MASK                     (0x40000000U)
10197 #define CAN_ETDC_TDMDIS_SHIFT                    (30U)
10198 /*! TDMDIS - Transceiver Delay Measurement Disable
10199  *  0b0..Enable
10200  *  0b1..Disable
10201  */
10202 #define CAN_ETDC_TDMDIS(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_TDMDIS_SHIFT)) & CAN_ETDC_TDMDIS_MASK)
10203 
10204 #define CAN_ETDC_ETDCEN_MASK                     (0x80000000U)
10205 #define CAN_ETDC_ETDCEN_SHIFT                    (31U)
10206 /*! ETDCEN - Transceiver Delay Compensation Enable
10207  *  0b0..Disable
10208  *  0b1..Enable
10209  */
10210 #define CAN_ETDC_ETDCEN(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_ETDCEN_SHIFT)) & CAN_ETDC_ETDCEN_MASK)
10211 /*! @} */
10212 
10213 /*! @name FDCTRL - CAN FD Control */
10214 /*! @{ */
10215 
10216 #define CAN_FDCTRL_TDCVAL_MASK                   (0x3FU)
10217 #define CAN_FDCTRL_TDCVAL_SHIFT                  (0U)
10218 /*! TDCVAL - Transceiver Delay Compensation Value */
10219 #define CAN_FDCTRL_TDCVAL(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCVAL_SHIFT)) & CAN_FDCTRL_TDCVAL_MASK)
10220 
10221 #define CAN_FDCTRL_TDCOFF_MASK                   (0x1F00U)
10222 #define CAN_FDCTRL_TDCOFF_SHIFT                  (8U)
10223 /*! TDCOFF - Transceiver Delay Compensation Offset */
10224 #define CAN_FDCTRL_TDCOFF(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCOFF_SHIFT)) & CAN_FDCTRL_TDCOFF_MASK)
10225 
10226 #define CAN_FDCTRL_TDCFAIL_MASK                  (0x4000U)
10227 #define CAN_FDCTRL_TDCFAIL_SHIFT                 (14U)
10228 /*! TDCFAIL - Transceiver Delay Compensation Fail
10229  *  0b0..In range
10230  *  0b1..Out of range
10231  */
10232 #define CAN_FDCTRL_TDCFAIL(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCFAIL_SHIFT)) & CAN_FDCTRL_TDCFAIL_MASK)
10233 
10234 #define CAN_FDCTRL_TDCEN_MASK                    (0x8000U)
10235 #define CAN_FDCTRL_TDCEN_SHIFT                   (15U)
10236 /*! TDCEN - Transceiver Delay Compensation Enable
10237  *  0b0..Disable
10238  *  0b1..Enable
10239  */
10240 #define CAN_FDCTRL_TDCEN(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCEN_SHIFT)) & CAN_FDCTRL_TDCEN_MASK)
10241 
10242 #define CAN_FDCTRL_MBDSR0_MASK                   (0x30000U)
10243 #define CAN_FDCTRL_MBDSR0_SHIFT                  (16U)
10244 /*! MBDSR0 - Message Buffer Data Size for Region 0
10245  *  0b00..8 bytes
10246  *  0b01..16 bytes
10247  *  0b10..32 bytes
10248  *  0b11..64 bytes
10249  */
10250 #define CAN_FDCTRL_MBDSR0(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR0_SHIFT)) & CAN_FDCTRL_MBDSR0_MASK)
10251 
10252 #define CAN_FDCTRL_FDRATE_MASK                   (0x80000000U)
10253 #define CAN_FDCTRL_FDRATE_SHIFT                  (31U)
10254 /*! FDRATE - Bit Rate Switch Enable
10255  *  0b0..Disable
10256  *  0b1..Enable
10257  */
10258 #define CAN_FDCTRL_FDRATE(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_FDRATE_SHIFT)) & CAN_FDCTRL_FDRATE_MASK)
10259 /*! @} */
10260 
10261 /*! @name FDCBT - CAN FD Bit Timing */
10262 /*! @{ */
10263 
10264 #define CAN_FDCBT_FPSEG2_MASK                    (0x7U)
10265 #define CAN_FDCBT_FPSEG2_SHIFT                   (0U)
10266 /*! FPSEG2 - Fast Phase Segment 2 */
10267 #define CAN_FDCBT_FPSEG2(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG2_SHIFT)) & CAN_FDCBT_FPSEG2_MASK)
10268 
10269 #define CAN_FDCBT_FPSEG1_MASK                    (0xE0U)
10270 #define CAN_FDCBT_FPSEG1_SHIFT                   (5U)
10271 /*! FPSEG1 - Fast Phase Segment 1 */
10272 #define CAN_FDCBT_FPSEG1(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG1_SHIFT)) & CAN_FDCBT_FPSEG1_MASK)
10273 
10274 #define CAN_FDCBT_FPROPSEG_MASK                  (0x7C00U)
10275 #define CAN_FDCBT_FPROPSEG_SHIFT                 (10U)
10276 /*! FPROPSEG - Fast Propagation Segment */
10277 #define CAN_FDCBT_FPROPSEG(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPROPSEG_SHIFT)) & CAN_FDCBT_FPROPSEG_MASK)
10278 
10279 #define CAN_FDCBT_FRJW_MASK                      (0x70000U)
10280 #define CAN_FDCBT_FRJW_SHIFT                     (16U)
10281 /*! FRJW - Fast Resync Jump Width */
10282 #define CAN_FDCBT_FRJW(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FRJW_SHIFT)) & CAN_FDCBT_FRJW_MASK)
10283 
10284 #define CAN_FDCBT_FPRESDIV_MASK                  (0x3FF00000U)
10285 #define CAN_FDCBT_FPRESDIV_SHIFT                 (20U)
10286 /*! FPRESDIV - Fast Prescaler Division Factor */
10287 #define CAN_FDCBT_FPRESDIV(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPRESDIV_SHIFT)) & CAN_FDCBT_FPRESDIV_MASK)
10288 /*! @} */
10289 
10290 /*! @name FDCRC - CAN FD CRC */
10291 /*! @{ */
10292 
10293 #define CAN_FDCRC_FD_TXCRC_MASK                  (0x1FFFFFU)
10294 #define CAN_FDCRC_FD_TXCRC_SHIFT                 (0U)
10295 /*! FD_TXCRC - Extended Transmitted CRC value */
10296 #define CAN_FDCRC_FD_TXCRC(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_TXCRC_SHIFT)) & CAN_FDCRC_FD_TXCRC_MASK)
10297 
10298 #define CAN_FDCRC_FD_MBCRC_MASK                  (0x7F000000U)
10299 #define CAN_FDCRC_FD_MBCRC_SHIFT                 (24U)
10300 /*! FD_MBCRC - CRC Message Buffer Number for FD_TXCRC */
10301 #define CAN_FDCRC_FD_MBCRC(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_MBCRC_SHIFT)) & CAN_FDCRC_FD_MBCRC_MASK)
10302 /*! @} */
10303 
10304 /*! @name ERFCR - Enhanced RX FIFO Control */
10305 /*! @{ */
10306 
10307 #define CAN_ERFCR_ERFWM_MASK                     (0x1FU)
10308 #define CAN_ERFCR_ERFWM_SHIFT                    (0U)
10309 /*! ERFWM - Enhanced RX FIFO Watermark */
10310 #define CAN_ERFCR_ERFWM(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_ERFWM_SHIFT)) & CAN_ERFCR_ERFWM_MASK)
10311 
10312 #define CAN_ERFCR_NFE_MASK                       (0x3F00U)
10313 #define CAN_ERFCR_NFE_SHIFT                      (8U)
10314 /*! NFE - Number of Enhanced RX FIFO Filter Elements */
10315 #define CAN_ERFCR_NFE(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_NFE_SHIFT)) & CAN_ERFCR_NFE_MASK)
10316 
10317 #define CAN_ERFCR_NEXIF_MASK                     (0x7F0000U)
10318 #define CAN_ERFCR_NEXIF_SHIFT                    (16U)
10319 /*! NEXIF - Number of Extended ID Filter Elements */
10320 #define CAN_ERFCR_NEXIF(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_NEXIF_SHIFT)) & CAN_ERFCR_NEXIF_MASK)
10321 
10322 #define CAN_ERFCR_DMALW_MASK                     (0x7C000000U)
10323 #define CAN_ERFCR_DMALW_SHIFT                    (26U)
10324 /*! DMALW - DMA Last Word */
10325 #define CAN_ERFCR_DMALW(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_DMALW_SHIFT)) & CAN_ERFCR_DMALW_MASK)
10326 
10327 #define CAN_ERFCR_ERFEN_MASK                     (0x80000000U)
10328 #define CAN_ERFCR_ERFEN_SHIFT                    (31U)
10329 /*! ERFEN - Enhanced RX FIFO enable
10330  *  0b0..Disable
10331  *  0b1..Enable
10332  */
10333 #define CAN_ERFCR_ERFEN(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_ERFEN_SHIFT)) & CAN_ERFCR_ERFEN_MASK)
10334 /*! @} */
10335 
10336 /*! @name ERFIER - Enhanced RX FIFO Interrupt Enable */
10337 /*! @{ */
10338 
10339 #define CAN_ERFIER_ERFDAIE_MASK                  (0x10000000U)
10340 #define CAN_ERFIER_ERFDAIE_SHIFT                 (28U)
10341 /*! ERFDAIE - Enhanced RX FIFO Data Available Interrupt Enable
10342  *  0b0..Disable
10343  *  0b1..Enable
10344  */
10345 #define CAN_ERFIER_ERFDAIE(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFDAIE_SHIFT)) & CAN_ERFIER_ERFDAIE_MASK)
10346 
10347 #define CAN_ERFIER_ERFWMIIE_MASK                 (0x20000000U)
10348 #define CAN_ERFIER_ERFWMIIE_SHIFT                (29U)
10349 /*! ERFWMIIE - Enhanced RX FIFO Watermark Indication Interrupt Enable
10350  *  0b0..Disable
10351  *  0b1..Enable
10352  */
10353 #define CAN_ERFIER_ERFWMIIE(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFWMIIE_SHIFT)) & CAN_ERFIER_ERFWMIIE_MASK)
10354 
10355 #define CAN_ERFIER_ERFOVFIE_MASK                 (0x40000000U)
10356 #define CAN_ERFIER_ERFOVFIE_SHIFT                (30U)
10357 /*! ERFOVFIE - Enhanced RX FIFO Overflow Interrupt Enable
10358  *  0b0..Disable
10359  *  0b1..Enable
10360  */
10361 #define CAN_ERFIER_ERFOVFIE(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFOVFIE_SHIFT)) & CAN_ERFIER_ERFOVFIE_MASK)
10362 
10363 #define CAN_ERFIER_ERFUFWIE_MASK                 (0x80000000U)
10364 #define CAN_ERFIER_ERFUFWIE_SHIFT                (31U)
10365 /*! ERFUFWIE - Enhanced RX FIFO Underflow Interrupt Enable
10366  *  0b0..Disable
10367  *  0b1..Enable
10368  */
10369 #define CAN_ERFIER_ERFUFWIE(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFUFWIE_SHIFT)) & CAN_ERFIER_ERFUFWIE_MASK)
10370 /*! @} */
10371 
10372 /*! @name ERFSR - Enhanced RX FIFO Status */
10373 /*! @{ */
10374 
10375 #define CAN_ERFSR_ERFEL_MASK                     (0x3FU)
10376 #define CAN_ERFSR_ERFEL_SHIFT                    (0U)
10377 /*! ERFEL - Enhanced RX FIFO Elements */
10378 #define CAN_ERFSR_ERFEL(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFEL_SHIFT)) & CAN_ERFSR_ERFEL_MASK)
10379 
10380 #define CAN_ERFSR_ERFF_MASK                      (0x10000U)
10381 #define CAN_ERFSR_ERFF_SHIFT                     (16U)
10382 /*! ERFF - Enhanced RX FIFO Full Flag
10383  *  0b0..Not full
10384  *  0b1..Full
10385  */
10386 #define CAN_ERFSR_ERFF(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFF_SHIFT)) & CAN_ERFSR_ERFF_MASK)
10387 
10388 #define CAN_ERFSR_ERFE_MASK                      (0x20000U)
10389 #define CAN_ERFSR_ERFE_SHIFT                     (17U)
10390 /*! ERFE - Enhanced RX FIFO Empty Flag
10391  *  0b0..Not empty
10392  *  0b1..Empty
10393  */
10394 #define CAN_ERFSR_ERFE(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFE_SHIFT)) & CAN_ERFSR_ERFE_MASK)
10395 
10396 #define CAN_ERFSR_ERFCLR_MASK                    (0x8000000U)
10397 #define CAN_ERFSR_ERFCLR_SHIFT                   (27U)
10398 /*! ERFCLR - Enhanced RX FIFO Clear
10399  *  0b0..No effect
10400  *  0b1..Clear enhanced RX FIFO content
10401  */
10402 #define CAN_ERFSR_ERFCLR(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFCLR_SHIFT)) & CAN_ERFSR_ERFCLR_MASK)
10403 
10404 #define CAN_ERFSR_ERFDA_MASK                     (0x10000000U)
10405 #define CAN_ERFSR_ERFDA_SHIFT                    (28U)
10406 /*! ERFDA - Enhanced RX FIFO Data Available Flag
10407  *  0b0..No such occurrence
10408  *  0b1..At least one message stored in Enhanced RX FIFO
10409  */
10410 #define CAN_ERFSR_ERFDA(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFDA_SHIFT)) & CAN_ERFSR_ERFDA_MASK)
10411 
10412 #define CAN_ERFSR_ERFWMI_MASK                    (0x20000000U)
10413 #define CAN_ERFSR_ERFWMI_SHIFT                   (29U)
10414 /*! ERFWMI - Enhanced RX FIFO Watermark Indication Flag
10415  *  0b0..No such occurrence
10416  *  0b1..Number of messages in FIFO is greater than the watermark
10417  */
10418 #define CAN_ERFSR_ERFWMI(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFWMI_SHIFT)) & CAN_ERFSR_ERFWMI_MASK)
10419 
10420 #define CAN_ERFSR_ERFOVF_MASK                    (0x40000000U)
10421 #define CAN_ERFSR_ERFOVF_SHIFT                   (30U)
10422 /*! ERFOVF - Enhanced RX FIFO Overflow Flag
10423  *  0b0..No such occurrence
10424  *  0b1..Overflow
10425  */
10426 #define CAN_ERFSR_ERFOVF(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFOVF_SHIFT)) & CAN_ERFSR_ERFOVF_MASK)
10427 
10428 #define CAN_ERFSR_ERFUFW_MASK                    (0x80000000U)
10429 #define CAN_ERFSR_ERFUFW_SHIFT                   (31U)
10430 /*! ERFUFW - Enhanced RX FIFO Underflow Flag
10431  *  0b0..No such occurrence
10432  *  0b1..Underflow
10433  */
10434 #define CAN_ERFSR_ERFUFW(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFUFW_SHIFT)) & CAN_ERFSR_ERFUFW_MASK)
10435 /*! @} */
10436 
10437 /*! @name ERFFEL - Enhanced RX FIFO Filter Element */
10438 /*! @{ */
10439 
10440 #define CAN_ERFFEL_FEL_MASK                      (0xFFFFFFFFU)
10441 #define CAN_ERFFEL_FEL_SHIFT                     (0U)
10442 /*! FEL - Filter Element Bits */
10443 #define CAN_ERFFEL_FEL(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ERFFEL_FEL_SHIFT)) & CAN_ERFFEL_FEL_MASK)
10444 /*! @} */
10445 
10446 /* The count of CAN_ERFFEL */
10447 #define CAN_ERFFEL_COUNT                         (32U)
10448 
10449 
10450 /*!
10451  * @}
10452  */ /* end of group CAN_Register_Masks */
10453 
10454 
10455 /* CAN - Peripheral instance base addresses */
10456 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
10457   /** Peripheral CAN0 base address */
10458   #define CAN0_BASE                                (0x500D4000u)
10459   /** Peripheral CAN0 base address */
10460   #define CAN0_BASE_NS                             (0x400D4000u)
10461   /** Peripheral CAN0 base pointer */
10462   #define CAN0                                     ((CAN_Type *)CAN0_BASE)
10463   /** Peripheral CAN0 base pointer */
10464   #define CAN0_NS                                  ((CAN_Type *)CAN0_BASE_NS)
10465   /** Array initializer of CAN peripheral base addresses */
10466   #define CAN_BASE_ADDRS                           { CAN0_BASE }
10467   /** Array initializer of CAN peripheral base pointers */
10468   #define CAN_BASE_PTRS                            { CAN0 }
10469   /** Array initializer of CAN peripheral base addresses */
10470   #define CAN_BASE_ADDRS_NS                        { CAN0_BASE_NS }
10471   /** Array initializer of CAN peripheral base pointers */
10472   #define CAN_BASE_PTRS_NS                         { CAN0_NS }
10473 #else
10474   /** Peripheral CAN0 base address */
10475   #define CAN0_BASE                                (0x400D4000u)
10476   /** Peripheral CAN0 base pointer */
10477   #define CAN0                                     ((CAN_Type *)CAN0_BASE)
10478   /** Array initializer of CAN peripheral base addresses */
10479   #define CAN_BASE_ADDRS                           { CAN0_BASE }
10480   /** Array initializer of CAN peripheral base pointers */
10481   #define CAN_BASE_PTRS                            { CAN0 }
10482 #endif
10483 /** Interrupt vectors for the CAN peripheral type */
10484 #define CAN_Rx_Warning_IRQS                      { CAN0_IRQn }
10485 #define CAN_Tx_Warning_IRQS                      { CAN0_IRQn }
10486 #define CAN_Wake_Up_IRQS                         { CAN0_IRQn }
10487 #define CAN_Error_IRQS                           { CAN0_IRQn }
10488 #define CAN_Bus_Off_IRQS                         { CAN0_IRQn }
10489 #define CAN_ORed_Message_buffer_IRQS             { CAN0_IRQn }
10490 
10491 /*!
10492  * @}
10493  */ /* end of group CAN_Peripheral_Access_Layer */
10494 
10495 
10496 /* ----------------------------------------------------------------------------
10497    -- CDOG Peripheral Access Layer
10498    ---------------------------------------------------------------------------- */
10499 
10500 /*!
10501  * @addtogroup CDOG_Peripheral_Access_Layer CDOG Peripheral Access Layer
10502  * @{
10503  */
10504 
10505 /** CDOG - Register Layout Typedef */
10506 typedef struct {
10507   __IO uint32_t CONTROL;                           /**< Control Register, offset: 0x0 */
10508   __IO uint32_t RELOAD;                            /**< Instruction Timer Reload Register, offset: 0x4 */
10509   __I  uint32_t INSTRUCTION_TIMER;                 /**< Instruction Timer Register, offset: 0x8 */
10510        uint8_t RESERVED_0[4];
10511   __I  uint32_t STATUS;                            /**< Status 1 Register, offset: 0x10 */
10512   __I  uint32_t STATUS2;                           /**< Status 2 Register, offset: 0x14 */
10513   __IO uint32_t FLAGS;                             /**< Flags Register, offset: 0x18 */
10514   __IO uint32_t PERSISTENT;                        /**< Persistent Data Storage Register, offset: 0x1C */
10515   __O  uint32_t START;                             /**< START Command Register, offset: 0x20 */
10516   __O  uint32_t STOP;                              /**< STOP Command Register, offset: 0x24 */
10517   __O  uint32_t RESTART;                           /**< RESTART Command Register, offset: 0x28 */
10518   __O  uint32_t ADD;                               /**< ADD Command Register, offset: 0x2C */
10519   __O  uint32_t ADD1;                              /**< ADD1 Command Register, offset: 0x30 */
10520   __O  uint32_t ADD16;                             /**< ADD16 Command Register, offset: 0x34 */
10521   __O  uint32_t ADD256;                            /**< ADD256 Command Register, offset: 0x38 */
10522   __O  uint32_t SUB;                               /**< SUB Command Register, offset: 0x3C */
10523   __O  uint32_t SUB1;                              /**< SUB1 Command Register, offset: 0x40 */
10524   __O  uint32_t SUB16;                             /**< SUB16 Command Register, offset: 0x44 */
10525   __O  uint32_t SUB256;                            /**< SUB256 Command Register, offset: 0x48 */
10526   __O  uint32_t ASSERT16;                          /**< ASSERT16 Command Register, offset: 0x4C */
10527 } CDOG_Type;
10528 
10529 /* ----------------------------------------------------------------------------
10530    -- CDOG Register Masks
10531    ---------------------------------------------------------------------------- */
10532 
10533 /*!
10534  * @addtogroup CDOG_Register_Masks CDOG Register Masks
10535  * @{
10536  */
10537 
10538 /*! @name CONTROL - Control Register */
10539 /*! @{ */
10540 
10541 #define CDOG_CONTROL_LOCK_CTRL_MASK              (0x3U)
10542 #define CDOG_CONTROL_LOCK_CTRL_SHIFT             (0U)
10543 /*! LOCK_CTRL - Lock control
10544  *  0b01..Locked
10545  *  0b10..Unlocked
10546  */
10547 #define CDOG_CONTROL_LOCK_CTRL(x)                (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_LOCK_CTRL_SHIFT)) & CDOG_CONTROL_LOCK_CTRL_MASK)
10548 
10549 #define CDOG_CONTROL_TIMEOUT_CTRL_MASK           (0x1CU)
10550 #define CDOG_CONTROL_TIMEOUT_CTRL_SHIFT          (2U)
10551 /*! TIMEOUT_CTRL - TIMEOUT fault control
10552  *  0b100..Disable both reset and interrupt
10553  *  0b001..Enable reset
10554  *  0b010..Enable interrupt
10555  */
10556 #define CDOG_CONTROL_TIMEOUT_CTRL(x)             (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_TIMEOUT_CTRL_SHIFT)) & CDOG_CONTROL_TIMEOUT_CTRL_MASK)
10557 
10558 #define CDOG_CONTROL_MISCOMPARE_CTRL_MASK        (0xE0U)
10559 #define CDOG_CONTROL_MISCOMPARE_CTRL_SHIFT       (5U)
10560 /*! MISCOMPARE_CTRL - MISCOMPARE fault control
10561  *  0b100..Disable both reset and interrupt
10562  *  0b001..Enable reset
10563  *  0b010..Enable interrupt
10564  */
10565 #define CDOG_CONTROL_MISCOMPARE_CTRL(x)          (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_MISCOMPARE_CTRL_SHIFT)) & CDOG_CONTROL_MISCOMPARE_CTRL_MASK)
10566 
10567 #define CDOG_CONTROL_SEQUENCE_CTRL_MASK          (0x700U)
10568 #define CDOG_CONTROL_SEQUENCE_CTRL_SHIFT         (8U)
10569 /*! SEQUENCE_CTRL - SEQUENCE fault control
10570  *  0b001..Enable reset
10571  *  0b010..Enable interrupt
10572  *  0b100..Disable both reset and interrupt
10573  */
10574 #define CDOG_CONTROL_SEQUENCE_CTRL(x)            (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_SEQUENCE_CTRL_SHIFT)) & CDOG_CONTROL_SEQUENCE_CTRL_MASK)
10575 
10576 #define CDOG_CONTROL_STATE_CTRL_MASK             (0x1C000U)
10577 #define CDOG_CONTROL_STATE_CTRL_SHIFT            (14U)
10578 /*! STATE_CTRL - STATE fault control
10579  *  0b001..Enable reset
10580  *  0b010..Enable interrupt
10581  *  0b100..Disable both reset and interrupt
10582  */
10583 #define CDOG_CONTROL_STATE_CTRL(x)               (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_STATE_CTRL_SHIFT)) & CDOG_CONTROL_STATE_CTRL_MASK)
10584 
10585 #define CDOG_CONTROL_ADDRESS_CTRL_MASK           (0xE0000U)
10586 #define CDOG_CONTROL_ADDRESS_CTRL_SHIFT          (17U)
10587 /*! ADDRESS_CTRL - ADDRESS fault control
10588  *  0b001..Enable reset
10589  *  0b010..Enable interrupt
10590  *  0b100..Disable both reset and interrupt
10591  */
10592 #define CDOG_CONTROL_ADDRESS_CTRL(x)             (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_ADDRESS_CTRL_SHIFT)) & CDOG_CONTROL_ADDRESS_CTRL_MASK)
10593 
10594 #define CDOG_CONTROL_IRQ_PAUSE_MASK              (0x30000000U)
10595 #define CDOG_CONTROL_IRQ_PAUSE_SHIFT             (28U)
10596 /*! IRQ_PAUSE - IRQ pause control
10597  *  0b01..Keep the timer running
10598  *  0b10..Stop the timer
10599  */
10600 #define CDOG_CONTROL_IRQ_PAUSE(x)                (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_IRQ_PAUSE_SHIFT)) & CDOG_CONTROL_IRQ_PAUSE_MASK)
10601 
10602 #define CDOG_CONTROL_DEBUG_HALT_CTRL_MASK        (0xC0000000U)
10603 #define CDOG_CONTROL_DEBUG_HALT_CTRL_SHIFT       (30U)
10604 /*! DEBUG_HALT_CTRL - DEBUG_HALT control
10605  *  0b01..Keep the timer running
10606  *  0b10..Stop the timer
10607  */
10608 #define CDOG_CONTROL_DEBUG_HALT_CTRL(x)          (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_DEBUG_HALT_CTRL_SHIFT)) & CDOG_CONTROL_DEBUG_HALT_CTRL_MASK)
10609 /*! @} */
10610 
10611 /*! @name RELOAD - Instruction Timer Reload Register */
10612 /*! @{ */
10613 
10614 #define CDOG_RELOAD_RLOAD_MASK                   (0xFFFFFFFFU)
10615 #define CDOG_RELOAD_RLOAD_SHIFT                  (0U)
10616 /*! RLOAD - Instruction Timer reload value */
10617 #define CDOG_RELOAD_RLOAD(x)                     (((uint32_t)(((uint32_t)(x)) << CDOG_RELOAD_RLOAD_SHIFT)) & CDOG_RELOAD_RLOAD_MASK)
10618 /*! @} */
10619 
10620 /*! @name INSTRUCTION_TIMER - Instruction Timer Register */
10621 /*! @{ */
10622 
10623 #define CDOG_INSTRUCTION_TIMER_INSTIM_MASK       (0xFFFFFFFFU)
10624 #define CDOG_INSTRUCTION_TIMER_INSTIM_SHIFT      (0U)
10625 /*! INSTIM - Current value of the Instruction Timer */
10626 #define CDOG_INSTRUCTION_TIMER_INSTIM(x)         (((uint32_t)(((uint32_t)(x)) << CDOG_INSTRUCTION_TIMER_INSTIM_SHIFT)) & CDOG_INSTRUCTION_TIMER_INSTIM_MASK)
10627 /*! @} */
10628 
10629 /*! @name STATUS - Status 1 Register */
10630 /*! @{ */
10631 
10632 #define CDOG_STATUS_NUMTOF_MASK                  (0xFFU)
10633 #define CDOG_STATUS_NUMTOF_SHIFT                 (0U)
10634 /*! NUMTOF - Number of TIMEOUT faults since the last POR */
10635 #define CDOG_STATUS_NUMTOF(x)                    (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_NUMTOF_SHIFT)) & CDOG_STATUS_NUMTOF_MASK)
10636 
10637 #define CDOG_STATUS_NUMMISCOMPF_MASK             (0xFF00U)
10638 #define CDOG_STATUS_NUMMISCOMPF_SHIFT            (8U)
10639 /*! NUMMISCOMPF - Number of MISCOMPARE faults since the last POR */
10640 #define CDOG_STATUS_NUMMISCOMPF(x)               (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_NUMMISCOMPF_SHIFT)) & CDOG_STATUS_NUMMISCOMPF_MASK)
10641 
10642 #define CDOG_STATUS_NUMILSEQF_MASK               (0xFF0000U)
10643 #define CDOG_STATUS_NUMILSEQF_SHIFT              (16U)
10644 /*! NUMILSEQF - Number of SEQUENCE faults since the last POR */
10645 #define CDOG_STATUS_NUMILSEQF(x)                 (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_NUMILSEQF_SHIFT)) & CDOG_STATUS_NUMILSEQF_MASK)
10646 
10647 #define CDOG_STATUS_CURST_MASK                   (0xF0000000U)
10648 #define CDOG_STATUS_CURST_SHIFT                  (28U)
10649 /*! CURST - Current State */
10650 #define CDOG_STATUS_CURST(x)                     (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_CURST_SHIFT)) & CDOG_STATUS_CURST_MASK)
10651 /*! @} */
10652 
10653 /*! @name STATUS2 - Status 2 Register */
10654 /*! @{ */
10655 
10656 #define CDOG_STATUS2_NUMCNTF_MASK                (0xFFU)
10657 #define CDOG_STATUS2_NUMCNTF_SHIFT               (0U)
10658 /*! NUMCNTF - Number of CONTROL faults since the last POR */
10659 #define CDOG_STATUS2_NUMCNTF(x)                  (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_NUMCNTF_SHIFT)) & CDOG_STATUS2_NUMCNTF_MASK)
10660 
10661 #define CDOG_STATUS2_NUMILLSTF_MASK              (0xFF00U)
10662 #define CDOG_STATUS2_NUMILLSTF_SHIFT             (8U)
10663 /*! NUMILLSTF - Number of STATE faults since the last POR */
10664 #define CDOG_STATUS2_NUMILLSTF(x)                (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_NUMILLSTF_SHIFT)) & CDOG_STATUS2_NUMILLSTF_MASK)
10665 
10666 #define CDOG_STATUS2_NUMILLA_MASK                (0xFF0000U)
10667 #define CDOG_STATUS2_NUMILLA_SHIFT               (16U)
10668 /*! NUMILLA - Number of ADDRESS faults since the last POR */
10669 #define CDOG_STATUS2_NUMILLA(x)                  (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_NUMILLA_SHIFT)) & CDOG_STATUS2_NUMILLA_MASK)
10670 /*! @} */
10671 
10672 /*! @name FLAGS - Flags Register */
10673 /*! @{ */
10674 
10675 #define CDOG_FLAGS_TO_FLAG_MASK                  (0x1U)
10676 #define CDOG_FLAGS_TO_FLAG_SHIFT                 (0U)
10677 /*! TO_FLAG - TIMEOUT fault flag
10678  *  0b0..A TIMEOUT fault has not occurred
10679  *  0b1..A TIMEOUT fault has occurred
10680  */
10681 #define CDOG_FLAGS_TO_FLAG(x)                    (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_TO_FLAG_SHIFT)) & CDOG_FLAGS_TO_FLAG_MASK)
10682 
10683 #define CDOG_FLAGS_MISCOM_FLAG_MASK              (0x2U)
10684 #define CDOG_FLAGS_MISCOM_FLAG_SHIFT             (1U)
10685 /*! MISCOM_FLAG - MISCOMPARE fault flag
10686  *  0b0..A MISCOMPARE fault has not occurred
10687  *  0b1..A MISCOMPARE fault has occurred
10688  */
10689 #define CDOG_FLAGS_MISCOM_FLAG(x)                (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_MISCOM_FLAG_SHIFT)) & CDOG_FLAGS_MISCOM_FLAG_MASK)
10690 
10691 #define CDOG_FLAGS_SEQ_FLAG_MASK                 (0x4U)
10692 #define CDOG_FLAGS_SEQ_FLAG_SHIFT                (2U)
10693 /*! SEQ_FLAG - SEQUENCE fault flag
10694  *  0b0..A SEQUENCE fault has not occurred
10695  *  0b1..A SEQUENCE fault has occurred
10696  */
10697 #define CDOG_FLAGS_SEQ_FLAG(x)                   (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_SEQ_FLAG_SHIFT)) & CDOG_FLAGS_SEQ_FLAG_MASK)
10698 
10699 #define CDOG_FLAGS_CNT_FLAG_MASK                 (0x8U)
10700 #define CDOG_FLAGS_CNT_FLAG_SHIFT                (3U)
10701 /*! CNT_FLAG - CONTROL fault flag
10702  *  0b0..A CONTROL fault has not occurred
10703  *  0b1..A CONTROL fault has occurred
10704  */
10705 #define CDOG_FLAGS_CNT_FLAG(x)                   (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_CNT_FLAG_SHIFT)) & CDOG_FLAGS_CNT_FLAG_MASK)
10706 
10707 #define CDOG_FLAGS_STATE_FLAG_MASK               (0x10U)
10708 #define CDOG_FLAGS_STATE_FLAG_SHIFT              (4U)
10709 /*! STATE_FLAG - STATE fault flag
10710  *  0b0..A STATE fault has not occurred
10711  *  0b1..A STATE fault has occurred
10712  */
10713 #define CDOG_FLAGS_STATE_FLAG(x)                 (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_STATE_FLAG_SHIFT)) & CDOG_FLAGS_STATE_FLAG_MASK)
10714 
10715 #define CDOG_FLAGS_ADDR_FLAG_MASK                (0x20U)
10716 #define CDOG_FLAGS_ADDR_FLAG_SHIFT               (5U)
10717 /*! ADDR_FLAG - ADDRESS fault flag
10718  *  0b0..An ADDRESS fault has not occurred
10719  *  0b1..An ADDRESS fault has occurred
10720  */
10721 #define CDOG_FLAGS_ADDR_FLAG(x)                  (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_ADDR_FLAG_SHIFT)) & CDOG_FLAGS_ADDR_FLAG_MASK)
10722 
10723 #define CDOG_FLAGS_POR_FLAG_MASK                 (0x10000U)
10724 #define CDOG_FLAGS_POR_FLAG_SHIFT                (16U)
10725 /*! POR_FLAG - Power-on reset flag
10726  *  0b0..A Power-on reset event has not occurred
10727  *  0b1..A Power-on reset event has occurred
10728  */
10729 #define CDOG_FLAGS_POR_FLAG(x)                   (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_POR_FLAG_SHIFT)) & CDOG_FLAGS_POR_FLAG_MASK)
10730 /*! @} */
10731 
10732 /*! @name PERSISTENT - Persistent Data Storage Register */
10733 /*! @{ */
10734 
10735 #define CDOG_PERSISTENT_PERSIS_MASK              (0xFFFFFFFFU)
10736 #define CDOG_PERSISTENT_PERSIS_SHIFT             (0U)
10737 /*! PERSIS - Persistent Storage */
10738 #define CDOG_PERSISTENT_PERSIS(x)                (((uint32_t)(((uint32_t)(x)) << CDOG_PERSISTENT_PERSIS_SHIFT)) & CDOG_PERSISTENT_PERSIS_MASK)
10739 /*! @} */
10740 
10741 /*! @name START - START Command Register */
10742 /*! @{ */
10743 
10744 #define CDOG_START_STRT_MASK                     (0xFFFFFFFFU)
10745 #define CDOG_START_STRT_SHIFT                    (0U)
10746 /*! STRT - Start command */
10747 #define CDOG_START_STRT(x)                       (((uint32_t)(((uint32_t)(x)) << CDOG_START_STRT_SHIFT)) & CDOG_START_STRT_MASK)
10748 /*! @} */
10749 
10750 /*! @name STOP - STOP Command Register */
10751 /*! @{ */
10752 
10753 #define CDOG_STOP_STP_MASK                       (0xFFFFFFFFU)
10754 #define CDOG_STOP_STP_SHIFT                      (0U)
10755 /*! STP - Stop command */
10756 #define CDOG_STOP_STP(x)                         (((uint32_t)(((uint32_t)(x)) << CDOG_STOP_STP_SHIFT)) & CDOG_STOP_STP_MASK)
10757 /*! @} */
10758 
10759 /*! @name RESTART - RESTART Command Register */
10760 /*! @{ */
10761 
10762 #define CDOG_RESTART_RSTRT_MASK                  (0xFFFFFFFFU)
10763 #define CDOG_RESTART_RSTRT_SHIFT                 (0U)
10764 /*! RSTRT - Restart command */
10765 #define CDOG_RESTART_RSTRT(x)                    (((uint32_t)(((uint32_t)(x)) << CDOG_RESTART_RSTRT_SHIFT)) & CDOG_RESTART_RSTRT_MASK)
10766 /*! @} */
10767 
10768 /*! @name ADD - ADD Command Register */
10769 /*! @{ */
10770 
10771 #define CDOG_ADD_AD_MASK                         (0xFFFFFFFFU)
10772 #define CDOG_ADD_AD_SHIFT                        (0U)
10773 /*! AD - ADD Write Value */
10774 #define CDOG_ADD_AD(x)                           (((uint32_t)(((uint32_t)(x)) << CDOG_ADD_AD_SHIFT)) & CDOG_ADD_AD_MASK)
10775 /*! @} */
10776 
10777 /*! @name ADD1 - ADD1 Command Register */
10778 /*! @{ */
10779 
10780 #define CDOG_ADD1_AD1_MASK                       (0xFFFFFFFFU)
10781 #define CDOG_ADD1_AD1_SHIFT                      (0U)
10782 /*! AD1 - ADD 1 */
10783 #define CDOG_ADD1_AD1(x)                         (((uint32_t)(((uint32_t)(x)) << CDOG_ADD1_AD1_SHIFT)) & CDOG_ADD1_AD1_MASK)
10784 /*! @} */
10785 
10786 /*! @name ADD16 - ADD16 Command Register */
10787 /*! @{ */
10788 
10789 #define CDOG_ADD16_AD16_MASK                     (0xFFFFFFFFU)
10790 #define CDOG_ADD16_AD16_SHIFT                    (0U)
10791 /*! AD16 - ADD 16 */
10792 #define CDOG_ADD16_AD16(x)                       (((uint32_t)(((uint32_t)(x)) << CDOG_ADD16_AD16_SHIFT)) & CDOG_ADD16_AD16_MASK)
10793 /*! @} */
10794 
10795 /*! @name ADD256 - ADD256 Command Register */
10796 /*! @{ */
10797 
10798 #define CDOG_ADD256_AD256_MASK                   (0xFFFFFFFFU)
10799 #define CDOG_ADD256_AD256_SHIFT                  (0U)
10800 /*! AD256 - ADD 256 */
10801 #define CDOG_ADD256_AD256(x)                     (((uint32_t)(((uint32_t)(x)) << CDOG_ADD256_AD256_SHIFT)) & CDOG_ADD256_AD256_MASK)
10802 /*! @} */
10803 
10804 /*! @name SUB - SUB Command Register */
10805 /*! @{ */
10806 
10807 #define CDOG_SUB_SB_MASK                         (0xFFFFFFFFU)
10808 #define CDOG_SUB_SB_SHIFT                        (0U)
10809 /*! SB - Subtract Write Value */
10810 #define CDOG_SUB_SB(x)                           (((uint32_t)(((uint32_t)(x)) << CDOG_SUB_SB_SHIFT)) & CDOG_SUB_SB_MASK)
10811 /*! @} */
10812 
10813 /*! @name SUB1 - SUB1 Command Register */
10814 /*! @{ */
10815 
10816 #define CDOG_SUB1_SB1_MASK                       (0xFFFFFFFFU)
10817 #define CDOG_SUB1_SB1_SHIFT                      (0U)
10818 /*! SB1 - Subtract 1 */
10819 #define CDOG_SUB1_SB1(x)                         (((uint32_t)(((uint32_t)(x)) << CDOG_SUB1_SB1_SHIFT)) & CDOG_SUB1_SB1_MASK)
10820 /*! @} */
10821 
10822 /*! @name SUB16 - SUB16 Command Register */
10823 /*! @{ */
10824 
10825 #define CDOG_SUB16_SB16_MASK                     (0xFFFFFFFFU)
10826 #define CDOG_SUB16_SB16_SHIFT                    (0U)
10827 /*! SB16 - Subtract 16 */
10828 #define CDOG_SUB16_SB16(x)                       (((uint32_t)(((uint32_t)(x)) << CDOG_SUB16_SB16_SHIFT)) & CDOG_SUB16_SB16_MASK)
10829 /*! @} */
10830 
10831 /*! @name SUB256 - SUB256 Command Register */
10832 /*! @{ */
10833 
10834 #define CDOG_SUB256_SB256_MASK                   (0xFFFFFFFFU)
10835 #define CDOG_SUB256_SB256_SHIFT                  (0U)
10836 /*! SB256 - Subtract 256 */
10837 #define CDOG_SUB256_SB256(x)                     (((uint32_t)(((uint32_t)(x)) << CDOG_SUB256_SB256_SHIFT)) & CDOG_SUB256_SB256_MASK)
10838 /*! @} */
10839 
10840 /*! @name ASSERT16 - ASSERT16 Command Register */
10841 /*! @{ */
10842 
10843 #define CDOG_ASSERT16_AST16_MASK                 (0xFFFFFFFFU)
10844 #define CDOG_ASSERT16_AST16_SHIFT                (0U)
10845 /*! AST16 - ASSERT16 Command */
10846 #define CDOG_ASSERT16_AST16(x)                   (((uint32_t)(((uint32_t)(x)) << CDOG_ASSERT16_AST16_SHIFT)) & CDOG_ASSERT16_AST16_MASK)
10847 /*! @} */
10848 
10849 
10850 /*!
10851  * @}
10852  */ /* end of group CDOG_Register_Masks */
10853 
10854 
10855 /* CDOG - Peripheral instance base addresses */
10856 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
10857   /** Peripheral CDOG0 base address */
10858   #define CDOG0_BASE                               (0x500BB000u)
10859   /** Peripheral CDOG0 base address */
10860   #define CDOG0_BASE_NS                            (0x400BB000u)
10861   /** Peripheral CDOG0 base pointer */
10862   #define CDOG0                                    ((CDOG_Type *)CDOG0_BASE)
10863   /** Peripheral CDOG0 base pointer */
10864   #define CDOG0_NS                                 ((CDOG_Type *)CDOG0_BASE_NS)
10865   /** Peripheral CDOG1 base address */
10866   #define CDOG1_BASE                               (0x500BC000u)
10867   /** Peripheral CDOG1 base address */
10868   #define CDOG1_BASE_NS                            (0x400BC000u)
10869   /** Peripheral CDOG1 base pointer */
10870   #define CDOG1                                    ((CDOG_Type *)CDOG1_BASE)
10871   /** Peripheral CDOG1 base pointer */
10872   #define CDOG1_NS                                 ((CDOG_Type *)CDOG1_BASE_NS)
10873   /** Array initializer of CDOG peripheral base addresses */
10874   #define CDOG_BASE_ADDRS                          { CDOG0_BASE, CDOG1_BASE }
10875   /** Array initializer of CDOG peripheral base pointers */
10876   #define CDOG_BASE_PTRS                           { CDOG0, CDOG1 }
10877   /** Array initializer of CDOG peripheral base addresses */
10878   #define CDOG_BASE_ADDRS_NS                       { CDOG0_BASE_NS, CDOG1_BASE_NS }
10879   /** Array initializer of CDOG peripheral base pointers */
10880   #define CDOG_BASE_PTRS_NS                        { CDOG0_NS, CDOG1_NS }
10881 #else
10882   /** Peripheral CDOG0 base address */
10883   #define CDOG0_BASE                               (0x400BB000u)
10884   /** Peripheral CDOG0 base pointer */
10885   #define CDOG0                                    ((CDOG_Type *)CDOG0_BASE)
10886   /** Peripheral CDOG1 base address */
10887   #define CDOG1_BASE                               (0x400BC000u)
10888   /** Peripheral CDOG1 base pointer */
10889   #define CDOG1                                    ((CDOG_Type *)CDOG1_BASE)
10890   /** Array initializer of CDOG peripheral base addresses */
10891   #define CDOG_BASE_ADDRS                          { CDOG0_BASE, CDOG1_BASE }
10892   /** Array initializer of CDOG peripheral base pointers */
10893   #define CDOG_BASE_PTRS                           { CDOG0, CDOG1 }
10894 #endif
10895 /** Interrupt vectors for the CDOG peripheral type */
10896 #define CDOG_IRQS                                { CDOG0_IRQn, CDOG1_IRQn }
10897 
10898 /*!
10899  * @}
10900  */ /* end of group CDOG_Peripheral_Access_Layer */
10901 
10902 
10903 /* ----------------------------------------------------------------------------
10904    -- CMC Peripheral Access Layer
10905    ---------------------------------------------------------------------------- */
10906 
10907 /*!
10908  * @addtogroup CMC_Peripheral_Access_Layer CMC Peripheral Access Layer
10909  * @{
10910  */
10911 
10912 /** CMC - Register Layout Typedef */
10913 typedef struct {
10914   __I  uint32_t VERID;                             /**< Version ID, offset: 0x0 */
10915        uint8_t RESERVED_0[12];
10916   __IO uint32_t CKCTRL;                            /**< Clock Control, offset: 0x10 */
10917   __IO uint32_t CKSTAT;                            /**< Clock Status, offset: 0x14 */
10918   __IO uint32_t PMPROT;                            /**< Power Mode Protection, offset: 0x18 */
10919   __O  uint32_t GPMCTRL;                           /**< Global Power Mode Control, offset: 0x1C */
10920   __IO uint32_t PMCTRL[2];                         /**< Power Mode Control, array offset: 0x20, array step: 0x4 */
10921        uint8_t RESERVED_1[88];
10922   __I  uint32_t SRS;                               /**< System Reset Status, offset: 0x80 */
10923   __IO uint32_t RPC;                               /**< Reset Pin Control, offset: 0x84 */
10924   __IO uint32_t SSRS;                              /**< Sticky System Reset Status, offset: 0x88 */
10925   __IO uint32_t SRIE;                              /**< System Reset Interrupt Enable, offset: 0x8C */
10926   __IO uint32_t SRIF;                              /**< System Reset Interrupt Flag, offset: 0x90 */
10927        uint8_t RESERVED_2[8];
10928   __I  uint32_t RSTCNT;                            /**< Reset Count Register, offset: 0x9C */
10929   __IO uint32_t MR[1];                             /**< Mode, array offset: 0xA0, array step: 0x4 */
10930        uint8_t RESERVED_3[12];
10931   __IO uint32_t FM[1];                             /**< Force Mode, array offset: 0xB0, array step: 0x4 */
10932        uint8_t RESERVED_4[12];
10933   __IO uint32_t SRAMDIS[1];                        /**< SRAM Disable, array offset: 0xC0, array step: 0x4 */
10934        uint8_t RESERVED_5[12];
10935   __IO uint32_t SRAMRET[1];                        /**< SRAM Retention, array offset: 0xD0, array step: 0x4 */
10936        uint8_t RESERVED_6[12];
10937   __IO uint32_t FLASHCR;                           /**< Flash Control, offset: 0xE0 */
10938        uint8_t RESERVED_7[28];
10939   __IO uint32_t BSR;                               /**< BootROM Status Register, offset: 0x100 */
10940        uint8_t RESERVED_8[8];
10941   __IO uint32_t BLR;                               /**< BootROM Lock Register, offset: 0x10C */
10942   __IO uint32_t CORECTL;                           /**< Core Control, offset: 0x110 */
10943        uint8_t RESERVED_9[12];
10944   __IO uint32_t DBGCTL;                            /**< Debug Control, offset: 0x120 */
10945 } CMC_Type;
10946 
10947 /* ----------------------------------------------------------------------------
10948    -- CMC Register Masks
10949    ---------------------------------------------------------------------------- */
10950 
10951 /*!
10952  * @addtogroup CMC_Register_Masks CMC Register Masks
10953  * @{
10954  */
10955 
10956 /*! @name VERID - Version ID */
10957 /*! @{ */
10958 
10959 #define CMC_VERID_FEATURE_MASK                   (0xFFFFU)
10960 #define CMC_VERID_FEATURE_SHIFT                  (0U)
10961 /*! FEATURE - Feature Specification Number */
10962 #define CMC_VERID_FEATURE(x)                     (((uint32_t)(((uint32_t)(x)) << CMC_VERID_FEATURE_SHIFT)) & CMC_VERID_FEATURE_MASK)
10963 
10964 #define CMC_VERID_MINOR_MASK                     (0xFF0000U)
10965 #define CMC_VERID_MINOR_SHIFT                    (16U)
10966 /*! MINOR - Minor Version Number */
10967 #define CMC_VERID_MINOR(x)                       (((uint32_t)(((uint32_t)(x)) << CMC_VERID_MINOR_SHIFT)) & CMC_VERID_MINOR_MASK)
10968 
10969 #define CMC_VERID_MAJOR_MASK                     (0xFF000000U)
10970 #define CMC_VERID_MAJOR_SHIFT                    (24U)
10971 /*! MAJOR - Major Version Number */
10972 #define CMC_VERID_MAJOR(x)                       (((uint32_t)(((uint32_t)(x)) << CMC_VERID_MAJOR_SHIFT)) & CMC_VERID_MAJOR_MASK)
10973 /*! @} */
10974 
10975 /*! @name CKCTRL - Clock Control */
10976 /*! @{ */
10977 
10978 #define CMC_CKCTRL_CKMODE_MASK                   (0xFU)
10979 #define CMC_CKCTRL_CKMODE_SHIFT                  (0U)
10980 /*! CKMODE - Clocking Mode
10981  *  0b0000..No clock gating
10982  *  0b0001..Core clock is gated
10983  *  0b1111..Core, platform, and peripheral clocks are gated, and core enters Low-Power mode.
10984  */
10985 #define CMC_CKCTRL_CKMODE(x)                     (((uint32_t)(((uint32_t)(x)) << CMC_CKCTRL_CKMODE_SHIFT)) & CMC_CKCTRL_CKMODE_MASK)
10986 
10987 #define CMC_CKCTRL_LOCK_MASK                     (0x80000000U)
10988 #define CMC_CKCTRL_LOCK_SHIFT                    (31U)
10989 /*! LOCK - Lock
10990  *  0b0..Allowed
10991  *  0b1..Blocked
10992  */
10993 #define CMC_CKCTRL_LOCK(x)                       (((uint32_t)(((uint32_t)(x)) << CMC_CKCTRL_LOCK_SHIFT)) & CMC_CKCTRL_LOCK_MASK)
10994 /*! @} */
10995 
10996 /*! @name CKSTAT - Clock Status */
10997 /*! @{ */
10998 
10999 #define CMC_CKSTAT_CKMODE_MASK                   (0xFU)
11000 #define CMC_CKSTAT_CKMODE_SHIFT                  (0U)
11001 /*! CKMODE - Low Power Status
11002  *  0b0000..Core clock not gated
11003  *  0b0001..Core clock was gated
11004  *  0b1111..Core, platform, and peripheral clocks were gated, and power domain entered Low-Power mode
11005  *  *..
11006  */
11007 #define CMC_CKSTAT_CKMODE(x)                     (((uint32_t)(((uint32_t)(x)) << CMC_CKSTAT_CKMODE_SHIFT)) & CMC_CKSTAT_CKMODE_MASK)
11008 
11009 #define CMC_CKSTAT_WAKEUP_MASK                   (0xFF00U)
11010 #define CMC_CKSTAT_WAKEUP_SHIFT                  (8U)
11011 /*! WAKEUP - Wake-up Source */
11012 #define CMC_CKSTAT_WAKEUP(x)                     (((uint32_t)(((uint32_t)(x)) << CMC_CKSTAT_WAKEUP_SHIFT)) & CMC_CKSTAT_WAKEUP_MASK)
11013 
11014 #define CMC_CKSTAT_VALID_MASK                    (0x80000000U)
11015 #define CMC_CKSTAT_VALID_SHIFT                   (31U)
11016 /*! VALID - Clock Status Valid
11017  *  0b0..Core clock not gated
11018  *  0b1..Core clock was gated due to Low-Power mode entry
11019  */
11020 #define CMC_CKSTAT_VALID(x)                      (((uint32_t)(((uint32_t)(x)) << CMC_CKSTAT_VALID_SHIFT)) & CMC_CKSTAT_VALID_MASK)
11021 /*! @} */
11022 
11023 /*! @name PMPROT - Power Mode Protection */
11024 /*! @{ */
11025 
11026 #define CMC_PMPROT_LPMODE_MASK                   (0xFU)
11027 #define CMC_PMPROT_LPMODE_SHIFT                  (0U)
11028 /*! LPMODE - Low-Power Mode
11029  *  0b0000..Not allowed
11030  *  0b0001..Allowed
11031  *  0b0010..Allowed
11032  *  0b0011..Allowed
11033  *  0b0100..Allowed
11034  *  0b0101..Allowed
11035  *  0b0110..Allowed
11036  *  0b0111..Allowed
11037  *  0b1000..Allowed
11038  *  0b1001..Allowed
11039  *  0b1010..Allowed
11040  *  0b1011..Allowed
11041  *  0b1100..Allowed
11042  *  0b1101..Allowed
11043  *  0b1110..Allowed
11044  *  0b1111..Allowed
11045  */
11046 #define CMC_PMPROT_LPMODE(x)                     (((uint32_t)(((uint32_t)(x)) << CMC_PMPROT_LPMODE_SHIFT)) & CMC_PMPROT_LPMODE_MASK)
11047 
11048 #define CMC_PMPROT_LOCK_MASK                     (0x80000000U)
11049 #define CMC_PMPROT_LOCK_SHIFT                    (31U)
11050 /*! LOCK - Lock Register
11051  *  0b0..Allowed
11052  *  0b1..Blocked
11053  */
11054 #define CMC_PMPROT_LOCK(x)                       (((uint32_t)(((uint32_t)(x)) << CMC_PMPROT_LOCK_SHIFT)) & CMC_PMPROT_LOCK_MASK)
11055 /*! @} */
11056 
11057 /*! @name GPMCTRL - Global Power Mode Control */
11058 /*! @{ */
11059 
11060 #define CMC_GPMCTRL_LPMODE_MASK                  (0xFU)
11061 #define CMC_GPMCTRL_LPMODE_SHIFT                 (0U)
11062 /*! LPMODE - Low-Power Mode */
11063 #define CMC_GPMCTRL_LPMODE(x)                    (((uint32_t)(((uint32_t)(x)) << CMC_GPMCTRL_LPMODE_SHIFT)) & CMC_GPMCTRL_LPMODE_MASK)
11064 /*! @} */
11065 
11066 /*! @name PMCTRL - Power Mode Control */
11067 /*! @{ */
11068 
11069 #define CMC_PMCTRL_LPMODE_MASK                   (0xFU)
11070 #define CMC_PMCTRL_LPMODE_SHIFT                  (0U)
11071 /*! LPMODE - Low-Power Mode
11072  *  0b0000..Active/Sleep
11073  *  0b0001..Deep Sleep
11074  *  0b0011..Power Down
11075  *  0b0111..Reserved
11076  *  0b1111..Deep-Power Down
11077  */
11078 #define CMC_PMCTRL_LPMODE(x)                     (((uint32_t)(((uint32_t)(x)) << CMC_PMCTRL_LPMODE_SHIFT)) & CMC_PMCTRL_LPMODE_MASK)
11079 /*! @} */
11080 
11081 /* The count of CMC_PMCTRL */
11082 #define CMC_PMCTRL_COUNT                         (2U)
11083 
11084 /*! @name SRS - System Reset Status */
11085 /*! @{ */
11086 
11087 #define CMC_SRS_WAKEUP_MASK                      (0x1U)
11088 #define CMC_SRS_WAKEUP_SHIFT                     (0U)
11089 /*! WAKEUP - Wake-up Reset
11090  *  0b0..Reset not generated
11091  *  0b1..Reset generated
11092  */
11093 #define CMC_SRS_WAKEUP(x)                        (((uint32_t)(((uint32_t)(x)) << CMC_SRS_WAKEUP_SHIFT)) & CMC_SRS_WAKEUP_MASK)
11094 
11095 #define CMC_SRS_POR_MASK                         (0x2U)
11096 #define CMC_SRS_POR_SHIFT                        (1U)
11097 /*! POR - Power-on Reset
11098  *  0b0..Reset not generated
11099  *  0b1..Reset generated
11100  */
11101 #define CMC_SRS_POR(x)                           (((uint32_t)(((uint32_t)(x)) << CMC_SRS_POR_SHIFT)) & CMC_SRS_POR_MASK)
11102 
11103 #define CMC_SRS_VD_MASK                          (0x4U)
11104 #define CMC_SRS_VD_SHIFT                         (2U)
11105 /*! VD - Voltage Detect Reset
11106  *  0b0..Reset not generated
11107  *  0b1..Reset generated
11108  */
11109 #define CMC_SRS_VD(x)                            (((uint32_t)(((uint32_t)(x)) << CMC_SRS_VD_SHIFT)) & CMC_SRS_VD_MASK)
11110 
11111 #define CMC_SRS_WARM_MASK                        (0x10U)
11112 #define CMC_SRS_WARM_SHIFT                       (4U)
11113 /*! WARM - Warm Reset
11114  *  0b0..Reset not generated
11115  *  0b1..Reset generated
11116  */
11117 #define CMC_SRS_WARM(x)                          (((uint32_t)(((uint32_t)(x)) << CMC_SRS_WARM_SHIFT)) & CMC_SRS_WARM_MASK)
11118 
11119 #define CMC_SRS_FATAL_MASK                       (0x20U)
11120 #define CMC_SRS_FATAL_SHIFT                      (5U)
11121 /*! FATAL - Fatal Reset
11122  *  0b0..Reset was not generated
11123  *  0b1..Reset was generated
11124  */
11125 #define CMC_SRS_FATAL(x)                         (((uint32_t)(((uint32_t)(x)) << CMC_SRS_FATAL_SHIFT)) & CMC_SRS_FATAL_MASK)
11126 
11127 #define CMC_SRS_PIN_MASK                         (0x100U)
11128 #define CMC_SRS_PIN_SHIFT                        (8U)
11129 /*! PIN - Pin Reset
11130  *  0b0..Reset was not generated
11131  *  0b1..Reset was generated
11132  */
11133 #define CMC_SRS_PIN(x)                           (((uint32_t)(((uint32_t)(x)) << CMC_SRS_PIN_SHIFT)) & CMC_SRS_PIN_MASK)
11134 
11135 #define CMC_SRS_DAP_MASK                         (0x200U)
11136 #define CMC_SRS_DAP_SHIFT                        (9U)
11137 /*! DAP - Debug Access Port Reset
11138  *  0b0..Reset was not generated
11139  *  0b1..Reset was generated
11140  */
11141 #define CMC_SRS_DAP(x)                           (((uint32_t)(((uint32_t)(x)) << CMC_SRS_DAP_SHIFT)) & CMC_SRS_DAP_MASK)
11142 
11143 #define CMC_SRS_RSTACK_MASK                      (0x400U)
11144 #define CMC_SRS_RSTACK_SHIFT                     (10U)
11145 /*! RSTACK - Reset Timeout
11146  *  0b0..Reset not generated
11147  *  0b1..Reset generated
11148  */
11149 #define CMC_SRS_RSTACK(x)                        (((uint32_t)(((uint32_t)(x)) << CMC_SRS_RSTACK_SHIFT)) & CMC_SRS_RSTACK_MASK)
11150 
11151 #define CMC_SRS_LPACK_MASK                       (0x800U)
11152 #define CMC_SRS_LPACK_SHIFT                      (11U)
11153 /*! LPACK - Low Power Acknowledge Timeout Reset
11154  *  0b0..Reset not generated
11155  *  0b1..Reset generated
11156  */
11157 #define CMC_SRS_LPACK(x)                         (((uint32_t)(((uint32_t)(x)) << CMC_SRS_LPACK_SHIFT)) & CMC_SRS_LPACK_MASK)
11158 
11159 #define CMC_SRS_SCG_MASK                         (0x1000U)
11160 #define CMC_SRS_SCG_SHIFT                        (12U)
11161 /*! SCG - System Clock Generation Reset
11162  *  0b0..Reset is not generated
11163  *  0b1..Reset is generated
11164  */
11165 #define CMC_SRS_SCG(x)                           (((uint32_t)(((uint32_t)(x)) << CMC_SRS_SCG_SHIFT)) & CMC_SRS_SCG_MASK)
11166 
11167 #define CMC_SRS_WWDT0_MASK                       (0x2000U)
11168 #define CMC_SRS_WWDT0_SHIFT                      (13U)
11169 /*! WWDT0 - Windowed Watchdog 0 Reset
11170  *  0b0..Reset is not generated
11171  *  0b1..Reset is generated
11172  */
11173 #define CMC_SRS_WWDT0(x)                         (((uint32_t)(((uint32_t)(x)) << CMC_SRS_WWDT0_SHIFT)) & CMC_SRS_WWDT0_MASK)
11174 
11175 #define CMC_SRS_SW_MASK                          (0x4000U)
11176 #define CMC_SRS_SW_SHIFT                         (14U)
11177 /*! SW - Software Reset
11178  *  0b0..Reset not generated
11179  *  0b1..Reset generated
11180  */
11181 #define CMC_SRS_SW(x)                            (((uint32_t)(((uint32_t)(x)) << CMC_SRS_SW_SHIFT)) & CMC_SRS_SW_MASK)
11182 
11183 #define CMC_SRS_LOCKUP_MASK                      (0x8000U)
11184 #define CMC_SRS_LOCKUP_SHIFT                     (15U)
11185 /*! LOCKUP - Lockup Reset
11186  *  0b0..Reset not generated
11187  *  0b1..Reset generated
11188  */
11189 #define CMC_SRS_LOCKUP(x)                        (((uint32_t)(((uint32_t)(x)) << CMC_SRS_LOCKUP_SHIFT)) & CMC_SRS_LOCKUP_MASK)
11190 
11191 #define CMC_SRS_CPU1_MASK                        (0x10000U)
11192 #define CMC_SRS_CPU1_SHIFT                       (16U)
11193 /*! CPU1 - CPU1 System Reset
11194  *  0b0..Reset not generated
11195  *  0b1..Reset generated
11196  */
11197 #define CMC_SRS_CPU1(x)                          (((uint32_t)(((uint32_t)(x)) << CMC_SRS_CPU1_SHIFT)) & CMC_SRS_CPU1_MASK)
11198 
11199 #define CMC_SRS_VBAT_MASK                        (0x1000000U)
11200 #define CMC_SRS_VBAT_SHIFT                       (24U)
11201 /*! VBAT - VBAT System Reset
11202  *  0b0..Reset not generated
11203  *  0b1..Reset generated
11204  */
11205 #define CMC_SRS_VBAT(x)                          (((uint32_t)(((uint32_t)(x)) << CMC_SRS_VBAT_SHIFT)) & CMC_SRS_VBAT_MASK)
11206 
11207 #define CMC_SRS_WWDT1_MASK                       (0x2000000U)
11208 #define CMC_SRS_WWDT1_SHIFT                      (25U)
11209 /*! WWDT1 - Windowed Watchdog 1 Reset
11210  *  0b0..Reset is not generated
11211  *  0b1..Reset is generated
11212  */
11213 #define CMC_SRS_WWDT1(x)                         (((uint32_t)(((uint32_t)(x)) << CMC_SRS_WWDT1_SHIFT)) & CMC_SRS_WWDT1_MASK)
11214 
11215 #define CMC_SRS_CDOG0_MASK                       (0x4000000U)
11216 #define CMC_SRS_CDOG0_SHIFT                      (26U)
11217 /*! CDOG0 - Code Watchdog 0 Reset
11218  *  0b0..Reset is not generated
11219  *  0b1..Reset is generated
11220  */
11221 #define CMC_SRS_CDOG0(x)                         (((uint32_t)(((uint32_t)(x)) << CMC_SRS_CDOG0_SHIFT)) & CMC_SRS_CDOG0_MASK)
11222 
11223 #define CMC_SRS_CDOG1_MASK                       (0x8000000U)
11224 #define CMC_SRS_CDOG1_SHIFT                      (27U)
11225 /*! CDOG1 - Code Watchdog 1 Reset
11226  *  0b0..Reset is not generated
11227  *  0b1..Reset is generated
11228  */
11229 #define CMC_SRS_CDOG1(x)                         (((uint32_t)(((uint32_t)(x)) << CMC_SRS_CDOG1_SHIFT)) & CMC_SRS_CDOG1_MASK)
11230 
11231 #define CMC_SRS_JTAG_MASK                        (0x10000000U)
11232 #define CMC_SRS_JTAG_SHIFT                       (28U)
11233 /*! JTAG - JTAG System Reset
11234  *  0b0..Reset not generated
11235  *  0b1..Reset generated
11236  */
11237 #define CMC_SRS_JTAG(x)                          (((uint32_t)(((uint32_t)(x)) << CMC_SRS_JTAG_SHIFT)) & CMC_SRS_JTAG_MASK)
11238 
11239 #define CMC_SRS_SECVIO_MASK                      (0x40000000U)
11240 #define CMC_SRS_SECVIO_SHIFT                     (30U)
11241 /*! SECVIO - Security Violation Reset
11242  *  0b0..Reset not generated
11243  *  0b1..Reset generated
11244  */
11245 #define CMC_SRS_SECVIO(x)                        (((uint32_t)(((uint32_t)(x)) << CMC_SRS_SECVIO_SHIFT)) & CMC_SRS_SECVIO_MASK)
11246 
11247 #define CMC_SRS_TAMPER_MASK                      (0x80000000U)
11248 #define CMC_SRS_TAMPER_SHIFT                     (31U)
11249 /*! TAMPER - Tamper Reset
11250  *  0b0..Reset not generated
11251  *  0b1..Reset generated
11252  */
11253 #define CMC_SRS_TAMPER(x)                        (((uint32_t)(((uint32_t)(x)) << CMC_SRS_TAMPER_SHIFT)) & CMC_SRS_TAMPER_MASK)
11254 /*! @} */
11255 
11256 /*! @name RPC - Reset Pin Control */
11257 /*! @{ */
11258 
11259 #define CMC_RPC_FILTCFG_MASK                     (0x1FU)
11260 #define CMC_RPC_FILTCFG_SHIFT                    (0U)
11261 /*! FILTCFG - Reset Filter Configuration */
11262 #define CMC_RPC_FILTCFG(x)                       (((uint32_t)(((uint32_t)(x)) << CMC_RPC_FILTCFG_SHIFT)) & CMC_RPC_FILTCFG_MASK)
11263 
11264 #define CMC_RPC_FILTEN_MASK                      (0x100U)
11265 #define CMC_RPC_FILTEN_SHIFT                     (8U)
11266 /*! FILTEN - Filter Enable
11267  *  0b0..Disables
11268  *  0b1..Enables
11269  */
11270 #define CMC_RPC_FILTEN(x)                        (((uint32_t)(((uint32_t)(x)) << CMC_RPC_FILTEN_SHIFT)) & CMC_RPC_FILTEN_MASK)
11271 
11272 #define CMC_RPC_LPFEN_MASK                       (0x200U)
11273 #define CMC_RPC_LPFEN_SHIFT                      (9U)
11274 /*! LPFEN - Low-Power Filter Enable
11275  *  0b0..Disables
11276  *  0b1..Enables
11277  */
11278 #define CMC_RPC_LPFEN(x)                         (((uint32_t)(((uint32_t)(x)) << CMC_RPC_LPFEN_SHIFT)) & CMC_RPC_LPFEN_MASK)
11279 /*! @} */
11280 
11281 /*! @name SSRS - Sticky System Reset Status */
11282 /*! @{ */
11283 
11284 #define CMC_SSRS_WAKEUP_MASK                     (0x1U)
11285 #define CMC_SSRS_WAKEUP_SHIFT                    (0U)
11286 /*! WAKEUP - Wake-up Reset
11287  *  0b0..Reset not generated
11288  *  0b1..Reset generated
11289  */
11290 #define CMC_SSRS_WAKEUP(x)                       (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_WAKEUP_SHIFT)) & CMC_SSRS_WAKEUP_MASK)
11291 
11292 #define CMC_SSRS_POR_MASK                        (0x2U)
11293 #define CMC_SSRS_POR_SHIFT                       (1U)
11294 /*! POR - Power-on Reset
11295  *  0b0..Reset not generated
11296  *  0b1..Reset generated
11297  */
11298 #define CMC_SSRS_POR(x)                          (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_POR_SHIFT)) & CMC_SSRS_POR_MASK)
11299 
11300 #define CMC_SSRS_VD_MASK                         (0x4U)
11301 #define CMC_SSRS_VD_SHIFT                        (2U)
11302 /*! VD - Voltage Detect Reset
11303  *  0b0..Reset not generated
11304  *  0b1..Reset generated
11305  */
11306 #define CMC_SSRS_VD(x)                           (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_VD_SHIFT)) & CMC_SSRS_VD_MASK)
11307 
11308 #define CMC_SSRS_WARM_MASK                       (0x10U)
11309 #define CMC_SSRS_WARM_SHIFT                      (4U)
11310 /*! WARM - Warm Reset
11311  *  0b0..Reset not generated
11312  *  0b1..Reset generated
11313  */
11314 #define CMC_SSRS_WARM(x)                         (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_WARM_SHIFT)) & CMC_SSRS_WARM_MASK)
11315 
11316 #define CMC_SSRS_FATAL_MASK                      (0x20U)
11317 #define CMC_SSRS_FATAL_SHIFT                     (5U)
11318 /*! FATAL - Fatal Reset
11319  *  0b0..Reset was not generated
11320  *  0b1..Reset was generated
11321  */
11322 #define CMC_SSRS_FATAL(x)                        (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_FATAL_SHIFT)) & CMC_SSRS_FATAL_MASK)
11323 
11324 #define CMC_SSRS_PIN_MASK                        (0x100U)
11325 #define CMC_SSRS_PIN_SHIFT                       (8U)
11326 /*! PIN - Pin Reset
11327  *  0b0..Reset not generated
11328  *  0b1..Reset generated
11329  */
11330 #define CMC_SSRS_PIN(x)                          (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_PIN_SHIFT)) & CMC_SSRS_PIN_MASK)
11331 
11332 #define CMC_SSRS_DAP_MASK                        (0x200U)
11333 #define CMC_SSRS_DAP_SHIFT                       (9U)
11334 /*! DAP - DAP Reset
11335  *  0b0..Reset not generated
11336  *  0b1..Reset generated
11337  */
11338 #define CMC_SSRS_DAP(x)                          (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_DAP_SHIFT)) & CMC_SSRS_DAP_MASK)
11339 
11340 #define CMC_SSRS_RSTACK_MASK                     (0x400U)
11341 #define CMC_SSRS_RSTACK_SHIFT                    (10U)
11342 /*! RSTACK - Reset Timeout
11343  *  0b0..Reset not generated
11344  *  0b1..Reset generated
11345  */
11346 #define CMC_SSRS_RSTACK(x)                       (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_RSTACK_SHIFT)) & CMC_SSRS_RSTACK_MASK)
11347 
11348 #define CMC_SSRS_LPACK_MASK                      (0x800U)
11349 #define CMC_SSRS_LPACK_SHIFT                     (11U)
11350 /*! LPACK - Low Power Acknowledge Timeout Reset
11351  *  0b0..Reset not generated
11352  *  0b1..Reset generated
11353  */
11354 #define CMC_SSRS_LPACK(x)                        (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_LPACK_SHIFT)) & CMC_SSRS_LPACK_MASK)
11355 
11356 #define CMC_SSRS_SCG_MASK                        (0x1000U)
11357 #define CMC_SSRS_SCG_SHIFT                       (12U)
11358 /*! SCG - System Clock Generation Reset
11359  *  0b0..Reset is not generated
11360  *  0b1..Reset is generated
11361  */
11362 #define CMC_SSRS_SCG(x)                          (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_SCG_SHIFT)) & CMC_SSRS_SCG_MASK)
11363 
11364 #define CMC_SSRS_WWDT0_MASK                      (0x2000U)
11365 #define CMC_SSRS_WWDT0_SHIFT                     (13U)
11366 /*! WWDT0 - Windowed Watchdog 0 Reset
11367  *  0b0..Reset is not generated
11368  *  0b1..Reset is generated
11369  */
11370 #define CMC_SSRS_WWDT0(x)                        (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_WWDT0_SHIFT)) & CMC_SSRS_WWDT0_MASK)
11371 
11372 #define CMC_SSRS_SW_MASK                         (0x4000U)
11373 #define CMC_SSRS_SW_SHIFT                        (14U)
11374 /*! SW - Software Reset
11375  *  0b0..Reset not generated
11376  *  0b1..Reset generated
11377  */
11378 #define CMC_SSRS_SW(x)                           (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_SW_SHIFT)) & CMC_SSRS_SW_MASK)
11379 
11380 #define CMC_SSRS_LOCKUP_MASK                     (0x8000U)
11381 #define CMC_SSRS_LOCKUP_SHIFT                    (15U)
11382 /*! LOCKUP - Lockup Reset
11383  *  0b0..Reset not generated
11384  *  0b1..Reset generated
11385  */
11386 #define CMC_SSRS_LOCKUP(x)                       (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_LOCKUP_SHIFT)) & CMC_SSRS_LOCKUP_MASK)
11387 
11388 #define CMC_SSRS_CPU1_MASK                       (0x10000U)
11389 #define CMC_SSRS_CPU1_SHIFT                      (16U)
11390 /*! CPU1 - CPU1 Reset
11391  *  0b0..Reset not generated from CPU1 reset source.
11392  *  0b1..Reset generated from CPU1 reset source.
11393  */
11394 #define CMC_SSRS_CPU1(x)                         (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_CPU1_SHIFT)) & CMC_SSRS_CPU1_MASK)
11395 
11396 #define CMC_SSRS_VBAT_MASK                       (0x1000000U)
11397 #define CMC_SSRS_VBAT_SHIFT                      (24U)
11398 /*! VBAT - VBAT System Reset
11399  *  0b0..Reset not generated
11400  *  0b1..Reset generated
11401  */
11402 #define CMC_SSRS_VBAT(x)                         (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_VBAT_SHIFT)) & CMC_SSRS_VBAT_MASK)
11403 
11404 #define CMC_SSRS_WWDT1_MASK                      (0x2000000U)
11405 #define CMC_SSRS_WWDT1_SHIFT                     (25U)
11406 /*! WWDT1 - Windowed Watchdog 1 Reset
11407  *  0b0..Reset is not generated
11408  *  0b1..Reset is generated
11409  */
11410 #define CMC_SSRS_WWDT1(x)                        (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_WWDT1_SHIFT)) & CMC_SSRS_WWDT1_MASK)
11411 
11412 #define CMC_SSRS_CDOG0_MASK                      (0x4000000U)
11413 #define CMC_SSRS_CDOG0_SHIFT                     (26U)
11414 /*! CDOG0 - Code Watchdog 0 Reset
11415  *  0b0..Reset is not generated
11416  *  0b1..Reset is generated
11417  */
11418 #define CMC_SSRS_CDOG0(x)                        (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_CDOG0_SHIFT)) & CMC_SSRS_CDOG0_MASK)
11419 
11420 #define CMC_SSRS_CDOG1_MASK                      (0x8000000U)
11421 #define CMC_SSRS_CDOG1_SHIFT                     (27U)
11422 /*! CDOG1 - Code Watchdog 1 Reset
11423  *  0b0..Reset is not generated
11424  *  0b1..Reset is generated
11425  */
11426 #define CMC_SSRS_CDOG1(x)                        (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_CDOG1_SHIFT)) & CMC_SSRS_CDOG1_MASK)
11427 
11428 #define CMC_SSRS_JTAG_MASK                       (0x10000000U)
11429 #define CMC_SSRS_JTAG_SHIFT                      (28U)
11430 /*! JTAG - JTAG System Reset
11431  *  0b0..Reset not generated
11432  *  0b1..Reset generated
11433  */
11434 #define CMC_SSRS_JTAG(x)                         (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_JTAG_SHIFT)) & CMC_SSRS_JTAG_MASK)
11435 
11436 #define CMC_SSRS_SECVIO_MASK                     (0x40000000U)
11437 #define CMC_SSRS_SECVIO_SHIFT                    (30U)
11438 /*! SECVIO - Security Violation Reset
11439  *  0b0..Reset not generated
11440  *  0b1..Reset generated
11441  */
11442 #define CMC_SSRS_SECVIO(x)                       (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_SECVIO_SHIFT)) & CMC_SSRS_SECVIO_MASK)
11443 
11444 #define CMC_SSRS_TAMPER_MASK                     (0x80000000U)
11445 #define CMC_SSRS_TAMPER_SHIFT                    (31U)
11446 /*! TAMPER - Tamper Reset
11447  *  0b0..Reset not generated
11448  *  0b1..Reset generated
11449  */
11450 #define CMC_SSRS_TAMPER(x)                       (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_TAMPER_SHIFT)) & CMC_SSRS_TAMPER_MASK)
11451 /*! @} */
11452 
11453 /*! @name SRIE - System Reset Interrupt Enable */
11454 /*! @{ */
11455 
11456 #define CMC_SRIE_PIN_MASK                        (0x100U)
11457 #define CMC_SRIE_PIN_SHIFT                       (8U)
11458 /*! PIN - Pin Reset
11459  *  0b0..Interrupt disabled
11460  *  0b1..Interrupt enabled
11461  */
11462 #define CMC_SRIE_PIN(x)                          (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_PIN_SHIFT)) & CMC_SRIE_PIN_MASK)
11463 
11464 #define CMC_SRIE_DAP_MASK                        (0x200U)
11465 #define CMC_SRIE_DAP_SHIFT                       (9U)
11466 /*! DAP - DAP Reset
11467  *  0b0..Interrupt disabled
11468  *  0b1..Interrupt enabled
11469  */
11470 #define CMC_SRIE_DAP(x)                          (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_DAP_SHIFT)) & CMC_SRIE_DAP_MASK)
11471 
11472 #define CMC_SRIE_LPACK_MASK                      (0x800U)
11473 #define CMC_SRIE_LPACK_SHIFT                     (11U)
11474 /*! LPACK - Low Power Acknowledge Timeout Reset
11475  *  0b0..Interrupt disabled
11476  *  0b1..Interrupt enabled
11477  */
11478 #define CMC_SRIE_LPACK(x)                        (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_LPACK_SHIFT)) & CMC_SRIE_LPACK_MASK)
11479 
11480 #define CMC_SRIE_SCG_MASK                        (0x1000U)
11481 #define CMC_SRIE_SCG_SHIFT                       (12U)
11482 /*! SCG - System Clock Generation Reset
11483  *  0b0..Interrupt disabled
11484  *  0b1..Interrupt enabled
11485  */
11486 #define CMC_SRIE_SCG(x)                          (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_SCG_SHIFT)) & CMC_SRIE_SCG_MASK)
11487 
11488 #define CMC_SRIE_WWDT0_MASK                      (0x2000U)
11489 #define CMC_SRIE_WWDT0_SHIFT                     (13U)
11490 /*! WWDT0 - Windowed Watchdog 0 Reset
11491  *  0b0..Interrupt disabled
11492  *  0b1..Interrupt enabled
11493  */
11494 #define CMC_SRIE_WWDT0(x)                        (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_WWDT0_SHIFT)) & CMC_SRIE_WWDT0_MASK)
11495 
11496 #define CMC_SRIE_SW_MASK                         (0x4000U)
11497 #define CMC_SRIE_SW_SHIFT                        (14U)
11498 /*! SW - Software Reset
11499  *  0b0..Interrupt disabled
11500  *  0b1..Interrupt enabled
11501  */
11502 #define CMC_SRIE_SW(x)                           (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_SW_SHIFT)) & CMC_SRIE_SW_MASK)
11503 
11504 #define CMC_SRIE_LOCKUP_MASK                     (0x8000U)
11505 #define CMC_SRIE_LOCKUP_SHIFT                    (15U)
11506 /*! LOCKUP - Lockup Reset
11507  *  0b0..Interrupt disabled
11508  *  0b1..Interrupt enabled
11509  */
11510 #define CMC_SRIE_LOCKUP(x)                       (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_LOCKUP_SHIFT)) & CMC_SRIE_LOCKUP_MASK)
11511 
11512 #define CMC_SRIE_CPU1_MASK                       (0x10000U)
11513 #define CMC_SRIE_CPU1_SHIFT                      (16U)
11514 /*! CPU1 - CPU1 Reset
11515  *  0b0..Interrupt disabled
11516  *  0b1..Interrupt enabled
11517  */
11518 #define CMC_SRIE_CPU1(x)                         (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_CPU1_SHIFT)) & CMC_SRIE_CPU1_MASK)
11519 
11520 #define CMC_SRIE_VBAT_MASK                       (0x1000000U)
11521 #define CMC_SRIE_VBAT_SHIFT                      (24U)
11522 /*! VBAT - VBAT System Reset
11523  *  0b0..Interrupt disabled
11524  *  0b1..Interrupt enabled
11525  */
11526 #define CMC_SRIE_VBAT(x)                         (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_VBAT_SHIFT)) & CMC_SRIE_VBAT_MASK)
11527 
11528 #define CMC_SRIE_WWDT1_MASK                      (0x2000000U)
11529 #define CMC_SRIE_WWDT1_SHIFT                     (25U)
11530 /*! WWDT1 - Windowed Watchdog 1 Reset
11531  *  0b0..Interrupt disabled
11532  *  0b1..Interrupt enabled
11533  */
11534 #define CMC_SRIE_WWDT1(x)                        (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_WWDT1_SHIFT)) & CMC_SRIE_WWDT1_MASK)
11535 
11536 #define CMC_SRIE_CDOG0_MASK                      (0x4000000U)
11537 #define CMC_SRIE_CDOG0_SHIFT                     (26U)
11538 /*! CDOG0 - Code Watchdog 0 Reset
11539  *  0b0..Interrupt disabled
11540  *  0b1..Interrupt enabled
11541  */
11542 #define CMC_SRIE_CDOG0(x)                        (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_CDOG0_SHIFT)) & CMC_SRIE_CDOG0_MASK)
11543 
11544 #define CMC_SRIE_CDOG1_MASK                      (0x8000000U)
11545 #define CMC_SRIE_CDOG1_SHIFT                     (27U)
11546 /*! CDOG1 - Code Watchdog 1 Reset
11547  *  0b0..Interrupt disabled
11548  *  0b1..Interrupt enabled
11549  */
11550 #define CMC_SRIE_CDOG1(x)                        (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_CDOG1_SHIFT)) & CMC_SRIE_CDOG1_MASK)
11551 /*! @} */
11552 
11553 /*! @name SRIF - System Reset Interrupt Flag */
11554 /*! @{ */
11555 
11556 #define CMC_SRIF_PIN_MASK                        (0x100U)
11557 #define CMC_SRIF_PIN_SHIFT                       (8U)
11558 /*! PIN - Pin Reset
11559  *  0b0..Reset source not pending
11560  *  0b1..Reset source pending
11561  */
11562 #define CMC_SRIF_PIN(x)                          (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_PIN_SHIFT)) & CMC_SRIF_PIN_MASK)
11563 
11564 #define CMC_SRIF_DAP_MASK                        (0x200U)
11565 #define CMC_SRIF_DAP_SHIFT                       (9U)
11566 /*! DAP - DAP Reset
11567  *  0b0..Reset source not pending
11568  *  0b1..Reset source pending
11569  */
11570 #define CMC_SRIF_DAP(x)                          (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_DAP_SHIFT)) & CMC_SRIF_DAP_MASK)
11571 
11572 #define CMC_SRIF_LPACK_MASK                      (0x800U)
11573 #define CMC_SRIF_LPACK_SHIFT                     (11U)
11574 /*! LPACK - Low Power Acknowledge Timeout Reset
11575  *  0b0..Reset source not pending
11576  *  0b1..Reset source pending
11577  */
11578 #define CMC_SRIF_LPACK(x)                        (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_LPACK_SHIFT)) & CMC_SRIF_LPACK_MASK)
11579 
11580 #define CMC_SRIF_WWDT0_MASK                      (0x2000U)
11581 #define CMC_SRIF_WWDT0_SHIFT                     (13U)
11582 /*! WWDT0 - Windowed Watchdog 0 Reset
11583  *  0b0..Reset source not pending
11584  *  0b1..Reset source pending
11585  */
11586 #define CMC_SRIF_WWDT0(x)                        (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_WWDT0_SHIFT)) & CMC_SRIF_WWDT0_MASK)
11587 
11588 #define CMC_SRIF_SW_MASK                         (0x4000U)
11589 #define CMC_SRIF_SW_SHIFT                        (14U)
11590 /*! SW - Software Reset
11591  *  0b0..Reset source not pending
11592  *  0b1..Reset source pending
11593  */
11594 #define CMC_SRIF_SW(x)                           (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_SW_SHIFT)) & CMC_SRIF_SW_MASK)
11595 
11596 #define CMC_SRIF_LOCKUP_MASK                     (0x8000U)
11597 #define CMC_SRIF_LOCKUP_SHIFT                    (15U)
11598 /*! LOCKUP - Lockup Reset
11599  *  0b0..Reset source not pending
11600  *  0b1..Reset source pending
11601  */
11602 #define CMC_SRIF_LOCKUP(x)                       (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_LOCKUP_SHIFT)) & CMC_SRIF_LOCKUP_MASK)
11603 
11604 #define CMC_SRIF_CPU1_MASK                       (0x10000U)
11605 #define CMC_SRIF_CPU1_SHIFT                      (16U)
11606 /*! CPU1 - CPU1 Reset
11607  *  0b0..Reset source not pending
11608  *  0b1..Reset source pending
11609  */
11610 #define CMC_SRIF_CPU1(x)                         (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_CPU1_SHIFT)) & CMC_SRIF_CPU1_MASK)
11611 
11612 #define CMC_SRIF_VBAT_MASK                       (0x1000000U)
11613 #define CMC_SRIF_VBAT_SHIFT                      (24U)
11614 /*! VBAT - VBAT System Reset
11615  *  0b0..Reset source not pending
11616  *  0b1..Reset source pending
11617  */
11618 #define CMC_SRIF_VBAT(x)                         (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_VBAT_SHIFT)) & CMC_SRIF_VBAT_MASK)
11619 
11620 #define CMC_SRIF_WWDT1_MASK                      (0x2000000U)
11621 #define CMC_SRIF_WWDT1_SHIFT                     (25U)
11622 /*! WWDT1 - Windowed Watchdog 1 Reset
11623  *  0b0..Reset source not pending
11624  *  0b1..Reset source pending
11625  */
11626 #define CMC_SRIF_WWDT1(x)                        (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_WWDT1_SHIFT)) & CMC_SRIF_WWDT1_MASK)
11627 
11628 #define CMC_SRIF_CDOG0_MASK                      (0x4000000U)
11629 #define CMC_SRIF_CDOG0_SHIFT                     (26U)
11630 /*! CDOG0 - Code Watchdog 0 Reset
11631  *  0b0..Reset source not pending
11632  *  0b1..Reset source pending
11633  */
11634 #define CMC_SRIF_CDOG0(x)                        (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_CDOG0_SHIFT)) & CMC_SRIF_CDOG0_MASK)
11635 
11636 #define CMC_SRIF_CDOG1_MASK                      (0x8000000U)
11637 #define CMC_SRIF_CDOG1_SHIFT                     (27U)
11638 /*! CDOG1 - Code Watchdog 1 Reset
11639  *  0b0..Reset source not pending
11640  *  0b1..Reset source pending
11641  */
11642 #define CMC_SRIF_CDOG1(x)                        (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_CDOG1_SHIFT)) & CMC_SRIF_CDOG1_MASK)
11643 /*! @} */
11644 
11645 /*! @name RSTCNT - Reset Count Register */
11646 /*! @{ */
11647 
11648 #define CMC_RSTCNT_COUNT_MASK                    (0xFFU)
11649 #define CMC_RSTCNT_COUNT_SHIFT                   (0U)
11650 /*! COUNT - Count */
11651 #define CMC_RSTCNT_COUNT(x)                      (((uint32_t)(((uint32_t)(x)) << CMC_RSTCNT_COUNT_SHIFT)) & CMC_RSTCNT_COUNT_MASK)
11652 /*! @} */
11653 
11654 /*! @name MR - Mode */
11655 /*! @{ */
11656 
11657 #define CMC_MR_ISPMODE_n_MASK                    (0x1U)
11658 #define CMC_MR_ISPMODE_n_SHIFT                   (0U)
11659 /*! ISPMODE_n - In System Programming Mode */
11660 #define CMC_MR_ISPMODE_n(x)                      (((uint32_t)(((uint32_t)(x)) << CMC_MR_ISPMODE_n_SHIFT)) & CMC_MR_ISPMODE_n_MASK)
11661 /*! @} */
11662 
11663 /* The count of CMC_MR */
11664 #define CMC_MR_COUNT                             (1U)
11665 
11666 /*! @name FM - Force Mode */
11667 /*! @{ */
11668 
11669 #define CMC_FM_FORCECFG_MASK                     (0x1U)
11670 #define CMC_FM_FORCECFG_SHIFT                    (0U)
11671 /*! FORCECFG - Boot Configuration
11672  *  0b0..No effect
11673  *  0b1..Asserts
11674  */
11675 #define CMC_FM_FORCECFG(x)                       (((uint32_t)(((uint32_t)(x)) << CMC_FM_FORCECFG_SHIFT)) & CMC_FM_FORCECFG_MASK)
11676 /*! @} */
11677 
11678 /* The count of CMC_FM */
11679 #define CMC_FM_COUNT                             (1U)
11680 
11681 /*! @name SRAMDIS - SRAM Disable */
11682 /*! @{ */
11683 
11684 #define CMC_SRAMDIS_DIS0_MASK                    (0x1U)
11685 #define CMC_SRAMDIS_DIS0_SHIFT                   (0U)
11686 /*! DIS0 - SRAM Disable
11687  *  0b0..Enables
11688  *  0b1..Disables
11689  */
11690 #define CMC_SRAMDIS_DIS0(x)                      (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS0_SHIFT)) & CMC_SRAMDIS_DIS0_MASK)
11691 
11692 #define CMC_SRAMDIS_DIS1_MASK                    (0x2U)
11693 #define CMC_SRAMDIS_DIS1_SHIFT                   (1U)
11694 /*! DIS1 - SRAM Disable
11695  *  0b0..Enables
11696  *  0b1..Disables
11697  */
11698 #define CMC_SRAMDIS_DIS1(x)                      (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS1_SHIFT)) & CMC_SRAMDIS_DIS1_MASK)
11699 
11700 #define CMC_SRAMDIS_DIS2_MASK                    (0x4U)
11701 #define CMC_SRAMDIS_DIS2_SHIFT                   (2U)
11702 /*! DIS2 - SRAM Disable
11703  *  0b0..Enables
11704  *  0b1..Disables
11705  */
11706 #define CMC_SRAMDIS_DIS2(x)                      (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS2_SHIFT)) & CMC_SRAMDIS_DIS2_MASK)
11707 
11708 #define CMC_SRAMDIS_DIS3_MASK                    (0x8U)
11709 #define CMC_SRAMDIS_DIS3_SHIFT                   (3U)
11710 /*! DIS3 - SRAM Disable
11711  *  0b0..Enables
11712  *  0b1..Disables
11713  */
11714 #define CMC_SRAMDIS_DIS3(x)                      (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS3_SHIFT)) & CMC_SRAMDIS_DIS3_MASK)
11715 
11716 #define CMC_SRAMDIS_DIS4_MASK                    (0x10U)
11717 #define CMC_SRAMDIS_DIS4_SHIFT                   (4U)
11718 /*! DIS4 - SRAM Disable
11719  *  0b0..Enables
11720  *  0b1..Disables
11721  */
11722 #define CMC_SRAMDIS_DIS4(x)                      (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS4_SHIFT)) & CMC_SRAMDIS_DIS4_MASK)
11723 
11724 #define CMC_SRAMDIS_DIS5_MASK                    (0x20U)
11725 #define CMC_SRAMDIS_DIS5_SHIFT                   (5U)
11726 /*! DIS5 - SRAM Disable
11727  *  0b0..Enables
11728  *  0b1..Disables
11729  */
11730 #define CMC_SRAMDIS_DIS5(x)                      (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS5_SHIFT)) & CMC_SRAMDIS_DIS5_MASK)
11731 
11732 #define CMC_SRAMDIS_DIS6_MASK                    (0x40U)
11733 #define CMC_SRAMDIS_DIS6_SHIFT                   (6U)
11734 /*! DIS6 - SRAM Disable
11735  *  0b0..Enables
11736  *  0b1..Disables
11737  */
11738 #define CMC_SRAMDIS_DIS6(x)                      (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS6_SHIFT)) & CMC_SRAMDIS_DIS6_MASK)
11739 
11740 #define CMC_SRAMDIS_DIS7_MASK                    (0x80U)
11741 #define CMC_SRAMDIS_DIS7_SHIFT                   (7U)
11742 /*! DIS7 - SRAM Disable
11743  *  0b0..Enables
11744  *  0b1..Disables
11745  */
11746 #define CMC_SRAMDIS_DIS7(x)                      (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS7_SHIFT)) & CMC_SRAMDIS_DIS7_MASK)
11747 
11748 #define CMC_SRAMDIS_DIS8_MASK                    (0x100U)
11749 #define CMC_SRAMDIS_DIS8_SHIFT                   (8U)
11750 /*! DIS8 - SRAM Disable
11751  *  0b0..Enables
11752  *  0b1..Disables
11753  */
11754 #define CMC_SRAMDIS_DIS8(x)                      (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS8_SHIFT)) & CMC_SRAMDIS_DIS8_MASK)
11755 
11756 #define CMC_SRAMDIS_DIS9_MASK                    (0x200U)
11757 #define CMC_SRAMDIS_DIS9_SHIFT                   (9U)
11758 /*! DIS9 - SRAM Disable
11759  *  0b0..Enables
11760  *  0b1..Disables
11761  */
11762 #define CMC_SRAMDIS_DIS9(x)                      (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS9_SHIFT)) & CMC_SRAMDIS_DIS9_MASK)
11763 
11764 #define CMC_SRAMDIS_DIS10_MASK                   (0x400U)
11765 #define CMC_SRAMDIS_DIS10_SHIFT                  (10U)
11766 /*! DIS10 - SRAM Disable
11767  *  0b0..Enables
11768  *  0b1..Disables
11769  */
11770 #define CMC_SRAMDIS_DIS10(x)                     (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS10_SHIFT)) & CMC_SRAMDIS_DIS10_MASK)
11771 
11772 #define CMC_SRAMDIS_DIS11_MASK                   (0x800U)
11773 #define CMC_SRAMDIS_DIS11_SHIFT                  (11U)
11774 /*! DIS11 - SRAM Disable
11775  *  0b0..Enables
11776  *  0b1..Disables
11777  */
11778 #define CMC_SRAMDIS_DIS11(x)                     (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS11_SHIFT)) & CMC_SRAMDIS_DIS11_MASK)
11779 
11780 #define CMC_SRAMDIS_DIS12_MASK                   (0x1000U)
11781 #define CMC_SRAMDIS_DIS12_SHIFT                  (12U)
11782 /*! DIS12 - SRAM Disable
11783  *  0b0..Enables
11784  *  0b1..Disables
11785  */
11786 #define CMC_SRAMDIS_DIS12(x)                     (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS12_SHIFT)) & CMC_SRAMDIS_DIS12_MASK)
11787 
11788 #define CMC_SRAMDIS_DIS13_MASK                   (0x2000U)
11789 #define CMC_SRAMDIS_DIS13_SHIFT                  (13U)
11790 /*! DIS13 - SRAM Disable
11791  *  0b0..Enables
11792  *  0b1..Disables
11793  */
11794 #define CMC_SRAMDIS_DIS13(x)                     (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS13_SHIFT)) & CMC_SRAMDIS_DIS13_MASK)
11795 
11796 #define CMC_SRAMDIS_DIS14_MASK                   (0x4000U)
11797 #define CMC_SRAMDIS_DIS14_SHIFT                  (14U)
11798 /*! DIS14 - SRAM Disable
11799  *  0b0..Enables
11800  *  0b1..Disables
11801  */
11802 #define CMC_SRAMDIS_DIS14(x)                     (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS14_SHIFT)) & CMC_SRAMDIS_DIS14_MASK)
11803 
11804 #define CMC_SRAMDIS_DIS15_MASK                   (0x8000U)
11805 #define CMC_SRAMDIS_DIS15_SHIFT                  (15U)
11806 /*! DIS15 - SRAM Disable
11807  *  0b0..Enables
11808  *  0b1..Disables
11809  */
11810 #define CMC_SRAMDIS_DIS15(x)                     (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS15_SHIFT)) & CMC_SRAMDIS_DIS15_MASK)
11811 
11812 #define CMC_SRAMDIS_DIS16_MASK                   (0x10000U)
11813 #define CMC_SRAMDIS_DIS16_SHIFT                  (16U)
11814 /*! DIS16 - SRAM Disable
11815  *  0b0..Enables
11816  *  0b1..Disables
11817  */
11818 #define CMC_SRAMDIS_DIS16(x)                     (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS16_SHIFT)) & CMC_SRAMDIS_DIS16_MASK)
11819 
11820 #define CMC_SRAMDIS_DIS17_MASK                   (0x20000U)
11821 #define CMC_SRAMDIS_DIS17_SHIFT                  (17U)
11822 /*! DIS17 - SRAM Disable
11823  *  0b0..Enables
11824  *  0b1..Disables
11825  */
11826 #define CMC_SRAMDIS_DIS17(x)                     (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS17_SHIFT)) & CMC_SRAMDIS_DIS17_MASK)
11827 
11828 #define CMC_SRAMDIS_DIS18_MASK                   (0x40000U)
11829 #define CMC_SRAMDIS_DIS18_SHIFT                  (18U)
11830 /*! DIS18 - SRAM Disable
11831  *  0b0..Enables
11832  *  0b1..Disables
11833  */
11834 #define CMC_SRAMDIS_DIS18(x)                     (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS18_SHIFT)) & CMC_SRAMDIS_DIS18_MASK)
11835 
11836 #define CMC_SRAMDIS_DIS19_MASK                   (0x80000U)
11837 #define CMC_SRAMDIS_DIS19_SHIFT                  (19U)
11838 /*! DIS19 - SRAM Disable
11839  *  0b0..Enables
11840  *  0b1..Disables
11841  */
11842 #define CMC_SRAMDIS_DIS19(x)                     (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS19_SHIFT)) & CMC_SRAMDIS_DIS19_MASK)
11843 
11844 #define CMC_SRAMDIS_DIS20_MASK                   (0x100000U)
11845 #define CMC_SRAMDIS_DIS20_SHIFT                  (20U)
11846 /*! DIS20 - SRAM Disable
11847  *  0b0..Enables
11848  *  0b1..Disables
11849  */
11850 #define CMC_SRAMDIS_DIS20(x)                     (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS20_SHIFT)) & CMC_SRAMDIS_DIS20_MASK)
11851 
11852 #define CMC_SRAMDIS_DIS21_MASK                   (0x200000U)
11853 #define CMC_SRAMDIS_DIS21_SHIFT                  (21U)
11854 /*! DIS21 - SRAM Disable
11855  *  0b0..Enables
11856  *  0b1..Disables
11857  */
11858 #define CMC_SRAMDIS_DIS21(x)                     (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS21_SHIFT)) & CMC_SRAMDIS_DIS21_MASK)
11859 
11860 #define CMC_SRAMDIS_DIS22_MASK                   (0x400000U)
11861 #define CMC_SRAMDIS_DIS22_SHIFT                  (22U)
11862 /*! DIS22 - SRAM Disable
11863  *  0b0..Enables
11864  *  0b1..Disables
11865  */
11866 #define CMC_SRAMDIS_DIS22(x)                     (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS22_SHIFT)) & CMC_SRAMDIS_DIS22_MASK)
11867 
11868 #define CMC_SRAMDIS_DIS23_MASK                   (0x800000U)
11869 #define CMC_SRAMDIS_DIS23_SHIFT                  (23U)
11870 /*! DIS23 - SRAM Disable
11871  *  0b0..Enables
11872  *  0b1..Disables
11873  */
11874 #define CMC_SRAMDIS_DIS23(x)                     (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS23_SHIFT)) & CMC_SRAMDIS_DIS23_MASK)
11875 
11876 #define CMC_SRAMDIS_DIS24_MASK                   (0x1000000U)
11877 #define CMC_SRAMDIS_DIS24_SHIFT                  (24U)
11878 /*! DIS24 - SRAM Disable
11879  *  0b0..Enables
11880  *  0b1..Disables
11881  */
11882 #define CMC_SRAMDIS_DIS24(x)                     (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS24_SHIFT)) & CMC_SRAMDIS_DIS24_MASK)
11883 
11884 #define CMC_SRAMDIS_DIS25_MASK                   (0x2000000U)
11885 #define CMC_SRAMDIS_DIS25_SHIFT                  (25U)
11886 /*! DIS25 - SRAM Disable
11887  *  0b0..Enables
11888  *  0b1..Disables
11889  */
11890 #define CMC_SRAMDIS_DIS25(x)                     (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS25_SHIFT)) & CMC_SRAMDIS_DIS25_MASK)
11891 
11892 #define CMC_SRAMDIS_DIS26_MASK                   (0x4000000U)
11893 #define CMC_SRAMDIS_DIS26_SHIFT                  (26U)
11894 /*! DIS26 - SRAM Disable
11895  *  0b0..Enables
11896  *  0b1..Disables
11897  */
11898 #define CMC_SRAMDIS_DIS26(x)                     (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS26_SHIFT)) & CMC_SRAMDIS_DIS26_MASK)
11899 
11900 #define CMC_SRAMDIS_DIS27_MASK                   (0x8000000U)
11901 #define CMC_SRAMDIS_DIS27_SHIFT                  (27U)
11902 /*! DIS27 - SRAM Disable
11903  *  0b0..Enables
11904  *  0b1..Disables
11905  */
11906 #define CMC_SRAMDIS_DIS27(x)                     (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS27_SHIFT)) & CMC_SRAMDIS_DIS27_MASK)
11907 
11908 #define CMC_SRAMDIS_DIS28_MASK                   (0x10000000U)
11909 #define CMC_SRAMDIS_DIS28_SHIFT                  (28U)
11910 /*! DIS28 - SRAM Disable
11911  *  0b0..Enables
11912  *  0b1..Disables
11913  */
11914 #define CMC_SRAMDIS_DIS28(x)                     (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS28_SHIFT)) & CMC_SRAMDIS_DIS28_MASK)
11915 
11916 #define CMC_SRAMDIS_DIS29_MASK                   (0x20000000U)
11917 #define CMC_SRAMDIS_DIS29_SHIFT                  (29U)
11918 /*! DIS29 - SRAM Disable
11919  *  0b0..Enables
11920  *  0b1..Disables
11921  */
11922 #define CMC_SRAMDIS_DIS29(x)                     (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS29_SHIFT)) & CMC_SRAMDIS_DIS29_MASK)
11923 
11924 #define CMC_SRAMDIS_DIS30_MASK                   (0x40000000U)
11925 #define CMC_SRAMDIS_DIS30_SHIFT                  (30U)
11926 /*! DIS30 - SRAM Disable
11927  *  0b0..Enables
11928  *  0b1..Disables
11929  */
11930 #define CMC_SRAMDIS_DIS30(x)                     (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS30_SHIFT)) & CMC_SRAMDIS_DIS30_MASK)
11931 
11932 #define CMC_SRAMDIS_DIS31_MASK                   (0x80000000U)
11933 #define CMC_SRAMDIS_DIS31_SHIFT                  (31U)
11934 /*! DIS31 - SRAM Disable
11935  *  0b0..Enables
11936  *  0b1..Disables
11937  */
11938 #define CMC_SRAMDIS_DIS31(x)                     (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS31_SHIFT)) & CMC_SRAMDIS_DIS31_MASK)
11939 /*! @} */
11940 
11941 /* The count of CMC_SRAMDIS */
11942 #define CMC_SRAMDIS_COUNT                        (1U)
11943 
11944 /*! @name SRAMRET - SRAM Retention */
11945 /*! @{ */
11946 
11947 #define CMC_SRAMRET_RET0_MASK                    (0x1U)
11948 #define CMC_SRAMRET_RET0_SHIFT                   (0U)
11949 /*! RET0 - SRAM Retention
11950  *  0b0..Retains
11951  *  0b1..Powers off
11952  */
11953 #define CMC_SRAMRET_RET0(x)                      (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET0_SHIFT)) & CMC_SRAMRET_RET0_MASK)
11954 
11955 #define CMC_SRAMRET_RET1_MASK                    (0x2U)
11956 #define CMC_SRAMRET_RET1_SHIFT                   (1U)
11957 /*! RET1 - SRAM Retention
11958  *  0b0..Retains
11959  *  0b1..Powers off
11960  */
11961 #define CMC_SRAMRET_RET1(x)                      (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET1_SHIFT)) & CMC_SRAMRET_RET1_MASK)
11962 
11963 #define CMC_SRAMRET_RET2_MASK                    (0x4U)
11964 #define CMC_SRAMRET_RET2_SHIFT                   (2U)
11965 /*! RET2 - SRAM Retention
11966  *  0b0..Retains
11967  *  0b1..Powers off
11968  */
11969 #define CMC_SRAMRET_RET2(x)                      (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET2_SHIFT)) & CMC_SRAMRET_RET2_MASK)
11970 
11971 #define CMC_SRAMRET_RET3_MASK                    (0x8U)
11972 #define CMC_SRAMRET_RET3_SHIFT                   (3U)
11973 /*! RET3 - SRAM Retention
11974  *  0b0..Retains
11975  *  0b1..Powers off
11976  */
11977 #define CMC_SRAMRET_RET3(x)                      (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET3_SHIFT)) & CMC_SRAMRET_RET3_MASK)
11978 
11979 #define CMC_SRAMRET_RET4_MASK                    (0x10U)
11980 #define CMC_SRAMRET_RET4_SHIFT                   (4U)
11981 /*! RET4 - SRAM Retention
11982  *  0b0..Retains
11983  *  0b1..Powers off
11984  */
11985 #define CMC_SRAMRET_RET4(x)                      (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET4_SHIFT)) & CMC_SRAMRET_RET4_MASK)
11986 
11987 #define CMC_SRAMRET_RET5_MASK                    (0x20U)
11988 #define CMC_SRAMRET_RET5_SHIFT                   (5U)
11989 /*! RET5 - SRAM Retention
11990  *  0b0..Retains
11991  *  0b1..Powers off
11992  */
11993 #define CMC_SRAMRET_RET5(x)                      (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET5_SHIFT)) & CMC_SRAMRET_RET5_MASK)
11994 
11995 #define CMC_SRAMRET_RET6_MASK                    (0x40U)
11996 #define CMC_SRAMRET_RET6_SHIFT                   (6U)
11997 /*! RET6 - SRAM Retention
11998  *  0b0..Retains
11999  *  0b1..Powers off
12000  */
12001 #define CMC_SRAMRET_RET6(x)                      (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET6_SHIFT)) & CMC_SRAMRET_RET6_MASK)
12002 
12003 #define CMC_SRAMRET_RET7_MASK                    (0x80U)
12004 #define CMC_SRAMRET_RET7_SHIFT                   (7U)
12005 /*! RET7 - SRAM Retention
12006  *  0b0..Retains
12007  *  0b1..Powers off
12008  */
12009 #define CMC_SRAMRET_RET7(x)                      (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET7_SHIFT)) & CMC_SRAMRET_RET7_MASK)
12010 
12011 #define CMC_SRAMRET_RET8_MASK                    (0x100U)
12012 #define CMC_SRAMRET_RET8_SHIFT                   (8U)
12013 /*! RET8 - SRAM Retention
12014  *  0b0..Retains
12015  *  0b1..Powers off
12016  */
12017 #define CMC_SRAMRET_RET8(x)                      (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET8_SHIFT)) & CMC_SRAMRET_RET8_MASK)
12018 
12019 #define CMC_SRAMRET_RET9_MASK                    (0x200U)
12020 #define CMC_SRAMRET_RET9_SHIFT                   (9U)
12021 /*! RET9 - SRAM Retention
12022  *  0b0..Retains
12023  *  0b1..Powers off
12024  */
12025 #define CMC_SRAMRET_RET9(x)                      (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET9_SHIFT)) & CMC_SRAMRET_RET9_MASK)
12026 
12027 #define CMC_SRAMRET_RET10_MASK                   (0x400U)
12028 #define CMC_SRAMRET_RET10_SHIFT                  (10U)
12029 /*! RET10 - SRAM Retention
12030  *  0b0..Retains
12031  *  0b1..Powers off
12032  */
12033 #define CMC_SRAMRET_RET10(x)                     (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET10_SHIFT)) & CMC_SRAMRET_RET10_MASK)
12034 
12035 #define CMC_SRAMRET_RET11_MASK                   (0x800U)
12036 #define CMC_SRAMRET_RET11_SHIFT                  (11U)
12037 /*! RET11 - SRAM Retention
12038  *  0b0..Retains
12039  *  0b1..Powers off
12040  */
12041 #define CMC_SRAMRET_RET11(x)                     (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET11_SHIFT)) & CMC_SRAMRET_RET11_MASK)
12042 
12043 #define CMC_SRAMRET_RET12_MASK                   (0x1000U)
12044 #define CMC_SRAMRET_RET12_SHIFT                  (12U)
12045 /*! RET12 - SRAM Retention
12046  *  0b0..Retains
12047  *  0b1..Powers off
12048  */
12049 #define CMC_SRAMRET_RET12(x)                     (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET12_SHIFT)) & CMC_SRAMRET_RET12_MASK)
12050 
12051 #define CMC_SRAMRET_RET13_MASK                   (0x2000U)
12052 #define CMC_SRAMRET_RET13_SHIFT                  (13U)
12053 /*! RET13 - SRAM Retention
12054  *  0b0..Retains
12055  *  0b1..Powers off
12056  */
12057 #define CMC_SRAMRET_RET13(x)                     (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET13_SHIFT)) & CMC_SRAMRET_RET13_MASK)
12058 
12059 #define CMC_SRAMRET_RET14_MASK                   (0x4000U)
12060 #define CMC_SRAMRET_RET14_SHIFT                  (14U)
12061 /*! RET14 - SRAM Retention
12062  *  0b0..Retains
12063  *  0b1..Powers off
12064  */
12065 #define CMC_SRAMRET_RET14(x)                     (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET14_SHIFT)) & CMC_SRAMRET_RET14_MASK)
12066 
12067 #define CMC_SRAMRET_RET15_MASK                   (0x8000U)
12068 #define CMC_SRAMRET_RET15_SHIFT                  (15U)
12069 /*! RET15 - SRAM Retention
12070  *  0b0..Retains
12071  *  0b1..Powers off
12072  */
12073 #define CMC_SRAMRET_RET15(x)                     (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET15_SHIFT)) & CMC_SRAMRET_RET15_MASK)
12074 
12075 #define CMC_SRAMRET_RET16_MASK                   (0x10000U)
12076 #define CMC_SRAMRET_RET16_SHIFT                  (16U)
12077 /*! RET16 - SRAM Retention
12078  *  0b0..Retains
12079  *  0b1..Powers off
12080  */
12081 #define CMC_SRAMRET_RET16(x)                     (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET16_SHIFT)) & CMC_SRAMRET_RET16_MASK)
12082 
12083 #define CMC_SRAMRET_RET17_MASK                   (0x20000U)
12084 #define CMC_SRAMRET_RET17_SHIFT                  (17U)
12085 /*! RET17 - SRAM Retention
12086  *  0b0..Retains
12087  *  0b1..Powers off
12088  */
12089 #define CMC_SRAMRET_RET17(x)                     (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET17_SHIFT)) & CMC_SRAMRET_RET17_MASK)
12090 
12091 #define CMC_SRAMRET_RET18_MASK                   (0x40000U)
12092 #define CMC_SRAMRET_RET18_SHIFT                  (18U)
12093 /*! RET18 - SRAM Retention
12094  *  0b0..Retains
12095  *  0b1..Powers off
12096  */
12097 #define CMC_SRAMRET_RET18(x)                     (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET18_SHIFT)) & CMC_SRAMRET_RET18_MASK)
12098 
12099 #define CMC_SRAMRET_RET19_MASK                   (0x80000U)
12100 #define CMC_SRAMRET_RET19_SHIFT                  (19U)
12101 /*! RET19 - SRAM Retention
12102  *  0b0..Retains
12103  *  0b1..Powers off
12104  */
12105 #define CMC_SRAMRET_RET19(x)                     (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET19_SHIFT)) & CMC_SRAMRET_RET19_MASK)
12106 
12107 #define CMC_SRAMRET_RET20_MASK                   (0x100000U)
12108 #define CMC_SRAMRET_RET20_SHIFT                  (20U)
12109 /*! RET20 - SRAM Retention
12110  *  0b0..Retains
12111  *  0b1..Powers off
12112  */
12113 #define CMC_SRAMRET_RET20(x)                     (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET20_SHIFT)) & CMC_SRAMRET_RET20_MASK)
12114 
12115 #define CMC_SRAMRET_RET21_MASK                   (0x200000U)
12116 #define CMC_SRAMRET_RET21_SHIFT                  (21U)
12117 /*! RET21 - SRAM Retention
12118  *  0b0..Retains
12119  *  0b1..Powers off
12120  */
12121 #define CMC_SRAMRET_RET21(x)                     (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET21_SHIFT)) & CMC_SRAMRET_RET21_MASK)
12122 
12123 #define CMC_SRAMRET_RET22_MASK                   (0x400000U)
12124 #define CMC_SRAMRET_RET22_SHIFT                  (22U)
12125 /*! RET22 - SRAM Retention
12126  *  0b0..Retains
12127  *  0b1..Powers off
12128  */
12129 #define CMC_SRAMRET_RET22(x)                     (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET22_SHIFT)) & CMC_SRAMRET_RET22_MASK)
12130 
12131 #define CMC_SRAMRET_RET23_MASK                   (0x800000U)
12132 #define CMC_SRAMRET_RET23_SHIFT                  (23U)
12133 /*! RET23 - SRAM Retention
12134  *  0b0..Retains
12135  *  0b1..Powers off
12136  */
12137 #define CMC_SRAMRET_RET23(x)                     (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET23_SHIFT)) & CMC_SRAMRET_RET23_MASK)
12138 
12139 #define CMC_SRAMRET_RET24_MASK                   (0x1000000U)
12140 #define CMC_SRAMRET_RET24_SHIFT                  (24U)
12141 /*! RET24 - SRAM Retention
12142  *  0b0..Retains
12143  *  0b1..Powers off
12144  */
12145 #define CMC_SRAMRET_RET24(x)                     (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET24_SHIFT)) & CMC_SRAMRET_RET24_MASK)
12146 
12147 #define CMC_SRAMRET_RET25_MASK                   (0x2000000U)
12148 #define CMC_SRAMRET_RET25_SHIFT                  (25U)
12149 /*! RET25 - SRAM Retention
12150  *  0b0..Retains
12151  *  0b1..Powers off
12152  */
12153 #define CMC_SRAMRET_RET25(x)                     (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET25_SHIFT)) & CMC_SRAMRET_RET25_MASK)
12154 
12155 #define CMC_SRAMRET_RET26_MASK                   (0x4000000U)
12156 #define CMC_SRAMRET_RET26_SHIFT                  (26U)
12157 /*! RET26 - SRAM Retention
12158  *  0b0..Retains
12159  *  0b1..Powers off
12160  */
12161 #define CMC_SRAMRET_RET26(x)                     (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET26_SHIFT)) & CMC_SRAMRET_RET26_MASK)
12162 
12163 #define CMC_SRAMRET_RET27_MASK                   (0x8000000U)
12164 #define CMC_SRAMRET_RET27_SHIFT                  (27U)
12165 /*! RET27 - SRAM Retention
12166  *  0b0..Retains
12167  *  0b1..Powers off
12168  */
12169 #define CMC_SRAMRET_RET27(x)                     (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET27_SHIFT)) & CMC_SRAMRET_RET27_MASK)
12170 
12171 #define CMC_SRAMRET_RET28_MASK                   (0x10000000U)
12172 #define CMC_SRAMRET_RET28_SHIFT                  (28U)
12173 /*! RET28 - SRAM Retention
12174  *  0b0..Retains
12175  *  0b1..Powers off
12176  */
12177 #define CMC_SRAMRET_RET28(x)                     (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET28_SHIFT)) & CMC_SRAMRET_RET28_MASK)
12178 
12179 #define CMC_SRAMRET_RET29_MASK                   (0x20000000U)
12180 #define CMC_SRAMRET_RET29_SHIFT                  (29U)
12181 /*! RET29 - SRAM Retention
12182  *  0b0..Retains
12183  *  0b1..Powers off
12184  */
12185 #define CMC_SRAMRET_RET29(x)                     (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET29_SHIFT)) & CMC_SRAMRET_RET29_MASK)
12186 
12187 #define CMC_SRAMRET_RET30_MASK                   (0x40000000U)
12188 #define CMC_SRAMRET_RET30_SHIFT                  (30U)
12189 /*! RET30 - SRAM Retention
12190  *  0b0..Retains
12191  *  0b1..Powers off
12192  */
12193 #define CMC_SRAMRET_RET30(x)                     (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET30_SHIFT)) & CMC_SRAMRET_RET30_MASK)
12194 
12195 #define CMC_SRAMRET_RET31_MASK                   (0x80000000U)
12196 #define CMC_SRAMRET_RET31_SHIFT                  (31U)
12197 /*! RET31 - SRAM Retention
12198  *  0b0..Retains
12199  *  0b1..Powers off
12200  */
12201 #define CMC_SRAMRET_RET31(x)                     (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET31_SHIFT)) & CMC_SRAMRET_RET31_MASK)
12202 /*! @} */
12203 
12204 /* The count of CMC_SRAMRET */
12205 #define CMC_SRAMRET_COUNT                        (1U)
12206 
12207 /*! @name FLASHCR - Flash Control */
12208 /*! @{ */
12209 
12210 #define CMC_FLASHCR_FLASHDIS_MASK                (0x1U)
12211 #define CMC_FLASHCR_FLASHDIS_SHIFT               (0U)
12212 /*! FLASHDIS - Flash Disable
12213  *  0b0..No effect
12214  *  0b1..Flash memory is disabled
12215  */
12216 #define CMC_FLASHCR_FLASHDIS(x)                  (((uint32_t)(((uint32_t)(x)) << CMC_FLASHCR_FLASHDIS_SHIFT)) & CMC_FLASHCR_FLASHDIS_MASK)
12217 
12218 #define CMC_FLASHCR_FLASHDOZE_MASK               (0x2U)
12219 #define CMC_FLASHCR_FLASHDOZE_SHIFT              (1U)
12220 /*! FLASHDOZE - Flash Doze
12221  *  0b0..No effect
12222  *  0b1..Flash memory is disabled when core is sleeping (CKMODE > 0)
12223  */
12224 #define CMC_FLASHCR_FLASHDOZE(x)                 (((uint32_t)(((uint32_t)(x)) << CMC_FLASHCR_FLASHDOZE_SHIFT)) & CMC_FLASHCR_FLASHDOZE_MASK)
12225 /*! @} */
12226 
12227 /*! @name BSR - BootROM Status Register */
12228 /*! @{ */
12229 
12230 #define CMC_BSR_STAT_MASK                        (0xFFFFFFFFU)
12231 #define CMC_BSR_STAT_SHIFT                       (0U)
12232 /*! STAT - Provides status information written by the BootROM. */
12233 #define CMC_BSR_STAT(x)                          (((uint32_t)(((uint32_t)(x)) << CMC_BSR_STAT_SHIFT)) & CMC_BSR_STAT_MASK)
12234 /*! @} */
12235 
12236 /*! @name BLR - BootROM Lock Register */
12237 /*! @{ */
12238 
12239 #define CMC_BLR_LOCK_MASK                        (0x7U)
12240 #define CMC_BLR_LOCK_SHIFT                       (0U)
12241 /*! LOCK - Lock
12242  *  0b010..BootROM Status and Lock Registers can be written
12243  *  0b101..BootROM Status and Lock Registers cannot be written
12244  */
12245 #define CMC_BLR_LOCK(x)                          (((uint32_t)(((uint32_t)(x)) << CMC_BLR_LOCK_SHIFT)) & CMC_BLR_LOCK_MASK)
12246 /*! @} */
12247 
12248 /*! @name CORECTL - Core Control */
12249 /*! @{ */
12250 
12251 #define CMC_CORECTL_NPIE_MASK                    (0x1U)
12252 #define CMC_CORECTL_NPIE_SHIFT                   (0U)
12253 /*! NPIE - Non-maskable Pin Interrupt Enable
12254  *  0b0..Disables
12255  *  0b1..Enables
12256  */
12257 #define CMC_CORECTL_NPIE(x)                      (((uint32_t)(((uint32_t)(x)) << CMC_CORECTL_NPIE_SHIFT)) & CMC_CORECTL_NPIE_MASK)
12258 /*! @} */
12259 
12260 /*! @name DBGCTL - Debug Control */
12261 /*! @{ */
12262 
12263 #define CMC_DBGCTL_SOD_MASK                      (0x1U)
12264 #define CMC_DBGCTL_SOD_SHIFT                     (0U)
12265 /*! SOD - Sleep Or Debug
12266  *  0b0..Remains enabled
12267  *  0b1..Disabled
12268  */
12269 #define CMC_DBGCTL_SOD(x)                        (((uint32_t)(((uint32_t)(x)) << CMC_DBGCTL_SOD_SHIFT)) & CMC_DBGCTL_SOD_MASK)
12270 /*! @} */
12271 
12272 
12273 /*!
12274  * @}
12275  */ /* end of group CMC_Register_Masks */
12276 
12277 
12278 /* CMC - Peripheral instance base addresses */
12279 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
12280   /** Peripheral CMC0 base address */
12281   #define CMC0_BASE                                (0x50048000u)
12282   /** Peripheral CMC0 base address */
12283   #define CMC0_BASE_NS                             (0x40048000u)
12284   /** Peripheral CMC0 base pointer */
12285   #define CMC0                                     ((CMC_Type *)CMC0_BASE)
12286   /** Peripheral CMC0 base pointer */
12287   #define CMC0_NS                                  ((CMC_Type *)CMC0_BASE_NS)
12288   /** Array initializer of CMC peripheral base addresses */
12289   #define CMC_BASE_ADDRS                           { CMC0_BASE }
12290   /** Array initializer of CMC peripheral base pointers */
12291   #define CMC_BASE_PTRS                            { CMC0 }
12292   /** Array initializer of CMC peripheral base addresses */
12293   #define CMC_BASE_ADDRS_NS                        { CMC0_BASE_NS }
12294   /** Array initializer of CMC peripheral base pointers */
12295   #define CMC_BASE_PTRS_NS                         { CMC0_NS }
12296 #else
12297   /** Peripheral CMC0 base address */
12298   #define CMC0_BASE                                (0x40048000u)
12299   /** Peripheral CMC0 base pointer */
12300   #define CMC0                                     ((CMC_Type *)CMC0_BASE)
12301   /** Array initializer of CMC peripheral base addresses */
12302   #define CMC_BASE_ADDRS                           { CMC0_BASE }
12303   /** Array initializer of CMC peripheral base pointers */
12304   #define CMC_BASE_PTRS                            { CMC0 }
12305 #endif
12306 /* Backward compatibility for CMC */
12307 #define CMC_SRAMDIS_DIS_MASK                     (0xFFFFFFFFU)
12308 #define CMC_SRAMDIS_DIS_SHIFT                    (0U)
12309 /*! DIS - SRAM Disable */
12310 #define CMC_SRAMDIS_DIS(x)                       (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS_SHIFT)) & CMC_SRAMDIS_DIS_MASK)
12311 
12312 #define CMC_SRAMRET_RET_MASK                     (0xFFFFFFFFU)
12313 #define CMC_SRAMRET_RET_SHIFT                    (0U)
12314 /*! RET - SRAM Retention */
12315 #define CMC_SRAMRET_RET(x)                       (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET_SHIFT)) & CMC_SRAMRET_RET_MASK)
12316 
12317 
12318 /*!
12319  * @}
12320  */ /* end of group CMC_Peripheral_Access_Layer */
12321 
12322 
12323 /* ----------------------------------------------------------------------------
12324    -- CRC Peripheral Access Layer
12325    ---------------------------------------------------------------------------- */
12326 
12327 /*!
12328  * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
12329  * @{
12330  */
12331 
12332 /** CRC - Register Layout Typedef */
12333 typedef struct {
12334   union {                                          /* offset: 0x0 */
12335     struct {                                         /* offset: 0x0 */
12336       __IO uint8_t DATALL;                             /**< CRC_DATALL register, offset: 0x0 */
12337       __IO uint8_t DATALU;                             /**< CRC_DATALU register, offset: 0x1 */
12338       __IO uint8_t DATAHL;                             /**< CRC_DATAHL register, offset: 0x2 */
12339       __IO uint8_t DATAHU;                             /**< CRC_DATAHU register, offset: 0x3 */
12340     } ACCESS8BIT;
12341     struct {                                         /* offset: 0x0 */
12342       __IO uint16_t DATAL;                             /**< CRC_DATAL register, offset: 0x0 */
12343       __IO uint16_t DATAH;                             /**< CRC_DATAH register, offset: 0x2 */
12344     } ACCESS16BIT;
12345     __IO uint32_t DATA;                              /**< Data, offset: 0x0 */
12346   };
12347   union {                                          /* offset: 0x4 */
12348     struct {                                         /* offset: 0x4 */
12349       __IO uint8_t GPOLYLL;                            /**< CRC_GPOLYLL register, offset: 0x4 */
12350       __IO uint8_t GPOLYLU;                            /**< CRC_GPOLYLU register, offset: 0x5 */
12351       __IO uint8_t GPOLYHL;                            /**< CRC_GPOLYHL register, offset: 0x6 */
12352       __IO uint8_t GPOLYHU;                            /**< CRC_GPOLYHU register, offset: 0x7 */
12353     } GPOLY_ACCESS8BIT;
12354     struct {                                         /* offset: 0x4 */
12355       __IO uint16_t GPOLYL;                            /**< CRC_GPOLYL register, offset: 0x4 */
12356       __IO uint16_t GPOLYH;                            /**< CRC_GPOLYH register, offset: 0x6 */
12357     } GPOLY_ACCESS16BIT;
12358     __IO uint32_t GPOLY;                             /**< Polynomial, offset: 0x4 */
12359   };
12360   union {                                          /* offset: 0x8 */
12361     struct {                                         /* offset: 0x8 */
12362            uint8_t RESERVED_0[3];
12363       __IO uint8_t CTRLHU;                             /**< CRC_CTRLHU register, offset: 0xB */
12364     } CTRL_ACCESS8BIT;
12365     __IO uint32_t CTRL;                              /**< Control, offset: 0x8 */
12366   };
12367 } CRC_Type;
12368 
12369 /* ----------------------------------------------------------------------------
12370    -- CRC Register Masks
12371    ---------------------------------------------------------------------------- */
12372 
12373 /*!
12374  * @addtogroup CRC_Register_Masks CRC Register Masks
12375  * @{
12376  */
12377 
12378 /*! @name DATALL - CRC_DATALL register */
12379 /*! @{ */
12380 
12381 #define CRC_DATALL_DATALL_MASK                   (0xFFU)
12382 #define CRC_DATALL_DATALL_SHIFT                  (0U)
12383 #define CRC_DATALL_DATALL(x)                     (((uint8_t)(((uint8_t)(x)) << CRC_DATALL_DATALL_SHIFT)) & CRC_DATALL_DATALL_MASK)
12384 /*! @} */
12385 
12386 /*! @name DATALU - CRC_DATALU register */
12387 /*! @{ */
12388 
12389 #define CRC_DATALU_DATALU_MASK                   (0xFFU)
12390 #define CRC_DATALU_DATALU_SHIFT                  (0U)
12391 #define CRC_DATALU_DATALU(x)                     (((uint8_t)(((uint8_t)(x)) << CRC_DATALU_DATALU_SHIFT)) & CRC_DATALU_DATALU_MASK)
12392 /*! @} */
12393 
12394 /*! @name DATAHL - CRC_DATAHL register */
12395 /*! @{ */
12396 
12397 #define CRC_DATAHL_DATAHL_MASK                   (0xFFU)
12398 #define CRC_DATAHL_DATAHL_SHIFT                  (0U)
12399 #define CRC_DATAHL_DATAHL(x)                     (((uint8_t)(((uint8_t)(x)) << CRC_DATAHL_DATAHL_SHIFT)) & CRC_DATAHL_DATAHL_MASK)
12400 /*! @} */
12401 
12402 /*! @name DATAHU - CRC_DATAHU register */
12403 /*! @{ */
12404 
12405 #define CRC_DATAHU_DATAHU_MASK                   (0xFFU)
12406 #define CRC_DATAHU_DATAHU_SHIFT                  (0U)
12407 #define CRC_DATAHU_DATAHU(x)                     (((uint8_t)(((uint8_t)(x)) << CRC_DATAHU_DATAHU_SHIFT)) & CRC_DATAHU_DATAHU_MASK)
12408 /*! @} */
12409 
12410 /*! @name DATAL - CRC_DATAL register */
12411 /*! @{ */
12412 
12413 #define CRC_DATAL_DATAL_MASK                     (0xFFFFU)
12414 #define CRC_DATAL_DATAL_SHIFT                    (0U)
12415 #define CRC_DATAL_DATAL(x)                       (((uint16_t)(((uint16_t)(x)) << CRC_DATAL_DATAL_SHIFT)) & CRC_DATAL_DATAL_MASK)
12416 /*! @} */
12417 
12418 /*! @name DATAH - CRC_DATAH register */
12419 /*! @{ */
12420 
12421 #define CRC_DATAH_DATAH_MASK                     (0xFFFFU)
12422 #define CRC_DATAH_DATAH_SHIFT                    (0U)
12423 #define CRC_DATAH_DATAH(x)                       (((uint16_t)(((uint16_t)(x)) << CRC_DATAH_DATAH_SHIFT)) & CRC_DATAH_DATAH_MASK)
12424 /*! @} */
12425 
12426 /*! @name DATA - Data */
12427 /*! @{ */
12428 
12429 #define CRC_DATA_LL_MASK                         (0xFFU)
12430 #define CRC_DATA_LL_SHIFT                        (0U)
12431 /*! LL - Lower Part of Low Byte */
12432 #define CRC_DATA_LL(x)                           (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LL_SHIFT)) & CRC_DATA_LL_MASK)
12433 
12434 #define CRC_DATA_LU_MASK                         (0xFF00U)
12435 #define CRC_DATA_LU_SHIFT                        (8U)
12436 /*! LU - Upper Part of Low Byte */
12437 #define CRC_DATA_LU(x)                           (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LU_SHIFT)) & CRC_DATA_LU_MASK)
12438 
12439 #define CRC_DATA_HL_MASK                         (0xFF0000U)
12440 #define CRC_DATA_HL_SHIFT                        (16U)
12441 /*! HL - Lower Part of High Byte */
12442 #define CRC_DATA_HL(x)                           (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HL_SHIFT)) & CRC_DATA_HL_MASK)
12443 
12444 #define CRC_DATA_HU_MASK                         (0xFF000000U)
12445 #define CRC_DATA_HU_SHIFT                        (24U)
12446 /*! HU - Upper Part of High Byte */
12447 #define CRC_DATA_HU(x)                           (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HU_SHIFT)) & CRC_DATA_HU_MASK)
12448 /*! @} */
12449 
12450 /*! @name GPOLYLL - CRC_GPOLYLL register */
12451 /*! @{ */
12452 
12453 #define CRC_GPOLYLL_GPOLYLL_MASK                 (0xFFU)
12454 #define CRC_GPOLYLL_GPOLYLL_SHIFT                (0U)
12455 #define CRC_GPOLYLL_GPOLYLL(x)                   (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLL_GPOLYLL_SHIFT)) & CRC_GPOLYLL_GPOLYLL_MASK)
12456 /*! @} */
12457 
12458 /*! @name GPOLYLU - CRC_GPOLYLU register */
12459 /*! @{ */
12460 
12461 #define CRC_GPOLYLU_GPOLYLU_MASK                 (0xFFU)
12462 #define CRC_GPOLYLU_GPOLYLU_SHIFT                (0U)
12463 #define CRC_GPOLYLU_GPOLYLU(x)                   (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLU_GPOLYLU_SHIFT)) & CRC_GPOLYLU_GPOLYLU_MASK)
12464 /*! @} */
12465 
12466 /*! @name GPOLYHL - CRC_GPOLYHL register */
12467 /*! @{ */
12468 
12469 #define CRC_GPOLYHL_GPOLYHL_MASK                 (0xFFU)
12470 #define CRC_GPOLYHL_GPOLYHL_SHIFT                (0U)
12471 #define CRC_GPOLYHL_GPOLYHL(x)                   (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHL_GPOLYHL_SHIFT)) & CRC_GPOLYHL_GPOLYHL_MASK)
12472 /*! @} */
12473 
12474 /*! @name GPOLYHU - CRC_GPOLYHU register */
12475 /*! @{ */
12476 
12477 #define CRC_GPOLYHU_GPOLYHU_MASK                 (0xFFU)
12478 #define CRC_GPOLYHU_GPOLYHU_SHIFT                (0U)
12479 #define CRC_GPOLYHU_GPOLYHU(x)                   (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHU_GPOLYHU_SHIFT)) & CRC_GPOLYHU_GPOLYHU_MASK)
12480 /*! @} */
12481 
12482 /*! @name GPOLYL - CRC_GPOLYL register */
12483 /*! @{ */
12484 
12485 #define CRC_GPOLYL_GPOLYL_MASK                   (0xFFFFU)
12486 #define CRC_GPOLYL_GPOLYL_SHIFT                  (0U)
12487 #define CRC_GPOLYL_GPOLYL(x)                     (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYL_GPOLYL_SHIFT)) & CRC_GPOLYL_GPOLYL_MASK)
12488 /*! @} */
12489 
12490 /*! @name GPOLYH - CRC_GPOLYH register */
12491 /*! @{ */
12492 
12493 #define CRC_GPOLYH_GPOLYH_MASK                   (0xFFFFU)
12494 #define CRC_GPOLYH_GPOLYH_SHIFT                  (0U)
12495 #define CRC_GPOLYH_GPOLYH(x)                     (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYH_GPOLYH_SHIFT)) & CRC_GPOLYH_GPOLYH_MASK)
12496 /*! @} */
12497 
12498 /*! @name GPOLY - Polynomial */
12499 /*! @{ */
12500 
12501 #define CRC_GPOLY_LOW_MASK                       (0xFFFFU)
12502 #define CRC_GPOLY_LOW_SHIFT                      (0U)
12503 /*! LOW - Low Half-Word */
12504 #define CRC_GPOLY_LOW(x)                         (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_LOW_SHIFT)) & CRC_GPOLY_LOW_MASK)
12505 
12506 #define CRC_GPOLY_HIGH_MASK                      (0xFFFF0000U)
12507 #define CRC_GPOLY_HIGH_SHIFT                     (16U)
12508 /*! HIGH - High Half-Word */
12509 #define CRC_GPOLY_HIGH(x)                        (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_HIGH_SHIFT)) & CRC_GPOLY_HIGH_MASK)
12510 /*! @} */
12511 
12512 /*! @name CTRLHU - CRC_CTRLHU register */
12513 /*! @{ */
12514 
12515 #define CRC_CTRLHU_TCRC_MASK                     (0x1U)
12516 #define CRC_CTRLHU_TCRC_SHIFT                    (0U)
12517 /*! TCRC - TCRC
12518  *  0b0..16 bits
12519  *  0b1..32 bits
12520  */
12521 #define CRC_CTRLHU_TCRC(x)                       (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TCRC_SHIFT)) & CRC_CTRLHU_TCRC_MASK)
12522 
12523 #define CRC_CTRLHU_WAS_MASK                      (0x2U)
12524 #define CRC_CTRLHU_WAS_SHIFT                     (1U)
12525 /*! WAS - Write as Seed
12526  *  0b0..Data values
12527  *  0b1..Seed values
12528  */
12529 #define CRC_CTRLHU_WAS(x)                        (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_WAS_SHIFT)) & CRC_CTRLHU_WAS_MASK)
12530 
12531 #define CRC_CTRLHU_FXOR_MASK                     (0x4U)
12532 #define CRC_CTRLHU_FXOR_SHIFT                    (2U)
12533 /*! FXOR - Complement Read of CRC Data Register
12534  *  0b0..Disables XOR on reading data.
12535  *  0b1..Inverts or complements the read value of the CRC Data.
12536  */
12537 #define CRC_CTRLHU_FXOR(x)                       (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_FXOR_SHIFT)) & CRC_CTRLHU_FXOR_MASK)
12538 
12539 #define CRC_CTRLHU_TOTR_MASK                     (0x30U)
12540 #define CRC_CTRLHU_TOTR_SHIFT                    (4U)
12541 /*! TOTR - Transpose Type for Read
12542  *  0b00..No transposition
12543  *  0b01..Bits in bytes are transposed, but bytes are not transposed.
12544  *  0b10..Both bits in bytes and bytes are transposed.
12545  *  0b11..Only bytes are transposed, no bits in a byte are transposed.
12546  */
12547 #define CRC_CTRLHU_TOTR(x)                       (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOTR_SHIFT)) & CRC_CTRLHU_TOTR_MASK)
12548 
12549 #define CRC_CTRLHU_TOT_MASK                      (0xC0U)
12550 #define CRC_CTRLHU_TOT_SHIFT                     (6U)
12551 /*! TOT - Transpose Type for Write
12552  *  0b00..No transposition
12553  *  0b01..Bits in bytes are transposed, but bytes are not transposed.
12554  *  0b10..Both bits in bytes and bytes are transposed.
12555  *  0b11..Only bytes are transposed, no bits in a byte are transposed.
12556  */
12557 #define CRC_CTRLHU_TOT(x)                        (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOT_SHIFT)) & CRC_CTRLHU_TOT_MASK)
12558 /*! @} */
12559 
12560 /*! @name CTRL - Control */
12561 /*! @{ */
12562 
12563 #define CRC_CTRL_TCRC_MASK                       (0x1000000U)
12564 #define CRC_CTRL_TCRC_SHIFT                      (24U)
12565 /*! TCRC - TCRC
12566  *  0b0..16 bits
12567  *  0b1..32 bits
12568  */
12569 #define CRC_CTRL_TCRC(x)                         (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TCRC_SHIFT)) & CRC_CTRL_TCRC_MASK)
12570 
12571 #define CRC_CTRL_WAS_MASK                        (0x2000000U)
12572 #define CRC_CTRL_WAS_SHIFT                       (25U)
12573 /*! WAS - Write as Seed
12574  *  0b0..Data values
12575  *  0b1..Seed values
12576  */
12577 #define CRC_CTRL_WAS(x)                          (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_WAS_SHIFT)) & CRC_CTRL_WAS_MASK)
12578 
12579 #define CRC_CTRL_FXOR_MASK                       (0x4000000U)
12580 #define CRC_CTRL_FXOR_SHIFT                      (26U)
12581 /*! FXOR - Complement Read of CRC Data Register
12582  *  0b0..Disables XOR on reading data.
12583  *  0b1..Inverts or complements the read value of the CRC Data.
12584  */
12585 #define CRC_CTRL_FXOR(x)                         (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_FXOR_SHIFT)) & CRC_CTRL_FXOR_MASK)
12586 
12587 #define CRC_CTRL_TOTR_MASK                       (0x30000000U)
12588 #define CRC_CTRL_TOTR_SHIFT                      (28U)
12589 /*! TOTR - Transpose Type for Read
12590  *  0b00..No transposition
12591  *  0b01..Bits in bytes are transposed, but bytes are not transposed.
12592  *  0b10..Both bits in bytes and bytes are transposed.
12593  *  0b11..Only bytes are transposed, no bits in a byte are transposed.
12594  */
12595 #define CRC_CTRL_TOTR(x)                         (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOTR_SHIFT)) & CRC_CTRL_TOTR_MASK)
12596 
12597 #define CRC_CTRL_TOT_MASK                        (0xC0000000U)
12598 #define CRC_CTRL_TOT_SHIFT                       (30U)
12599 /*! TOT - Transpose Type for Write
12600  *  0b00..No transposition
12601  *  0b01..Bits in bytes are transposed, but bytes are not transposed.
12602  *  0b10..Both bits in bytes and bytes are transposed.
12603  *  0b11..Only bytes are transposed, no bits in a byte are transposed.
12604  */
12605 #define CRC_CTRL_TOT(x)                          (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOT_SHIFT)) & CRC_CTRL_TOT_MASK)
12606 /*! @} */
12607 
12608 
12609 /*!
12610  * @}
12611  */ /* end of group CRC_Register_Masks */
12612 
12613 
12614 /* CRC - Peripheral instance base addresses */
12615 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
12616   /** Peripheral CRC0 base address */
12617   #define CRC0_BASE                                (0x500CB000u)
12618   /** Peripheral CRC0 base address */
12619   #define CRC0_BASE_NS                             (0x400CB000u)
12620   /** Peripheral CRC0 base pointer */
12621   #define CRC0                                     ((CRC_Type *)CRC0_BASE)
12622   /** Peripheral CRC0 base pointer */
12623   #define CRC0_NS                                  ((CRC_Type *)CRC0_BASE_NS)
12624   /** Array initializer of CRC peripheral base addresses */
12625   #define CRC_BASE_ADDRS                           { CRC0_BASE }
12626   /** Array initializer of CRC peripheral base pointers */
12627   #define CRC_BASE_PTRS                            { CRC0 }
12628   /** Array initializer of CRC peripheral base addresses */
12629   #define CRC_BASE_ADDRS_NS                        { CRC0_BASE_NS }
12630   /** Array initializer of CRC peripheral base pointers */
12631   #define CRC_BASE_PTRS_NS                         { CRC0_NS }
12632 #else
12633   /** Peripheral CRC0 base address */
12634   #define CRC0_BASE                                (0x400CB000u)
12635   /** Peripheral CRC0 base pointer */
12636   #define CRC0                                     ((CRC_Type *)CRC0_BASE)
12637   /** Array initializer of CRC peripheral base addresses */
12638   #define CRC_BASE_ADDRS                           { CRC0_BASE }
12639   /** Array initializer of CRC peripheral base pointers */
12640   #define CRC_BASE_PTRS                            { CRC0 }
12641 #endif
12642 
12643 /*!
12644  * @}
12645  */ /* end of group CRC_Peripheral_Access_Layer */
12646 
12647 
12648 /* ----------------------------------------------------------------------------
12649    -- CTIMER Peripheral Access Layer
12650    ---------------------------------------------------------------------------- */
12651 
12652 /*!
12653  * @addtogroup CTIMER_Peripheral_Access_Layer CTIMER Peripheral Access Layer
12654  * @{
12655  */
12656 
12657 /** CTIMER - Register Layout Typedef */
12658 typedef struct {
12659   __IO uint32_t IR;                                /**< Interrupt, offset: 0x0 */
12660   __IO uint32_t TCR;                               /**< Timer Control, offset: 0x4 */
12661   __IO uint32_t TC;                                /**< Timer Counter, offset: 0x8 */
12662   __IO uint32_t PR;                                /**< Prescale, offset: 0xC */
12663   __IO uint32_t PC;                                /**< Prescale Counter, offset: 0x10 */
12664   __IO uint32_t MCR;                               /**< Match Control, offset: 0x14 */
12665   __IO uint32_t MR[4];                             /**< Match, array offset: 0x18, array step: 0x4 */
12666   __IO uint32_t CCR;                               /**< Capture Control, offset: 0x28 */
12667   __I  uint32_t CR[4];                             /**< Capture, array offset: 0x2C, array step: 0x4 */
12668   __IO uint32_t EMR;                               /**< External Match, offset: 0x3C */
12669        uint8_t RESERVED_0[48];
12670   __IO uint32_t CTCR;                              /**< Count Control, offset: 0x70 */
12671   __IO uint32_t PWMC;                              /**< PWM Control, offset: 0x74 */
12672   __IO uint32_t MSR[4];                            /**< Match Shadow, array offset: 0x78, array step: 0x4 */
12673 } CTIMER_Type;
12674 
12675 /* ----------------------------------------------------------------------------
12676    -- CTIMER Register Masks
12677    ---------------------------------------------------------------------------- */
12678 
12679 /*!
12680  * @addtogroup CTIMER_Register_Masks CTIMER Register Masks
12681  * @{
12682  */
12683 
12684 /*! @name IR - Interrupt */
12685 /*! @{ */
12686 
12687 #define CTIMER_IR_MR0INT_MASK                    (0x1U)
12688 #define CTIMER_IR_MR0INT_SHIFT                   (0U)
12689 /*! MR0INT - Interrupt Flag for Match Channel 0 Event */
12690 #define CTIMER_IR_MR0INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR0INT_SHIFT)) & CTIMER_IR_MR0INT_MASK)
12691 
12692 #define CTIMER_IR_MR1INT_MASK                    (0x2U)
12693 #define CTIMER_IR_MR1INT_SHIFT                   (1U)
12694 /*! MR1INT - Interrupt Flag for Match Channel 1 Event */
12695 #define CTIMER_IR_MR1INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR1INT_SHIFT)) & CTIMER_IR_MR1INT_MASK)
12696 
12697 #define CTIMER_IR_MR2INT_MASK                    (0x4U)
12698 #define CTIMER_IR_MR2INT_SHIFT                   (2U)
12699 /*! MR2INT - Interrupt Flag for Match Channel 2 Event */
12700 #define CTIMER_IR_MR2INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR2INT_SHIFT)) & CTIMER_IR_MR2INT_MASK)
12701 
12702 #define CTIMER_IR_MR3INT_MASK                    (0x8U)
12703 #define CTIMER_IR_MR3INT_SHIFT                   (3U)
12704 /*! MR3INT - Interrupt Flag for Match Channel 3 Event */
12705 #define CTIMER_IR_MR3INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR3INT_SHIFT)) & CTIMER_IR_MR3INT_MASK)
12706 
12707 #define CTIMER_IR_CR0INT_MASK                    (0x10U)
12708 #define CTIMER_IR_CR0INT_SHIFT                   (4U)
12709 /*! CR0INT - Interrupt Flag for Capture Channel 0 Event */
12710 #define CTIMER_IR_CR0INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR0INT_SHIFT)) & CTIMER_IR_CR0INT_MASK)
12711 
12712 #define CTIMER_IR_CR1INT_MASK                    (0x20U)
12713 #define CTIMER_IR_CR1INT_SHIFT                   (5U)
12714 /*! CR1INT - Interrupt Flag for Capture Channel 1 Event */
12715 #define CTIMER_IR_CR1INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR1INT_SHIFT)) & CTIMER_IR_CR1INT_MASK)
12716 
12717 #define CTIMER_IR_CR2INT_MASK                    (0x40U)
12718 #define CTIMER_IR_CR2INT_SHIFT                   (6U)
12719 /*! CR2INT - Interrupt Flag for Capture Channel 2 Event */
12720 #define CTIMER_IR_CR2INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR2INT_SHIFT)) & CTIMER_IR_CR2INT_MASK)
12721 
12722 #define CTIMER_IR_CR3INT_MASK                    (0x80U)
12723 #define CTIMER_IR_CR3INT_SHIFT                   (7U)
12724 /*! CR3INT - Interrupt Flag for Capture Channel 3 Event */
12725 #define CTIMER_IR_CR3INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR3INT_SHIFT)) & CTIMER_IR_CR3INT_MASK)
12726 /*! @} */
12727 
12728 /*! @name TCR - Timer Control */
12729 /*! @{ */
12730 
12731 #define CTIMER_TCR_CEN_MASK                      (0x1U)
12732 #define CTIMER_TCR_CEN_SHIFT                     (0U)
12733 /*! CEN - Counter Enable
12734  *  0b0..Disable
12735  *  0b1..Enable
12736  */
12737 #define CTIMER_TCR_CEN(x)                        (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CEN_SHIFT)) & CTIMER_TCR_CEN_MASK)
12738 
12739 #define CTIMER_TCR_CRST_MASK                     (0x2U)
12740 #define CTIMER_TCR_CRST_SHIFT                    (1U)
12741 /*! CRST - Counter Reset Enable
12742  *  0b0..Disable
12743  *  0b1..Enable
12744  */
12745 #define CTIMER_TCR_CRST(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CRST_SHIFT)) & CTIMER_TCR_CRST_MASK)
12746 
12747 #define CTIMER_TCR_AGCEN_MASK                    (0x10U)
12748 #define CTIMER_TCR_AGCEN_SHIFT                   (4U)
12749 /*! AGCEN - Allow Global Count Enable
12750  *  0b0..Disable
12751  *  0b1..Enable
12752  */
12753 #define CTIMER_TCR_AGCEN(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_AGCEN_SHIFT)) & CTIMER_TCR_AGCEN_MASK)
12754 
12755 #define CTIMER_TCR_ATCEN_MASK                    (0x20U)
12756 #define CTIMER_TCR_ATCEN_SHIFT                   (5U)
12757 /*! ATCEN - Allow Trigger Count Enable
12758  *  0b0..Disable
12759  *  0b1..Enable
12760  */
12761 #define CTIMER_TCR_ATCEN(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_ATCEN_SHIFT)) & CTIMER_TCR_ATCEN_MASK)
12762 /*! @} */
12763 
12764 /*! @name TC - Timer Counter */
12765 /*! @{ */
12766 
12767 #define CTIMER_TC_TCVAL_MASK                     (0xFFFFFFFFU)
12768 #define CTIMER_TC_TCVAL_SHIFT                    (0U)
12769 /*! TCVAL - Timer Counter Value */
12770 #define CTIMER_TC_TCVAL(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_TC_TCVAL_SHIFT)) & CTIMER_TC_TCVAL_MASK)
12771 /*! @} */
12772 
12773 /*! @name PR - Prescale */
12774 /*! @{ */
12775 
12776 #define CTIMER_PR_PRVAL_MASK                     (0xFFFFFFFFU)
12777 #define CTIMER_PR_PRVAL_SHIFT                    (0U)
12778 /*! PRVAL - Prescale Reload Value */
12779 #define CTIMER_PR_PRVAL(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_PR_PRVAL_SHIFT)) & CTIMER_PR_PRVAL_MASK)
12780 /*! @} */
12781 
12782 /*! @name PC - Prescale Counter */
12783 /*! @{ */
12784 
12785 #define CTIMER_PC_PCVAL_MASK                     (0xFFFFFFFFU)
12786 #define CTIMER_PC_PCVAL_SHIFT                    (0U)
12787 /*! PCVAL - Prescale Counter Value */
12788 #define CTIMER_PC_PCVAL(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_PC_PCVAL_SHIFT)) & CTIMER_PC_PCVAL_MASK)
12789 /*! @} */
12790 
12791 /*! @name MCR - Match Control */
12792 /*! @{ */
12793 
12794 #define CTIMER_MCR_MR0I_MASK                     (0x1U)
12795 #define CTIMER_MCR_MR0I_SHIFT                    (0U)
12796 /*! MR0I - Interrupt on MR0
12797  *  0b0..Does not generate
12798  *  0b1..Generates
12799  */
12800 #define CTIMER_MCR_MR0I(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK)
12801 
12802 #define CTIMER_MCR_MR0R_MASK                     (0x2U)
12803 #define CTIMER_MCR_MR0R_SHIFT                    (1U)
12804 /*! MR0R - Reset on MR0
12805  *  0b0..Does not reset
12806  *  0b1..Resets
12807  */
12808 #define CTIMER_MCR_MR0R(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0R_SHIFT)) & CTIMER_MCR_MR0R_MASK)
12809 
12810 #define CTIMER_MCR_MR0S_MASK                     (0x4U)
12811 #define CTIMER_MCR_MR0S_SHIFT                    (2U)
12812 /*! MR0S - Stop on MR0
12813  *  0b0..Does not stop
12814  *  0b1..Stops
12815  */
12816 #define CTIMER_MCR_MR0S(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0S_SHIFT)) & CTIMER_MCR_MR0S_MASK)
12817 
12818 #define CTIMER_MCR_MR1I_MASK                     (0x8U)
12819 #define CTIMER_MCR_MR1I_SHIFT                    (3U)
12820 /*! MR1I - Interrupt on MR1
12821  *  0b0..Does not generate
12822  *  0b1..Generates
12823  */
12824 #define CTIMER_MCR_MR1I(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1I_SHIFT)) & CTIMER_MCR_MR1I_MASK)
12825 
12826 #define CTIMER_MCR_MR1R_MASK                     (0x10U)
12827 #define CTIMER_MCR_MR1R_SHIFT                    (4U)
12828 /*! MR1R - Reset on MR1
12829  *  0b0..Does not reset
12830  *  0b1..Resets
12831  */
12832 #define CTIMER_MCR_MR1R(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1R_SHIFT)) & CTIMER_MCR_MR1R_MASK)
12833 
12834 #define CTIMER_MCR_MR1S_MASK                     (0x20U)
12835 #define CTIMER_MCR_MR1S_SHIFT                    (5U)
12836 /*! MR1S - Stop on MR1
12837  *  0b0..Does not stop
12838  *  0b1..Stops
12839  */
12840 #define CTIMER_MCR_MR1S(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1S_SHIFT)) & CTIMER_MCR_MR1S_MASK)
12841 
12842 #define CTIMER_MCR_MR2I_MASK                     (0x40U)
12843 #define CTIMER_MCR_MR2I_SHIFT                    (6U)
12844 /*! MR2I - Interrupt on MR2
12845  *  0b0..Does not generate
12846  *  0b1..Generates
12847  */
12848 #define CTIMER_MCR_MR2I(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2I_SHIFT)) & CTIMER_MCR_MR2I_MASK)
12849 
12850 #define CTIMER_MCR_MR2R_MASK                     (0x80U)
12851 #define CTIMER_MCR_MR2R_SHIFT                    (7U)
12852 /*! MR2R - Reset on MR2
12853  *  0b0..Does not reset
12854  *  0b1..Resets
12855  */
12856 #define CTIMER_MCR_MR2R(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2R_SHIFT)) & CTIMER_MCR_MR2R_MASK)
12857 
12858 #define CTIMER_MCR_MR2S_MASK                     (0x100U)
12859 #define CTIMER_MCR_MR2S_SHIFT                    (8U)
12860 /*! MR2S - Stop on MR2
12861  *  0b0..Does not stop
12862  *  0b1..Stops
12863  */
12864 #define CTIMER_MCR_MR2S(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2S_SHIFT)) & CTIMER_MCR_MR2S_MASK)
12865 
12866 #define CTIMER_MCR_MR3I_MASK                     (0x200U)
12867 #define CTIMER_MCR_MR3I_SHIFT                    (9U)
12868 /*! MR3I - Interrupt on MR3
12869  *  0b0..Does not generate
12870  *  0b1..Generates
12871  */
12872 #define CTIMER_MCR_MR3I(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3I_SHIFT)) & CTIMER_MCR_MR3I_MASK)
12873 
12874 #define CTIMER_MCR_MR3R_MASK                     (0x400U)
12875 #define CTIMER_MCR_MR3R_SHIFT                    (10U)
12876 /*! MR3R - Reset on MR3
12877  *  0b0..Does not reset
12878  *  0b1..Resets
12879  */
12880 #define CTIMER_MCR_MR3R(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3R_SHIFT)) & CTIMER_MCR_MR3R_MASK)
12881 
12882 #define CTIMER_MCR_MR3S_MASK                     (0x800U)
12883 #define CTIMER_MCR_MR3S_SHIFT                    (11U)
12884 /*! MR3S - Stop on MR3
12885  *  0b0..Does not stop
12886  *  0b1..Stops
12887  */
12888 #define CTIMER_MCR_MR3S(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3S_SHIFT)) & CTIMER_MCR_MR3S_MASK)
12889 
12890 #define CTIMER_MCR_MR0RL_MASK                    (0x1000000U)
12891 #define CTIMER_MCR_MR0RL_SHIFT                   (24U)
12892 /*! MR0RL - Reload MR
12893  *  0b0..Does not reload
12894  *  0b1..Reloads
12895  */
12896 #define CTIMER_MCR_MR0RL(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0RL_SHIFT)) & CTIMER_MCR_MR0RL_MASK)
12897 
12898 #define CTIMER_MCR_MR1RL_MASK                    (0x2000000U)
12899 #define CTIMER_MCR_MR1RL_SHIFT                   (25U)
12900 /*! MR1RL - Reload MR
12901  *  0b0..Does not reload
12902  *  0b1..Reloads
12903  */
12904 #define CTIMER_MCR_MR1RL(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1RL_SHIFT)) & CTIMER_MCR_MR1RL_MASK)
12905 
12906 #define CTIMER_MCR_MR2RL_MASK                    (0x4000000U)
12907 #define CTIMER_MCR_MR2RL_SHIFT                   (26U)
12908 /*! MR2RL - Reload MR
12909  *  0b0..Does not reload
12910  *  0b1..Reloads
12911  */
12912 #define CTIMER_MCR_MR2RL(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2RL_SHIFT)) & CTIMER_MCR_MR2RL_MASK)
12913 
12914 #define CTIMER_MCR_MR3RL_MASK                    (0x8000000U)
12915 #define CTIMER_MCR_MR3RL_SHIFT                   (27U)
12916 /*! MR3RL - Reload MR
12917  *  0b0..Does not reload
12918  *  0b1..Reloads
12919  */
12920 #define CTIMER_MCR_MR3RL(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3RL_SHIFT)) & CTIMER_MCR_MR3RL_MASK)
12921 /*! @} */
12922 
12923 /*! @name MR - Match */
12924 /*! @{ */
12925 
12926 #define CTIMER_MR_MATCH_MASK                     (0xFFFFFFFFU)
12927 #define CTIMER_MR_MATCH_SHIFT                    (0U)
12928 /*! MATCH - Timer Counter Match Value */
12929 #define CTIMER_MR_MATCH(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MR_MATCH_SHIFT)) & CTIMER_MR_MATCH_MASK)
12930 /*! @} */
12931 
12932 /* The count of CTIMER_MR */
12933 #define CTIMER_MR_COUNT                          (4U)
12934 
12935 /*! @name CCR - Capture Control */
12936 /*! @{ */
12937 
12938 #define CTIMER_CCR_CAP0RE_MASK                   (0x1U)
12939 #define CTIMER_CCR_CAP0RE_SHIFT                  (0U)
12940 /*! CAP0RE - Rising Edge of Capture Channel 0
12941  *  0b0..Does not load
12942  *  0b1..Loads
12943  */
12944 #define CTIMER_CCR_CAP0RE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0RE_SHIFT)) & CTIMER_CCR_CAP0RE_MASK)
12945 
12946 #define CTIMER_CCR_CAP0FE_MASK                   (0x2U)
12947 #define CTIMER_CCR_CAP0FE_SHIFT                  (1U)
12948 /*! CAP0FE - Falling Edge of Capture Channel 0
12949  *  0b0..Does not load
12950  *  0b1..Loads
12951  */
12952 #define CTIMER_CCR_CAP0FE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0FE_SHIFT)) & CTIMER_CCR_CAP0FE_MASK)
12953 
12954 #define CTIMER_CCR_CAP0I_MASK                    (0x4U)
12955 #define CTIMER_CCR_CAP0I_SHIFT                   (2U)
12956 /*! CAP0I - Generate Interrupt on Channel 0 Capture Event
12957  *  0b0..Does not generate
12958  *  0b1..Generates
12959  */
12960 #define CTIMER_CCR_CAP0I(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK)
12961 
12962 #define CTIMER_CCR_CAP1RE_MASK                   (0x8U)
12963 #define CTIMER_CCR_CAP1RE_SHIFT                  (3U)
12964 /*! CAP1RE - Rising Edge of Capture Channel 1
12965  *  0b0..Does not load
12966  *  0b1..Loads
12967  */
12968 #define CTIMER_CCR_CAP1RE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1RE_SHIFT)) & CTIMER_CCR_CAP1RE_MASK)
12969 
12970 #define CTIMER_CCR_CAP1FE_MASK                   (0x10U)
12971 #define CTIMER_CCR_CAP1FE_SHIFT                  (4U)
12972 /*! CAP1FE - Falling Edge of Capture Channel 1
12973  *  0b0..Does not load
12974  *  0b1..Loads
12975  */
12976 #define CTIMER_CCR_CAP1FE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1FE_SHIFT)) & CTIMER_CCR_CAP1FE_MASK)
12977 
12978 #define CTIMER_CCR_CAP1I_MASK                    (0x20U)
12979 #define CTIMER_CCR_CAP1I_SHIFT                   (5U)
12980 /*! CAP1I - Generate Interrupt on Channel 1 Capture Event
12981  *  0b0..Does not generates
12982  *  0b1..Generates
12983  */
12984 #define CTIMER_CCR_CAP1I(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1I_SHIFT)) & CTIMER_CCR_CAP1I_MASK)
12985 
12986 #define CTIMER_CCR_CAP2RE_MASK                   (0x40U)
12987 #define CTIMER_CCR_CAP2RE_SHIFT                  (6U)
12988 /*! CAP2RE - Rising Edge of Capture Channel 2
12989  *  0b0..Does not load
12990  *  0b1..Loads
12991  */
12992 #define CTIMER_CCR_CAP2RE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2RE_SHIFT)) & CTIMER_CCR_CAP2RE_MASK)
12993 
12994 #define CTIMER_CCR_CAP2FE_MASK                   (0x80U)
12995 #define CTIMER_CCR_CAP2FE_SHIFT                  (7U)
12996 /*! CAP2FE - Falling Edge of Capture Channel 2
12997  *  0b0..Does not load
12998  *  0b1..Loads
12999  */
13000 #define CTIMER_CCR_CAP2FE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2FE_SHIFT)) & CTIMER_CCR_CAP2FE_MASK)
13001 
13002 #define CTIMER_CCR_CAP2I_MASK                    (0x100U)
13003 #define CTIMER_CCR_CAP2I_SHIFT                   (8U)
13004 /*! CAP2I - Generate Interrupt on Channel 2 Capture Event
13005  *  0b0..Does not generate
13006  *  0b1..Generates
13007  */
13008 #define CTIMER_CCR_CAP2I(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2I_SHIFT)) & CTIMER_CCR_CAP2I_MASK)
13009 
13010 #define CTIMER_CCR_CAP3RE_MASK                   (0x200U)
13011 #define CTIMER_CCR_CAP3RE_SHIFT                  (9U)
13012 /*! CAP3RE - Rising Edge of Capture Channel 3
13013  *  0b0..Does not load
13014  *  0b1..Loads
13015  */
13016 #define CTIMER_CCR_CAP3RE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3RE_SHIFT)) & CTIMER_CCR_CAP3RE_MASK)
13017 
13018 #define CTIMER_CCR_CAP3FE_MASK                   (0x400U)
13019 #define CTIMER_CCR_CAP3FE_SHIFT                  (10U)
13020 /*! CAP3FE - Falling Edge of Capture Channel 3
13021  *  0b0..Does not load
13022  *  0b1..Loads
13023  */
13024 #define CTIMER_CCR_CAP3FE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3FE_SHIFT)) & CTIMER_CCR_CAP3FE_MASK)
13025 
13026 #define CTIMER_CCR_CAP3I_MASK                    (0x800U)
13027 #define CTIMER_CCR_CAP3I_SHIFT                   (11U)
13028 /*! CAP3I - Generate Interrupt on Channel 3 Capture Event
13029  *  0b0..Does not generate
13030  *  0b1..Generates
13031  */
13032 #define CTIMER_CCR_CAP3I(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3I_SHIFT)) & CTIMER_CCR_CAP3I_MASK)
13033 /*! @} */
13034 
13035 /*! @name CR - Capture */
13036 /*! @{ */
13037 
13038 #define CTIMER_CR_CAP_MASK                       (0xFFFFFFFFU)
13039 #define CTIMER_CR_CAP_SHIFT                      (0U)
13040 /*! CAP - Timer Counter Capture Value */
13041 #define CTIMER_CR_CAP(x)                         (((uint32_t)(((uint32_t)(x)) << CTIMER_CR_CAP_SHIFT)) & CTIMER_CR_CAP_MASK)
13042 /*! @} */
13043 
13044 /* The count of CTIMER_CR */
13045 #define CTIMER_CR_COUNT                          (4U)
13046 
13047 /*! @name EMR - External Match */
13048 /*! @{ */
13049 
13050 #define CTIMER_EMR_EM0_MASK                      (0x1U)
13051 #define CTIMER_EMR_EM0_SHIFT                     (0U)
13052 /*! EM0 - External Match 0
13053  *  0b0..Low
13054  *  0b1..High
13055  */
13056 #define CTIMER_EMR_EM0(x)                        (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM0_SHIFT)) & CTIMER_EMR_EM0_MASK)
13057 
13058 #define CTIMER_EMR_EM1_MASK                      (0x2U)
13059 #define CTIMER_EMR_EM1_SHIFT                     (1U)
13060 /*! EM1 - External Match 1
13061  *  0b0..Low
13062  *  0b1..High
13063  */
13064 #define CTIMER_EMR_EM1(x)                        (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM1_SHIFT)) & CTIMER_EMR_EM1_MASK)
13065 
13066 #define CTIMER_EMR_EM2_MASK                      (0x4U)
13067 #define CTIMER_EMR_EM2_SHIFT                     (2U)
13068 /*! EM2 - External Match 2
13069  *  0b0..Low
13070  *  0b1..High
13071  */
13072 #define CTIMER_EMR_EM2(x)                        (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM2_SHIFT)) & CTIMER_EMR_EM2_MASK)
13073 
13074 #define CTIMER_EMR_EM3_MASK                      (0x8U)
13075 #define CTIMER_EMR_EM3_SHIFT                     (3U)
13076 /*! EM3 - External Match 3
13077  *  0b0..Low
13078  *  0b1..High
13079  */
13080 #define CTIMER_EMR_EM3(x)                        (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM3_SHIFT)) & CTIMER_EMR_EM3_MASK)
13081 
13082 #define CTIMER_EMR_EMC0_MASK                     (0x30U)
13083 #define CTIMER_EMR_EMC0_SHIFT                    (4U)
13084 /*! EMC0 - External Match Control 0
13085  *  0b00..Does nothing
13086  *  0b01..Goes low
13087  *  0b10..Goes high
13088  *  0b11..Toggles
13089  */
13090 #define CTIMER_EMR_EMC0(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC0_SHIFT)) & CTIMER_EMR_EMC0_MASK)
13091 
13092 #define CTIMER_EMR_EMC1_MASK                     (0xC0U)
13093 #define CTIMER_EMR_EMC1_SHIFT                    (6U)
13094 /*! EMC1 - External Match Control 1
13095  *  0b00..Does nothing
13096  *  0b01..Goes low
13097  *  0b10..Goes high
13098  *  0b11..Toggles
13099  */
13100 #define CTIMER_EMR_EMC1(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC1_SHIFT)) & CTIMER_EMR_EMC1_MASK)
13101 
13102 #define CTIMER_EMR_EMC2_MASK                     (0x300U)
13103 #define CTIMER_EMR_EMC2_SHIFT                    (8U)
13104 /*! EMC2 - External Match Control 2
13105  *  0b00..Does nothing
13106  *  0b01..Goes low
13107  *  0b10..Goes high
13108  *  0b11..Toggles
13109  */
13110 #define CTIMER_EMR_EMC2(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC2_SHIFT)) & CTIMER_EMR_EMC2_MASK)
13111 
13112 #define CTIMER_EMR_EMC3_MASK                     (0xC00U)
13113 #define CTIMER_EMR_EMC3_SHIFT                    (10U)
13114 /*! EMC3 - External Match Control 3
13115  *  0b00..Does nothing
13116  *  0b01..Goes low
13117  *  0b10..Goes high
13118  *  0b11..Toggles
13119  */
13120 #define CTIMER_EMR_EMC3(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC3_SHIFT)) & CTIMER_EMR_EMC3_MASK)
13121 /*! @} */
13122 
13123 /*! @name CTCR - Count Control */
13124 /*! @{ */
13125 
13126 #define CTIMER_CTCR_CTMODE_MASK                  (0x3U)
13127 #define CTIMER_CTCR_CTMODE_SHIFT                 (0U)
13128 /*! CTMODE - Counter Timer Mode
13129  *  0b00..Timer mode
13130  *  0b01..Counter mode rising edge
13131  *  0b10..Counter mode falling edge
13132  *  0b11..Counter mode dual edge
13133  */
13134 #define CTIMER_CTCR_CTMODE(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CTMODE_SHIFT)) & CTIMER_CTCR_CTMODE_MASK)
13135 
13136 #define CTIMER_CTCR_CINSEL_MASK                  (0xCU)
13137 #define CTIMER_CTCR_CINSEL_SHIFT                 (2U)
13138 /*! CINSEL - Count Input Select
13139  *  0b00..Channel 0, CAPn[0] for CTIMERn
13140  *  0b01..Channel 1, CAPn[1] for CTIMERn
13141  *  0b10..Channel 2, CAPn[2] for CTIMERn
13142  *  0b11..Channel 3, CAPn[3] for CTIMERn
13143  */
13144 #define CTIMER_CTCR_CINSEL(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CINSEL_SHIFT)) & CTIMER_CTCR_CINSEL_MASK)
13145 
13146 #define CTIMER_CTCR_ENCC_MASK                    (0x10U)
13147 #define CTIMER_CTCR_ENCC_SHIFT                   (4U)
13148 /*! ENCC - Capture Channel Enable */
13149 #define CTIMER_CTCR_ENCC(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_ENCC_SHIFT)) & CTIMER_CTCR_ENCC_MASK)
13150 
13151 #define CTIMER_CTCR_SELCC_MASK                   (0xE0U)
13152 #define CTIMER_CTCR_SELCC_SHIFT                  (5U)
13153 /*! SELCC - Edge Select
13154  *  0b000..Capture channel 0 rising edge
13155  *  0b001..Capture channel 0 falling edge
13156  *  0b010..Capture channel 1 rising edge
13157  *  0b011..Capture channel 1 falling edge
13158  *  0b100..Capture channel 2 rising edge
13159  *  0b101..Capture channel 2 falling edge
13160  */
13161 #define CTIMER_CTCR_SELCC(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_SELCC_SHIFT)) & CTIMER_CTCR_SELCC_MASK)
13162 /*! @} */
13163 
13164 /*! @name PWMC - PWM Control */
13165 /*! @{ */
13166 
13167 #define CTIMER_PWMC_PWMEN0_MASK                  (0x1U)
13168 #define CTIMER_PWMC_PWMEN0_SHIFT                 (0U)
13169 /*! PWMEN0 - PWM Mode Enable for Channel 0
13170  *  0b0..Disable
13171  *  0b1..Enable
13172  */
13173 #define CTIMER_PWMC_PWMEN0(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN0_SHIFT)) & CTIMER_PWMC_PWMEN0_MASK)
13174 
13175 #define CTIMER_PWMC_PWMEN1_MASK                  (0x2U)
13176 #define CTIMER_PWMC_PWMEN1_SHIFT                 (1U)
13177 /*! PWMEN1 - PWM Mode Enable for Channel 1
13178  *  0b0..Disable
13179  *  0b1..Enable
13180  */
13181 #define CTIMER_PWMC_PWMEN1(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN1_SHIFT)) & CTIMER_PWMC_PWMEN1_MASK)
13182 
13183 #define CTIMER_PWMC_PWMEN2_MASK                  (0x4U)
13184 #define CTIMER_PWMC_PWMEN2_SHIFT                 (2U)
13185 /*! PWMEN2 - PWM Mode Enable for Channel 2
13186  *  0b0..Disable
13187  *  0b1..Enable
13188  */
13189 #define CTIMER_PWMC_PWMEN2(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN2_SHIFT)) & CTIMER_PWMC_PWMEN2_MASK)
13190 
13191 #define CTIMER_PWMC_PWMEN3_MASK                  (0x8U)
13192 #define CTIMER_PWMC_PWMEN3_SHIFT                 (3U)
13193 /*! PWMEN3 - PWM Mode Enable for Channel 3
13194  *  0b0..Disable
13195  *  0b1..Enable
13196  */
13197 #define CTIMER_PWMC_PWMEN3(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN3_SHIFT)) & CTIMER_PWMC_PWMEN3_MASK)
13198 /*! @} */
13199 
13200 /*! @name MSR - Match Shadow */
13201 /*! @{ */
13202 
13203 #define CTIMER_MSR_MATCH_SHADOW_MASK             (0xFFFFFFFFU)
13204 #define CTIMER_MSR_MATCH_SHADOW_SHIFT            (0U)
13205 /*! MATCH_SHADOW - Timer Counter Match Shadow Value */
13206 #define CTIMER_MSR_MATCH_SHADOW(x)               (((uint32_t)(((uint32_t)(x)) << CTIMER_MSR_MATCH_SHADOW_SHIFT)) & CTIMER_MSR_MATCH_SHADOW_MASK)
13207 /*! @} */
13208 
13209 /* The count of CTIMER_MSR */
13210 #define CTIMER_MSR_COUNT                         (4U)
13211 
13212 
13213 /*!
13214  * @}
13215  */ /* end of group CTIMER_Register_Masks */
13216 
13217 
13218 /* CTIMER - Peripheral instance base addresses */
13219 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
13220   /** Peripheral CTIMER0 base address */
13221   #define CTIMER0_BASE                             (0x5000C000u)
13222   /** Peripheral CTIMER0 base address */
13223   #define CTIMER0_BASE_NS                          (0x4000C000u)
13224   /** Peripheral CTIMER0 base pointer */
13225   #define CTIMER0                                  ((CTIMER_Type *)CTIMER0_BASE)
13226   /** Peripheral CTIMER0 base pointer */
13227   #define CTIMER0_NS                               ((CTIMER_Type *)CTIMER0_BASE_NS)
13228   /** Peripheral CTIMER1 base address */
13229   #define CTIMER1_BASE                             (0x5000D000u)
13230   /** Peripheral CTIMER1 base address */
13231   #define CTIMER1_BASE_NS                          (0x4000D000u)
13232   /** Peripheral CTIMER1 base pointer */
13233   #define CTIMER1                                  ((CTIMER_Type *)CTIMER1_BASE)
13234   /** Peripheral CTIMER1 base pointer */
13235   #define CTIMER1_NS                               ((CTIMER_Type *)CTIMER1_BASE_NS)
13236   /** Peripheral CTIMER2 base address */
13237   #define CTIMER2_BASE                             (0x5000E000u)
13238   /** Peripheral CTIMER2 base address */
13239   #define CTIMER2_BASE_NS                          (0x4000E000u)
13240   /** Peripheral CTIMER2 base pointer */
13241   #define CTIMER2                                  ((CTIMER_Type *)CTIMER2_BASE)
13242   /** Peripheral CTIMER2 base pointer */
13243   #define CTIMER2_NS                               ((CTIMER_Type *)CTIMER2_BASE_NS)
13244   /** Peripheral CTIMER3 base address */
13245   #define CTIMER3_BASE                             (0x5000F000u)
13246   /** Peripheral CTIMER3 base address */
13247   #define CTIMER3_BASE_NS                          (0x4000F000u)
13248   /** Peripheral CTIMER3 base pointer */
13249   #define CTIMER3                                  ((CTIMER_Type *)CTIMER3_BASE)
13250   /** Peripheral CTIMER3 base pointer */
13251   #define CTIMER3_NS                               ((CTIMER_Type *)CTIMER3_BASE_NS)
13252   /** Peripheral CTIMER4 base address */
13253   #define CTIMER4_BASE                             (0x50010000u)
13254   /** Peripheral CTIMER4 base address */
13255   #define CTIMER4_BASE_NS                          (0x40010000u)
13256   /** Peripheral CTIMER4 base pointer */
13257   #define CTIMER4                                  ((CTIMER_Type *)CTIMER4_BASE)
13258   /** Peripheral CTIMER4 base pointer */
13259   #define CTIMER4_NS                               ((CTIMER_Type *)CTIMER4_BASE_NS)
13260   /** Array initializer of CTIMER peripheral base addresses */
13261   #define CTIMER_BASE_ADDRS                        { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE }
13262   /** Array initializer of CTIMER peripheral base pointers */
13263   #define CTIMER_BASE_PTRS                         { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 }
13264   /** Array initializer of CTIMER peripheral base addresses */
13265   #define CTIMER_BASE_ADDRS_NS                     { CTIMER0_BASE_NS, CTIMER1_BASE_NS, CTIMER2_BASE_NS, CTIMER3_BASE_NS, CTIMER4_BASE_NS }
13266   /** Array initializer of CTIMER peripheral base pointers */
13267   #define CTIMER_BASE_PTRS_NS                      { CTIMER0_NS, CTIMER1_NS, CTIMER2_NS, CTIMER3_NS, CTIMER4_NS }
13268 #else
13269   /** Peripheral CTIMER0 base address */
13270   #define CTIMER0_BASE                             (0x4000C000u)
13271   /** Peripheral CTIMER0 base pointer */
13272   #define CTIMER0                                  ((CTIMER_Type *)CTIMER0_BASE)
13273   /** Peripheral CTIMER1 base address */
13274   #define CTIMER1_BASE                             (0x4000D000u)
13275   /** Peripheral CTIMER1 base pointer */
13276   #define CTIMER1                                  ((CTIMER_Type *)CTIMER1_BASE)
13277   /** Peripheral CTIMER2 base address */
13278   #define CTIMER2_BASE                             (0x4000E000u)
13279   /** Peripheral CTIMER2 base pointer */
13280   #define CTIMER2                                  ((CTIMER_Type *)CTIMER2_BASE)
13281   /** Peripheral CTIMER3 base address */
13282   #define CTIMER3_BASE                             (0x4000F000u)
13283   /** Peripheral CTIMER3 base pointer */
13284   #define CTIMER3                                  ((CTIMER_Type *)CTIMER3_BASE)
13285   /** Peripheral CTIMER4 base address */
13286   #define CTIMER4_BASE                             (0x40010000u)
13287   /** Peripheral CTIMER4 base pointer */
13288   #define CTIMER4                                  ((CTIMER_Type *)CTIMER4_BASE)
13289   /** Array initializer of CTIMER peripheral base addresses */
13290   #define CTIMER_BASE_ADDRS                        { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE }
13291   /** Array initializer of CTIMER peripheral base pointers */
13292   #define CTIMER_BASE_PTRS                         { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 }
13293 #endif
13294 /** Interrupt vectors for the CTIMER peripheral type */
13295 #define CTIMER_IRQS                              { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn, CTIMER4_IRQn }
13296 
13297 /*!
13298  * @}
13299  */ /* end of group CTIMER_Peripheral_Access_Layer */
13300 
13301 
13302 /* ----------------------------------------------------------------------------
13303    -- DIGTMP Peripheral Access Layer
13304    ---------------------------------------------------------------------------- */
13305 
13306 /*!
13307  * @addtogroup DIGTMP_Peripheral_Access_Layer DIGTMP Peripheral Access Layer
13308  * @{
13309  */
13310 
13311 /** DIGTMP - Register Layout Typedef */
13312 typedef struct {
13313        uint8_t RESERVED_0[16];
13314   __IO uint32_t CR;                                /**< Control, offset: 0x10 */
13315   __IO uint32_t SR;                                /**< Status, offset: 0x14 */
13316   __IO uint32_t LR;                                /**< Lock, offset: 0x18 */
13317   __IO uint32_t IER;                               /**< Interrupt Enable, offset: 0x1C */
13318   __IO uint32_t TSR;                               /**< Tamper Seconds, offset: 0x20 */
13319   __IO uint32_t TER;                               /**< Tamper Enable, offset: 0x24 */
13320   __IO uint32_t PDR;                               /**< Pin Direction, offset: 0x28 */
13321   __IO uint32_t PPR;                               /**< Pin Polarity, offset: 0x2C */
13322   __IO uint32_t ATR[2];                            /**< Active Tamper, array offset: 0x30, array step: 0x4 */
13323        uint8_t RESERVED_1[8];
13324   __IO uint32_t PGFR[8];                           /**< Pin Glitch Filter, array offset: 0x40, array step: 0x4 */
13325 } DIGTMP_Type;
13326 
13327 /* ----------------------------------------------------------------------------
13328    -- DIGTMP Register Masks
13329    ---------------------------------------------------------------------------- */
13330 
13331 /*!
13332  * @addtogroup DIGTMP_Register_Masks DIGTMP Register Masks
13333  * @{
13334  */
13335 
13336 /*! @name CR - Control */
13337 /*! @{ */
13338 
13339 #define DIGTMP_CR_SWR_MASK                       (0x1U)
13340 #define DIGTMP_CR_SWR_SHIFT                      (0U)
13341 /*! SWR - Software Reset
13342  *  0b0..No effect
13343  *  0b1..Perform a software reset
13344  */
13345 #define DIGTMP_CR_SWR(x)                         (((uint32_t)(((uint32_t)(x)) << DIGTMP_CR_SWR_SHIFT)) & DIGTMP_CR_SWR_MASK)
13346 
13347 #define DIGTMP_CR_DEN_MASK                       (0x2U)
13348 #define DIGTMP_CR_DEN_SHIFT                      (1U)
13349 /*! DEN - Digital Tamper Enable
13350  *  0b0..Disables TDET clock and prescaler
13351  *  0b1..Enables TDET clock and prescaler
13352  */
13353 #define DIGTMP_CR_DEN(x)                         (((uint32_t)(((uint32_t)(x)) << DIGTMP_CR_DEN_SHIFT)) & DIGTMP_CR_DEN_MASK)
13354 
13355 #define DIGTMP_CR_TFSR_MASK                      (0x4U)
13356 #define DIGTMP_CR_TFSR_SHIFT                     (2U)
13357 /*! TFSR - Tamper Force System Reset
13358  *  0b0..Do not force chip reset
13359  *  0b1..Force chip reset
13360  */
13361 #define DIGTMP_CR_TFSR(x)                        (((uint32_t)(((uint32_t)(x)) << DIGTMP_CR_TFSR_SHIFT)) & DIGTMP_CR_TFSR_MASK)
13362 
13363 #define DIGTMP_CR_UM_MASK                        (0x8U)
13364 #define DIGTMP_CR_UM_SHIFT                       (3U)
13365 /*! UM - Update Mode
13366  *  0b0..No effect
13367  *  0b1..Allows the clearing of interrupts
13368  */
13369 #define DIGTMP_CR_UM(x)                          (((uint32_t)(((uint32_t)(x)) << DIGTMP_CR_UM_SHIFT)) & DIGTMP_CR_UM_MASK)
13370 
13371 #define DIGTMP_CR_ATCS0_MASK                     (0x10U)
13372 #define DIGTMP_CR_ATCS0_SHIFT                    (4U)
13373 /*! ATCS0 - Active Tamper Clock Source
13374  *  0b0..1 Hz prescaler clock
13375  *  0b1..64 Hz prescaler clock
13376  */
13377 #define DIGTMP_CR_ATCS0(x)                       (((uint32_t)(((uint32_t)(x)) << DIGTMP_CR_ATCS0_SHIFT)) & DIGTMP_CR_ATCS0_MASK)
13378 
13379 #define DIGTMP_CR_ATCS1_MASK                     (0x20U)
13380 #define DIGTMP_CR_ATCS1_SHIFT                    (5U)
13381 /*! ATCS1 - Active Tamper Clock Source
13382  *  0b0..1 Hz prescaler clock
13383  *  0b1..64 Hz prescaler clock
13384  */
13385 #define DIGTMP_CR_ATCS1(x)                       (((uint32_t)(((uint32_t)(x)) << DIGTMP_CR_ATCS1_SHIFT)) & DIGTMP_CR_ATCS1_MASK)
13386 
13387 #define DIGTMP_CR_DISTAM_MASK                    (0x100U)
13388 #define DIGTMP_CR_DISTAM_SHIFT                   (8U)
13389 /*! DISTAM - Disable Prescaler On Tamper
13390  *  0b0..No effect
13391  *  0b1..Automatically disables the prescaler after tamper detection
13392  */
13393 #define DIGTMP_CR_DISTAM(x)                      (((uint32_t)(((uint32_t)(x)) << DIGTMP_CR_DISTAM_SHIFT)) & DIGTMP_CR_DISTAM_MASK)
13394 
13395 #define DIGTMP_CR_DPR_MASK                       (0xFFFE0000U)
13396 #define DIGTMP_CR_DPR_SHIFT                      (17U)
13397 /*! DPR - Digital Tamper Prescaler */
13398 #define DIGTMP_CR_DPR(x)                         (((uint32_t)(((uint32_t)(x)) << DIGTMP_CR_DPR_SHIFT)) & DIGTMP_CR_DPR_MASK)
13399 /*! @} */
13400 
13401 /*! @name SR - Status */
13402 /*! @{ */
13403 
13404 #define DIGTMP_SR_DTF_MASK                       (0x1U)
13405 #define DIGTMP_SR_DTF_SHIFT                      (0U)
13406 /*! DTF - Digital Tamper Flag
13407  *  0b0..TDET tampering not detected
13408  *  0b1..TDET tampering detected
13409  */
13410 #define DIGTMP_SR_DTF(x)                         (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_DTF_SHIFT)) & DIGTMP_SR_DTF_MASK)
13411 
13412 #define DIGTMP_SR_TAF_MASK                       (0x2U)
13413 #define DIGTMP_SR_TAF_SHIFT                      (1U)
13414 /*! TAF - Tamper Acknowledge Flag
13415  *  0b0..Digital Tamper Flag (SR[DTF]) is clear or chip reset has not occurred after Digital Tamper Flag (SR[DTF]) was set.
13416  *  0b1..Chip reset has occurred after Digital Tamper Flag (SR[DTF]) was set.
13417  */
13418 #define DIGTMP_SR_TAF(x)                         (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TAF_SHIFT)) & DIGTMP_SR_TAF_MASK)
13419 
13420 #define DIGTMP_SR_TIF0_MASK                      (0x4U)
13421 #define DIGTMP_SR_TIF0_SHIFT                     (2U)
13422 /*! TIF0 - Tamper Input n Flag
13423  *  0b0..On-chip tamper not detected
13424  *  0b1..On-chip tamper detected
13425  */
13426 #define DIGTMP_SR_TIF0(x)                        (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TIF0_SHIFT)) & DIGTMP_SR_TIF0_MASK)
13427 
13428 #define DIGTMP_SR_TIF1_MASK                      (0x8U)
13429 #define DIGTMP_SR_TIF1_SHIFT                     (3U)
13430 /*! TIF1 - Tamper Input n Flag
13431  *  0b0..On-chip tamper not detected
13432  *  0b1..On-chip tamper detected
13433  */
13434 #define DIGTMP_SR_TIF1(x)                        (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TIF1_SHIFT)) & DIGTMP_SR_TIF1_MASK)
13435 
13436 #define DIGTMP_SR_TIF2_MASK                      (0x10U)
13437 #define DIGTMP_SR_TIF2_SHIFT                     (4U)
13438 /*! TIF2 - Tamper Input n Flag
13439  *  0b0..On-chip tamper not detected
13440  *  0b1..On-chip tamper detected
13441  */
13442 #define DIGTMP_SR_TIF2(x)                        (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TIF2_SHIFT)) & DIGTMP_SR_TIF2_MASK)
13443 
13444 #define DIGTMP_SR_TIF3_MASK                      (0x20U)
13445 #define DIGTMP_SR_TIF3_SHIFT                     (5U)
13446 /*! TIF3 - Tamper Input n Flag
13447  *  0b0..On-chip tamper not detected
13448  *  0b1..On-chip tamper detected
13449  */
13450 #define DIGTMP_SR_TIF3(x)                        (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TIF3_SHIFT)) & DIGTMP_SR_TIF3_MASK)
13451 
13452 #define DIGTMP_SR_TIF4_MASK                      (0x40U)
13453 #define DIGTMP_SR_TIF4_SHIFT                     (6U)
13454 /*! TIF4 - Tamper Input n Flag
13455  *  0b0..On-chip tamper not detected
13456  *  0b1..On-chip tamper detected
13457  */
13458 #define DIGTMP_SR_TIF4(x)                        (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TIF4_SHIFT)) & DIGTMP_SR_TIF4_MASK)
13459 
13460 #define DIGTMP_SR_TIF5_MASK                      (0x80U)
13461 #define DIGTMP_SR_TIF5_SHIFT                     (7U)
13462 /*! TIF5 - Tamper Input n Flag
13463  *  0b0..On-chip tamper not detected
13464  *  0b1..On-chip tamper detected
13465  */
13466 #define DIGTMP_SR_TIF5(x)                        (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TIF5_SHIFT)) & DIGTMP_SR_TIF5_MASK)
13467 
13468 #define DIGTMP_SR_TIF6_MASK                      (0x100U)
13469 #define DIGTMP_SR_TIF6_SHIFT                     (8U)
13470 /*! TIF6 - Tamper Input n Flag
13471  *  0b0..On-chip tamper not detected
13472  *  0b1..On-chip tamper detected
13473  */
13474 #define DIGTMP_SR_TIF6(x)                        (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TIF6_SHIFT)) & DIGTMP_SR_TIF6_MASK)
13475 
13476 #define DIGTMP_SR_TIF7_MASK                      (0x200U)
13477 #define DIGTMP_SR_TIF7_SHIFT                     (9U)
13478 /*! TIF7 - Tamper Input n Flag
13479  *  0b0..On-chip tamper not detected
13480  *  0b1..On-chip tamper detected
13481  */
13482 #define DIGTMP_SR_TIF7(x)                        (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TIF7_SHIFT)) & DIGTMP_SR_TIF7_MASK)
13483 
13484 #define DIGTMP_SR_TIF8_MASK                      (0x400U)
13485 #define DIGTMP_SR_TIF8_SHIFT                     (10U)
13486 /*! TIF8 - Tamper Input n Flag
13487  *  0b0..On-chip tamper not detected
13488  *  0b1..On-chip tamper detected
13489  */
13490 #define DIGTMP_SR_TIF8(x)                        (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TIF8_SHIFT)) & DIGTMP_SR_TIF8_MASK)
13491 
13492 #define DIGTMP_SR_TIF9_MASK                      (0x800U)
13493 #define DIGTMP_SR_TIF9_SHIFT                     (11U)
13494 /*! TIF9 - Tamper Input n Flag
13495  *  0b0..On-chip tamper not detected
13496  *  0b1..On-chip tamper detected
13497  */
13498 #define DIGTMP_SR_TIF9(x)                        (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TIF9_SHIFT)) & DIGTMP_SR_TIF9_MASK)
13499 
13500 #define DIGTMP_SR_TPF0_MASK                      (0x10000U)
13501 #define DIGTMP_SR_TPF0_SHIFT                     (16U)
13502 /*! TPF0 - Tamper Pin n Flag
13503  *  0b0..Pin tamper not detected
13504  *  0b1..Pin tamper detected
13505  */
13506 #define DIGTMP_SR_TPF0(x)                        (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TPF0_SHIFT)) & DIGTMP_SR_TPF0_MASK)
13507 
13508 #define DIGTMP_SR_TPF1_MASK                      (0x20000U)
13509 #define DIGTMP_SR_TPF1_SHIFT                     (17U)
13510 /*! TPF1 - Tamper Pin n Flag
13511  *  0b0..Pin tamper not detected
13512  *  0b1..Pin tamper detected
13513  */
13514 #define DIGTMP_SR_TPF1(x)                        (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TPF1_SHIFT)) & DIGTMP_SR_TPF1_MASK)
13515 
13516 #define DIGTMP_SR_TPF2_MASK                      (0x40000U)
13517 #define DIGTMP_SR_TPF2_SHIFT                     (18U)
13518 /*! TPF2 - Tamper Pin n Flag
13519  *  0b0..Pin tamper not detected
13520  *  0b1..Pin tamper detected
13521  */
13522 #define DIGTMP_SR_TPF2(x)                        (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TPF2_SHIFT)) & DIGTMP_SR_TPF2_MASK)
13523 
13524 #define DIGTMP_SR_TPF3_MASK                      (0x80000U)
13525 #define DIGTMP_SR_TPF3_SHIFT                     (19U)
13526 /*! TPF3 - Tamper Pin n Flag
13527  *  0b0..Pin tamper not detected
13528  *  0b1..Pin tamper detected
13529  */
13530 #define DIGTMP_SR_TPF3(x)                        (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TPF3_SHIFT)) & DIGTMP_SR_TPF3_MASK)
13531 
13532 #define DIGTMP_SR_TPF4_MASK                      (0x100000U)
13533 #define DIGTMP_SR_TPF4_SHIFT                     (20U)
13534 /*! TPF4 - Tamper Pin n Flag
13535  *  0b0..Pin tamper not detected
13536  *  0b1..Pin tamper detected
13537  */
13538 #define DIGTMP_SR_TPF4(x)                        (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TPF4_SHIFT)) & DIGTMP_SR_TPF4_MASK)
13539 
13540 #define DIGTMP_SR_TPF5_MASK                      (0x200000U)
13541 #define DIGTMP_SR_TPF5_SHIFT                     (21U)
13542 /*! TPF5 - Tamper Pin n Flag
13543  *  0b0..Pin tamper not detected
13544  *  0b1..Pin tamper detected
13545  */
13546 #define DIGTMP_SR_TPF5(x)                        (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TPF5_SHIFT)) & DIGTMP_SR_TPF5_MASK)
13547 
13548 #define DIGTMP_SR_TPF6_MASK                      (0x400000U)
13549 #define DIGTMP_SR_TPF6_SHIFT                     (22U)
13550 /*! TPF6 - Tamper Pin n Flag
13551  *  0b0..Pin tamper not detected
13552  *  0b1..Pin tamper detected
13553  */
13554 #define DIGTMP_SR_TPF6(x)                        (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TPF6_SHIFT)) & DIGTMP_SR_TPF6_MASK)
13555 
13556 #define DIGTMP_SR_TPF7_MASK                      (0x800000U)
13557 #define DIGTMP_SR_TPF7_SHIFT                     (23U)
13558 /*! TPF7 - Tamper Pin n Flag
13559  *  0b0..Pin tamper not detected
13560  *  0b1..Pin tamper detected
13561  */
13562 #define DIGTMP_SR_TPF7(x)                        (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TPF7_SHIFT)) & DIGTMP_SR_TPF7_MASK)
13563 /*! @} */
13564 
13565 /*! @name LR - Lock */
13566 /*! @{ */
13567 
13568 #define DIGTMP_LR_CRL_MASK                       (0x10U)
13569 #define DIGTMP_LR_CRL_SHIFT                      (4U)
13570 /*! CRL - Control Register Lock
13571  *  0b0..Locked and writes are ignored
13572  *  0b1..Not locked and writes complete as normal
13573  */
13574 #define DIGTMP_LR_CRL(x)                         (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_CRL_SHIFT)) & DIGTMP_LR_CRL_MASK)
13575 
13576 #define DIGTMP_LR_SRL_MASK                       (0x20U)
13577 #define DIGTMP_LR_SRL_SHIFT                      (5U)
13578 /*! SRL - Status Register Lock
13579  *  0b0..Locked and writes are ignored
13580  *  0b1..Not locked and writes complete as normal
13581  */
13582 #define DIGTMP_LR_SRL(x)                         (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_SRL_SHIFT)) & DIGTMP_LR_SRL_MASK)
13583 
13584 #define DIGTMP_LR_LRL_MASK                       (0x40U)
13585 #define DIGTMP_LR_LRL_SHIFT                      (6U)
13586 /*! LRL - Lock Register Lock
13587  *  0b0..Locked and writes are ignored
13588  *  0b1..Not locked and writes complete as normal
13589  */
13590 #define DIGTMP_LR_LRL(x)                         (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_LRL_SHIFT)) & DIGTMP_LR_LRL_MASK)
13591 
13592 #define DIGTMP_LR_IEL_MASK                       (0x80U)
13593 #define DIGTMP_LR_IEL_SHIFT                      (7U)
13594 /*! IEL - Interrupt Enable Lock
13595  *  0b0..Locked and writes are ignored
13596  *  0b1..Not locked and writes complete as normal
13597  */
13598 #define DIGTMP_LR_IEL(x)                         (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_IEL_SHIFT)) & DIGTMP_LR_IEL_MASK)
13599 
13600 #define DIGTMP_LR_TSL_MASK                       (0x100U)
13601 #define DIGTMP_LR_TSL_SHIFT                      (8U)
13602 /*! TSL - Tamper Seconds Lock
13603  *  0b0..Locked and writes are ignored
13604  *  0b1..Not locked and writes complete as normal
13605  */
13606 #define DIGTMP_LR_TSL(x)                         (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_TSL_SHIFT)) & DIGTMP_LR_TSL_MASK)
13607 
13608 #define DIGTMP_LR_TEL_MASK                       (0x200U)
13609 #define DIGTMP_LR_TEL_SHIFT                      (9U)
13610 /*! TEL - Tamper Enable Lock
13611  *  0b0..Locked and writes are ignored
13612  *  0b1..Not locked and writes complete as normal
13613  */
13614 #define DIGTMP_LR_TEL(x)                         (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_TEL_SHIFT)) & DIGTMP_LR_TEL_MASK)
13615 
13616 #define DIGTMP_LR_PDL_MASK                       (0x400U)
13617 #define DIGTMP_LR_PDL_SHIFT                      (10U)
13618 /*! PDL - Pin Direction Lock
13619  *  0b0..Locked and writes are ignored
13620  *  0b1..Not locked and writes complete as normal
13621  */
13622 #define DIGTMP_LR_PDL(x)                         (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_PDL_SHIFT)) & DIGTMP_LR_PDL_MASK)
13623 
13624 #define DIGTMP_LR_PPL_MASK                       (0x800U)
13625 #define DIGTMP_LR_PPL_SHIFT                      (11U)
13626 /*! PPL - Pin Polarity Lock
13627  *  0b0..Locked and writes are ignored
13628  *  0b1..Not locked and writes complete as normal
13629  */
13630 #define DIGTMP_LR_PPL(x)                         (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_PPL_SHIFT)) & DIGTMP_LR_PPL_MASK)
13631 
13632 #define DIGTMP_LR_ATL0_MASK                      (0x1000U)
13633 #define DIGTMP_LR_ATL0_SHIFT                     (12U)
13634 /*! ATL0 - Active Tamper Lock
13635  *  0b0..Locked and writes are ignored
13636  *  0b1..Not locked and writes complete as normal
13637  */
13638 #define DIGTMP_LR_ATL0(x)                        (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_ATL0_SHIFT)) & DIGTMP_LR_ATL0_MASK)
13639 
13640 #define DIGTMP_LR_ATL1_MASK                      (0x2000U)
13641 #define DIGTMP_LR_ATL1_SHIFT                     (13U)
13642 /*! ATL1 - Active Tamper Lock
13643  *  0b0..Locked and writes are ignored
13644  *  0b1..Not locked and writes complete as normal
13645  */
13646 #define DIGTMP_LR_ATL1(x)                        (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_ATL1_SHIFT)) & DIGTMP_LR_ATL1_MASK)
13647 
13648 #define DIGTMP_LR_GFL0_MASK                      (0x10000U)
13649 #define DIGTMP_LR_GFL0_SHIFT                     (16U)
13650 /*! GFL0 - Glitch Filter Lock
13651  *  0b0..Locked and writes are ignored
13652  *  0b1..Not locked and writes complete as normal
13653  */
13654 #define DIGTMP_LR_GFL0(x)                        (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_GFL0_SHIFT)) & DIGTMP_LR_GFL0_MASK)
13655 
13656 #define DIGTMP_LR_GFL1_MASK                      (0x20000U)
13657 #define DIGTMP_LR_GFL1_SHIFT                     (17U)
13658 /*! GFL1 - Glitch Filter Lock
13659  *  0b0..Locked and writes are ignored
13660  *  0b1..Not locked and writes complete as normal
13661  */
13662 #define DIGTMP_LR_GFL1(x)                        (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_GFL1_SHIFT)) & DIGTMP_LR_GFL1_MASK)
13663 
13664 #define DIGTMP_LR_GFL2_MASK                      (0x40000U)
13665 #define DIGTMP_LR_GFL2_SHIFT                     (18U)
13666 /*! GFL2 - Glitch Filter Lock
13667  *  0b0..Locked and writes are ignored
13668  *  0b1..Not locked and writes complete as normal
13669  */
13670 #define DIGTMP_LR_GFL2(x)                        (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_GFL2_SHIFT)) & DIGTMP_LR_GFL2_MASK)
13671 
13672 #define DIGTMP_LR_GFL3_MASK                      (0x80000U)
13673 #define DIGTMP_LR_GFL3_SHIFT                     (19U)
13674 /*! GFL3 - Glitch Filter Lock
13675  *  0b0..Locked and writes are ignored
13676  *  0b1..Not locked and writes complete as normal
13677  */
13678 #define DIGTMP_LR_GFL3(x)                        (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_GFL3_SHIFT)) & DIGTMP_LR_GFL3_MASK)
13679 
13680 #define DIGTMP_LR_GFL4_MASK                      (0x100000U)
13681 #define DIGTMP_LR_GFL4_SHIFT                     (20U)
13682 /*! GFL4 - Glitch Filter Lock
13683  *  0b0..Locked and writes are ignored
13684  *  0b1..Not locked and writes complete as normal
13685  */
13686 #define DIGTMP_LR_GFL4(x)                        (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_GFL4_SHIFT)) & DIGTMP_LR_GFL4_MASK)
13687 
13688 #define DIGTMP_LR_GFL5_MASK                      (0x200000U)
13689 #define DIGTMP_LR_GFL5_SHIFT                     (21U)
13690 /*! GFL5 - Glitch Filter Lock
13691  *  0b0..Locked and writes are ignored
13692  *  0b1..Not locked and writes complete as normal
13693  */
13694 #define DIGTMP_LR_GFL5(x)                        (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_GFL5_SHIFT)) & DIGTMP_LR_GFL5_MASK)
13695 
13696 #define DIGTMP_LR_GFL6_MASK                      (0x400000U)
13697 #define DIGTMP_LR_GFL6_SHIFT                     (22U)
13698 /*! GFL6 - Glitch Filter Lock
13699  *  0b0..Locked and writes are ignored
13700  *  0b1..Not locked and writes complete as normal
13701  */
13702 #define DIGTMP_LR_GFL6(x)                        (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_GFL6_SHIFT)) & DIGTMP_LR_GFL6_MASK)
13703 
13704 #define DIGTMP_LR_GFL7_MASK                      (0x800000U)
13705 #define DIGTMP_LR_GFL7_SHIFT                     (23U)
13706 /*! GFL7 - Glitch Filter Lock
13707  *  0b0..Locked and writes are ignored
13708  *  0b1..Not locked and writes complete as normal
13709  */
13710 #define DIGTMP_LR_GFL7(x)                        (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_GFL7_SHIFT)) & DIGTMP_LR_GFL7_MASK)
13711 /*! @} */
13712 
13713 /*! @name IER - Interrupt Enable */
13714 /*! @{ */
13715 
13716 #define DIGTMP_IER_DTIE_MASK                     (0x1U)
13717 #define DIGTMP_IER_DTIE_SHIFT                    (0U)
13718 /*! DTIE - Digital Tamper Interrupt Enable
13719  *  0b0..Disables
13720  *  0b1..Enables
13721  */
13722 #define DIGTMP_IER_DTIE(x)                       (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_DTIE_SHIFT)) & DIGTMP_IER_DTIE_MASK)
13723 
13724 #define DIGTMP_IER_TIIE0_MASK                    (0x4U)
13725 #define DIGTMP_IER_TIIE0_SHIFT                   (2U)
13726 /*! TIIE0 - Tamper Input n Interrupt Enable
13727  *  0b0..Disables
13728  *  0b1..Enables
13729  */
13730 #define DIGTMP_IER_TIIE0(x)                      (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TIIE0_SHIFT)) & DIGTMP_IER_TIIE0_MASK)
13731 
13732 #define DIGTMP_IER_TIIE1_MASK                    (0x8U)
13733 #define DIGTMP_IER_TIIE1_SHIFT                   (3U)
13734 /*! TIIE1 - Tamper Input n Interrupt Enable
13735  *  0b0..Disables
13736  *  0b1..Enables
13737  */
13738 #define DIGTMP_IER_TIIE1(x)                      (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TIIE1_SHIFT)) & DIGTMP_IER_TIIE1_MASK)
13739 
13740 #define DIGTMP_IER_TIIE2_MASK                    (0x10U)
13741 #define DIGTMP_IER_TIIE2_SHIFT                   (4U)
13742 /*! TIIE2 - Tamper Input n Interrupt Enable
13743  *  0b0..Disables
13744  *  0b1..Enables
13745  */
13746 #define DIGTMP_IER_TIIE2(x)                      (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TIIE2_SHIFT)) & DIGTMP_IER_TIIE2_MASK)
13747 
13748 #define DIGTMP_IER_TIIE3_MASK                    (0x20U)
13749 #define DIGTMP_IER_TIIE3_SHIFT                   (5U)
13750 /*! TIIE3 - Tamper Input n Interrupt Enable
13751  *  0b0..Disables
13752  *  0b1..Enables
13753  */
13754 #define DIGTMP_IER_TIIE3(x)                      (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TIIE3_SHIFT)) & DIGTMP_IER_TIIE3_MASK)
13755 
13756 #define DIGTMP_IER_TIIE4_MASK                    (0x40U)
13757 #define DIGTMP_IER_TIIE4_SHIFT                   (6U)
13758 /*! TIIE4 - Tamper Input n Interrupt Enable
13759  *  0b0..Disables
13760  *  0b1..Enables
13761  */
13762 #define DIGTMP_IER_TIIE4(x)                      (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TIIE4_SHIFT)) & DIGTMP_IER_TIIE4_MASK)
13763 
13764 #define DIGTMP_IER_TIIE5_MASK                    (0x80U)
13765 #define DIGTMP_IER_TIIE5_SHIFT                   (7U)
13766 /*! TIIE5 - Tamper Input n Interrupt Enable
13767  *  0b0..Disables
13768  *  0b1..Enables
13769  */
13770 #define DIGTMP_IER_TIIE5(x)                      (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TIIE5_SHIFT)) & DIGTMP_IER_TIIE5_MASK)
13771 
13772 #define DIGTMP_IER_TIIE6_MASK                    (0x100U)
13773 #define DIGTMP_IER_TIIE6_SHIFT                   (8U)
13774 /*! TIIE6 - Tamper Input n Interrupt Enable
13775  *  0b0..Disables
13776  *  0b1..Enables
13777  */
13778 #define DIGTMP_IER_TIIE6(x)                      (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TIIE6_SHIFT)) & DIGTMP_IER_TIIE6_MASK)
13779 
13780 #define DIGTMP_IER_TIIE7_MASK                    (0x200U)
13781 #define DIGTMP_IER_TIIE7_SHIFT                   (9U)
13782 /*! TIIE7 - Tamper Input n Interrupt Enable
13783  *  0b0..Disables
13784  *  0b1..Enables
13785  */
13786 #define DIGTMP_IER_TIIE7(x)                      (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TIIE7_SHIFT)) & DIGTMP_IER_TIIE7_MASK)
13787 
13788 #define DIGTMP_IER_TIIE8_MASK                    (0x400U)
13789 #define DIGTMP_IER_TIIE8_SHIFT                   (10U)
13790 /*! TIIE8 - Tamper Input n Interrupt Enable
13791  *  0b0..Disables
13792  *  0b1..Enables
13793  */
13794 #define DIGTMP_IER_TIIE8(x)                      (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TIIE8_SHIFT)) & DIGTMP_IER_TIIE8_MASK)
13795 
13796 #define DIGTMP_IER_TIIE9_MASK                    (0x800U)
13797 #define DIGTMP_IER_TIIE9_SHIFT                   (11U)
13798 /*! TIIE9 - Tamper Input n Interrupt Enable
13799  *  0b0..Disables
13800  *  0b1..Enables
13801  */
13802 #define DIGTMP_IER_TIIE9(x)                      (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TIIE9_SHIFT)) & DIGTMP_IER_TIIE9_MASK)
13803 
13804 #define DIGTMP_IER_TPIE0_MASK                    (0x10000U)
13805 #define DIGTMP_IER_TPIE0_SHIFT                   (16U)
13806 /*! TPIE0 - Tamper Pin n Interrupt Enable
13807  *  0b0..Disables
13808  *  0b1..Enables
13809  */
13810 #define DIGTMP_IER_TPIE0(x)                      (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TPIE0_SHIFT)) & DIGTMP_IER_TPIE0_MASK)
13811 
13812 #define DIGTMP_IER_TPIE1_MASK                    (0x20000U)
13813 #define DIGTMP_IER_TPIE1_SHIFT                   (17U)
13814 /*! TPIE1 - Tamper Pin n Interrupt Enable
13815  *  0b0..Disables
13816  *  0b1..Enables
13817  */
13818 #define DIGTMP_IER_TPIE1(x)                      (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TPIE1_SHIFT)) & DIGTMP_IER_TPIE1_MASK)
13819 
13820 #define DIGTMP_IER_TPIE2_MASK                    (0x40000U)
13821 #define DIGTMP_IER_TPIE2_SHIFT                   (18U)
13822 /*! TPIE2 - Tamper Pin n Interrupt Enable
13823  *  0b0..Disables
13824  *  0b1..Enables
13825  */
13826 #define DIGTMP_IER_TPIE2(x)                      (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TPIE2_SHIFT)) & DIGTMP_IER_TPIE2_MASK)
13827 
13828 #define DIGTMP_IER_TPIE3_MASK                    (0x80000U)
13829 #define DIGTMP_IER_TPIE3_SHIFT                   (19U)
13830 /*! TPIE3 - Tamper Pin n Interrupt Enable
13831  *  0b0..Disables
13832  *  0b1..Enables
13833  */
13834 #define DIGTMP_IER_TPIE3(x)                      (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TPIE3_SHIFT)) & DIGTMP_IER_TPIE3_MASK)
13835 
13836 #define DIGTMP_IER_TPIE4_MASK                    (0x100000U)
13837 #define DIGTMP_IER_TPIE4_SHIFT                   (20U)
13838 /*! TPIE4 - Tamper Pin n Interrupt Enable
13839  *  0b0..Disables
13840  *  0b1..Enables
13841  */
13842 #define DIGTMP_IER_TPIE4(x)                      (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TPIE4_SHIFT)) & DIGTMP_IER_TPIE4_MASK)
13843 
13844 #define DIGTMP_IER_TPIE5_MASK                    (0x200000U)
13845 #define DIGTMP_IER_TPIE5_SHIFT                   (21U)
13846 /*! TPIE5 - Tamper Pin n Interrupt Enable
13847  *  0b0..Disables
13848  *  0b1..Enables
13849  */
13850 #define DIGTMP_IER_TPIE5(x)                      (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TPIE5_SHIFT)) & DIGTMP_IER_TPIE5_MASK)
13851 
13852 #define DIGTMP_IER_TPIE6_MASK                    (0x400000U)
13853 #define DIGTMP_IER_TPIE6_SHIFT                   (22U)
13854 /*! TPIE6 - Tamper Pin n Interrupt Enable
13855  *  0b0..Disables
13856  *  0b1..Enables
13857  */
13858 #define DIGTMP_IER_TPIE6(x)                      (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TPIE6_SHIFT)) & DIGTMP_IER_TPIE6_MASK)
13859 
13860 #define DIGTMP_IER_TPIE7_MASK                    (0x800000U)
13861 #define DIGTMP_IER_TPIE7_SHIFT                   (23U)
13862 /*! TPIE7 - Tamper Pin n Interrupt Enable
13863  *  0b0..Disables
13864  *  0b1..Enables
13865  */
13866 #define DIGTMP_IER_TPIE7(x)                      (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TPIE7_SHIFT)) & DIGTMP_IER_TPIE7_MASK)
13867 /*! @} */
13868 
13869 /*! @name TSR - Tamper Seconds */
13870 /*! @{ */
13871 
13872 #define DIGTMP_TSR_TTS_MASK                      (0xFFFFFFFFU)
13873 #define DIGTMP_TSR_TTS_SHIFT                     (0U)
13874 /*! TTS - Tamper Time Seconds */
13875 #define DIGTMP_TSR_TTS(x)                        (((uint32_t)(((uint32_t)(x)) << DIGTMP_TSR_TTS_SHIFT)) & DIGTMP_TSR_TTS_MASK)
13876 /*! @} */
13877 
13878 /*! @name TER - Tamper Enable */
13879 /*! @{ */
13880 
13881 #define DIGTMP_TER_TIE0_MASK                     (0x4U)
13882 #define DIGTMP_TER_TIE0_SHIFT                    (2U)
13883 /*! TIE0 - Tamper Input Enable
13884  *  0b0..Disables
13885  *  0b1..Enables
13886  */
13887 #define DIGTMP_TER_TIE0(x)                       (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TIE0_SHIFT)) & DIGTMP_TER_TIE0_MASK)
13888 
13889 #define DIGTMP_TER_TIE1_MASK                     (0x8U)
13890 #define DIGTMP_TER_TIE1_SHIFT                    (3U)
13891 /*! TIE1 - Tamper Input Enable
13892  *  0b0..Disables
13893  *  0b1..Enables
13894  */
13895 #define DIGTMP_TER_TIE1(x)                       (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TIE1_SHIFT)) & DIGTMP_TER_TIE1_MASK)
13896 
13897 #define DIGTMP_TER_TIE2_MASK                     (0x10U)
13898 #define DIGTMP_TER_TIE2_SHIFT                    (4U)
13899 /*! TIE2 - Tamper Input Enable
13900  *  0b0..Disables
13901  *  0b1..Enables
13902  */
13903 #define DIGTMP_TER_TIE2(x)                       (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TIE2_SHIFT)) & DIGTMP_TER_TIE2_MASK)
13904 
13905 #define DIGTMP_TER_TIE3_MASK                     (0x20U)
13906 #define DIGTMP_TER_TIE3_SHIFT                    (5U)
13907 /*! TIE3 - Tamper Input Enable
13908  *  0b0..Disables
13909  *  0b1..Enables
13910  */
13911 #define DIGTMP_TER_TIE3(x)                       (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TIE3_SHIFT)) & DIGTMP_TER_TIE3_MASK)
13912 
13913 #define DIGTMP_TER_TIE4_MASK                     (0x40U)
13914 #define DIGTMP_TER_TIE4_SHIFT                    (6U)
13915 /*! TIE4 - Tamper Input Enable
13916  *  0b0..Disables
13917  *  0b1..Enables
13918  */
13919 #define DIGTMP_TER_TIE4(x)                       (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TIE4_SHIFT)) & DIGTMP_TER_TIE4_MASK)
13920 
13921 #define DIGTMP_TER_TIE5_MASK                     (0x80U)
13922 #define DIGTMP_TER_TIE5_SHIFT                    (7U)
13923 /*! TIE5 - Tamper Input Enable
13924  *  0b0..Disables
13925  *  0b1..Enables
13926  */
13927 #define DIGTMP_TER_TIE5(x)                       (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TIE5_SHIFT)) & DIGTMP_TER_TIE5_MASK)
13928 
13929 #define DIGTMP_TER_TIE6_MASK                     (0x100U)
13930 #define DIGTMP_TER_TIE6_SHIFT                    (8U)
13931 /*! TIE6 - Tamper Input Enable
13932  *  0b0..Disables
13933  *  0b1..Enables
13934  */
13935 #define DIGTMP_TER_TIE6(x)                       (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TIE6_SHIFT)) & DIGTMP_TER_TIE6_MASK)
13936 
13937 #define DIGTMP_TER_TIE7_MASK                     (0x200U)
13938 #define DIGTMP_TER_TIE7_SHIFT                    (9U)
13939 /*! TIE7 - Tamper Input Enable
13940  *  0b0..Disables
13941  *  0b1..Enables
13942  */
13943 #define DIGTMP_TER_TIE7(x)                       (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TIE7_SHIFT)) & DIGTMP_TER_TIE7_MASK)
13944 
13945 #define DIGTMP_TER_TIE8_MASK                     (0x400U)
13946 #define DIGTMP_TER_TIE8_SHIFT                    (10U)
13947 /*! TIE8 - Tamper Input Enable
13948  *  0b0..Disables
13949  *  0b1..Enables
13950  */
13951 #define DIGTMP_TER_TIE8(x)                       (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TIE8_SHIFT)) & DIGTMP_TER_TIE8_MASK)
13952 
13953 #define DIGTMP_TER_TIE9_MASK                     (0x800U)
13954 #define DIGTMP_TER_TIE9_SHIFT                    (11U)
13955 /*! TIE9 - Tamper Input Enable
13956  *  0b0..Disables
13957  *  0b1..Enables
13958  */
13959 #define DIGTMP_TER_TIE9(x)                       (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TIE9_SHIFT)) & DIGTMP_TER_TIE9_MASK)
13960 
13961 #define DIGTMP_TER_TPE0_MASK                     (0x10000U)
13962 #define DIGTMP_TER_TPE0_SHIFT                    (16U)
13963 /*! TPE0 - Tamper Pin Enable
13964  *  0b0..Disables
13965  *  0b1..Enables
13966  */
13967 #define DIGTMP_TER_TPE0(x)                       (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TPE0_SHIFT)) & DIGTMP_TER_TPE0_MASK)
13968 
13969 #define DIGTMP_TER_TPE1_MASK                     (0x20000U)
13970 #define DIGTMP_TER_TPE1_SHIFT                    (17U)
13971 /*! TPE1 - Tamper Pin Enable
13972  *  0b0..Disables
13973  *  0b1..Enables
13974  */
13975 #define DIGTMP_TER_TPE1(x)                       (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TPE1_SHIFT)) & DIGTMP_TER_TPE1_MASK)
13976 
13977 #define DIGTMP_TER_TPE2_MASK                     (0x40000U)
13978 #define DIGTMP_TER_TPE2_SHIFT                    (18U)
13979 /*! TPE2 - Tamper Pin Enable
13980  *  0b0..Disables
13981  *  0b1..Enables
13982  */
13983 #define DIGTMP_TER_TPE2(x)                       (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TPE2_SHIFT)) & DIGTMP_TER_TPE2_MASK)
13984 
13985 #define DIGTMP_TER_TPE3_MASK                     (0x80000U)
13986 #define DIGTMP_TER_TPE3_SHIFT                    (19U)
13987 /*! TPE3 - Tamper Pin Enable
13988  *  0b0..Disables
13989  *  0b1..Enables
13990  */
13991 #define DIGTMP_TER_TPE3(x)                       (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TPE3_SHIFT)) & DIGTMP_TER_TPE3_MASK)
13992 
13993 #define DIGTMP_TER_TPE4_MASK                     (0x100000U)
13994 #define DIGTMP_TER_TPE4_SHIFT                    (20U)
13995 /*! TPE4 - Tamper Pin Enable
13996  *  0b0..Disables
13997  *  0b1..Enables
13998  */
13999 #define DIGTMP_TER_TPE4(x)                       (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TPE4_SHIFT)) & DIGTMP_TER_TPE4_MASK)
14000 
14001 #define DIGTMP_TER_TPE5_MASK                     (0x200000U)
14002 #define DIGTMP_TER_TPE5_SHIFT                    (21U)
14003 /*! TPE5 - Tamper Pin Enable
14004  *  0b0..Disables
14005  *  0b1..Enables
14006  */
14007 #define DIGTMP_TER_TPE5(x)                       (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TPE5_SHIFT)) & DIGTMP_TER_TPE5_MASK)
14008 
14009 #define DIGTMP_TER_TPE6_MASK                     (0x400000U)
14010 #define DIGTMP_TER_TPE6_SHIFT                    (22U)
14011 /*! TPE6 - Tamper Pin Enable
14012  *  0b0..Disables
14013  *  0b1..Enables
14014  */
14015 #define DIGTMP_TER_TPE6(x)                       (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TPE6_SHIFT)) & DIGTMP_TER_TPE6_MASK)
14016 
14017 #define DIGTMP_TER_TPE7_MASK                     (0x800000U)
14018 #define DIGTMP_TER_TPE7_SHIFT                    (23U)
14019 /*! TPE7 - Tamper Pin Enable
14020  *  0b0..Disables
14021  *  0b1..Enables
14022  */
14023 #define DIGTMP_TER_TPE7(x)                       (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TPE7_SHIFT)) & DIGTMP_TER_TPE7_MASK)
14024 /*! @} */
14025 
14026 /*! @name PDR - Pin Direction */
14027 /*! @{ */
14028 
14029 #define DIGTMP_PDR_TPD0_MASK                     (0x1U)
14030 #define DIGTMP_PDR_TPD0_SHIFT                    (0U)
14031 /*! TPD0 - Tamper Pin Direction
14032  *  0b0..Input
14033  *  0b1..Output and drives the inverse of the expected value (tamper pin is asserted)
14034  */
14035 #define DIGTMP_PDR_TPD0(x)                       (((uint32_t)(((uint32_t)(x)) << DIGTMP_PDR_TPD0_SHIFT)) & DIGTMP_PDR_TPD0_MASK)
14036 
14037 #define DIGTMP_PDR_TPD1_MASK                     (0x2U)
14038 #define DIGTMP_PDR_TPD1_SHIFT                    (1U)
14039 /*! TPD1 - Tamper Pin Direction
14040  *  0b0..Input
14041  *  0b1..Output and drives the inverse of the expected value (tamper pin is asserted)
14042  */
14043 #define DIGTMP_PDR_TPD1(x)                       (((uint32_t)(((uint32_t)(x)) << DIGTMP_PDR_TPD1_SHIFT)) & DIGTMP_PDR_TPD1_MASK)
14044 
14045 #define DIGTMP_PDR_TPD2_MASK                     (0x4U)
14046 #define DIGTMP_PDR_TPD2_SHIFT                    (2U)
14047 /*! TPD2 - Tamper Pin Direction
14048  *  0b0..Input
14049  *  0b1..Output and drives the inverse of the expected value (tamper pin is asserted)
14050  */
14051 #define DIGTMP_PDR_TPD2(x)                       (((uint32_t)(((uint32_t)(x)) << DIGTMP_PDR_TPD2_SHIFT)) & DIGTMP_PDR_TPD2_MASK)
14052 
14053 #define DIGTMP_PDR_TPD3_MASK                     (0x8U)
14054 #define DIGTMP_PDR_TPD3_SHIFT                    (3U)
14055 /*! TPD3 - Tamper Pin Direction
14056  *  0b0..Input
14057  *  0b1..Output and drives the inverse of the expected value (tamper pin is asserted)
14058  */
14059 #define DIGTMP_PDR_TPD3(x)                       (((uint32_t)(((uint32_t)(x)) << DIGTMP_PDR_TPD3_SHIFT)) & DIGTMP_PDR_TPD3_MASK)
14060 
14061 #define DIGTMP_PDR_TPD4_MASK                     (0x10U)
14062 #define DIGTMP_PDR_TPD4_SHIFT                    (4U)
14063 /*! TPD4 - Tamper Pin Direction
14064  *  0b0..Input
14065  *  0b1..Output and drives the inverse of the expected value (tamper pin is asserted)
14066  */
14067 #define DIGTMP_PDR_TPD4(x)                       (((uint32_t)(((uint32_t)(x)) << DIGTMP_PDR_TPD4_SHIFT)) & DIGTMP_PDR_TPD4_MASK)
14068 
14069 #define DIGTMP_PDR_TPD5_MASK                     (0x20U)
14070 #define DIGTMP_PDR_TPD5_SHIFT                    (5U)
14071 /*! TPD5 - Tamper Pin Direction
14072  *  0b0..Input
14073  *  0b1..Output and drives the inverse of the expected value (tamper pin is asserted)
14074  */
14075 #define DIGTMP_PDR_TPD5(x)                       (((uint32_t)(((uint32_t)(x)) << DIGTMP_PDR_TPD5_SHIFT)) & DIGTMP_PDR_TPD5_MASK)
14076 
14077 #define DIGTMP_PDR_TPD6_MASK                     (0x40U)
14078 #define DIGTMP_PDR_TPD6_SHIFT                    (6U)
14079 /*! TPD6 - Tamper Pin Direction
14080  *  0b0..Input
14081  *  0b1..Output and drives the inverse of the expected value (tamper pin is asserted)
14082  */
14083 #define DIGTMP_PDR_TPD6(x)                       (((uint32_t)(((uint32_t)(x)) << DIGTMP_PDR_TPD6_SHIFT)) & DIGTMP_PDR_TPD6_MASK)
14084 
14085 #define DIGTMP_PDR_TPD7_MASK                     (0x80U)
14086 #define DIGTMP_PDR_TPD7_SHIFT                    (7U)
14087 /*! TPD7 - Tamper Pin Direction
14088  *  0b0..Input
14089  *  0b1..Output and drives the inverse of the expected value (tamper pin is asserted)
14090  */
14091 #define DIGTMP_PDR_TPD7(x)                       (((uint32_t)(((uint32_t)(x)) << DIGTMP_PDR_TPD7_SHIFT)) & DIGTMP_PDR_TPD7_MASK)
14092 
14093 #define DIGTMP_PDR_TPOD0_MASK                    (0x10000U)
14094 #define DIGTMP_PDR_TPOD0_SHIFT                   (16U)
14095 /*! TPOD0 - Tamper Pin Output Data
14096  *  0b0..Zero
14097  *  0b1..One
14098  */
14099 #define DIGTMP_PDR_TPOD0(x)                      (((uint32_t)(((uint32_t)(x)) << DIGTMP_PDR_TPOD0_SHIFT)) & DIGTMP_PDR_TPOD0_MASK)
14100 
14101 #define DIGTMP_PDR_TPOD1_MASK                    (0x20000U)
14102 #define DIGTMP_PDR_TPOD1_SHIFT                   (17U)
14103 /*! TPOD1 - Tamper Pin Output Data
14104  *  0b0..Zero
14105  *  0b1..One
14106  */
14107 #define DIGTMP_PDR_TPOD1(x)                      (((uint32_t)(((uint32_t)(x)) << DIGTMP_PDR_TPOD1_SHIFT)) & DIGTMP_PDR_TPOD1_MASK)
14108 
14109 #define DIGTMP_PDR_TPOD2_MASK                    (0x40000U)
14110 #define DIGTMP_PDR_TPOD2_SHIFT                   (18U)
14111 /*! TPOD2 - Tamper Pin Output Data
14112  *  0b0..Zero
14113  *  0b1..One
14114  */
14115 #define DIGTMP_PDR_TPOD2(x)                      (((uint32_t)(((uint32_t)(x)) << DIGTMP_PDR_TPOD2_SHIFT)) & DIGTMP_PDR_TPOD2_MASK)
14116 
14117 #define DIGTMP_PDR_TPOD3_MASK                    (0x80000U)
14118 #define DIGTMP_PDR_TPOD3_SHIFT                   (19U)
14119 /*! TPOD3 - Tamper Pin Output Data
14120  *  0b0..Zero
14121  *  0b1..One
14122  */
14123 #define DIGTMP_PDR_TPOD3(x)                      (((uint32_t)(((uint32_t)(x)) << DIGTMP_PDR_TPOD3_SHIFT)) & DIGTMP_PDR_TPOD3_MASK)
14124 
14125 #define DIGTMP_PDR_TPOD4_MASK                    (0x100000U)
14126 #define DIGTMP_PDR_TPOD4_SHIFT                   (20U)
14127 /*! TPOD4 - Tamper Pin Output Data
14128  *  0b0..Zero
14129  *  0b1..One
14130  */
14131 #define DIGTMP_PDR_TPOD4(x)                      (((uint32_t)(((uint32_t)(x)) << DIGTMP_PDR_TPOD4_SHIFT)) & DIGTMP_PDR_TPOD4_MASK)
14132 
14133 #define DIGTMP_PDR_TPOD5_MASK                    (0x200000U)
14134 #define DIGTMP_PDR_TPOD5_SHIFT                   (21U)
14135 /*! TPOD5 - Tamper Pin Output Data
14136  *  0b0..Zero
14137  *  0b1..One
14138  */
14139 #define DIGTMP_PDR_TPOD5(x)                      (((uint32_t)(((uint32_t)(x)) << DIGTMP_PDR_TPOD5_SHIFT)) & DIGTMP_PDR_TPOD5_MASK)
14140 
14141 #define DIGTMP_PDR_TPOD6_MASK                    (0x400000U)
14142 #define DIGTMP_PDR_TPOD6_SHIFT                   (22U)
14143 /*! TPOD6 - Tamper Pin Output Data
14144  *  0b0..Zero
14145  *  0b1..One
14146  */
14147 #define DIGTMP_PDR_TPOD6(x)                      (((uint32_t)(((uint32_t)(x)) << DIGTMP_PDR_TPOD6_SHIFT)) & DIGTMP_PDR_TPOD6_MASK)
14148 
14149 #define DIGTMP_PDR_TPOD7_MASK                    (0x800000U)
14150 #define DIGTMP_PDR_TPOD7_SHIFT                   (23U)
14151 /*! TPOD7 - Tamper Pin Output Data
14152  *  0b0..Zero
14153  *  0b1..One
14154  */
14155 #define DIGTMP_PDR_TPOD7(x)                      (((uint32_t)(((uint32_t)(x)) << DIGTMP_PDR_TPOD7_SHIFT)) & DIGTMP_PDR_TPOD7_MASK)
14156 /*! @} */
14157 
14158 /*! @name PPR - Pin Polarity */
14159 /*! @{ */
14160 
14161 #define DIGTMP_PPR_TPP0_MASK                     (0x1U)
14162 #define DIGTMP_PPR_TPP0_SHIFT                    (0U)
14163 /*! TPP0 - Tamper Pin n Polarity
14164  *  0b0..Not inverted
14165  *  0b1..Inverted
14166  */
14167 #define DIGTMP_PPR_TPP0(x)                       (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPP0_SHIFT)) & DIGTMP_PPR_TPP0_MASK)
14168 
14169 #define DIGTMP_PPR_TPP1_MASK                     (0x2U)
14170 #define DIGTMP_PPR_TPP1_SHIFT                    (1U)
14171 /*! TPP1 - Tamper Pin n Polarity
14172  *  0b0..Not inverted
14173  *  0b1..Inverted
14174  */
14175 #define DIGTMP_PPR_TPP1(x)                       (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPP1_SHIFT)) & DIGTMP_PPR_TPP1_MASK)
14176 
14177 #define DIGTMP_PPR_TPP2_MASK                     (0x4U)
14178 #define DIGTMP_PPR_TPP2_SHIFT                    (2U)
14179 /*! TPP2 - Tamper Pin n Polarity
14180  *  0b0..Not inverted
14181  *  0b1..Inverted
14182  */
14183 #define DIGTMP_PPR_TPP2(x)                       (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPP2_SHIFT)) & DIGTMP_PPR_TPP2_MASK)
14184 
14185 #define DIGTMP_PPR_TPP3_MASK                     (0x8U)
14186 #define DIGTMP_PPR_TPP3_SHIFT                    (3U)
14187 /*! TPP3 - Tamper Pin n Polarity
14188  *  0b0..Not inverted
14189  *  0b1..Inverted
14190  */
14191 #define DIGTMP_PPR_TPP3(x)                       (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPP3_SHIFT)) & DIGTMP_PPR_TPP3_MASK)
14192 
14193 #define DIGTMP_PPR_TPP4_MASK                     (0x10U)
14194 #define DIGTMP_PPR_TPP4_SHIFT                    (4U)
14195 /*! TPP4 - Tamper Pin n Polarity
14196  *  0b0..Not inverted
14197  *  0b1..Inverted
14198  */
14199 #define DIGTMP_PPR_TPP4(x)                       (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPP4_SHIFT)) & DIGTMP_PPR_TPP4_MASK)
14200 
14201 #define DIGTMP_PPR_TPP5_MASK                     (0x20U)
14202 #define DIGTMP_PPR_TPP5_SHIFT                    (5U)
14203 /*! TPP5 - Tamper Pin n Polarity
14204  *  0b0..Not inverted
14205  *  0b1..Inverted
14206  */
14207 #define DIGTMP_PPR_TPP5(x)                       (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPP5_SHIFT)) & DIGTMP_PPR_TPP5_MASK)
14208 
14209 #define DIGTMP_PPR_TPP6_MASK                     (0x40U)
14210 #define DIGTMP_PPR_TPP6_SHIFT                    (6U)
14211 /*! TPP6 - Tamper Pin n Polarity
14212  *  0b0..Not inverted
14213  *  0b1..Inverted
14214  */
14215 #define DIGTMP_PPR_TPP6(x)                       (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPP6_SHIFT)) & DIGTMP_PPR_TPP6_MASK)
14216 
14217 #define DIGTMP_PPR_TPP7_MASK                     (0x80U)
14218 #define DIGTMP_PPR_TPP7_SHIFT                    (7U)
14219 /*! TPP7 - Tamper Pin n Polarity
14220  *  0b0..Not inverted
14221  *  0b1..Inverted
14222  */
14223 #define DIGTMP_PPR_TPP7(x)                       (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPP7_SHIFT)) & DIGTMP_PPR_TPP7_MASK)
14224 
14225 #define DIGTMP_PPR_TPID0_MASK                    (0x10000U)
14226 #define DIGTMP_PPR_TPID0_SHIFT                   (16U)
14227 /*! TPID0 - Tamper Pin n Input Data
14228  *  0b0..Zero
14229  *  0b1..One
14230  */
14231 #define DIGTMP_PPR_TPID0(x)                      (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPID0_SHIFT)) & DIGTMP_PPR_TPID0_MASK)
14232 
14233 #define DIGTMP_PPR_TPID1_MASK                    (0x20000U)
14234 #define DIGTMP_PPR_TPID1_SHIFT                   (17U)
14235 /*! TPID1 - Tamper Pin n Input Data
14236  *  0b0..Zero
14237  *  0b1..One
14238  */
14239 #define DIGTMP_PPR_TPID1(x)                      (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPID1_SHIFT)) & DIGTMP_PPR_TPID1_MASK)
14240 
14241 #define DIGTMP_PPR_TPID2_MASK                    (0x40000U)
14242 #define DIGTMP_PPR_TPID2_SHIFT                   (18U)
14243 /*! TPID2 - Tamper Pin n Input Data
14244  *  0b0..Zero
14245  *  0b1..One
14246  */
14247 #define DIGTMP_PPR_TPID2(x)                      (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPID2_SHIFT)) & DIGTMP_PPR_TPID2_MASK)
14248 
14249 #define DIGTMP_PPR_TPID3_MASK                    (0x80000U)
14250 #define DIGTMP_PPR_TPID3_SHIFT                   (19U)
14251 /*! TPID3 - Tamper Pin n Input Data
14252  *  0b0..Zero
14253  *  0b1..One
14254  */
14255 #define DIGTMP_PPR_TPID3(x)                      (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPID3_SHIFT)) & DIGTMP_PPR_TPID3_MASK)
14256 
14257 #define DIGTMP_PPR_TPID4_MASK                    (0x100000U)
14258 #define DIGTMP_PPR_TPID4_SHIFT                   (20U)
14259 /*! TPID4 - Tamper Pin n Input Data
14260  *  0b0..Zero
14261  *  0b1..One
14262  */
14263 #define DIGTMP_PPR_TPID4(x)                      (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPID4_SHIFT)) & DIGTMP_PPR_TPID4_MASK)
14264 
14265 #define DIGTMP_PPR_TPID5_MASK                    (0x200000U)
14266 #define DIGTMP_PPR_TPID5_SHIFT                   (21U)
14267 /*! TPID5 - Tamper Pin n Input Data
14268  *  0b0..Zero
14269  *  0b1..One
14270  */
14271 #define DIGTMP_PPR_TPID5(x)                      (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPID5_SHIFT)) & DIGTMP_PPR_TPID5_MASK)
14272 
14273 #define DIGTMP_PPR_TPID6_MASK                    (0x400000U)
14274 #define DIGTMP_PPR_TPID6_SHIFT                   (22U)
14275 /*! TPID6 - Tamper Pin n Input Data
14276  *  0b0..Zero
14277  *  0b1..One
14278  */
14279 #define DIGTMP_PPR_TPID6(x)                      (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPID6_SHIFT)) & DIGTMP_PPR_TPID6_MASK)
14280 
14281 #define DIGTMP_PPR_TPID7_MASK                    (0x800000U)
14282 #define DIGTMP_PPR_TPID7_SHIFT                   (23U)
14283 /*! TPID7 - Tamper Pin n Input Data
14284  *  0b0..Zero
14285  *  0b1..One
14286  */
14287 #define DIGTMP_PPR_TPID7(x)                      (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPID7_SHIFT)) & DIGTMP_PPR_TPID7_MASK)
14288 /*! @} */
14289 
14290 /*! @name ATR - Active Tamper */
14291 /*! @{ */
14292 
14293 #define DIGTMP_ATR_ATSR_MASK                     (0xFFFFU)
14294 #define DIGTMP_ATR_ATSR_SHIFT                    (0U)
14295 /*! ATSR - Active Tamper Shift Register */
14296 #define DIGTMP_ATR_ATSR(x)                       (((uint32_t)(((uint32_t)(x)) << DIGTMP_ATR_ATSR_SHIFT)) & DIGTMP_ATR_ATSR_MASK)
14297 
14298 #define DIGTMP_ATR_ATP_MASK                      (0xFFFF0000U)
14299 #define DIGTMP_ATR_ATP_SHIFT                     (16U)
14300 /*! ATP - Active Tamper Polynomial */
14301 #define DIGTMP_ATR_ATP(x)                        (((uint32_t)(((uint32_t)(x)) << DIGTMP_ATR_ATP_SHIFT)) & DIGTMP_ATR_ATP_MASK)
14302 /*! @} */
14303 
14304 /* The count of DIGTMP_ATR */
14305 #define DIGTMP_ATR_COUNT                         (2U)
14306 
14307 /*! @name PGFR - Pin Glitch Filter */
14308 /*! @{ */
14309 
14310 #define DIGTMP_PGFR_GFW_MASK                     (0x3FU)
14311 #define DIGTMP_PGFR_GFW_SHIFT                    (0U)
14312 /*! GFW - Glitch Filter Width */
14313 #define DIGTMP_PGFR_GFW(x)                       (((uint32_t)(((uint32_t)(x)) << DIGTMP_PGFR_GFW_SHIFT)) & DIGTMP_PGFR_GFW_MASK)
14314 
14315 #define DIGTMP_PGFR_GFP_MASK                     (0x40U)
14316 #define DIGTMP_PGFR_GFP_SHIFT                    (6U)
14317 /*! GFP - Glitch Filter Prescaler
14318  *  0b0..512 Hz prescaler clock
14319  *  0b1..32.768 kHz clock
14320  */
14321 #define DIGTMP_PGFR_GFP(x)                       (((uint32_t)(((uint32_t)(x)) << DIGTMP_PGFR_GFP_SHIFT)) & DIGTMP_PGFR_GFP_MASK)
14322 
14323 #define DIGTMP_PGFR_GFE_MASK                     (0x80U)
14324 #define DIGTMP_PGFR_GFE_SHIFT                    (7U)
14325 /*! GFE - Glitch Filter Enable
14326  *  0b0..Bypasses
14327  *  0b1..Enables
14328  */
14329 #define DIGTMP_PGFR_GFE(x)                       (((uint32_t)(((uint32_t)(x)) << DIGTMP_PGFR_GFE_SHIFT)) & DIGTMP_PGFR_GFE_MASK)
14330 
14331 #define DIGTMP_PGFR_TPSW_MASK                    (0x300U)
14332 #define DIGTMP_PGFR_TPSW_SHIFT                   (8U)
14333 /*! TPSW - Tamper Pin Sample Width
14334  *  0b00..Continuous monitoring, pin sampling disabled
14335  *  0b01..2 cycles for pull enable and 1 cycle for input buffer enable
14336  *  0b10..4 cycles for pull enable and 2 cycles for input buffer enable
14337  *  0b11..8 cycles for pull enable and 4 cycles for input buffer enable
14338  */
14339 #define DIGTMP_PGFR_TPSW(x)                      (((uint32_t)(((uint32_t)(x)) << DIGTMP_PGFR_TPSW_SHIFT)) & DIGTMP_PGFR_TPSW_MASK)
14340 
14341 #define DIGTMP_PGFR_TPSF_MASK                    (0xC00U)
14342 #define DIGTMP_PGFR_TPSF_SHIFT                   (10U)
14343 /*! TPSF - Tamper Pin Sample Frequency
14344  *  0b00..Every 8 cycles
14345  *  0b01..Every 32 cycles
14346  *  0b10..Every 128 cycles
14347  *  0b11..Every 512 cycles
14348  */
14349 #define DIGTMP_PGFR_TPSF(x)                      (((uint32_t)(((uint32_t)(x)) << DIGTMP_PGFR_TPSF_SHIFT)) & DIGTMP_PGFR_TPSF_MASK)
14350 
14351 #define DIGTMP_PGFR_TPEX_MASK                    (0x30000U)
14352 #define DIGTMP_PGFR_TPEX_SHIFT                   (16U)
14353 /*! TPEX - Tamper Pin Expected
14354  *  0b00..Zero/passive tamper
14355  *  0b01..Active Tamper 0 output
14356  *  0b10..Active Tamper 1 output
14357  *  0b11..Active Tamper 0 output XORed with Active Tamper 1 output
14358  */
14359 #define DIGTMP_PGFR_TPEX(x)                      (((uint32_t)(((uint32_t)(x)) << DIGTMP_PGFR_TPEX_SHIFT)) & DIGTMP_PGFR_TPEX_MASK)
14360 
14361 #define DIGTMP_PGFR_TPE_MASK                     (0x1000000U)
14362 #define DIGTMP_PGFR_TPE_SHIFT                    (24U)
14363 /*! TPE - Tamper Pull Enable
14364  *  0b0..Disables
14365  *  0b1..Enables
14366  */
14367 #define DIGTMP_PGFR_TPE(x)                       (((uint32_t)(((uint32_t)(x)) << DIGTMP_PGFR_TPE_SHIFT)) & DIGTMP_PGFR_TPE_MASK)
14368 
14369 #define DIGTMP_PGFR_TPS_MASK                     (0x2000000U)
14370 #define DIGTMP_PGFR_TPS_SHIFT                    (25U)
14371 /*! TPS - Tamper Pull Select
14372  *  0b0..Asserts
14373  *  0b1..Negates
14374  */
14375 #define DIGTMP_PGFR_TPS(x)                       (((uint32_t)(((uint32_t)(x)) << DIGTMP_PGFR_TPS_SHIFT)) & DIGTMP_PGFR_TPS_MASK)
14376 /*! @} */
14377 
14378 /* The count of DIGTMP_PGFR */
14379 #define DIGTMP_PGFR_COUNT                        (8U)
14380 
14381 
14382 /*!
14383  * @}
14384  */ /* end of group DIGTMP_Register_Masks */
14385 
14386 
14387 /* DIGTMP - Peripheral instance base addresses */
14388 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
14389   /** Peripheral TDET0 base address */
14390   #define TDET0_BASE                               (0x50058000u)
14391   /** Peripheral TDET0 base address */
14392   #define TDET0_BASE_NS                            (0x40058000u)
14393   /** Peripheral TDET0 base pointer */
14394   #define TDET0                                    ((DIGTMP_Type *)TDET0_BASE)
14395   /** Peripheral TDET0 base pointer */
14396   #define TDET0_NS                                 ((DIGTMP_Type *)TDET0_BASE_NS)
14397   /** Array initializer of DIGTMP peripheral base addresses */
14398   #define DIGTMP_BASE_ADDRS                        { TDET0_BASE }
14399   /** Array initializer of DIGTMP peripheral base pointers */
14400   #define DIGTMP_BASE_PTRS                         { TDET0 }
14401   /** Array initializer of DIGTMP peripheral base addresses */
14402   #define DIGTMP_BASE_ADDRS_NS                     { TDET0_BASE_NS }
14403   /** Array initializer of DIGTMP peripheral base pointers */
14404   #define DIGTMP_BASE_PTRS_NS                      { TDET0_NS }
14405 #else
14406   /** Peripheral TDET0 base address */
14407   #define TDET0_BASE                               (0x40058000u)
14408   /** Peripheral TDET0 base pointer */
14409   #define TDET0                                    ((DIGTMP_Type *)TDET0_BASE)
14410   /** Array initializer of DIGTMP peripheral base addresses */
14411   #define DIGTMP_BASE_ADDRS                        { TDET0_BASE }
14412   /** Array initializer of DIGTMP peripheral base pointers */
14413   #define DIGTMP_BASE_PTRS                         { TDET0 }
14414 #endif
14415 
14416 /*!
14417  * @}
14418  */ /* end of group DIGTMP_Peripheral_Access_Layer */
14419 
14420 
14421 /* ----------------------------------------------------------------------------
14422    -- DM Peripheral Access Layer
14423    ---------------------------------------------------------------------------- */
14424 
14425 /*!
14426  * @addtogroup DM_Peripheral_Access_Layer DM Peripheral Access Layer
14427  * @{
14428  */
14429 
14430 /** DM - Register Layout Typedef */
14431 typedef struct {
14432   __IO uint32_t CSW;                               /**< Command and Status Word, offset: 0x0 */
14433   __IO uint32_t REQUEST;                           /**< Request Value, offset: 0x4 */
14434   __IO uint32_t RETURN;                            /**< Return Value, offset: 0x8 */
14435        uint8_t RESERVED_0[240];
14436   __I  uint32_t ID;                                /**< Identification, offset: 0xFC */
14437 } DM_Type;
14438 
14439 /* ----------------------------------------------------------------------------
14440    -- DM Register Masks
14441    ---------------------------------------------------------------------------- */
14442 
14443 /*!
14444  * @addtogroup DM_Register_Masks DM Register Masks
14445  * @{
14446  */
14447 
14448 /*! @name CSW - Command and Status Word */
14449 /*! @{ */
14450 
14451 #define DM_CSW_RESYNCH_REQ_MASK                  (0x1U)
14452 #define DM_CSW_RESYNCH_REQ_SHIFT                 (0U)
14453 /*! RESYNCH_REQ - Resynchronization Request
14454  *  0b0..No request
14455  *  0b1..Request for resynchronization
14456  */
14457 #define DM_CSW_RESYNCH_REQ(x)                    (((uint32_t)(((uint32_t)(x)) << DM_CSW_RESYNCH_REQ_SHIFT)) & DM_CSW_RESYNCH_REQ_MASK)
14458 
14459 #define DM_CSW_REQ_PENDING_MASK                  (0x2U)
14460 #define DM_CSW_REQ_PENDING_SHIFT                 (1U)
14461 /*! REQ_PENDING - Request Pending
14462  *  0b0..No request pending
14463  *  0b1..Request for resynchronization pending
14464  */
14465 #define DM_CSW_REQ_PENDING(x)                    (((uint32_t)(((uint32_t)(x)) << DM_CSW_REQ_PENDING_SHIFT)) & DM_CSW_REQ_PENDING_MASK)
14466 
14467 #define DM_CSW_DBG_OR_ERR_MASK                   (0x4U)
14468 #define DM_CSW_DBG_OR_ERR_SHIFT                  (2U)
14469 /*! DBG_OR_ERR - DBGMB Overrun Error
14470  *  0b0..No DBGMB Overrun error
14471  *  0b1..DBGMB overrun error. A DBGMB overrun occurred.
14472  */
14473 #define DM_CSW_DBG_OR_ERR(x)                     (((uint32_t)(((uint32_t)(x)) << DM_CSW_DBG_OR_ERR_SHIFT)) & DM_CSW_DBG_OR_ERR_MASK)
14474 
14475 #define DM_CSW_AHB_OR_ERR_MASK                   (0x8U)
14476 #define DM_CSW_AHB_OR_ERR_SHIFT                  (3U)
14477 /*! AHB_OR_ERR - AHB Overrun Error
14478  *  0b0..No AHB Overrun Error
14479  *  0b1..AHB Overrun Error. An AHB overrun occurred.
14480  */
14481 #define DM_CSW_AHB_OR_ERR(x)                     (((uint32_t)(((uint32_t)(x)) << DM_CSW_AHB_OR_ERR_SHIFT)) & DM_CSW_AHB_OR_ERR_MASK)
14482 
14483 #define DM_CSW_SOFT_RESET_MASK                   (0x10U)
14484 #define DM_CSW_SOFT_RESET_SHIFT                  (4U)
14485 /*! SOFT_RESET - Soft Reset */
14486 #define DM_CSW_SOFT_RESET(x)                     (((uint32_t)(((uint32_t)(x)) << DM_CSW_SOFT_RESET_SHIFT)) & DM_CSW_SOFT_RESET_MASK)
14487 
14488 #define DM_CSW_CHIP_RESET_REQ_MASK               (0x20U)
14489 #define DM_CSW_CHIP_RESET_REQ_SHIFT              (5U)
14490 /*! CHIP_RESET_REQ - Chip Reset Request */
14491 #define DM_CSW_CHIP_RESET_REQ(x)                 (((uint32_t)(((uint32_t)(x)) << DM_CSW_CHIP_RESET_REQ_SHIFT)) & DM_CSW_CHIP_RESET_REQ_MASK)
14492 /*! @} */
14493 
14494 /*! @name REQUEST - Request Value */
14495 /*! @{ */
14496 
14497 #define DM_REQUEST_REQUEST_MASK                  (0xFFFFFFFFU)
14498 #define DM_REQUEST_REQUEST_SHIFT                 (0U)
14499 /*! REQUEST - Request Value */
14500 #define DM_REQUEST_REQUEST(x)                    (((uint32_t)(((uint32_t)(x)) << DM_REQUEST_REQUEST_SHIFT)) & DM_REQUEST_REQUEST_MASK)
14501 /*! @} */
14502 
14503 /*! @name RETURN - Return Value */
14504 /*! @{ */
14505 
14506 #define DM_RETURN_RET_MASK                       (0xFFFFFFFFU)
14507 #define DM_RETURN_RET_SHIFT                      (0U)
14508 /*! RET - Return Value */
14509 #define DM_RETURN_RET(x)                         (((uint32_t)(((uint32_t)(x)) << DM_RETURN_RET_SHIFT)) & DM_RETURN_RET_MASK)
14510 /*! @} */
14511 
14512 /*! @name ID - Identification */
14513 /*! @{ */
14514 
14515 #define DM_ID_ID_MASK                            (0xFFFFFFFFU)
14516 #define DM_ID_ID_SHIFT                           (0U)
14517 /*! ID - Identification Value */
14518 #define DM_ID_ID(x)                              (((uint32_t)(((uint32_t)(x)) << DM_ID_ID_SHIFT)) & DM_ID_ID_MASK)
14519 /*! @} */
14520 
14521 
14522 /*!
14523  * @}
14524  */ /* end of group DM_Register_Masks */
14525 
14526 
14527 /* DM - Peripheral instance base addresses */
14528 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
14529   /** Peripheral DM0 base address */
14530   #define DM0_BASE                                 (0x500BD000u)
14531   /** Peripheral DM0 base address */
14532   #define DM0_BASE_NS                              (0x400BD000u)
14533   /** Peripheral DM0 base pointer */
14534   #define DM0                                      ((DM_Type *)DM0_BASE)
14535   /** Peripheral DM0 base pointer */
14536   #define DM0_NS                                   ((DM_Type *)DM0_BASE_NS)
14537   /** Array initializer of DM peripheral base addresses */
14538   #define DM_BASE_ADDRS                            { DM0_BASE }
14539   /** Array initializer of DM peripheral base pointers */
14540   #define DM_BASE_PTRS                             { DM0 }
14541   /** Array initializer of DM peripheral base addresses */
14542   #define DM_BASE_ADDRS_NS                         { DM0_BASE_NS }
14543   /** Array initializer of DM peripheral base pointers */
14544   #define DM_BASE_PTRS_NS                          { DM0_NS }
14545 #else
14546   /** Peripheral DM0 base address */
14547   #define DM0_BASE                                 (0x400BD000u)
14548   /** Peripheral DM0 base pointer */
14549   #define DM0                                      ((DM_Type *)DM0_BASE)
14550   /** Array initializer of DM peripheral base addresses */
14551   #define DM_BASE_ADDRS                            { DM0_BASE }
14552   /** Array initializer of DM peripheral base pointers */
14553   #define DM_BASE_PTRS                             { DM0 }
14554 #endif
14555 
14556 /*!
14557  * @}
14558  */ /* end of group DM_Peripheral_Access_Layer */
14559 
14560 
14561 /* ----------------------------------------------------------------------------
14562    -- DMA Peripheral Access Layer
14563    ---------------------------------------------------------------------------- */
14564 
14565 /*!
14566  * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
14567  * @{
14568  */
14569 
14570 /** DMA - Register Layout Typedef */
14571 typedef struct {
14572   __IO uint32_t MP_CSR;                            /**< Management Page Control, offset: 0x0 */
14573   __I  uint32_t MP_ES;                             /**< Management Page Error Status, offset: 0x4 */
14574   __I  uint32_t MP_INT;                            /**< Management Page Interrupt Request Status, offset: 0x8 */
14575   __I  uint32_t MP_HRS;                            /**< Management Page Hardware Request Status, offset: 0xC */
14576        uint8_t RESERVED_0[240];
14577   __IO uint32_t CH_GRPRI[16];                      /**< Channel Arbitration Group, array offset: 0x100, array step: 0x4 */
14578        uint8_t RESERVED_1[3776];
14579   struct {                                         /* offset: 0x1000, array step: 0x1000 */
14580     __IO uint32_t CH_CSR;                            /**< Channel Control and Status, array offset: 0x1000, array step: 0x1000 */
14581     __IO uint32_t CH_ES;                             /**< Channel Error Status, array offset: 0x1004, array step: 0x1000 */
14582     __IO uint32_t CH_INT;                            /**< Channel Interrupt Status, array offset: 0x1008, array step: 0x1000 */
14583     __IO uint32_t CH_SBR;                            /**< Channel System Bus, array offset: 0x100C, array step: 0x1000 */
14584     __IO uint32_t CH_PRI;                            /**< Channel Priority, array offset: 0x1010, array step: 0x1000 */
14585     __IO uint32_t CH_MUX;                            /**< Channel Multiplexor Configuration, array offset: 0x1014, array step: 0x1000 */
14586          uint8_t RESERVED_0[8];
14587     __IO uint32_t TCD_SADDR;                         /**< TCD Source Address, array offset: 0x1020, array step: 0x1000 */
14588     __IO uint16_t TCD_SOFF;                          /**< TCD Signed Source Address Offset, array offset: 0x1024, array step: 0x1000 */
14589     __IO uint16_t TCD_ATTR;                          /**< TCD Transfer Attributes, array offset: 0x1026, array step: 0x1000 */
14590     union {                                          /* offset: 0x1028, array step: 0x1000 */
14591       __IO uint32_t TCD_NBYTES_MLOFFNO;                /**< TCD Transfer Size Without Minor Loop Offsets, array offset: 0x1028, array step: 0x1000 */
14592       __IO uint32_t TCD_NBYTES_MLOFFYES;               /**< TCD Transfer Size with Minor Loop Offsets, array offset: 0x1028, array step: 0x1000 */
14593     };
14594     __IO uint32_t TCD_SLAST_SDA;                     /**< TCD Last Source Address Adjustment / Store DADDR Address, array offset: 0x102C, array step: 0x1000 */
14595     __IO uint32_t TCD_DADDR;                         /**< TCD Destination Address, array offset: 0x1030, array step: 0x1000 */
14596     __IO uint16_t TCD_DOFF;                          /**< TCD Signed Destination Address Offset, array offset: 0x1034, array step: 0x1000 */
14597     union {                                          /* offset: 0x1036, array step: 0x1000 */
14598       __IO uint16_t TCD_CITER_ELINKNO;                 /**< TCD Current Major Loop Count (Minor Loop Channel Linking Disabled), array offset: 0x1036, array step: 0x1000 */
14599       __IO uint16_t TCD_CITER_ELINKYES;                /**< TCD Current Major Loop Count (Minor Loop Channel Linking Enabled), array offset: 0x1036, array step: 0x1000 */
14600     };
14601     __IO uint32_t TCD_DLAST_SGA;                     /**< TCD Last Destination Address Adjustment / Scatter Gather Address, array offset: 0x1038, array step: 0x1000 */
14602     __IO uint16_t TCD_CSR;                           /**< TCD Control and Status, array offset: 0x103C, array step: 0x1000 */
14603     union {                                          /* offset: 0x103E, array step: 0x1000 */
14604       __IO uint16_t TCD_BITER_ELINKNO;                 /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled), array offset: 0x103E, array step: 0x1000 */
14605       __IO uint16_t TCD_BITER_ELINKYES;                /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled), array offset: 0x103E, array step: 0x1000 */
14606     };
14607          uint8_t RESERVED_1[4032];
14608   } CH[16];
14609 } DMA_Type;
14610 
14611 /* ----------------------------------------------------------------------------
14612    -- DMA Register Masks
14613    ---------------------------------------------------------------------------- */
14614 
14615 /*!
14616  * @addtogroup DMA_Register_Masks DMA Register Masks
14617  * @{
14618  */
14619 
14620 /*! @name MP_CSR - Management Page Control */
14621 /*! @{ */
14622 
14623 #define DMA_MP_CSR_EDBG_MASK                     (0x2U)
14624 #define DMA_MP_CSR_EDBG_SHIFT                    (1U)
14625 /*! EDBG - Enable Debug
14626  *  0b0..Debug mode disabled
14627  *  0b1..Debug mode is enabled.
14628  */
14629 #define DMA_MP_CSR_EDBG(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_EDBG_SHIFT)) & DMA_MP_CSR_EDBG_MASK)
14630 
14631 #define DMA_MP_CSR_ERCA_MASK                     (0x4U)
14632 #define DMA_MP_CSR_ERCA_SHIFT                    (2U)
14633 /*! ERCA - Enable Round Robin Channel Arbitration
14634  *  0b0..Round-robin channel arbitration disabled
14635  *  0b1..Round-robin channel arbitration enabled
14636  */
14637 #define DMA_MP_CSR_ERCA(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ERCA_SHIFT)) & DMA_MP_CSR_ERCA_MASK)
14638 
14639 #define DMA_MP_CSR_HAE_MASK                      (0x10U)
14640 #define DMA_MP_CSR_HAE_SHIFT                     (4U)
14641 /*! HAE - Halt After Error
14642  *  0b0..Normal operation
14643  *  0b1..Any error causes the HALT field to be set to 1
14644  */
14645 #define DMA_MP_CSR_HAE(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_HAE_SHIFT)) & DMA_MP_CSR_HAE_MASK)
14646 
14647 #define DMA_MP_CSR_HALT_MASK                     (0x20U)
14648 #define DMA_MP_CSR_HALT_SHIFT                    (5U)
14649 /*! HALT - Halt DMA Operations
14650  *  0b0..Normal operation
14651  *  0b1..Stall the start of any new channels
14652  */
14653 #define DMA_MP_CSR_HALT(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_HALT_SHIFT)) & DMA_MP_CSR_HALT_MASK)
14654 
14655 #define DMA_MP_CSR_GCLC_MASK                     (0x40U)
14656 #define DMA_MP_CSR_GCLC_SHIFT                    (6U)
14657 /*! GCLC - Global Channel Linking Control
14658  *  0b0..Channel linking disabled for all channels
14659  *  0b1..Channel linking available and controlled by each channel's link settings
14660  */
14661 #define DMA_MP_CSR_GCLC(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_GCLC_SHIFT)) & DMA_MP_CSR_GCLC_MASK)
14662 
14663 #define DMA_MP_CSR_GMRC_MASK                     (0x80U)
14664 #define DMA_MP_CSR_GMRC_SHIFT                    (7U)
14665 /*! GMRC - Global Master ID Replication Control
14666  *  0b0..Master ID replication disabled for all channels
14667  *  0b1..Master ID replication available and controlled by each channel's CHn_SBR[EMI] setting
14668  */
14669 #define DMA_MP_CSR_GMRC(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_GMRC_SHIFT)) & DMA_MP_CSR_GMRC_MASK)
14670 
14671 #define DMA_MP_CSR_ECX_MASK                      (0x100U)
14672 #define DMA_MP_CSR_ECX_SHIFT                     (8U)
14673 /*! ECX - Cancel Transfer With Error
14674  *  0b0..Normal operation
14675  *  0b1..Cancel the remaining data transfer
14676  */
14677 #define DMA_MP_CSR_ECX(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ECX_SHIFT)) & DMA_MP_CSR_ECX_MASK)
14678 
14679 #define DMA_MP_CSR_CX_MASK                       (0x200U)
14680 #define DMA_MP_CSR_CX_SHIFT                      (9U)
14681 /*! CX - Cancel Transfer
14682  *  0b0..Normal operation
14683  *  0b1..Cancel the remaining data transfer
14684  */
14685 #define DMA_MP_CSR_CX(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_CX_SHIFT)) & DMA_MP_CSR_CX_MASK)
14686 
14687 #define DMA_MP_CSR_ACTIVE_ID_MASK                (0xF000000U)
14688 #define DMA_MP_CSR_ACTIVE_ID_SHIFT               (24U)
14689 /*! ACTIVE_ID - Active Channel ID */
14690 #define DMA_MP_CSR_ACTIVE_ID(x)                  (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ACTIVE_ID_SHIFT)) & DMA_MP_CSR_ACTIVE_ID_MASK)
14691 
14692 #define DMA_MP_CSR_ACTIVE_MASK                   (0x80000000U)
14693 #define DMA_MP_CSR_ACTIVE_SHIFT                  (31U)
14694 /*! ACTIVE - DMA Active Status
14695  *  0b0..eDMA is idle
14696  *  0b1..eDMA is executing a channel
14697  */
14698 #define DMA_MP_CSR_ACTIVE(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ACTIVE_SHIFT)) & DMA_MP_CSR_ACTIVE_MASK)
14699 /*! @} */
14700 
14701 /*! @name MP_ES - Management Page Error Status */
14702 /*! @{ */
14703 
14704 #define DMA_MP_ES_DBE_MASK                       (0x1U)
14705 #define DMA_MP_ES_DBE_SHIFT                      (0U)
14706 /*! DBE - Destination Bus Error
14707  *  0b0..No destination bus error
14708  *  0b1..Last recorded error was a bus error on a destination write
14709  */
14710 #define DMA_MP_ES_DBE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_DBE_SHIFT)) & DMA_MP_ES_DBE_MASK)
14711 
14712 #define DMA_MP_ES_SBE_MASK                       (0x2U)
14713 #define DMA_MP_ES_SBE_SHIFT                      (1U)
14714 /*! SBE - Source Bus Error
14715  *  0b0..No source bus error
14716  *  0b1..Last recorded error was a bus error on a source read
14717  */
14718 #define DMA_MP_ES_SBE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SBE_SHIFT)) & DMA_MP_ES_SBE_MASK)
14719 
14720 #define DMA_MP_ES_SGE_MASK                       (0x4U)
14721 #define DMA_MP_ES_SGE_SHIFT                      (2U)
14722 /*! SGE - Scatter/Gather Configuration Error
14723  *  0b0..No scatter/gather configuration error
14724  *  0b1..Last recorded error was a configuration error detected in the TCDn_DLAST_SGA field
14725  */
14726 #define DMA_MP_ES_SGE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SGE_SHIFT)) & DMA_MP_ES_SGE_MASK)
14727 
14728 #define DMA_MP_ES_NCE_MASK                       (0x8U)
14729 #define DMA_MP_ES_NCE_SHIFT                      (3U)
14730 /*! NCE - NBYTES/CITER Configuration Error
14731  *  0b0..No NBYTES/CITER configuration error
14732  *  0b1..The last recorded error was NBYTES equal to zero or a CITER not equal to BITER error
14733  */
14734 #define DMA_MP_ES_NCE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_NCE_SHIFT)) & DMA_MP_ES_NCE_MASK)
14735 
14736 #define DMA_MP_ES_DOE_MASK                       (0x10U)
14737 #define DMA_MP_ES_DOE_SHIFT                      (4U)
14738 /*! DOE - Destination Offset Error
14739  *  0b0..No destination offset configuration error
14740  *  0b1..Last recorded error was a configuration error detected in the TCDn_DOFF field
14741  */
14742 #define DMA_MP_ES_DOE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_DOE_SHIFT)) & DMA_MP_ES_DOE_MASK)
14743 
14744 #define DMA_MP_ES_DAE_MASK                       (0x20U)
14745 #define DMA_MP_ES_DAE_SHIFT                      (5U)
14746 /*! DAE - Destination Address Error
14747  *  0b0..No destination address configuration error
14748  *  0b1..Last recorded error was a configuration error detected in the TCDn_DADDR field
14749  */
14750 #define DMA_MP_ES_DAE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_DAE_SHIFT)) & DMA_MP_ES_DAE_MASK)
14751 
14752 #define DMA_MP_ES_SOE_MASK                       (0x40U)
14753 #define DMA_MP_ES_SOE_SHIFT                      (6U)
14754 /*! SOE - Source Offset Error
14755  *  0b0..No source offset configuration error
14756  *  0b1..Last recorded error was a configuration error detected in the TCDn_SOFF field
14757  */
14758 #define DMA_MP_ES_SOE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SOE_SHIFT)) & DMA_MP_ES_SOE_MASK)
14759 
14760 #define DMA_MP_ES_SAE_MASK                       (0x80U)
14761 #define DMA_MP_ES_SAE_SHIFT                      (7U)
14762 /*! SAE - Source Address Error
14763  *  0b0..No source address configuration error
14764  *  0b1..Last recorded error was a configuration error detected in the TCDn_SADDR field
14765  */
14766 #define DMA_MP_ES_SAE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SAE_SHIFT)) & DMA_MP_ES_SAE_MASK)
14767 
14768 #define DMA_MP_ES_ECX_MASK                       (0x100U)
14769 #define DMA_MP_ES_ECX_SHIFT                      (8U)
14770 /*! ECX - Transfer Canceled
14771  *  0b0..No canceled transfers
14772  *  0b1..Last recorded entry was a canceled transfer by the error cancel transfer input
14773  */
14774 #define DMA_MP_ES_ECX(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_ECX_SHIFT)) & DMA_MP_ES_ECX_MASK)
14775 
14776 #define DMA_MP_ES_ERRCHN_MASK                    (0xF000000U)
14777 #define DMA_MP_ES_ERRCHN_SHIFT                   (24U)
14778 /*! ERRCHN - Error Channel Number or Canceled Channel Number */
14779 #define DMA_MP_ES_ERRCHN(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_ERRCHN_SHIFT)) & DMA_MP_ES_ERRCHN_MASK)
14780 
14781 #define DMA_MP_ES_VLD_MASK                       (0x80000000U)
14782 #define DMA_MP_ES_VLD_SHIFT                      (31U)
14783 /*! VLD - Valid
14784  *  0b0..No CHn_ES[ERR] fields are set to 1
14785  *  0b1..At least one CHn_ES[ERR] field is set to 1, indicating a valid error exists that software has not cleared
14786  */
14787 #define DMA_MP_ES_VLD(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_VLD_SHIFT)) & DMA_MP_ES_VLD_MASK)
14788 /*! @} */
14789 
14790 /*! @name MP_INT - Management Page Interrupt Request Status */
14791 /*! @{ */
14792 
14793 #define DMA_MP_INT_INT_MASK                      (0xFFFFU)
14794 #define DMA_MP_INT_INT_SHIFT                     (0U)
14795 /*! INT - Interrupt Request Status */
14796 #define DMA_MP_INT_INT(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_MP_INT_INT_SHIFT)) & DMA_MP_INT_INT_MASK)
14797 /*! @} */
14798 
14799 /*! @name MP_HRS - Management Page Hardware Request Status */
14800 /*! @{ */
14801 
14802 #define DMA_MP_HRS_HRS_MASK                      (0xFFFFFFFFU)
14803 #define DMA_MP_HRS_HRS_SHIFT                     (0U)
14804 /*! HRS - Hardware Request Status */
14805 #define DMA_MP_HRS_HRS(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_MP_HRS_HRS_SHIFT)) & DMA_MP_HRS_HRS_MASK)
14806 /*! @} */
14807 
14808 /*! @name CH_GRPRI - Channel Arbitration Group */
14809 /*! @{ */
14810 
14811 #define DMA_CH_GRPRI_GRPRI_MASK                  (0x1FU)
14812 #define DMA_CH_GRPRI_GRPRI_SHIFT                 (0U)
14813 /*! GRPRI - Arbitration Group For Channel n */
14814 #define DMA_CH_GRPRI_GRPRI(x)                    (((uint32_t)(((uint32_t)(x)) << DMA_CH_GRPRI_GRPRI_SHIFT)) & DMA_CH_GRPRI_GRPRI_MASK)
14815 /*! @} */
14816 
14817 /* The count of DMA_CH_GRPRI */
14818 #define DMA_CH_GRPRI_COUNT                       (16U)
14819 
14820 /*! @name CH_CSR - Channel Control and Status */
14821 /*! @{ */
14822 
14823 #define DMA_CH_CSR_ERQ_MASK                      (0x1U)
14824 #define DMA_CH_CSR_ERQ_SHIFT                     (0U)
14825 /*! ERQ - Enable DMA Request
14826  *  0b0..DMA hardware request signal for corresponding channel disabled
14827  *  0b1..DMA hardware request signal for corresponding channel enabled
14828  */
14829 #define DMA_CH_CSR_ERQ(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_ERQ_SHIFT)) & DMA_CH_CSR_ERQ_MASK)
14830 
14831 #define DMA_CH_CSR_EARQ_MASK                     (0x2U)
14832 #define DMA_CH_CSR_EARQ_SHIFT                    (1U)
14833 /*! EARQ - Enable Asynchronous DMA Request
14834  *  0b0..Disable asynchronous DMA request for the channel
14835  *  0b1..Enable asynchronous DMA request for the channel
14836  */
14837 #define DMA_CH_CSR_EARQ(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_EARQ_SHIFT)) & DMA_CH_CSR_EARQ_MASK)
14838 
14839 #define DMA_CH_CSR_EEI_MASK                      (0x4U)
14840 #define DMA_CH_CSR_EEI_SHIFT                     (2U)
14841 /*! EEI - Enable Error Interrupt
14842  *  0b0..Error signal for corresponding channel does not generate error interrupt
14843  *  0b1..Assertion of error signal for corresponding channel generates error interrupt request
14844  */
14845 #define DMA_CH_CSR_EEI(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_EEI_SHIFT)) & DMA_CH_CSR_EEI_MASK)
14846 
14847 #define DMA_CH_CSR_EBW_MASK                      (0x8U)
14848 #define DMA_CH_CSR_EBW_SHIFT                     (3U)
14849 /*! EBW - Enable Buffered Writes
14850  *  0b0..Buffered writes on system bus disabled
14851  *  0b1..Buffered writes on system bus enabled
14852  */
14853 #define DMA_CH_CSR_EBW(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_EBW_SHIFT)) & DMA_CH_CSR_EBW_MASK)
14854 
14855 #define DMA_CH_CSR_DONE_MASK                     (0x40000000U)
14856 #define DMA_CH_CSR_DONE_SHIFT                    (30U)
14857 /*! DONE - Channel Done */
14858 #define DMA_CH_CSR_DONE(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_DONE_SHIFT)) & DMA_CH_CSR_DONE_MASK)
14859 
14860 #define DMA_CH_CSR_ACTIVE_MASK                   (0x80000000U)
14861 #define DMA_CH_CSR_ACTIVE_SHIFT                  (31U)
14862 /*! ACTIVE - Channel Active */
14863 #define DMA_CH_CSR_ACTIVE(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_ACTIVE_SHIFT)) & DMA_CH_CSR_ACTIVE_MASK)
14864 /*! @} */
14865 
14866 /* The count of DMA_CH_CSR */
14867 #define DMA_CH_CSR_COUNT                         (16U)
14868 
14869 /*! @name CH_ES - Channel Error Status */
14870 /*! @{ */
14871 
14872 #define DMA_CH_ES_DBE_MASK                       (0x1U)
14873 #define DMA_CH_ES_DBE_SHIFT                      (0U)
14874 /*! DBE - Destination Bus Error
14875  *  0b0..No destination bus error
14876  *  0b1..Last recorded error was bus error on destination write
14877  */
14878 #define DMA_CH_ES_DBE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_DBE_SHIFT)) & DMA_CH_ES_DBE_MASK)
14879 
14880 #define DMA_CH_ES_SBE_MASK                       (0x2U)
14881 #define DMA_CH_ES_SBE_SHIFT                      (1U)
14882 /*! SBE - Source Bus Error
14883  *  0b0..No source bus error
14884  *  0b1..Last recorded error was bus error on source read
14885  */
14886 #define DMA_CH_ES_SBE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SBE_SHIFT)) & DMA_CH_ES_SBE_MASK)
14887 
14888 #define DMA_CH_ES_SGE_MASK                       (0x4U)
14889 #define DMA_CH_ES_SGE_SHIFT                      (2U)
14890 /*! SGE - Scatter/Gather Configuration Error
14891  *  0b0..No scatter/gather configuration error
14892  *  0b1..Last recorded error was a configuration error detected in the TCDn_DLAST_SGA field
14893  */
14894 #define DMA_CH_ES_SGE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SGE_SHIFT)) & DMA_CH_ES_SGE_MASK)
14895 
14896 #define DMA_CH_ES_NCE_MASK                       (0x8U)
14897 #define DMA_CH_ES_NCE_SHIFT                      (3U)
14898 /*! NCE - NBYTES/CITER Configuration Error
14899  *  0b0..No NBYTES/CITER configuration error
14900  *  0b1..Last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields
14901  */
14902 #define DMA_CH_ES_NCE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_NCE_SHIFT)) & DMA_CH_ES_NCE_MASK)
14903 
14904 #define DMA_CH_ES_DOE_MASK                       (0x10U)
14905 #define DMA_CH_ES_DOE_SHIFT                      (4U)
14906 /*! DOE - Destination Offset Error
14907  *  0b0..No destination offset configuration error
14908  *  0b1..Last recorded error was a configuration error detected in the TCDn_DOFF field
14909  */
14910 #define DMA_CH_ES_DOE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_DOE_SHIFT)) & DMA_CH_ES_DOE_MASK)
14911 
14912 #define DMA_CH_ES_DAE_MASK                       (0x20U)
14913 #define DMA_CH_ES_DAE_SHIFT                      (5U)
14914 /*! DAE - Destination Address Error
14915  *  0b0..No destination address configuration error
14916  *  0b1..Last recorded error was a configuration error detected in the TCDn_DADDR field
14917  */
14918 #define DMA_CH_ES_DAE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_DAE_SHIFT)) & DMA_CH_ES_DAE_MASK)
14919 
14920 #define DMA_CH_ES_SOE_MASK                       (0x40U)
14921 #define DMA_CH_ES_SOE_SHIFT                      (6U)
14922 /*! SOE - Source Offset Error
14923  *  0b0..No source offset configuration error
14924  *  0b1..Last recorded error was a configuration error detected in the TCDn_SOFF field
14925  */
14926 #define DMA_CH_ES_SOE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SOE_SHIFT)) & DMA_CH_ES_SOE_MASK)
14927 
14928 #define DMA_CH_ES_SAE_MASK                       (0x80U)
14929 #define DMA_CH_ES_SAE_SHIFT                      (7U)
14930 /*! SAE - Source Address Error
14931  *  0b0..No source address configuration error
14932  *  0b1..Last recorded error was a configuration error detected in the TCDn_SADDR field
14933  */
14934 #define DMA_CH_ES_SAE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SAE_SHIFT)) & DMA_CH_ES_SAE_MASK)
14935 
14936 #define DMA_CH_ES_ERR_MASK                       (0x80000000U)
14937 #define DMA_CH_ES_ERR_SHIFT                      (31U)
14938 /*! ERR - Error In Channel
14939  *  0b0..An error in this channel has not occurred
14940  *  0b1..An error in this channel has occurred
14941  */
14942 #define DMA_CH_ES_ERR(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_ERR_SHIFT)) & DMA_CH_ES_ERR_MASK)
14943 /*! @} */
14944 
14945 /* The count of DMA_CH_ES */
14946 #define DMA_CH_ES_COUNT                          (16U)
14947 
14948 /*! @name CH_INT - Channel Interrupt Status */
14949 /*! @{ */
14950 
14951 #define DMA_CH_INT_INT_MASK                      (0x1U)
14952 #define DMA_CH_INT_INT_SHIFT                     (0U)
14953 /*! INT - Interrupt Request
14954  *  0b0..Interrupt request for corresponding channel cleared
14955  *  0b1..Interrupt request for corresponding channel active
14956  */
14957 #define DMA_CH_INT_INT(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_INT_INT_SHIFT)) & DMA_CH_INT_INT_MASK)
14958 /*! @} */
14959 
14960 /* The count of DMA_CH_INT */
14961 #define DMA_CH_INT_COUNT                         (16U)
14962 
14963 /*! @name CH_SBR - Channel System Bus */
14964 /*! @{ */
14965 
14966 #define DMA_CH_SBR_MID_MASK                      (0x1FU)
14967 #define DMA_CH_SBR_MID_SHIFT                     (0U)
14968 /*! MID - Master ID */
14969 #define DMA_CH_SBR_MID(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_MID_SHIFT)) & DMA_CH_SBR_MID_MASK)
14970 
14971 #define DMA_CH_SBR_SEC_MASK                      (0x4000U)
14972 #define DMA_CH_SBR_SEC_SHIFT                     (14U)
14973 /*! SEC - Security Level
14974  *  0b0..Nonsecure protection level for DMA transfers
14975  *  0b1..Secure protection level for DMA transfers
14976  */
14977 #define DMA_CH_SBR_SEC(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_SEC_SHIFT)) & DMA_CH_SBR_SEC_MASK)
14978 
14979 #define DMA_CH_SBR_PAL_MASK                      (0x8000U)
14980 #define DMA_CH_SBR_PAL_SHIFT                     (15U)
14981 /*! PAL - Privileged Access Level
14982  *  0b0..User protection level for DMA transfers
14983  *  0b1..Privileged protection level for DMA transfers
14984  */
14985 #define DMA_CH_SBR_PAL(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_PAL_SHIFT)) & DMA_CH_SBR_PAL_MASK)
14986 
14987 #define DMA_CH_SBR_EMI_MASK                      (0x10000U)
14988 #define DMA_CH_SBR_EMI_SHIFT                     (16U)
14989 /*! EMI - Enable Master ID Replication
14990  *  0b0..Master ID replication is disabled
14991  *  0b1..Master ID replication is enabled
14992  */
14993 #define DMA_CH_SBR_EMI(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_EMI_SHIFT)) & DMA_CH_SBR_EMI_MASK)
14994 /*! @} */
14995 
14996 /* The count of DMA_CH_SBR */
14997 #define DMA_CH_SBR_COUNT                         (16U)
14998 
14999 /*! @name CH_PRI - Channel Priority */
15000 /*! @{ */
15001 
15002 #define DMA_CH_PRI_APL_MASK                      (0x7U)
15003 #define DMA_CH_PRI_APL_SHIFT                     (0U)
15004 /*! APL - Arbitration Priority Level */
15005 #define DMA_CH_PRI_APL(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_PRI_APL_SHIFT)) & DMA_CH_PRI_APL_MASK)
15006 
15007 #define DMA_CH_PRI_DPA_MASK                      (0x40000000U)
15008 #define DMA_CH_PRI_DPA_SHIFT                     (30U)
15009 /*! DPA - Disable Preempt Ability
15010  *  0b0..Channel can suspend a lower-priority channel
15011  *  0b1..Channel cannot suspend any other channel, regardless of channel priority
15012  */
15013 #define DMA_CH_PRI_DPA(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_PRI_DPA_SHIFT)) & DMA_CH_PRI_DPA_MASK)
15014 
15015 #define DMA_CH_PRI_ECP_MASK                      (0x80000000U)
15016 #define DMA_CH_PRI_ECP_SHIFT                     (31U)
15017 /*! ECP - Enable Channel Preemption
15018  *  0b0..Channel cannot be suspended by a higher-priority channel's service request
15019  *  0b1..Channel can be temporarily suspended by a higher-priority channel's service request
15020  */
15021 #define DMA_CH_PRI_ECP(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_PRI_ECP_SHIFT)) & DMA_CH_PRI_ECP_MASK)
15022 /*! @} */
15023 
15024 /* The count of DMA_CH_PRI */
15025 #define DMA_CH_PRI_COUNT                         (16U)
15026 
15027 /*! @name CH_MUX - Channel Multiplexor Configuration */
15028 /*! @{ */
15029 
15030 #define DMA_CH_MUX_SRC_MASK                      (0x7FU)
15031 #define DMA_CH_MUX_SRC_SHIFT                     (0U)
15032 /*! SRC - Service Request Source */
15033 #define DMA_CH_MUX_SRC(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_MUX_SRC_SHIFT)) & DMA_CH_MUX_SRC_MASK)
15034 /*! @} */
15035 
15036 /* The count of DMA_CH_MUX */
15037 #define DMA_CH_MUX_COUNT                         (16U)
15038 
15039 /*! @name TCD_SADDR - TCD Source Address */
15040 /*! @{ */
15041 
15042 #define DMA_TCD_SADDR_SADDR_MASK                 (0xFFFFFFFFU)
15043 #define DMA_TCD_SADDR_SADDR_SHIFT                (0U)
15044 /*! SADDR - Source Address */
15045 #define DMA_TCD_SADDR_SADDR(x)                   (((uint32_t)(((uint32_t)(x)) << DMA_TCD_SADDR_SADDR_SHIFT)) & DMA_TCD_SADDR_SADDR_MASK)
15046 /*! @} */
15047 
15048 /* The count of DMA_TCD_SADDR */
15049 #define DMA_TCD_SADDR_COUNT                      (16U)
15050 
15051 /*! @name TCD_SOFF - TCD Signed Source Address Offset */
15052 /*! @{ */
15053 
15054 #define DMA_TCD_SOFF_SOFF_MASK                   (0xFFFFU)
15055 #define DMA_TCD_SOFF_SOFF_SHIFT                  (0U)
15056 /*! SOFF - Source Address Signed Offset */
15057 #define DMA_TCD_SOFF_SOFF(x)                     (((uint16_t)(((uint16_t)(x)) << DMA_TCD_SOFF_SOFF_SHIFT)) & DMA_TCD_SOFF_SOFF_MASK)
15058 /*! @} */
15059 
15060 /* The count of DMA_TCD_SOFF */
15061 #define DMA_TCD_SOFF_COUNT                       (16U)
15062 
15063 /*! @name TCD_ATTR - TCD Transfer Attributes */
15064 /*! @{ */
15065 
15066 #define DMA_TCD_ATTR_DSIZE_MASK                  (0x7U)
15067 #define DMA_TCD_ATTR_DSIZE_SHIFT                 (0U)
15068 /*! DSIZE - Destination Data Transfer Size */
15069 #define DMA_TCD_ATTR_DSIZE(x)                    (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_DSIZE_SHIFT)) & DMA_TCD_ATTR_DSIZE_MASK)
15070 
15071 #define DMA_TCD_ATTR_DMOD_MASK                   (0xF8U)
15072 #define DMA_TCD_ATTR_DMOD_SHIFT                  (3U)
15073 /*! DMOD - Destination Address Modulo */
15074 #define DMA_TCD_ATTR_DMOD(x)                     (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_DMOD_SHIFT)) & DMA_TCD_ATTR_DMOD_MASK)
15075 
15076 #define DMA_TCD_ATTR_SSIZE_MASK                  (0x700U)
15077 #define DMA_TCD_ATTR_SSIZE_SHIFT                 (8U)
15078 /*! SSIZE - Source Data Transfer Size
15079  *  0b000..8-bit
15080  *  0b001..16-bit
15081  *  0b010..32-bit
15082  *  0b011..64-bit
15083  *  0b100..16-byte
15084  *  0b101..32-byte
15085  *  0b110..
15086  *  0b111..
15087  */
15088 #define DMA_TCD_ATTR_SSIZE(x)                    (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_SSIZE_SHIFT)) & DMA_TCD_ATTR_SSIZE_MASK)
15089 
15090 #define DMA_TCD_ATTR_SMOD_MASK                   (0xF800U)
15091 #define DMA_TCD_ATTR_SMOD_SHIFT                  (11U)
15092 /*! SMOD - Source Address Modulo
15093  *  0b00000..Source address modulo feature disabled
15094  *  0b00001..Source address modulo feature enabled for any non-zero value [1-31]
15095  */
15096 #define DMA_TCD_ATTR_SMOD(x)                     (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_SMOD_SHIFT)) & DMA_TCD_ATTR_SMOD_MASK)
15097 /*! @} */
15098 
15099 /* The count of DMA_TCD_ATTR */
15100 #define DMA_TCD_ATTR_COUNT                       (16U)
15101 
15102 /*! @name TCD_NBYTES_MLOFFNO - TCD Transfer Size Without Minor Loop Offsets */
15103 /*! @{ */
15104 
15105 #define DMA_TCD_NBYTES_MLOFFNO_NBYTES_MASK       (0x3FFFFFFFU)
15106 #define DMA_TCD_NBYTES_MLOFFNO_NBYTES_SHIFT      (0U)
15107 /*! NBYTES - Number of Bytes To Transfer Per Service Request */
15108 #define DMA_TCD_NBYTES_MLOFFNO_NBYTES(x)         (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_TCD_NBYTES_MLOFFNO_NBYTES_MASK)
15109 
15110 #define DMA_TCD_NBYTES_MLOFFNO_DMLOE_MASK        (0x40000000U)
15111 #define DMA_TCD_NBYTES_MLOFFNO_DMLOE_SHIFT       (30U)
15112 /*! DMLOE - Destination Minor Loop Offset Enable
15113  *  0b0..Minor loop offset not applied to DADDR
15114  *  0b1..Minor loop offset applied to DADDR
15115  */
15116 #define DMA_TCD_NBYTES_MLOFFNO_DMLOE(x)          (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFNO_DMLOE_MASK)
15117 
15118 #define DMA_TCD_NBYTES_MLOFFNO_SMLOE_MASK        (0x80000000U)
15119 #define DMA_TCD_NBYTES_MLOFFNO_SMLOE_SHIFT       (31U)
15120 /*! SMLOE - Source Minor Loop Offset Enable
15121  *  0b0..Minor loop offset not applied to SADDR
15122  *  0b1..Minor loop offset applied to SADDR
15123  */
15124 #define DMA_TCD_NBYTES_MLOFFNO_SMLOE(x)          (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFNO_SMLOE_MASK)
15125 /*! @} */
15126 
15127 /* The count of DMA_TCD_NBYTES_MLOFFNO */
15128 #define DMA_TCD_NBYTES_MLOFFNO_COUNT             (16U)
15129 
15130 /*! @name TCD_NBYTES_MLOFFYES - TCD Transfer Size with Minor Loop Offsets */
15131 /*! @{ */
15132 
15133 #define DMA_TCD_NBYTES_MLOFFYES_NBYTES_MASK      (0x3FFU)
15134 #define DMA_TCD_NBYTES_MLOFFYES_NBYTES_SHIFT     (0U)
15135 /*! NBYTES - Number of Bytes To Transfer Per Service Request */
15136 #define DMA_TCD_NBYTES_MLOFFYES_NBYTES(x)        (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_NBYTES_MASK)
15137 
15138 #define DMA_TCD_NBYTES_MLOFFYES_MLOFF_MASK       (0x3FFFFC00U)
15139 #define DMA_TCD_NBYTES_MLOFFYES_MLOFF_SHIFT      (10U)
15140 /*! MLOFF - Minor Loop Offset */
15141 #define DMA_TCD_NBYTES_MLOFFYES_MLOFF(x)         (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_MLOFF_MASK)
15142 
15143 #define DMA_TCD_NBYTES_MLOFFYES_DMLOE_MASK       (0x40000000U)
15144 #define DMA_TCD_NBYTES_MLOFFYES_DMLOE_SHIFT      (30U)
15145 /*! DMLOE - Destination Minor Loop Offset Enable
15146  *  0b0..Minor loop offset not applied to DADDR
15147  *  0b1..Minor loop offset applied to DADDR
15148  */
15149 #define DMA_TCD_NBYTES_MLOFFYES_DMLOE(x)         (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_DMLOE_MASK)
15150 
15151 #define DMA_TCD_NBYTES_MLOFFYES_SMLOE_MASK       (0x80000000U)
15152 #define DMA_TCD_NBYTES_MLOFFYES_SMLOE_SHIFT      (31U)
15153 /*! SMLOE - Source Minor Loop Offset Enable
15154  *  0b0..Minor loop offset not applied to SADDR
15155  *  0b1..Minor loop offset applied to SADDR
15156  */
15157 #define DMA_TCD_NBYTES_MLOFFYES_SMLOE(x)         (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_SMLOE_MASK)
15158 /*! @} */
15159 
15160 /* The count of DMA_TCD_NBYTES_MLOFFYES */
15161 #define DMA_TCD_NBYTES_MLOFFYES_COUNT            (16U)
15162 
15163 /*! @name TCD_SLAST_SDA - TCD Last Source Address Adjustment / Store DADDR Address */
15164 /*! @{ */
15165 
15166 #define DMA_TCD_SLAST_SDA_SLAST_SDA_MASK         (0xFFFFFFFFU)
15167 #define DMA_TCD_SLAST_SDA_SLAST_SDA_SHIFT        (0U)
15168 /*! SLAST_SDA - Last Source Address Adjustment / Store DADDR Address */
15169 #define DMA_TCD_SLAST_SDA_SLAST_SDA(x)           (((uint32_t)(((uint32_t)(x)) << DMA_TCD_SLAST_SDA_SLAST_SDA_SHIFT)) & DMA_TCD_SLAST_SDA_SLAST_SDA_MASK)
15170 /*! @} */
15171 
15172 /* The count of DMA_TCD_SLAST_SDA */
15173 #define DMA_TCD_SLAST_SDA_COUNT                  (16U)
15174 
15175 /*! @name TCD_DADDR - TCD Destination Address */
15176 /*! @{ */
15177 
15178 #define DMA_TCD_DADDR_DADDR_MASK                 (0xFFFFFFFFU)
15179 #define DMA_TCD_DADDR_DADDR_SHIFT                (0U)
15180 /*! DADDR - Destination Address */
15181 #define DMA_TCD_DADDR_DADDR(x)                   (((uint32_t)(((uint32_t)(x)) << DMA_TCD_DADDR_DADDR_SHIFT)) & DMA_TCD_DADDR_DADDR_MASK)
15182 /*! @} */
15183 
15184 /* The count of DMA_TCD_DADDR */
15185 #define DMA_TCD_DADDR_COUNT                      (16U)
15186 
15187 /*! @name TCD_DOFF - TCD Signed Destination Address Offset */
15188 /*! @{ */
15189 
15190 #define DMA_TCD_DOFF_DOFF_MASK                   (0xFFFFU)
15191 #define DMA_TCD_DOFF_DOFF_SHIFT                  (0U)
15192 /*! DOFF - Destination Address Signed Offset */
15193 #define DMA_TCD_DOFF_DOFF(x)                     (((uint16_t)(((uint16_t)(x)) << DMA_TCD_DOFF_DOFF_SHIFT)) & DMA_TCD_DOFF_DOFF_MASK)
15194 /*! @} */
15195 
15196 /* The count of DMA_TCD_DOFF */
15197 #define DMA_TCD_DOFF_COUNT                       (16U)
15198 
15199 /*! @name TCD_CITER_ELINKNO - TCD Current Major Loop Count (Minor Loop Channel Linking Disabled) */
15200 /*! @{ */
15201 
15202 #define DMA_TCD_CITER_ELINKNO_CITER_MASK         (0x7FFFU)
15203 #define DMA_TCD_CITER_ELINKNO_CITER_SHIFT        (0U)
15204 /*! CITER - Current Major Iteration Count */
15205 #define DMA_TCD_CITER_ELINKNO_CITER(x)           (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKNO_CITER_SHIFT)) & DMA_TCD_CITER_ELINKNO_CITER_MASK)
15206 
15207 #define DMA_TCD_CITER_ELINKNO_ELINK_MASK         (0x8000U)
15208 #define DMA_TCD_CITER_ELINKNO_ELINK_SHIFT        (15U)
15209 /*! ELINK - Enable Link
15210  *  0b0..Channel-to-channel linking disabled
15211  *  0b1..Channel-to-channel linking enabled
15212  */
15213 #define DMA_TCD_CITER_ELINKNO_ELINK(x)           (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_CITER_ELINKNO_ELINK_MASK)
15214 /*! @} */
15215 
15216 /* The count of DMA_TCD_CITER_ELINKNO */
15217 #define DMA_TCD_CITER_ELINKNO_COUNT              (16U)
15218 
15219 /*! @name TCD_CITER_ELINKYES - TCD Current Major Loop Count (Minor Loop Channel Linking Enabled) */
15220 /*! @{ */
15221 
15222 #define DMA_TCD_CITER_ELINKYES_CITER_MASK        (0x1FFU)
15223 #define DMA_TCD_CITER_ELINKYES_CITER_SHIFT       (0U)
15224 /*! CITER - Current Major Iteration Count */
15225 #define DMA_TCD_CITER_ELINKYES_CITER(x)          (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKYES_CITER_SHIFT)) & DMA_TCD_CITER_ELINKYES_CITER_MASK)
15226 
15227 #define DMA_TCD_CITER_ELINKYES_LINKCH_MASK       (0x1E00U)
15228 #define DMA_TCD_CITER_ELINKYES_LINKCH_SHIFT      (9U)
15229 /*! LINKCH - Minor Loop Link Channel Number */
15230 #define DMA_TCD_CITER_ELINKYES_LINKCH(x)         (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_CITER_ELINKYES_LINKCH_MASK)
15231 
15232 #define DMA_TCD_CITER_ELINKYES_ELINK_MASK        (0x8000U)
15233 #define DMA_TCD_CITER_ELINKYES_ELINK_SHIFT       (15U)
15234 /*! ELINK - Enable Link
15235  *  0b0..Channel-to-channel linking disabled
15236  *  0b1..Channel-to-channel linking enabled
15237  */
15238 #define DMA_TCD_CITER_ELINKYES_ELINK(x)          (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_CITER_ELINKYES_ELINK_MASK)
15239 /*! @} */
15240 
15241 /* The count of DMA_TCD_CITER_ELINKYES */
15242 #define DMA_TCD_CITER_ELINKYES_COUNT             (16U)
15243 
15244 /*! @name TCD_DLAST_SGA - TCD Last Destination Address Adjustment / Scatter Gather Address */
15245 /*! @{ */
15246 
15247 #define DMA_TCD_DLAST_SGA_DLAST_SGA_MASK         (0xFFFFFFFFU)
15248 #define DMA_TCD_DLAST_SGA_DLAST_SGA_SHIFT        (0U)
15249 /*! DLAST_SGA - Last Destination Address Adjustment / Scatter Gather Address */
15250 #define DMA_TCD_DLAST_SGA_DLAST_SGA(x)           (((uint32_t)(((uint32_t)(x)) << DMA_TCD_DLAST_SGA_DLAST_SGA_SHIFT)) & DMA_TCD_DLAST_SGA_DLAST_SGA_MASK)
15251 /*! @} */
15252 
15253 /* The count of DMA_TCD_DLAST_SGA */
15254 #define DMA_TCD_DLAST_SGA_COUNT                  (16U)
15255 
15256 /*! @name TCD_CSR - TCD Control and Status */
15257 /*! @{ */
15258 
15259 #define DMA_TCD_CSR_START_MASK                   (0x1U)
15260 #define DMA_TCD_CSR_START_SHIFT                  (0U)
15261 /*! START - Channel Start
15262  *  0b0..Channel not explicitly started
15263  *  0b1..Channel explicitly started via a software-initiated service request
15264  */
15265 #define DMA_TCD_CSR_START(x)                     (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_START_SHIFT)) & DMA_TCD_CSR_START_MASK)
15266 
15267 #define DMA_TCD_CSR_INTMAJOR_MASK                (0x2U)
15268 #define DMA_TCD_CSR_INTMAJOR_SHIFT               (1U)
15269 /*! INTMAJOR - Enable Interrupt If Major count complete
15270  *  0b0..End-of-major loop interrupt disabled
15271  *  0b1..End-of-major loop interrupt enabled
15272  */
15273 #define DMA_TCD_CSR_INTMAJOR(x)                  (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_INTMAJOR_SHIFT)) & DMA_TCD_CSR_INTMAJOR_MASK)
15274 
15275 #define DMA_TCD_CSR_INTHALF_MASK                 (0x4U)
15276 #define DMA_TCD_CSR_INTHALF_SHIFT                (2U)
15277 /*! INTHALF - Enable Interrupt If Major Counter Half-complete
15278  *  0b0..Halfway point interrupt disabled
15279  *  0b1..Halfway point interrupt enabled
15280  */
15281 #define DMA_TCD_CSR_INTHALF(x)                   (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_INTHALF_SHIFT)) & DMA_TCD_CSR_INTHALF_MASK)
15282 
15283 #define DMA_TCD_CSR_DREQ_MASK                    (0x8U)
15284 #define DMA_TCD_CSR_DREQ_SHIFT                   (3U)
15285 /*! DREQ - Disable Request
15286  *  0b0..No operation
15287  *  0b1..Clear the ERQ field to 0 upon major loop completion, thus disabling hardware service requests
15288  */
15289 #define DMA_TCD_CSR_DREQ(x)                      (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_DREQ_SHIFT)) & DMA_TCD_CSR_DREQ_MASK)
15290 
15291 #define DMA_TCD_CSR_ESG_MASK                     (0x10U)
15292 #define DMA_TCD_CSR_ESG_SHIFT                    (4U)
15293 /*! ESG - Enable Scatter/Gather Processing
15294  *  0b0..Current channel's TCD is normal format
15295  *  0b1..Current channel's TCD specifies scatter/gather format.
15296  */
15297 #define DMA_TCD_CSR_ESG(x)                       (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_ESG_SHIFT)) & DMA_TCD_CSR_ESG_MASK)
15298 
15299 #define DMA_TCD_CSR_MAJORELINK_MASK              (0x20U)
15300 #define DMA_TCD_CSR_MAJORELINK_SHIFT             (5U)
15301 /*! MAJORELINK - Enable Link When Major Loop Complete
15302  *  0b0..Channel-to-channel linking disabled
15303  *  0b1..Channel-to-channel linking enabled
15304  */
15305 #define DMA_TCD_CSR_MAJORELINK(x)                (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_MAJORELINK_SHIFT)) & DMA_TCD_CSR_MAJORELINK_MASK)
15306 
15307 #define DMA_TCD_CSR_EEOP_MASK                    (0x40U)
15308 #define DMA_TCD_CSR_EEOP_SHIFT                   (6U)
15309 /*! EEOP - Enable End-Of-Packet Processing
15310  *  0b0..End-of-packet operation disabled
15311  *  0b1..End-of-packet hardware input signal enabled
15312  */
15313 #define DMA_TCD_CSR_EEOP(x)                      (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_EEOP_SHIFT)) & DMA_TCD_CSR_EEOP_MASK)
15314 
15315 #define DMA_TCD_CSR_ESDA_MASK                    (0x80U)
15316 #define DMA_TCD_CSR_ESDA_SHIFT                   (7U)
15317 /*! ESDA - Enable Store Destination Address
15318  *  0b0..Ability to store destination address to system memory disabled
15319  *  0b1..Ability to store destination address to system memory enabled
15320  */
15321 #define DMA_TCD_CSR_ESDA(x)                      (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_ESDA_SHIFT)) & DMA_TCD_CSR_ESDA_MASK)
15322 
15323 #define DMA_TCD_CSR_MAJORLINKCH_MASK             (0xF00U)
15324 #define DMA_TCD_CSR_MAJORLINKCH_SHIFT            (8U)
15325 /*! MAJORLINKCH - Major Loop Link Channel Number */
15326 #define DMA_TCD_CSR_MAJORLINKCH(x)               (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_MAJORLINKCH_SHIFT)) & DMA_TCD_CSR_MAJORLINKCH_MASK)
15327 
15328 #define DMA_TCD_CSR_BWC_MASK                     (0xC000U)
15329 #define DMA_TCD_CSR_BWC_SHIFT                    (14U)
15330 /*! BWC - Bandwidth Control
15331  *  0b00..No eDMA engine stalls
15332  *  0b01..
15333  *  0b10..eDMA engine stalls for 4 cycles after each R/W
15334  *  0b11..eDMA engine stalls for 8 cycles after each R/W
15335  */
15336 #define DMA_TCD_CSR_BWC(x)                       (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_BWC_SHIFT)) & DMA_TCD_CSR_BWC_MASK)
15337 /*! @} */
15338 
15339 /* The count of DMA_TCD_CSR */
15340 #define DMA_TCD_CSR_COUNT                        (16U)
15341 
15342 /*! @name TCD_BITER_ELINKNO - TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled) */
15343 /*! @{ */
15344 
15345 #define DMA_TCD_BITER_ELINKNO_BITER_MASK         (0x7FFFU)
15346 #define DMA_TCD_BITER_ELINKNO_BITER_SHIFT        (0U)
15347 /*! BITER - Starting Major Iteration Count */
15348 #define DMA_TCD_BITER_ELINKNO_BITER(x)           (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKNO_BITER_SHIFT)) & DMA_TCD_BITER_ELINKNO_BITER_MASK)
15349 
15350 #define DMA_TCD_BITER_ELINKNO_ELINK_MASK         (0x8000U)
15351 #define DMA_TCD_BITER_ELINKNO_ELINK_SHIFT        (15U)
15352 /*! ELINK - Enables Link
15353  *  0b0..Channel-to-channel linking disabled
15354  *  0b1..Channel-to-channel linking enabled
15355  */
15356 #define DMA_TCD_BITER_ELINKNO_ELINK(x)           (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_BITER_ELINKNO_ELINK_MASK)
15357 /*! @} */
15358 
15359 /* The count of DMA_TCD_BITER_ELINKNO */
15360 #define DMA_TCD_BITER_ELINKNO_COUNT              (16U)
15361 
15362 /*! @name TCD_BITER_ELINKYES - TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled) */
15363 /*! @{ */
15364 
15365 #define DMA_TCD_BITER_ELINKYES_BITER_MASK        (0x1FFU)
15366 #define DMA_TCD_BITER_ELINKYES_BITER_SHIFT       (0U)
15367 /*! BITER - Starting Major Iteration Count */
15368 #define DMA_TCD_BITER_ELINKYES_BITER(x)          (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKYES_BITER_SHIFT)) & DMA_TCD_BITER_ELINKYES_BITER_MASK)
15369 
15370 #define DMA_TCD_BITER_ELINKYES_LINKCH_MASK       (0x1E00U)
15371 #define DMA_TCD_BITER_ELINKYES_LINKCH_SHIFT      (9U)
15372 /*! LINKCH - Link Channel Number */
15373 #define DMA_TCD_BITER_ELINKYES_LINKCH(x)         (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_BITER_ELINKYES_LINKCH_MASK)
15374 
15375 #define DMA_TCD_BITER_ELINKYES_ELINK_MASK        (0x8000U)
15376 #define DMA_TCD_BITER_ELINKYES_ELINK_SHIFT       (15U)
15377 /*! ELINK - Enable Link
15378  *  0b0..Channel-to-channel linking disabled
15379  *  0b1..Channel-to-channel linking enabled
15380  */
15381 #define DMA_TCD_BITER_ELINKYES_ELINK(x)          (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_BITER_ELINKYES_ELINK_MASK)
15382 /*! @} */
15383 
15384 /* The count of DMA_TCD_BITER_ELINKYES */
15385 #define DMA_TCD_BITER_ELINKYES_COUNT             (16U)
15386 
15387 
15388 /*!
15389  * @}
15390  */ /* end of group DMA_Register_Masks */
15391 
15392 
15393 /* DMA - Peripheral instance base addresses */
15394 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
15395   /** Peripheral DMA0 base address */
15396   #define DMA0_BASE                                (0x50080000u)
15397   /** Peripheral DMA0 base address */
15398   #define DMA0_BASE_NS                             (0x40080000u)
15399   /** Peripheral DMA0 base pointer */
15400   #define DMA0                                     ((DMA_Type *)DMA0_BASE)
15401   /** Peripheral DMA0 base pointer */
15402   #define DMA0_NS                                  ((DMA_Type *)DMA0_BASE_NS)
15403   /** Peripheral DMA1 base address */
15404   #define DMA1_BASE                                (0x500A0000u)
15405   /** Peripheral DMA1 base address */
15406   #define DMA1_BASE_NS                             (0x400A0000u)
15407   /** Peripheral DMA1 base pointer */
15408   #define DMA1                                     ((DMA_Type *)DMA1_BASE)
15409   /** Peripheral DMA1 base pointer */
15410   #define DMA1_NS                                  ((DMA_Type *)DMA1_BASE_NS)
15411   /** Array initializer of DMA peripheral base addresses */
15412   #define DMA_BASE_ADDRS                           { DMA0_BASE, DMA1_BASE }
15413   /** Array initializer of DMA peripheral base pointers */
15414   #define DMA_BASE_PTRS                            { DMA0, DMA1 }
15415   /** Array initializer of DMA peripheral base addresses */
15416   #define DMA_BASE_ADDRS_NS                        { DMA0_BASE_NS, DMA1_BASE_NS }
15417   /** Array initializer of DMA peripheral base pointers */
15418   #define DMA_BASE_PTRS_NS                         { DMA0_NS, DMA1_NS }
15419 #else
15420   /** Peripheral DMA0 base address */
15421   #define DMA0_BASE                                (0x40080000u)
15422   /** Peripheral DMA0 base pointer */
15423   #define DMA0                                     ((DMA_Type *)DMA0_BASE)
15424   /** Peripheral DMA1 base address */
15425   #define DMA1_BASE                                (0x400A0000u)
15426   /** Peripheral DMA1 base pointer */
15427   #define DMA1                                     ((DMA_Type *)DMA1_BASE)
15428   /** Array initializer of DMA peripheral base addresses */
15429   #define DMA_BASE_ADDRS                           { DMA0_BASE, DMA1_BASE }
15430   /** Array initializer of DMA peripheral base pointers */
15431   #define DMA_BASE_PTRS                            { DMA0, DMA1 }
15432 #endif
15433 /** Interrupt vectors for the DMA peripheral type */
15434 #define DMA_IRQS                                 { { EDMA_0_CH0_IRQn, EDMA_0_CH1_IRQn, EDMA_0_CH2_IRQn, EDMA_0_CH3_IRQn, EDMA_0_CH4_IRQn, EDMA_0_CH5_IRQn, EDMA_0_CH6_IRQn, EDMA_0_CH7_IRQn, EDMA_0_CH8_IRQn, EDMA_0_CH9_IRQn, EDMA_0_CH10_IRQn, EDMA_0_CH11_IRQn, EDMA_0_CH12_IRQn, EDMA_0_CH13_IRQn, EDMA_0_CH14_IRQn, EDMA_0_CH15_IRQn }, \
15435                                                    { EDMA_1_CH0_IRQn, EDMA_1_CH1_IRQn, EDMA_1_CH2_IRQn, EDMA_1_CH3_IRQn, EDMA_1_CH4_IRQn, EDMA_1_CH5_IRQn, EDMA_1_CH6_IRQn, EDMA_1_CH7_IRQn, EDMA_1_CH8_IRQn, EDMA_1_CH9_IRQn, EDMA_1_CH10_IRQn, EDMA_1_CH11_IRQn, EDMA_1_CH12_IRQn, EDMA_1_CH13_IRQn, EDMA_1_CH14_IRQn, EDMA_1_CH15_IRQn } }
15436 
15437 /*!
15438  * @}
15439  */ /* end of group DMA_Peripheral_Access_Layer */
15440 
15441 
15442 /* ----------------------------------------------------------------------------
15443    -- EIM Peripheral Access Layer
15444    ---------------------------------------------------------------------------- */
15445 
15446 /*!
15447  * @addtogroup EIM_Peripheral_Access_Layer EIM Peripheral Access Layer
15448  * @{
15449  */
15450 
15451 /** EIM - Register Layout Typedef */
15452 typedef struct {
15453   __IO uint32_t EIMCR;                             /**< Error Injection Module Configuration Register, offset: 0x0 */
15454   __IO uint32_t EICHEN;                            /**< Error Injection Channel Enable register, offset: 0x4 */
15455        uint8_t RESERVED_0[248];
15456   __IO uint32_t EICHD0_WORD0;                      /**< Error Injection Channel Descriptor 0, Word0, offset: 0x100 */
15457   __IO uint32_t EICHD0_WORD1;                      /**< Error Injection Channel Descriptor 0, Word1, offset: 0x104 */
15458        uint8_t RESERVED_1[56];
15459   __IO uint32_t EICHD1_WORD0;                      /**< Error Injection Channel Descriptor 1, Word0, offset: 0x140 */
15460   __IO uint32_t EICHD1_WORD1;                      /**< Error Injection Channel Descriptor 1, Word1, offset: 0x144 */
15461        uint8_t RESERVED_2[56];
15462   __IO uint32_t EICHD2_WORD0;                      /**< Error Injection Channel Descriptor 2, Word0, offset: 0x180 */
15463   __IO uint32_t EICHD2_WORD1;                      /**< Error Injection Channel Descriptor 2, Word1, offset: 0x184 */
15464        uint8_t RESERVED_3[56];
15465   __IO uint32_t EICHD3_WORD0;                      /**< Error Injection Channel Descriptor 3, Word0, offset: 0x1C0 */
15466   __IO uint32_t EICHD3_WORD1;                      /**< Error Injection Channel Descriptor 3, Word1, offset: 0x1C4 */
15467        uint8_t RESERVED_4[56];
15468   __IO uint32_t EICHD4_WORD0;                      /**< Error Injection Channel Descriptor 4, Word0, offset: 0x200 */
15469   __IO uint32_t EICHD4_WORD1;                      /**< Error Injection Channel Descriptor 4, Word1, offset: 0x204 */
15470        uint8_t RESERVED_5[56];
15471   __IO uint32_t EICHD5_WORD0;                      /**< Error Injection Channel Descriptor 5, Word0, offset: 0x240 */
15472   __IO uint32_t EICHD5_WORD1;                      /**< Error Injection Channel Descriptor 5, Word1, offset: 0x244 */
15473        uint8_t RESERVED_6[56];
15474   __IO uint32_t EICHD6_WORD0;                      /**< Error Injection Channel Descriptor 6, Word0, offset: 0x280 */
15475   __IO uint32_t EICHD6_WORD1;                      /**< Error Injection Channel Descriptor 6, Word1, offset: 0x284 */
15476        uint8_t RESERVED_7[56];
15477   __IO uint32_t EICHD7_WORD0;                      /**< Error Injection Channel Descriptor 7, Word0, offset: 0x2C0 */
15478   __IO uint32_t EICHD7_WORD1;                      /**< Error Injection Channel Descriptor 7, Word1, offset: 0x2C4 */
15479        uint8_t RESERVED_8[56];
15480   __IO uint32_t EICHD8_WORD0;                      /**< Error Injection Channel Descriptor 8, Word0, offset: 0x300 */
15481   __IO uint32_t EICHD8_WORD1;                      /**< Error Injection Channel Descriptor 8, Word1, offset: 0x304 */
15482 } EIM_Type;
15483 
15484 /* ----------------------------------------------------------------------------
15485    -- EIM Register Masks
15486    ---------------------------------------------------------------------------- */
15487 
15488 /*!
15489  * @addtogroup EIM_Register_Masks EIM Register Masks
15490  * @{
15491  */
15492 
15493 /*! @name EIMCR - Error Injection Module Configuration Register */
15494 /*! @{ */
15495 
15496 #define EIM_EIMCR_GEIEN_MASK                     (0x1U)
15497 #define EIM_EIMCR_GEIEN_SHIFT                    (0U)
15498 /*! GEIEN - Global Error Injection Enable
15499  *  0b0..Disabled
15500  *  0b1..Enabled
15501  */
15502 #define EIM_EIMCR_GEIEN(x)                       (((uint32_t)(((uint32_t)(x)) << EIM_EIMCR_GEIEN_SHIFT)) & EIM_EIMCR_GEIEN_MASK)
15503 /*! @} */
15504 
15505 /*! @name EICHEN - Error Injection Channel Enable register */
15506 /*! @{ */
15507 
15508 #define EIM_EICHEN_EICH8EN_MASK                  (0x800000U)
15509 #define EIM_EICHEN_EICH8EN_SHIFT                 (23U)
15510 /*! EICH8EN - Error Injection Channel 8 Enable
15511  *  0b0..Error injection is disabled on Error Injection Channel 8
15512  *  0b1..Error injection is enabled on Error Injection Channel 8
15513  */
15514 #define EIM_EICHEN_EICH8EN(x)                    (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH8EN_SHIFT)) & EIM_EICHEN_EICH8EN_MASK)
15515 
15516 #define EIM_EICHEN_EICH7EN_MASK                  (0x1000000U)
15517 #define EIM_EICHEN_EICH7EN_SHIFT                 (24U)
15518 /*! EICH7EN - Error Injection Channel 7 Enable
15519  *  0b0..Error injection is disabled on Error Injection Channel 7
15520  *  0b1..Error injection is enabled on Error Injection Channel 7
15521  */
15522 #define EIM_EICHEN_EICH7EN(x)                    (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH7EN_SHIFT)) & EIM_EICHEN_EICH7EN_MASK)
15523 
15524 #define EIM_EICHEN_EICH6EN_MASK                  (0x2000000U)
15525 #define EIM_EICHEN_EICH6EN_SHIFT                 (25U)
15526 /*! EICH6EN - Error Injection Channel 6 Enable
15527  *  0b0..Error injection is disabled on Error Injection Channel 6
15528  *  0b1..Error injection is enabled on Error Injection Channel 6
15529  */
15530 #define EIM_EICHEN_EICH6EN(x)                    (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH6EN_SHIFT)) & EIM_EICHEN_EICH6EN_MASK)
15531 
15532 #define EIM_EICHEN_EICH5EN_MASK                  (0x4000000U)
15533 #define EIM_EICHEN_EICH5EN_SHIFT                 (26U)
15534 /*! EICH5EN - Error Injection Channel 5 Enable
15535  *  0b0..Error injection is disabled on Error Injection Channel 5
15536  *  0b1..Error injection is enabled on Error Injection Channel 5
15537  */
15538 #define EIM_EICHEN_EICH5EN(x)                    (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH5EN_SHIFT)) & EIM_EICHEN_EICH5EN_MASK)
15539 
15540 #define EIM_EICHEN_EICH4EN_MASK                  (0x8000000U)
15541 #define EIM_EICHEN_EICH4EN_SHIFT                 (27U)
15542 /*! EICH4EN - Error Injection Channel 4 Enable
15543  *  0b0..Error injection is disabled on Error Injection Channel 4
15544  *  0b1..Error injection is enabled on Error Injection Channel 4
15545  */
15546 #define EIM_EICHEN_EICH4EN(x)                    (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH4EN_SHIFT)) & EIM_EICHEN_EICH4EN_MASK)
15547 
15548 #define EIM_EICHEN_EICH3EN_MASK                  (0x10000000U)
15549 #define EIM_EICHEN_EICH3EN_SHIFT                 (28U)
15550 /*! EICH3EN - Error Injection Channel 3 Enable
15551  *  0b0..Error injection is disabled on Error Injection Channel 3
15552  *  0b1..Error injection is enabled on Error Injection Channel 3
15553  */
15554 #define EIM_EICHEN_EICH3EN(x)                    (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH3EN_SHIFT)) & EIM_EICHEN_EICH3EN_MASK)
15555 
15556 #define EIM_EICHEN_EICH2EN_MASK                  (0x20000000U)
15557 #define EIM_EICHEN_EICH2EN_SHIFT                 (29U)
15558 /*! EICH2EN - Error Injection Channel 2 Enable
15559  *  0b0..Error injection is disabled on Error Injection Channel 2
15560  *  0b1..Error injection is enabled on Error Injection Channel 2
15561  */
15562 #define EIM_EICHEN_EICH2EN(x)                    (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH2EN_SHIFT)) & EIM_EICHEN_EICH2EN_MASK)
15563 
15564 #define EIM_EICHEN_EICH1EN_MASK                  (0x40000000U)
15565 #define EIM_EICHEN_EICH1EN_SHIFT                 (30U)
15566 /*! EICH1EN - Error Injection Channel 1 Enable
15567  *  0b0..Error injection is disabled on Error Injection Channel 1
15568  *  0b1..Error injection is enabled on Error Injection Channel 1
15569  */
15570 #define EIM_EICHEN_EICH1EN(x)                    (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH1EN_SHIFT)) & EIM_EICHEN_EICH1EN_MASK)
15571 
15572 #define EIM_EICHEN_EICH0EN_MASK                  (0x80000000U)
15573 #define EIM_EICHEN_EICH0EN_SHIFT                 (31U)
15574 /*! EICH0EN - Error Injection Channel 0 Enable
15575  *  0b0..Error injection is disabled on Error Injection Channel 0
15576  *  0b1..Error injection is enabled on Error Injection Channel 0
15577  */
15578 #define EIM_EICHEN_EICH0EN(x)                    (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH0EN_SHIFT)) & EIM_EICHEN_EICH0EN_MASK)
15579 /*! @} */
15580 
15581 /*! @name EICHD0_WORD0 - Error Injection Channel Descriptor 0, Word0 */
15582 /*! @{ */
15583 
15584 #define EIM_EICHD0_WORD0_CHKBIT_MASK_MASK        (0xFE000000U)
15585 #define EIM_EICHD0_WORD0_CHKBIT_MASK_SHIFT       (25U)
15586 /*! CHKBIT_MASK - Checkbit Mask */
15587 #define EIM_EICHD0_WORD0_CHKBIT_MASK(x)          (((uint32_t)(((uint32_t)(x)) << EIM_EICHD0_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD0_WORD0_CHKBIT_MASK_MASK)
15588 /*! @} */
15589 
15590 /*! @name EICHD0_WORD1 - Error Injection Channel Descriptor 0, Word1 */
15591 /*! @{ */
15592 
15593 #define EIM_EICHD0_WORD1_B0_3DATA_MASK_MASK      (0xFFFFFFFFU)
15594 #define EIM_EICHD0_WORD1_B0_3DATA_MASK_SHIFT     (0U)
15595 /*! B0_3DATA_MASK - Data Mask Bytes 0-3 */
15596 #define EIM_EICHD0_WORD1_B0_3DATA_MASK(x)        (((uint32_t)(((uint32_t)(x)) << EIM_EICHD0_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD0_WORD1_B0_3DATA_MASK_MASK)
15597 /*! @} */
15598 
15599 /*! @name EICHD1_WORD0 - Error Injection Channel Descriptor 1, Word0 */
15600 /*! @{ */
15601 
15602 #define EIM_EICHD1_WORD0_CHKBIT_MASK_MASK        (0xFE000000U)
15603 #define EIM_EICHD1_WORD0_CHKBIT_MASK_SHIFT       (25U)
15604 /*! CHKBIT_MASK - Checkbit Mask */
15605 #define EIM_EICHD1_WORD0_CHKBIT_MASK(x)          (((uint32_t)(((uint32_t)(x)) << EIM_EICHD1_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD1_WORD0_CHKBIT_MASK_MASK)
15606 /*! @} */
15607 
15608 /*! @name EICHD1_WORD1 - Error Injection Channel Descriptor 1, Word1 */
15609 /*! @{ */
15610 
15611 #define EIM_EICHD1_WORD1_B0_3DATA_MASK_MASK      (0xFFFFFFFFU)
15612 #define EIM_EICHD1_WORD1_B0_3DATA_MASK_SHIFT     (0U)
15613 /*! B0_3DATA_MASK - Data Mask Bytes 0-3 */
15614 #define EIM_EICHD1_WORD1_B0_3DATA_MASK(x)        (((uint32_t)(((uint32_t)(x)) << EIM_EICHD1_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD1_WORD1_B0_3DATA_MASK_MASK)
15615 /*! @} */
15616 
15617 /*! @name EICHD2_WORD0 - Error Injection Channel Descriptor 2, Word0 */
15618 /*! @{ */
15619 
15620 #define EIM_EICHD2_WORD0_CHKBIT_MASK_MASK        (0xFE000000U)
15621 #define EIM_EICHD2_WORD0_CHKBIT_MASK_SHIFT       (25U)
15622 /*! CHKBIT_MASK - Checkbit Mask */
15623 #define EIM_EICHD2_WORD0_CHKBIT_MASK(x)          (((uint32_t)(((uint32_t)(x)) << EIM_EICHD2_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD2_WORD0_CHKBIT_MASK_MASK)
15624 /*! @} */
15625 
15626 /*! @name EICHD2_WORD1 - Error Injection Channel Descriptor 2, Word1 */
15627 /*! @{ */
15628 
15629 #define EIM_EICHD2_WORD1_B0_3DATA_MASK_MASK      (0xFFFFFFFFU)
15630 #define EIM_EICHD2_WORD1_B0_3DATA_MASK_SHIFT     (0U)
15631 /*! B0_3DATA_MASK - Data Mask Bytes 0-3 */
15632 #define EIM_EICHD2_WORD1_B0_3DATA_MASK(x)        (((uint32_t)(((uint32_t)(x)) << EIM_EICHD2_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD2_WORD1_B0_3DATA_MASK_MASK)
15633 /*! @} */
15634 
15635 /*! @name EICHD3_WORD0 - Error Injection Channel Descriptor 3, Word0 */
15636 /*! @{ */
15637 
15638 #define EIM_EICHD3_WORD0_CHKBIT_MASK_MASK        (0xFE000000U)
15639 #define EIM_EICHD3_WORD0_CHKBIT_MASK_SHIFT       (25U)
15640 /*! CHKBIT_MASK - Checkbit Mask */
15641 #define EIM_EICHD3_WORD0_CHKBIT_MASK(x)          (((uint32_t)(((uint32_t)(x)) << EIM_EICHD3_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD3_WORD0_CHKBIT_MASK_MASK)
15642 /*! @} */
15643 
15644 /*! @name EICHD3_WORD1 - Error Injection Channel Descriptor 3, Word1 */
15645 /*! @{ */
15646 
15647 #define EIM_EICHD3_WORD1_B0_3DATA_MASK_MASK      (0xFFFFFFFFU)
15648 #define EIM_EICHD3_WORD1_B0_3DATA_MASK_SHIFT     (0U)
15649 /*! B0_3DATA_MASK - Data Mask Bytes 0-3 */
15650 #define EIM_EICHD3_WORD1_B0_3DATA_MASK(x)        (((uint32_t)(((uint32_t)(x)) << EIM_EICHD3_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD3_WORD1_B0_3DATA_MASK_MASK)
15651 /*! @} */
15652 
15653 /*! @name EICHD4_WORD0 - Error Injection Channel Descriptor 4, Word0 */
15654 /*! @{ */
15655 
15656 #define EIM_EICHD4_WORD0_CHKBIT_MASK_MASK        (0xFE000000U)
15657 #define EIM_EICHD4_WORD0_CHKBIT_MASK_SHIFT       (25U)
15658 /*! CHKBIT_MASK - Checkbit Mask */
15659 #define EIM_EICHD4_WORD0_CHKBIT_MASK(x)          (((uint32_t)(((uint32_t)(x)) << EIM_EICHD4_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD4_WORD0_CHKBIT_MASK_MASK)
15660 /*! @} */
15661 
15662 /*! @name EICHD4_WORD1 - Error Injection Channel Descriptor 4, Word1 */
15663 /*! @{ */
15664 
15665 #define EIM_EICHD4_WORD1_B0_3DATA_MASK_MASK      (0xFFFFFFFFU)
15666 #define EIM_EICHD4_WORD1_B0_3DATA_MASK_SHIFT     (0U)
15667 /*! B0_3DATA_MASK - Data Mask Bytes 0-3 */
15668 #define EIM_EICHD4_WORD1_B0_3DATA_MASK(x)        (((uint32_t)(((uint32_t)(x)) << EIM_EICHD4_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD4_WORD1_B0_3DATA_MASK_MASK)
15669 /*! @} */
15670 
15671 /*! @name EICHD5_WORD0 - Error Injection Channel Descriptor 5, Word0 */
15672 /*! @{ */
15673 
15674 #define EIM_EICHD5_WORD0_CHKBIT_MASK_MASK        (0xFE000000U)
15675 #define EIM_EICHD5_WORD0_CHKBIT_MASK_SHIFT       (25U)
15676 /*! CHKBIT_MASK - Checkbit Mask */
15677 #define EIM_EICHD5_WORD0_CHKBIT_MASK(x)          (((uint32_t)(((uint32_t)(x)) << EIM_EICHD5_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD5_WORD0_CHKBIT_MASK_MASK)
15678 /*! @} */
15679 
15680 /*! @name EICHD5_WORD1 - Error Injection Channel Descriptor 5, Word1 */
15681 /*! @{ */
15682 
15683 #define EIM_EICHD5_WORD1_B0_3DATA_MASK_MASK      (0xFFFFFFFFU)
15684 #define EIM_EICHD5_WORD1_B0_3DATA_MASK_SHIFT     (0U)
15685 /*! B0_3DATA_MASK - Data Mask Bytes 0-3 */
15686 #define EIM_EICHD5_WORD1_B0_3DATA_MASK(x)        (((uint32_t)(((uint32_t)(x)) << EIM_EICHD5_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD5_WORD1_B0_3DATA_MASK_MASK)
15687 /*! @} */
15688 
15689 /*! @name EICHD6_WORD0 - Error Injection Channel Descriptor 6, Word0 */
15690 /*! @{ */
15691 
15692 #define EIM_EICHD6_WORD0_CHKBIT_MASK_MASK        (0xFE000000U)
15693 #define EIM_EICHD6_WORD0_CHKBIT_MASK_SHIFT       (25U)
15694 /*! CHKBIT_MASK - Checkbit Mask */
15695 #define EIM_EICHD6_WORD0_CHKBIT_MASK(x)          (((uint32_t)(((uint32_t)(x)) << EIM_EICHD6_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD6_WORD0_CHKBIT_MASK_MASK)
15696 /*! @} */
15697 
15698 /*! @name EICHD6_WORD1 - Error Injection Channel Descriptor 6, Word1 */
15699 /*! @{ */
15700 
15701 #define EIM_EICHD6_WORD1_B0_3DATA_MASK_MASK      (0xFFFFFFFFU)
15702 #define EIM_EICHD6_WORD1_B0_3DATA_MASK_SHIFT     (0U)
15703 /*! B0_3DATA_MASK - Data Mask Bytes 0-3 */
15704 #define EIM_EICHD6_WORD1_B0_3DATA_MASK(x)        (((uint32_t)(((uint32_t)(x)) << EIM_EICHD6_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD6_WORD1_B0_3DATA_MASK_MASK)
15705 /*! @} */
15706 
15707 /*! @name EICHD7_WORD0 - Error Injection Channel Descriptor 7, Word0 */
15708 /*! @{ */
15709 
15710 #define EIM_EICHD7_WORD0_CHKBIT_MASK_MASK        (0x80000000U)
15711 #define EIM_EICHD7_WORD0_CHKBIT_MASK_SHIFT       (31U)
15712 /*! CHKBIT_MASK - Checkbit Mask */
15713 #define EIM_EICHD7_WORD0_CHKBIT_MASK(x)          (((uint32_t)(((uint32_t)(x)) << EIM_EICHD7_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD7_WORD0_CHKBIT_MASK_MASK)
15714 /*! @} */
15715 
15716 /*! @name EICHD7_WORD1 - Error Injection Channel Descriptor 7, Word1 */
15717 /*! @{ */
15718 
15719 #define EIM_EICHD7_WORD1_B0_3DATA_MASK_MASK      (0xFFFFFFFFU)
15720 #define EIM_EICHD7_WORD1_B0_3DATA_MASK_SHIFT     (0U)
15721 /*! B0_3DATA_MASK - Data Mask Bytes 0-3 */
15722 #define EIM_EICHD7_WORD1_B0_3DATA_MASK(x)        (((uint32_t)(((uint32_t)(x)) << EIM_EICHD7_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD7_WORD1_B0_3DATA_MASK_MASK)
15723 /*! @} */
15724 
15725 /*! @name EICHD8_WORD0 - Error Injection Channel Descriptor 8, Word0 */
15726 /*! @{ */
15727 
15728 #define EIM_EICHD8_WORD0_CHKBIT_MASK_MASK        (0xF0000000U)
15729 #define EIM_EICHD8_WORD0_CHKBIT_MASK_SHIFT       (28U)
15730 /*! CHKBIT_MASK - Checkbit Mask */
15731 #define EIM_EICHD8_WORD0_CHKBIT_MASK(x)          (((uint32_t)(((uint32_t)(x)) << EIM_EICHD8_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD8_WORD0_CHKBIT_MASK_MASK)
15732 /*! @} */
15733 
15734 /*! @name EICHD8_WORD1 - Error Injection Channel Descriptor 8, Word1 */
15735 /*! @{ */
15736 
15737 #define EIM_EICHD8_WORD1_B0_3DATA_MASK_MASK      (0xFFFFFFFFU)
15738 #define EIM_EICHD8_WORD1_B0_3DATA_MASK_SHIFT     (0U)
15739 /*! B0_3DATA_MASK - Data Mask Bytes 0-3 */
15740 #define EIM_EICHD8_WORD1_B0_3DATA_MASK(x)        (((uint32_t)(((uint32_t)(x)) << EIM_EICHD8_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD8_WORD1_B0_3DATA_MASK_MASK)
15741 /*! @} */
15742 
15743 
15744 /*!
15745  * @}
15746  */ /* end of group EIM_Register_Masks */
15747 
15748 
15749 /* EIM - Peripheral instance base addresses */
15750 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
15751   /** Peripheral EIM0 base address */
15752   #define EIM0_BASE                                (0x5005B000u)
15753   /** Peripheral EIM0 base address */
15754   #define EIM0_BASE_NS                             (0x4005B000u)
15755   /** Peripheral EIM0 base pointer */
15756   #define EIM0                                     ((EIM_Type *)EIM0_BASE)
15757   /** Peripheral EIM0 base pointer */
15758   #define EIM0_NS                                  ((EIM_Type *)EIM0_BASE_NS)
15759   /** Array initializer of EIM peripheral base addresses */
15760   #define EIM_BASE_ADDRS                           { EIM0_BASE }
15761   /** Array initializer of EIM peripheral base pointers */
15762   #define EIM_BASE_PTRS                            { EIM0 }
15763   /** Array initializer of EIM peripheral base addresses */
15764   #define EIM_BASE_ADDRS_NS                        { EIM0_BASE_NS }
15765   /** Array initializer of EIM peripheral base pointers */
15766   #define EIM_BASE_PTRS_NS                         { EIM0_NS }
15767 #else
15768   /** Peripheral EIM0 base address */
15769   #define EIM0_BASE                                (0x4005B000u)
15770   /** Peripheral EIM0 base pointer */
15771   #define EIM0                                     ((EIM_Type *)EIM0_BASE)
15772   /** Array initializer of EIM peripheral base addresses */
15773   #define EIM_BASE_ADDRS                           { EIM0_BASE }
15774   /** Array initializer of EIM peripheral base pointers */
15775   #define EIM_BASE_PTRS                            { EIM0 }
15776 #endif
15777 
15778 /*!
15779  * @}
15780  */ /* end of group EIM_Peripheral_Access_Layer */
15781 
15782 
15783 /* ----------------------------------------------------------------------------
15784    -- EMVSIM Peripheral Access Layer
15785    ---------------------------------------------------------------------------- */
15786 
15787 /*!
15788  * @addtogroup EMVSIM_Peripheral_Access_Layer EMVSIM Peripheral Access Layer
15789  * @{
15790  */
15791 
15792 /** EMVSIM - Register Layout Typedef */
15793 typedef struct {
15794   __I  uint32_t VER_ID;                            /**< Version ID, offset: 0x0 */
15795   __I  uint32_t PARAM;                             /**< Parameters, offset: 0x4 */
15796   __IO uint32_t CLKCFG;                            /**< Clock Configuration, offset: 0x8 */
15797   __IO uint32_t DIVISOR;                           /**< Baud Rate Divisor, offset: 0xC */
15798   __IO uint32_t CTRL;                              /**< Control, offset: 0x10 */
15799   __IO uint32_t INT_MASK;                          /**< Interrupt Mask, offset: 0x14 */
15800   __IO uint32_t RX_THD;                            /**< Receiver Threshold, offset: 0x18 */
15801   __IO uint32_t TX_THD;                            /**< Transmitter Threshold, offset: 0x1C */
15802   __IO uint32_t RX_STATUS;                         /**< Receive Status, offset: 0x20 */
15803   __IO uint32_t TX_STATUS;                         /**< Transmitter Status, offset: 0x24 */
15804   __IO uint32_t PCSR;                              /**< Port Control and Status, offset: 0x28 */
15805   __I  uint32_t RX_BUF;                            /**< Receive Data Read Buffer, offset: 0x2C */
15806   __O  uint32_t TX_BUF;                            /**< Transmit Data Buffer, offset: 0x30 */
15807   __IO uint32_t TX_GETU;                           /**< Transmitter Guard ETU Value, offset: 0x34 */
15808   __IO uint32_t CWT_VAL;                           /**< Character Wait Time Value, offset: 0x38 */
15809   __IO uint32_t BWT_VAL;                           /**< Block Wait Time Value, offset: 0x3C */
15810   __IO uint32_t BGT_VAL;                           /**< Block Guard Time Value, offset: 0x40 */
15811   __IO uint32_t GPCNT0_VAL;                        /**< General Purpose Counter 0 Timeout Value, offset: 0x44 */
15812   __IO uint32_t GPCNT1_VAL;                        /**< General Purpose Counter 1 Timeout Value, offset: 0x48 */
15813 } EMVSIM_Type;
15814 
15815 /* ----------------------------------------------------------------------------
15816    -- EMVSIM Register Masks
15817    ---------------------------------------------------------------------------- */
15818 
15819 /*!
15820  * @addtogroup EMVSIM_Register_Masks EMVSIM Register Masks
15821  * @{
15822  */
15823 
15824 /*! @name VER_ID - Version ID */
15825 /*! @{ */
15826 
15827 #define EMVSIM_VER_ID_VER_MASK                   (0xFFFFFFFFU)
15828 #define EMVSIM_VER_ID_VER_SHIFT                  (0U)
15829 /*! VER - Version ID */
15830 #define EMVSIM_VER_ID_VER(x)                     (((uint32_t)(((uint32_t)(x)) << EMVSIM_VER_ID_VER_SHIFT)) & EMVSIM_VER_ID_VER_MASK)
15831 /*! @} */
15832 
15833 /*! @name PARAM - Parameters */
15834 /*! @{ */
15835 
15836 #define EMVSIM_PARAM_RX_FIFO_DEPTH_MASK          (0xFFU)
15837 #define EMVSIM_PARAM_RX_FIFO_DEPTH_SHIFT         (0U)
15838 /*! RX_FIFO_DEPTH - Receive FIFO Depth */
15839 #define EMVSIM_PARAM_RX_FIFO_DEPTH(x)            (((uint32_t)(((uint32_t)(x)) << EMVSIM_PARAM_RX_FIFO_DEPTH_SHIFT)) & EMVSIM_PARAM_RX_FIFO_DEPTH_MASK)
15840 
15841 #define EMVSIM_PARAM_TX_FIFO_DEPTH_MASK          (0xFF00U)
15842 #define EMVSIM_PARAM_TX_FIFO_DEPTH_SHIFT         (8U)
15843 /*! TX_FIFO_DEPTH - Transmit FIFO Depth */
15844 #define EMVSIM_PARAM_TX_FIFO_DEPTH(x)            (((uint32_t)(((uint32_t)(x)) << EMVSIM_PARAM_TX_FIFO_DEPTH_SHIFT)) & EMVSIM_PARAM_TX_FIFO_DEPTH_MASK)
15845 /*! @} */
15846 
15847 /*! @name CLKCFG - Clock Configuration */
15848 /*! @{ */
15849 
15850 #define EMVSIM_CLKCFG_CLK_PRSC_MASK              (0xFFU)
15851 #define EMVSIM_CLKCFG_CLK_PRSC_SHIFT             (0U)
15852 /*! CLK_PRSC - Clock Prescaler Value */
15853 #define EMVSIM_CLKCFG_CLK_PRSC(x)                (((uint32_t)(((uint32_t)(x)) << EMVSIM_CLKCFG_CLK_PRSC_SHIFT)) & EMVSIM_CLKCFG_CLK_PRSC_MASK)
15854 
15855 #define EMVSIM_CLKCFG_GPCNT1_CLK_SEL_MASK        (0x300U)
15856 #define EMVSIM_CLKCFG_GPCNT1_CLK_SEL_SHIFT       (8U)
15857 /*! GPCNT1_CLK_SEL - General Purpose Counter 1 Clock Select
15858  *  0b00..Disable/reset
15859  *  0b01..Card clock
15860  *  0b10..Receive clock
15861  *  0b11..ETU clock (transmit clock)
15862  */
15863 #define EMVSIM_CLKCFG_GPCNT1_CLK_SEL(x)          (((uint32_t)(((uint32_t)(x)) << EMVSIM_CLKCFG_GPCNT1_CLK_SEL_SHIFT)) & EMVSIM_CLKCFG_GPCNT1_CLK_SEL_MASK)
15864 
15865 #define EMVSIM_CLKCFG_GPCNT0_CLK_SEL_MASK        (0xC00U)
15866 #define EMVSIM_CLKCFG_GPCNT0_CLK_SEL_SHIFT       (10U)
15867 /*! GPCNT0_CLK_SEL - General Purpose Counter 0 Clock Select
15868  *  0b00..Disable/reset
15869  *  0b01..Card clock
15870  *  0b10..Receive clock
15871  *  0b11..ETU clock (transmit clock)
15872  */
15873 #define EMVSIM_CLKCFG_GPCNT0_CLK_SEL(x)          (((uint32_t)(((uint32_t)(x)) << EMVSIM_CLKCFG_GPCNT0_CLK_SEL_SHIFT)) & EMVSIM_CLKCFG_GPCNT0_CLK_SEL_MASK)
15874 /*! @} */
15875 
15876 /*! @name DIVISOR - Baud Rate Divisor */
15877 /*! @{ */
15878 
15879 #define EMVSIM_DIVISOR_DIVISOR_VALUE_MASK        (0x1FFU)
15880 #define EMVSIM_DIVISOR_DIVISOR_VALUE_SHIFT       (0U)
15881 /*! DIVISOR_VALUE - Divisor (F/D) Value
15882  *  0b000000000-0b000000100..Invalid. As per ISO 7816 specification, the minimum value of F/D is 5.
15883  *  0b000000101-0b011111111..Divisor value F/D
15884  */
15885 #define EMVSIM_DIVISOR_DIVISOR_VALUE(x)          (((uint32_t)(((uint32_t)(x)) << EMVSIM_DIVISOR_DIVISOR_VALUE_SHIFT)) & EMVSIM_DIVISOR_DIVISOR_VALUE_MASK)
15886 /*! @} */
15887 
15888 /*! @name CTRL - Control */
15889 /*! @{ */
15890 
15891 #define EMVSIM_CTRL_IC_MASK                      (0x1U)
15892 #define EMVSIM_CTRL_IC_SHIFT                     (0U)
15893 /*! IC - Inverse Convention
15894  *  0b0..Direct
15895  *  0b1..Inverse
15896  */
15897 #define EMVSIM_CTRL_IC(x)                        (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_IC_SHIFT)) & EMVSIM_CTRL_IC_MASK)
15898 
15899 #define EMVSIM_CTRL_ICM_MASK                     (0x2U)
15900 #define EMVSIM_CTRL_ICM_SHIFT                    (1U)
15901 /*! ICM - Initial Character Mode
15902  *  0b0..Disable
15903  *  0b1..Enable
15904  */
15905 #define EMVSIM_CTRL_ICM(x)                       (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_ICM_SHIFT)) & EMVSIM_CTRL_ICM_MASK)
15906 
15907 #define EMVSIM_CTRL_ANACK_MASK                   (0x4U)
15908 #define EMVSIM_CTRL_ANACK_SHIFT                  (2U)
15909 /*! ANACK - Auto NACK Enable
15910  *  0b0..Disable
15911  *  0b1..Enable
15912  */
15913 #define EMVSIM_CTRL_ANACK(x)                     (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_ANACK_SHIFT)) & EMVSIM_CTRL_ANACK_MASK)
15914 
15915 #define EMVSIM_CTRL_ONACK_MASK                   (0x8U)
15916 #define EMVSIM_CTRL_ONACK_SHIFT                  (3U)
15917 /*! ONACK - Overrun NACK Enable
15918  *  0b0..Disable
15919  *  0b1..Enable
15920  */
15921 #define EMVSIM_CTRL_ONACK(x)                     (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_ONACK_SHIFT)) & EMVSIM_CTRL_ONACK_MASK)
15922 
15923 #define EMVSIM_CTRL_FLSH_RX_MASK                 (0x100U)
15924 #define EMVSIM_CTRL_FLSH_RX_SHIFT                (8U)
15925 /*! FLSH_RX - Flush Receiver
15926  *  0b0..Normal
15927  *  0b1..Reset
15928  */
15929 #define EMVSIM_CTRL_FLSH_RX(x)                   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_FLSH_RX_SHIFT)) & EMVSIM_CTRL_FLSH_RX_MASK)
15930 
15931 #define EMVSIM_CTRL_FLSH_TX_MASK                 (0x200U)
15932 #define EMVSIM_CTRL_FLSH_TX_SHIFT                (9U)
15933 /*! FLSH_TX - Flush Transmitter
15934  *  0b0..Normal
15935  *  0b1..Reset
15936  */
15937 #define EMVSIM_CTRL_FLSH_TX(x)                   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_FLSH_TX_SHIFT)) & EMVSIM_CTRL_FLSH_TX_MASK)
15938 
15939 #define EMVSIM_CTRL_SW_RST_MASK                  (0x400U)
15940 #define EMVSIM_CTRL_SW_RST_SHIFT                 (10U)
15941 /*! SW_RST - Software Reset
15942  *  0b0..Normal
15943  *  0b1..Reset
15944  */
15945 #define EMVSIM_CTRL_SW_RST(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_SW_RST_SHIFT)) & EMVSIM_CTRL_SW_RST_MASK)
15946 
15947 #define EMVSIM_CTRL_KILL_CLOCKS_MASK             (0x800U)
15948 #define EMVSIM_CTRL_KILL_CLOCKS_SHIFT            (11U)
15949 /*! KILL_CLOCKS - Kill Internal Clocks
15950  *  0b0..Enable
15951  *  0b1..Disable
15952  */
15953 #define EMVSIM_CTRL_KILL_CLOCKS(x)               (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_KILL_CLOCKS_SHIFT)) & EMVSIM_CTRL_KILL_CLOCKS_MASK)
15954 
15955 #define EMVSIM_CTRL_DOZE_EN_MASK                 (0x1000U)
15956 #define EMVSIM_CTRL_DOZE_EN_SHIFT                (12U)
15957 /*! DOZE_EN - Doze Enable
15958  *  0b0..Disable
15959  *  0b1..Enable
15960  */
15961 #define EMVSIM_CTRL_DOZE_EN(x)                   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_DOZE_EN_SHIFT)) & EMVSIM_CTRL_DOZE_EN_MASK)
15962 
15963 #define EMVSIM_CTRL_STOP_EN_MASK                 (0x2000U)
15964 #define EMVSIM_CTRL_STOP_EN_SHIFT                (13U)
15965 /*! STOP_EN - STOP Enable
15966  *  0b0..Disable
15967  *  0b1..Enable
15968  */
15969 #define EMVSIM_CTRL_STOP_EN(x)                   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_STOP_EN_SHIFT)) & EMVSIM_CTRL_STOP_EN_MASK)
15970 
15971 #define EMVSIM_CTRL_RCV_EN_MASK                  (0x10000U)
15972 #define EMVSIM_CTRL_RCV_EN_SHIFT                 (16U)
15973 /*! RCV_EN - Receiver Enable
15974  *  0b0..Disable
15975  *  0b1..Enable
15976  */
15977 #define EMVSIM_CTRL_RCV_EN(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RCV_EN_SHIFT)) & EMVSIM_CTRL_RCV_EN_MASK)
15978 
15979 #define EMVSIM_CTRL_XMT_EN_MASK                  (0x20000U)
15980 #define EMVSIM_CTRL_XMT_EN_SHIFT                 (17U)
15981 /*! XMT_EN - Transmitter Enable
15982  *  0b0..Disable
15983  *  0b1..Enable
15984  */
15985 #define EMVSIM_CTRL_XMT_EN(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_XMT_EN_SHIFT)) & EMVSIM_CTRL_XMT_EN_MASK)
15986 
15987 #define EMVSIM_CTRL_RCVR_11_MASK                 (0x40000U)
15988 #define EMVSIM_CTRL_RCVR_11_SHIFT                (18U)
15989 /*! RCVR_11 - Receiver 11 ETU Mode Enable
15990  *  0b0..12 ETU operation
15991  *  0b1..11 ETU operation
15992  */
15993 #define EMVSIM_CTRL_RCVR_11(x)                   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RCVR_11_SHIFT)) & EMVSIM_CTRL_RCVR_11_MASK)
15994 
15995 #define EMVSIM_CTRL_RX_DMA_EN_MASK               (0x80000U)
15996 #define EMVSIM_CTRL_RX_DMA_EN_SHIFT              (19U)
15997 /*! RX_DMA_EN - Receive DMA Enable
15998  *  0b0..Not asserted
15999  *  0b1..Asserted
16000  */
16001 #define EMVSIM_CTRL_RX_DMA_EN(x)                 (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RX_DMA_EN_SHIFT)) & EMVSIM_CTRL_RX_DMA_EN_MASK)
16002 
16003 #define EMVSIM_CTRL_TX_DMA_EN_MASK               (0x100000U)
16004 #define EMVSIM_CTRL_TX_DMA_EN_SHIFT              (20U)
16005 /*! TX_DMA_EN - Transmit DMA Enable
16006  *  0b0..Not asserted
16007  *  0b1..Asserted
16008  */
16009 #define EMVSIM_CTRL_TX_DMA_EN(x)                 (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_TX_DMA_EN_SHIFT)) & EMVSIM_CTRL_TX_DMA_EN_MASK)
16010 
16011 #define EMVSIM_CTRL_INV_CRC_VAL_MASK             (0x1000000U)
16012 #define EMVSIM_CTRL_INV_CRC_VAL_SHIFT            (24U)
16013 /*! INV_CRC_VAL - Invert CRC Output Value Bits
16014  *  0b0..Not inverted
16015  *  0b1..Inverted
16016  */
16017 #define EMVSIM_CTRL_INV_CRC_VAL(x)               (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_INV_CRC_VAL_SHIFT)) & EMVSIM_CTRL_INV_CRC_VAL_MASK)
16018 
16019 #define EMVSIM_CTRL_CRC_OUT_FLIP_MASK            (0x2000000U)
16020 #define EMVSIM_CTRL_CRC_OUT_FLIP_SHIFT           (25U)
16021 /*! CRC_OUT_FLIP - CRC Output Value Bit Reversal Or Flip Control
16022  *  0b0..Not reversed
16023  *  0b1..Reversed
16024  */
16025 #define EMVSIM_CTRL_CRC_OUT_FLIP(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CRC_OUT_FLIP_SHIFT)) & EMVSIM_CTRL_CRC_OUT_FLIP_MASK)
16026 
16027 #define EMVSIM_CTRL_CRC_IN_FLIP_MASK             (0x4000000U)
16028 #define EMVSIM_CTRL_CRC_IN_FLIP_SHIFT            (26U)
16029 /*! CRC_IN_FLIP - CRC Input Byte's Bit Reversal Or Flip Control
16030  *  0b0..Not reversed
16031  *  0b1..Reversed
16032  */
16033 #define EMVSIM_CTRL_CRC_IN_FLIP(x)               (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CRC_IN_FLIP_SHIFT)) & EMVSIM_CTRL_CRC_IN_FLIP_MASK)
16034 
16035 #define EMVSIM_CTRL_CWT_EN_MASK                  (0x8000000U)
16036 #define EMVSIM_CTRL_CWT_EN_SHIFT                 (27U)
16037 /*! CWT_EN - CWT Counter Enable
16038  *  0b0..Disable
16039  *  0b1..Enable
16040  */
16041 #define EMVSIM_CTRL_CWT_EN(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CWT_EN_SHIFT)) & EMVSIM_CTRL_CWT_EN_MASK)
16042 
16043 #define EMVSIM_CTRL_LRC_EN_MASK                  (0x10000000U)
16044 #define EMVSIM_CTRL_LRC_EN_SHIFT                 (28U)
16045 /*! LRC_EN - LRC Enable
16046  *  0b0..Disable
16047  *  0b1..Enable
16048  */
16049 #define EMVSIM_CTRL_LRC_EN(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_LRC_EN_SHIFT)) & EMVSIM_CTRL_LRC_EN_MASK)
16050 
16051 #define EMVSIM_CTRL_CRC_EN_MASK                  (0x20000000U)
16052 #define EMVSIM_CTRL_CRC_EN_SHIFT                 (29U)
16053 /*! CRC_EN - CRC Enable
16054  *  0b0..Disable
16055  *  0b1..Enable
16056  */
16057 #define EMVSIM_CTRL_CRC_EN(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CRC_EN_SHIFT)) & EMVSIM_CTRL_CRC_EN_MASK)
16058 
16059 #define EMVSIM_CTRL_XMT_CRC_LRC_MASK             (0x40000000U)
16060 #define EMVSIM_CTRL_XMT_CRC_LRC_SHIFT            (30U)
16061 /*! XMT_CRC_LRC - Transmit CRC or LRC Enable
16062  *  0b0..Do not transmit
16063  *  0b1..Transmit
16064  */
16065 #define EMVSIM_CTRL_XMT_CRC_LRC(x)               (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_XMT_CRC_LRC_SHIFT)) & EMVSIM_CTRL_XMT_CRC_LRC_MASK)
16066 
16067 #define EMVSIM_CTRL_BWT_EN_MASK                  (0x80000000U)
16068 #define EMVSIM_CTRL_BWT_EN_SHIFT                 (31U)
16069 /*! BWT_EN - Block Wait Time Counter Enable
16070  *  0b0..Disable
16071  *  0b1..Enable
16072  */
16073 #define EMVSIM_CTRL_BWT_EN(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_BWT_EN_SHIFT)) & EMVSIM_CTRL_BWT_EN_MASK)
16074 /*! @} */
16075 
16076 /*! @name INT_MASK - Interrupt Mask */
16077 /*! @{ */
16078 
16079 #define EMVSIM_INT_MASK_RDT_IM_MASK              (0x1U)
16080 #define EMVSIM_INT_MASK_RDT_IM_SHIFT             (0U)
16081 /*! RDT_IM - Receive Data Threshold Interrupt Mask
16082  *  0b0..Enable
16083  *  0b1..Masked
16084  */
16085 #define EMVSIM_INT_MASK_RDT_IM(x)                (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RDT_IM_SHIFT)) & EMVSIM_INT_MASK_RDT_IM_MASK)
16086 
16087 #define EMVSIM_INT_MASK_TC_IM_MASK               (0x2U)
16088 #define EMVSIM_INT_MASK_TC_IM_SHIFT              (1U)
16089 /*! TC_IM - Transmit Complete Interrupt Mask
16090  *  0b0..Enable
16091  *  0b1..Masked
16092  */
16093 #define EMVSIM_INT_MASK_TC_IM(x)                 (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TC_IM_SHIFT)) & EMVSIM_INT_MASK_TC_IM_MASK)
16094 
16095 #define EMVSIM_INT_MASK_RFO_IM_MASK              (0x4U)
16096 #define EMVSIM_INT_MASK_RFO_IM_SHIFT             (2U)
16097 /*! RFO_IM - Receive FIFO Overflow Interrupt Mask
16098  *  0b0..Enable
16099  *  0b1..Masked
16100  */
16101 #define EMVSIM_INT_MASK_RFO_IM(x)                (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RFO_IM_SHIFT)) & EMVSIM_INT_MASK_RFO_IM_MASK)
16102 
16103 #define EMVSIM_INT_MASK_ETC_IM_MASK              (0x8U)
16104 #define EMVSIM_INT_MASK_ETC_IM_SHIFT             (3U)
16105 /*! ETC_IM - Early Transmit Complete Interrupt Mask
16106  *  0b0..Enable
16107  *  0b1..Masked
16108  */
16109 #define EMVSIM_INT_MASK_ETC_IM(x)                (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_ETC_IM_SHIFT)) & EMVSIM_INT_MASK_ETC_IM_MASK)
16110 
16111 #define EMVSIM_INT_MASK_TFE_IM_MASK              (0x10U)
16112 #define EMVSIM_INT_MASK_TFE_IM_SHIFT             (4U)
16113 /*! TFE_IM - Transmit FIFO Empty Interrupt Mask
16114  *  0b0..Enable
16115  *  0b1..Masked
16116  */
16117 #define EMVSIM_INT_MASK_TFE_IM(x)                (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TFE_IM_SHIFT)) & EMVSIM_INT_MASK_TFE_IM_MASK)
16118 
16119 #define EMVSIM_INT_MASK_TNACK_IM_MASK            (0x20U)
16120 #define EMVSIM_INT_MASK_TNACK_IM_SHIFT           (5U)
16121 /*! TNACK_IM - Transmit NACK Threshold Interrupt Mask
16122  *  0b0..Enable
16123  *  0b1..Masked
16124  */
16125 #define EMVSIM_INT_MASK_TNACK_IM(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TNACK_IM_SHIFT)) & EMVSIM_INT_MASK_TNACK_IM_MASK)
16126 
16127 #define EMVSIM_INT_MASK_TFF_IM_MASK              (0x40U)
16128 #define EMVSIM_INT_MASK_TFF_IM_SHIFT             (6U)
16129 /*! TFF_IM - Transmit FIFO Full Interrupt Mask
16130  *  0b0..Enable
16131  *  0b1..Masked
16132  */
16133 #define EMVSIM_INT_MASK_TFF_IM(x)                (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TFF_IM_SHIFT)) & EMVSIM_INT_MASK_TFF_IM_MASK)
16134 
16135 #define EMVSIM_INT_MASK_TDT_IM_MASK              (0x80U)
16136 #define EMVSIM_INT_MASK_TDT_IM_SHIFT             (7U)
16137 /*! TDT_IM - Transmit Data Threshold Interrupt Mask
16138  *  0b0..Enable
16139  *  0b1..Masked
16140  */
16141 #define EMVSIM_INT_MASK_TDT_IM(x)                (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TDT_IM_SHIFT)) & EMVSIM_INT_MASK_TDT_IM_MASK)
16142 
16143 #define EMVSIM_INT_MASK_GPCNT0_IM_MASK           (0x100U)
16144 #define EMVSIM_INT_MASK_GPCNT0_IM_SHIFT          (8U)
16145 /*! GPCNT0_IM - General Purpose Timer 0 Timeout Interrupt Mask
16146  *  0b0..Enable
16147  *  0b1..Masked
16148  */
16149 #define EMVSIM_INT_MASK_GPCNT0_IM(x)             (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_GPCNT0_IM_SHIFT)) & EMVSIM_INT_MASK_GPCNT0_IM_MASK)
16150 
16151 #define EMVSIM_INT_MASK_CWT_ERR_IM_MASK          (0x200U)
16152 #define EMVSIM_INT_MASK_CWT_ERR_IM_SHIFT         (9U)
16153 /*! CWT_ERR_IM - Character Wait Time Error Interrupt Mask
16154  *  0b0..Enable
16155  *  0b1..Masked
16156  */
16157 #define EMVSIM_INT_MASK_CWT_ERR_IM(x)            (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_CWT_ERR_IM_SHIFT)) & EMVSIM_INT_MASK_CWT_ERR_IM_MASK)
16158 
16159 #define EMVSIM_INT_MASK_RNACK_IM_MASK            (0x400U)
16160 #define EMVSIM_INT_MASK_RNACK_IM_SHIFT           (10U)
16161 /*! RNACK_IM - Receiver NACK Threshold Interrupt Mask
16162  *  0b0..Enable
16163  *  0b1..Masked
16164  */
16165 #define EMVSIM_INT_MASK_RNACK_IM(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RNACK_IM_SHIFT)) & EMVSIM_INT_MASK_RNACK_IM_MASK)
16166 
16167 #define EMVSIM_INT_MASK_BWT_ERR_IM_MASK          (0x800U)
16168 #define EMVSIM_INT_MASK_BWT_ERR_IM_SHIFT         (11U)
16169 /*! BWT_ERR_IM - Block Wait Time Error Interrupt Mask
16170  *  0b0..Enable
16171  *  0b1..Masked
16172  */
16173 #define EMVSIM_INT_MASK_BWT_ERR_IM(x)            (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_BWT_ERR_IM_SHIFT)) & EMVSIM_INT_MASK_BWT_ERR_IM_MASK)
16174 
16175 #define EMVSIM_INT_MASK_BGT_ERR_IM_MASK          (0x1000U)
16176 #define EMVSIM_INT_MASK_BGT_ERR_IM_SHIFT         (12U)
16177 /*! BGT_ERR_IM - Block Guard Time Error Interrupt
16178  *  0b0..Enable
16179  *  0b1..Masked
16180  */
16181 #define EMVSIM_INT_MASK_BGT_ERR_IM(x)            (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_BGT_ERR_IM_SHIFT)) & EMVSIM_INT_MASK_BGT_ERR_IM_MASK)
16182 
16183 #define EMVSIM_INT_MASK_GPCNT1_IM_MASK           (0x2000U)
16184 #define EMVSIM_INT_MASK_GPCNT1_IM_SHIFT          (13U)
16185 /*! GPCNT1_IM - General Purpose Counter 1 Timeout Interrupt Mask
16186  *  0b0..Enable
16187  *  0b1..Masked
16188  */
16189 #define EMVSIM_INT_MASK_GPCNT1_IM(x)             (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_GPCNT1_IM_SHIFT)) & EMVSIM_INT_MASK_GPCNT1_IM_MASK)
16190 
16191 #define EMVSIM_INT_MASK_RX_DATA_IM_MASK          (0x4000U)
16192 #define EMVSIM_INT_MASK_RX_DATA_IM_SHIFT         (14U)
16193 /*! RX_DATA_IM - Receive Data Interrupt Mask
16194  *  0b0..Enable
16195  *  0b1..Masked
16196  */
16197 #define EMVSIM_INT_MASK_RX_DATA_IM(x)            (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RX_DATA_IM_SHIFT)) & EMVSIM_INT_MASK_RX_DATA_IM_MASK)
16198 
16199 #define EMVSIM_INT_MASK_PEF_IM_MASK              (0x8000U)
16200 #define EMVSIM_INT_MASK_PEF_IM_SHIFT             (15U)
16201 /*! PEF_IM - Parity Error Interrupt Mask
16202  *  0b0..Enable
16203  *  0b1..Masked
16204  */
16205 #define EMVSIM_INT_MASK_PEF_IM(x)                (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_PEF_IM_SHIFT)) & EMVSIM_INT_MASK_PEF_IM_MASK)
16206 /*! @} */
16207 
16208 /*! @name RX_THD - Receiver Threshold */
16209 /*! @{ */
16210 
16211 #define EMVSIM_RX_THD_RDT_MASK                   (0xFU)
16212 #define EMVSIM_RX_THD_RDT_SHIFT                  (0U)
16213 /*! RDT - Receiver Data Threshold Value */
16214 #define EMVSIM_RX_THD_RDT(x)                     (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_THD_RDT_SHIFT)) & EMVSIM_RX_THD_RDT_MASK)
16215 
16216 #define EMVSIM_RX_THD_RNCK_THD_MASK              (0xF00U)
16217 #define EMVSIM_RX_THD_RNCK_THD_SHIFT             (8U)
16218 /*! RNCK_THD - Receiver NACK Threshold Value */
16219 #define EMVSIM_RX_THD_RNCK_THD(x)                (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_THD_RNCK_THD_SHIFT)) & EMVSIM_RX_THD_RNCK_THD_MASK)
16220 /*! @} */
16221 
16222 /*! @name TX_THD - Transmitter Threshold */
16223 /*! @{ */
16224 
16225 #define EMVSIM_TX_THD_TDT_MASK                   (0xFU)
16226 #define EMVSIM_TX_THD_TDT_SHIFT                  (0U)
16227 /*! TDT - Transmitter Data Threshold Value */
16228 #define EMVSIM_TX_THD_TDT(x)                     (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_THD_TDT_SHIFT)) & EMVSIM_TX_THD_TDT_MASK)
16229 
16230 #define EMVSIM_TX_THD_TNCK_THD_MASK              (0xF00U)
16231 #define EMVSIM_TX_THD_TNCK_THD_SHIFT             (8U)
16232 /*! TNCK_THD - Transmitter NACK Threshold Value */
16233 #define EMVSIM_TX_THD_TNCK_THD(x)                (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_THD_TNCK_THD_SHIFT)) & EMVSIM_TX_THD_TNCK_THD_MASK)
16234 /*! @} */
16235 
16236 /*! @name RX_STATUS - Receive Status */
16237 /*! @{ */
16238 
16239 #define EMVSIM_RX_STATUS_RFO_MASK                (0x1U)
16240 #define EMVSIM_RX_STATUS_RFO_SHIFT               (0U)
16241 /*! RFO - Receive FIFO Overflow Flag
16242  *  0b0..No overrun error
16243  *  0b1..Overrun error
16244  */
16245 #define EMVSIM_RX_STATUS_RFO(x)                  (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RFO_SHIFT)) & EMVSIM_RX_STATUS_RFO_MASK)
16246 
16247 #define EMVSIM_RX_STATUS_RX_DATA_MASK            (0x10U)
16248 #define EMVSIM_RX_STATUS_RX_DATA_SHIFT           (4U)
16249 /*! RX_DATA - Receive Data Interrupt Flag
16250  *  0b0..No new byte
16251  *  0b1..New byte
16252  */
16253 #define EMVSIM_RX_STATUS_RX_DATA(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RX_DATA_SHIFT)) & EMVSIM_RX_STATUS_RX_DATA_MASK)
16254 
16255 #define EMVSIM_RX_STATUS_RDTF_MASK               (0x20U)
16256 #define EMVSIM_RX_STATUS_RDTF_SHIFT              (5U)
16257 /*! RDTF - Receive Data Threshold Interrupt Flag
16258  *  0b0..Less than threshold
16259  *  0b1..Greater than or equal to threshold
16260  */
16261 #define EMVSIM_RX_STATUS_RDTF(x)                 (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RDTF_SHIFT)) & EMVSIM_RX_STATUS_RDTF_MASK)
16262 
16263 #define EMVSIM_RX_STATUS_LRC_OK_MASK             (0x40U)
16264 #define EMVSIM_RX_STATUS_LRC_OK_SHIFT            (6U)
16265 /*! LRC_OK - LRC Check OK Flag
16266  *  0b0..No match
16267  *  0b1..Match
16268  */
16269 #define EMVSIM_RX_STATUS_LRC_OK(x)               (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_LRC_OK_SHIFT)) & EMVSIM_RX_STATUS_LRC_OK_MASK)
16270 
16271 #define EMVSIM_RX_STATUS_CRC_OK_MASK             (0x80U)
16272 #define EMVSIM_RX_STATUS_CRC_OK_SHIFT            (7U)
16273 /*! CRC_OK - CRC Check OK Flag
16274  *  0b0..Current CRC value does not match remainder.
16275  *  0b1..Current calculated CRC value matches the expected result.
16276  */
16277 #define EMVSIM_RX_STATUS_CRC_OK(x)               (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_CRC_OK_SHIFT)) & EMVSIM_RX_STATUS_CRC_OK_MASK)
16278 
16279 #define EMVSIM_RX_STATUS_CWT_ERR_MASK            (0x100U)
16280 #define EMVSIM_RX_STATUS_CWT_ERR_SHIFT           (8U)
16281 /*! CWT_ERR - Character Wait Time Error Flag
16282  *  0b0..No CWT violation
16283  *  0b1..CWT violation
16284  */
16285 #define EMVSIM_RX_STATUS_CWT_ERR(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_CWT_ERR_SHIFT)) & EMVSIM_RX_STATUS_CWT_ERR_MASK)
16286 
16287 #define EMVSIM_RX_STATUS_RTE_MASK                (0x200U)
16288 #define EMVSIM_RX_STATUS_RTE_SHIFT               (9U)
16289 /*! RTE - Received NACK Threshold Error Flag
16290  *  0b0..Less than
16291  *  0b1..Equal to
16292  */
16293 #define EMVSIM_RX_STATUS_RTE(x)                  (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RTE_SHIFT)) & EMVSIM_RX_STATUS_RTE_MASK)
16294 
16295 #define EMVSIM_RX_STATUS_BWT_ERR_MASK            (0x400U)
16296 #define EMVSIM_RX_STATUS_BWT_ERR_SHIFT           (10U)
16297 /*! BWT_ERR - Block Wait Time Error Flag
16298  *  0b0..Not exceeded
16299  *  0b1..Exceeded
16300  */
16301 #define EMVSIM_RX_STATUS_BWT_ERR(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_BWT_ERR_SHIFT)) & EMVSIM_RX_STATUS_BWT_ERR_MASK)
16302 
16303 #define EMVSIM_RX_STATUS_BGT_ERR_MASK            (0x800U)
16304 #define EMVSIM_RX_STATUS_BGT_ERR_SHIFT           (11U)
16305 /*! BGT_ERR - Block Guard Time Error Flag
16306  *  0b0..Sufficient
16307  *  0b1..Too small
16308  */
16309 #define EMVSIM_RX_STATUS_BGT_ERR(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_BGT_ERR_SHIFT)) & EMVSIM_RX_STATUS_BGT_ERR_MASK)
16310 
16311 #define EMVSIM_RX_STATUS_PEF_MASK                (0x1000U)
16312 #define EMVSIM_RX_STATUS_PEF_SHIFT               (12U)
16313 /*! PEF - Parity Error Flag
16314  *  0b0..No error
16315  *  0b1..Error
16316  */
16317 #define EMVSIM_RX_STATUS_PEF(x)                  (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_PEF_SHIFT)) & EMVSIM_RX_STATUS_PEF_MASK)
16318 
16319 #define EMVSIM_RX_STATUS_FEF_MASK                (0x2000U)
16320 #define EMVSIM_RX_STATUS_FEF_SHIFT               (13U)
16321 /*! FEF - Frame Error Flag
16322  *  0b0..No error
16323  *  0b1..Error
16324  */
16325 #define EMVSIM_RX_STATUS_FEF(x)                  (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_FEF_SHIFT)) & EMVSIM_RX_STATUS_FEF_MASK)
16326 
16327 #define EMVSIM_RX_STATUS_RX_WPTR_MASK            (0xF0000U)
16328 #define EMVSIM_RX_STATUS_RX_WPTR_SHIFT           (16U)
16329 /*! RX_WPTR - Receive FIFO Write Pointer Value */
16330 #define EMVSIM_RX_STATUS_RX_WPTR(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RX_WPTR_SHIFT)) & EMVSIM_RX_STATUS_RX_WPTR_MASK)
16331 
16332 #define EMVSIM_RX_STATUS_RX_CNT_MASK             (0xF000000U)
16333 #define EMVSIM_RX_STATUS_RX_CNT_SHIFT            (24U)
16334 /*! RX_CNT - Receive FIFO Byte Count
16335  *  0b0000..FIFO empty
16336  */
16337 #define EMVSIM_RX_STATUS_RX_CNT(x)               (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RX_CNT_SHIFT)) & EMVSIM_RX_STATUS_RX_CNT_MASK)
16338 /*! @} */
16339 
16340 /*! @name TX_STATUS - Transmitter Status */
16341 /*! @{ */
16342 
16343 #define EMVSIM_TX_STATUS_TNTE_MASK               (0x1U)
16344 #define EMVSIM_TX_STATUS_TNTE_SHIFT              (0U)
16345 /*! TNTE - Transmit NACK Threshold Error Flag
16346  *  0b0..Threshold not reached
16347  *  0b1..Threshold reached
16348  */
16349 #define EMVSIM_TX_STATUS_TNTE(x)                 (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TNTE_SHIFT)) & EMVSIM_TX_STATUS_TNTE_MASK)
16350 
16351 #define EMVSIM_TX_STATUS_TFE_MASK                (0x8U)
16352 #define EMVSIM_TX_STATUS_TFE_SHIFT               (3U)
16353 /*! TFE - Transmit FIFO Empty Flag
16354  *  0b0..Not empty
16355  *  0b1..Empty
16356  */
16357 #define EMVSIM_TX_STATUS_TFE(x)                  (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TFE_SHIFT)) & EMVSIM_TX_STATUS_TFE_MASK)
16358 
16359 #define EMVSIM_TX_STATUS_ETCF_MASK               (0x10U)
16360 #define EMVSIM_TX_STATUS_ETCF_SHIFT              (4U)
16361 /*! ETCF - Early Transmit Complete Flag
16362  *  0b0..Pending or incomplete
16363  *  0b1..Complete
16364  */
16365 #define EMVSIM_TX_STATUS_ETCF(x)                 (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_ETCF_SHIFT)) & EMVSIM_TX_STATUS_ETCF_MASK)
16366 
16367 #define EMVSIM_TX_STATUS_TCF_MASK                (0x20U)
16368 #define EMVSIM_TX_STATUS_TCF_SHIFT               (5U)
16369 /*! TCF - Transmit Complete Flag
16370  *  0b0..Pending or incomplete
16371  *  0b1..Complete
16372  */
16373 #define EMVSIM_TX_STATUS_TCF(x)                  (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TCF_SHIFT)) & EMVSIM_TX_STATUS_TCF_MASK)
16374 
16375 #define EMVSIM_TX_STATUS_TFF_MASK                (0x40U)
16376 #define EMVSIM_TX_STATUS_TFF_SHIFT               (6U)
16377 /*! TFF - Transmit FIFO Full Flag
16378  *  0b0..Not full
16379  *  0b1..Full
16380  */
16381 #define EMVSIM_TX_STATUS_TFF(x)                  (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TFF_SHIFT)) & EMVSIM_TX_STATUS_TFF_MASK)
16382 
16383 #define EMVSIM_TX_STATUS_TDTF_MASK               (0x80U)
16384 #define EMVSIM_TX_STATUS_TDTF_SHIFT              (7U)
16385 /*! TDTF - Transmit Data Threshold Flag
16386  *  0b0..Threshold exceeded or this field written to 0
16387  *  0b1..Threshold not exceeded
16388  */
16389 #define EMVSIM_TX_STATUS_TDTF(x)                 (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TDTF_SHIFT)) & EMVSIM_TX_STATUS_TDTF_MASK)
16390 
16391 #define EMVSIM_TX_STATUS_GPCNT0_TO_MASK          (0x100U)
16392 #define EMVSIM_TX_STATUS_GPCNT0_TO_SHIFT         (8U)
16393 /*! GPCNT0_TO - General Purpose Counter 0 Timeout Flag
16394  *  0b0..GPCNT0 not reached, or flag cleared
16395  *  0b1..GPCNT0 reached
16396  */
16397 #define EMVSIM_TX_STATUS_GPCNT0_TO(x)            (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_GPCNT0_TO_SHIFT)) & EMVSIM_TX_STATUS_GPCNT0_TO_MASK)
16398 
16399 #define EMVSIM_TX_STATUS_GPCNT1_TO_MASK          (0x200U)
16400 #define EMVSIM_TX_STATUS_GPCNT1_TO_SHIFT         (9U)
16401 /*! GPCNT1_TO - General Purpose Counter 1 Timeout Flag
16402  *  0b0..GPCNT1 not reached, or flag cleared
16403  *  0b1..GPCNT1 reached
16404  */
16405 #define EMVSIM_TX_STATUS_GPCNT1_TO(x)            (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_GPCNT1_TO_SHIFT)) & EMVSIM_TX_STATUS_GPCNT1_TO_MASK)
16406 
16407 #define EMVSIM_TX_STATUS_TX_RPTR_MASK            (0xF0000U)
16408 #define EMVSIM_TX_STATUS_TX_RPTR_SHIFT           (16U)
16409 /*! TX_RPTR - Transmit FIFO Read Pointer */
16410 #define EMVSIM_TX_STATUS_TX_RPTR(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TX_RPTR_SHIFT)) & EMVSIM_TX_STATUS_TX_RPTR_MASK)
16411 
16412 #define EMVSIM_TX_STATUS_TX_CNT_MASK             (0xF000000U)
16413 #define EMVSIM_TX_STATUS_TX_CNT_SHIFT            (24U)
16414 /*! TX_CNT - Transmit FIFO Byte Count
16415  *  0b0000..FIFO empty
16416  */
16417 #define EMVSIM_TX_STATUS_TX_CNT(x)               (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TX_CNT_SHIFT)) & EMVSIM_TX_STATUS_TX_CNT_MASK)
16418 /*! @} */
16419 
16420 /*! @name PCSR - Port Control and Status */
16421 /*! @{ */
16422 
16423 #define EMVSIM_PCSR_SAPD_MASK                    (0x1U)
16424 #define EMVSIM_PCSR_SAPD_SHIFT                   (0U)
16425 /*! SAPD - Auto Power Down Enable
16426  *  0b0..Disable
16427  *  0b1..Enable
16428  */
16429 #define EMVSIM_PCSR_SAPD(x)                      (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SAPD_SHIFT)) & EMVSIM_PCSR_SAPD_MASK)
16430 
16431 #define EMVSIM_PCSR_SVCC_EN_MASK                 (0x2U)
16432 #define EMVSIM_PCSR_SVCC_EN_SHIFT                (1U)
16433 /*! SVCC_EN - Vcc Enable for Smart Card
16434  *  0b0..Disable
16435  *  0b1..Enable
16436  */
16437 #define EMVSIM_PCSR_SVCC_EN(x)                   (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SVCC_EN_SHIFT)) & EMVSIM_PCSR_SVCC_EN_MASK)
16438 
16439 #define EMVSIM_PCSR_VCCENP_MASK                  (0x4U)
16440 #define EMVSIM_PCSR_VCCENP_SHIFT                 (2U)
16441 /*! VCCENP - VCC Enable Polarity Control
16442  *  0b0..Active high
16443  *  0b1..Active low
16444  */
16445 #define EMVSIM_PCSR_VCCENP(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_VCCENP_SHIFT)) & EMVSIM_PCSR_VCCENP_MASK)
16446 
16447 #define EMVSIM_PCSR_SRST_MASK                    (0x8U)
16448 #define EMVSIM_PCSR_SRST_SHIFT                   (3U)
16449 /*! SRST - Reset Smart Card
16450  *  0b0..Assert
16451  *  0b1..Deassert
16452  */
16453 #define EMVSIM_PCSR_SRST(x)                      (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SRST_SHIFT)) & EMVSIM_PCSR_SRST_MASK)
16454 
16455 #define EMVSIM_PCSR_SCEN_MASK                    (0x10U)
16456 #define EMVSIM_PCSR_SCEN_SHIFT                   (4U)
16457 /*! SCEN - Clock Enable for Smart Card
16458  *  0b0..Disable
16459  *  0b1..Enable
16460  */
16461 #define EMVSIM_PCSR_SCEN(x)                      (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SCEN_SHIFT)) & EMVSIM_PCSR_SCEN_MASK)
16462 
16463 #define EMVSIM_PCSR_SCSP_MASK                    (0x20U)
16464 #define EMVSIM_PCSR_SCSP_SHIFT                   (5U)
16465 /*! SCSP - Smart Card Clock Stop Polarity
16466  *  0b0..Logic 0
16467  *  0b1..Logic 1
16468  */
16469 #define EMVSIM_PCSR_SCSP(x)                      (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SCSP_SHIFT)) & EMVSIM_PCSR_SCSP_MASK)
16470 
16471 #define EMVSIM_PCSR_SPD_MASK                     (0x80U)
16472 #define EMVSIM_PCSR_SPD_SHIFT                    (7U)
16473 /*! SPD - Auto Power-Down Control
16474  *  0b0..No
16475  *  0b1..Yes
16476  */
16477 #define EMVSIM_PCSR_SPD(x)                       (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPD_SHIFT)) & EMVSIM_PCSR_SPD_MASK)
16478 
16479 #define EMVSIM_PCSR_SPDIM_MASK                   (0x1000000U)
16480 #define EMVSIM_PCSR_SPDIM_SHIFT                  (24U)
16481 /*! SPDIM - Smart Card Presence Detect Interrupt Mask
16482  *  0b0..Enable
16483  *  0b1..Mask
16484  */
16485 #define EMVSIM_PCSR_SPDIM(x)                     (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDIM_SHIFT)) & EMVSIM_PCSR_SPDIM_MASK)
16486 
16487 #define EMVSIM_PCSR_SPDIF_MASK                   (0x2000000U)
16488 #define EMVSIM_PCSR_SPDIF_SHIFT                  (25U)
16489 /*! SPDIF - Smart Card Presence Detect Interrupt Flag
16490  *  0b0..No insertion or removal
16491  *  0b1..Insertion or removal
16492  */
16493 #define EMVSIM_PCSR_SPDIF(x)                     (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDIF_SHIFT)) & EMVSIM_PCSR_SPDIF_MASK)
16494 
16495 #define EMVSIM_PCSR_SPDP_MASK                    (0x4000000U)
16496 #define EMVSIM_PCSR_SPDP_SHIFT                   (26U)
16497 /*! SPDP - Smart Card Presence Detect Pin Status
16498  *  0b0..Logic low
16499  *  0b1..Logic high
16500  */
16501 #define EMVSIM_PCSR_SPDP(x)                      (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDP_SHIFT)) & EMVSIM_PCSR_SPDP_MASK)
16502 
16503 #define EMVSIM_PCSR_SPDES_MASK                   (0x8000000U)
16504 #define EMVSIM_PCSR_SPDES_SHIFT                  (27U)
16505 /*! SPDES - SIM Presence Detect Edge Select
16506  *  0b0..Falling edge
16507  *  0b1..Rising edge
16508  */
16509 #define EMVSIM_PCSR_SPDES(x)                     (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDES_SHIFT)) & EMVSIM_PCSR_SPDES_MASK)
16510 /*! @} */
16511 
16512 /*! @name RX_BUF - Receive Data Read Buffer */
16513 /*! @{ */
16514 
16515 #define EMVSIM_RX_BUF_RX_BYTE_MASK               (0xFFU)
16516 #define EMVSIM_RX_BUF_RX_BYTE_SHIFT              (0U)
16517 /*! RX_BYTE - Receive Data Byte Read */
16518 #define EMVSIM_RX_BUF_RX_BYTE(x)                 (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_BUF_RX_BYTE_SHIFT)) & EMVSIM_RX_BUF_RX_BYTE_MASK)
16519 /*! @} */
16520 
16521 /*! @name TX_BUF - Transmit Data Buffer */
16522 /*! @{ */
16523 
16524 #define EMVSIM_TX_BUF_TX_BYTE_MASK               (0xFFU)
16525 #define EMVSIM_TX_BUF_TX_BYTE_SHIFT              (0U)
16526 /*! TX_BYTE - Transmit Data Byte */
16527 #define EMVSIM_TX_BUF_TX_BYTE(x)                 (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_BUF_TX_BYTE_SHIFT)) & EMVSIM_TX_BUF_TX_BYTE_MASK)
16528 /*! @} */
16529 
16530 /*! @name TX_GETU - Transmitter Guard ETU Value */
16531 /*! @{ */
16532 
16533 #define EMVSIM_TX_GETU_GETU_MASK                 (0xFFU)
16534 #define EMVSIM_TX_GETU_GETU_SHIFT                (0U)
16535 /*! GETU - Transmitter Guard Time Value in ETU */
16536 #define EMVSIM_TX_GETU_GETU(x)                   (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_GETU_GETU_SHIFT)) & EMVSIM_TX_GETU_GETU_MASK)
16537 /*! @} */
16538 
16539 /*! @name CWT_VAL - Character Wait Time Value */
16540 /*! @{ */
16541 
16542 #define EMVSIM_CWT_VAL_CWT_MASK                  (0xFFFFU)
16543 #define EMVSIM_CWT_VAL_CWT_SHIFT                 (0U)
16544 /*! CWT - Character Wait Time Value */
16545 #define EMVSIM_CWT_VAL_CWT(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_CWT_VAL_CWT_SHIFT)) & EMVSIM_CWT_VAL_CWT_MASK)
16546 /*! @} */
16547 
16548 /*! @name BWT_VAL - Block Wait Time Value */
16549 /*! @{ */
16550 
16551 #define EMVSIM_BWT_VAL_BWT_MASK                  (0xFFFFFFFFU)
16552 #define EMVSIM_BWT_VAL_BWT_SHIFT                 (0U)
16553 /*! BWT - Block Wait Time Value */
16554 #define EMVSIM_BWT_VAL_BWT(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_BWT_VAL_BWT_SHIFT)) & EMVSIM_BWT_VAL_BWT_MASK)
16555 /*! @} */
16556 
16557 /*! @name BGT_VAL - Block Guard Time Value */
16558 /*! @{ */
16559 
16560 #define EMVSIM_BGT_VAL_BGT_MASK                  (0xFFFFU)
16561 #define EMVSIM_BGT_VAL_BGT_SHIFT                 (0U)
16562 /*! BGT - Block Guard Time Value */
16563 #define EMVSIM_BGT_VAL_BGT(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_BGT_VAL_BGT_SHIFT)) & EMVSIM_BGT_VAL_BGT_MASK)
16564 /*! @} */
16565 
16566 /*! @name GPCNT0_VAL - General Purpose Counter 0 Timeout Value */
16567 /*! @{ */
16568 
16569 #define EMVSIM_GPCNT0_VAL_GPCNT0_MASK            (0xFFFFU)
16570 #define EMVSIM_GPCNT0_VAL_GPCNT0_SHIFT           (0U)
16571 /*! GPCNT0 - General Purpose Counter 0 Timeout Value */
16572 #define EMVSIM_GPCNT0_VAL_GPCNT0(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_GPCNT0_VAL_GPCNT0_SHIFT)) & EMVSIM_GPCNT0_VAL_GPCNT0_MASK)
16573 /*! @} */
16574 
16575 /*! @name GPCNT1_VAL - General Purpose Counter 1 Timeout Value */
16576 /*! @{ */
16577 
16578 #define EMVSIM_GPCNT1_VAL_GPCNT1_MASK            (0xFFFFU)
16579 #define EMVSIM_GPCNT1_VAL_GPCNT1_SHIFT           (0U)
16580 /*! GPCNT1 - General Purpose Counter 1 Timeout Value */
16581 #define EMVSIM_GPCNT1_VAL_GPCNT1(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_GPCNT1_VAL_GPCNT1_SHIFT)) & EMVSIM_GPCNT1_VAL_GPCNT1_MASK)
16582 /*! @} */
16583 
16584 
16585 /*!
16586  * @}
16587  */ /* end of group EMVSIM_Register_Masks */
16588 
16589 
16590 /* EMVSIM - Peripheral instance base addresses */
16591 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
16592   /** Peripheral EMVSIM0 base address */
16593   #define EMVSIM0_BASE                             (0x50103000u)
16594   /** Peripheral EMVSIM0 base address */
16595   #define EMVSIM0_BASE_NS                          (0x40103000u)
16596   /** Peripheral EMVSIM0 base pointer */
16597   #define EMVSIM0                                  ((EMVSIM_Type *)EMVSIM0_BASE)
16598   /** Peripheral EMVSIM0 base pointer */
16599   #define EMVSIM0_NS                               ((EMVSIM_Type *)EMVSIM0_BASE_NS)
16600   /** Peripheral EMVSIM1 base address */
16601   #define EMVSIM1_BASE                             (0x50104000u)
16602   /** Peripheral EMVSIM1 base address */
16603   #define EMVSIM1_BASE_NS                          (0x40104000u)
16604   /** Peripheral EMVSIM1 base pointer */
16605   #define EMVSIM1                                  ((EMVSIM_Type *)EMVSIM1_BASE)
16606   /** Peripheral EMVSIM1 base pointer */
16607   #define EMVSIM1_NS                               ((EMVSIM_Type *)EMVSIM1_BASE_NS)
16608   /** Array initializer of EMVSIM peripheral base addresses */
16609   #define EMVSIM_BASE_ADDRS                        { EMVSIM0_BASE, EMVSIM1_BASE }
16610   /** Array initializer of EMVSIM peripheral base pointers */
16611   #define EMVSIM_BASE_PTRS                         { EMVSIM0, EMVSIM1 }
16612   /** Array initializer of EMVSIM peripheral base addresses */
16613   #define EMVSIM_BASE_ADDRS_NS                     { EMVSIM0_BASE_NS, EMVSIM1_BASE_NS }
16614   /** Array initializer of EMVSIM peripheral base pointers */
16615   #define EMVSIM_BASE_PTRS_NS                      { EMVSIM0_NS, EMVSIM1_NS }
16616 #else
16617   /** Peripheral EMVSIM0 base address */
16618   #define EMVSIM0_BASE                             (0x40103000u)
16619   /** Peripheral EMVSIM0 base pointer */
16620   #define EMVSIM0                                  ((EMVSIM_Type *)EMVSIM0_BASE)
16621   /** Peripheral EMVSIM1 base address */
16622   #define EMVSIM1_BASE                             (0x40104000u)
16623   /** Peripheral EMVSIM1 base pointer */
16624   #define EMVSIM1                                  ((EMVSIM_Type *)EMVSIM1_BASE)
16625   /** Array initializer of EMVSIM peripheral base addresses */
16626   #define EMVSIM_BASE_ADDRS                        { EMVSIM0_BASE, EMVSIM1_BASE }
16627   /** Array initializer of EMVSIM peripheral base pointers */
16628   #define EMVSIM_BASE_PTRS                         { EMVSIM0, EMVSIM1 }
16629 #endif
16630 /** Interrupt vectors for the EMVSIM peripheral type */
16631 #define EMVSIM_IRQS                              { EMVSIM0_IRQn, EMVSIM1_IRQn }
16632 
16633 /*!
16634  * @}
16635  */ /* end of group EMVSIM_Peripheral_Access_Layer */
16636 
16637 
16638 /* ----------------------------------------------------------------------------
16639    -- ENET Peripheral Access Layer
16640    ---------------------------------------------------------------------------- */
16641 
16642 /*!
16643  * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer
16644  * @{
16645  */
16646 
16647 /** ENET - Register Layout Typedef */
16648 typedef struct {
16649   __IO uint32_t MAC_CONFIGURATION;                 /**< MAC Configuration, offset: 0x0 */
16650   __IO uint32_t MAC_EXT_CONFIGURATION;             /**< MAC Extended Configuration Register, offset: 0x4 */
16651   __IO uint32_t MAC_PACKET_FILTER;                 /**< MAC Packet Filter, offset: 0x8 */
16652   __IO uint32_t MAC_WATCHDOG_TIMEOUT;              /**< Watchdog Timeout, offset: 0xC */
16653        uint8_t RESERVED_0[64];
16654   __IO uint32_t MAC_VLAN_TAG_CTRL;                 /**< MAC VLAN Tag Control, offset: 0x50 */
16655        uint8_t RESERVED_1[12];
16656   __IO uint32_t MAC_VLAN_INCL;                     /**< VLAN Tag Inclusion or Replacement, offset: 0x60 */
16657   __IO uint32_t MAC_INNER_VLAN_INCL;               /**< MAC Inner VLAN Tag Inclusion or Replacement, offset: 0x64 */
16658        uint8_t RESERVED_2[8];
16659   __IO uint32_t MAC_TX_FLOW_CTRL_Q[1];             /**< MAC Q0 Tx Flow Control, array offset: 0x70, array step: 0x4 */
16660        uint8_t RESERVED_3[28];
16661   __IO uint32_t MAC_RX_FLOW_CTRL;                  /**< MAC Rx Flow Control, offset: 0x90 */
16662   __IO uint32_t MAC_RXQ_CTRL4;                     /**< Receive Queue Control 4, offset: 0x94 */
16663        uint8_t RESERVED_4[8];
16664   __IO uint32_t MAC_RXQ_CTRL[3];                   /**< Receive Queue Control 0..Receive Queue Control 2, array offset: 0xA0, array step: 0x4 */
16665        uint8_t RESERVED_5[4];
16666   __I  uint32_t MAC_INTERRUPT_STATUS;              /**< Interrupt Status, offset: 0xB0 */
16667   __IO uint32_t MAC_INTERRUPT_ENABLE;              /**< Interrupt Enable, offset: 0xB4 */
16668   __I  uint32_t MAC_RX_TX_STATUS;                  /**< Receive Transmit Status, offset: 0xB8 */
16669        uint8_t RESERVED_6[4];
16670   __IO uint32_t MAC_PMT_CONTROL_STATUS;            /**< PMT Control and Status, offset: 0xC0 */
16671   __IO uint32_t MAC_RWK_PACKET_FILTER;             /**< Remote Wakeup Filter, offset: 0xC4 */
16672        uint8_t RESERVED_7[8];
16673   __IO uint32_t MAC_LPI_CONTROL_STATUS;            /**< LPI Control and Status, offset: 0xD0 */
16674   __IO uint32_t MAC_LPI_TIMERS_CONTROL;            /**< LPI Timers Control, offset: 0xD4 */
16675   __IO uint32_t MAC_LPI_ENTRY_TIMER;               /**< Tx LPI Entry Timer Control, offset: 0xD8 */
16676   __IO uint32_t MAC_ONEUS_TIC_COUNTER;             /**< One-microsecond Reference Timer, offset: 0xDC */
16677        uint8_t RESERVED_8[48];
16678   __I  uint32_t MAC_VERSION;                       /**< MAC Version, offset: 0x110 */
16679   __I  uint32_t MAC_DEBUG;                         /**< MAC Debug, offset: 0x114 */
16680        uint8_t RESERVED_9[4];
16681   __I  uint32_t MAC_HW_FEAT[4];                    /**< Hardware Features 0..Hardware Features 3, array offset: 0x11C, array step: 0x4 */
16682        uint8_t RESERVED_10[212];
16683   __IO uint32_t MAC_MDIO_ADDRESS;                  /**< MDIO Address, offset: 0x200 */
16684   __IO uint32_t MAC_MDIO_DATA;                     /**< MAC MDIO Data, offset: 0x204 */
16685        uint8_t RESERVED_11[40];
16686   __IO uint32_t MAC_CSR_SW_CTRL;                   /**< CSR Software Control, offset: 0x230 */
16687        uint8_t RESERVED_12[204];
16688   __IO uint32_t MAC_ADDRESS0_HIGH;                 /**< MAC Address0 High, offset: 0x300 */
16689   __IO uint32_t MAC_ADDRESS0_LOW;                  /**< MAC Address0 Low, offset: 0x304 */
16690        uint8_t RESERVED_13[1896];
16691   __IO uint32_t INDIR_ACCESS_CTRL;                 /**< Indirect Access Control, offset: 0xA70 */
16692   __IO uint32_t INDIR_ACCESS_DATA;                 /**< Indirect Access Data, offset: 0xA74 */
16693        uint8_t RESERVED_14[136];
16694   __IO uint32_t MAC_TIMESTAMP_CONTROL;             /**< Timestamp Control, offset: 0xB00 */
16695   __IO uint32_t MAC_SUB_SECOND_INCREMENT;          /**< Subsecond Increment, offset: 0xB04 */
16696   __I  uint32_t MAC_SYSTEM_TIME_SECONDS;           /**< System Time Seconds, offset: 0xB08 */
16697   __I  uint32_t MAC_SYSTEM_TIME_NANOSECONDS;       /**< System Time Nanoseconds, offset: 0xB0C */
16698   __IO uint32_t MAC_SYSTEM_TIME_SECONDS_UPDATE;    /**< System Time Seconds Update, offset: 0xB10 */
16699   __IO uint32_t MAC_SYSTEM_TIME_NANOSECONDS_UPDATE; /**< System Time Nanoseconds Update, offset: 0xB14 */
16700   __IO uint32_t MAC_TIMESTAMP_ADDEND;              /**< Timestamp Addend, offset: 0xB18 */
16701        uint8_t RESERVED_15[4];
16702   __I  uint32_t MAC_TIMESTAMP_STATUS;              /**< Timestamp Status, offset: 0xB20 */
16703        uint8_t RESERVED_16[12];
16704   __I  uint32_t MAC_TX_TIMESTAMP_STATUS_NANOSECONDS; /**< Transmit Timestamp Status Nanoseconds, offset: 0xB30 */
16705   __I  uint32_t MAC_TX_TIMESTAMP_STATUS_SECONDS;   /**< Transmit Timestamp Status Seconds, offset: 0xB34 */
16706        uint8_t RESERVED_17[32];
16707   __IO uint32_t MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND; /**< Timestamp Ingress Correction Nanosecond, offset: 0xB58 */
16708   __IO uint32_t MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND; /**< Timestamp Egress Correction Nanosecond, offset: 0xB5C */
16709        uint8_t RESERVED_18[8];
16710   __I  uint32_t MAC_TIMESTAMP_INGRESS_LATENCY;     /**< Timestamp Ingress Latency, offset: 0xB68 */
16711   __I  uint32_t MAC_TIMESTAMP_EGRESS_LATENCY;      /**< Timestamp Egress Latency, offset: 0xB6C */
16712   __IO uint32_t MAC_PPS_CONTROL;                   /**< PPS Control, offset: 0xB70 */
16713        uint8_t RESERVED_19[12];
16714   __IO uint32_t PPS0_TARGET_TIME_SECONDS;          /**< PPS0 Target Time Seconds, offset: 0xB80 */
16715   __IO uint32_t PPS0_TARGET_TIME_NANOSECONDS;      /**< PPS0 Target Time Nanoseconds, offset: 0xB84 */
16716        uint8_t RESERVED_20[120];
16717   __IO uint32_t MTL_OPERATION_MODE;                /**< MTL Operation Mode, offset: 0xC00 */
16718        uint8_t RESERVED_21[28];
16719   __I  uint32_t MTL_INTERRUPT_STATUS;              /**< MTL Interrupt Status, offset: 0xC20 */
16720        uint8_t RESERVED_22[12];
16721   __IO uint32_t MTL_RXQ_DMA_MAP0;                  /**< Receive Queue and DMA Channel Mapping 0, offset: 0xC30 */
16722        uint8_t RESERVED_23[204];
16723   struct {                                         /* offset: 0xD00, array step: 0x40 */
16724     __IO uint32_t MTL_TXQX_OP_MODE;                  /**< Queue 0 Transmit Operation Mode..Queue 1 Transmit Operation Mode, array offset: 0xD00, array step: 0x40 */
16725     __I  uint32_t MTL_TXQX_UNDRFLW;                  /**< Queue 0 Underflow Counter..Queue 1 Underflow Counter, array offset: 0xD04, array step: 0x40 */
16726     __I  uint32_t MTL_TXQX_DBG;                      /**< Queue 0 Transmit Debug..Queue 1 Transmit Debug, array offset: 0xD08, array step: 0x40 */
16727          uint8_t RESERVED_0[4];
16728     __IO uint32_t MTL_TXQX_ETS_CTRL;                 /**< Queue 1 ETS Control, array offset: 0xD10, array step: 0x40, valid indices: [1] */
16729     __I  uint32_t MTL_TXQX_ETS_STAT;                 /**< Queue 0 ETS Status..Queue 1 ETS Status, array offset: 0xD14, array step: 0x40 */
16730     __IO uint32_t MTL_TXQX_QNTM_WGHT;                /**< Queue 0 Quantum or Weights..Queue 1 idleSlopeCredit, Quantum or Weights, array offset: 0xD18, array step: 0x40 */
16731     __IO uint32_t MTL_TXQX_SNDSLP_CRDT;              /**< Queue 1 sendSlopeCredit, array offset: 0xD1C, array step: 0x40, valid indices: [1] */
16732     __IO uint32_t MTL_TXQX_HI_CRDT;                  /**< Queue 1 hiCredit, array offset: 0xD20, array step: 0x40, valid indices: [1] */
16733     __IO uint32_t MTL_TXQX_LO_CRDT;                  /**< Queue 1 loCredit, array offset: 0xD24, array step: 0x40, valid indices: [1] */
16734          uint8_t RESERVED_1[4];
16735     __IO uint32_t MTL_QX_INTCTRL_STAT;               /**< Queue 0 Interrupt Control Status..Queue 1 Interrupt Control Status, array offset: 0xD2C, array step: 0x40 */
16736     __IO uint32_t MTL_RXQX_OP_MODE;                  /**< Queue 0 Receive Operation Mode..Queue 1 Receive Operation Mode, array offset: 0xD30, array step: 0x40 */
16737     __I  uint32_t MTL_RXQX_MISSPKT_OVRFLW_CNT;       /**< Queue 0 Missed Packet and Overflow Counter..Queue 1 Missed Packet and Overflow Counter, array offset: 0xD34, array step: 0x40 */
16738     __I  uint32_t MTL_RXQX_DBG;                      /**< Queue 0 Receive Debug..Queue 1 Receive Debug, array offset: 0xD38, array step: 0x40 */
16739     __IO uint32_t MTL_RXQX_CTRL;                     /**< Queue 0 Receive Control..Queue 1 Receive Control, array offset: 0xD3C, array step: 0x40 */
16740   } MTL_QUEUE[2];
16741        uint8_t RESERVED_24[640];
16742   __IO uint32_t DMA_MODE;                          /**< DMA Bus Mode, offset: 0x1000 */
16743   __IO uint32_t DMA_SYSBUS_MODE;                   /**< DMA System Bus Mode, offset: 0x1004 */
16744   __I  uint32_t DMA_INTERRUPT_STATUS;              /**< DMA Interrupt Status, offset: 0x1008 */
16745   __I  uint32_t DMA_DEBUG_STATUS0;                 /**< DMA Debug Status 0, offset: 0x100C */
16746        uint8_t RESERVED_25[240];
16747   struct {                                         /* offset: 0x1100, array step: 0x80 */
16748     __IO uint32_t DMA_CHX_CTRL;                      /**< DMA Channel 0 Control..DMA Channel 1 Control, array offset: 0x1100, array step: 0x80 */
16749     __IO uint32_t DMA_CHX_TX_CTRL;                   /**< DMA Channel 0 Transmit Control..DMA Channel 1 Transmit Control, array offset: 0x1104, array step: 0x80 */
16750     __IO uint32_t DMA_CHX_RX_CTRL;                   /**< DMA Channel 0 Receive Control..DMA Channel 1 Receive Control, array offset: 0x1108, array step: 0x80 */
16751          uint8_t RESERVED_0[8];
16752     __IO uint32_t DMA_CHX_TXDESC_LIST_ADDR;          /**< Channel 0 Tx Descriptor List Address register..Channel 1 Tx Descriptor List Address, array offset: 0x1114, array step: 0x80 */
16753          uint8_t RESERVED_1[4];
16754     __IO uint32_t DMA_CHX_RXDESC_LIST_ADDR;          /**< Channel 0 Rx Descriptor List Address register..Channel 1 Rx Descriptor List Address, array offset: 0x111C, array step: 0x80 */
16755     __IO uint32_t DMA_CHX_TXDESC_TAIL_PTR;           /**< Channel 0 Tx Descriptor Tail Pointer..Channel 1 Tx Descriptor Tail Pointer, array offset: 0x1120, array step: 0x80 */
16756          uint8_t RESERVED_2[4];
16757     __IO uint32_t DMA_CHX_RXDESC_TAIL_PTR;           /**< Channel 0 Rx Descriptor Tail Pointer..Channel 1 Rx Descriptor Tail Pointer, array offset: 0x1128, array step: 0x80 */
16758     __IO uint32_t DMA_CHX_TXDESC_RING_LENGTH;        /**< Channel 0 Tx Descriptor Ring Length..Channel 1 Tx Descriptor Ring Length, array offset: 0x112C, array step: 0x80 */
16759     __IO uint32_t DMA_CHX_RX_CONTROL2;               /**< Channeli Receive Control..DMA Channel 1 Receive Control, array offset: 0x1130, array step: 0x80 */
16760     __IO uint32_t DMA_CHX_INT_EN;                    /**< Channeli Interrupt Enable..Channel 1 Interrupt Enable, array offset: 0x1134, array step: 0x80 */
16761     __IO uint32_t DMA_CHX_RX_INT_WDTIMER;            /**< Channel 0 Receive Interrupt Watchdog Timer..Channel 1 Receive Interrupt Watchdog Timer, array offset: 0x1138, array step: 0x80 */
16762     __IO uint32_t DMA_CHX_SLOT_FUNC_CTRL_STAT;       /**< Channel 0 Slot Function Control and Status..Channel 1 Slot Function Control and Status, array offset: 0x113C, array step: 0x80 */
16763          uint8_t RESERVED_3[4];
16764     __I  uint32_t DMA_CHX_CUR_HST_TXDESC;            /**< Channel 0 Current Application Transmit Descriptor..Channel 1 Current Application Transmit Descriptor, array offset: 0x1144, array step: 0x80 */
16765          uint8_t RESERVED_4[4];
16766     __I  uint32_t DMA_CHX_CUR_HST_RXDESC;            /**< Channel 0 Current Application Receive Descriptor..Channel 1 Current Application Receive Descriptor, array offset: 0x114C, array step: 0x80 */
16767          uint8_t RESERVED_5[4];
16768     __I  uint32_t DMA_CHX_CUR_HST_TXBUF;             /**< Channel 0 Current Application Transmit Buffer Address..Channel 1 Current Application Transmit Buffer Address, array offset: 0x1154, array step: 0x80 */
16769          uint8_t RESERVED_6[4];
16770     __I  uint32_t DMA_CHX_CUR_HST_RXBUF;             /**< Channel 0 Current Application Receive Buffer Address..Channel 1 Current Application Receive Buffer Address, array offset: 0x115C, array step: 0x80 */
16771     __IO uint32_t DMA_CHX_STAT;                      /**< DMA Channel 0 Status..DMA Channel 1 Status, array offset: 0x1160, array step: 0x80 */
16772     __I  uint32_t DMA_CHX_MISS_FRAME_CNT;            /**< Channel 0 Missed Frame Counter..Channel 1 Missed Frame Counter, array offset: 0x1164, array step: 0x80 */
16773          uint8_t RESERVED_7[4];
16774     __I  uint32_t DMA_CHX_RX_ERI_CNT;                /**< Channel 0 Receive ERI Counter..Channel 1 Receive ERI Counter, array offset: 0x116C, array step: 0x80 */
16775          uint8_t RESERVED_8[16];
16776   } DMA_CH[2];
16777 } ENET_Type;
16778 
16779 /* ----------------------------------------------------------------------------
16780    -- ENET Register Masks
16781    ---------------------------------------------------------------------------- */
16782 
16783 /*!
16784  * @addtogroup ENET_Register_Masks ENET Register Masks
16785  * @{
16786  */
16787 
16788 /*! @name MAC_CONFIGURATION - MAC Configuration */
16789 /*! @{ */
16790 
16791 #define ENET_MAC_CONFIGURATION_RE_MASK           (0x1U)
16792 #define ENET_MAC_CONFIGURATION_RE_SHIFT          (0U)
16793 /*! RE - Receiver Enable
16794  *  0b0..Receiver is disabled
16795  *  0b1..Receiver is enabled
16796  */
16797 #define ENET_MAC_CONFIGURATION_RE(x)             (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIGURATION_RE_SHIFT)) & ENET_MAC_CONFIGURATION_RE_MASK)
16798 
16799 #define ENET_MAC_CONFIGURATION_TE_MASK           (0x2U)
16800 #define ENET_MAC_CONFIGURATION_TE_SHIFT          (1U)
16801 /*! TE - Transmitter Enable
16802  *  0b0..Transmitter is disabled
16803  *  0b1..Transmitter is enabled
16804  */
16805 #define ENET_MAC_CONFIGURATION_TE(x)             (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIGURATION_TE_SHIFT)) & ENET_MAC_CONFIGURATION_TE_MASK)
16806 
16807 #define ENET_MAC_CONFIGURATION_PRELEN_MASK       (0xCU)
16808 #define ENET_MAC_CONFIGURATION_PRELEN_SHIFT      (2U)
16809 /*! PRELEN - Preamble Length for Transmit packets
16810  *  0b10..3 bytes of preamble
16811  *  0b01..5 bytes of preamble
16812  *  0b00..7 bytes of preamble
16813  *  0b11..Reserved
16814  */
16815 #define ENET_MAC_CONFIGURATION_PRELEN(x)         (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIGURATION_PRELEN_SHIFT)) & ENET_MAC_CONFIGURATION_PRELEN_MASK)
16816 
16817 #define ENET_MAC_CONFIGURATION_DC_MASK           (0x10U)
16818 #define ENET_MAC_CONFIGURATION_DC_SHIFT          (4U)
16819 /*! DC - Deferral Check
16820  *  0b0..Deferral check function is disabled
16821  *  0b1..Deferral check function is enabled
16822  */
16823 #define ENET_MAC_CONFIGURATION_DC(x)             (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIGURATION_DC_SHIFT)) & ENET_MAC_CONFIGURATION_DC_MASK)
16824 
16825 #define ENET_MAC_CONFIGURATION_BL_MASK           (0x60U)
16826 #define ENET_MAC_CONFIGURATION_BL_SHIFT          (5U)
16827 /*! BL - Back-Off Limit
16828  *  0b11..k = min(n,1)
16829  *  0b00..k = min(n,10)
16830  *  0b10..k = min(n,4)
16831  *  0b01..k = min(n,8)
16832  */
16833 #define ENET_MAC_CONFIGURATION_BL(x)             (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIGURATION_BL_SHIFT)) & ENET_MAC_CONFIGURATION_BL_MASK)
16834 
16835 #define ENET_MAC_CONFIGURATION_DR_MASK           (0x100U)
16836 #define ENET_MAC_CONFIGURATION_DR_SHIFT          (8U)
16837 /*! DR - Disable Retry
16838  *  0b1..Disable Retry
16839  *  0b0..Enable Retry
16840  */
16841 #define ENET_MAC_CONFIGURATION_DR(x)             (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIGURATION_DR_SHIFT)) & ENET_MAC_CONFIGURATION_DR_MASK)
16842 
16843 #define ENET_MAC_CONFIGURATION_DCRS_MASK         (0x200U)
16844 #define ENET_MAC_CONFIGURATION_DCRS_SHIFT        (9U)
16845 /*! DCRS - Disable Carrier Sense During Transmission
16846  *  0b1..Disable Carrier Sense During Transmission
16847  *  0b0..Enable Carrier Sense During Transmission
16848  */
16849 #define ENET_MAC_CONFIGURATION_DCRS(x)           (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIGURATION_DCRS_SHIFT)) & ENET_MAC_CONFIGURATION_DCRS_MASK)
16850 
16851 #define ENET_MAC_CONFIGURATION_DO_MASK           (0x400U)
16852 #define ENET_MAC_CONFIGURATION_DO_SHIFT          (10U)
16853 /*! DO - Disable Receive Own
16854  *  0b1..Disable Receive Own
16855  *  0b0..Enable Receive Own
16856  */
16857 #define ENET_MAC_CONFIGURATION_DO(x)             (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIGURATION_DO_SHIFT)) & ENET_MAC_CONFIGURATION_DO_MASK)
16858 
16859 #define ENET_MAC_CONFIGURATION_ECRSFD_MASK       (0x800U)
16860 #define ENET_MAC_CONFIGURATION_ECRSFD_SHIFT      (11U)
16861 /*! ECRSFD - Enable Carrier Sense Before Transmission in Full-Duplex Mode
16862  *  0b0..ECRSFD is disabled
16863  *  0b1..ECRSFD is enabled
16864  */
16865 #define ENET_MAC_CONFIGURATION_ECRSFD(x)         (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIGURATION_ECRSFD_SHIFT)) & ENET_MAC_CONFIGURATION_ECRSFD_MASK)
16866 
16867 #define ENET_MAC_CONFIGURATION_LM_MASK           (0x1000U)
16868 #define ENET_MAC_CONFIGURATION_LM_SHIFT          (12U)
16869 /*! LM - Loopback Mode
16870  *  0b0..Loopback is disabled
16871  *  0b1..Loopback is enabled
16872  */
16873 #define ENET_MAC_CONFIGURATION_LM(x)             (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIGURATION_LM_SHIFT)) & ENET_MAC_CONFIGURATION_LM_MASK)
16874 
16875 #define ENET_MAC_CONFIGURATION_DM_MASK           (0x2000U)
16876 #define ENET_MAC_CONFIGURATION_DM_SHIFT          (13U)
16877 /*! DM - Duplex Mode
16878  *  0b1..Full-duplex mode
16879  *  0b0..Half-duplex mode
16880  */
16881 #define ENET_MAC_CONFIGURATION_DM(x)             (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIGURATION_DM_SHIFT)) & ENET_MAC_CONFIGURATION_DM_MASK)
16882 
16883 #define ENET_MAC_CONFIGURATION_FES_MASK          (0x4000U)
16884 #define ENET_MAC_CONFIGURATION_FES_SHIFT         (14U)
16885 /*! FES - Speed
16886  *  0b1..100 Mbps when PS bit is 1 and 2.5 Gbps when PS bit is 0
16887  *  0b0..10 Mbps when PS bit is 1 and 1 Gbps when PS bit is 0
16888  */
16889 #define ENET_MAC_CONFIGURATION_FES(x)            (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIGURATION_FES_SHIFT)) & ENET_MAC_CONFIGURATION_FES_MASK)
16890 
16891 #define ENET_MAC_CONFIGURATION_PS_MASK           (0x8000U)
16892 #define ENET_MAC_CONFIGURATION_PS_SHIFT          (15U)
16893 /*! PS - Port Select
16894  *  0b0..For 1000 or 2500 Mbps operations
16895  *  0b1..For 10 or 100 Mbps operations
16896  */
16897 #define ENET_MAC_CONFIGURATION_PS(x)             (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIGURATION_PS_SHIFT)) & ENET_MAC_CONFIGURATION_PS_MASK)
16898 
16899 #define ENET_MAC_CONFIGURATION_JE_MASK           (0x10000U)
16900 #define ENET_MAC_CONFIGURATION_JE_SHIFT          (16U)
16901 /*! JE - Jumbo Packet Enable
16902  *  0b0..Jumbo packet is disabled
16903  *  0b1..Jumbo packet is enabled
16904  */
16905 #define ENET_MAC_CONFIGURATION_JE(x)             (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIGURATION_JE_SHIFT)) & ENET_MAC_CONFIGURATION_JE_MASK)
16906 
16907 #define ENET_MAC_CONFIGURATION_JD_MASK           (0x20000U)
16908 #define ENET_MAC_CONFIGURATION_JD_SHIFT          (17U)
16909 /*! JD - Jabber Disable
16910  *  0b1..Jabber is disabled
16911  *  0b0..Jabber is enabled
16912  */
16913 #define ENET_MAC_CONFIGURATION_JD(x)             (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIGURATION_JD_SHIFT)) & ENET_MAC_CONFIGURATION_JD_MASK)
16914 
16915 #define ENET_MAC_CONFIGURATION_WD_MASK           (0x80000U)
16916 #define ENET_MAC_CONFIGURATION_WD_SHIFT          (19U)
16917 /*! WD - Watchdog Disable
16918  *  0b1..Watchdog is disabled
16919  *  0b0..Watchdog is enabled
16920  */
16921 #define ENET_MAC_CONFIGURATION_WD(x)             (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIGURATION_WD_SHIFT)) & ENET_MAC_CONFIGURATION_WD_MASK)
16922 
16923 #define ENET_MAC_CONFIGURATION_ACS_MASK          (0x100000U)
16924 #define ENET_MAC_CONFIGURATION_ACS_SHIFT         (20U)
16925 /*! ACS - Automatic Pad or CRC Stripping
16926  *  0b0..Automatic Pad or CRC Stripping is disabled
16927  *  0b1..Automatic Pad or CRC Stripping is enabled
16928  */
16929 #define ENET_MAC_CONFIGURATION_ACS(x)            (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIGURATION_ACS_SHIFT)) & ENET_MAC_CONFIGURATION_ACS_MASK)
16930 
16931 #define ENET_MAC_CONFIGURATION_CST_MASK          (0x200000U)
16932 #define ENET_MAC_CONFIGURATION_CST_SHIFT         (21U)
16933 /*! CST - CRC stripping for Type packets
16934  *  0b0..CRC stripping for Type packets is disabled
16935  *  0b1..CRC stripping for Type packets is enabled
16936  */
16937 #define ENET_MAC_CONFIGURATION_CST(x)            (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIGURATION_CST_SHIFT)) & ENET_MAC_CONFIGURATION_CST_MASK)
16938 
16939 #define ENET_MAC_CONFIGURATION_S2KP_MASK         (0x400000U)
16940 #define ENET_MAC_CONFIGURATION_S2KP_SHIFT        (22U)
16941 /*! S2KP - IEEE 802.3as Support for 2K Packets
16942  *  0b0..Support upto 2K packet is disabled
16943  *  0b1..Support upto 2K packet is Enabled
16944  */
16945 #define ENET_MAC_CONFIGURATION_S2KP(x)           (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIGURATION_S2KP_SHIFT)) & ENET_MAC_CONFIGURATION_S2KP_MASK)
16946 
16947 #define ENET_MAC_CONFIGURATION_GPSLCE_MASK       (0x800000U)
16948 #define ENET_MAC_CONFIGURATION_GPSLCE_SHIFT      (23U)
16949 /*! GPSLCE - Giant Packet Size Limit Control Enable
16950  *  0b0..Giant Packet Size Limit Control is disabled
16951  *  0b1..Giant Packet Size Limit Control is enabled
16952  */
16953 #define ENET_MAC_CONFIGURATION_GPSLCE(x)         (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIGURATION_GPSLCE_SHIFT)) & ENET_MAC_CONFIGURATION_GPSLCE_MASK)
16954 
16955 #define ENET_MAC_CONFIGURATION_IPG_MASK          (0x7000000U)
16956 #define ENET_MAC_CONFIGURATION_IPG_SHIFT         (24U)
16957 /*! IPG - Inter-Packet Gap
16958  *  0b111..40 bit times IPG
16959  *  0b110..48 bit times IPG
16960  *  0b101..56 bit times IPG
16961  *  0b100..64 bit times IPG
16962  *  0b011..72 bit times IPG
16963  *  0b010..80 bit times IPG
16964  *  0b001..88 bit times IPG
16965  *  0b000..96 bit times IPG
16966  */
16967 #define ENET_MAC_CONFIGURATION_IPG(x)            (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIGURATION_IPG_SHIFT)) & ENET_MAC_CONFIGURATION_IPG_MASK)
16968 
16969 #define ENET_MAC_CONFIGURATION_IPC_MASK          (0x8000000U)
16970 #define ENET_MAC_CONFIGURATION_IPC_SHIFT         (27U)
16971 /*! IPC - Checksum Offload
16972  *  0b0..IP header/payload checksum checking is disabled
16973  *  0b1..IP header/payload checksum checking is enabled
16974  */
16975 #define ENET_MAC_CONFIGURATION_IPC(x)            (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIGURATION_IPC_SHIFT)) & ENET_MAC_CONFIGURATION_IPC_MASK)
16976 
16977 #define ENET_MAC_CONFIGURATION_SARC_MASK         (0x70000000U)
16978 #define ENET_MAC_CONFIGURATION_SARC_SHIFT        (28U)
16979 /*! SARC - Source Address Insertion or Replacement Control
16980  *  0b010..Contents of MAC Addr-0 inserted in SA field
16981  *  0b011..Contents of MAC Addr-0 replaces SA field
16982  *  0b110..Contents of MAC Addr-1 inserted in SA field
16983  *  0b111..Contents of MAC Addr-1 replaces SA field
16984  *  0b000..mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation
16985  */
16986 #define ENET_MAC_CONFIGURATION_SARC(x)           (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIGURATION_SARC_SHIFT)) & ENET_MAC_CONFIGURATION_SARC_MASK)
16987 /*! @} */
16988 
16989 /*! @name MAC_EXT_CONFIGURATION - MAC Extended Configuration Register */
16990 /*! @{ */
16991 
16992 #define ENET_MAC_EXT_CONFIGURATION_GPSL_MASK     (0x3FFFU)
16993 #define ENET_MAC_EXT_CONFIGURATION_GPSL_SHIFT    (0U)
16994 /*! GPSL - Giant Packet Size Limit */
16995 #define ENET_MAC_EXT_CONFIGURATION_GPSL(x)       (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIGURATION_GPSL_SHIFT)) & ENET_MAC_EXT_CONFIGURATION_GPSL_MASK)
16996 
16997 #define ENET_MAC_EXT_CONFIGURATION_DCRCC_MASK    (0x10000U)
16998 #define ENET_MAC_EXT_CONFIGURATION_DCRCC_SHIFT   (16U)
16999 /*! DCRCC - Disable CRC Checking for Received Packets
17000  *  0b1..CRC Checking is disabled
17001  *  0b0..CRC Checking is enabled
17002  */
17003 #define ENET_MAC_EXT_CONFIGURATION_DCRCC(x)      (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIGURATION_DCRCC_SHIFT)) & ENET_MAC_EXT_CONFIGURATION_DCRCC_MASK)
17004 
17005 #define ENET_MAC_EXT_CONFIGURATION_SPEN_MASK     (0x20000U)
17006 #define ENET_MAC_EXT_CONFIGURATION_SPEN_SHIFT    (17U)
17007 /*! SPEN - Slow Protocol Detection Enable
17008  *  0b0..Slow Protocol Detection is disabled
17009  *  0b1..Slow Protocol Detection is enabled
17010  */
17011 #define ENET_MAC_EXT_CONFIGURATION_SPEN(x)       (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIGURATION_SPEN_SHIFT)) & ENET_MAC_EXT_CONFIGURATION_SPEN_MASK)
17012 
17013 #define ENET_MAC_EXT_CONFIGURATION_USP_MASK      (0x40000U)
17014 #define ENET_MAC_EXT_CONFIGURATION_USP_SHIFT     (18U)
17015 /*! USP - Unicast Slow Protocol Packet Detect
17016  *  0b0..Unicast Slow Protocol Packet Detection is disabled
17017  *  0b1..Unicast Slow Protocol Packet Detection is enabled
17018  */
17019 #define ENET_MAC_EXT_CONFIGURATION_USP(x)        (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIGURATION_USP_SHIFT)) & ENET_MAC_EXT_CONFIGURATION_USP_MASK)
17020 
17021 #define ENET_MAC_EXT_CONFIGURATION_PDC_MASK      (0x80000U)
17022 #define ENET_MAC_EXT_CONFIGURATION_PDC_SHIFT     (19U)
17023 /*! PDC - Packet Duplication Control
17024  *  0b0..Packet Duplication Control is disabled
17025  *  0b1..Packet Duplication Control is enabled
17026  */
17027 #define ENET_MAC_EXT_CONFIGURATION_PDC(x)        (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIGURATION_PDC_SHIFT)) & ENET_MAC_EXT_CONFIGURATION_PDC_MASK)
17028 
17029 #define ENET_MAC_EXT_CONFIGURATION_EIPGEN_MASK   (0x1000000U)
17030 #define ENET_MAC_EXT_CONFIGURATION_EIPGEN_SHIFT  (24U)
17031 /*! EIPGEN - Extended Inter-Packet Gap Enable
17032  *  0b0..Extended Inter-Packet Gap is disabled
17033  *  0b1..Extended Inter-Packet Gap is enabled
17034  */
17035 #define ENET_MAC_EXT_CONFIGURATION_EIPGEN(x)     (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIGURATION_EIPGEN_SHIFT)) & ENET_MAC_EXT_CONFIGURATION_EIPGEN_MASK)
17036 
17037 #define ENET_MAC_EXT_CONFIGURATION_EIPG_MASK     (0x3E000000U)
17038 #define ENET_MAC_EXT_CONFIGURATION_EIPG_SHIFT    (25U)
17039 /*! EIPG - Extended Inter-Packet Gap */
17040 #define ENET_MAC_EXT_CONFIGURATION_EIPG(x)       (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIGURATION_EIPG_SHIFT)) & ENET_MAC_EXT_CONFIGURATION_EIPG_MASK)
17041 /*! @} */
17042 
17043 /*! @name MAC_PACKET_FILTER - MAC Packet Filter */
17044 /*! @{ */
17045 
17046 #define ENET_MAC_PACKET_FILTER_PR_MASK           (0x1U)
17047 #define ENET_MAC_PACKET_FILTER_PR_SHIFT          (0U)
17048 /*! PR - Promiscuous Mode
17049  *  0b0..Promiscuous Mode is disabled
17050  *  0b1..Promiscuous Mode is enabled
17051  */
17052 #define ENET_MAC_PACKET_FILTER_PR(x)             (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PACKET_FILTER_PR_SHIFT)) & ENET_MAC_PACKET_FILTER_PR_MASK)
17053 
17054 #define ENET_MAC_PACKET_FILTER_DAIF_MASK         (0x8U)
17055 #define ENET_MAC_PACKET_FILTER_DAIF_SHIFT        (3U)
17056 /*! DAIF - DA Inverse Filtering
17057  *  0b0..DA Inverse Filtering is disabled
17058  *  0b1..DA Inverse Filtering is enabled
17059  */
17060 #define ENET_MAC_PACKET_FILTER_DAIF(x)           (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PACKET_FILTER_DAIF_SHIFT)) & ENET_MAC_PACKET_FILTER_DAIF_MASK)
17061 
17062 #define ENET_MAC_PACKET_FILTER_PM_MASK           (0x10U)
17063 #define ENET_MAC_PACKET_FILTER_PM_SHIFT          (4U)
17064 /*! PM - Pass All Multicast
17065  *  0b0..Pass All Multicast is disabled
17066  *  0b1..Pass All Multicast is enabled
17067  */
17068 #define ENET_MAC_PACKET_FILTER_PM(x)             (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PACKET_FILTER_PM_SHIFT)) & ENET_MAC_PACKET_FILTER_PM_MASK)
17069 
17070 #define ENET_MAC_PACKET_FILTER_DBF_MASK          (0x20U)
17071 #define ENET_MAC_PACKET_FILTER_DBF_SHIFT         (5U)
17072 /*! DBF - Disable Broadcast Packets
17073  *  0b1..Disable Broadcast Packets
17074  *  0b0..Enable Broadcast Packets
17075  */
17076 #define ENET_MAC_PACKET_FILTER_DBF(x)            (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PACKET_FILTER_DBF_SHIFT)) & ENET_MAC_PACKET_FILTER_DBF_MASK)
17077 
17078 #define ENET_MAC_PACKET_FILTER_PCF_MASK          (0xC0U)
17079 #define ENET_MAC_PACKET_FILTER_PCF_SHIFT         (6U)
17080 /*! PCF - Pass Control Packets
17081  *  0b00..MAC filters all control packets from reaching the application
17082  *  0b10..MAC forwards all control packets to the application even if they fail the address filter
17083  *  0b11..MAC forwards the control packets that pass the Address filter
17084  *  0b01..MAC forwards all control packets except Pause packets to the application even if they fail the address filter
17085  */
17086 #define ENET_MAC_PACKET_FILTER_PCF(x)            (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PACKET_FILTER_PCF_SHIFT)) & ENET_MAC_PACKET_FILTER_PCF_MASK)
17087 
17088 #define ENET_MAC_PACKET_FILTER_VTFE_MASK         (0x10000U)
17089 #define ENET_MAC_PACKET_FILTER_VTFE_SHIFT        (16U)
17090 /*! VTFE - VLAN Tag Filter Enable
17091  *  0b0..VLAN Tag Filter is disabled
17092  *  0b1..VLAN Tag Filter is enabled
17093  */
17094 #define ENET_MAC_PACKET_FILTER_VTFE(x)           (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PACKET_FILTER_VTFE_SHIFT)) & ENET_MAC_PACKET_FILTER_VTFE_MASK)
17095 
17096 #define ENET_MAC_PACKET_FILTER_RA_MASK           (0x80000000U)
17097 #define ENET_MAC_PACKET_FILTER_RA_SHIFT          (31U)
17098 /*! RA - Receive All
17099  *  0b0..Receive All is disabled
17100  *  0b1..Receive All is enabled
17101  */
17102 #define ENET_MAC_PACKET_FILTER_RA(x)             (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PACKET_FILTER_RA_SHIFT)) & ENET_MAC_PACKET_FILTER_RA_MASK)
17103 /*! @} */
17104 
17105 /*! @name MAC_WATCHDOG_TIMEOUT - Watchdog Timeout */
17106 /*! @{ */
17107 
17108 #define ENET_MAC_WATCHDOG_TIMEOUT_WTO_MASK       (0xFU)
17109 #define ENET_MAC_WATCHDOG_TIMEOUT_WTO_SHIFT      (0U)
17110 /*! WTO - Watchdog Timeout
17111  *  0b1000..10 KB
17112  *  0b1001..11 KB
17113  *  0b1010..12 KB
17114  *  0b1011..13 KB
17115  *  0b1100..14 KB
17116  *  0b1101..15 KB
17117  *  0b1110..16383 Bytes
17118  *  0b0000..2 KB
17119  *  0b0001..3 KB
17120  *  0b0010..4 KB
17121  *  0b0011..5 KB
17122  *  0b0100..6 KB
17123  *  0b0101..7 KB
17124  *  0b0110..8 KB
17125  *  0b0111..9 KB
17126  *  0b1111..Reserved
17127  */
17128 #define ENET_MAC_WATCHDOG_TIMEOUT_WTO(x)         (((uint32_t)(((uint32_t)(x)) << ENET_MAC_WATCHDOG_TIMEOUT_WTO_SHIFT)) & ENET_MAC_WATCHDOG_TIMEOUT_WTO_MASK)
17129 
17130 #define ENET_MAC_WATCHDOG_TIMEOUT_PWE_MASK       (0x100U)
17131 #define ENET_MAC_WATCHDOG_TIMEOUT_PWE_SHIFT      (8U)
17132 /*! PWE - Programmable Watchdog Enable
17133  *  0b0..Programmable Watchdog is disabled
17134  *  0b1..Programmable Watchdog is enabled
17135  */
17136 #define ENET_MAC_WATCHDOG_TIMEOUT_PWE(x)         (((uint32_t)(((uint32_t)(x)) << ENET_MAC_WATCHDOG_TIMEOUT_PWE_SHIFT)) & ENET_MAC_WATCHDOG_TIMEOUT_PWE_MASK)
17137 /*! @} */
17138 
17139 /*! @name MAC_VLAN_TAG_CTRL - MAC VLAN Tag Control */
17140 /*! @{ */
17141 
17142 #define ENET_MAC_VLAN_TAG_CTRL_VL_MASK           (0xFFFFU)
17143 #define ENET_MAC_VLAN_TAG_CTRL_VL_SHIFT          (0U)
17144 /*! VL - VLAN Tag Identifier for Receive Packets */
17145 #define ENET_MAC_VLAN_TAG_CTRL_VL(x)             (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_CTRL_VL_SHIFT)) & ENET_MAC_VLAN_TAG_CTRL_VL_MASK)
17146 
17147 #define ENET_MAC_VLAN_TAG_CTRL_ETV_MASK          (0x10000U)
17148 #define ENET_MAC_VLAN_TAG_CTRL_ETV_SHIFT         (16U)
17149 /*! ETV - Enable 12-Bit VLAN Tag Comparison
17150  *  0b0..12-bit VLAN Tag Comparison is disabled
17151  *  0b1..12-bit VLAN Tag Comparison is enabled
17152  */
17153 #define ENET_MAC_VLAN_TAG_CTRL_ETV(x)            (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_CTRL_ETV_SHIFT)) & ENET_MAC_VLAN_TAG_CTRL_ETV_MASK)
17154 
17155 #define ENET_MAC_VLAN_TAG_CTRL_VTIM_MASK         (0x20000U)
17156 #define ENET_MAC_VLAN_TAG_CTRL_VTIM_SHIFT        (17U)
17157 /*! VTIM - VLAN Tag Inverse Match Enable
17158  *  0b0..VLAN Tag Inverse Match is disabled
17159  *  0b1..VLAN Tag Inverse Match is enabled
17160  */
17161 #define ENET_MAC_VLAN_TAG_CTRL_VTIM(x)           (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_CTRL_VTIM_SHIFT)) & ENET_MAC_VLAN_TAG_CTRL_VTIM_MASK)
17162 
17163 #define ENET_MAC_VLAN_TAG_CTRL_ESVL_MASK         (0x40000U)
17164 #define ENET_MAC_VLAN_TAG_CTRL_ESVL_SHIFT        (18U)
17165 /*! ESVL - Enable S-VLAN
17166  *  0b0..S-VLAN is disabled
17167  *  0b1..S-VLAN is enabled
17168  */
17169 #define ENET_MAC_VLAN_TAG_CTRL_ESVL(x)           (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_CTRL_ESVL_SHIFT)) & ENET_MAC_VLAN_TAG_CTRL_ESVL_MASK)
17170 
17171 #define ENET_MAC_VLAN_TAG_CTRL_ERSVLM_MASK       (0x80000U)
17172 #define ENET_MAC_VLAN_TAG_CTRL_ERSVLM_SHIFT      (19U)
17173 /*! ERSVLM - Enable Receive S-VLAN Match
17174  *  0b0..Receive S-VLAN Match is disabled
17175  *  0b1..Receive S-VLAN Match is enabled
17176  */
17177 #define ENET_MAC_VLAN_TAG_CTRL_ERSVLM(x)         (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_CTRL_ERSVLM_SHIFT)) & ENET_MAC_VLAN_TAG_CTRL_ERSVLM_MASK)
17178 
17179 #define ENET_MAC_VLAN_TAG_CTRL_DOVLTC_MASK       (0x100000U)
17180 #define ENET_MAC_VLAN_TAG_CTRL_DOVLTC_SHIFT      (20U)
17181 /*! DOVLTC - Disable VLAN Type Check
17182  *  0b1..VLAN Type Check is disabled
17183  *  0b0..VLAN Type Check is enabled
17184  */
17185 #define ENET_MAC_VLAN_TAG_CTRL_DOVLTC(x)         (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_CTRL_DOVLTC_SHIFT)) & ENET_MAC_VLAN_TAG_CTRL_DOVLTC_MASK)
17186 
17187 #define ENET_MAC_VLAN_TAG_CTRL_EVLS_MASK         (0x600000U)
17188 #define ENET_MAC_VLAN_TAG_CTRL_EVLS_SHIFT        (21U)
17189 /*! EVLS - Enable VLAN Tag Stripping on Receive
17190  *  0b11..Always strip
17191  *  0b00..Do not strip
17192  *  0b10..Strip if VLAN filter fails
17193  *  0b01..Strip if VLAN filter passes
17194  */
17195 #define ENET_MAC_VLAN_TAG_CTRL_EVLS(x)           (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_CTRL_EVLS_SHIFT)) & ENET_MAC_VLAN_TAG_CTRL_EVLS_MASK)
17196 
17197 #define ENET_MAC_VLAN_TAG_CTRL_EVLRXS_MASK       (0x1000000U)
17198 #define ENET_MAC_VLAN_TAG_CTRL_EVLRXS_SHIFT      (24U)
17199 /*! EVLRXS - Enable VLAN Tag in Rx status
17200  *  0b0..VLAN Tag in Rx status is disabled
17201  *  0b1..VLAN Tag in Rx status is enabled
17202  */
17203 #define ENET_MAC_VLAN_TAG_CTRL_EVLRXS(x)         (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_CTRL_EVLRXS_SHIFT)) & ENET_MAC_VLAN_TAG_CTRL_EVLRXS_MASK)
17204 
17205 #define ENET_MAC_VLAN_TAG_CTRL_EDVLP_MASK        (0x4000000U)
17206 #define ENET_MAC_VLAN_TAG_CTRL_EDVLP_SHIFT       (26U)
17207 /*! EDVLP - Enable Double VLAN Processing
17208  *  0b0..Double VLAN Processing is disabled
17209  *  0b1..Double VLAN Processing is enabled
17210  */
17211 #define ENET_MAC_VLAN_TAG_CTRL_EDVLP(x)          (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_CTRL_EDVLP_SHIFT)) & ENET_MAC_VLAN_TAG_CTRL_EDVLP_MASK)
17212 
17213 #define ENET_MAC_VLAN_TAG_CTRL_ERIVLT_MASK       (0x8000000U)
17214 #define ENET_MAC_VLAN_TAG_CTRL_ERIVLT_SHIFT      (27U)
17215 /*! ERIVLT - Enable Inner VLAN Tag
17216  *  0b0..Inner VLAN tag is disabled
17217  *  0b1..Inner VLAN tag is enabled
17218  */
17219 #define ENET_MAC_VLAN_TAG_CTRL_ERIVLT(x)         (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_CTRL_ERIVLT_SHIFT)) & ENET_MAC_VLAN_TAG_CTRL_ERIVLT_MASK)
17220 
17221 #define ENET_MAC_VLAN_TAG_CTRL_EIVLS_MASK        (0x30000000U)
17222 #define ENET_MAC_VLAN_TAG_CTRL_EIVLS_SHIFT       (28U)
17223 /*! EIVLS - Enable Inner VLAN Tag Stripping on Receive
17224  *  0b11..Always strip
17225  *  0b00..Do not strip
17226  *  0b10..Strip if VLAN filter fails
17227  *  0b01..Strip if VLAN filter passes
17228  */
17229 #define ENET_MAC_VLAN_TAG_CTRL_EIVLS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_CTRL_EIVLS_SHIFT)) & ENET_MAC_VLAN_TAG_CTRL_EIVLS_MASK)
17230 
17231 #define ENET_MAC_VLAN_TAG_CTRL_EIVLRXS_MASK      (0x80000000U)
17232 #define ENET_MAC_VLAN_TAG_CTRL_EIVLRXS_SHIFT     (31U)
17233 /*! EIVLRXS - Enable Inner VLAN Tag in Rx Status
17234  *  0b0..Inner VLAN Tag in Rx status is disabled
17235  *  0b1..Inner VLAN Tag in Rx status is enabled
17236  */
17237 #define ENET_MAC_VLAN_TAG_CTRL_EIVLRXS(x)        (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_CTRL_EIVLRXS_SHIFT)) & ENET_MAC_VLAN_TAG_CTRL_EIVLRXS_MASK)
17238 /*! @} */
17239 
17240 /*! @name MAC_VLAN_INCL - VLAN Tag Inclusion or Replacement */
17241 /*! @{ */
17242 
17243 #define ENET_MAC_VLAN_INCL_VLT_MASK              (0xFFFFU)
17244 #define ENET_MAC_VLAN_INCL_VLT_SHIFT             (0U)
17245 /*! VLT - VLAN Tag for Transmit Packets */
17246 #define ENET_MAC_VLAN_INCL_VLT(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_INCL_VLT_SHIFT)) & ENET_MAC_VLAN_INCL_VLT_MASK)
17247 
17248 #define ENET_MAC_VLAN_INCL_VLC_MASK              (0x30000U)
17249 #define ENET_MAC_VLAN_INCL_VLC_SHIFT             (16U)
17250 /*! VLC - VLAN Tag Control in Transmit Packets
17251  *  0b01..VLAN tag deletion
17252  *  0b10..VLAN tag insertion
17253  *  0b00..No VLAN tag deletion, insertion, or replacement
17254  *  0b11..VLAN tag replacement
17255  */
17256 #define ENET_MAC_VLAN_INCL_VLC(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_INCL_VLC_SHIFT)) & ENET_MAC_VLAN_INCL_VLC_MASK)
17257 
17258 #define ENET_MAC_VLAN_INCL_VLP_MASK              (0x40000U)
17259 #define ENET_MAC_VLAN_INCL_VLP_SHIFT             (18U)
17260 /*! VLP - VLAN Priority Control
17261  *  0b0..VLAN Priority Control is disabled
17262  *  0b1..VLAN Priority Control is enabled
17263  */
17264 #define ENET_MAC_VLAN_INCL_VLP(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_INCL_VLP_SHIFT)) & ENET_MAC_VLAN_INCL_VLP_MASK)
17265 
17266 #define ENET_MAC_VLAN_INCL_CSVL_MASK             (0x80000U)
17267 #define ENET_MAC_VLAN_INCL_CSVL_SHIFT            (19U)
17268 /*! CSVL - C-VLAN or S-VLAN
17269  *  0b0..C-VLAN type (0x8100) is inserted or replaced
17270  *  0b1..S-VLAN type (0x88A8) is inserted or replaced
17271  */
17272 #define ENET_MAC_VLAN_INCL_CSVL(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_INCL_CSVL_SHIFT)) & ENET_MAC_VLAN_INCL_CSVL_MASK)
17273 
17274 #define ENET_MAC_VLAN_INCL_VLTI_MASK             (0x100000U)
17275 #define ENET_MAC_VLAN_INCL_VLTI_SHIFT            (20U)
17276 /*! VLTI - VLAN Tag Input
17277  *  0b0..VLAN Tag Input is disabled
17278  *  0b1..VLAN Tag Input is enabled
17279  */
17280 #define ENET_MAC_VLAN_INCL_VLTI(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_INCL_VLTI_SHIFT)) & ENET_MAC_VLAN_INCL_VLTI_MASK)
17281 
17282 #define ENET_MAC_VLAN_INCL_CBTI_MASK             (0x200000U)
17283 #define ENET_MAC_VLAN_INCL_CBTI_SHIFT            (21U)
17284 /*! CBTI - Channel based tag insertion
17285  *  0b0..Channel based tag insertion is disabled
17286  *  0b1..Channel based tag insertion is enabled
17287  */
17288 #define ENET_MAC_VLAN_INCL_CBTI(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_INCL_CBTI_SHIFT)) & ENET_MAC_VLAN_INCL_CBTI_MASK)
17289 
17290 #define ENET_MAC_VLAN_INCL_ADDR_MASK             (0x1000000U)
17291 #define ENET_MAC_VLAN_INCL_ADDR_SHIFT            (24U)
17292 /*! ADDR - Address */
17293 #define ENET_MAC_VLAN_INCL_ADDR(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_INCL_ADDR_SHIFT)) & ENET_MAC_VLAN_INCL_ADDR_MASK)
17294 
17295 #define ENET_MAC_VLAN_INCL_RDWR_MASK             (0x40000000U)
17296 #define ENET_MAC_VLAN_INCL_RDWR_SHIFT            (30U)
17297 /*! RDWR - Read write control
17298  *  0b0..Read operation of indirect access
17299  *  0b1..Write operation of indirect access
17300  */
17301 #define ENET_MAC_VLAN_INCL_RDWR(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_INCL_RDWR_SHIFT)) & ENET_MAC_VLAN_INCL_RDWR_MASK)
17302 
17303 #define ENET_MAC_VLAN_INCL_BUSY_MASK             (0x80000000U)
17304 #define ENET_MAC_VLAN_INCL_BUSY_SHIFT            (31U)
17305 /*! BUSY - Busy
17306  *  0b1..Busy status detected
17307  *  0b0..Busy status not detected
17308  */
17309 #define ENET_MAC_VLAN_INCL_BUSY(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_INCL_BUSY_SHIFT)) & ENET_MAC_VLAN_INCL_BUSY_MASK)
17310 /*! @} */
17311 
17312 /*! @name MAC_INNER_VLAN_INCL - MAC Inner VLAN Tag Inclusion or Replacement */
17313 /*! @{ */
17314 
17315 #define ENET_MAC_INNER_VLAN_INCL_VLT_MASK        (0xFFFFU)
17316 #define ENET_MAC_INNER_VLAN_INCL_VLT_SHIFT       (0U)
17317 /*! VLT - VLAN Tag for Transmit Packets */
17318 #define ENET_MAC_INNER_VLAN_INCL_VLT(x)          (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INNER_VLAN_INCL_VLT_SHIFT)) & ENET_MAC_INNER_VLAN_INCL_VLT_MASK)
17319 
17320 #define ENET_MAC_INNER_VLAN_INCL_VLC_MASK        (0x30000U)
17321 #define ENET_MAC_INNER_VLAN_INCL_VLC_SHIFT       (16U)
17322 /*! VLC - VLAN Tag Control in Transmit Packets
17323  *  0b01..VLAN tag deletion
17324  *  0b10..VLAN tag insertion
17325  *  0b00..No VLAN tag deletion, insertion, or replacement
17326  *  0b11..VLAN tag replacement
17327  */
17328 #define ENET_MAC_INNER_VLAN_INCL_VLC(x)          (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INNER_VLAN_INCL_VLC_SHIFT)) & ENET_MAC_INNER_VLAN_INCL_VLC_MASK)
17329 
17330 #define ENET_MAC_INNER_VLAN_INCL_VLP_MASK        (0x40000U)
17331 #define ENET_MAC_INNER_VLAN_INCL_VLP_SHIFT       (18U)
17332 /*! VLP - VLAN Priority Control
17333  *  0b0..VLAN Priority Control is disabled
17334  *  0b1..VLAN Priority Control is enabled
17335  */
17336 #define ENET_MAC_INNER_VLAN_INCL_VLP(x)          (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INNER_VLAN_INCL_VLP_SHIFT)) & ENET_MAC_INNER_VLAN_INCL_VLP_MASK)
17337 
17338 #define ENET_MAC_INNER_VLAN_INCL_CSVL_MASK       (0x80000U)
17339 #define ENET_MAC_INNER_VLAN_INCL_CSVL_SHIFT      (19U)
17340 /*! CSVL - C-VLAN or S-VLAN
17341  *  0b0..C-VLAN type (0x8100) is inserted
17342  *  0b1..S-VLAN type (0x88A8) is inserted
17343  */
17344 #define ENET_MAC_INNER_VLAN_INCL_CSVL(x)         (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INNER_VLAN_INCL_CSVL_SHIFT)) & ENET_MAC_INNER_VLAN_INCL_CSVL_MASK)
17345 
17346 #define ENET_MAC_INNER_VLAN_INCL_VLTI_MASK       (0x100000U)
17347 #define ENET_MAC_INNER_VLAN_INCL_VLTI_SHIFT      (20U)
17348 /*! VLTI - VLAN Tag Input
17349  *  0b0..VLAN Tag Input is disabled
17350  *  0b1..VLAN Tag Input is enabled
17351  */
17352 #define ENET_MAC_INNER_VLAN_INCL_VLTI(x)         (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INNER_VLAN_INCL_VLTI_SHIFT)) & ENET_MAC_INNER_VLAN_INCL_VLTI_MASK)
17353 /*! @} */
17354 
17355 /*! @name MAC_TX_FLOW_CTRL_Q - MAC Q0 Tx Flow Control */
17356 /*! @{ */
17357 
17358 #define ENET_MAC_TX_FLOW_CTRL_Q_FCB_BPA_MASK     (0x1U)
17359 #define ENET_MAC_TX_FLOW_CTRL_Q_FCB_BPA_SHIFT    (0U)
17360 /*! FCB_BPA - Flow Control Busy or Backpressure Activate
17361  *  0b0..Flow Control Busy or Backpressure Activate is disabled
17362  *  0b1..Flow Control Busy or Backpressure Activate is enabled
17363  */
17364 #define ENET_MAC_TX_FLOW_CTRL_Q_FCB_BPA(x)       (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_FCB_BPA_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_FCB_BPA_MASK)
17365 
17366 #define ENET_MAC_TX_FLOW_CTRL_Q_TFE_MASK         (0x2U)
17367 #define ENET_MAC_TX_FLOW_CTRL_Q_TFE_SHIFT        (1U)
17368 /*! TFE - Transmit Flow Control Enable
17369  *  0b0..Transmit Flow Control is disabled
17370  *  0b1..Transmit Flow Control is enabled
17371  */
17372 #define ENET_MAC_TX_FLOW_CTRL_Q_TFE(x)           (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_TFE_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_TFE_MASK)
17373 
17374 #define ENET_MAC_TX_FLOW_CTRL_Q_PLT_MASK         (0x70U)
17375 #define ENET_MAC_TX_FLOW_CTRL_Q_PLT_SHIFT        (4U)
17376 /*! PLT - Pause Low Threshold
17377  *  0b011..Pause Time minus 144 Slot Times (PT -144 slot times)
17378  *  0b100..Pause Time minus 256 Slot Times (PT -256 slot times)
17379  *  0b001..Pause Time minus 28 Slot Times (PT -28 slot times)
17380  *  0b010..Pause Time minus 36 Slot Times (PT -36 slot times)
17381  *  0b000..Pause Time minus 4 Slot Times (PT -4 slot times)
17382  *  0b101..Pause Time minus 512 Slot Times (PT -512 slot times)
17383  *  0b110..Reserved
17384  */
17385 #define ENET_MAC_TX_FLOW_CTRL_Q_PLT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_PLT_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_PLT_MASK)
17386 
17387 #define ENET_MAC_TX_FLOW_CTRL_Q_DZPQ_MASK        (0x80U)
17388 #define ENET_MAC_TX_FLOW_CTRL_Q_DZPQ_SHIFT       (7U)
17389 /*! DZPQ - Disable Zero-Quanta Pause
17390  *  0b1..Zero-Quanta Pause packet generation is disabled
17391  *  0b0..Zero-Quanta Pause packet generation is enabled
17392  */
17393 #define ENET_MAC_TX_FLOW_CTRL_Q_DZPQ(x)          (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_DZPQ_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_DZPQ_MASK)
17394 
17395 #define ENET_MAC_TX_FLOW_CTRL_Q_PT_MASK          (0xFFFF0000U)
17396 #define ENET_MAC_TX_FLOW_CTRL_Q_PT_SHIFT         (16U)
17397 /*! PT - Pause Time */
17398 #define ENET_MAC_TX_FLOW_CTRL_Q_PT(x)            (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_PT_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_PT_MASK)
17399 /*! @} */
17400 
17401 /* The count of ENET_MAC_TX_FLOW_CTRL_Q */
17402 #define ENET_MAC_TX_FLOW_CTRL_Q_COUNT            (1U)
17403 
17404 /*! @name MAC_RX_FLOW_CTRL - MAC Rx Flow Control */
17405 /*! @{ */
17406 
17407 #define ENET_MAC_RX_FLOW_CTRL_RFE_MASK           (0x1U)
17408 #define ENET_MAC_RX_FLOW_CTRL_RFE_SHIFT          (0U)
17409 /*! RFE - Receive Flow Control Enable
17410  *  0b0..Receive Flow Control is disabled
17411  *  0b1..Receive Flow Control is enabled
17412  */
17413 #define ENET_MAC_RX_FLOW_CTRL_RFE(x)             (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RX_FLOW_CTRL_RFE_SHIFT)) & ENET_MAC_RX_FLOW_CTRL_RFE_MASK)
17414 
17415 #define ENET_MAC_RX_FLOW_CTRL_UP_MASK            (0x2U)
17416 #define ENET_MAC_RX_FLOW_CTRL_UP_SHIFT           (1U)
17417 /*! UP - Unicast Pause Packet Detect
17418  *  0b0..Unicast Pause Packet Detect disabled
17419  *  0b1..Unicast Pause Packet Detect enabled
17420  */
17421 #define ENET_MAC_RX_FLOW_CTRL_UP(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RX_FLOW_CTRL_UP_SHIFT)) & ENET_MAC_RX_FLOW_CTRL_UP_MASK)
17422 /*! @} */
17423 
17424 /*! @name MAC_RXQ_CTRL4 - Receive Queue Control 4 */
17425 /*! @{ */
17426 
17427 #define ENET_MAC_RXQ_CTRL4_UFFQE_MASK            (0x1U)
17428 #define ENET_MAC_RXQ_CTRL4_UFFQE_SHIFT           (0U)
17429 /*! UFFQE - Unicast Address Filter Fail Packets Queuing Enable.
17430  *  0b0..Unicast Address Filter Fail Packets Queuing is disabled
17431  *  0b1..Unicast Address Filter Fail Packets Queuing is enabled
17432  */
17433 #define ENET_MAC_RXQ_CTRL4_UFFQE(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL4_UFFQE_SHIFT)) & ENET_MAC_RXQ_CTRL4_UFFQE_MASK)
17434 
17435 #define ENET_MAC_RXQ_CTRL4_UFFQ_MASK             (0x2U)
17436 #define ENET_MAC_RXQ_CTRL4_UFFQ_SHIFT            (1U)
17437 /*! UFFQ - Unicast Address Filter Fail Packets Queue. */
17438 #define ENET_MAC_RXQ_CTRL4_UFFQ(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL4_UFFQ_SHIFT)) & ENET_MAC_RXQ_CTRL4_UFFQ_MASK)
17439 
17440 #define ENET_MAC_RXQ_CTRL4_MFFQE_MASK            (0x100U)
17441 #define ENET_MAC_RXQ_CTRL4_MFFQE_SHIFT           (8U)
17442 /*! MFFQE - Multicast Address Filter Fail Packets Queuing Enable.
17443  *  0b0..Multicast Address Filter Fail Packets Queuing is disabled
17444  *  0b1..Multicast Address Filter Fail Packets Queuing is enabled
17445  */
17446 #define ENET_MAC_RXQ_CTRL4_MFFQE(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL4_MFFQE_SHIFT)) & ENET_MAC_RXQ_CTRL4_MFFQE_MASK)
17447 
17448 #define ENET_MAC_RXQ_CTRL4_MFFQ_MASK             (0x200U)
17449 #define ENET_MAC_RXQ_CTRL4_MFFQ_SHIFT            (9U)
17450 /*! MFFQ - Multicast Address Filter Fail Packets Queue. */
17451 #define ENET_MAC_RXQ_CTRL4_MFFQ(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL4_MFFQ_SHIFT)) & ENET_MAC_RXQ_CTRL4_MFFQ_MASK)
17452 
17453 #define ENET_MAC_RXQ_CTRL4_VFFQE_MASK            (0x10000U)
17454 #define ENET_MAC_RXQ_CTRL4_VFFQE_SHIFT           (16U)
17455 /*! VFFQE - VLAN Tag Filter Fail Packets Queuing Enable
17456  *  0b0..VLAN tag Filter Fail Packets Queuing is disabled
17457  *  0b1..VLAN tag Filter Fail Packets Queuing is enabled
17458  */
17459 #define ENET_MAC_RXQ_CTRL4_VFFQE(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL4_VFFQE_SHIFT)) & ENET_MAC_RXQ_CTRL4_VFFQE_MASK)
17460 
17461 #define ENET_MAC_RXQ_CTRL4_VFFQ_MASK             (0x20000U)
17462 #define ENET_MAC_RXQ_CTRL4_VFFQ_SHIFT            (17U)
17463 /*! VFFQ - VLAN Tag Filter Fail Packets Queue */
17464 #define ENET_MAC_RXQ_CTRL4_VFFQ(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL4_VFFQ_SHIFT)) & ENET_MAC_RXQ_CTRL4_VFFQ_MASK)
17465 /*! @} */
17466 
17467 /*! @name MAC_RXQ_CTRL - Receive Queue Control 0..Receive Queue Control 2 */
17468 /*! @{ */
17469 
17470 #define ENET_MAC_RXQ_CTRL_AVCPQ_MASK             (0x7U)
17471 #define ENET_MAC_RXQ_CTRL_AVCPQ_SHIFT            (0U)
17472 /*! AVCPQ - AV Untagged Control Packets Queue
17473  *  0b000..Receive Queue 0
17474  *  0b001..Receive Queue 1
17475  */
17476 #define ENET_MAC_RXQ_CTRL_AVCPQ(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_AVCPQ_SHIFT)) & ENET_MAC_RXQ_CTRL_AVCPQ_MASK)
17477 
17478 #define ENET_MAC_RXQ_CTRL_PSRQ0_MASK             (0xFFU)
17479 #define ENET_MAC_RXQ_CTRL_PSRQ0_SHIFT            (0U)
17480 /*! PSRQ0 - Priorities Selected in the Receive Queue 0 */
17481 #define ENET_MAC_RXQ_CTRL_PSRQ0(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_PSRQ0_SHIFT)) & ENET_MAC_RXQ_CTRL_PSRQ0_MASK)
17482 
17483 #define ENET_MAC_RXQ_CTRL_RXQ0EN_MASK            (0x3U)
17484 #define ENET_MAC_RXQ_CTRL_RXQ0EN_SHIFT           (0U)
17485 /*! RXQ0EN - Receive Queue 0 Enable
17486  *  0b00..Queue not enabled
17487  *  0b01..Queue enabled for AV
17488  *  0b10..Queue enabled for DCB/Generic
17489  *  0b11..Reserved
17490  */
17491 #define ENET_MAC_RXQ_CTRL_RXQ0EN(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_RXQ0EN_SHIFT)) & ENET_MAC_RXQ_CTRL_RXQ0EN_MASK)
17492 
17493 #define ENET_MAC_RXQ_CTRL_RXQ1EN_MASK            (0xCU)
17494 #define ENET_MAC_RXQ_CTRL_RXQ1EN_SHIFT           (2U)
17495 /*! RXQ1EN - Receive Queue 1 Enable
17496  *  0b00..Queue not enabled
17497  *  0b01..Queue enabled for AV
17498  *  0b10..Queue enabled for DCB/Generic
17499  *  0b11..Reserved
17500  */
17501 #define ENET_MAC_RXQ_CTRL_RXQ1EN(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_RXQ1EN_SHIFT)) & ENET_MAC_RXQ_CTRL_RXQ1EN_MASK)
17502 
17503 #define ENET_MAC_RXQ_CTRL_PTPQ_MASK              (0x70U)
17504 #define ENET_MAC_RXQ_CTRL_PTPQ_SHIFT             (4U)
17505 /*! PTPQ - PTP Packets Queue
17506  *  0b000..Receive Queue 0
17507  *  0b001..Receive Queue 1
17508  */
17509 #define ENET_MAC_RXQ_CTRL_PTPQ(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_PTPQ_SHIFT)) & ENET_MAC_RXQ_CTRL_PTPQ_MASK)
17510 
17511 #define ENET_MAC_RXQ_CTRL_PSRQ1_MASK             (0xFF00U)
17512 #define ENET_MAC_RXQ_CTRL_PSRQ1_SHIFT            (8U)
17513 /*! PSRQ1 - Priorities Selected in the Receive Queue 1 */
17514 #define ENET_MAC_RXQ_CTRL_PSRQ1(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_PSRQ1_SHIFT)) & ENET_MAC_RXQ_CTRL_PSRQ1_MASK)
17515 
17516 #define ENET_MAC_RXQ_CTRL_UPQ_MASK               (0x7000U)
17517 #define ENET_MAC_RXQ_CTRL_UPQ_SHIFT              (12U)
17518 /*! UPQ - Untagged Packet Queue
17519  *  0b000..Receive Queue 0
17520  *  0b001..Receive Queue 1
17521  */
17522 #define ENET_MAC_RXQ_CTRL_UPQ(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_UPQ_SHIFT)) & ENET_MAC_RXQ_CTRL_UPQ_MASK)
17523 
17524 #define ENET_MAC_RXQ_CTRL_MCBCQ_MASK             (0x70000U)
17525 #define ENET_MAC_RXQ_CTRL_MCBCQ_SHIFT            (16U)
17526 /*! MCBCQ - Multicast and Broadcast Queue
17527  *  0b000..Receive Queue 0
17528  *  0b001..Receive Queue 1
17529  */
17530 #define ENET_MAC_RXQ_CTRL_MCBCQ(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_MCBCQ_SHIFT)) & ENET_MAC_RXQ_CTRL_MCBCQ_MASK)
17531 
17532 #define ENET_MAC_RXQ_CTRL_MCBCQEN_MASK           (0x100000U)
17533 #define ENET_MAC_RXQ_CTRL_MCBCQEN_SHIFT          (20U)
17534 /*! MCBCQEN - Multicast and Broadcast Queue Enable
17535  *  0b0..Multicast and Broadcast Queue is disabled
17536  *  0b1..Multicast and Broadcast Queue is enabled
17537  */
17538 #define ENET_MAC_RXQ_CTRL_MCBCQEN(x)             (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_MCBCQEN_SHIFT)) & ENET_MAC_RXQ_CTRL_MCBCQEN_MASK)
17539 
17540 #define ENET_MAC_RXQ_CTRL_TACPQE_MASK            (0x200000U)
17541 #define ENET_MAC_RXQ_CTRL_TACPQE_SHIFT           (21U)
17542 /*! TACPQE - Tagged AV Control Packets Queuing Enable.
17543  *  0b0..Tagged AV Control Packets Queuing is disabled
17544  *  0b1..Tagged AV Control Packets Queuing is enabled
17545  */
17546 #define ENET_MAC_RXQ_CTRL_TACPQE(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_TACPQE_SHIFT)) & ENET_MAC_RXQ_CTRL_TACPQE_MASK)
17547 
17548 #define ENET_MAC_RXQ_CTRL_TPQC_MASK              (0xC00000U)
17549 #define ENET_MAC_RXQ_CTRL_TPQC_SHIFT             (22U)
17550 /*! TPQC - Tagged PTP over Ethernet Packets Queuing Control. */
17551 #define ENET_MAC_RXQ_CTRL_TPQC(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_TPQC_SHIFT)) & ENET_MAC_RXQ_CTRL_TPQC_MASK)
17552 
17553 #define ENET_MAC_RXQ_CTRL_OMCBCQ_MASK            (0x10000000U)
17554 #define ENET_MAC_RXQ_CTRL_OMCBCQ_SHIFT           (28U)
17555 /*! OMCBCQ - OMCBCQ
17556  *  0b0..overriding MCBCQ priority disabled
17557  *  0b1..overriding MCBCQ priority enabled
17558  */
17559 #define ENET_MAC_RXQ_CTRL_OMCBCQ(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_OMCBCQ_SHIFT)) & ENET_MAC_RXQ_CTRL_OMCBCQ_MASK)
17560 
17561 #define ENET_MAC_RXQ_CTRL_TBRQE_MASK             (0x20000000U)
17562 #define ENET_MAC_RXQ_CTRL_TBRQE_SHIFT            (29U)
17563 /*! TBRQE - Type Field Based Rx Queuing Enable */
17564 #define ENET_MAC_RXQ_CTRL_TBRQE(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_TBRQE_SHIFT)) & ENET_MAC_RXQ_CTRL_TBRQE_MASK)
17565 /*! @} */
17566 
17567 /* The count of ENET_MAC_RXQ_CTRL */
17568 #define ENET_MAC_RXQ_CTRL_COUNT                  (3U)
17569 
17570 /*! @name MAC_INTERRUPT_STATUS - Interrupt Status */
17571 /*! @{ */
17572 
17573 #define ENET_MAC_INTERRUPT_STATUS_PHYIS_MASK     (0x8U)
17574 #define ENET_MAC_INTERRUPT_STATUS_PHYIS_SHIFT    (3U)
17575 /*! PHYIS - PHY Interrupt
17576  *  0b1..PHY Interrupt detected
17577  *  0b0..PHY Interrupt not detected
17578  */
17579 #define ENET_MAC_INTERRUPT_STATUS_PHYIS(x)       (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTERRUPT_STATUS_PHYIS_SHIFT)) & ENET_MAC_INTERRUPT_STATUS_PHYIS_MASK)
17580 
17581 #define ENET_MAC_INTERRUPT_STATUS_PMTIS_MASK     (0x10U)
17582 #define ENET_MAC_INTERRUPT_STATUS_PMTIS_SHIFT    (4U)
17583 /*! PMTIS - PMTIS
17584  *  0b1..PMT Interrupt status active
17585  *  0b0..PMT Interrupt status not active
17586  */
17587 #define ENET_MAC_INTERRUPT_STATUS_PMTIS(x)       (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTERRUPT_STATUS_PMTIS_SHIFT)) & ENET_MAC_INTERRUPT_STATUS_PMTIS_MASK)
17588 
17589 #define ENET_MAC_INTERRUPT_STATUS_LPIIS_MASK     (0x20U)
17590 #define ENET_MAC_INTERRUPT_STATUS_LPIIS_SHIFT    (5U)
17591 /*! LPIIS - LPIIS
17592  *  0b1..LPI Interrupt status active
17593  *  0b0..LPI Interrupt status not active
17594  */
17595 #define ENET_MAC_INTERRUPT_STATUS_LPIIS(x)       (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTERRUPT_STATUS_LPIIS_SHIFT)) & ENET_MAC_INTERRUPT_STATUS_LPIIS_MASK)
17596 
17597 #define ENET_MAC_INTERRUPT_STATUS_TSIS_MASK      (0x1000U)
17598 #define ENET_MAC_INTERRUPT_STATUS_TSIS_SHIFT     (12U)
17599 /*! TSIS - TSIS
17600  *  0b1..Timestamp Interrupt status active
17601  *  0b0..Timestamp Interrupt status not active
17602  */
17603 #define ENET_MAC_INTERRUPT_STATUS_TSIS(x)        (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTERRUPT_STATUS_TSIS_SHIFT)) & ENET_MAC_INTERRUPT_STATUS_TSIS_MASK)
17604 
17605 #define ENET_MAC_INTERRUPT_STATUS_TXSTSIS_MASK   (0x2000U)
17606 #define ENET_MAC_INTERRUPT_STATUS_TXSTSIS_SHIFT  (13U)
17607 /*! TXSTSIS - Transmit Status Interrupt
17608  *  0b1..Transmit Interrupt status active
17609  *  0b0..Transmit Interrupt status not active
17610  */
17611 #define ENET_MAC_INTERRUPT_STATUS_TXSTSIS(x)     (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTERRUPT_STATUS_TXSTSIS_SHIFT)) & ENET_MAC_INTERRUPT_STATUS_TXSTSIS_MASK)
17612 
17613 #define ENET_MAC_INTERRUPT_STATUS_RXSTSIS_MASK   (0x4000U)
17614 #define ENET_MAC_INTERRUPT_STATUS_RXSTSIS_SHIFT  (14U)
17615 /*! RXSTSIS - Receive Status Interrupt
17616  *  0b1..Receive Interrupt status active
17617  *  0b0..Receive Interrupt status not active
17618  */
17619 #define ENET_MAC_INTERRUPT_STATUS_RXSTSIS(x)     (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTERRUPT_STATUS_RXSTSIS_SHIFT)) & ENET_MAC_INTERRUPT_STATUS_RXSTSIS_MASK)
17620 
17621 #define ENET_MAC_INTERRUPT_STATUS_MDIOIS_MASK    (0x40000U)
17622 #define ENET_MAC_INTERRUPT_STATUS_MDIOIS_SHIFT   (18U)
17623 /*! MDIOIS - MDIO Interrupt Status
17624  *  0b1..MDIO Interrupt status active
17625  *  0b0..MDIO Interrupt status not active
17626  */
17627 #define ENET_MAC_INTERRUPT_STATUS_MDIOIS(x)      (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTERRUPT_STATUS_MDIOIS_SHIFT)) & ENET_MAC_INTERRUPT_STATUS_MDIOIS_MASK)
17628 /*! @} */
17629 
17630 /*! @name MAC_INTERRUPT_ENABLE - Interrupt Enable */
17631 /*! @{ */
17632 
17633 #define ENET_MAC_INTERRUPT_ENABLE_PHYIE_MASK     (0x8U)
17634 #define ENET_MAC_INTERRUPT_ENABLE_PHYIE_SHIFT    (3U)
17635 /*! PHYIE - PHY Interrupt Enable
17636  *  0b0..PHY Interrupt is disabled
17637  *  0b1..PHY Interrupt is enabled
17638  */
17639 #define ENET_MAC_INTERRUPT_ENABLE_PHYIE(x)       (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTERRUPT_ENABLE_PHYIE_SHIFT)) & ENET_MAC_INTERRUPT_ENABLE_PHYIE_MASK)
17640 
17641 #define ENET_MAC_INTERRUPT_ENABLE_PMTIE_MASK     (0x10U)
17642 #define ENET_MAC_INTERRUPT_ENABLE_PMTIE_SHIFT    (4U)
17643 /*! PMTIE - PMT Interrupt Enable
17644  *  0b0..PMT Interrupt is disabled
17645  *  0b1..PMT Interrupt is enabled
17646  */
17647 #define ENET_MAC_INTERRUPT_ENABLE_PMTIE(x)       (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTERRUPT_ENABLE_PMTIE_SHIFT)) & ENET_MAC_INTERRUPT_ENABLE_PMTIE_MASK)
17648 
17649 #define ENET_MAC_INTERRUPT_ENABLE_LPIIE_MASK     (0x20U)
17650 #define ENET_MAC_INTERRUPT_ENABLE_LPIIE_SHIFT    (5U)
17651 /*! LPIIE - LPI Interrupt Enable
17652  *  0b0..LPI Interrupt is disabled
17653  *  0b1..LPI Interrupt is enabled
17654  */
17655 #define ENET_MAC_INTERRUPT_ENABLE_LPIIE(x)       (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTERRUPT_ENABLE_LPIIE_SHIFT)) & ENET_MAC_INTERRUPT_ENABLE_LPIIE_MASK)
17656 
17657 #define ENET_MAC_INTERRUPT_ENABLE_TSIE_MASK      (0x1000U)
17658 #define ENET_MAC_INTERRUPT_ENABLE_TSIE_SHIFT     (12U)
17659 /*! TSIE - Timestamp Interrupt Enable
17660  *  0b0..Timestamp Interrupt is disabled
17661  *  0b1..Timestamp Interrupt is enabled
17662  */
17663 #define ENET_MAC_INTERRUPT_ENABLE_TSIE(x)        (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTERRUPT_ENABLE_TSIE_SHIFT)) & ENET_MAC_INTERRUPT_ENABLE_TSIE_MASK)
17664 
17665 #define ENET_MAC_INTERRUPT_ENABLE_TXSTSIE_MASK   (0x2000U)
17666 #define ENET_MAC_INTERRUPT_ENABLE_TXSTSIE_SHIFT  (13U)
17667 /*! TXSTSIE - Transmit Status Interrupt Enable
17668  *  0b0..Timestamp Status Interrupt is disabled
17669  *  0b1..Timestamp Status Interrupt is enabled
17670  */
17671 #define ENET_MAC_INTERRUPT_ENABLE_TXSTSIE(x)     (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTERRUPT_ENABLE_TXSTSIE_SHIFT)) & ENET_MAC_INTERRUPT_ENABLE_TXSTSIE_MASK)
17672 
17673 #define ENET_MAC_INTERRUPT_ENABLE_RXSTSIE_MASK   (0x4000U)
17674 #define ENET_MAC_INTERRUPT_ENABLE_RXSTSIE_SHIFT  (14U)
17675 /*! RXSTSIE - Receive Status Interrupt Enable
17676  *  0b0..Receive Status Interrupt is disabled
17677  *  0b1..Receive Status Interrupt is enabled
17678  */
17679 #define ENET_MAC_INTERRUPT_ENABLE_RXSTSIE(x)     (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTERRUPT_ENABLE_RXSTSIE_SHIFT)) & ENET_MAC_INTERRUPT_ENABLE_RXSTSIE_MASK)
17680 
17681 #define ENET_MAC_INTERRUPT_ENABLE_MDIOIE_MASK    (0x40000U)
17682 #define ENET_MAC_INTERRUPT_ENABLE_MDIOIE_SHIFT   (18U)
17683 /*! MDIOIE - MDIO Interrupt Enable
17684  *  0b0..MDIO Interrupt is disabled
17685  *  0b1..MDIO Interrupt is enabled
17686  */
17687 #define ENET_MAC_INTERRUPT_ENABLE_MDIOIE(x)      (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTERRUPT_ENABLE_MDIOIE_SHIFT)) & ENET_MAC_INTERRUPT_ENABLE_MDIOIE_MASK)
17688 /*! @} */
17689 
17690 /*! @name MAC_RX_TX_STATUS - Receive Transmit Status */
17691 /*! @{ */
17692 
17693 #define ENET_MAC_RX_TX_STATUS_TJT_MASK           (0x1U)
17694 #define ENET_MAC_RX_TX_STATUS_TJT_SHIFT          (0U)
17695 /*! TJT - Transmit Jabber Timeout
17696  *  0b1..Transmit Jabber Timeout occurred
17697  *  0b0..No Transmit Jabber Timeout
17698  */
17699 #define ENET_MAC_RX_TX_STATUS_TJT(x)             (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RX_TX_STATUS_TJT_SHIFT)) & ENET_MAC_RX_TX_STATUS_TJT_MASK)
17700 
17701 #define ENET_MAC_RX_TX_STATUS_NCARR_MASK         (0x2U)
17702 #define ENET_MAC_RX_TX_STATUS_NCARR_SHIFT        (1U)
17703 /*! NCARR - No Carrier
17704  *  0b1..No carrier
17705  *  0b0..Carrier is present
17706  */
17707 #define ENET_MAC_RX_TX_STATUS_NCARR(x)           (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RX_TX_STATUS_NCARR_SHIFT)) & ENET_MAC_RX_TX_STATUS_NCARR_MASK)
17708 
17709 #define ENET_MAC_RX_TX_STATUS_LCARR_MASK         (0x4U)
17710 #define ENET_MAC_RX_TX_STATUS_LCARR_SHIFT        (2U)
17711 /*! LCARR - Loss of Carrier
17712  *  0b1..Loss of carrier
17713  *  0b0..Carrier is present
17714  */
17715 #define ENET_MAC_RX_TX_STATUS_LCARR(x)           (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RX_TX_STATUS_LCARR_SHIFT)) & ENET_MAC_RX_TX_STATUS_LCARR_MASK)
17716 
17717 #define ENET_MAC_RX_TX_STATUS_EXDEF_MASK         (0x8U)
17718 #define ENET_MAC_RX_TX_STATUS_EXDEF_SHIFT        (3U)
17719 /*! EXDEF - Excessive Deferral
17720  *  0b1..Excessive deferral
17721  *  0b0..No Excessive deferral
17722  */
17723 #define ENET_MAC_RX_TX_STATUS_EXDEF(x)           (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RX_TX_STATUS_EXDEF_SHIFT)) & ENET_MAC_RX_TX_STATUS_EXDEF_MASK)
17724 
17725 #define ENET_MAC_RX_TX_STATUS_LCOL_MASK          (0x10U)
17726 #define ENET_MAC_RX_TX_STATUS_LCOL_SHIFT         (4U)
17727 /*! LCOL - Late Collision
17728  *  0b1..Late collision is sensed
17729  *  0b0..No collision
17730  */
17731 #define ENET_MAC_RX_TX_STATUS_LCOL(x)            (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RX_TX_STATUS_LCOL_SHIFT)) & ENET_MAC_RX_TX_STATUS_LCOL_MASK)
17732 
17733 #define ENET_MAC_RX_TX_STATUS_EXCOL_MASK         (0x20U)
17734 #define ENET_MAC_RX_TX_STATUS_EXCOL_SHIFT        (5U)
17735 /*! EXCOL - Excessive Collisions
17736  *  0b1..Excessive collision is sensed
17737  *  0b0..No collision
17738  */
17739 #define ENET_MAC_RX_TX_STATUS_EXCOL(x)           (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RX_TX_STATUS_EXCOL_SHIFT)) & ENET_MAC_RX_TX_STATUS_EXCOL_MASK)
17740 
17741 #define ENET_MAC_RX_TX_STATUS_RWT_MASK           (0x100U)
17742 #define ENET_MAC_RX_TX_STATUS_RWT_SHIFT          (8U)
17743 /*! RWT - Receive Watchdog Timeout
17744  *  0b1..Receive watchdog timed out
17745  *  0b0..No receive watchdog timeout
17746  */
17747 #define ENET_MAC_RX_TX_STATUS_RWT(x)             (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RX_TX_STATUS_RWT_SHIFT)) & ENET_MAC_RX_TX_STATUS_RWT_MASK)
17748 /*! @} */
17749 
17750 /*! @name MAC_PMT_CONTROL_STATUS - PMT Control and Status */
17751 /*! @{ */
17752 
17753 #define ENET_MAC_PMT_CONTROL_STATUS_PWRDWN_MASK  (0x1U)
17754 #define ENET_MAC_PMT_CONTROL_STATUS_PWRDWN_SHIFT (0U)
17755 /*! PWRDWN - Power Down
17756  *  0b0..Power down is disabled
17757  *  0b1..Power down is enabled
17758  */
17759 #define ENET_MAC_PMT_CONTROL_STATUS_PWRDWN(x)    (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CONTROL_STATUS_PWRDWN_SHIFT)) & ENET_MAC_PMT_CONTROL_STATUS_PWRDWN_MASK)
17760 
17761 #define ENET_MAC_PMT_CONTROL_STATUS_MGKPKTEN_MASK (0x2U)
17762 #define ENET_MAC_PMT_CONTROL_STATUS_MGKPKTEN_SHIFT (1U)
17763 /*! MGKPKTEN - Magic Packet Enable
17764  *  0b0..Magic Packet is disabled
17765  *  0b1..Magic Packet is enabled
17766  */
17767 #define ENET_MAC_PMT_CONTROL_STATUS_MGKPKTEN(x)  (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CONTROL_STATUS_MGKPKTEN_SHIFT)) & ENET_MAC_PMT_CONTROL_STATUS_MGKPKTEN_MASK)
17768 
17769 #define ENET_MAC_PMT_CONTROL_STATUS_RWKPKTEN_MASK (0x4U)
17770 #define ENET_MAC_PMT_CONTROL_STATUS_RWKPKTEN_SHIFT (2U)
17771 /*! RWKPKTEN - Remote Wake-Up Packet Enable
17772  *  0b0..Remote wake-up packet is disabled
17773  *  0b1..Remote wake-up packet is enabled
17774  */
17775 #define ENET_MAC_PMT_CONTROL_STATUS_RWKPKTEN(x)  (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CONTROL_STATUS_RWKPKTEN_SHIFT)) & ENET_MAC_PMT_CONTROL_STATUS_RWKPKTEN_MASK)
17776 
17777 #define ENET_MAC_PMT_CONTROL_STATUS_MGKPRCVD_MASK (0x20U)
17778 #define ENET_MAC_PMT_CONTROL_STATUS_MGKPRCVD_SHIFT (5U)
17779 /*! MGKPRCVD - Magic Packet Received
17780  *  0b1..Magic packet is received
17781  *  0b0..No Magic packet is received
17782  */
17783 #define ENET_MAC_PMT_CONTROL_STATUS_MGKPRCVD(x)  (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CONTROL_STATUS_MGKPRCVD_SHIFT)) & ENET_MAC_PMT_CONTROL_STATUS_MGKPRCVD_MASK)
17784 
17785 #define ENET_MAC_PMT_CONTROL_STATUS_RWKPRCVD_MASK (0x40U)
17786 #define ENET_MAC_PMT_CONTROL_STATUS_RWKPRCVD_SHIFT (6U)
17787 /*! RWKPRCVD - Remote Wake-Up Packet Received
17788  *  0b1..Remote wake-up packet is received
17789  *  0b0..Remote wake-up packet is received
17790  */
17791 #define ENET_MAC_PMT_CONTROL_STATUS_RWKPRCVD(x)  (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CONTROL_STATUS_RWKPRCVD_SHIFT)) & ENET_MAC_PMT_CONTROL_STATUS_RWKPRCVD_MASK)
17792 
17793 #define ENET_MAC_PMT_CONTROL_STATUS_GLBLUCAST_MASK (0x200U)
17794 #define ENET_MAC_PMT_CONTROL_STATUS_GLBLUCAST_SHIFT (9U)
17795 /*! GLBLUCAST - Global Unicast
17796  *  0b0..Global unicast is disabled
17797  *  0b1..Global unicast is enabled
17798  */
17799 #define ENET_MAC_PMT_CONTROL_STATUS_GLBLUCAST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CONTROL_STATUS_GLBLUCAST_SHIFT)) & ENET_MAC_PMT_CONTROL_STATUS_GLBLUCAST_MASK)
17800 
17801 #define ENET_MAC_PMT_CONTROL_STATUS_RWKPFE_MASK  (0x400U)
17802 #define ENET_MAC_PMT_CONTROL_STATUS_RWKPFE_SHIFT (10U)
17803 /*! RWKPFE - Remote Wake-up Packet Forwarding Enable
17804  *  0b0..Remote Wake-up Packet Forwarding is disabled
17805  *  0b1..Remote Wake-up Packet Forwarding is enabled
17806  */
17807 #define ENET_MAC_PMT_CONTROL_STATUS_RWKPFE(x)    (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CONTROL_STATUS_RWKPFE_SHIFT)) & ENET_MAC_PMT_CONTROL_STATUS_RWKPFE_MASK)
17808 
17809 #define ENET_MAC_PMT_CONTROL_STATUS_RWKPTR_MASK  (0x1F000000U)
17810 #define ENET_MAC_PMT_CONTROL_STATUS_RWKPTR_SHIFT (24U)
17811 /*! RWKPTR - Remote Wake-up FIFO Pointer */
17812 #define ENET_MAC_PMT_CONTROL_STATUS_RWKPTR(x)    (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CONTROL_STATUS_RWKPTR_SHIFT)) & ENET_MAC_PMT_CONTROL_STATUS_RWKPTR_MASK)
17813 
17814 #define ENET_MAC_PMT_CONTROL_STATUS_RWKFILTRST_MASK (0x80000000U)
17815 #define ENET_MAC_PMT_CONTROL_STATUS_RWKFILTRST_SHIFT (31U)
17816 /*! RWKFILTRST - Remote Wake-Up Packet Filter Register Pointer Reset
17817  *  0b0..Remote Wake-Up Packet Filter Register Pointer is not Reset
17818  *  0b1..Remote Wake-Up Packet Filter Register Pointer is Reset
17819  */
17820 #define ENET_MAC_PMT_CONTROL_STATUS_RWKFILTRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CONTROL_STATUS_RWKFILTRST_SHIFT)) & ENET_MAC_PMT_CONTROL_STATUS_RWKFILTRST_MASK)
17821 /*! @} */
17822 
17823 /*! @name MAC_RWK_PACKET_FILTER - Remote Wakeup Filter */
17824 /*! @{ */
17825 
17826 #define ENET_MAC_RWK_PACKET_FILTER_WKUPFRMFTR_MASK (0xFFFFFFFFU)
17827 #define ENET_MAC_RWK_PACKET_FILTER_WKUPFRMFTR_SHIFT (0U)
17828 /*! WKUPFRMFTR - RWK Packet Filter */
17829 #define ENET_MAC_RWK_PACKET_FILTER_WKUPFRMFTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RWK_PACKET_FILTER_WKUPFRMFTR_SHIFT)) & ENET_MAC_RWK_PACKET_FILTER_WKUPFRMFTR_MASK)
17830 /*! @} */
17831 
17832 /*! @name MAC_LPI_CONTROL_STATUS - LPI Control and Status */
17833 /*! @{ */
17834 
17835 #define ENET_MAC_LPI_CONTROL_STATUS_TLPIEN_MASK  (0x1U)
17836 #define ENET_MAC_LPI_CONTROL_STATUS_TLPIEN_SHIFT (0U)
17837 /*! TLPIEN - Transmit LPI Entry
17838  *  0b1..Transmit LPI entry detected
17839  *  0b0..Transmit LPI entry not detected
17840  */
17841 #define ENET_MAC_LPI_CONTROL_STATUS_TLPIEN(x)    (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CONTROL_STATUS_TLPIEN_SHIFT)) & ENET_MAC_LPI_CONTROL_STATUS_TLPIEN_MASK)
17842 
17843 #define ENET_MAC_LPI_CONTROL_STATUS_TLPIEX_MASK  (0x2U)
17844 #define ENET_MAC_LPI_CONTROL_STATUS_TLPIEX_SHIFT (1U)
17845 /*! TLPIEX - Transmit LPI Exit
17846  *  0b1..Transmit LPI exit detected
17847  *  0b0..Transmit LPI exit not detected
17848  */
17849 #define ENET_MAC_LPI_CONTROL_STATUS_TLPIEX(x)    (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CONTROL_STATUS_TLPIEX_SHIFT)) & ENET_MAC_LPI_CONTROL_STATUS_TLPIEX_MASK)
17850 
17851 #define ENET_MAC_LPI_CONTROL_STATUS_RLPIEN_MASK  (0x4U)
17852 #define ENET_MAC_LPI_CONTROL_STATUS_RLPIEN_SHIFT (2U)
17853 /*! RLPIEN - Receive LPI Entry
17854  *  0b1..Receive LPI entry detected
17855  *  0b0..Receive LPI entry not detected
17856  */
17857 #define ENET_MAC_LPI_CONTROL_STATUS_RLPIEN(x)    (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CONTROL_STATUS_RLPIEN_SHIFT)) & ENET_MAC_LPI_CONTROL_STATUS_RLPIEN_MASK)
17858 
17859 #define ENET_MAC_LPI_CONTROL_STATUS_RLPIEX_MASK  (0x8U)
17860 #define ENET_MAC_LPI_CONTROL_STATUS_RLPIEX_SHIFT (3U)
17861 /*! RLPIEX - Receive LPI Exit
17862  *  0b1..Receive LPI exit detected
17863  *  0b0..Receive LPI exit not detected
17864  */
17865 #define ENET_MAC_LPI_CONTROL_STATUS_RLPIEX(x)    (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CONTROL_STATUS_RLPIEX_SHIFT)) & ENET_MAC_LPI_CONTROL_STATUS_RLPIEX_MASK)
17866 
17867 #define ENET_MAC_LPI_CONTROL_STATUS_TLPIST_MASK  (0x100U)
17868 #define ENET_MAC_LPI_CONTROL_STATUS_TLPIST_SHIFT (8U)
17869 /*! TLPIST - Transmit LPI State
17870  *  0b1..Transmit LPI state detected
17871  *  0b0..Transmit LPI state not detected
17872  */
17873 #define ENET_MAC_LPI_CONTROL_STATUS_TLPIST(x)    (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CONTROL_STATUS_TLPIST_SHIFT)) & ENET_MAC_LPI_CONTROL_STATUS_TLPIST_MASK)
17874 
17875 #define ENET_MAC_LPI_CONTROL_STATUS_RLPIST_MASK  (0x200U)
17876 #define ENET_MAC_LPI_CONTROL_STATUS_RLPIST_SHIFT (9U)
17877 /*! RLPIST - Receive LPI State
17878  *  0b1..Receive LPI state detected
17879  *  0b0..Receive LPI state not detected
17880  */
17881 #define ENET_MAC_LPI_CONTROL_STATUS_RLPIST(x)    (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CONTROL_STATUS_RLPIST_SHIFT)) & ENET_MAC_LPI_CONTROL_STATUS_RLPIST_MASK)
17882 
17883 #define ENET_MAC_LPI_CONTROL_STATUS_LPIEN_MASK   (0x10000U)
17884 #define ENET_MAC_LPI_CONTROL_STATUS_LPIEN_SHIFT  (16U)
17885 /*! LPIEN - LPI Enable
17886  *  0b0..LPI state is disabled
17887  *  0b1..LPI state is enabled
17888  */
17889 #define ENET_MAC_LPI_CONTROL_STATUS_LPIEN(x)     (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CONTROL_STATUS_LPIEN_SHIFT)) & ENET_MAC_LPI_CONTROL_STATUS_LPIEN_MASK)
17890 
17891 #define ENET_MAC_LPI_CONTROL_STATUS_PLS_MASK     (0x20000U)
17892 #define ENET_MAC_LPI_CONTROL_STATUS_PLS_SHIFT    (17U)
17893 /*! PLS - PHY Link Status
17894  *  0b0..link is down
17895  *  0b1..link is okay (UP)
17896  */
17897 #define ENET_MAC_LPI_CONTROL_STATUS_PLS(x)       (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CONTROL_STATUS_PLS_SHIFT)) & ENET_MAC_LPI_CONTROL_STATUS_PLS_MASK)
17898 
17899 #define ENET_MAC_LPI_CONTROL_STATUS_LPITXA_MASK  (0x80000U)
17900 #define ENET_MAC_LPI_CONTROL_STATUS_LPITXA_SHIFT (19U)
17901 /*! LPITXA - LPI Tx Automate
17902  *  0b0..LPI Tx Automate is disabled
17903  *  0b1..LPI Tx Automate is enabled
17904  */
17905 #define ENET_MAC_LPI_CONTROL_STATUS_LPITXA(x)    (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CONTROL_STATUS_LPITXA_SHIFT)) & ENET_MAC_LPI_CONTROL_STATUS_LPITXA_MASK)
17906 
17907 #define ENET_MAC_LPI_CONTROL_STATUS_LPIATE_MASK  (0x100000U)
17908 #define ENET_MAC_LPI_CONTROL_STATUS_LPIATE_SHIFT (20U)
17909 /*! LPIATE - LPI Timer Enable
17910  *  0b0..LPI Timer is disabled
17911  *  0b1..LPI Timer is enabled
17912  */
17913 #define ENET_MAC_LPI_CONTROL_STATUS_LPIATE(x)    (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CONTROL_STATUS_LPIATE_SHIFT)) & ENET_MAC_LPI_CONTROL_STATUS_LPIATE_MASK)
17914 
17915 #define ENET_MAC_LPI_CONTROL_STATUS_LPITCSE_MASK (0x200000U)
17916 #define ENET_MAC_LPI_CONTROL_STATUS_LPITCSE_SHIFT (21U)
17917 /*! LPITCSE - LPI Tx Clock Stop Enable
17918  *  0b0..LPI Tx Clock Stop is disabled
17919  *  0b1..LPI Tx Clock Stop is enabled
17920  */
17921 #define ENET_MAC_LPI_CONTROL_STATUS_LPITCSE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CONTROL_STATUS_LPITCSE_SHIFT)) & ENET_MAC_LPI_CONTROL_STATUS_LPITCSE_MASK)
17922 /*! @} */
17923 
17924 /*! @name MAC_LPI_TIMERS_CONTROL - LPI Timers Control */
17925 /*! @{ */
17926 
17927 #define ENET_MAC_LPI_TIMERS_CONTROL_TWT_MASK     (0xFFFFU)
17928 #define ENET_MAC_LPI_TIMERS_CONTROL_TWT_SHIFT    (0U)
17929 /*! TWT - LPI TW Timer */
17930 #define ENET_MAC_LPI_TIMERS_CONTROL_TWT(x)       (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_TIMERS_CONTROL_TWT_SHIFT)) & ENET_MAC_LPI_TIMERS_CONTROL_TWT_MASK)
17931 
17932 #define ENET_MAC_LPI_TIMERS_CONTROL_LST_MASK     (0x3FF0000U)
17933 #define ENET_MAC_LPI_TIMERS_CONTROL_LST_SHIFT    (16U)
17934 /*! LST - LPI LS Timer */
17935 #define ENET_MAC_LPI_TIMERS_CONTROL_LST(x)       (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_TIMERS_CONTROL_LST_SHIFT)) & ENET_MAC_LPI_TIMERS_CONTROL_LST_MASK)
17936 /*! @} */
17937 
17938 /*! @name MAC_LPI_ENTRY_TIMER - Tx LPI Entry Timer Control */
17939 /*! @{ */
17940 
17941 #define ENET_MAC_LPI_ENTRY_TIMER_LPIET_MASK      (0xFFFF8U)
17942 #define ENET_MAC_LPI_ENTRY_TIMER_LPIET_SHIFT     (3U)
17943 /*! LPIET - LPI Entry Timer */
17944 #define ENET_MAC_LPI_ENTRY_TIMER_LPIET(x)        (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_ENTRY_TIMER_LPIET_SHIFT)) & ENET_MAC_LPI_ENTRY_TIMER_LPIET_MASK)
17945 /*! @} */
17946 
17947 /*! @name MAC_ONEUS_TIC_COUNTER - One-microsecond Reference Timer */
17948 /*! @{ */
17949 
17950 #define ENET_MAC_ONEUS_TIC_COUNTER_TIC_1US_CNTR_MASK (0xFFFU)
17951 #define ENET_MAC_ONEUS_TIC_COUNTER_TIC_1US_CNTR_SHIFT (0U)
17952 /*! TIC_1US_CNTR - 1US TIC Counter */
17953 #define ENET_MAC_ONEUS_TIC_COUNTER_TIC_1US_CNTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_ONEUS_TIC_COUNTER_TIC_1US_CNTR_SHIFT)) & ENET_MAC_ONEUS_TIC_COUNTER_TIC_1US_CNTR_MASK)
17954 /*! @} */
17955 
17956 /*! @name MAC_VERSION - MAC Version */
17957 /*! @{ */
17958 
17959 #define ENET_MAC_VERSION_SNPSVER_MASK            (0xFFU)
17960 #define ENET_MAC_VERSION_SNPSVER_SHIFT           (0U)
17961 /*! SNPSVER - Synopsys-defined Version */
17962 #define ENET_MAC_VERSION_SNPSVER(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VERSION_SNPSVER_SHIFT)) & ENET_MAC_VERSION_SNPSVER_MASK)
17963 
17964 #define ENET_MAC_VERSION_USERVER_MASK            (0xFF00U)
17965 #define ENET_MAC_VERSION_USERVER_SHIFT           (8U)
17966 /*! USERVER - User-defined Version */
17967 #define ENET_MAC_VERSION_USERVER(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VERSION_USERVER_SHIFT)) & ENET_MAC_VERSION_USERVER_MASK)
17968 /*! @} */
17969 
17970 /*! @name MAC_DEBUG - MAC Debug */
17971 /*! @{ */
17972 
17973 #define ENET_MAC_DEBUG_RPESTS_MASK               (0x1U)
17974 #define ENET_MAC_DEBUG_RPESTS_SHIFT              (0U)
17975 /*! RPESTS - MAC GMII or MII Receive Protocol Engine Status
17976  *  0b1..MAC GMII or MII Receive Protocol Engine Status detected
17977  *  0b0..MAC GMII or MII Receive Protocol Engine Status not detected
17978  */
17979 #define ENET_MAC_DEBUG_RPESTS(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_MAC_DEBUG_RPESTS_SHIFT)) & ENET_MAC_DEBUG_RPESTS_MASK)
17980 
17981 #define ENET_MAC_DEBUG_RFCFCSTS_MASK             (0x6U)
17982 #define ENET_MAC_DEBUG_RFCFCSTS_SHIFT            (1U)
17983 /*! RFCFCSTS - MAC Receive Packet Controller FIFO Status */
17984 #define ENET_MAC_DEBUG_RFCFCSTS(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_DEBUG_RFCFCSTS_SHIFT)) & ENET_MAC_DEBUG_RFCFCSTS_MASK)
17985 
17986 #define ENET_MAC_DEBUG_TPESTS_MASK               (0x10000U)
17987 #define ENET_MAC_DEBUG_TPESTS_SHIFT              (16U)
17988 /*! TPESTS - MAC GMII or MII Transmit Protocol Engine Status
17989  *  0b1..MAC GMII or MII Transmit Protocol Engine Status detected
17990  *  0b0..MAC GMII or MII Transmit Protocol Engine Status not detected
17991  */
17992 #define ENET_MAC_DEBUG_TPESTS(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_MAC_DEBUG_TPESTS_SHIFT)) & ENET_MAC_DEBUG_TPESTS_MASK)
17993 
17994 #define ENET_MAC_DEBUG_TFCSTS_MASK               (0x60000U)
17995 #define ENET_MAC_DEBUG_TFCSTS_SHIFT              (17U)
17996 /*! TFCSTS - MAC Transmit Packet Controller Status
17997  *  0b10..Generating and transmitting a Pause control packet (in full-duplex mode)
17998  *  0b00..Idle state
17999  *  0b11..Transferring input packet for transmission
18000  *  0b01..Waiting for one of the following: Status of the previous packet OR IPG or back off period to be over
18001  */
18002 #define ENET_MAC_DEBUG_TFCSTS(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_MAC_DEBUG_TFCSTS_SHIFT)) & ENET_MAC_DEBUG_TFCSTS_MASK)
18003 /*! @} */
18004 
18005 /*! @name MAC_HW_FEAT - Hardware Features 0..Hardware Features 3 */
18006 /*! @{ */
18007 
18008 #define ENET_MAC_HW_FEAT_MIISEL_MASK             (0x1U)
18009 #define ENET_MAC_HW_FEAT_MIISEL_SHIFT            (0U)
18010 /*! MIISEL - 10 or 100 Mbps Support
18011  *  0b1..10 or 100 Mbps support
18012  *  0b0..No 10 or 100 Mbps support
18013  */
18014 #define ENET_MAC_HW_FEAT_MIISEL(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_MIISEL_SHIFT)) & ENET_MAC_HW_FEAT_MIISEL_MASK)
18015 
18016 #define ENET_MAC_HW_FEAT_NRVF_MASK               (0x7U)
18017 #define ENET_MAC_HW_FEAT_NRVF_SHIFT              (0U)
18018 /*! NRVF - Number of Extended VLAN Tag Filters Enabled
18019  *  0b011..16 Extended Rx VLAN Filters
18020  *  0b100..24 Extended Rx VLAN Filters
18021  *  0b101..32 Extended Rx VLAN Filters
18022  *  0b001..4 Extended Rx VLAN Filters
18023  *  0b010..8 Extended Rx VLAN Filters
18024  *  0b000..No Extended Rx VLAN Filters
18025  *  0b110..Reserved
18026  */
18027 #define ENET_MAC_HW_FEAT_NRVF(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_NRVF_SHIFT)) & ENET_MAC_HW_FEAT_NRVF_MASK)
18028 
18029 #define ENET_MAC_HW_FEAT_RXFIFOSIZE_MASK         (0x1FU)
18030 #define ENET_MAC_HW_FEAT_RXFIFOSIZE_SHIFT        (0U)
18031 /*! RXFIFOSIZE - MTL Receive FIFO Size
18032  *  0b00011..1024 bytes
18033  *  0b00000..128 bytes
18034  *  0b01010..128 KB
18035  *  0b00111..16384 bytes
18036  *  0b00100..2048 bytes
18037  *  0b00001..256 bytes
18038  *  0b01011..256 KB
18039  *  0b01000..32 KB
18040  *  0b00101..4096 bytes
18041  *  0b00010..512 bytes
18042  *  0b01001..64 KB
18043  *  0b00110..8192 bytes
18044  *  0b01100..Reserved
18045  */
18046 #define ENET_MAC_HW_FEAT_RXFIFOSIZE(x)           (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RXFIFOSIZE_SHIFT)) & ENET_MAC_HW_FEAT_RXFIFOSIZE_MASK)
18047 
18048 #define ENET_MAC_HW_FEAT_RXQCNT_MASK             (0xFU)
18049 #define ENET_MAC_HW_FEAT_RXQCNT_SHIFT            (0U)
18050 /*! RXQCNT - Number of MTL Receive Queues
18051  *  0b0000..1 MTL Rx Queue
18052  *  0b0001..2 MTL Rx Queues
18053  *  0b0010..3 MTL Rx Queues
18054  *  0b0011..4 MTL Rx Queues
18055  *  0b0100..5 MTL Rx Queues
18056  *  0b0101..6 MTL Rx Queues
18057  *  0b0110..7 MTL Rx Queues
18058  *  0b0111..8 MTL Rx Queues
18059  */
18060 #define ENET_MAC_HW_FEAT_RXQCNT(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RXQCNT_SHIFT)) & ENET_MAC_HW_FEAT_RXQCNT_MASK)
18061 
18062 #define ENET_MAC_HW_FEAT_GMIISEL_MASK            (0x2U)
18063 #define ENET_MAC_HW_FEAT_GMIISEL_SHIFT           (1U)
18064 /*! GMIISEL - 1000 Mbps Support
18065  *  0b1..1000 Mbps support
18066  *  0b0..No 1000 Mbps support
18067  */
18068 #define ENET_MAC_HW_FEAT_GMIISEL(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_GMIISEL_SHIFT)) & ENET_MAC_HW_FEAT_GMIISEL_MASK)
18069 
18070 #define ENET_MAC_HW_FEAT_HDSEL_MASK              (0x4U)
18071 #define ENET_MAC_HW_FEAT_HDSEL_SHIFT             (2U)
18072 /*! HDSEL - Half-duplex Support
18073  *  0b1..Half-duplex support
18074  *  0b0..No Half-duplex support
18075  */
18076 #define ENET_MAC_HW_FEAT_HDSEL(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_HDSEL_SHIFT)) & ENET_MAC_HW_FEAT_HDSEL_MASK)
18077 
18078 #define ENET_MAC_HW_FEAT_PCSSEL_MASK             (0x8U)
18079 #define ENET_MAC_HW_FEAT_PCSSEL_SHIFT            (3U)
18080 /*! PCSSEL - PCS Registers (TBI, SGMII, or RTBI PHY interface)
18081  *  0b1..PCS Registers (TBI, SGMII, or RTBI PHY interface)
18082  *  0b0..No PCS Registers (TBI, SGMII, or RTBI PHY interface)
18083  */
18084 #define ENET_MAC_HW_FEAT_PCSSEL(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_PCSSEL_SHIFT)) & ENET_MAC_HW_FEAT_PCSSEL_MASK)
18085 
18086 #define ENET_MAC_HW_FEAT_CBTISEL_MASK            (0x10U)
18087 #define ENET_MAC_HW_FEAT_CBTISEL_SHIFT           (4U)
18088 /*! CBTISEL - Queue/Channel based VLAN tag insertion on Tx Enable
18089  *  0b1..Enable Queue/Channel based VLAN tag insertion on Tx feature is selected
18090  *  0b0..Enable Queue/Channel based VLAN tag insertion on Tx feature is not selected
18091  */
18092 #define ENET_MAC_HW_FEAT_CBTISEL(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_CBTISEL_SHIFT)) & ENET_MAC_HW_FEAT_CBTISEL_MASK)
18093 
18094 #define ENET_MAC_HW_FEAT_VLHASH_MASK             (0x10U)
18095 #define ENET_MAC_HW_FEAT_VLHASH_SHIFT            (4U)
18096 /*! VLHASH - VLAN Hash Filter Selected
18097  *  0b1..VLAN Hash Filter selected
18098  *  0b0..VLAN Hash Filter not selected
18099  */
18100 #define ENET_MAC_HW_FEAT_VLHASH(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_VLHASH_SHIFT)) & ENET_MAC_HW_FEAT_VLHASH_MASK)
18101 
18102 #define ENET_MAC_HW_FEAT_DVLAN_MASK              (0x20U)
18103 #define ENET_MAC_HW_FEAT_DVLAN_SHIFT             (5U)
18104 /*! DVLAN - Double VLAN Tag Processing Selected
18105  *  0b1..Double VLAN option is selected
18106  *  0b0..Double VLAN option is not selected
18107  */
18108 #define ENET_MAC_HW_FEAT_DVLAN(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_DVLAN_SHIFT)) & ENET_MAC_HW_FEAT_DVLAN_MASK)
18109 
18110 #define ENET_MAC_HW_FEAT_SMASEL_MASK             (0x20U)
18111 #define ENET_MAC_HW_FEAT_SMASEL_SHIFT            (5U)
18112 /*! SMASEL - SMA (MDIO) Interface
18113  *  0b1..SMA (MDIO) Interface selected
18114  *  0b0..SMA (MDIO) Interface not selected
18115  */
18116 #define ENET_MAC_HW_FEAT_SMASEL(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_SMASEL_SHIFT)) & ENET_MAC_HW_FEAT_SMASEL_MASK)
18117 
18118 #define ENET_MAC_HW_FEAT_SPRAM_MASK              (0x20U)
18119 #define ENET_MAC_HW_FEAT_SPRAM_SHIFT             (5U)
18120 /*! SPRAM - Single Port RAM Enable
18121  *  0b1..Single Port RAM feature is selected
18122  *  0b0..Single Port RAM feature is not selected
18123  */
18124 #define ENET_MAC_HW_FEAT_SPRAM(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_SPRAM_SHIFT)) & ENET_MAC_HW_FEAT_SPRAM_MASK)
18125 
18126 #define ENET_MAC_HW_FEAT_RWKSEL_MASK             (0x40U)
18127 #define ENET_MAC_HW_FEAT_RWKSEL_SHIFT            (6U)
18128 /*! RWKSEL - PMT Remote Wake-up Packet Enable
18129  *  0b1..PMT Remote Wake-up Packet Enable option is selected
18130  *  0b0..PMT Remote Wake-up Packet Enable option is not selected
18131  */
18132 #define ENET_MAC_HW_FEAT_RWKSEL(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RWKSEL_SHIFT)) & ENET_MAC_HW_FEAT_RWKSEL_MASK)
18133 
18134 #define ENET_MAC_HW_FEAT_TXFIFOSIZE_MASK         (0x7C0U)
18135 #define ENET_MAC_HW_FEAT_TXFIFOSIZE_SHIFT        (6U)
18136 /*! TXFIFOSIZE - MTL Transmit FIFO Size
18137  *  0b00011..1024 bytes
18138  *  0b00000..128 bytes
18139  *  0b01010..128 KB
18140  *  0b00111..16384 bytes
18141  *  0b00100..2048 bytes
18142  *  0b00001..256 bytes
18143  *  0b01000..32 KB
18144  *  0b00101..4096 bytes
18145  *  0b00010..512 bytes
18146  *  0b01001..64 KB
18147  *  0b00110..8192 bytes
18148  *  0b01011..Reserved
18149  */
18150 #define ENET_MAC_HW_FEAT_TXFIFOSIZE(x)           (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TXFIFOSIZE_SHIFT)) & ENET_MAC_HW_FEAT_TXFIFOSIZE_MASK)
18151 
18152 #define ENET_MAC_HW_FEAT_TXQCNT_MASK             (0x3C0U)
18153 #define ENET_MAC_HW_FEAT_TXQCNT_SHIFT            (6U)
18154 /*! TXQCNT - Number of MTL Transmit Queues
18155  *  0b0000..1 MTL Tx Queue
18156  *  0b0001..2 MTL Tx Queues
18157  *  0b0010..3 MTL Tx Queues
18158  *  0b0011..4 MTL Tx Queues
18159  *  0b0100..5 MTL Tx Queues
18160  *  0b0101..6 MTL Tx Queues
18161  *  0b0110..7 MTL Tx Queues
18162  *  0b0111..8 MTL Tx Queues
18163  */
18164 #define ENET_MAC_HW_FEAT_TXQCNT(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TXQCNT_SHIFT)) & ENET_MAC_HW_FEAT_TXQCNT_MASK)
18165 
18166 #define ENET_MAC_HW_FEAT_MGKSEL_MASK             (0x80U)
18167 #define ENET_MAC_HW_FEAT_MGKSEL_SHIFT            (7U)
18168 /*! MGKSEL - PMT Magic Packet Enable
18169  *  0b1..PMT Magic Packet Enable option is selected
18170  *  0b0..PMT Magic Packet Enable option is not selected
18171  */
18172 #define ENET_MAC_HW_FEAT_MGKSEL(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_MGKSEL_SHIFT)) & ENET_MAC_HW_FEAT_MGKSEL_MASK)
18173 
18174 #define ENET_MAC_HW_FEAT_MMCSEL_MASK             (0x100U)
18175 #define ENET_MAC_HW_FEAT_MMCSEL_SHIFT            (8U)
18176 /*! MMCSEL - RMON Module Enable
18177  *  0b1..RMON Module Enable option is selected
18178  *  0b0..RMON Module Enable option is not selected
18179  */
18180 #define ENET_MAC_HW_FEAT_MMCSEL(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_MMCSEL_SHIFT)) & ENET_MAC_HW_FEAT_MMCSEL_MASK)
18181 
18182 #define ENET_MAC_HW_FEAT_ARPOFFSEL_MASK          (0x200U)
18183 #define ENET_MAC_HW_FEAT_ARPOFFSEL_SHIFT         (9U)
18184 /*! ARPOFFSEL - ARP Offload Enabled
18185  *  0b1..ARP Offload Enable option is selected
18186  *  0b0..ARP Offload Enable option is not selected
18187  */
18188 #define ENET_MAC_HW_FEAT_ARPOFFSEL(x)            (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ARPOFFSEL_SHIFT)) & ENET_MAC_HW_FEAT_ARPOFFSEL_MASK)
18189 
18190 #define ENET_MAC_HW_FEAT_PDUPSEL_MASK            (0x200U)
18191 #define ENET_MAC_HW_FEAT_PDUPSEL_SHIFT           (9U)
18192 /*! PDUPSEL - Broadcast/Multicast Packet Duplication
18193  *  0b1..Broadcast/Multicast Packet Duplication feature is selected
18194  *  0b0..Broadcast/Multicast Packet Duplication feature is not selected
18195  */
18196 #define ENET_MAC_HW_FEAT_PDUPSEL(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_PDUPSEL_SHIFT)) & ENET_MAC_HW_FEAT_PDUPSEL_MASK)
18197 
18198 #define ENET_MAC_HW_FEAT_FRPSEL_MASK             (0x400U)
18199 #define ENET_MAC_HW_FEAT_FRPSEL_SHIFT            (10U)
18200 /*! FRPSEL - Flexible Receive Parser Selected
18201  *  0b1..Flexible Receive Parser feature is selected
18202  *  0b0..Flexible Receive Parser feature is not selected
18203  */
18204 #define ENET_MAC_HW_FEAT_FRPSEL(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_FRPSEL_SHIFT)) & ENET_MAC_HW_FEAT_FRPSEL_MASK)
18205 
18206 #define ENET_MAC_HW_FEAT_FRPBS_MASK              (0x1800U)
18207 #define ENET_MAC_HW_FEAT_FRPBS_SHIFT             (11U)
18208 /*! FRPBS - Flexible Receive Parser Buffer size
18209  *  0b01..128 Bytes
18210  *  0b10..256 Bytes
18211  *  0b00..64 Bytes
18212  *  0b11..Reserved
18213  */
18214 #define ENET_MAC_HW_FEAT_FRPBS(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_FRPBS_SHIFT)) & ENET_MAC_HW_FEAT_FRPBS_MASK)
18215 
18216 #define ENET_MAC_HW_FEAT_OSTEN_MASK              (0x800U)
18217 #define ENET_MAC_HW_FEAT_OSTEN_SHIFT             (11U)
18218 /*! OSTEN - One-Step Timestamping Enable
18219  *  0b1..One-Step Timestamping feature is selected
18220  *  0b0..One-Step Timestamping feature is not selected
18221  */
18222 #define ENET_MAC_HW_FEAT_OSTEN(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_OSTEN_SHIFT)) & ENET_MAC_HW_FEAT_OSTEN_MASK)
18223 
18224 #define ENET_MAC_HW_FEAT_PTOEN_MASK              (0x1000U)
18225 #define ENET_MAC_HW_FEAT_PTOEN_SHIFT             (12U)
18226 /*! PTOEN - PTP Offload Enable
18227  *  0b1..PTP Offload feature is selected
18228  *  0b0..PTP Offload feature is not selected
18229  */
18230 #define ENET_MAC_HW_FEAT_PTOEN(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_PTOEN_SHIFT)) & ENET_MAC_HW_FEAT_PTOEN_MASK)
18231 
18232 #define ENET_MAC_HW_FEAT_RXCHCNT_MASK            (0xF000U)
18233 #define ENET_MAC_HW_FEAT_RXCHCNT_SHIFT           (12U)
18234 /*! RXCHCNT - Number of DMA Receive Channels
18235  *  0b0000..1 MTL Rx Channel
18236  *  0b0001..2 MTL Rx Channels
18237  *  0b0010..3 MTL Rx Channels
18238  *  0b0011..4 MTL Rx Channels
18239  *  0b0100..5 MTL Rx Channels
18240  *  0b0101..6 MTL Rx Channels
18241  *  0b0110..7 MTL Rx Channels
18242  *  0b0111..8 MTL Rx Channels
18243  */
18244 #define ENET_MAC_HW_FEAT_RXCHCNT(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RXCHCNT_SHIFT)) & ENET_MAC_HW_FEAT_RXCHCNT_MASK)
18245 
18246 #define ENET_MAC_HW_FEAT_TSSEL_MASK              (0x1000U)
18247 #define ENET_MAC_HW_FEAT_TSSEL_SHIFT             (12U)
18248 /*! TSSEL - IEEE 1588-2008 Timestamp Enabled
18249  *  0b1..IEEE 1588-2008 Timestamp Enable option is selected
18250  *  0b0..IEEE 1588-2008 Timestamp Enable option is not selected
18251  */
18252 #define ENET_MAC_HW_FEAT_TSSEL(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TSSEL_SHIFT)) & ENET_MAC_HW_FEAT_TSSEL_MASK)
18253 
18254 #define ENET_MAC_HW_FEAT_ADVTHWORD_MASK          (0x2000U)
18255 #define ENET_MAC_HW_FEAT_ADVTHWORD_SHIFT         (13U)
18256 /*! ADVTHWORD - IEEE 1588 High Word Register Enable
18257  *  0b1..IEEE 1588 High Word Register option is selected
18258  *  0b0..IEEE 1588 High Word Register option is not selected
18259  */
18260 #define ENET_MAC_HW_FEAT_ADVTHWORD(x)            (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ADVTHWORD_SHIFT)) & ENET_MAC_HW_FEAT_ADVTHWORD_MASK)
18261 
18262 #define ENET_MAC_HW_FEAT_EEESEL_MASK             (0x2000U)
18263 #define ENET_MAC_HW_FEAT_EEESEL_SHIFT            (13U)
18264 /*! EEESEL - Energy Efficient Ethernet Enabled
18265  *  0b1..Energy Efficient Ethernet Enable option is selected
18266  *  0b0..Energy Efficient Ethernet Enable option is not selected
18267  */
18268 #define ENET_MAC_HW_FEAT_EEESEL(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_EEESEL_SHIFT)) & ENET_MAC_HW_FEAT_EEESEL_MASK)
18269 
18270 #define ENET_MAC_HW_FEAT_FRPES_MASK              (0x6000U)
18271 #define ENET_MAC_HW_FEAT_FRPES_SHIFT             (13U)
18272 /*! FRPES - Flexible Receive Parser Table Entries size
18273  *  0b01..128 Entries
18274  *  0b10..256 Entries
18275  *  0b00..64 Entries
18276  *  0b11..Reserved
18277  */
18278 #define ENET_MAC_HW_FEAT_FRPES(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_FRPES_SHIFT)) & ENET_MAC_HW_FEAT_FRPES_MASK)
18279 
18280 #define ENET_MAC_HW_FEAT_ADDR64_MASK             (0xC000U)
18281 #define ENET_MAC_HW_FEAT_ADDR64_SHIFT            (14U)
18282 /*! ADDR64 - Address Width.
18283  *  0b00..32
18284  *  0b01..40
18285  *  0b10..48
18286  *  0b11..Reserved
18287  */
18288 #define ENET_MAC_HW_FEAT_ADDR64(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ADDR64_SHIFT)) & ENET_MAC_HW_FEAT_ADDR64_MASK)
18289 
18290 #define ENET_MAC_HW_FEAT_TXCOESEL_MASK           (0x4000U)
18291 #define ENET_MAC_HW_FEAT_TXCOESEL_SHIFT          (14U)
18292 /*! TXCOESEL - Transmit Checksum Offload Enabled
18293  *  0b1..Transmit Checksum Offload Enable option is selected
18294  *  0b0..Transmit Checksum Offload Enable option is not selected
18295  */
18296 #define ENET_MAC_HW_FEAT_TXCOESEL(x)             (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TXCOESEL_SHIFT)) & ENET_MAC_HW_FEAT_TXCOESEL_MASK)
18297 
18298 #define ENET_MAC_HW_FEAT_DCBEN_MASK              (0x10000U)
18299 #define ENET_MAC_HW_FEAT_DCBEN_SHIFT             (16U)
18300 /*! DCBEN - DCB Feature Enable
18301  *  0b1..DCB Feature is selected
18302  *  0b0..DCB Feature is not selected
18303  */
18304 #define ENET_MAC_HW_FEAT_DCBEN(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_DCBEN_SHIFT)) & ENET_MAC_HW_FEAT_DCBEN_MASK)
18305 
18306 #define ENET_MAC_HW_FEAT_ESTSEL_MASK             (0x10000U)
18307 #define ENET_MAC_HW_FEAT_ESTSEL_SHIFT            (16U)
18308 /*! ESTSEL - Enhancements to Scheduled Traffic Enable
18309  *  0b1..Enable Enhancements to Scheduling Traffic feature is selected
18310  *  0b0..Enable Enhancements to Scheduling Traffic feature is not selected
18311  */
18312 #define ENET_MAC_HW_FEAT_ESTSEL(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ESTSEL_SHIFT)) & ENET_MAC_HW_FEAT_ESTSEL_MASK)
18313 
18314 #define ENET_MAC_HW_FEAT_RDCSZ_MASK              (0x30000U)
18315 #define ENET_MAC_HW_FEAT_RDCSZ_SHIFT             (16U)
18316 /*! RDCSZ - Rx DMA Descriptor Cache Size in terms of 16 bytes descriptors: */
18317 #define ENET_MAC_HW_FEAT_RDCSZ(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RDCSZ_SHIFT)) & ENET_MAC_HW_FEAT_RDCSZ_MASK)
18318 
18319 #define ENET_MAC_HW_FEAT_RXCOESEL_MASK           (0x10000U)
18320 #define ENET_MAC_HW_FEAT_RXCOESEL_SHIFT          (16U)
18321 /*! RXCOESEL - Receive Checksum Offload Enabled
18322  *  0b1..Receive Checksum Offload Enable option is selected
18323  *  0b0..Receive Checksum Offload Enable option is not selected
18324  */
18325 #define ENET_MAC_HW_FEAT_RXCOESEL(x)             (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RXCOESEL_SHIFT)) & ENET_MAC_HW_FEAT_RXCOESEL_MASK)
18326 
18327 #define ENET_MAC_HW_FEAT_ESTDEP_MASK             (0xE0000U)
18328 #define ENET_MAC_HW_FEAT_ESTDEP_SHIFT            (17U)
18329 /*! ESTDEP - Depth of the Gate Control List
18330  *  0b101..1024
18331  *  0b010..128
18332  *  0b011..256
18333  *  0b100..512
18334  *  0b001..64
18335  *  0b000..No Depth configured
18336  *  0b110..Reserved
18337  */
18338 #define ENET_MAC_HW_FEAT_ESTDEP(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ESTDEP_SHIFT)) & ENET_MAC_HW_FEAT_ESTDEP_MASK)
18339 
18340 #define ENET_MAC_HW_FEAT_SPHEN_MASK              (0x20000U)
18341 #define ENET_MAC_HW_FEAT_SPHEN_SHIFT             (17U)
18342 /*! SPHEN - Split Header Feature Enable
18343  *  0b1..Split Header Feature is selected
18344  *  0b0..Split Header Feature is not selected
18345  */
18346 #define ENET_MAC_HW_FEAT_SPHEN(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_SPHEN_SHIFT)) & ENET_MAC_HW_FEAT_SPHEN_MASK)
18347 
18348 #define ENET_MAC_HW_FEAT_ADDMACADRSEL_MASK       (0x7C0000U)
18349 #define ENET_MAC_HW_FEAT_ADDMACADRSEL_SHIFT      (18U)
18350 /*! ADDMACADRSEL - MAC Addresses 1-31 Selected */
18351 #define ENET_MAC_HW_FEAT_ADDMACADRSEL(x)         (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ADDMACADRSEL_SHIFT)) & ENET_MAC_HW_FEAT_ADDMACADRSEL_MASK)
18352 
18353 #define ENET_MAC_HW_FEAT_TSOEN_MASK              (0x40000U)
18354 #define ENET_MAC_HW_FEAT_TSOEN_SHIFT             (18U)
18355 /*! TSOEN - TCP Segmentation Offload Enable
18356  *  0b1..TCP Segmentation Offload Feature is selected
18357  *  0b0..TCP Segmentation Offload Feature is not selected
18358  */
18359 #define ENET_MAC_HW_FEAT_TSOEN(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TSOEN_SHIFT)) & ENET_MAC_HW_FEAT_TSOEN_MASK)
18360 
18361 #define ENET_MAC_HW_FEAT_TXCHCNT_MASK            (0x3C0000U)
18362 #define ENET_MAC_HW_FEAT_TXCHCNT_SHIFT           (18U)
18363 /*! TXCHCNT - Number of DMA Transmit Channels
18364  *  0b0000..1 MTL Tx Channel
18365  *  0b0001..2 MTL Tx Channels
18366  *  0b0010..3 MTL Tx Channels
18367  *  0b0011..4 MTL Tx Channels
18368  *  0b0100..5 MTL Tx Channels
18369  *  0b0101..6 MTL Tx Channels
18370  *  0b0110..7 MTL Tx Channels
18371  *  0b0111..8 MTL Tx Channels
18372  */
18373 #define ENET_MAC_HW_FEAT_TXCHCNT(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TXCHCNT_SHIFT)) & ENET_MAC_HW_FEAT_TXCHCNT_MASK)
18374 
18375 #define ENET_MAC_HW_FEAT_DBGMEMA_MASK            (0x80000U)
18376 #define ENET_MAC_HW_FEAT_DBGMEMA_SHIFT           (19U)
18377 /*! DBGMEMA - DMA Debug Registers Enable
18378  *  0b1..DMA Debug Registers option is selected
18379  *  0b0..DMA Debug Registers option is not selected
18380  */
18381 #define ENET_MAC_HW_FEAT_DBGMEMA(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_DBGMEMA_SHIFT)) & ENET_MAC_HW_FEAT_DBGMEMA_MASK)
18382 
18383 #define ENET_MAC_HW_FEAT_AVSEL_MASK              (0x100000U)
18384 #define ENET_MAC_HW_FEAT_AVSEL_SHIFT             (20U)
18385 /*! AVSEL - AV Feature Enable
18386  *  0b1..AV Feature is selected
18387  *  0b0..AV Feature is not selected
18388  */
18389 #define ENET_MAC_HW_FEAT_AVSEL(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_AVSEL_SHIFT)) & ENET_MAC_HW_FEAT_AVSEL_MASK)
18390 
18391 #define ENET_MAC_HW_FEAT_ESTWID_MASK             (0x300000U)
18392 #define ENET_MAC_HW_FEAT_ESTWID_SHIFT            (20U)
18393 /*! ESTWID - Width of the Time Interval field in the Gate Control List
18394  *  0b00..Width not configured
18395  *  0b01..16
18396  *  0b10..20
18397  *  0b11..24
18398  */
18399 #define ENET_MAC_HW_FEAT_ESTWID(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ESTWID_SHIFT)) & ENET_MAC_HW_FEAT_ESTWID_MASK)
18400 
18401 #define ENET_MAC_HW_FEAT_RAVSEL_MASK             (0x200000U)
18402 #define ENET_MAC_HW_FEAT_RAVSEL_SHIFT            (21U)
18403 /*! RAVSEL - Rx Side Only AV Feature Enable
18404  *  0b1..Rx Side Only AV Feature is selected
18405  *  0b0..Rx Side Only AV Feature is not selected
18406  */
18407 #define ENET_MAC_HW_FEAT_RAVSEL(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RAVSEL_SHIFT)) & ENET_MAC_HW_FEAT_RAVSEL_MASK)
18408 
18409 #define ENET_MAC_HW_FEAT_TDCSZ_MASK              (0xC00000U)
18410 #define ENET_MAC_HW_FEAT_TDCSZ_SHIFT             (22U)
18411 /*! TDCSZ - Tx DMA Descriptor Cache Size in terms of 16 bytes descriptors: */
18412 #define ENET_MAC_HW_FEAT_TDCSZ(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TDCSZ_SHIFT)) & ENET_MAC_HW_FEAT_TDCSZ_MASK)
18413 
18414 #define ENET_MAC_HW_FEAT_MACADR32SEL_MASK        (0x800000U)
18415 #define ENET_MAC_HW_FEAT_MACADR32SEL_SHIFT       (23U)
18416 /*! MACADR32SEL - MAC Addresses 32-63 Selected
18417  *  0b1..MAC Addresses 32-63 Select option is selected
18418  *  0b0..MAC Addresses 32-63 Select option is not selected
18419  */
18420 #define ENET_MAC_HW_FEAT_MACADR32SEL(x)          (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_MACADR32SEL_SHIFT)) & ENET_MAC_HW_FEAT_MACADR32SEL_MASK)
18421 
18422 #define ENET_MAC_HW_FEAT_POUOST_MASK             (0x800000U)
18423 #define ENET_MAC_HW_FEAT_POUOST_SHIFT            (23U)
18424 /*! POUOST - One Step for PTP over UDP/IP Feature Enable
18425  *  0b1..One Step for PTP over UDP/IP Feature is selected
18426  *  0b0..One Step for PTP over UDP/IP Feature is not selected
18427  */
18428 #define ENET_MAC_HW_FEAT_POUOST(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_POUOST_SHIFT)) & ENET_MAC_HW_FEAT_POUOST_MASK)
18429 
18430 #define ENET_MAC_HW_FEAT_HASHTBLSZ_MASK          (0x3000000U)
18431 #define ENET_MAC_HW_FEAT_HASHTBLSZ_SHIFT         (24U)
18432 /*! HASHTBLSZ - Hash Table Size
18433  *  0b10..128
18434  *  0b11..256
18435  *  0b01..64
18436  *  0b00..No hash table
18437  */
18438 #define ENET_MAC_HW_FEAT_HASHTBLSZ(x)            (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_HASHTBLSZ_SHIFT)) & ENET_MAC_HW_FEAT_HASHTBLSZ_MASK)
18439 
18440 #define ENET_MAC_HW_FEAT_MACADR64SEL_MASK        (0x1000000U)
18441 #define ENET_MAC_HW_FEAT_MACADR64SEL_SHIFT       (24U)
18442 /*! MACADR64SEL - MAC Addresses 64-127 Selected
18443  *  0b1..MAC Addresses 64-127 Select option is selected
18444  *  0b0..MAC Addresses 64-127 Select option is not selected
18445  */
18446 #define ENET_MAC_HW_FEAT_MACADR64SEL(x)          (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_MACADR64SEL_SHIFT)) & ENET_MAC_HW_FEAT_MACADR64SEL_MASK)
18447 
18448 #define ENET_MAC_HW_FEAT_PPSOUTNUM_MASK          (0x7000000U)
18449 #define ENET_MAC_HW_FEAT_PPSOUTNUM_SHIFT         (24U)
18450 /*! PPSOUTNUM - Number of PPS Outputs
18451  *  0b001..1 PPS output
18452  *  0b010..2 PPS output
18453  *  0b011..3 PPS output
18454  *  0b100..4 PPS output
18455  *  0b000..No PPS output
18456  *  0b101..Reserved
18457  */
18458 #define ENET_MAC_HW_FEAT_PPSOUTNUM(x)            (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_PPSOUTNUM_SHIFT)) & ENET_MAC_HW_FEAT_PPSOUTNUM_MASK)
18459 
18460 #define ENET_MAC_HW_FEAT_TSSTSSEL_MASK           (0x6000000U)
18461 #define ENET_MAC_HW_FEAT_TSSTSSEL_SHIFT          (25U)
18462 /*! TSSTSSEL - Timestamp System Time Source
18463  *  0b10..Both
18464  *  0b01..External
18465  *  0b00..Internal
18466  *  0b11..Reserved
18467  */
18468 #define ENET_MAC_HW_FEAT_TSSTSSEL(x)             (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TSSTSSEL_SHIFT)) & ENET_MAC_HW_FEAT_TSSTSSEL_MASK)
18469 
18470 #define ENET_MAC_HW_FEAT_FPESEL_MASK             (0x4000000U)
18471 #define ENET_MAC_HW_FEAT_FPESEL_SHIFT            (26U)
18472 /*! FPESEL - Frame Preemption Enable
18473  *  0b1..Frame Preemption Enable feature is selected
18474  *  0b0..Frame Preemption Enable feature is not selected
18475  */
18476 #define ENET_MAC_HW_FEAT_FPESEL(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_FPESEL_SHIFT)) & ENET_MAC_HW_FEAT_FPESEL_MASK)
18477 
18478 #define ENET_MAC_HW_FEAT_L3L4FNUM_MASK           (0x78000000U)
18479 #define ENET_MAC_HW_FEAT_L3L4FNUM_SHIFT          (27U)
18480 /*! L3L4FNUM - Total number of L3 or L4 Filters
18481  *  0b0001..1 L3 or L4 Filter
18482  *  0b0010..2 L3 or L4 Filters
18483  *  0b0011..3 L3 or L4 Filters
18484  *  0b0100..4 L3 or L4 Filters
18485  *  0b0101..5 L3 or L4 Filters
18486  *  0b0110..6 L3 or L4 Filters
18487  *  0b0111..7 L3 or L4 Filters
18488  *  0b1000..8 L3 or L4 Filters
18489  *  0b0000..No L3 or L4 Filter
18490  */
18491 #define ENET_MAC_HW_FEAT_L3L4FNUM(x)             (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_L3L4FNUM_SHIFT)) & ENET_MAC_HW_FEAT_L3L4FNUM_MASK)
18492 
18493 #define ENET_MAC_HW_FEAT_SAVLANINS_MASK          (0x8000000U)
18494 #define ENET_MAC_HW_FEAT_SAVLANINS_SHIFT         (27U)
18495 /*! SAVLANINS - Source Address or VLAN Insertion Enable
18496  *  0b1..Source Address or VLAN Insertion Enable option is selected
18497  *  0b0..Source Address or VLAN Insertion Enable option is not selected
18498  */
18499 #define ENET_MAC_HW_FEAT_SAVLANINS(x)            (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_SAVLANINS_SHIFT)) & ENET_MAC_HW_FEAT_SAVLANINS_MASK)
18500 
18501 #define ENET_MAC_HW_FEAT_TBSSEL_MASK             (0x8000000U)
18502 #define ENET_MAC_HW_FEAT_TBSSEL_SHIFT            (27U)
18503 /*! TBSSEL - Time Based Scheduling Enable
18504  *  0b1..Time Based Scheduling Enable feature is selected
18505  *  0b0..Time Based Scheduling Enable feature is not selected
18506  */
18507 #define ENET_MAC_HW_FEAT_TBSSEL(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TBSSEL_SHIFT)) & ENET_MAC_HW_FEAT_TBSSEL_MASK)
18508 
18509 #define ENET_MAC_HW_FEAT_ACTPHYSEL_MASK          (0x70000000U)
18510 #define ENET_MAC_HW_FEAT_ACTPHYSEL_SHIFT         (28U)
18511 /*! ACTPHYSEL - Active PHY Selected
18512  *  0b000..GMII or MII
18513  *  0b111..RevMII
18514  *  0b001..RGMII
18515  *  0b100..RMII
18516  *  0b101..RTBI
18517  *  0b010..SGMII
18518  *  0b110..SMII
18519  *  0b011..TBI
18520  */
18521 #define ENET_MAC_HW_FEAT_ACTPHYSEL(x)            (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ACTPHYSEL_SHIFT)) & ENET_MAC_HW_FEAT_ACTPHYSEL_MASK)
18522 
18523 #define ENET_MAC_HW_FEAT_ASP_MASK                (0x30000000U)
18524 #define ENET_MAC_HW_FEAT_ASP_SHIFT               (28U)
18525 /*! ASP - Automotive Safety Package
18526  *  0b10..All the Automotive Safety features are selected without the "Parity Port Enable for external interface" feature
18527  *  0b11..All the Automotive Safety features are selected with the "Parity Port Enable for external interface" feature
18528  *  0b01..Only "ECC protection for external memory" feature is selected
18529  *  0b00..No Safety features selected
18530  */
18531 #define ENET_MAC_HW_FEAT_ASP(x)                  (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ASP_SHIFT)) & ENET_MAC_HW_FEAT_ASP_MASK)
18532 
18533 #define ENET_MAC_HW_FEAT_AUXSNAPNUM_MASK         (0x70000000U)
18534 #define ENET_MAC_HW_FEAT_AUXSNAPNUM_SHIFT        (28U)
18535 /*! AUXSNAPNUM - Number of Auxiliary Snapshot Inputs
18536  *  0b001..1 auxiliary input
18537  *  0b010..2 auxiliary input
18538  *  0b011..3 auxiliary input
18539  *  0b100..4 auxiliary input
18540  *  0b000..No auxiliary input
18541  *  0b101..Reserved
18542  */
18543 #define ENET_MAC_HW_FEAT_AUXSNAPNUM(x)           (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_AUXSNAPNUM_SHIFT)) & ENET_MAC_HW_FEAT_AUXSNAPNUM_MASK)
18544 /*! @} */
18545 
18546 /* The count of ENET_MAC_HW_FEAT */
18547 #define ENET_MAC_HW_FEAT_COUNT                   (4U)
18548 
18549 /*! @name MAC_MDIO_ADDRESS - MDIO Address */
18550 /*! @{ */
18551 
18552 #define ENET_MAC_MDIO_ADDRESS_GB_MASK            (0x1U)
18553 #define ENET_MAC_MDIO_ADDRESS_GB_SHIFT           (0U)
18554 /*! GB - GMII Busy
18555  *  0b0..GMII Busy is disabled
18556  *  0b1..GMII Busy is enabled
18557  */
18558 #define ENET_MAC_MDIO_ADDRESS_GB(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDRESS_GB_SHIFT)) & ENET_MAC_MDIO_ADDRESS_GB_MASK)
18559 
18560 #define ENET_MAC_MDIO_ADDRESS_C45E_MASK          (0x2U)
18561 #define ENET_MAC_MDIO_ADDRESS_C45E_SHIFT         (1U)
18562 /*! C45E - Clause 45 PHY Enable
18563  *  0b0..Clause 45 PHY is disabled
18564  *  0b1..Clause 45 PHY is enabled
18565  */
18566 #define ENET_MAC_MDIO_ADDRESS_C45E(x)            (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDRESS_C45E_SHIFT)) & ENET_MAC_MDIO_ADDRESS_C45E_MASK)
18567 
18568 #define ENET_MAC_MDIO_ADDRESS_GOC_0_MASK         (0x4U)
18569 #define ENET_MAC_MDIO_ADDRESS_GOC_0_SHIFT        (2U)
18570 /*! GOC_0 - GMII Operation Command 0
18571  *  0b0..GMII Operation Command 0 is disabled
18572  *  0b1..GMII Operation Command 0 is enabled
18573  */
18574 #define ENET_MAC_MDIO_ADDRESS_GOC_0(x)           (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDRESS_GOC_0_SHIFT)) & ENET_MAC_MDIO_ADDRESS_GOC_0_MASK)
18575 
18576 #define ENET_MAC_MDIO_ADDRESS_GOC_1_MASK         (0x8U)
18577 #define ENET_MAC_MDIO_ADDRESS_GOC_1_SHIFT        (3U)
18578 /*! GOC_1 - GMII Operation Command 1
18579  *  0b0..GMII Operation Command 1 is disabled
18580  *  0b1..GMII Operation Command 1 is enabled
18581  */
18582 #define ENET_MAC_MDIO_ADDRESS_GOC_1(x)           (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDRESS_GOC_1_SHIFT)) & ENET_MAC_MDIO_ADDRESS_GOC_1_MASK)
18583 
18584 #define ENET_MAC_MDIO_ADDRESS_SKAP_MASK          (0x10U)
18585 #define ENET_MAC_MDIO_ADDRESS_SKAP_SHIFT         (4U)
18586 /*! SKAP - Skip Address Packet
18587  *  0b0..Skip Address Packet is disabled
18588  *  0b1..Skip Address Packet is enabled
18589  */
18590 #define ENET_MAC_MDIO_ADDRESS_SKAP(x)            (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDRESS_SKAP_SHIFT)) & ENET_MAC_MDIO_ADDRESS_SKAP_MASK)
18591 
18592 #define ENET_MAC_MDIO_ADDRESS_CR_MASK            (0xF00U)
18593 #define ENET_MAC_MDIO_ADDRESS_CR_SHIFT           (8U)
18594 /*! CR - CR */
18595 #define ENET_MAC_MDIO_ADDRESS_CR(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDRESS_CR_SHIFT)) & ENET_MAC_MDIO_ADDRESS_CR_MASK)
18596 
18597 #define ENET_MAC_MDIO_ADDRESS_NTC_MASK           (0x7000U)
18598 #define ENET_MAC_MDIO_ADDRESS_NTC_SHIFT          (12U)
18599 /*! NTC - NTC */
18600 #define ENET_MAC_MDIO_ADDRESS_NTC(x)             (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDRESS_NTC_SHIFT)) & ENET_MAC_MDIO_ADDRESS_NTC_MASK)
18601 
18602 #define ENET_MAC_MDIO_ADDRESS_RDA_MASK           (0x1F0000U)
18603 #define ENET_MAC_MDIO_ADDRESS_RDA_SHIFT          (16U)
18604 /*! RDA - Register/Device Address */
18605 #define ENET_MAC_MDIO_ADDRESS_RDA(x)             (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDRESS_RDA_SHIFT)) & ENET_MAC_MDIO_ADDRESS_RDA_MASK)
18606 
18607 #define ENET_MAC_MDIO_ADDRESS_PA_MASK            (0x3E00000U)
18608 #define ENET_MAC_MDIO_ADDRESS_PA_SHIFT           (21U)
18609 /*! PA - Physical Layer Address */
18610 #define ENET_MAC_MDIO_ADDRESS_PA(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDRESS_PA_SHIFT)) & ENET_MAC_MDIO_ADDRESS_PA_MASK)
18611 
18612 #define ENET_MAC_MDIO_ADDRESS_BTB_MASK           (0x4000000U)
18613 #define ENET_MAC_MDIO_ADDRESS_BTB_SHIFT          (26U)
18614 /*! BTB - Back to Back transactions
18615  *  0b0..Back to Back transactions disabled
18616  *  0b1..Back to Back transactions enabled
18617  */
18618 #define ENET_MAC_MDIO_ADDRESS_BTB(x)             (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDRESS_BTB_SHIFT)) & ENET_MAC_MDIO_ADDRESS_BTB_MASK)
18619 
18620 #define ENET_MAC_MDIO_ADDRESS_PSE_MASK           (0x8000000U)
18621 #define ENET_MAC_MDIO_ADDRESS_PSE_SHIFT          (27U)
18622 /*! PSE - Preamble Suppression Enable
18623  *  0b0..Preamble Suppression disabled
18624  *  0b1..Preamble Suppression enabled
18625  */
18626 #define ENET_MAC_MDIO_ADDRESS_PSE(x)             (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDRESS_PSE_SHIFT)) & ENET_MAC_MDIO_ADDRESS_PSE_MASK)
18627 /*! @} */
18628 
18629 /*! @name MAC_MDIO_DATA - MAC MDIO Data */
18630 /*! @{ */
18631 
18632 #define ENET_MAC_MDIO_DATA_GD_MASK               (0xFFFFU)
18633 #define ENET_MAC_MDIO_DATA_GD_SHIFT              (0U)
18634 /*! GD - GMII Data */
18635 #define ENET_MAC_MDIO_DATA_GD(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_DATA_GD_SHIFT)) & ENET_MAC_MDIO_DATA_GD_MASK)
18636 
18637 #define ENET_MAC_MDIO_DATA_RA_MASK               (0xFFFF0000U)
18638 #define ENET_MAC_MDIO_DATA_RA_SHIFT              (16U)
18639 /*! RA - Register Address */
18640 #define ENET_MAC_MDIO_DATA_RA(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_DATA_RA_SHIFT)) & ENET_MAC_MDIO_DATA_RA_MASK)
18641 /*! @} */
18642 
18643 /*! @name MAC_CSR_SW_CTRL - CSR Software Control */
18644 /*! @{ */
18645 
18646 #define ENET_MAC_CSR_SW_CTRL_RCWE_MASK           (0x1U)
18647 #define ENET_MAC_CSR_SW_CTRL_RCWE_SHIFT          (0U)
18648 /*! RCWE - Register Clear on Write 1 Enable
18649  *  0b0..Register Clear on Write 1 is disabled
18650  *  0b1..Register Clear on Write 1 is enabled
18651  */
18652 #define ENET_MAC_CSR_SW_CTRL_RCWE(x)             (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CSR_SW_CTRL_RCWE_SHIFT)) & ENET_MAC_CSR_SW_CTRL_RCWE_MASK)
18653 /*! @} */
18654 
18655 /*! @name MAC_ADDRESS0_HIGH - MAC Address0 High */
18656 /*! @{ */
18657 
18658 #define ENET_MAC_ADDRESS0_HIGH_ADDRHI_MASK       (0xFFFFU)
18659 #define ENET_MAC_ADDRESS0_HIGH_ADDRHI_SHIFT      (0U)
18660 /*! ADDRHI - MAC Address0[47:32] */
18661 #define ENET_MAC_ADDRESS0_HIGH_ADDRHI(x)         (((uint32_t)(((uint32_t)(x)) << ENET_MAC_ADDRESS0_HIGH_ADDRHI_SHIFT)) & ENET_MAC_ADDRESS0_HIGH_ADDRHI_MASK)
18662 
18663 #define ENET_MAC_ADDRESS0_HIGH_DCS_MASK          (0x30000U)
18664 #define ENET_MAC_ADDRESS0_HIGH_DCS_SHIFT         (16U)
18665 /*! DCS - DMA Channel Select */
18666 #define ENET_MAC_ADDRESS0_HIGH_DCS(x)            (((uint32_t)(((uint32_t)(x)) << ENET_MAC_ADDRESS0_HIGH_DCS_SHIFT)) & ENET_MAC_ADDRESS0_HIGH_DCS_MASK)
18667 
18668 #define ENET_MAC_ADDRESS0_HIGH_AE_MASK           (0x80000000U)
18669 #define ENET_MAC_ADDRESS0_HIGH_AE_SHIFT          (31U)
18670 /*! AE - Address Enable
18671  *  0b0..INVALID : This bit must be always set to 1
18672  *  0b1..This bit is always set to 1
18673  */
18674 #define ENET_MAC_ADDRESS0_HIGH_AE(x)             (((uint32_t)(((uint32_t)(x)) << ENET_MAC_ADDRESS0_HIGH_AE_SHIFT)) & ENET_MAC_ADDRESS0_HIGH_AE_MASK)
18675 /*! @} */
18676 
18677 /*! @name MAC_ADDRESS0_LOW - MAC Address0 Low */
18678 /*! @{ */
18679 
18680 #define ENET_MAC_ADDRESS0_LOW_ADDRLO_MASK        (0xFFFFFFFFU)
18681 #define ENET_MAC_ADDRESS0_LOW_ADDRLO_SHIFT       (0U)
18682 /*! ADDRLO - MAC Address0[31:0] */
18683 #define ENET_MAC_ADDRESS0_LOW_ADDRLO(x)          (((uint32_t)(((uint32_t)(x)) << ENET_MAC_ADDRESS0_LOW_ADDRLO_SHIFT)) & ENET_MAC_ADDRESS0_LOW_ADDRLO_MASK)
18684 /*! @} */
18685 
18686 /*! @name INDIR_ACCESS_CTRL - Indirect Access Control */
18687 /*! @{ */
18688 
18689 #define ENET_INDIR_ACCESS_CTRL_OB_MASK           (0x1U)
18690 #define ENET_INDIR_ACCESS_CTRL_OB_SHIFT          (0U)
18691 /*! OB - Operation Busy. */
18692 #define ENET_INDIR_ACCESS_CTRL_OB(x)             (((uint32_t)(((uint32_t)(x)) << ENET_INDIR_ACCESS_CTRL_OB_SHIFT)) & ENET_INDIR_ACCESS_CTRL_OB_MASK)
18693 
18694 #define ENET_INDIR_ACCESS_CTRL_COM_MASK          (0x2U)
18695 #define ENET_INDIR_ACCESS_CTRL_COM_SHIFT         (1U)
18696 /*! COM - Command type
18697  *  0b1..Read operation
18698  *  0b0..Write operation
18699  */
18700 #define ENET_INDIR_ACCESS_CTRL_COM(x)            (((uint32_t)(((uint32_t)(x)) << ENET_INDIR_ACCESS_CTRL_COM_SHIFT)) & ENET_INDIR_ACCESS_CTRL_COM_MASK)
18701 
18702 #define ENET_INDIR_ACCESS_CTRL_AUTO_MASK         (0x20U)
18703 #define ENET_INDIR_ACCESS_CTRL_AUTO_SHIFT        (5U)
18704 /*! AUTO - Auto increment */
18705 #define ENET_INDIR_ACCESS_CTRL_AUTO(x)           (((uint32_t)(((uint32_t)(x)) << ENET_INDIR_ACCESS_CTRL_AUTO_SHIFT)) & ENET_INDIR_ACCESS_CTRL_AUTO_MASK)
18706 
18707 #define ENET_INDIR_ACCESS_CTRL_AOFF_MASK         (0xFF00U)
18708 #define ENET_INDIR_ACCESS_CTRL_AOFF_SHIFT        (8U)
18709 /*! AOFF - Address Offset */
18710 #define ENET_INDIR_ACCESS_CTRL_AOFF(x)           (((uint32_t)(((uint32_t)(x)) << ENET_INDIR_ACCESS_CTRL_AOFF_SHIFT)) & ENET_INDIR_ACCESS_CTRL_AOFF_MASK)
18711 
18712 #define ENET_INDIR_ACCESS_CTRL_MSEL_MASK         (0xF0000U)
18713 #define ENET_INDIR_ACCESS_CTRL_MSEL_SHIFT        (16U)
18714 /*! MSEL - Mode Select */
18715 #define ENET_INDIR_ACCESS_CTRL_MSEL(x)           (((uint32_t)(((uint32_t)(x)) << ENET_INDIR_ACCESS_CTRL_MSEL_SHIFT)) & ENET_INDIR_ACCESS_CTRL_MSEL_MASK)
18716 /*! @} */
18717 
18718 /*! @name INDIR_ACCESS_DATA - Indirect Access Data */
18719 /*! @{ */
18720 
18721 #define ENET_INDIR_ACCESS_DATA_DATA_MASK         (0xFFFFFFFFU)
18722 #define ENET_INDIR_ACCESS_DATA_DATA_SHIFT        (0U)
18723 /*! DATA - This field contains data to read/write for Indirect address access associated with MAC_Indir_Access_Ctrl */
18724 #define ENET_INDIR_ACCESS_DATA_DATA(x)           (((uint32_t)(((uint32_t)(x)) << ENET_INDIR_ACCESS_DATA_DATA_SHIFT)) & ENET_INDIR_ACCESS_DATA_DATA_MASK)
18725 /*! @} */
18726 
18727 /*! @name MAC_TIMESTAMP_CONTROL - Timestamp Control */
18728 /*! @{ */
18729 
18730 #define ENET_MAC_TIMESTAMP_CONTROL_TSENA_MASK    (0x1U)
18731 #define ENET_MAC_TIMESTAMP_CONTROL_TSENA_SHIFT   (0U)
18732 /*! TSENA - Enable Timestamp
18733  *  0b0..Timestamp is disabled
18734  *  0b1..Timestamp is enabled
18735  */
18736 #define ENET_MAC_TIMESTAMP_CONTROL_TSENA(x)      (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CONTROL_TSENA_SHIFT)) & ENET_MAC_TIMESTAMP_CONTROL_TSENA_MASK)
18737 
18738 #define ENET_MAC_TIMESTAMP_CONTROL_TSCFUPDT_MASK (0x2U)
18739 #define ENET_MAC_TIMESTAMP_CONTROL_TSCFUPDT_SHIFT (1U)
18740 /*! TSCFUPDT - Fine or Coarse Timestamp Update
18741  *  0b0..Coarse method is used to update system timestamp
18742  *  0b1..Fine method is used to update system timestamp
18743  */
18744 #define ENET_MAC_TIMESTAMP_CONTROL_TSCFUPDT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CONTROL_TSCFUPDT_SHIFT)) & ENET_MAC_TIMESTAMP_CONTROL_TSCFUPDT_MASK)
18745 
18746 #define ENET_MAC_TIMESTAMP_CONTROL_TSINIT_MASK   (0x4U)
18747 #define ENET_MAC_TIMESTAMP_CONTROL_TSINIT_SHIFT  (2U)
18748 /*! TSINIT - Initialize Timestamp
18749  *  0b0..Timestamp is not initialized
18750  *  0b1..Timestamp is initialized
18751  */
18752 #define ENET_MAC_TIMESTAMP_CONTROL_TSINIT(x)     (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CONTROL_TSINIT_SHIFT)) & ENET_MAC_TIMESTAMP_CONTROL_TSINIT_MASK)
18753 
18754 #define ENET_MAC_TIMESTAMP_CONTROL_TSUPDT_MASK   (0x8U)
18755 #define ENET_MAC_TIMESTAMP_CONTROL_TSUPDT_SHIFT  (3U)
18756 /*! TSUPDT - Update Timestamp
18757  *  0b0..Timestamp is not updated
18758  *  0b1..Timestamp is updated
18759  */
18760 #define ENET_MAC_TIMESTAMP_CONTROL_TSUPDT(x)     (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CONTROL_TSUPDT_SHIFT)) & ENET_MAC_TIMESTAMP_CONTROL_TSUPDT_MASK)
18761 
18762 #define ENET_MAC_TIMESTAMP_CONTROL_TSTRIG_MASK   (0x10U)
18763 #define ENET_MAC_TIMESTAMP_CONTROL_TSTRIG_SHIFT  (4U)
18764 /*! TSTRIG - Enable Timestamp Interrupt Trigger
18765  *  0b0..Timestamp Interrupt Trigger is not enabled
18766  *  0b1..Timestamp Interrupt Trigger is enabled
18767  */
18768 #define ENET_MAC_TIMESTAMP_CONTROL_TSTRIG(x)     (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CONTROL_TSTRIG_SHIFT)) & ENET_MAC_TIMESTAMP_CONTROL_TSTRIG_MASK)
18769 
18770 #define ENET_MAC_TIMESTAMP_CONTROL_TSADDREG_MASK (0x20U)
18771 #define ENET_MAC_TIMESTAMP_CONTROL_TSADDREG_SHIFT (5U)
18772 /*! TSADDREG - Update Addend Register
18773  *  0b0..Addend Register is not updated
18774  *  0b1..Addend Register is updated
18775  */
18776 #define ENET_MAC_TIMESTAMP_CONTROL_TSADDREG(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CONTROL_TSADDREG_SHIFT)) & ENET_MAC_TIMESTAMP_CONTROL_TSADDREG_MASK)
18777 
18778 #define ENET_MAC_TIMESTAMP_CONTROL_TSENALL_MASK  (0x100U)
18779 #define ENET_MAC_TIMESTAMP_CONTROL_TSENALL_SHIFT (8U)
18780 /*! TSENALL - Enable Timestamp for All Packets
18781  *  0b0..Timestamp for All Packets disabled
18782  *  0b1..Timestamp for All Packets enabled
18783  */
18784 #define ENET_MAC_TIMESTAMP_CONTROL_TSENALL(x)    (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CONTROL_TSENALL_SHIFT)) & ENET_MAC_TIMESTAMP_CONTROL_TSENALL_MASK)
18785 
18786 #define ENET_MAC_TIMESTAMP_CONTROL_TSCTRLSSR_MASK (0x200U)
18787 #define ENET_MAC_TIMESTAMP_CONTROL_TSCTRLSSR_SHIFT (9U)
18788 /*! TSCTRLSSR - Timestamp Digital or Binary Rollover Control
18789  *  0b0..Timestamp Digital Rollover Control is disabled and Binary Rollover Control is enabled
18790  *  0b1..Timestamp Digital Rollover Control is enabled and Binary Rollover Control is disabled
18791  */
18792 #define ENET_MAC_TIMESTAMP_CONTROL_TSCTRLSSR(x)  (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CONTROL_TSCTRLSSR_SHIFT)) & ENET_MAC_TIMESTAMP_CONTROL_TSCTRLSSR_MASK)
18793 
18794 #define ENET_MAC_TIMESTAMP_CONTROL_TSVER2ENA_MASK (0x400U)
18795 #define ENET_MAC_TIMESTAMP_CONTROL_TSVER2ENA_SHIFT (10U)
18796 /*! TSVER2ENA - Enable PTP Packet Processing for Version 2 Format
18797  *  0b0..PTP Packet Processing for Version 2 Format is disabled
18798  *  0b1..PTP Packet Processing for Version 2 Format is enabled
18799  */
18800 #define ENET_MAC_TIMESTAMP_CONTROL_TSVER2ENA(x)  (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CONTROL_TSVER2ENA_SHIFT)) & ENET_MAC_TIMESTAMP_CONTROL_TSVER2ENA_MASK)
18801 
18802 #define ENET_MAC_TIMESTAMP_CONTROL_TSIPENA_MASK  (0x800U)
18803 #define ENET_MAC_TIMESTAMP_CONTROL_TSIPENA_SHIFT (11U)
18804 /*! TSIPENA - Enable Processing of PTP over Ethernet Packets
18805  *  0b0..Processing of PTP over Ethernet Packets is disabled
18806  *  0b1..Processing of PTP over Ethernet Packets is enabled
18807  */
18808 #define ENET_MAC_TIMESTAMP_CONTROL_TSIPENA(x)    (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CONTROL_TSIPENA_SHIFT)) & ENET_MAC_TIMESTAMP_CONTROL_TSIPENA_MASK)
18809 
18810 #define ENET_MAC_TIMESTAMP_CONTROL_TSIPV6ENA_MASK (0x1000U)
18811 #define ENET_MAC_TIMESTAMP_CONTROL_TSIPV6ENA_SHIFT (12U)
18812 /*! TSIPV6ENA - Enable Processing of PTP Packets Sent over IPv6-UDP
18813  *  0b0..Processing of PTP Packets Sent over IPv6-UDP is disabled
18814  *  0b1..Processing of PTP Packets Sent over IPv6-UDP is enabled
18815  */
18816 #define ENET_MAC_TIMESTAMP_CONTROL_TSIPV6ENA(x)  (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CONTROL_TSIPV6ENA_SHIFT)) & ENET_MAC_TIMESTAMP_CONTROL_TSIPV6ENA_MASK)
18817 
18818 #define ENET_MAC_TIMESTAMP_CONTROL_TSIPV4ENA_MASK (0x2000U)
18819 #define ENET_MAC_TIMESTAMP_CONTROL_TSIPV4ENA_SHIFT (13U)
18820 /*! TSIPV4ENA - Enable Processing of PTP Packets Sent over IPv4-UDP
18821  *  0b0..Processing of PTP Packets Sent over IPv4-UDP is disabled
18822  *  0b1..Processing of PTP Packets Sent over IPv4-UDP is enabled
18823  */
18824 #define ENET_MAC_TIMESTAMP_CONTROL_TSIPV4ENA(x)  (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CONTROL_TSIPV4ENA_SHIFT)) & ENET_MAC_TIMESTAMP_CONTROL_TSIPV4ENA_MASK)
18825 
18826 #define ENET_MAC_TIMESTAMP_CONTROL_TSEVNTENA_MASK (0x4000U)
18827 #define ENET_MAC_TIMESTAMP_CONTROL_TSEVNTENA_SHIFT (14U)
18828 /*! TSEVNTENA - Enable Timestamp Snapshot for Event Messages
18829  *  0b0..Timestamp Snapshot for Event Messages is disabled
18830  *  0b1..Timestamp Snapshot for Event Messages is enabled
18831  */
18832 #define ENET_MAC_TIMESTAMP_CONTROL_TSEVNTENA(x)  (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CONTROL_TSEVNTENA_SHIFT)) & ENET_MAC_TIMESTAMP_CONTROL_TSEVNTENA_MASK)
18833 
18834 #define ENET_MAC_TIMESTAMP_CONTROL_TSMSTRENA_MASK (0x8000U)
18835 #define ENET_MAC_TIMESTAMP_CONTROL_TSMSTRENA_SHIFT (15U)
18836 /*! TSMSTRENA - Enable Snapshot for Messages Relevant to Master
18837  *  0b0..Snapshot for Messages Relevant to Master is disabled
18838  *  0b1..Snapshot for Messages Relevant to Master is enabled
18839  */
18840 #define ENET_MAC_TIMESTAMP_CONTROL_TSMSTRENA(x)  (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CONTROL_TSMSTRENA_SHIFT)) & ENET_MAC_TIMESTAMP_CONTROL_TSMSTRENA_MASK)
18841 
18842 #define ENET_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_MASK (0x30000U)
18843 #define ENET_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_SHIFT (16U)
18844 /*! SNAPTYPSEL - Select PTP packets for Taking Snapshots */
18845 #define ENET_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_SHIFT)) & ENET_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_MASK)
18846 
18847 #define ENET_MAC_TIMESTAMP_CONTROL_TSENMACADDR_MASK (0x40000U)
18848 #define ENET_MAC_TIMESTAMP_CONTROL_TSENMACADDR_SHIFT (18U)
18849 /*! TSENMACADDR - Enable MAC Address for PTP Packet Filtering
18850  *  0b0..MAC Address for PTP Packet Filtering is disabled
18851  *  0b1..MAC Address for PTP Packet Filtering is enabled
18852  */
18853 #define ENET_MAC_TIMESTAMP_CONTROL_TSENMACADDR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CONTROL_TSENMACADDR_SHIFT)) & ENET_MAC_TIMESTAMP_CONTROL_TSENMACADDR_MASK)
18854 
18855 #define ENET_MAC_TIMESTAMP_CONTROL_ESTI_MASK     (0x100000U)
18856 #define ENET_MAC_TIMESTAMP_CONTROL_ESTI_SHIFT    (20U)
18857 /*! ESTI - External System Time Input
18858  *  0b0..External System Time Input is disabled
18859  *  0b1..External System Time Input is enabled
18860  */
18861 #define ENET_MAC_TIMESTAMP_CONTROL_ESTI(x)       (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CONTROL_ESTI_SHIFT)) & ENET_MAC_TIMESTAMP_CONTROL_ESTI_MASK)
18862 
18863 #define ENET_MAC_TIMESTAMP_CONTROL_TXTSSTSM_MASK (0x1000000U)
18864 #define ENET_MAC_TIMESTAMP_CONTROL_TXTSSTSM_SHIFT (24U)
18865 /*! TXTSSTSM - Transmit Timestamp Status Mode
18866  *  0b0..Transmit Timestamp Status Mode is disabled
18867  *  0b1..Transmit Timestamp Status Mode is enabled
18868  */
18869 #define ENET_MAC_TIMESTAMP_CONTROL_TXTSSTSM(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CONTROL_TXTSSTSM_SHIFT)) & ENET_MAC_TIMESTAMP_CONTROL_TXTSSTSM_MASK)
18870 
18871 #define ENET_MAC_TIMESTAMP_CONTROL_AV8021ASMEN_MASK (0x10000000U)
18872 #define ENET_MAC_TIMESTAMP_CONTROL_AV8021ASMEN_SHIFT (28U)
18873 /*! AV8021ASMEN - AV 802.
18874  *  0b0..AV 802.1AS Mode is disabled
18875  *  0b1..AV 802.1AS Mode is enabled
18876  */
18877 #define ENET_MAC_TIMESTAMP_CONTROL_AV8021ASMEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CONTROL_AV8021ASMEN_SHIFT)) & ENET_MAC_TIMESTAMP_CONTROL_AV8021ASMEN_MASK)
18878 /*! @} */
18879 
18880 /*! @name MAC_SUB_SECOND_INCREMENT - Subsecond Increment */
18881 /*! @{ */
18882 
18883 #define ENET_MAC_SUB_SECOND_INCREMENT_SNSINC_MASK (0xFF0000U)
18884 #define ENET_MAC_SUB_SECOND_INCREMENT_SNSINC_SHIFT (16U)
18885 /*! SNSINC - Sub-nanosecond Increment Value */
18886 #define ENET_MAC_SUB_SECOND_INCREMENT_SNSINC(x)  (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SUB_SECOND_INCREMENT_SNSINC_SHIFT)) & ENET_MAC_SUB_SECOND_INCREMENT_SNSINC_MASK)
18887 /*! @} */
18888 
18889 /*! @name MAC_SYSTEM_TIME_SECONDS - System Time Seconds */
18890 /*! @{ */
18891 
18892 #define ENET_MAC_SYSTEM_TIME_SECONDS_TSS_MASK    (0xFFFFFFFFU)
18893 #define ENET_MAC_SYSTEM_TIME_SECONDS_TSS_SHIFT   (0U)
18894 /*! TSS - Timestamp Second */
18895 #define ENET_MAC_SYSTEM_TIME_SECONDS_TSS(x)      (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYSTEM_TIME_SECONDS_TSS_SHIFT)) & ENET_MAC_SYSTEM_TIME_SECONDS_TSS_MASK)
18896 /*! @} */
18897 
18898 /*! @name MAC_SYSTEM_TIME_NANOSECONDS - System Time Nanoseconds */
18899 /*! @{ */
18900 
18901 #define ENET_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_MASK (0x7FFFFFFFU)
18902 #define ENET_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_SHIFT (0U)
18903 /*! TSSS - Timestamp Sub Seconds */
18904 #define ENET_MAC_SYSTEM_TIME_NANOSECONDS_TSSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_SHIFT)) & ENET_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_MASK)
18905 /*! @} */
18906 
18907 /*! @name MAC_SYSTEM_TIME_SECONDS_UPDATE - System Time Seconds Update */
18908 /*! @{ */
18909 
18910 #define ENET_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_MASK (0xFFFFFFFFU)
18911 #define ENET_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_SHIFT (0U)
18912 /*! TSS - Timestamp Seconds */
18913 #define ENET_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_SHIFT)) & ENET_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_MASK)
18914 /*! @} */
18915 
18916 /*! @name MAC_SYSTEM_TIME_NANOSECONDS_UPDATE - System Time Nanoseconds Update */
18917 /*! @{ */
18918 
18919 #define ENET_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_MASK (0x7FFFFFFFU)
18920 #define ENET_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_SHIFT (0U)
18921 /*! TSSS - Timestamp Sub Seconds */
18922 #define ENET_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_SHIFT)) & ENET_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_MASK)
18923 
18924 #define ENET_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_MASK (0x80000000U)
18925 #define ENET_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_SHIFT (31U)
18926 /*! ADDSUB - Add or Subtract Time
18927  *  0b0..Add time
18928  *  0b1..Subtract time
18929  */
18930 #define ENET_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_SHIFT)) & ENET_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_MASK)
18931 /*! @} */
18932 
18933 /*! @name MAC_TIMESTAMP_ADDEND - Timestamp Addend */
18934 /*! @{ */
18935 
18936 #define ENET_MAC_TIMESTAMP_ADDEND_TSAR_MASK      (0xFFFFFFFFU)
18937 #define ENET_MAC_TIMESTAMP_ADDEND_TSAR_SHIFT     (0U)
18938 /*! TSAR - Timestamp Addend Register */
18939 #define ENET_MAC_TIMESTAMP_ADDEND_TSAR(x)        (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_ADDEND_TSAR_SHIFT)) & ENET_MAC_TIMESTAMP_ADDEND_TSAR_MASK)
18940 /*! @} */
18941 
18942 /*! @name MAC_TIMESTAMP_STATUS - Timestamp Status */
18943 /*! @{ */
18944 
18945 #define ENET_MAC_TIMESTAMP_STATUS_TSSOVF_MASK    (0x1U)
18946 #define ENET_MAC_TIMESTAMP_STATUS_TSSOVF_SHIFT   (0U)
18947 /*! TSSOVF - Timestamp Seconds Overflow
18948  *  0b1..Timestamp Seconds Overflow status detected
18949  *  0b0..Timestamp Seconds Overflow status not detected
18950  */
18951 #define ENET_MAC_TIMESTAMP_STATUS_TSSOVF(x)      (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_STATUS_TSSOVF_SHIFT)) & ENET_MAC_TIMESTAMP_STATUS_TSSOVF_MASK)
18952 
18953 #define ENET_MAC_TIMESTAMP_STATUS_TSTARGT0_MASK  (0x2U)
18954 #define ENET_MAC_TIMESTAMP_STATUS_TSTARGT0_SHIFT (1U)
18955 /*! TSTARGT0 - Timestamp Target Time Reached
18956  *  0b1..Timestamp Target Time Reached status detected
18957  *  0b0..Timestamp Target Time Reached status not detected
18958  */
18959 #define ENET_MAC_TIMESTAMP_STATUS_TSTARGT0(x)    (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_STATUS_TSTARGT0_SHIFT)) & ENET_MAC_TIMESTAMP_STATUS_TSTARGT0_MASK)
18960 
18961 #define ENET_MAC_TIMESTAMP_STATUS_TSTRGTERR0_MASK (0x8U)
18962 #define ENET_MAC_TIMESTAMP_STATUS_TSTRGTERR0_SHIFT (3U)
18963 /*! TSTRGTERR0 - Timestamp Target Time Error
18964  *  0b1..Timestamp Target Time Error status detected
18965  *  0b0..Timestamp Target Time Error status not detected
18966  */
18967 #define ENET_MAC_TIMESTAMP_STATUS_TSTRGTERR0(x)  (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_STATUS_TSTRGTERR0_SHIFT)) & ENET_MAC_TIMESTAMP_STATUS_TSTRGTERR0_MASK)
18968 
18969 #define ENET_MAC_TIMESTAMP_STATUS_TXTSSIS_MASK   (0x8000U)
18970 #define ENET_MAC_TIMESTAMP_STATUS_TXTSSIS_SHIFT  (15U)
18971 /*! TXTSSIS - Tx Timestamp Status Interrupt Status
18972  *  0b1..Tx Timestamp Status Interrupt status detected
18973  *  0b0..Tx Timestamp Status Interrupt status not detected
18974  */
18975 #define ENET_MAC_TIMESTAMP_STATUS_TXTSSIS(x)     (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_STATUS_TXTSSIS_SHIFT)) & ENET_MAC_TIMESTAMP_STATUS_TXTSSIS_MASK)
18976 /*! @} */
18977 
18978 /*! @name MAC_TX_TIMESTAMP_STATUS_NANOSECONDS - Transmit Timestamp Status Nanoseconds */
18979 /*! @{ */
18980 
18981 #define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_MASK (0x7FFFFFFFU)
18982 #define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_SHIFT (0U)
18983 /*! TXTSSLO - Transmit Timestamp Status Low */
18984 #define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_SHIFT)) & ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_MASK)
18985 
18986 #define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS_MASK (0x80000000U)
18987 #define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS_SHIFT (31U)
18988 /*! TXTSSMIS - TXTSSMIS
18989  *  0b1..Transmit Timestamp Status Missed status detected
18990  *  0b0..Transmit Timestamp Status Missed status not detected
18991  */
18992 #define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS_SHIFT)) & ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS_MASK)
18993 /*! @} */
18994 
18995 /*! @name MAC_TX_TIMESTAMP_STATUS_SECONDS - Transmit Timestamp Status Seconds */
18996 /*! @{ */
18997 
18998 #define ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_MASK (0xFFFFFFFFU)
18999 #define ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_SHIFT (0U)
19000 /*! TXTSSHI - Transmit Timestamp Status High */
19001 #define ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_SHIFT)) & ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_MASK)
19002 /*! @} */
19003 
19004 /*! @name MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND - Timestamp Ingress Correction Nanosecond */
19005 /*! @{ */
19006 
19007 #define ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_MASK (0xFFFFFFFFU)
19008 #define ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_SHIFT (0U)
19009 /*! TSIC - Timestamp Ingress Correction */
19010 #define ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_SHIFT)) & ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_MASK)
19011 /*! @} */
19012 
19013 /*! @name MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND - Timestamp Egress Correction Nanosecond */
19014 /*! @{ */
19015 
19016 #define ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_MASK (0xFFFFFFFFU)
19017 #define ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_SHIFT (0U)
19018 /*! TSEC - Timestamp Egress Correction */
19019 #define ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_SHIFT)) & ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_MASK)
19020 /*! @} */
19021 
19022 /*! @name MAC_TIMESTAMP_INGRESS_LATENCY - Timestamp Ingress Latency */
19023 /*! @{ */
19024 
19025 #define ENET_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_MASK (0xFF00U)
19026 #define ENET_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_SHIFT (8U)
19027 /*! ITLSNS - ITLSNS */
19028 #define ENET_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_SHIFT)) & ENET_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_MASK)
19029 
19030 #define ENET_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_MASK (0xFFF0000U)
19031 #define ENET_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_SHIFT (16U)
19032 /*! ITLNS - ITLNS */
19033 #define ENET_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_SHIFT)) & ENET_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_MASK)
19034 /*! @} */
19035 
19036 /*! @name MAC_TIMESTAMP_EGRESS_LATENCY - Timestamp Egress Latency */
19037 /*! @{ */
19038 
19039 #define ENET_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_MASK (0xFF00U)
19040 #define ENET_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_SHIFT (8U)
19041 /*! ETLSNS - Egress Timestamp Latency, in sub-nanoseconds */
19042 #define ENET_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_SHIFT)) & ENET_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_MASK)
19043 
19044 #define ENET_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_MASK (0xFFF0000U)
19045 #define ENET_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_SHIFT (16U)
19046 /*! ETLNS - Egress Timestamp Latency, in nanoseconds */
19047 #define ENET_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_SHIFT)) & ENET_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_MASK)
19048 /*! @} */
19049 
19050 /*! @name MAC_PPS_CONTROL - PPS Control */
19051 /*! @{ */
19052 
19053 #define ENET_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_MASK (0xFU)
19054 #define ENET_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_SHIFT (0U)
19055 /*! PPSCTRL_PPSCMD - PPS Output Frequency Control */
19056 #define ENET_MAC_PPS_CONTROL_PPSCTRL_PPSCMD(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_SHIFT)) & ENET_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_MASK)
19057 /*! @} */
19058 
19059 /*! @name PPS0_TARGET_TIME_SECONDS - PPS0 Target Time Seconds */
19060 /*! @{ */
19061 
19062 #define ENET_PPS0_TARGET_TIME_SECONDS_TSTRH0_MASK (0xFFFFFFFFU)
19063 #define ENET_PPS0_TARGET_TIME_SECONDS_TSTRH0_SHIFT (0U)
19064 /*! TSTRH0 - PPS Target Time Seconds Register */
19065 #define ENET_PPS0_TARGET_TIME_SECONDS_TSTRH0(x)  (((uint32_t)(((uint32_t)(x)) << ENET_PPS0_TARGET_TIME_SECONDS_TSTRH0_SHIFT)) & ENET_PPS0_TARGET_TIME_SECONDS_TSTRH0_MASK)
19066 /*! @} */
19067 
19068 /*! @name PPS0_TARGET_TIME_NANOSECONDS - PPS0 Target Time Nanoseconds */
19069 /*! @{ */
19070 
19071 #define ENET_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_MASK (0x7FFFFFFFU)
19072 #define ENET_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_SHIFT (0U)
19073 /*! TTSL0 - Target Time Low for PPS Register */
19074 #define ENET_PPS0_TARGET_TIME_NANOSECONDS_TTSL0(x) (((uint32_t)(((uint32_t)(x)) << ENET_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_SHIFT)) & ENET_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_MASK)
19075 /*! @} */
19076 
19077 /*! @name MTL_OPERATION_MODE - MTL Operation Mode */
19078 /*! @{ */
19079 
19080 #define ENET_MTL_OPERATION_MODE_DTXSTS_MASK      (0x2U)
19081 #define ENET_MTL_OPERATION_MODE_DTXSTS_SHIFT     (1U)
19082 /*! DTXSTS - Drop Transmit Status
19083  *  0b0..Drop Transmit Status is disabled
19084  *  0b1..Drop Transmit Status is enabled
19085  */
19086 #define ENET_MTL_OPERATION_MODE_DTXSTS(x)        (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OPERATION_MODE_DTXSTS_SHIFT)) & ENET_MTL_OPERATION_MODE_DTXSTS_MASK)
19087 
19088 #define ENET_MTL_OPERATION_MODE_RAA_MASK         (0x4U)
19089 #define ENET_MTL_OPERATION_MODE_RAA_SHIFT        (2U)
19090 /*! RAA - Receive Arbitration Algorithm
19091  *  0b0..Strict priority (SP)
19092  *  0b1..Weighted Strict Priority (WSP)
19093  */
19094 #define ENET_MTL_OPERATION_MODE_RAA(x)           (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OPERATION_MODE_RAA_SHIFT)) & ENET_MTL_OPERATION_MODE_RAA_MASK)
19095 
19096 #define ENET_MTL_OPERATION_MODE_SCHALG_MASK      (0x60U)
19097 #define ENET_MTL_OPERATION_MODE_SCHALG_SHIFT     (5U)
19098 /*! SCHALG - Tx Scheduling Algorithm
19099  *  0b10..DWRR algorithm when DCB feature is selected.Otherwise, Reserved
19100  *  0b11..Strict priority algorithm
19101  *  0b01..WFQ algorithm when DCB feature is selected.Otherwise, Reserved
19102  *  0b00..WRR algorithm
19103  */
19104 #define ENET_MTL_OPERATION_MODE_SCHALG(x)        (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OPERATION_MODE_SCHALG_SHIFT)) & ENET_MTL_OPERATION_MODE_SCHALG_MASK)
19105 
19106 #define ENET_MTL_OPERATION_MODE_CNTPRST_MASK     (0x100U)
19107 #define ENET_MTL_OPERATION_MODE_CNTPRST_SHIFT    (8U)
19108 /*! CNTPRST - Counters Preset
19109  *  0b0..Counters Preset is disabled
19110  *  0b1..Counters Preset is enabled
19111  */
19112 #define ENET_MTL_OPERATION_MODE_CNTPRST(x)       (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OPERATION_MODE_CNTPRST_SHIFT)) & ENET_MTL_OPERATION_MODE_CNTPRST_MASK)
19113 
19114 #define ENET_MTL_OPERATION_MODE_CNTCLR_MASK      (0x200U)
19115 #define ENET_MTL_OPERATION_MODE_CNTCLR_SHIFT     (9U)
19116 /*! CNTCLR - Counters Reset
19117  *  0b0..Counters are not reset
19118  *  0b1..All counters are reset
19119  */
19120 #define ENET_MTL_OPERATION_MODE_CNTCLR(x)        (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OPERATION_MODE_CNTCLR_SHIFT)) & ENET_MTL_OPERATION_MODE_CNTCLR_MASK)
19121 /*! @} */
19122 
19123 /*! @name MTL_INTERRUPT_STATUS - MTL Interrupt Status */
19124 /*! @{ */
19125 
19126 #define ENET_MTL_INTERRUPT_STATUS_Q0IS_MASK      (0x1U)
19127 #define ENET_MTL_INTERRUPT_STATUS_Q0IS_SHIFT     (0U)
19128 /*! Q0IS - Queue 0 Interrupt status
19129  *  0b1..Queue 0 Interrupt status detected
19130  *  0b0..Queue 0 Interrupt status not detected
19131  */
19132 #define ENET_MTL_INTERRUPT_STATUS_Q0IS(x)        (((uint32_t)(((uint32_t)(x)) << ENET_MTL_INTERRUPT_STATUS_Q0IS_SHIFT)) & ENET_MTL_INTERRUPT_STATUS_Q0IS_MASK)
19133 
19134 #define ENET_MTL_INTERRUPT_STATUS_Q1IS_MASK      (0x2U)
19135 #define ENET_MTL_INTERRUPT_STATUS_Q1IS_SHIFT     (1U)
19136 /*! Q1IS - Queue 1 Interrupt status
19137  *  0b1..Queue 1 Interrupt status detected
19138  *  0b0..Queue 1 Interrupt status not detected
19139  */
19140 #define ENET_MTL_INTERRUPT_STATUS_Q1IS(x)        (((uint32_t)(((uint32_t)(x)) << ENET_MTL_INTERRUPT_STATUS_Q1IS_SHIFT)) & ENET_MTL_INTERRUPT_STATUS_Q1IS_MASK)
19141 /*! @} */
19142 
19143 /*! @name MTL_RXQ_DMA_MAP0 - Receive Queue and DMA Channel Mapping 0 */
19144 /*! @{ */
19145 
19146 #define ENET_MTL_RXQ_DMA_MAP0_Q0MDMACH_MASK      (0x1U)
19147 #define ENET_MTL_RXQ_DMA_MAP0_Q0MDMACH_SHIFT     (0U)
19148 /*! Q0MDMACH - Queue 0 Mapped to DMA Channel */
19149 #define ENET_MTL_RXQ_DMA_MAP0_Q0MDMACH(x)        (((uint32_t)(((uint32_t)(x)) << ENET_MTL_RXQ_DMA_MAP0_Q0MDMACH_SHIFT)) & ENET_MTL_RXQ_DMA_MAP0_Q0MDMACH_MASK)
19150 
19151 #define ENET_MTL_RXQ_DMA_MAP0_Q0DDMACH_MASK      (0x10U)
19152 #define ENET_MTL_RXQ_DMA_MAP0_Q0DDMACH_SHIFT     (4U)
19153 /*! Q0DDMACH - Queue 0 Enabled for DA-based DMA Channel Selection
19154  *  0b0..Queue 0 disabled for DA-based DMA Channel Selection
19155  *  0b1..Queue 0 enabled for DA-based DMA Channel Selection
19156  */
19157 #define ENET_MTL_RXQ_DMA_MAP0_Q0DDMACH(x)        (((uint32_t)(((uint32_t)(x)) << ENET_MTL_RXQ_DMA_MAP0_Q0DDMACH_SHIFT)) & ENET_MTL_RXQ_DMA_MAP0_Q0DDMACH_MASK)
19158 
19159 #define ENET_MTL_RXQ_DMA_MAP0_Q1MDMACH_MASK      (0x100U)
19160 #define ENET_MTL_RXQ_DMA_MAP0_Q1MDMACH_SHIFT     (8U)
19161 /*! Q1MDMACH - Queue 1 Mapped to DMA Channel */
19162 #define ENET_MTL_RXQ_DMA_MAP0_Q1MDMACH(x)        (((uint32_t)(((uint32_t)(x)) << ENET_MTL_RXQ_DMA_MAP0_Q1MDMACH_SHIFT)) & ENET_MTL_RXQ_DMA_MAP0_Q1MDMACH_MASK)
19163 
19164 #define ENET_MTL_RXQ_DMA_MAP0_Q1DDMACH_MASK      (0x1000U)
19165 #define ENET_MTL_RXQ_DMA_MAP0_Q1DDMACH_SHIFT     (12U)
19166 /*! Q1DDMACH - Queue 1 Enabled for DA-based DMA Channel Selection
19167  *  0b0..Queue 1 disabled for DA-based DMA Channel Selection
19168  *  0b1..Queue 1 enabled for DA-based DMA Channel Selection
19169  */
19170 #define ENET_MTL_RXQ_DMA_MAP0_Q1DDMACH(x)        (((uint32_t)(((uint32_t)(x)) << ENET_MTL_RXQ_DMA_MAP0_Q1DDMACH_SHIFT)) & ENET_MTL_RXQ_DMA_MAP0_Q1DDMACH_MASK)
19171 /*! @} */
19172 
19173 /*! @name MTL_QUEUE_MTL_TXQX_OP_MODE - Queue 0 Transmit Operation Mode..Queue 1 Transmit Operation Mode */
19174 /*! @{ */
19175 
19176 #define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ_MASK (0x1U)
19177 #define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ_SHIFT (0U)
19178 /*! FTQ - Flush Transmit Queue
19179  *  0b0..Flush Transmit Queue is disabled
19180  *  0b1..Flush Transmit Queue is enabled
19181  */
19182 #define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ_MASK)
19183 
19184 #define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_MASK (0x2U)
19185 #define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_SHIFT (1U)
19186 /*! TSF - Transmit Store and Forward
19187  *  0b0..Transmit Store and Forward is disabled
19188  *  0b1..Transmit Store and Forward is enabled
19189  */
19190 #define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_MASK)
19191 
19192 #define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN_MASK (0xCU)
19193 #define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN_SHIFT (2U)
19194 /*! TXQEN - Transmit Queue Enable
19195  *  0b00..Not enabled
19196  *  0b10..Enabled
19197  *  0b01..Enable in AV mode (Reserved in non-AV)
19198  *  0b11..Reserved
19199  */
19200 #define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN_MASK)
19201 
19202 #define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC_MASK (0x70U)
19203 #define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC_SHIFT (4U)
19204 /*! TTC - Transmit Threshold Control
19205  *  0b011..128
19206  *  0b100..192
19207  *  0b101..256
19208  *  0b000..32
19209  *  0b110..384
19210  *  0b111..512
19211  *  0b001..64
19212  *  0b010..96
19213  */
19214 #define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC_MASK)
19215 
19216 #define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS_MASK (0x70000U)
19217 #define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS_SHIFT (16U)
19218 /*! TQS - Transmit Queue Size */
19219 #define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS_MASK)
19220 /*! @} */
19221 
19222 /* The count of ENET_MTL_QUEUE_MTL_TXQX_OP_MODE */
19223 #define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_COUNT    (2U)
19224 
19225 /*! @name MTL_QUEUE_MTL_TXQX_UNDRFLW - Queue 0 Underflow Counter..Queue 1 Underflow Counter */
19226 /*! @{ */
19227 
19228 #define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT_MASK (0x7FFU)
19229 #define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT_SHIFT (0U)
19230 /*! UFFRMCNT - Underflow Packet Counter */
19231 #define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT_MASK)
19232 
19233 #define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF_MASK (0x800U)
19234 #define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF_SHIFT (11U)
19235 /*! UFCNTOVF - Overflow Bit for Underflow Packet Counter
19236  *  0b1..Overflow detected for Underflow Packet Counter
19237  *  0b0..Overflow not detected for Underflow Packet Counter
19238  */
19239 #define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF_MASK)
19240 /*! @} */
19241 
19242 /* The count of ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW */
19243 #define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_COUNT    (2U)
19244 
19245 /*! @name MTL_QUEUE_MTL_TXQX_DBG - Queue 0 Transmit Debug..Queue 1 Transmit Debug */
19246 /*! @{ */
19247 
19248 #define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED_MASK (0x1U)
19249 #define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED_SHIFT (0U)
19250 /*! TXQPAUSED - Transmit Queue in Pause
19251  *  0b1..Transmit Queue in Pause status is detected
19252  *  0b0..Transmit Queue in Pause status is not detected
19253  */
19254 #define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED_MASK)
19255 
19256 #define ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS_MASK  (0x6U)
19257 #define ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS_SHIFT (1U)
19258 /*! TRCSTS - MTL Tx Queue Read Controller Status
19259  *  0b11..Flushing the Tx queue because of the Packet Abort request from the MAC
19260  *  0b00..Idle state
19261  *  0b01..Read state (transferring data to the MAC transmitter)
19262  *  0b10..Waiting for pending Tx Status from the MAC transmitter
19263  */
19264 #define ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS(x)    (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS_MASK)
19265 
19266 #define ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS_MASK  (0x8U)
19267 #define ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS_SHIFT (3U)
19268 /*! TWCSTS - MTL Tx Queue Write Controller Status
19269  *  0b1..MTL Tx Queue Write Controller status is detected
19270  *  0b0..MTL Tx Queue Write Controller status is not detected
19271  */
19272 #define ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS(x)    (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS_MASK)
19273 
19274 #define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS_MASK  (0x10U)
19275 #define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS_SHIFT (4U)
19276 /*! TXQSTS - MTL Tx Queue Not Empty Status
19277  *  0b1..MTL Tx Queue Not Empty status is detected
19278  *  0b0..MTL Tx Queue Not Empty status is not detected
19279  */
19280 #define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS(x)    (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS_MASK)
19281 
19282 #define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS_MASK (0x20U)
19283 #define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS_SHIFT (5U)
19284 /*! TXSTSFSTS - MTL Tx Status FIFO Full Status
19285  *  0b1..MTL Tx Status FIFO Full status is detected
19286  *  0b0..MTL Tx Status FIFO Full status is not detected
19287  */
19288 #define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS_MASK)
19289 
19290 #define ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ_MASK    (0x70000U)
19291 #define ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ_SHIFT   (16U)
19292 /*! PTXQ - Number of Packets in the Transmit Queue */
19293 #define ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ(x)      (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ_MASK)
19294 
19295 #define ENET_MTL_QUEUE_MTL_TXQX_DBG_STXSTSF_MASK (0x700000U)
19296 #define ENET_MTL_QUEUE_MTL_TXQX_DBG_STXSTSF_SHIFT (20U)
19297 /*! STXSTSF - Number of Status Words in Tx Status FIFO of Queue */
19298 #define ENET_MTL_QUEUE_MTL_TXQX_DBG_STXSTSF(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_STXSTSF_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_STXSTSF_MASK)
19299 /*! @} */
19300 
19301 /* The count of ENET_MTL_QUEUE_MTL_TXQX_DBG */
19302 #define ENET_MTL_QUEUE_MTL_TXQX_DBG_COUNT        (2U)
19303 
19304 /*! @name MTL_QUEUE_MTL_TXQX_ETS_CTRL - Queue 1 ETS Control */
19305 /*! @{ */
19306 
19307 #define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG_MASK (0x4U)
19308 #define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG_SHIFT (2U)
19309 /*! AVALG - AV Algorithm
19310  *  0b0..CBS Algorithm is disabled
19311  *  0b1..CBS Algorithm is enabled
19312  */
19313 #define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG_MASK)
19314 
19315 #define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC_MASK (0x8U)
19316 #define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC_SHIFT (3U)
19317 /*! CC - Credit Control
19318  *  0b0..Credit Control is disabled
19319  *  0b1..Credit Control is enabled
19320  */
19321 #define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC_MASK)
19322 
19323 #define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC_MASK (0x70U)
19324 #define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC_SHIFT (4U)
19325 /*! SLC - Slot Count
19326  *  0b100..16 slots
19327  *  0b000..1 slot
19328  *  0b001..2 slots
19329  *  0b010..4 slots
19330  *  0b011..8 slots
19331  *  0b101..Reserved
19332  */
19333 #define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC(x)  (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC_MASK)
19334 /*! @} */
19335 
19336 /* The count of ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL */
19337 #define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_COUNT   (2U)
19338 
19339 /*! @name MTL_QUEUE_MTL_TXQX_ETS_STAT - Queue 0 ETS Status..Queue 1 ETS Status */
19340 /*! @{ */
19341 
19342 #define ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS_MASK (0xFFFFFFU)
19343 #define ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS_SHIFT (0U)
19344 /*! ABS - Average Bits per Slot */
19345 #define ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS(x)  (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS_MASK)
19346 /*! @} */
19347 
19348 /* The count of ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT */
19349 #define ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_COUNT   (2U)
19350 
19351 /*! @name MTL_QUEUE_MTL_TXQX_QNTM_WGHT - Queue 0 Quantum or Weights..Queue 1 idleSlopeCredit, Quantum or Weights */
19352 /*! @{ */
19353 
19354 #define ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW_MASK (0x1FFFFFU)
19355 #define ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW_SHIFT (0U)
19356 /*! ISCQW - idleSlopeCredit, Quantum or Weights */
19357 #define ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW_MASK)
19358 /*! @} */
19359 
19360 /* The count of ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT */
19361 #define ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_COUNT  (2U)
19362 
19363 /*! @name MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT - Queue 1 sendSlopeCredit */
19364 /*! @{ */
19365 
19366 #define ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC_MASK (0x3FFFU)
19367 #define ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC_SHIFT (0U)
19368 /*! SSC - sendSlopeCredit Value */
19369 #define ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC_MASK)
19370 /*! @} */
19371 
19372 /* The count of ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT */
19373 #define ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_COUNT (2U)
19374 
19375 /*! @name MTL_QUEUE_MTL_TXQX_HI_CRDT - Queue 1 hiCredit */
19376 /*! @{ */
19377 
19378 #define ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC_MASK  (0x1FFFFFFFU)
19379 #define ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC_SHIFT (0U)
19380 /*! HC - hiCredit Value */
19381 #define ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC(x)    (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC_MASK)
19382 /*! @} */
19383 
19384 /* The count of ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT */
19385 #define ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_COUNT    (2U)
19386 
19387 /*! @name MTL_QUEUE_MTL_TXQX_LO_CRDT - Queue 1 loCredit */
19388 /*! @{ */
19389 
19390 #define ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC_MASK  (0x1FFFFFFFU)
19391 #define ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC_SHIFT (0U)
19392 /*! LC - loCredit Value */
19393 #define ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC(x)    (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC_MASK)
19394 /*! @} */
19395 
19396 /* The count of ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT */
19397 #define ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_COUNT    (2U)
19398 
19399 /*! @name MTL_QUEUE_MTL_QX_INTCTRL_STAT - Queue 0 Interrupt Control Status..Queue 1 Interrupt Control Status */
19400 /*! @{ */
19401 
19402 #define ENET_MTL_QUEUE_MTL_QX_INTCTRL_STAT_TXUNFIS_MASK (0x1U)
19403 #define ENET_MTL_QUEUE_MTL_QX_INTCTRL_STAT_TXUNFIS_SHIFT (0U)
19404 /*! TXUNFIS - Transmit Queue Underflow Interrupt Status
19405  *  0b1..Transmit Queue Underflow Interrupt Status detected
19406  *  0b0..Transmit Queue Underflow Interrupt Status not detected
19407  */
19408 #define ENET_MTL_QUEUE_MTL_QX_INTCTRL_STAT_TXUNFIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_QX_INTCTRL_STAT_TXUNFIS_SHIFT)) & ENET_MTL_QUEUE_MTL_QX_INTCTRL_STAT_TXUNFIS_MASK)
19409 
19410 #define ENET_MTL_QUEUE_MTL_QX_INTCTRL_STAT_ABPSIS_MASK (0x2U)
19411 #define ENET_MTL_QUEUE_MTL_QX_INTCTRL_STAT_ABPSIS_SHIFT (1U)
19412 /*! ABPSIS - Average Bits Per Slot Interrupt Status
19413  *  0b1..Average Bits Per Slot Interrupt Status detected
19414  *  0b0..Average Bits Per Slot Interrupt Status not detected
19415  */
19416 #define ENET_MTL_QUEUE_MTL_QX_INTCTRL_STAT_ABPSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_QX_INTCTRL_STAT_ABPSIS_SHIFT)) & ENET_MTL_QUEUE_MTL_QX_INTCTRL_STAT_ABPSIS_MASK)
19417 
19418 #define ENET_MTL_QUEUE_MTL_QX_INTCTRL_STAT_TXUIE_MASK (0x100U)
19419 #define ENET_MTL_QUEUE_MTL_QX_INTCTRL_STAT_TXUIE_SHIFT (8U)
19420 /*! TXUIE - Transmit Queue Underflow Interrupt Enable
19421  *  0b0..Transmit Queue Underflow Interrupt Status is disabled
19422  *  0b1..Transmit Queue Underflow Interrupt Status is enabled
19423  */
19424 #define ENET_MTL_QUEUE_MTL_QX_INTCTRL_STAT_TXUIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_QX_INTCTRL_STAT_TXUIE_SHIFT)) & ENET_MTL_QUEUE_MTL_QX_INTCTRL_STAT_TXUIE_MASK)
19425 
19426 #define ENET_MTL_QUEUE_MTL_QX_INTCTRL_STAT_ABPSIE_MASK (0x200U)
19427 #define ENET_MTL_QUEUE_MTL_QX_INTCTRL_STAT_ABPSIE_SHIFT (9U)
19428 /*! ABPSIE - Average Bits Per Slot Interrupt Enable
19429  *  0b0..Average Bits Per Slot Interrupt is disabled
19430  *  0b1..Average Bits Per Slot Interrupt is enabled
19431  */
19432 #define ENET_MTL_QUEUE_MTL_QX_INTCTRL_STAT_ABPSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_QX_INTCTRL_STAT_ABPSIE_SHIFT)) & ENET_MTL_QUEUE_MTL_QX_INTCTRL_STAT_ABPSIE_MASK)
19433 
19434 #define ENET_MTL_QUEUE_MTL_QX_INTCTRL_STAT_RXOVFIS_MASK (0x10000U)
19435 #define ENET_MTL_QUEUE_MTL_QX_INTCTRL_STAT_RXOVFIS_SHIFT (16U)
19436 /*! RXOVFIS - Receive Queue Overflow Interrupt Status
19437  *  0b1..Receive Queue Overflow Interrupt Status detected
19438  *  0b0..Receive Queue Overflow Interrupt Status not detected
19439  */
19440 #define ENET_MTL_QUEUE_MTL_QX_INTCTRL_STAT_RXOVFIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_QX_INTCTRL_STAT_RXOVFIS_SHIFT)) & ENET_MTL_QUEUE_MTL_QX_INTCTRL_STAT_RXOVFIS_MASK)
19441 
19442 #define ENET_MTL_QUEUE_MTL_QX_INTCTRL_STAT_RXOIE_MASK (0x1000000U)
19443 #define ENET_MTL_QUEUE_MTL_QX_INTCTRL_STAT_RXOIE_SHIFT (24U)
19444 /*! RXOIE - Receive Queue Overflow Interrupt Enable
19445  *  0b0..Receive Queue Overflow Interrupt is disabled
19446  *  0b1..Receive Queue Overflow Interrupt is enabled
19447  */
19448 #define ENET_MTL_QUEUE_MTL_QX_INTCTRL_STAT_RXOIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_QX_INTCTRL_STAT_RXOIE_SHIFT)) & ENET_MTL_QUEUE_MTL_QX_INTCTRL_STAT_RXOIE_MASK)
19449 /*! @} */
19450 
19451 /* The count of ENET_MTL_QUEUE_MTL_QX_INTCTRL_STAT */
19452 #define ENET_MTL_QUEUE_MTL_QX_INTCTRL_STAT_COUNT (2U)
19453 
19454 /*! @name MTL_QUEUE_MTL_RXQX_OP_MODE - Queue 0 Receive Operation Mode..Queue 1 Receive Operation Mode */
19455 /*! @{ */
19456 
19457 #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC_MASK (0x3U)
19458 #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC_SHIFT (0U)
19459 /*! RTC - Receive Queue Threshold Control
19460  *  0b11..128
19461  *  0b01..32
19462  *  0b00..64
19463  *  0b10..96
19464  */
19465 #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC_MASK)
19466 
19467 #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP_MASK (0x8U)
19468 #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP_SHIFT (3U)
19469 /*! FUP - Forward Undersized Good Packets
19470  *  0b0..Forward Undersized Good Packets is disabled
19471  *  0b1..Forward Undersized Good Packets is enabled
19472  */
19473 #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP_MASK)
19474 
19475 #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP_MASK (0x10U)
19476 #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP_SHIFT (4U)
19477 /*! FEP - Forward Error Packets
19478  *  0b0..Forward Error Packets is disabled
19479  *  0b1..Forward Error Packets is enabled
19480  */
19481 #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP_MASK)
19482 
19483 #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF_MASK (0x20U)
19484 #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF_SHIFT (5U)
19485 /*! RSF - Receive Queue Store and Forward
19486  *  0b0..Receive Queue Store and Forward is disabled
19487  *  0b1..Receive Queue Store and Forward is enabled
19488  */
19489 #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF_MASK)
19490 
19491 #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF_MASK (0x40U)
19492 #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF_SHIFT (6U)
19493 /*! DIS_TCP_EF - Disable Dropping of TCP/IP Checksum Error Packets
19494  *  0b1..Dropping of TCP/IP Checksum Error Packets is disabled
19495  *  0b0..Dropping of TCP/IP Checksum Error Packets is enabled
19496  */
19497 #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF_MASK)
19498 
19499 #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS_MASK (0x700000U)
19500 #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS_SHIFT (20U)
19501 /*! RQS - Receive Queue Size */
19502 #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS_MASK)
19503 /*! @} */
19504 
19505 /* The count of ENET_MTL_QUEUE_MTL_RXQX_OP_MODE */
19506 #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_COUNT    (2U)
19507 
19508 /*! @name MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT - Queue 0 Missed Packet and Overflow Counter..Queue 1 Missed Packet and Overflow Counter */
19509 /*! @{ */
19510 
19511 #define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_MASK (0x7FFU)
19512 #define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_SHIFT (0U)
19513 /*! OVFPKTCNT - Overflow Packet Counter */
19514 #define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_MASK)
19515 
19516 #define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_MASK (0x800U)
19517 #define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_SHIFT (11U)
19518 /*! OVFCNTOVF - Overflow Counter Overflow Bit
19519  *  0b1..Overflow Counter overflow detected
19520  *  0b0..Overflow Counter overflow not detected
19521  */
19522 #define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_MASK)
19523 
19524 #define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISPKTCNT_MASK (0x7FF0000U)
19525 #define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISPKTCNT_SHIFT (16U)
19526 /*! MISPKTCNT - Missed Packet Counter */
19527 #define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISPKTCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISPKTCNT_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISPKTCNT_MASK)
19528 
19529 #define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISCNTOVF_MASK (0x8000000U)
19530 #define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISCNTOVF_SHIFT (27U)
19531 /*! MISCNTOVF - Missed Packet Counter Overflow Bit
19532  *  0b1..Missed Packet Counter overflow detected
19533  *  0b0..Missed Packet Counter overflow not detected
19534  */
19535 #define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISCNTOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISCNTOVF_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISCNTOVF_MASK)
19536 /*! @} */
19537 
19538 /* The count of ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT */
19539 #define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_COUNT (2U)
19540 
19541 /*! @name MTL_QUEUE_MTL_RXQX_DBG - Queue 0 Receive Debug..Queue 1 Receive Debug */
19542 /*! @{ */
19543 
19544 #define ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS_MASK  (0x1U)
19545 #define ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS_SHIFT (0U)
19546 /*! RWCSTS - MTL Rx Queue Write Controller Active Status
19547  *  0b1..MTL Rx Queue Write Controller Active Status detected
19548  *  0b0..MTL Rx Queue Write Controller Active Status not detected
19549  */
19550 #define ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS(x)    (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS_MASK)
19551 
19552 #define ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS_MASK  (0x6U)
19553 #define ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS_SHIFT (1U)
19554 /*! RRCSTS - MTL Rx Queue Read Controller State
19555  *  0b11..Flushing the packet data and status
19556  *  0b00..Idle state
19557  *  0b01..Reading packet data
19558  *  0b10..Reading packet status (or timestamp)
19559  */
19560 #define ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS(x)    (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS_MASK)
19561 
19562 #define ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS_MASK  (0x30U)
19563 #define ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS_SHIFT (4U)
19564 /*! RXQSTS - MTL Rx Queue Fill-Level Status
19565  *  0b10..Rx Queue fill-level above flow-control activate threshold
19566  *  0b01..Rx Queue fill-level below flow-control deactivate threshold
19567  *  0b00..Rx Queue empty
19568  *  0b11..Rx Queue full
19569  */
19570 #define ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS(x)    (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS_MASK)
19571 
19572 #define ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ_MASK    (0x3FFF0000U)
19573 #define ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ_SHIFT   (16U)
19574 /*! PRXQ - Number of Packets in Receive Queue */
19575 #define ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ(x)      (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ_MASK)
19576 /*! @} */
19577 
19578 /* The count of ENET_MTL_QUEUE_MTL_RXQX_DBG */
19579 #define ENET_MTL_QUEUE_MTL_RXQX_DBG_COUNT        (2U)
19580 
19581 /*! @name MTL_QUEUE_MTL_RXQX_CTRL - Queue 0 Receive Control..Queue 1 Receive Control */
19582 /*! @{ */
19583 
19584 #define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT_MASK (0x7U)
19585 #define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT_SHIFT (0U)
19586 /*! RXQ_WEGT - Receive Queue Weight */
19587 #define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT_MASK)
19588 
19589 #define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_MASK (0x8U)
19590 #define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_SHIFT (3U)
19591 /*! RXQ_FRM_ARBIT - Receive Queue Packet Arbitration
19592  *  0b0..Receive Queue Packet Arbitration is disabled
19593  *  0b1..Receive Queue Packet Arbitration is enabled
19594  */
19595 #define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_MASK)
19596 /*! @} */
19597 
19598 /* The count of ENET_MTL_QUEUE_MTL_RXQX_CTRL */
19599 #define ENET_MTL_QUEUE_MTL_RXQX_CTRL_COUNT       (2U)
19600 
19601 /*! @name DMA_MODE - DMA Bus Mode */
19602 /*! @{ */
19603 
19604 #define ENET_DMA_MODE_SWR_MASK                   (0x1U)
19605 #define ENET_DMA_MODE_SWR_SHIFT                  (0U)
19606 /*! SWR - Software Reset
19607  *  0b0..Software Reset is disabled
19608  *  0b1..Software Reset is enabled
19609  */
19610 #define ENET_DMA_MODE_SWR(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_SWR_SHIFT)) & ENET_DMA_MODE_SWR_MASK)
19611 
19612 #define ENET_DMA_MODE_DA_MASK                    (0x2U)
19613 #define ENET_DMA_MODE_DA_SHIFT                   (1U)
19614 /*! DA - DMA Tx or Rx Arbitration Scheme
19615  *  0b1..Fixed Priority
19616  *  0b0..Weighted Round-Robin with Rx:Tx or Tx:Rx
19617  */
19618 #define ENET_DMA_MODE_DA(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_DA_SHIFT)) & ENET_DMA_MODE_DA_MASK)
19619 
19620 #define ENET_DMA_MODE_TAA_MASK                   (0x1CU)
19621 #define ENET_DMA_MODE_TAA_SHIFT                  (2U)
19622 /*! TAA - Transmit Arbitration Algorithm
19623  *  0b000..Fixed priority
19624  *  0b011..Reserved (for 3'b011 to 3'b111)
19625  *  0b010..Weighted Round-Robin (WRR)
19626  *  0b001..Weighted Strict Priority (WSP)
19627  */
19628 #define ENET_DMA_MODE_TAA(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_TAA_SHIFT)) & ENET_DMA_MODE_TAA_MASK)
19629 
19630 #define ENET_DMA_MODE_TXPR_MASK                  (0x800U)
19631 #define ENET_DMA_MODE_TXPR_SHIFT                 (11U)
19632 /*! TXPR - Transmit Priority
19633  *  0b0..Transmit Priority is disabled
19634  *  0b1..Transmit Priority is enabled
19635  */
19636 #define ENET_DMA_MODE_TXPR(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_TXPR_SHIFT)) & ENET_DMA_MODE_TXPR_MASK)
19637 
19638 #define ENET_DMA_MODE_PR_MASK                    (0x7000U)
19639 #define ENET_DMA_MODE_PR_SHIFT                   (12U)
19640 /*! PR - Priority Ratio
19641  *  0b000..The priority ratio is 1:1
19642  *  0b001..The priority ratio is 2:1
19643  *  0b010..The priority ratio is 3:1
19644  *  0b011..The priority ratio is 4:1
19645  *  0b100..The priority ratio is 5:1
19646  *  0b101..The priority ratio is 6:1
19647  *  0b110..The priority ratio is 7:1
19648  *  0b111..The priority ratio is 8:1
19649  */
19650 #define ENET_DMA_MODE_PR(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_PR_SHIFT)) & ENET_DMA_MODE_PR_MASK)
19651 /*! @} */
19652 
19653 /*! @name DMA_SYSBUS_MODE - DMA System Bus Mode */
19654 /*! @{ */
19655 
19656 #define ENET_DMA_SYSBUS_MODE_FB_MASK             (0x1U)
19657 #define ENET_DMA_SYSBUS_MODE_FB_SHIFT            (0U)
19658 /*! FB - Fixed Burst Length
19659  *  0b0..Fixed Burst Length is disabled
19660  *  0b1..Fixed Burst Length is enabled
19661  */
19662 #define ENET_DMA_SYSBUS_MODE_FB(x)               (((uint32_t)(((uint32_t)(x)) << ENET_DMA_SYSBUS_MODE_FB_SHIFT)) & ENET_DMA_SYSBUS_MODE_FB_MASK)
19663 
19664 #define ENET_DMA_SYSBUS_MODE_AAL_MASK            (0x1000U)
19665 #define ENET_DMA_SYSBUS_MODE_AAL_SHIFT           (12U)
19666 /*! AAL - Address-Aligned Beats
19667  *  0b0..Address-Aligned Beats is disabled
19668  *  0b1..Address-Aligned Beats is enabled
19669  */
19670 #define ENET_DMA_SYSBUS_MODE_AAL(x)              (((uint32_t)(((uint32_t)(x)) << ENET_DMA_SYSBUS_MODE_AAL_SHIFT)) & ENET_DMA_SYSBUS_MODE_AAL_MASK)
19671 
19672 #define ENET_DMA_SYSBUS_MODE_MB_MASK             (0x4000U)
19673 #define ENET_DMA_SYSBUS_MODE_MB_SHIFT            (14U)
19674 /*! MB - Mixed Burst
19675  *  0b0..Mixed Burst is disabled
19676  *  0b1..Mixed Burst is enabled
19677  */
19678 #define ENET_DMA_SYSBUS_MODE_MB(x)               (((uint32_t)(((uint32_t)(x)) << ENET_DMA_SYSBUS_MODE_MB_SHIFT)) & ENET_DMA_SYSBUS_MODE_MB_MASK)
19679 
19680 #define ENET_DMA_SYSBUS_MODE_RB_MASK             (0x8000U)
19681 #define ENET_DMA_SYSBUS_MODE_RB_SHIFT            (15U)
19682 /*! RB - Rebuild INCRx Burst
19683  *  0b0..Rebuild INCRx Burst is disabled
19684  *  0b1..Rebuild INCRx Burst is enabled
19685  */
19686 #define ENET_DMA_SYSBUS_MODE_RB(x)               (((uint32_t)(((uint32_t)(x)) << ENET_DMA_SYSBUS_MODE_RB_SHIFT)) & ENET_DMA_SYSBUS_MODE_RB_MASK)
19687 /*! @} */
19688 
19689 /*! @name DMA_INTERRUPT_STATUS - DMA Interrupt Status */
19690 /*! @{ */
19691 
19692 #define ENET_DMA_INTERRUPT_STATUS_DC0IS_MASK     (0x1U)
19693 #define ENET_DMA_INTERRUPT_STATUS_DC0IS_SHIFT    (0U)
19694 /*! DC0IS - DMA Channel 0 Interrupt Status
19695  *  0b1..DMA Channel 0 Interrupt Status detected
19696  *  0b0..DMA Channel 0 Interrupt Status not detected
19697  */
19698 #define ENET_DMA_INTERRUPT_STATUS_DC0IS(x)       (((uint32_t)(((uint32_t)(x)) << ENET_DMA_INTERRUPT_STATUS_DC0IS_SHIFT)) & ENET_DMA_INTERRUPT_STATUS_DC0IS_MASK)
19699 
19700 #define ENET_DMA_INTERRUPT_STATUS_DC1IS_MASK     (0x2U)
19701 #define ENET_DMA_INTERRUPT_STATUS_DC1IS_SHIFT    (1U)
19702 /*! DC1IS - DMA Channel 1 Interrupt Status
19703  *  0b1..DMA Channel 1 Interrupt Status detected
19704  *  0b0..DMA Channel 1 Interrupt Status not detected
19705  */
19706 #define ENET_DMA_INTERRUPT_STATUS_DC1IS(x)       (((uint32_t)(((uint32_t)(x)) << ENET_DMA_INTERRUPT_STATUS_DC1IS_SHIFT)) & ENET_DMA_INTERRUPT_STATUS_DC1IS_MASK)
19707 
19708 #define ENET_DMA_INTERRUPT_STATUS_MTLIS_MASK     (0x10000U)
19709 #define ENET_DMA_INTERRUPT_STATUS_MTLIS_SHIFT    (16U)
19710 /*! MTLIS - MTL Interrupt Status
19711  *  0b1..MTL Interrupt Status detected
19712  *  0b0..MTL Interrupt Status not detected
19713  */
19714 #define ENET_DMA_INTERRUPT_STATUS_MTLIS(x)       (((uint32_t)(((uint32_t)(x)) << ENET_DMA_INTERRUPT_STATUS_MTLIS_SHIFT)) & ENET_DMA_INTERRUPT_STATUS_MTLIS_MASK)
19715 
19716 #define ENET_DMA_INTERRUPT_STATUS_MACIS_MASK     (0x20000U)
19717 #define ENET_DMA_INTERRUPT_STATUS_MACIS_SHIFT    (17U)
19718 /*! MACIS - MAC Interrupt Status
19719  *  0b1..MAC Interrupt Status detected
19720  *  0b0..MAC Interrupt Status not detected
19721  */
19722 #define ENET_DMA_INTERRUPT_STATUS_MACIS(x)       (((uint32_t)(((uint32_t)(x)) << ENET_DMA_INTERRUPT_STATUS_MACIS_SHIFT)) & ENET_DMA_INTERRUPT_STATUS_MACIS_MASK)
19723 /*! @} */
19724 
19725 /*! @name DMA_DEBUG_STATUS0 - DMA Debug Status 0 */
19726 /*! @{ */
19727 
19728 #define ENET_DMA_DEBUG_STATUS0_AXWHSTS_MASK      (0x1U)
19729 #define ENET_DMA_DEBUG_STATUS0_AXWHSTS_SHIFT     (0U)
19730 /*! AXWHSTS - AHB Master Status
19731  *  0b1..AXI Master Write Channel or AHB Master Status detected
19732  *  0b0..AXI Master Write Channel or AHB Master Status not detected
19733  */
19734 #define ENET_DMA_DEBUG_STATUS0_AXWHSTS(x)        (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DEBUG_STATUS0_AXWHSTS_SHIFT)) & ENET_DMA_DEBUG_STATUS0_AXWHSTS_MASK)
19735 
19736 #define ENET_DMA_DEBUG_STATUS0_RPS0_MASK         (0xF00U)
19737 #define ENET_DMA_DEBUG_STATUS0_RPS0_SHIFT        (8U)
19738 /*! RPS0 - DMA Channel 0 Receive Process State
19739  *  0b0010..Reserved for future use
19740  *  0b0101..Running (Closing the Rx Descriptor)
19741  *  0b0001..Running (Fetching Rx Transfer Descriptor)
19742  *  0b0111..Running (Transferring the received packet data from the Rx buffer to the system memory)
19743  *  0b0011..Running (Waiting for Rx packet)
19744  *  0b0000..Stopped (Reset or Stop Receive Command issued)
19745  *  0b0100..Suspended (Rx Descriptor Unavailable)
19746  *  0b0110..Timestamp write state
19747  */
19748 #define ENET_DMA_DEBUG_STATUS0_RPS0(x)           (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DEBUG_STATUS0_RPS0_SHIFT)) & ENET_DMA_DEBUG_STATUS0_RPS0_MASK)
19749 
19750 #define ENET_DMA_DEBUG_STATUS0_TPS0_MASK         (0xF000U)
19751 #define ENET_DMA_DEBUG_STATUS0_TPS0_SHIFT        (12U)
19752 /*! TPS0 - DMA Channel 0 Transmit Process State
19753  *  0b0101..Reserved for future use
19754  *  0b0111..Running (Closing Tx Descriptor)
19755  *  0b0001..Running (Fetching Tx Transfer Descriptor)
19756  *  0b0011..Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO))
19757  *  0b0010..Running (Waiting for status)
19758  *  0b0000..Stopped (Reset or Stop Transmit Command issued)
19759  *  0b0110..Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow)
19760  *  0b0100..Timestamp write state
19761  */
19762 #define ENET_DMA_DEBUG_STATUS0_TPS0(x)           (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DEBUG_STATUS0_TPS0_SHIFT)) & ENET_DMA_DEBUG_STATUS0_TPS0_MASK)
19763 
19764 #define ENET_DMA_DEBUG_STATUS0_RPS1_MASK         (0xF0000U)
19765 #define ENET_DMA_DEBUG_STATUS0_RPS1_SHIFT        (16U)
19766 /*! RPS1 - DMA Channel 1 Receive Process State
19767  *  0b0010..Reserved for future use
19768  *  0b0101..Running (Closing the Rx Descriptor)
19769  *  0b0001..Running (Fetching Rx Transfer Descriptor)
19770  *  0b0111..Running (Transferring the received packet data from the Rx buffer to the system memory)
19771  *  0b0011..Running (Waiting for Rx packet)
19772  *  0b0000..Stopped (Reset or Stop Receive Command issued)
19773  *  0b0100..Suspended (Rx Descriptor Unavailable)
19774  *  0b0110..Timestamp write state
19775  */
19776 #define ENET_DMA_DEBUG_STATUS0_RPS1(x)           (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DEBUG_STATUS0_RPS1_SHIFT)) & ENET_DMA_DEBUG_STATUS0_RPS1_MASK)
19777 
19778 #define ENET_DMA_DEBUG_STATUS0_TPS1_MASK         (0xF00000U)
19779 #define ENET_DMA_DEBUG_STATUS0_TPS1_SHIFT        (20U)
19780 /*! TPS1 - DMA Channel 1 Transmit Process State
19781  *  0b0101..Reserved for future use
19782  *  0b0111..Running (Closing Tx Descriptor)
19783  *  0b0001..Running (Fetching Tx Transfer Descriptor)
19784  *  0b0011..Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO))
19785  *  0b0010..Running (Waiting for status)
19786  *  0b0000..Stopped (Reset or Stop Transmit Command issued)
19787  *  0b0110..Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow)
19788  *  0b0100..Timestamp write state
19789  */
19790 #define ENET_DMA_DEBUG_STATUS0_TPS1(x)           (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DEBUG_STATUS0_TPS1_SHIFT)) & ENET_DMA_DEBUG_STATUS0_TPS1_MASK)
19791 /*! @} */
19792 
19793 /*! @name DMA_CH_DMA_CHX_CTRL - DMA Channel 0 Control..DMA Channel 1 Control */
19794 /*! @{ */
19795 
19796 #define ENET_DMA_CH_DMA_CHX_CTRL_PBLx8_MASK      (0x10000U)
19797 #define ENET_DMA_CH_DMA_CHX_CTRL_PBLx8_SHIFT     (16U)
19798 /*! PBLx8 - 8xPBL mode
19799  *  0b0..8xPBL mode is disabled
19800  *  0b1..8xPBL mode is enabled
19801  */
19802 #define ENET_DMA_CH_DMA_CHX_CTRL_PBLx8(x)        (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CTRL_PBLx8_SHIFT)) & ENET_DMA_CH_DMA_CHX_CTRL_PBLx8_MASK)
19803 
19804 #define ENET_DMA_CH_DMA_CHX_CTRL_DSL_MASK        (0x1C0000U)
19805 #define ENET_DMA_CH_DMA_CHX_CTRL_DSL_SHIFT       (18U)
19806 /*! DSL - Descriptor Skip Length */
19807 #define ENET_DMA_CH_DMA_CHX_CTRL_DSL(x)          (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CTRL_DSL_SHIFT)) & ENET_DMA_CH_DMA_CHX_CTRL_DSL_MASK)
19808 /*! @} */
19809 
19810 /* The count of ENET_DMA_CH_DMA_CHX_CTRL */
19811 #define ENET_DMA_CH_DMA_CHX_CTRL_COUNT           (2U)
19812 
19813 /*! @name DMA_CH_DMA_CHX_TX_CTRL - DMA Channel 0 Transmit Control..DMA Channel 1 Transmit Control */
19814 /*! @{ */
19815 
19816 #define ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_MASK      (0x1U)
19817 #define ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_SHIFT     (0U)
19818 /*! ST - Start or Stop Transmission Command
19819  *  0b1..Start Transmission Command
19820  *  0b0..Stop Transmission Command
19821  */
19822 #define ENET_DMA_CH_DMA_CHX_TX_CTRL_ST(x)        (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_SHIFT)) & ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_MASK)
19823 
19824 #define ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW_MASK     (0xEU)
19825 #define ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW_SHIFT    (1U)
19826 /*! TCW - Transmit Channel Weight */
19827 #define ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW(x)       (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW_SHIFT)) & ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW_MASK)
19828 
19829 #define ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF_MASK     (0x10U)
19830 #define ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF_SHIFT    (4U)
19831 /*! OSF - Operate on Second Packet
19832  *  0b0..Operate on Second Packet disabled
19833  *  0b1..Operate on Second Packet enabled
19834  */
19835 #define ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF(x)       (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF_SHIFT)) & ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF_MASK)
19836 
19837 #define ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_MASK   (0x3F0000U)
19838 #define ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_SHIFT  (16U)
19839 /*! TxPBL - Transmit Programmable Burst Length */
19840 #define ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL(x)     (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_SHIFT)) & ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_MASK)
19841 
19842 #define ENET_DMA_CH_DMA_CHX_TX_CTRL_ETIC_MASK    (0x400000U)
19843 #define ENET_DMA_CH_DMA_CHX_TX_CTRL_ETIC_SHIFT   (22U)
19844 /*! ETIC - Early Transmit Interrupt Control
19845  *  0b0..Early Transmit Interrupt is disabled
19846  *  0b1..Early Transmit Interrupt is enabled
19847  */
19848 #define ENET_DMA_CH_DMA_CHX_TX_CTRL_ETIC(x)      (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TX_CTRL_ETIC_SHIFT)) & ENET_DMA_CH_DMA_CHX_TX_CTRL_ETIC_MASK)
19849 /*! @} */
19850 
19851 /* The count of ENET_DMA_CH_DMA_CHX_TX_CTRL */
19852 #define ENET_DMA_CH_DMA_CHX_TX_CTRL_COUNT        (2U)
19853 
19854 /*! @name DMA_CH_DMA_CHX_RX_CTRL - DMA Channel 0 Receive Control..DMA Channel 1 Receive Control */
19855 /*! @{ */
19856 
19857 #define ENET_DMA_CH_DMA_CHX_RX_CTRL_SR_MASK      (0x1U)
19858 #define ENET_DMA_CH_DMA_CHX_RX_CTRL_SR_SHIFT     (0U)
19859 /*! SR - Start or Stop Receive
19860  *  0b1..Start Receive
19861  *  0b0..Stop Receive
19862  */
19863 #define ENET_DMA_CH_DMA_CHX_RX_CTRL_SR(x)        (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_CTRL_SR_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_CTRL_SR_MASK)
19864 
19865 #define ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_X_0_MASK (0x6U)
19866 #define ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_X_0_SHIFT (1U)
19867 /*! RBSZ_X_0 - Receive Buffer size Low */
19868 #define ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_X_0(x)  (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_X_0_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_X_0_MASK)
19869 
19870 #define ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_13_Y_MASK (0x7FF8U)
19871 #define ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_13_Y_SHIFT (3U)
19872 /*! RBSZ_13_Y - Receive Buffer size High */
19873 #define ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_13_Y(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_13_Y_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_13_Y_MASK)
19874 
19875 #define ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL_MASK   (0x3F0000U)
19876 #define ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL_SHIFT  (16U)
19877 /*! RxPBL - Receive Programmable Burst Length */
19878 #define ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL(x)     (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL_MASK)
19879 
19880 #define ENET_DMA_CH_DMA_CHX_RX_CTRL_ERIC_MASK    (0x400000U)
19881 #define ENET_DMA_CH_DMA_CHX_RX_CTRL_ERIC_SHIFT   (22U)
19882 /*! ERIC - Early Receive Interrupt Control
19883  *  0b0..Early Receive Interrupt is disabled
19884  *  0b1..Early Receive Interrupt is enabled
19885  */
19886 #define ENET_DMA_CH_DMA_CHX_RX_CTRL_ERIC(x)      (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_CTRL_ERIC_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_CTRL_ERIC_MASK)
19887 
19888 #define ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF_MASK     (0x80000000U)
19889 #define ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF_SHIFT    (31U)
19890 /*! RPF - Rx Packet Flush.
19891  *  0b0..Rx Packet Flush is disabled
19892  *  0b1..Rx Packet Flush is enabled
19893  */
19894 #define ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF(x)       (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF_MASK)
19895 /*! @} */
19896 
19897 /* The count of ENET_DMA_CH_DMA_CHX_RX_CTRL */
19898 #define ENET_DMA_CH_DMA_CHX_RX_CTRL_COUNT        (2U)
19899 
19900 /*! @name DMA_CH_DMA_CHX_TXDESC_LIST_ADDR - Channel 0 Tx Descriptor List Address register..Channel 1 Tx Descriptor List Address */
19901 /*! @{ */
19902 
19903 #define ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_TDESLA_MASK (0xFFFFFFFCU)
19904 #define ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_TDESLA_SHIFT (2U)
19905 /*! TDESLA - Start of Transmit List */
19906 #define ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_TDESLA(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_TDESLA_SHIFT)) & ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_TDESLA_MASK)
19907 /*! @} */
19908 
19909 /* The count of ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR */
19910 #define ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_COUNT (2U)
19911 
19912 /*! @name DMA_CH_DMA_CHX_RXDESC_LIST_ADDR - Channel 0 Rx Descriptor List Address register..Channel 1 Rx Descriptor List Address */
19913 /*! @{ */
19914 
19915 #define ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_RDESLA_MASK (0xFFFFFFFCU)
19916 #define ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_RDESLA_SHIFT (2U)
19917 /*! RDESLA - Start of Receive List */
19918 #define ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_RDESLA(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_RDESLA_SHIFT)) & ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_RDESLA_MASK)
19919 /*! @} */
19920 
19921 /* The count of ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR */
19922 #define ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_COUNT (2U)
19923 
19924 /*! @name DMA_CH_DMA_CHX_TXDESC_TAIL_PTR - Channel 0 Tx Descriptor Tail Pointer..Channel 1 Tx Descriptor Tail Pointer */
19925 /*! @{ */
19926 
19927 #define ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP_MASK (0xFFFFFFFCU)
19928 #define ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP_SHIFT (2U)
19929 /*! TDTP - Transmit Descriptor Tail Pointer */
19930 #define ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP_SHIFT)) & ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP_MASK)
19931 /*! @} */
19932 
19933 /* The count of ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR */
19934 #define ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_COUNT (2U)
19935 
19936 /*! @name DMA_CH_DMA_CHX_RXDESC_TAIL_PTR - Channel 0 Rx Descriptor Tail Pointer..Channel 1 Rx Descriptor Tail Pointer */
19937 /*! @{ */
19938 
19939 #define ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP_MASK (0xFFFFFFFCU)
19940 #define ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP_SHIFT (2U)
19941 /*! RDTP - Receive Descriptor Tail Pointer */
19942 #define ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP_SHIFT)) & ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP_MASK)
19943 /*! @} */
19944 
19945 /* The count of ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR */
19946 #define ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_COUNT (2U)
19947 
19948 /*! @name DMA_CH_DMA_CHX_TXDESC_RING_LENGTH - Channel 0 Tx Descriptor Ring Length..Channel 1 Tx Descriptor Ring Length */
19949 /*! @{ */
19950 
19951 #define ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL_MASK (0x3FFU)
19952 #define ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL_SHIFT (0U)
19953 /*! TDRL - Transmit Descriptor Ring Length */
19954 #define ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL_SHIFT)) & ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL_MASK)
19955 /*! @} */
19956 
19957 /* The count of ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH */
19958 #define ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_COUNT (2U)
19959 
19960 /*! @name DMA_CH_DMA_CHX_RX_CONTROL2 - Channeli Receive Control..DMA Channel 1 Receive Control */
19961 /*! @{ */
19962 
19963 #define ENET_DMA_CH_DMA_CHX_RX_CONTROL2_RDRL_MASK (0x3FFU)
19964 #define ENET_DMA_CH_DMA_CHX_RX_CONTROL2_RDRL_SHIFT (0U)
19965 /*! RDRL - Receive Descriptor Ring Length */
19966 #define ENET_DMA_CH_DMA_CHX_RX_CONTROL2_RDRL(x)  (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_CONTROL2_RDRL_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_CONTROL2_RDRL_MASK)
19967 
19968 #define ENET_DMA_CH_DMA_CHX_RX_CONTROL2_ARBS_MASK (0xFF0000U)
19969 #define ENET_DMA_CH_DMA_CHX_RX_CONTROL2_ARBS_SHIFT (16U)
19970 /*! ARBS - Alternate Receive Buffer Size */
19971 #define ENET_DMA_CH_DMA_CHX_RX_CONTROL2_ARBS(x)  (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_CONTROL2_ARBS_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_CONTROL2_ARBS_MASK)
19972 /*! @} */
19973 
19974 /* The count of ENET_DMA_CH_DMA_CHX_RX_CONTROL2 */
19975 #define ENET_DMA_CH_DMA_CHX_RX_CONTROL2_COUNT    (2U)
19976 
19977 /*! @name DMA_CH_DMA_CHX_INT_EN - Channeli Interrupt Enable..Channel 1 Interrupt Enable */
19978 /*! @{ */
19979 
19980 #define ENET_DMA_CH_DMA_CHX_INT_EN_TIE_MASK      (0x1U)
19981 #define ENET_DMA_CH_DMA_CHX_INT_EN_TIE_SHIFT     (0U)
19982 /*! TIE - Transmit Interrupt Enable
19983  *  0b0..Transmit Interrupt is disabled
19984  *  0b1..Transmit Interrupt is enabled
19985  */
19986 #define ENET_DMA_CH_DMA_CHX_INT_EN_TIE(x)        (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_TIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_TIE_MASK)
19987 
19988 #define ENET_DMA_CH_DMA_CHX_INT_EN_TXSE_MASK     (0x2U)
19989 #define ENET_DMA_CH_DMA_CHX_INT_EN_TXSE_SHIFT    (1U)
19990 /*! TXSE - Transmit Stopped Enable
19991  *  0b0..Transmit Stopped is disabled
19992  *  0b1..Transmit Stopped is enabled
19993  */
19994 #define ENET_DMA_CH_DMA_CHX_INT_EN_TXSE(x)       (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_TXSE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_TXSE_MASK)
19995 
19996 #define ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_MASK     (0x4U)
19997 #define ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_SHIFT    (2U)
19998 /*! TBUE - Transmit Buffer Unavailable Enable
19999  *  0b0..Transmit Buffer Unavailable is disabled
20000  *  0b1..Transmit Buffer Unavailable is enabled
20001  */
20002 #define ENET_DMA_CH_DMA_CHX_INT_EN_TBUE(x)       (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_MASK)
20003 
20004 #define ENET_DMA_CH_DMA_CHX_INT_EN_RIE_MASK      (0x40U)
20005 #define ENET_DMA_CH_DMA_CHX_INT_EN_RIE_SHIFT     (6U)
20006 /*! RIE - Receive Interrupt Enable
20007  *  0b0..Receive Interrupt is disabled
20008  *  0b1..Receive Interrupt is enabled
20009  */
20010 #define ENET_DMA_CH_DMA_CHX_INT_EN_RIE(x)        (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_RIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_RIE_MASK)
20011 
20012 #define ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_MASK     (0x80U)
20013 #define ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_SHIFT    (7U)
20014 /*! RBUE - Receive Buffer Unavailable Enable
20015  *  0b0..Receive Buffer Unavailable is disabled
20016  *  0b1..Receive Buffer Unavailable is enabled
20017  */
20018 #define ENET_DMA_CH_DMA_CHX_INT_EN_RBUE(x)       (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_MASK)
20019 
20020 #define ENET_DMA_CH_DMA_CHX_INT_EN_RSE_MASK      (0x100U)
20021 #define ENET_DMA_CH_DMA_CHX_INT_EN_RSE_SHIFT     (8U)
20022 /*! RSE - Receive Stopped Enable
20023  *  0b0..Receive Stopped is disabled
20024  *  0b1..Receive Stopped is enabled
20025  */
20026 #define ENET_DMA_CH_DMA_CHX_INT_EN_RSE(x)        (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_RSE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_RSE_MASK)
20027 
20028 #define ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_MASK     (0x200U)
20029 #define ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_SHIFT    (9U)
20030 /*! RWTE - Receive Watchdog Timeout Enable
20031  *  0b0..Receive Watchdog Timeout is disabled
20032  *  0b1..Receive Watchdog Timeout is enabled
20033  */
20034 #define ENET_DMA_CH_DMA_CHX_INT_EN_RWTE(x)       (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_MASK)
20035 
20036 #define ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_MASK     (0x400U)
20037 #define ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_SHIFT    (10U)
20038 /*! ETIE - Early Transmit Interrupt Enable
20039  *  0b0..Early Transmit Interrupt is disabled
20040  *  0b1..Early Transmit Interrupt is enabled
20041  */
20042 #define ENET_DMA_CH_DMA_CHX_INT_EN_ETIE(x)       (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_MASK)
20043 
20044 #define ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_MASK     (0x800U)
20045 #define ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_SHIFT    (11U)
20046 /*! ERIE - Early Receive Interrupt Enable
20047  *  0b0..Early Receive Interrupt is disabled
20048  *  0b1..Early Receive Interrupt is enabled
20049  */
20050 #define ENET_DMA_CH_DMA_CHX_INT_EN_ERIE(x)       (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_MASK)
20051 
20052 #define ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_MASK     (0x1000U)
20053 #define ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_SHIFT    (12U)
20054 /*! FBEE - Fatal Bus Error Enable
20055  *  0b0..Fatal Bus Error is disabled
20056  *  0b1..Fatal Bus Error is enabled
20057  */
20058 #define ENET_DMA_CH_DMA_CHX_INT_EN_FBEE(x)       (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_MASK)
20059 
20060 #define ENET_DMA_CH_DMA_CHX_INT_EN_CDEE_MASK     (0x2000U)
20061 #define ENET_DMA_CH_DMA_CHX_INT_EN_CDEE_SHIFT    (13U)
20062 /*! CDEE - Context Descriptor Error Enable
20063  *  0b0..Context Descriptor Error is disabled
20064  *  0b1..Context Descriptor Error is enabled
20065  */
20066 #define ENET_DMA_CH_DMA_CHX_INT_EN_CDEE(x)       (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_CDEE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_CDEE_MASK)
20067 
20068 #define ENET_DMA_CH_DMA_CHX_INT_EN_AIE_MASK      (0x4000U)
20069 #define ENET_DMA_CH_DMA_CHX_INT_EN_AIE_SHIFT     (14U)
20070 /*! AIE - Abnormal Interrupt Summary Enable
20071  *  0b0..Abnormal Interrupt Summary is disabled
20072  *  0b1..Abnormal Interrupt Summary is enabled
20073  */
20074 #define ENET_DMA_CH_DMA_CHX_INT_EN_AIE(x)        (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_AIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_AIE_MASK)
20075 
20076 #define ENET_DMA_CH_DMA_CHX_INT_EN_NIE_MASK      (0x8000U)
20077 #define ENET_DMA_CH_DMA_CHX_INT_EN_NIE_SHIFT     (15U)
20078 /*! NIE - Normal Interrupt Summary Enable
20079  *  0b0..Normal Interrupt Summary is disabled
20080  *  0b1..Normal Interrupt Summary is enabled
20081  */
20082 #define ENET_DMA_CH_DMA_CHX_INT_EN_NIE(x)        (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_NIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_NIE_MASK)
20083 /*! @} */
20084 
20085 /* The count of ENET_DMA_CH_DMA_CHX_INT_EN */
20086 #define ENET_DMA_CH_DMA_CHX_INT_EN_COUNT         (2U)
20087 
20088 /*! @name DMA_CH_DMA_CHX_RX_INT_WDTIMER - Channel 0 Receive Interrupt Watchdog Timer..Channel 1 Receive Interrupt Watchdog Timer */
20089 /*! @{ */
20090 
20091 #define ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RWT_MASK (0xFFU)
20092 #define ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RWT_SHIFT (0U)
20093 /*! RWT - Receive Interrupt Watchdog Timer Count */
20094 #define ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RWT(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RWT_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RWT_MASK)
20095 
20096 #define ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RWTU_MASK (0x30000U)
20097 #define ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RWTU_SHIFT (16U)
20098 /*! RWTU - Receive Interrupt Watchdog Timer Count Units */
20099 #define ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RWTU(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RWTU_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RWTU_MASK)
20100 /*! @} */
20101 
20102 /* The count of ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER */
20103 #define ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_COUNT (2U)
20104 
20105 /*! @name DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT - Channel 0 Slot Function Control and Status..Channel 1 Slot Function Control and Status */
20106 /*! @{ */
20107 
20108 #define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_MASK (0x1U)
20109 #define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_SHIFT (0U)
20110 /*! ESC - Enable Slot Comparison
20111  *  0b0..Slot Comparison is disabled
20112  *  0b1..Slot Comparison is enabled
20113  */
20114 #define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_SHIFT)) & ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_MASK)
20115 
20116 #define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_MASK (0x2U)
20117 #define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_SHIFT (1U)
20118 /*! ASC - Advance Slot Check
20119  *  0b0..Advance Slot Check is disabled
20120  *  0b1..Advance Slot Check is enabled
20121  */
20122 #define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_SHIFT)) & ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_MASK)
20123 
20124 #define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_SIV_MASK (0xFFF0U)
20125 #define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_SIV_SHIFT (4U)
20126 /*! SIV - Slot Interval Value */
20127 #define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_SIV(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_SIV_SHIFT)) & ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_SIV_MASK)
20128 
20129 #define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_MASK (0xF0000U)
20130 #define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_SHIFT (16U)
20131 /*! RSN - Reference Slot Number */
20132 #define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_SHIFT)) & ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_MASK)
20133 /*! @} */
20134 
20135 /* The count of ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT */
20136 #define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_COUNT (2U)
20137 
20138 /*! @name DMA_CH_DMA_CHX_CUR_HST_TXDESC - Channel 0 Current Application Transmit Descriptor..Channel 1 Current Application Transmit Descriptor */
20139 /*! @{ */
20140 
20141 #define ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_CURTDESAPTR_MASK (0xFFFFFFFFU)
20142 #define ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_CURTDESAPTR_SHIFT (0U)
20143 /*! CURTDESAPTR - Application Transmit Descriptor Address Pointer */
20144 #define ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_CURTDESAPTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_CURTDESAPTR_SHIFT)) & ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_CURTDESAPTR_MASK)
20145 /*! @} */
20146 
20147 /* The count of ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC */
20148 #define ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_COUNT (2U)
20149 
20150 /*! @name DMA_CH_DMA_CHX_CUR_HST_RXDESC - Channel 0 Current Application Receive Descriptor..Channel 1 Current Application Receive Descriptor */
20151 /*! @{ */
20152 
20153 #define ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_CURRDESAPTR_MASK (0xFFFFFFFFU)
20154 #define ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_CURRDESAPTR_SHIFT (0U)
20155 /*! CURRDESAPTR - Application Receive Descriptor Address Pointer */
20156 #define ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_CURRDESAPTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_CURRDESAPTR_SHIFT)) & ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_CURRDESAPTR_MASK)
20157 /*! @} */
20158 
20159 /* The count of ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC */
20160 #define ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_COUNT (2U)
20161 
20162 /*! @name DMA_CH_DMA_CHX_CUR_HST_TXBUF - Channel 0 Current Application Transmit Buffer Address..Channel 1 Current Application Transmit Buffer Address */
20163 /*! @{ */
20164 
20165 #define ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_CURTBUFAPTR_MASK (0xFFFFFFFFU)
20166 #define ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_CURTBUFAPTR_SHIFT (0U)
20167 /*! CURTBUFAPTR - Application Transmit Buffer Address Pointer */
20168 #define ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_CURTBUFAPTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_CURTBUFAPTR_SHIFT)) & ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_CURTBUFAPTR_MASK)
20169 /*! @} */
20170 
20171 /* The count of ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF */
20172 #define ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_COUNT  (2U)
20173 
20174 /*! @name DMA_CH_DMA_CHX_CUR_HST_RXBUF - Channel 0 Current Application Receive Buffer Address..Channel 1 Current Application Receive Buffer Address */
20175 /*! @{ */
20176 
20177 #define ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_CURRBUFAPTR_MASK (0xFFFFFFFFU)
20178 #define ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_CURRBUFAPTR_SHIFT (0U)
20179 /*! CURRBUFAPTR - Application Receive Buffer Address Pointer */
20180 #define ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_CURRBUFAPTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_CURRBUFAPTR_SHIFT)) & ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_CURRBUFAPTR_MASK)
20181 /*! @} */
20182 
20183 /* The count of ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF */
20184 #define ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_COUNT  (2U)
20185 
20186 /*! @name DMA_CH_DMA_CHX_STAT - DMA Channel 0 Status..DMA Channel 1 Status */
20187 /*! @{ */
20188 
20189 #define ENET_DMA_CH_DMA_CHX_STAT_TI_MASK         (0x1U)
20190 #define ENET_DMA_CH_DMA_CHX_STAT_TI_SHIFT        (0U)
20191 /*! TI - Transmit Interrupt
20192  *  0b1..Transmit Interrupt status detected
20193  *  0b0..Transmit Interrupt status not detected
20194  */
20195 #define ENET_DMA_CH_DMA_CHX_STAT_TI(x)           (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_TI_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_TI_MASK)
20196 
20197 #define ENET_DMA_CH_DMA_CHX_STAT_TPS_MASK        (0x2U)
20198 #define ENET_DMA_CH_DMA_CHX_STAT_TPS_SHIFT       (1U)
20199 /*! TPS - Transmit Process Stopped
20200  *  0b1..Transmit Process Stopped status detected
20201  *  0b0..Transmit Process Stopped status not detected
20202  */
20203 #define ENET_DMA_CH_DMA_CHX_STAT_TPS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_TPS_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_TPS_MASK)
20204 
20205 #define ENET_DMA_CH_DMA_CHX_STAT_TBU_MASK        (0x4U)
20206 #define ENET_DMA_CH_DMA_CHX_STAT_TBU_SHIFT       (2U)
20207 /*! TBU - Transmit Buffer Unavailable
20208  *  0b1..Transmit Buffer Unavailable status detected
20209  *  0b0..Transmit Buffer Unavailable status not detected
20210  */
20211 #define ENET_DMA_CH_DMA_CHX_STAT_TBU(x)          (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_TBU_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_TBU_MASK)
20212 
20213 #define ENET_DMA_CH_DMA_CHX_STAT_RI_MASK         (0x40U)
20214 #define ENET_DMA_CH_DMA_CHX_STAT_RI_SHIFT        (6U)
20215 /*! RI - Receive Interrupt
20216  *  0b1..Receive Interrupt status detected
20217  *  0b0..Receive Interrupt status not detected
20218  */
20219 #define ENET_DMA_CH_DMA_CHX_STAT_RI(x)           (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_RI_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_RI_MASK)
20220 
20221 #define ENET_DMA_CH_DMA_CHX_STAT_RBU_MASK        (0x80U)
20222 #define ENET_DMA_CH_DMA_CHX_STAT_RBU_SHIFT       (7U)
20223 /*! RBU - Receive Buffer Unavailable
20224  *  0b1..Receive Buffer Unavailable status detected
20225  *  0b0..Receive Buffer Unavailable status not detected
20226  */
20227 #define ENET_DMA_CH_DMA_CHX_STAT_RBU(x)          (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_RBU_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_RBU_MASK)
20228 
20229 #define ENET_DMA_CH_DMA_CHX_STAT_RPS_MASK        (0x100U)
20230 #define ENET_DMA_CH_DMA_CHX_STAT_RPS_SHIFT       (8U)
20231 /*! RPS - Receive Process Stopped
20232  *  0b1..Receive Process Stopped status detected
20233  *  0b0..Receive Process Stopped status not detected
20234  */
20235 #define ENET_DMA_CH_DMA_CHX_STAT_RPS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_RPS_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_RPS_MASK)
20236 
20237 #define ENET_DMA_CH_DMA_CHX_STAT_RWT_MASK        (0x200U)
20238 #define ENET_DMA_CH_DMA_CHX_STAT_RWT_SHIFT       (9U)
20239 /*! RWT - Receive Watchdog Timeout
20240  *  0b1..Receive Watchdog Timeout status detected
20241  *  0b0..Receive Watchdog Timeout status not detected
20242  */
20243 #define ENET_DMA_CH_DMA_CHX_STAT_RWT(x)          (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_RWT_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_RWT_MASK)
20244 
20245 #define ENET_DMA_CH_DMA_CHX_STAT_ETI_MASK        (0x400U)
20246 #define ENET_DMA_CH_DMA_CHX_STAT_ETI_SHIFT       (10U)
20247 /*! ETI - Early Transmit Interrupt
20248  *  0b1..Early Transmit Interrupt status detected
20249  *  0b0..Early Transmit Interrupt status not detected
20250  */
20251 #define ENET_DMA_CH_DMA_CHX_STAT_ETI(x)          (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_ETI_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_ETI_MASK)
20252 
20253 #define ENET_DMA_CH_DMA_CHX_STAT_ERI_MASK        (0x800U)
20254 #define ENET_DMA_CH_DMA_CHX_STAT_ERI_SHIFT       (11U)
20255 /*! ERI - Early Receive Interrupt
20256  *  0b1..Early Receive Interrupt status detected
20257  *  0b0..Early Receive Interrupt status not detected
20258  */
20259 #define ENET_DMA_CH_DMA_CHX_STAT_ERI(x)          (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_ERI_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_ERI_MASK)
20260 
20261 #define ENET_DMA_CH_DMA_CHX_STAT_FBE_MASK        (0x1000U)
20262 #define ENET_DMA_CH_DMA_CHX_STAT_FBE_SHIFT       (12U)
20263 /*! FBE - Fatal Bus Error
20264  *  0b1..Fatal Bus Error status detected
20265  *  0b0..Fatal Bus Error status not detected
20266  */
20267 #define ENET_DMA_CH_DMA_CHX_STAT_FBE(x)          (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_FBE_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_FBE_MASK)
20268 
20269 #define ENET_DMA_CH_DMA_CHX_STAT_CDE_MASK        (0x2000U)
20270 #define ENET_DMA_CH_DMA_CHX_STAT_CDE_SHIFT       (13U)
20271 /*! CDE - Context Descriptor Error
20272  *  0b1..Context Descriptor Error status detected
20273  *  0b0..Context Descriptor Error status not detected
20274  */
20275 #define ENET_DMA_CH_DMA_CHX_STAT_CDE(x)          (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_CDE_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_CDE_MASK)
20276 
20277 #define ENET_DMA_CH_DMA_CHX_STAT_AIS_MASK        (0x4000U)
20278 #define ENET_DMA_CH_DMA_CHX_STAT_AIS_SHIFT       (14U)
20279 /*! AIS - Abnormal Interrupt Summary
20280  *  0b1..Abnormal Interrupt Summary status detected
20281  *  0b0..Abnormal Interrupt Summary status not detected
20282  */
20283 #define ENET_DMA_CH_DMA_CHX_STAT_AIS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_AIS_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_AIS_MASK)
20284 
20285 #define ENET_DMA_CH_DMA_CHX_STAT_NIS_MASK        (0x8000U)
20286 #define ENET_DMA_CH_DMA_CHX_STAT_NIS_SHIFT       (15U)
20287 /*! NIS - Normal Interrupt Summary
20288  *  0b1..Normal Interrupt Summary status detected
20289  *  0b0..Normal Interrupt Summary status not detected
20290  */
20291 #define ENET_DMA_CH_DMA_CHX_STAT_NIS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_NIS_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_NIS_MASK)
20292 
20293 #define ENET_DMA_CH_DMA_CHX_STAT_TEB_MASK        (0x70000U)
20294 #define ENET_DMA_CH_DMA_CHX_STAT_TEB_SHIFT       (16U)
20295 /*! TEB - Tx DMA Error Bits */
20296 #define ENET_DMA_CH_DMA_CHX_STAT_TEB(x)          (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_TEB_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_TEB_MASK)
20297 
20298 #define ENET_DMA_CH_DMA_CHX_STAT_REB_MASK        (0x380000U)
20299 #define ENET_DMA_CH_DMA_CHX_STAT_REB_SHIFT       (19U)
20300 /*! REB - Rx DMA Error Bits */
20301 #define ENET_DMA_CH_DMA_CHX_STAT_REB(x)          (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_REB_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_REB_MASK)
20302 /*! @} */
20303 
20304 /* The count of ENET_DMA_CH_DMA_CHX_STAT */
20305 #define ENET_DMA_CH_DMA_CHX_STAT_COUNT           (2U)
20306 
20307 /*! @name DMA_CH_DMA_CHX_MISS_FRAME_CNT - Channel 0 Missed Frame Counter..Channel 1 Missed Frame Counter */
20308 /*! @{ */
20309 
20310 #define ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_MFC_MASK (0x7FFU)
20311 #define ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_MFC_SHIFT (0U)
20312 /*! MFC - Dropped Packet Counters */
20313 #define ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_MFC(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_MFC_SHIFT)) & ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_MFC_MASK)
20314 
20315 #define ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_MFCO_MASK (0x8000U)
20316 #define ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_MFCO_SHIFT (15U)
20317 /*! MFCO - Overflow status of the MFC Counter
20318  *  0b1..Miss Frame Counter overflow occurred
20319  *  0b0..Miss Frame Counter overflow not occurred
20320  */
20321 #define ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_MFCO(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_MFCO_SHIFT)) & ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_MFCO_MASK)
20322 /*! @} */
20323 
20324 /* The count of ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT */
20325 #define ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_COUNT (2U)
20326 
20327 /*! @name DMA_CH_DMA_CHX_RX_ERI_CNT - Channel 0 Receive ERI Counter..Channel 1 Receive ERI Counter */
20328 /*! @{ */
20329 
20330 #define ENET_DMA_CH_DMA_CHX_RX_ERI_CNT_ECNT_MASK (0xFFFU)
20331 #define ENET_DMA_CH_DMA_CHX_RX_ERI_CNT_ECNT_SHIFT (0U)
20332 /*! ECNT - ERI Counter */
20333 #define ENET_DMA_CH_DMA_CHX_RX_ERI_CNT_ECNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_ERI_CNT_ECNT_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_ERI_CNT_ECNT_MASK)
20334 /*! @} */
20335 
20336 /* The count of ENET_DMA_CH_DMA_CHX_RX_ERI_CNT */
20337 #define ENET_DMA_CH_DMA_CHX_RX_ERI_CNT_COUNT     (2U)
20338 
20339 
20340 /*!
20341  * @}
20342  */ /* end of group ENET_Register_Masks */
20343 
20344 
20345 /* ENET - Peripheral instance base addresses */
20346 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
20347   /** Peripheral ENET0 base address */
20348   #define ENET0_BASE                               (0x50100000u)
20349   /** Peripheral ENET0 base address */
20350   #define ENET0_BASE_NS                            (0x40100000u)
20351   /** Peripheral ENET0 base pointer */
20352   #define ENET0                                    ((ENET_Type *)ENET0_BASE)
20353   /** Peripheral ENET0 base pointer */
20354   #define ENET0_NS                                 ((ENET_Type *)ENET0_BASE_NS)
20355   /** Array initializer of ENET peripheral base addresses */
20356   #define ENET_BASE_ADDRS                          { ENET0_BASE }
20357   /** Array initializer of ENET peripheral base pointers */
20358   #define ENET_BASE_PTRS                           { ENET0 }
20359   /** Array initializer of ENET peripheral base addresses */
20360   #define ENET_BASE_ADDRS_NS                       { ENET0_BASE_NS }
20361   /** Array initializer of ENET peripheral base pointers */
20362   #define ENET_BASE_PTRS_NS                        { ENET0_NS }
20363 #else
20364   /** Peripheral ENET0 base address */
20365   #define ENET0_BASE                               (0x40100000u)
20366   /** Peripheral ENET0 base pointer */
20367   #define ENET0                                    ((ENET_Type *)ENET0_BASE)
20368   /** Array initializer of ENET peripheral base addresses */
20369   #define ENET_BASE_ADDRS                          { ENET0_BASE }
20370   /** Array initializer of ENET peripheral base pointers */
20371   #define ENET_BASE_PTRS                           { ENET0 }
20372 #endif
20373 /** Interrupt vectors for the ENET peripheral type */
20374 #define ENET_IRQS                                { ETHERNET_IRQn }
20375 #define ENET_PMT_IRQS                            { ETHERNET_PMT_IRQn }
20376 #define ENET_MACLP_IRQS                          { ETHERNET_MACLP_IRQn }
20377 /* Backward compatibility */
20378 #define ENET ENET0
20379 
20380 
20381 /*!
20382  * @}
20383  */ /* end of group ENET_Peripheral_Access_Layer */
20384 
20385 
20386 /* ----------------------------------------------------------------------------
20387    -- ERM Peripheral Access Layer
20388    ---------------------------------------------------------------------------- */
20389 
20390 /*!
20391  * @addtogroup ERM_Peripheral_Access_Layer ERM Peripheral Access Layer
20392  * @{
20393  */
20394 
20395 /** ERM - Register Layout Typedef */
20396 typedef struct {
20397   __IO uint32_t CR0;                               /**< ERM Configuration Register 0, offset: 0x0 */
20398   __IO uint32_t CR1;                               /**< ERM Configuration Register 1, offset: 0x4 */
20399        uint8_t RESERVED_0[8];
20400   __IO uint32_t SR0;                               /**< ERM Status Register 0, offset: 0x10 */
20401   __IO uint32_t SR1;                               /**< ERM Status Register 1, offset: 0x14 */
20402        uint8_t RESERVED_1[232];
20403   __I  uint32_t EAR0;                              /**< ERM Memory 0 Error Address Register, offset: 0x100 */
20404   __I  uint32_t SYN0;                              /**< ERM Memory 0 Syndrome Register, offset: 0x104 */
20405   __IO uint32_t CORR_ERR_CNT0;                     /**< ERM Memory 0 Correctable Error Count Register, offset: 0x108 */
20406        uint8_t RESERVED_2[4];
20407   __I  uint32_t EAR1;                              /**< ERM Memory 1 Error Address Register, offset: 0x110 */
20408   __I  uint32_t SYN1;                              /**< ERM Memory 1 Syndrome Register, offset: 0x114 */
20409   __IO uint32_t CORR_ERR_CNT1;                     /**< ERM Memory 1 Correctable Error Count Register, offset: 0x118 */
20410        uint8_t RESERVED_3[4];
20411   __I  uint32_t EAR2;                              /**< ERM Memory 2 Error Address Register, offset: 0x120 */
20412   __I  uint32_t SYN2;                              /**< ERM Memory 2 Syndrome Register, offset: 0x124 */
20413   __IO uint32_t CORR_ERR_CNT2;                     /**< ERM Memory 2 Correctable Error Count Register, offset: 0x128 */
20414        uint8_t RESERVED_4[4];
20415   __I  uint32_t EAR3;                              /**< ERM Memory 3 Error Address Register, offset: 0x130 */
20416   __I  uint32_t SYN3;                              /**< ERM Memory 3 Syndrome Register, offset: 0x134 */
20417   __IO uint32_t CORR_ERR_CNT3;                     /**< ERM Memory 3 Correctable Error Count Register, offset: 0x138 */
20418        uint8_t RESERVED_5[4];
20419   __I  uint32_t EAR4;                              /**< ERM Memory 4 Error Address Register, offset: 0x140 */
20420   __I  uint32_t SYN4;                              /**< ERM Memory 4 Syndrome Register, offset: 0x144 */
20421   __IO uint32_t CORR_ERR_CNT4;                     /**< ERM Memory 4 Correctable Error Count Register, offset: 0x148 */
20422        uint8_t RESERVED_6[4];
20423   __I  uint32_t EAR5;                              /**< ERM Memory 5 Error Address Register, offset: 0x150 */
20424   __I  uint32_t SYN5;                              /**< ERM Memory 5 Syndrome Register, offset: 0x154 */
20425   __IO uint32_t CORR_ERR_CNT5;                     /**< ERM Memory 5 Correctable Error Count Register, offset: 0x158 */
20426        uint8_t RESERVED_7[4];
20427   __I  uint32_t EAR6;                              /**< ERM Memory 6 Error Address Register, offset: 0x160 */
20428   __I  uint32_t SYN6;                              /**< ERM Memory 6 Syndrome Register, offset: 0x164 */
20429   __IO uint32_t CORR_ERR_CNT6;                     /**< ERM Memory 6 Correctable Error Count Register, offset: 0x168 */
20430        uint8_t RESERVED_8[12];
20431   __IO uint32_t CORR_ERR_CNT7;                     /**< ERM Memory 7 Correctable Error Count Register, offset: 0x178 */
20432        uint8_t RESERVED_9[8];
20433   __I  uint32_t SYN8;                              /**< ERM Memory 8 Syndrome Register, offset: 0x184 */
20434   __IO uint32_t CORR_ERR_CNT8;                     /**< ERM Memory 8 Correctable Error Count Register, offset: 0x188 */
20435        uint8_t RESERVED_10[12];
20436   __IO uint32_t CORR_ERR_CNT9;                     /**< ERM Memory 9 Correctable Error Count Register, offset: 0x198 */
20437 } ERM_Type;
20438 
20439 /* ----------------------------------------------------------------------------
20440    -- ERM Register Masks
20441    ---------------------------------------------------------------------------- */
20442 
20443 /*!
20444  * @addtogroup ERM_Register_Masks ERM Register Masks
20445  * @{
20446  */
20447 
20448 /*! @name CR0 - ERM Configuration Register 0 */
20449 /*! @{ */
20450 
20451 #define ERM_CR0_ENCIE7_MASK                      (0x4U)
20452 #define ERM_CR0_ENCIE7_SHIFT                     (2U)
20453 /*! ENCIE7 - ENCIE7
20454  *  0b0..Interrupt notification of Memory 7 non-correctable error events is disabled.
20455  *  0b1..Interrupt notification of Memory 7 non-correctable error events is enabled.
20456  */
20457 #define ERM_CR0_ENCIE7(x)                        (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ENCIE7_SHIFT)) & ERM_CR0_ENCIE7_MASK)
20458 
20459 #define ERM_CR0_ESCIE7_MASK                      (0x8U)
20460 #define ERM_CR0_ESCIE7_SHIFT                     (3U)
20461 /*! ESCIE7 - ESCIE7
20462  *  0b0..Interrupt notification of Memory 7 single-bit correction events is disabled.
20463  *  0b1..Interrupt notification of Memory 7 single-bit correction events is enabled.
20464  */
20465 #define ERM_CR0_ESCIE7(x)                        (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ESCIE7_SHIFT)) & ERM_CR0_ESCIE7_MASK)
20466 
20467 #define ERM_CR0_ENCIE6_MASK                      (0x40U)
20468 #define ERM_CR0_ENCIE6_SHIFT                     (6U)
20469 /*! ENCIE6 - ENCIE6
20470  *  0b0..Interrupt notification of Memory 6 non-correctable error events is disabled.
20471  *  0b1..Interrupt notification of Memory 6 non-correctable error events is enabled.
20472  */
20473 #define ERM_CR0_ENCIE6(x)                        (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ENCIE6_SHIFT)) & ERM_CR0_ENCIE6_MASK)
20474 
20475 #define ERM_CR0_ESCIE6_MASK                      (0x80U)
20476 #define ERM_CR0_ESCIE6_SHIFT                     (7U)
20477 /*! ESCIE6 - ESCIE6
20478  *  0b0..Interrupt notification of Memory 6 single-bit correction events is disabled.
20479  *  0b1..Interrupt notification of Memory 6 single-bit correction events is enabled.
20480  */
20481 #define ERM_CR0_ESCIE6(x)                        (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ESCIE6_SHIFT)) & ERM_CR0_ESCIE6_MASK)
20482 
20483 #define ERM_CR0_ENCIE5_MASK                      (0x400U)
20484 #define ERM_CR0_ENCIE5_SHIFT                     (10U)
20485 /*! ENCIE5 - ENCIE5
20486  *  0b0..Interrupt notification of Memory 5 non-correctable error events is disabled.
20487  *  0b1..Interrupt notification of Memory 5 non-correctable error events is enabled.
20488  */
20489 #define ERM_CR0_ENCIE5(x)                        (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ENCIE5_SHIFT)) & ERM_CR0_ENCIE5_MASK)
20490 
20491 #define ERM_CR0_ESCIE5_MASK                      (0x800U)
20492 #define ERM_CR0_ESCIE5_SHIFT                     (11U)
20493 /*! ESCIE5 - ESCIE5
20494  *  0b0..Interrupt notification of Memory 5 single-bit correction events is disabled.
20495  *  0b1..Interrupt notification of Memory 5 single-bit correction events is enabled.
20496  */
20497 #define ERM_CR0_ESCIE5(x)                        (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ESCIE5_SHIFT)) & ERM_CR0_ESCIE5_MASK)
20498 
20499 #define ERM_CR0_ENCIE4_MASK                      (0x4000U)
20500 #define ERM_CR0_ENCIE4_SHIFT                     (14U)
20501 /*! ENCIE4 - ENCIE4
20502  *  0b0..Interrupt notification of Memory 4 non-correctable error events is disabled.
20503  *  0b1..Interrupt notification of Memory 4 non-correctable error events is enabled.
20504  */
20505 #define ERM_CR0_ENCIE4(x)                        (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ENCIE4_SHIFT)) & ERM_CR0_ENCIE4_MASK)
20506 
20507 #define ERM_CR0_ESCIE4_MASK                      (0x8000U)
20508 #define ERM_CR0_ESCIE4_SHIFT                     (15U)
20509 /*! ESCIE4 - ESCIE4
20510  *  0b0..Interrupt notification of Memory 4 single-bit correction events is disabled.
20511  *  0b1..Interrupt notification of Memory 4 single-bit correction events is enabled.
20512  */
20513 #define ERM_CR0_ESCIE4(x)                        (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ESCIE4_SHIFT)) & ERM_CR0_ESCIE4_MASK)
20514 
20515 #define ERM_CR0_ENCIE3_MASK                      (0x40000U)
20516 #define ERM_CR0_ENCIE3_SHIFT                     (18U)
20517 /*! ENCIE3 - ENCIE3
20518  *  0b0..Interrupt notification of Memory 3 non-correctable error events is disabled.
20519  *  0b1..Interrupt notification of Memory 3 non-correctable error events is enabled.
20520  */
20521 #define ERM_CR0_ENCIE3(x)                        (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ENCIE3_SHIFT)) & ERM_CR0_ENCIE3_MASK)
20522 
20523 #define ERM_CR0_ESCIE3_MASK                      (0x80000U)
20524 #define ERM_CR0_ESCIE3_SHIFT                     (19U)
20525 /*! ESCIE3 - ESCIE3
20526  *  0b0..Interrupt notification of Memory 3 single-bit correction events is disabled.
20527  *  0b1..Interrupt notification of Memory 3 single-bit correction events is enabled.
20528  */
20529 #define ERM_CR0_ESCIE3(x)                        (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ESCIE3_SHIFT)) & ERM_CR0_ESCIE3_MASK)
20530 
20531 #define ERM_CR0_ENCIE2_MASK                      (0x400000U)
20532 #define ERM_CR0_ENCIE2_SHIFT                     (22U)
20533 /*! ENCIE2 - ENCIE2
20534  *  0b0..Interrupt notification of Memory 2 non-correctable error events is disabled.
20535  *  0b1..Interrupt notification of Memory 2 non-correctable error events is enabled.
20536  */
20537 #define ERM_CR0_ENCIE2(x)                        (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ENCIE2_SHIFT)) & ERM_CR0_ENCIE2_MASK)
20538 
20539 #define ERM_CR0_ESCIE2_MASK                      (0x800000U)
20540 #define ERM_CR0_ESCIE2_SHIFT                     (23U)
20541 /*! ESCIE2 - ESCIE2
20542  *  0b0..Interrupt notification of Memory 2 single-bit correction events is disabled.
20543  *  0b1..Interrupt notification of Memory 2 single-bit correction events is enabled.
20544  */
20545 #define ERM_CR0_ESCIE2(x)                        (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ESCIE2_SHIFT)) & ERM_CR0_ESCIE2_MASK)
20546 
20547 #define ERM_CR0_ENCIE1_MASK                      (0x4000000U)
20548 #define ERM_CR0_ENCIE1_SHIFT                     (26U)
20549 /*! ENCIE1 - ENCIE1
20550  *  0b0..Interrupt notification of Memory 1 non-correctable error events is disabled.
20551  *  0b1..Interrupt notification of Memory 1 non-correctable error events is enabled.
20552  */
20553 #define ERM_CR0_ENCIE1(x)                        (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ENCIE1_SHIFT)) & ERM_CR0_ENCIE1_MASK)
20554 
20555 #define ERM_CR0_ESCIE1_MASK                      (0x8000000U)
20556 #define ERM_CR0_ESCIE1_SHIFT                     (27U)
20557 /*! ESCIE1 - ESCIE1
20558  *  0b0..Interrupt notification of Memory 1 single-bit correction events is disabled.
20559  *  0b1..Interrupt notification of Memory 1 single-bit correction events is enabled.
20560  */
20561 #define ERM_CR0_ESCIE1(x)                        (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ESCIE1_SHIFT)) & ERM_CR0_ESCIE1_MASK)
20562 
20563 #define ERM_CR0_ENCIE0_MASK                      (0x40000000U)
20564 #define ERM_CR0_ENCIE0_SHIFT                     (30U)
20565 /*! ENCIE0 - ENCIE0
20566  *  0b0..Interrupt notification of Memory 0 non-correctable error events is disabled.
20567  *  0b1..Interrupt notification of Memory 0 non-correctable error events is enabled.
20568  */
20569 #define ERM_CR0_ENCIE0(x)                        (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ENCIE0_SHIFT)) & ERM_CR0_ENCIE0_MASK)
20570 
20571 #define ERM_CR0_ESCIE0_MASK                      (0x80000000U)
20572 #define ERM_CR0_ESCIE0_SHIFT                     (31U)
20573 /*! ESCIE0 - ESCIE0
20574  *  0b0..Interrupt notification of Memory 0 single-bit correction events is disabled.
20575  *  0b1..Interrupt notification of Memory 0 single-bit correction events is enabled.
20576  */
20577 #define ERM_CR0_ESCIE0(x)                        (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ESCIE0_SHIFT)) & ERM_CR0_ESCIE0_MASK)
20578 /*! @} */
20579 
20580 /*! @name CR1 - ERM Configuration Register 1 */
20581 /*! @{ */
20582 
20583 #define ERM_CR1_ENCIE9_MASK                      (0x4000000U)
20584 #define ERM_CR1_ENCIE9_SHIFT                     (26U)
20585 /*! ENCIE9 - ENCIE9
20586  *  0b0..Interrupt notification of Memory 9 non-correctable error events is disabled.
20587  *  0b1..Interrupt notification of Memory 9 non-correctable error events is enabled.
20588  */
20589 #define ERM_CR1_ENCIE9(x)                        (((uint32_t)(((uint32_t)(x)) << ERM_CR1_ENCIE9_SHIFT)) & ERM_CR1_ENCIE9_MASK)
20590 
20591 #define ERM_CR1_ESCIE9_MASK                      (0x8000000U)
20592 #define ERM_CR1_ESCIE9_SHIFT                     (27U)
20593 /*! ESCIE9 - ESCIE9
20594  *  0b0..Interrupt notification of Memory 9 single-bit correction events is disabled.
20595  *  0b1..Interrupt notification of Memory 9 single-bit correction events is enabled.
20596  */
20597 #define ERM_CR1_ESCIE9(x)                        (((uint32_t)(((uint32_t)(x)) << ERM_CR1_ESCIE9_SHIFT)) & ERM_CR1_ESCIE9_MASK)
20598 
20599 #define ERM_CR1_ENCIE8_MASK                      (0x40000000U)
20600 #define ERM_CR1_ENCIE8_SHIFT                     (30U)
20601 /*! ENCIE8 - ENCIE8
20602  *  0b0..Interrupt notification of Memory 8 non-correctable error events is disabled.
20603  *  0b1..Interrupt notification of Memory 8 non-correctable error events is enabled.
20604  */
20605 #define ERM_CR1_ENCIE8(x)                        (((uint32_t)(((uint32_t)(x)) << ERM_CR1_ENCIE8_SHIFT)) & ERM_CR1_ENCIE8_MASK)
20606 
20607 #define ERM_CR1_ESCIE8_MASK                      (0x80000000U)
20608 #define ERM_CR1_ESCIE8_SHIFT                     (31U)
20609 /*! ESCIE8 - ESCIE8
20610  *  0b0..Interrupt notification of Memory 8 single-bit correction events is disabled.
20611  *  0b1..Interrupt notification of Memory 8 single-bit correction events is enabled.
20612  */
20613 #define ERM_CR1_ESCIE8(x)                        (((uint32_t)(((uint32_t)(x)) << ERM_CR1_ESCIE8_SHIFT)) & ERM_CR1_ESCIE8_MASK)
20614 /*! @} */
20615 
20616 /*! @name SR0 - ERM Status Register 0 */
20617 /*! @{ */
20618 
20619 #define ERM_SR0_NCE7_MASK                        (0x4U)
20620 #define ERM_SR0_NCE7_SHIFT                       (2U)
20621 /*! NCE7 - NCE7
20622  *  0b0..No non-correctable error event on Memory 7 detected.
20623  *  0b1..Non-correctable error event on Memory 7 detected.
20624  */
20625 #define ERM_SR0_NCE7(x)                          (((uint32_t)(((uint32_t)(x)) << ERM_SR0_NCE7_SHIFT)) & ERM_SR0_NCE7_MASK)
20626 
20627 #define ERM_SR0_SBC7_MASK                        (0x8U)
20628 #define ERM_SR0_SBC7_SHIFT                       (3U)
20629 /*! SBC7 - SBC7
20630  *  0b0..No single-bit correction event on Memory 7 detected.
20631  *  0b1..Single-bit correction event on Memory 7 detected.
20632  */
20633 #define ERM_SR0_SBC7(x)                          (((uint32_t)(((uint32_t)(x)) << ERM_SR0_SBC7_SHIFT)) & ERM_SR0_SBC7_MASK)
20634 
20635 #define ERM_SR0_NCE6_MASK                        (0x40U)
20636 #define ERM_SR0_NCE6_SHIFT                       (6U)
20637 /*! NCE6 - NCE6
20638  *  0b0..No non-correctable error event on Memory 6 detected.
20639  *  0b1..Non-correctable error event on Memory 6 detected.
20640  */
20641 #define ERM_SR0_NCE6(x)                          (((uint32_t)(((uint32_t)(x)) << ERM_SR0_NCE6_SHIFT)) & ERM_SR0_NCE6_MASK)
20642 
20643 #define ERM_SR0_SBC6_MASK                        (0x80U)
20644 #define ERM_SR0_SBC6_SHIFT                       (7U)
20645 /*! SBC6 - SBC6
20646  *  0b0..No single-bit correction event on Memory 6 detected.
20647  *  0b1..Single-bit correction event on Memory 6 detected.
20648  */
20649 #define ERM_SR0_SBC6(x)                          (((uint32_t)(((uint32_t)(x)) << ERM_SR0_SBC6_SHIFT)) & ERM_SR0_SBC6_MASK)
20650 
20651 #define ERM_SR0_NCE5_MASK                        (0x400U)
20652 #define ERM_SR0_NCE5_SHIFT                       (10U)
20653 /*! NCE5 - NCE5
20654  *  0b0..No non-correctable error event on Memory 5 detected.
20655  *  0b1..Non-correctable error event on Memory 5 detected.
20656  */
20657 #define ERM_SR0_NCE5(x)                          (((uint32_t)(((uint32_t)(x)) << ERM_SR0_NCE5_SHIFT)) & ERM_SR0_NCE5_MASK)
20658 
20659 #define ERM_SR0_SBC5_MASK                        (0x800U)
20660 #define ERM_SR0_SBC5_SHIFT                       (11U)
20661 /*! SBC5 - SBC5
20662  *  0b0..No single-bit correction event on Memory 5 detected.
20663  *  0b1..Single-bit correction event on Memory 5 detected.
20664  */
20665 #define ERM_SR0_SBC5(x)                          (((uint32_t)(((uint32_t)(x)) << ERM_SR0_SBC5_SHIFT)) & ERM_SR0_SBC5_MASK)
20666 
20667 #define ERM_SR0_NCE4_MASK                        (0x4000U)
20668 #define ERM_SR0_NCE4_SHIFT                       (14U)
20669 /*! NCE4 - NCE4
20670  *  0b0..No non-correctable error event on Memory 4 detected.
20671  *  0b1..Non-correctable error event on Memory 4 detected.
20672  */
20673 #define ERM_SR0_NCE4(x)                          (((uint32_t)(((uint32_t)(x)) << ERM_SR0_NCE4_SHIFT)) & ERM_SR0_NCE4_MASK)
20674 
20675 #define ERM_SR0_SBC4_MASK                        (0x8000U)
20676 #define ERM_SR0_SBC4_SHIFT                       (15U)
20677 /*! SBC4 - SBC4
20678  *  0b0..No single-bit correction event on Memory 4 detected.
20679  *  0b1..Single-bit correction event on Memory 4 detected.
20680  */
20681 #define ERM_SR0_SBC4(x)                          (((uint32_t)(((uint32_t)(x)) << ERM_SR0_SBC4_SHIFT)) & ERM_SR0_SBC4_MASK)
20682 
20683 #define ERM_SR0_NCE3_MASK                        (0x40000U)
20684 #define ERM_SR0_NCE3_SHIFT                       (18U)
20685 /*! NCE3 - NCE3
20686  *  0b0..No non-correctable error event on Memory 3 detected.
20687  *  0b1..Non-correctable error event on Memory 3 detected.
20688  */
20689 #define ERM_SR0_NCE3(x)                          (((uint32_t)(((uint32_t)(x)) << ERM_SR0_NCE3_SHIFT)) & ERM_SR0_NCE3_MASK)
20690 
20691 #define ERM_SR0_SBC3_MASK                        (0x80000U)
20692 #define ERM_SR0_SBC3_SHIFT                       (19U)
20693 /*! SBC3 - SBC3
20694  *  0b0..No single-bit correction event on Memory 3 detected.
20695  *  0b1..Single-bit correction event on Memory 3 detected.
20696  */
20697 #define ERM_SR0_SBC3(x)                          (((uint32_t)(((uint32_t)(x)) << ERM_SR0_SBC3_SHIFT)) & ERM_SR0_SBC3_MASK)
20698 
20699 #define ERM_SR0_NCE2_MASK                        (0x400000U)
20700 #define ERM_SR0_NCE2_SHIFT                       (22U)
20701 /*! NCE2 - NCE2
20702  *  0b0..No non-correctable error event on Memory 2 detected.
20703  *  0b1..Non-correctable error event on Memory 2 detected.
20704  */
20705 #define ERM_SR0_NCE2(x)                          (((uint32_t)(((uint32_t)(x)) << ERM_SR0_NCE2_SHIFT)) & ERM_SR0_NCE2_MASK)
20706 
20707 #define ERM_SR0_SBC2_MASK                        (0x800000U)
20708 #define ERM_SR0_SBC2_SHIFT                       (23U)
20709 /*! SBC2 - SBC2
20710  *  0b0..No single-bit correction event on Memory 2 detected.
20711  *  0b1..Single-bit correction event on Memory 2 detected.
20712  */
20713 #define ERM_SR0_SBC2(x)                          (((uint32_t)(((uint32_t)(x)) << ERM_SR0_SBC2_SHIFT)) & ERM_SR0_SBC2_MASK)
20714 
20715 #define ERM_SR0_NCE1_MASK                        (0x4000000U)
20716 #define ERM_SR0_NCE1_SHIFT                       (26U)
20717 /*! NCE1 - NCE1
20718  *  0b0..No non-correctable error event on Memory 1 detected.
20719  *  0b1..Non-correctable error event on Memory 1 detected.
20720  */
20721 #define ERM_SR0_NCE1(x)                          (((uint32_t)(((uint32_t)(x)) << ERM_SR0_NCE1_SHIFT)) & ERM_SR0_NCE1_MASK)
20722 
20723 #define ERM_SR0_SBC1_MASK                        (0x8000000U)
20724 #define ERM_SR0_SBC1_SHIFT                       (27U)
20725 /*! SBC1 - SBC1
20726  *  0b0..No single-bit correction event on Memory 1 detected.
20727  *  0b1..Single-bit correction event on Memory 1 detected.
20728  */
20729 #define ERM_SR0_SBC1(x)                          (((uint32_t)(((uint32_t)(x)) << ERM_SR0_SBC1_SHIFT)) & ERM_SR0_SBC1_MASK)
20730 
20731 #define ERM_SR0_NCE0_MASK                        (0x40000000U)
20732 #define ERM_SR0_NCE0_SHIFT                       (30U)
20733 /*! NCE0 - NCE0
20734  *  0b0..No non-correctable error event on Memory 0 detected.
20735  *  0b1..Non-correctable error event on Memory 0 detected.
20736  */
20737 #define ERM_SR0_NCE0(x)                          (((uint32_t)(((uint32_t)(x)) << ERM_SR0_NCE0_SHIFT)) & ERM_SR0_NCE0_MASK)
20738 
20739 #define ERM_SR0_SBC0_MASK                        (0x80000000U)
20740 #define ERM_SR0_SBC0_SHIFT                       (31U)
20741 /*! SBC0 - SBC0
20742  *  0b0..No single-bit correction event on Memory 0 detected.
20743  *  0b1..Single-bit correction event on Memory 0 detected.
20744  */
20745 #define ERM_SR0_SBC0(x)                          (((uint32_t)(((uint32_t)(x)) << ERM_SR0_SBC0_SHIFT)) & ERM_SR0_SBC0_MASK)
20746 /*! @} */
20747 
20748 /*! @name SR1 - ERM Status Register 1 */
20749 /*! @{ */
20750 
20751 #define ERM_SR1_NCE9_MASK                        (0x4000000U)
20752 #define ERM_SR1_NCE9_SHIFT                       (26U)
20753 /*! NCE9 - NCE9
20754  *  0b0..No non-correctable error event on Memory 9 detected.
20755  *  0b1..Non-correctable error event on Memory 9 detected.
20756  */
20757 #define ERM_SR1_NCE9(x)                          (((uint32_t)(((uint32_t)(x)) << ERM_SR1_NCE9_SHIFT)) & ERM_SR1_NCE9_MASK)
20758 
20759 #define ERM_SR1_SBC9_MASK                        (0x8000000U)
20760 #define ERM_SR1_SBC9_SHIFT                       (27U)
20761 /*! SBC9 - SBC9
20762  *  0b0..No single-bit correction event on Memory 9 detected.
20763  *  0b1..Single-bit correction event on Memory 9 detected.
20764  */
20765 #define ERM_SR1_SBC9(x)                          (((uint32_t)(((uint32_t)(x)) << ERM_SR1_SBC9_SHIFT)) & ERM_SR1_SBC9_MASK)
20766 
20767 #define ERM_SR1_NCE8_MASK                        (0x40000000U)
20768 #define ERM_SR1_NCE8_SHIFT                       (30U)
20769 /*! NCE8 - NCE8
20770  *  0b0..No non-correctable error event on Memory 8 detected.
20771  *  0b1..Non-correctable error event on Memory 8 detected.
20772  */
20773 #define ERM_SR1_NCE8(x)                          (((uint32_t)(((uint32_t)(x)) << ERM_SR1_NCE8_SHIFT)) & ERM_SR1_NCE8_MASK)
20774 
20775 #define ERM_SR1_SBC8_MASK                        (0x80000000U)
20776 #define ERM_SR1_SBC8_SHIFT                       (31U)
20777 /*! SBC8 - SBC8
20778  *  0b0..No single-bit correction event on Memory 8 detected.
20779  *  0b1..Single-bit correction event on Memory 8 detected.
20780  */
20781 #define ERM_SR1_SBC8(x)                          (((uint32_t)(((uint32_t)(x)) << ERM_SR1_SBC8_SHIFT)) & ERM_SR1_SBC8_MASK)
20782 /*! @} */
20783 
20784 /*! @name EAR0 - ERM Memory 0 Error Address Register */
20785 /*! @{ */
20786 
20787 #define ERM_EAR0_EAR_MASK                        (0xFFFFFFFFU)
20788 #define ERM_EAR0_EAR_SHIFT                       (0U)
20789 /*! EAR - EAR */
20790 #define ERM_EAR0_EAR(x)                          (((uint32_t)(((uint32_t)(x)) << ERM_EAR0_EAR_SHIFT)) & ERM_EAR0_EAR_MASK)
20791 /*! @} */
20792 
20793 /*! @name SYN0 - ERM Memory 0 Syndrome Register */
20794 /*! @{ */
20795 
20796 #define ERM_SYN0_SYNDROME_MASK                   (0xFF000000U)
20797 #define ERM_SYN0_SYNDROME_SHIFT                  (24U)
20798 /*! SYNDROME - SYNDROME */
20799 #define ERM_SYN0_SYNDROME(x)                     (((uint32_t)(((uint32_t)(x)) << ERM_SYN0_SYNDROME_SHIFT)) & ERM_SYN0_SYNDROME_MASK)
20800 /*! @} */
20801 
20802 /*! @name CORR_ERR_CNT0 - ERM Memory 0 Correctable Error Count Register */
20803 /*! @{ */
20804 
20805 #define ERM_CORR_ERR_CNT0_COUNT_MASK             (0xFFU)
20806 #define ERM_CORR_ERR_CNT0_COUNT_SHIFT            (0U)
20807 /*! COUNT - Memory n Correctable Error Count */
20808 #define ERM_CORR_ERR_CNT0_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT0_COUNT_SHIFT)) & ERM_CORR_ERR_CNT0_COUNT_MASK)
20809 /*! @} */
20810 
20811 /*! @name EAR1 - ERM Memory 1 Error Address Register */
20812 /*! @{ */
20813 
20814 #define ERM_EAR1_EAR_MASK                        (0xFFFFFFFFU)
20815 #define ERM_EAR1_EAR_SHIFT                       (0U)
20816 /*! EAR - EAR */
20817 #define ERM_EAR1_EAR(x)                          (((uint32_t)(((uint32_t)(x)) << ERM_EAR1_EAR_SHIFT)) & ERM_EAR1_EAR_MASK)
20818 /*! @} */
20819 
20820 /*! @name SYN1 - ERM Memory 1 Syndrome Register */
20821 /*! @{ */
20822 
20823 #define ERM_SYN1_SYNDROME_MASK                   (0xFF000000U)
20824 #define ERM_SYN1_SYNDROME_SHIFT                  (24U)
20825 /*! SYNDROME - SYNDROME */
20826 #define ERM_SYN1_SYNDROME(x)                     (((uint32_t)(((uint32_t)(x)) << ERM_SYN1_SYNDROME_SHIFT)) & ERM_SYN1_SYNDROME_MASK)
20827 /*! @} */
20828 
20829 /*! @name CORR_ERR_CNT1 - ERM Memory 1 Correctable Error Count Register */
20830 /*! @{ */
20831 
20832 #define ERM_CORR_ERR_CNT1_COUNT_MASK             (0xFFU)
20833 #define ERM_CORR_ERR_CNT1_COUNT_SHIFT            (0U)
20834 /*! COUNT - Memory n Correctable Error Count */
20835 #define ERM_CORR_ERR_CNT1_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT1_COUNT_SHIFT)) & ERM_CORR_ERR_CNT1_COUNT_MASK)
20836 /*! @} */
20837 
20838 /*! @name EAR2 - ERM Memory 2 Error Address Register */
20839 /*! @{ */
20840 
20841 #define ERM_EAR2_EAR_MASK                        (0xFFFFFFFFU)
20842 #define ERM_EAR2_EAR_SHIFT                       (0U)
20843 /*! EAR - EAR */
20844 #define ERM_EAR2_EAR(x)                          (((uint32_t)(((uint32_t)(x)) << ERM_EAR2_EAR_SHIFT)) & ERM_EAR2_EAR_MASK)
20845 /*! @} */
20846 
20847 /*! @name SYN2 - ERM Memory 2 Syndrome Register */
20848 /*! @{ */
20849 
20850 #define ERM_SYN2_SYNDROME_MASK                   (0xFF000000U)
20851 #define ERM_SYN2_SYNDROME_SHIFT                  (24U)
20852 /*! SYNDROME - SYNDROME */
20853 #define ERM_SYN2_SYNDROME(x)                     (((uint32_t)(((uint32_t)(x)) << ERM_SYN2_SYNDROME_SHIFT)) & ERM_SYN2_SYNDROME_MASK)
20854 /*! @} */
20855 
20856 /*! @name CORR_ERR_CNT2 - ERM Memory 2 Correctable Error Count Register */
20857 /*! @{ */
20858 
20859 #define ERM_CORR_ERR_CNT2_COUNT_MASK             (0xFFU)
20860 #define ERM_CORR_ERR_CNT2_COUNT_SHIFT            (0U)
20861 /*! COUNT - Memory n Correctable Error Count */
20862 #define ERM_CORR_ERR_CNT2_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT2_COUNT_SHIFT)) & ERM_CORR_ERR_CNT2_COUNT_MASK)
20863 /*! @} */
20864 
20865 /*! @name EAR3 - ERM Memory 3 Error Address Register */
20866 /*! @{ */
20867 
20868 #define ERM_EAR3_EAR_MASK                        (0xFFFFFFFFU)
20869 #define ERM_EAR3_EAR_SHIFT                       (0U)
20870 /*! EAR - EAR */
20871 #define ERM_EAR3_EAR(x)                          (((uint32_t)(((uint32_t)(x)) << ERM_EAR3_EAR_SHIFT)) & ERM_EAR3_EAR_MASK)
20872 /*! @} */
20873 
20874 /*! @name SYN3 - ERM Memory 3 Syndrome Register */
20875 /*! @{ */
20876 
20877 #define ERM_SYN3_SYNDROME_MASK                   (0xFF000000U)
20878 #define ERM_SYN3_SYNDROME_SHIFT                  (24U)
20879 /*! SYNDROME - SYNDROME */
20880 #define ERM_SYN3_SYNDROME(x)                     (((uint32_t)(((uint32_t)(x)) << ERM_SYN3_SYNDROME_SHIFT)) & ERM_SYN3_SYNDROME_MASK)
20881 /*! @} */
20882 
20883 /*! @name CORR_ERR_CNT3 - ERM Memory 3 Correctable Error Count Register */
20884 /*! @{ */
20885 
20886 #define ERM_CORR_ERR_CNT3_COUNT_MASK             (0xFFU)
20887 #define ERM_CORR_ERR_CNT3_COUNT_SHIFT            (0U)
20888 /*! COUNT - Memory n Correctable Error Count */
20889 #define ERM_CORR_ERR_CNT3_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT3_COUNT_SHIFT)) & ERM_CORR_ERR_CNT3_COUNT_MASK)
20890 /*! @} */
20891 
20892 /*! @name EAR4 - ERM Memory 4 Error Address Register */
20893 /*! @{ */
20894 
20895 #define ERM_EAR4_EAR_MASK                        (0xFFFFFFFFU)
20896 #define ERM_EAR4_EAR_SHIFT                       (0U)
20897 /*! EAR - EAR */
20898 #define ERM_EAR4_EAR(x)                          (((uint32_t)(((uint32_t)(x)) << ERM_EAR4_EAR_SHIFT)) & ERM_EAR4_EAR_MASK)
20899 /*! @} */
20900 
20901 /*! @name SYN4 - ERM Memory 4 Syndrome Register */
20902 /*! @{ */
20903 
20904 #define ERM_SYN4_SYNDROME_MASK                   (0xFF000000U)
20905 #define ERM_SYN4_SYNDROME_SHIFT                  (24U)
20906 /*! SYNDROME - SYNDROME */
20907 #define ERM_SYN4_SYNDROME(x)                     (((uint32_t)(((uint32_t)(x)) << ERM_SYN4_SYNDROME_SHIFT)) & ERM_SYN4_SYNDROME_MASK)
20908 /*! @} */
20909 
20910 /*! @name CORR_ERR_CNT4 - ERM Memory 4 Correctable Error Count Register */
20911 /*! @{ */
20912 
20913 #define ERM_CORR_ERR_CNT4_COUNT_MASK             (0xFFU)
20914 #define ERM_CORR_ERR_CNT4_COUNT_SHIFT            (0U)
20915 /*! COUNT - Memory n Correctable Error Count */
20916 #define ERM_CORR_ERR_CNT4_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT4_COUNT_SHIFT)) & ERM_CORR_ERR_CNT4_COUNT_MASK)
20917 /*! @} */
20918 
20919 /*! @name EAR5 - ERM Memory 5 Error Address Register */
20920 /*! @{ */
20921 
20922 #define ERM_EAR5_EAR_MASK                        (0xFFFFFFFFU)
20923 #define ERM_EAR5_EAR_SHIFT                       (0U)
20924 /*! EAR - EAR */
20925 #define ERM_EAR5_EAR(x)                          (((uint32_t)(((uint32_t)(x)) << ERM_EAR5_EAR_SHIFT)) & ERM_EAR5_EAR_MASK)
20926 /*! @} */
20927 
20928 /*! @name SYN5 - ERM Memory 5 Syndrome Register */
20929 /*! @{ */
20930 
20931 #define ERM_SYN5_SYNDROME_MASK                   (0xFF000000U)
20932 #define ERM_SYN5_SYNDROME_SHIFT                  (24U)
20933 /*! SYNDROME - SYNDROME */
20934 #define ERM_SYN5_SYNDROME(x)                     (((uint32_t)(((uint32_t)(x)) << ERM_SYN5_SYNDROME_SHIFT)) & ERM_SYN5_SYNDROME_MASK)
20935 /*! @} */
20936 
20937 /*! @name CORR_ERR_CNT5 - ERM Memory 5 Correctable Error Count Register */
20938 /*! @{ */
20939 
20940 #define ERM_CORR_ERR_CNT5_COUNT_MASK             (0xFFU)
20941 #define ERM_CORR_ERR_CNT5_COUNT_SHIFT            (0U)
20942 /*! COUNT - Memory n Correctable Error Count */
20943 #define ERM_CORR_ERR_CNT5_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT5_COUNT_SHIFT)) & ERM_CORR_ERR_CNT5_COUNT_MASK)
20944 /*! @} */
20945 
20946 /*! @name EAR6 - ERM Memory 6 Error Address Register */
20947 /*! @{ */
20948 
20949 #define ERM_EAR6_EAR_MASK                        (0xFFFFFFFFU)
20950 #define ERM_EAR6_EAR_SHIFT                       (0U)
20951 /*! EAR - EAR */
20952 #define ERM_EAR6_EAR(x)                          (((uint32_t)(((uint32_t)(x)) << ERM_EAR6_EAR_SHIFT)) & ERM_EAR6_EAR_MASK)
20953 /*! @} */
20954 
20955 /*! @name SYN6 - ERM Memory 6 Syndrome Register */
20956 /*! @{ */
20957 
20958 #define ERM_SYN6_SYNDROME_MASK                   (0xFF000000U)
20959 #define ERM_SYN6_SYNDROME_SHIFT                  (24U)
20960 /*! SYNDROME - SYNDROME */
20961 #define ERM_SYN6_SYNDROME(x)                     (((uint32_t)(((uint32_t)(x)) << ERM_SYN6_SYNDROME_SHIFT)) & ERM_SYN6_SYNDROME_MASK)
20962 /*! @} */
20963 
20964 /*! @name CORR_ERR_CNT6 - ERM Memory 6 Correctable Error Count Register */
20965 /*! @{ */
20966 
20967 #define ERM_CORR_ERR_CNT6_COUNT_MASK             (0xFFU)
20968 #define ERM_CORR_ERR_CNT6_COUNT_SHIFT            (0U)
20969 /*! COUNT - Memory n Correctable Error Count */
20970 #define ERM_CORR_ERR_CNT6_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT6_COUNT_SHIFT)) & ERM_CORR_ERR_CNT6_COUNT_MASK)
20971 /*! @} */
20972 
20973 /*! @name CORR_ERR_CNT7 - ERM Memory 7 Correctable Error Count Register */
20974 /*! @{ */
20975 
20976 #define ERM_CORR_ERR_CNT7_COUNT_MASK             (0xFFU)
20977 #define ERM_CORR_ERR_CNT7_COUNT_SHIFT            (0U)
20978 /*! COUNT - Memory n Correctable Error Count */
20979 #define ERM_CORR_ERR_CNT7_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT7_COUNT_SHIFT)) & ERM_CORR_ERR_CNT7_COUNT_MASK)
20980 /*! @} */
20981 
20982 /*! @name SYN8 - ERM Memory 8 Syndrome Register */
20983 /*! @{ */
20984 
20985 #define ERM_SYN8_SYNDROME_MASK                   (0xFF000000U)
20986 #define ERM_SYN8_SYNDROME_SHIFT                  (24U)
20987 /*! SYNDROME - SYNDROME */
20988 #define ERM_SYN8_SYNDROME(x)                     (((uint32_t)(((uint32_t)(x)) << ERM_SYN8_SYNDROME_SHIFT)) & ERM_SYN8_SYNDROME_MASK)
20989 /*! @} */
20990 
20991 /*! @name CORR_ERR_CNT8 - ERM Memory 8 Correctable Error Count Register */
20992 /*! @{ */
20993 
20994 #define ERM_CORR_ERR_CNT8_COUNT_MASK             (0xFFU)
20995 #define ERM_CORR_ERR_CNT8_COUNT_SHIFT            (0U)
20996 /*! COUNT - Memory n Correctable Error Count */
20997 #define ERM_CORR_ERR_CNT8_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT8_COUNT_SHIFT)) & ERM_CORR_ERR_CNT8_COUNT_MASK)
20998 /*! @} */
20999 
21000 /*! @name CORR_ERR_CNT9 - ERM Memory 9 Correctable Error Count Register */
21001 /*! @{ */
21002 
21003 #define ERM_CORR_ERR_CNT9_COUNT_MASK             (0xFFU)
21004 #define ERM_CORR_ERR_CNT9_COUNT_SHIFT            (0U)
21005 /*! COUNT - Memory n Correctable Error Count */
21006 #define ERM_CORR_ERR_CNT9_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT9_COUNT_SHIFT)) & ERM_CORR_ERR_CNT9_COUNT_MASK)
21007 /*! @} */
21008 
21009 
21010 /*!
21011  * @}
21012  */ /* end of group ERM_Register_Masks */
21013 
21014 
21015 /* ERM - Peripheral instance base addresses */
21016 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
21017   /** Peripheral ERM0 base address */
21018   #define ERM0_BASE                                (0x5005C000u)
21019   /** Peripheral ERM0 base address */
21020   #define ERM0_BASE_NS                             (0x4005C000u)
21021   /** Peripheral ERM0 base pointer */
21022   #define ERM0                                     ((ERM_Type *)ERM0_BASE)
21023   /** Peripheral ERM0 base pointer */
21024   #define ERM0_NS                                  ((ERM_Type *)ERM0_BASE_NS)
21025   /** Array initializer of ERM peripheral base addresses */
21026   #define ERM_BASE_ADDRS                           { ERM0_BASE }
21027   /** Array initializer of ERM peripheral base pointers */
21028   #define ERM_BASE_PTRS                            { ERM0 }
21029   /** Array initializer of ERM peripheral base addresses */
21030   #define ERM_BASE_ADDRS_NS                        { ERM0_BASE_NS }
21031   /** Array initializer of ERM peripheral base pointers */
21032   #define ERM_BASE_PTRS_NS                         { ERM0_NS }
21033 #else
21034   /** Peripheral ERM0 base address */
21035   #define ERM0_BASE                                (0x4005C000u)
21036   /** Peripheral ERM0 base pointer */
21037   #define ERM0                                     ((ERM_Type *)ERM0_BASE)
21038   /** Array initializer of ERM peripheral base addresses */
21039   #define ERM_BASE_ADDRS                           { ERM0_BASE }
21040   /** Array initializer of ERM peripheral base pointers */
21041   #define ERM_BASE_PTRS                            { ERM0 }
21042 #endif
21043 
21044 /*!
21045  * @}
21046  */ /* end of group ERM_Peripheral_Access_Layer */
21047 
21048 
21049 /* ----------------------------------------------------------------------------
21050    -- EVTG Peripheral Access Layer
21051    ---------------------------------------------------------------------------- */
21052 
21053 /*!
21054  * @addtogroup EVTG_Peripheral_Access_Layer EVTG Peripheral Access Layer
21055  * @{
21056  */
21057 
21058 /** EVTG - Register Layout Typedef */
21059 typedef struct {
21060   struct {                                         /* offset: 0x0, array step: 0x10 */
21061     __IO uint16_t EVTG_AOI0_BFT01;                   /**< AOI0 Boolean Function Term 0 and 1 Configuration, array offset: 0x0, array step: 0x10 */
21062     __IO uint16_t EVTG_AOI0_BFT23;                   /**< AOI0 Boolean Function Term 2 and 3 Configuration, array offset: 0x2, array step: 0x10 */
21063     __IO uint16_t EVTG_AOI1_BFT01;                   /**< AOI1 Boolean Function Term 0 and 1 Configuration, array offset: 0x4, array step: 0x10 */
21064     __IO uint16_t EVTG_AOI1_BFT23;                   /**< AOI1 Boolean Function Term 2 and 3 Configuration, array offset: 0x6, array step: 0x10 */
21065          uint8_t RESERVED_0[2];
21066     __IO uint16_t EVTG_CTRL;                         /**< Control and Status, array offset: 0xA, array step: 0x10 */
21067     __IO uint16_t EVTG_AOI0_FILT;                    /**< AOI0 Output Filter, array offset: 0xC, array step: 0x10 */
21068     __IO uint16_t EVTG_AOI1_FILT;                    /**< AOI1 Output Filter, array offset: 0xE, array step: 0x10 */
21069   } EVTG_INST[4];
21070 } EVTG_Type;
21071 
21072 /* ----------------------------------------------------------------------------
21073    -- EVTG Register Masks
21074    ---------------------------------------------------------------------------- */
21075 
21076 /*!
21077  * @addtogroup EVTG_Register_Masks EVTG Register Masks
21078  * @{
21079  */
21080 
21081 /*! @name EVTG_INST_EVTG_AOI0_BFT01 - AOI0 Boolean Function Term 0 and 1 Configuration */
21082 /*! @{ */
21083 
21084 #define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_DC_MASK (0x3U)
21085 #define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_DC_SHIFT (0U)
21086 /*! PT1_DC - Product Term 1, D Input Configuration
21087  *  0b00..Force the D input in this product term to a logical zero
21088  *  0b01..Pass the D input in this product term
21089  *  0b10..Complement the D input in this product term
21090  *  0b11..Force the D input in this product term to a logical one
21091  */
21092 #define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_DC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_DC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_DC_MASK)
21093 
21094 #define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_CC_MASK (0xCU)
21095 #define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_CC_SHIFT (2U)
21096 /*! PT1_CC - Product Term 1, C Input Configuration
21097  *  0b00..Force the C input in this product term to a logical zero
21098  *  0b01..Pass the C input in this product term
21099  *  0b10..Complement the C input in this product term
21100  *  0b11..Force the C input in this product term to a logical one
21101  */
21102 #define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_CC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_CC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_CC_MASK)
21103 
21104 #define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_BC_MASK (0x30U)
21105 #define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_BC_SHIFT (4U)
21106 /*! PT1_BC - Product Term 1, B Input Configuration
21107  *  0b00..Force the B input in this product term to a logical zero
21108  *  0b01..Pass the B input in this product term
21109  *  0b10..Complement the B input in this product term
21110  *  0b11..Force the B input in this product term to a logical one
21111  */
21112 #define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_BC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_BC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_BC_MASK)
21113 
21114 #define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_AC_MASK (0xC0U)
21115 #define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_AC_SHIFT (6U)
21116 /*! PT1_AC - Product Term 1, A Input Configuration
21117  *  0b00..Force the A input in this product term to a logical zero
21118  *  0b01..Pass the A input in this product term
21119  *  0b10..Complement the A input in this product term
21120  *  0b11..Force the A input in this product term to a logical one
21121  */
21122 #define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_AC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_AC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_AC_MASK)
21123 
21124 #define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_DC_MASK (0x300U)
21125 #define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_DC_SHIFT (8U)
21126 /*! PT0_DC - Product Term 0, D Input Configuration
21127  *  0b00..Force the D input in this product term to a logical zero
21128  *  0b01..Pass the D input in this product term
21129  *  0b10..Complement the D input in this product term
21130  *  0b11..Force the D input in this product term to a logical one
21131  */
21132 #define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_DC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_DC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_DC_MASK)
21133 
21134 #define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_CC_MASK (0xC00U)
21135 #define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_CC_SHIFT (10U)
21136 /*! PT0_CC - Product Term 0, C Input Configuration
21137  *  0b00..Force the C input in this product term to a logical zero
21138  *  0b01..Pass the C input in this product term
21139  *  0b10..Complement the C input in this product term
21140  *  0b11..Force the C input in this product term to a logical one
21141  */
21142 #define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_CC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_CC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_CC_MASK)
21143 
21144 #define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_BC_MASK (0x3000U)
21145 #define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_BC_SHIFT (12U)
21146 /*! PT0_BC - Product Term 0, B Input Configuration
21147  *  0b00..Force the B input in this product term to a logical zero
21148  *  0b01..Pass the B input in this product term
21149  *  0b10..Complement the B input in this product term
21150  *  0b11..Force the B input in this product term to a logical one
21151  */
21152 #define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_BC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_BC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_BC_MASK)
21153 
21154 #define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_AC_MASK (0xC000U)
21155 #define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_AC_SHIFT (14U)
21156 /*! PT0_AC - Product Term 0, A Input Configuration
21157  *  0b00..Force the A input in this product term to a logical zero
21158  *  0b01..Pass the A input in this product term
21159  *  0b10..Complement the A input in this product term
21160  *  0b11..Force the A input in this product term to a logical one
21161  */
21162 #define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_AC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_AC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_AC_MASK)
21163 /*! @} */
21164 
21165 /* The count of EVTG_EVTG_INST_EVTG_AOI0_BFT01 */
21166 #define EVTG_EVTG_INST_EVTG_AOI0_BFT01_COUNT     (4U)
21167 
21168 /*! @name EVTG_INST_EVTG_AOI0_BFT23 - AOI0 Boolean Function Term 2 and 3 Configuration */
21169 /*! @{ */
21170 
21171 #define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_DC_MASK (0x3U)
21172 #define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_DC_SHIFT (0U)
21173 /*! PT3_DC - Product Term 3, D Input Configuration
21174  *  0b00..Force the D input in this product term to a logical zero
21175  *  0b01..Pass the D input in this product term
21176  *  0b10..Complement the D input in this product term
21177  *  0b11..Force the D input in this product term to a logical one
21178  */
21179 #define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_DC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_DC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_DC_MASK)
21180 
21181 #define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_CC_MASK (0xCU)
21182 #define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_CC_SHIFT (2U)
21183 /*! PT3_CC - Product Term 3, C Input Configuration
21184  *  0b00..Force the C input in this product term to a logical zero
21185  *  0b01..Pass the C input in this product term
21186  *  0b10..Complement the C input in this product term
21187  *  0b11..Force the C input in this product term to a logical one
21188  */
21189 #define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_CC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_CC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_CC_MASK)
21190 
21191 #define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_BC_MASK (0x30U)
21192 #define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_BC_SHIFT (4U)
21193 /*! PT3_BC - Product Term 3, B Input Configuration
21194  *  0b00..Force the B input in this product term to a logical zero
21195  *  0b01..Pass the B input in this product term
21196  *  0b10..Complement the B input in this product term
21197  *  0b11..Force the B input in this product term to a logical one
21198  */
21199 #define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_BC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_BC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_BC_MASK)
21200 
21201 #define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_AC_MASK (0xC0U)
21202 #define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_AC_SHIFT (6U)
21203 /*! PT3_AC - Product Term 3, A Input Configuration
21204  *  0b00..Force the A input in this product term to a logical zero
21205  *  0b01..Pass the A input in this product term
21206  *  0b10..Complement the A input in this product term
21207  *  0b11..Force the A input in this product term to a logical one
21208  */
21209 #define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_AC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_AC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_AC_MASK)
21210 
21211 #define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_DC_MASK (0x300U)
21212 #define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_DC_SHIFT (8U)
21213 /*! PT2_DC - Product Term 2, D Input Configuration
21214  *  0b00..Force the D input in this product term to a logical zero
21215  *  0b01..Pass the D input in this product term
21216  *  0b10..Complement the D input in this product term
21217  *  0b11..Force the D input in this product term to a logical one
21218  */
21219 #define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_DC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_DC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_DC_MASK)
21220 
21221 #define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_CC_MASK (0xC00U)
21222 #define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_CC_SHIFT (10U)
21223 /*! PT2_CC - Product Term 2, C Input Configuration
21224  *  0b00..Force the C input in this product term to a logical zero
21225  *  0b01..Pass the C input in this product term
21226  *  0b10..Complement the C input in this product term
21227  *  0b11..Force the C input in this product term to a logical one
21228  */
21229 #define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_CC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_CC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_CC_MASK)
21230 
21231 #define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_BC_MASK (0x3000U)
21232 #define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_BC_SHIFT (12U)
21233 /*! PT2_BC - Product Term 2, B Input Configuration
21234  *  0b00..Force the B input in this product term to a logical zero
21235  *  0b01..Pass the B input in this product term
21236  *  0b10..Complement the B input in this product term
21237  *  0b11..Force the B input in this product term to a logical one
21238  */
21239 #define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_BC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_BC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_BC_MASK)
21240 
21241 #define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_AC_MASK (0xC000U)
21242 #define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_AC_SHIFT (14U)
21243 /*! PT2_AC - Product Term 2, A Input Configuration
21244  *  0b00..Force the A input in this product term to a logical zero
21245  *  0b01..Pass the A input in this product term
21246  *  0b10..Complement the A input in this product term
21247  *  0b11..Force the A input in this product term to a logical one
21248  */
21249 #define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_AC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_AC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_AC_MASK)
21250 /*! @} */
21251 
21252 /* The count of EVTG_EVTG_INST_EVTG_AOI0_BFT23 */
21253 #define EVTG_EVTG_INST_EVTG_AOI0_BFT23_COUNT     (4U)
21254 
21255 /*! @name EVTG_INST_EVTG_AOI1_BFT01 - AOI1 Boolean Function Term 0 and 1 Configuration */
21256 /*! @{ */
21257 
21258 #define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_DC_MASK (0x3U)
21259 #define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_DC_SHIFT (0U)
21260 /*! PT1_DC - Product Term 1, D Input Configuration
21261  *  0b00..Force the D input in this product term to a logical zero
21262  *  0b01..Pass the D input in this product term
21263  *  0b10..Complement the D input in this product term
21264  *  0b11..Force the D input in this product term to a logical one
21265  */
21266 #define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_DC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_DC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_DC_MASK)
21267 
21268 #define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_CC_MASK (0xCU)
21269 #define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_CC_SHIFT (2U)
21270 /*! PT1_CC - Product Term 1, C Input Configuration
21271  *  0b00..Force the C input in this product term to a logical zero
21272  *  0b01..Pass the C input in this product term
21273  *  0b10..Complement the C input in this product term
21274  *  0b11..Force the C input in this product term to a logical one
21275  */
21276 #define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_CC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_CC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_CC_MASK)
21277 
21278 #define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_BC_MASK (0x30U)
21279 #define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_BC_SHIFT (4U)
21280 /*! PT1_BC - Product Term 1, B Input Configuration
21281  *  0b00..Force the B input in this product term to a logical zero
21282  *  0b01..Pass the B input in this product term
21283  *  0b10..Complement the B input in this product term
21284  *  0b11..Force the B input in this product term to a logical one
21285  */
21286 #define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_BC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_BC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_BC_MASK)
21287 
21288 #define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_AC_MASK (0xC0U)
21289 #define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_AC_SHIFT (6U)
21290 /*! PT1_AC - Product Term 1, A Input Configuration
21291  *  0b00..Force the A input in this product term to a logical zero
21292  *  0b01..Pass the A input in this product term
21293  *  0b10..Complement the A input in this product term
21294  *  0b11..Force the A input in this product term to a logical one
21295  */
21296 #define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_AC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_AC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_AC_MASK)
21297 
21298 #define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_DC_MASK (0x300U)
21299 #define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_DC_SHIFT (8U)
21300 /*! PT0_DC - Product Term 0, D Input Configuration
21301  *  0b00..Force the D input in this product term to a logical zero
21302  *  0b01..Pass the D input in this product term
21303  *  0b10..Complement the D input in this product term
21304  *  0b11..Force the D input in this product term to a logical one
21305  */
21306 #define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_DC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_DC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_DC_MASK)
21307 
21308 #define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_CC_MASK (0xC00U)
21309 #define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_CC_SHIFT (10U)
21310 /*! PT0_CC - Product Term 0, C Input Configuration
21311  *  0b00..Force the C input in this product term to a logical zero
21312  *  0b01..Pass the C input in this product term
21313  *  0b10..Complement the C input in this product term
21314  *  0b11..Force the C input in this product term to a logical one
21315  */
21316 #define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_CC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_CC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_CC_MASK)
21317 
21318 #define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_BC_MASK (0x3000U)
21319 #define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_BC_SHIFT (12U)
21320 /*! PT0_BC - Product Term 0, B Input Configuration
21321  *  0b00..Force the B input in this product term to a logical zero
21322  *  0b01..Pass the B input in this product term
21323  *  0b10..Complement the B input in this product term
21324  *  0b11..Force the B input in this product term to a logical one
21325  */
21326 #define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_BC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_BC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_BC_MASK)
21327 
21328 #define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_AC_MASK (0xC000U)
21329 #define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_AC_SHIFT (14U)
21330 /*! PT0_AC - Product Term 0, A Input Configuration
21331  *  0b00..Force the A input in this product term to a logical zero
21332  *  0b01..Pass the A input in this product term
21333  *  0b10..Complement the A input in this product term
21334  *  0b11..Force the A input in this product term to a logical one
21335  */
21336 #define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_AC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_AC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_AC_MASK)
21337 /*! @} */
21338 
21339 /* The count of EVTG_EVTG_INST_EVTG_AOI1_BFT01 */
21340 #define EVTG_EVTG_INST_EVTG_AOI1_BFT01_COUNT     (4U)
21341 
21342 /*! @name EVTG_INST_EVTG_AOI1_BFT23 - AOI1 Boolean Function Term 2 and 3 Configuration */
21343 /*! @{ */
21344 
21345 #define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_DC_MASK (0x3U)
21346 #define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_DC_SHIFT (0U)
21347 /*! PT3_DC - Product Term 3, D Input Configuration
21348  *  0b00..Force the D input in this product term to a logical zero
21349  *  0b01..Pass the D input in this product term
21350  *  0b10..Complement the D input in this product term
21351  *  0b11..Force the D input in this product term to a logical one
21352  */
21353 #define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_DC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_DC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_DC_MASK)
21354 
21355 #define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_CC_MASK (0xCU)
21356 #define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_CC_SHIFT (2U)
21357 /*! PT3_CC - Product Term 3, C Input Configuration
21358  *  0b00..Force the C input in this product term to a logical zero
21359  *  0b01..Pass the C input in this product term
21360  *  0b10..Complement the C input in this product term
21361  *  0b11..Force the C input in this product term to a logical one
21362  */
21363 #define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_CC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_CC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_CC_MASK)
21364 
21365 #define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_BC_MASK (0x30U)
21366 #define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_BC_SHIFT (4U)
21367 /*! PT3_BC - Product Term 3, B Input Configuration
21368  *  0b00..Force the B input in this product term to a logical zero
21369  *  0b01..Pass the B input in this product term
21370  *  0b10..Complement the B input in this product term
21371  *  0b11..Force the B input in this product term to a logical one
21372  */
21373 #define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_BC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_BC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_BC_MASK)
21374 
21375 #define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_AC_MASK (0xC0U)
21376 #define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_AC_SHIFT (6U)
21377 /*! PT3_AC - Product Term 3, A Input Configuration
21378  *  0b00..Force the A input in this product term to a logical zero
21379  *  0b01..Pass the A input in this product term
21380  *  0b10..Complement the A input in this product term
21381  *  0b11..Force the A input in this product term to a logical one
21382  */
21383 #define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_AC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_AC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_AC_MASK)
21384 
21385 #define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_DC_MASK (0x300U)
21386 #define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_DC_SHIFT (8U)
21387 /*! PT2_DC - Product Term 2, D Input Configuration
21388  *  0b00..Force the D input in this product term to a logical zero
21389  *  0b01..Pass the D input in this product term
21390  *  0b10..Complement the D input in this product term
21391  *  0b11..Force the D input in this product term to a logical one
21392  */
21393 #define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_DC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_DC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_DC_MASK)
21394 
21395 #define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_CC_MASK (0xC00U)
21396 #define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_CC_SHIFT (10U)
21397 /*! PT2_CC - Product Term 2, C Input Configuration
21398  *  0b00..Force the C input in this product term to a logical zero
21399  *  0b01..Pass the C input in this product term
21400  *  0b10..Complement the C input in this product term
21401  *  0b11..Force the C input in this product term to a logical one
21402  */
21403 #define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_CC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_CC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_CC_MASK)
21404 
21405 #define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_BC_MASK (0x3000U)
21406 #define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_BC_SHIFT (12U)
21407 /*! PT2_BC - Product Term 2, B Input Configuration
21408  *  0b00..Force the B input in this product term to a logical zero
21409  *  0b01..Pass the B input in this product term
21410  *  0b10..Complement the B input in this product term
21411  *  0b11..Force the B input in this product term to a logical one
21412  */
21413 #define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_BC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_BC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_BC_MASK)
21414 
21415 #define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_AC_MASK (0xC000U)
21416 #define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_AC_SHIFT (14U)
21417 /*! PT2_AC - Product Term 2, A Input Configuration
21418  *  0b00..Force the A input in this product term to a logical zero
21419  *  0b01..Pass the A input in this product term
21420  *  0b10..Complement the A input in this product term
21421  *  0b11..Force the A input in this product term to a logical one
21422  */
21423 #define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_AC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_AC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_AC_MASK)
21424 /*! @} */
21425 
21426 /* The count of EVTG_EVTG_INST_EVTG_AOI1_BFT23 */
21427 #define EVTG_EVTG_INST_EVTG_AOI1_BFT23_COUNT     (4U)
21428 
21429 /*! @name EVTG_INST_EVTG_CTRL - Control and Status */
21430 /*! @{ */
21431 
21432 #define EVTG_EVTG_INST_EVTG_CTRL_FF_INIT_MASK    (0x1U)
21433 #define EVTG_EVTG_INST_EVTG_CTRL_FF_INIT_SHIFT   (0U)
21434 /*! FF_INIT - Flip flop Initial Value Configuration
21435  *  0b0..0
21436  *  0b1..1
21437  */
21438 #define EVTG_EVTG_INST_EVTG_CTRL_FF_INIT(x)      (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_CTRL_FF_INIT_SHIFT)) & EVTG_EVTG_INST_EVTG_CTRL_FF_INIT_MASK)
21439 
21440 #define EVTG_EVTG_INST_EVTG_CTRL_INIT_EN_MASK    (0x2U)
21441 #define EVTG_EVTG_INST_EVTG_CTRL_INIT_EN_SHIFT   (1U)
21442 /*! INIT_EN - Flip-Flop Initial Output Enable Control
21443  *  0b0..Write 0 does not generate enable pulse
21444  *  0b1..Write 1 generates enable pulse
21445  */
21446 #define EVTG_EVTG_INST_EVTG_CTRL_INIT_EN(x)      (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_CTRL_INIT_EN_SHIFT)) & EVTG_EVTG_INST_EVTG_CTRL_INIT_EN_MASK)
21447 
21448 #define EVTG_EVTG_INST_EVTG_CTRL_MODE_SEL_MASK   (0x1CU)
21449 #define EVTG_EVTG_INST_EVTG_CTRL_MODE_SEL_SHIFT  (2U)
21450 /*! MODE_SEL - Flip-Flop Mode Selection
21451  *  0b000..Bypass mode
21452  *  0b001..RS Trigger mode
21453  *  0b010..T-FF mode
21454  *  0b011..D-FF mode
21455  *  0b100..JK-FF mode
21456  *  0b101..Latch mode
21457  *  0b110..Reserved
21458  *  0b111..Reserved
21459  */
21460 #define EVTG_EVTG_INST_EVTG_CTRL_MODE_SEL(x)     (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_CTRL_MODE_SEL_SHIFT)) & EVTG_EVTG_INST_EVTG_CTRL_MODE_SEL_MASK)
21461 
21462 #define EVTG_EVTG_INST_EVTG_CTRL_FB_OVRD_MASK    (0xC0U)
21463 #define EVTG_EVTG_INST_EVTG_CTRL_FB_OVRD_SHIFT   (6U)
21464 /*! FB_OVRD - EVTG Output Feedback Override Control
21465  *  0b00..Replace An
21466  *  0b01..Replace Bn
21467  *  0b10..Replace Cn
21468  *  0b11..Replace Dn
21469  */
21470 #define EVTG_EVTG_INST_EVTG_CTRL_FB_OVRD(x)      (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_CTRL_FB_OVRD_SHIFT)) & EVTG_EVTG_INST_EVTG_CTRL_FB_OVRD_MASK)
21471 
21472 #define EVTG_EVTG_INST_EVTG_CTRL_SYNC_CTRL_MASK  (0xF00U)
21473 #define EVTG_EVTG_INST_EVTG_CTRL_SYNC_CTRL_SHIFT (8U)
21474 /*! SYNC_CTRL - Synchronize Control
21475  *  0bxxx1..EVTG input "An" will be synced by two bus clk cycles
21476  *  0bxxx0..EVTG input "An" will not be synced
21477  *  0bxx1x..EVTG input "Bn" will be synced by two bus clk cycles
21478  *  0bxx0x..EVTG input "Bn" will not be synced
21479  *  0bx1xx..EVTG input "Cn" will be synced by two bus clk cycles
21480  *  0bx0xx..EVTG input "Cn" will not be synced
21481  *  0b1xxx..EVTG input "Dn" will be synced by two bus clk cycles
21482  *  0b0xxx..EVTG input "Dn" will not be synced
21483  */
21484 #define EVTG_EVTG_INST_EVTG_CTRL_SYNC_CTRL(x)    (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_CTRL_SYNC_CTRL_SHIFT)) & EVTG_EVTG_INST_EVTG_CTRL_SYNC_CTRL_MASK)
21485 
21486 #define EVTG_EVTG_INST_EVTG_CTRL_FORCE_BYPASS_MASK (0x3000U)
21487 #define EVTG_EVTG_INST_EVTG_CTRL_FORCE_BYPASS_SHIFT (12U)
21488 /*! FORCE_BYPASS - Force Bypass Control
21489  *  0bx1..Whatever MODE_SEL is, will force bypass flip-flop and route the AOI_0(Filter_0) value directly to EVTG_OUTA
21490  *  0bx0..Will not force the bypass
21491  *  0b1x..Whatever MODE_SEL is, will force bypass flip-flop and route the AOI_1(Filter_1) value directly to EVTG_OUTB
21492  *  0b0x..Will not force the bypass
21493  */
21494 #define EVTG_EVTG_INST_EVTG_CTRL_FORCE_BYPASS(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_CTRL_FORCE_BYPASS_SHIFT)) & EVTG_EVTG_INST_EVTG_CTRL_FORCE_BYPASS_MASK)
21495 /*! @} */
21496 
21497 /* The count of EVTG_EVTG_INST_EVTG_CTRL */
21498 #define EVTG_EVTG_INST_EVTG_CTRL_COUNT           (4U)
21499 
21500 /*! @name EVTG_INST_EVTG_AOI0_FILT - AOI0 Output Filter */
21501 /*! @{ */
21502 
21503 #define EVTG_EVTG_INST_EVTG_AOI0_FILT_FILT_PER_MASK (0xFFU)
21504 #define EVTG_EVTG_INST_EVTG_AOI0_FILT_FILT_PER_SHIFT (0U)
21505 /*! FILT_PER - Output Filter Sample Period */
21506 #define EVTG_EVTG_INST_EVTG_AOI0_FILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_FILT_FILT_PER_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_FILT_FILT_PER_MASK)
21507 
21508 #define EVTG_EVTG_INST_EVTG_AOI0_FILT_FILT_CNT_MASK (0x700U)
21509 #define EVTG_EVTG_INST_EVTG_AOI0_FILT_FILT_CNT_SHIFT (8U)
21510 /*! FILT_CNT - Output Filter Sample Count */
21511 #define EVTG_EVTG_INST_EVTG_AOI0_FILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_FILT_FILT_CNT_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_FILT_FILT_CNT_MASK)
21512 /*! @} */
21513 
21514 /* The count of EVTG_EVTG_INST_EVTG_AOI0_FILT */
21515 #define EVTG_EVTG_INST_EVTG_AOI0_FILT_COUNT      (4U)
21516 
21517 /*! @name EVTG_INST_EVTG_AOI1_FILT - AOI1 Output Filter */
21518 /*! @{ */
21519 
21520 #define EVTG_EVTG_INST_EVTG_AOI1_FILT_FILT_PER_MASK (0xFFU)
21521 #define EVTG_EVTG_INST_EVTG_AOI1_FILT_FILT_PER_SHIFT (0U)
21522 /*! FILT_PER - Output Filter Sample Period */
21523 #define EVTG_EVTG_INST_EVTG_AOI1_FILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_FILT_FILT_PER_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_FILT_FILT_PER_MASK)
21524 
21525 #define EVTG_EVTG_INST_EVTG_AOI1_FILT_FILT_CNT_MASK (0x700U)
21526 #define EVTG_EVTG_INST_EVTG_AOI1_FILT_FILT_CNT_SHIFT (8U)
21527 /*! FILT_CNT - Output Filter Sample Count */
21528 #define EVTG_EVTG_INST_EVTG_AOI1_FILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_FILT_FILT_CNT_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_FILT_FILT_CNT_MASK)
21529 /*! @} */
21530 
21531 /* The count of EVTG_EVTG_INST_EVTG_AOI1_FILT */
21532 #define EVTG_EVTG_INST_EVTG_AOI1_FILT_COUNT      (4U)
21533 
21534 
21535 /*!
21536  * @}
21537  */ /* end of group EVTG_Register_Masks */
21538 
21539 
21540 /* EVTG - Peripheral instance base addresses */
21541 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
21542   /** Peripheral EVTG0 base address */
21543   #define EVTG0_BASE                               (0x500D2000u)
21544   /** Peripheral EVTG0 base address */
21545   #define EVTG0_BASE_NS                            (0x400D2000u)
21546   /** Peripheral EVTG0 base pointer */
21547   #define EVTG0                                    ((EVTG_Type *)EVTG0_BASE)
21548   /** Peripheral EVTG0 base pointer */
21549   #define EVTG0_NS                                 ((EVTG_Type *)EVTG0_BASE_NS)
21550   /** Array initializer of EVTG peripheral base addresses */
21551   #define EVTG_BASE_ADDRS                          { EVTG0_BASE }
21552   /** Array initializer of EVTG peripheral base pointers */
21553   #define EVTG_BASE_PTRS                           { EVTG0 }
21554   /** Array initializer of EVTG peripheral base addresses */
21555   #define EVTG_BASE_ADDRS_NS                       { EVTG0_BASE_NS }
21556   /** Array initializer of EVTG peripheral base pointers */
21557   #define EVTG_BASE_PTRS_NS                        { EVTG0_NS }
21558 #else
21559   /** Peripheral EVTG0 base address */
21560   #define EVTG0_BASE                               (0x400D2000u)
21561   /** Peripheral EVTG0 base pointer */
21562   #define EVTG0                                    ((EVTG_Type *)EVTG0_BASE)
21563   /** Array initializer of EVTG peripheral base addresses */
21564   #define EVTG_BASE_ADDRS                          { EVTG0_BASE }
21565   /** Array initializer of EVTG peripheral base pointers */
21566   #define EVTG_BASE_PTRS                           { EVTG0 }
21567 #endif
21568 
21569 /*!
21570  * @}
21571  */ /* end of group EVTG_Peripheral_Access_Layer */
21572 
21573 
21574 /* ----------------------------------------------------------------------------
21575    -- EWM Peripheral Access Layer
21576    ---------------------------------------------------------------------------- */
21577 
21578 /*!
21579  * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer
21580  * @{
21581  */
21582 
21583 /** EWM - Register Layout Typedef */
21584 typedef struct {
21585   __IO uint8_t CTRL;                               /**< Control, offset: 0x0 */
21586   __O  uint8_t SERV;                               /**< Service, offset: 0x1 */
21587   __IO uint8_t CMPL;                               /**< Compare Low, offset: 0x2 */
21588   __IO uint8_t CMPH;                               /**< Compare High, offset: 0x3 */
21589   __IO uint8_t CLKCTRL;                            /**< Clock Control, offset: 0x4 */
21590   __IO uint8_t CLKPRESCALER;                       /**< Clock Prescaler, offset: 0x5 */
21591 } EWM_Type;
21592 
21593 /* ----------------------------------------------------------------------------
21594    -- EWM Register Masks
21595    ---------------------------------------------------------------------------- */
21596 
21597 /*!
21598  * @addtogroup EWM_Register_Masks EWM Register Masks
21599  * @{
21600  */
21601 
21602 /*! @name CTRL - Control */
21603 /*! @{ */
21604 
21605 #define EWM_CTRL_EWMEN_MASK                      (0x1U)
21606 #define EWM_CTRL_EWMEN_SHIFT                     (0U)
21607 /*! EWMEN - EWM Enable
21608  *  0b0..Disables
21609  *  0b1..Enables
21610  */
21611 #define EWM_CTRL_EWMEN(x)                        (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK)
21612 
21613 #define EWM_CTRL_ASSIN_MASK                      (0x2U)
21614 #define EWM_CTRL_ASSIN_SHIFT                     (1U)
21615 /*! ASSIN - Assertion State Select
21616  *  0b0..Logic 0
21617  *  0b1..Logic 1
21618  */
21619 #define EWM_CTRL_ASSIN(x)                        (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK)
21620 
21621 #define EWM_CTRL_INEN_MASK                       (0x4U)
21622 #define EWM_CTRL_INEN_SHIFT                      (2U)
21623 /*! INEN - Input Enable
21624  *  0b0..Disables
21625  *  0b1..Enables
21626  */
21627 #define EWM_CTRL_INEN(x)                         (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK)
21628 
21629 #define EWM_CTRL_INTEN_MASK                      (0x8U)
21630 #define EWM_CTRL_INTEN_SHIFT                     (3U)
21631 /*! INTEN - Interrupt Enable
21632  *  0b1..Generates interrupt requests
21633  *  0b0..Deasserts interrupt requests
21634  */
21635 #define EWM_CTRL_INTEN(x)                        (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK)
21636 /*! @} */
21637 
21638 /*! @name SERV - Service */
21639 /*! @{ */
21640 
21641 #define EWM_SERV_SERVICE_MASK                    (0xFFU)
21642 #define EWM_SERV_SERVICE_SHIFT                   (0U)
21643 /*! SERVICE - Service */
21644 #define EWM_SERV_SERVICE(x)                      (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK)
21645 /*! @} */
21646 
21647 /*! @name CMPL - Compare Low */
21648 /*! @{ */
21649 
21650 #define EWM_CMPL_COMPAREL_MASK                   (0xFFU)
21651 #define EWM_CMPL_COMPAREL_SHIFT                  (0U)
21652 /*! COMPAREL - Compare Low */
21653 #define EWM_CMPL_COMPAREL(x)                     (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK)
21654 /*! @} */
21655 
21656 /*! @name CMPH - Compare High */
21657 /*! @{ */
21658 
21659 #define EWM_CMPH_COMPAREH_MASK                   (0xFFU)
21660 #define EWM_CMPH_COMPAREH_SHIFT                  (0U)
21661 /*! COMPAREH - Compare High */
21662 #define EWM_CMPH_COMPAREH(x)                     (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK)
21663 /*! @} */
21664 
21665 /*! @name CLKCTRL - Clock Control */
21666 /*! @{ */
21667 
21668 #define EWM_CLKCTRL_CLKSEL_MASK                  (0x3U)
21669 #define EWM_CLKCTRL_CLKSEL_SHIFT                 (0U)
21670 /*! CLKSEL - Clock Select */
21671 #define EWM_CLKCTRL_CLKSEL(x)                    (((uint8_t)(((uint8_t)(x)) << EWM_CLKCTRL_CLKSEL_SHIFT)) & EWM_CLKCTRL_CLKSEL_MASK)
21672 /*! @} */
21673 
21674 /*! @name CLKPRESCALER - Clock Prescaler */
21675 /*! @{ */
21676 
21677 #define EWM_CLKPRESCALER_CLK_DIV_MASK            (0xFFU)
21678 #define EWM_CLKPRESCALER_CLK_DIV_SHIFT           (0U)
21679 /*! CLK_DIV - Clock Divider */
21680 #define EWM_CLKPRESCALER_CLK_DIV(x)              (((uint8_t)(((uint8_t)(x)) << EWM_CLKPRESCALER_CLK_DIV_SHIFT)) & EWM_CLKPRESCALER_CLK_DIV_MASK)
21681 /*! @} */
21682 
21683 
21684 /*!
21685  * @}
21686  */ /* end of group EWM_Register_Masks */
21687 
21688 
21689 /* EWM - Peripheral instance base addresses */
21690 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
21691   /** Peripheral EWM0 base address */
21692   #define EWM0_BASE                                (0x500C0000u)
21693   /** Peripheral EWM0 base address */
21694   #define EWM0_BASE_NS                             (0x400C0000u)
21695   /** Peripheral EWM0 base pointer */
21696   #define EWM0                                     ((EWM_Type *)EWM0_BASE)
21697   /** Peripheral EWM0 base pointer */
21698   #define EWM0_NS                                  ((EWM_Type *)EWM0_BASE_NS)
21699   /** Array initializer of EWM peripheral base addresses */
21700   #define EWM_BASE_ADDRS                           { EWM0_BASE }
21701   /** Array initializer of EWM peripheral base pointers */
21702   #define EWM_BASE_PTRS                            { EWM0 }
21703   /** Array initializer of EWM peripheral base addresses */
21704   #define EWM_BASE_ADDRS_NS                        { EWM0_BASE_NS }
21705   /** Array initializer of EWM peripheral base pointers */
21706   #define EWM_BASE_PTRS_NS                         { EWM0_NS }
21707 #else
21708   /** Peripheral EWM0 base address */
21709   #define EWM0_BASE                                (0x400C0000u)
21710   /** Peripheral EWM0 base pointer */
21711   #define EWM0                                     ((EWM_Type *)EWM0_BASE)
21712   /** Array initializer of EWM peripheral base addresses */
21713   #define EWM_BASE_ADDRS                           { EWM0_BASE }
21714   /** Array initializer of EWM peripheral base pointers */
21715   #define EWM_BASE_PTRS                            { EWM0 }
21716 #endif
21717 
21718 /*!
21719  * @}
21720  */ /* end of group EWM_Peripheral_Access_Layer */
21721 
21722 
21723 /* ----------------------------------------------------------------------------
21724    -- FLEXIO Peripheral Access Layer
21725    ---------------------------------------------------------------------------- */
21726 
21727 /*!
21728  * @addtogroup FLEXIO_Peripheral_Access_Layer FLEXIO Peripheral Access Layer
21729  * @{
21730  */
21731 
21732 /** FLEXIO - Register Layout Typedef */
21733 typedef struct {
21734   __I  uint32_t VERID;                             /**< Version ID, offset: 0x0 */
21735   __I  uint32_t PARAM;                             /**< Parameter, offset: 0x4 */
21736   __IO uint32_t CTRL;                              /**< FLEXIO Control, offset: 0x8 */
21737   __I  uint32_t PIN;                               /**< Pin State, offset: 0xC */
21738   __IO uint32_t SHIFTSTAT;                         /**< Shifter Status, offset: 0x10 */
21739   __IO uint32_t SHIFTERR;                          /**< Shifter Error, offset: 0x14 */
21740   __IO uint32_t TIMSTAT;                           /**< Timer Status Flag, offset: 0x18 */
21741        uint8_t RESERVED_0[4];
21742   __IO uint32_t SHIFTSIEN;                         /**< Shifter Status Interrupt Enable, offset: 0x20 */
21743   __IO uint32_t SHIFTEIEN;                         /**< Shifter Error Interrupt Enable, offset: 0x24 */
21744   __IO uint32_t TIMIEN;                            /**< Timer Interrupt Enable, offset: 0x28 */
21745        uint8_t RESERVED_1[4];
21746   __IO uint32_t SHIFTSDEN;                         /**< Shifter Status DMA Enable, offset: 0x30 */
21747        uint8_t RESERVED_2[4];
21748   __IO uint32_t TIMERSDEN;                         /**< Timer Status DMA Enable, offset: 0x38 */
21749        uint8_t RESERVED_3[4];
21750   __IO uint32_t SHIFTSTATE;                        /**< Shifter State, offset: 0x40 */
21751        uint8_t RESERVED_4[4];
21752   __IO uint32_t TRGSTAT;                           /**< Trigger Status, offset: 0x48 */
21753   __IO uint32_t TRIGIEN;                           /**< External Trigger Interrupt Enable, offset: 0x4C */
21754   __IO uint32_t PINSTAT;                           /**< Pin Status, offset: 0x50 */
21755   __IO uint32_t PINIEN;                            /**< Pin Interrupt Enable, offset: 0x54 */
21756   __IO uint32_t PINREN;                            /**< Pin Rising Edge Enable, offset: 0x58 */
21757   __IO uint32_t PINFEN;                            /**< Pin Falling Edge Enable, offset: 0x5C */
21758   __IO uint32_t PINOUTD;                           /**< Pin Output Data, offset: 0x60 */
21759   __IO uint32_t PINOUTE;                           /**< Pin Output Enable, offset: 0x64 */
21760   __O  uint32_t PINOUTDIS;                         /**< Pin Output Disable, offset: 0x68 */
21761   __O  uint32_t PINOUTCLR;                         /**< Pin Output Clear, offset: 0x6C */
21762   __O  uint32_t PINOUTSET;                         /**< Pin Output Set, offset: 0x70 */
21763   __O  uint32_t PINOUTTOG;                         /**< Pin Output Toggle, offset: 0x74 */
21764        uint8_t RESERVED_5[8];
21765   __IO uint32_t SHIFTCTL[8];                       /**< Shifter Control, array offset: 0x80, array step: 0x4 */
21766        uint8_t RESERVED_6[96];
21767   __IO uint32_t SHIFTCFG[8];                       /**< Shifter Configuration, array offset: 0x100, array step: 0x4 */
21768        uint8_t RESERVED_7[224];
21769   __IO uint32_t SHIFTBUF[8];                       /**< Shifter Buffer, array offset: 0x200, array step: 0x4 */
21770        uint8_t RESERVED_8[96];
21771   __IO uint32_t SHIFTBUFBIS[8];                    /**< Shifter Buffer Bit Swapped, array offset: 0x280, array step: 0x4 */
21772        uint8_t RESERVED_9[96];
21773   __IO uint32_t SHIFTBUFBYS[8];                    /**< Shifter Buffer Byte Swapped, array offset: 0x300, array step: 0x4 */
21774        uint8_t RESERVED_10[96];
21775   __IO uint32_t SHIFTBUFBBS[8];                    /**< Shifter Buffer Bit Byte Swapped, array offset: 0x380, array step: 0x4 */
21776        uint8_t RESERVED_11[96];
21777   __IO uint32_t TIMCTL[8];                         /**< Timer Control, array offset: 0x400, array step: 0x4 */
21778        uint8_t RESERVED_12[96];
21779   __IO uint32_t TIMCFG[8];                         /**< Timer Configuration, array offset: 0x480, array step: 0x4 */
21780        uint8_t RESERVED_13[96];
21781   __IO uint32_t TIMCMP[8];                         /**< Timer Compare, array offset: 0x500, array step: 0x4 */
21782        uint8_t RESERVED_14[352];
21783   __IO uint32_t SHIFTBUFNBS[8];                    /**< Shifter Buffer Nibble Byte Swapped, array offset: 0x680, array step: 0x4 */
21784        uint8_t RESERVED_15[96];
21785   __IO uint32_t SHIFTBUFHWS[8];                    /**< Shifter Buffer Halfword Swapped, array offset: 0x700, array step: 0x4 */
21786        uint8_t RESERVED_16[96];
21787   __IO uint32_t SHIFTBUFNIS[8];                    /**< Shifter Buffer Nibble Swapped, array offset: 0x780, array step: 0x4 */
21788        uint8_t RESERVED_17[96];
21789   __IO uint32_t SHIFTBUFOES[8];                    /**< Shifter Buffer Odd Even Swapped, array offset: 0x800, array step: 0x4 */
21790        uint8_t RESERVED_18[96];
21791   __IO uint32_t SHIFTBUFEOS[8];                    /**< Shifter Buffer Even Odd Swapped, array offset: 0x880, array step: 0x4 */
21792        uint8_t RESERVED_19[96];
21793   __IO uint32_t SHIFTBUFHBS[8];                    /**< Shifter Buffer Halfword Byte Swapped, array offset: 0x900, array step: 0x4 */
21794 } FLEXIO_Type;
21795 
21796 /* ----------------------------------------------------------------------------
21797    -- FLEXIO Register Masks
21798    ---------------------------------------------------------------------------- */
21799 
21800 /*!
21801  * @addtogroup FLEXIO_Register_Masks FLEXIO Register Masks
21802  * @{
21803  */
21804 
21805 /*! @name VERID - Version ID */
21806 /*! @{ */
21807 
21808 #define FLEXIO_VERID_FEATURE_MASK                (0xFFFFU)
21809 #define FLEXIO_VERID_FEATURE_SHIFT               (0U)
21810 /*! FEATURE - Feature Specification Number
21811  *  0b0000000000000000..Standard features implemented
21812  *  0b0000000000000001..State, logic, and parallel modes supported
21813  *  0b0000000000000010..Pin control registers supported
21814  *  0b0000000000000011..State, logic, and parallel modes, plus pin control registers supported
21815  */
21816 #define FLEXIO_VERID_FEATURE(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_FEATURE_SHIFT)) & FLEXIO_VERID_FEATURE_MASK)
21817 
21818 #define FLEXIO_VERID_MINOR_MASK                  (0xFF0000U)
21819 #define FLEXIO_VERID_MINOR_SHIFT                 (16U)
21820 /*! MINOR - Minor Version Number */
21821 #define FLEXIO_VERID_MINOR(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MINOR_SHIFT)) & FLEXIO_VERID_MINOR_MASK)
21822 
21823 #define FLEXIO_VERID_MAJOR_MASK                  (0xFF000000U)
21824 #define FLEXIO_VERID_MAJOR_SHIFT                 (24U)
21825 /*! MAJOR - Major Version Number */
21826 #define FLEXIO_VERID_MAJOR(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MAJOR_SHIFT)) & FLEXIO_VERID_MAJOR_MASK)
21827 /*! @} */
21828 
21829 /*! @name PARAM - Parameter */
21830 /*! @{ */
21831 
21832 #define FLEXIO_PARAM_SHIFTER_MASK                (0xFFU)
21833 #define FLEXIO_PARAM_SHIFTER_SHIFT               (0U)
21834 /*! SHIFTER - Shifter Number */
21835 #define FLEXIO_PARAM_SHIFTER(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_SHIFTER_SHIFT)) & FLEXIO_PARAM_SHIFTER_MASK)
21836 
21837 #define FLEXIO_PARAM_TIMER_MASK                  (0xFF00U)
21838 #define FLEXIO_PARAM_TIMER_SHIFT                 (8U)
21839 /*! TIMER - Timer Number */
21840 #define FLEXIO_PARAM_TIMER(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TIMER_SHIFT)) & FLEXIO_PARAM_TIMER_MASK)
21841 
21842 #define FLEXIO_PARAM_PIN_MASK                    (0xFF0000U)
21843 #define FLEXIO_PARAM_PIN_SHIFT                   (16U)
21844 /*! PIN - Pin Number */
21845 #define FLEXIO_PARAM_PIN(x)                      (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_PIN_SHIFT)) & FLEXIO_PARAM_PIN_MASK)
21846 
21847 #define FLEXIO_PARAM_TRIGGER_MASK                (0xFF000000U)
21848 #define FLEXIO_PARAM_TRIGGER_SHIFT               (24U)
21849 /*! TRIGGER - Trigger Number */
21850 #define FLEXIO_PARAM_TRIGGER(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TRIGGER_SHIFT)) & FLEXIO_PARAM_TRIGGER_MASK)
21851 /*! @} */
21852 
21853 /*! @name CTRL - FLEXIO Control */
21854 /*! @{ */
21855 
21856 #define FLEXIO_CTRL_FLEXEN_MASK                  (0x1U)
21857 #define FLEXIO_CTRL_FLEXEN_SHIFT                 (0U)
21858 /*! FLEXEN - FLEXIO Enable
21859  *  0b0..Disable
21860  *  0b1..Enable
21861  */
21862 #define FLEXIO_CTRL_FLEXEN(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FLEXEN_SHIFT)) & FLEXIO_CTRL_FLEXEN_MASK)
21863 
21864 #define FLEXIO_CTRL_SWRST_MASK                   (0x2U)
21865 #define FLEXIO_CTRL_SWRST_SHIFT                  (1U)
21866 /*! SWRST - Software Reset
21867  *  0b0..Disabled
21868  *  0b1..Enabled
21869  */
21870 #define FLEXIO_CTRL_SWRST(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_SWRST_SHIFT)) & FLEXIO_CTRL_SWRST_MASK)
21871 
21872 #define FLEXIO_CTRL_FASTACC_MASK                 (0x4U)
21873 #define FLEXIO_CTRL_FASTACC_SHIFT                (2U)
21874 /*! FASTACC - Fast Access
21875  *  0b0..Normal
21876  *  0b1..Fast
21877  */
21878 #define FLEXIO_CTRL_FASTACC(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FASTACC_SHIFT)) & FLEXIO_CTRL_FASTACC_MASK)
21879 
21880 #define FLEXIO_CTRL_DBGE_MASK                    (0x40000000U)
21881 #define FLEXIO_CTRL_DBGE_SHIFT                   (30U)
21882 /*! DBGE - Debug Enable
21883  *  0b0..Disable
21884  *  0b1..Enable
21885  */
21886 #define FLEXIO_CTRL_DBGE(x)                      (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DBGE_SHIFT)) & FLEXIO_CTRL_DBGE_MASK)
21887 
21888 #define FLEXIO_CTRL_DOZEN_MASK                   (0x80000000U)
21889 #define FLEXIO_CTRL_DOZEN_SHIFT                  (31U)
21890 /*! DOZEN - Doze Enable
21891  *  0b0..Enable
21892  *  0b1..Disable
21893  */
21894 #define FLEXIO_CTRL_DOZEN(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DOZEN_SHIFT)) & FLEXIO_CTRL_DOZEN_MASK)
21895 /*! @} */
21896 
21897 /*! @name PIN - Pin State */
21898 /*! @{ */
21899 
21900 #define FLEXIO_PIN_PDI_MASK                      (0xFFFFFFFFU)
21901 #define FLEXIO_PIN_PDI_SHIFT                     (0U)
21902 /*! PDI - Pin Data Input */
21903 #define FLEXIO_PIN_PDI(x)                        (((uint32_t)(((uint32_t)(x)) << FLEXIO_PIN_PDI_SHIFT)) & FLEXIO_PIN_PDI_MASK)
21904 /*! @} */
21905 
21906 /*! @name SHIFTSTAT - Shifter Status */
21907 /*! @{ */
21908 
21909 #define FLEXIO_SHIFTSTAT_SSF_MASK                (0xFFU)
21910 #define FLEXIO_SHIFTSTAT_SSF_SHIFT               (0U)
21911 /*! SSF - Shifter Status Flag
21912  *  0b00000000..Clear
21913  *  0b00000001..Set
21914  *  0b00000000..No effect
21915  *  0b00000001..Clear the flag
21916  */
21917 #define FLEXIO_SHIFTSTAT_SSF(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTAT_SSF_SHIFT)) & FLEXIO_SHIFTSTAT_SSF_MASK)
21918 /*! @} */
21919 
21920 /*! @name SHIFTERR - Shifter Error */
21921 /*! @{ */
21922 
21923 #define FLEXIO_SHIFTERR_SEF_MASK                 (0xFFU)
21924 #define FLEXIO_SHIFTERR_SEF_SHIFT                (0U)
21925 /*! SEF - Shifter Error Flag
21926  *  0b00000000..Clear
21927  *  0b00000001..Set
21928  *  0b00000000..No effect
21929  *  0b00000001..Clear the flag
21930  */
21931 #define FLEXIO_SHIFTERR_SEF(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTERR_SEF_SHIFT)) & FLEXIO_SHIFTERR_SEF_MASK)
21932 /*! @} */
21933 
21934 /*! @name TIMSTAT - Timer Status Flag */
21935 /*! @{ */
21936 
21937 #define FLEXIO_TIMSTAT_TSF_MASK                  (0xFFU)
21938 #define FLEXIO_TIMSTAT_TSF_SHIFT                 (0U)
21939 /*! TSF - Timer Status Flag
21940  *  0b00000000..Clear
21941  *  0b00000001..Set
21942  *  0b00000000..No effect
21943  *  0b00000001..Clear the flag
21944  */
21945 #define FLEXIO_TIMSTAT_TSF(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMSTAT_TSF_SHIFT)) & FLEXIO_TIMSTAT_TSF_MASK)
21946 /*! @} */
21947 
21948 /*! @name SHIFTSIEN - Shifter Status Interrupt Enable */
21949 /*! @{ */
21950 
21951 #define FLEXIO_SHIFTSIEN_SSIE_MASK               (0xFFU)
21952 #define FLEXIO_SHIFTSIEN_SSIE_SHIFT              (0U)
21953 /*! SSIE - Shifter Status Interrupt Enable */
21954 #define FLEXIO_SHIFTSIEN_SSIE(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSIEN_SSIE_SHIFT)) & FLEXIO_SHIFTSIEN_SSIE_MASK)
21955 /*! @} */
21956 
21957 /*! @name SHIFTEIEN - Shifter Error Interrupt Enable */
21958 /*! @{ */
21959 
21960 #define FLEXIO_SHIFTEIEN_SEIE_MASK               (0xFFU)
21961 #define FLEXIO_SHIFTEIEN_SEIE_SHIFT              (0U)
21962 /*! SEIE - Shifter Error Interrupt Enable */
21963 #define FLEXIO_SHIFTEIEN_SEIE(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTEIEN_SEIE_SHIFT)) & FLEXIO_SHIFTEIEN_SEIE_MASK)
21964 /*! @} */
21965 
21966 /*! @name TIMIEN - Timer Interrupt Enable */
21967 /*! @{ */
21968 
21969 #define FLEXIO_TIMIEN_TEIE_MASK                  (0xFFU)
21970 #define FLEXIO_TIMIEN_TEIE_SHIFT                 (0U)
21971 /*! TEIE - Timer Status Interrupt Enable */
21972 #define FLEXIO_TIMIEN_TEIE(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMIEN_TEIE_SHIFT)) & FLEXIO_TIMIEN_TEIE_MASK)
21973 /*! @} */
21974 
21975 /*! @name SHIFTSDEN - Shifter Status DMA Enable */
21976 /*! @{ */
21977 
21978 #define FLEXIO_SHIFTSDEN_SSDE_MASK               (0xFFU)
21979 #define FLEXIO_SHIFTSDEN_SSDE_SHIFT              (0U)
21980 /*! SSDE - Shifter Status DMA Enable */
21981 #define FLEXIO_SHIFTSDEN_SSDE(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSDEN_SSDE_SHIFT)) & FLEXIO_SHIFTSDEN_SSDE_MASK)
21982 /*! @} */
21983 
21984 /*! @name TIMERSDEN - Timer Status DMA Enable */
21985 /*! @{ */
21986 
21987 #define FLEXIO_TIMERSDEN_TSDE_MASK               (0xFFU)
21988 #define FLEXIO_TIMERSDEN_TSDE_SHIFT              (0U)
21989 /*! TSDE - Timer Status DMA Enable */
21990 #define FLEXIO_TIMERSDEN_TSDE(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMERSDEN_TSDE_SHIFT)) & FLEXIO_TIMERSDEN_TSDE_MASK)
21991 /*! @} */
21992 
21993 /*! @name SHIFTSTATE - Shifter State */
21994 /*! @{ */
21995 
21996 #define FLEXIO_SHIFTSTATE_STATE_MASK             (0x7U)
21997 #define FLEXIO_SHIFTSTATE_STATE_SHIFT            (0U)
21998 /*! STATE - Current State Pointer */
21999 #define FLEXIO_SHIFTSTATE_STATE(x)               (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTATE_STATE_SHIFT)) & FLEXIO_SHIFTSTATE_STATE_MASK)
22000 /*! @} */
22001 
22002 /*! @name TRGSTAT - Trigger Status */
22003 /*! @{ */
22004 
22005 #define FLEXIO_TRGSTAT_ETSF_MASK                 (0xFFU)
22006 #define FLEXIO_TRGSTAT_ETSF_SHIFT                (0U)
22007 /*! ETSF - External Trigger Status Flag
22008  *  0b00000000..Clear
22009  *  0b00000001..Set
22010  *  0b00000000..No effect
22011  *  0b00000001..Clear the flag
22012  */
22013 #define FLEXIO_TRGSTAT_ETSF(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TRGSTAT_ETSF_SHIFT)) & FLEXIO_TRGSTAT_ETSF_MASK)
22014 /*! @} */
22015 
22016 /*! @name TRIGIEN - External Trigger Interrupt Enable */
22017 /*! @{ */
22018 
22019 #define FLEXIO_TRIGIEN_TRIE_MASK                 (0xFFU)
22020 #define FLEXIO_TRIGIEN_TRIE_SHIFT                (0U)
22021 /*! TRIE - External Trigger Interrupt Enable */
22022 #define FLEXIO_TRIGIEN_TRIE(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TRIGIEN_TRIE_SHIFT)) & FLEXIO_TRIGIEN_TRIE_MASK)
22023 /*! @} */
22024 
22025 /*! @name PINSTAT - Pin Status */
22026 /*! @{ */
22027 
22028 #define FLEXIO_PINSTAT_PSF_MASK                  (0xFFFFFFFFU)
22029 #define FLEXIO_PINSTAT_PSF_SHIFT                 (0U)
22030 /*! PSF - Pin Status Flag
22031  *  0b00000000000000000000000000000000..Clear
22032  *  0b00000000000000000000000000000001..Set
22033  *  0b00000000000000000000000000000000..No effect
22034  *  0b00000000000000000000000000000001..Clear the flag
22035  */
22036 #define FLEXIO_PINSTAT_PSF(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINSTAT_PSF_SHIFT)) & FLEXIO_PINSTAT_PSF_MASK)
22037 /*! @} */
22038 
22039 /*! @name PINIEN - Pin Interrupt Enable */
22040 /*! @{ */
22041 
22042 #define FLEXIO_PINIEN_PSIE_MASK                  (0xFFFFFFFFU)
22043 #define FLEXIO_PINIEN_PSIE_SHIFT                 (0U)
22044 /*! PSIE - Pin Status Interrupt Enable */
22045 #define FLEXIO_PINIEN_PSIE(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINIEN_PSIE_SHIFT)) & FLEXIO_PINIEN_PSIE_MASK)
22046 /*! @} */
22047 
22048 /*! @name PINREN - Pin Rising Edge Enable */
22049 /*! @{ */
22050 
22051 #define FLEXIO_PINREN_PRE_MASK                   (0xFFFFFFFFU)
22052 #define FLEXIO_PINREN_PRE_SHIFT                  (0U)
22053 /*! PRE - Pin Rising Edge */
22054 #define FLEXIO_PINREN_PRE(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINREN_PRE_SHIFT)) & FLEXIO_PINREN_PRE_MASK)
22055 /*! @} */
22056 
22057 /*! @name PINFEN - Pin Falling Edge Enable */
22058 /*! @{ */
22059 
22060 #define FLEXIO_PINFEN_PFE_MASK                   (0xFFFFFFFFU)
22061 #define FLEXIO_PINFEN_PFE_SHIFT                  (0U)
22062 /*! PFE - Pin Falling Edge */
22063 #define FLEXIO_PINFEN_PFE(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINFEN_PFE_SHIFT)) & FLEXIO_PINFEN_PFE_MASK)
22064 /*! @} */
22065 
22066 /*! @name PINOUTD - Pin Output Data */
22067 /*! @{ */
22068 
22069 #define FLEXIO_PINOUTD_OUTD_MASK                 (0xFFFFFFFFU)
22070 #define FLEXIO_PINOUTD_OUTD_SHIFT                (0U)
22071 /*! OUTD - Output Data */
22072 #define FLEXIO_PINOUTD_OUTD(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTD_OUTD_SHIFT)) & FLEXIO_PINOUTD_OUTD_MASK)
22073 /*! @} */
22074 
22075 /*! @name PINOUTE - Pin Output Enable */
22076 /*! @{ */
22077 
22078 #define FLEXIO_PINOUTE_OUTE_MASK                 (0xFFFFFFFFU)
22079 #define FLEXIO_PINOUTE_OUTE_SHIFT                (0U)
22080 /*! OUTE - Output Enable */
22081 #define FLEXIO_PINOUTE_OUTE(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTE_OUTE_SHIFT)) & FLEXIO_PINOUTE_OUTE_MASK)
22082 /*! @} */
22083 
22084 /*! @name PINOUTDIS - Pin Output Disable */
22085 /*! @{ */
22086 
22087 #define FLEXIO_PINOUTDIS_OUTDIS_MASK             (0xFFFFFFFFU)
22088 #define FLEXIO_PINOUTDIS_OUTDIS_SHIFT            (0U)
22089 /*! OUTDIS - Output Disable */
22090 #define FLEXIO_PINOUTDIS_OUTDIS(x)               (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTDIS_OUTDIS_SHIFT)) & FLEXIO_PINOUTDIS_OUTDIS_MASK)
22091 /*! @} */
22092 
22093 /*! @name PINOUTCLR - Pin Output Clear */
22094 /*! @{ */
22095 
22096 #define FLEXIO_PINOUTCLR_OUTCLR_MASK             (0xFFFFFFFFU)
22097 #define FLEXIO_PINOUTCLR_OUTCLR_SHIFT            (0U)
22098 /*! OUTCLR - Output Clear */
22099 #define FLEXIO_PINOUTCLR_OUTCLR(x)               (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTCLR_OUTCLR_SHIFT)) & FLEXIO_PINOUTCLR_OUTCLR_MASK)
22100 /*! @} */
22101 
22102 /*! @name PINOUTSET - Pin Output Set */
22103 /*! @{ */
22104 
22105 #define FLEXIO_PINOUTSET_OUTSET_MASK             (0xFFFFFFFFU)
22106 #define FLEXIO_PINOUTSET_OUTSET_SHIFT            (0U)
22107 /*! OUTSET - Output Set */
22108 #define FLEXIO_PINOUTSET_OUTSET(x)               (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTSET_OUTSET_SHIFT)) & FLEXIO_PINOUTSET_OUTSET_MASK)
22109 /*! @} */
22110 
22111 /*! @name PINOUTTOG - Pin Output Toggle */
22112 /*! @{ */
22113 
22114 #define FLEXIO_PINOUTTOG_OUTTOG_MASK             (0xFFFFFFFFU)
22115 #define FLEXIO_PINOUTTOG_OUTTOG_SHIFT            (0U)
22116 /*! OUTTOG - Output Toggle */
22117 #define FLEXIO_PINOUTTOG_OUTTOG(x)               (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTTOG_OUTTOG_SHIFT)) & FLEXIO_PINOUTTOG_OUTTOG_MASK)
22118 /*! @} */
22119 
22120 /*! @name SHIFTCTL - Shifter Control */
22121 /*! @{ */
22122 
22123 #define FLEXIO_SHIFTCTL_SMOD_MASK                (0x7U)
22124 #define FLEXIO_SHIFTCTL_SMOD_SHIFT               (0U)
22125 /*! SMOD - Shifter Mode
22126  *  0b000..Disable
22127  *  0b001..Receive mode; capture the current shifter content into SHIFTBUF on expiration of the timer
22128  *  0b010..Transmit mode; load SHIFTBUF contents into the shifter on expiration of the timer
22129  *  0b011..Reserved
22130  *  0b100..Match Store mode; shifter data is compared to SHIFTBUF content on expiration of the timer
22131  *  0b101..Match Continuous mode; shifter data is continuously compared to SHIFTBUF contents
22132  *  0b110..State mode; SHIFTBUF contents store programmable state attributes
22133  *  0b111..Logic mode; SHIFTBUF contents implement programmable logic lookup table
22134  */
22135 #define FLEXIO_SHIFTCTL_SMOD(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_SMOD_SHIFT)) & FLEXIO_SHIFTCTL_SMOD_MASK)
22136 
22137 #define FLEXIO_SHIFTCTL_PINPOL_MASK              (0x80U)
22138 #define FLEXIO_SHIFTCTL_PINPOL_SHIFT             (7U)
22139 /*! PINPOL - Shifter Pin Polarity
22140  *  0b0..Active high
22141  *  0b1..Active low
22142  */
22143 #define FLEXIO_SHIFTCTL_PINPOL(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINPOL_SHIFT)) & FLEXIO_SHIFTCTL_PINPOL_MASK)
22144 
22145 #define FLEXIO_SHIFTCTL_PINSEL_MASK              (0x1F00U)
22146 #define FLEXIO_SHIFTCTL_PINSEL_SHIFT             (8U)
22147 /*! PINSEL - Shifter Pin Select */
22148 #define FLEXIO_SHIFTCTL_PINSEL(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINSEL_SHIFT)) & FLEXIO_SHIFTCTL_PINSEL_MASK)
22149 
22150 #define FLEXIO_SHIFTCTL_PINCFG_MASK              (0x30000U)
22151 #define FLEXIO_SHIFTCTL_PINCFG_SHIFT             (16U)
22152 /*! PINCFG - Shifter Pin Configuration
22153  *  0b00..Shifter pin output disabled
22154  *  0b01..Shifter pin open-drain or bidirectional output enable
22155  *  0b10..Shifter pin bidirectional output data
22156  *  0b11..Shifter pin output
22157  */
22158 #define FLEXIO_SHIFTCTL_PINCFG(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINCFG_SHIFT)) & FLEXIO_SHIFTCTL_PINCFG_MASK)
22159 
22160 #define FLEXIO_SHIFTCTL_TIMPOL_MASK              (0x800000U)
22161 #define FLEXIO_SHIFTCTL_TIMPOL_SHIFT             (23U)
22162 /*! TIMPOL - Timer Polarity
22163  *  0b0..Positive edge
22164  *  0b1..Negative edge
22165  */
22166 #define FLEXIO_SHIFTCTL_TIMPOL(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMPOL_SHIFT)) & FLEXIO_SHIFTCTL_TIMPOL_MASK)
22167 
22168 #define FLEXIO_SHIFTCTL_TIMSEL_MASK              (0x7000000U)
22169 #define FLEXIO_SHIFTCTL_TIMSEL_SHIFT             (24U)
22170 /*! TIMSEL - Timer Select */
22171 #define FLEXIO_SHIFTCTL_TIMSEL(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMSEL_SHIFT)) & FLEXIO_SHIFTCTL_TIMSEL_MASK)
22172 /*! @} */
22173 
22174 /* The count of FLEXIO_SHIFTCTL */
22175 #define FLEXIO_SHIFTCTL_COUNT                    (8U)
22176 
22177 /*! @name SHIFTCFG - Shifter Configuration */
22178 /*! @{ */
22179 
22180 #define FLEXIO_SHIFTCFG_SSTART_MASK              (0x3U)
22181 #define FLEXIO_SHIFTCFG_SSTART_SHIFT             (0U)
22182 /*! SSTART - Shifter Start
22183  *  0b00..Start bit disabled for Transmitter, Receiver, and Match Store modes; Transmitter mode loads data on enable
22184  *  0b01..Start bit disabled for Transmitter, Receiver, and Match Store modes; Transmitter mode loads data on first shift
22185  *  0b10..Transmitter mode outputs start bit value 0 before loading data on first shift; if start bit is not 0,
22186  *        Receiver and Match Store modes set error flag
22187  *  0b11..Transmitter mode outputs start bit value 1 before loading data on first shift; if start bit is not 1,
22188  *        Receiver and Match Store modes set error flag
22189  */
22190 #define FLEXIO_SHIFTCFG_SSTART(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTART_SHIFT)) & FLEXIO_SHIFTCFG_SSTART_MASK)
22191 
22192 #define FLEXIO_SHIFTCFG_SSTOP_MASK               (0x30U)
22193 #define FLEXIO_SHIFTCFG_SSTOP_SHIFT              (4U)
22194 /*! SSTOP - Shifter Stop
22195  *  0b00..Stop bit disabled for Transmitter, Receiver, and Match Store modes
22196  *  0b01..Stop bit disabled for Transmitter, Receiver, and Match Store modes; when timer is in stop condition,
22197  *        Receiver and Match Store modes store receive data on the configured shift edge
22198  *  0b10..Transmitter mode outputs stop bit value 0 in Match Store mode; if stop bit is not 0, Receiver and Match
22199  *        Store modes set error flag (when timer is in stop condition, these modes also store receive data on the
22200  *        configured shift edge)
22201  *  0b11..Transmitter mode outputs stop bit value 1 in Match Store mode; if stop bit is not 1, Receiver and Match
22202  *        Store modes set error flag (when timer is in stop condition, these modes also store receive data on the
22203  *        configured shift edge)
22204  */
22205 #define FLEXIO_SHIFTCFG_SSTOP(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTOP_SHIFT)) & FLEXIO_SHIFTCFG_SSTOP_MASK)
22206 
22207 #define FLEXIO_SHIFTCFG_INSRC_MASK               (0x100U)
22208 #define FLEXIO_SHIFTCFG_INSRC_SHIFT              (8U)
22209 /*! INSRC - Input Source
22210  *  0b0..Pin
22211  *  0b1..Shifter n+1 output
22212  */
22213 #define FLEXIO_SHIFTCFG_INSRC(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_INSRC_SHIFT)) & FLEXIO_SHIFTCFG_INSRC_MASK)
22214 
22215 #define FLEXIO_SHIFTCFG_LATST_MASK               (0x200U)
22216 #define FLEXIO_SHIFTCFG_LATST_SHIFT              (9U)
22217 /*! LATST - Late Store
22218  *  0b0..Store the pre-shift register state
22219  *  0b1..Store the post-shift register state
22220  */
22221 #define FLEXIO_SHIFTCFG_LATST(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_LATST_SHIFT)) & FLEXIO_SHIFTCFG_LATST_MASK)
22222 
22223 #define FLEXIO_SHIFTCFG_SSIZE_MASK               (0x1000U)
22224 #define FLEXIO_SHIFTCFG_SSIZE_SHIFT              (12U)
22225 /*! SSIZE - Shifter Size
22226  *  0b0..32-bit
22227  *  0b1..24-bit
22228  */
22229 #define FLEXIO_SHIFTCFG_SSIZE(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSIZE_SHIFT)) & FLEXIO_SHIFTCFG_SSIZE_MASK)
22230 
22231 #define FLEXIO_SHIFTCFG_PWIDTH_MASK              (0x1F0000U)
22232 #define FLEXIO_SHIFTCFG_PWIDTH_SHIFT             (16U)
22233 /*! PWIDTH - Parallel Width */
22234 #define FLEXIO_SHIFTCFG_PWIDTH(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_PWIDTH_SHIFT)) & FLEXIO_SHIFTCFG_PWIDTH_MASK)
22235 /*! @} */
22236 
22237 /* The count of FLEXIO_SHIFTCFG */
22238 #define FLEXIO_SHIFTCFG_COUNT                    (8U)
22239 
22240 /*! @name SHIFTBUF - Shifter Buffer */
22241 /*! @{ */
22242 
22243 #define FLEXIO_SHIFTBUF_SHIFTBUF_MASK            (0xFFFFFFFFU)
22244 #define FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT           (0U)
22245 /*! SHIFTBUF - Shift Buffer */
22246 #define FLEXIO_SHIFTBUF_SHIFTBUF(x)              (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT)) & FLEXIO_SHIFTBUF_SHIFTBUF_MASK)
22247 /*! @} */
22248 
22249 /* The count of FLEXIO_SHIFTBUF */
22250 #define FLEXIO_SHIFTBUF_COUNT                    (8U)
22251 
22252 /*! @name SHIFTBUFBIS - Shifter Buffer Bit Swapped */
22253 /*! @{ */
22254 
22255 #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK      (0xFFFFFFFFU)
22256 #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT     (0U)
22257 /*! SHIFTBUFBIS - Shift Buffer */
22258 #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT)) & FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK)
22259 /*! @} */
22260 
22261 /* The count of FLEXIO_SHIFTBUFBIS */
22262 #define FLEXIO_SHIFTBUFBIS_COUNT                 (8U)
22263 
22264 /*! @name SHIFTBUFBYS - Shifter Buffer Byte Swapped */
22265 /*! @{ */
22266 
22267 #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK      (0xFFFFFFFFU)
22268 #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT     (0U)
22269 /*! SHIFTBUFBYS - Shift Buffer */
22270 #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT)) & FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK)
22271 /*! @} */
22272 
22273 /* The count of FLEXIO_SHIFTBUFBYS */
22274 #define FLEXIO_SHIFTBUFBYS_COUNT                 (8U)
22275 
22276 /*! @name SHIFTBUFBBS - Shifter Buffer Bit Byte Swapped */
22277 /*! @{ */
22278 
22279 #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK      (0xFFFFFFFFU)
22280 #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT     (0U)
22281 /*! SHIFTBUFBBS - Shift Buffer */
22282 #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT)) & FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK)
22283 /*! @} */
22284 
22285 /* The count of FLEXIO_SHIFTBUFBBS */
22286 #define FLEXIO_SHIFTBUFBBS_COUNT                 (8U)
22287 
22288 /*! @name TIMCTL - Timer Control */
22289 /*! @{ */
22290 
22291 #define FLEXIO_TIMCTL_TIMOD_MASK                 (0x7U)
22292 #define FLEXIO_TIMCTL_TIMOD_SHIFT                (0U)
22293 /*! TIMOD - Timer Mode
22294  *  0b000..Timer disabled
22295  *  0b001..Dual 8-bit counters baud mode
22296  *  0b010..Dual 8-bit counters PWM high mode
22297  *  0b011..Single 16-bit counter mode
22298  *  0b100..Single 16-bit counter disable mode
22299  *  0b101..Dual 8-bit counters word mode
22300  *  0b110..Dual 8-bit counters PWM low mode
22301  *  0b111..Single 16-bit input capture mode
22302  */
22303 #define FLEXIO_TIMCTL_TIMOD(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TIMOD_SHIFT)) & FLEXIO_TIMCTL_TIMOD_MASK)
22304 
22305 #define FLEXIO_TIMCTL_ONETIM_MASK                (0x20U)
22306 #define FLEXIO_TIMCTL_ONETIM_SHIFT               (5U)
22307 /*! ONETIM - Timer One Time Operation
22308  *  0b0..Generate the timer enable event as normal
22309  *  0b1..Block the timer enable event unless the timer status flag is clear
22310  */
22311 #define FLEXIO_TIMCTL_ONETIM(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_ONETIM_SHIFT)) & FLEXIO_TIMCTL_ONETIM_MASK)
22312 
22313 #define FLEXIO_TIMCTL_PININS_MASK                (0x40U)
22314 #define FLEXIO_TIMCTL_PININS_SHIFT               (6U)
22315 /*! PININS - Timer Pin Input Select
22316  *  0b0..PINSEL selects timer pin input and output
22317  *  0b1..PINSEL + 1 selects the timer pin input; timer pin output remains selected by PINSEL
22318  */
22319 #define FLEXIO_TIMCTL_PININS(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PININS_SHIFT)) & FLEXIO_TIMCTL_PININS_MASK)
22320 
22321 #define FLEXIO_TIMCTL_PINPOL_MASK                (0x80U)
22322 #define FLEXIO_TIMCTL_PINPOL_SHIFT               (7U)
22323 /*! PINPOL - Timer Pin Polarity
22324  *  0b0..Active high
22325  *  0b1..Active low
22326  */
22327 #define FLEXIO_TIMCTL_PINPOL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINPOL_SHIFT)) & FLEXIO_TIMCTL_PINPOL_MASK)
22328 
22329 #define FLEXIO_TIMCTL_PINSEL_MASK                (0x1F00U)
22330 #define FLEXIO_TIMCTL_PINSEL_SHIFT               (8U)
22331 /*! PINSEL - Timer Pin Select */
22332 #define FLEXIO_TIMCTL_PINSEL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINSEL_SHIFT)) & FLEXIO_TIMCTL_PINSEL_MASK)
22333 
22334 #define FLEXIO_TIMCTL_PINCFG_MASK                (0x30000U)
22335 #define FLEXIO_TIMCTL_PINCFG_SHIFT               (16U)
22336 /*! PINCFG - Timer Pin Configuration
22337  *  0b00..Timer pin output disabled
22338  *  0b01..Timer pin open-drain or bidirectional output enable
22339  *  0b10..Timer pin bidirectional output data
22340  *  0b11..Timer pin output
22341  */
22342 #define FLEXIO_TIMCTL_PINCFG(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINCFG_SHIFT)) & FLEXIO_TIMCTL_PINCFG_MASK)
22343 
22344 #define FLEXIO_TIMCTL_TRGSRC_MASK                (0x400000U)
22345 #define FLEXIO_TIMCTL_TRGSRC_SHIFT               (22U)
22346 /*! TRGSRC - Trigger Source
22347  *  0b0..External
22348  *  0b1..Internal
22349  */
22350 #define FLEXIO_TIMCTL_TRGSRC(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSRC_SHIFT)) & FLEXIO_TIMCTL_TRGSRC_MASK)
22351 
22352 #define FLEXIO_TIMCTL_TRGPOL_MASK                (0x800000U)
22353 #define FLEXIO_TIMCTL_TRGPOL_SHIFT               (23U)
22354 /*! TRGPOL - Trigger Polarity
22355  *  0b0..Active high
22356  *  0b1..Active low
22357  */
22358 #define FLEXIO_TIMCTL_TRGPOL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGPOL_SHIFT)) & FLEXIO_TIMCTL_TRGPOL_MASK)
22359 
22360 #define FLEXIO_TIMCTL_TRGSEL_MASK                (0x3F000000U)
22361 #define FLEXIO_TIMCTL_TRGSEL_SHIFT               (24U)
22362 /*! TRGSEL - Trigger Select */
22363 #define FLEXIO_TIMCTL_TRGSEL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSEL_SHIFT)) & FLEXIO_TIMCTL_TRGSEL_MASK)
22364 /*! @} */
22365 
22366 /* The count of FLEXIO_TIMCTL */
22367 #define FLEXIO_TIMCTL_COUNT                      (8U)
22368 
22369 /*! @name TIMCFG - Timer Configuration */
22370 /*! @{ */
22371 
22372 #define FLEXIO_TIMCFG_TSTART_MASK                (0x2U)
22373 #define FLEXIO_TIMCFG_TSTART_SHIFT               (1U)
22374 /*! TSTART - Timer Start
22375  *  0b0..Disabled
22376  *  0b1..Enabled
22377  */
22378 #define FLEXIO_TIMCFG_TSTART(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTART_SHIFT)) & FLEXIO_TIMCFG_TSTART_MASK)
22379 
22380 #define FLEXIO_TIMCFG_TSTOP_MASK                 (0x30U)
22381 #define FLEXIO_TIMCFG_TSTOP_SHIFT                (4U)
22382 /*! TSTOP - Timer Stop
22383  *  0b00..Disabled
22384  *  0b01..Enabled on timer compare
22385  *  0b10..Enabled on timer disable
22386  *  0b11..Enabled on timer compare and timer disable
22387  */
22388 #define FLEXIO_TIMCFG_TSTOP(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTOP_SHIFT)) & FLEXIO_TIMCFG_TSTOP_MASK)
22389 
22390 #define FLEXIO_TIMCFG_TIMENA_MASK                (0x700U)
22391 #define FLEXIO_TIMCFG_TIMENA_SHIFT               (8U)
22392 /*! TIMENA - Timer Enable
22393  *  0b000..Timer always enabled
22394  *  0b001..Timer enabled on timer n-1 enable
22395  *  0b010..Timer enabled on trigger high
22396  *  0b011..Timer enabled on trigger high and pin high
22397  *  0b100..Timer enabled on pin rising edge
22398  *  0b101..Timer enabled on pin rising edge and trigger high
22399  *  0b110..Timer enabled on trigger rising edge
22400  *  0b111..Timer enabled on trigger rising or falling edge
22401  */
22402 #define FLEXIO_TIMCFG_TIMENA(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMENA_SHIFT)) & FLEXIO_TIMCFG_TIMENA_MASK)
22403 
22404 #define FLEXIO_TIMCFG_TIMDIS_MASK                (0x7000U)
22405 #define FLEXIO_TIMCFG_TIMDIS_SHIFT               (12U)
22406 /*! TIMDIS - Timer Disable
22407  *  0b000..Timer never disabled
22408  *  0b001..Timer disabled on timer n-1 disable
22409  *  0b010..Timer disabled on timer compare (upper 8 bits match and decrement)
22410  *  0b011..Timer disabled on timer compare (upper 8 bits match and decrement) and trigger low
22411  *  0b100..Timer disabled on pin rising or falling edge
22412  *  0b101..Timer disabled on pin rising or falling edge provided trigger is high
22413  *  0b110..Timer disabled on trigger falling edge
22414  *  0b111..Reserved
22415  */
22416 #define FLEXIO_TIMCFG_TIMDIS(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDIS_SHIFT)) & FLEXIO_TIMCFG_TIMDIS_MASK)
22417 
22418 #define FLEXIO_TIMCFG_TIMRST_MASK                (0x70000U)
22419 #define FLEXIO_TIMCFG_TIMRST_SHIFT               (16U)
22420 /*! TIMRST - Timer Reset
22421  *  0b000..Never reset timer
22422  *  0b001..Timer reset on timer output high.
22423  *  0b010..Timer reset on timer pin equal to timer output
22424  *  0b011..Timer reset on timer trigger equal to timer output
22425  *  0b100..Timer reset on timer pin rising edge
22426  *  0b101..Reserved
22427  *  0b110..Timer reset on trigger rising edge
22428  *  0b111..Timer reset on trigger rising or falling edge
22429  */
22430 #define FLEXIO_TIMCFG_TIMRST(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMRST_SHIFT)) & FLEXIO_TIMCFG_TIMRST_MASK)
22431 
22432 #define FLEXIO_TIMCFG_TIMDEC_MASK                (0x700000U)
22433 #define FLEXIO_TIMCFG_TIMDEC_SHIFT               (20U)
22434 /*! TIMDEC - Timer Decrement
22435  *  0b000..Decrement counter on FLEXIO clock; shift clock equals timer output
22436  *  0b001..Decrement counter on trigger input (both edges); shift clock equals timer output
22437  *  0b010..Decrement counter on pin input (both edges); shift clock equals pin input
22438  *  0b011..Decrement counter on trigger input (both edges); shift clock equals trigger input
22439  *  0b100..Decrement counter on FLEXIO clock divided by 16; shift clock equals timer output
22440  *  0b101..Decrement counter on FLEXIO clock divided by 256; shift clock equals timer output
22441  *  0b110..Decrement counter on pin input (rising edge); shift clock equals pin input
22442  *  0b111..Decrement counter on trigger input (rising edge); shift clock equals trigger input
22443  */
22444 #define FLEXIO_TIMCFG_TIMDEC(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDEC_SHIFT)) & FLEXIO_TIMCFG_TIMDEC_MASK)
22445 
22446 #define FLEXIO_TIMCFG_TIMOUT_MASK                (0x3000000U)
22447 #define FLEXIO_TIMCFG_TIMOUT_SHIFT               (24U)
22448 /*! TIMOUT - Timer Output
22449  *  0b00..Logic one when enabled; not affected by timer reset
22450  *  0b01..Logic zero when enabled; not affected by timer reset
22451  *  0b10..Logic one when enabled and on timer reset
22452  *  0b11..Logic zero when enabled and on timer reset
22453  */
22454 #define FLEXIO_TIMCFG_TIMOUT(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMOUT_SHIFT)) & FLEXIO_TIMCFG_TIMOUT_MASK)
22455 /*! @} */
22456 
22457 /* The count of FLEXIO_TIMCFG */
22458 #define FLEXIO_TIMCFG_COUNT                      (8U)
22459 
22460 /*! @name TIMCMP - Timer Compare */
22461 /*! @{ */
22462 
22463 #define FLEXIO_TIMCMP_CMP_MASK                   (0xFFFFU)
22464 #define FLEXIO_TIMCMP_CMP_SHIFT                  (0U)
22465 /*! CMP - Timer Compare Value */
22466 #define FLEXIO_TIMCMP_CMP(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCMP_CMP_SHIFT)) & FLEXIO_TIMCMP_CMP_MASK)
22467 /*! @} */
22468 
22469 /* The count of FLEXIO_TIMCMP */
22470 #define FLEXIO_TIMCMP_COUNT                      (8U)
22471 
22472 /*! @name SHIFTBUFNBS - Shifter Buffer Nibble Byte Swapped */
22473 /*! @{ */
22474 
22475 #define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK      (0xFFFFFFFFU)
22476 #define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT     (0U)
22477 /*! SHIFTBUFNBS - Shift Buffer */
22478 #define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT)) & FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK)
22479 /*! @} */
22480 
22481 /* The count of FLEXIO_SHIFTBUFNBS */
22482 #define FLEXIO_SHIFTBUFNBS_COUNT                 (8U)
22483 
22484 /*! @name SHIFTBUFHWS - Shifter Buffer Halfword Swapped */
22485 /*! @{ */
22486 
22487 #define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK      (0xFFFFFFFFU)
22488 #define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT     (0U)
22489 /*! SHIFTBUFHWS - Shift Buffer */
22490 #define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT)) & FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK)
22491 /*! @} */
22492 
22493 /* The count of FLEXIO_SHIFTBUFHWS */
22494 #define FLEXIO_SHIFTBUFHWS_COUNT                 (8U)
22495 
22496 /*! @name SHIFTBUFNIS - Shifter Buffer Nibble Swapped */
22497 /*! @{ */
22498 
22499 #define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK      (0xFFFFFFFFU)
22500 #define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT     (0U)
22501 /*! SHIFTBUFNIS - Shift Buffer */
22502 #define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT)) & FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK)
22503 /*! @} */
22504 
22505 /* The count of FLEXIO_SHIFTBUFNIS */
22506 #define FLEXIO_SHIFTBUFNIS_COUNT                 (8U)
22507 
22508 /*! @name SHIFTBUFOES - Shifter Buffer Odd Even Swapped */
22509 /*! @{ */
22510 
22511 #define FLEXIO_SHIFTBUFOES_SHIFTBUFOES_MASK      (0xFFFFFFFFU)
22512 #define FLEXIO_SHIFTBUFOES_SHIFTBUFOES_SHIFT     (0U)
22513 /*! SHIFTBUFOES - Shift Buffer */
22514 #define FLEXIO_SHIFTBUFOES_SHIFTBUFOES(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFOES_SHIFTBUFOES_SHIFT)) & FLEXIO_SHIFTBUFOES_SHIFTBUFOES_MASK)
22515 /*! @} */
22516 
22517 /* The count of FLEXIO_SHIFTBUFOES */
22518 #define FLEXIO_SHIFTBUFOES_COUNT                 (8U)
22519 
22520 /*! @name SHIFTBUFEOS - Shifter Buffer Even Odd Swapped */
22521 /*! @{ */
22522 
22523 #define FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_MASK      (0xFFFFFFFFU)
22524 #define FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_SHIFT     (0U)
22525 /*! SHIFTBUFEOS - Shift Buffer */
22526 #define FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_SHIFT)) & FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_MASK)
22527 /*! @} */
22528 
22529 /* The count of FLEXIO_SHIFTBUFEOS */
22530 #define FLEXIO_SHIFTBUFEOS_COUNT                 (8U)
22531 
22532 /*! @name SHIFTBUFHBS - Shifter Buffer Halfword Byte Swapped */
22533 /*! @{ */
22534 
22535 #define FLEXIO_SHIFTBUFHBS_SHIFTBUFHBS_MASK      (0xFFFFFFFFU)
22536 #define FLEXIO_SHIFTBUFHBS_SHIFTBUFHBS_SHIFT     (0U)
22537 /*! SHIFTBUFHBS - Shift Buffer */
22538 #define FLEXIO_SHIFTBUFHBS_SHIFTBUFHBS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFHBS_SHIFTBUFHBS_SHIFT)) & FLEXIO_SHIFTBUFHBS_SHIFTBUFHBS_MASK)
22539 /*! @} */
22540 
22541 /* The count of FLEXIO_SHIFTBUFHBS */
22542 #define FLEXIO_SHIFTBUFHBS_COUNT                 (8U)
22543 
22544 
22545 /*!
22546  * @}
22547  */ /* end of group FLEXIO_Register_Masks */
22548 
22549 
22550 /* FLEXIO - Peripheral instance base addresses */
22551 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
22552   /** Peripheral FLEXIO0 base address */
22553   #define FLEXIO0_BASE                             (0x50105000u)
22554   /** Peripheral FLEXIO0 base address */
22555   #define FLEXIO0_BASE_NS                          (0x40105000u)
22556   /** Peripheral FLEXIO0 base pointer */
22557   #define FLEXIO0                                  ((FLEXIO_Type *)FLEXIO0_BASE)
22558   /** Peripheral FLEXIO0 base pointer */
22559   #define FLEXIO0_NS                               ((FLEXIO_Type *)FLEXIO0_BASE_NS)
22560   /** Array initializer of FLEXIO peripheral base addresses */
22561   #define FLEXIO_BASE_ADDRS                        { FLEXIO0_BASE }
22562   /** Array initializer of FLEXIO peripheral base pointers */
22563   #define FLEXIO_BASE_PTRS                         { FLEXIO0 }
22564   /** Array initializer of FLEXIO peripheral base addresses */
22565   #define FLEXIO_BASE_ADDRS_NS                     { FLEXIO0_BASE_NS }
22566   /** Array initializer of FLEXIO peripheral base pointers */
22567   #define FLEXIO_BASE_PTRS_NS                      { FLEXIO0_NS }
22568 #else
22569   /** Peripheral FLEXIO0 base address */
22570   #define FLEXIO0_BASE                             (0x40105000u)
22571   /** Peripheral FLEXIO0 base pointer */
22572   #define FLEXIO0                                  ((FLEXIO_Type *)FLEXIO0_BASE)
22573   /** Array initializer of FLEXIO peripheral base addresses */
22574   #define FLEXIO_BASE_ADDRS                        { FLEXIO0_BASE }
22575   /** Array initializer of FLEXIO peripheral base pointers */
22576   #define FLEXIO_BASE_PTRS                         { FLEXIO0 }
22577 #endif
22578 /** Interrupt vectors for the FLEXIO peripheral type */
22579 #define FLEXIO_IRQS                              { FLEXIO_IRQn }
22580 
22581 /*!
22582  * @}
22583  */ /* end of group FLEXIO_Peripheral_Access_Layer */
22584 
22585 
22586 /* ----------------------------------------------------------------------------
22587    -- FLEXSPI Peripheral Access Layer
22588    ---------------------------------------------------------------------------- */
22589 
22590 /*!
22591  * @addtogroup FLEXSPI_Peripheral_Access_Layer FLEXSPI Peripheral Access Layer
22592  * @{
22593  */
22594 
22595 /** FLEXSPI - Register Layout Typedef */
22596 typedef struct {
22597   __IO uint32_t MCR0;                              /**< Module Control 0, offset: 0x0 */
22598   __IO uint32_t MCR1;                              /**< Module Control 1, offset: 0x4 */
22599   __IO uint32_t MCR2;                              /**< Module Control 2, offset: 0x8 */
22600   __IO uint32_t AHBCR;                             /**< AHB Bus Control, offset: 0xC */
22601   __IO uint32_t INTEN;                             /**< Interrupt Enable, offset: 0x10 */
22602   __IO uint32_t INTR;                              /**< Interrupt, offset: 0x14 */
22603   __IO uint32_t LUTKEY;                            /**< LUT Key, offset: 0x18 */
22604   __IO uint32_t LUTCR;                             /**< LUT Control, offset: 0x1C */
22605   __IO uint32_t AHBRXBUFCR0[8];                    /**< AHB Receive Buffer 0 Control 0..AHB Receive Buffer 7 Control 0, array offset: 0x20, array step: 0x4 */
22606        uint8_t RESERVED_0[32];
22607   __IO uint32_t FLSHCR0[4];                        /**< Flash Control 0, array offset: 0x60, array step: 0x4 */
22608   __IO uint32_t FLSHCR1[4];                        /**< Flash Control 1, array offset: 0x70, array step: 0x4 */
22609   __IO uint32_t FLSHCR2[4];                        /**< Flash Control 2, array offset: 0x80, array step: 0x4 */
22610        uint8_t RESERVED_1[4];
22611   __IO uint32_t FLSHCR4;                           /**< Flash Control 4, offset: 0x94 */
22612        uint8_t RESERVED_2[8];
22613   __IO uint32_t IPCR0;                             /**< IP Control 0, offset: 0xA0 */
22614   __IO uint32_t IPCR1;                             /**< IP Control 1, offset: 0xA4 */
22615   __IO uint32_t IPCR2;                             /**< IP Control 2, offset: 0xA8 */
22616        uint8_t RESERVED_3[4];
22617   __O  uint32_t IPCMD;                             /**< IP Command, offset: 0xB0 */
22618   __IO uint32_t DLPR;                              /**< Data Learning Pattern, offset: 0xB4 */
22619   __IO uint32_t IPRXFCR;                           /**< IP Receive FIFO Control, offset: 0xB8 */
22620   __IO uint32_t IPTXFCR;                           /**< IP Transmit FIFO Control, offset: 0xBC */
22621   __IO uint32_t DLLCR[2];                          /**< DLL Control 0, array offset: 0xC0, array step: 0x4 */
22622        uint8_t RESERVED_4[24];
22623   __I  uint32_t STS0;                              /**< Status 0, offset: 0xE0 */
22624   __I  uint32_t STS1;                              /**< Status 1, offset: 0xE4 */
22625   __I  uint32_t STS2;                              /**< Status 2, offset: 0xE8 */
22626   __I  uint32_t AHBSPNDSTS;                        /**< AHB Suspend Status, offset: 0xEC */
22627   __I  uint32_t IPRXFSTS;                          /**< IP Receive FIFO Status, offset: 0xF0 */
22628   __I  uint32_t IPTXFSTS;                          /**< IP Transmit FIFO Status, offset: 0xF4 */
22629        uint8_t RESERVED_5[8];
22630   __I  uint32_t RFDR[32];                          /**< IP Receive FIFO Data 0..IP Receive FIFO Data 31, array offset: 0x100, array step: 0x4 */
22631   __O  uint32_t TFDR[32];                          /**< IP TX FIFO Data 0..IP TX FIFO Data 31, array offset: 0x180, array step: 0x4 */
22632   __IO uint32_t LUT[64];                           /**< Lookup Table 0..Lookup Table 63, array offset: 0x200, array step: 0x4 */
22633        uint8_t RESERVED_6[288];
22634   __IO uint32_t HADDRSTART;                        /**< HADDR REMAP Start Address, offset: 0x420 */
22635   __IO uint32_t HADDREND;                          /**< HADDR REMAP END ADDR, offset: 0x424 */
22636   __IO uint32_t HADDROFFSET;                       /**< HADDR Remap Offset, offset: 0x428 */
22637   __IO uint32_t IPEDCTRL;                          /**< IPED Function Control, offset: 0x42C */
22638   __IO uint32_t IPSNSZSTART0;                      /**< IPS Nonsecure Region 0 Start Address, offset: 0x430 */
22639   __IO uint32_t IPSNSZEND0;                        /**< IPS Nonsecure Region 0 End Address, offset: 0x434 */
22640   __IO uint32_t IPSNSZSTART1;                      /**< IPS Nonsecure Region 1 Start Address, offset: 0x438 */
22641   __IO uint32_t IPSNSZEND1;                        /**< IPS Nonsecure Region 1 End Address, offset: 0x43C */
22642   __IO uint32_t AHBBUFREGIONSTART0;                /**< Receive Buffer Start Address of Region 0, offset: 0x440 */
22643   __IO uint32_t AHBBUFREGIONEND0;                  /**< Receive Buffer Region 0 End Address, offset: 0x444 */
22644   __IO uint32_t AHBBUFREGIONSTART1;                /**< Receive Buffer Start Address of Region 1, offset: 0x448 */
22645   __IO uint32_t AHBBUFREGIONEND1;                  /**< Receive Buffer Region 1 End Address, offset: 0x44C */
22646   __IO uint32_t AHBBUFREGIONSTART2;                /**< Receive Buffer Start Address of Region 2, offset: 0x450 */
22647   __IO uint32_t AHBBUFREGIONEND2;                  /**< Receive Buffer Region 2 End Address, offset: 0x454 */
22648   __IO uint32_t AHBBUFREGIONSTART3;                /**< Receive Buffer Start Address of Region 3, offset: 0x458 */
22649   __IO uint32_t AHBBUFREGIONEND3;                  /**< Receive Buffer Region 3 End Address, offset: 0x45C */
22650        uint8_t RESERVED_7[160];
22651   __IO uint32_t IPEDCTXCTRL[2];                    /**< IPED context control 0..IPED context control 1, array offset: 0x500, array step: 0x4 */
22652        uint8_t RESERVED_8[24];
22653   __IO uint32_t IPEDCTX0IV0;                       /**< IPED Context0 IV0, offset: 0x520 */
22654   __IO uint32_t IPEDCTX0IV1;                       /**< IPED Context0 IV1, offset: 0x524 */
22655   __IO uint32_t IPEDCTX0START;                     /**< Start Address of Region, offset: 0x528 */
22656   __IO uint32_t IPEDCTX0END;                       /**< End Address of Region, offset: 0x52C */
22657   __IO uint32_t IPEDCTX0AAD0;                      /**< IPED Context0 Additional Authenticated Data0, offset: 0x530 */
22658   __IO uint32_t IPEDCTX0AAD1;                      /**< IPED Context0 Additional Authenticated Data1, offset: 0x534 */
22659        uint8_t RESERVED_9[8];
22660   __IO uint32_t IPEDCTX1IV0;                       /**< IPED Context1 IV0, offset: 0x540 */
22661   __IO uint32_t IPEDCTX1IV1;                       /**< IPED Context1 IV1, offset: 0x544 */
22662   __IO uint32_t IPEDCTX1START;                     /**< Start Address of Region, offset: 0x548 */
22663   __IO uint32_t IPEDCTX1END;                       /**< End Address of Region, offset: 0x54C */
22664   __IO uint32_t IPEDCTX1AAD0;                      /**< IPED Context1 Additional Authenticated Data0, offset: 0x550 */
22665   __IO uint32_t IPEDCTX1AAD1;                      /**< IPED Context1 Additional Authenticated Data1, offset: 0x554 */
22666        uint8_t RESERVED_10[8];
22667   __IO uint32_t IPEDCTX2IV0;                       /**< IPED Context2 IV0, offset: 0x560 */
22668   __IO uint32_t IPEDCTX2IV1;                       /**< IPED Context2 IV1, offset: 0x564 */
22669   __IO uint32_t IPEDCTX2START;                     /**< Start Address of Region, offset: 0x568 */
22670   __IO uint32_t IPEDCTX2END;                       /**< End Address of Region, offset: 0x56C */
22671   __IO uint32_t IPEDCTX2AAD0;                      /**< IPED Context2 Additional Authenticated Data0, offset: 0x570 */
22672   __IO uint32_t IPEDCTX2AAD1;                      /**< IPED Context2 Additional Authenticated Data1, offset: 0x574 */
22673        uint8_t RESERVED_11[8];
22674   __IO uint32_t IPEDCTX3IV0;                       /**< IPED Context3 IV0, offset: 0x580 */
22675   __IO uint32_t IPEDCTX3IV1;                       /**< IPED Context3 IV1, offset: 0x584 */
22676   __IO uint32_t IPEDCTX3START;                     /**< Start Address of Region, offset: 0x588 */
22677   __IO uint32_t IPEDCTX3END;                       /**< End Address of Region, offset: 0x58C */
22678   __IO uint32_t IPEDCTX3AAD0;                      /**< IPED Context3 Additional Authenticated Data0, offset: 0x590 */
22679   __IO uint32_t IPEDCTX3AAD1;                      /**< IPED Context3 Additional Authenticated Data1, offset: 0x594 */
22680        uint8_t RESERVED_12[8];
22681   __IO uint32_t IPEDCTX4IV0;                       /**< IPED Context4 IV0, offset: 0x5A0 */
22682   __IO uint32_t IPEDCTX4IV1;                       /**< IPED Context4 IV1, offset: 0x5A4 */
22683   __IO uint32_t IPEDCTX4START;                     /**< Start Address of Region, offset: 0x5A8 */
22684   __IO uint32_t IPEDCTX4END;                       /**< End Address of Region, offset: 0x5AC */
22685   __IO uint32_t IPEDCTX4AAD0;                      /**< IPED Context4 Additional Authenticated Data0, offset: 0x5B0 */
22686   __IO uint32_t IPEDCTX4AAD1;                      /**< IPED Context4 Additional Authenticated Data1, offset: 0x5B4 */
22687        uint8_t RESERVED_13[8];
22688   __IO uint32_t IPEDCTX5IV0;                       /**< IPED Context5 IV0, offset: 0x5C0 */
22689   __IO uint32_t IPEDCTX5IV1;                       /**< IPED Context5 IV1, offset: 0x5C4 */
22690   __IO uint32_t IPEDCTX5START;                     /**< Start Address of Region, offset: 0x5C8 */
22691   __IO uint32_t IPEDCTX5END;                       /**< End Address of Region, offset: 0x5CC */
22692   __IO uint32_t IPEDCTX5AAD0;                      /**< IPED Context5 Additional Authenticated Data0, offset: 0x5D0 */
22693   __IO uint32_t IPEDCTX5AAD1;                      /**< IPED Context5 Additional Authenticated Data1, offset: 0x5D4 */
22694        uint8_t RESERVED_14[8];
22695   __IO uint32_t IPEDCTX6IV0;                       /**< IPED Context6 IV0, offset: 0x5E0 */
22696   __IO uint32_t IPEDCTX6IV1;                       /**< IPED Context6 IV1, offset: 0x5E4 */
22697   __IO uint32_t IPEDCTX6START;                     /**< Start Address of Region, offset: 0x5E8 */
22698   __IO uint32_t IPEDCTX6END;                       /**< End Address of Region, offset: 0x5EC */
22699   __IO uint32_t IPEDCTX6AAD0;                      /**< IPED Context6 Additional Authenticated Data0, offset: 0x5F0 */
22700   __IO uint32_t IPEDCTX6AAD1;                      /**< IPED Context6 Additional Authenticated Data1, offset: 0x5F4 */
22701 } FLEXSPI_Type;
22702 
22703 /* ----------------------------------------------------------------------------
22704    -- FLEXSPI Register Masks
22705    ---------------------------------------------------------------------------- */
22706 
22707 /*!
22708  * @addtogroup FLEXSPI_Register_Masks FLEXSPI Register Masks
22709  * @{
22710  */
22711 
22712 /*! @name MCR0 - Module Control 0 */
22713 /*! @{ */
22714 
22715 #define FLEXSPI_MCR0_SWRESET_MASK                (0x1U)
22716 #define FLEXSPI_MCR0_SWRESET_SHIFT               (0U)
22717 /*! SWRESET - Software Reset
22718  *  0b0..No impact
22719  *  0b1..Software reset
22720  */
22721 #define FLEXSPI_MCR0_SWRESET(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SWRESET_SHIFT)) & FLEXSPI_MCR0_SWRESET_MASK)
22722 
22723 #define FLEXSPI_MCR0_MDIS_MASK                   (0x2U)
22724 #define FLEXSPI_MCR0_MDIS_SHIFT                  (1U)
22725 /*! MDIS - Module Disable
22726  *  0b0..No impact
22727  *  0b1..Module disable
22728  */
22729 #define FLEXSPI_MCR0_MDIS(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_MDIS_SHIFT)) & FLEXSPI_MCR0_MDIS_MASK)
22730 
22731 #define FLEXSPI_MCR0_RXCLKSRC_MASK               (0x30U)
22732 #define FLEXSPI_MCR0_RXCLKSRC_SHIFT              (4U)
22733 /*! RXCLKSRC - Sample Clock Source for Flash Reading
22734  *  0b00..Dummy Read strobe that FlexSPI generates, looped back internally
22735  *  0b01..Dummy Read strobe that FlexSPI generates, looped back from DQS pad
22736  *  0b10..SCLK output clock and looped back from SCLK pad
22737  *  0b11..Flash-memory-provided read strobe and input from DQS pad
22738  */
22739 #define FLEXSPI_MCR0_RXCLKSRC(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_RXCLKSRC_SHIFT)) & FLEXSPI_MCR0_RXCLKSRC_MASK)
22740 
22741 #define FLEXSPI_MCR0_ARDFEN_MASK                 (0x40U)
22742 #define FLEXSPI_MCR0_ARDFEN_SHIFT                (6U)
22743 /*! ARDFEN - AHB Read Access to IP Receive FIFO Enable
22744  *  0b0..AHB read access disabled. IP bus reads IP receive FIFO. AHB Bus read access to IP receive FIFO memory space produces bus error.
22745  *  0b1..AHB read access enabled. AHB bus reads IP receive FIFO. IP Bus read access to IP receive FIFO memory
22746  *       space returns data zero and causes no bus error.
22747  */
22748 #define FLEXSPI_MCR0_ARDFEN(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ARDFEN_SHIFT)) & FLEXSPI_MCR0_ARDFEN_MASK)
22749 
22750 #define FLEXSPI_MCR0_ATDFEN_MASK                 (0x80U)
22751 #define FLEXSPI_MCR0_ATDFEN_SHIFT                (7U)
22752 /*! ATDFEN - AHB Write Access to IP Transmit FIFO Enable
22753  *  0b0..AHB write access disabled. IP bus writes to IP transmit FIFO. AHB bus write access to IP transmit FIFO memory space produces bus error.
22754  *  0b1..AHB write access enabled. AHB bus writes to IP transmit FIFO. IP Bus write access to IP transmit FIFO
22755  *       memory space is ignored and causes no bus error.
22756  */
22757 #define FLEXSPI_MCR0_ATDFEN(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ATDFEN_SHIFT)) & FLEXSPI_MCR0_ATDFEN_MASK)
22758 
22759 #define FLEXSPI_MCR0_SERCLKDIV_MASK              (0x700U)
22760 #define FLEXSPI_MCR0_SERCLKDIV_SHIFT             (8U)
22761 /*! SERCLKDIV - Serial Root Clock Divider
22762  *  0b000..Divided by 1
22763  *  0b001..Divided by 2
22764  *  0b010..Divided by 3
22765  *  0b011..Divided by 4
22766  *  0b100..Divided by 5
22767  *  0b101..Divided by 6
22768  *  0b110..Divided by 7
22769  *  0b111..Divided by 8
22770  */
22771 #define FLEXSPI_MCR0_SERCLKDIV(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SERCLKDIV_SHIFT)) & FLEXSPI_MCR0_SERCLKDIV_MASK)
22772 
22773 #define FLEXSPI_MCR0_HSEN_MASK                   (0x800U)
22774 #define FLEXSPI_MCR0_HSEN_SHIFT                  (11U)
22775 /*! HSEN - Half Speed Serial Flash Memory Access Enable
22776  *  0b0..Disable
22777  *  0b1..Enable
22778  */
22779 #define FLEXSPI_MCR0_HSEN(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_HSEN_SHIFT)) & FLEXSPI_MCR0_HSEN_MASK)
22780 
22781 #define FLEXSPI_MCR0_DOZEEN_MASK                 (0x1000U)
22782 #define FLEXSPI_MCR0_DOZEEN_SHIFT                (12U)
22783 /*! DOZEEN - Doze Mode Enable
22784  *  0b0..Disable
22785  *  0b1..Enable
22786  */
22787 #define FLEXSPI_MCR0_DOZEEN(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_DOZEEN_SHIFT)) & FLEXSPI_MCR0_DOZEEN_MASK)
22788 
22789 #define FLEXSPI_MCR0_COMBINATIONEN_MASK          (0x2000U)
22790 #define FLEXSPI_MCR0_COMBINATIONEN_SHIFT         (13U)
22791 /*! COMBINATIONEN - Combination Mode Enable
22792  *  0b0..Disable
22793  *  0b1..Enable
22794  */
22795 #define FLEXSPI_MCR0_COMBINATIONEN(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_COMBINATIONEN_SHIFT)) & FLEXSPI_MCR0_COMBINATIONEN_MASK)
22796 
22797 #define FLEXSPI_MCR0_SCKFREERUNEN_MASK           (0x4000U)
22798 #define FLEXSPI_MCR0_SCKFREERUNEN_SHIFT          (14U)
22799 /*! SCKFREERUNEN - SCLK Free-running Enable
22800  *  0b0..Disable
22801  *  0b1..Enable
22802  */
22803 #define FLEXSPI_MCR0_SCKFREERUNEN(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SCKFREERUNEN_SHIFT)) & FLEXSPI_MCR0_SCKFREERUNEN_MASK)
22804 
22805 #define FLEXSPI_MCR0_LEARNEN_MASK                (0x8000U)
22806 #define FLEXSPI_MCR0_LEARNEN_SHIFT               (15U)
22807 /*! LEARNEN - Data Learning Enable
22808  *  0b0..Disable
22809  *  0b1..Enable
22810  */
22811 #define FLEXSPI_MCR0_LEARNEN(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_LEARNEN_SHIFT)) & FLEXSPI_MCR0_LEARNEN_MASK)
22812 
22813 #define FLEXSPI_MCR0_IPGRANTWAIT_MASK            (0xFF0000U)
22814 #define FLEXSPI_MCR0_IPGRANTWAIT_SHIFT           (16U)
22815 /*! IPGRANTWAIT - Timeout Wait Cycle for IP Command Grant */
22816 #define FLEXSPI_MCR0_IPGRANTWAIT(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_IPGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_IPGRANTWAIT_MASK)
22817 
22818 #define FLEXSPI_MCR0_AHBGRANTWAIT_MASK           (0xFF000000U)
22819 #define FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT          (24U)
22820 /*! AHBGRANTWAIT - Timeouts Wait Cycle for AHB command Grant */
22821 #define FLEXSPI_MCR0_AHBGRANTWAIT(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_AHBGRANTWAIT_MASK)
22822 /*! @} */
22823 
22824 /*! @name MCR1 - Module Control 1 */
22825 /*! @{ */
22826 
22827 #define FLEXSPI_MCR1_AHBBUSWAIT_MASK             (0xFFFFU)
22828 #define FLEXSPI_MCR1_AHBBUSWAIT_SHIFT            (0U)
22829 /*! AHBBUSWAIT - AHB Bus Wait */
22830 #define FLEXSPI_MCR1_AHBBUSWAIT(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_AHBBUSWAIT_SHIFT)) & FLEXSPI_MCR1_AHBBUSWAIT_MASK)
22831 
22832 #define FLEXSPI_MCR1_SEQWAIT_MASK                (0xFFFF0000U)
22833 #define FLEXSPI_MCR1_SEQWAIT_SHIFT               (16U)
22834 /*! SEQWAIT - Command Sequence Wait */
22835 #define FLEXSPI_MCR1_SEQWAIT(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_SEQWAIT_SHIFT)) & FLEXSPI_MCR1_SEQWAIT_MASK)
22836 /*! @} */
22837 
22838 /*! @name MCR2 - Module Control 2 */
22839 /*! @{ */
22840 
22841 #define FLEXSPI_MCR2_CLRAHBBUFOPT_MASK           (0x800U)
22842 #define FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT          (11U)
22843 /*! CLRAHBBUFOPT - Clear AHB Buffer
22844  *  0b0..Not cleared automatically
22845  *  0b1..Cleared automatically
22846  */
22847 #define FLEXSPI_MCR2_CLRAHBBUFOPT(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT)) & FLEXSPI_MCR2_CLRAHBBUFOPT_MASK)
22848 
22849 #define FLEXSPI_MCR2_CLRLEARNPHASE_MASK          (0x4000U)
22850 #define FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT         (14U)
22851 /*! CLRLEARNPHASE - Clear Learn Phase Selection
22852  *  0b0..No impact
22853  *  0b1..Reset sample clock phase selection to 0
22854  */
22855 #define FLEXSPI_MCR2_CLRLEARNPHASE(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT)) & FLEXSPI_MCR2_CLRLEARNPHASE_MASK)
22856 
22857 #define FLEXSPI_MCR2_SAMEDEVICEEN_MASK           (0x8000U)
22858 #define FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT          (15U)
22859 /*! SAMEDEVICEEN - Same Device Enable
22860  *  0b0..In Individual mode, FLSHA1CRx and FLSHA2CRx, FLSHB1CRx and FLSHB2CRx settings are applied to Flash A1,
22861  *       A2, B1, B2 separately. In Parallel mode, FLSHA1CRx register setting is applied to Flash A1 and B1, FLSHA2CRx
22862  *       register setting is applied to Flash A2 and B2. FLSHB1CRx and FLSHB2CRx register settings are ignored.
22863  *  0b1..FLSHA1CR0, FLSHA1CR1, and FLSHA1CR2 register settings are applied to Flash A1, A2, B1, B2. FLSHA2CRx,
22864  *       FLSHB1CRx, and FLSHB2CRx settings are ignored.
22865  */
22866 #define FLEXSPI_MCR2_SAMEDEVICEEN(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT)) & FLEXSPI_MCR2_SAMEDEVICEEN_MASK)
22867 
22868 #define FLEXSPI_MCR2_SCKBDIFFOPT_MASK            (0x80000U)
22869 #define FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT           (19U)
22870 /*! SCKBDIFFOPT - SCLK Port B Differential Output
22871  *  0b1..Use B_SCLK pad as port A SCLK inverted clock output (Differential clock to A_SCLK). Port B flash memory access is not available.
22872  *  0b0..Use B_SCLK pad as port B SCLK clock output. Port B flash memory access is available.
22873  */
22874 #define FLEXSPI_MCR2_SCKBDIFFOPT(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT)) & FLEXSPI_MCR2_SCKBDIFFOPT_MASK)
22875 
22876 #define FLEXSPI_MCR2_RXCLKSRC_B_MASK             (0x600000U)
22877 #define FLEXSPI_MCR2_RXCLKSRC_B_SHIFT            (21U)
22878 /*! RXCLKSRC_B - Port B Receiver Clock Source
22879  *  0b00..Dummy read strobe that FlexSPI generates, looped back internally.
22880  *  0b01..Dummy read strobe that FlexSPI generates, looped back from DQS pad.
22881  *  0b10..SCLK output clock and looped back from SCLK pad
22882  *  0b11..Flash-memory-provided read strobe and input from DQS pad
22883  */
22884 #define FLEXSPI_MCR2_RXCLKSRC_B(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_RXCLKSRC_B_SHIFT)) & FLEXSPI_MCR2_RXCLKSRC_B_MASK)
22885 
22886 #define FLEXSPI_MCR2_RX_CLK_SRC_DIFF_MASK        (0x800000U)
22887 #define FLEXSPI_MCR2_RX_CLK_SRC_DIFF_SHIFT       (23U)
22888 /*! RX_CLK_SRC_DIFF - Sample Clock Source Different
22889  *  0b0..Use MCR0[RXCLKSRC] for Port A and Port B. MCR2[RXCLKSRC_B] is ignored and MCR0[RXCLKSRC] selects the
22890  *       Sample Clock source for Flash Reading of both ports A and B.
22891  *  0b1..Use MCR0[RXCLKSRC] for Port A, and MCR2[RXCLKSRC_B] for Port B. MCR0[RXCLKSRC] selects the Sample Clock
22892  *       source for Flash Reading of port A (A_SCLK) and MCR2[RXCLKSRC_B] selects the Sample Clock source for Flash
22893  *       Reading of port B (B_SCLK).
22894  */
22895 #define FLEXSPI_MCR2_RX_CLK_SRC_DIFF(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_RX_CLK_SRC_DIFF_SHIFT)) & FLEXSPI_MCR2_RX_CLK_SRC_DIFF_MASK)
22896 
22897 #define FLEXSPI_MCR2_RESUMEWAIT_MASK             (0xFF000000U)
22898 #define FLEXSPI_MCR2_RESUMEWAIT_SHIFT            (24U)
22899 /*! RESUMEWAIT - Resume Wait Duration */
22900 #define FLEXSPI_MCR2_RESUMEWAIT(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_RESUMEWAIT_SHIFT)) & FLEXSPI_MCR2_RESUMEWAIT_MASK)
22901 /*! @} */
22902 
22903 /*! @name AHBCR - AHB Bus Control */
22904 /*! @{ */
22905 
22906 #define FLEXSPI_AHBCR_APAREN_MASK                (0x1U)
22907 #define FLEXSPI_AHBCR_APAREN_SHIFT               (0U)
22908 /*! APAREN - AHB Parallel Mode Enable
22909  *  0b0..Flash is accessed in Individual mode.
22910  *  0b1..Flash is accessed in Parallel mode.
22911  */
22912 #define FLEXSPI_AHBCR_APAREN(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_APAREN_SHIFT)) & FLEXSPI_AHBCR_APAREN_MASK)
22913 
22914 #define FLEXSPI_AHBCR_CLRAHBRXBUF_MASK           (0x2U)
22915 #define FLEXSPI_AHBCR_CLRAHBRXBUF_SHIFT          (1U)
22916 /*! CLRAHBRXBUF - Clear AHB Receive Buffer
22917  *  0b0..No impact.
22918  *  0b1..Enable clear operation.
22919  */
22920 #define FLEXSPI_AHBCR_CLRAHBRXBUF(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CLRAHBRXBUF_SHIFT)) & FLEXSPI_AHBCR_CLRAHBRXBUF_MASK)
22921 
22922 #define FLEXSPI_AHBCR_CLRAHBTXBUF_MASK           (0x4U)
22923 #define FLEXSPI_AHBCR_CLRAHBTXBUF_SHIFT          (2U)
22924 /*! CLRAHBTXBUF - Clear AHB Transmit Buffer
22925  *  0b0..No impact.
22926  *  0b1..Enable clear operation.
22927  */
22928 #define FLEXSPI_AHBCR_CLRAHBTXBUF(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CLRAHBTXBUF_SHIFT)) & FLEXSPI_AHBCR_CLRAHBTXBUF_MASK)
22929 
22930 #define FLEXSPI_AHBCR_CACHABLEEN_MASK            (0x8U)
22931 #define FLEXSPI_AHBCR_CACHABLEEN_SHIFT           (3U)
22932 /*! CACHABLEEN - Cacheable Read Access Enable
22933  *  0b0..Disabled. When an AHB bus cacheable read access occurs, FlexSPI does not check whether it hit the AHB transmit buffer.
22934  *  0b1..Enabled. When an AHB bus cacheable read access occurs, FlexSPI first checks whether the access hit the AHB transmit buffer.
22935  */
22936 #define FLEXSPI_AHBCR_CACHABLEEN(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CACHABLEEN_SHIFT)) & FLEXSPI_AHBCR_CACHABLEEN_MASK)
22937 
22938 #define FLEXSPI_AHBCR_BUFFERABLEEN_MASK          (0x10U)
22939 #define FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT         (4U)
22940 /*! BUFFERABLEEN - Bufferable Write Access Enable
22941  *  0b0..Disabled. For all AHB write accesses (bufferable or nonbufferable), FlexSPI returns AHB Bus Ready after
22942  *       transmitting all data and finishing command.
22943  *  0b1..Enabled. For AHB bufferable write access, FlexSPI returns AHB Bus Ready when the arbitrator grants the
22944  *       AHB command. FlexSPI does not wait for the AHB command to finish.
22945  */
22946 #define FLEXSPI_AHBCR_BUFFERABLEEN(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT)) & FLEXSPI_AHBCR_BUFFERABLEEN_MASK)
22947 
22948 #define FLEXSPI_AHBCR_PREFETCHEN_MASK            (0x20U)
22949 #define FLEXSPI_AHBCR_PREFETCHEN_SHIFT           (5U)
22950 /*! PREFETCHEN - AHB Read Prefetch Enable
22951  *  0b0..Disable
22952  *  0b1..Enable
22953  */
22954 #define FLEXSPI_AHBCR_PREFETCHEN(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_PREFETCHEN_SHIFT)) & FLEXSPI_AHBCR_PREFETCHEN_MASK)
22955 
22956 #define FLEXSPI_AHBCR_READADDROPT_MASK           (0x40U)
22957 #define FLEXSPI_AHBCR_READADDROPT_SHIFT          (6U)
22958 /*! READADDROPT - AHB Read Address Option
22959  *  0b0..AHB read burst start address alignment is limited when flash memory is accessed in parallel mode or flash is word-addressable.
22960  *  0b1..AHB read burst start address alignment is not limited. FlexSPI fetches more data than the AHB burst requires for address alignment.
22961  */
22962 #define FLEXSPI_AHBCR_READADDROPT(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_READADDROPT_SHIFT)) & FLEXSPI_AHBCR_READADDROPT_MASK)
22963 
22964 #define FLEXSPI_AHBCR_RESUMEDISABLE_MASK         (0x80U)
22965 #define FLEXSPI_AHBCR_RESUMEDISABLE_SHIFT        (7U)
22966 /*! RESUMEDISABLE - AHB Read Resume Disable
22967  *  0b0..Suspended AHB read prefetch resumes when AHB is IDLE.
22968  *  0b1..Suspended AHB read prefetch does not resume once aborted,
22969  */
22970 #define FLEXSPI_AHBCR_RESUMEDISABLE(x)           (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_RESUMEDISABLE_SHIFT)) & FLEXSPI_AHBCR_RESUMEDISABLE_MASK)
22971 
22972 #define FLEXSPI_AHBCR_READSZALIGN_MASK           (0x400U)
22973 #define FLEXSPI_AHBCR_READSZALIGN_SHIFT          (10U)
22974 /*! READSZALIGN - AHB Read Size Alignment
22975  *  0b0..Register settings such as PREFETCH_EN determine AHB read size.
22976  *  0b1..AHB read size to up size to 8 bytes aligned, no prefetching
22977  */
22978 #define FLEXSPI_AHBCR_READSZALIGN(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_READSZALIGN_SHIFT)) & FLEXSPI_AHBCR_READSZALIGN_MASK)
22979 
22980 #define FLEXSPI_AHBCR_ALIGNMENT_MASK             (0x300000U)
22981 #define FLEXSPI_AHBCR_ALIGNMENT_SHIFT            (20U)
22982 /*! ALIGNMENT - AHB Boundary Alignment
22983  *  0b00..No limit
22984  *  0b01..1 KB
22985  *  0b10..512 bytes
22986  *  0b11..256 bytes
22987  */
22988 #define FLEXSPI_AHBCR_ALIGNMENT(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_ALIGNMENT_SHIFT)) & FLEXSPI_AHBCR_ALIGNMENT_MASK)
22989 
22990 #define FLEXSPI_AHBCR_AFLASHBASE_MASK            (0xE0000000U)
22991 #define FLEXSPI_AHBCR_AFLASHBASE_SHIFT           (29U)
22992 /*! AFLASHBASE - AHB Memory-Mapped Flash Base Address */
22993 #define FLEXSPI_AHBCR_AFLASHBASE(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_AFLASHBASE_SHIFT)) & FLEXSPI_AHBCR_AFLASHBASE_MASK)
22994 /*! @} */
22995 
22996 /*! @name INTEN - Interrupt Enable */
22997 /*! @{ */
22998 
22999 #define FLEXSPI_INTEN_IPCMDDONEEN_MASK           (0x1U)
23000 #define FLEXSPI_INTEN_IPCMDDONEEN_SHIFT          (0U)
23001 /*! IPCMDDONEEN - IP-Triggered Command Sequences Execution Finished Interrupt Enable
23002  *  0b0..Disable interrupt or no impact
23003  *  0b1..Enable interrupt
23004  */
23005 #define FLEXSPI_INTEN_IPCMDDONEEN(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDDONEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDDONEEN_MASK)
23006 
23007 #define FLEXSPI_INTEN_IPCMDGEEN_MASK             (0x2U)
23008 #define FLEXSPI_INTEN_IPCMDGEEN_SHIFT            (1U)
23009 /*! IPCMDGEEN - IP-Triggered Command Sequences Grant Timeout Interrupt Enable
23010  *  0b0..Disable interrupt or no impact
23011  *  0b1..Enable interrupt
23012  */
23013 #define FLEXSPI_INTEN_IPCMDGEEN(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDGEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDGEEN_MASK)
23014 
23015 #define FLEXSPI_INTEN_AHBCMDGEEN_MASK            (0x4U)
23016 #define FLEXSPI_INTEN_AHBCMDGEEN_SHIFT           (2U)
23017 /*! AHBCMDGEEN - AHB-Triggered Command Sequences Grant Timeout Interrupt Enable.
23018  *  0b0..Disable interrupt or no impact
23019  *  0b1..Enable interrupt
23020  */
23021 #define FLEXSPI_INTEN_AHBCMDGEEN(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDGEEN_SHIFT)) & FLEXSPI_INTEN_AHBCMDGEEN_MASK)
23022 
23023 #define FLEXSPI_INTEN_IPCMDERREN_MASK            (0x8U)
23024 #define FLEXSPI_INTEN_IPCMDERREN_SHIFT           (3U)
23025 /*! IPCMDERREN - IP-Triggered Command Sequences Error Detected Interrupt Enable
23026  *  0b0..Disable interrupt or no impact
23027  *  0b1..Enable interrupt
23028  */
23029 #define FLEXSPI_INTEN_IPCMDERREN(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDERREN_SHIFT)) & FLEXSPI_INTEN_IPCMDERREN_MASK)
23030 
23031 #define FLEXSPI_INTEN_AHBCMDERREN_MASK           (0x10U)
23032 #define FLEXSPI_INTEN_AHBCMDERREN_SHIFT          (4U)
23033 /*! AHBCMDERREN - AHB-Triggered Command Sequences Error Detected Interrupt Enable
23034  *  0b0..Disable interrupt or no impact
23035  *  0b1..Enable interrupt
23036  */
23037 #define FLEXSPI_INTEN_AHBCMDERREN(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDERREN_SHIFT)) & FLEXSPI_INTEN_AHBCMDERREN_MASK)
23038 
23039 #define FLEXSPI_INTEN_IPRXWAEN_MASK              (0x20U)
23040 #define FLEXSPI_INTEN_IPRXWAEN_SHIFT             (5U)
23041 /*! IPRXWAEN - IP Receive FIFO Watermark Available Interrupt Enable
23042  *  0b0..Disable interrupt or no impact
23043  *  0b1..Enable interrupt
23044  */
23045 #define FLEXSPI_INTEN_IPRXWAEN(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPRXWAEN_SHIFT)) & FLEXSPI_INTEN_IPRXWAEN_MASK)
23046 
23047 #define FLEXSPI_INTEN_IPTXWEEN_MASK              (0x40U)
23048 #define FLEXSPI_INTEN_IPTXWEEN_SHIFT             (6U)
23049 /*! IPTXWEEN - IP Transmit FIFO Watermark Empty Interrupt Enable
23050  *  0b0..Disable interrupt or no impact
23051  *  0b1..Enable interrupt
23052  */
23053 #define FLEXSPI_INTEN_IPTXWEEN(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPTXWEEN_SHIFT)) & FLEXSPI_INTEN_IPTXWEEN_MASK)
23054 
23055 #define FLEXSPI_INTEN_DATALEARNFAILEN_MASK       (0x80U)
23056 #define FLEXSPI_INTEN_DATALEARNFAILEN_SHIFT      (7U)
23057 /*! DATALEARNFAILEN - Data Learning Failed Interrupt Enable
23058  *  0b0..Disable interrupt or no impact
23059  *  0b1..Enable interrupt
23060  */
23061 #define FLEXSPI_INTEN_DATALEARNFAILEN(x)         (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_DATALEARNFAILEN_SHIFT)) & FLEXSPI_INTEN_DATALEARNFAILEN_MASK)
23062 
23063 #define FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK         (0x100U)
23064 #define FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT        (8U)
23065 /*! SCKSTOPBYRDEN - SCLK Stopped By Read Interrupt Enable
23066  *  0b0..Disable interrupt or no impact
23067  *  0b1..Enable interrupt
23068  */
23069 #define FLEXSPI_INTEN_SCKSTOPBYRDEN(x)           (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK)
23070 
23071 #define FLEXSPI_INTEN_SCKSTOPBYWREN_MASK         (0x200U)
23072 #define FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT        (9U)
23073 /*! SCKSTOPBYWREN - SCLK Stopped By Write Interrupt Enable
23074  *  0b0..Disable interrupt or no impact
23075  *  0b1..Enable interrupt
23076  */
23077 #define FLEXSPI_INTEN_SCKSTOPBYWREN(x)           (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYWREN_MASK)
23078 
23079 #define FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK       (0x400U)
23080 #define FLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT      (10U)
23081 /*! AHBBUSTIMEOUTEN - AHB Bus Timeout Interrupt Enable
23082  *  0b0..Disable interrupt or no impact
23083  *  0b1..Enable interrupt
23084  */
23085 #define FLEXSPI_INTEN_AHBBUSTIMEOUTEN(x)         (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK)
23086 
23087 #define FLEXSPI_INTEN_SEQTIMEOUTEN_MASK          (0x800U)
23088 #define FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT         (11U)
23089 /*! SEQTIMEOUTEN - Sequence execution Timeout Interrupt Enable
23090  *  0b0..Disable interrupt or no impact
23091  *  0b1..Enable interrupt
23092  */
23093 #define FLEXSPI_INTEN_SEQTIMEOUTEN(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_SEQTIMEOUTEN_MASK)
23094 
23095 #define FLEXSPI_INTEN_IPCMDSECUREVIOEN_MASK      (0x10000U)
23096 #define FLEXSPI_INTEN_IPCMDSECUREVIOEN_SHIFT     (16U)
23097 /*! IPCMDSECUREVIOEN - IP Command Security Violation Interrupt Enable
23098  *  0b0..Disable interrupt or no impact
23099  *  0b1..Enable interrupt
23100  */
23101 #define FLEXSPI_INTEN_IPCMDSECUREVIOEN(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDSECUREVIOEN_SHIFT)) & FLEXSPI_INTEN_IPCMDSECUREVIOEN_MASK)
23102 
23103 #define FLEXSPI_INTEN_AHBGCMERREN_MASK           (0x20000U)
23104 #define FLEXSPI_INTEN_AHBGCMERREN_SHIFT          (17U)
23105 /*! AHBGCMERREN - AHB Read GCM Error Interrupt Enable
23106  *  0b0..Disable interrupt or no impact
23107  *  0b1..Enable interrupt
23108  */
23109 #define FLEXSPI_INTEN_AHBGCMERREN(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBGCMERREN_SHIFT)) & FLEXSPI_INTEN_AHBGCMERREN_MASK)
23110 /*! @} */
23111 
23112 /*! @name INTR - Interrupt */
23113 /*! @{ */
23114 
23115 #define FLEXSPI_INTR_IPCMDDONE_MASK              (0x1U)
23116 #define FLEXSPI_INTR_IPCMDDONE_SHIFT             (0U)
23117 /*! IPCMDDONE - IP-Triggered Command Sequences Execution Finished
23118  *  0b0..Interrupt condition has not occurred
23119  *  0b1..Interrupt condition has occurred
23120  *  0b0..No effect
23121  *  0b1..Clear the flag
23122  */
23123 #define FLEXSPI_INTR_IPCMDDONE(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDDONE_SHIFT)) & FLEXSPI_INTR_IPCMDDONE_MASK)
23124 
23125 #define FLEXSPI_INTR_IPCMDGE_MASK                (0x2U)
23126 #define FLEXSPI_INTR_IPCMDGE_SHIFT               (1U)
23127 /*! IPCMDGE - IP-Triggered Command Sequences Grant Timeout
23128  *  0b0..Interrupt condition has not occurred
23129  *  0b1..Interrupt condition has occurred
23130  *  0b0..No effect
23131  *  0b1..Clear the flag
23132  */
23133 #define FLEXSPI_INTR_IPCMDGE(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDGE_SHIFT)) & FLEXSPI_INTR_IPCMDGE_MASK)
23134 
23135 #define FLEXSPI_INTR_AHBCMDGE_MASK               (0x4U)
23136 #define FLEXSPI_INTR_AHBCMDGE_SHIFT              (2U)
23137 /*! AHBCMDGE - AHB-Triggered Command Sequences Grant Timeout
23138  *  0b0..Interrupt condition has not occurred
23139  *  0b1..Interrupt condition has occurred
23140  *  0b0..No effect
23141  *  0b1..Clear the flag
23142  */
23143 #define FLEXSPI_INTR_AHBCMDGE(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDGE_SHIFT)) & FLEXSPI_INTR_AHBCMDGE_MASK)
23144 
23145 #define FLEXSPI_INTR_IPCMDERR_MASK               (0x8U)
23146 #define FLEXSPI_INTR_IPCMDERR_SHIFT              (3U)
23147 /*! IPCMDERR - IP-Triggered Command Sequences Error
23148  *  0b0..Interrupt condition has not occurred
23149  *  0b1..Interrupt condition has occurred
23150  *  0b0..No effect
23151  *  0b1..Clear the flag
23152  */
23153 #define FLEXSPI_INTR_IPCMDERR(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDERR_SHIFT)) & FLEXSPI_INTR_IPCMDERR_MASK)
23154 
23155 #define FLEXSPI_INTR_AHBCMDERR_MASK              (0x10U)
23156 #define FLEXSPI_INTR_AHBCMDERR_SHIFT             (4U)
23157 /*! AHBCMDERR - AHB-Triggered Command Sequences Error
23158  *  0b0..Interrupt condition has not occurred
23159  *  0b1..Interrupt condition has occurred
23160  *  0b0..No effect
23161  *  0b1..Clear the flag
23162  */
23163 #define FLEXSPI_INTR_AHBCMDERR(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDERR_SHIFT)) & FLEXSPI_INTR_AHBCMDERR_MASK)
23164 
23165 #define FLEXSPI_INTR_IPRXWA_MASK                 (0x20U)
23166 #define FLEXSPI_INTR_IPRXWA_SHIFT                (5U)
23167 /*! IPRXWA - IP Receive FIFO Watermark Available
23168  *  0b0..Interrupt condition has not occurred
23169  *  0b1..Interrupt condition has occurred
23170  *  0b0..No effect
23171  *  0b1..Clear the flag
23172  */
23173 #define FLEXSPI_INTR_IPRXWA(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPRXWA_SHIFT)) & FLEXSPI_INTR_IPRXWA_MASK)
23174 
23175 #define FLEXSPI_INTR_IPTXWE_MASK                 (0x40U)
23176 #define FLEXSPI_INTR_IPTXWE_SHIFT                (6U)
23177 /*! IPTXWE - IP Transmit FIFO Watermark Empty
23178  *  0b0..Interrupt condition has not occurred
23179  *  0b1..Interrupt condition has occurred
23180  *  0b0..No effect
23181  *  0b1..Clear the flag
23182  */
23183 #define FLEXSPI_INTR_IPTXWE(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPTXWE_SHIFT)) & FLEXSPI_INTR_IPTXWE_MASK)
23184 
23185 #define FLEXSPI_INTR_DATALEARNFAIL_MASK          (0x80U)
23186 #define FLEXSPI_INTR_DATALEARNFAIL_SHIFT         (7U)
23187 /*! DATALEARNFAIL - Data Learning Failed
23188  *  0b0..Interrupt condition has not occurred
23189  *  0b1..Interrupt condition has occurred
23190  *  0b0..No effect
23191  *  0b1..Clear the flag
23192  */
23193 #define FLEXSPI_INTR_DATALEARNFAIL(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_DATALEARNFAIL_SHIFT)) & FLEXSPI_INTR_DATALEARNFAIL_MASK)
23194 
23195 #define FLEXSPI_INTR_SCKSTOPBYRD_MASK            (0x100U)
23196 #define FLEXSPI_INTR_SCKSTOPBYRD_SHIFT           (8U)
23197 /*! SCKSTOPBYRD - SCLK Stopped Due To Full Receive FIFO
23198  *  0b0..Interrupt condition has not occurred
23199  *  0b1..Interrupt condition has occurred
23200  *  0b0..No effect
23201  *  0b1..Clear the flag
23202  */
23203 #define FLEXSPI_INTR_SCKSTOPBYRD(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYRD_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYRD_MASK)
23204 
23205 #define FLEXSPI_INTR_SCKSTOPBYWR_MASK            (0x200U)
23206 #define FLEXSPI_INTR_SCKSTOPBYWR_SHIFT           (9U)
23207 /*! SCKSTOPBYWR - SCLK Stopped Due To Empty Transmit FIFO
23208  *  0b0..Interrupt condition has not occurred
23209  *  0b1..Interrupt condition has occurred
23210  *  0b0..No effect
23211  *  0b1..Clear the flag
23212  */
23213 #define FLEXSPI_INTR_SCKSTOPBYWR(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYWR_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYWR_MASK)
23214 
23215 #define FLEXSPI_INTR_AHBBUSTIMEOUT_MASK          (0x400U)
23216 #define FLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT         (10U)
23217 /*! AHBBUSTIMEOUT - AHB Bus Timeout
23218  *  0b0..Interrupt condition has not occurred
23219  *  0b1..Interrupt condition has occurred
23220  *  0b0..No effect
23221  *  0b1..Clear the flag
23222  */
23223 #define FLEXSPI_INTR_AHBBUSTIMEOUT(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT)) & FLEXSPI_INTR_AHBBUSTIMEOUT_MASK)
23224 
23225 #define FLEXSPI_INTR_SEQTIMEOUT_MASK             (0x800U)
23226 #define FLEXSPI_INTR_SEQTIMEOUT_SHIFT            (11U)
23227 /*! SEQTIMEOUT - Sequence Execution Timeout
23228  *  0b0..Interrupt condition has not occurred
23229  *  0b1..Interrupt condition has occurred
23230  *  0b0..No effect
23231  *  0b1..Clear the flag
23232  */
23233 #define FLEXSPI_INTR_SEQTIMEOUT(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SEQTIMEOUT_SHIFT)) & FLEXSPI_INTR_SEQTIMEOUT_MASK)
23234 
23235 #define FLEXSPI_INTR_IPCMDSECUREVIO_MASK         (0x10000U)
23236 #define FLEXSPI_INTR_IPCMDSECUREVIO_SHIFT        (16U)
23237 /*! IPCMDSECUREVIO - IP Command Security Violation
23238  *  0b0..Interrupt condition has not occurred
23239  *  0b1..Interrupt condition has occurred
23240  *  0b0..No effect
23241  *  0b1..Clear the flag
23242  */
23243 #define FLEXSPI_INTR_IPCMDSECUREVIO(x)           (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDSECUREVIO_SHIFT)) & FLEXSPI_INTR_IPCMDSECUREVIO_MASK)
23244 
23245 #define FLEXSPI_INTR_AHBGCMERR_MASK              (0x20000U)
23246 #define FLEXSPI_INTR_AHBGCMERR_SHIFT             (17U)
23247 /*! AHBGCMERR - AHB Read GCM Error
23248  *  0b0..Interrupt condition has not occurred
23249  *  0b1..Interrupt condition has occurred
23250  *  0b0..No effect
23251  *  0b1..Clear the flag
23252  */
23253 #define FLEXSPI_INTR_AHBGCMERR(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBGCMERR_SHIFT)) & FLEXSPI_INTR_AHBGCMERR_MASK)
23254 /*! @} */
23255 
23256 /*! @name LUTKEY - LUT Key */
23257 /*! @{ */
23258 
23259 #define FLEXSPI_LUTKEY_KEY_MASK                  (0xFFFFFFFFU)
23260 #define FLEXSPI_LUTKEY_KEY_SHIFT                 (0U)
23261 /*! KEY - LUT Key */
23262 #define FLEXSPI_LUTKEY_KEY(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTKEY_KEY_SHIFT)) & FLEXSPI_LUTKEY_KEY_MASK)
23263 /*! @} */
23264 
23265 /*! @name LUTCR - LUT Control */
23266 /*! @{ */
23267 
23268 #define FLEXSPI_LUTCR_LOCK_MASK                  (0x1U)
23269 #define FLEXSPI_LUTCR_LOCK_SHIFT                 (0U)
23270 /*! LOCK - Lock LUT
23271  *  0b0..LUT is unlocked (LUTCR[UNLOCK] must be 1)
23272  *  0b1..LUT is locked and cannot be written
23273  */
23274 #define FLEXSPI_LUTCR_LOCK(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_LOCK_SHIFT)) & FLEXSPI_LUTCR_LOCK_MASK)
23275 
23276 #define FLEXSPI_LUTCR_UNLOCK_MASK                (0x2U)
23277 #define FLEXSPI_LUTCR_UNLOCK_SHIFT               (1U)
23278 /*! UNLOCK - Unlock LUT
23279  *  0b0..LUT is locked (LUTCR[LOCK] must be 1)
23280  *  0b1..LUT is unlocked and can be written
23281  */
23282 #define FLEXSPI_LUTCR_UNLOCK(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_UNLOCK_SHIFT)) & FLEXSPI_LUTCR_UNLOCK_MASK)
23283 
23284 #define FLEXSPI_LUTCR_PROTECT_MASK               (0x4U)
23285 #define FLEXSPI_LUTCR_PROTECT_SHIFT              (2U)
23286 /*! PROTECT - LUT Protection
23287  *  0b0..Not protected. All IPS controllers can access LUTCR and LUT memory.
23288  *  0b1..Protected. Only secure IPS controller can change the value of LUTCR and write to LUT memory.
23289  */
23290 #define FLEXSPI_LUTCR_PROTECT(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_PROTECT_SHIFT)) & FLEXSPI_LUTCR_PROTECT_MASK)
23291 /*! @} */
23292 
23293 /*! @name AHBRXBUFCR0 - AHB Receive Buffer 0 Control 0..AHB Receive Buffer 7 Control 0 */
23294 /*! @{ */
23295 
23296 #define FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK           (0xFFU)
23297 #define FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT          (0U)
23298 /*! BUFSZ - AHB Receive Buffer Size */
23299 #define FLEXSPI_AHBRXBUFCR0_BUFSZ(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT)) & FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK)
23300 
23301 #define FLEXSPI_AHBRXBUFCR0_MSTRID_MASK          (0x1F0000U)
23302 #define FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT         (16U)
23303 /*! MSTRID - AHB Controller ID */
23304 #define FLEXSPI_AHBRXBUFCR0_MSTRID(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT)) & FLEXSPI_AHBRXBUFCR0_MSTRID_MASK)
23305 
23306 #define FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK        (0x7000000U)
23307 #define FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT       (24U)
23308 /*! PRIORITY - AHB Controller Read Priority */
23309 #define FLEXSPI_AHBRXBUFCR0_PRIORITY(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK)
23310 
23311 #define FLEXSPI_AHBRXBUFCR0_REGIONEN_MASK        (0x40000000U)
23312 #define FLEXSPI_AHBRXBUFCR0_REGIONEN_SHIFT       (30U)
23313 /*! REGIONEN - AHB Receive Buffer Address Region Enable
23314  *  0b0..Disabled. The buffer hit is based on the value of MSTRID only.
23315  *  0b1..Enabled. The buffer hit is based on the value of MSTRID and the address within AHBBUFREGIONSTARTn and AHBREGIONENDn.
23316  */
23317 #define FLEXSPI_AHBRXBUFCR0_REGIONEN(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_REGIONEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_REGIONEN_MASK)
23318 
23319 #define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK      (0x80000000U)
23320 #define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT     (31U)
23321 /*! PREFETCHEN - AHB Read Prefetch Enable
23322  *  0b0..Disabled
23323  *  0b1..Enabled when is enabled.
23324  */
23325 #define FLEXSPI_AHBRXBUFCR0_PREFETCHEN(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK)
23326 /*! @} */
23327 
23328 /* The count of FLEXSPI_AHBRXBUFCR0 */
23329 #define FLEXSPI_AHBRXBUFCR0_COUNT                (8U)
23330 
23331 /*! @name FLSHCR0 - Flash Control 0 */
23332 /*! @{ */
23333 
23334 #define FLEXSPI_FLSHCR0_FLSHSZ_MASK              (0x7FFFFFU)
23335 #define FLEXSPI_FLSHCR0_FLSHSZ_SHIFT             (0U)
23336 /*! FLSHSZ - Flash Size in KB */
23337 #define FLEXSPI_FLSHCR0_FLSHSZ(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_FLSHSZ_SHIFT)) & FLEXSPI_FLSHCR0_FLSHSZ_MASK)
23338 
23339 #define FLEXSPI_FLSHCR0_ADDRSHIFT_MASK           (0x20000000U)
23340 #define FLEXSPI_FLSHCR0_ADDRSHIFT_SHIFT          (29U)
23341 /*! ADDRSHIFT - AHB Address Shift Function control
23342  *  0b0..Disabled
23343  *  0b1..Enabled
23344  */
23345 #define FLEXSPI_FLSHCR0_ADDRSHIFT(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_ADDRSHIFT_SHIFT)) & FLEXSPI_FLSHCR0_ADDRSHIFT_MASK)
23346 
23347 #define FLEXSPI_FLSHCR0_SPLITWREN_MASK           (0x40000000U)
23348 #define FLEXSPI_FLSHCR0_SPLITWREN_SHIFT          (30U)
23349 /*! SPLITWREN - AHB Write Access Split Function Enable
23350  *  0b0..Disable
23351  *  0b1..Enable
23352  */
23353 #define FLEXSPI_FLSHCR0_SPLITWREN(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_SPLITWREN_SHIFT)) & FLEXSPI_FLSHCR0_SPLITWREN_MASK)
23354 
23355 #define FLEXSPI_FLSHCR0_SPLITRDEN_MASK           (0x80000000U)
23356 #define FLEXSPI_FLSHCR0_SPLITRDEN_SHIFT          (31U)
23357 /*! SPLITRDEN - AHB Read Access Split Function Enable
23358  *  0b0..Disable
23359  *  0b1..Enable
23360  */
23361 #define FLEXSPI_FLSHCR0_SPLITRDEN(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_SPLITRDEN_SHIFT)) & FLEXSPI_FLSHCR0_SPLITRDEN_MASK)
23362 /*! @} */
23363 
23364 /* The count of FLEXSPI_FLSHCR0 */
23365 #define FLEXSPI_FLSHCR0_COUNT                    (4U)
23366 
23367 /*! @name FLSHCR1 - Flash Control 1 */
23368 /*! @{ */
23369 
23370 #define FLEXSPI_FLSHCR1_TCSS_MASK                (0x1FU)
23371 #define FLEXSPI_FLSHCR1_TCSS_SHIFT               (0U)
23372 /*! TCSS - Serial Flash CS Setup Time */
23373 #define FLEXSPI_FLSHCR1_TCSS(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSS_SHIFT)) & FLEXSPI_FLSHCR1_TCSS_MASK)
23374 
23375 #define FLEXSPI_FLSHCR1_TCSH_MASK                (0x3E0U)
23376 #define FLEXSPI_FLSHCR1_TCSH_SHIFT               (5U)
23377 /*! TCSH - Serial Flash CS Hold Time */
23378 #define FLEXSPI_FLSHCR1_TCSH(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSH_SHIFT)) & FLEXSPI_FLSHCR1_TCSH_MASK)
23379 
23380 #define FLEXSPI_FLSHCR1_WA_MASK                  (0x400U)
23381 #define FLEXSPI_FLSHCR1_WA_SHIFT                 (10U)
23382 /*! WA - Word-Addressable
23383  *  0b0..Byte-addressable
23384  *  0b1..Word-addressable
23385  */
23386 #define FLEXSPI_FLSHCR1_WA(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_WA_SHIFT)) & FLEXSPI_FLSHCR1_WA_MASK)
23387 
23388 #define FLEXSPI_FLSHCR1_CAS_MASK                 (0x7800U)
23389 #define FLEXSPI_FLSHCR1_CAS_SHIFT                (11U)
23390 /*! CAS - Column Address Size */
23391 #define FLEXSPI_FLSHCR1_CAS(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CAS_SHIFT)) & FLEXSPI_FLSHCR1_CAS_MASK)
23392 
23393 #define FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK      (0x8000U)
23394 #define FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT     (15U)
23395 /*! CSINTERVALUNIT - Chip Select Interval Unit
23396  *  0b0..1 serial clock cycle
23397  *  0b1..256 serial clock cycles
23398  */
23399 #define FLEXSPI_FLSHCR1_CSINTERVALUNIT(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK)
23400 
23401 #define FLEXSPI_FLSHCR1_CSINTERVAL_MASK          (0xFFFF0000U)
23402 #define FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT         (16U)
23403 /*! CSINTERVAL - Chip Select Interval */
23404 #define FLEXSPI_FLSHCR1_CSINTERVAL(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVAL_MASK)
23405 /*! @} */
23406 
23407 /* The count of FLEXSPI_FLSHCR1 */
23408 #define FLEXSPI_FLSHCR1_COUNT                    (4U)
23409 
23410 /*! @name FLSHCR2 - Flash Control 2 */
23411 /*! @{ */
23412 
23413 #define FLEXSPI_FLSHCR2_ARDSEQID_MASK            (0xFU)
23414 #define FLEXSPI_FLSHCR2_ARDSEQID_SHIFT           (0U)
23415 /*! ARDSEQID - Sequence Index for AHB Read-Triggered Command in LUT */
23416 #define FLEXSPI_FLSHCR2_ARDSEQID(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQID_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQID_MASK)
23417 
23418 #define FLEXSPI_FLSHCR2_ARDSEQNUM_MASK           (0xE0U)
23419 #define FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT          (5U)
23420 /*! ARDSEQNUM - Sequence Number for AHB Read-Triggered Command */
23421 #define FLEXSPI_FLSHCR2_ARDSEQNUM(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQNUM_MASK)
23422 
23423 #define FLEXSPI_FLSHCR2_AWRSEQID_MASK            (0xF00U)
23424 #define FLEXSPI_FLSHCR2_AWRSEQID_SHIFT           (8U)
23425 /*! AWRSEQID - Sequence Index for AHB Write-Triggered Command */
23426 #define FLEXSPI_FLSHCR2_AWRSEQID(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQID_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQID_MASK)
23427 
23428 #define FLEXSPI_FLSHCR2_AWRSEQNUM_MASK           (0xE000U)
23429 #define FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT          (13U)
23430 /*! AWRSEQNUM - Sequence Number for AHB Write-Triggered Command */
23431 #define FLEXSPI_FLSHCR2_AWRSEQNUM(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQNUM_MASK)
23432 
23433 #define FLEXSPI_FLSHCR2_AWRWAIT_MASK             (0xFFF0000U)
23434 #define FLEXSPI_FLSHCR2_AWRWAIT_SHIFT            (16U)
23435 /*! AWRWAIT - AHB Write Wait */
23436 #define FLEXSPI_FLSHCR2_AWRWAIT(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAIT_MASK)
23437 
23438 #define FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK         (0x70000000U)
23439 #define FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT        (28U)
23440 /*! AWRWAITUNIT - AWRWAIT Unit
23441  *  0b000..2
23442  *  0b001..8
23443  *  0b010..32
23444  *  0b011..128
23445  *  0b100..512
23446  *  0b101..2048
23447  *  0b110..8192
23448  *  0b111..32768
23449  */
23450 #define FLEXSPI_FLSHCR2_AWRWAITUNIT(x)           (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK)
23451 
23452 #define FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK         (0x80000000U)
23453 #define FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT        (31U)
23454 /*! CLRINSTRPTR - Clear Instruction Pointer */
23455 #define FLEXSPI_FLSHCR2_CLRINSTRPTR(x)           (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT)) & FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK)
23456 /*! @} */
23457 
23458 /* The count of FLEXSPI_FLSHCR2 */
23459 #define FLEXSPI_FLSHCR2_COUNT                    (4U)
23460 
23461 /*! @name FLSHCR4 - Flash Control 4 */
23462 /*! @{ */
23463 
23464 #define FLEXSPI_FLSHCR4_WMOPT1_MASK              (0x1U)
23465 #define FLEXSPI_FLSHCR4_WMOPT1_SHIFT             (0U)
23466 /*! WMOPT1 - Write Mask Option 1
23467  *  0b0..When writing to an external device, DQS pin is used as write mask. When flash memory is accessed in
23468  *       individual mode, AHB or IP write burst start address alignment is not limited.
23469  *  0b1..When writing to an external device, DQS pin is not used as write mask. When flash memory is accessed in
23470  *       individual mode, AHB or IP write burst start address alignment is limited.
23471  */
23472 #define FLEXSPI_FLSHCR4_WMOPT1(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMOPT1_SHIFT)) & FLEXSPI_FLSHCR4_WMOPT1_MASK)
23473 
23474 #define FLEXSPI_FLSHCR4_WMENA_MASK               (0x4U)
23475 #define FLEXSPI_FLSHCR4_WMENA_SHIFT              (2U)
23476 /*! WMENA - Write Mask Enable for Port A
23477  *  0b0..Disabled. When writing to external device, DQS(RWDS) pin is not driven.
23478  *  0b1..Enabled. When writing to external device, FlexSPI drives DQS(RWDS) pin as write mask output.
23479  */
23480 #define FLEXSPI_FLSHCR4_WMENA(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENA_SHIFT)) & FLEXSPI_FLSHCR4_WMENA_MASK)
23481 
23482 #define FLEXSPI_FLSHCR4_WMENB_MASK               (0x8U)
23483 #define FLEXSPI_FLSHCR4_WMENB_SHIFT              (3U)
23484 /*! WMENB - Write Mask Enable for Port B
23485  *  0b0..Disabled. When writing to external device, DQS(RWDS) pin is not driven.
23486  *  0b1..Enabled. When writing to external device, FlexSPI drives DQS(RWDS) pin as write mask output.
23487  */
23488 #define FLEXSPI_FLSHCR4_WMENB(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENB_SHIFT)) & FLEXSPI_FLSHCR4_WMENB_MASK)
23489 /*! @} */
23490 
23491 /*! @name IPCR0 - IP Control 0 */
23492 /*! @{ */
23493 
23494 #define FLEXSPI_IPCR0_SFAR_MASK                  (0xFFFFFFFFU)
23495 #define FLEXSPI_IPCR0_SFAR_SHIFT                 (0U)
23496 /*! SFAR - Serial Flash Address */
23497 #define FLEXSPI_IPCR0_SFAR(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR0_SFAR_SHIFT)) & FLEXSPI_IPCR0_SFAR_MASK)
23498 /*! @} */
23499 
23500 /*! @name IPCR1 - IP Control 1 */
23501 /*! @{ */
23502 
23503 #define FLEXSPI_IPCR1_IDATSZ_MASK                (0xFFFFU)
23504 #define FLEXSPI_IPCR1_IDATSZ_SHIFT               (0U)
23505 /*! IDATSZ - Flash Read/Program Data Size (in bytes) for IP command. */
23506 #define FLEXSPI_IPCR1_IDATSZ(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IDATSZ_SHIFT)) & FLEXSPI_IPCR1_IDATSZ_MASK)
23507 
23508 #define FLEXSPI_IPCR1_ISEQID_MASK                (0xF0000U)
23509 #define FLEXSPI_IPCR1_ISEQID_SHIFT               (16U)
23510 /*! ISEQID - Sequence Index in LUT for IP command. */
23511 #define FLEXSPI_IPCR1_ISEQID(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQID_SHIFT)) & FLEXSPI_IPCR1_ISEQID_MASK)
23512 
23513 #define FLEXSPI_IPCR1_ISEQNUM_MASK               (0x7000000U)
23514 #define FLEXSPI_IPCR1_ISEQNUM_SHIFT              (24U)
23515 /*! ISEQNUM - Sequence Number for IP command: ISEQNUM+1. */
23516 #define FLEXSPI_IPCR1_ISEQNUM(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQNUM_SHIFT)) & FLEXSPI_IPCR1_ISEQNUM_MASK)
23517 
23518 #define FLEXSPI_IPCR1_IPAREN_MASK                (0x80000000U)
23519 #define FLEXSPI_IPCR1_IPAREN_SHIFT               (31U)
23520 /*! IPAREN - Parallel Mode Enable for IP Commands
23521  *  0b0..Disabled. Flash memory is accessed in Individual mode.
23522  *  0b1..Enabled. Flash memory is accessed in Parallel mode.
23523  */
23524 #define FLEXSPI_IPCR1_IPAREN(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IPAREN_SHIFT)) & FLEXSPI_IPCR1_IPAREN_MASK)
23525 /*! @} */
23526 
23527 /*! @name IPCR2 - IP Control 2 */
23528 /*! @{ */
23529 
23530 #define FLEXSPI_IPCR2_IPBLKAHBREQ_MASK           (0x1U)
23531 #define FLEXSPI_IPCR2_IPBLKAHBREQ_SHIFT          (0U)
23532 /*! IPBLKAHBREQ - IP Command Blocking AHB Command Request Enable
23533  *  0b0..IP commands do not block AHB command requests.
23534  *  0b1..IP commands block AHB command requests.
23535  */
23536 #define FLEXSPI_IPCR2_IPBLKAHBREQ(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR2_IPBLKAHBREQ_SHIFT)) & FLEXSPI_IPCR2_IPBLKAHBREQ_MASK)
23537 
23538 #define FLEXSPI_IPCR2_IPBLKAHBACK_MASK           (0x2U)
23539 #define FLEXSPI_IPCR2_IPBLKAHBACK_SHIFT          (1U)
23540 /*! IPBLKAHBACK - IP Command Blocking AHB Command Acknowledgment Enable
23541  *  0b0..IP commands do not block AHB command acknowledgment.
23542  *  0b1..IP commands block AHB command acknowledgment.
23543  */
23544 #define FLEXSPI_IPCR2_IPBLKAHBACK(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR2_IPBLKAHBACK_SHIFT)) & FLEXSPI_IPCR2_IPBLKAHBACK_MASK)
23545 
23546 #define FLEXSPI_IPCR2_IPBLKALLAHB_MASK           (0x4U)
23547 #define FLEXSPI_IPCR2_IPBLKALLAHB_SHIFT          (2U)
23548 /*! IPBLKALLAHB - IP Command Blocking All AHB Command Enable
23549  *  0b0..IP commands only block AHB commands that affect the IPED region.
23550  *  0b1..IP commands block all AHB commands.
23551  */
23552 #define FLEXSPI_IPCR2_IPBLKALLAHB(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR2_IPBLKALLAHB_SHIFT)) & FLEXSPI_IPCR2_IPBLKALLAHB_MASK)
23553 /*! @} */
23554 
23555 /*! @name IPCMD - IP Command */
23556 /*! @{ */
23557 
23558 #define FLEXSPI_IPCMD_TRG_MASK                   (0x1U)
23559 #define FLEXSPI_IPCMD_TRG_SHIFT                  (0U)
23560 /*! TRG - Command Trigger
23561  *  0b0..No action
23562  *  0b1..Start the IP command that the IPCR0 and IPCR1 registers define.
23563  */
23564 #define FLEXSPI_IPCMD_TRG(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCMD_TRG_SHIFT)) & FLEXSPI_IPCMD_TRG_MASK)
23565 /*! @} */
23566 
23567 /*! @name DLPR - Data Learning Pattern */
23568 /*! @{ */
23569 
23570 #define FLEXSPI_DLPR_DLP_MASK                    (0xFFFFFFFFU)
23571 #define FLEXSPI_DLPR_DLP_SHIFT                   (0U)
23572 /*! DLP - Data Learning Pattern */
23573 #define FLEXSPI_DLPR_DLP(x)                      (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLPR_DLP_SHIFT)) & FLEXSPI_DLPR_DLP_MASK)
23574 /*! @} */
23575 
23576 /*! @name IPRXFCR - IP Receive FIFO Control */
23577 /*! @{ */
23578 
23579 #define FLEXSPI_IPRXFCR_CLRIPRXF_MASK            (0x1U)
23580 #define FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT           (0U)
23581 /*! CLRIPRXF - Clear IP Receive FIFO
23582  *  0b0..No function
23583  *  0b1..A clock cycle pulse clears all valid data entries in IP receive FIFO.
23584  */
23585 #define FLEXSPI_IPRXFCR_CLRIPRXF(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT)) & FLEXSPI_IPRXFCR_CLRIPRXF_MASK)
23586 
23587 #define FLEXSPI_IPRXFCR_RXDMAEN_MASK             (0x2U)
23588 #define FLEXSPI_IPRXFCR_RXDMAEN_SHIFT            (1U)
23589 /*! RXDMAEN - IP Receive FIFO Reading by DMA Enable
23590  *  0b0..Disabled. The processor reads the FIFO.
23591  *  0b1..Enabled. DMA reads the FIFO.
23592  */
23593 #define FLEXSPI_IPRXFCR_RXDMAEN(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXDMAEN_SHIFT)) & FLEXSPI_IPRXFCR_RXDMAEN_MASK)
23594 
23595 #define FLEXSPI_IPRXFCR_RXWMRK_MASK              (0x1FCU)
23596 #define FLEXSPI_IPRXFCR_RXWMRK_SHIFT             (2U)
23597 /*! RXWMRK - IP Receive FIFO Watermark Level */
23598 #define FLEXSPI_IPRXFCR_RXWMRK(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXWMRK_SHIFT)) & FLEXSPI_IPRXFCR_RXWMRK_MASK)
23599 /*! @} */
23600 
23601 /*! @name IPTXFCR - IP Transmit FIFO Control */
23602 /*! @{ */
23603 
23604 #define FLEXSPI_IPTXFCR_CLRIPTXF_MASK            (0x1U)
23605 #define FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT           (0U)
23606 /*! CLRIPTXF - Clear IP Transmit FIFO
23607  *  0b0..No function
23608  *  0b1..A clock cycle pulse clears all valid data entries in the IP transmit FIFO.
23609  */
23610 #define FLEXSPI_IPTXFCR_CLRIPTXF(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT)) & FLEXSPI_IPTXFCR_CLRIPTXF_MASK)
23611 
23612 #define FLEXSPI_IPTXFCR_TXDMAEN_MASK             (0x2U)
23613 #define FLEXSPI_IPTXFCR_TXDMAEN_SHIFT            (1U)
23614 /*! TXDMAEN - Transmit FIFO DMA Enable
23615  *  0b0..Processor
23616  *  0b1..DMA
23617  */
23618 #define FLEXSPI_IPTXFCR_TXDMAEN(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXDMAEN_SHIFT)) & FLEXSPI_IPTXFCR_TXDMAEN_MASK)
23619 
23620 #define FLEXSPI_IPTXFCR_TXWMRK_MASK              (0x1FCU)
23621 #define FLEXSPI_IPTXFCR_TXWMRK_SHIFT             (2U)
23622 /*! TXWMRK - Transmit Watermark Level */
23623 #define FLEXSPI_IPTXFCR_TXWMRK(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXWMRK_SHIFT)) & FLEXSPI_IPTXFCR_TXWMRK_MASK)
23624 /*! @} */
23625 
23626 /*! @name DLLCR - DLL Control 0 */
23627 /*! @{ */
23628 
23629 #define FLEXSPI_DLLCR_DLLEN_MASK                 (0x1U)
23630 #define FLEXSPI_DLLCR_DLLEN_SHIFT                (0U)
23631 /*! DLLEN - DLL Calibration Enable
23632  *  0b0..Disable
23633  *  0b1..Enable
23634  */
23635 #define FLEXSPI_DLLCR_DLLEN(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLEN_SHIFT)) & FLEXSPI_DLLCR_DLLEN_MASK)
23636 
23637 #define FLEXSPI_DLLCR_DLLRESET_MASK              (0x2U)
23638 #define FLEXSPI_DLLCR_DLLRESET_SHIFT             (1U)
23639 /*! DLLRESET - DLL reset
23640  *  0b0..No function
23641  *  0b1..Force DLL reset.
23642  */
23643 #define FLEXSPI_DLLCR_DLLRESET(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLRESET_SHIFT)) & FLEXSPI_DLLCR_DLLRESET_MASK)
23644 
23645 #define FLEXSPI_DLLCR_SLVDLYTARGET_MASK          (0x78U)
23646 #define FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT         (3U)
23647 /*! SLVDLYTARGET - Target Delay Line */
23648 #define FLEXSPI_DLLCR_SLVDLYTARGET(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT)) & FLEXSPI_DLLCR_SLVDLYTARGET_MASK)
23649 
23650 #define FLEXSPI_DLLCR_OVRDEN_MASK                (0x100U)
23651 #define FLEXSPI_DLLCR_OVRDEN_SHIFT               (8U)
23652 /*! OVRDEN - Target Clock Delay Line Override Value Enable
23653  *  0b0..Disable
23654  *  0b1..Enable
23655  */
23656 #define FLEXSPI_DLLCR_OVRDEN(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDEN_SHIFT)) & FLEXSPI_DLLCR_OVRDEN_MASK)
23657 
23658 #define FLEXSPI_DLLCR_OVRDVAL_MASK               (0x7E00U)
23659 #define FLEXSPI_DLLCR_OVRDVAL_SHIFT              (9U)
23660 /*! OVRDVAL - Target Clock Delay Line Override Value */
23661 #define FLEXSPI_DLLCR_OVRDVAL(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDVAL_SHIFT)) & FLEXSPI_DLLCR_OVRDVAL_MASK)
23662 
23663 #define FLEXSPI_DLLCR_REFPHASEGAP_MASK           (0x18000U)
23664 #define FLEXSPI_DLLCR_REFPHASEGAP_SHIFT          (15U)
23665 /*! REFPHASEGAP - Reference Clock Delay Line Phase Adjust Gap. REFPHASEGAP setting of 2h is recommended if DLLEN is set. */
23666 #define FLEXSPI_DLLCR_REFPHASEGAP(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_REFPHASEGAP_SHIFT)) & FLEXSPI_DLLCR_REFPHASEGAP_MASK)
23667 /*! @} */
23668 
23669 /* The count of FLEXSPI_DLLCR */
23670 #define FLEXSPI_DLLCR_COUNT                      (2U)
23671 
23672 /*! @name STS0 - Status 0 */
23673 /*! @{ */
23674 
23675 #define FLEXSPI_STS0_SEQIDLE_MASK                (0x1U)
23676 #define FLEXSPI_STS0_SEQIDLE_SHIFT               (0U)
23677 /*! SEQIDLE - SEQ_CTL State Machine Idle
23678  *  0b0..Not idle
23679  *  0b1..Idle
23680  */
23681 #define FLEXSPI_STS0_SEQIDLE(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_SEQIDLE_SHIFT)) & FLEXSPI_STS0_SEQIDLE_MASK)
23682 
23683 #define FLEXSPI_STS0_ARBIDLE_MASK                (0x2U)
23684 #define FLEXSPI_STS0_ARBIDLE_SHIFT               (1U)
23685 /*! ARBIDLE - ARB_CTL State Machine Idle
23686  *  0b0..Not idle
23687  *  0b1..Idle
23688  */
23689 #define FLEXSPI_STS0_ARBIDLE(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBIDLE_SHIFT)) & FLEXSPI_STS0_ARBIDLE_MASK)
23690 
23691 #define FLEXSPI_STS0_ARBCMDSRC_MASK              (0xCU)
23692 #define FLEXSPI_STS0_ARBCMDSRC_SHIFT             (2U)
23693 /*! ARBCMDSRC - ARB Command Source
23694  *  0b00..Trigger source is AHB read command.
23695  *  0b01..Trigger source is AHB write command.
23696  *  0b10..Trigger source is IP command (by writing 1 to IPCMD[TRG]).
23697  *  0b11..Trigger source is a suspended command that has resumed.
23698  */
23699 #define FLEXSPI_STS0_ARBCMDSRC(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBCMDSRC_SHIFT)) & FLEXSPI_STS0_ARBCMDSRC_MASK)
23700 
23701 #define FLEXSPI_STS0_DATALEARNPHASEA_MASK        (0xF0U)
23702 #define FLEXSPI_STS0_DATALEARNPHASEA_SHIFT       (4U)
23703 /*! DATALEARNPHASEA - Data Learning Phase Selection on Port A */
23704 #define FLEXSPI_STS0_DATALEARNPHASEA(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_DATALEARNPHASEA_SHIFT)) & FLEXSPI_STS0_DATALEARNPHASEA_MASK)
23705 
23706 #define FLEXSPI_STS0_DATALEARNPHASEB_MASK        (0xF00U)
23707 #define FLEXSPI_STS0_DATALEARNPHASEB_SHIFT       (8U)
23708 /*! DATALEARNPHASEB - Data Learning Phase Selection on Port B */
23709 #define FLEXSPI_STS0_DATALEARNPHASEB(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_DATALEARNPHASEB_SHIFT)) & FLEXSPI_STS0_DATALEARNPHASEB_MASK)
23710 /*! @} */
23711 
23712 /*! @name STS1 - Status 1 */
23713 /*! @{ */
23714 
23715 #define FLEXSPI_STS1_AHBCMDERRID_MASK            (0xFU)
23716 #define FLEXSPI_STS1_AHBCMDERRID_SHIFT           (0U)
23717 /*! AHBCMDERRID - AHB Command Error ID */
23718 #define FLEXSPI_STS1_AHBCMDERRID(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRID_SHIFT)) & FLEXSPI_STS1_AHBCMDERRID_MASK)
23719 
23720 #define FLEXSPI_STS1_AHBCMDERRCODE_MASK          (0xF00U)
23721 #define FLEXSPI_STS1_AHBCMDERRCODE_SHIFT         (8U)
23722 /*! AHBCMDERRCODE - AHB Command Error Code
23723  *  0b0000..No error
23724  *  0b0010..AHB Write command with JMP_ON_CS instruction used in the sequence
23725  *  0b0011..Unknown instruction opcode in the sequence
23726  *  0b0100..DUMMY_SDR or DUMMY_RWDS_SDR instruction used in DDR sequence
23727  *  0b0101..DUMMY_DDR or DUMMY_RWDS_DDR instruction used in SDR sequence
23728  *  0b1110..Sequence execution timeout
23729  */
23730 #define FLEXSPI_STS1_AHBCMDERRCODE(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRCODE_SHIFT)) & FLEXSPI_STS1_AHBCMDERRCODE_MASK)
23731 
23732 #define FLEXSPI_STS1_IPCMDERRID_MASK             (0xF0000U)
23733 #define FLEXSPI_STS1_IPCMDERRID_SHIFT            (16U)
23734 /*! IPCMDERRID - IP Command Error ID */
23735 #define FLEXSPI_STS1_IPCMDERRID(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRID_SHIFT)) & FLEXSPI_STS1_IPCMDERRID_MASK)
23736 
23737 #define FLEXSPI_STS1_IPCMDERRCODE_MASK           (0xF000000U)
23738 #define FLEXSPI_STS1_IPCMDERRCODE_SHIFT          (24U)
23739 /*! IPCMDERRCODE - IP Command Error Code
23740  *  0b0000..No error
23741  *  0b0010..IP command with JMP_ON_CS instruction used in the sequence
23742  *  0b0011..Unknown instruction opcode in the sequence
23743  *  0b0100..DUMMY_SDR or DUMMY_RWDS_SDR instruction used in DDR sequence
23744  *  0b0101..DUMMY_DDR or DUMMY_RWDS_DDR instruction used in SDR sequence
23745  *  0b0110..Flash memory access start address exceeds entire flash address range (A1, A2, B1, and B2)
23746  *  0b1110..Sequence execution timeout
23747  *  0b1111..Flash boundary crossed
23748  */
23749 #define FLEXSPI_STS1_IPCMDERRCODE(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRCODE_SHIFT)) & FLEXSPI_STS1_IPCMDERRCODE_MASK)
23750 /*! @} */
23751 
23752 /*! @name STS2 - Status 2 */
23753 /*! @{ */
23754 
23755 #define FLEXSPI_STS2_ASLVLOCK_MASK               (0x1U)
23756 #define FLEXSPI_STS2_ASLVLOCK_SHIFT              (0U)
23757 /*! ASLVLOCK - Flash A Sample Target Delay Line Locked
23758  *  0b0..Not locked
23759  *  0b1..Locked
23760  */
23761 #define FLEXSPI_STS2_ASLVLOCK(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVLOCK_SHIFT)) & FLEXSPI_STS2_ASLVLOCK_MASK)
23762 
23763 #define FLEXSPI_STS2_AREFLOCK_MASK               (0x2U)
23764 #define FLEXSPI_STS2_AREFLOCK_SHIFT              (1U)
23765 /*! AREFLOCK - Flash A Sample Clock Reference Delay Line Locked
23766  *  0b0..Not locked
23767  *  0b1..Locked
23768  */
23769 #define FLEXSPI_STS2_AREFLOCK(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFLOCK_SHIFT)) & FLEXSPI_STS2_AREFLOCK_MASK)
23770 
23771 #define FLEXSPI_STS2_ASLVSEL_MASK                (0xFCU)
23772 #define FLEXSPI_STS2_ASLVSEL_SHIFT               (2U)
23773 /*! ASLVSEL - Flash A Sample Clock Target Delay Line Delay Cell Number */
23774 #define FLEXSPI_STS2_ASLVSEL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVSEL_SHIFT)) & FLEXSPI_STS2_ASLVSEL_MASK)
23775 
23776 #define FLEXSPI_STS2_AREFSEL_MASK                (0x3F00U)
23777 #define FLEXSPI_STS2_AREFSEL_SHIFT               (8U)
23778 /*! AREFSEL - Flash A Sample Clock Reference Delay Line Delay Cell Number */
23779 #define FLEXSPI_STS2_AREFSEL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFSEL_SHIFT)) & FLEXSPI_STS2_AREFSEL_MASK)
23780 
23781 #define FLEXSPI_STS2_BSLVLOCK_MASK               (0x10000U)
23782 #define FLEXSPI_STS2_BSLVLOCK_SHIFT              (16U)
23783 /*! BSLVLOCK - Flash B Sample Target Reference Delay Line Locked
23784  *  0b0..Not locked
23785  *  0b1..Locked
23786  */
23787 #define FLEXSPI_STS2_BSLVLOCK(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVLOCK_SHIFT)) & FLEXSPI_STS2_BSLVLOCK_MASK)
23788 
23789 #define FLEXSPI_STS2_BREFLOCK_MASK               (0x20000U)
23790 #define FLEXSPI_STS2_BREFLOCK_SHIFT              (17U)
23791 /*! BREFLOCK - Flash B Sample Clock Reference Delay Line Locked
23792  *  0b0..Not locked
23793  *  0b1..Locked
23794  */
23795 #define FLEXSPI_STS2_BREFLOCK(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFLOCK_SHIFT)) & FLEXSPI_STS2_BREFLOCK_MASK)
23796 
23797 #define FLEXSPI_STS2_BSLVSEL_MASK                (0xFC0000U)
23798 #define FLEXSPI_STS2_BSLVSEL_SHIFT               (18U)
23799 /*! BSLVSEL - Flash B Sample Clock Target Delay Line Delay Cell Number */
23800 #define FLEXSPI_STS2_BSLVSEL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVSEL_SHIFT)) & FLEXSPI_STS2_BSLVSEL_MASK)
23801 
23802 #define FLEXSPI_STS2_BREFSEL_MASK                (0x3F000000U)
23803 #define FLEXSPI_STS2_BREFSEL_SHIFT               (24U)
23804 /*! BREFSEL - Flash B Sample Clock Reference Delay Line Delay Cell Number */
23805 #define FLEXSPI_STS2_BREFSEL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFSEL_SHIFT)) & FLEXSPI_STS2_BREFSEL_MASK)
23806 /*! @} */
23807 
23808 /*! @name AHBSPNDSTS - AHB Suspend Status */
23809 /*! @{ */
23810 
23811 #define FLEXSPI_AHBSPNDSTS_ACTIVE_MASK           (0x1U)
23812 #define FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT          (0U)
23813 /*! ACTIVE - Active AHB Read Prefetch Suspended
23814  *  0b0..No suspended AHB read prefetch command.
23815  *  0b1..An AHB read prefetch command sequence has been suspended.
23816  */
23817 #define FLEXSPI_AHBSPNDSTS_ACTIVE(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT)) & FLEXSPI_AHBSPNDSTS_ACTIVE_MASK)
23818 
23819 #define FLEXSPI_AHBSPNDSTS_BUFID_MASK            (0xEU)
23820 #define FLEXSPI_AHBSPNDSTS_BUFID_SHIFT           (1U)
23821 /*! BUFID - AHB Receive Buffer ID for Suspended Command Sequence */
23822 #define FLEXSPI_AHBSPNDSTS_BUFID(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_BUFID_SHIFT)) & FLEXSPI_AHBSPNDSTS_BUFID_MASK)
23823 
23824 #define FLEXSPI_AHBSPNDSTS_DATLFT_MASK           (0xFFFF0000U)
23825 #define FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT          (16U)
23826 /*! DATLFT - Data Left */
23827 #define FLEXSPI_AHBSPNDSTS_DATLFT(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT)) & FLEXSPI_AHBSPNDSTS_DATLFT_MASK)
23828 /*! @} */
23829 
23830 /*! @name IPRXFSTS - IP Receive FIFO Status */
23831 /*! @{ */
23832 
23833 #define FLEXSPI_IPRXFSTS_FILL_MASK               (0xFFU)
23834 #define FLEXSPI_IPRXFSTS_FILL_SHIFT              (0U)
23835 /*! FILL - Fill Level of IP Receive FIFO */
23836 #define FLEXSPI_IPRXFSTS_FILL(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_FILL_SHIFT)) & FLEXSPI_IPRXFSTS_FILL_MASK)
23837 
23838 #define FLEXSPI_IPRXFSTS_RDCNTR_MASK             (0xFFFF0000U)
23839 #define FLEXSPI_IPRXFSTS_RDCNTR_SHIFT            (16U)
23840 /*! RDCNTR - Read Data Counter */
23841 #define FLEXSPI_IPRXFSTS_RDCNTR(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_RDCNTR_SHIFT)) & FLEXSPI_IPRXFSTS_RDCNTR_MASK)
23842 /*! @} */
23843 
23844 /*! @name IPTXFSTS - IP Transmit FIFO Status */
23845 /*! @{ */
23846 
23847 #define FLEXSPI_IPTXFSTS_FILL_MASK               (0xFFU)
23848 #define FLEXSPI_IPTXFSTS_FILL_SHIFT              (0U)
23849 /*! FILL - Fill Level of IP Transmit FIFO */
23850 #define FLEXSPI_IPTXFSTS_FILL(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_FILL_SHIFT)) & FLEXSPI_IPTXFSTS_FILL_MASK)
23851 
23852 #define FLEXSPI_IPTXFSTS_WRCNTR_MASK             (0xFFFF0000U)
23853 #define FLEXSPI_IPTXFSTS_WRCNTR_SHIFT            (16U)
23854 /*! WRCNTR - Write Data Counter */
23855 #define FLEXSPI_IPTXFSTS_WRCNTR(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_WRCNTR_SHIFT)) & FLEXSPI_IPTXFSTS_WRCNTR_MASK)
23856 /*! @} */
23857 
23858 /*! @name RFDR - IP Receive FIFO Data 0..IP Receive FIFO Data 31 */
23859 /*! @{ */
23860 
23861 #define FLEXSPI_RFDR_RXDATA_MASK                 (0xFFFFFFFFU)
23862 #define FLEXSPI_RFDR_RXDATA_SHIFT                (0U)
23863 /*! RXDATA - Receive Data */
23864 #define FLEXSPI_RFDR_RXDATA(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_RFDR_RXDATA_SHIFT)) & FLEXSPI_RFDR_RXDATA_MASK)
23865 /*! @} */
23866 
23867 /* The count of FLEXSPI_RFDR */
23868 #define FLEXSPI_RFDR_COUNT                       (32U)
23869 
23870 /*! @name TFDR - IP TX FIFO Data 0..IP TX FIFO Data 31 */
23871 /*! @{ */
23872 
23873 #define FLEXSPI_TFDR_TXDATA_MASK                 (0xFFFFFFFFU)
23874 #define FLEXSPI_TFDR_TXDATA_SHIFT                (0U)
23875 /*! TXDATA - Transmit Data */
23876 #define FLEXSPI_TFDR_TXDATA(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_TFDR_TXDATA_SHIFT)) & FLEXSPI_TFDR_TXDATA_MASK)
23877 /*! @} */
23878 
23879 /* The count of FLEXSPI_TFDR */
23880 #define FLEXSPI_TFDR_COUNT                       (32U)
23881 
23882 /*! @name LUT - Lookup Table 0..Lookup Table 63 */
23883 /*! @{ */
23884 
23885 #define FLEXSPI_LUT_OPERAND0_MASK                (0xFFU)
23886 #define FLEXSPI_LUT_OPERAND0_SHIFT               (0U)
23887 /*! OPERAND0 - OPERAND0 */
23888 #define FLEXSPI_LUT_OPERAND0(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND0_SHIFT)) & FLEXSPI_LUT_OPERAND0_MASK)
23889 
23890 #define FLEXSPI_LUT_NUM_PADS0_MASK               (0x300U)
23891 #define FLEXSPI_LUT_NUM_PADS0_SHIFT              (8U)
23892 /*! NUM_PADS0 - NUM_PADS0 */
23893 #define FLEXSPI_LUT_NUM_PADS0(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS0_SHIFT)) & FLEXSPI_LUT_NUM_PADS0_MASK)
23894 
23895 #define FLEXSPI_LUT_OPCODE0_MASK                 (0xFC00U)
23896 #define FLEXSPI_LUT_OPCODE0_SHIFT                (10U)
23897 /*! OPCODE0 - OPCODE */
23898 #define FLEXSPI_LUT_OPCODE0(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE0_SHIFT)) & FLEXSPI_LUT_OPCODE0_MASK)
23899 
23900 #define FLEXSPI_LUT_OPERAND1_MASK                (0xFF0000U)
23901 #define FLEXSPI_LUT_OPERAND1_SHIFT               (16U)
23902 /*! OPERAND1 - OPERAND1 */
23903 #define FLEXSPI_LUT_OPERAND1(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND1_SHIFT)) & FLEXSPI_LUT_OPERAND1_MASK)
23904 
23905 #define FLEXSPI_LUT_NUM_PADS1_MASK               (0x3000000U)
23906 #define FLEXSPI_LUT_NUM_PADS1_SHIFT              (24U)
23907 /*! NUM_PADS1 - NUM_PADS1 */
23908 #define FLEXSPI_LUT_NUM_PADS1(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS1_SHIFT)) & FLEXSPI_LUT_NUM_PADS1_MASK)
23909 
23910 #define FLEXSPI_LUT_OPCODE1_MASK                 (0xFC000000U)
23911 #define FLEXSPI_LUT_OPCODE1_SHIFT                (26U)
23912 /*! OPCODE1 - OPCODE1 */
23913 #define FLEXSPI_LUT_OPCODE1(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE1_SHIFT)) & FLEXSPI_LUT_OPCODE1_MASK)
23914 /*! @} */
23915 
23916 /* The count of FLEXSPI_LUT */
23917 #define FLEXSPI_LUT_COUNT                        (64U)
23918 
23919 /*! @name HADDRSTART - HADDR REMAP Start Address */
23920 /*! @{ */
23921 
23922 #define FLEXSPI_HADDRSTART_REMAPEN_MASK          (0x1U)
23923 #define FLEXSPI_HADDRSTART_REMAPEN_SHIFT         (0U)
23924 /*! REMAPEN - AHB Bus Address Remap Enable
23925  *  0b0..HADDR REMAP Disabled
23926  *  0b1..HADDR REMAP Enabled
23927  */
23928 #define FLEXSPI_HADDRSTART_REMAPEN(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HADDRSTART_REMAPEN_SHIFT)) & FLEXSPI_HADDRSTART_REMAPEN_MASK)
23929 
23930 #define FLEXSPI_HADDRSTART_ADDRSTART_MASK        (0xFFFFF000U)
23931 #define FLEXSPI_HADDRSTART_ADDRSTART_SHIFT       (12U)
23932 /*! ADDRSTART - HADDR Start Address */
23933 #define FLEXSPI_HADDRSTART_ADDRSTART(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HADDRSTART_ADDRSTART_SHIFT)) & FLEXSPI_HADDRSTART_ADDRSTART_MASK)
23934 /*! @} */
23935 
23936 /*! @name HADDREND - HADDR REMAP END ADDR */
23937 /*! @{ */
23938 
23939 #define FLEXSPI_HADDREND_ENDSTART_MASK           (0xFFFFF000U)
23940 #define FLEXSPI_HADDREND_ENDSTART_SHIFT          (12U)
23941 /*! ENDSTART - End Address of HADDR Remap Range */
23942 #define FLEXSPI_HADDREND_ENDSTART(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HADDREND_ENDSTART_SHIFT)) & FLEXSPI_HADDREND_ENDSTART_MASK)
23943 /*! @} */
23944 
23945 /*! @name HADDROFFSET - HADDR Remap Offset */
23946 /*! @{ */
23947 
23948 #define FLEXSPI_HADDROFFSET_ADDROFFSET_MASK      (0xFFFFF000U)
23949 #define FLEXSPI_HADDROFFSET_ADDROFFSET_SHIFT     (12U)
23950 /*! ADDROFFSET - HADDR Offset */
23951 #define FLEXSPI_HADDROFFSET_ADDROFFSET(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HADDROFFSET_ADDROFFSET_SHIFT)) & FLEXSPI_HADDROFFSET_ADDROFFSET_MASK)
23952 /*! @} */
23953 
23954 /*! @name IPEDCTRL - IPED Function Control */
23955 /*! @{ */
23956 
23957 #define FLEXSPI_IPEDCTRL_CONFIG_MASK             (0x1U)
23958 #define FLEXSPI_IPEDCTRL_CONFIG_SHIFT            (0U)
23959 /*! CONFIG - IPED Mode Select
23960  *  0b0..Fully pipelined
23961  *  0b1..Not fully pipelined
23962  */
23963 #define FLEXSPI_IPEDCTRL_CONFIG(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTRL_CONFIG_SHIFT)) & FLEXSPI_IPEDCTRL_CONFIG_MASK)
23964 
23965 #define FLEXSPI_IPEDCTRL_IPED_EN_MASK            (0x2U)
23966 #define FLEXSPI_IPEDCTRL_IPED_EN_SHIFT           (1U)
23967 /*! IPED_EN - IPED Encryption and Decryption Enable
23968  *  0b0..Disable
23969  *  0b1..Enable
23970  */
23971 #define FLEXSPI_IPEDCTRL_IPED_EN(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTRL_IPED_EN_SHIFT)) & FLEXSPI_IPEDCTRL_IPED_EN_MASK)
23972 
23973 #define FLEXSPI_IPEDCTRL_IPWR_EN_MASK            (0x4U)
23974 #define FLEXSPI_IPEDCTRL_IPWR_EN_SHIFT           (2U)
23975 /*! IPWR_EN - IP Write IPED CTR Mode Encryption Enable
23976  *  0b0..Disable
23977  *  0b1..Enable
23978  */
23979 #define FLEXSPI_IPEDCTRL_IPWR_EN(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTRL_IPWR_EN_SHIFT)) & FLEXSPI_IPEDCTRL_IPWR_EN_MASK)
23980 
23981 #define FLEXSPI_IPEDCTRL_AHBWR_EN_MASK           (0x8U)
23982 #define FLEXSPI_IPEDCTRL_AHBWR_EN_SHIFT          (3U)
23983 /*! AHBWR_EN - AHB Write IPED CTR Mode Encryption Enable.
23984  *  0b0..Disable
23985  *  0b1..Enable
23986  */
23987 #define FLEXSPI_IPEDCTRL_AHBWR_EN(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTRL_AHBWR_EN_SHIFT)) & FLEXSPI_IPEDCTRL_AHBWR_EN_MASK)
23988 
23989 #define FLEXSPI_IPEDCTRL_AHBRD_EN_MASK           (0x10U)
23990 #define FLEXSPI_IPEDCTRL_AHBRD_EN_SHIFT          (4U)
23991 /*! AHBRD_EN - AHB Read IPED CTR Mode Decryption Enable
23992  *  0b0..Disable
23993  *  0b1..Enable
23994  */
23995 #define FLEXSPI_IPEDCTRL_AHBRD_EN(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTRL_AHBRD_EN_SHIFT)) & FLEXSPI_IPEDCTRL_AHBRD_EN_MASK)
23996 
23997 #define FLEXSPI_IPEDCTRL_IPGCMWR_MASK            (0x40U)
23998 #define FLEXSPI_IPEDCTRL_IPGCMWR_SHIFT           (6U)
23999 /*! IPGCMWR - IP Write GCM Mode Enable
24000  *  0b0..Disabled
24001  *  0b1..Enabled
24002  */
24003 #define FLEXSPI_IPEDCTRL_IPGCMWR(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTRL_IPGCMWR_SHIFT)) & FLEXSPI_IPEDCTRL_IPGCMWR_MASK)
24004 
24005 #define FLEXSPI_IPEDCTRL_AHGCMWR_MASK            (0x80U)
24006 #define FLEXSPI_IPEDCTRL_AHGCMWR_SHIFT           (7U)
24007 /*! AHGCMWR - AHB Write IPED GCM Mode Encryption Enable
24008  *  0b0..Disable
24009  *  0b1..Enable
24010  */
24011 #define FLEXSPI_IPEDCTRL_AHGCMWR(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTRL_AHGCMWR_SHIFT)) & FLEXSPI_IPEDCTRL_AHGCMWR_MASK)
24012 
24013 #define FLEXSPI_IPEDCTRL_AHBGCMRD_MASK           (0x100U)
24014 #define FLEXSPI_IPEDCTRL_AHBGCMRD_SHIFT          (8U)
24015 /*! AHBGCMRD - AHB Read IPED GCM Mode Decryption Enable
24016  *  0b0..Disable
24017  *  0b1..Enable
24018  */
24019 #define FLEXSPI_IPEDCTRL_AHBGCMRD(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTRL_AHBGCMRD_SHIFT)) & FLEXSPI_IPEDCTRL_AHBGCMRD_MASK)
24020 
24021 #define FLEXSPI_IPEDCTRL_IPED_PROTECT_MASK       (0x200U)
24022 #define FLEXSPI_IPEDCTRL_IPED_PROTECT_SHIFT      (9U)
24023 /*! IPED_PROTECT - IPED Protection
24024  *  0b0..No restrictions
24025  *  0b1..Only privileged controllers can write IPED registers.
24026  */
24027 #define FLEXSPI_IPEDCTRL_IPED_PROTECT(x)         (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTRL_IPED_PROTECT_SHIFT)) & FLEXSPI_IPEDCTRL_IPED_PROTECT_MASK)
24028 
24029 #define FLEXSPI_IPEDCTRL_IPED_SWRESET_MASK       (0x400U)
24030 #define FLEXSPI_IPEDCTRL_IPED_SWRESET_SHIFT      (10U)
24031 /*! IPED_SWRESET - Abort Current Decryption or Encryption
24032  *  0b0..No function.
24033  *  0b1..Aborts current decryption or encryption and waits for the next start operation.
24034  */
24035 #define FLEXSPI_IPEDCTRL_IPED_SWRESET(x)         (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTRL_IPED_SWRESET_SHIFT)) & FLEXSPI_IPEDCTRL_IPED_SWRESET_MASK)
24036 /*! @} */
24037 
24038 /*! @name IPSNSZSTART0 - IPS Nonsecure Region 0 Start Address */
24039 /*! @{ */
24040 
24041 #define FLEXSPI_IPSNSZSTART0_start_address_MASK  (0xFFFFF000U)
24042 #define FLEXSPI_IPSNSZSTART0_start_address_SHIFT (12U)
24043 /*! start_address - Start Address of Nonsecure Region */
24044 #define FLEXSPI_IPSNSZSTART0_start_address(x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPSNSZSTART0_start_address_SHIFT)) & FLEXSPI_IPSNSZSTART0_start_address_MASK)
24045 /*! @} */
24046 
24047 /*! @name IPSNSZEND0 - IPS Nonsecure Region 0 End Address */
24048 /*! @{ */
24049 
24050 #define FLEXSPI_IPSNSZEND0_end_address_MASK      (0xFFFFF000U)
24051 #define FLEXSPI_IPSNSZEND0_end_address_SHIFT     (12U)
24052 /*! end_address - End Address of Nonsecure Region */
24053 #define FLEXSPI_IPSNSZEND0_end_address(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPSNSZEND0_end_address_SHIFT)) & FLEXSPI_IPSNSZEND0_end_address_MASK)
24054 /*! @} */
24055 
24056 /*! @name IPSNSZSTART1 - IPS Nonsecure Region 1 Start Address */
24057 /*! @{ */
24058 
24059 #define FLEXSPI_IPSNSZSTART1_start_address_MASK  (0xFFFFF000U)
24060 #define FLEXSPI_IPSNSZSTART1_start_address_SHIFT (12U)
24061 /*! start_address - Start Address of Nonsecure Region */
24062 #define FLEXSPI_IPSNSZSTART1_start_address(x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPSNSZSTART1_start_address_SHIFT)) & FLEXSPI_IPSNSZSTART1_start_address_MASK)
24063 /*! @} */
24064 
24065 /*! @name IPSNSZEND1 - IPS Nonsecure Region 1 End Address */
24066 /*! @{ */
24067 
24068 #define FLEXSPI_IPSNSZEND1_end_address_MASK      (0xFFFFF000U)
24069 #define FLEXSPI_IPSNSZEND1_end_address_SHIFT     (12U)
24070 /*! end_address - End Address of Nonsecure Region */
24071 #define FLEXSPI_IPSNSZEND1_end_address(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPSNSZEND1_end_address_SHIFT)) & FLEXSPI_IPSNSZEND1_end_address_MASK)
24072 /*! @} */
24073 
24074 /*! @name AHBBUFREGIONSTART0 - Receive Buffer Start Address of Region 0 */
24075 /*! @{ */
24076 
24077 #define FLEXSPI_AHBBUFREGIONSTART0_START_ADDRESS_MASK (0xFFFFF000U)
24078 #define FLEXSPI_AHBBUFREGIONSTART0_START_ADDRESS_SHIFT (12U)
24079 /*! START_ADDRESS - Start Address of Prefetch Sub-Buffer Region */
24080 #define FLEXSPI_AHBBUFREGIONSTART0_START_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONSTART0_START_ADDRESS_SHIFT)) & FLEXSPI_AHBBUFREGIONSTART0_START_ADDRESS_MASK)
24081 /*! @} */
24082 
24083 /*! @name AHBBUFREGIONEND0 - Receive Buffer Region 0 End Address */
24084 /*! @{ */
24085 
24086 #define FLEXSPI_AHBBUFREGIONEND0_END_ADDRESS_MASK (0xFFFFF000U)
24087 #define FLEXSPI_AHBBUFREGIONEND0_END_ADDRESS_SHIFT (12U)
24088 /*! END_ADDRESS - End Address of Prefetch Sub-Buffer Region */
24089 #define FLEXSPI_AHBBUFREGIONEND0_END_ADDRESS(x)  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONEND0_END_ADDRESS_SHIFT)) & FLEXSPI_AHBBUFREGIONEND0_END_ADDRESS_MASK)
24090 /*! @} */
24091 
24092 /*! @name AHBBUFREGIONSTART1 - Receive Buffer Start Address of Region 1 */
24093 /*! @{ */
24094 
24095 #define FLEXSPI_AHBBUFREGIONSTART1_START_ADDRESS_MASK (0xFFFFF000U)
24096 #define FLEXSPI_AHBBUFREGIONSTART1_START_ADDRESS_SHIFT (12U)
24097 /*! START_ADDRESS - Start Address of Prefetch Sub-Buffer Region */
24098 #define FLEXSPI_AHBBUFREGIONSTART1_START_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONSTART1_START_ADDRESS_SHIFT)) & FLEXSPI_AHBBUFREGIONSTART1_START_ADDRESS_MASK)
24099 /*! @} */
24100 
24101 /*! @name AHBBUFREGIONEND1 - Receive Buffer Region 1 End Address */
24102 /*! @{ */
24103 
24104 #define FLEXSPI_AHBBUFREGIONEND1_END_ADDRESS_MASK (0xFFFFF000U)
24105 #define FLEXSPI_AHBBUFREGIONEND1_END_ADDRESS_SHIFT (12U)
24106 /*! END_ADDRESS - End Address of Prefetch Sub-Buffer Region */
24107 #define FLEXSPI_AHBBUFREGIONEND1_END_ADDRESS(x)  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONEND1_END_ADDRESS_SHIFT)) & FLEXSPI_AHBBUFREGIONEND1_END_ADDRESS_MASK)
24108 /*! @} */
24109 
24110 /*! @name AHBBUFREGIONSTART2 - Receive Buffer Start Address of Region 2 */
24111 /*! @{ */
24112 
24113 #define FLEXSPI_AHBBUFREGIONSTART2_START_ADDRESS_MASK (0xFFFFF000U)
24114 #define FLEXSPI_AHBBUFREGIONSTART2_START_ADDRESS_SHIFT (12U)
24115 /*! START_ADDRESS - Start Address of Prefetch Sub-Buffer Region */
24116 #define FLEXSPI_AHBBUFREGIONSTART2_START_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONSTART2_START_ADDRESS_SHIFT)) & FLEXSPI_AHBBUFREGIONSTART2_START_ADDRESS_MASK)
24117 /*! @} */
24118 
24119 /*! @name AHBBUFREGIONEND2 - Receive Buffer Region 2 End Address */
24120 /*! @{ */
24121 
24122 #define FLEXSPI_AHBBUFREGIONEND2_END_ADDRESS_MASK (0xFFFFF000U)
24123 #define FLEXSPI_AHBBUFREGIONEND2_END_ADDRESS_SHIFT (12U)
24124 /*! END_ADDRESS - End Address of Prefetch Sub-Buffer Region */
24125 #define FLEXSPI_AHBBUFREGIONEND2_END_ADDRESS(x)  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONEND2_END_ADDRESS_SHIFT)) & FLEXSPI_AHBBUFREGIONEND2_END_ADDRESS_MASK)
24126 /*! @} */
24127 
24128 /*! @name AHBBUFREGIONSTART3 - Receive Buffer Start Address of Region 3 */
24129 /*! @{ */
24130 
24131 #define FLEXSPI_AHBBUFREGIONSTART3_START_ADDRESS_MASK (0xFFFFF000U)
24132 #define FLEXSPI_AHBBUFREGIONSTART3_START_ADDRESS_SHIFT (12U)
24133 /*! START_ADDRESS - Start Address of Prefetch Sub-Buffer Region */
24134 #define FLEXSPI_AHBBUFREGIONSTART3_START_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONSTART3_START_ADDRESS_SHIFT)) & FLEXSPI_AHBBUFREGIONSTART3_START_ADDRESS_MASK)
24135 /*! @} */
24136 
24137 /*! @name AHBBUFREGIONEND3 - Receive Buffer Region 3 End Address */
24138 /*! @{ */
24139 
24140 #define FLEXSPI_AHBBUFREGIONEND3_END_ADDRESS_MASK (0xFFFFF000U)
24141 #define FLEXSPI_AHBBUFREGIONEND3_END_ADDRESS_SHIFT (12U)
24142 /*! END_ADDRESS - End Address of Prefetch Sub-Buffer Region */
24143 #define FLEXSPI_AHBBUFREGIONEND3_END_ADDRESS(x)  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONEND3_END_ADDRESS_SHIFT)) & FLEXSPI_AHBBUFREGIONEND3_END_ADDRESS_MASK)
24144 /*! @} */
24145 
24146 /*! @name IPEDCTXCTRLX_IPEDCTXCTRL - IPED context control 0..IPED context control 1 */
24147 /*! @{ */
24148 
24149 #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX0_FREEZE0_MASK (0x3U)
24150 #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX0_FREEZE0_SHIFT (0U)
24151 /*! CTX0_FREEZE0 - Context Register Freeze for Region 0 */
24152 #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX0_FREEZE0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX0_FREEZE0_SHIFT)) & FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX0_FREEZE0_MASK)
24153 
24154 #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX0_FREEZE1_MASK (0x3U)
24155 #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX0_FREEZE1_SHIFT (0U)
24156 /*! CTX0_FREEZE1 - Context Register Freeze for Region 0 */
24157 #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX0_FREEZE1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX0_FREEZE1_SHIFT)) & FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX0_FREEZE1_MASK)
24158 
24159 #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX1_FREEZE0_MASK (0xCU)
24160 #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX1_FREEZE0_SHIFT (2U)
24161 /*! CTX1_FREEZE0 - Context Register Freeze for Region 1 */
24162 #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX1_FREEZE0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX1_FREEZE0_SHIFT)) & FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX1_FREEZE0_MASK)
24163 
24164 #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX1_FREEZE1_MASK (0xCU)
24165 #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX1_FREEZE1_SHIFT (2U)
24166 /*! CTX1_FREEZE1 - Context Register Freeze for Region 1 */
24167 #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX1_FREEZE1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX1_FREEZE1_SHIFT)) & FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX1_FREEZE1_MASK)
24168 
24169 #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX2_FREEZE0_MASK (0x30U)
24170 #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX2_FREEZE0_SHIFT (4U)
24171 /*! CTX2_FREEZE0 - Context Register Freeze for Region 2 */
24172 #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX2_FREEZE0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX2_FREEZE0_SHIFT)) & FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX2_FREEZE0_MASK)
24173 
24174 #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX2_FREEZE1_MASK (0x30U)
24175 #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX2_FREEZE1_SHIFT (4U)
24176 /*! CTX2_FREEZE1 - Context Register Freeze for Region 2 */
24177 #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX2_FREEZE1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX2_FREEZE1_SHIFT)) & FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX2_FREEZE1_MASK)
24178 
24179 #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX3_FREEZE0_MASK (0xC0U)
24180 #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX3_FREEZE0_SHIFT (6U)
24181 /*! CTX3_FREEZE0 - Context Register Freeze for Region 3 */
24182 #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX3_FREEZE0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX3_FREEZE0_SHIFT)) & FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX3_FREEZE0_MASK)
24183 
24184 #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX3_FREEZE1_MASK (0xC0U)
24185 #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX3_FREEZE1_SHIFT (6U)
24186 /*! CTX3_FREEZE1 - Context Register Freeze for Region 3 */
24187 #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX3_FREEZE1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX3_FREEZE1_SHIFT)) & FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX3_FREEZE1_MASK)
24188 
24189 #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX4_FREEZE0_MASK (0x300U)
24190 #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX4_FREEZE0_SHIFT (8U)
24191 /*! CTX4_FREEZE0 - Context Register Freeze for Region 4 */
24192 #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX4_FREEZE0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX4_FREEZE0_SHIFT)) & FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX4_FREEZE0_MASK)
24193 
24194 #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX4_FREEZE1_MASK (0x300U)
24195 #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX4_FREEZE1_SHIFT (8U)
24196 /*! CTX4_FREEZE1 - Context Register Freeze for Region 4 */
24197 #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX4_FREEZE1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX4_FREEZE1_SHIFT)) & FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX4_FREEZE1_MASK)
24198 
24199 #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX5_FREEZE0_MASK (0xC00U)
24200 #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX5_FREEZE0_SHIFT (10U)
24201 /*! CTX5_FREEZE0 - Context Register Freeze for Region 5 */
24202 #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX5_FREEZE0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX5_FREEZE0_SHIFT)) & FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX5_FREEZE0_MASK)
24203 
24204 #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX5_FREEZE1_MASK (0xC00U)
24205 #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX5_FREEZE1_SHIFT (10U)
24206 /*! CTX5_FREEZE1 - Context Register Freeze for Region 5 */
24207 #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX5_FREEZE1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX5_FREEZE1_SHIFT)) & FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX5_FREEZE1_MASK)
24208 
24209 #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX6_FREEZE0_MASK (0x3000U)
24210 #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX6_FREEZE0_SHIFT (12U)
24211 /*! CTX6_FREEZE0 - Context Register Freeze for Region 6 */
24212 #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX6_FREEZE0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX6_FREEZE0_SHIFT)) & FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX6_FREEZE0_MASK)
24213 
24214 #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX6_FREEZE1_MASK (0x3000U)
24215 #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX6_FREEZE1_SHIFT (12U)
24216 /*! CTX6_FREEZE1 - Context Register Freeze for Region 6 */
24217 #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX6_FREEZE1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX6_FREEZE1_SHIFT)) & FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX6_FREEZE1_MASK)
24218 /*! @} */
24219 
24220 /* The count of FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL */
24221 #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_COUNT   (2U)
24222 
24223 /*! @name IPEDCTX0IV0 - IPED Context0 IV0 */
24224 /*! @{ */
24225 
24226 #define FLEXSPI_IPEDCTX0IV0_CTX0_IV0_MASK        (0xFFFFFFFFU)
24227 #define FLEXSPI_IPEDCTX0IV0_CTX0_IV0_SHIFT       (0U)
24228 /*! CTX0_IV0 - Lowest 32 bits of IV for region 0. */
24229 #define FLEXSPI_IPEDCTX0IV0_CTX0_IV0(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX0IV0_CTX0_IV0_SHIFT)) & FLEXSPI_IPEDCTX0IV0_CTX0_IV0_MASK)
24230 /*! @} */
24231 
24232 /*! @name IPEDCTX0IV1 - IPED Context0 IV1 */
24233 /*! @{ */
24234 
24235 #define FLEXSPI_IPEDCTX0IV1_CTX0_IV1_MASK        (0xFFFFFFFFU)
24236 #define FLEXSPI_IPEDCTX0IV1_CTX0_IV1_SHIFT       (0U)
24237 /*! CTX0_IV1 - Highest 32 bits of IV for region 0. */
24238 #define FLEXSPI_IPEDCTX0IV1_CTX0_IV1(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX0IV1_CTX0_IV1_SHIFT)) & FLEXSPI_IPEDCTX0IV1_CTX0_IV1_MASK)
24239 /*! @} */
24240 
24241 /*! @name IPEDCTX0START - Start Address of Region */
24242 /*! @{ */
24243 
24244 #define FLEXSPI_IPEDCTX0START_GCM_MASK           (0x1U)
24245 #define FLEXSPI_IPEDCTX0START_GCM_SHIFT          (0U)
24246 /*! GCM - GCM Mode Enable
24247  *  0b0..Disabled. CTR mode is used.
24248  *  0b1..Enabled. GCM mode is used.
24249  */
24250 #define FLEXSPI_IPEDCTX0START_GCM(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX0START_GCM_SHIFT)) & FLEXSPI_IPEDCTX0START_GCM_MASK)
24251 
24252 #define FLEXSPI_IPEDCTX0START_ahbbuserror_dis_MASK (0x2U)
24253 #define FLEXSPI_IPEDCTX0START_ahbbuserror_dis_SHIFT (1U)
24254 /*! ahbbuserror_dis - AHB Bus Error Disable
24255  *  0b0..AHB bus errors enabled
24256  *  0b1..AHB bus errors disabled
24257  */
24258 #define FLEXSPI_IPEDCTX0START_ahbbuserror_dis(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX0START_ahbbuserror_dis_SHIFT)) & FLEXSPI_IPEDCTX0START_ahbbuserror_dis_MASK)
24259 
24260 #define FLEXSPI_IPEDCTX0START_start_address_MASK (0xFFFFFF00U)
24261 #define FLEXSPI_IPEDCTX0START_start_address_SHIFT (8U)
24262 /*! start_address - Start Address */
24263 #define FLEXSPI_IPEDCTX0START_start_address(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX0START_start_address_SHIFT)) & FLEXSPI_IPEDCTX0START_start_address_MASK)
24264 /*! @} */
24265 
24266 /*! @name IPEDCTX0END - End Address of Region */
24267 /*! @{ */
24268 
24269 #define FLEXSPI_IPEDCTX0END_end_address_MASK     (0xFFFFFF00U)
24270 #define FLEXSPI_IPEDCTX0END_end_address_SHIFT    (8U)
24271 /*! end_address - End Address of IPED Region */
24272 #define FLEXSPI_IPEDCTX0END_end_address(x)       (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX0END_end_address_SHIFT)) & FLEXSPI_IPEDCTX0END_end_address_MASK)
24273 /*! @} */
24274 
24275 /*! @name IPEDCTX0AAD0 - IPED Context0 Additional Authenticated Data0 */
24276 /*! @{ */
24277 
24278 #define FLEXSPI_IPEDCTX0AAD0_CTX0_AAD0_MASK      (0xFFFFFFFFU)
24279 #define FLEXSPI_IPEDCTX0AAD0_CTX0_AAD0_SHIFT     (0U)
24280 /*! CTX0_AAD0 - CTX AAD */
24281 #define FLEXSPI_IPEDCTX0AAD0_CTX0_AAD0(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX0AAD0_CTX0_AAD0_SHIFT)) & FLEXSPI_IPEDCTX0AAD0_CTX0_AAD0_MASK)
24282 /*! @} */
24283 
24284 /*! @name IPEDCTX0AAD1 - IPED Context0 Additional Authenticated Data1 */
24285 /*! @{ */
24286 
24287 #define FLEXSPI_IPEDCTX0AAD1_CTX0_AAD1_MASK      (0xFFFFFFFFU)
24288 #define FLEXSPI_IPEDCTX0AAD1_CTX0_AAD1_SHIFT     (0U)
24289 /*! CTX0_AAD1 - CTX AAD */
24290 #define FLEXSPI_IPEDCTX0AAD1_CTX0_AAD1(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX0AAD1_CTX0_AAD1_SHIFT)) & FLEXSPI_IPEDCTX0AAD1_CTX0_AAD1_MASK)
24291 /*! @} */
24292 
24293 /*! @name IPEDCTX1IV0 - IPED Context1 IV0 */
24294 /*! @{ */
24295 
24296 #define FLEXSPI_IPEDCTX1IV0_CTX1_IV0_MASK        (0xFFFFFFFFU)
24297 #define FLEXSPI_IPEDCTX1IV0_CTX1_IV0_SHIFT       (0U)
24298 /*! CTX1_IV0 - Lowest 32 bits of IV for region 1. */
24299 #define FLEXSPI_IPEDCTX1IV0_CTX1_IV0(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX1IV0_CTX1_IV0_SHIFT)) & FLEXSPI_IPEDCTX1IV0_CTX1_IV0_MASK)
24300 /*! @} */
24301 
24302 /*! @name IPEDCTX1IV1 - IPED Context1 IV1 */
24303 /*! @{ */
24304 
24305 #define FLEXSPI_IPEDCTX1IV1_CTX1_IV1_MASK        (0xFFFFFFFFU)
24306 #define FLEXSPI_IPEDCTX1IV1_CTX1_IV1_SHIFT       (0U)
24307 /*! CTX1_IV1 - Highest 32 bits of IV for region 1. */
24308 #define FLEXSPI_IPEDCTX1IV1_CTX1_IV1(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX1IV1_CTX1_IV1_SHIFT)) & FLEXSPI_IPEDCTX1IV1_CTX1_IV1_MASK)
24309 /*! @} */
24310 
24311 /*! @name IPEDCTX1START - Start Address of Region */
24312 /*! @{ */
24313 
24314 #define FLEXSPI_IPEDCTX1START_GCM_MASK           (0x1U)
24315 #define FLEXSPI_IPEDCTX1START_GCM_SHIFT          (0U)
24316 /*! GCM - GCM Mode Enable
24317  *  0b0..Disabled. CTR mode is used.
24318  *  0b1..Enabled. GCM mode is used.
24319  */
24320 #define FLEXSPI_IPEDCTX1START_GCM(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX1START_GCM_SHIFT)) & FLEXSPI_IPEDCTX1START_GCM_MASK)
24321 
24322 #define FLEXSPI_IPEDCTX1START_ahbbuserror_dis_MASK (0x2U)
24323 #define FLEXSPI_IPEDCTX1START_ahbbuserror_dis_SHIFT (1U)
24324 /*! ahbbuserror_dis - AHB Bus Error Disable
24325  *  0b0..AHB bus errors enabled
24326  *  0b1..AHB bus errors disabled
24327  */
24328 #define FLEXSPI_IPEDCTX1START_ahbbuserror_dis(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX1START_ahbbuserror_dis_SHIFT)) & FLEXSPI_IPEDCTX1START_ahbbuserror_dis_MASK)
24329 
24330 #define FLEXSPI_IPEDCTX1START_start_address_MASK (0xFFFFFF00U)
24331 #define FLEXSPI_IPEDCTX1START_start_address_SHIFT (8U)
24332 /*! start_address - Start Address */
24333 #define FLEXSPI_IPEDCTX1START_start_address(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX1START_start_address_SHIFT)) & FLEXSPI_IPEDCTX1START_start_address_MASK)
24334 /*! @} */
24335 
24336 /*! @name IPEDCTX1END - End Address of Region */
24337 /*! @{ */
24338 
24339 #define FLEXSPI_IPEDCTX1END_end_address_MASK     (0xFFFFFF00U)
24340 #define FLEXSPI_IPEDCTX1END_end_address_SHIFT    (8U)
24341 /*! end_address - End Address of IPED Region */
24342 #define FLEXSPI_IPEDCTX1END_end_address(x)       (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX1END_end_address_SHIFT)) & FLEXSPI_IPEDCTX1END_end_address_MASK)
24343 /*! @} */
24344 
24345 /*! @name IPEDCTX1AAD0 - IPED Context1 Additional Authenticated Data0 */
24346 /*! @{ */
24347 
24348 #define FLEXSPI_IPEDCTX1AAD0_CTX1_AAD0_MASK      (0xFFFFFFFFU)
24349 #define FLEXSPI_IPEDCTX1AAD0_CTX1_AAD0_SHIFT     (0U)
24350 /*! CTX1_AAD0 - CTX AAD */
24351 #define FLEXSPI_IPEDCTX1AAD0_CTX1_AAD0(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX1AAD0_CTX1_AAD0_SHIFT)) & FLEXSPI_IPEDCTX1AAD0_CTX1_AAD0_MASK)
24352 /*! @} */
24353 
24354 /*! @name IPEDCTX1AAD1 - IPED Context1 Additional Authenticated Data1 */
24355 /*! @{ */
24356 
24357 #define FLEXSPI_IPEDCTX1AAD1_CTX1_AAD1_MASK      (0xFFFFFFFFU)
24358 #define FLEXSPI_IPEDCTX1AAD1_CTX1_AAD1_SHIFT     (0U)
24359 /*! CTX1_AAD1 - CTX AAD */
24360 #define FLEXSPI_IPEDCTX1AAD1_CTX1_AAD1(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX1AAD1_CTX1_AAD1_SHIFT)) & FLEXSPI_IPEDCTX1AAD1_CTX1_AAD1_MASK)
24361 /*! @} */
24362 
24363 /*! @name IPEDCTX2IV0 - IPED Context2 IV0 */
24364 /*! @{ */
24365 
24366 #define FLEXSPI_IPEDCTX2IV0_CTX2_IV0_MASK        (0xFFFFFFFFU)
24367 #define FLEXSPI_IPEDCTX2IV0_CTX2_IV0_SHIFT       (0U)
24368 /*! CTX2_IV0 - Lowest 32 bits of IV for region 2. */
24369 #define FLEXSPI_IPEDCTX2IV0_CTX2_IV0(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX2IV0_CTX2_IV0_SHIFT)) & FLEXSPI_IPEDCTX2IV0_CTX2_IV0_MASK)
24370 /*! @} */
24371 
24372 /*! @name IPEDCTX2IV1 - IPED Context2 IV1 */
24373 /*! @{ */
24374 
24375 #define FLEXSPI_IPEDCTX2IV1_CTX2_IV1_MASK        (0xFFFFFFFFU)
24376 #define FLEXSPI_IPEDCTX2IV1_CTX2_IV1_SHIFT       (0U)
24377 /*! CTX2_IV1 - Highest 32 bits of IV for region 2. */
24378 #define FLEXSPI_IPEDCTX2IV1_CTX2_IV1(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX2IV1_CTX2_IV1_SHIFT)) & FLEXSPI_IPEDCTX2IV1_CTX2_IV1_MASK)
24379 /*! @} */
24380 
24381 /*! @name IPEDCTX2START - Start Address of Region */
24382 /*! @{ */
24383 
24384 #define FLEXSPI_IPEDCTX2START_GCM_MASK           (0x1U)
24385 #define FLEXSPI_IPEDCTX2START_GCM_SHIFT          (0U)
24386 /*! GCM - GCM Mode Enable
24387  *  0b0..Disabled. CTR mode is used.
24388  *  0b1..Enabled. GCM mode is used.
24389  */
24390 #define FLEXSPI_IPEDCTX2START_GCM(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX2START_GCM_SHIFT)) & FLEXSPI_IPEDCTX2START_GCM_MASK)
24391 
24392 #define FLEXSPI_IPEDCTX2START_ahbbuserror_dis_MASK (0x2U)
24393 #define FLEXSPI_IPEDCTX2START_ahbbuserror_dis_SHIFT (1U)
24394 /*! ahbbuserror_dis - AHB Bus Error Disable
24395  *  0b0..AHB bus errors enabled
24396  *  0b1..AHB bus errors disabled
24397  */
24398 #define FLEXSPI_IPEDCTX2START_ahbbuserror_dis(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX2START_ahbbuserror_dis_SHIFT)) & FLEXSPI_IPEDCTX2START_ahbbuserror_dis_MASK)
24399 
24400 #define FLEXSPI_IPEDCTX2START_start_address_MASK (0xFFFFFF00U)
24401 #define FLEXSPI_IPEDCTX2START_start_address_SHIFT (8U)
24402 /*! start_address - Start Address */
24403 #define FLEXSPI_IPEDCTX2START_start_address(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX2START_start_address_SHIFT)) & FLEXSPI_IPEDCTX2START_start_address_MASK)
24404 /*! @} */
24405 
24406 /*! @name IPEDCTX2END - End Address of Region */
24407 /*! @{ */
24408 
24409 #define FLEXSPI_IPEDCTX2END_end_address_MASK     (0xFFFFFF00U)
24410 #define FLEXSPI_IPEDCTX2END_end_address_SHIFT    (8U)
24411 /*! end_address - End Address of IPED Region */
24412 #define FLEXSPI_IPEDCTX2END_end_address(x)       (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX2END_end_address_SHIFT)) & FLEXSPI_IPEDCTX2END_end_address_MASK)
24413 /*! @} */
24414 
24415 /*! @name IPEDCTX2AAD0 - IPED Context2 Additional Authenticated Data0 */
24416 /*! @{ */
24417 
24418 #define FLEXSPI_IPEDCTX2AAD0_CTX2_AAD0_MASK      (0xFFFFFFFFU)
24419 #define FLEXSPI_IPEDCTX2AAD0_CTX2_AAD0_SHIFT     (0U)
24420 /*! CTX2_AAD0 - CTX AAD */
24421 #define FLEXSPI_IPEDCTX2AAD0_CTX2_AAD0(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX2AAD0_CTX2_AAD0_SHIFT)) & FLEXSPI_IPEDCTX2AAD0_CTX2_AAD0_MASK)
24422 /*! @} */
24423 
24424 /*! @name IPEDCTX2AAD1 - IPED Context2 Additional Authenticated Data1 */
24425 /*! @{ */
24426 
24427 #define FLEXSPI_IPEDCTX2AAD1_CTX2_AAD1_MASK      (0xFFFFFFFFU)
24428 #define FLEXSPI_IPEDCTX2AAD1_CTX2_AAD1_SHIFT     (0U)
24429 /*! CTX2_AAD1 - CTX AAD */
24430 #define FLEXSPI_IPEDCTX2AAD1_CTX2_AAD1(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX2AAD1_CTX2_AAD1_SHIFT)) & FLEXSPI_IPEDCTX2AAD1_CTX2_AAD1_MASK)
24431 /*! @} */
24432 
24433 /*! @name IPEDCTX3IV0 - IPED Context3 IV0 */
24434 /*! @{ */
24435 
24436 #define FLEXSPI_IPEDCTX3IV0_CTX3_IV0_MASK        (0xFFFFFFFFU)
24437 #define FLEXSPI_IPEDCTX3IV0_CTX3_IV0_SHIFT       (0U)
24438 /*! CTX3_IV0 - Lowest 32 bits of IV for region 3. */
24439 #define FLEXSPI_IPEDCTX3IV0_CTX3_IV0(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX3IV0_CTX3_IV0_SHIFT)) & FLEXSPI_IPEDCTX3IV0_CTX3_IV0_MASK)
24440 /*! @} */
24441 
24442 /*! @name IPEDCTX3IV1 - IPED Context3 IV1 */
24443 /*! @{ */
24444 
24445 #define FLEXSPI_IPEDCTX3IV1_CTX3_IV1_MASK        (0xFFFFFFFFU)
24446 #define FLEXSPI_IPEDCTX3IV1_CTX3_IV1_SHIFT       (0U)
24447 /*! CTX3_IV1 - Highest 32 bits of IV for region 3. */
24448 #define FLEXSPI_IPEDCTX3IV1_CTX3_IV1(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX3IV1_CTX3_IV1_SHIFT)) & FLEXSPI_IPEDCTX3IV1_CTX3_IV1_MASK)
24449 /*! @} */
24450 
24451 /*! @name IPEDCTX3START - Start Address of Region */
24452 /*! @{ */
24453 
24454 #define FLEXSPI_IPEDCTX3START_GCM_MASK           (0x1U)
24455 #define FLEXSPI_IPEDCTX3START_GCM_SHIFT          (0U)
24456 /*! GCM - GCM Mode Enable
24457  *  0b0..Disabled. CTR mode is used.
24458  *  0b1..Enabled. GCM mode is used.
24459  */
24460 #define FLEXSPI_IPEDCTX3START_GCM(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX3START_GCM_SHIFT)) & FLEXSPI_IPEDCTX3START_GCM_MASK)
24461 
24462 #define FLEXSPI_IPEDCTX3START_ahbbuserror_dis_MASK (0x2U)
24463 #define FLEXSPI_IPEDCTX3START_ahbbuserror_dis_SHIFT (1U)
24464 /*! ahbbuserror_dis - AHB Bus Error Disable
24465  *  0b0..AHB bus errors enabled
24466  *  0b1..AHB bus errors disabled
24467  */
24468 #define FLEXSPI_IPEDCTX3START_ahbbuserror_dis(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX3START_ahbbuserror_dis_SHIFT)) & FLEXSPI_IPEDCTX3START_ahbbuserror_dis_MASK)
24469 
24470 #define FLEXSPI_IPEDCTX3START_start_address_MASK (0xFFFFFF00U)
24471 #define FLEXSPI_IPEDCTX3START_start_address_SHIFT (8U)
24472 /*! start_address - Start Address */
24473 #define FLEXSPI_IPEDCTX3START_start_address(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX3START_start_address_SHIFT)) & FLEXSPI_IPEDCTX3START_start_address_MASK)
24474 /*! @} */
24475 
24476 /*! @name IPEDCTX3END - End Address of Region */
24477 /*! @{ */
24478 
24479 #define FLEXSPI_IPEDCTX3END_end_address_MASK     (0xFFFFFF00U)
24480 #define FLEXSPI_IPEDCTX3END_end_address_SHIFT    (8U)
24481 /*! end_address - End Address of IPED Region */
24482 #define FLEXSPI_IPEDCTX3END_end_address(x)       (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX3END_end_address_SHIFT)) & FLEXSPI_IPEDCTX3END_end_address_MASK)
24483 /*! @} */
24484 
24485 /*! @name IPEDCTX3AAD0 - IPED Context3 Additional Authenticated Data0 */
24486 /*! @{ */
24487 
24488 #define FLEXSPI_IPEDCTX3AAD0_CTX3_AAD0_MASK      (0xFFFFFFFFU)
24489 #define FLEXSPI_IPEDCTX3AAD0_CTX3_AAD0_SHIFT     (0U)
24490 /*! CTX3_AAD0 - CTX AAD */
24491 #define FLEXSPI_IPEDCTX3AAD0_CTX3_AAD0(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX3AAD0_CTX3_AAD0_SHIFT)) & FLEXSPI_IPEDCTX3AAD0_CTX3_AAD0_MASK)
24492 /*! @} */
24493 
24494 /*! @name IPEDCTX3AAD1 - IPED Context3 Additional Authenticated Data1 */
24495 /*! @{ */
24496 
24497 #define FLEXSPI_IPEDCTX3AAD1_CTX3_AAD1_MASK      (0xFFFFFFFFU)
24498 #define FLEXSPI_IPEDCTX3AAD1_CTX3_AAD1_SHIFT     (0U)
24499 /*! CTX3_AAD1 - CTX AAD */
24500 #define FLEXSPI_IPEDCTX3AAD1_CTX3_AAD1(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX3AAD1_CTX3_AAD1_SHIFT)) & FLEXSPI_IPEDCTX3AAD1_CTX3_AAD1_MASK)
24501 /*! @} */
24502 
24503 /*! @name IPEDCTX4IV0 - IPED Context4 IV0 */
24504 /*! @{ */
24505 
24506 #define FLEXSPI_IPEDCTX4IV0_CTX4_IV0_MASK        (0xFFFFFFFFU)
24507 #define FLEXSPI_IPEDCTX4IV0_CTX4_IV0_SHIFT       (0U)
24508 /*! CTX4_IV0 - Lowest 32 bits of IV for region 4. */
24509 #define FLEXSPI_IPEDCTX4IV0_CTX4_IV0(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX4IV0_CTX4_IV0_SHIFT)) & FLEXSPI_IPEDCTX4IV0_CTX4_IV0_MASK)
24510 /*! @} */
24511 
24512 /*! @name IPEDCTX4IV1 - IPED Context4 IV1 */
24513 /*! @{ */
24514 
24515 #define FLEXSPI_IPEDCTX4IV1_CTX4_IV1_MASK        (0xFFFFFFFFU)
24516 #define FLEXSPI_IPEDCTX4IV1_CTX4_IV1_SHIFT       (0U)
24517 /*! CTX4_IV1 - Highest 32 bits of IV for region 4. */
24518 #define FLEXSPI_IPEDCTX4IV1_CTX4_IV1(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX4IV1_CTX4_IV1_SHIFT)) & FLEXSPI_IPEDCTX4IV1_CTX4_IV1_MASK)
24519 /*! @} */
24520 
24521 /*! @name IPEDCTX4START - Start Address of Region */
24522 /*! @{ */
24523 
24524 #define FLEXSPI_IPEDCTX4START_GCM_MASK           (0x1U)
24525 #define FLEXSPI_IPEDCTX4START_GCM_SHIFT          (0U)
24526 /*! GCM - GCM Mode Enable
24527  *  0b0..Disabled. CTR mode is used.
24528  *  0b1..Enabled. GCM mode is used.
24529  */
24530 #define FLEXSPI_IPEDCTX4START_GCM(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX4START_GCM_SHIFT)) & FLEXSPI_IPEDCTX4START_GCM_MASK)
24531 
24532 #define FLEXSPI_IPEDCTX4START_ahbbuserror_dis_MASK (0x2U)
24533 #define FLEXSPI_IPEDCTX4START_ahbbuserror_dis_SHIFT (1U)
24534 /*! ahbbuserror_dis - AHB Bus Error Disable
24535  *  0b0..AHB bus errors enabled
24536  *  0b1..AHB bus errors disabled
24537  */
24538 #define FLEXSPI_IPEDCTX4START_ahbbuserror_dis(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX4START_ahbbuserror_dis_SHIFT)) & FLEXSPI_IPEDCTX4START_ahbbuserror_dis_MASK)
24539 
24540 #define FLEXSPI_IPEDCTX4START_start_address_MASK (0xFFFFFF00U)
24541 #define FLEXSPI_IPEDCTX4START_start_address_SHIFT (8U)
24542 /*! start_address - Start Address */
24543 #define FLEXSPI_IPEDCTX4START_start_address(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX4START_start_address_SHIFT)) & FLEXSPI_IPEDCTX4START_start_address_MASK)
24544 /*! @} */
24545 
24546 /*! @name IPEDCTX4END - End Address of Region */
24547 /*! @{ */
24548 
24549 #define FLEXSPI_IPEDCTX4END_end_address_MASK     (0xFFFFFF00U)
24550 #define FLEXSPI_IPEDCTX4END_end_address_SHIFT    (8U)
24551 /*! end_address - End Address of IPED Region */
24552 #define FLEXSPI_IPEDCTX4END_end_address(x)       (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX4END_end_address_SHIFT)) & FLEXSPI_IPEDCTX4END_end_address_MASK)
24553 /*! @} */
24554 
24555 /*! @name IPEDCTX4AAD0 - IPED Context4 Additional Authenticated Data0 */
24556 /*! @{ */
24557 
24558 #define FLEXSPI_IPEDCTX4AAD0_CTX4_AAD0_MASK      (0xFFFFFFFFU)
24559 #define FLEXSPI_IPEDCTX4AAD0_CTX4_AAD0_SHIFT     (0U)
24560 /*! CTX4_AAD0 - CTX AAD */
24561 #define FLEXSPI_IPEDCTX4AAD0_CTX4_AAD0(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX4AAD0_CTX4_AAD0_SHIFT)) & FLEXSPI_IPEDCTX4AAD0_CTX4_AAD0_MASK)
24562 /*! @} */
24563 
24564 /*! @name IPEDCTX4AAD1 - IPED Context4 Additional Authenticated Data1 */
24565 /*! @{ */
24566 
24567 #define FLEXSPI_IPEDCTX4AAD1_CTX4_AAD1_MASK      (0xFFFFFFFFU)
24568 #define FLEXSPI_IPEDCTX4AAD1_CTX4_AAD1_SHIFT     (0U)
24569 /*! CTX4_AAD1 - CTX AAD */
24570 #define FLEXSPI_IPEDCTX4AAD1_CTX4_AAD1(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX4AAD1_CTX4_AAD1_SHIFT)) & FLEXSPI_IPEDCTX4AAD1_CTX4_AAD1_MASK)
24571 /*! @} */
24572 
24573 /*! @name IPEDCTX5IV0 - IPED Context5 IV0 */
24574 /*! @{ */
24575 
24576 #define FLEXSPI_IPEDCTX5IV0_CTX5_IV0_MASK        (0xFFFFFFFFU)
24577 #define FLEXSPI_IPEDCTX5IV0_CTX5_IV0_SHIFT       (0U)
24578 /*! CTX5_IV0 - Lowest 32 bits of IV for region 5. */
24579 #define FLEXSPI_IPEDCTX5IV0_CTX5_IV0(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX5IV0_CTX5_IV0_SHIFT)) & FLEXSPI_IPEDCTX5IV0_CTX5_IV0_MASK)
24580 /*! @} */
24581 
24582 /*! @name IPEDCTX5IV1 - IPED Context5 IV1 */
24583 /*! @{ */
24584 
24585 #define FLEXSPI_IPEDCTX5IV1_CTX5_IV1_MASK        (0xFFFFFFFFU)
24586 #define FLEXSPI_IPEDCTX5IV1_CTX5_IV1_SHIFT       (0U)
24587 /*! CTX5_IV1 - Highest 32 bits of IV for region 5. */
24588 #define FLEXSPI_IPEDCTX5IV1_CTX5_IV1(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX5IV1_CTX5_IV1_SHIFT)) & FLEXSPI_IPEDCTX5IV1_CTX5_IV1_MASK)
24589 /*! @} */
24590 
24591 /*! @name IPEDCTX5START - Start Address of Region */
24592 /*! @{ */
24593 
24594 #define FLEXSPI_IPEDCTX5START_GCM_MASK           (0x1U)
24595 #define FLEXSPI_IPEDCTX5START_GCM_SHIFT          (0U)
24596 /*! GCM - GCM Mode Enable
24597  *  0b0..Disabled. CTR mode is used.
24598  *  0b1..Enabled. GCM mode is used.
24599  */
24600 #define FLEXSPI_IPEDCTX5START_GCM(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX5START_GCM_SHIFT)) & FLEXSPI_IPEDCTX5START_GCM_MASK)
24601 
24602 #define FLEXSPI_IPEDCTX5START_ahbbuserror_dis_MASK (0x2U)
24603 #define FLEXSPI_IPEDCTX5START_ahbbuserror_dis_SHIFT (1U)
24604 /*! ahbbuserror_dis - AHB Bus Error Disable
24605  *  0b0..AHB bus errors enabled
24606  *  0b1..AHB bus errors disabled
24607  */
24608 #define FLEXSPI_IPEDCTX5START_ahbbuserror_dis(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX5START_ahbbuserror_dis_SHIFT)) & FLEXSPI_IPEDCTX5START_ahbbuserror_dis_MASK)
24609 
24610 #define FLEXSPI_IPEDCTX5START_start_address_MASK (0xFFFFFF00U)
24611 #define FLEXSPI_IPEDCTX5START_start_address_SHIFT (8U)
24612 /*! start_address - Start Address */
24613 #define FLEXSPI_IPEDCTX5START_start_address(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX5START_start_address_SHIFT)) & FLEXSPI_IPEDCTX5START_start_address_MASK)
24614 /*! @} */
24615 
24616 /*! @name IPEDCTX5END - End Address of Region */
24617 /*! @{ */
24618 
24619 #define FLEXSPI_IPEDCTX5END_end_address_MASK     (0xFFFFFF00U)
24620 #define FLEXSPI_IPEDCTX5END_end_address_SHIFT    (8U)
24621 /*! end_address - End Address of IPED Region */
24622 #define FLEXSPI_IPEDCTX5END_end_address(x)       (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX5END_end_address_SHIFT)) & FLEXSPI_IPEDCTX5END_end_address_MASK)
24623 /*! @} */
24624 
24625 /*! @name IPEDCTX5AAD0 - IPED Context5 Additional Authenticated Data0 */
24626 /*! @{ */
24627 
24628 #define FLEXSPI_IPEDCTX5AAD0_CTX5_AAD0_MASK      (0xFFFFFFFFU)
24629 #define FLEXSPI_IPEDCTX5AAD0_CTX5_AAD0_SHIFT     (0U)
24630 /*! CTX5_AAD0 - CTX AAD */
24631 #define FLEXSPI_IPEDCTX5AAD0_CTX5_AAD0(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX5AAD0_CTX5_AAD0_SHIFT)) & FLEXSPI_IPEDCTX5AAD0_CTX5_AAD0_MASK)
24632 /*! @} */
24633 
24634 /*! @name IPEDCTX5AAD1 - IPED Context5 Additional Authenticated Data1 */
24635 /*! @{ */
24636 
24637 #define FLEXSPI_IPEDCTX5AAD1_CTX5_AAD1_MASK      (0xFFFFFFFFU)
24638 #define FLEXSPI_IPEDCTX5AAD1_CTX5_AAD1_SHIFT     (0U)
24639 /*! CTX5_AAD1 - CTX AAD */
24640 #define FLEXSPI_IPEDCTX5AAD1_CTX5_AAD1(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX5AAD1_CTX5_AAD1_SHIFT)) & FLEXSPI_IPEDCTX5AAD1_CTX5_AAD1_MASK)
24641 /*! @} */
24642 
24643 /*! @name IPEDCTX6IV0 - IPED Context6 IV0 */
24644 /*! @{ */
24645 
24646 #define FLEXSPI_IPEDCTX6IV0_CTX6_IV0_MASK        (0xFFFFFFFFU)
24647 #define FLEXSPI_IPEDCTX6IV0_CTX6_IV0_SHIFT       (0U)
24648 /*! CTX6_IV0 - Lowest 32 bits of IV for region 6. */
24649 #define FLEXSPI_IPEDCTX6IV0_CTX6_IV0(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX6IV0_CTX6_IV0_SHIFT)) & FLEXSPI_IPEDCTX6IV0_CTX6_IV0_MASK)
24650 /*! @} */
24651 
24652 /*! @name IPEDCTX6IV1 - IPED Context6 IV1 */
24653 /*! @{ */
24654 
24655 #define FLEXSPI_IPEDCTX6IV1_CTX6_IV1_MASK        (0xFFFFFFFFU)
24656 #define FLEXSPI_IPEDCTX6IV1_CTX6_IV1_SHIFT       (0U)
24657 /*! CTX6_IV1 - Highest 32 bits of IV for region 6. */
24658 #define FLEXSPI_IPEDCTX6IV1_CTX6_IV1(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX6IV1_CTX6_IV1_SHIFT)) & FLEXSPI_IPEDCTX6IV1_CTX6_IV1_MASK)
24659 /*! @} */
24660 
24661 /*! @name IPEDCTX6START - Start Address of Region */
24662 /*! @{ */
24663 
24664 #define FLEXSPI_IPEDCTX6START_GCM_MASK           (0x1U)
24665 #define FLEXSPI_IPEDCTX6START_GCM_SHIFT          (0U)
24666 /*! GCM - GCM Mode Enable
24667  *  0b0..Disabled. CTR mode is used.
24668  *  0b1..Enabled. GCM mode is used.
24669  */
24670 #define FLEXSPI_IPEDCTX6START_GCM(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX6START_GCM_SHIFT)) & FLEXSPI_IPEDCTX6START_GCM_MASK)
24671 
24672 #define FLEXSPI_IPEDCTX6START_ahbbuserror_dis_MASK (0x2U)
24673 #define FLEXSPI_IPEDCTX6START_ahbbuserror_dis_SHIFT (1U)
24674 /*! ahbbuserror_dis - AHB Bus Error Disable
24675  *  0b0..AHB bus errors enabled
24676  *  0b1..AHB bus errors disabled
24677  */
24678 #define FLEXSPI_IPEDCTX6START_ahbbuserror_dis(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX6START_ahbbuserror_dis_SHIFT)) & FLEXSPI_IPEDCTX6START_ahbbuserror_dis_MASK)
24679 
24680 #define FLEXSPI_IPEDCTX6START_start_address_MASK (0xFFFFFF00U)
24681 #define FLEXSPI_IPEDCTX6START_start_address_SHIFT (8U)
24682 /*! start_address - Start Address */
24683 #define FLEXSPI_IPEDCTX6START_start_address(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX6START_start_address_SHIFT)) & FLEXSPI_IPEDCTX6START_start_address_MASK)
24684 /*! @} */
24685 
24686 /*! @name IPEDCTX6END - End Address of Region */
24687 /*! @{ */
24688 
24689 #define FLEXSPI_IPEDCTX6END_end_address_MASK     (0xFFFFFF00U)
24690 #define FLEXSPI_IPEDCTX6END_end_address_SHIFT    (8U)
24691 /*! end_address - End Address of IPED Region */
24692 #define FLEXSPI_IPEDCTX6END_end_address(x)       (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX6END_end_address_SHIFT)) & FLEXSPI_IPEDCTX6END_end_address_MASK)
24693 /*! @} */
24694 
24695 /*! @name IPEDCTX6AAD0 - IPED Context6 Additional Authenticated Data0 */
24696 /*! @{ */
24697 
24698 #define FLEXSPI_IPEDCTX6AAD0_CTX6_AAD0_MASK      (0xFFFFFFFFU)
24699 #define FLEXSPI_IPEDCTX6AAD0_CTX6_AAD0_SHIFT     (0U)
24700 /*! CTX6_AAD0 - CTX AAD */
24701 #define FLEXSPI_IPEDCTX6AAD0_CTX6_AAD0(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX6AAD0_CTX6_AAD0_SHIFT)) & FLEXSPI_IPEDCTX6AAD0_CTX6_AAD0_MASK)
24702 /*! @} */
24703 
24704 /*! @name IPEDCTX6AAD1 - IPED Context6 Additional Authenticated Data1 */
24705 /*! @{ */
24706 
24707 #define FLEXSPI_IPEDCTX6AAD1_CTX6_AAD1_MASK      (0xFFFFFFFFU)
24708 #define FLEXSPI_IPEDCTX6AAD1_CTX6_AAD1_SHIFT     (0U)
24709 /*! CTX6_AAD1 - CTX AAD */
24710 #define FLEXSPI_IPEDCTX6AAD1_CTX6_AAD1(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX6AAD1_CTX6_AAD1_SHIFT)) & FLEXSPI_IPEDCTX6AAD1_CTX6_AAD1_MASK)
24711 /*! @} */
24712 
24713 
24714 /*!
24715  * @}
24716  */ /* end of group FLEXSPI_Register_Masks */
24717 
24718 
24719 /* FLEXSPI - Peripheral instance base addresses */
24720 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
24721   /** Peripheral FLEXSPI0 base address */
24722   #define FLEXSPI0_BASE                            (0x500C8000u)
24723   /** Peripheral FLEXSPI0 base address */
24724   #define FLEXSPI0_BASE_NS                         (0x400C8000u)
24725   /** Peripheral FLEXSPI0 base pointer */
24726   #define FLEXSPI0                                 ((FLEXSPI_Type *)FLEXSPI0_BASE)
24727   /** Peripheral FLEXSPI0 base pointer */
24728   #define FLEXSPI0_NS                              ((FLEXSPI_Type *)FLEXSPI0_BASE_NS)
24729   /** Array initializer of FLEXSPI peripheral base addresses */
24730   #define FLEXSPI_BASE_ADDRS                       { FLEXSPI0_BASE }
24731   /** Array initializer of FLEXSPI peripheral base pointers */
24732   #define FLEXSPI_BASE_PTRS                        { FLEXSPI0 }
24733   /** Array initializer of FLEXSPI peripheral base addresses */
24734   #define FLEXSPI_BASE_ADDRS_NS                    { FLEXSPI0_BASE_NS }
24735   /** Array initializer of FLEXSPI peripheral base pointers */
24736   #define FLEXSPI_BASE_PTRS_NS                     { FLEXSPI0_NS }
24737 #else
24738   /** Peripheral FLEXSPI0 base address */
24739   #define FLEXSPI0_BASE                            (0x400C8000u)
24740   /** Peripheral FLEXSPI0 base pointer */
24741   #define FLEXSPI0                                 ((FLEXSPI_Type *)FLEXSPI0_BASE)
24742   /** Array initializer of FLEXSPI peripheral base addresses */
24743   #define FLEXSPI_BASE_ADDRS                       { FLEXSPI0_BASE }
24744   /** Array initializer of FLEXSPI peripheral base pointers */
24745   #define FLEXSPI_BASE_PTRS                        { FLEXSPI0 }
24746 #endif
24747 /** Interrupt vectors for the FLEXSPI peripheral type */
24748 #define FLEXSPI_IRQS                             { FLEXSPI0_IRQn }
24749 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
24750 /** FlexSPI0 AMBA base address */
24751 #define FlexSPI0_AMBA_BASE                        (0x18000000u)
24752 /** FlexSPI0 AMBA end address */
24753 #define FlexSPI0_AMBA_END                         (0x1FFFFFFFu)
24754 /** FlexSPI0 AMBA base address */
24755 #define FlexSPI0_AMBA_BASE_NS                     (0x08000000U)
24756 /** FlexSPI0 AMBA end address */
24757 #define FlexSPI0_AMBA_END_NS                      (0x0FFFFFFFU)
24758 /* FlexSPI0 alias1 base address. */
24759 #define FlexSPI0_ALIAS1_BASE                      (0x80000000U)
24760 /* FlexSPI0 alias1 base NS address. */
24761 #define FlexSPI0_ALIAS1_BASE_NS                   (0x90000000U)
24762 /* FlexSPI0 alias2 base address. */
24763 #define FlexSPI0_ALIAS2_BASE                      (0xA0000000U)
24764 /* FlexSPI0 alias2 base NS address. */
24765 #define FlexSPI0_ALIAS2_BASE_NS                   (0xB0000000U)
24766 #else
24767 /** FlexSPI0 AMBA base address */
24768 #define FlexSPI0_AMBA_BASE                        (0x08000000U)
24769 /** FlexSPI0 AMBA end address */
24770 #define FlexSPI0_AMBA_END                         (0x0FFFFFFFU)
24771 /* FlexSPI0 alias1 base address. */
24772 #define FlexSPI0_ALIAS1_BASE                      (0x80000000U)
24773 /* FlexSPI0 alias2 base address. */
24774 #define FlexSPI0_ALIAS2_BASE                      (0xA0000000U)
24775 #endif
24776 
24777 
24778 /*!
24779  * @}
24780  */ /* end of group FLEXSPI_Peripheral_Access_Layer */
24781 
24782 
24783 /* ----------------------------------------------------------------------------
24784    -- FMU Peripheral Access Layer
24785    ---------------------------------------------------------------------------- */
24786 
24787 /*!
24788  * @addtogroup FMU_Peripheral_Access_Layer FMU Peripheral Access Layer
24789  * @{
24790  */
24791 
24792 /** FMU - Register Layout Typedef */
24793 typedef struct {
24794   __IO uint32_t FSTAT;                             /**< Flash Status Register, offset: 0x0 */
24795   __IO uint32_t FCNFG;                             /**< Flash Configuration Register, offset: 0x4 */
24796   __IO uint32_t FCTRL;                             /**< Flash Control Register, offset: 0x8 */
24797        uint8_t RESERVED_0[4];
24798   __IO uint32_t FCCOB[8];                          /**< Flash Common Command Object Registers, array offset: 0x10, array step: 0x4 */
24799 } FMU_Type;
24800 
24801 /* ----------------------------------------------------------------------------
24802    -- FMU Register Masks
24803    ---------------------------------------------------------------------------- */
24804 
24805 /*!
24806  * @addtogroup FMU_Register_Masks FMU Register Masks
24807  * @{
24808  */
24809 
24810 /*! @name FSTAT - Flash Status Register */
24811 /*! @{ */
24812 
24813 #define FMU_FSTAT_FAIL_MASK                      (0x1U)
24814 #define FMU_FSTAT_FAIL_SHIFT                     (0U)
24815 /*! FAIL - Command Fail Flag
24816  *  0b0..Error not detected
24817  *  0b1..Error detected
24818  */
24819 #define FMU_FSTAT_FAIL(x)                        (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_FAIL_SHIFT)) & FMU_FSTAT_FAIL_MASK)
24820 
24821 #define FMU_FSTAT_CMDABT_MASK                    (0x4U)
24822 #define FMU_FSTAT_CMDABT_SHIFT                   (2U)
24823 /*! CMDABT - Command Abort Flag
24824  *  0b0..No command abort detected
24825  *  0b1..Command abort detected
24826  */
24827 #define FMU_FSTAT_CMDABT(x)                      (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_CMDABT_SHIFT)) & FMU_FSTAT_CMDABT_MASK)
24828 
24829 #define FMU_FSTAT_PVIOL_MASK                     (0x10U)
24830 #define FMU_FSTAT_PVIOL_SHIFT                    (4U)
24831 /*! PVIOL - Command Protection Violation Flag
24832  *  0b0..No protection violation detected
24833  *  0b1..Protection violation detected
24834  */
24835 #define FMU_FSTAT_PVIOL(x)                       (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_PVIOL_SHIFT)) & FMU_FSTAT_PVIOL_MASK)
24836 
24837 #define FMU_FSTAT_ACCERR_MASK                    (0x20U)
24838 #define FMU_FSTAT_ACCERR_SHIFT                   (5U)
24839 /*! ACCERR - Command Access Error Flag
24840  *  0b0..No access error detected
24841  *  0b1..Access error detected
24842  */
24843 #define FMU_FSTAT_ACCERR(x)                      (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_ACCERR_SHIFT)) & FMU_FSTAT_ACCERR_MASK)
24844 
24845 #define FMU_FSTAT_CWSABT_MASK                    (0x40U)
24846 #define FMU_FSTAT_CWSABT_SHIFT                   (6U)
24847 /*! CWSABT - Command Write Sequence Abort Flag
24848  *  0b0..Command write sequence not aborted
24849  *  0b1..Command write sequence aborted
24850  */
24851 #define FMU_FSTAT_CWSABT(x)                      (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_CWSABT_SHIFT)) & FMU_FSTAT_CWSABT_MASK)
24852 
24853 #define FMU_FSTAT_CCIF_MASK                      (0x80U)
24854 #define FMU_FSTAT_CCIF_SHIFT                     (7U)
24855 /*! CCIF - Command Complete Interrupt Flag
24856  *  0b0..Flash command, initialization, or power mode recovery in progress
24857  *  0b1..Flash command, initialization, or power mode recovery has completed
24858  */
24859 #define FMU_FSTAT_CCIF(x)                        (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_CCIF_SHIFT)) & FMU_FSTAT_CCIF_MASK)
24860 
24861 #define FMU_FSTAT_CMDPRT_MASK                    (0x300U)
24862 #define FMU_FSTAT_CMDPRT_SHIFT                   (8U)
24863 /*! CMDPRT - Command protection level
24864  *  0b00..Secure, normal access
24865  *  0b01..Secure, privileged access
24866  *  0b10..Nonsecure, normal access
24867  *  0b11..Nonsecure, privileged access
24868  */
24869 #define FMU_FSTAT_CMDPRT(x)                      (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_CMDPRT_SHIFT)) & FMU_FSTAT_CMDPRT_MASK)
24870 
24871 #define FMU_FSTAT_CMDP_MASK                      (0x800U)
24872 #define FMU_FSTAT_CMDP_SHIFT                     (11U)
24873 /*! CMDP - Command protection status flag
24874  *  0b0..Command protection level and domain ID are stale
24875  *  0b1..Command protection level (CMDPRT) and domain ID (CMDDID) are set
24876  */
24877 #define FMU_FSTAT_CMDP(x)                        (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_CMDP_SHIFT)) & FMU_FSTAT_CMDP_MASK)
24878 
24879 #define FMU_FSTAT_CMDDID_MASK                    (0xF000U)
24880 #define FMU_FSTAT_CMDDID_SHIFT                   (12U)
24881 /*! CMDDID - Command domain ID */
24882 #define FMU_FSTAT_CMDDID(x)                      (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_CMDDID_SHIFT)) & FMU_FSTAT_CMDDID_MASK)
24883 
24884 #define FMU_FSTAT_DFDIF_MASK                     (0x10000U)
24885 #define FMU_FSTAT_DFDIF_SHIFT                    (16U)
24886 /*! DFDIF - Double Bit Fault Detect Interrupt Flag
24887  *  0b0..Double bit fault not detected during a valid flash read access
24888  *  0b1..Double bit fault detected (or FCTRL[FDFD] is set) during a valid flash read access
24889  */
24890 #define FMU_FSTAT_DFDIF(x)                       (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_DFDIF_SHIFT)) & FMU_FSTAT_DFDIF_MASK)
24891 
24892 #define FMU_FSTAT_SALV_USED_MASK                 (0x20000U)
24893 #define FMU_FSTAT_SALV_USED_SHIFT                (17U)
24894 /*! SALV_USED - Salvage Used for Erase operation
24895  *  0b0..Salvage not used during last operation
24896  *  0b1..Salvage used during the last erase operation
24897  */
24898 #define FMU_FSTAT_SALV_USED(x)                   (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_SALV_USED_SHIFT)) & FMU_FSTAT_SALV_USED_MASK)
24899 
24900 #define FMU_FSTAT_PEWEN_MASK                     (0x3000000U)
24901 #define FMU_FSTAT_PEWEN_SHIFT                    (24U)
24902 /*! PEWEN - Program-Erase Write Enable Control
24903  *  0b00..Writes are not enabled
24904  *  0b01..Writes are enabled for one flash or IFR phrase (phrase programming, sector erase)
24905  *  0b10..Writes are enabled for one flash or IFR page (page programming)
24906  *  0b11..Reserved
24907  */
24908 #define FMU_FSTAT_PEWEN(x)                       (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_PEWEN_SHIFT)) & FMU_FSTAT_PEWEN_MASK)
24909 
24910 #define FMU_FSTAT_PERDY_MASK                     (0x80000000U)
24911 #define FMU_FSTAT_PERDY_SHIFT                    (31U)
24912 /*! PERDY - Program-Erase Ready Control/Status Flag
24913  *  0b0..Program or sector erase command operation not stalled
24914  *  0b1..Program or sector erase command operation ready to execute
24915  */
24916 #define FMU_FSTAT_PERDY(x)                       (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_PERDY_SHIFT)) & FMU_FSTAT_PERDY_MASK)
24917 /*! @} */
24918 
24919 /*! @name FCNFG - Flash Configuration Register */
24920 /*! @{ */
24921 
24922 #define FMU_FCNFG_CCIE_MASK                      (0x80U)
24923 #define FMU_FCNFG_CCIE_SHIFT                     (7U)
24924 /*! CCIE - Command Complete Interrupt Enable
24925  *  0b0..Command complete interrupt disabled
24926  *  0b1..Command complete interrupt enabled
24927  */
24928 #define FMU_FCNFG_CCIE(x)                        (((uint32_t)(((uint32_t)(x)) << FMU_FCNFG_CCIE_SHIFT)) & FMU_FCNFG_CCIE_MASK)
24929 
24930 #define FMU_FCNFG_ERSREQ_MASK                    (0x100U)
24931 #define FMU_FCNFG_ERSREQ_SHIFT                   (8U)
24932 /*! ERSREQ - Mass Erase Request
24933  *  0b0..No request or request complete
24934  *  0b1..Request to run the Mass Erase operation
24935  */
24936 #define FMU_FCNFG_ERSREQ(x)                      (((uint32_t)(((uint32_t)(x)) << FMU_FCNFG_ERSREQ_SHIFT)) & FMU_FCNFG_ERSREQ_MASK)
24937 
24938 #define FMU_FCNFG_DFDIE_MASK                     (0x10000U)
24939 #define FMU_FCNFG_DFDIE_SHIFT                    (16U)
24940 /*! DFDIE - Double Bit Fault Detect Interrupt Enable
24941  *  0b0..Double bit fault detect interrupt disabled
24942  *  0b1..Double bit fault detect interrupt enabled
24943  */
24944 #define FMU_FCNFG_DFDIE(x)                       (((uint32_t)(((uint32_t)(x)) << FMU_FCNFG_DFDIE_SHIFT)) & FMU_FCNFG_DFDIE_MASK)
24945 
24946 #define FMU_FCNFG_ERSIEN0_MASK                   (0xF000000U)
24947 #define FMU_FCNFG_ERSIEN0_SHIFT                  (24U)
24948 /*! ERSIEN0 - Erase IFR Sector Enable - Block 0
24949  *  0b0000..Block 0 IFR Sector X is protected from erase by ERSSCR command
24950  *  0b0001..Block 0 IFR Sector X is not protected from erase by ERSSCR command
24951  */
24952 #define FMU_FCNFG_ERSIEN0(x)                     (((uint32_t)(((uint32_t)(x)) << FMU_FCNFG_ERSIEN0_SHIFT)) & FMU_FCNFG_ERSIEN0_MASK)
24953 
24954 #define FMU_FCNFG_ERSIEN1_MASK                   (0xF0000000U)
24955 #define FMU_FCNFG_ERSIEN1_SHIFT                  (28U)
24956 /*! ERSIEN1 - Erase IFR Sector Enable - Block 1 (for dual block configs)
24957  *  0b0000..Block 1 IFR Sector X is protected from erase by ERSSCR command
24958  *  0b0001..Block 1 IFR Sector X is not protected from erase by ERSSCR command
24959  */
24960 #define FMU_FCNFG_ERSIEN1(x)                     (((uint32_t)(((uint32_t)(x)) << FMU_FCNFG_ERSIEN1_SHIFT)) & FMU_FCNFG_ERSIEN1_MASK)
24961 /*! @} */
24962 
24963 /*! @name FCTRL - Flash Control Register */
24964 /*! @{ */
24965 
24966 #define FMU_FCTRL_RWSC_MASK                      (0xFU)
24967 #define FMU_FCTRL_RWSC_SHIFT                     (0U)
24968 /*! RWSC - Read Wait-State Control */
24969 #define FMU_FCTRL_RWSC(x)                        (((uint32_t)(((uint32_t)(x)) << FMU_FCTRL_RWSC_SHIFT)) & FMU_FCTRL_RWSC_MASK)
24970 
24971 #define FMU_FCTRL_FDFD_MASK                      (0x10000U)
24972 #define FMU_FCTRL_FDFD_SHIFT                     (16U)
24973 /*! FDFD - Force Double Bit Fault Detect
24974  *  0b0..FSTAT[DFDIF] sets only if a double bit fault is detected during a valid flash read access from the platform flash controller
24975  *  0b1..FSTAT[DFDIF] sets during any valid flash read access from the platform flash controller. An interrupt
24976  *       request is generated if the DFDIE bit is set.
24977  */
24978 #define FMU_FCTRL_FDFD(x)                        (((uint32_t)(((uint32_t)(x)) << FMU_FCTRL_FDFD_SHIFT)) & FMU_FCTRL_FDFD_MASK)
24979 
24980 #define FMU_FCTRL_ABTREQ_MASK                    (0x1000000U)
24981 #define FMU_FCTRL_ABTREQ_SHIFT                   (24U)
24982 /*! ABTREQ - Abort Request
24983  *  0b0..No request to abort a command write sequence
24984  *  0b1..Request to abort a command write sequence
24985  */
24986 #define FMU_FCTRL_ABTREQ(x)                      (((uint32_t)(((uint32_t)(x)) << FMU_FCTRL_ABTREQ_SHIFT)) & FMU_FCTRL_ABTREQ_MASK)
24987 /*! @} */
24988 
24989 /*! @name FCCOB - Flash Common Command Object Registers */
24990 /*! @{ */
24991 
24992 #define FMU_FCCOB_CCOBn_MASK                     (0xFFFFFFFFU)
24993 #define FMU_FCCOB_CCOBn_SHIFT                    (0U)
24994 /*! CCOBn - CCOBn */
24995 #define FMU_FCCOB_CCOBn(x)                       (((uint32_t)(((uint32_t)(x)) << FMU_FCCOB_CCOBn_SHIFT)) & FMU_FCCOB_CCOBn_MASK)
24996 /*! @} */
24997 
24998 /* The count of FMU_FCCOB */
24999 #define FMU_FCCOB_COUNT                          (8U)
25000 
25001 
25002 /*!
25003  * @}
25004  */ /* end of group FMU_Register_Masks */
25005 
25006 
25007 /* FMU - Peripheral instance base addresses */
25008 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
25009   /** Peripheral FMU0 base address */
25010   #define FMU0_BASE                                (0x50043000u)
25011   /** Peripheral FMU0 base address */
25012   #define FMU0_BASE_NS                             (0x40043000u)
25013   /** Peripheral FMU0 base pointer */
25014   #define FMU0                                     ((FMU_Type *)FMU0_BASE)
25015   /** Peripheral FMU0 base pointer */
25016   #define FMU0_NS                                  ((FMU_Type *)FMU0_BASE_NS)
25017   /** Array initializer of FMU peripheral base addresses */
25018   #define FMU_BASE_ADDRS                           { FMU0_BASE }
25019   /** Array initializer of FMU peripheral base pointers */
25020   #define FMU_BASE_PTRS                            { FMU0 }
25021   /** Array initializer of FMU peripheral base addresses */
25022   #define FMU_BASE_ADDRS_NS                        { FMU0_BASE_NS }
25023   /** Array initializer of FMU peripheral base pointers */
25024   #define FMU_BASE_PTRS_NS                         { FMU0_NS }
25025 #else
25026   /** Peripheral FMU0 base address */
25027   #define FMU0_BASE                                (0x40043000u)
25028   /** Peripheral FMU0 base pointer */
25029   #define FMU0                                     ((FMU_Type *)FMU0_BASE)
25030   /** Array initializer of FMU peripheral base addresses */
25031   #define FMU_BASE_ADDRS                           { FMU0_BASE }
25032   /** Array initializer of FMU peripheral base pointers */
25033   #define FMU_BASE_PTRS                            { FMU0 }
25034 #endif
25035 
25036 /*!
25037  * @}
25038  */ /* end of group FMU_Peripheral_Access_Layer */
25039 
25040 
25041 /* ----------------------------------------------------------------------------
25042    -- FMUTEST Peripheral Access Layer
25043    ---------------------------------------------------------------------------- */
25044 
25045 /*!
25046  * @addtogroup FMUTEST_Peripheral_Access_Layer FMUTEST Peripheral Access Layer
25047  * @{
25048  */
25049 
25050 /** FMUTEST - Register Layout Typedef */
25051 typedef struct {
25052   __IO uint32_t FSTAT;                             /**< Flash Status Register, offset: 0x0 */
25053   __IO uint32_t FCNFG;                             /**< Flash Configuration Register, offset: 0x4 */
25054   __IO uint32_t FCTRL;                             /**< Flash Control Register, offset: 0x8 */
25055   __I  uint32_t FTEST;                             /**< Flash Test Register, offset: 0xC */
25056   __IO uint32_t FCCOB0;                            /**< Flash Command Control 0 Register, offset: 0x10 */
25057   __IO uint32_t FCCOB1;                            /**< Flash Command Control 1 Register, offset: 0x14 */
25058   __IO uint32_t FCCOB2;                            /**< Flash Command Control 2 Register, offset: 0x18 */
25059   __IO uint32_t FCCOB3;                            /**< Flash Command Control 3 Register, offset: 0x1C */
25060   __IO uint32_t FCCOB4;                            /**< Flash Command Control 4 Register, offset: 0x20 */
25061   __IO uint32_t FCCOB5;                            /**< Flash Command Control 5 Register, offset: 0x24 */
25062   __IO uint32_t FCCOB6;                            /**< Flash Command Control 6 Register, offset: 0x28 */
25063   __IO uint32_t FCCOB7;                            /**< Flash Command Control 7 Register, offset: 0x2C */
25064        uint8_t RESERVED_0[208];
25065   __IO uint32_t RESET_STATUS;                      /**< FMU Initialization Tracking Register, offset: 0x100 */
25066   __IO uint32_t MCTL;                              /**< FMU Control Register, offset: 0x104 */
25067   __I  uint32_t BSEL_GEN;                          /**< FMU Block Select Generation Register, offset: 0x108 */
25068   __IO uint32_t PWR_OPT;                           /**< Power Mode Options Register, offset: 0x10C */
25069   __I  uint32_t CMD_CHECK;                         /**< FMU Command Check Register, offset: 0x110 */
25070        uint8_t RESERVED_1[12];
25071   __IO uint32_t BSEL;                              /**< FMU Block Select Register, offset: 0x120 */
25072   __IO uint32_t MSIZE;                             /**< FMU Memory Size Register, offset: 0x124 */
25073   __IO uint32_t FLASH_RD_ADD;                      /**< Flash Read Address Register, offset: 0x128 */
25074        uint8_t RESERVED_2[4];
25075   __IO uint32_t FLASH_STOP_ADD;                    /**< Flash Stop Address Register, offset: 0x130 */
25076   __IO uint32_t FLASH_RD_CTRL;                     /**< Flash Read Control Register, offset: 0x134 */
25077   __IO uint32_t MM_ADDR;                           /**< Memory Map Address Register, offset: 0x138 */
25078        uint8_t RESERVED_3[4];
25079   __IO uint32_t MM_WDATA;                          /**< Memory Map Write Data Register, offset: 0x140 */
25080   __IO uint32_t MM_CTL;                            /**< Memory Map Control Register, offset: 0x144 */
25081   __IO uint32_t UINT_CTL;                          /**< User Interface Control Register, offset: 0x148 */
25082   __IO uint32_t RD_DATA0;                          /**< Read Data 0 Register, offset: 0x14C */
25083   __IO uint32_t RD_DATA1;                          /**< Read Data 1 Register, offset: 0x150 */
25084   __IO uint32_t RD_DATA2;                          /**< Read Data 2 Register, offset: 0x154 */
25085   __IO uint32_t RD_DATA3;                          /**< Read Data 3 Register, offset: 0x158 */
25086   __IO uint32_t PARITY;                            /**< Parity Register, offset: 0x15C */
25087   __IO uint32_t RD_PATH_CTRL_STATUS;               /**< Read Path Control and Status Register, offset: 0x160 */
25088   __IO uint32_t SMW_DIN0;                          /**< SMW DIN 0 Register, offset: 0x164 */
25089   __IO uint32_t SMW_DIN1;                          /**< SMW DIN 1 Register, offset: 0x168 */
25090   __IO uint32_t SMW_DIN2;                          /**< SMW DIN 2 Register, offset: 0x16C */
25091   __IO uint32_t SMW_DIN3;                          /**< SMW DIN 3 Register, offset: 0x170 */
25092   __IO uint32_t SMW_ADDR;                          /**< SMW Address Register, offset: 0x174 */
25093   __IO uint32_t SMW_CMD_WAIT;                      /**< SMW Command and Wait Register, offset: 0x178 */
25094   __I  uint32_t SMW_STATUS;                        /**< SMW Status Register, offset: 0x17C */
25095   __IO uint32_t SOCTRIM0_0;                        /**< SoC Trim Phrase 0 Word 0 Register, offset: 0x180 */
25096   __IO uint32_t SOCTRIM0_1;                        /**< SoC Trim Phrase 0 Word 1 Register, offset: 0x184 */
25097   __IO uint32_t SOCTRIM0_2;                        /**< SoC Trim Phrase 0 Word 2 Register, offset: 0x188 */
25098   __IO uint32_t SOCTRIM0_3;                        /**< SoC Trim Phrase 0 Word 3 Register, offset: 0x18C */
25099   __IO uint32_t SOCTRIM1_0;                        /**< SoC Trim Phrase 1 Word 0 Register, offset: 0x190 */
25100   __IO uint32_t SOCTRIM1_1;                        /**< SoC Trim Phrase 1 Word 1 Register, offset: 0x194 */
25101   __IO uint32_t SOCTRIM1_2;                        /**< SoC Trim Phrase 1 Word 2 Register, offset: 0x198 */
25102   __IO uint32_t SOCTRIM1_3;                        /**< SoC Trim Phrase 1 Word 3 Register, offset: 0x19C */
25103   __IO uint32_t SOCTRIM2_0;                        /**< SoC Trim Phrase 2 Word 0 Register, offset: 0x1A0 */
25104   __IO uint32_t SOCTRIM2_1;                        /**< SoC Trim Phrase 2 Word 1 Register, offset: 0x1A4 */
25105   __IO uint32_t SOCTRIM2_2;                        /**< SoC Trim Phrase 2 Word 2 Register, offset: 0x1A8 */
25106   __IO uint32_t SOCTRIM2_3;                        /**< SoC Trim Phrase 2 Word 3 Register, offset: 0x1AC */
25107   __IO uint32_t SOCTRIM3_0;                        /**< SoC Trim Phrase 3 Word 0 Register, offset: 0x1B0 */
25108   __IO uint32_t SOCTRIM3_1;                        /**< SoC Trim Phrase 3 Word 1 Register, offset: 0x1B4 */
25109   __IO uint32_t SOCTRIM3_2;                        /**< SoC Trim Phrase 3 Word 2 Register, offset: 0x1B8 */
25110   __IO uint32_t SOCTRIM3_3;                        /**< SoC Trim Phrase 3 Word 3 Register, offset: 0x1BC */
25111   __IO uint32_t SOCTRIM4_0;                        /**< SoC Trim Phrase 4 Word 0 Register, offset: 0x1C0 */
25112   __IO uint32_t SOCTRIM4_1;                        /**< SoC Trim Phrase 4 Word 1 Register, offset: 0x1C4 */
25113   __IO uint32_t SOCTRIM4_2;                        /**< SoC Trim Phrase 4 Word 2 Register, offset: 0x1C8 */
25114   __IO uint32_t SOCTRIM4_3;                        /**< SoC Trim Phrase 4 Word 3 Register, offset: 0x1CC */
25115   __IO uint32_t SOCTRIM5_0;                        /**< SoC Trim Phrase 5 Word 0 Register, offset: 0x1D0 */
25116   __IO uint32_t SOCTRIM5_1;                        /**< SoC Trim Phrase 5 Word 1 Register, offset: 0x1D4 */
25117   __IO uint32_t SOCTRIM5_2;                        /**< SoC Trim Phrase 5 Word 2 Register, offset: 0x1D8 */
25118   __IO uint32_t SOCTRIM5_3;                        /**< SoC Trim Phrase 5 Word 3 Register, offset: 0x1DC */
25119   __IO uint32_t SOCTRIM6_0;                        /**< SoC Trim Phrase 6 Word 0 Register, offset: 0x1E0 */
25120   __IO uint32_t SOCTRIM6_1;                        /**< SoC Trim Phrase 6 Word 1 Register, offset: 0x1E4 */
25121   __IO uint32_t SOCTRIM6_2;                        /**< SoC Trim Phrase 6 Word 2 Register, offset: 0x1E8 */
25122   __IO uint32_t SOCTRIM6_3;                        /**< SoC Trim Phrase 6 Word 3 Register, offset: 0x1EC */
25123   __IO uint32_t SOCTRIM7_0;                        /**< SoC Trim Phrase 7 Word 0 Register, offset: 0x1F0 */
25124   __IO uint32_t SOCTRIM7_1;                        /**< SoC Trim Phrase 7 Word 1 Register, offset: 0x1F4 */
25125   __IO uint32_t SOCTRIM7_2;                        /**< SoC Trim Phrase 7 Word 2 Register, offset: 0x1F8 */
25126   __IO uint32_t SOCTRIM7_3;                        /**< SoC Trim Phrase 7 Word 3 Register, offset: 0x1FC */
25127        uint8_t RESERVED_4[4];
25128   __IO uint32_t R_IP_CONFIG;                       /**< BIST Configuration Register, offset: 0x204 */
25129   __IO uint32_t R_TESTCODE;                        /**< BIST Test Code Register, offset: 0x208 */
25130   __IO uint32_t R_DFT_CTRL;                        /**< BIST DFT Control Register, offset: 0x20C */
25131   __IO uint32_t R_ADR_CTRL;                        /**< BIST Address Control Register, offset: 0x210 */
25132   __IO uint32_t R_DATA_CTRL0;                      /**< BIST Data Control 0 Register, offset: 0x214 */
25133   __IO uint32_t R_PIN_CTRL;                        /**< BIST Pin Control Register, offset: 0x218 */
25134   __IO uint32_t R_CNT_LOOP_CTRL;                   /**< BIST Loop Count Control Register, offset: 0x21C */
25135   __IO uint32_t R_TIMER_CTRL;                      /**< BIST Timer Control Register, offset: 0x220 */
25136   __IO uint32_t R_TEST_CTRL;                       /**< BIST Test Control Register, offset: 0x224 */
25137   __O  uint32_t R_ABORT_LOOP;                      /**< BIST Abort Loop Register, offset: 0x228 */
25138   __I  uint32_t R_ADR_QUERY;                       /**< BIST Address Query Register, offset: 0x22C */
25139   __I  uint32_t R_DOUT_QUERY0;                     /**< BIST DOUT Query 0 Register, offset: 0x230 */
25140        uint8_t RESERVED_5[8];
25141   __I  uint32_t R_SMW_QUERY;                       /**< BIST SMW Query Register, offset: 0x23C */
25142   __IO uint32_t R_SMW_SETTING0;                    /**< BIST SMW Setting 0 Register, offset: 0x240 */
25143   __IO uint32_t R_SMW_SETTING1;                    /**< BIST SMW Setting 1 Register, offset: 0x244 */
25144   __IO uint32_t R_SMP_WHV0;                        /**< BIST SMP WHV Setting 0 Register, offset: 0x248 */
25145   __IO uint32_t R_SMP_WHV1;                        /**< BIST SMP WHV Setting 1 Register, offset: 0x24C */
25146   __IO uint32_t R_SME_WHV0;                        /**< BIST SME WHV Setting 0 Register, offset: 0x250 */
25147   __IO uint32_t R_SME_WHV1;                        /**< BIST SME WHV Setting 1 Register, offset: 0x254 */
25148   __IO uint32_t R_SMW_SETTING2;                    /**< BIST SMW Setting 2 Register, offset: 0x258 */
25149   __I  uint32_t R_D_MISR0;                         /**< BIST DIN MISR 0 Register, offset: 0x25C */
25150   __I  uint32_t R_A_MISR0;                         /**< BIST Address MISR 0 Register, offset: 0x260 */
25151   __I  uint32_t R_C_MISR0;                         /**< BIST Control MISR 0 Register, offset: 0x264 */
25152   __IO uint32_t R_SMW_SETTING3;                    /**< BIST SMW Setting 3 Register, offset: 0x268 */
25153   __IO uint32_t R_DATA_CTRL1;                      /**< BIST Data Control 1 Register, offset: 0x26C */
25154   __IO uint32_t R_DATA_CTRL2;                      /**< BIST Data Control 2 Register, offset: 0x270 */
25155   __IO uint32_t R_DATA_CTRL3;                      /**< BIST Data Control 3 Register, offset: 0x274 */
25156        uint8_t RESERVED_6[8];
25157   __I  uint32_t R_REPAIR0_0;                       /**< BIST Repair 0 for Block 0 Register, offset: 0x280 */
25158   __I  uint32_t R_REPAIR0_1;                       /**< BIST Repair 1 Block 0 Register, offset: 0x284 */
25159   __I  uint32_t R_REPAIR1_0;                       /**< BIST Repair 0 Block 1 Register, offset: 0x288 */
25160   __I  uint32_t R_REPAIR1_1;                       /**< BIST Repair 1 Block 1 Register, offset: 0x28C */
25161        uint8_t RESERVED_7[132];
25162   __IO uint32_t R_DATA_CTRL0_EX;                   /**< BIST Data Control 0 Extension Register, offset: 0x314 */
25163        uint8_t RESERVED_8[8];
25164   __IO uint32_t R_TIMER_CTRL_EX;                   /**< BIST Timer Control Extension Register, offset: 0x320 */
25165        uint8_t RESERVED_9[12];
25166   __I  uint32_t R_DOUT_QUERY1;                     /**< BIST DOUT Query 1 Register, offset: 0x330 */
25167        uint8_t RESERVED_10[40];
25168   __I  uint32_t R_D_MISR1;                         /**< BIST DIN MISR 1 Register, offset: 0x35C */
25169   __I  uint32_t R_A_MISR1;                         /**< BIST Address MISR 1 Register, offset: 0x360 */
25170   __I  uint32_t R_C_MISR1;                         /**< BIST Control MISR 1 Register, offset: 0x364 */
25171        uint8_t RESERVED_11[4];
25172   __IO uint32_t R_DATA_CTRL1_EX;                   /**< BIST Data Control 1 Extension Register, offset: 0x36C */
25173   __IO uint32_t R_DATA_CTRL2_EX;                   /**< BIST Data Control 2 Extension Register, offset: 0x370 */
25174   __IO uint32_t R_DATA_CTRL3_EX;                   /**< BIST Data Control 3 Extension Register, offset: 0x374 */
25175        uint8_t RESERVED_12[136];
25176   __IO uint32_t SMW_TIMER_OPTION;                  /**< SMW Timer Option Register, offset: 0x400 */
25177   __IO uint32_t SMW_SETTING_OPTION0;               /**< SMW Setting Option 0 Register, offset: 0x404 */
25178   __IO uint32_t SMW_SETTING_OPTION2;               /**< SMW Setting Option 2 Register, offset: 0x408 */
25179   __IO uint32_t SMW_SETTING_OPTION3;               /**< SMW Setting Option 3 Register, offset: 0x40C */
25180   __IO uint32_t SMW_SMP_WHV_OPTION0;               /**< SMW SMP WHV Option 0 Register, offset: 0x410 */
25181   __IO uint32_t SMW_SME_WHV_OPTION0;               /**< SMW SME WHV Option 0 Register, offset: 0x414 */
25182   __IO uint32_t SMW_SETTING_OPTION1;               /**< SMW Setting Option 1 Register, offset: 0x418 */
25183   __IO uint32_t SMW_SMP_WHV_OPTION1;               /**< SMW SMP WHV Option 1 Register, offset: 0x41C */
25184   __IO uint32_t SMW_SME_WHV_OPTION1;               /**< SMW SME WHV Option 1 Register, offset: 0x420 */
25185        uint8_t RESERVED_13[220];
25186   __IO uint32_t REPAIR0_0;                         /**< FMU Repair 0 Block 0 Register, offset: 0x500 */
25187   __IO uint32_t REPAIR0_1;                         /**< FMU Repair 1 Block 0 Register, offset: 0x504 */
25188   __IO uint32_t REPAIR1_0;                         /**< FMU Repair 0 Block 1 Register, offset: 0x508 */
25189   __IO uint32_t REPAIR1_1;                         /**< FMU Repair 1 Block 1 Register, offset: 0x50C */
25190        uint8_t RESERVED_14[240];
25191   __IO uint32_t SMW_HB_SIGNALS;                    /**< SMW HB Signals Register, offset: 0x600 */
25192   __IO uint32_t BIST_DUMP_CTRL;                    /**< BIST Datadump Control Register, offset: 0x604 */
25193        uint8_t RESERVED_15[4];
25194   __IO uint32_t ATX_PIN_CTRL;                      /**< ATX Pin Control Register, offset: 0x60C */
25195   __IO uint32_t FAILCNT;                           /**< Fail Count Register, offset: 0x610 */
25196   __IO uint32_t PGM_PULSE_CNT0;                    /**< Block 0 Program Pulse Count Register, offset: 0x614 */
25197   __IO uint32_t PGM_PULSE_CNT1;                    /**< Block 1 Program Pulse Count Register, offset: 0x618 */
25198   __IO uint32_t ERS_PULSE_CNT;                     /**< Erase Pulse Count Register, offset: 0x61C */
25199   __IO uint32_t MAX_PULSE_CNT;                     /**< Maximum Pulse Count Register, offset: 0x620 */
25200   __IO uint32_t PORT_CTRL;                         /**< Port Control Register, offset: 0x624 */
25201 } FMUTEST_Type;
25202 
25203 /* ----------------------------------------------------------------------------
25204    -- FMUTEST Register Masks
25205    ---------------------------------------------------------------------------- */
25206 
25207 /*!
25208  * @addtogroup FMUTEST_Register_Masks FMUTEST Register Masks
25209  * @{
25210  */
25211 
25212 /*! @name FSTAT - Flash Status Register */
25213 /*! @{ */
25214 
25215 #define FMUTEST_FSTAT_FAIL_MASK                  (0x1U)
25216 #define FMUTEST_FSTAT_FAIL_SHIFT                 (0U)
25217 /*! FAIL - Command Fail Flag
25218  *  0b0..Error not detected
25219  *  0b1..Error detected
25220  */
25221 #define FMUTEST_FSTAT_FAIL(x)                    (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_FAIL_SHIFT)) & FMUTEST_FSTAT_FAIL_MASK)
25222 
25223 #define FMUTEST_FSTAT_CMDABT_MASK                (0x4U)
25224 #define FMUTEST_FSTAT_CMDABT_SHIFT               (2U)
25225 /*! CMDABT - Command Abort Flag
25226  *  0b0..No command abort detected
25227  *  0b1..Command abort detected
25228  */
25229 #define FMUTEST_FSTAT_CMDABT(x)                  (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_CMDABT_SHIFT)) & FMUTEST_FSTAT_CMDABT_MASK)
25230 
25231 #define FMUTEST_FSTAT_PVIOL_MASK                 (0x10U)
25232 #define FMUTEST_FSTAT_PVIOL_SHIFT                (4U)
25233 /*! PVIOL - Command Protection Violation Flag
25234  *  0b0..No protection violation detected
25235  *  0b1..Protection violation detected
25236  */
25237 #define FMUTEST_FSTAT_PVIOL(x)                   (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_PVIOL_SHIFT)) & FMUTEST_FSTAT_PVIOL_MASK)
25238 
25239 #define FMUTEST_FSTAT_ACCERR_MASK                (0x20U)
25240 #define FMUTEST_FSTAT_ACCERR_SHIFT               (5U)
25241 /*! ACCERR - Command Access Error Flag
25242  *  0b0..No access error detected
25243  *  0b1..Access error detected
25244  */
25245 #define FMUTEST_FSTAT_ACCERR(x)                  (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_ACCERR_SHIFT)) & FMUTEST_FSTAT_ACCERR_MASK)
25246 
25247 #define FMUTEST_FSTAT_CWSABT_MASK                (0x40U)
25248 #define FMUTEST_FSTAT_CWSABT_SHIFT               (6U)
25249 /*! CWSABT - Command Write Sequence Abort Flag
25250  *  0b0..Command write sequence not aborted
25251  *  0b1..Command write sequence aborted
25252  */
25253 #define FMUTEST_FSTAT_CWSABT(x)                  (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_CWSABT_SHIFT)) & FMUTEST_FSTAT_CWSABT_MASK)
25254 
25255 #define FMUTEST_FSTAT_CCIF_MASK                  (0x80U)
25256 #define FMUTEST_FSTAT_CCIF_SHIFT                 (7U)
25257 /*! CCIF - Command Complete Interrupt Flag
25258  *  0b0..Flash command or initialization in progress
25259  *  0b1..Flash command or initialization has completed
25260  */
25261 #define FMUTEST_FSTAT_CCIF(x)                    (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_CCIF_SHIFT)) & FMUTEST_FSTAT_CCIF_MASK)
25262 
25263 #define FMUTEST_FSTAT_CMDPRT_MASK                (0x300U)
25264 #define FMUTEST_FSTAT_CMDPRT_SHIFT               (8U)
25265 /*! CMDPRT - Command Protection Level
25266  *  0b00..Secure, normal access
25267  *  0b01..Secure, privileged access
25268  *  0b10..Nonsecure, normal access
25269  *  0b11..Nonsecure, privileged access
25270  */
25271 #define FMUTEST_FSTAT_CMDPRT(x)                  (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_CMDPRT_SHIFT)) & FMUTEST_FSTAT_CMDPRT_MASK)
25272 
25273 #define FMUTEST_FSTAT_CMDP_MASK                  (0x800U)
25274 #define FMUTEST_FSTAT_CMDP_SHIFT                 (11U)
25275 /*! CMDP - Command Protection Status Flag
25276  *  0b0..Command protection level and domain ID are stale
25277  *  0b1..Command protection level (CMDPRT) and domain ID (CMDDID) are set
25278  */
25279 #define FMUTEST_FSTAT_CMDP(x)                    (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_CMDP_SHIFT)) & FMUTEST_FSTAT_CMDP_MASK)
25280 
25281 #define FMUTEST_FSTAT_CMDDID_MASK                (0xF000U)
25282 #define FMUTEST_FSTAT_CMDDID_SHIFT               (12U)
25283 /*! CMDDID - Command Domain ID */
25284 #define FMUTEST_FSTAT_CMDDID(x)                  (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_CMDDID_SHIFT)) & FMUTEST_FSTAT_CMDDID_MASK)
25285 
25286 #define FMUTEST_FSTAT_DFDIF_MASK                 (0x10000U)
25287 #define FMUTEST_FSTAT_DFDIF_SHIFT                (16U)
25288 /*! DFDIF - Double Bit Fault Detect Interrupt Flag
25289  *  0b0..Double bit fault not detected during a valid flash read access from the FMC
25290  *  0b1..Double bit fault detected (or FCTRL[FDFD] is set) during a valid flash read access from the FMC
25291  */
25292 #define FMUTEST_FSTAT_DFDIF(x)                   (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_DFDIF_SHIFT)) & FMUTEST_FSTAT_DFDIF_MASK)
25293 
25294 #define FMUTEST_FSTAT_SALV_USED_MASK             (0x20000U)
25295 #define FMUTEST_FSTAT_SALV_USED_SHIFT            (17U)
25296 /*! SALV_USED - Salvage Used for Erase operation
25297  *  0b0..Salvage not used during the last operation
25298  *  0b1..Salvage used during the last erase operation
25299  */
25300 #define FMUTEST_FSTAT_SALV_USED(x)               (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_SALV_USED_SHIFT)) & FMUTEST_FSTAT_SALV_USED_MASK)
25301 
25302 #define FMUTEST_FSTAT_PEWEN_MASK                 (0x3000000U)
25303 #define FMUTEST_FSTAT_PEWEN_SHIFT                (24U)
25304 /*! PEWEN - Program-Erase Write Enable Control
25305  *  0b00..Writes are not enabled
25306  *  0b01..Writes are enabled for one flash or IFR phrase (phrase programming, sector erase)
25307  *  0b10..Writes are enabled for one flash or IFR page (page programming)
25308  *  0b11..Reserved
25309  */
25310 #define FMUTEST_FSTAT_PEWEN(x)                   (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_PEWEN_SHIFT)) & FMUTEST_FSTAT_PEWEN_MASK)
25311 
25312 #define FMUTEST_FSTAT_PERDY_MASK                 (0x80000000U)
25313 #define FMUTEST_FSTAT_PERDY_SHIFT                (31U)
25314 /*! PERDY - Program/Erase Ready Control/Status Flag
25315  *  0b0..Program or sector erase command operation is not stalled
25316  *  0b1..Program or sector erase command operation is stalled
25317  */
25318 #define FMUTEST_FSTAT_PERDY(x)                   (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_PERDY_SHIFT)) & FMUTEST_FSTAT_PERDY_MASK)
25319 /*! @} */
25320 
25321 /*! @name FCNFG - Flash Configuration Register */
25322 /*! @{ */
25323 
25324 #define FMUTEST_FCNFG_CCIE_MASK                  (0x80U)
25325 #define FMUTEST_FCNFG_CCIE_SHIFT                 (7U)
25326 /*! CCIE - Command Complete Interrupt Enable
25327  *  0b0..Command complete interrupt disabled
25328  *  0b1..Command complete interrupt enabled. An interrupt request is generated whenever the FSTAT[CCIF] flag is set.
25329  */
25330 #define FMUTEST_FCNFG_CCIE(x)                    (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCNFG_CCIE_SHIFT)) & FMUTEST_FCNFG_CCIE_MASK)
25331 
25332 #define FMUTEST_FCNFG_ERSREQ_MASK                (0x100U)
25333 #define FMUTEST_FCNFG_ERSREQ_SHIFT               (8U)
25334 /*! ERSREQ - Mass Erase (Erase All) Request
25335  *  0b0..No request or request complete
25336  *  0b1..Request to run the Mass Erase operation
25337  */
25338 #define FMUTEST_FCNFG_ERSREQ(x)                  (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCNFG_ERSREQ_SHIFT)) & FMUTEST_FCNFG_ERSREQ_MASK)
25339 
25340 #define FMUTEST_FCNFG_DFDIE_MASK                 (0x10000U)
25341 #define FMUTEST_FCNFG_DFDIE_SHIFT                (16U)
25342 /*! DFDIE - Double Bit Fault Detect Interrupt Enable
25343  *  0b0..Double bit fault detect interrupt disabled
25344  *  0b1..Double bit fault detect interrupt enabled; an interrupt request is generated whenever the FSTAT[DFDIF] flag is set
25345  */
25346 #define FMUTEST_FCNFG_DFDIE(x)                   (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCNFG_DFDIE_SHIFT)) & FMUTEST_FCNFG_DFDIE_MASK)
25347 
25348 #define FMUTEST_FCNFG_ERSIEN0_MASK               (0xF000000U)
25349 #define FMUTEST_FCNFG_ERSIEN0_SHIFT              (24U)
25350 /*! ERSIEN0 - Erase IFR Sector Enable - Block 0
25351  *  0b0000..Block 0 IFR Sector X is protected from erase by ERSSCR command
25352  *  0b0001..Block 0 IFR Sector X is not protected from erase by ERSSCR command
25353  */
25354 #define FMUTEST_FCNFG_ERSIEN0(x)                 (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCNFG_ERSIEN0_SHIFT)) & FMUTEST_FCNFG_ERSIEN0_MASK)
25355 
25356 #define FMUTEST_FCNFG_ERSIEN1_MASK               (0xF0000000U)
25357 #define FMUTEST_FCNFG_ERSIEN1_SHIFT              (28U)
25358 /*! ERSIEN1 - Erase IFR Sector Enable - Block 1 (for dual block configs)
25359  *  0b0000..Block 1 IFR Sector X is protected from erase by ERSSCR command
25360  *  0b0001..Block 1 IFR Sector X is not protected from erase by ERSSCR command
25361  */
25362 #define FMUTEST_FCNFG_ERSIEN1(x)                 (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCNFG_ERSIEN1_SHIFT)) & FMUTEST_FCNFG_ERSIEN1_MASK)
25363 /*! @} */
25364 
25365 /*! @name FCTRL - Flash Control Register */
25366 /*! @{ */
25367 
25368 #define FMUTEST_FCTRL_RWSC_MASK                  (0xFU)
25369 #define FMUTEST_FCTRL_RWSC_SHIFT                 (0U)
25370 /*! RWSC - Read Wait-State Control
25371  *  0b0000..no additional wait-states are added (single cycle access)
25372  *  0b0001..1 additional wait-state is added
25373  *  0b0010..2 additional wait-states are added
25374  *  0b0011..3 additional wait-states are added
25375  *  0b0100..4 additional wait-states are added
25376  *  0b0101..5 additional wait-states are added
25377  *  0b0110..6 additional wait-states are added
25378  *  0b0111..7 additional wait-states are added
25379  *  0b1000..8 additional wait-states are added
25380  *  0b1001..9 additional wait-states are added
25381  *  0b1010..10 additional wait-states are added
25382  *  0b1011..11 additional wait-states are added
25383  *  0b1100..12 additional wait-states are added
25384  *  0b1101..13 additional wait-states are added
25385  *  0b1110..14 additional wait-states are added
25386  *  0b1111..15 additional wait-states are added
25387  */
25388 #define FMUTEST_FCTRL_RWSC(x)                    (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCTRL_RWSC_SHIFT)) & FMUTEST_FCTRL_RWSC_MASK)
25389 
25390 #define FMUTEST_FCTRL_LSACTIVE_MASK              (0x100U)
25391 #define FMUTEST_FCTRL_LSACTIVE_SHIFT             (8U)
25392 /*! LSACTIVE - Low Speed Active Mode
25393  *  0b0..Full speed active mode requested
25394  *  0b1..Low speed active mode requested
25395  */
25396 #define FMUTEST_FCTRL_LSACTIVE(x)                (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCTRL_LSACTIVE_SHIFT)) & FMUTEST_FCTRL_LSACTIVE_MASK)
25397 
25398 #define FMUTEST_FCTRL_FDFD_MASK                  (0x10000U)
25399 #define FMUTEST_FCTRL_FDFD_SHIFT                 (16U)
25400 /*! FDFD - Force Double Bit Fault Detect
25401  *  0b0..FSTAT[DFDIF] sets only if a double bit fault is detected during a valid flash read access from the FMC
25402  *  0b1..FSTAT[DFDIF] sets during any valid flash read access from the FMC; an interrupt request is generated if the DFDIE bit is set
25403  */
25404 #define FMUTEST_FCTRL_FDFD(x)                    (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCTRL_FDFD_SHIFT)) & FMUTEST_FCTRL_FDFD_MASK)
25405 
25406 #define FMUTEST_FCTRL_ABTREQ_MASK                (0x1000000U)
25407 #define FMUTEST_FCTRL_ABTREQ_SHIFT               (24U)
25408 /*! ABTREQ - Abort Request
25409  *  0b0..No request to abort a command write sequence
25410  *  0b1..Request to abort a command write sequence
25411  */
25412 #define FMUTEST_FCTRL_ABTREQ(x)                  (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCTRL_ABTREQ_SHIFT)) & FMUTEST_FCTRL_ABTREQ_MASK)
25413 /*! @} */
25414 
25415 /*! @name FTEST - Flash Test Register */
25416 /*! @{ */
25417 
25418 #define FMUTEST_FTEST_TMECTL_MASK                (0x1U)
25419 #define FMUTEST_FTEST_TMECTL_SHIFT               (0U)
25420 /*! TMECTL - Test Mode Entry Control
25421  *  0b0..FTEST register always reads 0 and writes to FTEST are ignored
25422  *  0b1..FTEST register is readable and can be written to enable writability of TME
25423  */
25424 #define FMUTEST_FTEST_TMECTL(x)                  (((uint32_t)(((uint32_t)(x)) << FMUTEST_FTEST_TMECTL_SHIFT)) & FMUTEST_FTEST_TMECTL_MASK)
25425 
25426 #define FMUTEST_FTEST_TMEWR_MASK                 (0x2U)
25427 #define FMUTEST_FTEST_TMEWR_SHIFT                (1U)
25428 /*! TMEWR - Test Mode Entry Writable
25429  *  0b0..TME bit is not writable
25430  *  0b1..TME bit is writable
25431  */
25432 #define FMUTEST_FTEST_TMEWR(x)                   (((uint32_t)(((uint32_t)(x)) << FMUTEST_FTEST_TMEWR_SHIFT)) & FMUTEST_FTEST_TMEWR_MASK)
25433 
25434 #define FMUTEST_FTEST_TME_MASK                   (0x4U)
25435 #define FMUTEST_FTEST_TME_SHIFT                  (2U)
25436 /*! TME - Test Mode Entry
25437  *  0b0..Test mode entry not requested
25438  *  0b1..Test mode entry requested
25439  */
25440 #define FMUTEST_FTEST_TME(x)                     (((uint32_t)(((uint32_t)(x)) << FMUTEST_FTEST_TME_SHIFT)) & FMUTEST_FTEST_TME_MASK)
25441 
25442 #define FMUTEST_FTEST_TMODE_MASK                 (0x8U)
25443 #define FMUTEST_FTEST_TMODE_SHIFT                (3U)
25444 /*! TMODE - Test Mode Status
25445  *  0b0..Test mode not active
25446  *  0b1..Test mode active
25447  */
25448 #define FMUTEST_FTEST_TMODE(x)                   (((uint32_t)(((uint32_t)(x)) << FMUTEST_FTEST_TMODE_SHIFT)) & FMUTEST_FTEST_TMODE_MASK)
25449 
25450 #define FMUTEST_FTEST_TMELOCK_MASK               (0x10U)
25451 #define FMUTEST_FTEST_TMELOCK_SHIFT              (4U)
25452 /*! TMELOCK - Test Mode Entry Lock
25453  *  0b0..FTEST register not locked from accepting writes
25454  *  0b1..FTEST register locked from accepting writes
25455  */
25456 #define FMUTEST_FTEST_TMELOCK(x)                 (((uint32_t)(((uint32_t)(x)) << FMUTEST_FTEST_TMELOCK_SHIFT)) & FMUTEST_FTEST_TMELOCK_MASK)
25457 /*! @} */
25458 
25459 /*! @name FCCOB0 - Flash Command Control 0 Register */
25460 /*! @{ */
25461 
25462 #define FMUTEST_FCCOB0_CMDCODE_MASK              (0xFFU)
25463 #define FMUTEST_FCCOB0_CMDCODE_SHIFT             (0U)
25464 /*! CMDCODE - Command code */
25465 #define FMUTEST_FCCOB0_CMDCODE(x)                (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCCOB0_CMDCODE_SHIFT)) & FMUTEST_FCCOB0_CMDCODE_MASK)
25466 /*! @} */
25467 
25468 /*! @name FCCOB1 - Flash Command Control 1 Register */
25469 /*! @{ */
25470 
25471 #define FMUTEST_FCCOB1_CMDOPT_MASK               (0xFFU)
25472 #define FMUTEST_FCCOB1_CMDOPT_SHIFT              (0U)
25473 /*! CMDOPT - Command options */
25474 #define FMUTEST_FCCOB1_CMDOPT(x)                 (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCCOB1_CMDOPT_SHIFT)) & FMUTEST_FCCOB1_CMDOPT_MASK)
25475 /*! @} */
25476 
25477 /*! @name FCCOB2 - Flash Command Control 2 Register */
25478 /*! @{ */
25479 
25480 #define FMUTEST_FCCOB2_CMDADDR_MASK              (0xFFFFFFFFU)
25481 #define FMUTEST_FCCOB2_CMDADDR_SHIFT             (0U)
25482 /*! CMDADDR - Command starting address */
25483 #define FMUTEST_FCCOB2_CMDADDR(x)                (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCCOB2_CMDADDR_SHIFT)) & FMUTEST_FCCOB2_CMDADDR_MASK)
25484 /*! @} */
25485 
25486 /*! @name FCCOB3 - Flash Command Control 3 Register */
25487 /*! @{ */
25488 
25489 #define FMUTEST_FCCOB3_CMDADDRE_MASK             (0xFFFFFFFFU)
25490 #define FMUTEST_FCCOB3_CMDADDRE_SHIFT            (0U)
25491 /*! CMDADDRE - Command ending address */
25492 #define FMUTEST_FCCOB3_CMDADDRE(x)               (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCCOB3_CMDADDRE_SHIFT)) & FMUTEST_FCCOB3_CMDADDRE_MASK)
25493 /*! @} */
25494 
25495 /*! @name FCCOB4 - Flash Command Control 4 Register */
25496 /*! @{ */
25497 
25498 #define FMUTEST_FCCOB4_CMDDATA0_MASK             (0xFFFFFFFFU)
25499 #define FMUTEST_FCCOB4_CMDDATA0_SHIFT            (0U)
25500 /*! CMDDATA0 - Command data word 0 */
25501 #define FMUTEST_FCCOB4_CMDDATA0(x)               (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCCOB4_CMDDATA0_SHIFT)) & FMUTEST_FCCOB4_CMDDATA0_MASK)
25502 /*! @} */
25503 
25504 /*! @name FCCOB5 - Flash Command Control 5 Register */
25505 /*! @{ */
25506 
25507 #define FMUTEST_FCCOB5_CMDDATA1_MASK             (0xFFFFFFFFU)
25508 #define FMUTEST_FCCOB5_CMDDATA1_SHIFT            (0U)
25509 /*! CMDDATA1 - Command data word 1 */
25510 #define FMUTEST_FCCOB5_CMDDATA1(x)               (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCCOB5_CMDDATA1_SHIFT)) & FMUTEST_FCCOB5_CMDDATA1_MASK)
25511 /*! @} */
25512 
25513 /*! @name FCCOB6 - Flash Command Control 6 Register */
25514 /*! @{ */
25515 
25516 #define FMUTEST_FCCOB6_CMDDATA2_MASK             (0xFFFFFFFFU)
25517 #define FMUTEST_FCCOB6_CMDDATA2_SHIFT            (0U)
25518 /*! CMDDATA2 - Command data word 2 */
25519 #define FMUTEST_FCCOB6_CMDDATA2(x)               (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCCOB6_CMDDATA2_SHIFT)) & FMUTEST_FCCOB6_CMDDATA2_MASK)
25520 /*! @} */
25521 
25522 /*! @name FCCOB7 - Flash Command Control 7 Register */
25523 /*! @{ */
25524 
25525 #define FMUTEST_FCCOB7_CMDDATA3_MASK             (0xFFFFFFFFU)
25526 #define FMUTEST_FCCOB7_CMDDATA3_SHIFT            (0U)
25527 /*! CMDDATA3 - Command data word 3 */
25528 #define FMUTEST_FCCOB7_CMDDATA3(x)               (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCCOB7_CMDDATA3_SHIFT)) & FMUTEST_FCCOB7_CMDDATA3_MASK)
25529 /*! @} */
25530 
25531 /*! @name RESET_STATUS - FMU Initialization Tracking Register */
25532 /*! @{ */
25533 
25534 #define FMUTEST_RESET_STATUS_ARY_TRIM_DONE_MASK  (0x1U)
25535 #define FMUTEST_RESET_STATUS_ARY_TRIM_DONE_SHIFT (0U)
25536 /*! ARY_TRIM_DONE - Array Trim Complete
25537  *  0b0..Recall register load operation has not been completed
25538  *  0b1..Recall register load operation has completed
25539  */
25540 #define FMUTEST_RESET_STATUS_ARY_TRIM_DONE(x)    (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_ARY_TRIM_DONE_SHIFT)) & FMUTEST_RESET_STATUS_ARY_TRIM_DONE_MASK)
25541 
25542 #define FMUTEST_RESET_STATUS_FMU_PARM_EN_MASK    (0x2U)
25543 #define FMUTEST_RESET_STATUS_FMU_PARM_EN_SHIFT   (1U)
25544 /*! FMU_PARM_EN - Status of the C0DE_C0DEh check to enable loading of the FMU parameters
25545  *  0b0..C0DE_C0DEh check not attempted
25546  *  0b1..C0DE_C0DEh check completed
25547  */
25548 #define FMUTEST_RESET_STATUS_FMU_PARM_EN(x)      (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_FMU_PARM_EN_SHIFT)) & FMUTEST_RESET_STATUS_FMU_PARM_EN_MASK)
25549 
25550 #define FMUTEST_RESET_STATUS_FMU_PARM_DONE_MASK  (0x4U)
25551 #define FMUTEST_RESET_STATUS_FMU_PARM_DONE_SHIFT (2U)
25552 /*! FMU_PARM_DONE - FMU Register Load Complete
25553  *  0b0..FMU registers have not been loaded
25554  *  0b1..FMU registers have been loaded
25555  */
25556 #define FMUTEST_RESET_STATUS_FMU_PARM_DONE(x)    (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_FMU_PARM_DONE_SHIFT)) & FMUTEST_RESET_STATUS_FMU_PARM_DONE_MASK)
25557 
25558 #define FMUTEST_RESET_STATUS_SOC_TRIM_EN_MASK    (0x8U)
25559 #define FMUTEST_RESET_STATUS_SOC_TRIM_EN_SHIFT   (3U)
25560 /*! SOC_TRIM_EN - Status of the C0DE_C0DEh check to enable loading of the SoC trim settings
25561  *  0b0..C0DE_C0DEh check not attempted
25562  *  0b1..C0DE_C0DEh check completed
25563  */
25564 #define FMUTEST_RESET_STATUS_SOC_TRIM_EN(x)      (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_SOC_TRIM_EN_SHIFT)) & FMUTEST_RESET_STATUS_SOC_TRIM_EN_MASK)
25565 
25566 #define FMUTEST_RESET_STATUS_SOC_TRIM_ECC_MASK   (0x10U)
25567 #define FMUTEST_RESET_STATUS_SOC_TRIM_ECC_SHIFT  (4U)
25568 /*! SOC_TRIM_ECC - Status of the C0DE_C0DEh check for enabling ECC decoder during reads of SoC trim settings
25569  *  0b0..C0DE_C0DEh check failed
25570  *  0b1..C0DE_C0DEh check passed
25571  */
25572 #define FMUTEST_RESET_STATUS_SOC_TRIM_ECC(x)     (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_SOC_TRIM_ECC_SHIFT)) & FMUTEST_RESET_STATUS_SOC_TRIM_ECC_MASK)
25573 
25574 #define FMUTEST_RESET_STATUS_SOC_TRIM_DONE_MASK  (0x20U)
25575 #define FMUTEST_RESET_STATUS_SOC_TRIM_DONE_SHIFT (5U)
25576 /*! SOC_TRIM_DONE - SoC Trim Complete
25577  *  0b0..SoC Trim registers have not been updated
25578  *  0b1..All SoC Trim registers have been updated
25579  */
25580 #define FMUTEST_RESET_STATUS_SOC_TRIM_DONE(x)    (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_SOC_TRIM_DONE_SHIFT)) & FMUTEST_RESET_STATUS_SOC_TRIM_DONE_MASK)
25581 
25582 #define FMUTEST_RESET_STATUS_RPR_DONE_MASK       (0x40U)
25583 #define FMUTEST_RESET_STATUS_RPR_DONE_SHIFT      (6U)
25584 /*! RPR_DONE - Array Repair Complete
25585  *  0b0..Repair registers have not been loaded
25586  *  0b1..Repair registers have been loaded
25587  */
25588 #define FMUTEST_RESET_STATUS_RPR_DONE(x)         (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_RPR_DONE_SHIFT)) & FMUTEST_RESET_STATUS_RPR_DONE_MASK)
25589 
25590 #define FMUTEST_RESET_STATUS_INIT_DONE_MASK      (0x80U)
25591 #define FMUTEST_RESET_STATUS_INIT_DONE_SHIFT     (7U)
25592 /*! INIT_DONE - Initialization Done
25593  *  0b0..All initialization steps did not complete
25594  *  0b1..All initialization steps completed
25595  */
25596 #define FMUTEST_RESET_STATUS_INIT_DONE(x)        (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_INIT_DONE_SHIFT)) & FMUTEST_RESET_STATUS_INIT_DONE_MASK)
25597 
25598 #define FMUTEST_RESET_STATUS_RST_SF_ERR_MASK     (0x100U)
25599 #define FMUTEST_RESET_STATUS_RST_SF_ERR_SHIFT    (8U)
25600 /*! RST_SF_ERR - ECC Single Fault during Reset Recovery
25601  *  0b0..No single-bit faults detected during initialization
25602  *  0b1..At least one single ECC fault was detected during initialization
25603  */
25604 #define FMUTEST_RESET_STATUS_RST_SF_ERR(x)       (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_RST_SF_ERR_SHIFT)) & FMUTEST_RESET_STATUS_RST_SF_ERR_MASK)
25605 
25606 #define FMUTEST_RESET_STATUS_RST_DF_ERR_MASK     (0x200U)
25607 #define FMUTEST_RESET_STATUS_RST_DF_ERR_SHIFT    (9U)
25608 /*! RST_DF_ERR - ECC Double Fault during Reset Recovery
25609  *  0b0..No double-bit faults detected during initialization
25610  *  0b1..Double-bit ECC fault was detected during initialization
25611  */
25612 #define FMUTEST_RESET_STATUS_RST_DF_ERR(x)       (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_RST_DF_ERR_SHIFT)) & FMUTEST_RESET_STATUS_RST_DF_ERR_MASK)
25613 
25614 #define FMUTEST_RESET_STATUS_SOC_TRIM_DF_ERR_MASK (0x3FC00U)
25615 #define FMUTEST_RESET_STATUS_SOC_TRIM_DF_ERR_SHIFT (10U)
25616 /*! SOC_TRIM_DF_ERR - ECC Double Fault during load of SoC Trim phrases */
25617 #define FMUTEST_RESET_STATUS_SOC_TRIM_DF_ERR(x)  (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_SOC_TRIM_DF_ERR_SHIFT)) & FMUTEST_RESET_STATUS_SOC_TRIM_DF_ERR_MASK)
25618 
25619 #define FMUTEST_RESET_STATUS_RST_PATCH_LD_MASK   (0x40000U)
25620 #define FMUTEST_RESET_STATUS_RST_PATCH_LD_SHIFT  (18U)
25621 /*! RST_PATCH_LD - Reset Patch Required
25622  *  0b0..No patch required to be loaded during reset
25623  *  0b1..Patch loaded during reset
25624  */
25625 #define FMUTEST_RESET_STATUS_RST_PATCH_LD(x)     (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_RST_PATCH_LD_SHIFT)) & FMUTEST_RESET_STATUS_RST_PATCH_LD_MASK)
25626 
25627 #define FMUTEST_RESET_STATUS_RECALL_DATA_MISMATCH_MASK (0x80000U)
25628 #define FMUTEST_RESET_STATUS_RECALL_DATA_MISMATCH_SHIFT (19U)
25629 /*! RECALL_DATA_MISMATCH - Recall Data Mismatch
25630  *  0b0..Data read towards end of reset matched data read for Recall
25631  *  0b1..Data read towards end of reset did not match data read for recall
25632  */
25633 #define FMUTEST_RESET_STATUS_RECALL_DATA_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_RECALL_DATA_MISMATCH_SHIFT)) & FMUTEST_RESET_STATUS_RECALL_DATA_MISMATCH_MASK)
25634 /*! @} */
25635 
25636 /*! @name MCTL - FMU Control Register */
25637 /*! @{ */
25638 
25639 #define FMUTEST_MCTL_COREHLD_MASK                (0x1U)
25640 #define FMUTEST_MCTL_COREHLD_SHIFT               (0U)
25641 /*! COREHLD - Core Hold
25642  *  0b0..CPU access is allowed
25643  *  0b1..CPU access must be blocked
25644  */
25645 #define FMUTEST_MCTL_COREHLD(x)                  (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_COREHLD_SHIFT)) & FMUTEST_MCTL_COREHLD_MASK)
25646 
25647 #define FMUTEST_MCTL_LSACT_EN_MASK               (0x4U)
25648 #define FMUTEST_MCTL_LSACT_EN_SHIFT              (2U)
25649 /*! LSACT_EN - LSACTIVE Feature Enable
25650  *  0b0..LSACTIVE feature disabled completely: FCTRL[LSACTIVE] is forced low and no longer writable, LVE cannot assert at the TSMC array interface.
25651  *  0b1..LSACTIVE feature fully enabled and controllable by SoC and internal UINT SM.
25652  */
25653 #define FMUTEST_MCTL_LSACT_EN(x)                 (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_LSACT_EN_SHIFT)) & FMUTEST_MCTL_LSACT_EN_MASK)
25654 
25655 #define FMUTEST_MCTL_LSACTWREN_MASK              (0x8U)
25656 #define FMUTEST_MCTL_LSACTWREN_SHIFT             (3U)
25657 /*! LSACTWREN - LSACTIVE Write Enable
25658  *  0b0..Unrestricted write access allowed
25659  *  0b1..Write access while CMP set must match CMDDID and CMDPRT
25660  */
25661 #define FMUTEST_MCTL_LSACTWREN(x)                (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_LSACTWREN_SHIFT)) & FMUTEST_MCTL_LSACTWREN_MASK)
25662 
25663 #define FMUTEST_MCTL_MASTER_REPAIR_EN_MASK       (0x10U)
25664 #define FMUTEST_MCTL_MASTER_REPAIR_EN_SHIFT      (4U)
25665 /*! MASTER_REPAIR_EN - Master Repair Enable
25666  *  0b0..Repair disabled
25667  *  0b1..Repair enable determined by bit 0 of each REPAIR register
25668  */
25669 #define FMUTEST_MCTL_MASTER_REPAIR_EN(x)         (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_MASTER_REPAIR_EN_SHIFT)) & FMUTEST_MCTL_MASTER_REPAIR_EN_MASK)
25670 
25671 #define FMUTEST_MCTL_RFCMDEN_MASK                (0x20U)
25672 #define FMUTEST_MCTL_RFCMDEN_SHIFT               (5U)
25673 /*! RFCMDEN - RF Active Command Enable Control
25674  *  0b0..Flash commands blocked (CCIF not writable)
25675  *  0b1..Flash commands allowed
25676  */
25677 #define FMUTEST_MCTL_RFCMDEN(x)                  (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_RFCMDEN_SHIFT)) & FMUTEST_MCTL_RFCMDEN_MASK)
25678 
25679 #define FMUTEST_MCTL_CWSABTEN_MASK               (0x40U)
25680 #define FMUTEST_MCTL_CWSABTEN_SHIFT              (6U)
25681 /*! CWSABTEN - Command Write Sequence Abort Enable
25682  *  0b0..CWS abort feature is disabled
25683  *  0b1..CWS abort feature is enabled
25684  */
25685 #define FMUTEST_MCTL_CWSABTEN(x)                 (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_CWSABTEN_SHIFT)) & FMUTEST_MCTL_CWSABTEN_MASK)
25686 
25687 #define FMUTEST_MCTL_MRGRDDIS_MASK               (0x80U)
25688 #define FMUTEST_MCTL_MRGRDDIS_SHIFT              (7U)
25689 /*! MRGRDDIS - Margin Read Disable
25690  *  0b0..Margin Read Settings are enabled
25691  *  0b1..Margin Read Settings are disabled
25692  */
25693 #define FMUTEST_MCTL_MRGRDDIS(x)                 (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_MRGRDDIS_SHIFT)) & FMUTEST_MCTL_MRGRDDIS_MASK)
25694 
25695 #define FMUTEST_MCTL_MRGRD0_MASK                 (0xF00U)
25696 #define FMUTEST_MCTL_MRGRD0_SHIFT                (8U)
25697 /*! MRGRD0 - Margin Read Setting for Program */
25698 #define FMUTEST_MCTL_MRGRD0(x)                   (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_MRGRD0_SHIFT)) & FMUTEST_MCTL_MRGRD0_MASK)
25699 
25700 #define FMUTEST_MCTL_MRGRD1_MASK                 (0xF000U)
25701 #define FMUTEST_MCTL_MRGRD1_SHIFT                (12U)
25702 /*! MRGRD1 - Margin Read Setting for Erase */
25703 #define FMUTEST_MCTL_MRGRD1(x)                   (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_MRGRD1_SHIFT)) & FMUTEST_MCTL_MRGRD1_MASK)
25704 
25705 #define FMUTEST_MCTL_ERSAACK_MASK                (0x10000U)
25706 #define FMUTEST_MCTL_ERSAACK_SHIFT               (16U)
25707 /*! ERSAACK - Mass Erase (Erase All) Acknowledge
25708  *  0b0..Mass Erase operation is not active (operation has completed or has not started)
25709  *  0b1..Mass Erase operation is active (controller acknowledges that the soc_ersall_req input is asserted and will continue with the operation)
25710  */
25711 #define FMUTEST_MCTL_ERSAACK(x)                  (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_ERSAACK_SHIFT)) & FMUTEST_MCTL_ERSAACK_MASK)
25712 
25713 #define FMUTEST_MCTL_SCAN_OBS_MASK               (0x80000U)
25714 #define FMUTEST_MCTL_SCAN_OBS_SHIFT              (19U)
25715 /*! SCAN_OBS - Scan Observability Control
25716  *  0b0..Normal functional behavior
25717  *  0b1..Enables observation of signals that may otherwise be ATPG untestable
25718  */
25719 #define FMUTEST_MCTL_SCAN_OBS(x)                 (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_SCAN_OBS_SHIFT)) & FMUTEST_MCTL_SCAN_OBS_MASK)
25720 
25721 #define FMUTEST_MCTL_BIST_CTL_MASK               (0x100000U)
25722 #define FMUTEST_MCTL_BIST_CTL_SHIFT              (20U)
25723 /*! BIST_CTL - BIST IP Control
25724  *  0b0..BIST IP disabled
25725  *  0b1..BIST IP enabled
25726  */
25727 #define FMUTEST_MCTL_BIST_CTL(x)                 (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_BIST_CTL_SHIFT)) & FMUTEST_MCTL_BIST_CTL_MASK)
25728 
25729 #define FMUTEST_MCTL_SMWR_CTL_MASK               (0x200000U)
25730 #define FMUTEST_MCTL_SMWR_CTL_SHIFT              (21U)
25731 /*! SMWR_CTL - SMWR IP Control
25732  *  0b0..SMWR IP disabled
25733  *  0b1..SMWR IP enabled
25734  */
25735 #define FMUTEST_MCTL_SMWR_CTL(x)                 (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_SMWR_CTL_SHIFT)) & FMUTEST_MCTL_SMWR_CTL_MASK)
25736 
25737 #define FMUTEST_MCTL_SALV_DIS_MASK               (0x1000000U)
25738 #define FMUTEST_MCTL_SALV_DIS_SHIFT              (24U)
25739 /*! SALV_DIS - Salvage Disable
25740  *  0b0..Salvage enabled (ECC used during erase verify)
25741  *  0b1..Salvage disabled (ECC not used during erase verify)
25742  */
25743 #define FMUTEST_MCTL_SALV_DIS(x)                 (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_SALV_DIS_SHIFT)) & FMUTEST_MCTL_SALV_DIS_MASK)
25744 
25745 #define FMUTEST_MCTL_SOC_ECC_CTL_MASK            (0x2000000U)
25746 #define FMUTEST_MCTL_SOC_ECC_CTL_SHIFT           (25U)
25747 /*! SOC_ECC_CTL - SOC ECC Control
25748  *  0b0..ECC is enabled for SOC read access
25749  *  0b1..ECC is disabled for SOC read access
25750  */
25751 #define FMUTEST_MCTL_SOC_ECC_CTL(x)              (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_SOC_ECC_CTL_SHIFT)) & FMUTEST_MCTL_SOC_ECC_CTL_MASK)
25752 
25753 #define FMUTEST_MCTL_FMU_ECC_CTL_MASK            (0x4000000U)
25754 #define FMUTEST_MCTL_FMU_ECC_CTL_SHIFT           (26U)
25755 /*! FMU_ECC_CTL - FMU ECC Control
25756  *  0b0..ECC is enabled for FMU program operations
25757  *  0b1..ECC is disabled for FMU program operations
25758  */
25759 #define FMUTEST_MCTL_FMU_ECC_CTL(x)              (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_FMU_ECC_CTL_SHIFT)) & FMUTEST_MCTL_FMU_ECC_CTL_MASK)
25760 
25761 #define FMUTEST_MCTL_BIST_PWR_DIS_MASK           (0x20000000U)
25762 #define FMUTEST_MCTL_BIST_PWR_DIS_SHIFT          (29U)
25763 /*! BIST_PWR_DIS - BIST Power Mode Disable
25764  *  0b0..BIST DFT logic has full control of SLM and LVE when BIST is enabled (including during commands)
25765  *  0b1..BIST DFT logic has no control of SLM and LVE; power mode RTL is in complete control of SLM and LVE values
25766  */
25767 #define FMUTEST_MCTL_BIST_PWR_DIS(x)             (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_BIST_PWR_DIS_SHIFT)) & FMUTEST_MCTL_BIST_PWR_DIS_MASK)
25768 
25769 #define FMUTEST_MCTL_OSC_H_MASK                  (0x80000000U)
25770 #define FMUTEST_MCTL_OSC_H_SHIFT                 (31U)
25771 /*! OSC_H - Oscillator control
25772  *  0b0..Use APB clock
25773  *  0b1..Use a known fixed-frequency clock, e.g. 12 MHz
25774  */
25775 #define FMUTEST_MCTL_OSC_H(x)                    (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_OSC_H_SHIFT)) & FMUTEST_MCTL_OSC_H_MASK)
25776 /*! @} */
25777 
25778 /*! @name BSEL_GEN - FMU Block Select Generation Register */
25779 /*! @{ */
25780 
25781 #define FMUTEST_BSEL_GEN_SBSEL_GEN_MASK          (0x3U)
25782 #define FMUTEST_BSEL_GEN_SBSEL_GEN_SHIFT         (0U)
25783 /*! SBSEL_GEN - Generated SBSEL */
25784 #define FMUTEST_BSEL_GEN_SBSEL_GEN(x)            (((uint32_t)(((uint32_t)(x)) << FMUTEST_BSEL_GEN_SBSEL_GEN_SHIFT)) & FMUTEST_BSEL_GEN_SBSEL_GEN_MASK)
25785 
25786 #define FMUTEST_BSEL_GEN_MBSEL_GEN_MASK          (0x300U)
25787 #define FMUTEST_BSEL_GEN_MBSEL_GEN_SHIFT         (8U)
25788 /*! MBSEL_GEN - Generated MBSEL */
25789 #define FMUTEST_BSEL_GEN_MBSEL_GEN(x)            (((uint32_t)(((uint32_t)(x)) << FMUTEST_BSEL_GEN_MBSEL_GEN_SHIFT)) & FMUTEST_BSEL_GEN_MBSEL_GEN_MASK)
25790 /*! @} */
25791 
25792 /*! @name PWR_OPT - Power Mode Options Register */
25793 /*! @{ */
25794 
25795 #define FMUTEST_PWR_OPT_PD_CDIV_MASK             (0xFFU)
25796 #define FMUTEST_PWR_OPT_PD_CDIV_SHIFT            (0U)
25797 /*! PD_CDIV - Power Down Clock Divider Setting */
25798 #define FMUTEST_PWR_OPT_PD_CDIV(x)               (((uint32_t)(((uint32_t)(x)) << FMUTEST_PWR_OPT_PD_CDIV_SHIFT)) & FMUTEST_PWR_OPT_PD_CDIV_MASK)
25799 
25800 #define FMUTEST_PWR_OPT_SLM_COUNT_MASK           (0x3FF0000U)
25801 #define FMUTEST_PWR_OPT_SLM_COUNT_SHIFT          (16U)
25802 /*! SLM_COUNT - Sleep Recovery Timer Count */
25803 #define FMUTEST_PWR_OPT_SLM_COUNT(x)             (((uint32_t)(((uint32_t)(x)) << FMUTEST_PWR_OPT_SLM_COUNT_SHIFT)) & FMUTEST_PWR_OPT_SLM_COUNT_MASK)
25804 
25805 #define FMUTEST_PWR_OPT_PD_TIMER_EN_MASK         (0x80000000U)
25806 #define FMUTEST_PWR_OPT_PD_TIMER_EN_SHIFT        (31U)
25807 /*! PD_TIMER_EN - Power Down BIST Timer Enable
25808  *  0b0..BIST timer is not triggered during Power Down recovery
25809  *  0b1..BIST timer is triggered during Power Down recovery (default behavior)
25810  */
25811 #define FMUTEST_PWR_OPT_PD_TIMER_EN(x)           (((uint32_t)(((uint32_t)(x)) << FMUTEST_PWR_OPT_PD_TIMER_EN_SHIFT)) & FMUTEST_PWR_OPT_PD_TIMER_EN_MASK)
25812 /*! @} */
25813 
25814 /*! @name CMD_CHECK - FMU Command Check Register */
25815 /*! @{ */
25816 
25817 #define FMUTEST_CMD_CHECK_ALIGNFAIL_PHR_MASK     (0x1U)
25818 #define FMUTEST_CMD_CHECK_ALIGNFAIL_PHR_SHIFT    (0U)
25819 /*! ALIGNFAIL_PHR - Phrase Alignment Fail
25820  *  0b0..The address is phrase-aligned
25821  *  0b1..The address is not phrase-aligned
25822  */
25823 #define FMUTEST_CMD_CHECK_ALIGNFAIL_PHR(x)       (((uint32_t)(((uint32_t)(x)) << FMUTEST_CMD_CHECK_ALIGNFAIL_PHR_SHIFT)) & FMUTEST_CMD_CHECK_ALIGNFAIL_PHR_MASK)
25824 
25825 #define FMUTEST_CMD_CHECK_ALIGNFAIL_PG_MASK      (0x2U)
25826 #define FMUTEST_CMD_CHECK_ALIGNFAIL_PG_SHIFT     (1U)
25827 /*! ALIGNFAIL_PG - Page Alignment Fail
25828  *  0b0..The address is page-aligned
25829  *  0b1..The address is not page-aligned
25830  */
25831 #define FMUTEST_CMD_CHECK_ALIGNFAIL_PG(x)        (((uint32_t)(((uint32_t)(x)) << FMUTEST_CMD_CHECK_ALIGNFAIL_PG_SHIFT)) & FMUTEST_CMD_CHECK_ALIGNFAIL_PG_MASK)
25832 
25833 #define FMUTEST_CMD_CHECK_ALIGNFAIL_SCR_MASK     (0x4U)
25834 #define FMUTEST_CMD_CHECK_ALIGNFAIL_SCR_SHIFT    (2U)
25835 /*! ALIGNFAIL_SCR - Sector Alignment Fail
25836  *  0b0..The address is sector-aligned
25837  *  0b1..The address is not sector-aligned
25838  */
25839 #define FMUTEST_CMD_CHECK_ALIGNFAIL_SCR(x)       (((uint32_t)(((uint32_t)(x)) << FMUTEST_CMD_CHECK_ALIGNFAIL_SCR_SHIFT)) & FMUTEST_CMD_CHECK_ALIGNFAIL_SCR_MASK)
25840 
25841 #define FMUTEST_CMD_CHECK_ALIGNFAIL_BLK_MASK     (0x8U)
25842 #define FMUTEST_CMD_CHECK_ALIGNFAIL_BLK_SHIFT    (3U)
25843 /*! ALIGNFAIL_BLK - Block Alignment Fail
25844  *  0b0..The address is block-aligned
25845  *  0b1..The address is not block-aligned
25846  */
25847 #define FMUTEST_CMD_CHECK_ALIGNFAIL_BLK(x)       (((uint32_t)(((uint32_t)(x)) << FMUTEST_CMD_CHECK_ALIGNFAIL_BLK_SHIFT)) & FMUTEST_CMD_CHECK_ALIGNFAIL_BLK_MASK)
25848 
25849 #define FMUTEST_CMD_CHECK_ADDR_FAIL_MASK         (0x10U)
25850 #define FMUTEST_CMD_CHECK_ADDR_FAIL_SHIFT        (4U)
25851 /*! ADDR_FAIL - Address Fail
25852  *  0b0..The address is within the flash or IFR address space
25853  *  0b1..The address is outside the flash or IFR address space
25854  */
25855 #define FMUTEST_CMD_CHECK_ADDR_FAIL(x)           (((uint32_t)(((uint32_t)(x)) << FMUTEST_CMD_CHECK_ADDR_FAIL_SHIFT)) & FMUTEST_CMD_CHECK_ADDR_FAIL_MASK)
25856 
25857 #define FMUTEST_CMD_CHECK_IFR_CMD_MASK           (0x20U)
25858 #define FMUTEST_CMD_CHECK_IFR_CMD_SHIFT          (5U)
25859 /*! IFR_CMD - IFR Command
25860  *  0b0..The command operates on a main flash address
25861  *  0b1..The command operates on an IFR address
25862  */
25863 #define FMUTEST_CMD_CHECK_IFR_CMD(x)             (((uint32_t)(((uint32_t)(x)) << FMUTEST_CMD_CHECK_IFR_CMD_SHIFT)) & FMUTEST_CMD_CHECK_IFR_CMD_MASK)
25864 
25865 #define FMUTEST_CMD_CHECK_ALL_CMD_MASK           (0x40U)
25866 #define FMUTEST_CMD_CHECK_ALL_CMD_SHIFT          (6U)
25867 /*! ALL_CMD - All Blocks Command
25868  *  0b0..The command operates on a single flash block
25869  *  0b1..The command operates on all flash blocks
25870  */
25871 #define FMUTEST_CMD_CHECK_ALL_CMD(x)             (((uint32_t)(((uint32_t)(x)) << FMUTEST_CMD_CHECK_ALL_CMD_SHIFT)) & FMUTEST_CMD_CHECK_ALL_CMD_MASK)
25872 
25873 #define FMUTEST_CMD_CHECK_RANGE_FAIL_MASK        (0x80U)
25874 #define FMUTEST_CMD_CHECK_RANGE_FAIL_SHIFT       (7U)
25875 /*! RANGE_FAIL - Address Range Fail
25876  *  0b0..The address range is valid
25877  *  0b1..The address range is invalid
25878  */
25879 #define FMUTEST_CMD_CHECK_RANGE_FAIL(x)          (((uint32_t)(((uint32_t)(x)) << FMUTEST_CMD_CHECK_RANGE_FAIL_SHIFT)) & FMUTEST_CMD_CHECK_RANGE_FAIL_MASK)
25880 
25881 #define FMUTEST_CMD_CHECK_SCR_ALIGN_CHK_MASK     (0x100U)
25882 #define FMUTEST_CMD_CHECK_SCR_ALIGN_CHK_SHIFT    (8U)
25883 /*! SCR_ALIGN_CHK - Sector Alignment Check
25884  *  0b0..No sector alignment check
25885  *  0b1..Sector alignment check
25886  */
25887 #define FMUTEST_CMD_CHECK_SCR_ALIGN_CHK(x)       (((uint32_t)(((uint32_t)(x)) << FMUTEST_CMD_CHECK_SCR_ALIGN_CHK_SHIFT)) & FMUTEST_CMD_CHECK_SCR_ALIGN_CHK_MASK)
25888 
25889 #define FMUTEST_CMD_CHECK_OPTION_FAIL_MASK       (0x200U)
25890 #define FMUTEST_CMD_CHECK_OPTION_FAIL_SHIFT      (9U)
25891 /*! OPTION_FAIL - Option Check Fail
25892  *  0b0..Option check passes for read command or command is not a read command
25893  *  0b1..Option check fails for read command
25894  */
25895 #define FMUTEST_CMD_CHECK_OPTION_FAIL(x)         (((uint32_t)(((uint32_t)(x)) << FMUTEST_CMD_CHECK_OPTION_FAIL_SHIFT)) & FMUTEST_CMD_CHECK_OPTION_FAIL_MASK)
25896 
25897 #define FMUTEST_CMD_CHECK_ILLEGAL_CMD_MASK       (0x400U)
25898 #define FMUTEST_CMD_CHECK_ILLEGAL_CMD_SHIFT      (10U)
25899 /*! ILLEGAL_CMD - Illegal Command
25900  *  0b0..Command is legal
25901  *  0b1..Command is illegal
25902  */
25903 #define FMUTEST_CMD_CHECK_ILLEGAL_CMD(x)         (((uint32_t)(((uint32_t)(x)) << FMUTEST_CMD_CHECK_ILLEGAL_CMD_SHIFT)) & FMUTEST_CMD_CHECK_ILLEGAL_CMD_MASK)
25904 /*! @} */
25905 
25906 /*! @name BSEL - FMU Block Select Register */
25907 /*! @{ */
25908 
25909 #define FMUTEST_BSEL_SBSEL_MASK                  (0x3U)
25910 #define FMUTEST_BSEL_SBSEL_SHIFT                 (0U)
25911 /*! SBSEL - Slave Block Select */
25912 #define FMUTEST_BSEL_SBSEL(x)                    (((uint32_t)(((uint32_t)(x)) << FMUTEST_BSEL_SBSEL_SHIFT)) & FMUTEST_BSEL_SBSEL_MASK)
25913 
25914 #define FMUTEST_BSEL_MBSEL_MASK                  (0x300U)
25915 #define FMUTEST_BSEL_MBSEL_SHIFT                 (8U)
25916 /*! MBSEL - Master Block Select */
25917 #define FMUTEST_BSEL_MBSEL(x)                    (((uint32_t)(((uint32_t)(x)) << FMUTEST_BSEL_MBSEL_SHIFT)) & FMUTEST_BSEL_MBSEL_MASK)
25918 /*! @} */
25919 
25920 /*! @name MSIZE - FMU Memory Size Register */
25921 /*! @{ */
25922 
25923 #define FMUTEST_MSIZE_MAXADDR0_MASK              (0xFFU)
25924 #define FMUTEST_MSIZE_MAXADDR0_SHIFT             (0U)
25925 /*! MAXADDR0 - Size of Flash Block 0 */
25926 #define FMUTEST_MSIZE_MAXADDR0(x)                (((uint32_t)(((uint32_t)(x)) << FMUTEST_MSIZE_MAXADDR0_SHIFT)) & FMUTEST_MSIZE_MAXADDR0_MASK)
25927 
25928 #define FMUTEST_MSIZE_MAXADDR1_MASK              (0xFF00U)
25929 #define FMUTEST_MSIZE_MAXADDR1_SHIFT             (8U)
25930 /*! MAXADDR1 - Size of Flash Block 1 */
25931 #define FMUTEST_MSIZE_MAXADDR1(x)                (((uint32_t)(((uint32_t)(x)) << FMUTEST_MSIZE_MAXADDR1_SHIFT)) & FMUTEST_MSIZE_MAXADDR1_MASK)
25932 /*! @} */
25933 
25934 /*! @name FLASH_RD_ADD - Flash Read Address Register */
25935 /*! @{ */
25936 
25937 #define FMUTEST_FLASH_RD_ADD_FLASH_RD_ADD_MASK   (0xFFFFFFFFU)
25938 #define FMUTEST_FLASH_RD_ADD_FLASH_RD_ADD_SHIFT  (0U)
25939 /*! FLASH_RD_ADD - Flash Read Address */
25940 #define FMUTEST_FLASH_RD_ADD_FLASH_RD_ADD(x)     (((uint32_t)(((uint32_t)(x)) << FMUTEST_FLASH_RD_ADD_FLASH_RD_ADD_SHIFT)) & FMUTEST_FLASH_RD_ADD_FLASH_RD_ADD_MASK)
25941 /*! @} */
25942 
25943 /*! @name FLASH_STOP_ADD - Flash Stop Address Register */
25944 /*! @{ */
25945 
25946 #define FMUTEST_FLASH_STOP_ADD_FLASH_STOP_ADD_MASK (0xFFFFFFFFU)
25947 #define FMUTEST_FLASH_STOP_ADD_FLASH_STOP_ADD_SHIFT (0U)
25948 /*! FLASH_STOP_ADD - Flash Stop Address */
25949 #define FMUTEST_FLASH_STOP_ADD_FLASH_STOP_ADD(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FLASH_STOP_ADD_FLASH_STOP_ADD_SHIFT)) & FMUTEST_FLASH_STOP_ADD_FLASH_STOP_ADD_MASK)
25950 /*! @} */
25951 
25952 /*! @name FLASH_RD_CTRL - Flash Read Control Register */
25953 /*! @{ */
25954 
25955 #define FMUTEST_FLASH_RD_CTRL_FLASH_RD_MASK      (0x1U)
25956 #define FMUTEST_FLASH_RD_CTRL_FLASH_RD_SHIFT     (0U)
25957 /*! FLASH_RD - Flash Read Enable
25958  *  0b0..Manual flash read not enabled.(default)
25959  *  0b1..Manual flash read enabled
25960  */
25961 #define FMUTEST_FLASH_RD_CTRL_FLASH_RD(x)        (((uint32_t)(((uint32_t)(x)) << FMUTEST_FLASH_RD_CTRL_FLASH_RD_SHIFT)) & FMUTEST_FLASH_RD_CTRL_FLASH_RD_MASK)
25962 
25963 #define FMUTEST_FLASH_RD_CTRL_WIDE_LOAD_MASK     (0x2U)
25964 #define FMUTEST_FLASH_RD_CTRL_WIDE_LOAD_SHIFT    (1U)
25965 /*! WIDE_LOAD - Wide Load Enable
25966  *  0b0..Wide load mode disabled (default)
25967  *  0b1..Wide load mode enabled
25968  */
25969 #define FMUTEST_FLASH_RD_CTRL_WIDE_LOAD(x)       (((uint32_t)(((uint32_t)(x)) << FMUTEST_FLASH_RD_CTRL_WIDE_LOAD_SHIFT)) & FMUTEST_FLASH_RD_CTRL_WIDE_LOAD_MASK)
25970 
25971 #define FMUTEST_FLASH_RD_CTRL_SINGLE_RD_MASK     (0x4U)
25972 #define FMUTEST_FLASH_RD_CTRL_SINGLE_RD_SHIFT    (2U)
25973 /*! SINGLE_RD - Single Flash Read
25974  *  0b0..Normal UINT operation
25975  *  0b1..UINT configured for single cycle reads
25976  */
25977 #define FMUTEST_FLASH_RD_CTRL_SINGLE_RD(x)       (((uint32_t)(((uint32_t)(x)) << FMUTEST_FLASH_RD_CTRL_SINGLE_RD_SHIFT)) & FMUTEST_FLASH_RD_CTRL_SINGLE_RD_MASK)
25978 /*! @} */
25979 
25980 /*! @name MM_ADDR - Memory Map Address Register */
25981 /*! @{ */
25982 
25983 #define FMUTEST_MM_ADDR_MM_ADDR_MASK             (0xFFFFFFFFU)
25984 #define FMUTEST_MM_ADDR_MM_ADDR_SHIFT            (0U)
25985 /*! MM_ADDR - Memory Map Address */
25986 #define FMUTEST_MM_ADDR_MM_ADDR(x)               (((uint32_t)(((uint32_t)(x)) << FMUTEST_MM_ADDR_MM_ADDR_SHIFT)) & FMUTEST_MM_ADDR_MM_ADDR_MASK)
25987 /*! @} */
25988 
25989 /*! @name MM_WDATA - Memory Map Write Data Register */
25990 /*! @{ */
25991 
25992 #define FMUTEST_MM_WDATA_MM_WDATA_MASK           (0xFFFFFFFFU)
25993 #define FMUTEST_MM_WDATA_MM_WDATA_SHIFT          (0U)
25994 /*! MM_WDATA - Memory Map Write Data */
25995 #define FMUTEST_MM_WDATA_MM_WDATA(x)             (((uint32_t)(((uint32_t)(x)) << FMUTEST_MM_WDATA_MM_WDATA_SHIFT)) & FMUTEST_MM_WDATA_MM_WDATA_MASK)
25996 /*! @} */
25997 
25998 /*! @name MM_CTL - Memory Map Control Register */
25999 /*! @{ */
26000 
26001 #define FMUTEST_MM_CTL_MM_SEL_MASK               (0x1U)
26002 #define FMUTEST_MM_CTL_MM_SEL_SHIFT              (0U)
26003 /*! MM_SEL - Register Access Enable */
26004 #define FMUTEST_MM_CTL_MM_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << FMUTEST_MM_CTL_MM_SEL_SHIFT)) & FMUTEST_MM_CTL_MM_SEL_MASK)
26005 
26006 #define FMUTEST_MM_CTL_MM_RD_MASK                (0x2U)
26007 #define FMUTEST_MM_CTL_MM_RD_SHIFT               (1U)
26008 /*! MM_RD - Register R/W Control
26009  *  0b0..Write to register
26010  *  0b1..Read register
26011  */
26012 #define FMUTEST_MM_CTL_MM_RD(x)                  (((uint32_t)(((uint32_t)(x)) << FMUTEST_MM_CTL_MM_RD_SHIFT)) & FMUTEST_MM_CTL_MM_RD_MASK)
26013 
26014 #define FMUTEST_MM_CTL_BIST_ON_MASK              (0x4U)
26015 #define FMUTEST_MM_CTL_BIST_ON_SHIFT             (2U)
26016 /*! BIST_ON - BIST on
26017  *  0b0..BIST enable not forced by user interface
26018  *  0b1..BIST enable control by user interface
26019  */
26020 #define FMUTEST_MM_CTL_BIST_ON(x)                (((uint32_t)(((uint32_t)(x)) << FMUTEST_MM_CTL_BIST_ON_SHIFT)) & FMUTEST_MM_CTL_BIST_ON_MASK)
26021 
26022 #define FMUTEST_MM_CTL_FORCE_SW_CLK_MASK         (0x8U)
26023 #define FMUTEST_MM_CTL_FORCE_SW_CLK_SHIFT        (3U)
26024 /*! FORCE_SW_CLK - Force Switch Clock
26025  *  0b0..Switch clock not forced on (gated normally)
26026  *  0b1..Switch clock forced on
26027  */
26028 #define FMUTEST_MM_CTL_FORCE_SW_CLK(x)           (((uint32_t)(((uint32_t)(x)) << FMUTEST_MM_CTL_FORCE_SW_CLK_SHIFT)) & FMUTEST_MM_CTL_FORCE_SW_CLK_MASK)
26029 /*! @} */
26030 
26031 /*! @name UINT_CTL - User Interface Control Register */
26032 /*! @{ */
26033 
26034 #define FMUTEST_UINT_CTL_SET_FAIL_MASK           (0x1U)
26035 #define FMUTEST_UINT_CTL_SET_FAIL_SHIFT          (0U)
26036 /*! SET_FAIL - Set Fail On Exit
26037  *  0b0..FAIL flag should not be set on command exit (no failure detected)
26038  *  0b1..FAIL flag should be set on command exit
26039  */
26040 #define FMUTEST_UINT_CTL_SET_FAIL(x)             (((uint32_t)(((uint32_t)(x)) << FMUTEST_UINT_CTL_SET_FAIL_SHIFT)) & FMUTEST_UINT_CTL_SET_FAIL_MASK)
26041 
26042 #define FMUTEST_UINT_CTL_DBERR_MASK              (0x2U)
26043 #define FMUTEST_UINT_CTL_DBERR_SHIFT             (1U)
26044 /*! DBERR - Double-Bit ECC Fault Detect
26045  *  0b0..No double-bit fault detected during UINT-driven read sequence
26046  *  0b1..Double-bit fault detected during UINT-driven read sequence
26047  */
26048 #define FMUTEST_UINT_CTL_DBERR(x)                (((uint32_t)(((uint32_t)(x)) << FMUTEST_UINT_CTL_DBERR_SHIFT)) & FMUTEST_UINT_CTL_DBERR_MASK)
26049 /*! @} */
26050 
26051 /*! @name RD_DATA0 - Read Data 0 Register */
26052 /*! @{ */
26053 
26054 #define FMUTEST_RD_DATA0_RD_DATA0_MASK           (0xFFFFFFFFU)
26055 #define FMUTEST_RD_DATA0_RD_DATA0_SHIFT          (0U)
26056 /*! RD_DATA0 - Read Data 0 */
26057 #define FMUTEST_RD_DATA0_RD_DATA0(x)             (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_DATA0_RD_DATA0_SHIFT)) & FMUTEST_RD_DATA0_RD_DATA0_MASK)
26058 /*! @} */
26059 
26060 /*! @name RD_DATA1 - Read Data 1 Register */
26061 /*! @{ */
26062 
26063 #define FMUTEST_RD_DATA1_RD_DATA1_MASK           (0xFFFFFFFFU)
26064 #define FMUTEST_RD_DATA1_RD_DATA1_SHIFT          (0U)
26065 /*! RD_DATA1 - Read Data 1 */
26066 #define FMUTEST_RD_DATA1_RD_DATA1(x)             (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_DATA1_RD_DATA1_SHIFT)) & FMUTEST_RD_DATA1_RD_DATA1_MASK)
26067 /*! @} */
26068 
26069 /*! @name RD_DATA2 - Read Data 2 Register */
26070 /*! @{ */
26071 
26072 #define FMUTEST_RD_DATA2_RD_DATA2_MASK           (0xFFFFFFFFU)
26073 #define FMUTEST_RD_DATA2_RD_DATA2_SHIFT          (0U)
26074 /*! RD_DATA2 - Read Data 2 */
26075 #define FMUTEST_RD_DATA2_RD_DATA2(x)             (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_DATA2_RD_DATA2_SHIFT)) & FMUTEST_RD_DATA2_RD_DATA2_MASK)
26076 /*! @} */
26077 
26078 /*! @name RD_DATA3 - Read Data 3 Register */
26079 /*! @{ */
26080 
26081 #define FMUTEST_RD_DATA3_RD_DATA3_MASK           (0xFFFFFFFFU)
26082 #define FMUTEST_RD_DATA3_RD_DATA3_SHIFT          (0U)
26083 /*! RD_DATA3 - Read Data 3 */
26084 #define FMUTEST_RD_DATA3_RD_DATA3(x)             (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_DATA3_RD_DATA3_SHIFT)) & FMUTEST_RD_DATA3_RD_DATA3_MASK)
26085 /*! @} */
26086 
26087 /*! @name PARITY - Parity Register */
26088 /*! @{ */
26089 
26090 #define FMUTEST_PARITY_PARITY_MASK               (0x1FFU)
26091 #define FMUTEST_PARITY_PARITY_SHIFT              (0U)
26092 /*! PARITY - Read data [136:128] */
26093 #define FMUTEST_PARITY_PARITY(x)                 (((uint32_t)(((uint32_t)(x)) << FMUTEST_PARITY_PARITY_SHIFT)) & FMUTEST_PARITY_PARITY_MASK)
26094 /*! @} */
26095 
26096 /*! @name RD_PATH_CTRL_STATUS - Read Path Control and Status Register */
26097 /*! @{ */
26098 
26099 #define FMUTEST_RD_PATH_CTRL_STATUS_RD_CAPT_MASK (0xFFU)
26100 #define FMUTEST_RD_PATH_CTRL_STATUS_RD_CAPT_SHIFT (0U)
26101 /*! RD_CAPT - Read Capture Clock Periods */
26102 #define FMUTEST_RD_PATH_CTRL_STATUS_RD_CAPT(x)   (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_RD_CAPT_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_RD_CAPT_MASK)
26103 
26104 #define FMUTEST_RD_PATH_CTRL_STATUS_SE_SIZE_MASK (0xFF00U)
26105 #define FMUTEST_RD_PATH_CTRL_STATUS_SE_SIZE_SHIFT (8U)
26106 /*! SE_SIZE - SE Clock Periods */
26107 #define FMUTEST_RD_PATH_CTRL_STATUS_SE_SIZE(x)   (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_SE_SIZE_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_SE_SIZE_MASK)
26108 
26109 #define FMUTEST_RD_PATH_CTRL_STATUS_ECC_ENABLEB_MASK (0x10000U)
26110 #define FMUTEST_RD_PATH_CTRL_STATUS_ECC_ENABLEB_SHIFT (16U)
26111 /*! ECC_ENABLEB - ECC Decoder Control
26112  *  0b0..ECC decoder enabled (default)
26113  *  0b1..ECC decoder disabled
26114  */
26115 #define FMUTEST_RD_PATH_CTRL_STATUS_ECC_ENABLEB(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_ECC_ENABLEB_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_ECC_ENABLEB_MASK)
26116 
26117 #define FMUTEST_RD_PATH_CTRL_STATUS_MISR_EN_MASK (0x20000U)
26118 #define FMUTEST_RD_PATH_CTRL_STATUS_MISR_EN_SHIFT (17U)
26119 /*! MISR_EN - MISR Enable
26120  *  0b0..MISR option disabled (default)
26121  *  0b1..MISR option enabled
26122  */
26123 #define FMUTEST_RD_PATH_CTRL_STATUS_MISR_EN(x)   (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_MISR_EN_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_MISR_EN_MASK)
26124 
26125 #define FMUTEST_RD_PATH_CTRL_STATUS_CPY_PAR_EN_MASK (0x40000U)
26126 #define FMUTEST_RD_PATH_CTRL_STATUS_CPY_PAR_EN_SHIFT (18U)
26127 /*! CPY_PAR_EN - Copy Parity Enable
26128  *  0b0..Copy parity disabled
26129  *  0b1..Copy parity enabled
26130  */
26131 #define FMUTEST_RD_PATH_CTRL_STATUS_CPY_PAR_EN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_CPY_PAR_EN_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_CPY_PAR_EN_MASK)
26132 
26133 #define FMUTEST_RD_PATH_CTRL_STATUS_BIST_MUX_TO_SMW_MASK (0x80000U)
26134 #define FMUTEST_RD_PATH_CTRL_STATUS_BIST_MUX_TO_SMW_SHIFT (19U)
26135 /*! BIST_MUX_TO_SMW - BIST Mux to SMW
26136  *  0b0..BIST drives fields
26137  *  0b1..SMW registers drive fields
26138  */
26139 #define FMUTEST_RD_PATH_CTRL_STATUS_BIST_MUX_TO_SMW(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_BIST_MUX_TO_SMW_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_BIST_MUX_TO_SMW_MASK)
26140 
26141 #define FMUTEST_RD_PATH_CTRL_STATUS_AD_SET_MASK  (0xF00000U)
26142 #define FMUTEST_RD_PATH_CTRL_STATUS_AD_SET_SHIFT (20U)
26143 /*! AD_SET - Multi-Cycle Address Setup Time */
26144 #define FMUTEST_RD_PATH_CTRL_STATUS_AD_SET(x)    (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_AD_SET_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_AD_SET_MASK)
26145 
26146 #define FMUTEST_RD_PATH_CTRL_STATUS_WR_PATH_EN_MASK (0x1000000U)
26147 #define FMUTEST_RD_PATH_CTRL_STATUS_WR_PATH_EN_SHIFT (24U)
26148 /*! WR_PATH_EN - Write Path Enable
26149  *  0b0..Writes to BIST setting registers driven by MM_WDATA
26150  *  0b1..Writes to BIST setting registers driven by SMW_DIN
26151  */
26152 #define FMUTEST_RD_PATH_CTRL_STATUS_WR_PATH_EN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_WR_PATH_EN_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_WR_PATH_EN_MASK)
26153 
26154 #define FMUTEST_RD_PATH_CTRL_STATUS_WR_PATH_ECC_EN_MASK (0x2000000U)
26155 #define FMUTEST_RD_PATH_CTRL_STATUS_WR_PATH_ECC_EN_SHIFT (25U)
26156 /*! WR_PATH_ECC_EN - Write Path ECC Enable
26157  *  0b0..ECC encoding disabled
26158  *  0b1..ECC encoding enabled
26159  */
26160 #define FMUTEST_RD_PATH_CTRL_STATUS_WR_PATH_ECC_EN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_WR_PATH_ECC_EN_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_WR_PATH_ECC_EN_MASK)
26161 
26162 #define FMUTEST_RD_PATH_CTRL_STATUS_DBERR_REG_MASK (0x4000000U)
26163 #define FMUTEST_RD_PATH_CTRL_STATUS_DBERR_REG_SHIFT (26U)
26164 /*! DBERR_REG - Double-Bit Error
26165  *  0b0..Double-bit fault not detected
26166  *  0b1..Double-bit fault detected on previous UINT flash read
26167  */
26168 #define FMUTEST_RD_PATH_CTRL_STATUS_DBERR_REG(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_DBERR_REG_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_DBERR_REG_MASK)
26169 
26170 #define FMUTEST_RD_PATH_CTRL_STATUS_SBERR_REG_MASK (0x8000000U)
26171 #define FMUTEST_RD_PATH_CTRL_STATUS_SBERR_REG_SHIFT (27U)
26172 /*! SBERR_REG - Single-Bit Error
26173  *  0b0..Single-bit fault not detected
26174  *  0b1..Single-bit fault detected on previous UINT flash read
26175  */
26176 #define FMUTEST_RD_PATH_CTRL_STATUS_SBERR_REG(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_SBERR_REG_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_SBERR_REG_MASK)
26177 
26178 #define FMUTEST_RD_PATH_CTRL_STATUS_CPY_PHRASE_EN_MASK (0x10000000U)
26179 #define FMUTEST_RD_PATH_CTRL_STATUS_CPY_PHRASE_EN_SHIFT (28U)
26180 /*! CPY_PHRASE_EN - Copy Phrase Enable
26181  *  0b0..Copy Flash read data disabled
26182  *  0b1..Copy Flash read data enabled
26183  */
26184 #define FMUTEST_RD_PATH_CTRL_STATUS_CPY_PHRASE_EN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_CPY_PHRASE_EN_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_CPY_PHRASE_EN_MASK)
26185 
26186 #define FMUTEST_RD_PATH_CTRL_STATUS_SMW_ARRAY1_SMW0_SEL_MASK (0x20000000U)
26187 #define FMUTEST_RD_PATH_CTRL_STATUS_SMW_ARRAY1_SMW0_SEL_SHIFT (29U)
26188 /*! SMW_ARRAY1_SMW0_SEL - SMW_ARRAY1_SMW0_SEL
26189  *  0b0..Select block 0
26190  *  0b1..Select block 1
26191  */
26192 #define FMUTEST_RD_PATH_CTRL_STATUS_SMW_ARRAY1_SMW0_SEL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_SMW_ARRAY1_SMW0_SEL_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_SMW_ARRAY1_SMW0_SEL_MASK)
26193 
26194 #define FMUTEST_RD_PATH_CTRL_STATUS_BIST_ECC_EN_MASK (0x40000000U)
26195 #define FMUTEST_RD_PATH_CTRL_STATUS_BIST_ECC_EN_SHIFT (30U)
26196 /*! BIST_ECC_EN - BIST ECC Enable
26197  *  0b0..ECC correction disabled
26198  *  0b1..ECC correction enabled
26199  */
26200 #define FMUTEST_RD_PATH_CTRL_STATUS_BIST_ECC_EN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_BIST_ECC_EN_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_BIST_ECC_EN_MASK)
26201 
26202 #define FMUTEST_RD_PATH_CTRL_STATUS_LAST_READ_MASK (0x80000000U)
26203 #define FMUTEST_RD_PATH_CTRL_STATUS_LAST_READ_SHIFT (31U)
26204 /*! LAST_READ - Last Read
26205  *  0b0..Latest read not last in multi-address operation
26206  *  0b1..Latest read last in multi-address operation
26207  */
26208 #define FMUTEST_RD_PATH_CTRL_STATUS_LAST_READ(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_LAST_READ_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_LAST_READ_MASK)
26209 /*! @} */
26210 
26211 /*! @name SMW_DIN0 - SMW DIN 0 Register */
26212 /*! @{ */
26213 
26214 #define FMUTEST_SMW_DIN0_SMW_DIN0_MASK           (0xFFFFFFFFU)
26215 #define FMUTEST_SMW_DIN0_SMW_DIN0_SHIFT          (0U)
26216 /*! SMW_DIN0 - SMW DIN 0 */
26217 #define FMUTEST_SMW_DIN0_SMW_DIN0(x)             (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_DIN0_SMW_DIN0_SHIFT)) & FMUTEST_SMW_DIN0_SMW_DIN0_MASK)
26218 /*! @} */
26219 
26220 /*! @name SMW_DIN1 - SMW DIN 1 Register */
26221 /*! @{ */
26222 
26223 #define FMUTEST_SMW_DIN1_SMW_DIN1_MASK           (0xFFFFFFFFU)
26224 #define FMUTEST_SMW_DIN1_SMW_DIN1_SHIFT          (0U)
26225 /*! SMW_DIN1 - SMW DIN 1 */
26226 #define FMUTEST_SMW_DIN1_SMW_DIN1(x)             (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_DIN1_SMW_DIN1_SHIFT)) & FMUTEST_SMW_DIN1_SMW_DIN1_MASK)
26227 /*! @} */
26228 
26229 /*! @name SMW_DIN2 - SMW DIN 2 Register */
26230 /*! @{ */
26231 
26232 #define FMUTEST_SMW_DIN2_SMW_DIN2_MASK           (0xFFFFFFFFU)
26233 #define FMUTEST_SMW_DIN2_SMW_DIN2_SHIFT          (0U)
26234 /*! SMW_DIN2 - SMW DIN 2 */
26235 #define FMUTEST_SMW_DIN2_SMW_DIN2(x)             (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_DIN2_SMW_DIN2_SHIFT)) & FMUTEST_SMW_DIN2_SMW_DIN2_MASK)
26236 /*! @} */
26237 
26238 /*! @name SMW_DIN3 - SMW DIN 3 Register */
26239 /*! @{ */
26240 
26241 #define FMUTEST_SMW_DIN3_SMW_DIN3_MASK           (0xFFFFFFFFU)
26242 #define FMUTEST_SMW_DIN3_SMW_DIN3_SHIFT          (0U)
26243 /*! SMW_DIN3 - SMW DIN 3 */
26244 #define FMUTEST_SMW_DIN3_SMW_DIN3(x)             (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_DIN3_SMW_DIN3_SHIFT)) & FMUTEST_SMW_DIN3_SMW_DIN3_MASK)
26245 /*! @} */
26246 
26247 /*! @name SMW_ADDR - SMW Address Register */
26248 /*! @{ */
26249 
26250 #define FMUTEST_SMW_ADDR_SMW_ADDR_MASK           (0xFFFFFFFFU)
26251 #define FMUTEST_SMW_ADDR_SMW_ADDR_SHIFT          (0U)
26252 /*! SMW_ADDR - SMW Address */
26253 #define FMUTEST_SMW_ADDR_SMW_ADDR(x)             (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_ADDR_SMW_ADDR_SHIFT)) & FMUTEST_SMW_ADDR_SMW_ADDR_MASK)
26254 /*! @} */
26255 
26256 /*! @name SMW_CMD_WAIT - SMW Command and Wait Register */
26257 /*! @{ */
26258 
26259 #define FMUTEST_SMW_CMD_WAIT_CMD_MASK            (0x7U)
26260 #define FMUTEST_SMW_CMD_WAIT_CMD_SHIFT           (0U)
26261 /*! CMD - SMW Command
26262  *  0b000..IDLE
26263  *  0b001..ABORT
26264  *  0b010..SME2 to one-shot mass erase
26265  *  0b011..SME3 to sector erase on selected array
26266  *  0b100..SMP1 to program phrase or page on selected array with shot disabled on previously programmed bit
26267  *  0b101..Reserved for SME4 (multi-sector erase)
26268  *  0b110..SMP2 to program phrase or page on selected array to repair cells of weak program after power loss
26269  *  0b111..Reserved
26270  */
26271 #define FMUTEST_SMW_CMD_WAIT_CMD(x)              (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_CMD_WAIT_CMD_SHIFT)) & FMUTEST_SMW_CMD_WAIT_CMD_MASK)
26272 
26273 #define FMUTEST_SMW_CMD_WAIT_WAIT_EN_MASK        (0x8U)
26274 #define FMUTEST_SMW_CMD_WAIT_WAIT_EN_SHIFT       (3U)
26275 /*! WAIT_EN - SMW Wait Enable
26276  *  0b0..Wait feature disabled
26277  *  0b1..Wait feature enabled
26278  */
26279 #define FMUTEST_SMW_CMD_WAIT_WAIT_EN(x)          (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_CMD_WAIT_WAIT_EN_SHIFT)) & FMUTEST_SMW_CMD_WAIT_WAIT_EN_MASK)
26280 
26281 #define FMUTEST_SMW_CMD_WAIT_WAIT_AUTO_SET_MASK  (0x10U)
26282 #define FMUTEST_SMW_CMD_WAIT_WAIT_AUTO_SET_SHIFT (4U)
26283 /*! WAIT_AUTO_SET - SMW Wait Auto Set */
26284 #define FMUTEST_SMW_CMD_WAIT_WAIT_AUTO_SET(x)    (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_CMD_WAIT_WAIT_AUTO_SET_SHIFT)) & FMUTEST_SMW_CMD_WAIT_WAIT_AUTO_SET_MASK)
26285 /*! @} */
26286 
26287 /*! @name SMW_STATUS - SMW Status Register */
26288 /*! @{ */
26289 
26290 #define FMUTEST_SMW_STATUS_SMW_ERR_MASK          (0x1U)
26291 #define FMUTEST_SMW_STATUS_SMW_ERR_SHIFT         (0U)
26292 /*! SMW_ERR - SMW Error
26293  *  0b0..Error not detected
26294  *  0b1..Error detected
26295  */
26296 #define FMUTEST_SMW_STATUS_SMW_ERR(x)            (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_STATUS_SMW_ERR_SHIFT)) & FMUTEST_SMW_STATUS_SMW_ERR_MASK)
26297 
26298 #define FMUTEST_SMW_STATUS_SMW_BUSY_MASK         (0x2U)
26299 #define FMUTEST_SMW_STATUS_SMW_BUSY_SHIFT        (1U)
26300 /*! SMW_BUSY - SMW Busy
26301  *  0b0..SMW command not active
26302  *  0b1..SMW command is active
26303  */
26304 #define FMUTEST_SMW_STATUS_SMW_BUSY(x)           (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_STATUS_SMW_BUSY_SHIFT)) & FMUTEST_SMW_STATUS_SMW_BUSY_MASK)
26305 
26306 #define FMUTEST_SMW_STATUS_BIST_BUSY_MASK        (0x4U)
26307 #define FMUTEST_SMW_STATUS_BIST_BUSY_SHIFT       (2U)
26308 /*! BIST_BUSY - BIST Busy
26309  *  0b0..BIST Command not active
26310  *  0b1..BIST Command is active
26311  */
26312 #define FMUTEST_SMW_STATUS_BIST_BUSY(x)          (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_STATUS_BIST_BUSY_SHIFT)) & FMUTEST_SMW_STATUS_BIST_BUSY_MASK)
26313 /*! @} */
26314 
26315 /*! @name SOCTRIM0_0 - SoC Trim Phrase 0 Word 0 Register */
26316 /*! @{ */
26317 
26318 #define FMUTEST_SOCTRIM0_0_TRIM0_0_MASK          (0xFFFFFFFFU)
26319 #define FMUTEST_SOCTRIM0_0_TRIM0_0_SHIFT         (0U)
26320 /*! TRIM0_0 - TRIM0_0 */
26321 #define FMUTEST_SOCTRIM0_0_TRIM0_0(x)            (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM0_0_TRIM0_0_SHIFT)) & FMUTEST_SOCTRIM0_0_TRIM0_0_MASK)
26322 /*! @} */
26323 
26324 /*! @name SOCTRIM0_1 - SoC Trim Phrase 0 Word 1 Register */
26325 /*! @{ */
26326 
26327 #define FMUTEST_SOCTRIM0_1_TRIM0_1_MASK          (0xFFFFFFFFU)
26328 #define FMUTEST_SOCTRIM0_1_TRIM0_1_SHIFT         (0U)
26329 /*! TRIM0_1 - TRIM0_1 */
26330 #define FMUTEST_SOCTRIM0_1_TRIM0_1(x)            (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM0_1_TRIM0_1_SHIFT)) & FMUTEST_SOCTRIM0_1_TRIM0_1_MASK)
26331 /*! @} */
26332 
26333 /*! @name SOCTRIM0_2 - SoC Trim Phrase 0 Word 2 Register */
26334 /*! @{ */
26335 
26336 #define FMUTEST_SOCTRIM0_2_TRIM0_2_MASK          (0xFFFFFFFFU)
26337 #define FMUTEST_SOCTRIM0_2_TRIM0_2_SHIFT         (0U)
26338 /*! TRIM0_2 - TRIM0_2 */
26339 #define FMUTEST_SOCTRIM0_2_TRIM0_2(x)            (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM0_2_TRIM0_2_SHIFT)) & FMUTEST_SOCTRIM0_2_TRIM0_2_MASK)
26340 /*! @} */
26341 
26342 /*! @name SOCTRIM0_3 - SoC Trim Phrase 0 Word 3 Register */
26343 /*! @{ */
26344 
26345 #define FMUTEST_SOCTRIM0_3_TRIM0_3_MASK          (0xFFFFFFFFU)
26346 #define FMUTEST_SOCTRIM0_3_TRIM0_3_SHIFT         (0U)
26347 /*! TRIM0_3 - TRIM0_3 */
26348 #define FMUTEST_SOCTRIM0_3_TRIM0_3(x)            (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM0_3_TRIM0_3_SHIFT)) & FMUTEST_SOCTRIM0_3_TRIM0_3_MASK)
26349 /*! @} */
26350 
26351 /*! @name SOCTRIM1_0 - SoC Trim Phrase 1 Word 0 Register */
26352 /*! @{ */
26353 
26354 #define FMUTEST_SOCTRIM1_0_TRIM1_0_MASK          (0xFFFFFFFFU)
26355 #define FMUTEST_SOCTRIM1_0_TRIM1_0_SHIFT         (0U)
26356 /*! TRIM1_0 - TRIM1_0 */
26357 #define FMUTEST_SOCTRIM1_0_TRIM1_0(x)            (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM1_0_TRIM1_0_SHIFT)) & FMUTEST_SOCTRIM1_0_TRIM1_0_MASK)
26358 /*! @} */
26359 
26360 /*! @name SOCTRIM1_1 - SoC Trim Phrase 1 Word 1 Register */
26361 /*! @{ */
26362 
26363 #define FMUTEST_SOCTRIM1_1_TRIM1_1_MASK          (0xFFFFFFFFU)
26364 #define FMUTEST_SOCTRIM1_1_TRIM1_1_SHIFT         (0U)
26365 /*! TRIM1_1 - TRIM1_1 */
26366 #define FMUTEST_SOCTRIM1_1_TRIM1_1(x)            (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM1_1_TRIM1_1_SHIFT)) & FMUTEST_SOCTRIM1_1_TRIM1_1_MASK)
26367 /*! @} */
26368 
26369 /*! @name SOCTRIM1_2 - SoC Trim Phrase 1 Word 2 Register */
26370 /*! @{ */
26371 
26372 #define FMUTEST_SOCTRIM1_2_TRIM1_2_MASK          (0xFFFFFFFFU)
26373 #define FMUTEST_SOCTRIM1_2_TRIM1_2_SHIFT         (0U)
26374 /*! TRIM1_2 - TRIM1_2 */
26375 #define FMUTEST_SOCTRIM1_2_TRIM1_2(x)            (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM1_2_TRIM1_2_SHIFT)) & FMUTEST_SOCTRIM1_2_TRIM1_2_MASK)
26376 /*! @} */
26377 
26378 /*! @name SOCTRIM1_3 - SoC Trim Phrase 1 Word 3 Register */
26379 /*! @{ */
26380 
26381 #define FMUTEST_SOCTRIM1_3_TRIM1_3_MASK          (0xFFFFFFFFU)
26382 #define FMUTEST_SOCTRIM1_3_TRIM1_3_SHIFT         (0U)
26383 /*! TRIM1_3 - TRIM1_3 */
26384 #define FMUTEST_SOCTRIM1_3_TRIM1_3(x)            (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM1_3_TRIM1_3_SHIFT)) & FMUTEST_SOCTRIM1_3_TRIM1_3_MASK)
26385 /*! @} */
26386 
26387 /*! @name SOCTRIM2_0 - SoC Trim Phrase 2 Word 0 Register */
26388 /*! @{ */
26389 
26390 #define FMUTEST_SOCTRIM2_0_TRIM2_0_MASK          (0xFFFFFFFFU)
26391 #define FMUTEST_SOCTRIM2_0_TRIM2_0_SHIFT         (0U)
26392 /*! TRIM2_0 - TRIM2_0 */
26393 #define FMUTEST_SOCTRIM2_0_TRIM2_0(x)            (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM2_0_TRIM2_0_SHIFT)) & FMUTEST_SOCTRIM2_0_TRIM2_0_MASK)
26394 /*! @} */
26395 
26396 /*! @name SOCTRIM2_1 - SoC Trim Phrase 2 Word 1 Register */
26397 /*! @{ */
26398 
26399 #define FMUTEST_SOCTRIM2_1_TRIM2_1_MASK          (0xFFFFFFFFU)
26400 #define FMUTEST_SOCTRIM2_1_TRIM2_1_SHIFT         (0U)
26401 /*! TRIM2_1 - TRIM2_1 */
26402 #define FMUTEST_SOCTRIM2_1_TRIM2_1(x)            (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM2_1_TRIM2_1_SHIFT)) & FMUTEST_SOCTRIM2_1_TRIM2_1_MASK)
26403 /*! @} */
26404 
26405 /*! @name SOCTRIM2_2 - SoC Trim Phrase 2 Word 2 Register */
26406 /*! @{ */
26407 
26408 #define FMUTEST_SOCTRIM2_2_TRIM2_2_MASK          (0xFFFFFFFFU)
26409 #define FMUTEST_SOCTRIM2_2_TRIM2_2_SHIFT         (0U)
26410 /*! TRIM2_2 - TRIM2_2 */
26411 #define FMUTEST_SOCTRIM2_2_TRIM2_2(x)            (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM2_2_TRIM2_2_SHIFT)) & FMUTEST_SOCTRIM2_2_TRIM2_2_MASK)
26412 /*! @} */
26413 
26414 /*! @name SOCTRIM2_3 - SoC Trim Phrase 2 Word 3 Register */
26415 /*! @{ */
26416 
26417 #define FMUTEST_SOCTRIM2_3_TRIM2_3_MASK          (0xFFFFFFFFU)
26418 #define FMUTEST_SOCTRIM2_3_TRIM2_3_SHIFT         (0U)
26419 /*! TRIM2_3 - TRIM2_3 */
26420 #define FMUTEST_SOCTRIM2_3_TRIM2_3(x)            (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM2_3_TRIM2_3_SHIFT)) & FMUTEST_SOCTRIM2_3_TRIM2_3_MASK)
26421 /*! @} */
26422 
26423 /*! @name SOCTRIM3_0 - SoC Trim Phrase 3 Word 0 Register */
26424 /*! @{ */
26425 
26426 #define FMUTEST_SOCTRIM3_0_TRIM3_0_MASK          (0xFFFFFFFFU)
26427 #define FMUTEST_SOCTRIM3_0_TRIM3_0_SHIFT         (0U)
26428 /*! TRIM3_0 - TRIM3_0 */
26429 #define FMUTEST_SOCTRIM3_0_TRIM3_0(x)            (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM3_0_TRIM3_0_SHIFT)) & FMUTEST_SOCTRIM3_0_TRIM3_0_MASK)
26430 /*! @} */
26431 
26432 /*! @name SOCTRIM3_1 - SoC Trim Phrase 3 Word 1 Register */
26433 /*! @{ */
26434 
26435 #define FMUTEST_SOCTRIM3_1_TRIM3_1_MASK          (0xFFFFFFFFU)
26436 #define FMUTEST_SOCTRIM3_1_TRIM3_1_SHIFT         (0U)
26437 /*! TRIM3_1 - TRIM3_1 */
26438 #define FMUTEST_SOCTRIM3_1_TRIM3_1(x)            (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM3_1_TRIM3_1_SHIFT)) & FMUTEST_SOCTRIM3_1_TRIM3_1_MASK)
26439 /*! @} */
26440 
26441 /*! @name SOCTRIM3_2 - SoC Trim Phrase 3 Word 2 Register */
26442 /*! @{ */
26443 
26444 #define FMUTEST_SOCTRIM3_2_TRIM3_2_MASK          (0xFFFFFFFFU)
26445 #define FMUTEST_SOCTRIM3_2_TRIM3_2_SHIFT         (0U)
26446 /*! TRIM3_2 - TRIM3_2 */
26447 #define FMUTEST_SOCTRIM3_2_TRIM3_2(x)            (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM3_2_TRIM3_2_SHIFT)) & FMUTEST_SOCTRIM3_2_TRIM3_2_MASK)
26448 /*! @} */
26449 
26450 /*! @name SOCTRIM3_3 - SoC Trim Phrase 3 Word 3 Register */
26451 /*! @{ */
26452 
26453 #define FMUTEST_SOCTRIM3_3_TRIM3_3_MASK          (0xFFFFFFFFU)
26454 #define FMUTEST_SOCTRIM3_3_TRIM3_3_SHIFT         (0U)
26455 /*! TRIM3_3 - TRIM3_3 */
26456 #define FMUTEST_SOCTRIM3_3_TRIM3_3(x)            (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM3_3_TRIM3_3_SHIFT)) & FMUTEST_SOCTRIM3_3_TRIM3_3_MASK)
26457 /*! @} */
26458 
26459 /*! @name SOCTRIM4_0 - SoC Trim Phrase 4 Word 0 Register */
26460 /*! @{ */
26461 
26462 #define FMUTEST_SOCTRIM4_0_TRIM4_0_MASK          (0xFFFFFFFFU)
26463 #define FMUTEST_SOCTRIM4_0_TRIM4_0_SHIFT         (0U)
26464 /*! TRIM4_0 - TRIM4_0 */
26465 #define FMUTEST_SOCTRIM4_0_TRIM4_0(x)            (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM4_0_TRIM4_0_SHIFT)) & FMUTEST_SOCTRIM4_0_TRIM4_0_MASK)
26466 /*! @} */
26467 
26468 /*! @name SOCTRIM4_1 - SoC Trim Phrase 4 Word 1 Register */
26469 /*! @{ */
26470 
26471 #define FMUTEST_SOCTRIM4_1_TRIM4_1_MASK          (0xFFFFFFFFU)
26472 #define FMUTEST_SOCTRIM4_1_TRIM4_1_SHIFT         (0U)
26473 /*! TRIM4_1 - TRIM4_1 */
26474 #define FMUTEST_SOCTRIM4_1_TRIM4_1(x)            (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM4_1_TRIM4_1_SHIFT)) & FMUTEST_SOCTRIM4_1_TRIM4_1_MASK)
26475 /*! @} */
26476 
26477 /*! @name SOCTRIM4_2 - SoC Trim Phrase 4 Word 2 Register */
26478 /*! @{ */
26479 
26480 #define FMUTEST_SOCTRIM4_2_TRIM4_2_MASK          (0xFFFFFFFFU)
26481 #define FMUTEST_SOCTRIM4_2_TRIM4_2_SHIFT         (0U)
26482 /*! TRIM4_2 - TRIM4_2 */
26483 #define FMUTEST_SOCTRIM4_2_TRIM4_2(x)            (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM4_2_TRIM4_2_SHIFT)) & FMUTEST_SOCTRIM4_2_TRIM4_2_MASK)
26484 /*! @} */
26485 
26486 /*! @name SOCTRIM4_3 - SoC Trim Phrase 4 Word 3 Register */
26487 /*! @{ */
26488 
26489 #define FMUTEST_SOCTRIM4_3_TRIM4_3_MASK          (0xFFFFFFFFU)
26490 #define FMUTEST_SOCTRIM4_3_TRIM4_3_SHIFT         (0U)
26491 /*! TRIM4_3 - TRIM4_3 */
26492 #define FMUTEST_SOCTRIM4_3_TRIM4_3(x)            (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM4_3_TRIM4_3_SHIFT)) & FMUTEST_SOCTRIM4_3_TRIM4_3_MASK)
26493 /*! @} */
26494 
26495 /*! @name SOCTRIM5_0 - SoC Trim Phrase 5 Word 0 Register */
26496 /*! @{ */
26497 
26498 #define FMUTEST_SOCTRIM5_0_TRIM5_0_MASK          (0xFFFFFFFFU)
26499 #define FMUTEST_SOCTRIM5_0_TRIM5_0_SHIFT         (0U)
26500 /*! TRIM5_0 - TRIM5_0 */
26501 #define FMUTEST_SOCTRIM5_0_TRIM5_0(x)            (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM5_0_TRIM5_0_SHIFT)) & FMUTEST_SOCTRIM5_0_TRIM5_0_MASK)
26502 /*! @} */
26503 
26504 /*! @name SOCTRIM5_1 - SoC Trim Phrase 5 Word 1 Register */
26505 /*! @{ */
26506 
26507 #define FMUTEST_SOCTRIM5_1_TRIM5_1_MASK          (0xFFFFFFFFU)
26508 #define FMUTEST_SOCTRIM5_1_TRIM5_1_SHIFT         (0U)
26509 /*! TRIM5_1 - TRIM5_1 */
26510 #define FMUTEST_SOCTRIM5_1_TRIM5_1(x)            (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM5_1_TRIM5_1_SHIFT)) & FMUTEST_SOCTRIM5_1_TRIM5_1_MASK)
26511 /*! @} */
26512 
26513 /*! @name SOCTRIM5_2 - SoC Trim Phrase 5 Word 2 Register */
26514 /*! @{ */
26515 
26516 #define FMUTEST_SOCTRIM5_2_TRIM5_2_MASK          (0xFFFFFFFFU)
26517 #define FMUTEST_SOCTRIM5_2_TRIM5_2_SHIFT         (0U)
26518 /*! TRIM5_2 - TRIM5_2 */
26519 #define FMUTEST_SOCTRIM5_2_TRIM5_2(x)            (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM5_2_TRIM5_2_SHIFT)) & FMUTEST_SOCTRIM5_2_TRIM5_2_MASK)
26520 /*! @} */
26521 
26522 /*! @name SOCTRIM5_3 - SoC Trim Phrase 5 Word 3 Register */
26523 /*! @{ */
26524 
26525 #define FMUTEST_SOCTRIM5_3_TRIM5_3_MASK          (0xFFFFFFFFU)
26526 #define FMUTEST_SOCTRIM5_3_TRIM5_3_SHIFT         (0U)
26527 /*! TRIM5_3 - TRIM5_3 */
26528 #define FMUTEST_SOCTRIM5_3_TRIM5_3(x)            (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM5_3_TRIM5_3_SHIFT)) & FMUTEST_SOCTRIM5_3_TRIM5_3_MASK)
26529 /*! @} */
26530 
26531 /*! @name SOCTRIM6_0 - SoC Trim Phrase 6 Word 0 Register */
26532 /*! @{ */
26533 
26534 #define FMUTEST_SOCTRIM6_0_TRIM6_0_MASK          (0xFFFFFFFFU)
26535 #define FMUTEST_SOCTRIM6_0_TRIM6_0_SHIFT         (0U)
26536 /*! TRIM6_0 - TRIM6_0 */
26537 #define FMUTEST_SOCTRIM6_0_TRIM6_0(x)            (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM6_0_TRIM6_0_SHIFT)) & FMUTEST_SOCTRIM6_0_TRIM6_0_MASK)
26538 /*! @} */
26539 
26540 /*! @name SOCTRIM6_1 - SoC Trim Phrase 6 Word 1 Register */
26541 /*! @{ */
26542 
26543 #define FMUTEST_SOCTRIM6_1_TRIM6_1_MASK          (0xFFFFFFFFU)
26544 #define FMUTEST_SOCTRIM6_1_TRIM6_1_SHIFT         (0U)
26545 /*! TRIM6_1 - TRIM6_1 */
26546 #define FMUTEST_SOCTRIM6_1_TRIM6_1(x)            (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM6_1_TRIM6_1_SHIFT)) & FMUTEST_SOCTRIM6_1_TRIM6_1_MASK)
26547 /*! @} */
26548 
26549 /*! @name SOCTRIM6_2 - SoC Trim Phrase 6 Word 2 Register */
26550 /*! @{ */
26551 
26552 #define FMUTEST_SOCTRIM6_2_TRIM6_2_MASK          (0xFFFFFFFFU)
26553 #define FMUTEST_SOCTRIM6_2_TRIM6_2_SHIFT         (0U)
26554 /*! TRIM6_2 - TRIM6_2 */
26555 #define FMUTEST_SOCTRIM6_2_TRIM6_2(x)            (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM6_2_TRIM6_2_SHIFT)) & FMUTEST_SOCTRIM6_2_TRIM6_2_MASK)
26556 /*! @} */
26557 
26558 /*! @name SOCTRIM6_3 - SoC Trim Phrase 6 Word 3 Register */
26559 /*! @{ */
26560 
26561 #define FMUTEST_SOCTRIM6_3_TRIM6_3_MASK          (0xFFFFFFFFU)
26562 #define FMUTEST_SOCTRIM6_3_TRIM6_3_SHIFT         (0U)
26563 /*! TRIM6_3 - TRIM6_3 */
26564 #define FMUTEST_SOCTRIM6_3_TRIM6_3(x)            (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM6_3_TRIM6_3_SHIFT)) & FMUTEST_SOCTRIM6_3_TRIM6_3_MASK)
26565 /*! @} */
26566 
26567 /*! @name SOCTRIM7_0 - SoC Trim Phrase 7 Word 0 Register */
26568 /*! @{ */
26569 
26570 #define FMUTEST_SOCTRIM7_0_TRIM7_0_MASK          (0xFFFFFFFFU)
26571 #define FMUTEST_SOCTRIM7_0_TRIM7_0_SHIFT         (0U)
26572 /*! TRIM7_0 - TRIM7_0 */
26573 #define FMUTEST_SOCTRIM7_0_TRIM7_0(x)            (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM7_0_TRIM7_0_SHIFT)) & FMUTEST_SOCTRIM7_0_TRIM7_0_MASK)
26574 /*! @} */
26575 
26576 /*! @name SOCTRIM7_1 - SoC Trim Phrase 7 Word 1 Register */
26577 /*! @{ */
26578 
26579 #define FMUTEST_SOCTRIM7_1_TRIM7_1_MASK          (0xFFFFFFFFU)
26580 #define FMUTEST_SOCTRIM7_1_TRIM7_1_SHIFT         (0U)
26581 /*! TRIM7_1 - TRIM7_1 */
26582 #define FMUTEST_SOCTRIM7_1_TRIM7_1(x)            (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM7_1_TRIM7_1_SHIFT)) & FMUTEST_SOCTRIM7_1_TRIM7_1_MASK)
26583 /*! @} */
26584 
26585 /*! @name SOCTRIM7_2 - SoC Trim Phrase 7 Word 2 Register */
26586 /*! @{ */
26587 
26588 #define FMUTEST_SOCTRIM7_2_TRIM7_2_MASK          (0xFFFFFFFFU)
26589 #define FMUTEST_SOCTRIM7_2_TRIM7_2_SHIFT         (0U)
26590 /*! TRIM7_2 - TRIM7_2 */
26591 #define FMUTEST_SOCTRIM7_2_TRIM7_2(x)            (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM7_2_TRIM7_2_SHIFT)) & FMUTEST_SOCTRIM7_2_TRIM7_2_MASK)
26592 /*! @} */
26593 
26594 /*! @name SOCTRIM7_3 - SoC Trim Phrase 7 Word 3 Register */
26595 /*! @{ */
26596 
26597 #define FMUTEST_SOCTRIM7_3_TRIM7_3_MASK          (0xFFFFFFFFU)
26598 #define FMUTEST_SOCTRIM7_3_TRIM7_3_SHIFT         (0U)
26599 /*! TRIM7_3 - TRIM7_3 */
26600 #define FMUTEST_SOCTRIM7_3_TRIM7_3(x)            (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM7_3_TRIM7_3_SHIFT)) & FMUTEST_SOCTRIM7_3_TRIM7_3_MASK)
26601 /*! @} */
26602 
26603 /*! @name R_IP_CONFIG - BIST Configuration Register */
26604 /*! @{ */
26605 
26606 #define FMUTEST_R_IP_CONFIG_IPSEL0_MASK          (0x3U)
26607 #define FMUTEST_R_IP_CONFIG_IPSEL0_SHIFT         (0U)
26608 /*! IPSEL0 - Block 0 Select Control
26609  *  0b00..Unselect block 0
26610  *  0b01..not used, reserved
26611  *  0b10..Enable block 0 test, repair off (default)
26612  *  0b11..Enable block 0 test, repair on
26613  */
26614 #define FMUTEST_R_IP_CONFIG_IPSEL0(x)            (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_IP_CONFIG_IPSEL0_SHIFT)) & FMUTEST_R_IP_CONFIG_IPSEL0_MASK)
26615 
26616 #define FMUTEST_R_IP_CONFIG_IPSEL1_MASK          (0xCU)
26617 #define FMUTEST_R_IP_CONFIG_IPSEL1_SHIFT         (2U)
26618 /*! IPSEL1 - Block 1 Select Control
26619  *  0b00..Unselect block 1
26620  *  0b01..not used, reserved
26621  *  0b10..Enable block 1 test, repair off (default)
26622  *  0b11..Enable block 1 test, repair on
26623  */
26624 #define FMUTEST_R_IP_CONFIG_IPSEL1(x)            (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_IP_CONFIG_IPSEL1_SHIFT)) & FMUTEST_R_IP_CONFIG_IPSEL1_MASK)
26625 
26626 #define FMUTEST_R_IP_CONFIG_BIST_CDIVL_MASK      (0xFF0U)
26627 #define FMUTEST_R_IP_CONFIG_BIST_CDIVL_SHIFT     (4U)
26628 /*! BIST_CDIVL - Clock Divide Scalar for Long Pulse */
26629 #define FMUTEST_R_IP_CONFIG_BIST_CDIVL(x)        (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_IP_CONFIG_BIST_CDIVL_SHIFT)) & FMUTEST_R_IP_CONFIG_BIST_CDIVL_MASK)
26630 
26631 #define FMUTEST_R_IP_CONFIG_CDIVS_MASK           (0x7000U)
26632 #define FMUTEST_R_IP_CONFIG_CDIVS_SHIFT          (12U)
26633 /*! CDIVS - Number of clock cycles to generate short pulse */
26634 #define FMUTEST_R_IP_CONFIG_CDIVS(x)             (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_IP_CONFIG_CDIVS_SHIFT)) & FMUTEST_R_IP_CONFIG_CDIVS_MASK)
26635 
26636 #define FMUTEST_R_IP_CONFIG_BIST_TVFY_MASK       (0xF8000U)
26637 #define FMUTEST_R_IP_CONFIG_BIST_TVFY_SHIFT      (15U)
26638 /*! BIST_TVFY - Timer adjust for verify */
26639 #define FMUTEST_R_IP_CONFIG_BIST_TVFY(x)         (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_IP_CONFIG_BIST_TVFY_SHIFT)) & FMUTEST_R_IP_CONFIG_BIST_TVFY_MASK)
26640 
26641 #define FMUTEST_R_IP_CONFIG_TSTCTL_MASK          (0x300000U)
26642 #define FMUTEST_R_IP_CONFIG_TSTCTL_SHIFT         (20U)
26643 /*! TSTCTL - BIST self-test control
26644  *  0b00..Default, disable both BIST self-test and MISR
26645  *  0b01..Enable BIST self-test mode DOUT from macro will be forced to '0', and disable MISR.
26646  *  0b10..Enable MISR
26647  *  0b11..Enable both BIST self-test mode and MISR
26648  */
26649 #define FMUTEST_R_IP_CONFIG_TSTCTL(x)            (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_IP_CONFIG_TSTCTL_SHIFT)) & FMUTEST_R_IP_CONFIG_TSTCTL_MASK)
26650 
26651 #define FMUTEST_R_IP_CONFIG_DBGCTL_MASK          (0x400000U)
26652 #define FMUTEST_R_IP_CONFIG_DBGCTL_SHIFT         (22U)
26653 /*! DBGCTL - Debug feature control
26654  *  0b0..Default
26655  *  0b1..Enable debug feature to collect failure address and data.
26656  */
26657 #define FMUTEST_R_IP_CONFIG_DBGCTL(x)            (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_IP_CONFIG_DBGCTL_SHIFT)) & FMUTEST_R_IP_CONFIG_DBGCTL_MASK)
26658 
26659 #define FMUTEST_R_IP_CONFIG_BIST_CLK_SEL_MASK    (0x800000U)
26660 #define FMUTEST_R_IP_CONFIG_BIST_CLK_SEL_SHIFT   (23U)
26661 /*! BIST_CLK_SEL - BIST Clock Select */
26662 #define FMUTEST_R_IP_CONFIG_BIST_CLK_SEL(x)      (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_IP_CONFIG_BIST_CLK_SEL_SHIFT)) & FMUTEST_R_IP_CONFIG_BIST_CLK_SEL_MASK)
26663 
26664 #define FMUTEST_R_IP_CONFIG_SMWTST_MASK          (0x3000000U)
26665 #define FMUTEST_R_IP_CONFIG_SMWTST_SHIFT         (24U)
26666 /*! SMWTST - SMWR DOUT Function Control
26667  *  0b00..Default
26668  *  0b01..Enable SMWR self-test mode, DOUT from macro will be forced to all 0
26669  *  0b10..Enable SMWR self-test mode, DOUT from macro will be forced to all 1
26670  *  0b11..Reserved (unused)
26671  */
26672 #define FMUTEST_R_IP_CONFIG_SMWTST(x)            (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_IP_CONFIG_SMWTST_SHIFT)) & FMUTEST_R_IP_CONFIG_SMWTST_MASK)
26673 
26674 #define FMUTEST_R_IP_CONFIG_ECCEN_MASK           (0x4000000U)
26675 #define FMUTEST_R_IP_CONFIG_ECCEN_SHIFT          (26U)
26676 /*! ECCEN - BIST ECC Control
26677  *  0b0..Default mode (no ECC encode or decode)
26678  *  0b1..Enable ECC encode/decode
26679  */
26680 #define FMUTEST_R_IP_CONFIG_ECCEN(x)             (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_IP_CONFIG_ECCEN_SHIFT)) & FMUTEST_R_IP_CONFIG_ECCEN_MASK)
26681 /*! @} */
26682 
26683 /*! @name R_TESTCODE - BIST Test Code Register */
26684 /*! @{ */
26685 
26686 #define FMUTEST_R_TESTCODE_TESTCODE_MASK         (0x3FU)
26687 #define FMUTEST_R_TESTCODE_TESTCODE_SHIFT        (0U)
26688 /*! TESTCODE - Used to store test code information before running TMR-RST/TMRSET BIST command */
26689 #define FMUTEST_R_TESTCODE_TESTCODE(x)           (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TESTCODE_TESTCODE_SHIFT)) & FMUTEST_R_TESTCODE_TESTCODE_MASK)
26690 /*! @} */
26691 
26692 /*! @name R_DFT_CTRL - BIST DFT Control Register */
26693 /*! @{ */
26694 
26695 #define FMUTEST_R_DFT_CTRL_DFT_XADR_MASK         (0xFU)
26696 #define FMUTEST_R_DFT_CTRL_DFT_XADR_SHIFT        (0U)
26697 /*! DFT_XADR - DFT XADR Pattern
26698  *  0b0000..XADR fixed, no change at all
26699  *  0b0001..XADR increased by 1 after row. For READ operation, XADR increases by 1 after reading the last word of
26700  *          row. For PROG operation, XADR increases by 1 after NVSTR falls.
26701  *  0b0010..XADR increased for diagonal. For PROG-DIAGONAL operation, XADR is increased to create diagonal pattern.
26702  *  0b0011..XADR increased by sector. During ERASE operation, XADR increased by number of rows in a sector when NVSTR falls.
26703  *  0b0100..XADR inversed. XADR is inversed after reading one word or after programming one row when NVSTR falls.
26704  *  0b0101..XADR increased by 2 after row. For READ operation, XADR is increased by 2 after reading the last word
26705  *          of a row. For PROG operation, XADR is increased by 2 when NVSTR falls.
26706  *  0b0110..XADR[0] inversed. XADR[0] is inversed after reading one word or after programming one row when NVSTR falls.
26707  *  0b0111..XADR increased by 1. For READ operations only, XADR increased by 1 after each read cycle.
26708  *  0b1000..XADR decreased by 1 after row. For READ operations only, XADR is decreased by 1 after YADR decreases to 0.
26709  *  0b1001..XADR decreased by 1. For READ operations only, XADR is decreased by 1 after each read cycle.
26710  */
26711 #define FMUTEST_R_DFT_CTRL_DFT_XADR(x)           (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DFT_CTRL_DFT_XADR_SHIFT)) & FMUTEST_R_DFT_CTRL_DFT_XADR_MASK)
26712 
26713 #define FMUTEST_R_DFT_CTRL_DFT_YADR_MASK         (0xF0U)
26714 #define FMUTEST_R_DFT_CTRL_DFT_YADR_SHIFT        (4U)
26715 /*! DFT_YADR - DFT YADR Pattern
26716  *  0b0000..YADR fixed, no change at all
26717  *  0b0001..YADR for ICKBD. For PROG and READ operations, YADR changed to generate inverse checkerboard pattern.
26718  *  0b0010..YADR for CKBD. For PROG and READ operations, YADR changed to generate checkerboard pattern.
26719  *  0b0011..YADR increased by 1. For READ operations, YADR increased by 1 after each read cycle. For PROG
26720  *          operations, YADR increased by 1 after YE falls.
26721  *  0b0100..YADR increased for diagonal. For PROG-DIAGONAL operation, YADR is increased to create diagonal pattern.
26722  *  0b0101..YADR inversed. YADR is inversed after reading one word or after programming one word when YE falls.
26723  *  0b0110..YADR[0] inversed. YADR[0] is inversed after reading one word or after programming one word when YE falls.
26724  *  0b0111..YADR increased by 1 after last row. For READ operations only, YADR is increased by 1 after XADR reaches last row.
26725  *  0b1000..YADR decreased by 1. For READ operations only, YADR is decreased by 1 after each read cycle.
26726  *  0b1001..YADR decreased by 1 after first row. For READ operations only, YADR is decreased by 1 after XADR decreases to 0.
26727  */
26728 #define FMUTEST_R_DFT_CTRL_DFT_YADR(x)           (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DFT_CTRL_DFT_YADR_SHIFT)) & FMUTEST_R_DFT_CTRL_DFT_YADR_MASK)
26729 
26730 #define FMUTEST_R_DFT_CTRL_DFT_DATA_MASK         (0xF00U)
26731 #define FMUTEST_R_DFT_CTRL_DFT_DATA_SHIFT        (8U)
26732 /*! DFT_DATA - DFT Data Pattern
26733  *  0b0000..CKBD pattern. For READ operations only, compare DOUT with checkerboard data pattern for each read cycle.
26734  *  0b0001..ICKBD pattern. For READ operations only, compare DOUT with inverse checkerboard data pattern for each read cycle.
26735  *  0b0010..Diagonal pattern. Used for READ operations only, compare DOUT to diagonal pattern.
26736  *  0b0011..Fixed data pattern. For READ operations, comparison to DOUT for selected groups; refer to
26737  *          R_ADR_CTRL[GRPSEL] for modules with multiple groups.
26738  *  0b0100..Random data pattern which will be generated based on the initial seed set in R_DATA; for READ
26739  *          operations, used for DOUT comparison of selected groups. For PROG operations, used to control DIN of selected
26740  *          groups.
26741  *  0b0101..DOUT based pattern. For READ operations only, DOUT of selected group will be latched in R_DATA. If
26742  *          more than one group is selected in R_ADR_CTRL[GRPSEL], the group with the lower index will be latched.
26743  *  0b0110..R_DATA based pattern. For READ operations, expected DOUT value of selected groups equals to R_DATA
26744  *          when XADR[0]==YADR[0] or ~R_DATA when XADR[0]!=YADR[0]. For PROG operations, DIN of selected groups equals
26745  *          R_DATA when XADR[0]==YADR[0] or ~R_DATA when XADR[0]!=YADR[0].
26746  *  0b0111..SCAN-IO pattern. For READ operations, control expected DOUT value of selected groups to SCAN-IO data
26747  *          pattern. For PROG operations, control DIN of selected groups to SCAN-IO data pattern.
26748  *  0b1000..REPAIR set. For PROG operation to IFR1(7,1) and IFR1(7,2), R_REPAIR0_0 and R_REPAIR0_1 or R_REPAIR1_0
26749  *          and R_REPAIR1_1 will control DIN. For READ operation on IFR1(7,1) and IFR1(7,2), DOUT will be compared
26750  *          against R_REPAIR0_0 and R_REPAIR0_1 or R_REPAIR1_0 andR_REPAIR1_1. When this option is selected, only
26751  *          one flash block can be selected.
26752  *  0b1001..REPAIR load. For READ operation only, DOUT from IFR1(7,1) and IFR1(7,2) is loaded to R_REPAIR0 and R_REPAIR1.
26753  */
26754 #define FMUTEST_R_DFT_CTRL_DFT_DATA(x)           (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DFT_CTRL_DFT_DATA_SHIFT)) & FMUTEST_R_DFT_CTRL_DFT_DATA_MASK)
26755 
26756 #define FMUTEST_R_DFT_CTRL_CMP_MASK_MASK         (0x3000U)
26757 #define FMUTEST_R_DFT_CTRL_CMP_MASK_SHIFT        (12U)
26758 /*! CMP_MASK - Data Compare Mask
26759  *  0b00..Expected data is compared to DOUT
26760  *  0b01..Expected data (only 0s are considered) are compared to DOUT
26761  *  0b10..Expected data (only 1s are considered) are compared to DOUT
26762  */
26763 #define FMUTEST_R_DFT_CTRL_CMP_MASK(x)           (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DFT_CTRL_CMP_MASK_SHIFT)) & FMUTEST_R_DFT_CTRL_CMP_MASK_MASK)
26764 
26765 #define FMUTEST_R_DFT_CTRL_DFT_DATA_SRC_MASK     (0x4000U)
26766 #define FMUTEST_R_DFT_CTRL_DFT_DATA_SRC_SHIFT    (14U)
26767 /*! DFT_DATA_SRC - DFT Data Source
26768  *  0b0..{R_DATA_CTRL0,R_DATA_CTRL_EX[2:0],R_DATA_CTRL0,R_DATA_CTRL_EX[2:0],R_DATA_CTRL0,R_DATA_CTRL_EX[2:0],R_DATA_CTRL0} is used
26769  *  0b1..{R_DATA_CTRL3,R_DATA_CTRL2_EX[2:0],R_DATA_CTRL2,R_DATA_CTRL1_EX[2:0],R_DATA_CTRL1,R_DATA_CTRL_EX[2:0],R_DATA_CTRL0} is used
26770  */
26771 #define FMUTEST_R_DFT_CTRL_DFT_DATA_SRC(x)       (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DFT_CTRL_DFT_DATA_SRC_SHIFT)) & FMUTEST_R_DFT_CTRL_DFT_DATA_SRC_MASK)
26772 /*! @} */
26773 
26774 /*! @name R_ADR_CTRL - BIST Address Control Register */
26775 /*! @{ */
26776 
26777 #define FMUTEST_R_ADR_CTRL_GRPSEL_MASK           (0xFU)
26778 #define FMUTEST_R_ADR_CTRL_GRPSEL_SHIFT          (0U)
26779 /*! GRPSEL - Data Group Select
26780  *  0b0000..Select no data
26781  *  0b0001..Select data slice [34:0]
26782  *  0b0010..Select data slice [69:35]
26783  *  0b0100..Select data slice [104:70]
26784  *  0b1000..Select data slice [136:105]
26785  *  0b1111..Select data [136:0]
26786  */
26787 #define FMUTEST_R_ADR_CTRL_GRPSEL(x)             (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_ADR_CTRL_GRPSEL_SHIFT)) & FMUTEST_R_ADR_CTRL_GRPSEL_MASK)
26788 
26789 #define FMUTEST_R_ADR_CTRL_XADR_MASK             (0xFFF0U)
26790 #define FMUTEST_R_ADR_CTRL_XADR_SHIFT            (4U)
26791 /*! XADR - BIST XADR */
26792 #define FMUTEST_R_ADR_CTRL_XADR(x)               (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_ADR_CTRL_XADR_SHIFT)) & FMUTEST_R_ADR_CTRL_XADR_MASK)
26793 
26794 #define FMUTEST_R_ADR_CTRL_YADR_MASK             (0x1F0000U)
26795 #define FMUTEST_R_ADR_CTRL_YADR_SHIFT            (16U)
26796 /*! YADR - BIST YADR */
26797 #define FMUTEST_R_ADR_CTRL_YADR(x)               (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_ADR_CTRL_YADR_SHIFT)) & FMUTEST_R_ADR_CTRL_YADR_MASK)
26798 
26799 #define FMUTEST_R_ADR_CTRL_PROG_ATTR_MASK        (0xE00000U)
26800 #define FMUTEST_R_ADR_CTRL_PROG_ATTR_SHIFT       (21U)
26801 /*! PROG_ATTR - Program Attribute
26802  *  0b000..One YE pulse will program one data slice group
26803  *  0b001..One YE pulse will program two data slice groups
26804  *  0b010..One YE pulse will program three data slice groups (reserved)
26805  *  0b011..One YE pulse will program four data slice groups
26806  *  0b100..One YE pulse will program five data slice groups (reserved)
26807  *  0b101..One YE pulse will program six data slice groups (reserved)
26808  *  0b110..One YE pulse will program seven data slice groups (reserved)
26809  *  0b111..One YE pulse will program eight data slice groups (reserved)
26810  */
26811 #define FMUTEST_R_ADR_CTRL_PROG_ATTR(x)          (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_ADR_CTRL_PROG_ATTR_SHIFT)) & FMUTEST_R_ADR_CTRL_PROG_ATTR_MASK)
26812 /*! @} */
26813 
26814 /*! @name R_DATA_CTRL0 - BIST Data Control 0 Register */
26815 /*! @{ */
26816 
26817 #define FMUTEST_R_DATA_CTRL0_DATA0_MASK          (0xFFFFFFFFU)
26818 #define FMUTEST_R_DATA_CTRL0_DATA0_SHIFT         (0U)
26819 /*! DATA0 - BIST Data 0 Low */
26820 #define FMUTEST_R_DATA_CTRL0_DATA0(x)            (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DATA_CTRL0_DATA0_SHIFT)) & FMUTEST_R_DATA_CTRL0_DATA0_MASK)
26821 /*! @} */
26822 
26823 /*! @name R_PIN_CTRL - BIST Pin Control Register */
26824 /*! @{ */
26825 
26826 #define FMUTEST_R_PIN_CTRL_MAS1_MASK             (0x1U)
26827 #define FMUTEST_R_PIN_CTRL_MAS1_SHIFT            (0U)
26828 /*! MAS1 - Mass Erase */
26829 #define FMUTEST_R_PIN_CTRL_MAS1(x)               (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_MAS1_SHIFT)) & FMUTEST_R_PIN_CTRL_MAS1_MASK)
26830 
26831 #define FMUTEST_R_PIN_CTRL_IFREN_MASK            (0x2U)
26832 #define FMUTEST_R_PIN_CTRL_IFREN_SHIFT           (1U)
26833 /*! IFREN - IFR Enable */
26834 #define FMUTEST_R_PIN_CTRL_IFREN(x)              (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_IFREN_SHIFT)) & FMUTEST_R_PIN_CTRL_IFREN_MASK)
26835 
26836 #define FMUTEST_R_PIN_CTRL_IFREN1_MASK           (0x4U)
26837 #define FMUTEST_R_PIN_CTRL_IFREN1_SHIFT          (2U)
26838 /*! IFREN1 - IFR1 Enable */
26839 #define FMUTEST_R_PIN_CTRL_IFREN1(x)             (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_IFREN1_SHIFT)) & FMUTEST_R_PIN_CTRL_IFREN1_MASK)
26840 
26841 #define FMUTEST_R_PIN_CTRL_REDEN_MASK            (0x8U)
26842 #define FMUTEST_R_PIN_CTRL_REDEN_SHIFT           (3U)
26843 /*! REDEN - Redundancy Block Enable */
26844 #define FMUTEST_R_PIN_CTRL_REDEN(x)              (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_REDEN_SHIFT)) & FMUTEST_R_PIN_CTRL_REDEN_MASK)
26845 
26846 #define FMUTEST_R_PIN_CTRL_LVE_MASK              (0x10U)
26847 #define FMUTEST_R_PIN_CTRL_LVE_SHIFT             (4U)
26848 /*! LVE - Low Voltage Enable */
26849 #define FMUTEST_R_PIN_CTRL_LVE(x)                (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_LVE_SHIFT)) & FMUTEST_R_PIN_CTRL_LVE_MASK)
26850 
26851 #define FMUTEST_R_PIN_CTRL_PV_MASK               (0x20U)
26852 #define FMUTEST_R_PIN_CTRL_PV_SHIFT              (5U)
26853 /*! PV - Program Verify Enable */
26854 #define FMUTEST_R_PIN_CTRL_PV(x)                 (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_PV_SHIFT)) & FMUTEST_R_PIN_CTRL_PV_MASK)
26855 
26856 #define FMUTEST_R_PIN_CTRL_EV_MASK               (0x40U)
26857 #define FMUTEST_R_PIN_CTRL_EV_SHIFT              (6U)
26858 /*! EV - Erase Verify Enable */
26859 #define FMUTEST_R_PIN_CTRL_EV(x)                 (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_EV_SHIFT)) & FMUTEST_R_PIN_CTRL_EV_MASK)
26860 
26861 #define FMUTEST_R_PIN_CTRL_WIPGM_MASK            (0x180U)
26862 #define FMUTEST_R_PIN_CTRL_WIPGM_SHIFT           (7U)
26863 /*! WIPGM - Program Current */
26864 #define FMUTEST_R_PIN_CTRL_WIPGM(x)              (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_WIPGM_SHIFT)) & FMUTEST_R_PIN_CTRL_WIPGM_MASK)
26865 
26866 #define FMUTEST_R_PIN_CTRL_WHV_MASK              (0x1E00U)
26867 #define FMUTEST_R_PIN_CTRL_WHV_SHIFT             (9U)
26868 /*! WHV - High Voltage Level */
26869 #define FMUTEST_R_PIN_CTRL_WHV(x)                (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_WHV_SHIFT)) & FMUTEST_R_PIN_CTRL_WHV_MASK)
26870 
26871 #define FMUTEST_R_PIN_CTRL_WMV_MASK              (0xE000U)
26872 #define FMUTEST_R_PIN_CTRL_WMV_SHIFT             (13U)
26873 /*! WMV - Medium Voltage Level */
26874 #define FMUTEST_R_PIN_CTRL_WMV(x)                (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_WMV_SHIFT)) & FMUTEST_R_PIN_CTRL_WMV_MASK)
26875 
26876 #define FMUTEST_R_PIN_CTRL_XE_MASK               (0x10000U)
26877 #define FMUTEST_R_PIN_CTRL_XE_SHIFT              (16U)
26878 /*! XE - X Address Enable */
26879 #define FMUTEST_R_PIN_CTRL_XE(x)                 (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_XE_SHIFT)) & FMUTEST_R_PIN_CTRL_XE_MASK)
26880 
26881 #define FMUTEST_R_PIN_CTRL_YE_MASK               (0x20000U)
26882 #define FMUTEST_R_PIN_CTRL_YE_SHIFT              (17U)
26883 /*! YE - Y Address Enable */
26884 #define FMUTEST_R_PIN_CTRL_YE(x)                 (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_YE_SHIFT)) & FMUTEST_R_PIN_CTRL_YE_MASK)
26885 
26886 #define FMUTEST_R_PIN_CTRL_SE_MASK               (0x40000U)
26887 #define FMUTEST_R_PIN_CTRL_SE_SHIFT              (18U)
26888 /*! SE - Sense Amp Enable */
26889 #define FMUTEST_R_PIN_CTRL_SE(x)                 (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_SE_SHIFT)) & FMUTEST_R_PIN_CTRL_SE_MASK)
26890 
26891 #define FMUTEST_R_PIN_CTRL_ERASE_MASK            (0x80000U)
26892 #define FMUTEST_R_PIN_CTRL_ERASE_SHIFT           (19U)
26893 /*! ERASE - Erase Mode */
26894 #define FMUTEST_R_PIN_CTRL_ERASE(x)              (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_ERASE_SHIFT)) & FMUTEST_R_PIN_CTRL_ERASE_MASK)
26895 
26896 #define FMUTEST_R_PIN_CTRL_PROG_MASK             (0x100000U)
26897 #define FMUTEST_R_PIN_CTRL_PROG_SHIFT            (20U)
26898 /*! PROG - Program Mode */
26899 #define FMUTEST_R_PIN_CTRL_PROG(x)               (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_PROG_SHIFT)) & FMUTEST_R_PIN_CTRL_PROG_MASK)
26900 
26901 #define FMUTEST_R_PIN_CTRL_NVSTR_MASK            (0x200000U)
26902 #define FMUTEST_R_PIN_CTRL_NVSTR_SHIFT           (21U)
26903 /*! NVSTR - NVM Store */
26904 #define FMUTEST_R_PIN_CTRL_NVSTR(x)              (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_NVSTR_SHIFT)) & FMUTEST_R_PIN_CTRL_NVSTR_MASK)
26905 
26906 #define FMUTEST_R_PIN_CTRL_SLM_MASK              (0x400000U)
26907 #define FMUTEST_R_PIN_CTRL_SLM_SHIFT             (22U)
26908 /*! SLM - Sleep Mode Enable */
26909 #define FMUTEST_R_PIN_CTRL_SLM(x)                (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_SLM_SHIFT)) & FMUTEST_R_PIN_CTRL_SLM_MASK)
26910 
26911 #define FMUTEST_R_PIN_CTRL_RECALL_MASK           (0x800000U)
26912 #define FMUTEST_R_PIN_CTRL_RECALL_SHIFT          (23U)
26913 /*! RECALL - Recall Trim Code */
26914 #define FMUTEST_R_PIN_CTRL_RECALL(x)             (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_RECALL_SHIFT)) & FMUTEST_R_PIN_CTRL_RECALL_MASK)
26915 
26916 #define FMUTEST_R_PIN_CTRL_HEM_MASK              (0x1000000U)
26917 #define FMUTEST_R_PIN_CTRL_HEM_SHIFT             (24U)
26918 /*! HEM - HEM Control */
26919 #define FMUTEST_R_PIN_CTRL_HEM(x)                (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_HEM_SHIFT)) & FMUTEST_R_PIN_CTRL_HEM_MASK)
26920 /*! @} */
26921 
26922 /*! @name R_CNT_LOOP_CTRL - BIST Loop Count Control Register */
26923 /*! @{ */
26924 
26925 #define FMUTEST_R_CNT_LOOP_CTRL_LOOPCNT_MASK     (0xFFFU)
26926 #define FMUTEST_R_CNT_LOOP_CTRL_LOOPCNT_SHIFT    (0U)
26927 /*! LOOPCNT - Loop Count Control */
26928 #define FMUTEST_R_CNT_LOOP_CTRL_LOOPCNT(x)       (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_CNT_LOOP_CTRL_LOOPCNT_SHIFT)) & FMUTEST_R_CNT_LOOP_CTRL_LOOPCNT_MASK)
26929 
26930 #define FMUTEST_R_CNT_LOOP_CTRL_LOOPOPT_MASK     (0x7000U)
26931 #define FMUTEST_R_CNT_LOOP_CTRL_LOOPOPT_SHIFT    (12U)
26932 /*! LOOPOPT - Loop Option
26933  *  0b000..Loop is disabled; selected BIST operation is run once
26934  *  0b001..Loop is enabled; XADR increments by 1 XADR increments by 1 for each new loop. Stops when total loop count meets LOOPCNT+1.
26935  *  0b010..Loop is enabled; YADR increments by 1 YADR increments by 1 for each new loop. Stops when total loop count meets LOOPCNT+1.
26936  *  0b011..Loop is enabled; XADR increments by 2 XADR increments by 2 for each new loop. Stops when total loop count meets LOOPCNT+1.
26937  *  0b100..Loop is enabled; XADR increments by sector XADR increments by 16 for each new loop. Stops when total loop count meets LOOPCNT+1.
26938  */
26939 #define FMUTEST_R_CNT_LOOP_CTRL_LOOPOPT(x)       (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_CNT_LOOP_CTRL_LOOPOPT_SHIFT)) & FMUTEST_R_CNT_LOOP_CTRL_LOOPOPT_MASK)
26940 
26941 #define FMUTEST_R_CNT_LOOP_CTRL_LOOPUNIT_MASK    (0x38000U)
26942 #define FMUTEST_R_CNT_LOOP_CTRL_LOOPUNIT_SHIFT   (15U)
26943 /*! LOOPUNIT - Loop Time Unit
26944  *  0b000..Clock cycles
26945  *  0b001..0.5 usec
26946  *  0b010..1 usec
26947  *  0b011..10 usec
26948  *  0b100..100 usec
26949  *  0b101..1 msec
26950  *  0b110..10 msec
26951  *  0b111..100 msec
26952  */
26953 #define FMUTEST_R_CNT_LOOP_CTRL_LOOPUNIT(x)      (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_CNT_LOOP_CTRL_LOOPUNIT_SHIFT)) & FMUTEST_R_CNT_LOOP_CTRL_LOOPUNIT_MASK)
26954 
26955 #define FMUTEST_R_CNT_LOOP_CTRL_LOOPDLY_MASK     (0x1FC0000U)
26956 #define FMUTEST_R_CNT_LOOP_CTRL_LOOPDLY_SHIFT    (18U)
26957 /*! LOOPDLY - Loop Time Delay Scalar */
26958 #define FMUTEST_R_CNT_LOOP_CTRL_LOOPDLY(x)       (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_CNT_LOOP_CTRL_LOOPDLY_SHIFT)) & FMUTEST_R_CNT_LOOP_CTRL_LOOPDLY_MASK)
26959 /*! @} */
26960 
26961 /*! @name R_TIMER_CTRL - BIST Timer Control Register */
26962 /*! @{ */
26963 
26964 #define FMUTEST_R_TIMER_CTRL_TNVSUNIT_MASK       (0x7U)
26965 #define FMUTEST_R_TIMER_CTRL_TNVSUNIT_SHIFT      (0U)
26966 /*! TNVSUNIT - Tnvs Time Unit
26967  *  0b000..Clock cycles
26968  *  0b001..0.5 usec
26969  *  0b010..1 usec
26970  *  0b011..10 usec
26971  *  0b100..100 usec
26972  *  0b101..1 msec
26973  *  0b110..10 msec
26974  *  0b111..100 msec
26975  */
26976 #define FMUTEST_R_TIMER_CTRL_TNVSUNIT(x)         (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TIMER_CTRL_TNVSUNIT_SHIFT)) & FMUTEST_R_TIMER_CTRL_TNVSUNIT_MASK)
26977 
26978 #define FMUTEST_R_TIMER_CTRL_TNVSDLY_MASK        (0x78U)
26979 #define FMUTEST_R_TIMER_CTRL_TNVSDLY_SHIFT       (3U)
26980 /*! TNVSDLY - Tnvs Time Delay Scalar */
26981 #define FMUTEST_R_TIMER_CTRL_TNVSDLY(x)          (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TIMER_CTRL_TNVSDLY_SHIFT)) & FMUTEST_R_TIMER_CTRL_TNVSDLY_MASK)
26982 
26983 #define FMUTEST_R_TIMER_CTRL_TNVHUNIT_MASK       (0x380U)
26984 #define FMUTEST_R_TIMER_CTRL_TNVHUNIT_SHIFT      (7U)
26985 /*! TNVHUNIT - Tnvh Time Unit
26986  *  0b000..Clock cycles
26987  *  0b001..0.5 usec
26988  *  0b010..1 usec
26989  *  0b011..10 usec
26990  *  0b100..100 usec
26991  *  0b101..1 msec
26992  *  0b110..10 msec
26993  *  0b111..100 msec
26994  */
26995 #define FMUTEST_R_TIMER_CTRL_TNVHUNIT(x)         (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TIMER_CTRL_TNVHUNIT_SHIFT)) & FMUTEST_R_TIMER_CTRL_TNVHUNIT_MASK)
26996 
26997 #define FMUTEST_R_TIMER_CTRL_TNVHDLY_MASK        (0x3C00U)
26998 #define FMUTEST_R_TIMER_CTRL_TNVHDLY_SHIFT       (10U)
26999 /*! TNVHDLY - Tnvh Time Delay Scalar */
27000 #define FMUTEST_R_TIMER_CTRL_TNVHDLY(x)          (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TIMER_CTRL_TNVHDLY_SHIFT)) & FMUTEST_R_TIMER_CTRL_TNVHDLY_MASK)
27001 
27002 #define FMUTEST_R_TIMER_CTRL_TPGSUNIT_MASK       (0x1C000U)
27003 #define FMUTEST_R_TIMER_CTRL_TPGSUNIT_SHIFT      (14U)
27004 /*! TPGSUNIT - Tpgs Time Unit
27005  *  0b000..Clock cycles
27006  *  0b001..0.5 usec
27007  *  0b010..1 usec
27008  *  0b011..10 usec
27009  *  0b100..100 usec
27010  *  0b101..1 msec
27011  *  0b110..10 msec
27012  *  0b111..100 msec
27013  */
27014 #define FMUTEST_R_TIMER_CTRL_TPGSUNIT(x)         (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TIMER_CTRL_TPGSUNIT_SHIFT)) & FMUTEST_R_TIMER_CTRL_TPGSUNIT_MASK)
27015 
27016 #define FMUTEST_R_TIMER_CTRL_TPGSDLY_MASK        (0x1E0000U)
27017 #define FMUTEST_R_TIMER_CTRL_TPGSDLY_SHIFT       (17U)
27018 /*! TPGSDLY - Tpgs Time Delay Scalar */
27019 #define FMUTEST_R_TIMER_CTRL_TPGSDLY(x)          (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TIMER_CTRL_TPGSDLY_SHIFT)) & FMUTEST_R_TIMER_CTRL_TPGSDLY_MASK)
27020 
27021 #define FMUTEST_R_TIMER_CTRL_TRCVUNIT_MASK       (0xE00000U)
27022 #define FMUTEST_R_TIMER_CTRL_TRCVUNIT_SHIFT      (21U)
27023 /*! TRCVUNIT - Trcv Time Unit
27024  *  0b000..Clock cycles
27025  *  0b001..0.5 usec
27026  *  0b010..1 usec
27027  *  0b011..10 usec
27028  *  0b100..100 usec
27029  *  0b101..1 msec
27030  *  0b110..10 msec
27031  *  0b111..100 msec
27032  */
27033 #define FMUTEST_R_TIMER_CTRL_TRCVUNIT(x)         (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TIMER_CTRL_TRCVUNIT_SHIFT)) & FMUTEST_R_TIMER_CTRL_TRCVUNIT_MASK)
27034 
27035 #define FMUTEST_R_TIMER_CTRL_TRCVDLY_MASK        (0xF000000U)
27036 #define FMUTEST_R_TIMER_CTRL_TRCVDLY_SHIFT       (24U)
27037 /*! TRCVDLY - Trcv Time Delay Scalar */
27038 #define FMUTEST_R_TIMER_CTRL_TRCVDLY(x)          (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TIMER_CTRL_TRCVDLY_SHIFT)) & FMUTEST_R_TIMER_CTRL_TRCVDLY_MASK)
27039 
27040 #define FMUTEST_R_TIMER_CTRL_TLVSUNIT_MASK       (0x70000000U)
27041 #define FMUTEST_R_TIMER_CTRL_TLVSUNIT_SHIFT      (28U)
27042 /*! TLVSUNIT - Tlvs Time Unit
27043  *  0b000..Clock cycles
27044  *  0b001..0.5 usec
27045  *  0b010..1 usec
27046  *  0b011..10 usec
27047  *  0b100..100 usec
27048  *  0b101..1 msec
27049  *  0b110..10 msec
27050  *  0b111..100 msec
27051  */
27052 #define FMUTEST_R_TIMER_CTRL_TLVSUNIT(x)         (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TIMER_CTRL_TLVSUNIT_SHIFT)) & FMUTEST_R_TIMER_CTRL_TLVSUNIT_MASK)
27053 
27054 #define FMUTEST_R_TIMER_CTRL_TLVSDLY_L_MASK      (0x80000000U)
27055 #define FMUTEST_R_TIMER_CTRL_TLVSDLY_L_SHIFT     (31U)
27056 /*! TLVSDLY_L - Tlvs Time Delay Scalar Low */
27057 #define FMUTEST_R_TIMER_CTRL_TLVSDLY_L(x)        (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TIMER_CTRL_TLVSDLY_L_SHIFT)) & FMUTEST_R_TIMER_CTRL_TLVSDLY_L_MASK)
27058 /*! @} */
27059 
27060 /*! @name R_TEST_CTRL - BIST Test Control Register */
27061 /*! @{ */
27062 
27063 #define FMUTEST_R_TEST_CTRL_BUSY_MASK            (0x1U)
27064 #define FMUTEST_R_TEST_CTRL_BUSY_SHIFT           (0U)
27065 /*! BUSY - BIST Busy Status
27066  *  0b0..BIST is idle
27067  *  0b1..BIST is busy
27068  */
27069 #define FMUTEST_R_TEST_CTRL_BUSY(x)              (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TEST_CTRL_BUSY_SHIFT)) & FMUTEST_R_TEST_CTRL_BUSY_MASK)
27070 
27071 #define FMUTEST_R_TEST_CTRL_DEBUG_MASK           (0x2U)
27072 #define FMUTEST_R_TEST_CTRL_DEBUG_SHIFT          (1U)
27073 /*! DEBUG - BIST Debug Status */
27074 #define FMUTEST_R_TEST_CTRL_DEBUG(x)             (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TEST_CTRL_DEBUG_SHIFT)) & FMUTEST_R_TEST_CTRL_DEBUG_MASK)
27075 
27076 #define FMUTEST_R_TEST_CTRL_STATUS0_MASK         (0x4U)
27077 #define FMUTEST_R_TEST_CTRL_STATUS0_SHIFT        (2U)
27078 /*! STATUS0 - BIST Status 0
27079  *  0b0..BIST test passed on flash block 0
27080  *  0b1..BIST test failed on flash block 0
27081  */
27082 #define FMUTEST_R_TEST_CTRL_STATUS0(x)           (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TEST_CTRL_STATUS0_SHIFT)) & FMUTEST_R_TEST_CTRL_STATUS0_MASK)
27083 
27084 #define FMUTEST_R_TEST_CTRL_STATUS1_MASK         (0x8U)
27085 #define FMUTEST_R_TEST_CTRL_STATUS1_SHIFT        (3U)
27086 /*! STATUS1 - BIST status 1
27087  *  0b0..BIST test passed on flash block 1
27088  *  0b1..BIST test failed on flash block 1
27089  */
27090 #define FMUTEST_R_TEST_CTRL_STATUS1(x)           (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TEST_CTRL_STATUS1_SHIFT)) & FMUTEST_R_TEST_CTRL_STATUS1_MASK)
27091 
27092 #define FMUTEST_R_TEST_CTRL_DEBUGRUN_MASK        (0x10U)
27093 #define FMUTEST_R_TEST_CTRL_DEBUGRUN_SHIFT       (4U)
27094 /*! DEBUGRUN - BIST Continue Debug Run */
27095 #define FMUTEST_R_TEST_CTRL_DEBUGRUN(x)          (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TEST_CTRL_DEBUGRUN_SHIFT)) & FMUTEST_R_TEST_CTRL_DEBUGRUN_MASK)
27096 
27097 #define FMUTEST_R_TEST_CTRL_STARTRUN_MASK        (0x20U)
27098 #define FMUTEST_R_TEST_CTRL_STARTRUN_SHIFT       (5U)
27099 /*! STARTRUN - Run New BIST Operation */
27100 #define FMUTEST_R_TEST_CTRL_STARTRUN(x)          (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TEST_CTRL_STARTRUN_SHIFT)) & FMUTEST_R_TEST_CTRL_STARTRUN_MASK)
27101 
27102 #define FMUTEST_R_TEST_CTRL_CMDINDEX_MASK        (0xFFC0U)
27103 #define FMUTEST_R_TEST_CTRL_CMDINDEX_SHIFT       (6U)
27104 /*! CMDINDEX - BIST Command Index (code) */
27105 #define FMUTEST_R_TEST_CTRL_CMDINDEX(x)          (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TEST_CTRL_CMDINDEX_SHIFT)) & FMUTEST_R_TEST_CTRL_CMDINDEX_MASK)
27106 
27107 #define FMUTEST_R_TEST_CTRL_DISABLE_IP1_MASK     (0x10000U)
27108 #define FMUTEST_R_TEST_CTRL_DISABLE_IP1_SHIFT    (16U)
27109 /*! DISABLE_IP1 - BIST Disable IP1 */
27110 #define FMUTEST_R_TEST_CTRL_DISABLE_IP1(x)       (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TEST_CTRL_DISABLE_IP1_SHIFT)) & FMUTEST_R_TEST_CTRL_DISABLE_IP1_MASK)
27111 /*! @} */
27112 
27113 /*! @name R_ABORT_LOOP - BIST Abort Loop Register */
27114 /*! @{ */
27115 
27116 #define FMUTEST_R_ABORT_LOOP_ABORT_LOOP_MASK     (0x1U)
27117 #define FMUTEST_R_ABORT_LOOP_ABORT_LOOP_SHIFT    (0U)
27118 /*! ABORT_LOOP - Abort Loop
27119  *  0b0..No effect
27120  *  0b1..Abort BIST loop commands and force the loop counter to return to 0x0
27121  */
27122 #define FMUTEST_R_ABORT_LOOP_ABORT_LOOP(x)       (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_ABORT_LOOP_ABORT_LOOP_SHIFT)) & FMUTEST_R_ABORT_LOOP_ABORT_LOOP_MASK)
27123 /*! @} */
27124 
27125 /*! @name R_ADR_QUERY - BIST Address Query Register */
27126 /*! @{ */
27127 
27128 #define FMUTEST_R_ADR_QUERY_YADRFAIL_MASK        (0x1FU)
27129 #define FMUTEST_R_ADR_QUERY_YADRFAIL_SHIFT       (0U)
27130 /*! YADRFAIL - Failing YADR */
27131 #define FMUTEST_R_ADR_QUERY_YADRFAIL(x)          (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_ADR_QUERY_YADRFAIL_SHIFT)) & FMUTEST_R_ADR_QUERY_YADRFAIL_MASK)
27132 
27133 #define FMUTEST_R_ADR_QUERY_XADRFAIL_MASK        (0x1FFE0U)
27134 #define FMUTEST_R_ADR_QUERY_XADRFAIL_SHIFT       (5U)
27135 /*! XADRFAIL - Failing XADR */
27136 #define FMUTEST_R_ADR_QUERY_XADRFAIL(x)          (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_ADR_QUERY_XADRFAIL_SHIFT)) & FMUTEST_R_ADR_QUERY_XADRFAIL_MASK)
27137 /*! @} */
27138 
27139 /*! @name R_DOUT_QUERY0 - BIST DOUT Query 0 Register */
27140 /*! @{ */
27141 
27142 #define FMUTEST_R_DOUT_QUERY0_DOUTFAIL_MASK      (0xFFFFFFFFU)
27143 #define FMUTEST_R_DOUT_QUERY0_DOUTFAIL_SHIFT     (0U)
27144 /*! DOUTFAIL - Failing DOUT Low */
27145 #define FMUTEST_R_DOUT_QUERY0_DOUTFAIL(x)        (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DOUT_QUERY0_DOUTFAIL_SHIFT)) & FMUTEST_R_DOUT_QUERY0_DOUTFAIL_MASK)
27146 /*! @} */
27147 
27148 /*! @name R_SMW_QUERY - BIST SMW Query Register */
27149 /*! @{ */
27150 
27151 #define FMUTEST_R_SMW_QUERY_SMWLOOP_MASK         (0x3FFU)
27152 #define FMUTEST_R_SMW_QUERY_SMWLOOP_SHIFT        (0U)
27153 /*! SMWLOOP - SMW Total Loop Count */
27154 #define FMUTEST_R_SMW_QUERY_SMWLOOP(x)           (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_SMW_QUERY_SMWLOOP_SHIFT)) & FMUTEST_R_SMW_QUERY_SMWLOOP_MASK)
27155 
27156 #define FMUTEST_R_SMW_QUERY_SMWLAST_MASK         (0x7FC00U)
27157 #define FMUTEST_R_SMW_QUERY_SMWLAST_SHIFT        (10U)
27158 /*! SMWLAST - SMW Last Voltage Setting */
27159 #define FMUTEST_R_SMW_QUERY_SMWLAST(x)           (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_SMW_QUERY_SMWLAST_SHIFT)) & FMUTEST_R_SMW_QUERY_SMWLAST_MASK)
27160 /*! @} */
27161 
27162 /*! @name R_SMW_SETTING0 - BIST SMW Setting 0 Register */
27163 /*! @{ */
27164 
27165 #define FMUTEST_R_SMW_SETTING0_SMWPARM0_MASK     (0x7FFFFFFFU)
27166 #define FMUTEST_R_SMW_SETTING0_SMWPARM0_SHIFT    (0U)
27167 /*! SMWPARM0 - SMW Parameter Set 0 */
27168 #define FMUTEST_R_SMW_SETTING0_SMWPARM0(x)       (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_SMW_SETTING0_SMWPARM0_SHIFT)) & FMUTEST_R_SMW_SETTING0_SMWPARM0_MASK)
27169 /*! @} */
27170 
27171 /*! @name R_SMW_SETTING1 - BIST SMW Setting 1 Register */
27172 /*! @{ */
27173 
27174 #define FMUTEST_R_SMW_SETTING1_SMWPARM1_MASK     (0xFFFFFFFU)
27175 #define FMUTEST_R_SMW_SETTING1_SMWPARM1_SHIFT    (0U)
27176 /*! SMWPARM1 - SMW Parameter Set 1 */
27177 #define FMUTEST_R_SMW_SETTING1_SMWPARM1(x)       (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_SMW_SETTING1_SMWPARM1_SHIFT)) & FMUTEST_R_SMW_SETTING1_SMWPARM1_MASK)
27178 /*! @} */
27179 
27180 /*! @name R_SMP_WHV0 - BIST SMP WHV Setting 0 Register */
27181 /*! @{ */
27182 
27183 #define FMUTEST_R_SMP_WHV0_SMPWHV0_MASK          (0xFFFFFFFFU)
27184 #define FMUTEST_R_SMP_WHV0_SMPWHV0_SHIFT         (0U)
27185 /*! SMPWHV0 - SMP WHV Parameter Set 0 */
27186 #define FMUTEST_R_SMP_WHV0_SMPWHV0(x)            (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_SMP_WHV0_SMPWHV0_SHIFT)) & FMUTEST_R_SMP_WHV0_SMPWHV0_MASK)
27187 /*! @} */
27188 
27189 /*! @name R_SMP_WHV1 - BIST SMP WHV Setting 1 Register */
27190 /*! @{ */
27191 
27192 #define FMUTEST_R_SMP_WHV1_SMPWHV1_MASK          (0xFFFFFFFFU)
27193 #define FMUTEST_R_SMP_WHV1_SMPWHV1_SHIFT         (0U)
27194 /*! SMPWHV1 - SMP WHV Parameter Set 1 */
27195 #define FMUTEST_R_SMP_WHV1_SMPWHV1(x)            (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_SMP_WHV1_SMPWHV1_SHIFT)) & FMUTEST_R_SMP_WHV1_SMPWHV1_MASK)
27196 /*! @} */
27197 
27198 /*! @name R_SME_WHV0 - BIST SME WHV Setting 0 Register */
27199 /*! @{ */
27200 
27201 #define FMUTEST_R_SME_WHV0_SMEWHV0_MASK          (0xFFFFFFFFU)
27202 #define FMUTEST_R_SME_WHV0_SMEWHV0_SHIFT         (0U)
27203 /*! SMEWHV0 - SME WHV Parameter Set 0 */
27204 #define FMUTEST_R_SME_WHV0_SMEWHV0(x)            (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_SME_WHV0_SMEWHV0_SHIFT)) & FMUTEST_R_SME_WHV0_SMEWHV0_MASK)
27205 /*! @} */
27206 
27207 /*! @name R_SME_WHV1 - BIST SME WHV Setting 1 Register */
27208 /*! @{ */
27209 
27210 #define FMUTEST_R_SME_WHV1_SMEWHV1_MASK          (0xFFFFFFFFU)
27211 #define FMUTEST_R_SME_WHV1_SMEWHV1_SHIFT         (0U)
27212 /*! SMEWHV1 - SME WHV Parameter Set 1 */
27213 #define FMUTEST_R_SME_WHV1_SMEWHV1(x)            (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_SME_WHV1_SMEWHV1_SHIFT)) & FMUTEST_R_SME_WHV1_SMEWHV1_MASK)
27214 /*! @} */
27215 
27216 /*! @name R_SMW_SETTING2 - BIST SMW Setting 2 Register */
27217 /*! @{ */
27218 
27219 #define FMUTEST_R_SMW_SETTING2_SMWPARM2_MASK     (0x1FFFFFFFU)
27220 #define FMUTEST_R_SMW_SETTING2_SMWPARM2_SHIFT    (0U)
27221 /*! SMWPARM2 - SMW Parameter Set 2 */
27222 #define FMUTEST_R_SMW_SETTING2_SMWPARM2(x)       (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_SMW_SETTING2_SMWPARM2_SHIFT)) & FMUTEST_R_SMW_SETTING2_SMWPARM2_MASK)
27223 /*! @} */
27224 
27225 /*! @name R_D_MISR0 - BIST DIN MISR 0 Register */
27226 /*! @{ */
27227 
27228 #define FMUTEST_R_D_MISR0_DATASIG0_MASK          (0xFFFFFFFFU)
27229 #define FMUTEST_R_D_MISR0_DATASIG0_SHIFT         (0U)
27230 /*! DATASIG0 - Data Signature */
27231 #define FMUTEST_R_D_MISR0_DATASIG0(x)            (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_D_MISR0_DATASIG0_SHIFT)) & FMUTEST_R_D_MISR0_DATASIG0_MASK)
27232 /*! @} */
27233 
27234 /*! @name R_A_MISR0 - BIST Address MISR 0 Register */
27235 /*! @{ */
27236 
27237 #define FMUTEST_R_A_MISR0_ADRSIG0_MASK           (0xFFFFFFFFU)
27238 #define FMUTEST_R_A_MISR0_ADRSIG0_SHIFT          (0U)
27239 /*! ADRSIG0 - Address Signature */
27240 #define FMUTEST_R_A_MISR0_ADRSIG0(x)             (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_A_MISR0_ADRSIG0_SHIFT)) & FMUTEST_R_A_MISR0_ADRSIG0_MASK)
27241 /*! @} */
27242 
27243 /*! @name R_C_MISR0 - BIST Control MISR 0 Register */
27244 /*! @{ */
27245 
27246 #define FMUTEST_R_C_MISR0_CTRLSIG0_MASK          (0xFFFFFFFFU)
27247 #define FMUTEST_R_C_MISR0_CTRLSIG0_SHIFT         (0U)
27248 /*! CTRLSIG0 - Control Signature */
27249 #define FMUTEST_R_C_MISR0_CTRLSIG0(x)            (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_C_MISR0_CTRLSIG0_SHIFT)) & FMUTEST_R_C_MISR0_CTRLSIG0_MASK)
27250 /*! @} */
27251 
27252 /*! @name R_SMW_SETTING3 - BIST SMW Setting 3 Register */
27253 /*! @{ */
27254 
27255 #define FMUTEST_R_SMW_SETTING3_SMWPARM3_MASK     (0x1FFFFU)
27256 #define FMUTEST_R_SMW_SETTING3_SMWPARM3_SHIFT    (0U)
27257 /*! SMWPARM3 - SMW Parameter Set 3 */
27258 #define FMUTEST_R_SMW_SETTING3_SMWPARM3(x)       (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_SMW_SETTING3_SMWPARM3_SHIFT)) & FMUTEST_R_SMW_SETTING3_SMWPARM3_MASK)
27259 /*! @} */
27260 
27261 /*! @name R_DATA_CTRL1 - BIST Data Control 1 Register */
27262 /*! @{ */
27263 
27264 #define FMUTEST_R_DATA_CTRL1_DATA1_MASK          (0xFFFFFFFFU)
27265 #define FMUTEST_R_DATA_CTRL1_DATA1_SHIFT         (0U)
27266 /*! DATA1 - BIST Data 1 Low */
27267 #define FMUTEST_R_DATA_CTRL1_DATA1(x)            (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DATA_CTRL1_DATA1_SHIFT)) & FMUTEST_R_DATA_CTRL1_DATA1_MASK)
27268 /*! @} */
27269 
27270 /*! @name R_DATA_CTRL2 - BIST Data Control 2 Register */
27271 /*! @{ */
27272 
27273 #define FMUTEST_R_DATA_CTRL2_DATA2_MASK          (0xFFFFFFFFU)
27274 #define FMUTEST_R_DATA_CTRL2_DATA2_SHIFT         (0U)
27275 /*! DATA2 - BIST Data 2 Low */
27276 #define FMUTEST_R_DATA_CTRL2_DATA2(x)            (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DATA_CTRL2_DATA2_SHIFT)) & FMUTEST_R_DATA_CTRL2_DATA2_MASK)
27277 /*! @} */
27278 
27279 /*! @name R_DATA_CTRL3 - BIST Data Control 3 Register */
27280 /*! @{ */
27281 
27282 #define FMUTEST_R_DATA_CTRL3_DATA3_MASK          (0xFFFFFFFFU)
27283 #define FMUTEST_R_DATA_CTRL3_DATA3_SHIFT         (0U)
27284 /*! DATA3 - BIST Data 3 Low */
27285 #define FMUTEST_R_DATA_CTRL3_DATA3(x)            (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DATA_CTRL3_DATA3_SHIFT)) & FMUTEST_R_DATA_CTRL3_DATA3_MASK)
27286 /*! @} */
27287 
27288 /*! @name R_REPAIR0_0 - BIST Repair 0 for Block 0 Register */
27289 /*! @{ */
27290 
27291 #define FMUTEST_R_REPAIR0_0_RDIS0_0_MASK         (0x1U)
27292 #define FMUTEST_R_REPAIR0_0_RDIS0_0_SHIFT        (0U)
27293 /*! RDIS0_0 - Control Repair 0 in Block 0.
27294  *  0b0..Repair address is valid
27295  *  0b1..Repair address is not valid
27296  */
27297 #define FMUTEST_R_REPAIR0_0_RDIS0_0(x)           (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_REPAIR0_0_RDIS0_0_SHIFT)) & FMUTEST_R_REPAIR0_0_RDIS0_0_MASK)
27298 
27299 #define FMUTEST_R_REPAIR0_0_RADR0_0_MASK         (0x1FEU)
27300 #define FMUTEST_R_REPAIR0_0_RADR0_0_SHIFT        (1U)
27301 /*! RADR0_0 - XADR for Repair 0 in Block 0 */
27302 #define FMUTEST_R_REPAIR0_0_RADR0_0(x)           (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_REPAIR0_0_RADR0_0_SHIFT)) & FMUTEST_R_REPAIR0_0_RADR0_0_MASK)
27303 /*! @} */
27304 
27305 /*! @name R_REPAIR0_1 - BIST Repair 1 Block 0 Register */
27306 /*! @{ */
27307 
27308 #define FMUTEST_R_REPAIR0_1_RDIS0_1_MASK         (0x1U)
27309 #define FMUTEST_R_REPAIR0_1_RDIS0_1_SHIFT        (0U)
27310 /*! RDIS0_1 - Control Repair 1 in Block 0.
27311  *  0b0..Repair address is valid
27312  *  0b1..Repair address is not valid
27313  */
27314 #define FMUTEST_R_REPAIR0_1_RDIS0_1(x)           (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_REPAIR0_1_RDIS0_1_SHIFT)) & FMUTEST_R_REPAIR0_1_RDIS0_1_MASK)
27315 
27316 #define FMUTEST_R_REPAIR0_1_RADR0_1_MASK         (0x1FEU)
27317 #define FMUTEST_R_REPAIR0_1_RADR0_1_SHIFT        (1U)
27318 /*! RADR0_1 - XADR for Repair 1 in Block 0. */
27319 #define FMUTEST_R_REPAIR0_1_RADR0_1(x)           (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_REPAIR0_1_RADR0_1_SHIFT)) & FMUTEST_R_REPAIR0_1_RADR0_1_MASK)
27320 /*! @} */
27321 
27322 /*! @name R_REPAIR1_0 - BIST Repair 0 Block 1 Register */
27323 /*! @{ */
27324 
27325 #define FMUTEST_R_REPAIR1_0_RDIS1_0_MASK         (0x1U)
27326 #define FMUTEST_R_REPAIR1_0_RDIS1_0_SHIFT        (0U)
27327 /*! RDIS1_0 - Control Repair 0 in Block 1.
27328  *  0b0..Repair address is valid
27329  *  0b1..Repair address is not valid
27330  */
27331 #define FMUTEST_R_REPAIR1_0_RDIS1_0(x)           (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_REPAIR1_0_RDIS1_0_SHIFT)) & FMUTEST_R_REPAIR1_0_RDIS1_0_MASK)
27332 
27333 #define FMUTEST_R_REPAIR1_0_RADR1_0_MASK         (0x1FEU)
27334 #define FMUTEST_R_REPAIR1_0_RADR1_0_SHIFT        (1U)
27335 /*! RADR1_0 - XADR for Repair 0 in Block 1. */
27336 #define FMUTEST_R_REPAIR1_0_RADR1_0(x)           (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_REPAIR1_0_RADR1_0_SHIFT)) & FMUTEST_R_REPAIR1_0_RADR1_0_MASK)
27337 /*! @} */
27338 
27339 /*! @name R_REPAIR1_1 - BIST Repair 1 Block 1 Register */
27340 /*! @{ */
27341 
27342 #define FMUTEST_R_REPAIR1_1_RDIS1_1_MASK         (0x1U)
27343 #define FMUTEST_R_REPAIR1_1_RDIS1_1_SHIFT        (0U)
27344 /*! RDIS1_1 - Control Repair 1 in Block 1.
27345  *  0b0..Repair address is valid
27346  *  0b1..Repair address is not valid
27347  */
27348 #define FMUTEST_R_REPAIR1_1_RDIS1_1(x)           (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_REPAIR1_1_RDIS1_1_SHIFT)) & FMUTEST_R_REPAIR1_1_RDIS1_1_MASK)
27349 
27350 #define FMUTEST_R_REPAIR1_1_RADR1_1_MASK         (0x1FEU)
27351 #define FMUTEST_R_REPAIR1_1_RADR1_1_SHIFT        (1U)
27352 /*! RADR1_1 - XADR for Repair 1 in Block 1. */
27353 #define FMUTEST_R_REPAIR1_1_RADR1_1(x)           (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_REPAIR1_1_RADR1_1_SHIFT)) & FMUTEST_R_REPAIR1_1_RADR1_1_MASK)
27354 /*! @} */
27355 
27356 /*! @name R_DATA_CTRL0_EX - BIST Data Control 0 Extension Register */
27357 /*! @{ */
27358 
27359 #define FMUTEST_R_DATA_CTRL0_EX_DATA0X_MASK      (0x7U)
27360 #define FMUTEST_R_DATA_CTRL0_EX_DATA0X_SHIFT     (0U)
27361 /*! DATA0X - BIST Data 0 High */
27362 #define FMUTEST_R_DATA_CTRL0_EX_DATA0X(x)        (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DATA_CTRL0_EX_DATA0X_SHIFT)) & FMUTEST_R_DATA_CTRL0_EX_DATA0X_MASK)
27363 /*! @} */
27364 
27365 /*! @name R_TIMER_CTRL_EX - BIST Timer Control Extension Register */
27366 /*! @{ */
27367 
27368 #define FMUTEST_R_TIMER_CTRL_EX_TLVSDLY_H_MASK   (0x7U)
27369 #define FMUTEST_R_TIMER_CTRL_EX_TLVSDLY_H_SHIFT  (0U)
27370 /*! TLVSDLY_H - Tlvs Time Delay Scalar High */
27371 #define FMUTEST_R_TIMER_CTRL_EX_TLVSDLY_H(x)     (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TIMER_CTRL_EX_TLVSDLY_H_SHIFT)) & FMUTEST_R_TIMER_CTRL_EX_TLVSDLY_H_MASK)
27372 /*! @} */
27373 
27374 /*! @name R_DOUT_QUERY1 - BIST DOUT Query 1 Register */
27375 /*! @{ */
27376 
27377 #define FMUTEST_R_DOUT_QUERY1_DOUT_MASK          (0x7U)
27378 #define FMUTEST_R_DOUT_QUERY1_DOUT_SHIFT         (0U)
27379 /*! DOUT - Failing DOUT High */
27380 #define FMUTEST_R_DOUT_QUERY1_DOUT(x)            (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DOUT_QUERY1_DOUT_SHIFT)) & FMUTEST_R_DOUT_QUERY1_DOUT_MASK)
27381 /*! @} */
27382 
27383 /*! @name R_D_MISR1 - BIST DIN MISR 1 Register */
27384 /*! @{ */
27385 
27386 #define FMUTEST_R_D_MISR1_DATASIG1_MASK          (0xFFU)
27387 #define FMUTEST_R_D_MISR1_DATASIG1_SHIFT         (0U)
27388 /*! DATASIG1 - MISR Data Signature High */
27389 #define FMUTEST_R_D_MISR1_DATASIG1(x)            (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_D_MISR1_DATASIG1_SHIFT)) & FMUTEST_R_D_MISR1_DATASIG1_MASK)
27390 /*! @} */
27391 
27392 /*! @name R_A_MISR1 - BIST Address MISR 1 Register */
27393 /*! @{ */
27394 
27395 #define FMUTEST_R_A_MISR1_ADRSIG1_MASK           (0xFFU)
27396 #define FMUTEST_R_A_MISR1_ADRSIG1_SHIFT          (0U)
27397 /*! ADRSIG1 - MISR Address Signature High */
27398 #define FMUTEST_R_A_MISR1_ADRSIG1(x)             (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_A_MISR1_ADRSIG1_SHIFT)) & FMUTEST_R_A_MISR1_ADRSIG1_MASK)
27399 /*! @} */
27400 
27401 /*! @name R_C_MISR1 - BIST Control MISR 1 Register */
27402 /*! @{ */
27403 
27404 #define FMUTEST_R_C_MISR1_CTRLSIG1_MASK          (0xFFU)
27405 #define FMUTEST_R_C_MISR1_CTRLSIG1_SHIFT         (0U)
27406 /*! CTRLSIG1 - MISR Control Signature High */
27407 #define FMUTEST_R_C_MISR1_CTRLSIG1(x)            (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_C_MISR1_CTRLSIG1_SHIFT)) & FMUTEST_R_C_MISR1_CTRLSIG1_MASK)
27408 /*! @} */
27409 
27410 /*! @name R_DATA_CTRL1_EX - BIST Data Control 1 Extension Register */
27411 /*! @{ */
27412 
27413 #define FMUTEST_R_DATA_CTRL1_EX_DATA1X_MASK      (0x7U)
27414 #define FMUTEST_R_DATA_CTRL1_EX_DATA1X_SHIFT     (0U)
27415 /*! DATA1X - BIST Data 1 High */
27416 #define FMUTEST_R_DATA_CTRL1_EX_DATA1X(x)        (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DATA_CTRL1_EX_DATA1X_SHIFT)) & FMUTEST_R_DATA_CTRL1_EX_DATA1X_MASK)
27417 /*! @} */
27418 
27419 /*! @name R_DATA_CTRL2_EX - BIST Data Control 2 Extension Register */
27420 /*! @{ */
27421 
27422 #define FMUTEST_R_DATA_CTRL2_EX_DATA2X_MASK      (0x7U)
27423 #define FMUTEST_R_DATA_CTRL2_EX_DATA2X_SHIFT     (0U)
27424 /*! DATA2X - BIST Data 2 High */
27425 #define FMUTEST_R_DATA_CTRL2_EX_DATA2X(x)        (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DATA_CTRL2_EX_DATA2X_SHIFT)) & FMUTEST_R_DATA_CTRL2_EX_DATA2X_MASK)
27426 /*! @} */
27427 
27428 /*! @name R_DATA_CTRL3_EX - BIST Data Control 3 Extension Register */
27429 /*! @{ */
27430 
27431 #define FMUTEST_R_DATA_CTRL3_EX_DATA3X_MASK      (0x7U)
27432 #define FMUTEST_R_DATA_CTRL3_EX_DATA3X_SHIFT     (0U)
27433 /*! DATA3X - BIST Data 3 High */
27434 #define FMUTEST_R_DATA_CTRL3_EX_DATA3X(x)        (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DATA_CTRL3_EX_DATA3X_SHIFT)) & FMUTEST_R_DATA_CTRL3_EX_DATA3X_MASK)
27435 /*! @} */
27436 
27437 /*! @name SMW_TIMER_OPTION - SMW Timer Option Register */
27438 /*! @{ */
27439 
27440 #define FMUTEST_SMW_TIMER_OPTION_SMW_CDIVL_MASK  (0xFFU)
27441 #define FMUTEST_SMW_TIMER_OPTION_SMW_CDIVL_SHIFT (0U)
27442 /*! SMW_CDIVL - Clock Divide Scalar for Long Pulse */
27443 #define FMUTEST_SMW_TIMER_OPTION_SMW_CDIVL(x)    (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_TIMER_OPTION_SMW_CDIVL_SHIFT)) & FMUTEST_SMW_TIMER_OPTION_SMW_CDIVL_MASK)
27444 
27445 #define FMUTEST_SMW_TIMER_OPTION_SMW_TVFY_MASK   (0x1F00U)
27446 #define FMUTEST_SMW_TIMER_OPTION_SMW_TVFY_SHIFT  (8U)
27447 /*! SMW_TVFY - Timer Adjust for Verify */
27448 #define FMUTEST_SMW_TIMER_OPTION_SMW_TVFY(x)     (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_TIMER_OPTION_SMW_TVFY_SHIFT)) & FMUTEST_SMW_TIMER_OPTION_SMW_TVFY_MASK)
27449 /*! @} */
27450 
27451 /*! @name SMW_SETTING_OPTION0 - SMW Setting Option 0 Register */
27452 /*! @{ */
27453 
27454 #define FMUTEST_SMW_SETTING_OPTION0_MV_INIT_MASK (0x1C000U)
27455 #define FMUTEST_SMW_SETTING_OPTION0_MV_INIT_SHIFT (14U)
27456 /*! MV_INIT - Medium Voltage Level Select Initial */
27457 #define FMUTEST_SMW_SETTING_OPTION0_MV_INIT(x)   (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION0_MV_INIT_SHIFT)) & FMUTEST_SMW_SETTING_OPTION0_MV_INIT_MASK)
27458 
27459 #define FMUTEST_SMW_SETTING_OPTION0_MV_END_MASK  (0xE0000U)
27460 #define FMUTEST_SMW_SETTING_OPTION0_MV_END_SHIFT (17U)
27461 /*! MV_END - Medium Voltage Level Select Final */
27462 #define FMUTEST_SMW_SETTING_OPTION0_MV_END(x)    (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION0_MV_END_SHIFT)) & FMUTEST_SMW_SETTING_OPTION0_MV_END_MASK)
27463 
27464 #define FMUTEST_SMW_SETTING_OPTION0_MV_MISC_MASK (0xF00000U)
27465 #define FMUTEST_SMW_SETTING_OPTION0_MV_MISC_SHIFT (20U)
27466 /*! MV_MISC - Medium Voltage Control Misc */
27467 #define FMUTEST_SMW_SETTING_OPTION0_MV_MISC(x)   (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION0_MV_MISC_SHIFT)) & FMUTEST_SMW_SETTING_OPTION0_MV_MISC_MASK)
27468 
27469 #define FMUTEST_SMW_SETTING_OPTION0_IPGM_INIT_MASK (0x3000000U)
27470 #define FMUTEST_SMW_SETTING_OPTION0_IPGM_INIT_SHIFT (24U)
27471 /*! IPGM_INIT - Program Current Control Initial */
27472 #define FMUTEST_SMW_SETTING_OPTION0_IPGM_INIT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION0_IPGM_INIT_SHIFT)) & FMUTEST_SMW_SETTING_OPTION0_IPGM_INIT_MASK)
27473 
27474 #define FMUTEST_SMW_SETTING_OPTION0_IPGM_END_MASK (0xC000000U)
27475 #define FMUTEST_SMW_SETTING_OPTION0_IPGM_END_SHIFT (26U)
27476 /*! IPGM_END - Program Current Control Final */
27477 #define FMUTEST_SMW_SETTING_OPTION0_IPGM_END(x)  (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION0_IPGM_END_SHIFT)) & FMUTEST_SMW_SETTING_OPTION0_IPGM_END_MASK)
27478 
27479 #define FMUTEST_SMW_SETTING_OPTION0_IPGM_MISC_MASK (0x70000000U)
27480 #define FMUTEST_SMW_SETTING_OPTION0_IPGM_MISC_SHIFT (28U)
27481 /*! IPGM_MISC - Program Current Control Misc */
27482 #define FMUTEST_SMW_SETTING_OPTION0_IPGM_MISC(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION0_IPGM_MISC_SHIFT)) & FMUTEST_SMW_SETTING_OPTION0_IPGM_MISC_MASK)
27483 /*! @} */
27484 
27485 /*! @name SMW_SETTING_OPTION2 - SMW Setting Option 2 Register */
27486 /*! @{ */
27487 
27488 #define FMUTEST_SMW_SETTING_OPTION2_THVS_CTRL_MASK (0x7U)
27489 #define FMUTEST_SMW_SETTING_OPTION2_THVS_CTRL_SHIFT (0U)
27490 /*! THVS_CTRL - Thvs control */
27491 #define FMUTEST_SMW_SETTING_OPTION2_THVS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION2_THVS_CTRL_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_THVS_CTRL_MASK)
27492 
27493 #define FMUTEST_SMW_SETTING_OPTION2_TRCV_CTRL_MASK (0x38U)
27494 #define FMUTEST_SMW_SETTING_OPTION2_TRCV_CTRL_SHIFT (3U)
27495 /*! TRCV_CTRL - Trcv Control */
27496 #define FMUTEST_SMW_SETTING_OPTION2_TRCV_CTRL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION2_TRCV_CTRL_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_TRCV_CTRL_MASK)
27497 
27498 #define FMUTEST_SMW_SETTING_OPTION2_XTRA_ERS_MASK (0xC0U)
27499 #define FMUTEST_SMW_SETTING_OPTION2_XTRA_ERS_SHIFT (6U)
27500 /*! XTRA_ERS - Number of Post Shots for SME */
27501 #define FMUTEST_SMW_SETTING_OPTION2_XTRA_ERS(x)  (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION2_XTRA_ERS_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_XTRA_ERS_MASK)
27502 
27503 #define FMUTEST_SMW_SETTING_OPTION2_XTRA_PGM_MASK (0x300U)
27504 #define FMUTEST_SMW_SETTING_OPTION2_XTRA_PGM_SHIFT (8U)
27505 /*! XTRA_PGM - Number of Post Shots for SMP */
27506 #define FMUTEST_SMW_SETTING_OPTION2_XTRA_PGM(x)  (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION2_XTRA_PGM_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_XTRA_PGM_MASK)
27507 
27508 #define FMUTEST_SMW_SETTING_OPTION2_WHV_CNTR_MASK (0x3FC00U)
27509 #define FMUTEST_SMW_SETTING_OPTION2_WHV_CNTR_SHIFT (10U)
27510 /*! WHV_CNTR - WHV Counter */
27511 #define FMUTEST_SMW_SETTING_OPTION2_WHV_CNTR(x)  (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION2_WHV_CNTR_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_WHV_CNTR_MASK)
27512 
27513 #define FMUTEST_SMW_SETTING_OPTION2_POST_TERS_MASK (0x1C0000U)
27514 #define FMUTEST_SMW_SETTING_OPTION2_POST_TERS_SHIFT (18U)
27515 /*! POST_TERS - Post Ters Time
27516  *  0b000..50 usec
27517  *  0b001..100 usec
27518  *  0b010..200 usec
27519  *  0b011..300 usec
27520  *  0b100..500 usec
27521  *  0b101..1 msec
27522  *  0b110..1.5 msec
27523  *  0b111..2 msec
27524  */
27525 #define FMUTEST_SMW_SETTING_OPTION2_POST_TERS(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION2_POST_TERS_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_POST_TERS_MASK)
27526 
27527 #define FMUTEST_SMW_SETTING_OPTION2_POST_TPGM_MASK (0x600000U)
27528 #define FMUTEST_SMW_SETTING_OPTION2_POST_TPGM_SHIFT (21U)
27529 /*! POST_TPGM - Post Tpgm Time
27530  *  0b00..1 usec
27531  *  0b01..2 usec
27532  *  0b10..4 usec
27533  *  0b11..8 usec
27534  */
27535 #define FMUTEST_SMW_SETTING_OPTION2_POST_TPGM(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION2_POST_TPGM_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_POST_TPGM_MASK)
27536 
27537 #define FMUTEST_SMW_SETTING_OPTION2_VFY_OPT_MASK (0x1800000U)
27538 #define FMUTEST_SMW_SETTING_OPTION2_VFY_OPT_SHIFT (23U)
27539 /*! VFY_OPT - Verify Option
27540  *  0b00..Skip verify for post shot only, verify for all other shots
27541  *  0b01..Skip verify for the 1st and post shots
27542  *  0b10..Skip the 1st, 2nd, and post shots
27543  *  0b11..Skip verify for all shots
27544  */
27545 #define FMUTEST_SMW_SETTING_OPTION2_VFY_OPT(x)   (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION2_VFY_OPT_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_VFY_OPT_MASK)
27546 
27547 #define FMUTEST_SMW_SETTING_OPTION2_TPGM_OPT_MASK (0x6000000U)
27548 #define FMUTEST_SMW_SETTING_OPTION2_TPGM_OPT_SHIFT (25U)
27549 /*! TPGM_OPT - Tpgm Option
27550  *  0b00..Fixed Tpgm for all shots, except post shot
27551  *  0b01..Increase Tpgm option by 1 for each loop until Tpgm reaches 4 usec
27552  *  0b10..Increase Tpgm option by 1 for each loop until Tpgm reaches 8 usec
27553  *  0b11..Unused
27554  */
27555 #define FMUTEST_SMW_SETTING_OPTION2_TPGM_OPT(x)  (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION2_TPGM_OPT_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_TPGM_OPT_MASK)
27556 
27557 #define FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_MASK (0x8000000U)
27558 #define FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_SHIFT (27U)
27559 /*! MASK0_OPT - MASK0_OPT
27560  *  0b0..Mask programmed bits passing PV until extra shot
27561  *  0b1..Always program bits even if they pass PV
27562  */
27563 #define FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_MASK)
27564 
27565 #define FMUTEST_SMW_SETTING_OPTION2_DIS_PRER_MASK (0x10000000U)
27566 #define FMUTEST_SMW_SETTING_OPTION2_DIS_PRER_SHIFT (28U)
27567 /*! DIS_PRER - Disable pre-PV Read before First Program Shot
27568  *  0b0..Enable pre-PV read before first program shot
27569  *  0b1..Disable pre-PV read before first program shot
27570  */
27571 #define FMUTEST_SMW_SETTING_OPTION2_DIS_PRER(x)  (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION2_DIS_PRER_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_DIS_PRER_MASK)
27572 /*! @} */
27573 
27574 /*! @name SMW_SETTING_OPTION3 - SMW Setting Option 3 Register */
27575 /*! @{ */
27576 
27577 #define FMUTEST_SMW_SETTING_OPTION3_HEM_WHV_CNTR_MASK (0xFFU)
27578 #define FMUTEST_SMW_SETTING_OPTION3_HEM_WHV_CNTR_SHIFT (0U)
27579 /*! HEM_WHV_CNTR - WHV_COUNTER for HEM-erase Cycle */
27580 #define FMUTEST_SMW_SETTING_OPTION3_HEM_WHV_CNTR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION3_HEM_WHV_CNTR_SHIFT)) & FMUTEST_SMW_SETTING_OPTION3_HEM_WHV_CNTR_MASK)
27581 
27582 #define FMUTEST_SMW_SETTING_OPTION3_HEM_MAX_ERS_MASK (0x1FF00U)
27583 #define FMUTEST_SMW_SETTING_OPTION3_HEM_MAX_ERS_SHIFT (8U)
27584 /*! HEM_MAX_ERS - HEM Max Erase Shot Count */
27585 #define FMUTEST_SMW_SETTING_OPTION3_HEM_MAX_ERS(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION3_HEM_MAX_ERS_SHIFT)) & FMUTEST_SMW_SETTING_OPTION3_HEM_MAX_ERS_MASK)
27586 /*! @} */
27587 
27588 /*! @name SMW_SMP_WHV_OPTION0 - SMW SMP WHV Option 0 Register */
27589 /*! @{ */
27590 
27591 #define FMUTEST_SMW_SMP_WHV_OPTION0_SMP_WHV_OPT0_MASK (0xFFFFFFFFU)
27592 #define FMUTEST_SMW_SMP_WHV_OPTION0_SMP_WHV_OPT0_SHIFT (0U)
27593 /*! SMP_WHV_OPT0 - Smart Program WHV Option Low */
27594 #define FMUTEST_SMW_SMP_WHV_OPTION0_SMP_WHV_OPT0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SMP_WHV_OPTION0_SMP_WHV_OPT0_SHIFT)) & FMUTEST_SMW_SMP_WHV_OPTION0_SMP_WHV_OPT0_MASK)
27595 /*! @} */
27596 
27597 /*! @name SMW_SME_WHV_OPTION0 - SMW SME WHV Option 0 Register */
27598 /*! @{ */
27599 
27600 #define FMUTEST_SMW_SME_WHV_OPTION0_SME_WHV_OPT0_MASK (0xFFFFFFFFU)
27601 #define FMUTEST_SMW_SME_WHV_OPTION0_SME_WHV_OPT0_SHIFT (0U)
27602 /*! SME_WHV_OPT0 - Smart Erase WHV Option Low */
27603 #define FMUTEST_SMW_SME_WHV_OPTION0_SME_WHV_OPT0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SME_WHV_OPTION0_SME_WHV_OPT0_SHIFT)) & FMUTEST_SMW_SME_WHV_OPTION0_SME_WHV_OPT0_MASK)
27604 /*! @} */
27605 
27606 /*! @name SMW_SETTING_OPTION1 - SMW Setting Option 1 Register */
27607 /*! @{ */
27608 
27609 #define FMUTEST_SMW_SETTING_OPTION1_TERS_CTRL0_MASK (0x7U)
27610 #define FMUTEST_SMW_SETTING_OPTION1_TERS_CTRL0_SHIFT (0U)
27611 /*! TERS_CTRL0 - Ters Control
27612  *  0b000..50 usec
27613  *  0b001..100 usec
27614  *  0b010..200 usec
27615  *  0b011..300 usec
27616  *  0b100..500 usec
27617  *  0b101..1 msec
27618  *  0b110..1.5 msec
27619  *  0b111..2 msec
27620  */
27621 #define FMUTEST_SMW_SETTING_OPTION1_TERS_CTRL0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION1_TERS_CTRL0_SHIFT)) & FMUTEST_SMW_SETTING_OPTION1_TERS_CTRL0_MASK)
27622 
27623 #define FMUTEST_SMW_SETTING_OPTION1_TPGM_CTRL_MASK (0x18U)
27624 #define FMUTEST_SMW_SETTING_OPTION1_TPGM_CTRL_SHIFT (3U)
27625 /*! TPGM_CTRL - Tpgm Control
27626  *  0b00..1 usec
27627  *  0b01..2 usec
27628  *  0b10..4 usec
27629  *  0b11..8 usec
27630  */
27631 #define FMUTEST_SMW_SETTING_OPTION1_TPGM_CTRL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION1_TPGM_CTRL_SHIFT)) & FMUTEST_SMW_SETTING_OPTION1_TPGM_CTRL_MASK)
27632 
27633 #define FMUTEST_SMW_SETTING_OPTION1_TNVS_CTRL_MASK (0xE0U)
27634 #define FMUTEST_SMW_SETTING_OPTION1_TNVS_CTRL_SHIFT (5U)
27635 /*! TNVS_CTRL - Tnvs Control
27636  *  0b000..5 usec
27637  *  0b001..8 usec
27638  *  0b010..11 usec
27639  *  0b011..14 usec
27640  *  0b100..17 usec
27641  *  0b101..20 usec
27642  *  0b110..23 usec
27643  *  0b111..26 usec
27644  */
27645 #define FMUTEST_SMW_SETTING_OPTION1_TNVS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION1_TNVS_CTRL_SHIFT)) & FMUTEST_SMW_SETTING_OPTION1_TNVS_CTRL_MASK)
27646 
27647 #define FMUTEST_SMW_SETTING_OPTION1_TNVH_CTRL_MASK (0x700U)
27648 #define FMUTEST_SMW_SETTING_OPTION1_TNVH_CTRL_SHIFT (8U)
27649 /*! TNVH_CTRL - Tnvh Control
27650  *  0b000..2 usec
27651  *  0b001..2.5 usec
27652  *  0b010..3 usec
27653  *  0b011..3.5 usec
27654  *  0b100..4 usec
27655  *  0b101..4.5 usec
27656  *  0b110..5 usec
27657  *  0b111..5.5 usec
27658  */
27659 #define FMUTEST_SMW_SETTING_OPTION1_TNVH_CTRL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION1_TNVH_CTRL_SHIFT)) & FMUTEST_SMW_SETTING_OPTION1_TNVH_CTRL_MASK)
27660 
27661 #define FMUTEST_SMW_SETTING_OPTION1_TPGS_CTRL_MASK (0x3800U)
27662 #define FMUTEST_SMW_SETTING_OPTION1_TPGS_CTRL_SHIFT (11U)
27663 /*! TPGS_CTRL - Tpgs Control
27664  *  0b000..1 usec
27665  *  0b001..2 usec
27666  *  0b010..3 usec
27667  *  0b011..4 usec
27668  *  0b100..5 usec
27669  *  0b101..6 usec
27670  *  0b110..7 usec
27671  *  0b111..8 usec
27672  */
27673 #define FMUTEST_SMW_SETTING_OPTION1_TPGS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION1_TPGS_CTRL_SHIFT)) & FMUTEST_SMW_SETTING_OPTION1_TPGS_CTRL_MASK)
27674 
27675 #define FMUTEST_SMW_SETTING_OPTION1_MAX_ERASE_MASK (0x7FC000U)
27676 #define FMUTEST_SMW_SETTING_OPTION1_MAX_ERASE_SHIFT (14U)
27677 /*! MAX_ERASE - Number of Erase Shots */
27678 #define FMUTEST_SMW_SETTING_OPTION1_MAX_ERASE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION1_MAX_ERASE_SHIFT)) & FMUTEST_SMW_SETTING_OPTION1_MAX_ERASE_MASK)
27679 
27680 #define FMUTEST_SMW_SETTING_OPTION1_MAX_PROG_MASK (0xF800000U)
27681 #define FMUTEST_SMW_SETTING_OPTION1_MAX_PROG_SHIFT (23U)
27682 /*! MAX_PROG - Number of Program Shots */
27683 #define FMUTEST_SMW_SETTING_OPTION1_MAX_PROG(x)  (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION1_MAX_PROG_SHIFT)) & FMUTEST_SMW_SETTING_OPTION1_MAX_PROG_MASK)
27684 /*! @} */
27685 
27686 /*! @name SMW_SMP_WHV_OPTION1 - SMW SMP WHV Option 1 Register */
27687 /*! @{ */
27688 
27689 #define FMUTEST_SMW_SMP_WHV_OPTION1_SMP_WHV_OPT1_MASK (0xFFFFFFFFU)
27690 #define FMUTEST_SMW_SMP_WHV_OPTION1_SMP_WHV_OPT1_SHIFT (0U)
27691 /*! SMP_WHV_OPT1 - Smart Program WHV Option High */
27692 #define FMUTEST_SMW_SMP_WHV_OPTION1_SMP_WHV_OPT1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SMP_WHV_OPTION1_SMP_WHV_OPT1_SHIFT)) & FMUTEST_SMW_SMP_WHV_OPTION1_SMP_WHV_OPT1_MASK)
27693 /*! @} */
27694 
27695 /*! @name SMW_SME_WHV_OPTION1 - SMW SME WHV Option 1 Register */
27696 /*! @{ */
27697 
27698 #define FMUTEST_SMW_SME_WHV_OPTION1_SME_WHV_OPT1_MASK (0xFFFFFFFFU)
27699 #define FMUTEST_SMW_SME_WHV_OPTION1_SME_WHV_OPT1_SHIFT (0U)
27700 /*! SME_WHV_OPT1 - Smart Erase WHV Option High */
27701 #define FMUTEST_SMW_SME_WHV_OPTION1_SME_WHV_OPT1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SME_WHV_OPTION1_SME_WHV_OPT1_SHIFT)) & FMUTEST_SMW_SME_WHV_OPTION1_SME_WHV_OPT1_MASK)
27702 /*! @} */
27703 
27704 /*! @name REPAIR0_0 - FMU Repair 0 Block 0 Register */
27705 /*! @{ */
27706 
27707 #define FMUTEST_REPAIR0_0_RDIS0_0_MASK           (0x1U)
27708 #define FMUTEST_REPAIR0_0_RDIS0_0_SHIFT          (0U)
27709 /*! RDIS0_0 - RDIS0_0
27710  *  0b0..Repair address is valid
27711  *  0b1..Repair address is not valid
27712  */
27713 #define FMUTEST_REPAIR0_0_RDIS0_0(x)             (((uint32_t)(((uint32_t)(x)) << FMUTEST_REPAIR0_0_RDIS0_0_SHIFT)) & FMUTEST_REPAIR0_0_RDIS0_0_MASK)
27714 
27715 #define FMUTEST_REPAIR0_0_RADR0_0_MASK           (0x1FEU)
27716 #define FMUTEST_REPAIR0_0_RADR0_0_SHIFT          (1U)
27717 /*! RADR0_0 - RADR0_0 */
27718 #define FMUTEST_REPAIR0_0_RADR0_0(x)             (((uint32_t)(((uint32_t)(x)) << FMUTEST_REPAIR0_0_RADR0_0_SHIFT)) & FMUTEST_REPAIR0_0_RADR0_0_MASK)
27719 /*! @} */
27720 
27721 /*! @name REPAIR0_1 - FMU Repair 1 Block 0 Register */
27722 /*! @{ */
27723 
27724 #define FMUTEST_REPAIR0_1_RDIS0_1_MASK           (0x1U)
27725 #define FMUTEST_REPAIR0_1_RDIS0_1_SHIFT          (0U)
27726 /*! RDIS0_1 - RDIS0_1
27727  *  0b0..Repair address is valid
27728  *  0b1..Repair address is not valid
27729  */
27730 #define FMUTEST_REPAIR0_1_RDIS0_1(x)             (((uint32_t)(((uint32_t)(x)) << FMUTEST_REPAIR0_1_RDIS0_1_SHIFT)) & FMUTEST_REPAIR0_1_RDIS0_1_MASK)
27731 
27732 #define FMUTEST_REPAIR0_1_RADR0_1_MASK           (0x1FEU)
27733 #define FMUTEST_REPAIR0_1_RADR0_1_SHIFT          (1U)
27734 /*! RADR0_1 - RADR0_1 */
27735 #define FMUTEST_REPAIR0_1_RADR0_1(x)             (((uint32_t)(((uint32_t)(x)) << FMUTEST_REPAIR0_1_RADR0_1_SHIFT)) & FMUTEST_REPAIR0_1_RADR0_1_MASK)
27736 /*! @} */
27737 
27738 /*! @name REPAIR1_0 - FMU Repair 0 Block 1 Register */
27739 /*! @{ */
27740 
27741 #define FMUTEST_REPAIR1_0_RDIS1_0_MASK           (0x1U)
27742 #define FMUTEST_REPAIR1_0_RDIS1_0_SHIFT          (0U)
27743 /*! RDIS1_0 - RDIS1_0
27744  *  0b0..Repair address is valid
27745  *  0b1..Repair address is not valid
27746  */
27747 #define FMUTEST_REPAIR1_0_RDIS1_0(x)             (((uint32_t)(((uint32_t)(x)) << FMUTEST_REPAIR1_0_RDIS1_0_SHIFT)) & FMUTEST_REPAIR1_0_RDIS1_0_MASK)
27748 
27749 #define FMUTEST_REPAIR1_0_RADR1_0_MASK           (0x1FEU)
27750 #define FMUTEST_REPAIR1_0_RADR1_0_SHIFT          (1U)
27751 /*! RADR1_0 - RADR1_0 */
27752 #define FMUTEST_REPAIR1_0_RADR1_0(x)             (((uint32_t)(((uint32_t)(x)) << FMUTEST_REPAIR1_0_RADR1_0_SHIFT)) & FMUTEST_REPAIR1_0_RADR1_0_MASK)
27753 /*! @} */
27754 
27755 /*! @name REPAIR1_1 - FMU Repair 1 Block 1 Register */
27756 /*! @{ */
27757 
27758 #define FMUTEST_REPAIR1_1_RDIS1_1_MASK           (0x1U)
27759 #define FMUTEST_REPAIR1_1_RDIS1_1_SHIFT          (0U)
27760 /*! RDIS1_1 - RDIS1_1
27761  *  0b0..Repair address is valid
27762  *  0b1..Repair address is not valid
27763  */
27764 #define FMUTEST_REPAIR1_1_RDIS1_1(x)             (((uint32_t)(((uint32_t)(x)) << FMUTEST_REPAIR1_1_RDIS1_1_SHIFT)) & FMUTEST_REPAIR1_1_RDIS1_1_MASK)
27765 
27766 #define FMUTEST_REPAIR1_1_RADR1_1_MASK           (0x1FEU)
27767 #define FMUTEST_REPAIR1_1_RADR1_1_SHIFT          (1U)
27768 /*! RADR1_1 - RADR1_1 */
27769 #define FMUTEST_REPAIR1_1_RADR1_1(x)             (((uint32_t)(((uint32_t)(x)) << FMUTEST_REPAIR1_1_RADR1_1_SHIFT)) & FMUTEST_REPAIR1_1_RADR1_1_MASK)
27770 /*! @} */
27771 
27772 /*! @name SMW_HB_SIGNALS - SMW HB Signals Register */
27773 /*! @{ */
27774 
27775 #define FMUTEST_SMW_HB_SIGNALS_SMW_ARRAY_MASK    (0x7U)
27776 #define FMUTEST_SMW_HB_SIGNALS_SMW_ARRAY_SHIFT   (0U)
27777 /*! SMW_ARRAY - SMW Region Select
27778  *  0b000..Main array
27779  *  0b001..IFR space only or main (and REDEN space) with IFR space for mass erase
27780  *  0b010..IFR1 space
27781  *  0b100..REDEN space
27782  */
27783 #define FMUTEST_SMW_HB_SIGNALS_SMW_ARRAY(x)      (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_HB_SIGNALS_SMW_ARRAY_SHIFT)) & FMUTEST_SMW_HB_SIGNALS_SMW_ARRAY_MASK)
27784 
27785 #define FMUTEST_SMW_HB_SIGNALS_USER_IFREN1_MASK  (0x8U)
27786 #define FMUTEST_SMW_HB_SIGNALS_USER_IFREN1_SHIFT (3U)
27787 /*! USER_IFREN1 - IFR1 Enable
27788  *  0b0..IFREN1 input to the flash array is driven LOW
27789  *  0b1..IFREN1 input to the flash array is driven HIGH
27790  */
27791 #define FMUTEST_SMW_HB_SIGNALS_USER_IFREN1(x)    (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_HB_SIGNALS_USER_IFREN1_SHIFT)) & FMUTEST_SMW_HB_SIGNALS_USER_IFREN1_MASK)
27792 
27793 #define FMUTEST_SMW_HB_SIGNALS_USER_PV_MASK      (0x10U)
27794 #define FMUTEST_SMW_HB_SIGNALS_USER_PV_SHIFT     (4U)
27795 /*! USER_PV - Program Verify
27796  *  0b0..PV input to the flash array is driven LOW
27797  *  0b1..PV input to the flash array is driven HIGH
27798  */
27799 #define FMUTEST_SMW_HB_SIGNALS_USER_PV(x)        (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_HB_SIGNALS_USER_PV_SHIFT)) & FMUTEST_SMW_HB_SIGNALS_USER_PV_MASK)
27800 
27801 #define FMUTEST_SMW_HB_SIGNALS_USER_EV_MASK      (0x20U)
27802 #define FMUTEST_SMW_HB_SIGNALS_USER_EV_SHIFT     (5U)
27803 /*! USER_EV - Erase Verify
27804  *  0b0..EV input to the flash array is driven LOW
27805  *  0b1..EV input to the flash array is driven HIGH
27806  */
27807 #define FMUTEST_SMW_HB_SIGNALS_USER_EV(x)        (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_HB_SIGNALS_USER_EV_SHIFT)) & FMUTEST_SMW_HB_SIGNALS_USER_EV_MASK)
27808 
27809 #define FMUTEST_SMW_HB_SIGNALS_USER_IFREN_MASK   (0x40U)
27810 #define FMUTEST_SMW_HB_SIGNALS_USER_IFREN_SHIFT  (6U)
27811 /*! USER_IFREN - IFR Enable
27812  *  0b0..IFREN input to the flash array is driven LOW
27813  *  0b1..IFREN input to the flash array is driven HIGH
27814  */
27815 #define FMUTEST_SMW_HB_SIGNALS_USER_IFREN(x)     (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_HB_SIGNALS_USER_IFREN_SHIFT)) & FMUTEST_SMW_HB_SIGNALS_USER_IFREN_MASK)
27816 
27817 #define FMUTEST_SMW_HB_SIGNALS_USER_REDEN_MASK   (0x80U)
27818 #define FMUTEST_SMW_HB_SIGNALS_USER_REDEN_SHIFT  (7U)
27819 /*! USER_REDEN - Repair Read Enable
27820  *  0b0..REDEN input to the flash array is driven LOW
27821  *  0b1..REDEN input to the flash array is driven HIGH
27822  */
27823 #define FMUTEST_SMW_HB_SIGNALS_USER_REDEN(x)     (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_HB_SIGNALS_USER_REDEN_SHIFT)) & FMUTEST_SMW_HB_SIGNALS_USER_REDEN_MASK)
27824 
27825 #define FMUTEST_SMW_HB_SIGNALS_USER_HEM_MASK     (0x100U)
27826 #define FMUTEST_SMW_HB_SIGNALS_USER_HEM_SHIFT    (8U)
27827 /*! USER_HEM - High Endurance Enable
27828  *  0b0..HEM input to SMW / BIST PIN_CTRL[24] is driven LOW
27829  *  0b1..HEM input to SMW / BIST PIN_CTRL[24] is driven HIGH
27830  */
27831 #define FMUTEST_SMW_HB_SIGNALS_USER_HEM(x)       (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_HB_SIGNALS_USER_HEM_SHIFT)) & FMUTEST_SMW_HB_SIGNALS_USER_HEM_MASK)
27832 /*! @} */
27833 
27834 /*! @name BIST_DUMP_CTRL - BIST Datadump Control Register */
27835 /*! @{ */
27836 
27837 #define FMUTEST_BIST_DUMP_CTRL_BIST_DONE_MASK    (0x10000U)
27838 #define FMUTEST_BIST_DUMP_CTRL_BIST_DONE_SHIFT   (16U)
27839 /*! BIST_DONE - BIST Done
27840  *  0b0..The BIST (or data dump) is running
27841  *  0b1..The BIST (or data dump) has completed
27842  */
27843 #define FMUTEST_BIST_DUMP_CTRL_BIST_DONE(x)      (((uint32_t)(((uint32_t)(x)) << FMUTEST_BIST_DUMP_CTRL_BIST_DONE_SHIFT)) & FMUTEST_BIST_DUMP_CTRL_BIST_DONE_MASK)
27844 
27845 #define FMUTEST_BIST_DUMP_CTRL_BIST_FAIL_MASK    (0x20000U)
27846 #define FMUTEST_BIST_DUMP_CTRL_BIST_FAIL_SHIFT   (17U)
27847 /*! BIST_FAIL - BIST Fail
27848  *  0b0..The last BIST operation completed successfully (or could not fail)
27849  *  0b1..The last BIST operation failed
27850  */
27851 #define FMUTEST_BIST_DUMP_CTRL_BIST_FAIL(x)      (((uint32_t)(((uint32_t)(x)) << FMUTEST_BIST_DUMP_CTRL_BIST_FAIL_SHIFT)) & FMUTEST_BIST_DUMP_CTRL_BIST_FAIL_MASK)
27852 
27853 #define FMUTEST_BIST_DUMP_CTRL_DATADUMP_MASK     (0x40000U)
27854 #define FMUTEST_BIST_DUMP_CTRL_DATADUMP_SHIFT    (18U)
27855 /*! DATADUMP - Data Dump Enable */
27856 #define FMUTEST_BIST_DUMP_CTRL_DATADUMP(x)       (((uint32_t)(((uint32_t)(x)) << FMUTEST_BIST_DUMP_CTRL_DATADUMP_SHIFT)) & FMUTEST_BIST_DUMP_CTRL_DATADUMP_MASK)
27857 
27858 #define FMUTEST_BIST_DUMP_CTRL_DATADUMP_TRIG_MASK (0x80000U)
27859 #define FMUTEST_BIST_DUMP_CTRL_DATADUMP_TRIG_SHIFT (19U)
27860 /*! DATADUMP_TRIG - Data Dump Trigger */
27861 #define FMUTEST_BIST_DUMP_CTRL_DATADUMP_TRIG(x)  (((uint32_t)(((uint32_t)(x)) << FMUTEST_BIST_DUMP_CTRL_DATADUMP_TRIG_SHIFT)) & FMUTEST_BIST_DUMP_CTRL_DATADUMP_TRIG_MASK)
27862 
27863 #define FMUTEST_BIST_DUMP_CTRL_DATADUMP_PATT_MASK (0x300000U)
27864 #define FMUTEST_BIST_DUMP_CTRL_DATADUMP_PATT_SHIFT (20U)
27865 /*! DATADUMP_PATT - Data Dump Pattern Select
27866  *  0b00..All ones
27867  *  0b01..All zeroes
27868  *  0b10..Checkerboard
27869  *  0b11..Inverse checkerboard
27870  */
27871 #define FMUTEST_BIST_DUMP_CTRL_DATADUMP_PATT(x)  (((uint32_t)(((uint32_t)(x)) << FMUTEST_BIST_DUMP_CTRL_DATADUMP_PATT_SHIFT)) & FMUTEST_BIST_DUMP_CTRL_DATADUMP_PATT_MASK)
27872 
27873 #define FMUTEST_BIST_DUMP_CTRL_DATADUMP_MRGEN_MASK (0x400000U)
27874 #define FMUTEST_BIST_DUMP_CTRL_DATADUMP_MRGEN_SHIFT (22U)
27875 /*! DATADUMP_MRGEN - Data Dump Margin Enable
27876  *  0b0..Normal read pulse shape
27877  *  0b1..Margin read pulse shape
27878  */
27879 #define FMUTEST_BIST_DUMP_CTRL_DATADUMP_MRGEN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_BIST_DUMP_CTRL_DATADUMP_MRGEN_SHIFT)) & FMUTEST_BIST_DUMP_CTRL_DATADUMP_MRGEN_MASK)
27880 
27881 #define FMUTEST_BIST_DUMP_CTRL_DATADUMP_MRGTYPE_MASK (0x800000U)
27882 #define FMUTEST_BIST_DUMP_CTRL_DATADUMP_MRGTYPE_SHIFT (23U)
27883 /*! DATADUMP_MRGTYPE - Data Dump Margin Type
27884  *  0b0..DIN method used
27885  *  0b1..TM method used
27886  */
27887 #define FMUTEST_BIST_DUMP_CTRL_DATADUMP_MRGTYPE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_BIST_DUMP_CTRL_DATADUMP_MRGTYPE_SHIFT)) & FMUTEST_BIST_DUMP_CTRL_DATADUMP_MRGTYPE_MASK)
27888 /*! @} */
27889 
27890 /*! @name ATX_PIN_CTRL - ATX Pin Control Register */
27891 /*! @{ */
27892 
27893 #define FMUTEST_ATX_PIN_CTRL_TM_TO_ATX_MASK      (0xFFU)
27894 #define FMUTEST_ATX_PIN_CTRL_TM_TO_ATX_SHIFT     (0U)
27895 /*! TM_TO_ATX - TM to ATX
27896  *  0b00000001..TM[0] to ATX0
27897  *  0b00000010..TM[1] to ATX0
27898  *  0b00000100..TM[2] to ATX0
27899  *  0b00001000..TM[3] to ATX0
27900  *  0b00010000..TM[0] to ATX1
27901  *  0b00100000..TM[1] to ATX1
27902  *  0b01000000..TM[2] to ATX1
27903  *  0b10000000..TM[3] to ATX1
27904  */
27905 #define FMUTEST_ATX_PIN_CTRL_TM_TO_ATX(x)        (((uint32_t)(((uint32_t)(x)) << FMUTEST_ATX_PIN_CTRL_TM_TO_ATX_SHIFT)) & FMUTEST_ATX_PIN_CTRL_TM_TO_ATX_MASK)
27906 /*! @} */
27907 
27908 /*! @name FAILCNT - Fail Count Register */
27909 /*! @{ */
27910 
27911 #define FMUTEST_FAILCNT_FAILCNT_MASK             (0xFFFFFFFFU)
27912 #define FMUTEST_FAILCNT_FAILCNT_SHIFT            (0U)
27913 /*! FAILCNT - Fail Count */
27914 #define FMUTEST_FAILCNT_FAILCNT(x)               (((uint32_t)(((uint32_t)(x)) << FMUTEST_FAILCNT_FAILCNT_SHIFT)) & FMUTEST_FAILCNT_FAILCNT_MASK)
27915 /*! @} */
27916 
27917 /*! @name PGM_PULSE_CNT0 - Block 0 Program Pulse Count Register */
27918 /*! @{ */
27919 
27920 #define FMUTEST_PGM_PULSE_CNT0_PGM_CNT0_MASK     (0xFFFFFFFFU)
27921 #define FMUTEST_PGM_PULSE_CNT0_PGM_CNT0_SHIFT    (0U)
27922 /*! PGM_CNT0 - Program Pulse Count */
27923 #define FMUTEST_PGM_PULSE_CNT0_PGM_CNT0(x)       (((uint32_t)(((uint32_t)(x)) << FMUTEST_PGM_PULSE_CNT0_PGM_CNT0_SHIFT)) & FMUTEST_PGM_PULSE_CNT0_PGM_CNT0_MASK)
27924 /*! @} */
27925 
27926 /*! @name PGM_PULSE_CNT1 - Block 1 Program Pulse Count Register */
27927 /*! @{ */
27928 
27929 #define FMUTEST_PGM_PULSE_CNT1_PGM_CNT1_MASK     (0xFFFFFFFFU)
27930 #define FMUTEST_PGM_PULSE_CNT1_PGM_CNT1_SHIFT    (0U)
27931 /*! PGM_CNT1 - Program Pulse Count */
27932 #define FMUTEST_PGM_PULSE_CNT1_PGM_CNT1(x)       (((uint32_t)(((uint32_t)(x)) << FMUTEST_PGM_PULSE_CNT1_PGM_CNT1_SHIFT)) & FMUTEST_PGM_PULSE_CNT1_PGM_CNT1_MASK)
27933 /*! @} */
27934 
27935 /*! @name ERS_PULSE_CNT - Erase Pulse Count Register */
27936 /*! @{ */
27937 
27938 #define FMUTEST_ERS_PULSE_CNT_ERS_CNT0_MASK      (0xFFFFU)
27939 #define FMUTEST_ERS_PULSE_CNT_ERS_CNT0_SHIFT     (0U)
27940 /*! ERS_CNT0 - Block 0 Erase Pulse Count */
27941 #define FMUTEST_ERS_PULSE_CNT_ERS_CNT0(x)        (((uint32_t)(((uint32_t)(x)) << FMUTEST_ERS_PULSE_CNT_ERS_CNT0_SHIFT)) & FMUTEST_ERS_PULSE_CNT_ERS_CNT0_MASK)
27942 
27943 #define FMUTEST_ERS_PULSE_CNT_ERS_CNT1_MASK      (0xFFFF0000U)
27944 #define FMUTEST_ERS_PULSE_CNT_ERS_CNT1_SHIFT     (16U)
27945 /*! ERS_CNT1 - Block 1 Erase Pulse Count */
27946 #define FMUTEST_ERS_PULSE_CNT_ERS_CNT1(x)        (((uint32_t)(((uint32_t)(x)) << FMUTEST_ERS_PULSE_CNT_ERS_CNT1_SHIFT)) & FMUTEST_ERS_PULSE_CNT_ERS_CNT1_MASK)
27947 /*! @} */
27948 
27949 /*! @name MAX_PULSE_CNT - Maximum Pulse Count Register */
27950 /*! @{ */
27951 
27952 #define FMUTEST_MAX_PULSE_CNT_LAST_PCNT_MASK     (0x1FFU)
27953 #define FMUTEST_MAX_PULSE_CNT_LAST_PCNT_SHIFT    (0U)
27954 /*! LAST_PCNT - Last SMW Operation's Pulse Count */
27955 #define FMUTEST_MAX_PULSE_CNT_LAST_PCNT(x)       (((uint32_t)(((uint32_t)(x)) << FMUTEST_MAX_PULSE_CNT_LAST_PCNT_SHIFT)) & FMUTEST_MAX_PULSE_CNT_LAST_PCNT_MASK)
27956 
27957 #define FMUTEST_MAX_PULSE_CNT_MAX_ERS_CNT_MASK   (0x1FF0000U)
27958 #define FMUTEST_MAX_PULSE_CNT_MAX_ERS_CNT_SHIFT  (16U)
27959 /*! MAX_ERS_CNT - Maximum Erase Pulse Count */
27960 #define FMUTEST_MAX_PULSE_CNT_MAX_ERS_CNT(x)     (((uint32_t)(((uint32_t)(x)) << FMUTEST_MAX_PULSE_CNT_MAX_ERS_CNT_SHIFT)) & FMUTEST_MAX_PULSE_CNT_MAX_ERS_CNT_MASK)
27961 
27962 #define FMUTEST_MAX_PULSE_CNT_MAX_PGM_CNT_MASK   (0xF8000000U)
27963 #define FMUTEST_MAX_PULSE_CNT_MAX_PGM_CNT_SHIFT  (27U)
27964 /*! MAX_PGM_CNT - Maximum Program Pulse Count */
27965 #define FMUTEST_MAX_PULSE_CNT_MAX_PGM_CNT(x)     (((uint32_t)(((uint32_t)(x)) << FMUTEST_MAX_PULSE_CNT_MAX_PGM_CNT_SHIFT)) & FMUTEST_MAX_PULSE_CNT_MAX_PGM_CNT_MASK)
27966 /*! @} */
27967 
27968 /*! @name PORT_CTRL - Port Control Register */
27969 /*! @{ */
27970 
27971 #define FMUTEST_PORT_CTRL_BDONE_SEL_MASK         (0x3U)
27972 #define FMUTEST_PORT_CTRL_BDONE_SEL_SHIFT        (0U)
27973 /*! BDONE_SEL - BIST Done Select
27974  *  0b00..Select internal bist_done signal from current module instantiation
27975  *  0b01..Select ipt_bist_fail signal from current module instantiation
27976  *  0b10..Select ipt_bist_done signal from other module instantiation
27977  *  0b11..Select AND of internal bist_done signal from current module instantiation with ipt_bist_done signal from other module instantiation
27978  */
27979 #define FMUTEST_PORT_CTRL_BDONE_SEL(x)           (((uint32_t)(((uint32_t)(x)) << FMUTEST_PORT_CTRL_BDONE_SEL_SHIFT)) & FMUTEST_PORT_CTRL_BDONE_SEL_MASK)
27980 
27981 #define FMUTEST_PORT_CTRL_BSDO_SEL_MASK          (0xCU)
27982 #define FMUTEST_PORT_CTRL_BSDO_SEL_SHIFT         (2U)
27983 /*! BSDO_SEL - BIST Serial Data Output Select
27984  *  0b00..Select internal bist_sdo signal from current module instantiation
27985  *  0b01..Select ipt_bist_done signal from current module instantiation
27986  *  0b10..Select ipt_bist_sdo signal from other module instantiation
27987  *  0b11..Select ipt_bist_done signal from other module instantiation
27988  */
27989 #define FMUTEST_PORT_CTRL_BSDO_SEL(x)            (((uint32_t)(((uint32_t)(x)) << FMUTEST_PORT_CTRL_BSDO_SEL_SHIFT)) & FMUTEST_PORT_CTRL_BSDO_SEL_MASK)
27990 /*! @} */
27991 
27992 
27993 /*!
27994  * @}
27995  */ /* end of group FMUTEST_Register_Masks */
27996 
27997 
27998 /* FMUTEST - Peripheral instance base addresses */
27999 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
28000   /** Peripheral FMU0TEST base address */
28001   #define FMU0TEST_BASE                            (0x50043000u)
28002   /** Peripheral FMU0TEST base address */
28003   #define FMU0TEST_BASE_NS                         (0x40043000u)
28004   /** Peripheral FMU0TEST base pointer */
28005   #define FMU0TEST                                 ((FMUTEST_Type *)FMU0TEST_BASE)
28006   /** Peripheral FMU0TEST base pointer */
28007   #define FMU0TEST_NS                              ((FMUTEST_Type *)FMU0TEST_BASE_NS)
28008   /** Array initializer of FMUTEST peripheral base addresses */
28009   #define FMUTEST_BASE_ADDRS                       { FMU0TEST_BASE }
28010   /** Array initializer of FMUTEST peripheral base pointers */
28011   #define FMUTEST_BASE_PTRS                        { FMU0TEST }
28012   /** Array initializer of FMUTEST peripheral base addresses */
28013   #define FMUTEST_BASE_ADDRS_NS                    { FMU0TEST_BASE_NS }
28014   /** Array initializer of FMUTEST peripheral base pointers */
28015   #define FMUTEST_BASE_PTRS_NS                     { FMU0TEST_NS }
28016 #else
28017   /** Peripheral FMU0TEST base address */
28018   #define FMU0TEST_BASE                            (0x40043000u)
28019   /** Peripheral FMU0TEST base pointer */
28020   #define FMU0TEST                                 ((FMUTEST_Type *)FMU0TEST_BASE)
28021   /** Array initializer of FMUTEST peripheral base addresses */
28022   #define FMUTEST_BASE_ADDRS                       { FMU0TEST_BASE }
28023   /** Array initializer of FMUTEST peripheral base pointers */
28024   #define FMUTEST_BASE_PTRS                        { FMU0TEST }
28025 #endif
28026 
28027 /*!
28028  * @}
28029  */ /* end of group FMUTEST_Peripheral_Access_Layer */
28030 
28031 
28032 /* ----------------------------------------------------------------------------
28033    -- FREQME Peripheral Access Layer
28034    ---------------------------------------------------------------------------- */
28035 
28036 /*!
28037  * @addtogroup FREQME_Peripheral_Access_Layer FREQME Peripheral Access Layer
28038  * @{
28039  */
28040 
28041 /** FREQME - Register Layout Typedef */
28042 typedef struct {
28043   union {                                          /* offset: 0x0 */
28044     __I  uint32_t CTRL_R;                            /**< Control (in Read mode), offset: 0x0 */
28045     __O  uint32_t CTRL_W;                            /**< Control (in Write mode), offset: 0x0 */
28046   };
28047   __IO uint32_t CTRLSTAT;                          /**< Control Status, offset: 0x4 */
28048   __IO uint32_t MIN;                               /**< Minimum, offset: 0x8 */
28049   __IO uint32_t MAX;                               /**< Maximum, offset: 0xC */
28050 } FREQME_Type;
28051 
28052 /* ----------------------------------------------------------------------------
28053    -- FREQME Register Masks
28054    ---------------------------------------------------------------------------- */
28055 
28056 /*!
28057  * @addtogroup FREQME_Register_Masks FREQME Register Masks
28058  * @{
28059  */
28060 
28061 /*! @name CTRL_R - Control (in Read mode) */
28062 /*! @{ */
28063 
28064 #define FREQME_CTRL_R_RESULT_MASK                (0x7FFFFFFFU)
28065 #define FREQME_CTRL_R_RESULT_SHIFT               (0U)
28066 #define FREQME_CTRL_R_RESULT(x)                  (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_R_RESULT_SHIFT)) & FREQME_CTRL_R_RESULT_MASK)
28067 
28068 #define FREQME_CTRL_R_MEASURE_IN_PROGRESS_MASK   (0x80000000U)
28069 #define FREQME_CTRL_R_MEASURE_IN_PROGRESS_SHIFT  (31U)
28070 /*! MEASURE_IN_PROGRESS - Measurement In Progress
28071  *  0b0..Complete
28072  *  0b1..In progress
28073  */
28074 #define FREQME_CTRL_R_MEASURE_IN_PROGRESS(x)     (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_R_MEASURE_IN_PROGRESS_SHIFT)) & FREQME_CTRL_R_MEASURE_IN_PROGRESS_MASK)
28075 /*! @} */
28076 
28077 /*! @name CTRL_W - Control (in Write mode) */
28078 /*! @{ */
28079 
28080 #define FREQME_CTRL_W_REF_SCALE_MASK             (0x1FU)
28081 #define FREQME_CTRL_W_REF_SCALE_SHIFT            (0U)
28082 /*! REF_SCALE - Reference Clock Scaling Factor */
28083 #define FREQME_CTRL_W_REF_SCALE(x)               (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_REF_SCALE_SHIFT)) & FREQME_CTRL_W_REF_SCALE_MASK)
28084 
28085 #define FREQME_CTRL_W_PULSE_MODE_MASK            (0x100U)
28086 #define FREQME_CTRL_W_PULSE_MODE_SHIFT           (8U)
28087 /*! PULSE_MODE - Pulse Width Measurement Mode Select
28088  *  0b0..Frequency Measurement mode
28089  *  0b1..Pulse Width Measurement mode
28090  */
28091 #define FREQME_CTRL_W_PULSE_MODE(x)              (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_PULSE_MODE_SHIFT)) & FREQME_CTRL_W_PULSE_MODE_MASK)
28092 
28093 #define FREQME_CTRL_W_PULSE_POL_MASK             (0x200U)
28094 #define FREQME_CTRL_W_PULSE_POL_SHIFT            (9U)
28095 /*! PULSE_POL - Pulse Polarity
28096  *  0b0..High period
28097  *  0b1..Low period
28098  */
28099 #define FREQME_CTRL_W_PULSE_POL(x)               (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_PULSE_POL_SHIFT)) & FREQME_CTRL_W_PULSE_POL_MASK)
28100 
28101 #define FREQME_CTRL_W_LT_MIN_INT_EN_MASK         (0x1000U)
28102 #define FREQME_CTRL_W_LT_MIN_INT_EN_SHIFT        (12U)
28103 /*! LT_MIN_INT_EN - Less Than Minimum Interrupt Enable
28104  *  0b0..Disable
28105  *  0b1..Enable
28106  */
28107 #define FREQME_CTRL_W_LT_MIN_INT_EN(x)           (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_LT_MIN_INT_EN_SHIFT)) & FREQME_CTRL_W_LT_MIN_INT_EN_MASK)
28108 
28109 #define FREQME_CTRL_W_GT_MAX_INT_EN_MASK         (0x2000U)
28110 #define FREQME_CTRL_W_GT_MAX_INT_EN_SHIFT        (13U)
28111 /*! GT_MAX_INT_EN - Greater Than Maximum Interrupt Enable
28112  *  0b0..Disable
28113  *  0b1..Enable
28114  */
28115 #define FREQME_CTRL_W_GT_MAX_INT_EN(x)           (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_GT_MAX_INT_EN_SHIFT)) & FREQME_CTRL_W_GT_MAX_INT_EN_MASK)
28116 
28117 #define FREQME_CTRL_W_RESULT_READY_INT_EN_MASK   (0x4000U)
28118 #define FREQME_CTRL_W_RESULT_READY_INT_EN_SHIFT  (14U)
28119 /*! RESULT_READY_INT_EN - Result Ready Interrupt Enable
28120  *  0b0..Disable
28121  *  0b1..Enable
28122  */
28123 #define FREQME_CTRL_W_RESULT_READY_INT_EN(x)     (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_RESULT_READY_INT_EN_SHIFT)) & FREQME_CTRL_W_RESULT_READY_INT_EN_MASK)
28124 
28125 #define FREQME_CTRL_W_CONTINUOUS_MODE_EN_MASK    (0x40000000U)
28126 #define FREQME_CTRL_W_CONTINUOUS_MODE_EN_SHIFT   (30U)
28127 /*! CONTINUOUS_MODE_EN - Continuous Mode Enable
28128  *  0b0..Disable
28129  *  0b1..Enable
28130  */
28131 #define FREQME_CTRL_W_CONTINUOUS_MODE_EN(x)      (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_CONTINUOUS_MODE_EN_SHIFT)) & FREQME_CTRL_W_CONTINUOUS_MODE_EN_MASK)
28132 
28133 #define FREQME_CTRL_W_MEASURE_IN_PROGRESS_MASK   (0x80000000U)
28134 #define FREQME_CTRL_W_MEASURE_IN_PROGRESS_SHIFT  (31U)
28135 /*! MEASURE_IN_PROGRESS - Measurement In Progress
28136  *  0b0..Terminates measurement
28137  *  0b1..Initiates measurement
28138  */
28139 #define FREQME_CTRL_W_MEASURE_IN_PROGRESS(x)     (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_MEASURE_IN_PROGRESS_SHIFT)) & FREQME_CTRL_W_MEASURE_IN_PROGRESS_MASK)
28140 /*! @} */
28141 
28142 /*! @name CTRLSTAT - Control Status */
28143 /*! @{ */
28144 
28145 #define FREQME_CTRLSTAT_REF_SCALE_MASK           (0x1FU)
28146 #define FREQME_CTRLSTAT_REF_SCALE_SHIFT          (0U)
28147 /*! REF_SCALE - Reference Scale */
28148 #define FREQME_CTRLSTAT_REF_SCALE(x)             (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_REF_SCALE_SHIFT)) & FREQME_CTRLSTAT_REF_SCALE_MASK)
28149 
28150 #define FREQME_CTRLSTAT_PULSE_MODE_MASK          (0x100U)
28151 #define FREQME_CTRLSTAT_PULSE_MODE_SHIFT         (8U)
28152 /*! PULSE_MODE - Pulse Mode
28153  *  0b0..Frequency Measurement mode
28154  *  0b1..Pulse Width Measurement mode
28155  */
28156 #define FREQME_CTRLSTAT_PULSE_MODE(x)            (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_PULSE_MODE_SHIFT)) & FREQME_CTRLSTAT_PULSE_MODE_MASK)
28157 
28158 #define FREQME_CTRLSTAT_PULSE_POL_MASK           (0x200U)
28159 #define FREQME_CTRLSTAT_PULSE_POL_SHIFT          (9U)
28160 /*! PULSE_POL - Pulse Polarity
28161  *  0b0..High period
28162  *  0b1..Low period
28163  */
28164 #define FREQME_CTRLSTAT_PULSE_POL(x)             (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_PULSE_POL_SHIFT)) & FREQME_CTRLSTAT_PULSE_POL_MASK)
28165 
28166 #define FREQME_CTRLSTAT_LT_MIN_INT_EN_MASK       (0x1000U)
28167 #define FREQME_CTRLSTAT_LT_MIN_INT_EN_SHIFT      (12U)
28168 /*! LT_MIN_INT_EN - Less Than Minimum Interrupt Enable
28169  *  0b0..Disabled
28170  *  0b1..Enabled
28171  */
28172 #define FREQME_CTRLSTAT_LT_MIN_INT_EN(x)         (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_LT_MIN_INT_EN_SHIFT)) & FREQME_CTRLSTAT_LT_MIN_INT_EN_MASK)
28173 
28174 #define FREQME_CTRLSTAT_GT_MAX_INT_EN_MASK       (0x2000U)
28175 #define FREQME_CTRLSTAT_GT_MAX_INT_EN_SHIFT      (13U)
28176 /*! GT_MAX_INT_EN - Greater Than Maximum Interrupt Enable
28177  *  0b0..Disabled
28178  *  0b1..Enabled
28179  */
28180 #define FREQME_CTRLSTAT_GT_MAX_INT_EN(x)         (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_GT_MAX_INT_EN_SHIFT)) & FREQME_CTRLSTAT_GT_MAX_INT_EN_MASK)
28181 
28182 #define FREQME_CTRLSTAT_RESULT_READY_INT_EN_MASK (0x4000U)
28183 #define FREQME_CTRLSTAT_RESULT_READY_INT_EN_SHIFT (14U)
28184 /*! RESULT_READY_INT_EN - Result Ready Interrupt Enable
28185  *  0b0..Disabled
28186  *  0b1..Enabled
28187  */
28188 #define FREQME_CTRLSTAT_RESULT_READY_INT_EN(x)   (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_RESULT_READY_INT_EN_SHIFT)) & FREQME_CTRLSTAT_RESULT_READY_INT_EN_MASK)
28189 
28190 #define FREQME_CTRLSTAT_LT_MIN_STAT_MASK         (0x1000000U)
28191 #define FREQME_CTRLSTAT_LT_MIN_STAT_SHIFT        (24U)
28192 /*! LT_MIN_STAT - Less Than Minimum Results Status
28193  *  0b0..Greater than MIN[MIN_VALUE]
28194  *  0b1..Less than MIN[MIN_VALUE]
28195  */
28196 #define FREQME_CTRLSTAT_LT_MIN_STAT(x)           (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_LT_MIN_STAT_SHIFT)) & FREQME_CTRLSTAT_LT_MIN_STAT_MASK)
28197 
28198 #define FREQME_CTRLSTAT_GT_MAX_STAT_MASK         (0x2000000U)
28199 #define FREQME_CTRLSTAT_GT_MAX_STAT_SHIFT        (25U)
28200 /*! GT_MAX_STAT - Greater Than Maximum Result Status
28201  *  0b0..Less than MAX[MAX_VALUE]
28202  *  0b1..Greater than MAX[MAX_VALUE]
28203  */
28204 #define FREQME_CTRLSTAT_GT_MAX_STAT(x)           (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_GT_MAX_STAT_SHIFT)) & FREQME_CTRLSTAT_GT_MAX_STAT_MASK)
28205 
28206 #define FREQME_CTRLSTAT_RESULT_READY_STAT_MASK   (0x4000000U)
28207 #define FREQME_CTRLSTAT_RESULT_READY_STAT_SHIFT  (26U)
28208 /*! RESULT_READY_STAT - Result Ready Status
28209  *  0b0..Not complete
28210  *  0b1..Complete
28211  */
28212 #define FREQME_CTRLSTAT_RESULT_READY_STAT(x)     (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_RESULT_READY_STAT_SHIFT)) & FREQME_CTRLSTAT_RESULT_READY_STAT_MASK)
28213 
28214 #define FREQME_CTRLSTAT_CONTINUOUS_MODE_EN_MASK  (0x40000000U)
28215 #define FREQME_CTRLSTAT_CONTINUOUS_MODE_EN_SHIFT (30U)
28216 /*! CONTINUOUS_MODE_EN - Continuous Mode Enable Status
28217  *  0b0..Disabled
28218  *  0b1..Enabled
28219  */
28220 #define FREQME_CTRLSTAT_CONTINUOUS_MODE_EN(x)    (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_CONTINUOUS_MODE_EN_SHIFT)) & FREQME_CTRLSTAT_CONTINUOUS_MODE_EN_MASK)
28221 
28222 #define FREQME_CTRLSTAT_MEASURE_IN_PROGRESS_MASK (0x80000000U)
28223 #define FREQME_CTRLSTAT_MEASURE_IN_PROGRESS_SHIFT (31U)
28224 /*! MEASURE_IN_PROGRESS - Measurement in Progress Status
28225  *  0b0..Not in progress
28226  *  0b1..In progress
28227  */
28228 #define FREQME_CTRLSTAT_MEASURE_IN_PROGRESS(x)   (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_MEASURE_IN_PROGRESS_SHIFT)) & FREQME_CTRLSTAT_MEASURE_IN_PROGRESS_MASK)
28229 /*! @} */
28230 
28231 /*! @name MIN - Minimum */
28232 /*! @{ */
28233 
28234 #define FREQME_MIN_MIN_VALUE_MASK                (0x7FFFFFFFU)
28235 #define FREQME_MIN_MIN_VALUE_SHIFT               (0U)
28236 /*! MIN_VALUE - Minimum Value */
28237 #define FREQME_MIN_MIN_VALUE(x)                  (((uint32_t)(((uint32_t)(x)) << FREQME_MIN_MIN_VALUE_SHIFT)) & FREQME_MIN_MIN_VALUE_MASK)
28238 /*! @} */
28239 
28240 /*! @name MAX - Maximum */
28241 /*! @{ */
28242 
28243 #define FREQME_MAX_MAX_VALUE_MASK                (0x7FFFFFFFU)
28244 #define FREQME_MAX_MAX_VALUE_SHIFT               (0U)
28245 /*! MAX_VALUE - Maximum Value */
28246 #define FREQME_MAX_MAX_VALUE(x)                  (((uint32_t)(((uint32_t)(x)) << FREQME_MAX_MAX_VALUE_SHIFT)) & FREQME_MAX_MAX_VALUE_MASK)
28247 /*! @} */
28248 
28249 
28250 /*!
28251  * @}
28252  */ /* end of group FREQME_Register_Masks */
28253 
28254 
28255 /* FREQME - Peripheral instance base addresses */
28256 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
28257   /** Peripheral FREQME0 base address */
28258   #define FREQME0_BASE                             (0x50011000u)
28259   /** Peripheral FREQME0 base address */
28260   #define FREQME0_BASE_NS                          (0x40011000u)
28261   /** Peripheral FREQME0 base pointer */
28262   #define FREQME0                                  ((FREQME_Type *)FREQME0_BASE)
28263   /** Peripheral FREQME0 base pointer */
28264   #define FREQME0_NS                               ((FREQME_Type *)FREQME0_BASE_NS)
28265   /** Array initializer of FREQME peripheral base addresses */
28266   #define FREQME_BASE_ADDRS                        { FREQME0_BASE }
28267   /** Array initializer of FREQME peripheral base pointers */
28268   #define FREQME_BASE_PTRS                         { FREQME0 }
28269   /** Array initializer of FREQME peripheral base addresses */
28270   #define FREQME_BASE_ADDRS_NS                     { FREQME0_BASE_NS }
28271   /** Array initializer of FREQME peripheral base pointers */
28272   #define FREQME_BASE_PTRS_NS                      { FREQME0_NS }
28273 #else
28274   /** Peripheral FREQME0 base address */
28275   #define FREQME0_BASE                             (0x40011000u)
28276   /** Peripheral FREQME0 base pointer */
28277   #define FREQME0                                  ((FREQME_Type *)FREQME0_BASE)
28278   /** Array initializer of FREQME peripheral base addresses */
28279   #define FREQME_BASE_ADDRS                        { FREQME0_BASE }
28280   /** Array initializer of FREQME peripheral base pointers */
28281   #define FREQME_BASE_PTRS                         { FREQME0 }
28282 #endif
28283 /** Interrupt vectors for the FREQME peripheral type */
28284 #define FREQME_IRQS                              { Freqme_IRQn }
28285 
28286 /*!
28287  * @}
28288  */ /* end of group FREQME_Peripheral_Access_Layer */
28289 
28290 
28291 /* ----------------------------------------------------------------------------
28292    -- GDET Peripheral Access Layer
28293    ---------------------------------------------------------------------------- */
28294 
28295 /*!
28296  * @addtogroup GDET_Peripheral_Access_Layer GDET Peripheral Access Layer
28297  * @{
28298  */
28299 
28300 /** GDET - Register Layout Typedef */
28301 typedef struct {
28302   __IO uint32_t GDET_CONF_0;                       /**< GDET Configuration 0 Register, offset: 0x0 */
28303   __IO uint32_t GDET_CONF_1;                       /**< GDET Configuration 1 Register, offset: 0x4 */
28304   __IO uint32_t GDET_ENABLE1;                      /**< GDET Enable Register, offset: 0x8 */
28305   __IO uint32_t GDET_CONF_2;                       /**< GDET Configuration 2 Register, offset: 0xC */
28306   __IO uint32_t GDET_CONF_3;                       /**< GDET Configuration 3 Register, offset: 0x10 */
28307   __IO uint32_t GDET_CONF_4;                       /**< GDET Configuration 4 Register, offset: 0x14 */
28308   __IO uint32_t GDET_CONF_5;                       /**< GDET Configuration 5 Register, offset: 0x18 */
28309        uint8_t RESERVED_0[4004];
28310   __IO uint32_t GDET_RESET;                        /**< GDET Reset Register, offset: 0xFC0 */
28311   __IO uint32_t GDET_TEST;                         /**< GDET Test Register, offset: 0xFC4 */
28312        uint8_t RESERVED_1[4];
28313   __IO uint32_t GDET_DLY_CTRL;                     /**< GDET Delay Control Register, offset: 0xFCC */
28314 } GDET_Type;
28315 
28316 /* ----------------------------------------------------------------------------
28317    -- GDET Register Masks
28318    ---------------------------------------------------------------------------- */
28319 
28320 /*!
28321  * @addtogroup GDET_Register_Masks GDET Register Masks
28322  * @{
28323  */
28324 
28325 /*! @name GDET_CONF_0 - GDET Configuration 0 Register */
28326 /*! @{ */
28327 
28328 #define GDET_GDET_CONF_0_FIELD_3_0_MASK          (0xFU)
28329 #define GDET_GDET_CONF_0_FIELD_3_0_SHIFT         (0U)
28330 /*! FIELD_3_0 - GDET Configuration 0 Field 3_0 */
28331 #define GDET_GDET_CONF_0_FIELD_3_0(x)            (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_0_FIELD_3_0_SHIFT)) & GDET_GDET_CONF_0_FIELD_3_0_MASK)
28332 
28333 #define GDET_GDET_CONF_0_FIELD_3_0_MASK          (0xFU)
28334 #define GDET_GDET_CONF_0_FIELD_3_0_SHIFT         (0U)
28335 /*! field_3_0 - GDET configuration 0 Field 3_0 */
28336 #define GDET_GDET_CONF_0_FIELD_3_0(x)            (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_0_FIELD_3_0_SHIFT)) & GDET_GDET_CONF_0_FIELD_3_0_MASK)
28337 
28338 #define GDET_GDET_CONF_0_SBZ_MASK                (0x10U)
28339 #define GDET_GDET_CONF_0_SBZ_SHIFT               (4U)
28340 /*! SBZ - Should Be Left to Zero */
28341 #define GDET_GDET_CONF_0_SBZ(x)                  (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_0_SBZ_SHIFT)) & GDET_GDET_CONF_0_SBZ_MASK)
28342 
28343 #define GDET_GDET_CONF_0_SBZ_MASK                (0x10U)
28344 #define GDET_GDET_CONF_0_SBZ_SHIFT               (4U)
28345 /*! sbz - Should be left to zero */
28346 #define GDET_GDET_CONF_0_SBZ(x)                  (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_0_SBZ_SHIFT)) & GDET_GDET_CONF_0_SBZ_MASK)
28347 
28348 #define GDET_GDET_CONF_0_RFU_MASK                (0xFFFFFFE0U)
28349 #define GDET_GDET_CONF_0_RFU_SHIFT               (5U)
28350 /*! RFU - Reserved for Future Use */
28351 #define GDET_GDET_CONF_0_RFU(x)                  (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_0_RFU_SHIFT)) & GDET_GDET_CONF_0_RFU_MASK)
28352 
28353 #define GDET_GDET_CONF_0_RFU_MASK                (0xFFFFFFE0U)
28354 #define GDET_GDET_CONF_0_RFU_SHIFT               (5U)
28355 /*! rfu - Reserved for Future Use */
28356 #define GDET_GDET_CONF_0_RFU(x)                  (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_0_RFU_SHIFT)) & GDET_GDET_CONF_0_RFU_MASK)
28357 /*! @} */
28358 
28359 /*! @name GDET_CONF_1 - GDET Configuration 1 Register */
28360 /*! @{ */
28361 
28362 #define GDET_GDET_CONF_1_FIELD_1_0_MASK          (0x3U)
28363 #define GDET_GDET_CONF_1_FIELD_1_0_SHIFT         (0U)
28364 /*! FIELD_1_0 - GDET Configuration 1 Field 1_0 */
28365 #define GDET_GDET_CONF_1_FIELD_1_0(x)            (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_FIELD_1_0_SHIFT)) & GDET_GDET_CONF_1_FIELD_1_0_MASK)
28366 
28367 #define GDET_GDET_CONF_1_FIELD_1_0_MASK          (0x3U)
28368 #define GDET_GDET_CONF_1_FIELD_1_0_SHIFT         (0U)
28369 /*! field_1_0 - GDET configuration 1 Field 1_0 */
28370 #define GDET_GDET_CONF_1_FIELD_1_0(x)            (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_FIELD_1_0_SHIFT)) & GDET_GDET_CONF_1_FIELD_1_0_MASK)
28371 
28372 #define GDET_GDET_CONF_1_FIELD_3_2_MASK          (0xCU)
28373 #define GDET_GDET_CONF_1_FIELD_3_2_SHIFT         (2U)
28374 /*! FIELD_3_2 - GDET Configuration 1 Field 3_2 */
28375 #define GDET_GDET_CONF_1_FIELD_3_2(x)            (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_FIELD_3_2_SHIFT)) & GDET_GDET_CONF_1_FIELD_3_2_MASK)
28376 
28377 #define GDET_GDET_CONF_1_FIELD_3_2_MASK          (0xCU)
28378 #define GDET_GDET_CONF_1_FIELD_3_2_SHIFT         (2U)
28379 /*! field_3_2 - GDET configuration 1 Field 3_2 */
28380 #define GDET_GDET_CONF_1_FIELD_3_2(x)            (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_FIELD_3_2_SHIFT)) & GDET_GDET_CONF_1_FIELD_3_2_MASK)
28381 
28382 #define GDET_GDET_CONF_1_SBZ1_MASK               (0x10U)
28383 #define GDET_GDET_CONF_1_SBZ1_SHIFT              (4U)
28384 /*! SBZ1 - Should Be Left to Zero */
28385 #define GDET_GDET_CONF_1_SBZ1(x)                 (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_SBZ1_SHIFT)) & GDET_GDET_CONF_1_SBZ1_MASK)
28386 
28387 #define GDET_GDET_CONF_1_SBZ1_MASK               (0x10U)
28388 #define GDET_GDET_CONF_1_SBZ1_SHIFT              (4U)
28389 /*! sbz1 - Should be left to zero */
28390 #define GDET_GDET_CONF_1_SBZ1(x)                 (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_SBZ1_SHIFT)) & GDET_GDET_CONF_1_SBZ1_MASK)
28391 
28392 #define GDET_GDET_CONF_1_SBZ2_MASK               (0x20U)
28393 #define GDET_GDET_CONF_1_SBZ2_SHIFT              (5U)
28394 /*! SBZ2 - Should Be Left to Zero */
28395 #define GDET_GDET_CONF_1_SBZ2(x)                 (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_SBZ2_SHIFT)) & GDET_GDET_CONF_1_SBZ2_MASK)
28396 
28397 #define GDET_GDET_CONF_1_SBZ2_MASK               (0x20U)
28398 #define GDET_GDET_CONF_1_SBZ2_SHIFT              (5U)
28399 /*! sbz2 - Should be left to zero */
28400 #define GDET_GDET_CONF_1_SBZ2(x)                 (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_SBZ2_SHIFT)) & GDET_GDET_CONF_1_SBZ2_MASK)
28401 
28402 #define GDET_GDET_CONF_1_SBZ3_MASK               (0x40U)
28403 #define GDET_GDET_CONF_1_SBZ3_SHIFT              (6U)
28404 /*! SBZ3 - Should Be Left to Zero */
28405 #define GDET_GDET_CONF_1_SBZ3(x)                 (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_SBZ3_SHIFT)) & GDET_GDET_CONF_1_SBZ3_MASK)
28406 
28407 #define GDET_GDET_CONF_1_SBZ3_MASK               (0x40U)
28408 #define GDET_GDET_CONF_1_SBZ3_SHIFT              (6U)
28409 /*! sbz3 - Should be left to zero */
28410 #define GDET_GDET_CONF_1_SBZ3(x)                 (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_SBZ3_SHIFT)) & GDET_GDET_CONF_1_SBZ3_MASK)
28411 
28412 #define GDET_GDET_CONF_1_FIELD_7_MASK            (0x80U)
28413 #define GDET_GDET_CONF_1_FIELD_7_SHIFT           (7U)
28414 /*! FIELD_7 - GDET Configuration 1 Field 7 */
28415 #define GDET_GDET_CONF_1_FIELD_7(x)              (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_FIELD_7_SHIFT)) & GDET_GDET_CONF_1_FIELD_7_MASK)
28416 
28417 #define GDET_GDET_CONF_1_FIELD_7_MASK            (0x80U)
28418 #define GDET_GDET_CONF_1_FIELD_7_SHIFT           (7U)
28419 /*! field_7 - GDET configuration 1 Field 7 */
28420 #define GDET_GDET_CONF_1_FIELD_7(x)              (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_FIELD_7_SHIFT)) & GDET_GDET_CONF_1_FIELD_7_MASK)
28421 
28422 #define GDET_GDET_CONF_1_FIELD_8_MASK            (0x100U)
28423 #define GDET_GDET_CONF_1_FIELD_8_SHIFT           (8U)
28424 /*! FIELD_8 - GDET Configuration 1 Field 8 */
28425 #define GDET_GDET_CONF_1_FIELD_8(x)              (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_FIELD_8_SHIFT)) & GDET_GDET_CONF_1_FIELD_8_MASK)
28426 
28427 #define GDET_GDET_CONF_1_FIELD_8_MASK            (0x100U)
28428 #define GDET_GDET_CONF_1_FIELD_8_SHIFT           (8U)
28429 /*! field_8 - GDET configuration 1 Field 8 */
28430 #define GDET_GDET_CONF_1_FIELD_8(x)              (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_FIELD_8_SHIFT)) & GDET_GDET_CONF_1_FIELD_8_MASK)
28431 
28432 #define GDET_GDET_CONF_1_SBZ4_MASK               (0x200U)
28433 #define GDET_GDET_CONF_1_SBZ4_SHIFT              (9U)
28434 /*! SBZ4 - Should Be Left to Zero */
28435 #define GDET_GDET_CONF_1_SBZ4(x)                 (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_SBZ4_SHIFT)) & GDET_GDET_CONF_1_SBZ4_MASK)
28436 
28437 #define GDET_GDET_CONF_1_SBZ4_MASK               (0x200U)
28438 #define GDET_GDET_CONF_1_SBZ4_SHIFT              (9U)
28439 /*! sbz4 - Should be left to zero */
28440 #define GDET_GDET_CONF_1_SBZ4(x)                 (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_SBZ4_SHIFT)) & GDET_GDET_CONF_1_SBZ4_MASK)
28441 
28442 #define GDET_GDET_CONF_1_SBZ5_MASK               (0x400U)
28443 #define GDET_GDET_CONF_1_SBZ5_SHIFT              (10U)
28444 /*! SBZ5 - Should Be Left to Zero */
28445 #define GDET_GDET_CONF_1_SBZ5(x)                 (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_SBZ5_SHIFT)) & GDET_GDET_CONF_1_SBZ5_MASK)
28446 
28447 #define GDET_GDET_CONF_1_SBZ5_MASK               (0x400U)
28448 #define GDET_GDET_CONF_1_SBZ5_SHIFT              (10U)
28449 /*! sbz5 - Should be left to zero */
28450 #define GDET_GDET_CONF_1_SBZ5(x)                 (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_SBZ5_SHIFT)) & GDET_GDET_CONF_1_SBZ5_MASK)
28451 
28452 #define GDET_GDET_CONF_1_RFU_MASK                (0xFFFFF800U)
28453 #define GDET_GDET_CONF_1_RFU_SHIFT               (11U)
28454 /*! RFU - Reserved for Future Use */
28455 #define GDET_GDET_CONF_1_RFU(x)                  (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_RFU_SHIFT)) & GDET_GDET_CONF_1_RFU_MASK)
28456 
28457 #define GDET_GDET_CONF_1_RFU_MASK                (0xFFFFF800U)
28458 #define GDET_GDET_CONF_1_RFU_SHIFT               (11U)
28459 /*! rfu - Reserved for Future Use */
28460 #define GDET_GDET_CONF_1_RFU(x)                  (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_RFU_SHIFT)) & GDET_GDET_CONF_1_RFU_MASK)
28461 /*! @} */
28462 
28463 /*! @name GDET_ENABLE1 - GDET Enable Register */
28464 /*! @{ */
28465 
28466 #define GDET_GDET_ENABLE1_EN1_MASK               (0x1U)
28467 #define GDET_GDET_ENABLE1_EN1_SHIFT              (0U)
28468 /*! EN1 - If set, the detector will be clock gated */
28469 #define GDET_GDET_ENABLE1_EN1(x)                 (((uint32_t)(((uint32_t)(x)) << GDET_GDET_ENABLE1_EN1_SHIFT)) & GDET_GDET_ENABLE1_EN1_MASK)
28470 
28471 #define GDET_GDET_ENABLE1_EN1_MASK               (0x1U)
28472 #define GDET_GDET_ENABLE1_EN1_SHIFT              (0U)
28473 /*! en1 - If set, the detector will be clock gated */
28474 #define GDET_GDET_ENABLE1_EN1(x)                 (((uint32_t)(((uint32_t)(x)) << GDET_GDET_ENABLE1_EN1_SHIFT)) & GDET_GDET_ENABLE1_EN1_MASK)
28475 
28476 #define GDET_GDET_ENABLE1_RFU_MASK               (0xFFFFFFFEU)
28477 #define GDET_GDET_ENABLE1_RFU_SHIFT              (1U)
28478 /*! RFU - Reserved for Future Use */
28479 #define GDET_GDET_ENABLE1_RFU(x)                 (((uint32_t)(((uint32_t)(x)) << GDET_GDET_ENABLE1_RFU_SHIFT)) & GDET_GDET_ENABLE1_RFU_MASK)
28480 
28481 #define GDET_GDET_ENABLE1_RFU_MASK               (0xFFFFFFFEU)
28482 #define GDET_GDET_ENABLE1_RFU_SHIFT              (1U)
28483 /*! rfu - Reserved for Future Use */
28484 #define GDET_GDET_ENABLE1_RFU(x)                 (((uint32_t)(((uint32_t)(x)) << GDET_GDET_ENABLE1_RFU_SHIFT)) & GDET_GDET_ENABLE1_RFU_MASK)
28485 /*! @} */
28486 
28487 /*! @name GDET_CONF_2 - GDET Configuration 2 Register */
28488 /*! @{ */
28489 
28490 #define GDET_GDET_CONF_2_FIELD_6_0_MASK          (0x7FU)
28491 #define GDET_GDET_CONF_2_FIELD_6_0_SHIFT         (0U)
28492 /*! FIELD_6_0 - GDET Configuration 2 Field 6_0 */
28493 #define GDET_GDET_CONF_2_FIELD_6_0(x)            (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_2_FIELD_6_0_SHIFT)) & GDET_GDET_CONF_2_FIELD_6_0_MASK)
28494 
28495 #define GDET_GDET_CONF_2_FIELD_6_0_MASK          (0x7FU)
28496 #define GDET_GDET_CONF_2_FIELD_6_0_SHIFT         (0U)
28497 /*! field_6_0 - GDET configuration 2 Field 6_0 */
28498 #define GDET_GDET_CONF_2_FIELD_6_0(x)            (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_2_FIELD_6_0_SHIFT)) & GDET_GDET_CONF_2_FIELD_6_0_MASK)
28499 
28500 #define GDET_GDET_CONF_2_RFU1_MASK               (0xFF80U)
28501 #define GDET_GDET_CONF_2_RFU1_SHIFT              (7U)
28502 /*! RFU1 - Reserved for Future Use */
28503 #define GDET_GDET_CONF_2_RFU1(x)                 (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_2_RFU1_SHIFT)) & GDET_GDET_CONF_2_RFU1_MASK)
28504 
28505 #define GDET_GDET_CONF_2_RFU1_MASK               (0xFF80U)
28506 #define GDET_GDET_CONF_2_RFU1_SHIFT              (7U)
28507 /*! rfu1 - Reserved for Future Use */
28508 #define GDET_GDET_CONF_2_RFU1(x)                 (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_2_RFU1_SHIFT)) & GDET_GDET_CONF_2_RFU1_MASK)
28509 
28510 #define GDET_GDET_CONF_2_FIELD_21_16_MASK        (0x3F0000U)
28511 #define GDET_GDET_CONF_2_FIELD_21_16_SHIFT       (16U)
28512 /*! FIELD_21_16 - GDET Configuration 2 Field 21_16 */
28513 #define GDET_GDET_CONF_2_FIELD_21_16(x)          (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_2_FIELD_21_16_SHIFT)) & GDET_GDET_CONF_2_FIELD_21_16_MASK)
28514 
28515 #define GDET_GDET_CONF_2_FIELD_21_16_MASK        (0x3F0000U)
28516 #define GDET_GDET_CONF_2_FIELD_21_16_SHIFT       (16U)
28517 /*! field_21_16 - GDET configuration 2 Field 21_16 */
28518 #define GDET_GDET_CONF_2_FIELD_21_16(x)          (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_2_FIELD_21_16_SHIFT)) & GDET_GDET_CONF_2_FIELD_21_16_MASK)
28519 
28520 #define GDET_GDET_CONF_2_RFU2_MASK               (0xC00000U)
28521 #define GDET_GDET_CONF_2_RFU2_SHIFT              (22U)
28522 /*! RFU2 - Reserved for Future Use */
28523 #define GDET_GDET_CONF_2_RFU2(x)                 (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_2_RFU2_SHIFT)) & GDET_GDET_CONF_2_RFU2_MASK)
28524 
28525 #define GDET_GDET_CONF_2_RFU2_MASK               (0xC00000U)
28526 #define GDET_GDET_CONF_2_RFU2_SHIFT              (22U)
28527 /*! rfu2 - Reserved for Future Use */
28528 #define GDET_GDET_CONF_2_RFU2(x)                 (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_2_RFU2_SHIFT)) & GDET_GDET_CONF_2_RFU2_MASK)
28529 
28530 #define GDET_GDET_CONF_2_FIELD_29_24_MASK        (0x3F000000U)
28531 #define GDET_GDET_CONF_2_FIELD_29_24_SHIFT       (24U)
28532 /*! FIELD_29_24 - GDET Configuration 2 Field 29_24 */
28533 #define GDET_GDET_CONF_2_FIELD_29_24(x)          (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_2_FIELD_29_24_SHIFT)) & GDET_GDET_CONF_2_FIELD_29_24_MASK)
28534 
28535 #define GDET_GDET_CONF_2_FIELD_29_24_MASK        (0x3F000000U)
28536 #define GDET_GDET_CONF_2_FIELD_29_24_SHIFT       (24U)
28537 /*! field_29_24 - GDET configuration 2 Field 29_24 */
28538 #define GDET_GDET_CONF_2_FIELD_29_24(x)          (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_2_FIELD_29_24_SHIFT)) & GDET_GDET_CONF_2_FIELD_29_24_MASK)
28539 
28540 #define GDET_GDET_CONF_2_RFU3_MASK               (0xC0000000U)
28541 #define GDET_GDET_CONF_2_RFU3_SHIFT              (30U)
28542 /*! RFU3 - Reserved for Future Use */
28543 #define GDET_GDET_CONF_2_RFU3(x)                 (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_2_RFU3_SHIFT)) & GDET_GDET_CONF_2_RFU3_MASK)
28544 
28545 #define GDET_GDET_CONF_2_RFU3_MASK               (0xC0000000U)
28546 #define GDET_GDET_CONF_2_RFU3_SHIFT              (30U)
28547 /*! rfu3 - Reserved for Future Use */
28548 #define GDET_GDET_CONF_2_RFU3(x)                 (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_2_RFU3_SHIFT)) & GDET_GDET_CONF_2_RFU3_MASK)
28549 /*! @} */
28550 
28551 /*! @name GDET_CONF_3 - GDET Configuration 3 Register */
28552 /*! @{ */
28553 
28554 #define GDET_GDET_CONF_3_FIELD_6_0_MASK          (0x7FU)
28555 #define GDET_GDET_CONF_3_FIELD_6_0_SHIFT         (0U)
28556 /*! FIELD_6_0 - GDET Configuration 3 Field 6_0 */
28557 #define GDET_GDET_CONF_3_FIELD_6_0(x)            (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_3_FIELD_6_0_SHIFT)) & GDET_GDET_CONF_3_FIELD_6_0_MASK)
28558 
28559 #define GDET_GDET_CONF_3_FIELD_6_0_MASK          (0x7FU)
28560 #define GDET_GDET_CONF_3_FIELD_6_0_SHIFT         (0U)
28561 /*! field_6_0 - GDET configuration 3 Field 6_0 */
28562 #define GDET_GDET_CONF_3_FIELD_6_0(x)            (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_3_FIELD_6_0_SHIFT)) & GDET_GDET_CONF_3_FIELD_6_0_MASK)
28563 
28564 #define GDET_GDET_CONF_3_RFU1_MASK               (0xFFFFFF80U)
28565 #define GDET_GDET_CONF_3_RFU1_SHIFT              (7U)
28566 /*! RFU1 - Reserved for Future Use */
28567 #define GDET_GDET_CONF_3_RFU1(x)                 (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_3_RFU1_SHIFT)) & GDET_GDET_CONF_3_RFU1_MASK)
28568 
28569 #define GDET_GDET_CONF_3_RFU1_MASK               (0xFFFFFF80U)
28570 #define GDET_GDET_CONF_3_RFU1_SHIFT              (7U)
28571 /*! rfu1 - Reserved for Future Use */
28572 #define GDET_GDET_CONF_3_RFU1(x)                 (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_3_RFU1_SHIFT)) & GDET_GDET_CONF_3_RFU1_MASK)
28573 /*! @} */
28574 
28575 /*! @name GDET_CONF_4 - GDET Configuration 4 Register */
28576 /*! @{ */
28577 
28578 #define GDET_GDET_CONF_4_FIELD_6_0_MASK          (0x7FU)
28579 #define GDET_GDET_CONF_4_FIELD_6_0_SHIFT         (0U)
28580 /*! FIELD_6_0 - GDET Configuration 4 Field 6_0 */
28581 #define GDET_GDET_CONF_4_FIELD_6_0(x)            (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_4_FIELD_6_0_SHIFT)) & GDET_GDET_CONF_4_FIELD_6_0_MASK)
28582 
28583 #define GDET_GDET_CONF_4_FIELD_6_0_MASK          (0x7FU)
28584 #define GDET_GDET_CONF_4_FIELD_6_0_SHIFT         (0U)
28585 /*! field_6_0 - GDET configuration 4 Field 6_0 */
28586 #define GDET_GDET_CONF_4_FIELD_6_0(x)            (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_4_FIELD_6_0_SHIFT)) & GDET_GDET_CONF_4_FIELD_6_0_MASK)
28587 
28588 #define GDET_GDET_CONF_4_RFU1_MASK               (0xFFFFFF80U)
28589 #define GDET_GDET_CONF_4_RFU1_SHIFT              (7U)
28590 /*! RFU1 - Reserved for Future Use */
28591 #define GDET_GDET_CONF_4_RFU1(x)                 (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_4_RFU1_SHIFT)) & GDET_GDET_CONF_4_RFU1_MASK)
28592 
28593 #define GDET_GDET_CONF_4_RFU1_MASK               (0xFFFFFF80U)
28594 #define GDET_GDET_CONF_4_RFU1_SHIFT              (7U)
28595 /*! rfu1 - Reserved for Future Use */
28596 #define GDET_GDET_CONF_4_RFU1(x)                 (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_4_RFU1_SHIFT)) & GDET_GDET_CONF_4_RFU1_MASK)
28597 /*! @} */
28598 
28599 /*! @name GDET_CONF_5 - GDET Configuration 5 Register */
28600 /*! @{ */
28601 
28602 #define GDET_GDET_CONF_5_FIELD_5_0_MASK          (0x3FU)
28603 #define GDET_GDET_CONF_5_FIELD_5_0_SHIFT         (0U)
28604 /*! FIELD_5_0 - GDET Configuration 5 Field 5_0 */
28605 #define GDET_GDET_CONF_5_FIELD_5_0(x)            (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_5_FIELD_5_0_SHIFT)) & GDET_GDET_CONF_5_FIELD_5_0_MASK)
28606 
28607 #define GDET_GDET_CONF_5_FIELD_5_0_MASK          (0x3FU)
28608 #define GDET_GDET_CONF_5_FIELD_5_0_SHIFT         (0U)
28609 /*! field_5_0 - GDET configuration 5 Field 5_0 */
28610 #define GDET_GDET_CONF_5_FIELD_5_0(x)            (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_5_FIELD_5_0_SHIFT)) & GDET_GDET_CONF_5_FIELD_5_0_MASK)
28611 
28612 #define GDET_GDET_CONF_5_FIELD_11_6_MASK         (0xFC0U)
28613 #define GDET_GDET_CONF_5_FIELD_11_6_SHIFT        (6U)
28614 /*! FIELD_11_6 - GDET Configuration 5 Field 11_6 */
28615 #define GDET_GDET_CONF_5_FIELD_11_6(x)           (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_5_FIELD_11_6_SHIFT)) & GDET_GDET_CONF_5_FIELD_11_6_MASK)
28616 
28617 #define GDET_GDET_CONF_5_FIELD_11_6_MASK         (0xFC0U)
28618 #define GDET_GDET_CONF_5_FIELD_11_6_SHIFT        (6U)
28619 /*! field_11_6 - GDET configuration 5 Field 11_6 */
28620 #define GDET_GDET_CONF_5_FIELD_11_6(x)           (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_5_FIELD_11_6_SHIFT)) & GDET_GDET_CONF_5_FIELD_11_6_MASK)
28621 
28622 #define GDET_GDET_CONF_5_RFU1_MASK               (0xFFFFF000U)
28623 #define GDET_GDET_CONF_5_RFU1_SHIFT              (12U)
28624 /*! RFU1 - Reserved for Future Use */
28625 #define GDET_GDET_CONF_5_RFU1(x)                 (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_5_RFU1_SHIFT)) & GDET_GDET_CONF_5_RFU1_MASK)
28626 
28627 #define GDET_GDET_CONF_5_RFU1_MASK               (0xFFFFF000U)
28628 #define GDET_GDET_CONF_5_RFU1_SHIFT              (12U)
28629 /*! rfu1 - Reserved for Future Use */
28630 #define GDET_GDET_CONF_5_RFU1(x)                 (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_5_RFU1_SHIFT)) & GDET_GDET_CONF_5_RFU1_MASK)
28631 /*! @} */
28632 
28633 /*! @name GDET_RESET - GDET Reset Register */
28634 /*! @{ */
28635 
28636 #define GDET_GDET_RESET_RFU1_MASK                (0x7U)
28637 #define GDET_GDET_RESET_RFU1_SHIFT               (0U)
28638 /*! RFU1 - Reserved for Future Use */
28639 #define GDET_GDET_RESET_RFU1(x)                  (((uint32_t)(((uint32_t)(x)) << GDET_GDET_RESET_RFU1_SHIFT)) & GDET_GDET_RESET_RFU1_MASK)
28640 
28641 #define GDET_GDET_RESET_RFU1_MASK                (0x7U)
28642 #define GDET_GDET_RESET_RFU1_SHIFT               (0U)
28643 /*! rfu1 - Reserved for Future Use */
28644 #define GDET_GDET_RESET_RFU1(x)                  (((uint32_t)(((uint32_t)(x)) << GDET_GDET_RESET_RFU1_SHIFT)) & GDET_GDET_RESET_RFU1_MASK)
28645 
28646 #define GDET_GDET_RESET_SFT_RST_MASK             (0x8U)
28647 #define GDET_GDET_RESET_SFT_RST_SHIFT            (3U)
28648 /*! SFT_RST - Soft Reset for the Core Reset */
28649 #define GDET_GDET_RESET_SFT_RST(x)               (((uint32_t)(((uint32_t)(x)) << GDET_GDET_RESET_SFT_RST_SHIFT)) & GDET_GDET_RESET_SFT_RST_MASK)
28650 
28651 #define GDET_GDET_RESET_SFT_RST_MASK             (0x8U)
28652 #define GDET_GDET_RESET_SFT_RST_SHIFT            (3U)
28653 /*! sft_rst - Soft reset for the core reset (SFR configuration will be preseved).This register reads as 0 */
28654 #define GDET_GDET_RESET_SFT_RST(x)               (((uint32_t)(((uint32_t)(x)) << GDET_GDET_RESET_SFT_RST_SHIFT)) & GDET_GDET_RESET_SFT_RST_MASK)
28655 
28656 #define GDET_GDET_RESET_RFU2_MASK                (0xFFFFFFF0U)
28657 #define GDET_GDET_RESET_RFU2_SHIFT               (4U)
28658 /*! RFU2 - Reserved for Future Use */
28659 #define GDET_GDET_RESET_RFU2(x)                  (((uint32_t)(((uint32_t)(x)) << GDET_GDET_RESET_RFU2_SHIFT)) & GDET_GDET_RESET_RFU2_MASK)
28660 
28661 #define GDET_GDET_RESET_RFU2_MASK                (0xFFFFFFF0U)
28662 #define GDET_GDET_RESET_RFU2_SHIFT               (4U)
28663 /*! rfu2 - Reserved for Future Use */
28664 #define GDET_GDET_RESET_RFU2(x)                  (((uint32_t)(((uint32_t)(x)) << GDET_GDET_RESET_RFU2_SHIFT)) & GDET_GDET_RESET_RFU2_MASK)
28665 /*! @} */
28666 
28667 /*! @name GDET_TEST - GDET Test Register */
28668 /*! @{ */
28669 
28670 #define GDET_GDET_TEST_SBZ_MASK                  (0x1U)
28671 #define GDET_GDET_TEST_SBZ_SHIFT                 (0U)
28672 /*! SBZ - Should Be Left to Zero */
28673 #define GDET_GDET_TEST_SBZ(x)                    (((uint32_t)(((uint32_t)(x)) << GDET_GDET_TEST_SBZ_SHIFT)) & GDET_GDET_TEST_SBZ_MASK)
28674 
28675 #define GDET_GDET_TEST_SBZ_MASK                  (0x1U)
28676 #define GDET_GDET_TEST_SBZ_SHIFT                 (0U)
28677 /*! sbz - Should be left to zero */
28678 #define GDET_GDET_TEST_SBZ(x)                    (((uint32_t)(((uint32_t)(x)) << GDET_GDET_TEST_SBZ_SHIFT)) & GDET_GDET_TEST_SBZ_MASK)
28679 
28680 #define GDET_GDET_TEST_RFU_MASK                  (0xFFFFFFFEU)
28681 #define GDET_GDET_TEST_RFU_SHIFT                 (1U)
28682 /*! RFU - Reserved for Future Use */
28683 #define GDET_GDET_TEST_RFU(x)                    (((uint32_t)(((uint32_t)(x)) << GDET_GDET_TEST_RFU_SHIFT)) & GDET_GDET_TEST_RFU_MASK)
28684 
28685 #define GDET_GDET_TEST_RFU_MASK                  (0xFFFFFFFEU)
28686 #define GDET_GDET_TEST_RFU_SHIFT                 (1U)
28687 /*! rfu - Reserved for Future Use */
28688 #define GDET_GDET_TEST_RFU(x)                    (((uint32_t)(((uint32_t)(x)) << GDET_GDET_TEST_RFU_SHIFT)) & GDET_GDET_TEST_RFU_MASK)
28689 /*! @} */
28690 
28691 /*! @name GDET_DLY_CTRL - GDET Delay Control Register */
28692 /*! @{ */
28693 
28694 #define GDET_GDET_DLY_CTRL_VOL_SEL_MASK          (0x3U)
28695 #define GDET_GDET_DLY_CTRL_VOL_SEL_SHIFT         (0U)
28696 /*! VOL_SEL - GDET Delay Control of the Voltage Mode */
28697 #define GDET_GDET_DLY_CTRL_VOL_SEL(x)            (((uint32_t)(((uint32_t)(x)) << GDET_GDET_DLY_CTRL_VOL_SEL_SHIFT)) & GDET_GDET_DLY_CTRL_VOL_SEL_MASK)
28698 
28699 #define GDET_GDET_DLY_CTRL_VOL_SEL_MASK          (0x3U)
28700 #define GDET_GDET_DLY_CTRL_VOL_SEL_SHIFT         (0U)
28701 /*! vol_sel - GDET delay control of the voltage mode. Used to select the trim code appropiate to the voltage mode. */
28702 #define GDET_GDET_DLY_CTRL_VOL_SEL(x)            (((uint32_t)(((uint32_t)(x)) << GDET_GDET_DLY_CTRL_VOL_SEL_SHIFT)) & GDET_GDET_DLY_CTRL_VOL_SEL_MASK)
28703 
28704 #define GDET_GDET_DLY_CTRL_SW_VOL_CTRL_MASK      (0x4U)
28705 #define GDET_GDET_DLY_CTRL_SW_VOL_CTRL_SHIFT     (2U)
28706 /*! SW_VOL_CTRL - Select the Control of the Trim Code to the Delay Line */
28707 #define GDET_GDET_DLY_CTRL_SW_VOL_CTRL(x)        (((uint32_t)(((uint32_t)(x)) << GDET_GDET_DLY_CTRL_SW_VOL_CTRL_SHIFT)) & GDET_GDET_DLY_CTRL_SW_VOL_CTRL_MASK)
28708 
28709 #define GDET_GDET_DLY_CTRL_SW_VOL_CTRL_MASK      (0x4U)
28710 #define GDET_GDET_DLY_CTRL_SW_VOL_CTRL_SHIFT     (2U)
28711 /*! sw_vol_ctrl - Select the control of the trim code to the delay line via HW port (0) or SW SFR (1) */
28712 #define GDET_GDET_DLY_CTRL_SW_VOL_CTRL(x)        (((uint32_t)(((uint32_t)(x)) << GDET_GDET_DLY_CTRL_SW_VOL_CTRL_SHIFT)) & GDET_GDET_DLY_CTRL_SW_VOL_CTRL_MASK)
28713 
28714 #define GDET_GDET_DLY_CTRL_RFU_MASK              (0xFFFFFFF8U)
28715 #define GDET_GDET_DLY_CTRL_RFU_SHIFT             (3U)
28716 /*! RFU - Reserved for Future Use */
28717 #define GDET_GDET_DLY_CTRL_RFU(x)                (((uint32_t)(((uint32_t)(x)) << GDET_GDET_DLY_CTRL_RFU_SHIFT)) & GDET_GDET_DLY_CTRL_RFU_MASK)
28718 
28719 #define GDET_GDET_DLY_CTRL_RFU_MASK              (0xFFFFFFF8U)
28720 #define GDET_GDET_DLY_CTRL_RFU_SHIFT             (3U)
28721 /*! rfu - Reserved for Future Use */
28722 #define GDET_GDET_DLY_CTRL_RFU(x)                (((uint32_t)(((uint32_t)(x)) << GDET_GDET_DLY_CTRL_RFU_SHIFT)) & GDET_GDET_DLY_CTRL_RFU_MASK)
28723 /*! @} */
28724 
28725 
28726 /*!
28727  * @}
28728  */ /* end of group GDET_Register_Masks */
28729 
28730 
28731 /* GDET - Peripheral instance base addresses */
28732 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
28733   /** Peripheral GDET0 base address */
28734   #define GDET0_BASE                               (0x50024000u)
28735   /** Peripheral GDET0 base address */
28736   #define GDET0_BASE_NS                            (0x40024000u)
28737   /** Peripheral GDET0 base pointer */
28738   #define GDET0                                    ((GDET_Type *)GDET0_BASE)
28739   /** Peripheral GDET0 base pointer */
28740   #define GDET0_NS                                 ((GDET_Type *)GDET0_BASE_NS)
28741   /** Peripheral GDET1 base address */
28742   #define GDET1_BASE                               (0x50025000u)
28743   /** Peripheral GDET1 base address */
28744   #define GDET1_BASE_NS                            (0x40025000u)
28745   /** Peripheral GDET1 base pointer */
28746   #define GDET1                                    ((GDET_Type *)GDET1_BASE)
28747   /** Peripheral GDET1 base pointer */
28748   #define GDET1_NS                                 ((GDET_Type *)GDET1_BASE_NS)
28749   /** Array initializer of GDET peripheral base addresses */
28750   #define GDET_BASE_ADDRS                          { GDET0_BASE, GDET1_BASE }
28751   /** Array initializer of GDET peripheral base pointers */
28752   #define GDET_BASE_PTRS                           { GDET0, GDET1 }
28753   /** Array initializer of GDET peripheral base addresses */
28754   #define GDET_BASE_ADDRS_NS                       { GDET0_BASE_NS, GDET1_BASE_NS }
28755   /** Array initializer of GDET peripheral base pointers */
28756   #define GDET_BASE_PTRS_NS                        { GDET0_NS, GDET1_NS }
28757 #else
28758   /** Peripheral GDET0 base address */
28759   #define GDET0_BASE                               (0x40024000u)
28760   /** Peripheral GDET0 base pointer */
28761   #define GDET0                                    ((GDET_Type *)GDET0_BASE)
28762   /** Peripheral GDET1 base address */
28763   #define GDET1_BASE                               (0x40025000u)
28764   /** Peripheral GDET1 base pointer */
28765   #define GDET1                                    ((GDET_Type *)GDET1_BASE)
28766   /** Array initializer of GDET peripheral base addresses */
28767   #define GDET_BASE_ADDRS                          { GDET0_BASE, GDET1_BASE }
28768   /** Array initializer of GDET peripheral base pointers */
28769   #define GDET_BASE_PTRS                           { GDET0, GDET1 }
28770 #endif
28771 
28772 /*!
28773  * @}
28774  */ /* end of group GDET_Peripheral_Access_Layer */
28775 
28776 
28777 /* ----------------------------------------------------------------------------
28778    -- GPIO Peripheral Access Layer
28779    ---------------------------------------------------------------------------- */
28780 
28781 /*!
28782  * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
28783  * @{
28784  */
28785 
28786 /** GPIO - Register Layout Typedef */
28787 typedef struct {
28788   __I  uint32_t VERID;                             /**< Version ID, offset: 0x0 */
28789   __I  uint32_t PARAM;                             /**< Parameter, offset: 0x4 */
28790        uint8_t RESERVED_0[4];
28791   __IO uint32_t LOCK;                              /**< Lock, offset: 0xC */
28792   __IO uint32_t PCNS;                              /**< Pin Control Nonsecure, offset: 0x10 */
28793   __IO uint32_t ICNS;                              /**< Interrupt Control Nonsecure, offset: 0x14 */
28794   __IO uint32_t PCNP;                              /**< Pin Control Nonprivilege, offset: 0x18 */
28795   __IO uint32_t ICNP;                              /**< Interrupt Control Nonprivilege, offset: 0x1C */
28796        uint8_t RESERVED_1[32];
28797   __IO uint32_t PDOR;                              /**< Port Data Output, offset: 0x40 */
28798   __O  uint32_t PSOR;                              /**< Port Set Output, offset: 0x44 */
28799   __O  uint32_t PCOR;                              /**< Port Clear Output, offset: 0x48 */
28800   __O  uint32_t PTOR;                              /**< Port Toggle Output, offset: 0x4C */
28801   __I  uint32_t PDIR;                              /**< Port Data Input, offset: 0x50 */
28802   __IO uint32_t PDDR;                              /**< Port Data Direction, offset: 0x54 */
28803   __IO uint32_t PIDR;                              /**< Port Input Disable, offset: 0x58 */
28804        uint8_t RESERVED_2[4];
28805   __IO uint8_t PDR[32];                            /**< Pin Data, array offset: 0x60, array step: 0x1 */
28806   __IO uint32_t ICR[32];                           /**< Interrupt Control 0..Interrupt Control 31, array offset: 0x80, array step: 0x4 */
28807   __O  uint32_t GICLR;                             /**< Global Interrupt Control Low, offset: 0x100 */
28808   __O  uint32_t GICHR;                             /**< Global Interrupt Control High, offset: 0x104 */
28809        uint8_t RESERVED_3[24];
28810   __IO uint32_t ISFR[2];                           /**< Interrupt Status Flag, array offset: 0x120, array step: 0x4 */
28811 } GPIO_Type;
28812 
28813 /* ----------------------------------------------------------------------------
28814    -- GPIO Register Masks
28815    ---------------------------------------------------------------------------- */
28816 
28817 /*!
28818  * @addtogroup GPIO_Register_Masks GPIO Register Masks
28819  * @{
28820  */
28821 
28822 /*! @name VERID - Version ID */
28823 /*! @{ */
28824 
28825 #define GPIO_VERID_FEATURE_MASK                  (0xFFFFU)
28826 #define GPIO_VERID_FEATURE_SHIFT                 (0U)
28827 /*! FEATURE - Feature Specification Number
28828  *  0b0000000000000000..Basic implementation
28829  *  0b0000000000000001..Protection registers implemented
28830  */
28831 #define GPIO_VERID_FEATURE(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_VERID_FEATURE_SHIFT)) & GPIO_VERID_FEATURE_MASK)
28832 
28833 #define GPIO_VERID_MINOR_MASK                    (0xFF0000U)
28834 #define GPIO_VERID_MINOR_SHIFT                   (16U)
28835 /*! MINOR - Minor Version Number */
28836 #define GPIO_VERID_MINOR(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_VERID_MINOR_SHIFT)) & GPIO_VERID_MINOR_MASK)
28837 
28838 #define GPIO_VERID_MAJOR_MASK                    (0xFF000000U)
28839 #define GPIO_VERID_MAJOR_SHIFT                   (24U)
28840 /*! MAJOR - Major Version Number */
28841 #define GPIO_VERID_MAJOR(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_VERID_MAJOR_SHIFT)) & GPIO_VERID_MAJOR_MASK)
28842 /*! @} */
28843 
28844 /*! @name PARAM - Parameter */
28845 /*! @{ */
28846 
28847 #define GPIO_PARAM_IRQNUM_MASK                   (0xFU)
28848 #define GPIO_PARAM_IRQNUM_SHIFT                  (0U)
28849 /*! IRQNUM - Interrupt Number */
28850 #define GPIO_PARAM_IRQNUM(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_PARAM_IRQNUM_SHIFT)) & GPIO_PARAM_IRQNUM_MASK)
28851 /*! @} */
28852 
28853 /*! @name LOCK - Lock */
28854 /*! @{ */
28855 
28856 #define GPIO_LOCK_PCNS_MASK                      (0x1U)
28857 #define GPIO_LOCK_PCNS_SHIFT                     (0U)
28858 /*! PCNS - Lock PCNS
28859  *  0b0..Writable in Secure-Privilege state
28860  *  0b1..Not writable until the next reset
28861  */
28862 #define GPIO_LOCK_PCNS(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_LOCK_PCNS_SHIFT)) & GPIO_LOCK_PCNS_MASK)
28863 
28864 #define GPIO_LOCK_ICNS_MASK                      (0x2U)
28865 #define GPIO_LOCK_ICNS_SHIFT                     (1U)
28866 /*! ICNS - Lock ICNS
28867  *  0b0..Writable in Secure-Privilege state
28868  *  0b1..Not writable until the next reset
28869  */
28870 #define GPIO_LOCK_ICNS(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_LOCK_ICNS_SHIFT)) & GPIO_LOCK_ICNS_MASK)
28871 
28872 #define GPIO_LOCK_PCNP_MASK                      (0x4U)
28873 #define GPIO_LOCK_PCNP_SHIFT                     (2U)
28874 /*! PCNP - Lock PCNP
28875  *  0b0..Writable in Secure-Privilege state
28876  *  0b1..Not writable until the next reset
28877  */
28878 #define GPIO_LOCK_PCNP(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_LOCK_PCNP_SHIFT)) & GPIO_LOCK_PCNP_MASK)
28879 
28880 #define GPIO_LOCK_ICNP_MASK                      (0x8U)
28881 #define GPIO_LOCK_ICNP_SHIFT                     (3U)
28882 /*! ICNP - Lock ICNP
28883  *  0b0..Writable in Secure-Privilege state
28884  *  0b1..Not writable until the next reset
28885  */
28886 #define GPIO_LOCK_ICNP(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_LOCK_ICNP_SHIFT)) & GPIO_LOCK_ICNP_MASK)
28887 /*! @} */
28888 
28889 /*! @name PCNS - Pin Control Nonsecure */
28890 /*! @{ */
28891 
28892 #define GPIO_PCNS_NSE0_MASK                      (0x1U)
28893 #define GPIO_PCNS_NSE0_SHIFT                     (0U)
28894 /*! NSE0 - Nonsecure Enable
28895  *  0b0..Secure access
28896  *  0b1..Nonsecure access
28897  */
28898 #define GPIO_PCNS_NSE0(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE0_SHIFT)) & GPIO_PCNS_NSE0_MASK)
28899 
28900 #define GPIO_PCNS_NSE1_MASK                      (0x2U)
28901 #define GPIO_PCNS_NSE1_SHIFT                     (1U)
28902 /*! NSE1 - Nonsecure Enable
28903  *  0b0..Secure access
28904  *  0b1..Nonsecure access
28905  */
28906 #define GPIO_PCNS_NSE1(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE1_SHIFT)) & GPIO_PCNS_NSE1_MASK)
28907 
28908 #define GPIO_PCNS_NSE2_MASK                      (0x4U)
28909 #define GPIO_PCNS_NSE2_SHIFT                     (2U)
28910 /*! NSE2 - Nonsecure Enable
28911  *  0b0..Secure access
28912  *  0b1..Nonsecure access
28913  */
28914 #define GPIO_PCNS_NSE2(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE2_SHIFT)) & GPIO_PCNS_NSE2_MASK)
28915 
28916 #define GPIO_PCNS_NSE3_MASK                      (0x8U)
28917 #define GPIO_PCNS_NSE3_SHIFT                     (3U)
28918 /*! NSE3 - Nonsecure Enable
28919  *  0b0..Secure access
28920  *  0b1..Nonsecure access
28921  */
28922 #define GPIO_PCNS_NSE3(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE3_SHIFT)) & GPIO_PCNS_NSE3_MASK)
28923 
28924 #define GPIO_PCNS_NSE4_MASK                      (0x10U)
28925 #define GPIO_PCNS_NSE4_SHIFT                     (4U)
28926 /*! NSE4 - Nonsecure Enable
28927  *  0b0..Secure access
28928  *  0b1..Nonsecure access
28929  */
28930 #define GPIO_PCNS_NSE4(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE4_SHIFT)) & GPIO_PCNS_NSE4_MASK)
28931 
28932 #define GPIO_PCNS_NSE5_MASK                      (0x20U)
28933 #define GPIO_PCNS_NSE5_SHIFT                     (5U)
28934 /*! NSE5 - Nonsecure Enable
28935  *  0b0..Secure access
28936  *  0b1..Nonsecure access
28937  */
28938 #define GPIO_PCNS_NSE5(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE5_SHIFT)) & GPIO_PCNS_NSE5_MASK)
28939 
28940 #define GPIO_PCNS_NSE6_MASK                      (0x40U)
28941 #define GPIO_PCNS_NSE6_SHIFT                     (6U)
28942 /*! NSE6 - Nonsecure Enable
28943  *  0b0..Secure access
28944  *  0b1..Nonsecure access
28945  */
28946 #define GPIO_PCNS_NSE6(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE6_SHIFT)) & GPIO_PCNS_NSE6_MASK)
28947 
28948 #define GPIO_PCNS_NSE7_MASK                      (0x80U)
28949 #define GPIO_PCNS_NSE7_SHIFT                     (7U)
28950 /*! NSE7 - Nonsecure Enable
28951  *  0b0..Secure access
28952  *  0b1..Nonsecure access
28953  */
28954 #define GPIO_PCNS_NSE7(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE7_SHIFT)) & GPIO_PCNS_NSE7_MASK)
28955 
28956 #define GPIO_PCNS_NSE8_MASK                      (0x100U)
28957 #define GPIO_PCNS_NSE8_SHIFT                     (8U)
28958 /*! NSE8 - Nonsecure Enable
28959  *  0b0..Secure access
28960  *  0b1..Nonsecure access
28961  */
28962 #define GPIO_PCNS_NSE8(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE8_SHIFT)) & GPIO_PCNS_NSE8_MASK)
28963 
28964 #define GPIO_PCNS_NSE9_MASK                      (0x200U)
28965 #define GPIO_PCNS_NSE9_SHIFT                     (9U)
28966 /*! NSE9 - Nonsecure Enable
28967  *  0b0..Secure access
28968  *  0b1..Nonsecure access
28969  */
28970 #define GPIO_PCNS_NSE9(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE9_SHIFT)) & GPIO_PCNS_NSE9_MASK)
28971 
28972 #define GPIO_PCNS_NSE10_MASK                     (0x400U)
28973 #define GPIO_PCNS_NSE10_SHIFT                    (10U)
28974 /*! NSE10 - Nonsecure Enable
28975  *  0b0..Secure access
28976  *  0b1..Nonsecure access
28977  */
28978 #define GPIO_PCNS_NSE10(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE10_SHIFT)) & GPIO_PCNS_NSE10_MASK)
28979 
28980 #define GPIO_PCNS_NSE11_MASK                     (0x800U)
28981 #define GPIO_PCNS_NSE11_SHIFT                    (11U)
28982 /*! NSE11 - Nonsecure Enable
28983  *  0b0..Secure access
28984  *  0b1..Nonsecure access
28985  */
28986 #define GPIO_PCNS_NSE11(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE11_SHIFT)) & GPIO_PCNS_NSE11_MASK)
28987 
28988 #define GPIO_PCNS_NSE12_MASK                     (0x1000U)
28989 #define GPIO_PCNS_NSE12_SHIFT                    (12U)
28990 /*! NSE12 - Nonsecure Enable
28991  *  0b0..Secure access
28992  *  0b1..Nonsecure access
28993  */
28994 #define GPIO_PCNS_NSE12(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE12_SHIFT)) & GPIO_PCNS_NSE12_MASK)
28995 
28996 #define GPIO_PCNS_NSE13_MASK                     (0x2000U)
28997 #define GPIO_PCNS_NSE13_SHIFT                    (13U)
28998 /*! NSE13 - Nonsecure Enable
28999  *  0b0..Secure access
29000  *  0b1..Nonsecure access
29001  */
29002 #define GPIO_PCNS_NSE13(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE13_SHIFT)) & GPIO_PCNS_NSE13_MASK)
29003 
29004 #define GPIO_PCNS_NSE14_MASK                     (0x4000U)
29005 #define GPIO_PCNS_NSE14_SHIFT                    (14U)
29006 /*! NSE14 - Nonsecure Enable
29007  *  0b0..Secure access
29008  *  0b1..Nonsecure access
29009  */
29010 #define GPIO_PCNS_NSE14(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE14_SHIFT)) & GPIO_PCNS_NSE14_MASK)
29011 
29012 #define GPIO_PCNS_NSE15_MASK                     (0x8000U)
29013 #define GPIO_PCNS_NSE15_SHIFT                    (15U)
29014 /*! NSE15 - Nonsecure Enable
29015  *  0b0..Secure access
29016  *  0b1..Nonsecure access
29017  */
29018 #define GPIO_PCNS_NSE15(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE15_SHIFT)) & GPIO_PCNS_NSE15_MASK)
29019 
29020 #define GPIO_PCNS_NSE16_MASK                     (0x10000U)
29021 #define GPIO_PCNS_NSE16_SHIFT                    (16U)
29022 /*! NSE16 - Nonsecure Enable
29023  *  0b0..Secure access
29024  *  0b1..Nonsecure access
29025  */
29026 #define GPIO_PCNS_NSE16(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE16_SHIFT)) & GPIO_PCNS_NSE16_MASK)
29027 
29028 #define GPIO_PCNS_NSE17_MASK                     (0x20000U)
29029 #define GPIO_PCNS_NSE17_SHIFT                    (17U)
29030 /*! NSE17 - Nonsecure Enable
29031  *  0b0..Secure access
29032  *  0b1..Nonsecure access
29033  */
29034 #define GPIO_PCNS_NSE17(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE17_SHIFT)) & GPIO_PCNS_NSE17_MASK)
29035 
29036 #define GPIO_PCNS_NSE18_MASK                     (0x40000U)
29037 #define GPIO_PCNS_NSE18_SHIFT                    (18U)
29038 /*! NSE18 - Nonsecure Enable
29039  *  0b0..Secure access
29040  *  0b1..Nonsecure access
29041  */
29042 #define GPIO_PCNS_NSE18(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE18_SHIFT)) & GPIO_PCNS_NSE18_MASK)
29043 
29044 #define GPIO_PCNS_NSE19_MASK                     (0x80000U)
29045 #define GPIO_PCNS_NSE19_SHIFT                    (19U)
29046 /*! NSE19 - Nonsecure Enable
29047  *  0b0..Secure access
29048  *  0b1..Nonsecure access
29049  */
29050 #define GPIO_PCNS_NSE19(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE19_SHIFT)) & GPIO_PCNS_NSE19_MASK)
29051 
29052 #define GPIO_PCNS_NSE20_MASK                     (0x100000U)
29053 #define GPIO_PCNS_NSE20_SHIFT                    (20U)
29054 /*! NSE20 - Nonsecure Enable
29055  *  0b0..Secure access
29056  *  0b1..Nonsecure access
29057  */
29058 #define GPIO_PCNS_NSE20(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE20_SHIFT)) & GPIO_PCNS_NSE20_MASK)
29059 
29060 #define GPIO_PCNS_NSE21_MASK                     (0x200000U)
29061 #define GPIO_PCNS_NSE21_SHIFT                    (21U)
29062 /*! NSE21 - Nonsecure Enable
29063  *  0b0..Secure access
29064  *  0b1..Nonsecure access
29065  */
29066 #define GPIO_PCNS_NSE21(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE21_SHIFT)) & GPIO_PCNS_NSE21_MASK)
29067 
29068 #define GPIO_PCNS_NSE22_MASK                     (0x400000U)
29069 #define GPIO_PCNS_NSE22_SHIFT                    (22U)
29070 /*! NSE22 - Nonsecure Enable
29071  *  0b0..Secure access
29072  *  0b1..Nonsecure access
29073  */
29074 #define GPIO_PCNS_NSE22(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE22_SHIFT)) & GPIO_PCNS_NSE22_MASK)
29075 
29076 #define GPIO_PCNS_NSE23_MASK                     (0x800000U)
29077 #define GPIO_PCNS_NSE23_SHIFT                    (23U)
29078 /*! NSE23 - Nonsecure Enable
29079  *  0b0..Secure access
29080  *  0b1..Nonsecure access
29081  */
29082 #define GPIO_PCNS_NSE23(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE23_SHIFT)) & GPIO_PCNS_NSE23_MASK)
29083 
29084 #define GPIO_PCNS_NSE24_MASK                     (0x1000000U)
29085 #define GPIO_PCNS_NSE24_SHIFT                    (24U)
29086 /*! NSE24 - Nonsecure Enable
29087  *  0b0..Secure access
29088  *  0b1..Nonsecure access
29089  */
29090 #define GPIO_PCNS_NSE24(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE24_SHIFT)) & GPIO_PCNS_NSE24_MASK)
29091 
29092 #define GPIO_PCNS_NSE25_MASK                     (0x2000000U)
29093 #define GPIO_PCNS_NSE25_SHIFT                    (25U)
29094 /*! NSE25 - Nonsecure Enable
29095  *  0b0..Secure access
29096  *  0b1..Nonsecure access
29097  */
29098 #define GPIO_PCNS_NSE25(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE25_SHIFT)) & GPIO_PCNS_NSE25_MASK)
29099 
29100 #define GPIO_PCNS_NSE26_MASK                     (0x4000000U)
29101 #define GPIO_PCNS_NSE26_SHIFT                    (26U)
29102 /*! NSE26 - Nonsecure Enable
29103  *  0b0..Secure access
29104  *  0b1..Nonsecure access
29105  */
29106 #define GPIO_PCNS_NSE26(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE26_SHIFT)) & GPIO_PCNS_NSE26_MASK)
29107 
29108 #define GPIO_PCNS_NSE27_MASK                     (0x8000000U)
29109 #define GPIO_PCNS_NSE27_SHIFT                    (27U)
29110 /*! NSE27 - Nonsecure Enable
29111  *  0b0..Secure access
29112  *  0b1..Nonsecure access
29113  */
29114 #define GPIO_PCNS_NSE27(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE27_SHIFT)) & GPIO_PCNS_NSE27_MASK)
29115 
29116 #define GPIO_PCNS_NSE28_MASK                     (0x10000000U)
29117 #define GPIO_PCNS_NSE28_SHIFT                    (28U)
29118 /*! NSE28 - Nonsecure Enable
29119  *  0b0..Secure access
29120  *  0b1..Nonsecure access
29121  */
29122 #define GPIO_PCNS_NSE28(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE28_SHIFT)) & GPIO_PCNS_NSE28_MASK)
29123 
29124 #define GPIO_PCNS_NSE29_MASK                     (0x20000000U)
29125 #define GPIO_PCNS_NSE29_SHIFT                    (29U)
29126 /*! NSE29 - Nonsecure Enable
29127  *  0b0..Secure access
29128  *  0b1..Nonsecure access
29129  */
29130 #define GPIO_PCNS_NSE29(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE29_SHIFT)) & GPIO_PCNS_NSE29_MASK)
29131 
29132 #define GPIO_PCNS_NSE30_MASK                     (0x40000000U)
29133 #define GPIO_PCNS_NSE30_SHIFT                    (30U)
29134 /*! NSE30 - Nonsecure Enable
29135  *  0b0..Secure access
29136  *  0b1..Nonsecure access
29137  */
29138 #define GPIO_PCNS_NSE30(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE30_SHIFT)) & GPIO_PCNS_NSE30_MASK)
29139 
29140 #define GPIO_PCNS_NSE31_MASK                     (0x80000000U)
29141 #define GPIO_PCNS_NSE31_SHIFT                    (31U)
29142 /*! NSE31 - Nonsecure Enable
29143  *  0b0..Secure access
29144  *  0b1..Nonsecure access
29145  */
29146 #define GPIO_PCNS_NSE31(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE31_SHIFT)) & GPIO_PCNS_NSE31_MASK)
29147 /*! @} */
29148 
29149 /*! @name ICNS - Interrupt Control Nonsecure */
29150 /*! @{ */
29151 
29152 #define GPIO_ICNS_NSE0_MASK                      (0x1U)
29153 #define GPIO_ICNS_NSE0_SHIFT                     (0U)
29154 /*! NSE0 - Nonsecure Enable
29155  *  0b0..Secure access
29156  *  0b1..Nonsecure access
29157  */
29158 #define GPIO_ICNS_NSE0(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICNS_NSE0_SHIFT)) & GPIO_ICNS_NSE0_MASK)
29159 
29160 #define GPIO_ICNS_NSE1_MASK                      (0x2U)
29161 #define GPIO_ICNS_NSE1_SHIFT                     (1U)
29162 /*! NSE1 - Nonsecure Enable
29163  *  0b0..Secure access
29164  *  0b1..Nonsecure access
29165  */
29166 #define GPIO_ICNS_NSE1(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICNS_NSE1_SHIFT)) & GPIO_ICNS_NSE1_MASK)
29167 /*! @} */
29168 
29169 /*! @name PCNP - Pin Control Nonprivilege */
29170 /*! @{ */
29171 
29172 #define GPIO_PCNP_NPE0_MASK                      (0x1U)
29173 #define GPIO_PCNP_NPE0_SHIFT                     (0U)
29174 /*! NPE0 - Nonprivilege Enable
29175  *  0b0..Privilege access
29176  *  0b1..Nonprivilege access
29177  */
29178 #define GPIO_PCNP_NPE0(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE0_SHIFT)) & GPIO_PCNP_NPE0_MASK)
29179 
29180 #define GPIO_PCNP_NPE1_MASK                      (0x2U)
29181 #define GPIO_PCNP_NPE1_SHIFT                     (1U)
29182 /*! NPE1 - Nonprivilege Enable
29183  *  0b0..Privilege access
29184  *  0b1..Nonprivilege access
29185  */
29186 #define GPIO_PCNP_NPE1(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE1_SHIFT)) & GPIO_PCNP_NPE1_MASK)
29187 
29188 #define GPIO_PCNP_NPE2_MASK                      (0x4U)
29189 #define GPIO_PCNP_NPE2_SHIFT                     (2U)
29190 /*! NPE2 - Nonprivilege Enable
29191  *  0b0..Privilege access
29192  *  0b1..Nonprivilege access
29193  */
29194 #define GPIO_PCNP_NPE2(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE2_SHIFT)) & GPIO_PCNP_NPE2_MASK)
29195 
29196 #define GPIO_PCNP_NPE3_MASK                      (0x8U)
29197 #define GPIO_PCNP_NPE3_SHIFT                     (3U)
29198 /*! NPE3 - Nonprivilege Enable
29199  *  0b0..Privilege access
29200  *  0b1..Nonprivilege access
29201  */
29202 #define GPIO_PCNP_NPE3(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE3_SHIFT)) & GPIO_PCNP_NPE3_MASK)
29203 
29204 #define GPIO_PCNP_NPE4_MASK                      (0x10U)
29205 #define GPIO_PCNP_NPE4_SHIFT                     (4U)
29206 /*! NPE4 - Nonprivilege Enable
29207  *  0b0..Privilege access
29208  *  0b1..Nonprivilege access
29209  */
29210 #define GPIO_PCNP_NPE4(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE4_SHIFT)) & GPIO_PCNP_NPE4_MASK)
29211 
29212 #define GPIO_PCNP_NPE5_MASK                      (0x20U)
29213 #define GPIO_PCNP_NPE5_SHIFT                     (5U)
29214 /*! NPE5 - Nonprivilege Enable
29215  *  0b0..Privilege access
29216  *  0b1..Nonprivilege access
29217  */
29218 #define GPIO_PCNP_NPE5(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE5_SHIFT)) & GPIO_PCNP_NPE5_MASK)
29219 
29220 #define GPIO_PCNP_NPE6_MASK                      (0x40U)
29221 #define GPIO_PCNP_NPE6_SHIFT                     (6U)
29222 /*! NPE6 - Nonprivilege Enable
29223  *  0b0..Privilege access
29224  *  0b1..Nonprivilege access
29225  */
29226 #define GPIO_PCNP_NPE6(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE6_SHIFT)) & GPIO_PCNP_NPE6_MASK)
29227 
29228 #define GPIO_PCNP_NPE7_MASK                      (0x80U)
29229 #define GPIO_PCNP_NPE7_SHIFT                     (7U)
29230 /*! NPE7 - Nonprivilege Enable
29231  *  0b0..Privilege access
29232  *  0b1..Nonprivilege access
29233  */
29234 #define GPIO_PCNP_NPE7(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE7_SHIFT)) & GPIO_PCNP_NPE7_MASK)
29235 
29236 #define GPIO_PCNP_NPE8_MASK                      (0x100U)
29237 #define GPIO_PCNP_NPE8_SHIFT                     (8U)
29238 /*! NPE8 - Nonprivilege Enable
29239  *  0b0..Privilege access
29240  *  0b1..Nonprivilege access
29241  */
29242 #define GPIO_PCNP_NPE8(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE8_SHIFT)) & GPIO_PCNP_NPE8_MASK)
29243 
29244 #define GPIO_PCNP_NPE9_MASK                      (0x200U)
29245 #define GPIO_PCNP_NPE9_SHIFT                     (9U)
29246 /*! NPE9 - Nonprivilege Enable
29247  *  0b0..Privilege access
29248  *  0b1..Nonprivilege access
29249  */
29250 #define GPIO_PCNP_NPE9(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE9_SHIFT)) & GPIO_PCNP_NPE9_MASK)
29251 
29252 #define GPIO_PCNP_NPE10_MASK                     (0x400U)
29253 #define GPIO_PCNP_NPE10_SHIFT                    (10U)
29254 /*! NPE10 - Nonprivilege Enable
29255  *  0b0..Privilege access
29256  *  0b1..Nonprivilege access
29257  */
29258 #define GPIO_PCNP_NPE10(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE10_SHIFT)) & GPIO_PCNP_NPE10_MASK)
29259 
29260 #define GPIO_PCNP_NPE11_MASK                     (0x800U)
29261 #define GPIO_PCNP_NPE11_SHIFT                    (11U)
29262 /*! NPE11 - Nonprivilege Enable
29263  *  0b0..Privilege access
29264  *  0b1..Nonprivilege access
29265  */
29266 #define GPIO_PCNP_NPE11(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE11_SHIFT)) & GPIO_PCNP_NPE11_MASK)
29267 
29268 #define GPIO_PCNP_NPE12_MASK                     (0x1000U)
29269 #define GPIO_PCNP_NPE12_SHIFT                    (12U)
29270 /*! NPE12 - Nonprivilege Enable
29271  *  0b0..Privilege access
29272  *  0b1..Nonprivilege access
29273  */
29274 #define GPIO_PCNP_NPE12(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE12_SHIFT)) & GPIO_PCNP_NPE12_MASK)
29275 
29276 #define GPIO_PCNP_NPE13_MASK                     (0x2000U)
29277 #define GPIO_PCNP_NPE13_SHIFT                    (13U)
29278 /*! NPE13 - Nonprivilege Enable
29279  *  0b0..Privilege access
29280  *  0b1..Nonprivilege access
29281  */
29282 #define GPIO_PCNP_NPE13(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE13_SHIFT)) & GPIO_PCNP_NPE13_MASK)
29283 
29284 #define GPIO_PCNP_NPE14_MASK                     (0x4000U)
29285 #define GPIO_PCNP_NPE14_SHIFT                    (14U)
29286 /*! NPE14 - Nonprivilege Enable
29287  *  0b0..Privilege access
29288  *  0b1..Nonprivilege access
29289  */
29290 #define GPIO_PCNP_NPE14(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE14_SHIFT)) & GPIO_PCNP_NPE14_MASK)
29291 
29292 #define GPIO_PCNP_NPE15_MASK                     (0x8000U)
29293 #define GPIO_PCNP_NPE15_SHIFT                    (15U)
29294 /*! NPE15 - Nonprivilege Enable
29295  *  0b0..Privilege access
29296  *  0b1..Nonprivilege access
29297  */
29298 #define GPIO_PCNP_NPE15(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE15_SHIFT)) & GPIO_PCNP_NPE15_MASK)
29299 
29300 #define GPIO_PCNP_NPE16_MASK                     (0x10000U)
29301 #define GPIO_PCNP_NPE16_SHIFT                    (16U)
29302 /*! NPE16 - Nonprivilege Enable
29303  *  0b0..Privilege access
29304  *  0b1..Nonprivilege access
29305  */
29306 #define GPIO_PCNP_NPE16(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE16_SHIFT)) & GPIO_PCNP_NPE16_MASK)
29307 
29308 #define GPIO_PCNP_NPE17_MASK                     (0x20000U)
29309 #define GPIO_PCNP_NPE17_SHIFT                    (17U)
29310 /*! NPE17 - Nonprivilege Enable
29311  *  0b0..Privilege access
29312  *  0b1..Nonprivilege access
29313  */
29314 #define GPIO_PCNP_NPE17(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE17_SHIFT)) & GPIO_PCNP_NPE17_MASK)
29315 
29316 #define GPIO_PCNP_NPE18_MASK                     (0x40000U)
29317 #define GPIO_PCNP_NPE18_SHIFT                    (18U)
29318 /*! NPE18 - Nonprivilege Enable
29319  *  0b0..Privilege access
29320  *  0b1..Nonprivilege access
29321  */
29322 #define GPIO_PCNP_NPE18(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE18_SHIFT)) & GPIO_PCNP_NPE18_MASK)
29323 
29324 #define GPIO_PCNP_NPE19_MASK                     (0x80000U)
29325 #define GPIO_PCNP_NPE19_SHIFT                    (19U)
29326 /*! NPE19 - Nonprivilege Enable
29327  *  0b0..Privilege access
29328  *  0b1..Nonprivilege access
29329  */
29330 #define GPIO_PCNP_NPE19(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE19_SHIFT)) & GPIO_PCNP_NPE19_MASK)
29331 
29332 #define GPIO_PCNP_NPE20_MASK                     (0x100000U)
29333 #define GPIO_PCNP_NPE20_SHIFT                    (20U)
29334 /*! NPE20 - Nonprivilege Enable
29335  *  0b0..Privilege access
29336  *  0b1..Nonprivilege access
29337  */
29338 #define GPIO_PCNP_NPE20(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE20_SHIFT)) & GPIO_PCNP_NPE20_MASK)
29339 
29340 #define GPIO_PCNP_NPE21_MASK                     (0x200000U)
29341 #define GPIO_PCNP_NPE21_SHIFT                    (21U)
29342 /*! NPE21 - Nonprivilege Enable
29343  *  0b0..Privilege access
29344  *  0b1..Nonprivilege access
29345  */
29346 #define GPIO_PCNP_NPE21(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE21_SHIFT)) & GPIO_PCNP_NPE21_MASK)
29347 
29348 #define GPIO_PCNP_NPE22_MASK                     (0x400000U)
29349 #define GPIO_PCNP_NPE22_SHIFT                    (22U)
29350 /*! NPE22 - Nonprivilege Enable
29351  *  0b0..Privilege access
29352  *  0b1..Nonprivilege access
29353  */
29354 #define GPIO_PCNP_NPE22(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE22_SHIFT)) & GPIO_PCNP_NPE22_MASK)
29355 
29356 #define GPIO_PCNP_NPE23_MASK                     (0x800000U)
29357 #define GPIO_PCNP_NPE23_SHIFT                    (23U)
29358 /*! NPE23 - Nonprivilege Enable
29359  *  0b0..Privilege access
29360  *  0b1..Nonprivilege access
29361  */
29362 #define GPIO_PCNP_NPE23(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE23_SHIFT)) & GPIO_PCNP_NPE23_MASK)
29363 
29364 #define GPIO_PCNP_NPE24_MASK                     (0x1000000U)
29365 #define GPIO_PCNP_NPE24_SHIFT                    (24U)
29366 /*! NPE24 - Nonprivilege Enable
29367  *  0b0..Privilege access
29368  *  0b1..Nonprivilege access
29369  */
29370 #define GPIO_PCNP_NPE24(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE24_SHIFT)) & GPIO_PCNP_NPE24_MASK)
29371 
29372 #define GPIO_PCNP_NPE25_MASK                     (0x2000000U)
29373 #define GPIO_PCNP_NPE25_SHIFT                    (25U)
29374 /*! NPE25 - Nonprivilege Enable
29375  *  0b0..Privilege access
29376  *  0b1..Nonprivilege access
29377  */
29378 #define GPIO_PCNP_NPE25(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE25_SHIFT)) & GPIO_PCNP_NPE25_MASK)
29379 
29380 #define GPIO_PCNP_NPE26_MASK                     (0x4000000U)
29381 #define GPIO_PCNP_NPE26_SHIFT                    (26U)
29382 /*! NPE26 - Nonprivilege Enable
29383  *  0b0..Privilege access
29384  *  0b1..Nonprivilege access
29385  */
29386 #define GPIO_PCNP_NPE26(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE26_SHIFT)) & GPIO_PCNP_NPE26_MASK)
29387 
29388 #define GPIO_PCNP_NPE27_MASK                     (0x8000000U)
29389 #define GPIO_PCNP_NPE27_SHIFT                    (27U)
29390 /*! NPE27 - Nonprivilege Enable
29391  *  0b0..Privilege access
29392  *  0b1..Nonprivilege access
29393  */
29394 #define GPIO_PCNP_NPE27(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE27_SHIFT)) & GPIO_PCNP_NPE27_MASK)
29395 
29396 #define GPIO_PCNP_NPE28_MASK                     (0x10000000U)
29397 #define GPIO_PCNP_NPE28_SHIFT                    (28U)
29398 /*! NPE28 - Nonprivilege Enable
29399  *  0b0..Privilege access
29400  *  0b1..Nonprivilege access
29401  */
29402 #define GPIO_PCNP_NPE28(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE28_SHIFT)) & GPIO_PCNP_NPE28_MASK)
29403 
29404 #define GPIO_PCNP_NPE29_MASK                     (0x20000000U)
29405 #define GPIO_PCNP_NPE29_SHIFT                    (29U)
29406 /*! NPE29 - Nonprivilege Enable
29407  *  0b0..Privilege access
29408  *  0b1..Nonprivilege access
29409  */
29410 #define GPIO_PCNP_NPE29(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE29_SHIFT)) & GPIO_PCNP_NPE29_MASK)
29411 
29412 #define GPIO_PCNP_NPE30_MASK                     (0x40000000U)
29413 #define GPIO_PCNP_NPE30_SHIFT                    (30U)
29414 /*! NPE30 - Nonprivilege Enable
29415  *  0b0..Privilege access
29416  *  0b1..Nonprivilege access
29417  */
29418 #define GPIO_PCNP_NPE30(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE30_SHIFT)) & GPIO_PCNP_NPE30_MASK)
29419 
29420 #define GPIO_PCNP_NPE31_MASK                     (0x80000000U)
29421 #define GPIO_PCNP_NPE31_SHIFT                    (31U)
29422 /*! NPE31 - Nonprivilege Enable
29423  *  0b0..Privilege access
29424  *  0b1..Nonprivilege access
29425  */
29426 #define GPIO_PCNP_NPE31(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE31_SHIFT)) & GPIO_PCNP_NPE31_MASK)
29427 /*! @} */
29428 
29429 /*! @name ICNP - Interrupt Control Nonprivilege */
29430 /*! @{ */
29431 
29432 #define GPIO_ICNP_NPE0_MASK                      (0x1U)
29433 #define GPIO_ICNP_NPE0_SHIFT                     (0U)
29434 /*! NPE0 - Nonprivilege Enable
29435  *  0b0..Privilege access
29436  *  0b1..Nonprivilege access
29437  */
29438 #define GPIO_ICNP_NPE0(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICNP_NPE0_SHIFT)) & GPIO_ICNP_NPE0_MASK)
29439 
29440 #define GPIO_ICNP_NPE1_MASK                      (0x2U)
29441 #define GPIO_ICNP_NPE1_SHIFT                     (1U)
29442 /*! NPE1 - Nonprivilege Enable
29443  *  0b0..Privilege access
29444  *  0b1..Nonprivilege access
29445  */
29446 #define GPIO_ICNP_NPE1(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICNP_NPE1_SHIFT)) & GPIO_ICNP_NPE1_MASK)
29447 /*! @} */
29448 
29449 /*! @name PDOR - Port Data Output */
29450 /*! @{ */
29451 
29452 #define GPIO_PDOR_PDO0_MASK                      (0x1U)
29453 #define GPIO_PDOR_PDO0_SHIFT                     (0U)
29454 /*! PDO0 - Port Data Output
29455  *  0b0..Logic level 0
29456  *  0b1..Logic level 1
29457  */
29458 #define GPIO_PDOR_PDO0(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO0_SHIFT)) & GPIO_PDOR_PDO0_MASK)
29459 
29460 #define GPIO_PDOR_PDO1_MASK                      (0x2U)
29461 #define GPIO_PDOR_PDO1_SHIFT                     (1U)
29462 /*! PDO1 - Port Data Output
29463  *  0b0..Logic level 0
29464  *  0b1..Logic level 1
29465  */
29466 #define GPIO_PDOR_PDO1(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO1_SHIFT)) & GPIO_PDOR_PDO1_MASK)
29467 
29468 #define GPIO_PDOR_PDO2_MASK                      (0x4U)
29469 #define GPIO_PDOR_PDO2_SHIFT                     (2U)
29470 /*! PDO2 - Port Data Output
29471  *  0b0..Logic level 0
29472  *  0b1..Logic level 1
29473  */
29474 #define GPIO_PDOR_PDO2(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO2_SHIFT)) & GPIO_PDOR_PDO2_MASK)
29475 
29476 #define GPIO_PDOR_PDO3_MASK                      (0x8U)
29477 #define GPIO_PDOR_PDO3_SHIFT                     (3U)
29478 /*! PDO3 - Port Data Output
29479  *  0b0..Logic level 0
29480  *  0b1..Logic level 1
29481  */
29482 #define GPIO_PDOR_PDO3(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO3_SHIFT)) & GPIO_PDOR_PDO3_MASK)
29483 
29484 #define GPIO_PDOR_PDO4_MASK                      (0x10U)
29485 #define GPIO_PDOR_PDO4_SHIFT                     (4U)
29486 /*! PDO4 - Port Data Output
29487  *  0b0..Logic level 0
29488  *  0b1..Logic level 1
29489  */
29490 #define GPIO_PDOR_PDO4(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO4_SHIFT)) & GPIO_PDOR_PDO4_MASK)
29491 
29492 #define GPIO_PDOR_PDO5_MASK                      (0x20U)
29493 #define GPIO_PDOR_PDO5_SHIFT                     (5U)
29494 /*! PDO5 - Port Data Output
29495  *  0b0..Logic level 0
29496  *  0b1..Logic level 1
29497  */
29498 #define GPIO_PDOR_PDO5(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO5_SHIFT)) & GPIO_PDOR_PDO5_MASK)
29499 
29500 #define GPIO_PDOR_PDO6_MASK                      (0x40U)
29501 #define GPIO_PDOR_PDO6_SHIFT                     (6U)
29502 /*! PDO6 - Port Data Output
29503  *  0b0..Logic level 0
29504  *  0b1..Logic level 1
29505  */
29506 #define GPIO_PDOR_PDO6(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO6_SHIFT)) & GPIO_PDOR_PDO6_MASK)
29507 
29508 #define GPIO_PDOR_PDO7_MASK                      (0x80U)
29509 #define GPIO_PDOR_PDO7_SHIFT                     (7U)
29510 /*! PDO7 - Port Data Output
29511  *  0b0..Logic level 0
29512  *  0b1..Logic level 1
29513  */
29514 #define GPIO_PDOR_PDO7(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO7_SHIFT)) & GPIO_PDOR_PDO7_MASK)
29515 
29516 #define GPIO_PDOR_PDO8_MASK                      (0x100U)
29517 #define GPIO_PDOR_PDO8_SHIFT                     (8U)
29518 /*! PDO8 - Port Data Output
29519  *  0b0..Logic level 0
29520  *  0b1..Logic level 1
29521  */
29522 #define GPIO_PDOR_PDO8(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO8_SHIFT)) & GPIO_PDOR_PDO8_MASK)
29523 
29524 #define GPIO_PDOR_PDO9_MASK                      (0x200U)
29525 #define GPIO_PDOR_PDO9_SHIFT                     (9U)
29526 /*! PDO9 - Port Data Output
29527  *  0b0..Logic level 0
29528  *  0b1..Logic level 1
29529  */
29530 #define GPIO_PDOR_PDO9(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO9_SHIFT)) & GPIO_PDOR_PDO9_MASK)
29531 
29532 #define GPIO_PDOR_PDO10_MASK                     (0x400U)
29533 #define GPIO_PDOR_PDO10_SHIFT                    (10U)
29534 /*! PDO10 - Port Data Output
29535  *  0b0..Logic level 0
29536  *  0b1..Logic level 1
29537  */
29538 #define GPIO_PDOR_PDO10(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO10_SHIFT)) & GPIO_PDOR_PDO10_MASK)
29539 
29540 #define GPIO_PDOR_PDO11_MASK                     (0x800U)
29541 #define GPIO_PDOR_PDO11_SHIFT                    (11U)
29542 /*! PDO11 - Port Data Output
29543  *  0b0..Logic level 0
29544  *  0b1..Logic level 1
29545  */
29546 #define GPIO_PDOR_PDO11(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO11_SHIFT)) & GPIO_PDOR_PDO11_MASK)
29547 
29548 #define GPIO_PDOR_PDO12_MASK                     (0x1000U)
29549 #define GPIO_PDOR_PDO12_SHIFT                    (12U)
29550 /*! PDO12 - Port Data Output
29551  *  0b0..Logic level 0
29552  *  0b1..Logic level 1
29553  */
29554 #define GPIO_PDOR_PDO12(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO12_SHIFT)) & GPIO_PDOR_PDO12_MASK)
29555 
29556 #define GPIO_PDOR_PDO13_MASK                     (0x2000U)
29557 #define GPIO_PDOR_PDO13_SHIFT                    (13U)
29558 /*! PDO13 - Port Data Output
29559  *  0b0..Logic level 0
29560  *  0b1..Logic level 1
29561  */
29562 #define GPIO_PDOR_PDO13(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO13_SHIFT)) & GPIO_PDOR_PDO13_MASK)
29563 
29564 #define GPIO_PDOR_PDO14_MASK                     (0x4000U)
29565 #define GPIO_PDOR_PDO14_SHIFT                    (14U)
29566 /*! PDO14 - Port Data Output
29567  *  0b0..Logic level 0
29568  *  0b1..Logic level 1
29569  */
29570 #define GPIO_PDOR_PDO14(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO14_SHIFT)) & GPIO_PDOR_PDO14_MASK)
29571 
29572 #define GPIO_PDOR_PDO15_MASK                     (0x8000U)
29573 #define GPIO_PDOR_PDO15_SHIFT                    (15U)
29574 /*! PDO15 - Port Data Output
29575  *  0b0..Logic level 0
29576  *  0b1..Logic level 1
29577  */
29578 #define GPIO_PDOR_PDO15(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO15_SHIFT)) & GPIO_PDOR_PDO15_MASK)
29579 
29580 #define GPIO_PDOR_PDO16_MASK                     (0x10000U)
29581 #define GPIO_PDOR_PDO16_SHIFT                    (16U)
29582 /*! PDO16 - Port Data Output
29583  *  0b0..Logic level 0
29584  *  0b1..Logic level 1
29585  */
29586 #define GPIO_PDOR_PDO16(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO16_SHIFT)) & GPIO_PDOR_PDO16_MASK)
29587 
29588 #define GPIO_PDOR_PDO17_MASK                     (0x20000U)
29589 #define GPIO_PDOR_PDO17_SHIFT                    (17U)
29590 /*! PDO17 - Port Data Output
29591  *  0b0..Logic level 0
29592  *  0b1..Logic level 1
29593  */
29594 #define GPIO_PDOR_PDO17(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO17_SHIFT)) & GPIO_PDOR_PDO17_MASK)
29595 
29596 #define GPIO_PDOR_PDO18_MASK                     (0x40000U)
29597 #define GPIO_PDOR_PDO18_SHIFT                    (18U)
29598 /*! PDO18 - Port Data Output
29599  *  0b0..Logic level 0
29600  *  0b1..Logic level 1
29601  */
29602 #define GPIO_PDOR_PDO18(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO18_SHIFT)) & GPIO_PDOR_PDO18_MASK)
29603 
29604 #define GPIO_PDOR_PDO19_MASK                     (0x80000U)
29605 #define GPIO_PDOR_PDO19_SHIFT                    (19U)
29606 /*! PDO19 - Port Data Output
29607  *  0b0..Logic level 0
29608  *  0b1..Logic level 1
29609  */
29610 #define GPIO_PDOR_PDO19(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO19_SHIFT)) & GPIO_PDOR_PDO19_MASK)
29611 
29612 #define GPIO_PDOR_PDO20_MASK                     (0x100000U)
29613 #define GPIO_PDOR_PDO20_SHIFT                    (20U)
29614 /*! PDO20 - Port Data Output
29615  *  0b0..Logic level 0
29616  *  0b1..Logic level 1
29617  */
29618 #define GPIO_PDOR_PDO20(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO20_SHIFT)) & GPIO_PDOR_PDO20_MASK)
29619 
29620 #define GPIO_PDOR_PDO21_MASK                     (0x200000U)
29621 #define GPIO_PDOR_PDO21_SHIFT                    (21U)
29622 /*! PDO21 - Port Data Output
29623  *  0b0..Logic level 0
29624  *  0b1..Logic level 1
29625  */
29626 #define GPIO_PDOR_PDO21(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO21_SHIFT)) & GPIO_PDOR_PDO21_MASK)
29627 
29628 #define GPIO_PDOR_PDO22_MASK                     (0x400000U)
29629 #define GPIO_PDOR_PDO22_SHIFT                    (22U)
29630 /*! PDO22 - Port Data Output
29631  *  0b0..Logic level 0
29632  *  0b1..Logic level 1
29633  */
29634 #define GPIO_PDOR_PDO22(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO22_SHIFT)) & GPIO_PDOR_PDO22_MASK)
29635 
29636 #define GPIO_PDOR_PDO23_MASK                     (0x800000U)
29637 #define GPIO_PDOR_PDO23_SHIFT                    (23U)
29638 /*! PDO23 - Port Data Output
29639  *  0b0..Logic level 0
29640  *  0b1..Logic level 1
29641  */
29642 #define GPIO_PDOR_PDO23(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO23_SHIFT)) & GPIO_PDOR_PDO23_MASK)
29643 
29644 #define GPIO_PDOR_PDO24_MASK                     (0x1000000U)
29645 #define GPIO_PDOR_PDO24_SHIFT                    (24U)
29646 /*! PDO24 - Port Data Output
29647  *  0b0..Logic level 0
29648  *  0b1..Logic level 1
29649  */
29650 #define GPIO_PDOR_PDO24(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO24_SHIFT)) & GPIO_PDOR_PDO24_MASK)
29651 
29652 #define GPIO_PDOR_PDO25_MASK                     (0x2000000U)
29653 #define GPIO_PDOR_PDO25_SHIFT                    (25U)
29654 /*! PDO25 - Port Data Output
29655  *  0b0..Logic level 0
29656  *  0b1..Logic level 1
29657  */
29658 #define GPIO_PDOR_PDO25(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO25_SHIFT)) & GPIO_PDOR_PDO25_MASK)
29659 
29660 #define GPIO_PDOR_PDO26_MASK                     (0x4000000U)
29661 #define GPIO_PDOR_PDO26_SHIFT                    (26U)
29662 /*! PDO26 - Port Data Output
29663  *  0b0..Logic level 0
29664  *  0b1..Logic level 1
29665  */
29666 #define GPIO_PDOR_PDO26(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO26_SHIFT)) & GPIO_PDOR_PDO26_MASK)
29667 
29668 #define GPIO_PDOR_PDO27_MASK                     (0x8000000U)
29669 #define GPIO_PDOR_PDO27_SHIFT                    (27U)
29670 /*! PDO27 - Port Data Output
29671  *  0b0..Logic level 0
29672  *  0b1..Logic level 1
29673  */
29674 #define GPIO_PDOR_PDO27(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO27_SHIFT)) & GPIO_PDOR_PDO27_MASK)
29675 
29676 #define GPIO_PDOR_PDO28_MASK                     (0x10000000U)
29677 #define GPIO_PDOR_PDO28_SHIFT                    (28U)
29678 /*! PDO28 - Port Data Output
29679  *  0b0..Logic level 0
29680  *  0b1..Logic level 1
29681  */
29682 #define GPIO_PDOR_PDO28(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO28_SHIFT)) & GPIO_PDOR_PDO28_MASK)
29683 
29684 #define GPIO_PDOR_PDO29_MASK                     (0x20000000U)
29685 #define GPIO_PDOR_PDO29_SHIFT                    (29U)
29686 /*! PDO29 - Port Data Output
29687  *  0b0..Logic level 0
29688  *  0b1..Logic level 1
29689  */
29690 #define GPIO_PDOR_PDO29(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO29_SHIFT)) & GPIO_PDOR_PDO29_MASK)
29691 
29692 #define GPIO_PDOR_PDO30_MASK                     (0x40000000U)
29693 #define GPIO_PDOR_PDO30_SHIFT                    (30U)
29694 /*! PDO30 - Port Data Output
29695  *  0b0..Logic level 0
29696  *  0b1..Logic level 1
29697  */
29698 #define GPIO_PDOR_PDO30(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO30_SHIFT)) & GPIO_PDOR_PDO30_MASK)
29699 
29700 #define GPIO_PDOR_PDO31_MASK                     (0x80000000U)
29701 #define GPIO_PDOR_PDO31_SHIFT                    (31U)
29702 /*! PDO31 - Port Data Output
29703  *  0b0..Logic level 0
29704  *  0b1..Logic level 1
29705  */
29706 #define GPIO_PDOR_PDO31(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO31_SHIFT)) & GPIO_PDOR_PDO31_MASK)
29707 /*! @} */
29708 
29709 /*! @name PSOR - Port Set Output */
29710 /*! @{ */
29711 
29712 #define GPIO_PSOR_PTSO0_MASK                     (0x1U)
29713 #define GPIO_PSOR_PTSO0_SHIFT                    (0U)
29714 /*! PTSO0 - Port Set Output
29715  *  0b0..No change
29716  *  0b1..Corresponding field in PDOR becomes 1
29717  */
29718 #define GPIO_PSOR_PTSO0(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO0_SHIFT)) & GPIO_PSOR_PTSO0_MASK)
29719 
29720 #define GPIO_PSOR_PTSO1_MASK                     (0x2U)
29721 #define GPIO_PSOR_PTSO1_SHIFT                    (1U)
29722 /*! PTSO1 - Port Set Output
29723  *  0b0..No change
29724  *  0b1..Corresponding field in PDOR becomes 1
29725  */
29726 #define GPIO_PSOR_PTSO1(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO1_SHIFT)) & GPIO_PSOR_PTSO1_MASK)
29727 
29728 #define GPIO_PSOR_PTSO2_MASK                     (0x4U)
29729 #define GPIO_PSOR_PTSO2_SHIFT                    (2U)
29730 /*! PTSO2 - Port Set Output
29731  *  0b0..No change
29732  *  0b1..Corresponding field in PDOR becomes 1
29733  */
29734 #define GPIO_PSOR_PTSO2(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO2_SHIFT)) & GPIO_PSOR_PTSO2_MASK)
29735 
29736 #define GPIO_PSOR_PTSO3_MASK                     (0x8U)
29737 #define GPIO_PSOR_PTSO3_SHIFT                    (3U)
29738 /*! PTSO3 - Port Set Output
29739  *  0b0..No change
29740  *  0b1..Corresponding field in PDOR becomes 1
29741  */
29742 #define GPIO_PSOR_PTSO3(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO3_SHIFT)) & GPIO_PSOR_PTSO3_MASK)
29743 
29744 #define GPIO_PSOR_PTSO4_MASK                     (0x10U)
29745 #define GPIO_PSOR_PTSO4_SHIFT                    (4U)
29746 /*! PTSO4 - Port Set Output
29747  *  0b0..No change
29748  *  0b1..Corresponding field in PDOR becomes 1
29749  */
29750 #define GPIO_PSOR_PTSO4(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO4_SHIFT)) & GPIO_PSOR_PTSO4_MASK)
29751 
29752 #define GPIO_PSOR_PTSO5_MASK                     (0x20U)
29753 #define GPIO_PSOR_PTSO5_SHIFT                    (5U)
29754 /*! PTSO5 - Port Set Output
29755  *  0b0..No change
29756  *  0b1..Corresponding field in PDOR becomes 1
29757  */
29758 #define GPIO_PSOR_PTSO5(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO5_SHIFT)) & GPIO_PSOR_PTSO5_MASK)
29759 
29760 #define GPIO_PSOR_PTSO6_MASK                     (0x40U)
29761 #define GPIO_PSOR_PTSO6_SHIFT                    (6U)
29762 /*! PTSO6 - Port Set Output
29763  *  0b0..No change
29764  *  0b1..Corresponding field in PDOR becomes 1
29765  */
29766 #define GPIO_PSOR_PTSO6(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO6_SHIFT)) & GPIO_PSOR_PTSO6_MASK)
29767 
29768 #define GPIO_PSOR_PTSO7_MASK                     (0x80U)
29769 #define GPIO_PSOR_PTSO7_SHIFT                    (7U)
29770 /*! PTSO7 - Port Set Output
29771  *  0b0..No change
29772  *  0b1..Corresponding field in PDOR becomes 1
29773  */
29774 #define GPIO_PSOR_PTSO7(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO7_SHIFT)) & GPIO_PSOR_PTSO7_MASK)
29775 
29776 #define GPIO_PSOR_PTSO8_MASK                     (0x100U)
29777 #define GPIO_PSOR_PTSO8_SHIFT                    (8U)
29778 /*! PTSO8 - Port Set Output
29779  *  0b0..No change
29780  *  0b1..Corresponding field in PDOR becomes 1
29781  */
29782 #define GPIO_PSOR_PTSO8(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO8_SHIFT)) & GPIO_PSOR_PTSO8_MASK)
29783 
29784 #define GPIO_PSOR_PTSO9_MASK                     (0x200U)
29785 #define GPIO_PSOR_PTSO9_SHIFT                    (9U)
29786 /*! PTSO9 - Port Set Output
29787  *  0b0..No change
29788  *  0b1..Corresponding field in PDOR becomes 1
29789  */
29790 #define GPIO_PSOR_PTSO9(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO9_SHIFT)) & GPIO_PSOR_PTSO9_MASK)
29791 
29792 #define GPIO_PSOR_PTSO10_MASK                    (0x400U)
29793 #define GPIO_PSOR_PTSO10_SHIFT                   (10U)
29794 /*! PTSO10 - Port Set Output
29795  *  0b0..No change
29796  *  0b1..Corresponding field in PDOR becomes 1
29797  */
29798 #define GPIO_PSOR_PTSO10(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO10_SHIFT)) & GPIO_PSOR_PTSO10_MASK)
29799 
29800 #define GPIO_PSOR_PTSO11_MASK                    (0x800U)
29801 #define GPIO_PSOR_PTSO11_SHIFT                   (11U)
29802 /*! PTSO11 - Port Set Output
29803  *  0b0..No change
29804  *  0b1..Corresponding field in PDOR becomes 1
29805  */
29806 #define GPIO_PSOR_PTSO11(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO11_SHIFT)) & GPIO_PSOR_PTSO11_MASK)
29807 
29808 #define GPIO_PSOR_PTSO12_MASK                    (0x1000U)
29809 #define GPIO_PSOR_PTSO12_SHIFT                   (12U)
29810 /*! PTSO12 - Port Set Output
29811  *  0b0..No change
29812  *  0b1..Corresponding field in PDOR becomes 1
29813  */
29814 #define GPIO_PSOR_PTSO12(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO12_SHIFT)) & GPIO_PSOR_PTSO12_MASK)
29815 
29816 #define GPIO_PSOR_PTSO13_MASK                    (0x2000U)
29817 #define GPIO_PSOR_PTSO13_SHIFT                   (13U)
29818 /*! PTSO13 - Port Set Output
29819  *  0b0..No change
29820  *  0b1..Corresponding field in PDOR becomes 1
29821  */
29822 #define GPIO_PSOR_PTSO13(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO13_SHIFT)) & GPIO_PSOR_PTSO13_MASK)
29823 
29824 #define GPIO_PSOR_PTSO14_MASK                    (0x4000U)
29825 #define GPIO_PSOR_PTSO14_SHIFT                   (14U)
29826 /*! PTSO14 - Port Set Output
29827  *  0b0..No change
29828  *  0b1..Corresponding field in PDOR becomes 1
29829  */
29830 #define GPIO_PSOR_PTSO14(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO14_SHIFT)) & GPIO_PSOR_PTSO14_MASK)
29831 
29832 #define GPIO_PSOR_PTSO15_MASK                    (0x8000U)
29833 #define GPIO_PSOR_PTSO15_SHIFT                   (15U)
29834 /*! PTSO15 - Port Set Output
29835  *  0b0..No change
29836  *  0b1..Corresponding field in PDOR becomes 1
29837  */
29838 #define GPIO_PSOR_PTSO15(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO15_SHIFT)) & GPIO_PSOR_PTSO15_MASK)
29839 
29840 #define GPIO_PSOR_PTSO16_MASK                    (0x10000U)
29841 #define GPIO_PSOR_PTSO16_SHIFT                   (16U)
29842 /*! PTSO16 - Port Set Output
29843  *  0b0..No change
29844  *  0b1..Corresponding field in PDOR becomes 1
29845  */
29846 #define GPIO_PSOR_PTSO16(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO16_SHIFT)) & GPIO_PSOR_PTSO16_MASK)
29847 
29848 #define GPIO_PSOR_PTSO17_MASK                    (0x20000U)
29849 #define GPIO_PSOR_PTSO17_SHIFT                   (17U)
29850 /*! PTSO17 - Port Set Output
29851  *  0b0..No change
29852  *  0b1..Corresponding field in PDOR becomes 1
29853  */
29854 #define GPIO_PSOR_PTSO17(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO17_SHIFT)) & GPIO_PSOR_PTSO17_MASK)
29855 
29856 #define GPIO_PSOR_PTSO18_MASK                    (0x40000U)
29857 #define GPIO_PSOR_PTSO18_SHIFT                   (18U)
29858 /*! PTSO18 - Port Set Output
29859  *  0b0..No change
29860  *  0b1..Corresponding field in PDOR becomes 1
29861  */
29862 #define GPIO_PSOR_PTSO18(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO18_SHIFT)) & GPIO_PSOR_PTSO18_MASK)
29863 
29864 #define GPIO_PSOR_PTSO19_MASK                    (0x80000U)
29865 #define GPIO_PSOR_PTSO19_SHIFT                   (19U)
29866 /*! PTSO19 - Port Set Output
29867  *  0b0..No change
29868  *  0b1..Corresponding field in PDOR becomes 1
29869  */
29870 #define GPIO_PSOR_PTSO19(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO19_SHIFT)) & GPIO_PSOR_PTSO19_MASK)
29871 
29872 #define GPIO_PSOR_PTSO20_MASK                    (0x100000U)
29873 #define GPIO_PSOR_PTSO20_SHIFT                   (20U)
29874 /*! PTSO20 - Port Set Output
29875  *  0b0..No change
29876  *  0b1..Corresponding field in PDOR becomes 1
29877  */
29878 #define GPIO_PSOR_PTSO20(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO20_SHIFT)) & GPIO_PSOR_PTSO20_MASK)
29879 
29880 #define GPIO_PSOR_PTSO21_MASK                    (0x200000U)
29881 #define GPIO_PSOR_PTSO21_SHIFT                   (21U)
29882 /*! PTSO21 - Port Set Output
29883  *  0b0..No change
29884  *  0b1..Corresponding field in PDOR becomes 1
29885  */
29886 #define GPIO_PSOR_PTSO21(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO21_SHIFT)) & GPIO_PSOR_PTSO21_MASK)
29887 
29888 #define GPIO_PSOR_PTSO22_MASK                    (0x400000U)
29889 #define GPIO_PSOR_PTSO22_SHIFT                   (22U)
29890 /*! PTSO22 - Port Set Output
29891  *  0b0..No change
29892  *  0b1..Corresponding field in PDOR becomes 1
29893  */
29894 #define GPIO_PSOR_PTSO22(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO22_SHIFT)) & GPIO_PSOR_PTSO22_MASK)
29895 
29896 #define GPIO_PSOR_PTSO23_MASK                    (0x800000U)
29897 #define GPIO_PSOR_PTSO23_SHIFT                   (23U)
29898 /*! PTSO23 - Port Set Output
29899  *  0b0..No change
29900  *  0b1..Corresponding field in PDOR becomes 1
29901  */
29902 #define GPIO_PSOR_PTSO23(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO23_SHIFT)) & GPIO_PSOR_PTSO23_MASK)
29903 
29904 #define GPIO_PSOR_PTSO24_MASK                    (0x1000000U)
29905 #define GPIO_PSOR_PTSO24_SHIFT                   (24U)
29906 /*! PTSO24 - Port Set Output
29907  *  0b0..No change
29908  *  0b1..Corresponding field in PDOR becomes 1
29909  */
29910 #define GPIO_PSOR_PTSO24(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO24_SHIFT)) & GPIO_PSOR_PTSO24_MASK)
29911 
29912 #define GPIO_PSOR_PTSO25_MASK                    (0x2000000U)
29913 #define GPIO_PSOR_PTSO25_SHIFT                   (25U)
29914 /*! PTSO25 - Port Set Output
29915  *  0b0..No change
29916  *  0b1..Corresponding field in PDOR becomes 1
29917  */
29918 #define GPIO_PSOR_PTSO25(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO25_SHIFT)) & GPIO_PSOR_PTSO25_MASK)
29919 
29920 #define GPIO_PSOR_PTSO26_MASK                    (0x4000000U)
29921 #define GPIO_PSOR_PTSO26_SHIFT                   (26U)
29922 /*! PTSO26 - Port Set Output
29923  *  0b0..No change
29924  *  0b1..Corresponding field in PDOR becomes 1
29925  */
29926 #define GPIO_PSOR_PTSO26(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO26_SHIFT)) & GPIO_PSOR_PTSO26_MASK)
29927 
29928 #define GPIO_PSOR_PTSO27_MASK                    (0x8000000U)
29929 #define GPIO_PSOR_PTSO27_SHIFT                   (27U)
29930 /*! PTSO27 - Port Set Output
29931  *  0b0..No change
29932  *  0b1..Corresponding field in PDOR becomes 1
29933  */
29934 #define GPIO_PSOR_PTSO27(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO27_SHIFT)) & GPIO_PSOR_PTSO27_MASK)
29935 
29936 #define GPIO_PSOR_PTSO28_MASK                    (0x10000000U)
29937 #define GPIO_PSOR_PTSO28_SHIFT                   (28U)
29938 /*! PTSO28 - Port Set Output
29939  *  0b0..No change
29940  *  0b1..Corresponding field in PDOR becomes 1
29941  */
29942 #define GPIO_PSOR_PTSO28(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO28_SHIFT)) & GPIO_PSOR_PTSO28_MASK)
29943 
29944 #define GPIO_PSOR_PTSO29_MASK                    (0x20000000U)
29945 #define GPIO_PSOR_PTSO29_SHIFT                   (29U)
29946 /*! PTSO29 - Port Set Output
29947  *  0b0..No change
29948  *  0b1..Corresponding field in PDOR becomes 1
29949  */
29950 #define GPIO_PSOR_PTSO29(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO29_SHIFT)) & GPIO_PSOR_PTSO29_MASK)
29951 
29952 #define GPIO_PSOR_PTSO30_MASK                    (0x40000000U)
29953 #define GPIO_PSOR_PTSO30_SHIFT                   (30U)
29954 /*! PTSO30 - Port Set Output
29955  *  0b0..No change
29956  *  0b1..Corresponding field in PDOR becomes 1
29957  */
29958 #define GPIO_PSOR_PTSO30(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO30_SHIFT)) & GPIO_PSOR_PTSO30_MASK)
29959 
29960 #define GPIO_PSOR_PTSO31_MASK                    (0x80000000U)
29961 #define GPIO_PSOR_PTSO31_SHIFT                   (31U)
29962 /*! PTSO31 - Port Set Output
29963  *  0b0..No change
29964  *  0b1..Corresponding field in PDOR becomes 1
29965  */
29966 #define GPIO_PSOR_PTSO31(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO31_SHIFT)) & GPIO_PSOR_PTSO31_MASK)
29967 /*! @} */
29968 
29969 /*! @name PCOR - Port Clear Output */
29970 /*! @{ */
29971 
29972 #define GPIO_PCOR_PTCO0_MASK                     (0x1U)
29973 #define GPIO_PCOR_PTCO0_SHIFT                    (0U)
29974 /*! PTCO0 - Port Clear Output
29975  *  0b0..No change
29976  *  0b1..Corresponding field in PDOR becomes 0
29977  */
29978 #define GPIO_PCOR_PTCO0(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO0_SHIFT)) & GPIO_PCOR_PTCO0_MASK)
29979 
29980 #define GPIO_PCOR_PTCO1_MASK                     (0x2U)
29981 #define GPIO_PCOR_PTCO1_SHIFT                    (1U)
29982 /*! PTCO1 - Port Clear Output
29983  *  0b0..No change
29984  *  0b1..Corresponding field in PDOR becomes 0
29985  */
29986 #define GPIO_PCOR_PTCO1(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO1_SHIFT)) & GPIO_PCOR_PTCO1_MASK)
29987 
29988 #define GPIO_PCOR_PTCO2_MASK                     (0x4U)
29989 #define GPIO_PCOR_PTCO2_SHIFT                    (2U)
29990 /*! PTCO2 - Port Clear Output
29991  *  0b0..No change
29992  *  0b1..Corresponding field in PDOR becomes 0
29993  */
29994 #define GPIO_PCOR_PTCO2(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO2_SHIFT)) & GPIO_PCOR_PTCO2_MASK)
29995 
29996 #define GPIO_PCOR_PTCO3_MASK                     (0x8U)
29997 #define GPIO_PCOR_PTCO3_SHIFT                    (3U)
29998 /*! PTCO3 - Port Clear Output
29999  *  0b0..No change
30000  *  0b1..Corresponding field in PDOR becomes 0
30001  */
30002 #define GPIO_PCOR_PTCO3(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO3_SHIFT)) & GPIO_PCOR_PTCO3_MASK)
30003 
30004 #define GPIO_PCOR_PTCO4_MASK                     (0x10U)
30005 #define GPIO_PCOR_PTCO4_SHIFT                    (4U)
30006 /*! PTCO4 - Port Clear Output
30007  *  0b0..No change
30008  *  0b1..Corresponding field in PDOR becomes 0
30009  */
30010 #define GPIO_PCOR_PTCO4(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO4_SHIFT)) & GPIO_PCOR_PTCO4_MASK)
30011 
30012 #define GPIO_PCOR_PTCO5_MASK                     (0x20U)
30013 #define GPIO_PCOR_PTCO5_SHIFT                    (5U)
30014 /*! PTCO5 - Port Clear Output
30015  *  0b0..No change
30016  *  0b1..Corresponding field in PDOR becomes 0
30017  */
30018 #define GPIO_PCOR_PTCO5(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO5_SHIFT)) & GPIO_PCOR_PTCO5_MASK)
30019 
30020 #define GPIO_PCOR_PTCO6_MASK                     (0x40U)
30021 #define GPIO_PCOR_PTCO6_SHIFT                    (6U)
30022 /*! PTCO6 - Port Clear Output
30023  *  0b0..No change
30024  *  0b1..Corresponding field in PDOR becomes 0
30025  */
30026 #define GPIO_PCOR_PTCO6(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO6_SHIFT)) & GPIO_PCOR_PTCO6_MASK)
30027 
30028 #define GPIO_PCOR_PTCO7_MASK                     (0x80U)
30029 #define GPIO_PCOR_PTCO7_SHIFT                    (7U)
30030 /*! PTCO7 - Port Clear Output
30031  *  0b0..No change
30032  *  0b1..Corresponding field in PDOR becomes 0
30033  */
30034 #define GPIO_PCOR_PTCO7(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO7_SHIFT)) & GPIO_PCOR_PTCO7_MASK)
30035 
30036 #define GPIO_PCOR_PTCO8_MASK                     (0x100U)
30037 #define GPIO_PCOR_PTCO8_SHIFT                    (8U)
30038 /*! PTCO8 - Port Clear Output
30039  *  0b0..No change
30040  *  0b1..Corresponding field in PDOR becomes 0
30041  */
30042 #define GPIO_PCOR_PTCO8(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO8_SHIFT)) & GPIO_PCOR_PTCO8_MASK)
30043 
30044 #define GPIO_PCOR_PTCO9_MASK                     (0x200U)
30045 #define GPIO_PCOR_PTCO9_SHIFT                    (9U)
30046 /*! PTCO9 - Port Clear Output
30047  *  0b0..No change
30048  *  0b1..Corresponding field in PDOR becomes 0
30049  */
30050 #define GPIO_PCOR_PTCO9(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO9_SHIFT)) & GPIO_PCOR_PTCO9_MASK)
30051 
30052 #define GPIO_PCOR_PTCO10_MASK                    (0x400U)
30053 #define GPIO_PCOR_PTCO10_SHIFT                   (10U)
30054 /*! PTCO10 - Port Clear Output
30055  *  0b0..No change
30056  *  0b1..Corresponding field in PDOR becomes 0
30057  */
30058 #define GPIO_PCOR_PTCO10(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO10_SHIFT)) & GPIO_PCOR_PTCO10_MASK)
30059 
30060 #define GPIO_PCOR_PTCO11_MASK                    (0x800U)
30061 #define GPIO_PCOR_PTCO11_SHIFT                   (11U)
30062 /*! PTCO11 - Port Clear Output
30063  *  0b0..No change
30064  *  0b1..Corresponding field in PDOR becomes 0
30065  */
30066 #define GPIO_PCOR_PTCO11(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO11_SHIFT)) & GPIO_PCOR_PTCO11_MASK)
30067 
30068 #define GPIO_PCOR_PTCO12_MASK                    (0x1000U)
30069 #define GPIO_PCOR_PTCO12_SHIFT                   (12U)
30070 /*! PTCO12 - Port Clear Output
30071  *  0b0..No change
30072  *  0b1..Corresponding field in PDOR becomes 0
30073  */
30074 #define GPIO_PCOR_PTCO12(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO12_SHIFT)) & GPIO_PCOR_PTCO12_MASK)
30075 
30076 #define GPIO_PCOR_PTCO13_MASK                    (0x2000U)
30077 #define GPIO_PCOR_PTCO13_SHIFT                   (13U)
30078 /*! PTCO13 - Port Clear Output
30079  *  0b0..No change
30080  *  0b1..Corresponding field in PDOR becomes 0
30081  */
30082 #define GPIO_PCOR_PTCO13(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO13_SHIFT)) & GPIO_PCOR_PTCO13_MASK)
30083 
30084 #define GPIO_PCOR_PTCO14_MASK                    (0x4000U)
30085 #define GPIO_PCOR_PTCO14_SHIFT                   (14U)
30086 /*! PTCO14 - Port Clear Output
30087  *  0b0..No change
30088  *  0b1..Corresponding field in PDOR becomes 0
30089  */
30090 #define GPIO_PCOR_PTCO14(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO14_SHIFT)) & GPIO_PCOR_PTCO14_MASK)
30091 
30092 #define GPIO_PCOR_PTCO15_MASK                    (0x8000U)
30093 #define GPIO_PCOR_PTCO15_SHIFT                   (15U)
30094 /*! PTCO15 - Port Clear Output
30095  *  0b0..No change
30096  *  0b1..Corresponding field in PDOR becomes 0
30097  */
30098 #define GPIO_PCOR_PTCO15(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO15_SHIFT)) & GPIO_PCOR_PTCO15_MASK)
30099 
30100 #define GPIO_PCOR_PTCO16_MASK                    (0x10000U)
30101 #define GPIO_PCOR_PTCO16_SHIFT                   (16U)
30102 /*! PTCO16 - Port Clear Output
30103  *  0b0..No change
30104  *  0b1..Corresponding field in PDOR becomes 0
30105  */
30106 #define GPIO_PCOR_PTCO16(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO16_SHIFT)) & GPIO_PCOR_PTCO16_MASK)
30107 
30108 #define GPIO_PCOR_PTCO17_MASK                    (0x20000U)
30109 #define GPIO_PCOR_PTCO17_SHIFT                   (17U)
30110 /*! PTCO17 - Port Clear Output
30111  *  0b0..No change
30112  *  0b1..Corresponding field in PDOR becomes 0
30113  */
30114 #define GPIO_PCOR_PTCO17(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO17_SHIFT)) & GPIO_PCOR_PTCO17_MASK)
30115 
30116 #define GPIO_PCOR_PTCO18_MASK                    (0x40000U)
30117 #define GPIO_PCOR_PTCO18_SHIFT                   (18U)
30118 /*! PTCO18 - Port Clear Output
30119  *  0b0..No change
30120  *  0b1..Corresponding field in PDOR becomes 0
30121  */
30122 #define GPIO_PCOR_PTCO18(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO18_SHIFT)) & GPIO_PCOR_PTCO18_MASK)
30123 
30124 #define GPIO_PCOR_PTCO19_MASK                    (0x80000U)
30125 #define GPIO_PCOR_PTCO19_SHIFT                   (19U)
30126 /*! PTCO19 - Port Clear Output
30127  *  0b0..No change
30128  *  0b1..Corresponding field in PDOR becomes 0
30129  */
30130 #define GPIO_PCOR_PTCO19(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO19_SHIFT)) & GPIO_PCOR_PTCO19_MASK)
30131 
30132 #define GPIO_PCOR_PTCO20_MASK                    (0x100000U)
30133 #define GPIO_PCOR_PTCO20_SHIFT                   (20U)
30134 /*! PTCO20 - Port Clear Output
30135  *  0b0..No change
30136  *  0b1..Corresponding field in PDOR becomes 0
30137  */
30138 #define GPIO_PCOR_PTCO20(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO20_SHIFT)) & GPIO_PCOR_PTCO20_MASK)
30139 
30140 #define GPIO_PCOR_PTCO21_MASK                    (0x200000U)
30141 #define GPIO_PCOR_PTCO21_SHIFT                   (21U)
30142 /*! PTCO21 - Port Clear Output
30143  *  0b0..No change
30144  *  0b1..Corresponding field in PDOR becomes 0
30145  */
30146 #define GPIO_PCOR_PTCO21(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO21_SHIFT)) & GPIO_PCOR_PTCO21_MASK)
30147 
30148 #define GPIO_PCOR_PTCO22_MASK                    (0x400000U)
30149 #define GPIO_PCOR_PTCO22_SHIFT                   (22U)
30150 /*! PTCO22 - Port Clear Output
30151  *  0b0..No change
30152  *  0b1..Corresponding field in PDOR becomes 0
30153  */
30154 #define GPIO_PCOR_PTCO22(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO22_SHIFT)) & GPIO_PCOR_PTCO22_MASK)
30155 
30156 #define GPIO_PCOR_PTCO23_MASK                    (0x800000U)
30157 #define GPIO_PCOR_PTCO23_SHIFT                   (23U)
30158 /*! PTCO23 - Port Clear Output
30159  *  0b0..No change
30160  *  0b1..Corresponding field in PDOR becomes 0
30161  */
30162 #define GPIO_PCOR_PTCO23(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO23_SHIFT)) & GPIO_PCOR_PTCO23_MASK)
30163 
30164 #define GPIO_PCOR_PTCO24_MASK                    (0x1000000U)
30165 #define GPIO_PCOR_PTCO24_SHIFT                   (24U)
30166 /*! PTCO24 - Port Clear Output
30167  *  0b0..No change
30168  *  0b1..Corresponding field in PDOR becomes 0
30169  */
30170 #define GPIO_PCOR_PTCO24(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO24_SHIFT)) & GPIO_PCOR_PTCO24_MASK)
30171 
30172 #define GPIO_PCOR_PTCO25_MASK                    (0x2000000U)
30173 #define GPIO_PCOR_PTCO25_SHIFT                   (25U)
30174 /*! PTCO25 - Port Clear Output
30175  *  0b0..No change
30176  *  0b1..Corresponding field in PDOR becomes 0
30177  */
30178 #define GPIO_PCOR_PTCO25(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO25_SHIFT)) & GPIO_PCOR_PTCO25_MASK)
30179 
30180 #define GPIO_PCOR_PTCO26_MASK                    (0x4000000U)
30181 #define GPIO_PCOR_PTCO26_SHIFT                   (26U)
30182 /*! PTCO26 - Port Clear Output
30183  *  0b0..No change
30184  *  0b1..Corresponding field in PDOR becomes 0
30185  */
30186 #define GPIO_PCOR_PTCO26(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO26_SHIFT)) & GPIO_PCOR_PTCO26_MASK)
30187 
30188 #define GPIO_PCOR_PTCO27_MASK                    (0x8000000U)
30189 #define GPIO_PCOR_PTCO27_SHIFT                   (27U)
30190 /*! PTCO27 - Port Clear Output
30191  *  0b0..No change
30192  *  0b1..Corresponding field in PDOR becomes 0
30193  */
30194 #define GPIO_PCOR_PTCO27(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO27_SHIFT)) & GPIO_PCOR_PTCO27_MASK)
30195 
30196 #define GPIO_PCOR_PTCO28_MASK                    (0x10000000U)
30197 #define GPIO_PCOR_PTCO28_SHIFT                   (28U)
30198 /*! PTCO28 - Port Clear Output
30199  *  0b0..No change
30200  *  0b1..Corresponding field in PDOR becomes 0
30201  */
30202 #define GPIO_PCOR_PTCO28(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO28_SHIFT)) & GPIO_PCOR_PTCO28_MASK)
30203 
30204 #define GPIO_PCOR_PTCO29_MASK                    (0x20000000U)
30205 #define GPIO_PCOR_PTCO29_SHIFT                   (29U)
30206 /*! PTCO29 - Port Clear Output
30207  *  0b0..No change
30208  *  0b1..Corresponding field in PDOR becomes 0
30209  */
30210 #define GPIO_PCOR_PTCO29(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO29_SHIFT)) & GPIO_PCOR_PTCO29_MASK)
30211 
30212 #define GPIO_PCOR_PTCO30_MASK                    (0x40000000U)
30213 #define GPIO_PCOR_PTCO30_SHIFT                   (30U)
30214 /*! PTCO30 - Port Clear Output
30215  *  0b0..No change
30216  *  0b1..Corresponding field in PDOR becomes 0
30217  */
30218 #define GPIO_PCOR_PTCO30(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO30_SHIFT)) & GPIO_PCOR_PTCO30_MASK)
30219 
30220 #define GPIO_PCOR_PTCO31_MASK                    (0x80000000U)
30221 #define GPIO_PCOR_PTCO31_SHIFT                   (31U)
30222 /*! PTCO31 - Port Clear Output
30223  *  0b0..No change
30224  *  0b1..Corresponding field in PDOR becomes 0
30225  */
30226 #define GPIO_PCOR_PTCO31(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO31_SHIFT)) & GPIO_PCOR_PTCO31_MASK)
30227 /*! @} */
30228 
30229 /*! @name PTOR - Port Toggle Output */
30230 /*! @{ */
30231 
30232 #define GPIO_PTOR_PTTO0_MASK                     (0x1U)
30233 #define GPIO_PTOR_PTTO0_SHIFT                    (0U)
30234 /*! PTTO0 - Port Toggle Output
30235  *  0b0..No change
30236  *  0b1..Set to the inverse of its current logic state
30237  */
30238 #define GPIO_PTOR_PTTO0(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO0_SHIFT)) & GPIO_PTOR_PTTO0_MASK)
30239 
30240 #define GPIO_PTOR_PTTO1_MASK                     (0x2U)
30241 #define GPIO_PTOR_PTTO1_SHIFT                    (1U)
30242 /*! PTTO1 - Port Toggle Output
30243  *  0b0..No change
30244  *  0b1..Set to the inverse of its current logic state
30245  */
30246 #define GPIO_PTOR_PTTO1(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO1_SHIFT)) & GPIO_PTOR_PTTO1_MASK)
30247 
30248 #define GPIO_PTOR_PTTO2_MASK                     (0x4U)
30249 #define GPIO_PTOR_PTTO2_SHIFT                    (2U)
30250 /*! PTTO2 - Port Toggle Output
30251  *  0b0..No change
30252  *  0b1..Set to the inverse of its current logic state
30253  */
30254 #define GPIO_PTOR_PTTO2(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO2_SHIFT)) & GPIO_PTOR_PTTO2_MASK)
30255 
30256 #define GPIO_PTOR_PTTO3_MASK                     (0x8U)
30257 #define GPIO_PTOR_PTTO3_SHIFT                    (3U)
30258 /*! PTTO3 - Port Toggle Output
30259  *  0b0..No change
30260  *  0b1..Set to the inverse of its current logic state
30261  */
30262 #define GPIO_PTOR_PTTO3(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO3_SHIFT)) & GPIO_PTOR_PTTO3_MASK)
30263 
30264 #define GPIO_PTOR_PTTO4_MASK                     (0x10U)
30265 #define GPIO_PTOR_PTTO4_SHIFT                    (4U)
30266 /*! PTTO4 - Port Toggle Output
30267  *  0b0..No change
30268  *  0b1..Set to the inverse of its current logic state
30269  */
30270 #define GPIO_PTOR_PTTO4(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO4_SHIFT)) & GPIO_PTOR_PTTO4_MASK)
30271 
30272 #define GPIO_PTOR_PTTO5_MASK                     (0x20U)
30273 #define GPIO_PTOR_PTTO5_SHIFT                    (5U)
30274 /*! PTTO5 - Port Toggle Output
30275  *  0b0..No change
30276  *  0b1..Set to the inverse of its current logic state
30277  */
30278 #define GPIO_PTOR_PTTO5(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO5_SHIFT)) & GPIO_PTOR_PTTO5_MASK)
30279 
30280 #define GPIO_PTOR_PTTO6_MASK                     (0x40U)
30281 #define GPIO_PTOR_PTTO6_SHIFT                    (6U)
30282 /*! PTTO6 - Port Toggle Output
30283  *  0b0..No change
30284  *  0b1..Set to the inverse of its current logic state
30285  */
30286 #define GPIO_PTOR_PTTO6(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO6_SHIFT)) & GPIO_PTOR_PTTO6_MASK)
30287 
30288 #define GPIO_PTOR_PTTO7_MASK                     (0x80U)
30289 #define GPIO_PTOR_PTTO7_SHIFT                    (7U)
30290 /*! PTTO7 - Port Toggle Output
30291  *  0b0..No change
30292  *  0b1..Set to the inverse of its current logic state
30293  */
30294 #define GPIO_PTOR_PTTO7(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO7_SHIFT)) & GPIO_PTOR_PTTO7_MASK)
30295 
30296 #define GPIO_PTOR_PTTO8_MASK                     (0x100U)
30297 #define GPIO_PTOR_PTTO8_SHIFT                    (8U)
30298 /*! PTTO8 - Port Toggle Output
30299  *  0b0..No change
30300  *  0b1..Set to the inverse of its current logic state
30301  */
30302 #define GPIO_PTOR_PTTO8(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO8_SHIFT)) & GPIO_PTOR_PTTO8_MASK)
30303 
30304 #define GPIO_PTOR_PTTO9_MASK                     (0x200U)
30305 #define GPIO_PTOR_PTTO9_SHIFT                    (9U)
30306 /*! PTTO9 - Port Toggle Output
30307  *  0b0..No change
30308  *  0b1..Set to the inverse of its current logic state
30309  */
30310 #define GPIO_PTOR_PTTO9(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO9_SHIFT)) & GPIO_PTOR_PTTO9_MASK)
30311 
30312 #define GPIO_PTOR_PTTO10_MASK                    (0x400U)
30313 #define GPIO_PTOR_PTTO10_SHIFT                   (10U)
30314 /*! PTTO10 - Port Toggle Output
30315  *  0b0..No change
30316  *  0b1..Set to the inverse of its current logic state
30317  */
30318 #define GPIO_PTOR_PTTO10(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO10_SHIFT)) & GPIO_PTOR_PTTO10_MASK)
30319 
30320 #define GPIO_PTOR_PTTO11_MASK                    (0x800U)
30321 #define GPIO_PTOR_PTTO11_SHIFT                   (11U)
30322 /*! PTTO11 - Port Toggle Output
30323  *  0b0..No change
30324  *  0b1..Set to the inverse of its current logic state
30325  */
30326 #define GPIO_PTOR_PTTO11(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO11_SHIFT)) & GPIO_PTOR_PTTO11_MASK)
30327 
30328 #define GPIO_PTOR_PTTO12_MASK                    (0x1000U)
30329 #define GPIO_PTOR_PTTO12_SHIFT                   (12U)
30330 /*! PTTO12 - Port Toggle Output
30331  *  0b0..No change
30332  *  0b1..Set to the inverse of its current logic state
30333  */
30334 #define GPIO_PTOR_PTTO12(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO12_SHIFT)) & GPIO_PTOR_PTTO12_MASK)
30335 
30336 #define GPIO_PTOR_PTTO13_MASK                    (0x2000U)
30337 #define GPIO_PTOR_PTTO13_SHIFT                   (13U)
30338 /*! PTTO13 - Port Toggle Output
30339  *  0b0..No change
30340  *  0b1..Set to the inverse of its current logic state
30341  */
30342 #define GPIO_PTOR_PTTO13(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO13_SHIFT)) & GPIO_PTOR_PTTO13_MASK)
30343 
30344 #define GPIO_PTOR_PTTO14_MASK                    (0x4000U)
30345 #define GPIO_PTOR_PTTO14_SHIFT                   (14U)
30346 /*! PTTO14 - Port Toggle Output
30347  *  0b0..No change
30348  *  0b1..Set to the inverse of its current logic state
30349  */
30350 #define GPIO_PTOR_PTTO14(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO14_SHIFT)) & GPIO_PTOR_PTTO14_MASK)
30351 
30352 #define GPIO_PTOR_PTTO15_MASK                    (0x8000U)
30353 #define GPIO_PTOR_PTTO15_SHIFT                   (15U)
30354 /*! PTTO15 - Port Toggle Output
30355  *  0b0..No change
30356  *  0b1..Set to the inverse of its current logic state
30357  */
30358 #define GPIO_PTOR_PTTO15(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO15_SHIFT)) & GPIO_PTOR_PTTO15_MASK)
30359 
30360 #define GPIO_PTOR_PTTO16_MASK                    (0x10000U)
30361 #define GPIO_PTOR_PTTO16_SHIFT                   (16U)
30362 /*! PTTO16 - Port Toggle Output
30363  *  0b0..No change
30364  *  0b1..Set to the inverse of its current logic state
30365  */
30366 #define GPIO_PTOR_PTTO16(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO16_SHIFT)) & GPIO_PTOR_PTTO16_MASK)
30367 
30368 #define GPIO_PTOR_PTTO17_MASK                    (0x20000U)
30369 #define GPIO_PTOR_PTTO17_SHIFT                   (17U)
30370 /*! PTTO17 - Port Toggle Output
30371  *  0b0..No change
30372  *  0b1..Set to the inverse of its current logic state
30373  */
30374 #define GPIO_PTOR_PTTO17(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO17_SHIFT)) & GPIO_PTOR_PTTO17_MASK)
30375 
30376 #define GPIO_PTOR_PTTO18_MASK                    (0x40000U)
30377 #define GPIO_PTOR_PTTO18_SHIFT                   (18U)
30378 /*! PTTO18 - Port Toggle Output
30379  *  0b0..No change
30380  *  0b1..Set to the inverse of its current logic state
30381  */
30382 #define GPIO_PTOR_PTTO18(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO18_SHIFT)) & GPIO_PTOR_PTTO18_MASK)
30383 
30384 #define GPIO_PTOR_PTTO19_MASK                    (0x80000U)
30385 #define GPIO_PTOR_PTTO19_SHIFT                   (19U)
30386 /*! PTTO19 - Port Toggle Output
30387  *  0b0..No change
30388  *  0b1..Set to the inverse of its current logic state
30389  */
30390 #define GPIO_PTOR_PTTO19(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO19_SHIFT)) & GPIO_PTOR_PTTO19_MASK)
30391 
30392 #define GPIO_PTOR_PTTO20_MASK                    (0x100000U)
30393 #define GPIO_PTOR_PTTO20_SHIFT                   (20U)
30394 /*! PTTO20 - Port Toggle Output
30395  *  0b0..No change
30396  *  0b1..Set to the inverse of its current logic state
30397  */
30398 #define GPIO_PTOR_PTTO20(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO20_SHIFT)) & GPIO_PTOR_PTTO20_MASK)
30399 
30400 #define GPIO_PTOR_PTTO21_MASK                    (0x200000U)
30401 #define GPIO_PTOR_PTTO21_SHIFT                   (21U)
30402 /*! PTTO21 - Port Toggle Output
30403  *  0b0..No change
30404  *  0b1..Set to the inverse of its current logic state
30405  */
30406 #define GPIO_PTOR_PTTO21(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO21_SHIFT)) & GPIO_PTOR_PTTO21_MASK)
30407 
30408 #define GPIO_PTOR_PTTO22_MASK                    (0x400000U)
30409 #define GPIO_PTOR_PTTO22_SHIFT                   (22U)
30410 /*! PTTO22 - Port Toggle Output
30411  *  0b0..No change
30412  *  0b1..Set to the inverse of its current logic state
30413  */
30414 #define GPIO_PTOR_PTTO22(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO22_SHIFT)) & GPIO_PTOR_PTTO22_MASK)
30415 
30416 #define GPIO_PTOR_PTTO23_MASK                    (0x800000U)
30417 #define GPIO_PTOR_PTTO23_SHIFT                   (23U)
30418 /*! PTTO23 - Port Toggle Output
30419  *  0b0..No change
30420  *  0b1..Set to the inverse of its current logic state
30421  */
30422 #define GPIO_PTOR_PTTO23(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO23_SHIFT)) & GPIO_PTOR_PTTO23_MASK)
30423 
30424 #define GPIO_PTOR_PTTO24_MASK                    (0x1000000U)
30425 #define GPIO_PTOR_PTTO24_SHIFT                   (24U)
30426 /*! PTTO24 - Port Toggle Output
30427  *  0b0..No change
30428  *  0b1..Set to the inverse of its current logic state
30429  */
30430 #define GPIO_PTOR_PTTO24(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO24_SHIFT)) & GPIO_PTOR_PTTO24_MASK)
30431 
30432 #define GPIO_PTOR_PTTO25_MASK                    (0x2000000U)
30433 #define GPIO_PTOR_PTTO25_SHIFT                   (25U)
30434 /*! PTTO25 - Port Toggle Output
30435  *  0b0..No change
30436  *  0b1..Set to the inverse of its current logic state
30437  */
30438 #define GPIO_PTOR_PTTO25(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO25_SHIFT)) & GPIO_PTOR_PTTO25_MASK)
30439 
30440 #define GPIO_PTOR_PTTO26_MASK                    (0x4000000U)
30441 #define GPIO_PTOR_PTTO26_SHIFT                   (26U)
30442 /*! PTTO26 - Port Toggle Output
30443  *  0b0..No change
30444  *  0b1..Set to the inverse of its current logic state
30445  */
30446 #define GPIO_PTOR_PTTO26(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO26_SHIFT)) & GPIO_PTOR_PTTO26_MASK)
30447 
30448 #define GPIO_PTOR_PTTO27_MASK                    (0x8000000U)
30449 #define GPIO_PTOR_PTTO27_SHIFT                   (27U)
30450 /*! PTTO27 - Port Toggle Output
30451  *  0b0..No change
30452  *  0b1..Set to the inverse of its current logic state
30453  */
30454 #define GPIO_PTOR_PTTO27(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO27_SHIFT)) & GPIO_PTOR_PTTO27_MASK)
30455 
30456 #define GPIO_PTOR_PTTO28_MASK                    (0x10000000U)
30457 #define GPIO_PTOR_PTTO28_SHIFT                   (28U)
30458 /*! PTTO28 - Port Toggle Output
30459  *  0b0..No change
30460  *  0b1..Set to the inverse of its current logic state
30461  */
30462 #define GPIO_PTOR_PTTO28(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO28_SHIFT)) & GPIO_PTOR_PTTO28_MASK)
30463 
30464 #define GPIO_PTOR_PTTO29_MASK                    (0x20000000U)
30465 #define GPIO_PTOR_PTTO29_SHIFT                   (29U)
30466 /*! PTTO29 - Port Toggle Output
30467  *  0b0..No change
30468  *  0b1..Set to the inverse of its current logic state
30469  */
30470 #define GPIO_PTOR_PTTO29(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO29_SHIFT)) & GPIO_PTOR_PTTO29_MASK)
30471 
30472 #define GPIO_PTOR_PTTO30_MASK                    (0x40000000U)
30473 #define GPIO_PTOR_PTTO30_SHIFT                   (30U)
30474 /*! PTTO30 - Port Toggle Output
30475  *  0b0..No change
30476  *  0b1..Set to the inverse of its current logic state
30477  */
30478 #define GPIO_PTOR_PTTO30(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO30_SHIFT)) & GPIO_PTOR_PTTO30_MASK)
30479 
30480 #define GPIO_PTOR_PTTO31_MASK                    (0x80000000U)
30481 #define GPIO_PTOR_PTTO31_SHIFT                   (31U)
30482 /*! PTTO31 - Port Toggle Output
30483  *  0b0..No change
30484  *  0b1..Set to the inverse of its current logic state
30485  */
30486 #define GPIO_PTOR_PTTO31(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO31_SHIFT)) & GPIO_PTOR_PTTO31_MASK)
30487 /*! @} */
30488 
30489 /*! @name PDIR - Port Data Input */
30490 /*! @{ */
30491 
30492 #define GPIO_PDIR_PDI0_MASK                      (0x1U)
30493 #define GPIO_PDIR_PDI0_SHIFT                     (0U)
30494 /*! PDI0 - Port Data Input
30495  *  0b0..Logic 0
30496  *  0b1..Logic 1
30497  */
30498 #define GPIO_PDIR_PDI0(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI0_SHIFT)) & GPIO_PDIR_PDI0_MASK)
30499 
30500 #define GPIO_PDIR_PDI1_MASK                      (0x2U)
30501 #define GPIO_PDIR_PDI1_SHIFT                     (1U)
30502 /*! PDI1 - Port Data Input
30503  *  0b0..Logic 0
30504  *  0b1..Logic 1
30505  */
30506 #define GPIO_PDIR_PDI1(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI1_SHIFT)) & GPIO_PDIR_PDI1_MASK)
30507 
30508 #define GPIO_PDIR_PDI2_MASK                      (0x4U)
30509 #define GPIO_PDIR_PDI2_SHIFT                     (2U)
30510 /*! PDI2 - Port Data Input
30511  *  0b0..Logic 0
30512  *  0b1..Logic 1
30513  */
30514 #define GPIO_PDIR_PDI2(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI2_SHIFT)) & GPIO_PDIR_PDI2_MASK)
30515 
30516 #define GPIO_PDIR_PDI3_MASK                      (0x8U)
30517 #define GPIO_PDIR_PDI3_SHIFT                     (3U)
30518 /*! PDI3 - Port Data Input
30519  *  0b0..Logic 0
30520  *  0b1..Logic 1
30521  */
30522 #define GPIO_PDIR_PDI3(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI3_SHIFT)) & GPIO_PDIR_PDI3_MASK)
30523 
30524 #define GPIO_PDIR_PDI4_MASK                      (0x10U)
30525 #define GPIO_PDIR_PDI4_SHIFT                     (4U)
30526 /*! PDI4 - Port Data Input
30527  *  0b0..Logic 0
30528  *  0b1..Logic 1
30529  */
30530 #define GPIO_PDIR_PDI4(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI4_SHIFT)) & GPIO_PDIR_PDI4_MASK)
30531 
30532 #define GPIO_PDIR_PDI5_MASK                      (0x20U)
30533 #define GPIO_PDIR_PDI5_SHIFT                     (5U)
30534 /*! PDI5 - Port Data Input
30535  *  0b0..Logic 0
30536  *  0b1..Logic 1
30537  */
30538 #define GPIO_PDIR_PDI5(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI5_SHIFT)) & GPIO_PDIR_PDI5_MASK)
30539 
30540 #define GPIO_PDIR_PDI6_MASK                      (0x40U)
30541 #define GPIO_PDIR_PDI6_SHIFT                     (6U)
30542 /*! PDI6 - Port Data Input
30543  *  0b0..Logic 0
30544  *  0b1..Logic 1
30545  */
30546 #define GPIO_PDIR_PDI6(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI6_SHIFT)) & GPIO_PDIR_PDI6_MASK)
30547 
30548 #define GPIO_PDIR_PDI7_MASK                      (0x80U)
30549 #define GPIO_PDIR_PDI7_SHIFT                     (7U)
30550 /*! PDI7 - Port Data Input
30551  *  0b0..Logic 0
30552  *  0b1..Logic 1
30553  */
30554 #define GPIO_PDIR_PDI7(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI7_SHIFT)) & GPIO_PDIR_PDI7_MASK)
30555 
30556 #define GPIO_PDIR_PDI8_MASK                      (0x100U)
30557 #define GPIO_PDIR_PDI8_SHIFT                     (8U)
30558 /*! PDI8 - Port Data Input
30559  *  0b0..Logic 0
30560  *  0b1..Logic 1
30561  */
30562 #define GPIO_PDIR_PDI8(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI8_SHIFT)) & GPIO_PDIR_PDI8_MASK)
30563 
30564 #define GPIO_PDIR_PDI9_MASK                      (0x200U)
30565 #define GPIO_PDIR_PDI9_SHIFT                     (9U)
30566 /*! PDI9 - Port Data Input
30567  *  0b0..Logic 0
30568  *  0b1..Logic 1
30569  */
30570 #define GPIO_PDIR_PDI9(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI9_SHIFT)) & GPIO_PDIR_PDI9_MASK)
30571 
30572 #define GPIO_PDIR_PDI10_MASK                     (0x400U)
30573 #define GPIO_PDIR_PDI10_SHIFT                    (10U)
30574 /*! PDI10 - Port Data Input
30575  *  0b0..Logic 0
30576  *  0b1..Logic 1
30577  */
30578 #define GPIO_PDIR_PDI10(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI10_SHIFT)) & GPIO_PDIR_PDI10_MASK)
30579 
30580 #define GPIO_PDIR_PDI11_MASK                     (0x800U)
30581 #define GPIO_PDIR_PDI11_SHIFT                    (11U)
30582 /*! PDI11 - Port Data Input
30583  *  0b0..Logic 0
30584  *  0b1..Logic 1
30585  */
30586 #define GPIO_PDIR_PDI11(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI11_SHIFT)) & GPIO_PDIR_PDI11_MASK)
30587 
30588 #define GPIO_PDIR_PDI12_MASK                     (0x1000U)
30589 #define GPIO_PDIR_PDI12_SHIFT                    (12U)
30590 /*! PDI12 - Port Data Input
30591  *  0b0..Logic 0
30592  *  0b1..Logic 1
30593  */
30594 #define GPIO_PDIR_PDI12(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI12_SHIFT)) & GPIO_PDIR_PDI12_MASK)
30595 
30596 #define GPIO_PDIR_PDI13_MASK                     (0x2000U)
30597 #define GPIO_PDIR_PDI13_SHIFT                    (13U)
30598 /*! PDI13 - Port Data Input
30599  *  0b0..Logic 0
30600  *  0b1..Logic 1
30601  */
30602 #define GPIO_PDIR_PDI13(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI13_SHIFT)) & GPIO_PDIR_PDI13_MASK)
30603 
30604 #define GPIO_PDIR_PDI14_MASK                     (0x4000U)
30605 #define GPIO_PDIR_PDI14_SHIFT                    (14U)
30606 /*! PDI14 - Port Data Input
30607  *  0b0..Logic 0
30608  *  0b1..Logic 1
30609  */
30610 #define GPIO_PDIR_PDI14(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI14_SHIFT)) & GPIO_PDIR_PDI14_MASK)
30611 
30612 #define GPIO_PDIR_PDI15_MASK                     (0x8000U)
30613 #define GPIO_PDIR_PDI15_SHIFT                    (15U)
30614 /*! PDI15 - Port Data Input
30615  *  0b0..Logic 0
30616  *  0b1..Logic 1
30617  */
30618 #define GPIO_PDIR_PDI15(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI15_SHIFT)) & GPIO_PDIR_PDI15_MASK)
30619 
30620 #define GPIO_PDIR_PDI16_MASK                     (0x10000U)
30621 #define GPIO_PDIR_PDI16_SHIFT                    (16U)
30622 /*! PDI16 - Port Data Input
30623  *  0b0..Logic 0
30624  *  0b1..Logic 1
30625  */
30626 #define GPIO_PDIR_PDI16(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI16_SHIFT)) & GPIO_PDIR_PDI16_MASK)
30627 
30628 #define GPIO_PDIR_PDI17_MASK                     (0x20000U)
30629 #define GPIO_PDIR_PDI17_SHIFT                    (17U)
30630 /*! PDI17 - Port Data Input
30631  *  0b0..Logic 0
30632  *  0b1..Logic 1
30633  */
30634 #define GPIO_PDIR_PDI17(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI17_SHIFT)) & GPIO_PDIR_PDI17_MASK)
30635 
30636 #define GPIO_PDIR_PDI18_MASK                     (0x40000U)
30637 #define GPIO_PDIR_PDI18_SHIFT                    (18U)
30638 /*! PDI18 - Port Data Input
30639  *  0b0..Logic 0
30640  *  0b1..Logic 1
30641  */
30642 #define GPIO_PDIR_PDI18(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI18_SHIFT)) & GPIO_PDIR_PDI18_MASK)
30643 
30644 #define GPIO_PDIR_PDI19_MASK                     (0x80000U)
30645 #define GPIO_PDIR_PDI19_SHIFT                    (19U)
30646 /*! PDI19 - Port Data Input
30647  *  0b0..Logic 0
30648  *  0b1..Logic 1
30649  */
30650 #define GPIO_PDIR_PDI19(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI19_SHIFT)) & GPIO_PDIR_PDI19_MASK)
30651 
30652 #define GPIO_PDIR_PDI20_MASK                     (0x100000U)
30653 #define GPIO_PDIR_PDI20_SHIFT                    (20U)
30654 /*! PDI20 - Port Data Input
30655  *  0b0..Logic 0
30656  *  0b1..Logic 1
30657  */
30658 #define GPIO_PDIR_PDI20(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI20_SHIFT)) & GPIO_PDIR_PDI20_MASK)
30659 
30660 #define GPIO_PDIR_PDI21_MASK                     (0x200000U)
30661 #define GPIO_PDIR_PDI21_SHIFT                    (21U)
30662 /*! PDI21 - Port Data Input
30663  *  0b0..Logic 0
30664  *  0b1..Logic 1
30665  */
30666 #define GPIO_PDIR_PDI21(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI21_SHIFT)) & GPIO_PDIR_PDI21_MASK)
30667 
30668 #define GPIO_PDIR_PDI22_MASK                     (0x400000U)
30669 #define GPIO_PDIR_PDI22_SHIFT                    (22U)
30670 /*! PDI22 - Port Data Input
30671  *  0b0..Logic 0
30672  *  0b1..Logic 1
30673  */
30674 #define GPIO_PDIR_PDI22(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI22_SHIFT)) & GPIO_PDIR_PDI22_MASK)
30675 
30676 #define GPIO_PDIR_PDI23_MASK                     (0x800000U)
30677 #define GPIO_PDIR_PDI23_SHIFT                    (23U)
30678 /*! PDI23 - Port Data Input
30679  *  0b0..Logic 0
30680  *  0b1..Logic 1
30681  */
30682 #define GPIO_PDIR_PDI23(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI23_SHIFT)) & GPIO_PDIR_PDI23_MASK)
30683 
30684 #define GPIO_PDIR_PDI24_MASK                     (0x1000000U)
30685 #define GPIO_PDIR_PDI24_SHIFT                    (24U)
30686 /*! PDI24 - Port Data Input
30687  *  0b0..Logic 0
30688  *  0b1..Logic 1
30689  */
30690 #define GPIO_PDIR_PDI24(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI24_SHIFT)) & GPIO_PDIR_PDI24_MASK)
30691 
30692 #define GPIO_PDIR_PDI25_MASK                     (0x2000000U)
30693 #define GPIO_PDIR_PDI25_SHIFT                    (25U)
30694 /*! PDI25 - Port Data Input
30695  *  0b0..Logic 0
30696  *  0b1..Logic 1
30697  */
30698 #define GPIO_PDIR_PDI25(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI25_SHIFT)) & GPIO_PDIR_PDI25_MASK)
30699 
30700 #define GPIO_PDIR_PDI26_MASK                     (0x4000000U)
30701 #define GPIO_PDIR_PDI26_SHIFT                    (26U)
30702 /*! PDI26 - Port Data Input
30703  *  0b0..Logic 0
30704  *  0b1..Logic 1
30705  */
30706 #define GPIO_PDIR_PDI26(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI26_SHIFT)) & GPIO_PDIR_PDI26_MASK)
30707 
30708 #define GPIO_PDIR_PDI27_MASK                     (0x8000000U)
30709 #define GPIO_PDIR_PDI27_SHIFT                    (27U)
30710 /*! PDI27 - Port Data Input
30711  *  0b0..Logic 0
30712  *  0b1..Logic 1
30713  */
30714 #define GPIO_PDIR_PDI27(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI27_SHIFT)) & GPIO_PDIR_PDI27_MASK)
30715 
30716 #define GPIO_PDIR_PDI28_MASK                     (0x10000000U)
30717 #define GPIO_PDIR_PDI28_SHIFT                    (28U)
30718 /*! PDI28 - Port Data Input
30719  *  0b0..Logic 0
30720  *  0b1..Logic 1
30721  */
30722 #define GPIO_PDIR_PDI28(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI28_SHIFT)) & GPIO_PDIR_PDI28_MASK)
30723 
30724 #define GPIO_PDIR_PDI29_MASK                     (0x20000000U)
30725 #define GPIO_PDIR_PDI29_SHIFT                    (29U)
30726 /*! PDI29 - Port Data Input
30727  *  0b0..Logic 0
30728  *  0b1..Logic 1
30729  */
30730 #define GPIO_PDIR_PDI29(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI29_SHIFT)) & GPIO_PDIR_PDI29_MASK)
30731 
30732 #define GPIO_PDIR_PDI30_MASK                     (0x40000000U)
30733 #define GPIO_PDIR_PDI30_SHIFT                    (30U)
30734 /*! PDI30 - Port Data Input
30735  *  0b0..Logic 0
30736  *  0b1..Logic 1
30737  */
30738 #define GPIO_PDIR_PDI30(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI30_SHIFT)) & GPIO_PDIR_PDI30_MASK)
30739 
30740 #define GPIO_PDIR_PDI31_MASK                     (0x80000000U)
30741 #define GPIO_PDIR_PDI31_SHIFT                    (31U)
30742 /*! PDI31 - Port Data Input
30743  *  0b0..Logic 0
30744  *  0b1..Logic 1
30745  */
30746 #define GPIO_PDIR_PDI31(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI31_SHIFT)) & GPIO_PDIR_PDI31_MASK)
30747 /*! @} */
30748 
30749 /*! @name PDDR - Port Data Direction */
30750 /*! @{ */
30751 
30752 #define GPIO_PDDR_PDD0_MASK                      (0x1U)
30753 #define GPIO_PDDR_PDD0_SHIFT                     (0U)
30754 /*! PDD0 - Port Data Direction
30755  *  0b0..Input
30756  *  0b1..Output
30757  */
30758 #define GPIO_PDDR_PDD0(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD0_SHIFT)) & GPIO_PDDR_PDD0_MASK)
30759 
30760 #define GPIO_PDDR_PDD1_MASK                      (0x2U)
30761 #define GPIO_PDDR_PDD1_SHIFT                     (1U)
30762 /*! PDD1 - Port Data Direction
30763  *  0b0..Input
30764  *  0b1..Output
30765  */
30766 #define GPIO_PDDR_PDD1(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD1_SHIFT)) & GPIO_PDDR_PDD1_MASK)
30767 
30768 #define GPIO_PDDR_PDD2_MASK                      (0x4U)
30769 #define GPIO_PDDR_PDD2_SHIFT                     (2U)
30770 /*! PDD2 - Port Data Direction
30771  *  0b0..Input
30772  *  0b1..Output
30773  */
30774 #define GPIO_PDDR_PDD2(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD2_SHIFT)) & GPIO_PDDR_PDD2_MASK)
30775 
30776 #define GPIO_PDDR_PDD3_MASK                      (0x8U)
30777 #define GPIO_PDDR_PDD3_SHIFT                     (3U)
30778 /*! PDD3 - Port Data Direction
30779  *  0b0..Input
30780  *  0b1..Output
30781  */
30782 #define GPIO_PDDR_PDD3(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD3_SHIFT)) & GPIO_PDDR_PDD3_MASK)
30783 
30784 #define GPIO_PDDR_PDD4_MASK                      (0x10U)
30785 #define GPIO_PDDR_PDD4_SHIFT                     (4U)
30786 /*! PDD4 - Port Data Direction
30787  *  0b0..Input
30788  *  0b1..Output
30789  */
30790 #define GPIO_PDDR_PDD4(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD4_SHIFT)) & GPIO_PDDR_PDD4_MASK)
30791 
30792 #define GPIO_PDDR_PDD5_MASK                      (0x20U)
30793 #define GPIO_PDDR_PDD5_SHIFT                     (5U)
30794 /*! PDD5 - Port Data Direction
30795  *  0b0..Input
30796  *  0b1..Output
30797  */
30798 #define GPIO_PDDR_PDD5(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD5_SHIFT)) & GPIO_PDDR_PDD5_MASK)
30799 
30800 #define GPIO_PDDR_PDD6_MASK                      (0x40U)
30801 #define GPIO_PDDR_PDD6_SHIFT                     (6U)
30802 /*! PDD6 - Port Data Direction
30803  *  0b0..Input
30804  *  0b1..Output
30805  */
30806 #define GPIO_PDDR_PDD6(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD6_SHIFT)) & GPIO_PDDR_PDD6_MASK)
30807 
30808 #define GPIO_PDDR_PDD7_MASK                      (0x80U)
30809 #define GPIO_PDDR_PDD7_SHIFT                     (7U)
30810 /*! PDD7 - Port Data Direction
30811  *  0b0..Input
30812  *  0b1..Output
30813  */
30814 #define GPIO_PDDR_PDD7(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD7_SHIFT)) & GPIO_PDDR_PDD7_MASK)
30815 
30816 #define GPIO_PDDR_PDD8_MASK                      (0x100U)
30817 #define GPIO_PDDR_PDD8_SHIFT                     (8U)
30818 /*! PDD8 - Port Data Direction
30819  *  0b0..Input
30820  *  0b1..Output
30821  */
30822 #define GPIO_PDDR_PDD8(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD8_SHIFT)) & GPIO_PDDR_PDD8_MASK)
30823 
30824 #define GPIO_PDDR_PDD9_MASK                      (0x200U)
30825 #define GPIO_PDDR_PDD9_SHIFT                     (9U)
30826 /*! PDD9 - Port Data Direction
30827  *  0b0..Input
30828  *  0b1..Output
30829  */
30830 #define GPIO_PDDR_PDD9(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD9_SHIFT)) & GPIO_PDDR_PDD9_MASK)
30831 
30832 #define GPIO_PDDR_PDD10_MASK                     (0x400U)
30833 #define GPIO_PDDR_PDD10_SHIFT                    (10U)
30834 /*! PDD10 - Port Data Direction
30835  *  0b0..Input
30836  *  0b1..Output
30837  */
30838 #define GPIO_PDDR_PDD10(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD10_SHIFT)) & GPIO_PDDR_PDD10_MASK)
30839 
30840 #define GPIO_PDDR_PDD11_MASK                     (0x800U)
30841 #define GPIO_PDDR_PDD11_SHIFT                    (11U)
30842 /*! PDD11 - Port Data Direction
30843  *  0b0..Input
30844  *  0b1..Output
30845  */
30846 #define GPIO_PDDR_PDD11(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD11_SHIFT)) & GPIO_PDDR_PDD11_MASK)
30847 
30848 #define GPIO_PDDR_PDD12_MASK                     (0x1000U)
30849 #define GPIO_PDDR_PDD12_SHIFT                    (12U)
30850 /*! PDD12 - Port Data Direction
30851  *  0b0..Input
30852  *  0b1..Output
30853  */
30854 #define GPIO_PDDR_PDD12(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD12_SHIFT)) & GPIO_PDDR_PDD12_MASK)
30855 
30856 #define GPIO_PDDR_PDD13_MASK                     (0x2000U)
30857 #define GPIO_PDDR_PDD13_SHIFT                    (13U)
30858 /*! PDD13 - Port Data Direction
30859  *  0b0..Input
30860  *  0b1..Output
30861  */
30862 #define GPIO_PDDR_PDD13(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD13_SHIFT)) & GPIO_PDDR_PDD13_MASK)
30863 
30864 #define GPIO_PDDR_PDD14_MASK                     (0x4000U)
30865 #define GPIO_PDDR_PDD14_SHIFT                    (14U)
30866 /*! PDD14 - Port Data Direction
30867  *  0b0..Input
30868  *  0b1..Output
30869  */
30870 #define GPIO_PDDR_PDD14(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD14_SHIFT)) & GPIO_PDDR_PDD14_MASK)
30871 
30872 #define GPIO_PDDR_PDD15_MASK                     (0x8000U)
30873 #define GPIO_PDDR_PDD15_SHIFT                    (15U)
30874 /*! PDD15 - Port Data Direction
30875  *  0b0..Input
30876  *  0b1..Output
30877  */
30878 #define GPIO_PDDR_PDD15(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD15_SHIFT)) & GPIO_PDDR_PDD15_MASK)
30879 
30880 #define GPIO_PDDR_PDD16_MASK                     (0x10000U)
30881 #define GPIO_PDDR_PDD16_SHIFT                    (16U)
30882 /*! PDD16 - Port Data Direction
30883  *  0b0..Input
30884  *  0b1..Output
30885  */
30886 #define GPIO_PDDR_PDD16(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD16_SHIFT)) & GPIO_PDDR_PDD16_MASK)
30887 
30888 #define GPIO_PDDR_PDD17_MASK                     (0x20000U)
30889 #define GPIO_PDDR_PDD17_SHIFT                    (17U)
30890 /*! PDD17 - Port Data Direction
30891  *  0b0..Input
30892  *  0b1..Output
30893  */
30894 #define GPIO_PDDR_PDD17(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD17_SHIFT)) & GPIO_PDDR_PDD17_MASK)
30895 
30896 #define GPIO_PDDR_PDD18_MASK                     (0x40000U)
30897 #define GPIO_PDDR_PDD18_SHIFT                    (18U)
30898 /*! PDD18 - Port Data Direction
30899  *  0b0..Input
30900  *  0b1..Output
30901  */
30902 #define GPIO_PDDR_PDD18(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD18_SHIFT)) & GPIO_PDDR_PDD18_MASK)
30903 
30904 #define GPIO_PDDR_PDD19_MASK                     (0x80000U)
30905 #define GPIO_PDDR_PDD19_SHIFT                    (19U)
30906 /*! PDD19 - Port Data Direction
30907  *  0b0..Input
30908  *  0b1..Output
30909  */
30910 #define GPIO_PDDR_PDD19(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD19_SHIFT)) & GPIO_PDDR_PDD19_MASK)
30911 
30912 #define GPIO_PDDR_PDD20_MASK                     (0x100000U)
30913 #define GPIO_PDDR_PDD20_SHIFT                    (20U)
30914 /*! PDD20 - Port Data Direction
30915  *  0b0..Input
30916  *  0b1..Output
30917  */
30918 #define GPIO_PDDR_PDD20(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD20_SHIFT)) & GPIO_PDDR_PDD20_MASK)
30919 
30920 #define GPIO_PDDR_PDD21_MASK                     (0x200000U)
30921 #define GPIO_PDDR_PDD21_SHIFT                    (21U)
30922 /*! PDD21 - Port Data Direction
30923  *  0b0..Input
30924  *  0b1..Output
30925  */
30926 #define GPIO_PDDR_PDD21(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD21_SHIFT)) & GPIO_PDDR_PDD21_MASK)
30927 
30928 #define GPIO_PDDR_PDD22_MASK                     (0x400000U)
30929 #define GPIO_PDDR_PDD22_SHIFT                    (22U)
30930 /*! PDD22 - Port Data Direction
30931  *  0b0..Input
30932  *  0b1..Output
30933  */
30934 #define GPIO_PDDR_PDD22(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD22_SHIFT)) & GPIO_PDDR_PDD22_MASK)
30935 
30936 #define GPIO_PDDR_PDD23_MASK                     (0x800000U)
30937 #define GPIO_PDDR_PDD23_SHIFT                    (23U)
30938 /*! PDD23 - Port Data Direction
30939  *  0b0..Input
30940  *  0b1..Output
30941  */
30942 #define GPIO_PDDR_PDD23(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD23_SHIFT)) & GPIO_PDDR_PDD23_MASK)
30943 
30944 #define GPIO_PDDR_PDD24_MASK                     (0x1000000U)
30945 #define GPIO_PDDR_PDD24_SHIFT                    (24U)
30946 /*! PDD24 - Port Data Direction
30947  *  0b0..Input
30948  *  0b1..Output
30949  */
30950 #define GPIO_PDDR_PDD24(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD24_SHIFT)) & GPIO_PDDR_PDD24_MASK)
30951 
30952 #define GPIO_PDDR_PDD25_MASK                     (0x2000000U)
30953 #define GPIO_PDDR_PDD25_SHIFT                    (25U)
30954 /*! PDD25 - Port Data Direction
30955  *  0b0..Input
30956  *  0b1..Output
30957  */
30958 #define GPIO_PDDR_PDD25(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD25_SHIFT)) & GPIO_PDDR_PDD25_MASK)
30959 
30960 #define GPIO_PDDR_PDD26_MASK                     (0x4000000U)
30961 #define GPIO_PDDR_PDD26_SHIFT                    (26U)
30962 /*! PDD26 - Port Data Direction
30963  *  0b0..Input
30964  *  0b1..Output
30965  */
30966 #define GPIO_PDDR_PDD26(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD26_SHIFT)) & GPIO_PDDR_PDD26_MASK)
30967 
30968 #define GPIO_PDDR_PDD27_MASK                     (0x8000000U)
30969 #define GPIO_PDDR_PDD27_SHIFT                    (27U)
30970 /*! PDD27 - Port Data Direction
30971  *  0b0..Input
30972  *  0b1..Output
30973  */
30974 #define GPIO_PDDR_PDD27(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD27_SHIFT)) & GPIO_PDDR_PDD27_MASK)
30975 
30976 #define GPIO_PDDR_PDD28_MASK                     (0x10000000U)
30977 #define GPIO_PDDR_PDD28_SHIFT                    (28U)
30978 /*! PDD28 - Port Data Direction
30979  *  0b0..Input
30980  *  0b1..Output
30981  */
30982 #define GPIO_PDDR_PDD28(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD28_SHIFT)) & GPIO_PDDR_PDD28_MASK)
30983 
30984 #define GPIO_PDDR_PDD29_MASK                     (0x20000000U)
30985 #define GPIO_PDDR_PDD29_SHIFT                    (29U)
30986 /*! PDD29 - Port Data Direction
30987  *  0b0..Input
30988  *  0b1..Output
30989  */
30990 #define GPIO_PDDR_PDD29(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD29_SHIFT)) & GPIO_PDDR_PDD29_MASK)
30991 
30992 #define GPIO_PDDR_PDD30_MASK                     (0x40000000U)
30993 #define GPIO_PDDR_PDD30_SHIFT                    (30U)
30994 /*! PDD30 - Port Data Direction
30995  *  0b0..Input
30996  *  0b1..Output
30997  */
30998 #define GPIO_PDDR_PDD30(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD30_SHIFT)) & GPIO_PDDR_PDD30_MASK)
30999 
31000 #define GPIO_PDDR_PDD31_MASK                     (0x80000000U)
31001 #define GPIO_PDDR_PDD31_SHIFT                    (31U)
31002 /*! PDD31 - Port Data Direction
31003  *  0b0..Input
31004  *  0b1..Output
31005  */
31006 #define GPIO_PDDR_PDD31(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD31_SHIFT)) & GPIO_PDDR_PDD31_MASK)
31007 /*! @} */
31008 
31009 /*! @name PIDR - Port Input Disable */
31010 /*! @{ */
31011 
31012 #define GPIO_PIDR_PID0_MASK                      (0x1U)
31013 #define GPIO_PIDR_PID0_SHIFT                     (0U)
31014 /*! PID0 - Port Input Disable
31015  *  0b0..Configured for general-purpose input
31016  *  0b1..Disabled for general-purpose input
31017  */
31018 #define GPIO_PIDR_PID0(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID0_SHIFT)) & GPIO_PIDR_PID0_MASK)
31019 
31020 #define GPIO_PIDR_PID1_MASK                      (0x2U)
31021 #define GPIO_PIDR_PID1_SHIFT                     (1U)
31022 /*! PID1 - Port Input Disable
31023  *  0b0..Configured for general-purpose input
31024  *  0b1..Disabled for general-purpose input
31025  */
31026 #define GPIO_PIDR_PID1(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID1_SHIFT)) & GPIO_PIDR_PID1_MASK)
31027 
31028 #define GPIO_PIDR_PID2_MASK                      (0x4U)
31029 #define GPIO_PIDR_PID2_SHIFT                     (2U)
31030 /*! PID2 - Port Input Disable
31031  *  0b0..Configured for general-purpose input
31032  *  0b1..Disabled for general-purpose input
31033  */
31034 #define GPIO_PIDR_PID2(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID2_SHIFT)) & GPIO_PIDR_PID2_MASK)
31035 
31036 #define GPIO_PIDR_PID3_MASK                      (0x8U)
31037 #define GPIO_PIDR_PID3_SHIFT                     (3U)
31038 /*! PID3 - Port Input Disable
31039  *  0b0..Configured for general-purpose input
31040  *  0b1..Disabled for general-purpose input
31041  */
31042 #define GPIO_PIDR_PID3(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID3_SHIFT)) & GPIO_PIDR_PID3_MASK)
31043 
31044 #define GPIO_PIDR_PID4_MASK                      (0x10U)
31045 #define GPIO_PIDR_PID4_SHIFT                     (4U)
31046 /*! PID4 - Port Input Disable
31047  *  0b0..Configured for general-purpose input
31048  *  0b1..Disabled for general-purpose input
31049  */
31050 #define GPIO_PIDR_PID4(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID4_SHIFT)) & GPIO_PIDR_PID4_MASK)
31051 
31052 #define GPIO_PIDR_PID5_MASK                      (0x20U)
31053 #define GPIO_PIDR_PID5_SHIFT                     (5U)
31054 /*! PID5 - Port Input Disable
31055  *  0b0..Configured for general-purpose input
31056  *  0b1..Disabled for general-purpose input
31057  */
31058 #define GPIO_PIDR_PID5(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID5_SHIFT)) & GPIO_PIDR_PID5_MASK)
31059 
31060 #define GPIO_PIDR_PID6_MASK                      (0x40U)
31061 #define GPIO_PIDR_PID6_SHIFT                     (6U)
31062 /*! PID6 - Port Input Disable
31063  *  0b0..Configured for general-purpose input
31064  *  0b1..Disabled for general-purpose input
31065  */
31066 #define GPIO_PIDR_PID6(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID6_SHIFT)) & GPIO_PIDR_PID6_MASK)
31067 
31068 #define GPIO_PIDR_PID7_MASK                      (0x80U)
31069 #define GPIO_PIDR_PID7_SHIFT                     (7U)
31070 /*! PID7 - Port Input Disable
31071  *  0b0..Configured for general-purpose input
31072  *  0b1..Disabled for general-purpose input
31073  */
31074 #define GPIO_PIDR_PID7(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID7_SHIFT)) & GPIO_PIDR_PID7_MASK)
31075 
31076 #define GPIO_PIDR_PID8_MASK                      (0x100U)
31077 #define GPIO_PIDR_PID8_SHIFT                     (8U)
31078 /*! PID8 - Port Input Disable
31079  *  0b0..Configured for general-purpose input
31080  *  0b1..Disabled for general-purpose input
31081  */
31082 #define GPIO_PIDR_PID8(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID8_SHIFT)) & GPIO_PIDR_PID8_MASK)
31083 
31084 #define GPIO_PIDR_PID9_MASK                      (0x200U)
31085 #define GPIO_PIDR_PID9_SHIFT                     (9U)
31086 /*! PID9 - Port Input Disable
31087  *  0b0..Configured for general-purpose input
31088  *  0b1..Disabled for general-purpose input
31089  */
31090 #define GPIO_PIDR_PID9(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID9_SHIFT)) & GPIO_PIDR_PID9_MASK)
31091 
31092 #define GPIO_PIDR_PID10_MASK                     (0x400U)
31093 #define GPIO_PIDR_PID10_SHIFT                    (10U)
31094 /*! PID10 - Port Input Disable
31095  *  0b0..Configured for general-purpose input
31096  *  0b1..Disabled for general-purpose input
31097  */
31098 #define GPIO_PIDR_PID10(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID10_SHIFT)) & GPIO_PIDR_PID10_MASK)
31099 
31100 #define GPIO_PIDR_PID11_MASK                     (0x800U)
31101 #define GPIO_PIDR_PID11_SHIFT                    (11U)
31102 /*! PID11 - Port Input Disable
31103  *  0b0..Configured for general-purpose input
31104  *  0b1..Disabled for general-purpose input
31105  */
31106 #define GPIO_PIDR_PID11(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID11_SHIFT)) & GPIO_PIDR_PID11_MASK)
31107 
31108 #define GPIO_PIDR_PID12_MASK                     (0x1000U)
31109 #define GPIO_PIDR_PID12_SHIFT                    (12U)
31110 /*! PID12 - Port Input Disable
31111  *  0b0..Configured for general-purpose input
31112  *  0b1..Disabled for general-purpose input
31113  */
31114 #define GPIO_PIDR_PID12(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID12_SHIFT)) & GPIO_PIDR_PID12_MASK)
31115 
31116 #define GPIO_PIDR_PID13_MASK                     (0x2000U)
31117 #define GPIO_PIDR_PID13_SHIFT                    (13U)
31118 /*! PID13 - Port Input Disable
31119  *  0b0..Configured for general-purpose input
31120  *  0b1..Disabled for general-purpose input
31121  */
31122 #define GPIO_PIDR_PID13(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID13_SHIFT)) & GPIO_PIDR_PID13_MASK)
31123 
31124 #define GPIO_PIDR_PID14_MASK                     (0x4000U)
31125 #define GPIO_PIDR_PID14_SHIFT                    (14U)
31126 /*! PID14 - Port Input Disable
31127  *  0b0..Configured for general-purpose input
31128  *  0b1..Disabled for general-purpose input
31129  */
31130 #define GPIO_PIDR_PID14(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID14_SHIFT)) & GPIO_PIDR_PID14_MASK)
31131 
31132 #define GPIO_PIDR_PID15_MASK                     (0x8000U)
31133 #define GPIO_PIDR_PID15_SHIFT                    (15U)
31134 /*! PID15 - Port Input Disable
31135  *  0b0..Configured for general-purpose input
31136  *  0b1..Disabled for general-purpose input
31137  */
31138 #define GPIO_PIDR_PID15(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID15_SHIFT)) & GPIO_PIDR_PID15_MASK)
31139 
31140 #define GPIO_PIDR_PID16_MASK                     (0x10000U)
31141 #define GPIO_PIDR_PID16_SHIFT                    (16U)
31142 /*! PID16 - Port Input Disable
31143  *  0b0..Configured for general-purpose input
31144  *  0b1..Disabled for general-purpose input
31145  */
31146 #define GPIO_PIDR_PID16(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID16_SHIFT)) & GPIO_PIDR_PID16_MASK)
31147 
31148 #define GPIO_PIDR_PID17_MASK                     (0x20000U)
31149 #define GPIO_PIDR_PID17_SHIFT                    (17U)
31150 /*! PID17 - Port Input Disable
31151  *  0b0..Configured for general-purpose input
31152  *  0b1..Disabled for general-purpose input
31153  */
31154 #define GPIO_PIDR_PID17(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID17_SHIFT)) & GPIO_PIDR_PID17_MASK)
31155 
31156 #define GPIO_PIDR_PID18_MASK                     (0x40000U)
31157 #define GPIO_PIDR_PID18_SHIFT                    (18U)
31158 /*! PID18 - Port Input Disable
31159  *  0b0..Configured for general-purpose input
31160  *  0b1..Disabled for general-purpose input
31161  */
31162 #define GPIO_PIDR_PID18(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID18_SHIFT)) & GPIO_PIDR_PID18_MASK)
31163 
31164 #define GPIO_PIDR_PID19_MASK                     (0x80000U)
31165 #define GPIO_PIDR_PID19_SHIFT                    (19U)
31166 /*! PID19 - Port Input Disable
31167  *  0b0..Configured for general-purpose input
31168  *  0b1..Disabled for general-purpose input
31169  */
31170 #define GPIO_PIDR_PID19(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID19_SHIFT)) & GPIO_PIDR_PID19_MASK)
31171 
31172 #define GPIO_PIDR_PID20_MASK                     (0x100000U)
31173 #define GPIO_PIDR_PID20_SHIFT                    (20U)
31174 /*! PID20 - Port Input Disable
31175  *  0b0..Configured for general-purpose input
31176  *  0b1..Disabled for general-purpose input
31177  */
31178 #define GPIO_PIDR_PID20(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID20_SHIFT)) & GPIO_PIDR_PID20_MASK)
31179 
31180 #define GPIO_PIDR_PID21_MASK                     (0x200000U)
31181 #define GPIO_PIDR_PID21_SHIFT                    (21U)
31182 /*! PID21 - Port Input Disable
31183  *  0b0..Configured for general-purpose input
31184  *  0b1..Disabled for general-purpose input
31185  */
31186 #define GPIO_PIDR_PID21(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID21_SHIFT)) & GPIO_PIDR_PID21_MASK)
31187 
31188 #define GPIO_PIDR_PID22_MASK                     (0x400000U)
31189 #define GPIO_PIDR_PID22_SHIFT                    (22U)
31190 /*! PID22 - Port Input Disable
31191  *  0b0..Configured for general-purpose input
31192  *  0b1..Disabled for general-purpose input
31193  */
31194 #define GPIO_PIDR_PID22(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID22_SHIFT)) & GPIO_PIDR_PID22_MASK)
31195 
31196 #define GPIO_PIDR_PID23_MASK                     (0x800000U)
31197 #define GPIO_PIDR_PID23_SHIFT                    (23U)
31198 /*! PID23 - Port Input Disable
31199  *  0b0..Configured for general-purpose input
31200  *  0b1..Disabled for general-purpose input
31201  */
31202 #define GPIO_PIDR_PID23(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID23_SHIFT)) & GPIO_PIDR_PID23_MASK)
31203 
31204 #define GPIO_PIDR_PID24_MASK                     (0x1000000U)
31205 #define GPIO_PIDR_PID24_SHIFT                    (24U)
31206 /*! PID24 - Port Input Disable
31207  *  0b0..Configured for general-purpose input
31208  *  0b1..Disabled for general-purpose input
31209  */
31210 #define GPIO_PIDR_PID24(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID24_SHIFT)) & GPIO_PIDR_PID24_MASK)
31211 
31212 #define GPIO_PIDR_PID25_MASK                     (0x2000000U)
31213 #define GPIO_PIDR_PID25_SHIFT                    (25U)
31214 /*! PID25 - Port Input Disable
31215  *  0b0..Configured for general-purpose input
31216  *  0b1..Disabled for general-purpose input
31217  */
31218 #define GPIO_PIDR_PID25(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID25_SHIFT)) & GPIO_PIDR_PID25_MASK)
31219 
31220 #define GPIO_PIDR_PID26_MASK                     (0x4000000U)
31221 #define GPIO_PIDR_PID26_SHIFT                    (26U)
31222 /*! PID26 - Port Input Disable
31223  *  0b0..Configured for general-purpose input
31224  *  0b1..Disabled for general-purpose input
31225  */
31226 #define GPIO_PIDR_PID26(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID26_SHIFT)) & GPIO_PIDR_PID26_MASK)
31227 
31228 #define GPIO_PIDR_PID27_MASK                     (0x8000000U)
31229 #define GPIO_PIDR_PID27_SHIFT                    (27U)
31230 /*! PID27 - Port Input Disable
31231  *  0b0..Configured for general-purpose input
31232  *  0b1..Disabled for general-purpose input
31233  */
31234 #define GPIO_PIDR_PID27(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID27_SHIFT)) & GPIO_PIDR_PID27_MASK)
31235 
31236 #define GPIO_PIDR_PID28_MASK                     (0x10000000U)
31237 #define GPIO_PIDR_PID28_SHIFT                    (28U)
31238 /*! PID28 - Port Input Disable
31239  *  0b0..Configured for general-purpose input
31240  *  0b1..Disabled for general-purpose input
31241  */
31242 #define GPIO_PIDR_PID28(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID28_SHIFT)) & GPIO_PIDR_PID28_MASK)
31243 
31244 #define GPIO_PIDR_PID29_MASK                     (0x20000000U)
31245 #define GPIO_PIDR_PID29_SHIFT                    (29U)
31246 /*! PID29 - Port Input Disable
31247  *  0b0..Configured for general-purpose input
31248  *  0b1..Disabled for general-purpose input
31249  */
31250 #define GPIO_PIDR_PID29(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID29_SHIFT)) & GPIO_PIDR_PID29_MASK)
31251 
31252 #define GPIO_PIDR_PID30_MASK                     (0x40000000U)
31253 #define GPIO_PIDR_PID30_SHIFT                    (30U)
31254 /*! PID30 - Port Input Disable
31255  *  0b0..Configured for general-purpose input
31256  *  0b1..Disabled for general-purpose input
31257  */
31258 #define GPIO_PIDR_PID30(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID30_SHIFT)) & GPIO_PIDR_PID30_MASK)
31259 
31260 #define GPIO_PIDR_PID31_MASK                     (0x80000000U)
31261 #define GPIO_PIDR_PID31_SHIFT                    (31U)
31262 /*! PID31 - Port Input Disable
31263  *  0b0..Configured for general-purpose input
31264  *  0b1..Disabled for general-purpose input
31265  */
31266 #define GPIO_PIDR_PID31(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID31_SHIFT)) & GPIO_PIDR_PID31_MASK)
31267 /*! @} */
31268 
31269 /*! @name PDR - Pin Data */
31270 /*! @{ */
31271 
31272 #define GPIO_PDR_PD_MASK                         (0x1U)
31273 #define GPIO_PDR_PD_SHIFT                        (0U)
31274 /*! PD - Pin Data (I/O)
31275  *  0b0..Logic zero
31276  *  0b1..Logic one
31277  */
31278 #define GPIO_PDR_PD(x)                           (((uint8_t)(((uint8_t)(x)) << GPIO_PDR_PD_SHIFT)) & GPIO_PDR_PD_MASK)
31279 /*! @} */
31280 
31281 /* The count of GPIO_PDR */
31282 #define GPIO_PDR_COUNT                           (32U)
31283 
31284 /*! @name ICR - Interrupt Control 0..Interrupt Control 31 */
31285 /*! @{ */
31286 
31287 #define GPIO_ICR_IRQC_MASK                       (0xF0000U)
31288 #define GPIO_ICR_IRQC_SHIFT                      (16U)
31289 /*! IRQC - Interrupt Configuration
31290  *  0b0000..ISF is disabled
31291  *  0b0001..ISF and DMA request on rising edge
31292  *  0b0010..ISF and DMA request on falling edge
31293  *  0b0011..ISF and DMA request on either edge
31294  *  0b0100..Reserved
31295  *  0b0101..ISF sets on rising edge
31296  *  0b0110..ISF sets on falling edge
31297  *  0b0111..ISF sets on either edge
31298  *  0b1000..ISF and interrupt when logic 0
31299  *  0b1001..ISF and interrupt on rising edge
31300  *  0b1010..ISF and interrupt on falling edge
31301  *  0b1011..ISF and Interrupt on either edge
31302  *  0b1100..ISF and interrupt when logic 1
31303  *  0b1101..Enable active-high trigger output; ISF on rising edge (pin state is ORed with other enabled triggers
31304  *          to generate the output trigger for use by other peripherals)
31305  *  0b1110..Enable active-low trigger output; ISF on falling edge (pin state is inverted and ORed with other
31306  *          enabled triggers to generate the output trigger for use by other peripherals)
31307  *  0b1111..Reserved
31308  */
31309 #define GPIO_ICR_IRQC(x)                         (((uint32_t)(((uint32_t)(x)) << GPIO_ICR_IRQC_SHIFT)) & GPIO_ICR_IRQC_MASK)
31310 
31311 #define GPIO_ICR_IRQS_MASK                       (0x100000U)
31312 #define GPIO_ICR_IRQS_SHIFT                      (20U)
31313 /*! IRQS - Interrupt Select
31314  *  0b0..Interrupt, trigger output, or DMA request 0
31315  *  0b1..Interrupt, trigger output, or DMA request 1
31316  */
31317 #define GPIO_ICR_IRQS(x)                         (((uint32_t)(((uint32_t)(x)) << GPIO_ICR_IRQS_SHIFT)) & GPIO_ICR_IRQS_MASK)
31318 
31319 #define GPIO_ICR_LK_MASK                         (0x800000U)
31320 #define GPIO_ICR_LK_SHIFT                        (23U)
31321 /*! LK - Lock
31322  *  0b0..Lock
31323  *  0b1..Do not lock
31324  */
31325 #define GPIO_ICR_LK(x)                           (((uint32_t)(((uint32_t)(x)) << GPIO_ICR_LK_SHIFT)) & GPIO_ICR_LK_MASK)
31326 
31327 #define GPIO_ICR_ISF_MASK                        (0x1000000U)
31328 #define GPIO_ICR_ISF_SHIFT                       (24U)
31329 /*! ISF - Interrupt Status Flag
31330  *  0b0..Not detected
31331  *  0b1..Detected
31332  *  0b0..No effect
31333  *  0b1..Clear the flag
31334  */
31335 #define GPIO_ICR_ISF(x)                          (((uint32_t)(((uint32_t)(x)) << GPIO_ICR_ISF_SHIFT)) & GPIO_ICR_ISF_MASK)
31336 /*! @} */
31337 
31338 /* The count of GPIO_ICR */
31339 #define GPIO_ICR_COUNT                           (32U)
31340 
31341 /*! @name GICLR - Global Interrupt Control Low */
31342 /*! @{ */
31343 
31344 #define GPIO_GICLR_GIWE0_MASK                    (0x1U)
31345 #define GPIO_GICLR_GIWE0_SHIFT                   (0U)
31346 /*! GIWE0 - Global Interrupt Write Enable
31347  *  0b0..Not updated
31348  *  0b1..Updated
31349  */
31350 #define GPIO_GICLR_GIWE0(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE0_SHIFT)) & GPIO_GICLR_GIWE0_MASK)
31351 
31352 #define GPIO_GICLR_GIWE1_MASK                    (0x2U)
31353 #define GPIO_GICLR_GIWE1_SHIFT                   (1U)
31354 /*! GIWE1 - Global Interrupt Write Enable
31355  *  0b0..Not updated
31356  *  0b1..Updated
31357  */
31358 #define GPIO_GICLR_GIWE1(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE1_SHIFT)) & GPIO_GICLR_GIWE1_MASK)
31359 
31360 #define GPIO_GICLR_GIWE2_MASK                    (0x4U)
31361 #define GPIO_GICLR_GIWE2_SHIFT                   (2U)
31362 /*! GIWE2 - Global Interrupt Write Enable
31363  *  0b0..Not updated
31364  *  0b1..Updated
31365  */
31366 #define GPIO_GICLR_GIWE2(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE2_SHIFT)) & GPIO_GICLR_GIWE2_MASK)
31367 
31368 #define GPIO_GICLR_GIWE3_MASK                    (0x8U)
31369 #define GPIO_GICLR_GIWE3_SHIFT                   (3U)
31370 /*! GIWE3 - Global Interrupt Write Enable
31371  *  0b0..Not updated
31372  *  0b1..Updated
31373  */
31374 #define GPIO_GICLR_GIWE3(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE3_SHIFT)) & GPIO_GICLR_GIWE3_MASK)
31375 
31376 #define GPIO_GICLR_GIWE4_MASK                    (0x10U)
31377 #define GPIO_GICLR_GIWE4_SHIFT                   (4U)
31378 /*! GIWE4 - Global Interrupt Write Enable
31379  *  0b0..Not updated
31380  *  0b1..Updated
31381  */
31382 #define GPIO_GICLR_GIWE4(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE4_SHIFT)) & GPIO_GICLR_GIWE4_MASK)
31383 
31384 #define GPIO_GICLR_GIWE5_MASK                    (0x20U)
31385 #define GPIO_GICLR_GIWE5_SHIFT                   (5U)
31386 /*! GIWE5 - Global Interrupt Write Enable
31387  *  0b0..Not updated
31388  *  0b1..Updated
31389  */
31390 #define GPIO_GICLR_GIWE5(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE5_SHIFT)) & GPIO_GICLR_GIWE5_MASK)
31391 
31392 #define GPIO_GICLR_GIWE6_MASK                    (0x40U)
31393 #define GPIO_GICLR_GIWE6_SHIFT                   (6U)
31394 /*! GIWE6 - Global Interrupt Write Enable
31395  *  0b0..Not updated
31396  *  0b1..Updated
31397  */
31398 #define GPIO_GICLR_GIWE6(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE6_SHIFT)) & GPIO_GICLR_GIWE6_MASK)
31399 
31400 #define GPIO_GICLR_GIWE7_MASK                    (0x80U)
31401 #define GPIO_GICLR_GIWE7_SHIFT                   (7U)
31402 /*! GIWE7 - Global Interrupt Write Enable
31403  *  0b0..Not updated
31404  *  0b1..Updated
31405  */
31406 #define GPIO_GICLR_GIWE7(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE7_SHIFT)) & GPIO_GICLR_GIWE7_MASK)
31407 
31408 #define GPIO_GICLR_GIWE8_MASK                    (0x100U)
31409 #define GPIO_GICLR_GIWE8_SHIFT                   (8U)
31410 /*! GIWE8 - Global Interrupt Write Enable
31411  *  0b0..Not updated
31412  *  0b1..Updated
31413  */
31414 #define GPIO_GICLR_GIWE8(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE8_SHIFT)) & GPIO_GICLR_GIWE8_MASK)
31415 
31416 #define GPIO_GICLR_GIWE9_MASK                    (0x200U)
31417 #define GPIO_GICLR_GIWE9_SHIFT                   (9U)
31418 /*! GIWE9 - Global Interrupt Write Enable
31419  *  0b0..Not updated
31420  *  0b1..Updated
31421  */
31422 #define GPIO_GICLR_GIWE9(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE9_SHIFT)) & GPIO_GICLR_GIWE9_MASK)
31423 
31424 #define GPIO_GICLR_GIWE10_MASK                   (0x400U)
31425 #define GPIO_GICLR_GIWE10_SHIFT                  (10U)
31426 /*! GIWE10 - Global Interrupt Write Enable
31427  *  0b0..Not updated
31428  *  0b1..Updated
31429  */
31430 #define GPIO_GICLR_GIWE10(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE10_SHIFT)) & GPIO_GICLR_GIWE10_MASK)
31431 
31432 #define GPIO_GICLR_GIWE11_MASK                   (0x800U)
31433 #define GPIO_GICLR_GIWE11_SHIFT                  (11U)
31434 /*! GIWE11 - Global Interrupt Write Enable
31435  *  0b0..Not updated
31436  *  0b1..Updated
31437  */
31438 #define GPIO_GICLR_GIWE11(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE11_SHIFT)) & GPIO_GICLR_GIWE11_MASK)
31439 
31440 #define GPIO_GICLR_GIWE12_MASK                   (0x1000U)
31441 #define GPIO_GICLR_GIWE12_SHIFT                  (12U)
31442 /*! GIWE12 - Global Interrupt Write Enable
31443  *  0b0..Not updated
31444  *  0b1..Updated
31445  */
31446 #define GPIO_GICLR_GIWE12(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE12_SHIFT)) & GPIO_GICLR_GIWE12_MASK)
31447 
31448 #define GPIO_GICLR_GIWE13_MASK                   (0x2000U)
31449 #define GPIO_GICLR_GIWE13_SHIFT                  (13U)
31450 /*! GIWE13 - Global Interrupt Write Enable
31451  *  0b0..Not updated
31452  *  0b1..Updated
31453  */
31454 #define GPIO_GICLR_GIWE13(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE13_SHIFT)) & GPIO_GICLR_GIWE13_MASK)
31455 
31456 #define GPIO_GICLR_GIWE14_MASK                   (0x4000U)
31457 #define GPIO_GICLR_GIWE14_SHIFT                  (14U)
31458 /*! GIWE14 - Global Interrupt Write Enable
31459  *  0b0..Not updated
31460  *  0b1..Updated
31461  */
31462 #define GPIO_GICLR_GIWE14(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE14_SHIFT)) & GPIO_GICLR_GIWE14_MASK)
31463 
31464 #define GPIO_GICLR_GIWE15_MASK                   (0x8000U)
31465 #define GPIO_GICLR_GIWE15_SHIFT                  (15U)
31466 /*! GIWE15 - Global Interrupt Write Enable
31467  *  0b0..Not updated
31468  *  0b1..Updated
31469  */
31470 #define GPIO_GICLR_GIWE15(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE15_SHIFT)) & GPIO_GICLR_GIWE15_MASK)
31471 
31472 #define GPIO_GICLR_GIWD_MASK                     (0xFFFF0000U)
31473 #define GPIO_GICLR_GIWD_SHIFT                    (16U)
31474 /*! GIWD - Global Interrupt Write Data */
31475 #define GPIO_GICLR_GIWD(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWD_SHIFT)) & GPIO_GICLR_GIWD_MASK)
31476 /*! @} */
31477 
31478 /*! @name GICHR - Global Interrupt Control High */
31479 /*! @{ */
31480 
31481 #define GPIO_GICHR_GIWE16_MASK                   (0x1U)
31482 #define GPIO_GICHR_GIWE16_SHIFT                  (0U)
31483 /*! GIWE16 - Global Interrupt Write Enable
31484  *  0b0..Not updated.
31485  *  0b1..Updated
31486  */
31487 #define GPIO_GICHR_GIWE16(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE16_SHIFT)) & GPIO_GICHR_GIWE16_MASK)
31488 
31489 #define GPIO_GICHR_GIWE17_MASK                   (0x2U)
31490 #define GPIO_GICHR_GIWE17_SHIFT                  (1U)
31491 /*! GIWE17 - Global Interrupt Write Enable
31492  *  0b0..Not updated.
31493  *  0b1..Updated
31494  */
31495 #define GPIO_GICHR_GIWE17(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE17_SHIFT)) & GPIO_GICHR_GIWE17_MASK)
31496 
31497 #define GPIO_GICHR_GIWE18_MASK                   (0x4U)
31498 #define GPIO_GICHR_GIWE18_SHIFT                  (2U)
31499 /*! GIWE18 - Global Interrupt Write Enable
31500  *  0b0..Not updated.
31501  *  0b1..Updated
31502  */
31503 #define GPIO_GICHR_GIWE18(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE18_SHIFT)) & GPIO_GICHR_GIWE18_MASK)
31504 
31505 #define GPIO_GICHR_GIWE19_MASK                   (0x8U)
31506 #define GPIO_GICHR_GIWE19_SHIFT                  (3U)
31507 /*! GIWE19 - Global Interrupt Write Enable
31508  *  0b0..Not updated.
31509  *  0b1..Updated
31510  */
31511 #define GPIO_GICHR_GIWE19(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE19_SHIFT)) & GPIO_GICHR_GIWE19_MASK)
31512 
31513 #define GPIO_GICHR_GIWE20_MASK                   (0x10U)
31514 #define GPIO_GICHR_GIWE20_SHIFT                  (4U)
31515 /*! GIWE20 - Global Interrupt Write Enable
31516  *  0b0..Not updated.
31517  *  0b1..Updated
31518  */
31519 #define GPIO_GICHR_GIWE20(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE20_SHIFT)) & GPIO_GICHR_GIWE20_MASK)
31520 
31521 #define GPIO_GICHR_GIWE21_MASK                   (0x20U)
31522 #define GPIO_GICHR_GIWE21_SHIFT                  (5U)
31523 /*! GIWE21 - Global Interrupt Write Enable
31524  *  0b0..Not updated.
31525  *  0b1..Updated
31526  */
31527 #define GPIO_GICHR_GIWE21(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE21_SHIFT)) & GPIO_GICHR_GIWE21_MASK)
31528 
31529 #define GPIO_GICHR_GIWE22_MASK                   (0x40U)
31530 #define GPIO_GICHR_GIWE22_SHIFT                  (6U)
31531 /*! GIWE22 - Global Interrupt Write Enable
31532  *  0b0..Not updated.
31533  *  0b1..Updated
31534  */
31535 #define GPIO_GICHR_GIWE22(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE22_SHIFT)) & GPIO_GICHR_GIWE22_MASK)
31536 
31537 #define GPIO_GICHR_GIWE23_MASK                   (0x80U)
31538 #define GPIO_GICHR_GIWE23_SHIFT                  (7U)
31539 /*! GIWE23 - Global Interrupt Write Enable
31540  *  0b0..Not updated.
31541  *  0b1..Updated
31542  */
31543 #define GPIO_GICHR_GIWE23(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE23_SHIFT)) & GPIO_GICHR_GIWE23_MASK)
31544 
31545 #define GPIO_GICHR_GIWE24_MASK                   (0x100U)
31546 #define GPIO_GICHR_GIWE24_SHIFT                  (8U)
31547 /*! GIWE24 - Global Interrupt Write Enable
31548  *  0b0..Not updated.
31549  *  0b1..Updated
31550  */
31551 #define GPIO_GICHR_GIWE24(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE24_SHIFT)) & GPIO_GICHR_GIWE24_MASK)
31552 
31553 #define GPIO_GICHR_GIWE25_MASK                   (0x200U)
31554 #define GPIO_GICHR_GIWE25_SHIFT                  (9U)
31555 /*! GIWE25 - Global Interrupt Write Enable
31556  *  0b0..Not updated.
31557  *  0b1..Updated
31558  */
31559 #define GPIO_GICHR_GIWE25(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE25_SHIFT)) & GPIO_GICHR_GIWE25_MASK)
31560 
31561 #define GPIO_GICHR_GIWE26_MASK                   (0x400U)
31562 #define GPIO_GICHR_GIWE26_SHIFT                  (10U)
31563 /*! GIWE26 - Global Interrupt Write Enable
31564  *  0b0..Not updated.
31565  *  0b1..Updated
31566  */
31567 #define GPIO_GICHR_GIWE26(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE26_SHIFT)) & GPIO_GICHR_GIWE26_MASK)
31568 
31569 #define GPIO_GICHR_GIWE27_MASK                   (0x800U)
31570 #define GPIO_GICHR_GIWE27_SHIFT                  (11U)
31571 /*! GIWE27 - Global Interrupt Write Enable
31572  *  0b0..Not updated.
31573  *  0b1..Updated
31574  */
31575 #define GPIO_GICHR_GIWE27(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE27_SHIFT)) & GPIO_GICHR_GIWE27_MASK)
31576 
31577 #define GPIO_GICHR_GIWE28_MASK                   (0x1000U)
31578 #define GPIO_GICHR_GIWE28_SHIFT                  (12U)
31579 /*! GIWE28 - Global Interrupt Write Enable
31580  *  0b0..Not updated.
31581  *  0b1..Updated
31582  */
31583 #define GPIO_GICHR_GIWE28(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE28_SHIFT)) & GPIO_GICHR_GIWE28_MASK)
31584 
31585 #define GPIO_GICHR_GIWE29_MASK                   (0x2000U)
31586 #define GPIO_GICHR_GIWE29_SHIFT                  (13U)
31587 /*! GIWE29 - Global Interrupt Write Enable
31588  *  0b0..Not updated.
31589  *  0b1..Updated
31590  */
31591 #define GPIO_GICHR_GIWE29(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE29_SHIFT)) & GPIO_GICHR_GIWE29_MASK)
31592 
31593 #define GPIO_GICHR_GIWE30_MASK                   (0x4000U)
31594 #define GPIO_GICHR_GIWE30_SHIFT                  (14U)
31595 /*! GIWE30 - Global Interrupt Write Enable
31596  *  0b0..Not updated.
31597  *  0b1..Updated
31598  */
31599 #define GPIO_GICHR_GIWE30(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE30_SHIFT)) & GPIO_GICHR_GIWE30_MASK)
31600 
31601 #define GPIO_GICHR_GIWE31_MASK                   (0x8000U)
31602 #define GPIO_GICHR_GIWE31_SHIFT                  (15U)
31603 /*! GIWE31 - Global Interrupt Write Enable
31604  *  0b0..Not updated.
31605  *  0b1..Updated
31606  */
31607 #define GPIO_GICHR_GIWE31(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE31_SHIFT)) & GPIO_GICHR_GIWE31_MASK)
31608 
31609 #define GPIO_GICHR_GIWD_MASK                     (0xFFFF0000U)
31610 #define GPIO_GICHR_GIWD_SHIFT                    (16U)
31611 /*! GIWD - Global Interrupt Write Data */
31612 #define GPIO_GICHR_GIWD(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWD_SHIFT)) & GPIO_GICHR_GIWD_MASK)
31613 /*! @} */
31614 
31615 /*! @name ISFR - Interrupt Status Flag */
31616 /*! @{ */
31617 
31618 #define GPIO_ISFR_ISF0_MASK                      (0x1U)
31619 #define GPIO_ISFR_ISF0_SHIFT                     (0U)
31620 /*! ISF0 - Interrupt Status Flag
31621  *  0b0..Not detected
31622  *  0b1..Detected
31623  *  0b0..No effect
31624  *  0b1..Clear the flag
31625  */
31626 #define GPIO_ISFR_ISF0(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF0_SHIFT)) & GPIO_ISFR_ISF0_MASK)
31627 
31628 #define GPIO_ISFR_ISF1_MASK                      (0x2U)
31629 #define GPIO_ISFR_ISF1_SHIFT                     (1U)
31630 /*! ISF1 - Interrupt Status Flag
31631  *  0b0..Not detected
31632  *  0b1..Detected
31633  *  0b0..No effect
31634  *  0b1..Clear the flag
31635  */
31636 #define GPIO_ISFR_ISF1(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF1_SHIFT)) & GPIO_ISFR_ISF1_MASK)
31637 
31638 #define GPIO_ISFR_ISF2_MASK                      (0x4U)
31639 #define GPIO_ISFR_ISF2_SHIFT                     (2U)
31640 /*! ISF2 - Interrupt Status Flag
31641  *  0b0..Not detected
31642  *  0b1..Detected
31643  *  0b0..No effect
31644  *  0b1..Clear the flag
31645  */
31646 #define GPIO_ISFR_ISF2(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF2_SHIFT)) & GPIO_ISFR_ISF2_MASK)
31647 
31648 #define GPIO_ISFR_ISF3_MASK                      (0x8U)
31649 #define GPIO_ISFR_ISF3_SHIFT                     (3U)
31650 /*! ISF3 - Interrupt Status Flag
31651  *  0b0..Not detected
31652  *  0b1..Detected
31653  *  0b0..No effect
31654  *  0b1..Clear the flag
31655  */
31656 #define GPIO_ISFR_ISF3(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF3_SHIFT)) & GPIO_ISFR_ISF3_MASK)
31657 
31658 #define GPIO_ISFR_ISF4_MASK                      (0x10U)
31659 #define GPIO_ISFR_ISF4_SHIFT                     (4U)
31660 /*! ISF4 - Interrupt Status Flag
31661  *  0b0..Not detected
31662  *  0b1..Detected
31663  *  0b0..No effect
31664  *  0b1..Clear the flag
31665  */
31666 #define GPIO_ISFR_ISF4(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF4_SHIFT)) & GPIO_ISFR_ISF4_MASK)
31667 
31668 #define GPIO_ISFR_ISF5_MASK                      (0x20U)
31669 #define GPIO_ISFR_ISF5_SHIFT                     (5U)
31670 /*! ISF5 - Interrupt Status Flag
31671  *  0b0..Not detected
31672  *  0b1..Detected
31673  *  0b0..No effect
31674  *  0b1..Clear the flag
31675  */
31676 #define GPIO_ISFR_ISF5(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF5_SHIFT)) & GPIO_ISFR_ISF5_MASK)
31677 
31678 #define GPIO_ISFR_ISF6_MASK                      (0x40U)
31679 #define GPIO_ISFR_ISF6_SHIFT                     (6U)
31680 /*! ISF6 - Interrupt Status Flag
31681  *  0b0..Not detected
31682  *  0b1..Detected
31683  *  0b0..No effect
31684  *  0b1..Clear the flag
31685  */
31686 #define GPIO_ISFR_ISF6(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF6_SHIFT)) & GPIO_ISFR_ISF6_MASK)
31687 
31688 #define GPIO_ISFR_ISF7_MASK                      (0x80U)
31689 #define GPIO_ISFR_ISF7_SHIFT                     (7U)
31690 /*! ISF7 - Interrupt Status Flag
31691  *  0b0..Not detected
31692  *  0b1..Detected
31693  *  0b0..No effect
31694  *  0b1..Clear the flag
31695  */
31696 #define GPIO_ISFR_ISF7(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF7_SHIFT)) & GPIO_ISFR_ISF7_MASK)
31697 
31698 #define GPIO_ISFR_ISF8_MASK                      (0x100U)
31699 #define GPIO_ISFR_ISF8_SHIFT                     (8U)
31700 /*! ISF8 - Interrupt Status Flag
31701  *  0b0..Not detected
31702  *  0b1..Detected
31703  *  0b0..No effect
31704  *  0b1..Clear the flag
31705  */
31706 #define GPIO_ISFR_ISF8(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF8_SHIFT)) & GPIO_ISFR_ISF8_MASK)
31707 
31708 #define GPIO_ISFR_ISF9_MASK                      (0x200U)
31709 #define GPIO_ISFR_ISF9_SHIFT                     (9U)
31710 /*! ISF9 - Interrupt Status Flag
31711  *  0b0..Not detected
31712  *  0b1..Detected
31713  *  0b0..No effect
31714  *  0b1..Clear the flag
31715  */
31716 #define GPIO_ISFR_ISF9(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF9_SHIFT)) & GPIO_ISFR_ISF9_MASK)
31717 
31718 #define GPIO_ISFR_ISF10_MASK                     (0x400U)
31719 #define GPIO_ISFR_ISF10_SHIFT                    (10U)
31720 /*! ISF10 - Interrupt Status Flag
31721  *  0b0..Not detected
31722  *  0b1..Detected
31723  *  0b0..No effect
31724  *  0b1..Clear the flag
31725  */
31726 #define GPIO_ISFR_ISF10(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF10_SHIFT)) & GPIO_ISFR_ISF10_MASK)
31727 
31728 #define GPIO_ISFR_ISF11_MASK                     (0x800U)
31729 #define GPIO_ISFR_ISF11_SHIFT                    (11U)
31730 /*! ISF11 - Interrupt Status Flag
31731  *  0b0..Not detected
31732  *  0b1..Detected
31733  *  0b0..No effect
31734  *  0b1..Clear the flag
31735  */
31736 #define GPIO_ISFR_ISF11(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF11_SHIFT)) & GPIO_ISFR_ISF11_MASK)
31737 
31738 #define GPIO_ISFR_ISF12_MASK                     (0x1000U)
31739 #define GPIO_ISFR_ISF12_SHIFT                    (12U)
31740 /*! ISF12 - Interrupt Status Flag
31741  *  0b0..Not detected
31742  *  0b1..Detected
31743  *  0b0..No effect
31744  *  0b1..Clear the flag
31745  */
31746 #define GPIO_ISFR_ISF12(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF12_SHIFT)) & GPIO_ISFR_ISF12_MASK)
31747 
31748 #define GPIO_ISFR_ISF13_MASK                     (0x2000U)
31749 #define GPIO_ISFR_ISF13_SHIFT                    (13U)
31750 /*! ISF13 - Interrupt Status Flag
31751  *  0b0..Not detected
31752  *  0b1..Detected
31753  *  0b0..No effect
31754  *  0b1..Clear the flag
31755  */
31756 #define GPIO_ISFR_ISF13(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF13_SHIFT)) & GPIO_ISFR_ISF13_MASK)
31757 
31758 #define GPIO_ISFR_ISF14_MASK                     (0x4000U)
31759 #define GPIO_ISFR_ISF14_SHIFT                    (14U)
31760 /*! ISF14 - Interrupt Status Flag
31761  *  0b0..Not detected
31762  *  0b1..Detected
31763  *  0b0..No effect
31764  *  0b1..Clear the flag
31765  */
31766 #define GPIO_ISFR_ISF14(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF14_SHIFT)) & GPIO_ISFR_ISF14_MASK)
31767 
31768 #define GPIO_ISFR_ISF15_MASK                     (0x8000U)
31769 #define GPIO_ISFR_ISF15_SHIFT                    (15U)
31770 /*! ISF15 - Interrupt Status Flag
31771  *  0b0..Not detected
31772  *  0b1..Detected
31773  *  0b0..No effect
31774  *  0b1..Clear the flag
31775  */
31776 #define GPIO_ISFR_ISF15(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF15_SHIFT)) & GPIO_ISFR_ISF15_MASK)
31777 
31778 #define GPIO_ISFR_ISF16_MASK                     (0x10000U)
31779 #define GPIO_ISFR_ISF16_SHIFT                    (16U)
31780 /*! ISF16 - Interrupt Status Flag
31781  *  0b0..Not detected
31782  *  0b1..Detected
31783  *  0b0..No effect
31784  *  0b1..Clear the flag
31785  */
31786 #define GPIO_ISFR_ISF16(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF16_SHIFT)) & GPIO_ISFR_ISF16_MASK)
31787 
31788 #define GPIO_ISFR_ISF17_MASK                     (0x20000U)
31789 #define GPIO_ISFR_ISF17_SHIFT                    (17U)
31790 /*! ISF17 - Interrupt Status Flag
31791  *  0b0..Not detected
31792  *  0b1..Detected
31793  *  0b0..No effect
31794  *  0b1..Clear the flag
31795  */
31796 #define GPIO_ISFR_ISF17(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF17_SHIFT)) & GPIO_ISFR_ISF17_MASK)
31797 
31798 #define GPIO_ISFR_ISF18_MASK                     (0x40000U)
31799 #define GPIO_ISFR_ISF18_SHIFT                    (18U)
31800 /*! ISF18 - Interrupt Status Flag
31801  *  0b0..Not detected
31802  *  0b1..Detected
31803  *  0b0..No effect
31804  *  0b1..Clear the flag
31805  */
31806 #define GPIO_ISFR_ISF18(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF18_SHIFT)) & GPIO_ISFR_ISF18_MASK)
31807 
31808 #define GPIO_ISFR_ISF19_MASK                     (0x80000U)
31809 #define GPIO_ISFR_ISF19_SHIFT                    (19U)
31810 /*! ISF19 - Interrupt Status Flag
31811  *  0b0..Not detected
31812  *  0b1..Detected
31813  *  0b0..No effect
31814  *  0b1..Clear the flag
31815  */
31816 #define GPIO_ISFR_ISF19(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF19_SHIFT)) & GPIO_ISFR_ISF19_MASK)
31817 
31818 #define GPIO_ISFR_ISF20_MASK                     (0x100000U)
31819 #define GPIO_ISFR_ISF20_SHIFT                    (20U)
31820 /*! ISF20 - Interrupt Status Flag
31821  *  0b0..Not detected
31822  *  0b1..Detected
31823  *  0b0..No effect
31824  *  0b1..Clear the flag
31825  */
31826 #define GPIO_ISFR_ISF20(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF20_SHIFT)) & GPIO_ISFR_ISF20_MASK)
31827 
31828 #define GPIO_ISFR_ISF21_MASK                     (0x200000U)
31829 #define GPIO_ISFR_ISF21_SHIFT                    (21U)
31830 /*! ISF21 - Interrupt Status Flag
31831  *  0b0..Not detected
31832  *  0b1..Detected
31833  *  0b0..No effect
31834  *  0b1..Clear the flag
31835  */
31836 #define GPIO_ISFR_ISF21(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF21_SHIFT)) & GPIO_ISFR_ISF21_MASK)
31837 
31838 #define GPIO_ISFR_ISF22_MASK                     (0x400000U)
31839 #define GPIO_ISFR_ISF22_SHIFT                    (22U)
31840 /*! ISF22 - Interrupt Status Flag
31841  *  0b0..Not detected
31842  *  0b1..Detected
31843  *  0b0..No effect
31844  *  0b1..Clear the flag
31845  */
31846 #define GPIO_ISFR_ISF22(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF22_SHIFT)) & GPIO_ISFR_ISF22_MASK)
31847 
31848 #define GPIO_ISFR_ISF23_MASK                     (0x800000U)
31849 #define GPIO_ISFR_ISF23_SHIFT                    (23U)
31850 /*! ISF23 - Interrupt Status Flag
31851  *  0b0..Not detected
31852  *  0b1..Detected
31853  *  0b0..No effect
31854  *  0b1..Clear the flag
31855  */
31856 #define GPIO_ISFR_ISF23(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF23_SHIFT)) & GPIO_ISFR_ISF23_MASK)
31857 
31858 #define GPIO_ISFR_ISF24_MASK                     (0x1000000U)
31859 #define GPIO_ISFR_ISF24_SHIFT                    (24U)
31860 /*! ISF24 - Interrupt Status Flag
31861  *  0b0..Not detected
31862  *  0b1..Detected
31863  *  0b0..No effect
31864  *  0b1..Clear the flag
31865  */
31866 #define GPIO_ISFR_ISF24(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF24_SHIFT)) & GPIO_ISFR_ISF24_MASK)
31867 
31868 #define GPIO_ISFR_ISF25_MASK                     (0x2000000U)
31869 #define GPIO_ISFR_ISF25_SHIFT                    (25U)
31870 /*! ISF25 - Interrupt Status Flag
31871  *  0b0..Not detected
31872  *  0b1..Detected
31873  *  0b0..No effect
31874  *  0b1..Clear the flag
31875  */
31876 #define GPIO_ISFR_ISF25(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF25_SHIFT)) & GPIO_ISFR_ISF25_MASK)
31877 
31878 #define GPIO_ISFR_ISF26_MASK                     (0x4000000U)
31879 #define GPIO_ISFR_ISF26_SHIFT                    (26U)
31880 /*! ISF26 - Interrupt Status Flag
31881  *  0b0..Not detected
31882  *  0b1..Detected
31883  *  0b0..No effect
31884  *  0b1..Clear the flag
31885  */
31886 #define GPIO_ISFR_ISF26(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF26_SHIFT)) & GPIO_ISFR_ISF26_MASK)
31887 
31888 #define GPIO_ISFR_ISF27_MASK                     (0x8000000U)
31889 #define GPIO_ISFR_ISF27_SHIFT                    (27U)
31890 /*! ISF27 - Interrupt Status Flag
31891  *  0b0..Not detected
31892  *  0b1..Detected
31893  *  0b0..No effect
31894  *  0b1..Clear the flag
31895  */
31896 #define GPIO_ISFR_ISF27(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF27_SHIFT)) & GPIO_ISFR_ISF27_MASK)
31897 
31898 #define GPIO_ISFR_ISF28_MASK                     (0x10000000U)
31899 #define GPIO_ISFR_ISF28_SHIFT                    (28U)
31900 /*! ISF28 - Interrupt Status Flag
31901  *  0b0..Not detected
31902  *  0b1..Detected
31903  *  0b0..No effect
31904  *  0b1..Clear the flag
31905  */
31906 #define GPIO_ISFR_ISF28(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF28_SHIFT)) & GPIO_ISFR_ISF28_MASK)
31907 
31908 #define GPIO_ISFR_ISF29_MASK                     (0x20000000U)
31909 #define GPIO_ISFR_ISF29_SHIFT                    (29U)
31910 /*! ISF29 - Interrupt Status Flag
31911  *  0b0..Not detected
31912  *  0b1..Detected
31913  *  0b0..No effect
31914  *  0b1..Clear the flag
31915  */
31916 #define GPIO_ISFR_ISF29(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF29_SHIFT)) & GPIO_ISFR_ISF29_MASK)
31917 
31918 #define GPIO_ISFR_ISF30_MASK                     (0x40000000U)
31919 #define GPIO_ISFR_ISF30_SHIFT                    (30U)
31920 /*! ISF30 - Interrupt Status Flag
31921  *  0b0..Not detected
31922  *  0b1..Detected
31923  *  0b0..No effect
31924  *  0b1..Clear the flag
31925  */
31926 #define GPIO_ISFR_ISF30(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF30_SHIFT)) & GPIO_ISFR_ISF30_MASK)
31927 
31928 #define GPIO_ISFR_ISF31_MASK                     (0x80000000U)
31929 #define GPIO_ISFR_ISF31_SHIFT                    (31U)
31930 /*! ISF31 - Interrupt Status Flag
31931  *  0b0..Not detected
31932  *  0b1..Detected
31933  *  0b0..No effect
31934  *  0b1..Clear the flag
31935  */
31936 #define GPIO_ISFR_ISF31(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF31_SHIFT)) & GPIO_ISFR_ISF31_MASK)
31937 /*! @} */
31938 
31939 /* The count of GPIO_ISFR */
31940 #define GPIO_ISFR_COUNT                          (2U)
31941 
31942 
31943 /*!
31944  * @}
31945  */ /* end of group GPIO_Register_Masks */
31946 
31947 
31948 /* GPIO - Peripheral instance base addresses */
31949 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
31950   /** Peripheral GPIO0 base address */
31951   #define GPIO0_BASE                               (0x50096000u)
31952   /** Peripheral GPIO0 base address */
31953   #define GPIO0_BASE_NS                            (0x40096000u)
31954   /** Peripheral GPIO0 base pointer */
31955   #define GPIO0                                    ((GPIO_Type *)GPIO0_BASE)
31956   /** Peripheral GPIO0 base pointer */
31957   #define GPIO0_NS                                 ((GPIO_Type *)GPIO0_BASE_NS)
31958   /** Peripheral GPIO0_ALIAS1 base address */
31959   #define GPIO0_ALIAS1_BASE                        (0x50097000u)
31960   /** Peripheral GPIO0_ALIAS1 base address */
31961   #define GPIO0_ALIAS1_BASE_NS                     (0x40097000u)
31962   /** Peripheral GPIO0_ALIAS1 base pointer */
31963   #define GPIO0_ALIAS1                             ((GPIO_Type *)GPIO0_ALIAS1_BASE)
31964   /** Peripheral GPIO0_ALIAS1 base pointer */
31965   #define GPIO0_ALIAS1_NS                          ((GPIO_Type *)GPIO0_ALIAS1_BASE_NS)
31966   /** Peripheral GPIO1 base address */
31967   #define GPIO1_BASE                               (0x50098000u)
31968   /** Peripheral GPIO1 base address */
31969   #define GPIO1_BASE_NS                            (0x40098000u)
31970   /** Peripheral GPIO1 base pointer */
31971   #define GPIO1                                    ((GPIO_Type *)GPIO1_BASE)
31972   /** Peripheral GPIO1 base pointer */
31973   #define GPIO1_NS                                 ((GPIO_Type *)GPIO1_BASE_NS)
31974   /** Peripheral GPIO1_ALIAS1 base address */
31975   #define GPIO1_ALIAS1_BASE                        (0x50099000u)
31976   /** Peripheral GPIO1_ALIAS1 base address */
31977   #define GPIO1_ALIAS1_BASE_NS                     (0x40099000u)
31978   /** Peripheral GPIO1_ALIAS1 base pointer */
31979   #define GPIO1_ALIAS1                             ((GPIO_Type *)GPIO1_ALIAS1_BASE)
31980   /** Peripheral GPIO1_ALIAS1 base pointer */
31981   #define GPIO1_ALIAS1_NS                          ((GPIO_Type *)GPIO1_ALIAS1_BASE_NS)
31982   /** Peripheral GPIO2 base address */
31983   #define GPIO2_BASE                               (0x5009A000u)
31984   /** Peripheral GPIO2 base address */
31985   #define GPIO2_BASE_NS                            (0x4009A000u)
31986   /** Peripheral GPIO2 base pointer */
31987   #define GPIO2                                    ((GPIO_Type *)GPIO2_BASE)
31988   /** Peripheral GPIO2 base pointer */
31989   #define GPIO2_NS                                 ((GPIO_Type *)GPIO2_BASE_NS)
31990   /** Peripheral GPIO2_ALIAS1 base address */
31991   #define GPIO2_ALIAS1_BASE                        (0x5009B000u)
31992   /** Peripheral GPIO2_ALIAS1 base address */
31993   #define GPIO2_ALIAS1_BASE_NS                     (0x4009B000u)
31994   /** Peripheral GPIO2_ALIAS1 base pointer */
31995   #define GPIO2_ALIAS1                             ((GPIO_Type *)GPIO2_ALIAS1_BASE)
31996   /** Peripheral GPIO2_ALIAS1 base pointer */
31997   #define GPIO2_ALIAS1_NS                          ((GPIO_Type *)GPIO2_ALIAS1_BASE_NS)
31998   /** Peripheral GPIO3 base address */
31999   #define GPIO3_BASE                               (0x5009C000u)
32000   /** Peripheral GPIO3 base address */
32001   #define GPIO3_BASE_NS                            (0x4009C000u)
32002   /** Peripheral GPIO3 base pointer */
32003   #define GPIO3                                    ((GPIO_Type *)GPIO3_BASE)
32004   /** Peripheral GPIO3 base pointer */
32005   #define GPIO3_NS                                 ((GPIO_Type *)GPIO3_BASE_NS)
32006   /** Peripheral GPIO3_ALIAS1 base address */
32007   #define GPIO3_ALIAS1_BASE                        (0x5009D000u)
32008   /** Peripheral GPIO3_ALIAS1 base address */
32009   #define GPIO3_ALIAS1_BASE_NS                     (0x4009D000u)
32010   /** Peripheral GPIO3_ALIAS1 base pointer */
32011   #define GPIO3_ALIAS1                             ((GPIO_Type *)GPIO3_ALIAS1_BASE)
32012   /** Peripheral GPIO3_ALIAS1 base pointer */
32013   #define GPIO3_ALIAS1_NS                          ((GPIO_Type *)GPIO3_ALIAS1_BASE_NS)
32014   /** Peripheral GPIO4 base address */
32015   #define GPIO4_BASE                               (0x5009E000u)
32016   /** Peripheral GPIO4 base address */
32017   #define GPIO4_BASE_NS                            (0x4009E000u)
32018   /** Peripheral GPIO4 base pointer */
32019   #define GPIO4                                    ((GPIO_Type *)GPIO4_BASE)
32020   /** Peripheral GPIO4 base pointer */
32021   #define GPIO4_NS                                 ((GPIO_Type *)GPIO4_BASE_NS)
32022   /** Peripheral GPIO4_ALIAS1 base address */
32023   #define GPIO4_ALIAS1_BASE                        (0x5009F000u)
32024   /** Peripheral GPIO4_ALIAS1 base address */
32025   #define GPIO4_ALIAS1_BASE_NS                     (0x4009F000u)
32026   /** Peripheral GPIO4_ALIAS1 base pointer */
32027   #define GPIO4_ALIAS1                             ((GPIO_Type *)GPIO4_ALIAS1_BASE)
32028   /** Peripheral GPIO4_ALIAS1 base pointer */
32029   #define GPIO4_ALIAS1_NS                          ((GPIO_Type *)GPIO4_ALIAS1_BASE_NS)
32030   /** Peripheral GPIO5 base address */
32031   #define GPIO5_BASE                               (0x50040000u)
32032   /** Peripheral GPIO5 base address */
32033   #define GPIO5_BASE_NS                            (0x40040000u)
32034   /** Peripheral GPIO5 base pointer */
32035   #define GPIO5                                    ((GPIO_Type *)GPIO5_BASE)
32036   /** Peripheral GPIO5 base pointer */
32037   #define GPIO5_NS                                 ((GPIO_Type *)GPIO5_BASE_NS)
32038   /** Peripheral GPIO5_ALIAS1 base address */
32039   #define GPIO5_ALIAS1_BASE                        (0x50041000u)
32040   /** Peripheral GPIO5_ALIAS1 base address */
32041   #define GPIO5_ALIAS1_BASE_NS                     (0x40041000u)
32042   /** Peripheral GPIO5_ALIAS1 base pointer */
32043   #define GPIO5_ALIAS1                             ((GPIO_Type *)GPIO5_ALIAS1_BASE)
32044   /** Peripheral GPIO5_ALIAS1 base pointer */
32045   #define GPIO5_ALIAS1_NS                          ((GPIO_Type *)GPIO5_ALIAS1_BASE_NS)
32046   /** Array initializer of GPIO peripheral base addresses */
32047   #define GPIO_BASE_ADDRS                          { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE }
32048   #define GPIO_ALIAS1_BASE_ADDRS                   { GPIO0_ALIAS1_BASE, GPIO1_ALIAS1_BASE, GPIO2_ALIAS1_BASE, GPIO3_ALIAS1_BASE, GPIO4_ALIAS1_BASE, GPIO5_ALIAS1_BASE }
32049   /** Array initializer of GPIO peripheral base pointers */
32050   #define GPIO_BASE_PTRS                           { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5 }
32051   #define GPIO_ALIAS1_BASE_PTRS                    { GPIO0_ALIAS1, GPIO1_ALIAS1, GPIO2_ALIAS1, GPIO3_ALIAS1, GPIO4_ALIAS1, GPIO5_ALIAS1 }
32052   /** Array initializer of GPIO peripheral base addresses */
32053   #define GPIO_BASE_ADDRS_NS                       { GPIO0_BASE_NS, GPIO1_BASE_NS, GPIO2_BASE_NS, GPIO3_BASE_NS, GPIO4_BASE_NS, GPIO5_BASE_NS }
32054   #define GPIO_ALIAS1_BASE_ADDRS_NS                { GPIO0_ALIAS1_BASE_NS, GPIO1_ALIAS1_BASE_NS, GPIO2_ALIAS1_BASE_NS, GPIO3_ALIAS1_BASE_NS, GPIO4_ALIAS1_BASE_NS, GPIO5_ALIAS1_BASE_NS }
32055   /** Array initializer of GPIO peripheral base pointers */
32056   #define GPIO_BASE_PTRS_NS                        { GPIO0_NS, GPIO1_NS, GPIO2_NS, GPIO3_NS, GPIO4_NS, GPIO5_NS }
32057   #define GPIO_ALIAS1_BASE_PTRS_NS                 { GPIO0_ALIAS1_NS, GPIO1_ALIAS1_NS, GPIO2_ALIAS1_NS, GPIO3_ALIAS1_NS, GPIO4_ALIAS1_NS, GPIO5_ALIAS1_NS }
32058 #else
32059   /** Peripheral GPIO0 base address */
32060   #define GPIO0_BASE                               (0x40096000u)
32061   /** Peripheral GPIO0 base pointer */
32062   #define GPIO0                                    ((GPIO_Type *)GPIO0_BASE)
32063   /** Peripheral GPIO0_ALIAS1 base address */
32064   #define GPIO0_ALIAS1_BASE                        (0x40097000u)
32065   /** Peripheral GPIO0_ALIAS1 base pointer */
32066   #define GPIO0_ALIAS1                             ((GPIO_Type *)GPIO0_ALIAS1_BASE)
32067   /** Peripheral GPIO1 base address */
32068   #define GPIO1_BASE                               (0x40098000u)
32069   /** Peripheral GPIO1 base pointer */
32070   #define GPIO1                                    ((GPIO_Type *)GPIO1_BASE)
32071   /** Peripheral GPIO1_ALIAS1 base address */
32072   #define GPIO1_ALIAS1_BASE                        (0x40099000u)
32073   /** Peripheral GPIO1_ALIAS1 base pointer */
32074   #define GPIO1_ALIAS1                             ((GPIO_Type *)GPIO1_ALIAS1_BASE)
32075   /** Peripheral GPIO2 base address */
32076   #define GPIO2_BASE                               (0x4009A000u)
32077   /** Peripheral GPIO2 base pointer */
32078   #define GPIO2                                    ((GPIO_Type *)GPIO2_BASE)
32079   /** Peripheral GPIO2_ALIAS1 base address */
32080   #define GPIO2_ALIAS1_BASE                        (0x4009B000u)
32081   /** Peripheral GPIO2_ALIAS1 base pointer */
32082   #define GPIO2_ALIAS1                             ((GPIO_Type *)GPIO2_ALIAS1_BASE)
32083   /** Peripheral GPIO3 base address */
32084   #define GPIO3_BASE                               (0x4009C000u)
32085   /** Peripheral GPIO3 base pointer */
32086   #define GPIO3                                    ((GPIO_Type *)GPIO3_BASE)
32087   /** Peripheral GPIO3_ALIAS1 base address */
32088   #define GPIO3_ALIAS1_BASE                        (0x4009D000u)
32089   /** Peripheral GPIO3_ALIAS1 base pointer */
32090   #define GPIO3_ALIAS1                             ((GPIO_Type *)GPIO3_ALIAS1_BASE)
32091   /** Peripheral GPIO4 base address */
32092   #define GPIO4_BASE                               (0x4009E000u)
32093   /** Peripheral GPIO4 base pointer */
32094   #define GPIO4                                    ((GPIO_Type *)GPIO4_BASE)
32095   /** Peripheral GPIO4_ALIAS1 base address */
32096   #define GPIO4_ALIAS1_BASE                        (0x4009F000u)
32097   /** Peripheral GPIO4_ALIAS1 base pointer */
32098   #define GPIO4_ALIAS1                             ((GPIO_Type *)GPIO4_ALIAS1_BASE)
32099   /** Peripheral GPIO5 base address */
32100   #define GPIO5_BASE                               (0x40040000u)
32101   /** Peripheral GPIO5 base pointer */
32102   #define GPIO5                                    ((GPIO_Type *)GPIO5_BASE)
32103   /** Peripheral GPIO5_ALIAS1 base address */
32104   #define GPIO5_ALIAS1_BASE                        (0x40041000u)
32105   /** Peripheral GPIO5_ALIAS1 base pointer */
32106   #define GPIO5_ALIAS1                             ((GPIO_Type *)GPIO5_ALIAS1_BASE)
32107   /** Array initializer of GPIO peripheral base addresses */
32108   #define GPIO_BASE_ADDRS                          { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE }
32109   #define GPIO_ALIAS1_BASE_ADDRS                   { GPIO0_ALIAS1_BASE, GPIO1_ALIAS1_BASE, GPIO2_ALIAS1_BASE, GPIO3_ALIAS1_BASE, GPIO4_ALIAS1_BASE, GPIO5_ALIAS1_BASE }
32110   /** Array initializer of GPIO peripheral base pointers */
32111   #define GPIO_BASE_PTRS                           { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5 }
32112   #define GPIO_ALIAS1_BASE_PTRS                    { GPIO0_ALIAS1, GPIO1_ALIAS1, GPIO2_ALIAS1, GPIO3_ALIAS1, GPIO4_ALIAS1, GPIO5_ALIAS1 }
32113 #endif
32114 /* Interrupt vectors for the GPIO peripheral type */
32115 #define GPIO_IRQS   {GPIO00_IRQn, GPIO10_IRQn, GPIO20_IRQn, GPIO30_IRQn,GPIO40_IRQn,GPIO50_IRQn}
32116 #define GPIO_IRQS_1 {GPIO01_IRQn, GPIO11_IRQn, GPIO21_IRQn, GPIO31_IRQn,GPIO41_IRQn,GPIO51_IRQn}
32117 
32118 
32119 /*!
32120  * @}
32121  */ /* end of group GPIO_Peripheral_Access_Layer */
32122 
32123 
32124 /* ----------------------------------------------------------------------------
32125    -- I2S Peripheral Access Layer
32126    ---------------------------------------------------------------------------- */
32127 
32128 /*!
32129  * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
32130  * @{
32131  */
32132 
32133 /** I2S - Register Layout Typedef */
32134 typedef struct {
32135   __I  uint32_t VERID;                             /**< Version ID, offset: 0x0 */
32136   __I  uint32_t PARAM;                             /**< Parameter, offset: 0x4 */
32137   __IO uint32_t TCSR;                              /**< Transmit Control, offset: 0x8 */
32138   __IO uint32_t TCR1;                              /**< Transmit Configuration 1, offset: 0xC */
32139   __IO uint32_t TCR2;                              /**< Transmit Configuration 2, offset: 0x10 */
32140   __IO uint32_t TCR3;                              /**< Transmit Configuration 3, offset: 0x14 */
32141   __IO uint32_t TCR4;                              /**< Transmit Configuration 4, offset: 0x18 */
32142   __IO uint32_t TCR5;                              /**< Transmit Configuration 5, offset: 0x1C */
32143   __O  uint32_t TDR[2];                            /**< Transmit Data, array offset: 0x20, array step: 0x4 */
32144        uint8_t RESERVED_0[24];
32145   __I  uint32_t TFR[2];                            /**< Transmit FIFO, array offset: 0x40, array step: 0x4 */
32146        uint8_t RESERVED_1[24];
32147   __IO uint32_t TMR;                               /**< Transmit Mask, offset: 0x60 */
32148        uint8_t RESERVED_2[36];
32149   __IO uint32_t RCSR;                              /**< Receive Control, offset: 0x88 */
32150   __IO uint32_t RCR1;                              /**< Receive Configuration 1, offset: 0x8C */
32151   __IO uint32_t RCR2;                              /**< Receive Configuration 2, offset: 0x90 */
32152   __IO uint32_t RCR3;                              /**< Receive Configuration 3, offset: 0x94 */
32153   __IO uint32_t RCR4;                              /**< Receive Configuration 4, offset: 0x98 */
32154   __IO uint32_t RCR5;                              /**< Receive Configuration 5, offset: 0x9C */
32155   __I  uint32_t RDR[2];                            /**< Receive Data, array offset: 0xA0, array step: 0x4 */
32156        uint8_t RESERVED_3[24];
32157   __I  uint32_t RFR[2];                            /**< Receive FIFO, array offset: 0xC0, array step: 0x4 */
32158        uint8_t RESERVED_4[24];
32159   __IO uint32_t RMR;                               /**< Receive Mask, offset: 0xE0 */
32160        uint8_t RESERVED_5[28];
32161   __IO uint32_t MCR;                               /**< MCLK Control, offset: 0x100 */
32162 } I2S_Type;
32163 
32164 /* ----------------------------------------------------------------------------
32165    -- I2S Register Masks
32166    ---------------------------------------------------------------------------- */
32167 
32168 /*!
32169  * @addtogroup I2S_Register_Masks I2S Register Masks
32170  * @{
32171  */
32172 
32173 /*! @name VERID - Version ID */
32174 /*! @{ */
32175 
32176 #define I2S_VERID_FEATURE_MASK                   (0xFFFFU)
32177 #define I2S_VERID_FEATURE_SHIFT                  (0U)
32178 /*! FEATURE - Feature Specification Number
32179  *  0b0000000000000000..Standard feature set
32180  */
32181 #define I2S_VERID_FEATURE(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_VERID_FEATURE_SHIFT)) & I2S_VERID_FEATURE_MASK)
32182 
32183 #define I2S_VERID_MINOR_MASK                     (0xFF0000U)
32184 #define I2S_VERID_MINOR_SHIFT                    (16U)
32185 /*! MINOR - Minor Version Number */
32186 #define I2S_VERID_MINOR(x)                       (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MINOR_SHIFT)) & I2S_VERID_MINOR_MASK)
32187 
32188 #define I2S_VERID_MAJOR_MASK                     (0xFF000000U)
32189 #define I2S_VERID_MAJOR_SHIFT                    (24U)
32190 /*! MAJOR - Major Version Number */
32191 #define I2S_VERID_MAJOR(x)                       (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MAJOR_SHIFT)) & I2S_VERID_MAJOR_MASK)
32192 /*! @} */
32193 
32194 /*! @name PARAM - Parameter */
32195 /*! @{ */
32196 
32197 #define I2S_PARAM_DATALINE_MASK                  (0xFU)
32198 #define I2S_PARAM_DATALINE_SHIFT                 (0U)
32199 /*! DATALINE - Number of Data Lines */
32200 #define I2S_PARAM_DATALINE(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_DATALINE_SHIFT)) & I2S_PARAM_DATALINE_MASK)
32201 
32202 #define I2S_PARAM_FIFO_MASK                      (0xF00U)
32203 #define I2S_PARAM_FIFO_SHIFT                     (8U)
32204 /*! FIFO - FIFO Size */
32205 #define I2S_PARAM_FIFO(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FIFO_SHIFT)) & I2S_PARAM_FIFO_MASK)
32206 
32207 #define I2S_PARAM_FRAME_MASK                     (0xF0000U)
32208 #define I2S_PARAM_FRAME_SHIFT                    (16U)
32209 /*! FRAME - Frame Size */
32210 #define I2S_PARAM_FRAME(x)                       (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FRAME_SHIFT)) & I2S_PARAM_FRAME_MASK)
32211 /*! @} */
32212 
32213 /*! @name TCSR - Transmit Control */
32214 /*! @{ */
32215 
32216 #define I2S_TCSR_FRDE_MASK                       (0x1U)
32217 #define I2S_TCSR_FRDE_SHIFT                      (0U)
32218 /*! FRDE - FIFO Request DMA Enable
32219  *  0b0..Disable
32220  *  0b1..Enable
32221  */
32222 #define I2S_TCSR_FRDE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK)
32223 
32224 #define I2S_TCSR_FWDE_MASK                       (0x2U)
32225 #define I2S_TCSR_FWDE_SHIFT                      (1U)
32226 /*! FWDE - FIFO Warning DMA Enable
32227  *  0b0..Disable
32228  *  0b1..Enable
32229  */
32230 #define I2S_TCSR_FWDE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK)
32231 
32232 #define I2S_TCSR_FRIE_MASK                       (0x100U)
32233 #define I2S_TCSR_FRIE_SHIFT                      (8U)
32234 /*! FRIE - FIFO Request Interrupt Enable
32235  *  0b0..Disable
32236  *  0b1..Enable
32237  */
32238 #define I2S_TCSR_FRIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK)
32239 
32240 #define I2S_TCSR_FWIE_MASK                       (0x200U)
32241 #define I2S_TCSR_FWIE_SHIFT                      (9U)
32242 /*! FWIE - FIFO Warning Interrupt Enable
32243  *  0b0..Disable
32244  *  0b1..Enable
32245  */
32246 #define I2S_TCSR_FWIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK)
32247 
32248 #define I2S_TCSR_FEIE_MASK                       (0x400U)
32249 #define I2S_TCSR_FEIE_SHIFT                      (10U)
32250 /*! FEIE - FIFO Error Interrupt Enable
32251  *  0b0..Disable
32252  *  0b1..Enable
32253  */
32254 #define I2S_TCSR_FEIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK)
32255 
32256 #define I2S_TCSR_SEIE_MASK                       (0x800U)
32257 #define I2S_TCSR_SEIE_SHIFT                      (11U)
32258 /*! SEIE - Sync Error Interrupt Enable
32259  *  0b0..Disable
32260  *  0b1..Enable
32261  */
32262 #define I2S_TCSR_SEIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK)
32263 
32264 #define I2S_TCSR_WSIE_MASK                       (0x1000U)
32265 #define I2S_TCSR_WSIE_SHIFT                      (12U)
32266 /*! WSIE - Word Start Interrupt Enable
32267  *  0b0..Disable
32268  *  0b1..Enable
32269  */
32270 #define I2S_TCSR_WSIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK)
32271 
32272 #define I2S_TCSR_FRF_MASK                        (0x10000U)
32273 #define I2S_TCSR_FRF_SHIFT                       (16U)
32274 /*! FRF - FIFO Request Flag
32275  *  0b0..Watermark not reached
32276  *  0b1..Watermark reached
32277  */
32278 #define I2S_TCSR_FRF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK)
32279 
32280 #define I2S_TCSR_FWF_MASK                        (0x20000U)
32281 #define I2S_TCSR_FWF_SHIFT                       (17U)
32282 /*! FWF - FIFO Warning Flag
32283  *  0b0..Not empty
32284  *  0b1..Empty
32285  */
32286 #define I2S_TCSR_FWF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK)
32287 
32288 #define I2S_TCSR_FEF_MASK                        (0x40000U)
32289 #define I2S_TCSR_FEF_SHIFT                       (18U)
32290 /*! FEF - FIFO Error Flag
32291  *  0b0..Not detected
32292  *  0b1..Detected
32293  *  0b0..No effect
32294  *  0b1..Clear the flag
32295  */
32296 #define I2S_TCSR_FEF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
32297 
32298 #define I2S_TCSR_SEF_MASK                        (0x80000U)
32299 #define I2S_TCSR_SEF_SHIFT                       (19U)
32300 /*! SEF - Sync Error Flag
32301  *  0b0..Not detected
32302  *  0b1..Detected
32303  *  0b0..No effect
32304  *  0b1..Clear the flag
32305  */
32306 #define I2S_TCSR_SEF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK)
32307 
32308 #define I2S_TCSR_WSF_MASK                        (0x100000U)
32309 #define I2S_TCSR_WSF_SHIFT                       (20U)
32310 /*! WSF - Word Start Flag
32311  *  0b0..Not detected
32312  *  0b1..Detected
32313  *  0b0..No effect
32314  *  0b1..Clear the flag
32315  */
32316 #define I2S_TCSR_WSF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK)
32317 
32318 #define I2S_TCSR_SR_MASK                         (0x1000000U)
32319 #define I2S_TCSR_SR_SHIFT                        (24U)
32320 /*! SR - Software Reset
32321  *  0b0..No effect
32322  *  0b1..Software reset
32323  */
32324 #define I2S_TCSR_SR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK)
32325 
32326 #define I2S_TCSR_FR_MASK                         (0x2000000U)
32327 #define I2S_TCSR_FR_SHIFT                        (25U)
32328 /*! FR - FIFO Reset
32329  *  0b0..No effect
32330  *  0b1..FIFO reset
32331  */
32332 #define I2S_TCSR_FR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK)
32333 
32334 #define I2S_TCSR_BCE_MASK                        (0x10000000U)
32335 #define I2S_TCSR_BCE_SHIFT                       (28U)
32336 /*! BCE - Bit Clock Enable
32337  *  0b0..Disable
32338  *  0b1..Enable
32339  */
32340 #define I2S_TCSR_BCE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK)
32341 
32342 #define I2S_TCSR_DBGE_MASK                       (0x20000000U)
32343 #define I2S_TCSR_DBGE_SHIFT                      (29U)
32344 /*! DBGE - Debug Enable
32345  *  0b0..Disable
32346  *  0b1..Enable
32347  */
32348 #define I2S_TCSR_DBGE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK)
32349 
32350 #define I2S_TCSR_STOPE_MASK                      (0x40000000U)
32351 #define I2S_TCSR_STOPE_SHIFT                     (30U)
32352 /*! STOPE - Stop Enable
32353  *  0b0..Disable
32354  *  0b1..Enable
32355  */
32356 #define I2S_TCSR_STOPE(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK)
32357 
32358 #define I2S_TCSR_TE_MASK                         (0x80000000U)
32359 #define I2S_TCSR_TE_SHIFT                        (31U)
32360 /*! TE - Transmitter Enable
32361  *  0b0..Disable
32362  *  0b1..Enable (or transmitter has been disabled and has not yet reached the end of the frame)
32363  */
32364 #define I2S_TCSR_TE(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK)
32365 /*! @} */
32366 
32367 /*! @name TCR1 - Transmit Configuration 1 */
32368 /*! @{ */
32369 
32370 #define I2S_TCR1_TFW_MASK                        (0x7U)
32371 #define I2S_TCR1_TFW_SHIFT                       (0U)
32372 /*! TFW - Transmit FIFO Watermark
32373  *  0b000..1
32374  *  0b001..2
32375  *  0b010-0b110..(TFW +1)
32376  *  0b111..8
32377  */
32378 #define I2S_TCR1_TFW(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK)
32379 /*! @} */
32380 
32381 /*! @name TCR2 - Transmit Configuration 2 */
32382 /*! @{ */
32383 
32384 #define I2S_TCR2_DIV_MASK                        (0xFFU)
32385 #define I2S_TCR2_DIV_SHIFT                       (0U)
32386 /*! DIV - Bit Clock Divide */
32387 #define I2S_TCR2_DIV(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK)
32388 
32389 #define I2S_TCR2_BYP_MASK                        (0x800000U)
32390 #define I2S_TCR2_BYP_SHIFT                       (23U)
32391 /*! BYP - Bit Clock Bypass
32392  *  0b0..Disable
32393  *  0b1..Enable
32394  */
32395 #define I2S_TCR2_BYP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BYP_SHIFT)) & I2S_TCR2_BYP_MASK)
32396 
32397 #define I2S_TCR2_BCD_MASK                        (0x1000000U)
32398 #define I2S_TCR2_BCD_SHIFT                       (24U)
32399 /*! BCD - Bit Clock Direction
32400  *  0b0..Generate externally in Target mode
32401  *  0b1..Generate internally in Controller mode
32402  */
32403 #define I2S_TCR2_BCD(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK)
32404 
32405 #define I2S_TCR2_BCP_MASK                        (0x2000000U)
32406 #define I2S_TCR2_BCP_SHIFT                       (25U)
32407 /*! BCP - Bit Clock Polarity
32408  *  0b0..Active high
32409  *  0b1..Active low
32410  */
32411 #define I2S_TCR2_BCP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK)
32412 
32413 #define I2S_TCR2_MSEL_MASK                       (0xC000000U)
32414 #define I2S_TCR2_MSEL_SHIFT                      (26U)
32415 /*! MSEL - MCLK Select
32416  *  0b00..Bus clock
32417  *  0b01..Controller clock (MCLK) option 1
32418  *  0b10..Controller clock (MCLK) option 2
32419  *  0b11..Controller clock (MCLK) option 3
32420  */
32421 #define I2S_TCR2_MSEL(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK)
32422 
32423 #define I2S_TCR2_BCI_MASK                        (0x10000000U)
32424 #define I2S_TCR2_BCI_SHIFT                       (28U)
32425 /*! BCI - Bit Clock Input
32426  *  0b0..Disable
32427  *  0b1..Enable
32428  */
32429 #define I2S_TCR2_BCI(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK)
32430 
32431 #define I2S_TCR2_BCS_MASK                        (0x20000000U)
32432 #define I2S_TCR2_BCS_SHIFT                       (29U)
32433 /*! BCS - Bit Clock Swap
32434  *  0b0..Use the normal bit clock source
32435  *  0b1..Swap the bit clock source
32436  */
32437 #define I2S_TCR2_BCS(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK)
32438 
32439 #define I2S_TCR2_SYNC_MASK                       (0xC0000000U)
32440 #define I2S_TCR2_SYNC_SHIFT                      (30U)
32441 /*! SYNC - Synchronous Mode
32442  *  0b00..Asynchronous mode
32443  *  0b01..Synchronous with receiver
32444  *  0b10..Synchronous with another SAI transmitter
32445  *  0b11..Synchronous with another SAI receiver
32446  */
32447 #define I2S_TCR2_SYNC(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK)
32448 /*! @} */
32449 
32450 /*! @name TCR3 - Transmit Configuration 3 */
32451 /*! @{ */
32452 
32453 #define I2S_TCR3_WDFL_MASK                       (0x1FU)
32454 #define I2S_TCR3_WDFL_SHIFT                      (0U)
32455 /*! WDFL - Word Flag Configuration */
32456 #define I2S_TCR3_WDFL(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK)
32457 
32458 #define I2S_TCR3_TCE_MASK                        (0x30000U)
32459 #define I2S_TCR3_TCE_SHIFT                       (16U)
32460 /*! TCE - Transmit Channel Enable */
32461 #define I2S_TCR3_TCE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK)
32462 
32463 #define I2S_TCR3_CFR_MASK                        (0x3000000U)
32464 #define I2S_TCR3_CFR_SHIFT                       (24U)
32465 /*! CFR - Channel FIFO Reset */
32466 #define I2S_TCR3_CFR(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_CFR_SHIFT)) & I2S_TCR3_CFR_MASK)
32467 /*! @} */
32468 
32469 /*! @name TCR4 - Transmit Configuration 4 */
32470 /*! @{ */
32471 
32472 #define I2S_TCR4_FSD_MASK                        (0x1U)
32473 #define I2S_TCR4_FSD_SHIFT                       (0U)
32474 /*! FSD - Frame Sync Direction
32475  *  0b0..Generated externally in Target mode
32476  *  0b1..Generated internally in Controller mode
32477  */
32478 #define I2S_TCR4_FSD(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK)
32479 
32480 #define I2S_TCR4_FSP_MASK                        (0x2U)
32481 #define I2S_TCR4_FSP_SHIFT                       (1U)
32482 /*! FSP - Frame Sync Polarity
32483  *  0b0..Active high
32484  *  0b1..Active low
32485  */
32486 #define I2S_TCR4_FSP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK)
32487 
32488 #define I2S_TCR4_ONDEM_MASK                      (0x4U)
32489 #define I2S_TCR4_ONDEM_SHIFT                     (2U)
32490 /*! ONDEM - On-Demand Mode
32491  *  0b0..Generated continuously
32492  *  0b1..Generated after the FIFO warning flag is cleared
32493  */
32494 #define I2S_TCR4_ONDEM(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK)
32495 
32496 #define I2S_TCR4_FSE_MASK                        (0x8U)
32497 #define I2S_TCR4_FSE_SHIFT                       (3U)
32498 /*! FSE - Frame Sync Early
32499  *  0b0..First bit of the frame
32500  *  0b1..One bit before the first bit of the frame
32501  */
32502 #define I2S_TCR4_FSE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK)
32503 
32504 #define I2S_TCR4_MF_MASK                         (0x10U)
32505 #define I2S_TCR4_MF_SHIFT                        (4U)
32506 /*! MF - MSB First
32507  *  0b0..LSB
32508  *  0b1..MSB
32509  */
32510 #define I2S_TCR4_MF(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK)
32511 
32512 #define I2S_TCR4_CHMOD_MASK                      (0x20U)
32513 #define I2S_TCR4_CHMOD_SHIFT                     (5U)
32514 /*! CHMOD - Channel Mode
32515  *  0b0..TDM mode
32516  *  0b1..Output mode
32517  */
32518 #define I2S_TCR4_CHMOD(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_CHMOD_SHIFT)) & I2S_TCR4_CHMOD_MASK)
32519 
32520 #define I2S_TCR4_SYWD_MASK                       (0x1F00U)
32521 #define I2S_TCR4_SYWD_SHIFT                      (8U)
32522 /*! SYWD - Sync Width */
32523 #define I2S_TCR4_SYWD(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
32524 
32525 #define I2S_TCR4_FRSZ_MASK                       (0x1F0000U)
32526 #define I2S_TCR4_FRSZ_SHIFT                      (16U)
32527 /*! FRSZ - Frame Size */
32528 #define I2S_TCR4_FRSZ(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK)
32529 
32530 #define I2S_TCR4_FPACK_MASK                      (0x3000000U)
32531 #define I2S_TCR4_FPACK_SHIFT                     (24U)
32532 /*! FPACK - FIFO Packing Mode
32533  *  0b00..Disable FIFO packing
32534  *  0b01..Reserved
32535  *  0b10..Enable 8-bit FIFO packing
32536  *  0b11..Enable 16-bit FIFO packing
32537  */
32538 #define I2S_TCR4_FPACK(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK)
32539 
32540 #define I2S_TCR4_FCOMB_MASK                      (0xC000000U)
32541 #define I2S_TCR4_FCOMB_SHIFT                     (26U)
32542 /*! FCOMB - FIFO Combine Mode
32543  *  0b00..Disable
32544  *  0b01..Enable on FIFO reads (from transmit shift registers)
32545  *  0b10..Enable on FIFO writes (by software)
32546  *  0b11..Enable on FIFO reads (from transmit shift registers) and writes (by software)
32547  */
32548 #define I2S_TCR4_FCOMB(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCOMB_SHIFT)) & I2S_TCR4_FCOMB_MASK)
32549 
32550 #define I2S_TCR4_FCONT_MASK                      (0x10000000U)
32551 #define I2S_TCR4_FCONT_SHIFT                     (28U)
32552 /*! FCONT - FIFO Continue on Error
32553  *  0b0..Continue from the start of the next frame
32554  *  0b1..Continue from the same word that caused the FIFO error
32555  */
32556 #define I2S_TCR4_FCONT(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK)
32557 /*! @} */
32558 
32559 /*! @name TCR5 - Transmit Configuration 5 */
32560 /*! @{ */
32561 
32562 #define I2S_TCR5_FBT_MASK                        (0x1F00U)
32563 #define I2S_TCR5_FBT_SHIFT                       (8U)
32564 /*! FBT - First Bit Shifted
32565  *  0b00000..0
32566  *  0b00001-0b11110..FBT
32567  *  0b11111..31
32568  */
32569 #define I2S_TCR5_FBT(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK)
32570 
32571 #define I2S_TCR5_W0W_MASK                        (0x1F0000U)
32572 #define I2S_TCR5_W0W_SHIFT                       (16U)
32573 /*! W0W - Word 0 Width
32574  *  0b00111..8
32575  *  0b01000..9
32576  *  0b01001-0b11110..(W0W value + 1)
32577  *  0b11111..32
32578  */
32579 #define I2S_TCR5_W0W(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK)
32580 
32581 #define I2S_TCR5_WNW_MASK                        (0x1F000000U)
32582 #define I2S_TCR5_WNW_SHIFT                       (24U)
32583 /*! WNW - Word N Width
32584  *  0b00111..8
32585  *  0b01000..9
32586  *  0b01001-0b11110..(WNW value + 1)
32587  *  0b11111..32
32588  */
32589 #define I2S_TCR5_WNW(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK)
32590 /*! @} */
32591 
32592 /*! @name TDR - Transmit Data */
32593 /*! @{ */
32594 
32595 #define I2S_TDR_TDR_MASK                         (0xFFFFFFFFU)
32596 #define I2S_TDR_TDR_SHIFT                        (0U)
32597 /*! TDR - Transmit Data */
32598 #define I2S_TDR_TDR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK)
32599 /*! @} */
32600 
32601 /* The count of I2S_TDR */
32602 #define I2S_TDR_COUNT                            (2U)
32603 
32604 /*! @name TFR - Transmit FIFO */
32605 /*! @{ */
32606 
32607 #define I2S_TFR_RFP_MASK                         (0xFU)
32608 #define I2S_TFR_RFP_SHIFT                        (0U)
32609 /*! RFP - Read FIFO Pointer */
32610 #define I2S_TFR_RFP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK)
32611 
32612 #define I2S_TFR_WFP_MASK                         (0xF0000U)
32613 #define I2S_TFR_WFP_SHIFT                        (16U)
32614 /*! WFP - Write FIFO Pointer */
32615 #define I2S_TFR_WFP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK)
32616 
32617 #define I2S_TFR_WCP_MASK                         (0x80000000U)
32618 #define I2S_TFR_WCP_SHIFT                        (31U)
32619 /*! WCP - Write Channel Pointer
32620  *  0b0..No effect
32621  *  0b1..Next FIFO to be written
32622  */
32623 #define I2S_TFR_WCP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WCP_SHIFT)) & I2S_TFR_WCP_MASK)
32624 /*! @} */
32625 
32626 /* The count of I2S_TFR */
32627 #define I2S_TFR_COUNT                            (2U)
32628 
32629 /*! @name TMR - Transmit Mask */
32630 /*! @{ */
32631 
32632 #define I2S_TMR_TWM_MASK                         (0xFFFFFFFFU)
32633 #define I2S_TMR_TWM_SHIFT                        (0U)
32634 /*! TWM - Transmit Word Mask
32635  *  0b00000000000000000000000000000000..Enable
32636  *  0b00000000000000000000000000000001..Mask
32637  */
32638 #define I2S_TMR_TWM(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK)
32639 /*! @} */
32640 
32641 /*! @name RCSR - Receive Control */
32642 /*! @{ */
32643 
32644 #define I2S_RCSR_FRDE_MASK                       (0x1U)
32645 #define I2S_RCSR_FRDE_SHIFT                      (0U)
32646 /*! FRDE - FIFO Request DMA Enable
32647  *  0b0..Disable
32648  *  0b1..Enable
32649  */
32650 #define I2S_RCSR_FRDE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK)
32651 
32652 #define I2S_RCSR_FWDE_MASK                       (0x2U)
32653 #define I2S_RCSR_FWDE_SHIFT                      (1U)
32654 /*! FWDE - FIFO Warning DMA Enable
32655  *  0b0..Disable
32656  *  0b1..Enable
32657  */
32658 #define I2S_RCSR_FWDE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK)
32659 
32660 #define I2S_RCSR_FRIE_MASK                       (0x100U)
32661 #define I2S_RCSR_FRIE_SHIFT                      (8U)
32662 /*! FRIE - FIFO Request Interrupt Enable
32663  *  0b0..Disable
32664  *  0b1..Enable
32665  */
32666 #define I2S_RCSR_FRIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK)
32667 
32668 #define I2S_RCSR_FWIE_MASK                       (0x200U)
32669 #define I2S_RCSR_FWIE_SHIFT                      (9U)
32670 /*! FWIE - FIFO Warning Interrupt Enable
32671  *  0b0..Disable
32672  *  0b1..Enable
32673  */
32674 #define I2S_RCSR_FWIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK)
32675 
32676 #define I2S_RCSR_FEIE_MASK                       (0x400U)
32677 #define I2S_RCSR_FEIE_SHIFT                      (10U)
32678 /*! FEIE - FIFO Error Interrupt Enable
32679  *  0b0..Disable
32680  *  0b1..Enable
32681  */
32682 #define I2S_RCSR_FEIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK)
32683 
32684 #define I2S_RCSR_SEIE_MASK                       (0x800U)
32685 #define I2S_RCSR_SEIE_SHIFT                      (11U)
32686 /*! SEIE - Sync Error Interrupt Enable
32687  *  0b0..Disable
32688  *  0b1..Enable
32689  */
32690 #define I2S_RCSR_SEIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK)
32691 
32692 #define I2S_RCSR_WSIE_MASK                       (0x1000U)
32693 #define I2S_RCSR_WSIE_SHIFT                      (12U)
32694 /*! WSIE - Word Start Interrupt Enable
32695  *  0b0..Disable
32696  *  0b1..Enable
32697  */
32698 #define I2S_RCSR_WSIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK)
32699 
32700 #define I2S_RCSR_FRF_MASK                        (0x10000U)
32701 #define I2S_RCSR_FRF_SHIFT                       (16U)
32702 /*! FRF - FIFO Request Flag
32703  *  0b0..Watermark not reached
32704  *  0b1..Watermark reached
32705  */
32706 #define I2S_RCSR_FRF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK)
32707 
32708 #define I2S_RCSR_FWF_MASK                        (0x20000U)
32709 #define I2S_RCSR_FWF_SHIFT                       (17U)
32710 /*! FWF - FIFO Warning Flag
32711  *  0b0..Not full
32712  *  0b1..Full
32713  */
32714 #define I2S_RCSR_FWF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK)
32715 
32716 #define I2S_RCSR_FEF_MASK                        (0x40000U)
32717 #define I2S_RCSR_FEF_SHIFT                       (18U)
32718 /*! FEF - FIFO Error Flag
32719  *  0b0..No error
32720  *  0b1..Receive overflow detected
32721  *  0b0..No effect
32722  *  0b1..Clear the flag
32723  */
32724 #define I2S_RCSR_FEF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK)
32725 
32726 #define I2S_RCSR_SEF_MASK                        (0x80000U)
32727 #define I2S_RCSR_SEF_SHIFT                       (19U)
32728 /*! SEF - Sync Error Flag
32729  *  0b0..Not detected
32730  *  0b1..Detected
32731  *  0b0..No effect
32732  *  0b1..Clear the flag
32733  */
32734 #define I2S_RCSR_SEF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK)
32735 
32736 #define I2S_RCSR_WSF_MASK                        (0x100000U)
32737 #define I2S_RCSR_WSF_SHIFT                       (20U)
32738 /*! WSF - Word Start Flag
32739  *  0b0..Not detected
32740  *  0b1..Detected
32741  *  0b0..No effect
32742  *  0b1..Clear the flag
32743  */
32744 #define I2S_RCSR_WSF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK)
32745 
32746 #define I2S_RCSR_SR_MASK                         (0x1000000U)
32747 #define I2S_RCSR_SR_SHIFT                        (24U)
32748 /*! SR - Software Reset
32749  *  0b0..No effect
32750  *  0b1..Software reset
32751  */
32752 #define I2S_RCSR_SR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK)
32753 
32754 #define I2S_RCSR_FR_MASK                         (0x2000000U)
32755 #define I2S_RCSR_FR_SHIFT                        (25U)
32756 /*! FR - FIFO Reset
32757  *  0b0..No effect
32758  *  0b1..Reset
32759  */
32760 #define I2S_RCSR_FR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK)
32761 
32762 #define I2S_RCSR_BCE_MASK                        (0x10000000U)
32763 #define I2S_RCSR_BCE_SHIFT                       (28U)
32764 /*! BCE - Bit Clock Enable
32765  *  0b0..Disable
32766  *  0b1..Enable
32767  */
32768 #define I2S_RCSR_BCE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK)
32769 
32770 #define I2S_RCSR_DBGE_MASK                       (0x20000000U)
32771 #define I2S_RCSR_DBGE_SHIFT                      (29U)
32772 /*! DBGE - Debug Enable
32773  *  0b0..Disable after completing the current frame
32774  *  0b1..Enable
32775  */
32776 #define I2S_RCSR_DBGE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK)
32777 
32778 #define I2S_RCSR_STOPE_MASK                      (0x40000000U)
32779 #define I2S_RCSR_STOPE_SHIFT                     (30U)
32780 /*! STOPE - Stop Enable
32781  *  0b0..Disable
32782  *  0b1..Enable
32783  */
32784 #define I2S_RCSR_STOPE(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK)
32785 
32786 #define I2S_RCSR_RE_MASK                         (0x80000000U)
32787 #define I2S_RCSR_RE_SHIFT                        (31U)
32788 /*! RE - Receiver Enable
32789  *  0b0..Disable
32790  *  0b1..Enable (or receiver disabled and not yet reached end of frame)
32791  */
32792 #define I2S_RCSR_RE(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK)
32793 /*! @} */
32794 
32795 /*! @name RCR1 - Receive Configuration 1 */
32796 /*! @{ */
32797 
32798 #define I2S_RCR1_RFW_MASK                        (0x7U)
32799 #define I2S_RCR1_RFW_SHIFT                       (0U)
32800 /*! RFW - Receive FIFO Watermark
32801  *  0b000..1
32802  *  0b001..2
32803  *  0b010-0b110..(RFW value + 1)
32804  *  0b111..8
32805  */
32806 #define I2S_RCR1_RFW(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK)
32807 /*! @} */
32808 
32809 /*! @name RCR2 - Receive Configuration 2 */
32810 /*! @{ */
32811 
32812 #define I2S_RCR2_DIV_MASK                        (0xFFU)
32813 #define I2S_RCR2_DIV_SHIFT                       (0U)
32814 /*! DIV - Bit Clock Divide */
32815 #define I2S_RCR2_DIV(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK)
32816 
32817 #define I2S_RCR2_BYP_MASK                        (0x800000U)
32818 #define I2S_RCR2_BYP_SHIFT                       (23U)
32819 /*! BYP - Bit Clock Bypass
32820  *  0b0..Disable
32821  *  0b1..Enable
32822  */
32823 #define I2S_RCR2_BYP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BYP_SHIFT)) & I2S_RCR2_BYP_MASK)
32824 
32825 #define I2S_RCR2_BCD_MASK                        (0x1000000U)
32826 #define I2S_RCR2_BCD_SHIFT                       (24U)
32827 /*! BCD - Bit Clock Direction
32828  *  0b0..Generated externally in Target mode
32829  *  0b1..Generated internally in Controller mode
32830  */
32831 #define I2S_RCR2_BCD(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK)
32832 
32833 #define I2S_RCR2_BCP_MASK                        (0x2000000U)
32834 #define I2S_RCR2_BCP_SHIFT                       (25U)
32835 /*! BCP - Bit Clock Polarity
32836  *  0b0..Active high
32837  *  0b1..Active low
32838  */
32839 #define I2S_RCR2_BCP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK)
32840 
32841 #define I2S_RCR2_MSEL_MASK                       (0xC000000U)
32842 #define I2S_RCR2_MSEL_SHIFT                      (26U)
32843 /*! MSEL - MCLK Select
32844  *  0b00..Bus clock
32845  *  0b01..Controller clock (MCLK) option 1
32846  *  0b10..Controller clock (MCLK) option 2
32847  *  0b11..Controller clock (MCLK) option 3
32848  */
32849 #define I2S_RCR2_MSEL(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK)
32850 
32851 #define I2S_RCR2_BCI_MASK                        (0x10000000U)
32852 #define I2S_RCR2_BCI_SHIFT                       (28U)
32853 /*! BCI - Bit Clock Input
32854  *  0b0..Disable
32855  *  0b1..Enable
32856  */
32857 #define I2S_RCR2_BCI(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK)
32858 
32859 #define I2S_RCR2_BCS_MASK                        (0x20000000U)
32860 #define I2S_RCR2_BCS_SHIFT                       (29U)
32861 /*! BCS - Bit Clock Swap
32862  *  0b0..Use the normal bit clock source
32863  *  0b1..Swap the bit clock source
32864  */
32865 #define I2S_RCR2_BCS(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK)
32866 
32867 #define I2S_RCR2_SYNC_MASK                       (0xC0000000U)
32868 #define I2S_RCR2_SYNC_SHIFT                      (30U)
32869 /*! SYNC - Synchronous Mode
32870  *  0b00..Asynchronous mode
32871  *  0b01..Synchronous with transmitter
32872  *  0b10..Synchronous with another SAI receiver
32873  *  0b11..Synchronous with another SAI transmitter
32874  */
32875 #define I2S_RCR2_SYNC(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK)
32876 /*! @} */
32877 
32878 /*! @name RCR3 - Receive Configuration 3 */
32879 /*! @{ */
32880 
32881 #define I2S_RCR3_WDFL_MASK                       (0x1FU)
32882 #define I2S_RCR3_WDFL_SHIFT                      (0U)
32883 /*! WDFL - Word Flag Configuration
32884  *  0b00000..Word 1
32885  *  0b00001..Word 2
32886  *  0b00010-0b11110..Word (WDFL value + 1)
32887  *  0b11111..Word 32
32888  */
32889 #define I2S_RCR3_WDFL(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK)
32890 
32891 #define I2S_RCR3_RCE_MASK                        (0x30000U)
32892 #define I2S_RCR3_RCE_SHIFT                       (16U)
32893 /*! RCE - Receive Channel Enable */
32894 #define I2S_RCR3_RCE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK)
32895 
32896 #define I2S_RCR3_CFR_MASK                        (0x3000000U)
32897 #define I2S_RCR3_CFR_SHIFT                       (24U)
32898 /*! CFR - Channel FIFO Reset */
32899 #define I2S_RCR3_CFR(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_CFR_SHIFT)) & I2S_RCR3_CFR_MASK)
32900 /*! @} */
32901 
32902 /*! @name RCR4 - Receive Configuration 4 */
32903 /*! @{ */
32904 
32905 #define I2S_RCR4_FSD_MASK                        (0x1U)
32906 #define I2S_RCR4_FSD_SHIFT                       (0U)
32907 /*! FSD - Frame Sync Direction
32908  *  0b0..Generated externally in Target mode
32909  *  0b1..Generated internally in Controller mode
32910  */
32911 #define I2S_RCR4_FSD(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK)
32912 
32913 #define I2S_RCR4_FSP_MASK                        (0x2U)
32914 #define I2S_RCR4_FSP_SHIFT                       (1U)
32915 /*! FSP - Frame Sync Polarity
32916  *  0b0..Active high
32917  *  0b1..Active low
32918  */
32919 #define I2S_RCR4_FSP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK)
32920 
32921 #define I2S_RCR4_ONDEM_MASK                      (0x4U)
32922 #define I2S_RCR4_ONDEM_SHIFT                     (2U)
32923 /*! ONDEM - On-Demand Mode
32924  *  0b0..Generated continuously
32925  *  0b1..Generated when the FIFO warning flag is 0
32926  */
32927 #define I2S_RCR4_ONDEM(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK)
32928 
32929 #define I2S_RCR4_FSE_MASK                        (0x8U)
32930 #define I2S_RCR4_FSE_SHIFT                       (3U)
32931 /*! FSE - Frame Sync Early
32932  *  0b0..First bit of the frame
32933  *  0b1..One bit before the first bit of the frame
32934  */
32935 #define I2S_RCR4_FSE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK)
32936 
32937 #define I2S_RCR4_MF_MASK                         (0x10U)
32938 #define I2S_RCR4_MF_SHIFT                        (4U)
32939 /*! MF - MSB First
32940  *  0b0..LSB
32941  *  0b1..MSB
32942  */
32943 #define I2S_RCR4_MF(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK)
32944 
32945 #define I2S_RCR4_SYWD_MASK                       (0x1F00U)
32946 #define I2S_RCR4_SYWD_SHIFT                      (8U)
32947 /*! SYWD - Sync Width
32948  *  0b00000..1
32949  *  0b00001..2
32950  *  0b00010-0b11110..(SYWD value + 1)
32951  *  0b11111..32
32952  */
32953 #define I2S_RCR4_SYWD(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK)
32954 
32955 #define I2S_RCR4_FRSZ_MASK                       (0x1F0000U)
32956 #define I2S_RCR4_FRSZ_SHIFT                      (16U)
32957 /*! FRSZ - Frame Size
32958  *  0b00000..1
32959  *  0b00001..2
32960  *  0b00010-0b11110..(FRSZ value + 1)
32961  *  0b11111..32
32962  */
32963 #define I2S_RCR4_FRSZ(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK)
32964 
32965 #define I2S_RCR4_FPACK_MASK                      (0x3000000U)
32966 #define I2S_RCR4_FPACK_SHIFT                     (24U)
32967 /*! FPACK - FIFO Packing Mode
32968  *  0b00..Disable
32969  *  0b01..Reserved
32970  *  0b10..Enable 8-bit FIFO packing
32971  *  0b11..Enable 16-bit FIFO packing
32972  */
32973 #define I2S_RCR4_FPACK(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK)
32974 
32975 #define I2S_RCR4_FCOMB_MASK                      (0xC000000U)
32976 #define I2S_RCR4_FCOMB_SHIFT                     (26U)
32977 /*! FCOMB - FIFO Combine Mode
32978  *  0b00..Disable
32979  *  0b01..Enable on FIFO writes (from receive shift registers)
32980  *  0b10..Enable on FIFO reads (by software)
32981  *  0b11..Enable on FIFO writes (from receive shift registers) and reads (by software)
32982  */
32983 #define I2S_RCR4_FCOMB(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCOMB_SHIFT)) & I2S_RCR4_FCOMB_MASK)
32984 
32985 #define I2S_RCR4_FCONT_MASK                      (0x10000000U)
32986 #define I2S_RCR4_FCONT_SHIFT                     (28U)
32987 /*! FCONT - FIFO Continue on Error
32988  *  0b0..From the start of the next frame after the FIFO error flag is cleared
32989  *  0b1..From the same word that caused the FIFO error to become 1 after the FIFO warning flag is cleared
32990  */
32991 #define I2S_RCR4_FCONT(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK)
32992 /*! @} */
32993 
32994 /*! @name RCR5 - Receive Configuration 5 */
32995 /*! @{ */
32996 
32997 #define I2S_RCR5_FBT_MASK                        (0x1F00U)
32998 #define I2S_RCR5_FBT_SHIFT                       (8U)
32999 /*! FBT - First Bit Shifted
33000  *  0b00000..0
33001  *  0b00001-0b11110..FBT value
33002  *  0b11111..31
33003  */
33004 #define I2S_RCR5_FBT(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK)
33005 
33006 #define I2S_RCR5_W0W_MASK                        (0x1F0000U)
33007 #define I2S_RCR5_W0W_SHIFT                       (16U)
33008 /*! W0W - Word 0 Width
33009  *  0b00000..1
33010  *  0b00001..2
33011  *  0b00010-0b11110..(W0W value + 1)
33012  *  0b11111..32
33013  */
33014 #define I2S_RCR5_W0W(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK)
33015 
33016 #define I2S_RCR5_WNW_MASK                        (0x1F000000U)
33017 #define I2S_RCR5_WNW_SHIFT                       (24U)
33018 /*! WNW - Word N Width
33019  *  0b00111..8
33020  *  0b01000..9
33021  *  0b01001-0b11110..(WNW value + 1)
33022  *  0b11111..32
33023  */
33024 #define I2S_RCR5_WNW(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK)
33025 /*! @} */
33026 
33027 /*! @name RDR - Receive Data */
33028 /*! @{ */
33029 
33030 #define I2S_RDR_RDR_MASK                         (0xFFFFFFFFU)
33031 #define I2S_RDR_RDR_SHIFT                        (0U)
33032 /*! RDR - Receive Data */
33033 #define I2S_RDR_RDR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK)
33034 /*! @} */
33035 
33036 /* The count of I2S_RDR */
33037 #define I2S_RDR_COUNT                            (2U)
33038 
33039 /*! @name RFR - Receive FIFO */
33040 /*! @{ */
33041 
33042 #define I2S_RFR_RFP_MASK                         (0xFU)
33043 #define I2S_RFR_RFP_SHIFT                        (0U)
33044 /*! RFP - Read FIFO Pointer */
33045 #define I2S_RFR_RFP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK)
33046 
33047 #define I2S_RFR_RCP_MASK                         (0x8000U)
33048 #define I2S_RFR_RCP_SHIFT                        (15U)
33049 /*! RCP - Read Channel Pointer
33050  *  0b0..No effect
33051  *  0b1..Next FIFO to be read
33052  */
33053 #define I2S_RFR_RCP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RCP_SHIFT)) & I2S_RFR_RCP_MASK)
33054 
33055 #define I2S_RFR_WFP_MASK                         (0xF0000U)
33056 #define I2S_RFR_WFP_SHIFT                        (16U)
33057 /*! WFP - Write FIFO Pointer */
33058 #define I2S_RFR_WFP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK)
33059 /*! @} */
33060 
33061 /* The count of I2S_RFR */
33062 #define I2S_RFR_COUNT                            (2U)
33063 
33064 /*! @name RMR - Receive Mask */
33065 /*! @{ */
33066 
33067 #define I2S_RMR_RWM_MASK                         (0xFFFFFFFFU)
33068 #define I2S_RMR_RWM_SHIFT                        (0U)
33069 /*! RWM - Receive Word Mask
33070  *  0b00000000000000000000000000000000..Enable
33071  *  0b00000000000000000000000000000001..Mask
33072  */
33073 #define I2S_RMR_RWM(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK)
33074 /*! @} */
33075 
33076 /*! @name MCR - MCLK Control */
33077 /*! @{ */
33078 
33079 #define I2S_MCR_DIV_MASK                         (0xFFU)
33080 #define I2S_MCR_DIV_SHIFT                        (0U)
33081 /*! DIV - MCLK Post Divide */
33082 #define I2S_MCR_DIV(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_MCR_DIV_SHIFT)) & I2S_MCR_DIV_MASK)
33083 
33084 #define I2S_MCR_DIVEN_MASK                       (0x800000U)
33085 #define I2S_MCR_DIVEN_SHIFT                      (23U)
33086 /*! DIVEN - MCLK Post Divide Enable
33087  *  0b0..Disable
33088  *  0b1..Enable
33089  */
33090 #define I2S_MCR_DIVEN(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_MCR_DIVEN_SHIFT)) & I2S_MCR_DIVEN_MASK)
33091 
33092 #define I2S_MCR_MSEL_MASK                        (0x3000000U)
33093 #define I2S_MCR_MSEL_SHIFT                       (24U)
33094 /*! MSEL - MCLK Select
33095  *  0b00..Controller clock (MCLK) option 1
33096  *  0b01..Reserved
33097  *  0b10..Controller clock (MCLK) option 2
33098  *  0b11..Controller clock (MCLK) option 3
33099  */
33100 #define I2S_MCR_MSEL(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MSEL_SHIFT)) & I2S_MCR_MSEL_MASK)
33101 
33102 #define I2S_MCR_MOE_MASK                         (0x40000000U)
33103 #define I2S_MCR_MOE_SHIFT                        (30U)
33104 /*! MOE - MCLK Output Enable
33105  *  0b0..Input
33106  *  0b1..Output
33107  */
33108 #define I2S_MCR_MOE(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MOE_SHIFT)) & I2S_MCR_MOE_MASK)
33109 /*! @} */
33110 
33111 
33112 /*!
33113  * @}
33114  */ /* end of group I2S_Register_Masks */
33115 
33116 
33117 /* I2S - Peripheral instance base addresses */
33118 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
33119   /** Peripheral SAI0 base address */
33120   #define SAI0_BASE                                (0x50106000u)
33121   /** Peripheral SAI0 base address */
33122   #define SAI0_BASE_NS                             (0x40106000u)
33123   /** Peripheral SAI0 base pointer */
33124   #define SAI0                                     ((I2S_Type *)SAI0_BASE)
33125   /** Peripheral SAI0 base pointer */
33126   #define SAI0_NS                                  ((I2S_Type *)SAI0_BASE_NS)
33127   /** Peripheral SAI1 base address */
33128   #define SAI1_BASE                                (0x50107000u)
33129   /** Peripheral SAI1 base address */
33130   #define SAI1_BASE_NS                             (0x40107000u)
33131   /** Peripheral SAI1 base pointer */
33132   #define SAI1                                     ((I2S_Type *)SAI1_BASE)
33133   /** Peripheral SAI1 base pointer */
33134   #define SAI1_NS                                  ((I2S_Type *)SAI1_BASE_NS)
33135   /** Array initializer of I2S peripheral base addresses */
33136   #define I2S_BASE_ADDRS                           { SAI0_BASE, SAI1_BASE }
33137   /** Array initializer of I2S peripheral base pointers */
33138   #define I2S_BASE_PTRS                            { SAI0, SAI1 }
33139   /** Array initializer of I2S peripheral base addresses */
33140   #define I2S_BASE_ADDRS_NS                        { SAI0_BASE_NS, SAI1_BASE_NS }
33141   /** Array initializer of I2S peripheral base pointers */
33142   #define I2S_BASE_PTRS_NS                         { SAI0_NS, SAI1_NS }
33143 #else
33144   /** Peripheral SAI0 base address */
33145   #define SAI0_BASE                                (0x40106000u)
33146   /** Peripheral SAI0 base pointer */
33147   #define SAI0                                     ((I2S_Type *)SAI0_BASE)
33148   /** Peripheral SAI1 base address */
33149   #define SAI1_BASE                                (0x40107000u)
33150   /** Peripheral SAI1 base pointer */
33151   #define SAI1                                     ((I2S_Type *)SAI1_BASE)
33152   /** Array initializer of I2S peripheral base addresses */
33153   #define I2S_BASE_ADDRS                           { SAI0_BASE, SAI1_BASE }
33154   /** Array initializer of I2S peripheral base pointers */
33155   #define I2S_BASE_PTRS                            { SAI0, SAI1 }
33156 #endif
33157 /** Interrupt vectors for the I2S peripheral type */
33158 #define I2S_RX_IRQS                              { SAI0_IRQn, SAI1_IRQn }
33159 #define I2S_TX_IRQS                              { SAI0_IRQn, SAI1_IRQn }
33160 
33161 /*!
33162  * @}
33163  */ /* end of group I2S_Peripheral_Access_Layer */
33164 
33165 
33166 /* ----------------------------------------------------------------------------
33167    -- I3C Peripheral Access Layer
33168    ---------------------------------------------------------------------------- */
33169 
33170 /*!
33171  * @addtogroup I3C_Peripheral_Access_Layer I3C Peripheral Access Layer
33172  * @{
33173  */
33174 
33175 /** I3C - Register Layout Typedef */
33176 typedef struct {
33177   __IO uint32_t MCONFIG;                           /**< Controller Configuration, offset: 0x0 */
33178   __IO uint32_t SCONFIG;                           /**< Target Configuration, offset: 0x4 */
33179   __IO uint32_t SSTATUS;                           /**< Target Status, offset: 0x8 */
33180   __IO uint32_t SCTRL;                             /**< Target Control, offset: 0xC */
33181   __IO uint32_t SINTSET;                           /**< Target Interrupt Set, offset: 0x10 */
33182   __IO uint32_t SINTCLR;                           /**< Target Interrupt Clear, offset: 0x14 */
33183   __I  uint32_t SINTMASKED;                        /**< Target Interrupt Mask, offset: 0x18 */
33184   __IO uint32_t SERRWARN;                          /**< Target Errors and Warnings, offset: 0x1C */
33185   __IO uint32_t SDMACTRL;                          /**< Target DMA Control, offset: 0x20 */
33186        uint8_t RESERVED_0[8];
33187   __IO uint32_t SDATACTRL;                         /**< Target Data Control, offset: 0x2C */
33188   __O  uint32_t SWDATAB;                           /**< Target Write Data Byte, offset: 0x30 */
33189   __O  uint32_t SWDATABE;                          /**< Target Write Data Byte End, offset: 0x34 */
33190   __O  uint32_t SWDATAH;                           /**< Target Write Data Halfword, offset: 0x38 */
33191   __O  uint32_t SWDATAHE;                          /**< Target Write Data Halfword End, offset: 0x3C */
33192   __I  uint32_t SRDATAB;                           /**< Target Read Data Byte, offset: 0x40 */
33193        uint8_t RESERVED_1[4];
33194   __I  uint32_t SRDATAH;                           /**< Target Read Data Halfword, offset: 0x48 */
33195        uint8_t RESERVED_2[8];
33196   __O  uint32_t SWDATAB1;                          /**< Target Write Data Byte, offset: 0x54 */
33197        uint8_t RESERVED_3[4];
33198   __I  uint32_t SCAPABILITIES2;                    /**< Target Capabilities 2, offset: 0x5C */
33199   __I  uint32_t SCAPABILITIES;                     /**< Target Capabilities, offset: 0x60 */
33200   __IO uint32_t SDYNADDR;                          /**< Target Dynamic Address, offset: 0x64 */
33201   __IO uint32_t SMAXLIMITS;                        /**< Target Maximum Limits, offset: 0x68 */
33202   __IO uint32_t SIDPARTNO;                         /**< Target ID Part Number, offset: 0x6C */
33203   __IO uint32_t SIDEXT;                            /**< Target ID Extension, offset: 0x70 */
33204   __IO uint32_t SVENDORID;                         /**< Target Vendor ID, offset: 0x74 */
33205   __IO uint32_t STCCLOCK;                          /**< Target Time Control Clock, offset: 0x78 */
33206   __I  uint32_t SMSGMAPADDR;                       /**< Target Message Map Address, offset: 0x7C */
33207        uint8_t RESERVED_4[4];
33208   __IO uint32_t MCTRL;                             /**< Controller Control, offset: 0x84 */
33209   __IO uint32_t MSTATUS;                           /**< Controller Status, offset: 0x88 */
33210   __IO uint32_t MIBIRULES;                         /**< Controller In-band Interrupt Registry and Rules, offset: 0x8C */
33211   __IO uint32_t MINTSET;                           /**< Controller Interrupt Set, offset: 0x90 */
33212   __IO uint32_t MINTCLR;                           /**< Controller Interrupt Clear, offset: 0x94 */
33213   __I  uint32_t MINTMASKED;                        /**< Controller Interrupt Mask, offset: 0x98 */
33214   __IO uint32_t MERRWARN;                          /**< Controller Errors and Warnings, offset: 0x9C */
33215   __IO uint32_t MDMACTRL;                          /**< Controller DMA Control, offset: 0xA0 */
33216        uint8_t RESERVED_5[8];
33217   __IO uint32_t MDATACTRL;                         /**< Controller Data Control, offset: 0xAC */
33218   __O  uint32_t MWDATAB;                           /**< Controller Write Data Byte, offset: 0xB0 */
33219   __O  uint32_t MWDATABE;                          /**< Controller Write Data Byte End, offset: 0xB4 */
33220   __O  uint32_t MWDATAH;                           /**< Controller Write Data Halfword, offset: 0xB8 */
33221   __O  uint32_t MWDATAHE;                          /**< Controller Write Data Halfword End, offset: 0xBC */
33222   __I  uint32_t MRDATAB;                           /**< Controller Read Data Byte, offset: 0xC0 */
33223        uint8_t RESERVED_6[4];
33224   __I  uint32_t MRDATAH;                           /**< Controller Read Data Halfword, offset: 0xC8 */
33225   __O  uint32_t MWDATAB1;                          /**< Controller Write Byte Data 1 (to Bus), offset: 0xCC */
33226   union {                                          /* offset: 0xD0 */
33227     __O  uint32_t MWMSG_SDR_CONTROL;                 /**< Controller Write Message Control in SDR mode, offset: 0xD0 */
33228     __O  uint32_t MWMSG_SDR_DATA;                    /**< Controller Write Message Data in SDR mode, offset: 0xD0 */
33229   };
33230   __I  uint32_t MRMSG_SDR;                         /**< Controller Read Message in SDR mode, offset: 0xD4 */
33231   union {                                          /* offset: 0xD8 */
33232     __O  uint32_t MWMSG_DDR_CONTROL;                 /**< Controller Write Message in DDR mode: First Control Word, offset: 0xD8 */
33233     __O  uint32_t MWMSG_DDR_CONTROL2;                /**< Controller Write Message in DDR Mode Control 2, offset: 0xD8 */
33234     __O  uint32_t MWMSG_DDR_DATA;                    /**< Controller Write Message Data in DDR mode, offset: 0xD8 */
33235   };
33236   __I  uint32_t MRMSG_DDR;                         /**< Controller Read Message in DDR mode, offset: 0xDC */
33237        uint8_t RESERVED_7[4];
33238   __IO uint32_t MDYNADDR;                          /**< Controller Dynamic Address, offset: 0xE4 */
33239        uint8_t RESERVED_8[52];
33240   __I  uint32_t SMAPCTRL0;                         /**< Map Feature Control 0, offset: 0x11C */
33241        uint8_t RESERVED_9[32];
33242   __IO uint32_t IBIEXT1;                           /**< Extended IBI Data 1, offset: 0x140 */
33243   __IO uint32_t IBIEXT2;                           /**< Extended IBI Data 2, offset: 0x144 */
33244        uint8_t RESERVED_10[3764];
33245   __I  uint32_t SID;                               /**< Target Module ID, offset: 0xFFC */
33246 } I3C_Type;
33247 
33248 /* ----------------------------------------------------------------------------
33249    -- I3C Register Masks
33250    ---------------------------------------------------------------------------- */
33251 
33252 /*!
33253  * @addtogroup I3C_Register_Masks I3C Register Masks
33254  * @{
33255  */
33256 
33257 /*! @name MCONFIG - Controller Configuration */
33258 /*! @{ */
33259 
33260 #define I3C_MCONFIG_MSTENA_MASK                  (0x3U)
33261 #define I3C_MCONFIG_MSTENA_SHIFT                 (0U)
33262 /*! MSTENA - Controller Enable
33263  *  0b00..CONTROLLER_OFF
33264  *  0b01..CONTROLLER_ON
33265  *  0b10..CONTROLLER_CAPABLE
33266  *  0b11..I2C_CONTROLLER_MODE
33267  */
33268 #define I3C_MCONFIG_MSTENA(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_MSTENA_SHIFT)) & I3C_MCONFIG_MSTENA_MASK)
33269 
33270 #define I3C_MCONFIG_DISTO_MASK                   (0x8U)
33271 #define I3C_MCONFIG_DISTO_SHIFT                  (3U)
33272 /*! DISTO - Disable Timeout
33273  *  0b1..Disabled, if configured
33274  *  0b0..Enabled
33275  */
33276 #define I3C_MCONFIG_DISTO(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_DISTO_SHIFT)) & I3C_MCONFIG_DISTO_MASK)
33277 
33278 #define I3C_MCONFIG_HKEEP_MASK                   (0x30U)
33279 #define I3C_MCONFIG_HKEEP_SHIFT                  (4U)
33280 /*! HKEEP - High-Keeper
33281  *  0b00..None
33282  *  0b01..WIRED_IN
33283  *  0b10..PASSIVE_SDA
33284  *  0b11..PASSIVE_ON_SDA_SCL
33285  */
33286 #define I3C_MCONFIG_HKEEP(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_HKEEP_SHIFT)) & I3C_MCONFIG_HKEEP_MASK)
33287 
33288 #define I3C_MCONFIG_ODSTOP_MASK                  (0x40U)
33289 #define I3C_MCONFIG_ODSTOP_SHIFT                 (6U)
33290 /*! ODSTOP - Open Drain Stop
33291  *  0b1..Enable
33292  *  0b0..Disable
33293  */
33294 #define I3C_MCONFIG_ODSTOP(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODSTOP_SHIFT)) & I3C_MCONFIG_ODSTOP_MASK)
33295 
33296 #define I3C_MCONFIG_PPBAUD_MASK                  (0xF00U)
33297 #define I3C_MCONFIG_PPBAUD_SHIFT                 (8U)
33298 /*! PPBAUD - Push-Pull Baud Rate */
33299 #define I3C_MCONFIG_PPBAUD(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_PPBAUD_SHIFT)) & I3C_MCONFIG_PPBAUD_MASK)
33300 
33301 #define I3C_MCONFIG_PPLOW_MASK                   (0xF000U)
33302 #define I3C_MCONFIG_PPLOW_SHIFT                  (12U)
33303 /*! PPLOW - Push-Pull Low */
33304 #define I3C_MCONFIG_PPLOW(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_PPLOW_SHIFT)) & I3C_MCONFIG_PPLOW_MASK)
33305 
33306 #define I3C_MCONFIG_ODBAUD_MASK                  (0xFF0000U)
33307 #define I3C_MCONFIG_ODBAUD_SHIFT                 (16U)
33308 /*! ODBAUD - Open Drain Baud Rate */
33309 #define I3C_MCONFIG_ODBAUD(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODBAUD_SHIFT)) & I3C_MCONFIG_ODBAUD_MASK)
33310 
33311 #define I3C_MCONFIG_ODHPP_MASK                   (0x1000000U)
33312 #define I3C_MCONFIG_ODHPP_SHIFT                  (24U)
33313 /*! ODHPP - Open Drain High Push-Pull
33314  *  0b1..Enable
33315  *  0b0..Disable
33316  */
33317 #define I3C_MCONFIG_ODHPP(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODHPP_SHIFT)) & I3C_MCONFIG_ODHPP_MASK)
33318 
33319 #define I3C_MCONFIG_SKEW_MASK                    (0xE000000U)
33320 #define I3C_MCONFIG_SKEW_SHIFT                   (25U)
33321 /*! SKEW - Skew */
33322 #define I3C_MCONFIG_SKEW(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_SKEW_SHIFT)) & I3C_MCONFIG_SKEW_MASK)
33323 
33324 #define I3C_MCONFIG_I2CBAUD_MASK                 (0xF0000000U)
33325 #define I3C_MCONFIG_I2CBAUD_SHIFT                (28U)
33326 /*! I2CBAUD - I2C Baud Rate */
33327 #define I3C_MCONFIG_I2CBAUD(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_I2CBAUD_SHIFT)) & I3C_MCONFIG_I2CBAUD_MASK)
33328 /*! @} */
33329 
33330 /*! @name SCONFIG - Target Configuration */
33331 /*! @{ */
33332 
33333 #define I3C_SCONFIG_SLVENA_MASK                  (0x1U)
33334 #define I3C_SCONFIG_SLVENA_SHIFT                 (0U)
33335 /*! SLVENA - Target Enable
33336  *  0b1..Enable
33337  *  0b0..Disable
33338  */
33339 #define I3C_SCONFIG_SLVENA(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_SLVENA_SHIFT)) & I3C_SCONFIG_SLVENA_MASK)
33340 
33341 #define I3C_SCONFIG_NACK_MASK                    (0x2U)
33342 #define I3C_SCONFIG_NACK_SHIFT                   (1U)
33343 /*! NACK - Not Acknowledge
33344  *  0b1..Always enable NACK mode (works normally)
33345  *  0b0..Always disable NACK mode
33346  */
33347 #define I3C_SCONFIG_NACK(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_NACK_SHIFT)) & I3C_SCONFIG_NACK_MASK)
33348 
33349 #define I3C_SCONFIG_MATCHSS_MASK                 (0x4U)
33350 #define I3C_SCONFIG_MATCHSS_SHIFT                (2U)
33351 /*! MATCHSS - Match Start or Stop
33352  *  0b1..Enable
33353  *  0b0..Disable
33354  */
33355 #define I3C_SCONFIG_MATCHSS(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_MATCHSS_SHIFT)) & I3C_SCONFIG_MATCHSS_MASK)
33356 
33357 #define I3C_SCONFIG_S0IGNORE_MASK                (0x8U)
33358 #define I3C_SCONFIG_S0IGNORE_SHIFT               (3U)
33359 /*! S0IGNORE - Ignore TE0 or TE1 Errors
33360  *  0b1..Ignore TE0 or TE1 errors
33361  *  0b0..Do not ignore TE0 or TE1 errors
33362  */
33363 #define I3C_SCONFIG_S0IGNORE(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_S0IGNORE_SHIFT)) & I3C_SCONFIG_S0IGNORE_MASK)
33364 
33365 #define I3C_SCONFIG_DDROK_MASK                   (0x10U)
33366 #define I3C_SCONFIG_DDROK_SHIFT                  (4U)
33367 /*! DDROK - Double Data Rate OK
33368  *  0b1..Allow HDR-DDR messaging
33369  *  0b0..Do not allow HDR-DDR messaging
33370  */
33371 #define I3C_SCONFIG_DDROK(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_DDROK_SHIFT)) & I3C_SCONFIG_DDROK_MASK)
33372 
33373 #define I3C_SCONFIG_IDRAND_MASK                  (0x100U)
33374 #define I3C_SCONFIG_IDRAND_SHIFT                 (8U)
33375 /*! IDRAND - ID random
33376  *  0b1..Random value
33377  *  0b0..Part number and an instance
33378  */
33379 #define I3C_SCONFIG_IDRAND(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_IDRAND_SHIFT)) & I3C_SCONFIG_IDRAND_MASK)
33380 
33381 #define I3C_SCONFIG_OFFLINE_MASK                 (0x200U)
33382 #define I3C_SCONFIG_OFFLINE_SHIFT                (9U)
33383 /*! OFFLINE - Offline
33384  *  0b1..Enable
33385  *  0b0..Disable
33386  */
33387 #define I3C_SCONFIG_OFFLINE(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_OFFLINE_SHIFT)) & I3C_SCONFIG_OFFLINE_MASK)
33388 
33389 #define I3C_SCONFIG_BAMATCH_MASK                 (0xFF0000U)
33390 #define I3C_SCONFIG_BAMATCH_SHIFT                (16U)
33391 /*! BAMATCH - Bus Available Match */
33392 #define I3C_SCONFIG_BAMATCH(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_BAMATCH_SHIFT)) & I3C_SCONFIG_BAMATCH_MASK)
33393 
33394 #define I3C_SCONFIG_SADDR_MASK                   (0xFE000000U)
33395 #define I3C_SCONFIG_SADDR_SHIFT                  (25U)
33396 /*! SADDR - Static Address */
33397 #define I3C_SCONFIG_SADDR(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_SADDR_SHIFT)) & I3C_SCONFIG_SADDR_MASK)
33398 /*! @} */
33399 
33400 /*! @name SSTATUS - Target Status */
33401 /*! @{ */
33402 
33403 #define I3C_SSTATUS_STNOTSTOP_MASK               (0x1U)
33404 #define I3C_SSTATUS_STNOTSTOP_SHIFT              (0U)
33405 /*! STNOTSTOP - Status not Stop
33406  *  0b1..Busy
33407  *  0b0..In STOP condition
33408  */
33409 #define I3C_SSTATUS_STNOTSTOP(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STNOTSTOP_SHIFT)) & I3C_SSTATUS_STNOTSTOP_MASK)
33410 
33411 #define I3C_SSTATUS_STMSG_MASK                   (0x2U)
33412 #define I3C_SSTATUS_STMSG_SHIFT                  (1U)
33413 /*! STMSG - Status Message
33414  *  0b1..Busy
33415  *  0b0..Idle
33416  */
33417 #define I3C_SSTATUS_STMSG(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STMSG_SHIFT)) & I3C_SSTATUS_STMSG_MASK)
33418 
33419 #define I3C_SSTATUS_STCCCH_MASK                  (0x4U)
33420 #define I3C_SSTATUS_STCCCH_SHIFT                 (2U)
33421 /*! STCCCH - Status Common Command Code Handler
33422  *  0b1..Handled automatically
33423  *  0b0..No CCC message handled
33424  */
33425 #define I3C_SSTATUS_STCCCH(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STCCCH_SHIFT)) & I3C_SSTATUS_STCCCH_MASK)
33426 
33427 #define I3C_SSTATUS_STREQRD_MASK                 (0x8U)
33428 #define I3C_SSTATUS_STREQRD_SHIFT                (3U)
33429 /*! STREQRD - Status Request Read
33430  *  0b1..SDR read from this target or an IBI is being pushed out
33431  *  0b0..Not an SDR read
33432  */
33433 #define I3C_SSTATUS_STREQRD(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STREQRD_SHIFT)) & I3C_SSTATUS_STREQRD_MASK)
33434 
33435 #define I3C_SSTATUS_STREQWR_MASK                 (0x10U)
33436 #define I3C_SSTATUS_STREQWR_SHIFT                (4U)
33437 /*! STREQWR - Status Request Write
33438  *  0b1..SDR write data from the controller, but not in ENTDAA mode
33439  *  0b0..Not an SDR write
33440  */
33441 #define I3C_SSTATUS_STREQWR(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STREQWR_SHIFT)) & I3C_SSTATUS_STREQWR_MASK)
33442 
33443 #define I3C_SSTATUS_STDAA_MASK                   (0x20U)
33444 #define I3C_SSTATUS_STDAA_SHIFT                  (5U)
33445 /*! STDAA - Status Dynamic Address Assignment
33446  *  0b1..In ENTDAA mode
33447  *  0b0..Not in ENTDAA mode
33448  */
33449 #define I3C_SSTATUS_STDAA(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STDAA_SHIFT)) & I3C_SSTATUS_STDAA_MASK)
33450 
33451 #define I3C_SSTATUS_STHDR_MASK                   (0x40U)
33452 #define I3C_SSTATUS_STHDR_SHIFT                  (6U)
33453 /*! STHDR - Status High Data Rate
33454  *  0b1..I3C bus in HDR-DDR mode
33455  *  0b0..I3C bus not in HDR-DDR mode
33456  */
33457 #define I3C_SSTATUS_STHDR(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STHDR_SHIFT)) & I3C_SSTATUS_STHDR_MASK)
33458 
33459 #define I3C_SSTATUS_START_MASK                   (0x100U)
33460 #define I3C_SSTATUS_START_SHIFT                  (8U)
33461 /*! START - Start
33462  *  0b1..Detected
33463  *  0b0..Not detected
33464  *  0b0..No effect
33465  *  0b1..Clear the flag
33466  */
33467 #define I3C_SSTATUS_START(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_START_SHIFT)) & I3C_SSTATUS_START_MASK)
33468 
33469 #define I3C_SSTATUS_MATCHED_MASK                 (0x200U)
33470 #define I3C_SSTATUS_MATCHED_SHIFT                (9U)
33471 /*! MATCHED - Matched
33472  *  0b1..Header matched
33473  *  0b0..Header not matched
33474  *  0b0..No effect
33475  *  0b1..Clear the flag
33476  */
33477 #define I3C_SSTATUS_MATCHED(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_MATCHED_SHIFT)) & I3C_SSTATUS_MATCHED_MASK)
33478 
33479 #define I3C_SSTATUS_STOP_MASK                    (0x400U)
33480 #define I3C_SSTATUS_STOP_SHIFT                   (10U)
33481 /*! STOP - Stop
33482  *  0b1..Stopped state detected
33483  *  0b0..No Stopped state detected
33484  *  0b0..No effect
33485  *  0b1..Clear the flag
33486  */
33487 #define I3C_SSTATUS_STOP(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STOP_SHIFT)) & I3C_SSTATUS_STOP_MASK)
33488 
33489 #define I3C_SSTATUS_RX_PEND_MASK                 (0x800U)
33490 #define I3C_SSTATUS_RX_PEND_SHIFT                (11U)
33491 /*! RX_PEND - Received Message Pending
33492  *  0b1..Received message pending
33493  *  0b0..No received message pending
33494  */
33495 #define I3C_SSTATUS_RX_PEND(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_RX_PEND_SHIFT)) & I3C_SSTATUS_RX_PEND_MASK)
33496 
33497 #define I3C_SSTATUS_TXNOTFULL_MASK               (0x1000U)
33498 #define I3C_SSTATUS_TXNOTFULL_SHIFT              (12U)
33499 /*! TXNOTFULL - Transmit Buffer Not Full
33500  *  0b1..Transmit buffer not full
33501  *  0b0..Transmit buffer full
33502  */
33503 #define I3C_SSTATUS_TXNOTFULL(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_TXNOTFULL_SHIFT)) & I3C_SSTATUS_TXNOTFULL_MASK)
33504 
33505 #define I3C_SSTATUS_DACHG_MASK                   (0x2000U)
33506 #define I3C_SSTATUS_DACHG_SHIFT                  (13U)
33507 /*! DACHG - Dynamic Address Change
33508  *  0b1..DA change detected
33509  *  0b0..No DA change detected
33510  *  0b0..No effect
33511  *  0b1..Clear the flag
33512  */
33513 #define I3C_SSTATUS_DACHG(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_DACHG_SHIFT)) & I3C_SSTATUS_DACHG_MASK)
33514 
33515 #define I3C_SSTATUS_CCC_MASK                     (0x4000U)
33516 #define I3C_SSTATUS_CCC_SHIFT                    (14U)
33517 /*! CCC - Common Command Code
33518  *  0b1..CCC received
33519  *  0b0..CCC not received
33520  *  0b0..No effect
33521  *  0b1..Clear the flag
33522  */
33523 #define I3C_SSTATUS_CCC(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_CCC_SHIFT)) & I3C_SSTATUS_CCC_MASK)
33524 
33525 #define I3C_SSTATUS_ERRWARN_MASK                 (0x8000U)
33526 #define I3C_SSTATUS_ERRWARN_SHIFT                (15U)
33527 /*! ERRWARN - Error Warning */
33528 #define I3C_SSTATUS_ERRWARN(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_ERRWARN_SHIFT)) & I3C_SSTATUS_ERRWARN_MASK)
33529 
33530 #define I3C_SSTATUS_HDRMATCH_MASK                (0x10000U)
33531 #define I3C_SSTATUS_HDRMATCH_SHIFT               (16U)
33532 /*! HDRMATCH - High Data Rate Command Match
33533  *  0b1..Matched the I3C dynamic address
33534  *  0b0..Did not match
33535  *  0b0..No effect
33536  *  0b1..Clear the flag
33537  */
33538 #define I3C_SSTATUS_HDRMATCH(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_HDRMATCH_SHIFT)) & I3C_SSTATUS_HDRMATCH_MASK)
33539 
33540 #define I3C_SSTATUS_CHANDLED_MASK                (0x20000U)
33541 #define I3C_SSTATUS_CHANDLED_SHIFT               (17U)
33542 /*! CHANDLED - Common Command Code Handled
33543  *  0b1..CCC handling in progress
33544  *  0b0..CCC handling not in progress
33545  *  0b0..No effect
33546  *  0b1..Clear the flag
33547  */
33548 #define I3C_SSTATUS_CHANDLED(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_CHANDLED_SHIFT)) & I3C_SSTATUS_CHANDLED_MASK)
33549 
33550 #define I3C_SSTATUS_EVENT_MASK                   (0x40000U)
33551 #define I3C_SSTATUS_EVENT_SHIFT                  (18U)
33552 /*! EVENT - Event
33553  *  0b1..IBI, CR, or HJ occurred
33554  *  0b0..No event occurred
33555  *  0b0..No effect
33556  *  0b1..Clear the flag
33557  */
33558 #define I3C_SSTATUS_EVENT(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_EVENT_SHIFT)) & I3C_SSTATUS_EVENT_MASK)
33559 
33560 #define I3C_SSTATUS_EVDET_MASK                   (0x300000U)
33561 #define I3C_SSTATUS_EVDET_SHIFT                  (20U)
33562 /*! EVDET - Event Details
33563  *  0b00..NONE (no event or no pending event)
33564  *  0b01..NO_REQUEST (request is not sent yet; either there is no START condition yet, or is waiting for Bus-Available or Bus-Idle (HJ))
33565  *  0b10..NACKed (not acknowledged, request sent and rejected); I3C tries again
33566  *  0b11..ACKed (acknowledged; request sent and accepted), so done (unless the time control data is still being sent)
33567  */
33568 #define I3C_SSTATUS_EVDET(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_EVDET_SHIFT)) & I3C_SSTATUS_EVDET_MASK)
33569 
33570 #define I3C_SSTATUS_IBIDIS_MASK                  (0x1000000U)
33571 #define I3C_SSTATUS_IBIDIS_SHIFT                 (24U)
33572 /*! IBIDIS - In-Band Interrupts Disable
33573  *  0b1..Disabled
33574  *  0b0..Enabled
33575  */
33576 #define I3C_SSTATUS_IBIDIS(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_IBIDIS_SHIFT)) & I3C_SSTATUS_IBIDIS_MASK)
33577 
33578 #define I3C_SSTATUS_MRDIS_MASK                   (0x2000000U)
33579 #define I3C_SSTATUS_MRDIS_SHIFT                  (25U)
33580 /*! MRDIS - Controller Requests Disable
33581  *  0b1..Disabled
33582  *  0b0..Enabled
33583  */
33584 #define I3C_SSTATUS_MRDIS(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_MRDIS_SHIFT)) & I3C_SSTATUS_MRDIS_MASK)
33585 
33586 #define I3C_SSTATUS_HJDIS_MASK                   (0x8000000U)
33587 #define I3C_SSTATUS_HJDIS_SHIFT                  (27U)
33588 /*! HJDIS - Hot-Join Disabled
33589  *  0b1..Disabled
33590  *  0b0..Enabled
33591  */
33592 #define I3C_SSTATUS_HJDIS(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_HJDIS_SHIFT)) & I3C_SSTATUS_HJDIS_MASK)
33593 
33594 #define I3C_SSTATUS_ACTSTATE_MASK                (0x30000000U)
33595 #define I3C_SSTATUS_ACTSTATE_SHIFT               (28U)
33596 /*! ACTSTATE - Activity State from Common Command Codes (CCC)
33597  *  0b00..NO_LATENCY (normal bus operations)
33598  *  0b01..LATENCY_1MS (1 ms of latency)
33599  *  0b10..LATENCY_100MS (100 ms of latency)
33600  *  0b11..LATENCY_10S (10 seconds of latency)
33601  */
33602 #define I3C_SSTATUS_ACTSTATE(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_ACTSTATE_SHIFT)) & I3C_SSTATUS_ACTSTATE_MASK)
33603 
33604 #define I3C_SSTATUS_TIMECTRL_MASK                (0xC0000000U)
33605 #define I3C_SSTATUS_TIMECTRL_SHIFT               (30U)
33606 /*! TIMECTRL - Time Control
33607  *  0b00..NO_TIME_CONTROL (no time control is enabled)
33608  *  0b01..SYNC_MODE (Synchronous mode is enabled)
33609  *  0b10..ASYNC_MODE (Asynchronous standard mode (0 or 1) is enabled)
33610  *  0b11..BOTHSYNCASYNC (both Synchronous and Asynchronous modes are enabled)
33611  */
33612 #define I3C_SSTATUS_TIMECTRL(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_TIMECTRL_SHIFT)) & I3C_SSTATUS_TIMECTRL_MASK)
33613 /*! @} */
33614 
33615 /*! @name SCTRL - Target Control */
33616 /*! @{ */
33617 
33618 #define I3C_SCTRL_EVENT_MASK                     (0x3U)
33619 #define I3C_SCTRL_EVENT_SHIFT                    (0U)
33620 /*! EVENT - Event
33621  *  0b00..NORMAL_MODE
33622  *  0b01..IBI
33623  *  0b10..CONTROLLER_REQUEST
33624  *  0b11..HOT_JOIN_REQUEST
33625  */
33626 #define I3C_SCTRL_EVENT(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_EVENT_SHIFT)) & I3C_SCTRL_EVENT_MASK)
33627 
33628 #define I3C_SCTRL_EXTDATA_MASK                   (0x8U)
33629 #define I3C_SCTRL_EXTDATA_SHIFT                  (3U)
33630 /*! EXTDATA - Extended Data
33631  *  0b1..Enable
33632  *  0b0..Disable
33633  */
33634 #define I3C_SCTRL_EXTDATA(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_EXTDATA_SHIFT)) & I3C_SCTRL_EXTDATA_MASK)
33635 
33636 #define I3C_SCTRL_IBIDATA_MASK                   (0xFF00U)
33637 #define I3C_SCTRL_IBIDATA_SHIFT                  (8U)
33638 /*! IBIDATA - In-Band Interrupt Data */
33639 #define I3C_SCTRL_IBIDATA(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_IBIDATA_SHIFT)) & I3C_SCTRL_IBIDATA_MASK)
33640 
33641 #define I3C_SCTRL_PENDINT_MASK                   (0xF0000U)
33642 #define I3C_SCTRL_PENDINT_SHIFT                  (16U)
33643 /*! PENDINT - Pending Interrupt */
33644 #define I3C_SCTRL_PENDINT(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_PENDINT_SHIFT)) & I3C_SCTRL_PENDINT_MASK)
33645 
33646 #define I3C_SCTRL_ACTSTATE_MASK                  (0x300000U)
33647 #define I3C_SCTRL_ACTSTATE_SHIFT                 (20U)
33648 /*! ACTSTATE - Activity State of Target */
33649 #define I3C_SCTRL_ACTSTATE(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_ACTSTATE_SHIFT)) & I3C_SCTRL_ACTSTATE_MASK)
33650 
33651 #define I3C_SCTRL_VENDINFO_MASK                  (0xFF000000U)
33652 #define I3C_SCTRL_VENDINFO_SHIFT                 (24U)
33653 /*! VENDINFO - Vendor Information */
33654 #define I3C_SCTRL_VENDINFO(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_VENDINFO_SHIFT)) & I3C_SCTRL_VENDINFO_MASK)
33655 /*! @} */
33656 
33657 /*! @name SINTSET - Target Interrupt Set */
33658 /*! @{ */
33659 
33660 #define I3C_SINTSET_START_MASK                   (0x100U)
33661 #define I3C_SINTSET_START_SHIFT                  (8U)
33662 /*! START - Start Interrupt Enable
33663  *  0b1..Enable
33664  *  0b0..Disable
33665  */
33666 #define I3C_SINTSET_START(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_START_SHIFT)) & I3C_SINTSET_START_MASK)
33667 
33668 #define I3C_SINTSET_MATCHED_MASK                 (0x200U)
33669 #define I3C_SINTSET_MATCHED_SHIFT                (9U)
33670 /*! MATCHED - Match Interrupt Enable
33671  *  0b1..Enable
33672  *  0b0..Disable
33673  */
33674 #define I3C_SINTSET_MATCHED(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_MATCHED_SHIFT)) & I3C_SINTSET_MATCHED_MASK)
33675 
33676 #define I3C_SINTSET_STOP_MASK                    (0x400U)
33677 #define I3C_SINTSET_STOP_SHIFT                   (10U)
33678 /*! STOP - Stop Interrupt Enable
33679  *  0b1..Enable
33680  *  0b0..Disable
33681  */
33682 #define I3C_SINTSET_STOP(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_STOP_SHIFT)) & I3C_SINTSET_STOP_MASK)
33683 
33684 #define I3C_SINTSET_RXPEND_MASK                  (0x800U)
33685 #define I3C_SINTSET_RXPEND_SHIFT                 (11U)
33686 /*! RXPEND - Receive Interrupt Enable
33687  *  0b1..Enable
33688  *  0b0..Disable
33689  */
33690 #define I3C_SINTSET_RXPEND(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_RXPEND_SHIFT)) & I3C_SINTSET_RXPEND_MASK)
33691 
33692 #define I3C_SINTSET_TXSEND_MASK                  (0x1000U)
33693 #define I3C_SINTSET_TXSEND_SHIFT                 (12U)
33694 /*! TXSEND - Transmit Interrupt Enable
33695  *  0b1..Enable
33696  *  0b0..Disable
33697  */
33698 #define I3C_SINTSET_TXSEND(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_TXSEND_SHIFT)) & I3C_SINTSET_TXSEND_MASK)
33699 
33700 #define I3C_SINTSET_DACHG_MASK                   (0x2000U)
33701 #define I3C_SINTSET_DACHG_SHIFT                  (13U)
33702 /*! DACHG - Dynamic Address Change Interrupt Enable
33703  *  0b1..Enable
33704  *  0b0..Disable
33705  */
33706 #define I3C_SINTSET_DACHG(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_DACHG_SHIFT)) & I3C_SINTSET_DACHG_MASK)
33707 
33708 #define I3C_SINTSET_CCC_MASK                     (0x4000U)
33709 #define I3C_SINTSET_CCC_SHIFT                    (14U)
33710 /*! CCC - Common Command Code (CCC) Interrupt Enable
33711  *  0b1..Enable
33712  *  0b0..Disable
33713  */
33714 #define I3C_SINTSET_CCC(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_CCC_SHIFT)) & I3C_SINTSET_CCC_MASK)
33715 
33716 #define I3C_SINTSET_ERRWARN_MASK                 (0x8000U)
33717 #define I3C_SINTSET_ERRWARN_SHIFT                (15U)
33718 /*! ERRWARN - Error or Warning Interrupt Enable
33719  *  0b1..Enable
33720  *  0b0..Disable
33721  */
33722 #define I3C_SINTSET_ERRWARN(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_ERRWARN_SHIFT)) & I3C_SINTSET_ERRWARN_MASK)
33723 
33724 #define I3C_SINTSET_DDRMATCHED_MASK              (0x10000U)
33725 #define I3C_SINTSET_DDRMATCHED_SHIFT             (16U)
33726 /*! DDRMATCHED - Double Data Rate Interrupt Enable
33727  *  0b1..Enable
33728  *  0b0..Disable
33729  */
33730 #define I3C_SINTSET_DDRMATCHED(x)                (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_DDRMATCHED_SHIFT)) & I3C_SINTSET_DDRMATCHED_MASK)
33731 
33732 #define I3C_SINTSET_CHANDLED_MASK                (0x20000U)
33733 #define I3C_SINTSET_CHANDLED_SHIFT               (17U)
33734 /*! CHANDLED - Common Command Code (CCC) Interrupt Enable
33735  *  0b1..Enable
33736  *  0b0..Disable
33737  */
33738 #define I3C_SINTSET_CHANDLED(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_CHANDLED_SHIFT)) & I3C_SINTSET_CHANDLED_MASK)
33739 
33740 #define I3C_SINTSET_EVENT_MASK                   (0x40000U)
33741 #define I3C_SINTSET_EVENT_SHIFT                  (18U)
33742 /*! EVENT - Event Interrupt Enable
33743  *  0b1..Enable
33744  *  0b0..Disable
33745  */
33746 #define I3C_SINTSET_EVENT(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_EVENT_SHIFT)) & I3C_SINTSET_EVENT_MASK)
33747 /*! @} */
33748 
33749 /*! @name SINTCLR - Target Interrupt Clear */
33750 /*! @{ */
33751 
33752 #define I3C_SINTCLR_START_MASK                   (0x100U)
33753 #define I3C_SINTCLR_START_SHIFT                  (8U)
33754 /*! START - START Interrupt Enable Clear */
33755 #define I3C_SINTCLR_START(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_START_SHIFT)) & I3C_SINTCLR_START_MASK)
33756 
33757 #define I3C_SINTCLR_MATCHED_MASK                 (0x200U)
33758 #define I3C_SINTCLR_MATCHED_SHIFT                (9U)
33759 /*! MATCHED - Matched Interrupt Enable Clear */
33760 #define I3C_SINTCLR_MATCHED(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_MATCHED_SHIFT)) & I3C_SINTCLR_MATCHED_MASK)
33761 
33762 #define I3C_SINTCLR_STOP_MASK                    (0x400U)
33763 #define I3C_SINTCLR_STOP_SHIFT                   (10U)
33764 /*! STOP - STOP Interrupt Enable Clear */
33765 #define I3C_SINTCLR_STOP(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_STOP_SHIFT)) & I3C_SINTCLR_STOP_MASK)
33766 
33767 #define I3C_SINTCLR_RXPEND_MASK                  (0x800U)
33768 #define I3C_SINTCLR_RXPEND_SHIFT                 (11U)
33769 /*! RXPEND - RXPEND Interrupt Enable Clear */
33770 #define I3C_SINTCLR_RXPEND(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_RXPEND_SHIFT)) & I3C_SINTCLR_RXPEND_MASK)
33771 
33772 #define I3C_SINTCLR_TXSEND_MASK                  (0x1000U)
33773 #define I3C_SINTCLR_TXSEND_SHIFT                 (12U)
33774 /*! TXSEND - TXSEND Interrupt Enable Clear */
33775 #define I3C_SINTCLR_TXSEND(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_TXSEND_SHIFT)) & I3C_SINTCLR_TXSEND_MASK)
33776 
33777 #define I3C_SINTCLR_DACHG_MASK                   (0x2000U)
33778 #define I3C_SINTCLR_DACHG_SHIFT                  (13U)
33779 /*! DACHG - DACHG Interrupt Enable Clear */
33780 #define I3C_SINTCLR_DACHG(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_DACHG_SHIFT)) & I3C_SINTCLR_DACHG_MASK)
33781 
33782 #define I3C_SINTCLR_CCC_MASK                     (0x4000U)
33783 #define I3C_SINTCLR_CCC_SHIFT                    (14U)
33784 /*! CCC - CCC Interrupt Enable Clear */
33785 #define I3C_SINTCLR_CCC(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_CCC_SHIFT)) & I3C_SINTCLR_CCC_MASK)
33786 
33787 #define I3C_SINTCLR_ERRWARN_MASK                 (0x8000U)
33788 #define I3C_SINTCLR_ERRWARN_SHIFT                (15U)
33789 /*! ERRWARN - ERRWARN Interrupt Enable Clear */
33790 #define I3C_SINTCLR_ERRWARN(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_ERRWARN_SHIFT)) & I3C_SINTCLR_ERRWARN_MASK)
33791 
33792 #define I3C_SINTCLR_DDRMATCHED_MASK              (0x10000U)
33793 #define I3C_SINTCLR_DDRMATCHED_SHIFT             (16U)
33794 /*! DDRMATCHED - DDRMATCHED Interrupt Enable Clear */
33795 #define I3C_SINTCLR_DDRMATCHED(x)                (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_DDRMATCHED_SHIFT)) & I3C_SINTCLR_DDRMATCHED_MASK)
33796 
33797 #define I3C_SINTCLR_CHANDLED_MASK                (0x20000U)
33798 #define I3C_SINTCLR_CHANDLED_SHIFT               (17U)
33799 /*! CHANDLED - CHANDLED Interrupt Enable Clear */
33800 #define I3C_SINTCLR_CHANDLED(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_CHANDLED_SHIFT)) & I3C_SINTCLR_CHANDLED_MASK)
33801 
33802 #define I3C_SINTCLR_EVENT_MASK                   (0x40000U)
33803 #define I3C_SINTCLR_EVENT_SHIFT                  (18U)
33804 /*! EVENT - EVENT Interrupt Enable Clear */
33805 #define I3C_SINTCLR_EVENT(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_EVENT_SHIFT)) & I3C_SINTCLR_EVENT_MASK)
33806 /*! @} */
33807 
33808 /*! @name SINTMASKED - Target Interrupt Mask */
33809 /*! @{ */
33810 
33811 #define I3C_SINTMASKED_START_MASK                (0x100U)
33812 #define I3C_SINTMASKED_START_SHIFT               (8U)
33813 /*! START - START Interrupt Mask */
33814 #define I3C_SINTMASKED_START(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_START_SHIFT)) & I3C_SINTMASKED_START_MASK)
33815 
33816 #define I3C_SINTMASKED_MATCHED_MASK              (0x200U)
33817 #define I3C_SINTMASKED_MATCHED_SHIFT             (9U)
33818 /*! MATCHED - MATCHED Interrupt Mask */
33819 #define I3C_SINTMASKED_MATCHED(x)                (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_MATCHED_SHIFT)) & I3C_SINTMASKED_MATCHED_MASK)
33820 
33821 #define I3C_SINTMASKED_STOP_MASK                 (0x400U)
33822 #define I3C_SINTMASKED_STOP_SHIFT                (10U)
33823 /*! STOP - STOP Interrupt Mask */
33824 #define I3C_SINTMASKED_STOP(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_STOP_SHIFT)) & I3C_SINTMASKED_STOP_MASK)
33825 
33826 #define I3C_SINTMASKED_RXPEND_MASK               (0x800U)
33827 #define I3C_SINTMASKED_RXPEND_SHIFT              (11U)
33828 /*! RXPEND - RXPEND Interrupt Mask */
33829 #define I3C_SINTMASKED_RXPEND(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_RXPEND_SHIFT)) & I3C_SINTMASKED_RXPEND_MASK)
33830 
33831 #define I3C_SINTMASKED_TXSEND_MASK               (0x1000U)
33832 #define I3C_SINTMASKED_TXSEND_SHIFT              (12U)
33833 /*! TXSEND - TXSEND Interrupt Mask */
33834 #define I3C_SINTMASKED_TXSEND(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_TXSEND_SHIFT)) & I3C_SINTMASKED_TXSEND_MASK)
33835 
33836 #define I3C_SINTMASKED_DACHG_MASK                (0x2000U)
33837 #define I3C_SINTMASKED_DACHG_SHIFT               (13U)
33838 /*! DACHG - DACHG Interrupt Mask */
33839 #define I3C_SINTMASKED_DACHG(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_DACHG_SHIFT)) & I3C_SINTMASKED_DACHG_MASK)
33840 
33841 #define I3C_SINTMASKED_CCC_MASK                  (0x4000U)
33842 #define I3C_SINTMASKED_CCC_SHIFT                 (14U)
33843 /*! CCC - CCC Interrupt Mask */
33844 #define I3C_SINTMASKED_CCC(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_CCC_SHIFT)) & I3C_SINTMASKED_CCC_MASK)
33845 
33846 #define I3C_SINTMASKED_ERRWARN_MASK              (0x8000U)
33847 #define I3C_SINTMASKED_ERRWARN_SHIFT             (15U)
33848 /*! ERRWARN - ERRWARN Interrupt Mask */
33849 #define I3C_SINTMASKED_ERRWARN(x)                (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_ERRWARN_SHIFT)) & I3C_SINTMASKED_ERRWARN_MASK)
33850 
33851 #define I3C_SINTMASKED_DDRMATCHED_MASK           (0x10000U)
33852 #define I3C_SINTMASKED_DDRMATCHED_SHIFT          (16U)
33853 /*! DDRMATCHED - DDRMATCHED Interrupt Mask */
33854 #define I3C_SINTMASKED_DDRMATCHED(x)             (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_DDRMATCHED_SHIFT)) & I3C_SINTMASKED_DDRMATCHED_MASK)
33855 
33856 #define I3C_SINTMASKED_CHANDLED_MASK             (0x20000U)
33857 #define I3C_SINTMASKED_CHANDLED_SHIFT            (17U)
33858 /*! CHANDLED - CHANDLED Interrupt Mask */
33859 #define I3C_SINTMASKED_CHANDLED(x)               (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_CHANDLED_SHIFT)) & I3C_SINTMASKED_CHANDLED_MASK)
33860 
33861 #define I3C_SINTMASKED_EVENT_MASK                (0x40000U)
33862 #define I3C_SINTMASKED_EVENT_SHIFT               (18U)
33863 /*! EVENT - EVENT Interrupt Mask */
33864 #define I3C_SINTMASKED_EVENT(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_EVENT_SHIFT)) & I3C_SINTMASKED_EVENT_MASK)
33865 /*! @} */
33866 
33867 /*! @name SERRWARN - Target Errors and Warnings */
33868 /*! @{ */
33869 
33870 #define I3C_SERRWARN_ORUN_MASK                   (0x1U)
33871 #define I3C_SERRWARN_ORUN_SHIFT                  (0U)
33872 /*! ORUN - Overrun Error
33873  *  0b1..Overrun error
33874  *  0b0..No overrun error
33875  *  0b0..No effect
33876  *  0b1..Clear the flag
33877  */
33878 #define I3C_SERRWARN_ORUN(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_ORUN_SHIFT)) & I3C_SERRWARN_ORUN_MASK)
33879 
33880 #define I3C_SERRWARN_URUN_MASK                   (0x2U)
33881 #define I3C_SERRWARN_URUN_SHIFT                  (1U)
33882 /*! URUN - Underrun Error
33883  *  0b1..Underrun error
33884  *  0b0..No underrun error
33885  *  0b0..No effect
33886  *  0b1..Clear the flag
33887  */
33888 #define I3C_SERRWARN_URUN(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_URUN_SHIFT)) & I3C_SERRWARN_URUN_MASK)
33889 
33890 #define I3C_SERRWARN_URUNNACK_MASK               (0x4U)
33891 #define I3C_SERRWARN_URUNNACK_SHIFT              (2U)
33892 /*! URUNNACK - Underrun and Not Acknowledged (NACKed) Error
33893  *  0b1..Underrun; not acknowledged error
33894  *  0b0..No underrun; not acknowledged error
33895  *  0b0..No effect
33896  *  0b1..Clear the flag
33897  */
33898 #define I3C_SERRWARN_URUNNACK(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_URUNNACK_SHIFT)) & I3C_SERRWARN_URUNNACK_MASK)
33899 
33900 #define I3C_SERRWARN_TERM_MASK                   (0x8U)
33901 #define I3C_SERRWARN_TERM_SHIFT                  (3U)
33902 /*! TERM - Terminated Error
33903  *  0b1..Terminated error
33904  *  0b0..No terminated error
33905  *  0b0..No effect
33906  *  0b1..Clear the flag
33907  */
33908 #define I3C_SERRWARN_TERM(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_TERM_SHIFT)) & I3C_SERRWARN_TERM_MASK)
33909 
33910 #define I3C_SERRWARN_INVSTART_MASK               (0x10U)
33911 #define I3C_SERRWARN_INVSTART_SHIFT              (4U)
33912 /*! INVSTART - Invalid Start Error
33913  *  0b1..Invalid start error
33914  *  0b0..No invalid start error
33915  *  0b0..No effect
33916  *  0b1..Clear the flag
33917  */
33918 #define I3C_SERRWARN_INVSTART(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_INVSTART_SHIFT)) & I3C_SERRWARN_INVSTART_MASK)
33919 
33920 #define I3C_SERRWARN_SPAR_MASK                   (0x100U)
33921 #define I3C_SERRWARN_SPAR_SHIFT                  (8U)
33922 /*! SPAR - SDR Parity Error
33923  *  0b1..SDR parity error
33924  *  0b0..No SDR parity error
33925  *  0b0..No effect
33926  *  0b1..Clear the flag
33927  */
33928 #define I3C_SERRWARN_SPAR(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_SPAR_SHIFT)) & I3C_SERRWARN_SPAR_MASK)
33929 
33930 #define I3C_SERRWARN_HPAR_MASK                   (0x200U)
33931 #define I3C_SERRWARN_HPAR_SHIFT                  (9U)
33932 /*! HPAR - HDR Parity Error
33933  *  0b1..HDR parity error
33934  *  0b0..No HDR parity error
33935  *  0b0..No effect
33936  *  0b1..Clear the flag
33937  */
33938 #define I3C_SERRWARN_HPAR(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_HPAR_SHIFT)) & I3C_SERRWARN_HPAR_MASK)
33939 
33940 #define I3C_SERRWARN_HCRC_MASK                   (0x400U)
33941 #define I3C_SERRWARN_HCRC_SHIFT                  (10U)
33942 /*! HCRC - HDR-DDR CRC Error
33943  *  0b1..HDR-DDR CRC error occurred
33944  *  0b0..No HDR-DDR CRC error occurred
33945  *  0b0..No effect
33946  *  0b1..Clear the flag
33947  */
33948 #define I3C_SERRWARN_HCRC(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_HCRC_SHIFT)) & I3C_SERRWARN_HCRC_MASK)
33949 
33950 #define I3C_SERRWARN_S0S1_MASK                   (0x800U)
33951 #define I3C_SERRWARN_S0S1_SHIFT                  (11U)
33952 /*! S0S1 - TE0 or TE1 Error
33953  *  0b1..TE0 or TE1 error occurred
33954  *  0b0..No TE0 or TE1 error occurred
33955  *  0b0..No effect
33956  *  0b1..Clear the flag
33957  */
33958 #define I3C_SERRWARN_S0S1(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_S0S1_SHIFT)) & I3C_SERRWARN_S0S1_MASK)
33959 
33960 #define I3C_SERRWARN_OREAD_MASK                  (0x10000U)
33961 #define I3C_SERRWARN_OREAD_SHIFT                 (16U)
33962 /*! OREAD - Over-Read Error
33963  *  0b1..Over-read error
33964  *  0b0..No over-read error
33965  *  0b0..No effect
33966  *  0b1..Clear the flag
33967  */
33968 #define I3C_SERRWARN_OREAD(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_OREAD_SHIFT)) & I3C_SERRWARN_OREAD_MASK)
33969 
33970 #define I3C_SERRWARN_OWRITE_MASK                 (0x20000U)
33971 #define I3C_SERRWARN_OWRITE_SHIFT                (17U)
33972 /*! OWRITE - Over-Write Error
33973  *  0b1..Overwrite error
33974  *  0b0..No overwrite error
33975  *  0b0..No effect
33976  *  0b1..Clear the flag
33977  */
33978 #define I3C_SERRWARN_OWRITE(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_OWRITE_SHIFT)) & I3C_SERRWARN_OWRITE_MASK)
33979 /*! @} */
33980 
33981 /*! @name SDMACTRL - Target DMA Control */
33982 /*! @{ */
33983 
33984 #define I3C_SDMACTRL_DMAFB_MASK                  (0x3U)
33985 #define I3C_SDMACTRL_DMAFB_SHIFT                 (0U)
33986 /*! DMAFB - DMA Read (From-Bus) Trigger
33987  *  0b00..DMA not used
33988  *  0b01..DMA enabled for one frame
33989  *  0b10..DMA enabled until turned off
33990  *  0b11..
33991  */
33992 #define I3C_SDMACTRL_DMAFB(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SDMACTRL_DMAFB_SHIFT)) & I3C_SDMACTRL_DMAFB_MASK)
33993 
33994 #define I3C_SDMACTRL_DMATB_MASK                  (0xCU)
33995 #define I3C_SDMACTRL_DMATB_SHIFT                 (2U)
33996 /*! DMATB - DMA Write (To-Bus) Trigger
33997  *  0b00..DMA not used
33998  *  0b01..DMA enabled for one frame
33999  *  0b10..DMA enabled until turned off
34000  *  0b11..
34001  */
34002 #define I3C_SDMACTRL_DMATB(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SDMACTRL_DMATB_SHIFT)) & I3C_SDMACTRL_DMATB_MASK)
34003 
34004 #define I3C_SDMACTRL_DMAWIDTH_MASK               (0x30U)
34005 #define I3C_SDMACTRL_DMAWIDTH_SHIFT              (4U)
34006 /*! DMAWIDTH - Width of DMA Operations
34007  *  0b00, 0b01..Byte
34008  *  0b10..Halfword (16 bits) (this value ensures that two bytes are available in the FIFO)
34009  *  0b11..
34010  */
34011 #define I3C_SDMACTRL_DMAWIDTH(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SDMACTRL_DMAWIDTH_SHIFT)) & I3C_SDMACTRL_DMAWIDTH_MASK)
34012 /*! @} */
34013 
34014 /*! @name SDATACTRL - Target Data Control */
34015 /*! @{ */
34016 
34017 #define I3C_SDATACTRL_FLUSHTB_MASK               (0x1U)
34018 #define I3C_SDATACTRL_FLUSHTB_SHIFT              (0U)
34019 /*! FLUSHTB - Flush To-Bus Buffer or FIFO */
34020 #define I3C_SDATACTRL_FLUSHTB(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_FLUSHTB_SHIFT)) & I3C_SDATACTRL_FLUSHTB_MASK)
34021 
34022 #define I3C_SDATACTRL_FLUSHFB_MASK               (0x2U)
34023 #define I3C_SDATACTRL_FLUSHFB_SHIFT              (1U)
34024 /*! FLUSHFB - Flush From-Bus Buffer or FIFO */
34025 #define I3C_SDATACTRL_FLUSHFB(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_FLUSHFB_SHIFT)) & I3C_SDATACTRL_FLUSHFB_MASK)
34026 
34027 #define I3C_SDATACTRL_UNLOCK_MASK                (0x8U)
34028 #define I3C_SDATACTRL_UNLOCK_SHIFT               (3U)
34029 /*! UNLOCK - Unlock
34030  *  0b0..Cannot be changed
34031  *  0b1..Can be changed
34032  */
34033 #define I3C_SDATACTRL_UNLOCK(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_UNLOCK_SHIFT)) & I3C_SDATACTRL_UNLOCK_MASK)
34034 
34035 #define I3C_SDATACTRL_TXTRIG_MASK                (0x30U)
34036 #define I3C_SDATACTRL_TXTRIG_SHIFT               (4U)
34037 /*! TXTRIG - Transmit Trigger Level
34038  *  0b00..Trigger when empty
34039  *  0b01..Trigger when 1/4 full or less
34040  *  0b10..Trigger when 1/2 full or less
34041  *  0b11..Default (trigger when 1 less than full or less)
34042  */
34043 #define I3C_SDATACTRL_TXTRIG(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_TXTRIG_SHIFT)) & I3C_SDATACTRL_TXTRIG_MASK)
34044 
34045 #define I3C_SDATACTRL_RXTRIG_MASK                (0xC0U)
34046 #define I3C_SDATACTRL_RXTRIG_SHIFT               (6U)
34047 /*! RXTRIG - Receive Trigger Level
34048  *  0b00..Trigger when not empty
34049  *  0b01..Trigger when 1/4 or more full
34050  *  0b10..Trigger when 1/2 or more full
34051  *  0b11..Trigger when 3/4 or more full
34052  */
34053 #define I3C_SDATACTRL_RXTRIG(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_RXTRIG_SHIFT)) & I3C_SDATACTRL_RXTRIG_MASK)
34054 
34055 #define I3C_SDATACTRL_TXCOUNT_MASK               (0x1F0000U)
34056 #define I3C_SDATACTRL_TXCOUNT_SHIFT              (16U)
34057 /*! TXCOUNT - Count of Bytes in Transmit */
34058 #define I3C_SDATACTRL_TXCOUNT(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_TXCOUNT_SHIFT)) & I3C_SDATACTRL_TXCOUNT_MASK)
34059 
34060 #define I3C_SDATACTRL_RXCOUNT_MASK               (0x1F000000U)
34061 #define I3C_SDATACTRL_RXCOUNT_SHIFT              (24U)
34062 /*! RXCOUNT - Count of Bytes in Receive */
34063 #define I3C_SDATACTRL_RXCOUNT(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_RXCOUNT_SHIFT)) & I3C_SDATACTRL_RXCOUNT_MASK)
34064 
34065 #define I3C_SDATACTRL_TXFULL_MASK                (0x40000000U)
34066 #define I3C_SDATACTRL_TXFULL_SHIFT               (30U)
34067 /*! TXFULL - Transmit is Full
34068  *  0b1..Full
34069  *  0b0..Not full
34070  */
34071 #define I3C_SDATACTRL_TXFULL(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_TXFULL_SHIFT)) & I3C_SDATACTRL_TXFULL_MASK)
34072 
34073 #define I3C_SDATACTRL_RXEMPTY_MASK               (0x80000000U)
34074 #define I3C_SDATACTRL_RXEMPTY_SHIFT              (31U)
34075 /*! RXEMPTY - Receive is Empty
34076  *  0b1..Empty
34077  *  0b0..Not empty
34078  */
34079 #define I3C_SDATACTRL_RXEMPTY(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_RXEMPTY_SHIFT)) & I3C_SDATACTRL_RXEMPTY_MASK)
34080 /*! @} */
34081 
34082 /*! @name SWDATAB - Target Write Data Byte */
34083 /*! @{ */
34084 
34085 #define I3C_SWDATAB_DATA_MASK                    (0xFFU)
34086 #define I3C_SWDATAB_DATA_SHIFT                   (0U)
34087 /*! DATA - Data */
34088 #define I3C_SWDATAB_DATA(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB_DATA_SHIFT)) & I3C_SWDATAB_DATA_MASK)
34089 
34090 #define I3C_SWDATAB_END_MASK                     (0x100U)
34091 #define I3C_SWDATAB_END_SHIFT                    (8U)
34092 /*! END - End
34093  *  0b1..End
34094  *  0b0..Not the end
34095  */
34096 #define I3C_SWDATAB_END(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB_END_SHIFT)) & I3C_SWDATAB_END_MASK)
34097 
34098 #define I3C_SWDATAB_END_ALSO_MASK                (0x10000U)
34099 #define I3C_SWDATAB_END_ALSO_SHIFT               (16U)
34100 /*! END_ALSO - End Also
34101  *  0b1..End
34102  *  0b0..Not the end
34103  */
34104 #define I3C_SWDATAB_END_ALSO(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB_END_ALSO_SHIFT)) & I3C_SWDATAB_END_ALSO_MASK)
34105 /*! @} */
34106 
34107 /*! @name SWDATABE - Target Write Data Byte End */
34108 /*! @{ */
34109 
34110 #define I3C_SWDATABE_DATA_MASK                   (0xFFU)
34111 #define I3C_SWDATABE_DATA_SHIFT                  (0U)
34112 /*! DATA - Data */
34113 #define I3C_SWDATABE_DATA(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SWDATABE_DATA_SHIFT)) & I3C_SWDATABE_DATA_MASK)
34114 /*! @} */
34115 
34116 /*! @name SWDATAH - Target Write Data Halfword */
34117 /*! @{ */
34118 
34119 #define I3C_SWDATAH_DATA0_MASK                   (0xFFU)
34120 #define I3C_SWDATAH_DATA0_SHIFT                  (0U)
34121 /*! DATA0 - Data 0 */
34122 #define I3C_SWDATAH_DATA0(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAH_DATA0_SHIFT)) & I3C_SWDATAH_DATA0_MASK)
34123 
34124 #define I3C_SWDATAH_DATA1_MASK                   (0xFF00U)
34125 #define I3C_SWDATAH_DATA1_SHIFT                  (8U)
34126 /*! DATA1 - Data 1 */
34127 #define I3C_SWDATAH_DATA1(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAH_DATA1_SHIFT)) & I3C_SWDATAH_DATA1_MASK)
34128 
34129 #define I3C_SWDATAH_END_MASK                     (0x10000U)
34130 #define I3C_SWDATAH_END_SHIFT                    (16U)
34131 /*! END - End of Message
34132  *  0b1..End
34133  *  0b0..Not the end
34134  */
34135 #define I3C_SWDATAH_END(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAH_END_SHIFT)) & I3C_SWDATAH_END_MASK)
34136 /*! @} */
34137 
34138 /*! @name SWDATAHE - Target Write Data Halfword End */
34139 /*! @{ */
34140 
34141 #define I3C_SWDATAHE_DATA0_MASK                  (0xFFU)
34142 #define I3C_SWDATAHE_DATA0_SHIFT                 (0U)
34143 /*! DATA0 - Data 0 */
34144 #define I3C_SWDATAHE_DATA0(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAHE_DATA0_SHIFT)) & I3C_SWDATAHE_DATA0_MASK)
34145 
34146 #define I3C_SWDATAHE_DATA1_MASK                  (0xFF00U)
34147 #define I3C_SWDATAHE_DATA1_SHIFT                 (8U)
34148 /*! DATA1 - Data 1 */
34149 #define I3C_SWDATAHE_DATA1(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAHE_DATA1_SHIFT)) & I3C_SWDATAHE_DATA1_MASK)
34150 /*! @} */
34151 
34152 /*! @name SRDATAB - Target Read Data Byte */
34153 /*! @{ */
34154 
34155 #define I3C_SRDATAB_DATA0_MASK                   (0xFFU)
34156 #define I3C_SRDATAB_DATA0_SHIFT                  (0U)
34157 /*! DATA0 - Data 0 */
34158 #define I3C_SRDATAB_DATA0(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SRDATAB_DATA0_SHIFT)) & I3C_SRDATAB_DATA0_MASK)
34159 /*! @} */
34160 
34161 /*! @name SRDATAH - Target Read Data Halfword */
34162 /*! @{ */
34163 
34164 #define I3C_SRDATAH_LSB_MASK                     (0xFFU)
34165 #define I3C_SRDATAH_LSB_SHIFT                    (0U)
34166 /*! LSB - Low Byte */
34167 #define I3C_SRDATAH_LSB(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_SRDATAH_LSB_SHIFT)) & I3C_SRDATAH_LSB_MASK)
34168 
34169 #define I3C_SRDATAH_MSB_MASK                     (0xFF00U)
34170 #define I3C_SRDATAH_MSB_SHIFT                    (8U)
34171 /*! MSB - High Byte */
34172 #define I3C_SRDATAH_MSB(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_SRDATAH_MSB_SHIFT)) & I3C_SRDATAH_MSB_MASK)
34173 /*! @} */
34174 
34175 /*! @name SWDATAB1 - Target Write Data Byte */
34176 /*! @{ */
34177 
34178 #define I3C_SWDATAB1_DATA_MASK                   (0xFFU)
34179 #define I3C_SWDATAB1_DATA_SHIFT                  (0U)
34180 /*! DATA - Data */
34181 #define I3C_SWDATAB1_DATA(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB1_DATA_SHIFT)) & I3C_SWDATAB1_DATA_MASK)
34182 /*! @} */
34183 
34184 /*! @name SCAPABILITIES2 - Target Capabilities 2 */
34185 /*! @{ */
34186 
34187 #define I3C_SCAPABILITIES2_MAPCNT_MASK           (0xFU)
34188 #define I3C_SCAPABILITIES2_MAPCNT_SHIFT          (0U)
34189 /*! MAPCNT - Map Count */
34190 #define I3C_SCAPABILITIES2_MAPCNT(x)             (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_MAPCNT_SHIFT)) & I3C_SCAPABILITIES2_MAPCNT_MASK)
34191 
34192 #define I3C_SCAPABILITIES2_I2C10B_MASK           (0x10U)
34193 #define I3C_SCAPABILITIES2_I2C10B_SHIFT          (4U)
34194 /*! I2C10B - I2C 10-bit Address
34195  *  0b0..Not supported
34196  *  0b1..Supported
34197  */
34198 #define I3C_SCAPABILITIES2_I2C10B(x)             (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_I2C10B_SHIFT)) & I3C_SCAPABILITIES2_I2C10B_MASK)
34199 
34200 #define I3C_SCAPABILITIES2_I2CRST_MASK           (0x20U)
34201 #define I3C_SCAPABILITIES2_I2CRST_SHIFT          (5U)
34202 /*! I2CRST - I2C Software Reset
34203  *  0b0..Not supported
34204  *  0b1..Supported
34205  */
34206 #define I3C_SCAPABILITIES2_I2CRST(x)             (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_I2CRST_SHIFT)) & I3C_SCAPABILITIES2_I2CRST_MASK)
34207 
34208 #define I3C_SCAPABILITIES2_I2CDEVID_MASK         (0x40U)
34209 #define I3C_SCAPABILITIES2_I2CDEVID_SHIFT        (6U)
34210 /*! I2CDEVID - I2C Device ID
34211  *  0b0..Not supported
34212  *  0b1..Supported
34213  */
34214 #define I3C_SCAPABILITIES2_I2CDEVID(x)           (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_I2CDEVID_SHIFT)) & I3C_SCAPABILITIES2_I2CDEVID_MASK)
34215 
34216 #define I3C_SCAPABILITIES2_IBIEXT_MASK           (0x100U)
34217 #define I3C_SCAPABILITIES2_IBIEXT_SHIFT          (8U)
34218 /*! IBIEXT - In-Band Interrupt EXTDATA
34219  *  0b0..Not supported
34220  *  0b1..Supported
34221  */
34222 #define I3C_SCAPABILITIES2_IBIEXT(x)             (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_IBIEXT_SHIFT)) & I3C_SCAPABILITIES2_IBIEXT_MASK)
34223 
34224 #define I3C_SCAPABILITIES2_IBIXREG_MASK          (0x200U)
34225 #define I3C_SCAPABILITIES2_IBIXREG_SHIFT         (9U)
34226 /*! IBIXREG - In-Band Interrupt Extended Register
34227  *  0b0..Not supported
34228  *  0b1..Supported
34229  */
34230 #define I3C_SCAPABILITIES2_IBIXREG(x)            (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_IBIXREG_SHIFT)) & I3C_SCAPABILITIES2_IBIXREG_MASK)
34231 
34232 #define I3C_SCAPABILITIES2_SLVRST_MASK           (0x20000U)
34233 #define I3C_SCAPABILITIES2_SLVRST_SHIFT          (17U)
34234 /*! SLVRST - Target Reset
34235  *  0b0..Not supported
34236  *  0b1..Supported
34237  */
34238 #define I3C_SCAPABILITIES2_SLVRST(x)             (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_SLVRST_SHIFT)) & I3C_SCAPABILITIES2_SLVRST_MASK)
34239 
34240 #define I3C_SCAPABILITIES2_GROUP_MASK            (0xC0000U)
34241 #define I3C_SCAPABILITIES2_GROUP_SHIFT           (18U)
34242 /*! GROUP - Group
34243  *  0b00..v1.1 group addressing not supported
34244  *  0b01..One group supported
34245  *  0b10..Two groups supported
34246  *  0b11..Three groups supported
34247  */
34248 #define I3C_SCAPABILITIES2_GROUP(x)              (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_GROUP_SHIFT)) & I3C_SCAPABILITIES2_GROUP_MASK)
34249 
34250 #define I3C_SCAPABILITIES2_AASA_MASK             (0x200000U)
34251 #define I3C_SCAPABILITIES2_AASA_SHIFT            (21U)
34252 /*! AASA - SETAASA
34253  *  0b1..SETAASA supported
34254  *  0b0..SETAASA not supported
34255  */
34256 #define I3C_SCAPABILITIES2_AASA(x)               (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_AASA_SHIFT)) & I3C_SCAPABILITIES2_AASA_MASK)
34257 
34258 #define I3C_SCAPABILITIES2_SSTSUB_MASK           (0x400000U)
34259 #define I3C_SCAPABILITIES2_SSTSUB_SHIFT          (22U)
34260 /*! SSTSUB - Target-Target(s)-Tunnel Subscriber Capable
34261  *  0b1..Subscriber capable
34262  *  0b0..Not subscriber capable
34263  */
34264 #define I3C_SCAPABILITIES2_SSTSUB(x)             (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_SSTSUB_SHIFT)) & I3C_SCAPABILITIES2_SSTSUB_MASK)
34265 
34266 #define I3C_SCAPABILITIES2_SSTWR_MASK            (0x800000U)
34267 #define I3C_SCAPABILITIES2_SSTWR_SHIFT           (23U)
34268 /*! SSTWR - Target-Target(s)-Tunnel Write Capable
34269  *  0b1..Write capable
34270  *  0b0..Not write capable
34271  */
34272 #define I3C_SCAPABILITIES2_SSTWR(x)              (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_SSTWR_SHIFT)) & I3C_SCAPABILITIES2_SSTWR_MASK)
34273 /*! @} */
34274 
34275 /*! @name SCAPABILITIES - Target Capabilities */
34276 /*! @{ */
34277 
34278 #define I3C_SCAPABILITIES_IDENA_MASK             (0x3U)
34279 #define I3C_SCAPABILITIES_IDENA_SHIFT            (0U)
34280 /*! IDENA - ID 48b Handler
34281  *  0b00..Application
34282  *  0b01..Hardware
34283  *  0b10..Hardware, but the I3C module instance handles ID 48b
34284  *  0b11..A part number register (PARTNO)
34285  */
34286 #define I3C_SCAPABILITIES_IDENA(x)               (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_IDENA_SHIFT)) & I3C_SCAPABILITIES_IDENA_MASK)
34287 
34288 #define I3C_SCAPABILITIES_IDREG_MASK             (0x3CU)
34289 #define I3C_SCAPABILITIES_IDREG_SHIFT            (2U)
34290 /*! IDREG - ID Register
34291  *  0b0000..All ID register features disabled
34292  *  0bxxx1..ID Instance is a register; used if there is no PARTNO register
34293  *  0bxx1x..An ID Random field is available
34294  *  0bx1xx..A Device Characteristic Register (DCR) is available
34295  *  0b1xxx..A Bus Characteristics Register (BCR) is available
34296  */
34297 #define I3C_SCAPABILITIES_IDREG(x)               (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_IDREG_SHIFT)) & I3C_SCAPABILITIES_IDREG_MASK)
34298 
34299 #define I3C_SCAPABILITIES_HDRSUPP_MASK           (0xC0U)
34300 #define I3C_SCAPABILITIES_HDRSUPP_SHIFT          (6U)
34301 /*! HDRSUPP - High Data Rate Support
34302  *  0b00..No HDR modes supported
34303  *  0b01..DDR mode supported
34304  *  *..
34305  */
34306 #define I3C_SCAPABILITIES_HDRSUPP(x)             (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_HDRSUPP_SHIFT)) & I3C_SCAPABILITIES_HDRSUPP_MASK)
34307 
34308 #define I3C_SCAPABILITIES_MASTER_MASK            (0x200U)
34309 #define I3C_SCAPABILITIES_MASTER_SHIFT           (9U)
34310 /*! MASTER - Controller
34311  *  0b0..Not supported
34312  *  0b1..Supported
34313  */
34314 #define I3C_SCAPABILITIES_MASTER(x)              (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_MASTER_SHIFT)) & I3C_SCAPABILITIES_MASTER_MASK)
34315 
34316 #define I3C_SCAPABILITIES_SADDR_MASK             (0xC00U)
34317 #define I3C_SCAPABILITIES_SADDR_SHIFT            (10U)
34318 /*! SADDR - Static Address
34319  *  0b00..No static address
34320  *  0b01..Static address is fixed in hardware
34321  *  0b10..Hardware controls the static address dynamically (for example, from the pin strap)
34322  *  0b11..SCONFIG register supplies the static address
34323  */
34324 #define I3C_SCAPABILITIES_SADDR(x)               (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_SADDR_SHIFT)) & I3C_SCAPABILITIES_SADDR_MASK)
34325 
34326 #define I3C_SCAPABILITIES_CCCHANDLE_MASK         (0xF000U)
34327 #define I3C_SCAPABILITIES_CCCHANDLE_SHIFT        (12U)
34328 /*! CCCHANDLE - Common Command Codes Handling
34329  *  0b0000..All handling features disabled
34330  *  0bxxx1..The I3C module manages events, activities, status, HDR, and if enabled for it, ID and static-address-related items
34331  *  0bxx1x..The I3C module manages maximum read and write lengths, and max data speed
34332  *  0bx1xx..GETSTATUS CCC returns the values of SCTRL[PENDINT] and SCTRL[ACTSTATE]
34333  *  0b1xxx..GETSTATUS CCC returns the value of SCTRL[VENDINFO]
34334  */
34335 #define I3C_SCAPABILITIES_CCCHANDLE(x)           (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_CCCHANDLE_SHIFT)) & I3C_SCAPABILITIES_CCCHANDLE_MASK)
34336 
34337 #define I3C_SCAPABILITIES_IBI_MR_HJ_MASK         (0x1F0000U)
34338 #define I3C_SCAPABILITIES_IBI_MR_HJ_SHIFT        (16U)
34339 /*! IBI_MR_HJ - In-Band Interrupts, Controller Requests, Hot-Join Events
34340  *  0b00000..Application cannot generate IBI, CR, or HJ
34341  *  0bxxxx1..Application can generate an IBI
34342  *  0bxxx1x..When bit 0 = 1, the IBI has data from the SCTRL register
34343  *  0bxx1xx..Application can generate a controller request for a secondary controller
34344  *  0bx1xxx..Application can generate a Hot-Join event
34345  *  0b1xxxx..Application can use SCONFIG[BAMATCH] for bus-available timing
34346  */
34347 #define I3C_SCAPABILITIES_IBI_MR_HJ(x)           (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_IBI_MR_HJ_SHIFT)) & I3C_SCAPABILITIES_IBI_MR_HJ_MASK)
34348 
34349 #define I3C_SCAPABILITIES_TIMECTRL_MASK          (0x200000U)
34350 #define I3C_SCAPABILITIES_TIMECTRL_SHIFT         (21U)
34351 /*! TIMECTRL - Time Control
34352  *  0b0..No time control supported
34353  *  0b1..At least one time-control type supported
34354  */
34355 #define I3C_SCAPABILITIES_TIMECTRL(x)            (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_TIMECTRL_SHIFT)) & I3C_SCAPABILITIES_TIMECTRL_MASK)
34356 
34357 #define I3C_SCAPABILITIES_EXTFIFO_MASK           (0x3800000U)
34358 #define I3C_SCAPABILITIES_EXTFIFO_SHIFT          (23U)
34359 /*! EXTFIFO - External FIFO
34360  *  0b000..No external FIFO available
34361  *  0b001..Standard available or free external FIFO
34362  *  0b010..Request track external FIFO
34363  *  *..
34364  */
34365 #define I3C_SCAPABILITIES_EXTFIFO(x)             (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_EXTFIFO_SHIFT)) & I3C_SCAPABILITIES_EXTFIFO_MASK)
34366 
34367 #define I3C_SCAPABILITIES_FIFOTX_MASK            (0xC000000U)
34368 #define I3C_SCAPABILITIES_FIFOTX_SHIFT           (26U)
34369 /*! FIFOTX - FIFO Transmit
34370  *  0b00..Two
34371  *  0b01..Four
34372  *  0b10..Eight
34373  *  0b11..16 or larger
34374  */
34375 #define I3C_SCAPABILITIES_FIFOTX(x)              (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_FIFOTX_SHIFT)) & I3C_SCAPABILITIES_FIFOTX_MASK)
34376 
34377 #define I3C_SCAPABILITIES_FIFORX_MASK            (0x30000000U)
34378 #define I3C_SCAPABILITIES_FIFORX_SHIFT           (28U)
34379 /*! FIFORX - FIFO Receive
34380  *  0b00..Two or three
34381  *  0b01..Four
34382  *  0b10..Eight
34383  *  0b11..16 or larger
34384  */
34385 #define I3C_SCAPABILITIES_FIFORX(x)              (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_FIFORX_SHIFT)) & I3C_SCAPABILITIES_FIFORX_MASK)
34386 
34387 #define I3C_SCAPABILITIES_INT_MASK               (0x40000000U)
34388 #define I3C_SCAPABILITIES_INT_SHIFT              (30U)
34389 /*! INT - Interrupts
34390  *  0b1..Supported
34391  *  0b0..Not supported
34392  */
34393 #define I3C_SCAPABILITIES_INT(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_INT_SHIFT)) & I3C_SCAPABILITIES_INT_MASK)
34394 
34395 #define I3C_SCAPABILITIES_DMA_MASK               (0x80000000U)
34396 #define I3C_SCAPABILITIES_DMA_SHIFT              (31U)
34397 /*! DMA - Direct Memory Access
34398  *  0b1..Supported
34399  *  0b0..Not supported
34400  */
34401 #define I3C_SCAPABILITIES_DMA(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_DMA_SHIFT)) & I3C_SCAPABILITIES_DMA_MASK)
34402 /*! @} */
34403 
34404 /*! @name SDYNADDR - Target Dynamic Address */
34405 /*! @{ */
34406 
34407 #define I3C_SDYNADDR_DAVALID_MASK                (0x1U)
34408 #define I3C_SDYNADDR_DAVALID_SHIFT               (0U)
34409 /*! DAVALID - Dynamic Address Valid
34410  *  0b0..DANOTASSIGNED: a dynamic address is not assigned
34411  *  0b1..DAASSIGNED: a dynamic address is assigned
34412  */
34413 #define I3C_SDYNADDR_DAVALID(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_DAVALID_SHIFT)) & I3C_SDYNADDR_DAVALID_MASK)
34414 
34415 #define I3C_SDYNADDR_DADDR_MASK                  (0xFEU)
34416 #define I3C_SDYNADDR_DADDR_SHIFT                 (1U)
34417 /*! DADDR - Dynamic Address */
34418 #define I3C_SDYNADDR_DADDR(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_DADDR_SHIFT)) & I3C_SDYNADDR_DADDR_MASK)
34419 
34420 #define I3C_SDYNADDR_MAPSA_MASK                  (0x1000U)
34421 #define I3C_SDYNADDR_MAPSA_SHIFT                 (12U)
34422 /*! MAPSA - Map a Static Address */
34423 #define I3C_SDYNADDR_MAPSA(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_MAPSA_SHIFT)) & I3C_SDYNADDR_MAPSA_MASK)
34424 
34425 #define I3C_SDYNADDR_SA10B_MASK                  (0xE000U)
34426 #define I3C_SDYNADDR_SA10B_SHIFT                 (13U)
34427 /*! SA10B - 10-Bit Static Address */
34428 #define I3C_SDYNADDR_SA10B(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_SA10B_SHIFT)) & I3C_SDYNADDR_SA10B_MASK)
34429 
34430 #define I3C_SDYNADDR_KEY_MASK                    (0xFFFF0000U)
34431 #define I3C_SDYNADDR_KEY_SHIFT                   (16U)
34432 /*! KEY - Key */
34433 #define I3C_SDYNADDR_KEY(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_KEY_SHIFT)) & I3C_SDYNADDR_KEY_MASK)
34434 /*! @} */
34435 
34436 /*! @name SMAXLIMITS - Target Maximum Limits */
34437 /*! @{ */
34438 
34439 #define I3C_SMAXLIMITS_MAXRD_MASK                (0xFFFU)
34440 #define I3C_SMAXLIMITS_MAXRD_SHIFT               (0U)
34441 /*! MAXRD - Maximum Read Length */
34442 #define I3C_SMAXLIMITS_MAXRD(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SMAXLIMITS_MAXRD_SHIFT)) & I3C_SMAXLIMITS_MAXRD_MASK)
34443 
34444 #define I3C_SMAXLIMITS_MAXWR_MASK                (0xFFF0000U)
34445 #define I3C_SMAXLIMITS_MAXWR_SHIFT               (16U)
34446 /*! MAXWR - Maximum Write Length */
34447 #define I3C_SMAXLIMITS_MAXWR(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SMAXLIMITS_MAXWR_SHIFT)) & I3C_SMAXLIMITS_MAXWR_MASK)
34448 /*! @} */
34449 
34450 /*! @name SIDPARTNO - Target ID Part Number */
34451 /*! @{ */
34452 
34453 #define I3C_SIDPARTNO_PARTNO_MASK                (0xFFFFFFFFU)
34454 #define I3C_SIDPARTNO_PARTNO_SHIFT               (0U)
34455 /*! PARTNO - Part Number */
34456 #define I3C_SIDPARTNO_PARTNO(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SIDPARTNO_PARTNO_SHIFT)) & I3C_SIDPARTNO_PARTNO_MASK)
34457 /*! @} */
34458 
34459 /*! @name SIDEXT - Target ID Extension */
34460 /*! @{ */
34461 
34462 #define I3C_SIDEXT_DCR_MASK                      (0xFF00U)
34463 #define I3C_SIDEXT_DCR_SHIFT                     (8U)
34464 /*! DCR - Device Characteristic Register */
34465 #define I3C_SIDEXT_DCR(x)                        (((uint32_t)(((uint32_t)(x)) << I3C_SIDEXT_DCR_SHIFT)) & I3C_SIDEXT_DCR_MASK)
34466 
34467 #define I3C_SIDEXT_BCR_MASK                      (0xFF0000U)
34468 #define I3C_SIDEXT_BCR_SHIFT                     (16U)
34469 /*! BCR - Bus Characteristics Register */
34470 #define I3C_SIDEXT_BCR(x)                        (((uint32_t)(((uint32_t)(x)) << I3C_SIDEXT_BCR_SHIFT)) & I3C_SIDEXT_BCR_MASK)
34471 /*! @} */
34472 
34473 /*! @name SVENDORID - Target Vendor ID */
34474 /*! @{ */
34475 
34476 #define I3C_SVENDORID_VID_MASK                   (0x7FFFU)
34477 #define I3C_SVENDORID_VID_SHIFT                  (0U)
34478 /*! VID - Vendor ID */
34479 #define I3C_SVENDORID_VID(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SVENDORID_VID_SHIFT)) & I3C_SVENDORID_VID_MASK)
34480 /*! @} */
34481 
34482 /*! @name STCCLOCK - Target Time Control Clock */
34483 /*! @{ */
34484 
34485 #define I3C_STCCLOCK_ACCURACY_MASK               (0xFFU)
34486 #define I3C_STCCLOCK_ACCURACY_SHIFT              (0U)
34487 /*! ACCURACY - Clock Accuracy */
34488 #define I3C_STCCLOCK_ACCURACY(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_STCCLOCK_ACCURACY_SHIFT)) & I3C_STCCLOCK_ACCURACY_MASK)
34489 
34490 #define I3C_STCCLOCK_FREQ_MASK                   (0xFF00U)
34491 #define I3C_STCCLOCK_FREQ_SHIFT                  (8U)
34492 /*! FREQ - Clock Frequency */
34493 #define I3C_STCCLOCK_FREQ(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_STCCLOCK_FREQ_SHIFT)) & I3C_STCCLOCK_FREQ_MASK)
34494 /*! @} */
34495 
34496 /*! @name SMSGMAPADDR - Target Message Map Address */
34497 /*! @{ */
34498 
34499 #define I3C_SMSGMAPADDR_MAPLAST_MASK             (0xFU)
34500 #define I3C_SMSGMAPADDR_MAPLAST_SHIFT            (0U)
34501 /*! MAPLAST - Matched Address Index */
34502 #define I3C_SMSGMAPADDR_MAPLAST(x)               (((uint32_t)(((uint32_t)(x)) << I3C_SMSGMAPADDR_MAPLAST_SHIFT)) & I3C_SMSGMAPADDR_MAPLAST_MASK)
34503 
34504 #define I3C_SMSGMAPADDR_LASTSTATIC_MASK          (0x10U)
34505 #define I3C_SMSGMAPADDR_LASTSTATIC_SHIFT         (4U)
34506 /*! LASTSTATIC - Last Static Address Matched
34507  *  0b1..I2C static address
34508  *  0b0..I3C dynamic address
34509  */
34510 #define I3C_SMSGMAPADDR_LASTSTATIC(x)            (((uint32_t)(((uint32_t)(x)) << I3C_SMSGMAPADDR_LASTSTATIC_SHIFT)) & I3C_SMSGMAPADDR_LASTSTATIC_MASK)
34511 
34512 #define I3C_SMSGMAPADDR_MAPLASTM1_MASK           (0xF00U)
34513 #define I3C_SMSGMAPADDR_MAPLASTM1_SHIFT          (8U)
34514 /*! MAPLASTM1 - Matched Previous Address Index 1 */
34515 #define I3C_SMSGMAPADDR_MAPLASTM1(x)             (((uint32_t)(((uint32_t)(x)) << I3C_SMSGMAPADDR_MAPLASTM1_SHIFT)) & I3C_SMSGMAPADDR_MAPLASTM1_MASK)
34516 
34517 #define I3C_SMSGMAPADDR_MAPLASTM2_MASK           (0xF0000U)
34518 #define I3C_SMSGMAPADDR_MAPLASTM2_SHIFT          (16U)
34519 /*! MAPLASTM2 - Matched Previous Index 2 */
34520 #define I3C_SMSGMAPADDR_MAPLASTM2(x)             (((uint32_t)(((uint32_t)(x)) << I3C_SMSGMAPADDR_MAPLASTM2_SHIFT)) & I3C_SMSGMAPADDR_MAPLASTM2_MASK)
34521 /*! @} */
34522 
34523 /*! @name MCTRL - Controller Control */
34524 /*! @{ */
34525 
34526 #define I3C_MCTRL_REQUEST_MASK                   (0x7U)
34527 #define I3C_MCTRL_REQUEST_SHIFT                  (0U)
34528 /*! REQUEST - Request
34529  *  0b000..NONE
34530  *  0b001..EMITSTARTADDR
34531  *  0b010..EMITSTOP
34532  *  0b011..IBIACKNACK
34533  *  0b100..PROCESSDAA
34534  *  0b101..
34535  *  0b110..Force Exit and Target Reset
34536  *  0b111..AUTOIBI
34537  */
34538 #define I3C_MCTRL_REQUEST(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_REQUEST_SHIFT)) & I3C_MCTRL_REQUEST_MASK)
34539 
34540 #define I3C_MCTRL_TYPE_MASK                      (0x30U)
34541 #define I3C_MCTRL_TYPE_SHIFT                     (4U)
34542 /*! TYPE - Bus Type with EmitStartAddr
34543  *  0b00..I3C
34544  *  0b01..I2C
34545  *  0b10..DDR
34546  *  0b11..
34547  */
34548 #define I3C_MCTRL_TYPE(x)                        (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_TYPE_SHIFT)) & I3C_MCTRL_TYPE_MASK)
34549 
34550 #define I3C_MCTRL_IBIRESP_MASK                   (0xC0U)
34551 #define I3C_MCTRL_IBIRESP_SHIFT                  (6U)
34552 /*! IBIRESP - In-Band Interrupt Response
34553  *  0b00..ACK (acknowledge)
34554  *  0b01..NACK (reject)
34555  *  0b10..Acknowledge with mandatory byte
34556  *  0b11..Manual
34557  */
34558 #define I3C_MCTRL_IBIRESP(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_IBIRESP_SHIFT)) & I3C_MCTRL_IBIRESP_MASK)
34559 
34560 #define I3C_MCTRL_DIR_MASK                       (0x100U)
34561 #define I3C_MCTRL_DIR_SHIFT                      (8U)
34562 /*! DIR - Direction
34563  *  0b0..Write
34564  *  0b1..Read
34565  */
34566 #define I3C_MCTRL_DIR(x)                         (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_DIR_SHIFT)) & I3C_MCTRL_DIR_MASK)
34567 
34568 #define I3C_MCTRL_ADDR_MASK                      (0xFE00U)
34569 #define I3C_MCTRL_ADDR_SHIFT                     (9U)
34570 /*! ADDR - Address */
34571 #define I3C_MCTRL_ADDR(x)                        (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_ADDR_SHIFT)) & I3C_MCTRL_ADDR_MASK)
34572 
34573 #define I3C_MCTRL_RDTERM_MASK                    (0xFF0000U)
34574 #define I3C_MCTRL_RDTERM_SHIFT                   (16U)
34575 /*! RDTERM - Read Terminate Counter */
34576 #define I3C_MCTRL_RDTERM(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_RDTERM_SHIFT)) & I3C_MCTRL_RDTERM_MASK)
34577 /*! @} */
34578 
34579 /*! @name MSTATUS - Controller Status */
34580 /*! @{ */
34581 
34582 #define I3C_MSTATUS_STATE_MASK                   (0x7U)
34583 #define I3C_MSTATUS_STATE_SHIFT                  (0U)
34584 /*! STATE - State of the Controller
34585  *  0b000..IDLE (bus has stopped)
34586  *  0b001..SLVREQ (target request)
34587  *  0b010..MSGSDR
34588  *  0b011..NORMACT
34589  *  0b100..MSGDDR
34590  *  0b101..DAA
34591  *  0b110..IBIACK
34592  *  0b111..IBIRCV
34593  */
34594 #define I3C_MSTATUS_STATE(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_STATE_SHIFT)) & I3C_MSTATUS_STATE_MASK)
34595 
34596 #define I3C_MSTATUS_BETWEEN_MASK                 (0x10U)
34597 #define I3C_MSTATUS_BETWEEN_SHIFT                (4U)
34598 /*! BETWEEN - Between
34599  *  0b0..Inactive (for other cases)
34600  *  0b1..Active
34601  */
34602 #define I3C_MSTATUS_BETWEEN(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_BETWEEN_SHIFT)) & I3C_MSTATUS_BETWEEN_MASK)
34603 
34604 #define I3C_MSTATUS_NACKED_MASK                  (0x20U)
34605 #define I3C_MSTATUS_NACKED_SHIFT                 (5U)
34606 /*! NACKED - Not Acknowledged
34607  *  0b1..NACKed (not acknowledged)
34608  *  0b0..Not NACKed
34609  */
34610 #define I3C_MSTATUS_NACKED(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_NACKED_SHIFT)) & I3C_MSTATUS_NACKED_MASK)
34611 
34612 #define I3C_MSTATUS_IBITYPE_MASK                 (0xC0U)
34613 #define I3C_MSTATUS_IBITYPE_SHIFT                (6U)
34614 /*! IBITYPE - In-Band Interrupt (IBI) Type
34615  *  0b00..NONE (no IBI: this status occurs when MSTATUS[IBIWON] becomes 0)
34616  *  0b01..IBI
34617  *  0b10..CR
34618  *  0b11..HJ
34619  */
34620 #define I3C_MSTATUS_IBITYPE(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_IBITYPE_SHIFT)) & I3C_MSTATUS_IBITYPE_MASK)
34621 
34622 #define I3C_MSTATUS_SLVSTART_MASK                (0x100U)
34623 #define I3C_MSTATUS_SLVSTART_SHIFT               (8U)
34624 /*! SLVSTART - Target Start
34625  *  0b1..Target requesting START
34626  *  0b0..Target not requesting START
34627  *  0b0..No effect
34628  *  0b1..Clear the flag
34629  */
34630 #define I3C_MSTATUS_SLVSTART(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_SLVSTART_SHIFT)) & I3C_MSTATUS_SLVSTART_MASK)
34631 
34632 #define I3C_MSTATUS_MCTRLDONE_MASK               (0x200U)
34633 #define I3C_MSTATUS_MCTRLDONE_SHIFT              (9U)
34634 /*! MCTRLDONE - Controller Control Done
34635  *  0b1..Done
34636  *  0b0..Not done
34637  *  0b0..No effect
34638  *  0b1..Clear the flag
34639  */
34640 #define I3C_MSTATUS_MCTRLDONE(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_MCTRLDONE_SHIFT)) & I3C_MSTATUS_MCTRLDONE_MASK)
34641 
34642 #define I3C_MSTATUS_COMPLETE_MASK                (0x400U)
34643 #define I3C_MSTATUS_COMPLETE_SHIFT               (10U)
34644 /*! COMPLETE - Complete
34645  *  0b1..Complete
34646  *  0b0..Not complete
34647  *  0b0..No effect
34648  *  0b1..Clear the flag
34649  */
34650 #define I3C_MSTATUS_COMPLETE(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_COMPLETE_SHIFT)) & I3C_MSTATUS_COMPLETE_MASK)
34651 
34652 #define I3C_MSTATUS_RXPEND_MASK                  (0x800U)
34653 #define I3C_MSTATUS_RXPEND_SHIFT                 (11U)
34654 /*! RXPEND - RXPEND
34655  *  0b1..Receive message pending
34656  *  0b0..No receive message pending
34657  */
34658 #define I3C_MSTATUS_RXPEND(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_RXPEND_SHIFT)) & I3C_MSTATUS_RXPEND_MASK)
34659 
34660 #define I3C_MSTATUS_TXNOTFULL_MASK               (0x1000U)
34661 #define I3C_MSTATUS_TXNOTFULL_SHIFT              (12U)
34662 /*! TXNOTFULL - TX Buffer or FIFO Not Full
34663  *  0b1..Receive buffer or FIFO not full
34664  *  0b0..Receive buffer or FIFO full
34665  */
34666 #define I3C_MSTATUS_TXNOTFULL(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_TXNOTFULL_SHIFT)) & I3C_MSTATUS_TXNOTFULL_MASK)
34667 
34668 #define I3C_MSTATUS_IBIWON_MASK                  (0x2000U)
34669 #define I3C_MSTATUS_IBIWON_SHIFT                 (13U)
34670 /*! IBIWON - In-Band Interrupt (IBI) Won
34671  *  0b1..IBI arbitration won
34672  *  0b0..No IBI arbitration won
34673  *  0b0..No effect
34674  *  0b1..Clear the flag
34675  */
34676 #define I3C_MSTATUS_IBIWON(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_IBIWON_SHIFT)) & I3C_MSTATUS_IBIWON_MASK)
34677 
34678 #define I3C_MSTATUS_ERRWARN_MASK                 (0x8000U)
34679 #define I3C_MSTATUS_ERRWARN_SHIFT                (15U)
34680 /*! ERRWARN - Error or Warning
34681  *  0b1..Error or warning
34682  *  0b0..No error or warning
34683  */
34684 #define I3C_MSTATUS_ERRWARN(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_ERRWARN_SHIFT)) & I3C_MSTATUS_ERRWARN_MASK)
34685 
34686 #define I3C_MSTATUS_NOWMASTER_MASK               (0x80000U)
34687 #define I3C_MSTATUS_NOWMASTER_SHIFT              (19U)
34688 /*! NOWMASTER - Module is now Controller
34689  *  0b1..Controller
34690  *  0b0..Not a controller
34691  *  0b0..No effect
34692  *  0b1..Clear the flag
34693  */
34694 #define I3C_MSTATUS_NOWMASTER(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_NOWMASTER_SHIFT)) & I3C_MSTATUS_NOWMASTER_MASK)
34695 
34696 #define I3C_MSTATUS_IBIADDR_MASK                 (0x7F000000U)
34697 #define I3C_MSTATUS_IBIADDR_SHIFT                (24U)
34698 /*! IBIADDR - IBI Address */
34699 #define I3C_MSTATUS_IBIADDR(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_IBIADDR_SHIFT)) & I3C_MSTATUS_IBIADDR_MASK)
34700 /*! @} */
34701 
34702 /*! @name MIBIRULES - Controller In-band Interrupt Registry and Rules */
34703 /*! @{ */
34704 
34705 #define I3C_MIBIRULES_ADDR0_MASK                 (0x3FU)
34706 #define I3C_MIBIRULES_ADDR0_SHIFT                (0U)
34707 /*! ADDR0 - ADDR0 */
34708 #define I3C_MIBIRULES_ADDR0(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR0_SHIFT)) & I3C_MIBIRULES_ADDR0_MASK)
34709 
34710 #define I3C_MIBIRULES_ADDR1_MASK                 (0xFC0U)
34711 #define I3C_MIBIRULES_ADDR1_SHIFT                (6U)
34712 /*! ADDR1 - ADDR1 */
34713 #define I3C_MIBIRULES_ADDR1(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR1_SHIFT)) & I3C_MIBIRULES_ADDR1_MASK)
34714 
34715 #define I3C_MIBIRULES_ADDR2_MASK                 (0x3F000U)
34716 #define I3C_MIBIRULES_ADDR2_SHIFT                (12U)
34717 /*! ADDR2 - ADDR2 */
34718 #define I3C_MIBIRULES_ADDR2(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR2_SHIFT)) & I3C_MIBIRULES_ADDR2_MASK)
34719 
34720 #define I3C_MIBIRULES_ADDR3_MASK                 (0xFC0000U)
34721 #define I3C_MIBIRULES_ADDR3_SHIFT                (18U)
34722 /*! ADDR3 - ADDR3 */
34723 #define I3C_MIBIRULES_ADDR3(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR3_SHIFT)) & I3C_MIBIRULES_ADDR3_MASK)
34724 
34725 #define I3C_MIBIRULES_ADDR4_MASK                 (0x3F000000U)
34726 #define I3C_MIBIRULES_ADDR4_SHIFT                (24U)
34727 /*! ADDR4 - ADDR4 */
34728 #define I3C_MIBIRULES_ADDR4(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR4_SHIFT)) & I3C_MIBIRULES_ADDR4_MASK)
34729 
34730 #define I3C_MIBIRULES_MSB0_MASK                  (0x40000000U)
34731 #define I3C_MIBIRULES_MSB0_SHIFT                 (30U)
34732 /*! MSB0 - Most Significant Address Bit is 0
34733  *  0b1..MSB is 0
34734  *  0b0..MSB is not 0
34735  */
34736 #define I3C_MIBIRULES_MSB0(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_MSB0_SHIFT)) & I3C_MIBIRULES_MSB0_MASK)
34737 
34738 #define I3C_MIBIRULES_NOBYTE_MASK                (0x80000000U)
34739 #define I3C_MIBIRULES_NOBYTE_SHIFT               (31U)
34740 /*! NOBYTE - No IBI byte
34741  *  0b1..Without mandatory IBI byte
34742  *  0b0..With mandatory IBI byte
34743  */
34744 #define I3C_MIBIRULES_NOBYTE(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_NOBYTE_SHIFT)) & I3C_MIBIRULES_NOBYTE_MASK)
34745 /*! @} */
34746 
34747 /*! @name MINTSET - Controller Interrupt Set */
34748 /*! @{ */
34749 
34750 #define I3C_MINTSET_SLVSTART_MASK                (0x100U)
34751 #define I3C_MINTSET_SLVSTART_SHIFT               (8U)
34752 /*! SLVSTART - Target Start Interrupt Enable
34753  *  0b1..Enable
34754  *  0b0..Disable
34755  */
34756 #define I3C_MINTSET_SLVSTART(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_SLVSTART_SHIFT)) & I3C_MINTSET_SLVSTART_MASK)
34757 
34758 #define I3C_MINTSET_MCTRLDONE_MASK               (0x200U)
34759 #define I3C_MINTSET_MCTRLDONE_SHIFT              (9U)
34760 /*! MCTRLDONE - Controller Control Done Interrupt Enable
34761  *  0b1..Enable
34762  *  0b0..Disable
34763  */
34764 #define I3C_MINTSET_MCTRLDONE(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_MCTRLDONE_SHIFT)) & I3C_MINTSET_MCTRLDONE_MASK)
34765 
34766 #define I3C_MINTSET_COMPLETE_MASK                (0x400U)
34767 #define I3C_MINTSET_COMPLETE_SHIFT               (10U)
34768 /*! COMPLETE - Completed Message Interrupt Enable
34769  *  0b1..Enable
34770  *  0b0..Disable
34771  */
34772 #define I3C_MINTSET_COMPLETE(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_COMPLETE_SHIFT)) & I3C_MINTSET_COMPLETE_MASK)
34773 
34774 #define I3C_MINTSET_RXPEND_MASK                  (0x800U)
34775 #define I3C_MINTSET_RXPEND_SHIFT                 (11U)
34776 /*! RXPEND - Receive Pending Interrupt Enable */
34777 #define I3C_MINTSET_RXPEND(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_RXPEND_SHIFT)) & I3C_MINTSET_RXPEND_MASK)
34778 
34779 #define I3C_MINTSET_TXNOTFULL_MASK               (0x1000U)
34780 #define I3C_MINTSET_TXNOTFULL_SHIFT              (12U)
34781 /*! TXNOTFULL - Transmit Buffer/FIFO Not Full Interrupt Enable
34782  *  0b1..Enable
34783  *  0b0..Disable
34784  */
34785 #define I3C_MINTSET_TXNOTFULL(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_TXNOTFULL_SHIFT)) & I3C_MINTSET_TXNOTFULL_MASK)
34786 
34787 #define I3C_MINTSET_IBIWON_MASK                  (0x2000U)
34788 #define I3C_MINTSET_IBIWON_SHIFT                 (13U)
34789 /*! IBIWON - IBI Won Interrupt Enable
34790  *  0b1..Enable
34791  *  0b0..Disable
34792  */
34793 #define I3C_MINTSET_IBIWON(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_IBIWON_SHIFT)) & I3C_MINTSET_IBIWON_MASK)
34794 
34795 #define I3C_MINTSET_ERRWARN_MASK                 (0x8000U)
34796 #define I3C_MINTSET_ERRWARN_SHIFT                (15U)
34797 /*! ERRWARN - Error or Warning (ERRWARN) Interrupt Enable
34798  *  0b1..Enable
34799  *  0b0..Disable
34800  */
34801 #define I3C_MINTSET_ERRWARN(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_ERRWARN_SHIFT)) & I3C_MINTSET_ERRWARN_MASK)
34802 
34803 #define I3C_MINTSET_NOWMASTER_MASK               (0x80000U)
34804 #define I3C_MINTSET_NOWMASTER_SHIFT              (19U)
34805 /*! NOWMASTER - Now Controller Interrupt Enable
34806  *  0b1..Enable
34807  *  0b0..Disable
34808  */
34809 #define I3C_MINTSET_NOWMASTER(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_NOWMASTER_SHIFT)) & I3C_MINTSET_NOWMASTER_MASK)
34810 /*! @} */
34811 
34812 /*! @name MINTCLR - Controller Interrupt Clear */
34813 /*! @{ */
34814 
34815 #define I3C_MINTCLR_SLVSTART_MASK                (0x100U)
34816 #define I3C_MINTCLR_SLVSTART_SHIFT               (8U)
34817 /*! SLVSTART - SLVSTART Interrupt Enable Clear
34818  *  0b1..Interrupt enable cleared
34819  *  0b0..No effect
34820  *  0b0..No effect
34821  *  0b1..Clear the flag
34822  */
34823 #define I3C_MINTCLR_SLVSTART(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_SLVSTART_SHIFT)) & I3C_MINTCLR_SLVSTART_MASK)
34824 
34825 #define I3C_MINTCLR_MCTRLDONE_MASK               (0x200U)
34826 #define I3C_MINTCLR_MCTRLDONE_SHIFT              (9U)
34827 /*! MCTRLDONE - MCTRLDONE Interrupt Enable Clear
34828  *  0b1..Interrupt enable cleared
34829  *  0b0..No effect
34830  *  0b0..No effect
34831  *  0b1..Clear the flag
34832  */
34833 #define I3C_MINTCLR_MCTRLDONE(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_MCTRLDONE_SHIFT)) & I3C_MINTCLR_MCTRLDONE_MASK)
34834 
34835 #define I3C_MINTCLR_COMPLETE_MASK                (0x400U)
34836 #define I3C_MINTCLR_COMPLETE_SHIFT               (10U)
34837 /*! COMPLETE - COMPLETE Interrupt Enable Clear
34838  *  0b1..Interrupt enable cleared
34839  *  0b0..No effect
34840  *  0b0..No effect
34841  *  0b1..Clear the flag
34842  */
34843 #define I3C_MINTCLR_COMPLETE(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_COMPLETE_SHIFT)) & I3C_MINTCLR_COMPLETE_MASK)
34844 
34845 #define I3C_MINTCLR_RXPEND_MASK                  (0x800U)
34846 #define I3C_MINTCLR_RXPEND_SHIFT                 (11U)
34847 /*! RXPEND - RXPEND Interrupt Enable Clear
34848  *  0b1..Interrupt enable cleared
34849  *  0b0..No effect
34850  *  0b0..No effect
34851  *  0b1..Clear the flag
34852  */
34853 #define I3C_MINTCLR_RXPEND(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_RXPEND_SHIFT)) & I3C_MINTCLR_RXPEND_MASK)
34854 
34855 #define I3C_MINTCLR_TXNOTFULL_MASK               (0x1000U)
34856 #define I3C_MINTCLR_TXNOTFULL_SHIFT              (12U)
34857 /*! TXNOTFULL - TXNOTFULL Interrupt Enable Clear
34858  *  0b1..Interrupt enable cleared
34859  *  0b0..No effect
34860  *  0b0..No effect
34861  *  0b1..Clear the flag
34862  */
34863 #define I3C_MINTCLR_TXNOTFULL(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_TXNOTFULL_SHIFT)) & I3C_MINTCLR_TXNOTFULL_MASK)
34864 
34865 #define I3C_MINTCLR_IBIWON_MASK                  (0x2000U)
34866 #define I3C_MINTCLR_IBIWON_SHIFT                 (13U)
34867 /*! IBIWON - IBIWON Interrupt Enable Clear
34868  *  0b1..Interrupt enable cleared
34869  *  0b0..No effect
34870  *  0b0..No effect
34871  *  0b1..Clear the flag
34872  */
34873 #define I3C_MINTCLR_IBIWON(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_IBIWON_SHIFT)) & I3C_MINTCLR_IBIWON_MASK)
34874 
34875 #define I3C_MINTCLR_ERRWARN_MASK                 (0x8000U)
34876 #define I3C_MINTCLR_ERRWARN_SHIFT                (15U)
34877 /*! ERRWARN - ERRWARN Interrupt Enable Clear
34878  *  0b1..Interrupt enable cleared
34879  *  0b0..No effect
34880  *  0b0..No effect
34881  *  0b1..Clear the flag
34882  */
34883 #define I3C_MINTCLR_ERRWARN(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_ERRWARN_SHIFT)) & I3C_MINTCLR_ERRWARN_MASK)
34884 
34885 #define I3C_MINTCLR_NOWMASTER_MASK               (0x80000U)
34886 #define I3C_MINTCLR_NOWMASTER_SHIFT              (19U)
34887 /*! NOWMASTER - NOWCONTROLLER Interrupt Enable Clear
34888  *  0b1..Interrupt enable cleared
34889  *  0b0..No effect
34890  *  0b0..No effect
34891  *  0b1..Clear the flag
34892  */
34893 #define I3C_MINTCLR_NOWMASTER(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_NOWMASTER_SHIFT)) & I3C_MINTCLR_NOWMASTER_MASK)
34894 /*! @} */
34895 
34896 /*! @name MINTMASKED - Controller Interrupt Mask */
34897 /*! @{ */
34898 
34899 #define I3C_MINTMASKED_SLVSTART_MASK             (0x100U)
34900 #define I3C_MINTMASKED_SLVSTART_SHIFT            (8U)
34901 /*! SLVSTART - SLVSTART Interrupt Mask
34902  *  0b1..Enabled
34903  *  0b0..Disabled
34904  */
34905 #define I3C_MINTMASKED_SLVSTART(x)               (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_SLVSTART_SHIFT)) & I3C_MINTMASKED_SLVSTART_MASK)
34906 
34907 #define I3C_MINTMASKED_MCTRLDONE_MASK            (0x200U)
34908 #define I3C_MINTMASKED_MCTRLDONE_SHIFT           (9U)
34909 /*! MCTRLDONE - MCTRLDONE Interrupt Mask
34910  *  0b1..Enabled
34911  *  0b0..Disabled
34912  */
34913 #define I3C_MINTMASKED_MCTRLDONE(x)              (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_MCTRLDONE_SHIFT)) & I3C_MINTMASKED_MCTRLDONE_MASK)
34914 
34915 #define I3C_MINTMASKED_COMPLETE_MASK             (0x400U)
34916 #define I3C_MINTMASKED_COMPLETE_SHIFT            (10U)
34917 /*! COMPLETE - COMPLETE Interrupt Mask
34918  *  0b1..Enabled
34919  *  0b0..Disabled
34920  */
34921 #define I3C_MINTMASKED_COMPLETE(x)               (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_COMPLETE_SHIFT)) & I3C_MINTMASKED_COMPLETE_MASK)
34922 
34923 #define I3C_MINTMASKED_RXPEND_MASK               (0x800U)
34924 #define I3C_MINTMASKED_RXPEND_SHIFT              (11U)
34925 /*! RXPEND - RXPEND Interrupt Mask */
34926 #define I3C_MINTMASKED_RXPEND(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_RXPEND_SHIFT)) & I3C_MINTMASKED_RXPEND_MASK)
34927 
34928 #define I3C_MINTMASKED_TXNOTFULL_MASK            (0x1000U)
34929 #define I3C_MINTMASKED_TXNOTFULL_SHIFT           (12U)
34930 /*! TXNOTFULL - TXNOTFULL Interrupt Mask
34931  *  0b1..Enabled
34932  *  0b0..Disabled
34933  */
34934 #define I3C_MINTMASKED_TXNOTFULL(x)              (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_TXNOTFULL_SHIFT)) & I3C_MINTMASKED_TXNOTFULL_MASK)
34935 
34936 #define I3C_MINTMASKED_IBIWON_MASK               (0x2000U)
34937 #define I3C_MINTMASKED_IBIWON_SHIFT              (13U)
34938 /*! IBIWON - IBIWON Interrupt Mask
34939  *  0b1..Enabled
34940  *  0b0..Disabled
34941  */
34942 #define I3C_MINTMASKED_IBIWON(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_IBIWON_SHIFT)) & I3C_MINTMASKED_IBIWON_MASK)
34943 
34944 #define I3C_MINTMASKED_ERRWARN_MASK              (0x8000U)
34945 #define I3C_MINTMASKED_ERRWARN_SHIFT             (15U)
34946 /*! ERRWARN - ERRWARN Interrupt Mask
34947  *  0b1..Enabled
34948  *  0b0..Disabled
34949  */
34950 #define I3C_MINTMASKED_ERRWARN(x)                (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_ERRWARN_SHIFT)) & I3C_MINTMASKED_ERRWARN_MASK)
34951 
34952 #define I3C_MINTMASKED_NOWMASTER_MASK            (0x80000U)
34953 #define I3C_MINTMASKED_NOWMASTER_SHIFT           (19U)
34954 /*! NOWMASTER - NOWCONTROLLER Interrupt Mask
34955  *  0b1..Enabled
34956  *  0b0..Disabled
34957  */
34958 #define I3C_MINTMASKED_NOWMASTER(x)              (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_NOWMASTER_SHIFT)) & I3C_MINTMASKED_NOWMASTER_MASK)
34959 /*! @} */
34960 
34961 /*! @name MERRWARN - Controller Errors and Warnings */
34962 /*! @{ */
34963 
34964 #define I3C_MERRWARN_NACK_MASK                   (0x4U)
34965 #define I3C_MERRWARN_NACK_SHIFT                  (2U)
34966 /*! NACK - Not Acknowledge Error
34967  *  0b1..Error
34968  *  0b0..No error
34969  *  0b0..No effect
34970  *  0b1..Clear the flag
34971  */
34972 #define I3C_MERRWARN_NACK(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_NACK_SHIFT)) & I3C_MERRWARN_NACK_MASK)
34973 
34974 #define I3C_MERRWARN_WRABT_MASK                  (0x8U)
34975 #define I3C_MERRWARN_WRABT_SHIFT                 (3U)
34976 /*! WRABT - Write Abort Error
34977  *  0b1..Error
34978  *  0b0..No error
34979  *  0b0..No effect
34980  *  0b1..Clear the flag
34981  */
34982 #define I3C_MERRWARN_WRABT(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_WRABT_SHIFT)) & I3C_MERRWARN_WRABT_MASK)
34983 
34984 #define I3C_MERRWARN_HPAR_MASK                   (0x200U)
34985 #define I3C_MERRWARN_HPAR_SHIFT                  (9U)
34986 /*! HPAR - High Data Rate Parity
34987  *  0b1..Error
34988  *  0b0..No error
34989  *  0b0..No effect
34990  *  0b1..Clear the flag
34991  */
34992 #define I3C_MERRWARN_HPAR(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_HPAR_SHIFT)) & I3C_MERRWARN_HPAR_MASK)
34993 
34994 #define I3C_MERRWARN_HCRC_MASK                   (0x400U)
34995 #define I3C_MERRWARN_HCRC_SHIFT                  (10U)
34996 /*! HCRC - High Data Rate CRC Error
34997  *  0b1..Error
34998  *  0b0..No error
34999  *  0b0..No effect
35000  *  0b1..Clear the flag
35001  */
35002 #define I3C_MERRWARN_HCRC(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_HCRC_SHIFT)) & I3C_MERRWARN_HCRC_MASK)
35003 
35004 #define I3C_MERRWARN_OREAD_MASK                  (0x10000U)
35005 #define I3C_MERRWARN_OREAD_SHIFT                 (16U)
35006 /*! OREAD - Overread Error
35007  *  0b1..Error
35008  *  0b0..No error
35009  *  0b0..No effect
35010  *  0b1..Clear the flag
35011  */
35012 #define I3C_MERRWARN_OREAD(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_OREAD_SHIFT)) & I3C_MERRWARN_OREAD_MASK)
35013 
35014 #define I3C_MERRWARN_OWRITE_MASK                 (0x20000U)
35015 #define I3C_MERRWARN_OWRITE_SHIFT                (17U)
35016 /*! OWRITE - Overwrite Error
35017  *  0b1..Error
35018  *  0b0..No error
35019  *  0b0..No effect
35020  *  0b1..Clear the flag
35021  */
35022 #define I3C_MERRWARN_OWRITE(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_OWRITE_SHIFT)) & I3C_MERRWARN_OWRITE_MASK)
35023 
35024 #define I3C_MERRWARN_MSGERR_MASK                 (0x40000U)
35025 #define I3C_MERRWARN_MSGERR_SHIFT                (18U)
35026 /*! MSGERR - Message Error
35027  *  0b1..Error
35028  *  0b0..No error
35029  *  0b0..No effect
35030  *  0b1..Clear the flag
35031  */
35032 #define I3C_MERRWARN_MSGERR(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_MSGERR_SHIFT)) & I3C_MERRWARN_MSGERR_MASK)
35033 
35034 #define I3C_MERRWARN_INVREQ_MASK                 (0x80000U)
35035 #define I3C_MERRWARN_INVREQ_SHIFT                (19U)
35036 /*! INVREQ - Invalid Request Error
35037  *  0b1..Error
35038  *  0b0..No error
35039  *  0b0..No effect
35040  *  0b1..Clear the flag
35041  */
35042 #define I3C_MERRWARN_INVREQ(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_INVREQ_SHIFT)) & I3C_MERRWARN_INVREQ_MASK)
35043 
35044 #define I3C_MERRWARN_TIMEOUT_MASK                (0x100000U)
35045 #define I3C_MERRWARN_TIMEOUT_SHIFT               (20U)
35046 /*! TIMEOUT - Timeout Error
35047  *  0b1..Error
35048  *  0b0..No error
35049  *  0b0..No effect
35050  *  0b1..Clear the flag
35051  */
35052 #define I3C_MERRWARN_TIMEOUT(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_TIMEOUT_SHIFT)) & I3C_MERRWARN_TIMEOUT_MASK)
35053 /*! @} */
35054 
35055 /*! @name MDMACTRL - Controller DMA Control */
35056 /*! @{ */
35057 
35058 #define I3C_MDMACTRL_DMAFB_MASK                  (0x3U)
35059 #define I3C_MDMACTRL_DMAFB_SHIFT                 (0U)
35060 /*! DMAFB - DMA from Bus
35061  *  0b00..DMA not used
35062  *  0b01..Enable DMA for one frame
35063  *  0b10..Enable DMA until DMA is turned off
35064  *  0b11..
35065  */
35066 #define I3C_MDMACTRL_DMAFB(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MDMACTRL_DMAFB_SHIFT)) & I3C_MDMACTRL_DMAFB_MASK)
35067 
35068 #define I3C_MDMACTRL_DMATB_MASK                  (0xCU)
35069 #define I3C_MDMACTRL_DMATB_SHIFT                 (2U)
35070 /*! DMATB - DMA to Bus
35071  *  0b00..DMA not used
35072  *  0b01..Enable DMA for one frame (ended by DMA or terminated)
35073  *  0b10..Enable DMA until DMA is turned off
35074  *  0b11..
35075  */
35076 #define I3C_MDMACTRL_DMATB(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MDMACTRL_DMATB_SHIFT)) & I3C_MDMACTRL_DMATB_MASK)
35077 
35078 #define I3C_MDMACTRL_DMAWIDTH_MASK               (0x30U)
35079 #define I3C_MDMACTRL_DMAWIDTH_SHIFT              (4U)
35080 /*! DMAWIDTH - DMA Width
35081  *  0b00, 0b01..Byte
35082  *  0b10..Halfword (16 bits)
35083  *  0b11..
35084  */
35085 #define I3C_MDMACTRL_DMAWIDTH(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MDMACTRL_DMAWIDTH_SHIFT)) & I3C_MDMACTRL_DMAWIDTH_MASK)
35086 /*! @} */
35087 
35088 /*! @name MDATACTRL - Controller Data Control */
35089 /*! @{ */
35090 
35091 #define I3C_MDATACTRL_FLUSHTB_MASK               (0x1U)
35092 #define I3C_MDATACTRL_FLUSHTB_SHIFT              (0U)
35093 /*! FLUSHTB - Flush To-Bus Buffer or FIFO
35094  *  0b1..Flush the buffer
35095  *  0b0..No action
35096  */
35097 #define I3C_MDATACTRL_FLUSHTB(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_FLUSHTB_SHIFT)) & I3C_MDATACTRL_FLUSHTB_MASK)
35098 
35099 #define I3C_MDATACTRL_FLUSHFB_MASK               (0x2U)
35100 #define I3C_MDATACTRL_FLUSHFB_SHIFT              (1U)
35101 /*! FLUSHFB - Flush From-Bus Buffer or FIFO
35102  *  0b1..Flush the buffer
35103  *  0b0..No action
35104  */
35105 #define I3C_MDATACTRL_FLUSHFB(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_FLUSHFB_SHIFT)) & I3C_MDATACTRL_FLUSHFB_MASK)
35106 
35107 #define I3C_MDATACTRL_UNLOCK_MASK                (0x8U)
35108 #define I3C_MDATACTRL_UNLOCK_SHIFT               (3U)
35109 /*! UNLOCK - Unlock
35110  *  0b0..Locked
35111  *  0b1..Unlocked
35112  */
35113 #define I3C_MDATACTRL_UNLOCK(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_UNLOCK_SHIFT)) & I3C_MDATACTRL_UNLOCK_MASK)
35114 
35115 #define I3C_MDATACTRL_TXTRIG_MASK                (0x30U)
35116 #define I3C_MDATACTRL_TXTRIG_SHIFT               (4U)
35117 /*! TXTRIG - Transmit Trigger Level
35118  *  0b00..Trigger when empty
35119  *  0b01..Trigger when 1/4 full or less
35120  *  0b10..Trigger when 1/2 full or less
35121  *  0b11..Trigger when 1 less than full or less (default)
35122  */
35123 #define I3C_MDATACTRL_TXTRIG(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_TXTRIG_SHIFT)) & I3C_MDATACTRL_TXTRIG_MASK)
35124 
35125 #define I3C_MDATACTRL_RXTRIG_MASK                (0xC0U)
35126 #define I3C_MDATACTRL_RXTRIG_SHIFT               (6U)
35127 /*! RXTRIG - Receive Trigger Level
35128  *  0b00..Trigger when not empty
35129  *  0b01..Trigger when 1/4 full or more
35130  *  0b10..Trigger when 1/2 full or more
35131  *  0b11..Trigger when 3/4 full or more
35132  */
35133 #define I3C_MDATACTRL_RXTRIG(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_RXTRIG_SHIFT)) & I3C_MDATACTRL_RXTRIG_MASK)
35134 
35135 #define I3C_MDATACTRL_TXCOUNT_MASK               (0x1F0000U)
35136 #define I3C_MDATACTRL_TXCOUNT_SHIFT              (16U)
35137 /*! TXCOUNT - Transmit Byte Count */
35138 #define I3C_MDATACTRL_TXCOUNT(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_TXCOUNT_SHIFT)) & I3C_MDATACTRL_TXCOUNT_MASK)
35139 
35140 #define I3C_MDATACTRL_RXCOUNT_MASK               (0x1F000000U)
35141 #define I3C_MDATACTRL_RXCOUNT_SHIFT              (24U)
35142 /*! RXCOUNT - Receive Byte Count */
35143 #define I3C_MDATACTRL_RXCOUNT(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_RXCOUNT_SHIFT)) & I3C_MDATACTRL_RXCOUNT_MASK)
35144 
35145 #define I3C_MDATACTRL_TXFULL_MASK                (0x40000000U)
35146 #define I3C_MDATACTRL_TXFULL_SHIFT               (30U)
35147 /*! TXFULL - Transmit is Full
35148  *  0b0..Not full
35149  *  0b1..Full
35150  */
35151 #define I3C_MDATACTRL_TXFULL(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_TXFULL_SHIFT)) & I3C_MDATACTRL_TXFULL_MASK)
35152 
35153 #define I3C_MDATACTRL_RXEMPTY_MASK               (0x80000000U)
35154 #define I3C_MDATACTRL_RXEMPTY_SHIFT              (31U)
35155 /*! RXEMPTY - Receive is Empty
35156  *  0b0..Not empty
35157  *  0b1..Empty
35158  */
35159 #define I3C_MDATACTRL_RXEMPTY(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_RXEMPTY_SHIFT)) & I3C_MDATACTRL_RXEMPTY_MASK)
35160 /*! @} */
35161 
35162 /*! @name MWDATAB - Controller Write Data Byte */
35163 /*! @{ */
35164 
35165 #define I3C_MWDATAB_VALUE_MASK                   (0xFFU)
35166 #define I3C_MWDATAB_VALUE_SHIFT                  (0U)
35167 /*! VALUE - Data Byte */
35168 #define I3C_MWDATAB_VALUE(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB_VALUE_SHIFT)) & I3C_MWDATAB_VALUE_MASK)
35169 
35170 #define I3C_MWDATAB_END_MASK                     (0x100U)
35171 #define I3C_MWDATAB_END_SHIFT                    (8U)
35172 /*! END - End of Message
35173  *  0b0..Not the end
35174  *  0b1..End
35175  */
35176 #define I3C_MWDATAB_END(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB_END_SHIFT)) & I3C_MWDATAB_END_MASK)
35177 
35178 #define I3C_MWDATAB_END_ALSO_MASK                (0x10000U)
35179 #define I3C_MWDATAB_END_ALSO_SHIFT               (16U)
35180 /*! END_ALSO - End of Message ALSO
35181  *  0b0..Not the end
35182  *  0b1..End
35183  */
35184 #define I3C_MWDATAB_END_ALSO(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB_END_ALSO_SHIFT)) & I3C_MWDATAB_END_ALSO_MASK)
35185 /*! @} */
35186 
35187 /*! @name MWDATABE - Controller Write Data Byte End */
35188 /*! @{ */
35189 
35190 #define I3C_MWDATABE_VALUE_MASK                  (0xFFU)
35191 #define I3C_MWDATABE_VALUE_SHIFT                 (0U)
35192 /*! VALUE - Data */
35193 #define I3C_MWDATABE_VALUE(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MWDATABE_VALUE_SHIFT)) & I3C_MWDATABE_VALUE_MASK)
35194 /*! @} */
35195 
35196 /*! @name MWDATAH - Controller Write Data Halfword */
35197 /*! @{ */
35198 
35199 #define I3C_MWDATAH_DATA0_MASK                   (0xFFU)
35200 #define I3C_MWDATAH_DATA0_SHIFT                  (0U)
35201 /*! DATA0 - Data Byte 0 */
35202 #define I3C_MWDATAH_DATA0(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAH_DATA0_SHIFT)) & I3C_MWDATAH_DATA0_MASK)
35203 
35204 #define I3C_MWDATAH_DATA1_MASK                   (0xFF00U)
35205 #define I3C_MWDATAH_DATA1_SHIFT                  (8U)
35206 /*! DATA1 - Data Byte 1 */
35207 #define I3C_MWDATAH_DATA1(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAH_DATA1_SHIFT)) & I3C_MWDATAH_DATA1_MASK)
35208 
35209 #define I3C_MWDATAH_END_MASK                     (0x10000U)
35210 #define I3C_MWDATAH_END_SHIFT                    (16U)
35211 /*! END - End of Message
35212  *  0b0..Not the end
35213  *  0b1..End
35214  */
35215 #define I3C_MWDATAH_END(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAH_END_SHIFT)) & I3C_MWDATAH_END_MASK)
35216 /*! @} */
35217 
35218 /*! @name MWDATAHE - Controller Write Data Halfword End */
35219 /*! @{ */
35220 
35221 #define I3C_MWDATAHE_DATA0_MASK                  (0xFFU)
35222 #define I3C_MWDATAHE_DATA0_SHIFT                 (0U)
35223 /*! DATA0 - Data Byte 0 */
35224 #define I3C_MWDATAHE_DATA0(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAHE_DATA0_SHIFT)) & I3C_MWDATAHE_DATA0_MASK)
35225 
35226 #define I3C_MWDATAHE_DATA1_MASK                  (0xFF00U)
35227 #define I3C_MWDATAHE_DATA1_SHIFT                 (8U)
35228 /*! DATA1 - Data Byte 1 */
35229 #define I3C_MWDATAHE_DATA1(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAHE_DATA1_SHIFT)) & I3C_MWDATAHE_DATA1_MASK)
35230 /*! @} */
35231 
35232 /*! @name MRDATAB - Controller Read Data Byte */
35233 /*! @{ */
35234 
35235 #define I3C_MRDATAB_VALUE_MASK                   (0xFFU)
35236 #define I3C_MRDATAB_VALUE_SHIFT                  (0U)
35237 /*! VALUE - Value */
35238 #define I3C_MRDATAB_VALUE(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MRDATAB_VALUE_SHIFT)) & I3C_MRDATAB_VALUE_MASK)
35239 /*! @} */
35240 
35241 /*! @name MRDATAH - Controller Read Data Halfword */
35242 /*! @{ */
35243 
35244 #define I3C_MRDATAH_LSB_MASK                     (0xFFU)
35245 #define I3C_MRDATAH_LSB_SHIFT                    (0U)
35246 /*! LSB - Low Byte */
35247 #define I3C_MRDATAH_LSB(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_MRDATAH_LSB_SHIFT)) & I3C_MRDATAH_LSB_MASK)
35248 
35249 #define I3C_MRDATAH_MSB_MASK                     (0xFF00U)
35250 #define I3C_MRDATAH_MSB_SHIFT                    (8U)
35251 /*! MSB - High Byte */
35252 #define I3C_MRDATAH_MSB(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_MRDATAH_MSB_SHIFT)) & I3C_MRDATAH_MSB_MASK)
35253 /*! @} */
35254 
35255 /*! @name MWDATAB1 - Controller Write Byte Data 1 (to Bus) */
35256 /*! @{ */
35257 
35258 #define I3C_MWDATAB1_VALUE_MASK                  (0xFFU)
35259 #define I3C_MWDATAB1_VALUE_SHIFT                 (0U)
35260 /*! VALUE - Value */
35261 #define I3C_MWDATAB1_VALUE(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB1_VALUE_SHIFT)) & I3C_MWDATAB1_VALUE_MASK)
35262 /*! @} */
35263 
35264 /*! @name MWMSG_SDR_CONTROL - Controller Write Message Control in SDR mode */
35265 /*! @{ */
35266 
35267 #define I3C_MWMSG_SDR_CONTROL_DIR_MASK           (0x1U)
35268 #define I3C_MWMSG_SDR_CONTROL_DIR_SHIFT          (0U)
35269 /*! DIR - Direction
35270  *  0b0..Write
35271  *  0b1..Read
35272  */
35273 #define I3C_MWMSG_SDR_CONTROL_DIR(x)             (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_DIR_SHIFT)) & I3C_MWMSG_SDR_CONTROL_DIR_MASK)
35274 
35275 #define I3C_MWMSG_SDR_CONTROL_ADDR_MASK          (0xFEU)
35276 #define I3C_MWMSG_SDR_CONTROL_ADDR_SHIFT         (1U)
35277 /*! ADDR - Address */
35278 #define I3C_MWMSG_SDR_CONTROL_ADDR(x)            (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_ADDR_SHIFT)) & I3C_MWMSG_SDR_CONTROL_ADDR_MASK)
35279 
35280 #define I3C_MWMSG_SDR_CONTROL_END_MASK           (0x100U)
35281 #define I3C_MWMSG_SDR_CONTROL_END_SHIFT          (8U)
35282 /*! END - End of SDR Message
35283  *  0b0..Not the end
35284  *  0b1..End
35285  */
35286 #define I3C_MWMSG_SDR_CONTROL_END(x)             (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_END_SHIFT)) & I3C_MWMSG_SDR_CONTROL_END_MASK)
35287 
35288 #define I3C_MWMSG_SDR_CONTROL_I2C_MASK           (0x400U)
35289 #define I3C_MWMSG_SDR_CONTROL_I2C_SHIFT          (10U)
35290 /*! I2C - I2C
35291  *  0b0..I3C message
35292  *  0b1..I2C message
35293  */
35294 #define I3C_MWMSG_SDR_CONTROL_I2C(x)             (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_I2C_SHIFT)) & I3C_MWMSG_SDR_CONTROL_I2C_MASK)
35295 
35296 #define I3C_MWMSG_SDR_CONTROL_LEN_MASK           (0xF800U)
35297 #define I3C_MWMSG_SDR_CONTROL_LEN_SHIFT          (11U)
35298 /*! LEN - Length */
35299 #define I3C_MWMSG_SDR_CONTROL_LEN(x)             (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_LEN_SHIFT)) & I3C_MWMSG_SDR_CONTROL_LEN_MASK)
35300 /*! @} */
35301 
35302 /*! @name MWMSG_SDR_DATA - Controller Write Message Data in SDR mode */
35303 /*! @{ */
35304 
35305 #define I3C_MWMSG_SDR_DATA_DATA16B_MASK          (0xFFFFU)
35306 #define I3C_MWMSG_SDR_DATA_DATA16B_SHIFT         (0U)
35307 /*! DATA16B - Data */
35308 #define I3C_MWMSG_SDR_DATA_DATA16B(x)            (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_DATA_DATA16B_SHIFT)) & I3C_MWMSG_SDR_DATA_DATA16B_MASK)
35309 /*! @} */
35310 
35311 /*! @name MRMSG_SDR - Controller Read Message in SDR mode */
35312 /*! @{ */
35313 
35314 #define I3C_MRMSG_SDR_DATA_MASK                  (0xFFFFU)
35315 #define I3C_MRMSG_SDR_DATA_SHIFT                 (0U)
35316 /*! DATA - Data */
35317 #define I3C_MRMSG_SDR_DATA(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MRMSG_SDR_DATA_SHIFT)) & I3C_MRMSG_SDR_DATA_MASK)
35318 /*! @} */
35319 
35320 /*! @name MWMSG_DDR_CONTROL - Controller Write Message in DDR mode: First Control Word */
35321 /*! @{ */
35322 
35323 #define I3C_MWMSG_DDR_CONTROL_ADDRCMD_MASK       (0xFFFFU)
35324 #define I3C_MWMSG_DDR_CONTROL_ADDRCMD_SHIFT      (0U)
35325 /*! ADDRCMD - Address Command */
35326 #define I3C_MWMSG_DDR_CONTROL_ADDRCMD(x)         (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_CONTROL_ADDRCMD_SHIFT)) & I3C_MWMSG_DDR_CONTROL_ADDRCMD_MASK)
35327 /*! @} */
35328 
35329 /*! @name MWMSG_DDR_CONTROL2 - Controller Write Message in DDR Mode Control 2 */
35330 /*! @{ */
35331 
35332 #define I3C_MWMSG_DDR_CONTROL2_LEN_MASK          (0x3FFU)
35333 #define I3C_MWMSG_DDR_CONTROL2_LEN_SHIFT         (0U)
35334 /*! LEN - Length of Message */
35335 #define I3C_MWMSG_DDR_CONTROL2_LEN(x)            (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_CONTROL2_LEN_SHIFT)) & I3C_MWMSG_DDR_CONTROL2_LEN_MASK)
35336 
35337 #define I3C_MWMSG_DDR_CONTROL2_END_MASK          (0x4000U)
35338 #define I3C_MWMSG_DDR_CONTROL2_END_SHIFT         (14U)
35339 /*! END - End of Message
35340  *  0b1..End
35341  *  0b0..Not the end
35342  */
35343 #define I3C_MWMSG_DDR_CONTROL2_END(x)            (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_CONTROL2_END_SHIFT)) & I3C_MWMSG_DDR_CONTROL2_END_MASK)
35344 /*! @} */
35345 
35346 /*! @name MWMSG_DDR_DATA - Controller Write Message Data in DDR mode */
35347 /*! @{ */
35348 
35349 #define I3C_MWMSG_DDR_DATA_DATA16B_MASK          (0xFFFFU)
35350 #define I3C_MWMSG_DDR_DATA_DATA16B_SHIFT         (0U)
35351 /*! DATA16B - Data */
35352 #define I3C_MWMSG_DDR_DATA_DATA16B(x)            (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_DATA_DATA16B_SHIFT)) & I3C_MWMSG_DDR_DATA_DATA16B_MASK)
35353 /*! @} */
35354 
35355 /*! @name MRMSG_DDR - Controller Read Message in DDR mode */
35356 /*! @{ */
35357 
35358 #define I3C_MRMSG_DDR_DATA_MASK                  (0xFFFFU)
35359 #define I3C_MRMSG_DDR_DATA_SHIFT                 (0U)
35360 /*! DATA - Data */
35361 #define I3C_MRMSG_DDR_DATA(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MRMSG_DDR_DATA_SHIFT)) & I3C_MRMSG_DDR_DATA_MASK)
35362 /*! @} */
35363 
35364 /*! @name MDYNADDR - Controller Dynamic Address */
35365 /*! @{ */
35366 
35367 #define I3C_MDYNADDR_DAVALID_MASK                (0x1U)
35368 #define I3C_MDYNADDR_DAVALID_SHIFT               (0U)
35369 /*! DAVALID - Dynamic Address Valid
35370  *  0b1..Valid DA assigned
35371  *  0b0..No valid DA assigned
35372  */
35373 #define I3C_MDYNADDR_DAVALID(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MDYNADDR_DAVALID_SHIFT)) & I3C_MDYNADDR_DAVALID_MASK)
35374 
35375 #define I3C_MDYNADDR_DADDR_MASK                  (0xFEU)
35376 #define I3C_MDYNADDR_DADDR_SHIFT                 (1U)
35377 /*! DADDR - Dynamic Address */
35378 #define I3C_MDYNADDR_DADDR(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MDYNADDR_DADDR_SHIFT)) & I3C_MDYNADDR_DADDR_MASK)
35379 /*! @} */
35380 
35381 /*! @name SMAPCTRL0 - Map Feature Control 0 */
35382 /*! @{ */
35383 
35384 #define I3C_SMAPCTRL0_ENA_MASK                   (0x1U)
35385 #define I3C_SMAPCTRL0_ENA_SHIFT                  (0U)
35386 /*! ENA - Enable Primary Dynamic Address
35387  *  0b0..Disabled
35388  *  0b1..Enabled
35389  */
35390 #define I3C_SMAPCTRL0_ENA(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL0_ENA_SHIFT)) & I3C_SMAPCTRL0_ENA_MASK)
35391 
35392 #define I3C_SMAPCTRL0_DA_MASK                    (0xFEU)
35393 #define I3C_SMAPCTRL0_DA_SHIFT                   (1U)
35394 /*! DA - Dynamic Address */
35395 #define I3C_SMAPCTRL0_DA(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL0_DA_SHIFT)) & I3C_SMAPCTRL0_DA_MASK)
35396 
35397 #define I3C_SMAPCTRL0_CAUSE_MASK                 (0x700U)
35398 #define I3C_SMAPCTRL0_CAUSE_SHIFT                (8U)
35399 /*! CAUSE - Cause
35400  *  0b000..No information (this value occurs when not configured to write DA)
35401  *  0b001..Set using ENTDAA
35402  *  0b010..Set using SETDASA, SETAASA, or SETNEWDA
35403  *  0b011..Cleared using RSTDAA
35404  *  0b100..Auto MAP change happened last
35405  *  *..
35406  */
35407 #define I3C_SMAPCTRL0_CAUSE(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL0_CAUSE_SHIFT)) & I3C_SMAPCTRL0_CAUSE_MASK)
35408 /*! @} */
35409 
35410 /*! @name IBIEXT1 - Extended IBI Data 1 */
35411 /*! @{ */
35412 
35413 #define I3C_IBIEXT1_CNT_MASK                     (0x7U)
35414 #define I3C_IBIEXT1_CNT_SHIFT                    (0U)
35415 /*! CNT - Count */
35416 #define I3C_IBIEXT1_CNT(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_CNT_SHIFT)) & I3C_IBIEXT1_CNT_MASK)
35417 
35418 #define I3C_IBIEXT1_MAX_MASK                     (0x70U)
35419 #define I3C_IBIEXT1_MAX_SHIFT                    (4U)
35420 /*! MAX - Maximum */
35421 #define I3C_IBIEXT1_MAX(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_MAX_SHIFT)) & I3C_IBIEXT1_MAX_MASK)
35422 
35423 #define I3C_IBIEXT1_EXT1_MASK                    (0xFF00U)
35424 #define I3C_IBIEXT1_EXT1_SHIFT                   (8U)
35425 /*! EXT1 - Extra Byte 1 */
35426 #define I3C_IBIEXT1_EXT1(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_EXT1_SHIFT)) & I3C_IBIEXT1_EXT1_MASK)
35427 
35428 #define I3C_IBIEXT1_EXT2_MASK                    (0xFF0000U)
35429 #define I3C_IBIEXT1_EXT2_SHIFT                   (16U)
35430 /*! EXT2 - Extra Byte 2 */
35431 #define I3C_IBIEXT1_EXT2(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_EXT2_SHIFT)) & I3C_IBIEXT1_EXT2_MASK)
35432 
35433 #define I3C_IBIEXT1_EXT3_MASK                    (0xFF000000U)
35434 #define I3C_IBIEXT1_EXT3_SHIFT                   (24U)
35435 /*! EXT3 - Extra Byte 3 */
35436 #define I3C_IBIEXT1_EXT3(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_EXT3_SHIFT)) & I3C_IBIEXT1_EXT3_MASK)
35437 /*! @} */
35438 
35439 /*! @name IBIEXT2 - Extended IBI Data 2 */
35440 /*! @{ */
35441 
35442 #define I3C_IBIEXT2_EXT4_MASK                    (0xFFU)
35443 #define I3C_IBIEXT2_EXT4_SHIFT                   (0U)
35444 /*! EXT4 - Extra Byte 4 */
35445 #define I3C_IBIEXT2_EXT4(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT2_EXT4_SHIFT)) & I3C_IBIEXT2_EXT4_MASK)
35446 
35447 #define I3C_IBIEXT2_EXT5_MASK                    (0xFF00U)
35448 #define I3C_IBIEXT2_EXT5_SHIFT                   (8U)
35449 /*! EXT5 - Extra Byte 5 */
35450 #define I3C_IBIEXT2_EXT5(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT2_EXT5_SHIFT)) & I3C_IBIEXT2_EXT5_MASK)
35451 
35452 #define I3C_IBIEXT2_EXT6_MASK                    (0xFF0000U)
35453 #define I3C_IBIEXT2_EXT6_SHIFT                   (16U)
35454 /*! EXT6 - Extra Byte 6 */
35455 #define I3C_IBIEXT2_EXT6(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT2_EXT6_SHIFT)) & I3C_IBIEXT2_EXT6_MASK)
35456 
35457 #define I3C_IBIEXT2_EXT7_MASK                    (0xFF000000U)
35458 #define I3C_IBIEXT2_EXT7_SHIFT                   (24U)
35459 /*! EXT7 - Extra Byte 7 */
35460 #define I3C_IBIEXT2_EXT7(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT2_EXT7_SHIFT)) & I3C_IBIEXT2_EXT7_MASK)
35461 /*! @} */
35462 
35463 /*! @name SID - Target Module ID */
35464 /*! @{ */
35465 
35466 #define I3C_SID_ID_MASK                          (0xFFFFFFFFU)
35467 #define I3C_SID_ID_SHIFT                         (0U)
35468 /*! ID - ID */
35469 #define I3C_SID_ID(x)                            (((uint32_t)(((uint32_t)(x)) << I3C_SID_ID_SHIFT)) & I3C_SID_ID_MASK)
35470 /*! @} */
35471 
35472 
35473 /*!
35474  * @}
35475  */ /* end of group I3C_Register_Masks */
35476 
35477 
35478 /* I3C - Peripheral instance base addresses */
35479 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
35480   /** Peripheral I3C0 base address */
35481   #define I3C0_BASE                                (0x50021000u)
35482   /** Peripheral I3C0 base address */
35483   #define I3C0_BASE_NS                             (0x40021000u)
35484   /** Peripheral I3C0 base pointer */
35485   #define I3C0                                     ((I3C_Type *)I3C0_BASE)
35486   /** Peripheral I3C0 base pointer */
35487   #define I3C0_NS                                  ((I3C_Type *)I3C0_BASE_NS)
35488   /** Peripheral I3C1 base address */
35489   #define I3C1_BASE                                (0x50022000u)
35490   /** Peripheral I3C1 base address */
35491   #define I3C1_BASE_NS                             (0x40022000u)
35492   /** Peripheral I3C1 base pointer */
35493   #define I3C1                                     ((I3C_Type *)I3C1_BASE)
35494   /** Peripheral I3C1 base pointer */
35495   #define I3C1_NS                                  ((I3C_Type *)I3C1_BASE_NS)
35496   /** Array initializer of I3C peripheral base addresses */
35497   #define I3C_BASE_ADDRS                           { I3C0_BASE, I3C1_BASE }
35498   /** Array initializer of I3C peripheral base pointers */
35499   #define I3C_BASE_PTRS                            { I3C0, I3C1 }
35500   /** Array initializer of I3C peripheral base addresses */
35501   #define I3C_BASE_ADDRS_NS                        { I3C0_BASE_NS, I3C1_BASE_NS }
35502   /** Array initializer of I3C peripheral base pointers */
35503   #define I3C_BASE_PTRS_NS                         { I3C0_NS, I3C1_NS }
35504 #else
35505   /** Peripheral I3C0 base address */
35506   #define I3C0_BASE                                (0x40021000u)
35507   /** Peripheral I3C0 base pointer */
35508   #define I3C0                                     ((I3C_Type *)I3C0_BASE)
35509   /** Peripheral I3C1 base address */
35510   #define I3C1_BASE                                (0x40022000u)
35511   /** Peripheral I3C1 base pointer */
35512   #define I3C1                                     ((I3C_Type *)I3C1_BASE)
35513   /** Array initializer of I3C peripheral base addresses */
35514   #define I3C_BASE_ADDRS                           { I3C0_BASE, I3C1_BASE }
35515   /** Array initializer of I3C peripheral base pointers */
35516   #define I3C_BASE_PTRS                            { I3C0, I3C1 }
35517 #endif
35518 /** Interrupt vectors for the I3C peripheral type */
35519 #define I3C_IRQS                                 { I3C0_IRQn, I3C1_IRQn }
35520 
35521 /*!
35522  * @}
35523  */ /* end of group I3C_Peripheral_Access_Layer */
35524 
35525 
35526 /* ----------------------------------------------------------------------------
35527    -- INPUTMUX Peripheral Access Layer
35528    ---------------------------------------------------------------------------- */
35529 
35530 /*!
35531  * @addtogroup INPUTMUX_Peripheral_Access_Layer INPUTMUX Peripheral Access Layer
35532  * @{
35533  */
35534 
35535 /** INPUTMUX - Register Layout Typedef */
35536 typedef struct {
35537   __IO uint32_t SCT0_INMUX[8];                     /**< Inputmux Register for SCT0 Input, array offset: 0x0, array step: 0x4 */
35538   __IO uint32_t CTIMER0CAP0;                       /**< Capture Select Register for CTIMER Inputs, offset: 0x20 */
35539   __IO uint32_t CTIMER0CAP1;                       /**< Capture Select Register for CTIMER Inputs, offset: 0x24 */
35540   __IO uint32_t CTIMER0CAP2;                       /**< Capture Select Register for CTIMER Inputs, offset: 0x28 */
35541   __IO uint32_t CTIMER0CAP3;                       /**< Capture Select Register for CTIMER Inputs, offset: 0x2C */
35542   __IO uint32_t TIMER0TRIG;                        /**< Trigger Register for CTIMER, offset: 0x30 */
35543        uint8_t RESERVED_0[12];
35544   __IO uint32_t CTIMER1CAP0;                       /**< Capture Select Register for CTIMER Inputs, offset: 0x40 */
35545   __IO uint32_t CTIMER1CAP1;                       /**< Capture Select Register for CTIMER Inputs, offset: 0x44 */
35546   __IO uint32_t CTIMER1CAP2;                       /**< Capture Select Register for CTIMER Inputs, offset: 0x48 */
35547   __IO uint32_t CTIMER1CAP3;                       /**< Capture Select Register for CTIMER Inputs, offset: 0x4C */
35548   __IO uint32_t TIMER1TRIG;                        /**< Trigger Register for CTIMER, offset: 0x50 */
35549        uint8_t RESERVED_1[12];
35550   __IO uint32_t CTIMER2CAP0;                       /**< Capture Select Register for CTIMER Inputs, offset: 0x60 */
35551   __IO uint32_t CTIMER2CAP1;                       /**< Capture Select Register for CTIMER Inputs, offset: 0x64 */
35552   __IO uint32_t CTIMER2CAP2;                       /**< Capture Select Register for CTIMER Inputs, offset: 0x68 */
35553   __IO uint32_t CTIMER2CAP3;                       /**< Capture Select Register for CTIMER Inputs, offset: 0x6C */
35554   __IO uint32_t TIMER2TRIG;                        /**< Trigger Register for CTIMER, offset: 0x70 */
35555        uint8_t RESERVED_2[44];
35556   __IO uint32_t SMARTDMAARCHB_INMUX[8];            /**< Inputmux Register for SMARTDMA Arch B Inputs, array offset: 0xA0, array step: 0x4 */
35557   __IO uint32_t PINTSEL[8];                        /**< Pin Interrupt Select, array offset: 0xC0, array step: 0x4 */
35558        uint8_t RESERVED_3[160];
35559   __IO uint32_t FREQMEAS_REF;                      /**< Selection for Frequency Measurement Reference Clock, offset: 0x180 */
35560   __IO uint32_t FREQMEAS_TAR;                      /**< Selection for Frequency Measurement Target Clock, offset: 0x184 */
35561        uint8_t RESERVED_4[24];
35562   __IO uint32_t CTIMER3CAP0;                       /**< Capture Select Register for CTIMER Inputs, offset: 0x1A0 */
35563   __IO uint32_t CTIMER3CAP1;                       /**< Capture Select Register for CTIMER Inputs, offset: 0x1A4 */
35564   __IO uint32_t CTIMER3CAP2;                       /**< Capture Select Register for CTIMER Inputs, offset: 0x1A8 */
35565   __IO uint32_t CTIMER3CAP3;                       /**< Capture Select Register for CTIMER Inputs, offset: 0x1AC */
35566   __IO uint32_t TIMER3TRIG;                        /**< Trigger Register for CTIMER, offset: 0x1B0 */
35567        uint8_t RESERVED_5[12];
35568   __IO uint32_t CTIMER4CAP0;                       /**< Capture Select Register for CTIMER Inputs, offset: 0x1C0 */
35569   __IO uint32_t CTIMER4CAP1;                       /**< Capture Select Register for CTIMER Inputs, offset: 0x1C4 */
35570   __IO uint32_t CTIMER4CAP2;                       /**< Capture Select Register for CTIMER Inputs, offset: 0x1C8 */
35571   __IO uint32_t CTIMER4CAP3;                       /**< Capture Select Register for CTIMER Inputs, offset: 0x1CC */
35572   __IO uint32_t TIMER4TRIG;                        /**< Trigger Register for CTIMER, offset: 0x1D0 */
35573        uint8_t RESERVED_6[140];
35574   __IO uint32_t CMP0_TRIG;                         /**< CMP0 Input Connections, offset: 0x260 */
35575        uint8_t RESERVED_7[28];
35576   __IO uint32_t ADC0_TRIG[4];                      /**< ADC Trigger Input Connections, array offset: 0x280, array step: 0x4 */
35577        uint8_t RESERVED_8[48];
35578   __IO uint32_t ADC1_TRIG[4];                      /**< ADC Trigger Input Connections, array offset: 0x2C0, array step: 0x4 */
35579        uint8_t RESERVED_9[48];
35580   __IO uint32_t DAC0_TRIG;                         /**< DAC0 Trigger Inputs, offset: 0x300 */
35581        uint8_t RESERVED_10[28];
35582   __IO uint32_t DAC1_TRIG;                         /**< DAC1 Trigger Inputs, offset: 0x320 */
35583        uint8_t RESERVED_11[28];
35584   __IO uint32_t DAC2_TRIG;                         /**< DAC2 Trigger Inputs, offset: 0x340 */
35585        uint8_t RESERVED_12[28];
35586   struct {                                         /* offset: 0x360, array step: 0x20 */
35587     __IO uint32_t QDC_TRIG;                          /**< QDC0 Trigger Input Connections..QDC1 Trigger Input Connections, array offset: 0x360, array step: 0x20 */
35588     __IO uint32_t QDC_HOME;                          /**< QDC0 Input Connections..QDC1 Input Connections, array offset: 0x364, array step: 0x20 */
35589     __IO uint32_t QDC_INDEX;                         /**< QDC0 Input Connections..QDC1 Input Connections, array offset: 0x368, array step: 0x20 */
35590     __IO uint32_t QDC_PHASEB;                        /**< QDC0 Input Connections..QDC1 Input Connections, array offset: 0x36C, array step: 0x20 */
35591     __IO uint32_t QDC_PHASEA;                        /**< QDC0 Input Connections..QDC1 Input Connections, array offset: 0x370, array step: 0x20 */
35592          uint8_t RESERVED_0[12];
35593   } QDCN[2];
35594   __IO uint32_t FLEXPWM0_SM_EXTSYNC[4];            /**< PWM0 External Synchronization, array offset: 0x3A0, array step: 0x4 */
35595   __IO uint32_t FLEXPWM0_SM_EXTA[4];               /**< PWM0 Input Trigger Connections, array offset: 0x3B0, array step: 0x4 */
35596   __IO uint32_t FLEXPWM0_EXTFORCE;                 /**< PWM0 External Force Trigger Connections, offset: 0x3C0 */
35597   __IO uint32_t FLEXPWM0_FAULT[4];                 /**< PWM0 Fault Input Trigger Connections, array offset: 0x3C4, array step: 0x4 */
35598        uint8_t RESERVED_13[12];
35599   __IO uint32_t FLEXPWM1_SM_EXTSYNC[4];            /**< PWM1 External Synchronization, array offset: 0x3E0, array step: 0x4 */
35600   __IO uint32_t FLEXPWM1_SM_EXTA[4];               /**< PWM1 Input EXTA Connections, array offset: 0x3F0, array step: 0x4 */
35601   __IO uint32_t FLEXPWM1_EXTFORCE;                 /**< PWM1 External Force Trigger Connections, offset: 0x400 */
35602   __IO uint32_t FLEXPWM1_FAULT[4];                 /**< PWM1 Fault Input Trigger Connections, array offset: 0x404, array step: 0x4 */
35603        uint8_t RESERVED_14[12];
35604   __IO uint32_t PWM0_EXT_CLK;                      /**< PWM0 External Clock Trigger, offset: 0x420 */
35605   __IO uint32_t PWM1_EXT_CLK;                      /**< PWM1 External Clock Trigger, offset: 0x424 */
35606        uint8_t RESERVED_15[24];
35607   __IO uint32_t EVTG_TRIG[16];                     /**< EVTG Trigger Input Connections, array offset: 0x440, array step: 0x4 */
35608   __IO uint32_t USBFS_TRIG;                        /**< USB-FS Trigger Input Connections, offset: 0x480 */
35609        uint8_t RESERVED_16[28];
35610   __IO uint32_t TSI_TRIG;                          /**< TSI Trigger Input Connections, offset: 0x4A0 */
35611        uint8_t RESERVED_17[28];
35612   __IO uint32_t EXT_TRIG[8];                       /**< EXT Trigger Connections, array offset: 0x4C0, array step: 0x4 */
35613   __IO uint32_t CMP1_TRIG;                         /**< CMP1 Input Connections, offset: 0x4E0 */
35614        uint8_t RESERVED_18[28];
35615   __IO uint32_t CMP2_TRIG;                         /**< CMP2 Input Connections, offset: 0x500 */
35616        uint8_t RESERVED_19[28];
35617   __IO uint32_t SINC_FILTER_CH[5];                 /**< SINC Filter Channel Trigger Input Connections, array offset: 0x520, array step: 0x4 */
35618        uint8_t RESERVED_20[76];
35619   __IO uint32_t OPAMP_TRIG[3];                     /**< OPAMP Trigger Input Connections, array offset: 0x580, array step: 0x4 */
35620        uint8_t RESERVED_21[20];
35621   __IO uint32_t FLEXCOMM0_TRIG;                    /**< LP_FLEXCOMM0 Trigger Input Connections, offset: 0x5A0 */
35622        uint8_t RESERVED_22[28];
35623   __IO uint32_t FLEXCOMM1_TRIG;                    /**< LP_FLEXCOMM1 Trigger Input Connections, offset: 0x5C0 */
35624        uint8_t RESERVED_23[28];
35625   __IO uint32_t FLEXCOMM2_TRIG;                    /**< LP_FLEXCOMM2 Trigger Input Connections, offset: 0x5E0 */
35626        uint8_t RESERVED_24[28];
35627   __IO uint32_t FLEXCOMM3_TRIG;                    /**< LP_FLEXCOMM3 Trigger Input Connections, offset: 0x600 */
35628        uint8_t RESERVED_25[28];
35629   __IO uint32_t FLEXCOMM4_TRIG;                    /**< LP_FLEXCOMM4 Trigger Input Connections, offset: 0x620 */
35630        uint8_t RESERVED_26[28];
35631   __IO uint32_t FLEXCOMM5_TRIG;                    /**< LP_FLEXCOMM5 Trigger Input Connections, offset: 0x640 */
35632        uint8_t RESERVED_27[28];
35633   __IO uint32_t FLEXCOMM6_TRIG;                    /**< LP_FLEXCOMM6 Trigger Input Connections, offset: 0x660 */
35634        uint8_t RESERVED_28[28];
35635   __IO uint32_t FLEXCOMM7_TRIG;                    /**< LP_FLEXCOMM7 Trigger Input Connections, offset: 0x680 */
35636        uint8_t RESERVED_29[28];
35637   __IO uint32_t FLEXCOMM8_TRIG;                    /**< LP_FLEXCOMM8 Trigger Input Connections, offset: 0x6A0 */
35638        uint8_t RESERVED_30[28];
35639   __IO uint32_t FLEXCOMM9_TRIG;                    /**< LP_FLEXCOMM9 Trigger Input Connections, offset: 0x6C0 */
35640        uint8_t RESERVED_31[28];
35641   __IO uint32_t FLEXIO_TRIG[8];                    /**< FlexIO Trigger Input Connections, array offset: 0x6E0, array step: 0x4 */
35642   __IO uint32_t DMA0_REQ_ENABLE0;                  /**< DMA0 Request Enable0, offset: 0x700 */
35643   __O  uint32_t DMA0_REQ_ENABLE0_SET;              /**< DMA0 Request Enable0, offset: 0x704 */
35644   __O  uint32_t DMA0_REQ_ENABLE0_CLR;              /**< DMA0 Request Enable0, offset: 0x708 */
35645   __O  uint32_t DMA0_REQ_ENABLE0_TOG;              /**< DMA0 Request Enable0, offset: 0x70C */
35646   __IO uint32_t DMA0_REQ_ENABLE1;                  /**< DMA0 Request Enable1, offset: 0x710 */
35647   __O  uint32_t DMA0_REQ_ENABLE1_SET;              /**< DMA0 Request Enable1, offset: 0x714 */
35648   __O  uint32_t DMA0_REQ_ENABLE1_CLR;              /**< DMA0 Request Enable1, offset: 0x718 */
35649   __O  uint32_t DMA0_REQ_ENABLE1_TOG;              /**< DMA0 Request Enable1, offset: 0x71C */
35650   __IO uint32_t DMA0_REQ_ENABLE2;                  /**< DMA0 Request Enable2, offset: 0x720 */
35651   __O  uint32_t DMA0_REQ_ENABLE2_SET;              /**< DMA0 Request Enable2, offset: 0x724 */
35652   __O  uint32_t DMA0_REQ_ENABLE2_CLR;              /**< DMA0 Request Enable2, offset: 0x728 */
35653   __O  uint32_t DMA0_REQ_ENABLE2_TOG;              /**< DMA0 Request Enable2, offset: 0x72C */
35654   __IO uint32_t DMA0_REQ_ENABLE3;                  /**< DMA0 Request Enable3, offset: 0x730 */
35655   __O  uint32_t DMA0_REQ_ENABLE3_SET;              /**< DMA0 Request Enable3, offset: 0x734 */
35656   __O  uint32_t DMA0_REQ_ENABLE3_CLR;              /**< DMA0 Request Enable3, offset: 0x738 */
35657        uint8_t RESERVED_32[68];
35658   __IO uint32_t DMA1_REQ_ENABLE0;                  /**< DMA1 Request Enable0, offset: 0x780 */
35659   __O  uint32_t DMA1_REQ_ENABLE0_SET;              /**< DMA1 Request Enable0, offset: 0x784 */
35660   __O  uint32_t DMA1_REQ_ENABLE0_CLR;              /**< DMA1 Request Enable0, offset: 0x788 */
35661   __O  uint32_t DMA1_REQ_ENABLE0_TOG;              /**< DMA1 Request Enable0, offset: 0x78C */
35662   __IO uint32_t DMA1_REQ_ENABLE1;                  /**< DMA1 Request Enable1, offset: 0x790 */
35663   __O  uint32_t DMA1_REQ_ENABLE1_SET;              /**< DMA1 Request Enable1, offset: 0x794 */
35664   __O  uint32_t DMA1_REQ_ENABLE1_CLR;              /**< DMA1 Request Enable1, offset: 0x798 */
35665   __O  uint32_t DMA1_REQ_ENABLE1_TOG;              /**< DMA1 Request Enable1, offset: 0x79C */
35666   __IO uint32_t DMA1_REQ_ENABLE2;                  /**< DMA1 Request Enable2, offset: 0x7A0 */
35667   __O  uint32_t DMA1_REQ_ENABLE2_SET;              /**< DMA1 Request Enable2, offset: 0x7A4 */
35668   __O  uint32_t DMA1_REQ_ENABLE2_CLR;              /**< DMA1 Request Enable2, offset: 0x7A8 */
35669   __O  uint32_t DMA1_REQ_ENABLE2_TOG;              /**< DMA1 Request Enable2, offset: 0x7AC */
35670   __IO uint32_t DMA1_REQ_ENABLE3;                  /**< DMA1 Request Enable3, offset: 0x7B0 */
35671   __O  uint32_t DMA1_REQ_ENABLE3_SET;              /**< DMA1 Request Enable3, offset: 0x7B4 */
35672   __O  uint32_t DMA1_REQ_ENABLE3_CLR;              /**< DMA1 Request Enable3, offset: 0x7B8 */
35673 } INPUTMUX_Type;
35674 
35675 /* ----------------------------------------------------------------------------
35676    -- INPUTMUX Register Masks
35677    ---------------------------------------------------------------------------- */
35678 
35679 /*!
35680  * @addtogroup INPUTMUX_Register_Masks INPUTMUX Register Masks
35681  * @{
35682  */
35683 
35684 /*! @name INPUTMUX_SCT0_SCT0_INMUX - Inputmux Register for SCT0 Input */
35685 /*! @{ */
35686 
35687 #define INPUTMUX_INPUTMUX_SCT0_SCT0_INMUX_INP_MASK (0x7FU)
35688 #define INPUTMUX_INPUTMUX_SCT0_SCT0_INMUX_INP_SHIFT (0U)
35689 /*! INP - Input number to SCT0 inputs.
35690  *  0b0000000..SCT0_IN0 input is selected
35691  *  0b0000001..SCT0_IN1 input is selected
35692  *  0b0000010..SCT0_IN2 input is selected
35693  *  0b0000011..SCT0_IN3 input is selected
35694  *  0b0000100..SCT0_IN4 input is selected
35695  *  0b0000101..SCT0_IN5 input is selected
35696  *  0b0000110..SCT0_IN6 input is selected
35697  *  0b0000111..SCT0_IN7 input is selected
35698  *  0b0001000..CTIMER0_MAT0 input is selected
35699  *  0b0001001..CTIMER1_MAT0 input is selected
35700  *  0b0001010..CTIMER2_MAT0 input is selected
35701  *  0b0001011..CTIMER3_MAT0 input is selected
35702  *  0b0001100..CTIMER4_MAT0 input is selected
35703  *  0b0001101..ADC0 ADC0_IRQ input is selected
35704  *  0b0001110..PINT GPIO_INT_BMAT input is selected
35705  *  0b0001111..usb0 start of frame input is selected
35706  *  0b0010000..usb1 start of frame input is selected
35707  *  0b0010001..SINC Filter CH0 Conversion Complete input is selected
35708  *  0b0010010..SINC Filter CH1 Conversion Complete input is selected
35709  *  0b0010011..SINC Filter CH2 Conversion Complete input is selected
35710  *  0b0010100..SINC Filter CH3 Conversion Complete input is selected
35711  *  0b0010101..SINC Filter CH4 Conversion Complete input is selected
35712  *  0b0010110..Reserved
35713  *  0b0010111..DEBUG_HALTED input is selected
35714  *  0b0011000..ADC1_IRQ input is selected
35715  *  0b0011001..ADC0_tcomp[0] input is selected
35716  *  0b0011010..ADC0_tcomp[1] input is selected
35717  *  0b0011011..ADC0_tcomp[2] input is selected
35718  *  0b0011100..ADC0_tcomp[3] input is selected
35719  *  0b0011101..ADC1_tcomp[0] input is selected
35720  *  0b0011110..ADC1_tcomp[1] input is selected
35721  *  0b0011111..ADC1_tcomp[2] input is selected
35722  *  0b0100000..ADC1_tcomp[3] input is selected
35723  *  0b0100001..CMP0_OUT input is selected
35724  *  0b0100010..CMP1_OUT input is selected
35725  *  0b0100011..CMP2_OUT input is selected
35726  *  0b0100100..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected
35727  *  0b0100101..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected
35728  *  0b0100110..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected
35729  *  0b0100111..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected
35730  *  0b0101000..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected
35731  *  0b0101001..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected
35732  *  0b0101010..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected
35733  *  0b0101011..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected
35734  *  0b0101100..QDC0_CMP/POS_MATCH input is selected
35735  *  0b0101101..QDC1_CMP/POS_MATCH input is selected
35736  *  0b0101110..EVTG_OUT0A input is selected
35737  *  0b0101111..EVTG_OUT0B input is selected
35738  *  0b0110000..EVTG_OUT1A input is selected
35739  *  0b0110001..EVTG_OUT1B input is selected
35740  *  0b0110010..EVTG_OUT2A input is selected
35741  *  0b0110011..EVTG_OUT2B input is selected
35742  *  0b0110100..EVTG_OUT3A input is selected
35743  *  0b0110101..EVTG_OUT3B input is selected
35744  *  0b0110110..FC3_P0 (SDO, SDA) input is selected
35745  *  0b0110111..FC3_P1 (SCK, TXD, SCL) input is selected
35746  *  0b0111000..FC3_P2 (RTS, SCLS, TXD) input is selected
35747  *  0b0111001..FC3_P3 (PCS[0], CTS, SDAS) input is selected
35748  *  0b0111010..Reserved
35749  *  0b0111011..Reserved
35750  *  0b0111100..LP_FLEXCOMM0 trig 0 (lpuart_trg_txword) input is selected
35751  *  0b0111101..LP_FLEXCOMM0 trig 1 (lpuart_trg_rxword) input is selected
35752  *  0b0111110..LP_FLEXCOMM0 trig 2 (lpuart_trg_rxidle) input is selected
35753  *  0b0111111..LP_FLEXCOMM1 trig 0 input is selected
35754  *  0b1000000..LP_FLEXCOMM1 trig 1 input is selected
35755  *  0b1000001..LP_FLEXCOMM1 trig 2 input is selected
35756  *  0b1000010..LP_FLEXCOMM2 trig 0 input is selected
35757  *  0b1000011..LP_FLEXCOMM2 trig 1 input is selected
35758  *  0b1000100..LP_FLEXCOMM2 trig 2 input is selected
35759  *  0b1000101..LP_FLEXCOMM3 trig 0 input is selected
35760  *  0b1000110..LP_FLEXCOMM3 trig 1 input is selected
35761  *  0b1000111..LP_FLEXCOMM3 trig 2 input is selected
35762  *  0b1001000..LP_FLEXCOMM3 trig 3 input is selected
35763  *  0b1001001..SAI0 TX BCLK input is selected
35764  *  0b1001010..SAI0 RX BCLK input is selected
35765  *  0b1001011..SAI1 TX BCLK input is selected
35766  *  0b1001100..SAI1 RX BCLK input is selected
35767  *  *..
35768  */
35769 #define INPUTMUX_INPUTMUX_SCT0_SCT0_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_INPUTMUX_SCT0_SCT0_INMUX_INP_SHIFT)) & INPUTMUX_INPUTMUX_SCT0_SCT0_INMUX_INP_MASK)
35770 /*! @} */
35771 
35772 /* The count of INPUTMUX_INPUTMUX_SCT0_SCT0_INMUX */
35773 #define INPUTMUX_INPUTMUX_SCT0_SCT0_INMUX_COUNT  (8U)
35774 
35775 /*! @name CTIMER0CAP0 - Capture Select Register for CTIMER Inputs */
35776 /*! @{ */
35777 
35778 #define INPUTMUX_CTIMER0CAP0_INP_MASK            (0x7FU)
35779 #define INPUTMUX_CTIMER0CAP0_INP_SHIFT           (0U)
35780 /*! INP - Input number for CTIMER
35781  *  0b0000000..CT_INP0 input is selected
35782  *  0b0000001..CT_INP1 input is selected
35783  *  0b0000010..CT_INP2 input is selected
35784  *  0b0000011..CT_INP3 input is selected
35785  *  0b0000100..CT_INP4 input is selected
35786  *  0b0000101..CT_INP5 input is selected
35787  *  0b0000110..CT_INP6 input is selected
35788  *  0b0000111..CT_INP7 input is selected
35789  *  0b0001000..CT_INP8 input is selected
35790  *  0b0001001..CT_INP9 input is selected
35791  *  0b0001010..CT_INP10 input is selected
35792  *  0b0001011..CT_INP11 input is selected
35793  *  0b0001100..CT_INP12 input is selected
35794  *  0b0001101..CT_INP13 input is selected
35795  *  0b0001110..CT_INP14 input is selected
35796  *  0b0001111..CT_INP15 input is selected
35797  *  0b0010000..CT_INP16 input is selected
35798  *  0b0010001..CT_INP17 input is selected
35799  *  0b0010010..CT_INP18 input is selected
35800  *  0b0010011..CT_INP19 input is selected
35801  *  0b0010100..usb0 start of frame input is selected
35802  *  0b0010101..usb1 start of frame input is selected
35803  *  0b0010110..DCDC_BURST_ACTIVE input is selected
35804  *  0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected
35805  *  0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected
35806  *  0b0011001..ADC0_IRQ input is selected
35807  *  0b0011010..ADC1_IRQ input is selected
35808  *  0b0011011..CMP0_OUT input is selected
35809  *  0b0011100..CMP1_OUT input is selected
35810  *  0b0011101..CMP2_OUT input is selected
35811  *  0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected
35812  *  0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected
35813  *  0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected
35814  *  0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected
35815  *  0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected
35816  *  0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected
35817  *  0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected
35818  *  0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected
35819  *  0b0100110..QDC0_CMP/POS_MATCH input is selected
35820  *  0b0100111..QDC1_CMP/POS_MATCH input is selected
35821  *  0b0101000..EVTG_OUT0A input is selected
35822  *  0b0101001..EVTG_OUT0B input is selected
35823  *  0b0101010..EVTG_OUT1A input is selected
35824  *  0b0101011..EVTG_OUT1B input is selected
35825  *  0b0101100..EVTG_OUT2A input is selected
35826  *  0b0101101..EVTG_OUT2B input is selected
35827  *  0b0101110..EVTG_OUT3A input is selected
35828  *  0b0101111..EVTG_OUT3B input is selected
35829  *  0b0110000..Reserved
35830  *  0b0110001..Reserved
35831  *  0b0110010..LP_FLEXCOMM0 trig 0 input is selected
35832  *  0b0110011..LP_FLEXCOMM0 trig 1 input is selected
35833  *  0b0110100..LP_FLEXCOMM0 trig 2 input is selected
35834  *  0b0110101..LP_FLEXCOMM1 trig 0 input is selected
35835  *  0b0110110..LP_FLEXCOMM1 trig 1 input is selected
35836  *  0b0110111..LP_FLEXCOMM1 trig 2 input is selected
35837  *  0b0111000..LP_FLEXCOMM2 trig 0 input is selected
35838  *  0b0111001..LP_FLEXCOMM2 trig 1 input is selected
35839  *  0b0111010..LP_FLEXCOMM2 trig 2 input is selected
35840  *  0b0111011..LP_FLEXCOMM3 trig 0 input is selected
35841  *  0b0111100..LP_FLEXCOMM3 trig 1 input is selected
35842  *  0b0111101..LP_FLEXCOMM3 trig 2 input is selected
35843  *  0b0111110..LP_FLEXCOMM3 trig 3 input is selected
35844  *  0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected
35845  *  0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected
35846  *  *..
35847  */
35848 #define INPUTMUX_CTIMER0CAP0_INP(x)              (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER0CAP0_INP_SHIFT)) & INPUTMUX_CTIMER0CAP0_INP_MASK)
35849 /*! @} */
35850 
35851 /*! @name CTIMER0CAP1 - Capture Select Register for CTIMER Inputs */
35852 /*! @{ */
35853 
35854 #define INPUTMUX_CTIMER0CAP1_INP_MASK            (0x7FU)
35855 #define INPUTMUX_CTIMER0CAP1_INP_SHIFT           (0U)
35856 /*! INP - Input number for CTIMER
35857  *  0b0000000..CT_INP0 input is selected
35858  *  0b0000001..CT_INP1 input is selected
35859  *  0b0000010..CT_INP2 input is selected
35860  *  0b0000011..CT_INP3 input is selected
35861  *  0b0000100..CT_INP4 input is selected
35862  *  0b0000101..CT_INP5 input is selected
35863  *  0b0000110..CT_INP6 input is selected
35864  *  0b0000111..CT_INP7 input is selected
35865  *  0b0001000..CT_INP8 input is selected
35866  *  0b0001001..CT_INP9 input is selected
35867  *  0b0001010..CT_INP10 input is selected
35868  *  0b0001011..CT_INP11 input is selected
35869  *  0b0001100..CT_INP12 input is selected
35870  *  0b0001101..CT_INP13 input is selected
35871  *  0b0001110..CT_INP14 input is selected
35872  *  0b0001111..CT_INP15 input is selected
35873  *  0b0010000..CT_INP16 input is selected
35874  *  0b0010001..CT_INP17 input is selected
35875  *  0b0010010..CT_INP18 input is selected
35876  *  0b0010011..CT_INP19 input is selected
35877  *  0b0010100..usb0 start of frame input is selected
35878  *  0b0010101..usb1 start of frame input is selected
35879  *  0b0010110..DCDC_BURST_ACTIVE input is selected
35880  *  0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected
35881  *  0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected
35882  *  0b0011001..ADC0_IRQ input is selected
35883  *  0b0011010..ADC1_IRQ input is selected
35884  *  0b0011011..CMP0_OUT input is selected
35885  *  0b0011100..CMP1_OUT input is selected
35886  *  0b0011101..CMP2_OUT input is selected
35887  *  0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected
35888  *  0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected
35889  *  0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected
35890  *  0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected
35891  *  0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected
35892  *  0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected
35893  *  0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected
35894  *  0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected
35895  *  0b0100110..QDC0_CMP/POS_MATCH input is selected
35896  *  0b0100111..QDC1_CMP/POS_MATCH input is selected
35897  *  0b0101000..EVTG_OUT0A input is selected
35898  *  0b0101001..EVTG_OUT0B input is selected
35899  *  0b0101010..EVTG_OUT1A input is selected
35900  *  0b0101011..EVTG_OUT1B input is selected
35901  *  0b0101100..EVTG_OUT2A input is selected
35902  *  0b0101101..EVTG_OUT2B input is selected
35903  *  0b0101110..EVTG_OUT3A input is selected
35904  *  0b0101111..EVTG_OUT3B input is selected
35905  *  0b0110000..Reserved
35906  *  0b0110001..Reserved
35907  *  0b0110010..LP_FLEXCOMM0 trig 0 input is selected
35908  *  0b0110011..LP_FLEXCOMM0 trig 1 input is selected
35909  *  0b0110100..LP_FLEXCOMM0 trig 2 input is selected
35910  *  0b0110101..LP_FLEXCOMM1 trig 0 input is selected
35911  *  0b0110110..LP_FLEXCOMM1 trig 1 input is selected
35912  *  0b0110111..LP_FLEXCOMM1 trig 2 input is selected
35913  *  0b0111000..LP_FLEXCOMM2 trig 0 input is selected
35914  *  0b0111001..LP_FLEXCOMM2 trig 1 input is selected
35915  *  0b0111010..LP_FLEXCOMM2 trig 2 input is selected
35916  *  0b0111011..LP_FLEXCOMM3 trig 0 input is selected
35917  *  0b0111100..LP_FLEXCOMM3 trig 1 input is selected
35918  *  0b0111101..LP_FLEXCOMM3 trig 2 input is selected
35919  *  0b0111110..LP_FLEXCOMM3 trig 3 input is selected
35920  *  0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected
35921  *  0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected
35922  *  *..
35923  */
35924 #define INPUTMUX_CTIMER0CAP1_INP(x)              (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER0CAP1_INP_SHIFT)) & INPUTMUX_CTIMER0CAP1_INP_MASK)
35925 /*! @} */
35926 
35927 /*! @name CTIMER0CAP2 - Capture Select Register for CTIMER Inputs */
35928 /*! @{ */
35929 
35930 #define INPUTMUX_CTIMER0CAP2_INP_MASK            (0x7FU)
35931 #define INPUTMUX_CTIMER0CAP2_INP_SHIFT           (0U)
35932 /*! INP - Input number for CTIMER
35933  *  0b0000000..CT_INP0 input is selected
35934  *  0b0000001..CT_INP1 input is selected
35935  *  0b0000010..CT_INP2 input is selected
35936  *  0b0000011..CT_INP3 input is selected
35937  *  0b0000100..CT_INP4 input is selected
35938  *  0b0000101..CT_INP5 input is selected
35939  *  0b0000110..CT_INP6 input is selected
35940  *  0b0000111..CT_INP7 input is selected
35941  *  0b0001000..CT_INP8 input is selected
35942  *  0b0001001..CT_INP9 input is selected
35943  *  0b0001010..CT_INP10 input is selected
35944  *  0b0001011..CT_INP11 input is selected
35945  *  0b0001100..CT_INP12 input is selected
35946  *  0b0001101..CT_INP13 input is selected
35947  *  0b0001110..CT_INP14 input is selected
35948  *  0b0001111..CT_INP15 input is selected
35949  *  0b0010000..CT_INP16 input is selected
35950  *  0b0010001..CT_INP17 input is selected
35951  *  0b0010010..CT_INP18 input is selected
35952  *  0b0010011..CT_INP19 input is selected
35953  *  0b0010100..usb0 start of frame input is selected
35954  *  0b0010101..usb1 start of frame input is selected
35955  *  0b0010110..DCDC_BURST_ACTIVE input is selected
35956  *  0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected
35957  *  0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected
35958  *  0b0011001..ADC0_IRQ input is selected
35959  *  0b0011010..ADC1_IRQ input is selected
35960  *  0b0011011..CMP0_OUT input is selected
35961  *  0b0011100..CMP1_OUT input is selected
35962  *  0b0011101..CMP2_OUT input is selected
35963  *  0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected
35964  *  0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected
35965  *  0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected
35966  *  0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected
35967  *  0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected
35968  *  0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected
35969  *  0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected
35970  *  0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected
35971  *  0b0100110..QDC0_CMP/POS_MATCH input is selected
35972  *  0b0100111..QDC1_CMP/POS_MATCH input is selected
35973  *  0b0101000..EVTG_OUT0A input is selected
35974  *  0b0101001..EVTG_OUT0B input is selected
35975  *  0b0101010..EVTG_OUT1A input is selected
35976  *  0b0101011..EVTG_OUT1B input is selected
35977  *  0b0101100..EVTG_OUT2A input is selected
35978  *  0b0101101..EVTG_OUT2B input is selected
35979  *  0b0101110..EVTG_OUT3A input is selected
35980  *  0b0101111..EVTG_OUT3B input is selected
35981  *  0b0110000..Reserved
35982  *  0b0110001..Reserved
35983  *  0b0110010..LP_FLEXCOMM0 trig 0 input is selected
35984  *  0b0110011..LP_FLEXCOMM0 trig 1 input is selected
35985  *  0b0110100..LP_FLEXCOMM0 trig 2 input is selected
35986  *  0b0110101..LP_FLEXCOMM1 trig 0 input is selected
35987  *  0b0110110..LP_FLEXCOMM1 trig 1 input is selected
35988  *  0b0110111..LP_FLEXCOMM1 trig 2 input is selected
35989  *  0b0111000..LP_FLEXCOMM2 trig 0 input is selected
35990  *  0b0111001..LP_FLEXCOMM2 trig 1 input is selected
35991  *  0b0111010..LP_FLEXCOMM2 trig 2 input is selected
35992  *  0b0111011..LP_FLEXCOMM3 trig 0 input is selected
35993  *  0b0111100..LP_FLEXCOMM3 trig 1 input is selected
35994  *  0b0111101..LP_FLEXCOMM3 trig 2 input is selected
35995  *  0b0111110..LP_FLEXCOMM3 trig 3 input is selected
35996  *  0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected
35997  *  0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected
35998  *  *..
35999  */
36000 #define INPUTMUX_CTIMER0CAP2_INP(x)              (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER0CAP2_INP_SHIFT)) & INPUTMUX_CTIMER0CAP2_INP_MASK)
36001 /*! @} */
36002 
36003 /*! @name CTIMER0CAP3 - Capture Select Register for CTIMER Inputs */
36004 /*! @{ */
36005 
36006 #define INPUTMUX_CTIMER0CAP3_INP_MASK            (0x7FU)
36007 #define INPUTMUX_CTIMER0CAP3_INP_SHIFT           (0U)
36008 /*! INP - Input number for CTIMER
36009  *  0b0000000..CT_INP0 input is selected
36010  *  0b0000001..CT_INP1 input is selected
36011  *  0b0000010..CT_INP2 input is selected
36012  *  0b0000011..CT_INP3 input is selected
36013  *  0b0000100..CT_INP4 input is selected
36014  *  0b0000101..CT_INP5 input is selected
36015  *  0b0000110..CT_INP6 input is selected
36016  *  0b0000111..CT_INP7 input is selected
36017  *  0b0001000..CT_INP8 input is selected
36018  *  0b0001001..CT_INP9 input is selected
36019  *  0b0001010..CT_INP10 input is selected
36020  *  0b0001011..CT_INP11 input is selected
36021  *  0b0001100..CT_INP12 input is selected
36022  *  0b0001101..CT_INP13 input is selected
36023  *  0b0001110..CT_INP14 input is selected
36024  *  0b0001111..CT_INP15 input is selected
36025  *  0b0010000..CT_INP16 input is selected
36026  *  0b0010001..CT_INP17 input is selected
36027  *  0b0010010..CT_INP18 input is selected
36028  *  0b0010011..CT_INP19 input is selected
36029  *  0b0010100..usb0 start of frame input is selected
36030  *  0b0010101..usb1 start of frame input is selected
36031  *  0b0010110..DCDC_BURST_ACTIVE input is selected
36032  *  0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected
36033  *  0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected
36034  *  0b0011001..ADC0_IRQ input is selected
36035  *  0b0011010..ADC1_IRQ input is selected
36036  *  0b0011011..CMP0_OUT input is selected
36037  *  0b0011100..CMP1_OUT input is selected
36038  *  0b0011101..CMP2_OUT input is selected
36039  *  0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected
36040  *  0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected
36041  *  0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected
36042  *  0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected
36043  *  0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected
36044  *  0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected
36045  *  0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected
36046  *  0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected
36047  *  0b0100110..QDC0_CMP/POS_MATCH input is selected
36048  *  0b0100111..QDC1_CMP/POS_MATCH input is selected
36049  *  0b0101000..EVTG_OUT0A input is selected
36050  *  0b0101001..EVTG_OUT0B input is selected
36051  *  0b0101010..EVTG_OUT1A input is selected
36052  *  0b0101011..EVTG_OUT1B input is selected
36053  *  0b0101100..EVTG_OUT2A input is selected
36054  *  0b0101101..EVTG_OUT2B input is selected
36055  *  0b0101110..EVTG_OUT3A input is selected
36056  *  0b0101111..EVTG_OUT3B input is selected
36057  *  0b0110000..Reserved
36058  *  0b0110001..Reserved
36059  *  0b0110010..LP_FLEXCOMM0 trig 0 input is selected
36060  *  0b0110011..LP_FLEXCOMM0 trig 1 input is selected
36061  *  0b0110100..LP_FLEXCOMM0 trig 2 input is selected
36062  *  0b0110101..LP_FLEXCOMM1 trig 0 input is selected
36063  *  0b0110110..LP_FLEXCOMM1 trig 1 input is selected
36064  *  0b0110111..LP_FLEXCOMM1 trig 2 input is selected
36065  *  0b0111000..LP_FLEXCOMM2 trig 0 input is selected
36066  *  0b0111001..LP_FLEXCOMM2 trig 1 input is selected
36067  *  0b0111010..LP_FLEXCOMM2 trig 2 input is selected
36068  *  0b0111011..LP_FLEXCOMM3 trig 0 input is selected
36069  *  0b0111100..LP_FLEXCOMM3 trig 1 input is selected
36070  *  0b0111101..LP_FLEXCOMM3 trig 2 input is selected
36071  *  0b0111110..LP_FLEXCOMM3 trig 3 input is selected
36072  *  0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected
36073  *  0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected
36074  *  *..
36075  */
36076 #define INPUTMUX_CTIMER0CAP3_INP(x)              (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER0CAP3_INP_SHIFT)) & INPUTMUX_CTIMER0CAP3_INP_MASK)
36077 /*! @} */
36078 
36079 /*! @name TIMER0TRIG - Trigger Register for CTIMER */
36080 /*! @{ */
36081 
36082 #define INPUTMUX_TIMER0TRIG_INP_MASK             (0x7FU)
36083 #define INPUTMUX_TIMER0TRIG_INP_SHIFT            (0U)
36084 /*! INP - Input number for CTIMER
36085  *  0b0000000..CT_INP0 input is selected
36086  *  0b0000001..CT_INP1 input is selected
36087  *  0b0000010..CT_INP2 input is selected
36088  *  0b0000011..CT_INP3 input is selected
36089  *  0b0000100..CT_INP4 input is selected
36090  *  0b0000101..CT_INP5 input is selected
36091  *  0b0000110..CT_INP6 input is selected
36092  *  0b0000111..CT_INP7 input is selected
36093  *  0b0001000..CT_INP8 input is selected
36094  *  0b0001001..CT_INP9 input is selected
36095  *  0b0001010..CT_INP10 input is selected
36096  *  0b0001011..CT_INP11 input is selected
36097  *  0b0001100..CT_INP12 input is selected
36098  *  0b0001101..CT_INP13 input is selected
36099  *  0b0001110..CT_INP14 input is selected
36100  *  0b0001111..CT_INP15 input is selected
36101  *  0b0010000..CT_INP16 input is selected
36102  *  0b0010001..CT_INP17 input is selected
36103  *  0b0010010..CT_INP18 input is selected
36104  *  0b0010011..CT_INP19 input is selected
36105  *  0b0010100..usb0 start of frame input is selected
36106  *  0b0010101..usb1 start of frame input is selected
36107  *  0b0010110..DCDC_BURST_ACTIVE input is selected
36108  *  0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected
36109  *  0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected
36110  *  0b0011001..ADC0_IRQ input is selected
36111  *  0b0011010..ADC1_IRQ input is selected
36112  *  0b0011011..CMP0_OUT input is selected
36113  *  0b0011100..CMP1_OUT input is selected
36114  *  0b0011101..CMP2_OUT input is selected
36115  *  0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected
36116  *  0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected
36117  *  0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected
36118  *  0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected
36119  *  0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected
36120  *  0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected
36121  *  0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected
36122  *  0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected
36123  *  0b0100110..QDC0_CMP/POS_MATCH input is selected
36124  *  0b0100111..QDC1_CMP/POS_MATCH input is selected
36125  *  0b0101000..EVTG_OUT0A input is selected
36126  *  0b0101001..EVTG_OUT0B input is selected
36127  *  0b0101010..EVTG_OUT1A input is selected
36128  *  0b0101011..EVTG_OUT1B input is selected
36129  *  0b0101100..EVTG_OUT2A input is selected
36130  *  0b0101101..EVTG_OUT2B input is selected
36131  *  0b0101110..EVTG_OUT3A input is selected
36132  *  0b0101111..EVTG_OUT3B input is selected
36133  *  0b0110000..Reserved
36134  *  0b0110001..Reserved
36135  *  0b0110010..LP_FLEXCOMM0 trig 0 input is selected
36136  *  0b0110011..LP_FLEXCOMM0 trig 1 input is selected
36137  *  0b0110100..LP_FLEXCOMM0 trig 2 input is selected
36138  *  0b0110101..LP_FLEXCOMM1 trig 0 input is selected
36139  *  0b0110110..LP_FLEXCOMM1 trig 1 input is selected
36140  *  0b0110111..LP_FLEXCOMM1 trig 2 input is selected
36141  *  0b0111000..LP_FLEXCOMM2 trig 0 input is selected
36142  *  0b0111001..LP_FLEXCOMM2 trig 1 input is selected
36143  *  0b0111010..LP_FLEXCOMM2 trig 2 input is selected
36144  *  0b0111011..LP_FLEXCOMM3 trig 0 input is selected
36145  *  0b0111100..LP_FLEXCOMM3 trig 1 input is selected
36146  *  0b0111101..LP_FLEXCOMM3 trig 2 input is selected
36147  *  0b0111110..LP_FLEXCOMM3 trig 3 input is selected
36148  *  0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected
36149  *  0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected
36150  *  *..
36151  */
36152 #define INPUTMUX_TIMER0TRIG_INP(x)               (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER0TRIG_INP_SHIFT)) & INPUTMUX_TIMER0TRIG_INP_MASK)
36153 /*! @} */
36154 
36155 /*! @name CTIMER1CAP0 - Capture Select Register for CTIMER Inputs */
36156 /*! @{ */
36157 
36158 #define INPUTMUX_CTIMER1CAP0_INP_MASK            (0x7FU)
36159 #define INPUTMUX_CTIMER1CAP0_INP_SHIFT           (0U)
36160 /*! INP - Input number for CTIMER
36161  *  0b0000000..CT_INP0 input is selected
36162  *  0b0000001..CT_INP1 input is selected
36163  *  0b0000010..CT_INP2 input is selected
36164  *  0b0000011..CT_INP3 input is selected
36165  *  0b0000100..CT_INP4 input is selected
36166  *  0b0000101..CT_INP5 input is selected
36167  *  0b0000110..CT_INP6 input is selected
36168  *  0b0000111..CT_INP7 input is selected
36169  *  0b0001000..CT_INP8 input is selected
36170  *  0b0001001..CT_INP9 input is selected
36171  *  0b0001010..CT_INP10 input is selected
36172  *  0b0001011..CT_INP11 input is selected
36173  *  0b0001100..CT_INP12 input is selected
36174  *  0b0001101..CT_INP13 input is selected
36175  *  0b0001110..CT_INP14 input is selected
36176  *  0b0001111..CT_INP15 input is selected
36177  *  0b0010000..CT_INP16 input is selected
36178  *  0b0010001..CT_INP17 input is selected
36179  *  0b0010010..CT_INP18 input is selected
36180  *  0b0010011..CT_INP19 input is selected
36181  *  0b0010100..usb0 start of frame input is selected
36182  *  0b0010101..usb1 start of frame input is selected
36183  *  0b0010110..DCDC_BURST_ACTIVE input is selected
36184  *  0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected
36185  *  0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected
36186  *  0b0011001..ADC0_IRQ input is selected
36187  *  0b0011010..ADC1_IRQ input is selected
36188  *  0b0011011..CMP0_OUT input is selected
36189  *  0b0011100..CMP1_OUT input is selected
36190  *  0b0011101..CMP2_OUT input is selected
36191  *  0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected
36192  *  0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected
36193  *  0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected
36194  *  0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected
36195  *  0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected
36196  *  0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected
36197  *  0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected
36198  *  0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected
36199  *  0b0100110..QDC0_CMP/POS_MATCH input is selected
36200  *  0b0100111..QDC1_CMP/POS_MATCH input is selected
36201  *  0b0101000..EVTG_OUT0A input is selected
36202  *  0b0101001..EVTG_OUT0B input is selected
36203  *  0b0101010..EVTG_OUT1A input is selected
36204  *  0b0101011..EVTG_OUT1B input is selected
36205  *  0b0101100..EVTG_OUT2A input is selected
36206  *  0b0101101..EVTG_OUT2B input is selected
36207  *  0b0101110..EVTG_OUT3A input is selected
36208  *  0b0101111..EVTG_OUT3B input is selected
36209  *  0b0110000..Reserved
36210  *  0b0110001..Reserved
36211  *  0b0110010..LP_FLEXCOMM0 trig 0 input is selected
36212  *  0b0110011..LP_FLEXCOMM0 trig 1 input is selected
36213  *  0b0110100..LP_FLEXCOMM0 trig 2 input is selected
36214  *  0b0110101..LP_FLEXCOMM1 trig 0 input is selected
36215  *  0b0110110..LP_FLEXCOMM1 trig 1 input is selected
36216  *  0b0110111..LP_FLEXCOMM1 trig 2 input is selected
36217  *  0b0111000..LP_FLEXCOMM2 trig 0 input is selected
36218  *  0b0111001..LP_FLEXCOMM2 trig 1 input is selected
36219  *  0b0111010..LP_FLEXCOMM2 trig 2 input is selected
36220  *  0b0111011..LP_FLEXCOMM3 trig 0 input is selected
36221  *  0b0111100..LP_FLEXCOMM3 trig 1 input is selected
36222  *  0b0111101..LP_FLEXCOMM3 trig 2 input is selected
36223  *  0b0111110..LP_FLEXCOMM3 trig 3 input is selected
36224  *  0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected
36225  *  0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected
36226  *  *..
36227  */
36228 #define INPUTMUX_CTIMER1CAP0_INP(x)              (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER1CAP0_INP_SHIFT)) & INPUTMUX_CTIMER1CAP0_INP_MASK)
36229 /*! @} */
36230 
36231 /*! @name CTIMER1CAP1 - Capture Select Register for CTIMER Inputs */
36232 /*! @{ */
36233 
36234 #define INPUTMUX_CTIMER1CAP1_INP_MASK            (0x7FU)
36235 #define INPUTMUX_CTIMER1CAP1_INP_SHIFT           (0U)
36236 /*! INP - Input number for CTIMER
36237  *  0b0000000..CT_INP0 input is selected
36238  *  0b0000001..CT_INP1 input is selected
36239  *  0b0000010..CT_INP2 input is selected
36240  *  0b0000011..CT_INP3 input is selected
36241  *  0b0000100..CT_INP4 input is selected
36242  *  0b0000101..CT_INP5 input is selected
36243  *  0b0000110..CT_INP6 input is selected
36244  *  0b0000111..CT_INP7 input is selected
36245  *  0b0001000..CT_INP8 input is selected
36246  *  0b0001001..CT_INP9 input is selected
36247  *  0b0001010..CT_INP10 input is selected
36248  *  0b0001011..CT_INP11 input is selected
36249  *  0b0001100..CT_INP12 input is selected
36250  *  0b0001101..CT_INP13 input is selected
36251  *  0b0001110..CT_INP14 input is selected
36252  *  0b0001111..CT_INP15 input is selected
36253  *  0b0010000..CT_INP16 input is selected
36254  *  0b0010001..CT_INP17 input is selected
36255  *  0b0010010..CT_INP18 input is selected
36256  *  0b0010011..CT_INP19 input is selected
36257  *  0b0010100..usb0 start of frame input is selected
36258  *  0b0010101..usb1 start of frame input is selected
36259  *  0b0010110..DCDC_BURST_ACTIVE input is selected
36260  *  0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected
36261  *  0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected
36262  *  0b0011001..ADC0_IRQ input is selected
36263  *  0b0011010..ADC1_IRQ input is selected
36264  *  0b0011011..CMP0_OUT input is selected
36265  *  0b0011100..CMP1_OUT input is selected
36266  *  0b0011101..CMP2_OUT input is selected
36267  *  0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected
36268  *  0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected
36269  *  0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected
36270  *  0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected
36271  *  0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected
36272  *  0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected
36273  *  0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected
36274  *  0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected
36275  *  0b0100110..QDC0_CMP/POS_MATCH input is selected
36276  *  0b0100111..QDC1_CMP/POS_MATCH input is selected
36277  *  0b0101000..EVTG_OUT0A input is selected
36278  *  0b0101001..EVTG_OUT0B input is selected
36279  *  0b0101010..EVTG_OUT1A input is selected
36280  *  0b0101011..EVTG_OUT1B input is selected
36281  *  0b0101100..EVTG_OUT2A input is selected
36282  *  0b0101101..EVTG_OUT2B input is selected
36283  *  0b0101110..EVTG_OUT3A input is selected
36284  *  0b0101111..EVTG_OUT3B input is selected
36285  *  0b0110000..Reserved
36286  *  0b0110001..Reserved
36287  *  0b0110010..LP_FLEXCOMM0 trig 0 input is selected
36288  *  0b0110011..LP_FLEXCOMM0 trig 1 input is selected
36289  *  0b0110100..LP_FLEXCOMM0 trig 2 input is selected
36290  *  0b0110101..LP_FLEXCOMM1 trig 0 input is selected
36291  *  0b0110110..LP_FLEXCOMM1 trig 1 input is selected
36292  *  0b0110111..LP_FLEXCOMM1 trig 2 input is selected
36293  *  0b0111000..LP_FLEXCOMM2 trig 0 input is selected
36294  *  0b0111001..LP_FLEXCOMM2 trig 1 input is selected
36295  *  0b0111010..LP_FLEXCOMM2 trig 2 input is selected
36296  *  0b0111011..LP_FLEXCOMM3 trig 0 input is selected
36297  *  0b0111100..LP_FLEXCOMM3 trig 1 input is selected
36298  *  0b0111101..LP_FLEXCOMM3 trig 2 input is selected
36299  *  0b0111110..LP_FLEXCOMM3 trig 3 input is selected
36300  *  0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected
36301  *  0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected
36302  *  *..
36303  */
36304 #define INPUTMUX_CTIMER1CAP1_INP(x)              (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER1CAP1_INP_SHIFT)) & INPUTMUX_CTIMER1CAP1_INP_MASK)
36305 /*! @} */
36306 
36307 /*! @name CTIMER1CAP2 - Capture Select Register for CTIMER Inputs */
36308 /*! @{ */
36309 
36310 #define INPUTMUX_CTIMER1CAP2_INP_MASK            (0x7FU)
36311 #define INPUTMUX_CTIMER1CAP2_INP_SHIFT           (0U)
36312 /*! INP - Input number for CTIMER
36313  *  0b0000000..CT_INP0 input is selected
36314  *  0b0000001..CT_INP1 input is selected
36315  *  0b0000010..CT_INP2 input is selected
36316  *  0b0000011..CT_INP3 input is selected
36317  *  0b0000100..CT_INP4 input is selected
36318  *  0b0000101..CT_INP5 input is selected
36319  *  0b0000110..CT_INP6 input is selected
36320  *  0b0000111..CT_INP7 input is selected
36321  *  0b0001000..CT_INP8 input is selected
36322  *  0b0001001..CT_INP9 input is selected
36323  *  0b0001010..CT_INP10 input is selected
36324  *  0b0001011..CT_INP11 input is selected
36325  *  0b0001100..CT_INP12 input is selected
36326  *  0b0001101..CT_INP13 input is selected
36327  *  0b0001110..CT_INP14 input is selected
36328  *  0b0001111..CT_INP15 input is selected
36329  *  0b0010000..CT_INP16 input is selected
36330  *  0b0010001..CT_INP17 input is selected
36331  *  0b0010010..CT_INP18 input is selected
36332  *  0b0010011..CT_INP19 input is selected
36333  *  0b0010100..usb0 start of frame input is selected
36334  *  0b0010101..usb1 start of frame input is selected
36335  *  0b0010110..DCDC_BURST_ACTIVE input is selected
36336  *  0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected
36337  *  0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected
36338  *  0b0011001..ADC0_IRQ input is selected
36339  *  0b0011010..ADC1_IRQ input is selected
36340  *  0b0011011..CMP0_OUT input is selected
36341  *  0b0011100..CMP1_OUT input is selected
36342  *  0b0011101..CMP2_OUT input is selected
36343  *  0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected
36344  *  0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected
36345  *  0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected
36346  *  0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected
36347  *  0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected
36348  *  0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected
36349  *  0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected
36350  *  0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected
36351  *  0b0100110..QDC0_CMP/POS_MATCH input is selected
36352  *  0b0100111..QDC1_CMP/POS_MATCH input is selected
36353  *  0b0101000..EVTG_OUT0A input is selected
36354  *  0b0101001..EVTG_OUT0B input is selected
36355  *  0b0101010..EVTG_OUT1A input is selected
36356  *  0b0101011..EVTG_OUT1B input is selected
36357  *  0b0101100..EVTG_OUT2A input is selected
36358  *  0b0101101..EVTG_OUT2B input is selected
36359  *  0b0101110..EVTG_OUT3A input is selected
36360  *  0b0101111..EVTG_OUT3B input is selected
36361  *  0b0110000..Reserved
36362  *  0b0110001..Reserved
36363  *  0b0110010..LP_FLEXCOMM0 trig 0 input is selected
36364  *  0b0110011..LP_FLEXCOMM0 trig 1 input is selected
36365  *  0b0110100..LP_FLEXCOMM0 trig 2 input is selected
36366  *  0b0110101..LP_FLEXCOMM1 trig 0 input is selected
36367  *  0b0110110..LP_FLEXCOMM1 trig 1 input is selected
36368  *  0b0110111..LP_FLEXCOMM1 trig 2 input is selected
36369  *  0b0111000..LP_FLEXCOMM2 trig 0 input is selected
36370  *  0b0111001..LP_FLEXCOMM2 trig 1 input is selected
36371  *  0b0111010..LP_FLEXCOMM2 trig 2 input is selected
36372  *  0b0111011..LP_FLEXCOMM3 trig 0 input is selected
36373  *  0b0111100..LP_FLEXCOMM3 trig 1 input is selected
36374  *  0b0111101..LP_FLEXCOMM3 trig 2 input is selected
36375  *  0b0111110..LP_FLEXCOMM3 trig 3 input is selected
36376  *  0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected
36377  *  0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected
36378  *  *..
36379  */
36380 #define INPUTMUX_CTIMER1CAP2_INP(x)              (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER1CAP2_INP_SHIFT)) & INPUTMUX_CTIMER1CAP2_INP_MASK)
36381 /*! @} */
36382 
36383 /*! @name CTIMER1CAP3 - Capture Select Register for CTIMER Inputs */
36384 /*! @{ */
36385 
36386 #define INPUTMUX_CTIMER1CAP3_INP_MASK            (0x7FU)
36387 #define INPUTMUX_CTIMER1CAP3_INP_SHIFT           (0U)
36388 /*! INP - Input number for CTIMER
36389  *  0b0000000..CT_INP0 input is selected
36390  *  0b0000001..CT_INP1 input is selected
36391  *  0b0000010..CT_INP2 input is selected
36392  *  0b0000011..CT_INP3 input is selected
36393  *  0b0000100..CT_INP4 input is selected
36394  *  0b0000101..CT_INP5 input is selected
36395  *  0b0000110..CT_INP6 input is selected
36396  *  0b0000111..CT_INP7 input is selected
36397  *  0b0001000..CT_INP8 input is selected
36398  *  0b0001001..CT_INP9 input is selected
36399  *  0b0001010..CT_INP10 input is selected
36400  *  0b0001011..CT_INP11 input is selected
36401  *  0b0001100..CT_INP12 input is selected
36402  *  0b0001101..CT_INP13 input is selected
36403  *  0b0001110..CT_INP14 input is selected
36404  *  0b0001111..CT_INP15 input is selected
36405  *  0b0010000..CT_INP16 input is selected
36406  *  0b0010001..CT_INP17 input is selected
36407  *  0b0010010..CT_INP18 input is selected
36408  *  0b0010011..CT_INP19 input is selected
36409  *  0b0010100..usb0 start of frame input is selected
36410  *  0b0010101..usb1 start of frame input is selected
36411  *  0b0010110..DCDC_BURST_ACTIVE input is selected
36412  *  0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected
36413  *  0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected
36414  *  0b0011001..ADC0_IRQ input is selected
36415  *  0b0011010..ADC1_IRQ input is selected
36416  *  0b0011011..CMP0_OUT input is selected
36417  *  0b0011100..CMP1_OUT input is selected
36418  *  0b0011101..CMP2_OUT input is selected
36419  *  0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected
36420  *  0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected
36421  *  0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected
36422  *  0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected
36423  *  0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected
36424  *  0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected
36425  *  0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected
36426  *  0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected
36427  *  0b0100110..QDC0_CMP/POS_MATCH input is selected
36428  *  0b0100111..QDC1_CMP/POS_MATCH input is selected
36429  *  0b0101000..EVTG_OUT0A input is selected
36430  *  0b0101001..EVTG_OUT0B input is selected
36431  *  0b0101010..EVTG_OUT1A input is selected
36432  *  0b0101011..EVTG_OUT1B input is selected
36433  *  0b0101100..EVTG_OUT2A input is selected
36434  *  0b0101101..EVTG_OUT2B input is selected
36435  *  0b0101110..EVTG_OUT3A input is selected
36436  *  0b0101111..EVTG_OUT3B input is selected
36437  *  0b0110000..Reserved
36438  *  0b0110001..Reserved
36439  *  0b0110010..LP_FLEXCOMM0 trig 0 input is selected
36440  *  0b0110011..LP_FLEXCOMM0 trig 1 input is selected
36441  *  0b0110100..LP_FLEXCOMM0 trig 2 input is selected
36442  *  0b0110101..LP_FLEXCOMM1 trig 0 input is selected
36443  *  0b0110110..LP_FLEXCOMM1 trig 1 input is selected
36444  *  0b0110111..LP_FLEXCOMM1 trig 2 input is selected
36445  *  0b0111000..LP_FLEXCOMM2 trig 0 input is selected
36446  *  0b0111001..LP_FLEXCOMM2 trig 1 input is selected
36447  *  0b0111010..LP_FLEXCOMM2 trig 2 input is selected
36448  *  0b0111011..LP_FLEXCOMM3 trig 0 input is selected
36449  *  0b0111100..LP_FLEXCOMM3 trig 1 input is selected
36450  *  0b0111101..LP_FLEXCOMM3 trig 2 input is selected
36451  *  0b0111110..LP_FLEXCOMM3 trig 3 input is selected
36452  *  0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected
36453  *  0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected
36454  *  *..
36455  */
36456 #define INPUTMUX_CTIMER1CAP3_INP(x)              (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER1CAP3_INP_SHIFT)) & INPUTMUX_CTIMER1CAP3_INP_MASK)
36457 /*! @} */
36458 
36459 /*! @name TIMER1TRIG - Trigger Register for CTIMER */
36460 /*! @{ */
36461 
36462 #define INPUTMUX_TIMER1TRIG_INP_MASK             (0x7FU)
36463 #define INPUTMUX_TIMER1TRIG_INP_SHIFT            (0U)
36464 /*! INP - Input number for CTIMER
36465  *  0b0000000..CT_INP0 input is selected
36466  *  0b0000001..CT_INP1 input is selected
36467  *  0b0000010..CT_INP2 input is selected
36468  *  0b0000011..CT_INP3 input is selected
36469  *  0b0000100..CT_INP4 input is selected
36470  *  0b0000101..CT_INP5 input is selected
36471  *  0b0000110..CT_INP6 input is selected
36472  *  0b0000111..CT_INP7 input is selected
36473  *  0b0001000..CT_INP8 input is selected
36474  *  0b0001001..CT_INP9 input is selected
36475  *  0b0001010..CT_INP10 input is selected
36476  *  0b0001011..CT_INP11 input is selected
36477  *  0b0001100..CT_INP12 input is selected
36478  *  0b0001101..CT_INP13 input is selected
36479  *  0b0001110..CT_INP14 input is selected
36480  *  0b0001111..CT_INP15 input is selected
36481  *  0b0010000..CT_INP16 input is selected
36482  *  0b0010001..CT_INP17 input is selected
36483  *  0b0010010..CT_INP18 input is selected
36484  *  0b0010011..CT_INP19 input is selected
36485  *  0b0010100..usb0 start of frame input is selected
36486  *  0b0010101..usb1 start of frame input is selected
36487  *  0b0010110..DCDC_BURST_ACTIVE input is selected
36488  *  0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected
36489  *  0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected
36490  *  0b0011001..ADC0_IRQ input is selected
36491  *  0b0011010..ADC1_IRQ input is selected
36492  *  0b0011011..CMP0_OUT input is selected
36493  *  0b0011100..CMP1_OUT input is selected
36494  *  0b0011101..CMP2_OUT input is selected
36495  *  0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected
36496  *  0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected
36497  *  0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected
36498  *  0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected
36499  *  0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected
36500  *  0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected
36501  *  0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected
36502  *  0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected
36503  *  0b0100110..QDC0_CMP/POS_MATCH input is selected
36504  *  0b0100111..QDC1_CMP/POS_MATCH input is selected
36505  *  0b0101000..EVTG_OUT0A input is selected
36506  *  0b0101001..EVTG_OUT0B input is selected
36507  *  0b0101010..EVTG_OUT1A input is selected
36508  *  0b0101011..EVTG_OUT1B input is selected
36509  *  0b0101100..EVTG_OUT2A input is selected
36510  *  0b0101101..EVTG_OUT2B input is selected
36511  *  0b0101110..EVTG_OUT3A input is selected
36512  *  0b0101111..EVTG_OUT3B input is selected
36513  *  0b0110000..Reserved
36514  *  0b0110001..Reserved
36515  *  0b0110010..LP_FLEXCOMM0 trig 0 input is selected
36516  *  0b0110011..LP_FLEXCOMM0 trig 1 input is selected
36517  *  0b0110100..LP_FLEXCOMM0 trig 2 input is selected
36518  *  0b0110101..LP_FLEXCOMM1 trig 0 input is selected
36519  *  0b0110110..LP_FLEXCOMM1 trig 1 input is selected
36520  *  0b0110111..LP_FLEXCOMM1 trig 2 input is selected
36521  *  0b0111000..LP_FLEXCOMM2 trig 0 input is selected
36522  *  0b0111001..LP_FLEXCOMM2 trig 1 input is selected
36523  *  0b0111010..LP_FLEXCOMM2 trig 2 input is selected
36524  *  0b0111011..LP_FLEXCOMM3 trig 0 input is selected
36525  *  0b0111100..LP_FLEXCOMM3 trig 1 input is selected
36526  *  0b0111101..LP_FLEXCOMM3 trig 2 input is selected
36527  *  0b0111110..LP_FLEXCOMM3 trig 3 input is selected
36528  *  0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected
36529  *  0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected
36530  *  *..
36531  */
36532 #define INPUTMUX_TIMER1TRIG_INP(x)               (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER1TRIG_INP_SHIFT)) & INPUTMUX_TIMER1TRIG_INP_MASK)
36533 /*! @} */
36534 
36535 /*! @name CTIMER2CAP0 - Capture Select Register for CTIMER Inputs */
36536 /*! @{ */
36537 
36538 #define INPUTMUX_CTIMER2CAP0_INP_MASK            (0x7FU)
36539 #define INPUTMUX_CTIMER2CAP0_INP_SHIFT           (0U)
36540 /*! INP - Input number for CTIMER
36541  *  0b0000000..CT_INP0 input is selected
36542  *  0b0000001..CT_INP1 input is selected
36543  *  0b0000010..CT_INP2 input is selected
36544  *  0b0000011..CT_INP3 input is selected
36545  *  0b0000100..CT_INP4 input is selected
36546  *  0b0000101..CT_INP5 input is selected
36547  *  0b0000110..CT_INP6 input is selected
36548  *  0b0000111..CT_INP7 input is selected
36549  *  0b0001000..CT_INP8 input is selected
36550  *  0b0001001..CT_INP9 input is selected
36551  *  0b0001010..CT_INP10 input is selected
36552  *  0b0001011..CT_INP11 input is selected
36553  *  0b0001100..CT_INP12 input is selected
36554  *  0b0001101..CT_INP13 input is selected
36555  *  0b0001110..CT_INP14 input is selected
36556  *  0b0001111..CT_INP15 input is selected
36557  *  0b0010000..CT_INP16 input is selected
36558  *  0b0010001..CT_INP17 input is selected
36559  *  0b0010010..CT_INP18 input is selected
36560  *  0b0010011..CT_INP19 input is selected
36561  *  0b0010100..usb0 start of frame input is selected
36562  *  0b0010101..usb1 start of frame input is selected
36563  *  0b0010110..DCDC_BURST_ACTIVE input is selected
36564  *  0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected
36565  *  0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected
36566  *  0b0011001..ADC0_IRQ input is selected
36567  *  0b0011010..ADC1_IRQ input is selected
36568  *  0b0011011..CMP0_OUT input is selected
36569  *  0b0011100..CMP1_OUT input is selected
36570  *  0b0011101..CMP2_OUT input is selected
36571  *  0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected
36572  *  0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected
36573  *  0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected
36574  *  0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected
36575  *  0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected
36576  *  0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected
36577  *  0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected
36578  *  0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected
36579  *  0b0100110..QDC0_CMP/POS_MATCH input is selected
36580  *  0b0100111..QDC1_CMP/POS_MATCH input is selected
36581  *  0b0101000..EVTG_OUT0A input is selected
36582  *  0b0101001..EVTG_OUT0B input is selected
36583  *  0b0101010..EVTG_OUT1A input is selected
36584  *  0b0101011..EVTG_OUT1B input is selected
36585  *  0b0101100..EVTG_OUT2A input is selected
36586  *  0b0101101..EVTG_OUT2B input is selected
36587  *  0b0101110..EVTG_OUT3A input is selected
36588  *  0b0101111..EVTG_OUT3B input is selected
36589  *  0b0110000..Reserved
36590  *  0b0110001..Reserved
36591  *  0b0110010..LP_FLEXCOMM0 trig 0 input is selected
36592  *  0b0110011..LP_FLEXCOMM0 trig 1 input is selected
36593  *  0b0110100..LP_FLEXCOMM0 trig 2 input is selected
36594  *  0b0110101..LP_FLEXCOMM1 trig 0 input is selected
36595  *  0b0110110..LP_FLEXCOMM1 trig 1 input is selected
36596  *  0b0110111..LP_FLEXCOMM1 trig 2 input is selected
36597  *  0b0111000..LP_FLEXCOMM2 trig 0 input is selected
36598  *  0b0111001..LP_FLEXCOMM2 trig 1 input is selected
36599  *  0b0111010..LP_FLEXCOMM2 trig 2 input is selected
36600  *  0b0111011..LP_FLEXCOMM3 trig 0 input is selected
36601  *  0b0111100..LP_FLEXCOMM3 trig 1 input is selected
36602  *  0b0111101..LP_FLEXCOMM3 trig 2 input is selected
36603  *  0b0111110..LP_FLEXCOMM3 trig 3 input is selected
36604  *  0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected
36605  *  0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected
36606  *  *..
36607  */
36608 #define INPUTMUX_CTIMER2CAP0_INP(x)              (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER2CAP0_INP_SHIFT)) & INPUTMUX_CTIMER2CAP0_INP_MASK)
36609 /*! @} */
36610 
36611 /*! @name CTIMER2CAP1 - Capture Select Register for CTIMER Inputs */
36612 /*! @{ */
36613 
36614 #define INPUTMUX_CTIMER2CAP1_INP_MASK            (0x7FU)
36615 #define INPUTMUX_CTIMER2CAP1_INP_SHIFT           (0U)
36616 /*! INP - Input number for CTIMER
36617  *  0b0000000..CT_INP0 input is selected
36618  *  0b0000001..CT_INP1 input is selected
36619  *  0b0000010..CT_INP2 input is selected
36620  *  0b0000011..CT_INP3 input is selected
36621  *  0b0000100..CT_INP4 input is selected
36622  *  0b0000101..CT_INP5 input is selected
36623  *  0b0000110..CT_INP6 input is selected
36624  *  0b0000111..CT_INP7 input is selected
36625  *  0b0001000..CT_INP8 input is selected
36626  *  0b0001001..CT_INP9 input is selected
36627  *  0b0001010..CT_INP10 input is selected
36628  *  0b0001011..CT_INP11 input is selected
36629  *  0b0001100..CT_INP12 input is selected
36630  *  0b0001101..CT_INP13 input is selected
36631  *  0b0001110..CT_INP14 input is selected
36632  *  0b0001111..CT_INP15 input is selected
36633  *  0b0010000..CT_INP16 input is selected
36634  *  0b0010001..CT_INP17 input is selected
36635  *  0b0010010..CT_INP18 input is selected
36636  *  0b0010011..CT_INP19 input is selected
36637  *  0b0010100..usb0 start of frame input is selected
36638  *  0b0010101..usb1 start of frame input is selected
36639  *  0b0010110..DCDC_BURST_ACTIVE input is selected
36640  *  0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected
36641  *  0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected
36642  *  0b0011001..ADC0_IRQ input is selected
36643  *  0b0011010..ADC1_IRQ input is selected
36644  *  0b0011011..CMP0_OUT input is selected
36645  *  0b0011100..CMP1_OUT input is selected
36646  *  0b0011101..CMP2_OUT input is selected
36647  *  0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected
36648  *  0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected
36649  *  0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected
36650  *  0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected
36651  *  0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected
36652  *  0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected
36653  *  0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected
36654  *  0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected
36655  *  0b0100110..QDC0_CMP/POS_MATCH input is selected
36656  *  0b0100111..QDC1_CMP/POS_MATCH input is selected
36657  *  0b0101000..EVTG_OUT0A input is selected
36658  *  0b0101001..EVTG_OUT0B input is selected
36659  *  0b0101010..EVTG_OUT1A input is selected
36660  *  0b0101011..EVTG_OUT1B input is selected
36661  *  0b0101100..EVTG_OUT2A input is selected
36662  *  0b0101101..EVTG_OUT2B input is selected
36663  *  0b0101110..EVTG_OUT3A input is selected
36664  *  0b0101111..EVTG_OUT3B input is selected
36665  *  0b0110000..Reserved
36666  *  0b0110001..Reserved
36667  *  0b0110010..LP_FLEXCOMM0 trig 0 input is selected
36668  *  0b0110011..LP_FLEXCOMM0 trig 1 input is selected
36669  *  0b0110100..LP_FLEXCOMM0 trig 2 input is selected
36670  *  0b0110101..LP_FLEXCOMM1 trig 0 input is selected
36671  *  0b0110110..LP_FLEXCOMM1 trig 1 input is selected
36672  *  0b0110111..LP_FLEXCOMM1 trig 2 input is selected
36673  *  0b0111000..LP_FLEXCOMM2 trig 0 input is selected
36674  *  0b0111001..LP_FLEXCOMM2 trig 1 input is selected
36675  *  0b0111010..LP_FLEXCOMM2 trig 2 input is selected
36676  *  0b0111011..LP_FLEXCOMM3 trig 0 input is selected
36677  *  0b0111100..LP_FLEXCOMM3 trig 1 input is selected
36678  *  0b0111101..LP_FLEXCOMM3 trig 2 input is selected
36679  *  0b0111110..LP_FLEXCOMM3 trig 3 input is selected
36680  *  0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected
36681  *  0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected
36682  *  *..
36683  */
36684 #define INPUTMUX_CTIMER2CAP1_INP(x)              (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER2CAP1_INP_SHIFT)) & INPUTMUX_CTIMER2CAP1_INP_MASK)
36685 /*! @} */
36686 
36687 /*! @name CTIMER2CAP2 - Capture Select Register for CTIMER Inputs */
36688 /*! @{ */
36689 
36690 #define INPUTMUX_CTIMER2CAP2_INP_MASK            (0x7FU)
36691 #define INPUTMUX_CTIMER2CAP2_INP_SHIFT           (0U)
36692 /*! INP - Input number for CTIMER
36693  *  0b0000000..CT_INP0 input is selected
36694  *  0b0000001..CT_INP1 input is selected
36695  *  0b0000010..CT_INP2 input is selected
36696  *  0b0000011..CT_INP3 input is selected
36697  *  0b0000100..CT_INP4 input is selected
36698  *  0b0000101..CT_INP5 input is selected
36699  *  0b0000110..CT_INP6 input is selected
36700  *  0b0000111..CT_INP7 input is selected
36701  *  0b0001000..CT_INP8 input is selected
36702  *  0b0001001..CT_INP9 input is selected
36703  *  0b0001010..CT_INP10 input is selected
36704  *  0b0001011..CT_INP11 input is selected
36705  *  0b0001100..CT_INP12 input is selected
36706  *  0b0001101..CT_INP13 input is selected
36707  *  0b0001110..CT_INP14 input is selected
36708  *  0b0001111..CT_INP15 input is selected
36709  *  0b0010000..CT_INP16 input is selected
36710  *  0b0010001..CT_INP17 input is selected
36711  *  0b0010010..CT_INP18 input is selected
36712  *  0b0010011..CT_INP19 input is selected
36713  *  0b0010100..usb0 start of frame input is selected
36714  *  0b0010101..usb1 start of frame input is selected
36715  *  0b0010110..DCDC_BURST_ACTIVE input is selected
36716  *  0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected
36717  *  0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected
36718  *  0b0011001..ADC0_IRQ input is selected
36719  *  0b0011010..ADC1_IRQ input is selected
36720  *  0b0011011..CMP0_OUT input is selected
36721  *  0b0011100..CMP1_OUT input is selected
36722  *  0b0011101..CMP2_OUT input is selected
36723  *  0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected
36724  *  0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected
36725  *  0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected
36726  *  0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected
36727  *  0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected
36728  *  0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected
36729  *  0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected
36730  *  0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected
36731  *  0b0100110..QDC0_CMP/POS_MATCH input is selected
36732  *  0b0100111..QDC1_CMP/POS_MATCH input is selected
36733  *  0b0101000..EVTG_OUT0A input is selected
36734  *  0b0101001..EVTG_OUT0B input is selected
36735  *  0b0101010..EVTG_OUT1A input is selected
36736  *  0b0101011..EVTG_OUT1B input is selected
36737  *  0b0101100..EVTG_OUT2A input is selected
36738  *  0b0101101..EVTG_OUT2B input is selected
36739  *  0b0101110..EVTG_OUT3A input is selected
36740  *  0b0101111..EVTG_OUT3B input is selected
36741  *  0b0110000..Reserved
36742  *  0b0110001..Reserved
36743  *  0b0110010..LP_FLEXCOMM0 trig 0 input is selected
36744  *  0b0110011..LP_FLEXCOMM0 trig 1 input is selected
36745  *  0b0110100..LP_FLEXCOMM0 trig 2 input is selected
36746  *  0b0110101..LP_FLEXCOMM1 trig 0 input is selected
36747  *  0b0110110..LP_FLEXCOMM1 trig 1 input is selected
36748  *  0b0110111..LP_FLEXCOMM1 trig 2 input is selected
36749  *  0b0111000..LP_FLEXCOMM2 trig 0 input is selected
36750  *  0b0111001..LP_FLEXCOMM2 trig 1 input is selected
36751  *  0b0111010..LP_FLEXCOMM2 trig 2 input is selected
36752  *  0b0111011..LP_FLEXCOMM3 trig 0 input is selected
36753  *  0b0111100..LP_FLEXCOMM3 trig 1 input is selected
36754  *  0b0111101..LP_FLEXCOMM3 trig 2 input is selected
36755  *  0b0111110..LP_FLEXCOMM3 trig 3 input is selected
36756  *  0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected
36757  *  0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected
36758  *  *..
36759  */
36760 #define INPUTMUX_CTIMER2CAP2_INP(x)              (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER2CAP2_INP_SHIFT)) & INPUTMUX_CTIMER2CAP2_INP_MASK)
36761 /*! @} */
36762 
36763 /*! @name CTIMER2CAP3 - Capture Select Register for CTIMER Inputs */
36764 /*! @{ */
36765 
36766 #define INPUTMUX_CTIMER2CAP3_INP_MASK            (0x7FU)
36767 #define INPUTMUX_CTIMER2CAP3_INP_SHIFT           (0U)
36768 /*! INP - Input number for CTIMER
36769  *  0b0000000..CT_INP0 input is selected
36770  *  0b0000001..CT_INP1 input is selected
36771  *  0b0000010..CT_INP2 input is selected
36772  *  0b0000011..CT_INP3 input is selected
36773  *  0b0000100..CT_INP4 input is selected
36774  *  0b0000101..CT_INP5 input is selected
36775  *  0b0000110..CT_INP6 input is selected
36776  *  0b0000111..CT_INP7 input is selected
36777  *  0b0001000..CT_INP8 input is selected
36778  *  0b0001001..CT_INP9 input is selected
36779  *  0b0001010..CT_INP10 input is selected
36780  *  0b0001011..CT_INP11 input is selected
36781  *  0b0001100..CT_INP12 input is selected
36782  *  0b0001101..CT_INP13 input is selected
36783  *  0b0001110..CT_INP14 input is selected
36784  *  0b0001111..CT_INP15 input is selected
36785  *  0b0010000..CT_INP16 input is selected
36786  *  0b0010001..CT_INP17 input is selected
36787  *  0b0010010..CT_INP18 input is selected
36788  *  0b0010011..CT_INP19 input is selected
36789  *  0b0010100..usb0 start of frame input is selected
36790  *  0b0010101..usb1 start of frame input is selected
36791  *  0b0010110..DCDC_BURST_ACTIVE input is selected
36792  *  0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected
36793  *  0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected
36794  *  0b0011001..ADC0_IRQ input is selected
36795  *  0b0011010..ADC1_IRQ input is selected
36796  *  0b0011011..CMP0_OUT input is selected
36797  *  0b0011100..CMP1_OUT input is selected
36798  *  0b0011101..CMP2_OUT input is selected
36799  *  0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected
36800  *  0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected
36801  *  0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected
36802  *  0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected
36803  *  0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected
36804  *  0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected
36805  *  0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected
36806  *  0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected
36807  *  0b0100110..QDC0_CMP/POS_MATCH input is selected
36808  *  0b0100111..QDC1_CMP/POS_MATCH input is selected
36809  *  0b0101000..EVTG_OUT0A input is selected
36810  *  0b0101001..EVTG_OUT0B input is selected
36811  *  0b0101010..EVTG_OUT1A input is selected
36812  *  0b0101011..EVTG_OUT1B input is selected
36813  *  0b0101100..EVTG_OUT2A input is selected
36814  *  0b0101101..EVTG_OUT2B input is selected
36815  *  0b0101110..EVTG_OUT3A input is selected
36816  *  0b0101111..EVTG_OUT3B input is selected
36817  *  0b0110000..Reserved
36818  *  0b0110001..Reserved
36819  *  0b0110010..LP_FLEXCOMM0 trig 0 input is selected
36820  *  0b0110011..LP_FLEXCOMM0 trig 1 input is selected
36821  *  0b0110100..LP_FLEXCOMM0 trig 2 input is selected
36822  *  0b0110101..LP_FLEXCOMM1 trig 0 input is selected
36823  *  0b0110110..LP_FLEXCOMM1 trig 1 input is selected
36824  *  0b0110111..LP_FLEXCOMM1 trig 2 input is selected
36825  *  0b0111000..LP_FLEXCOMM2 trig 0 input is selected
36826  *  0b0111001..LP_FLEXCOMM2 trig 1 input is selected
36827  *  0b0111010..LP_FLEXCOMM2 trig 2 input is selected
36828  *  0b0111011..LP_FLEXCOMM3 trig 0 input is selected
36829  *  0b0111100..LP_FLEXCOMM3 trig 1 input is selected
36830  *  0b0111101..LP_FLEXCOMM3 trig 2 input is selected
36831  *  0b0111110..LP_FLEXCOMM3 trig 3 input is selected
36832  *  0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected
36833  *  0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected
36834  *  *..
36835  */
36836 #define INPUTMUX_CTIMER2CAP3_INP(x)              (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER2CAP3_INP_SHIFT)) & INPUTMUX_CTIMER2CAP3_INP_MASK)
36837 /*! @} */
36838 
36839 /*! @name TIMER2TRIG - Trigger Register for CTIMER */
36840 /*! @{ */
36841 
36842 #define INPUTMUX_TIMER2TRIG_INP_MASK             (0x7FU)
36843 #define INPUTMUX_TIMER2TRIG_INP_SHIFT            (0U)
36844 /*! INP - Input number for CTIMER
36845  *  0b0000000..CT_INP0 input is selected
36846  *  0b0000001..CT_INP1 input is selected
36847  *  0b0000010..CT_INP2 input is selected
36848  *  0b0000011..CT_INP3 input is selected
36849  *  0b0000100..CT_INP4 input is selected
36850  *  0b0000101..CT_INP5 input is selected
36851  *  0b0000110..CT_INP6 input is selected
36852  *  0b0000111..CT_INP7 input is selected
36853  *  0b0001000..CT_INP8 input is selected
36854  *  0b0001001..CT_INP9 input is selected
36855  *  0b0001010..CT_INP10 input is selected
36856  *  0b0001011..CT_INP11 input is selected
36857  *  0b0001100..CT_INP12 input is selected
36858  *  0b0001101..CT_INP13 input is selected
36859  *  0b0001110..CT_INP14 input is selected
36860  *  0b0001111..CT_INP15 input is selected
36861  *  0b0010000..CT_INP16 input is selected
36862  *  0b0010001..CT_INP17 input is selected
36863  *  0b0010010..CT_INP18 input is selected
36864  *  0b0010011..CT_INP19 input is selected
36865  *  0b0010100..usb0 start of frame input is selected
36866  *  0b0010101..usb1 start of frame input is selected
36867  *  0b0010110..DCDC_BURST_ACTIVE input is selected
36868  *  0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected
36869  *  0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected
36870  *  0b0011001..ADC0_IRQ input is selected
36871  *  0b0011010..ADC1_IRQ input is selected
36872  *  0b0011011..CMP0_OUT input is selected
36873  *  0b0011100..CMP1_OUT input is selected
36874  *  0b0011101..CMP2_OUT input is selected
36875  *  0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected
36876  *  0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected
36877  *  0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected
36878  *  0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected
36879  *  0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected
36880  *  0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected
36881  *  0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected
36882  *  0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected
36883  *  0b0100110..QDC0_CMP/POS_MATCH input is selected
36884  *  0b0100111..QDC1_CMP/POS_MATCH input is selected
36885  *  0b0101000..EVTG_OUT0A input is selected
36886  *  0b0101001..EVTG_OUT0B input is selected
36887  *  0b0101010..EVTG_OUT1A input is selected
36888  *  0b0101011..EVTG_OUT1B input is selected
36889  *  0b0101100..EVTG_OUT2A input is selected
36890  *  0b0101101..EVTG_OUT2B input is selected
36891  *  0b0101110..EVTG_OUT3A input is selected
36892  *  0b0101111..EVTG_OUT3B input is selected
36893  *  0b0110000..Reserved
36894  *  0b0110001..Reserved
36895  *  0b0110010..LP_FLEXCOMM0 trig 0 input is selected
36896  *  0b0110011..LP_FLEXCOMM0 trig 1 input is selected
36897  *  0b0110100..LP_FLEXCOMM0 trig 2 input is selected
36898  *  0b0110101..LP_FLEXCOMM1 trig 0 input is selected
36899  *  0b0110110..LP_FLEXCOMM1 trig 1 input is selected
36900  *  0b0110111..LP_FLEXCOMM1 trig 2 input is selected
36901  *  0b0111000..LP_FLEXCOMM2 trig 0 input is selected
36902  *  0b0111001..LP_FLEXCOMM2 trig 1 input is selected
36903  *  0b0111010..LP_FLEXCOMM2 trig 2 input is selected
36904  *  0b0111011..LP_FLEXCOMM3 trig 0 input is selected
36905  *  0b0111100..LP_FLEXCOMM3 trig 1 input is selected
36906  *  0b0111101..LP_FLEXCOMM3 trig 2 input is selected
36907  *  0b0111110..LP_FLEXCOMM3 trig 3 input is selected
36908  *  0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected
36909  *  0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected
36910  *  *..
36911  */
36912 #define INPUTMUX_TIMER2TRIG_INP(x)               (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER2TRIG_INP_SHIFT)) & INPUTMUX_TIMER2TRIG_INP_MASK)
36913 /*! @} */
36914 
36915 /*! @name INPUTMUX_SMARTDMA_SMARTDMAARCHB_INMUX - Inputmux Register for SMARTDMA Arch B Inputs */
36916 /*! @{ */
36917 
36918 #define INPUTMUX_INPUTMUX_SMARTDMA_SMARTDMAARCHB_INMUX_INP_MASK (0x7FU)
36919 #define INPUTMUX_INPUTMUX_SMARTDMA_SMARTDMAARCHB_INMUX_INP_SHIFT (0U)
36920 /*! INP - Input number select to SmartDMA ARCHB input
36921  *  0b0000000..FlexIO interrupt is selected as input
36922  *  0b0000001..GPIO P0_1 input is selected
36923  *  0b0000010..GPIO P0_2 input is selected
36924  *  0b0000011..GPIO P0_3 input is selected
36925  *  0b0000100..GPIO P0_4 input is selected
36926  *  0b0000101..GPIO P0_5 input is selected
36927  *  0b0000110..GPIO P0_6 input is selected
36928  *  0b0000111..GPIO P0_7 input is selected
36929  *  0b0001000..GPIO P0_8 input is selected
36930  *  0b0001001..GPIO P0_9 input is selected
36931  *  0b0001010..GPIO P0_10 input is selected
36932  *  0b0001011..GPIO P0_11 input is selected
36933  *  0b0001100..GPIO P0_12 input is selected
36934  *  0b0001101..GPIO P0_13 input is selected
36935  *  0b0001110..GPIO P0_14 input is selected
36936  *  0b0001111..GPIO P0_15 input is selected
36937  *  0b0010000..SCT0 SCT_OUT8 input is selected
36938  *  0b0010001..SCT0 SCT_OUT9 input is selected
36939  *  0b0010010..Reserved
36940  *  0b0010011..Reserved
36941  *  0b0010100..MRT0 MRT_CH0_IRQ input is selected
36942  *  0b0010101..MRT0 MRT_CH1_IRQ input is selected
36943  *  0b0010110..CTIMER4_MAT3 input is selected
36944  *  0b0010111..CTIMER4_MAT2 input is selected
36945  *  0b0011000..CTIMER3_MAT3 input is selected
36946  *  0b0011001..CTIMER3_MAT2 input is selected
36947  *  0b0011010..CTIMER1_MAT3 input is selected
36948  *  0b0011011..CTIMER1_MAT2 input is selected
36949  *  0b0011100..UTICK0 UTICK_IRQ input is selected
36950  *  0b0011101..WWDT0 WDT0_IRQ input is selected
36951  *  0b0011110..ADC0 ADC0_IRQ input is selected
36952  *  0b0011111..CMP0_IRQ input is selected
36953  *  0b0100000..Reserved
36954  *  0b0100001..LP_FLEXCOMM7_IRQ input is selected
36955  *  0b0100010..LP_FLEXCOMM6_IRQ input is selected
36956  *  0b0100011..LP_FLEXCOMM5_IRQ input is selected
36957  *  0b0100100..LP_FLEXCOMM4_IRQ input is selected
36958  *  0b0100101..LP_FLEXCOMM3_IRQ input is selected
36959  *  0b0100110..LP_FLEXCOMM2_IRQ input is selected
36960  *  0b0100111..LP_FLEXCOMM1_IRQ input is selected
36961  *  0b0101000..LP_FLEXCOMM0_IRQ input is selected
36962  *  0b0101001..DMA0_IRQ input is selected
36963  *  0b0101010..DMA1_IRQ input is selected
36964  *  0b0101011..SYS_IRQSYS_IRQ combines the CDOG IRQ, WWDT IRQ, MBC secure violation IRQ, Secure AHB Matrix secure
36965  *             violation IRQ, GDET IRQ, ELS S50 error IRQ, PKC error IRQ, and VBAT IRQ using the logical OR
36966  *             operation. input is selected
36967  *  0b0101100..RTC_COMBO_IRQ input is selected
36968  *  0b0101101..ARM_TXEV input is selected
36969  *  0b0101110..PINT0 GPIO_INT_BMATCH input is selected
36970  *  0b0101111..Reserved
36971  *  0b0110000..Reserved
36972  *  0b0110001..CMP0_OUT input is selected
36973  *  0b0110010..usb0 start of frame input is selected
36974  *  0b0110011..usb1 start of frame input is selected
36975  *  0b0110100..OSTIMER0 OS_EVENT_TIMER_IRQ input is selected
36976  *  0b0110101..ADC1_IRQ input is selected
36977  *  0b0110110..CMP0_IRQ/CMP1_IRQ/CMP2_IRQ input is selected
36978  *  0b0110111..DAC0_IRQ input is selected
36979  *  0b0111000..DAC1_IRQ/DAC2_IRQ input is selected
36980  *  0b0111001..PWM0_IRQ input is selected
36981  *  0b0111010..PWM1_IRQ input is selected
36982  *  0b0111011..QDC0_IRQ input is selected
36983  *  0b0111100..QDC1_IRQ input is selected
36984  *  0b0111101..EVTG_OUT0A input is selected
36985  *  0b0111110..EVTG_OUT1A input is selected
36986  *  0b0111111..Reserved
36987  *  0b1000000..Reserved
36988  *  0b1000001..GPIO1_alias0 GPIO1 Pin Event Trig 0 input is selected
36989  *  0b1000010..GPIO1_alias1 GPIO1 Pin Event Trig 1 input is selected
36990  *  0b1000011..GPIO2_alias0 GPIO2 Pin Event Trig 0 input is selected
36991  *  0b1000100..GPIO2_alias1 GPIO2 Pin Event Trig 1 input is selected
36992  *  0b1000101..GPIO3_alias0 GPIO3 Pin Event Trig 0 input is selected
36993  *  0b1000110..GPIO3_alias1 GPIO3 Pin Event Trig 1 input is selected
36994  *  *..
36995  */
36996 #define INPUTMUX_INPUTMUX_SMARTDMA_SMARTDMAARCHB_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_INPUTMUX_SMARTDMA_SMARTDMAARCHB_INMUX_INP_SHIFT)) & INPUTMUX_INPUTMUX_SMARTDMA_SMARTDMAARCHB_INMUX_INP_MASK)
36997 /*! @} */
36998 
36999 /* The count of INPUTMUX_INPUTMUX_SMARTDMA_SMARTDMAARCHB_INMUX */
37000 #define INPUTMUX_INPUTMUX_SMARTDMA_SMARTDMAARCHB_INMUX_COUNT (8U)
37001 
37002 /*! @name INPUTMUX_GPIO_INT_PINTSEL - Pin Interrupt Select */
37003 /*! @{ */
37004 
37005 #define INPUTMUX_INPUTMUX_GPIO_INT_PINTSEL_INP_MASK (0x7FU)
37006 #define INPUTMUX_INPUTMUX_GPIO_INT_PINTSEL_INP_SHIFT (0U)
37007 /*! INP - Pin number select for pin interrupt or pattern match engine input. For PIOx_y: INP = (x *
37008  *    32) + y. PIO0_0 to PIO1_31 correspond to numbers 0 to 63.
37009  *  0b0000000..GPIO P0_0 input is selected
37010  *  0b0000001..GPIO P0_1 input is selected
37011  *  0b0000010..GPIO P0_2 input is selected
37012  *  0b0000011..GPIO P0_3 input is selected
37013  *  0b0000100..GPIO P0_4 input is selected
37014  *  0b0000101..GPIO P0_5 input is selected
37015  *  0b0000110..GPIO P0_6 input is selected
37016  *  0b0000111..GPIO P0_7 input is selected
37017  *  0b0001000..GPIO P0_8 input is selected
37018  *  0b0001001..GPIO P0_9 input is selected
37019  *  0b0001010..GPIO P0_10 input is selected
37020  *  0b0001011..GPIO P0_11 input is selected
37021  *  0b0001100..GPIO P0_12 input is selected
37022  *  0b0001101..GPIO P0_13 input is selected
37023  *  0b0001110..GPIO P0_14 input is selected
37024  *  0b0001111..GPIO P0_15 input is selected
37025  *  0b0010000..GPIO P0_16 input is selected
37026  *  0b0010001..GPIO P0_17 input is selected
37027  *  0b0010010..GPIO P0_18 input is selected
37028  *  0b0010011..GPIO P0_19 input is selected
37029  *  0b0010100..GPIO P0_20 input is selected
37030  *  0b0010101..GPIO P0_21 input is selected
37031  *  0b0010110..GPIO P0_22 input is selected
37032  *  0b0010111..GPIO P0_23 input is selected
37033  *  0b0011000..GPIO P0_24 input is selected
37034  *  0b0011001..GPIO P0_25 input is selected
37035  *  0b0011010..GPIO P0_26 input is selected
37036  *  0b0011011..GPIO P0_27 input is selected
37037  *  0b0011100..GPIO P0_28 input is selected
37038  *  0b0011101..GPIO P0_29 input is selected
37039  *  0b0011110..GPIO P0_30 input is selected
37040  *  0b0011111..GPIO P0_31 input is selected
37041  *  0b0100000..GPIO P1_0 input is selected
37042  *  0b0100001..GPIO P1_1 input is selected
37043  *  0b0100010..GPIO P1_2 input is selected
37044  *  0b0100011..GPIO P1_3 input is selected
37045  *  0b0100100..GPIO P1_4 input is selected
37046  *  0b0100101..GPIO P1_5 input is selected
37047  *  0b0100110..GPIO P1_6 input is selected
37048  *  0b0100111..GPIO P1_7 input is selected
37049  *  0b0101000..GPIO P1_8 input is selected
37050  *  0b0101001..GPIO P1_9 input is selected
37051  *  0b0101010..GPIO P1_10 input is selected
37052  *  0b0101011..GPIO P1_11 input is selected
37053  *  0b0101100..GPIO P1_12 input is selected
37054  *  0b0101101..GPIO P1_13 input is selected
37055  *  0b0101110..GPIO P1_14 input is selected
37056  *  0b0101111..GPIO P1_15 input is selected
37057  *  0b0110000..GPIO P1_16 input is selected
37058  *  0b0110001..GPIO P1_17 input is selected
37059  *  0b0110010..GPIO P1_18 input is selected
37060  *  0b0110011..GPIO P1_19 input is selected
37061  *  0b0110100..GPIO P1_20 input is selected
37062  *  0b0110101..GPIO P1_21 input is selected
37063  *  0b0110110..GPIO P1_22 input is selected
37064  *  0b0110111..GPIO P1_23 input is selected
37065  *  0b0111000..Reserved
37066  *  0b0111001..Reserved
37067  *  0b0111010..Reserved
37068  *  0b0111011..Reserved
37069  *  0b0111100..Reserved
37070  *  0b0111101..Reserved
37071  *  0b0111110..GPIO P1_30 input is selected
37072  *  0b0111111..GPIO P1_31 input is selected
37073  *  *..
37074  */
37075 #define INPUTMUX_INPUTMUX_GPIO_INT_PINTSEL_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_INPUTMUX_GPIO_INT_PINTSEL_INP_SHIFT)) & INPUTMUX_INPUTMUX_GPIO_INT_PINTSEL_INP_MASK)
37076 /*! @} */
37077 
37078 /* The count of INPUTMUX_INPUTMUX_GPIO_INT_PINTSEL */
37079 #define INPUTMUX_INPUTMUX_GPIO_INT_PINTSEL_COUNT (8U)
37080 
37081 /*! @name FREQMEAS_REF - Selection for Frequency Measurement Reference Clock */
37082 /*! @{ */
37083 
37084 #define INPUTMUX_FREQMEAS_REF_INP_MASK           (0x3FU)
37085 #define INPUTMUX_FREQMEAS_REF_INP_SHIFT          (0U)
37086 /*! INP - Clock source number (binary value) for frequency measure function reference clock.
37087  *  0b000000..clk_in (output of clk_in or XTAL mux in Clockgen) input is selected
37088  *  0b000001..FRO_12M input is selected
37089  *  0b000010..FRO_144M input is selected
37090  *  0b000011..Reserved
37091  *  0b000100..OSC_32K input is selected
37092  *  0b000101..CPU/system_clk input is selected
37093  *  0b000110..FREQME_CLK_IN0 input is selected
37094  *  0b000111..FREQME_CLK_IN1 input is selected
37095  *  0b001000..EVTG_OUT0A input is selected
37096  *  0b001001..EVTG_OUT1A input is selected
37097  *  *..
37098  */
37099 #define INPUTMUX_FREQMEAS_REF_INP(x)             (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_REF_INP_SHIFT)) & INPUTMUX_FREQMEAS_REF_INP_MASK)
37100 /*! @} */
37101 
37102 /*! @name FREQMEAS_TAR - Selection for Frequency Measurement Target Clock */
37103 /*! @{ */
37104 
37105 #define INPUTMUX_FREQMEAS_TAR_INP_MASK           (0x3FU)
37106 #define INPUTMUX_FREQMEAS_TAR_INP_SHIFT          (0U)
37107 /*! INP - Clock source number (binary value) for frequency measure function target clock.
37108  *  0b000000..clk_in (output of clk_in or XTAL mux in Clockgen) input is selected
37109  *  0b000001..FRO_12M input is selected
37110  *  0b000010..FRO_144M input is selected
37111  *  0b000011..Reserved
37112  *  0b000100..OSC_32K input is selected
37113  *  0b000101..CPU/system_clk input is selected
37114  *  0b000110..FREQME_CLK_IN0 input is selected
37115  *  0b000111..FREQME_CLK_IN1 input is selected
37116  *  0b001000..EVTG_OUT0A input is selected
37117  *  0b001001..EVTG_OUT1A input is selected
37118  *  *..
37119  */
37120 #define INPUTMUX_FREQMEAS_TAR_INP(x)             (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_TAR_INP_SHIFT)) & INPUTMUX_FREQMEAS_TAR_INP_MASK)
37121 /*! @} */
37122 
37123 /*! @name CTIMER3CAP0 - Capture Select Register for CTIMER Inputs */
37124 /*! @{ */
37125 
37126 #define INPUTMUX_CTIMER3CAP0_INP_MASK            (0x7FU)
37127 #define INPUTMUX_CTIMER3CAP0_INP_SHIFT           (0U)
37128 /*! INP - Input number for CTIMER
37129  *  0b0000000..CT_INP0 input is selected
37130  *  0b0000001..CT_INP1 input is selected
37131  *  0b0000010..CT_INP2 input is selected
37132  *  0b0000011..CT_INP3 input is selected
37133  *  0b0000100..CT_INP4 input is selected
37134  *  0b0000101..CT_INP5 input is selected
37135  *  0b0000110..CT_INP6 input is selected
37136  *  0b0000111..CT_INP7 input is selected
37137  *  0b0001000..CT_INP8 input is selected
37138  *  0b0001001..CT_INP9 input is selected
37139  *  0b0001010..CT_INP10 input is selected
37140  *  0b0001011..CT_INP11 input is selected
37141  *  0b0001100..CT_INP12 input is selected
37142  *  0b0001101..CT_INP13 input is selected
37143  *  0b0001110..CT_INP14 input is selected
37144  *  0b0001111..CT_INP15 input is selected
37145  *  0b0010000..CT_INP16 input is selected
37146  *  0b0010001..CT_INP17 input is selected
37147  *  0b0010010..CT_INP18 input is selected
37148  *  0b0010011..CT_INP19 input is selected
37149  *  0b0010100..usb0 start of frame input is selected
37150  *  0b0010101..usb1 start of frame input is selected
37151  *  0b0010110..DCDC_BURST_ACTIVE input is selected
37152  *  0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected
37153  *  0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected
37154  *  0b0011001..ADC0 ADC0_IRQ input is selected
37155  *  0b0011010..ADC0 ADC1_IRQ input is selected
37156  *  0b0011011..CMP0_OUT input is selected
37157  *  0b0011100..CMP1_OUT input is selected
37158  *  0b0011101..CMP2_OUT input is selected
37159  *  0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected
37160  *  0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected
37161  *  0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected
37162  *  0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected
37163  *  0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected
37164  *  0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected
37165  *  0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected
37166  *  0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected
37167  *  0b0100110..QDC0_CMP/POS_MATCH input is selected
37168  *  0b0100111..QDC1_CMP/POS_MATCH input is selected
37169  *  0b0101000..EVTG_OUT0A input is selected
37170  *  0b0101001..EVTG_OUT0B input is selected
37171  *  0b0101010..EVTG_OUT1A input is selected
37172  *  0b0101011..EVTG_OUT1B input is selected
37173  *  0b0101100..EVTG_OUT2A input is selected
37174  *  0b0101101..EVTG_OUT2B input is selected
37175  *  0b0101110..EVTG_OUT3A input is selected
37176  *  0b0101111..EVTG_OUT3B input is selected
37177  *  0b0110000..Reserved
37178  *  0b0110001..Reserved
37179  *  0b0110010..LP_FLEXCOMM0 trig 0 input is selected
37180  *  0b0110011..LP_FLEXCOMM0 trig 1 input is selected
37181  *  0b0110100..LP_FLEXCOMM0 trig 2 input is selected
37182  *  0b0110101..LP_FLEXCOMM1 trig 0 input is selected
37183  *  0b0110110..LP_FLEXCOMM1 trig 1 input is selected
37184  *  0b0110111..LP_FLEXCOMM1 trig 2 input is selected
37185  *  0b0111000..LP_FLEXCOMM2 trig 0 input is selected
37186  *  0b0111001..LP_FLEXCOMM2 trig 1 input is selected
37187  *  0b0111010..LP_FLEXCOMM2 trig 2 input is selected
37188  *  0b0111011..LP_FLEXCOMM3 trig 0 input is selected
37189  *  0b0111100..LP_FLEXCOMM3 trig 1 input is selected
37190  *  0b0111101..LP_FLEXCOMM3 trig 2 input is selected
37191  *  0b0111110..LP_FLEXCOMM3 trig 3 input is selected
37192  *  0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected
37193  *  0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected
37194  *  *..
37195  */
37196 #define INPUTMUX_CTIMER3CAP0_INP(x)              (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER3CAP0_INP_SHIFT)) & INPUTMUX_CTIMER3CAP0_INP_MASK)
37197 /*! @} */
37198 
37199 /*! @name CTIMER3CAP1 - Capture Select Register for CTIMER Inputs */
37200 /*! @{ */
37201 
37202 #define INPUTMUX_CTIMER3CAP1_INP_MASK            (0x7FU)
37203 #define INPUTMUX_CTIMER3CAP1_INP_SHIFT           (0U)
37204 /*! INP - Input number for CTIMER
37205  *  0b0000000..CT_INP0 input is selected
37206  *  0b0000001..CT_INP1 input is selected
37207  *  0b0000010..CT_INP2 input is selected
37208  *  0b0000011..CT_INP3 input is selected
37209  *  0b0000100..CT_INP4 input is selected
37210  *  0b0000101..CT_INP5 input is selected
37211  *  0b0000110..CT_INP6 input is selected
37212  *  0b0000111..CT_INP7 input is selected
37213  *  0b0001000..CT_INP8 input is selected
37214  *  0b0001001..CT_INP9 input is selected
37215  *  0b0001010..CT_INP10 input is selected
37216  *  0b0001011..CT_INP11 input is selected
37217  *  0b0001100..CT_INP12 input is selected
37218  *  0b0001101..CT_INP13 input is selected
37219  *  0b0001110..CT_INP14 input is selected
37220  *  0b0001111..CT_INP15 input is selected
37221  *  0b0010000..CT_INP16 input is selected
37222  *  0b0010001..CT_INP17 input is selected
37223  *  0b0010010..CT_INP18 input is selected
37224  *  0b0010011..CT_INP19 input is selected
37225  *  0b0010100..usb0 start of frame input is selected
37226  *  0b0010101..usb1 start of frame input is selected
37227  *  0b0010110..DCDC_BURST_ACTIVE input is selected
37228  *  0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected
37229  *  0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected
37230  *  0b0011001..ADC0 ADC0_IRQ input is selected
37231  *  0b0011010..ADC0 ADC1_IRQ input is selected
37232  *  0b0011011..CMP0_OUT input is selected
37233  *  0b0011100..CMP1_OUT input is selected
37234  *  0b0011101..CMP2_OUT input is selected
37235  *  0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected
37236  *  0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected
37237  *  0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected
37238  *  0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected
37239  *  0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected
37240  *  0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected
37241  *  0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected
37242  *  0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected
37243  *  0b0100110..QDC0_CMP/POS_MATCH input is selected
37244  *  0b0100111..QDC1_CMP/POS_MATCH input is selected
37245  *  0b0101000..EVTG_OUT0A input is selected
37246  *  0b0101001..EVTG_OUT0B input is selected
37247  *  0b0101010..EVTG_OUT1A input is selected
37248  *  0b0101011..EVTG_OUT1B input is selected
37249  *  0b0101100..EVTG_OUT2A input is selected
37250  *  0b0101101..EVTG_OUT2B input is selected
37251  *  0b0101110..EVTG_OUT3A input is selected
37252  *  0b0101111..EVTG_OUT3B input is selected
37253  *  0b0110000..Reserved
37254  *  0b0110001..Reserved
37255  *  0b0110010..LP_FLEXCOMM0 trig 0 input is selected
37256  *  0b0110011..LP_FLEXCOMM0 trig 1 input is selected
37257  *  0b0110100..LP_FLEXCOMM0 trig 2 input is selected
37258  *  0b0110101..LP_FLEXCOMM1 trig 0 input is selected
37259  *  0b0110110..LP_FLEXCOMM1 trig 1 input is selected
37260  *  0b0110111..LP_FLEXCOMM1 trig 2 input is selected
37261  *  0b0111000..LP_FLEXCOMM2 trig 0 input is selected
37262  *  0b0111001..LP_FLEXCOMM2 trig 1 input is selected
37263  *  0b0111010..LP_FLEXCOMM2 trig 2 input is selected
37264  *  0b0111011..LP_FLEXCOMM3 trig 0 input is selected
37265  *  0b0111100..LP_FLEXCOMM3 trig 1 input is selected
37266  *  0b0111101..LP_FLEXCOMM3 trig 2 input is selected
37267  *  0b0111110..LP_FLEXCOMM3 trig 3 input is selected
37268  *  0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected
37269  *  0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected
37270  *  *..
37271  */
37272 #define INPUTMUX_CTIMER3CAP1_INP(x)              (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER3CAP1_INP_SHIFT)) & INPUTMUX_CTIMER3CAP1_INP_MASK)
37273 /*! @} */
37274 
37275 /*! @name CTIMER3CAP2 - Capture Select Register for CTIMER Inputs */
37276 /*! @{ */
37277 
37278 #define INPUTMUX_CTIMER3CAP2_INP_MASK            (0x7FU)
37279 #define INPUTMUX_CTIMER3CAP2_INP_SHIFT           (0U)
37280 /*! INP - Input number for CTIMER
37281  *  0b0000000..CT_INP0 input is selected
37282  *  0b0000001..CT_INP1 input is selected
37283  *  0b0000010..CT_INP2 input is selected
37284  *  0b0000011..CT_INP3 input is selected
37285  *  0b0000100..CT_INP4 input is selected
37286  *  0b0000101..CT_INP5 input is selected
37287  *  0b0000110..CT_INP6 input is selected
37288  *  0b0000111..CT_INP7 input is selected
37289  *  0b0001000..CT_INP8 input is selected
37290  *  0b0001001..CT_INP9 input is selected
37291  *  0b0001010..CT_INP10 input is selected
37292  *  0b0001011..CT_INP11 input is selected
37293  *  0b0001100..CT_INP12 input is selected
37294  *  0b0001101..CT_INP13 input is selected
37295  *  0b0001110..CT_INP14 input is selected
37296  *  0b0001111..CT_INP15 input is selected
37297  *  0b0010000..CT_INP16 input is selected
37298  *  0b0010001..CT_INP17 input is selected
37299  *  0b0010010..CT_INP18 input is selected
37300  *  0b0010011..CT_INP19 input is selected
37301  *  0b0010100..usb0 start of frame input is selected
37302  *  0b0010101..usb1 start of frame input is selected
37303  *  0b0010110..DCDC_BURST_ACTIVE input is selected
37304  *  0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected
37305  *  0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected
37306  *  0b0011001..ADC0 ADC0_IRQ input is selected
37307  *  0b0011010..ADC0 ADC1_IRQ input is selected
37308  *  0b0011011..CMP0_OUT input is selected
37309  *  0b0011100..CMP1_OUT input is selected
37310  *  0b0011101..CMP2_OUT input is selected
37311  *  0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected
37312  *  0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected
37313  *  0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected
37314  *  0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected
37315  *  0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected
37316  *  0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected
37317  *  0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected
37318  *  0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected
37319  *  0b0100110..QDC0_CMP/POS_MATCH input is selected
37320  *  0b0100111..QDC1_CMP/POS_MATCH input is selected
37321  *  0b0101000..EVTG_OUT0A input is selected
37322  *  0b0101001..EVTG_OUT0B input is selected
37323  *  0b0101010..EVTG_OUT1A input is selected
37324  *  0b0101011..EVTG_OUT1B input is selected
37325  *  0b0101100..EVTG_OUT2A input is selected
37326  *  0b0101101..EVTG_OUT2B input is selected
37327  *  0b0101110..EVTG_OUT3A input is selected
37328  *  0b0101111..EVTG_OUT3B input is selected
37329  *  0b0110000..Reserved
37330  *  0b0110001..Reserved
37331  *  0b0110010..LP_FLEXCOMM0 trig 0 input is selected
37332  *  0b0110011..LP_FLEXCOMM0 trig 1 input is selected
37333  *  0b0110100..LP_FLEXCOMM0 trig 2 input is selected
37334  *  0b0110101..LP_FLEXCOMM1 trig 0 input is selected
37335  *  0b0110110..LP_FLEXCOMM1 trig 1 input is selected
37336  *  0b0110111..LP_FLEXCOMM1 trig 2 input is selected
37337  *  0b0111000..LP_FLEXCOMM2 trig 0 input is selected
37338  *  0b0111001..LP_FLEXCOMM2 trig 1 input is selected
37339  *  0b0111010..LP_FLEXCOMM2 trig 2 input is selected
37340  *  0b0111011..LP_FLEXCOMM3 trig 0 input is selected
37341  *  0b0111100..LP_FLEXCOMM3 trig 1 input is selected
37342  *  0b0111101..LP_FLEXCOMM3 trig 2 input is selected
37343  *  0b0111110..LP_FLEXCOMM3 trig 3 input is selected
37344  *  0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected
37345  *  0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected
37346  *  *..
37347  */
37348 #define INPUTMUX_CTIMER3CAP2_INP(x)              (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER3CAP2_INP_SHIFT)) & INPUTMUX_CTIMER3CAP2_INP_MASK)
37349 /*! @} */
37350 
37351 /*! @name CTIMER3CAP3 - Capture Select Register for CTIMER Inputs */
37352 /*! @{ */
37353 
37354 #define INPUTMUX_CTIMER3CAP3_INP_MASK            (0x7FU)
37355 #define INPUTMUX_CTIMER3CAP3_INP_SHIFT           (0U)
37356 /*! INP - Input number for CTIMER
37357  *  0b0000000..CT_INP0 input is selected
37358  *  0b0000001..CT_INP1 input is selected
37359  *  0b0000010..CT_INP2 input is selected
37360  *  0b0000011..CT_INP3 input is selected
37361  *  0b0000100..CT_INP4 input is selected
37362  *  0b0000101..CT_INP5 input is selected
37363  *  0b0000110..CT_INP6 input is selected
37364  *  0b0000111..CT_INP7 input is selected
37365  *  0b0001000..CT_INP8 input is selected
37366  *  0b0001001..CT_INP9 input is selected
37367  *  0b0001010..CT_INP10 input is selected
37368  *  0b0001011..CT_INP11 input is selected
37369  *  0b0001100..CT_INP12 input is selected
37370  *  0b0001101..CT_INP13 input is selected
37371  *  0b0001110..CT_INP14 input is selected
37372  *  0b0001111..CT_INP15 input is selected
37373  *  0b0010000..CT_INP16 input is selected
37374  *  0b0010001..CT_INP17 input is selected
37375  *  0b0010010..CT_INP18 input is selected
37376  *  0b0010011..CT_INP19 input is selected
37377  *  0b0010100..usb0 start of frame input is selected
37378  *  0b0010101..usb1 start of frame input is selected
37379  *  0b0010110..DCDC_BURST_ACTIVE input is selected
37380  *  0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected
37381  *  0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected
37382  *  0b0011001..ADC0 ADC0_IRQ input is selected
37383  *  0b0011010..ADC0 ADC1_IRQ input is selected
37384  *  0b0011011..CMP0_OUT input is selected
37385  *  0b0011100..CMP1_OUT input is selected
37386  *  0b0011101..CMP2_OUT input is selected
37387  *  0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected
37388  *  0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected
37389  *  0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected
37390  *  0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected
37391  *  0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected
37392  *  0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected
37393  *  0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected
37394  *  0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected
37395  *  0b0100110..QDC0_CMP/POS_MATCH input is selected
37396  *  0b0100111..QDC1_CMP/POS_MATCH input is selected
37397  *  0b0101000..EVTG_OUT0A input is selected
37398  *  0b0101001..EVTG_OUT0B input is selected
37399  *  0b0101010..EVTG_OUT1A input is selected
37400  *  0b0101011..EVTG_OUT1B input is selected
37401  *  0b0101100..EVTG_OUT2A input is selected
37402  *  0b0101101..EVTG_OUT2B input is selected
37403  *  0b0101110..EVTG_OUT3A input is selected
37404  *  0b0101111..EVTG_OUT3B input is selected
37405  *  0b0110000..Reserved
37406  *  0b0110001..Reserved
37407  *  0b0110010..LP_FLEXCOMM0 trig 0 input is selected
37408  *  0b0110011..LP_FLEXCOMM0 trig 1 input is selected
37409  *  0b0110100..LP_FLEXCOMM0 trig 2 input is selected
37410  *  0b0110101..LP_FLEXCOMM1 trig 0 input is selected
37411  *  0b0110110..LP_FLEXCOMM1 trig 1 input is selected
37412  *  0b0110111..LP_FLEXCOMM1 trig 2 input is selected
37413  *  0b0111000..LP_FLEXCOMM2 trig 0 input is selected
37414  *  0b0111001..LP_FLEXCOMM2 trig 1 input is selected
37415  *  0b0111010..LP_FLEXCOMM2 trig 2 input is selected
37416  *  0b0111011..LP_FLEXCOMM3 trig 0 input is selected
37417  *  0b0111100..LP_FLEXCOMM3 trig 1 input is selected
37418  *  0b0111101..LP_FLEXCOMM3 trig 2 input is selected
37419  *  0b0111110..LP_FLEXCOMM3 trig 3 input is selected
37420  *  0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected
37421  *  0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected
37422  *  *..
37423  */
37424 #define INPUTMUX_CTIMER3CAP3_INP(x)              (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER3CAP3_INP_SHIFT)) & INPUTMUX_CTIMER3CAP3_INP_MASK)
37425 /*! @} */
37426 
37427 /*! @name TIMER3TRIG - Trigger Register for CTIMER */
37428 /*! @{ */
37429 
37430 #define INPUTMUX_TIMER3TRIG_INP_MASK             (0x7FU)
37431 #define INPUTMUX_TIMER3TRIG_INP_SHIFT            (0U)
37432 /*! INP - Input number for CTIMER
37433  *  0b0000000..CT_INP0 input is selected
37434  *  0b0000001..CT_INP1 input is selected
37435  *  0b0000010..CT_INP2 input is selected
37436  *  0b0000011..CT_INP3 input is selected
37437  *  0b0000100..CT_INP4 input is selected
37438  *  0b0000101..CT_INP5 input is selected
37439  *  0b0000110..CT_INP6 input is selected
37440  *  0b0000111..CT_INP7 input is selected
37441  *  0b0001000..CT_INP8 input is selected
37442  *  0b0001001..CT_INP9 input is selected
37443  *  0b0001010..CT_INP10 input is selected
37444  *  0b0001011..CT_INP11 input is selected
37445  *  0b0001100..CT_INP12 input is selected
37446  *  0b0001101..CT_INP13 input is selected
37447  *  0b0001110..CT_INP14 input is selected
37448  *  0b0001111..CT_INP15 input is selected
37449  *  0b0010000..CT_INP16 input is selected
37450  *  0b0010001..CT_INP17 input is selected
37451  *  0b0010010..CT_INP18 input is selected
37452  *  0b0010011..CT_INP19 input is selected
37453  *  0b0010100..usb0 start of frame input is selected
37454  *  0b0010101..usb1 start of frame input is selected
37455  *  0b0010110..DCDC_BURST_ACTIVE input is selected
37456  *  0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected
37457  *  0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected
37458  *  0b0011001..ADC0 ADC0_IRQ input is selected
37459  *  0b0011010..ADC0 ADC1_IRQ input is selected
37460  *  0b0011011..CMP0_OUT input is selected
37461  *  0b0011100..CMP1_OUT input is selected
37462  *  0b0011101..CMP2_OUT input is selected
37463  *  0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected
37464  *  0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected
37465  *  0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected
37466  *  0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected
37467  *  0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected
37468  *  0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected
37469  *  0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected
37470  *  0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected
37471  *  0b0100110..QDC0_CMP/POS_MATCH input is selected
37472  *  0b0100111..QDC1_CMP/POS_MATCH input is selected
37473  *  0b0101000..EVTG_OUT0A input is selected
37474  *  0b0101001..EVTG_OUT0B input is selected
37475  *  0b0101010..EVTG_OUT1A input is selected
37476  *  0b0101011..EVTG_OUT1B input is selected
37477  *  0b0101100..EVTG_OUT2A input is selected
37478  *  0b0101101..EVTG_OUT2B input is selected
37479  *  0b0101110..EVTG_OUT3A input is selected
37480  *  0b0101111..EVTG_OUT3B input is selected
37481  *  0b0110000..Reserved
37482  *  0b0110001..Reserved
37483  *  0b0110010..LP_FLEXCOMM0 trig 0 input is selected
37484  *  0b0110011..LP_FLEXCOMM0 trig 1 input is selected
37485  *  0b0110100..LP_FLEXCOMM0 trig 2 input is selected
37486  *  0b0110101..LP_FLEXCOMM1 trig 0 input is selected
37487  *  0b0110110..LP_FLEXCOMM1 trig 1 input is selected
37488  *  0b0110111..LP_FLEXCOMM1 trig 2 input is selected
37489  *  0b0111000..LP_FLEXCOMM2 trig 0 input is selected
37490  *  0b0111001..LP_FLEXCOMM2 trig 1 input is selected
37491  *  0b0111010..LP_FLEXCOMM2 trig 2 input is selected
37492  *  0b0111011..LP_FLEXCOMM3 trig 0 input is selected
37493  *  0b0111100..LP_FLEXCOMM3 trig 1 input is selected
37494  *  0b0111101..LP_FLEXCOMM3 trig 2 input is selected
37495  *  0b0111110..LP_FLEXCOMM3 trig 3 input is selected
37496  *  0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected
37497  *  0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected
37498  *  *..
37499  */
37500 #define INPUTMUX_TIMER3TRIG_INP(x)               (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER3TRIG_INP_SHIFT)) & INPUTMUX_TIMER3TRIG_INP_MASK)
37501 /*! @} */
37502 
37503 /*! @name CTIMER4CAP0 - Capture Select Register for CTIMER Inputs */
37504 /*! @{ */
37505 
37506 #define INPUTMUX_CTIMER4CAP0_INP_MASK            (0x7FU)
37507 #define INPUTMUX_CTIMER4CAP0_INP_SHIFT           (0U)
37508 /*! INP - Input number for CTIMER
37509  *  0b0000000..CT_INP0 input is selected
37510  *  0b0000001..CT_INP1 input is selected
37511  *  0b0000010..CT_INP2 input is selected
37512  *  0b0000011..CT_INP3 input is selected
37513  *  0b0000100..CT_INP4 input is selected
37514  *  0b0000101..CT_INP5 input is selected
37515  *  0b0000110..CT_INP6 input is selected
37516  *  0b0000111..CT_INP7 input is selected
37517  *  0b0001000..CT_INP8 input is selected
37518  *  0b0001001..CT_INP9 input is selected
37519  *  0b0001010..CT_INP10 input is selected
37520  *  0b0001011..CT_INP11 input is selected
37521  *  0b0001100..CT_INP12 input is selected
37522  *  0b0001101..CT_INP13 input is selected
37523  *  0b0001110..CT_INP14 input is selected
37524  *  0b0001111..CT_INP15 input is selected
37525  *  0b0010000..CT_INP16 input is selected
37526  *  0b0010001..CT_INP17 input is selected
37527  *  0b0010010..CT_INP18 input is selected
37528  *  0b0010011..CT_INP19 input is selected
37529  *  0b0010100..usb0 start of frame input is selected
37530  *  0b0010101..usb1 start of frame input is selected
37531  *  0b0010110..DCDC_BURST_ACTIVE input is selected
37532  *  0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected
37533  *  0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected
37534  *  0b0011001..ADC0 ADC0_IRQ input is selected
37535  *  0b0011010..ADC0 ADC1_IRQ input is selected
37536  *  0b0011011..CMP0_OUT input is selected
37537  *  0b0011100..CMP1_OUT input is selected
37538  *  0b0011101..CMP2_OUT input is selected
37539  *  0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected
37540  *  0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected
37541  *  0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected
37542  *  0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected
37543  *  0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected
37544  *  0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected
37545  *  0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected
37546  *  0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected
37547  *  0b0100110..QDC0_CMP/POS_MATCH input is selected
37548  *  0b0100111..QDC1_CMP/POS_MATCH input is selected
37549  *  0b0101000..EVTG_OUT0A input is selected
37550  *  0b0101001..EVTG_OUT0B input is selected
37551  *  0b0101010..EVTG_OUT1A input is selected
37552  *  0b0101011..EVTG_OUT1B input is selected
37553  *  0b0101100..EVTG_OUT2A input is selected
37554  *  0b0101101..EVTG_OUT2B input is selected
37555  *  0b0101110..EVTG_OUT3A input is selected
37556  *  0b0101111..EVTG_OUT3B input is selected
37557  *  0b0110000..Reserved
37558  *  0b0110001..Reserved
37559  *  0b0110010..LP_FLEXCOMM0 trig 0 input is selected
37560  *  0b0110011..LP_FLEXCOMM0 trig 1 input is selected
37561  *  0b0110100..LP_FLEXCOMM0 trig 2 input is selected
37562  *  0b0110101..LP_FLEXCOMM1 trig 0 input is selected
37563  *  0b0110110..LP_FLEXCOMM1 trig 1 input is selected
37564  *  0b0110111..LP_FLEXCOMM1 trig 2 input is selected
37565  *  0b0111000..LP_FLEXCOMM2 trig 0 input is selected
37566  *  0b0111001..LP_FLEXCOMM2 trig 1 input is selected
37567  *  0b0111010..LP_FLEXCOMM2 trig 2 input is selected
37568  *  0b0111011..LP_FLEXCOMM3 trig 0 input is selected
37569  *  0b0111100..LP_FLEXCOMM3 trig 1 input is selected
37570  *  0b0111101..LP_FLEXCOMM3 trig 2 input is selected
37571  *  0b0111110..LP_FLEXCOMM3 trig 3 input is selected
37572  *  0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected
37573  *  0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected
37574  *  *..
37575  */
37576 #define INPUTMUX_CTIMER4CAP0_INP(x)              (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER4CAP0_INP_SHIFT)) & INPUTMUX_CTIMER4CAP0_INP_MASK)
37577 /*! @} */
37578 
37579 /*! @name CTIMER4CAP1 - Capture Select Register for CTIMER Inputs */
37580 /*! @{ */
37581 
37582 #define INPUTMUX_CTIMER4CAP1_INP_MASK            (0x7FU)
37583 #define INPUTMUX_CTIMER4CAP1_INP_SHIFT           (0U)
37584 /*! INP - Input number for CTIMER
37585  *  0b0000000..CT_INP0 input is selected
37586  *  0b0000001..CT_INP1 input is selected
37587  *  0b0000010..CT_INP2 input is selected
37588  *  0b0000011..CT_INP3 input is selected
37589  *  0b0000100..CT_INP4 input is selected
37590  *  0b0000101..CT_INP5 input is selected
37591  *  0b0000110..CT_INP6 input is selected
37592  *  0b0000111..CT_INP7 input is selected
37593  *  0b0001000..CT_INP8 input is selected
37594  *  0b0001001..CT_INP9 input is selected
37595  *  0b0001010..CT_INP10 input is selected
37596  *  0b0001011..CT_INP11 input is selected
37597  *  0b0001100..CT_INP12 input is selected
37598  *  0b0001101..CT_INP13 input is selected
37599  *  0b0001110..CT_INP14 input is selected
37600  *  0b0001111..CT_INP15 input is selected
37601  *  0b0010000..CT_INP16 input is selected
37602  *  0b0010001..CT_INP17 input is selected
37603  *  0b0010010..CT_INP18 input is selected
37604  *  0b0010011..CT_INP19 input is selected
37605  *  0b0010100..usb0 start of frame input is selected
37606  *  0b0010101..usb1 start of frame input is selected
37607  *  0b0010110..DCDC_BURST_ACTIVE input is selected
37608  *  0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected
37609  *  0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected
37610  *  0b0011001..ADC0 ADC0_IRQ input is selected
37611  *  0b0011010..ADC0 ADC1_IRQ input is selected
37612  *  0b0011011..CMP0_OUT input is selected
37613  *  0b0011100..CMP1_OUT input is selected
37614  *  0b0011101..CMP2_OUT input is selected
37615  *  0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected
37616  *  0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected
37617  *  0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected
37618  *  0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected
37619  *  0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected
37620  *  0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected
37621  *  0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected
37622  *  0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected
37623  *  0b0100110..QDC0_CMP/POS_MATCH input is selected
37624  *  0b0100111..QDC1_CMP/POS_MATCH input is selected
37625  *  0b0101000..EVTG_OUT0A input is selected
37626  *  0b0101001..EVTG_OUT0B input is selected
37627  *  0b0101010..EVTG_OUT1A input is selected
37628  *  0b0101011..EVTG_OUT1B input is selected
37629  *  0b0101100..EVTG_OUT2A input is selected
37630  *  0b0101101..EVTG_OUT2B input is selected
37631  *  0b0101110..EVTG_OUT3A input is selected
37632  *  0b0101111..EVTG_OUT3B input is selected
37633  *  0b0110000..Reserved
37634  *  0b0110001..Reserved
37635  *  0b0110010..LP_FLEXCOMM0 trig 0 input is selected
37636  *  0b0110011..LP_FLEXCOMM0 trig 1 input is selected
37637  *  0b0110100..LP_FLEXCOMM0 trig 2 input is selected
37638  *  0b0110101..LP_FLEXCOMM1 trig 0 input is selected
37639  *  0b0110110..LP_FLEXCOMM1 trig 1 input is selected
37640  *  0b0110111..LP_FLEXCOMM1 trig 2 input is selected
37641  *  0b0111000..LP_FLEXCOMM2 trig 0 input is selected
37642  *  0b0111001..LP_FLEXCOMM2 trig 1 input is selected
37643  *  0b0111010..LP_FLEXCOMM2 trig 2 input is selected
37644  *  0b0111011..LP_FLEXCOMM3 trig 0 input is selected
37645  *  0b0111100..LP_FLEXCOMM3 trig 1 input is selected
37646  *  0b0111101..LP_FLEXCOMM3 trig 2 input is selected
37647  *  0b0111110..LP_FLEXCOMM3 trig 3 input is selected
37648  *  0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected
37649  *  0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected
37650  *  *..
37651  */
37652 #define INPUTMUX_CTIMER4CAP1_INP(x)              (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER4CAP1_INP_SHIFT)) & INPUTMUX_CTIMER4CAP1_INP_MASK)
37653 /*! @} */
37654 
37655 /*! @name CTIMER4CAP2 - Capture Select Register for CTIMER Inputs */
37656 /*! @{ */
37657 
37658 #define INPUTMUX_CTIMER4CAP2_INP_MASK            (0x7FU)
37659 #define INPUTMUX_CTIMER4CAP2_INP_SHIFT           (0U)
37660 /*! INP - Input number for CTIMER
37661  *  0b0000000..CT_INP0 input is selected
37662  *  0b0000001..CT_INP1 input is selected
37663  *  0b0000010..CT_INP2 input is selected
37664  *  0b0000011..CT_INP3 input is selected
37665  *  0b0000100..CT_INP4 input is selected
37666  *  0b0000101..CT_INP5 input is selected
37667  *  0b0000110..CT_INP6 input is selected
37668  *  0b0000111..CT_INP7 input is selected
37669  *  0b0001000..CT_INP8 input is selected
37670  *  0b0001001..CT_INP9 input is selected
37671  *  0b0001010..CT_INP10 input is selected
37672  *  0b0001011..CT_INP11 input is selected
37673  *  0b0001100..CT_INP12 input is selected
37674  *  0b0001101..CT_INP13 input is selected
37675  *  0b0001110..CT_INP14 input is selected
37676  *  0b0001111..CT_INP15 input is selected
37677  *  0b0010000..CT_INP16 input is selected
37678  *  0b0010001..CT_INP17 input is selected
37679  *  0b0010010..CT_INP18 input is selected
37680  *  0b0010011..CT_INP19 input is selected
37681  *  0b0010100..usb0 start of frame input is selected
37682  *  0b0010101..usb1 start of frame input is selected
37683  *  0b0010110..DCDC_BURST_ACTIVE input is selected
37684  *  0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected
37685  *  0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected
37686  *  0b0011001..ADC0 ADC0_IRQ input is selected
37687  *  0b0011010..ADC0 ADC1_IRQ input is selected
37688  *  0b0011011..CMP0_OUT input is selected
37689  *  0b0011100..CMP1_OUT input is selected
37690  *  0b0011101..CMP2_OUT input is selected
37691  *  0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected
37692  *  0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected
37693  *  0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected
37694  *  0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected
37695  *  0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected
37696  *  0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected
37697  *  0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected
37698  *  0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected
37699  *  0b0100110..QDC0_CMP/POS_MATCH input is selected
37700  *  0b0100111..QDC1_CMP/POS_MATCH input is selected
37701  *  0b0101000..EVTG_OUT0A input is selected
37702  *  0b0101001..EVTG_OUT0B input is selected
37703  *  0b0101010..EVTG_OUT1A input is selected
37704  *  0b0101011..EVTG_OUT1B input is selected
37705  *  0b0101100..EVTG_OUT2A input is selected
37706  *  0b0101101..EVTG_OUT2B input is selected
37707  *  0b0101110..EVTG_OUT3A input is selected
37708  *  0b0101111..EVTG_OUT3B input is selected
37709  *  0b0110000..Reserved
37710  *  0b0110001..Reserved
37711  *  0b0110010..LP_FLEXCOMM0 trig 0 input is selected
37712  *  0b0110011..LP_FLEXCOMM0 trig 1 input is selected
37713  *  0b0110100..LP_FLEXCOMM0 trig 2 input is selected
37714  *  0b0110101..LP_FLEXCOMM1 trig 0 input is selected
37715  *  0b0110110..LP_FLEXCOMM1 trig 1 input is selected
37716  *  0b0110111..LP_FLEXCOMM1 trig 2 input is selected
37717  *  0b0111000..LP_FLEXCOMM2 trig 0 input is selected
37718  *  0b0111001..LP_FLEXCOMM2 trig 1 input is selected
37719  *  0b0111010..LP_FLEXCOMM2 trig 2 input is selected
37720  *  0b0111011..LP_FLEXCOMM3 trig 0 input is selected
37721  *  0b0111100..LP_FLEXCOMM3 trig 1 input is selected
37722  *  0b0111101..LP_FLEXCOMM3 trig 2 input is selected
37723  *  0b0111110..LP_FLEXCOMM3 trig 3 input is selected
37724  *  0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected
37725  *  0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected
37726  *  *..
37727  */
37728 #define INPUTMUX_CTIMER4CAP2_INP(x)              (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER4CAP2_INP_SHIFT)) & INPUTMUX_CTIMER4CAP2_INP_MASK)
37729 /*! @} */
37730 
37731 /*! @name CTIMER4CAP3 - Capture Select Register for CTIMER Inputs */
37732 /*! @{ */
37733 
37734 #define INPUTMUX_CTIMER4CAP3_INP_MASK            (0x7FU)
37735 #define INPUTMUX_CTIMER4CAP3_INP_SHIFT           (0U)
37736 /*! INP - Input number for CTIMER
37737  *  0b0000000..CT_INP0 input is selected
37738  *  0b0000001..CT_INP1 input is selected
37739  *  0b0000010..CT_INP2 input is selected
37740  *  0b0000011..CT_INP3 input is selected
37741  *  0b0000100..CT_INP4 input is selected
37742  *  0b0000101..CT_INP5 input is selected
37743  *  0b0000110..CT_INP6 input is selected
37744  *  0b0000111..CT_INP7 input is selected
37745  *  0b0001000..CT_INP8 input is selected
37746  *  0b0001001..CT_INP9 input is selected
37747  *  0b0001010..CT_INP10 input is selected
37748  *  0b0001011..CT_INP11 input is selected
37749  *  0b0001100..CT_INP12 input is selected
37750  *  0b0001101..CT_INP13 input is selected
37751  *  0b0001110..CT_INP14 input is selected
37752  *  0b0001111..CT_INP15 input is selected
37753  *  0b0010000..CT_INP16 input is selected
37754  *  0b0010001..CT_INP17 input is selected
37755  *  0b0010010..CT_INP18 input is selected
37756  *  0b0010011..CT_INP19 input is selected
37757  *  0b0010100..usb0 start of frame input is selected
37758  *  0b0010101..usb1 start of frame input is selected
37759  *  0b0010110..DCDC_BURST_ACTIVE input is selected
37760  *  0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected
37761  *  0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected
37762  *  0b0011001..ADC0 ADC0_IRQ input is selected
37763  *  0b0011010..ADC0 ADC1_IRQ input is selected
37764  *  0b0011011..CMP0_OUT input is selected
37765  *  0b0011100..CMP1_OUT input is selected
37766  *  0b0011101..CMP2_OUT input is selected
37767  *  0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected
37768  *  0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected
37769  *  0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected
37770  *  0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected
37771  *  0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected
37772  *  0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected
37773  *  0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected
37774  *  0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected
37775  *  0b0100110..QDC0_CMP/POS_MATCH input is selected
37776  *  0b0100111..QDC1_CMP/POS_MATCH input is selected
37777  *  0b0101000..EVTG_OUT0A input is selected
37778  *  0b0101001..EVTG_OUT0B input is selected
37779  *  0b0101010..EVTG_OUT1A input is selected
37780  *  0b0101011..EVTG_OUT1B input is selected
37781  *  0b0101100..EVTG_OUT2A input is selected
37782  *  0b0101101..EVTG_OUT2B input is selected
37783  *  0b0101110..EVTG_OUT3A input is selected
37784  *  0b0101111..EVTG_OUT3B input is selected
37785  *  0b0110000..Reserved
37786  *  0b0110001..Reserved
37787  *  0b0110010..LP_FLEXCOMM0 trig 0 input is selected
37788  *  0b0110011..LP_FLEXCOMM0 trig 1 input is selected
37789  *  0b0110100..LP_FLEXCOMM0 trig 2 input is selected
37790  *  0b0110101..LP_FLEXCOMM1 trig 0 input is selected
37791  *  0b0110110..LP_FLEXCOMM1 trig 1 input is selected
37792  *  0b0110111..LP_FLEXCOMM1 trig 2 input is selected
37793  *  0b0111000..LP_FLEXCOMM2 trig 0 input is selected
37794  *  0b0111001..LP_FLEXCOMM2 trig 1 input is selected
37795  *  0b0111010..LP_FLEXCOMM2 trig 2 input is selected
37796  *  0b0111011..LP_FLEXCOMM3 trig 0 input is selected
37797  *  0b0111100..LP_FLEXCOMM3 trig 1 input is selected
37798  *  0b0111101..LP_FLEXCOMM3 trig 2 input is selected
37799  *  0b0111110..LP_FLEXCOMM3 trig 3 input is selected
37800  *  0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected
37801  *  0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected
37802  *  *..
37803  */
37804 #define INPUTMUX_CTIMER4CAP3_INP(x)              (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER4CAP3_INP_SHIFT)) & INPUTMUX_CTIMER4CAP3_INP_MASK)
37805 /*! @} */
37806 
37807 /*! @name TIMER4TRIG - Trigger Register for CTIMER */
37808 /*! @{ */
37809 
37810 #define INPUTMUX_TIMER4TRIG_INP_MASK             (0x7FU)
37811 #define INPUTMUX_TIMER4TRIG_INP_SHIFT            (0U)
37812 /*! INP - Input number for CTIMER
37813  *  0b0000000..CT_INP0 input is selected
37814  *  0b0000001..CT_INP1 input is selected
37815  *  0b0000010..CT_INP2 input is selected
37816  *  0b0000011..CT_INP3 input is selected
37817  *  0b0000100..CT_INP4 input is selected
37818  *  0b0000101..CT_INP5 input is selected
37819  *  0b0000110..CT_INP6 input is selected
37820  *  0b0000111..CT_INP7 input is selected
37821  *  0b0001000..CT_INP8 input is selected
37822  *  0b0001001..CT_INP9 input is selected
37823  *  0b0001010..CT_INP10 input is selected
37824  *  0b0001011..CT_INP11 input is selected
37825  *  0b0001100..CT_INP12 input is selected
37826  *  0b0001101..CT_INP13 input is selected
37827  *  0b0001110..CT_INP14 input is selected
37828  *  0b0001111..CT_INP15 input is selected
37829  *  0b0010000..CT_INP16 input is selected
37830  *  0b0010001..CT_INP17 input is selected
37831  *  0b0010010..CT_INP18 input is selected
37832  *  0b0010011..CT_INP19 input is selected
37833  *  0b0010100..usb0 start of frame input is selected
37834  *  0b0010101..usb1 start of frame input is selected
37835  *  0b0010110..DCDC_BURST_ACTIVE input is selected
37836  *  0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected
37837  *  0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected
37838  *  0b0011001..ADC0 ADC0_IRQ input is selected
37839  *  0b0011010..ADC0 ADC1_IRQ input is selected
37840  *  0b0011011..CMP0_OUT input is selected
37841  *  0b0011100..CMP1_OUT input is selected
37842  *  0b0011101..CMP2_OUT input is selected
37843  *  0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected
37844  *  0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected
37845  *  0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected
37846  *  0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected
37847  *  0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected
37848  *  0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected
37849  *  0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected
37850  *  0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected
37851  *  0b0100110..QDC0_CMP/POS_MATCH input is selected
37852  *  0b0100111..QDC1_CMP/POS_MATCH input is selected
37853  *  0b0101000..EVTG_OUT0A input is selected
37854  *  0b0101001..EVTG_OUT0B input is selected
37855  *  0b0101010..EVTG_OUT1A input is selected
37856  *  0b0101011..EVTG_OUT1B input is selected
37857  *  0b0101100..EVTG_OUT2A input is selected
37858  *  0b0101101..EVTG_OUT2B input is selected
37859  *  0b0101110..EVTG_OUT3A input is selected
37860  *  0b0101111..EVTG_OUT3B input is selected
37861  *  0b0110000..Reserved
37862  *  0b0110001..Reserved
37863  *  0b0110010..LP_FLEXCOMM0 trig 0 input is selected
37864  *  0b0110011..LP_FLEXCOMM0 trig 1 input is selected
37865  *  0b0110100..LP_FLEXCOMM0 trig 2 input is selected
37866  *  0b0110101..LP_FLEXCOMM1 trig 0 input is selected
37867  *  0b0110110..LP_FLEXCOMM1 trig 1 input is selected
37868  *  0b0110111..LP_FLEXCOMM1 trig 2 input is selected
37869  *  0b0111000..LP_FLEXCOMM2 trig 0 input is selected
37870  *  0b0111001..LP_FLEXCOMM2 trig 1 input is selected
37871  *  0b0111010..LP_FLEXCOMM2 trig 2 input is selected
37872  *  0b0111011..LP_FLEXCOMM3 trig 0 input is selected
37873  *  0b0111100..LP_FLEXCOMM3 trig 1 input is selected
37874  *  0b0111101..LP_FLEXCOMM3 trig 2 input is selected
37875  *  0b0111110..LP_FLEXCOMM3 trig 3 input is selected
37876  *  0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected
37877  *  0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected
37878  *  *..
37879  */
37880 #define INPUTMUX_TIMER4TRIG_INP(x)               (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER4TRIG_INP_SHIFT)) & INPUTMUX_TIMER4TRIG_INP_MASK)
37881 /*! @} */
37882 
37883 /*! @name CMP0_TRIG - CMP0 Input Connections */
37884 /*! @{ */
37885 
37886 #define INPUTMUX_CMP0_TRIG_TRIGIN_MASK           (0x3FU)
37887 #define INPUTMUX_CMP0_TRIG_TRIGIN_SHIFT          (0U)
37888 /*! TRIGIN - CMP0 input trigger
37889  *  0b000000..PINT PIN_INT0 input is selected
37890  *  0b000001..PINT PIN_INT6 input is selected
37891  *  0b000010..SCT_OUT4 input is selected
37892  *  0b000011..SCT_OUT5 input is selected
37893  *  0b000100..SCT_OUT6 input is selected
37894  *  0b000101..CTIMER0_MAT3 input is selected
37895  *  0b000110..CTIMER1_MAT3 input is selected
37896  *  0b000111..CTIMER2_MAT3 input is selected
37897  *  0b001000..CTIMER0_MAT0 input is selected
37898  *  0b001001..CTIMER4_MAT0 input is selected
37899  *  0b001010..Reserved
37900  *  0b001011..Reserved
37901  *  0b001100..PINT GPIO_INT_BMAT input is selected
37902  *  0b001101..ADC0_tcomp[0] input is selected
37903  *  0b001110..ADC1_tcomp[0] input is selected
37904  *  0b001111..Reserved
37905  *  0b010000..Reserved
37906  *  0b010001..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected
37907  *  0b010010..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected
37908  *  0b010011..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected
37909  *  0b010100..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected
37910  *  0b010101..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected
37911  *  0b010110..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected
37912  *  0b010111..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected
37913  *  0b011000..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected
37914  *  0b011001..QDC0_CMP/POS_MATCH input is selected
37915  *  0b011010..QDC1_CMP/POS_MATCH input is selected
37916  *  0b011011..EVTG_OUT0A input is selected
37917  *  0b011100..EVTG_OUT0B input is selected
37918  *  0b011101..EVTG_OUT1A input is selected
37919  *  0b011110..EVTG_OUT1B input is selected
37920  *  0b011111..EVTG_OUT2A input is selected
37921  *  0b100000..EVTG_OUT2B input is selected
37922  *  0b100001..EVTG_OUT3A input is selected
37923  *  0b100010..EVTG_OUT3B input is selected
37924  *  0b100011..LPTMR0 input is selected
37925  *  0b100100..LPTMR1 input is selected
37926  *  0b100101..GPIO2 Pin Event Trig 0 input is selected
37927  *  0b100110..GPIO2 Pin Event Trig 1 input is selected
37928  *  0b100111..GPIO3 Pin Event Trig 0 input is selected
37929  *  0b101000..GPIO3 Pin Event Trig 1 input is selected
37930  *  *..
37931  */
37932 #define INPUTMUX_CMP0_TRIG_TRIGIN(x)             (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CMP0_TRIG_TRIGIN_SHIFT)) & INPUTMUX_CMP0_TRIG_TRIGIN_MASK)
37933 /*! @} */
37934 
37935 /*! @name ADC0_TRIGM_ADC0_TRIG - ADC Trigger Input Connections */
37936 /*! @{ */
37937 
37938 #define INPUTMUX_ADC0_TRIGM_ADC0_TRIG_TRIGIN_MASK (0xFFU)
37939 #define INPUTMUX_ADC0_TRIGM_ADC0_TRIG_TRIGIN_SHIFT (0U)
37940 /*! TRIGIN - ADC0 trigger inputs
37941  *  0b00000000..PINT PIN_INT0 input is selected
37942  *  0b00000001..PINT PIN_INT1 input is selected
37943  *  0b00000010..SCT0 SCT_OUT4 input is selected
37944  *  0b00000011..SCT0 SCT_OUT5 input is selected
37945  *  0b00000100..SCT0 SCT_OUT9 input is selected
37946  *  0b00000101..CTIMER0_MAT3 input is selected
37947  *  0b00000110..CTIMER1_MAT3 input is selected
37948  *  0b00000111..CTIMER2_MAT3 input is selected
37949  *  0b00001000..CTIMER3_MAT3 input is selected
37950  *  0b00001001..CTIMER4_MAT3 input is selected
37951  *  0b00001010..DCDC_Burst_Done_Trig input is selected
37952  *  0b00001011..Reserved
37953  *  0b00001100..PINT GPIO_INT_BMAT input is selected
37954  *  0b00001101..ADC0_tcomp[0] input is selected
37955  *  0b00001110..ADC0_tcomp[1] input is selected
37956  *  0b00001111..ADC0_tcomp[2] input is selected
37957  *  0b00010000..ADC0_tcomp[3] input is selected
37958  *  0b00010001..ADC1_tcomp[0] input is selected
37959  *  0b00010010..ADC1_tcomp[1] input is selected
37960  *  0b00010011..ADC1_tcomp[2] input is selected
37961  *  0b00010100..ADC1_tcomp[3] input is selected
37962  *  0b00010101..CMP0_OUT input is selected
37963  *  0b00010110..CMP1_OUT input is selected
37964  *  0b00010111..CMP2_OUT input is selected
37965  *  0b00011000..PWM0_SM0_MUX_TRIG0 input is selected
37966  *  0b00011001..PWM0_SM0_MUX_TRIG1 input is selected
37967  *  0b00011010..PWM0_SM1_MUX_TRIG0 input is selected
37968  *  0b00011011..PWM0_SM1_MUX_TRIG1 input is selected
37969  *  0b00011100..PWM0_SM2_MUX_TRIG0 input is selected
37970  *  0b00011101..PWM0_SM2_MUX_TRIG1 input is selected
37971  *  0b00011110..PWM0_SM3_MUX_TRIG0 input is selected
37972  *  0b00011111..PWM0_SM3_MUX_TRIG1 input is selected
37973  *  0b00100000..PWM1_SM0_MUX_TRIG0 input is selected
37974  *  0b00100001..PWM1_SM0_MUX_TRIG1 input is selected
37975  *  0b00100010..PWM1_SM1_MUX_TRIG0 input is selected
37976  *  0b00100011..PWM1_SM1_MUX_TRIG1 input is selected
37977  *  0b00100100..PWM1_SM2_MUX_TRIG0 input is selected
37978  *  0b00100101..PWM1_SM2_MUX_TRIG1 input is selected
37979  *  0b00100110..PWM1_SM3_MUX_TRIG0 input is selected
37980  *  0b00100111..PWM1_SM3_MUX_TRIG1 input is selected
37981  *  0b00101000..QDC0_CMP/POS_MATCH input is selected
37982  *  0b00101001..QDC1_CMP/POS_MATCH input is selected
37983  *  0b00101010..EVTG_OUT0A input is selected
37984  *  0b00101011..EVTG_OUT0B input is selected
37985  *  0b00101100..EVTG_OUT1A input is selected
37986  *  0b00101101..EVTG_OUT1B input is selected
37987  *  0b00101110..EVTG_OUT2A input is selected
37988  *  0b00101111..EVTG_OUT2B input is selected
37989  *  0b00110000..EVTG_OUT3A input is selected
37990  *  0b00110001..EVTG_OUT3B input is selected
37991  *  0b00110010..LPTMR0 input is selected
37992  *  0b00110011..LPTMR1 input is selected
37993  *  0b00110100..FlexIO CH0 input is selected
37994  *  0b00110101..FlexIO CH1 input is selected
37995  *  0b00110110..FlexIO CH2 input is selected
37996  *  0b00110111..FlexIO CH3 input is selected
37997  *  0b00111000..SINC Filter CH0 Conversion Complete input is selected
37998  *  0b00111001..SINC Filter CH1 Conversion Complete input is selected
37999  *  0b00111010..SINC Filter CH2 Conversion Complete input is selected
38000  *  0b00111011..SINC Filter CH3 Conversion Complete input is selected
38001  *  0b00111100..SINC Filter CH4 Conversion Complete input is selected
38002  *  0b00111101..GPIO2 Pin Event Trig 0 input is selected
38003  *  0b00111110..GPIO2 Pin Event Trig 1 input is selected
38004  *  0b00111111..GPIO3 Pin Event Trig 0 input is selected
38005  *  0b01000000..GPIO3 Pin Event Trig 1 input is selected
38006  *  0b01000001..WUU input is selected
38007  *  *..
38008  */
38009 #define INPUTMUX_ADC0_TRIGM_ADC0_TRIG_TRIGIN(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_ADC0_TRIGM_ADC0_TRIG_TRIGIN_SHIFT)) & INPUTMUX_ADC0_TRIGM_ADC0_TRIG_TRIGIN_MASK)
38010 /*! @} */
38011 
38012 /* The count of INPUTMUX_ADC0_TRIGM_ADC0_TRIG */
38013 #define INPUTMUX_ADC0_TRIGM_ADC0_TRIG_COUNT      (4U)
38014 
38015 /*! @name ADC1_TRIGN_ADC1_TRIG - ADC Trigger Input Connections */
38016 /*! @{ */
38017 
38018 #define INPUTMUX_ADC1_TRIGN_ADC1_TRIG_TRIGIN_MASK (0xFFU)
38019 #define INPUTMUX_ADC1_TRIGN_ADC1_TRIG_TRIGIN_SHIFT (0U)
38020 /*! TRIGIN - ADC1 trigger inputs
38021  *  0b00000000..PINT PIN_INT0 input is selected
38022  *  0b00000001..PINT PIN_INT2 input is selected
38023  *  0b00000010..SCT0 SCT_OUT4 input is selected
38024  *  0b00000011..SCT0 SCT_OUT5 input is selected
38025  *  0b00000100..SCT0 SCT_OUT3 input is selected
38026  *  0b00000101..CTIMER0_MAT3 input is selected
38027  *  0b00000110..CTIMER1_MAT3 input is selected
38028  *  0b00000111..CTIMER2_MAT3 input is selected
38029  *  0b00001000..CTIMER3_MAT2 input is selected
38030  *  0b00001001..CTIMER4_MAT1 input is selected
38031  *  0b00001010..DCDC_Burst_Done_Trig input is selected
38032  *  0b00001011..Reserved
38033  *  0b00001100..PINT GPIO_INT_BMAT input is selected
38034  *  0b00001101..ADC0_tcomp[0] input is selected
38035  *  0b00001110..ADC0_tcomp[1] input is selected
38036  *  0b00001111..ADC0_tcomp[2] input is selected
38037  *  0b00010000..ADC0_tcomp[3] input is selected
38038  *  0b00010001..ADC1_tcomp[0] input is selected
38039  *  0b00010010..ADC1_tcomp[1] input is selected
38040  *  0b00010011..ADC1_tcomp[2] input is selected
38041  *  0b00010100..ADC1_tcomp[3] input is selected
38042  *  0b00010101..CMP0_OUT input is selected
38043  *  0b00010110..CMP1_OUT input is selected
38044  *  0b00010111..CMP2_OUT input is selected
38045  *  0b00011000..PWM0_SM0_MUX_TRIG0 input is selected
38046  *  0b00011001..PWM0_SM0_MUX_TRIG1 input is selected
38047  *  0b00011010..PWM0_SM1_MUX_TRIG0 input is selected
38048  *  0b00011011..PWM0_SM1_MUX_TRIG1 input is selected
38049  *  0b00011100..PWM0_SM2_MUX_TRIG0 input is selected
38050  *  0b00011101..PWM0_SM2_MUX_TRIG1 input is selected
38051  *  0b00011110..PWM0_SM3_MUX_TRIG0 input is selected
38052  *  0b00011111..PWM0_SM3_MUX_TRIG1 input is selected
38053  *  0b00100000..PWM1_SM0_MUX_TRIG0 input is selected
38054  *  0b00100001..PWM1_SM0_MUX_TRIG1 input is selected
38055  *  0b00100010..PWM1_SM1_MUX_TRIG0 input is selected
38056  *  0b00100011..PWM1_SM1_MUX_TRIG1 input is selected
38057  *  0b00100100..PWM1_SM2_MUX_TRIG0 input is selected
38058  *  0b00100101..PWM1_SM2_MUX_TRIG1 input is selected
38059  *  0b00100110..PWM1_SM3_MUX_TRIG0 input is selected
38060  *  0b00100111..PWM1_SM3_MUX_TRIG1 input is selected
38061  *  0b00101000..QDC0_CMP/POS_MATCH input is selected
38062  *  0b00101001..QDC1_CMP/POS_MATCH input is selected
38063  *  0b00101010..EVTG_OUT0A input is selected
38064  *  0b00101011..EVTG_OUT0B input is selected
38065  *  0b00101100..EVTG_OUT1A input is selected
38066  *  0b00101101..EVTG_OUT1B input is selected
38067  *  0b00101110..EVTG_OUT2A input is selected
38068  *  0b00101111..EVTG_OUT2B input is selected
38069  *  0b00110000..EVTG_OUT3A input is selected
38070  *  0b00110001..EVTG_OUT3B input is selected
38071  *  0b00110010..LPTMR0 input is selected
38072  *  0b00110011..LPTMR1 input is selected
38073  *  0b00110100..FlexIO CH0 input is selected
38074  *  0b00110101..FlexIO CH1 input is selected
38075  *  0b00110110..FlexIO CH2 input is selected
38076  *  0b00110111..FlexIO CH3 input is selected
38077  *  0b00111000..SINC Filter CH0 Conversion Complete input is selected
38078  *  0b00111001..SINC Filter CH1 Conversion Complete input is selected
38079  *  0b00111010..SINC Filter CH2 Conversion Complete input is selected
38080  *  0b00111011..SINC Filter CH3 Conversion Complete input is selected
38081  *  0b00111100..SINC Filter CH4 Conversion Complete input is selected
38082  *  0b00111101..GPIO2 Pin Event Trig 0 input is selected
38083  *  0b00111110..GPIO2 Pin Event Trig 1 input is selected
38084  *  0b00111111..GPIO3 Pin Event Trig 0 input is selected
38085  *  0b01000000..GPIO3 Pin Event Trig 1 input is selected
38086  *  0b01000001..WUU input is selected
38087  *  *..
38088  */
38089 #define INPUTMUX_ADC1_TRIGN_ADC1_TRIG_TRIGIN(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_ADC1_TRIGN_ADC1_TRIG_TRIGIN_SHIFT)) & INPUTMUX_ADC1_TRIGN_ADC1_TRIG_TRIGIN_MASK)
38090 /*! @} */
38091 
38092 /* The count of INPUTMUX_ADC1_TRIGN_ADC1_TRIG */
38093 #define INPUTMUX_ADC1_TRIGN_ADC1_TRIG_COUNT      (4U)
38094 
38095 /*! @name DAC0_TRIG - DAC0 Trigger Inputs */
38096 /*! @{ */
38097 
38098 #define INPUTMUX_DAC0_TRIG_TRIGIN_MASK           (0x3FU)
38099 #define INPUTMUX_DAC0_TRIG_TRIGIN_SHIFT          (0U)
38100 /*! TRIGIN - DAC0 trigger input
38101  *  0b000000..PINT PIN_INT0 input is selected
38102  *  0b000001..PINT PIN_INT3 input is selected
38103  *  0b000010..SCT0 SCT_OUT4 input is selected
38104  *  0b000011..SCT0 SCT_OUT5 input is selected
38105  *  0b000100..SCT0 SCT_OUT0 input is selected
38106  *  0b000101..CTIMER0_MAT3 input is selected
38107  *  0b000110..CTIMER1_MAT3 input is selected
38108  *  0b000111..CTIMER2_MAT3 input is selected
38109  *  0b001000..CTIMER2_MAT0 input is selected
38110  *  0b001001..CTIMER3_MAT0 input is selected
38111  *  0b001010..Reserved
38112  *  0b001011..Reserved
38113  *  0b001100..PINT GPIO_INT_BMAT input is selected
38114  *  0b001101..ADC0_tcomp[0] input is selected
38115  *  0b001110..ADC1_tcomp[0] input is selected
38116  *  0b001111..CMP0_OUT input is selected
38117  *  0b010000..CMP1_OUT input is selected
38118  *  0b010001..CMP2_OUT input is selected
38119  *  0b010010..EVTG_OUT0A input is selected
38120  *  0b010011..EVTG_OUT0B input is selected
38121  *  0b010100..EVTG_OUT1A input is selected
38122  *  0b010101..EVTG_OUT1B input is selected
38123  *  0b010110..EVTG_OUT2A input is selected
38124  *  0b010111..EVTG_OUT2B input is selected
38125  *  0b011000..EVTG_OUT3A input is selected
38126  *  0b011001..EVTG_OUT3B input is selected
38127  *  0b011010..LPTMR0 input is selected
38128  *  0b011011..LPTMR1 input is selected
38129  *  0b011100..GPIO2 Pin Event Trig 0 input is selected
38130  *  0b011101..GPIO2 Pin Event Trig 1 input is selected
38131  *  0b011110..GPIO3 Pin Event Trig 0 input is selected
38132  *  0b011111..GPIO3 Pin Event Trig 1 input is selected
38133  *  *..
38134  */
38135 #define INPUTMUX_DAC0_TRIG_TRIGIN(x)             (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DAC0_TRIG_TRIGIN_SHIFT)) & INPUTMUX_DAC0_TRIG_TRIGIN_MASK)
38136 /*! @} */
38137 
38138 /*! @name DAC1_TRIG - DAC1 Trigger Inputs */
38139 /*! @{ */
38140 
38141 #define INPUTMUX_DAC1_TRIG_TRIGIN_MASK           (0x3FU)
38142 #define INPUTMUX_DAC1_TRIG_TRIGIN_SHIFT          (0U)
38143 /*! TRIGIN - DAC1 trigger input
38144  *  0b000000..PINT PIN_INT0 input is selected
38145  *  0b000001..PINT PIN_INT4 input is selected
38146  *  0b000010..SCT0 SCT_OUT4 input is selected
38147  *  0b000011..SCT0 SCT_OUT5 input is selected
38148  *  0b000100..SCT0 SCT_OUT1 input is selected
38149  *  0b000101..CTIMER0_MAT3 input is selected
38150  *  0b000110..CTIMER1_MAT3 input is selected
38151  *  0b000111..CTIMER2_MAT3 input is selected
38152  *  0b001000..CTIMER2_MAT1 input is selected
38153  *  0b001001..CTIMER3_MAT1 input is selected
38154  *  0b001010..Reserved
38155  *  0b001011..Reserved
38156  *  0b001100..PINT GPIO_INT_BMAT input is selected
38157  *  0b001101..ADC0_tcomp[1] input is selected
38158  *  0b001110..ADC1_tcomp[1] input is selected
38159  *  0b001111..CMP0_OUT input is selected
38160  *  0b010000..CMP1_OUT input is selected
38161  *  0b010001..CMP2_OUT input is selected
38162  *  0b010010..EVTG_OUT0A input is selected
38163  *  0b010011..EVTG_OUT0B input is selected
38164  *  0b010100..EVTG_OUT1A input is selected
38165  *  0b010101..EVTG_OUT1B input is selected
38166  *  0b010110..EVTG_OUT2A input is selected
38167  *  0b010111..EVTG_OUT2B input is selected
38168  *  0b011000..EVTG_OUT3A input is selected
38169  *  0b011001..EVTG_OUT3B input is selected
38170  *  0b011010..LPTMR0 input is selected
38171  *  0b011011..LPTMR1 input is selected
38172  *  0b011100..GPIO2 Pin Event Trig 0 input is selected
38173  *  0b011101..GPIO2 Pin Event Trig 1 input is selected
38174  *  0b011110..GPIO3 Pin Event Trig 0 input is selected
38175  *  0b011111..GPIO3 Pin Event Trig 1 input is selected
38176  *  *..
38177  */
38178 #define INPUTMUX_DAC1_TRIG_TRIGIN(x)             (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DAC1_TRIG_TRIGIN_SHIFT)) & INPUTMUX_DAC1_TRIG_TRIGIN_MASK)
38179 /*! @} */
38180 
38181 /*! @name DAC2_TRIG - DAC2 Trigger Inputs */
38182 /*! @{ */
38183 
38184 #define INPUTMUX_DAC2_TRIG_TRIGIN_MASK           (0x3FU)
38185 #define INPUTMUX_DAC2_TRIG_TRIGIN_SHIFT          (0U)
38186 /*! TRIGIN - DAC2 trigger input
38187  *  0b000000..PINT PIN_INT0 input is selected
38188  *  0b000001..PINT PIN_INT5 input is selected
38189  *  0b000010..SCT0 SCT_OUT4 input is selected
38190  *  0b000011..SCT0 SCT_OUT5 input is selected
38191  *  0b000100..SCT0 SCT_OUT2 input is selected
38192  *  0b000101..CTIMER0_MAT3 input is selected
38193  *  0b000110..CTIMER1_MAT3 input is selected
38194  *  0b000111..CTIMER2_MAT3 input is selected
38195  *  0b001000..CTIMER2_MAT2 input is selected
38196  *  0b001001..CTIMER3_MAT2 input is selected
38197  *  0b001010..Reserved
38198  *  0b001011..Reserved
38199  *  0b001100..PINT GPIO_INT_BMAT input is selected
38200  *  0b001101..ADC0_tcomp[2] input is selected
38201  *  0b001110..ADC1_tcomp[2] input is selected
38202  *  0b001111..CMP0_OUT input is selected
38203  *  0b010000..CMP1_OUT input is selected
38204  *  0b010001..CMP2_OUT input is selected
38205  *  0b010010..EVTG_OUT0A input is selected
38206  *  0b010011..EVTG_OUT0B input is selected
38207  *  0b010100..EVTG_OUT1A input is selected
38208  *  0b010101..EVTG_OUT1B input is selected
38209  *  0b010110..EVTG_OUT2A input is selected
38210  *  0b010111..EVTG_OUT2B input is selected
38211  *  0b011000..EVTG_OUT3A input is selected
38212  *  0b011001..EVTG_OUT3B input is selected
38213  *  0b011010..LPTMR0 input is selected
38214  *  0b011011..LPTMR1 input is selected
38215  *  0b011100..GPIO2 Pin Event Trig 0 input is selected
38216  *  0b011101..GPIO2 Pin Event Trig 1 input is selected
38217  *  0b011110..GPIO3 Pin Event Trig 0 input is selected
38218  *  0b011111..GPIO3 Pin Event Trig 1 input is selected
38219  *  *..
38220  */
38221 #define INPUTMUX_DAC2_TRIG_TRIGIN(x)             (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DAC2_TRIG_TRIGIN_SHIFT)) & INPUTMUX_DAC2_TRIG_TRIGIN_MASK)
38222 /*! @} */
38223 
38224 /*! @name QDCN_QDC_TRIG - QDC0 Trigger Input Connections..QDC1 Trigger Input Connections */
38225 /*! @{ */
38226 
38227 #define INPUTMUX_QDCN_QDC_TRIG_INP_MASK          (0x3FU)
38228 #define INPUTMUX_QDCN_QDC_TRIG_INP_SHIFT         (0U)
38229 /*! INP - QDC1 trigger input connections
38230  *  0b000000..PINT PIN_INT0 input is selected
38231  *  0b000001..PINT PIN_INT4 input is selected
38232  *  0b000010..SCT_OUT4 input is selected
38233  *  0b000011..SCT_OUT5 input is selected
38234  *  0b000100..SCT_OUT1 input is selected
38235  *  0b000101..CTIMER0_MAT3 input is selected
38236  *  0b000110..CTIMER1_MAT3 input is selected
38237  *  0b000111..CTIMER2_MAT3 input is selected
38238  *  0b001000..CTIMER1_MAT0 input is selected
38239  *  0b001001..CTIMER3_MAT0 input is selected
38240  *  0b001010..Reserved
38241  *  0b001011..ARM_TXEV input is selected
38242  *  0b001100..PINT GPIO_INT_BMAT input is selected
38243  *  0b001101..ADC0_tcomp[0] input is selected
38244  *  0b001110..ADC0_tcomp[1] input is selected
38245  *  0b001111..ADC0_tcomp[2] input is selected
38246  *  0b010000..ADC0_tcomp[3] input is selected
38247  *  0b010001..ADC1_tcomp[0] input is selected
38248  *  0b010010..ADC1_tcomp[1] input is selected
38249  *  0b010011..ADC1_tcomp[2] input is selected
38250  *  0b010100..ADC1_tcomp[3] input is selected
38251  *  0b010101..CMP0_OUT input is selected
38252  *  0b010110..CMP1_OUT input is selected
38253  *  0b010111..CMP2_OUT input is selected
38254  *  0b011000..PWM1_SM0_MUX_TRIG0 input is selected
38255  *  0b011001..PWM1_SM0_MUX_TRIG1 input is selected
38256  *  0b011010..PWM1_SM1_MUX_TRIG0 input is selected
38257  *  0b011011..PWM1_SM1_MUX_TRIG1 input is selected
38258  *  0b011100..PWM1_SM2_MUX_TRIG0 input is selected
38259  *  0b011101..PWM1_SM2_MUX_TRIG1 input is selected
38260  *  0b011110..PWM1_SM3_MUX_TRIG0 input is selected
38261  *  0b011111..PWM1_SM3_MUX_TRIG1 input is selected
38262  *  0b100000..QDC0_CMP/POS_MATCH input is selected
38263  *  0b100001..QDC1_CMP/POS_MATCH input is selected
38264  *  0b100010..EVTG_OUT0A input is selected
38265  *  0b100011..EVTG_OUT0B input is selected
38266  *  0b100100..EVTG_OUT1A input is selected
38267  *  0b100101..EVTG_OUT1B input is selected
38268  *  0b100110..EVTG_OUT2A input is selected
38269  *  0b100111..EVTG_OUT2B input is selected
38270  *  0b101000..EVTG_OUT3A input is selected
38271  *  0b101001..EVTG_OUT3B input is selected
38272  *  0b101010..TRIG_IN0 input is selected
38273  *  0b101011..TRIG_IN1 input is selected
38274  *  0b101100..TRIG_IN2 input is selected
38275  *  0b101101..TRIG_IN3 input is selected
38276  *  0b101110..TRIG_IN4 input is selected
38277  *  0b101111..TRIG_IN5 input is selected
38278  *  0b110000..TRIG_IN6 input is selected
38279  *  0b110001..TRIG_IN7 input is selected
38280  *  0b110010..TRIG_IN8 input is selected
38281  *  0b110011..TRIG_IN9 input is selected
38282  *  *..
38283  */
38284 #define INPUTMUX_QDCN_QDC_TRIG_INP(x)            (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDCN_QDC_TRIG_INP_SHIFT)) & INPUTMUX_QDCN_QDC_TRIG_INP_MASK)
38285 /*! @} */
38286 
38287 /* The count of INPUTMUX_QDCN_QDC_TRIG */
38288 #define INPUTMUX_QDCN_QDC_TRIG_COUNT             (2U)
38289 
38290 /*! @name QDCN_QDC_HOME - QDC0 Input Connections..QDC1 Input Connections */
38291 /*! @{ */
38292 
38293 #define INPUTMUX_QDCN_QDC_HOME_INP_MASK          (0x3FU)
38294 #define INPUTMUX_QDCN_QDC_HOME_INP_SHIFT         (0U)
38295 /*! INP - QDC1 HOME input connections
38296  *  0b000000..PINT PIN_INT0 input is selected
38297  *  0b000001..PINT PIN_INT4 input is selected
38298  *  0b000010..SCT0 SCT_OUT4 input is selected
38299  *  0b000011..SCT0 SCT_OUT5 input is selected
38300  *  0b000100..SCT0 SCT_OUT1 input is selected
38301  *  0b000101..CTIMER0_MAT3 input is selected
38302  *  0b000110..CTIMER1_MAT3 input is selected
38303  *  0b000111..CTIMER2_MAT3 input is selected
38304  *  0b001000..CTIMER1_MAT0 input is selected
38305  *  0b001001..CTIMER3_MAT0 input is selected
38306  *  0b001010..Reserved
38307  *  0b001011..ARM_TXEV input is selected
38308  *  0b001100..PINT GPIO_INT_BMAT input is selected
38309  *  0b001101..ADC0_tcomp[0] input is selected
38310  *  0b001110..ADC0_tcomp[1] input is selected
38311  *  0b001111..ADC0_tcomp[2] input is selected
38312  *  0b010000..ADC0_tcomp[3] input is selected
38313  *  0b010001..ADC1_tcomp[0] input is selected
38314  *  0b010010..ADC1_tcomp[1] input is selected
38315  *  0b010011..ADC1_tcomp[2] input is selected
38316  *  0b010100..ADC1_tcomp[3] input is selected
38317  *  0b010101..CMP0_OUT input is selected
38318  *  0b010110..CMP1_OUT input is selected
38319  *  0b010111..CMP2_OUT input is selected
38320  *  0b011000..PWM1_SM0_MUX_TRIG0 input is selected
38321  *  0b011001..PWM1_SM0_MUX_TRIG1 input is selected
38322  *  0b011010..PWM1_SM1_MUX_TRIG0 input is selected
38323  *  0b011011..PWM1_SM1_MUX_TRIG1 input is selected
38324  *  0b011100..PWM1_SM2_MUX_TRIG0 input is selected
38325  *  0b011101..PWM1_SM2_MUX_TRIG1 input is selected
38326  *  0b011110..PWM1_SM3_MUX_TRIG0 input is selected
38327  *  0b011111..PWM1_SM3_MUX_TRIG1 input is selected
38328  *  0b100000..QDC0_CMP/POS_MATCH input is selected
38329  *  0b100001..QDC1_CMP/POS_MATCH input is selected
38330  *  0b100010..EVTG_OUT0A input is selected
38331  *  0b100011..EVTG_OUT0B input is selected
38332  *  0b100100..EVTG_OUT1A input is selected
38333  *  0b100101..EVTG_OUT1B input is selected
38334  *  0b100110..EVTG_OUT2A input is selected
38335  *  0b100111..EVTG_OUT2B input is selected
38336  *  0b101000..EVTG_OUT3A input is selected
38337  *  0b101001..EVTG_OUT3B input is selected
38338  *  0b101010..TRIG_IN0 input is selected
38339  *  0b101011..TRIG_IN1 input is selected
38340  *  0b101100..TRIG_IN2 input is selected
38341  *  0b101101..TRIG_IN3 input is selected
38342  *  0b101110..TRIG_IN4 input is selected
38343  *  0b101111..TRIG_IN5 input is selected
38344  *  0b110000..TRIG_IN6 input is selected
38345  *  0b110001..TRIG_IN7 input is selected
38346  *  0b110010..TRIG_IN8 input is selected
38347  *  0b110011..TRIG_IN9 input is selected
38348  *  *..
38349  */
38350 #define INPUTMUX_QDCN_QDC_HOME_INP(x)            (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDCN_QDC_HOME_INP_SHIFT)) & INPUTMUX_QDCN_QDC_HOME_INP_MASK)
38351 /*! @} */
38352 
38353 /* The count of INPUTMUX_QDCN_QDC_HOME */
38354 #define INPUTMUX_QDCN_QDC_HOME_COUNT             (2U)
38355 
38356 /*! @name QDCN_QDC_INDEX - QDC0 Input Connections..QDC1 Input Connections */
38357 /*! @{ */
38358 
38359 #define INPUTMUX_QDCN_QDC_INDEX_INP_MASK         (0x3FU)
38360 #define INPUTMUX_QDCN_QDC_INDEX_INP_SHIFT        (0U)
38361 /*! INP - QDC1 INDEX input connections
38362  *  0b000000..PINT PIN_INT0 input is selected
38363  *  0b000001..PINT PIN_INT4 input is selected
38364  *  0b000010..SCT_OUT4 input is selected
38365  *  0b000011..SCT_OUT5 input is selected
38366  *  0b000100..SCT_OUT1 input is selected
38367  *  0b000101..CTIMER0_MAT3 input is selected
38368  *  0b000110..CTIMER1_MAT3 input is selected
38369  *  0b000111..CTIMER2_MAT3 input is selected
38370  *  0b001000..CTIMER1_MAT0 input is selected
38371  *  0b001001..CTIMER3_MAT0 input is selected
38372  *  0b001010..Reserved
38373  *  0b001011..ARM_TXEV input is selected
38374  *  0b001100..PINT GPIO_INT_BMAT input is selected
38375  *  0b001101..ADC0_tcomp[0] input is selected
38376  *  0b001110..ADC0_tcomp[1] input is selected
38377  *  0b001111..ADC0_tcomp[2] input is selected
38378  *  0b010000..ADC0_tcomp[3] input is selected
38379  *  0b010001..ADC1_tcomp[0] input is selected
38380  *  0b010010..ADC1_tcomp[1] input is selected
38381  *  0b010011..ADC1_tcomp[2] input is selected
38382  *  0b010100..ADC1_tcomp[3] input is selected
38383  *  0b010101..CMP0_OUT input is selected
38384  *  0b010110..CMP1_OUT input is selected
38385  *  0b010111..CMP2_OUT input is selected
38386  *  0b011000..PWM1_SM0_MUX_TRIG0 input is selected
38387  *  0b011001..PWM1_SM0_MUX_TRIG1 input is selected
38388  *  0b011010..PWM1_SM1_MUX_TRIG0 input is selected
38389  *  0b011011..PWM1_SM1_MUX_TRIG1 input is selected
38390  *  0b011100..PWM1_SM2_MUX_TRIG0 input is selected
38391  *  0b011101..PWM1_SM2_MUX_TRIG1 input is selected
38392  *  0b011110..PWM1_SM3_MUX_TRIG0 input is selected
38393  *  0b011111..PWM1_SM3_MUX_TRIG1 input is selected
38394  *  0b100000..QDC0_CMP/POS_MATCH input is selected
38395  *  0b100001..QDC1_CMP/POS_MATCH input is selected
38396  *  0b100010..EVTG_OUT0A input is selected
38397  *  0b100011..EVTG_OUT0B input is selected
38398  *  0b100100..EVTG_OUT1A input is selected
38399  *  0b100101..EVTG_OUT1B input is selected
38400  *  0b100110..EVTG_OUT2A input is selected
38401  *  0b100111..EVTG_OUT2B input is selected
38402  *  0b101000..EVTG_OUT3A input is selected
38403  *  0b101001..EVTG_OUT3B input is selected
38404  *  0b101010..TRIG_IN0 input is selected
38405  *  0b101011..TRIG_IN1 input is selected
38406  *  0b101100..TRIG_IN2 input is selected
38407  *  0b101101..TRIG_IN3 input is selected
38408  *  0b101110..TRIG_IN4 input is selected
38409  *  0b101111..TRIG_IN5 input is selected
38410  *  0b110000..TRIG_IN6 input is selected
38411  *  0b110001..TRIG_IN7 input is selected
38412  *  0b110010..TRIG_IN8 input is selected
38413  *  0b110011..TRIG_IN9 input is selected
38414  *  *..
38415  */
38416 #define INPUTMUX_QDCN_QDC_INDEX_INP(x)           (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDCN_QDC_INDEX_INP_SHIFT)) & INPUTMUX_QDCN_QDC_INDEX_INP_MASK)
38417 /*! @} */
38418 
38419 /* The count of INPUTMUX_QDCN_QDC_INDEX */
38420 #define INPUTMUX_QDCN_QDC_INDEX_COUNT            (2U)
38421 
38422 /*! @name QDCN_QDC_PHASEB - QDC0 Input Connections..QDC1 Input Connections */
38423 /*! @{ */
38424 
38425 #define INPUTMUX_QDCN_QDC_PHASEB_INP_MASK        (0x3FU)
38426 #define INPUTMUX_QDCN_QDC_PHASEB_INP_SHIFT       (0U)
38427 /*! INP - QDC1 PHASEB input connections
38428  *  0b000000..PINT PIN_INT0 input is selected
38429  *  0b000001..PINT PIN_INT4 input is selected
38430  *  0b000010..SCT_OUT4 input is selected
38431  *  0b000011..SCT_OUT5 input is selected
38432  *  0b000100..SCT_OUT1 input is selected
38433  *  0b000101..CTIMER0_MAT3 input is selected
38434  *  0b000110..CTIMER1_MAT3 input is selected
38435  *  0b000111..CTIMER2_MAT3 input is selected
38436  *  0b001000..CTIMER1_MAT0 input is selected
38437  *  0b001001..CTIMER3_MAT0 input is selected
38438  *  0b001010..Reserved
38439  *  0b001011..ARM_TXEV input is selected
38440  *  0b001100..PINT GPIO_INT_BMAT input is selected
38441  *  0b001101..ADC0_tcomp[0] input is selected
38442  *  0b001110..ADC0_tcomp[1] input is selected
38443  *  0b001111..ADC0_tcomp[2] input is selected
38444  *  0b010000..ADC0_tcomp[3] input is selected
38445  *  0b010001..ADC1_tcomp[0] input is selected
38446  *  0b010010..ADC1_tcomp[1] input is selected
38447  *  0b010011..ADC1_tcomp[2] input is selected
38448  *  0b010100..ADC1_tcomp[3] input is selected
38449  *  0b010101..CMP0_OUT input is selected
38450  *  0b010110..CMP1_OUT input is selected
38451  *  0b010111..CMP2_OUT input is selected
38452  *  0b011000..PWM1_SM0_MUX_TRIG0 input is selected
38453  *  0b011001..PWM1_SM0_MUX_TRIG1 input is selected
38454  *  0b011010..PWM1_SM1_MUX_TRIG0 input is selected
38455  *  0b011011..PWM1_SM1_MUX_TRIG1 input is selected
38456  *  0b011100..PWM1_SM2_MUX_TRIG0 input is selected
38457  *  0b011101..PWM1_SM2_MUX_TRIG1 input is selected
38458  *  0b011110..PWM1_SM3_MUX_TRIG0 input is selected
38459  *  0b011111..PWM1_SM3_MUX_TRIG1 input is selected
38460  *  0b100000..QDC0_CMP/POS_MATCH input is selected
38461  *  0b100001..QDC1_CMP/POS_MATCH input is selected
38462  *  0b100010..EVTG_OUT0A input is selected
38463  *  0b100011..EVTG_OUT0B input is selected
38464  *  0b100100..EVTG_OUT1A input is selected
38465  *  0b100101..EVTG_OUT1B input is selected
38466  *  0b100110..EVTG_OUT2A input is selected
38467  *  0b100111..EVTG_OUT2B input is selected
38468  *  0b101000..EVTG_OUT3A input is selected
38469  *  0b101001..EVTG_OUT3B input is selected
38470  *  0b101010..TRIG_IN0 input is selected
38471  *  0b101011..TRIG_IN1 input is selected
38472  *  0b101100..TRIG_IN2 input is selected
38473  *  0b101101..TRIG_IN3 input is selected
38474  *  0b101110..TRIG_IN4 input is selected
38475  *  0b101111..TRIG_IN5 input is selected
38476  *  0b110000..TRIG_IN6 input is selected
38477  *  0b110001..TRIG_IN7 input is selected
38478  *  0b110010..TRIG_IN8 input is selected
38479  *  0b110011..TRIG_IN9 input is selected
38480  *  *..
38481  */
38482 #define INPUTMUX_QDCN_QDC_PHASEB_INP(x)          (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDCN_QDC_PHASEB_INP_SHIFT)) & INPUTMUX_QDCN_QDC_PHASEB_INP_MASK)
38483 /*! @} */
38484 
38485 /* The count of INPUTMUX_QDCN_QDC_PHASEB */
38486 #define INPUTMUX_QDCN_QDC_PHASEB_COUNT           (2U)
38487 
38488 /*! @name QDCN_QDC_PHASEA - QDC0 Input Connections..QDC1 Input Connections */
38489 /*! @{ */
38490 
38491 #define INPUTMUX_QDCN_QDC_PHASEA_INP_MASK        (0x3FU)
38492 #define INPUTMUX_QDCN_QDC_PHASEA_INP_SHIFT       (0U)
38493 /*! INP - QDC1 PHASEA input connections
38494  *  0b000000..PINT PIN_INT0 input is selected
38495  *  0b000001..PINT PIN_INT4 input is selected
38496  *  0b000010..SCT_OUT4 input is selected
38497  *  0b000011..SCT_OUT5 input is selected
38498  *  0b000100..SCT_OUT1 input is selected
38499  *  0b000101..CTIMER0_MAT3 input is selected
38500  *  0b000110..CTIMER1_MAT3 input is selected
38501  *  0b000111..CTIMER2_MAT3 input is selected
38502  *  0b001000..CTIMER1_MAT0 input is selected
38503  *  0b001001..CTIMER3_MAT0 input is selected
38504  *  0b001010..Reserved
38505  *  0b001011..ARM_TXEV input is selected
38506  *  0b001100..PINT GPIO_INT_BMAT input is selected
38507  *  0b001101..ADC0_tcomp[0] input is selected
38508  *  0b001110..ADC0_tcomp[1] input is selected
38509  *  0b001111..ADC0_tcomp[2] input is selected
38510  *  0b010000..ADC0_tcomp[3] input is selected
38511  *  0b010001..ADC1_tcomp[0] input is selected
38512  *  0b010010..ADC1_tcomp[1] input is selected
38513  *  0b010011..ADC1_tcomp[2] input is selected
38514  *  0b010100..ADC1_tcomp[3] input is selected
38515  *  0b010101..CMP0_OUT input is selected
38516  *  0b010110..CMP1_OUT input is selected
38517  *  0b010111..CMP2_OUT input is selected
38518  *  0b011000..PWM1_SM0_MUX_TRIG0 input is selected
38519  *  0b011001..PWM1_SM0_MUX_TRIG1 input is selected
38520  *  0b011010..PWM1_SM1_MUX_TRIG0 input is selected
38521  *  0b011011..PWM1_SM1_MUX_TRIG1 input is selected
38522  *  0b011100..PWM1_SM2_MUX_TRIG0 input is selected
38523  *  0b011101..PWM1_SM2_MUX_TRIG1 input is selected
38524  *  0b011110..PWM1_SM3_MUX_TRIG0 input is selected
38525  *  0b011111..PWM1_SM3_MUX_TRIG1 input is selected
38526  *  0b100000..QDC0_CMP/POS_MATCH input is selected
38527  *  0b100001..QDC1_CMP/POS_MATCH input is selected
38528  *  0b100010..EVTG_OUT0A input is selected
38529  *  0b100011..EVTG_OUT0B input is selected
38530  *  0b100100..EVTG_OUT1A input is selected
38531  *  0b100101..EVTG_OUT1B input is selected
38532  *  0b100110..EVTG_OUT2A input is selected
38533  *  0b100111..EVTG_OUT2B input is selected
38534  *  0b101000..EVTG_OUT3A input is selected
38535  *  0b101001..EVTG_OUT3B input is selected
38536  *  0b101010..TRIG_IN0 input is selected
38537  *  0b101011..TRIG_IN1 input is selected
38538  *  0b101100..TRIG_IN2 input is selected
38539  *  0b101101..TRIG_IN3 input is selected
38540  *  0b101110..TRIG_IN4 input is selected
38541  *  0b101111..TRIG_IN5 input is selected
38542  *  0b110000..TRIG_IN6 input is selected
38543  *  0b110001..TRIG_IN7 input is selected
38544  *  0b110010..TRIG_IN8 input is selected
38545  *  0b110011..TRIG_IN9 input is selected
38546  *  *..
38547  */
38548 #define INPUTMUX_QDCN_QDC_PHASEA_INP(x)          (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDCN_QDC_PHASEA_INP_SHIFT)) & INPUTMUX_QDCN_QDC_PHASEA_INP_MASK)
38549 /*! @} */
38550 
38551 /* The count of INPUTMUX_QDCN_QDC_PHASEA */
38552 #define INPUTMUX_QDCN_QDC_PHASEA_COUNT           (2U)
38553 
38554 /*! @name FLEXPWM_SM_EXTSYNC_FLEXPWM0_SM_EXTSYNC - PWM0 External Synchronization */
38555 /*! @{ */
38556 
38557 #define INPUTMUX_FLEXPWM_SM_EXTSYNC_FLEXPWM0_SM_EXTSYNC_TRIGIN_MASK (0x3FU)
38558 #define INPUTMUX_FLEXPWM_SM_EXTSYNC_FLEXPWM0_SM_EXTSYNC_TRIGIN_SHIFT (0U)
38559 /*! TRIGIN - EXTSYNC input connections for PWM0
38560  *  0b000000..PINT PIN_INT0 input is selected
38561  *  0b000001..PINT PIN_INT5 input is selected
38562  *  0b000010..SCT_OUT4 input is selected
38563  *  0b000011..SCT_OUT5 input is selected
38564  *  0b000100..SCT_OUT2 input is selected
38565  *  0b000101..CTIMER0_MAT3 input is selected
38566  *  0b000110..CTIMER1_MAT3 input is selected
38567  *  0b000111..CTIMER2_MAT3 input is selected
38568  *  0b001000..CTIMER2_MAT0 input is selected
38569  *  0b001001..CTIMER4_MAT0 input is selected
38570  *  0b001010..Reserved
38571  *  0b001011..ARM_TXEV input is selected
38572  *  0b001100..PINT GPIO_INT_BMAT input is selected
38573  *  0b001101..ADC0_tcomp[0] input is selected
38574  *  0b001110..ADC0_tcomp[1] input is selected
38575  *  0b001111..ADC0_tcomp[2] input is selected
38576  *  0b010000..ADC0_tcomp[3] input is selected
38577  *  0b010001..ADC1_tcomp[0] input is selected
38578  *  0b010010..ADC1_tcomp[1] input is selected
38579  *  0b010011..ADC1_tcomp[2] input is selected
38580  *  0b010100..ADC1_tcomp[3] input is selected
38581  *  0b010101..CMP0_OUT input is selected
38582  *  0b010110..CMP1_OUT input is selected
38583  *  0b010111..CMP2_OUT input is selected
38584  *  0b011000..PWM1_SM0_MUX_TRIG0 input is selected
38585  *  0b011001..PWM1_SM0_MUX_TRIG1 input is selected
38586  *  0b011010..PWM1_SM1_MUX_TRIG0 input is selected
38587  *  0b011011..PWM1_SM1_MUX_TRIG1 input is selected
38588  *  0b011100..PWM1_SM2_MUX_TRIG0 input is selected
38589  *  0b011101..PWM1_SM2_MUX_TRIG1 input is selected
38590  *  0b011110..PWM1_SM3_MUX_TRIG0 input is selected
38591  *  0b011111..PWM1_SM3_MUX_TRIG1 input is selected
38592  *  0b100000..QDC0_CMP/POS_MATCH input is selected
38593  *  0b100001..QDC1_CMP/POS_MATCH input is selected
38594  *  0b100010..EVTG_OUT0A input is selected
38595  *  0b100011..EVTG_OUT0B input is selected
38596  *  0b100100..EVTG_OUT1A input is selected
38597  *  0b100101..EVTG_OUT1B input is selected
38598  *  0b100110..EVTG_OUT2A input is selected
38599  *  0b100111..EVTG_OUT2B input is selected
38600  *  0b101000..EVTG_OUT3A input is selected
38601  *  0b101001..EVTG_OUT3B input is selected
38602  *  0b101010..TRIG_IN0 input is selected
38603  *  0b101011..TRIG_IN1 input is selected
38604  *  0b101100..TRIG_IN2 input is selected
38605  *  0b101101..TRIG_IN3 input is selected
38606  *  0b101110..TRIG_IN4 input is selected
38607  *  0b101111..TRIG_IN5 input is selected
38608  *  0b110000..TRIG_IN6 input is selected
38609  *  0b110001..TRIG_IN7 input is selected
38610  *  0b110010..TRIG_IN8 input is selected
38611  *  0b110011..TRIG_IN9 input is selected
38612  *  0b110100..SINC Filter CH0 sync Break input is selected
38613  *  0b110101..SINC Filter CH1 sync Break input is selected
38614  *  0b110110..SINC Filter CH2 sync Break input is selected
38615  *  0b110111..SINC Filter CH3 sync Break input is selected
38616  *  0b111000..SINC Filter CH4 sync Break input is selected
38617  *  0b111001..GPIO2 Pin Event Trig 0 input is selected
38618  *  0b111010..GPIO2 Pin Event Trig 1 input is selected
38619  *  0b111011..GPIO3 Pin Event Trig 0 input is selected
38620  *  0b111100..GPIO3 Pin Event Trig 1 input is selected
38621  *  *..
38622  */
38623 #define INPUTMUX_FLEXPWM_SM_EXTSYNC_FLEXPWM0_SM_EXTSYNC_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM_SM_EXTSYNC_FLEXPWM0_SM_EXTSYNC_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM_SM_EXTSYNC_FLEXPWM0_SM_EXTSYNC_TRIGIN_MASK)
38624 /*! @} */
38625 
38626 /* The count of INPUTMUX_FLEXPWM_SM_EXTSYNC_FLEXPWM0_SM_EXTSYNC */
38627 #define INPUTMUX_FLEXPWM_SM_EXTSYNC_FLEXPWM0_SM_EXTSYNC_COUNT (4U)
38628 
38629 /*! @name FLEXPWM_SM_EXT_FLEXPWM0_SM_EXTA - PWM0 Input Trigger Connections */
38630 /*! @{ */
38631 
38632 #define INPUTMUX_FLEXPWM_SM_EXT_FLEXPWM0_SM_EXTA_TRIGIN_MASK (0x3FU)
38633 #define INPUTMUX_FLEXPWM_SM_EXT_FLEXPWM0_SM_EXTA_TRIGIN_SHIFT (0U)
38634 /*! TRIGIN - EXTA input connections for PWM0
38635  *  0b000000..PINT PIN_INT0 input is selected
38636  *  0b000001..PINT PIN_INT5 input is selected
38637  *  0b000010..SCT_OUT4 input is selected
38638  *  0b000011..SCT_OUT5 input is selected
38639  *  0b000100..SCT_OUT2 input is selected
38640  *  0b000101..CTIMER0_MAT3 input is selected
38641  *  0b000110..CTIMER1_MAT3 input is selected
38642  *  0b000111..CTIMER2_MAT3 input is selected
38643  *  0b001000..CTIMER2_MAT0 input is selected
38644  *  0b001001..CTIMER4_MAT0 input is selected
38645  *  0b001010..Reserved
38646  *  0b001011..ARM_TXEV input is selected
38647  *  0b001100..PINT GPIO_INT_BMAT input is selected
38648  *  0b001101..ADC0_tcomp[0] input is selected
38649  *  0b001110..ADC0_tcomp[1] input is selected
38650  *  0b001111..ADC0_tcomp[2] input is selected
38651  *  0b010000..ADC0_tcomp[3] input is selected
38652  *  0b010001..ADC1_tcomp[0] input is selected
38653  *  0b010010..ADC1_tcomp[1] input is selected
38654  *  0b010011..ADC1_tcomp[2] input is selected
38655  *  0b010100..ADC1_tcomp[3] input is selected
38656  *  0b010101..CMP0_OUT input is selected
38657  *  0b010110..CMP1_OUT input is selected
38658  *  0b010111..CMP2_OUT input is selected
38659  *  0b011000..PWM1_SM0_MUX_TRIG0 input is selected
38660  *  0b011001..PWM1_SM0_MUX_TRIG1 input is selected
38661  *  0b011010..PWM1_SM1_MUX_TRIG0 input is selected
38662  *  0b011011..PWM1_SM1_MUX_TRIG1 input is selected
38663  *  0b011100..PWM1_SM2_MUX_TRIG0 input is selected
38664  *  0b011101..PWM1_SM2_MUX_TRIG1 input is selected
38665  *  0b011110..PWM1_SM3_MUX_TRIG0 input is selected
38666  *  0b011111..PWM1_SM3_MUX_TRIG1 input is selected
38667  *  0b100000..QDC0_CMP/POS_MATCH input is selected
38668  *  0b100001..QDC1_CMP/POS_MATCH input is selected
38669  *  0b100010..EVTG_OUT0A input is selected
38670  *  0b100011..EVTG_OUT0B input is selected
38671  *  0b100100..EVTG_OUT1A input is selected
38672  *  0b100101..EVTG_OUT1B input is selected
38673  *  0b100110..EVTG_OUT2A input is selected
38674  *  0b100111..EVTG_OUT2B input is selected
38675  *  0b101000..EVTG_OUT3A input is selected
38676  *  0b101001..EVTG_OUT3B input is selected
38677  *  0b101010..TRIG_IN0 input is selected
38678  *  0b101011..TRIG_IN1 input is selected
38679  *  0b101100..TRIG_IN2 input is selected
38680  *  0b101101..TRIG_IN3 input is selected
38681  *  0b101110..TRIG_IN4 input is selected
38682  *  0b101111..TRIG_IN5 input is selected
38683  *  0b110000..TRIG_IN6 input is selected
38684  *  0b110001..TRIG_IN7 input is selected
38685  *  0b110010..TRIG_IN8 input is selected
38686  *  0b110011..TRIG_IN9 input is selected
38687  *  0b110100..SINC Filter CH0 sync Break input is selected
38688  *  0b110101..SINC Filter CH1 sync Break input is selected
38689  *  0b110110..SINC Filter CH2 sync Break input is selected
38690  *  0b110111..SINC Filter CH3 sync Break input is selected
38691  *  0b111000..SINC Filter CH4 sync Break input is selected
38692  *  0b111001..GPIO2 Pin Event Trig 0 input is selected
38693  *  0b111010..GPIO2 Pin Event Trig 1 input is selected
38694  *  0b111011..GPIO3 Pin Event Trig 0 input is selected
38695  *  0b111100..GPIO3 Pin Event Trig 1 input is selected
38696  *  *..
38697  */
38698 #define INPUTMUX_FLEXPWM_SM_EXT_FLEXPWM0_SM_EXTA_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM_SM_EXT_FLEXPWM0_SM_EXTA_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM_SM_EXT_FLEXPWM0_SM_EXTA_TRIGIN_MASK)
38699 /*! @} */
38700 
38701 /* The count of INPUTMUX_FLEXPWM_SM_EXT_FLEXPWM0_SM_EXTA */
38702 #define INPUTMUX_FLEXPWM_SM_EXT_FLEXPWM0_SM_EXTA_COUNT (4U)
38703 
38704 /*! @name FLEXPWM0_EXTFORCE - PWM0 External Force Trigger Connections */
38705 /*! @{ */
38706 
38707 #define INPUTMUX_FLEXPWM0_EXTFORCE_TRIGIN_MASK   (0x3FU)
38708 #define INPUTMUX_FLEXPWM0_EXTFORCE_TRIGIN_SHIFT  (0U)
38709 /*! TRIGIN - EXTFORCE input connections for PWM0
38710  *  0b000000..PINT PIN_INT0 input is selected
38711  *  0b000001..PINT PIN_INT5 input is selected
38712  *  0b000010..SCT_OUT4 input is selected
38713  *  0b000011..SCT_OUT5 input is selected
38714  *  0b000100..SCT_OUT2 input is selected
38715  *  0b000101..CTIMER0_MAT3 input is selected
38716  *  0b000110..CTIMER1_MAT3 input is selected
38717  *  0b000111..CTIMER2_MAT3 input is selected
38718  *  0b001000..CTIMER2_MAT0 input is selected
38719  *  0b001001..CTIMER4_MAT0 input is selected
38720  *  0b001010..Reserved
38721  *  0b001011..ARM_TXEV input is selected
38722  *  0b001100..PINT GPIO_INT_BMAT input is selected
38723  *  0b001101..ADC0_tcomp[0] input is selected
38724  *  0b001110..ADC0_tcomp[1] input is selected
38725  *  0b001111..ADC0_tcomp[2] input is selected
38726  *  0b010000..ADC0_tcomp[3] input is selected
38727  *  0b010001..ADC1_tcomp[0] input is selected
38728  *  0b010010..ADC1_tcomp[1] input is selected
38729  *  0b010011..ADC1_tcomp[2] input is selected
38730  *  0b010100..ADC1_tcomp[3] input is selected
38731  *  0b010101..CMP0_OUT input is selected
38732  *  0b010110..CMP1_OUT input is selected
38733  *  0b010111..CMP2_OUT input is selected
38734  *  0b011000..PWM1_SM0_MUX_TRIG0 input is selected
38735  *  0b011001..PWM1_SM0_MUX_TRIG1 input is selected
38736  *  0b011010..PWM1_SM1_MUX_TRIG0 input is selected
38737  *  0b011011..PWM1_SM1_MUX_TRIG1 input is selected
38738  *  0b011100..PWM1_SM2_MUX_TRIG0 input is selected
38739  *  0b011101..PWM1_SM2_MUX_TRIG1 input is selected
38740  *  0b011110..PWM1_SM3_MUX_TRIG0 input is selected
38741  *  0b011111..PWM1_SM3_MUX_TRIG1 input is selected
38742  *  0b100000..QDC0_CMP/POS_MATCH input is selected
38743  *  0b100001..QDC1_CMP/POS_MATCH input is selected
38744  *  0b100010..EVTG_OUT0A input is selected
38745  *  0b100011..EVTG_OUT0B input is selected
38746  *  0b100100..EVTG_OUT1A input is selected
38747  *  0b100101..EVTG_OUT1B input is selected
38748  *  0b100110..EVTG_OUT2A input is selected
38749  *  0b100111..EVTG_OUT2B input is selected
38750  *  0b101000..EVTG_OUT3A input is selected
38751  *  0b101001..EVTG_OUT3B input is selected
38752  *  0b101010..TRIG_IN0 input is selected
38753  *  0b101011..TRIG_IN1 input is selected
38754  *  0b101100..TRIG_IN2 input is selected
38755  *  0b101101..TRIG_IN3 input is selected
38756  *  0b101110..TRIG_IN4 input is selected
38757  *  0b101111..TRIG_IN5 input is selected
38758  *  0b110000..TRIG_IN6 input is selected
38759  *  0b110001..TRIG_IN7 input is selected
38760  *  0b110010..TRIG_IN8 input is selected
38761  *  0b110011..TRIG_IN9 input is selected
38762  *  0b110100..SINC Filter CH0 sync Break input is selected
38763  *  0b110101..SINC Filter CH1 sync Break input is selected
38764  *  0b110110..SINC Filter CH2 sync Break input is selected
38765  *  0b110111..SINC Filter CH3 sync Break input is selected
38766  *  0b111000..SINC Filter CH4 sync Break input is selected
38767  *  0b111001..GPIO2 Pin Event Trig 0 input is selected
38768  *  0b111010..GPIO2 Pin Event Trig 1 input is selected
38769  *  0b111011..GPIO3 Pin Event Trig 0 input is selected
38770  *  0b111100..GPIO3 Pin Event Trig 1 input is selected
38771  *  *..
38772  */
38773 #define INPUTMUX_FLEXPWM0_EXTFORCE_TRIGIN(x)     (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM0_EXTFORCE_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM0_EXTFORCE_TRIGIN_MASK)
38774 /*! @} */
38775 
38776 /*! @name FLEXPWM_FAULT_FLEXPWM0_FAULT - PWM0 Fault Input Trigger Connections */
38777 /*! @{ */
38778 
38779 #define INPUTMUX_FLEXPWM_FAULT_FLEXPWM0_FAULT_TRIGIN_MASK (0x3FU)
38780 #define INPUTMUX_FLEXPWM_FAULT_FLEXPWM0_FAULT_TRIGIN_SHIFT (0U)
38781 /*! TRIGIN - FAULT input connections for PWM0
38782  *  0b000000..PINT PIN_INT0 input is selected
38783  *  0b000001..PINT PIN_INT5 input is selected
38784  *  0b000010..SCT_OUT4 input is selected
38785  *  0b000011..SCT_OUT5 input is selected
38786  *  0b000100..SCT_OUT2 input is selected
38787  *  0b000101..CTIMER0_MAT3 input is selected
38788  *  0b000110..CTIMER1_MAT3 input is selected
38789  *  0b000111..CTIMER2_MAT3 input is selected
38790  *  0b001000..CTIMER2_MAT0 input is selected
38791  *  0b001001..CTIMER4_MAT0 input is selected
38792  *  0b001010..Reserved
38793  *  0b001011..ARM_TXEV input is selected
38794  *  0b001100..PINT GPIO_INT_BMAT input is selected
38795  *  0b001101..ADC0_tcomp[0] input is selected
38796  *  0b001110..ADC0_tcomp[1] input is selected
38797  *  0b001111..ADC0_tcomp[2] input is selected
38798  *  0b010000..ADC0_tcomp[3] input is selected
38799  *  0b010001..ADC1_tcomp[0] input is selected
38800  *  0b010010..ADC1_tcomp[1] input is selected
38801  *  0b010011..ADC1_tcomp[2] input is selected
38802  *  0b010100..ADC1_tcomp[3] input is selected
38803  *  0b010101..CMP0_OUT input is selected
38804  *  0b010110..CMP1_OUT input is selected
38805  *  0b010111..CMP2_OUT input is selected
38806  *  0b011000..PWM1_SM0_MUX_TRIG0 input is selected
38807  *  0b011001..PWM1_SM0_MUX_TRIG1 input is selected
38808  *  0b011010..PWM1_SM1_MUX_TRIG0 input is selected
38809  *  0b011011..PWM1_SM1_MUX_TRIG1 input is selected
38810  *  0b011100..PWM1_SM2_MUX_TRIG0 input is selected
38811  *  0b011101..PWM1_SM2_MUX_TRIG1 input is selected
38812  *  0b011110..PWM1_SM3_MUX_TRIG0 input is selected
38813  *  0b011111..PWM1_SM3_MUX_TRIG1 input is selected
38814  *  0b100000..QDC0_CMP/POS_MATCH input is selected
38815  *  0b100001..QDC1_CMP/POS_MATCH input is selected
38816  *  0b100010..EVTG_OUT0A input is selected
38817  *  0b100011..EVTG_OUT0B input is selected
38818  *  0b100100..EVTG_OUT1A input is selected
38819  *  0b100101..EVTG_OUT1B input is selected
38820  *  0b100110..EVTG_OUT2A input is selected
38821  *  0b100111..EVTG_OUT2B input is selected
38822  *  0b101000..EVTG_OUT3A input is selected
38823  *  0b101001..EVTG_OUT3B input is selected
38824  *  0b101010..TRIG_IN0 input is selected
38825  *  0b101011..TRIG_IN1 input is selected
38826  *  0b101100..TRIG_IN2 input is selected
38827  *  0b101101..TRIG_IN3 input is selected
38828  *  0b101110..TRIG_IN4 input is selected
38829  *  0b101111..TRIG_IN5 input is selected
38830  *  0b110000..TRIG_IN6 input is selected
38831  *  0b110001..TRIG_IN7 input is selected
38832  *  0b110010..TRIG_IN8 input is selected
38833  *  0b110011..TRIG_IN9 input is selected
38834  *  0b110100..SINC Filter CH0 sync Break input is selected
38835  *  0b110101..SINC Filter CH1 sync Break input is selected
38836  *  0b110110..SINC Filter CH2 sync Break input is selected
38837  *  0b110111..SINC Filter CH3 sync Break input is selected
38838  *  0b111000..SINC Filter CH4 sync Break input is selected
38839  *  0b111001..GPIO2 Pin Event Trig 0 input is selected
38840  *  0b111010..GPIO2 Pin Event Trig 1 input is selected
38841  *  0b111011..GPIO3 Pin Event Trig 0 input is selected
38842  *  0b111100..GPIO3 Pin Event Trig 1 input is selected
38843  *  *..
38844  */
38845 #define INPUTMUX_FLEXPWM_FAULT_FLEXPWM0_FAULT_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM_FAULT_FLEXPWM0_FAULT_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM_FAULT_FLEXPWM0_FAULT_TRIGIN_MASK)
38846 /*! @} */
38847 
38848 /* The count of INPUTMUX_FLEXPWM_FAULT_FLEXPWM0_FAULT */
38849 #define INPUTMUX_FLEXPWM_FAULT_FLEXPWM0_FAULT_COUNT (4U)
38850 
38851 /*! @name FLEXPWM1_SM_EXTSYNC_ARRAY_FLEXPWM1_SM_EXTSYNC - PWM1 External Synchronization */
38852 /*! @{ */
38853 
38854 #define INPUTMUX_FLEXPWM1_SM_EXTSYNC_ARRAY_FLEXPWM1_SM_EXTSYNC_TRIGIN_MASK (0x3FU)
38855 #define INPUTMUX_FLEXPWM1_SM_EXTSYNC_ARRAY_FLEXPWM1_SM_EXTSYNC_TRIGIN_SHIFT (0U)
38856 /*! TRIGIN - EXTSYNC input connections for PWM1
38857  *  0b000000..PINT PIN_INT0 input is selected
38858  *  0b000001..PINT PIN_INT2 input is selected
38859  *  0b000010..SCT_OUT4 input is selected
38860  *  0b000011..SCT_OUT5 input is selected
38861  *  0b000100..SCT_OUT3 input is selected
38862  *  0b000101..CTIMER0_MAT3 input is selected
38863  *  0b000110..CTIMER1_MAT3 input is selected
38864  *  0b000111..CTIMER2_MAT3 input is selected
38865  *  0b001000..CTIMER2_MAT1 input is selected
38866  *  0b001001..CTIMER4_MAT1 input is selected
38867  *  0b001010..Reserved
38868  *  0b001011..ARM_TXEV input is selected
38869  *  0b001100..PINT GPIO_INT_BMAT input is selected
38870  *  0b001101..ADC0_tcomp[0] input is selected
38871  *  0b001110..ADC0_tcomp[1] input is selected
38872  *  0b001111..ADC0_tcomp[2] input is selected
38873  *  0b010000..ADC0_tcomp[3] input is selected
38874  *  0b010001..ADC1_tcomp[0] input is selected
38875  *  0b010010..ADC1_tcomp[1] input is selected
38876  *  0b010011..ADC1_tcomp[2] input is selected
38877  *  0b010100..ADC1_tcomp[3] input is selected
38878  *  0b010101..CMP0_OUT input is selected
38879  *  0b010110..CMP1_OUT input is selected
38880  *  0b010111..CMP2_OUT input is selected
38881  *  0b011000..PWM0_SM0_MUX_TRIG0 input is selected
38882  *  0b011001..PWM0_SM0_MUX_TRIG1 input is selected
38883  *  0b011010..PWM0_SM1_MUX_TRIG0 input is selected
38884  *  0b011011..PWM0_SM1_MUX_TRIG1 input is selected
38885  *  0b011100..PWM0_SM2_MUX_TRIG0 input is selected
38886  *  0b011101..PWM0_SM2_MUX_TRIG1 input is selected
38887  *  0b011110..PWM0_SM3_MUX_TRIG0 input is selected
38888  *  0b011111..PWM0_SM3_MUX_TRIG1 input is selected
38889  *  0b100000..QDC0_CMP/POS_MATCH input is selected
38890  *  0b100001..QDC1_CMP/POS_MATCH input is selected
38891  *  0b100010..EVTG_OUT0A input is selected
38892  *  0b100011..EVTG_OUT0B input is selected
38893  *  0b100100..EVTG_OUT1A input is selected
38894  *  0b100101..EVTG_OUT1B input is selected
38895  *  0b100110..EVTG_OUT2A input is selected
38896  *  0b100111..EVTG_OUT2B input is selected
38897  *  0b101000..EVTG_OUT3A input is selected
38898  *  0b101001..EVTG_OUT3B input is selected
38899  *  0b101010..TRIG_IN0 input is selected
38900  *  0b101011..TRIG_IN1 input is selected
38901  *  0b101100..TRIG_IN2 input is selected
38902  *  0b101101..TRIG_IN3 input is selected
38903  *  0b101110..TRIG_IN4 input is selected
38904  *  0b101111..TRIG_IN5 input is selected
38905  *  0b110000..TRIG_IN6 input is selected
38906  *  0b110001..TRIG_IN7 input is selected
38907  *  0b110010..TRIG_IN8 input is selected
38908  *  0b110011..TRIG_IN9 input is selected
38909  *  0b110100..SINC Filter CH0 sync Break input is selected
38910  *  0b110101..SINC Filter CH1 sync Break input is selected
38911  *  0b110110..SINC Filter CH2 sync Break input is selected
38912  *  0b110111..SINC Filter CH3 sync Break input is selected
38913  *  0b111000..SINC Filter CH4 sync Break input is selected
38914  *  0b111001..GPIO2 Pin Event Trig 0 input is selected
38915  *  0b111010..GPIO2 Pin Event Trig 1 input is selected
38916  *  0b111011..GPIO3 Pin Event Trig 0 input is selected
38917  *  0b111100..GPIO3 Pin Event Trig 1 input is selected
38918  *  *..
38919  */
38920 #define INPUTMUX_FLEXPWM1_SM_EXTSYNC_ARRAY_FLEXPWM1_SM_EXTSYNC_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM1_SM_EXTSYNC_ARRAY_FLEXPWM1_SM_EXTSYNC_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM1_SM_EXTSYNC_ARRAY_FLEXPWM1_SM_EXTSYNC_TRIGIN_MASK)
38921 /*! @} */
38922 
38923 /* The count of INPUTMUX_FLEXPWM1_SM_EXTSYNC_ARRAY_FLEXPWM1_SM_EXTSYNC */
38924 #define INPUTMUX_FLEXPWM1_SM_EXTSYNC_ARRAY_FLEXPWM1_SM_EXTSYNC_COUNT (4U)
38925 
38926 /*! @name FLEXPWM_SM1_EXTA_ARRAY_FLEXPWM1_SM_EXTA - PWM1 Input EXTA Connections */
38927 /*! @{ */
38928 
38929 #define INPUTMUX_FLEXPWM_SM1_EXTA_ARRAY_FLEXPWM1_SM_EXTA_TRIGIN_MASK (0x3FU)
38930 #define INPUTMUX_FLEXPWM_SM1_EXTA_ARRAY_FLEXPWM1_SM_EXTA_TRIGIN_SHIFT (0U)
38931 /*! TRIGIN - EXTA input connections for PWM1
38932  *  0b000000..PINT PIN_INT0 input is selected
38933  *  0b000001..PINT PIN_INT2 input is selected
38934  *  0b000010..SCT_OUT4 input is selected
38935  *  0b000011..SCT_OUT5 input is selected
38936  *  0b000100..SCT_OUT3 input is selected
38937  *  0b000101..CTIMER0_MAT3 input is selected
38938  *  0b000110..CTIMER1_MAT3 input is selected
38939  *  0b000111..CTIMER2_MAT3 input is selected
38940  *  0b001000..CTIMER2_MAT1 input is selected
38941  *  0b001001..CTIMER4_MAT1 input is selected
38942  *  0b001010..Reserved
38943  *  0b001011..ARM_TXEV input is selected
38944  *  0b001100..PINT GPIO_INT_BMAT input is selected
38945  *  0b001101..ADC0_tcomp[0] input is selected
38946  *  0b001110..ADC0_tcomp[1] input is selected
38947  *  0b001111..ADC0_tcomp[2] input is selected
38948  *  0b010000..ADC0_tcomp[3] input is selected
38949  *  0b010001..ADC1_tcomp[0] input is selected
38950  *  0b010010..ADC1_tcomp[1] input is selected
38951  *  0b010011..ADC1_tcomp[2] input is selected
38952  *  0b010100..ADC1_tcomp[3] input is selected
38953  *  0b010101..CMP0_OUT input is selected
38954  *  0b010110..CMP1_OUT input is selected
38955  *  0b010111..CMP2_OUT input is selected
38956  *  0b011000..PWM0_SM0_MUX_TRIG0 input is selected
38957  *  0b011001..PWM0_SM0_MUX_TRIG1 input is selected
38958  *  0b011010..PWM0_SM1_MUX_TRIG0 input is selected
38959  *  0b011011..PWM0_SM1_MUX_TRIG1 input is selected
38960  *  0b011100..PWM0_SM2_MUX_TRIG0 input is selected
38961  *  0b011101..PWM0_SM2_MUX_TRIG1 input is selected
38962  *  0b011110..PWM0_SM3_MUX_TRIG0 input is selected
38963  *  0b011111..PWM0_SM3_MUX_TRIG1 input is selected
38964  *  0b100000..QDC0_CMP/POS_MATCH input is selected
38965  *  0b100001..QDC1_CMP/POS_MATCH input is selected
38966  *  0b100010..EVTG_OUT0A input is selected
38967  *  0b100011..EVTG_OUT0B input is selected
38968  *  0b100100..EVTG_OUT1A input is selected
38969  *  0b100101..EVTG_OUT1B input is selected
38970  *  0b100110..EVTG_OUT2A input is selected
38971  *  0b100111..EVTG_OUT2B input is selected
38972  *  0b101000..EVTG_OUT3A input is selected
38973  *  0b101001..EVTG_OUT3B input is selected
38974  *  0b101010..TRIG_IN0 input is selected
38975  *  0b101011..TRIG_IN1 input is selected
38976  *  0b101100..TRIG_IN2 input is selected
38977  *  0b101101..TRIG_IN3 input is selected
38978  *  0b101110..TRIG_IN4 input is selected
38979  *  0b101111..TRIG_IN5 input is selected
38980  *  0b110000..TRIG_IN6 input is selected
38981  *  0b110001..TRIG_IN7 input is selected
38982  *  0b110010..TRIG_IN8 input is selected
38983  *  0b110011..TRIG_IN9 input is selected
38984  *  0b110100..SINC Filter CH0 sync Break input is selected
38985  *  0b110101..SINC Filter CH1 sync Break input is selected
38986  *  0b110110..SINC Filter CH2 sync Break input is selected
38987  *  0b110111..SINC Filter CH3 sync Break input is selected
38988  *  0b111000..SINC Filter CH4 sync Break input is selected
38989  *  0b111001..GPIO2 Pin Event Trig 0 input is selected
38990  *  0b111010..GPIO2 Pin Event Trig 1 input is selected
38991  *  0b111011..GPIO3 Pin Event Trig 0 input is selected
38992  *  0b111100..GPIO3 Pin Event Trig 1 input is selected
38993  *  *..
38994  */
38995 #define INPUTMUX_FLEXPWM_SM1_EXTA_ARRAY_FLEXPWM1_SM_EXTA_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM_SM1_EXTA_ARRAY_FLEXPWM1_SM_EXTA_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM_SM1_EXTA_ARRAY_FLEXPWM1_SM_EXTA_TRIGIN_MASK)
38996 /*! @} */
38997 
38998 /* The count of INPUTMUX_FLEXPWM_SM1_EXTA_ARRAY_FLEXPWM1_SM_EXTA */
38999 #define INPUTMUX_FLEXPWM_SM1_EXTA_ARRAY_FLEXPWM1_SM_EXTA_COUNT (4U)
39000 
39001 /*! @name FLEXPWM1_EXTFORCE - PWM1 External Force Trigger Connections */
39002 /*! @{ */
39003 
39004 #define INPUTMUX_FLEXPWM1_EXTFORCE_TRIGIN_MASK   (0x3FU)
39005 #define INPUTMUX_FLEXPWM1_EXTFORCE_TRIGIN_SHIFT  (0U)
39006 /*! TRIGIN - EXTFORCE input connections for PWM1
39007  *  0b000000..PINT PIN_INT0 input is selected
39008  *  0b000001..PINT PIN_INT2 input is selected
39009  *  0b000010..SCT_OUT4 input is selected
39010  *  0b000011..SCT_OUT5 input is selected
39011  *  0b000100..SCT_OUT3 input is selected
39012  *  0b000101..CTIMER0_MAT3 input is selected
39013  *  0b000110..CTIMER1_MAT3 input is selected
39014  *  0b000111..CTIMER2_MAT3 input is selected
39015  *  0b001000..CTIMER2_MAT1 input is selected
39016  *  0b001001..CTIMER4_MAT1 input is selected
39017  *  0b001010..Reserved
39018  *  0b001011..ARM_TXEV input is selected
39019  *  0b001100..PINT GPIO_INT_BMAT input is selected
39020  *  0b001101..ADC0_tcomp[0] input is selected
39021  *  0b001110..ADC0_tcomp[1] input is selected
39022  *  0b001111..ADC0_tcomp[2] input is selected
39023  *  0b010000..ADC0_tcomp[3] input is selected
39024  *  0b010001..ADC1_tcomp[0] input is selected
39025  *  0b010010..ADC1_tcomp[1] input is selected
39026  *  0b010011..ADC1_tcomp[2] input is selected
39027  *  0b010100..ADC1_tcomp[3] input is selected
39028  *  0b010101..CMP0_OUT input is selected
39029  *  0b010110..CMP1_OUT input is selected
39030  *  0b010111..CMP2_OUT input is selected
39031  *  0b011000..PWM0_SM0_MUX_TRIG0 input is selected
39032  *  0b011001..PWM0_SM0_MUX_TRIG1 input is selected
39033  *  0b011010..PWM0_SM1_MUX_TRIG0 input is selected
39034  *  0b011011..PWM0_SM1_MUX_TRIG1 input is selected
39035  *  0b011100..PWM0_SM2_MUX_TRIG0 input is selected
39036  *  0b011101..PWM0_SM2_MUX_TRIG1 input is selected
39037  *  0b011110..PWM0_SM3_MUX_TRIG0 input is selected
39038  *  0b011111..PWM0_SM3_MUX_TRIG1 input is selected
39039  *  0b100000..QDC0_CMP/POS_MATCH input is selected
39040  *  0b100001..QDC1_CMP/POS_MATCH input is selected
39041  *  0b100010..EVTG_OUT0A input is selected
39042  *  0b100011..EVTG_OUT0B input is selected
39043  *  0b100100..EVTG_OUT1A input is selected
39044  *  0b100101..EVTG_OUT1B input is selected
39045  *  0b100110..EVTG_OUT2A input is selected
39046  *  0b100111..EVTG_OUT2B input is selected
39047  *  0b101000..EVTG_OUT3A input is selected
39048  *  0b101001..EVTG_OUT3B input is selected
39049  *  0b101010..TRIG_IN0 input is selected
39050  *  0b101011..TRIG_IN1 input is selected
39051  *  0b101100..TRIG_IN2 input is selected
39052  *  0b101101..TRIG_IN3 input is selected
39053  *  0b101110..TRIG_IN4 input is selected
39054  *  0b101111..TRIG_IN5 input is selected
39055  *  0b110000..TRIG_IN6 input is selected
39056  *  0b110001..TRIG_IN7 input is selected
39057  *  0b110010..TRIG_IN8 input is selected
39058  *  0b110011..TRIG_IN9 input is selected
39059  *  0b110100..SINC Filter CH0 sync Break input is selected
39060  *  0b110101..SINC Filter CH1 sync Break input is selected
39061  *  0b110110..SINC Filter CH2 sync Break input is selected
39062  *  0b110111..SINC Filter CH3 sync Break input is selected
39063  *  0b111000..SINC Filter CH4 sync Break input is selected
39064  *  0b111001..GPIO2 Pin Event Trig 0 input is selected
39065  *  0b111010..GPIO2 Pin Event Trig 1 input is selected
39066  *  0b111011..GPIO3 Pin Event Trig 0 input is selected
39067  *  0b111100..GPIO3 Pin Event Trig 1 input is selected
39068  *  *..
39069  */
39070 #define INPUTMUX_FLEXPWM1_EXTFORCE_TRIGIN(x)     (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM1_EXTFORCE_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM1_EXTFORCE_TRIGIN_MASK)
39071 /*! @} */
39072 
39073 /*! @name FLEXPWM1_FAULT - PWM1 Fault Input Trigger Connections */
39074 /*! @{ */
39075 
39076 #define INPUTMUX_FLEXPWM1_FAULT_TRIGIN_MASK      (0x3FU)
39077 #define INPUTMUX_FLEXPWM1_FAULT_TRIGIN_SHIFT     (0U)
39078 /*! TRIGIN - FAULT input connections for PWM1
39079  *  0b000000..PINT PIN_INT0 input is selected
39080  *  0b000001..PINT PIN_INT2 input is selected
39081  *  0b000010..SCT_OUT4 input is selected
39082  *  0b000011..SCT_OUT5 input is selected
39083  *  0b000100..SCT_OUT3 input is selected
39084  *  0b000101..CTIMER0_MAT3 input is selected
39085  *  0b000110..CTIMER1_MAT3 input is selected
39086  *  0b000111..CTIMER2_MAT3 input is selected
39087  *  0b001000..CTIMER2_MAT1 input is selected
39088  *  0b001001..CTIMER4_MAT1 input is selected
39089  *  0b001010..Reserved
39090  *  0b001011..ARM_TXEV input is selected
39091  *  0b001100..PINT GPIO_INT_BMAT input is selected
39092  *  0b001101..ADC0_tcomp[0] input is selected
39093  *  0b001110..ADC0_tcomp[1] input is selected
39094  *  0b001111..ADC0_tcomp[2] input is selected
39095  *  0b010000..ADC0_tcomp[3] input is selected
39096  *  0b010001..ADC1_tcomp[0] input is selected
39097  *  0b010010..ADC1_tcomp[1] input is selected
39098  *  0b010011..ADC1_tcomp[2] input is selected
39099  *  0b010100..ADC1_tcomp[3] input is selected
39100  *  0b010101..CMP0_OUT input is selected
39101  *  0b010110..CMP1_OUT input is selected
39102  *  0b010111..CMP2_OUT input is selected
39103  *  0b011000..PWM0_SM0_MUX_TRIG0 input is selected
39104  *  0b011001..PWM0_SM0_MUX_TRIG1 input is selected
39105  *  0b011010..PWM0_SM1_MUX_TRIG0 input is selected
39106  *  0b011011..PWM0_SM1_MUX_TRIG1 input is selected
39107  *  0b011100..PWM0_SM2_MUX_TRIG0 input is selected
39108  *  0b011101..PWM0_SM2_MUX_TRIG1 input is selected
39109  *  0b011110..PWM0_SM3_MUX_TRIG0 input is selected
39110  *  0b011111..PWM0_SM3_MUX_TRIG1 input is selected
39111  *  0b100000..QDC0_CMP/POS_MATCH input is selected
39112  *  0b100001..QDC1_CMP/POS_MATCH input is selected
39113  *  0b100010..EVTG_OUT0A input is selected
39114  *  0b100011..EVTG_OUT0B input is selected
39115  *  0b100100..EVTG_OUT1A input is selected
39116  *  0b100101..EVTG_OUT1B input is selected
39117  *  0b100110..EVTG_OUT2A input is selected
39118  *  0b100111..EVTG_OUT2B input is selected
39119  *  0b101000..EVTG_OUT3A input is selected
39120  *  0b101001..EVTG_OUT3B input is selected
39121  *  0b101010..TRIG_IN0 input is selected
39122  *  0b101011..TRIG_IN1 input is selected
39123  *  0b101100..TRIG_IN2 input is selected
39124  *  0b101101..TRIG_IN3 input is selected
39125  *  0b101110..TRIG_IN4 input is selected
39126  *  0b101111..TRIG_IN5 input is selected
39127  *  0b110000..TRIG_IN6 input is selected
39128  *  0b110001..TRIG_IN7 input is selected
39129  *  0b110010..TRIG_IN8 input is selected
39130  *  0b110011..TRIG_IN9 input is selected
39131  *  0b110100..SINC Filter CH0 sync Break input is selected
39132  *  0b110101..SINC Filter CH1 sync Break input is selected
39133  *  0b110110..SINC Filter CH2 sync Break input is selected
39134  *  0b110111..SINC Filter CH3 sync Break input is selected
39135  *  0b111000..SINC Filter CH4 sync Break input is selected
39136  *  0b111001..GPIO2 Pin Event Trig 0 input is selected
39137  *  0b111010..GPIO2 Pin Event Trig 1 input is selected
39138  *  0b111011..GPIO3 Pin Event Trig 0 input is selected
39139  *  0b111100..GPIO3 Pin Event Trig 1 input is selected
39140  *  *..
39141  */
39142 #define INPUTMUX_FLEXPWM1_FAULT_TRIGIN(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM1_FAULT_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM1_FAULT_TRIGIN_MASK)
39143 /*! @} */
39144 
39145 /* The count of INPUTMUX_FLEXPWM1_FAULT */
39146 #define INPUTMUX_FLEXPWM1_FAULT_COUNT            (4U)
39147 
39148 /*! @name PWM0_EXT_CLK - PWM0 External Clock Trigger */
39149 /*! @{ */
39150 
39151 #define INPUTMUX_PWM0_EXT_CLK_TRIGIN_MASK        (0x7U)
39152 #define INPUTMUX_PWM0_EXT_CLK_TRIGIN_SHIFT       (0U)
39153 /*! TRIGIN - EXT_CLK input connections for PWM0
39154  *  0b000..FRO16K input is selected
39155  *  0b001..OSC_32k input is selected
39156  *  0b010..EVTG_OUT0A input is selected
39157  *  0b011..EVTG_OUT1A input is selected
39158  *  0b100..TRIG_IN0 input is selected
39159  *  0b101..TRIG_IN7 input is selected
39160  *  *..
39161  */
39162 #define INPUTMUX_PWM0_EXT_CLK_TRIGIN(x)          (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PWM0_EXT_CLK_TRIGIN_SHIFT)) & INPUTMUX_PWM0_EXT_CLK_TRIGIN_MASK)
39163 /*! @} */
39164 
39165 /*! @name PWM1_EXT_CLK - PWM1 External Clock Trigger */
39166 /*! @{ */
39167 
39168 #define INPUTMUX_PWM1_EXT_CLK_TRIGIN_MASK        (0xFU)
39169 #define INPUTMUX_PWM1_EXT_CLK_TRIGIN_SHIFT       (0U)
39170 /*! TRIGIN - EXT_CLK input connections for PWM1
39171  *  0b0000..FRO16K input is selected
39172  *  0b0001..OSC_32k input is selected
39173  *  0b0010..EVTG_OUT0A input is selected
39174  *  0b0011..EVTG_OUT1A input is selected
39175  *  0b0100..TRIG_IN0 input is selected
39176  *  0b0101..TRIG_IN7 input is selected
39177  *  *..
39178  */
39179 #define INPUTMUX_PWM1_EXT_CLK_TRIGIN(x)          (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PWM1_EXT_CLK_TRIGIN_SHIFT)) & INPUTMUX_PWM1_EXT_CLK_TRIGIN_MASK)
39180 /*! @} */
39181 
39182 /*! @name EVTG_TRIGN_EVTG_TRIG - EVTG Trigger Input Connections */
39183 /*! @{ */
39184 
39185 #define INPUTMUX_EVTG_TRIGN_EVTG_TRIG_INP_MASK   (0x3FU)
39186 #define INPUTMUX_EVTG_TRIGN_EVTG_TRIG_INP_SHIFT  (0U)
39187 /*! INP - EVTG trigger input connections
39188  *  0b000000..PINT PIN_INT0 input is selected
39189  *  0b000001..PINT PIN_INT1 input is selected
39190  *  0b000010..SCT_OUT0 input is selected
39191  *  0b000011..SCT_OUT1 input is selected
39192  *  0b000100..SCT_OUT2 input is selected
39193  *  0b000101..SCT_OUT3 input is selected
39194  *  0b000110..CTIMER0_MAT3 input is selected
39195  *  0b000111..CTIMER1_MAT3 input is selected
39196  *  0b001000..CTIMER2_MAT3 input is selected
39197  *  0b001001..CTIMER2_MAT2 input is selected
39198  *  0b001010..CTIMER3_MAT2 input is selected
39199  *  0b001011..CTIMER4_MAT2 input is selected
39200  *  0b001100..Reserved
39201  *  0b001101..PINT GPIO_INT_BMAT input is selected
39202  *  0b001110..ADC0_IRQ input is selected
39203  *  0b001111..ADC1_IRQ input is selected
39204  *  0b010000..ADC0_tcomp[0] input is selected
39205  *  0b010001..ADC0_tcomp[1] input is selected
39206  *  0b010010..ADC0_tcomp[2] input is selected
39207  *  0b010011..ADC0_tcomp[3] input is selected
39208  *  0b010100..ADC1_tcomp[0] input is selected
39209  *  0b010101..ADC1_tcomp[1] input is selected
39210  *  0b010110..ADC1_tcomp[2] input is selected
39211  *  0b010111..ADC1_tcomp[3] input is selected
39212  *  0b011000..CMP0_OUT input is selected
39213  *  0b011001..CMP1_OUT input is selected
39214  *  0b011010..CMP2_OUT input is selected
39215  *  0b011011..PWM0_SM0_MUX_TRIG0 input is selected
39216  *  0b011100..PWM0_SM0_MUX_TRIG1 input is selected
39217  *  0b011101..PWM0_SM1_MUX_TRIG0 input is selected
39218  *  0b011110..PWM0_SM1_MUX_TRIG1 input is selected
39219  *  0b011111..PWM0_SM2_MUX_TRIG0 input is selected
39220  *  0b100000..PWM0_SM2_MUX_TRIG1 input is selected
39221  *  0b100001..PWM0_SM3_MUX_TRIG0 input is selected
39222  *  0b100010..PWM0_SM3_MUX_TRIG1 input is selected
39223  *  0b100011..PWM1_SM0_MUX_TRIG0 input is selected
39224  *  0b100100..PWM1_SM0_MUX_TRIG1 input is selected
39225  *  0b100101..PWM1_SM1_MUX_TRIG0 input is selected
39226  *  0b100110..PWM1_SM1_MUX_TRIG1 input is selected
39227  *  0b100111..PWM1_SM2_MUX_TRIG0 input is selected
39228  *  0b101000..PWM1_SM2_MUX_TRIG1 input is selected
39229  *  0b101001..PWM1_SM3_MUX_TRIG0 input is selected
39230  *  0b101010..PWM1_SM3_MUX_TRIG1 input is selected
39231  *  0b101011..QDC0_CMP/POS_MATCH input is selected
39232  *  0b101100..QDC1_CMP/POS_MATCH input is selected
39233  *  0b101101..TRIG_IN0 input is selected
39234  *  0b101110..TRIG_IN1 input is selected
39235  *  0b101111..TRIG_IN2 input is selected
39236  *  0b110000..TRIG_IN3 input is selected
39237  *  0b110001..LPTMR0 input is selected
39238  *  0b110010..LPTMR1 input is selected
39239  *  0b110011..SINC Filter CH0 Break input is selected
39240  *  0b110100..SINC Filter CH1 Break input is selected
39241  *  0b110101..SINC Filter CH2 Break input is selected
39242  *  0b110110..SINC Filter CH3 Break input is selected
39243  *  0b110111..SINC Filter CH4 Break input is selected
39244  *  0b111000..Reserved
39245  *  0b111001..Reserved
39246  *  *..
39247  */
39248 #define INPUTMUX_EVTG_TRIGN_EVTG_TRIG_INP(x)     (((uint32_t)(((uint32_t)(x)) << INPUTMUX_EVTG_TRIGN_EVTG_TRIG_INP_SHIFT)) & INPUTMUX_EVTG_TRIGN_EVTG_TRIG_INP_MASK)
39249 /*! @} */
39250 
39251 /* The count of INPUTMUX_EVTG_TRIGN_EVTG_TRIG */
39252 #define INPUTMUX_EVTG_TRIGN_EVTG_TRIG_COUNT      (16U)
39253 
39254 /*! @name USBFS_TRIG - USB-FS Trigger Input Connections */
39255 /*! @{ */
39256 
39257 #define INPUTMUX_USBFS_TRIG_INP_MASK             (0xFU)
39258 #define INPUTMUX_USBFS_TRIG_INP_SHIFT            (0U)
39259 /*! INP - USB-FS trigger input connections. The trigger output of LP_FLEXCOMM is an input of peripheral INPUTMUX.
39260  *  0b0000..LP_FLEXCOMM 0 trigger out [3] input is selected
39261  *  0b0001..LP_FLEXCOMM 1 trigger out [3] input is selected
39262  *  0b0010..LP_FLEXCOMM 2 trigger out [3] input is selected
39263  *  0b0011..LP_FLEXCOMM 3 trigger out [3] input is selected
39264  *  0b0100..LP_FLEXCOMM 4 trigger out [3] input is selected
39265  *  0b0101..LP_FLEXCOMM 5 trigger out [3] input is selected
39266  *  0b0110..LP_FLEXCOMM 6 trigger out [3] input is selected
39267  *  0b0111..LP_FLEXCOMM 7 trigger out [3] input is selected
39268  *  0b1000..LP_FLEXCOMM 8 trigger out [3] input is selected
39269  *  0b1001..LP_FLEXCOMM 9 trigger out [3] input is selected
39270  *  *..
39271  */
39272 #define INPUTMUX_USBFS_TRIG_INP(x)               (((uint32_t)(((uint32_t)(x)) << INPUTMUX_USBFS_TRIG_INP_SHIFT)) & INPUTMUX_USBFS_TRIG_INP_MASK)
39273 /*! @} */
39274 
39275 /*! @name TSI_TRIG - TSI Trigger Input Connections */
39276 /*! @{ */
39277 
39278 #define INPUTMUX_TSI_TRIG_INP_MASK               (0x3U)
39279 #define INPUTMUX_TSI_TRIG_INP_SHIFT              (0U)
39280 /*! INP - TSI trigger input connections
39281  *  0b00..LPTMR0 input is selected
39282  *  0b01..LPTMR1 input is selected
39283  *  *..
39284  */
39285 #define INPUTMUX_TSI_TRIG_INP(x)                 (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TSI_TRIG_INP_SHIFT)) & INPUTMUX_TSI_TRIG_INP_MASK)
39286 /*! @} */
39287 
39288 /*! @name EXT_TRIGN_EXT_TRIG - EXT Trigger Connections */
39289 /*! @{ */
39290 
39291 #define INPUTMUX_EXT_TRIGN_EXT_TRIG_INP_MASK     (0x3FU)
39292 #define INPUTMUX_EXT_TRIGN_EXT_TRIG_INP_SHIFT    (0U)
39293 /*! INP - TRIG_OUTa pin input connections
39294  *  0b000000..PINT PIN_INT0 input is selected
39295  *  0b000001..PINT PIN_INT1 input is selected
39296  *  0b000010..ADC0_IRQ input is selected
39297  *  0b000011..ADC1_IRQ input is selected
39298  *  0b000100..ADC0_tcomp[0] input is selected
39299  *  0b000101..ADC1_tcomp[0] input is selected
39300  *  0b000110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected
39301  *  0b000111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected
39302  *  0b001000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected
39303  *  0b001001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected
39304  *  0b001010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected
39305  *  0b001011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected
39306  *  0b001100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected
39307  *  0b001101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected
39308  *  0b001110..QDC0_CMP/POS_MATCH input is selected
39309  *  0b001111..QDC1_CMP/POS_MATCH input is selected
39310  *  0b010000..EVTG_OUT0A input is selected
39311  *  0b010001..EVTG_OUT0B input is selected
39312  *  0b010010..EVTG_OUT1A input is selected
39313  *  0b010011..EVTG_OUT1B input is selected
39314  *  0b010100..EVTG_OUT2A input is selected
39315  *  0b010101..EVTG_OUT2B input is selected
39316  *  0b010110..EVTG_OUT3A input is selected
39317  *  0b010111..EVTG_OUT3B input is selected
39318  *  0b011000..Reserved
39319  *  0b011001..Reserved
39320  *  0b011010..LPTMR0 input is selected
39321  *  0b011011..LPTMR1 input is selected
39322  *  0b011100..SCT Out0 input is selected
39323  *  0b011101..SCT Out1 input is selected
39324  *  0b011110..SCT Out2 input is selected
39325  *  0b011111..SCT Out3 input is selected
39326  *  0b100000..SCT Out4 input is selected
39327  *  0b100001..SCT Out5 input is selected
39328  *  0b100010..LP_FLEXCOMM0 trigger output 3 input is selected
39329  *  0b100011..LP_FLEXCOMM1 trigger output 3 input is selected
39330  *  0b100100..LP_FLEXCOMM2 trigger output 3 input is selected
39331  *  0b100101..LP_FLEXCOMM3 trigger output 3 input is selected
39332  *  0b100110..LP_FLEXCOMM4 trigger output 3 input is selected
39333  *  0b100111..LP_FLEXCOMM5 trigger output 3 input is selected
39334  *  0b101000..LP_FLEXCOMM6 trigger output 3 input is selected
39335  *  0b101001..LP_FLEXCOMM7 trigger output 3 input is selected
39336  *  0b101010..LP_FLEXCOMM8 trigger output 3 input is selected
39337  *  0b101011..LP_FLEXCOMM9 trigger output 3 input is selected
39338  *  0b101100..CMP0_OUT input is selected
39339  *  0b101101..CMP1_OUT input is selected
39340  *  0b101110..CMP2_OUT input is selected
39341  *  0b101111..ENET_PPS_OUT_0 input is selected
39342  *  *..
39343  */
39344 #define INPUTMUX_EXT_TRIGN_EXT_TRIG_INP(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_EXT_TRIGN_EXT_TRIG_INP_SHIFT)) & INPUTMUX_EXT_TRIGN_EXT_TRIG_INP_MASK)
39345 /*! @} */
39346 
39347 /* The count of INPUTMUX_EXT_TRIGN_EXT_TRIG */
39348 #define INPUTMUX_EXT_TRIGN_EXT_TRIG_COUNT        (8U)
39349 
39350 /*! @name CMP1_TRIG - CMP1 Input Connections */
39351 /*! @{ */
39352 
39353 #define INPUTMUX_CMP1_TRIG_TRIGIN_MASK           (0x3FU)
39354 #define INPUTMUX_CMP1_TRIG_TRIGIN_SHIFT          (0U)
39355 /*! TRIGIN - CMP1 input trigger
39356  *  0b000000..PINT PIN_INT0 input is selected
39357  *  0b000001..PINT PIN_INT7 input is selected
39358  *  0b000010..SCT0 SCT_OUT4 input is selected
39359  *  0b000011..SCT0 SCT_OUT5 input is selected
39360  *  0b000100..SCT0 SCT_OUT7 input is selected
39361  *  0b000101..CTIMER0_MAT3 input is selected
39362  *  0b000110..CTIMER1_MAT3 input is selected
39363  *  0b000111..CTIMER2_MAT3 input is selected
39364  *  0b001000..CTIMER3_MAT1 input is selected
39365  *  0b001001..CTIMER4_MAT1 input is selected
39366  *  0b001010..Reserved
39367  *  0b001011..Reserved
39368  *  0b001100..PINT GPIO_INT_BMAT input is selected
39369  *  0b001101..ADC0_tcomp[1] input is selected
39370  *  0b001110..ADC1_tcomp[1] input is selected
39371  *  0b001111..Reserved
39372  *  0b010000..Reserved
39373  *  0b010001..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected
39374  *  0b010010..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected
39375  *  0b010011..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected
39376  *  0b010100..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected
39377  *  0b010101..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected
39378  *  0b010110..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected
39379  *  0b010111..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected
39380  *  0b011000..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected
39381  *  0b011001..QDC0_CMP/POS_MATCH input is selected
39382  *  0b011010..QDC1_CMP/POS_MATCH input is selected
39383  *  0b011011..EVTG_OUT0A input is selected
39384  *  0b011100..EVTG_OUT0B input is selected
39385  *  0b011101..EVTG_OUT1A input is selected
39386  *  0b011110..EVTG_OUT1B input is selected
39387  *  0b011111..EVTG_OUT2A input is selected
39388  *  0b100000..EVTG_OUT2B input is selected
39389  *  0b100001..EVTG_OUT3A input is selected
39390  *  0b100010..EVTG_OUT3B input is selected
39391  *  0b100011..LPTMR0 input is selected
39392  *  0b100100..LPTMR1 input is selected
39393  *  0b100101..GPIO2 Pin Event Trig 0 input is selected
39394  *  0b100110..GPIO2 Pin Event Trig 1 input is selected
39395  *  0b100111..GPIO3 Pin Event Trig 0 input is selected
39396  *  0b101000..GPIO3 Pin Event Trig 1 input is selected
39397  *  *..
39398  */
39399 #define INPUTMUX_CMP1_TRIG_TRIGIN(x)             (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CMP1_TRIG_TRIGIN_SHIFT)) & INPUTMUX_CMP1_TRIG_TRIGIN_MASK)
39400 /*! @} */
39401 
39402 /*! @name CMP2_TRIG - CMP2 Input Connections */
39403 /*! @{ */
39404 
39405 #define INPUTMUX_CMP2_TRIG_TRIGIN_MASK           (0x3FU)
39406 #define INPUTMUX_CMP2_TRIG_TRIGIN_SHIFT          (0U)
39407 /*! TRIGIN - CMP2 input trigger
39408  *  0b000000..PINT PIN_INT0 input is selected
39409  *  0b000001..PINT PIN_INT4 input is selected
39410  *  0b000010..SCT0 SCT_OUT4 input is selected
39411  *  0b000011..SCT0 SCT_OUT5 input is selected
39412  *  0b000100..SCT0 SCT_OUT8 input is selected
39413  *  0b000101..CTIMER0_MAT3 input is selected
39414  *  0b000110..CTIMER1_MAT3 input is selected
39415  *  0b000111..CTIMER2_MAT3 input is selected
39416  *  0b001000..CTIMER3_MAT2 input is selected
39417  *  0b001001..CTIMER4_MAT2 input is selected
39418  *  0b001010..Reserved
39419  *  0b001011..Reserved
39420  *  0b001100..PINT GPIO_INT_BMAT input is selected
39421  *  0b001101..ADC0_tcomp[2] input is selected
39422  *  0b001110..ADC1_tcomp[2] input is selected
39423  *  0b001111..Reserved
39424  *  0b010000..Reserved
39425  *  0b010001..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected
39426  *  0b010010..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected
39427  *  0b010011..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected
39428  *  0b010100..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected
39429  *  0b010101..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected
39430  *  0b010110..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected
39431  *  0b010111..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected
39432  *  0b011000..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected
39433  *  0b011001..QDC0_CMP/POS_MATCH input is selected
39434  *  0b011010..QDC1_CMP/POS_MATCH input is selected
39435  *  0b011011..EVTG_OUT0A input is selected
39436  *  0b011100..EVTG_OUT0B input is selected
39437  *  0b011101..EVTG_OUT1A input is selected
39438  *  0b011110..EVTG_OUT1B input is selected
39439  *  0b011111..EVTG_OUT2A input is selected
39440  *  0b100000..EVTG_OUT2B input is selected
39441  *  0b100001..EVTG_OUT3A input is selected
39442  *  0b100010..EVTG_OUT3B input is selected
39443  *  0b100011..LPTMR0 input is selected
39444  *  0b100100..LPTMR1 input is selected
39445  *  0b100101..GPIO2 Pin Event Trig 0 input is selected
39446  *  0b100110..GPIO2 Pin Event Trig 1 input is selected
39447  *  0b100111..GPIO3 Pin Event Trig 0 input is selected
39448  *  0b101000..GPIO3 Pin Event Trig 1 input is selected
39449  *  *..
39450  */
39451 #define INPUTMUX_CMP2_TRIG_TRIGIN(x)             (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CMP2_TRIG_TRIGIN_SHIFT)) & INPUTMUX_CMP2_TRIG_TRIGIN_MASK)
39452 /*! @} */
39453 
39454 /*! @name SINC_FILTER_CHN_SINC_FILTER_CH - SINC Filter Channel Trigger Input Connections */
39455 /*! @{ */
39456 
39457 #define INPUTMUX_SINC_FILTER_CHN_SINC_FILTER_CH_INP_MASK (0x3FU)
39458 #define INPUTMUX_SINC_FILTER_CHN_SINC_FILTER_CH_INP_SHIFT (0U)
39459 /*! INP - SINC FILTER trigger input connections
39460  *  0b000000..PINT PIN_INT0 input is selected
39461  *  0b000001..PINT PIN_INT1 input is selected
39462  *  0b000010..SCT_OUT4 input is selected
39463  *  0b000011..SCT_OUT5 input is selected
39464  *  0b000100..SCT_OUT9 input is selected
39465  *  0b000101..CTIMER0_MAT3 input is selected
39466  *  0b000110..CTIMER1_MAT3 input is selected
39467  *  0b000111..CTIMER2_MAT3 input is selected
39468  *  0b001000..CTIMER3_MAT3 input is selected
39469  *  0b001001..CTIMER4_MAT3 input is selected
39470  *  0b001010..Reserved
39471  *  0b001011..Reserved
39472  *  0b001100..PINT GPIO_INT_BMAT input is selected
39473  *  0b001101..ADC0_tcomp[0] input is selected
39474  *  0b001110..ADC0_tcomp[1] input is selected
39475  *  0b001111..ADC0_tcomp[2] input is selected
39476  *  0b010000..ADC0_tcomp[3] input is selected
39477  *  0b010001..ADC1_tcomp[0] input is selected
39478  *  0b010010..ADC1_tcomp[1] input is selected
39479  *  0b010011..ADC1_tcomp[2] input is selected
39480  *  0b010100..ADC1_tcomp[3] input is selected
39481  *  0b010101..CMP0_OUT input is selected
39482  *  0b010110..CMP1_OUT input is selected
39483  *  0b010111..CMP2_OUT input is selected
39484  *  0b011000..PWM0_SM0_MUX_TRIG0 input is selected
39485  *  0b011001..PWM0_SM0_MUX_TRIG1 input is selected
39486  *  0b011010..PWM0_SM1_MUX_TRIG0 input is selected
39487  *  0b011011..PWM0_SM1_MUX_TRIG1 input is selected
39488  *  0b011100..PWM0_SM2_MUX_TRIG0 input is selected
39489  *  0b011101..PWM0_SM2_MUX_TRIG1 input is selected
39490  *  0b011110..PWM0_SM3_MUX_TRIG0 input is selected
39491  *  0b011111..PWM0_SM3_MUX_TRIG1 input is selected
39492  *  0b100000..PWM1_SM0_MUX_TRIG0 input is selected
39493  *  0b100001..PWM1_SM0_MUX_TRIG1 input is selected
39494  *  0b100010..PWM1_SM1_MUX_TRIG0 input is selected
39495  *  0b100011..PWM1_SM1_MUX_TRIG1 input is selected
39496  *  0b100100..PWM1_SM2_MUX_TRIG0 input is selected
39497  *  0b100101..PWM1_SM2_MUX_TRIG1 input is selected
39498  *  0b100110..PWM1_SM3_MUX_TRIG0 input is selected
39499  *  0b100111..PWM1_SM3_MUX_TRIG1 input is selected
39500  *  0b101000..QDC0_CMP/POS_MATCH input is selected
39501  *  0b101001..QDC1_CMP/POS_MATCH input is selected
39502  *  0b101010..EVTG_OUT0A input is selected
39503  *  0b101011..EVTG_OUT0B input is selected
39504  *  0b101100..EVTG_OUT1A input is selected
39505  *  0b101101..EVTG_OUT1B input is selected
39506  *  0b101110..EVTG_OUT2A input is selected
39507  *  0b101111..EVTG_OUT2B input is selected
39508  *  0b110000..EVTG_OUT3A input is selected
39509  *  0b110001..EVTG_OUT3B input is selected
39510  *  0b110010..LPTMR0 input is selected
39511  *  0b110011..LPTMR1 input is selected
39512  *  0b110100..FlexIO CH0 input is selected
39513  *  0b110101..FlexIO CH1 input is selected
39514  *  0b110110..FlexIO CH2 input is selected
39515  *  0b110111..FlexIO CH3 input is selected
39516  *  0b111000..WUU input is selected
39517  *  *..
39518  */
39519 #define INPUTMUX_SINC_FILTER_CHN_SINC_FILTER_CH_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_SINC_FILTER_CHN_SINC_FILTER_CH_INP_SHIFT)) & INPUTMUX_SINC_FILTER_CHN_SINC_FILTER_CH_INP_MASK)
39520 /*! @} */
39521 
39522 /* The count of INPUTMUX_SINC_FILTER_CHN_SINC_FILTER_CH */
39523 #define INPUTMUX_SINC_FILTER_CHN_SINC_FILTER_CH_COUNT (5U)
39524 
39525 /*! @name OPAMPN_TRIG_OPAMP_TRIG - OPAMP Trigger Input Connections */
39526 /*! @{ */
39527 
39528 #define INPUTMUX_OPAMPN_TRIG_OPAMP_TRIG_INP_MASK (0x3FU)
39529 #define INPUTMUX_OPAMPN_TRIG_OPAMP_TRIG_INP_SHIFT (0U)
39530 /*! INP - OPAMP trigger input connections
39531  *  0b000000..PINT PIN_INT0 input is selected
39532  *  0b000001..PINT PIN_INT1 input is selected
39533  *  0b000010..PINT PIN_INT2 input is selected
39534  *  0b000011..PINT PIN_INT3 input is selected
39535  *  0b000100..SCT_OUT4 input is selected
39536  *  0b000101..SCT_OUT5 input is selected
39537  *  0b000110..SCT_OUT6 input is selected
39538  *  0b000111..SCT_OUT7 input is selected
39539  *  0b001000..SCT_OUT8 input is selected
39540  *  0b001001..CTIMER0_MAT3 input is selected
39541  *  0b001010..CTIMER1_MAT3 input is selected
39542  *  0b001011..CTIMER2_MAT3 input is selected
39543  *  0b001100..CTIMER3_MAT3 input is selected
39544  *  0b001101..CTIMER4_MAT3 input is selected
39545  *  0b001110..PINT GPIO_INT_BMAT input is selected
39546  *  0b001111..ADC0_tcomp[0] input is selected
39547  *  0b010000..ADC0_tcomp[1] input is selected
39548  *  0b010001..ADC0_tcomp[2] input is selected
39549  *  0b010010..ADC0_tcomp[3] input is selected
39550  *  0b010011..ADC1_tcomp[0] input is selected
39551  *  0b010100..ADC1_tcomp[1] input is selected
39552  *  0b010101..ADC1_tcomp[2] input is selected
39553  *  0b010110..ADC1_tcomp[3] input is selected
39554  *  0b010111..PWM0_SM0_MUX_TRIG0 input is selected
39555  *  0b011000..PWM0_SM0_MUX_TRIG1 input is selected
39556  *  0b011001..PWM0_SM1_MUX_TRIG0 input is selected
39557  *  0b011010..PWM0_SM1_MUX_TRIG1 input is selected
39558  *  0b011011..PWM0_SM2_MUX_TRIG0 input is selected
39559  *  0b011100..PWM0_SM2_MUX_TRIG1 input is selected
39560  *  0b011101..PWM0_SM3_MUX_TRIG0 input is selected
39561  *  0b011110..PWM0_SM3_MUX_TRIG1 input is selected
39562  *  0b011111..PWM1_SM0_MUX_TRIG0 input is selected
39563  *  0b100000..PWM1_SM0_MUX_TRIG1 input is selected
39564  *  0b100001..PWM1_SM1_MUX_TRIG0 input is selected
39565  *  0b100010..PWM1_SM1_MUX_TRIG1 input is selected
39566  *  0b100011..PWM1_SM2_MUX_TRIG0 input is selected
39567  *  0b100100..PWM1_SM2_MUX_TRIG1 input is selected
39568  *  0b100101..PWM1_SM3_MUX_TRIG0 input is selected
39569  *  0b100110..PWM1_SM3_MUX_TRIG1 input is selected
39570  *  0b100111..EVTG_OUT0A input is selected
39571  *  0b101000..EVTG_OUT0B input is selected
39572  *  0b101001..EVTG_OUT1A input is selected
39573  *  0b101010..EVTG_OUT1B input is selected
39574  *  0b101011..EVTG_OUT2A input is selected
39575  *  0b101100..EVTG_OUT2B input is selected
39576  *  0b101101..EVTG_OUT3A input is selected
39577  *  0b101110..EVTG_OUT3B input is selected
39578  *  0b101111..TRIG_IN0 input is selected
39579  *  0b110000..TRIG_IN1 input is selected
39580  *  0b110001..TRIG_IN2 input is selected
39581  *  0b110010..TRIG_IN3 input is selected
39582  *  0b110011..FlexIO CH4 input is selected
39583  *  0b110100..FlexIO CH5 input is selected
39584  *  0b110101..FlexIO CH6 input is selected
39585  *  0b110110..FlexIO CH7 input is selected
39586  *  *..
39587  */
39588 #define INPUTMUX_OPAMPN_TRIG_OPAMP_TRIG_INP(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_OPAMPN_TRIG_OPAMP_TRIG_INP_SHIFT)) & INPUTMUX_OPAMPN_TRIG_OPAMP_TRIG_INP_MASK)
39589 /*! @} */
39590 
39591 /* The count of INPUTMUX_OPAMPN_TRIG_OPAMP_TRIG */
39592 #define INPUTMUX_OPAMPN_TRIG_OPAMP_TRIG_COUNT    (3U)
39593 
39594 /*! @name FLEXCOMM0_TRIG - LP_FLEXCOMM0 Trigger Input Connections */
39595 /*! @{ */
39596 
39597 #define INPUTMUX_FLEXCOMM0_TRIG_INP_MASK         (0x3FU)
39598 #define INPUTMUX_FLEXCOMM0_TRIG_INP_SHIFT        (0U)
39599 /*! INP - LP_FLEXCOMM0 trigger input connections
39600  *  0b000000..PINT PIN_INT4 input is selected
39601  *  0b000001..PINT PIN_INT5 input is selected
39602  *  0b000010..PINT PIN_INT6 input is selected
39603  *  0b000011..SCT_OUT5 input is selected
39604  *  0b000100..SCT_OUT6 input is selected
39605  *  0b000101..SCT_OUT7 input is selected
39606  *  0b000110..CTIMER0_MAT1 input is selected
39607  *  0b000111..CTIMER1_MAT1 input is selected
39608  *  0b001000..CTIMER2_MAT0 input is selected
39609  *  0b001001..CTIMER3_MAT0 input is selected
39610  *  0b001010..CTIMER4_MAT0 input is selected
39611  *  0b001011..LPTMR0 input is selected
39612  *  0b001100..LPTMR1 input is selected
39613  *  0b001101..Reserved
39614  *  0b001110..PINT GPIO_INT_BMAT input is selected
39615  *  0b001111..CMP0_OUT input is selected
39616  *  0b010000..CMP1_OUT input is selected
39617  *  0b010001..CMP2_OUT input is selected
39618  *  0b010010..EVTG_OUT0A input is selected
39619  *  0b010011..EVTG_OUT0B input is selected
39620  *  0b010100..EVTG_OUT1A input is selected
39621  *  0b010101..EVTG_OUT1B input is selected
39622  *  0b010110..EVTG_OUT2A input is selected
39623  *  0b010111..EVTG_OUT2B input is selected
39624  *  0b011000..EVTG_OUT3A input is selected
39625  *  0b011001..EVTG_OUT3B input is selected
39626  *  0b011010..TRIG_IN0 input is selected
39627  *  0b011011..TRIG_IN1 input is selected
39628  *  0b011100..TRIG_IN2 input is selected
39629  *  0b011101..TRIG_IN3 input is selected
39630  *  0b011110..TRIG_IN4 input is selected
39631  *  0b011111..TRIG_IN10 input is selected
39632  *  0b100000..TRIG_IN11 input is selected
39633  *  0b100001..FlexIO CH4 input is selected
39634  *  0b100010..FlexIO CH5 input is selected
39635  *  0b100011..FlexIO CH6 input is selected
39636  *  0b100100..FlexIO CH7 input is selected
39637  *  0b100101..USB0 ipp_ind_uart_rxd_usbmux input is selected
39638  *  0b100110..GPIO2 Pin Event Trig 0 input is selected
39639  *  0b100111..GPIO2 Pin Event Trig 1 input is selected
39640  *  0b101000..GPIO3 Pin Event Trig 0 input is selected
39641  *  0b101001..GPIO3 Pin Event Trig 1 input is selected
39642  *  0b101010..WUU input is selected
39643  *  *..
39644  */
39645 #define INPUTMUX_FLEXCOMM0_TRIG_INP(x)           (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXCOMM0_TRIG_INP_SHIFT)) & INPUTMUX_FLEXCOMM0_TRIG_INP_MASK)
39646 /*! @} */
39647 
39648 /*! @name FLEXCOMM1_TRIG - LP_FLEXCOMM1 Trigger Input Connections */
39649 /*! @{ */
39650 
39651 #define INPUTMUX_FLEXCOMM1_TRIG_INP_MASK         (0x3FU)
39652 #define INPUTMUX_FLEXCOMM1_TRIG_INP_SHIFT        (0U)
39653 /*! INP - LP_FLEXCOMM1 trigger input connections
39654  *  0b000000..PINT PIN_INT4 input is selected
39655  *  0b000001..PINT PIN_INT5 input is selected
39656  *  0b000010..PINT PIN_INT6 input is selected
39657  *  0b000011..SCT_OUT5 input is selected
39658  *  0b000100..SCT_OUT6 input is selected
39659  *  0b000101..SCT_OUT7 input is selected
39660  *  0b000110..CTIMER0_MAT1 input is selected
39661  *  0b000111..CTIMER1_MAT1 input is selected
39662  *  0b001000..CTIMER2_MAT0 input is selected
39663  *  0b001001..CTIMER3_MAT0 input is selected
39664  *  0b001010..CTIMER4_MAT0 input is selected
39665  *  0b001011..LPTMR0 input is selected
39666  *  0b001100..LPTMR1 input is selected
39667  *  0b001101..Reserved
39668  *  0b001110..PINT GPIO_INT_BMAT input is selected
39669  *  0b001111..CMP0_OUT input is selected
39670  *  0b010000..CMP1_OUT input is selected
39671  *  0b010001..CMP2_OUT input is selected
39672  *  0b010010..EVTG_OUT0A input is selected
39673  *  0b010011..EVTG_OUT0B input is selected
39674  *  0b010100..EVTG_OUT1A input is selected
39675  *  0b010101..EVTG_OUT1B input is selected
39676  *  0b010110..EVTG_OUT2A input is selected
39677  *  0b010111..EVTG_OUT2B input is selected
39678  *  0b011000..EVTG_OUT3A input is selected
39679  *  0b011001..EVTG_OUT3B input is selected
39680  *  0b011010..TRIG_IN0 input is selected
39681  *  0b011011..TRIG_IN1 input is selected
39682  *  0b011100..TRIG_IN2 input is selected
39683  *  0b011101..TRIG_IN3 input is selected
39684  *  0b011110..TRIG_IN4 input is selected
39685  *  0b011111..TRIG_IN10 input is selected
39686  *  0b100000..TRIG_IN11 input is selected
39687  *  0b100001..FlexIO CH4 input is selected
39688  *  0b100010..FlexIO CH5 input is selected
39689  *  0b100011..FlexIO CH6 input is selected
39690  *  0b100100..FlexIO CH7 input is selected
39691  *  0b100101..USB0 ipp_ind_uart_rxd_usbmux input is selected
39692  *  0b100110..GPIO2 Pin Event Trig 0 input is selected
39693  *  0b100111..GPIO2 Pin Event Trig 1 input is selected
39694  *  0b101000..GPIO3 Pin Event Trig 0 input is selected
39695  *  0b101001..GPIO3 Pin Event Trig 1 input is selected
39696  *  0b101010..WUU input is selected
39697  *  *..
39698  */
39699 #define INPUTMUX_FLEXCOMM1_TRIG_INP(x)           (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXCOMM1_TRIG_INP_SHIFT)) & INPUTMUX_FLEXCOMM1_TRIG_INP_MASK)
39700 /*! @} */
39701 
39702 /*! @name FLEXCOMM2_TRIG - LP_FLEXCOMM2 Trigger Input Connections */
39703 /*! @{ */
39704 
39705 #define INPUTMUX_FLEXCOMM2_TRIG_INP_MASK         (0x3FU)
39706 #define INPUTMUX_FLEXCOMM2_TRIG_INP_SHIFT        (0U)
39707 /*! INP - LP_FLEXCOMM2 trigger input connections
39708  *  0b000000..PINT PIN_INT4 input is selected
39709  *  0b000001..PINT PIN_INT6 input is selected
39710  *  0b000010..PINT PIN_INT7 input is selected
39711  *  0b000011..SCT_OUT5 input is selected
39712  *  0b000100..SCT_OUT8 input is selected
39713  *  0b000101..SCT_OUT9 input is selected
39714  *  0b000110..CTIMER0_MAT1 input is selected
39715  *  0b000111..CTIMER1_MAT1 input is selected
39716  *  0b001000..CTIMER2_MAT1 input is selected
39717  *  0b001001..CTIMER3_MAT1 input is selected
39718  *  0b001010..CTIMER4_MAT1 input is selected
39719  *  0b001011..LPTMR0 input is selected
39720  *  0b001100..LPTMR1 input is selected
39721  *  0b001101..Reserved
39722  *  0b001110..PINT GPIO_INT_BMAT input is selected
39723  *  0b001111..CMP0_OUT input is selected
39724  *  0b010000..CMP1_OUT input is selected
39725  *  0b010001..CMP2_OUT input is selected
39726  *  0b010010..EVTG_OUT0A input is selected
39727  *  0b010011..EVTG_OUT0B input is selected
39728  *  0b010100..EVTG_OUT1A input is selected
39729  *  0b010101..EVTG_OUT1B input is selected
39730  *  0b010110..EVTG_OUT2A input is selected
39731  *  0b010111..EVTG_OUT2B input is selected
39732  *  0b011000..EVTG_OUT3A input is selected
39733  *  0b011001..EVTG_OUT3B input is selected
39734  *  0b011010..TRIG_IN0 input is selected
39735  *  0b011011..TRIG_IN1 input is selected
39736  *  0b011100..TRIG_IN2 input is selected
39737  *  0b011101..TRIG_IN3 input is selected
39738  *  0b011110..TRIG_IN4 input is selected
39739  *  0b011111..TRIG_IN10 input is selected
39740  *  0b100000..TRIG_IN11 input is selected
39741  *  0b100001..FlexIO CH4 input is selected
39742  *  0b100010..FlexIO CH5 input is selected
39743  *  0b100011..FlexIO CH6 input is selected
39744  *  0b100100..FlexIO CH7 input is selected
39745  *  0b100101..USB0 ipp_ind_uart_rxd_usbmux input is selected
39746  *  0b100110..GPIO2 Pin Event Trig 0 input is selected
39747  *  0b100111..GPIO2 Pin Event Trig 1 input is selected
39748  *  0b101000..GPIO3 Pin Event Trig 0 input is selected
39749  *  0b101001..GPIO3 Pin Event Trig 1 input is selected
39750  *  0b101010..WUU input is selected
39751  *  *..
39752  */
39753 #define INPUTMUX_FLEXCOMM2_TRIG_INP(x)           (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXCOMM2_TRIG_INP_SHIFT)) & INPUTMUX_FLEXCOMM2_TRIG_INP_MASK)
39754 /*! @} */
39755 
39756 /*! @name FLEXCOMM3_TRIG - LP_FLEXCOMM3 Trigger Input Connections */
39757 /*! @{ */
39758 
39759 #define INPUTMUX_FLEXCOMM3_TRIG_INP_MASK         (0x3FU)
39760 #define INPUTMUX_FLEXCOMM3_TRIG_INP_SHIFT        (0U)
39761 /*! INP - LP_FLEXCOMM3 trigger input connections
39762  *  0b000000..PINT PIN_INT4 input is selected
39763  *  0b000001..PINT PIN_INT5 input is selected
39764  *  0b000010..PINT PIN_INT7 input is selected
39765  *  0b000011..SCT_OUT5 input is selected
39766  *  0b000100..SCT_OUT8 input is selected
39767  *  0b000101..SCT_OUT9 input is selected
39768  *  0b000110..CTIMER0_MAT1 input is selected
39769  *  0b000111..CTIMER1_MAT1 input is selected
39770  *  0b001000..CTIMER2_MAT1 input is selected
39771  *  0b001001..CTIMER3_MAT1 input is selected
39772  *  0b001010..CTIMER4_MAT1 input is selected
39773  *  0b001011..LPTMR0 input is selected
39774  *  0b001100..LPTMR1 input is selected
39775  *  0b001101..Reserved
39776  *  0b001110..PINT GPIO_INT_BMAT input is selected
39777  *  0b001111..CMP0_OUT input is selected
39778  *  0b010000..CMP1_OUT input is selected
39779  *  0b010001..CMP2_OUT input is selected
39780  *  0b010010..EVTG_OUT0A input is selected
39781  *  0b010011..EVTG_OUT0B input is selected
39782  *  0b010100..EVTG_OUT1A input is selected
39783  *  0b010101..EVTG_OUT1B input is selected
39784  *  0b010110..EVTG_OUT2A input is selected
39785  *  0b010111..EVTG_OUT2B input is selected
39786  *  0b011000..EVTG_OUT3A input is selected
39787  *  0b011001..EVTG_OUT3B input is selected
39788  *  0b011010..TRIG_IN0 input is selected
39789  *  0b011011..TRIG_IN1 input is selected
39790  *  0b011100..TRIG_IN2 input is selected
39791  *  0b011101..TRIG_IN3 input is selected
39792  *  0b011110..TRIG_IN4 input is selected
39793  *  0b011111..TRIG_IN10 input is selected
39794  *  0b100000..TRIG_IN11 input is selected
39795  *  0b100001..FlexIO CH4 input is selected
39796  *  0b100010..FlexIO CH5 input is selected
39797  *  0b100011..FlexIO CH6 input is selected
39798  *  0b100100..FlexIO CH7 input is selected
39799  *  0b100101..USB0 ipp_ind_uart_rxd_usbmux input is selected
39800  *  0b100110..GPIO2 Pin Event Trig 0 input is selected
39801  *  0b100111..GPIO2 Pin Event Trig 1 input is selected
39802  *  0b101000..GPIO3 Pin Event Trig 0 input is selected
39803  *  0b101001..GPIO3 Pin Event Trig 1 input is selected
39804  *  0b101010..WUU input is selected
39805  *  *..
39806  */
39807 #define INPUTMUX_FLEXCOMM3_TRIG_INP(x)           (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXCOMM3_TRIG_INP_SHIFT)) & INPUTMUX_FLEXCOMM3_TRIG_INP_MASK)
39808 /*! @} */
39809 
39810 /*! @name FLEXCOMM4_TRIG - LP_FLEXCOMM4 Trigger Input Connections */
39811 /*! @{ */
39812 
39813 #define INPUTMUX_FLEXCOMM4_TRIG_INP_MASK         (0x3FU)
39814 #define INPUTMUX_FLEXCOMM4_TRIG_INP_SHIFT        (0U)
39815 /*! INP - LP_FLEXCOMM4 trigger input connections
39816  *  0b000000..PINT PIN_INT4 input is selected
39817  *  0b000001..PINT PIN_INT5 input is selected
39818  *  0b000010..PINT PIN_INT7 input is selected
39819  *  0b000011..SCT_OUT0 input is selected
39820  *  0b000100..SCT_OUT1 input is selected
39821  *  0b000101..SCT_OUT2 input is selected
39822  *  0b000110..CTIMER0_MAT1 input is selected
39823  *  0b000111..CTIMER1_MAT1 input is selected
39824  *  0b001000..CTIMER2_MAT2 input is selected
39825  *  0b001001..CTIMER3_MAT2 input is selected
39826  *  0b001010..CTIMER4_MAT2 input is selected
39827  *  0b001011..LPTMR0 input is selected
39828  *  0b001100..LPTMR1 input is selected
39829  *  0b001101..Reserved
39830  *  0b001110..PINT GPIO_INT_BMAT input is selected
39831  *  0b001111..CMP0_OUT input is selected
39832  *  0b010000..CMP1_OUT input is selected
39833  *  0b010001..CMP2_OUT input is selected
39834  *  0b010010..EVTG_OUT0A input is selected
39835  *  0b010011..EVTG_OUT0B input is selected
39836  *  0b010100..EVTG_OUT1A input is selected
39837  *  0b010101..EVTG_OUT1B input is selected
39838  *  0b010110..EVTG_OUT2A input is selected
39839  *  0b010111..EVTG_OUT2B input is selected
39840  *  0b011000..EVTG_OUT3A input is selected
39841  *  0b011001..EVTG_OUT3B input is selected
39842  *  0b011010..TRIG_IN0 input is selected
39843  *  0b011011..TRIG_IN1 input is selected
39844  *  0b011100..TRIG_IN2 input is selected
39845  *  0b011101..TRIG_IN3 input is selected
39846  *  0b011110..TRIG_IN4 input is selected
39847  *  0b011111..TRIG_IN10 input is selected
39848  *  0b100000..TRIG_IN11 input is selected
39849  *  0b100001..FlexIO CH4 input is selected
39850  *  0b100010..FlexIO CH5 input is selected
39851  *  0b100011..FlexIO CH6 input is selected
39852  *  0b100100..FlexIO CH7 input is selected
39853  *  0b100101..USB0 ipp_ind_uart_rxd_usbmux input is selected
39854  *  0b100110..GPIO2 Pin Event Trig 0 input is selected
39855  *  0b100111..GPIO2 Pin Event Trig 1 input is selected
39856  *  0b101000..GPIO3 Pin Event Trig 0 input is selected
39857  *  0b101001..GPIO3 Pin Event Trig 1 input is selected
39858  *  0b101010..WUU input is selected
39859  *  *..
39860  */
39861 #define INPUTMUX_FLEXCOMM4_TRIG_INP(x)           (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXCOMM4_TRIG_INP_SHIFT)) & INPUTMUX_FLEXCOMM4_TRIG_INP_MASK)
39862 /*! @} */
39863 
39864 /*! @name FLEXCOMM5_TRIG - LP_FLEXCOMM5 Trigger Input Connections */
39865 /*! @{ */
39866 
39867 #define INPUTMUX_FLEXCOMM5_TRIG_INP_MASK         (0x3FU)
39868 #define INPUTMUX_FLEXCOMM5_TRIG_INP_SHIFT        (0U)
39869 /*! INP - LP_FLEXCOMM5 trigger input connections
39870  *  0b000000..PINT PIN_INT4 input is selected
39871  *  0b000001..PINT PIN_INT5 input is selected
39872  *  0b000010..PINT PIN_INT7 input is selected
39873  *  0b000011..SCT_OUT0 input is selected
39874  *  0b000100..SCT_OUT1 input is selected
39875  *  0b000101..SCT_OUT2 input is selected
39876  *  0b000110..CTIMER0_MAT1 input is selected
39877  *  0b000111..CTIMER1_MAT1 input is selected
39878  *  0b001000..CTIMER2_MAT2 input is selected
39879  *  0b001001..CTIMER3_MAT2 input is selected
39880  *  0b001010..CTIMER4_MAT2 input is selected
39881  *  0b001011..LPTMR0 input is selected
39882  *  0b001100..LPTMR1 input is selected
39883  *  0b001101..Reserved
39884  *  0b001110..PINT GPIO_INT_BMAT input is selected
39885  *  0b001111..CMP0_OUT input is selected
39886  *  0b010000..CMP1_OUT input is selected
39887  *  0b010001..CMP2_OUT input is selected
39888  *  0b010010..EVTG_OUT0A input is selected
39889  *  0b010011..EVTG_OUT0B input is selected
39890  *  0b010100..EVTG_OUT1A input is selected
39891  *  0b010101..EVTG_OUT1B input is selected
39892  *  0b010110..EVTG_OUT2A input is selected
39893  *  0b010111..EVTG_OUT2B input is selected
39894  *  0b011000..EVTG_OUT3A input is selected
39895  *  0b011001..EVTG_OUT3B input is selected
39896  *  0b011010..TRIG_IN0 input is selected
39897  *  0b011011..TRIG_IN1 input is selected
39898  *  0b011100..TRIG_IN2 input is selected
39899  *  0b011101..TRIG_IN3 input is selected
39900  *  0b011110..TRIG_IN4 input is selected
39901  *  0b011111..TRIG_IN10 input is selected
39902  *  0b100000..TRIG_IN11 input is selected
39903  *  0b100001..FlexIO CH4 input is selected
39904  *  0b100010..FlexIO CH5 input is selected
39905  *  0b100011..FlexIO CH6 input is selected
39906  *  0b100100..FlexIO CH7 input is selected
39907  *  0b100101..USB0 ipp_ind_uart_rxd_usbmux input is selected
39908  *  0b100110..GPIO2 Pin Event Trig 0 input is selected
39909  *  0b100111..GPIO2 Pin Event Trig 1 input is selected
39910  *  0b101000..GPIO3 Pin Event Trig 0 input is selected
39911  *  0b101001..GPIO3 Pin Event Trig 1 input is selected
39912  *  0b101010..WUU input is selected
39913  *  *..
39914  */
39915 #define INPUTMUX_FLEXCOMM5_TRIG_INP(x)           (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXCOMM5_TRIG_INP_SHIFT)) & INPUTMUX_FLEXCOMM5_TRIG_INP_MASK)
39916 /*! @} */
39917 
39918 /*! @name FLEXCOMM6_TRIG - LP_FLEXCOMM6 Trigger Input Connections */
39919 /*! @{ */
39920 
39921 #define INPUTMUX_FLEXCOMM6_TRIG_INP_MASK         (0x3FU)
39922 #define INPUTMUX_FLEXCOMM6_TRIG_INP_SHIFT        (0U)
39923 /*! INP - LP_FLEXCOMM6 trigger input connections
39924  *  0b000000..PINT PIN_INT4 input is selected
39925  *  0b000001..PINT PIN_INT5 input is selected
39926  *  0b000010..PINT PIN_INT7 input is selected
39927  *  0b000011..SCT_OUT0 input is selected
39928  *  0b000100..SCT_OUT3 input is selected
39929  *  0b000101..SCT_OUT4 input is selected
39930  *  0b000110..CTIMER0_MAT1 input is selected
39931  *  0b000111..CTIMER1_MAT1 input is selected
39932  *  0b001000..CTIMER2_MAT3 input is selected
39933  *  0b001001..CTIMER3_MAT3 input is selected
39934  *  0b001010..CTIMER4_MAT3 input is selected
39935  *  0b001011..LPTMR0 input is selected
39936  *  0b001100..LPTMR1 input is selected
39937  *  0b001101..Reserved
39938  *  0b001110..PINT GPIO_INT_BMAT input is selected
39939  *  0b001111..CMP0_OUT input is selected
39940  *  0b010000..CMP1_OUT input is selected
39941  *  0b010001..CMP2_OUT input is selected
39942  *  0b010010..EVTG_OUT0A input is selected
39943  *  0b010011..EVTG_OUT0B input is selected
39944  *  0b010100..EVTG_OUT1A input is selected
39945  *  0b010101..EVTG_OUT1B input is selected
39946  *  0b010110..EVTG_OUT2A input is selected
39947  *  0b010111..EVTG_OUT2B input is selected
39948  *  0b011000..EVTG_OUT3A input is selected
39949  *  0b011001..EVTG_OUT3B input is selected
39950  *  0b011010..TRIG_IN0 input is selected
39951  *  0b011011..TRIG_IN1 input is selected
39952  *  0b011100..TRIG_IN2 input is selected
39953  *  0b011101..TRIG_IN3 input is selected
39954  *  0b011110..TRIG_IN4 input is selected
39955  *  0b011111..TRIG_IN10 input is selected
39956  *  0b100000..TRIG_IN11 input is selected
39957  *  0b100001..FlexIO CH4 input is selected
39958  *  0b100010..FlexIO CH5 input is selected
39959  *  0b100011..FlexIO CH6 input is selected
39960  *  0b100100..FlexIO CH7 input is selected
39961  *  0b100101..USB0 ipp_ind_uart_rxd_usbmux input is selected
39962  *  0b100110..GPIO2 Pin Event Trig 0 input is selected
39963  *  0b100111..GPIO2 Pin Event Trig 1 input is selected
39964  *  0b101000..GPIO3 Pin Event Trig 0 input is selected
39965  *  0b101001..GPIO3 Pin Event Trig 1 input is selected
39966  *  0b101010..WUU input is selected
39967  *  *..
39968  */
39969 #define INPUTMUX_FLEXCOMM6_TRIG_INP(x)           (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXCOMM6_TRIG_INP_SHIFT)) & INPUTMUX_FLEXCOMM6_TRIG_INP_MASK)
39970 /*! @} */
39971 
39972 /*! @name FLEXCOMM7_TRIG - LP_FLEXCOMM7 Trigger Input Connections */
39973 /*! @{ */
39974 
39975 #define INPUTMUX_FLEXCOMM7_TRIG_INP_MASK         (0x3FU)
39976 #define INPUTMUX_FLEXCOMM7_TRIG_INP_SHIFT        (0U)
39977 /*! INP - LP_FLEXCOMM7 trigger input connections
39978  *  0b000000..PINT PIN_INT4 input is selected
39979  *  0b000001..PINT PIN_INT5 input is selected
39980  *  0b000010..PINT PIN_INT7 input is selected
39981  *  0b000011..SCT_OUT0 input is selected
39982  *  0b000100..SCT_OUT3 input is selected
39983  *  0b000101..SCT_OUT4 input is selected
39984  *  0b000110..CTIMER0_MAT1 input is selected
39985  *  0b000111..CTIMER1_MAT1 input is selected
39986  *  0b001000..CTIMER2_MAT3 input is selected
39987  *  0b001001..CTIMER3_MAT3 input is selected
39988  *  0b001010..CTIMER4_MAT3 input is selected
39989  *  0b001011..LPTMR0 input is selected
39990  *  0b001100..LPTMR1 input is selected
39991  *  0b001101..Reserved
39992  *  0b001110..PINT GPIO_INT_BMAT input is selected
39993  *  0b001111..CMP0_OUT input is selected
39994  *  0b010000..CMP1_OUT input is selected
39995  *  0b010001..CMP2_OUT input is selected
39996  *  0b010010..EVTG_OUT0A input is selected
39997  *  0b010011..EVTG_OUT0B input is selected
39998  *  0b010100..EVTG_OUT1A input is selected
39999  *  0b010101..EVTG_OUT1B input is selected
40000  *  0b010110..EVTG_OUT2A input is selected
40001  *  0b010111..EVTG_OUT2B input is selected
40002  *  0b011000..EVTG_OUT3A input is selected
40003  *  0b011001..EVTG_OUT3B input is selected
40004  *  0b011010..TRIG_IN0 input is selected
40005  *  0b011011..TRIG_IN1 input is selected
40006  *  0b011100..TRIG_IN2 input is selected
40007  *  0b011101..TRIG_IN3 input is selected
40008  *  0b011110..TRIG_IN4 input is selected
40009  *  0b011111..TRIG_IN10 input is selected
40010  *  0b100000..TRIG_IN11 input is selected
40011  *  0b100001..FlexIO CH4 input is selected
40012  *  0b100010..FlexIO CH5 input is selected
40013  *  0b100011..FlexIO CH6 input is selected
40014  *  0b100100..FlexIO CH7 input is selected
40015  *  0b100101..USB0 ipp_ind_uart_rxd_usbmux input is selected
40016  *  0b100110..GPIO2 Pin Event Trig 0 input is selected
40017  *  0b100111..GPIO2 Pin Event Trig 1 input is selected
40018  *  0b101000..GPIO3 Pin Event Trig 0 input is selected
40019  *  0b101001..GPIO3 Pin Event Trig 1 input is selected
40020  *  0b101010..WUU input is selected
40021  *  *..
40022  */
40023 #define INPUTMUX_FLEXCOMM7_TRIG_INP(x)           (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXCOMM7_TRIG_INP_SHIFT)) & INPUTMUX_FLEXCOMM7_TRIG_INP_MASK)
40024 /*! @} */
40025 
40026 /*! @name FLEXCOMM8_TRIG - LP_FLEXCOMM8 Trigger Input Connections */
40027 /*! @{ */
40028 
40029 #define INPUTMUX_FLEXCOMM8_TRIG_INP_MASK         (0x3FU)
40030 #define INPUTMUX_FLEXCOMM8_TRIG_INP_SHIFT        (0U)
40031 /*! INP - LP_FLEXCOMM8 trigger input connections
40032  *  0b000000..PINT PIN_INT4 input is selected
40033  *  0b000001..PINT PIN_INT5 input is selected
40034  *  0b000010..PINT PIN_INT7 input is selected
40035  *  0b000011..SCT_OUT0 input is selected
40036  *  0b000100..SCT_OUT3 input is selected
40037  *  0b000101..SCT_OUT4 input is selected
40038  *  0b000110..CTIMER0_MAT1 input is selected
40039  *  0b000111..CTIMER1_MAT1 input is selected
40040  *  0b001000..CTIMER2_MAT3 input is selected
40041  *  0b001001..CTIMER3_MAT3 input is selected
40042  *  0b001010..CTIMER4_MAT3 input is selected
40043  *  0b001011..LPTMR0 input is selected
40044  *  0b001100..LPTMR1 input is selected
40045  *  0b001101..Reserved
40046  *  0b001110..PINT GPIO_INT_BMAT input is selected
40047  *  0b001111..CMP0_OUT input is selected
40048  *  0b010000..CMP1_OUT input is selected
40049  *  0b010001..CMP2_OUT input is selected
40050  *  0b010010..EVTG_OUT0A input is selected
40051  *  0b010011..EVTG_OUT0B input is selected
40052  *  0b010100..EVTG_OUT1A input is selected
40053  *  0b010101..EVTG_OUT1B input is selected
40054  *  0b010110..EVTG_OUT2A input is selected
40055  *  0b010111..EVTG_OUT2B input is selected
40056  *  0b011000..EVTG_OUT3A input is selected
40057  *  0b011001..EVTG_OUT3B input is selected
40058  *  0b011010..TRIG_IN0 input is selected
40059  *  0b011011..TRIG_IN1 input is selected
40060  *  0b011100..TRIG_IN2 input is selected
40061  *  0b011101..TRIG_IN3 input is selected
40062  *  0b011110..TRIG_IN4 input is selected
40063  *  0b011111..TRIG_IN10 input is selected
40064  *  0b100000..TRIG_IN11 input is selected
40065  *  0b100001..FlexIO CH4 input is selected
40066  *  0b100010..FlexIO CH5 input is selected
40067  *  0b100011..FlexIO CH6 input is selected
40068  *  0b100100..FlexIO CH7 input is selected
40069  *  0b100101..USB0 ipp_ind_uart_rxd_usbmux input is selected
40070  *  0b100110..GPIO2 Pin Event Trig 0 input is selected
40071  *  0b100111..GPIO2 Pin Event Trig 1 input is selected
40072  *  0b101000..GPIO3 Pin Event Trig 0 input is selected
40073  *  0b101001..GPIO3 Pin Event Trig 1 input is selected
40074  *  0b101010..WUU input is selected
40075  *  *..
40076  */
40077 #define INPUTMUX_FLEXCOMM8_TRIG_INP(x)           (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXCOMM8_TRIG_INP_SHIFT)) & INPUTMUX_FLEXCOMM8_TRIG_INP_MASK)
40078 /*! @} */
40079 
40080 /*! @name FLEXCOMM9_TRIG - LP_FLEXCOMM9 Trigger Input Connections */
40081 /*! @{ */
40082 
40083 #define INPUTMUX_FLEXCOMM9_TRIG_INP_MASK         (0x3FU)
40084 #define INPUTMUX_FLEXCOMM9_TRIG_INP_SHIFT        (0U)
40085 /*! INP - LP_FLEXCOMM9 trigger input connections
40086  *  0b000000..PINT PIN_INT4 input is selected
40087  *  0b000001..PINT PIN_INT5 input is selected
40088  *  0b000010..PINT PIN_INT7 input is selected
40089  *  0b000011..SCT_OUT0 input is selected
40090  *  0b000100..SCT_OUT3 input is selected
40091  *  0b000101..SCT_OUT4 input is selected
40092  *  0b000110..CTIMER0_MAT1 input is selected
40093  *  0b000111..CTIMER1_MAT1 input is selected
40094  *  0b001000..CTIMER2_MAT0 input is selected
40095  *  0b001001..CTIMER3_MAT0 input is selected
40096  *  0b001010..CTIMER4_MAT0 input is selected
40097  *  0b001011..LPTMR0 input is selected
40098  *  0b001100..LPTMR1 input is selected
40099  *  0b001101..Reserved
40100  *  0b001110..PINT GPIO_INT_BMAT input is selected
40101  *  0b001111..CMP0_OUT input is selected
40102  *  0b010000..CMP1_OUT input is selected
40103  *  0b010001..CMP2_OUT input is selected
40104  *  0b010010..EVTG_OUT0A input is selected
40105  *  0b010011..EVTG_OUT0B input is selected
40106  *  0b010100..EVTG_OUT1A input is selected
40107  *  0b010101..EVTG_OUT1B input is selected
40108  *  0b010110..EVTG_OUT2A input is selected
40109  *  0b010111..EVTG_OUT2B input is selected
40110  *  0b011000..EVTG_OUT3A input is selected
40111  *  0b011001..EVTG_OUT3B input is selected
40112  *  0b011010..TRIG_IN0 input is selected
40113  *  0b011011..TRIG_IN1 input is selected
40114  *  0b011100..TRIG_IN2 input is selected
40115  *  0b011101..TRIG_IN3 input is selected
40116  *  0b011110..TRIG_IN4 input is selected
40117  *  0b011111..TRIG_IN10 input is selected
40118  *  0b100000..TRIG_IN11 input is selected
40119  *  0b100001..FlexIO CH4 input is selected
40120  *  0b100010..FlexIO CH5 input is selected
40121  *  0b100011..FlexIO CH6 input is selected
40122  *  0b100100..FlexIO CH7 input is selected
40123  *  0b100101..USB0 ipp_ind_uart_rxd_usbmux input is selected
40124  *  0b100110..GPIO2 Pin Event Trig 0 input is selected
40125  *  0b100111..GPIO2 Pin Event Trig 1 input is selected
40126  *  0b101000..GPIO3 Pin Event Trig 0 input is selected
40127  *  0b101001..GPIO3 Pin Event Trig 1 input is selected
40128  *  0b101010..WUU input is selected
40129  *  *..
40130  */
40131 #define INPUTMUX_FLEXCOMM9_TRIG_INP(x)           (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXCOMM9_TRIG_INP_SHIFT)) & INPUTMUX_FLEXCOMM9_TRIG_INP_MASK)
40132 /*! @} */
40133 
40134 /*! @name FLEXIO_TRIGN_FLEXIO_TRIG - FlexIO Trigger Input Connections */
40135 /*! @{ */
40136 
40137 #define INPUTMUX_FLEXIO_TRIGN_FLEXIO_TRIG_INP_MASK (0x7FU)
40138 #define INPUTMUX_FLEXIO_TRIGN_FLEXIO_TRIG_INP_SHIFT (0U)
40139 /*! INP - Input number for FlexIO0.
40140  *  0b0000000..PINT PIN_INT4 input is selected
40141  *  0b0000001..PINT PIN_INT5 input is selected
40142  *  0b0000010..PINT PIN_INT6 input is selected
40143  *  0b0000011..PINT PIN_INT7 input is selected
40144  *  0b0000100..SCT_OUT5 input is selected
40145  *  0b0000101..SCT_OUT6 input is selected
40146  *  0b0000110..SCT_OUT7 input is selected
40147  *  0b0000111..SCT_OUT8 input is selected
40148  *  0b0001000..SCT_OUT9 input is selected
40149  *  0b0001001..T0_MAT1 input is selected
40150  *  0b0001010..T1_MAT1 input is selected
40151  *  0b0001011..T2_MAT1 input is selected
40152  *  0b0001100..T3_MAT1 input is selected
40153  *  0b0001101..T4_MAT1 input is selected
40154  *  0b0001110..LPTMR0 input is selected
40155  *  0b0001111..LPTMR1 input is selected
40156  *  0b0010000..Reserved
40157  *  0b0010001..PINT GPIO_INT_BMAT input is selected
40158  *  0b0010010..ADC0_tcomp[0] input is selected
40159  *  0b0010011..ADC0_tcomp[1] input is selected
40160  *  0b0010100..ADC0_tcomp[2] input is selected
40161  *  0b0010101..ADC0_tcomp[3] input is selected
40162  *  0b0010110..ADC1_tcomp[0] input is selected
40163  *  0b0010111..ADC1_tcomp[1] input is selected
40164  *  0b0011000..ADC1_tcomp[2] input is selected
40165  *  0b0011001..ADC1_tcomp[3] input is selected
40166  *  0b0011010..CMP0_OUT input is selected
40167  *  0b0011011..CMP1_OUT input is selected
40168  *  0b0011100..CMP2_OUT input is selected
40169  *  0b0011101..PWM0_SM0_MUX_TRIG0 input is selected
40170  *  0b0011110..PWM0_SM0_MUX_TRIG1 input is selected
40171  *  0b0011111..PWM0_SM1_MUX_TRIG0 input is selected
40172  *  0b0100000..PWM0_SM1_MUX_TRIG1 input is selected
40173  *  0b0100001..PWM0_SM2_MUX_TRIG0 input is selected
40174  *  0b0100010..PWM0_SM2_MUX_TRIG1 input is selected
40175  *  0b0100011..PWM0_SM3_MUX_TRIG0 input is selected
40176  *  0b0100100..PWM0_SM3_MUX_TRIG1 input is selected
40177  *  0b0100101..PWM1_SM0_MUX_TRIG0 input is selected
40178  *  0b0100110..PWM1_SM0_MUX_TRIG1 input is selected
40179  *  0b0100111..PWM1_SM1_MUX_TRIG0 input is selected
40180  *  0b0101000..PWM1_SM1_MUX_TRIG1 input is selected
40181  *  0b0101001..PWM1_SM2_MUX_TRIG0 input is selected
40182  *  0b0101010..PWM1_SM2_MUX_TRIG1 input is selected
40183  *  0b0101011..PWM1_SM3_MUX_TRIG0 input is selected
40184  *  0b0101100..PWM1_SM3_MUX_TRIG1 input is selected
40185  *  0b0101101..EVTG_OUT0A input is selected
40186  *  0b0101110..EVTG_OUT0B input is selected
40187  *  0b0101111..EVTG_OUT1A input is selected
40188  *  0b0110000..EVTG_OUT1B input is selected
40189  *  0b0110001..EVTG_OUT2A input is selected
40190  *  0b0110010..EVTG_OUT2B input is selected
40191  *  0b0110011..EVTG_OUT3A input is selected
40192  *  0b0110100..EVTG_OUT3B input is selected
40193  *  0b0110101..TRIG_IN0 input is selected
40194  *  0b0110110..TRIG_IN1 input is selected
40195  *  0b0110111..TRIG_IN2 input is selected
40196  *  0b0111000..TRIG_IN3 input is selected
40197  *  0b0111001..TRIG_IN4 input is selected
40198  *  0b0111010..SINC Filter CH0 Conversion Complete input is selected
40199  *  0b0111011..SINC Filter CH1 Conversion Complete input is selected
40200  *  0b0111100..SINC Filter CH2 Conversion Complete input is selected
40201  *  0b0111101..SINC Filter CH3 Conversion Complete input is selected
40202  *  0b0111110..SINC Filter CH4 Conversion Complete input is selected
40203  *  0b0111111..LP_FLEXCOMM0 trig 0 (lpuart_trg_txword) input is selected
40204  *  0b1000000..LP_FLEXCOMM0 trig 1 (lpuart_trg_rxword) input is selected
40205  *  0b1000001..LP_FLEXCOMM0 trig 2 (lpuart_trg_rxidle) input is selected
40206  *  0b1000010..LP_FLEXCOMM1 trig 0 input is selected
40207  *  0b1000011..LP_FLEXCOMM1 trig 1 input is selected
40208  *  0b1000100..LP_FLEXCOMM1 trig 2 input is selected
40209  *  0b1000101..LP_FLEXCOMM2 trig 0 input is selected
40210  *  0b1000110..LP_FLEXCOMM2 trig 1 input is selected
40211  *  0b1000111..LP_FLEXCOMM2 trig 2 input is selected
40212  *  0b1001000..LP_FLEXCOMM3 trig 0 input is selected
40213  *  0b1001001..LP_FLEXCOMM3 trig 1 input is selected
40214  *  0b1001010..LP_FLEXCOMM3 trig 2 input is selected
40215  *  0b1001011..LP_FLEXCOMM3 trig 3 input is selected
40216  *  0b1001100..WUU input is selected
40217  *  *..
40218  */
40219 #define INPUTMUX_FLEXIO_TRIGN_FLEXIO_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXIO_TRIGN_FLEXIO_TRIG_INP_SHIFT)) & INPUTMUX_FLEXIO_TRIGN_FLEXIO_TRIG_INP_MASK)
40220 /*! @} */
40221 
40222 /* The count of INPUTMUX_FLEXIO_TRIGN_FLEXIO_TRIG */
40223 #define INPUTMUX_FLEXIO_TRIGN_FLEXIO_TRIG_COUNT  (8U)
40224 
40225 /*! @name DMA0_REQ_ENABLE0 - DMA0 Request Enable0 */
40226 /*! @{ */
40227 
40228 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ1_EN0_MASK  (0x2U)
40229 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ1_EN0_SHIFT (1U)
40230 /*! REQ1_EN0 - This register is used to enable and disable FLEXSPI0 receive event request.
40231  *  0b0..Disable
40232  *  0b1..Enable
40233  */
40234 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ1_EN0(x)    (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ1_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ1_EN0_MASK)
40235 
40236 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ2_EN0_MASK  (0x4U)
40237 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ2_EN0_SHIFT (2U)
40238 /*! REQ2_EN0 - This register is used to enable and disable FLEXSPI0 transmit event request.
40239  *  0b0..Disable
40240  *  0b1..Enable
40241  */
40242 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ2_EN0(x)    (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ2_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ2_EN0_MASK)
40243 
40244 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ3_EN0_MASK  (0x8U)
40245 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ3_EN0_SHIFT (3U)
40246 /*! REQ3_EN0 - This register is used to enable and disable PINT0 INT0 request.
40247  *  0b0..Disable
40248  *  0b1..Enable
40249  */
40250 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ3_EN0(x)    (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ3_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ3_EN0_MASK)
40251 
40252 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ4_EN0_MASK  (0x10U)
40253 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ4_EN0_SHIFT (4U)
40254 /*! REQ4_EN0 - This register is used to enable and disable PINT0 INT1 request.
40255  *  0b0..Disable
40256  *  0b1..Enable
40257  */
40258 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ4_EN0(x)    (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ4_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ4_EN0_MASK)
40259 
40260 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ5_EN0_MASK  (0x20U)
40261 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ5_EN0_SHIFT (5U)
40262 /*! REQ5_EN0 - This register is used to enable and disable PINT0 INT2 request.
40263  *  0b0..Disable
40264  *  0b1..Enable
40265  */
40266 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ5_EN0(x)    (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ5_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ5_EN0_MASK)
40267 
40268 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ6_EN0_MASK  (0x40U)
40269 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ6_EN0_SHIFT (6U)
40270 /*! REQ6_EN0 - This register is used to enable and disable PINT0 INT3 request.
40271  *  0b0..Disable
40272  *  0b1..Enable
40273  */
40274 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ6_EN0(x)    (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ6_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ6_EN0_MASK)
40275 
40276 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ7_EN0_MASK  (0x80U)
40277 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ7_EN0_SHIFT (7U)
40278 /*! REQ7_EN0 - This register is used to enable and disable CTIMER0 DMAREQ_M0 request.
40279  *  0b0..Disable
40280  *  0b1..Enable
40281  */
40282 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ7_EN0(x)    (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ7_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ7_EN0_MASK)
40283 
40284 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ8_EN0_MASK  (0x100U)
40285 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ8_EN0_SHIFT (8U)
40286 /*! REQ8_EN0 - This register is used to enable and disable CTIMER0 DMAREQ_M1 request.
40287  *  0b0..Disable
40288  *  0b1..Enable
40289  */
40290 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ8_EN0(x)    (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ8_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ8_EN0_MASK)
40291 
40292 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ9_EN0_MASK  (0x200U)
40293 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ9_EN0_SHIFT (9U)
40294 /*! REQ9_EN0 - This register is used to enable and disable CTIMER1 DMAREQ_M0 request.
40295  *  0b0..Disable
40296  *  0b1..Enable
40297  */
40298 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ9_EN0(x)    (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ9_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ9_EN0_MASK)
40299 
40300 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ10_EN0_MASK (0x400U)
40301 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ10_EN0_SHIFT (10U)
40302 /*! REQ10_EN0 - This register is used to enable and disable CTIMER1 DMAREQ_M1 request.
40303  *  0b0..Disable
40304  *  0b1..Enable
40305  */
40306 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ10_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ10_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ10_EN0_MASK)
40307 
40308 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ11_EN0_MASK (0x800U)
40309 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ11_EN0_SHIFT (11U)
40310 /*! REQ11_EN0 - This register is used to enable and disable CTIMER2 DMAREQ_M0 request.
40311  *  0b0..Disable
40312  *  0b1..Enable
40313  */
40314 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ11_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ11_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ11_EN0_MASK)
40315 
40316 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ12_EN0_MASK (0x1000U)
40317 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ12_EN0_SHIFT (12U)
40318 /*! REQ12_EN0 - This register is used to enable and disable CTIMER2 DMAREQ_M1 request.
40319  *  0b0..Disable
40320  *  0b1..Enable
40321  */
40322 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ12_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ12_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ12_EN0_MASK)
40323 
40324 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ13_EN0_MASK (0x2000U)
40325 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ13_EN0_SHIFT (13U)
40326 /*! REQ13_EN0 - This register is used to enable and disable CTIMER3 DMAREQ_M0 request.
40327  *  0b0..Disable
40328  *  0b1..Enable
40329  */
40330 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ13_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ13_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ13_EN0_MASK)
40331 
40332 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ14_EN0_MASK (0x4000U)
40333 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ14_EN0_SHIFT (14U)
40334 /*! REQ14_EN0 - This register is used to enable and disable CTIMER3 DMAREQ_M1 request.
40335  *  0b0..Disable
40336  *  0b1..Enable
40337  */
40338 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ14_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ14_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ14_EN0_MASK)
40339 
40340 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ15_EN0_MASK (0x8000U)
40341 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ15_EN0_SHIFT (15U)
40342 /*! REQ15_EN0 - This register is used to enable and disable CTIMER4 DMAREQ_M0 request.
40343  *  0b0..Disable
40344  *  0b1..Enable
40345  */
40346 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ15_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ15_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ15_EN0_MASK)
40347 
40348 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ16_EN0_MASK (0x10000U)
40349 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ16_EN0_SHIFT (16U)
40350 /*! REQ16_EN0 - This register is used to enable and disable CTIMER4 DMAREQ_M1 request.
40351  *  0b0..Disable
40352  *  0b1..Enable
40353  */
40354 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ16_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ16_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ16_EN0_MASK)
40355 
40356 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ17_EN0_MASK (0x20000U)
40357 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ17_EN0_SHIFT (17U)
40358 /*! REQ17_EN0 - This register is used to enable and disable WUU0 wake up event request.
40359  *  0b0..Disable
40360  *  0b1..Enable
40361  */
40362 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ17_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ17_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ17_EN0_MASK)
40363 
40364 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ18_EN0_MASK (0x40000U)
40365 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ18_EN0_SHIFT (18U)
40366 /*! REQ18_EN0 - This register is used to enable and disable MICFIL0 FIFO_request.
40367  *  0b0..Disable
40368  *  0b1..Enable
40369  */
40370 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ18_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ18_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ18_EN0_MASK)
40371 
40372 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ19_EN0_MASK (0x80000U)
40373 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ19_EN0_SHIFT (19U)
40374 /*! REQ19_EN0 - This register is used to enable and disable SCT0 DMA0 request.
40375  *  0b0..Disable
40376  *  0b1..Enable
40377  */
40378 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ19_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ19_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ19_EN0_MASK)
40379 
40380 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ20_EN0_MASK (0x100000U)
40381 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ20_EN0_SHIFT (20U)
40382 /*! REQ20_EN0 - This register is used to enable and disable SCT0 DMA1 request.
40383  *  0b0..Disable
40384  *  0b1..Enable
40385  */
40386 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ20_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ20_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ20_EN0_MASK)
40387 
40388 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ21_EN0_MASK (0x200000U)
40389 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ21_EN0_SHIFT (21U)
40390 /*! REQ21_EN0 - This register is used to enable and disable ADC0 FIFO A request.
40391  *  0b0..Disable
40392  *  0b1..Enable
40393  */
40394 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ21_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ21_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ21_EN0_MASK)
40395 
40396 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ22_EN0_MASK (0x400000U)
40397 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ22_EN0_SHIFT (22U)
40398 /*! REQ22_EN0 - This register is used to enable and disable ADC0 FIFO B request.
40399  *  0b0..Disable
40400  *  0b1..Enable
40401  */
40402 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ22_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ22_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ22_EN0_MASK)
40403 
40404 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ23_EN0_MASK (0x800000U)
40405 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ23_EN0_SHIFT (23U)
40406 /*! REQ23_EN0 - This register is used to enable and disable ADC1 FIFO A request.
40407  *  0b0..Disable
40408  *  0b1..Enable
40409  */
40410 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ23_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ23_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ23_EN0_MASK)
40411 
40412 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ24_EN0_MASK (0x1000000U)
40413 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ24_EN0_SHIFT (24U)
40414 /*! REQ24_EN0 - This register is used to enable and disable ADC1 FIFO B request.
40415  *  0b0..Disable
40416  *  0b1..Enable
40417  */
40418 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ24_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ24_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ24_EN0_MASK)
40419 
40420 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ25_EN0_MASK (0x2000000U)
40421 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ25_EN0_SHIFT (25U)
40422 /*! REQ25_EN0 - This register is used to enable and disable DAC0 FIFO_request.
40423  *  0b0..Disable
40424  *  0b1..Enable
40425  */
40426 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ25_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ25_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ25_EN0_MASK)
40427 
40428 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ26_EN0_MASK (0x4000000U)
40429 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ26_EN0_SHIFT (26U)
40430 /*! REQ26_EN0 - This register is used to enable and disable DAC1 FIFO_request.
40431  *  0b0..Disable
40432  *  0b1..Enable
40433  */
40434 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ26_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ26_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ26_EN0_MASK)
40435 
40436 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ27_EN0_MASK (0x8000000U)
40437 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ27_EN0_SHIFT (27U)
40438 /*! REQ27_EN0 - This register is used to enable and disable DAC2 FIFO_request.
40439  *  0b0..Disable
40440  *  0b1..Enable
40441  */
40442 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ27_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ27_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ27_EN0_MASK)
40443 
40444 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ28_EN0_MASK (0x10000000U)
40445 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ28_EN0_SHIFT (28U)
40446 /*! REQ28_EN0 - This register is used to enable and disable CMP0 DMA_request.
40447  *  0b0..Disable
40448  *  0b1..Enable
40449  */
40450 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ28_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ28_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ28_EN0_MASK)
40451 
40452 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ29_EN0_MASK (0x20000000U)
40453 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ29_EN0_SHIFT (29U)
40454 /*! REQ29_EN0 - This register is used to enable and disable CMP1 DMA_request.
40455  *  0b0..Disable
40456  *  0b1..Enable
40457  */
40458 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ29_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ29_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ29_EN0_MASK)
40459 
40460 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ30_EN0_MASK (0x40000000U)
40461 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ30_EN0_SHIFT (30U)
40462 /*! REQ30_EN0 - This register is used to enable and disable CMP2 DMA_request.
40463  *  0b0..Disable
40464  *  0b1..Enable
40465  */
40466 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ30_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ30_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ30_EN0_MASK)
40467 
40468 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ31_EN0_MASK (0x80000000U)
40469 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ31_EN0_SHIFT (31U)
40470 /*! REQ31_EN0 - This register is used to enable and disable EVTG0 OUT0A request.
40471  *  0b0..Disable
40472  *  0b1..Enable
40473  */
40474 #define INPUTMUX_DMA0_REQ_ENABLE0_REQ31_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ31_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ31_EN0_MASK)
40475 /*! @} */
40476 
40477 /*! @name DMA0_REQ_ENABLE0_SET - DMA0 Request Enable0 */
40478 /*! @{ */
40479 
40480 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ1_EN0_MASK (0x2U)
40481 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ1_EN0_SHIFT (1U)
40482 /*! REQ1_EN0 - Writing a 1 to REQ1_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */
40483 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ1_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ1_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ1_EN0_MASK)
40484 
40485 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ2_EN0_MASK (0x4U)
40486 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ2_EN0_SHIFT (2U)
40487 /*! REQ2_EN0 - Writing a 1 to REQ2_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */
40488 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ2_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ2_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ2_EN0_MASK)
40489 
40490 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ3_EN0_MASK (0x8U)
40491 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ3_EN0_SHIFT (3U)
40492 /*! REQ3_EN0 - Writing a 1 to REQ3_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */
40493 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ3_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ3_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ3_EN0_MASK)
40494 
40495 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ4_EN0_MASK (0x10U)
40496 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ4_EN0_SHIFT (4U)
40497 /*! REQ4_EN0 - Writing a 1 to REQ4_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */
40498 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ4_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ4_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ4_EN0_MASK)
40499 
40500 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ5_EN0_MASK (0x20U)
40501 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ5_EN0_SHIFT (5U)
40502 /*! REQ5_EN0 - Writing a 1 to REQ5_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */
40503 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ5_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ5_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ5_EN0_MASK)
40504 
40505 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ6_EN0_MASK (0x40U)
40506 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ6_EN0_SHIFT (6U)
40507 /*! REQ6_EN0 - Writing a 1 to REQ6_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */
40508 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ6_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ6_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ6_EN0_MASK)
40509 
40510 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ7_EN0_MASK (0x80U)
40511 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ7_EN0_SHIFT (7U)
40512 /*! REQ7_EN0 - Writing a 1 to REQ7_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */
40513 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ7_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ7_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ7_EN0_MASK)
40514 
40515 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ8_EN0_MASK (0x100U)
40516 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ8_EN0_SHIFT (8U)
40517 /*! REQ8_EN0 - Writing a 1 to REQ8_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */
40518 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ8_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ8_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ8_EN0_MASK)
40519 
40520 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ9_EN0_MASK (0x200U)
40521 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ9_EN0_SHIFT (9U)
40522 /*! REQ9_EN0 - Writing a 1 to REQ9_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */
40523 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ9_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ9_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ9_EN0_MASK)
40524 
40525 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ10_EN0_MASK (0x400U)
40526 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ10_EN0_SHIFT (10U)
40527 /*! REQ10_EN0 - Writing a 1 to REQ10_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */
40528 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ10_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ10_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ10_EN0_MASK)
40529 
40530 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ11_EN0_MASK (0x800U)
40531 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ11_EN0_SHIFT (11U)
40532 /*! REQ11_EN0 - Writing a 1 to REQ11_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */
40533 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ11_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ11_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ11_EN0_MASK)
40534 
40535 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ12_EN0_MASK (0x1000U)
40536 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ12_EN0_SHIFT (12U)
40537 /*! REQ12_EN0 - Writing a 1 to REQ12_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */
40538 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ12_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ12_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ12_EN0_MASK)
40539 
40540 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ13_EN0_MASK (0x2000U)
40541 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ13_EN0_SHIFT (13U)
40542 /*! REQ13_EN0 - Writing a 1 to REQ13_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */
40543 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ13_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ13_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ13_EN0_MASK)
40544 
40545 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ14_EN0_MASK (0x4000U)
40546 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ14_EN0_SHIFT (14U)
40547 /*! REQ14_EN0 - Writing a 1 to REQ14_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */
40548 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ14_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ14_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ14_EN0_MASK)
40549 
40550 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ15_EN0_MASK (0x8000U)
40551 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ15_EN0_SHIFT (15U)
40552 /*! REQ15_EN0 - Writing a 1 to REQ15_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */
40553 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ15_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ15_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ15_EN0_MASK)
40554 
40555 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ16_EN0_MASK (0x10000U)
40556 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ16_EN0_SHIFT (16U)
40557 /*! REQ16_EN0 - Writing a 1 to REQ16_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */
40558 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ16_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ16_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ16_EN0_MASK)
40559 
40560 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ17_EN0_MASK (0x20000U)
40561 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ17_EN0_SHIFT (17U)
40562 /*! REQ17_EN0 - Writing a 1 to REQ17_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */
40563 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ17_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ17_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ17_EN0_MASK)
40564 
40565 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ18_EN0_MASK (0x40000U)
40566 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ18_EN0_SHIFT (18U)
40567 /*! REQ18_EN0 - Writing a 1 to REQ18_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */
40568 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ18_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ18_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ18_EN0_MASK)
40569 
40570 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ19_EN0_MASK (0x80000U)
40571 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ19_EN0_SHIFT (19U)
40572 /*! REQ19_EN0 - Writing a 1 to REQ19_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */
40573 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ19_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ19_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ19_EN0_MASK)
40574 
40575 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ20_EN0_MASK (0x100000U)
40576 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ20_EN0_SHIFT (20U)
40577 /*! REQ20_EN0 - Writing a 1 to REQ20_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */
40578 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ20_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ20_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ20_EN0_MASK)
40579 
40580 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ21_EN0_MASK (0x200000U)
40581 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ21_EN0_SHIFT (21U)
40582 /*! REQ21_EN0 - Writing a 1 to REQ21_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */
40583 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ21_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ21_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ21_EN0_MASK)
40584 
40585 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ22_EN0_MASK (0x400000U)
40586 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ22_EN0_SHIFT (22U)
40587 /*! REQ22_EN0 - Writing a 1 to REQ22_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */
40588 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ22_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ22_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ22_EN0_MASK)
40589 
40590 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ23_EN0_MASK (0x800000U)
40591 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ23_EN0_SHIFT (23U)
40592 /*! REQ23_EN0 - Writing a 1 to REQ23_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */
40593 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ23_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ23_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ23_EN0_MASK)
40594 
40595 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ24_EN0_MASK (0x1000000U)
40596 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ24_EN0_SHIFT (24U)
40597 /*! REQ24_EN0 - Writing a 1 to REQ24_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */
40598 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ24_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ24_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ24_EN0_MASK)
40599 
40600 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ25_EN0_MASK (0x2000000U)
40601 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ25_EN0_SHIFT (25U)
40602 /*! REQ25_EN0 - Writing a 1 to REQ25_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */
40603 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ25_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ25_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ25_EN0_MASK)
40604 
40605 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ26_EN0_MASK (0x4000000U)
40606 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ26_EN0_SHIFT (26U)
40607 /*! REQ26_EN0 - Writing a 1 to REQ26_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */
40608 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ26_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ26_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ26_EN0_MASK)
40609 
40610 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ27_EN0_MASK (0x8000000U)
40611 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ27_EN0_SHIFT (27U)
40612 /*! REQ27_EN0 - Writing a 1 to REQ27_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */
40613 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ27_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ27_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ27_EN0_MASK)
40614 
40615 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ28_EN0_MASK (0x10000000U)
40616 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ28_EN0_SHIFT (28U)
40617 /*! REQ28_EN0 - Writing a 1 to REQ28_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */
40618 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ28_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ28_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ28_EN0_MASK)
40619 
40620 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ29_EN0_MASK (0x20000000U)
40621 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ29_EN0_SHIFT (29U)
40622 /*! REQ29_EN0 - Writing a 1 to REQ29_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */
40623 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ29_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ29_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ29_EN0_MASK)
40624 
40625 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ30_EN0_MASK (0x40000000U)
40626 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ30_EN0_SHIFT (30U)
40627 /*! REQ30_EN0 - Writing a 1 to REQ30_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */
40628 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ30_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ30_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ30_EN0_MASK)
40629 
40630 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ31_EN0_MASK (0x80000000U)
40631 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ31_EN0_SHIFT (31U)
40632 /*! REQ31_EN0 - Writing a 1 to REQ31_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */
40633 #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ31_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ31_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ31_EN0_MASK)
40634 /*! @} */
40635 
40636 /*! @name DMA0_REQ_ENABLE0_CLR - DMA0 Request Enable0 */
40637 /*! @{ */
40638 
40639 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ1_EN0_MASK (0x2U)
40640 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ1_EN0_SHIFT (1U)
40641 /*! REQ1_EN0 - Writing a 1 to REQ1_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */
40642 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ1_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ1_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ1_EN0_MASK)
40643 
40644 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ2_EN0_MASK (0x4U)
40645 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ2_EN0_SHIFT (2U)
40646 /*! REQ2_EN0 - Writing a 1 to REQ2_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */
40647 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ2_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ2_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ2_EN0_MASK)
40648 
40649 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ3_EN0_MASK (0x8U)
40650 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ3_EN0_SHIFT (3U)
40651 /*! REQ3_EN0 - Writing a 1 to REQ3_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */
40652 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ3_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ3_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ3_EN0_MASK)
40653 
40654 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ4_EN0_MASK (0x10U)
40655 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ4_EN0_SHIFT (4U)
40656 /*! REQ4_EN0 - Writing a 1 to REQ4_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */
40657 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ4_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ4_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ4_EN0_MASK)
40658 
40659 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ5_EN0_MASK (0x20U)
40660 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ5_EN0_SHIFT (5U)
40661 /*! REQ5_EN0 - Writing a 1 to REQ5_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */
40662 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ5_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ5_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ5_EN0_MASK)
40663 
40664 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ6_EN0_MASK (0x40U)
40665 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ6_EN0_SHIFT (6U)
40666 /*! REQ6_EN0 - Writing a 1 to REQ6_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */
40667 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ6_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ6_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ6_EN0_MASK)
40668 
40669 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ7_EN0_MASK (0x80U)
40670 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ7_EN0_SHIFT (7U)
40671 /*! REQ7_EN0 - Writing a 1 to REQ7_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */
40672 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ7_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ7_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ7_EN0_MASK)
40673 
40674 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ8_EN0_MASK (0x100U)
40675 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ8_EN0_SHIFT (8U)
40676 /*! REQ8_EN0 - Writing a 1 to REQ8_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */
40677 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ8_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ8_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ8_EN0_MASK)
40678 
40679 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ9_EN0_MASK (0x200U)
40680 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ9_EN0_SHIFT (9U)
40681 /*! REQ9_EN0 - Writing a 1 to REQ9_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */
40682 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ9_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ9_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ9_EN0_MASK)
40683 
40684 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ10_EN0_MASK (0x400U)
40685 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ10_EN0_SHIFT (10U)
40686 /*! REQ10_EN0 - Writing a 1 to REQ10_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */
40687 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ10_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ10_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ10_EN0_MASK)
40688 
40689 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ11_EN0_MASK (0x800U)
40690 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ11_EN0_SHIFT (11U)
40691 /*! REQ11_EN0 - Writing a 1 to REQ11_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */
40692 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ11_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ11_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ11_EN0_MASK)
40693 
40694 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ12_EN0_MASK (0x1000U)
40695 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ12_EN0_SHIFT (12U)
40696 /*! REQ12_EN0 - Writing a 1 to REQ12_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */
40697 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ12_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ12_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ12_EN0_MASK)
40698 
40699 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ13_EN0_MASK (0x2000U)
40700 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ13_EN0_SHIFT (13U)
40701 /*! REQ13_EN0 - Writing a 1 to REQ13_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */
40702 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ13_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ13_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ13_EN0_MASK)
40703 
40704 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ14_EN0_MASK (0x4000U)
40705 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ14_EN0_SHIFT (14U)
40706 /*! REQ14_EN0 - Writing a 1 to REQ14_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */
40707 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ14_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ14_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ14_EN0_MASK)
40708 
40709 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ15_EN0_MASK (0x8000U)
40710 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ15_EN0_SHIFT (15U)
40711 /*! REQ15_EN0 - Writing a 1 to REQ15_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */
40712 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ15_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ15_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ15_EN0_MASK)
40713 
40714 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ16_EN0_MASK (0x10000U)
40715 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ16_EN0_SHIFT (16U)
40716 /*! REQ16_EN0 - Writing a 1 to REQ16_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */
40717 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ16_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ16_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ16_EN0_MASK)
40718 
40719 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ17_EN0_MASK (0x20000U)
40720 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ17_EN0_SHIFT (17U)
40721 /*! REQ17_EN0 - Writing a 1 to REQ17_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */
40722 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ17_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ17_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ17_EN0_MASK)
40723 
40724 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ18_EN0_MASK (0x40000U)
40725 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ18_EN0_SHIFT (18U)
40726 /*! REQ18_EN0 - Writing a 1 to REQ18_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */
40727 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ18_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ18_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ18_EN0_MASK)
40728 
40729 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ19_EN0_MASK (0x80000U)
40730 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ19_EN0_SHIFT (19U)
40731 /*! REQ19_EN0 - Writing a 1 to REQ19_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */
40732 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ19_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ19_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ19_EN0_MASK)
40733 
40734 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ20_EN0_MASK (0x100000U)
40735 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ20_EN0_SHIFT (20U)
40736 /*! REQ20_EN0 - Writing a 1 to REQ20_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */
40737 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ20_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ20_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ20_EN0_MASK)
40738 
40739 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ21_EN0_MASK (0x200000U)
40740 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ21_EN0_SHIFT (21U)
40741 /*! REQ21_EN0 - Writing a 1 to REQ21_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */
40742 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ21_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ21_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ21_EN0_MASK)
40743 
40744 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ22_EN0_MASK (0x400000U)
40745 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ22_EN0_SHIFT (22U)
40746 /*! REQ22_EN0 - Writing a 1 to REQ22_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */
40747 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ22_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ22_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ22_EN0_MASK)
40748 
40749 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ23_EN0_MASK (0x800000U)
40750 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ23_EN0_SHIFT (23U)
40751 /*! REQ23_EN0 - Writing a 1 to REQ23_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */
40752 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ23_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ23_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ23_EN0_MASK)
40753 
40754 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ24_EN0_MASK (0x1000000U)
40755 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ24_EN0_SHIFT (24U)
40756 /*! REQ24_EN0 - Writing a 1 to REQ24_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */
40757 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ24_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ24_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ24_EN0_MASK)
40758 
40759 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ25_EN0_MASK (0x2000000U)
40760 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ25_EN0_SHIFT (25U)
40761 /*! REQ25_EN0 - Writing a 1 to REQ25_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */
40762 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ25_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ25_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ25_EN0_MASK)
40763 
40764 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ26_EN0_MASK (0x4000000U)
40765 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ26_EN0_SHIFT (26U)
40766 /*! REQ26_EN0 - Writing a 1 to REQ26_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */
40767 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ26_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ26_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ26_EN0_MASK)
40768 
40769 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ27_EN0_MASK (0x8000000U)
40770 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ27_EN0_SHIFT (27U)
40771 /*! REQ27_EN0 - Writing a 1 to REQ27_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */
40772 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ27_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ27_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ27_EN0_MASK)
40773 
40774 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ28_EN0_MASK (0x10000000U)
40775 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ28_EN0_SHIFT (28U)
40776 /*! REQ28_EN0 - Writing a 1 to REQ28_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */
40777 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ28_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ28_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ28_EN0_MASK)
40778 
40779 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ29_EN0_MASK (0x20000000U)
40780 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ29_EN0_SHIFT (29U)
40781 /*! REQ29_EN0 - Writing a 1 to REQ29_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */
40782 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ29_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ29_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ29_EN0_MASK)
40783 
40784 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ30_EN0_MASK (0x40000000U)
40785 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ30_EN0_SHIFT (30U)
40786 /*! REQ30_EN0 - Writing a 1 to REQ30_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */
40787 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ30_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ30_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ30_EN0_MASK)
40788 
40789 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ31_EN0_MASK (0x80000000U)
40790 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ31_EN0_SHIFT (31U)
40791 /*! REQ31_EN0 - Writing a 1 to REQ31_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */
40792 #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ31_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ31_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ31_EN0_MASK)
40793 /*! @} */
40794 
40795 /*! @name DMA0_REQ_ENABLE0_TOG - DMA0 Request Enable0 */
40796 /*! @{ */
40797 
40798 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ1_EN0_MASK (0x2U)
40799 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ1_EN0_SHIFT (1U)
40800 /*! REQ1_EN0 - Writing a 1 to REQ1_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */
40801 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ1_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ1_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ1_EN0_MASK)
40802 
40803 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ2_EN0_MASK (0x4U)
40804 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ2_EN0_SHIFT (2U)
40805 /*! REQ2_EN0 - Writing a 1 to REQ2_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */
40806 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ2_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ2_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ2_EN0_MASK)
40807 
40808 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ3_EN0_MASK (0x8U)
40809 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ3_EN0_SHIFT (3U)
40810 /*! REQ3_EN0 - Writing a 1 to REQ3_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */
40811 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ3_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ3_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ3_EN0_MASK)
40812 
40813 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ4_EN0_MASK (0x10U)
40814 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ4_EN0_SHIFT (4U)
40815 /*! REQ4_EN0 - Writing a 1 to REQ4_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */
40816 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ4_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ4_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ4_EN0_MASK)
40817 
40818 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ5_EN0_MASK (0x20U)
40819 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ5_EN0_SHIFT (5U)
40820 /*! REQ5_EN0 - Writing a 1 to REQ5_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */
40821 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ5_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ5_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ5_EN0_MASK)
40822 
40823 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ6_EN0_MASK (0x40U)
40824 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ6_EN0_SHIFT (6U)
40825 /*! REQ6_EN0 - Writing a 1 to REQ6_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */
40826 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ6_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ6_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ6_EN0_MASK)
40827 
40828 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ7_EN0_MASK (0x80U)
40829 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ7_EN0_SHIFT (7U)
40830 /*! REQ7_EN0 - Writing a 1 to REQ7_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */
40831 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ7_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ7_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ7_EN0_MASK)
40832 
40833 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ8_EN0_MASK (0x100U)
40834 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ8_EN0_SHIFT (8U)
40835 /*! REQ8_EN0 - Writing a 1 to REQ8_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */
40836 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ8_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ8_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ8_EN0_MASK)
40837 
40838 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ9_EN0_MASK (0x200U)
40839 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ9_EN0_SHIFT (9U)
40840 /*! REQ9_EN0 - Writing a 1 to RE9_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */
40841 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ9_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ9_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ9_EN0_MASK)
40842 
40843 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ10_EN0_MASK (0x400U)
40844 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ10_EN0_SHIFT (10U)
40845 /*! REQ10_EN0 - Writing a 1 to REQ10_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */
40846 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ10_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ10_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ10_EN0_MASK)
40847 
40848 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ11_EN0_MASK (0x800U)
40849 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ11_EN0_SHIFT (11U)
40850 /*! REQ11_EN0 - Writing a 1 to REQ11_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */
40851 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ11_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ11_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ11_EN0_MASK)
40852 
40853 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ12_EN0_MASK (0x1000U)
40854 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ12_EN0_SHIFT (12U)
40855 /*! REQ12_EN0 - Writing a 1 to REQ12_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */
40856 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ12_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ12_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ12_EN0_MASK)
40857 
40858 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ13_EN0_MASK (0x2000U)
40859 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ13_EN0_SHIFT (13U)
40860 /*! REQ13_EN0 - Writing a 1 to REQ13_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */
40861 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ13_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ13_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ13_EN0_MASK)
40862 
40863 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ14_EN0_MASK (0x4000U)
40864 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ14_EN0_SHIFT (14U)
40865 /*! REQ14_EN0 - Writing a 1 to REQ14_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */
40866 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ14_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ14_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ14_EN0_MASK)
40867 
40868 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ15_EN0_MASK (0x8000U)
40869 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ15_EN0_SHIFT (15U)
40870 /*! REQ15_EN0 - Writing a 1 to REQ15_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */
40871 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ15_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ15_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ15_EN0_MASK)
40872 
40873 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ16_EN0_MASK (0x10000U)
40874 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ16_EN0_SHIFT (16U)
40875 /*! REQ16_EN0 - Writing a 1 to REQ16_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */
40876 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ16_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ16_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ16_EN0_MASK)
40877 
40878 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ17_EN0_MASK (0x20000U)
40879 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ17_EN0_SHIFT (17U)
40880 /*! REQ17_EN0 - Writing a 1 to REQ17_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */
40881 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ17_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ17_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ17_EN0_MASK)
40882 
40883 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ18_EN0_MASK (0x40000U)
40884 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ18_EN0_SHIFT (18U)
40885 /*! REQ18_EN0 - Writing a 1 to REQ18_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */
40886 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ18_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ18_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ18_EN0_MASK)
40887 
40888 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ19_EN0_MASK (0x80000U)
40889 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ19_EN0_SHIFT (19U)
40890 /*! REQ19_EN0 - Writing a 1 to REQ19_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */
40891 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ19_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ19_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ19_EN0_MASK)
40892 
40893 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ20_EN0_MASK (0x100000U)
40894 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ20_EN0_SHIFT (20U)
40895 /*! REQ20_EN0 - Writing a 1 to REQ20_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */
40896 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ20_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ20_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ20_EN0_MASK)
40897 
40898 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ21_EN0_MASK (0x200000U)
40899 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ21_EN0_SHIFT (21U)
40900 /*! REQ21_EN0 - Writing a 1 to REQ21_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */
40901 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ21_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ21_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ21_EN0_MASK)
40902 
40903 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ22_EN0_MASK (0x400000U)
40904 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ22_EN0_SHIFT (22U)
40905 /*! REQ22_EN0 - Writing a 1 to REQ22_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */
40906 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ22_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ22_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ22_EN0_MASK)
40907 
40908 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ23_EN0_MASK (0x800000U)
40909 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ23_EN0_SHIFT (23U)
40910 /*! REQ23_EN0 - Writing a 1 to REQ23_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */
40911 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ23_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ23_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ23_EN0_MASK)
40912 
40913 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ24_EN0_MASK (0x1000000U)
40914 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ24_EN0_SHIFT (24U)
40915 /*! REQ24_EN0 - Writing a 1 to REQ24_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */
40916 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ24_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ24_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ24_EN0_MASK)
40917 
40918 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ25_EN0_MASK (0x2000000U)
40919 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ25_EN0_SHIFT (25U)
40920 /*! REQ25_EN0 - Writing a 1 to REQ25_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */
40921 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ25_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ25_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ25_EN0_MASK)
40922 
40923 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ26_EN0_MASK (0x4000000U)
40924 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ26_EN0_SHIFT (26U)
40925 /*! REQ26_EN0 - Writing a 1 to REQ26_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */
40926 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ26_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ26_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ26_EN0_MASK)
40927 
40928 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ27_EN0_MASK (0x8000000U)
40929 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ27_EN0_SHIFT (27U)
40930 /*! REQ27_EN0 - Writing a 1 to REQ27_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */
40931 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ27_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ27_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ27_EN0_MASK)
40932 
40933 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ28_EN0_MASK (0x10000000U)
40934 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ28_EN0_SHIFT (28U)
40935 /*! REQ28_EN0 - Writing a 1 to REQ28_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */
40936 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ28_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ28_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ28_EN0_MASK)
40937 
40938 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ29_EN0_MASK (0x20000000U)
40939 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ29_EN0_SHIFT (29U)
40940 /*! REQ29_EN0 - Writing a 1 to REQ29_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */
40941 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ29_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ29_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ29_EN0_MASK)
40942 
40943 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ30_EN0_MASK (0x40000000U)
40944 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ30_EN0_SHIFT (30U)
40945 /*! REQ30_EN0 - Writing a 1 to REQ30_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */
40946 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ30_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ30_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ30_EN0_MASK)
40947 
40948 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ31_EN0_MASK (0x80000000U)
40949 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ31_EN0_SHIFT (31U)
40950 /*! REQ31_EN0 - Writing a 1 to REQ31_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */
40951 #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ31_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ31_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ31_EN0_MASK)
40952 /*! @} */
40953 
40954 /*! @name DMA0_REQ_ENABLE1 - DMA0 Request Enable1 */
40955 /*! @{ */
40956 
40957 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ32_EN0_MASK (0x1U)
40958 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ32_EN0_SHIFT (0U)
40959 /*! REQ32_EN0 - This register is used to enable and disable EVTG0 OUT0B request.
40960  *  0b0..Disable
40961  *  0b1..Enable
40962  */
40963 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ32_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ32_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ32_EN0_MASK)
40964 
40965 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ33_EN0_MASK (0x2U)
40966 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ33_EN0_SHIFT (1U)
40967 /*! REQ33_EN0 - This register is used to enable and disable EVTG0 OUT1A request.
40968  *  0b0..Disable
40969  *  0b1..Enable
40970  */
40971 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ33_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ33_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ33_EN0_MASK)
40972 
40973 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ34_EN0_MASK (0x4U)
40974 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ34_EN0_SHIFT (2U)
40975 /*! REQ34_EN0 - This register is used to enable and disable EVTG0 OUT1B request.
40976  *  0b0..Disable
40977  *  0b1..Enable
40978  */
40979 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ34_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ34_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ34_EN0_MASK)
40980 
40981 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ35_EN0_MASK (0x8U)
40982 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ35_EN0_SHIFT (3U)
40983 /*! REQ35_EN0 - This register is used to enable and disable EVTG0 OUT2A request.
40984  *  0b0..Disable
40985  *  0b1..Enable
40986  */
40987 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ35_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ35_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ35_EN0_MASK)
40988 
40989 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ36_EN0_MASK (0x10U)
40990 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ36_EN0_SHIFT (4U)
40991 /*! REQ36_EN0 - This register is used to enable and disable EVTG0 OUT2B request.
40992  *  0b0..Disable
40993  *  0b1..Enable
40994  */
40995 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ36_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ36_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ36_EN0_MASK)
40996 
40997 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ37_EN0_MASK (0x20U)
40998 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ37_EN0_SHIFT (5U)
40999 /*! REQ37_EN0 - This register is used to enable and disable EVTG0 OUT3A request.
41000  *  0b0..Disable
41001  *  0b1..Enable
41002  */
41003 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ37_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ37_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ37_EN0_MASK)
41004 
41005 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ38_EN0_MASK (0x40U)
41006 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ38_EN0_SHIFT (6U)
41007 /*! REQ38_EN0 - This register is used to enable and disable EVTG0 OUT3B request.
41008  *  0b0..Disable
41009  *  0b1..Enable
41010  */
41011 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ38_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ38_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ38_EN0_MASK)
41012 
41013 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ39_EN0_MASK (0x80U)
41014 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ39_EN0_SHIFT (7U)
41015 /*! REQ39_EN0 - This register is used to enable and disable PWM0 Req_capt0 request.
41016  *  0b0..Disable
41017  *  0b1..Enable
41018  */
41019 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ39_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ39_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ39_EN0_MASK)
41020 
41021 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ40_EN0_MASK (0x100U)
41022 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ40_EN0_SHIFT (8U)
41023 /*! REQ40_EN0 - This register is used to enable and disable PWM0 Req_capt1 request.
41024  *  0b0..Disable
41025  *  0b1..Enable
41026  */
41027 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ40_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ40_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ40_EN0_MASK)
41028 
41029 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ41_EN0_MASK (0x200U)
41030 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ41_EN0_SHIFT (9U)
41031 /*! REQ41_EN0 - This register is used to enable and disable PWM0 Req_capt2 request.
41032  *  0b0..Disable
41033  *  0b1..Enable
41034  */
41035 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ41_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ41_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ41_EN0_MASK)
41036 
41037 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ42_EN0_MASK (0x400U)
41038 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ42_EN0_SHIFT (10U)
41039 /*! REQ42_EN0 - This register is used to enable and disable PWM0 Req_capt3 request.
41040  *  0b0..Disable
41041  *  0b1..Enable
41042  */
41043 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ42_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ42_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ42_EN0_MASK)
41044 
41045 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ43_EN0_MASK (0x800U)
41046 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ43_EN0_SHIFT (11U)
41047 /*! REQ43_EN0 - This register is used to enable and disable PWM0 Req_val0 request.
41048  *  0b0..Disable
41049  *  0b1..Enable
41050  */
41051 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ43_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ43_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ43_EN0_MASK)
41052 
41053 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ44_EN0_MASK (0x1000U)
41054 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ44_EN0_SHIFT (12U)
41055 /*! REQ44_EN0 - This register is used to enable and disable PWM0 Req_val1 request.
41056  *  0b0..Disable
41057  *  0b1..Enable
41058  */
41059 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ44_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ44_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ44_EN0_MASK)
41060 
41061 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ45_EN0_MASK (0x2000U)
41062 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ45_EN0_SHIFT (13U)
41063 /*! REQ45_EN0 - This register is used to enable and disable PWM0 Req_val2 request.
41064  *  0b0..Disable
41065  *  0b1..Enable
41066  */
41067 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ45_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ45_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ45_EN0_MASK)
41068 
41069 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ46_EN0_MASK (0x4000U)
41070 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ46_EN0_SHIFT (14U)
41071 /*! REQ46_EN0 - This register is used to enable and disable PWM0 Req_val3 request.
41072  *  0b0..Disable
41073  *  0b1..Enable
41074  */
41075 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ46_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ46_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ46_EN0_MASK)
41076 
41077 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ47_EN0_MASK (0x8000U)
41078 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ47_EN0_SHIFT (15U)
41079 /*! REQ47_EN0 - This register is used to enable and disable PWM1 Req_capt0 request.
41080  *  0b0..Disable
41081  *  0b1..Enable
41082  */
41083 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ47_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ47_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ47_EN0_MASK)
41084 
41085 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ48_EN0_MASK (0x10000U)
41086 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ48_EN0_SHIFT (16U)
41087 /*! REQ48_EN0 - This register is used to enable and disable PWM1 Req_capt1 request.
41088  *  0b0..Disable
41089  *  0b1..Enable
41090  */
41091 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ48_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ48_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ48_EN0_MASK)
41092 
41093 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ49_EN0_MASK (0x20000U)
41094 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ49_EN0_SHIFT (17U)
41095 /*! REQ49_EN0 - This register is used to enable and disable PWM1 Req_capt2 request.
41096  *  0b0..Disable
41097  *  0b1..Enable
41098  */
41099 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ49_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ49_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ49_EN0_MASK)
41100 
41101 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ50_EN0_MASK (0x40000U)
41102 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ50_EN0_SHIFT (18U)
41103 /*! REQ50_EN0 - This register is used to enable and disable PWM1 Req_capt3 request.
41104  *  0b0..Disable
41105  *  0b1..Enable
41106  */
41107 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ50_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ50_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ50_EN0_MASK)
41108 
41109 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ51_EN0_MASK (0x80000U)
41110 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ51_EN0_SHIFT (19U)
41111 /*! REQ51_EN0 - This register is used to enable and disable PWM1 Req_val0 request.
41112  *  0b0..Disable
41113  *  0b1..Enable
41114  */
41115 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ51_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ51_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ51_EN0_MASK)
41116 
41117 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ52_EN0_MASK (0x100000U)
41118 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ52_EN0_SHIFT (20U)
41119 /*! REQ52_EN0 - This register is used to enable and disable PWM1 Req_val1 request.
41120  *  0b0..Disable
41121  *  0b1..Enable
41122  */
41123 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ52_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ52_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ52_EN0_MASK)
41124 
41125 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ53_EN0_MASK (0x200000U)
41126 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ53_EN0_SHIFT (21U)
41127 /*! REQ53_EN0 - This register is used to enable and disable PWM1 Req_val2 request.
41128  *  0b0..Disable
41129  *  0b1..Enable
41130  */
41131 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ53_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ53_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ53_EN0_MASK)
41132 
41133 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ54_EN0_MASK (0x400000U)
41134 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ54_EN0_SHIFT (22U)
41135 /*! REQ54_EN0 - This register is used to enable and disable PWM1 Req_val3 request.
41136  *  0b0..Disable
41137  *  0b1..Enable
41138  */
41139 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ54_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ54_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ54_EN0_MASK)
41140 
41141 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ57_EN0_MASK (0x2000000U)
41142 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ57_EN0_SHIFT (25U)
41143 /*! REQ57_EN0 - This register is used to enable and disable LPTMR0 counter match event request.
41144  *  0b0..Disable
41145  *  0b1..Enable
41146  */
41147 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ57_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ57_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ57_EN0_MASK)
41148 
41149 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ58_EN0_MASK (0x4000000U)
41150 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ58_EN0_SHIFT (26U)
41151 /*! REQ58_EN0 - This register is used to enable and disable LPTMR1 counter match event request.
41152  *  0b0..Disable
41153  *  0b1..Enable
41154  */
41155 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ58_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ58_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ58_EN0_MASK)
41156 
41157 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ59_EN0_MASK (0x8000000U)
41158 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ59_EN0_SHIFT (27U)
41159 /*! REQ59_EN0 - This register is used to enable and disable CAN0 DMA request.
41160  *  0b0..Disable
41161  *  0b1..Enable
41162  */
41163 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ59_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ59_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ59_EN0_MASK)
41164 
41165 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ60_EN0_MASK (0x10000000U)
41166 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ60_EN0_SHIFT (28U)
41167 /*! REQ60_EN0 - This register is used to enable and disable CAN1 DMA request.
41168  *  0b0..Disable
41169  *  0b1..Enable
41170  */
41171 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ60_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ60_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ60_EN0_MASK)
41172 
41173 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ61_EN0_MASK (0x20000000U)
41174 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ61_EN0_SHIFT (29U)
41175 /*! REQ61_EN0 - This register is used to enable and disable FlexIO0 Shifter0 Status DMA request OR Timer0 Status DMA request.
41176  *  0b0..Disable
41177  *  0b1..Enable
41178  */
41179 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ61_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ61_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ61_EN0_MASK)
41180 
41181 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ62_EN0_MASK (0x40000000U)
41182 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ62_EN0_SHIFT (30U)
41183 /*! REQ62_EN0 - This register is used to enable and disable FlexIO0 Shifter1 Status DMA request OR Timer1 Status DMA request.
41184  *  0b0..Disable
41185  *  0b1..Enable
41186  */
41187 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ62_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ62_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ62_EN0_MASK)
41188 
41189 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ63_EN0_MASK (0x80000000U)
41190 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ63_EN0_SHIFT (31U)
41191 /*! REQ63_EN0 - This register is used to enable and disable FlexIO0 Shifter2 Status DMA request OR Timer2 Status DMA request.
41192  *  0b0..Disable
41193  *  0b1..Enable
41194  */
41195 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ63_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ63_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ63_EN0_MASK)
41196 /*! @} */
41197 
41198 /*! @name DMA0_REQ_ENABLE1_SET - DMA0 Request Enable1 */
41199 /*! @{ */
41200 
41201 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ32_EN0_MASK (0x1U)
41202 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ32_EN0_SHIFT (0U)
41203 /*! REQ32_EN0 - Writing a 1 to REQ32_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */
41204 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ32_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ32_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ32_EN0_MASK)
41205 
41206 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ33_EN0_MASK (0x2U)
41207 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ33_EN0_SHIFT (1U)
41208 /*! REQ33_EN0 - Writing a 1 to REQ33_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */
41209 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ33_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ33_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ33_EN0_MASK)
41210 
41211 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ34_EN0_MASK (0x4U)
41212 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ34_EN0_SHIFT (2U)
41213 /*! REQ34_EN0 - Writing a 1 to REQ34_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */
41214 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ34_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ34_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ34_EN0_MASK)
41215 
41216 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ35_EN0_MASK (0x8U)
41217 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ35_EN0_SHIFT (3U)
41218 /*! REQ35_EN0 - Writing a 1 to REQ35_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */
41219 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ35_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ35_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ35_EN0_MASK)
41220 
41221 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ36_EN0_MASK (0x10U)
41222 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ36_EN0_SHIFT (4U)
41223 /*! REQ36_EN0 - Writing a 1 to REQ36_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */
41224 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ36_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ36_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ36_EN0_MASK)
41225 
41226 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ37_EN0_MASK (0x20U)
41227 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ37_EN0_SHIFT (5U)
41228 /*! REQ37_EN0 - Writing a 1 to REQ37_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */
41229 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ37_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ37_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ37_EN0_MASK)
41230 
41231 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ38_EN0_MASK (0x40U)
41232 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ38_EN0_SHIFT (6U)
41233 /*! REQ38_EN0 - Writing a 1 to REQ38_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */
41234 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ38_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ38_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ38_EN0_MASK)
41235 
41236 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ39_EN0_MASK (0x80U)
41237 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ39_EN0_SHIFT (7U)
41238 /*! REQ39_EN0 - Writing a 1 to REQ39_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */
41239 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ39_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ39_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ39_EN0_MASK)
41240 
41241 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ40_EN0_MASK (0x100U)
41242 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ40_EN0_SHIFT (8U)
41243 /*! REQ40_EN0 - Writing a 1 to REQ40_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */
41244 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ40_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ40_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ40_EN0_MASK)
41245 
41246 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ41_EN0_MASK (0x200U)
41247 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ41_EN0_SHIFT (9U)
41248 /*! REQ41_EN0 - Writing a 1 to REQ41_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */
41249 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ41_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ41_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ41_EN0_MASK)
41250 
41251 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ42_EN0_MASK (0x400U)
41252 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ42_EN0_SHIFT (10U)
41253 /*! REQ42_EN0 - Writing a 1 to REQ42_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */
41254 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ42_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ42_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ42_EN0_MASK)
41255 
41256 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ43_EN0_MASK (0x800U)
41257 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ43_EN0_SHIFT (11U)
41258 /*! REQ43_EN0 - Writing a 1 to REQ43_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */
41259 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ43_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ43_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ43_EN0_MASK)
41260 
41261 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ44_EN0_MASK (0x1000U)
41262 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ44_EN0_SHIFT (12U)
41263 /*! REQ44_EN0 - Writing a 1 to REQ44_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */
41264 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ44_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ44_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ44_EN0_MASK)
41265 
41266 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ45_EN0_MASK (0x2000U)
41267 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ45_EN0_SHIFT (13U)
41268 /*! REQ45_EN0 - Writing a 1 to REQ45_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */
41269 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ45_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ45_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ45_EN0_MASK)
41270 
41271 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ46_EN0_MASK (0x4000U)
41272 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ46_EN0_SHIFT (14U)
41273 /*! REQ46_EN0 - Writing a 1 to REQ46_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */
41274 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ46_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ46_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ46_EN0_MASK)
41275 
41276 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ47_EN0_MASK (0x8000U)
41277 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ47_EN0_SHIFT (15U)
41278 /*! REQ47_EN0 - Writing a 1 to REQ47_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */
41279 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ47_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ47_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ47_EN0_MASK)
41280 
41281 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ48_EN0_MASK (0x10000U)
41282 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ48_EN0_SHIFT (16U)
41283 /*! REQ48_EN0 - Writing a 1 to REQ48_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */
41284 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ48_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ48_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ48_EN0_MASK)
41285 
41286 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ49_EN0_MASK (0x20000U)
41287 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ49_EN0_SHIFT (17U)
41288 /*! REQ49_EN0 - Writing a 1 to REQ49_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */
41289 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ49_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ49_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ49_EN0_MASK)
41290 
41291 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ50_EN0_MASK (0x40000U)
41292 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ50_EN0_SHIFT (18U)
41293 /*! REQ50_EN0 - Writing a 1 to REQ50_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */
41294 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ50_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ50_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ50_EN0_MASK)
41295 
41296 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ51_EN0_MASK (0x80000U)
41297 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ51_EN0_SHIFT (19U)
41298 /*! REQ51_EN0 - Writing a 1 to REQ51_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */
41299 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ51_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ51_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ51_EN0_MASK)
41300 
41301 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ52_EN0_MASK (0x100000U)
41302 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ52_EN0_SHIFT (20U)
41303 /*! REQ52_EN0 - Writing a 1 to REQ52_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */
41304 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ52_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ52_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ52_EN0_MASK)
41305 
41306 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ53_EN0_MASK (0x200000U)
41307 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ53_EN0_SHIFT (21U)
41308 /*! REQ53_EN0 - Writing a 1 to REQ53_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */
41309 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ53_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ53_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ53_EN0_MASK)
41310 
41311 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ54_EN0_MASK (0x400000U)
41312 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ54_EN0_SHIFT (22U)
41313 /*! REQ54_EN0 - Writing a 1 to REQ54_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */
41314 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ54_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ54_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ54_EN0_MASK)
41315 
41316 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ57_EN0_MASK (0x2000000U)
41317 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ57_EN0_SHIFT (25U)
41318 /*! REQ57_EN0 - Writing a 1 to REQ57_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */
41319 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ57_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ57_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ57_EN0_MASK)
41320 
41321 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ58_EN0_MASK (0x4000000U)
41322 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ58_EN0_SHIFT (26U)
41323 /*! REQ58_EN0 - Writing a 1 to REQ58_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */
41324 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ58_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ58_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ58_EN0_MASK)
41325 
41326 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ59_EN0_MASK (0x8000000U)
41327 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ59_EN0_SHIFT (27U)
41328 /*! REQ59_EN0 - Writing a 1 to REQ59_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */
41329 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ59_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ59_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ59_EN0_MASK)
41330 
41331 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ60_EN0_MASK (0x10000000U)
41332 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ60_EN0_SHIFT (28U)
41333 /*! REQ60_EN0 - Writing a 1 to REQ60_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */
41334 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ60_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ60_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ60_EN0_MASK)
41335 
41336 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ61_EN0_MASK (0x20000000U)
41337 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ61_EN0_SHIFT (29U)
41338 /*! REQ61_EN0 - Writing a 1 to REQ61_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */
41339 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ61_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ61_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ61_EN0_MASK)
41340 
41341 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ62_EN0_MASK (0x40000000U)
41342 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ62_EN0_SHIFT (30U)
41343 /*! REQ62_EN0 - Writing a 1 to REQ62_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */
41344 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ62_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ62_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ62_EN0_MASK)
41345 
41346 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ63_EN0_MASK (0x80000000U)
41347 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ63_EN0_SHIFT (31U)
41348 /*! REQ63_EN0 - Writing a 1 to REQ63_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */
41349 #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ63_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ63_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ63_EN0_MASK)
41350 /*! @} */
41351 
41352 /*! @name DMA0_REQ_ENABLE1_CLR - DMA0 Request Enable1 */
41353 /*! @{ */
41354 
41355 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ32_EN0_MASK (0x1U)
41356 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ32_EN0_SHIFT (0U)
41357 /*! REQ32_EN0 - Writing a 1 to REQ32_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */
41358 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ32_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ32_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ32_EN0_MASK)
41359 
41360 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ33_EN0_MASK (0x2U)
41361 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ33_EN0_SHIFT (1U)
41362 /*! REQ33_EN0 - Writing a 1 to REQ33_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */
41363 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ33_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ33_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ33_EN0_MASK)
41364 
41365 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ34_EN0_MASK (0x4U)
41366 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ34_EN0_SHIFT (2U)
41367 /*! REQ34_EN0 - Writing a 1 to REQ34_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */
41368 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ34_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ34_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ34_EN0_MASK)
41369 
41370 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ35_EN0_MASK (0x8U)
41371 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ35_EN0_SHIFT (3U)
41372 /*! REQ35_EN0 - Writing a 1 to REQ35_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */
41373 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ35_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ35_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ35_EN0_MASK)
41374 
41375 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ36_EN0_MASK (0x10U)
41376 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ36_EN0_SHIFT (4U)
41377 /*! REQ36_EN0 - Writing a 1 to REQ36_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */
41378 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ36_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ36_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ36_EN0_MASK)
41379 
41380 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ37_EN0_MASK (0x20U)
41381 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ37_EN0_SHIFT (5U)
41382 /*! REQ37_EN0 - Writing a 1 to REQ37_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */
41383 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ37_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ37_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ37_EN0_MASK)
41384 
41385 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ38_EN0_MASK (0x40U)
41386 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ38_EN0_SHIFT (6U)
41387 /*! REQ38_EN0 - Writing a 1 to REQ38_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */
41388 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ38_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ38_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ38_EN0_MASK)
41389 
41390 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ39_EN0_MASK (0x80U)
41391 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ39_EN0_SHIFT (7U)
41392 /*! REQ39_EN0 - Writing a 1 to REQ39_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */
41393 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ39_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ39_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ39_EN0_MASK)
41394 
41395 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ40_EN0_MASK (0x100U)
41396 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ40_EN0_SHIFT (8U)
41397 /*! REQ40_EN0 - Writing a 1 to REQ40_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */
41398 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ40_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ40_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ40_EN0_MASK)
41399 
41400 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ41_EN0_MASK (0x200U)
41401 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ41_EN0_SHIFT (9U)
41402 /*! REQ41_EN0 - Writing a 1 to REQ41_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */
41403 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ41_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ41_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ41_EN0_MASK)
41404 
41405 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ42_EN0_MASK (0x400U)
41406 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ42_EN0_SHIFT (10U)
41407 /*! REQ42_EN0 - Writing a 1 to REQ42_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */
41408 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ42_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ42_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ42_EN0_MASK)
41409 
41410 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ43_EN0_MASK (0x800U)
41411 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ43_EN0_SHIFT (11U)
41412 /*! REQ43_EN0 - Writing a 1 to REQ43_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */
41413 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ43_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ43_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ43_EN0_MASK)
41414 
41415 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ44_EN0_MASK (0x1000U)
41416 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ44_EN0_SHIFT (12U)
41417 /*! REQ44_EN0 - Writing a 1 to REQ44_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */
41418 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ44_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ44_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ44_EN0_MASK)
41419 
41420 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ45_EN0_MASK (0x2000U)
41421 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ45_EN0_SHIFT (13U)
41422 /*! REQ45_EN0 - Writing a 1 to REQ45_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */
41423 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ45_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ45_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ45_EN0_MASK)
41424 
41425 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ46_EN0_MASK (0x4000U)
41426 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ46_EN0_SHIFT (14U)
41427 /*! REQ46_EN0 - Writing a 1 to REQ46_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */
41428 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ46_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ46_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ46_EN0_MASK)
41429 
41430 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ47_EN0_MASK (0x8000U)
41431 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ47_EN0_SHIFT (15U)
41432 /*! REQ47_EN0 - Writing a 1 to REQ47_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */
41433 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ47_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ47_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ47_EN0_MASK)
41434 
41435 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ48_EN0_MASK (0x10000U)
41436 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ48_EN0_SHIFT (16U)
41437 /*! REQ48_EN0 - Writing a 1 to REQ48_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */
41438 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ48_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ48_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ48_EN0_MASK)
41439 
41440 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ49_EN0_MASK (0x20000U)
41441 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ49_EN0_SHIFT (17U)
41442 /*! REQ49_EN0 - Writing a 1 to REQ49_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */
41443 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ49_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ49_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ49_EN0_MASK)
41444 
41445 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ50_EN0_MASK (0x40000U)
41446 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ50_EN0_SHIFT (18U)
41447 /*! REQ50_EN0 - Writing a 1 to REQ50_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */
41448 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ50_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ50_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ50_EN0_MASK)
41449 
41450 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ51_EN0_MASK (0x80000U)
41451 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ51_EN0_SHIFT (19U)
41452 /*! REQ51_EN0 - Writing a 1 to REQ51_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */
41453 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ51_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ51_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ51_EN0_MASK)
41454 
41455 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ52_EN0_MASK (0x100000U)
41456 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ52_EN0_SHIFT (20U)
41457 /*! REQ52_EN0 - Writing a 1 to REQ52_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */
41458 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ52_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ52_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ52_EN0_MASK)
41459 
41460 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ53_EN0_MASK (0x200000U)
41461 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ53_EN0_SHIFT (21U)
41462 /*! REQ53_EN0 - Writing a 1 to REQ53_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */
41463 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ53_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ53_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ53_EN0_MASK)
41464 
41465 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ54_EN0_MASK (0x400000U)
41466 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ54_EN0_SHIFT (22U)
41467 /*! REQ54_EN0 - Writing a 1 to REQ54_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */
41468 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ54_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ54_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ54_EN0_MASK)
41469 
41470 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ57_EN0_MASK (0x2000000U)
41471 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ57_EN0_SHIFT (25U)
41472 /*! REQ57_EN0 - Writing a 1 to REQ57_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */
41473 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ57_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ57_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ57_EN0_MASK)
41474 
41475 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ58_EN0_MASK (0x4000000U)
41476 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ58_EN0_SHIFT (26U)
41477 /*! REQ58_EN0 - Writing a 1 to REQ58_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */
41478 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ58_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ58_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ58_EN0_MASK)
41479 
41480 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ59_EN0_MASK (0x8000000U)
41481 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ59_EN0_SHIFT (27U)
41482 /*! REQ59_EN0 - Writing a 1 to REQ59_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */
41483 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ59_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ59_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ59_EN0_MASK)
41484 
41485 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ60_EN0_MASK (0x10000000U)
41486 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ60_EN0_SHIFT (28U)
41487 /*! REQ60_EN0 - Writing a 1 to REQ60_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */
41488 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ60_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ60_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ60_EN0_MASK)
41489 
41490 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ61_EN0_MASK (0x20000000U)
41491 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ61_EN0_SHIFT (29U)
41492 /*! REQ61_EN0 - Writing a 1 to REQ61_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */
41493 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ61_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ61_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ61_EN0_MASK)
41494 
41495 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ62_EN0_MASK (0x40000000U)
41496 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ62_EN0_SHIFT (30U)
41497 /*! REQ62_EN0 - Writing a 1 to REQ62_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */
41498 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ62_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ62_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ62_EN0_MASK)
41499 
41500 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ63_EN0_MASK (0x80000000U)
41501 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ63_EN0_SHIFT (31U)
41502 /*! REQ63_EN0 - Writing a 1 to REQ63_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */
41503 #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ63_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ63_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ63_EN0_MASK)
41504 /*! @} */
41505 
41506 /*! @name DMA0_REQ_ENABLE1_TOG - DMA0 Request Enable1 */
41507 /*! @{ */
41508 
41509 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ32_EN0_MASK (0x1U)
41510 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ32_EN0_SHIFT (0U)
41511 /*! REQ32_EN0 - Writing a 1 to REQ32_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */
41512 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ32_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ32_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ32_EN0_MASK)
41513 
41514 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ33_EN0_MASK (0x2U)
41515 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ33_EN0_SHIFT (1U)
41516 /*! REQ33_EN0 - Writing a 1 to REQ33_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */
41517 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ33_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ33_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ33_EN0_MASK)
41518 
41519 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ34_EN0_MASK (0x4U)
41520 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ34_EN0_SHIFT (2U)
41521 /*! REQ34_EN0 - Writing a 1 to REQ34_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */
41522 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ34_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ34_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ34_EN0_MASK)
41523 
41524 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ35_EN0_MASK (0x8U)
41525 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ35_EN0_SHIFT (3U)
41526 /*! REQ35_EN0 - Writing a 1 to REQ35_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */
41527 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ35_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ35_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ35_EN0_MASK)
41528 
41529 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ36_EN0_MASK (0x10U)
41530 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ36_EN0_SHIFT (4U)
41531 /*! REQ36_EN0 - Writing a 1 to REQ36_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */
41532 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ36_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ36_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ36_EN0_MASK)
41533 
41534 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ37_EN0_MASK (0x20U)
41535 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ37_EN0_SHIFT (5U)
41536 /*! REQ37_EN0 - Writing a 1 to REQ37_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */
41537 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ37_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ37_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ37_EN0_MASK)
41538 
41539 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ38_EN0_MASK (0x40U)
41540 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ38_EN0_SHIFT (6U)
41541 /*! REQ38_EN0 - Writing a 1 to REQ38_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */
41542 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ38_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ38_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ38_EN0_MASK)
41543 
41544 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ39_EN0_MASK (0x80U)
41545 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ39_EN0_SHIFT (7U)
41546 /*! REQ39_EN0 - Writing a 1 to REQ39_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */
41547 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ39_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ39_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ39_EN0_MASK)
41548 
41549 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ40_EN0_MASK (0x100U)
41550 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ40_EN0_SHIFT (8U)
41551 /*! REQ40_EN0 - Writing a 1 to REQ40_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */
41552 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ40_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ40_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ40_EN0_MASK)
41553 
41554 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ41_EN0_MASK (0x200U)
41555 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ41_EN0_SHIFT (9U)
41556 /*! REQ41_EN0 - Writing a 1 to REQ41_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */
41557 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ41_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ41_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ41_EN0_MASK)
41558 
41559 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ42_EN0_MASK (0x400U)
41560 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ42_EN0_SHIFT (10U)
41561 /*! REQ42_EN0 - Writing a 1 to REQ42_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */
41562 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ42_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ42_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ42_EN0_MASK)
41563 
41564 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ43_EN0_MASK (0x800U)
41565 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ43_EN0_SHIFT (11U)
41566 /*! REQ43_EN0 - Writing a 1 to REQ43_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */
41567 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ43_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ43_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ43_EN0_MASK)
41568 
41569 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ44_EN0_MASK (0x1000U)
41570 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ44_EN0_SHIFT (12U)
41571 /*! REQ44_EN0 - Writing a 1 to REQ44_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */
41572 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ44_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ44_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ44_EN0_MASK)
41573 
41574 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ45_EN0_MASK (0x2000U)
41575 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ45_EN0_SHIFT (13U)
41576 /*! REQ45_EN0 - Writing a 1 to REQ55_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */
41577 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ45_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ45_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ45_EN0_MASK)
41578 
41579 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ46_EN0_MASK (0x4000U)
41580 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ46_EN0_SHIFT (14U)
41581 /*! REQ46_EN0 - Writing a 1 to REQ46_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */
41582 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ46_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ46_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ46_EN0_MASK)
41583 
41584 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ47_EN0_MASK (0x8000U)
41585 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ47_EN0_SHIFT (15U)
41586 /*! REQ47_EN0 - Writing a 1 to REQ47_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */
41587 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ47_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ47_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ47_EN0_MASK)
41588 
41589 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ48_EN0_MASK (0x10000U)
41590 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ48_EN0_SHIFT (16U)
41591 /*! REQ48_EN0 - Writing a 1 to REQ48_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */
41592 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ48_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ48_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ48_EN0_MASK)
41593 
41594 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ49_EN0_MASK (0x20000U)
41595 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ49_EN0_SHIFT (17U)
41596 /*! REQ49_EN0 - Writing a 1 to REQ49_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */
41597 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ49_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ49_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ49_EN0_MASK)
41598 
41599 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ50_EN0_MASK (0x40000U)
41600 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ50_EN0_SHIFT (18U)
41601 /*! REQ50_EN0 - Writing a 1 to REQ50_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */
41602 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ50_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ50_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ50_EN0_MASK)
41603 
41604 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ51_EN0_MASK (0x80000U)
41605 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ51_EN0_SHIFT (19U)
41606 /*! REQ51_EN0 - Writing a 1 to REQ51_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */
41607 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ51_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ51_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ51_EN0_MASK)
41608 
41609 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ52_EN0_MASK (0x100000U)
41610 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ52_EN0_SHIFT (20U)
41611 /*! REQ52_EN0 - Writing a 1 to REQ52_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */
41612 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ52_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ52_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ52_EN0_MASK)
41613 
41614 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ53_EN0_MASK (0x200000U)
41615 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ53_EN0_SHIFT (21U)
41616 /*! REQ53_EN0 - Writing a 1 to REQ53_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */
41617 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ53_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ53_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ53_EN0_MASK)
41618 
41619 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ54_EN0_MASK (0x400000U)
41620 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ54_EN0_SHIFT (22U)
41621 /*! REQ54_EN0 - Writing a 1 to REQ54_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */
41622 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ54_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ54_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ54_EN0_MASK)
41623 
41624 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ57_EN0_MASK (0x2000000U)
41625 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ57_EN0_SHIFT (25U)
41626 /*! REQ57_EN0 - Writing a 1 to REQ57_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */
41627 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ57_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ57_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ57_EN0_MASK)
41628 
41629 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ58_EN0_MASK (0x4000000U)
41630 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ58_EN0_SHIFT (26U)
41631 /*! REQ58_EN0 - Writing a 1 to REQ58_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */
41632 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ58_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ58_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ58_EN0_MASK)
41633 
41634 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ59_EN0_MASK (0x8000000U)
41635 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ59_EN0_SHIFT (27U)
41636 /*! REQ59_EN0 - Writing a 1 to REQ59_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */
41637 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ59_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ59_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ59_EN0_MASK)
41638 
41639 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ60_EN0_MASK (0x10000000U)
41640 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ60_EN0_SHIFT (28U)
41641 /*! REQ60_EN0 - Writing a 1 to REQ60_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */
41642 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ60_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ60_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ60_EN0_MASK)
41643 
41644 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ61_EN0_MASK (0x20000000U)
41645 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ61_EN0_SHIFT (29U)
41646 /*! REQ61_EN0 - Writing a 1 to REQ61_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */
41647 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ61_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ61_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ61_EN0_MASK)
41648 
41649 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ62_EN0_MASK (0x40000000U)
41650 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ62_EN0_SHIFT (30U)
41651 /*! REQ62_EN0 - Writing a 1 to REQ62_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */
41652 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ62_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ62_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ62_EN0_MASK)
41653 
41654 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ63_EN0_MASK (0x80000000U)
41655 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ63_EN0_SHIFT (31U)
41656 /*! REQ63_EN0 - Writing a 1 to REQ63_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */
41657 #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ63_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ63_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ63_EN0_MASK)
41658 /*! @} */
41659 
41660 /*! @name DMA0_REQ_ENABLE2 - DMA0 Request Enable2 */
41661 /*! @{ */
41662 
41663 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ64_EN0_MASK (0x1U)
41664 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ64_EN0_SHIFT (0U)
41665 /*! REQ64_EN0 - This register is used to enable and disable FlexIO0 shift register 3 request.
41666  *  0b0..Disable
41667  *  0b1..Enable
41668  */
41669 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ64_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ64_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ64_EN0_MASK)
41670 
41671 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ65_EN0_MASK (0x2U)
41672 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ65_EN0_SHIFT (1U)
41673 /*! REQ65_EN0 - This register is used to enable and disable FlexIO0 shift register 4 request.
41674  *  0b0..Disable
41675  *  0b1..Enable
41676  */
41677 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ65_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ65_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ65_EN0_MASK)
41678 
41679 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ66_EN0_MASK (0x4U)
41680 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ66_EN0_SHIFT (2U)
41681 /*! REQ66_EN0 - This register is used to enable and disable FlexIO0 shift register 5 request.
41682  *  0b0..Disable
41683  *  0b1..Enable
41684  */
41685 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ66_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ66_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ66_EN0_MASK)
41686 
41687 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ67_EN0_MASK (0x8U)
41688 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ67_EN0_SHIFT (3U)
41689 /*! REQ67_EN0 - This register is used to enable and disable FlexIO0 shift register 6 request.
41690  *  0b0..Disable
41691  *  0b1..Enable
41692  */
41693 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ67_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ67_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ67_EN0_MASK)
41694 
41695 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ68_EN0_MASK (0x10U)
41696 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ68_EN0_SHIFT (4U)
41697 /*! REQ68_EN0 - This register is used to enable and disable FlexIO0 shift register 7 request.
41698  *  0b0..Disable
41699  *  0b1..Enable
41700  */
41701 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ68_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ68_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ68_EN0_MASK)
41702 
41703 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ69_EN0_MASK (0x20U)
41704 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ69_EN0_SHIFT (5U)
41705 /*! REQ69_EN0 - This register is used to enable and disable LP_FLEXCOMM0 receive request.
41706  *  0b0..Disable
41707  *  0b1..Enable
41708  */
41709 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ69_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ69_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ69_EN0_MASK)
41710 
41711 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ70_EN0_MASK (0x40U)
41712 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ70_EN0_SHIFT (6U)
41713 /*! REQ70_EN0 - This register is used to enable and disable LP_FLEXCOMM0 transmit request.
41714  *  0b0..Disable
41715  *  0b1..Enable
41716  */
41717 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ70_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ70_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ70_EN0_MASK)
41718 
41719 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ71_EN0_MASK (0x80U)
41720 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ71_EN0_SHIFT (7U)
41721 /*! REQ71_EN0 - This register is used to enable and disable LP_FLEXCOMM1 receive request.
41722  *  0b0..Disable
41723  *  0b1..Enable
41724  */
41725 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ71_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ71_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ71_EN0_MASK)
41726 
41727 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ72_EN0_MASK (0x100U)
41728 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ72_EN0_SHIFT (8U)
41729 /*! REQ72_EN0 - This register is used to enable and disable LP_FLEXCOMM1 transmit request.
41730  *  0b0..Disable
41731  *  0b1..Enable
41732  */
41733 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ72_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ72_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ72_EN0_MASK)
41734 
41735 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ73_EN0_MASK (0x200U)
41736 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ73_EN0_SHIFT (9U)
41737 /*! REQ73_EN0 - This register is used to enable and disable LP_FLEXCOMM2 receive request.
41738  *  0b0..Disable
41739  *  0b1..Enable
41740  */
41741 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ73_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ73_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ73_EN0_MASK)
41742 
41743 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ74_EN0_MASK (0x400U)
41744 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ74_EN0_SHIFT (10U)
41745 /*! REQ74_EN0 - This register is used to enable and disable LP_FLEXCOMM2 transmit request.
41746  *  0b0..Disable
41747  *  0b1..Enable
41748  */
41749 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ74_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ74_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ74_EN0_MASK)
41750 
41751 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ75_EN0_MASK (0x800U)
41752 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ75_EN0_SHIFT (11U)
41753 /*! REQ75_EN0 - This register is used to enable and disable LP_FLEXCOMM3 receive request.
41754  *  0b0..Disable
41755  *  0b1..Enable
41756  */
41757 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ75_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ75_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ75_EN0_MASK)
41758 
41759 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ76_EN0_MASK (0x1000U)
41760 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ76_EN0_SHIFT (12U)
41761 /*! REQ76_EN0 - This register is used to enable and disable LP_FLEXCOMM3 transmit request.
41762  *  0b0..Disable
41763  *  0b1..Enable
41764  */
41765 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ76_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ76_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ76_EN0_MASK)
41766 
41767 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ77_EN0_MASK (0x2000U)
41768 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ77_EN0_SHIFT (13U)
41769 /*! REQ77_EN0 - This register is used to enable and disable LP_FLEXCOMM4 receive request.
41770  *  0b0..Disable
41771  *  0b1..Enable
41772  */
41773 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ77_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ77_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ77_EN0_MASK)
41774 
41775 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ78_EN0_MASK (0x4000U)
41776 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ78_EN0_SHIFT (14U)
41777 /*! REQ78_EN0 - This register is used to enable and disable LP_FLEXCOMM4 transmit request.
41778  *  0b0..Disable
41779  *  0b1..Enable
41780  */
41781 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ78_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ78_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ78_EN0_MASK)
41782 
41783 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ79_EN0_MASK (0x8000U)
41784 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ79_EN0_SHIFT (15U)
41785 /*! REQ79_EN0 - This register is used to enable and disable LP_FLEXCOMM5 receive request.
41786  *  0b0..Disable
41787  *  0b1..Enable
41788  */
41789 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ79_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ79_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ79_EN0_MASK)
41790 
41791 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ80_EN0_MASK (0x10000U)
41792 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ80_EN0_SHIFT (16U)
41793 /*! REQ80_EN0 - This register is used to enable and disable LP_FLEXCOMM5 transmit request.
41794  *  0b0..Disable
41795  *  0b1..Enable
41796  */
41797 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ80_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ80_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ80_EN0_MASK)
41798 
41799 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ81_EN0_MASK (0x20000U)
41800 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ81_EN0_SHIFT (17U)
41801 /*! REQ81_EN0 - This register is used to enable and disable LP_FLEXCOMM6 receive request.
41802  *  0b0..Disable
41803  *  0b1..Enable
41804  */
41805 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ81_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ81_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ81_EN0_MASK)
41806 
41807 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ82_EN0_MASK (0x40000U)
41808 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ82_EN0_SHIFT (18U)
41809 /*! REQ82_EN0 - This register is used to enable and disable LP_FLEXCOMM6 transmit request.
41810  *  0b0..Disable
41811  *  0b1..Enable
41812  */
41813 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ82_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ82_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ82_EN0_MASK)
41814 
41815 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ83_EN0_MASK (0x80000U)
41816 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ83_EN0_SHIFT (19U)
41817 /*! REQ83_EN0 - This register is used to enable and disable LP_FLEXCOMM7 receive request.
41818  *  0b0..Disable
41819  *  0b1..Enable
41820  */
41821 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ83_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ83_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ83_EN0_MASK)
41822 
41823 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ84_EN0_MASK (0x100000U)
41824 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ84_EN0_SHIFT (20U)
41825 /*! REQ84_EN0 - This register is used to enable and disable LP_FLEXCOMM7 transmit request.
41826  *  0b0..Disable
41827  *  0b1..Enable
41828  */
41829 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ84_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ84_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ84_EN0_MASK)
41830 
41831 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ85_EN0_MASK (0x200000U)
41832 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ85_EN0_SHIFT (21U)
41833 /*! REQ85_EN0 - This register is used to enable and disable LP_FLEXCOMM8 receive request.
41834  *  0b0..Disable
41835  *  0b1..Enable
41836  */
41837 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ85_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ85_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ85_EN0_MASK)
41838 
41839 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ86_EN0_MASK (0x400000U)
41840 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ86_EN0_SHIFT (22U)
41841 /*! REQ86_EN0 - This register is used to enable and disable LP_FLEXCOMM8 transmit request.
41842  *  0b0..Disable
41843  *  0b1..Enable
41844  */
41845 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ86_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ86_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ86_EN0_MASK)
41846 
41847 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ87_EN0_MASK (0x800000U)
41848 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ87_EN0_SHIFT (23U)
41849 /*! REQ87_EN0 - This register is used to enable and disable LP_FLEXCOMM9 receive request.
41850  *  0b0..Disable
41851  *  0b1..Enable
41852  */
41853 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ87_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ87_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ87_EN0_MASK)
41854 
41855 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ88_EN0_MASK (0x1000000U)
41856 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ88_EN0_SHIFT (24U)
41857 /*! REQ88_EN0 - This register is used to enable and disable LP_FLEXCOMM9 transmit request.
41858  *  0b0..Disable
41859  *  0b1..Enable
41860  */
41861 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ88_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ88_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ88_EN0_MASK)
41862 
41863 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ91_EN0_MASK (0x8000000U)
41864 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ91_EN0_SHIFT (27U)
41865 /*! REQ91_EN0 - This register is used to enable and disable EMVSIM0 receive request.
41866  *  0b0..Disable
41867  *  0b1..Enable
41868  */
41869 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ91_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ91_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ91_EN0_MASK)
41870 
41871 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ92_EN0_MASK (0x10000000U)
41872 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ92_EN0_SHIFT (28U)
41873 /*! REQ92_EN0 - This register is used to enable and disable EMVSIM0 transmit request.
41874  *  0b0..Disable
41875  *  0b1..Enable
41876  */
41877 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ92_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ92_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ92_EN0_MASK)
41878 
41879 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ93_EN0_MASK (0x20000000U)
41880 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ93_EN0_SHIFT (29U)
41881 /*! REQ93_EN0 - This register is used to enable and disable EMVSIM1 receive request.
41882  *  0b0..Disable
41883  *  0b1..Enable
41884  */
41885 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ93_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ93_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ93_EN0_MASK)
41886 
41887 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ94_EN0_MASK (0x40000000U)
41888 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ94_EN0_SHIFT (30U)
41889 /*! REQ94_EN0 - This register is used to enable and disable EMVSIM1 transmit request.
41890  *  0b0..Disable
41891  *  0b1..Enable
41892  */
41893 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ94_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ94_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ94_EN0_MASK)
41894 
41895 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ95_EN0_MASK (0x80000000U)
41896 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ95_EN0_SHIFT (31U)
41897 /*! REQ95_EN0 - This register is used to enable and disable I3C0 receive request.
41898  *  0b0..Disable
41899  *  0b1..Enable
41900  */
41901 #define INPUTMUX_DMA0_REQ_ENABLE2_REQ95_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ95_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ95_EN0_MASK)
41902 /*! @} */
41903 
41904 /*! @name DMA0_REQ_ENABLE2_SET - DMA0 Request Enable2 */
41905 /*! @{ */
41906 
41907 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ64_EN0_MASK (0x1U)
41908 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ64_EN0_SHIFT (0U)
41909 /*! REQ64_EN0 - Writing a 1 to REQ64_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */
41910 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ64_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ64_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ64_EN0_MASK)
41911 
41912 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ65_EN0_MASK (0x2U)
41913 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ65_EN0_SHIFT (1U)
41914 /*! REQ65_EN0 - Writing a 1 to REQ65_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */
41915 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ65_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ65_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ65_EN0_MASK)
41916 
41917 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ66_EN0_MASK (0x4U)
41918 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ66_EN0_SHIFT (2U)
41919 /*! REQ66_EN0 - Writing a 1 to REQ66_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */
41920 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ66_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ66_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ66_EN0_MASK)
41921 
41922 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ67_EN0_MASK (0x8U)
41923 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ67_EN0_SHIFT (3U)
41924 /*! REQ67_EN0 - Writing a 1 to REQ67_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */
41925 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ67_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ67_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ67_EN0_MASK)
41926 
41927 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ68_EN0_MASK (0x10U)
41928 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ68_EN0_SHIFT (4U)
41929 /*! REQ68_EN0 - Writing a 1 to REQ68_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */
41930 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ68_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ68_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ68_EN0_MASK)
41931 
41932 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ69_EN0_MASK (0x20U)
41933 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ69_EN0_SHIFT (5U)
41934 /*! REQ69_EN0 - Writing a 1 to REQ69_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */
41935 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ69_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ69_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ69_EN0_MASK)
41936 
41937 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ70_EN0_MASK (0x40U)
41938 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ70_EN0_SHIFT (6U)
41939 /*! REQ70_EN0 - Writing a 1 to REQ70_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */
41940 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ70_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ70_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ70_EN0_MASK)
41941 
41942 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ71_EN0_MASK (0x80U)
41943 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ71_EN0_SHIFT (7U)
41944 /*! REQ71_EN0 - Writing a 1 to REQ71_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */
41945 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ71_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ71_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ71_EN0_MASK)
41946 
41947 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ72_EN0_MASK (0x100U)
41948 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ72_EN0_SHIFT (8U)
41949 /*! REQ72_EN0 - Writing a 1 to REQ72_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */
41950 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ72_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ72_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ72_EN0_MASK)
41951 
41952 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ73_EN0_MASK (0x200U)
41953 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ73_EN0_SHIFT (9U)
41954 /*! REQ73_EN0 - Writing a 1 to REQ73_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */
41955 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ73_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ73_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ73_EN0_MASK)
41956 
41957 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ74_EN0_MASK (0x400U)
41958 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ74_EN0_SHIFT (10U)
41959 /*! REQ74_EN0 - Writing a 1 to REQ74_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */
41960 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ74_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ74_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ74_EN0_MASK)
41961 
41962 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ75_EN0_MASK (0x800U)
41963 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ75_EN0_SHIFT (11U)
41964 /*! REQ75_EN0 - Writing a 1 to REQ75_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */
41965 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ75_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ75_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ75_EN0_MASK)
41966 
41967 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ76_EN0_MASK (0x1000U)
41968 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ76_EN0_SHIFT (12U)
41969 /*! REQ76_EN0 - Writing a 1 to REQ876_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */
41970 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ76_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ76_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ76_EN0_MASK)
41971 
41972 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ77_EN0_MASK (0x2000U)
41973 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ77_EN0_SHIFT (13U)
41974 /*! REQ77_EN0 - Writing a 1 to REQ77_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */
41975 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ77_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ77_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ77_EN0_MASK)
41976 
41977 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ78_EN0_MASK (0x4000U)
41978 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ78_EN0_SHIFT (14U)
41979 /*! REQ78_EN0 - Writing a 1 to REQ78_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */
41980 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ78_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ78_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ78_EN0_MASK)
41981 
41982 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ79_EN0_MASK (0x8000U)
41983 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ79_EN0_SHIFT (15U)
41984 /*! REQ79_EN0 - Writing a 1 to REQ79_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */
41985 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ79_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ79_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ79_EN0_MASK)
41986 
41987 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ80_EN0_MASK (0x10000U)
41988 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ80_EN0_SHIFT (16U)
41989 /*! REQ80_EN0 - Writing a 1 to REQ80_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */
41990 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ80_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ80_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ80_EN0_MASK)
41991 
41992 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ81_EN0_MASK (0x20000U)
41993 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ81_EN0_SHIFT (17U)
41994 /*! REQ81_EN0 - Writing a 1 to REQ81_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */
41995 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ81_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ81_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ81_EN0_MASK)
41996 
41997 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ82_EN0_MASK (0x40000U)
41998 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ82_EN0_SHIFT (18U)
41999 /*! REQ82_EN0 - Writing a 1 to REQ82_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */
42000 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ82_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ82_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ82_EN0_MASK)
42001 
42002 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ83_EN0_MASK (0x80000U)
42003 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ83_EN0_SHIFT (19U)
42004 /*! REQ83_EN0 - Writing a 1 to REQ83_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */
42005 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ83_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ83_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ83_EN0_MASK)
42006 
42007 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ84_EN0_MASK (0x100000U)
42008 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ84_EN0_SHIFT (20U)
42009 /*! REQ84_EN0 - Writing a 1 to REQ84_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */
42010 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ84_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ84_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ84_EN0_MASK)
42011 
42012 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ85_EN0_MASK (0x200000U)
42013 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ85_EN0_SHIFT (21U)
42014 /*! REQ85_EN0 - Writing a 1 to REQ85_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */
42015 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ85_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ85_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ85_EN0_MASK)
42016 
42017 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ86_EN0_MASK (0x400000U)
42018 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ86_EN0_SHIFT (22U)
42019 /*! REQ86_EN0 - Writing a 1 to REQ86_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */
42020 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ86_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ86_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ86_EN0_MASK)
42021 
42022 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ87_EN0_MASK (0x800000U)
42023 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ87_EN0_SHIFT (23U)
42024 /*! REQ87_EN0 - Writing a 1 to REQ87_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */
42025 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ87_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ87_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ87_EN0_MASK)
42026 
42027 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ88_EN0_MASK (0x1000000U)
42028 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ88_EN0_SHIFT (24U)
42029 /*! REQ88_EN0 - Writing a 1 to REQ88_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */
42030 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ88_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ88_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ88_EN0_MASK)
42031 
42032 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ91_EN0_MASK (0x8000000U)
42033 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ91_EN0_SHIFT (27U)
42034 /*! REQ91_EN0 - Writing a 1 to REQ91_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */
42035 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ91_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ91_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ91_EN0_MASK)
42036 
42037 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ92_EN0_MASK (0x10000000U)
42038 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ92_EN0_SHIFT (28U)
42039 /*! REQ92_EN0 - Writing a 1 to REQ92_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */
42040 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ92_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ92_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ92_EN0_MASK)
42041 
42042 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ93_EN0_MASK (0x20000000U)
42043 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ93_EN0_SHIFT (29U)
42044 /*! REQ93_EN0 - Writing a 1 to REQ93_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */
42045 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ93_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ93_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ93_EN0_MASK)
42046 
42047 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ94_EN0_MASK (0x40000000U)
42048 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ94_EN0_SHIFT (30U)
42049 /*! REQ94_EN0 - Writing a 1 to REQ94_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */
42050 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ94_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ94_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ94_EN0_MASK)
42051 
42052 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ95_EN0_MASK (0x80000000U)
42053 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ95_EN0_SHIFT (31U)
42054 /*! REQ95_EN0 - Writing a 1 to REQ95_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */
42055 #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ95_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ95_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ95_EN0_MASK)
42056 /*! @} */
42057 
42058 /*! @name DMA0_REQ_ENABLE2_CLR - DMA0 Request Enable2 */
42059 /*! @{ */
42060 
42061 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ64_EN0_MASK (0x1U)
42062 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ64_EN0_SHIFT (0U)
42063 /*! REQ64_EN0 - Writing a 1 to REQ64_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */
42064 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ64_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ64_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ64_EN0_MASK)
42065 
42066 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ65_EN0_MASK (0x2U)
42067 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ65_EN0_SHIFT (1U)
42068 /*! REQ65_EN0 - Writing a 1 to REQ65_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */
42069 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ65_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ65_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ65_EN0_MASK)
42070 
42071 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ66_EN0_MASK (0x4U)
42072 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ66_EN0_SHIFT (2U)
42073 /*! REQ66_EN0 - Writing a 1 to REQ66_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */
42074 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ66_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ66_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ66_EN0_MASK)
42075 
42076 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ67_EN0_MASK (0x8U)
42077 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ67_EN0_SHIFT (3U)
42078 /*! REQ67_EN0 - Writing a 1 to REQ67_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */
42079 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ67_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ67_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ67_EN0_MASK)
42080 
42081 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ68_EN0_MASK (0x10U)
42082 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ68_EN0_SHIFT (4U)
42083 /*! REQ68_EN0 - Writing a 1 to REQ68_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */
42084 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ68_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ68_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ68_EN0_MASK)
42085 
42086 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ69_EN0_MASK (0x20U)
42087 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ69_EN0_SHIFT (5U)
42088 /*! REQ69_EN0 - Writing a 1 to REQ69_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */
42089 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ69_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ69_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ69_EN0_MASK)
42090 
42091 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ70_EN0_MASK (0x40U)
42092 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ70_EN0_SHIFT (6U)
42093 /*! REQ70_EN0 - Writing a 1 to REQ70_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */
42094 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ70_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ70_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ70_EN0_MASK)
42095 
42096 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ71_EN0_MASK (0x80U)
42097 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ71_EN0_SHIFT (7U)
42098 /*! REQ71_EN0 - Writing a 1 to REQ71_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */
42099 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ71_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ71_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ71_EN0_MASK)
42100 
42101 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ72_EN0_MASK (0x100U)
42102 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ72_EN0_SHIFT (8U)
42103 /*! REQ72_EN0 - Writing a 1 to REQ72_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */
42104 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ72_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ72_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ72_EN0_MASK)
42105 
42106 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ73_EN0_MASK (0x200U)
42107 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ73_EN0_SHIFT (9U)
42108 /*! REQ73_EN0 - Writing a 1 to REQ73_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */
42109 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ73_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ73_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ73_EN0_MASK)
42110 
42111 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ74_EN0_MASK (0x400U)
42112 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ74_EN0_SHIFT (10U)
42113 /*! REQ74_EN0 - Writing a 1 to REQ74_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */
42114 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ74_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ74_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ74_EN0_MASK)
42115 
42116 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ75_EN0_MASK (0x800U)
42117 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ75_EN0_SHIFT (11U)
42118 /*! REQ75_EN0 - Writing a 1 to REQ75_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */
42119 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ75_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ75_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ75_EN0_MASK)
42120 
42121 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ76_EN0_MASK (0x1000U)
42122 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ76_EN0_SHIFT (12U)
42123 /*! REQ76_EN0 - Writing a 1 to REQ76_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */
42124 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ76_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ76_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ76_EN0_MASK)
42125 
42126 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ77_EN0_MASK (0x2000U)
42127 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ77_EN0_SHIFT (13U)
42128 /*! REQ77_EN0 - Writing a 1 to REQ77_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */
42129 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ77_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ77_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ77_EN0_MASK)
42130 
42131 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ78_EN0_MASK (0x4000U)
42132 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ78_EN0_SHIFT (14U)
42133 /*! REQ78_EN0 - Writing a 1 to REQ78_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */
42134 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ78_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ78_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ78_EN0_MASK)
42135 
42136 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ79_EN0_MASK (0x8000U)
42137 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ79_EN0_SHIFT (15U)
42138 /*! REQ79_EN0 - Writing a 1 to REQ79_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */
42139 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ79_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ79_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ79_EN0_MASK)
42140 
42141 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ80_EN0_MASK (0x10000U)
42142 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ80_EN0_SHIFT (16U)
42143 /*! REQ80_EN0 - Writing a 1 to REQ80_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */
42144 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ80_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ80_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ80_EN0_MASK)
42145 
42146 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ81_EN0_MASK (0x20000U)
42147 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ81_EN0_SHIFT (17U)
42148 /*! REQ81_EN0 - Writing a 1 to REQ81_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */
42149 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ81_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ81_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ81_EN0_MASK)
42150 
42151 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ82_EN0_MASK (0x40000U)
42152 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ82_EN0_SHIFT (18U)
42153 /*! REQ82_EN0 - Writing a 1 to REQ82_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */
42154 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ82_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ82_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ82_EN0_MASK)
42155 
42156 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ83_EN0_MASK (0x80000U)
42157 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ83_EN0_SHIFT (19U)
42158 /*! REQ83_EN0 - Writing a 1 to REQ83_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */
42159 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ83_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ83_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ83_EN0_MASK)
42160 
42161 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ84_EN0_MASK (0x100000U)
42162 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ84_EN0_SHIFT (20U)
42163 /*! REQ84_EN0 - Writing a 1 to REQ84_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */
42164 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ84_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ84_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ84_EN0_MASK)
42165 
42166 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ85_EN0_MASK (0x200000U)
42167 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ85_EN0_SHIFT (21U)
42168 /*! REQ85_EN0 - Writing a 1 to REQ85_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */
42169 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ85_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ85_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ85_EN0_MASK)
42170 
42171 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ86_EN0_MASK (0x400000U)
42172 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ86_EN0_SHIFT (22U)
42173 /*! REQ86_EN0 - Writing a 1 to REQ86_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */
42174 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ86_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ86_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ86_EN0_MASK)
42175 
42176 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ87_EN0_MASK (0x800000U)
42177 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ87_EN0_SHIFT (23U)
42178 /*! REQ87_EN0 - Writing a 1 to REQ87_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */
42179 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ87_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ87_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ87_EN0_MASK)
42180 
42181 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ88_EN0_MASK (0x1000000U)
42182 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ88_EN0_SHIFT (24U)
42183 /*! REQ88_EN0 - Writing a 1 to REQ88_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */
42184 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ88_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ88_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ88_EN0_MASK)
42185 
42186 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ91_EN0_MASK (0x8000000U)
42187 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ91_EN0_SHIFT (27U)
42188 /*! REQ91_EN0 - Writing a 1 to REQ91_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */
42189 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ91_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ91_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ91_EN0_MASK)
42190 
42191 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ92_EN0_MASK (0x10000000U)
42192 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ92_EN0_SHIFT (28U)
42193 /*! REQ92_EN0 - Writing a 1 to REQ92_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */
42194 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ92_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ92_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ92_EN0_MASK)
42195 
42196 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ93_EN0_MASK (0x20000000U)
42197 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ93_EN0_SHIFT (29U)
42198 /*! REQ93_EN0 - Writing a 1 to REQ93_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */
42199 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ93_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ93_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ93_EN0_MASK)
42200 
42201 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ94_EN0_MASK (0x40000000U)
42202 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ94_EN0_SHIFT (30U)
42203 /*! REQ94_EN0 - Writing a 1 to REQ94_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */
42204 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ94_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ94_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ94_EN0_MASK)
42205 
42206 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ95_EN0_MASK (0x80000000U)
42207 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ95_EN0_SHIFT (31U)
42208 /*! REQ95_EN0 - Writing a 1 to REQ95_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */
42209 #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ95_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ95_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ95_EN0_MASK)
42210 /*! @} */
42211 
42212 /*! @name DMA0_REQ_ENABLE2_TOG - DMA0 Request Enable2 */
42213 /*! @{ */
42214 
42215 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ64_EN0_MASK (0x1U)
42216 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ64_EN0_SHIFT (0U)
42217 /*! REQ64_EN0 - Writing a 1 to REQ64_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */
42218 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ64_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ64_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ64_EN0_MASK)
42219 
42220 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ65_EN0_MASK (0x2U)
42221 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ65_EN0_SHIFT (1U)
42222 /*! REQ65_EN0 - Writing a 1 to REQ65_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */
42223 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ65_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ65_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ65_EN0_MASK)
42224 
42225 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ66_EN0_MASK (0x4U)
42226 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ66_EN0_SHIFT (2U)
42227 /*! REQ66_EN0 - Writing a 1 to REQ66_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */
42228 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ66_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ66_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ66_EN0_MASK)
42229 
42230 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ67_EN0_MASK (0x8U)
42231 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ67_EN0_SHIFT (3U)
42232 /*! REQ67_EN0 - Writing a 1 to REQ67_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */
42233 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ67_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ67_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ67_EN0_MASK)
42234 
42235 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ68_EN0_MASK (0x10U)
42236 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ68_EN0_SHIFT (4U)
42237 /*! REQ68_EN0 - Writing a 1 to REQ68_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */
42238 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ68_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ68_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ68_EN0_MASK)
42239 
42240 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ69_EN0_MASK (0x20U)
42241 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ69_EN0_SHIFT (5U)
42242 /*! REQ69_EN0 - Writing a 1 to REQ69_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */
42243 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ69_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ69_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ69_EN0_MASK)
42244 
42245 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ70_EN0_MASK (0x40U)
42246 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ70_EN0_SHIFT (6U)
42247 /*! REQ70_EN0 - Writing a 1 to REQ70_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */
42248 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ70_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ70_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ70_EN0_MASK)
42249 
42250 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ71_EN0_MASK (0x80U)
42251 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ71_EN0_SHIFT (7U)
42252 /*! REQ71_EN0 - Writing a 1 to REQ71_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */
42253 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ71_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ71_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ71_EN0_MASK)
42254 
42255 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ72_EN0_MASK (0x100U)
42256 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ72_EN0_SHIFT (8U)
42257 /*! REQ72_EN0 - Writing a 1 to REQ72_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */
42258 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ72_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ72_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ72_EN0_MASK)
42259 
42260 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ73_EN0_MASK (0x200U)
42261 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ73_EN0_SHIFT (9U)
42262 /*! REQ73_EN0 - Writing a 1 to REQ73_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */
42263 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ73_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ73_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ73_EN0_MASK)
42264 
42265 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ74_EN0_MASK (0x400U)
42266 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ74_EN0_SHIFT (10U)
42267 /*! REQ74_EN0 - Writing a 1 to REQ74_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */
42268 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ74_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ74_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ74_EN0_MASK)
42269 
42270 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ75_EN0_MASK (0x800U)
42271 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ75_EN0_SHIFT (11U)
42272 /*! REQ75_EN0 - Writing a 1 to REQ75_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */
42273 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ75_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ75_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ75_EN0_MASK)
42274 
42275 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ76_EN0_MASK (0x1000U)
42276 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ76_EN0_SHIFT (12U)
42277 /*! REQ76_EN0 - Writing a 1 to REQ76_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */
42278 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ76_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ76_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ76_EN0_MASK)
42279 
42280 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ77_EN0_MASK (0x2000U)
42281 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ77_EN0_SHIFT (13U)
42282 /*! REQ77_EN0 - Writing a 1 to REQ77_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */
42283 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ77_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ77_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ77_EN0_MASK)
42284 
42285 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ78_EN0_MASK (0x4000U)
42286 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ78_EN0_SHIFT (14U)
42287 /*! REQ78_EN0 - Writing a 1 to REQ78_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */
42288 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ78_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ78_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ78_EN0_MASK)
42289 
42290 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ79_EN0_MASK (0x8000U)
42291 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ79_EN0_SHIFT (15U)
42292 /*! REQ79_EN0 - Writing a 1 to REQ79_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */
42293 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ79_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ79_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ79_EN0_MASK)
42294 
42295 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ80_EN0_MASK (0x10000U)
42296 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ80_EN0_SHIFT (16U)
42297 /*! REQ80_EN0 - Writing a 1 to REQ80_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */
42298 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ80_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ80_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ80_EN0_MASK)
42299 
42300 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ81_EN0_MASK (0x20000U)
42301 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ81_EN0_SHIFT (17U)
42302 /*! REQ81_EN0 - Writing a 1 to REQ81_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */
42303 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ81_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ81_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ81_EN0_MASK)
42304 
42305 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ82_EN0_MASK (0x40000U)
42306 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ82_EN0_SHIFT (18U)
42307 /*! REQ82_EN0 - Writing a 1 to REQ82_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */
42308 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ82_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ82_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ82_EN0_MASK)
42309 
42310 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ83_EN0_MASK (0x80000U)
42311 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ83_EN0_SHIFT (19U)
42312 /*! REQ83_EN0 - Writing a 1 to REQ83_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */
42313 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ83_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ83_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ83_EN0_MASK)
42314 
42315 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ84_EN0_MASK (0x100000U)
42316 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ84_EN0_SHIFT (20U)
42317 /*! REQ84_EN0 - Writing a 1 to REQ84_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */
42318 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ84_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ84_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ84_EN0_MASK)
42319 
42320 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ85_EN0_MASK (0x200000U)
42321 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ85_EN0_SHIFT (21U)
42322 /*! REQ85_EN0 - Writing a 1 to REQ85_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */
42323 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ85_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ85_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ85_EN0_MASK)
42324 
42325 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ86_EN0_MASK (0x400000U)
42326 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ86_EN0_SHIFT (22U)
42327 /*! REQ86_EN0 - Writing a 1 to REQ86_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */
42328 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ86_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ86_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ86_EN0_MASK)
42329 
42330 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ87_EN0_MASK (0x800000U)
42331 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ87_EN0_SHIFT (23U)
42332 /*! REQ87_EN0 - Writing a 1 to REQ87_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */
42333 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ87_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ87_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ87_EN0_MASK)
42334 
42335 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ88_EN0_MASK (0x1000000U)
42336 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ88_EN0_SHIFT (24U)
42337 /*! REQ88_EN0 - Writing a 1 to REQ88_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */
42338 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ88_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ88_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ88_EN0_MASK)
42339 
42340 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ91_EN0_MASK (0x8000000U)
42341 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ91_EN0_SHIFT (27U)
42342 /*! REQ91_EN0 - Writing a 1 to REQ91_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */
42343 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ91_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ91_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ91_EN0_MASK)
42344 
42345 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ92_EN0_MASK (0x10000000U)
42346 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ92_EN0_SHIFT (28U)
42347 /*! REQ92_EN0 - Writing a 1 to REQ92_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */
42348 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ92_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ92_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ92_EN0_MASK)
42349 
42350 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ93_EN0_MASK (0x20000000U)
42351 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ93_EN0_SHIFT (29U)
42352 /*! REQ93_EN0 - Writing a 1 to REQ93_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */
42353 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ93_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ93_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ93_EN0_MASK)
42354 
42355 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ94_EN0_MASK (0x40000000U)
42356 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ94_EN0_SHIFT (30U)
42357 /*! REQ94_EN0 - Writing a 1 to REQ94_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */
42358 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ94_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ94_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ94_EN0_MASK)
42359 
42360 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ95_EN0_MASK (0x80000000U)
42361 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ95_EN0_SHIFT (31U)
42362 /*! REQ95_EN0 - Writing a 1 to REQ95_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */
42363 #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ95_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ95_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ95_EN0_MASK)
42364 /*! @} */
42365 
42366 /*! @name DMA0_REQ_ENABLE3 - DMA0 Request Enable3 */
42367 /*! @{ */
42368 
42369 #define INPUTMUX_DMA0_REQ_ENABLE3_REQ96_EN0_MASK (0x1U)
42370 #define INPUTMUX_DMA0_REQ_ENABLE3_REQ96_EN0_SHIFT (0U)
42371 /*! REQ96_EN0 - This register is used to enable and disable I3C0 transmit request.
42372  *  0b0..Disable
42373  *  0b1..Enable
42374  */
42375 #define INPUTMUX_DMA0_REQ_ENABLE3_REQ96_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ96_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ96_EN0_MASK)
42376 
42377 #define INPUTMUX_DMA0_REQ_ENABLE3_REQ97_EN0_MASK (0x2U)
42378 #define INPUTMUX_DMA0_REQ_ENABLE3_REQ97_EN0_SHIFT (1U)
42379 /*! REQ97_EN0 - This register is used to enable and disable I3C1 receive request.
42380  *  0b0..Disable
42381  *  0b1..Enable
42382  */
42383 #define INPUTMUX_DMA0_REQ_ENABLE3_REQ97_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ97_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ97_EN0_MASK)
42384 
42385 #define INPUTMUX_DMA0_REQ_ENABLE3_REQ98_EN0_MASK (0x4U)
42386 #define INPUTMUX_DMA0_REQ_ENABLE3_REQ98_EN0_SHIFT (2U)
42387 /*! REQ98_EN0 - This register is used to enable and disable I3C1 transmit request.
42388  *  0b0..Disable
42389  *  0b1..Enable
42390  */
42391 #define INPUTMUX_DMA0_REQ_ENABLE3_REQ98_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ98_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ98_EN0_MASK)
42392 
42393 #define INPUTMUX_DMA0_REQ_ENABLE3_REQ99_EN0_MASK (0x8U)
42394 #define INPUTMUX_DMA0_REQ_ENABLE3_REQ99_EN0_SHIFT (3U)
42395 /*! REQ99_EN0 - This register is used to enable and disable SAI0 receive request.
42396  *  0b0..Disable
42397  *  0b1..Enable
42398  */
42399 #define INPUTMUX_DMA0_REQ_ENABLE3_REQ99_EN0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ99_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ99_EN0_MASK)
42400 
42401 #define INPUTMUX_DMA0_REQ_ENABLE3_REQ100_EN0_MASK (0x10U)
42402 #define INPUTMUX_DMA0_REQ_ENABLE3_REQ100_EN0_SHIFT (4U)
42403 /*! REQ100_EN0 - This register is used to enable and disable SAI0 transmit request.
42404  *  0b0..Disable
42405  *  0b1..Enable
42406  */
42407 #define INPUTMUX_DMA0_REQ_ENABLE3_REQ100_EN0(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ100_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ100_EN0_MASK)
42408 
42409 #define INPUTMUX_DMA0_REQ_ENABLE3_REQ101_EN0_MASK (0x20U)
42410 #define INPUTMUX_DMA0_REQ_ENABLE3_REQ101_EN0_SHIFT (5U)
42411 /*! REQ101_EN0 - This register is used to enable and disable SAI1 receive request.
42412  *  0b0..Disable
42413  *  0b1..Enable
42414  */
42415 #define INPUTMUX_DMA0_REQ_ENABLE3_REQ101_EN0(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ101_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ101_EN0_MASK)
42416 
42417 #define INPUTMUX_DMA0_REQ_ENABLE3_REQ102_EN0_MASK (0x40U)
42418 #define INPUTMUX_DMA0_REQ_ENABLE3_REQ102_EN0_SHIFT (6U)
42419 /*! REQ102_EN0 - This register is used to enable and disable SAI1 transmit request.
42420  *  0b0..Disable
42421  *  0b1..Enable
42422  */
42423 #define INPUTMUX_DMA0_REQ_ENABLE3_REQ102_EN0(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ102_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ102_EN0_MASK)
42424 
42425 #define INPUTMUX_DMA0_REQ_ENABLE3_REQ103_EN0_MASK (0x80U)
42426 #define INPUTMUX_DMA0_REQ_ENABLE3_REQ103_EN0_SHIFT (7U)
42427 /*! REQ103_EN0 - This register is used to enable and disable SINC0 ipd_req_sinc[0] or ipd_req_alt [0] request.
42428  *  0b0..Disable
42429  *  0b1..Enable
42430  */
42431 #define INPUTMUX_DMA0_REQ_ENABLE3_REQ103_EN0(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ103_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ103_EN0_MASK)
42432 
42433 #define INPUTMUX_DMA0_REQ_ENABLE3_REQ104_EN0_MASK (0x100U)
42434 #define INPUTMUX_DMA0_REQ_ENABLE3_REQ104_EN0_SHIFT (8U)
42435 /*! REQ104_EN0 - This register is used to enable and disable SINC0 ipd_req_sinc[1] or ipd_req_alt [1] request.
42436  *  0b0..Disable
42437  *  0b1..Enable
42438  */
42439 #define INPUTMUX_DMA0_REQ_ENABLE3_REQ104_EN0(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ104_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ104_EN0_MASK)
42440 
42441 #define INPUTMUX_DMA0_REQ_ENABLE3_REQ105_EN0_MASK (0x200U)
42442 #define INPUTMUX_DMA0_REQ_ENABLE3_REQ105_EN0_SHIFT (9U)
42443 /*! REQ105_EN0 - This register is used to enable and disable SINC0 ipd_req_sinc[2] or ipd_req_alt [2] request.
42444  *  0b0..Disable
42445  *  0b1..Enable
42446  */
42447 #define INPUTMUX_DMA0_REQ_ENABLE3_REQ105_EN0(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ105_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ105_EN0_MASK)
42448 
42449 #define INPUTMUX_DMA0_REQ_ENABLE3_REQ106_EN0_MASK (0x400U)
42450 #define INPUTMUX_DMA0_REQ_ENABLE3_REQ106_EN0_SHIFT (10U)
42451 /*! REQ106_EN0 - This register is used to enable and disable SINC0 ipd_req_sinc[3] or ipd_req_alt [3] request.
42452  *  0b0..Disable
42453  *  0b1..Enable
42454  */
42455 #define INPUTMUX_DMA0_REQ_ENABLE3_REQ106_EN0(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ106_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ106_EN0_MASK)
42456 
42457 #define INPUTMUX_DMA0_REQ_ENABLE3_REQ107_EN0_MASK (0x800U)
42458 #define INPUTMUX_DMA0_REQ_ENABLE3_REQ107_EN0_SHIFT (11U)
42459 /*! REQ107_EN0 - This register is used to enable and disable SINC0 ipd_req_sinc[4] or ipd_req_alt [4] request.
42460  *  0b0..Disable
42461  *  0b1..Enable
42462  */
42463 #define INPUTMUX_DMA0_REQ_ENABLE3_REQ107_EN0(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ107_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ107_EN0_MASK)
42464 
42465 #define INPUTMUX_DMA0_REQ_ENABLE3_REQ108_EN0_MASK (0x1000U)
42466 #define INPUTMUX_DMA0_REQ_ENABLE3_REQ108_EN0_SHIFT (12U)
42467 /*! REQ108_EN0 - This register is used to enable and disable GPIO0 pin event request 0.
42468  *  0b0..Disable
42469  *  0b1..Enable
42470  */
42471 #define INPUTMUX_DMA0_REQ_ENABLE3_REQ108_EN0(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ108_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ108_EN0_MASK)
42472 
42473 #define INPUTMUX_DMA0_REQ_ENABLE3_REQ109_EN0_MASK (0x2000U)
42474 #define INPUTMUX_DMA0_REQ_ENABLE3_REQ109_EN0_SHIFT (13U)
42475 /*! REQ109_EN0 - This register is used to enable and disable GPIO0 pin event request 1.
42476  *  0b0..Disable
42477  *  0b1..Enable
42478  */
42479 #define INPUTMUX_DMA0_REQ_ENABLE3_REQ109_EN0(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ109_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ109_EN0_MASK)
42480 
42481 #define INPUTMUX_DMA0_REQ_ENABLE3_REQ110_EN0_MASK (0x4000U)
42482 #define INPUTMUX_DMA0_REQ_ENABLE3_REQ110_EN0_SHIFT (14U)
42483 /*! REQ110_EN0 - This register is used to enable and disable GPIO1 pin event request 0.
42484  *  0b0..Disable
42485  *  0b1..Enable
42486  */
42487 #define INPUTMUX_DMA0_REQ_ENABLE3_REQ110_EN0(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ110_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ110_EN0_MASK)
42488 
42489 #define INPUTMUX_DMA0_REQ_ENABLE3_REQ111_EN0_MASK (0x8000U)
42490 #define INPUTMUX_DMA0_REQ_ENABLE3_REQ111_EN0_SHIFT (15U)
42491 /*! REQ111_EN0 - This register is used to enable and disable GPIO1 pin event request 1.
42492  *  0b0..Disable
42493  *  0b1..Enable
42494  */
42495 #define INPUTMUX_DMA0_REQ_ENABLE3_REQ111_EN0(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ111_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ111_EN0_MASK)
42496 
42497 #define INPUTMUX_DMA0_REQ_ENABLE3_REQ112_EN0_MASK (0x10000U)
42498 #define INPUTMUX_DMA0_REQ_ENABLE3_REQ112_EN0_SHIFT (16U)
42499 /*! REQ112_EN0 - This register is used to enable and disable GPIO2 pin event request 0.
42500  *  0b0..Disable
42501  *  0b1..Enable
42502  */
42503 #define INPUTMUX_DMA0_REQ_ENABLE3_REQ112_EN0(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ112_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ112_EN0_MASK)
42504 
42505 #define INPUTMUX_DMA0_REQ_ENABLE3_REQ113_EN0_MASK (0x20000U)
42506 #define INPUTMUX_DMA0_REQ_ENABLE3_REQ113_EN0_SHIFT (17U)
42507 /*! REQ113_EN0 - This register is used to enable and disable GPIO2 pin event request 1.
42508  *  0b0..Disable
42509  *  0b1..Enable
42510  */
42511 #define INPUTMUX_DMA0_REQ_ENABLE3_REQ113_EN0(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ113_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ113_EN0_MASK)
42512 
42513 #define INPUTMUX_DMA0_REQ_ENABLE3_REQ114_EN0_MASK (0x40000U)
42514 #define INPUTMUX_DMA0_REQ_ENABLE3_REQ114_EN0_SHIFT (18U)
42515 /*! REQ114_EN0 - This register is used to enable and disable GPIO3 pin event request 0.
42516  *  0b0..Disable
42517  *  0b1..Enable
42518  */
42519 #define INPUTMUX_DMA0_REQ_ENABLE3_REQ114_EN0(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ114_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ114_EN0_MASK)
42520 
42521 #define INPUTMUX_DMA0_REQ_ENABLE3_REQ115_EN0_MASK (0x80000U)
42522 #define INPUTMUX_DMA0_REQ_ENABLE3_REQ115_EN0_SHIFT (19U)
42523 /*! REQ115_EN0 - This register is used to enable and disable GPIO3 pin event request 1.
42524  *  0b0..Disable
42525  *  0b1..Enable
42526  */
42527 #define INPUTMUX_DMA0_REQ_ENABLE3_REQ115_EN0(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ115_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ115_EN0_MASK)
42528 
42529 #define INPUTMUX_DMA0_REQ_ENABLE3_REQ116_EN0_MASK (0x100000U)
42530 #define INPUTMUX_DMA0_REQ_ENABLE3_REQ116_EN0_SHIFT (20U)
42531 /*! REQ116_EN0 - This register is used to enable and disable GPIO4 pin event request 0.
42532  *  0b0..Disable
42533  *  0b1..Enable
42534  */
42535 #define INPUTMUX_DMA0_REQ_ENABLE3_REQ116_EN0(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ116_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ116_EN0_MASK)
42536 
42537 #define INPUTMUX_DMA0_REQ_ENABLE3_REQ117_EN0_MASK (0x200000U)
42538 #define INPUTMUX_DMA0_REQ_ENABLE3_REQ117_EN0_SHIFT (21U)
42539 /*! REQ117_EN0 - This register is used to enable and disable GPIO4 pin event request 1.
42540  *  0b0..Disable
42541  *  0b1..Enable
42542  */
42543 #define INPUTMUX_DMA0_REQ_ENABLE3_REQ117_EN0(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ117_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ117_EN0_MASK)
42544 
42545 #define INPUTMUX_DMA0_REQ_ENABLE3_REQ118_EN0_MASK (0x400000U)
42546 #define INPUTMUX_DMA0_REQ_ENABLE3_REQ118_EN0_SHIFT (22U)
42547 /*! REQ118_EN0 - This register is used to enable and disable GPIO5 pin event request 0.
42548  *  0b0..Disable
42549  *  0b1..Enable
42550  */
42551 #define INPUTMUX_DMA0_REQ_ENABLE3_REQ118_EN0(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ118_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ118_EN0_MASK)
42552 
42553 #define INPUTMUX_DMA0_REQ_ENABLE3_REQ119_EN0_MASK (0x800000U)
42554 #define INPUTMUX_DMA0_REQ_ENABLE3_REQ119_EN0_SHIFT (23U)
42555 /*! REQ119_EN0 - This register is used to enable and disable GPIO5 pin event request 1.
42556  *  0b0..Disable
42557  *  0b1..Enable
42558  */
42559 #define INPUTMUX_DMA0_REQ_ENABLE3_REQ119_EN0(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ119_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ119_EN0_MASK)
42560 
42561 #define INPUTMUX_DMA0_REQ_ENABLE3_REQ120_EN0_MASK (0x1000000U)
42562 #define INPUTMUX_DMA0_REQ_ENABLE3_REQ120_EN0_SHIFT (24U)
42563 /*! REQ120_EN0 - This register is used to enable and disable TSI0 end of scan request.
42564  *  0b0..Disable
42565  *  0b1..Enable
42566  */
42567 #define INPUTMUX_DMA0_REQ_ENABLE3_REQ120_EN0(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ120_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ120_EN0_MASK)
42568 
42569 #define INPUTMUX_DMA0_REQ_ENABLE3_REQ121_EN0_MASK (0x2000000U)
42570 #define INPUTMUX_DMA0_REQ_ENABLE3_REQ121_EN0_SHIFT (25U)
42571 /*! REQ121_EN0 - This register is used to enable and disable TSI0 out of range request.
42572  *  0b0..Disable
42573  *  0b1..Enable
42574  */
42575 #define INPUTMUX_DMA0_REQ_ENABLE3_REQ121_EN0(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ121_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ121_EN0_MASK)
42576 /*! @} */
42577 
42578 /*! @name DMA0_REQ_ENABLE3_SET - DMA0 Request Enable3 */
42579 /*! @{ */
42580 
42581 #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ96_EN0_MASK (0x1U)
42582 #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ96_EN0_SHIFT (0U)
42583 /*! REQ96_EN0 - Writing a 1 to REQ96_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */
42584 #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ96_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ96_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ96_EN0_MASK)
42585 
42586 #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ97_EN0_MASK (0x2U)
42587 #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ97_EN0_SHIFT (1U)
42588 /*! REQ97_EN0 - Writing a 1 to REQ97_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */
42589 #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ97_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ97_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ97_EN0_MASK)
42590 
42591 #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ98_EN0_MASK (0x4U)
42592 #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ98_EN0_SHIFT (2U)
42593 /*! REQ98_EN0 - Writing a 1 to REQ98_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */
42594 #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ98_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ98_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ98_EN0_MASK)
42595 
42596 #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ99_EN0_MASK (0x8U)
42597 #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ99_EN0_SHIFT (3U)
42598 /*! REQ99_EN0 - Writing a 1 to REQ99_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */
42599 #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ99_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ99_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ99_EN0_MASK)
42600 
42601 #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ100_EN0_MASK (0x10U)
42602 #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ100_EN0_SHIFT (4U)
42603 /*! REQ100_EN0 - Writing a 1 to REQ100_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */
42604 #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ100_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ100_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ100_EN0_MASK)
42605 
42606 #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ101_EN0_MASK (0x20U)
42607 #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ101_EN0_SHIFT (5U)
42608 /*! REQ101_EN0 - Writing a 1 to REQ101_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */
42609 #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ101_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ101_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ101_EN0_MASK)
42610 
42611 #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ102_EN0_MASK (0x40U)
42612 #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ102_EN0_SHIFT (6U)
42613 /*! REQ102_EN0 - Writing a 1 to REQ102_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */
42614 #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ102_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ102_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ102_EN0_MASK)
42615 
42616 #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ103_EN0_MASK (0x80U)
42617 #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ103_EN0_SHIFT (7U)
42618 /*! REQ103_EN0 - Writing a 1 to REQ103_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */
42619 #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ103_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ103_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ103_EN0_MASK)
42620 
42621 #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ104_EN0_MASK (0x100U)
42622 #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ104_EN0_SHIFT (8U)
42623 /*! REQ104_EN0 - Writing a 1 to REQ104_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */
42624 #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ104_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ104_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ104_EN0_MASK)
42625 
42626 #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ105_EN0_MASK (0x200U)
42627 #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ105_EN0_SHIFT (9U)
42628 /*! REQ105_EN0 - Writing a 1 to REQ105_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */
42629 #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ105_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ105_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ105_EN0_MASK)
42630 
42631 #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ106_EN0_MASK (0x400U)
42632 #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ106_EN0_SHIFT (10U)
42633 /*! REQ106_EN0 - Writing a 1 to REQ106_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */
42634 #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ106_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ106_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ106_EN0_MASK)
42635 
42636 #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ107_EN0_MASK (0x800U)
42637 #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ107_EN0_SHIFT (11U)
42638 /*! REQ107_EN0 - Writing a 1 to REQ107_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */
42639 #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ107_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ107_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ107_EN0_MASK)
42640 
42641 #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ108_EN0_MASK (0x1000U)
42642 #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ108_EN0_SHIFT (12U)
42643 /*! REQ108_EN0 - Writing a 1 to REQ108_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */
42644 #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ108_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ108_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ108_EN0_MASK)
42645 
42646 #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ109_EN0_MASK (0x2000U)
42647 #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ109_EN0_SHIFT (13U)
42648 /*! REQ109_EN0 - Writing a 1 to REQ109_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */
42649 #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ109_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ109_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ109_EN0_MASK)
42650 
42651 #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ110_EN0_MASK (0x4000U)
42652 #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ110_EN0_SHIFT (14U)
42653 /*! REQ110_EN0 - Writing a 1 to REQ110_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */
42654 #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ110_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ110_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ110_EN0_MASK)
42655 
42656 #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ111_EN0_MASK (0x8000U)
42657 #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ111_EN0_SHIFT (15U)
42658 /*! REQ111_EN0 - Writing a 1 to REQ111_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */
42659 #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ111_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ111_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ111_EN0_MASK)
42660 
42661 #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ112_EN0_MASK (0x10000U)
42662 #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ112_EN0_SHIFT (16U)
42663 /*! REQ112_EN0 - Writing a 1 to REQ112_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */
42664 #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ112_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ112_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ112_EN0_MASK)
42665 
42666 #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ113_EN0_MASK (0x20000U)
42667 #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ113_EN0_SHIFT (17U)
42668 /*! REQ113_EN0 - Writing a 1 to REQ113_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */
42669 #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ113_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ113_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ113_EN0_MASK)
42670 
42671 #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ114_EN0_MASK (0x40000U)
42672 #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ114_EN0_SHIFT (18U)
42673 /*! REQ114_EN0 - Writing a 1 to REQ114_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */
42674 #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ114_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ114_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ114_EN0_MASK)
42675 
42676 #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ115_EN0_MASK (0x80000U)
42677 #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ115_EN0_SHIFT (19U)
42678 /*! REQ115_EN0 - Writing a 1 to REQ115_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */
42679 #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ115_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ115_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ115_EN0_MASK)
42680 
42681 #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ116_EN0_MASK (0x100000U)
42682 #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ116_EN0_SHIFT (20U)
42683 /*! REQ116_EN0 - Writing a 1 to REQ116_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */
42684 #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ116_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ116_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ116_EN0_MASK)
42685 
42686 #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ117_EN0_MASK (0x200000U)
42687 #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ117_EN0_SHIFT (21U)
42688 /*! REQ117_EN0 - Writing a 1 to REQ117_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */
42689 #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ117_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ117_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ117_EN0_MASK)
42690 
42691 #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ118_EN0_MASK (0x400000U)
42692 #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ118_EN0_SHIFT (22U)
42693 /*! REQ118_EN0 - Writing a 1 to REQ118_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */
42694 #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ118_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ118_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ118_EN0_MASK)
42695 
42696 #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ119_EN0_MASK (0x800000U)
42697 #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ119_EN0_SHIFT (23U)
42698 /*! REQ119_EN0 - Writing a 1 to REQ119_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */
42699 #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ119_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ119_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ119_EN0_MASK)
42700 
42701 #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ120_EN0_MASK (0x1000000U)
42702 #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ120_EN0_SHIFT (24U)
42703 /*! REQ120_EN0 - Writing a 1 to REQ120_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */
42704 #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ120_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ120_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ120_EN0_MASK)
42705 
42706 #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ121_EN0_MASK (0x2000000U)
42707 #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ121_EN0_SHIFT (25U)
42708 /*! REQ121_EN0 - Writing a 1 to REQ121_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */
42709 #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ121_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ121_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ121_EN0_MASK)
42710 /*! @} */
42711 
42712 /*! @name DMA0_REQ_ENABLE3_CLR - DMA0 Request Enable3 */
42713 /*! @{ */
42714 
42715 #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ96_EN0_MASK (0x1U)
42716 #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ96_EN0_SHIFT (0U)
42717 /*! REQ96_EN0 - Writing a 1 to REQ96_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */
42718 #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ96_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ96_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ96_EN0_MASK)
42719 
42720 #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ97_EN0_MASK (0x2U)
42721 #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ97_EN0_SHIFT (1U)
42722 /*! REQ97_EN0 - Writing a 1 to REQ97_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */
42723 #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ97_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ97_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ97_EN0_MASK)
42724 
42725 #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ98_EN0_MASK (0x4U)
42726 #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ98_EN0_SHIFT (2U)
42727 /*! REQ98_EN0 - Writing a 1 to REQ98_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */
42728 #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ98_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ98_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ98_EN0_MASK)
42729 
42730 #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ99_EN0_MASK (0x8U)
42731 #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ99_EN0_SHIFT (3U)
42732 /*! REQ99_EN0 - Writing a 1 to REQ99_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */
42733 #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ99_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ99_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ99_EN0_MASK)
42734 
42735 #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ100_EN0_MASK (0x10U)
42736 #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ100_EN0_SHIFT (4U)
42737 /*! REQ100_EN0 - Writing a 1 to REQ100_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */
42738 #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ100_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ100_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ100_EN0_MASK)
42739 
42740 #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ101_EN0_MASK (0x20U)
42741 #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ101_EN0_SHIFT (5U)
42742 /*! REQ101_EN0 - Writing a 1 to REQ101_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */
42743 #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ101_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ101_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ101_EN0_MASK)
42744 
42745 #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ102_EN0_MASK (0x40U)
42746 #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ102_EN0_SHIFT (6U)
42747 /*! REQ102_EN0 - Writing a 1 to REQ102_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */
42748 #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ102_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ102_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ102_EN0_MASK)
42749 
42750 #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ103_EN0_MASK (0x80U)
42751 #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ103_EN0_SHIFT (7U)
42752 /*! REQ103_EN0 - Writing a 1 to REQ103_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */
42753 #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ103_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ103_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ103_EN0_MASK)
42754 
42755 #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ104_EN0_MASK (0x100U)
42756 #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ104_EN0_SHIFT (8U)
42757 /*! REQ104_EN0 - Writing a 1 to REQ104_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */
42758 #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ104_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ104_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ104_EN0_MASK)
42759 
42760 #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ105_EN0_MASK (0x200U)
42761 #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ105_EN0_SHIFT (9U)
42762 /*! REQ105_EN0 - Writing a 1 to REQ105_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */
42763 #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ105_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ105_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ105_EN0_MASK)
42764 
42765 #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ106_EN0_MASK (0x400U)
42766 #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ106_EN0_SHIFT (10U)
42767 /*! REQ106_EN0 - Writing a 1 to REQ106_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */
42768 #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ106_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ106_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ106_EN0_MASK)
42769 
42770 #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ107_EN0_MASK (0x800U)
42771 #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ107_EN0_SHIFT (11U)
42772 /*! REQ107_EN0 - Writing a 1 to REQ107_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */
42773 #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ107_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ107_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ107_EN0_MASK)
42774 
42775 #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ108_EN0_MASK (0x1000U)
42776 #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ108_EN0_SHIFT (12U)
42777 /*! REQ108_EN0 - Writing a 1 to REQ108_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */
42778 #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ108_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ108_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ108_EN0_MASK)
42779 
42780 #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ109_EN0_MASK (0x2000U)
42781 #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ109_EN0_SHIFT (13U)
42782 /*! REQ109_EN0 - Writing a 1 to REQ109_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */
42783 #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ109_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ109_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ109_EN0_MASK)
42784 
42785 #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ110_EN0_MASK (0x4000U)
42786 #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ110_EN0_SHIFT (14U)
42787 /*! REQ110_EN0 - Writing a 1 to REQ110_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */
42788 #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ110_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ110_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ110_EN0_MASK)
42789 
42790 #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ111_EN0_MASK (0x8000U)
42791 #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ111_EN0_SHIFT (15U)
42792 /*! REQ111_EN0 - Writing a 1 to REQ111_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */
42793 #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ111_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ111_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ111_EN0_MASK)
42794 
42795 #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ112_EN0_MASK (0x10000U)
42796 #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ112_EN0_SHIFT (16U)
42797 /*! REQ112_EN0 - Writing a 1 to REQ112_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */
42798 #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ112_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ112_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ112_EN0_MASK)
42799 
42800 #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ113_EN0_MASK (0x20000U)
42801 #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ113_EN0_SHIFT (17U)
42802 /*! REQ113_EN0 - Writing a 1 to REQ113_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */
42803 #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ113_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ113_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ113_EN0_MASK)
42804 
42805 #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ114_EN0_MASK (0x40000U)
42806 #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ114_EN0_SHIFT (18U)
42807 /*! REQ114_EN0 - Writing a 1 to REQ114_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */
42808 #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ114_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ114_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ114_EN0_MASK)
42809 
42810 #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ115_EN0_MASK (0x80000U)
42811 #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ115_EN0_SHIFT (19U)
42812 /*! REQ115_EN0 - Writing a 1 to REQ115_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */
42813 #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ115_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ115_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ115_EN0_MASK)
42814 
42815 #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ116_EN0_MASK (0x100000U)
42816 #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ116_EN0_SHIFT (20U)
42817 /*! REQ116_EN0 - Writing a 1 to REQ116_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */
42818 #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ116_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ116_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ116_EN0_MASK)
42819 
42820 #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ117_EN0_MASK (0x200000U)
42821 #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ117_EN0_SHIFT (21U)
42822 /*! REQ117_EN0 - Writing a 1 to REQ117_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */
42823 #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ117_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ117_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ117_EN0_MASK)
42824 
42825 #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ118_EN0_MASK (0x400000U)
42826 #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ118_EN0_SHIFT (22U)
42827 /*! REQ118_EN0 - Writing a 1 to REQ118_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */
42828 #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ118_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ118_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ118_EN0_MASK)
42829 
42830 #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ119_EN0_MASK (0x800000U)
42831 #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ119_EN0_SHIFT (23U)
42832 /*! REQ119_EN0 - Writing a 1 to REQ119_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */
42833 #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ119_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ119_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ119_EN0_MASK)
42834 
42835 #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ120_EN0_MASK (0x1000000U)
42836 #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ120_EN0_SHIFT (24U)
42837 /*! REQ120_EN0 - Writing a 1 to REQ120_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */
42838 #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ120_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ120_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ120_EN0_MASK)
42839 
42840 #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ121_EN0_MASK (0x2000000U)
42841 #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ121_EN0_SHIFT (25U)
42842 /*! REQ121_EN0 - Writing a 1 to REQ121_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */
42843 #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ121_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ121_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ121_EN0_MASK)
42844 /*! @} */
42845 
42846 /*! @name DMA1_REQ_ENABLE0 - DMA1 Request Enable0 */
42847 /*! @{ */
42848 
42849 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ1_EN1_MASK  (0x2U)
42850 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ1_EN1_SHIFT (1U)
42851 /*! REQ1_EN1 - This register is used to enable and disable FLEXSPI0 receive event request.
42852  *  0b0..Disable
42853  *  0b1..Enable
42854  */
42855 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ1_EN1(x)    (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ1_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ1_EN1_MASK)
42856 
42857 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ2_EN1_MASK  (0x4U)
42858 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ2_EN1_SHIFT (2U)
42859 /*! REQ2_EN1 - This register is used to enable and disable FLEXSPI0 transmit event request.
42860  *  0b0..Disable
42861  *  0b1..Enable
42862  */
42863 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ2_EN1(x)    (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ2_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ2_EN1_MASK)
42864 
42865 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ3_EN1_MASK  (0x8U)
42866 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ3_EN1_SHIFT (3U)
42867 /*! REQ3_EN1 - This register is used to enable and disable PINT0 INT0 request.
42868  *  0b0..Disable
42869  *  0b1..Enable
42870  */
42871 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ3_EN1(x)    (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ3_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ3_EN1_MASK)
42872 
42873 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ4_EN1_MASK  (0x10U)
42874 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ4_EN1_SHIFT (4U)
42875 /*! REQ4_EN1 - This register is used to enable and disable PINT0 INT1 request.
42876  *  0b0..Disable
42877  *  0b1..Enable
42878  */
42879 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ4_EN1(x)    (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ4_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ4_EN1_MASK)
42880 
42881 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ5_EN1_MASK  (0x20U)
42882 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ5_EN1_SHIFT (5U)
42883 /*! REQ5_EN1 - This register is used to enable and disable PINT0 INT2 request.
42884  *  0b0..Disable
42885  *  0b1..Enable
42886  */
42887 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ5_EN1(x)    (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ5_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ5_EN1_MASK)
42888 
42889 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ6_EN1_MASK  (0x40U)
42890 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ6_EN1_SHIFT (6U)
42891 /*! REQ6_EN1 - This register is used to enable and disable PINT0 INT3 request.
42892  *  0b0..Disable
42893  *  0b1..Enable
42894  */
42895 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ6_EN1(x)    (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ6_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ6_EN1_MASK)
42896 
42897 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ7_EN1_MASK  (0x80U)
42898 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ7_EN1_SHIFT (7U)
42899 /*! REQ7_EN1 - This register is used to enable and disable CTIMER0 DMAREQ_M0 request.
42900  *  0b0..Disable
42901  *  0b1..Enable
42902  */
42903 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ7_EN1(x)    (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ7_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ7_EN1_MASK)
42904 
42905 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ8_EN1_MASK  (0x100U)
42906 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ8_EN1_SHIFT (8U)
42907 /*! REQ8_EN1 - This register is used to enable and disable CTIMER0 DMAREQ_M1 request.
42908  *  0b0..Disable
42909  *  0b1..Enable
42910  */
42911 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ8_EN1(x)    (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ8_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ8_EN1_MASK)
42912 
42913 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ9_EN1_MASK  (0x200U)
42914 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ9_EN1_SHIFT (9U)
42915 /*! REQ9_EN1 - This register is used to enable and disable CTIMER1 DMAREQ_M0 request.
42916  *  0b0..Disable
42917  *  0b1..Enable
42918  */
42919 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ9_EN1(x)    (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ9_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ9_EN1_MASK)
42920 
42921 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ10_EN1_MASK (0x400U)
42922 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ10_EN1_SHIFT (10U)
42923 /*! REQ10_EN1 - This register is used to enable and disable CTIMER1 DMAREQ_M1 request.
42924  *  0b0..Disable
42925  *  0b1..Enable
42926  */
42927 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ10_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ10_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ10_EN1_MASK)
42928 
42929 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ11_EN1_MASK (0x800U)
42930 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ11_EN1_SHIFT (11U)
42931 /*! REQ11_EN1 - This register is used to enable and disable CTIMER2 DMAREQ_M0 request.
42932  *  0b0..Disable
42933  *  0b1..Enable
42934  */
42935 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ11_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ11_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ11_EN1_MASK)
42936 
42937 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ12_EN1_MASK (0x1000U)
42938 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ12_EN1_SHIFT (12U)
42939 /*! REQ12_EN1 - This register is used to enable and disable CTIMER2 DMAREQ_M1 request.
42940  *  0b0..Disable
42941  *  0b1..Enable
42942  */
42943 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ12_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ12_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ12_EN1_MASK)
42944 
42945 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ13_EN1_MASK (0x2000U)
42946 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ13_EN1_SHIFT (13U)
42947 /*! REQ13_EN1 - This register is used to enable and disable CTIMER3 DMAREQ_M0 request.
42948  *  0b0..Disable
42949  *  0b1..Enable
42950  */
42951 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ13_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ13_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ13_EN1_MASK)
42952 
42953 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ14_EN1_MASK (0x4000U)
42954 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ14_EN1_SHIFT (14U)
42955 /*! REQ14_EN1 - This register is used to enable and disable CTIMER3 DMAREQ_M1 request.
42956  *  0b0..Disable
42957  *  0b1..Enable
42958  */
42959 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ14_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ14_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ14_EN1_MASK)
42960 
42961 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ15_EN1_MASK (0x8000U)
42962 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ15_EN1_SHIFT (15U)
42963 /*! REQ15_EN1 - This register is used to enable and disable CTIMER4 DMAREQ_M0 request.
42964  *  0b0..Disable
42965  *  0b1..Enable
42966  */
42967 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ15_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ15_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ15_EN1_MASK)
42968 
42969 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ16_EN1_MASK (0x10000U)
42970 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ16_EN1_SHIFT (16U)
42971 /*! REQ16_EN1 - This register is used to enable and disable CTIMER4 DMAREQ_M1 request.
42972  *  0b0..Disable
42973  *  0b1..Enable
42974  */
42975 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ16_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ16_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ16_EN1_MASK)
42976 
42977 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ17_EN1_MASK (0x20000U)
42978 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ17_EN1_SHIFT (17U)
42979 /*! REQ17_EN1 - This register is used to enable and disable WUU0 wake up event request.
42980  *  0b0..Disable
42981  *  0b1..Enable
42982  */
42983 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ17_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ17_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ17_EN1_MASK)
42984 
42985 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ18_EN1_MASK (0x40000U)
42986 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ18_EN1_SHIFT (18U)
42987 /*! REQ18_EN1 - This register is used to enable and disable MICFIL0 FIFO_request.
42988  *  0b0..Disable
42989  *  0b1..Enable
42990  */
42991 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ18_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ18_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ18_EN1_MASK)
42992 
42993 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ19_EN1_MASK (0x80000U)
42994 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ19_EN1_SHIFT (19U)
42995 /*! REQ19_EN1 - This register is used to enable and disable SCT0 DMA0 request.
42996  *  0b0..Disable
42997  *  0b1..Enable
42998  */
42999 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ19_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ19_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ19_EN1_MASK)
43000 
43001 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ20_EN1_MASK (0x100000U)
43002 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ20_EN1_SHIFT (20U)
43003 /*! REQ20_EN1 - This register is used to enable and disable SCT0 DMA1 request.
43004  *  0b0..Disable
43005  *  0b1..Enable
43006  */
43007 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ20_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ20_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ20_EN1_MASK)
43008 
43009 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ21_EN1_MASK (0x200000U)
43010 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ21_EN1_SHIFT (21U)
43011 /*! REQ21_EN1 - This register is used to enable and disable ADC0 FIFO A request.
43012  *  0b0..Disable
43013  *  0b1..Enable
43014  */
43015 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ21_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ21_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ21_EN1_MASK)
43016 
43017 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ22_EN1_MASK (0x400000U)
43018 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ22_EN1_SHIFT (22U)
43019 /*! REQ22_EN1 - This register is used to enable and disable ADC0 FIFO B request.
43020  *  0b0..Disable
43021  *  0b1..Enable
43022  */
43023 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ22_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ22_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ22_EN1_MASK)
43024 
43025 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ23_EN1_MASK (0x800000U)
43026 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ23_EN1_SHIFT (23U)
43027 /*! REQ23_EN1 - This register is used to enable and disable ADC1 FIFO A request.
43028  *  0b0..Disable
43029  *  0b1..Enable
43030  */
43031 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ23_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ23_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ23_EN1_MASK)
43032 
43033 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ24_EN1_MASK (0x1000000U)
43034 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ24_EN1_SHIFT (24U)
43035 /*! REQ24_EN1 - This register is used to enable and disable ADC1 FIFO B request.
43036  *  0b0..Disable
43037  *  0b1..Enable
43038  */
43039 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ24_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ24_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ24_EN1_MASK)
43040 
43041 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ25_EN1_MASK (0x2000000U)
43042 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ25_EN1_SHIFT (25U)
43043 /*! REQ25_EN1 - This register is used to enable and disable DAC0 FIFO_request.
43044  *  0b0..Disable
43045  *  0b1..Enable
43046  */
43047 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ25_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ25_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ25_EN1_MASK)
43048 
43049 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ26_EN1_MASK (0x4000000U)
43050 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ26_EN1_SHIFT (26U)
43051 /*! REQ26_EN1 - This register is used to enable and disable DAC1 FIFO_request.
43052  *  0b0..Disable
43053  *  0b1..Enable
43054  */
43055 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ26_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ26_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ26_EN1_MASK)
43056 
43057 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ27_EN1_MASK (0x8000000U)
43058 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ27_EN1_SHIFT (27U)
43059 /*! REQ27_EN1 - This register is used to enable and disable DAC2 FIFO_request.
43060  *  0b0..Disable
43061  *  0b1..Enable
43062  */
43063 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ27_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ27_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ27_EN1_MASK)
43064 
43065 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ28_EN1_MASK (0x10000000U)
43066 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ28_EN1_SHIFT (28U)
43067 /*! REQ28_EN1 - This register is used to enable and disable CMP0 DMA_request.
43068  *  0b0..Disable
43069  *  0b1..Enable
43070  */
43071 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ28_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ28_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ28_EN1_MASK)
43072 
43073 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ29_EN1_MASK (0x20000000U)
43074 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ29_EN1_SHIFT (29U)
43075 /*! REQ29_EN1 - This register is used to enable and disable CMP1 DMA_request.
43076  *  0b0..Disable
43077  *  0b1..Enable
43078  */
43079 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ29_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ29_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ29_EN1_MASK)
43080 
43081 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ30_EN1_MASK (0x40000000U)
43082 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ30_EN1_SHIFT (30U)
43083 /*! REQ30_EN1 - This register is used to enable and disable CMP2 DMA_request.
43084  *  0b0..Disable
43085  *  0b1..Enable
43086  */
43087 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ30_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ30_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ30_EN1_MASK)
43088 
43089 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ31_EN1_MASK (0x80000000U)
43090 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ31_EN1_SHIFT (31U)
43091 /*! REQ31_EN1 - This register is used to enable and disable EVTG0 OUT0A request.
43092  *  0b0..Disable
43093  *  0b1..Enable
43094  */
43095 #define INPUTMUX_DMA1_REQ_ENABLE0_REQ31_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ31_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ31_EN1_MASK)
43096 /*! @} */
43097 
43098 /*! @name DMA1_REQ_ENABLE0_SET - DMA1 Request Enable0 */
43099 /*! @{ */
43100 
43101 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ1_EN1_MASK (0x2U)
43102 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ1_EN1_SHIFT (1U)
43103 /*! REQ1_EN1 - Writing a 1 to REQ1_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */
43104 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ1_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ1_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ1_EN1_MASK)
43105 
43106 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ2_EN1_MASK (0x4U)
43107 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ2_EN1_SHIFT (2U)
43108 /*! REQ2_EN1 - Writing a 1 to REQ2_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */
43109 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ2_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ2_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ2_EN1_MASK)
43110 
43111 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ3_EN1_MASK (0x8U)
43112 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ3_EN1_SHIFT (3U)
43113 /*! REQ3_EN1 - Writing a 1 to REQ3_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */
43114 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ3_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ3_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ3_EN1_MASK)
43115 
43116 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ4_EN1_MASK (0x10U)
43117 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ4_EN1_SHIFT (4U)
43118 /*! REQ4_EN1 - Writing a 1 to REQ4_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */
43119 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ4_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ4_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ4_EN1_MASK)
43120 
43121 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ5_EN1_MASK (0x20U)
43122 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ5_EN1_SHIFT (5U)
43123 /*! REQ5_EN1 - Writing a 1 to REQ5_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */
43124 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ5_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ5_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ5_EN1_MASK)
43125 
43126 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ6_EN1_MASK (0x40U)
43127 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ6_EN1_SHIFT (6U)
43128 /*! REQ6_EN1 - Writing a 1 to REQ6_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */
43129 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ6_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ6_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ6_EN1_MASK)
43130 
43131 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ7_EN1_MASK (0x80U)
43132 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ7_EN1_SHIFT (7U)
43133 /*! REQ7_EN1 - Writing a 1 to REQ7_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */
43134 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ7_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ7_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ7_EN1_MASK)
43135 
43136 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ8_EN1_MASK (0x100U)
43137 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ8_EN1_SHIFT (8U)
43138 /*! REQ8_EN1 - Writing a 1 to REQ8_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */
43139 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ8_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ8_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ8_EN1_MASK)
43140 
43141 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ9_EN1_MASK (0x200U)
43142 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ9_EN1_SHIFT (9U)
43143 /*! REQ9_EN1 - Writing a 1 to REQ9_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */
43144 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ9_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ9_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ9_EN1_MASK)
43145 
43146 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ10_EN1_MASK (0x400U)
43147 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ10_EN1_SHIFT (10U)
43148 /*! REQ10_EN1 - Writing a 1 to REQ10_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */
43149 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ10_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ10_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ10_EN1_MASK)
43150 
43151 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ11_EN1_MASK (0x800U)
43152 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ11_EN1_SHIFT (11U)
43153 /*! REQ11_EN1 - Writing a 1 to REQ11_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */
43154 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ11_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ11_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ11_EN1_MASK)
43155 
43156 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ12_EN1_MASK (0x1000U)
43157 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ12_EN1_SHIFT (12U)
43158 /*! REQ12_EN1 - Writing a 1 to REQ12_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */
43159 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ12_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ12_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ12_EN1_MASK)
43160 
43161 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ13_EN1_MASK (0x2000U)
43162 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ13_EN1_SHIFT (13U)
43163 /*! REQ13_EN1 - Writing a 1 to REQ13_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */
43164 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ13_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ13_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ13_EN1_MASK)
43165 
43166 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ14_EN1_MASK (0x4000U)
43167 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ14_EN1_SHIFT (14U)
43168 /*! REQ14_EN1 - Writing a 1 to REQ14_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */
43169 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ14_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ14_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ14_EN1_MASK)
43170 
43171 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ15_EN1_MASK (0x8000U)
43172 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ15_EN1_SHIFT (15U)
43173 /*! REQ15_EN1 - Writing a 1 to REQ15_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */
43174 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ15_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ15_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ15_EN1_MASK)
43175 
43176 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ16_EN1_MASK (0x10000U)
43177 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ16_EN1_SHIFT (16U)
43178 /*! REQ16_EN1 - Writing a 1 to REQ16_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */
43179 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ16_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ16_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ16_EN1_MASK)
43180 
43181 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ17_EN1_MASK (0x20000U)
43182 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ17_EN1_SHIFT (17U)
43183 /*! REQ17_EN1 - Writing a 1 to REQ17_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */
43184 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ17_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ17_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ17_EN1_MASK)
43185 
43186 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ18_EN1_MASK (0x40000U)
43187 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ18_EN1_SHIFT (18U)
43188 /*! REQ18_EN1 - Writing a 1 to REQ18_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */
43189 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ18_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ18_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ18_EN1_MASK)
43190 
43191 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ19_EN1_MASK (0x80000U)
43192 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ19_EN1_SHIFT (19U)
43193 /*! REQ19_EN1 - Writing a 1 to REQ19_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */
43194 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ19_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ19_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ19_EN1_MASK)
43195 
43196 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ20_EN1_MASK (0x100000U)
43197 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ20_EN1_SHIFT (20U)
43198 /*! REQ20_EN1 - Writing a 1 to REQ20_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */
43199 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ20_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ20_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ20_EN1_MASK)
43200 
43201 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ21_EN1_MASK (0x200000U)
43202 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ21_EN1_SHIFT (21U)
43203 /*! REQ21_EN1 - Writing a 1 to REQ21_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */
43204 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ21_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ21_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ21_EN1_MASK)
43205 
43206 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ22_EN1_MASK (0x400000U)
43207 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ22_EN1_SHIFT (22U)
43208 /*! REQ22_EN1 - Writing a 1 to REQ22_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */
43209 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ22_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ22_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ22_EN1_MASK)
43210 
43211 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ23_EN1_MASK (0x800000U)
43212 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ23_EN1_SHIFT (23U)
43213 /*! REQ23_EN1 - Writing a 1 to REQ23_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */
43214 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ23_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ23_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ23_EN1_MASK)
43215 
43216 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ24_EN1_MASK (0x1000000U)
43217 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ24_EN1_SHIFT (24U)
43218 /*! REQ24_EN1 - Writing a 1 to REQ24_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */
43219 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ24_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ24_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ24_EN1_MASK)
43220 
43221 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ25_EN1_MASK (0x2000000U)
43222 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ25_EN1_SHIFT (25U)
43223 /*! REQ25_EN1 - Writing a 1 to REQ25_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */
43224 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ25_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ25_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ25_EN1_MASK)
43225 
43226 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ26_EN1_MASK (0x4000000U)
43227 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ26_EN1_SHIFT (26U)
43228 /*! REQ26_EN1 - Writing a 1 to REQ26_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */
43229 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ26_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ26_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ26_EN1_MASK)
43230 
43231 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ27_EN1_MASK (0x8000000U)
43232 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ27_EN1_SHIFT (27U)
43233 /*! REQ27_EN1 - Writing a 1 to REQ27_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */
43234 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ27_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ27_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ27_EN1_MASK)
43235 
43236 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ28_EN1_MASK (0x10000000U)
43237 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ28_EN1_SHIFT (28U)
43238 /*! REQ28_EN1 - Writing a 1 to REQ28_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */
43239 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ28_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ28_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ28_EN1_MASK)
43240 
43241 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ29_EN1_MASK (0x20000000U)
43242 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ29_EN1_SHIFT (29U)
43243 /*! REQ29_EN1 - Writing a 1 to REQ29_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */
43244 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ29_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ29_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ29_EN1_MASK)
43245 
43246 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ30_EN1_MASK (0x40000000U)
43247 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ30_EN1_SHIFT (30U)
43248 /*! REQ30_EN1 - Writing a 1 to REQ30_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */
43249 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ30_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ30_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ30_EN1_MASK)
43250 
43251 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ31_EN1_MASK (0x80000000U)
43252 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ31_EN1_SHIFT (31U)
43253 /*! REQ31_EN1 - Writing a 1 to REQ31_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */
43254 #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ31_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ31_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ31_EN1_MASK)
43255 /*! @} */
43256 
43257 /*! @name DMA1_REQ_ENABLE0_CLR - DMA1 Request Enable0 */
43258 /*! @{ */
43259 
43260 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ1_EN1_MASK (0x2U)
43261 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ1_EN1_SHIFT (1U)
43262 /*! REQ1_EN1 - Writing a 1 to REQ1_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */
43263 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ1_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ1_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ1_EN1_MASK)
43264 
43265 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ2_EN1_MASK (0x4U)
43266 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ2_EN1_SHIFT (2U)
43267 /*! REQ2_EN1 - Writing a 1 to REQ2_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */
43268 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ2_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ2_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ2_EN1_MASK)
43269 
43270 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ3_EN1_MASK (0x8U)
43271 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ3_EN1_SHIFT (3U)
43272 /*! REQ3_EN1 - Writing a 1 to REQ3_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */
43273 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ3_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ3_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ3_EN1_MASK)
43274 
43275 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ4_EN1_MASK (0x10U)
43276 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ4_EN1_SHIFT (4U)
43277 /*! REQ4_EN1 - Writing a 1 to REQ4_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */
43278 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ4_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ4_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ4_EN1_MASK)
43279 
43280 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ5_EN1_MASK (0x20U)
43281 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ5_EN1_SHIFT (5U)
43282 /*! REQ5_EN1 - Writing a 1 to REQ5_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */
43283 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ5_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ5_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ5_EN1_MASK)
43284 
43285 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ6_EN1_MASK (0x40U)
43286 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ6_EN1_SHIFT (6U)
43287 /*! REQ6_EN1 - Writing a 1 to REQ6_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */
43288 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ6_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ6_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ6_EN1_MASK)
43289 
43290 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ7_EN1_MASK (0x80U)
43291 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ7_EN1_SHIFT (7U)
43292 /*! REQ7_EN1 - Writing a 1 to REQ7_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */
43293 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ7_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ7_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ7_EN1_MASK)
43294 
43295 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ8_EN1_MASK (0x100U)
43296 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ8_EN1_SHIFT (8U)
43297 /*! REQ8_EN1 - Writing a 1 to REQ8_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */
43298 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ8_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ8_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ8_EN1_MASK)
43299 
43300 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ9_EN1_MASK (0x200U)
43301 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ9_EN1_SHIFT (9U)
43302 /*! REQ9_EN1 - Writing a 1 to REQ9_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */
43303 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ9_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ9_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ9_EN1_MASK)
43304 
43305 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ10_EN1_MASK (0x400U)
43306 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ10_EN1_SHIFT (10U)
43307 /*! REQ10_EN1 - Writing a 1 to REQ10_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */
43308 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ10_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ10_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ10_EN1_MASK)
43309 
43310 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ11_EN1_MASK (0x800U)
43311 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ11_EN1_SHIFT (11U)
43312 /*! REQ11_EN1 - Writing a 1 to REQ11_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */
43313 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ11_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ11_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ11_EN1_MASK)
43314 
43315 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ12_EN1_MASK (0x1000U)
43316 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ12_EN1_SHIFT (12U)
43317 /*! REQ12_EN1 - Writing a 1 to REQ12_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */
43318 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ12_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ12_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ12_EN1_MASK)
43319 
43320 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ13_EN1_MASK (0x2000U)
43321 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ13_EN1_SHIFT (13U)
43322 /*! REQ13_EN1 - Writing a 1 to REQ13_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */
43323 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ13_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ13_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ13_EN1_MASK)
43324 
43325 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ14_EN1_MASK (0x4000U)
43326 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ14_EN1_SHIFT (14U)
43327 /*! REQ14_EN1 - Writing a 1 to REQ14_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */
43328 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ14_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ14_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ14_EN1_MASK)
43329 
43330 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ15_EN1_MASK (0x8000U)
43331 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ15_EN1_SHIFT (15U)
43332 /*! REQ15_EN1 - Writing a 1 to REQ15_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */
43333 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ15_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ15_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ15_EN1_MASK)
43334 
43335 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ16_EN1_MASK (0x10000U)
43336 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ16_EN1_SHIFT (16U)
43337 /*! REQ16_EN1 - Writing a 1 to REQ16_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */
43338 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ16_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ16_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ16_EN1_MASK)
43339 
43340 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ17_EN1_MASK (0x20000U)
43341 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ17_EN1_SHIFT (17U)
43342 /*! REQ17_EN1 - Writing a 1 to REQ17_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */
43343 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ17_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ17_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ17_EN1_MASK)
43344 
43345 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ18_EN1_MASK (0x40000U)
43346 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ18_EN1_SHIFT (18U)
43347 /*! REQ18_EN1 - Writing a 1 to REQ18_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */
43348 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ18_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ18_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ18_EN1_MASK)
43349 
43350 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ19_EN1_MASK (0x80000U)
43351 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ19_EN1_SHIFT (19U)
43352 /*! REQ19_EN1 - Writing a 1 to REQ19_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */
43353 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ19_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ19_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ19_EN1_MASK)
43354 
43355 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ20_EN1_MASK (0x100000U)
43356 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ20_EN1_SHIFT (20U)
43357 /*! REQ20_EN1 - Writing a 1 to REQ20_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */
43358 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ20_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ20_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ20_EN1_MASK)
43359 
43360 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ21_EN1_MASK (0x200000U)
43361 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ21_EN1_SHIFT (21U)
43362 /*! REQ21_EN1 - Writing a 1 to REQ21_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */
43363 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ21_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ21_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ21_EN1_MASK)
43364 
43365 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ22_EN1_MASK (0x400000U)
43366 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ22_EN1_SHIFT (22U)
43367 /*! REQ22_EN1 - Writing a 1 to REQ22_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */
43368 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ22_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ22_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ22_EN1_MASK)
43369 
43370 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ23_EN1_MASK (0x800000U)
43371 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ23_EN1_SHIFT (23U)
43372 /*! REQ23_EN1 - Writing a 1 to REQ23_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */
43373 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ23_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ23_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ23_EN1_MASK)
43374 
43375 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ24_EN1_MASK (0x1000000U)
43376 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ24_EN1_SHIFT (24U)
43377 /*! REQ24_EN1 - Writing a 1 to REQ24_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */
43378 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ24_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ24_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ24_EN1_MASK)
43379 
43380 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ25_EN1_MASK (0x2000000U)
43381 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ25_EN1_SHIFT (25U)
43382 /*! REQ25_EN1 - Writing a 1 to REQ25_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */
43383 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ25_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ25_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ25_EN1_MASK)
43384 
43385 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ26_EN1_MASK (0x4000000U)
43386 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ26_EN1_SHIFT (26U)
43387 /*! REQ26_EN1 - Writing a 1 to REQ26_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */
43388 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ26_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ26_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ26_EN1_MASK)
43389 
43390 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ27_EN1_MASK (0x8000000U)
43391 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ27_EN1_SHIFT (27U)
43392 /*! REQ27_EN1 - Writing a 1 to REQ27_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */
43393 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ27_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ27_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ27_EN1_MASK)
43394 
43395 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ28_EN1_MASK (0x10000000U)
43396 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ28_EN1_SHIFT (28U)
43397 /*! REQ28_EN1 - Writing a 1 to REQ28_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */
43398 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ28_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ28_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ28_EN1_MASK)
43399 
43400 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ29_EN1_MASK (0x20000000U)
43401 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ29_EN1_SHIFT (29U)
43402 /*! REQ29_EN1 - Writing a 1 to REQ29_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */
43403 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ29_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ29_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ29_EN1_MASK)
43404 
43405 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ30_EN1_MASK (0x40000000U)
43406 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ30_EN1_SHIFT (30U)
43407 /*! REQ30_EN1 - Writing a 1 to REQ30_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */
43408 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ30_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ30_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ30_EN1_MASK)
43409 
43410 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ31_EN1_MASK (0x80000000U)
43411 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ31_EN1_SHIFT (31U)
43412 /*! REQ31_EN1 - Writing a 1 to REQ31_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */
43413 #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ31_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ31_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ31_EN1_MASK)
43414 /*! @} */
43415 
43416 /*! @name DMA1_REQ_ENABLE0_TOG - DMA1 Request Enable0 */
43417 /*! @{ */
43418 
43419 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ1_EN1_MASK (0x2U)
43420 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ1_EN1_SHIFT (1U)
43421 /*! REQ1_EN1 - Writing a 1 to REQ1_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */
43422 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ1_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ1_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ1_EN1_MASK)
43423 
43424 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ2_EN1_MASK (0x4U)
43425 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ2_EN1_SHIFT (2U)
43426 /*! REQ2_EN1 - Writing a 1 to REQ2_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */
43427 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ2_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ2_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ2_EN1_MASK)
43428 
43429 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ3_EN1_MASK (0x8U)
43430 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ3_EN1_SHIFT (3U)
43431 /*! REQ3_EN1 - Writing a 1 to REQ3_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */
43432 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ3_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ3_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ3_EN1_MASK)
43433 
43434 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ4_EN1_MASK (0x10U)
43435 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ4_EN1_SHIFT (4U)
43436 /*! REQ4_EN1 - Writing a 1 to REQ4_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */
43437 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ4_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ4_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ4_EN1_MASK)
43438 
43439 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ5_EN1_MASK (0x20U)
43440 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ5_EN1_SHIFT (5U)
43441 /*! REQ5_EN1 - Writing a 1 to REQ5_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */
43442 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ5_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ5_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ5_EN1_MASK)
43443 
43444 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ6_EN1_MASK (0x40U)
43445 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ6_EN1_SHIFT (6U)
43446 /*! REQ6_EN1 - Writing a 1 to REQ6_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */
43447 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ6_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ6_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ6_EN1_MASK)
43448 
43449 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ7_EN1_MASK (0x80U)
43450 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ7_EN1_SHIFT (7U)
43451 /*! REQ7_EN1 - Writing a 1 to REQ7_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */
43452 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ7_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ7_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ7_EN1_MASK)
43453 
43454 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ8_EN1_MASK (0x100U)
43455 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ8_EN1_SHIFT (8U)
43456 /*! REQ8_EN1 - Writing a 1 to REQ8_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */
43457 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ8_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ8_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ8_EN1_MASK)
43458 
43459 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ9_EN1_MASK (0x200U)
43460 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ9_EN1_SHIFT (9U)
43461 /*! REQ9_EN1 - Writing a 1 to RE9_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */
43462 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ9_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ9_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ9_EN1_MASK)
43463 
43464 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ10_EN1_MASK (0x400U)
43465 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ10_EN1_SHIFT (10U)
43466 /*! REQ10_EN1 - Writing a 1 to REQ10_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */
43467 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ10_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ10_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ10_EN1_MASK)
43468 
43469 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ11_EN1_MASK (0x800U)
43470 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ11_EN1_SHIFT (11U)
43471 /*! REQ11_EN1 - Writing a 1 to REQ11_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */
43472 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ11_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ11_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ11_EN1_MASK)
43473 
43474 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ12_EN1_MASK (0x1000U)
43475 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ12_EN1_SHIFT (12U)
43476 /*! REQ12_EN1 - Writing a 1 to REQ12_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */
43477 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ12_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ12_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ12_EN1_MASK)
43478 
43479 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ13_EN1_MASK (0x2000U)
43480 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ13_EN1_SHIFT (13U)
43481 /*! REQ13_EN1 - Writing a 1 to REQ13_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */
43482 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ13_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ13_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ13_EN1_MASK)
43483 
43484 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ14_EN1_MASK (0x4000U)
43485 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ14_EN1_SHIFT (14U)
43486 /*! REQ14_EN1 - Writing a 1 to REQ14_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */
43487 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ14_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ14_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ14_EN1_MASK)
43488 
43489 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ15_EN1_MASK (0x8000U)
43490 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ15_EN1_SHIFT (15U)
43491 /*! REQ15_EN1 - Writing a 1 to REQ15_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */
43492 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ15_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ15_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ15_EN1_MASK)
43493 
43494 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ16_EN1_MASK (0x10000U)
43495 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ16_EN1_SHIFT (16U)
43496 /*! REQ16_EN1 - Writing a 1 to REQ16_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */
43497 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ16_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ16_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ16_EN1_MASK)
43498 
43499 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ17_EN1_MASK (0x20000U)
43500 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ17_EN1_SHIFT (17U)
43501 /*! REQ17_EN1 - Writing a 1 to REQ17_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */
43502 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ17_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ17_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ17_EN1_MASK)
43503 
43504 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ18_EN1_MASK (0x40000U)
43505 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ18_EN1_SHIFT (18U)
43506 /*! REQ18_EN1 - Writing a 1 to REQ18_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */
43507 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ18_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ18_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ18_EN1_MASK)
43508 
43509 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ19_EN1_MASK (0x80000U)
43510 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ19_EN1_SHIFT (19U)
43511 /*! REQ19_EN1 - Writing a 1 to REQ19_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */
43512 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ19_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ19_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ19_EN1_MASK)
43513 
43514 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ20_EN1_MASK (0x100000U)
43515 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ20_EN1_SHIFT (20U)
43516 /*! REQ20_EN1 - Writing a 1 to REQ20_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */
43517 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ20_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ20_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ20_EN1_MASK)
43518 
43519 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ21_EN1_MASK (0x200000U)
43520 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ21_EN1_SHIFT (21U)
43521 /*! REQ21_EN1 - Writing a 1 to REQ21_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */
43522 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ21_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ21_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ21_EN1_MASK)
43523 
43524 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ22_EN1_MASK (0x400000U)
43525 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ22_EN1_SHIFT (22U)
43526 /*! REQ22_EN1 - Writing a 1 to REQ22_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */
43527 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ22_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ22_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ22_EN1_MASK)
43528 
43529 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ23_EN1_MASK (0x800000U)
43530 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ23_EN1_SHIFT (23U)
43531 /*! REQ23_EN1 - Writing a 1 to REQ23_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */
43532 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ23_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ23_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ23_EN1_MASK)
43533 
43534 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ24_EN1_MASK (0x1000000U)
43535 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ24_EN1_SHIFT (24U)
43536 /*! REQ24_EN1 - Writing a 1 to REQ24_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */
43537 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ24_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ24_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ24_EN1_MASK)
43538 
43539 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ25_EN1_MASK (0x2000000U)
43540 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ25_EN1_SHIFT (25U)
43541 /*! REQ25_EN1 - Writing a 1 to REQ25_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */
43542 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ25_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ25_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ25_EN1_MASK)
43543 
43544 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ26_EN1_MASK (0x4000000U)
43545 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ26_EN1_SHIFT (26U)
43546 /*! REQ26_EN1 - Writing a 1 to REQ26_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */
43547 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ26_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ26_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ26_EN1_MASK)
43548 
43549 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ27_EN1_MASK (0x8000000U)
43550 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ27_EN1_SHIFT (27U)
43551 /*! REQ27_EN1 - Writing a 1 to REQ27_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */
43552 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ27_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ27_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ27_EN1_MASK)
43553 
43554 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ28_EN1_MASK (0x10000000U)
43555 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ28_EN1_SHIFT (28U)
43556 /*! REQ28_EN1 - Writing a 1 to REQ28_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */
43557 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ28_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ28_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ28_EN1_MASK)
43558 
43559 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ29_EN1_MASK (0x20000000U)
43560 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ29_EN1_SHIFT (29U)
43561 /*! REQ29_EN1 - Writing a 1 to REQ29_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */
43562 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ29_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ29_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ29_EN1_MASK)
43563 
43564 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ30_EN1_MASK (0x40000000U)
43565 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ30_EN1_SHIFT (30U)
43566 /*! REQ30_EN1 - Writing a 1 to REQ30_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */
43567 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ30_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ30_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ30_EN1_MASK)
43568 
43569 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ31_EN1_MASK (0x80000000U)
43570 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ31_EN1_SHIFT (31U)
43571 /*! REQ31_EN1 - Writing a 1 to REQ31_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */
43572 #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ31_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ31_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ31_EN1_MASK)
43573 /*! @} */
43574 
43575 /*! @name DMA1_REQ_ENABLE1 - DMA1 Request Enable1 */
43576 /*! @{ */
43577 
43578 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ32_EN1_MASK (0x1U)
43579 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ32_EN1_SHIFT (0U)
43580 /*! REQ32_EN1 - This register is used to enable and disable EVTG0 OUT0B request.
43581  *  0b0..Disable
43582  *  0b1..Enable
43583  */
43584 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ32_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ32_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ32_EN1_MASK)
43585 
43586 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ33_EN1_MASK (0x2U)
43587 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ33_EN1_SHIFT (1U)
43588 /*! REQ33_EN1 - This register is used to enable and disable EVTG0 OUT1A request.
43589  *  0b0..Disable
43590  *  0b1..Enable
43591  */
43592 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ33_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ33_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ33_EN1_MASK)
43593 
43594 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ34_EN1_MASK (0x4U)
43595 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ34_EN1_SHIFT (2U)
43596 /*! REQ34_EN1 - This register is used to enable and disable EVTG0 OUT1B request.
43597  *  0b0..Disable
43598  *  0b1..Enable
43599  */
43600 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ34_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ34_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ34_EN1_MASK)
43601 
43602 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ35_EN1_MASK (0x8U)
43603 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ35_EN1_SHIFT (3U)
43604 /*! REQ35_EN1 - This register is used to enable and disable EVTG0 OUT2A request.
43605  *  0b0..Disable
43606  *  0b1..Enable
43607  */
43608 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ35_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ35_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ35_EN1_MASK)
43609 
43610 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ36_EN1_MASK (0x10U)
43611 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ36_EN1_SHIFT (4U)
43612 /*! REQ36_EN1 - This register is used to enable and disable EVTG0 OUT2B request.
43613  *  0b0..Disable
43614  *  0b1..Enable
43615  */
43616 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ36_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ36_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ36_EN1_MASK)
43617 
43618 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ37_EN1_MASK (0x20U)
43619 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ37_EN1_SHIFT (5U)
43620 /*! REQ37_EN1 - This register is used to enable and disable EVTG0 OUT3A request.
43621  *  0b0..Disable
43622  *  0b1..Enable
43623  */
43624 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ37_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ37_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ37_EN1_MASK)
43625 
43626 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ38_EN1_MASK (0x40U)
43627 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ38_EN1_SHIFT (6U)
43628 /*! REQ38_EN1 - This register is used to enable and disable EVTG0 OUT3B request.
43629  *  0b0..Disable
43630  *  0b1..Enable
43631  */
43632 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ38_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ38_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ38_EN1_MASK)
43633 
43634 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ39_EN1_MASK (0x80U)
43635 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ39_EN1_SHIFT (7U)
43636 /*! REQ39_EN1 - This register is used to enable and disable PWM0 Req_capt0 request.
43637  *  0b0..Disable
43638  *  0b1..Enable
43639  */
43640 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ39_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ39_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ39_EN1_MASK)
43641 
43642 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ40_EN1_MASK (0x100U)
43643 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ40_EN1_SHIFT (8U)
43644 /*! REQ40_EN1 - This register is used to enable and disable PWM0 Req_capt1 request.
43645  *  0b0..Disable
43646  *  0b1..Enable
43647  */
43648 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ40_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ40_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ40_EN1_MASK)
43649 
43650 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ41_EN1_MASK (0x200U)
43651 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ41_EN1_SHIFT (9U)
43652 /*! REQ41_EN1 - This register is used to enable and disable PWM0 Req_capt2 request.
43653  *  0b0..Disable
43654  *  0b1..Enable
43655  */
43656 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ41_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ41_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ41_EN1_MASK)
43657 
43658 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ42_EN1_MASK (0x400U)
43659 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ42_EN1_SHIFT (10U)
43660 /*! REQ42_EN1 - This register is used to enable and disable PWM0 Req_capt3 request.
43661  *  0b0..Disable
43662  *  0b1..Enable
43663  */
43664 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ42_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ42_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ42_EN1_MASK)
43665 
43666 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ43_EN1_MASK (0x800U)
43667 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ43_EN1_SHIFT (11U)
43668 /*! REQ43_EN1 - This register is used to enable and disable PWM0 Req_val0 request.
43669  *  0b0..Disable
43670  *  0b1..Enable
43671  */
43672 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ43_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ43_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ43_EN1_MASK)
43673 
43674 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ44_EN1_MASK (0x1000U)
43675 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ44_EN1_SHIFT (12U)
43676 /*! REQ44_EN1 - This register is used to enable and disable PWM0 Req_val1 request.
43677  *  0b0..Disable
43678  *  0b1..Enable
43679  */
43680 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ44_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ44_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ44_EN1_MASK)
43681 
43682 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ45_EN1_MASK (0x2000U)
43683 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ45_EN1_SHIFT (13U)
43684 /*! REQ45_EN1 - This register is used to enable and disable PWM0 Req_val2 request.
43685  *  0b0..Disable
43686  *  0b1..Enable
43687  */
43688 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ45_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ45_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ45_EN1_MASK)
43689 
43690 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ46_EN1_MASK (0x4000U)
43691 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ46_EN1_SHIFT (14U)
43692 /*! REQ46_EN1 - This register is used to enable and disable PWM0 Req_val3 request.
43693  *  0b0..Disable
43694  *  0b1..Enable
43695  */
43696 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ46_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ46_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ46_EN1_MASK)
43697 
43698 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ47_EN1_MASK (0x8000U)
43699 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ47_EN1_SHIFT (15U)
43700 /*! REQ47_EN1 - This register is used to enable and disable PWM1 Req_capt0 request.
43701  *  0b0..Disable
43702  *  0b1..Enable
43703  */
43704 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ47_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ47_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ47_EN1_MASK)
43705 
43706 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ48_EN1_MASK (0x10000U)
43707 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ48_EN1_SHIFT (16U)
43708 /*! REQ48_EN1 - This register is used to enable and disable PWM1 Req_capt1 request.
43709  *  0b0..Disable
43710  *  0b1..Enable
43711  */
43712 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ48_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ48_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ48_EN1_MASK)
43713 
43714 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ49_EN1_MASK (0x20000U)
43715 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ49_EN1_SHIFT (17U)
43716 /*! REQ49_EN1 - This register is used to enable and disable PWM1 Req_capt2 request.
43717  *  0b0..Disable
43718  *  0b1..Enable
43719  */
43720 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ49_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ49_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ49_EN1_MASK)
43721 
43722 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ50_EN1_MASK (0x40000U)
43723 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ50_EN1_SHIFT (18U)
43724 /*! REQ50_EN1 - This register is used to enable and disable PWM1 Req_capt3 request.
43725  *  0b0..Disable
43726  *  0b1..Enable
43727  */
43728 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ50_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ50_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ50_EN1_MASK)
43729 
43730 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ51_EN1_MASK (0x80000U)
43731 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ51_EN1_SHIFT (19U)
43732 /*! REQ51_EN1 - This register is used to enable and disable PWM1 Req_val0 request.
43733  *  0b0..Disable
43734  *  0b1..Enable
43735  */
43736 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ51_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ51_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ51_EN1_MASK)
43737 
43738 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ52_EN1_MASK (0x100000U)
43739 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ52_EN1_SHIFT (20U)
43740 /*! REQ52_EN1 - This register is used to enable and disable PWM1 Req_val1 request.
43741  *  0b0..Disable
43742  *  0b1..Enable
43743  */
43744 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ52_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ52_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ52_EN1_MASK)
43745 
43746 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ53_EN1_MASK (0x200000U)
43747 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ53_EN1_SHIFT (21U)
43748 /*! REQ53_EN1 - This register is used to enable and disable PWM1 Req_val2 request.
43749  *  0b0..Disable
43750  *  0b1..Enable
43751  */
43752 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ53_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ53_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ53_EN1_MASK)
43753 
43754 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ54_EN1_MASK (0x400000U)
43755 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ54_EN1_SHIFT (22U)
43756 /*! REQ54_EN1 - This register is used to enable and disable PWM1 Req_val3 request.
43757  *  0b0..Disable
43758  *  0b1..Enable
43759  */
43760 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ54_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ54_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ54_EN1_MASK)
43761 
43762 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ57_EN1_MASK (0x2000000U)
43763 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ57_EN1_SHIFT (25U)
43764 /*! REQ57_EN1 - This register is used to enable and disable LPTMR0 counter match event request.
43765  *  0b0..Disable
43766  *  0b1..Enable
43767  */
43768 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ57_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ57_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ57_EN1_MASK)
43769 
43770 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ58_EN1_MASK (0x4000000U)
43771 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ58_EN1_SHIFT (26U)
43772 /*! REQ58_EN1 - This register is used to enable and disable LPTMR1 counter match event request.
43773  *  0b0..Disable
43774  *  0b1..Enable
43775  */
43776 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ58_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ58_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ58_EN1_MASK)
43777 
43778 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ59_EN1_MASK (0x8000000U)
43779 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ59_EN1_SHIFT (27U)
43780 /*! REQ59_EN1 - This register is used to enable and disable CAN0 DMA request.
43781  *  0b0..Disable
43782  *  0b1..Enable
43783  */
43784 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ59_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ59_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ59_EN1_MASK)
43785 
43786 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ60_EN1_MASK (0x10000000U)
43787 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ60_EN1_SHIFT (28U)
43788 /*! REQ60_EN1 - This register is used to enable and disable CAN1 DMA request.
43789  *  0b0..Disable
43790  *  0b1..Enable
43791  */
43792 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ60_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ60_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ60_EN1_MASK)
43793 
43794 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ61_EN1_MASK (0x20000000U)
43795 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ61_EN1_SHIFT (29U)
43796 /*! REQ61_EN1 - This register is used to enable and disable FlexIO0 Shifter0 Status DMA request OR Timer0 Status DMA request.
43797  *  0b0..Disable
43798  *  0b1..Enable
43799  */
43800 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ61_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ61_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ61_EN1_MASK)
43801 
43802 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ62_EN1_MASK (0x40000000U)
43803 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ62_EN1_SHIFT (30U)
43804 /*! REQ62_EN1 - This register is used to enable and disable FlexIO0 Shifter1 Status DMA request OR Timer1 Status DMA request.
43805  *  0b0..Disable
43806  *  0b1..Enable
43807  */
43808 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ62_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ62_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ62_EN1_MASK)
43809 
43810 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ63_EN1_MASK (0x80000000U)
43811 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ63_EN1_SHIFT (31U)
43812 /*! REQ63_EN1 - This register is used to enable and disable FlexIO0 Shifter2 Status DMA request OR Timer2 Status DMA request.
43813  *  0b0..Disable
43814  *  0b1..Enable
43815  */
43816 #define INPUTMUX_DMA1_REQ_ENABLE1_REQ63_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ63_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ63_EN1_MASK)
43817 /*! @} */
43818 
43819 /*! @name DMA1_REQ_ENABLE1_SET - DMA1 Request Enable1 */
43820 /*! @{ */
43821 
43822 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ32_EN1_MASK (0x1U)
43823 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ32_EN1_SHIFT (0U)
43824 /*! REQ32_EN1 - Writing a 1 to REQ32_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */
43825 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ32_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ32_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ32_EN1_MASK)
43826 
43827 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ33_EN1_MASK (0x2U)
43828 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ33_EN1_SHIFT (1U)
43829 /*! REQ33_EN1 - Writing a 1 to REQ33_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */
43830 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ33_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ33_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ33_EN1_MASK)
43831 
43832 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ34_EN1_MASK (0x4U)
43833 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ34_EN1_SHIFT (2U)
43834 /*! REQ34_EN1 - Writing a 1 to REQ34_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */
43835 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ34_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ34_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ34_EN1_MASK)
43836 
43837 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ35_EN1_MASK (0x8U)
43838 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ35_EN1_SHIFT (3U)
43839 /*! REQ35_EN1 - Writing a 1 to REQ35_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */
43840 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ35_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ35_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ35_EN1_MASK)
43841 
43842 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ36_EN1_MASK (0x10U)
43843 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ36_EN1_SHIFT (4U)
43844 /*! REQ36_EN1 - Writing a 1 to REQ36_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */
43845 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ36_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ36_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ36_EN1_MASK)
43846 
43847 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ37_EN1_MASK (0x20U)
43848 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ37_EN1_SHIFT (5U)
43849 /*! REQ37_EN1 - Writing a 1 to REQ37_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */
43850 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ37_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ37_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ37_EN1_MASK)
43851 
43852 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ38_EN1_MASK (0x40U)
43853 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ38_EN1_SHIFT (6U)
43854 /*! REQ38_EN1 - Writing a 1 to REQ38_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */
43855 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ38_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ38_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ38_EN1_MASK)
43856 
43857 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ39_EN1_MASK (0x80U)
43858 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ39_EN1_SHIFT (7U)
43859 /*! REQ39_EN1 - Writing a 1 to REQ39_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */
43860 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ39_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ39_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ39_EN1_MASK)
43861 
43862 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ40_EN1_MASK (0x100U)
43863 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ40_EN1_SHIFT (8U)
43864 /*! REQ40_EN1 - Writing a 1 to REQ40_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */
43865 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ40_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ40_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ40_EN1_MASK)
43866 
43867 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ41_EN1_MASK (0x200U)
43868 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ41_EN1_SHIFT (9U)
43869 /*! REQ41_EN1 - Writing a 1 to REQ41_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */
43870 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ41_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ41_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ41_EN1_MASK)
43871 
43872 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ42_EN1_MASK (0x400U)
43873 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ42_EN1_SHIFT (10U)
43874 /*! REQ42_EN1 - Writing a 1 to REQ42_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */
43875 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ42_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ42_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ42_EN1_MASK)
43876 
43877 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ43_EN1_MASK (0x800U)
43878 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ43_EN1_SHIFT (11U)
43879 /*! REQ43_EN1 - Writing a 1 to REQ43_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */
43880 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ43_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ43_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ43_EN1_MASK)
43881 
43882 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ44_EN1_MASK (0x1000U)
43883 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ44_EN1_SHIFT (12U)
43884 /*! REQ44_EN1 - Writing a 1 to REQ44_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */
43885 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ44_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ44_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ44_EN1_MASK)
43886 
43887 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ45_EN1_MASK (0x2000U)
43888 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ45_EN1_SHIFT (13U)
43889 /*! REQ45_EN1 - Writing a 1 to REQ45_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */
43890 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ45_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ45_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ45_EN1_MASK)
43891 
43892 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ46_EN1_MASK (0x4000U)
43893 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ46_EN1_SHIFT (14U)
43894 /*! REQ46_EN1 - Writing a 1 to REQ46_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */
43895 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ46_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ46_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ46_EN1_MASK)
43896 
43897 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ47_EN1_MASK (0x8000U)
43898 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ47_EN1_SHIFT (15U)
43899 /*! REQ47_EN1 - Writing a 1 to REQ47_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */
43900 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ47_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ47_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ47_EN1_MASK)
43901 
43902 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ48_EN1_MASK (0x10000U)
43903 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ48_EN1_SHIFT (16U)
43904 /*! REQ48_EN1 - Writing a 1 to REQ48_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */
43905 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ48_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ48_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ48_EN1_MASK)
43906 
43907 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ49_EN1_MASK (0x20000U)
43908 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ49_EN1_SHIFT (17U)
43909 /*! REQ49_EN1 - Writing a 1 to REQ49_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */
43910 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ49_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ49_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ49_EN1_MASK)
43911 
43912 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ50_EN1_MASK (0x40000U)
43913 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ50_EN1_SHIFT (18U)
43914 /*! REQ50_EN1 - Writing a 1 to REQ50_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */
43915 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ50_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ50_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ50_EN1_MASK)
43916 
43917 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ51_EN1_MASK (0x80000U)
43918 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ51_EN1_SHIFT (19U)
43919 /*! REQ51_EN1 - Writing a 1 to REQ51_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */
43920 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ51_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ51_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ51_EN1_MASK)
43921 
43922 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ52_EN1_MASK (0x100000U)
43923 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ52_EN1_SHIFT (20U)
43924 /*! REQ52_EN1 - Writing a 1 to REQ52_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */
43925 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ52_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ52_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ52_EN1_MASK)
43926 
43927 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ53_EN1_MASK (0x200000U)
43928 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ53_EN1_SHIFT (21U)
43929 /*! REQ53_EN1 - Writing a 1 to REQ53_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */
43930 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ53_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ53_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ53_EN1_MASK)
43931 
43932 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ54_EN1_MASK (0x400000U)
43933 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ54_EN1_SHIFT (22U)
43934 /*! REQ54_EN1 - Writing a 1 to REQ54_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */
43935 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ54_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ54_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ54_EN1_MASK)
43936 
43937 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ57_EN1_MASK (0x2000000U)
43938 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ57_EN1_SHIFT (25U)
43939 /*! REQ57_EN1 - Writing a 1 to REQ57_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */
43940 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ57_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ57_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ57_EN1_MASK)
43941 
43942 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ58_EN1_MASK (0x4000000U)
43943 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ58_EN1_SHIFT (26U)
43944 /*! REQ58_EN1 - Writing a 1 to REQ58_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */
43945 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ58_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ58_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ58_EN1_MASK)
43946 
43947 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ59_EN1_MASK (0x8000000U)
43948 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ59_EN1_SHIFT (27U)
43949 /*! REQ59_EN1 - Writing a 1 to REQ59_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */
43950 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ59_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ59_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ59_EN1_MASK)
43951 
43952 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ60_EN1_MASK (0x10000000U)
43953 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ60_EN1_SHIFT (28U)
43954 /*! REQ60_EN1 - Writing a 1 to REQ60_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */
43955 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ60_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ60_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ60_EN1_MASK)
43956 
43957 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ61_EN1_MASK (0x20000000U)
43958 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ61_EN1_SHIFT (29U)
43959 /*! REQ61_EN1 - Writing a 1 to REQ61_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */
43960 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ61_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ61_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ61_EN1_MASK)
43961 
43962 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ62_EN1_MASK (0x40000000U)
43963 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ62_EN1_SHIFT (30U)
43964 /*! REQ62_EN1 - Writing a 1 to REQ62_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */
43965 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ62_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ62_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ62_EN1_MASK)
43966 
43967 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ63_EN1_MASK (0x80000000U)
43968 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ63_EN1_SHIFT (31U)
43969 /*! REQ63_EN1 - Writing a 1 to REQ63_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */
43970 #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ63_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ63_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ63_EN1_MASK)
43971 /*! @} */
43972 
43973 /*! @name DMA1_REQ_ENABLE1_CLR - DMA1 Request Enable1 */
43974 /*! @{ */
43975 
43976 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ32_EN1_MASK (0x1U)
43977 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ32_EN1_SHIFT (0U)
43978 /*! REQ32_EN1 - Writing a 1 to REQ32_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */
43979 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ32_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ32_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ32_EN1_MASK)
43980 
43981 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ33_EN1_MASK (0x2U)
43982 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ33_EN1_SHIFT (1U)
43983 /*! REQ33_EN1 - Writing a 1 to REQ33_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */
43984 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ33_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ33_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ33_EN1_MASK)
43985 
43986 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ34_EN1_MASK (0x4U)
43987 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ34_EN1_SHIFT (2U)
43988 /*! REQ34_EN1 - Writing a 1 to REQ34_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */
43989 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ34_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ34_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ34_EN1_MASK)
43990 
43991 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ35_EN1_MASK (0x8U)
43992 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ35_EN1_SHIFT (3U)
43993 /*! REQ35_EN1 - Writing a 1 to REQ35_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */
43994 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ35_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ35_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ35_EN1_MASK)
43995 
43996 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ36_EN1_MASK (0x10U)
43997 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ36_EN1_SHIFT (4U)
43998 /*! REQ36_EN1 - Writing a 1 to REQ36_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */
43999 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ36_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ36_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ36_EN1_MASK)
44000 
44001 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ37_EN1_MASK (0x20U)
44002 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ37_EN1_SHIFT (5U)
44003 /*! REQ37_EN1 - Writing a 1 to REQ37_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */
44004 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ37_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ37_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ37_EN1_MASK)
44005 
44006 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ38_EN1_MASK (0x40U)
44007 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ38_EN1_SHIFT (6U)
44008 /*! REQ38_EN1 - Writing a 1 to REQ38_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */
44009 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ38_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ38_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ38_EN1_MASK)
44010 
44011 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ39_EN1_MASK (0x80U)
44012 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ39_EN1_SHIFT (7U)
44013 /*! REQ39_EN1 - Writing a 1 to REQ39_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */
44014 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ39_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ39_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ39_EN1_MASK)
44015 
44016 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ40_EN1_MASK (0x100U)
44017 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ40_EN1_SHIFT (8U)
44018 /*! REQ40_EN1 - Writing a 1 to REQ40_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */
44019 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ40_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ40_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ40_EN1_MASK)
44020 
44021 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ41_EN1_MASK (0x200U)
44022 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ41_EN1_SHIFT (9U)
44023 /*! REQ41_EN1 - Writing a 1 to REQ41_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */
44024 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ41_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ41_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ41_EN1_MASK)
44025 
44026 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ42_EN1_MASK (0x400U)
44027 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ42_EN1_SHIFT (10U)
44028 /*! REQ42_EN1 - Writing a 1 to REQ42_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */
44029 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ42_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ42_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ42_EN1_MASK)
44030 
44031 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ43_EN1_MASK (0x800U)
44032 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ43_EN1_SHIFT (11U)
44033 /*! REQ43_EN1 - Writing a 1 to REQ43_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */
44034 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ43_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ43_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ43_EN1_MASK)
44035 
44036 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ44_EN1_MASK (0x1000U)
44037 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ44_EN1_SHIFT (12U)
44038 /*! REQ44_EN1 - Writing a 1 to REQ44_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */
44039 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ44_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ44_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ44_EN1_MASK)
44040 
44041 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ45_EN1_MASK (0x2000U)
44042 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ45_EN1_SHIFT (13U)
44043 /*! REQ45_EN1 - Writing a 1 to REQ45_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */
44044 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ45_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ45_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ45_EN1_MASK)
44045 
44046 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ46_EN1_MASK (0x4000U)
44047 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ46_EN1_SHIFT (14U)
44048 /*! REQ46_EN1 - Writing a 1 to REQ46_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */
44049 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ46_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ46_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ46_EN1_MASK)
44050 
44051 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ47_EN1_MASK (0x8000U)
44052 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ47_EN1_SHIFT (15U)
44053 /*! REQ47_EN1 - Writing a 1 to REQ47_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */
44054 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ47_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ47_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ47_EN1_MASK)
44055 
44056 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ48_EN1_MASK (0x10000U)
44057 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ48_EN1_SHIFT (16U)
44058 /*! REQ48_EN1 - Writing a 1 to REQ48_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */
44059 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ48_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ48_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ48_EN1_MASK)
44060 
44061 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ49_EN1_MASK (0x20000U)
44062 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ49_EN1_SHIFT (17U)
44063 /*! REQ49_EN1 - Writing a 1 to REQ49_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */
44064 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ49_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ49_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ49_EN1_MASK)
44065 
44066 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ50_EN1_MASK (0x40000U)
44067 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ50_EN1_SHIFT (18U)
44068 /*! REQ50_EN1 - Writing a 1 to REQ50_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */
44069 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ50_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ50_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ50_EN1_MASK)
44070 
44071 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ51_EN1_MASK (0x80000U)
44072 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ51_EN1_SHIFT (19U)
44073 /*! REQ51_EN1 - Writing a 1 to REQ51_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */
44074 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ51_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ51_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ51_EN1_MASK)
44075 
44076 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ52_EN1_MASK (0x100000U)
44077 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ52_EN1_SHIFT (20U)
44078 /*! REQ52_EN1 - Writing a 1 to REQ52_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */
44079 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ52_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ52_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ52_EN1_MASK)
44080 
44081 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ53_EN1_MASK (0x200000U)
44082 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ53_EN1_SHIFT (21U)
44083 /*! REQ53_EN1 - Writing a 1 to REQ53_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */
44084 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ53_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ53_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ53_EN1_MASK)
44085 
44086 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ54_EN1_MASK (0x400000U)
44087 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ54_EN1_SHIFT (22U)
44088 /*! REQ54_EN1 - Writing a 1 to REQ54_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */
44089 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ54_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ54_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ54_EN1_MASK)
44090 
44091 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ57_EN1_MASK (0x2000000U)
44092 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ57_EN1_SHIFT (25U)
44093 /*! REQ57_EN1 - Writing a 1 to REQ57_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */
44094 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ57_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ57_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ57_EN1_MASK)
44095 
44096 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ58_EN1_MASK (0x4000000U)
44097 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ58_EN1_SHIFT (26U)
44098 /*! REQ58_EN1 - Writing a 1 to REQ58_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */
44099 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ58_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ58_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ58_EN1_MASK)
44100 
44101 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ59_EN1_MASK (0x8000000U)
44102 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ59_EN1_SHIFT (27U)
44103 /*! REQ59_EN1 - Writing a 1 to REQ59_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */
44104 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ59_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ59_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ59_EN1_MASK)
44105 
44106 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ60_EN1_MASK (0x10000000U)
44107 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ60_EN1_SHIFT (28U)
44108 /*! REQ60_EN1 - Writing a 1 to REQ60_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */
44109 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ60_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ60_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ60_EN1_MASK)
44110 
44111 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ61_EN1_MASK (0x20000000U)
44112 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ61_EN1_SHIFT (29U)
44113 /*! REQ61_EN1 - Writing a 1 to REQ61_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */
44114 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ61_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ61_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ61_EN1_MASK)
44115 
44116 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ62_EN1_MASK (0x40000000U)
44117 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ62_EN1_SHIFT (30U)
44118 /*! REQ62_EN1 - Writing a 1 to REQ62_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */
44119 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ62_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ62_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ62_EN1_MASK)
44120 
44121 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ63_EN1_MASK (0x80000000U)
44122 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ63_EN1_SHIFT (31U)
44123 /*! REQ63_EN1 - Writing a 1 to REQ63_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */
44124 #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ63_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ63_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ63_EN1_MASK)
44125 /*! @} */
44126 
44127 /*! @name DMA1_REQ_ENABLE1_TOG - DMA1 Request Enable1 */
44128 /*! @{ */
44129 
44130 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ32_EN1_MASK (0x1U)
44131 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ32_EN1_SHIFT (0U)
44132 /*! REQ32_EN1 - Writing a 1 to REQ32_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */
44133 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ32_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ32_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ32_EN1_MASK)
44134 
44135 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ33_EN1_MASK (0x2U)
44136 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ33_EN1_SHIFT (1U)
44137 /*! REQ33_EN1 - Writing a 1 to REQ33_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */
44138 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ33_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ33_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ33_EN1_MASK)
44139 
44140 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ34_EN1_MASK (0x4U)
44141 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ34_EN1_SHIFT (2U)
44142 /*! REQ34_EN1 - Writing a 1 to REQ34_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */
44143 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ34_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ34_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ34_EN1_MASK)
44144 
44145 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ35_EN1_MASK (0x8U)
44146 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ35_EN1_SHIFT (3U)
44147 /*! REQ35_EN1 - Writing a 1 to REQ35_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */
44148 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ35_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ35_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ35_EN1_MASK)
44149 
44150 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ36_EN1_MASK (0x10U)
44151 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ36_EN1_SHIFT (4U)
44152 /*! REQ36_EN1 - Writing a 1 to REQ36_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */
44153 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ36_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ36_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ36_EN1_MASK)
44154 
44155 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ37_EN1_MASK (0x20U)
44156 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ37_EN1_SHIFT (5U)
44157 /*! REQ37_EN1 - Writing a 1 to REQ37_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */
44158 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ37_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ37_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ37_EN1_MASK)
44159 
44160 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ38_EN1_MASK (0x40U)
44161 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ38_EN1_SHIFT (6U)
44162 /*! REQ38_EN1 - Writing a 1 to REQ38_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */
44163 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ38_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ38_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ38_EN1_MASK)
44164 
44165 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ39_EN1_MASK (0x80U)
44166 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ39_EN1_SHIFT (7U)
44167 /*! REQ39_EN1 - Writing a 1 to REQ39_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */
44168 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ39_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ39_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ39_EN1_MASK)
44169 
44170 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ40_EN1_MASK (0x100U)
44171 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ40_EN1_SHIFT (8U)
44172 /*! REQ40_EN1 - Writing a 1 to REQ40_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */
44173 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ40_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ40_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ40_EN1_MASK)
44174 
44175 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ41_EN1_MASK (0x200U)
44176 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ41_EN1_SHIFT (9U)
44177 /*! REQ41_EN1 - Writing a 1 to REQ41_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */
44178 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ41_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ41_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ41_EN1_MASK)
44179 
44180 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ42_EN1_MASK (0x400U)
44181 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ42_EN1_SHIFT (10U)
44182 /*! REQ42_EN1 - Writing a 1 to REQ42_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */
44183 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ42_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ42_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ42_EN1_MASK)
44184 
44185 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ43_EN1_MASK (0x800U)
44186 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ43_EN1_SHIFT (11U)
44187 /*! REQ43_EN1 - Writing a 1 to REQ43_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */
44188 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ43_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ43_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ43_EN1_MASK)
44189 
44190 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ44_EN1_MASK (0x1000U)
44191 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ44_EN1_SHIFT (12U)
44192 /*! REQ44_EN1 - Writing a 1 to REQ44_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */
44193 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ44_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ44_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ44_EN1_MASK)
44194 
44195 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ45_EN1_MASK (0x2000U)
44196 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ45_EN1_SHIFT (13U)
44197 /*! REQ45_EN1 - Writing a 1 to REQ55_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */
44198 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ45_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ45_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ45_EN1_MASK)
44199 
44200 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ46_EN1_MASK (0x4000U)
44201 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ46_EN1_SHIFT (14U)
44202 /*! REQ46_EN1 - Writing a 1 to REQ46_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */
44203 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ46_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ46_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ46_EN1_MASK)
44204 
44205 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ47_EN1_MASK (0x8000U)
44206 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ47_EN1_SHIFT (15U)
44207 /*! REQ47_EN1 - Writing a 1 to REQ47_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */
44208 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ47_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ47_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ47_EN1_MASK)
44209 
44210 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ48_EN1_MASK (0x10000U)
44211 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ48_EN1_SHIFT (16U)
44212 /*! REQ48_EN1 - Writing a 1 to REQ48_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */
44213 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ48_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ48_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ48_EN1_MASK)
44214 
44215 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ49_EN1_MASK (0x20000U)
44216 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ49_EN1_SHIFT (17U)
44217 /*! REQ49_EN1 - Writing a 1 to REQ49_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */
44218 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ49_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ49_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ49_EN1_MASK)
44219 
44220 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ50_EN1_MASK (0x40000U)
44221 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ50_EN1_SHIFT (18U)
44222 /*! REQ50_EN1 - Writing a 1 to REQ50_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */
44223 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ50_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ50_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ50_EN1_MASK)
44224 
44225 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ51_EN1_MASK (0x80000U)
44226 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ51_EN1_SHIFT (19U)
44227 /*! REQ51_EN1 - Writing a 1 to REQ51_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */
44228 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ51_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ51_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ51_EN1_MASK)
44229 
44230 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ52_EN1_MASK (0x100000U)
44231 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ52_EN1_SHIFT (20U)
44232 /*! REQ52_EN1 - Writing a 1 to REQ52_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */
44233 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ52_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ52_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ52_EN1_MASK)
44234 
44235 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ53_EN1_MASK (0x200000U)
44236 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ53_EN1_SHIFT (21U)
44237 /*! REQ53_EN1 - Writing a 1 to REQ53_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */
44238 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ53_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ53_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ53_EN1_MASK)
44239 
44240 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ54_EN1_MASK (0x400000U)
44241 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ54_EN1_SHIFT (22U)
44242 /*! REQ54_EN1 - Writing a 1 to REQ54_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */
44243 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ54_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ54_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ54_EN1_MASK)
44244 
44245 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ57_EN1_MASK (0x2000000U)
44246 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ57_EN1_SHIFT (25U)
44247 /*! REQ57_EN1 - Writing a 1 to REQ57_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */
44248 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ57_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ57_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ57_EN1_MASK)
44249 
44250 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ58_EN1_MASK (0x4000000U)
44251 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ58_EN1_SHIFT (26U)
44252 /*! REQ58_EN1 - Writing a 1 to REQ58_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */
44253 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ58_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ58_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ58_EN1_MASK)
44254 
44255 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ59_EN1_MASK (0x8000000U)
44256 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ59_EN1_SHIFT (27U)
44257 /*! REQ59_EN1 - Writing a 1 to REQ59_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */
44258 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ59_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ59_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ59_EN1_MASK)
44259 
44260 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ60_EN1_MASK (0x10000000U)
44261 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ60_EN1_SHIFT (28U)
44262 /*! REQ60_EN1 - Writing a 1 to REQ60_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */
44263 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ60_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ60_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ60_EN1_MASK)
44264 
44265 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ61_EN1_MASK (0x20000000U)
44266 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ61_EN1_SHIFT (29U)
44267 /*! REQ61_EN1 - Writing a 1 to REQ61_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */
44268 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ61_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ61_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ61_EN1_MASK)
44269 
44270 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ62_EN1_MASK (0x40000000U)
44271 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ62_EN1_SHIFT (30U)
44272 /*! REQ62_EN1 - Writing a 1 to REQ62_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */
44273 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ62_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ62_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ62_EN1_MASK)
44274 
44275 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ63_EN1_MASK (0x80000000U)
44276 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ63_EN1_SHIFT (31U)
44277 /*! REQ63_EN1 - Writing a 1 to REQ63_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */
44278 #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ63_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ63_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ63_EN1_MASK)
44279 /*! @} */
44280 
44281 /*! @name DMA1_REQ_ENABLE2 - DMA1 Request Enable2 */
44282 /*! @{ */
44283 
44284 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ64_EN1_MASK (0x1U)
44285 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ64_EN1_SHIFT (0U)
44286 /*! REQ64_EN1 - This register is used to enable and disable FlexIO0 Shifter3 Status DMA request OR Timer3 Status DMA request.
44287  *  0b0..Disable
44288  *  0b1..Enable
44289  */
44290 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ64_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ64_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ64_EN1_MASK)
44291 
44292 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ65_EN1_MASK (0x2U)
44293 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ65_EN1_SHIFT (1U)
44294 /*! REQ65_EN1 - This register is used to enable and disable FlexIO0 Shifter4 Status DMA request OR Timer4 Status DMA request.
44295  *  0b0..Disable
44296  *  0b1..Enable
44297  */
44298 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ65_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ65_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ65_EN1_MASK)
44299 
44300 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ66_EN1_MASK (0x4U)
44301 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ66_EN1_SHIFT (2U)
44302 /*! REQ66_EN1 - This register is used to enable and disable FlexIO0 Shifter5 Status DMA request OR Timer5 Status DMA request.
44303  *  0b0..Disable
44304  *  0b1..Enable
44305  */
44306 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ66_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ66_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ66_EN1_MASK)
44307 
44308 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ67_EN1_MASK (0x8U)
44309 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ67_EN1_SHIFT (3U)
44310 /*! REQ67_EN1 - This register is used to enable and disable FlexIO0 Shifter6 Status DMA request OR Timer6 Status DMA request.
44311  *  0b0..Disable
44312  *  0b1..Enable
44313  */
44314 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ67_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ67_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ67_EN1_MASK)
44315 
44316 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ68_EN1_MASK (0x10U)
44317 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ68_EN1_SHIFT (4U)
44318 /*! REQ68_EN1 - This register is used to enable and disable FlexIO0 Shifter7 Status DMA request OR Timer7 Status DMA request.
44319  *  0b0..Disable
44320  *  0b1..Enable
44321  */
44322 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ68_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ68_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ68_EN1_MASK)
44323 
44324 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ69_EN1_MASK (0x20U)
44325 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ69_EN1_SHIFT (5U)
44326 /*! REQ69_EN1 - This register is used to enable and disable LP_FLEXCOMM0 receive request.
44327  *  0b0..Disable
44328  *  0b1..Enable
44329  */
44330 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ69_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ69_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ69_EN1_MASK)
44331 
44332 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ70_EN1_MASK (0x40U)
44333 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ70_EN1_SHIFT (6U)
44334 /*! REQ70_EN1 - This register is used to enable and disable LP_FLEXCOMM0 transmit request.
44335  *  0b0..Disable
44336  *  0b1..Enable
44337  */
44338 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ70_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ70_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ70_EN1_MASK)
44339 
44340 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ71_EN1_MASK (0x80U)
44341 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ71_EN1_SHIFT (7U)
44342 /*! REQ71_EN1 - This register is used to enable and disable LP_FLEXCOMM1 receive request.
44343  *  0b0..Disable
44344  *  0b1..Enable
44345  */
44346 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ71_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ71_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ71_EN1_MASK)
44347 
44348 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ72_EN1_MASK (0x100U)
44349 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ72_EN1_SHIFT (8U)
44350 /*! REQ72_EN1 - This register is used to enable and disable LP_FLEXCOMM1 transmit request.
44351  *  0b0..Disable
44352  *  0b1..Enable
44353  */
44354 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ72_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ72_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ72_EN1_MASK)
44355 
44356 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ73_EN1_MASK (0x200U)
44357 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ73_EN1_SHIFT (9U)
44358 /*! REQ73_EN1 - This register is used to enable and disable LP_FLEXCOMM2 receive request.
44359  *  0b0..Disable
44360  *  0b1..Enable
44361  */
44362 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ73_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ73_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ73_EN1_MASK)
44363 
44364 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ74_EN1_MASK (0x400U)
44365 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ74_EN1_SHIFT (10U)
44366 /*! REQ74_EN1 - This register is used to enable and disable LP_FLEXCOMM2 transmit request.
44367  *  0b0..Disable
44368  *  0b1..Enable
44369  */
44370 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ74_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ74_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ74_EN1_MASK)
44371 
44372 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ75_EN1_MASK (0x800U)
44373 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ75_EN1_SHIFT (11U)
44374 /*! REQ75_EN1 - This register is used to enable and disable LP_FLEXCOMM3 receive request.
44375  *  0b0..Disable
44376  *  0b1..Enable
44377  */
44378 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ75_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ75_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ75_EN1_MASK)
44379 
44380 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ76_EN1_MASK (0x1000U)
44381 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ76_EN1_SHIFT (12U)
44382 /*! REQ76_EN1 - This register is used to enable and disable LP_FLEXCOMM3 transmit request.
44383  *  0b0..Disable
44384  *  0b1..Enable
44385  */
44386 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ76_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ76_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ76_EN1_MASK)
44387 
44388 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ77_EN1_MASK (0x2000U)
44389 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ77_EN1_SHIFT (13U)
44390 /*! REQ77_EN1 - This register is used to enable and disable LP_FLEXCOMM4 receive request.
44391  *  0b0..Disable
44392  *  0b1..Enable
44393  */
44394 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ77_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ77_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ77_EN1_MASK)
44395 
44396 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ78_EN1_MASK (0x4000U)
44397 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ78_EN1_SHIFT (14U)
44398 /*! REQ78_EN1 - This register is used to enable and disable LP_FLEXCOMM4 transmit request.
44399  *  0b0..Disable
44400  *  0b1..Enable
44401  */
44402 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ78_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ78_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ78_EN1_MASK)
44403 
44404 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ79_EN1_MASK (0x8000U)
44405 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ79_EN1_SHIFT (15U)
44406 /*! REQ79_EN1 - This register is used to enable and disable LP_FLEXCOMM5 receive request.
44407  *  0b0..Disable
44408  *  0b1..Enable
44409  */
44410 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ79_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ79_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ79_EN1_MASK)
44411 
44412 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ80_EN1_MASK (0x10000U)
44413 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ80_EN1_SHIFT (16U)
44414 /*! REQ80_EN1 - This register is used to enable and disable LP_FLEXCOMM5 transmit request.
44415  *  0b0..Disable
44416  *  0b1..Enable
44417  */
44418 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ80_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ80_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ80_EN1_MASK)
44419 
44420 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ81_EN1_MASK (0x20000U)
44421 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ81_EN1_SHIFT (17U)
44422 /*! REQ81_EN1 - This register is used to enable and disable LP_FLEXCOMM6 receive request.
44423  *  0b0..Disable
44424  *  0b1..Enable
44425  */
44426 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ81_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ81_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ81_EN1_MASK)
44427 
44428 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ82_EN1_MASK (0x40000U)
44429 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ82_EN1_SHIFT (18U)
44430 /*! REQ82_EN1 - This register is used to enable and disable LP_FLEXCOMM6 transmit request.
44431  *  0b0..Disable
44432  *  0b1..Enable
44433  */
44434 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ82_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ82_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ82_EN1_MASK)
44435 
44436 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ83_EN1_MASK (0x80000U)
44437 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ83_EN1_SHIFT (19U)
44438 /*! REQ83_EN1 - This register is used to enable and disable LP_FLEXCOMM7 receive request.
44439  *  0b0..Disable
44440  *  0b1..Enable
44441  */
44442 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ83_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ83_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ83_EN1_MASK)
44443 
44444 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ84_EN1_MASK (0x100000U)
44445 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ84_EN1_SHIFT (20U)
44446 /*! REQ84_EN1 - This register is used to enable and disable LP_FLEXCOMM7 transmit request.
44447  *  0b0..Disable
44448  *  0b1..Enable
44449  */
44450 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ84_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ84_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ84_EN1_MASK)
44451 
44452 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ85_EN1_MASK (0x200000U)
44453 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ85_EN1_SHIFT (21U)
44454 /*! REQ85_EN1 - This register is used to enable and disable LP_FLEXCOMM8 receive request.
44455  *  0b0..Disable
44456  *  0b1..Enable
44457  */
44458 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ85_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ85_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ85_EN1_MASK)
44459 
44460 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ86_EN1_MASK (0x400000U)
44461 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ86_EN1_SHIFT (22U)
44462 /*! REQ86_EN1 - This register is used to enable and disable LP_FLEXCOMM8 transmit request.
44463  *  0b0..Disable
44464  *  0b1..Enable
44465  */
44466 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ86_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ86_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ86_EN1_MASK)
44467 
44468 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ87_EN1_MASK (0x800000U)
44469 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ87_EN1_SHIFT (23U)
44470 /*! REQ87_EN1 - This register is used to enable and disable LP_FLEXCOMM9 receive request.
44471  *  0b0..Disable
44472  *  0b1..Enable
44473  */
44474 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ87_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ87_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ87_EN1_MASK)
44475 
44476 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ88_EN1_MASK (0x1000000U)
44477 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ88_EN1_SHIFT (24U)
44478 /*! REQ88_EN1 - This register is used to enable and disable LP_FLEXCOMM9 transmit request.
44479  *  0b0..Disable
44480  *  0b1..Enable
44481  */
44482 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ88_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ88_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ88_EN1_MASK)
44483 
44484 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ91_EN1_MASK (0x8000000U)
44485 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ91_EN1_SHIFT (27U)
44486 /*! REQ91_EN1 - This register is used to enable and disable EMVSIM0 receive request.
44487  *  0b0..Disable
44488  *  0b1..Enable
44489  */
44490 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ91_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ91_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ91_EN1_MASK)
44491 
44492 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ92_EN1_MASK (0x10000000U)
44493 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ92_EN1_SHIFT (28U)
44494 /*! REQ92_EN1 - This register is used to enable and disable EMVSIM0 transmit request.
44495  *  0b0..Disable
44496  *  0b1..Enable
44497  */
44498 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ92_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ92_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ92_EN1_MASK)
44499 
44500 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ93_EN1_MASK (0x20000000U)
44501 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ93_EN1_SHIFT (29U)
44502 /*! REQ93_EN1 - This register is used to enable and disable EMVSIM1 receive request.
44503  *  0b0..Disable
44504  *  0b1..Enable
44505  */
44506 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ93_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ93_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ93_EN1_MASK)
44507 
44508 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ94_EN1_MASK (0x40000000U)
44509 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ94_EN1_SHIFT (30U)
44510 /*! REQ94_EN1 - This register is used to enable and disable EMVSIM1 transmit request.
44511  *  0b0..Disable
44512  *  0b1..Enable
44513  */
44514 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ94_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ94_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ94_EN1_MASK)
44515 
44516 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ95_EN1_MASK (0x80000000U)
44517 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ95_EN1_SHIFT (31U)
44518 /*! REQ95_EN1 - This register is used to enable and disable I3C0 receive request.
44519  *  0b0..Disable
44520  *  0b1..Enable
44521  */
44522 #define INPUTMUX_DMA1_REQ_ENABLE2_REQ95_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ95_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ95_EN1_MASK)
44523 /*! @} */
44524 
44525 /*! @name DMA1_REQ_ENABLE2_SET - DMA1 Request Enable2 */
44526 /*! @{ */
44527 
44528 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ64_EN1_MASK (0x1U)
44529 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ64_EN1_SHIFT (0U)
44530 /*! REQ64_EN1 - Writing a 1 to REQ64_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */
44531 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ64_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ64_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ64_EN1_MASK)
44532 
44533 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ65_EN1_MASK (0x2U)
44534 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ65_EN1_SHIFT (1U)
44535 /*! REQ65_EN1 - Writing a 1 to REQ65_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */
44536 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ65_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ65_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ65_EN1_MASK)
44537 
44538 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ66_EN1_MASK (0x4U)
44539 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ66_EN1_SHIFT (2U)
44540 /*! REQ66_EN1 - Writing a 1 to REQ66_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */
44541 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ66_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ66_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ66_EN1_MASK)
44542 
44543 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ67_EN1_MASK (0x8U)
44544 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ67_EN1_SHIFT (3U)
44545 /*! REQ67_EN1 - Writing a 1 to REQ67_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */
44546 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ67_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ67_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ67_EN1_MASK)
44547 
44548 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ68_EN1_MASK (0x10U)
44549 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ68_EN1_SHIFT (4U)
44550 /*! REQ68_EN1 - Writing a 1 to REQ68_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */
44551 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ68_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ68_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ68_EN1_MASK)
44552 
44553 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ69_EN1_MASK (0x20U)
44554 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ69_EN1_SHIFT (5U)
44555 /*! REQ69_EN1 - Writing a 1 to REQ69_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */
44556 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ69_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ69_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ69_EN1_MASK)
44557 
44558 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ70_EN1_MASK (0x40U)
44559 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ70_EN1_SHIFT (6U)
44560 /*! REQ70_EN1 - Writing a 1 to REQ70_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */
44561 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ70_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ70_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ70_EN1_MASK)
44562 
44563 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ71_EN1_MASK (0x80U)
44564 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ71_EN1_SHIFT (7U)
44565 /*! REQ71_EN1 - Writing a 1 to REQ71_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */
44566 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ71_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ71_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ71_EN1_MASK)
44567 
44568 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ72_EN1_MASK (0x100U)
44569 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ72_EN1_SHIFT (8U)
44570 /*! REQ72_EN1 - Writing a 1 to REQ72_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */
44571 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ72_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ72_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ72_EN1_MASK)
44572 
44573 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ73_EN1_MASK (0x200U)
44574 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ73_EN1_SHIFT (9U)
44575 /*! REQ73_EN1 - Writing a 1 to REQ73_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */
44576 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ73_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ73_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ73_EN1_MASK)
44577 
44578 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ74_EN1_MASK (0x400U)
44579 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ74_EN1_SHIFT (10U)
44580 /*! REQ74_EN1 - Writing a 1 to REQ74_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */
44581 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ74_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ74_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ74_EN1_MASK)
44582 
44583 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ75_EN1_MASK (0x800U)
44584 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ75_EN1_SHIFT (11U)
44585 /*! REQ75_EN1 - Writing a 1 to REQ75_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */
44586 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ75_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ75_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ75_EN1_MASK)
44587 
44588 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ76_EN1_MASK (0x1000U)
44589 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ76_EN1_SHIFT (12U)
44590 /*! REQ76_EN1 - Writing a 1 to REQ876_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */
44591 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ76_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ76_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ76_EN1_MASK)
44592 
44593 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ77_EN1_MASK (0x2000U)
44594 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ77_EN1_SHIFT (13U)
44595 /*! REQ77_EN1 - Writing a 1 to REQ77_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */
44596 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ77_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ77_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ77_EN1_MASK)
44597 
44598 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ78_EN1_MASK (0x4000U)
44599 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ78_EN1_SHIFT (14U)
44600 /*! REQ78_EN1 - Writing a 1 to REQ78_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */
44601 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ78_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ78_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ78_EN1_MASK)
44602 
44603 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ79_EN1_MASK (0x8000U)
44604 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ79_EN1_SHIFT (15U)
44605 /*! REQ79_EN1 - Writing a 1 to REQ79_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */
44606 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ79_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ79_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ79_EN1_MASK)
44607 
44608 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ80_EN1_MASK (0x10000U)
44609 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ80_EN1_SHIFT (16U)
44610 /*! REQ80_EN1 - Writing a 1 to REQ80_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */
44611 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ80_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ80_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ80_EN1_MASK)
44612 
44613 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ81_EN1_MASK (0x20000U)
44614 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ81_EN1_SHIFT (17U)
44615 /*! REQ81_EN1 - Writing a 1 to REQ81_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */
44616 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ81_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ81_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ81_EN1_MASK)
44617 
44618 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ82_EN1_MASK (0x40000U)
44619 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ82_EN1_SHIFT (18U)
44620 /*! REQ82_EN1 - Writing a 1 to REQ82_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */
44621 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ82_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ82_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ82_EN1_MASK)
44622 
44623 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ83_EN1_MASK (0x80000U)
44624 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ83_EN1_SHIFT (19U)
44625 /*! REQ83_EN1 - Writing a 1 to REQ83_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */
44626 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ83_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ83_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ83_EN1_MASK)
44627 
44628 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ84_EN1_MASK (0x100000U)
44629 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ84_EN1_SHIFT (20U)
44630 /*! REQ84_EN1 - Writing a 1 to REQ84_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */
44631 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ84_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ84_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ84_EN1_MASK)
44632 
44633 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ85_EN1_MASK (0x200000U)
44634 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ85_EN1_SHIFT (21U)
44635 /*! REQ85_EN1 - Writing a 1 to REQ85_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */
44636 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ85_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ85_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ85_EN1_MASK)
44637 
44638 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ86_EN1_MASK (0x400000U)
44639 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ86_EN1_SHIFT (22U)
44640 /*! REQ86_EN1 - Writing a 1 to REQ86_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */
44641 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ86_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ86_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ86_EN1_MASK)
44642 
44643 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ87_EN1_MASK (0x800000U)
44644 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ87_EN1_SHIFT (23U)
44645 /*! REQ87_EN1 - Writing a 1 to REQ87_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */
44646 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ87_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ87_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ87_EN1_MASK)
44647 
44648 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ88_EN1_MASK (0x1000000U)
44649 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ88_EN1_SHIFT (24U)
44650 /*! REQ88_EN1 - Writing a 1 to REQ88_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */
44651 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ88_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ88_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ88_EN1_MASK)
44652 
44653 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ89_EN1_MASK (0x2000000U)
44654 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ89_EN1_SHIFT (25U)
44655 /*! REQ89_EN1 - Writing a 1 to REQ89_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */
44656 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ89_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ89_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ89_EN1_MASK)
44657 
44658 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ90_EN1_MASK (0x4000000U)
44659 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ90_EN1_SHIFT (26U)
44660 /*! REQ90_EN1 - Writing a 1 to REQ90_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */
44661 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ90_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ90_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ90_EN1_MASK)
44662 
44663 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ91_EN1_MASK (0x8000000U)
44664 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ91_EN1_SHIFT (27U)
44665 /*! REQ91_EN1 - Writing a 1 to REQ91_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */
44666 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ91_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ91_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ91_EN1_MASK)
44667 
44668 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ92_EN1_MASK (0x10000000U)
44669 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ92_EN1_SHIFT (28U)
44670 /*! REQ92_EN1 - Writing a 1 to REQ92_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */
44671 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ92_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ92_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ92_EN1_MASK)
44672 
44673 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ93_EN1_MASK (0x20000000U)
44674 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ93_EN1_SHIFT (29U)
44675 /*! REQ93_EN1 - Writing a 1 to REQ93_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */
44676 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ93_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ93_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ93_EN1_MASK)
44677 
44678 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ94_EN1_MASK (0x40000000U)
44679 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ94_EN1_SHIFT (30U)
44680 /*! REQ94_EN1 - Writing a 1 to REQ94_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */
44681 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ94_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ94_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ94_EN1_MASK)
44682 
44683 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ95_EN1_MASK (0x80000000U)
44684 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ95_EN1_SHIFT (31U)
44685 /*! REQ95_EN1 - Writing a 1 to REQ95_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */
44686 #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ95_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ95_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ95_EN1_MASK)
44687 /*! @} */
44688 
44689 /*! @name DMA1_REQ_ENABLE2_CLR - DMA1 Request Enable2 */
44690 /*! @{ */
44691 
44692 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ64_EN1_MASK (0x1U)
44693 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ64_EN1_SHIFT (0U)
44694 /*! REQ64_EN1 - Writing a 1 to REQ64_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */
44695 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ64_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ64_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ64_EN1_MASK)
44696 
44697 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ65_EN1_MASK (0x2U)
44698 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ65_EN1_SHIFT (1U)
44699 /*! REQ65_EN1 - Writing a 1 to REQ65_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */
44700 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ65_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ65_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ65_EN1_MASK)
44701 
44702 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ66_EN1_MASK (0x4U)
44703 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ66_EN1_SHIFT (2U)
44704 /*! REQ66_EN1 - Writing a 1 to REQ66_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */
44705 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ66_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ66_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ66_EN1_MASK)
44706 
44707 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ67_EN1_MASK (0x8U)
44708 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ67_EN1_SHIFT (3U)
44709 /*! REQ67_EN1 - Writing a 1 to REQ67_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */
44710 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ67_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ67_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ67_EN1_MASK)
44711 
44712 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ68_EN1_MASK (0x10U)
44713 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ68_EN1_SHIFT (4U)
44714 /*! REQ68_EN1 - Writing a 1 to REQ68_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */
44715 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ68_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ68_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ68_EN1_MASK)
44716 
44717 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ69_EN1_MASK (0x20U)
44718 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ69_EN1_SHIFT (5U)
44719 /*! REQ69_EN1 - Writing a 1 to REQ69_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */
44720 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ69_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ69_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ69_EN1_MASK)
44721 
44722 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ70_EN1_MASK (0x40U)
44723 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ70_EN1_SHIFT (6U)
44724 /*! REQ70_EN1 - Writing a 1 to REQ70_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */
44725 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ70_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ70_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ70_EN1_MASK)
44726 
44727 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ71_EN1_MASK (0x80U)
44728 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ71_EN1_SHIFT (7U)
44729 /*! REQ71_EN1 - Writing a 1 to REQ71_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */
44730 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ71_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ71_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ71_EN1_MASK)
44731 
44732 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ72_EN1_MASK (0x100U)
44733 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ72_EN1_SHIFT (8U)
44734 /*! REQ72_EN1 - Writing a 1 to REQ72_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */
44735 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ72_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ72_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ72_EN1_MASK)
44736 
44737 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ73_EN1_MASK (0x200U)
44738 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ73_EN1_SHIFT (9U)
44739 /*! REQ73_EN1 - Writing a 1 to REQ73_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */
44740 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ73_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ73_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ73_EN1_MASK)
44741 
44742 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ74_EN1_MASK (0x400U)
44743 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ74_EN1_SHIFT (10U)
44744 /*! REQ74_EN1 - Writing a 1 to REQ74_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */
44745 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ74_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ74_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ74_EN1_MASK)
44746 
44747 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ75_EN1_MASK (0x800U)
44748 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ75_EN1_SHIFT (11U)
44749 /*! REQ75_EN1 - Writing a 1 to REQ75_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */
44750 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ75_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ75_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ75_EN1_MASK)
44751 
44752 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ76_EN1_MASK (0x1000U)
44753 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ76_EN1_SHIFT (12U)
44754 /*! REQ76_EN1 - Writing a 1 to REQ76_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */
44755 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ76_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ76_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ76_EN1_MASK)
44756 
44757 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ77_EN1_MASK (0x2000U)
44758 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ77_EN1_SHIFT (13U)
44759 /*! REQ77_EN1 - Writing a 1 to REQ77_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */
44760 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ77_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ77_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ77_EN1_MASK)
44761 
44762 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ78_EN1_MASK (0x4000U)
44763 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ78_EN1_SHIFT (14U)
44764 /*! REQ78_EN1 - Writing a 1 to REQ78_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */
44765 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ78_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ78_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ78_EN1_MASK)
44766 
44767 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ79_EN1_MASK (0x8000U)
44768 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ79_EN1_SHIFT (15U)
44769 /*! REQ79_EN1 - Writing a 1 to REQ79_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */
44770 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ79_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ79_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ79_EN1_MASK)
44771 
44772 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ80_EN1_MASK (0x10000U)
44773 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ80_EN1_SHIFT (16U)
44774 /*! REQ80_EN1 - Writing a 1 to REQ80_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */
44775 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ80_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ80_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ80_EN1_MASK)
44776 
44777 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ81_EN1_MASK (0x20000U)
44778 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ81_EN1_SHIFT (17U)
44779 /*! REQ81_EN1 - Writing a 1 to REQ81_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */
44780 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ81_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ81_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ81_EN1_MASK)
44781 
44782 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ82_EN1_MASK (0x40000U)
44783 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ82_EN1_SHIFT (18U)
44784 /*! REQ82_EN1 - Writing a 1 to REQ82_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */
44785 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ82_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ82_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ82_EN1_MASK)
44786 
44787 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ83_EN1_MASK (0x80000U)
44788 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ83_EN1_SHIFT (19U)
44789 /*! REQ83_EN1 - Writing a 1 to REQ83_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */
44790 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ83_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ83_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ83_EN1_MASK)
44791 
44792 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ84_EN1_MASK (0x100000U)
44793 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ84_EN1_SHIFT (20U)
44794 /*! REQ84_EN1 - Writing a 1 to REQ84_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */
44795 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ84_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ84_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ84_EN1_MASK)
44796 
44797 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ85_EN1_MASK (0x200000U)
44798 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ85_EN1_SHIFT (21U)
44799 /*! REQ85_EN1 - Writing a 1 to REQ85_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */
44800 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ85_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ85_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ85_EN1_MASK)
44801 
44802 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ86_EN1_MASK (0x400000U)
44803 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ86_EN1_SHIFT (22U)
44804 /*! REQ86_EN1 - Writing a 1 to REQ86_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */
44805 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ86_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ86_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ86_EN1_MASK)
44806 
44807 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ87_EN1_MASK (0x800000U)
44808 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ87_EN1_SHIFT (23U)
44809 /*! REQ87_EN1 - Writing a 1 to REQ87_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */
44810 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ87_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ87_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ87_EN1_MASK)
44811 
44812 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ88_EN1_MASK (0x1000000U)
44813 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ88_EN1_SHIFT (24U)
44814 /*! REQ88_EN1 - Writing a 1 to REQ88_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */
44815 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ88_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ88_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ88_EN1_MASK)
44816 
44817 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ89_EN1_MASK (0x2000000U)
44818 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ89_EN1_SHIFT (25U)
44819 /*! REQ89_EN1 - Writing a 1 to REQ89_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */
44820 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ89_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ89_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ89_EN1_MASK)
44821 
44822 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ90_EN1_MASK (0x4000000U)
44823 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ90_EN1_SHIFT (26U)
44824 /*! REQ90_EN1 - Writing a 1 to REQ90_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */
44825 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ90_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ90_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ90_EN1_MASK)
44826 
44827 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ91_EN1_MASK (0x8000000U)
44828 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ91_EN1_SHIFT (27U)
44829 /*! REQ91_EN1 - Writing a 1 to REQ91_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */
44830 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ91_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ91_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ91_EN1_MASK)
44831 
44832 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ92_EN1_MASK (0x10000000U)
44833 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ92_EN1_SHIFT (28U)
44834 /*! REQ92_EN1 - Writing a 1 to REQ92_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */
44835 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ92_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ92_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ92_EN1_MASK)
44836 
44837 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ93_EN1_MASK (0x20000000U)
44838 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ93_EN1_SHIFT (29U)
44839 /*! REQ93_EN1 - Writing a 1 to REQ93_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */
44840 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ93_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ93_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ93_EN1_MASK)
44841 
44842 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ94_EN1_MASK (0x40000000U)
44843 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ94_EN1_SHIFT (30U)
44844 /*! REQ94_EN1 - Writing a 1 to REQ94_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */
44845 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ94_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ94_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ94_EN1_MASK)
44846 
44847 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ95_EN1_MASK (0x80000000U)
44848 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ95_EN1_SHIFT (31U)
44849 /*! REQ95_EN1 - Writing a 1 to REQ95_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */
44850 #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ95_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ95_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ95_EN1_MASK)
44851 /*! @} */
44852 
44853 /*! @name DMA1_REQ_ENABLE2_TOG - DMA1 Request Enable2 */
44854 /*! @{ */
44855 
44856 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ64_EN1_MASK (0x1U)
44857 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ64_EN1_SHIFT (0U)
44858 /*! REQ64_EN1 - Writing a 1 to REQ64_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */
44859 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ64_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ64_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ64_EN1_MASK)
44860 
44861 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ65_EN1_MASK (0x2U)
44862 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ65_EN1_SHIFT (1U)
44863 /*! REQ65_EN1 - Writing a 1 to REQ65_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */
44864 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ65_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ65_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ65_EN1_MASK)
44865 
44866 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ66_EN1_MASK (0x4U)
44867 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ66_EN1_SHIFT (2U)
44868 /*! REQ66_EN1 - Writing a 1 to REQ66_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */
44869 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ66_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ66_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ66_EN1_MASK)
44870 
44871 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ67_EN1_MASK (0x8U)
44872 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ67_EN1_SHIFT (3U)
44873 /*! REQ67_EN1 - Writing a 1 to REQ67_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */
44874 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ67_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ67_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ67_EN1_MASK)
44875 
44876 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ68_EN1_MASK (0x10U)
44877 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ68_EN1_SHIFT (4U)
44878 /*! REQ68_EN1 - Writing a 1 to REQ68_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */
44879 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ68_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ68_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ68_EN1_MASK)
44880 
44881 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ69_EN1_MASK (0x20U)
44882 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ69_EN1_SHIFT (5U)
44883 /*! REQ69_EN1 - Writing a 1 to REQ69_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */
44884 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ69_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ69_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ69_EN1_MASK)
44885 
44886 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ70_EN1_MASK (0x40U)
44887 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ70_EN1_SHIFT (6U)
44888 /*! REQ70_EN1 - Writing a 1 to REQ70_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */
44889 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ70_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ70_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ70_EN1_MASK)
44890 
44891 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ71_EN1_MASK (0x80U)
44892 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ71_EN1_SHIFT (7U)
44893 /*! REQ71_EN1 - Writing a 1 to REQ71_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */
44894 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ71_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ71_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ71_EN1_MASK)
44895 
44896 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ72_EN1_MASK (0x100U)
44897 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ72_EN1_SHIFT (8U)
44898 /*! REQ72_EN1 - Writing a 1 to REQ72_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */
44899 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ72_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ72_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ72_EN1_MASK)
44900 
44901 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ73_EN1_MASK (0x200U)
44902 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ73_EN1_SHIFT (9U)
44903 /*! REQ73_EN1 - Writing a 1 to REQ73_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */
44904 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ73_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ73_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ73_EN1_MASK)
44905 
44906 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ74_EN1_MASK (0x400U)
44907 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ74_EN1_SHIFT (10U)
44908 /*! REQ74_EN1 - Writing a 1 to REQ74_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */
44909 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ74_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ74_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ74_EN1_MASK)
44910 
44911 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ75_EN1_MASK (0x800U)
44912 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ75_EN1_SHIFT (11U)
44913 /*! REQ75_EN1 - Writing a 1 to REQ75_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */
44914 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ75_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ75_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ75_EN1_MASK)
44915 
44916 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ76_EN1_MASK (0x1000U)
44917 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ76_EN1_SHIFT (12U)
44918 /*! REQ76_EN1 - Writing a 1 to REQ76_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */
44919 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ76_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ76_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ76_EN1_MASK)
44920 
44921 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ77_EN1_MASK (0x2000U)
44922 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ77_EN1_SHIFT (13U)
44923 /*! REQ77_EN1 - Writing a 1 to REQ77_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */
44924 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ77_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ77_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ77_EN1_MASK)
44925 
44926 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ78_EN1_MASK (0x4000U)
44927 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ78_EN1_SHIFT (14U)
44928 /*! REQ78_EN1 - Writing a 1 to REQ78_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */
44929 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ78_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ78_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ78_EN1_MASK)
44930 
44931 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ79_EN1_MASK (0x8000U)
44932 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ79_EN1_SHIFT (15U)
44933 /*! REQ79_EN1 - Writing a 1 to REQ79_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */
44934 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ79_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ79_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ79_EN1_MASK)
44935 
44936 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ80_EN1_MASK (0x10000U)
44937 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ80_EN1_SHIFT (16U)
44938 /*! REQ80_EN1 - Writing a 1 to REQ80_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */
44939 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ80_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ80_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ80_EN1_MASK)
44940 
44941 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ81_EN1_MASK (0x20000U)
44942 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ81_EN1_SHIFT (17U)
44943 /*! REQ81_EN1 - Writing a 1 to REQ81_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */
44944 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ81_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ81_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ81_EN1_MASK)
44945 
44946 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ82_EN1_MASK (0x40000U)
44947 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ82_EN1_SHIFT (18U)
44948 /*! REQ82_EN1 - Writing a 1 to REQ82_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */
44949 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ82_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ82_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ82_EN1_MASK)
44950 
44951 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ83_EN1_MASK (0x80000U)
44952 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ83_EN1_SHIFT (19U)
44953 /*! REQ83_EN1 - Writing a 1 to REQ83_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */
44954 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ83_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ83_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ83_EN1_MASK)
44955 
44956 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ84_EN1_MASK (0x100000U)
44957 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ84_EN1_SHIFT (20U)
44958 /*! REQ84_EN1 - Writing a 1 to REQ84_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */
44959 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ84_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ84_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ84_EN1_MASK)
44960 
44961 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ85_EN1_MASK (0x200000U)
44962 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ85_EN1_SHIFT (21U)
44963 /*! REQ85_EN1 - Writing a 1 to REQ85_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */
44964 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ85_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ85_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ85_EN1_MASK)
44965 
44966 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ86_EN1_MASK (0x400000U)
44967 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ86_EN1_SHIFT (22U)
44968 /*! REQ86_EN1 - Writing a 1 to REQ86_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */
44969 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ86_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ86_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ86_EN1_MASK)
44970 
44971 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ87_EN1_MASK (0x800000U)
44972 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ87_EN1_SHIFT (23U)
44973 /*! REQ87_EN1 - Writing a 1 to REQ87_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */
44974 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ87_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ87_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ87_EN1_MASK)
44975 
44976 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ88_EN1_MASK (0x1000000U)
44977 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ88_EN1_SHIFT (24U)
44978 /*! REQ88_EN1 - Writing a 1 to REQ88_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */
44979 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ88_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ88_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ88_EN1_MASK)
44980 
44981 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ89_EN1_MASK (0x2000000U)
44982 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ89_EN1_SHIFT (25U)
44983 /*! REQ89_EN1 - Writing a 1 to REQ89_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */
44984 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ89_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ89_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ89_EN1_MASK)
44985 
44986 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ90_EN1_MASK (0x4000000U)
44987 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ90_EN1_SHIFT (26U)
44988 /*! REQ90_EN1 - Writing a 1 to REQ90_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */
44989 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ90_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ90_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ90_EN1_MASK)
44990 
44991 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ91_EN1_MASK (0x8000000U)
44992 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ91_EN1_SHIFT (27U)
44993 /*! REQ91_EN1 - Writing a 1 to REQ91_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */
44994 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ91_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ91_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ91_EN1_MASK)
44995 
44996 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ92_EN1_MASK (0x10000000U)
44997 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ92_EN1_SHIFT (28U)
44998 /*! REQ92_EN1 - Writing a 1 to REQ92_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */
44999 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ92_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ92_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ92_EN1_MASK)
45000 
45001 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ93_EN1_MASK (0x20000000U)
45002 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ93_EN1_SHIFT (29U)
45003 /*! REQ93_EN1 - Writing a 1 to REQ93_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */
45004 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ93_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ93_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ93_EN1_MASK)
45005 
45006 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ94_EN1_MASK (0x40000000U)
45007 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ94_EN1_SHIFT (30U)
45008 /*! REQ94_EN1 - Writing a 1 to REQ94_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */
45009 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ94_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ94_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ94_EN1_MASK)
45010 
45011 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ95_EN1_MASK (0x80000000U)
45012 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ95_EN1_SHIFT (31U)
45013 /*! REQ95_EN1 - Writing a 1 to REQ95_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */
45014 #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ95_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ95_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ95_EN1_MASK)
45015 /*! @} */
45016 
45017 /*! @name DMA1_REQ_ENABLE3 - DMA1 Request Enable3 */
45018 /*! @{ */
45019 
45020 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ96_EN1_MASK (0x1U)
45021 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ96_EN1_SHIFT (0U)
45022 /*! REQ96_EN1 - This register is used to enable and disable I3C0 transmit request.
45023  *  0b0..Disable
45024  *  0b1..Enable
45025  */
45026 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ96_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ96_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ96_EN1_MASK)
45027 
45028 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ97_EN1_MASK (0x2U)
45029 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ97_EN1_SHIFT (1U)
45030 /*! REQ97_EN1 - This register is used to enable and disable I3C1 receive request.
45031  *  0b0..Disable
45032  *  0b1..Enable
45033  */
45034 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ97_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ97_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ97_EN1_MASK)
45035 
45036 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ98_EN1_MASK (0x4U)
45037 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ98_EN1_SHIFT (2U)
45038 /*! REQ98_EN1 - This register is used to enable and disable I3C1 transmit request.
45039  *  0b0..Disable
45040  *  0b1..Enable
45041  */
45042 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ98_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ98_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ98_EN1_MASK)
45043 
45044 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ99_EN1_MASK (0x8U)
45045 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ99_EN1_SHIFT (3U)
45046 /*! REQ99_EN1 - This register is used to enable and disable SAI0 receive request.
45047  *  0b0..Disable
45048  *  0b1..Enable
45049  */
45050 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ99_EN1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ99_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ99_EN1_MASK)
45051 
45052 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ100_EN1_MASK (0x10U)
45053 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ100_EN1_SHIFT (4U)
45054 /*! REQ100_EN1 - This register is used to enable and disable SAI0 transmit request.
45055  *  0b0..Disable
45056  *  0b1..Enable
45057  */
45058 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ100_EN1(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ100_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ100_EN1_MASK)
45059 
45060 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ101_EN1_MASK (0x20U)
45061 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ101_EN1_SHIFT (5U)
45062 /*! REQ101_EN1 - This register is used to enable and disable SAI1 receive request.
45063  *  0b0..Disable
45064  *  0b1..Enable
45065  */
45066 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ101_EN1(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ101_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ101_EN1_MASK)
45067 
45068 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ102_EN1_MASK (0x40U)
45069 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ102_EN1_SHIFT (6U)
45070 /*! REQ102_EN1 - This register is used to enable and disable SAI1 transmit request.
45071  *  0b0..Disable
45072  *  0b1..Enable
45073  */
45074 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ102_EN1(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ102_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ102_EN1_MASK)
45075 
45076 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ103_EN1_MASK (0x80U)
45077 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ103_EN1_SHIFT (7U)
45078 /*! REQ103_EN1 - This register is used to enable and disable SINC0 ipd_req_sinc[0] or ipd_req_alt [0] request.
45079  *  0b0..Disable
45080  *  0b1..Enable
45081  */
45082 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ103_EN1(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ103_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ103_EN1_MASK)
45083 
45084 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ104_EN1_MASK (0x100U)
45085 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ104_EN1_SHIFT (8U)
45086 /*! REQ104_EN1 - This register is used to enable and disable SINC0 ipd_req_sinc[1] or ipd_req_alt [1] request.
45087  *  0b0..Disable
45088  *  0b1..Enable
45089  */
45090 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ104_EN1(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ104_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ104_EN1_MASK)
45091 
45092 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ105_EN1_MASK (0x200U)
45093 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ105_EN1_SHIFT (9U)
45094 /*! REQ105_EN1 - This register is used to enable and disable SINC0 ipd_req_sinc[2] or ipd_req_alt [2] request.
45095  *  0b0..Disable
45096  *  0b1..Enable
45097  */
45098 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ105_EN1(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ105_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ105_EN1_MASK)
45099 
45100 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ106_EN1_MASK (0x400U)
45101 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ106_EN1_SHIFT (10U)
45102 /*! REQ106_EN1 - This register is used to enable and disable SINC0 ipd_req_sinc[3] or ipd_req_alt [3] request.
45103  *  0b0..Disable
45104  *  0b1..Enable
45105  */
45106 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ106_EN1(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ106_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ106_EN1_MASK)
45107 
45108 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ107_EN1_MASK (0x800U)
45109 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ107_EN1_SHIFT (11U)
45110 /*! REQ107_EN1 - This register is used to enable and disable SINC0 ipd_req_sinc[4] or ipd_req_alt [4] request.
45111  *  0b0..Disable
45112  *  0b1..Enable
45113  */
45114 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ107_EN1(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ107_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ107_EN1_MASK)
45115 
45116 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ108_EN1_MASK (0x1000U)
45117 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ108_EN1_SHIFT (12U)
45118 /*! REQ108_EN1 - This register is used to enable and disable GPIO0 pin event request 0.
45119  *  0b0..Disable
45120  *  0b1..Enable
45121  */
45122 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ108_EN1(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ108_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ108_EN1_MASK)
45123 
45124 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ109_EN1_MASK (0x2000U)
45125 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ109_EN1_SHIFT (13U)
45126 /*! REQ109_EN1 - This register is used to enable and disable GPIO0 pin event request 1.
45127  *  0b0..Disable
45128  *  0b1..Enable
45129  */
45130 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ109_EN1(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ109_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ109_EN1_MASK)
45131 
45132 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ110_EN1_MASK (0x4000U)
45133 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ110_EN1_SHIFT (14U)
45134 /*! REQ110_EN1 - This register is used to enable and disable GPIO1 pin event request 0.
45135  *  0b0..Disable
45136  *  0b1..Enable
45137  */
45138 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ110_EN1(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ110_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ110_EN1_MASK)
45139 
45140 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ111_EN1_MASK (0x8000U)
45141 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ111_EN1_SHIFT (15U)
45142 /*! REQ111_EN1 - This register is used to enable and disable GPIO1 pin event request 1.
45143  *  0b0..Disable
45144  *  0b1..Enable
45145  */
45146 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ111_EN1(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ111_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ111_EN1_MASK)
45147 
45148 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ112_EN1_MASK (0x10000U)
45149 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ112_EN1_SHIFT (16U)
45150 /*! REQ112_EN1 - This register is used to enable and disable GPIO2 pin event request 0.
45151  *  0b0..Disable
45152  *  0b1..Enable
45153  */
45154 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ112_EN1(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ112_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ112_EN1_MASK)
45155 
45156 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ113_EN1_MASK (0x20000U)
45157 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ113_EN1_SHIFT (17U)
45158 /*! REQ113_EN1 - This register is used to enable and disable GPIO2 pin event request 1.
45159  *  0b0..Disable
45160  *  0b1..Enable
45161  */
45162 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ113_EN1(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ113_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ113_EN1_MASK)
45163 
45164 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ114_EN1_MASK (0x40000U)
45165 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ114_EN1_SHIFT (18U)
45166 /*! REQ114_EN1 - This register is used to enable and disable GPIO3 pin event request 0.
45167  *  0b0..Disable
45168  *  0b1..Enable
45169  */
45170 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ114_EN1(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ114_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ114_EN1_MASK)
45171 
45172 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ115_EN1_MASK (0x80000U)
45173 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ115_EN1_SHIFT (19U)
45174 /*! REQ115_EN1 - This register is used to enable and disable GPIO3 pin event request 1.
45175  *  0b0..Disable
45176  *  0b1..Enable
45177  */
45178 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ115_EN1(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ115_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ115_EN1_MASK)
45179 
45180 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ116_EN1_MASK (0x100000U)
45181 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ116_EN1_SHIFT (20U)
45182 /*! REQ116_EN1 - This register is used to enable and disable GPIO4 pin event request 0.
45183  *  0b0..Disable
45184  *  0b1..Enable
45185  */
45186 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ116_EN1(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ116_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ116_EN1_MASK)
45187 
45188 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ117_EN1_MASK (0x200000U)
45189 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ117_EN1_SHIFT (21U)
45190 /*! REQ117_EN1 - This register is used to enable and disable GPIO4 pin event request 1.
45191  *  0b0..Disable
45192  *  0b1..Enable
45193  */
45194 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ117_EN1(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ117_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ117_EN1_MASK)
45195 
45196 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ118_EN1_MASK (0x400000U)
45197 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ118_EN1_SHIFT (22U)
45198 /*! REQ118_EN1 - This register is used to enable and disable GPIO5 pin event request 0.
45199  *  0b0..Disable
45200  *  0b1..Enable
45201  */
45202 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ118_EN1(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ118_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ118_EN1_MASK)
45203 
45204 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ119_EN1_MASK (0x800000U)
45205 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ119_EN1_SHIFT (23U)
45206 /*! REQ119_EN1 - This register is used to enable and disable GPIO5 pin event request 1.
45207  *  0b0..Disable
45208  *  0b1..Enable
45209  */
45210 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ119_EN1(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ119_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ119_EN1_MASK)
45211 
45212 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ120_EN1_MASK (0x1000000U)
45213 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ120_EN1_SHIFT (24U)
45214 /*! REQ120_EN1 - This register is used to enable and disable TSI0 end of scan request.
45215  *  0b0..Disable
45216  *  0b1..Enable
45217  */
45218 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ120_EN1(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ120_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ120_EN1_MASK)
45219 
45220 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ121_EN1_MASK (0x2000000U)
45221 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ121_EN1_SHIFT (25U)
45222 /*! REQ121_EN1 - This register is used to enable and disable TSI0 out of range request.
45223  *  0b0..Disable
45224  *  0b1..Enable
45225  */
45226 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ121_EN1(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ121_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ121_EN1_MASK)
45227 /*! @} */
45228 
45229 /*! @name DMA1_REQ_ENABLE3_SET - DMA1 Request Enable3 */
45230 /*! @{ */
45231 
45232 #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ96_EN1_MASK (0x1U)
45233 #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ96_EN1_SHIFT (0U)
45234 /*! REQ96_EN1 - Writing a 1 to REQ96_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */
45235 #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ96_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ96_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ96_EN1_MASK)
45236 
45237 #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ97_EN1_MASK (0x2U)
45238 #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ97_EN1_SHIFT (1U)
45239 /*! REQ97_EN1 - Writing a 1 to REQ97_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */
45240 #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ97_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ97_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ97_EN1_MASK)
45241 
45242 #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ98_EN1_MASK (0x4U)
45243 #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ98_EN1_SHIFT (2U)
45244 /*! REQ98_EN1 - Writing a 1 to REQ98_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */
45245 #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ98_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ98_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ98_EN1_MASK)
45246 
45247 #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ99_EN1_MASK (0x8U)
45248 #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ99_EN1_SHIFT (3U)
45249 /*! REQ99_EN1 - Writing a 1 to REQ99_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */
45250 #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ99_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ99_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ99_EN1_MASK)
45251 
45252 #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ100_EN1_MASK (0x10U)
45253 #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ100_EN1_SHIFT (4U)
45254 /*! REQ100_EN1 - Writing a 1 to REQ100_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */
45255 #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ100_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ100_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ100_EN1_MASK)
45256 
45257 #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ101_EN1_MASK (0x20U)
45258 #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ101_EN1_SHIFT (5U)
45259 /*! REQ101_EN1 - Writing a 1 to REQ101_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */
45260 #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ101_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ101_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ101_EN1_MASK)
45261 
45262 #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ102_EN1_MASK (0x40U)
45263 #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ102_EN1_SHIFT (6U)
45264 /*! REQ102_EN1 - Writing a 1 to REQ102_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */
45265 #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ102_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ102_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ102_EN1_MASK)
45266 
45267 #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ103_EN1_MASK (0x80U)
45268 #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ103_EN1_SHIFT (7U)
45269 /*! REQ103_EN1 - Writing a 1 to REQ103_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */
45270 #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ103_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ103_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ103_EN1_MASK)
45271 
45272 #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ104_EN1_MASK (0x100U)
45273 #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ104_EN1_SHIFT (8U)
45274 /*! REQ104_EN1 - Writing a 1 to REQ104_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */
45275 #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ104_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ104_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ104_EN1_MASK)
45276 
45277 #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ105_EN1_MASK (0x200U)
45278 #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ105_EN1_SHIFT (9U)
45279 /*! REQ105_EN1 - Writing a 1 to REQ105_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */
45280 #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ105_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ105_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ105_EN1_MASK)
45281 
45282 #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ106_EN1_MASK (0x400U)
45283 #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ106_EN1_SHIFT (10U)
45284 /*! REQ106_EN1 - Writing a 1 to REQ106_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */
45285 #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ106_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ106_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ106_EN1_MASK)
45286 
45287 #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ107_EN1_MASK (0x800U)
45288 #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ107_EN1_SHIFT (11U)
45289 /*! REQ107_EN1 - Writing a 1 to REQ107_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */
45290 #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ107_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ107_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ107_EN1_MASK)
45291 
45292 #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ108_EN1_MASK (0x1000U)
45293 #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ108_EN1_SHIFT (12U)
45294 /*! REQ108_EN1 - Writing a 1 to REQ108_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */
45295 #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ108_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ108_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ108_EN1_MASK)
45296 
45297 #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ109_EN1_MASK (0x2000U)
45298 #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ109_EN1_SHIFT (13U)
45299 /*! REQ109_EN1 - Writing a 1 to REQ109_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */
45300 #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ109_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ109_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ109_EN1_MASK)
45301 
45302 #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ110_EN1_MASK (0x4000U)
45303 #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ110_EN1_SHIFT (14U)
45304 /*! REQ110_EN1 - Writing a 1 to REQ110_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */
45305 #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ110_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ110_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ110_EN1_MASK)
45306 
45307 #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ111_EN1_MASK (0x8000U)
45308 #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ111_EN1_SHIFT (15U)
45309 /*! REQ111_EN1 - Writing a 1 to REQ111_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */
45310 #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ111_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ111_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ111_EN1_MASK)
45311 
45312 #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ112_EN1_MASK (0x10000U)
45313 #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ112_EN1_SHIFT (16U)
45314 /*! REQ112_EN1 - Writing a 1 to REQ112_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */
45315 #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ112_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ112_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ112_EN1_MASK)
45316 
45317 #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ113_EN1_MASK (0x20000U)
45318 #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ113_EN1_SHIFT (17U)
45319 /*! REQ113_EN1 - Writing a 1 to REQ113_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */
45320 #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ113_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ113_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ113_EN1_MASK)
45321 
45322 #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ114_EN1_MASK (0x40000U)
45323 #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ114_EN1_SHIFT (18U)
45324 /*! REQ114_EN1 - Writing a 1 to REQ114_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */
45325 #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ114_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ114_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ114_EN1_MASK)
45326 
45327 #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ115_EN1_MASK (0x80000U)
45328 #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ115_EN1_SHIFT (19U)
45329 /*! REQ115_EN1 - Writing a 1 to REQ115_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */
45330 #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ115_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ115_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ115_EN1_MASK)
45331 
45332 #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ116_EN1_MASK (0x100000U)
45333 #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ116_EN1_SHIFT (20U)
45334 /*! REQ116_EN1 - Writing a 1 to REQ116_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */
45335 #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ116_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ116_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ116_EN1_MASK)
45336 
45337 #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ117_EN1_MASK (0x200000U)
45338 #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ117_EN1_SHIFT (21U)
45339 /*! REQ117_EN1 - Writing a 1 to REQ117_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */
45340 #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ117_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ117_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ117_EN1_MASK)
45341 
45342 #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ118_EN1_MASK (0x400000U)
45343 #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ118_EN1_SHIFT (22U)
45344 /*! REQ118_EN1 - Writing a 1 to REQ118_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */
45345 #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ118_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ118_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ118_EN1_MASK)
45346 
45347 #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ119_EN1_MASK (0x800000U)
45348 #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ119_EN1_SHIFT (23U)
45349 /*! REQ119_EN1 - Writing a 1 to REQ119_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */
45350 #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ119_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ119_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ119_EN1_MASK)
45351 
45352 #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ120_EN1_MASK (0x1000000U)
45353 #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ120_EN1_SHIFT (24U)
45354 /*! REQ120_EN1 - Writing a 1 to REQ120_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */
45355 #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ120_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ120_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ120_EN1_MASK)
45356 
45357 #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ121_EN1_MASK (0x2000000U)
45358 #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ121_EN1_SHIFT (25U)
45359 /*! REQ121_EN1 - Writing a 1 to REQ121_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */
45360 #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ121_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ121_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ121_EN1_MASK)
45361 /*! @} */
45362 
45363 /*! @name DMA1_REQ_ENABLE3_CLR - DMA1 Request Enable3 */
45364 /*! @{ */
45365 
45366 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ96_EN1_MASK (0x1U)
45367 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ96_EN1_SHIFT (0U)
45368 /*! REQ96_EN1 - Writing a 1 to REQ96_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */
45369 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ96_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ96_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ96_EN1_MASK)
45370 
45371 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ97_EN1_MASK (0x2U)
45372 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ97_EN1_SHIFT (1U)
45373 /*! REQ97_EN1 - Writing a 1 to REQ97_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */
45374 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ97_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ97_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ97_EN1_MASK)
45375 
45376 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ98_EN1_MASK (0x4U)
45377 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ98_EN1_SHIFT (2U)
45378 /*! REQ98_EN1 - Writing a 1 to REQ98_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */
45379 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ98_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ98_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ98_EN1_MASK)
45380 
45381 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ99_EN1_MASK (0x8U)
45382 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ99_EN1_SHIFT (3U)
45383 /*! REQ99_EN1 - Writing a 1 to REQ99_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */
45384 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ99_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ99_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ99_EN1_MASK)
45385 
45386 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ100_EN1_MASK (0x10U)
45387 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ100_EN1_SHIFT (4U)
45388 /*! REQ100_EN1 - Writing a 1 to REQ100_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */
45389 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ100_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ100_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ100_EN1_MASK)
45390 
45391 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ101_EN1_MASK (0x20U)
45392 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ101_EN1_SHIFT (5U)
45393 /*! REQ101_EN1 - Writing a 1 to REQ101_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */
45394 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ101_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ101_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ101_EN1_MASK)
45395 
45396 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ102_EN1_MASK (0x40U)
45397 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ102_EN1_SHIFT (6U)
45398 /*! REQ102_EN1 - Writing a 1 to REQ102_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */
45399 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ102_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ102_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ102_EN1_MASK)
45400 
45401 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ103_EN1_MASK (0x80U)
45402 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ103_EN1_SHIFT (7U)
45403 /*! REQ103_EN1 - Writing a 1 to REQ103_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */
45404 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ103_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ103_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ103_EN1_MASK)
45405 
45406 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ104_EN1_MASK (0x100U)
45407 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ104_EN1_SHIFT (8U)
45408 /*! REQ104_EN1 - Writing a 1 to REQ104_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */
45409 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ104_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ104_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ104_EN1_MASK)
45410 
45411 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ105_EN1_MASK (0x200U)
45412 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ105_EN1_SHIFT (9U)
45413 /*! REQ105_EN1 - Writing a 1 to REQ105_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */
45414 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ105_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ105_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ105_EN1_MASK)
45415 
45416 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ106_EN1_MASK (0x400U)
45417 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ106_EN1_SHIFT (10U)
45418 /*! REQ106_EN1 - Writing a 1 to REQ106_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */
45419 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ106_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ106_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ106_EN1_MASK)
45420 
45421 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ107_EN1_MASK (0x800U)
45422 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ107_EN1_SHIFT (11U)
45423 /*! REQ107_EN1 - Writing a 1 to REQ107_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */
45424 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ107_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ107_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ107_EN1_MASK)
45425 
45426 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ108_EN1_MASK (0x1000U)
45427 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ108_EN1_SHIFT (12U)
45428 /*! REQ108_EN1 - Writing a 1 to REQ108_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */
45429 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ108_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ108_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ108_EN1_MASK)
45430 
45431 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ109_EN1_MASK (0x2000U)
45432 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ109_EN1_SHIFT (13U)
45433 /*! REQ109_EN1 - Writing a 1 to REQ109_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */
45434 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ109_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ109_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ109_EN1_MASK)
45435 
45436 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ110_EN1_MASK (0x4000U)
45437 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ110_EN1_SHIFT (14U)
45438 /*! REQ110_EN1 - Writing a 1 to REQ110_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */
45439 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ110_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ110_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ110_EN1_MASK)
45440 
45441 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ111_EN1_MASK (0x8000U)
45442 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ111_EN1_SHIFT (15U)
45443 /*! REQ111_EN1 - Writing a 1 to REQ111_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */
45444 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ111_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ111_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ111_EN1_MASK)
45445 
45446 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ112_EN1_MASK (0x10000U)
45447 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ112_EN1_SHIFT (16U)
45448 /*! REQ112_EN1 - Writing a 1 to REQ112_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */
45449 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ112_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ112_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ112_EN1_MASK)
45450 
45451 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ113_EN1_MASK (0x20000U)
45452 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ113_EN1_SHIFT (17U)
45453 /*! REQ113_EN1 - Writing a 1 to REQ113_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */
45454 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ113_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ113_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ113_EN1_MASK)
45455 
45456 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ114_EN1_MASK (0x40000U)
45457 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ114_EN1_SHIFT (18U)
45458 /*! REQ114_EN1 - Writing a 1 to REQ114_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */
45459 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ114_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ114_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ114_EN1_MASK)
45460 
45461 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ115_EN1_MASK (0x80000U)
45462 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ115_EN1_SHIFT (19U)
45463 /*! REQ115_EN1 - Writing a 1 to REQ115_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */
45464 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ115_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ115_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ115_EN1_MASK)
45465 
45466 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ116_EN1_MASK (0x100000U)
45467 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ116_EN1_SHIFT (20U)
45468 /*! REQ116_EN1 - Writing a 1 to REQ116_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */
45469 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ116_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ116_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ116_EN1_MASK)
45470 
45471 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ117_EN1_MASK (0x200000U)
45472 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ117_EN1_SHIFT (21U)
45473 /*! REQ117_EN1 - Writing a 1 to REQ117_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */
45474 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ117_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ117_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ117_EN1_MASK)
45475 
45476 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ118_EN1_MASK (0x400000U)
45477 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ118_EN1_SHIFT (22U)
45478 /*! REQ118_EN1 - Writing a 1 to REQ118_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */
45479 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ118_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ118_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ118_EN1_MASK)
45480 
45481 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ119_EN1_MASK (0x800000U)
45482 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ119_EN1_SHIFT (23U)
45483 /*! REQ119_EN1 - Writing a 1 to REQ119_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */
45484 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ119_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ119_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ119_EN1_MASK)
45485 
45486 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ120_EN1_MASK (0x1000000U)
45487 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ120_EN1_SHIFT (24U)
45488 /*! REQ120_EN1 - Writing a 1 to REQ120_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */
45489 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ120_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ120_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ120_EN1_MASK)
45490 
45491 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ121_EN1_MASK (0x2000000U)
45492 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ121_EN1_SHIFT (25U)
45493 /*! REQ121_EN1 - Writing a 1 to REQ121_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3. */
45494 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ121_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ121_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ121_EN1_MASK)
45495 /*! @} */
45496 
45497 
45498 /*!
45499  * @}
45500  */ /* end of group INPUTMUX_Register_Masks */
45501 
45502 
45503 /* INPUTMUX - Peripheral instance base addresses */
45504 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
45505   /** Peripheral INPUTMUX0 base address */
45506   #define INPUTMUX0_BASE                           (0x50006000u)
45507   /** Peripheral INPUTMUX0 base address */
45508   #define INPUTMUX0_BASE_NS                        (0x40006000u)
45509   /** Peripheral INPUTMUX0 base pointer */
45510   #define INPUTMUX0                                ((INPUTMUX_Type *)INPUTMUX0_BASE)
45511   /** Peripheral INPUTMUX0 base pointer */
45512   #define INPUTMUX0_NS                             ((INPUTMUX_Type *)INPUTMUX0_BASE_NS)
45513   /** Array initializer of INPUTMUX peripheral base addresses */
45514   #define INPUTMUX_BASE_ADDRS                      { INPUTMUX0_BASE }
45515   /** Array initializer of INPUTMUX peripheral base pointers */
45516   #define INPUTMUX_BASE_PTRS                       { INPUTMUX0 }
45517   /** Array initializer of INPUTMUX peripheral base addresses */
45518   #define INPUTMUX_BASE_ADDRS_NS                   { INPUTMUX0_BASE_NS }
45519   /** Array initializer of INPUTMUX peripheral base pointers */
45520   #define INPUTMUX_BASE_PTRS_NS                    { INPUTMUX0_NS }
45521 #else
45522   /** Peripheral INPUTMUX0 base address */
45523   #define INPUTMUX0_BASE                           (0x40006000u)
45524   /** Peripheral INPUTMUX0 base pointer */
45525   #define INPUTMUX0                                ((INPUTMUX_Type *)INPUTMUX0_BASE)
45526   /** Array initializer of INPUTMUX peripheral base addresses */
45527   #define INPUTMUX_BASE_ADDRS                      { INPUTMUX0_BASE }
45528   /** Array initializer of INPUTMUX peripheral base pointers */
45529   #define INPUTMUX_BASE_PTRS                       { INPUTMUX0 }
45530 #endif
45531 /* Backward compatibility for INPUTMUX */
45532 #define INPUTMUX    INPUTMUX0
45533 
45534 
45535 /*!
45536  * @}
45537  */ /* end of group INPUTMUX_Peripheral_Access_Layer */
45538 
45539 
45540 /* ----------------------------------------------------------------------------
45541    -- INTM Peripheral Access Layer
45542    ---------------------------------------------------------------------------- */
45543 
45544 /*!
45545  * @addtogroup INTM_Peripheral_Access_Layer INTM Peripheral Access Layer
45546  * @{
45547  */
45548 
45549 /** INTM - Register Layout Typedef */
45550 typedef struct {
45551   __IO uint32_t INTM_MM;                           /**< Monitor Mode, offset: 0x0 */
45552   __O  uint32_t INTM_IACK;                         /**< Interrupt Acknowledge, offset: 0x4 */
45553   struct {                                         /* offset: 0x8, array step: 0x10 */
45554     __IO uint32_t INTM_IRQSEL;                       /**< Interrupt Request Select for Monitor 0..Interrupt Request Select for Monitor 3, array offset: 0x8, array step: 0x10 */
45555     __IO uint32_t INTM_LATENCY;                      /**< Interrupt Latency for Monitor 0..Interrupt Latency for Monitor 3, array offset: 0xC, array step: 0x10 */
45556     __IO uint32_t INTM_TIMER;                        /**< Timer for Monitor 0..Timer for Monitor 3, array offset: 0x10, array step: 0x10 */
45557     __I  uint32_t INTM_STATUS;                       /**< Status for Monitor 0..Status for Monitor 3, array offset: 0x14, array step: 0x10 */
45558   } MON[4];
45559 } INTM_Type;
45560 
45561 /* ----------------------------------------------------------------------------
45562    -- INTM Register Masks
45563    ---------------------------------------------------------------------------- */
45564 
45565 /*!
45566  * @addtogroup INTM_Register_Masks INTM Register Masks
45567  * @{
45568  */
45569 
45570 /*! @name INTM_MM - Monitor Mode */
45571 /*! @{ */
45572 
45573 #define INTM_INTM_MM_MM_MASK                     (0x1U)
45574 #define INTM_INTM_MM_MM_SHIFT                    (0U)
45575 /*! MM - Monitor Mode
45576  *  0b1..Enable
45577  *  0b0..Disable
45578  */
45579 #define INTM_INTM_MM_MM(x)                       (((uint32_t)(((uint32_t)(x)) << INTM_INTM_MM_MM_SHIFT)) & INTM_INTM_MM_MM_MASK)
45580 /*! @} */
45581 
45582 /*! @name INTM_IACK - Interrupt Acknowledge */
45583 /*! @{ */
45584 
45585 #define INTM_INTM_IACK_IRQ_MASK                  (0x3FFU)
45586 #define INTM_INTM_IACK_IRQ_SHIFT                 (0U)
45587 /*! IRQ - Interrupt Request */
45588 #define INTM_INTM_IACK_IRQ(x)                    (((uint32_t)(((uint32_t)(x)) << INTM_INTM_IACK_IRQ_SHIFT)) & INTM_INTM_IACK_IRQ_MASK)
45589 /*! @} */
45590 
45591 /*! @name MON_INTM_IRQSEL - Interrupt Request Select for Monitor 0..Interrupt Request Select for Monitor 3 */
45592 /*! @{ */
45593 
45594 #define INTM_MON_INTM_IRQSEL_IRQ_MASK            (0x3FFU)
45595 #define INTM_MON_INTM_IRQSEL_IRQ_SHIFT           (0U)
45596 /*! IRQ - Interrupt Request */
45597 #define INTM_MON_INTM_IRQSEL_IRQ(x)              (((uint32_t)(((uint32_t)(x)) << INTM_MON_INTM_IRQSEL_IRQ_SHIFT)) & INTM_MON_INTM_IRQSEL_IRQ_MASK)
45598 /*! @} */
45599 
45600 /* The count of INTM_MON_INTM_IRQSEL */
45601 #define INTM_MON_INTM_IRQSEL_COUNT               (4U)
45602 
45603 /*! @name MON_INTM_LATENCY - Interrupt Latency for Monitor 0..Interrupt Latency for Monitor 3 */
45604 /*! @{ */
45605 
45606 #define INTM_MON_INTM_LATENCY_LAT_MASK           (0xFFFFFFU)
45607 #define INTM_MON_INTM_LATENCY_LAT_SHIFT          (0U)
45608 /*! LAT - Latency */
45609 #define INTM_MON_INTM_LATENCY_LAT(x)             (((uint32_t)(((uint32_t)(x)) << INTM_MON_INTM_LATENCY_LAT_SHIFT)) & INTM_MON_INTM_LATENCY_LAT_MASK)
45610 /*! @} */
45611 
45612 /* The count of INTM_MON_INTM_LATENCY */
45613 #define INTM_MON_INTM_LATENCY_COUNT              (4U)
45614 
45615 /*! @name MON_INTM_TIMER - Timer for Monitor 0..Timer for Monitor 3 */
45616 /*! @{ */
45617 
45618 #define INTM_MON_INTM_TIMER_TIMER_MASK           (0xFFFFFFU)
45619 #define INTM_MON_INTM_TIMER_TIMER_SHIFT          (0U)
45620 /*! TIMER - Timer */
45621 #define INTM_MON_INTM_TIMER_TIMER(x)             (((uint32_t)(((uint32_t)(x)) << INTM_MON_INTM_TIMER_TIMER_SHIFT)) & INTM_MON_INTM_TIMER_TIMER_MASK)
45622 /*! @} */
45623 
45624 /* The count of INTM_MON_INTM_TIMER */
45625 #define INTM_MON_INTM_TIMER_COUNT                (4U)
45626 
45627 /*! @name MON_INTM_STATUS - Status for Monitor 0..Status for Monitor 3 */
45628 /*! @{ */
45629 
45630 #define INTM_MON_INTM_STATUS_STATUS_MASK         (0x1U)
45631 #define INTM_MON_INTM_STATUS_STATUS_SHIFT        (0U)
45632 /*! STATUS - Monitor status
45633  *  0b1..Exceeded
45634  *  0b0..Did not exceed
45635  */
45636 #define INTM_MON_INTM_STATUS_STATUS(x)           (((uint32_t)(((uint32_t)(x)) << INTM_MON_INTM_STATUS_STATUS_SHIFT)) & INTM_MON_INTM_STATUS_STATUS_MASK)
45637 /*! @} */
45638 
45639 /* The count of INTM_MON_INTM_STATUS */
45640 #define INTM_MON_INTM_STATUS_COUNT               (4U)
45641 
45642 
45643 /*!
45644  * @}
45645  */ /* end of group INTM_Register_Masks */
45646 
45647 
45648 /* INTM - Peripheral instance base addresses */
45649 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
45650   /** Peripheral INTM0 base address */
45651   #define INTM0_BASE                               (0x5005D000u)
45652   /** Peripheral INTM0 base address */
45653   #define INTM0_BASE_NS                            (0x4005D000u)
45654   /** Peripheral INTM0 base pointer */
45655   #define INTM0                                    ((INTM_Type *)INTM0_BASE)
45656   /** Peripheral INTM0 base pointer */
45657   #define INTM0_NS                                 ((INTM_Type *)INTM0_BASE_NS)
45658   /** Array initializer of INTM peripheral base addresses */
45659   #define INTM_BASE_ADDRS                          { INTM0_BASE }
45660   /** Array initializer of INTM peripheral base pointers */
45661   #define INTM_BASE_PTRS                           { INTM0 }
45662   /** Array initializer of INTM peripheral base addresses */
45663   #define INTM_BASE_ADDRS_NS                       { INTM0_BASE_NS }
45664   /** Array initializer of INTM peripheral base pointers */
45665   #define INTM_BASE_PTRS_NS                        { INTM0_NS }
45666 #else
45667   /** Peripheral INTM0 base address */
45668   #define INTM0_BASE                               (0x4005D000u)
45669   /** Peripheral INTM0 base pointer */
45670   #define INTM0                                    ((INTM_Type *)INTM0_BASE)
45671   /** Array initializer of INTM peripheral base addresses */
45672   #define INTM_BASE_ADDRS                          { INTM0_BASE }
45673   /** Array initializer of INTM peripheral base pointers */
45674   #define INTM_BASE_PTRS                           { INTM0 }
45675 #endif
45676 
45677 /*!
45678  * @}
45679  */ /* end of group INTM_Peripheral_Access_Layer */
45680 
45681 
45682 /* ----------------------------------------------------------------------------
45683    -- ITRC Peripheral Access Layer
45684    ---------------------------------------------------------------------------- */
45685 
45686 /*!
45687  * @addtogroup ITRC_Peripheral_Access_Layer ITRC Peripheral Access Layer
45688  * @{
45689  */
45690 
45691 /** ITRC - Register Layout Typedef */
45692 typedef struct {
45693   __IO uint32_t STATUS;                            /**< ITRC outputs and IN0 to IN15 Status, offset: 0x0 */
45694   __IO uint32_t STATUS1;                           /**< ITRC IN16 to IN47 Status, offset: 0x4 */
45695   __IO uint32_t OUT_SEL[7][2];                     /**< Trigger Source IN0 to IN15 selector, array offset: 0x8, array step: index*0x8, index2*0x4 */
45696        uint8_t RESERVED_0[8];
45697   __IO uint32_t OUT_SEL_1[7][2];                   /**< Trigger Source IN16 to IN31 selector, array offset: 0x48, array step: index*0x8, index2*0x4 */
45698        uint8_t RESERVED_1[8];
45699   __IO uint32_t OUT_SEL_2[7][2];                   /**< Trigger source IN32 to IN47 selector, array offset: 0x88, array step: index*0x8, index2*0x4 */
45700        uint8_t RESERVED_2[48];
45701   __O  uint32_t SW_EVENT0;                         /**< Software event 0, offset: 0xF0 */
45702   __O  uint32_t SW_EVENT1;                         /**< Software event 1, offset: 0xF4 */
45703 } ITRC_Type;
45704 
45705 /* ----------------------------------------------------------------------------
45706    -- ITRC Register Masks
45707    ---------------------------------------------------------------------------- */
45708 
45709 /*!
45710  * @addtogroup ITRC_Register_Masks ITRC Register Masks
45711  * @{
45712  */
45713 
45714 /*! @name STATUS - ITRC outputs and IN0 to IN15 Status */
45715 /*! @{ */
45716 
45717 #define ITRC_STATUS_IN0_STATUS_MASK              (0x1U)
45718 #define ITRC_STATUS_IN0_STATUS_SHIFT             (0U)
45719 /*! IN0_STATUS - GDET0 & 1 interrupt.
45720  *  0b0..Output not triggered.
45721  *  0b1..Output has been triggered.
45722  */
45723 #define ITRC_STATUS_IN0_STATUS(x)                (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN0_STATUS_SHIFT)) & ITRC_STATUS_IN0_STATUS_MASK)
45724 
45725 #define ITRC_STATUS_IN1_STATUS_MASK              (0x2U)
45726 #define ITRC_STATUS_IN1_STATUS_SHIFT             (1U)
45727 /*! IN1_STATUS - TDET tamper output.
45728  *  0b0..Output not triggered.
45729  *  0b1..Output has been triggered.
45730  */
45731 #define ITRC_STATUS_IN1_STATUS(x)                (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN1_STATUS_SHIFT)) & ITRC_STATUS_IN1_STATUS_MASK)
45732 
45733 #define ITRC_STATUS_IN2_STATUS_MASK              (0x4U)
45734 #define ITRC_STATUS_IN2_STATUS_SHIFT             (2U)
45735 /*! IN2_STATUS - Code Watchdog 0 interrupt.
45736  *  0b0..Output not triggered.
45737  *  0b1..Output has been triggered.
45738  */
45739 #define ITRC_STATUS_IN2_STATUS(x)                (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN2_STATUS_SHIFT)) & ITRC_STATUS_IN2_STATUS_MASK)
45740 
45741 #define ITRC_STATUS_IN3_STATUS_MASK              (0x8U)
45742 #define ITRC_STATUS_IN3_STATUS_SHIFT             (3U)
45743 /*! IN3_STATUS - VBAT volt tamper output.
45744  *  0b0..Output not triggered.
45745  *  0b1..Output has been triggered.
45746  */
45747 #define ITRC_STATUS_IN3_STATUS(x)                (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN3_STATUS_SHIFT)) & ITRC_STATUS_IN3_STATUS_MASK)
45748 
45749 #define ITRC_STATUS_IN4_STATUS_MASK              (0x10U)
45750 #define ITRC_STATUS_IN4_STATUS_SHIFT             (4U)
45751 /*! IN4_STATUS - SPC VDD_CORE_LVD detect.
45752  *  0b0..Output not triggered.
45753  *  0b1..Output has been triggered.
45754  */
45755 #define ITRC_STATUS_IN4_STATUS(x)                (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN4_STATUS_SHIFT)) & ITRC_STATUS_IN4_STATUS_MASK)
45756 
45757 #define ITRC_STATUS_IN5_STATUS_MASK              (0x20U)
45758 #define ITRC_STATUS_IN5_STATUS_SHIFT             (5U)
45759 /*! IN5_STATUS - Watch Dog timer event occurred.
45760  *  0b0..Output not triggered.
45761  *  0b1..Output has been triggered.
45762  */
45763 #define ITRC_STATUS_IN5_STATUS(x)                (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN5_STATUS_SHIFT)) & ITRC_STATUS_IN5_STATUS_MASK)
45764 
45765 #define ITRC_STATUS_IN6_STATUS_MASK              (0x40U)
45766 #define ITRC_STATUS_IN6_STATUS_SHIFT             (6U)
45767 /*! IN6_STATUS - Flash ECC mismatch event occurred.
45768  *  0b0..Output not triggered.
45769  *  0b1..Output has been triggered.
45770  */
45771 #define ITRC_STATUS_IN6_STATUS(x)                (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN6_STATUS_SHIFT)) & ITRC_STATUS_IN6_STATUS_MASK)
45772 
45773 #define ITRC_STATUS_IN7_STATUS_MASK              (0x80U)
45774 #define ITRC_STATUS_IN7_STATUS_SHIFT             (7U)
45775 /*! IN7_STATUS - AHB secure bus checkers detected illegal access.
45776  *  0b0..Output not triggered.
45777  *  0b1..Output has been triggered.
45778  */
45779 #define ITRC_STATUS_IN7_STATUS(x)                (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN7_STATUS_SHIFT)) & ITRC_STATUS_IN7_STATUS_MASK)
45780 
45781 #define ITRC_STATUS_IN8_STATUS_MASK              (0x100U)
45782 #define ITRC_STATUS_IN8_STATUS_SHIFT             (8U)
45783 /*! IN8_STATUS - ELS error event occurred.
45784  *  0b0..Output not triggered.
45785  *  0b1..Output has been triggered.
45786  */
45787 #define ITRC_STATUS_IN8_STATUS(x)                (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN8_STATUS_SHIFT)) & ITRC_STATUS_IN8_STATUS_MASK)
45788 
45789 #define ITRC_STATUS_IN9_STATUS_MASK              (0x200U)
45790 #define ITRC_STATUS_IN9_STATUS_SHIFT             (9U)
45791 /*! IN9_STATUS - SPC VDD_CORE glitch detect event occurred.
45792  *  0b0..Output not triggered.
45793  *  0b1..Output has been triggered.
45794  */
45795 #define ITRC_STATUS_IN9_STATUS(x)                (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN9_STATUS_SHIFT)) & ITRC_STATUS_IN9_STATUS_MASK)
45796 
45797 #define ITRC_STATUS_IN10_STATUS_MASK             (0x400U)
45798 #define ITRC_STATUS_IN10_STATUS_SHIFT            (10U)
45799 /*! IN10_STATUS - PKC module detected an error event.
45800  *  0b0..Output not triggered.
45801  *  0b1..Output has been triggered.
45802  */
45803 #define ITRC_STATUS_IN10_STATUS(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN10_STATUS_SHIFT)) & ITRC_STATUS_IN10_STATUS_MASK)
45804 
45805 #define ITRC_STATUS_IN11_STATUS_MASK             (0x800U)
45806 #define ITRC_STATUS_IN11_STATUS_SHIFT            (11U)
45807 /*! IN11_STATUS - Code Watchdog 1 interrupt.
45808  *  0b0..Output not triggered.
45809  *  0b1..Output has been triggered.
45810  */
45811 #define ITRC_STATUS_IN11_STATUS(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN11_STATUS_SHIFT)) & ITRC_STATUS_IN11_STATUS_MASK)
45812 
45813 #define ITRC_STATUS_IN112_STATUS_MASK            (0x1000U)
45814 #define ITRC_STATUS_IN112_STATUS_SHIFT           (12U)
45815 /*! IN112_STATUS - Watchdog 1 timer event interrupt.
45816  *  0b0..Output not triggered.
45817  *  0b1..Output has been triggered.
45818  */
45819 #define ITRC_STATUS_IN112_STATUS(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN112_STATUS_SHIFT)) & ITRC_STATUS_IN112_STATUS_MASK)
45820 
45821 #define ITRC_STATUS_IN113_STATUS_MASK            (0x2000U)
45822 #define ITRC_STATUS_IN113_STATUS_SHIFT           (13U)
45823 /*! IN113_STATUS - FREQME out of range status output.
45824  *  0b0..Output not triggered.
45825  *  0b1..Output has been triggered.
45826  */
45827 #define ITRC_STATUS_IN113_STATUS(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN113_STATUS_SHIFT)) & ITRC_STATUS_IN113_STATUS_MASK)
45828 
45829 #define ITRC_STATUS_IN14_STATUS_MASK             (0x4000U)
45830 #define ITRC_STATUS_IN14_STATUS_SHIFT            (14U)
45831 /*! IN14_STATUS - Software event 0 occurred.
45832  *  0b0..Output not triggered.
45833  *  0b1..Output has been triggered.
45834  */
45835 #define ITRC_STATUS_IN14_STATUS(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN14_STATUS_SHIFT)) & ITRC_STATUS_IN14_STATUS_MASK)
45836 
45837 #define ITRC_STATUS_IN15_STATUS_MASK             (0x8000U)
45838 #define ITRC_STATUS_IN15_STATUS_SHIFT            (15U)
45839 /*! IN15_STATUS - Software event 1 occurred.
45840  *  0b0..Output not triggered.
45841  *  0b1..Output has been triggered.
45842  */
45843 #define ITRC_STATUS_IN15_STATUS(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN15_STATUS_SHIFT)) & ITRC_STATUS_IN15_STATUS_MASK)
45844 
45845 #define ITRC_STATUS_OUT0_STATUS_MASK             (0x10000U)
45846 #define ITRC_STATUS_OUT0_STATUS_SHIFT            (16U)
45847 /*! OUT0_STATUS - ITRC triggered ITRC_IRQ output.
45848  *  0b0..Output not triggered.
45849  *  0b1..Output has been triggered.
45850  */
45851 #define ITRC_STATUS_OUT0_STATUS(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_OUT0_STATUS_SHIFT)) & ITRC_STATUS_OUT0_STATUS_MASK)
45852 
45853 #define ITRC_STATUS_OUT1_STATUS_MASK             (0x20000U)
45854 #define ITRC_STATUS_OUT1_STATUS_SHIFT            (17U)
45855 /*! OUT1_STATUS - ITRC triggered ELS_RESET to clear ELS key store.
45856  *  0b0..Output not triggered.
45857  *  0b1..Output has been triggered.
45858  */
45859 #define ITRC_STATUS_OUT1_STATUS(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_OUT1_STATUS_SHIFT)) & ITRC_STATUS_OUT1_STATUS_MASK)
45860 
45861 #define ITRC_STATUS_OUT2_STATUS_MASK             (0x40000U)
45862 #define ITRC_STATUS_OUT2_STATUS_SHIFT            (18U)
45863 /*! OUT2_STATUS - ITRC triggered PUF_ZEROIZE to clear PUF key store and RAM.
45864  *  0b0..Output not triggered.
45865  *  0b1..Output has been triggered.
45866  */
45867 #define ITRC_STATUS_OUT2_STATUS(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_OUT2_STATUS_SHIFT)) & ITRC_STATUS_OUT2_STATUS_MASK)
45868 
45869 #define ITRC_STATUS_OUT3_STATUS_MASK             (0x80000U)
45870 #define ITRC_STATUS_OUT3_STATUS_SHIFT            (19U)
45871 /*! OUT3_STATUS - ITRC triggered RAM_ZEROIZE.
45872  *  0b0..Output not triggered.
45873  *  0b1..Output has been triggered.
45874  */
45875 #define ITRC_STATUS_OUT3_STATUS(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_OUT3_STATUS_SHIFT)) & ITRC_STATUS_OUT3_STATUS_MASK)
45876 
45877 #define ITRC_STATUS_OUT4_STATUS_MASK             (0x100000U)
45878 #define ITRC_STATUS_OUT4_STATUS_SHIFT            (20U)
45879 /*! OUT4_STATUS - ITRC triggered CHIP_RESET to reset the chip after all other response process finished.
45880  *  0b0..Output not triggered.
45881  *  0b1..Output has been triggered.
45882  */
45883 #define ITRC_STATUS_OUT4_STATUS(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_OUT4_STATUS_SHIFT)) & ITRC_STATUS_OUT4_STATUS_MASK)
45884 
45885 #define ITRC_STATUS_OUT5_STATUS_MASK             (0x200000U)
45886 #define ITRC_STATUS_OUT5_STATUS_SHIFT            (21U)
45887 /*! OUT5_STATUS - ITRC triggered TMPR_OUT0 internal signal connected to various on-chip multiplexers.
45888  *  0b0..Output not triggered.
45889  *  0b1..Output has been triggered.
45890  */
45891 #define ITRC_STATUS_OUT5_STATUS(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_OUT5_STATUS_SHIFT)) & ITRC_STATUS_OUT5_STATUS_MASK)
45892 
45893 #define ITRC_STATUS_OUT6_STATUS_MASK             (0x400000U)
45894 #define ITRC_STATUS_OUT6_STATUS_SHIFT            (22U)
45895 /*! OUT6_STATUS - ITRC triggered TMPR_OUT1 internal signal connected to various on-chip multiplexers.
45896  *  0b0..Output not triggered.
45897  *  0b1..Output has been triggered.
45898  */
45899 #define ITRC_STATUS_OUT6_STATUS(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_OUT6_STATUS_SHIFT)) & ITRC_STATUS_OUT6_STATUS_MASK)
45900 /*! @} */
45901 
45902 /*! @name STATUS1 - ITRC IN16 to IN47 Status */
45903 /*! @{ */
45904 
45905 #define ITRC_STATUS1_IN16_STATUS_MASK            (0x1U)
45906 #define ITRC_STATUS1_IN16_STATUS_SHIFT           (0U)
45907 /*! IN16_STATUS - SSPC VDD_SYS_LVD detect event occurred.
45908  *  0b0..Output not triggered.
45909  *  0b1..Output has been triggered.
45910  */
45911 #define ITRC_STATUS1_IN16_STATUS(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN16_STATUS_SHIFT)) & ITRC_STATUS1_IN16_STATUS_MASK)
45912 
45913 #define ITRC_STATUS1_IN17_STATUS_MASK            (0x2U)
45914 #define ITRC_STATUS1_IN17_STATUS_SHIFT           (1U)
45915 /*! IN17_STATUS - SPC VDD_IO_LVD detect event occurred.
45916  *  0b0..Output not triggered.
45917  *  0b1..Output has been triggered.
45918  */
45919 #define ITRC_STATUS1_IN17_STATUS(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN17_STATUS_SHIFT)) & ITRC_STATUS1_IN17_STATUS_MASK)
45920 
45921 #define ITRC_STATUS1_IN18_STATUS_MASK            (0x4U)
45922 #define ITRC_STATUS1_IN18_STATUS_SHIFT           (2U)
45923 /*! IN18_STATUS - Reserved
45924  *  0b0..Output not triggered.
45925  *  0b1..Output has been triggered.
45926  */
45927 #define ITRC_STATUS1_IN18_STATUS(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN18_STATUS_SHIFT)) & ITRC_STATUS1_IN18_STATUS_MASK)
45928 
45929 #define ITRC_STATUS1_IN19_STATUS_MASK            (0x8U)
45930 #define ITRC_STATUS1_IN19_STATUS_SHIFT           (3U)
45931 /*! IN19_STATUS - Reserved
45932  *  0b0..Output not triggered.
45933  *  0b1..Output has been triggered.
45934  */
45935 #define ITRC_STATUS1_IN19_STATUS(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN19_STATUS_SHIFT)) & ITRC_STATUS1_IN19_STATUS_MASK)
45936 
45937 #define ITRC_STATUS1_IN20_STATUS_MASK            (0x10U)
45938 #define ITRC_STATUS1_IN20_STATUS_SHIFT           (4U)
45939 /*! IN20_STATUS - VBAT clock tamper output event occurred.
45940  *  0b0..Output not triggered.
45941  *  0b1..Output has been triggered.
45942  */
45943 #define ITRC_STATUS1_IN20_STATUS(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN20_STATUS_SHIFT)) & ITRC_STATUS1_IN20_STATUS_MASK)
45944 
45945 #define ITRC_STATUS1_IN24_21_STATUS_MASK         (0x1E0U)
45946 #define ITRC_STATUS1_IN24_21_STATUS_SHIFT        (5U)
45947 /*! IN24_21_STATUS - INTM interrupt monitor error 3~0 event occurred.
45948  *  0b0000..Output not triggered.
45949  *  0b0001..Output has been triggered.
45950  */
45951 #define ITRC_STATUS1_IN24_21_STATUS(x)           (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN24_21_STATUS_SHIFT)) & ITRC_STATUS1_IN24_21_STATUS_MASK)
45952 
45953 #define ITRC_STATUS1_IN32_25_STATUS_MASK         (0x1FE00U)
45954 #define ITRC_STATUS1_IN32_25_STATUS_SHIFT        (9U)
45955 /*! IN32_25_STATUS - MSF SOCTRIM 7~0 ECC error event occurred.
45956  *  0b00000000..Output not triggered.
45957  *  0b00000001..Output has been triggered.
45958  */
45959 #define ITRC_STATUS1_IN32_25_STATUS(x)           (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN32_25_STATUS_SHIFT)) & ITRC_STATUS1_IN32_25_STATUS_MASK)
45960 
45961 #define ITRC_STATUS1_IN33_STATUS_MASK            (0x20000U)
45962 #define ITRC_STATUS1_IN33_STATUS_SHIFT           (17U)
45963 /*! IN33_STATUS - GDET0/1 SFR error event occurred.
45964  *  0b0..Output not triggered.
45965  *  0b1..Output has been triggered.
45966  */
45967 #define ITRC_STATUS1_IN33_STATUS(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN33_STATUS_SHIFT)) & ITRC_STATUS1_IN33_STATUS_MASK)
45968 
45969 #define ITRC_STATUS1_IN34_STATUS_MASK            (0x40000U)
45970 #define ITRC_STATUS1_IN34_STATUS_SHIFT           (18U)
45971 /*! IN34_STATUS - SPC VDD_CORE high voltage detect event occurred.
45972  *  0b0..Output not triggered.
45973  *  0b1..Output has been triggered.
45974  */
45975 #define ITRC_STATUS1_IN34_STATUS(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN34_STATUS_SHIFT)) & ITRC_STATUS1_IN34_STATUS_MASK)
45976 
45977 #define ITRC_STATUS1_IN35_STATUS_MASK            (0x80000U)
45978 #define ITRC_STATUS1_IN35_STATUS_SHIFT           (19U)
45979 /*! IN35_STATUS - SPC VDD_SYS_HVD high voltage detect event occurred.
45980  *  0b0..Output not triggered.
45981  *  0b1..Output has been triggered.
45982  */
45983 #define ITRC_STATUS1_IN35_STATUS(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN35_STATUS_SHIFT)) & ITRC_STATUS1_IN35_STATUS_MASK)
45984 
45985 #define ITRC_STATUS1_IN36_STATUS_MASK            (0x100000U)
45986 #define ITRC_STATUS1_IN36_STATUS_SHIFT           (20U)
45987 /*! IN36_STATUS - SPC VDD_IO high voltage detect event occurred.
45988  *  0b0..Output not triggered.
45989  *  0b1..Output has been triggered.
45990  */
45991 #define ITRC_STATUS1_IN36_STATUS(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN36_STATUS_SHIFT)) & ITRC_STATUS1_IN36_STATUS_MASK)
45992 
45993 #define ITRC_STATUS1_IN37_STATUS_MASK            (0x200000U)
45994 #define ITRC_STATUS1_IN37_STATUS_SHIFT           (21U)
45995 /*! IN37_STATUS - FLEXSPI GCM error event occurred.
45996  *  0b0..Output not triggered.
45997  *  0b1..Output has been triggered.
45998  */
45999 #define ITRC_STATUS1_IN37_STATUS(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN37_STATUS_SHIFT)) & ITRC_STATUS1_IN37_STATUS_MASK)
46000 
46001 #define ITRC_STATUS1_IN46_STATUS_MASK            (0x40000000U)
46002 #define ITRC_STATUS1_IN46_STATUS_SHIFT           (30U)
46003 /*! IN46_STATUS - SM3 SGI error event occurred.
46004  *  0b0..Output not triggered.
46005  *  0b1..Output has been triggered.
46006  */
46007 #define ITRC_STATUS1_IN46_STATUS(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN46_STATUS_SHIFT)) & ITRC_STATUS1_IN46_STATUS_MASK)
46008 
46009 #define ITRC_STATUS1_IN47_STATUS_MASK            (0x80000000U)
46010 #define ITRC_STATUS1_IN47_STATUS_SHIFT           (31U)
46011 /*! IN47_STATUS - TRNG HW error event occurred.
46012  *  0b0..Output not triggered.
46013  *  0b1..Output has been triggered.
46014  */
46015 #define ITRC_STATUS1_IN47_STATUS(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN47_STATUS_SHIFT)) & ITRC_STATUS1_IN47_STATUS_MASK)
46016 /*! @} */
46017 
46018 /*! @name OUTX_SEL_OUTX_SELY_OUT_SEL - Trigger Source IN0 to IN15 selector */
46019 /*! @{ */
46020 
46021 #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN0_SELn_MASK (0x3U)
46022 #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN0_SELn_SHIFT (0U)
46023 /*! IN0_SELn - Selects digital glitch detector as a trigger source. */
46024 #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN0_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN0_SELn_SHIFT)) & ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN0_SELn_MASK)
46025 
46026 #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN1_SELn_MASK (0xCU)
46027 #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN1_SELn_SHIFT (2U)
46028 /*! IN1_SELn - Selects TDET event as a trigger source. */
46029 #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN1_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN1_SELn_SHIFT)) & ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN1_SELn_MASK)
46030 
46031 #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN2_SELn_MASK (0x30U)
46032 #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN2_SELn_SHIFT (4U)
46033 /*! IN2_SELn - Selects Code Watchdog 0 event as a trigger source. */
46034 #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN2_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN2_SELn_SHIFT)) & ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN2_SELn_MASK)
46035 
46036 #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN3_SELn_MASK (0xC0U)
46037 #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN3_SELn_SHIFT (6U)
46038 /*! IN3_SELn - Selects VBAT voltage tamper event as a trigger source. */
46039 #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN3_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN3_SELn_SHIFT)) & ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN3_SELn_MASK)
46040 
46041 #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN4_SELn_MASK (0x300U)
46042 #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN4_SELn_SHIFT (8U)
46043 /*! IN4_SELn - Selects low-voltage event on VDD_CORE rail as a trigger source. */
46044 #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN4_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN4_SELn_SHIFT)) & ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN4_SELn_MASK)
46045 
46046 #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN5_SELn_MASK (0xC00U)
46047 #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN5_SELn_SHIFT (10U)
46048 /*! IN5_SELn - Selects Watchdog 0 timer event as a trigger source. */
46049 #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN5_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN5_SELn_SHIFT)) & ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN5_SELn_MASK)
46050 
46051 #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN6_SELn_MASK (0x3000U)
46052 #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN6_SELn_SHIFT (12U)
46053 /*! IN6_SELn - Selects Flash ECC mismatch event as a trigger source. */
46054 #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN6_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN6_SELn_SHIFT)) & ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN6_SELn_MASK)
46055 
46056 #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN7_SELn_MASK (0xC000U)
46057 #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN7_SELn_SHIFT (14U)
46058 /*! IN7_SELn - Selects AHB secure bus or MBC bus illegal access event as a trigger source. */
46059 #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN7_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN7_SELn_SHIFT)) & ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN7_SELn_MASK)
46060 
46061 #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN8_SELn_MASK (0x30000U)
46062 #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN8_SELn_SHIFT (16U)
46063 /*! IN8_SELn - Selects ELS error event as a trigger source. */
46064 #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN8_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN8_SELn_SHIFT)) & ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN8_SELn_MASK)
46065 
46066 #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN9_SELn_MASK (0xC0000U)
46067 #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN9_SELn_SHIFT (18U)
46068 /*! IN9_SELn - Selects SPC VDD_CORE glitch detector as a trigger source. */
46069 #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN9_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN9_SELn_SHIFT)) & ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN9_SELn_MASK)
46070 
46071 #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN10_SELn_MASK (0x300000U)
46072 #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN10_SELn_SHIFT (20U)
46073 /*! IN10_SELn - Selects PKC error event as a trigger source. */
46074 #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN10_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN10_SELn_SHIFT)) & ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN10_SELn_MASK)
46075 
46076 #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN11_SELn_MASK (0xC00000U)
46077 #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN11_SELn_SHIFT (22U)
46078 /*! IN11_SELn - Selects Code Watchdog 1 event as a trigger source. */
46079 #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN11_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN11_SELn_SHIFT)) & ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN11_SELn_MASK)
46080 
46081 #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN12_SELn_MASK (0x3000000U)
46082 #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN12_SELn_SHIFT (24U)
46083 /*! IN12_SELn - Selects Watchdog 1 timer event as a trigger source. */
46084 #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN12_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN12_SELn_SHIFT)) & ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN12_SELn_MASK)
46085 
46086 #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN13_SELn_MASK (0xC000000U)
46087 #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN13_SELn_SHIFT (26U)
46088 /*! IN13_SELn - Selects FREQME out of range status output as a trigger source. */
46089 #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN13_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN13_SELn_SHIFT)) & ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN13_SELn_MASK)
46090 
46091 #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN14_SELn_MASK (0x30000000U)
46092 #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN14_SELn_SHIFT (28U)
46093 /*! IN14_SELn - Selects software event 0 as a trigger source. */
46094 #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN14_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN14_SELn_SHIFT)) & ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN14_SELn_MASK)
46095 
46096 #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN15_SELn_MASK (0xC0000000U)
46097 #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN15_SELn_SHIFT (30U)
46098 /*! IN15_SELn - Selects software event 1 as a trigger source. */
46099 #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN15_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN15_SELn_SHIFT)) & ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN15_SELn_MASK)
46100 /*! @} */
46101 
46102 /* The count of ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL */
46103 #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_COUNT    (7U)
46104 
46105 /* The count of ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL */
46106 #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_COUNT2   (2U)
46107 
46108 /*! @name OUTX_SEL_1_OUTX_SELY_OUT_SEL_1 - Trigger Source IN16 to IN31 selector */
46109 /*! @{ */
46110 
46111 #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN16_SELn_MASK (0x3U)
46112 #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN16_SELn_SHIFT (0U)
46113 /*! IN16_SELn - Selects SPC VDD_SYS_LVD detect as a trigger source. */
46114 #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN16_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN16_SELn_SHIFT)) & ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN16_SELn_MASK)
46115 
46116 #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN17_SELn_MASK (0xCU)
46117 #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN17_SELn_SHIFT (2U)
46118 /*! IN17_SELn - Selects SPC VDD_IO_LVD detect as a trigger source. */
46119 #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN17_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN17_SELn_SHIFT)) & ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN17_SELn_MASK)
46120 
46121 #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN18_SELn_MASK (0x30U)
46122 #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN18_SELn_SHIFT (4U)
46123 /*! IN18_SELn - Reserved. */
46124 #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN18_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN18_SELn_SHIFT)) & ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN18_SELn_MASK)
46125 
46126 #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN19_SELn_MASK (0xC0U)
46127 #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN19_SELn_SHIFT (6U)
46128 /*! IN19_SELn - Selects VBAT temperature tamper output event as a trigger source. */
46129 #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN19_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN19_SELn_SHIFT)) & ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN19_SELn_MASK)
46130 
46131 #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN20_SELn_MASK (0x300U)
46132 #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN20_SELn_SHIFT (8U)
46133 /*! IN20_SELn - Selects VBAT clock tamper output event as a trigger source. */
46134 #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN20_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN20_SELn_SHIFT)) & ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN20_SELn_MASK)
46135 
46136 #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN21_SELn_MASK (0xC00U)
46137 #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN21_SELn_SHIFT (10U)
46138 /*! IN21_SELn - Selects INTM interrupt monitor error 0 event as a trigger source. */
46139 #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN21_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN21_SELn_SHIFT)) & ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN21_SELn_MASK)
46140 
46141 #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN22_SELn_MASK (0x3000U)
46142 #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN22_SELn_SHIFT (12U)
46143 /*! IN22_SELn - Selects INTM interrupt monitor error 1 event as a trigger source. */
46144 #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN22_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN22_SELn_SHIFT)) & ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN22_SELn_MASK)
46145 
46146 #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN23_SELn_MASK (0xC000U)
46147 #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN23_SELn_SHIFT (14U)
46148 /*! IN23_SELn - Selects INTM interrupt monitor error 2 event as a trigger source. */
46149 #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN23_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN23_SELn_SHIFT)) & ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN23_SELn_MASK)
46150 
46151 #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN24_SELn_MASK (0x30000U)
46152 #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN24_SELn_SHIFT (16U)
46153 /*! IN24_SELn - Selects INTM interrupt monitor error 3 event as a trigger source. */
46154 #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN24_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN24_SELn_SHIFT)) & ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN24_SELn_MASK)
46155 
46156 #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN25_SELn_MASK (0xC0000U)
46157 #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN25_SELn_SHIFT (18U)
46158 /*! IN25_SELn - Selects MSF SOCTRIM 0 ECC error event as a trigger source. */
46159 #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN25_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN25_SELn_SHIFT)) & ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN25_SELn_MASK)
46160 
46161 #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN26_SELn_MASK (0x300000U)
46162 #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN26_SELn_SHIFT (20U)
46163 /*! IN26_SELn - Selects MSF SOCTRIM 1 ECC error event as a trigger source. */
46164 #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN26_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN26_SELn_SHIFT)) & ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN26_SELn_MASK)
46165 
46166 #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN27_SELn_MASK (0xC00000U)
46167 #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN27_SELn_SHIFT (22U)
46168 /*! IN27_SELn - Selects MSF SOCTRIM 2 ECC error event as a trigger source. */
46169 #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN27_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN27_SELn_SHIFT)) & ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN27_SELn_MASK)
46170 
46171 #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN28_SELn_MASK (0x3000000U)
46172 #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN28_SELn_SHIFT (24U)
46173 /*! IN28_SELn - Selects MSF SOCTRIM 3 ECC error event as a trigger source. */
46174 #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN28_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN28_SELn_SHIFT)) & ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN28_SELn_MASK)
46175 
46176 #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN29_SELn_MASK (0xC000000U)
46177 #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN29_SELn_SHIFT (26U)
46178 /*! IN29_SELn - Selects MSF SOCTRIM 4 ECC error event as a trigger source. */
46179 #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN29_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN29_SELn_SHIFT)) & ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN29_SELn_MASK)
46180 
46181 #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN30_SELn_MASK (0x30000000U)
46182 #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN30_SELn_SHIFT (28U)
46183 /*! IN30_SELn - Selects MSF SOCTRIM 5 ECC error event as a trigger source. */
46184 #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN30_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN30_SELn_SHIFT)) & ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN30_SELn_MASK)
46185 
46186 #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN31_SELn_MASK (0xC0000000U)
46187 #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN31_SELn_SHIFT (30U)
46188 /*! IN31_SELn - Selects MSF SOCTRIM 6 ECC error event as a trigger source. */
46189 #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN31_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN31_SELn_SHIFT)) & ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN31_SELn_MASK)
46190 /*! @} */
46191 
46192 /* The count of ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1 */
46193 #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_COUNT (7U)
46194 
46195 /* The count of ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1 */
46196 #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_COUNT2 (2U)
46197 
46198 /*! @name OUTX_SEL_2_OUTX_SELY_OUT_SEL_2 - Trigger source IN32 to IN47 selector */
46199 /*! @{ */
46200 
46201 #define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN32_SELn_MASK (0x3U)
46202 #define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN32_SELn_SHIFT (0U)
46203 /*! IN32_SELn - Selects MSF SOCTRIM 7 ECC error event as a trigger source. */
46204 #define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN32_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN32_SELn_SHIFT)) & ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN32_SELn_MASK)
46205 
46206 #define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN33_SELn_MASK (0xCU)
46207 #define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN33_SELn_SHIFT (2U)
46208 /*! IN33_SELn - Selects GDET0 & 1 SFR error detect as a trigger source. */
46209 #define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN33_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN33_SELn_SHIFT)) & ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN33_SELn_MASK)
46210 
46211 #define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN34_SELn_MASK (0x30U)
46212 #define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN34_SELn_SHIFT (4U)
46213 /*! IN34_SELn - Selects SPC VDD_CORE_HVD as a trigger source. */
46214 #define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN34_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN34_SELn_SHIFT)) & ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN34_SELn_MASK)
46215 
46216 #define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN35_SELn_MASK (0xC0U)
46217 #define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN35_SELn_SHIFT (6U)
46218 /*! IN35_SELn - Selects VDD_SYS_HVD as a trigger source. */
46219 #define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN35_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN35_SELn_SHIFT)) & ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN35_SELn_MASK)
46220 
46221 #define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN36_SELn_MASK (0x300U)
46222 #define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN36_SELn_SHIFT (8U)
46223 /*! IN36_SELn - Selects VDD_IO_HVD as a trigger source. */
46224 #define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN36_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN36_SELn_SHIFT)) & ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN36_SELn_MASK)
46225 
46226 #define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN37_SELn_MASK (0xC00U)
46227 #define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN37_SELn_SHIFT (10U)
46228 /*! IN37_SELn - Selects FLEXSPI GCM error as a trigger source. */
46229 #define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN37_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN37_SELn_SHIFT)) & ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN37_SELn_MASK)
46230 
46231 #define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN46_SELn_MASK (0x30000000U)
46232 #define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN46_SELn_SHIFT (28U)
46233 /*! IN46_SELn - Selects SM3 SGI error as a trigger source. */
46234 #define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN46_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN46_SELn_SHIFT)) & ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN46_SELn_MASK)
46235 
46236 #define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN47_SELn_MASK (0xC0000000U)
46237 #define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN47_SELn_SHIFT (30U)
46238 /*! IN47_SELn - Selects TRNG HW Error as a trigger source. */
46239 #define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN47_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN47_SELn_SHIFT)) & ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN47_SELn_MASK)
46240 /*! @} */
46241 
46242 /* The count of ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2 */
46243 #define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_COUNT (7U)
46244 
46245 /* The count of ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2 */
46246 #define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_COUNT2 (2U)
46247 
46248 /*! @name SW_EVENT0 - Software event 0 */
46249 /*! @{ */
46250 
46251 #define ITRC_SW_EVENT0_TRIGGER_SW_EVENT_0_MASK   (0xFFFFFFFFU)
46252 #define ITRC_SW_EVENT0_TRIGGER_SW_EVENT_0_SHIFT  (0U)
46253 /*! TRIGGER_SW_EVENT_0 - Trigger software event 0. */
46254 #define ITRC_SW_EVENT0_TRIGGER_SW_EVENT_0(x)     (((uint32_t)(((uint32_t)(x)) << ITRC_SW_EVENT0_TRIGGER_SW_EVENT_0_SHIFT)) & ITRC_SW_EVENT0_TRIGGER_SW_EVENT_0_MASK)
46255 /*! @} */
46256 
46257 /*! @name SW_EVENT1 - Software event 1 */
46258 /*! @{ */
46259 
46260 #define ITRC_SW_EVENT1_TRIGGER_SW_EVENT_1_MASK   (0xFFFFFFFFU)
46261 #define ITRC_SW_EVENT1_TRIGGER_SW_EVENT_1_SHIFT  (0U)
46262 /*! TRIGGER_SW_EVENT_1 - Trigger software event 1. */
46263 #define ITRC_SW_EVENT1_TRIGGER_SW_EVENT_1(x)     (((uint32_t)(((uint32_t)(x)) << ITRC_SW_EVENT1_TRIGGER_SW_EVENT_1_SHIFT)) & ITRC_SW_EVENT1_TRIGGER_SW_EVENT_1_MASK)
46264 /*! @} */
46265 
46266 
46267 /*!
46268  * @}
46269  */ /* end of group ITRC_Register_Masks */
46270 
46271 
46272 /* ITRC - Peripheral instance base addresses */
46273 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
46274   /** Peripheral ITRC0 base address */
46275   #define ITRC0_BASE                               (0x50026000u)
46276   /** Peripheral ITRC0 base address */
46277   #define ITRC0_BASE_NS                            (0x40026000u)
46278   /** Peripheral ITRC0 base pointer */
46279   #define ITRC0                                    ((ITRC_Type *)ITRC0_BASE)
46280   /** Peripheral ITRC0 base pointer */
46281   #define ITRC0_NS                                 ((ITRC_Type *)ITRC0_BASE_NS)
46282   /** Array initializer of ITRC peripheral base addresses */
46283   #define ITRC_BASE_ADDRS                          { ITRC0_BASE }
46284   /** Array initializer of ITRC peripheral base pointers */
46285   #define ITRC_BASE_PTRS                           { ITRC0 }
46286   /** Array initializer of ITRC peripheral base addresses */
46287   #define ITRC_BASE_ADDRS_NS                       { ITRC0_BASE_NS }
46288   /** Array initializer of ITRC peripheral base pointers */
46289   #define ITRC_BASE_PTRS_NS                        { ITRC0_NS }
46290 #else
46291   /** Peripheral ITRC0 base address */
46292   #define ITRC0_BASE                               (0x40026000u)
46293   /** Peripheral ITRC0 base pointer */
46294   #define ITRC0                                    ((ITRC_Type *)ITRC0_BASE)
46295   /** Array initializer of ITRC peripheral base addresses */
46296   #define ITRC_BASE_ADDRS                          { ITRC0_BASE }
46297   /** Array initializer of ITRC peripheral base pointers */
46298   #define ITRC_BASE_PTRS                           { ITRC0 }
46299 #endif
46300 
46301 /*!
46302  * @}
46303  */ /* end of group ITRC_Peripheral_Access_Layer */
46304 
46305 
46306 /* ----------------------------------------------------------------------------
46307    -- LPCMP Peripheral Access Layer
46308    ---------------------------------------------------------------------------- */
46309 
46310 /*!
46311  * @addtogroup LPCMP_Peripheral_Access_Layer LPCMP Peripheral Access Layer
46312  * @{
46313  */
46314 
46315 /** LPCMP - Register Layout Typedef */
46316 typedef struct {
46317   __I  uint32_t VERID;                             /**< Version ID, offset: 0x0 */
46318   __I  uint32_t PARAM;                             /**< Parameter, offset: 0x4 */
46319   __IO uint32_t CCR0;                              /**< Comparator Control Register 0, offset: 0x8 */
46320   __IO uint32_t CCR1;                              /**< Comparator Control Register 1, offset: 0xC */
46321   __IO uint32_t CCR2;                              /**< Comparator Control Register 2, offset: 0x10 */
46322        uint8_t RESERVED_0[4];
46323   __IO uint32_t DCR;                               /**< DAC Control, offset: 0x18 */
46324   __IO uint32_t IER;                               /**< Interrupt Enable, offset: 0x1C */
46325   __IO uint32_t CSR;                               /**< Comparator Status, offset: 0x20 */
46326   __IO uint32_t RRCR0;                             /**< Round Robin Control Register 0, offset: 0x24 */
46327   __IO uint32_t RRCR1;                             /**< Round Robin Control Register 1, offset: 0x28 */
46328   __IO uint32_t RRCSR;                             /**< Round Robin Control and Status, offset: 0x2C */
46329   __IO uint32_t RRSR;                              /**< Round Robin Status, offset: 0x30 */
46330        uint8_t RESERVED_1[4];
46331   __IO uint32_t RRCR2;                             /**< Round Robin Control Register 2, offset: 0x38 */
46332 } LPCMP_Type;
46333 
46334 /* ----------------------------------------------------------------------------
46335    -- LPCMP Register Masks
46336    ---------------------------------------------------------------------------- */
46337 
46338 /*!
46339  * @addtogroup LPCMP_Register_Masks LPCMP Register Masks
46340  * @{
46341  */
46342 
46343 /*! @name VERID - Version ID */
46344 /*! @{ */
46345 
46346 #define LPCMP_VERID_FEATURE_MASK                 (0xFFFFU)
46347 #define LPCMP_VERID_FEATURE_SHIFT                (0U)
46348 /*! FEATURE - Feature Specification Number
46349  *  0b0000000000000001..Round robin feature
46350  */
46351 #define LPCMP_VERID_FEATURE(x)                   (((uint32_t)(((uint32_t)(x)) << LPCMP_VERID_FEATURE_SHIFT)) & LPCMP_VERID_FEATURE_MASK)
46352 
46353 #define LPCMP_VERID_MINOR_MASK                   (0xFF0000U)
46354 #define LPCMP_VERID_MINOR_SHIFT                  (16U)
46355 /*! MINOR - Minor Version Number */
46356 #define LPCMP_VERID_MINOR(x)                     (((uint32_t)(((uint32_t)(x)) << LPCMP_VERID_MINOR_SHIFT)) & LPCMP_VERID_MINOR_MASK)
46357 
46358 #define LPCMP_VERID_MAJOR_MASK                   (0xFF000000U)
46359 #define LPCMP_VERID_MAJOR_SHIFT                  (24U)
46360 /*! MAJOR - Major Version Number */
46361 #define LPCMP_VERID_MAJOR(x)                     (((uint32_t)(((uint32_t)(x)) << LPCMP_VERID_MAJOR_SHIFT)) & LPCMP_VERID_MAJOR_MASK)
46362 /*! @} */
46363 
46364 /*! @name PARAM - Parameter */
46365 /*! @{ */
46366 
46367 #define LPCMP_PARAM_DAC_RES_MASK                 (0xFU)
46368 #define LPCMP_PARAM_DAC_RES_SHIFT                (0U)
46369 /*! DAC_RES - DAC Resolution
46370  *  0b0000..4-bit DAC
46371  *  0b0001..6-bit DAC
46372  *  0b0010..8-bit DAC
46373  *  0b0011..10-bit DAC
46374  *  0b0100..12-bit DAC
46375  *  0b0101..14-bit DAC
46376  *  0b0110..16-bit DAC
46377  */
46378 #define LPCMP_PARAM_DAC_RES(x)                   (((uint32_t)(((uint32_t)(x)) << LPCMP_PARAM_DAC_RES_SHIFT)) & LPCMP_PARAM_DAC_RES_MASK)
46379 /*! @} */
46380 
46381 /*! @name CCR0 - Comparator Control Register 0 */
46382 /*! @{ */
46383 
46384 #define LPCMP_CCR0_CMP_EN_MASK                   (0x1U)
46385 #define LPCMP_CCR0_CMP_EN_SHIFT                  (0U)
46386 /*! CMP_EN - Comparator Enable
46387  *  0b0..Disable (The analog logic remains off and consumes no power.)
46388  *  0b1..Enable
46389  */
46390 #define LPCMP_CCR0_CMP_EN(x)                     (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR0_CMP_EN_SHIFT)) & LPCMP_CCR0_CMP_EN_MASK)
46391 /*! @} */
46392 
46393 /*! @name CCR1 - Comparator Control Register 1 */
46394 /*! @{ */
46395 
46396 #define LPCMP_CCR1_WINDOW_EN_MASK                (0x1U)
46397 #define LPCMP_CCR1_WINDOW_EN_SHIFT               (0U)
46398 /*! WINDOW_EN - Windowing Enable
46399  *  0b0..Disable
46400  *  0b1..Enable
46401  */
46402 #define LPCMP_CCR1_WINDOW_EN(x)                  (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_WINDOW_EN_SHIFT)) & LPCMP_CCR1_WINDOW_EN_MASK)
46403 
46404 #define LPCMP_CCR1_SAMPLE_EN_MASK                (0x2U)
46405 #define LPCMP_CCR1_SAMPLE_EN_SHIFT               (1U)
46406 /*! SAMPLE_EN - Sampling Enable
46407  *  0b0..Disable
46408  *  0b1..Enable
46409  */
46410 #define LPCMP_CCR1_SAMPLE_EN(x)                  (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_SAMPLE_EN_SHIFT)) & LPCMP_CCR1_SAMPLE_EN_MASK)
46411 
46412 #define LPCMP_CCR1_DMA_EN_MASK                   (0x4U)
46413 #define LPCMP_CCR1_DMA_EN_SHIFT                  (2U)
46414 /*! DMA_EN - DMA Enable
46415  *  0b0..Disable
46416  *  0b1..Enable
46417  */
46418 #define LPCMP_CCR1_DMA_EN(x)                     (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_DMA_EN_SHIFT)) & LPCMP_CCR1_DMA_EN_MASK)
46419 
46420 #define LPCMP_CCR1_COUT_INV_MASK                 (0x8U)
46421 #define LPCMP_CCR1_COUT_INV_SHIFT                (3U)
46422 /*! COUT_INV - Comparator Invert
46423  *  0b0..Do not invert
46424  *  0b1..Invert
46425  */
46426 #define LPCMP_CCR1_COUT_INV(x)                   (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_COUT_INV_SHIFT)) & LPCMP_CCR1_COUT_INV_MASK)
46427 
46428 #define LPCMP_CCR1_COUT_SEL_MASK                 (0x10U)
46429 #define LPCMP_CCR1_COUT_SEL_SHIFT                (4U)
46430 /*! COUT_SEL - Comparator Output Select
46431  *  0b0..Use COUT (filtered)
46432  *  0b1..Use COUTA (unfiltered)
46433  */
46434 #define LPCMP_CCR1_COUT_SEL(x)                   (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_COUT_SEL_SHIFT)) & LPCMP_CCR1_COUT_SEL_MASK)
46435 
46436 #define LPCMP_CCR1_COUT_PEN_MASK                 (0x20U)
46437 #define LPCMP_CCR1_COUT_PEN_SHIFT                (5U)
46438 /*! COUT_PEN - Comparator Output Pin Enable
46439  *  0b0..Not available
46440  *  0b1..Available
46441  */
46442 #define LPCMP_CCR1_COUT_PEN(x)                   (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_COUT_PEN_SHIFT)) & LPCMP_CCR1_COUT_PEN_MASK)
46443 
46444 #define LPCMP_CCR1_COUTA_OWEN_MASK               (0x40U)
46445 #define LPCMP_CCR1_COUTA_OWEN_SHIFT              (6U)
46446 /*! COUTA_OWEN - COUTA_OW Enable
46447  *  0b0..COUTA holds the last sampled value.
46448  *  0b1..Enables the COUTA signal value to be defined by COUTA_OW.
46449  */
46450 #define LPCMP_CCR1_COUTA_OWEN(x)                 (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_COUTA_OWEN_SHIFT)) & LPCMP_CCR1_COUTA_OWEN_MASK)
46451 
46452 #define LPCMP_CCR1_COUTA_OW_MASK                 (0x80U)
46453 #define LPCMP_CCR1_COUTA_OW_SHIFT                (7U)
46454 /*! COUTA_OW - COUTA Output Level for Closed Window
46455  *  0b0..COUTA is 0
46456  *  0b1..COUTA is 1
46457  */
46458 #define LPCMP_CCR1_COUTA_OW(x)                   (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_COUTA_OW_SHIFT)) & LPCMP_CCR1_COUTA_OW_MASK)
46459 
46460 #define LPCMP_CCR1_WINDOW_INV_MASK               (0x100U)
46461 #define LPCMP_CCR1_WINDOW_INV_SHIFT              (8U)
46462 /*! WINDOW_INV - WINDOW/SAMPLE Signal Invert
46463  *  0b0..Do not invert
46464  *  0b1..Invert
46465  */
46466 #define LPCMP_CCR1_WINDOW_INV(x)                 (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_WINDOW_INV_SHIFT)) & LPCMP_CCR1_WINDOW_INV_MASK)
46467 
46468 #define LPCMP_CCR1_WINDOW_CLS_MASK               (0x200U)
46469 #define LPCMP_CCR1_WINDOW_CLS_SHIFT              (9U)
46470 /*! WINDOW_CLS - COUT Event Window Close
46471  *  0b0..COUT event cannot close the window
46472  *  0b1..COUT event can close the window
46473  */
46474 #define LPCMP_CCR1_WINDOW_CLS(x)                 (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_WINDOW_CLS_SHIFT)) & LPCMP_CCR1_WINDOW_CLS_MASK)
46475 
46476 #define LPCMP_CCR1_EVT_SEL_MASK                  (0xC00U)
46477 #define LPCMP_CCR1_EVT_SEL_SHIFT                 (10U)
46478 /*! EVT_SEL - COUT Event Select
46479  *  0b00..Rising edge
46480  *  0b01..Falling edge
46481  *  0b1x..Both edges
46482  */
46483 #define LPCMP_CCR1_EVT_SEL(x)                    (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_EVT_SEL_SHIFT)) & LPCMP_CCR1_EVT_SEL_MASK)
46484 
46485 #define LPCMP_CCR1_FUNC_CLK_SEL_MASK             (0x3000U)
46486 #define LPCMP_CCR1_FUNC_CLK_SEL_SHIFT            (12U)
46487 /*! FUNC_CLK_SEL - Functional Clock Source Select
46488  *  0b00..Select functional clock source 0
46489  *  0b01..Select functional clock source 1
46490  *  0b10..Select functional clock source 2
46491  *  0b11..Select functional clock source 3
46492  */
46493 #define LPCMP_CCR1_FUNC_CLK_SEL(x)               (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_FUNC_CLK_SEL_SHIFT)) & LPCMP_CCR1_FUNC_CLK_SEL_MASK)
46494 
46495 #define LPCMP_CCR1_FILT_CNT_MASK                 (0x70000U)
46496 #define LPCMP_CCR1_FILT_CNT_SHIFT                (16U)
46497 /*! FILT_CNT - Filter Sample Count
46498  *  0b000..Filter is bypassed: COUT = COUTA
46499  *  0b001..1 consecutive sample (Comparator output is simply sampled.)
46500  *  0b010..2 consecutive samples
46501  *  0b011..3 consecutive samples
46502  *  0b100..4 consecutive samples
46503  *  0b101..5 consecutive samples
46504  *  0b110..6 consecutive samples
46505  *  0b111..7 consecutive samples
46506  */
46507 #define LPCMP_CCR1_FILT_CNT(x)                   (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_FILT_CNT_SHIFT)) & LPCMP_CCR1_FILT_CNT_MASK)
46508 
46509 #define LPCMP_CCR1_FILT_PER_MASK                 (0xFF000000U)
46510 #define LPCMP_CCR1_FILT_PER_SHIFT                (24U)
46511 /*! FILT_PER - Filter Sample Period */
46512 #define LPCMP_CCR1_FILT_PER(x)                   (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_FILT_PER_SHIFT)) & LPCMP_CCR1_FILT_PER_MASK)
46513 /*! @} */
46514 
46515 /*! @name CCR2 - Comparator Control Register 2 */
46516 /*! @{ */
46517 
46518 #define LPCMP_CCR2_CMP_HPMD_MASK                 (0x1U)
46519 #define LPCMP_CCR2_CMP_HPMD_SHIFT                (0U)
46520 /*! CMP_HPMD - CMP High Power Mode Select
46521  *  0b0..Low power (speed) comparison mode
46522  *  0b1..High power (speed) comparison mode
46523  */
46524 #define LPCMP_CCR2_CMP_HPMD(x)                   (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR2_CMP_HPMD_SHIFT)) & LPCMP_CCR2_CMP_HPMD_MASK)
46525 
46526 #define LPCMP_CCR2_CMP_NPMD_MASK                 (0x2U)
46527 #define LPCMP_CCR2_CMP_NPMD_SHIFT                (1U)
46528 /*! CMP_NPMD - CMP Nano Power Mode Select
46529  *  0b0..Disables CMP Nano power mode. CCR2[CMP_HPMD] determines the mode for the comparator.
46530  *  0b1..Enables CMP Nano power mode.
46531  */
46532 #define LPCMP_CCR2_CMP_NPMD(x)                   (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR2_CMP_NPMD_SHIFT)) & LPCMP_CCR2_CMP_NPMD_MASK)
46533 
46534 #define LPCMP_CCR2_HYSTCTR_MASK                  (0x30U)
46535 #define LPCMP_CCR2_HYSTCTR_SHIFT                 (4U)
46536 /*! HYSTCTR - Comparator Hysteresis Control
46537  *  0b00..Level 0: Analog comparator hysteresis 0 mV.
46538  *  0b01..Level 1: Analog comparator hysteresis 10 mV.
46539  *  0b10..Level 2: Analog comparator hysteresis 20 mV.
46540  *  0b11..Level 3: Analog comparator hysteresis 30 mV.
46541  */
46542 #define LPCMP_CCR2_HYSTCTR(x)                    (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR2_HYSTCTR_SHIFT)) & LPCMP_CCR2_HYSTCTR_MASK)
46543 
46544 #define LPCMP_CCR2_PSEL_MASK                     (0x70000U)
46545 #define LPCMP_CCR2_PSEL_SHIFT                    (16U)
46546 /*! PSEL - Plus Input MUX Select
46547  *  0b000..Input 0p
46548  *  0b001..Input 1p
46549  *  0b010..Input 2p
46550  *  0b011..Input 3p
46551  *  0b100..Input 4p
46552  *  0b101..Input 5p
46553  *  0b110..Reserved
46554  *  0b111..Internal DAC output
46555  */
46556 #define LPCMP_CCR2_PSEL(x)                       (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR2_PSEL_SHIFT)) & LPCMP_CCR2_PSEL_MASK)
46557 
46558 #define LPCMP_CCR2_MSEL_MASK                     (0x700000U)
46559 #define LPCMP_CCR2_MSEL_SHIFT                    (20U)
46560 /*! MSEL - Minus Input MUX Select
46561  *  0b000..Input 0m
46562  *  0b001..Input 1m
46563  *  0b010..Input 2m
46564  *  0b011..Input 3m
46565  *  0b100..Input 4m
46566  *  0b101..Input 5m
46567  *  0b110..Reserved
46568  *  0b111..Internal DAC output
46569  */
46570 #define LPCMP_CCR2_MSEL(x)                       (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR2_MSEL_SHIFT)) & LPCMP_CCR2_MSEL_MASK)
46571 /*! @} */
46572 
46573 /*! @name DCR - DAC Control */
46574 /*! @{ */
46575 
46576 #define LPCMP_DCR_DAC_EN_MASK                    (0x1U)
46577 #define LPCMP_DCR_DAC_EN_SHIFT                   (0U)
46578 /*! DAC_EN - DAC Enable
46579  *  0b0..Disable
46580  *  0b1..Enable
46581  */
46582 #define LPCMP_DCR_DAC_EN(x)                      (((uint32_t)(((uint32_t)(x)) << LPCMP_DCR_DAC_EN_SHIFT)) & LPCMP_DCR_DAC_EN_MASK)
46583 
46584 #define LPCMP_DCR_DAC_HPMD_MASK                  (0x2U)
46585 #define LPCMP_DCR_DAC_HPMD_SHIFT                 (1U)
46586 /*! DAC_HPMD - DAC High Power Mode
46587  *  0b0..Disable
46588  *  0b1..Enable
46589  */
46590 #define LPCMP_DCR_DAC_HPMD(x)                    (((uint32_t)(((uint32_t)(x)) << LPCMP_DCR_DAC_HPMD_SHIFT)) & LPCMP_DCR_DAC_HPMD_MASK)
46591 
46592 #define LPCMP_DCR_VRSEL_MASK                     (0x100U)
46593 #define LPCMP_DCR_VRSEL_SHIFT                    (8U)
46594 /*! VRSEL - DAC Reference High Voltage Source Select
46595  *  0b0..VREFH0
46596  *  0b1..VREFH1
46597  */
46598 #define LPCMP_DCR_VRSEL(x)                       (((uint32_t)(((uint32_t)(x)) << LPCMP_DCR_VRSEL_SHIFT)) & LPCMP_DCR_VRSEL_MASK)
46599 
46600 #define LPCMP_DCR_DAC_DATA_MASK                  (0xFF0000U)
46601 #define LPCMP_DCR_DAC_DATA_SHIFT                 (16U)
46602 /*! DAC_DATA - DAC Output Voltage Select */
46603 #define LPCMP_DCR_DAC_DATA(x)                    (((uint32_t)(((uint32_t)(x)) << LPCMP_DCR_DAC_DATA_SHIFT)) & LPCMP_DCR_DAC_DATA_MASK)
46604 /*! @} */
46605 
46606 /*! @name IER - Interrupt Enable */
46607 /*! @{ */
46608 
46609 #define LPCMP_IER_CFR_IE_MASK                    (0x1U)
46610 #define LPCMP_IER_CFR_IE_SHIFT                   (0U)
46611 /*! CFR_IE - Comparator Flag Rising Interrupt Enable
46612  *  0b0..Disables the comparator flag rising interrupt.
46613  *  0b1..Enables the comparator flag rising interrupt when CFR is set.
46614  */
46615 #define LPCMP_IER_CFR_IE(x)                      (((uint32_t)(((uint32_t)(x)) << LPCMP_IER_CFR_IE_SHIFT)) & LPCMP_IER_CFR_IE_MASK)
46616 
46617 #define LPCMP_IER_CFF_IE_MASK                    (0x2U)
46618 #define LPCMP_IER_CFF_IE_SHIFT                   (1U)
46619 /*! CFF_IE - Comparator Flag Falling Interrupt Enable
46620  *  0b0..Disables the comparator flag falling interrupt.
46621  *  0b1..Enables the comparator flag falling interrupt when CFF is set.
46622  */
46623 #define LPCMP_IER_CFF_IE(x)                      (((uint32_t)(((uint32_t)(x)) << LPCMP_IER_CFF_IE_SHIFT)) & LPCMP_IER_CFF_IE_MASK)
46624 
46625 #define LPCMP_IER_RRF_IE_MASK                    (0x4U)
46626 #define LPCMP_IER_RRF_IE_SHIFT                   (2U)
46627 /*! RRF_IE - Round-Robin Flag Interrupt Enable
46628  *  0b0..Disables the round-robin flag interrupt.
46629  *  0b1..Enables the round-robin flag interrupt when the comparison result changes for a given channel.
46630  */
46631 #define LPCMP_IER_RRF_IE(x)                      (((uint32_t)(((uint32_t)(x)) << LPCMP_IER_RRF_IE_SHIFT)) & LPCMP_IER_RRF_IE_MASK)
46632 /*! @} */
46633 
46634 /*! @name CSR - Comparator Status */
46635 /*! @{ */
46636 
46637 #define LPCMP_CSR_CFR_MASK                       (0x1U)
46638 #define LPCMP_CSR_CFR_SHIFT                      (0U)
46639 /*! CFR - Analog Comparator Flag Rising
46640  *  0b0..Not detected
46641  *  0b1..Detected
46642  */
46643 #define LPCMP_CSR_CFR(x)                         (((uint32_t)(((uint32_t)(x)) << LPCMP_CSR_CFR_SHIFT)) & LPCMP_CSR_CFR_MASK)
46644 
46645 #define LPCMP_CSR_CFF_MASK                       (0x2U)
46646 #define LPCMP_CSR_CFF_SHIFT                      (1U)
46647 /*! CFF - Analog Comparator Flag Falling
46648  *  0b0..Not detected
46649  *  0b1..Detected
46650  */
46651 #define LPCMP_CSR_CFF(x)                         (((uint32_t)(((uint32_t)(x)) << LPCMP_CSR_CFF_SHIFT)) & LPCMP_CSR_CFF_MASK)
46652 
46653 #define LPCMP_CSR_RRF_MASK                       (0x4U)
46654 #define LPCMP_CSR_RRF_SHIFT                      (2U)
46655 /*! RRF - Round-Robin Flag
46656  *  0b0..Not detected
46657  *  0b1..Detected
46658  */
46659 #define LPCMP_CSR_RRF(x)                         (((uint32_t)(((uint32_t)(x)) << LPCMP_CSR_RRF_SHIFT)) & LPCMP_CSR_RRF_MASK)
46660 
46661 #define LPCMP_CSR_COUT_MASK                      (0x100U)
46662 #define LPCMP_CSR_COUT_SHIFT                     (8U)
46663 /*! COUT - Analog Comparator Output */
46664 #define LPCMP_CSR_COUT(x)                        (((uint32_t)(((uint32_t)(x)) << LPCMP_CSR_COUT_SHIFT)) & LPCMP_CSR_COUT_MASK)
46665 /*! @} */
46666 
46667 /*! @name RRCR0 - Round Robin Control Register 0 */
46668 /*! @{ */
46669 
46670 #define LPCMP_RRCR0_RR_EN_MASK                   (0x1U)
46671 #define LPCMP_RRCR0_RR_EN_SHIFT                  (0U)
46672 /*! RR_EN - Round-Robin Enable
46673  *  0b1..Enable
46674  *  0b0..Disable
46675  */
46676 #define LPCMP_RRCR0_RR_EN(x)                     (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_EN_SHIFT)) & LPCMP_RRCR0_RR_EN_MASK)
46677 
46678 #define LPCMP_RRCR0_RR_TRG_SEL_MASK              (0x2U)
46679 #define LPCMP_RRCR0_RR_TRG_SEL_SHIFT             (1U)
46680 /*! RR_TRG_SEL - Round-Robin Trigger Select
46681  *  0b0..External trigger
46682  *  0b1..Internal trigger
46683  */
46684 #define LPCMP_RRCR0_RR_TRG_SEL(x)                (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_TRG_SEL_SHIFT)) & LPCMP_RRCR0_RR_TRG_SEL_MASK)
46685 
46686 #define LPCMP_RRCR0_RR_NSAM_MASK                 (0x300U)
46687 #define LPCMP_RRCR0_RR_NSAM_SHIFT                (8U)
46688 /*! RR_NSAM - Number of Sample Clocks
46689  *  0b00..0 clock
46690  *  0b01..1 clock
46691  *  0b10..2 clocks
46692  *  0b11..3 clocks
46693  */
46694 #define LPCMP_RRCR0_RR_NSAM(x)                   (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_NSAM_SHIFT)) & LPCMP_RRCR0_RR_NSAM_MASK)
46695 
46696 #define LPCMP_RRCR0_RR_CLK_SEL_MASK              (0x3000U)
46697 #define LPCMP_RRCR0_RR_CLK_SEL_SHIFT             (12U)
46698 /*! RR_CLK_SEL - Round Robin Clock Source Select
46699  *  0b00..Select Round Robin clock Source 0
46700  *  0b01..Select Round Robin clock Source 1
46701  *  0b10..Select Round Robin clock Source 2
46702  *  0b11..Select Round Robin clock Source 3
46703  */
46704 #define LPCMP_RRCR0_RR_CLK_SEL(x)                (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_CLK_SEL_SHIFT)) & LPCMP_RRCR0_RR_CLK_SEL_MASK)
46705 
46706 #define LPCMP_RRCR0_RR_INITMOD_MASK              (0x3F0000U)
46707 #define LPCMP_RRCR0_RR_INITMOD_SHIFT             (16U)
46708 /*! RR_INITMOD - Initialization Delay Modulus
46709  *  0b000000..63 cycles (same as 111111b)
46710  *  0b000001-0b111111..1 to 63 cycles
46711  */
46712 #define LPCMP_RRCR0_RR_INITMOD(x)                (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_INITMOD_SHIFT)) & LPCMP_RRCR0_RR_INITMOD_MASK)
46713 
46714 #define LPCMP_RRCR0_RR_SAMPLE_CNT_MASK           (0xF000000U)
46715 #define LPCMP_RRCR0_RR_SAMPLE_CNT_SHIFT          (24U)
46716 /*! RR_SAMPLE_CNT - Number of Sample for One Channel
46717  *  0b0000..1 samples
46718  *  0b0001..2 samples
46719  *  0b0010..3 samples
46720  *  0b0011..4 samples
46721  *  0b0100..5 samples
46722  *  0b0101..6 samples
46723  *  0b0110..7 samples
46724  *  0b0111..8 samples
46725  *  0b1000..9 samples
46726  *  0b1001..10 samples
46727  *  0b1010..11 samples
46728  *  0b1011..12 samples
46729  *  0b1100..13 samples
46730  *  0b1101..14 samples
46731  *  0b1110..15 samples
46732  *  0b1111..16 samples
46733  */
46734 #define LPCMP_RRCR0_RR_SAMPLE_CNT(x)             (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_SAMPLE_CNT_SHIFT)) & LPCMP_RRCR0_RR_SAMPLE_CNT_MASK)
46735 
46736 #define LPCMP_RRCR0_RR_SAMPLE_THRESHOLD_MASK     (0xF0000000U)
46737 #define LPCMP_RRCR0_RR_SAMPLE_THRESHOLD_SHIFT    (28U)
46738 /*! RR_SAMPLE_THRESHOLD - Sample Time Threshold
46739  *  0b0000..At least 1 sampled "1", the final result is "1"
46740  *  0b0001..At least 2 sampled "1", the final result is "1"
46741  *  0b0010..At least 3 sampled "1", the final result is "1"
46742  *  0b0011..At least 4 sampled "1", the final result is "1"
46743  *  0b0100..At least 5 sampled "1", the final result is "1"
46744  *  0b0101..At least 6 sampled "1", the final result is "1"
46745  *  0b0110..At least 7 sampled "1", the final result is "1"
46746  *  0b0111..At least 8 sampled "1", the final result is "1"
46747  *  0b1000..At least 9 sampled "1", the final result is "1"
46748  *  0b1001..At least 10 sampled "1", the final result is "1"
46749  *  0b1010..At least 11 sampled "1", the final result is "1"
46750  *  0b1011..At least 12 sampled "1", the final result is "1"
46751  *  0b1100..At least 13 sampled "1", the final result is "1"
46752  *  0b1101..At least 14 sampled "1", the final result is "1"
46753  *  0b1110..At least 15 sampled "1", the final result is "1"
46754  *  0b1111..At least 16 sampled "1", the final result is "1"
46755  */
46756 #define LPCMP_RRCR0_RR_SAMPLE_THRESHOLD(x)       (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_SAMPLE_THRESHOLD_SHIFT)) & LPCMP_RRCR0_RR_SAMPLE_THRESHOLD_MASK)
46757 /*! @} */
46758 
46759 /*! @name RRCR1 - Round Robin Control Register 1 */
46760 /*! @{ */
46761 
46762 #define LPCMP_RRCR1_RR_CH0EN_MASK                (0x1U)
46763 #define LPCMP_RRCR1_RR_CH0EN_SHIFT               (0U)
46764 /*! RR_CH0EN - Channel 0 Input Enable in Trigger Mode
46765  *  0b1..Enable
46766  *  0b0..Disable
46767  */
46768 #define LPCMP_RRCR1_RR_CH0EN(x)                  (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH0EN_SHIFT)) & LPCMP_RRCR1_RR_CH0EN_MASK)
46769 
46770 #define LPCMP_RRCR1_RR_CH1EN_MASK                (0x2U)
46771 #define LPCMP_RRCR1_RR_CH1EN_SHIFT               (1U)
46772 /*! RR_CH1EN - Channel 1 Input Enable in Trigger Mode
46773  *  0b1..Enable
46774  *  0b0..Disable
46775  */
46776 #define LPCMP_RRCR1_RR_CH1EN(x)                  (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH1EN_SHIFT)) & LPCMP_RRCR1_RR_CH1EN_MASK)
46777 
46778 #define LPCMP_RRCR1_RR_CH2EN_MASK                (0x4U)
46779 #define LPCMP_RRCR1_RR_CH2EN_SHIFT               (2U)
46780 /*! RR_CH2EN - Channel 2 Input Enable in Trigger Mode
46781  *  0b1..Enable
46782  *  0b0..Disable
46783  */
46784 #define LPCMP_RRCR1_RR_CH2EN(x)                  (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH2EN_SHIFT)) & LPCMP_RRCR1_RR_CH2EN_MASK)
46785 
46786 #define LPCMP_RRCR1_RR_CH3EN_MASK                (0x8U)
46787 #define LPCMP_RRCR1_RR_CH3EN_SHIFT               (3U)
46788 /*! RR_CH3EN - Channel 3 Input Enable in Trigger Mode
46789  *  0b1..Enable
46790  *  0b0..Disable
46791  */
46792 #define LPCMP_RRCR1_RR_CH3EN(x)                  (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH3EN_SHIFT)) & LPCMP_RRCR1_RR_CH3EN_MASK)
46793 
46794 #define LPCMP_RRCR1_RR_CH4EN_MASK                (0x10U)
46795 #define LPCMP_RRCR1_RR_CH4EN_SHIFT               (4U)
46796 /*! RR_CH4EN - Channel 4 Input Enable in Trigger Mode
46797  *  0b1..Enable
46798  *  0b0..Disable
46799  */
46800 #define LPCMP_RRCR1_RR_CH4EN(x)                  (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH4EN_SHIFT)) & LPCMP_RRCR1_RR_CH4EN_MASK)
46801 
46802 #define LPCMP_RRCR1_RR_CH5EN_MASK                (0x20U)
46803 #define LPCMP_RRCR1_RR_CH5EN_SHIFT               (5U)
46804 /*! RR_CH5EN - Channel 5 Input Enable in Trigger Mode
46805  *  0b1..Enable
46806  *  0b0..Disable
46807  */
46808 #define LPCMP_RRCR1_RR_CH5EN(x)                  (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH5EN_SHIFT)) & LPCMP_RRCR1_RR_CH5EN_MASK)
46809 
46810 #define LPCMP_RRCR1_RR_CH6EN_MASK                (0x40U)
46811 #define LPCMP_RRCR1_RR_CH6EN_SHIFT               (6U)
46812 /*! RR_CH6EN - Channel 6 Input Enable in Trigger Mode
46813  *  0b1..Enable
46814  *  0b0..Disable
46815  */
46816 #define LPCMP_RRCR1_RR_CH6EN(x)                  (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH6EN_SHIFT)) & LPCMP_RRCR1_RR_CH6EN_MASK)
46817 
46818 #define LPCMP_RRCR1_RR_CH7EN_MASK                (0x80U)
46819 #define LPCMP_RRCR1_RR_CH7EN_SHIFT               (7U)
46820 /*! RR_CH7EN - Channel 7 Input Enable in Trigger Mode
46821  *  0b1..Enable
46822  *  0b0..Disable
46823  */
46824 #define LPCMP_RRCR1_RR_CH7EN(x)                  (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH7EN_SHIFT)) & LPCMP_RRCR1_RR_CH7EN_MASK)
46825 
46826 #define LPCMP_RRCR1_FIXP_MASK                    (0x10000U)
46827 #define LPCMP_RRCR1_FIXP_SHIFT                   (16U)
46828 /*! FIXP - Fixed Port
46829  *  0b0..Fix the plus port. Sweep only the inputs to the minus port.
46830  *  0b1..Fix the minus port. Sweep only the inputs to the plus port.
46831  */
46832 #define LPCMP_RRCR1_FIXP(x)                      (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_FIXP_SHIFT)) & LPCMP_RRCR1_FIXP_MASK)
46833 
46834 #define LPCMP_RRCR1_FIXCH_MASK                   (0x700000U)
46835 #define LPCMP_RRCR1_FIXCH_SHIFT                  (20U)
46836 /*! FIXCH - Fixed Channel Select
46837  *  0b000..Channel 0
46838  *  0b001..Channel 1
46839  *  0b010..Channel 2
46840  *  0b011..Channel 3
46841  *  0b100..Channel 4
46842  *  0b101..Channel 5
46843  *  0b110..Channel 6
46844  *  0b111..Channel 7
46845  */
46846 #define LPCMP_RRCR1_FIXCH(x)                     (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_FIXCH_SHIFT)) & LPCMP_RRCR1_FIXCH_MASK)
46847 /*! @} */
46848 
46849 /*! @name RRCSR - Round Robin Control and Status */
46850 /*! @{ */
46851 
46852 #define LPCMP_RRCSR_RR_CH0OUT_MASK               (0x1U)
46853 #define LPCMP_RRCSR_RR_CH0OUT_SHIFT              (0U)
46854 /*! RR_CH0OUT - Comparison Result for Channel 0 */
46855 #define LPCMP_RRCSR_RR_CH0OUT(x)                 (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH0OUT_SHIFT)) & LPCMP_RRCSR_RR_CH0OUT_MASK)
46856 
46857 #define LPCMP_RRCSR_RR_CH1OUT_MASK               (0x2U)
46858 #define LPCMP_RRCSR_RR_CH1OUT_SHIFT              (1U)
46859 /*! RR_CH1OUT - Comparison Result for Channel 1 */
46860 #define LPCMP_RRCSR_RR_CH1OUT(x)                 (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH1OUT_SHIFT)) & LPCMP_RRCSR_RR_CH1OUT_MASK)
46861 
46862 #define LPCMP_RRCSR_RR_CH2OUT_MASK               (0x4U)
46863 #define LPCMP_RRCSR_RR_CH2OUT_SHIFT              (2U)
46864 /*! RR_CH2OUT - Comparison Result for Channel 2 */
46865 #define LPCMP_RRCSR_RR_CH2OUT(x)                 (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH2OUT_SHIFT)) & LPCMP_RRCSR_RR_CH2OUT_MASK)
46866 
46867 #define LPCMP_RRCSR_RR_CH3OUT_MASK               (0x8U)
46868 #define LPCMP_RRCSR_RR_CH3OUT_SHIFT              (3U)
46869 /*! RR_CH3OUT - Comparison Result for Channel 3 */
46870 #define LPCMP_RRCSR_RR_CH3OUT(x)                 (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH3OUT_SHIFT)) & LPCMP_RRCSR_RR_CH3OUT_MASK)
46871 
46872 #define LPCMP_RRCSR_RR_CH4OUT_MASK               (0x10U)
46873 #define LPCMP_RRCSR_RR_CH4OUT_SHIFT              (4U)
46874 /*! RR_CH4OUT - Comparison Result for Channel 4 */
46875 #define LPCMP_RRCSR_RR_CH4OUT(x)                 (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH4OUT_SHIFT)) & LPCMP_RRCSR_RR_CH4OUT_MASK)
46876 
46877 #define LPCMP_RRCSR_RR_CH5OUT_MASK               (0x20U)
46878 #define LPCMP_RRCSR_RR_CH5OUT_SHIFT              (5U)
46879 /*! RR_CH5OUT - Comparison Result for Channel 5 */
46880 #define LPCMP_RRCSR_RR_CH5OUT(x)                 (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH5OUT_SHIFT)) & LPCMP_RRCSR_RR_CH5OUT_MASK)
46881 
46882 #define LPCMP_RRCSR_RR_CH6OUT_MASK               (0x40U)
46883 #define LPCMP_RRCSR_RR_CH6OUT_SHIFT              (6U)
46884 /*! RR_CH6OUT - Comparison Result for Channel 6 */
46885 #define LPCMP_RRCSR_RR_CH6OUT(x)                 (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH6OUT_SHIFT)) & LPCMP_RRCSR_RR_CH6OUT_MASK)
46886 
46887 #define LPCMP_RRCSR_RR_CH7OUT_MASK               (0x80U)
46888 #define LPCMP_RRCSR_RR_CH7OUT_SHIFT              (7U)
46889 /*! RR_CH7OUT - Comparison Result for Channel 7 */
46890 #define LPCMP_RRCSR_RR_CH7OUT(x)                 (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH7OUT_SHIFT)) & LPCMP_RRCSR_RR_CH7OUT_MASK)
46891 /*! @} */
46892 
46893 /*! @name RRSR - Round Robin Status */
46894 /*! @{ */
46895 
46896 #define LPCMP_RRSR_RR_CH0F_MASK                  (0x1U)
46897 #define LPCMP_RRSR_RR_CH0F_SHIFT                 (0U)
46898 /*! RR_CH0F - Channel 0 Input Changed Flag
46899  *  0b0..No different
46900  *  0b1..Different
46901  */
46902 #define LPCMP_RRSR_RR_CH0F(x)                    (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH0F_SHIFT)) & LPCMP_RRSR_RR_CH0F_MASK)
46903 
46904 #define LPCMP_RRSR_RR_CH1F_MASK                  (0x2U)
46905 #define LPCMP_RRSR_RR_CH1F_SHIFT                 (1U)
46906 /*! RR_CH1F - Channel 1 Input Changed Flag
46907  *  0b0..No different
46908  *  0b1..Different
46909  */
46910 #define LPCMP_RRSR_RR_CH1F(x)                    (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH1F_SHIFT)) & LPCMP_RRSR_RR_CH1F_MASK)
46911 
46912 #define LPCMP_RRSR_RR_CH2F_MASK                  (0x4U)
46913 #define LPCMP_RRSR_RR_CH2F_SHIFT                 (2U)
46914 /*! RR_CH2F - Channel 2 Input Changed Flag
46915  *  0b0..No different
46916  *  0b1..Different
46917  */
46918 #define LPCMP_RRSR_RR_CH2F(x)                    (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH2F_SHIFT)) & LPCMP_RRSR_RR_CH2F_MASK)
46919 
46920 #define LPCMP_RRSR_RR_CH3F_MASK                  (0x8U)
46921 #define LPCMP_RRSR_RR_CH3F_SHIFT                 (3U)
46922 /*! RR_CH3F - Channel 3 Input Changed Flag
46923  *  0b0..No different
46924  *  0b1..Different
46925  */
46926 #define LPCMP_RRSR_RR_CH3F(x)                    (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH3F_SHIFT)) & LPCMP_RRSR_RR_CH3F_MASK)
46927 
46928 #define LPCMP_RRSR_RR_CH4F_MASK                  (0x10U)
46929 #define LPCMP_RRSR_RR_CH4F_SHIFT                 (4U)
46930 /*! RR_CH4F - Channel 4 Input Changed Flag
46931  *  0b0..No different
46932  *  0b1..Different
46933  */
46934 #define LPCMP_RRSR_RR_CH4F(x)                    (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH4F_SHIFT)) & LPCMP_RRSR_RR_CH4F_MASK)
46935 
46936 #define LPCMP_RRSR_RR_CH5F_MASK                  (0x20U)
46937 #define LPCMP_RRSR_RR_CH5F_SHIFT                 (5U)
46938 /*! RR_CH5F - Channel 5 Input Changed Flag
46939  *  0b0..No different
46940  *  0b1..Different
46941  */
46942 #define LPCMP_RRSR_RR_CH5F(x)                    (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH5F_SHIFT)) & LPCMP_RRSR_RR_CH5F_MASK)
46943 
46944 #define LPCMP_RRSR_RR_CH6F_MASK                  (0x40U)
46945 #define LPCMP_RRSR_RR_CH6F_SHIFT                 (6U)
46946 /*! RR_CH6F - Channel 6 Input Changed Flag
46947  *  0b0..No different
46948  *  0b1..Different
46949  */
46950 #define LPCMP_RRSR_RR_CH6F(x)                    (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH6F_SHIFT)) & LPCMP_RRSR_RR_CH6F_MASK)
46951 
46952 #define LPCMP_RRSR_RR_CH7F_MASK                  (0x80U)
46953 #define LPCMP_RRSR_RR_CH7F_SHIFT                 (7U)
46954 /*! RR_CH7F - Channel 7 Input Changed Flag
46955  *  0b0..No different
46956  *  0b1..Different
46957  */
46958 #define LPCMP_RRSR_RR_CH7F(x)                    (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH7F_SHIFT)) & LPCMP_RRSR_RR_CH7F_MASK)
46959 /*! @} */
46960 
46961 /*! @name RRCR2 - Round Robin Control Register 2 */
46962 /*! @{ */
46963 
46964 #define LPCMP_RRCR2_RR_TIMER_RELOAD_MASK         (0xFFFFFFFU)
46965 #define LPCMP_RRCR2_RR_TIMER_RELOAD_SHIFT        (0U)
46966 /*! RR_TIMER_RELOAD - Number of Sample Clocks */
46967 #define LPCMP_RRCR2_RR_TIMER_RELOAD(x)           (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR2_RR_TIMER_RELOAD_SHIFT)) & LPCMP_RRCR2_RR_TIMER_RELOAD_MASK)
46968 
46969 #define LPCMP_RRCR2_RR_TIMER_EN_MASK             (0x80000000U)
46970 #define LPCMP_RRCR2_RR_TIMER_EN_SHIFT            (31U)
46971 /*! RR_TIMER_EN - Round-Robin Internal Timer Enable
46972  *  0b0..Disables
46973  *  0b1..Enables
46974  */
46975 #define LPCMP_RRCR2_RR_TIMER_EN(x)               (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR2_RR_TIMER_EN_SHIFT)) & LPCMP_RRCR2_RR_TIMER_EN_MASK)
46976 /*! @} */
46977 
46978 
46979 /*!
46980  * @}
46981  */ /* end of group LPCMP_Register_Masks */
46982 
46983 
46984 /* LPCMP - Peripheral instance base addresses */
46985 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
46986   /** Peripheral CMP0 base address */
46987   #define CMP0_BASE                                (0x50051000u)
46988   /** Peripheral CMP0 base address */
46989   #define CMP0_BASE_NS                             (0x40051000u)
46990   /** Peripheral CMP0 base pointer */
46991   #define CMP0                                     ((LPCMP_Type *)CMP0_BASE)
46992   /** Peripheral CMP0 base pointer */
46993   #define CMP0_NS                                  ((LPCMP_Type *)CMP0_BASE_NS)
46994   /** Peripheral CMP1 base address */
46995   #define CMP1_BASE                                (0x50052000u)
46996   /** Peripheral CMP1 base address */
46997   #define CMP1_BASE_NS                             (0x40052000u)
46998   /** Peripheral CMP1 base pointer */
46999   #define CMP1                                     ((LPCMP_Type *)CMP1_BASE)
47000   /** Peripheral CMP1 base pointer */
47001   #define CMP1_NS                                  ((LPCMP_Type *)CMP1_BASE_NS)
47002   /** Array initializer of LPCMP peripheral base addresses */
47003   #define LPCMP_BASE_ADDRS                         { CMP0_BASE, CMP1_BASE }
47004   /** Array initializer of LPCMP peripheral base pointers */
47005   #define LPCMP_BASE_PTRS                          { CMP0, CMP1 }
47006   /** Array initializer of LPCMP peripheral base addresses */
47007   #define LPCMP_BASE_ADDRS_NS                      { CMP0_BASE_NS, CMP1_BASE_NS }
47008   /** Array initializer of LPCMP peripheral base pointers */
47009   #define LPCMP_BASE_PTRS_NS                       { CMP0_NS, CMP1_NS }
47010 #else
47011   /** Peripheral CMP0 base address */
47012   #define CMP0_BASE                                (0x40051000u)
47013   /** Peripheral CMP0 base pointer */
47014   #define CMP0                                     ((LPCMP_Type *)CMP0_BASE)
47015   /** Peripheral CMP1 base address */
47016   #define CMP1_BASE                                (0x40052000u)
47017   /** Peripheral CMP1 base pointer */
47018   #define CMP1                                     ((LPCMP_Type *)CMP1_BASE)
47019   /** Array initializer of LPCMP peripheral base addresses */
47020   #define LPCMP_BASE_ADDRS                         { CMP0_BASE, CMP1_BASE }
47021   /** Array initializer of LPCMP peripheral base pointers */
47022   #define LPCMP_BASE_PTRS                          { CMP0, CMP1 }
47023 #endif
47024 /** Interrupt vectors for the LPCMP peripheral type */
47025 #define LPCMP_IRQS                               { HSCMP0_IRQn, HSCMP1_IRQn }
47026 
47027 /*!
47028  * @}
47029  */ /* end of group LPCMP_Peripheral_Access_Layer */
47030 
47031 
47032 /* ----------------------------------------------------------------------------
47033    -- LPDAC Peripheral Access Layer
47034    ---------------------------------------------------------------------------- */
47035 
47036 /*!
47037  * @addtogroup LPDAC_Peripheral_Access_Layer LPDAC Peripheral Access Layer
47038  * @{
47039  */
47040 
47041 /** LPDAC - Register Layout Typedef */
47042 typedef struct {
47043   __I  uint32_t VERID;                             /**< Version Identifier, offset: 0x0 */
47044   __I  uint32_t PARAM;                             /**< Parameter, offset: 0x4 */
47045   __O  uint32_t DATA;                              /**< Data, offset: 0x8 */
47046   __IO uint32_t GCR;                               /**< Global Control, offset: 0xC */
47047   __IO uint32_t FCR;                               /**< DAC FIFO Control, offset: 0x10 */
47048   __I  uint32_t FPR;                               /**< DAC FIFO Pointer, offset: 0x14 */
47049   __IO uint32_t FSR;                               /**< FIFO Status, offset: 0x18 */
47050   __IO uint32_t IER;                               /**< Interrupt Enable, offset: 0x1C */
47051   __IO uint32_t DER;                               /**< DMA Enable, offset: 0x20 */
47052   __IO uint32_t RCR;                               /**< Reset Control, offset: 0x24 */
47053   __O  uint32_t TCR;                               /**< Trigger Control, offset: 0x28 */
47054   __IO uint32_t PCR;                               /**< Periodic Trigger Control, offset: 0x2C */
47055 } LPDAC_Type;
47056 
47057 /* ----------------------------------------------------------------------------
47058    -- LPDAC Register Masks
47059    ---------------------------------------------------------------------------- */
47060 
47061 /*!
47062  * @addtogroup LPDAC_Register_Masks LPDAC Register Masks
47063  * @{
47064  */
47065 
47066 /*! @name VERID - Version Identifier */
47067 /*! @{ */
47068 
47069 #define LPDAC_VERID_FEATURE_MASK                 (0xFFFFU)
47070 #define LPDAC_VERID_FEATURE_SHIFT                (0U)
47071 /*! FEATURE - Feature Identification Number */
47072 #define LPDAC_VERID_FEATURE(x)                   (((uint32_t)(((uint32_t)(x)) << LPDAC_VERID_FEATURE_SHIFT)) & LPDAC_VERID_FEATURE_MASK)
47073 
47074 #define LPDAC_VERID_MINOR_MASK                   (0xFF0000U)
47075 #define LPDAC_VERID_MINOR_SHIFT                  (16U)
47076 /*! MINOR - Minor Version Number */
47077 #define LPDAC_VERID_MINOR(x)                     (((uint32_t)(((uint32_t)(x)) << LPDAC_VERID_MINOR_SHIFT)) & LPDAC_VERID_MINOR_MASK)
47078 
47079 #define LPDAC_VERID_MAJOR_MASK                   (0xFF000000U)
47080 #define LPDAC_VERID_MAJOR_SHIFT                  (24U)
47081 /*! MAJOR - Major Version Number */
47082 #define LPDAC_VERID_MAJOR(x)                     (((uint32_t)(((uint32_t)(x)) << LPDAC_VERID_MAJOR_SHIFT)) & LPDAC_VERID_MAJOR_MASK)
47083 /*! @} */
47084 
47085 /*! @name PARAM - Parameter */
47086 /*! @{ */
47087 
47088 #define LPDAC_PARAM_FIFOSZ_MASK                  (0x7U)
47089 #define LPDAC_PARAM_FIFOSZ_SHIFT                 (0U)
47090 /*! FIFOSZ - FIFO Size
47091  *  0b000..Reserved
47092  *  0b001..FIFO depth is 4
47093  *  0b010..FIFO depth is 8
47094  *  0b011..FIFO depth is 16
47095  *  0b100..FIFO depth is 32
47096  *  0b101..FIFO depth is 64
47097  *  0b110..FIFO depth is 128
47098  *  0b111..FIFO depth is 256
47099  */
47100 #define LPDAC_PARAM_FIFOSZ(x)                    (((uint32_t)(((uint32_t)(x)) << LPDAC_PARAM_FIFOSZ_SHIFT)) & LPDAC_PARAM_FIFOSZ_MASK)
47101 /*! @} */
47102 
47103 /*! @name DATA - Data */
47104 /*! @{ */
47105 
47106 #define LPDAC_DATA_DATA_MASK                     (0xFFFU)
47107 #define LPDAC_DATA_DATA_SHIFT                    (0U)
47108 /*! DATA - FIFO Entry or Buffer Entry */
47109 #define LPDAC_DATA_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPDAC_DATA_DATA_SHIFT)) & LPDAC_DATA_DATA_MASK)
47110 /*! @} */
47111 
47112 /*! @name GCR - Global Control */
47113 /*! @{ */
47114 
47115 #define LPDAC_GCR_DACEN_MASK                     (0x1U)
47116 #define LPDAC_GCR_DACEN_SHIFT                    (0U)
47117 /*! DACEN - DAC Enable
47118  *  0b0..Disables
47119  *  0b1..Enables
47120  */
47121 #define LPDAC_GCR_DACEN(x)                       (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_DACEN_SHIFT)) & LPDAC_GCR_DACEN_MASK)
47122 
47123 #define LPDAC_GCR_DACRFS_MASK                    (0x6U)
47124 #define LPDAC_GCR_DACRFS_SHIFT                   (1U)
47125 /*! DACRFS - DAC Reference Select
47126  *  0b00..Selects VREFH0 as the reference voltage.
47127  *  0b01..Selects VREFH1 as the reference voltage.
47128  *  0b10..Selects VREFH2 as the reference voltage.
47129  *  0b11..Reserved.
47130  */
47131 #define LPDAC_GCR_DACRFS(x)                      (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_DACRFS_SHIFT)) & LPDAC_GCR_DACRFS_MASK)
47132 
47133 #define LPDAC_GCR_FIFOEN_MASK                    (0x8U)
47134 #define LPDAC_GCR_FIFOEN_SHIFT                   (3U)
47135 /*! FIFOEN - FIFO Enable
47136  *  0b0..Enables FIFO mode and disables Buffer mode. Any data written to DATA[DATA] goes to buffer then goes to conversion.
47137  *  0b1..Enables FIFO mode. Data will be first read from FIFO to buffer and then goes to conversion.
47138  */
47139 #define LPDAC_GCR_FIFOEN(x)                      (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_FIFOEN_SHIFT)) & LPDAC_GCR_FIFOEN_MASK)
47140 
47141 #define LPDAC_GCR_SWMD_MASK                      (0x10U)
47142 #define LPDAC_GCR_SWMD_SHIFT                     (4U)
47143 /*! SWMD - Swing Back Mode
47144  *  0b0..Disables
47145  *  0b1..Enables
47146  */
47147 #define LPDAC_GCR_SWMD(x)                        (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_SWMD_SHIFT)) & LPDAC_GCR_SWMD_MASK)
47148 
47149 #define LPDAC_GCR_TRGSEL_MASK                    (0x20U)
47150 #define LPDAC_GCR_TRGSEL_SHIFT                   (5U)
47151 /*! TRGSEL - DAC Trigger Select
47152  *  0b0..Hardware trigger
47153  *  0b1..Software trigger
47154  */
47155 #define LPDAC_GCR_TRGSEL(x)                      (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_TRGSEL_SHIFT)) & LPDAC_GCR_TRGSEL_MASK)
47156 
47157 #define LPDAC_GCR_PTGEN_MASK                     (0x40U)
47158 #define LPDAC_GCR_PTGEN_SHIFT                    (6U)
47159 /*! PTGEN - DAC Periodic Trigger Mode Enable
47160  *  0b0..Disables
47161  *  0b1..Enables
47162  */
47163 #define LPDAC_GCR_PTGEN(x)                       (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_PTGEN_SHIFT)) & LPDAC_GCR_PTGEN_MASK)
47164 
47165 #define LPDAC_GCR_LATCH_CYC_MASK                 (0xF00U)
47166 #define LPDAC_GCR_LATCH_CYC_SHIFT                (8U)
47167 /*! LATCH_CYC - RCLK Cycles Before Data Latch */
47168 #define LPDAC_GCR_LATCH_CYC(x)                   (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_LATCH_CYC_SHIFT)) & LPDAC_GCR_LATCH_CYC_MASK)
47169 
47170 #define LPDAC_GCR_BUF_EN_MASK                    (0x20000U)
47171 #define LPDAC_GCR_BUF_EN_SHIFT                   (17U)
47172 /*! BUF_EN - Buffer Enable
47173  *  0b0..Not used
47174  *  0b1..Used
47175  */
47176 #define LPDAC_GCR_BUF_EN(x)                      (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_BUF_EN_SHIFT)) & LPDAC_GCR_BUF_EN_MASK)
47177 
47178 #define LPDAC_GCR_IREF_PTAT_EXT_SEL_MASK         (0x100000U)
47179 #define LPDAC_GCR_IREF_PTAT_EXT_SEL_SHIFT        (20U)
47180 /*! IREF_PTAT_EXT_SEL - External On-Chip PTAT Current Reference Select
47181  *  0b0..Not selected
47182  *  0b1..Selected
47183  */
47184 #define LPDAC_GCR_IREF_PTAT_EXT_SEL(x)           (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_IREF_PTAT_EXT_SEL_SHIFT)) & LPDAC_GCR_IREF_PTAT_EXT_SEL_MASK)
47185 
47186 #define LPDAC_GCR_IREF_ZTC_EXT_SEL_MASK          (0x200000U)
47187 #define LPDAC_GCR_IREF_ZTC_EXT_SEL_SHIFT         (21U)
47188 /*! IREF_ZTC_EXT_SEL - External On-Chip ZTC Current Reference Select
47189  *  0b0..Not selected
47190  *  0b1..Selected
47191  */
47192 #define LPDAC_GCR_IREF_ZTC_EXT_SEL(x)            (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_IREF_ZTC_EXT_SEL_SHIFT)) & LPDAC_GCR_IREF_ZTC_EXT_SEL_MASK)
47193 
47194 #define LPDAC_GCR_BUF_SPD_CTRL_MASK              (0x800000U)
47195 #define LPDAC_GCR_BUF_SPD_CTRL_SHIFT             (23U)
47196 /*! BUF_SPD_CTRL - OPAMP as Buffer, Speed Control Signal
47197  *  0b0..Lower Low-Power mode
47198  *  0b1..Low-Power mode
47199  */
47200 #define LPDAC_GCR_BUF_SPD_CTRL(x)                (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_BUF_SPD_CTRL_SHIFT)) & LPDAC_GCR_BUF_SPD_CTRL_MASK)
47201 /*! @} */
47202 
47203 /*! @name FCR - DAC FIFO Control */
47204 /*! @{ */
47205 
47206 #define LPDAC_FCR_WML_MASK                       (0xFU)
47207 #define LPDAC_FCR_WML_SHIFT                      (0U)
47208 /*! WML - Watermark Level */
47209 #define LPDAC_FCR_WML(x)                         (((uint32_t)(((uint32_t)(x)) << LPDAC_FCR_WML_SHIFT)) & LPDAC_FCR_WML_MASK)
47210 /*! @} */
47211 
47212 /*! @name FPR - DAC FIFO Pointer */
47213 /*! @{ */
47214 
47215 #define LPDAC_FPR_FIFO_RPT_MASK                  (0xFU)
47216 #define LPDAC_FPR_FIFO_RPT_SHIFT                 (0U)
47217 /*! FIFO_RPT - FIFO Read Pointer */
47218 #define LPDAC_FPR_FIFO_RPT(x)                    (((uint32_t)(((uint32_t)(x)) << LPDAC_FPR_FIFO_RPT_SHIFT)) & LPDAC_FPR_FIFO_RPT_MASK)
47219 
47220 #define LPDAC_FPR_FIFO_WPT_MASK                  (0xF0000U)
47221 #define LPDAC_FPR_FIFO_WPT_SHIFT                 (16U)
47222 /*! FIFO_WPT - FIFO Write Pointer */
47223 #define LPDAC_FPR_FIFO_WPT(x)                    (((uint32_t)(((uint32_t)(x)) << LPDAC_FPR_FIFO_WPT_SHIFT)) & LPDAC_FPR_FIFO_WPT_MASK)
47224 /*! @} */
47225 
47226 /*! @name FSR - FIFO Status */
47227 /*! @{ */
47228 
47229 #define LPDAC_FSR_FULL_MASK                      (0x1U)
47230 #define LPDAC_FSR_FULL_SHIFT                     (0U)
47231 /*! FULL - FIFO Full Flag
47232  *  0b0..Not full
47233  *  0b1..Full
47234  */
47235 #define LPDAC_FSR_FULL(x)                        (((uint32_t)(((uint32_t)(x)) << LPDAC_FSR_FULL_SHIFT)) & LPDAC_FSR_FULL_MASK)
47236 
47237 #define LPDAC_FSR_EMPTY_MASK                     (0x2U)
47238 #define LPDAC_FSR_EMPTY_SHIFT                    (1U)
47239 /*! EMPTY - FIFO Empty Flag
47240  *  0b0..Not empty
47241  *  0b1..Empty
47242  */
47243 #define LPDAC_FSR_EMPTY(x)                       (((uint32_t)(((uint32_t)(x)) << LPDAC_FSR_EMPTY_SHIFT)) & LPDAC_FSR_EMPTY_MASK)
47244 
47245 #define LPDAC_FSR_WM_MASK                        (0x4U)
47246 #define LPDAC_FSR_WM_SHIFT                       (2U)
47247 /*! WM - FIFO Watermark Status Flag
47248  *  0b0..Data in FIFO is more than watermark level
47249  *  0b1..Data in FIFO is less than or equal to watermark level
47250  */
47251 #define LPDAC_FSR_WM(x)                          (((uint32_t)(((uint32_t)(x)) << LPDAC_FSR_WM_SHIFT)) & LPDAC_FSR_WM_MASK)
47252 
47253 #define LPDAC_FSR_SWBK_MASK                      (0x8U)
47254 #define LPDAC_FSR_SWBK_SHIFT                     (3U)
47255 /*! SWBK - Swing Back One Cycle Complete Flag
47256  *  0b0..No swing back cycle has completed since the last time the flag was cleared
47257  *  0b1..At least one swing back cycle has occurred since the last time the flag was cleared
47258  */
47259 #define LPDAC_FSR_SWBK(x)                        (((uint32_t)(((uint32_t)(x)) << LPDAC_FSR_SWBK_SHIFT)) & LPDAC_FSR_SWBK_MASK)
47260 
47261 #define LPDAC_FSR_OF_MASK                        (0x40U)
47262 #define LPDAC_FSR_OF_SHIFT                       (6U)
47263 /*! OF - FIFO Overflow Flag
47264  *  0b0..No overflow has occurred since the last time the flag was cleared
47265  *  0b1..At least one FIFO overflow has occurred since the last time the flag was cleared
47266  */
47267 #define LPDAC_FSR_OF(x)                          (((uint32_t)(((uint32_t)(x)) << LPDAC_FSR_OF_SHIFT)) & LPDAC_FSR_OF_MASK)
47268 
47269 #define LPDAC_FSR_UF_MASK                        (0x80U)
47270 #define LPDAC_FSR_UF_SHIFT                       (7U)
47271 /*! UF - FIFO Underflow Flag
47272  *  0b0..No underflow has occurred since the last time the flag was cleared
47273  *  0b1..At least one trigger underflow has occurred since the last time the flag was cleared
47274  */
47275 #define LPDAC_FSR_UF(x)                          (((uint32_t)(((uint32_t)(x)) << LPDAC_FSR_UF_SHIFT)) & LPDAC_FSR_UF_MASK)
47276 
47277 #define LPDAC_FSR_PTGCOCO_MASK                   (0x100U)
47278 #define LPDAC_FSR_PTGCOCO_SHIFT                  (8U)
47279 /*! PTGCOCO - Period Trigger Mode Conversion Complete Flag
47280  *  0b0..Not completed or not started
47281  *  0b1..Completed
47282  */
47283 #define LPDAC_FSR_PTGCOCO(x)                     (((uint32_t)(((uint32_t)(x)) << LPDAC_FSR_PTGCOCO_SHIFT)) & LPDAC_FSR_PTGCOCO_MASK)
47284 /*! @} */
47285 
47286 /*! @name IER - Interrupt Enable */
47287 /*! @{ */
47288 
47289 #define LPDAC_IER_FULL_IE_MASK                   (0x1U)
47290 #define LPDAC_IER_FULL_IE_SHIFT                  (0U)
47291 /*! FULL_IE - FIFO Full Interrupt Enable
47292  *  0b0..Disables
47293  *  0b1..Enables
47294  */
47295 #define LPDAC_IER_FULL_IE(x)                     (((uint32_t)(((uint32_t)(x)) << LPDAC_IER_FULL_IE_SHIFT)) & LPDAC_IER_FULL_IE_MASK)
47296 
47297 #define LPDAC_IER_EMPTY_IE_MASK                  (0x2U)
47298 #define LPDAC_IER_EMPTY_IE_SHIFT                 (1U)
47299 /*! EMPTY_IE - FIFO Empty Interrupt Enable
47300  *  0b0..Disables
47301  *  0b1..Enables
47302  */
47303 #define LPDAC_IER_EMPTY_IE(x)                    (((uint32_t)(((uint32_t)(x)) << LPDAC_IER_EMPTY_IE_SHIFT)) & LPDAC_IER_EMPTY_IE_MASK)
47304 
47305 #define LPDAC_IER_WM_IE_MASK                     (0x4U)
47306 #define LPDAC_IER_WM_IE_SHIFT                    (2U)
47307 /*! WM_IE - FIFO Watermark Interrupt Enable
47308  *  0b0..Disables
47309  *  0b1..Enables
47310  */
47311 #define LPDAC_IER_WM_IE(x)                       (((uint32_t)(((uint32_t)(x)) << LPDAC_IER_WM_IE_SHIFT)) & LPDAC_IER_WM_IE_MASK)
47312 
47313 #define LPDAC_IER_SWBK_IE_MASK                   (0x8U)
47314 #define LPDAC_IER_SWBK_IE_SHIFT                  (3U)
47315 /*! SWBK_IE - Swing Back One Cycle Complete Interrupt Enable
47316  *  0b0..Disables
47317  *  0b1..Enables
47318  */
47319 #define LPDAC_IER_SWBK_IE(x)                     (((uint32_t)(((uint32_t)(x)) << LPDAC_IER_SWBK_IE_SHIFT)) & LPDAC_IER_SWBK_IE_MASK)
47320 
47321 #define LPDAC_IER_OF_IE_MASK                     (0x40U)
47322 #define LPDAC_IER_OF_IE_SHIFT                    (6U)
47323 /*! OF_IE - FIFO Overflow Interrupt Enable
47324  *  0b0..Disables
47325  *  0b1..Enables
47326  */
47327 #define LPDAC_IER_OF_IE(x)                       (((uint32_t)(((uint32_t)(x)) << LPDAC_IER_OF_IE_SHIFT)) & LPDAC_IER_OF_IE_MASK)
47328 
47329 #define LPDAC_IER_UF_IE_MASK                     (0x80U)
47330 #define LPDAC_IER_UF_IE_SHIFT                    (7U)
47331 /*! UF_IE - FIFO Underflow Interrupt Enable
47332  *  0b0..Disables
47333  *  0b1..Enables
47334  */
47335 #define LPDAC_IER_UF_IE(x)                       (((uint32_t)(((uint32_t)(x)) << LPDAC_IER_UF_IE_SHIFT)) & LPDAC_IER_UF_IE_MASK)
47336 
47337 #define LPDAC_IER_PTGCOCO_IE_MASK                (0x100U)
47338 #define LPDAC_IER_PTGCOCO_IE_SHIFT               (8U)
47339 /*! PTGCOCO_IE - PTG Mode Conversion Complete Interrupt Enable
47340  *  0b0..Disables
47341  *  0b1..Enables
47342  */
47343 #define LPDAC_IER_PTGCOCO_IE(x)                  (((uint32_t)(((uint32_t)(x)) << LPDAC_IER_PTGCOCO_IE_SHIFT)) & LPDAC_IER_PTGCOCO_IE_MASK)
47344 /*! @} */
47345 
47346 /*! @name DER - DMA Enable */
47347 /*! @{ */
47348 
47349 #define LPDAC_DER_EMPTY_DMAEN_MASK               (0x2U)
47350 #define LPDAC_DER_EMPTY_DMAEN_SHIFT              (1U)
47351 /*! EMPTY_DMAEN - FIFO Empty DMA Enable
47352  *  0b0..Disables
47353  *  0b1..Enables
47354  */
47355 #define LPDAC_DER_EMPTY_DMAEN(x)                 (((uint32_t)(((uint32_t)(x)) << LPDAC_DER_EMPTY_DMAEN_SHIFT)) & LPDAC_DER_EMPTY_DMAEN_MASK)
47356 
47357 #define LPDAC_DER_WM_DMAEN_MASK                  (0x4U)
47358 #define LPDAC_DER_WM_DMAEN_SHIFT                 (2U)
47359 /*! WM_DMAEN - FIFO Watermark DMA Enable
47360  *  0b0..Disables
47361  *  0b1..Enables
47362  */
47363 #define LPDAC_DER_WM_DMAEN(x)                    (((uint32_t)(((uint32_t)(x)) << LPDAC_DER_WM_DMAEN_SHIFT)) & LPDAC_DER_WM_DMAEN_MASK)
47364 /*! @} */
47365 
47366 /*! @name RCR - Reset Control */
47367 /*! @{ */
47368 
47369 #define LPDAC_RCR_SWRST_MASK                     (0x1U)
47370 #define LPDAC_RCR_SWRST_SHIFT                    (0U)
47371 /*! SWRST - Software Reset
47372  *  0b0..No effect
47373  *  0b1..Software reset
47374  */
47375 #define LPDAC_RCR_SWRST(x)                       (((uint32_t)(((uint32_t)(x)) << LPDAC_RCR_SWRST_SHIFT)) & LPDAC_RCR_SWRST_MASK)
47376 
47377 #define LPDAC_RCR_FIFORST_MASK                   (0x2U)
47378 #define LPDAC_RCR_FIFORST_SHIFT                  (1U)
47379 /*! FIFORST - FIFO Reset
47380  *  0b0..No effect
47381  *  0b1..FIFO reset
47382  */
47383 #define LPDAC_RCR_FIFORST(x)                     (((uint32_t)(((uint32_t)(x)) << LPDAC_RCR_FIFORST_SHIFT)) & LPDAC_RCR_FIFORST_MASK)
47384 /*! @} */
47385 
47386 /*! @name TCR - Trigger Control */
47387 /*! @{ */
47388 
47389 #define LPDAC_TCR_SWTRG_MASK                     (0x1U)
47390 #define LPDAC_TCR_SWTRG_SHIFT                    (0U)
47391 /*! SWTRG - Software Trigger
47392  *  0b0..Not valid
47393  *  0b1..Valid
47394  */
47395 #define LPDAC_TCR_SWTRG(x)                       (((uint32_t)(((uint32_t)(x)) << LPDAC_TCR_SWTRG_SHIFT)) & LPDAC_TCR_SWTRG_MASK)
47396 /*! @} */
47397 
47398 /*! @name PCR - Periodic Trigger Control */
47399 /*! @{ */
47400 
47401 #define LPDAC_PCR_PTG_NUM_MASK                   (0xFFFFU)
47402 #define LPDAC_PCR_PTG_NUM_SHIFT                  (0U)
47403 /*! PTG_NUM - Periodic Trigger Number */
47404 #define LPDAC_PCR_PTG_NUM(x)                     (((uint32_t)(((uint32_t)(x)) << LPDAC_PCR_PTG_NUM_SHIFT)) & LPDAC_PCR_PTG_NUM_MASK)
47405 
47406 #define LPDAC_PCR_PTG_PERIOD_MASK                (0xFFFF0000U)
47407 #define LPDAC_PCR_PTG_PERIOD_SHIFT               (16U)
47408 /*! PTG_PERIOD - Periodic Trigger Period Width */
47409 #define LPDAC_PCR_PTG_PERIOD(x)                  (((uint32_t)(((uint32_t)(x)) << LPDAC_PCR_PTG_PERIOD_SHIFT)) & LPDAC_PCR_PTG_PERIOD_MASK)
47410 /*! @} */
47411 
47412 
47413 /*!
47414  * @}
47415  */ /* end of group LPDAC_Register_Masks */
47416 
47417 
47418 /* LPDAC - Peripheral instance base addresses */
47419 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
47420   /** Peripheral DAC0 base address */
47421   #define DAC0_BASE                                (0x5010F000u)
47422   /** Peripheral DAC0 base address */
47423   #define DAC0_BASE_NS                             (0x4010F000u)
47424   /** Peripheral DAC0 base pointer */
47425   #define DAC0                                     ((LPDAC_Type *)DAC0_BASE)
47426   /** Peripheral DAC0 base pointer */
47427   #define DAC0_NS                                  ((LPDAC_Type *)DAC0_BASE_NS)
47428   /** Array initializer of LPDAC peripheral base addresses */
47429   #define LPDAC_BASE_ADDRS                         { DAC0_BASE }
47430   /** Array initializer of LPDAC peripheral base pointers */
47431   #define LPDAC_BASE_PTRS                          { DAC0 }
47432   /** Array initializer of LPDAC peripheral base addresses */
47433   #define LPDAC_BASE_ADDRS_NS                      { DAC0_BASE_NS }
47434   /** Array initializer of LPDAC peripheral base pointers */
47435   #define LPDAC_BASE_PTRS_NS                       { DAC0_NS }
47436 #else
47437   /** Peripheral DAC0 base address */
47438   #define DAC0_BASE                                (0x4010F000u)
47439   /** Peripheral DAC0 base pointer */
47440   #define DAC0                                     ((LPDAC_Type *)DAC0_BASE)
47441   /** Array initializer of LPDAC peripheral base addresses */
47442   #define LPDAC_BASE_ADDRS                         { DAC0_BASE }
47443   /** Array initializer of LPDAC peripheral base pointers */
47444   #define LPDAC_BASE_PTRS                          { DAC0 }
47445 #endif
47446 /** Interrupt vectors for the LPDAC peripheral type */
47447 #define LPDAC_IRQS                               { DAC0_IRQn }
47448 
47449 /*!
47450  * @}
47451  */ /* end of group LPDAC_Peripheral_Access_Layer */
47452 
47453 
47454 /* ----------------------------------------------------------------------------
47455    -- LPI2C Peripheral Access Layer
47456    ---------------------------------------------------------------------------- */
47457 
47458 /*!
47459  * @addtogroup LPI2C_Peripheral_Access_Layer LPI2C Peripheral Access Layer
47460  * @{
47461  */
47462 
47463 /** LPI2C - Register Layout Typedef */
47464 typedef struct {
47465   __I  uint32_t VERID;                             /**< Version ID, offset: 0x0 */
47466   __I  uint32_t PARAM;                             /**< Parameter, offset: 0x4 */
47467        uint8_t RESERVED_0[8];
47468   __IO uint32_t MCR;                               /**< Controller Control, offset: 0x10 */
47469   __IO uint32_t MSR;                               /**< Controller Status, offset: 0x14 */
47470   __IO uint32_t MIER;                              /**< Controller Interrupt Enable, offset: 0x18 */
47471   __IO uint32_t MDER;                              /**< Controller DMA Enable, offset: 0x1C */
47472   __IO uint32_t MCFGR0;                            /**< Controller Configuration 0, offset: 0x20 */
47473   __IO uint32_t MCFGR1;                            /**< Controller Configuration 1, offset: 0x24 */
47474   __IO uint32_t MCFGR2;                            /**< Controller Configuration 2, offset: 0x28 */
47475   __IO uint32_t MCFGR3;                            /**< Controller Configuration 3, offset: 0x2C */
47476        uint8_t RESERVED_1[16];
47477   __IO uint32_t MDMR;                              /**< Controller Data Match, offset: 0x40 */
47478        uint8_t RESERVED_2[4];
47479   __IO uint32_t MCCR0;                             /**< Controller Clock Configuration 0, offset: 0x48 */
47480        uint8_t RESERVED_3[4];
47481   __IO uint32_t MCCR1;                             /**< Controller Clock Configuration 1, offset: 0x50 */
47482        uint8_t RESERVED_4[4];
47483   __IO uint32_t MFCR;                              /**< Controller FIFO Control, offset: 0x58 */
47484   __I  uint32_t MFSR;                              /**< Controller FIFO Status, offset: 0x5C */
47485   __O  uint32_t MTDR;                              /**< Controller Transmit Data, offset: 0x60 */
47486        uint8_t RESERVED_5[12];
47487   __I  uint32_t MRDR;                              /**< Controller Receive Data, offset: 0x70 */
47488        uint8_t RESERVED_6[4];
47489   __I  uint32_t MRDROR;                            /**< Controller Receive Data Read Only, offset: 0x78 */
47490        uint8_t RESERVED_7[148];
47491   __IO uint32_t SCR;                               /**< Target Control, offset: 0x110 */
47492   __IO uint32_t SSR;                               /**< Target Status, offset: 0x114 */
47493   __IO uint32_t SIER;                              /**< Target Interrupt Enable, offset: 0x118 */
47494   __IO uint32_t SDER;                              /**< Target DMA Enable, offset: 0x11C */
47495   __IO uint32_t SCFGR0;                            /**< Target Configuration 0, offset: 0x120 */
47496   __IO uint32_t SCFGR1;                            /**< Target Configuration 1, offset: 0x124 */
47497   __IO uint32_t SCFGR2;                            /**< Target Configuration 2, offset: 0x128 */
47498        uint8_t RESERVED_8[20];
47499   __IO uint32_t SAMR;                              /**< Target Address Match, offset: 0x140 */
47500        uint8_t RESERVED_9[12];
47501   __I  uint32_t SASR;                              /**< Target Address Status, offset: 0x150 */
47502   __IO uint32_t STAR;                              /**< Target Transmit ACK, offset: 0x154 */
47503        uint8_t RESERVED_10[8];
47504   __O  uint32_t STDR;                              /**< Target Transmit Data, offset: 0x160 */
47505        uint8_t RESERVED_11[12];
47506   __I  uint32_t SRDR;                              /**< Target Receive Data, offset: 0x170 */
47507        uint8_t RESERVED_12[4];
47508   __I  uint32_t SRDROR;                            /**< Target Receive Data Read Only, offset: 0x178 */
47509        uint8_t RESERVED_13[132];
47510   __O  uint32_t MTCBR[128];                        /**< Controller Transmit Command Burst, array offset: 0x200, array step: 0x4 */
47511   __O  uint32_t MTDBR[253];                        /**< Transmit Data Burst, array offset: 0x400, array step: 0x4 */
47512 } LPI2C_Type;
47513 
47514 /* ----------------------------------------------------------------------------
47515    -- LPI2C Register Masks
47516    ---------------------------------------------------------------------------- */
47517 
47518 /*!
47519  * @addtogroup LPI2C_Register_Masks LPI2C Register Masks
47520  * @{
47521  */
47522 
47523 /*! @name VERID - Version ID */
47524 /*! @{ */
47525 
47526 #define LPI2C_VERID_FEATURE_MASK                 (0xFFFFU)
47527 #define LPI2C_VERID_FEATURE_SHIFT                (0U)
47528 /*! FEATURE - Feature Specification Number
47529  *  0b0000000000000010..Controller only, with standard feature set
47530  *  0b0000000000000011..Controller and target, with standard feature set
47531  */
47532 #define LPI2C_VERID_FEATURE(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK)
47533 
47534 #define LPI2C_VERID_MINOR_MASK                   (0xFF0000U)
47535 #define LPI2C_VERID_MINOR_SHIFT                  (16U)
47536 /*! MINOR - Minor Version Number */
47537 #define LPI2C_VERID_MINOR(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_SHIFT)) & LPI2C_VERID_MINOR_MASK)
47538 
47539 #define LPI2C_VERID_MAJOR_MASK                   (0xFF000000U)
47540 #define LPI2C_VERID_MAJOR_SHIFT                  (24U)
47541 /*! MAJOR - Major Version Number */
47542 #define LPI2C_VERID_MAJOR(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK)
47543 /*! @} */
47544 
47545 /*! @name PARAM - Parameter */
47546 /*! @{ */
47547 
47548 #define LPI2C_PARAM_MTXFIFO_MASK                 (0xFU)
47549 #define LPI2C_PARAM_MTXFIFO_SHIFT                (0U)
47550 /*! MTXFIFO - Controller Transmit FIFO Size */
47551 #define LPI2C_PARAM_MTXFIFO(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK)
47552 
47553 #define LPI2C_PARAM_MRXFIFO_MASK                 (0xF00U)
47554 #define LPI2C_PARAM_MRXFIFO_SHIFT                (8U)
47555 /*! MRXFIFO - Controller Receive FIFO Size */
47556 #define LPI2C_PARAM_MRXFIFO(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK)
47557 /*! @} */
47558 
47559 /*! @name MCR - Controller Control */
47560 /*! @{ */
47561 
47562 #define LPI2C_MCR_MEN_MASK                       (0x1U)
47563 #define LPI2C_MCR_MEN_SHIFT                      (0U)
47564 /*! MEN - Controller Enable
47565  *  0b0..Disable
47566  *  0b1..Enable
47567  */
47568 #define LPI2C_MCR_MEN(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIFT)) & LPI2C_MCR_MEN_MASK)
47569 
47570 #define LPI2C_MCR_RST_MASK                       (0x2U)
47571 #define LPI2C_MCR_RST_SHIFT                      (1U)
47572 /*! RST - Software Reset
47573  *  0b0..No effect
47574  *  0b1..Reset
47575  */
47576 #define LPI2C_MCR_RST(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIFT)) & LPI2C_MCR_RST_MASK)
47577 
47578 #define LPI2C_MCR_DOZEN_MASK                     (0x4U)
47579 #define LPI2C_MCR_DOZEN_SHIFT                    (2U)
47580 /*! DOZEN - Doze Mode Enable
47581  *  0b0..Enable
47582  *  0b1..Disable
47583  */
47584 #define LPI2C_MCR_DOZEN(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SHIFT)) & LPI2C_MCR_DOZEN_MASK)
47585 
47586 #define LPI2C_MCR_DBGEN_MASK                     (0x8U)
47587 #define LPI2C_MCR_DBGEN_SHIFT                    (3U)
47588 /*! DBGEN - Debug Enable
47589  *  0b0..Disable
47590  *  0b1..Enable
47591  */
47592 #define LPI2C_MCR_DBGEN(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SHIFT)) & LPI2C_MCR_DBGEN_MASK)
47593 
47594 #define LPI2C_MCR_RTF_MASK                       (0x100U)
47595 #define LPI2C_MCR_RTF_SHIFT                      (8U)
47596 /*! RTF - Reset Transmit FIFO
47597  *  0b0..No effect
47598  *  0b1..Reset transmit FIFO
47599  */
47600 #define LPI2C_MCR_RTF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIFT)) & LPI2C_MCR_RTF_MASK)
47601 
47602 #define LPI2C_MCR_RRF_MASK                       (0x200U)
47603 #define LPI2C_MCR_RRF_SHIFT                      (9U)
47604 /*! RRF - Reset Receive FIFO
47605  *  0b0..No effect
47606  *  0b1..Reset receive FIFO
47607  */
47608 #define LPI2C_MCR_RRF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RRF_SHIFT)) & LPI2C_MCR_RRF_MASK)
47609 /*! @} */
47610 
47611 /*! @name MSR - Controller Status */
47612 /*! @{ */
47613 
47614 #define LPI2C_MSR_TDF_MASK                       (0x1U)
47615 #define LPI2C_MSR_TDF_SHIFT                      (0U)
47616 /*! TDF - Transmit Data Flag
47617  *  0b0..Transmit data not requested
47618  *  0b1..Transmit data requested
47619  */
47620 #define LPI2C_MSR_TDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_TDF_SHIFT)) & LPI2C_MSR_TDF_MASK)
47621 
47622 #define LPI2C_MSR_RDF_MASK                       (0x2U)
47623 #define LPI2C_MSR_RDF_SHIFT                      (1U)
47624 /*! RDF - Receive Data Flag
47625  *  0b0..Receive data not ready
47626  *  0b1..Receive data ready
47627  */
47628 #define LPI2C_MSR_RDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_RDF_SHIFT)) & LPI2C_MSR_RDF_MASK)
47629 
47630 #define LPI2C_MSR_EPF_MASK                       (0x100U)
47631 #define LPI2C_MSR_EPF_SHIFT                      (8U)
47632 /*! EPF - End Packet Flag
47633  *  0b0..No Stop or repeated Start generated
47634  *  0b1..Stop or repeated Start generated
47635  *  0b0..No effect
47636  *  0b1..Clear the flag
47637  */
47638 #define LPI2C_MSR_EPF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIFT)) & LPI2C_MSR_EPF_MASK)
47639 
47640 #define LPI2C_MSR_SDF_MASK                       (0x200U)
47641 #define LPI2C_MSR_SDF_SHIFT                      (9U)
47642 /*! SDF - Stop Detect Flag
47643  *  0b0..No Stop condition generated
47644  *  0b1..Stop condition generated
47645  *  0b0..No effect
47646  *  0b1..Clear the flag
47647  */
47648 #define LPI2C_MSR_SDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIFT)) & LPI2C_MSR_SDF_MASK)
47649 
47650 #define LPI2C_MSR_NDF_MASK                       (0x400U)
47651 #define LPI2C_MSR_NDF_SHIFT                      (10U)
47652 /*! NDF - NACK Detect Flag
47653  *  0b0..No unexpected NACK detected
47654  *  0b1..Unexpected NACK detected
47655  *  0b0..No effect
47656  *  0b1..Clear the flag
47657  */
47658 #define LPI2C_MSR_NDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIFT)) & LPI2C_MSR_NDF_MASK)
47659 
47660 #define LPI2C_MSR_ALF_MASK                       (0x800U)
47661 #define LPI2C_MSR_ALF_SHIFT                      (11U)
47662 /*! ALF - Arbitration Lost Flag
47663  *  0b0..Controller did not lose arbitration
47664  *  0b1..Controller lost arbitration
47665  *  0b0..No effect
47666  *  0b1..Clear the flag
47667  */
47668 #define LPI2C_MSR_ALF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIFT)) & LPI2C_MSR_ALF_MASK)
47669 
47670 #define LPI2C_MSR_FEF_MASK                       (0x1000U)
47671 #define LPI2C_MSR_FEF_SHIFT                      (12U)
47672 /*! FEF - FIFO Error Flag
47673  *  0b0..No FIFO error
47674  *  0b1..FIFO error
47675  *  0b0..No effect
47676  *  0b1..Clear the flag
47677  */
47678 #define LPI2C_MSR_FEF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_FEF_SHIFT)) & LPI2C_MSR_FEF_MASK)
47679 
47680 #define LPI2C_MSR_PLTF_MASK                      (0x2000U)
47681 #define LPI2C_MSR_PLTF_SHIFT                     (13U)
47682 /*! PLTF - Pin Low Timeout Flag
47683  *  0b0..Pin low timeout did not occur
47684  *  0b1..Pin low timeout occurred
47685  *  0b0..No effect
47686  *  0b1..Clear the flag
47687  */
47688 #define LPI2C_MSR_PLTF(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_PLTF_SHIFT)) & LPI2C_MSR_PLTF_MASK)
47689 
47690 #define LPI2C_MSR_DMF_MASK                       (0x4000U)
47691 #define LPI2C_MSR_DMF_SHIFT                      (14U)
47692 /*! DMF - Data Match Flag
47693  *  0b0..Matching data not received
47694  *  0b1..Matching data received
47695  *  0b0..No effect
47696  *  0b1..Clear the flag
47697  */
47698 #define LPI2C_MSR_DMF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_DMF_SHIFT)) & LPI2C_MSR_DMF_MASK)
47699 
47700 #define LPI2C_MSR_STF_MASK                       (0x8000U)
47701 #define LPI2C_MSR_STF_SHIFT                      (15U)
47702 /*! STF - Start Flag
47703  *  0b0..Start condition not detected
47704  *  0b1..Start condition detected
47705  *  0b0..No effect
47706  *  0b1..Clear the flag
47707  */
47708 #define LPI2C_MSR_STF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_STF_SHIFT)) & LPI2C_MSR_STF_MASK)
47709 
47710 #define LPI2C_MSR_MBF_MASK                       (0x1000000U)
47711 #define LPI2C_MSR_MBF_SHIFT                      (24U)
47712 /*! MBF - Controller Busy Flag
47713  *  0b0..Idle
47714  *  0b1..Busy
47715  */
47716 #define LPI2C_MSR_MBF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_MBF_SHIFT)) & LPI2C_MSR_MBF_MASK)
47717 
47718 #define LPI2C_MSR_BBF_MASK                       (0x2000000U)
47719 #define LPI2C_MSR_BBF_SHIFT                      (25U)
47720 /*! BBF - Bus Busy Flag
47721  *  0b0..Idle
47722  *  0b1..Busy
47723  */
47724 #define LPI2C_MSR_BBF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_BBF_SHIFT)) & LPI2C_MSR_BBF_MASK)
47725 /*! @} */
47726 
47727 /*! @name MIER - Controller Interrupt Enable */
47728 /*! @{ */
47729 
47730 #define LPI2C_MIER_TDIE_MASK                     (0x1U)
47731 #define LPI2C_MIER_TDIE_SHIFT                    (0U)
47732 /*! TDIE - Transmit Data Interrupt Enable
47733  *  0b0..Disable
47734  *  0b1..Enable
47735  */
47736 #define LPI2C_MIER_TDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_TDIE_SHIFT)) & LPI2C_MIER_TDIE_MASK)
47737 
47738 #define LPI2C_MIER_RDIE_MASK                     (0x2U)
47739 #define LPI2C_MIER_RDIE_SHIFT                    (1U)
47740 /*! RDIE - Receive Data Interrupt Enable
47741  *  0b0..Disable
47742  *  0b1..Enable
47743  */
47744 #define LPI2C_MIER_RDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_RDIE_SHIFT)) & LPI2C_MIER_RDIE_MASK)
47745 
47746 #define LPI2C_MIER_EPIE_MASK                     (0x100U)
47747 #define LPI2C_MIER_EPIE_SHIFT                    (8U)
47748 /*! EPIE - End Packet Interrupt Enable
47749  *  0b0..Disable
47750  *  0b1..Enable
47751  */
47752 #define LPI2C_MIER_EPIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_EPIE_SHIFT)) & LPI2C_MIER_EPIE_MASK)
47753 
47754 #define LPI2C_MIER_SDIE_MASK                     (0x200U)
47755 #define LPI2C_MIER_SDIE_SHIFT                    (9U)
47756 /*! SDIE - Stop Detect Interrupt Enable
47757  *  0b0..Disable
47758  *  0b1..Enable
47759  */
47760 #define LPI2C_MIER_SDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_SDIE_SHIFT)) & LPI2C_MIER_SDIE_MASK)
47761 
47762 #define LPI2C_MIER_NDIE_MASK                     (0x400U)
47763 #define LPI2C_MIER_NDIE_SHIFT                    (10U)
47764 /*! NDIE - NACK Detect Interrupt Enable
47765  *  0b0..Disable
47766  *  0b1..Enable
47767  */
47768 #define LPI2C_MIER_NDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_NDIE_SHIFT)) & LPI2C_MIER_NDIE_MASK)
47769 
47770 #define LPI2C_MIER_ALIE_MASK                     (0x800U)
47771 #define LPI2C_MIER_ALIE_SHIFT                    (11U)
47772 /*! ALIE - Arbitration Lost Interrupt Enable
47773  *  0b0..Disable
47774  *  0b1..Enable
47775  */
47776 #define LPI2C_MIER_ALIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_ALIE_SHIFT)) & LPI2C_MIER_ALIE_MASK)
47777 
47778 #define LPI2C_MIER_FEIE_MASK                     (0x1000U)
47779 #define LPI2C_MIER_FEIE_SHIFT                    (12U)
47780 /*! FEIE - FIFO Error Interrupt Enable
47781  *  0b0..Disable
47782  *  0b1..Enable
47783  */
47784 #define LPI2C_MIER_FEIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_FEIE_SHIFT)) & LPI2C_MIER_FEIE_MASK)
47785 
47786 #define LPI2C_MIER_PLTIE_MASK                    (0x2000U)
47787 #define LPI2C_MIER_PLTIE_SHIFT                   (13U)
47788 /*! PLTIE - Pin Low Timeout Interrupt Enable
47789  *  0b0..Disable
47790  *  0b1..Enable
47791  */
47792 #define LPI2C_MIER_PLTIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_PLTIE_SHIFT)) & LPI2C_MIER_PLTIE_MASK)
47793 
47794 #define LPI2C_MIER_DMIE_MASK                     (0x4000U)
47795 #define LPI2C_MIER_DMIE_SHIFT                    (14U)
47796 /*! DMIE - Data Match Interrupt Enable
47797  *  0b0..Disable
47798  *  0b1..Enable
47799  */
47800 #define LPI2C_MIER_DMIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_DMIE_SHIFT)) & LPI2C_MIER_DMIE_MASK)
47801 
47802 #define LPI2C_MIER_STIE_MASK                     (0x8000U)
47803 #define LPI2C_MIER_STIE_SHIFT                    (15U)
47804 /*! STIE - Start Interrupt Enable
47805  *  0b0..Disable
47806  *  0b1..Enable
47807  */
47808 #define LPI2C_MIER_STIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_STIE_SHIFT)) & LPI2C_MIER_STIE_MASK)
47809 /*! @} */
47810 
47811 /*! @name MDER - Controller DMA Enable */
47812 /*! @{ */
47813 
47814 #define LPI2C_MDER_TDDE_MASK                     (0x1U)
47815 #define LPI2C_MDER_TDDE_SHIFT                    (0U)
47816 /*! TDDE - Transmit Data DMA Enable
47817  *  0b0..Disable
47818  *  0b1..Enable
47819  */
47820 #define LPI2C_MDER_TDDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_TDDE_SHIFT)) & LPI2C_MDER_TDDE_MASK)
47821 
47822 #define LPI2C_MDER_RDDE_MASK                     (0x2U)
47823 #define LPI2C_MDER_RDDE_SHIFT                    (1U)
47824 /*! RDDE - Receive Data DMA Enable
47825  *  0b0..Disable
47826  *  0b1..Enable
47827  */
47828 #define LPI2C_MDER_RDDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_RDDE_SHIFT)) & LPI2C_MDER_RDDE_MASK)
47829 /*! @} */
47830 
47831 /*! @name MCFGR0 - Controller Configuration 0 */
47832 /*! @{ */
47833 
47834 #define LPI2C_MCFGR0_HREN_MASK                   (0x1U)
47835 #define LPI2C_MCFGR0_HREN_SHIFT                  (0U)
47836 /*! HREN - Host Request Enable
47837  *  0b0..Disable
47838  *  0b1..Enable
47839  */
47840 #define LPI2C_MCFGR0_HREN(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HREN_SHIFT)) & LPI2C_MCFGR0_HREN_MASK)
47841 
47842 #define LPI2C_MCFGR0_HRPOL_MASK                  (0x2U)
47843 #define LPI2C_MCFGR0_HRPOL_SHIFT                 (1U)
47844 /*! HRPOL - Host Request Polarity
47845  *  0b0..Active low
47846  *  0b1..Active high
47847  */
47848 #define LPI2C_MCFGR0_HRPOL(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRPOL_SHIFT)) & LPI2C_MCFGR0_HRPOL_MASK)
47849 
47850 #define LPI2C_MCFGR0_HRSEL_MASK                  (0x4U)
47851 #define LPI2C_MCFGR0_HRSEL_SHIFT                 (2U)
47852 /*! HRSEL - Host Request Select
47853  *  0b0..Host request input is pin HREQ
47854  *  0b1..Host request input is input trigger
47855  */
47856 #define LPI2C_MCFGR0_HRSEL(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRSEL_SHIFT)) & LPI2C_MCFGR0_HRSEL_MASK)
47857 
47858 #define LPI2C_MCFGR0_HRDIR_MASK                  (0x8U)
47859 #define LPI2C_MCFGR0_HRDIR_SHIFT                 (3U)
47860 /*! HRDIR - Host Request Direction
47861  *  0b0..HREQ pin is input (for LPI2C controller)
47862  *  0b1..HREQ pin is output (for LPI2C target)
47863  */
47864 #define LPI2C_MCFGR0_HRDIR(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRDIR_SHIFT)) & LPI2C_MCFGR0_HRDIR_MASK)
47865 
47866 #define LPI2C_MCFGR0_CIRFIFO_MASK                (0x100U)
47867 #define LPI2C_MCFGR0_CIRFIFO_SHIFT               (8U)
47868 /*! CIRFIFO - Circular FIFO Enable
47869  *  0b0..Disable
47870  *  0b1..Enable
47871  */
47872 #define LPI2C_MCFGR0_CIRFIFO(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_CIRFIFO_SHIFT)) & LPI2C_MCFGR0_CIRFIFO_MASK)
47873 
47874 #define LPI2C_MCFGR0_RDMO_MASK                   (0x200U)
47875 #define LPI2C_MCFGR0_RDMO_SHIFT                  (9U)
47876 /*! RDMO - Receive Data Match Only
47877  *  0b0..Received data is stored in the receive FIFO
47878  *  0b1..Received data is discarded unless MSR[DMF] is set
47879  */
47880 #define LPI2C_MCFGR0_RDMO(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RDMO_SHIFT)) & LPI2C_MCFGR0_RDMO_MASK)
47881 
47882 #define LPI2C_MCFGR0_RELAX_MASK                  (0x10000U)
47883 #define LPI2C_MCFGR0_RELAX_SHIFT                 (16U)
47884 /*! RELAX - Relaxed Mode
47885  *  0b0..Normal transfer
47886  *  0b1..Relaxed transfer
47887  */
47888 #define LPI2C_MCFGR0_RELAX(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RELAX_SHIFT)) & LPI2C_MCFGR0_RELAX_MASK)
47889 
47890 #define LPI2C_MCFGR0_ABORT_MASK                  (0x20000U)
47891 #define LPI2C_MCFGR0_ABORT_SHIFT                 (17U)
47892 /*! ABORT - Abort Transfer
47893  *  0b0..Normal transfer
47894  *  0b1..Abort existing transfer and do not start a new one
47895  */
47896 #define LPI2C_MCFGR0_ABORT(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_ABORT_SHIFT)) & LPI2C_MCFGR0_ABORT_MASK)
47897 /*! @} */
47898 
47899 /*! @name MCFGR1 - Controller Configuration 1 */
47900 /*! @{ */
47901 
47902 #define LPI2C_MCFGR1_PRESCALE_MASK               (0x7U)
47903 #define LPI2C_MCFGR1_PRESCALE_SHIFT              (0U)
47904 /*! PRESCALE - Prescaler
47905  *  0b000..Divide by 1
47906  *  0b001..Divide by 2
47907  *  0b010..Divide by 4
47908  *  0b011..Divide by 8
47909  *  0b100..Divide by 16
47910  *  0b101..Divide by 32
47911  *  0b110..Divide by 64
47912  *  0b111..Divide by 128
47913  */
47914 #define LPI2C_MCFGR1_PRESCALE(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PRESCALE_SHIFT)) & LPI2C_MCFGR1_PRESCALE_MASK)
47915 
47916 #define LPI2C_MCFGR1_AUTOSTOP_MASK               (0x100U)
47917 #define LPI2C_MCFGR1_AUTOSTOP_SHIFT              (8U)
47918 /*! AUTOSTOP - Automatic Stop Generation
47919  *  0b0..No effect
47920  *  0b1..Stop automatically generated
47921  */
47922 #define LPI2C_MCFGR1_AUTOSTOP(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_AUTOSTOP_SHIFT)) & LPI2C_MCFGR1_AUTOSTOP_MASK)
47923 
47924 #define LPI2C_MCFGR1_IGNACK_MASK                 (0x200U)
47925 #define LPI2C_MCFGR1_IGNACK_SHIFT                (9U)
47926 /*! IGNACK - Ignore NACK
47927  *  0b0..No effect
47928  *  0b1..Treat a received NACK as an ACK
47929  */
47930 #define LPI2C_MCFGR1_IGNACK(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_IGNACK_SHIFT)) & LPI2C_MCFGR1_IGNACK_MASK)
47931 
47932 #define LPI2C_MCFGR1_TIMECFG_MASK                (0x400U)
47933 #define LPI2C_MCFGR1_TIMECFG_SHIFT               (10U)
47934 /*! TIMECFG - Timeout Configuration
47935  *  0b0..SCL
47936  *  0b1..SCL or SDA
47937  */
47938 #define LPI2C_MCFGR1_TIMECFG(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_TIMECFG_SHIFT)) & LPI2C_MCFGR1_TIMECFG_MASK)
47939 
47940 #define LPI2C_MCFGR1_STOPCFG_MASK                (0x800U)
47941 #define LPI2C_MCFGR1_STOPCFG_SHIFT               (11U)
47942 /*! STOPCFG - Stop Configuration
47943  *  0b0..Any Stop condition
47944  *  0b1..Last Stop condition
47945  */
47946 #define LPI2C_MCFGR1_STOPCFG(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_STOPCFG_SHIFT)) & LPI2C_MCFGR1_STOPCFG_MASK)
47947 
47948 #define LPI2C_MCFGR1_STARTCFG_MASK               (0x1000U)
47949 #define LPI2C_MCFGR1_STARTCFG_SHIFT              (12U)
47950 /*! STARTCFG - Start Configuration
47951  *  0b0..Sets when both I2C bus and LPI2C controller are idle
47952  *  0b1..Sets when I2C bus is idle
47953  */
47954 #define LPI2C_MCFGR1_STARTCFG(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_STARTCFG_SHIFT)) & LPI2C_MCFGR1_STARTCFG_MASK)
47955 
47956 #define LPI2C_MCFGR1_MATCFG_MASK                 (0x70000U)
47957 #define LPI2C_MCFGR1_MATCFG_SHIFT                (16U)
47958 /*! MATCFG - Match Configuration
47959  *  0b000..Match is disabled
47960  *  0b001..Reserved
47961  *  0b010..Match is enabled: first data word equals MDMR[MATCH0] OR MDMR[MATCH1]
47962  *  0b011..Match is enabled: any data word equals MDMR[MATCH0] OR MDMR[MATCH1]
47963  *  0b100..Match is enabled: (first data word equals MDMR[MATCH0]) AND (second data word equals MDMR[MATCH1)
47964  *  0b101..Match is enabled: (any data word equals MDMR[MATCH0]) AND (next data word equals MDMR[MATCH1)
47965  *  0b110..Match is enabled: (first data word AND MDMR[MATCH1]) equals (MDMR[MATCH0] AND MDMR[MATCH1])
47966  *  0b111..Match is enabled: (any data word AND MDMR[MATCH1]) equals (MDMR[MATCH0] AND MDMR[MATCH1])
47967  */
47968 #define LPI2C_MCFGR1_MATCFG(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_MATCFG_SHIFT)) & LPI2C_MCFGR1_MATCFG_MASK)
47969 
47970 #define LPI2C_MCFGR1_PINCFG_MASK                 (0x7000000U)
47971 #define LPI2C_MCFGR1_PINCFG_SHIFT                (24U)
47972 /*! PINCFG - Pin Configuration
47973  *  0b000..Two-pin open drain mode
47974  *  0b001..Two-pin output only mode (Ultra-Fast mode)
47975  *  0b010..Two-pin push-pull mode
47976  *  0b011..Four-pin push-pull mode
47977  *  0b100..Two-pin open-drain mode with separate LPI2C target
47978  *  0b101..Two-pin output only mode (Ultra-Fast mode) with separate LPI2C target
47979  *  0b110..Two-pin push-pull mode with separate LPI2C target
47980  *  0b111..Four-pin push-pull mode (inverted outputs)
47981  */
47982 #define LPI2C_MCFGR1_PINCFG(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PINCFG_SHIFT)) & LPI2C_MCFGR1_PINCFG_MASK)
47983 /*! @} */
47984 
47985 /*! @name MCFGR2 - Controller Configuration 2 */
47986 /*! @{ */
47987 
47988 #define LPI2C_MCFGR2_BUSIDLE_MASK                (0xFFFU)
47989 #define LPI2C_MCFGR2_BUSIDLE_SHIFT               (0U)
47990 /*! BUSIDLE - Bus Idle Timeout */
47991 #define LPI2C_MCFGR2_BUSIDLE(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_BUSIDLE_SHIFT)) & LPI2C_MCFGR2_BUSIDLE_MASK)
47992 
47993 #define LPI2C_MCFGR2_FILTSCL_MASK                (0xF0000U)
47994 #define LPI2C_MCFGR2_FILTSCL_SHIFT               (16U)
47995 /*! FILTSCL - Glitch Filter SCL */
47996 #define LPI2C_MCFGR2_FILTSCL(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSCL_SHIFT)) & LPI2C_MCFGR2_FILTSCL_MASK)
47997 
47998 #define LPI2C_MCFGR2_FILTSDA_MASK                (0xF000000U)
47999 #define LPI2C_MCFGR2_FILTSDA_SHIFT               (24U)
48000 /*! FILTSDA - Glitch Filter SDA */
48001 #define LPI2C_MCFGR2_FILTSDA(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSDA_SHIFT)) & LPI2C_MCFGR2_FILTSDA_MASK)
48002 /*! @} */
48003 
48004 /*! @name MCFGR3 - Controller Configuration 3 */
48005 /*! @{ */
48006 
48007 #define LPI2C_MCFGR3_PINLOW_MASK                 (0xFFF00U)
48008 #define LPI2C_MCFGR3_PINLOW_SHIFT                (8U)
48009 /*! PINLOW - Pin Low Timeout */
48010 #define LPI2C_MCFGR3_PINLOW(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR3_PINLOW_SHIFT)) & LPI2C_MCFGR3_PINLOW_MASK)
48011 /*! @} */
48012 
48013 /*! @name MDMR - Controller Data Match */
48014 /*! @{ */
48015 
48016 #define LPI2C_MDMR_MATCH0_MASK                   (0xFFU)
48017 #define LPI2C_MDMR_MATCH0_SHIFT                  (0U)
48018 /*! MATCH0 - Match 0 Value */
48019 #define LPI2C_MDMR_MATCH0(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH0_SHIFT)) & LPI2C_MDMR_MATCH0_MASK)
48020 
48021 #define LPI2C_MDMR_MATCH1_MASK                   (0xFF0000U)
48022 #define LPI2C_MDMR_MATCH1_SHIFT                  (16U)
48023 /*! MATCH1 - Match 1 Value */
48024 #define LPI2C_MDMR_MATCH1(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH1_SHIFT)) & LPI2C_MDMR_MATCH1_MASK)
48025 /*! @} */
48026 
48027 /*! @name MCCR0 - Controller Clock Configuration 0 */
48028 /*! @{ */
48029 
48030 #define LPI2C_MCCR0_CLKLO_MASK                   (0x3FU)
48031 #define LPI2C_MCCR0_CLKLO_SHIFT                  (0U)
48032 /*! CLKLO - Clock Low Period */
48033 #define LPI2C_MCCR0_CLKLO(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKLO_SHIFT)) & LPI2C_MCCR0_CLKLO_MASK)
48034 
48035 #define LPI2C_MCCR0_CLKHI_MASK                   (0x3F00U)
48036 #define LPI2C_MCCR0_CLKHI_SHIFT                  (8U)
48037 /*! CLKHI - Clock High Period */
48038 #define LPI2C_MCCR0_CLKHI(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKHI_SHIFT)) & LPI2C_MCCR0_CLKHI_MASK)
48039 
48040 #define LPI2C_MCCR0_SETHOLD_MASK                 (0x3F0000U)
48041 #define LPI2C_MCCR0_SETHOLD_SHIFT                (16U)
48042 /*! SETHOLD - Setup Hold Delay */
48043 #define LPI2C_MCCR0_SETHOLD(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_SETHOLD_SHIFT)) & LPI2C_MCCR0_SETHOLD_MASK)
48044 
48045 #define LPI2C_MCCR0_DATAVD_MASK                  (0x3F000000U)
48046 #define LPI2C_MCCR0_DATAVD_SHIFT                 (24U)
48047 /*! DATAVD - Data Valid Delay */
48048 #define LPI2C_MCCR0_DATAVD(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_DATAVD_SHIFT)) & LPI2C_MCCR0_DATAVD_MASK)
48049 /*! @} */
48050 
48051 /*! @name MCCR1 - Controller Clock Configuration 1 */
48052 /*! @{ */
48053 
48054 #define LPI2C_MCCR1_CLKLO_MASK                   (0x3FU)
48055 #define LPI2C_MCCR1_CLKLO_SHIFT                  (0U)
48056 /*! CLKLO - Clock Low Period */
48057 #define LPI2C_MCCR1_CLKLO(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKLO_SHIFT)) & LPI2C_MCCR1_CLKLO_MASK)
48058 
48059 #define LPI2C_MCCR1_CLKHI_MASK                   (0x3F00U)
48060 #define LPI2C_MCCR1_CLKHI_SHIFT                  (8U)
48061 /*! CLKHI - Clock High Period */
48062 #define LPI2C_MCCR1_CLKHI(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKHI_SHIFT)) & LPI2C_MCCR1_CLKHI_MASK)
48063 
48064 #define LPI2C_MCCR1_SETHOLD_MASK                 (0x3F0000U)
48065 #define LPI2C_MCCR1_SETHOLD_SHIFT                (16U)
48066 /*! SETHOLD - Setup Hold Delay */
48067 #define LPI2C_MCCR1_SETHOLD(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_SETHOLD_SHIFT)) & LPI2C_MCCR1_SETHOLD_MASK)
48068 
48069 #define LPI2C_MCCR1_DATAVD_MASK                  (0x3F000000U)
48070 #define LPI2C_MCCR1_DATAVD_SHIFT                 (24U)
48071 /*! DATAVD - Data Valid Delay */
48072 #define LPI2C_MCCR1_DATAVD(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_DATAVD_SHIFT)) & LPI2C_MCCR1_DATAVD_MASK)
48073 /*! @} */
48074 
48075 /*! @name MFCR - Controller FIFO Control */
48076 /*! @{ */
48077 
48078 #define LPI2C_MFCR_TXWATER_MASK                  (0x7U)
48079 #define LPI2C_MFCR_TXWATER_SHIFT                 (0U)
48080 /*! TXWATER - Transmit FIFO Watermark */
48081 #define LPI2C_MFCR_TXWATER(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_TXWATER_SHIFT)) & LPI2C_MFCR_TXWATER_MASK)
48082 
48083 #define LPI2C_MFCR_RXWATER_MASK                  (0x70000U)
48084 #define LPI2C_MFCR_RXWATER_SHIFT                 (16U)
48085 /*! RXWATER - Receive FIFO Watermark */
48086 #define LPI2C_MFCR_RXWATER(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_RXWATER_SHIFT)) & LPI2C_MFCR_RXWATER_MASK)
48087 /*! @} */
48088 
48089 /*! @name MFSR - Controller FIFO Status */
48090 /*! @{ */
48091 
48092 #define LPI2C_MFSR_TXCOUNT_MASK                  (0xFU)
48093 #define LPI2C_MFSR_TXCOUNT_SHIFT                 (0U)
48094 /*! TXCOUNT - Transmit FIFO Count */
48095 #define LPI2C_MFSR_TXCOUNT(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_TXCOUNT_SHIFT)) & LPI2C_MFSR_TXCOUNT_MASK)
48096 
48097 #define LPI2C_MFSR_RXCOUNT_MASK                  (0xF0000U)
48098 #define LPI2C_MFSR_RXCOUNT_SHIFT                 (16U)
48099 /*! RXCOUNT - Receive FIFO Count */
48100 #define LPI2C_MFSR_RXCOUNT(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_RXCOUNT_SHIFT)) & LPI2C_MFSR_RXCOUNT_MASK)
48101 /*! @} */
48102 
48103 /*! @name MTDR - Controller Transmit Data */
48104 /*! @{ */
48105 
48106 #define LPI2C_MTDR_DATA_MASK                     (0xFFU)
48107 #define LPI2C_MTDR_DATA_SHIFT                    (0U)
48108 /*! DATA - Transmit Data */
48109 #define LPI2C_MTDR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_DATA_SHIFT)) & LPI2C_MTDR_DATA_MASK)
48110 
48111 #define LPI2C_MTDR_CMD_MASK                      (0x700U)
48112 #define LPI2C_MTDR_CMD_SHIFT                     (8U)
48113 /*! CMD - Command Data
48114  *  0b000..Transmit the value in DATA[7:0]
48115  *  0b001..Receive (DATA[7:0] + 1) bytes
48116  *  0b010..Generate Stop condition on I2C bus
48117  *  0b011..Receive and discard (DATA[7:0] + 1) bytes
48118  *  0b100..Generate (repeated) Start on the I2C bus and transmit the address in DATA[7:0]
48119  *  0b101..Generate (repeated) Start on the I2C bus and transmit the address in DATA[7:0] (this transfer expects a NACK to be returned)
48120  *  0b110..Generate (repeated) Start on the I2C bus and transmit the address in DATA[7:0] using HS mode
48121  *  0b111..Generate (repeated) Start on the I2C bus and transmit the address in DATA[7:0] using HS mode (this transfer expects a NACK to be returned)
48122  */
48123 #define LPI2C_MTDR_CMD(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_CMD_SHIFT)) & LPI2C_MTDR_CMD_MASK)
48124 /*! @} */
48125 
48126 /*! @name MRDR - Controller Receive Data */
48127 /*! @{ */
48128 
48129 #define LPI2C_MRDR_DATA_MASK                     (0xFFU)
48130 #define LPI2C_MRDR_DATA_SHIFT                    (0U)
48131 /*! DATA - Receive Data */
48132 #define LPI2C_MRDR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_DATA_SHIFT)) & LPI2C_MRDR_DATA_MASK)
48133 
48134 #define LPI2C_MRDR_RXEMPTY_MASK                  (0x4000U)
48135 #define LPI2C_MRDR_RXEMPTY_SHIFT                 (14U)
48136 /*! RXEMPTY - Receive Empty
48137  *  0b0..Not empty
48138  *  0b1..Empty
48139  */
48140 #define LPI2C_MRDR_RXEMPTY(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_RXEMPTY_SHIFT)) & LPI2C_MRDR_RXEMPTY_MASK)
48141 /*! @} */
48142 
48143 /*! @name MRDROR - Controller Receive Data Read Only */
48144 /*! @{ */
48145 
48146 #define LPI2C_MRDROR_DATA_MASK                   (0xFFU)
48147 #define LPI2C_MRDROR_DATA_SHIFT                  (0U)
48148 /*! DATA - Receive Data */
48149 #define LPI2C_MRDROR_DATA(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDROR_DATA_SHIFT)) & LPI2C_MRDROR_DATA_MASK)
48150 
48151 #define LPI2C_MRDROR_RXEMPTY_MASK                (0x4000U)
48152 #define LPI2C_MRDROR_RXEMPTY_SHIFT               (14U)
48153 /*! RXEMPTY - RX Empty
48154  *  0b0..Not empty
48155  *  0b1..Empty
48156  */
48157 #define LPI2C_MRDROR_RXEMPTY(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDROR_RXEMPTY_SHIFT)) & LPI2C_MRDROR_RXEMPTY_MASK)
48158 /*! @} */
48159 
48160 /*! @name SCR - Target Control */
48161 /*! @{ */
48162 
48163 #define LPI2C_SCR_SEN_MASK                       (0x1U)
48164 #define LPI2C_SCR_SEN_SHIFT                      (0U)
48165 /*! SEN - Target Enable
48166  *  0b0..Disable
48167  *  0b1..Enable
48168  */
48169 #define LPI2C_SCR_SEN(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_SEN_SHIFT)) & LPI2C_SCR_SEN_MASK)
48170 
48171 #define LPI2C_SCR_RST_MASK                       (0x2U)
48172 #define LPI2C_SCR_RST_SHIFT                      (1U)
48173 /*! RST - Software Reset
48174  *  0b0..Not reset
48175  *  0b1..Reset
48176  */
48177 #define LPI2C_SCR_RST(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RST_SHIFT)) & LPI2C_SCR_RST_MASK)
48178 
48179 #define LPI2C_SCR_FILTEN_MASK                    (0x10U)
48180 #define LPI2C_SCR_FILTEN_SHIFT                   (4U)
48181 /*! FILTEN - Filter Enable
48182  *  0b0..Disable
48183  *  0b1..Enable
48184  */
48185 #define LPI2C_SCR_FILTEN(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTEN_SHIFT)) & LPI2C_SCR_FILTEN_MASK)
48186 
48187 #define LPI2C_SCR_FILTDZ_MASK                    (0x20U)
48188 #define LPI2C_SCR_FILTDZ_SHIFT                   (5U)
48189 /*! FILTDZ - Filter Doze Enable
48190  *  0b0..Enable
48191  *  0b1..Disable
48192  */
48193 #define LPI2C_SCR_FILTDZ(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTDZ_SHIFT)) & LPI2C_SCR_FILTDZ_MASK)
48194 
48195 #define LPI2C_SCR_RTF_MASK                       (0x100U)
48196 #define LPI2C_SCR_RTF_SHIFT                      (8U)
48197 /*! RTF - Reset Transmit FIFO
48198  *  0b0..No effect
48199  *  0b1..STDR is now empty
48200  */
48201 #define LPI2C_SCR_RTF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RTF_SHIFT)) & LPI2C_SCR_RTF_MASK)
48202 
48203 #define LPI2C_SCR_RRF_MASK                       (0x200U)
48204 #define LPI2C_SCR_RRF_SHIFT                      (9U)
48205 /*! RRF - Reset Receive FIFO
48206  *  0b0..No effect
48207  *  0b1..SRDR is now empty
48208  */
48209 #define LPI2C_SCR_RRF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RRF_SHIFT)) & LPI2C_SCR_RRF_MASK)
48210 /*! @} */
48211 
48212 /*! @name SSR - Target Status */
48213 /*! @{ */
48214 
48215 #define LPI2C_SSR_TDF_MASK                       (0x1U)
48216 #define LPI2C_SSR_TDF_SHIFT                      (0U)
48217 /*! TDF - Transmit Data Flag
48218  *  0b0..Transmit data not requested
48219  *  0b1..Transmit data is requested
48220  */
48221 #define LPI2C_SSR_TDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TDF_SHIFT)) & LPI2C_SSR_TDF_MASK)
48222 
48223 #define LPI2C_SSR_RDF_MASK                       (0x2U)
48224 #define LPI2C_SSR_RDF_SHIFT                      (1U)
48225 /*! RDF - Receive Data Flag
48226  *  0b0..Not ready
48227  *  0b1..Ready
48228  */
48229 #define LPI2C_SSR_RDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RDF_SHIFT)) & LPI2C_SSR_RDF_MASK)
48230 
48231 #define LPI2C_SSR_AVF_MASK                       (0x4U)
48232 #define LPI2C_SSR_AVF_SHIFT                      (2U)
48233 /*! AVF - Address Valid Flag
48234  *  0b0..Not valid
48235  *  0b1..Valid
48236  */
48237 #define LPI2C_SSR_AVF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AVF_SHIFT)) & LPI2C_SSR_AVF_MASK)
48238 
48239 #define LPI2C_SSR_TAF_MASK                       (0x8U)
48240 #define LPI2C_SSR_TAF_SHIFT                      (3U)
48241 /*! TAF - Transmit ACK Flag
48242  *  0b0..Not required
48243  *  0b1..Required
48244  */
48245 #define LPI2C_SSR_TAF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TAF_SHIFT)) & LPI2C_SSR_TAF_MASK)
48246 
48247 #define LPI2C_SSR_RSF_MASK                       (0x100U)
48248 #define LPI2C_SSR_RSF_SHIFT                      (8U)
48249 /*! RSF - Repeated Start Flag
48250  *  0b0..No repeated Start detected
48251  *  0b1..Repeated Start detected
48252  *  0b0..No effect
48253  *  0b1..Clear the flag
48254  */
48255 #define LPI2C_SSR_RSF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RSF_SHIFT)) & LPI2C_SSR_RSF_MASK)
48256 
48257 #define LPI2C_SSR_SDF_MASK                       (0x200U)
48258 #define LPI2C_SSR_SDF_SHIFT                      (9U)
48259 /*! SDF - Stop Detect Flag
48260  *  0b0..No Stop detected
48261  *  0b1..Stop detected
48262  *  0b0..No effect
48263  *  0b1..Clear the flag
48264  */
48265 #define LPI2C_SSR_SDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SDF_SHIFT)) & LPI2C_SSR_SDF_MASK)
48266 
48267 #define LPI2C_SSR_BEF_MASK                       (0x400U)
48268 #define LPI2C_SSR_BEF_SHIFT                      (10U)
48269 /*! BEF - Bit Error Flag
48270  *  0b0..No bit error occurred
48271  *  0b1..Bit error occurred
48272  *  0b0..No effect
48273  *  0b1..Clear the flag
48274  */
48275 #define LPI2C_SSR_BEF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BEF_SHIFT)) & LPI2C_SSR_BEF_MASK)
48276 
48277 #define LPI2C_SSR_FEF_MASK                       (0x800U)
48278 #define LPI2C_SSR_FEF_SHIFT                      (11U)
48279 /*! FEF - FIFO Error Flag
48280  *  0b0..No FIFO error
48281  *  0b1..FIFO error
48282  *  0b0..No effect
48283  *  0b1..Clear the flag
48284  */
48285 #define LPI2C_SSR_FEF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_FEF_SHIFT)) & LPI2C_SSR_FEF_MASK)
48286 
48287 #define LPI2C_SSR_AM0F_MASK                      (0x1000U)
48288 #define LPI2C_SSR_AM0F_SHIFT                     (12U)
48289 /*! AM0F - Address Match 0 Flag
48290  *  0b0..ADDR0 matching address not received
48291  *  0b1..ADDR0 matching address received
48292  */
48293 #define LPI2C_SSR_AM0F(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM0F_SHIFT)) & LPI2C_SSR_AM0F_MASK)
48294 
48295 #define LPI2C_SSR_AM1F_MASK                      (0x2000U)
48296 #define LPI2C_SSR_AM1F_SHIFT                     (13U)
48297 /*! AM1F - Address Match 1 Flag
48298  *  0b0..Matching address not received
48299  *  0b1..Matching address received
48300  */
48301 #define LPI2C_SSR_AM1F(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM1F_SHIFT)) & LPI2C_SSR_AM1F_MASK)
48302 
48303 #define LPI2C_SSR_GCF_MASK                       (0x4000U)
48304 #define LPI2C_SSR_GCF_SHIFT                      (14U)
48305 /*! GCF - General Call Flag
48306  *  0b0..General call address disabled or not detected
48307  *  0b1..General call address detected
48308  */
48309 #define LPI2C_SSR_GCF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_GCF_SHIFT)) & LPI2C_SSR_GCF_MASK)
48310 
48311 #define LPI2C_SSR_SARF_MASK                      (0x8000U)
48312 #define LPI2C_SSR_SARF_SHIFT                     (15U)
48313 /*! SARF - SMBus Alert Response Flag
48314  *  0b0..Disabled or not detected
48315  *  0b1..Enabled and detected
48316  */
48317 #define LPI2C_SSR_SARF(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SARF_SHIFT)) & LPI2C_SSR_SARF_MASK)
48318 
48319 #define LPI2C_SSR_SBF_MASK                       (0x1000000U)
48320 #define LPI2C_SSR_SBF_SHIFT                      (24U)
48321 /*! SBF - Target Busy Flag
48322  *  0b0..Idle
48323  *  0b1..Busy
48324  */
48325 #define LPI2C_SSR_SBF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SBF_SHIFT)) & LPI2C_SSR_SBF_MASK)
48326 
48327 #define LPI2C_SSR_BBF_MASK                       (0x2000000U)
48328 #define LPI2C_SSR_BBF_SHIFT                      (25U)
48329 /*! BBF - Bus Busy Flag
48330  *  0b0..Idle
48331  *  0b1..Busy
48332  */
48333 #define LPI2C_SSR_BBF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BBF_SHIFT)) & LPI2C_SSR_BBF_MASK)
48334 /*! @} */
48335 
48336 /*! @name SIER - Target Interrupt Enable */
48337 /*! @{ */
48338 
48339 #define LPI2C_SIER_TDIE_MASK                     (0x1U)
48340 #define LPI2C_SIER_TDIE_SHIFT                    (0U)
48341 /*! TDIE - Transmit Data Interrupt Enable
48342  *  0b0..Disable
48343  *  0b1..Enable
48344  */
48345 #define LPI2C_SIER_TDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TDIE_SHIFT)) & LPI2C_SIER_TDIE_MASK)
48346 
48347 #define LPI2C_SIER_RDIE_MASK                     (0x2U)
48348 #define LPI2C_SIER_RDIE_SHIFT                    (1U)
48349 /*! RDIE - Receive Data Interrupt Enable
48350  *  0b0..Disable
48351  *  0b1..Enable
48352  */
48353 #define LPI2C_SIER_RDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RDIE_SHIFT)) & LPI2C_SIER_RDIE_MASK)
48354 
48355 #define LPI2C_SIER_AVIE_MASK                     (0x4U)
48356 #define LPI2C_SIER_AVIE_SHIFT                    (2U)
48357 /*! AVIE - Address Valid Interrupt Enable
48358  *  0b0..Disable
48359  *  0b1..Enable
48360  */
48361 #define LPI2C_SIER_AVIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AVIE_SHIFT)) & LPI2C_SIER_AVIE_MASK)
48362 
48363 #define LPI2C_SIER_TAIE_MASK                     (0x8U)
48364 #define LPI2C_SIER_TAIE_SHIFT                    (3U)
48365 /*! TAIE - Transmit ACK Interrupt Enable
48366  *  0b0..Disable
48367  *  0b1..Enable
48368  */
48369 #define LPI2C_SIER_TAIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TAIE_SHIFT)) & LPI2C_SIER_TAIE_MASK)
48370 
48371 #define LPI2C_SIER_RSIE_MASK                     (0x100U)
48372 #define LPI2C_SIER_RSIE_SHIFT                    (8U)
48373 /*! RSIE - Repeated Start Interrupt Enable
48374  *  0b0..Disable
48375  *  0b1..Enable
48376  */
48377 #define LPI2C_SIER_RSIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RSIE_SHIFT)) & LPI2C_SIER_RSIE_MASK)
48378 
48379 #define LPI2C_SIER_SDIE_MASK                     (0x200U)
48380 #define LPI2C_SIER_SDIE_SHIFT                    (9U)
48381 /*! SDIE - Stop Detect Interrupt Enable
48382  *  0b0..Disable
48383  *  0b1..Enable
48384  */
48385 #define LPI2C_SIER_SDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SDIE_SHIFT)) & LPI2C_SIER_SDIE_MASK)
48386 
48387 #define LPI2C_SIER_BEIE_MASK                     (0x400U)
48388 #define LPI2C_SIER_BEIE_SHIFT                    (10U)
48389 /*! BEIE - Bit Error Interrupt Enable
48390  *  0b0..Disable
48391  *  0b1..Enable
48392  */
48393 #define LPI2C_SIER_BEIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_BEIE_SHIFT)) & LPI2C_SIER_BEIE_MASK)
48394 
48395 #define LPI2C_SIER_FEIE_MASK                     (0x800U)
48396 #define LPI2C_SIER_FEIE_SHIFT                    (11U)
48397 /*! FEIE - FIFO Error Interrupt Enable
48398  *  0b0..Disable
48399  *  0b1..Enable
48400  */
48401 #define LPI2C_SIER_FEIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_FEIE_SHIFT)) & LPI2C_SIER_FEIE_MASK)
48402 
48403 #define LPI2C_SIER_AM0IE_MASK                    (0x1000U)
48404 #define LPI2C_SIER_AM0IE_SHIFT                   (12U)
48405 /*! AM0IE - Address Match 0 Interrupt Enable
48406  *  0b0..Disable
48407  *  0b1..Enable
48408  */
48409 #define LPI2C_SIER_AM0IE(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM0IE_SHIFT)) & LPI2C_SIER_AM0IE_MASK)
48410 
48411 #define LPI2C_SIER_AM1IE_MASK                    (0x2000U)
48412 #define LPI2C_SIER_AM1IE_SHIFT                   (13U)
48413 /*! AM1IE - Address Match 1 Interrupt Enable
48414  *  0b0..Disable
48415  *  0b1..Enable
48416  */
48417 #define LPI2C_SIER_AM1IE(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM1IE_SHIFT)) & LPI2C_SIER_AM1IE_MASK)
48418 
48419 #define LPI2C_SIER_GCIE_MASK                     (0x4000U)
48420 #define LPI2C_SIER_GCIE_SHIFT                    (14U)
48421 /*! GCIE - General Call Interrupt Enable
48422  *  0b0..Disabled
48423  *  0b1..Enabled
48424  */
48425 #define LPI2C_SIER_GCIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_GCIE_SHIFT)) & LPI2C_SIER_GCIE_MASK)
48426 
48427 #define LPI2C_SIER_SARIE_MASK                    (0x8000U)
48428 #define LPI2C_SIER_SARIE_SHIFT                   (15U)
48429 /*! SARIE - SMBus Alert Response Interrupt Enable
48430  *  0b0..Disable
48431  *  0b1..Enable
48432  */
48433 #define LPI2C_SIER_SARIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SARIE_SHIFT)) & LPI2C_SIER_SARIE_MASK)
48434 /*! @} */
48435 
48436 /*! @name SDER - Target DMA Enable */
48437 /*! @{ */
48438 
48439 #define LPI2C_SDER_TDDE_MASK                     (0x1U)
48440 #define LPI2C_SDER_TDDE_SHIFT                    (0U)
48441 /*! TDDE - Transmit Data DMA Enable
48442  *  0b0..Disable
48443  *  0b1..Enable
48444  */
48445 #define LPI2C_SDER_TDDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_TDDE_SHIFT)) & LPI2C_SDER_TDDE_MASK)
48446 
48447 #define LPI2C_SDER_RDDE_MASK                     (0x2U)
48448 #define LPI2C_SDER_RDDE_SHIFT                    (1U)
48449 /*! RDDE - Receive Data DMA Enable
48450  *  0b0..Disable DMA request
48451  *  0b1..Enable DMA request
48452  */
48453 #define LPI2C_SDER_RDDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RDDE_SHIFT)) & LPI2C_SDER_RDDE_MASK)
48454 
48455 #define LPI2C_SDER_AVDE_MASK                     (0x4U)
48456 #define LPI2C_SDER_AVDE_SHIFT                    (2U)
48457 /*! AVDE - Address Valid DMA Enable
48458  *  0b0..Disable
48459  *  0b1..Enable
48460  */
48461 #define LPI2C_SDER_AVDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_AVDE_SHIFT)) & LPI2C_SDER_AVDE_MASK)
48462 
48463 #define LPI2C_SDER_RSDE_MASK                     (0x100U)
48464 #define LPI2C_SDER_RSDE_SHIFT                    (8U)
48465 /*! RSDE - Repeated Start DMA Enable
48466  *  0b0..Disable
48467  *  0b1..Enable
48468  */
48469 #define LPI2C_SDER_RSDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RSDE_SHIFT)) & LPI2C_SDER_RSDE_MASK)
48470 
48471 #define LPI2C_SDER_SDDE_MASK                     (0x200U)
48472 #define LPI2C_SDER_SDDE_SHIFT                    (9U)
48473 /*! SDDE - Stop Detect DMA Enable
48474  *  0b0..Disable
48475  *  0b1..Enable
48476  */
48477 #define LPI2C_SDER_SDDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_SDDE_SHIFT)) & LPI2C_SDER_SDDE_MASK)
48478 /*! @} */
48479 
48480 /*! @name SCFGR0 - Target Configuration 0 */
48481 /*! @{ */
48482 
48483 #define LPI2C_SCFGR0_RDREQ_MASK                  (0x1U)
48484 #define LPI2C_SCFGR0_RDREQ_SHIFT                 (0U)
48485 /*! RDREQ - Read Request
48486  *  0b0..Disable
48487  *  0b1..Enable
48488  */
48489 #define LPI2C_SCFGR0_RDREQ(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR0_RDREQ_SHIFT)) & LPI2C_SCFGR0_RDREQ_MASK)
48490 
48491 #define LPI2C_SCFGR0_RDACK_MASK                  (0x2U)
48492 #define LPI2C_SCFGR0_RDACK_SHIFT                 (1U)
48493 /*! RDACK - Read Acknowledge Flag
48494  *  0b0..Read Request not acknowledged
48495  *  0b1..Read Request acknowledged
48496  */
48497 #define LPI2C_SCFGR0_RDACK(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR0_RDACK_SHIFT)) & LPI2C_SCFGR0_RDACK_MASK)
48498 /*! @} */
48499 
48500 /*! @name SCFGR1 - Target Configuration 1 */
48501 /*! @{ */
48502 
48503 #define LPI2C_SCFGR1_ADRSTALL_MASK               (0x1U)
48504 #define LPI2C_SCFGR1_ADRSTALL_SHIFT              (0U)
48505 /*! ADRSTALL - Address SCL Stall
48506  *  0b0..Disable
48507  *  0b1..Enable
48508  */
48509 #define LPI2C_SCFGR1_ADRSTALL(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADRSTALL_SHIFT)) & LPI2C_SCFGR1_ADRSTALL_MASK)
48510 
48511 #define LPI2C_SCFGR1_RXSTALL_MASK                (0x2U)
48512 #define LPI2C_SCFGR1_RXSTALL_SHIFT               (1U)
48513 /*! RXSTALL - RX SCL Stall
48514  *  0b0..Disable
48515  *  0b1..Enable
48516  */
48517 #define LPI2C_SCFGR1_RXSTALL(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXSTALL_SHIFT)) & LPI2C_SCFGR1_RXSTALL_MASK)
48518 
48519 #define LPI2C_SCFGR1_TXDSTALL_MASK               (0x4U)
48520 #define LPI2C_SCFGR1_TXDSTALL_SHIFT              (2U)
48521 /*! TXDSTALL - Transmit Data SCL Stall
48522  *  0b0..Disable
48523  *  0b1..Enable
48524  */
48525 #define LPI2C_SCFGR1_TXDSTALL(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXDSTALL_SHIFT)) & LPI2C_SCFGR1_TXDSTALL_MASK)
48526 
48527 #define LPI2C_SCFGR1_ACKSTALL_MASK               (0x8U)
48528 #define LPI2C_SCFGR1_ACKSTALL_SHIFT              (3U)
48529 /*! ACKSTALL - ACK SCL Stall
48530  *  0b0..Disable
48531  *  0b1..Enable
48532  */
48533 #define LPI2C_SCFGR1_ACKSTALL(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ACKSTALL_SHIFT)) & LPI2C_SCFGR1_ACKSTALL_MASK)
48534 
48535 #define LPI2C_SCFGR1_RXNACK_MASK                 (0x10U)
48536 #define LPI2C_SCFGR1_RXNACK_SHIFT                (4U)
48537 /*! RXNACK - Receive NACK
48538  *  0b0..ACK or NACK always determined by STAR[TXNACK]
48539  *  0b1..NACK always generated on address overrun or receive data overrun, otherwise ACK or NACK is determined by STAR[TXNACK]
48540  */
48541 #define LPI2C_SCFGR1_RXNACK(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXNACK_SHIFT)) & LPI2C_SCFGR1_RXNACK_MASK)
48542 
48543 #define LPI2C_SCFGR1_GCEN_MASK                   (0x100U)
48544 #define LPI2C_SCFGR1_GCEN_SHIFT                  (8U)
48545 /*! GCEN - General Call Enable
48546  *  0b0..Disable
48547  *  0b1..Enable
48548  */
48549 #define LPI2C_SCFGR1_GCEN(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_GCEN_SHIFT)) & LPI2C_SCFGR1_GCEN_MASK)
48550 
48551 #define LPI2C_SCFGR1_SAEN_MASK                   (0x200U)
48552 #define LPI2C_SCFGR1_SAEN_SHIFT                  (9U)
48553 /*! SAEN - SMBus Alert Enable
48554  *  0b0..Disable
48555  *  0b1..Enable
48556  */
48557 #define LPI2C_SCFGR1_SAEN(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SAEN_SHIFT)) & LPI2C_SCFGR1_SAEN_MASK)
48558 
48559 #define LPI2C_SCFGR1_TXCFG_MASK                  (0x400U)
48560 #define LPI2C_SCFGR1_TXCFG_SHIFT                 (10U)
48561 /*! TXCFG - Transmit Flag Configuration
48562  *  0b0..MSR[TDF] is set only during a target-transmit transfer when STDR is empty
48563  *  0b1..MSR[TDF] is set whenever STDR is empty
48564  */
48565 #define LPI2C_SCFGR1_TXCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXCFG_SHIFT)) & LPI2C_SCFGR1_TXCFG_MASK)
48566 
48567 #define LPI2C_SCFGR1_RXCFG_MASK                  (0x800U)
48568 #define LPI2C_SCFGR1_RXCFG_SHIFT                 (11U)
48569 /*! RXCFG - Receive Data Configuration
48570  *  0b0..Return received data, clear MSR[RDF]
48571  *  0b1..Return SASR and clear SSR[AVF] when SSR[AVF] is set, return received data and clear MSR[RDF] when SSR[AFV] is not set
48572  */
48573 #define LPI2C_SCFGR1_RXCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXCFG_SHIFT)) & LPI2C_SCFGR1_RXCFG_MASK)
48574 
48575 #define LPI2C_SCFGR1_IGNACK_MASK                 (0x1000U)
48576 #define LPI2C_SCFGR1_IGNACK_SHIFT                (12U)
48577 /*! IGNACK - Ignore NACK
48578  *  0b0..End transfer on NACK
48579  *  0b1..Do not end transfer on NACK
48580  */
48581 #define LPI2C_SCFGR1_IGNACK(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_IGNACK_SHIFT)) & LPI2C_SCFGR1_IGNACK_MASK)
48582 
48583 #define LPI2C_SCFGR1_HSMEN_MASK                  (0x2000U)
48584 #define LPI2C_SCFGR1_HSMEN_SHIFT                 (13U)
48585 /*! HSMEN - HS Mode Enable
48586  *  0b0..Disable
48587  *  0b1..Enable
48588  */
48589 #define LPI2C_SCFGR1_HSMEN(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_HSMEN_SHIFT)) & LPI2C_SCFGR1_HSMEN_MASK)
48590 
48591 #define LPI2C_SCFGR1_ADDRCFG_MASK                (0x70000U)
48592 #define LPI2C_SCFGR1_ADDRCFG_SHIFT               (16U)
48593 /*! ADDRCFG - Address Configuration
48594  *  0b000..Address match 0 (7-bit)
48595  *  0b001..Address match 0 (10-bit)
48596  *  0b010..Address match 0 (7-bit) or address match 1 (7-bit)
48597  *  0b011..Address match 0 (10-bit) or address match 1 (10-bit)
48598  *  0b100..Address match 0 (7-bit) or address match 1 (10-bit)
48599  *  0b101..Address match 0 (10-bit) or address match 1 (7-bit)
48600  *  0b110..From address match 0 (7-bit) to address match 1 (7-bit)
48601  *  0b111..From address match 0 (10-bit) to address match 1 (10-bit)
48602  */
48603 #define LPI2C_SCFGR1_ADDRCFG(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADDRCFG_SHIFT)) & LPI2C_SCFGR1_ADDRCFG_MASK)
48604 
48605 #define LPI2C_SCFGR1_RXALL_MASK                  (0x1000000U)
48606 #define LPI2C_SCFGR1_RXALL_SHIFT                 (24U)
48607 /*! RXALL - Receive All
48608  *  0b0..Disable
48609  *  0b1..Enable
48610  */
48611 #define LPI2C_SCFGR1_RXALL(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXALL_SHIFT)) & LPI2C_SCFGR1_RXALL_MASK)
48612 
48613 #define LPI2C_SCFGR1_RSCFG_MASK                  (0x2000000U)
48614 #define LPI2C_SCFGR1_RSCFG_SHIFT                 (25U)
48615 /*! RSCFG - Repeated Start Configuration
48616  *  0b0..Any repeated Start condition following an address match
48617  *  0b1..Any repeated Start condition
48618  */
48619 #define LPI2C_SCFGR1_RSCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RSCFG_SHIFT)) & LPI2C_SCFGR1_RSCFG_MASK)
48620 
48621 #define LPI2C_SCFGR1_SDCFG_MASK                  (0x4000000U)
48622 #define LPI2C_SCFGR1_SDCFG_SHIFT                 (26U)
48623 /*! SDCFG - Stop Detect Configuration
48624  *  0b0..Any Stop condition following an address match
48625  *  0b1..Any Stop condition
48626  */
48627 #define LPI2C_SCFGR1_SDCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SDCFG_SHIFT)) & LPI2C_SCFGR1_SDCFG_MASK)
48628 /*! @} */
48629 
48630 /*! @name SCFGR2 - Target Configuration 2 */
48631 /*! @{ */
48632 
48633 #define LPI2C_SCFGR2_CLKHOLD_MASK                (0xFU)
48634 #define LPI2C_SCFGR2_CLKHOLD_SHIFT               (0U)
48635 /*! CLKHOLD - Clock Hold Time */
48636 #define LPI2C_SCFGR2_CLKHOLD(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_CLKHOLD_SHIFT)) & LPI2C_SCFGR2_CLKHOLD_MASK)
48637 
48638 #define LPI2C_SCFGR2_DATAVD_MASK                 (0x3F00U)
48639 #define LPI2C_SCFGR2_DATAVD_SHIFT                (8U)
48640 /*! DATAVD - Data Valid Delay */
48641 #define LPI2C_SCFGR2_DATAVD(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_DATAVD_SHIFT)) & LPI2C_SCFGR2_DATAVD_MASK)
48642 
48643 #define LPI2C_SCFGR2_FILTSCL_MASK                (0xF0000U)
48644 #define LPI2C_SCFGR2_FILTSCL_SHIFT               (16U)
48645 /*! FILTSCL - Glitch Filter SCL */
48646 #define LPI2C_SCFGR2_FILTSCL(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSCL_SHIFT)) & LPI2C_SCFGR2_FILTSCL_MASK)
48647 
48648 #define LPI2C_SCFGR2_FILTSDA_MASK                (0xF000000U)
48649 #define LPI2C_SCFGR2_FILTSDA_SHIFT               (24U)
48650 /*! FILTSDA - Glitch Filter SDA */
48651 #define LPI2C_SCFGR2_FILTSDA(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSDA_SHIFT)) & LPI2C_SCFGR2_FILTSDA_MASK)
48652 /*! @} */
48653 
48654 /*! @name SAMR - Target Address Match */
48655 /*! @{ */
48656 
48657 #define LPI2C_SAMR_ADDR0_MASK                    (0x7FEU)
48658 #define LPI2C_SAMR_ADDR0_SHIFT                   (1U)
48659 /*! ADDR0 - Address 0 Value */
48660 #define LPI2C_SAMR_ADDR0(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR0_SHIFT)) & LPI2C_SAMR_ADDR0_MASK)
48661 
48662 #define LPI2C_SAMR_ADDR1_MASK                    (0x7FE0000U)
48663 #define LPI2C_SAMR_ADDR1_SHIFT                   (17U)
48664 /*! ADDR1 - Address 1 Value */
48665 #define LPI2C_SAMR_ADDR1(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR1_SHIFT)) & LPI2C_SAMR_ADDR1_MASK)
48666 /*! @} */
48667 
48668 /*! @name SASR - Target Address Status */
48669 /*! @{ */
48670 
48671 #define LPI2C_SASR_RADDR_MASK                    (0x7FFU)
48672 #define LPI2C_SASR_RADDR_SHIFT                   (0U)
48673 /*! RADDR - Received Address */
48674 #define LPI2C_SASR_RADDR(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_RADDR_SHIFT)) & LPI2C_SASR_RADDR_MASK)
48675 
48676 #define LPI2C_SASR_ANV_MASK                      (0x4000U)
48677 #define LPI2C_SASR_ANV_SHIFT                     (14U)
48678 /*! ANV - Address Not Valid
48679  *  0b0..Valid
48680  *  0b1..Not valid
48681  */
48682 #define LPI2C_SASR_ANV(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_ANV_SHIFT)) & LPI2C_SASR_ANV_MASK)
48683 /*! @} */
48684 
48685 /*! @name STAR - Target Transmit ACK */
48686 /*! @{ */
48687 
48688 #define LPI2C_STAR_TXNACK_MASK                   (0x1U)
48689 #define LPI2C_STAR_TXNACK_SHIFT                  (0U)
48690 /*! TXNACK - Transmit NACK
48691  *  0b0..Transmit ACK
48692  *  0b1..Transmit NACK
48693  */
48694 #define LPI2C_STAR_TXNACK(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_STAR_TXNACK_SHIFT)) & LPI2C_STAR_TXNACK_MASK)
48695 /*! @} */
48696 
48697 /*! @name STDR - Target Transmit Data */
48698 /*! @{ */
48699 
48700 #define LPI2C_STDR_DATA_MASK                     (0xFFU)
48701 #define LPI2C_STDR_DATA_SHIFT                    (0U)
48702 /*! DATA - Transmit Data */
48703 #define LPI2C_STDR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_STDR_DATA_SHIFT)) & LPI2C_STDR_DATA_MASK)
48704 /*! @} */
48705 
48706 /*! @name SRDR - Target Receive Data */
48707 /*! @{ */
48708 
48709 #define LPI2C_SRDR_DATA_MASK                     (0xFFU)
48710 #define LPI2C_SRDR_DATA_SHIFT                    (0U)
48711 /*! DATA - Received Data */
48712 #define LPI2C_SRDR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_DATA_SHIFT)) & LPI2C_SRDR_DATA_MASK)
48713 
48714 #define LPI2C_SRDR_RADDR_MASK                    (0x700U)
48715 #define LPI2C_SRDR_RADDR_SHIFT                   (8U)
48716 /*! RADDR - Received Address */
48717 #define LPI2C_SRDR_RADDR(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RADDR_SHIFT)) & LPI2C_SRDR_RADDR_MASK)
48718 
48719 #define LPI2C_SRDR_RXEMPTY_MASK                  (0x4000U)
48720 #define LPI2C_SRDR_RXEMPTY_SHIFT                 (14U)
48721 /*! RXEMPTY - Receive Empty
48722  *  0b0..Not empty
48723  *  0b1..Empty
48724  */
48725 #define LPI2C_SRDR_RXEMPTY(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RXEMPTY_SHIFT)) & LPI2C_SRDR_RXEMPTY_MASK)
48726 
48727 #define LPI2C_SRDR_SOF_MASK                      (0x8000U)
48728 #define LPI2C_SRDR_SOF_SHIFT                     (15U)
48729 /*! SOF - Start of Frame
48730  *  0b0..Not first
48731  *  0b1..First
48732  */
48733 #define LPI2C_SRDR_SOF(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_SOF_SHIFT)) & LPI2C_SRDR_SOF_MASK)
48734 /*! @} */
48735 
48736 /*! @name SRDROR - Target Receive Data Read Only */
48737 /*! @{ */
48738 
48739 #define LPI2C_SRDROR_DATA_MASK                   (0xFFU)
48740 #define LPI2C_SRDROR_DATA_SHIFT                  (0U)
48741 /*! DATA - Receive Data */
48742 #define LPI2C_SRDROR_DATA(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDROR_DATA_SHIFT)) & LPI2C_SRDROR_DATA_MASK)
48743 
48744 #define LPI2C_SRDROR_RADDR_MASK                  (0x700U)
48745 #define LPI2C_SRDROR_RADDR_SHIFT                 (8U)
48746 /*! RADDR - Received Address */
48747 #define LPI2C_SRDROR_RADDR(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDROR_RADDR_SHIFT)) & LPI2C_SRDROR_RADDR_MASK)
48748 
48749 #define LPI2C_SRDROR_RXEMPTY_MASK                (0x4000U)
48750 #define LPI2C_SRDROR_RXEMPTY_SHIFT               (14U)
48751 /*! RXEMPTY - Receive Empty
48752  *  0b0..Not empty
48753  *  0b1..Empty
48754  */
48755 #define LPI2C_SRDROR_RXEMPTY(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDROR_RXEMPTY_SHIFT)) & LPI2C_SRDROR_RXEMPTY_MASK)
48756 
48757 #define LPI2C_SRDROR_SOF_MASK                    (0x8000U)
48758 #define LPI2C_SRDROR_SOF_SHIFT                   (15U)
48759 /*! SOF - Start of Frame
48760  *  0b0..Not the first
48761  *  0b1..First
48762  */
48763 #define LPI2C_SRDROR_SOF(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDROR_SOF_SHIFT)) & LPI2C_SRDROR_SOF_MASK)
48764 /*! @} */
48765 
48766 /*! @name MTCBR - Controller Transmit Command Burst */
48767 /*! @{ */
48768 
48769 #define LPI2C_MTCBR_DATA_MASK                    (0xFFU)
48770 #define LPI2C_MTCBR_DATA_SHIFT                   (0U)
48771 /*! DATA - Data */
48772 #define LPI2C_MTCBR_DATA(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_MTCBR_DATA_SHIFT)) & LPI2C_MTCBR_DATA_MASK)
48773 
48774 #define LPI2C_MTCBR_CMD_MASK                     (0x700U)
48775 #define LPI2C_MTCBR_CMD_SHIFT                    (8U)
48776 /*! CMD - Command */
48777 #define LPI2C_MTCBR_CMD(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MTCBR_CMD_SHIFT)) & LPI2C_MTCBR_CMD_MASK)
48778 /*! @} */
48779 
48780 /* The count of LPI2C_MTCBR */
48781 #define LPI2C_MTCBR_COUNT                        (128U)
48782 
48783 /*! @name MTDBR - Transmit Data Burst */
48784 /*! @{ */
48785 
48786 #define LPI2C_MTDBR_DATA0_MASK                   (0xFFU)
48787 #define LPI2C_MTDBR_DATA0_SHIFT                  (0U)
48788 /*! DATA0 - Data */
48789 #define LPI2C_MTDBR_DATA0(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDBR_DATA0_SHIFT)) & LPI2C_MTDBR_DATA0_MASK)
48790 
48791 #define LPI2C_MTDBR_DATA1_MASK                   (0xFF00U)
48792 #define LPI2C_MTDBR_DATA1_SHIFT                  (8U)
48793 /*! DATA1 - Data */
48794 #define LPI2C_MTDBR_DATA1(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDBR_DATA1_SHIFT)) & LPI2C_MTDBR_DATA1_MASK)
48795 
48796 #define LPI2C_MTDBR_DATA2_MASK                   (0xFF0000U)
48797 #define LPI2C_MTDBR_DATA2_SHIFT                  (16U)
48798 /*! DATA2 - Data */
48799 #define LPI2C_MTDBR_DATA2(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDBR_DATA2_SHIFT)) & LPI2C_MTDBR_DATA2_MASK)
48800 
48801 #define LPI2C_MTDBR_DATA3_MASK                   (0xFF000000U)
48802 #define LPI2C_MTDBR_DATA3_SHIFT                  (24U)
48803 /*! DATA3 - Data */
48804 #define LPI2C_MTDBR_DATA3(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDBR_DATA3_SHIFT)) & LPI2C_MTDBR_DATA3_MASK)
48805 /*! @} */
48806 
48807 /* The count of LPI2C_MTDBR */
48808 #define LPI2C_MTDBR_COUNT                        (253U)
48809 
48810 
48811 /*!
48812  * @}
48813  */ /* end of group LPI2C_Register_Masks */
48814 
48815 
48816 /* LPI2C - Peripheral instance base addresses */
48817 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
48818   /** Peripheral LPI2C0 base address */
48819   #define LPI2C0_BASE                              (0x50092800u)
48820   /** Peripheral LPI2C0 base address */
48821   #define LPI2C0_BASE_NS                           (0x40092800u)
48822   /** Peripheral LPI2C0 base pointer */
48823   #define LPI2C0                                   ((LPI2C_Type *)LPI2C0_BASE)
48824   /** Peripheral LPI2C0 base pointer */
48825   #define LPI2C0_NS                                ((LPI2C_Type *)LPI2C0_BASE_NS)
48826   /** Peripheral LPI2C1 base address */
48827   #define LPI2C1_BASE                              (0x50093800u)
48828   /** Peripheral LPI2C1 base address */
48829   #define LPI2C1_BASE_NS                           (0x40093800u)
48830   /** Peripheral LPI2C1 base pointer */
48831   #define LPI2C1                                   ((LPI2C_Type *)LPI2C1_BASE)
48832   /** Peripheral LPI2C1 base pointer */
48833   #define LPI2C1_NS                                ((LPI2C_Type *)LPI2C1_BASE_NS)
48834   /** Peripheral LPI2C2 base address */
48835   #define LPI2C2_BASE                              (0x50094800u)
48836   /** Peripheral LPI2C2 base address */
48837   #define LPI2C2_BASE_NS                           (0x40094800u)
48838   /** Peripheral LPI2C2 base pointer */
48839   #define LPI2C2                                   ((LPI2C_Type *)LPI2C2_BASE)
48840   /** Peripheral LPI2C2 base pointer */
48841   #define LPI2C2_NS                                ((LPI2C_Type *)LPI2C2_BASE_NS)
48842   /** Peripheral LPI2C3 base address */
48843   #define LPI2C3_BASE                              (0x50095800u)
48844   /** Peripheral LPI2C3 base address */
48845   #define LPI2C3_BASE_NS                           (0x40095800u)
48846   /** Peripheral LPI2C3 base pointer */
48847   #define LPI2C3                                   ((LPI2C_Type *)LPI2C3_BASE)
48848   /** Peripheral LPI2C3 base pointer */
48849   #define LPI2C3_NS                                ((LPI2C_Type *)LPI2C3_BASE_NS)
48850   /** Peripheral LPI2C4 base address */
48851   #define LPI2C4_BASE                              (0x500B4800u)
48852   /** Peripheral LPI2C4 base address */
48853   #define LPI2C4_BASE_NS                           (0x400B4800u)
48854   /** Peripheral LPI2C4 base pointer */
48855   #define LPI2C4                                   ((LPI2C_Type *)LPI2C4_BASE)
48856   /** Peripheral LPI2C4 base pointer */
48857   #define LPI2C4_NS                                ((LPI2C_Type *)LPI2C4_BASE_NS)
48858   /** Peripheral LPI2C5 base address */
48859   #define LPI2C5_BASE                              (0x500B5800u)
48860   /** Peripheral LPI2C5 base address */
48861   #define LPI2C5_BASE_NS                           (0x400B5800u)
48862   /** Peripheral LPI2C5 base pointer */
48863   #define LPI2C5                                   ((LPI2C_Type *)LPI2C5_BASE)
48864   /** Peripheral LPI2C5 base pointer */
48865   #define LPI2C5_NS                                ((LPI2C_Type *)LPI2C5_BASE_NS)
48866   /** Peripheral LPI2C6 base address */
48867   #define LPI2C6_BASE                              (0x500B6800u)
48868   /** Peripheral LPI2C6 base address */
48869   #define LPI2C6_BASE_NS                           (0x400B6800u)
48870   /** Peripheral LPI2C6 base pointer */
48871   #define LPI2C6                                   ((LPI2C_Type *)LPI2C6_BASE)
48872   /** Peripheral LPI2C6 base pointer */
48873   #define LPI2C6_NS                                ((LPI2C_Type *)LPI2C6_BASE_NS)
48874   /** Peripheral LPI2C7 base address */
48875   #define LPI2C7_BASE                              (0x500B7800u)
48876   /** Peripheral LPI2C7 base address */
48877   #define LPI2C7_BASE_NS                           (0x400B7800u)
48878   /** Peripheral LPI2C7 base pointer */
48879   #define LPI2C7                                   ((LPI2C_Type *)LPI2C7_BASE)
48880   /** Peripheral LPI2C7 base pointer */
48881   #define LPI2C7_NS                                ((LPI2C_Type *)LPI2C7_BASE_NS)
48882   /** Peripheral LPI2C8 base address */
48883   #define LPI2C8_BASE                              (0x500B8800u)
48884   /** Peripheral LPI2C8 base address */
48885   #define LPI2C8_BASE_NS                           (0x400B8800u)
48886   /** Peripheral LPI2C8 base pointer */
48887   #define LPI2C8                                   ((LPI2C_Type *)LPI2C8_BASE)
48888   /** Peripheral LPI2C8 base pointer */
48889   #define LPI2C8_NS                                ((LPI2C_Type *)LPI2C8_BASE_NS)
48890   /** Peripheral LPI2C9 base address */
48891   #define LPI2C9_BASE                              (0x500B9800u)
48892   /** Peripheral LPI2C9 base address */
48893   #define LPI2C9_BASE_NS                           (0x400B9800u)
48894   /** Peripheral LPI2C9 base pointer */
48895   #define LPI2C9                                   ((LPI2C_Type *)LPI2C9_BASE)
48896   /** Peripheral LPI2C9 base pointer */
48897   #define LPI2C9_NS                                ((LPI2C_Type *)LPI2C9_BASE_NS)
48898   /** Array initializer of LPI2C peripheral base addresses */
48899   #define LPI2C_BASE_ADDRS                         { LPI2C0_BASE, LPI2C1_BASE, LPI2C2_BASE, LPI2C3_BASE, LPI2C4_BASE, LPI2C5_BASE, LPI2C6_BASE, LPI2C7_BASE, LPI2C8_BASE, LPI2C9_BASE }
48900   /** Array initializer of LPI2C peripheral base pointers */
48901   #define LPI2C_BASE_PTRS                          { LPI2C0, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPI2C5, LPI2C6, LPI2C7, LPI2C8, LPI2C9 }
48902   /** Array initializer of LPI2C peripheral base addresses */
48903   #define LPI2C_BASE_ADDRS_NS                      { LPI2C0_BASE_NS, LPI2C1_BASE_NS, LPI2C2_BASE_NS, LPI2C3_BASE_NS, LPI2C4_BASE_NS, LPI2C5_BASE_NS, LPI2C6_BASE_NS, LPI2C7_BASE_NS, LPI2C8_BASE_NS, LPI2C9_BASE_NS }
48904   /** Array initializer of LPI2C peripheral base pointers */
48905   #define LPI2C_BASE_PTRS_NS                       { LPI2C0_NS, LPI2C1_NS, LPI2C2_NS, LPI2C3_NS, LPI2C4_NS, LPI2C5_NS, LPI2C6_NS, LPI2C7_NS, LPI2C8_NS, LPI2C9_NS }
48906 #else
48907   /** Peripheral LPI2C0 base address */
48908   #define LPI2C0_BASE                              (0x40092800u)
48909   /** Peripheral LPI2C0 base pointer */
48910   #define LPI2C0                                   ((LPI2C_Type *)LPI2C0_BASE)
48911   /** Peripheral LPI2C1 base address */
48912   #define LPI2C1_BASE                              (0x40093800u)
48913   /** Peripheral LPI2C1 base pointer */
48914   #define LPI2C1                                   ((LPI2C_Type *)LPI2C1_BASE)
48915   /** Peripheral LPI2C2 base address */
48916   #define LPI2C2_BASE                              (0x40094800u)
48917   /** Peripheral LPI2C2 base pointer */
48918   #define LPI2C2                                   ((LPI2C_Type *)LPI2C2_BASE)
48919   /** Peripheral LPI2C3 base address */
48920   #define LPI2C3_BASE                              (0x40095800u)
48921   /** Peripheral LPI2C3 base pointer */
48922   #define LPI2C3                                   ((LPI2C_Type *)LPI2C3_BASE)
48923   /** Peripheral LPI2C4 base address */
48924   #define LPI2C4_BASE                              (0x400B4800u)
48925   /** Peripheral LPI2C4 base pointer */
48926   #define LPI2C4                                   ((LPI2C_Type *)LPI2C4_BASE)
48927   /** Peripheral LPI2C5 base address */
48928   #define LPI2C5_BASE                              (0x400B5800u)
48929   /** Peripheral LPI2C5 base pointer */
48930   #define LPI2C5                                   ((LPI2C_Type *)LPI2C5_BASE)
48931   /** Peripheral LPI2C6 base address */
48932   #define LPI2C6_BASE                              (0x400B6800u)
48933   /** Peripheral LPI2C6 base pointer */
48934   #define LPI2C6                                   ((LPI2C_Type *)LPI2C6_BASE)
48935   /** Peripheral LPI2C7 base address */
48936   #define LPI2C7_BASE                              (0x400B7800u)
48937   /** Peripheral LPI2C7 base pointer */
48938   #define LPI2C7                                   ((LPI2C_Type *)LPI2C7_BASE)
48939   /** Peripheral LPI2C8 base address */
48940   #define LPI2C8_BASE                              (0x400B8800u)
48941   /** Peripheral LPI2C8 base pointer */
48942   #define LPI2C8                                   ((LPI2C_Type *)LPI2C8_BASE)
48943   /** Peripheral LPI2C9 base address */
48944   #define LPI2C9_BASE                              (0x400B9800u)
48945   /** Peripheral LPI2C9 base pointer */
48946   #define LPI2C9                                   ((LPI2C_Type *)LPI2C9_BASE)
48947   /** Array initializer of LPI2C peripheral base addresses */
48948   #define LPI2C_BASE_ADDRS                         { LPI2C0_BASE, LPI2C1_BASE, LPI2C2_BASE, LPI2C3_BASE, LPI2C4_BASE, LPI2C5_BASE, LPI2C6_BASE, LPI2C7_BASE, LPI2C8_BASE, LPI2C9_BASE }
48949   /** Array initializer of LPI2C peripheral base pointers */
48950   #define LPI2C_BASE_PTRS                          { LPI2C0, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPI2C5, LPI2C6, LPI2C7, LPI2C8, LPI2C9 }
48951 #endif
48952 /** Interrupt vectors for the LPI2C peripheral type */
48953 #define LPI2C_IRQS                               { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn, LP_FLEXCOMM8_IRQn, LP_FLEXCOMM9_IRQn }
48954 
48955 /*!
48956  * @}
48957  */ /* end of group LPI2C_Peripheral_Access_Layer */
48958 
48959 
48960 /* ----------------------------------------------------------------------------
48961    -- LPSPI Peripheral Access Layer
48962    ---------------------------------------------------------------------------- */
48963 
48964 /*!
48965  * @addtogroup LPSPI_Peripheral_Access_Layer LPSPI Peripheral Access Layer
48966  * @{
48967  */
48968 
48969 /** LPSPI - Register Layout Typedef */
48970 typedef struct {
48971   __I  uint32_t VERID;                             /**< Version ID, offset: 0x0 */
48972   __I  uint32_t PARAM;                             /**< Parameter, offset: 0x4 */
48973        uint8_t RESERVED_0[8];
48974   __IO uint32_t CR;                                /**< Control, offset: 0x10 */
48975   __IO uint32_t SR;                                /**< Status, offset: 0x14 */
48976   __IO uint32_t IER;                               /**< Interrupt Enable, offset: 0x18 */
48977   __IO uint32_t DER;                               /**< DMA Enable, offset: 0x1C */
48978   __IO uint32_t CFGR0;                             /**< Configuration 0, offset: 0x20 */
48979   __IO uint32_t CFGR1;                             /**< Configuration 1, offset: 0x24 */
48980        uint8_t RESERVED_1[8];
48981   __IO uint32_t DMR0;                              /**< Data Match 0, offset: 0x30 */
48982   __IO uint32_t DMR1;                              /**< Data Match 1, offset: 0x34 */
48983        uint8_t RESERVED_2[8];
48984   __IO uint32_t CCR;                               /**< Clock Configuration, offset: 0x40 */
48985   __IO uint32_t CCR1;                              /**< Clock Configuration 1, offset: 0x44 */
48986        uint8_t RESERVED_3[16];
48987   __IO uint32_t FCR;                               /**< FIFO Control, offset: 0x58 */
48988   __I  uint32_t FSR;                               /**< FIFO Status, offset: 0x5C */
48989   __IO uint32_t TCR;                               /**< Transmit Command, offset: 0x60 */
48990   __O  uint32_t TDR;                               /**< Transmit Data, offset: 0x64 */
48991        uint8_t RESERVED_4[8];
48992   __I  uint32_t RSR;                               /**< Receive Status, offset: 0x70 */
48993   __I  uint32_t RDR;                               /**< Receive Data, offset: 0x74 */
48994   __I  uint32_t RDROR;                             /**< Receive Data Read Only, offset: 0x78 */
48995        uint8_t RESERVED_5[896];
48996   __O  uint32_t TCBR;                              /**< Transmit Command Burst, offset: 0x3FC */
48997   __O  uint32_t TDBR[128];                         /**< Transmit Data Burst, array offset: 0x400, array step: 0x4 */
48998   __I  uint32_t RDBR[128];                         /**< Receive Data Burst, array offset: 0x600, array step: 0x4 */
48999 } LPSPI_Type;
49000 
49001 /* ----------------------------------------------------------------------------
49002    -- LPSPI Register Masks
49003    ---------------------------------------------------------------------------- */
49004 
49005 /*!
49006  * @addtogroup LPSPI_Register_Masks LPSPI Register Masks
49007  * @{
49008  */
49009 
49010 /*! @name VERID - Version ID */
49011 /*! @{ */
49012 
49013 #define LPSPI_VERID_FEATURE_MASK                 (0xFFFFU)
49014 #define LPSPI_VERID_FEATURE_SHIFT                (0U)
49015 /*! FEATURE - Module Identification Number
49016  *  0b0000000000000100..Standard feature set supporting a 32-bit shift register.
49017  *  *..
49018  */
49019 #define LPSPI_VERID_FEATURE(x)                   (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_FEATURE_SHIFT)) & LPSPI_VERID_FEATURE_MASK)
49020 
49021 #define LPSPI_VERID_MINOR_MASK                   (0xFF0000U)
49022 #define LPSPI_VERID_MINOR_SHIFT                  (16U)
49023 /*! MINOR - Minor Version Number */
49024 #define LPSPI_VERID_MINOR(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MINOR_SHIFT)) & LPSPI_VERID_MINOR_MASK)
49025 
49026 #define LPSPI_VERID_MAJOR_MASK                   (0xFF000000U)
49027 #define LPSPI_VERID_MAJOR_SHIFT                  (24U)
49028 /*! MAJOR - Major Version Number */
49029 #define LPSPI_VERID_MAJOR(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MAJOR_SHIFT)) & LPSPI_VERID_MAJOR_MASK)
49030 /*! @} */
49031 
49032 /*! @name PARAM - Parameter */
49033 /*! @{ */
49034 
49035 #define LPSPI_PARAM_TXFIFO_MASK                  (0xFFU)
49036 #define LPSPI_PARAM_TXFIFO_SHIFT                 (0U)
49037 /*! TXFIFO - Transmit FIFO Size */
49038 #define LPSPI_PARAM_TXFIFO(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_TXFIFO_SHIFT)) & LPSPI_PARAM_TXFIFO_MASK)
49039 
49040 #define LPSPI_PARAM_RXFIFO_MASK                  (0xFF00U)
49041 #define LPSPI_PARAM_RXFIFO_SHIFT                 (8U)
49042 /*! RXFIFO - Receive FIFO Size */
49043 #define LPSPI_PARAM_RXFIFO(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_RXFIFO_SHIFT)) & LPSPI_PARAM_RXFIFO_MASK)
49044 
49045 #define LPSPI_PARAM_PCSNUM_MASK                  (0xFF0000U)
49046 #define LPSPI_PARAM_PCSNUM_SHIFT                 (16U)
49047 /*! PCSNUM - PCS Number */
49048 #define LPSPI_PARAM_PCSNUM(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_PCSNUM_SHIFT)) & LPSPI_PARAM_PCSNUM_MASK)
49049 /*! @} */
49050 
49051 /*! @name CR - Control */
49052 /*! @{ */
49053 
49054 #define LPSPI_CR_MEN_MASK                        (0x1U)
49055 #define LPSPI_CR_MEN_SHIFT                       (0U)
49056 /*! MEN - Module Enable
49057  *  0b0..Disable
49058  *  0b1..Enable
49059  */
49060 #define LPSPI_CR_MEN(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_MEN_SHIFT)) & LPSPI_CR_MEN_MASK)
49061 
49062 #define LPSPI_CR_RST_MASK                        (0x2U)
49063 #define LPSPI_CR_RST_SHIFT                       (1U)
49064 /*! RST - Software Reset
49065  *  0b0..Not reset
49066  *  0b1..Reset
49067  */
49068 #define LPSPI_CR_RST(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RST_SHIFT)) & LPSPI_CR_RST_MASK)
49069 
49070 #define LPSPI_CR_DBGEN_MASK                      (0x8U)
49071 #define LPSPI_CR_DBGEN_SHIFT                     (3U)
49072 /*! DBGEN - Debug Enable
49073  *  0b0..Disable
49074  *  0b1..Enable
49075  */
49076 #define LPSPI_CR_DBGEN(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DBGEN_SHIFT)) & LPSPI_CR_DBGEN_MASK)
49077 
49078 #define LPSPI_CR_RTF_MASK                        (0x100U)
49079 #define LPSPI_CR_RTF_SHIFT                       (8U)
49080 /*! RTF - Reset Transmit FIFO
49081  *  0b0..No effect
49082  *  0b1..Reset
49083  */
49084 #define LPSPI_CR_RTF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RTF_SHIFT)) & LPSPI_CR_RTF_MASK)
49085 
49086 #define LPSPI_CR_RRF_MASK                        (0x200U)
49087 #define LPSPI_CR_RRF_SHIFT                       (9U)
49088 /*! RRF - Reset Receive FIFO
49089  *  0b0..No effect
49090  *  0b1..Reset
49091  */
49092 #define LPSPI_CR_RRF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RRF_SHIFT)) & LPSPI_CR_RRF_MASK)
49093 /*! @} */
49094 
49095 /*! @name SR - Status */
49096 /*! @{ */
49097 
49098 #define LPSPI_SR_TDF_MASK                        (0x1U)
49099 #define LPSPI_SR_TDF_SHIFT                       (0U)
49100 /*! TDF - Transmit Data Flag
49101  *  0b0..Transmit data not requested
49102  *  0b1..Transmit data requested
49103  */
49104 #define LPSPI_SR_TDF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TDF_SHIFT)) & LPSPI_SR_TDF_MASK)
49105 
49106 #define LPSPI_SR_RDF_MASK                        (0x2U)
49107 #define LPSPI_SR_RDF_SHIFT                       (1U)
49108 /*! RDF - Receive Data Flag
49109  *  0b0..Receive data not ready
49110  *  0b1..Receive data ready
49111  */
49112 #define LPSPI_SR_RDF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_RDF_SHIFT)) & LPSPI_SR_RDF_MASK)
49113 
49114 #define LPSPI_SR_WCF_MASK                        (0x100U)
49115 #define LPSPI_SR_WCF_SHIFT                       (8U)
49116 /*! WCF - Word Complete Flag
49117  *  0b0..Not complete
49118  *  0b1..Complete
49119  *  0b0..No effect
49120  *  0b1..Clear the flag
49121  */
49122 #define LPSPI_SR_WCF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_WCF_SHIFT)) & LPSPI_SR_WCF_MASK)
49123 
49124 #define LPSPI_SR_FCF_MASK                        (0x200U)
49125 #define LPSPI_SR_FCF_SHIFT                       (9U)
49126 /*! FCF - Frame Complete Flag
49127  *  0b0..Not complete
49128  *  0b1..Complete
49129  *  0b0..No effect
49130  *  0b1..Clear the flag
49131  */
49132 #define LPSPI_SR_FCF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_FCF_SHIFT)) & LPSPI_SR_FCF_MASK)
49133 
49134 #define LPSPI_SR_TCF_MASK                        (0x400U)
49135 #define LPSPI_SR_TCF_SHIFT                       (10U)
49136 /*! TCF - Transfer Complete Flag
49137  *  0b0..Not complete
49138  *  0b1..Complete
49139  *  0b0..No effect
49140  *  0b1..Clear the flag
49141  */
49142 #define LPSPI_SR_TCF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TCF_SHIFT)) & LPSPI_SR_TCF_MASK)
49143 
49144 #define LPSPI_SR_TEF_MASK                        (0x800U)
49145 #define LPSPI_SR_TEF_SHIFT                       (11U)
49146 /*! TEF - Transmit Error Flag
49147  *  0b0..No underrun
49148  *  0b1..Underrun
49149  *  0b0..No effect
49150  *  0b1..Clear the flag
49151  */
49152 #define LPSPI_SR_TEF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TEF_SHIFT)) & LPSPI_SR_TEF_MASK)
49153 
49154 #define LPSPI_SR_REF_MASK                        (0x1000U)
49155 #define LPSPI_SR_REF_SHIFT                       (12U)
49156 /*! REF - Receive Error Flag
49157  *  0b0..No overflow
49158  *  0b1..Overflow
49159  *  0b0..No effect
49160  *  0b1..Clear the flag
49161  */
49162 #define LPSPI_SR_REF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_REF_SHIFT)) & LPSPI_SR_REF_MASK)
49163 
49164 #define LPSPI_SR_DMF_MASK                        (0x2000U)
49165 #define LPSPI_SR_DMF_SHIFT                       (13U)
49166 /*! DMF - Data Match Flag
49167  *  0b0..No match
49168  *  0b1..Match
49169  *  0b0..No effect
49170  *  0b1..Clear the flag
49171  */
49172 #define LPSPI_SR_DMF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_DMF_SHIFT)) & LPSPI_SR_DMF_MASK)
49173 
49174 #define LPSPI_SR_MBF_MASK                        (0x1000000U)
49175 #define LPSPI_SR_MBF_SHIFT                       (24U)
49176 /*! MBF - Module Busy Flag
49177  *  0b0..LPSPI is idle
49178  *  0b1..LPSPI is busy
49179  */
49180 #define LPSPI_SR_MBF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_MBF_SHIFT)) & LPSPI_SR_MBF_MASK)
49181 /*! @} */
49182 
49183 /*! @name IER - Interrupt Enable */
49184 /*! @{ */
49185 
49186 #define LPSPI_IER_TDIE_MASK                      (0x1U)
49187 #define LPSPI_IER_TDIE_SHIFT                     (0U)
49188 /*! TDIE - Transmit Data Interrupt Enable
49189  *  0b0..Disable
49190  *  0b1..Enable
49191  */
49192 #define LPSPI_IER_TDIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TDIE_SHIFT)) & LPSPI_IER_TDIE_MASK)
49193 
49194 #define LPSPI_IER_RDIE_MASK                      (0x2U)
49195 #define LPSPI_IER_RDIE_SHIFT                     (1U)
49196 /*! RDIE - Receive Data Interrupt Enable
49197  *  0b0..Disable
49198  *  0b1..Enable
49199  */
49200 #define LPSPI_IER_RDIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_RDIE_SHIFT)) & LPSPI_IER_RDIE_MASK)
49201 
49202 #define LPSPI_IER_WCIE_MASK                      (0x100U)
49203 #define LPSPI_IER_WCIE_SHIFT                     (8U)
49204 /*! WCIE - Word Complete Interrupt Enable
49205  *  0b0..Disable
49206  *  0b1..Enable
49207  */
49208 #define LPSPI_IER_WCIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_WCIE_SHIFT)) & LPSPI_IER_WCIE_MASK)
49209 
49210 #define LPSPI_IER_FCIE_MASK                      (0x200U)
49211 #define LPSPI_IER_FCIE_SHIFT                     (9U)
49212 /*! FCIE - Frame Complete Interrupt Enable
49213  *  0b0..Disable
49214  *  0b1..Enable
49215  */
49216 #define LPSPI_IER_FCIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_FCIE_SHIFT)) & LPSPI_IER_FCIE_MASK)
49217 
49218 #define LPSPI_IER_TCIE_MASK                      (0x400U)
49219 #define LPSPI_IER_TCIE_SHIFT                     (10U)
49220 /*! TCIE - Transfer Complete Interrupt Enable
49221  *  0b0..Disable
49222  *  0b1..Enable
49223  */
49224 #define LPSPI_IER_TCIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TCIE_SHIFT)) & LPSPI_IER_TCIE_MASK)
49225 
49226 #define LPSPI_IER_TEIE_MASK                      (0x800U)
49227 #define LPSPI_IER_TEIE_SHIFT                     (11U)
49228 /*! TEIE - Transmit Error Interrupt Enable
49229  *  0b0..Disable
49230  *  0b1..Enable
49231  */
49232 #define LPSPI_IER_TEIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TEIE_SHIFT)) & LPSPI_IER_TEIE_MASK)
49233 
49234 #define LPSPI_IER_REIE_MASK                      (0x1000U)
49235 #define LPSPI_IER_REIE_SHIFT                     (12U)
49236 /*! REIE - Receive Error Interrupt Enable
49237  *  0b0..Disable
49238  *  0b1..Enable
49239  */
49240 #define LPSPI_IER_REIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_REIE_SHIFT)) & LPSPI_IER_REIE_MASK)
49241 
49242 #define LPSPI_IER_DMIE_MASK                      (0x2000U)
49243 #define LPSPI_IER_DMIE_SHIFT                     (13U)
49244 /*! DMIE - Data Match Interrupt Enable
49245  *  0b0..Disable
49246  *  0b1..Enable
49247  */
49248 #define LPSPI_IER_DMIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_DMIE_SHIFT)) & LPSPI_IER_DMIE_MASK)
49249 /*! @} */
49250 
49251 /*! @name DER - DMA Enable */
49252 /*! @{ */
49253 
49254 #define LPSPI_DER_TDDE_MASK                      (0x1U)
49255 #define LPSPI_DER_TDDE_SHIFT                     (0U)
49256 /*! TDDE - Transmit Data DMA Enable
49257  *  0b0..Disable
49258  *  0b1..Enable
49259  */
49260 #define LPSPI_DER_TDDE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_TDDE_SHIFT)) & LPSPI_DER_TDDE_MASK)
49261 
49262 #define LPSPI_DER_RDDE_MASK                      (0x2U)
49263 #define LPSPI_DER_RDDE_SHIFT                     (1U)
49264 /*! RDDE - Receive Data DMA Enable
49265  *  0b0..Disable
49266  *  0b1..Enable
49267  */
49268 #define LPSPI_DER_RDDE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_RDDE_SHIFT)) & LPSPI_DER_RDDE_MASK)
49269 
49270 #define LPSPI_DER_FCDE_MASK                      (0x200U)
49271 #define LPSPI_DER_FCDE_SHIFT                     (9U)
49272 /*! FCDE - Frame Complete DMA Enable
49273  *  0b0..Disable
49274  *  0b1..Enable
49275  */
49276 #define LPSPI_DER_FCDE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_FCDE_SHIFT)) & LPSPI_DER_FCDE_MASK)
49277 /*! @} */
49278 
49279 /*! @name CFGR0 - Configuration 0 */
49280 /*! @{ */
49281 
49282 #define LPSPI_CFGR0_HREN_MASK                    (0x1U)
49283 #define LPSPI_CFGR0_HREN_SHIFT                   (0U)
49284 /*! HREN - Host Request Enable
49285  *  0b0..Disable
49286  *  0b1..Enable
49287  */
49288 #define LPSPI_CFGR0_HREN(x)                      (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HREN_SHIFT)) & LPSPI_CFGR0_HREN_MASK)
49289 
49290 #define LPSPI_CFGR0_HRPOL_MASK                   (0x2U)
49291 #define LPSPI_CFGR0_HRPOL_SHIFT                  (1U)
49292 /*! HRPOL - Host Request Polarity
49293  *  0b0..Active high
49294  *  0b1..Active low
49295  */
49296 #define LPSPI_CFGR0_HRPOL(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRPOL_SHIFT)) & LPSPI_CFGR0_HRPOL_MASK)
49297 
49298 #define LPSPI_CFGR0_HRSEL_MASK                   (0x4U)
49299 #define LPSPI_CFGR0_HRSEL_SHIFT                  (2U)
49300 /*! HRSEL - Host Request Select
49301  *  0b0..HREQ pin
49302  *  0b1..Input trigger
49303  */
49304 #define LPSPI_CFGR0_HRSEL(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRSEL_SHIFT)) & LPSPI_CFGR0_HRSEL_MASK)
49305 
49306 #define LPSPI_CFGR0_HRDIR_MASK                   (0x8U)
49307 #define LPSPI_CFGR0_HRDIR_SHIFT                  (3U)
49308 /*! HRDIR - Host Request Direction
49309  *  0b0..Input
49310  *  0b1..Output
49311  */
49312 #define LPSPI_CFGR0_HRDIR(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRDIR_SHIFT)) & LPSPI_CFGR0_HRDIR_MASK)
49313 
49314 #define LPSPI_CFGR0_CIRFIFO_MASK                 (0x100U)
49315 #define LPSPI_CFGR0_CIRFIFO_SHIFT                (8U)
49316 /*! CIRFIFO - Circular FIFO Enable
49317  *  0b0..Disable
49318  *  0b1..Enable
49319  */
49320 #define LPSPI_CFGR0_CIRFIFO(x)                   (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_CIRFIFO_SHIFT)) & LPSPI_CFGR0_CIRFIFO_MASK)
49321 
49322 #define LPSPI_CFGR0_RDMO_MASK                    (0x200U)
49323 #define LPSPI_CFGR0_RDMO_SHIFT                   (9U)
49324 /*! RDMO - Receive Data Match Only
49325  *  0b0..Disable
49326  *  0b1..Enable
49327  */
49328 #define LPSPI_CFGR0_RDMO(x)                      (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_RDMO_SHIFT)) & LPSPI_CFGR0_RDMO_MASK)
49329 /*! @} */
49330 
49331 /*! @name CFGR1 - Configuration 1 */
49332 /*! @{ */
49333 
49334 #define LPSPI_CFGR1_MASTER_MASK                  (0x1U)
49335 #define LPSPI_CFGR1_MASTER_SHIFT                 (0U)
49336 /*! MASTER - Master Mode
49337  *  0b0..Slave mode
49338  *  0b1..Master mode
49339  */
49340 #define LPSPI_CFGR1_MASTER(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK)
49341 
49342 #define LPSPI_CFGR1_SAMPLE_MASK                  (0x2U)
49343 #define LPSPI_CFGR1_SAMPLE_SHIFT                 (1U)
49344 /*! SAMPLE - Sample Point
49345  *  0b0..SCK edge
49346  *  0b1..Delayed SCK edge
49347  */
49348 #define LPSPI_CFGR1_SAMPLE(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_SAMPLE_SHIFT)) & LPSPI_CFGR1_SAMPLE_MASK)
49349 
49350 #define LPSPI_CFGR1_AUTOPCS_MASK                 (0x4U)
49351 #define LPSPI_CFGR1_AUTOPCS_SHIFT                (2U)
49352 /*! AUTOPCS - Automatic PCS
49353  *  0b0..Disable
49354  *  0b1..Enable
49355  */
49356 #define LPSPI_CFGR1_AUTOPCS(x)                   (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_AUTOPCS_SHIFT)) & LPSPI_CFGR1_AUTOPCS_MASK)
49357 
49358 #define LPSPI_CFGR1_NOSTALL_MASK                 (0x8U)
49359 #define LPSPI_CFGR1_NOSTALL_SHIFT                (3U)
49360 /*! NOSTALL - No Stall
49361  *  0b0..Disable
49362  *  0b1..Enable
49363  */
49364 #define LPSPI_CFGR1_NOSTALL(x)                   (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_NOSTALL_SHIFT)) & LPSPI_CFGR1_NOSTALL_MASK)
49365 
49366 #define LPSPI_CFGR1_PARTIAL_MASK                 (0x10U)
49367 #define LPSPI_CFGR1_PARTIAL_SHIFT                (4U)
49368 /*! PARTIAL - Partial Enable
49369  *  0b0..Discard
49370  *  0b1..Store
49371  */
49372 #define LPSPI_CFGR1_PARTIAL(x)                   (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PARTIAL_SHIFT)) & LPSPI_CFGR1_PARTIAL_MASK)
49373 
49374 #define LPSPI_CFGR1_PCSPOL_MASK                  (0xF00U)
49375 #define LPSPI_CFGR1_PCSPOL_SHIFT                 (8U)
49376 /*! PCSPOL - Peripheral Chip Select Polarity
49377  *  0b0000..Active low
49378  *  0b0001..Active high
49379  */
49380 #define LPSPI_CFGR1_PCSPOL(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK)
49381 
49382 #define LPSPI_CFGR1_MATCFG_MASK                  (0x70000U)
49383 #define LPSPI_CFGR1_MATCFG_SHIFT                 (16U)
49384 /*! MATCFG - Match Configuration
49385  *  0b000..Match is disabled
49386  *  0b001..
49387  *  0b010..Match first data word with compare word
49388  *  0b011..Match any data word with compare word
49389  *  0b100..Sequential match, first data word
49390  *  0b101..Sequential match, any data word
49391  *  0b110..Match first data word (masked) with compare word (masked)
49392  *  0b111..Match any data word (masked) with compare word (masked)
49393  */
49394 #define LPSPI_CFGR1_MATCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK)
49395 
49396 #define LPSPI_CFGR1_PINCFG_MASK                  (0x3000000U)
49397 #define LPSPI_CFGR1_PINCFG_SHIFT                 (24U)
49398 /*! PINCFG - Pin Configuration
49399  *  0b00..SIN is used for input data; SOUT is used for output data
49400  *  0b01..SIN is used for both input and output data; only half-duplex serial transfers are supported
49401  *  0b10..SOUT is used for both input and output data; only half-duplex serial transfers are supported
49402  *  0b11..SOUT is used for input data; SIN is used for output data
49403  */
49404 #define LPSPI_CFGR1_PINCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PINCFG_SHIFT)) & LPSPI_CFGR1_PINCFG_MASK)
49405 
49406 #define LPSPI_CFGR1_OUTCFG_MASK                  (0x4000000U)
49407 #define LPSPI_CFGR1_OUTCFG_SHIFT                 (26U)
49408 /*! OUTCFG - Output Configuration
49409  *  0b0..Retain last value
49410  *  0b1..3-stated
49411  */
49412 #define LPSPI_CFGR1_OUTCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_OUTCFG_SHIFT)) & LPSPI_CFGR1_OUTCFG_MASK)
49413 
49414 #define LPSPI_CFGR1_PCSCFG_MASK                  (0x8000000U)
49415 #define LPSPI_CFGR1_PCSCFG_SHIFT                 (27U)
49416 /*! PCSCFG - Peripheral Chip Select Configuration
49417  *  0b0..PCS[3:2] configured for chip select function
49418  *  0b1..PCS[3:2] configured for half-duplex 4-bit transfers (PCS[3:2] = DATA[3:2])
49419  */
49420 #define LPSPI_CFGR1_PCSCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSCFG_SHIFT)) & LPSPI_CFGR1_PCSCFG_MASK)
49421 /*! @} */
49422 
49423 /*! @name DMR0 - Data Match 0 */
49424 /*! @{ */
49425 
49426 #define LPSPI_DMR0_MATCH0_MASK                   (0xFFFFFFFFU)
49427 #define LPSPI_DMR0_MATCH0_SHIFT                  (0U)
49428 /*! MATCH0 - Match 0 Value */
49429 #define LPSPI_DMR0_MATCH0(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR0_MATCH0_SHIFT)) & LPSPI_DMR0_MATCH0_MASK)
49430 /*! @} */
49431 
49432 /*! @name DMR1 - Data Match 1 */
49433 /*! @{ */
49434 
49435 #define LPSPI_DMR1_MATCH1_MASK                   (0xFFFFFFFFU)
49436 #define LPSPI_DMR1_MATCH1_SHIFT                  (0U)
49437 /*! MATCH1 - Match 1 Value */
49438 #define LPSPI_DMR1_MATCH1(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR1_MATCH1_SHIFT)) & LPSPI_DMR1_MATCH1_MASK)
49439 /*! @} */
49440 
49441 /*! @name CCR - Clock Configuration */
49442 /*! @{ */
49443 
49444 #define LPSPI_CCR_SCKDIV_MASK                    (0xFFU)
49445 #define LPSPI_CCR_SCKDIV_SHIFT                   (0U)
49446 /*! SCKDIV - SCK Divider */
49447 #define LPSPI_CCR_SCKDIV(x)                      (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKDIV_SHIFT)) & LPSPI_CCR_SCKDIV_MASK)
49448 
49449 #define LPSPI_CCR_DBT_MASK                       (0xFF00U)
49450 #define LPSPI_CCR_DBT_SHIFT                      (8U)
49451 /*! DBT - Delay Between Transfers */
49452 #define LPSPI_CCR_DBT(x)                         (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_DBT_SHIFT)) & LPSPI_CCR_DBT_MASK)
49453 
49454 #define LPSPI_CCR_PCSSCK_MASK                    (0xFF0000U)
49455 #define LPSPI_CCR_PCSSCK_SHIFT                   (16U)
49456 /*! PCSSCK - PCS-to-SCK Delay */
49457 #define LPSPI_CCR_PCSSCK(x)                      (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_PCSSCK_SHIFT)) & LPSPI_CCR_PCSSCK_MASK)
49458 
49459 #define LPSPI_CCR_SCKPCS_MASK                    (0xFF000000U)
49460 #define LPSPI_CCR_SCKPCS_SHIFT                   (24U)
49461 /*! SCKPCS - SCK-to-PCS Delay */
49462 #define LPSPI_CCR_SCKPCS(x)                      (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKPCS_SHIFT)) & LPSPI_CCR_SCKPCS_MASK)
49463 /*! @} */
49464 
49465 /*! @name CCR1 - Clock Configuration 1 */
49466 /*! @{ */
49467 
49468 #define LPSPI_CCR1_SCKSET_MASK                   (0xFFU)
49469 #define LPSPI_CCR1_SCKSET_SHIFT                  (0U)
49470 /*! SCKSET - SCK Setup */
49471 #define LPSPI_CCR1_SCKSET(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR1_SCKSET_SHIFT)) & LPSPI_CCR1_SCKSET_MASK)
49472 
49473 #define LPSPI_CCR1_SCKHLD_MASK                   (0xFF00U)
49474 #define LPSPI_CCR1_SCKHLD_SHIFT                  (8U)
49475 /*! SCKHLD - SCK Hold */
49476 #define LPSPI_CCR1_SCKHLD(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR1_SCKHLD_SHIFT)) & LPSPI_CCR1_SCKHLD_MASK)
49477 
49478 #define LPSPI_CCR1_PCSPCS_MASK                   (0xFF0000U)
49479 #define LPSPI_CCR1_PCSPCS_SHIFT                  (16U)
49480 /*! PCSPCS - PCS to PCS Delay */
49481 #define LPSPI_CCR1_PCSPCS(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR1_PCSPCS_SHIFT)) & LPSPI_CCR1_PCSPCS_MASK)
49482 
49483 #define LPSPI_CCR1_SCKSCK_MASK                   (0xFF000000U)
49484 #define LPSPI_CCR1_SCKSCK_SHIFT                  (24U)
49485 /*! SCKSCK - SCK Inter-Frame Delay */
49486 #define LPSPI_CCR1_SCKSCK(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR1_SCKSCK_SHIFT)) & LPSPI_CCR1_SCKSCK_MASK)
49487 /*! @} */
49488 
49489 /*! @name FCR - FIFO Control */
49490 /*! @{ */
49491 
49492 #define LPSPI_FCR_TXWATER_MASK                   (0x7U)
49493 #define LPSPI_FCR_TXWATER_SHIFT                  (0U)
49494 /*! TXWATER - Transmit FIFO Watermark */
49495 #define LPSPI_FCR_TXWATER(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_TXWATER_SHIFT)) & LPSPI_FCR_TXWATER_MASK)
49496 
49497 #define LPSPI_FCR_RXWATER_MASK                   (0x70000U)
49498 #define LPSPI_FCR_RXWATER_SHIFT                  (16U)
49499 /*! RXWATER - Receive FIFO Watermark */
49500 #define LPSPI_FCR_RXWATER(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_RXWATER_SHIFT)) & LPSPI_FCR_RXWATER_MASK)
49501 /*! @} */
49502 
49503 /*! @name FSR - FIFO Status */
49504 /*! @{ */
49505 
49506 #define LPSPI_FSR_TXCOUNT_MASK                   (0xFU)
49507 #define LPSPI_FSR_TXCOUNT_SHIFT                  (0U)
49508 /*! TXCOUNT - Transmit FIFO Count */
49509 #define LPSPI_FSR_TXCOUNT(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_TXCOUNT_SHIFT)) & LPSPI_FSR_TXCOUNT_MASK)
49510 
49511 #define LPSPI_FSR_RXCOUNT_MASK                   (0xF0000U)
49512 #define LPSPI_FSR_RXCOUNT_SHIFT                  (16U)
49513 /*! RXCOUNT - Receive FIFO Count */
49514 #define LPSPI_FSR_RXCOUNT(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_RXCOUNT_SHIFT)) & LPSPI_FSR_RXCOUNT_MASK)
49515 /*! @} */
49516 
49517 /*! @name TCR - Transmit Command */
49518 /*! @{ */
49519 
49520 #define LPSPI_TCR_FRAMESZ_MASK                   (0xFFFU)
49521 #define LPSPI_TCR_FRAMESZ_SHIFT                  (0U)
49522 /*! FRAMESZ - Frame Size */
49523 #define LPSPI_TCR_FRAMESZ(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_FRAMESZ_SHIFT)) & LPSPI_TCR_FRAMESZ_MASK)
49524 
49525 #define LPSPI_TCR_WIDTH_MASK                     (0x30000U)
49526 #define LPSPI_TCR_WIDTH_SHIFT                    (16U)
49527 /*! WIDTH - Transfer Width
49528  *  0b00..1-bit transfer
49529  *  0b01..2-bit transfer
49530  *  0b10..4-bit transfer
49531  *  0b11..Reserved
49532  */
49533 #define LPSPI_TCR_WIDTH(x)                       (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_WIDTH_SHIFT)) & LPSPI_TCR_WIDTH_MASK)
49534 
49535 #define LPSPI_TCR_TXMSK_MASK                     (0x40000U)
49536 #define LPSPI_TCR_TXMSK_SHIFT                    (18U)
49537 /*! TXMSK - Transmit Data Mask
49538  *  0b0..Normal transfer
49539  *  0b1..Mask transmit data
49540  */
49541 #define LPSPI_TCR_TXMSK(x)                       (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_TXMSK_SHIFT)) & LPSPI_TCR_TXMSK_MASK)
49542 
49543 #define LPSPI_TCR_RXMSK_MASK                     (0x80000U)
49544 #define LPSPI_TCR_RXMSK_SHIFT                    (19U)
49545 /*! RXMSK - Receive Data Mask
49546  *  0b0..Normal transfer
49547  *  0b1..Mask receive data
49548  */
49549 #define LPSPI_TCR_RXMSK(x)                       (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_RXMSK_SHIFT)) & LPSPI_TCR_RXMSK_MASK)
49550 
49551 #define LPSPI_TCR_CONTC_MASK                     (0x100000U)
49552 #define LPSPI_TCR_CONTC_SHIFT                    (20U)
49553 /*! CONTC - Continuing Command
49554  *  0b0..Command word for start of new transfer
49555  *  0b1..Command word for continuing transfer
49556  */
49557 #define LPSPI_TCR_CONTC(x)                       (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONTC_SHIFT)) & LPSPI_TCR_CONTC_MASK)
49558 
49559 #define LPSPI_TCR_CONT_MASK                      (0x200000U)
49560 #define LPSPI_TCR_CONT_SHIFT                     (21U)
49561 /*! CONT - Continuous Transfer
49562  *  0b0..Disable
49563  *  0b1..Enable
49564  */
49565 #define LPSPI_TCR_CONT(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONT_SHIFT)) & LPSPI_TCR_CONT_MASK)
49566 
49567 #define LPSPI_TCR_BYSW_MASK                      (0x400000U)
49568 #define LPSPI_TCR_BYSW_SHIFT                     (22U)
49569 /*! BYSW - Byte Swap
49570  *  0b0..Disable byte swap
49571  *  0b1..Enable byte swap
49572  */
49573 #define LPSPI_TCR_BYSW(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_BYSW_SHIFT)) & LPSPI_TCR_BYSW_MASK)
49574 
49575 #define LPSPI_TCR_LSBF_MASK                      (0x800000U)
49576 #define LPSPI_TCR_LSBF_SHIFT                     (23U)
49577 /*! LSBF - LSB First
49578  *  0b0..MSB first
49579  *  0b1..LSB first
49580  */
49581 #define LPSPI_TCR_LSBF(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_LSBF_SHIFT)) & LPSPI_TCR_LSBF_MASK)
49582 
49583 #define LPSPI_TCR_PCS_MASK                       (0x3000000U)
49584 #define LPSPI_TCR_PCS_SHIFT                      (24U)
49585 /*! PCS - Peripheral Chip Select
49586  *  0b00..Transfer using PCS[0]
49587  *  0b01..Transfer using PCS[1]
49588  *  0b10..Transfer using PCS[2]
49589  *  0b11..Transfer using PCS[3]
49590  */
49591 #define LPSPI_TCR_PCS(x)                         (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PCS_SHIFT)) & LPSPI_TCR_PCS_MASK)
49592 
49593 #define LPSPI_TCR_PRESCALE_MASK                  (0x38000000U)
49594 #define LPSPI_TCR_PRESCALE_SHIFT                 (27U)
49595 /*! PRESCALE - Prescaler Value
49596  *  0b000..Divide by 1
49597  *  0b001..Divide by 2
49598  *  0b010..Divide by 4
49599  *  0b011..Divide by 8
49600  *  0b100..Divide by 16
49601  *  0b101..Divide by 32
49602  *  0b110..Divide by 64
49603  *  0b111..Divide by 128
49604  */
49605 #define LPSPI_TCR_PRESCALE(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PRESCALE_SHIFT)) & LPSPI_TCR_PRESCALE_MASK)
49606 
49607 #define LPSPI_TCR_CPHA_MASK                      (0x40000000U)
49608 #define LPSPI_TCR_CPHA_SHIFT                     (30U)
49609 /*! CPHA - Clock Phase
49610  *  0b0..Captured
49611  *  0b1..Changed
49612  */
49613 #define LPSPI_TCR_CPHA(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPHA_SHIFT)) & LPSPI_TCR_CPHA_MASK)
49614 
49615 #define LPSPI_TCR_CPOL_MASK                      (0x80000000U)
49616 #define LPSPI_TCR_CPOL_SHIFT                     (31U)
49617 /*! CPOL - Clock Polarity
49618  *  0b0..Inactive low
49619  *  0b1..Inactive high
49620  */
49621 #define LPSPI_TCR_CPOL(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPOL_SHIFT)) & LPSPI_TCR_CPOL_MASK)
49622 /*! @} */
49623 
49624 /*! @name TDR - Transmit Data */
49625 /*! @{ */
49626 
49627 #define LPSPI_TDR_DATA_MASK                      (0xFFFFFFFFU)
49628 #define LPSPI_TDR_DATA_SHIFT                     (0U)
49629 /*! DATA - Transmit Data */
49630 #define LPSPI_TDR_DATA(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TDR_DATA_SHIFT)) & LPSPI_TDR_DATA_MASK)
49631 /*! @} */
49632 
49633 /*! @name RSR - Receive Status */
49634 /*! @{ */
49635 
49636 #define LPSPI_RSR_SOF_MASK                       (0x1U)
49637 #define LPSPI_RSR_SOF_SHIFT                      (0U)
49638 /*! SOF - Start of Frame
49639  *  0b0..Subsequent data word
49640  *  0b1..First data word
49641  */
49642 #define LPSPI_RSR_SOF(x)                         (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_SOF_SHIFT)) & LPSPI_RSR_SOF_MASK)
49643 
49644 #define LPSPI_RSR_RXEMPTY_MASK                   (0x2U)
49645 #define LPSPI_RSR_RXEMPTY_SHIFT                  (1U)
49646 /*! RXEMPTY - RX FIFO Empty
49647  *  0b0..Not empty
49648  *  0b1..Empty
49649  */
49650 #define LPSPI_RSR_RXEMPTY(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_RXEMPTY_SHIFT)) & LPSPI_RSR_RXEMPTY_MASK)
49651 /*! @} */
49652 
49653 /*! @name RDR - Receive Data */
49654 /*! @{ */
49655 
49656 #define LPSPI_RDR_DATA_MASK                      (0xFFFFFFFFU)
49657 #define LPSPI_RDR_DATA_SHIFT                     (0U)
49658 /*! DATA - Receive Data */
49659 #define LPSPI_RDR_DATA(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_RDR_DATA_SHIFT)) & LPSPI_RDR_DATA_MASK)
49660 /*! @} */
49661 
49662 /*! @name RDROR - Receive Data Read Only */
49663 /*! @{ */
49664 
49665 #define LPSPI_RDROR_DATA_MASK                    (0xFFFFFFFFU)
49666 #define LPSPI_RDROR_DATA_SHIFT                   (0U)
49667 /*! DATA - Receive Data */
49668 #define LPSPI_RDROR_DATA(x)                      (((uint32_t)(((uint32_t)(x)) << LPSPI_RDROR_DATA_SHIFT)) & LPSPI_RDROR_DATA_MASK)
49669 /*! @} */
49670 
49671 /*! @name TCBR - Transmit Command Burst */
49672 /*! @{ */
49673 
49674 #define LPSPI_TCBR_DATA_MASK                     (0xFFFFFFFFU)
49675 #define LPSPI_TCBR_DATA_SHIFT                    (0U)
49676 /*! DATA - Command Data */
49677 #define LPSPI_TCBR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPSPI_TCBR_DATA_SHIFT)) & LPSPI_TCBR_DATA_MASK)
49678 /*! @} */
49679 
49680 /*! @name TDBR - Transmit Data Burst */
49681 /*! @{ */
49682 
49683 #define LPSPI_TDBR_DATA_MASK                     (0xFFFFFFFFU)
49684 #define LPSPI_TDBR_DATA_SHIFT                    (0U)
49685 /*! DATA - Data */
49686 #define LPSPI_TDBR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPSPI_TDBR_DATA_SHIFT)) & LPSPI_TDBR_DATA_MASK)
49687 /*! @} */
49688 
49689 /* The count of LPSPI_TDBR */
49690 #define LPSPI_TDBR_COUNT                         (128U)
49691 
49692 /*! @name RDBR - Receive Data Burst */
49693 /*! @{ */
49694 
49695 #define LPSPI_RDBR_DATA_MASK                     (0xFFFFFFFFU)
49696 #define LPSPI_RDBR_DATA_SHIFT                    (0U)
49697 /*! DATA - Data */
49698 #define LPSPI_RDBR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPSPI_RDBR_DATA_SHIFT)) & LPSPI_RDBR_DATA_MASK)
49699 /*! @} */
49700 
49701 /* The count of LPSPI_RDBR */
49702 #define LPSPI_RDBR_COUNT                         (128U)
49703 
49704 
49705 /*!
49706  * @}
49707  */ /* end of group LPSPI_Register_Masks */
49708 
49709 
49710 /* LPSPI - Peripheral instance base addresses */
49711 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
49712   /** Peripheral LPSPI0 base address */
49713   #define LPSPI0_BASE                              (0x50092000u)
49714   /** Peripheral LPSPI0 base address */
49715   #define LPSPI0_BASE_NS                           (0x40092000u)
49716   /** Peripheral LPSPI0 base pointer */
49717   #define LPSPI0                                   ((LPSPI_Type *)LPSPI0_BASE)
49718   /** Peripheral LPSPI0 base pointer */
49719   #define LPSPI0_NS                                ((LPSPI_Type *)LPSPI0_BASE_NS)
49720   /** Peripheral LPSPI1 base address */
49721   #define LPSPI1_BASE                              (0x50093000u)
49722   /** Peripheral LPSPI1 base address */
49723   #define LPSPI1_BASE_NS                           (0x40093000u)
49724   /** Peripheral LPSPI1 base pointer */
49725   #define LPSPI1                                   ((LPSPI_Type *)LPSPI1_BASE)
49726   /** Peripheral LPSPI1 base pointer */
49727   #define LPSPI1_NS                                ((LPSPI_Type *)LPSPI1_BASE_NS)
49728   /** Peripheral LPSPI2 base address */
49729   #define LPSPI2_BASE                              (0x50094000u)
49730   /** Peripheral LPSPI2 base address */
49731   #define LPSPI2_BASE_NS                           (0x40094000u)
49732   /** Peripheral LPSPI2 base pointer */
49733   #define LPSPI2                                   ((LPSPI_Type *)LPSPI2_BASE)
49734   /** Peripheral LPSPI2 base pointer */
49735   #define LPSPI2_NS                                ((LPSPI_Type *)LPSPI2_BASE_NS)
49736   /** Peripheral LPSPI3 base address */
49737   #define LPSPI3_BASE                              (0x50095000u)
49738   /** Peripheral LPSPI3 base address */
49739   #define LPSPI3_BASE_NS                           (0x40095000u)
49740   /** Peripheral LPSPI3 base pointer */
49741   #define LPSPI3                                   ((LPSPI_Type *)LPSPI3_BASE)
49742   /** Peripheral LPSPI3 base pointer */
49743   #define LPSPI3_NS                                ((LPSPI_Type *)LPSPI3_BASE_NS)
49744   /** Peripheral LPSPI4 base address */
49745   #define LPSPI4_BASE                              (0x500B4000u)
49746   /** Peripheral LPSPI4 base address */
49747   #define LPSPI4_BASE_NS                           (0x400B4000u)
49748   /** Peripheral LPSPI4 base pointer */
49749   #define LPSPI4                                   ((LPSPI_Type *)LPSPI4_BASE)
49750   /** Peripheral LPSPI4 base pointer */
49751   #define LPSPI4_NS                                ((LPSPI_Type *)LPSPI4_BASE_NS)
49752   /** Peripheral LPSPI5 base address */
49753   #define LPSPI5_BASE                              (0x500B5000u)
49754   /** Peripheral LPSPI5 base address */
49755   #define LPSPI5_BASE_NS                           (0x400B5000u)
49756   /** Peripheral LPSPI5 base pointer */
49757   #define LPSPI5                                   ((LPSPI_Type *)LPSPI5_BASE)
49758   /** Peripheral LPSPI5 base pointer */
49759   #define LPSPI5_NS                                ((LPSPI_Type *)LPSPI5_BASE_NS)
49760   /** Peripheral LPSPI6 base address */
49761   #define LPSPI6_BASE                              (0x500B6000u)
49762   /** Peripheral LPSPI6 base address */
49763   #define LPSPI6_BASE_NS                           (0x400B6000u)
49764   /** Peripheral LPSPI6 base pointer */
49765   #define LPSPI6                                   ((LPSPI_Type *)LPSPI6_BASE)
49766   /** Peripheral LPSPI6 base pointer */
49767   #define LPSPI6_NS                                ((LPSPI_Type *)LPSPI6_BASE_NS)
49768   /** Peripheral LPSPI7 base address */
49769   #define LPSPI7_BASE                              (0x500B7000u)
49770   /** Peripheral LPSPI7 base address */
49771   #define LPSPI7_BASE_NS                           (0x400B7000u)
49772   /** Peripheral LPSPI7 base pointer */
49773   #define LPSPI7                                   ((LPSPI_Type *)LPSPI7_BASE)
49774   /** Peripheral LPSPI7 base pointer */
49775   #define LPSPI7_NS                                ((LPSPI_Type *)LPSPI7_BASE_NS)
49776   /** Peripheral LPSPI8 base address */
49777   #define LPSPI8_BASE                              (0x500B8000u)
49778   /** Peripheral LPSPI8 base address */
49779   #define LPSPI8_BASE_NS                           (0x400B8000u)
49780   /** Peripheral LPSPI8 base pointer */
49781   #define LPSPI8                                   ((LPSPI_Type *)LPSPI8_BASE)
49782   /** Peripheral LPSPI8 base pointer */
49783   #define LPSPI8_NS                                ((LPSPI_Type *)LPSPI8_BASE_NS)
49784   /** Peripheral LPSPI9 base address */
49785   #define LPSPI9_BASE                              (0x500B9000u)
49786   /** Peripheral LPSPI9 base address */
49787   #define LPSPI9_BASE_NS                           (0x400B9000u)
49788   /** Peripheral LPSPI9 base pointer */
49789   #define LPSPI9                                   ((LPSPI_Type *)LPSPI9_BASE)
49790   /** Peripheral LPSPI9 base pointer */
49791   #define LPSPI9_NS                                ((LPSPI_Type *)LPSPI9_BASE_NS)
49792   /** Array initializer of LPSPI peripheral base addresses */
49793   #define LPSPI_BASE_ADDRS                         { LPSPI0_BASE, LPSPI1_BASE, LPSPI2_BASE, LPSPI3_BASE, LPSPI4_BASE, LPSPI5_BASE, LPSPI6_BASE, LPSPI7_BASE, LPSPI8_BASE, LPSPI9_BASE }
49794   /** Array initializer of LPSPI peripheral base pointers */
49795   #define LPSPI_BASE_PTRS                          { LPSPI0, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPSPI5, LPSPI6, LPSPI7, LPSPI8, LPSPI9 }
49796   /** Array initializer of LPSPI peripheral base addresses */
49797   #define LPSPI_BASE_ADDRS_NS                      { LPSPI0_BASE_NS, LPSPI1_BASE_NS, LPSPI2_BASE_NS, LPSPI3_BASE_NS, LPSPI4_BASE_NS, LPSPI5_BASE_NS, LPSPI6_BASE_NS, LPSPI7_BASE_NS, LPSPI8_BASE_NS, LPSPI9_BASE_NS }
49798   /** Array initializer of LPSPI peripheral base pointers */
49799   #define LPSPI_BASE_PTRS_NS                       { LPSPI0_NS, LPSPI1_NS, LPSPI2_NS, LPSPI3_NS, LPSPI4_NS, LPSPI5_NS, LPSPI6_NS, LPSPI7_NS, LPSPI8_NS, LPSPI9_NS }
49800 #else
49801   /** Peripheral LPSPI0 base address */
49802   #define LPSPI0_BASE                              (0x40092000u)
49803   /** Peripheral LPSPI0 base pointer */
49804   #define LPSPI0                                   ((LPSPI_Type *)LPSPI0_BASE)
49805   /** Peripheral LPSPI1 base address */
49806   #define LPSPI1_BASE                              (0x40093000u)
49807   /** Peripheral LPSPI1 base pointer */
49808   #define LPSPI1                                   ((LPSPI_Type *)LPSPI1_BASE)
49809   /** Peripheral LPSPI2 base address */
49810   #define LPSPI2_BASE                              (0x40094000u)
49811   /** Peripheral LPSPI2 base pointer */
49812   #define LPSPI2                                   ((LPSPI_Type *)LPSPI2_BASE)
49813   /** Peripheral LPSPI3 base address */
49814   #define LPSPI3_BASE                              (0x40095000u)
49815   /** Peripheral LPSPI3 base pointer */
49816   #define LPSPI3                                   ((LPSPI_Type *)LPSPI3_BASE)
49817   /** Peripheral LPSPI4 base address */
49818   #define LPSPI4_BASE                              (0x400B4000u)
49819   /** Peripheral LPSPI4 base pointer */
49820   #define LPSPI4                                   ((LPSPI_Type *)LPSPI4_BASE)
49821   /** Peripheral LPSPI5 base address */
49822   #define LPSPI5_BASE                              (0x400B5000u)
49823   /** Peripheral LPSPI5 base pointer */
49824   #define LPSPI5                                   ((LPSPI_Type *)LPSPI5_BASE)
49825   /** Peripheral LPSPI6 base address */
49826   #define LPSPI6_BASE                              (0x400B6000u)
49827   /** Peripheral LPSPI6 base pointer */
49828   #define LPSPI6                                   ((LPSPI_Type *)LPSPI6_BASE)
49829   /** Peripheral LPSPI7 base address */
49830   #define LPSPI7_BASE                              (0x400B7000u)
49831   /** Peripheral LPSPI7 base pointer */
49832   #define LPSPI7                                   ((LPSPI_Type *)LPSPI7_BASE)
49833   /** Peripheral LPSPI8 base address */
49834   #define LPSPI8_BASE                              (0x400B8000u)
49835   /** Peripheral LPSPI8 base pointer */
49836   #define LPSPI8                                   ((LPSPI_Type *)LPSPI8_BASE)
49837   /** Peripheral LPSPI9 base address */
49838   #define LPSPI9_BASE                              (0x400B9000u)
49839   /** Peripheral LPSPI9 base pointer */
49840   #define LPSPI9                                   ((LPSPI_Type *)LPSPI9_BASE)
49841   /** Array initializer of LPSPI peripheral base addresses */
49842   #define LPSPI_BASE_ADDRS                         { LPSPI0_BASE, LPSPI1_BASE, LPSPI2_BASE, LPSPI3_BASE, LPSPI4_BASE, LPSPI5_BASE, LPSPI6_BASE, LPSPI7_BASE, LPSPI8_BASE, LPSPI9_BASE }
49843   /** Array initializer of LPSPI peripheral base pointers */
49844   #define LPSPI_BASE_PTRS                          { LPSPI0, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPSPI5, LPSPI6, LPSPI7, LPSPI8, LPSPI9 }
49845 #endif
49846 /** Interrupt vectors for the LPSPI peripheral type */
49847 #define LPSPI_IRQS                               { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn, LP_FLEXCOMM8_IRQn, LP_FLEXCOMM9_IRQn }
49848 
49849 /*!
49850  * @}
49851  */ /* end of group LPSPI_Peripheral_Access_Layer */
49852 
49853 
49854 /* ----------------------------------------------------------------------------
49855    -- LPTMR Peripheral Access Layer
49856    ---------------------------------------------------------------------------- */
49857 
49858 /*!
49859  * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
49860  * @{
49861  */
49862 
49863 /** LPTMR - Register Layout Typedef */
49864 typedef struct {
49865   __IO uint32_t CSR;                               /**< Control Status, offset: 0x0 */
49866   __IO uint32_t PSR;                               /**< Prescaler and Glitch Filter, offset: 0x4 */
49867   __IO uint32_t CMR;                               /**< Compare, offset: 0x8 */
49868   __IO uint32_t CNR;                               /**< Counter, offset: 0xC */
49869 } LPTMR_Type;
49870 
49871 /* ----------------------------------------------------------------------------
49872    -- LPTMR Register Masks
49873    ---------------------------------------------------------------------------- */
49874 
49875 /*!
49876  * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
49877  * @{
49878  */
49879 
49880 /*! @name CSR - Control Status */
49881 /*! @{ */
49882 
49883 #define LPTMR_CSR_TEN_MASK                       (0x1U)
49884 #define LPTMR_CSR_TEN_SHIFT                      (0U)
49885 /*! TEN - Timer Enable
49886  *  0b0..Disable
49887  *  0b1..Enable
49888  */
49889 #define LPTMR_CSR_TEN(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK)
49890 
49891 #define LPTMR_CSR_TMS_MASK                       (0x2U)
49892 #define LPTMR_CSR_TMS_SHIFT                      (1U)
49893 /*! TMS - Timer Mode Select
49894  *  0b0..Time Counter
49895  *  0b1..Pulse Counter
49896  */
49897 #define LPTMR_CSR_TMS(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK)
49898 
49899 #define LPTMR_CSR_TFC_MASK                       (0x4U)
49900 #define LPTMR_CSR_TFC_SHIFT                      (2U)
49901 /*! TFC - Timer Free-Running Counter
49902  *  0b0..Reset when TCF asserts
49903  *  0b1..Reset on overflow
49904  */
49905 #define LPTMR_CSR_TFC(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK)
49906 
49907 #define LPTMR_CSR_TPP_MASK                       (0x8U)
49908 #define LPTMR_CSR_TPP_SHIFT                      (3U)
49909 /*! TPP - Timer Pin Polarity
49910  *  0b0..Active-high
49911  *  0b1..Active-low
49912  */
49913 #define LPTMR_CSR_TPP(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK)
49914 
49915 #define LPTMR_CSR_TPS_MASK                       (0x30U)
49916 #define LPTMR_CSR_TPS_SHIFT                      (4U)
49917 /*! TPS - Timer Pin Select
49918  *  0b00..Input 0
49919  *  0b01..Input 1
49920  *  0b10..Input 2
49921  *  0b11..Input 3
49922  */
49923 #define LPTMR_CSR_TPS(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK)
49924 
49925 #define LPTMR_CSR_TIE_MASK                       (0x40U)
49926 #define LPTMR_CSR_TIE_SHIFT                      (6U)
49927 /*! TIE - Timer Interrupt Enable
49928  *  0b0..Disable
49929  *  0b1..Enable
49930  */
49931 #define LPTMR_CSR_TIE(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK)
49932 
49933 #define LPTMR_CSR_TCF_MASK                       (0x80U)
49934 #define LPTMR_CSR_TCF_SHIFT                      (7U)
49935 /*! TCF - Timer Compare Flag
49936  *  0b0..CNR != (CMR + 1)
49937  *  0b1..CNR = (CMR + 1)
49938  *  0b0..No effect
49939  *  0b1..Clear the flag
49940  */
49941 #define LPTMR_CSR_TCF(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK)
49942 
49943 #define LPTMR_CSR_TDRE_MASK                      (0x100U)
49944 #define LPTMR_CSR_TDRE_SHIFT                     (8U)
49945 /*! TDRE - Timer DMA Request Enable
49946  *  0b0..Disable
49947  *  0b1..Enable
49948  */
49949 #define LPTMR_CSR_TDRE(x)                        (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TDRE_SHIFT)) & LPTMR_CSR_TDRE_MASK)
49950 /*! @} */
49951 
49952 /*! @name PSR - Prescaler and Glitch Filter */
49953 /*! @{ */
49954 
49955 #define LPTMR_PSR_PCS_MASK                       (0x3U)
49956 #define LPTMR_PSR_PCS_SHIFT                      (0U)
49957 /*! PCS - Prescaler and Glitch Filter Clock Select
49958  *  0b00..Clock 0
49959  *  0b01..Clock 1
49960  *  0b10..Clock 2
49961  *  0b11..Clock 3
49962  */
49963 #define LPTMR_PSR_PCS(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK)
49964 
49965 #define LPTMR_PSR_PBYP_MASK                      (0x4U)
49966 #define LPTMR_PSR_PBYP_SHIFT                     (2U)
49967 /*! PBYP - Prescaler and Glitch Filter Bypass
49968  *  0b0..Prescaler and glitch filter enable
49969  *  0b1..Prescaler and glitch filter bypass
49970  */
49971 #define LPTMR_PSR_PBYP(x)                        (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK)
49972 
49973 #define LPTMR_PSR_PRESCALE_MASK                  (0x78U)
49974 #define LPTMR_PSR_PRESCALE_SHIFT                 (3U)
49975 /*! PRESCALE - Prescaler and Glitch Filter Value
49976  *  0b0000..Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration
49977  *  0b0001..Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after two rising clock edges
49978  *  0b0010..Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after four rising clock edges
49979  *  0b0011..Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after eight rising clock edges
49980  *  0b0100..Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges
49981  *  0b0101..Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges
49982  *  0b0110..Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges
49983  *  0b0111..Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges
49984  *  0b1000..Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges
49985  *  0b1001..Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges
49986  *  0b1010..Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges
49987  *  0b1011..Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges
49988  *  0b1100..Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges
49989  *  0b1101..Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges
49990  *  0b1110..Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges
49991  *  0b1111..Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges
49992  */
49993 #define LPTMR_PSR_PRESCALE(x)                    (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK)
49994 /*! @} */
49995 
49996 /*! @name CMR - Compare */
49997 /*! @{ */
49998 
49999 #define LPTMR_CMR_COMPARE_MASK                   (0xFFFFFFFFU)
50000 #define LPTMR_CMR_COMPARE_SHIFT                  (0U)
50001 /*! COMPARE - Compare Value */
50002 #define LPTMR_CMR_COMPARE(x)                     (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK)
50003 /*! @} */
50004 
50005 /*! @name CNR - Counter */
50006 /*! @{ */
50007 
50008 #define LPTMR_CNR_COUNTER_MASK                   (0xFFFFFFFFU)
50009 #define LPTMR_CNR_COUNTER_SHIFT                  (0U)
50010 /*! COUNTER - Counter Value */
50011 #define LPTMR_CNR_COUNTER(x)                     (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK)
50012 /*! @} */
50013 
50014 
50015 /*!
50016  * @}
50017  */ /* end of group LPTMR_Register_Masks */
50018 
50019 
50020 /* LPTMR - Peripheral instance base addresses */
50021 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
50022   /** Peripheral LPTMR0 base address */
50023   #define LPTMR0_BASE                              (0x5004A000u)
50024   /** Peripheral LPTMR0 base address */
50025   #define LPTMR0_BASE_NS                           (0x4004A000u)
50026   /** Peripheral LPTMR0 base pointer */
50027   #define LPTMR0                                   ((LPTMR_Type *)LPTMR0_BASE)
50028   /** Peripheral LPTMR0 base pointer */
50029   #define LPTMR0_NS                                ((LPTMR_Type *)LPTMR0_BASE_NS)
50030   /** Peripheral LPTMR1 base address */
50031   #define LPTMR1_BASE                              (0x5004B000u)
50032   /** Peripheral LPTMR1 base address */
50033   #define LPTMR1_BASE_NS                           (0x4004B000u)
50034   /** Peripheral LPTMR1 base pointer */
50035   #define LPTMR1                                   ((LPTMR_Type *)LPTMR1_BASE)
50036   /** Peripheral LPTMR1 base pointer */
50037   #define LPTMR1_NS                                ((LPTMR_Type *)LPTMR1_BASE_NS)
50038   /** Array initializer of LPTMR peripheral base addresses */
50039   #define LPTMR_BASE_ADDRS                         { LPTMR0_BASE, LPTMR1_BASE }
50040   /** Array initializer of LPTMR peripheral base pointers */
50041   #define LPTMR_BASE_PTRS                          { LPTMR0, LPTMR1 }
50042   /** Array initializer of LPTMR peripheral base addresses */
50043   #define LPTMR_BASE_ADDRS_NS                      { LPTMR0_BASE_NS, LPTMR1_BASE_NS }
50044   /** Array initializer of LPTMR peripheral base pointers */
50045   #define LPTMR_BASE_PTRS_NS                       { LPTMR0_NS, LPTMR1_NS }
50046 #else
50047   /** Peripheral LPTMR0 base address */
50048   #define LPTMR0_BASE                              (0x4004A000u)
50049   /** Peripheral LPTMR0 base pointer */
50050   #define LPTMR0                                   ((LPTMR_Type *)LPTMR0_BASE)
50051   /** Peripheral LPTMR1 base address */
50052   #define LPTMR1_BASE                              (0x4004B000u)
50053   /** Peripheral LPTMR1 base pointer */
50054   #define LPTMR1                                   ((LPTMR_Type *)LPTMR1_BASE)
50055   /** Array initializer of LPTMR peripheral base addresses */
50056   #define LPTMR_BASE_ADDRS                         { LPTMR0_BASE, LPTMR1_BASE }
50057   /** Array initializer of LPTMR peripheral base pointers */
50058   #define LPTMR_BASE_PTRS                          { LPTMR0, LPTMR1 }
50059 #endif
50060 /** Interrupt vectors for the LPTMR peripheral type */
50061 #define LPTMR_IRQS                               { LPTMR0_IRQn, LPTMR1_IRQn }
50062 
50063 /*!
50064  * @}
50065  */ /* end of group LPTMR_Peripheral_Access_Layer */
50066 
50067 
50068 /* ----------------------------------------------------------------------------
50069    -- LPUART Peripheral Access Layer
50070    ---------------------------------------------------------------------------- */
50071 
50072 /*!
50073  * @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer
50074  * @{
50075  */
50076 
50077 /** LPUART - Register Layout Typedef */
50078 typedef struct {
50079   __I  uint32_t VERID;                             /**< Version ID, offset: 0x0 */
50080   __I  uint32_t PARAM;                             /**< Parameter, offset: 0x4 */
50081   __IO uint32_t GLOBAL;                            /**< Global, offset: 0x8 */
50082   __IO uint32_t PINCFG;                            /**< Pin Configuration, offset: 0xC */
50083   __IO uint32_t BAUD;                              /**< Baud Rate, offset: 0x10 */
50084   __IO uint32_t STAT;                              /**< Status, offset: 0x14 */
50085   __IO uint32_t CTRL;                              /**< Control, offset: 0x18 */
50086   __IO uint32_t DATA;                              /**< Data, offset: 0x1C */
50087   __IO uint32_t MATCH;                             /**< Match Address, offset: 0x20 */
50088   __IO uint32_t MODIR;                             /**< MODEM IrDA, offset: 0x24 */
50089   __IO uint32_t FIFO;                              /**< FIFO, offset: 0x28 */
50090   __IO uint32_t WATER;                             /**< Watermark, offset: 0x2C */
50091   __I  uint32_t DATARO;                            /**< Data Read-Only, offset: 0x30 */
50092        uint8_t RESERVED_0[12];
50093   __IO uint32_t MCR;                               /**< MODEM Control, offset: 0x40 */
50094   __IO uint32_t MSR;                               /**< MODEM Status, offset: 0x44 */
50095   __IO uint32_t REIR;                              /**< Receiver Extended Idle, offset: 0x48 */
50096   __IO uint32_t TEIR;                              /**< Transmitter Extended Idle, offset: 0x4C */
50097   __IO uint32_t HDCR;                              /**< Half Duplex Control, offset: 0x50 */
50098        uint8_t RESERVED_1[4];
50099   __IO uint32_t TOCR;                              /**< Timeout Control, offset: 0x58 */
50100   __IO uint32_t TOSR;                              /**< Timeout Status, offset: 0x5C */
50101   __IO uint32_t TIMEOUT[4];                        /**< Timeout N, array offset: 0x60, array step: 0x4 */
50102        uint8_t RESERVED_2[400];
50103   __O  uint32_t TCBR[128];                         /**< Transmit Command Burst, array offset: 0x200, array step: 0x4 */
50104   __O  uint32_t TDBR[256];                         /**< Transmit Data Burst, array offset: 0x400, array step: 0x4 */
50105 } LPUART_Type;
50106 
50107 /* ----------------------------------------------------------------------------
50108    -- LPUART Register Masks
50109    ---------------------------------------------------------------------------- */
50110 
50111 /*!
50112  * @addtogroup LPUART_Register_Masks LPUART Register Masks
50113  * @{
50114  */
50115 
50116 /*! @name VERID - Version ID */
50117 /*! @{ */
50118 
50119 #define LPUART_VERID_FEATURE_MASK                (0xFFFFU)
50120 #define LPUART_VERID_FEATURE_SHIFT               (0U)
50121 /*! FEATURE - Feature Identification Number
50122  *  0b0000000000000001..Standard feature set
50123  *  0b0000000000000011..Standard feature set with MODEM and IrDA support
50124  *  0b0000000000000111..Enhanced feature set with full MODEM, IrDA, and enhanced idle detection
50125  */
50126 #define LPUART_VERID_FEATURE(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_FEATURE_SHIFT)) & LPUART_VERID_FEATURE_MASK)
50127 
50128 #define LPUART_VERID_MINOR_MASK                  (0xFF0000U)
50129 #define LPUART_VERID_MINOR_SHIFT                 (16U)
50130 /*! MINOR - Minor Version Number */
50131 #define LPUART_VERID_MINOR(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MINOR_SHIFT)) & LPUART_VERID_MINOR_MASK)
50132 
50133 #define LPUART_VERID_MAJOR_MASK                  (0xFF000000U)
50134 #define LPUART_VERID_MAJOR_SHIFT                 (24U)
50135 /*! MAJOR - Major Version Number */
50136 #define LPUART_VERID_MAJOR(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MAJOR_SHIFT)) & LPUART_VERID_MAJOR_MASK)
50137 /*! @} */
50138 
50139 /*! @name PARAM - Parameter */
50140 /*! @{ */
50141 
50142 #define LPUART_PARAM_TXFIFO_MASK                 (0xFFU)
50143 #define LPUART_PARAM_TXFIFO_SHIFT                (0U)
50144 /*! TXFIFO - Transmit FIFO Size */
50145 #define LPUART_PARAM_TXFIFO(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_TXFIFO_SHIFT)) & LPUART_PARAM_TXFIFO_MASK)
50146 
50147 #define LPUART_PARAM_RXFIFO_MASK                 (0xFF00U)
50148 #define LPUART_PARAM_RXFIFO_SHIFT                (8U)
50149 /*! RXFIFO - Receive FIFO Size */
50150 #define LPUART_PARAM_RXFIFO(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_RXFIFO_SHIFT)) & LPUART_PARAM_RXFIFO_MASK)
50151 /*! @} */
50152 
50153 /*! @name GLOBAL - Global */
50154 /*! @{ */
50155 
50156 #define LPUART_GLOBAL_RST_MASK                   (0x2U)
50157 #define LPUART_GLOBAL_RST_SHIFT                  (1U)
50158 /*! RST - Software Reset
50159  *  0b0..Not reset
50160  *  0b1..Reset
50161  */
50162 #define LPUART_GLOBAL_RST(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_GLOBAL_RST_SHIFT)) & LPUART_GLOBAL_RST_MASK)
50163 /*! @} */
50164 
50165 /*! @name PINCFG - Pin Configuration */
50166 /*! @{ */
50167 
50168 #define LPUART_PINCFG_TRGSEL_MASK                (0x3U)
50169 #define LPUART_PINCFG_TRGSEL_SHIFT               (0U)
50170 /*! TRGSEL - Trigger Select
50171  *  0b00..Input trigger disabled
50172  *  0b01..Input trigger used instead of the RXD pin input
50173  *  0b10..Input trigger used instead of the CTS_B pin input
50174  *  0b11..Input trigger used to modulate the TXD pin output, which (after TXINV configuration) is internally ANDed with the input trigger
50175  */
50176 #define LPUART_PINCFG_TRGSEL(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_PINCFG_TRGSEL_SHIFT)) & LPUART_PINCFG_TRGSEL_MASK)
50177 /*! @} */
50178 
50179 /*! @name BAUD - Baud Rate */
50180 /*! @{ */
50181 
50182 #define LPUART_BAUD_SBR_MASK                     (0x1FFFU)
50183 #define LPUART_BAUD_SBR_SHIFT                    (0U)
50184 /*! SBR - Baud Rate Modulo Divisor */
50185 #define LPUART_BAUD_SBR(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK)
50186 
50187 #define LPUART_BAUD_SBNS_MASK                    (0x2000U)
50188 #define LPUART_BAUD_SBNS_SHIFT                   (13U)
50189 /*! SBNS - Stop Bit Number Select
50190  *  0b0..One stop bit
50191  *  0b1..Two stop bits
50192  */
50193 #define LPUART_BAUD_SBNS(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK)
50194 
50195 #define LPUART_BAUD_RXEDGIE_MASK                 (0x4000U)
50196 #define LPUART_BAUD_RXEDGIE_SHIFT                (14U)
50197 /*! RXEDGIE - RX Input Active Edge Interrupt Enable
50198  *  0b0..Disable
50199  *  0b1..Enable
50200  */
50201 #define LPUART_BAUD_RXEDGIE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK)
50202 
50203 #define LPUART_BAUD_LBKDIE_MASK                  (0x8000U)
50204 #define LPUART_BAUD_LBKDIE_SHIFT                 (15U)
50205 /*! LBKDIE - LIN Break Detect Interrupt Enable
50206  *  0b0..Disable
50207  *  0b1..Enable
50208  */
50209 #define LPUART_BAUD_LBKDIE(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK)
50210 
50211 #define LPUART_BAUD_RESYNCDIS_MASK               (0x10000U)
50212 #define LPUART_BAUD_RESYNCDIS_SHIFT              (16U)
50213 /*! RESYNCDIS - Resynchronization Disable
50214  *  0b0..Enable
50215  *  0b1..Disable
50216  */
50217 #define LPUART_BAUD_RESYNCDIS(x)                 (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK)
50218 
50219 #define LPUART_BAUD_BOTHEDGE_MASK                (0x20000U)
50220 #define LPUART_BAUD_BOTHEDGE_SHIFT               (17U)
50221 /*! BOTHEDGE - Both Edge Sampling
50222  *  0b0..Rising edge
50223  *  0b1..Both rising and falling edges
50224  */
50225 #define LPUART_BAUD_BOTHEDGE(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK)
50226 
50227 #define LPUART_BAUD_MATCFG_MASK                  (0xC0000U)
50228 #define LPUART_BAUD_MATCFG_SHIFT                 (18U)
50229 /*! MATCFG - Match Configuration
50230  *  0b00..Address match wake-up
50231  *  0b01..Idle match wake-up
50232  *  0b10..Match on and match off
50233  *  0b11..Enables RWU on data match and match on or off for the transmitter CTS input
50234  */
50235 #define LPUART_BAUD_MATCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK)
50236 
50237 #define LPUART_BAUD_RIDMAE_MASK                  (0x100000U)
50238 #define LPUART_BAUD_RIDMAE_SHIFT                 (20U)
50239 /*! RIDMAE - Receiver Idle DMA Enable
50240  *  0b0..Disable
50241  *  0b1..Enable
50242  */
50243 #define LPUART_BAUD_RIDMAE(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RIDMAE_SHIFT)) & LPUART_BAUD_RIDMAE_MASK)
50244 
50245 #define LPUART_BAUD_RDMAE_MASK                   (0x200000U)
50246 #define LPUART_BAUD_RDMAE_SHIFT                  (21U)
50247 /*! RDMAE - Receiver Full DMA Enable
50248  *  0b0..Disable
50249  *  0b1..Enable
50250  */
50251 #define LPUART_BAUD_RDMAE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK)
50252 
50253 #define LPUART_BAUD_TDMAE_MASK                   (0x800000U)
50254 #define LPUART_BAUD_TDMAE_SHIFT                  (23U)
50255 /*! TDMAE - Transmitter DMA Enable
50256  *  0b0..Disable
50257  *  0b1..Enable
50258  */
50259 #define LPUART_BAUD_TDMAE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK)
50260 
50261 #define LPUART_BAUD_OSR_MASK                     (0x1F000000U)
50262 #define LPUART_BAUD_OSR_SHIFT                    (24U)
50263 /*! OSR - Oversampling Ratio
50264  *  0b00000..Results in an OSR of 16
50265  *  0b00001..Reserved
50266  *  0b00010..Reserved
50267  *  0b00011..Results in an OSR of 4 (requires BAUD[BOTHEDGE] to be 1)
50268  *  0b00100..Results in an OSR of 5 (requires BAUD[BOTHEDGE] to be 1)
50269  *  0b00101..Results in an OSR of 6 (requires BAUD[BOTHEDGE] to be 1)
50270  *  0b00110..Results in an OSR of 7 (requires BAUD[BOTHEDGE] to be 1)
50271  *  0b00111..Results in an OSR of 8
50272  *  0b01000..Results in an OSR of 9
50273  *  0b01001..Results in an OSR of 10
50274  *  0b01010..Results in an OSR of 11
50275  *  0b01011..Results in an OSR of 12
50276  *  0b01100..Results in an OSR of 13
50277  *  0b01101..Results in an OSR of 14
50278  *  0b01110..Results in an OSR of 15
50279  *  0b01111..Results in an OSR of 16
50280  *  0b10000..Results in an OSR of 17
50281  *  0b10001..Results in an OSR of 18
50282  *  0b10010..Results in an OSR of 19
50283  *  0b10011..Results in an OSR of 20
50284  *  0b10100..Results in an OSR of 21
50285  *  0b10101..Results in an OSR of 22
50286  *  0b10110..Results in an OSR of 23
50287  *  0b10111..Results in an OSR of 24
50288  *  0b11000..Results in an OSR of 25
50289  *  0b11001..Results in an OSR of 26
50290  *  0b11010..Results in an OSR of 27
50291  *  0b11011..Results in an OSR of 28
50292  *  0b11100..Results in an OSR of 29
50293  *  0b11101..Results in an OSR of 30
50294  *  0b11110..Results in an OSR of 31
50295  *  0b11111..Results in an OSR of 32
50296  */
50297 #define LPUART_BAUD_OSR(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK)
50298 
50299 #define LPUART_BAUD_M10_MASK                     (0x20000000U)
50300 #define LPUART_BAUD_M10_SHIFT                    (29U)
50301 /*! M10 - 10-Bit Mode Select
50302  *  0b0..Receiver and transmitter use 7-bit to 9-bit data characters
50303  *  0b1..Receiver and transmitter use 10-bit data characters
50304  */
50305 #define LPUART_BAUD_M10(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK)
50306 
50307 #define LPUART_BAUD_MAEN2_MASK                   (0x40000000U)
50308 #define LPUART_BAUD_MAEN2_SHIFT                  (30U)
50309 /*! MAEN2 - Match Address Mode Enable 2
50310  *  0b0..Disable
50311  *  0b1..Enable
50312  */
50313 #define LPUART_BAUD_MAEN2(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK)
50314 
50315 #define LPUART_BAUD_MAEN1_MASK                   (0x80000000U)
50316 #define LPUART_BAUD_MAEN1_SHIFT                  (31U)
50317 /*! MAEN1 - Match Address Mode Enable 1
50318  *  0b0..Disable
50319  *  0b1..Enable
50320  */
50321 #define LPUART_BAUD_MAEN1(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK)
50322 /*! @} */
50323 
50324 /*! @name STAT - Status */
50325 /*! @{ */
50326 
50327 #define LPUART_STAT_LBKFE_MASK                   (0x1U)
50328 #define LPUART_STAT_LBKFE_SHIFT                  (0U)
50329 /*! LBKFE - LIN Break Flag Enable
50330  *  0b0..Disable
50331  *  0b1..Enable
50332  */
50333 #define LPUART_STAT_LBKFE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKFE_SHIFT)) & LPUART_STAT_LBKFE_MASK)
50334 
50335 #define LPUART_STAT_AME_MASK                     (0x2U)
50336 #define LPUART_STAT_AME_SHIFT                    (1U)
50337 /*! AME - Address Mark Enable
50338  *  0b0..Disable
50339  *  0b1..Enable
50340  */
50341 #define LPUART_STAT_AME(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_AME_SHIFT)) & LPUART_STAT_AME_MASK)
50342 
50343 #define LPUART_STAT_MSF_MASK                     (0x100U)
50344 #define LPUART_STAT_MSF_SHIFT                    (8U)
50345 /*! MSF - MODEM Status Flag
50346  *  0b0..Field is 0
50347  *  0b1..Field is 1
50348  */
50349 #define LPUART_STAT_MSF(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSF_SHIFT)) & LPUART_STAT_MSF_MASK)
50350 
50351 #define LPUART_STAT_TSF_MASK                     (0x200U)
50352 #define LPUART_STAT_TSF_SHIFT                    (9U)
50353 /*! TSF - Timeout Status Flag
50354  *  0b0..Field is 0
50355  *  0b1..Field is 1
50356  */
50357 #define LPUART_STAT_TSF(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TSF_SHIFT)) & LPUART_STAT_TSF_MASK)
50358 
50359 #define LPUART_STAT_MA2F_MASK                    (0x4000U)
50360 #define LPUART_STAT_MA2F_SHIFT                   (14U)
50361 /*! MA2F - Match 2 Flag
50362  *  0b0..Not equal to MA2
50363  *  0b1..Equal to MA2
50364  *  0b0..No effect
50365  *  0b1..Clear the flag
50366  */
50367 #define LPUART_STAT_MA2F(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK)
50368 
50369 #define LPUART_STAT_MA1F_MASK                    (0x8000U)
50370 #define LPUART_STAT_MA1F_SHIFT                   (15U)
50371 /*! MA1F - Match 1 Flag
50372  *  0b0..Not equal to MA1
50373  *  0b1..Equal to MA1
50374  *  0b0..No effect
50375  *  0b1..Clear the flag
50376  */
50377 #define LPUART_STAT_MA1F(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK)
50378 
50379 #define LPUART_STAT_PF_MASK                      (0x10000U)
50380 #define LPUART_STAT_PF_SHIFT                     (16U)
50381 /*! PF - Parity Error Flag
50382  *  0b0..No parity error detected
50383  *  0b1..Parity error detected
50384  *  0b0..No effect
50385  *  0b1..Clear the flag
50386  */
50387 #define LPUART_STAT_PF(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK)
50388 
50389 #define LPUART_STAT_FE_MASK                      (0x20000U)
50390 #define LPUART_STAT_FE_SHIFT                     (17U)
50391 /*! FE - Framing Error Flag
50392  *  0b0..No framing error detected (this does not guarantee that the framing is correct)
50393  *  0b1..Framing error detected
50394  *  0b0..No effect
50395  *  0b1..Clear the flag
50396  */
50397 #define LPUART_STAT_FE(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK)
50398 
50399 #define LPUART_STAT_NF_MASK                      (0x40000U)
50400 #define LPUART_STAT_NF_SHIFT                     (18U)
50401 /*! NF - Noise Flag
50402  *  0b0..No noise detected
50403  *  0b1..Noise detected
50404  *  0b0..No effect
50405  *  0b1..Clear the flag
50406  */
50407 #define LPUART_STAT_NF(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK)
50408 
50409 #define LPUART_STAT_OR_MASK                      (0x80000U)
50410 #define LPUART_STAT_OR_SHIFT                     (19U)
50411 /*! OR - Receiver Overrun Flag
50412  *  0b0..No overrun
50413  *  0b1..Receive overrun (new LPUART data is lost)
50414  *  0b0..No effect
50415  *  0b1..Clear the flag
50416  */
50417 #define LPUART_STAT_OR(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK)
50418 
50419 #define LPUART_STAT_IDLE_MASK                    (0x100000U)
50420 #define LPUART_STAT_IDLE_SHIFT                   (20U)
50421 /*! IDLE - Idle Line Flag
50422  *  0b0..Idle line detected
50423  *  0b1..Idle line not detected
50424  *  0b0..No effect
50425  *  0b1..Clear the flag
50426  */
50427 #define LPUART_STAT_IDLE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK)
50428 
50429 #define LPUART_STAT_RDRF_MASK                    (0x200000U)
50430 #define LPUART_STAT_RDRF_SHIFT                   (21U)
50431 /*! RDRF - Receive Data Register Full Flag
50432  *  0b0..Equal to or less than watermark
50433  *  0b1..Greater than watermark
50434  */
50435 #define LPUART_STAT_RDRF(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK)
50436 
50437 #define LPUART_STAT_TC_MASK                      (0x400000U)
50438 #define LPUART_STAT_TC_SHIFT                     (22U)
50439 /*! TC - Transmission Complete Flag
50440  *  0b0..Transmitter active
50441  *  0b1..Transmitter idle
50442  */
50443 #define LPUART_STAT_TC(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK)
50444 
50445 #define LPUART_STAT_TDRE_MASK                    (0x800000U)
50446 #define LPUART_STAT_TDRE_SHIFT                   (23U)
50447 /*! TDRE - Transmit Data Register Empty Flag
50448  *  0b0..Greater than watermark
50449  *  0b1..Equal to or less than watermark
50450  */
50451 #define LPUART_STAT_TDRE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK)
50452 
50453 #define LPUART_STAT_RAF_MASK                     (0x1000000U)
50454 #define LPUART_STAT_RAF_SHIFT                    (24U)
50455 /*! RAF - Receiver Active Flag
50456  *  0b0..Idle, waiting for a start bit
50457  *  0b1..Receiver active (RXD pin input not idle)
50458  */
50459 #define LPUART_STAT_RAF(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK)
50460 
50461 #define LPUART_STAT_LBKDE_MASK                   (0x2000000U)
50462 #define LPUART_STAT_LBKDE_SHIFT                  (25U)
50463 /*! LBKDE - LIN Break Detection Enable
50464  *  0b0..Disable
50465  *  0b1..Enable
50466  */
50467 #define LPUART_STAT_LBKDE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK)
50468 
50469 #define LPUART_STAT_BRK13_MASK                   (0x4000000U)
50470 #define LPUART_STAT_BRK13_SHIFT                  (26U)
50471 /*! BRK13 - Break Character Generation Length
50472  *  0b0..9 to 13 bit times
50473  *  0b1..12 to 15 bit times
50474  */
50475 #define LPUART_STAT_BRK13(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK)
50476 
50477 #define LPUART_STAT_RWUID_MASK                   (0x8000000U)
50478 #define LPUART_STAT_RWUID_SHIFT                  (27U)
50479 /*! RWUID - Receive Wake Up Idle Detect
50480  *  0b0..STAT[IDLE] does not become 1
50481  *  0b1..STAT[IDLE] becomes 1
50482  */
50483 #define LPUART_STAT_RWUID(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK)
50484 
50485 #define LPUART_STAT_RXINV_MASK                   (0x10000000U)
50486 #define LPUART_STAT_RXINV_SHIFT                  (28U)
50487 /*! RXINV - Receive Data Inversion
50488  *  0b0..Inverted
50489  *  0b1..Not inverted
50490  */
50491 #define LPUART_STAT_RXINV(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK)
50492 
50493 #define LPUART_STAT_MSBF_MASK                    (0x20000000U)
50494 #define LPUART_STAT_MSBF_SHIFT                   (29U)
50495 /*! MSBF - MSB First
50496  *  0b0..LSB
50497  *  0b1..MSB
50498  */
50499 #define LPUART_STAT_MSBF(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK)
50500 
50501 #define LPUART_STAT_RXEDGIF_MASK                 (0x40000000U)
50502 #define LPUART_STAT_RXEDGIF_SHIFT                (30U)
50503 /*! RXEDGIF - RXD Pin Active Edge Interrupt Flag
50504  *  0b0..Not occurred
50505  *  0b1..Occurred
50506  *  0b0..No effect
50507  *  0b1..Clear the flag
50508  */
50509 #define LPUART_STAT_RXEDGIF(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK)
50510 
50511 #define LPUART_STAT_LBKDIF_MASK                  (0x80000000U)
50512 #define LPUART_STAT_LBKDIF_SHIFT                 (31U)
50513 /*! LBKDIF - LIN Break Detect Interrupt Flag
50514  *  0b0..Not detected
50515  *  0b1..Detected
50516  *  0b0..No effect
50517  *  0b1..Clear the flag
50518  */
50519 #define LPUART_STAT_LBKDIF(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK)
50520 /*! @} */
50521 
50522 /*! @name CTRL - Control */
50523 /*! @{ */
50524 
50525 #define LPUART_CTRL_PT_MASK                      (0x1U)
50526 #define LPUART_CTRL_PT_SHIFT                     (0U)
50527 /*! PT - Parity Type
50528  *  0b0..Even parity
50529  *  0b1..Odd parity
50530  */
50531 #define LPUART_CTRL_PT(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK)
50532 
50533 #define LPUART_CTRL_PE_MASK                      (0x2U)
50534 #define LPUART_CTRL_PE_SHIFT                     (1U)
50535 /*! PE - Parity Enable
50536  *  0b0..Disable
50537  *  0b1..Enable
50538  */
50539 #define LPUART_CTRL_PE(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK)
50540 
50541 #define LPUART_CTRL_ILT_MASK                     (0x4U)
50542 #define LPUART_CTRL_ILT_SHIFT                    (2U)
50543 /*! ILT - Idle Line Type Select
50544  *  0b0..After the start bit
50545  *  0b1..After the stop bit
50546  */
50547 #define LPUART_CTRL_ILT(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK)
50548 
50549 #define LPUART_CTRL_WAKE_MASK                    (0x8U)
50550 #define LPUART_CTRL_WAKE_SHIFT                   (3U)
50551 /*! WAKE - Receiver Wake-Up Method Select
50552  *  0b0..Idle
50553  *  0b1..Mark
50554  */
50555 #define LPUART_CTRL_WAKE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK)
50556 
50557 #define LPUART_CTRL_M_MASK                       (0x10U)
50558 #define LPUART_CTRL_M_SHIFT                      (4U)
50559 /*! M - 9-Bit Or 8-Bit Mode Select
50560  *  0b0..8-bit
50561  *  0b1..9-bit
50562  */
50563 #define LPUART_CTRL_M(x)                         (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK)
50564 
50565 #define LPUART_CTRL_RSRC_MASK                    (0x20U)
50566 #define LPUART_CTRL_RSRC_SHIFT                   (5U)
50567 /*! RSRC - Receiver Source Select
50568  *  0b0..Internal Loopback mode
50569  *  0b1..Single-wire mode
50570  */
50571 #define LPUART_CTRL_RSRC(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK)
50572 
50573 #define LPUART_CTRL_DOZEEN_MASK                  (0x40U)
50574 #define LPUART_CTRL_DOZEEN_SHIFT                 (6U)
50575 /*! DOZEEN - Doze Mode
50576  *  0b0..Enable
50577  *  0b1..Disable
50578  */
50579 #define LPUART_CTRL_DOZEEN(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK)
50580 
50581 #define LPUART_CTRL_LOOPS_MASK                   (0x80U)
50582 #define LPUART_CTRL_LOOPS_SHIFT                  (7U)
50583 /*! LOOPS - Loop Mode Select
50584  *  0b0..Normal operation: RXD and TXD use separate pins
50585  *  0b1..Loop mode or Single-Wire mode
50586  */
50587 #define LPUART_CTRL_LOOPS(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK)
50588 
50589 #define LPUART_CTRL_IDLECFG_MASK                 (0x700U)
50590 #define LPUART_CTRL_IDLECFG_SHIFT                (8U)
50591 /*! IDLECFG - Idle Configuration
50592  *  0b000..1
50593  *  0b001..2
50594  *  0b010..4
50595  *  0b011..8
50596  *  0b100..16
50597  *  0b101..32
50598  *  0b110..64
50599  *  0b111..128
50600  */
50601 #define LPUART_CTRL_IDLECFG(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK)
50602 
50603 #define LPUART_CTRL_M7_MASK                      (0x800U)
50604 #define LPUART_CTRL_M7_SHIFT                     (11U)
50605 /*! M7 - 7-Bit Mode Select
50606  *  0b0..8-bit to 10-bit
50607  *  0b1..7-bit
50608  */
50609 #define LPUART_CTRL_M7(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M7_SHIFT)) & LPUART_CTRL_M7_MASK)
50610 
50611 #define LPUART_CTRL_MA2IE_MASK                   (0x4000U)
50612 #define LPUART_CTRL_MA2IE_SHIFT                  (14U)
50613 /*! MA2IE - Match 2 (MA2F) Interrupt Enable
50614  *  0b0..Disable
50615  *  0b1..Enable
50616  */
50617 #define LPUART_CTRL_MA2IE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK)
50618 
50619 #define LPUART_CTRL_MA1IE_MASK                   (0x8000U)
50620 #define LPUART_CTRL_MA1IE_SHIFT                  (15U)
50621 /*! MA1IE - Match 1 (MA1F) Interrupt Enable
50622  *  0b0..Disable
50623  *  0b1..Enable
50624  */
50625 #define LPUART_CTRL_MA1IE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK)
50626 
50627 #define LPUART_CTRL_SBK_MASK                     (0x10000U)
50628 #define LPUART_CTRL_SBK_SHIFT                    (16U)
50629 /*! SBK - Send Break
50630  *  0b0..Normal transmitter operation
50631  *  0b1..Queue break character(s) to be sent
50632  */
50633 #define LPUART_CTRL_SBK(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK)
50634 
50635 #define LPUART_CTRL_RWU_MASK                     (0x20000U)
50636 #define LPUART_CTRL_RWU_SHIFT                    (17U)
50637 /*! RWU - Receiver Wake-Up Control
50638  *  0b0..Normal receiver operation
50639  *  0b1..LPUART receiver in standby, waiting for a wake-up condition
50640  */
50641 #define LPUART_CTRL_RWU(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK)
50642 
50643 #define LPUART_CTRL_RE_MASK                      (0x40000U)
50644 #define LPUART_CTRL_RE_SHIFT                     (18U)
50645 /*! RE - Receiver Enable
50646  *  0b0..Disable
50647  *  0b1..Enable
50648  */
50649 #define LPUART_CTRL_RE(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK)
50650 
50651 #define LPUART_CTRL_TE_MASK                      (0x80000U)
50652 #define LPUART_CTRL_TE_SHIFT                     (19U)
50653 /*! TE - Transmitter Enable
50654  *  0b0..Disable
50655  *  0b1..Enable
50656  */
50657 #define LPUART_CTRL_TE(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK)
50658 
50659 #define LPUART_CTRL_ILIE_MASK                    (0x100000U)
50660 #define LPUART_CTRL_ILIE_SHIFT                   (20U)
50661 /*! ILIE - Idle Line Interrupt Enable
50662  *  0b0..Disable
50663  *  0b1..Enable
50664  */
50665 #define LPUART_CTRL_ILIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK)
50666 
50667 #define LPUART_CTRL_RIE_MASK                     (0x200000U)
50668 #define LPUART_CTRL_RIE_SHIFT                    (21U)
50669 /*! RIE - Receiver Interrupt Enable
50670  *  0b0..Disable
50671  *  0b1..Enable
50672  */
50673 #define LPUART_CTRL_RIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK)
50674 
50675 #define LPUART_CTRL_TCIE_MASK                    (0x400000U)
50676 #define LPUART_CTRL_TCIE_SHIFT                   (22U)
50677 /*! TCIE - Transmission Complete Interrupt Enable
50678  *  0b0..Disable
50679  *  0b1..Enable
50680  */
50681 #define LPUART_CTRL_TCIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK)
50682 
50683 #define LPUART_CTRL_TIE_MASK                     (0x800000U)
50684 #define LPUART_CTRL_TIE_SHIFT                    (23U)
50685 /*! TIE - Transmit Interrupt Enable
50686  *  0b0..Disable
50687  *  0b1..Enable
50688  */
50689 #define LPUART_CTRL_TIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK)
50690 
50691 #define LPUART_CTRL_PEIE_MASK                    (0x1000000U)
50692 #define LPUART_CTRL_PEIE_SHIFT                   (24U)
50693 /*! PEIE - Parity Error Interrupt Enable
50694  *  0b0..Disable
50695  *  0b1..Enable
50696  */
50697 #define LPUART_CTRL_PEIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK)
50698 
50699 #define LPUART_CTRL_FEIE_MASK                    (0x2000000U)
50700 #define LPUART_CTRL_FEIE_SHIFT                   (25U)
50701 /*! FEIE - Framing Error Interrupt Enable
50702  *  0b0..Disable
50703  *  0b1..Enable
50704  */
50705 #define LPUART_CTRL_FEIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK)
50706 
50707 #define LPUART_CTRL_NEIE_MASK                    (0x4000000U)
50708 #define LPUART_CTRL_NEIE_SHIFT                   (26U)
50709 /*! NEIE - Noise Error Interrupt Enable
50710  *  0b0..Disable
50711  *  0b1..Enable
50712  */
50713 #define LPUART_CTRL_NEIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK)
50714 
50715 #define LPUART_CTRL_ORIE_MASK                    (0x8000000U)
50716 #define LPUART_CTRL_ORIE_SHIFT                   (27U)
50717 /*! ORIE - Overrun Interrupt Enable
50718  *  0b0..Disable
50719  *  0b1..Enable
50720  */
50721 #define LPUART_CTRL_ORIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK)
50722 
50723 #define LPUART_CTRL_TXINV_MASK                   (0x10000000U)
50724 #define LPUART_CTRL_TXINV_SHIFT                  (28U)
50725 /*! TXINV - Transmit Data Inversion
50726  *  0b0..Not inverted
50727  *  0b1..Inverted
50728  */
50729 #define LPUART_CTRL_TXINV(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK)
50730 
50731 #define LPUART_CTRL_TXDIR_MASK                   (0x20000000U)
50732 #define LPUART_CTRL_TXDIR_SHIFT                  (29U)
50733 /*! TXDIR - TXD Pin Direction in Single-Wire Mode
50734  *  0b0..Input
50735  *  0b1..Output
50736  */
50737 #define LPUART_CTRL_TXDIR(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK)
50738 
50739 #define LPUART_CTRL_R9T8_MASK                    (0x40000000U)
50740 #define LPUART_CTRL_R9T8_SHIFT                   (30U)
50741 /*! R9T8 - Receive Bit 9 Transmit Bit 8 */
50742 #define LPUART_CTRL_R9T8(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK)
50743 
50744 #define LPUART_CTRL_R8T9_MASK                    (0x80000000U)
50745 #define LPUART_CTRL_R8T9_SHIFT                   (31U)
50746 /*! R8T9 - Receive Bit 8 Transmit Bit 9 */
50747 #define LPUART_CTRL_R8T9(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK)
50748 /*! @} */
50749 
50750 /*! @name DATA - Data */
50751 /*! @{ */
50752 
50753 #define LPUART_DATA_R0T0_MASK                    (0x1U)
50754 #define LPUART_DATA_R0T0_SHIFT                   (0U)
50755 /*! R0T0 - Read receive FIFO bit 0 or write transmit FIFO bit 0 */
50756 #define LPUART_DATA_R0T0(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK)
50757 
50758 #define LPUART_DATA_R1T1_MASK                    (0x2U)
50759 #define LPUART_DATA_R1T1_SHIFT                   (1U)
50760 /*! R1T1 - Read receive FIFO bit 1 or write transmit FIFO bit 1 */
50761 #define LPUART_DATA_R1T1(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK)
50762 
50763 #define LPUART_DATA_R2T2_MASK                    (0x4U)
50764 #define LPUART_DATA_R2T2_SHIFT                   (2U)
50765 /*! R2T2 - Read receive FIFO bit 2 or write transmit FIFO bit 2 */
50766 #define LPUART_DATA_R2T2(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK)
50767 
50768 #define LPUART_DATA_R3T3_MASK                    (0x8U)
50769 #define LPUART_DATA_R3T3_SHIFT                   (3U)
50770 /*! R3T3 - Read receive FIFO bit 3 or write transmit FIFO bit 3 */
50771 #define LPUART_DATA_R3T3(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK)
50772 
50773 #define LPUART_DATA_R4T4_MASK                    (0x10U)
50774 #define LPUART_DATA_R4T4_SHIFT                   (4U)
50775 /*! R4T4 - Read receive FIFO bit 4 or write transmit FIFO bit 4 */
50776 #define LPUART_DATA_R4T4(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK)
50777 
50778 #define LPUART_DATA_R5T5_MASK                    (0x20U)
50779 #define LPUART_DATA_R5T5_SHIFT                   (5U)
50780 /*! R5T5 - Read receive FIFO bit 5 or write transmit FIFO bit 5 */
50781 #define LPUART_DATA_R5T5(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK)
50782 
50783 #define LPUART_DATA_R6T6_MASK                    (0x40U)
50784 #define LPUART_DATA_R6T6_SHIFT                   (6U)
50785 /*! R6T6 - Read receive FIFO bit 6 or write transmit FIFO bit 6 */
50786 #define LPUART_DATA_R6T6(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK)
50787 
50788 #define LPUART_DATA_R7T7_MASK                    (0x80U)
50789 #define LPUART_DATA_R7T7_SHIFT                   (7U)
50790 /*! R7T7 - Read receive FIFO bit 7 or write transmit FIFO bit 7 */
50791 #define LPUART_DATA_R7T7(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK)
50792 
50793 #define LPUART_DATA_R8T8_MASK                    (0x100U)
50794 #define LPUART_DATA_R8T8_SHIFT                   (8U)
50795 /*! R8T8 - Read receive FIFO bit 8 or write transmit FIFO bit 8 */
50796 #define LPUART_DATA_R8T8(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK)
50797 
50798 #define LPUART_DATA_R9T9_MASK                    (0x200U)
50799 #define LPUART_DATA_R9T9_SHIFT                   (9U)
50800 /*! R9T9 - Read receive FIFO bit 9 or write transmit FIFO bit 9 */
50801 #define LPUART_DATA_R9T9(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK)
50802 
50803 #define LPUART_DATA_LINBRK_MASK                  (0x400U)
50804 #define LPUART_DATA_LINBRK_SHIFT                 (10U)
50805 /*! LINBRK - LIN Break
50806  *  0b0..Not detected
50807  *  0b1..Detected
50808  */
50809 #define LPUART_DATA_LINBRK(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_LINBRK_SHIFT)) & LPUART_DATA_LINBRK_MASK)
50810 
50811 #define LPUART_DATA_IDLINE_MASK                  (0x800U)
50812 #define LPUART_DATA_IDLINE_SHIFT                 (11U)
50813 /*! IDLINE - Idle Line
50814  *  0b0..Not idle
50815  *  0b1..Idle
50816  */
50817 #define LPUART_DATA_IDLINE(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK)
50818 
50819 #define LPUART_DATA_RXEMPT_MASK                  (0x1000U)
50820 #define LPUART_DATA_RXEMPT_SHIFT                 (12U)
50821 /*! RXEMPT - Receive Buffer Empty
50822  *  0b0..Valid data
50823  *  0b1..Invalid data and empty
50824  */
50825 #define LPUART_DATA_RXEMPT(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK)
50826 
50827 #define LPUART_DATA_FRETSC_MASK                  (0x2000U)
50828 #define LPUART_DATA_FRETSC_SHIFT                 (13U)
50829 /*! FRETSC - Frame Error Transmit Special Character
50830  *  0b0..Received without a frame error on reads or transmits a normal character on writes
50831  *  0b1..Received with a frame error on reads or transmits an idle or break character on writes
50832  */
50833 #define LPUART_DATA_FRETSC(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK)
50834 
50835 #define LPUART_DATA_PARITYE_MASK                 (0x4000U)
50836 #define LPUART_DATA_PARITYE_SHIFT                (14U)
50837 /*! PARITYE - Parity Error
50838  *  0b0..Received without a parity error
50839  *  0b1..Received with a parity error
50840  */
50841 #define LPUART_DATA_PARITYE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK)
50842 
50843 #define LPUART_DATA_NOISY_MASK                   (0x8000U)
50844 #define LPUART_DATA_NOISY_SHIFT                  (15U)
50845 /*! NOISY - Noisy Data Received
50846  *  0b0..Received without noise
50847  *  0b1..Received with noise
50848  */
50849 #define LPUART_DATA_NOISY(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK)
50850 /*! @} */
50851 
50852 /*! @name MATCH - Match Address */
50853 /*! @{ */
50854 
50855 #define LPUART_MATCH_MA1_MASK                    (0x3FFU)
50856 #define LPUART_MATCH_MA1_SHIFT                   (0U)
50857 /*! MA1 - Match Address 1 */
50858 #define LPUART_MATCH_MA1(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK)
50859 
50860 #define LPUART_MATCH_MA2_MASK                    (0x3FF0000U)
50861 #define LPUART_MATCH_MA2_SHIFT                   (16U)
50862 /*! MA2 - Match Address 2 */
50863 #define LPUART_MATCH_MA2(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK)
50864 /*! @} */
50865 
50866 /*! @name MODIR - MODEM IrDA */
50867 /*! @{ */
50868 
50869 #define LPUART_MODIR_TXCTSE_MASK                 (0x1U)
50870 #define LPUART_MODIR_TXCTSE_SHIFT                (0U)
50871 /*! TXCTSE - Transmitter CTS Enable
50872  *  0b0..Disable
50873  *  0b1..Enable
50874  */
50875 #define LPUART_MODIR_TXCTSE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK)
50876 
50877 #define LPUART_MODIR_TXRTSE_MASK                 (0x2U)
50878 #define LPUART_MODIR_TXRTSE_SHIFT                (1U)
50879 /*! TXRTSE - Transmitter RTS Enable
50880  *  0b0..Disable
50881  *  0b1..Enable
50882  */
50883 #define LPUART_MODIR_TXRTSE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK)
50884 
50885 #define LPUART_MODIR_TXRTSPOL_MASK               (0x4U)
50886 #define LPUART_MODIR_TXRTSPOL_SHIFT              (2U)
50887 /*! TXRTSPOL - Transmitter RTS Polarity
50888  *  0b0..Active low
50889  *  0b1..Active high
50890  */
50891 #define LPUART_MODIR_TXRTSPOL(x)                 (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK)
50892 
50893 #define LPUART_MODIR_RXRTSE_MASK                 (0x8U)
50894 #define LPUART_MODIR_RXRTSE_SHIFT                (3U)
50895 /*! RXRTSE - Receiver RTS Enable
50896  *  0b0..Disable
50897  *  0b1..Enable
50898  */
50899 #define LPUART_MODIR_RXRTSE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK)
50900 
50901 #define LPUART_MODIR_TXCTSC_MASK                 (0x10U)
50902 #define LPUART_MODIR_TXCTSC_SHIFT                (4U)
50903 /*! TXCTSC - Transmit CTS Configuration
50904  *  0b0..Sampled at the start of each character
50905  *  0b1..Sampled when the transmitter is idle
50906  */
50907 #define LPUART_MODIR_TXCTSC(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK)
50908 
50909 #define LPUART_MODIR_TXCTSSRC_MASK               (0x20U)
50910 #define LPUART_MODIR_TXCTSSRC_SHIFT              (5U)
50911 /*! TXCTSSRC - Transmit CTS Source
50912  *  0b0..The CTS_B pin
50913  *  0b1..An internal connection to the receiver address match result
50914  */
50915 #define LPUART_MODIR_TXCTSSRC(x)                 (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK)
50916 
50917 #define LPUART_MODIR_RTSWATER_MASK               (0x700U)
50918 #define LPUART_MODIR_RTSWATER_SHIFT              (8U)
50919 /*! RTSWATER - Receive RTS Configuration */
50920 #define LPUART_MODIR_RTSWATER(x)                 (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RTSWATER_SHIFT)) & LPUART_MODIR_RTSWATER_MASK)
50921 
50922 #define LPUART_MODIR_TNP_MASK                    (0x30000U)
50923 #define LPUART_MODIR_TNP_SHIFT                   (16U)
50924 /*! TNP - Transmitter Narrow Pulse
50925  *  0b00..1 / OSR
50926  *  0b01..2 / OSR
50927  *  0b10..3 / OSR
50928  *  0b11..4 / OSR
50929  */
50930 #define LPUART_MODIR_TNP(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK)
50931 
50932 #define LPUART_MODIR_IREN_MASK                   (0x40000U)
50933 #define LPUART_MODIR_IREN_SHIFT                  (18U)
50934 /*! IREN - IR Enable
50935  *  0b0..Disable
50936  *  0b1..Enable
50937  */
50938 #define LPUART_MODIR_IREN(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK)
50939 /*! @} */
50940 
50941 /*! @name FIFO - FIFO */
50942 /*! @{ */
50943 
50944 #define LPUART_FIFO_RXFIFOSIZE_MASK              (0x7U)
50945 #define LPUART_FIFO_RXFIFOSIZE_SHIFT             (0U)
50946 /*! RXFIFOSIZE - Receive FIFO Buffer Depth
50947  *  0b000..1
50948  *  0b001..4
50949  *  0b010..8
50950  *  0b011..16
50951  *  0b100..32
50952  *  0b101..64
50953  *  0b110..128
50954  *  0b111..256
50955  */
50956 #define LPUART_FIFO_RXFIFOSIZE(x)                (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFIFOSIZE_SHIFT)) & LPUART_FIFO_RXFIFOSIZE_MASK)
50957 
50958 #define LPUART_FIFO_RXFE_MASK                    (0x8U)
50959 #define LPUART_FIFO_RXFE_SHIFT                   (3U)
50960 /*! RXFE - Receive FIFO Enable
50961  *  0b0..Disable
50962  *  0b1..Enable
50963  */
50964 #define LPUART_FIFO_RXFE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFE_SHIFT)) & LPUART_FIFO_RXFE_MASK)
50965 
50966 #define LPUART_FIFO_TXFIFOSIZE_MASK              (0x70U)
50967 #define LPUART_FIFO_TXFIFOSIZE_SHIFT             (4U)
50968 /*! TXFIFOSIZE - Transmit FIFO Buffer Depth
50969  *  0b000..1
50970  *  0b001..4
50971  *  0b010..8
50972  *  0b011..16
50973  *  0b100..32
50974  *  0b101..64
50975  *  0b110..128
50976  *  0b111..256
50977  */
50978 #define LPUART_FIFO_TXFIFOSIZE(x)                (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFIFOSIZE_SHIFT)) & LPUART_FIFO_TXFIFOSIZE_MASK)
50979 
50980 #define LPUART_FIFO_TXFE_MASK                    (0x80U)
50981 #define LPUART_FIFO_TXFE_SHIFT                   (7U)
50982 /*! TXFE - Transmit FIFO Enable
50983  *  0b0..Disable
50984  *  0b1..Enable
50985  */
50986 #define LPUART_FIFO_TXFE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFE_SHIFT)) & LPUART_FIFO_TXFE_MASK)
50987 
50988 #define LPUART_FIFO_RXUFE_MASK                   (0x100U)
50989 #define LPUART_FIFO_RXUFE_SHIFT                  (8U)
50990 /*! RXUFE - Receive FIFO Underflow Interrupt Enable
50991  *  0b0..Disable
50992  *  0b1..Enable
50993  */
50994 #define LPUART_FIFO_RXUFE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUFE_SHIFT)) & LPUART_FIFO_RXUFE_MASK)
50995 
50996 #define LPUART_FIFO_TXOFE_MASK                   (0x200U)
50997 #define LPUART_FIFO_TXOFE_SHIFT                  (9U)
50998 /*! TXOFE - Transmit FIFO Overflow Interrupt Enable
50999  *  0b0..Disable
51000  *  0b1..Enable
51001  */
51002 #define LPUART_FIFO_TXOFE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOFE_SHIFT)) & LPUART_FIFO_TXOFE_MASK)
51003 
51004 #define LPUART_FIFO_RXIDEN_MASK                  (0x1C00U)
51005 #define LPUART_FIFO_RXIDEN_SHIFT                 (10U)
51006 /*! RXIDEN - Receiver Idle Empty Enable
51007  *  0b000..Disable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle
51008  *  0b001..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for one character
51009  *  0b010..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for two characters
51010  *  0b011..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for four characters
51011  *  0b100..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for eight characters
51012  *  0b101..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for 16 characters
51013  *  0b110..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for 32 characters
51014  *  0b111..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for 64 characters
51015  */
51016 #define LPUART_FIFO_RXIDEN(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXIDEN_SHIFT)) & LPUART_FIFO_RXIDEN_MASK)
51017 
51018 #define LPUART_FIFO_RXFLUSH_MASK                 (0x4000U)
51019 #define LPUART_FIFO_RXFLUSH_SHIFT                (14U)
51020 /*! RXFLUSH - Receive FIFO Flush
51021  *  0b0..No effect
51022  *  0b1..All data flushed out
51023  */
51024 #define LPUART_FIFO_RXFLUSH(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFLUSH_SHIFT)) & LPUART_FIFO_RXFLUSH_MASK)
51025 
51026 #define LPUART_FIFO_TXFLUSH_MASK                 (0x8000U)
51027 #define LPUART_FIFO_TXFLUSH_SHIFT                (15U)
51028 /*! TXFLUSH - Transmit FIFO Flush
51029  *  0b0..No effect
51030  *  0b1..All data flushed out
51031  */
51032 #define LPUART_FIFO_TXFLUSH(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFLUSH_SHIFT)) & LPUART_FIFO_TXFLUSH_MASK)
51033 
51034 #define LPUART_FIFO_RXUF_MASK                    (0x10000U)
51035 #define LPUART_FIFO_RXUF_SHIFT                   (16U)
51036 /*! RXUF - Receiver FIFO Underflow Flag
51037  *  0b0..No underflow
51038  *  0b1..Underflow
51039  *  0b0..No effect
51040  *  0b1..Clear the flag
51041  */
51042 #define LPUART_FIFO_RXUF(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUF_SHIFT)) & LPUART_FIFO_RXUF_MASK)
51043 
51044 #define LPUART_FIFO_TXOF_MASK                    (0x20000U)
51045 #define LPUART_FIFO_TXOF_SHIFT                   (17U)
51046 /*! TXOF - Transmitter FIFO Overflow Flag
51047  *  0b0..No overflow
51048  *  0b1..Overflow
51049  *  0b0..No effect
51050  *  0b1..Clear the flag
51051  */
51052 #define LPUART_FIFO_TXOF(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOF_SHIFT)) & LPUART_FIFO_TXOF_MASK)
51053 
51054 #define LPUART_FIFO_RXEMPT_MASK                  (0x400000U)
51055 #define LPUART_FIFO_RXEMPT_SHIFT                 (22U)
51056 /*! RXEMPT - Receive FIFO Or Buffer Empty
51057  *  0b0..Not empty
51058  *  0b1..Empty
51059  */
51060 #define LPUART_FIFO_RXEMPT(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXEMPT_SHIFT)) & LPUART_FIFO_RXEMPT_MASK)
51061 
51062 #define LPUART_FIFO_TXEMPT_MASK                  (0x800000U)
51063 #define LPUART_FIFO_TXEMPT_SHIFT                 (23U)
51064 /*! TXEMPT - Transmit FIFO Or Buffer Empty
51065  *  0b0..Not empty
51066  *  0b1..Empty
51067  */
51068 #define LPUART_FIFO_TXEMPT(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXEMPT_SHIFT)) & LPUART_FIFO_TXEMPT_MASK)
51069 /*! @} */
51070 
51071 /*! @name WATER - Watermark */
51072 /*! @{ */
51073 
51074 #define LPUART_WATER_TXWATER_MASK                (0x7U)
51075 #define LPUART_WATER_TXWATER_SHIFT               (0U)
51076 /*! TXWATER - Transmit Watermark */
51077 #define LPUART_WATER_TXWATER(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXWATER_SHIFT)) & LPUART_WATER_TXWATER_MASK)
51078 
51079 #define LPUART_WATER_TXCOUNT_MASK                (0xF00U)
51080 #define LPUART_WATER_TXCOUNT_SHIFT               (8U)
51081 /*! TXCOUNT - Transmit Counter */
51082 #define LPUART_WATER_TXCOUNT(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXCOUNT_SHIFT)) & LPUART_WATER_TXCOUNT_MASK)
51083 
51084 #define LPUART_WATER_RXWATER_MASK                (0x70000U)
51085 #define LPUART_WATER_RXWATER_SHIFT               (16U)
51086 /*! RXWATER - Receive Watermark */
51087 #define LPUART_WATER_RXWATER(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXWATER_SHIFT)) & LPUART_WATER_RXWATER_MASK)
51088 
51089 #define LPUART_WATER_RXCOUNT_MASK                (0xF000000U)
51090 #define LPUART_WATER_RXCOUNT_SHIFT               (24U)
51091 /*! RXCOUNT - Receive Counter */
51092 #define LPUART_WATER_RXCOUNT(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXCOUNT_SHIFT)) & LPUART_WATER_RXCOUNT_MASK)
51093 /*! @} */
51094 
51095 /*! @name DATARO - Data Read-Only */
51096 /*! @{ */
51097 
51098 #define LPUART_DATARO_DATA_MASK                  (0xFFFFU)
51099 #define LPUART_DATARO_DATA_SHIFT                 (0U)
51100 /*! DATA - Receive Data */
51101 #define LPUART_DATARO_DATA(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_DATARO_DATA_SHIFT)) & LPUART_DATARO_DATA_MASK)
51102 /*! @} */
51103 
51104 /*! @name MCR - MODEM Control */
51105 /*! @{ */
51106 
51107 #define LPUART_MCR_CTS_MASK                      (0x1U)
51108 #define LPUART_MCR_CTS_SHIFT                     (0U)
51109 /*! CTS - Clear To Send
51110  *  0b0..Disable interrupt
51111  *  0b1..Enable interrupt
51112  */
51113 #define LPUART_MCR_CTS(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_MCR_CTS_SHIFT)) & LPUART_MCR_CTS_MASK)
51114 
51115 #define LPUART_MCR_DSR_MASK                      (0x2U)
51116 #define LPUART_MCR_DSR_SHIFT                     (1U)
51117 /*! DSR - Data Set Ready
51118  *  0b0..Disable interrupt
51119  *  0b1..Enable interrupt
51120  */
51121 #define LPUART_MCR_DSR(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_MCR_DSR_SHIFT)) & LPUART_MCR_DSR_MASK)
51122 
51123 #define LPUART_MCR_RIN_MASK                      (0x4U)
51124 #define LPUART_MCR_RIN_SHIFT                     (2U)
51125 /*! RIN - Ring Indicator
51126  *  0b0..Disable interrupt
51127  *  0b1..Enable interrupt
51128  */
51129 #define LPUART_MCR_RIN(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_MCR_RIN_SHIFT)) & LPUART_MCR_RIN_MASK)
51130 
51131 #define LPUART_MCR_DCD_MASK                      (0x8U)
51132 #define LPUART_MCR_DCD_SHIFT                     (3U)
51133 /*! DCD - Data Carrier Detect
51134  *  0b0..Disable interrupt
51135  *  0b1..Enable interrupt
51136  */
51137 #define LPUART_MCR_DCD(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_MCR_DCD_SHIFT)) & LPUART_MCR_DCD_MASK)
51138 
51139 #define LPUART_MCR_DTR_MASK                      (0x100U)
51140 #define LPUART_MCR_DTR_SHIFT                     (8U)
51141 /*! DTR - Data Terminal Ready
51142  *  0b0..Logic one
51143  *  0b1..Logic zero
51144  */
51145 #define LPUART_MCR_DTR(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_MCR_DTR_SHIFT)) & LPUART_MCR_DTR_MASK)
51146 
51147 #define LPUART_MCR_RTS_MASK                      (0x200U)
51148 #define LPUART_MCR_RTS_SHIFT                     (9U)
51149 /*! RTS - Request To Send
51150  *  0b0..Logic one
51151  *  0b1..Logic zero
51152  */
51153 #define LPUART_MCR_RTS(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_MCR_RTS_SHIFT)) & LPUART_MCR_RTS_MASK)
51154 /*! @} */
51155 
51156 /*! @name MSR - MODEM Status */
51157 /*! @{ */
51158 
51159 #define LPUART_MSR_DCTS_MASK                     (0x1U)
51160 #define LPUART_MSR_DCTS_SHIFT                    (0U)
51161 /*! DCTS - Delta Clear To Send
51162  *  0b0..Did not change state
51163  *  0b1..Changed state
51164  *  0b0..No effect
51165  *  0b1..Clear the flag
51166  */
51167 #define LPUART_MSR_DCTS(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_DCTS_SHIFT)) & LPUART_MSR_DCTS_MASK)
51168 
51169 #define LPUART_MSR_DDSR_MASK                     (0x2U)
51170 #define LPUART_MSR_DDSR_SHIFT                    (1U)
51171 /*! DDSR - Delta Data Set Ready
51172  *  0b0..Did not change state
51173  *  0b1..Changed state
51174  *  0b0..No effect
51175  *  0b1..Clear the flag
51176  */
51177 #define LPUART_MSR_DDSR(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_DDSR_SHIFT)) & LPUART_MSR_DDSR_MASK)
51178 
51179 #define LPUART_MSR_DRI_MASK                      (0x4U)
51180 #define LPUART_MSR_DRI_SHIFT                     (2U)
51181 /*! DRI - Delta Ring Indicator
51182  *  0b0..Did not change state
51183  *  0b1..Changed state
51184  *  0b0..No effect
51185  *  0b1..Clear the flag
51186  */
51187 #define LPUART_MSR_DRI(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_DRI_SHIFT)) & LPUART_MSR_DRI_MASK)
51188 
51189 #define LPUART_MSR_DDCD_MASK                     (0x8U)
51190 #define LPUART_MSR_DDCD_SHIFT                    (3U)
51191 /*! DDCD - Delta Data Carrier Detect
51192  *  0b0..Did not change state
51193  *  0b1..Changed state
51194  *  0b0..No effect
51195  *  0b1..Clear the flag
51196  */
51197 #define LPUART_MSR_DDCD(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_DDCD_SHIFT)) & LPUART_MSR_DDCD_MASK)
51198 
51199 #define LPUART_MSR_CTS_MASK                      (0x10U)
51200 #define LPUART_MSR_CTS_SHIFT                     (4U)
51201 /*! CTS - Clear To Send
51202  *  0b0..Logic one
51203  *  0b1..Logic zero
51204  */
51205 #define LPUART_MSR_CTS(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_CTS_SHIFT)) & LPUART_MSR_CTS_MASK)
51206 
51207 #define LPUART_MSR_DSR_MASK                      (0x20U)
51208 #define LPUART_MSR_DSR_SHIFT                     (5U)
51209 /*! DSR - Data Set Ready
51210  *  0b0..Logic one
51211  *  0b1..Logic zero
51212  */
51213 #define LPUART_MSR_DSR(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_DSR_SHIFT)) & LPUART_MSR_DSR_MASK)
51214 
51215 #define LPUART_MSR_RIN_MASK                      (0x40U)
51216 #define LPUART_MSR_RIN_SHIFT                     (6U)
51217 /*! RIN - Ring Indicator
51218  *  0b0..Logic one
51219  *  0b1..Logic zero
51220  */
51221 #define LPUART_MSR_RIN(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_RIN_SHIFT)) & LPUART_MSR_RIN_MASK)
51222 
51223 #define LPUART_MSR_DCD_MASK                      (0x80U)
51224 #define LPUART_MSR_DCD_SHIFT                     (7U)
51225 /*! DCD - Data Carrier Detect
51226  *  0b0..Logic one
51227  *  0b1..Logic zero
51228  */
51229 #define LPUART_MSR_DCD(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_DCD_SHIFT)) & LPUART_MSR_DCD_MASK)
51230 /*! @} */
51231 
51232 /*! @name REIR - Receiver Extended Idle */
51233 /*! @{ */
51234 
51235 #define LPUART_REIR_IDTIME_MASK                  (0x3FFFU)
51236 #define LPUART_REIR_IDTIME_SHIFT                 (0U)
51237 /*! IDTIME - Idle Time */
51238 #define LPUART_REIR_IDTIME(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_REIR_IDTIME_SHIFT)) & LPUART_REIR_IDTIME_MASK)
51239 /*! @} */
51240 
51241 /*! @name TEIR - Transmitter Extended Idle */
51242 /*! @{ */
51243 
51244 #define LPUART_TEIR_IDTIME_MASK                  (0x3FFFU)
51245 #define LPUART_TEIR_IDTIME_SHIFT                 (0U)
51246 /*! IDTIME - Idle Time */
51247 #define LPUART_TEIR_IDTIME(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_TEIR_IDTIME_SHIFT)) & LPUART_TEIR_IDTIME_MASK)
51248 /*! @} */
51249 
51250 /*! @name HDCR - Half Duplex Control */
51251 /*! @{ */
51252 
51253 #define LPUART_HDCR_TXSTALL_MASK                 (0x1U)
51254 #define LPUART_HDCR_TXSTALL_SHIFT                (0U)
51255 /*! TXSTALL - Transmit Stall
51256  *  0b0..No effect
51257  *  0b1..Does not become busy
51258  */
51259 #define LPUART_HDCR_TXSTALL(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_HDCR_TXSTALL_SHIFT)) & LPUART_HDCR_TXSTALL_MASK)
51260 
51261 #define LPUART_HDCR_RXSEL_MASK                   (0x2U)
51262 #define LPUART_HDCR_RXSEL_SHIFT                  (1U)
51263 /*! RXSEL - Receive Select
51264  *  0b0..RXD
51265  *  0b1..TXD
51266  */
51267 #define LPUART_HDCR_RXSEL(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_HDCR_RXSEL_SHIFT)) & LPUART_HDCR_RXSEL_MASK)
51268 
51269 #define LPUART_HDCR_RXWRMSK_MASK                 (0x4U)
51270 #define LPUART_HDCR_RXWRMSK_SHIFT                (2U)
51271 /*! RXWRMSK - Receive FIFO Write Mask
51272  *  0b0..Do not mask
51273  *  0b1..Mask
51274  */
51275 #define LPUART_HDCR_RXWRMSK(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_HDCR_RXWRMSK_SHIFT)) & LPUART_HDCR_RXWRMSK_MASK)
51276 
51277 #define LPUART_HDCR_RXMSK_MASK                   (0x8U)
51278 #define LPUART_HDCR_RXMSK_SHIFT                  (3U)
51279 /*! RXMSK - Receive Mask
51280  *  0b0..Do not mask
51281  *  0b1..Mask
51282  */
51283 #define LPUART_HDCR_RXMSK(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_HDCR_RXMSK_SHIFT)) & LPUART_HDCR_RXMSK_MASK)
51284 
51285 #define LPUART_HDCR_RTSEXT_MASK                  (0xFF00U)
51286 #define LPUART_HDCR_RTSEXT_SHIFT                 (8U)
51287 /*! RTSEXT - RTS Extended */
51288 #define LPUART_HDCR_RTSEXT(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_HDCR_RTSEXT_SHIFT)) & LPUART_HDCR_RTSEXT_MASK)
51289 /*! @} */
51290 
51291 /*! @name TOCR - Timeout Control */
51292 /*! @{ */
51293 
51294 #define LPUART_TOCR_TOEN_MASK                    (0xFU)
51295 #define LPUART_TOCR_TOEN_SHIFT                   (0U)
51296 /*! TOEN - Timeout Enable */
51297 #define LPUART_TOCR_TOEN(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_TOCR_TOEN_SHIFT)) & LPUART_TOCR_TOEN_MASK)
51298 
51299 #define LPUART_TOCR_TOIE_MASK                    (0xF00U)
51300 #define LPUART_TOCR_TOIE_SHIFT                   (8U)
51301 /*! TOIE - Timeout Interrupt Enable */
51302 #define LPUART_TOCR_TOIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_TOCR_TOIE_SHIFT)) & LPUART_TOCR_TOIE_MASK)
51303 /*! @} */
51304 
51305 /*! @name TOSR - Timeout Status */
51306 /*! @{ */
51307 
51308 #define LPUART_TOSR_TOZ_MASK                     (0xFU)
51309 #define LPUART_TOSR_TOZ_SHIFT                    (0U)
51310 /*! TOZ - Timeout Zero */
51311 #define LPUART_TOSR_TOZ(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_TOSR_TOZ_SHIFT)) & LPUART_TOSR_TOZ_MASK)
51312 
51313 #define LPUART_TOSR_TOF_MASK                     (0xF00U)
51314 #define LPUART_TOSR_TOF_SHIFT                    (8U)
51315 /*! TOF - Timeout Flag
51316  *  0b0000..Not occurred
51317  *  0b0001..Occurred
51318  *  0b0000..No effect
51319  *  0b0001..Clear the flag
51320  */
51321 #define LPUART_TOSR_TOF(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_TOSR_TOF_SHIFT)) & LPUART_TOSR_TOF_MASK)
51322 /*! @} */
51323 
51324 /*! @name TIMEOUT - Timeout N */
51325 /*! @{ */
51326 
51327 #define LPUART_TIMEOUT_TIMEOUT_MASK              (0x3FFFU)
51328 #define LPUART_TIMEOUT_TIMEOUT_SHIFT             (0U)
51329 /*! TIMEOUT - Timeout Value */
51330 #define LPUART_TIMEOUT_TIMEOUT(x)                (((uint32_t)(((uint32_t)(x)) << LPUART_TIMEOUT_TIMEOUT_SHIFT)) & LPUART_TIMEOUT_TIMEOUT_MASK)
51331 
51332 #define LPUART_TIMEOUT_CFG_MASK                  (0xC0000000U)
51333 #define LPUART_TIMEOUT_CFG_SHIFT                 (30U)
51334 /*! CFG - Idle Configuration
51335  *  0b00..Becomes 1 after timeout characters are received
51336  *  0b01..Becomes 1 when idle for timeout bit clocks
51337  *  0b10..Becomes 1 when idle for timeout bit clocks following the next character
51338  *  0b11..Becomes 1 when idle for at least timeout bit clocks, but a new character is detected before the extended idle timeout is reached
51339  */
51340 #define LPUART_TIMEOUT_CFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_TIMEOUT_CFG_SHIFT)) & LPUART_TIMEOUT_CFG_MASK)
51341 /*! @} */
51342 
51343 /* The count of LPUART_TIMEOUT */
51344 #define LPUART_TIMEOUT_COUNT                     (4U)
51345 
51346 /*! @name TCBR - Transmit Command Burst */
51347 /*! @{ */
51348 
51349 #define LPUART_TCBR_DATA_MASK                    (0xFFFFU)
51350 #define LPUART_TCBR_DATA_SHIFT                   (0U)
51351 /*! DATA - Data */
51352 #define LPUART_TCBR_DATA(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_TCBR_DATA_SHIFT)) & LPUART_TCBR_DATA_MASK)
51353 /*! @} */
51354 
51355 /* The count of LPUART_TCBR */
51356 #define LPUART_TCBR_COUNT                        (128U)
51357 
51358 /*! @name TDBR - Transmit Data Burst */
51359 /*! @{ */
51360 
51361 #define LPUART_TDBR_DATA0_MASK                   (0xFFU)
51362 #define LPUART_TDBR_DATA0_SHIFT                  (0U)
51363 /*! DATA0 - Data0 */
51364 #define LPUART_TDBR_DATA0(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_TDBR_DATA0_SHIFT)) & LPUART_TDBR_DATA0_MASK)
51365 
51366 #define LPUART_TDBR_DATA1_MASK                   (0xFF00U)
51367 #define LPUART_TDBR_DATA1_SHIFT                  (8U)
51368 /*! DATA1 - Data1 */
51369 #define LPUART_TDBR_DATA1(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_TDBR_DATA1_SHIFT)) & LPUART_TDBR_DATA1_MASK)
51370 
51371 #define LPUART_TDBR_DATA2_MASK                   (0xFF0000U)
51372 #define LPUART_TDBR_DATA2_SHIFT                  (16U)
51373 /*! DATA2 - Data2 */
51374 #define LPUART_TDBR_DATA2(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_TDBR_DATA2_SHIFT)) & LPUART_TDBR_DATA2_MASK)
51375 
51376 #define LPUART_TDBR_DATA3_MASK                   (0xFF000000U)
51377 #define LPUART_TDBR_DATA3_SHIFT                  (24U)
51378 /*! DATA3 - Data3 */
51379 #define LPUART_TDBR_DATA3(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_TDBR_DATA3_SHIFT)) & LPUART_TDBR_DATA3_MASK)
51380 /*! @} */
51381 
51382 /* The count of LPUART_TDBR */
51383 #define LPUART_TDBR_COUNT                        (256U)
51384 
51385 
51386 /*!
51387  * @}
51388  */ /* end of group LPUART_Register_Masks */
51389 
51390 
51391 /* LPUART - Peripheral instance base addresses */
51392 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
51393   /** Peripheral LPUART0 base address */
51394   #define LPUART0_BASE                             (0x50092000u)
51395   /** Peripheral LPUART0 base address */
51396   #define LPUART0_BASE_NS                          (0x40092000u)
51397   /** Peripheral LPUART0 base pointer */
51398   #define LPUART0                                  ((LPUART_Type *)LPUART0_BASE)
51399   /** Peripheral LPUART0 base pointer */
51400   #define LPUART0_NS                               ((LPUART_Type *)LPUART0_BASE_NS)
51401   /** Peripheral LPUART1 base address */
51402   #define LPUART1_BASE                             (0x50093000u)
51403   /** Peripheral LPUART1 base address */
51404   #define LPUART1_BASE_NS                          (0x40093000u)
51405   /** Peripheral LPUART1 base pointer */
51406   #define LPUART1                                  ((LPUART_Type *)LPUART1_BASE)
51407   /** Peripheral LPUART1 base pointer */
51408   #define LPUART1_NS                               ((LPUART_Type *)LPUART1_BASE_NS)
51409   /** Peripheral LPUART2 base address */
51410   #define LPUART2_BASE                             (0x50094000u)
51411   /** Peripheral LPUART2 base address */
51412   #define LPUART2_BASE_NS                          (0x40094000u)
51413   /** Peripheral LPUART2 base pointer */
51414   #define LPUART2                                  ((LPUART_Type *)LPUART2_BASE)
51415   /** Peripheral LPUART2 base pointer */
51416   #define LPUART2_NS                               ((LPUART_Type *)LPUART2_BASE_NS)
51417   /** Peripheral LPUART3 base address */
51418   #define LPUART3_BASE                             (0x50095000u)
51419   /** Peripheral LPUART3 base address */
51420   #define LPUART3_BASE_NS                          (0x40095000u)
51421   /** Peripheral LPUART3 base pointer */
51422   #define LPUART3                                  ((LPUART_Type *)LPUART3_BASE)
51423   /** Peripheral LPUART3 base pointer */
51424   #define LPUART3_NS                               ((LPUART_Type *)LPUART3_BASE_NS)
51425   /** Peripheral LPUART4 base address */
51426   #define LPUART4_BASE                             (0x500B4000u)
51427   /** Peripheral LPUART4 base address */
51428   #define LPUART4_BASE_NS                          (0x400B4000u)
51429   /** Peripheral LPUART4 base pointer */
51430   #define LPUART4                                  ((LPUART_Type *)LPUART4_BASE)
51431   /** Peripheral LPUART4 base pointer */
51432   #define LPUART4_NS                               ((LPUART_Type *)LPUART4_BASE_NS)
51433   /** Peripheral LPUART5 base address */
51434   #define LPUART5_BASE                             (0x500B5000u)
51435   /** Peripheral LPUART5 base address */
51436   #define LPUART5_BASE_NS                          (0x400B5000u)
51437   /** Peripheral LPUART5 base pointer */
51438   #define LPUART5                                  ((LPUART_Type *)LPUART5_BASE)
51439   /** Peripheral LPUART5 base pointer */
51440   #define LPUART5_NS                               ((LPUART_Type *)LPUART5_BASE_NS)
51441   /** Peripheral LPUART6 base address */
51442   #define LPUART6_BASE                             (0x500B6000u)
51443   /** Peripheral LPUART6 base address */
51444   #define LPUART6_BASE_NS                          (0x400B6000u)
51445   /** Peripheral LPUART6 base pointer */
51446   #define LPUART6                                  ((LPUART_Type *)LPUART6_BASE)
51447   /** Peripheral LPUART6 base pointer */
51448   #define LPUART6_NS                               ((LPUART_Type *)LPUART6_BASE_NS)
51449   /** Peripheral LPUART7 base address */
51450   #define LPUART7_BASE                             (0x500B7000u)
51451   /** Peripheral LPUART7 base address */
51452   #define LPUART7_BASE_NS                          (0x400B7000u)
51453   /** Peripheral LPUART7 base pointer */
51454   #define LPUART7                                  ((LPUART_Type *)LPUART7_BASE)
51455   /** Peripheral LPUART7 base pointer */
51456   #define LPUART7_NS                               ((LPUART_Type *)LPUART7_BASE_NS)
51457   /** Peripheral LPUART8 base address */
51458   #define LPUART8_BASE                             (0x500B8000u)
51459   /** Peripheral LPUART8 base address */
51460   #define LPUART8_BASE_NS                          (0x400B8000u)
51461   /** Peripheral LPUART8 base pointer */
51462   #define LPUART8                                  ((LPUART_Type *)LPUART8_BASE)
51463   /** Peripheral LPUART8 base pointer */
51464   #define LPUART8_NS                               ((LPUART_Type *)LPUART8_BASE_NS)
51465   /** Peripheral LPUART9 base address */
51466   #define LPUART9_BASE                             (0x500B9000u)
51467   /** Peripheral LPUART9 base address */
51468   #define LPUART9_BASE_NS                          (0x400B9000u)
51469   /** Peripheral LPUART9 base pointer */
51470   #define LPUART9                                  ((LPUART_Type *)LPUART9_BASE)
51471   /** Peripheral LPUART9 base pointer */
51472   #define LPUART9_NS                               ((LPUART_Type *)LPUART9_BASE_NS)
51473   /** Array initializer of LPUART peripheral base addresses */
51474   #define LPUART_BASE_ADDRS                        { LPUART0_BASE, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE, LPUART4_BASE, LPUART5_BASE, LPUART6_BASE, LPUART7_BASE, LPUART8_BASE, LPUART9_BASE }
51475   /** Array initializer of LPUART peripheral base pointers */
51476   #define LPUART_BASE_PTRS                         { LPUART0, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, LPUART9 }
51477   /** Array initializer of LPUART peripheral base addresses */
51478   #define LPUART_BASE_ADDRS_NS                     { LPUART0_BASE_NS, LPUART1_BASE_NS, LPUART2_BASE_NS, LPUART3_BASE_NS, LPUART4_BASE_NS, LPUART5_BASE_NS, LPUART6_BASE_NS, LPUART7_BASE_NS, LPUART8_BASE_NS, LPUART9_BASE_NS }
51479   /** Array initializer of LPUART peripheral base pointers */
51480   #define LPUART_BASE_PTRS_NS                      { LPUART0_NS, LPUART1_NS, LPUART2_NS, LPUART3_NS, LPUART4_NS, LPUART5_NS, LPUART6_NS, LPUART7_NS, LPUART8_NS, LPUART9_NS }
51481 #else
51482   /** Peripheral LPUART0 base address */
51483   #define LPUART0_BASE                             (0x40092000u)
51484   /** Peripheral LPUART0 base pointer */
51485   #define LPUART0                                  ((LPUART_Type *)LPUART0_BASE)
51486   /** Peripheral LPUART1 base address */
51487   #define LPUART1_BASE                             (0x40093000u)
51488   /** Peripheral LPUART1 base pointer */
51489   #define LPUART1                                  ((LPUART_Type *)LPUART1_BASE)
51490   /** Peripheral LPUART2 base address */
51491   #define LPUART2_BASE                             (0x40094000u)
51492   /** Peripheral LPUART2 base pointer */
51493   #define LPUART2                                  ((LPUART_Type *)LPUART2_BASE)
51494   /** Peripheral LPUART3 base address */
51495   #define LPUART3_BASE                             (0x40095000u)
51496   /** Peripheral LPUART3 base pointer */
51497   #define LPUART3                                  ((LPUART_Type *)LPUART3_BASE)
51498   /** Peripheral LPUART4 base address */
51499   #define LPUART4_BASE                             (0x400B4000u)
51500   /** Peripheral LPUART4 base pointer */
51501   #define LPUART4                                  ((LPUART_Type *)LPUART4_BASE)
51502   /** Peripheral LPUART5 base address */
51503   #define LPUART5_BASE                             (0x400B5000u)
51504   /** Peripheral LPUART5 base pointer */
51505   #define LPUART5                                  ((LPUART_Type *)LPUART5_BASE)
51506   /** Peripheral LPUART6 base address */
51507   #define LPUART6_BASE                             (0x400B6000u)
51508   /** Peripheral LPUART6 base pointer */
51509   #define LPUART6                                  ((LPUART_Type *)LPUART6_BASE)
51510   /** Peripheral LPUART7 base address */
51511   #define LPUART7_BASE                             (0x400B7000u)
51512   /** Peripheral LPUART7 base pointer */
51513   #define LPUART7                                  ((LPUART_Type *)LPUART7_BASE)
51514   /** Peripheral LPUART8 base address */
51515   #define LPUART8_BASE                             (0x400B8000u)
51516   /** Peripheral LPUART8 base pointer */
51517   #define LPUART8                                  ((LPUART_Type *)LPUART8_BASE)
51518   /** Peripheral LPUART9 base address */
51519   #define LPUART9_BASE                             (0x400B9000u)
51520   /** Peripheral LPUART9 base pointer */
51521   #define LPUART9                                  ((LPUART_Type *)LPUART9_BASE)
51522   /** Array initializer of LPUART peripheral base addresses */
51523   #define LPUART_BASE_ADDRS                        { LPUART0_BASE, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE, LPUART4_BASE, LPUART5_BASE, LPUART6_BASE, LPUART7_BASE, LPUART8_BASE, LPUART9_BASE }
51524   /** Array initializer of LPUART peripheral base pointers */
51525   #define LPUART_BASE_PTRS                         { LPUART0, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, LPUART9 }
51526 #endif
51527 /** Interrupt vectors for the LPUART peripheral type */
51528 #define LPUART_RX_TX_IRQS                        { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn, LP_FLEXCOMM8_IRQn, LP_FLEXCOMM9_IRQn }
51529 #define LPUART_ERR_IRQS                          { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn, LP_FLEXCOMM8_IRQn, LP_FLEXCOMM9_IRQn }
51530 
51531 /*!
51532  * @}
51533  */ /* end of group LPUART_Peripheral_Access_Layer */
51534 
51535 
51536 /* ----------------------------------------------------------------------------
51537    -- LP_FLEXCOMM Peripheral Access Layer
51538    ---------------------------------------------------------------------------- */
51539 
51540 /*!
51541  * @addtogroup LP_FLEXCOMM_Peripheral_Access_Layer LP_FLEXCOMM Peripheral Access Layer
51542  * @{
51543  */
51544 
51545 /** LP_FLEXCOMM - Register Layout Typedef */
51546 typedef struct {
51547        uint8_t RESERVED_0[4084];
51548   __I  uint32_t ISTAT;                             /**< Interrupt Status, offset: 0xFF4 */
51549   __IO uint32_t PSELID;                            /**< Peripheral Select and ID, offset: 0xFF8 */
51550 } LP_FLEXCOMM_Type;
51551 
51552 /* ----------------------------------------------------------------------------
51553    -- LP_FLEXCOMM Register Masks
51554    ---------------------------------------------------------------------------- */
51555 
51556 /*!
51557  * @addtogroup LP_FLEXCOMM_Register_Masks LP_FLEXCOMM Register Masks
51558  * @{
51559  */
51560 
51561 /*! @name ISTAT - Interrupt Status */
51562 /*! @{ */
51563 
51564 #define LP_FLEXCOMM_ISTAT_UARTTX_MASK            (0x1U)
51565 #define LP_FLEXCOMM_ISTAT_UARTTX_SHIFT           (0U)
51566 /*! UARTTX - UART TX Interrupt
51567  *  0b0..Clear
51568  *  0b1..Set
51569  */
51570 #define LP_FLEXCOMM_ISTAT_UARTTX(x)              (((uint32_t)(((uint32_t)(x)) << LP_FLEXCOMM_ISTAT_UARTTX_SHIFT)) & LP_FLEXCOMM_ISTAT_UARTTX_MASK)
51571 
51572 #define LP_FLEXCOMM_ISTAT_UARTRX_MASK            (0x2U)
51573 #define LP_FLEXCOMM_ISTAT_UARTRX_SHIFT           (1U)
51574 /*! UARTRX - UART RX Interrupt
51575  *  0b0..Clear
51576  *  0b1..Set
51577  */
51578 #define LP_FLEXCOMM_ISTAT_UARTRX(x)              (((uint32_t)(((uint32_t)(x)) << LP_FLEXCOMM_ISTAT_UARTRX_SHIFT)) & LP_FLEXCOMM_ISTAT_UARTRX_MASK)
51579 
51580 #define LP_FLEXCOMM_ISTAT_SPI_MASK               (0x4U)
51581 #define LP_FLEXCOMM_ISTAT_SPI_SHIFT              (2U)
51582 /*! SPI - SPI Interrupt
51583  *  0b0..Clear
51584  *  0b1..Set
51585  */
51586 #define LP_FLEXCOMM_ISTAT_SPI(x)                 (((uint32_t)(((uint32_t)(x)) << LP_FLEXCOMM_ISTAT_SPI_SHIFT)) & LP_FLEXCOMM_ISTAT_SPI_MASK)
51587 
51588 #define LP_FLEXCOMM_ISTAT_I2CM_MASK              (0x10U)
51589 #define LP_FLEXCOMM_ISTAT_I2CM_SHIFT             (4U)
51590 /*! I2CM - I2C Controller Interrupt
51591  *  0b0..Clear
51592  *  0b1..Set
51593  */
51594 #define LP_FLEXCOMM_ISTAT_I2CM(x)                (((uint32_t)(((uint32_t)(x)) << LP_FLEXCOMM_ISTAT_I2CM_SHIFT)) & LP_FLEXCOMM_ISTAT_I2CM_MASK)
51595 
51596 #define LP_FLEXCOMM_ISTAT_I2CS_MASK              (0x20U)
51597 #define LP_FLEXCOMM_ISTAT_I2CS_SHIFT             (5U)
51598 /*! I2CS - I2C Subordinate Interrupt
51599  *  0b0..Clear
51600  *  0b1..Set
51601  */
51602 #define LP_FLEXCOMM_ISTAT_I2CS(x)                (((uint32_t)(((uint32_t)(x)) << LP_FLEXCOMM_ISTAT_I2CS_SHIFT)) & LP_FLEXCOMM_ISTAT_I2CS_MASK)
51603 /*! @} */
51604 
51605 /*! @name PSELID - Peripheral Select and ID */
51606 /*! @{ */
51607 
51608 #define LP_FLEXCOMM_PSELID_PERSEL_MASK           (0x7U)
51609 #define LP_FLEXCOMM_PSELID_PERSEL_SHIFT          (0U)
51610 /*! PERSEL - Peripheral Select
51611  *  0b000..No peripheral selected
51612  *  0b001..UART
51613  *  0b011..I2C
51614  *  0b111..UART and I2C
51615  *  0b010..SPI
51616  */
51617 #define LP_FLEXCOMM_PSELID_PERSEL(x)             (((uint32_t)(((uint32_t)(x)) << LP_FLEXCOMM_PSELID_PERSEL_SHIFT)) & LP_FLEXCOMM_PSELID_PERSEL_MASK)
51618 
51619 #define LP_FLEXCOMM_PSELID_LOCK_MASK             (0x8U)
51620 #define LP_FLEXCOMM_PSELID_LOCK_SHIFT            (3U)
51621 /*! LOCK - Lock
51622  *  0b0..PERSEL is writable
51623  *  0b1..PERSEL is not writable
51624  */
51625 #define LP_FLEXCOMM_PSELID_LOCK(x)               (((uint32_t)(((uint32_t)(x)) << LP_FLEXCOMM_PSELID_LOCK_SHIFT)) & LP_FLEXCOMM_PSELID_LOCK_MASK)
51626 
51627 #define LP_FLEXCOMM_PSELID_UARTPRESENT_MASK      (0x10U)
51628 #define LP_FLEXCOMM_PSELID_UARTPRESENT_SHIFT     (4U)
51629 /*! UARTPRESENT - UART Present
51630  *  0b0..Not supported
51631  *  0b1..Supported
51632  */
51633 #define LP_FLEXCOMM_PSELID_UARTPRESENT(x)        (((uint32_t)(((uint32_t)(x)) << LP_FLEXCOMM_PSELID_UARTPRESENT_SHIFT)) & LP_FLEXCOMM_PSELID_UARTPRESENT_MASK)
51634 
51635 #define LP_FLEXCOMM_PSELID_SPIPRESENT_MASK       (0x20U)
51636 #define LP_FLEXCOMM_PSELID_SPIPRESENT_SHIFT      (5U)
51637 /*! SPIPRESENT - SPI Present
51638  *  0b0..Not supported
51639  *  0b1..Supported
51640  */
51641 #define LP_FLEXCOMM_PSELID_SPIPRESENT(x)         (((uint32_t)(((uint32_t)(x)) << LP_FLEXCOMM_PSELID_SPIPRESENT_SHIFT)) & LP_FLEXCOMM_PSELID_SPIPRESENT_MASK)
51642 
51643 #define LP_FLEXCOMM_PSELID_I2CPRESENT_MASK       (0x40U)
51644 #define LP_FLEXCOMM_PSELID_I2CPRESENT_SHIFT      (6U)
51645 /*! I2CPRESENT - I2C Present
51646  *  0b0..Not supported
51647  *  0b1..Supported
51648  */
51649 #define LP_FLEXCOMM_PSELID_I2CPRESENT(x)         (((uint32_t)(((uint32_t)(x)) << LP_FLEXCOMM_PSELID_I2CPRESENT_SHIFT)) & LP_FLEXCOMM_PSELID_I2CPRESENT_MASK)
51650 
51651 #define LP_FLEXCOMM_PSELID_ID_MASK               (0xFFFFF000U)
51652 #define LP_FLEXCOMM_PSELID_ID_SHIFT              (12U)
51653 /*! ID - LP_FLEXCOMM interface ID */
51654 #define LP_FLEXCOMM_PSELID_ID(x)                 (((uint32_t)(((uint32_t)(x)) << LP_FLEXCOMM_PSELID_ID_SHIFT)) & LP_FLEXCOMM_PSELID_ID_MASK)
51655 /*! @} */
51656 
51657 
51658 /*!
51659  * @}
51660  */ /* end of group LP_FLEXCOMM_Register_Masks */
51661 
51662 
51663 /* LP_FLEXCOMM - Peripheral instance base addresses */
51664 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
51665   /** Peripheral LP_FLEXCOMM0 base address */
51666   #define LP_FLEXCOMM0_BASE                        (0x50092000u)
51667   /** Peripheral LP_FLEXCOMM0 base address */
51668   #define LP_FLEXCOMM0_BASE_NS                     (0x40092000u)
51669   /** Peripheral LP_FLEXCOMM0 base pointer */
51670   #define LP_FLEXCOMM0                             ((LP_FLEXCOMM_Type *)LP_FLEXCOMM0_BASE)
51671   /** Peripheral LP_FLEXCOMM0 base pointer */
51672   #define LP_FLEXCOMM0_NS                          ((LP_FLEXCOMM_Type *)LP_FLEXCOMM0_BASE_NS)
51673   /** Peripheral LP_FLEXCOMM1 base address */
51674   #define LP_FLEXCOMM1_BASE                        (0x50093000u)
51675   /** Peripheral LP_FLEXCOMM1 base address */
51676   #define LP_FLEXCOMM1_BASE_NS                     (0x40093000u)
51677   /** Peripheral LP_FLEXCOMM1 base pointer */
51678   #define LP_FLEXCOMM1                             ((LP_FLEXCOMM_Type *)LP_FLEXCOMM1_BASE)
51679   /** Peripheral LP_FLEXCOMM1 base pointer */
51680   #define LP_FLEXCOMM1_NS                          ((LP_FLEXCOMM_Type *)LP_FLEXCOMM1_BASE_NS)
51681   /** Peripheral LP_FLEXCOMM2 base address */
51682   #define LP_FLEXCOMM2_BASE                        (0x50094000u)
51683   /** Peripheral LP_FLEXCOMM2 base address */
51684   #define LP_FLEXCOMM2_BASE_NS                     (0x40094000u)
51685   /** Peripheral LP_FLEXCOMM2 base pointer */
51686   #define LP_FLEXCOMM2                             ((LP_FLEXCOMM_Type *)LP_FLEXCOMM2_BASE)
51687   /** Peripheral LP_FLEXCOMM2 base pointer */
51688   #define LP_FLEXCOMM2_NS                          ((LP_FLEXCOMM_Type *)LP_FLEXCOMM2_BASE_NS)
51689   /** Peripheral LP_FLEXCOMM3 base address */
51690   #define LP_FLEXCOMM3_BASE                        (0x50095000u)
51691   /** Peripheral LP_FLEXCOMM3 base address */
51692   #define LP_FLEXCOMM3_BASE_NS                     (0x40095000u)
51693   /** Peripheral LP_FLEXCOMM3 base pointer */
51694   #define LP_FLEXCOMM3                             ((LP_FLEXCOMM_Type *)LP_FLEXCOMM3_BASE)
51695   /** Peripheral LP_FLEXCOMM3 base pointer */
51696   #define LP_FLEXCOMM3_NS                          ((LP_FLEXCOMM_Type *)LP_FLEXCOMM3_BASE_NS)
51697   /** Peripheral LP_FLEXCOMM4 base address */
51698   #define LP_FLEXCOMM4_BASE                        (0x500B4000u)
51699   /** Peripheral LP_FLEXCOMM4 base address */
51700   #define LP_FLEXCOMM4_BASE_NS                     (0x400B4000u)
51701   /** Peripheral LP_FLEXCOMM4 base pointer */
51702   #define LP_FLEXCOMM4                             ((LP_FLEXCOMM_Type *)LP_FLEXCOMM4_BASE)
51703   /** Peripheral LP_FLEXCOMM4 base pointer */
51704   #define LP_FLEXCOMM4_NS                          ((LP_FLEXCOMM_Type *)LP_FLEXCOMM4_BASE_NS)
51705   /** Peripheral LP_FLEXCOMM5 base address */
51706   #define LP_FLEXCOMM5_BASE                        (0x500B5000u)
51707   /** Peripheral LP_FLEXCOMM5 base address */
51708   #define LP_FLEXCOMM5_BASE_NS                     (0x400B5000u)
51709   /** Peripheral LP_FLEXCOMM5 base pointer */
51710   #define LP_FLEXCOMM5                             ((LP_FLEXCOMM_Type *)LP_FLEXCOMM5_BASE)
51711   /** Peripheral LP_FLEXCOMM5 base pointer */
51712   #define LP_FLEXCOMM5_NS                          ((LP_FLEXCOMM_Type *)LP_FLEXCOMM5_BASE_NS)
51713   /** Peripheral LP_FLEXCOMM6 base address */
51714   #define LP_FLEXCOMM6_BASE                        (0x500B6000u)
51715   /** Peripheral LP_FLEXCOMM6 base address */
51716   #define LP_FLEXCOMM6_BASE_NS                     (0x400B6000u)
51717   /** Peripheral LP_FLEXCOMM6 base pointer */
51718   #define LP_FLEXCOMM6                             ((LP_FLEXCOMM_Type *)LP_FLEXCOMM6_BASE)
51719   /** Peripheral LP_FLEXCOMM6 base pointer */
51720   #define LP_FLEXCOMM6_NS                          ((LP_FLEXCOMM_Type *)LP_FLEXCOMM6_BASE_NS)
51721   /** Peripheral LP_FLEXCOMM7 base address */
51722   #define LP_FLEXCOMM7_BASE                        (0x500B7000u)
51723   /** Peripheral LP_FLEXCOMM7 base address */
51724   #define LP_FLEXCOMM7_BASE_NS                     (0x400B7000u)
51725   /** Peripheral LP_FLEXCOMM7 base pointer */
51726   #define LP_FLEXCOMM7                             ((LP_FLEXCOMM_Type *)LP_FLEXCOMM7_BASE)
51727   /** Peripheral LP_FLEXCOMM7 base pointer */
51728   #define LP_FLEXCOMM7_NS                          ((LP_FLEXCOMM_Type *)LP_FLEXCOMM7_BASE_NS)
51729   /** Peripheral LP_FLEXCOMM8 base address */
51730   #define LP_FLEXCOMM8_BASE                        (0x500B8000u)
51731   /** Peripheral LP_FLEXCOMM8 base address */
51732   #define LP_FLEXCOMM8_BASE_NS                     (0x400B8000u)
51733   /** Peripheral LP_FLEXCOMM8 base pointer */
51734   #define LP_FLEXCOMM8                             ((LP_FLEXCOMM_Type *)LP_FLEXCOMM8_BASE)
51735   /** Peripheral LP_FLEXCOMM8 base pointer */
51736   #define LP_FLEXCOMM8_NS                          ((LP_FLEXCOMM_Type *)LP_FLEXCOMM8_BASE_NS)
51737   /** Peripheral LP_FLEXCOMM9 base address */
51738   #define LP_FLEXCOMM9_BASE                        (0x500B9000u)
51739   /** Peripheral LP_FLEXCOMM9 base address */
51740   #define LP_FLEXCOMM9_BASE_NS                     (0x400B9000u)
51741   /** Peripheral LP_FLEXCOMM9 base pointer */
51742   #define LP_FLEXCOMM9                             ((LP_FLEXCOMM_Type *)LP_FLEXCOMM9_BASE)
51743   /** Peripheral LP_FLEXCOMM9 base pointer */
51744   #define LP_FLEXCOMM9_NS                          ((LP_FLEXCOMM_Type *)LP_FLEXCOMM9_BASE_NS)
51745   /** Array initializer of LP_FLEXCOMM peripheral base addresses */
51746   #define LP_FLEXCOMM_BASE_ADDRS                   { LP_FLEXCOMM0_BASE, LP_FLEXCOMM1_BASE, LP_FLEXCOMM2_BASE, LP_FLEXCOMM3_BASE, LP_FLEXCOMM4_BASE, LP_FLEXCOMM5_BASE, LP_FLEXCOMM6_BASE, LP_FLEXCOMM7_BASE, LP_FLEXCOMM8_BASE, LP_FLEXCOMM9_BASE }
51747   /** Array initializer of LP_FLEXCOMM peripheral base pointers */
51748   #define LP_FLEXCOMM_BASE_PTRS                    { LP_FLEXCOMM0, LP_FLEXCOMM1, LP_FLEXCOMM2, LP_FLEXCOMM3, LP_FLEXCOMM4, LP_FLEXCOMM5, LP_FLEXCOMM6, LP_FLEXCOMM7, LP_FLEXCOMM8, LP_FLEXCOMM9 }
51749   /** Array initializer of LP_FLEXCOMM peripheral base addresses */
51750   #define LP_FLEXCOMM_BASE_ADDRS_NS                { LP_FLEXCOMM0_BASE_NS, LP_FLEXCOMM1_BASE_NS, LP_FLEXCOMM2_BASE_NS, LP_FLEXCOMM3_BASE_NS, LP_FLEXCOMM4_BASE_NS, LP_FLEXCOMM5_BASE_NS, LP_FLEXCOMM6_BASE_NS, LP_FLEXCOMM7_BASE_NS, LP_FLEXCOMM8_BASE_NS, LP_FLEXCOMM9_BASE_NS }
51751   /** Array initializer of LP_FLEXCOMM peripheral base pointers */
51752   #define LP_FLEXCOMM_BASE_PTRS_NS                 { LP_FLEXCOMM0_NS, LP_FLEXCOMM1_NS, LP_FLEXCOMM2_NS, LP_FLEXCOMM3_NS, LP_FLEXCOMM4_NS, LP_FLEXCOMM5_NS, LP_FLEXCOMM6_NS, LP_FLEXCOMM7_NS, LP_FLEXCOMM8_NS, LP_FLEXCOMM9_NS }
51753 #else
51754   /** Peripheral LP_FLEXCOMM0 base address */
51755   #define LP_FLEXCOMM0_BASE                        (0x40092000u)
51756   /** Peripheral LP_FLEXCOMM0 base pointer */
51757   #define LP_FLEXCOMM0                             ((LP_FLEXCOMM_Type *)LP_FLEXCOMM0_BASE)
51758   /** Peripheral LP_FLEXCOMM1 base address */
51759   #define LP_FLEXCOMM1_BASE                        (0x40093000u)
51760   /** Peripheral LP_FLEXCOMM1 base pointer */
51761   #define LP_FLEXCOMM1                             ((LP_FLEXCOMM_Type *)LP_FLEXCOMM1_BASE)
51762   /** Peripheral LP_FLEXCOMM2 base address */
51763   #define LP_FLEXCOMM2_BASE                        (0x40094000u)
51764   /** Peripheral LP_FLEXCOMM2 base pointer */
51765   #define LP_FLEXCOMM2                             ((LP_FLEXCOMM_Type *)LP_FLEXCOMM2_BASE)
51766   /** Peripheral LP_FLEXCOMM3 base address */
51767   #define LP_FLEXCOMM3_BASE                        (0x40095000u)
51768   /** Peripheral LP_FLEXCOMM3 base pointer */
51769   #define LP_FLEXCOMM3                             ((LP_FLEXCOMM_Type *)LP_FLEXCOMM3_BASE)
51770   /** Peripheral LP_FLEXCOMM4 base address */
51771   #define LP_FLEXCOMM4_BASE                        (0x400B4000u)
51772   /** Peripheral LP_FLEXCOMM4 base pointer */
51773   #define LP_FLEXCOMM4                             ((LP_FLEXCOMM_Type *)LP_FLEXCOMM4_BASE)
51774   /** Peripheral LP_FLEXCOMM5 base address */
51775   #define LP_FLEXCOMM5_BASE                        (0x400B5000u)
51776   /** Peripheral LP_FLEXCOMM5 base pointer */
51777   #define LP_FLEXCOMM5                             ((LP_FLEXCOMM_Type *)LP_FLEXCOMM5_BASE)
51778   /** Peripheral LP_FLEXCOMM6 base address */
51779   #define LP_FLEXCOMM6_BASE                        (0x400B6000u)
51780   /** Peripheral LP_FLEXCOMM6 base pointer */
51781   #define LP_FLEXCOMM6                             ((LP_FLEXCOMM_Type *)LP_FLEXCOMM6_BASE)
51782   /** Peripheral LP_FLEXCOMM7 base address */
51783   #define LP_FLEXCOMM7_BASE                        (0x400B7000u)
51784   /** Peripheral LP_FLEXCOMM7 base pointer */
51785   #define LP_FLEXCOMM7                             ((LP_FLEXCOMM_Type *)LP_FLEXCOMM7_BASE)
51786   /** Peripheral LP_FLEXCOMM8 base address */
51787   #define LP_FLEXCOMM8_BASE                        (0x400B8000u)
51788   /** Peripheral LP_FLEXCOMM8 base pointer */
51789   #define LP_FLEXCOMM8                             ((LP_FLEXCOMM_Type *)LP_FLEXCOMM8_BASE)
51790   /** Peripheral LP_FLEXCOMM9 base address */
51791   #define LP_FLEXCOMM9_BASE                        (0x400B9000u)
51792   /** Peripheral LP_FLEXCOMM9 base pointer */
51793   #define LP_FLEXCOMM9                             ((LP_FLEXCOMM_Type *)LP_FLEXCOMM9_BASE)
51794   /** Array initializer of LP_FLEXCOMM peripheral base addresses */
51795   #define LP_FLEXCOMM_BASE_ADDRS                   { LP_FLEXCOMM0_BASE, LP_FLEXCOMM1_BASE, LP_FLEXCOMM2_BASE, LP_FLEXCOMM3_BASE, LP_FLEXCOMM4_BASE, LP_FLEXCOMM5_BASE, LP_FLEXCOMM6_BASE, LP_FLEXCOMM7_BASE, LP_FLEXCOMM8_BASE, LP_FLEXCOMM9_BASE }
51796   /** Array initializer of LP_FLEXCOMM peripheral base pointers */
51797   #define LP_FLEXCOMM_BASE_PTRS                    { LP_FLEXCOMM0, LP_FLEXCOMM1, LP_FLEXCOMM2, LP_FLEXCOMM3, LP_FLEXCOMM4, LP_FLEXCOMM5, LP_FLEXCOMM6, LP_FLEXCOMM7, LP_FLEXCOMM8, LP_FLEXCOMM9 }
51798 #endif
51799 /** Interrupt vectors for the LP_FLEXCOMM peripheral type */
51800 #define LP_FLEXCOMM_IRQS                         { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn, LP_FLEXCOMM8_IRQn, LP_FLEXCOMM9_IRQn }
51801 
51802 /*!
51803  * @}
51804  */ /* end of group LP_FLEXCOMM_Peripheral_Access_Layer */
51805 
51806 
51807 /* ----------------------------------------------------------------------------
51808    -- MAILBOX Peripheral Access Layer
51809    ---------------------------------------------------------------------------- */
51810 
51811 /*!
51812  * @addtogroup MAILBOX_Peripheral_Access_Layer MAILBOX Peripheral Access Layer
51813  * @{
51814  */
51815 
51816 /** MAILBOX - Register Layout Typedef */
51817 typedef struct {
51818   struct {                                         /* offset: 0x0, array step: 0x10 */
51819     __IO uint32_t IRQ;                               /**< Cortex-M33 (CPU0) Interrupt..CoolFlux (CPU1) Interrupt, array offset: 0x0, array step: 0x10 */
51820     __O  uint32_t IRQSET;                            /**< Cortex-M33 (CPU0) Interrupt Set..CoolFlux (CPU1) Interrupt Set, array offset: 0x4, array step: 0x10 */
51821     __O  uint32_t IRQCLR;                            /**< Cortex-M33 (CPU0) Interrupt Clear..CoolFlux (CPU1) Interrupt Clear, array offset: 0x8, array step: 0x10 */
51822          uint8_t RESERVED_0[4];
51823   } MBOXIRQ[2];
51824        uint8_t RESERVED_0[216];
51825   __IO uint32_t MUTEX;                             /**< Mutual Exclusion, offset: 0xF8 */
51826 } MAILBOX_Type;
51827 
51828 /* ----------------------------------------------------------------------------
51829    -- MAILBOX Register Masks
51830    ---------------------------------------------------------------------------- */
51831 
51832 /*!
51833  * @addtogroup MAILBOX_Register_Masks MAILBOX Register Masks
51834  * @{
51835  */
51836 
51837 /*! @name MBOXIRQ_IRQ - Cortex-M33 (CPU0) Interrupt..CoolFlux (CPU1) Interrupt */
51838 /*! @{ */
51839 
51840 #define MAILBOX_MBOXIRQ_IRQ_INTREQ_MASK          (0xFFFFFFFFU)
51841 #define MAILBOX_MBOXIRQ_IRQ_INTREQ_SHIFT         (0U)
51842 /*! INTREQ - Interrupt Request */
51843 #define MAILBOX_MBOXIRQ_IRQ_INTREQ(x)            (((uint32_t)(((uint32_t)(x)) << MAILBOX_MBOXIRQ_IRQ_INTREQ_SHIFT)) & MAILBOX_MBOXIRQ_IRQ_INTREQ_MASK)
51844 /*! @} */
51845 
51846 /* The count of MAILBOX_MBOXIRQ_IRQ */
51847 #define MAILBOX_MBOXIRQ_IRQ_COUNT                (2U)
51848 
51849 /*! @name MBOXIRQ_IRQSET - Cortex-M33 (CPU0) Interrupt Set..CoolFlux (CPU1) Interrupt Set */
51850 /*! @{ */
51851 
51852 #define MAILBOX_MBOXIRQ_IRQSET_INTREQSET_MASK    (0xFFFFFFFFU)
51853 #define MAILBOX_MBOXIRQ_IRQSET_INTREQSET_SHIFT   (0U)
51854 /*! INTREQSET - Interrupt Request Set 1 */
51855 #define MAILBOX_MBOXIRQ_IRQSET_INTREQSET(x)      (((uint32_t)(((uint32_t)(x)) << MAILBOX_MBOXIRQ_IRQSET_INTREQSET_SHIFT)) & MAILBOX_MBOXIRQ_IRQSET_INTREQSET_MASK)
51856 /*! @} */
51857 
51858 /* The count of MAILBOX_MBOXIRQ_IRQSET */
51859 #define MAILBOX_MBOXIRQ_IRQSET_COUNT             (2U)
51860 
51861 /*! @name MBOXIRQ_IRQCLR - Cortex-M33 (CPU0) Interrupt Clear..CoolFlux (CPU1) Interrupt Clear */
51862 /*! @{ */
51863 
51864 #define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_MASK    (0xFFFFFFFFU)
51865 #define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_SHIFT   (0U)
51866 /*! INTREQCLR - Interrupt Request Clear 1 */
51867 #define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR(x)      (((uint32_t)(((uint32_t)(x)) << MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_SHIFT)) & MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_MASK)
51868 /*! @} */
51869 
51870 /* The count of MAILBOX_MBOXIRQ_IRQCLR */
51871 #define MAILBOX_MBOXIRQ_IRQCLR_COUNT             (2U)
51872 
51873 /*! @name MUTEX - Mutual Exclusion */
51874 /*! @{ */
51875 
51876 #define MAILBOX_MUTEX_EX_MASK                    (0x1U)
51877 #define MAILBOX_MUTEX_EX_SHIFT                   (0U)
51878 /*! EX - Mutual Exclusion Request
51879  *  0b0..Resource unavailable
51880  *  0b1..Resource available
51881  */
51882 #define MAILBOX_MUTEX_EX(x)                      (((uint32_t)(((uint32_t)(x)) << MAILBOX_MUTEX_EX_SHIFT)) & MAILBOX_MUTEX_EX_MASK)
51883 /*! @} */
51884 
51885 
51886 /*!
51887  * @}
51888  */ /* end of group MAILBOX_Register_Masks */
51889 
51890 
51891 /* MAILBOX - Peripheral instance base addresses */
51892 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
51893   /** Peripheral MAILBOX base address */
51894   #define MAILBOX_BASE                             (0x500B2000u)
51895   /** Peripheral MAILBOX base address */
51896   #define MAILBOX_BASE_NS                          (0x400B2000u)
51897   /** Peripheral MAILBOX base pointer */
51898   #define MAILBOX                                  ((MAILBOX_Type *)MAILBOX_BASE)
51899   /** Peripheral MAILBOX base pointer */
51900   #define MAILBOX_NS                               ((MAILBOX_Type *)MAILBOX_BASE_NS)
51901   /** Array initializer of MAILBOX peripheral base addresses */
51902   #define MAILBOX_BASE_ADDRS                       { MAILBOX_BASE }
51903   /** Array initializer of MAILBOX peripheral base pointers */
51904   #define MAILBOX_BASE_PTRS                        { MAILBOX }
51905   /** Array initializer of MAILBOX peripheral base addresses */
51906   #define MAILBOX_BASE_ADDRS_NS                    { MAILBOX_BASE_NS }
51907   /** Array initializer of MAILBOX peripheral base pointers */
51908   #define MAILBOX_BASE_PTRS_NS                     { MAILBOX_NS }
51909 #else
51910   /** Peripheral MAILBOX base address */
51911   #define MAILBOX_BASE                             (0x400B2000u)
51912   /** Peripheral MAILBOX base pointer */
51913   #define MAILBOX                                  ((MAILBOX_Type *)MAILBOX_BASE)
51914   /** Array initializer of MAILBOX peripheral base addresses */
51915   #define MAILBOX_BASE_ADDRS                       { MAILBOX_BASE }
51916   /** Array initializer of MAILBOX peripheral base pointers */
51917   #define MAILBOX_BASE_PTRS                        { MAILBOX }
51918 #endif
51919 
51920 /*!
51921  * @}
51922  */ /* end of group MAILBOX_Peripheral_Access_Layer */
51923 
51924 
51925 /* ----------------------------------------------------------------------------
51926    -- MRT Peripheral Access Layer
51927    ---------------------------------------------------------------------------- */
51928 
51929 /*!
51930  * @addtogroup MRT_Peripheral_Access_Layer MRT Peripheral Access Layer
51931  * @{
51932  */
51933 
51934 /** MRT - Register Layout Typedef */
51935 typedef struct {
51936   struct {                                         /* offset: 0x0, array step: 0x10 */
51937     __IO uint32_t INTVAL;                            /**< Time Interval Value, array offset: 0x0, array step: 0x10 */
51938     __I  uint32_t TIMER;                             /**< Timer, array offset: 0x4, array step: 0x10 */
51939     __IO uint32_t CTRL;                              /**< Control, array offset: 0x8, array step: 0x10 */
51940     __IO uint32_t STAT;                              /**< Status, array offset: 0xC, array step: 0x10 */
51941   } CHANNEL[4];
51942        uint8_t RESERVED_0[176];
51943   __IO uint32_t MODCFG;                            /**< Module Configuration, offset: 0xF0 */
51944   __I  uint32_t IDLE_CH;                           /**< Idle Channel, offset: 0xF4 */
51945   __IO uint32_t IRQ_FLAG;                          /**< Global Interrupt Flag, offset: 0xF8 */
51946 } MRT_Type;
51947 
51948 /* ----------------------------------------------------------------------------
51949    -- MRT Register Masks
51950    ---------------------------------------------------------------------------- */
51951 
51952 /*!
51953  * @addtogroup MRT_Register_Masks MRT Register Masks
51954  * @{
51955  */
51956 
51957 /*! @name CHANNEL_INTVAL - Time Interval Value */
51958 /*! @{ */
51959 
51960 #define MRT_CHANNEL_INTVAL_IVALUE_MASK           (0xFFFFFFU)
51961 #define MRT_CHANNEL_INTVAL_IVALUE_SHIFT          (0U)
51962 /*! IVALUE - Time Interval Load Value. */
51963 #define MRT_CHANNEL_INTVAL_IVALUE(x)             (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_IVALUE_SHIFT)) & MRT_CHANNEL_INTVAL_IVALUE_MASK)
51964 
51965 #define MRT_CHANNEL_INTVAL_LOAD_MASK             (0x80000000U)
51966 #define MRT_CHANNEL_INTVAL_LOAD_SHIFT            (31U)
51967 /*! LOAD - Force Load Enable
51968  *  0b0..No force load
51969  *  0b1..Force load
51970  */
51971 #define MRT_CHANNEL_INTVAL_LOAD(x)               (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_LOAD_SHIFT)) & MRT_CHANNEL_INTVAL_LOAD_MASK)
51972 /*! @} */
51973 
51974 /* The count of MRT_CHANNEL_INTVAL */
51975 #define MRT_CHANNEL_INTVAL_COUNT                 (4U)
51976 
51977 /*! @name CHANNEL_TIMER - Timer */
51978 /*! @{ */
51979 
51980 #define MRT_CHANNEL_TIMER_VALUE_MASK             (0xFFFFFFU)
51981 #define MRT_CHANNEL_TIMER_VALUE_SHIFT            (0U)
51982 /*! VALUE - Current Timer Value */
51983 #define MRT_CHANNEL_TIMER_VALUE(x)               (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_TIMER_VALUE_SHIFT)) & MRT_CHANNEL_TIMER_VALUE_MASK)
51984 /*! @} */
51985 
51986 /* The count of MRT_CHANNEL_TIMER */
51987 #define MRT_CHANNEL_TIMER_COUNT                  (4U)
51988 
51989 /*! @name CHANNEL_CTRL - Control */
51990 /*! @{ */
51991 
51992 #define MRT_CHANNEL_CTRL_INTEN_MASK              (0x1U)
51993 #define MRT_CHANNEL_CTRL_INTEN_SHIFT             (0U)
51994 /*! INTEN - Interrupt request
51995  *  0b0..Disabled
51996  *  0b1..Enabled
51997  */
51998 #define MRT_CHANNEL_CTRL_INTEN(x)                (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_INTEN_SHIFT)) & MRT_CHANNEL_CTRL_INTEN_MASK)
51999 
52000 #define MRT_CHANNEL_CTRL_MODE_MASK               (0x6U)
52001 #define MRT_CHANNEL_CTRL_MODE_SHIFT              (1U)
52002 /*! MODE - MRT Operating mode
52003  *  0b00..Repeat Interrupt mode
52004  *  0b01..One-Shot Interrupt mode
52005  *  0b10..One-Shot Stall mode
52006  *  0b11..Reserved
52007  */
52008 #define MRT_CHANNEL_CTRL_MODE(x)                 (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_MODE_SHIFT)) & MRT_CHANNEL_CTRL_MODE_MASK)
52009 /*! @} */
52010 
52011 /* The count of MRT_CHANNEL_CTRL */
52012 #define MRT_CHANNEL_CTRL_COUNT                   (4U)
52013 
52014 /*! @name CHANNEL_STAT - Status */
52015 /*! @{ */
52016 
52017 #define MRT_CHANNEL_STAT_INTFLAG_MASK            (0x1U)
52018 #define MRT_CHANNEL_STAT_INTFLAG_SHIFT           (0U)
52019 /*! INTFLAG - Interrupt Flag
52020  *  0b0..No pending interrupt.
52021  *  0b1..Pending interrupt.
52022  */
52023 #define MRT_CHANNEL_STAT_INTFLAG(x)              (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INTFLAG_SHIFT)) & MRT_CHANNEL_STAT_INTFLAG_MASK)
52024 
52025 #define MRT_CHANNEL_STAT_RUN_MASK                (0x2U)
52026 #define MRT_CHANNEL_STAT_RUN_SHIFT               (1U)
52027 /*! RUN - Timer n State
52028  *  0b0..Idle state.
52029  *  0b1..Running.
52030  */
52031 #define MRT_CHANNEL_STAT_RUN(x)                  (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_RUN_SHIFT)) & MRT_CHANNEL_STAT_RUN_MASK)
52032 
52033 #define MRT_CHANNEL_STAT_INUSE_MASK              (0x4U)
52034 #define MRT_CHANNEL_STAT_INUSE_SHIFT             (2U)
52035 /*! INUSE - Channel-In-Use flag
52036  *  0b0..This timer channel is not in use.
52037  *  0b1..This timer channel is in use.
52038  */
52039 #define MRT_CHANNEL_STAT_INUSE(x)                (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INUSE_SHIFT)) & MRT_CHANNEL_STAT_INUSE_MASK)
52040 /*! @} */
52041 
52042 /* The count of MRT_CHANNEL_STAT */
52043 #define MRT_CHANNEL_STAT_COUNT                   (4U)
52044 
52045 /*! @name MODCFG - Module Configuration */
52046 /*! @{ */
52047 
52048 #define MRT_MODCFG_NOC_MASK                      (0xFU)
52049 #define MRT_MODCFG_NOC_SHIFT                     (0U)
52050 /*! NOC - Number of Channels */
52051 #define MRT_MODCFG_NOC(x)                        (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOC_SHIFT)) & MRT_MODCFG_NOC_MASK)
52052 
52053 #define MRT_MODCFG_NOB_MASK                      (0x1F0U)
52054 #define MRT_MODCFG_NOB_SHIFT                     (4U)
52055 /*! NOB - Number of Bits */
52056 #define MRT_MODCFG_NOB(x)                        (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOB_SHIFT)) & MRT_MODCFG_NOB_MASK)
52057 
52058 #define MRT_MODCFG_MULTITASK_MASK                (0x80000000U)
52059 #define MRT_MODCFG_MULTITASK_SHIFT               (31U)
52060 /*! MULTITASK - MULTITASK
52061  *  0b0..Hardware status mode.
52062  *  0b1..Multitask mode
52063  */
52064 #define MRT_MODCFG_MULTITASK(x)                  (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_MULTITASK_SHIFT)) & MRT_MODCFG_MULTITASK_MASK)
52065 /*! @} */
52066 
52067 /*! @name IDLE_CH - Idle Channel */
52068 /*! @{ */
52069 
52070 #define MRT_IDLE_CH_CHAN_MASK                    (0xF0U)
52071 #define MRT_IDLE_CH_CHAN_SHIFT                   (4U)
52072 /*! CHAN - Idle Channel */
52073 #define MRT_IDLE_CH_CHAN(x)                      (((uint32_t)(((uint32_t)(x)) << MRT_IDLE_CH_CHAN_SHIFT)) & MRT_IDLE_CH_CHAN_MASK)
52074 /*! @} */
52075 
52076 /*! @name IRQ_FLAG - Global Interrupt Flag */
52077 /*! @{ */
52078 
52079 #define MRT_IRQ_FLAG_GFLAG0_MASK                 (0x1U)
52080 #define MRT_IRQ_FLAG_GFLAG0_SHIFT                (0U)
52081 /*! GFLAG0 - Interrupt Flag
52082  *  0b0..No pending interrupt.
52083  *  0b1..Pending interrupt
52084  */
52085 #define MRT_IRQ_FLAG_GFLAG0(x)                   (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG0_SHIFT)) & MRT_IRQ_FLAG_GFLAG0_MASK)
52086 
52087 #define MRT_IRQ_FLAG_GFLAG1_MASK                 (0x2U)
52088 #define MRT_IRQ_FLAG_GFLAG1_SHIFT                (1U)
52089 /*! GFLAG1 - Interrupt Flag */
52090 #define MRT_IRQ_FLAG_GFLAG1(x)                   (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG1_SHIFT)) & MRT_IRQ_FLAG_GFLAG1_MASK)
52091 
52092 #define MRT_IRQ_FLAG_GFLAG2_MASK                 (0x4U)
52093 #define MRT_IRQ_FLAG_GFLAG2_SHIFT                (2U)
52094 /*! GFLAG2 - Interrupt Flag */
52095 #define MRT_IRQ_FLAG_GFLAG2(x)                   (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG2_SHIFT)) & MRT_IRQ_FLAG_GFLAG2_MASK)
52096 
52097 #define MRT_IRQ_FLAG_GFLAG3_MASK                 (0x8U)
52098 #define MRT_IRQ_FLAG_GFLAG3_SHIFT                (3U)
52099 /*! GFLAG3 - Interrupt Flag */
52100 #define MRT_IRQ_FLAG_GFLAG3(x)                   (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG3_SHIFT)) & MRT_IRQ_FLAG_GFLAG3_MASK)
52101 /*! @} */
52102 
52103 
52104 /*!
52105  * @}
52106  */ /* end of group MRT_Register_Masks */
52107 
52108 
52109 /* MRT - Peripheral instance base addresses */
52110 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
52111   /** Peripheral MRT0 base address */
52112   #define MRT0_BASE                                (0x50013000u)
52113   /** Peripheral MRT0 base address */
52114   #define MRT0_BASE_NS                             (0x40013000u)
52115   /** Peripheral MRT0 base pointer */
52116   #define MRT0                                     ((MRT_Type *)MRT0_BASE)
52117   /** Peripheral MRT0 base pointer */
52118   #define MRT0_NS                                  ((MRT_Type *)MRT0_BASE_NS)
52119   /** Array initializer of MRT peripheral base addresses */
52120   #define MRT_BASE_ADDRS                           { MRT0_BASE }
52121   /** Array initializer of MRT peripheral base pointers */
52122   #define MRT_BASE_PTRS                            { MRT0 }
52123   /** Array initializer of MRT peripheral base addresses */
52124   #define MRT_BASE_ADDRS_NS                        { MRT0_BASE_NS }
52125   /** Array initializer of MRT peripheral base pointers */
52126   #define MRT_BASE_PTRS_NS                         { MRT0_NS }
52127 #else
52128   /** Peripheral MRT0 base address */
52129   #define MRT0_BASE                                (0x40013000u)
52130   /** Peripheral MRT0 base pointer */
52131   #define MRT0                                     ((MRT_Type *)MRT0_BASE)
52132   /** Array initializer of MRT peripheral base addresses */
52133   #define MRT_BASE_ADDRS                           { MRT0_BASE }
52134   /** Array initializer of MRT peripheral base pointers */
52135   #define MRT_BASE_PTRS                            { MRT0 }
52136 #endif
52137 /** Interrupt vectors for the MRT peripheral type */
52138 #define MRT_IRQS                                 { MRT0_IRQn }
52139 
52140 /*!
52141  * @}
52142  */ /* end of group MRT_Peripheral_Access_Layer */
52143 
52144 
52145 /* ----------------------------------------------------------------------------
52146    -- NPX Peripheral Access Layer
52147    ---------------------------------------------------------------------------- */
52148 
52149 /*!
52150  * @addtogroup NPX_Peripheral_Access_Layer NPX Peripheral Access Layer
52151  * @{
52152  */
52153 
52154 /** NPX - Register Layout Typedef */
52155 typedef struct {
52156   __IO uint32_t NPXCR;                             /**< NPX Control Register, offset: 0x0 */
52157        uint8_t RESERVED_0[4];
52158   __I  uint32_t NPXSR;                             /**< NPX Status Register, offset: 0x8 */
52159        uint8_t RESERVED_1[4];
52160   __O  uint32_t CACMSK;                            /**< Flash Cache Obfuscation Mask, offset: 0x10 */
52161        uint8_t RESERVED_2[12];
52162   __IO uint32_t REMAP;                             /**< Data Remap, offset: 0x20 */
52163        uint8_t RESERVED_3[28];
52164   struct {                                         /* offset: 0x40, array step: 0x10 */
52165     __IO uint32_t VMAPCTX_WD[2];                     /**< Bitmap of Valid Control for Memory Context 0..Bitmap of Valid Control for Memory Context 3, array offset: 0x40, array step: index*0x10, index2*0x4 */
52166     __O  uint32_t BIVCTX_WD[2];                      /**< Block Initial Vector for Memory Context 0..Block Initial Vector for Memory Context 3, array offset: 0x48, array step: index*0x10, index2*0x4 */
52167   } CTX_VALID_IV_ARRAY[4];
52168 } NPX_Type;
52169 
52170 /* ----------------------------------------------------------------------------
52171    -- NPX Register Masks
52172    ---------------------------------------------------------------------------- */
52173 
52174 /*!
52175  * @addtogroup NPX_Register_Masks NPX Register Masks
52176  * @{
52177  */
52178 
52179 /*! @name NPXCR - NPX Control Register */
52180 /*! @{ */
52181 
52182 #define NPX_NPXCR_GEE_MASK                       (0x1U)
52183 #define NPX_NPXCR_GEE_SHIFT                      (0U)
52184 /*! GEE - Global Encryption Enable
52185  *  0b1..Global encryption enabled. NPX on-the-fly encryption is enabled if the flash access hits in a valid
52186  *       memory context. Subsequent reads return 1.
52187  *  0b0..Global encryption disabled. NPX on-the-fly encryption is disabled. Subsequent reads return 0.
52188  */
52189 #define NPX_NPXCR_GEE(x)                         (((uint32_t)(((uint32_t)(x)) << NPX_NPXCR_GEE_SHIFT)) & NPX_NPXCR_GEE_MASK)
52190 
52191 #define NPX_NPXCR_GDE_MASK                       (0x4U)
52192 #define NPX_NPXCR_GDE_SHIFT                      (2U)
52193 /*! GDE - Global Decryption Enable
52194  *  0b1..Global decryption enabled. NPX on-the-fly decryption is globally enabled. Subsequent reads return 1.
52195  *  0b0..Global decryption disabled. NPX on-the-fly decryption is globally disabled. Subsequent reads return 0.
52196  */
52197 #define NPX_NPXCR_GDE(x)                         (((uint32_t)(((uint32_t)(x)) << NPX_NPXCR_GDE_SHIFT)) & NPX_NPXCR_GDE_MASK)
52198 
52199 #define NPX_NPXCR_GLK_MASK                       (0x10U)
52200 #define NPX_NPXCR_GLK_SHIFT                      (4U)
52201 /*! GLK - Global Lock Enable
52202  *  0b1..Lock enabled: cannot write to VMAPCTXn, NPXCR, or CACMSK. Subsequent reads return 1.
52203  *  0b0..Lock disabled. Subsequent reads return 0.
52204  */
52205 #define NPX_NPXCR_GLK(x)                         (((uint32_t)(((uint32_t)(x)) << NPX_NPXCR_GLK_SHIFT)) & NPX_NPXCR_GLK_MASK)
52206 
52207 #define NPX_NPXCR_MLK_MASK                       (0x40U)
52208 #define NPX_NPXCR_MLK_SHIFT                      (6U)
52209 /*! MLK - Mask Lock Enable
52210  *  0b1..Lock enabled: cannot write to mask. Subsequent reads return 1.
52211  *  0b0..Lock disabled. Subsequent reads return 0.
52212  */
52213 #define NPX_NPXCR_MLK(x)                         (((uint32_t)(((uint32_t)(x)) << NPX_NPXCR_MLK_SHIFT)) & NPX_NPXCR_MLK_MASK)
52214 
52215 #define NPX_NPXCR_CTX0LK_MASK                    (0x100U)
52216 #define NPX_NPXCR_CTX0LK_SHIFT                   (8U)
52217 /*! CTX0LK - Lock Enable for Context 0
52218  *  0b1..Lock enabled: cannot write to VMAPCTX0 (becomes read-only)
52219  *  0b0..Lock disabled: VMAPCTX0 remains read-write
52220  */
52221 #define NPX_NPXCR_CTX0LK(x)                      (((uint32_t)(((uint32_t)(x)) << NPX_NPXCR_CTX0LK_SHIFT)) & NPX_NPXCR_CTX0LK_MASK)
52222 
52223 #define NPX_NPXCR_CTX1LK_MASK                    (0x400U)
52224 #define NPX_NPXCR_CTX1LK_SHIFT                   (10U)
52225 /*! CTX1LK - Lock Enable for Context 1
52226  *  0b1..Lock enabled: cannot write to VMAPCTX1 (becomes read-only)
52227  *  0b0..Lock disabled: VMAPCTX1 remains read-write
52228  */
52229 #define NPX_NPXCR_CTX1LK(x)                      (((uint32_t)(((uint32_t)(x)) << NPX_NPXCR_CTX1LK_SHIFT)) & NPX_NPXCR_CTX1LK_MASK)
52230 
52231 #define NPX_NPXCR_CTX2LK_MASK                    (0x1000U)
52232 #define NPX_NPXCR_CTX2LK_SHIFT                   (12U)
52233 /*! CTX2LK - Lock Enable for Context 2
52234  *  0b1..Lock enabled: cannot write to VMAPCTX2 (becomes read-only)
52235  *  0b0..Lock disabled: VMAPCTX2 remains read-write
52236  */
52237 #define NPX_NPXCR_CTX2LK(x)                      (((uint32_t)(((uint32_t)(x)) << NPX_NPXCR_CTX2LK_SHIFT)) & NPX_NPXCR_CTX2LK_MASK)
52238 
52239 #define NPX_NPXCR_CTX3LK_MASK                    (0x4000U)
52240 #define NPX_NPXCR_CTX3LK_SHIFT                   (14U)
52241 /*! CTX3LK - Lock Enable for Context 3
52242  *  0b1..Lock enabled: cannot write to VMAPCTX3 (becomes read-only)
52243  *  0b0..Lock disabled: VMAPCTX3 remains read-write
52244  */
52245 #define NPX_NPXCR_CTX3LK(x)                      (((uint32_t)(((uint32_t)(x)) << NPX_NPXCR_CTX3LK_SHIFT)) & NPX_NPXCR_CTX3LK_MASK)
52246 /*! @} */
52247 
52248 /*! @name NPXSR - NPX Status Register */
52249 /*! @{ */
52250 
52251 #define NPX_NPXSR_NUMCTX_MASK                    (0xFU)
52252 #define NPX_NPXSR_NUMCTX_SHIFT                   (0U)
52253 /*! NUMCTX - Number of implemented memory contexts
52254  *  0b0000..No (zero) implemented memory contexts
52255  *  0b0001..1 implemented memory contexts
52256  *  0b0010..2 implemented memory contexts
52257  *  0b0011..3 implemented memory contexts
52258  *  0b0100..4 implemented memory contexts
52259  */
52260 #define NPX_NPXSR_NUMCTX(x)                      (((uint32_t)(((uint32_t)(x)) << NPX_NPXSR_NUMCTX_SHIFT)) & NPX_NPXSR_NUMCTX_MASK)
52261 
52262 #define NPX_NPXSR_V0_MASK                        (0x100U)
52263 #define NPX_NPXSR_V0_SHIFT                       (8U)
52264 /*! V0 - Key n Valid
52265  *  0b0..Not valid
52266  *  0b1..Valid
52267  */
52268 #define NPX_NPXSR_V0(x)                          (((uint32_t)(((uint32_t)(x)) << NPX_NPXSR_V0_SHIFT)) & NPX_NPXSR_V0_MASK)
52269 
52270 #define NPX_NPXSR_V1_MASK                        (0x200U)
52271 #define NPX_NPXSR_V1_SHIFT                       (9U)
52272 /*! V1 - Key n Valid
52273  *  0b0..Not valid
52274  *  0b1..Valid
52275  */
52276 #define NPX_NPXSR_V1(x)                          (((uint32_t)(((uint32_t)(x)) << NPX_NPXSR_V1_SHIFT)) & NPX_NPXSR_V1_MASK)
52277 
52278 #define NPX_NPXSR_V2_MASK                        (0x400U)
52279 #define NPX_NPXSR_V2_SHIFT                       (10U)
52280 /*! V2 - Key n Valid
52281  *  0b0..Not valid
52282  *  0b1..Valid
52283  */
52284 #define NPX_NPXSR_V2(x)                          (((uint32_t)(((uint32_t)(x)) << NPX_NPXSR_V2_SHIFT)) & NPX_NPXSR_V2_MASK)
52285 
52286 #define NPX_NPXSR_V3_MASK                        (0x800U)
52287 #define NPX_NPXSR_V3_SHIFT                       (11U)
52288 /*! V3 - Key n Valid
52289  *  0b0..Not valid
52290  *  0b1..Valid
52291  */
52292 #define NPX_NPXSR_V3(x)                          (((uint32_t)(((uint32_t)(x)) << NPX_NPXSR_V3_SHIFT)) & NPX_NPXSR_V3_MASK)
52293 /*! @} */
52294 
52295 /*! @name CACMSK - Flash Cache Obfuscation Mask */
52296 /*! @{ */
52297 
52298 #define NPX_CACMSK_OBMASK_MASK                   (0xFFFFFFFFU)
52299 #define NPX_CACMSK_OBMASK_SHIFT                  (0U)
52300 /*! OBMASK - Obfuscation Mask */
52301 #define NPX_CACMSK_OBMASK(x)                     (((uint32_t)(((uint32_t)(x)) << NPX_CACMSK_OBMASK_SHIFT)) & NPX_CACMSK_OBMASK_MASK)
52302 /*! @} */
52303 
52304 /*! @name REMAP - Data Remap */
52305 /*! @{ */
52306 
52307 #define NPX_REMAP_REMAPLK_MASK                   (0x1U)
52308 #define NPX_REMAP_REMAPLK_SHIFT                  (0U)
52309 /*! REMAPLK - Remap Lock Enable
52310  *  0b1..Lock enabled: cannot write to REMAP
52311  *  0b0..Lock disabled: can write to REMAP
52312  */
52313 #define NPX_REMAP_REMAPLK(x)                     (((uint32_t)(((uint32_t)(x)) << NPX_REMAP_REMAPLK_SHIFT)) & NPX_REMAP_REMAPLK_MASK)
52314 
52315 #define NPX_REMAP_LIM_MASK                       (0x1F0000U)
52316 #define NPX_REMAP_LIM_SHIFT                      (16U)
52317 /*! LIM - LIM Remapping Address */
52318 #define NPX_REMAP_LIM(x)                         (((uint32_t)(((uint32_t)(x)) << NPX_REMAP_LIM_SHIFT)) & NPX_REMAP_LIM_MASK)
52319 
52320 #define NPX_REMAP_LIMDP_MASK                     (0x1F000000U)
52321 #define NPX_REMAP_LIMDP_SHIFT                    (24U)
52322 /*! LIMDP - LIMDP Remapping Address */
52323 #define NPX_REMAP_LIMDP(x)                       (((uint32_t)(((uint32_t)(x)) << NPX_REMAP_LIMDP_SHIFT)) & NPX_REMAP_LIMDP_MASK)
52324 /*! @} */
52325 
52326 /*! @name CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD - Bitmap of Valid Control for Memory Context 0..Bitmap of Valid Control for Memory Context 3 */
52327 /*! @{ */
52328 
52329 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL0_MASK (0x1U)
52330 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL0_SHIFT (0U)
52331 /*! VAL0 - Block valid enable for encryption/decryption
52332  *  0b0..Disable
52333  *  0b1..Enable
52334  */
52335 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL0(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL0_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL0_MASK)
52336 
52337 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL32_MASK (0x1U)
52338 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL32_SHIFT (0U)
52339 /*! VAL32 - Block valid enable for encryption/decryption
52340  *  0b0..Disable
52341  *  0b1..Enable
52342  */
52343 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL32(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL32_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL32_MASK)
52344 
52345 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL1_MASK (0x2U)
52346 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL1_SHIFT (1U)
52347 /*! VAL1 - Block valid enable for encryption/decryption
52348  *  0b0..Disable
52349  *  0b1..Enable
52350  */
52351 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL1(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL1_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL1_MASK)
52352 
52353 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL33_MASK (0x2U)
52354 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL33_SHIFT (1U)
52355 /*! VAL33 - Block valid enable for encryption/decryption
52356  *  0b0..Disable
52357  *  0b1..Enable
52358  */
52359 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL33(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL33_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL33_MASK)
52360 
52361 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL2_MASK (0x4U)
52362 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL2_SHIFT (2U)
52363 /*! VAL2 - Block valid enable for encryption/decryption
52364  *  0b0..Disable
52365  *  0b1..Enable
52366  */
52367 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL2(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL2_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL2_MASK)
52368 
52369 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL34_MASK (0x4U)
52370 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL34_SHIFT (2U)
52371 /*! VAL34 - Block valid enable for encryption/decryption
52372  *  0b0..Disable
52373  *  0b1..Enable
52374  */
52375 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL34(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL34_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL34_MASK)
52376 
52377 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL3_MASK (0x8U)
52378 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL3_SHIFT (3U)
52379 /*! VAL3 - Block valid enable for encryption/decryption
52380  *  0b0..Disable
52381  *  0b1..Enable
52382  */
52383 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL3(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL3_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL3_MASK)
52384 
52385 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL35_MASK (0x8U)
52386 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL35_SHIFT (3U)
52387 /*! VAL35 - Block valid enable for encryption/decryption
52388  *  0b0..Disable
52389  *  0b1..Enable
52390  */
52391 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL35(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL35_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL35_MASK)
52392 
52393 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL4_MASK (0x10U)
52394 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL4_SHIFT (4U)
52395 /*! VAL4 - Block valid enable for encryption/decryption
52396  *  0b0..Disable
52397  *  0b1..Enable
52398  */
52399 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL4(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL4_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL4_MASK)
52400 
52401 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL36_MASK (0x10U)
52402 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL36_SHIFT (4U)
52403 /*! VAL36 - Block valid enable for encryption/decryption
52404  *  0b0..Disable
52405  *  0b1..Enable
52406  */
52407 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL36(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL36_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL36_MASK)
52408 
52409 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL5_MASK (0x20U)
52410 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL5_SHIFT (5U)
52411 /*! VAL5 - Block valid enable for encryption/decryption
52412  *  0b0..Disable
52413  *  0b1..Enable
52414  */
52415 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL5(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL5_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL5_MASK)
52416 
52417 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL37_MASK (0x20U)
52418 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL37_SHIFT (5U)
52419 /*! VAL37 - Block valid enable for encryption/decryption
52420  *  0b0..Disable
52421  *  0b1..Enable
52422  */
52423 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL37(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL37_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL37_MASK)
52424 
52425 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL6_MASK (0x40U)
52426 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL6_SHIFT (6U)
52427 /*! VAL6 - Block valid enable for encryption/decryption
52428  *  0b0..Disable
52429  *  0b1..Enable
52430  */
52431 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL6(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL6_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL6_MASK)
52432 
52433 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL38_MASK (0x40U)
52434 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL38_SHIFT (6U)
52435 /*! VAL38 - Block valid enable for encryption/decryption
52436  *  0b0..Disable
52437  *  0b1..Enable
52438  */
52439 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL38(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL38_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL38_MASK)
52440 
52441 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL7_MASK (0x80U)
52442 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL7_SHIFT (7U)
52443 /*! VAL7 - Block valid enable for encryption/decryption
52444  *  0b0..Disable
52445  *  0b1..Enable
52446  */
52447 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL7(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL7_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL7_MASK)
52448 
52449 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL39_MASK (0x80U)
52450 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL39_SHIFT (7U)
52451 /*! VAL39 - Block valid enable for encryption/decryption
52452  *  0b0..Disable
52453  *  0b1..Enable
52454  */
52455 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL39(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL39_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL39_MASK)
52456 
52457 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL8_MASK (0x100U)
52458 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL8_SHIFT (8U)
52459 /*! VAL8 - Block valid enable for encryption/decryption
52460  *  0b0..Disable
52461  *  0b1..Enable
52462  */
52463 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL8(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL8_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL8_MASK)
52464 
52465 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL40_MASK (0x100U)
52466 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL40_SHIFT (8U)
52467 /*! VAL40 - Block valid enable for encryption/decryption
52468  *  0b0..Disable
52469  *  0b1..Enable
52470  */
52471 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL40(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL40_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL40_MASK)
52472 
52473 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL9_MASK (0x200U)
52474 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL9_SHIFT (9U)
52475 /*! VAL9 - Block valid enable for encryption/decryption
52476  *  0b0..Disable
52477  *  0b1..Enable
52478  */
52479 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL9(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL9_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL9_MASK)
52480 
52481 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL41_MASK (0x200U)
52482 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL41_SHIFT (9U)
52483 /*! VAL41 - Block valid enable for encryption/decryption
52484  *  0b0..Disable
52485  *  0b1..Enable
52486  */
52487 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL41(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL41_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL41_MASK)
52488 
52489 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL10_MASK (0x400U)
52490 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL10_SHIFT (10U)
52491 /*! VAL10 - Block valid enable for encryption/decryption
52492  *  0b0..Disable
52493  *  0b1..Enable
52494  */
52495 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL10(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL10_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL10_MASK)
52496 
52497 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL42_MASK (0x400U)
52498 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL42_SHIFT (10U)
52499 /*! VAL42 - Block valid enable for encryption/decryption
52500  *  0b0..Disable
52501  *  0b1..Enable
52502  */
52503 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL42(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL42_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL42_MASK)
52504 
52505 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL11_MASK (0x800U)
52506 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL11_SHIFT (11U)
52507 /*! VAL11 - Block valid enable for encryption/decryption
52508  *  0b0..Disable
52509  *  0b1..Enable
52510  */
52511 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL11(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL11_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL11_MASK)
52512 
52513 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL43_MASK (0x800U)
52514 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL43_SHIFT (11U)
52515 /*! VAL43 - Block valid enable for encryption/decryption
52516  *  0b0..Disable
52517  *  0b1..Enable
52518  */
52519 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL43(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL43_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL43_MASK)
52520 
52521 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL12_MASK (0x1000U)
52522 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL12_SHIFT (12U)
52523 /*! VAL12 - Block valid enable for encryption/decryption
52524  *  0b0..Disable
52525  *  0b1..Enable
52526  */
52527 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL12(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL12_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL12_MASK)
52528 
52529 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL44_MASK (0x1000U)
52530 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL44_SHIFT (12U)
52531 /*! VAL44 - Block valid enable for encryption/decryption
52532  *  0b0..Disable
52533  *  0b1..Enable
52534  */
52535 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL44(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL44_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL44_MASK)
52536 
52537 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL13_MASK (0x2000U)
52538 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL13_SHIFT (13U)
52539 /*! VAL13 - Block valid enable for encryption/decryption
52540  *  0b0..Disable
52541  *  0b1..Enable
52542  */
52543 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL13(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL13_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL13_MASK)
52544 
52545 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL45_MASK (0x2000U)
52546 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL45_SHIFT (13U)
52547 /*! VAL45 - Block valid enable for encryption/decryption
52548  *  0b0..Disable
52549  *  0b1..Enable
52550  */
52551 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL45(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL45_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL45_MASK)
52552 
52553 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL14_MASK (0x4000U)
52554 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL14_SHIFT (14U)
52555 /*! VAL14 - Block valid enable for encryption/decryption
52556  *  0b0..Disable
52557  *  0b1..Enable
52558  */
52559 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL14(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL14_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL14_MASK)
52560 
52561 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL46_MASK (0x4000U)
52562 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL46_SHIFT (14U)
52563 /*! VAL46 - Block valid enable for encryption/decryption
52564  *  0b0..Disable
52565  *  0b1..Enable
52566  */
52567 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL46(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL46_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL46_MASK)
52568 
52569 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL15_MASK (0x8000U)
52570 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL15_SHIFT (15U)
52571 /*! VAL15 - Block valid enable for encryption/decryption
52572  *  0b0..Disable
52573  *  0b1..Enable
52574  */
52575 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL15(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL15_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL15_MASK)
52576 
52577 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL47_MASK (0x8000U)
52578 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL47_SHIFT (15U)
52579 /*! VAL47 - Block valid enable for encryption/decryption
52580  *  0b0..Disable
52581  *  0b1..Enable
52582  */
52583 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL47(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL47_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL47_MASK)
52584 
52585 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL16_MASK (0x10000U)
52586 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL16_SHIFT (16U)
52587 /*! VAL16 - Block valid enable for encryption/decryption
52588  *  0b0..Disable
52589  *  0b1..Enable
52590  */
52591 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL16(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL16_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL16_MASK)
52592 
52593 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL48_MASK (0x10000U)
52594 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL48_SHIFT (16U)
52595 /*! VAL48 - Block valid enable for encryption/decryption
52596  *  0b0..Disable
52597  *  0b1..Enable
52598  */
52599 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL48(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL48_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL48_MASK)
52600 
52601 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL17_MASK (0x20000U)
52602 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL17_SHIFT (17U)
52603 /*! VAL17 - Block valid enable for encryption/decryption
52604  *  0b0..Disable
52605  *  0b1..Enable
52606  */
52607 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL17(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL17_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL17_MASK)
52608 
52609 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL49_MASK (0x20000U)
52610 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL49_SHIFT (17U)
52611 /*! VAL49 - Block valid enable for encryption/decryption
52612  *  0b0..Disable
52613  *  0b1..Enable
52614  */
52615 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL49(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL49_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL49_MASK)
52616 
52617 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL18_MASK (0x40000U)
52618 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL18_SHIFT (18U)
52619 /*! VAL18 - Block valid enable for encryption/decryption
52620  *  0b0..Disable
52621  *  0b1..Enable
52622  */
52623 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL18(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL18_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL18_MASK)
52624 
52625 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL50_MASK (0x40000U)
52626 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL50_SHIFT (18U)
52627 /*! VAL50 - Block valid enable for encryption/decryption
52628  *  0b0..Disable
52629  *  0b1..Enable
52630  */
52631 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL50(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL50_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL50_MASK)
52632 
52633 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL19_MASK (0x80000U)
52634 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL19_SHIFT (19U)
52635 /*! VAL19 - Block valid enable for encryption/decryption
52636  *  0b0..Disable
52637  *  0b1..Enable
52638  */
52639 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL19(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL19_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL19_MASK)
52640 
52641 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL51_MASK (0x80000U)
52642 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL51_SHIFT (19U)
52643 /*! VAL51 - Block valid enable for encryption/decryption
52644  *  0b0..Disable
52645  *  0b1..Enable
52646  */
52647 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL51(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL51_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL51_MASK)
52648 
52649 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL20_MASK (0x100000U)
52650 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL20_SHIFT (20U)
52651 /*! VAL20 - Block valid enable for encryption/decryption
52652  *  0b0..Disable
52653  *  0b1..Enable
52654  */
52655 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL20(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL20_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL20_MASK)
52656 
52657 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL52_MASK (0x100000U)
52658 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL52_SHIFT (20U)
52659 /*! VAL52 - Block valid enable for encryption/decryption
52660  *  0b0..Disable
52661  *  0b1..Enable
52662  */
52663 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL52(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL52_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL52_MASK)
52664 
52665 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL21_MASK (0x200000U)
52666 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL21_SHIFT (21U)
52667 /*! VAL21 - Block valid enable for encryption/decryption
52668  *  0b0..Disable
52669  *  0b1..Enable
52670  */
52671 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL21(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL21_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL21_MASK)
52672 
52673 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL53_MASK (0x200000U)
52674 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL53_SHIFT (21U)
52675 /*! VAL53 - Block valid enable for encryption/decryption
52676  *  0b0..Disable
52677  *  0b1..Enable
52678  */
52679 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL53(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL53_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL53_MASK)
52680 
52681 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL22_MASK (0x400000U)
52682 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL22_SHIFT (22U)
52683 /*! VAL22 - Block valid enable for encryption/decryption
52684  *  0b0..Disable
52685  *  0b1..Enable
52686  */
52687 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL22(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL22_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL22_MASK)
52688 
52689 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL54_MASK (0x400000U)
52690 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL54_SHIFT (22U)
52691 /*! VAL54 - Block valid enable for encryption/decryption
52692  *  0b0..Disable
52693  *  0b1..Enable
52694  */
52695 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL54(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL54_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL54_MASK)
52696 
52697 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL23_MASK (0x800000U)
52698 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL23_SHIFT (23U)
52699 /*! VAL23 - Block valid enable for encryption/decryption
52700  *  0b0..Disable
52701  *  0b1..Enable
52702  */
52703 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL23(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL23_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL23_MASK)
52704 
52705 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL55_MASK (0x800000U)
52706 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL55_SHIFT (23U)
52707 /*! VAL55 - Block valid enable for encryption/decryption
52708  *  0b0..Disable
52709  *  0b1..Enable
52710  */
52711 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL55(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL55_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL55_MASK)
52712 
52713 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL24_MASK (0x1000000U)
52714 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL24_SHIFT (24U)
52715 /*! VAL24 - Block valid enable for encryption/decryption
52716  *  0b0..Disable
52717  *  0b1..Enable
52718  */
52719 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL24(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL24_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL24_MASK)
52720 
52721 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL56_MASK (0x1000000U)
52722 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL56_SHIFT (24U)
52723 /*! VAL56 - Block valid enable for encryption/decryption
52724  *  0b0..Disable
52725  *  0b1..Enable
52726  */
52727 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL56(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL56_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL56_MASK)
52728 
52729 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL25_MASK (0x2000000U)
52730 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL25_SHIFT (25U)
52731 /*! VAL25 - Block valid enable for encryption/decryption
52732  *  0b0..Disable
52733  *  0b1..Enable
52734  */
52735 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL25(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL25_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL25_MASK)
52736 
52737 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL57_MASK (0x2000000U)
52738 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL57_SHIFT (25U)
52739 /*! VAL57 - Block valid enable for encryption/decryption
52740  *  0b0..Disable
52741  *  0b1..Enable
52742  */
52743 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL57(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL57_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL57_MASK)
52744 
52745 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL26_MASK (0x4000000U)
52746 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL26_SHIFT (26U)
52747 /*! VAL26 - Block valid enable for encryption/decryption
52748  *  0b0..Disable
52749  *  0b1..Enable
52750  */
52751 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL26(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL26_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL26_MASK)
52752 
52753 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL58_MASK (0x4000000U)
52754 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL58_SHIFT (26U)
52755 /*! VAL58 - Block valid enable for encryption/decryption
52756  *  0b0..Disable
52757  *  0b1..Enable
52758  */
52759 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL58(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL58_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL58_MASK)
52760 
52761 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL27_MASK (0x8000000U)
52762 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL27_SHIFT (27U)
52763 /*! VAL27 - Block valid enable for encryption/decryption
52764  *  0b0..Disable
52765  *  0b1..Enable
52766  */
52767 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL27(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL27_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL27_MASK)
52768 
52769 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL59_MASK (0x8000000U)
52770 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL59_SHIFT (27U)
52771 /*! VAL59 - Block valid enable for encryption/decryption
52772  *  0b0..Disable
52773  *  0b1..Enable
52774  */
52775 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL59(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL59_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL59_MASK)
52776 
52777 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL28_MASK (0x10000000U)
52778 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL28_SHIFT (28U)
52779 /*! VAL28 - Block valid enable for encryption/decryption
52780  *  0b0..Disable
52781  *  0b1..Enable
52782  */
52783 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL28(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL28_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL28_MASK)
52784 
52785 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL60_MASK (0x10000000U)
52786 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL60_SHIFT (28U)
52787 /*! VAL60 - Block valid enable for encryption/decryption
52788  *  0b0..Disable
52789  *  0b1..Enable
52790  */
52791 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL60(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL60_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL60_MASK)
52792 
52793 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL29_MASK (0x20000000U)
52794 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL29_SHIFT (29U)
52795 /*! VAL29 - Block valid enable for encryption/decryption
52796  *  0b0..Disable
52797  *  0b1..Enable
52798  */
52799 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL29(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL29_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL29_MASK)
52800 
52801 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL61_MASK (0x20000000U)
52802 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL61_SHIFT (29U)
52803 /*! VAL61 - Block valid enable for encryption/decryption
52804  *  0b0..Disable
52805  *  0b1..Enable
52806  */
52807 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL61(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL61_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL61_MASK)
52808 
52809 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL30_MASK (0x40000000U)
52810 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL30_SHIFT (30U)
52811 /*! VAL30 - Block valid enable for encryption/decryption
52812  *  0b0..Disable
52813  *  0b1..Enable
52814  */
52815 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL30(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL30_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL30_MASK)
52816 
52817 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL62_MASK (0x40000000U)
52818 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL62_SHIFT (30U)
52819 /*! VAL62 - Block valid enable for encryption/decryption
52820  *  0b0..Disable
52821  *  0b1..Enable
52822  */
52823 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL62(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL62_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL62_MASK)
52824 
52825 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL31_MASK (0x80000000U)
52826 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL31_SHIFT (31U)
52827 /*! VAL31 - Block valid enable for encryption/decryption
52828  *  0b0..Disable
52829  *  0b1..Enable
52830  */
52831 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL31(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL31_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL31_MASK)
52832 
52833 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL63_MASK (0x80000000U)
52834 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL63_SHIFT (31U)
52835 /*! VAL63 - Block valid enable for encryption/decryption
52836  *  0b0..Disable
52837  *  0b1..Enable
52838  */
52839 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL63(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL63_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL63_MASK)
52840 /*! @} */
52841 
52842 /* The count of NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD */
52843 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_COUNT (4U)
52844 
52845 /* The count of NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD */
52846 #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_COUNT2 (2U)
52847 
52848 /*! @name CTX_VALID_IV_ARRAY_BIVCTX_ARRAY_BIVCTX_WD - Block Initial Vector for Memory Context 0..Block Initial Vector for Memory Context 3 */
52849 /*! @{ */
52850 
52851 #define NPX_CTX_VALID_IV_ARRAY_BIVCTX_ARRAY_BIVCTX_WD_BIV_WD0_MASK (0xFFFFFFFFU)
52852 #define NPX_CTX_VALID_IV_ARRAY_BIVCTX_ARRAY_BIVCTX_WD_BIV_WD0_SHIFT (0U)
52853 /*! BIV_WD0 - Block Initial Vector Word0 */
52854 #define NPX_CTX_VALID_IV_ARRAY_BIVCTX_ARRAY_BIVCTX_WD_BIV_WD0(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_BIVCTX_ARRAY_BIVCTX_WD_BIV_WD0_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_BIVCTX_ARRAY_BIVCTX_WD_BIV_WD0_MASK)
52855 
52856 #define NPX_CTX_VALID_IV_ARRAY_BIVCTX_ARRAY_BIVCTX_WD_BIV_WD1_MASK (0xFFFFFFFFU)
52857 #define NPX_CTX_VALID_IV_ARRAY_BIVCTX_ARRAY_BIVCTX_WD_BIV_WD1_SHIFT (0U)
52858 /*! BIV_WD1 - Block Initial Vector Word1 */
52859 #define NPX_CTX_VALID_IV_ARRAY_BIVCTX_ARRAY_BIVCTX_WD_BIV_WD1(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_BIVCTX_ARRAY_BIVCTX_WD_BIV_WD1_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_BIVCTX_ARRAY_BIVCTX_WD_BIV_WD1_MASK)
52860 /*! @} */
52861 
52862 /* The count of NPX_CTX_VALID_IV_ARRAY_BIVCTX_ARRAY_BIVCTX_WD */
52863 #define NPX_CTX_VALID_IV_ARRAY_BIVCTX_ARRAY_BIVCTX_WD_COUNT (4U)
52864 
52865 /* The count of NPX_CTX_VALID_IV_ARRAY_BIVCTX_ARRAY_BIVCTX_WD */
52866 #define NPX_CTX_VALID_IV_ARRAY_BIVCTX_ARRAY_BIVCTX_WD_COUNT2 (2U)
52867 
52868 
52869 /*!
52870  * @}
52871  */ /* end of group NPX_Register_Masks */
52872 
52873 
52874 /* NPX - Peripheral instance base addresses */
52875 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
52876   /** Peripheral NPX0 base address */
52877   #define NPX0_BASE                                (0x500CC000u)
52878   /** Peripheral NPX0 base address */
52879   #define NPX0_BASE_NS                             (0x400CC000u)
52880   /** Peripheral NPX0 base pointer */
52881   #define NPX0                                     ((NPX_Type *)NPX0_BASE)
52882   /** Peripheral NPX0 base pointer */
52883   #define NPX0_NS                                  ((NPX_Type *)NPX0_BASE_NS)
52884   /** Array initializer of NPX peripheral base addresses */
52885   #define NPX_BASE_ADDRS                           { NPX0_BASE }
52886   /** Array initializer of NPX peripheral base pointers */
52887   #define NPX_BASE_PTRS                            { NPX0 }
52888   /** Array initializer of NPX peripheral base addresses */
52889   #define NPX_BASE_ADDRS_NS                        { NPX0_BASE_NS }
52890   /** Array initializer of NPX peripheral base pointers */
52891   #define NPX_BASE_PTRS_NS                         { NPX0_NS }
52892 #else
52893   /** Peripheral NPX0 base address */
52894   #define NPX0_BASE                                (0x400CC000u)
52895   /** Peripheral NPX0 base pointer */
52896   #define NPX0                                     ((NPX_Type *)NPX0_BASE)
52897   /** Array initializer of NPX peripheral base addresses */
52898   #define NPX_BASE_ADDRS                           { NPX0_BASE }
52899   /** Array initializer of NPX peripheral base pointers */
52900   #define NPX_BASE_PTRS                            { NPX0 }
52901 #endif
52902 
52903 /*!
52904  * @}
52905  */ /* end of group NPX_Peripheral_Access_Layer */
52906 
52907 
52908 /* ----------------------------------------------------------------------------
52909    -- OSTIMER Peripheral Access Layer
52910    ---------------------------------------------------------------------------- */
52911 
52912 /*!
52913  * @addtogroup OSTIMER_Peripheral_Access_Layer OSTIMER Peripheral Access Layer
52914  * @{
52915  */
52916 
52917 /** OSTIMER - Register Layout Typedef */
52918 typedef struct {
52919   __I  uint32_t EVTIMERL;                          /**< EVTIMER Low, offset: 0x0 */
52920   __I  uint32_t EVTIMERH;                          /**< EVTIMER High, offset: 0x4 */
52921   __I  uint32_t CAPTURE_L;                         /**< Local Capture Low for CPU, offset: 0x8 */
52922   __I  uint32_t CAPTURE_H;                         /**< Local Capture High for CPU, offset: 0xC */
52923   __IO uint32_t MATCH_L;                           /**< Local Match Low for CPU, offset: 0x10 */
52924   __IO uint32_t MATCH_H;                           /**< Local Match High for CPU, offset: 0x14 */
52925        uint8_t RESERVED_0[4];
52926   __IO uint32_t OSEVENT_CTRL;                      /**< OSTIMER Control for CPU, offset: 0x1C */
52927 } OSTIMER_Type;
52928 
52929 /* ----------------------------------------------------------------------------
52930    -- OSTIMER Register Masks
52931    ---------------------------------------------------------------------------- */
52932 
52933 /*!
52934  * @addtogroup OSTIMER_Register_Masks OSTIMER Register Masks
52935  * @{
52936  */
52937 
52938 /*! @name EVTIMERL - EVTIMER Low */
52939 /*! @{ */
52940 
52941 #define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_MASK (0xFFFFFFFFU)
52942 #define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_SHIFT (0U)
52943 /*! EVTIMER_COUNT_VALUE - EVTimer Count Value */
52944 #define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE(x)  (((uint32_t)(((uint32_t)(x)) << OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_SHIFT)) & OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_MASK)
52945 /*! @} */
52946 
52947 /*! @name EVTIMERH - EVTIMER High */
52948 /*! @{ */
52949 
52950 #define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_MASK (0x3FFU)
52951 #define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_SHIFT (0U)
52952 /*! EVTIMER_COUNT_VALUE - EVTimer Count Value */
52953 #define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE(x)  (((uint32_t)(((uint32_t)(x)) << OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_SHIFT)) & OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_MASK)
52954 /*! @} */
52955 
52956 /*! @name CAPTURE_L - Local Capture Low for CPU */
52957 /*! @{ */
52958 
52959 #define OSTIMER_CAPTURE_L_CAPTURE_VALUE_MASK     (0xFFFFFFFFU)
52960 #define OSTIMER_CAPTURE_L_CAPTURE_VALUE_SHIFT    (0U)
52961 /*! CAPTURE_VALUE - EVTimer Capture Value */
52962 #define OSTIMER_CAPTURE_L_CAPTURE_VALUE(x)       (((uint32_t)(((uint32_t)(x)) << OSTIMER_CAPTURE_L_CAPTURE_VALUE_SHIFT)) & OSTIMER_CAPTURE_L_CAPTURE_VALUE_MASK)
52963 /*! @} */
52964 
52965 /*! @name CAPTURE_H - Local Capture High for CPU */
52966 /*! @{ */
52967 
52968 #define OSTIMER_CAPTURE_H_CAPTURE_VALUE_MASK     (0x3FFU)
52969 #define OSTIMER_CAPTURE_H_CAPTURE_VALUE_SHIFT    (0U)
52970 /*! CAPTURE_VALUE - EVTimer Capture Value */
52971 #define OSTIMER_CAPTURE_H_CAPTURE_VALUE(x)       (((uint32_t)(((uint32_t)(x)) << OSTIMER_CAPTURE_H_CAPTURE_VALUE_SHIFT)) & OSTIMER_CAPTURE_H_CAPTURE_VALUE_MASK)
52972 /*! @} */
52973 
52974 /*! @name MATCH_L - Local Match Low for CPU */
52975 /*! @{ */
52976 
52977 #define OSTIMER_MATCH_L_MATCH_VALUE_MASK         (0xFFFFFFFFU)
52978 #define OSTIMER_MATCH_L_MATCH_VALUE_SHIFT        (0U)
52979 /*! MATCH_VALUE - EVTimer Match Value */
52980 #define OSTIMER_MATCH_L_MATCH_VALUE(x)           (((uint32_t)(((uint32_t)(x)) << OSTIMER_MATCH_L_MATCH_VALUE_SHIFT)) & OSTIMER_MATCH_L_MATCH_VALUE_MASK)
52981 /*! @} */
52982 
52983 /*! @name MATCH_H - Local Match High for CPU */
52984 /*! @{ */
52985 
52986 #define OSTIMER_MATCH_H_MATCH_VALUE_MASK         (0x3FFU)
52987 #define OSTIMER_MATCH_H_MATCH_VALUE_SHIFT        (0U)
52988 /*! MATCH_VALUE - EVTimer Match Value */
52989 #define OSTIMER_MATCH_H_MATCH_VALUE(x)           (((uint32_t)(((uint32_t)(x)) << OSTIMER_MATCH_H_MATCH_VALUE_SHIFT)) & OSTIMER_MATCH_H_MATCH_VALUE_MASK)
52990 /*! @} */
52991 
52992 /*! @name OSEVENT_CTRL - OSTIMER Control for CPU */
52993 /*! @{ */
52994 
52995 #define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK (0x1U)
52996 #define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_SHIFT (0U)
52997 /*! OSTIMER_INTRFLAG - Interrupt Flag */
52998 #define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_SHIFT)) & OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK)
52999 
53000 #define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK (0x2U)
53001 #define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_SHIFT (1U)
53002 /*! OSTIMER_INTENA - Interrupt or Wake-Up Request
53003  *  0b0..Interrupts blocked
53004  *  0b1..Interrupts enabled
53005  */
53006 #define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA(x)   (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_SHIFT)) & OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK)
53007 
53008 #define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK   (0x4U)
53009 #define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_SHIFT  (2U)
53010 /*! MATCH_WR_RDY - EVTimer Match Write Ready */
53011 #define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY(x)     (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_SHIFT)) & OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK)
53012 /*! @} */
53013 
53014 
53015 /*!
53016  * @}
53017  */ /* end of group OSTIMER_Register_Masks */
53018 
53019 
53020 /* OSTIMER - Peripheral instance base addresses */
53021 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
53022   /** Peripheral OSTIMER0 base address */
53023   #define OSTIMER0_BASE                            (0x50049000u)
53024   /** Peripheral OSTIMER0 base address */
53025   #define OSTIMER0_BASE_NS                         (0x40049000u)
53026   /** Peripheral OSTIMER0 base pointer */
53027   #define OSTIMER0                                 ((OSTIMER_Type *)OSTIMER0_BASE)
53028   /** Peripheral OSTIMER0 base pointer */
53029   #define OSTIMER0_NS                              ((OSTIMER_Type *)OSTIMER0_BASE_NS)
53030   /** Array initializer of OSTIMER peripheral base addresses */
53031   #define OSTIMER_BASE_ADDRS                       { OSTIMER0_BASE }
53032   /** Array initializer of OSTIMER peripheral base pointers */
53033   #define OSTIMER_BASE_PTRS                        { OSTIMER0 }
53034   /** Array initializer of OSTIMER peripheral base addresses */
53035   #define OSTIMER_BASE_ADDRS_NS                    { OSTIMER0_BASE_NS }
53036   /** Array initializer of OSTIMER peripheral base pointers */
53037   #define OSTIMER_BASE_PTRS_NS                     { OSTIMER0_NS }
53038 #else
53039   /** Peripheral OSTIMER0 base address */
53040   #define OSTIMER0_BASE                            (0x40049000u)
53041   /** Peripheral OSTIMER0 base pointer */
53042   #define OSTIMER0                                 ((OSTIMER_Type *)OSTIMER0_BASE)
53043   /** Array initializer of OSTIMER peripheral base addresses */
53044   #define OSTIMER_BASE_ADDRS                       { OSTIMER0_BASE }
53045   /** Array initializer of OSTIMER peripheral base pointers */
53046   #define OSTIMER_BASE_PTRS                        { OSTIMER0 }
53047 #endif
53048 /** Interrupt vectors for the OSTIMER peripheral type */
53049 #define OSTIMER_IRQS                             { OS_EVENT_IRQn }
53050 
53051 /*!
53052  * @}
53053  */ /* end of group OSTIMER_Peripheral_Access_Layer */
53054 
53055 
53056 /* ----------------------------------------------------------------------------
53057    -- OTPC Peripheral Access Layer
53058    ---------------------------------------------------------------------------- */
53059 
53060 /*!
53061  * @addtogroup OTPC_Peripheral_Access_Layer OTPC Peripheral Access Layer
53062  * @{
53063  */
53064 
53065 /** OTPC - Register Layout Typedef */
53066 typedef struct {
53067   __I  uint32_t VERID;                             /**< Version ID, offset: 0x0 */
53068   __I  uint32_t PARAM;                             /**< Parameters, offset: 0x4 */
53069   __IO uint32_t SR;                                /**< Status, offset: 0x8 */
53070        uint8_t RESERVED_0[4];
53071   __IO uint32_t RWC;                               /**< Read and Write Control, offset: 0x10 */
53072   __IO uint32_t RLC;                               /**< Reload Control, offset: 0x14 */
53073   __IO uint32_t PCR;                               /**< Power Control, offset: 0x18 */
53074        uint8_t RESERVED_1[4];
53075   __IO uint32_t WDATA;                             /**< Write Data, offset: 0x20 */
53076   __I  uint32_t RDATA;                             /**< Read Data, offset: 0x24 */
53077        uint8_t RESERVED_2[8];
53078   __IO uint32_t TIMING1;                           /**< Timing1, offset: 0x30 */
53079   __IO uint32_t TIMING2;                           /**< Timing2, offset: 0x34 */
53080        uint8_t RESERVED_3[456];
53081   __I  uint32_t LOCK;                              /**< Lock, offset: 0x200 */
53082   __I  uint32_t SECURE;                            /**< Secure, offset: 0x204 */
53083   __I  uint32_t SECURE_INV;                        /**< Inverted Secure, offset: 0x208 */
53084   __I  uint32_t DBG_KEY;                           /**< Debug and Key, offset: 0x20C */
53085   __IO uint32_t MISC_CFG;                          /**< MISC Config, offset: 0x210 */
53086   __IO uint32_t PHANTOM_CFG;                       /**< PHANTOM Config, offset: 0x214 */
53087   __IO uint32_t FLEX_CFG0;                         /**< Flexible Config 0, offset: 0x218 */
53088   __IO uint32_t FLEX_CFG1;                         /**< Flexible Config 1, offset: 0x21C */
53089 } OTPC_Type;
53090 
53091 /* ----------------------------------------------------------------------------
53092    -- OTPC Register Masks
53093    ---------------------------------------------------------------------------- */
53094 
53095 /*!
53096  * @addtogroup OTPC_Register_Masks OTPC Register Masks
53097  * @{
53098  */
53099 
53100 /*! @name VERID - Version ID */
53101 /*! @{ */
53102 
53103 #define OTPC_VERID_FEATURE_MASK                  (0xFFFFU)
53104 #define OTPC_VERID_FEATURE_SHIFT                 (0U)
53105 /*! FEATURE - Feature Specification Number
53106  *  0b0000000000000000..Standard feature set
53107  */
53108 #define OTPC_VERID_FEATURE(x)                    (((uint32_t)(((uint32_t)(x)) << OTPC_VERID_FEATURE_SHIFT)) & OTPC_VERID_FEATURE_MASK)
53109 
53110 #define OTPC_VERID_MINOR_MASK                    (0xFF0000U)
53111 #define OTPC_VERID_MINOR_SHIFT                   (16U)
53112 /*! MINOR - Minor Version Number */
53113 #define OTPC_VERID_MINOR(x)                      (((uint32_t)(((uint32_t)(x)) << OTPC_VERID_MINOR_SHIFT)) & OTPC_VERID_MINOR_MASK)
53114 
53115 #define OTPC_VERID_MAJOR_MASK                    (0xFF000000U)
53116 #define OTPC_VERID_MAJOR_SHIFT                   (24U)
53117 /*! MAJOR - Major Version Number */
53118 #define OTPC_VERID_MAJOR(x)                      (((uint32_t)(((uint32_t)(x)) << OTPC_VERID_MAJOR_SHIFT)) & OTPC_VERID_MAJOR_MASK)
53119 /*! @} */
53120 
53121 /*! @name PARAM - Parameters */
53122 /*! @{ */
53123 
53124 #define OTPC_PARAM_NUM_FUSE_MASK                 (0xFFFFU)
53125 #define OTPC_PARAM_NUM_FUSE_SHIFT                (0U)
53126 /*! NUM_FUSE - Number of fuse bytes */
53127 #define OTPC_PARAM_NUM_FUSE(x)                   (((uint32_t)(((uint32_t)(x)) << OTPC_PARAM_NUM_FUSE_SHIFT)) & OTPC_PARAM_NUM_FUSE_MASK)
53128 /*! @} */
53129 
53130 /*! @name SR - Status */
53131 /*! @{ */
53132 
53133 #define OTPC_SR_BUSY_MASK                        (0x1U)
53134 #define OTPC_SR_BUSY_SHIFT                       (0U)
53135 /*! BUSY - Busy status
53136  *  0b0..Not busy (transaction complete)
53137  *  0b1..Busy
53138  */
53139 #define OTPC_SR_BUSY(x)                          (((uint32_t)(((uint32_t)(x)) << OTPC_SR_BUSY_SHIFT)) & OTPC_SR_BUSY_MASK)
53140 
53141 #define OTPC_SR_ERROR_MASK                       (0x2U)
53142 #define OTPC_SR_ERROR_SHIFT                      (1U)
53143 /*! ERROR - Error flag
53144  *  0b0..No error
53145  *  0b1..Error
53146  */
53147 #define OTPC_SR_ERROR(x)                         (((uint32_t)(((uint32_t)(x)) << OTPC_SR_ERROR_SHIFT)) & OTPC_SR_ERROR_MASK)
53148 
53149 #define OTPC_SR_ECC_SF_MASK                      (0x4U)
53150 #define OTPC_SR_ECC_SF_SHIFT                     (2U)
53151 /*! ECC_SF - ECC single fault
53152  *  0b0..No fault
53153  *  0b1..Fault
53154  */
53155 #define OTPC_SR_ECC_SF(x)                        (((uint32_t)(((uint32_t)(x)) << OTPC_SR_ECC_SF_SHIFT)) & OTPC_SR_ECC_SF_MASK)
53156 
53157 #define OTPC_SR_ECC_DF_MASK                      (0x8U)
53158 #define OTPC_SR_ECC_DF_SHIFT                     (3U)
53159 /*! ECC_DF - ECC double fault
53160  *  0b0..No fault
53161  *  0b1..Fault
53162  */
53163 #define OTPC_SR_ECC_DF(x)                        (((uint32_t)(((uint32_t)(x)) << OTPC_SR_ECC_DF_SHIFT)) & OTPC_SR_ECC_DF_MASK)
53164 
53165 #define OTPC_SR_TRI_F_MASK                       (0x10U)
53166 #define OTPC_SR_TRI_F_SHIFT                      (4U)
53167 /*! TRI_F - Triple voting fault
53168  *  0b0..No fault
53169  *  0b1..Fault
53170  */
53171 #define OTPC_SR_TRI_F(x)                         (((uint32_t)(((uint32_t)(x)) << OTPC_SR_TRI_F_SHIFT)) & OTPC_SR_TRI_F_MASK)
53172 
53173 #define OTPC_SR_RD_FUSE_LOCK_MASK                (0x100U)
53174 #define OTPC_SR_RD_FUSE_LOCK_SHIFT               (8U)
53175 /*! RD_FUSE_LOCK - Read fuse lock error
53176  *  0b0..No error
53177  *  0b1..Error
53178  */
53179 #define OTPC_SR_RD_FUSE_LOCK(x)                  (((uint32_t)(((uint32_t)(x)) << OTPC_SR_RD_FUSE_LOCK_SHIFT)) & OTPC_SR_RD_FUSE_LOCK_MASK)
53180 
53181 #define OTPC_SR_WR_FUSE_LOCK_MASK                (0x200U)
53182 #define OTPC_SR_WR_FUSE_LOCK_SHIFT               (9U)
53183 /*! WR_FUSE_LOCK - Write fuse lock error
53184  *  0b0..No error
53185  *  0b1..Error
53186  */
53187 #define OTPC_SR_WR_FUSE_LOCK(x)                  (((uint32_t)(((uint32_t)(x)) << OTPC_SR_WR_FUSE_LOCK_SHIFT)) & OTPC_SR_WR_FUSE_LOCK_MASK)
53188 
53189 #define OTPC_SR_RD_REG_LOCK_MASK                 (0x400U)
53190 #define OTPC_SR_RD_REG_LOCK_SHIFT                (10U)
53191 /*! RD_REG_LOCK - Read register lock error
53192  *  0b0..No error
53193  *  0b1..Error
53194  */
53195 #define OTPC_SR_RD_REG_LOCK(x)                   (((uint32_t)(((uint32_t)(x)) << OTPC_SR_RD_REG_LOCK_SHIFT)) & OTPC_SR_RD_REG_LOCK_MASK)
53196 
53197 #define OTPC_SR_WR_REG_LOCK_MASK                 (0x800U)
53198 #define OTPC_SR_WR_REG_LOCK_SHIFT                (11U)
53199 /*! WR_REG_LOCK - Write register lock error
53200  *  0b0..No error
53201  *  0b1..Error
53202  */
53203 #define OTPC_SR_WR_REG_LOCK(x)                   (((uint32_t)(((uint32_t)(x)) << OTPC_SR_WR_REG_LOCK_SHIFT)) & OTPC_SR_WR_REG_LOCK_MASK)
53204 
53205 #define OTPC_SR_WR_REG_BUSY_MASK                 (0x1000U)
53206 #define OTPC_SR_WR_REG_BUSY_SHIFT                (12U)
53207 /*! WR_REG_BUSY - Write register when busy error
53208  *  0b0..No error
53209  *  0b1..Error
53210  */
53211 #define OTPC_SR_WR_REG_BUSY(x)                   (((uint32_t)(((uint32_t)(x)) << OTPC_SR_WR_REG_BUSY_SHIFT)) & OTPC_SR_WR_REG_BUSY_MASK)
53212 
53213 #define OTPC_SR_WR_POWER_OFF_MASK                (0x2000U)
53214 #define OTPC_SR_WR_POWER_OFF_SHIFT               (13U)
53215 /*! WR_POWER_OFF - Write when power off error
53216  *  0b0..No error
53217  *  0b1..Error
53218  */
53219 #define OTPC_SR_WR_POWER_OFF(x)                  (((uint32_t)(((uint32_t)(x)) << OTPC_SR_WR_POWER_OFF_SHIFT)) & OTPC_SR_WR_POWER_OFF_MASK)
53220 
53221 #define OTPC_SR_FSM_MASK                         (0x10000U)
53222 #define OTPC_SR_FSM_SHIFT                        (16U)
53223 /*! FSM - Finite-state machine error
53224  *  0b0..No error
53225  *  0b1..Error
53226  */
53227 #define OTPC_SR_FSM(x)                           (((uint32_t)(((uint32_t)(x)) << OTPC_SR_FSM_SHIFT)) & OTPC_SR_FSM_MASK)
53228 
53229 #define OTPC_SR_FLC_MASK                         (0x20000U)
53230 #define OTPC_SR_FLC_SHIFT                        (17U)
53231 /*! FLC - Fuse load counter error
53232  *  0b0..No error
53233  *  0b1..Error
53234  */
53235 #define OTPC_SR_FLC(x)                           (((uint32_t)(((uint32_t)(x)) << OTPC_SR_FLC_SHIFT)) & OTPC_SR_FLC_MASK)
53236 
53237 #define OTPC_SR_ADC_MASK                         (0x40000U)
53238 #define OTPC_SR_ADC_SHIFT                        (18U)
53239 /*! ADC - Address and data compare error
53240  *  0b0..No error
53241  *  0b1..Error
53242  */
53243 #define OTPC_SR_ADC(x)                           (((uint32_t)(((uint32_t)(x)) << OTPC_SR_ADC_SHIFT)) & OTPC_SR_ADC_MASK)
53244 
53245 #define OTPC_SR_IRC_MASK                         (0x80000U)
53246 #define OTPC_SR_IRC_SHIFT                        (19U)
53247 /*! IRC - Inverted register compare error
53248  *  0b0..No error
53249  *  0b1..Error
53250  */
53251 #define OTPC_SR_IRC(x)                           (((uint32_t)(((uint32_t)(x)) << OTPC_SR_IRC_SHIFT)) & OTPC_SR_IRC_MASK)
53252 
53253 #define OTPC_SR_FSC_MASK                         (0x100000U)
53254 #define OTPC_SR_FSC_SHIFT                        (20U)
53255 /*! FSC - Fuse and shadow register compare error
53256  *  0b0..No error
53257  *  0b1..Error
53258  */
53259 #define OTPC_SR_FSC(x)                           (((uint32_t)(((uint32_t)(x)) << OTPC_SR_FSC_SHIFT)) & OTPC_SR_FSC_MASK)
53260 /*! @} */
53261 
53262 /*! @name RWC - Read and Write Control */
53263 /*! @{ */
53264 
53265 #define OTPC_RWC_ADDR_MASK                       (0x7FU)
53266 #define OTPC_RWC_ADDR_SHIFT                      (0U)
53267 /*! ADDR - EFUSE address */
53268 #define OTPC_RWC_ADDR(x)                         (((uint32_t)(((uint32_t)(x)) << OTPC_RWC_ADDR_SHIFT)) & OTPC_RWC_ADDR_MASK)
53269 
53270 #define OTPC_RWC_WR_ALL1S_MASK                   (0x1000U)
53271 #define OTPC_RWC_WR_ALL1S_SHIFT                  (12U)
53272 /*! WR_ALL1S - Write all 1s
53273  *  0b0..Uses the WDATA value
53274  *  0b1..Writes all 1s
53275  */
53276 #define OTPC_RWC_WR_ALL1S(x)                     (((uint32_t)(((uint32_t)(x)) << OTPC_RWC_WR_ALL1S_SHIFT)) & OTPC_RWC_WR_ALL1S_MASK)
53277 
53278 #define OTPC_RWC_READ_EFUSE_MASK                 (0x2000U)
53279 #define OTPC_RWC_READ_EFUSE_SHIFT                (13U)
53280 /*! READ_EFUSE - Read EFUSE
53281  *  0b0..Starts program operation when the WR_UNLOCK value is 0x9527; otherwise, takes no action.
53282  *  0b1..Starts read operation
53283  */
53284 #define OTPC_RWC_READ_EFUSE(x)                   (((uint32_t)(((uint32_t)(x)) << OTPC_RWC_READ_EFUSE_SHIFT)) & OTPC_RWC_READ_EFUSE_MASK)
53285 
53286 #define OTPC_RWC_READ_UPDATE_MASK                (0x4000U)
53287 #define OTPC_RWC_READ_UPDATE_SHIFT               (14U)
53288 /*! READ_UPDATE - Read update
53289  *  0b0..Shadow register does not update
53290  *  0b1..Shadow register updates
53291  */
53292 #define OTPC_RWC_READ_UPDATE(x)                  (((uint32_t)(((uint32_t)(x)) << OTPC_RWC_READ_UPDATE_SHIFT)) & OTPC_RWC_READ_UPDATE_MASK)
53293 
53294 #define OTPC_RWC_WR_UNLOCK_MASK                  (0xFFFF0000U)
53295 #define OTPC_RWC_WR_UNLOCK_SHIFT                 (16U)
53296 /*! WR_UNLOCK - Write Unlock */
53297 #define OTPC_RWC_WR_UNLOCK(x)                    (((uint32_t)(((uint32_t)(x)) << OTPC_RWC_WR_UNLOCK_SHIFT)) & OTPC_RWC_WR_UNLOCK_MASK)
53298 /*! @} */
53299 
53300 /*! @name RLC - Reload Control */
53301 /*! @{ */
53302 
53303 #define OTPC_RLC_RELOAD_SHADOWS_MASK             (0x1U)
53304 #define OTPC_RLC_RELOAD_SHADOWS_SHIFT            (0U)
53305 /*! RELOAD_SHADOWS - Reload shadow registers
53306  *  0b0..No action (when writing) or reload complete (when reading)
53307  *  0b1..Reload
53308  */
53309 #define OTPC_RLC_RELOAD_SHADOWS(x)               (((uint32_t)(((uint32_t)(x)) << OTPC_RLC_RELOAD_SHADOWS_SHIFT)) & OTPC_RLC_RELOAD_SHADOWS_MASK)
53310 /*! @} */
53311 
53312 /*! @name PCR - Power Control */
53313 /*! @{ */
53314 
53315 #define OTPC_PCR_HVREQ_MASK                      (0x1U)
53316 #define OTPC_PCR_HVREQ_SHIFT                     (0U)
53317 /*! HVREQ - Strong switch request
53318  *  0b0..Turn off
53319  *  0b1..Turn on
53320  */
53321 #define OTPC_PCR_HVREQ(x)                        (((uint32_t)(((uint32_t)(x)) << OTPC_PCR_HVREQ_SHIFT)) & OTPC_PCR_HVREQ_MASK)
53322 
53323 #define OTPC_PCR_LVREQ_MASK                      (0x2U)
53324 #define OTPC_PCR_LVREQ_SHIFT                     (1U)
53325 /*! LVREQ - Weak switch request
53326  *  0b0..Turn off
53327  *  0b1..Turn on
53328  */
53329 #define OTPC_PCR_LVREQ(x)                        (((uint32_t)(((uint32_t)(x)) << OTPC_PCR_LVREQ_SHIFT)) & OTPC_PCR_LVREQ_MASK)
53330 
53331 #define OTPC_PCR_PDREQ_MASK                      (0x4U)
53332 #define OTPC_PCR_PDREQ_SHIFT                     (2U)
53333 /*! PDREQ - Power down request
53334  *  0b0..PD pin is set to low when OTPC is in idle state. It means EFUSE hardmacro is in standby mode. Idle state
53335  *       means OTPC is not in read and program modes.
53336  *  0b1..PD pin is set to high when OTPC is in idle state. It means EFUSE hardmacro is in power down mode.
53337  */
53338 #define OTPC_PCR_PDREQ(x)                        (((uint32_t)(((uint32_t)(x)) << OTPC_PCR_PDREQ_SHIFT)) & OTPC_PCR_PDREQ_MASK)
53339 /*! @} */
53340 
53341 /*! @name WDATA - Write Data */
53342 /*! @{ */
53343 
53344 #define OTPC_WDATA_DAT_MASK                      (0xFFFFFFFFU)
53345 #define OTPC_WDATA_DAT_SHIFT                     (0U)
53346 /*! DAT - Write data */
53347 #define OTPC_WDATA_DAT(x)                        (((uint32_t)(((uint32_t)(x)) << OTPC_WDATA_DAT_SHIFT)) & OTPC_WDATA_DAT_MASK)
53348 /*! @} */
53349 
53350 /*! @name RDATA - Read Data */
53351 /*! @{ */
53352 
53353 #define OTPC_RDATA_DAT_MASK                      (0xFFFFFFFFU)
53354 #define OTPC_RDATA_DAT_SHIFT                     (0U)
53355 /*! DAT - Read data */
53356 #define OTPC_RDATA_DAT(x)                        (((uint32_t)(((uint32_t)(x)) << OTPC_RDATA_DAT_SHIFT)) & OTPC_RDATA_DAT_MASK)
53357 /*! @} */
53358 
53359 /*! @name TIMING1 - Timing1 */
53360 /*! @{ */
53361 
53362 #define OTPC_TIMING1_TADDR_MASK                  (0xFU)
53363 #define OTPC_TIMING1_TADDR_SHIFT                 (0U)
53364 /*! TADDR - Address to STROBE setup and hold time */
53365 #define OTPC_TIMING1_TADDR(x)                    (((uint32_t)(((uint32_t)(x)) << OTPC_TIMING1_TADDR_SHIFT)) & OTPC_TIMING1_TADDR_MASK)
53366 
53367 #define OTPC_TIMING1_TRELAX_MASK                 (0xF0U)
53368 #define OTPC_TIMING1_TRELAX_SHIFT                (4U)
53369 /*! TRELAX - CSB, PGENB and LOAD to STROBE setup and hold time */
53370 #define OTPC_TIMING1_TRELAX(x)                   (((uint32_t)(((uint32_t)(x)) << OTPC_TIMING1_TRELAX_SHIFT)) & OTPC_TIMING1_TRELAX_MASK)
53371 
53372 #define OTPC_TIMING1_TRD_MASK                    (0x3F00U)
53373 #define OTPC_TIMING1_TRD_SHIFT                   (8U)
53374 /*! TRD - Read strobe pulse width time */
53375 #define OTPC_TIMING1_TRD(x)                      (((uint32_t)(((uint32_t)(x)) << OTPC_TIMING1_TRD_SHIFT)) & OTPC_TIMING1_TRD_MASK)
53376 
53377 #define OTPC_TIMING1_TPS_MASK                    (0x3F0000U)
53378 #define OTPC_TIMING1_TPS_SHIFT                   (16U)
53379 /*! TPS - PS to CSB setup and hold time between power switch and chip select assertion */
53380 #define OTPC_TIMING1_TPS(x)                      (((uint32_t)(((uint32_t)(x)) << OTPC_TIMING1_TPS_SHIFT)) & OTPC_TIMING1_TPS_MASK)
53381 
53382 #define OTPC_TIMING1_TPD_MASK                    (0xFF000000U)
53383 #define OTPC_TIMING1_TPD_SHIFT                   (24U)
53384 /*! TPD - PD to CSB setup time between power down signal deassertion and chip select signal assertion */
53385 #define OTPC_TIMING1_TPD(x)                      (((uint32_t)(((uint32_t)(x)) << OTPC_TIMING1_TPD_SHIFT)) & OTPC_TIMING1_TPD_MASK)
53386 /*! @} */
53387 
53388 /*! @name TIMING2 - Timing2 */
53389 /*! @{ */
53390 
53391 #define OTPC_TIMING2_TPGM_MASK                   (0xFFFU)
53392 #define OTPC_TIMING2_TPGM_SHIFT                  (0U)
53393 /*! TPGM - Typical program strobe pulse width time */
53394 #define OTPC_TIMING2_TPGM(x)                     (((uint32_t)(((uint32_t)(x)) << OTPC_TIMING2_TPGM_SHIFT)) & OTPC_TIMING2_TPGM_MASK)
53395 /*! @} */
53396 
53397 /*! @name LOCK - Lock */
53398 /*! @{ */
53399 
53400 #define OTPC_LOCK_NXP_PART_CFG_LOCK_MASK         (0x7U)
53401 #define OTPC_LOCK_NXP_PART_CFG_LOCK_SHIFT        (0U)
53402 /*! NXP_PART_CFG_LOCK - NXP Part Config Lock */
53403 #define OTPC_LOCK_NXP_PART_CFG_LOCK(x)           (((uint32_t)(((uint32_t)(x)) << OTPC_LOCK_NXP_PART_CFG_LOCK_SHIFT)) & OTPC_LOCK_NXP_PART_CFG_LOCK_MASK)
53404 
53405 #define OTPC_LOCK_NXP_EXT_LOCK_MASK              (0x38U)
53406 #define OTPC_LOCK_NXP_EXT_LOCK_SHIFT             (3U)
53407 /*! NXP_EXT_LOCK - NXP EXT Lock */
53408 #define OTPC_LOCK_NXP_EXT_LOCK(x)                (((uint32_t)(((uint32_t)(x)) << OTPC_LOCK_NXP_EXT_LOCK_SHIFT)) & OTPC_LOCK_NXP_EXT_LOCK_MASK)
53409 
53410 #define OTPC_LOCK_BOOT_CFG_LOCK_MASK             (0xE00U)
53411 #define OTPC_LOCK_BOOT_CFG_LOCK_SHIFT            (9U)
53412 /*! BOOT_CFG_LOCK - Boot config Lock */
53413 #define OTPC_LOCK_BOOT_CFG_LOCK(x)               (((uint32_t)(((uint32_t)(x)) << OTPC_LOCK_BOOT_CFG_LOCK_SHIFT)) & OTPC_LOCK_BOOT_CFG_LOCK_MASK)
53414 
53415 #define OTPC_LOCK_PRINCE_CFG_LOCK_MASK           (0x7000U)
53416 #define OTPC_LOCK_PRINCE_CFG_LOCK_SHIFT          (12U)
53417 /*! PRINCE_CFG_LOCK - Prince Config Lock */
53418 #define OTPC_LOCK_PRINCE_CFG_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << OTPC_LOCK_PRINCE_CFG_LOCK_SHIFT)) & OTPC_LOCK_PRINCE_CFG_LOCK_MASK)
53419 
53420 #define OTPC_LOCK_OSCAA_KEY_LOCK_MASK            (0x38000U)
53421 #define OTPC_LOCK_OSCAA_KEY_LOCK_SHIFT           (15U)
53422 /*! OSCAA_KEY_LOCK - OSCAA Key Lock */
53423 #define OTPC_LOCK_OSCAA_KEY_LOCK(x)              (((uint32_t)(((uint32_t)(x)) << OTPC_LOCK_OSCAA_KEY_LOCK_SHIFT)) & OTPC_LOCK_OSCAA_KEY_LOCK_MASK)
53424 
53425 #define OTPC_LOCK_CUST_LOCK0_MASK                (0x1C0000U)
53426 #define OTPC_LOCK_CUST_LOCK0_SHIFT               (18U)
53427 /*! CUST_LOCK0 - CUST Lock 0 */
53428 #define OTPC_LOCK_CUST_LOCK0(x)                  (((uint32_t)(((uint32_t)(x)) << OTPC_LOCK_CUST_LOCK0_SHIFT)) & OTPC_LOCK_CUST_LOCK0_MASK)
53429 
53430 #define OTPC_LOCK_CUST_LOCK1_MASK                (0xE00000U)
53431 #define OTPC_LOCK_CUST_LOCK1_SHIFT               (21U)
53432 /*! CUST_LOCK1 - CUST Lock 1 */
53433 #define OTPC_LOCK_CUST_LOCK1(x)                  (((uint32_t)(((uint32_t)(x)) << OTPC_LOCK_CUST_LOCK1_SHIFT)) & OTPC_LOCK_CUST_LOCK1_MASK)
53434 
53435 #define OTPC_LOCK_CUST_LOCK2_MASK                (0x7000000U)
53436 #define OTPC_LOCK_CUST_LOCK2_SHIFT               (24U)
53437 /*! CUST_LOCK2 - CUST Lock 2 */
53438 #define OTPC_LOCK_CUST_LOCK2(x)                  (((uint32_t)(((uint32_t)(x)) << OTPC_LOCK_CUST_LOCK2_SHIFT)) & OTPC_LOCK_CUST_LOCK2_MASK)
53439 
53440 #define OTPC_LOCK_CUST_LOCK3_MASK                (0x38000000U)
53441 #define OTPC_LOCK_CUST_LOCK3_SHIFT               (27U)
53442 /*! CUST_LOCK3 - CUST Lock 3 */
53443 #define OTPC_LOCK_CUST_LOCK3(x)                  (((uint32_t)(((uint32_t)(x)) << OTPC_LOCK_CUST_LOCK3_SHIFT)) & OTPC_LOCK_CUST_LOCK3_MASK)
53444 /*! @} */
53445 
53446 /*! @name SECURE - Secure */
53447 /*! @{ */
53448 
53449 #define OTPC_SECURE_DAT_MASK                     (0xFFFFFFFFU)
53450 #define OTPC_SECURE_DAT_SHIFT                    (0U)
53451 /*! DAT - Data */
53452 #define OTPC_SECURE_DAT(x)                       (((uint32_t)(((uint32_t)(x)) << OTPC_SECURE_DAT_SHIFT)) & OTPC_SECURE_DAT_MASK)
53453 /*! @} */
53454 
53455 /*! @name SECURE_INV - Inverted Secure */
53456 /*! @{ */
53457 
53458 #define OTPC_SECURE_INV_DAT_MASK                 (0xFFFFFFFFU)
53459 #define OTPC_SECURE_INV_DAT_SHIFT                (0U)
53460 /*! DAT - Data */
53461 #define OTPC_SECURE_INV_DAT(x)                   (((uint32_t)(((uint32_t)(x)) << OTPC_SECURE_INV_DAT_SHIFT)) & OTPC_SECURE_INV_DAT_MASK)
53462 /*! @} */
53463 
53464 /*! @name DBG_KEY - Debug and Key */
53465 /*! @{ */
53466 
53467 #define OTPC_DBG_KEY_DAT_MASK                    (0xFFFFFFFFU)
53468 #define OTPC_DBG_KEY_DAT_SHIFT                   (0U)
53469 /*! DAT - Data */
53470 #define OTPC_DBG_KEY_DAT(x)                      (((uint32_t)(((uint32_t)(x)) << OTPC_DBG_KEY_DAT_SHIFT)) & OTPC_DBG_KEY_DAT_MASK)
53471 /*! @} */
53472 
53473 /*! @name MISC_CFG - MISC Config */
53474 /*! @{ */
53475 
53476 #define OTPC_MISC_CFG_DAT_MASK                   (0xFFFFFFFFU)
53477 #define OTPC_MISC_CFG_DAT_SHIFT                  (0U)
53478 /*! DAT - Data */
53479 #define OTPC_MISC_CFG_DAT(x)                     (((uint32_t)(((uint32_t)(x)) << OTPC_MISC_CFG_DAT_SHIFT)) & OTPC_MISC_CFG_DAT_MASK)
53480 /*! @} */
53481 
53482 /*! @name PHANTOM_CFG - PHANTOM Config */
53483 /*! @{ */
53484 
53485 #define OTPC_PHANTOM_CFG_DAT_MASK                (0xFFFFFFFFU)
53486 #define OTPC_PHANTOM_CFG_DAT_SHIFT               (0U)
53487 /*! DAT - Data */
53488 #define OTPC_PHANTOM_CFG_DAT(x)                  (((uint32_t)(((uint32_t)(x)) << OTPC_PHANTOM_CFG_DAT_SHIFT)) & OTPC_PHANTOM_CFG_DAT_MASK)
53489 /*! @} */
53490 
53491 /*! @name FLEX_CFG0 - Flexible Config 0 */
53492 /*! @{ */
53493 
53494 #define OTPC_FLEX_CFG0_DAT_MASK                  (0xFFFFFFFFU)
53495 #define OTPC_FLEX_CFG0_DAT_SHIFT                 (0U)
53496 /*! DAT - Data */
53497 #define OTPC_FLEX_CFG0_DAT(x)                    (((uint32_t)(((uint32_t)(x)) << OTPC_FLEX_CFG0_DAT_SHIFT)) & OTPC_FLEX_CFG0_DAT_MASK)
53498 /*! @} */
53499 
53500 /*! @name FLEX_CFG1 - Flexible Config 1 */
53501 /*! @{ */
53502 
53503 #define OTPC_FLEX_CFG1_DAT_MASK                  (0xFFFFFFFFU)
53504 #define OTPC_FLEX_CFG1_DAT_SHIFT                 (0U)
53505 /*! DAT - Data */
53506 #define OTPC_FLEX_CFG1_DAT(x)                    (((uint32_t)(((uint32_t)(x)) << OTPC_FLEX_CFG1_DAT_SHIFT)) & OTPC_FLEX_CFG1_DAT_MASK)
53507 /*! @} */
53508 
53509 
53510 /*!
53511  * @}
53512  */ /* end of group OTPC_Register_Masks */
53513 
53514 
53515 /* OTPC - Peripheral instance base addresses */
53516 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
53517   /** Peripheral OTPC0 base address */
53518   #define OTPC0_BASE                               (0x500C9000u)
53519   /** Peripheral OTPC0 base address */
53520   #define OTPC0_BASE_NS                            (0x400C9000u)
53521   /** Peripheral OTPC0 base pointer */
53522   #define OTPC0                                    ((OTPC_Type *)OTPC0_BASE)
53523   /** Peripheral OTPC0 base pointer */
53524   #define OTPC0_NS                                 ((OTPC_Type *)OTPC0_BASE_NS)
53525   /** Array initializer of OTPC peripheral base addresses */
53526   #define OTPC_BASE_ADDRS                          { OTPC0_BASE }
53527   /** Array initializer of OTPC peripheral base pointers */
53528   #define OTPC_BASE_PTRS                           { OTPC0 }
53529   /** Array initializer of OTPC peripheral base addresses */
53530   #define OTPC_BASE_ADDRS_NS                       { OTPC0_BASE_NS }
53531   /** Array initializer of OTPC peripheral base pointers */
53532   #define OTPC_BASE_PTRS_NS                        { OTPC0_NS }
53533 #else
53534   /** Peripheral OTPC0 base address */
53535   #define OTPC0_BASE                               (0x400C9000u)
53536   /** Peripheral OTPC0 base pointer */
53537   #define OTPC0                                    ((OTPC_Type *)OTPC0_BASE)
53538   /** Array initializer of OTPC peripheral base addresses */
53539   #define OTPC_BASE_ADDRS                          { OTPC0_BASE }
53540   /** Array initializer of OTPC peripheral base pointers */
53541   #define OTPC_BASE_PTRS                           { OTPC0 }
53542 #endif
53543 
53544 /*!
53545  * @}
53546  */ /* end of group OTPC_Peripheral_Access_Layer */
53547 
53548 
53549 /* ----------------------------------------------------------------------------
53550    -- PDM Peripheral Access Layer
53551    ---------------------------------------------------------------------------- */
53552 
53553 /*!
53554  * @addtogroup PDM_Peripheral_Access_Layer PDM Peripheral Access Layer
53555  * @{
53556  */
53557 
53558 /** PDM - Register Layout Typedef */
53559 typedef struct {
53560   __IO uint32_t CTRL_1;                            /**< MICFIL Control 1, offset: 0x0 */
53561   __IO uint32_t CTRL_2;                            /**< MICFIL Control 2, offset: 0x4 */
53562   __IO uint32_t STAT;                              /**< MICFIL Status, offset: 0x8 */
53563        uint8_t RESERVED_0[4];
53564   __IO uint32_t FIFO_CTRL;                         /**< MICFIL FIFO Control, offset: 0x10 */
53565   __IO uint32_t FIFO_STAT;                         /**< MICFIL FIFO Status, offset: 0x14 */
53566        uint8_t RESERVED_1[12];
53567   __I  uint32_t DATACH[4];                         /**< MICFIL Output Result, array offset: 0x24, array step: 0x4 */
53568        uint8_t RESERVED_2[48];
53569   __I  uint32_t DC_CTRL;                           /**< MICFIL DC Remover Control, offset: 0x64 */
53570   __IO uint32_t DC_OUT_CTRL;                       /**< MICFIL Output DC Remover Control, offset: 0x68 */
53571        uint8_t RESERVED_3[8];
53572   __IO uint32_t RANGE_CTRL;                        /**< MICFIL Range Control, offset: 0x74 */
53573        uint8_t RESERVED_4[4];
53574   __IO uint32_t RANGE_STAT;                        /**< MICFIL Range Status, offset: 0x7C */
53575   __IO uint32_t FSYNC_CTRL;                        /**< Frame Synchronization Control, offset: 0x80 */
53576   __I  uint32_t VERID;                             /**< Version ID, offset: 0x84 */
53577   __I  uint32_t PARAM;                             /**< Parameter, offset: 0x88 */
53578 } PDM_Type;
53579 
53580 /* ----------------------------------------------------------------------------
53581    -- PDM Register Masks
53582    ---------------------------------------------------------------------------- */
53583 
53584 /*!
53585  * @addtogroup PDM_Register_Masks PDM Register Masks
53586  * @{
53587  */
53588 
53589 /*! @name CTRL_1 - MICFIL Control 1 */
53590 /*! @{ */
53591 
53592 #define PDM_CTRL_1_CH0EN_MASK                    (0x1U)
53593 #define PDM_CTRL_1_CH0EN_SHIFT                   (0U)
53594 /*! CH0EN - Channel 0 Enable */
53595 #define PDM_CTRL_1_CH0EN(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH0EN_SHIFT)) & PDM_CTRL_1_CH0EN_MASK)
53596 
53597 #define PDM_CTRL_1_CH1EN_MASK                    (0x2U)
53598 #define PDM_CTRL_1_CH1EN_SHIFT                   (1U)
53599 /*! CH1EN - Channel 1 Enable */
53600 #define PDM_CTRL_1_CH1EN(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH1EN_SHIFT)) & PDM_CTRL_1_CH1EN_MASK)
53601 
53602 #define PDM_CTRL_1_CH2EN_MASK                    (0x4U)
53603 #define PDM_CTRL_1_CH2EN_SHIFT                   (2U)
53604 /*! CH2EN - Channel 2 Enable */
53605 #define PDM_CTRL_1_CH2EN(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH2EN_SHIFT)) & PDM_CTRL_1_CH2EN_MASK)
53606 
53607 #define PDM_CTRL_1_CH3EN_MASK                    (0x8U)
53608 #define PDM_CTRL_1_CH3EN_SHIFT                   (3U)
53609 /*! CH3EN - Channel 3 Enable */
53610 #define PDM_CTRL_1_CH3EN(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH3EN_SHIFT)) & PDM_CTRL_1_CH3EN_MASK)
53611 
53612 #define PDM_CTRL_1_FSYNCEN_MASK                  (0x10000U)
53613 #define PDM_CTRL_1_FSYNCEN_SHIFT                 (16U)
53614 /*! FSYNCEN - Frame Synchronization Enable
53615  *  0b0..Disables
53616  *  0b1..Enables
53617  */
53618 #define PDM_CTRL_1_FSYNCEN(x)                    (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_FSYNCEN_SHIFT)) & PDM_CTRL_1_FSYNCEN_MASK)
53619 
53620 #define PDM_CTRL_1_DECFILS_MASK                  (0x100000U)
53621 #define PDM_CTRL_1_DECFILS_SHIFT                 (20U)
53622 /*! DECFILS - Decimation Filter Enable in Stop
53623  *  0b0..Stops decimation filter
53624  *  0b1..Keeps decimation filter running
53625  */
53626 #define PDM_CTRL_1_DECFILS(x)                    (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DECFILS_SHIFT)) & PDM_CTRL_1_DECFILS_MASK)
53627 
53628 #define PDM_CTRL_1_ERREN_MASK                    (0x800000U)
53629 #define PDM_CTRL_1_ERREN_SHIFT                   (23U)
53630 /*! ERREN - Error Interruption Enable
53631  *  0b0..Disables
53632  *  0b1..Enables
53633  */
53634 #define PDM_CTRL_1_ERREN(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_ERREN_SHIFT)) & PDM_CTRL_1_ERREN_MASK)
53635 
53636 #define PDM_CTRL_1_DISEL_MASK                    (0x3000000U)
53637 #define PDM_CTRL_1_DISEL_SHIFT                   (24U)
53638 /*! DISEL - DMA Interrupt Selection
53639  *  0b00..Disables DMA and interrupt requests
53640  *  0b01..Enables DMA requests
53641  *  0b10..Enables interrupt requests
53642  *  0b11..Reserved
53643  */
53644 #define PDM_CTRL_1_DISEL(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DISEL_SHIFT)) & PDM_CTRL_1_DISEL_MASK)
53645 
53646 #define PDM_CTRL_1_DBGE_MASK                     (0x4000000U)
53647 #define PDM_CTRL_1_DBGE_SHIFT                    (26U)
53648 /*! DBGE - Module Enable in Debug
53649  *  0b0..Disables after completing the current frame
53650  *  0b1..Enables operation
53651  */
53652 #define PDM_CTRL_1_DBGE(x)                       (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DBGE_SHIFT)) & PDM_CTRL_1_DBGE_MASK)
53653 
53654 #define PDM_CTRL_1_SRES_MASK                     (0x8000000U)
53655 #define PDM_CTRL_1_SRES_SHIFT                    (27U)
53656 /*! SRES - Software Reset
53657  *  0b0..No action
53658  *  0b1..Software reset
53659  */
53660 #define PDM_CTRL_1_SRES(x)                       (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_SRES_SHIFT)) & PDM_CTRL_1_SRES_MASK)
53661 
53662 #define PDM_CTRL_1_DBG_MASK                      (0x10000000U)
53663 #define PDM_CTRL_1_DBG_SHIFT                     (28U)
53664 /*! DBG - Debug Mode
53665  *  0b0..Normal
53666  *  0b1..Debug
53667  */
53668 #define PDM_CTRL_1_DBG(x)                        (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DBG_SHIFT)) & PDM_CTRL_1_DBG_MASK)
53669 
53670 #define PDM_CTRL_1_PDMIEN_MASK                   (0x20000000U)
53671 #define PDM_CTRL_1_PDMIEN_SHIFT                  (29U)
53672 /*! PDMIEN - MICFIL Enable
53673  *  0b0..Stops MICFIL operation
53674  *  0b1..Starts MICFIL operation
53675  */
53676 #define PDM_CTRL_1_PDMIEN(x)                     (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_PDMIEN_SHIFT)) & PDM_CTRL_1_PDMIEN_MASK)
53677 
53678 #define PDM_CTRL_1_DOZEN_MASK                    (0x40000000U)
53679 #define PDM_CTRL_1_DOZEN_SHIFT                   (30U)
53680 /*! DOZEN - Stop Enable
53681  *  0b0..Disables
53682  *  0b1..Enables
53683  */
53684 #define PDM_CTRL_1_DOZEN(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DOZEN_SHIFT)) & PDM_CTRL_1_DOZEN_MASK)
53685 
53686 #define PDM_CTRL_1_MDIS_MASK                     (0x80000000U)
53687 #define PDM_CTRL_1_MDIS_SHIFT                    (31U)
53688 /*! MDIS - Module Disable
53689  *  0b0..Normal mode
53690  *  0b1..DLL mode
53691  */
53692 #define PDM_CTRL_1_MDIS(x)                       (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_MDIS_SHIFT)) & PDM_CTRL_1_MDIS_MASK)
53693 /*! @} */
53694 
53695 /*! @name CTRL_2 - MICFIL Control 2 */
53696 /*! @{ */
53697 
53698 #define PDM_CTRL_2_CLKDIV_MASK                   (0xFFU)
53699 #define PDM_CTRL_2_CLKDIV_SHIFT                  (0U)
53700 /*! CLKDIV - Clock Divider
53701  *  0b00000000..Internal clock divider value = 0
53702  *  0b00000001..Internal clock divider value = 1
53703  *  0b00000010-0b11111110.....
53704  *  0b11111111..Internal clock divider value = 255
53705  */
53706 #define PDM_CTRL_2_CLKDIV(x)                     (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_CLKDIV_SHIFT)) & PDM_CTRL_2_CLKDIV_MASK)
53707 
53708 #define PDM_CTRL_2_CLKDIVDIS_MASK                (0x8000U)
53709 #define PDM_CTRL_2_CLKDIVDIS_SHIFT               (15U)
53710 /*! CLKDIVDIS - Clock Divider Disable
53711  *  0b0..Enables
53712  *  0b1..Disables
53713  */
53714 #define PDM_CTRL_2_CLKDIVDIS(x)                  (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_CLKDIVDIS_SHIFT)) & PDM_CTRL_2_CLKDIVDIS_MASK)
53715 
53716 #define PDM_CTRL_2_CICOSR_MASK                   (0xF0000U)
53717 #define PDM_CTRL_2_CICOSR_SHIFT                  (16U)
53718 /*! CICOSR - CIC Decimation Rate
53719  *  0b0000..CIC oversampling rate = 0
53720  *  0b0001..CIC oversampling rate = 1
53721  *  0b0010-0b1110.....
53722  *  0b1111..CIC oversampling rate = 15
53723  */
53724 #define PDM_CTRL_2_CICOSR(x)                     (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_CICOSR_SHIFT)) & PDM_CTRL_2_CICOSR_MASK)
53725 
53726 #define PDM_CTRL_2_QSEL_MASK                     (0xE000000U)
53727 #define PDM_CTRL_2_QSEL_SHIFT                    (25U)
53728 /*! QSEL - Quality Mode
53729  *  0b001..High-Quality mode
53730  *  0b000..Medium-Quality mode
53731  *  0b111..Low-Quality mode
53732  *  0b110..Very-Low-Quality 0 mode
53733  *  0b101..Very-Low-Quality 1 mode
53734  *  0b100..Very-Low-Quality 2 mode
53735  */
53736 #define PDM_CTRL_2_QSEL(x)                       (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_QSEL_SHIFT)) & PDM_CTRL_2_QSEL_MASK)
53737 /*! @} */
53738 
53739 /*! @name STAT - MICFIL Status */
53740 /*! @{ */
53741 
53742 #define PDM_STAT_CH0F_MASK                       (0x1U)
53743 #define PDM_STAT_CH0F_SHIFT                      (0U)
53744 /*! CH0F - Channel 0 Output Data Flag
53745  *  0b0..Not surpassed
53746  *  0b1..Surpassed
53747  */
53748 #define PDM_STAT_CH0F(x)                         (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH0F_SHIFT)) & PDM_STAT_CH0F_MASK)
53749 
53750 #define PDM_STAT_CH1F_MASK                       (0x2U)
53751 #define PDM_STAT_CH1F_SHIFT                      (1U)
53752 /*! CH1F - Channel 1 Output Data Flag
53753  *  0b0..Not surpassed
53754  *  0b1..Surpassed
53755  */
53756 #define PDM_STAT_CH1F(x)                         (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH1F_SHIFT)) & PDM_STAT_CH1F_MASK)
53757 
53758 #define PDM_STAT_CH2F_MASK                       (0x4U)
53759 #define PDM_STAT_CH2F_SHIFT                      (2U)
53760 /*! CH2F - Channel 2 Output Data Flag
53761  *  0b0..Not surpassed
53762  *  0b1..Surpassed
53763  */
53764 #define PDM_STAT_CH2F(x)                         (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH2F_SHIFT)) & PDM_STAT_CH2F_MASK)
53765 
53766 #define PDM_STAT_CH3F_MASK                       (0x8U)
53767 #define PDM_STAT_CH3F_SHIFT                      (3U)
53768 /*! CH3F - Channel 3 Output Data Flag
53769  *  0b0..Not surpassed
53770  *  0b1..Surpassed
53771  */
53772 #define PDM_STAT_CH3F(x)                         (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH3F_SHIFT)) & PDM_STAT_CH3F_MASK)
53773 
53774 #define PDM_STAT_BSY_FIL_MASK                    (0x80000000U)
53775 #define PDM_STAT_BSY_FIL_SHIFT                   (31U)
53776 /*! BSY_FIL - Busy Flag
53777  *  0b1..MICFIL is running
53778  *  0b0..MICFIL is stopped
53779  */
53780 #define PDM_STAT_BSY_FIL(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_STAT_BSY_FIL_SHIFT)) & PDM_STAT_BSY_FIL_MASK)
53781 /*! @} */
53782 
53783 /*! @name FIFO_CTRL - MICFIL FIFO Control */
53784 /*! @{ */
53785 
53786 #define PDM_FIFO_CTRL_FIFOWMK_MASK               (0xFU)
53787 #define PDM_FIFO_CTRL_FIFOWMK_SHIFT              (0U)
53788 /*! FIFOWMK - FIFO Watermark Control */
53789 #define PDM_FIFO_CTRL_FIFOWMK(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_CTRL_FIFOWMK_SHIFT)) & PDM_FIFO_CTRL_FIFOWMK_MASK)
53790 /*! @} */
53791 
53792 /*! @name FIFO_STAT - MICFIL FIFO Status */
53793 /*! @{ */
53794 
53795 #define PDM_FIFO_STAT_FIFOOVF0_MASK              (0x1U)
53796 #define PDM_FIFO_STAT_FIFOOVF0_SHIFT             (0U)
53797 /*! FIFOOVF0 - FIFO Overflow Exception Flag for Channel 0
53798  *  0b0..No exception by FIFO overflow
53799  *  0b1..Exception by FIFO overflow
53800  */
53801 #define PDM_FIFO_STAT_FIFOOVF0(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF0_SHIFT)) & PDM_FIFO_STAT_FIFOOVF0_MASK)
53802 
53803 #define PDM_FIFO_STAT_FIFOOVF1_MASK              (0x2U)
53804 #define PDM_FIFO_STAT_FIFOOVF1_SHIFT             (1U)
53805 /*! FIFOOVF1 - FIFO Overflow Exception Flag for Channel 1
53806  *  0b0..No exception by FIFO overflow
53807  *  0b1..Exception by FIFO overflow
53808  */
53809 #define PDM_FIFO_STAT_FIFOOVF1(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF1_SHIFT)) & PDM_FIFO_STAT_FIFOOVF1_MASK)
53810 
53811 #define PDM_FIFO_STAT_FIFOOVF2_MASK              (0x4U)
53812 #define PDM_FIFO_STAT_FIFOOVF2_SHIFT             (2U)
53813 /*! FIFOOVF2 - FIFO Overflow Exception Flag for Channel 2
53814  *  0b0..No exception by FIFO overflow
53815  *  0b1..Exception by FIFO overflow
53816  */
53817 #define PDM_FIFO_STAT_FIFOOVF2(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF2_SHIFT)) & PDM_FIFO_STAT_FIFOOVF2_MASK)
53818 
53819 #define PDM_FIFO_STAT_FIFOOVF3_MASK              (0x8U)
53820 #define PDM_FIFO_STAT_FIFOOVF3_SHIFT             (3U)
53821 /*! FIFOOVF3 - FIFO Overflow Exception Flag for Channel 3
53822  *  0b0..No exception by FIFO overflow
53823  *  0b1..Exception by FIFO overflow
53824  */
53825 #define PDM_FIFO_STAT_FIFOOVF3(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF3_SHIFT)) & PDM_FIFO_STAT_FIFOOVF3_MASK)
53826 
53827 #define PDM_FIFO_STAT_FIFOUND0_MASK              (0x100U)
53828 #define PDM_FIFO_STAT_FIFOUND0_SHIFT             (8U)
53829 /*! FIFOUND0 - FIFO Underflow Exception Flag for Channel 0
53830  *  0b0..No exception by FIFO underflow
53831  *  0b1..Exception by FIFO underflow
53832  */
53833 #define PDM_FIFO_STAT_FIFOUND0(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND0_SHIFT)) & PDM_FIFO_STAT_FIFOUND0_MASK)
53834 
53835 #define PDM_FIFO_STAT_FIFOUND1_MASK              (0x200U)
53836 #define PDM_FIFO_STAT_FIFOUND1_SHIFT             (9U)
53837 /*! FIFOUND1 - FIFO Underflow Exception Flag for Channel 1
53838  *  0b0..No exception by FIFO underflow
53839  *  0b1..Exception by FIFO underflow
53840  */
53841 #define PDM_FIFO_STAT_FIFOUND1(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND1_SHIFT)) & PDM_FIFO_STAT_FIFOUND1_MASK)
53842 
53843 #define PDM_FIFO_STAT_FIFOUND2_MASK              (0x400U)
53844 #define PDM_FIFO_STAT_FIFOUND2_SHIFT             (10U)
53845 /*! FIFOUND2 - FIFO Underflow Exception Flag for Channel 2
53846  *  0b0..No exception by FIFO underflow
53847  *  0b1..Exception by FIFO underflow
53848  */
53849 #define PDM_FIFO_STAT_FIFOUND2(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND2_SHIFT)) & PDM_FIFO_STAT_FIFOUND2_MASK)
53850 
53851 #define PDM_FIFO_STAT_FIFOUND3_MASK              (0x800U)
53852 #define PDM_FIFO_STAT_FIFOUND3_SHIFT             (11U)
53853 /*! FIFOUND3 - FIFO Underflow Exception Flag for Channel 3
53854  *  0b0..No exception by FIFO underflow
53855  *  0b1..Exception by FIFO underflow
53856  */
53857 #define PDM_FIFO_STAT_FIFOUND3(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND3_SHIFT)) & PDM_FIFO_STAT_FIFOUND3_MASK)
53858 /*! @} */
53859 
53860 /*! @name DATACHN_DATACH - MICFIL Output Result */
53861 /*! @{ */
53862 
53863 #define PDM_DATACHN_DATACH_DATA_MASK             (0xFFFFFFFFU)
53864 #define PDM_DATACHN_DATACH_DATA_SHIFT            (0U)
53865 /*! DATA - Channel n Data */
53866 #define PDM_DATACHN_DATACH_DATA(x)               (((uint32_t)(((uint32_t)(x)) << PDM_DATACHN_DATACH_DATA_SHIFT)) & PDM_DATACHN_DATACH_DATA_MASK)
53867 /*! @} */
53868 
53869 /* The count of PDM_DATACHN_DATACH */
53870 #define PDM_DATACHN_DATACH_COUNT                 (4U)
53871 
53872 /*! @name DC_CTRL - MICFIL DC Remover Control */
53873 /*! @{ */
53874 
53875 #define PDM_DC_CTRL_DCCONFIG0_MASK               (0x3U)
53876 #define PDM_DC_CTRL_DCCONFIG0_SHIFT              (0U)
53877 /*! DCCONFIG0 - Channel 0 DC Remover Configuration
53878  *  0b11..DC remover is bypassed
53879  *  0b00..20 Hz (PDM_CLK = 3.072 MHz)
53880  *  0b01..13.3 Hz (PDM_CLK = 3.072 MHz)
53881  *  0b10..40 Hz (PDM_CLK = 3.072 MHz)
53882  */
53883 #define PDM_DC_CTRL_DCCONFIG0(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG0_SHIFT)) & PDM_DC_CTRL_DCCONFIG0_MASK)
53884 
53885 #define PDM_DC_CTRL_DCCONFIG1_MASK               (0xCU)
53886 #define PDM_DC_CTRL_DCCONFIG1_SHIFT              (2U)
53887 /*! DCCONFIG1 - Channel 1 DC Remover Configuration
53888  *  0b11..DC remover is bypassed
53889  *  0b00..20 Hz (PDM_CLK = 3.072 MHz)
53890  *  0b01..13.3 Hz (PDM_CLK = 3.072 MHz)
53891  *  0b10..40 Hz (PDM_CLK = 3.072 MHz)
53892  */
53893 #define PDM_DC_CTRL_DCCONFIG1(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG1_SHIFT)) & PDM_DC_CTRL_DCCONFIG1_MASK)
53894 
53895 #define PDM_DC_CTRL_DCCONFIG2_MASK               (0x30U)
53896 #define PDM_DC_CTRL_DCCONFIG2_SHIFT              (4U)
53897 /*! DCCONFIG2 - Channel 2 DC Remover Configuration
53898  *  0b11..DC remover is bypassed
53899  *  0b00..20 Hz (PDM_CLK = 3.072 MHz)
53900  *  0b01..13.3 Hz (PDM_CLK = 3.072 MHz)
53901  *  0b10..40 Hz (PDM_CLK = 3.072 MHz)
53902  */
53903 #define PDM_DC_CTRL_DCCONFIG2(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG2_SHIFT)) & PDM_DC_CTRL_DCCONFIG2_MASK)
53904 
53905 #define PDM_DC_CTRL_DCCONFIG3_MASK               (0xC0U)
53906 #define PDM_DC_CTRL_DCCONFIG3_SHIFT              (6U)
53907 /*! DCCONFIG3 - Channel 3 DC Remover Configuration
53908  *  0b11..DC remover is bypassed
53909  *  0b00..20 Hz (PDM_CLK = 3.072 MHz)
53910  *  0b01..13.3 Hz (PDM_CLK = 3.072 MHz)
53911  *  0b10..40 Hz (PDM_CLK = 3.072 MHz)
53912  */
53913 #define PDM_DC_CTRL_DCCONFIG3(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG3_SHIFT)) & PDM_DC_CTRL_DCCONFIG3_MASK)
53914 /*! @} */
53915 
53916 /*! @name DC_OUT_CTRL - MICFIL Output DC Remover Control */
53917 /*! @{ */
53918 
53919 #define PDM_DC_OUT_CTRL_DCCONFIG0_MASK           (0x3U)
53920 #define PDM_DC_OUT_CTRL_DCCONFIG0_SHIFT          (0U)
53921 /*! DCCONFIG0 - Channel 0 DC Remover Configuration
53922  *  0b11..DC remover is bypassed
53923  *  0b00..20 Hz (FS = 48 kHz)
53924  *  0b01..13.3 Hz (FS = 48 kHz)
53925  *  0b10..40 Hz (FS = 48 kHz)
53926  */
53927 #define PDM_DC_OUT_CTRL_DCCONFIG0(x)             (((uint32_t)(((uint32_t)(x)) << PDM_DC_OUT_CTRL_DCCONFIG0_SHIFT)) & PDM_DC_OUT_CTRL_DCCONFIG0_MASK)
53928 
53929 #define PDM_DC_OUT_CTRL_DCCONFIG1_MASK           (0xCU)
53930 #define PDM_DC_OUT_CTRL_DCCONFIG1_SHIFT          (2U)
53931 /*! DCCONFIG1 - Channel 1 DC Remover Configuration
53932  *  0b11..DC remover is bypassed
53933  *  0b00..20 Hz (FS = 48 kHz)
53934  *  0b01..13.3 Hz (FS = 48 kHz)
53935  *  0b10..40 Hz (FS = 48 kHz)
53936  */
53937 #define PDM_DC_OUT_CTRL_DCCONFIG1(x)             (((uint32_t)(((uint32_t)(x)) << PDM_DC_OUT_CTRL_DCCONFIG1_SHIFT)) & PDM_DC_OUT_CTRL_DCCONFIG1_MASK)
53938 
53939 #define PDM_DC_OUT_CTRL_DCCONFIG2_MASK           (0x30U)
53940 #define PDM_DC_OUT_CTRL_DCCONFIG2_SHIFT          (4U)
53941 /*! DCCONFIG2 - Channel 2 DC Remover Configuration
53942  *  0b11..DC remover is bypassed
53943  *  0b00..20 Hz (FS = 48 kHz)
53944  *  0b01..13.3 Hz (FS = 48 kHz)
53945  *  0b10..40 Hz (FS = 48 kHz)
53946  */
53947 #define PDM_DC_OUT_CTRL_DCCONFIG2(x)             (((uint32_t)(((uint32_t)(x)) << PDM_DC_OUT_CTRL_DCCONFIG2_SHIFT)) & PDM_DC_OUT_CTRL_DCCONFIG2_MASK)
53948 
53949 #define PDM_DC_OUT_CTRL_DCCONFIG3_MASK           (0xC0U)
53950 #define PDM_DC_OUT_CTRL_DCCONFIG3_SHIFT          (6U)
53951 /*! DCCONFIG3 - Channel 3 DC Remover Configuration
53952  *  0b11..DC remover is bypassed
53953  *  0b00..20 Hz (FS = 48 kHz)
53954  *  0b01..13.3 Hz (FS = 48 kHz)
53955  *  0b10..40 Hz (FS = 48 kHz)
53956  */
53957 #define PDM_DC_OUT_CTRL_DCCONFIG3(x)             (((uint32_t)(((uint32_t)(x)) << PDM_DC_OUT_CTRL_DCCONFIG3_SHIFT)) & PDM_DC_OUT_CTRL_DCCONFIG3_MASK)
53958 /*! @} */
53959 
53960 /*! @name RANGE_CTRL - MICFIL Range Control */
53961 /*! @{ */
53962 
53963 #define PDM_RANGE_CTRL_RANGEADJ0_MASK            (0xFU)
53964 #define PDM_RANGE_CTRL_RANGEADJ0_SHIFT           (0U)
53965 /*! RANGEADJ0 - Channel 0 Range Adjustment */
53966 #define PDM_RANGE_CTRL_RANGEADJ0(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ0_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ0_MASK)
53967 
53968 #define PDM_RANGE_CTRL_RANGEADJ1_MASK            (0xF0U)
53969 #define PDM_RANGE_CTRL_RANGEADJ1_SHIFT           (4U)
53970 /*! RANGEADJ1 - Channel 1 Range Adjustment */
53971 #define PDM_RANGE_CTRL_RANGEADJ1(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ1_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ1_MASK)
53972 
53973 #define PDM_RANGE_CTRL_RANGEADJ2_MASK            (0xF00U)
53974 #define PDM_RANGE_CTRL_RANGEADJ2_SHIFT           (8U)
53975 /*! RANGEADJ2 - Channel 2 Range Adjustment */
53976 #define PDM_RANGE_CTRL_RANGEADJ2(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ2_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ2_MASK)
53977 
53978 #define PDM_RANGE_CTRL_RANGEADJ3_MASK            (0xF000U)
53979 #define PDM_RANGE_CTRL_RANGEADJ3_SHIFT           (12U)
53980 /*! RANGEADJ3 - Channel 3 Range Adjustment */
53981 #define PDM_RANGE_CTRL_RANGEADJ3(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ3_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ3_MASK)
53982 /*! @} */
53983 
53984 /*! @name RANGE_STAT - MICFIL Range Status */
53985 /*! @{ */
53986 
53987 #define PDM_RANGE_STAT_RANGEOVF0_MASK            (0x1U)
53988 #define PDM_RANGE_STAT_RANGEOVF0_SHIFT           (0U)
53989 /*! RANGEOVF0 - Channel 0 Range Overflow Error Flag
53990  *  0b0..No exception by range overflow
53991  *  0b1..Exception by range overflow
53992  */
53993 #define PDM_RANGE_STAT_RANGEOVF0(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF0_SHIFT)) & PDM_RANGE_STAT_RANGEOVF0_MASK)
53994 
53995 #define PDM_RANGE_STAT_RANGEOVF1_MASK            (0x2U)
53996 #define PDM_RANGE_STAT_RANGEOVF1_SHIFT           (1U)
53997 /*! RANGEOVF1 - Channel 1 Range Overflow Error Flag
53998  *  0b0..No exception by range overflow
53999  *  0b1..Exception by range overflow
54000  */
54001 #define PDM_RANGE_STAT_RANGEOVF1(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF1_SHIFT)) & PDM_RANGE_STAT_RANGEOVF1_MASK)
54002 
54003 #define PDM_RANGE_STAT_RANGEOVF2_MASK            (0x4U)
54004 #define PDM_RANGE_STAT_RANGEOVF2_SHIFT           (2U)
54005 /*! RANGEOVF2 - Channel 2 Range Overflow Error Flag
54006  *  0b0..No exception by range overflow
54007  *  0b1..Exception by range overflow
54008  */
54009 #define PDM_RANGE_STAT_RANGEOVF2(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF2_SHIFT)) & PDM_RANGE_STAT_RANGEOVF2_MASK)
54010 
54011 #define PDM_RANGE_STAT_RANGEOVF3_MASK            (0x8U)
54012 #define PDM_RANGE_STAT_RANGEOVF3_SHIFT           (3U)
54013 /*! RANGEOVF3 - Channel 3 Range Overflow Error Flag
54014  *  0b0..No exception by range overflow
54015  *  0b1..Exception by range overflow
54016  */
54017 #define PDM_RANGE_STAT_RANGEOVF3(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF3_SHIFT)) & PDM_RANGE_STAT_RANGEOVF3_MASK)
54018 
54019 #define PDM_RANGE_STAT_RANGEUNF0_MASK            (0x10000U)
54020 #define PDM_RANGE_STAT_RANGEUNF0_SHIFT           (16U)
54021 /*! RANGEUNF0 - Channel 0 Range Underflow Error Flag
54022  *  0b0..No exception by range underflow
54023  *  0b1..Exception by range underflow
54024  */
54025 #define PDM_RANGE_STAT_RANGEUNF0(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF0_SHIFT)) & PDM_RANGE_STAT_RANGEUNF0_MASK)
54026 
54027 #define PDM_RANGE_STAT_RANGEUNF1_MASK            (0x20000U)
54028 #define PDM_RANGE_STAT_RANGEUNF1_SHIFT           (17U)
54029 /*! RANGEUNF1 - Channel 1 Range Underflow Error Flag
54030  *  0b0..No exception by range underflow
54031  *  0b1..Exception by range underflow
54032  */
54033 #define PDM_RANGE_STAT_RANGEUNF1(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF1_SHIFT)) & PDM_RANGE_STAT_RANGEUNF1_MASK)
54034 
54035 #define PDM_RANGE_STAT_RANGEUNF2_MASK            (0x40000U)
54036 #define PDM_RANGE_STAT_RANGEUNF2_SHIFT           (18U)
54037 /*! RANGEUNF2 - Channel 2 Range Underflow Error Flag
54038  *  0b0..No exception by range underflow
54039  *  0b1..Exception by range underflow
54040  */
54041 #define PDM_RANGE_STAT_RANGEUNF2(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF2_SHIFT)) & PDM_RANGE_STAT_RANGEUNF2_MASK)
54042 
54043 #define PDM_RANGE_STAT_RANGEUNF3_MASK            (0x80000U)
54044 #define PDM_RANGE_STAT_RANGEUNF3_SHIFT           (19U)
54045 /*! RANGEUNF3 - Channel 3 Range Underflow Error Flag
54046  *  0b0..No exception by range underflow
54047  *  0b1..Exception by range underflow
54048  */
54049 #define PDM_RANGE_STAT_RANGEUNF3(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF3_SHIFT)) & PDM_RANGE_STAT_RANGEUNF3_MASK)
54050 /*! @} */
54051 
54052 /*! @name FSYNC_CTRL - Frame Synchronization Control */
54053 /*! @{ */
54054 
54055 #define PDM_FSYNC_CTRL_FSYNCLEN_MASK             (0xFFFFFFFFU)
54056 #define PDM_FSYNC_CTRL_FSYNCLEN_SHIFT            (0U)
54057 /*! FSYNCLEN - Frame Synchronization Window Length */
54058 #define PDM_FSYNC_CTRL_FSYNCLEN(x)               (((uint32_t)(((uint32_t)(x)) << PDM_FSYNC_CTRL_FSYNCLEN_SHIFT)) & PDM_FSYNC_CTRL_FSYNCLEN_MASK)
54059 /*! @} */
54060 
54061 /*! @name VERID - Version ID */
54062 /*! @{ */
54063 
54064 #define PDM_VERID_FEATURE_MASK                   (0xFFFFU)
54065 #define PDM_VERID_FEATURE_SHIFT                  (0U)
54066 /*! FEATURE - Feature Specification Number */
54067 #define PDM_VERID_FEATURE(x)                     (((uint32_t)(((uint32_t)(x)) << PDM_VERID_FEATURE_SHIFT)) & PDM_VERID_FEATURE_MASK)
54068 
54069 #define PDM_VERID_MINOR_MASK                     (0xFF0000U)
54070 #define PDM_VERID_MINOR_SHIFT                    (16U)
54071 /*! MINOR - Minor Version Number */
54072 #define PDM_VERID_MINOR(x)                       (((uint32_t)(((uint32_t)(x)) << PDM_VERID_MINOR_SHIFT)) & PDM_VERID_MINOR_MASK)
54073 
54074 #define PDM_VERID_MAJOR_MASK                     (0xFF000000U)
54075 #define PDM_VERID_MAJOR_SHIFT                    (24U)
54076 /*! MAJOR - Major Version Number */
54077 #define PDM_VERID_MAJOR(x)                       (((uint32_t)(((uint32_t)(x)) << PDM_VERID_MAJOR_SHIFT)) & PDM_VERID_MAJOR_MASK)
54078 /*! @} */
54079 
54080 /*! @name PARAM - Parameter */
54081 /*! @{ */
54082 
54083 #define PDM_PARAM_NPAIR_MASK                     (0xFU)
54084 #define PDM_PARAM_NPAIR_SHIFT                    (0U)
54085 /*! NPAIR - Number of Microphone Pairs
54086  *  0b0000..None
54087  *  0b0001..1 pair
54088  *  0b0010..2 pairs
54089  *  0b0011-0b1110.....
54090  *  0b1111..15 pairs
54091  */
54092 #define PDM_PARAM_NPAIR(x)                       (((uint32_t)(((uint32_t)(x)) << PDM_PARAM_NPAIR_SHIFT)) & PDM_PARAM_NPAIR_MASK)
54093 
54094 #define PDM_PARAM_FIFO_PTRWID_MASK               (0xF0U)
54095 #define PDM_PARAM_FIFO_PTRWID_SHIFT              (4U)
54096 /*! FIFO_PTRWID - FIFO Pointer Width
54097  *  0b0000..0 bits
54098  *  0b0001..1 bit
54099  *  0b0010..2 bits
54100  *  0b0011-0b1110.....
54101  *  0b1111..15 bits
54102  */
54103 #define PDM_PARAM_FIFO_PTRWID(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_PARAM_FIFO_PTRWID_SHIFT)) & PDM_PARAM_FIFO_PTRWID_MASK)
54104 
54105 #define PDM_PARAM_FIL_OUT_WIDTH_24B_MASK         (0x100U)
54106 #define PDM_PARAM_FIL_OUT_WIDTH_24B_SHIFT        (8U)
54107 /*! FIL_OUT_WIDTH_24B - Filter Output Width
54108  *  0b0..16 bits
54109  *  0b1..24 bits
54110  */
54111 #define PDM_PARAM_FIL_OUT_WIDTH_24B(x)           (((uint32_t)(((uint32_t)(x)) << PDM_PARAM_FIL_OUT_WIDTH_24B_SHIFT)) & PDM_PARAM_FIL_OUT_WIDTH_24B_MASK)
54112 
54113 #define PDM_PARAM_LOW_POWER_MASK                 (0x200U)
54114 #define PDM_PARAM_LOW_POWER_SHIFT                (9U)
54115 /*! LOW_POWER - Low-Power Decimation Filter
54116  *  0b0..Disables
54117  *  0b1..Enables
54118  */
54119 #define PDM_PARAM_LOW_POWER(x)                   (((uint32_t)(((uint32_t)(x)) << PDM_PARAM_LOW_POWER_SHIFT)) & PDM_PARAM_LOW_POWER_MASK)
54120 
54121 #define PDM_PARAM_DC_BYPASS_MASK                 (0x400U)
54122 #define PDM_PARAM_DC_BYPASS_SHIFT                (10U)
54123 /*! DC_BYPASS - Input DC Remover Bypass
54124  *  0b0..Active
54125  *  0b1..Disabled
54126  */
54127 #define PDM_PARAM_DC_BYPASS(x)                   (((uint32_t)(((uint32_t)(x)) << PDM_PARAM_DC_BYPASS_SHIFT)) & PDM_PARAM_DC_BYPASS_MASK)
54128 
54129 #define PDM_PARAM_DC_OUT_BYPASS_MASK             (0x800U)
54130 #define PDM_PARAM_DC_OUT_BYPASS_SHIFT            (11U)
54131 /*! DC_OUT_BYPASS - Output DC Remover Bypass
54132  *  0b0..Active
54133  *  0b1..Disabled
54134  */
54135 #define PDM_PARAM_DC_OUT_BYPASS(x)               (((uint32_t)(((uint32_t)(x)) << PDM_PARAM_DC_OUT_BYPASS_SHIFT)) & PDM_PARAM_DC_OUT_BYPASS_MASK)
54136 /*! @} */
54137 
54138 
54139 /*!
54140  * @}
54141  */ /* end of group PDM_Register_Masks */
54142 
54143 
54144 /* PDM - Peripheral instance base addresses */
54145 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
54146   /** Peripheral PDM base address */
54147   #define PDM_BASE                                 (0x5010C000u)
54148   /** Peripheral PDM base address */
54149   #define PDM_BASE_NS                              (0x4010C000u)
54150   /** Peripheral PDM base pointer */
54151   #define PDM                                      ((PDM_Type *)PDM_BASE)
54152   /** Peripheral PDM base pointer */
54153   #define PDM_NS                                   ((PDM_Type *)PDM_BASE_NS)
54154   /** Array initializer of PDM peripheral base addresses */
54155   #define PDM_BASE_ADDRS                           { PDM_BASE }
54156   /** Array initializer of PDM peripheral base pointers */
54157   #define PDM_BASE_PTRS                            { PDM }
54158   /** Array initializer of PDM peripheral base addresses */
54159   #define PDM_BASE_ADDRS_NS                        { PDM_BASE_NS }
54160   /** Array initializer of PDM peripheral base pointers */
54161   #define PDM_BASE_PTRS_NS                         { PDM_NS }
54162 #else
54163   /** Peripheral PDM base address */
54164   #define PDM_BASE                                 (0x4010C000u)
54165   /** Peripheral PDM base pointer */
54166   #define PDM                                      ((PDM_Type *)PDM_BASE)
54167   /** Array initializer of PDM peripheral base addresses */
54168   #define PDM_BASE_ADDRS                           { PDM_BASE }
54169   /** Array initializer of PDM peripheral base pointers */
54170   #define PDM_BASE_PTRS                            { PDM }
54171 #endif
54172 /** Interrupt vectors for the PDM peripheral type */
54173 #define PDM_IRQS                                 { PDM_EVENT_IRQn }
54174 
54175 /*!
54176  * @}
54177  */ /* end of group PDM_Peripheral_Access_Layer */
54178 
54179 
54180 /* ----------------------------------------------------------------------------
54181    -- PINT Peripheral Access Layer
54182    ---------------------------------------------------------------------------- */
54183 
54184 /*!
54185  * @addtogroup PINT_Peripheral_Access_Layer PINT Peripheral Access Layer
54186  * @{
54187  */
54188 
54189 /** PINT - Register Layout Typedef */
54190 typedef struct {
54191   __IO uint32_t ISEL;                              /**< Pin Interrupt Mode, offset: 0x0 */
54192   __IO uint32_t IENR;                              /**< Pin Interrupt Level or Rising-Edge Interrupt Enable, offset: 0x4 */
54193   __O  uint32_t SIENR;                             /**< Pin Interrupt Level or Rising-Edge Interrupt Set, offset: 0x8 */
54194   __IO uint32_t CIENR;                             /**< Pin Interrupt Level (Rising-Edge Interrupt) Clear, offset: 0xC */
54195   __IO uint32_t IENF;                              /**< Pin Interrupt Active Level or Falling-Edge Interrupt Enable, offset: 0x10 */
54196   __O  uint32_t SIENF;                             /**< Pin Interrupt Active Level or Falling-Edge Interrupt Set, offset: 0x14 */
54197   __O  uint32_t CIENF;                             /**< Pin Interrupt Active Level or Falling-Edge Interrupt Clear, offset: 0x18 */
54198   __IO uint32_t RISE;                              /**< Pin Interrupt Rising Edge, offset: 0x1C */
54199   __IO uint32_t FALL;                              /**< Pin Interrupt Falling Edge, offset: 0x20 */
54200   __IO uint32_t IST;                               /**< Pin Interrupt Status, offset: 0x24 */
54201   __IO uint32_t PMCTRL;                            /**< Pattern-Match Interrupt Control, offset: 0x28 */
54202   __IO uint32_t PMSRC;                             /**< Pattern-Match Interrupt Bit-Slice Source, offset: 0x2C */
54203   __IO uint32_t PMCFG;                             /**< Pattern-Match Interrupt Bit Slice Configuration, offset: 0x30 */
54204 } PINT_Type;
54205 
54206 /* ----------------------------------------------------------------------------
54207    -- PINT Register Masks
54208    ---------------------------------------------------------------------------- */
54209 
54210 /*!
54211  * @addtogroup PINT_Register_Masks PINT Register Masks
54212  * @{
54213  */
54214 
54215 /*! @name ISEL - Pin Interrupt Mode */
54216 /*! @{ */
54217 
54218 #define PINT_ISEL_PMODE_MASK                     (0xFFU)
54219 #define PINT_ISEL_PMODE_SHIFT                    (0U)
54220 /*! PMODE - Interrupt mode
54221  *  0b00000000..In bit n configures the interrupt to be edge-sensitive
54222  *  0b00000001..In bit n configures the interrupt to be level-sensitive
54223  */
54224 #define PINT_ISEL_PMODE(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_ISEL_PMODE_SHIFT)) & PINT_ISEL_PMODE_MASK)
54225 /*! @} */
54226 
54227 /*! @name IENR - Pin Interrupt Level or Rising-Edge Interrupt Enable */
54228 /*! @{ */
54229 
54230 #define PINT_IENR_ENRL_MASK                      (0xFFU)
54231 #define PINT_IENR_ENRL_SHIFT                     (0U)
54232 /*! ENRL - Enables Interrupt
54233  *  0b00000000..In bit n disables the corresponding interrupt
54234  *  0b00000001..In bit n enables the corresponding interrupt
54235  */
54236 #define PINT_IENR_ENRL(x)                        (((uint32_t)(((uint32_t)(x)) << PINT_IENR_ENRL_SHIFT)) & PINT_IENR_ENRL_MASK)
54237 /*! @} */
54238 
54239 /*! @name SIENR - Pin Interrupt Level or Rising-Edge Interrupt Set */
54240 /*! @{ */
54241 
54242 #define PINT_SIENR_SETENRL_MASK                  (0xFFU)
54243 #define PINT_SIENR_SETENRL_SHIFT                 (0U)
54244 /*! SETENRL - Configures IENR
54245  *  0b00000000..No operation for interrupt n
54246  *  0b00000001..Enable rising edge or level interrupt for interrupt n
54247  */
54248 #define PINT_SIENR_SETENRL(x)                    (((uint32_t)(((uint32_t)(x)) << PINT_SIENR_SETENRL_SHIFT)) & PINT_SIENR_SETENRL_MASK)
54249 /*! @} */
54250 
54251 /*! @name CIENR - Pin Interrupt Level (Rising-Edge Interrupt) Clear */
54252 /*! @{ */
54253 
54254 #define PINT_CIENR_CENRL_MASK                    (0xFFU)
54255 #define PINT_CIENR_CENRL_SHIFT                   (0U)
54256 /*! CENRL - Clear bits in IENR
54257  *  0b00000000..No operation
54258  *  0b00000001..Disable rising edge or level interrupt
54259  */
54260 #define PINT_CIENR_CENRL(x)                      (((uint32_t)(((uint32_t)(x)) << PINT_CIENR_CENRL_SHIFT)) & PINT_CIENR_CENRL_MASK)
54261 /*! @} */
54262 
54263 /*! @name IENF - Pin Interrupt Active Level or Falling-Edge Interrupt Enable */
54264 /*! @{ */
54265 
54266 #define PINT_IENF_ENAF_MASK                      (0xFFU)
54267 #define PINT_IENF_ENAF_SHIFT                     (0U)
54268 /*! ENAF - Enables Interrupt
54269  *  0b00000000..Disable (set active interrupt level LOW)
54270  *  0b00000001..Enable (set active interrupt level HIGH)
54271  */
54272 #define PINT_IENF_ENAF(x)                        (((uint32_t)(((uint32_t)(x)) << PINT_IENF_ENAF_SHIFT)) & PINT_IENF_ENAF_MASK)
54273 /*! @} */
54274 
54275 /*! @name SIENF - Pin Interrupt Active Level or Falling-Edge Interrupt Set */
54276 /*! @{ */
54277 
54278 #define PINT_SIENF_SETENAF_MASK                  (0xFFU)
54279 #define PINT_SIENF_SETENAF_SHIFT                 (0U)
54280 /*! SETENAF
54281  *  0b00000000..Writes 0 to IENF.
54282  *  0b00000001..Select HIGH-active interrupt or enable falling-edge interrupt
54283  */
54284 #define PINT_SIENF_SETENAF(x)                    (((uint32_t)(((uint32_t)(x)) << PINT_SIENF_SETENAF_SHIFT)) & PINT_SIENF_SETENAF_MASK)
54285 /*! @} */
54286 
54287 /*! @name CIENF - Pin Interrupt Active Level or Falling-Edge Interrupt Clear */
54288 /*! @{ */
54289 
54290 #define PINT_CIENF_CENAF_MASK                    (0xFFU)
54291 #define PINT_CIENF_CENAF_SHIFT                   (0U)
54292 /*! CENAF - Writes 0 to IENF
54293  *  0b00000000..No operation
54294  *  0b00000001..LOW-active interrupt selected or falling-edge interrupt disabled
54295  */
54296 #define PINT_CIENF_CENAF(x)                      (((uint32_t)(((uint32_t)(x)) << PINT_CIENF_CENAF_SHIFT)) & PINT_CIENF_CENAF_MASK)
54297 /*! @} */
54298 
54299 /*! @name RISE - Pin Interrupt Rising Edge */
54300 /*! @{ */
54301 
54302 #define PINT_RISE_RDET_MASK                      (0xFFU)
54303 #define PINT_RISE_RDET_SHIFT                     (0U)
54304 /*! RDET - Rising-Edge Detect
54305  *  0b00000000..Read 0- No rising edge (since Reset or you wrote a 1 to this field last time), Write 0- No operation
54306  *  0b00000001..Read 1- Rising edge (since Reset or you wrote a 1 to this field last time), Write 1- Clear rising-edge detection for this pin
54307  */
54308 #define PINT_RISE_RDET(x)                        (((uint32_t)(((uint32_t)(x)) << PINT_RISE_RDET_SHIFT)) & PINT_RISE_RDET_MASK)
54309 /*! @} */
54310 
54311 /*! @name FALL - Pin Interrupt Falling Edge */
54312 /*! @{ */
54313 
54314 #define PINT_FALL_FDET_MASK                      (0xFFU)
54315 #define PINT_FALL_FDET_SHIFT                     (0U)
54316 /*! FDET - Falling-Edge Detect
54317  *  0b00000000..Read 0- No falling edge (since Reset or you wrote a 1 to this field last time), Write 0- No operation
54318  *  0b00000001..Read 1- Falling edge (since Reset or you wrote a 1 to this field last time), Write 1- Clear falling-edge detection for this bit
54319  */
54320 #define PINT_FALL_FDET(x)                        (((uint32_t)(((uint32_t)(x)) << PINT_FALL_FDET_SHIFT)) & PINT_FALL_FDET_MASK)
54321 /*! @} */
54322 
54323 /*! @name IST - Pin Interrupt Status */
54324 /*! @{ */
54325 
54326 #define PINT_IST_PSTAT_MASK                      (0xFFU)
54327 #define PINT_IST_PSTAT_SHIFT                     (0U)
54328 /*! PSTAT - Pin Interrupt Status
54329  *  0b00000000..Read 0- Interrupt is not requested, Write 0- No operation
54330  *  0b00000001..Read 1- Interrupt is requested, Write 1 (edge-sensitive)- clear rising- and falling-edge detection
54331  *              for this pin, Write 1 (level-sensitive)- switch the active level for this pin in
54332  */
54333 #define PINT_IST_PSTAT(x)                        (((uint32_t)(((uint32_t)(x)) << PINT_IST_PSTAT_SHIFT)) & PINT_IST_PSTAT_MASK)
54334 /*! @} */
54335 
54336 /*! @name PMCTRL - Pattern-Match Interrupt Control */
54337 /*! @{ */
54338 
54339 #define PINT_PMCTRL_SEL_PMATCH_MASK              (0x1U)
54340 #define PINT_PMCTRL_SEL_PMATCH_SHIFT             (0U)
54341 /*! SEL_PMATCH - Specifies whether the pin interrupts are controlled by the pin interrupt function
54342  *    or by the pattern-match function. If this value is 0b, interrupts are driven in response to the
54343  *    standard pin interrupt function. If this value is 1b, interrupts are driven in response to
54344  *    pattern matches.
54345  *  0b0..Pin interrupt
54346  *  0b1..Pattern match
54347  */
54348 #define PINT_PMCTRL_SEL_PMATCH(x)                (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_SEL_PMATCH_SHIFT)) & PINT_PMCTRL_SEL_PMATCH_MASK)
54349 
54350 #define PINT_PMCTRL_ENA_RXEV_MASK                (0x2U)
54351 #define PINT_PMCTRL_ENA_RXEV_SHIFT               (1U)
54352 /*! ENA_RXEV - Enables the RXEV output to the CPU and/or to a GPIO output, when the specified
54353  *    Boolean expression evaluates to true. If this value is 0b, RXEV output to the CPU is disabled. If
54354  *    this value is 1b, RXEV output to the CPU is enabled.
54355  *  0b0..Disabled
54356  *  0b1..Enabled
54357  */
54358 #define PINT_PMCTRL_ENA_RXEV(x)                  (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_ENA_RXEV_SHIFT)) & PINT_PMCTRL_ENA_RXEV_MASK)
54359 
54360 #define PINT_PMCTRL_PMAT_MASK                    (0xFF000000U)
54361 #define PINT_PMCTRL_PMAT_SHIFT                   (24U)
54362 /*! PMAT - Pattern Matches
54363  *  0b00000001..The corresponding product term is matched by the current state of the appropriate inputs
54364  */
54365 #define PINT_PMCTRL_PMAT(x)                      (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_PMAT_SHIFT)) & PINT_PMCTRL_PMAT_MASK)
54366 /*! @} */
54367 
54368 /*! @name PMSRC - Pattern-Match Interrupt Bit-Slice Source */
54369 /*! @{ */
54370 
54371 #define PINT_PMSRC_SRC0_MASK                     (0x700U)
54372 #define PINT_PMSRC_SRC0_SHIFT                    (8U)
54373 /*! SRC0 - Selects the input source for bit slice 0
54374  *  0b000..Input 0 (selects the pin identified in PINSEL0)
54375  *  0b001..Input 1 (selects the pin identified in PINSEL1)
54376  *  0b010..Input 2 (selects the pin identified in PINSEL2)
54377  *  0b011..Input 3 (selects the pin identified in PINSEL3)
54378  *  0b100..Input 4 (selects the pin identified in PINSEL4)
54379  *  0b101..Input 5 (selects the pin identified in PINSEL5)
54380  *  0b110..Input 6 (selects the pin identified in PINSEL6)
54381  *  0b111..Input 7 (selects the pin identified in PINSEL7)
54382  */
54383 #define PINT_PMSRC_SRC0(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC0_SHIFT)) & PINT_PMSRC_SRC0_MASK)
54384 
54385 #define PINT_PMSRC_SRC1_MASK                     (0x3800U)
54386 #define PINT_PMSRC_SRC1_SHIFT                    (11U)
54387 /*! SRC1 - Selects the input source for bit slice 1
54388  *  0b000..Input 0 (selects the pin identified in PINSEL0)
54389  *  0b001..Input 1 (selects the pin identified in PINSEL1)
54390  *  0b010..Input 2 (selects the pin identified in PINSEL2)
54391  *  0b011..Input 3 (selects the pin identified in PINSEL3)
54392  *  0b100..Input 4 (selects the pin identified in PINSEL4)
54393  *  0b101..Input 5 (selects the pin identified in PINSEL5)
54394  *  0b110..Input 6 (selects the pin identified in PINSEL6)
54395  *  0b111..Input 7 (selects the pin identified in PINSEL7)
54396  */
54397 #define PINT_PMSRC_SRC1(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC1_SHIFT)) & PINT_PMSRC_SRC1_MASK)
54398 
54399 #define PINT_PMSRC_SRC2_MASK                     (0x1C000U)
54400 #define PINT_PMSRC_SRC2_SHIFT                    (14U)
54401 /*! SRC2 - Selects the input source for bit slice 2
54402  *  0b000..Input 0 (selects the pin identified in PINSEL0)
54403  *  0b001..Input 1 (selects the pin identified in PINSEL1)
54404  *  0b010..Input 2 (selects the pin identified in PINSEL2)
54405  *  0b011..Input 3 (selects the pin identified in PINSEL3)
54406  *  0b100..Input 4 (selects the pin identified in PINSEL4)
54407  *  0b101..Input 5 (selects the pin identified in PINSEL5)
54408  *  0b110..Input 6 (selects the pin identified in PINSEL6)
54409  *  0b111..Input 7 (selects the pin identified in PINSEL7)
54410  */
54411 #define PINT_PMSRC_SRC2(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC2_SHIFT)) & PINT_PMSRC_SRC2_MASK)
54412 
54413 #define PINT_PMSRC_SRC3_MASK                     (0xE0000U)
54414 #define PINT_PMSRC_SRC3_SHIFT                    (17U)
54415 /*! SRC3 - Selects the input source for bit slice 3
54416  *  0b000..Input 0 (selects the pin identified in PINSEL0)
54417  *  0b001..Input 1 (selects the pin identified in PINSEL1)
54418  *  0b010..Input 2 (selects the pin identified in PINSEL2)
54419  *  0b011..Input 3 (selects the pin identified in PINSEL3)
54420  *  0b100..Input 4 (selects the pin identified in PINSEL4)
54421  *  0b101..Input 5 (selects the pin identified in PINSEL5)
54422  *  0b110..Input 6 (selects the pin identified in PINSEL6)
54423  *  0b111..Input 7 (selects the pin identified in PINSEL7)
54424  */
54425 #define PINT_PMSRC_SRC3(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC3_SHIFT)) & PINT_PMSRC_SRC3_MASK)
54426 
54427 #define PINT_PMSRC_SRC4_MASK                     (0x700000U)
54428 #define PINT_PMSRC_SRC4_SHIFT                    (20U)
54429 /*! SRC4 - Selects the input source for bit slice 4
54430  *  0b000..Input 0 (selects the pin identified in PINSEL0)
54431  *  0b001..Input 1 (selects the pin identified in PINSEL1)
54432  *  0b010..Input 2 (selects the pin identified in PINSEL2)
54433  *  0b011..Input 3 (selects the pin identified in PINSEL3)
54434  *  0b100..Input 4 (selects the pin identified in PINSEL4)
54435  *  0b101..Input 5 (selects the pin identified in PINSEL5)
54436  *  0b110..Input 6 (selects the pin identified in PINSEL6)
54437  *  0b111..Input 7 (selects the pin identified in PINSEL7)
54438  */
54439 #define PINT_PMSRC_SRC4(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC4_SHIFT)) & PINT_PMSRC_SRC4_MASK)
54440 
54441 #define PINT_PMSRC_SRC5_MASK                     (0x3800000U)
54442 #define PINT_PMSRC_SRC5_SHIFT                    (23U)
54443 /*! SRC5 - Selects the input source for bit slice 5
54444  *  0b000..Input 0 (selects the pin identified in PINSEL0)
54445  *  0b001..Input 1 (selects the pin identified in PINSEL1)
54446  *  0b010..Input 2 (selects the pin identified in PINSEL2)
54447  *  0b011..Input 3 (selects the pin identified in PINSEL3)
54448  *  0b100..Input 4 (selects the pin identified in PINSEL4)
54449  *  0b101..Input 5 (selects the pin identified in PINSEL5)
54450  *  0b110..Input 6 (selects the pin identified in PINSEL6)
54451  *  0b111..Input 7 (selects the pin identified in PINSEL7)
54452  */
54453 #define PINT_PMSRC_SRC5(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC5_SHIFT)) & PINT_PMSRC_SRC5_MASK)
54454 
54455 #define PINT_PMSRC_SRC6_MASK                     (0x1C000000U)
54456 #define PINT_PMSRC_SRC6_SHIFT                    (26U)
54457 /*! SRC6 - Selects the input source for bit slice 6
54458  *  0b000..Input 0 (selects the pin identified in PINSEL0)
54459  *  0b001..Input 1 (selects the pin identified in PINSEL1)
54460  *  0b010..Input 2 (selects the pin identified in PINSEL2)
54461  *  0b011..Input 3 (selects the pin identified in PINSEL3)
54462  *  0b100..Input 4 (selects the pin identified in PINSEL4)
54463  *  0b101..Input 5 (selects the pin identified in PINSEL5)
54464  *  0b110..Input 6 (selects the pin identified in PINSEL6)
54465  *  0b111..Input 7 (selects the pin identified in PINSEL7)
54466  */
54467 #define PINT_PMSRC_SRC6(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC6_SHIFT)) & PINT_PMSRC_SRC6_MASK)
54468 
54469 #define PINT_PMSRC_SRC7_MASK                     (0xE0000000U)
54470 #define PINT_PMSRC_SRC7_SHIFT                    (29U)
54471 /*! SRC7 - Selects the input source for bit slice 7
54472  *  0b000..Input 0 (selects the pin identified in PINSEL0)
54473  *  0b001..Input 1 (selects the pin identified in PINSEL1)
54474  *  0b010..Input 2 (selects the pin identified in PINSEL2)
54475  *  0b011..Input 3 (selects the pin identified in PINSEL3)
54476  *  0b100..Input 4 (selects the pin identified in PINSEL4)
54477  *  0b101..Input 5 (selects the pin identified in PINSEL5)
54478  *  0b110..Input 6 (selects the pin identified in PINSEL6)
54479  *  0b111..Input 7 (selects the pin identified in PINSEL7)
54480  */
54481 #define PINT_PMSRC_SRC7(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC7_SHIFT)) & PINT_PMSRC_SRC7_MASK)
54482 /*! @} */
54483 
54484 /*! @name PMCFG - Pattern-Match Interrupt Bit Slice Configuration */
54485 /*! @{ */
54486 
54487 #define PINT_PMCFG_PROD_ENDPTS0_MASK             (0x1U)
54488 #define PINT_PMCFG_PROD_ENDPTS0_SHIFT            (0U)
54489 /*! PROD_ENDPTS0 - Determines whether slice 0 is an endpoint. Slice 0 is not an endpoint. Slice 0 is
54490  *    the endpoint of a product term (minterm). Pin interrupt 0 in the NVIC is raised if the
54491  *    minterm evaluates as true.
54492  *  0b0..No effect
54493  *  0b1..Endpoint
54494  */
54495 #define PINT_PMCFG_PROD_ENDPTS0(x)               (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS0_SHIFT)) & PINT_PMCFG_PROD_ENDPTS0_MASK)
54496 
54497 #define PINT_PMCFG_PROD_ENDPTS1_MASK             (0x2U)
54498 #define PINT_PMCFG_PROD_ENDPTS1_SHIFT            (1U)
54499 /*! PROD_ENDPTS1 - Determines whether slice 1 is an endpoint. Slice 1 is not an endpoint. Slice 1 is
54500  *    the endpoint of a product term (minterm). Pin interrupt 1 in the NVIC is raised if the
54501  *    minterm evaluates as true.
54502  *  0b0..No effect
54503  *  0b1..Endpoint
54504  */
54505 #define PINT_PMCFG_PROD_ENDPTS1(x)               (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS1_SHIFT)) & PINT_PMCFG_PROD_ENDPTS1_MASK)
54506 
54507 #define PINT_PMCFG_PROD_ENDPTS2_MASK             (0x4U)
54508 #define PINT_PMCFG_PROD_ENDPTS2_SHIFT            (2U)
54509 /*! PROD_ENDPTS2 - Determines whether slice 2 is an endpoint. Slice 2 is not an endpoint. Slice 2 is
54510  *    the endpoint of a product term (minterm). Pin interrupt 2 in the NVIC is raised if the
54511  *    minterm evaluates as true.
54512  *  0b0..No effect
54513  *  0b1..Endpoint
54514  */
54515 #define PINT_PMCFG_PROD_ENDPTS2(x)               (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS2_SHIFT)) & PINT_PMCFG_PROD_ENDPTS2_MASK)
54516 
54517 #define PINT_PMCFG_PROD_ENDPTS3_MASK             (0x8U)
54518 #define PINT_PMCFG_PROD_ENDPTS3_SHIFT            (3U)
54519 /*! PROD_ENDPTS3 - Determines whether slice 3 is an endpoint. Slice 3 is not an endpoint. Slice 3 is
54520  *    the endpoint of a product term (minterm). Pin interrupt 3 in the NVIC is raised if the
54521  *    minterm evaluates as true.
54522  *  0b0..No effect
54523  *  0b1..Endpoint
54524  */
54525 #define PINT_PMCFG_PROD_ENDPTS3(x)               (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS3_SHIFT)) & PINT_PMCFG_PROD_ENDPTS3_MASK)
54526 
54527 #define PINT_PMCFG_PROD_ENDPTS4_MASK             (0x10U)
54528 #define PINT_PMCFG_PROD_ENDPTS4_SHIFT            (4U)
54529 /*! PROD_ENDPTS4 - Determines whether slice 4 is an endpoint. Slice 4 is not an endpoint. Slice 4 is
54530  *    the endpoint of a product term (minterm). Pin interrupt 4 in the NVIC is raised if the
54531  *    minterm evaluates as true.
54532  *  0b0..No effect
54533  *  0b1..Endpoint
54534  */
54535 #define PINT_PMCFG_PROD_ENDPTS4(x)               (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS4_SHIFT)) & PINT_PMCFG_PROD_ENDPTS4_MASK)
54536 
54537 #define PINT_PMCFG_PROD_ENDPTS5_MASK             (0x20U)
54538 #define PINT_PMCFG_PROD_ENDPTS5_SHIFT            (5U)
54539 /*! PROD_ENDPTS5 - Determines whether slice 5 is an endpoint. Slice 5 is not an endpoint. Slice 5 is
54540  *    the endpoint of a product term (minterm). Pin interrupt 5 in the NVIC is raised if the
54541  *    minterm evaluates as true.
54542  *  0b0..No effect
54543  *  0b1..Endpoint
54544  */
54545 #define PINT_PMCFG_PROD_ENDPTS5(x)               (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS5_SHIFT)) & PINT_PMCFG_PROD_ENDPTS5_MASK)
54546 
54547 #define PINT_PMCFG_PROD_ENDPTS6_MASK             (0x40U)
54548 #define PINT_PMCFG_PROD_ENDPTS6_SHIFT            (6U)
54549 /*! PROD_ENDPTS6 - Determines whether slice 6 is an endpoint. Slice 6 is not an endpoint. Slice 6 is
54550  *    the endpoint of a product term (minterm). Pin interrupt 6 in the NVIC is raised if the
54551  *    minterm evaluates as true.
54552  *  0b0..No effect
54553  *  0b1..Endpoint
54554  */
54555 #define PINT_PMCFG_PROD_ENDPTS6(x)               (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS6_SHIFT)) & PINT_PMCFG_PROD_ENDPTS6_MASK)
54556 
54557 #define PINT_PMCFG_CFG0_MASK                     (0x700U)
54558 #define PINT_PMCFG_CFG0_SHIFT                    (8U)
54559 /*! CFG0 - Match Configuration
54560  *  0b000..Constant HIGH
54561  *  0b001..Sticky rising edge
54562  *  0b010..Sticky falling edge
54563  *  0b011..Sticky rising or falling edge
54564  *  0b100..High level
54565  *  0b101..Low level
54566  *  0b110..Constant 0
54567  *  0b111..Event (Nonsticky rising or falling edge)
54568  */
54569 #define PINT_PMCFG_CFG0(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG0_SHIFT)) & PINT_PMCFG_CFG0_MASK)
54570 
54571 #define PINT_PMCFG_CFG1_MASK                     (0x3800U)
54572 #define PINT_PMCFG_CFG1_SHIFT                    (11U)
54573 /*! CFG1 - Match Configuration
54574  *  0b000..Constant HIGH
54575  *  0b001..Sticky rising edge
54576  *  0b010..Sticky falling edge
54577  *  0b011..Sticky rising or falling edge
54578  *  0b100..High level
54579  *  0b101..Low level
54580  *  0b110..Constant 0
54581  *  0b111..Event (Nonsticky rising or falling edge)
54582  */
54583 #define PINT_PMCFG_CFG1(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG1_SHIFT)) & PINT_PMCFG_CFG1_MASK)
54584 
54585 #define PINT_PMCFG_CFG2_MASK                     (0x1C000U)
54586 #define PINT_PMCFG_CFG2_SHIFT                    (14U)
54587 /*! CFG2 - Match Configuration
54588  *  0b000..Constant HIGH
54589  *  0b001..Sticky rising edge
54590  *  0b010..Sticky falling edge
54591  *  0b011..Sticky rising or falling edge
54592  *  0b100..High level
54593  *  0b101..Low level
54594  *  0b110..Constant 0
54595  *  0b111..Event (Nonsticky rising or falling edge)
54596  */
54597 #define PINT_PMCFG_CFG2(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG2_SHIFT)) & PINT_PMCFG_CFG2_MASK)
54598 
54599 #define PINT_PMCFG_CFG3_MASK                     (0xE0000U)
54600 #define PINT_PMCFG_CFG3_SHIFT                    (17U)
54601 /*! CFG3 - Match Configuration
54602  *  0b000..Constant HIGH
54603  *  0b001..Sticky rising edge
54604  *  0b010..Sticky falling edge
54605  *  0b011..Sticky rising or falling edge
54606  *  0b100..High level
54607  *  0b101..Low level
54608  *  0b110..Constant 0
54609  *  0b111..Event (Nonsticky rising or falling edge)
54610  */
54611 #define PINT_PMCFG_CFG3(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG3_SHIFT)) & PINT_PMCFG_CFG3_MASK)
54612 
54613 #define PINT_PMCFG_CFG4_MASK                     (0x700000U)
54614 #define PINT_PMCFG_CFG4_SHIFT                    (20U)
54615 /*! CFG4 - Match Configuration
54616  *  0b000..Constant HIGH
54617  *  0b001..Sticky rising edge
54618  *  0b010..Sticky falling edge
54619  *  0b011..Sticky rising or falling edge
54620  *  0b100..High level
54621  *  0b101..Low level
54622  *  0b110..Constant 0
54623  *  0b111..Event (Nonsticky rising or falling edge)
54624  */
54625 #define PINT_PMCFG_CFG4(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG4_SHIFT)) & PINT_PMCFG_CFG4_MASK)
54626 
54627 #define PINT_PMCFG_CFG5_MASK                     (0x3800000U)
54628 #define PINT_PMCFG_CFG5_SHIFT                    (23U)
54629 /*! CFG5 - Match Configuration
54630  *  0b000..Constant HIGH
54631  *  0b001..Sticky rising edge
54632  *  0b010..Sticky falling edge
54633  *  0b011..Sticky rising or falling edge
54634  *  0b100..High level
54635  *  0b101..Low level
54636  *  0b110..Constant 0
54637  *  0b111..Event (Nonsticky rising or falling edge)
54638  */
54639 #define PINT_PMCFG_CFG5(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG5_SHIFT)) & PINT_PMCFG_CFG5_MASK)
54640 
54641 #define PINT_PMCFG_CFG6_MASK                     (0x1C000000U)
54642 #define PINT_PMCFG_CFG6_SHIFT                    (26U)
54643 /*! CFG6 - Match Configuration
54644  *  0b000..Constant HIGH
54645  *  0b001..Sticky rising edge
54646  *  0b010..Sticky falling edge
54647  *  0b011..Sticky rising or falling edge
54648  *  0b100..High level
54649  *  0b101..Low level
54650  *  0b110..Constant 0
54651  *  0b111..Event (Nonsticky rising or falling edge)
54652  */
54653 #define PINT_PMCFG_CFG6(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG6_SHIFT)) & PINT_PMCFG_CFG6_MASK)
54654 
54655 #define PINT_PMCFG_CFG7_MASK                     (0xE0000000U)
54656 #define PINT_PMCFG_CFG7_SHIFT                    (29U)
54657 /*! CFG7 - Match Configuration
54658  *  0b000..Constant HIGH
54659  *  0b001..Sticky rising edge
54660  *  0b010..Sticky falling edge
54661  *  0b011..Sticky rising or falling edge
54662  *  0b100..High level
54663  *  0b101..Low level
54664  *  0b110..Constant 0
54665  *  0b111..Event (Nonsticky rising or falling edge)
54666  */
54667 #define PINT_PMCFG_CFG7(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG7_SHIFT)) & PINT_PMCFG_CFG7_MASK)
54668 /*! @} */
54669 
54670 
54671 /*!
54672  * @}
54673  */ /* end of group PINT_Register_Masks */
54674 
54675 
54676 /* PINT - Peripheral instance base addresses */
54677 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
54678   /** Peripheral PINT0 base address */
54679   #define PINT0_BASE                               (0x50004000u)
54680   /** Peripheral PINT0 base address */
54681   #define PINT0_BASE_NS                            (0x40004000u)
54682   /** Peripheral PINT0 base pointer */
54683   #define PINT0                                    ((PINT_Type *)PINT0_BASE)
54684   /** Peripheral PINT0 base pointer */
54685   #define PINT0_NS                                 ((PINT_Type *)PINT0_BASE_NS)
54686   /** Array initializer of PINT peripheral base addresses */
54687   #define PINT_BASE_ADDRS                          { PINT0_BASE }
54688   /** Array initializer of PINT peripheral base pointers */
54689   #define PINT_BASE_PTRS                           { PINT0 }
54690   /** Array initializer of PINT peripheral base addresses */
54691   #define PINT_BASE_ADDRS_NS                       { PINT0_BASE_NS }
54692   /** Array initializer of PINT peripheral base pointers */
54693   #define PINT_BASE_PTRS_NS                        { PINT0_NS }
54694 #else
54695   /** Peripheral PINT0 base address */
54696   #define PINT0_BASE                               (0x40004000u)
54697   /** Peripheral PINT0 base pointer */
54698   #define PINT0                                    ((PINT_Type *)PINT0_BASE)
54699   /** Array initializer of PINT peripheral base addresses */
54700   #define PINT_BASE_ADDRS                          { PINT0_BASE }
54701   /** Array initializer of PINT peripheral base pointers */
54702   #define PINT_BASE_PTRS                           { PINT0 }
54703 #endif
54704 /** Interrupt vectors for the PINT peripheral type */
54705 #define PINT_IRQS                                { PINT0_IRQn }
54706 /* Backward compatibility */
54707 #define PINT                               PINT0
54708 
54709 
54710 /*!
54711  * @}
54712  */ /* end of group PINT_Peripheral_Access_Layer */
54713 
54714 
54715 /* ----------------------------------------------------------------------------
54716    -- PKC Peripheral Access Layer
54717    ---------------------------------------------------------------------------- */
54718 
54719 /*!
54720  * @addtogroup PKC_Peripheral_Access_Layer PKC Peripheral Access Layer
54721  * @{
54722  */
54723 
54724 /** PKC - Register Layout Typedef */
54725 typedef struct {
54726   __I  uint32_t PKC_STATUS;                        /**< Status Register, offset: 0x0 */
54727   __IO uint32_t PKC_CTRL;                          /**< Control Register, offset: 0x4 */
54728   __IO uint32_t PKC_CFG;                           /**< Configuration register, offset: 0x8 */
54729        uint8_t RESERVED_0[4];
54730   __IO uint32_t PKC_MODE1;                         /**< Mode register, parameter set 1, offset: 0x10 */
54731   __IO uint32_t PKC_XYPTR1;                        /**< X+Y pointer register, parameter set 1, offset: 0x14 */
54732   __IO uint32_t PKC_ZRPTR1;                        /**< Z+R pointer register, parameter set 1, offset: 0x18 */
54733   __IO uint32_t PKC_LEN1;                          /**< Length register, parameter set 1, offset: 0x1C */
54734   __IO uint32_t PKC_MODE2;                         /**< Mode register, parameter set 2, offset: 0x20 */
54735   __IO uint32_t PKC_XYPTR2;                        /**< X+Y pointer register, parameter set 2, offset: 0x24 */
54736   __IO uint32_t PKC_ZRPTR2;                        /**< Z+R pointer register, parameter set 2, offset: 0x28 */
54737   __IO uint32_t PKC_LEN2;                          /**< Length register, parameter set 2, offset: 0x2C */
54738        uint8_t RESERVED_1[16];
54739   __IO uint32_t PKC_UPTR;                          /**< Universal pointer FUP program, offset: 0x40 */
54740   __IO uint32_t PKC_UPTRT;                         /**< Universal pointer FUP table, offset: 0x44 */
54741   __IO uint32_t PKC_ULEN;                          /**< Universal pointer length, offset: 0x48 */
54742        uint8_t RESERVED_2[4];
54743   __IO uint32_t PKC_MCDATA;                        /**< MC pattern data interface, offset: 0x50 */
54744        uint8_t RESERVED_3[12];
54745   __I  uint32_t PKC_VERSION;                       /**< PKC version register, offset: 0x60 */
54746        uint8_t RESERVED_4[3916];
54747   __O  uint32_t PKC_SOFT_RST;                      /**< Software reset, offset: 0xFB0 */
54748        uint8_t RESERVED_5[12];
54749   __I  uint32_t PKC_ACCESS_ERR;                    /**< Access Error, offset: 0xFC0 */
54750   __O  uint32_t PKC_ACCESS_ERR_CLR;                /**< Clear Access Error, offset: 0xFC4 */
54751        uint8_t RESERVED_6[16];
54752   __O  uint32_t PKC_INT_CLR_ENABLE;                /**< Interrupt enable clear, offset: 0xFD8 */
54753   __O  uint32_t PKC_INT_SET_ENABLE;                /**< Interrupt enable set, offset: 0xFDC */
54754   __I  uint32_t PKC_INT_STATUS;                    /**< Interrupt status, offset: 0xFE0 */
54755   __I  uint32_t PKC_INT_ENABLE;                    /**< Interrupt enable, offset: 0xFE4 */
54756   __O  uint32_t PKC_INT_CLR_STATUS;                /**< Interrupt status clear, offset: 0xFE8 */
54757   __O  uint32_t PKC_INT_SET_STATUS;                /**< Interrupt status set, offset: 0xFEC */
54758        uint8_t RESERVED_7[12];
54759   __I  uint32_t PKC_MODULE_ID;                     /**< Module ID, offset: 0xFFC */
54760 } PKC_Type;
54761 
54762 /* ----------------------------------------------------------------------------
54763    -- PKC Register Masks
54764    ---------------------------------------------------------------------------- */
54765 
54766 /*!
54767  * @addtogroup PKC_Register_Masks PKC Register Masks
54768  * @{
54769  */
54770 
54771 /*! @name PKC_STATUS - Status Register */
54772 /*! @{ */
54773 
54774 #define PKC_PKC_STATUS_ACTIV_MASK                (0x1U)
54775 #define PKC_PKC_STATUS_ACTIV_SHIFT               (0U)
54776 /*! ACTIV - PKC ACTIV */
54777 #define PKC_PKC_STATUS_ACTIV(x)                  (((uint32_t)(((uint32_t)(x)) << PKC_PKC_STATUS_ACTIV_SHIFT)) & PKC_PKC_STATUS_ACTIV_MASK)
54778 
54779 #define PKC_PKC_STATUS_CARRY_MASK                (0x2U)
54780 #define PKC_PKC_STATUS_CARRY_SHIFT               (1U)
54781 /*! CARRY - Carry overflow flag */
54782 #define PKC_PKC_STATUS_CARRY(x)                  (((uint32_t)(((uint32_t)(x)) << PKC_PKC_STATUS_CARRY_SHIFT)) & PKC_PKC_STATUS_CARRY_MASK)
54783 
54784 #define PKC_PKC_STATUS_ZERO_MASK                 (0x4U)
54785 #define PKC_PKC_STATUS_ZERO_SHIFT                (2U)
54786 /*! ZERO - Zero result flag */
54787 #define PKC_PKC_STATUS_ZERO(x)                   (((uint32_t)(((uint32_t)(x)) << PKC_PKC_STATUS_ZERO_SHIFT)) & PKC_PKC_STATUS_ZERO_MASK)
54788 
54789 #define PKC_PKC_STATUS_GOANY_MASK                (0x8U)
54790 #define PKC_PKC_STATUS_GOANY_SHIFT               (3U)
54791 /*! GOANY - Combined GO status flag */
54792 #define PKC_PKC_STATUS_GOANY(x)                  (((uint32_t)(((uint32_t)(x)) << PKC_PKC_STATUS_GOANY_SHIFT)) & PKC_PKC_STATUS_GOANY_MASK)
54793 
54794 #define PKC_PKC_STATUS_LOCKED_MASK               (0x60U)
54795 #define PKC_PKC_STATUS_LOCKED_SHIFT              (5U)
54796 /*! LOCKED - Parameter set locked */
54797 #define PKC_PKC_STATUS_LOCKED(x)                 (((uint32_t)(((uint32_t)(x)) << PKC_PKC_STATUS_LOCKED_SHIFT)) & PKC_PKC_STATUS_LOCKED_MASK)
54798 /*! @} */
54799 
54800 /*! @name PKC_CTRL - Control Register */
54801 /*! @{ */
54802 
54803 #define PKC_PKC_CTRL_RESET_MASK                  (0x1U)
54804 #define PKC_PKC_CTRL_RESET_SHIFT                 (0U)
54805 /*! RESET - PKC reset control bit */
54806 #define PKC_PKC_CTRL_RESET(x)                    (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_RESET_SHIFT)) & PKC_PKC_CTRL_RESET_MASK)
54807 
54808 #define PKC_PKC_CTRL_STOP_MASK                   (0x2U)
54809 #define PKC_PKC_CTRL_STOP_SHIFT                  (1U)
54810 /*! STOP - Freeze PKC calculation */
54811 #define PKC_PKC_CTRL_STOP(x)                     (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_STOP_SHIFT)) & PKC_PKC_CTRL_STOP_MASK)
54812 
54813 #define PKC_PKC_CTRL_GOD1_MASK                   (0x4U)
54814 #define PKC_PKC_CTRL_GOD1_SHIFT                  (2U)
54815 /*! GOD1 - Control bit to start direct operation using parameter set 1 */
54816 #define PKC_PKC_CTRL_GOD1(x)                     (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_GOD1_SHIFT)) & PKC_PKC_CTRL_GOD1_MASK)
54817 
54818 #define PKC_PKC_CTRL_GOD2_MASK                   (0x8U)
54819 #define PKC_PKC_CTRL_GOD2_SHIFT                  (3U)
54820 /*! GOD2 - Control bit to start direct operation using parameter set 2 */
54821 #define PKC_PKC_CTRL_GOD2(x)                     (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_GOD2_SHIFT)) & PKC_PKC_CTRL_GOD2_MASK)
54822 
54823 #define PKC_PKC_CTRL_GOM1_MASK                   (0x10U)
54824 #define PKC_PKC_CTRL_GOM1_SHIFT                  (4U)
54825 /*! GOM1 - Control bit to start MC pattern using parameter set 1 */
54826 #define PKC_PKC_CTRL_GOM1(x)                     (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_GOM1_SHIFT)) & PKC_PKC_CTRL_GOM1_MASK)
54827 
54828 #define PKC_PKC_CTRL_GOM2_MASK                   (0x20U)
54829 #define PKC_PKC_CTRL_GOM2_SHIFT                  (5U)
54830 /*! GOM2 - Control bit to start MC pattern using parameter set 2 */
54831 #define PKC_PKC_CTRL_GOM2(x)                     (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_GOM2_SHIFT)) & PKC_PKC_CTRL_GOM2_MASK)
54832 
54833 #define PKC_PKC_CTRL_GOU_MASK                    (0x40U)
54834 #define PKC_PKC_CTRL_GOU_SHIFT                   (6U)
54835 /*! GOU - Control bit to start pipe operation */
54836 #define PKC_PKC_CTRL_GOU(x)                      (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_GOU_SHIFT)) & PKC_PKC_CTRL_GOU_MASK)
54837 
54838 #define PKC_PKC_CTRL_GF2CONV_MASK                (0x80U)
54839 #define PKC_PKC_CTRL_GF2CONV_SHIFT               (7U)
54840 /*! GF2CONV - Convert to GF2 calculation modes */
54841 #define PKC_PKC_CTRL_GF2CONV(x)                  (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_GF2CONV_SHIFT)) & PKC_PKC_CTRL_GF2CONV_MASK)
54842 
54843 #define PKC_PKC_CTRL_CLRCACHE_MASK               (0x100U)
54844 #define PKC_PKC_CTRL_CLRCACHE_SHIFT              (8U)
54845 /*! CLRCACHE - Clear universal pointer cache */
54846 #define PKC_PKC_CTRL_CLRCACHE(x)                 (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_CLRCACHE_SHIFT)) & PKC_PKC_CTRL_CLRCACHE_MASK)
54847 
54848 #define PKC_PKC_CTRL_CACHE_EN_MASK               (0x200U)
54849 #define PKC_PKC_CTRL_CACHE_EN_SHIFT              (9U)
54850 /*! CACHE_EN - Enable universal pointer cache */
54851 #define PKC_PKC_CTRL_CACHE_EN(x)                 (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_CACHE_EN_SHIFT)) & PKC_PKC_CTRL_CACHE_EN_MASK)
54852 
54853 #define PKC_PKC_CTRL_REDMUL_MASK                 (0xC00U)
54854 #define PKC_PKC_CTRL_REDMUL_SHIFT                (10U)
54855 /*! REDMUL - Reduced multiplier mode
54856  *  0b00..full size mode, 3 least significant bits of pointer and length are ignored, minimum supported length 0x0008
54857  *  0b01..Reserved - Error Generated if selected
54858  *  0b10..64-bit mode, 3 least significant bits of pointer and length are ignored, minimum supported length 0x0008
54859  *  0b11..Reserved - Error Generated if selected
54860  */
54861 #define PKC_PKC_CTRL_REDMUL(x)                   (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_REDMUL_SHIFT)) & PKC_PKC_CTRL_REDMUL_MASK)
54862 /*! @} */
54863 
54864 /*! @name PKC_CFG - Configuration register */
54865 /*! @{ */
54866 
54867 #define PKC_PKC_CFG_IDLEOP_MASK                  (0x1U)
54868 #define PKC_PKC_CFG_IDLEOP_SHIFT                 (0U)
54869 #define PKC_PKC_CFG_IDLEOP(x)                    (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_IDLEOP_SHIFT)) & PKC_PKC_CFG_IDLEOP_MASK)
54870 
54871 #define PKC_PKC_CFG_RFU1_MASK                    (0x2U)
54872 #define PKC_PKC_CFG_RFU1_SHIFT                   (1U)
54873 #define PKC_PKC_CFG_RFU1(x)                      (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_RFU1_SHIFT)) & PKC_PKC_CFG_RFU1_MASK)
54874 
54875 #define PKC_PKC_CFG_RFU2_MASK                    (0x4U)
54876 #define PKC_PKC_CFG_RFU2_SHIFT                   (2U)
54877 #define PKC_PKC_CFG_RFU2(x)                      (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_RFU2_SHIFT)) & PKC_PKC_CFG_RFU2_MASK)
54878 
54879 #define PKC_PKC_CFG_CLKRND_MASK                  (0x8U)
54880 #define PKC_PKC_CFG_CLKRND_SHIFT                 (3U)
54881 #define PKC_PKC_CFG_CLKRND(x)                    (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_CLKRND_SHIFT)) & PKC_PKC_CFG_CLKRND_MASK)
54882 
54883 #define PKC_PKC_CFG_REDMULNOISE_MASK             (0x10U)
54884 #define PKC_PKC_CFG_REDMULNOISE_SHIFT            (4U)
54885 #define PKC_PKC_CFG_REDMULNOISE(x)               (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_REDMULNOISE_SHIFT)) & PKC_PKC_CFG_REDMULNOISE_MASK)
54886 
54887 #define PKC_PKC_CFG_RNDDLY_MASK                  (0xE0U)
54888 #define PKC_PKC_CFG_RNDDLY_SHIFT                 (5U)
54889 #define PKC_PKC_CFG_RNDDLY(x)                    (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_RNDDLY_SHIFT)) & PKC_PKC_CFG_RNDDLY_MASK)
54890 
54891 #define PKC_PKC_CFG_SBXNOISE_MASK                (0x100U)
54892 #define PKC_PKC_CFG_SBXNOISE_SHIFT               (8U)
54893 #define PKC_PKC_CFG_SBXNOISE(x)                  (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_SBXNOISE_SHIFT)) & PKC_PKC_CFG_SBXNOISE_MASK)
54894 
54895 #define PKC_PKC_CFG_ALPNOISE_MASK                (0x200U)
54896 #define PKC_PKC_CFG_ALPNOISE_SHIFT               (9U)
54897 #define PKC_PKC_CFG_ALPNOISE(x)                  (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_ALPNOISE_SHIFT)) & PKC_PKC_CFG_ALPNOISE_MASK)
54898 
54899 #define PKC_PKC_CFG_FMULNOISE_MASK               (0x400U)
54900 #define PKC_PKC_CFG_FMULNOISE_SHIFT              (10U)
54901 #define PKC_PKC_CFG_FMULNOISE(x)                 (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_FMULNOISE_SHIFT)) & PKC_PKC_CFG_FMULNOISE_MASK)
54902 /*! @} */
54903 
54904 /*! @name PKC_MODE1 - Mode register, parameter set 1 */
54905 /*! @{ */
54906 
54907 #define PKC_PKC_MODE1_MODE_MASK                  (0xFFU)
54908 #define PKC_PKC_MODE1_MODE_SHIFT                 (0U)
54909 /*! MODE - Calculation Mode / MC Start address */
54910 #define PKC_PKC_MODE1_MODE(x)                    (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODE1_MODE_SHIFT)) & PKC_PKC_MODE1_MODE_MASK)
54911 /*! @} */
54912 
54913 /*! @name PKC_XYPTR1 - X+Y pointer register, parameter set 1 */
54914 /*! @{ */
54915 
54916 #define PKC_PKC_XYPTR1_XPTR_MASK                 (0xFFFFU)
54917 #define PKC_PKC_XYPTR1_XPTR_SHIFT                (0U)
54918 /*! XPTR - Start address of X operand in PKCRAM with byte granularity */
54919 #define PKC_PKC_XYPTR1_XPTR(x)                   (((uint32_t)(((uint32_t)(x)) << PKC_PKC_XYPTR1_XPTR_SHIFT)) & PKC_PKC_XYPTR1_XPTR_MASK)
54920 
54921 #define PKC_PKC_XYPTR1_YPTR_MASK                 (0xFFFF0000U)
54922 #define PKC_PKC_XYPTR1_YPTR_SHIFT                (16U)
54923 /*! YPTR - Start address of Y operand in PKCRAM with byte granularity */
54924 #define PKC_PKC_XYPTR1_YPTR(x)                   (((uint32_t)(((uint32_t)(x)) << PKC_PKC_XYPTR1_YPTR_SHIFT)) & PKC_PKC_XYPTR1_YPTR_MASK)
54925 /*! @} */
54926 
54927 /*! @name PKC_ZRPTR1 - Z+R pointer register, parameter set 1 */
54928 /*! @{ */
54929 
54930 #define PKC_PKC_ZRPTR1_ZPTR_MASK                 (0xFFFFU)
54931 #define PKC_PKC_ZRPTR1_ZPTR_SHIFT                (0U)
54932 /*! ZPTR - Start address of Z operand in PKCRAM with byte granularity or constant for calculation modes using CONST */
54933 #define PKC_PKC_ZRPTR1_ZPTR(x)                   (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ZRPTR1_ZPTR_SHIFT)) & PKC_PKC_ZRPTR1_ZPTR_MASK)
54934 
54935 #define PKC_PKC_ZRPTR1_RPTR_MASK                 (0xFFFF0000U)
54936 #define PKC_PKC_ZRPTR1_RPTR_SHIFT                (16U)
54937 /*! RPTR - Start address of R result in PKCRAM with byte granularity */
54938 #define PKC_PKC_ZRPTR1_RPTR(x)                   (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ZRPTR1_RPTR_SHIFT)) & PKC_PKC_ZRPTR1_RPTR_MASK)
54939 /*! @} */
54940 
54941 /*! @name PKC_LEN1 - Length register, parameter set 1 */
54942 /*! @{ */
54943 
54944 #define PKC_PKC_LEN1_LEN_MASK                    (0xFFFFU)
54945 #define PKC_PKC_LEN1_LEN_SHIFT                   (0U)
54946 /*! LEN - Operand length */
54947 #define PKC_PKC_LEN1_LEN(x)                      (((uint32_t)(((uint32_t)(x)) << PKC_PKC_LEN1_LEN_SHIFT)) & PKC_PKC_LEN1_LEN_MASK)
54948 
54949 #define PKC_PKC_LEN1_MCLEN_MASK                  (0xFFFF0000U)
54950 #define PKC_PKC_LEN1_MCLEN_SHIFT                 (16U)
54951 /*! MCLEN - Loop counter for microcode pattern */
54952 #define PKC_PKC_LEN1_MCLEN(x)                    (((uint32_t)(((uint32_t)(x)) << PKC_PKC_LEN1_MCLEN_SHIFT)) & PKC_PKC_LEN1_MCLEN_MASK)
54953 /*! @} */
54954 
54955 /*! @name PKC_MODE2 - Mode register, parameter set 2 */
54956 /*! @{ */
54957 
54958 #define PKC_PKC_MODE2_MODE_MASK                  (0xFFU)
54959 #define PKC_PKC_MODE2_MODE_SHIFT                 (0U)
54960 /*! MODE - Calculation Mode / MC Start address */
54961 #define PKC_PKC_MODE2_MODE(x)                    (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODE2_MODE_SHIFT)) & PKC_PKC_MODE2_MODE_MASK)
54962 /*! @} */
54963 
54964 /*! @name PKC_XYPTR2 - X+Y pointer register, parameter set 2 */
54965 /*! @{ */
54966 
54967 #define PKC_PKC_XYPTR2_XPTR_MASK                 (0xFFFFU)
54968 #define PKC_PKC_XYPTR2_XPTR_SHIFT                (0U)
54969 /*! XPTR - Start address of X operand in PKCRAM with byte granularity */
54970 #define PKC_PKC_XYPTR2_XPTR(x)                   (((uint32_t)(((uint32_t)(x)) << PKC_PKC_XYPTR2_XPTR_SHIFT)) & PKC_PKC_XYPTR2_XPTR_MASK)
54971 
54972 #define PKC_PKC_XYPTR2_YPTR_MASK                 (0xFFFF0000U)
54973 #define PKC_PKC_XYPTR2_YPTR_SHIFT                (16U)
54974 /*! YPTR - Start address of Y operand in PKCRAM with byte granularity */
54975 #define PKC_PKC_XYPTR2_YPTR(x)                   (((uint32_t)(((uint32_t)(x)) << PKC_PKC_XYPTR2_YPTR_SHIFT)) & PKC_PKC_XYPTR2_YPTR_MASK)
54976 /*! @} */
54977 
54978 /*! @name PKC_ZRPTR2 - Z+R pointer register, parameter set 2 */
54979 /*! @{ */
54980 
54981 #define PKC_PKC_ZRPTR2_ZPT_MASK                  (0xFFFFU)
54982 #define PKC_PKC_ZRPTR2_ZPT_SHIFT                 (0U)
54983 /*! ZPT - Start address of Z operand in PKCRAM with byte granularity or constant for calculation modes using CONST */
54984 #define PKC_PKC_ZRPTR2_ZPT(x)                    (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ZRPTR2_ZPT_SHIFT)) & PKC_PKC_ZRPTR2_ZPT_MASK)
54985 
54986 #define PKC_PKC_ZRPTR2_RPTR_MASK                 (0xFFFF0000U)
54987 #define PKC_PKC_ZRPTR2_RPTR_SHIFT                (16U)
54988 /*! RPTR - Start address of R result in PKCRAM with byte granularity */
54989 #define PKC_PKC_ZRPTR2_RPTR(x)                   (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ZRPTR2_RPTR_SHIFT)) & PKC_PKC_ZRPTR2_RPTR_MASK)
54990 /*! @} */
54991 
54992 /*! @name PKC_LEN2 - Length register, parameter set 2 */
54993 /*! @{ */
54994 
54995 #define PKC_PKC_LEN2_LEN_MASK                    (0xFFFFU)
54996 #define PKC_PKC_LEN2_LEN_SHIFT                   (0U)
54997 /*! LEN - Operand length */
54998 #define PKC_PKC_LEN2_LEN(x)                      (((uint32_t)(((uint32_t)(x)) << PKC_PKC_LEN2_LEN_SHIFT)) & PKC_PKC_LEN2_LEN_MASK)
54999 
55000 #define PKC_PKC_LEN2_MCLEN_MASK                  (0xFFFF0000U)
55001 #define PKC_PKC_LEN2_MCLEN_SHIFT                 (16U)
55002 /*! MCLEN - Loop counter for microcode pattern */
55003 #define PKC_PKC_LEN2_MCLEN(x)                    (((uint32_t)(((uint32_t)(x)) << PKC_PKC_LEN2_MCLEN_SHIFT)) & PKC_PKC_LEN2_MCLEN_MASK)
55004 /*! @} */
55005 
55006 /*! @name PKC_UPTR - Universal pointer FUP program */
55007 /*! @{ */
55008 
55009 #define PKC_PKC_UPTR_PTR_MASK                    (0xFFFFFFFFU)
55010 #define PKC_PKC_UPTR_PTR_SHIFT                   (0U)
55011 /*! PTR - Pointer to start address of PKC FUP program */
55012 #define PKC_PKC_UPTR_PTR(x)                      (((uint32_t)(((uint32_t)(x)) << PKC_PKC_UPTR_PTR_SHIFT)) & PKC_PKC_UPTR_PTR_MASK)
55013 /*! @} */
55014 
55015 /*! @name PKC_UPTRT - Universal pointer FUP table */
55016 /*! @{ */
55017 
55018 #define PKC_PKC_UPTRT_PTR_MASK                   (0xFFFFFFFFU)
55019 #define PKC_PKC_UPTRT_PTR_SHIFT                  (0U)
55020 /*! PTR - Pointer to start address of PKC FUP table */
55021 #define PKC_PKC_UPTRT_PTR(x)                     (((uint32_t)(((uint32_t)(x)) << PKC_PKC_UPTRT_PTR_SHIFT)) & PKC_PKC_UPTRT_PTR_MASK)
55022 /*! @} */
55023 
55024 /*! @name PKC_ULEN - Universal pointer length */
55025 /*! @{ */
55026 
55027 #define PKC_PKC_ULEN_LEN_MASK                    (0xFFU)
55028 #define PKC_PKC_ULEN_LEN_SHIFT                   (0U)
55029 /*! LEN - Length of universal pointer calculation */
55030 #define PKC_PKC_ULEN_LEN(x)                      (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ULEN_LEN_SHIFT)) & PKC_PKC_ULEN_LEN_MASK)
55031 /*! @} */
55032 
55033 /*! @name PKC_MCDATA - MC pattern data interface */
55034 /*! @{ */
55035 
55036 #define PKC_PKC_MCDATA_MCDATA_MASK               (0xFFFFFFFFU)
55037 #define PKC_PKC_MCDATA_MCDATA_SHIFT              (0U)
55038 /*! MCDATA - Microcode read/write data */
55039 #define PKC_PKC_MCDATA_MCDATA(x)                 (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MCDATA_MCDATA_SHIFT)) & PKC_PKC_MCDATA_MCDATA_MASK)
55040 /*! @} */
55041 
55042 /*! @name PKC_VERSION - PKC version register */
55043 /*! @{ */
55044 
55045 #define PKC_PKC_VERSION_MULSIZE_MASK             (0x3U)
55046 #define PKC_PKC_VERSION_MULSIZE_SHIFT            (0U)
55047 /*! MULSIZE
55048  *  0b01..32-bit multiplier
55049  *  0b10..64-bit multiplier
55050  *  0b11..128-bit multiplier
55051  *  0b10..128-bit multiplier
55052  *  0b01..64-bit multiplier
55053  */
55054 #define PKC_PKC_VERSION_MULSIZE(x)               (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_MULSIZE_SHIFT)) & PKC_PKC_VERSION_MULSIZE_MASK)
55055 
55056 #define PKC_PKC_VERSION_MCAVAIL_MASK             (0x4U)
55057 #define PKC_PKC_VERSION_MCAVAIL_SHIFT            (2U)
55058 #define PKC_PKC_VERSION_MCAVAIL(x)               (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_MCAVAIL_SHIFT)) & PKC_PKC_VERSION_MCAVAIL_MASK)
55059 
55060 #define PKC_PKC_VERSION_UPAVAIL_MASK             (0x8U)
55061 #define PKC_PKC_VERSION_UPAVAIL_SHIFT            (3U)
55062 #define PKC_PKC_VERSION_UPAVAIL(x)               (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_UPAVAIL_SHIFT)) & PKC_PKC_VERSION_UPAVAIL_MASK)
55063 
55064 #define PKC_PKC_VERSION_UPCACHEAVAIL_MASK        (0x10U)
55065 #define PKC_PKC_VERSION_UPCACHEAVAIL_SHIFT       (4U)
55066 #define PKC_PKC_VERSION_UPCACHEAVAIL(x)          (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_UPCACHEAVAIL_SHIFT)) & PKC_PKC_VERSION_UPCACHEAVAIL_MASK)
55067 
55068 #define PKC_PKC_VERSION_GF2AVAIL_MASK            (0x20U)
55069 #define PKC_PKC_VERSION_GF2AVAIL_SHIFT           (5U)
55070 #define PKC_PKC_VERSION_GF2AVAIL(x)              (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_GF2AVAIL_SHIFT)) & PKC_PKC_VERSION_GF2AVAIL_MASK)
55071 
55072 #define PKC_PKC_VERSION_PARAMNUM_MASK            (0xC0U)
55073 #define PKC_PKC_VERSION_PARAMNUM_SHIFT           (6U)
55074 #define PKC_PKC_VERSION_PARAMNUM(x)              (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_PARAMNUM_SHIFT)) & PKC_PKC_VERSION_PARAMNUM_MASK)
55075 
55076 #define PKC_PKC_VERSION_SBX0AVAIL_MASK           (0x100U)
55077 #define PKC_PKC_VERSION_SBX0AVAIL_SHIFT          (8U)
55078 #define PKC_PKC_VERSION_SBX0AVAIL(x)             (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_SBX0AVAIL_SHIFT)) & PKC_PKC_VERSION_SBX0AVAIL_MASK)
55079 
55080 #define PKC_PKC_VERSION_SBX1AVAIL_MASK           (0x200U)
55081 #define PKC_PKC_VERSION_SBX1AVAIL_SHIFT          (9U)
55082 #define PKC_PKC_VERSION_SBX1AVAIL(x)             (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_SBX1AVAIL_SHIFT)) & PKC_PKC_VERSION_SBX1AVAIL_MASK)
55083 
55084 #define PKC_PKC_VERSION_SBX2AVAIL_MASK           (0x400U)
55085 #define PKC_PKC_VERSION_SBX2AVAIL_SHIFT          (10U)
55086 #define PKC_PKC_VERSION_SBX2AVAIL(x)             (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_SBX2AVAIL_SHIFT)) & PKC_PKC_VERSION_SBX2AVAIL_MASK)
55087 
55088 #define PKC_PKC_VERSION_SBX3AVAIL_MASK           (0x800U)
55089 #define PKC_PKC_VERSION_SBX3AVAIL_SHIFT          (11U)
55090 #define PKC_PKC_VERSION_SBX3AVAIL(x)             (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_SBX3AVAIL_SHIFT)) & PKC_PKC_VERSION_SBX3AVAIL_MASK)
55091 
55092 #define PKC_PKC_VERSION_MCRECONF_SIZE_MASK       (0xFF000U)
55093 #define PKC_PKC_VERSION_MCRECONF_SIZE_SHIFT      (12U)
55094 #define PKC_PKC_VERSION_MCRECONF_SIZE(x)         (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_MCRECONF_SIZE_SHIFT)) & PKC_PKC_VERSION_MCRECONF_SIZE_MASK)
55095 /*! @} */
55096 
55097 /*! @name PKC_SOFT_RST - Software reset */
55098 /*! @{ */
55099 
55100 #define PKC_PKC_SOFT_RST_SOFT_RST_MASK           (0x1U)
55101 #define PKC_PKC_SOFT_RST_SOFT_RST_SHIFT          (0U)
55102 #define PKC_PKC_SOFT_RST_SOFT_RST(x)             (((uint32_t)(((uint32_t)(x)) << PKC_PKC_SOFT_RST_SOFT_RST_SHIFT)) & PKC_PKC_SOFT_RST_SOFT_RST_MASK)
55103 /*! @} */
55104 
55105 /*! @name PKC_ACCESS_ERR - Access Error */
55106 /*! @{ */
55107 
55108 #define PKC_PKC_ACCESS_ERR_APB_NOTAV_MASK        (0x1U)
55109 #define PKC_PKC_ACCESS_ERR_APB_NOTAV_SHIFT       (0U)
55110 /*! APB_NOTAV - APB Error */
55111 #define PKC_PKC_ACCESS_ERR_APB_NOTAV(x)          (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_APB_NOTAV_SHIFT)) & PKC_PKC_ACCESS_ERR_APB_NOTAV_MASK)
55112 
55113 #define PKC_PKC_ACCESS_ERR_APB_WRGMD_MASK        (0x2U)
55114 #define PKC_PKC_ACCESS_ERR_APB_WRGMD_SHIFT       (1U)
55115 /*! APB_WRGMD - APB Error */
55116 #define PKC_PKC_ACCESS_ERR_APB_WRGMD(x)          (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_APB_WRGMD_SHIFT)) & PKC_PKC_ACCESS_ERR_APB_WRGMD_MASK)
55117 
55118 #define PKC_PKC_ACCESS_ERR_APB_MASTER_MASK       (0xF0U)
55119 #define PKC_PKC_ACCESS_ERR_APB_MASTER_SHIFT      (4U)
55120 #define PKC_PKC_ACCESS_ERR_APB_MASTER(x)         (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_APB_MASTER_SHIFT)) & PKC_PKC_ACCESS_ERR_APB_MASTER_MASK)
55121 
55122 #define PKC_PKC_ACCESS_ERR_AHB_MASK              (0x400U)
55123 #define PKC_PKC_ACCESS_ERR_AHB_SHIFT             (10U)
55124 /*! AHB - AHB Error */
55125 #define PKC_PKC_ACCESS_ERR_AHB(x)                (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_AHB_SHIFT)) & PKC_PKC_ACCESS_ERR_AHB_MASK)
55126 
55127 #define PKC_PKC_ACCESS_ERR_PKCC_MASK             (0x10000U)
55128 #define PKC_PKC_ACCESS_ERR_PKCC_SHIFT            (16U)
55129 #define PKC_PKC_ACCESS_ERR_PKCC(x)               (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_PKCC_SHIFT)) & PKC_PKC_ACCESS_ERR_PKCC_MASK)
55130 
55131 #define PKC_PKC_ACCESS_ERR_FDET_MASK             (0x20000U)
55132 #define PKC_PKC_ACCESS_ERR_FDET_SHIFT            (17U)
55133 #define PKC_PKC_ACCESS_ERR_FDET(x)               (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_FDET_SHIFT)) & PKC_PKC_ACCESS_ERR_FDET_MASK)
55134 
55135 #define PKC_PKC_ACCESS_ERR_CTRL_MASK             (0x40000U)
55136 #define PKC_PKC_ACCESS_ERR_CTRL_SHIFT            (18U)
55137 #define PKC_PKC_ACCESS_ERR_CTRL(x)               (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_CTRL_SHIFT)) & PKC_PKC_ACCESS_ERR_CTRL_MASK)
55138 
55139 #define PKC_PKC_ACCESS_ERR_UCRC_MASK             (0x80000U)
55140 #define PKC_PKC_ACCESS_ERR_UCRC_SHIFT            (19U)
55141 #define PKC_PKC_ACCESS_ERR_UCRC(x)               (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_UCRC_SHIFT)) & PKC_PKC_ACCESS_ERR_UCRC_MASK)
55142 /*! @} */
55143 
55144 /*! @name PKC_ACCESS_ERR_CLR - Clear Access Error */
55145 /*! @{ */
55146 
55147 #define PKC_PKC_ACCESS_ERR_CLR_ERR_CLR_MASK      (0x1U)
55148 #define PKC_PKC_ACCESS_ERR_CLR_ERR_CLR_SHIFT     (0U)
55149 #define PKC_PKC_ACCESS_ERR_CLR_ERR_CLR(x)        (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_CLR_ERR_CLR_SHIFT)) & PKC_PKC_ACCESS_ERR_CLR_ERR_CLR_MASK)
55150 /*! @} */
55151 
55152 /*! @name PKC_INT_CLR_ENABLE - Interrupt enable clear */
55153 /*! @{ */
55154 
55155 #define PKC_PKC_INT_CLR_ENABLE_EN_PDONE_MASK     (0x1U)
55156 #define PKC_PKC_INT_CLR_ENABLE_EN_PDONE_SHIFT    (0U)
55157 #define PKC_PKC_INT_CLR_ENABLE_EN_PDONE(x)       (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_CLR_ENABLE_EN_PDONE_SHIFT)) & PKC_PKC_INT_CLR_ENABLE_EN_PDONE_MASK)
55158 /*! @} */
55159 
55160 /*! @name PKC_INT_SET_ENABLE - Interrupt enable set */
55161 /*! @{ */
55162 
55163 #define PKC_PKC_INT_SET_ENABLE_EN_PDONE_MASK     (0x1U)
55164 #define PKC_PKC_INT_SET_ENABLE_EN_PDONE_SHIFT    (0U)
55165 #define PKC_PKC_INT_SET_ENABLE_EN_PDONE(x)       (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_SET_ENABLE_EN_PDONE_SHIFT)) & PKC_PKC_INT_SET_ENABLE_EN_PDONE_MASK)
55166 /*! @} */
55167 
55168 /*! @name PKC_INT_STATUS - Interrupt status */
55169 /*! @{ */
55170 
55171 #define PKC_PKC_INT_STATUS_INT_PDONE_MASK        (0x1U)
55172 #define PKC_PKC_INT_STATUS_INT_PDONE_SHIFT       (0U)
55173 /*! INT_PDONE - End-of-computation status flag */
55174 #define PKC_PKC_INT_STATUS_INT_PDONE(x)          (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_STATUS_INT_PDONE_SHIFT)) & PKC_PKC_INT_STATUS_INT_PDONE_MASK)
55175 /*! @} */
55176 
55177 /*! @name PKC_INT_ENABLE - Interrupt enable */
55178 /*! @{ */
55179 
55180 #define PKC_PKC_INT_ENABLE_EN_PDONE_MASK         (0x1U)
55181 #define PKC_PKC_INT_ENABLE_EN_PDONE_SHIFT        (0U)
55182 /*! EN_PDONE - PDONE interrupt enable flag */
55183 #define PKC_PKC_INT_ENABLE_EN_PDONE(x)           (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_ENABLE_EN_PDONE_SHIFT)) & PKC_PKC_INT_ENABLE_EN_PDONE_MASK)
55184 /*! @} */
55185 
55186 /*! @name PKC_INT_CLR_STATUS - Interrupt status clear */
55187 /*! @{ */
55188 
55189 #define PKC_PKC_INT_CLR_STATUS_INT_PDONE_MASK    (0x1U)
55190 #define PKC_PKC_INT_CLR_STATUS_INT_PDONE_SHIFT   (0U)
55191 #define PKC_PKC_INT_CLR_STATUS_INT_PDONE(x)      (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_CLR_STATUS_INT_PDONE_SHIFT)) & PKC_PKC_INT_CLR_STATUS_INT_PDONE_MASK)
55192 /*! @} */
55193 
55194 /*! @name PKC_INT_SET_STATUS - Interrupt status set */
55195 /*! @{ */
55196 
55197 #define PKC_PKC_INT_SET_STATUS_INT_PDONE_MASK    (0x1U)
55198 #define PKC_PKC_INT_SET_STATUS_INT_PDONE_SHIFT   (0U)
55199 #define PKC_PKC_INT_SET_STATUS_INT_PDONE(x)      (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_SET_STATUS_INT_PDONE_SHIFT)) & PKC_PKC_INT_SET_STATUS_INT_PDONE_MASK)
55200 /*! @} */
55201 
55202 /*! @name PKC_MODULE_ID - Module ID */
55203 /*! @{ */
55204 
55205 #define PKC_PKC_MODULE_ID_SIZE_MASK              (0xFFU)
55206 #define PKC_PKC_MODULE_ID_SIZE_SHIFT             (0U)
55207 #define PKC_PKC_MODULE_ID_SIZE(x)                (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODULE_ID_SIZE_SHIFT)) & PKC_PKC_MODULE_ID_SIZE_MASK)
55208 
55209 #define PKC_PKC_MODULE_ID_MINOR_REV_MASK         (0xF00U)
55210 #define PKC_PKC_MODULE_ID_MINOR_REV_SHIFT        (8U)
55211 #define PKC_PKC_MODULE_ID_MINOR_REV(x)           (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODULE_ID_MINOR_REV_SHIFT)) & PKC_PKC_MODULE_ID_MINOR_REV_MASK)
55212 
55213 #define PKC_PKC_MODULE_ID_MAJOR_REV_MASK         (0xF000U)
55214 #define PKC_PKC_MODULE_ID_MAJOR_REV_SHIFT        (12U)
55215 #define PKC_PKC_MODULE_ID_MAJOR_REV(x)           (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODULE_ID_MAJOR_REV_SHIFT)) & PKC_PKC_MODULE_ID_MAJOR_REV_MASK)
55216 
55217 #define PKC_PKC_MODULE_ID_ID_MASK                (0xFFFF0000U)
55218 #define PKC_PKC_MODULE_ID_ID_SHIFT               (16U)
55219 #define PKC_PKC_MODULE_ID_ID(x)                  (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODULE_ID_ID_SHIFT)) & PKC_PKC_MODULE_ID_ID_MASK)
55220 /*! @} */
55221 
55222 
55223 /*!
55224  * @}
55225  */ /* end of group PKC_Register_Masks */
55226 
55227 
55228 /* PKC - Peripheral instance base addresses */
55229 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
55230   /** Peripheral PKC0 base address */
55231   #define PKC0_BASE                                (0x5002B000u)
55232   /** Peripheral PKC0 base address */
55233   #define PKC0_BASE_NS                             (0x4002B000u)
55234   /** Peripheral PKC0 base pointer */
55235   #define PKC0                                     ((PKC_Type *)PKC0_BASE)
55236   /** Peripheral PKC0 base pointer */
55237   #define PKC0_NS                                  ((PKC_Type *)PKC0_BASE_NS)
55238   /** Array initializer of PKC peripheral base addresses */
55239   #define PKC_BASE_ADDRS                           { PKC0_BASE }
55240   /** Array initializer of PKC peripheral base pointers */
55241   #define PKC_BASE_PTRS                            { PKC0 }
55242   /** Array initializer of PKC peripheral base addresses */
55243   #define PKC_BASE_ADDRS_NS                        { PKC0_BASE_NS }
55244   /** Array initializer of PKC peripheral base pointers */
55245   #define PKC_BASE_PTRS_NS                         { PKC0_NS }
55246 #else
55247   /** Peripheral PKC0 base address */
55248   #define PKC0_BASE                                (0x4002B000u)
55249   /** Peripheral PKC0 base pointer */
55250   #define PKC0                                     ((PKC_Type *)PKC0_BASE)
55251   /** Array initializer of PKC peripheral base addresses */
55252   #define PKC_BASE_ADDRS                           { PKC0_BASE }
55253   /** Array initializer of PKC peripheral base pointers */
55254   #define PKC_BASE_PTRS                            { PKC0 }
55255 #endif
55256 
55257 /*!
55258  * @}
55259  */ /* end of group PKC_Peripheral_Access_Layer */
55260 
55261 
55262 /* ----------------------------------------------------------------------------
55263    -- PLU Peripheral Access Layer
55264    ---------------------------------------------------------------------------- */
55265 
55266 /*!
55267  * @addtogroup PLU_Peripheral_Access_Layer PLU Peripheral Access Layer
55268  * @{
55269  */
55270 
55271 /** PLU - Register Layout Typedef */
55272 typedef struct {
55273   struct {                                         /* offset: 0x0, array step: 0x20 */
55274     __IO uint32_t INP_MUX[5];                        /**< Input select register for LUTn (0 to 25), Inputx (5 inputs), array offset: 0x0, array step: index*0x20, index2*0x4 */
55275          uint8_t RESERVED_0[12];
55276   } LUT[26];
55277        uint8_t RESERVED_0[1216];
55278   __IO uint32_t LUT_TRUTH[26];                     /**< PLU LUT truth table, array offset: 0x800, array step: 0x4 */
55279        uint8_t RESERVED_1[152];
55280   __I  uint32_t OUTPUTS;                           /**< PLU outputs, offset: 0x900 */
55281   __IO uint32_t WAKEINT_CTRL;                      /**< Wakeup interrupt control, offset: 0x904 */
55282        uint8_t RESERVED_2[760];
55283   __IO uint32_t OUTPUT_MUX[8];                     /**< PLU output multiplexer, array offset: 0xC00, array step: 0x4 */
55284 } PLU_Type;
55285 
55286 /* ----------------------------------------------------------------------------
55287    -- PLU Register Masks
55288    ---------------------------------------------------------------------------- */
55289 
55290 /*!
55291  * @addtogroup PLU_Register_Masks PLU Register Masks
55292  * @{
55293  */
55294 
55295 /*! @name LUT_INP_MUX - Input select register for LUTn (0 to 25), Inputx (5 inputs) */
55296 /*! @{ */
55297 
55298 #define PLU_LUT_INP_MUX_LUTn_INPx_MASK           (0x3FU)
55299 #define PLU_LUT_INP_MUX_LUTn_INPx_SHIFT          (0U)
55300 /*! LUTn_INPx - Selects the input source to be connected to LUTn_INPx
55301  *  0b000000..PLU primary inputs 0
55302  *  0b000001..PLU primary inputs 1
55303  *  0b000010..PLU primary inputs 2
55304  *  0b000011..PLU primary inputs 3
55305  *  0b000100..PLU primary inputs 4
55306  *  0b000101..PLU primary inputs 5
55307  *  0b000110..Output of LUT0
55308  *  0b000111..Output of LUT1
55309  *  0b001000..Output of LUT2
55310  *  0b001001..Output of LUT3
55311  *  0b001010..Output of LUT4
55312  *  0b001011..Output of LUT5
55313  *  0b001100..Output of LUT6
55314  *  0b001101..Output of LUT7
55315  *  0b001110..Output of LUT8
55316  *  0b001111..Output of LUT9
55317  *  0b010000..Output of LUT10
55318  *  0b010001..Output of LUT11
55319  *  0b010010..Output of LUT12
55320  *  0b010011..Output of LUT13
55321  *  0b010100..Output of LUT14
55322  *  0b010101..Output of LUT15
55323  *  0b010110..Output of LUT16
55324  *  0b010111..Output of LUT17
55325  *  0b011000..Output of LUT18
55326  *  0b011001..Output of LUT19
55327  *  0b011010..Output of LUT20
55328  *  0b011011..Output of LUT21
55329  *  0b011100..Output of LUT22
55330  *  0b011101..Output of LUT23
55331  *  0b011110..Output of LUT24
55332  *  0b011111..Output of LUT25
55333  *  0b100000..State[0]
55334  *  0b100001..State[1]
55335  *  0b100010..State[2]
55336  *  0b100011..State[3]
55337  */
55338 #define PLU_LUT_INP_MUX_LUTn_INPx(x)             (((uint32_t)(((uint32_t)(x)) << PLU_LUT_INP_MUX_LUTn_INPx_SHIFT)) & PLU_LUT_INP_MUX_LUTn_INPx_MASK)
55339 /*! @} */
55340 
55341 /* The count of PLU_LUT_INP_MUX */
55342 #define PLU_LUT_INP_MUX_COUNT                    (26U)
55343 
55344 /* The count of PLU_LUT_INP_MUX */
55345 #define PLU_LUT_INP_MUX_COUNT2                   (5U)
55346 
55347 /*! @name LUT_TRUTH - PLU LUT truth table */
55348 /*! @{ */
55349 
55350 #define PLU_LUT_TRUTH_LUT_TRUTH_MASK             (0xFFFFFFFFU)
55351 #define PLU_LUT_TRUTH_LUT_TRUTH_SHIFT            (0U)
55352 /*! LUT_TRUTH - LUT truth table */
55353 #define PLU_LUT_TRUTH_LUT_TRUTH(x)               (((uint32_t)(((uint32_t)(x)) << PLU_LUT_TRUTH_LUT_TRUTH_SHIFT)) & PLU_LUT_TRUTH_LUT_TRUTH_MASK)
55354 /*! @} */
55355 
55356 /* The count of PLU_LUT_TRUTH */
55357 #define PLU_LUT_TRUTH_COUNT                      (26U)
55358 
55359 /*! @name OUTPUTS - PLU outputs */
55360 /*! @{ */
55361 
55362 #define PLU_OUTPUTS_OUTPUT_STATE_MASK            (0xFFU)
55363 #define PLU_OUTPUTS_OUTPUT_STATE_SHIFT           (0U)
55364 /*! OUTPUT_STATE - Output state */
55365 #define PLU_OUTPUTS_OUTPUT_STATE(x)              (((uint32_t)(((uint32_t)(x)) << PLU_OUTPUTS_OUTPUT_STATE_SHIFT)) & PLU_OUTPUTS_OUTPUT_STATE_MASK)
55366 /*! @} */
55367 
55368 /*! @name WAKEINT_CTRL - Wakeup interrupt control */
55369 /*! @{ */
55370 
55371 #define PLU_WAKEINT_CTRL_MASK_MASK               (0xFFU)
55372 #define PLU_WAKEINT_CTRL_MASK_SHIFT              (0U)
55373 /*! MASK - Interrupt mask */
55374 #define PLU_WAKEINT_CTRL_MASK(x)                 (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_MASK_SHIFT)) & PLU_WAKEINT_CTRL_MASK_MASK)
55375 
55376 #define PLU_WAKEINT_CTRL_FILTER_MODE_MASK        (0x300U)
55377 #define PLU_WAKEINT_CTRL_FILTER_MODE_SHIFT       (8U)
55378 /*! FILTER_MODE - Filter Mode
55379  *  0b00..Bypass mode
55380  *  0b01..Filter 1 clock period
55381  *  0b10..Filter 2 clock period
55382  *  0b11..Filter 3 clock period
55383  */
55384 #define PLU_WAKEINT_CTRL_FILTER_MODE(x)          (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_FILTER_MODE_SHIFT)) & PLU_WAKEINT_CTRL_FILTER_MODE_MASK)
55385 
55386 #define PLU_WAKEINT_CTRL_FILTER_CLKSEL_MASK      (0xC00U)
55387 #define PLU_WAKEINT_CTRL_FILTER_CLKSEL_SHIFT     (10U)
55388 /*! FILTER_CLKSEL - Filter clock select
55389  *  0b00..Selects the 1 MHz low-power oscillator as the filter clock.
55390  *  0b01..Selects the 12 MHz FRO as the filter clock.
55391  *  0b10..Reserved
55392  *  0b11..Reserved
55393  */
55394 #define PLU_WAKEINT_CTRL_FILTER_CLKSEL(x)        (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_FILTER_CLKSEL_SHIFT)) & PLU_WAKEINT_CTRL_FILTER_CLKSEL_MASK)
55395 
55396 #define PLU_WAKEINT_CTRL_LATCH_ENABLE_MASK       (0x1000U)
55397 #define PLU_WAKEINT_CTRL_LATCH_ENABLE_SHIFT      (12U)
55398 /*! LATCH_ENABLE - Latch the interrupt */
55399 #define PLU_WAKEINT_CTRL_LATCH_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_LATCH_ENABLE_SHIFT)) & PLU_WAKEINT_CTRL_LATCH_ENABLE_MASK)
55400 
55401 #define PLU_WAKEINT_CTRL_INTR_CLEAR_MASK         (0x2000U)
55402 #define PLU_WAKEINT_CTRL_INTR_CLEAR_SHIFT        (13U)
55403 /*! INTR_CLEAR - Write to clear wakeint_latched */
55404 #define PLU_WAKEINT_CTRL_INTR_CLEAR(x)           (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_INTR_CLEAR_SHIFT)) & PLU_WAKEINT_CTRL_INTR_CLEAR_MASK)
55405 /*! @} */
55406 
55407 /*! @name OUTPUT_MUX - PLU output multiplexer */
55408 /*! @{ */
55409 
55410 #define PLU_OUTPUT_MUX_OUTPUT_MASK               (0x1FU)
55411 #define PLU_OUTPUT_MUX_OUTPUT_SHIFT              (0U)
55412 /*! OUTPUT - Selects the source to be connected to PLU output n.
55413  *  0b00000..LUT output 0
55414  *  0b00001..LUT output 1
55415  *  0b00010..LUT output 2
55416  *  0b00011..LUT output 3
55417  *  0b00100..LUT output 4
55418  *  0b00101..LUT output 5
55419  *  0b00110..LUT output 6
55420  *  0b00111..LUT output 7
55421  *  0b01000..LUT output 8
55422  *  0b01001..LUT output 9
55423  *  0b01010..LUT output 10
55424  *  0b01011..LUT output 11
55425  *  0b01100..LUT output 12
55426  *  0b01101..LUT output 13
55427  *  0b01110..LUT output 14
55428  *  0b01111..LUT output 15
55429  *  0b10000..LUT output 16
55430  *  0b10001..LUT output 17
55431  *  0b10010..LUT output 18
55432  *  0b10011..LUT output 19
55433  *  0b10100..LUT output 20
55434  *  0b10101..LUT output 21
55435  *  0b10110..LUT output 22
55436  *  0b10111..LUT output 23
55437  *  0b11000..LUT output 24
55438  *  0b11001..LUT output 25
55439  *  0b11010..State[0]
55440  *  0b11011..State[1]
55441  *  0b11100..State[2]
55442  *  0b11101..State[3]
55443  */
55444 #define PLU_OUTPUT_MUX_OUTPUT(x)                 (((uint32_t)(((uint32_t)(x)) << PLU_OUTPUT_MUX_OUTPUT_SHIFT)) & PLU_OUTPUT_MUX_OUTPUT_MASK)
55445 /*! @} */
55446 
55447 /* The count of PLU_OUTPUT_MUX */
55448 #define PLU_OUTPUT_MUX_COUNT                     (8U)
55449 
55450 
55451 /*!
55452  * @}
55453  */ /* end of group PLU_Register_Masks */
55454 
55455 
55456 /* PLU - Peripheral instance base addresses */
55457 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
55458   /** Peripheral PLU0 base address */
55459   #define PLU0_BASE                                (0x50034000u)
55460   /** Peripheral PLU0 base address */
55461   #define PLU0_BASE_NS                             (0x40034000u)
55462   /** Peripheral PLU0 base pointer */
55463   #define PLU0                                     ((PLU_Type *)PLU0_BASE)
55464   /** Peripheral PLU0 base pointer */
55465   #define PLU0_NS                                  ((PLU_Type *)PLU0_BASE_NS)
55466   /** Array initializer of PLU peripheral base addresses */
55467   #define PLU_BASE_ADDRS                           { PLU0_BASE }
55468   /** Array initializer of PLU peripheral base pointers */
55469   #define PLU_BASE_PTRS                            { PLU0 }
55470   /** Array initializer of PLU peripheral base addresses */
55471   #define PLU_BASE_ADDRS_NS                        { PLU0_BASE_NS }
55472   /** Array initializer of PLU peripheral base pointers */
55473   #define PLU_BASE_PTRS_NS                         { PLU0_NS }
55474 #else
55475   /** Peripheral PLU0 base address */
55476   #define PLU0_BASE                                (0x40034000u)
55477   /** Peripheral PLU0 base pointer */
55478   #define PLU0                                     ((PLU_Type *)PLU0_BASE)
55479   /** Array initializer of PLU peripheral base addresses */
55480   #define PLU_BASE_ADDRS                           { PLU0_BASE }
55481   /** Array initializer of PLU peripheral base pointers */
55482   #define PLU_BASE_PTRS                            { PLU0 }
55483 #endif
55484 /* Backward compatibility */
55485 #define PLU                               PLU0
55486 
55487 
55488 /*!
55489  * @}
55490  */ /* end of group PLU_Peripheral_Access_Layer */
55491 
55492 
55493 /* ----------------------------------------------------------------------------
55494    -- PORT Peripheral Access Layer
55495    ---------------------------------------------------------------------------- */
55496 
55497 /*!
55498  * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
55499  * @{
55500  */
55501 
55502 /** PORT - Register Layout Typedef */
55503 typedef struct {
55504   __I  uint32_t VERID;                             /**< Version ID, offset: 0x0 */
55505        uint8_t RESERVED_0[12];
55506   __O  uint32_t GPCLR;                             /**< Global Pin Control Low, offset: 0x10 */
55507   __O  uint32_t GPCHR;                             /**< Global Pin Control High, offset: 0x14 */
55508        uint8_t RESERVED_1[8];
55509   __IO uint32_t CONFIG;                            /**< Configuration, offset: 0x20 */
55510        uint8_t RESERVED_2[28];
55511   __I  uint32_t EDFR;                              /**< EFT Detect Flag, offset: 0x40 */
55512   __IO uint32_t EDIER;                             /**< EFT Detect Interrupt Enable, offset: 0x44 */
55513   __IO uint32_t EDCR;                              /**< EFT Detect Clear, offset: 0x48 */
55514        uint8_t RESERVED_3[20];
55515   __IO uint32_t CALIB0;                            /**< Calibration 0, offset: 0x60, available only on: PORT0, PORT1, PORT2, PORT3 (missing on PORT4, PORT5) */
55516   __IO uint32_t CALIB1;                            /**< Calibration 1, offset: 0x64, available only on: PORT0, PORT1, PORT2, PORT3 (missing on PORT4, PORT5) */
55517        uint8_t RESERVED_4[24];
55518   __IO uint32_t PCR[32];                           /**< Pin Control 0..Pin Control 31, array offset: 0x80, array step: 0x4, irregular array, not all indices are valid */
55519 } PORT_Type;
55520 
55521 /* ----------------------------------------------------------------------------
55522    -- PORT Register Masks
55523    ---------------------------------------------------------------------------- */
55524 
55525 /*!
55526  * @addtogroup PORT_Register_Masks PORT Register Masks
55527  * @{
55528  */
55529 
55530 /*! @name VERID - Version ID */
55531 /*! @{ */
55532 
55533 #define PORT_VERID_FEATURE_MASK                  (0xFFFFU)
55534 #define PORT_VERID_FEATURE_SHIFT                 (0U)
55535 /*! FEATURE - Feature Specification Number
55536  *  0b0000000000000000..Basic implementation
55537  */
55538 #define PORT_VERID_FEATURE(x)                    (((uint32_t)(((uint32_t)(x)) << PORT_VERID_FEATURE_SHIFT)) & PORT_VERID_FEATURE_MASK)
55539 
55540 #define PORT_VERID_MINOR_MASK                    (0xFF0000U)
55541 #define PORT_VERID_MINOR_SHIFT                   (16U)
55542 /*! MINOR - Minor Version Number */
55543 #define PORT_VERID_MINOR(x)                      (((uint32_t)(((uint32_t)(x)) << PORT_VERID_MINOR_SHIFT)) & PORT_VERID_MINOR_MASK)
55544 
55545 #define PORT_VERID_MAJOR_MASK                    (0xFF000000U)
55546 #define PORT_VERID_MAJOR_SHIFT                   (24U)
55547 /*! MAJOR - Major Version Number */
55548 #define PORT_VERID_MAJOR(x)                      (((uint32_t)(((uint32_t)(x)) << PORT_VERID_MAJOR_SHIFT)) & PORT_VERID_MAJOR_MASK)
55549 /*! @} */
55550 
55551 /*! @name GPCLR - Global Pin Control Low */
55552 /*! @{ */
55553 
55554 #define PORT_GPCLR_GPWD_MASK                     (0xFFFFU)
55555 #define PORT_GPCLR_GPWD_SHIFT                    (0U)
55556 /*! GPWD - Global Pin Write Data */
55557 #define PORT_GPCLR_GPWD(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWD_SHIFT)) & PORT_GPCLR_GPWD_MASK)
55558 
55559 #define PORT_GPCLR_GPWE0_MASK                    (0x10000U)
55560 #define PORT_GPCLR_GPWE0_SHIFT                   (16U)
55561 /*! GPWE0 - Global Pin Write Enable
55562  *  0b0..Not updated
55563  *  0b1..Updated
55564  */
55565 #define PORT_GPCLR_GPWE0(x)                      (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE0_SHIFT)) & PORT_GPCLR_GPWE0_MASK)
55566 
55567 #define PORT_GPCLR_GPWE1_MASK                    (0x20000U)
55568 #define PORT_GPCLR_GPWE1_SHIFT                   (17U)
55569 /*! GPWE1 - Global Pin Write Enable
55570  *  0b0..Not updated
55571  *  0b1..Updated
55572  */
55573 #define PORT_GPCLR_GPWE1(x)                      (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE1_SHIFT)) & PORT_GPCLR_GPWE1_MASK)
55574 
55575 #define PORT_GPCLR_GPWE2_MASK                    (0x40000U)
55576 #define PORT_GPCLR_GPWE2_SHIFT                   (18U)
55577 /*! GPWE2 - Global Pin Write Enable
55578  *  0b0..Not updated
55579  *  0b1..Updated
55580  */
55581 #define PORT_GPCLR_GPWE2(x)                      (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE2_SHIFT)) & PORT_GPCLR_GPWE2_MASK)
55582 
55583 #define PORT_GPCLR_GPWE3_MASK                    (0x80000U)
55584 #define PORT_GPCLR_GPWE3_SHIFT                   (19U)
55585 /*! GPWE3 - Global Pin Write Enable
55586  *  0b0..Not updated
55587  *  0b1..Updated
55588  */
55589 #define PORT_GPCLR_GPWE3(x)                      (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE3_SHIFT)) & PORT_GPCLR_GPWE3_MASK)
55590 
55591 #define PORT_GPCLR_GPWE4_MASK                    (0x100000U)
55592 #define PORT_GPCLR_GPWE4_SHIFT                   (20U)
55593 /*! GPWE4 - Global Pin Write Enable
55594  *  0b0..Not updated
55595  *  0b1..Updated
55596  */
55597 #define PORT_GPCLR_GPWE4(x)                      (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE4_SHIFT)) & PORT_GPCLR_GPWE4_MASK)
55598 
55599 #define PORT_GPCLR_GPWE5_MASK                    (0x200000U)
55600 #define PORT_GPCLR_GPWE5_SHIFT                   (21U)
55601 /*! GPWE5 - Global Pin Write Enable
55602  *  0b0..Not updated
55603  *  0b1..Updated
55604  */
55605 #define PORT_GPCLR_GPWE5(x)                      (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE5_SHIFT)) & PORT_GPCLR_GPWE5_MASK)
55606 
55607 #define PORT_GPCLR_GPWE6_MASK                    (0x400000U)
55608 #define PORT_GPCLR_GPWE6_SHIFT                   (22U)
55609 /*! GPWE6 - Global Pin Write Enable
55610  *  0b0..Not updated
55611  *  0b1..Updated
55612  */
55613 #define PORT_GPCLR_GPWE6(x)                      (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE6_SHIFT)) & PORT_GPCLR_GPWE6_MASK)
55614 
55615 #define PORT_GPCLR_GPWE7_MASK                    (0x800000U)
55616 #define PORT_GPCLR_GPWE7_SHIFT                   (23U)
55617 /*! GPWE7 - Global Pin Write Enable
55618  *  0b0..Not updated
55619  *  0b1..Updated
55620  */
55621 #define PORT_GPCLR_GPWE7(x)                      (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE7_SHIFT)) & PORT_GPCLR_GPWE7_MASK)
55622 
55623 #define PORT_GPCLR_GPWE8_MASK                    (0x1000000U)
55624 #define PORT_GPCLR_GPWE8_SHIFT                   (24U)
55625 /*! GPWE8 - Global Pin Write Enable
55626  *  0b0..Not updated
55627  *  0b1..Updated
55628  */
55629 #define PORT_GPCLR_GPWE8(x)                      (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE8_SHIFT)) & PORT_GPCLR_GPWE8_MASK)
55630 
55631 #define PORT_GPCLR_GPWE9_MASK                    (0x2000000U)
55632 #define PORT_GPCLR_GPWE9_SHIFT                   (25U)
55633 /*! GPWE9 - Global Pin Write Enable
55634  *  0b0..Not updated
55635  *  0b1..Updated
55636  */
55637 #define PORT_GPCLR_GPWE9(x)                      (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE9_SHIFT)) & PORT_GPCLR_GPWE9_MASK)
55638 
55639 #define PORT_GPCLR_GPWE10_MASK                   (0x4000000U)
55640 #define PORT_GPCLR_GPWE10_SHIFT                  (26U)
55641 /*! GPWE10 - Global Pin Write Enable
55642  *  0b0..Not updated
55643  *  0b1..Updated
55644  */
55645 #define PORT_GPCLR_GPWE10(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE10_SHIFT)) & PORT_GPCLR_GPWE10_MASK)
55646 
55647 #define PORT_GPCLR_GPWE11_MASK                   (0x8000000U)
55648 #define PORT_GPCLR_GPWE11_SHIFT                  (27U)
55649 /*! GPWE11 - Global Pin Write Enable
55650  *  0b0..Not updated
55651  *  0b1..Updated
55652  */
55653 #define PORT_GPCLR_GPWE11(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE11_SHIFT)) & PORT_GPCLR_GPWE11_MASK)
55654 
55655 #define PORT_GPCLR_GPWE12_MASK                   (0x10000000U)
55656 #define PORT_GPCLR_GPWE12_SHIFT                  (28U)
55657 /*! GPWE12 - Global Pin Write Enable
55658  *  0b0..Not updated
55659  *  0b1..Updated
55660  */
55661 #define PORT_GPCLR_GPWE12(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE12_SHIFT)) & PORT_GPCLR_GPWE12_MASK)
55662 
55663 #define PORT_GPCLR_GPWE13_MASK                   (0x20000000U)
55664 #define PORT_GPCLR_GPWE13_SHIFT                  (29U)
55665 /*! GPWE13 - Global Pin Write Enable
55666  *  0b0..Not updated
55667  *  0b1..Updated
55668  */
55669 #define PORT_GPCLR_GPWE13(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE13_SHIFT)) & PORT_GPCLR_GPWE13_MASK)
55670 
55671 #define PORT_GPCLR_GPWE14_MASK                   (0x40000000U)
55672 #define PORT_GPCLR_GPWE14_SHIFT                  (30U)
55673 /*! GPWE14 - Global Pin Write Enable
55674  *  0b0..Not updated
55675  *  0b1..Updated
55676  */
55677 #define PORT_GPCLR_GPWE14(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE14_SHIFT)) & PORT_GPCLR_GPWE14_MASK)
55678 
55679 #define PORT_GPCLR_GPWE15_MASK                   (0x80000000U)
55680 #define PORT_GPCLR_GPWE15_SHIFT                  (31U)
55681 /*! GPWE15 - Global Pin Write Enable
55682  *  0b0..Not updated
55683  *  0b1..Updated
55684  */
55685 #define PORT_GPCLR_GPWE15(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE15_SHIFT)) & PORT_GPCLR_GPWE15_MASK)
55686 /*! @} */
55687 
55688 /*! @name GPCHR - Global Pin Control High */
55689 /*! @{ */
55690 
55691 #define PORT_GPCHR_GPWD_MASK                     (0xFFFFU)
55692 #define PORT_GPCHR_GPWD_SHIFT                    (0U)
55693 /*! GPWD - Global Pin Write Data */
55694 #define PORT_GPCHR_GPWD(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWD_SHIFT)) & PORT_GPCHR_GPWD_MASK)
55695 
55696 #define PORT_GPCHR_GPWE16_MASK                   (0x10000U)
55697 #define PORT_GPCHR_GPWE16_SHIFT                  (16U)
55698 /*! GPWE16 - Global Pin Write Enable
55699  *  0b0..Not updated
55700  *  0b1..Updated
55701  */
55702 #define PORT_GPCHR_GPWE16(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE16_SHIFT)) & PORT_GPCHR_GPWE16_MASK)
55703 
55704 #define PORT_GPCHR_GPWE17_MASK                   (0x20000U)
55705 #define PORT_GPCHR_GPWE17_SHIFT                  (17U)
55706 /*! GPWE17 - Global Pin Write Enable
55707  *  0b0..Not updated
55708  *  0b1..Updated
55709  */
55710 #define PORT_GPCHR_GPWE17(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE17_SHIFT)) & PORT_GPCHR_GPWE17_MASK)
55711 
55712 #define PORT_GPCHR_GPWE18_MASK                   (0x40000U)
55713 #define PORT_GPCHR_GPWE18_SHIFT                  (18U)
55714 /*! GPWE18 - Global Pin Write Enable
55715  *  0b0..Not updated
55716  *  0b1..Updated
55717  */
55718 #define PORT_GPCHR_GPWE18(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE18_SHIFT)) & PORT_GPCHR_GPWE18_MASK)
55719 
55720 #define PORT_GPCHR_GPWE19_MASK                   (0x80000U)
55721 #define PORT_GPCHR_GPWE19_SHIFT                  (19U)
55722 /*! GPWE19 - Global Pin Write Enable
55723  *  0b0..Not updated
55724  *  0b1..Updated
55725  */
55726 #define PORT_GPCHR_GPWE19(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE19_SHIFT)) & PORT_GPCHR_GPWE19_MASK)
55727 
55728 #define PORT_GPCHR_GPWE20_MASK                   (0x100000U)
55729 #define PORT_GPCHR_GPWE20_SHIFT                  (20U)
55730 /*! GPWE20 - Global Pin Write Enable
55731  *  0b0..Not updated
55732  *  0b1..Updated
55733  */
55734 #define PORT_GPCHR_GPWE20(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE20_SHIFT)) & PORT_GPCHR_GPWE20_MASK)
55735 
55736 #define PORT_GPCHR_GPWE21_MASK                   (0x200000U)
55737 #define PORT_GPCHR_GPWE21_SHIFT                  (21U)
55738 /*! GPWE21 - Global Pin Write Enable
55739  *  0b0..Not updated
55740  *  0b1..Updated
55741  */
55742 #define PORT_GPCHR_GPWE21(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE21_SHIFT)) & PORT_GPCHR_GPWE21_MASK)
55743 
55744 #define PORT_GPCHR_GPWE22_MASK                   (0x400000U)
55745 #define PORT_GPCHR_GPWE22_SHIFT                  (22U)
55746 /*! GPWE22 - Global Pin Write Enable
55747  *  0b0..Not updated
55748  *  0b1..Updated
55749  */
55750 #define PORT_GPCHR_GPWE22(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE22_SHIFT)) & PORT_GPCHR_GPWE22_MASK)
55751 
55752 #define PORT_GPCHR_GPWE23_MASK                   (0x800000U)
55753 #define PORT_GPCHR_GPWE23_SHIFT                  (23U)
55754 /*! GPWE23 - Global Pin Write Enable
55755  *  0b0..Not updated
55756  *  0b1..Updated
55757  */
55758 #define PORT_GPCHR_GPWE23(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE23_SHIFT)) & PORT_GPCHR_GPWE23_MASK)
55759 
55760 #define PORT_GPCHR_GPWE24_MASK                   (0x1000000U)
55761 #define PORT_GPCHR_GPWE24_SHIFT                  (24U)
55762 /*! GPWE24 - Global Pin Write Enable
55763  *  0b0..Not updated
55764  *  0b1..Updated
55765  */
55766 #define PORT_GPCHR_GPWE24(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE24_SHIFT)) & PORT_GPCHR_GPWE24_MASK)
55767 
55768 #define PORT_GPCHR_GPWE25_MASK                   (0x2000000U)
55769 #define PORT_GPCHR_GPWE25_SHIFT                  (25U)
55770 /*! GPWE25 - Global Pin Write Enable
55771  *  0b0..Not updated
55772  *  0b1..Updated
55773  */
55774 #define PORT_GPCHR_GPWE25(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE25_SHIFT)) & PORT_GPCHR_GPWE25_MASK)
55775 
55776 #define PORT_GPCHR_GPWE26_MASK                   (0x4000000U)
55777 #define PORT_GPCHR_GPWE26_SHIFT                  (26U)
55778 /*! GPWE26 - Global Pin Write Enable
55779  *  0b0..Not updated
55780  *  0b1..Updated
55781  */
55782 #define PORT_GPCHR_GPWE26(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE26_SHIFT)) & PORT_GPCHR_GPWE26_MASK)
55783 
55784 #define PORT_GPCHR_GPWE27_MASK                   (0x8000000U)
55785 #define PORT_GPCHR_GPWE27_SHIFT                  (27U)
55786 /*! GPWE27 - Global Pin Write Enable
55787  *  0b0..Not updated
55788  *  0b1..Updated
55789  */
55790 #define PORT_GPCHR_GPWE27(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE27_SHIFT)) & PORT_GPCHR_GPWE27_MASK)
55791 
55792 #define PORT_GPCHR_GPWE28_MASK                   (0x10000000U)
55793 #define PORT_GPCHR_GPWE28_SHIFT                  (28U)
55794 /*! GPWE28 - Global Pin Write Enable
55795  *  0b0..Not updated
55796  *  0b1..Updated
55797  */
55798 #define PORT_GPCHR_GPWE28(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE28_SHIFT)) & PORT_GPCHR_GPWE28_MASK)
55799 
55800 #define PORT_GPCHR_GPWE29_MASK                   (0x20000000U)
55801 #define PORT_GPCHR_GPWE29_SHIFT                  (29U)
55802 /*! GPWE29 - Global Pin Write Enable
55803  *  0b0..Not updated
55804  *  0b1..Updated
55805  */
55806 #define PORT_GPCHR_GPWE29(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE29_SHIFT)) & PORT_GPCHR_GPWE29_MASK)
55807 
55808 #define PORT_GPCHR_GPWE30_MASK                   (0x40000000U)
55809 #define PORT_GPCHR_GPWE30_SHIFT                  (30U)
55810 /*! GPWE30 - Global Pin Write Enable
55811  *  0b0..Not updated
55812  *  0b1..Updated
55813  */
55814 #define PORT_GPCHR_GPWE30(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE30_SHIFT)) & PORT_GPCHR_GPWE30_MASK)
55815 
55816 #define PORT_GPCHR_GPWE31_MASK                   (0x80000000U)
55817 #define PORT_GPCHR_GPWE31_SHIFT                  (31U)
55818 /*! GPWE31 - Global Pin Write Enable
55819  *  0b0..Not updated
55820  *  0b1..Updated
55821  */
55822 #define PORT_GPCHR_GPWE31(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE31_SHIFT)) & PORT_GPCHR_GPWE31_MASK)
55823 /*! @} */
55824 
55825 /*! @name CONFIG - Configuration */
55826 /*! @{ */
55827 
55828 #define PORT_CONFIG_RANGE_MASK                   (0x1U)
55829 #define PORT_CONFIG_RANGE_SHIFT                  (0U)
55830 /*! RANGE - Port Voltage Range
55831  *  0b0..1.71 V-3.6 V
55832  *  0b1..2.70 V-3.6 V
55833  */
55834 #define PORT_CONFIG_RANGE(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_CONFIG_RANGE_SHIFT)) & PORT_CONFIG_RANGE_MASK)
55835 /*! @} */
55836 
55837 /*! @name EDFR - EFT Detect Flag */
55838 /*! @{ */
55839 
55840 #define PORT_EDFR_EDF0_MASK                      (0x1U)
55841 #define PORT_EDFR_EDF0_SHIFT                     (0U)
55842 /*! EDF0 - EFT Detect Flag
55843  *  0b0..No EFT event detected
55844  *  0b1..High or/and low EFT event detected
55845  */
55846 #define PORT_EDFR_EDF0(x)                        (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF0_SHIFT)) & PORT_EDFR_EDF0_MASK)
55847 
55848 #define PORT_EDFR_EDF1_MASK                      (0x2U)
55849 #define PORT_EDFR_EDF1_SHIFT                     (1U)
55850 /*! EDF1 - EFT Detect Flag
55851  *  0b0..No EFT event detected
55852  *  0b1..High or/and low EFT event detected
55853  */
55854 #define PORT_EDFR_EDF1(x)                        (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF1_SHIFT)) & PORT_EDFR_EDF1_MASK)
55855 
55856 #define PORT_EDFR_EDF2_MASK                      (0x4U)
55857 #define PORT_EDFR_EDF2_SHIFT                     (2U)
55858 /*! EDF2 - EFT Detect Flag
55859  *  0b0..No EFT event detected
55860  *  0b1..High or/and low EFT event detected
55861  */
55862 #define PORT_EDFR_EDF2(x)                        (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF2_SHIFT)) & PORT_EDFR_EDF2_MASK)
55863 
55864 #define PORT_EDFR_EDF3_MASK                      (0x8U)
55865 #define PORT_EDFR_EDF3_SHIFT                     (3U)
55866 /*! EDF3 - EFT Detect Flag
55867  *  0b0..No EFT event detected
55868  *  0b1..High or/and low EFT event detected
55869  */
55870 #define PORT_EDFR_EDF3(x)                        (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF3_SHIFT)) & PORT_EDFR_EDF3_MASK)
55871 
55872 #define PORT_EDFR_EDF4_MASK                      (0x10U)
55873 #define PORT_EDFR_EDF4_SHIFT                     (4U)
55874 /*! EDF4 - EFT Detect Flag
55875  *  0b0..No EFT event detected
55876  *  0b1..High or/and low EFT event detected
55877  */
55878 #define PORT_EDFR_EDF4(x)                        (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF4_SHIFT)) & PORT_EDFR_EDF4_MASK)
55879 
55880 #define PORT_EDFR_EDF5_MASK                      (0x20U)
55881 #define PORT_EDFR_EDF5_SHIFT                     (5U)
55882 /*! EDF5 - EFT Detect Flag
55883  *  0b0..No EFT event detected
55884  *  0b1..High or/and low EFT event detected
55885  */
55886 #define PORT_EDFR_EDF5(x)                        (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF5_SHIFT)) & PORT_EDFR_EDF5_MASK)
55887 
55888 #define PORT_EDFR_EDF6_MASK                      (0x40U)
55889 #define PORT_EDFR_EDF6_SHIFT                     (6U)
55890 /*! EDF6 - EFT Detect Flag
55891  *  0b0..No EFT event detected
55892  *  0b1..High or/and low EFT event detected
55893  */
55894 #define PORT_EDFR_EDF6(x)                        (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF6_SHIFT)) & PORT_EDFR_EDF6_MASK)
55895 
55896 #define PORT_EDFR_EDF7_MASK                      (0x80U)
55897 #define PORT_EDFR_EDF7_SHIFT                     (7U)
55898 /*! EDF7 - EFT Detect Flag
55899  *  0b0..No EFT event detected
55900  *  0b1..High or/and low EFT event detected
55901  */
55902 #define PORT_EDFR_EDF7(x)                        (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF7_SHIFT)) & PORT_EDFR_EDF7_MASK)
55903 
55904 #define PORT_EDFR_EDF8_MASK                      (0x100U)
55905 #define PORT_EDFR_EDF8_SHIFT                     (8U)
55906 /*! EDF8 - EFT Detect Flag
55907  *  0b0..No EFT event detected
55908  *  0b1..High or/and low EFT event detected
55909  */
55910 #define PORT_EDFR_EDF8(x)                        (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF8_SHIFT)) & PORT_EDFR_EDF8_MASK)
55911 
55912 #define PORT_EDFR_EDF9_MASK                      (0x200U)
55913 #define PORT_EDFR_EDF9_SHIFT                     (9U)
55914 /*! EDF9 - EFT Detect Flag
55915  *  0b0..No EFT event detected
55916  *  0b1..High or/and low EFT event detected
55917  */
55918 #define PORT_EDFR_EDF9(x)                        (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF9_SHIFT)) & PORT_EDFR_EDF9_MASK)
55919 
55920 #define PORT_EDFR_EDF10_MASK                     (0x400U)
55921 #define PORT_EDFR_EDF10_SHIFT                    (10U)
55922 /*! EDF10 - EFT Detect Flag
55923  *  0b0..No EFT event detected
55924  *  0b1..High or/and low EFT event detected
55925  */
55926 #define PORT_EDFR_EDF10(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF10_SHIFT)) & PORT_EDFR_EDF10_MASK)
55927 
55928 #define PORT_EDFR_EDF11_MASK                     (0x800U)
55929 #define PORT_EDFR_EDF11_SHIFT                    (11U)
55930 /*! EDF11 - EFT Detect Flag
55931  *  0b0..No EFT event detected
55932  *  0b1..High or/and low EFT event detected
55933  */
55934 #define PORT_EDFR_EDF11(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF11_SHIFT)) & PORT_EDFR_EDF11_MASK)
55935 
55936 #define PORT_EDFR_EDF12_MASK                     (0x1000U)
55937 #define PORT_EDFR_EDF12_SHIFT                    (12U)
55938 /*! EDF12 - EFT Detect Flag
55939  *  0b0..No EFT event detected
55940  *  0b1..High or/and low EFT event detected
55941  */
55942 #define PORT_EDFR_EDF12(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF12_SHIFT)) & PORT_EDFR_EDF12_MASK)
55943 
55944 #define PORT_EDFR_EDF13_MASK                     (0x2000U)
55945 #define PORT_EDFR_EDF13_SHIFT                    (13U)
55946 /*! EDF13 - EFT Detect Flag
55947  *  0b0..No EFT event detected
55948  *  0b1..High or/and low EFT event detected
55949  */
55950 #define PORT_EDFR_EDF13(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF13_SHIFT)) & PORT_EDFR_EDF13_MASK)
55951 
55952 #define PORT_EDFR_EDF14_MASK                     (0x4000U)
55953 #define PORT_EDFR_EDF14_SHIFT                    (14U)
55954 /*! EDF14 - EFT Detect Flag
55955  *  0b0..No EFT event detected
55956  *  0b1..High or/and low EFT event detected
55957  */
55958 #define PORT_EDFR_EDF14(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF14_SHIFT)) & PORT_EDFR_EDF14_MASK)
55959 
55960 #define PORT_EDFR_EDF15_MASK                     (0x8000U)
55961 #define PORT_EDFR_EDF15_SHIFT                    (15U)
55962 /*! EDF15 - EFT Detect Flag
55963  *  0b0..No EFT event detected
55964  *  0b1..High or/and low EFT event detected
55965  */
55966 #define PORT_EDFR_EDF15(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF15_SHIFT)) & PORT_EDFR_EDF15_MASK)
55967 
55968 #define PORT_EDFR_EDF16_MASK                     (0x10000U)
55969 #define PORT_EDFR_EDF16_SHIFT                    (16U)
55970 /*! EDF16 - EFT Detect Flag
55971  *  0b0..No EFT event detected
55972  *  0b1..High or/and low EFT event detected
55973  */
55974 #define PORT_EDFR_EDF16(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF16_SHIFT)) & PORT_EDFR_EDF16_MASK)
55975 
55976 #define PORT_EDFR_EDF17_MASK                     (0x20000U)
55977 #define PORT_EDFR_EDF17_SHIFT                    (17U)
55978 /*! EDF17 - EFT Detect Flag
55979  *  0b0..No EFT event detected
55980  *  0b1..High or/and low EFT event detected
55981  */
55982 #define PORT_EDFR_EDF17(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF17_SHIFT)) & PORT_EDFR_EDF17_MASK)
55983 
55984 #define PORT_EDFR_EDF18_MASK                     (0x40000U)
55985 #define PORT_EDFR_EDF18_SHIFT                    (18U)
55986 /*! EDF18 - EFT Detect Flag
55987  *  0b0..No EFT event detected
55988  *  0b1..High or/and low EFT event detected
55989  */
55990 #define PORT_EDFR_EDF18(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF18_SHIFT)) & PORT_EDFR_EDF18_MASK)
55991 
55992 #define PORT_EDFR_EDF19_MASK                     (0x80000U)
55993 #define PORT_EDFR_EDF19_SHIFT                    (19U)
55994 /*! EDF19 - EFT Detect Flag
55995  *  0b0..No EFT event detected
55996  *  0b1..High or/and low EFT event detected
55997  */
55998 #define PORT_EDFR_EDF19(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF19_SHIFT)) & PORT_EDFR_EDF19_MASK)
55999 
56000 #define PORT_EDFR_EDF20_MASK                     (0x100000U)
56001 #define PORT_EDFR_EDF20_SHIFT                    (20U)
56002 /*! EDF20 - EFT Detect Flag
56003  *  0b0..No EFT event detected
56004  *  0b1..High or/and low EFT event detected
56005  */
56006 #define PORT_EDFR_EDF20(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF20_SHIFT)) & PORT_EDFR_EDF20_MASK)
56007 
56008 #define PORT_EDFR_EDF21_MASK                     (0x200000U)
56009 #define PORT_EDFR_EDF21_SHIFT                    (21U)
56010 /*! EDF21 - EFT Detect Flag
56011  *  0b0..No EFT event detected
56012  *  0b1..High or/and low EFT event detected
56013  */
56014 #define PORT_EDFR_EDF21(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF21_SHIFT)) & PORT_EDFR_EDF21_MASK)
56015 
56016 #define PORT_EDFR_EDF22_MASK                     (0x400000U)
56017 #define PORT_EDFR_EDF22_SHIFT                    (22U)
56018 /*! EDF22 - EFT Detect Flag
56019  *  0b0..No EFT event detected
56020  *  0b1..High or/and low EFT event detected
56021  */
56022 #define PORT_EDFR_EDF22(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF22_SHIFT)) & PORT_EDFR_EDF22_MASK)
56023 
56024 #define PORT_EDFR_EDF23_MASK                     (0x800000U)
56025 #define PORT_EDFR_EDF23_SHIFT                    (23U)
56026 /*! EDF23 - EFT Detect Flag
56027  *  0b0..No EFT event detected
56028  *  0b1..High or/and low EFT event detected
56029  */
56030 #define PORT_EDFR_EDF23(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF23_SHIFT)) & PORT_EDFR_EDF23_MASK)
56031 
56032 #define PORT_EDFR_EDF24_MASK                     (0x1000000U)
56033 #define PORT_EDFR_EDF24_SHIFT                    (24U)
56034 /*! EDF24 - EFT Detect Flag
56035  *  0b0..No EFT event detected
56036  *  0b1..High or/and low EFT event detected
56037  */
56038 #define PORT_EDFR_EDF24(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF24_SHIFT)) & PORT_EDFR_EDF24_MASK)
56039 
56040 #define PORT_EDFR_EDF25_MASK                     (0x2000000U)
56041 #define PORT_EDFR_EDF25_SHIFT                    (25U)
56042 /*! EDF25 - EFT Detect Flag
56043  *  0b0..No EFT event detected
56044  *  0b1..High or/and low EFT event detected
56045  */
56046 #define PORT_EDFR_EDF25(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF25_SHIFT)) & PORT_EDFR_EDF25_MASK)
56047 
56048 #define PORT_EDFR_EDF26_MASK                     (0x4000000U)
56049 #define PORT_EDFR_EDF26_SHIFT                    (26U)
56050 /*! EDF26 - EFT Detect Flag
56051  *  0b0..No EFT event detected
56052  *  0b1..High or/and low EFT event detected
56053  */
56054 #define PORT_EDFR_EDF26(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF26_SHIFT)) & PORT_EDFR_EDF26_MASK)
56055 
56056 #define PORT_EDFR_EDF27_MASK                     (0x8000000U)
56057 #define PORT_EDFR_EDF27_SHIFT                    (27U)
56058 /*! EDF27 - EFT Detect Flag
56059  *  0b0..No EFT event detected
56060  *  0b1..High or/and low EFT event detected
56061  */
56062 #define PORT_EDFR_EDF27(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF27_SHIFT)) & PORT_EDFR_EDF27_MASK)
56063 
56064 #define PORT_EDFR_EDF28_MASK                     (0x10000000U)
56065 #define PORT_EDFR_EDF28_SHIFT                    (28U)
56066 /*! EDF28 - EFT Detect Flag
56067  *  0b0..No EFT event detected
56068  *  0b1..High or/and low EFT event detected
56069  */
56070 #define PORT_EDFR_EDF28(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF28_SHIFT)) & PORT_EDFR_EDF28_MASK)
56071 
56072 #define PORT_EDFR_EDF29_MASK                     (0x20000000U)
56073 #define PORT_EDFR_EDF29_SHIFT                    (29U)
56074 /*! EDF29 - EFT Detect Flag
56075  *  0b0..No EFT event detected
56076  *  0b1..High or/and low EFT event detected
56077  */
56078 #define PORT_EDFR_EDF29(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF29_SHIFT)) & PORT_EDFR_EDF29_MASK)
56079 
56080 #define PORT_EDFR_EDF30_MASK                     (0x40000000U)
56081 #define PORT_EDFR_EDF30_SHIFT                    (30U)
56082 /*! EDF30 - EFT Detect Flag
56083  *  0b0..No EFT event detected
56084  *  0b1..High or/and low EFT event detected
56085  */
56086 #define PORT_EDFR_EDF30(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF30_SHIFT)) & PORT_EDFR_EDF30_MASK)
56087 
56088 #define PORT_EDFR_EDF31_MASK                     (0x80000000U)
56089 #define PORT_EDFR_EDF31_SHIFT                    (31U)
56090 /*! EDF31 - EFT Detect Flag
56091  *  0b0..No EFT event detected
56092  *  0b1..High or/and low EFT event detected
56093  */
56094 #define PORT_EDFR_EDF31(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF31_SHIFT)) & PORT_EDFR_EDF31_MASK)
56095 /*! @} */
56096 
56097 /*! @name EDIER - EFT Detect Interrupt Enable */
56098 /*! @{ */
56099 
56100 #define PORT_EDIER_EDIE0_MASK                    (0x1U)
56101 #define PORT_EDIER_EDIE0_SHIFT                   (0U)
56102 /*! EDIE0 - EFT Detect Interrupt Enable
56103  *  0b0..Interrupt not generated upon detection of the EFT event
56104  *  0b1..Interrupt generated upon detection of the EFT event
56105  */
56106 #define PORT_EDIER_EDIE0(x)                      (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE0_SHIFT)) & PORT_EDIER_EDIE0_MASK)
56107 
56108 #define PORT_EDIER_EDIE1_MASK                    (0x2U)
56109 #define PORT_EDIER_EDIE1_SHIFT                   (1U)
56110 /*! EDIE1 - EFT Detect Interrupt Enable
56111  *  0b0..Interrupt not generated upon detection of the EFT event
56112  *  0b1..Interrupt generated upon detection of the EFT event
56113  */
56114 #define PORT_EDIER_EDIE1(x)                      (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE1_SHIFT)) & PORT_EDIER_EDIE1_MASK)
56115 
56116 #define PORT_EDIER_EDIE2_MASK                    (0x4U)
56117 #define PORT_EDIER_EDIE2_SHIFT                   (2U)
56118 /*! EDIE2 - EFT Detect Interrupt Enable
56119  *  0b0..Interrupt not generated upon detection of the EFT event
56120  *  0b1..Interrupt generated upon detection of the EFT event
56121  */
56122 #define PORT_EDIER_EDIE2(x)                      (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE2_SHIFT)) & PORT_EDIER_EDIE2_MASK)
56123 
56124 #define PORT_EDIER_EDIE3_MASK                    (0x8U)
56125 #define PORT_EDIER_EDIE3_SHIFT                   (3U)
56126 /*! EDIE3 - EFT Detect Interrupt Enable
56127  *  0b0..Interrupt not generated upon detection of the EFT event
56128  *  0b1..Interrupt generated upon detection of the EFT event
56129  */
56130 #define PORT_EDIER_EDIE3(x)                      (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE3_SHIFT)) & PORT_EDIER_EDIE3_MASK)
56131 
56132 #define PORT_EDIER_EDIE4_MASK                    (0x10U)
56133 #define PORT_EDIER_EDIE4_SHIFT                   (4U)
56134 /*! EDIE4 - EFT Detect Interrupt Enable
56135  *  0b0..Interrupt not generated upon detection of the EFT event
56136  *  0b1..Interrupt generated upon detection of the EFT event
56137  */
56138 #define PORT_EDIER_EDIE4(x)                      (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE4_SHIFT)) & PORT_EDIER_EDIE4_MASK)
56139 
56140 #define PORT_EDIER_EDIE5_MASK                    (0x20U)
56141 #define PORT_EDIER_EDIE5_SHIFT                   (5U)
56142 /*! EDIE5 - EFT Detect Interrupt Enable
56143  *  0b0..Interrupt not generated upon detection of the EFT event
56144  *  0b1..Interrupt generated upon detection of the EFT event
56145  */
56146 #define PORT_EDIER_EDIE5(x)                      (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE5_SHIFT)) & PORT_EDIER_EDIE5_MASK)
56147 
56148 #define PORT_EDIER_EDIE6_MASK                    (0x40U)
56149 #define PORT_EDIER_EDIE6_SHIFT                   (6U)
56150 /*! EDIE6 - EFT Detect Interrupt Enable
56151  *  0b0..Interrupt not generated upon detection of the EFT event
56152  *  0b1..Interrupt generated upon detection of the EFT event
56153  */
56154 #define PORT_EDIER_EDIE6(x)                      (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE6_SHIFT)) & PORT_EDIER_EDIE6_MASK)
56155 
56156 #define PORT_EDIER_EDIE7_MASK                    (0x80U)
56157 #define PORT_EDIER_EDIE7_SHIFT                   (7U)
56158 /*! EDIE7 - EFT Detect Interrupt Enable
56159  *  0b0..Interrupt not generated upon detection of the EFT event
56160  *  0b1..Interrupt generated upon detection of the EFT event
56161  */
56162 #define PORT_EDIER_EDIE7(x)                      (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE7_SHIFT)) & PORT_EDIER_EDIE7_MASK)
56163 
56164 #define PORT_EDIER_EDIE8_MASK                    (0x100U)
56165 #define PORT_EDIER_EDIE8_SHIFT                   (8U)
56166 /*! EDIE8 - EFT Detect Interrupt Enable
56167  *  0b0..Interrupt not generated upon detection of the EFT event
56168  *  0b1..Interrupt generated upon detection of the EFT event
56169  */
56170 #define PORT_EDIER_EDIE8(x)                      (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE8_SHIFT)) & PORT_EDIER_EDIE8_MASK)
56171 
56172 #define PORT_EDIER_EDIE9_MASK                    (0x200U)
56173 #define PORT_EDIER_EDIE9_SHIFT                   (9U)
56174 /*! EDIE9 - EFT Detect Interrupt Enable
56175  *  0b0..Interrupt not generated upon detection of the EFT event
56176  *  0b1..Interrupt generated upon detection of the EFT event
56177  */
56178 #define PORT_EDIER_EDIE9(x)                      (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE9_SHIFT)) & PORT_EDIER_EDIE9_MASK)
56179 
56180 #define PORT_EDIER_EDIE10_MASK                   (0x400U)
56181 #define PORT_EDIER_EDIE10_SHIFT                  (10U)
56182 /*! EDIE10 - EFT Detect Interrupt Enable
56183  *  0b0..Interrupt not generated upon detection of the EFT event
56184  *  0b1..Interrupt generated upon detection of the EFT event
56185  */
56186 #define PORT_EDIER_EDIE10(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE10_SHIFT)) & PORT_EDIER_EDIE10_MASK)
56187 
56188 #define PORT_EDIER_EDIE11_MASK                   (0x800U)
56189 #define PORT_EDIER_EDIE11_SHIFT                  (11U)
56190 /*! EDIE11 - EFT Detect Interrupt Enable
56191  *  0b0..Interrupt not generated upon detection of the EFT event
56192  *  0b1..Interrupt generated upon detection of the EFT event
56193  */
56194 #define PORT_EDIER_EDIE11(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE11_SHIFT)) & PORT_EDIER_EDIE11_MASK)
56195 
56196 #define PORT_EDIER_EDIE12_MASK                   (0x1000U)
56197 #define PORT_EDIER_EDIE12_SHIFT                  (12U)
56198 /*! EDIE12 - EFT Detect Interrupt Enable
56199  *  0b0..Interrupt not generated upon detection of the EFT event
56200  *  0b1..Interrupt generated upon detection of the EFT event
56201  */
56202 #define PORT_EDIER_EDIE12(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE12_SHIFT)) & PORT_EDIER_EDIE12_MASK)
56203 
56204 #define PORT_EDIER_EDIE13_MASK                   (0x2000U)
56205 #define PORT_EDIER_EDIE13_SHIFT                  (13U)
56206 /*! EDIE13 - EFT Detect Interrupt Enable
56207  *  0b0..Interrupt not generated upon detection of the EFT event
56208  *  0b1..Interrupt generated upon detection of the EFT event
56209  */
56210 #define PORT_EDIER_EDIE13(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE13_SHIFT)) & PORT_EDIER_EDIE13_MASK)
56211 
56212 #define PORT_EDIER_EDIE14_MASK                   (0x4000U)
56213 #define PORT_EDIER_EDIE14_SHIFT                  (14U)
56214 /*! EDIE14 - EFT Detect Interrupt Enable
56215  *  0b0..Interrupt not generated upon detection of the EFT event
56216  *  0b1..Interrupt generated upon detection of the EFT event
56217  */
56218 #define PORT_EDIER_EDIE14(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE14_SHIFT)) & PORT_EDIER_EDIE14_MASK)
56219 
56220 #define PORT_EDIER_EDIE15_MASK                   (0x8000U)
56221 #define PORT_EDIER_EDIE15_SHIFT                  (15U)
56222 /*! EDIE15 - EFT Detect Interrupt Enable
56223  *  0b0..Interrupt not generated upon detection of the EFT event
56224  *  0b1..Interrupt generated upon detection of the EFT event
56225  */
56226 #define PORT_EDIER_EDIE15(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE15_SHIFT)) & PORT_EDIER_EDIE15_MASK)
56227 
56228 #define PORT_EDIER_EDIE16_MASK                   (0x10000U)
56229 #define PORT_EDIER_EDIE16_SHIFT                  (16U)
56230 /*! EDIE16 - EFT Detect Interrupt Enable
56231  *  0b0..Interrupt not generated upon detection of the EFT event
56232  *  0b1..Interrupt generated upon detection of the EFT event
56233  */
56234 #define PORT_EDIER_EDIE16(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE16_SHIFT)) & PORT_EDIER_EDIE16_MASK)
56235 
56236 #define PORT_EDIER_EDIE17_MASK                   (0x20000U)
56237 #define PORT_EDIER_EDIE17_SHIFT                  (17U)
56238 /*! EDIE17 - EFT Detect Interrupt Enable
56239  *  0b0..Interrupt not generated upon detection of the EFT event
56240  *  0b1..Interrupt generated upon detection of the EFT event
56241  */
56242 #define PORT_EDIER_EDIE17(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE17_SHIFT)) & PORT_EDIER_EDIE17_MASK)
56243 
56244 #define PORT_EDIER_EDIE18_MASK                   (0x40000U)
56245 #define PORT_EDIER_EDIE18_SHIFT                  (18U)
56246 /*! EDIE18 - EFT Detect Interrupt Enable
56247  *  0b0..Interrupt not generated upon detection of the EFT event
56248  *  0b1..Interrupt generated upon detection of the EFT event
56249  */
56250 #define PORT_EDIER_EDIE18(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE18_SHIFT)) & PORT_EDIER_EDIE18_MASK)
56251 
56252 #define PORT_EDIER_EDIE19_MASK                   (0x80000U)
56253 #define PORT_EDIER_EDIE19_SHIFT                  (19U)
56254 /*! EDIE19 - EFT Detect Interrupt Enable
56255  *  0b0..Interrupt not generated upon detection of the EFT event
56256  *  0b1..Interrupt generated upon detection of the EFT event
56257  */
56258 #define PORT_EDIER_EDIE19(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE19_SHIFT)) & PORT_EDIER_EDIE19_MASK)
56259 
56260 #define PORT_EDIER_EDIE20_MASK                   (0x100000U)
56261 #define PORT_EDIER_EDIE20_SHIFT                  (20U)
56262 /*! EDIE20 - EFT Detect Interrupt Enable
56263  *  0b0..Interrupt not generated upon detection of the EFT event
56264  *  0b1..Interrupt generated upon detection of the EFT event
56265  */
56266 #define PORT_EDIER_EDIE20(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE20_SHIFT)) & PORT_EDIER_EDIE20_MASK)
56267 
56268 #define PORT_EDIER_EDIE21_MASK                   (0x200000U)
56269 #define PORT_EDIER_EDIE21_SHIFT                  (21U)
56270 /*! EDIE21 - EFT Detect Interrupt Enable
56271  *  0b0..Interrupt not generated upon detection of the EFT event
56272  *  0b1..Interrupt generated upon detection of the EFT event
56273  */
56274 #define PORT_EDIER_EDIE21(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE21_SHIFT)) & PORT_EDIER_EDIE21_MASK)
56275 
56276 #define PORT_EDIER_EDIE22_MASK                   (0x400000U)
56277 #define PORT_EDIER_EDIE22_SHIFT                  (22U)
56278 /*! EDIE22 - EFT Detect Interrupt Enable
56279  *  0b0..Interrupt not generated upon detection of the EFT event
56280  *  0b1..Interrupt generated upon detection of the EFT event
56281  */
56282 #define PORT_EDIER_EDIE22(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE22_SHIFT)) & PORT_EDIER_EDIE22_MASK)
56283 
56284 #define PORT_EDIER_EDIE23_MASK                   (0x800000U)
56285 #define PORT_EDIER_EDIE23_SHIFT                  (23U)
56286 /*! EDIE23 - EFT Detect Interrupt Enable
56287  *  0b0..Interrupt not generated upon detection of the EFT event
56288  *  0b1..Interrupt generated upon detection of the EFT event
56289  */
56290 #define PORT_EDIER_EDIE23(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE23_SHIFT)) & PORT_EDIER_EDIE23_MASK)
56291 
56292 #define PORT_EDIER_EDIE24_MASK                   (0x1000000U)
56293 #define PORT_EDIER_EDIE24_SHIFT                  (24U)
56294 /*! EDIE24 - EFT Detect Interrupt Enable
56295  *  0b0..Interrupt not generated upon detection of the EFT event
56296  *  0b1..Interrupt generated upon detection of the EFT event
56297  */
56298 #define PORT_EDIER_EDIE24(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE24_SHIFT)) & PORT_EDIER_EDIE24_MASK)
56299 
56300 #define PORT_EDIER_EDIE25_MASK                   (0x2000000U)
56301 #define PORT_EDIER_EDIE25_SHIFT                  (25U)
56302 /*! EDIE25 - EFT Detect Interrupt Enable
56303  *  0b0..Interrupt not generated upon detection of the EFT event
56304  *  0b1..Interrupt generated upon detection of the EFT event
56305  */
56306 #define PORT_EDIER_EDIE25(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE25_SHIFT)) & PORT_EDIER_EDIE25_MASK)
56307 
56308 #define PORT_EDIER_EDIE26_MASK                   (0x4000000U)
56309 #define PORT_EDIER_EDIE26_SHIFT                  (26U)
56310 /*! EDIE26 - EFT Detect Interrupt Enable
56311  *  0b0..Interrupt not generated upon detection of the EFT event
56312  *  0b1..Interrupt generated upon detection of the EFT event
56313  */
56314 #define PORT_EDIER_EDIE26(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE26_SHIFT)) & PORT_EDIER_EDIE26_MASK)
56315 
56316 #define PORT_EDIER_EDIE27_MASK                   (0x8000000U)
56317 #define PORT_EDIER_EDIE27_SHIFT                  (27U)
56318 /*! EDIE27 - EFT Detect Interrupt Enable
56319  *  0b0..Interrupt not generated upon detection of the EFT event
56320  *  0b1..Interrupt generated upon detection of the EFT event
56321  */
56322 #define PORT_EDIER_EDIE27(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE27_SHIFT)) & PORT_EDIER_EDIE27_MASK)
56323 
56324 #define PORT_EDIER_EDIE28_MASK                   (0x10000000U)
56325 #define PORT_EDIER_EDIE28_SHIFT                  (28U)
56326 /*! EDIE28 - EFT Detect Interrupt Enable
56327  *  0b0..Interrupt not generated upon detection of the EFT event
56328  *  0b1..Interrupt generated upon detection of the EFT event
56329  */
56330 #define PORT_EDIER_EDIE28(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE28_SHIFT)) & PORT_EDIER_EDIE28_MASK)
56331 
56332 #define PORT_EDIER_EDIE29_MASK                   (0x20000000U)
56333 #define PORT_EDIER_EDIE29_SHIFT                  (29U)
56334 /*! EDIE29 - EFT Detect Interrupt Enable
56335  *  0b0..Interrupt not generated upon detection of the EFT event
56336  *  0b1..Interrupt generated upon detection of the EFT event
56337  */
56338 #define PORT_EDIER_EDIE29(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE29_SHIFT)) & PORT_EDIER_EDIE29_MASK)
56339 
56340 #define PORT_EDIER_EDIE30_MASK                   (0x40000000U)
56341 #define PORT_EDIER_EDIE30_SHIFT                  (30U)
56342 /*! EDIE30 - EFT Detect Interrupt Enable
56343  *  0b0..Interrupt not generated upon detection of the EFT event
56344  *  0b1..Interrupt generated upon detection of the EFT event
56345  */
56346 #define PORT_EDIER_EDIE30(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE30_SHIFT)) & PORT_EDIER_EDIE30_MASK)
56347 
56348 #define PORT_EDIER_EDIE31_MASK                   (0x80000000U)
56349 #define PORT_EDIER_EDIE31_SHIFT                  (31U)
56350 /*! EDIE31 - EFT Detect Interrupt Enable
56351  *  0b0..Interrupt not generated upon detection of the EFT event
56352  *  0b1..Interrupt generated upon detection of the EFT event
56353  */
56354 #define PORT_EDIER_EDIE31(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE31_SHIFT)) & PORT_EDIER_EDIE31_MASK)
56355 /*! @} */
56356 
56357 /*! @name EDCR - EFT Detect Clear */
56358 /*! @{ */
56359 
56360 #define PORT_EDCR_EDHC_MASK                      (0x1U)
56361 #define PORT_EDCR_EDHC_SHIFT                     (0U)
56362 /*! EDHC - EFT Detect High Clear
56363  *  0b0..Does not clear
56364  *  0b1..Clears
56365  */
56366 #define PORT_EDCR_EDHC(x)                        (((uint32_t)(((uint32_t)(x)) << PORT_EDCR_EDHC_SHIFT)) & PORT_EDCR_EDHC_MASK)
56367 
56368 #define PORT_EDCR_EDLC_MASK                      (0x2U)
56369 #define PORT_EDCR_EDLC_SHIFT                     (1U)
56370 /*! EDLC - EFT Detect Low Clear
56371  *  0b0..Does not clear
56372  *  0b1..Clears
56373  */
56374 #define PORT_EDCR_EDLC(x)                        (((uint32_t)(((uint32_t)(x)) << PORT_EDCR_EDLC_SHIFT)) & PORT_EDCR_EDLC_MASK)
56375 /*! @} */
56376 
56377 /*! @name CALIB0 - Calibration 0 */
56378 /*! @{ */
56379 
56380 #define PORT_CALIB0_NCAL_MASK                    (0x3FU)
56381 #define PORT_CALIB0_NCAL_SHIFT                   (0U)
56382 /*! NCAL - Calibration of NMOS Output Driver */
56383 #define PORT_CALIB0_NCAL(x)                      (((uint32_t)(((uint32_t)(x)) << PORT_CALIB0_NCAL_SHIFT)) & PORT_CALIB0_NCAL_MASK)
56384 
56385 #define PORT_CALIB0_PCAL_MASK                    (0x3F0000U)
56386 #define PORT_CALIB0_PCAL_SHIFT                   (16U)
56387 /*! PCAL - Calibration of PMOS Output Driver */
56388 #define PORT_CALIB0_PCAL(x)                      (((uint32_t)(((uint32_t)(x)) << PORT_CALIB0_PCAL_SHIFT)) & PORT_CALIB0_PCAL_MASK)
56389 /*! @} */
56390 
56391 /*! @name CALIB1 - Calibration 1 */
56392 /*! @{ */
56393 
56394 #define PORT_CALIB1_NCAL_MASK                    (0x3FU)
56395 #define PORT_CALIB1_NCAL_SHIFT                   (0U)
56396 /*! NCAL - Calibration of NMOS Output Driver */
56397 #define PORT_CALIB1_NCAL(x)                      (((uint32_t)(((uint32_t)(x)) << PORT_CALIB1_NCAL_SHIFT)) & PORT_CALIB1_NCAL_MASK)
56398 
56399 #define PORT_CALIB1_PCAL_MASK                    (0x3F0000U)
56400 #define PORT_CALIB1_PCAL_SHIFT                   (16U)
56401 /*! PCAL - Calibration of PMOS Output Driver */
56402 #define PORT_CALIB1_PCAL(x)                      (((uint32_t)(((uint32_t)(x)) << PORT_CALIB1_PCAL_SHIFT)) & PORT_CALIB1_PCAL_MASK)
56403 /*! @} */
56404 
56405 /*! @name PCR - Pin Control 0..Pin Control 31 */
56406 /*! @{ */
56407 
56408 #define PORT_PCR_PS_MASK                         (0x1U)
56409 #define PORT_PCR_PS_SHIFT                        (0U)
56410 /*! PS - Pull Select
56411  *  0b0..Enables internal pulldown resistor
56412  *  0b1..Enables internal pullup resistor
56413  */
56414 #define PORT_PCR_PS(x)                           (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PS_SHIFT)) & PORT_PCR_PS_MASK)
56415 
56416 #define PORT_PCR_PE_MASK                         (0x2U)
56417 #define PORT_PCR_PE_SHIFT                        (1U)
56418 /*! PE - Pull Enable
56419  *  0b0..Disables
56420  *  0b1..Enables
56421  */
56422 #define PORT_PCR_PE(x)                           (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PE_SHIFT)) & PORT_PCR_PE_MASK)
56423 
56424 #define PORT_PCR_PV_MASK                         (0x4U)
56425 #define PORT_PCR_PV_SHIFT                        (2U)
56426 /*! PV - Pull Value
56427  *  0b0..Low
56428  *  0b1..High
56429  */
56430 #define PORT_PCR_PV(x)                           (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PV_SHIFT)) & PORT_PCR_PV_MASK)
56431 
56432 #define PORT_PCR_SRE_MASK                        (0x8U)
56433 #define PORT_PCR_SRE_SHIFT                       (3U)
56434 /*! SRE - Slew Rate Enable
56435  *  0b0..Fast
56436  *  0b1..Slow
56437  */
56438 #define PORT_PCR_SRE(x)                          (((uint32_t)(((uint32_t)(x)) << PORT_PCR_SRE_SHIFT)) & PORT_PCR_SRE_MASK)
56439 
56440 #define PORT_PCR_PFE_MASK                        (0x10U)
56441 #define PORT_PCR_PFE_SHIFT                       (4U)
56442 /*! PFE - Passive Filter Enable
56443  *  0b0..Disables
56444  *  0b1..Enables
56445  */
56446 #define PORT_PCR_PFE(x)                          (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PFE_SHIFT)) & PORT_PCR_PFE_MASK)
56447 
56448 #define PORT_PCR_ODE_MASK                        (0x20U)
56449 #define PORT_PCR_ODE_SHIFT                       (5U)
56450 /*! ODE - Open Drain Enable
56451  *  0b0..Disables
56452  *  0b1..Enables
56453  */
56454 #define PORT_PCR_ODE(x)                          (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ODE_SHIFT)) & PORT_PCR_ODE_MASK)
56455 
56456 #define PORT_PCR_DSE_MASK                        (0x40U)
56457 #define PORT_PCR_DSE_SHIFT                       (6U)
56458 /*! DSE - Drive Strength Enable
56459  *  0b0..Low
56460  *  0b1..High
56461  */
56462 #define PORT_PCR_DSE(x)                          (((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE_SHIFT)) & PORT_PCR_DSE_MASK)
56463 
56464 #define PORT_PCR_MUX_MASK                        (0xF00U)  /* Merged from fields with different position or width, of widths (2, 4), largest definition used */
56465 #define PORT_PCR_MUX_SHIFT                       (8U)
56466 /*! MUX - Pin Multiplex Control
56467  *  0b0000..Alternative 0 (GPIO)
56468  *  0b0001..Alternative 1 (chip-specific)
56469  *  0b0010..Alternative 2 (chip-specific)
56470  *  0b0011..Alternative 3 (chip-specific)
56471  *  0b0100..Alternative 4 (chip-specific)
56472  *  0b0101..Alternative 5 (chip-specific)
56473  *  0b0110..Alternative 6 (chip-specific)
56474  *  0b0111..Alternative 7 (chip-specific)
56475  *  0b1000..Alternative 8 (chip-specific)
56476  *  0b1001..Alternative 9 (chip-specific)
56477  *  0b1010..Alternative 10 (chip-specific)
56478  *  0b1011..Alternative 11 (chip-specific)
56479  *  0b1100..Alternative 12 (chip-specific)
56480  *  0b1101..Alternative 13 (chip-specific)
56481  */
56482 #define PORT_PCR_MUX(x)                          (((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK)  /* Merged from fields with different position or width, of widths (2, 4), largest definition used */
56483 
56484 #define PORT_PCR_IBE_MASK                        (0x1000U)
56485 #define PORT_PCR_IBE_SHIFT                       (12U)
56486 /*! IBE - Input Buffer Enable
56487  *  0b0..Disables
56488  *  0b1..Enables
56489  */
56490 #define PORT_PCR_IBE(x)                          (((uint32_t)(((uint32_t)(x)) << PORT_PCR_IBE_SHIFT)) & PORT_PCR_IBE_MASK)
56491 
56492 #define PORT_PCR_INV_MASK                        (0x2000U)
56493 #define PORT_PCR_INV_SHIFT                       (13U)
56494 /*! INV - Invert Input
56495  *  0b0..Does not invert
56496  *  0b1..Inverts
56497  */
56498 #define PORT_PCR_INV(x)                          (((uint32_t)(((uint32_t)(x)) << PORT_PCR_INV_SHIFT)) & PORT_PCR_INV_MASK)
56499 
56500 #define PORT_PCR_LK_MASK                         (0x8000U)
56501 #define PORT_PCR_LK_SHIFT                        (15U)
56502 /*! LK - Lock Register
56503  *  0b0..Does not lock
56504  *  0b1..Locks
56505  */
56506 #define PORT_PCR_LK(x)                           (((uint32_t)(((uint32_t)(x)) << PORT_PCR_LK_SHIFT)) & PORT_PCR_LK_MASK)
56507 /*! @} */
56508 
56509 /* The count of PORT_PCR */
56510 #define PORT_PCR_COUNT                           (32U)
56511 
56512 
56513 /*!
56514  * @}
56515  */ /* end of group PORT_Register_Masks */
56516 
56517 
56518 /* PORT - Peripheral instance base addresses */
56519 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
56520   /** Peripheral PORT0 base address */
56521   #define PORT0_BASE                               (0x50116000u)
56522   /** Peripheral PORT0 base address */
56523   #define PORT0_BASE_NS                            (0x40116000u)
56524   /** Peripheral PORT0 base pointer */
56525   #define PORT0                                    ((PORT_Type *)PORT0_BASE)
56526   /** Peripheral PORT0 base pointer */
56527   #define PORT0_NS                                 ((PORT_Type *)PORT0_BASE_NS)
56528   /** Peripheral PORT1 base address */
56529   #define PORT1_BASE                               (0x50117000u)
56530   /** Peripheral PORT1 base address */
56531   #define PORT1_BASE_NS                            (0x40117000u)
56532   /** Peripheral PORT1 base pointer */
56533   #define PORT1                                    ((PORT_Type *)PORT1_BASE)
56534   /** Peripheral PORT1 base pointer */
56535   #define PORT1_NS                                 ((PORT_Type *)PORT1_BASE_NS)
56536   /** Peripheral PORT2 base address */
56537   #define PORT2_BASE                               (0x50118000u)
56538   /** Peripheral PORT2 base address */
56539   #define PORT2_BASE_NS                            (0x40118000u)
56540   /** Peripheral PORT2 base pointer */
56541   #define PORT2                                    ((PORT_Type *)PORT2_BASE)
56542   /** Peripheral PORT2 base pointer */
56543   #define PORT2_NS                                 ((PORT_Type *)PORT2_BASE_NS)
56544   /** Peripheral PORT3 base address */
56545   #define PORT3_BASE                               (0x50119000u)
56546   /** Peripheral PORT3 base address */
56547   #define PORT3_BASE_NS                            (0x40119000u)
56548   /** Peripheral PORT3 base pointer */
56549   #define PORT3                                    ((PORT_Type *)PORT3_BASE)
56550   /** Peripheral PORT3 base pointer */
56551   #define PORT3_NS                                 ((PORT_Type *)PORT3_BASE_NS)
56552   /** Peripheral PORT4 base address */
56553   #define PORT4_BASE                               (0x5011A000u)
56554   /** Peripheral PORT4 base address */
56555   #define PORT4_BASE_NS                            (0x4011A000u)
56556   /** Peripheral PORT4 base pointer */
56557   #define PORT4                                    ((PORT_Type *)PORT4_BASE)
56558   /** Peripheral PORT4 base pointer */
56559   #define PORT4_NS                                 ((PORT_Type *)PORT4_BASE_NS)
56560   /** Peripheral PORT5 base address */
56561   #define PORT5_BASE                               (0x50042000u)
56562   /** Peripheral PORT5 base address */
56563   #define PORT5_BASE_NS                            (0x40042000u)
56564   /** Peripheral PORT5 base pointer */
56565   #define PORT5                                    ((PORT_Type *)PORT5_BASE)
56566   /** Peripheral PORT5 base pointer */
56567   #define PORT5_NS                                 ((PORT_Type *)PORT5_BASE_NS)
56568   /** Array initializer of PORT peripheral base addresses */
56569   #define PORT_BASE_ADDRS                          { PORT0_BASE, PORT1_BASE, PORT2_BASE, PORT3_BASE, PORT4_BASE, PORT5_BASE }
56570   /** Array initializer of PORT peripheral base pointers */
56571   #define PORT_BASE_PTRS                           { PORT0, PORT1, PORT2, PORT3, PORT4, PORT5 }
56572   /** Array initializer of PORT peripheral base addresses */
56573   #define PORT_BASE_ADDRS_NS                       { PORT0_BASE_NS, PORT1_BASE_NS, PORT2_BASE_NS, PORT3_BASE_NS, PORT4_BASE_NS, PORT5_BASE_NS }
56574   /** Array initializer of PORT peripheral base pointers */
56575   #define PORT_BASE_PTRS_NS                        { PORT0_NS, PORT1_NS, PORT2_NS, PORT3_NS, PORT4_NS, PORT5_NS }
56576 #else
56577   /** Peripheral PORT0 base address */
56578   #define PORT0_BASE                               (0x40116000u)
56579   /** Peripheral PORT0 base pointer */
56580   #define PORT0                                    ((PORT_Type *)PORT0_BASE)
56581   /** Peripheral PORT1 base address */
56582   #define PORT1_BASE                               (0x40117000u)
56583   /** Peripheral PORT1 base pointer */
56584   #define PORT1                                    ((PORT_Type *)PORT1_BASE)
56585   /** Peripheral PORT2 base address */
56586   #define PORT2_BASE                               (0x40118000u)
56587   /** Peripheral PORT2 base pointer */
56588   #define PORT2                                    ((PORT_Type *)PORT2_BASE)
56589   /** Peripheral PORT3 base address */
56590   #define PORT3_BASE                               (0x40119000u)
56591   /** Peripheral PORT3 base pointer */
56592   #define PORT3                                    ((PORT_Type *)PORT3_BASE)
56593   /** Peripheral PORT4 base address */
56594   #define PORT4_BASE                               (0x4011A000u)
56595   /** Peripheral PORT4 base pointer */
56596   #define PORT4                                    ((PORT_Type *)PORT4_BASE)
56597   /** Peripheral PORT5 base address */
56598   #define PORT5_BASE                               (0x40042000u)
56599   /** Peripheral PORT5 base pointer */
56600   #define PORT5                                    ((PORT_Type *)PORT5_BASE)
56601   /** Array initializer of PORT peripheral base addresses */
56602   #define PORT_BASE_ADDRS                          { PORT0_BASE, PORT1_BASE, PORT2_BASE, PORT3_BASE, PORT4_BASE, PORT5_BASE }
56603   /** Array initializer of PORT peripheral base pointers */
56604   #define PORT_BASE_PTRS                           { PORT0, PORT1, PORT2, PORT3, PORT4, PORT5 }
56605 #endif
56606 
56607 /*!
56608  * @}
56609  */ /* end of group PORT_Peripheral_Access_Layer */
56610 
56611 
56612 /* ----------------------------------------------------------------------------
56613    -- POWERQUAD Peripheral Access Layer
56614    ---------------------------------------------------------------------------- */
56615 
56616 /*!
56617  * @addtogroup POWERQUAD_Peripheral_Access_Layer POWERQUAD Peripheral Access Layer
56618  * @{
56619  */
56620 
56621 /** POWERQUAD - Register Layout Typedef */
56622 typedef struct {
56623   __IO uint32_t OUTBASE;                           /**< Output Base, offset: 0x0 */
56624   __IO uint32_t OUTFORMAT;                         /**< Output Format, offset: 0x4 */
56625   __IO uint32_t TMPBASE;                           /**< Temporary Base, offset: 0x8 */
56626   __IO uint32_t TMPFORMAT;                         /**< Temporary Format, offset: 0xC */
56627   __IO uint32_t INABASE;                           /**< Input A Base, offset: 0x10 */
56628   __IO uint32_t INAFORMAT;                         /**< Input A Format, offset: 0x14 */
56629   __IO uint32_t INBBASE;                           /**< Input B Base, offset: 0x18 */
56630   __IO uint32_t INBFORMAT;                         /**< Input B Format, offset: 0x1C */
56631        uint8_t RESERVED_0[224];
56632   __IO uint32_t CONTROL;                           /**< Control, offset: 0x100 */
56633   __IO uint32_t LENGTH;                            /**< Length, offset: 0x104 */
56634   __IO uint32_t CPPRE;                             /**< Coprocessor Prescale, offset: 0x108 */
56635   __IO uint32_t MISC;                              /**< Miscellaneous, offset: 0x10C */
56636   __IO uint32_t CURSORY;                           /**< Cursory, offset: 0x110 */
56637        uint8_t RESERVED_1[108];
56638   __IO uint32_t CORDIC_X;                          /**< CORDIC Input X, offset: 0x180 */
56639   __IO uint32_t CORDIC_Y;                          /**< CORDIC Input Y, offset: 0x184 */
56640   __IO uint32_t CORDIC_Z;                          /**< CORDIC Input Z, offset: 0x188 */
56641   __IO uint32_t ERRSTAT;                           /**< Error Status, offset: 0x18C */
56642   __IO uint32_t INTREN;                            /**< Interrupt Enable, offset: 0x190 */
56643   __IO uint32_t EVENTEN;                           /**< Event Enable, offset: 0x194 */
56644   __IO uint32_t INTRSTAT;                          /**< Interrupt Status, offset: 0x198 */
56645        uint8_t RESERVED_2[100];
56646   __IO uint32_t GPREG[16];                         /**< General Purpose Register Bank n, array offset: 0x200, array step: 0x4 */
56647   __IO uint32_t COMPREG[8];                        /**< Compute Register Bank n, array offset: 0x240, array step: 0x4 */
56648 } POWERQUAD_Type;
56649 
56650 /* ----------------------------------------------------------------------------
56651    -- POWERQUAD Register Masks
56652    ---------------------------------------------------------------------------- */
56653 
56654 /*!
56655  * @addtogroup POWERQUAD_Register_Masks POWERQUAD Register Masks
56656  * @{
56657  */
56658 
56659 /*! @name OUTBASE - Output Base */
56660 /*! @{ */
56661 
56662 #define POWERQUAD_OUTBASE_OUTBASE_MASK           (0xFFFFFFFFU)
56663 #define POWERQUAD_OUTBASE_OUTBASE_SHIFT          (0U)
56664 /*! OUTBASE - Output Region Base Address */
56665 #define POWERQUAD_OUTBASE_OUTBASE(x)             (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTBASE_OUTBASE_SHIFT)) & POWERQUAD_OUTBASE_OUTBASE_MASK)
56666 /*! @} */
56667 
56668 /*! @name OUTFORMAT - Output Format */
56669 /*! @{ */
56670 
56671 #define POWERQUAD_OUTFORMAT_OUT_FORMATINT_MASK   (0x3U)
56672 #define POWERQUAD_OUTFORMAT_OUT_FORMATINT_SHIFT  (0U)
56673 /*! OUT_FORMATINT - Output Internal Format
56674  *  0b00..Q15 16-bit fixed-point integer
56675  *  0b01..Q31 32-bit fixed-point integer
56676  *  0b10..F32 32-bit floating-point format
56677  *  0b11..
56678  */
56679 #define POWERQUAD_OUTFORMAT_OUT_FORMATINT(x)     (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTFORMAT_OUT_FORMATINT_SHIFT)) & POWERQUAD_OUTFORMAT_OUT_FORMATINT_MASK)
56680 
56681 #define POWERQUAD_OUTFORMAT_OUT_FORMATEXT_MASK   (0x30U)
56682 #define POWERQUAD_OUTFORMAT_OUT_FORMATEXT_SHIFT  (4U)
56683 /*! OUT_FORMATEXT - Output External Format
56684  *  0b00..Q15 16-bit fixed-point integer
56685  *  0b01..Q31 32-bit fixed-point integer
56686  *  0b10..F32 32-bit floating-point format
56687  *  0b11..
56688  */
56689 #define POWERQUAD_OUTFORMAT_OUT_FORMATEXT(x)     (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTFORMAT_OUT_FORMATEXT_SHIFT)) & POWERQUAD_OUTFORMAT_OUT_FORMATEXT_MASK)
56690 
56691 #define POWERQUAD_OUTFORMAT_OUT_SCALER_MASK      (0xFF00U)
56692 #define POWERQUAD_OUTFORMAT_OUT_SCALER_SHIFT     (8U)
56693 /*! OUT_SCALER - 8-bit Scaling Value for Result Data */
56694 #define POWERQUAD_OUTFORMAT_OUT_SCALER(x)        (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTFORMAT_OUT_SCALER_SHIFT)) & POWERQUAD_OUTFORMAT_OUT_SCALER_MASK)
56695 /*! @} */
56696 
56697 /*! @name TMPBASE - Temporary Base */
56698 /*! @{ */
56699 
56700 #define POWERQUAD_TMPBASE_TMPBASE_MASK           (0xFFFFFFFFU)
56701 #define POWERQUAD_TMPBASE_TMPBASE_SHIFT          (0U)
56702 /*! TMPBASE - Base Address for the Temporary Region */
56703 #define POWERQUAD_TMPBASE_TMPBASE(x)             (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPBASE_TMPBASE_SHIFT)) & POWERQUAD_TMPBASE_TMPBASE_MASK)
56704 /*! @} */
56705 
56706 /*! @name TMPFORMAT - Temporary Format */
56707 /*! @{ */
56708 
56709 #define POWERQUAD_TMPFORMAT_TMP_FORMATINT_MASK   (0x3U)
56710 #define POWERQUAD_TMPFORMAT_TMP_FORMATINT_SHIFT  (0U)
56711 /*! TMP_FORMATINT - Temporary Internal Format
56712  *  0b00..Q15 16-bit fixed-point integer
56713  *  0b01..Q31 32-bit fixed-point integer
56714  *  0b10..F32 32-bit floating-point format
56715  *  0b11..
56716  */
56717 #define POWERQUAD_TMPFORMAT_TMP_FORMATINT(x)     (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPFORMAT_TMP_FORMATINT_SHIFT)) & POWERQUAD_TMPFORMAT_TMP_FORMATINT_MASK)
56718 
56719 #define POWERQUAD_TMPFORMAT_TMP_FORMATEXT_MASK   (0x30U)
56720 #define POWERQUAD_TMPFORMAT_TMP_FORMATEXT_SHIFT  (4U)
56721 /*! TMP_FORMATEXT - Temporary External Format
56722  *  0b00..Q15 16-bit fixed-point integer
56723  *  0b01..Q31 32-bit fixed-point integer
56724  *  0b10..F32 32-bit floating-point format
56725  *  0b11..
56726  */
56727 #define POWERQUAD_TMPFORMAT_TMP_FORMATEXT(x)     (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPFORMAT_TMP_FORMATEXT_SHIFT)) & POWERQUAD_TMPFORMAT_TMP_FORMATEXT_MASK)
56728 
56729 #define POWERQUAD_TMPFORMAT_TMP_SCALER_MASK      (0xFF00U)
56730 #define POWERQUAD_TMPFORMAT_TMP_SCALER_SHIFT     (8U)
56731 /*! TMP_SCALER - Scaling Value for Temporary Data. */
56732 #define POWERQUAD_TMPFORMAT_TMP_SCALER(x)        (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPFORMAT_TMP_SCALER_SHIFT)) & POWERQUAD_TMPFORMAT_TMP_SCALER_MASK)
56733 /*! @} */
56734 
56735 /*! @name INABASE - Input A Base */
56736 /*! @{ */
56737 
56738 #define POWERQUAD_INABASE_INABASE_MASK           (0xFFFFFFFFU)
56739 #define POWERQUAD_INABASE_INABASE_SHIFT          (0U)
56740 /*! INABASE - Input A Base */
56741 #define POWERQUAD_INABASE_INABASE(x)             (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INABASE_INABASE_SHIFT)) & POWERQUAD_INABASE_INABASE_MASK)
56742 /*! @} */
56743 
56744 /*! @name INAFORMAT - Input A Format */
56745 /*! @{ */
56746 
56747 #define POWERQUAD_INAFORMAT_INA_FORMATINT_MASK   (0x3U)
56748 #define POWERQUAD_INAFORMAT_INA_FORMATINT_SHIFT  (0U)
56749 /*! INA_FORMATINT - Input A Internal Format
56750  *  0b00..Q15 16-bit fixed-point integer
56751  *  0b01..Q31 32-bit fixed-point integer
56752  *  0b10..F32 32-bit floating-point format
56753  *  0b11..
56754  */
56755 #define POWERQUAD_INAFORMAT_INA_FORMATINT(x)     (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INAFORMAT_INA_FORMATINT_SHIFT)) & POWERQUAD_INAFORMAT_INA_FORMATINT_MASK)
56756 
56757 #define POWERQUAD_INAFORMAT_INA_FORMATEXT_MASK   (0x30U)
56758 #define POWERQUAD_INAFORMAT_INA_FORMATEXT_SHIFT  (4U)
56759 /*! INA_FORMATEXT - Input A External Format
56760  *  0b00..Q15 16-bit fixed-point integer
56761  *  0b01..Q31 32-bit fixed-point integer
56762  *  0b10..F32 32-bit floating-point format
56763  *  0b11..
56764  */
56765 #define POWERQUAD_INAFORMAT_INA_FORMATEXT(x)     (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INAFORMAT_INA_FORMATEXT_SHIFT)) & POWERQUAD_INAFORMAT_INA_FORMATEXT_MASK)
56766 
56767 #define POWERQUAD_INAFORMAT_INA_SCALER_MASK      (0xFF00U)
56768 #define POWERQUAD_INAFORMAT_INA_SCALER_SHIFT     (8U)
56769 /*! INA_SCALER - Input A Scaler Value */
56770 #define POWERQUAD_INAFORMAT_INA_SCALER(x)        (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INAFORMAT_INA_SCALER_SHIFT)) & POWERQUAD_INAFORMAT_INA_SCALER_MASK)
56771 /*! @} */
56772 
56773 /*! @name INBBASE - Input B Base */
56774 /*! @{ */
56775 
56776 #define POWERQUAD_INBBASE_INBBASE_MASK           (0xFFFFFFFFU)
56777 #define POWERQUAD_INBBASE_INBBASE_SHIFT          (0U)
56778 /*! INBBASE - Input B Base */
56779 #define POWERQUAD_INBBASE_INBBASE(x)             (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBBASE_INBBASE_SHIFT)) & POWERQUAD_INBBASE_INBBASE_MASK)
56780 /*! @} */
56781 
56782 /*! @name INBFORMAT - Input B Format */
56783 /*! @{ */
56784 
56785 #define POWERQUAD_INBFORMAT_INB_FORMATINT_MASK   (0x3U)
56786 #define POWERQUAD_INBFORMAT_INB_FORMATINT_SHIFT  (0U)
56787 /*! INB_FORMATINT - Input B Internal Format
56788  *  0b00..Q15 16-bit fixed-point integer
56789  *  0b01..Q31 32-bit fixed-point integer
56790  *  0b10..F32 32-bit floating-point format
56791  *  0b11..
56792  */
56793 #define POWERQUAD_INBFORMAT_INB_FORMATINT(x)     (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBFORMAT_INB_FORMATINT_SHIFT)) & POWERQUAD_INBFORMAT_INB_FORMATINT_MASK)
56794 
56795 #define POWERQUAD_INBFORMAT_INB_FORMATEXT_MASK   (0x30U)
56796 #define POWERQUAD_INBFORMAT_INB_FORMATEXT_SHIFT  (4U)
56797 /*! INB_FORMATEXT - Input B External Format
56798  *  0b00..Q15 16-bit fixed-point integer
56799  *  0b01..Q31 32-bit fixed-point integer
56800  *  0b10..F32 32-bit floating-point format
56801  *  0b11..
56802  */
56803 #define POWERQUAD_INBFORMAT_INB_FORMATEXT(x)     (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBFORMAT_INB_FORMATEXT_SHIFT)) & POWERQUAD_INBFORMAT_INB_FORMATEXT_MASK)
56804 
56805 #define POWERQUAD_INBFORMAT_INB_SCALER_MASK      (0xFF00U)
56806 #define POWERQUAD_INBFORMAT_INB_SCALER_SHIFT     (8U)
56807 /*! INB_SCALER - Input B Scaler */
56808 #define POWERQUAD_INBFORMAT_INB_SCALER(x)        (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBFORMAT_INB_SCALER_SHIFT)) & POWERQUAD_INBFORMAT_INB_SCALER_MASK)
56809 /*! @} */
56810 
56811 /*! @name CONTROL - Control */
56812 /*! @{ */
56813 
56814 #define POWERQUAD_CONTROL_DECODE_OPCODE_MASK     (0xFU)
56815 #define POWERQUAD_CONTROL_DECODE_OPCODE_SHIFT    (0U)
56816 /*! DECODE_OPCODE - Decode Opcode */
56817 #define POWERQUAD_CONTROL_DECODE_OPCODE(x)       (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CONTROL_DECODE_OPCODE_SHIFT)) & POWERQUAD_CONTROL_DECODE_OPCODE_MASK)
56818 
56819 #define POWERQUAD_CONTROL_DECODE_MACHINE_MASK    (0xF0U)
56820 #define POWERQUAD_CONTROL_DECODE_MACHINE_SHIFT   (4U)
56821 /*! DECODE_MACHINE - Decode Machine
56822  *  0b0000..Coprocessor
56823  *  0b0001..Matrix engine
56824  *  0b0010..Transform engine
56825  *  0b0011..Filter engine
56826  *  0b0101..CORDIC engine
56827  *  0b0100, 0b0110-0b1111..
56828  */
56829 #define POWERQUAD_CONTROL_DECODE_MACHINE(x)      (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CONTROL_DECODE_MACHINE_SHIFT)) & POWERQUAD_CONTROL_DECODE_MACHINE_MASK)
56830 
56831 #define POWERQUAD_CONTROL_INST_BUSY_MASK         (0x80000000U)
56832 #define POWERQUAD_CONTROL_INST_BUSY_SHIFT        (31U)
56833 /*! INST_BUSY - Instruction Busy
56834  *  0b1..Busy
56835  *  0b0..Not busy
56836  */
56837 #define POWERQUAD_CONTROL_INST_BUSY(x)           (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CONTROL_INST_BUSY_SHIFT)) & POWERQUAD_CONTROL_INST_BUSY_MASK)
56838 /*! @} */
56839 
56840 /*! @name LENGTH - Length */
56841 /*! @{ */
56842 
56843 #define POWERQUAD_LENGTH_INST_LENGTH_MASK        (0xFFFFFFFFU)
56844 #define POWERQUAD_LENGTH_INST_LENGTH_SHIFT       (0U)
56845 /*! INST_LENGTH - Instruction length */
56846 #define POWERQUAD_LENGTH_INST_LENGTH(x)          (((uint32_t)(((uint32_t)(x)) << POWERQUAD_LENGTH_INST_LENGTH_SHIFT)) & POWERQUAD_LENGTH_INST_LENGTH_MASK)
56847 /*! @} */
56848 
56849 /*! @name CPPRE - Coprocessor Prescale */
56850 /*! @{ */
56851 
56852 #define POWERQUAD_CPPRE_CPPRE_IN_MASK            (0xFFU)
56853 #define POWERQUAD_CPPRE_CPPRE_IN_SHIFT           (0U)
56854 /*! CPPRE_IN - Prescaling Input */
56855 #define POWERQUAD_CPPRE_CPPRE_IN(x)              (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_IN_SHIFT)) & POWERQUAD_CPPRE_CPPRE_IN_MASK)
56856 
56857 #define POWERQUAD_CPPRE_CPPRE_OUT_MASK           (0xFF00U)
56858 #define POWERQUAD_CPPRE_CPPRE_OUT_SHIFT          (8U)
56859 /*! CPPRE_OUT - Postscaling Output */
56860 #define POWERQUAD_CPPRE_CPPRE_OUT(x)             (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_OUT_SHIFT)) & POWERQUAD_CPPRE_CPPRE_OUT_MASK)
56861 
56862 #define POWERQUAD_CPPRE_CPPRE_SAT_MASK           (0x10000U)
56863 #define POWERQUAD_CPPRE_CPPRE_SAT_SHIFT          (16U)
56864 /*! CPPRE_SAT - Saturation
56865  *  0b0..No saturation
56866  *  0b1..Forces sub-32 bit saturation
56867  */
56868 #define POWERQUAD_CPPRE_CPPRE_SAT(x)             (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_SAT_SHIFT)) & POWERQUAD_CPPRE_CPPRE_SAT_MASK)
56869 
56870 #define POWERQUAD_CPPRE_CPPRE_SAT8_MASK          (0x20000U)
56871 #define POWERQUAD_CPPRE_CPPRE_SAT8_SHIFT         (17U)
56872 /*! CPPRE_SAT8 - Saturation 8
56873  *  0b0..8 bits
56874  *  0b1..16 bits
56875  */
56876 #define POWERQUAD_CPPRE_CPPRE_SAT8(x)            (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_SAT8_SHIFT)) & POWERQUAD_CPPRE_CPPRE_SAT8_MASK)
56877 /*! @} */
56878 
56879 /*! @name MISC - Miscellaneous */
56880 /*! @{ */
56881 
56882 #define POWERQUAD_MISC_INST_MISC_MASK            (0xFFFFFFFFU)
56883 #define POWERQUAD_MISC_INST_MISC_SHIFT           (0U)
56884 /*! INST_MISC - Scaling Factor */
56885 #define POWERQUAD_MISC_INST_MISC(x)              (((uint32_t)(((uint32_t)(x)) << POWERQUAD_MISC_INST_MISC_SHIFT)) & POWERQUAD_MISC_INST_MISC_MASK)
56886 /*! @} */
56887 
56888 /*! @name CURSORY - Cursory */
56889 /*! @{ */
56890 
56891 #define POWERQUAD_CURSORY_CURSORY_MASK           (0x1U)
56892 #define POWERQUAD_CURSORY_CURSORY_SHIFT          (0U)
56893 /*! CURSORY - Cursory Mode
56894  *  0b0..Disable cursory mode, full floating-point accuracy (24-bit mantissa + 2 bits before rounding).
56895  *  0b1..Enable cursory Mode, 16-bit mantissa (bottom bits are zeroed for inputs and outputs of MACs).
56896  */
56897 #define POWERQUAD_CURSORY_CURSORY(x)             (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CURSORY_CURSORY_SHIFT)) & POWERQUAD_CURSORY_CURSORY_MASK)
56898 /*! @} */
56899 
56900 /*! @name CORDIC_X - CORDIC Input X */
56901 /*! @{ */
56902 
56903 #define POWERQUAD_CORDIC_X_CORDIC_X_MASK         (0xFFFFFFFFU)
56904 #define POWERQUAD_CORDIC_X_CORDIC_X_SHIFT        (0U)
56905 /*! CORDIC_X - CORDIC Input X */
56906 #define POWERQUAD_CORDIC_X_CORDIC_X(x)           (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CORDIC_X_CORDIC_X_SHIFT)) & POWERQUAD_CORDIC_X_CORDIC_X_MASK)
56907 /*! @} */
56908 
56909 /*! @name CORDIC_Y - CORDIC Input Y */
56910 /*! @{ */
56911 
56912 #define POWERQUAD_CORDIC_Y_CORDIC_Y_MASK         (0xFFFFFFFFU)
56913 #define POWERQUAD_CORDIC_Y_CORDIC_Y_SHIFT        (0U)
56914 /*! CORDIC_Y - CORDIC Input Y */
56915 #define POWERQUAD_CORDIC_Y_CORDIC_Y(x)           (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CORDIC_Y_CORDIC_Y_SHIFT)) & POWERQUAD_CORDIC_Y_CORDIC_Y_MASK)
56916 /*! @} */
56917 
56918 /*! @name CORDIC_Z - CORDIC Input Z */
56919 /*! @{ */
56920 
56921 #define POWERQUAD_CORDIC_Z_CORDIC_Z_MASK         (0xFFFFFFFFU)
56922 #define POWERQUAD_CORDIC_Z_CORDIC_Z_SHIFT        (0U)
56923 /*! CORDIC_Z - CORDIC Input Z */
56924 #define POWERQUAD_CORDIC_Z_CORDIC_Z(x)           (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CORDIC_Z_CORDIC_Z_SHIFT)) & POWERQUAD_CORDIC_Z_CORDIC_Z_MASK)
56925 /*! @} */
56926 
56927 /*! @name ERRSTAT - Error Status */
56928 /*! @{ */
56929 
56930 #define POWERQUAD_ERRSTAT_OVERFLOW_MASK          (0x1U)
56931 #define POWERQUAD_ERRSTAT_OVERFLOW_SHIFT         (0U)
56932 /*! OVERFLOW - Floating-point Overflow
56933  *  0b0..No error
56934  *  0b1..Error on floating-point overflow
56935  */
56936 #define POWERQUAD_ERRSTAT_OVERFLOW(x)            (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_OVERFLOW_SHIFT)) & POWERQUAD_ERRSTAT_OVERFLOW_MASK)
56937 
56938 #define POWERQUAD_ERRSTAT_NAN_MASK               (0x2U)
56939 #define POWERQUAD_ERRSTAT_NAN_SHIFT              (1U)
56940 /*! NAN - Floating-Point Not-a-Number (NaN)
56941  *  0b0..No error
56942  *  0b1..Error on floating-point NaN
56943  */
56944 #define POWERQUAD_ERRSTAT_NAN(x)                 (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_NAN_SHIFT)) & POWERQUAD_ERRSTAT_NAN_MASK)
56945 
56946 #define POWERQUAD_ERRSTAT_FIXEDOVERFLOW_MASK     (0x4U)
56947 #define POWERQUAD_ERRSTAT_FIXEDOVERFLOW_SHIFT    (2U)
56948 /*! FIXEDOVERFLOW - Fixed-point Overflow
56949  *  0b0..No error
56950  *  0b1..Error on fixed-point overflow
56951  */
56952 #define POWERQUAD_ERRSTAT_FIXEDOVERFLOW(x)       (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_FIXEDOVERFLOW_SHIFT)) & POWERQUAD_ERRSTAT_FIXEDOVERFLOW_MASK)
56953 
56954 #define POWERQUAD_ERRSTAT_UNDERFLOW_MASK         (0x8U)
56955 #define POWERQUAD_ERRSTAT_UNDERFLOW_SHIFT        (3U)
56956 /*! UNDERFLOW - Underflow
56957  *  0b0..No error
56958  *  0b1..Error on underflow
56959  */
56960 #define POWERQUAD_ERRSTAT_UNDERFLOW(x)           (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_UNDERFLOW_SHIFT)) & POWERQUAD_ERRSTAT_UNDERFLOW_MASK)
56961 
56962 #define POWERQUAD_ERRSTAT_BUSERROR_MASK          (0x10U)
56963 #define POWERQUAD_ERRSTAT_BUSERROR_SHIFT         (4U)
56964 /*! BUSERROR - Bus Error
56965  *  0b0..No error
56966  *  0b1..Error on bus
56967  */
56968 #define POWERQUAD_ERRSTAT_BUSERROR(x)            (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_BUSERROR_SHIFT)) & POWERQUAD_ERRSTAT_BUSERROR_MASK)
56969 /*! @} */
56970 
56971 /*! @name INTREN - Interrupt Enable */
56972 /*! @{ */
56973 
56974 #define POWERQUAD_INTREN_INTR_OFLOW_MASK         (0x1U)
56975 #define POWERQUAD_INTREN_INTR_OFLOW_SHIFT        (0U)
56976 /*! INTR_OFLOW - Interrupt Floating-point Overflow
56977  *  0b0..Disable interrupt
56978  *  0b1..Enable interrupt
56979  */
56980 #define POWERQUAD_INTREN_INTR_OFLOW(x)           (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_OFLOW_SHIFT)) & POWERQUAD_INTREN_INTR_OFLOW_MASK)
56981 
56982 #define POWERQUAD_INTREN_INTR_NAN_MASK           (0x2U)
56983 #define POWERQUAD_INTREN_INTR_NAN_SHIFT          (1U)
56984 /*! INTR_NAN - Interrupt Floating-point NaN
56985  *  0b0..Disable interrupt
56986  *  0b1..Enable interrupt
56987  */
56988 #define POWERQUAD_INTREN_INTR_NAN(x)             (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_NAN_SHIFT)) & POWERQUAD_INTREN_INTR_NAN_MASK)
56989 
56990 #define POWERQUAD_INTREN_INTR_FIXED_MASK         (0x4U)
56991 #define POWERQUAD_INTREN_INTR_FIXED_SHIFT        (2U)
56992 /*! INTR_FIXED - Interrupt on Fixed-point Overflow
56993  *  0b0..Disable interrupt
56994  *  0b1..Enable interrupt
56995  */
56996 #define POWERQUAD_INTREN_INTR_FIXED(x)           (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_FIXED_SHIFT)) & POWERQUAD_INTREN_INTR_FIXED_MASK)
56997 
56998 #define POWERQUAD_INTREN_INTR_UFLOW_MASK         (0x8U)
56999 #define POWERQUAD_INTREN_INTR_UFLOW_SHIFT        (3U)
57000 /*! INTR_UFLOW - Interrupt on Underflow
57001  *  0b0..Disable interrupt
57002  *  0b1..Enable interrupt
57003  */
57004 #define POWERQUAD_INTREN_INTR_UFLOW(x)           (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_UFLOW_SHIFT)) & POWERQUAD_INTREN_INTR_UFLOW_MASK)
57005 
57006 #define POWERQUAD_INTREN_INTR_BERR_MASK          (0x10U)
57007 #define POWERQUAD_INTREN_INTR_BERR_SHIFT         (4U)
57008 /*! INTR_BERR - Interrupt on AHBM Bus Error
57009  *  0b0..Disable interrupt
57010  *  0b1..Enable interrupt
57011  */
57012 #define POWERQUAD_INTREN_INTR_BERR(x)            (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_BERR_SHIFT)) & POWERQUAD_INTREN_INTR_BERR_MASK)
57013 
57014 #define POWERQUAD_INTREN_INTR_COMP_MASK          (0x80U)
57015 #define POWERQUAD_INTREN_INTR_COMP_SHIFT         (7U)
57016 /*! INTR_COMP - Interrupt on Instruction Completion
57017  *  0b0..Disable interrupt
57018  *  0b1..Enable interrupt
57019  */
57020 #define POWERQUAD_INTREN_INTR_COMP(x)            (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_COMP_SHIFT)) & POWERQUAD_INTREN_INTR_COMP_MASK)
57021 /*! @} */
57022 
57023 /*! @name EVENTEN - Event Enable */
57024 /*! @{ */
57025 
57026 #define POWERQUAD_EVENTEN_EVENT_OFLOW_MASK       (0x1U)
57027 #define POWERQUAD_EVENTEN_EVENT_OFLOW_SHIFT      (0U)
57028 /*! EVENT_OFLOW - Event Trigger on Floating-point Overflow
57029  *  0b0..Disable event trigger
57030  *  0b1..Enable event trigger
57031  */
57032 #define POWERQUAD_EVENTEN_EVENT_OFLOW(x)         (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_OFLOW_SHIFT)) & POWERQUAD_EVENTEN_EVENT_OFLOW_MASK)
57033 
57034 #define POWERQUAD_EVENTEN_EVENT_NAN_MASK         (0x2U)
57035 #define POWERQUAD_EVENTEN_EVENT_NAN_SHIFT        (1U)
57036 /*! EVENT_NAN - Event Trigger on Floating-Point NaN
57037  *  0b0..Disable event trigger
57038  *  0b1..Enable event trigger
57039  */
57040 #define POWERQUAD_EVENTEN_EVENT_NAN(x)           (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_NAN_SHIFT)) & POWERQUAD_EVENTEN_EVENT_NAN_MASK)
57041 
57042 #define POWERQUAD_EVENTEN_EVENT_FIXED_MASK       (0x4U)
57043 #define POWERQUAD_EVENTEN_EVENT_FIXED_SHIFT      (2U)
57044 /*! EVENT_FIXED - Event Trigger on Fixed-point Overflow
57045  *  0b0..Disable event trigger
57046  *  0b1..Enable event trigger
57047  */
57048 #define POWERQUAD_EVENTEN_EVENT_FIXED(x)         (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_FIXED_SHIFT)) & POWERQUAD_EVENTEN_EVENT_FIXED_MASK)
57049 
57050 #define POWERQUAD_EVENTEN_EVENT_UFLOW_MASK       (0x8U)
57051 #define POWERQUAD_EVENTEN_EVENT_UFLOW_SHIFT      (3U)
57052 /*! EVENT_UFLOW - Event Trigger on Underflow
57053  *  0b0..Disable event trigger
57054  *  0b1..Enable event trigger
57055  */
57056 #define POWERQUAD_EVENTEN_EVENT_UFLOW(x)         (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_UFLOW_SHIFT)) & POWERQUAD_EVENTEN_EVENT_UFLOW_MASK)
57057 
57058 #define POWERQUAD_EVENTEN_EVENT_BERR_MASK        (0x10U)
57059 #define POWERQUAD_EVENTEN_EVENT_BERR_SHIFT       (4U)
57060 /*! EVENT_BERR - Event Trigger on AHBM Bus Error
57061  *  0b0..Disable event trigger
57062  *  0b1..Enable event trigger
57063  */
57064 #define POWERQUAD_EVENTEN_EVENT_BERR(x)          (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_BERR_SHIFT)) & POWERQUAD_EVENTEN_EVENT_BERR_MASK)
57065 
57066 #define POWERQUAD_EVENTEN_EVENT_COMP_MASK        (0x80U)
57067 #define POWERQUAD_EVENTEN_EVENT_COMP_SHIFT       (7U)
57068 /*! EVENT_COMP - Event Trigger on Instruction Completion
57069  *  0b0..Disable event trigger
57070  *  0b1..Enable event trigger
57071  */
57072 #define POWERQUAD_EVENTEN_EVENT_COMP(x)          (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_COMP_SHIFT)) & POWERQUAD_EVENTEN_EVENT_COMP_MASK)
57073 /*! @} */
57074 
57075 /*! @name INTRSTAT - Interrupt Status */
57076 /*! @{ */
57077 
57078 #define POWERQUAD_INTRSTAT_INTR_STAT_MASK        (0x1U)
57079 #define POWERQUAD_INTRSTAT_INTR_STAT_SHIFT       (0U)
57080 /*! INTR_STAT - Interrupt Status
57081  *  0b0..No new interrupt
57082  *  0b1..Interrupt captured
57083  */
57084 #define POWERQUAD_INTRSTAT_INTR_STAT(x)          (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTRSTAT_INTR_STAT_SHIFT)) & POWERQUAD_INTRSTAT_INTR_STAT_MASK)
57085 /*! @} */
57086 
57087 /*! @name GPREG - General Purpose Register Bank n */
57088 /*! @{ */
57089 
57090 #define POWERQUAD_GPREG_GPREG_MASK               (0xFFFFFFFFU)
57091 #define POWERQUAD_GPREG_GPREG_SHIFT              (0U)
57092 /*! GPREG - General Purpose Bank */
57093 #define POWERQUAD_GPREG_GPREG(x)                 (((uint32_t)(((uint32_t)(x)) << POWERQUAD_GPREG_GPREG_SHIFT)) & POWERQUAD_GPREG_GPREG_MASK)
57094 /*! @} */
57095 
57096 /* The count of POWERQUAD_GPREG */
57097 #define POWERQUAD_GPREG_COUNT                    (16U)
57098 
57099 /*! @name COMPREGS_COMPREG - Compute Register Bank n */
57100 /*! @{ */
57101 
57102 #define POWERQUAD_COMPREGS_COMPREG_COMPREG_MASK  (0xFFFFFFFFU)
57103 #define POWERQUAD_COMPREGS_COMPREG_COMPREG_SHIFT (0U)
57104 /*! COMPREG - Compute bank */
57105 #define POWERQUAD_COMPREGS_COMPREG_COMPREG(x)    (((uint32_t)(((uint32_t)(x)) << POWERQUAD_COMPREGS_COMPREG_COMPREG_SHIFT)) & POWERQUAD_COMPREGS_COMPREG_COMPREG_MASK)
57106 /*! @} */
57107 
57108 /* The count of POWERQUAD_COMPREGS_COMPREG */
57109 #define POWERQUAD_COMPREGS_COMPREG_COUNT         (8U)
57110 
57111 
57112 /*!
57113  * @}
57114  */ /* end of group POWERQUAD_Register_Masks */
57115 
57116 
57117 /* POWERQUAD - Peripheral instance base addresses */
57118 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
57119   /** Peripheral POWERQUAD base address */
57120   #define POWERQUAD_BASE                           (0x500BF000u)
57121   /** Peripheral POWERQUAD base address */
57122   #define POWERQUAD_BASE_NS                        (0x400BF000u)
57123   /** Peripheral POWERQUAD base pointer */
57124   #define POWERQUAD                                ((POWERQUAD_Type *)POWERQUAD_BASE)
57125   /** Peripheral POWERQUAD base pointer */
57126   #define POWERQUAD_NS                             ((POWERQUAD_Type *)POWERQUAD_BASE_NS)
57127   /** Array initializer of POWERQUAD peripheral base addresses */
57128   #define POWERQUAD_BASE_ADDRS                     { POWERQUAD_BASE }
57129   /** Array initializer of POWERQUAD peripheral base pointers */
57130   #define POWERQUAD_BASE_PTRS                      { POWERQUAD }
57131   /** Array initializer of POWERQUAD peripheral base addresses */
57132   #define POWERQUAD_BASE_ADDRS_NS                  { POWERQUAD_BASE_NS }
57133   /** Array initializer of POWERQUAD peripheral base pointers */
57134   #define POWERQUAD_BASE_PTRS_NS                   { POWERQUAD_NS }
57135 #else
57136   /** Peripheral POWERQUAD base address */
57137   #define POWERQUAD_BASE                           (0x400BF000u)
57138   /** Peripheral POWERQUAD base pointer */
57139   #define POWERQUAD                                ((POWERQUAD_Type *)POWERQUAD_BASE)
57140   /** Array initializer of POWERQUAD peripheral base addresses */
57141   #define POWERQUAD_BASE_ADDRS                     { POWERQUAD_BASE }
57142   /** Array initializer of POWERQUAD peripheral base pointers */
57143   #define POWERQUAD_BASE_PTRS                      { POWERQUAD }
57144 #endif
57145 /** Interrupt vectors for the POWERQUAD peripheral type */
57146 #define POWERQUAD_IRQS                           { PQ_IRQn }
57147 
57148 /*!
57149  * @}
57150  */ /* end of group POWERQUAD_Peripheral_Access_Layer */
57151 
57152 
57153 /* ----------------------------------------------------------------------------
57154    -- PUF Peripheral Access Layer
57155    ---------------------------------------------------------------------------- */
57156 
57157 /*!
57158  * @addtogroup PUF_Peripheral_Access_Layer PUF Peripheral Access Layer
57159  * @{
57160  */
57161 
57162 /** PUF - Register Layout Typedef */
57163 typedef struct {
57164   __IO uint32_t CR;                                /**< Control, offset: 0x0 */
57165   __I  uint32_t ORR;                               /**< Operation Result, offset: 0x4 */
57166   __IO uint32_t SR;                                /**< Status, offset: 0x8 */
57167   __I  uint32_t AR;                                /**< Allow, offset: 0xC */
57168   __IO uint32_t IER;                               /**< Interrupt Enable, offset: 0x10 */
57169   __IO uint32_t IMR;                               /**< Interrupt Mask, offset: 0x14 */
57170   __IO uint32_t ISR;                               /**< Interrupt Status, offset: 0x18 */
57171        uint8_t RESERVED_0[4];
57172   __IO uint32_t DATA_DEST;                         /**< Data Destination, offset: 0x20 */
57173   __IO uint32_t DATA_SRC;                          /**< Data Source, offset: 0x24 */
57174        uint8_t RESERVED_1[120];
57175   __O  uint32_t DIR;                               /**< Data Input, offset: 0xA0 */
57176        uint8_t RESERVED_2[4];
57177   __I  uint32_t DOR;                               /**< Data Output, offset: 0xA8 */
57178        uint8_t RESERVED_3[20];
57179   __IO uint32_t MISC;                              /**< Miscellaneous, offset: 0xC0 */
57180        uint8_t RESERVED_4[12];
57181   __IO uint32_t IF_SR;                             /**< Interface Status, offset: 0xD0 */
57182        uint8_t RESERVED_5[8];
57183   __I  uint32_t PSR;                               /**< PUF Score, offset: 0xDC */
57184   __I  uint32_t HW_RUC0;                           /**< Hardware Restrict User Context 0, offset: 0xE0 */
57185   __I  uint32_t HW_RUC1;                           /**< Hardware Restrict User Context 1, offset: 0xE4 */
57186        uint8_t RESERVED_6[12];
57187   __I  uint32_t HW_INFO;                           /**< Hardware Information, offset: 0xF4 */
57188   __I  uint32_t HW_ID;                             /**< Hardware Identifier, offset: 0xF8 */
57189   __I  uint32_t HW_VER;                            /**< Hardware Version, offset: 0xFC */
57190   __IO uint32_t CONFIG;                            /**< PUF command blocking configuration, offset: 0x100 */
57191   __IO uint32_t SEC_LOCK;                          /**< Security level lock, offset: 0x104 */
57192   __IO uint32_t APP_CTX_MASK;                      /**< Application defined context mask, offset: 0x108 */
57193        uint8_t RESERVED_7[500];
57194   __IO uint32_t SRAM_CFG;                          /**< SRAM Configuration, offset: 0x300 */
57195   __I  uint32_t SRAM_STATUS;                       /**< Status, offset: 0x304 */
57196        uint8_t RESERVED_8[208];
57197   __O  uint32_t SRAM_INT_CLR_ENABLE;               /**< Interrupt Enable Clear, offset: 0x3D8 */
57198   __O  uint32_t SRAM_INT_SET_ENABLE;               /**< Interrupt Enable Set, offset: 0x3DC */
57199   __I  uint32_t SRAM_INT_STATUS;                   /**< Interrupt Status, offset: 0x3E0 */
57200   __I  uint32_t SRAM_INT_ENABLE;                   /**< Interrupt Enable, offset: 0x3E4 */
57201   __O  uint32_t SRAM_INT_CLR_STATUS;               /**< Interrupt Status Clear, offset: 0x3E8 */
57202   __O  uint32_t SRAM_INT_SET_STATUS;               /**< Interrupt Status set, offset: 0x3EC */
57203 } PUF_Type;
57204 
57205 /* ----------------------------------------------------------------------------
57206    -- PUF Register Masks
57207    ---------------------------------------------------------------------------- */
57208 
57209 /*!
57210  * @addtogroup PUF_Register_Masks PUF Register Masks
57211  * @{
57212  */
57213 
57214 /*! @name CR - Control */
57215 /*! @{ */
57216 
57217 #define PUF_CR_ZEROIZE_MASK                      (0x1U)
57218 #define PUF_CR_ZEROIZE_SHIFT                     (0U)
57219 /*! ZEROIZE - Zeroize operation */
57220 #define PUF_CR_ZEROIZE(x)                        (((uint32_t)(((uint32_t)(x)) << PUF_CR_ZEROIZE_SHIFT)) & PUF_CR_ZEROIZE_MASK)
57221 
57222 #define PUF_CR_ENROLL_MASK                       (0x2U)
57223 #define PUF_CR_ENROLL_SHIFT                      (1U)
57224 /*! ENROLL - Enroll operation */
57225 #define PUF_CR_ENROLL(x)                         (((uint32_t)(((uint32_t)(x)) << PUF_CR_ENROLL_SHIFT)) & PUF_CR_ENROLL_MASK)
57226 
57227 #define PUF_CR_START_MASK                        (0x4U)
57228 #define PUF_CR_START_SHIFT                       (2U)
57229 /*! START - Start operation */
57230 #define PUF_CR_START(x)                          (((uint32_t)(((uint32_t)(x)) << PUF_CR_START_SHIFT)) & PUF_CR_START_MASK)
57231 
57232 #define PUF_CR_RECONSTRUCT_MASK                  (0x8U)
57233 #define PUF_CR_RECONSTRUCT_SHIFT                 (3U)
57234 /*! RECONSTRUCT - Reconstruct operation */
57235 #define PUF_CR_RECONSTRUCT(x)                    (((uint32_t)(((uint32_t)(x)) << PUF_CR_RECONSTRUCT_SHIFT)) & PUF_CR_RECONSTRUCT_MASK)
57236 
57237 #define PUF_CR_STOP_MASK                         (0x20U)
57238 #define PUF_CR_STOP_SHIFT                        (5U)
57239 /*! STOP - Stop operation */
57240 #define PUF_CR_STOP(x)                           (((uint32_t)(((uint32_t)(x)) << PUF_CR_STOP_SHIFT)) & PUF_CR_STOP_MASK)
57241 
57242 #define PUF_CR_GET_KEY_MASK                      (0x40U)
57243 #define PUF_CR_GET_KEY_SHIFT                     (6U)
57244 /*! GET_KEY - Get Key operation */
57245 #define PUF_CR_GET_KEY(x)                        (((uint32_t)(((uint32_t)(x)) << PUF_CR_GET_KEY_SHIFT)) & PUF_CR_GET_KEY_MASK)
57246 
57247 #define PUF_CR_UNWRAP_MASK                       (0x80U)
57248 #define PUF_CR_UNWRAP_SHIFT                      (7U)
57249 /*! UNWRAP - Unwrap operation */
57250 #define PUF_CR_UNWRAP(x)                         (((uint32_t)(((uint32_t)(x)) << PUF_CR_UNWRAP_SHIFT)) & PUF_CR_UNWRAP_MASK)
57251 
57252 #define PUF_CR_WRAP_GENERATED_RANDOM_MASK        (0x100U)
57253 #define PUF_CR_WRAP_GENERATED_RANDOM_SHIFT       (8U)
57254 /*! WRAP_GENERATED_RANDOM - Wrap Generated Random operation */
57255 #define PUF_CR_WRAP_GENERATED_RANDOM(x)          (((uint32_t)(((uint32_t)(x)) << PUF_CR_WRAP_GENERATED_RANDOM_SHIFT)) & PUF_CR_WRAP_GENERATED_RANDOM_MASK)
57256 
57257 #define PUF_CR_WRAP_MASK                         (0x200U)
57258 #define PUF_CR_WRAP_SHIFT                        (9U)
57259 /*! WRAP - Wrap operation */
57260 #define PUF_CR_WRAP(x)                           (((uint32_t)(((uint32_t)(x)) << PUF_CR_WRAP_SHIFT)) & PUF_CR_WRAP_MASK)
57261 
57262 #define PUF_CR_GENERATE_RANDOM_MASK              (0x8000U)
57263 #define PUF_CR_GENERATE_RANDOM_SHIFT             (15U)
57264 /*! GENERATE_RANDOM - Generate Random operation */
57265 #define PUF_CR_GENERATE_RANDOM(x)                (((uint32_t)(((uint32_t)(x)) << PUF_CR_GENERATE_RANDOM_SHIFT)) & PUF_CR_GENERATE_RANDOM_MASK)
57266 
57267 #define PUF_CR_TEST_MEMORY_MASK                  (0x40000000U)
57268 #define PUF_CR_TEST_MEMORY_SHIFT                 (30U)
57269 /*! TEST_MEMORY - Test memory operation */
57270 #define PUF_CR_TEST_MEMORY(x)                    (((uint32_t)(((uint32_t)(x)) << PUF_CR_TEST_MEMORY_SHIFT)) & PUF_CR_TEST_MEMORY_MASK)
57271 
57272 #define PUF_CR_TEST_PUF_MASK                     (0x80000000U)
57273 #define PUF_CR_TEST_PUF_SHIFT                    (31U)
57274 /*! TEST_PUF - Test PUF operation */
57275 #define PUF_CR_TEST_PUF(x)                       (((uint32_t)(((uint32_t)(x)) << PUF_CR_TEST_PUF_SHIFT)) & PUF_CR_TEST_PUF_MASK)
57276 /*! @} */
57277 
57278 /*! @name ORR - Operation Result */
57279 /*! @{ */
57280 
57281 #define PUF_ORR_RESULT_CODE_MASK                 (0xFFU)
57282 #define PUF_ORR_RESULT_CODE_SHIFT                (0U)
57283 /*! RESULT_CODE - Result code of last operation
57284  *  0b00000000..Indicates that the last operation was successful or operation is in progress.
57285  *  0b11110000..Indicates that the AC is not for the current product/version.
57286  *  0b11110001..Indicates that the AC in the second phase is not for the current product/version.
57287  *  0b11110010..Indicates that the AC is corrupted.
57288  *  0b11110011..Indicates that the AC in the second phase is corrupted.
57289  *  0b11110100..Indicates that the authentication of the provided AC failed.
57290  *  0b11110101..Indicates that the authentication of the provided AC failed in the second phase.
57291  *  0b11110110..Indicates that the SRAM PUF quality verification fails.
57292  *  0b11110111..Indicates that the incorrect or unsupported context is provided.
57293  *  0b11111000..Indicates that a data destination was set that is not allowed according to other settings and the current PUF state.
57294  *  0b11111111..Indicates that the PUF SRAM access has failed.
57295  */
57296 #define PUF_ORR_RESULT_CODE(x)                   (((uint32_t)(((uint32_t)(x)) << PUF_ORR_RESULT_CODE_SHIFT)) & PUF_ORR_RESULT_CODE_MASK)
57297 
57298 #define PUF_ORR_LAST_OPERATION_MASK              (0xFF000000U)
57299 #define PUF_ORR_LAST_OPERATION_SHIFT             (24U)
57300 /*! LAST_OPERATION - Last operation type
57301  *  0b00000000..Indicates that the operation is in progress.
57302  *  0b00000001..Indicates that the last operation was Enroll.
57303  *  0b00000010..Indicates that the last operation was Start.
57304  *  0b00000011..Indicates that the last operation was Reconstruct
57305  *  0b00000101..Indicates that the last operation was Stop.
57306  *  0b00000110..Indicates that the last operation was Get Key.
57307  *  0b00000111..Indicates that the last operation was Unwrap.
57308  *  0b00001000..Indicates that the last operation was Wrap Generated Random.
57309  *  0b00001001..Indicates that the last operation was Wrap.
57310  *  0b00001111..Indicates that the last operation was Generate Random.
57311  *  0b00011110..Indicates that the last operation was Test Memory.
57312  *  0b00011111..Indicates that the last operation was Test PUF.
57313  *  0b00100000..Indicates that the last operation was Initialization.
57314  *  0b00101111..Indicates that the last operation was Zeroize.
57315  */
57316 #define PUF_ORR_LAST_OPERATION(x)                (((uint32_t)(((uint32_t)(x)) << PUF_ORR_LAST_OPERATION_SHIFT)) & PUF_ORR_LAST_OPERATION_MASK)
57317 /*! @} */
57318 
57319 /*! @name SR - Status */
57320 /*! @{ */
57321 
57322 #define PUF_SR_BUSY_MASK                         (0x1U)
57323 #define PUF_SR_BUSY_SHIFT                        (0U)
57324 /*! BUSY - Operation in progress */
57325 #define PUF_SR_BUSY(x)                           (((uint32_t)(((uint32_t)(x)) << PUF_SR_BUSY_SHIFT)) & PUF_SR_BUSY_MASK)
57326 
57327 #define PUF_SR_OK_MASK                           (0x2U)
57328 #define PUF_SR_OK_SHIFT                          (1U)
57329 /*! OK - Last operation successful */
57330 #define PUF_SR_OK(x)                             (((uint32_t)(((uint32_t)(x)) << PUF_SR_OK_SHIFT)) & PUF_SR_OK_MASK)
57331 
57332 #define PUF_SR_ERROR_MASK                        (0x4U)
57333 #define PUF_SR_ERROR_SHIFT                       (2U)
57334 /*! ERROR - Last operation failed */
57335 #define PUF_SR_ERROR(x)                          (((uint32_t)(((uint32_t)(x)) << PUF_SR_ERROR_SHIFT)) & PUF_SR_ERROR_MASK)
57336 
57337 #define PUF_SR_ZEROIZED_MASK                     (0x8U)
57338 #define PUF_SR_ZEROIZED_SHIFT                    (3U)
57339 /*! ZEROIZED - Zeroized or Locked state */
57340 #define PUF_SR_ZEROIZED(x)                       (((uint32_t)(((uint32_t)(x)) << PUF_SR_ZEROIZED_SHIFT)) & PUF_SR_ZEROIZED_MASK)
57341 
57342 #define PUF_SR_REJECTED_MASK                     (0x10U)
57343 #define PUF_SR_REJECTED_SHIFT                    (4U)
57344 /*! REJECTED - Operation rejected */
57345 #define PUF_SR_REJECTED(x)                       (((uint32_t)(((uint32_t)(x)) << PUF_SR_REJECTED_SHIFT)) & PUF_SR_REJECTED_MASK)
57346 
57347 #define PUF_SR_DI_REQUEST_MASK                   (0x20U)
57348 #define PUF_SR_DI_REQUEST_SHIFT                  (5U)
57349 /*! DI_REQUEST - Indicates the request for data in transfer via the DIR register */
57350 #define PUF_SR_DI_REQUEST(x)                     (((uint32_t)(((uint32_t)(x)) << PUF_SR_DI_REQUEST_SHIFT)) & PUF_SR_DI_REQUEST_MASK)
57351 
57352 #define PUF_SR_DO_REQUEST_MASK                   (0x40U)
57353 #define PUF_SR_DO_REQUEST_SHIFT                  (6U)
57354 /*! DO_REQUEST - Indicates the request for data out transfer via the DOR register */
57355 #define PUF_SR_DO_REQUEST(x)                     (((uint32_t)(((uint32_t)(x)) << PUF_SR_DO_REQUEST_SHIFT)) & PUF_SR_DO_REQUEST_MASK)
57356 /*! @} */
57357 
57358 /*! @name AR - Allow */
57359 /*! @{ */
57360 
57361 #define PUF_AR_ALLOW_ENROLL_MASK                 (0x2U)
57362 #define PUF_AR_ALLOW_ENROLL_SHIFT                (1U)
57363 /*! ALLOW_ENROLL - Enroll operation
57364  *  0b0..Indicates that the Enroll operation is not allowed
57365  *  0b1..Indicates that the Enroll operation is allowed
57366  */
57367 #define PUF_AR_ALLOW_ENROLL(x)                   (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_ENROLL_SHIFT)) & PUF_AR_ALLOW_ENROLL_MASK)
57368 
57369 #define PUF_AR_ALLOW_START_MASK                  (0x4U)
57370 #define PUF_AR_ALLOW_START_SHIFT                 (2U)
57371 /*! ALLOW_START - Start operation
57372  *  0b0..Indicates that the Start operation is not allowed
57373  *  0b1..Indicates that the Start operation is allowed
57374  */
57375 #define PUF_AR_ALLOW_START(x)                    (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_START_SHIFT)) & PUF_AR_ALLOW_START_MASK)
57376 
57377 #define PUF_AR_ALLOW_RECONSTRUCT_MASK            (0x8U)
57378 #define PUF_AR_ALLOW_RECONSTRUCT_SHIFT           (3U)
57379 /*! ALLOW_RECONSTRUCT - Reconstruct operation
57380  *  0b0..Indicates that the Reconstruct operation is not allowed
57381  *  0b1..Indicates that the Reconstruct operation is allowed
57382  */
57383 #define PUF_AR_ALLOW_RECONSTRUCT(x)              (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_RECONSTRUCT_SHIFT)) & PUF_AR_ALLOW_RECONSTRUCT_MASK)
57384 
57385 #define PUF_AR_ALLOW_STOP_MASK                   (0x20U)
57386 #define PUF_AR_ALLOW_STOP_SHIFT                  (5U)
57387 /*! ALLOW_STOP - Stop operation
57388  *  0b0..Indicates that the Stop operation is not allowed
57389  *  0b1..Indicates that the Stop operation is allowed
57390  */
57391 #define PUF_AR_ALLOW_STOP(x)                     (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_STOP_SHIFT)) & PUF_AR_ALLOW_STOP_MASK)
57392 
57393 #define PUF_AR_ALLOW_GET_KEY_MASK                (0x40U)
57394 #define PUF_AR_ALLOW_GET_KEY_SHIFT               (6U)
57395 /*! ALLOW_GET_KEY - Get Key operation
57396  *  0b0..Indicates that the Get Key operation is not allowed
57397  *  0b1..Indicates that the Get Key operation is allowed
57398  */
57399 #define PUF_AR_ALLOW_GET_KEY(x)                  (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_GET_KEY_SHIFT)) & PUF_AR_ALLOW_GET_KEY_MASK)
57400 
57401 #define PUF_AR_ALLOW_UNWRAP_MASK                 (0x80U)
57402 #define PUF_AR_ALLOW_UNWRAP_SHIFT                (7U)
57403 /*! ALLOW_UNWRAP - Unwrap operation
57404  *  0b0..Indicates that the Unwrap operation is not allowed
57405  *  0b1..Indicates that the Unwrap operation is allowed
57406  */
57407 #define PUF_AR_ALLOW_UNWRAP(x)                   (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_UNWRAP_SHIFT)) & PUF_AR_ALLOW_UNWRAP_MASK)
57408 
57409 #define PUF_AR_ALLOW_WRAP_GENERATED_RANDOM_MASK  (0x100U)
57410 #define PUF_AR_ALLOW_WRAP_GENERATED_RANDOM_SHIFT (8U)
57411 /*! ALLOW_WRAP_GENERATED_RANDOM - Wrap Generated Random operation
57412  *  0b0..Indicates that the Wrap Generated Random operation is not allowed
57413  *  0b1..Indicates that the Wrap Generated Random operation is allowed
57414  */
57415 #define PUF_AR_ALLOW_WRAP_GENERATED_RANDOM(x)    (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_WRAP_GENERATED_RANDOM_SHIFT)) & PUF_AR_ALLOW_WRAP_GENERATED_RANDOM_MASK)
57416 
57417 #define PUF_AR_ALLOW_WRAP_MASK                   (0x200U)
57418 #define PUF_AR_ALLOW_WRAP_SHIFT                  (9U)
57419 /*! ALLOW_WRAP - Wrap operation
57420  *  0b0..Indicates that the Wrap operation is not allowed
57421  *  0b1..Indicates that the Wrap operation is allowed
57422  */
57423 #define PUF_AR_ALLOW_WRAP(x)                     (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_WRAP_SHIFT)) & PUF_AR_ALLOW_WRAP_MASK)
57424 
57425 #define PUF_AR_ALLOW_GENERATE_RANDOM_MASK        (0x8000U)
57426 #define PUF_AR_ALLOW_GENERATE_RANDOM_SHIFT       (15U)
57427 /*! ALLOW_GENERATE_RANDOM - Generate Random operation
57428  *  0b0..Indicates that the Generate Random operation is not allowed
57429  *  0b1..Indicates that the Generate Random operation is allowed
57430  */
57431 #define PUF_AR_ALLOW_GENERATE_RANDOM(x)          (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_GENERATE_RANDOM_SHIFT)) & PUF_AR_ALLOW_GENERATE_RANDOM_MASK)
57432 
57433 #define PUF_AR_ALLOW_TEST_MEMORY_MASK            (0x40000000U)
57434 #define PUF_AR_ALLOW_TEST_MEMORY_SHIFT           (30U)
57435 /*! ALLOW_TEST_MEMORY
57436  *  0b0..Indicates that the Test Memory operation is not allowed
57437  *  0b1..Indicates that the Test Memory operation is allowed
57438  */
57439 #define PUF_AR_ALLOW_TEST_MEMORY(x)              (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_TEST_MEMORY_SHIFT)) & PUF_AR_ALLOW_TEST_MEMORY_MASK)
57440 
57441 #define PUF_AR_ALLOW_TEST_PUF_MASK               (0x80000000U)
57442 #define PUF_AR_ALLOW_TEST_PUF_SHIFT              (31U)
57443 /*! ALLOW_TEST_PUF - Test PUF operation
57444  *  0b0..Test PUF operation is not allowed
57445  *  0b1..Test PUF operation is allowed
57446  */
57447 #define PUF_AR_ALLOW_TEST_PUF(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_TEST_PUF_SHIFT)) & PUF_AR_ALLOW_TEST_PUF_MASK)
57448 /*! @} */
57449 
57450 /*! @name IER - Interrupt Enable */
57451 /*! @{ */
57452 
57453 #define PUF_IER_INT_EN_MASK                      (0x1U)
57454 #define PUF_IER_INT_EN_SHIFT                     (0U)
57455 /*! INT_EN - Interrupt enable
57456  *  0b0..Disables all PUF interrupts
57457  *  0b1..Enables all PUF interrupts that are enabled in the Interrupt Mask register
57458  */
57459 #define PUF_IER_INT_EN(x)                        (((uint32_t)(((uint32_t)(x)) << PUF_IER_INT_EN_SHIFT)) & PUF_IER_INT_EN_MASK)
57460 /*! @} */
57461 
57462 /*! @name IMR - Interrupt Mask */
57463 /*! @{ */
57464 
57465 #define PUF_IMR_INT_EN_BUSY_MASK                 (0x1U)
57466 #define PUF_IMR_INT_EN_BUSY_SHIFT                (0U)
57467 /*! INT_EN_BUSY - Busy interrupt */
57468 #define PUF_IMR_INT_EN_BUSY(x)                   (((uint32_t)(((uint32_t)(x)) << PUF_IMR_INT_EN_BUSY_SHIFT)) & PUF_IMR_INT_EN_BUSY_MASK)
57469 
57470 #define PUF_IMR_INT_EN_OK_MASK                   (0x2U)
57471 #define PUF_IMR_INT_EN_OK_SHIFT                  (1U)
57472 /*! INT_EN_OK - Ok interrupt */
57473 #define PUF_IMR_INT_EN_OK(x)                     (((uint32_t)(((uint32_t)(x)) << PUF_IMR_INT_EN_OK_SHIFT)) & PUF_IMR_INT_EN_OK_MASK)
57474 
57475 #define PUF_IMR_INT_EN_ERROR_MASK                (0x4U)
57476 #define PUF_IMR_INT_EN_ERROR_SHIFT               (2U)
57477 /*! INT_EN_ERROR - Error interrupt */
57478 #define PUF_IMR_INT_EN_ERROR(x)                  (((uint32_t)(((uint32_t)(x)) << PUF_IMR_INT_EN_ERROR_SHIFT)) & PUF_IMR_INT_EN_ERROR_MASK)
57479 
57480 #define PUF_IMR_INT_EN_ZEROIZED_MASK             (0x8U)
57481 #define PUF_IMR_INT_EN_ZEROIZED_SHIFT            (3U)
57482 /*! INT_EN_ZEROIZED - Zeroized interrupt */
57483 #define PUF_IMR_INT_EN_ZEROIZED(x)               (((uint32_t)(((uint32_t)(x)) << PUF_IMR_INT_EN_ZEROIZED_SHIFT)) & PUF_IMR_INT_EN_ZEROIZED_MASK)
57484 
57485 #define PUF_IMR_INT_EN_REJECTED_MASK             (0x10U)
57486 #define PUF_IMR_INT_EN_REJECTED_SHIFT            (4U)
57487 /*! INT_EN_REJECTED - Rejected interrupt */
57488 #define PUF_IMR_INT_EN_REJECTED(x)               (((uint32_t)(((uint32_t)(x)) << PUF_IMR_INT_EN_REJECTED_SHIFT)) & PUF_IMR_INT_EN_REJECTED_MASK)
57489 
57490 #define PUF_IMR_INT_EN_DI_REQUEST_MASK           (0x20U)
57491 #define PUF_IMR_INT_EN_DI_REQUEST_SHIFT          (5U)
57492 /*! INT_EN_DI_REQUEST - Data in request interrupt */
57493 #define PUF_IMR_INT_EN_DI_REQUEST(x)             (((uint32_t)(((uint32_t)(x)) << PUF_IMR_INT_EN_DI_REQUEST_SHIFT)) & PUF_IMR_INT_EN_DI_REQUEST_MASK)
57494 
57495 #define PUF_IMR_INT_EN_DO_REQUEST_MASK           (0x40U)
57496 #define PUF_IMR_INT_EN_DO_REQUEST_SHIFT          (6U)
57497 /*! INT_EN_DO_REQUEST - Data out request interrupt */
57498 #define PUF_IMR_INT_EN_DO_REQUEST(x)             (((uint32_t)(((uint32_t)(x)) << PUF_IMR_INT_EN_DO_REQUEST_SHIFT)) & PUF_IMR_INT_EN_DO_REQUEST_MASK)
57499 /*! @} */
57500 
57501 /*! @name ISR - Interrupt Status */
57502 /*! @{ */
57503 
57504 #define PUF_ISR_INT_BUSY_MASK                    (0x1U)
57505 #define PUF_ISR_INT_BUSY_SHIFT                   (0U)
57506 /*! INT_BUSY - Negative edge occurred on Busy */
57507 #define PUF_ISR_INT_BUSY(x)                      (((uint32_t)(((uint32_t)(x)) << PUF_ISR_INT_BUSY_SHIFT)) & PUF_ISR_INT_BUSY_MASK)
57508 
57509 #define PUF_ISR_INT_OK_MASK                      (0x2U)
57510 #define PUF_ISR_INT_OK_SHIFT                     (1U)
57511 /*! INT_OK - Positive edge occurred on Ok */
57512 #define PUF_ISR_INT_OK(x)                        (((uint32_t)(((uint32_t)(x)) << PUF_ISR_INT_OK_SHIFT)) & PUF_ISR_INT_OK_MASK)
57513 
57514 #define PUF_ISR_INT_ERROR_MASK                   (0x4U)
57515 #define PUF_ISR_INT_ERROR_SHIFT                  (2U)
57516 /*! INT_ERROR - Positive edge occurred on Error */
57517 #define PUF_ISR_INT_ERROR(x)                     (((uint32_t)(((uint32_t)(x)) << PUF_ISR_INT_ERROR_SHIFT)) & PUF_ISR_INT_ERROR_MASK)
57518 
57519 #define PUF_ISR_INT_ZEROIZED_MASK                (0x8U)
57520 #define PUF_ISR_INT_ZEROIZED_SHIFT               (3U)
57521 /*! INT_ZEROIZED - Positive edge occurred on Zeroized */
57522 #define PUF_ISR_INT_ZEROIZED(x)                  (((uint32_t)(((uint32_t)(x)) << PUF_ISR_INT_ZEROIZED_SHIFT)) & PUF_ISR_INT_ZEROIZED_MASK)
57523 
57524 #define PUF_ISR_INT_REJECTED_MASK                (0x10U)
57525 #define PUF_ISR_INT_REJECTED_SHIFT               (4U)
57526 /*! INT_REJECTED - Positive edge occurred on Rejected */
57527 #define PUF_ISR_INT_REJECTED(x)                  (((uint32_t)(((uint32_t)(x)) << PUF_ISR_INT_REJECTED_SHIFT)) & PUF_ISR_INT_REJECTED_MASK)
57528 
57529 #define PUF_ISR_INT_DI_REQUEST_MASK              (0x20U)
57530 #define PUF_ISR_INT_DI_REQUEST_SHIFT             (5U)
57531 /*! INT_DI_REQUEST - Positive edge occurred on di_request */
57532 #define PUF_ISR_INT_DI_REQUEST(x)                (((uint32_t)(((uint32_t)(x)) << PUF_ISR_INT_DI_REQUEST_SHIFT)) & PUF_ISR_INT_DI_REQUEST_MASK)
57533 
57534 #define PUF_ISR_INT_DO_REQUEST_MASK              (0x40U)
57535 #define PUF_ISR_INT_DO_REQUEST_SHIFT             (6U)
57536 /*! INT_DO_REQUEST - Positive edge occurred on do_request */
57537 #define PUF_ISR_INT_DO_REQUEST(x)                (((uint32_t)(((uint32_t)(x)) << PUF_ISR_INT_DO_REQUEST_SHIFT)) & PUF_ISR_INT_DO_REQUEST_MASK)
57538 /*! @} */
57539 
57540 /*! @name DATA_DEST - Data Destination */
57541 /*! @{ */
57542 
57543 #define PUF_DATA_DEST_DEST_DOR_MASK              (0x1U)
57544 #define PUF_DATA_DEST_DEST_DOR_SHIFT             (0U)
57545 /*! DEST_DOR - Key available via the DOR register */
57546 #define PUF_DATA_DEST_DEST_DOR(x)                (((uint32_t)(((uint32_t)(x)) << PUF_DATA_DEST_DEST_DOR_SHIFT)) & PUF_DATA_DEST_DEST_DOR_MASK)
57547 
57548 #define PUF_DATA_DEST_DEST_SO_MASK               (0x2U)
57549 #define PUF_DATA_DEST_DEST_SO_SHIFT              (1U)
57550 /*! DEST_SO - Key available to ELS */
57551 #define PUF_DATA_DEST_DEST_SO(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_DATA_DEST_DEST_SO_SHIFT)) & PUF_DATA_DEST_DEST_SO_MASK)
57552 /*! @} */
57553 
57554 /*! @name DATA_SRC - Data Source */
57555 /*! @{ */
57556 
57557 #define PUF_DATA_SRC_SRC_DIR_MASK                (0x1U)
57558 #define PUF_DATA_SRC_SRC_DIR_SHIFT               (0U)
57559 /*! SRC_DIR - Data provided via the DIR register */
57560 #define PUF_DATA_SRC_SRC_DIR(x)                  (((uint32_t)(((uint32_t)(x)) << PUF_DATA_SRC_SRC_DIR_SHIFT)) & PUF_DATA_SRC_SRC_DIR_MASK)
57561 
57562 #define PUF_DATA_SRC_SRC_SI_MASK                 (0x2U)
57563 #define PUF_DATA_SRC_SRC_SI_SHIFT                (1U)
57564 /*! SRC_SI - Data provided via the SI interface */
57565 #define PUF_DATA_SRC_SRC_SI(x)                   (((uint32_t)(((uint32_t)(x)) << PUF_DATA_SRC_SRC_SI_SHIFT)) & PUF_DATA_SRC_SRC_SI_MASK)
57566 /*! @} */
57567 
57568 /*! @name DIR - Data Input */
57569 /*! @{ */
57570 
57571 #define PUF_DIR_DI_MASK                          (0xFFFFFFFFU)
57572 #define PUF_DIR_DI_SHIFT                         (0U)
57573 /*! DI - Input data */
57574 #define PUF_DIR_DI(x)                            (((uint32_t)(((uint32_t)(x)) << PUF_DIR_DI_SHIFT)) & PUF_DIR_DI_MASK)
57575 /*! @} */
57576 
57577 /*! @name DOR - Data Output */
57578 /*! @{ */
57579 
57580 #define PUF_DOR_DO_MASK                          (0xFFFFFFFFU)
57581 #define PUF_DOR_DO_SHIFT                         (0U)
57582 /*! DO - Output data */
57583 #define PUF_DOR_DO(x)                            (((uint32_t)(((uint32_t)(x)) << PUF_DOR_DO_SHIFT)) & PUF_DOR_DO_MASK)
57584 /*! @} */
57585 
57586 /*! @name MISC - Miscellaneous */
57587 /*! @{ */
57588 
57589 #define PUF_MISC_DATA_ENDIANNESS_MASK            (0x1U)
57590 #define PUF_MISC_DATA_ENDIANNESS_SHIFT           (0U)
57591 /*! DATA_ENDIANNESS - Defines the endianness of data in DIR and DOR:
57592  *  0b0..Little endian
57593  *  0b1..Big endian (default)
57594  */
57595 #define PUF_MISC_DATA_ENDIANNESS(x)              (((uint32_t)(((uint32_t)(x)) << PUF_MISC_DATA_ENDIANNESS_SHIFT)) & PUF_MISC_DATA_ENDIANNESS_MASK)
57596 /*! @} */
57597 
57598 /*! @name IF_SR - Interface Status */
57599 /*! @{ */
57600 
57601 #define PUF_IF_SR_APB_ERROR_MASK                 (0x1U)
57602 #define PUF_IF_SR_APB_ERROR_SHIFT                (0U)
57603 /*! APB_ERROR - APB error */
57604 #define PUF_IF_SR_APB_ERROR(x)                   (((uint32_t)(((uint32_t)(x)) << PUF_IF_SR_APB_ERROR_SHIFT)) & PUF_IF_SR_APB_ERROR_MASK)
57605 /*! @} */
57606 
57607 /*! @name PSR - PUF Score */
57608 /*! @{ */
57609 
57610 #define PUF_PSR_PUF_SCORE_MASK                   (0xFU)
57611 #define PUF_PSR_PUF_SCORE_SHIFT                  (0U)
57612 /*! PUF_SCORE - Provides the PUF score obtained during the last Test PUF, Enroll or Start operation. */
57613 #define PUF_PSR_PUF_SCORE(x)                     (((uint32_t)(((uint32_t)(x)) << PUF_PSR_PUF_SCORE_SHIFT)) & PUF_PSR_PUF_SCORE_MASK)
57614 /*! @} */
57615 
57616 /*! @name HW_RUC0 - Hardware Restrict User Context 0 */
57617 /*! @{ */
57618 
57619 #define PUF_HW_RUC0_LC_STATE_MASK                (0xFFU)
57620 #define PUF_HW_RUC0_LC_STATE_SHIFT               (0U)
57621 /*! LC_STATE - Life cycle state based restrictions
57622  *  0b00000011..OEM Develop
57623  *  0b00000111..OEM Develop 2
57624  *  0b00001111..OEM In-field
57625  *  0b00011111..OEM Field return
57626  *  0b00111111..NXP Field Return/Failure Analysis
57627  *  0b11001111..In-field Locked
57628  *  0b11111111..Bricked
57629  */
57630 #define PUF_HW_RUC0_LC_STATE(x)                  (((uint32_t)(((uint32_t)(x)) << PUF_HW_RUC0_LC_STATE_SHIFT)) & PUF_HW_RUC0_LC_STATE_MASK)
57631 
57632 #define PUF_HW_RUC0_BOOT_STATE_MASK              (0xFFFF00U)
57633 #define PUF_HW_RUC0_BOOT_STATE_SHIFT             (8U)
57634 /*! BOOT_STATE - Temporal boot state */
57635 #define PUF_HW_RUC0_BOOT_STATE(x)                (((uint32_t)(((uint32_t)(x)) << PUF_HW_RUC0_BOOT_STATE_SHIFT)) & PUF_HW_RUC0_BOOT_STATE_MASK)
57636 
57637 #define PUF_HW_RUC0_CPU0_DEBUG_MASK              (0x1000000U)
57638 #define PUF_HW_RUC0_CPU0_DEBUG_SHIFT             (24U)
57639 /*! CPU0_DEBUG - Disable key access when debugger is attached to CPU0 after power-up */
57640 #define PUF_HW_RUC0_CPU0_DEBUG(x)                (((uint32_t)(((uint32_t)(x)) << PUF_HW_RUC0_CPU0_DEBUG_SHIFT)) & PUF_HW_RUC0_CPU0_DEBUG_MASK)
57641 
57642 #define PUF_HW_RUC0_COOLFLUX_DEBUG_MASK          (0x2000000U)
57643 #define PUF_HW_RUC0_COOLFLUX_DEBUG_SHIFT         (25U)
57644 /*! COOLFLUX_DEBUG - Disable key access when debugger is attached to COOLFLUX after power-up */
57645 #define PUF_HW_RUC0_COOLFLUX_DEBUG(x)            (((uint32_t)(((uint32_t)(x)) << PUF_HW_RUC0_COOLFLUX_DEBUG_SHIFT)) & PUF_HW_RUC0_COOLFLUX_DEBUG_MASK)
57646 
57647 #define PUF_HW_RUC0_dsp_debug_MASK               (0x4000000U)
57648 #define PUF_HW_RUC0_dsp_debug_SHIFT              (26U)
57649 /*! dsp_debug - DSP debug status. */
57650 #define PUF_HW_RUC0_dsp_debug(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_HW_RUC0_dsp_debug_SHIFT)) & PUF_HW_RUC0_dsp_debug_MASK)
57651 
57652 #define PUF_HW_RUC0_ACCESS_LEVEL_MASK            (0xF0000000U)
57653 #define PUF_HW_RUC0_ACCESS_LEVEL_SHIFT           (28U)
57654 /*! ACCESS_LEVEL - Restrict the key access based on TrustZone security level */
57655 #define PUF_HW_RUC0_ACCESS_LEVEL(x)              (((uint32_t)(((uint32_t)(x)) << PUF_HW_RUC0_ACCESS_LEVEL_SHIFT)) & PUF_HW_RUC0_ACCESS_LEVEL_MASK)
57656 /*! @} */
57657 
57658 /*! @name HW_RUC1 - Hardware Restrict User Context 1 */
57659 /*! @{ */
57660 
57661 #define PUF_HW_RUC1_APP_CTX_MASK                 (0xFFFFFFFFU)
57662 #define PUF_HW_RUC1_APP_CTX_SHIFT                (0U)
57663 /*! APP_CTX - Application customizable context */
57664 #define PUF_HW_RUC1_APP_CTX(x)                   (((uint32_t)(((uint32_t)(x)) << PUF_HW_RUC1_APP_CTX_SHIFT)) & PUF_HW_RUC1_APP_CTX_MASK)
57665 /*! @} */
57666 
57667 /*! @name HW_INFO - Hardware Information */
57668 /*! @{ */
57669 
57670 #define PUF_HW_INFO_CONFIG_WRAP_MASK             (0x1000000U)
57671 #define PUF_HW_INFO_CONFIG_WRAP_SHIFT            (24U)
57672 /*! CONFIG_WRAP - Wrap configuration
57673  *  0b0..Indicates that Wrap is not included
57674  *  0b1..Indicates that Wrap is included
57675  */
57676 #define PUF_HW_INFO_CONFIG_WRAP(x)               (((uint32_t)(((uint32_t)(x)) << PUF_HW_INFO_CONFIG_WRAP_SHIFT)) & PUF_HW_INFO_CONFIG_WRAP_MASK)
57677 
57678 #define PUF_HW_INFO_CONFIG_TYPE_MASK             (0xF0000000U)
57679 #define PUF_HW_INFO_CONFIG_TYPE_SHIFT            (28U)
57680 /*! CONFIG_TYPE - PUF configuration
57681  *  0b0001..Indicates that PUF configuration is Safe.
57682  *  0b0010..Indicates that PUF configuration is Plus.
57683  */
57684 #define PUF_HW_INFO_CONFIG_TYPE(x)               (((uint32_t)(((uint32_t)(x)) << PUF_HW_INFO_CONFIG_TYPE_SHIFT)) & PUF_HW_INFO_CONFIG_TYPE_MASK)
57685 /*! @} */
57686 
57687 /*! @name HW_ID - Hardware Identifier */
57688 /*! @{ */
57689 
57690 #define PUF_HW_ID_HW_ID_MASK                     (0xFFFFFFFFU)
57691 #define PUF_HW_ID_HW_ID_SHIFT                    (0U)
57692 /*! HW_ID - Provides the hardware identifier */
57693 #define PUF_HW_ID_HW_ID(x)                       (((uint32_t)(((uint32_t)(x)) << PUF_HW_ID_HW_ID_SHIFT)) & PUF_HW_ID_HW_ID_MASK)
57694 /*! @} */
57695 
57696 /*! @name HW_VER - Hardware Version */
57697 /*! @{ */
57698 
57699 #define PUF_HW_VER_HW_REV_MASK                   (0xFFU)
57700 #define PUF_HW_VER_HW_REV_SHIFT                  (0U)
57701 /*! HW_REV - Provides the hardware version, patch part */
57702 #define PUF_HW_VER_HW_REV(x)                     (((uint32_t)(((uint32_t)(x)) << PUF_HW_VER_HW_REV_SHIFT)) & PUF_HW_VER_HW_REV_MASK)
57703 
57704 #define PUF_HW_VER_HW_VERSION_MINOR_MASK         (0xFF00U)
57705 #define PUF_HW_VER_HW_VERSION_MINOR_SHIFT        (8U)
57706 /*! HW_VERSION_MINOR - Provides the hardware version, minor part */
57707 #define PUF_HW_VER_HW_VERSION_MINOR(x)           (((uint32_t)(((uint32_t)(x)) << PUF_HW_VER_HW_VERSION_MINOR_SHIFT)) & PUF_HW_VER_HW_VERSION_MINOR_MASK)
57708 
57709 #define PUF_HW_VER_HW_VERSION_MAJOR_MASK         (0xFF0000U)
57710 #define PUF_HW_VER_HW_VERSION_MAJOR_SHIFT        (16U)
57711 /*! HW_VERSION_MAJOR - Provides the hardware version, major part */
57712 #define PUF_HW_VER_HW_VERSION_MAJOR(x)           (((uint32_t)(((uint32_t)(x)) << PUF_HW_VER_HW_VERSION_MAJOR_SHIFT)) & PUF_HW_VER_HW_VERSION_MAJOR_MASK)
57713 /*! @} */
57714 
57715 /*! @name CONFIG - PUF command blocking configuration */
57716 /*! @{ */
57717 
57718 #define PUF_CONFIG_DIS_PUF_ENROLL_MASK           (0x2U)
57719 #define PUF_CONFIG_DIS_PUF_ENROLL_SHIFT          (1U)
57720 /*! DIS_PUF_ENROLL - Disable PUF enroll command
57721  *  0b0..Command enabled
57722  *  0b1..Command disabled
57723  */
57724 #define PUF_CONFIG_DIS_PUF_ENROLL(x)             (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_ENROLL_SHIFT)) & PUF_CONFIG_DIS_PUF_ENROLL_MASK)
57725 
57726 #define PUF_CONFIG_DIS_PUF_START_MASK            (0x4U)
57727 #define PUF_CONFIG_DIS_PUF_START_SHIFT           (2U)
57728 /*! DIS_PUF_START - Disable PUF start command
57729  *  0b0..Command enabled
57730  *  0b1..Command disabled
57731  */
57732 #define PUF_CONFIG_DIS_PUF_START(x)              (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_START_SHIFT)) & PUF_CONFIG_DIS_PUF_START_MASK)
57733 
57734 #define PUF_CONFIG_DIS_PUF_STOP_MASK             (0x20U)
57735 #define PUF_CONFIG_DIS_PUF_STOP_SHIFT            (5U)
57736 /*! DIS_PUF_STOP - Disable PUF stop command
57737  *  0b0..Command enabled
57738  *  0b1..Command disabled
57739  */
57740 #define PUF_CONFIG_DIS_PUF_STOP(x)               (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_STOP_SHIFT)) & PUF_CONFIG_DIS_PUF_STOP_MASK)
57741 
57742 #define PUF_CONFIG_DIS_PUF_GET_KEY_MASK          (0x40U)
57743 #define PUF_CONFIG_DIS_PUF_GET_KEY_SHIFT         (6U)
57744 /*! DIS_PUF_GET_KEY - Disable PUF get key command
57745  *  0b0..Command enabled
57746  *  0b1..Command disabled
57747  */
57748 #define PUF_CONFIG_DIS_PUF_GET_KEY(x)            (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_GET_KEY_SHIFT)) & PUF_CONFIG_DIS_PUF_GET_KEY_MASK)
57749 
57750 #define PUF_CONFIG_DIS_PUF_UNWRAP_KEY_MASK       (0x80U)
57751 #define PUF_CONFIG_DIS_PUF_UNWRAP_KEY_SHIFT      (7U)
57752 /*! DIS_PUF_UNWRAP_KEY - Disable PUF unwrap key command
57753  *  0b0..Command enabled
57754  *  0b1..Command disabled
57755  */
57756 #define PUF_CONFIG_DIS_PUF_UNWRAP_KEY(x)         (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_UNWRAP_KEY_SHIFT)) & PUF_CONFIG_DIS_PUF_UNWRAP_KEY_MASK)
57757 
57758 #define PUF_CONFIG_DIS_PUF_GEN_WRAP_KEY_MASK     (0x100U)
57759 #define PUF_CONFIG_DIS_PUF_GEN_WRAP_KEY_SHIFT    (8U)
57760 /*! DIS_PUF_GEN_WRAP_KEY - Disable PUF generate and wrap key command
57761  *  0b0..Command enabled
57762  *  0b1..Command disabled
57763  */
57764 #define PUF_CONFIG_DIS_PUF_GEN_WRAP_KEY(x)       (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_GEN_WRAP_KEY_SHIFT)) & PUF_CONFIG_DIS_PUF_GEN_WRAP_KEY_MASK)
57765 
57766 #define PUF_CONFIG_DIS_PUF_WRAP_KEY_MASK         (0x200U)
57767 #define PUF_CONFIG_DIS_PUF_WRAP_KEY_SHIFT        (9U)
57768 /*! DIS_PUF_WRAP_KEY - Disable PUF wrap key command
57769  *  0b0..Command enabled
57770  *  0b1..Command disabled
57771  */
57772 #define PUF_CONFIG_DIS_PUF_WRAP_KEY(x)           (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_WRAP_KEY_SHIFT)) & PUF_CONFIG_DIS_PUF_WRAP_KEY_MASK)
57773 
57774 #define PUF_CONFIG_DIS_PUF_GEN_RANDOM_NUMBER_MASK (0x8000U)
57775 #define PUF_CONFIG_DIS_PUF_GEN_RANDOM_NUMBER_SHIFT (15U)
57776 /*! DIS_PUF_GEN_RANDOM_NUMBER - Disable PUF generate and wrap key command
57777  *  0b0..Command enabled
57778  *  0b1..Command disabled
57779  */
57780 #define PUF_CONFIG_DIS_PUF_GEN_RANDOM_NUMBER(x)  (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_GEN_RANDOM_NUMBER_SHIFT)) & PUF_CONFIG_DIS_PUF_GEN_RANDOM_NUMBER_MASK)
57781 
57782 #define PUF_CONFIG_DIS_PUF_TEST_MASK             (0x80000000U)
57783 #define PUF_CONFIG_DIS_PUF_TEST_SHIFT            (31U)
57784 /*! DIS_PUF_TEST - Disable PUF test command
57785  *  0b0..Command enabled
57786  *  0b1..Command disabled
57787  */
57788 #define PUF_CONFIG_DIS_PUF_TEST(x)               (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_TEST_SHIFT)) & PUF_CONFIG_DIS_PUF_TEST_MASK)
57789 /*! @} */
57790 
57791 /*! @name SEC_LOCK - Security level lock */
57792 /*! @{ */
57793 
57794 #define PUF_SEC_LOCK_SEC_LEVEL_MASK              (0x3U)
57795 #define PUF_SEC_LOCK_SEC_LEVEL_SHIFT             (0U)
57796 /*! SEC_LEVEL - Security Level
57797  *  0b00..Non-secure and non-privileged Master
57798  *  0b01..Non-secure and privileged Master
57799  *  0b10..Secure and non-privileged Master
57800  *  0b11..Secure and privileged Master
57801  */
57802 #define PUF_SEC_LOCK_SEC_LEVEL(x)                (((uint32_t)(((uint32_t)(x)) << PUF_SEC_LOCK_SEC_LEVEL_SHIFT)) & PUF_SEC_LOCK_SEC_LEVEL_MASK)
57803 
57804 #define PUF_SEC_LOCK_ANTI_POLE_SEC_LEVEL_MASK    (0xCU)
57805 #define PUF_SEC_LOCK_ANTI_POLE_SEC_LEVEL_SHIFT   (2U)
57806 /*! ANTI_POLE_SEC_LEVEL - Anti-pole of security level
57807  *  0b00..Secure and privileged Master
57808  *  0b01..Secure and non-privileged Master
57809  *  0b10..Non-secure and privileged Master
57810  *  0b11..Non-secure and non-privileged Master
57811  */
57812 #define PUF_SEC_LOCK_ANTI_POLE_SEC_LEVEL(x)      (((uint32_t)(((uint32_t)(x)) << PUF_SEC_LOCK_ANTI_POLE_SEC_LEVEL_SHIFT)) & PUF_SEC_LOCK_ANTI_POLE_SEC_LEVEL_MASK)
57813 
57814 #define PUF_SEC_LOCK_PATTERN_MASK                (0xFFF0U)
57815 #define PUF_SEC_LOCK_PATTERN_SHIFT               (4U)
57816 /*! PATTERN - Pattern */
57817 #define PUF_SEC_LOCK_PATTERN(x)                  (((uint32_t)(((uint32_t)(x)) << PUF_SEC_LOCK_PATTERN_SHIFT)) & PUF_SEC_LOCK_PATTERN_MASK)
57818 /*! @} */
57819 
57820 /*! @name APP_CTX_MASK - Application defined context mask */
57821 /*! @{ */
57822 
57823 #define PUF_APP_CTX_MASK_APP_CTX_MASK_MASK       (0xFFFFFFFFU)
57824 #define PUF_APP_CTX_MASK_APP_CTX_MASK_SHIFT      (0U)
57825 /*! APP_CTX_MASK - Application defined context */
57826 #define PUF_APP_CTX_MASK_APP_CTX_MASK(x)         (((uint32_t)(((uint32_t)(x)) << PUF_APP_CTX_MASK_APP_CTX_MASK_SHIFT)) & PUF_APP_CTX_MASK_APP_CTX_MASK_MASK)
57827 /*! @} */
57828 
57829 /*! @name SRAM_CFG - SRAM Configuration */
57830 /*! @{ */
57831 
57832 #define PUF_SRAM_CFG_ENABLE_MASK                 (0x1U)
57833 #define PUF_SRAM_CFG_ENABLE_SHIFT                (0U)
57834 /*! ENABLE - PUF SRAM Controller activation
57835  *  0b0..Disabled
57836  *  0b1..Enabled
57837  */
57838 #define PUF_SRAM_CFG_ENABLE(x)                   (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_CFG_ENABLE_SHIFT)) & PUF_SRAM_CFG_ENABLE_MASK)
57839 
57840 #define PUF_SRAM_CFG_CKGATING_MASK               (0x4U)
57841 #define PUF_SRAM_CFG_CKGATING_SHIFT              (2U)
57842 /*! CKGATING - PUF SRAM Clock Gating control
57843  *  0b0..Disabled
57844  *  0b1..Enabled
57845  */
57846 #define PUF_SRAM_CFG_CKGATING(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_CFG_CKGATING_SHIFT)) & PUF_SRAM_CFG_CKGATING_MASK)
57847 /*! @} */
57848 
57849 /*! @name SRAM_STATUS - Status */
57850 /*! @{ */
57851 
57852 #define PUF_SRAM_STATUS_READY_MASK               (0x1U)
57853 #define PUF_SRAM_STATUS_READY_SHIFT              (0U)
57854 /*! READY - PUF SRAM Controller State */
57855 #define PUF_SRAM_STATUS_READY(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_STATUS_READY_SHIFT)) & PUF_SRAM_STATUS_READY_MASK)
57856 /*! @} */
57857 
57858 /*! @name SRAM_INT_CLR_ENABLE - Interrupt Enable Clear */
57859 /*! @{ */
57860 
57861 #define PUF_SRAM_INT_CLR_ENABLE_READY_MASK       (0x1U)
57862 #define PUF_SRAM_INT_CLR_ENABLE_READY_SHIFT      (0U)
57863 /*! READY - READY Interrupt Enable clear */
57864 #define PUF_SRAM_INT_CLR_ENABLE_READY(x)         (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_CLR_ENABLE_READY_SHIFT)) & PUF_SRAM_INT_CLR_ENABLE_READY_MASK)
57865 
57866 #define PUF_SRAM_INT_CLR_ENABLE_APB_ERR_MASK     (0x2U)
57867 #define PUF_SRAM_INT_CLR_ENABLE_APB_ERR_SHIFT    (1U)
57868 /*! APB_ERR - APB_ERR Interrupt Enable clear */
57869 #define PUF_SRAM_INT_CLR_ENABLE_APB_ERR(x)       (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_CLR_ENABLE_APB_ERR_SHIFT)) & PUF_SRAM_INT_CLR_ENABLE_APB_ERR_MASK)
57870 /*! @} */
57871 
57872 /*! @name SRAM_INT_SET_ENABLE - Interrupt Enable Set */
57873 /*! @{ */
57874 
57875 #define PUF_SRAM_INT_SET_ENABLE_READY_MASK       (0x1U)
57876 #define PUF_SRAM_INT_SET_ENABLE_READY_SHIFT      (0U)
57877 /*! READY - READY Interrupt Enable set */
57878 #define PUF_SRAM_INT_SET_ENABLE_READY(x)         (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_SET_ENABLE_READY_SHIFT)) & PUF_SRAM_INT_SET_ENABLE_READY_MASK)
57879 
57880 #define PUF_SRAM_INT_SET_ENABLE_APB_ERR_MASK     (0x2U)
57881 #define PUF_SRAM_INT_SET_ENABLE_APB_ERR_SHIFT    (1U)
57882 /*! APB_ERR - APB_ERR Interrupt Enable set */
57883 #define PUF_SRAM_INT_SET_ENABLE_APB_ERR(x)       (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_SET_ENABLE_APB_ERR_SHIFT)) & PUF_SRAM_INT_SET_ENABLE_APB_ERR_MASK)
57884 /*! @} */
57885 
57886 /*! @name SRAM_INT_STATUS - Interrupt Status */
57887 /*! @{ */
57888 
57889 #define PUF_SRAM_INT_STATUS_READY_MASK           (0x1U)
57890 #define PUF_SRAM_INT_STATUS_READY_SHIFT          (0U)
57891 /*! READY - READY Interrupt Status */
57892 #define PUF_SRAM_INT_STATUS_READY(x)             (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_STATUS_READY_SHIFT)) & PUF_SRAM_INT_STATUS_READY_MASK)
57893 
57894 #define PUF_SRAM_INT_STATUS_APB_ERR_MASK         (0x2U)
57895 #define PUF_SRAM_INT_STATUS_APB_ERR_SHIFT        (1U)
57896 /*! APB_ERR - APB_ERR Interrupt Status */
57897 #define PUF_SRAM_INT_STATUS_APB_ERR(x)           (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_STATUS_APB_ERR_SHIFT)) & PUF_SRAM_INT_STATUS_APB_ERR_MASK)
57898 /*! @} */
57899 
57900 /*! @name SRAM_INT_ENABLE - Interrupt Enable */
57901 /*! @{ */
57902 
57903 #define PUF_SRAM_INT_ENABLE_READY_MASK           (0x1U)
57904 #define PUF_SRAM_INT_ENABLE_READY_SHIFT          (0U)
57905 /*! READY - READY Interrupt Enable
57906  *  0b0..Disabled
57907  *  0b1..Enabled
57908  */
57909 #define PUF_SRAM_INT_ENABLE_READY(x)             (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_ENABLE_READY_SHIFT)) & PUF_SRAM_INT_ENABLE_READY_MASK)
57910 
57911 #define PUF_SRAM_INT_ENABLE_SRAM_APB_ERR_MASK    (0x2U)
57912 #define PUF_SRAM_INT_ENABLE_SRAM_APB_ERR_SHIFT   (1U)
57913 /*! SRAM_APB_ERR - APB_ERR Interrupt Enable
57914  *  0b0..Disabled
57915  *  0b1..Enabled
57916  */
57917 #define PUF_SRAM_INT_ENABLE_SRAM_APB_ERR(x)      (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_ENABLE_SRAM_APB_ERR_SHIFT)) & PUF_SRAM_INT_ENABLE_SRAM_APB_ERR_MASK)
57918 /*! @} */
57919 
57920 /*! @name SRAM_INT_CLR_STATUS - Interrupt Status Clear */
57921 /*! @{ */
57922 
57923 #define PUF_SRAM_INT_CLR_STATUS_READY_MASK       (0x1U)
57924 #define PUF_SRAM_INT_CLR_STATUS_READY_SHIFT      (0U)
57925 /*! READY - READY Interrupt Status clear */
57926 #define PUF_SRAM_INT_CLR_STATUS_READY(x)         (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_CLR_STATUS_READY_SHIFT)) & PUF_SRAM_INT_CLR_STATUS_READY_MASK)
57927 
57928 #define PUF_SRAM_INT_CLR_STATUS_APB_ERR_MASK     (0x2U)
57929 #define PUF_SRAM_INT_CLR_STATUS_APB_ERR_SHIFT    (1U)
57930 /*! APB_ERR - APB_ERR Interrupt Status Clear
57931  *  0b0..No effect
57932  *  0b1..Clears the APB_ERR bit field in register INT_STATUS. Automatically reset by the Hardware
57933  */
57934 #define PUF_SRAM_INT_CLR_STATUS_APB_ERR(x)       (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_CLR_STATUS_APB_ERR_SHIFT)) & PUF_SRAM_INT_CLR_STATUS_APB_ERR_MASK)
57935 /*! @} */
57936 
57937 /*! @name SRAM_INT_SET_STATUS - Interrupt Status set */
57938 /*! @{ */
57939 
57940 #define PUF_SRAM_INT_SET_STATUS_READY_MASK       (0x1U)
57941 #define PUF_SRAM_INT_SET_STATUS_READY_SHIFT      (0U)
57942 /*! READY - READY Interrupt Status set */
57943 #define PUF_SRAM_INT_SET_STATUS_READY(x)         (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_SET_STATUS_READY_SHIFT)) & PUF_SRAM_INT_SET_STATUS_READY_MASK)
57944 
57945 #define PUF_SRAM_INT_SET_STATUS_APB_ERR_MASK     (0x2U)
57946 #define PUF_SRAM_INT_SET_STATUS_APB_ERR_SHIFT    (1U)
57947 /*! APB_ERR - APB_ERR Interrupt Status Set
57948  *  0b0..No effect
57949  *  0b1..Clears the APB_ERR bit field in register INT_STATUS. Automatically reset by the Hardware
57950  */
57951 #define PUF_SRAM_INT_SET_STATUS_APB_ERR(x)       (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_SET_STATUS_APB_ERR_SHIFT)) & PUF_SRAM_INT_SET_STATUS_APB_ERR_MASK)
57952 /*! @} */
57953 
57954 
57955 /*!
57956  * @}
57957  */ /* end of group PUF_Register_Masks */
57958 
57959 
57960 /* PUF - Peripheral instance base addresses */
57961 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
57962   /** Peripheral PUF base address */
57963   #define PUF_BASE                                 (0x5002C000u)
57964   /** Peripheral PUF base address */
57965   #define PUF_BASE_NS                              (0x4002C000u)
57966   /** Peripheral PUF base pointer */
57967   #define PUF                                      ((PUF_Type *)PUF_BASE)
57968   /** Peripheral PUF base pointer */
57969   #define PUF_NS                                   ((PUF_Type *)PUF_BASE_NS)
57970   /** Peripheral PUF_ALIAS1 base address */
57971   #define PUF_ALIAS1_BASE                          (0x5002D000u)
57972   /** Peripheral PUF_ALIAS1 base address */
57973   #define PUF_ALIAS1_BASE_NS                       (0x4002D000u)
57974   /** Peripheral PUF_ALIAS1 base pointer */
57975   #define PUF_ALIAS1                               ((PUF_Type *)PUF_ALIAS1_BASE)
57976   /** Peripheral PUF_ALIAS1 base pointer */
57977   #define PUF_ALIAS1_NS                            ((PUF_Type *)PUF_ALIAS1_BASE_NS)
57978   /** Peripheral PUF_ALIAS2 base address */
57979   #define PUF_ALIAS2_BASE                          (0x5002E000u)
57980   /** Peripheral PUF_ALIAS2 base address */
57981   #define PUF_ALIAS2_BASE_NS                       (0x4002E000u)
57982   /** Peripheral PUF_ALIAS2 base pointer */
57983   #define PUF_ALIAS2                               ((PUF_Type *)PUF_ALIAS2_BASE)
57984   /** Peripheral PUF_ALIAS2 base pointer */
57985   #define PUF_ALIAS2_NS                            ((PUF_Type *)PUF_ALIAS2_BASE_NS)
57986   /** Peripheral PUF_ALIAS3 base address */
57987   #define PUF_ALIAS3_BASE                          (0x5002F000u)
57988   /** Peripheral PUF_ALIAS3 base address */
57989   #define PUF_ALIAS3_BASE_NS                       (0x4002F000u)
57990   /** Peripheral PUF_ALIAS3 base pointer */
57991   #define PUF_ALIAS3                               ((PUF_Type *)PUF_ALIAS3_BASE)
57992   /** Peripheral PUF_ALIAS3 base pointer */
57993   #define PUF_ALIAS3_NS                            ((PUF_Type *)PUF_ALIAS3_BASE_NS)
57994   /** Array initializer of PUF peripheral base addresses */
57995   #define PUF_BASE_ADDRS                           { PUF_BASE, PUF_ALIAS1_BASE, PUF_ALIAS2_BASE, PUF_ALIAS3_BASE }
57996   /** Array initializer of PUF peripheral base pointers */
57997   #define PUF_BASE_PTRS                            { PUF, PUF_ALIAS1, PUF_ALIAS2, PUF_ALIAS3 }
57998   /** Array initializer of PUF peripheral base addresses */
57999   #define PUF_BASE_ADDRS_NS                        { PUF_BASE_NS, PUF_ALIAS1_BASE_NS, PUF_ALIAS2_BASE_NS, PUF_ALIAS3_BASE_NS }
58000   /** Array initializer of PUF peripheral base pointers */
58001   #define PUF_BASE_PTRS_NS                         { PUF_NS, PUF_ALIAS1_NS, PUF_ALIAS2_NS, PUF_ALIAS3_NS }
58002 #else
58003   /** Peripheral PUF base address */
58004   #define PUF_BASE                                 (0x4002C000u)
58005   /** Peripheral PUF base pointer */
58006   #define PUF                                      ((PUF_Type *)PUF_BASE)
58007   /** Peripheral PUF_ALIAS1 base address */
58008   #define PUF_ALIAS1_BASE                          (0x4002D000u)
58009   /** Peripheral PUF_ALIAS1 base pointer */
58010   #define PUF_ALIAS1                               ((PUF_Type *)PUF_ALIAS1_BASE)
58011   /** Peripheral PUF_ALIAS2 base address */
58012   #define PUF_ALIAS2_BASE                          (0x4002E000u)
58013   /** Peripheral PUF_ALIAS2 base pointer */
58014   #define PUF_ALIAS2                               ((PUF_Type *)PUF_ALIAS2_BASE)
58015   /** Peripheral PUF_ALIAS3 base address */
58016   #define PUF_ALIAS3_BASE                          (0x4002F000u)
58017   /** Peripheral PUF_ALIAS3 base pointer */
58018   #define PUF_ALIAS3                               ((PUF_Type *)PUF_ALIAS3_BASE)
58019   /** Array initializer of PUF peripheral base addresses */
58020   #define PUF_BASE_ADDRS                           { PUF_BASE, PUF_ALIAS1_BASE, PUF_ALIAS2_BASE, PUF_ALIAS3_BASE }
58021   /** Array initializer of PUF peripheral base pointers */
58022   #define PUF_BASE_PTRS                            { PUF, PUF_ALIAS1, PUF_ALIAS2, PUF_ALIAS3 }
58023 #endif
58024 
58025 /*!
58026  * @}
58027  */ /* end of group PUF_Peripheral_Access_Layer */
58028 
58029 
58030 /* ----------------------------------------------------------------------------
58031    -- PWM Peripheral Access Layer
58032    ---------------------------------------------------------------------------- */
58033 
58034 /*!
58035  * @addtogroup PWM_Peripheral_Access_Layer PWM Peripheral Access Layer
58036  * @{
58037  */
58038 
58039 /** PWM - Register Layout Typedef */
58040 typedef struct {
58041   struct {                                         /* offset: 0x0, array step: 0x60 */
58042     __I  uint16_t CNT;                               /**< Counter Register, array offset: 0x0, array step: 0x60 */
58043     __IO uint16_t INIT;                              /**< Initial Count Register, array offset: 0x2, array step: 0x60 */
58044     __IO uint16_t CTRL2;                             /**< Control 2 Register, array offset: 0x4, array step: 0x60 */
58045     __IO uint16_t CTRL;                              /**< Control Register, array offset: 0x6, array step: 0x60 */
58046          uint8_t RESERVED_0[2];
58047     __IO uint16_t VAL0;                              /**< Value Register 0, array offset: 0xA, array step: 0x60 */
58048     __IO uint16_t FRACVAL1;                          /**< Fractional Value Register 1, array offset: 0xC, array step: 0x60 */
58049     __IO uint16_t VAL1;                              /**< Value Register 1, array offset: 0xE, array step: 0x60 */
58050     __IO uint16_t FRACVAL2;                          /**< Fractional Value Register 2, array offset: 0x10, array step: 0x60 */
58051     __IO uint16_t VAL2;                              /**< Value Register 2, array offset: 0x12, array step: 0x60 */
58052     __IO uint16_t FRACVAL3;                          /**< Fractional Value Register 3, array offset: 0x14, array step: 0x60 */
58053     __IO uint16_t VAL3;                              /**< Value Register 3, array offset: 0x16, array step: 0x60 */
58054     __IO uint16_t FRACVAL4;                          /**< Fractional Value Register 4, array offset: 0x18, array step: 0x60 */
58055     __IO uint16_t VAL4;                              /**< Value Register 4, array offset: 0x1A, array step: 0x60 */
58056     __IO uint16_t FRACVAL5;                          /**< Fractional Value Register 5, array offset: 0x1C, array step: 0x60 */
58057     __IO uint16_t VAL5;                              /**< Value Register 5, array offset: 0x1E, array step: 0x60 */
58058     __IO uint16_t FRCTRL;                            /**< Fractional Control Register, array offset: 0x20, array step: 0x60 */
58059     __IO uint16_t OCTRL;                             /**< Output Control Register, array offset: 0x22, array step: 0x60 */
58060     __IO uint16_t STS;                               /**< Status Register, array offset: 0x24, array step: 0x60 */
58061     __IO uint16_t INTEN;                             /**< Interrupt Enable Register, array offset: 0x26, array step: 0x60 */
58062     __IO uint16_t DMAEN;                             /**< DMA Enable Register, array offset: 0x28, array step: 0x60 */
58063     __IO uint16_t TCTRL;                             /**< Output Trigger Control Register, array offset: 0x2A, array step: 0x60 */
58064     __IO uint16_t DISMAP[1];                         /**< Fault Disable Mapping Register 0, array offset: 0x2C, array step: index*0x60, index2*0x2 */
58065          uint8_t RESERVED_1[2];
58066     __IO uint16_t DTCNT0;                            /**< Deadtime Count Register 0, array offset: 0x30, array step: 0x60 */
58067     __IO uint16_t DTCNT1;                            /**< Deadtime Count Register 1, array offset: 0x32, array step: 0x60 */
58068     __IO uint16_t CAPTCTRLA;                         /**< Capture Control A Register, array offset: 0x34, array step: 0x60 */
58069     __IO uint16_t CAPTCOMPA;                         /**< Capture Compare A Register, array offset: 0x36, array step: 0x60 */
58070     __IO uint16_t CAPTCTRLB;                         /**< Capture Control B Register, array offset: 0x38, array step: 0x60 */
58071     __IO uint16_t CAPTCOMPB;                         /**< Capture Compare B Register, array offset: 0x3A, array step: 0x60 */
58072     __IO uint16_t CAPTCTRLX;                         /**< Capture Control X Register, array offset: 0x3C, array step: 0x60 */
58073     __IO uint16_t CAPTCOMPX;                         /**< Capture Compare X Register, array offset: 0x3E, array step: 0x60 */
58074     __I  uint16_t CVAL0;                             /**< Capture Value 0 Register, array offset: 0x40, array step: 0x60 */
58075     __I  uint16_t CVAL0CYC;                          /**< Capture Value 0 Cycle Register, array offset: 0x42, array step: 0x60 */
58076     __I  uint16_t CVAL1;                             /**< Capture Value 1 Register, array offset: 0x44, array step: 0x60 */
58077     __I  uint16_t CVAL1CYC;                          /**< Capture Value 1 Cycle Register, array offset: 0x46, array step: 0x60 */
58078     __I  uint16_t CVAL2;                             /**< Capture Value 2 Register, array offset: 0x48, array step: 0x60 */
58079     __I  uint16_t CVAL2CYC;                          /**< Capture Value 2 Cycle Register, array offset: 0x4A, array step: 0x60 */
58080     __I  uint16_t CVAL3;                             /**< Capture Value 3 Register, array offset: 0x4C, array step: 0x60 */
58081     __I  uint16_t CVAL3CYC;                          /**< Capture Value 3 Cycle Register, array offset: 0x4E, array step: 0x60 */
58082     __I  uint16_t CVAL4;                             /**< Capture Value 4 Register, array offset: 0x50, array step: 0x60 */
58083     __I  uint16_t CVAL4CYC;                          /**< Capture Value 4 Cycle Register, array offset: 0x52, array step: 0x60 */
58084     __I  uint16_t CVAL5;                             /**< Capture Value 5 Register, array offset: 0x54, array step: 0x60 */
58085     __I  uint16_t CVAL5CYC;                          /**< Capture Value 5 Cycle Register, array offset: 0x56, array step: 0x60 */
58086     __IO uint16_t PHASEDLY;                          /**< Phase Delay Register, array offset: 0x58, array step: 0x60, valid indices: [1-3] */
58087     __IO uint16_t CAPTFILTA;                         /**< Capture PWM_A Input Filter Register, array offset: 0x5A, array step: 0x60 */
58088     __IO uint16_t CAPTFILTB;                         /**< Capture PWM_B Input Filter Register, array offset: 0x5C, array step: 0x60 */
58089     __IO uint16_t CAPTFILTX;                         /**< Capture PWM_X Input Filter Register, array offset: 0x5E, array step: 0x60 */
58090   } SM[4];
58091   __IO uint16_t OUTEN;                             /**< Output Enable Register, offset: 0x180 */
58092   __IO uint16_t MASK;                              /**< Mask Register, offset: 0x182 */
58093   __IO uint16_t SWCOUT;                            /**< Software Controlled Output Register, offset: 0x184 */
58094   __IO uint16_t DTSRCSEL;                          /**< PWM Source Select Register, offset: 0x186 */
58095   __IO uint16_t MCTRL;                             /**< Master Control Register, offset: 0x188 */
58096   __IO uint16_t MCTRL2;                            /**< Master Control 2 Register, offset: 0x18A */
58097   __IO uint16_t FCTRL;                             /**< Fault Control Register, offset: 0x18C */
58098   __IO uint16_t FSTS;                              /**< Fault Status Register, offset: 0x18E */
58099   __IO uint16_t FFILT;                             /**< Fault Filter Register, offset: 0x190 */
58100   __IO uint16_t FTST;                              /**< Fault Test Register, offset: 0x192 */
58101   __IO uint16_t FCTRL2;                            /**< Fault Control 2 Register, offset: 0x194 */
58102 } PWM_Type;
58103 
58104 /* ----------------------------------------------------------------------------
58105    -- PWM Register Masks
58106    ---------------------------------------------------------------------------- */
58107 
58108 /*!
58109  * @addtogroup PWM_Register_Masks PWM Register Masks
58110  * @{
58111  */
58112 
58113 /*! @name CNT - Counter Register */
58114 /*! @{ */
58115 
58116 #define PWM_CNT_CNT_MASK                         (0xFFFFU)
58117 #define PWM_CNT_CNT_SHIFT                        (0U)
58118 /*! CNT - Counter Register Bits */
58119 #define PWM_CNT_CNT(x)                           (((uint16_t)(((uint16_t)(x)) << PWM_CNT_CNT_SHIFT)) & PWM_CNT_CNT_MASK)
58120 /*! @} */
58121 
58122 /* The count of PWM_CNT */
58123 #define PWM_CNT_COUNT                            (4U)
58124 
58125 /*! @name INIT - Initial Count Register */
58126 /*! @{ */
58127 
58128 #define PWM_INIT_INIT_MASK                       (0xFFFFU)
58129 #define PWM_INIT_INIT_SHIFT                      (0U)
58130 /*! INIT - Initial Count Register Bits */
58131 #define PWM_INIT_INIT(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_INIT_INIT_SHIFT)) & PWM_INIT_INIT_MASK)
58132 /*! @} */
58133 
58134 /* The count of PWM_INIT */
58135 #define PWM_INIT_COUNT                           (4U)
58136 
58137 /*! @name CTRL2 - Control 2 Register */
58138 /*! @{ */
58139 
58140 #define PWM_CTRL2_CLK_SEL_MASK                   (0x3U)
58141 #define PWM_CTRL2_CLK_SEL_SHIFT                  (0U)
58142 /*! CLK_SEL - Clock Source Select
58143  *  0b00..The IPBus clock is used as the clock for the local prescaler and counter.
58144  *  0b01..EXT_CLK is used as the clock for the local prescaler and counter.
58145  *  0b10..Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This
58146  *        setting should not be used in submodule 0 as it forces the clock to logic 0.
58147  *  0b11..Reserved
58148  */
58149 #define PWM_CTRL2_CLK_SEL(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_CLK_SEL_SHIFT)) & PWM_CTRL2_CLK_SEL_MASK)
58150 
58151 #define PWM_CTRL2_RELOAD_SEL_MASK                (0x4U)
58152 #define PWM_CTRL2_RELOAD_SEL_SHIFT               (2U)
58153 /*! RELOAD_SEL - Reload Source Select
58154  *  0b0..The local RELOAD signal is used to reload registers.
58155  *  0b1..The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used
58156  *       in submodule 0 as it forces the RELOAD signal to logic 0.
58157  */
58158 #define PWM_CTRL2_RELOAD_SEL(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_RELOAD_SEL_SHIFT)) & PWM_CTRL2_RELOAD_SEL_MASK)
58159 
58160 #define PWM_CTRL2_FORCE_SEL_MASK                 (0x38U)
58161 #define PWM_CTRL2_FORCE_SEL_SHIFT                (3U)
58162 /*! FORCE_SEL - Force Select
58163  *  0b000..The local force signal, CTRL2[FORCE], from this submodule is used to force updates.
58164  *  0b001..The master force signal from submodule 0 is used to force updates. This setting should not be used in
58165  *         submodule 0 as it holds the FORCE OUTPUT signal to logic 0.
58166  *  0b010..The local reload signal from this submodule is used to force updates without regard to the state of LDOK.
58167  *  0b011..The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should
58168  *         not be used in submodule0 as it holds the FORCE OUTPUT signal to logic 0.
58169  *  0b100..The local sync signal from this submodule is used to force updates.
58170  *  0b101..The master sync signal from submodule0 is used to force updates. This setting should not be used in
58171  *         submodule0 as it holds the FORCE OUTPUT signal to logic 0.
58172  *  0b110..The external force signal, EXT_FORCE, from outside the PWM module causes updates.
58173  *  0b111..The external sync signal, EXT_SYNC, from outside the PWM module causes updates.
58174  */
58175 #define PWM_CTRL2_FORCE_SEL(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SEL_SHIFT)) & PWM_CTRL2_FORCE_SEL_MASK)
58176 
58177 #define PWM_CTRL2_FORCE_MASK                     (0x40U)
58178 #define PWM_CTRL2_FORCE_SHIFT                    (6U)
58179 /*! FORCE - Force Initialization */
58180 #define PWM_CTRL2_FORCE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SHIFT)) & PWM_CTRL2_FORCE_MASK)
58181 
58182 #define PWM_CTRL2_FRCEN_MASK                     (0x80U)
58183 #define PWM_CTRL2_FRCEN_SHIFT                    (7U)
58184 /*! FRCEN - Force Enable
58185  *  0b0..Initialization from a FORCE_OUT is disabled.
58186  *  0b1..Initialization from a FORCE_OUT is enabled.
58187  */
58188 #define PWM_CTRL2_FRCEN(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FRCEN_SHIFT)) & PWM_CTRL2_FRCEN_MASK)
58189 
58190 #define PWM_CTRL2_INIT_SEL_MASK                  (0x300U)
58191 #define PWM_CTRL2_INIT_SEL_SHIFT                 (8U)
58192 /*! INIT_SEL - Initialization Control Select
58193  *  0b00..Local sync (PWM_X) causes initialization.
58194  *  0b01..Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as
58195  *        it forces the INIT signal to logic 0. The submodule counter will only re-initialize when a master reload
58196  *        occurs.
58197  *  0b10..Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it forces the INIT signal to logic 0.
58198  *  0b11..EXT_SYNC causes initialization.
58199  */
58200 #define PWM_CTRL2_INIT_SEL(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INIT_SEL_SHIFT)) & PWM_CTRL2_INIT_SEL_MASK)
58201 
58202 #define PWM_CTRL2_PWMX_INIT_MASK                 (0x400U)
58203 #define PWM_CTRL2_PWMX_INIT_SHIFT                (10U)
58204 /*! PWMX_INIT - PWM_X Initial Value */
58205 #define PWM_CTRL2_PWMX_INIT(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWMX_INIT_SHIFT)) & PWM_CTRL2_PWMX_INIT_MASK)
58206 
58207 #define PWM_CTRL2_PWM45_INIT_MASK                (0x800U)
58208 #define PWM_CTRL2_PWM45_INIT_SHIFT               (11U)
58209 /*! PWM45_INIT - PWM45 Initial Value */
58210 #define PWM_CTRL2_PWM45_INIT(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM45_INIT_SHIFT)) & PWM_CTRL2_PWM45_INIT_MASK)
58211 
58212 #define PWM_CTRL2_PWM23_INIT_MASK                (0x1000U)
58213 #define PWM_CTRL2_PWM23_INIT_SHIFT               (12U)
58214 /*! PWM23_INIT - PWM23 Initial Value */
58215 #define PWM_CTRL2_PWM23_INIT(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM23_INIT_SHIFT)) & PWM_CTRL2_PWM23_INIT_MASK)
58216 
58217 #define PWM_CTRL2_INDEP_MASK                     (0x2000U)
58218 #define PWM_CTRL2_INDEP_SHIFT                    (13U)
58219 /*! INDEP - Independent or Complementary Pair Operation
58220  *  0b0..PWM_A and PWM_B form a complementary PWM pair.
58221  *  0b1..PWM_A and PWM_B outputs are independent PWMs.
58222  */
58223 #define PWM_CTRL2_INDEP(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INDEP_SHIFT)) & PWM_CTRL2_INDEP_MASK)
58224 
58225 #define PWM_CTRL2_DBGEN_MASK                     (0x8000U)
58226 #define PWM_CTRL2_DBGEN_SHIFT                    (15U)
58227 /*! DBGEN - Debug Enable */
58228 #define PWM_CTRL2_DBGEN(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_DBGEN_SHIFT)) & PWM_CTRL2_DBGEN_MASK)
58229 /*! @} */
58230 
58231 /* The count of PWM_CTRL2 */
58232 #define PWM_CTRL2_COUNT                          (4U)
58233 
58234 /*! @name CTRL - Control Register */
58235 /*! @{ */
58236 
58237 #define PWM_CTRL_DBLEN_MASK                      (0x1U)
58238 #define PWM_CTRL_DBLEN_SHIFT                     (0U)
58239 /*! DBLEN - Double Switching Enable
58240  *  0b0..Double switching disabled.
58241  *  0b1..Double switching enabled.
58242  */
58243 #define PWM_CTRL_DBLEN(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLEN_SHIFT)) & PWM_CTRL_DBLEN_MASK)
58244 
58245 #define PWM_CTRL_DBLX_MASK                       (0x2U)
58246 #define PWM_CTRL_DBLX_SHIFT                      (1U)
58247 /*! DBLX - PWM_X Double Switching Enable
58248  *  0b0..PWM_X double pulse disabled.
58249  *  0b1..PWM_X double pulse enabled.
58250  */
58251 #define PWM_CTRL_DBLX(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLX_SHIFT)) & PWM_CTRL_DBLX_MASK)
58252 
58253 #define PWM_CTRL_LDMOD_MASK                      (0x4U)
58254 #define PWM_CTRL_LDMOD_SHIFT                     (2U)
58255 /*! LDMOD - Load Mode Select
58256  *  0b0..Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL[LDOK] is set.
58257  *  0b1..Buffered registers of this submodule are loaded and take effect immediately upon MCTRL[LDOK] being set.
58258  *       In this case, it is not necessary to set CTRL[FULL] or CTRL[HALF].
58259  */
58260 #define PWM_CTRL_LDMOD(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDMOD_SHIFT)) & PWM_CTRL_LDMOD_MASK)
58261 
58262 #define PWM_CTRL_SPLIT_MASK                      (0x8U)
58263 #define PWM_CTRL_SPLIT_SHIFT                     (3U)
58264 /*! SPLIT - Split the DBLPWM signal to PWM_A and PWM_B
58265  *  0b0..DBLPWM is not split. PWM_A and PWM_B each have double pulses.
58266  *  0b1..DBLPWM is split to PWM_A and PWM_B.
58267  */
58268 #define PWM_CTRL_SPLIT(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_SPLIT_SHIFT)) & PWM_CTRL_SPLIT_MASK)
58269 
58270 #define PWM_CTRL_PRSC_MASK                       (0x70U)
58271 #define PWM_CTRL_PRSC_SHIFT                      (4U)
58272 /*! PRSC - Prescaler
58273  *  0b000..Prescaler 1
58274  *  0b001..Prescaler 2
58275  *  0b010..Prescaler 4
58276  *  0b011..Prescaler 8
58277  *  0b100..Prescaler 16
58278  *  0b101..Prescaler 32
58279  *  0b110..Prescaler 64
58280  *  0b111..Prescaler 128
58281  */
58282 #define PWM_CTRL_PRSC(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_PRSC_SHIFT)) & PWM_CTRL_PRSC_MASK)
58283 
58284 #define PWM_CTRL_COMPMODE_MASK                   (0x80U)
58285 #define PWM_CTRL_COMPMODE_SHIFT                  (7U)
58286 /*! COMPMODE - Compare Mode
58287  *  0b0..The VAL* registers and the PWM counter are compared using an "equal to" method. This means that PWM edges
58288  *       are only produced when the counter is equal to one of the VAL* register values. This implies that a PWM_A
58289  *       output that is high at the end of a period maintains this state until a match with VAL3 clears the output
58290  *       in the following period.
58291  *  0b1..The VAL* registers and the PWM counter are compared using an "equal to or greater than" method. This
58292  *       means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register
58293  *       values. This implies that a PWM_A output that is high at the end of a period could go low at the start of the
58294  *       next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value.
58295  */
58296 #define PWM_CTRL_COMPMODE(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_COMPMODE_SHIFT)) & PWM_CTRL_COMPMODE_MASK)
58297 
58298 #define PWM_CTRL_DT_MASK                         (0x300U)
58299 #define PWM_CTRL_DT_SHIFT                        (8U)
58300 /*! DT - Deadtime */
58301 #define PWM_CTRL_DT(x)                           (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DT_SHIFT)) & PWM_CTRL_DT_MASK)
58302 
58303 #define PWM_CTRL_FULL_MASK                       (0x400U)
58304 #define PWM_CTRL_FULL_SHIFT                      (10U)
58305 /*! FULL - Full Cycle Reload
58306  *  0b0..Full-cycle reloads disabled.
58307  *  0b1..Full-cycle reloads enabled.
58308  */
58309 #define PWM_CTRL_FULL(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_FULL_SHIFT)) & PWM_CTRL_FULL_MASK)
58310 
58311 #define PWM_CTRL_HALF_MASK                       (0x800U)
58312 #define PWM_CTRL_HALF_SHIFT                      (11U)
58313 /*! HALF - Half Cycle Reload
58314  *  0b0..Half-cycle reloads disabled.
58315  *  0b1..Half-cycle reloads enabled.
58316  */
58317 #define PWM_CTRL_HALF(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_HALF_SHIFT)) & PWM_CTRL_HALF_MASK)
58318 
58319 #define PWM_CTRL_LDFQ_MASK                       (0xF000U)
58320 #define PWM_CTRL_LDFQ_SHIFT                      (12U)
58321 /*! LDFQ - Load Frequency
58322  *  0b0000..Every PWM opportunity
58323  *  0b0001..Every 2 PWM opportunities
58324  *  0b0010..Every 3 PWM opportunities
58325  *  0b0011..Every 4 PWM opportunities
58326  *  0b0100..Every 5 PWM opportunities
58327  *  0b0101..Every 6 PWM opportunities
58328  *  0b0110..Every 7 PWM opportunities
58329  *  0b0111..Every 8 PWM opportunities
58330  *  0b1000..Every 9 PWM opportunities
58331  *  0b1001..Every 10 PWM opportunities
58332  *  0b1010..Every 11 PWM opportunities
58333  *  0b1011..Every 12 PWM opportunities
58334  *  0b1100..Every 13 PWM opportunities
58335  *  0b1101..Every 14 PWM opportunities
58336  *  0b1110..Every 15 PWM opportunities
58337  *  0b1111..Every 16 PWM opportunities
58338  */
58339 #define PWM_CTRL_LDFQ(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDFQ_SHIFT)) & PWM_CTRL_LDFQ_MASK)
58340 /*! @} */
58341 
58342 /* The count of PWM_CTRL */
58343 #define PWM_CTRL_COUNT                           (4U)
58344 
58345 /*! @name VAL0 - Value Register 0 */
58346 /*! @{ */
58347 
58348 #define PWM_VAL0_VAL0_MASK                       (0xFFFFU)
58349 #define PWM_VAL0_VAL0_SHIFT                      (0U)
58350 /*! VAL0 - Value 0 */
58351 #define PWM_VAL0_VAL0(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_VAL0_VAL0_SHIFT)) & PWM_VAL0_VAL0_MASK)
58352 /*! @} */
58353 
58354 /* The count of PWM_VAL0 */
58355 #define PWM_VAL0_COUNT                           (4U)
58356 
58357 /*! @name FRACVAL1 - Fractional Value Register 1 */
58358 /*! @{ */
58359 
58360 #define PWM_FRACVAL1_FRACVAL1_MASK               (0xF800U)
58361 #define PWM_FRACVAL1_FRACVAL1_SHIFT              (11U)
58362 /*! FRACVAL1 - Fractional Value 1 */
58363 #define PWM_FRACVAL1_FRACVAL1(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL1_FRACVAL1_SHIFT)) & PWM_FRACVAL1_FRACVAL1_MASK)
58364 /*! @} */
58365 
58366 /* The count of PWM_FRACVAL1 */
58367 #define PWM_FRACVAL1_COUNT                       (4U)
58368 
58369 /*! @name VAL1 - Value Register 1 */
58370 /*! @{ */
58371 
58372 #define PWM_VAL1_VAL1_MASK                       (0xFFFFU)
58373 #define PWM_VAL1_VAL1_SHIFT                      (0U)
58374 /*! VAL1 - Value 1 */
58375 #define PWM_VAL1_VAL1(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_VAL1_VAL1_SHIFT)) & PWM_VAL1_VAL1_MASK)
58376 /*! @} */
58377 
58378 /* The count of PWM_VAL1 */
58379 #define PWM_VAL1_COUNT                           (4U)
58380 
58381 /*! @name FRACVAL2 - Fractional Value Register 2 */
58382 /*! @{ */
58383 
58384 #define PWM_FRACVAL2_FRACVAL2_MASK               (0xF800U)
58385 #define PWM_FRACVAL2_FRACVAL2_SHIFT              (11U)
58386 /*! FRACVAL2 - Fractional Value 2 */
58387 #define PWM_FRACVAL2_FRACVAL2(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL2_FRACVAL2_SHIFT)) & PWM_FRACVAL2_FRACVAL2_MASK)
58388 /*! @} */
58389 
58390 /* The count of PWM_FRACVAL2 */
58391 #define PWM_FRACVAL2_COUNT                       (4U)
58392 
58393 /*! @name VAL2 - Value Register 2 */
58394 /*! @{ */
58395 
58396 #define PWM_VAL2_VAL2_MASK                       (0xFFFFU)
58397 #define PWM_VAL2_VAL2_SHIFT                      (0U)
58398 /*! VAL2 - Value 2 */
58399 #define PWM_VAL2_VAL2(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_VAL2_VAL2_SHIFT)) & PWM_VAL2_VAL2_MASK)
58400 /*! @} */
58401 
58402 /* The count of PWM_VAL2 */
58403 #define PWM_VAL2_COUNT                           (4U)
58404 
58405 /*! @name FRACVAL3 - Fractional Value Register 3 */
58406 /*! @{ */
58407 
58408 #define PWM_FRACVAL3_FRACVAL3_MASK               (0xF800U)
58409 #define PWM_FRACVAL3_FRACVAL3_SHIFT              (11U)
58410 /*! FRACVAL3 - Fractional Value 3 */
58411 #define PWM_FRACVAL3_FRACVAL3(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL3_FRACVAL3_SHIFT)) & PWM_FRACVAL3_FRACVAL3_MASK)
58412 /*! @} */
58413 
58414 /* The count of PWM_FRACVAL3 */
58415 #define PWM_FRACVAL3_COUNT                       (4U)
58416 
58417 /*! @name VAL3 - Value Register 3 */
58418 /*! @{ */
58419 
58420 #define PWM_VAL3_VAL3_MASK                       (0xFFFFU)
58421 #define PWM_VAL3_VAL3_SHIFT                      (0U)
58422 /*! VAL3 - Value 3 */
58423 #define PWM_VAL3_VAL3(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_VAL3_VAL3_SHIFT)) & PWM_VAL3_VAL3_MASK)
58424 /*! @} */
58425 
58426 /* The count of PWM_VAL3 */
58427 #define PWM_VAL3_COUNT                           (4U)
58428 
58429 /*! @name FRACVAL4 - Fractional Value Register 4 */
58430 /*! @{ */
58431 
58432 #define PWM_FRACVAL4_FRACVAL4_MASK               (0xF800U)
58433 #define PWM_FRACVAL4_FRACVAL4_SHIFT              (11U)
58434 /*! FRACVAL4 - Fractional Value 4 */
58435 #define PWM_FRACVAL4_FRACVAL4(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL4_FRACVAL4_SHIFT)) & PWM_FRACVAL4_FRACVAL4_MASK)
58436 /*! @} */
58437 
58438 /* The count of PWM_FRACVAL4 */
58439 #define PWM_FRACVAL4_COUNT                       (4U)
58440 
58441 /*! @name VAL4 - Value Register 4 */
58442 /*! @{ */
58443 
58444 #define PWM_VAL4_VAL4_MASK                       (0xFFFFU)
58445 #define PWM_VAL4_VAL4_SHIFT                      (0U)
58446 /*! VAL4 - Value 4 */
58447 #define PWM_VAL4_VAL4(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_VAL4_VAL4_SHIFT)) & PWM_VAL4_VAL4_MASK)
58448 /*! @} */
58449 
58450 /* The count of PWM_VAL4 */
58451 #define PWM_VAL4_COUNT                           (4U)
58452 
58453 /*! @name FRACVAL5 - Fractional Value Register 5 */
58454 /*! @{ */
58455 
58456 #define PWM_FRACVAL5_FRACVAL5_MASK               (0xF800U)
58457 #define PWM_FRACVAL5_FRACVAL5_SHIFT              (11U)
58458 /*! FRACVAL5 - Fractional Value 5 */
58459 #define PWM_FRACVAL5_FRACVAL5(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL5_FRACVAL5_SHIFT)) & PWM_FRACVAL5_FRACVAL5_MASK)
58460 /*! @} */
58461 
58462 /* The count of PWM_FRACVAL5 */
58463 #define PWM_FRACVAL5_COUNT                       (4U)
58464 
58465 /*! @name VAL5 - Value Register 5 */
58466 /*! @{ */
58467 
58468 #define PWM_VAL5_VAL5_MASK                       (0xFFFFU)
58469 #define PWM_VAL5_VAL5_SHIFT                      (0U)
58470 /*! VAL5 - Value 5 */
58471 #define PWM_VAL5_VAL5(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_VAL5_VAL5_SHIFT)) & PWM_VAL5_VAL5_MASK)
58472 /*! @} */
58473 
58474 /* The count of PWM_VAL5 */
58475 #define PWM_VAL5_COUNT                           (4U)
58476 
58477 /*! @name FRCTRL - Fractional Control Register */
58478 /*! @{ */
58479 
58480 #define PWM_FRCTRL_FRAC1_EN_MASK                 (0x2U)
58481 #define PWM_FRCTRL_FRAC1_EN_SHIFT                (1U)
58482 /*! FRAC1_EN - Fractional Cycle PWM Period Enable
58483  *  0b0..Disable fractional cycle length for the PWM period.
58484  *  0b1..Enable fractional cycle length for the PWM period.
58485  */
58486 #define PWM_FRCTRL_FRAC1_EN(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC1_EN_SHIFT)) & PWM_FRCTRL_FRAC1_EN_MASK)
58487 
58488 #define PWM_FRCTRL_FRAC23_EN_MASK                (0x4U)
58489 #define PWM_FRCTRL_FRAC23_EN_SHIFT               (2U)
58490 /*! FRAC23_EN - Fractional Cycle Placement Enable for PWM_A
58491  *  0b0..Disable fractional cycle placement for PWM_A.
58492  *  0b1..Enable fractional cycle placement for PWM_A.
58493  */
58494 #define PWM_FRCTRL_FRAC23_EN(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC23_EN_SHIFT)) & PWM_FRCTRL_FRAC23_EN_MASK)
58495 
58496 #define PWM_FRCTRL_FRAC45_EN_MASK                (0x10U)
58497 #define PWM_FRCTRL_FRAC45_EN_SHIFT               (4U)
58498 /*! FRAC45_EN - Fractional Cycle Placement Enable for PWM_B
58499  *  0b0..Disable fractional cycle placement for PWM_B.
58500  *  0b1..Enable fractional cycle placement for PWM_B.
58501  */
58502 #define PWM_FRCTRL_FRAC45_EN(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC45_EN_SHIFT)) & PWM_FRCTRL_FRAC45_EN_MASK)
58503 
58504 #define PWM_FRCTRL_TEST_MASK                     (0x8000U)
58505 #define PWM_FRCTRL_TEST_SHIFT                    (15U)
58506 /*! TEST - Test Status Bit */
58507 #define PWM_FRCTRL_TEST(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_TEST_SHIFT)) & PWM_FRCTRL_TEST_MASK)
58508 /*! @} */
58509 
58510 /* The count of PWM_FRCTRL */
58511 #define PWM_FRCTRL_COUNT                         (4U)
58512 
58513 /*! @name OCTRL - Output Control Register */
58514 /*! @{ */
58515 
58516 #define PWM_OCTRL_PWMXFS_MASK                    (0x3U)
58517 #define PWM_OCTRL_PWMXFS_SHIFT                   (0U)
58518 /*! PWMXFS - PWM_X Fault State
58519  *  0b00..Output is forced to logic 0 state prior to consideration of output polarity control.
58520  *  0b01..Output is forced to logic 1 state prior to consideration of output polarity control.
58521  *  0b10, 0b11..Output is put in a high-impedance state.
58522  */
58523 #define PWM_OCTRL_PWMXFS(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMXFS_SHIFT)) & PWM_OCTRL_PWMXFS_MASK)
58524 
58525 #define PWM_OCTRL_PWMBFS_MASK                    (0xCU)
58526 #define PWM_OCTRL_PWMBFS_SHIFT                   (2U)
58527 /*! PWMBFS - PWM_B Fault State
58528  *  0b00..Output is forced to logic 0 state prior to consideration of output polarity control.
58529  *  0b01..Output is forced to logic 1 state prior to consideration of output polarity control.
58530  *  0b10, 0b11..Output is put in a high-impedance state.
58531  */
58532 #define PWM_OCTRL_PWMBFS(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMBFS_SHIFT)) & PWM_OCTRL_PWMBFS_MASK)
58533 
58534 #define PWM_OCTRL_PWMAFS_MASK                    (0x30U)
58535 #define PWM_OCTRL_PWMAFS_SHIFT                   (4U)
58536 /*! PWMAFS - PWM_A Fault State
58537  *  0b00..Output is forced to logic 0 state prior to consideration of output polarity control.
58538  *  0b01..Output is forced to logic 1 state prior to consideration of output polarity control.
58539  *  0b10, 0b11..Output is put in a high-impedance state.
58540  */
58541 #define PWM_OCTRL_PWMAFS(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMAFS_SHIFT)) & PWM_OCTRL_PWMAFS_MASK)
58542 
58543 #define PWM_OCTRL_POLX_MASK                      (0x100U)
58544 #define PWM_OCTRL_POLX_SHIFT                     (8U)
58545 /*! POLX - PWM_X Output Polarity
58546  *  0b0..PWM_X output not inverted. A high level on the PWM_X pin represents the "on" or "active" state.
58547  *  0b1..PWM_X output inverted. A low level on the PWM_X pin represents the "on" or "active" state.
58548  */
58549 #define PWM_OCTRL_POLX(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLX_SHIFT)) & PWM_OCTRL_POLX_MASK)
58550 
58551 #define PWM_OCTRL_POLB_MASK                      (0x200U)
58552 #define PWM_OCTRL_POLB_SHIFT                     (9U)
58553 /*! POLB - PWM_B Output Polarity
58554  *  0b0..PWM_B output not inverted. A high level on the PWM_B pin represents the "on" or "active" state.
58555  *  0b1..PWM_B output inverted. A low level on the PWM_B pin represents the "on" or "active" state.
58556  */
58557 #define PWM_OCTRL_POLB(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLB_SHIFT)) & PWM_OCTRL_POLB_MASK)
58558 
58559 #define PWM_OCTRL_POLA_MASK                      (0x400U)
58560 #define PWM_OCTRL_POLA_SHIFT                     (10U)
58561 /*! POLA - PWM_A Output Polarity
58562  *  0b0..PWM_A output not inverted. A high level on the PWM_A pin represents the "on" or "active" state.
58563  *  0b1..PWM_A output inverted. A low level on the PWM_A pin represents the "on" or "active" state.
58564  */
58565 #define PWM_OCTRL_POLA(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLA_SHIFT)) & PWM_OCTRL_POLA_MASK)
58566 
58567 #define PWM_OCTRL_PWMX_IN_MASK                   (0x2000U)
58568 #define PWM_OCTRL_PWMX_IN_SHIFT                  (13U)
58569 /*! PWMX_IN - PWM_X Input */
58570 #define PWM_OCTRL_PWMX_IN(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMX_IN_SHIFT)) & PWM_OCTRL_PWMX_IN_MASK)
58571 
58572 #define PWM_OCTRL_PWMB_IN_MASK                   (0x4000U)
58573 #define PWM_OCTRL_PWMB_IN_SHIFT                  (14U)
58574 /*! PWMB_IN - PWM_B Input */
58575 #define PWM_OCTRL_PWMB_IN(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMB_IN_SHIFT)) & PWM_OCTRL_PWMB_IN_MASK)
58576 
58577 #define PWM_OCTRL_PWMA_IN_MASK                   (0x8000U)
58578 #define PWM_OCTRL_PWMA_IN_SHIFT                  (15U)
58579 /*! PWMA_IN - PWM_A Input */
58580 #define PWM_OCTRL_PWMA_IN(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMA_IN_SHIFT)) & PWM_OCTRL_PWMA_IN_MASK)
58581 /*! @} */
58582 
58583 /* The count of PWM_OCTRL */
58584 #define PWM_OCTRL_COUNT                          (4U)
58585 
58586 /*! @name STS - Status Register */
58587 /*! @{ */
58588 
58589 #define PWM_STS_CMPF_MASK                        (0x3FU)
58590 #define PWM_STS_CMPF_SHIFT                       (0U)
58591 /*! CMPF - Compare Flags
58592  *  0b000000..No compare event has occurred for a particular VALx value.
58593  *  0b000001..A compare event has occurred for a particular VALx value.
58594  */
58595 #define PWM_STS_CMPF(x)                          (((uint16_t)(((uint16_t)(x)) << PWM_STS_CMPF_SHIFT)) & PWM_STS_CMPF_MASK)
58596 
58597 #define PWM_STS_CFX0_MASK                        (0x40U)
58598 #define PWM_STS_CFX0_SHIFT                       (6U)
58599 /*! CFX0 - Capture Flag X0 */
58600 #define PWM_STS_CFX0(x)                          (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX0_SHIFT)) & PWM_STS_CFX0_MASK)
58601 
58602 #define PWM_STS_CFX1_MASK                        (0x80U)
58603 #define PWM_STS_CFX1_SHIFT                       (7U)
58604 /*! CFX1 - Capture Flag X1 */
58605 #define PWM_STS_CFX1(x)                          (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX1_SHIFT)) & PWM_STS_CFX1_MASK)
58606 
58607 #define PWM_STS_CFB0_MASK                        (0x100U)
58608 #define PWM_STS_CFB0_SHIFT                       (8U)
58609 /*! CFB0 - Capture Flag B0 */
58610 #define PWM_STS_CFB0(x)                          (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFB0_SHIFT)) & PWM_STS_CFB0_MASK)
58611 
58612 #define PWM_STS_CFB1_MASK                        (0x200U)
58613 #define PWM_STS_CFB1_SHIFT                       (9U)
58614 /*! CFB1 - Capture Flag B1 */
58615 #define PWM_STS_CFB1(x)                          (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFB1_SHIFT)) & PWM_STS_CFB1_MASK)
58616 
58617 #define PWM_STS_CFA0_MASK                        (0x400U)
58618 #define PWM_STS_CFA0_SHIFT                       (10U)
58619 /*! CFA0 - Capture Flag A0 */
58620 #define PWM_STS_CFA0(x)                          (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFA0_SHIFT)) & PWM_STS_CFA0_MASK)
58621 
58622 #define PWM_STS_CFA1_MASK                        (0x800U)
58623 #define PWM_STS_CFA1_SHIFT                       (11U)
58624 /*! CFA1 - Capture Flag A1 */
58625 #define PWM_STS_CFA1(x)                          (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFA1_SHIFT)) & PWM_STS_CFA1_MASK)
58626 
58627 #define PWM_STS_RF_MASK                          (0x1000U)
58628 #define PWM_STS_RF_SHIFT                         (12U)
58629 /*! RF - Reload Flag
58630  *  0b0..No new reload cycle since last STS[RF] clearing
58631  *  0b1..New reload cycle since last STS[RF] clearing
58632  */
58633 #define PWM_STS_RF(x)                            (((uint16_t)(((uint16_t)(x)) << PWM_STS_RF_SHIFT)) & PWM_STS_RF_MASK)
58634 
58635 #define PWM_STS_REF_MASK                         (0x2000U)
58636 #define PWM_STS_REF_SHIFT                        (13U)
58637 /*! REF - Reload Error Flag
58638  *  0b0..No reload error occurred.
58639  *  0b1..Reload signal occurred with non-coherent data and MCTRL[LDOK] = 0.
58640  */
58641 #define PWM_STS_REF(x)                           (((uint16_t)(((uint16_t)(x)) << PWM_STS_REF_SHIFT)) & PWM_STS_REF_MASK)
58642 
58643 #define PWM_STS_RUF_MASK                         (0x4000U)
58644 #define PWM_STS_RUF_SHIFT                        (14U)
58645 /*! RUF - Registers Updated Flag
58646  *  0b0..No register update has occurred since last reload.
58647  *  0b1..At least one of the double buffered registers has been updated since the last reload.
58648  */
58649 #define PWM_STS_RUF(x)                           (((uint16_t)(((uint16_t)(x)) << PWM_STS_RUF_SHIFT)) & PWM_STS_RUF_MASK)
58650 /*! @} */
58651 
58652 /* The count of PWM_STS */
58653 #define PWM_STS_COUNT                            (4U)
58654 
58655 /*! @name INTEN - Interrupt Enable Register */
58656 /*! @{ */
58657 
58658 #define PWM_INTEN_CMPIE_MASK                     (0x3FU)
58659 #define PWM_INTEN_CMPIE_SHIFT                    (0U)
58660 /*! CMPIE - Compare Interrupt Enables
58661  *  0b000000..The corresponding STS[CMPF] bit will not cause an interrupt request.
58662  *  0b000001..The corresponding STS[CMPF] bit will cause an interrupt request.
58663  */
58664 #define PWM_INTEN_CMPIE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CMPIE_SHIFT)) & PWM_INTEN_CMPIE_MASK)
58665 
58666 #define PWM_INTEN_CX0IE_MASK                     (0x40U)
58667 #define PWM_INTEN_CX0IE_SHIFT                    (6U)
58668 /*! CX0IE - Capture X 0 Interrupt Enable
58669  *  0b0..Interrupt request disabled for STS[CFX0].
58670  *  0b1..Interrupt request enabled for STS[CFX0].
58671  */
58672 #define PWM_INTEN_CX0IE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX0IE_SHIFT)) & PWM_INTEN_CX0IE_MASK)
58673 
58674 #define PWM_INTEN_CX1IE_MASK                     (0x80U)
58675 #define PWM_INTEN_CX1IE_SHIFT                    (7U)
58676 /*! CX1IE - Capture X 1 Interrupt Enable
58677  *  0b0..Interrupt request disabled for STS[CFX1].
58678  *  0b1..Interrupt request enabled for STS[CFX1].
58679  */
58680 #define PWM_INTEN_CX1IE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX1IE_SHIFT)) & PWM_INTEN_CX1IE_MASK)
58681 
58682 #define PWM_INTEN_CB0IE_MASK                     (0x100U)
58683 #define PWM_INTEN_CB0IE_SHIFT                    (8U)
58684 /*! CB0IE - Capture B 0 Interrupt Enable
58685  *  0b0..Interrupt request disabled for STS[CFB0].
58686  *  0b1..Interrupt request enabled for STS[CFB0].
58687  */
58688 #define PWM_INTEN_CB0IE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB0IE_SHIFT)) & PWM_INTEN_CB0IE_MASK)
58689 
58690 #define PWM_INTEN_CB1IE_MASK                     (0x200U)
58691 #define PWM_INTEN_CB1IE_SHIFT                    (9U)
58692 /*! CB1IE - Capture B 1 Interrupt Enable
58693  *  0b0..Interrupt request disabled for STS[CFB1].
58694  *  0b1..Interrupt request enabled for STS[CFB1].
58695  */
58696 #define PWM_INTEN_CB1IE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB1IE_SHIFT)) & PWM_INTEN_CB1IE_MASK)
58697 
58698 #define PWM_INTEN_CA0IE_MASK                     (0x400U)
58699 #define PWM_INTEN_CA0IE_SHIFT                    (10U)
58700 /*! CA0IE - Capture A 0 Interrupt Enable
58701  *  0b0..Interrupt request disabled for STS[CFA0].
58702  *  0b1..Interrupt request enabled for STS[CFA0].
58703  */
58704 #define PWM_INTEN_CA0IE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA0IE_SHIFT)) & PWM_INTEN_CA0IE_MASK)
58705 
58706 #define PWM_INTEN_CA1IE_MASK                     (0x800U)
58707 #define PWM_INTEN_CA1IE_SHIFT                    (11U)
58708 /*! CA1IE - Capture A 1 Interrupt Enable
58709  *  0b0..Interrupt request disabled for STS[CFA1]
58710  *  0b1..Interrupt request enabled for STS[CFA1]
58711  */
58712 #define PWM_INTEN_CA1IE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA1IE_SHIFT)) & PWM_INTEN_CA1IE_MASK)
58713 
58714 #define PWM_INTEN_RIE_MASK                       (0x1000U)
58715 #define PWM_INTEN_RIE_SHIFT                      (12U)
58716 /*! RIE - Reload Interrupt Enable
58717  *  0b0..STS[RF] CPU interrupt requests disabled
58718  *  0b1..STS[RF] CPU interrupt requests enabled
58719  */
58720 #define PWM_INTEN_RIE(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_RIE_SHIFT)) & PWM_INTEN_RIE_MASK)
58721 
58722 #define PWM_INTEN_REIE_MASK                      (0x2000U)
58723 #define PWM_INTEN_REIE_SHIFT                     (13U)
58724 /*! REIE - Reload Error Interrupt Enable
58725  *  0b0..STS[REF] CPU interrupt requests disabled
58726  *  0b1..STS[REF] CPU interrupt requests enabled
58727  */
58728 #define PWM_INTEN_REIE(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_REIE_SHIFT)) & PWM_INTEN_REIE_MASK)
58729 /*! @} */
58730 
58731 /* The count of PWM_INTEN */
58732 #define PWM_INTEN_COUNT                          (4U)
58733 
58734 /*! @name DMAEN - DMA Enable Register */
58735 /*! @{ */
58736 
58737 #define PWM_DMAEN_CX0DE_MASK                     (0x1U)
58738 #define PWM_DMAEN_CX0DE_SHIFT                    (0U)
58739 /*! CX0DE - Capture X0 FIFO DMA Enable */
58740 #define PWM_DMAEN_CX0DE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX0DE_SHIFT)) & PWM_DMAEN_CX0DE_MASK)
58741 
58742 #define PWM_DMAEN_CX1DE_MASK                     (0x2U)
58743 #define PWM_DMAEN_CX1DE_SHIFT                    (1U)
58744 /*! CX1DE - Capture X1 FIFO DMA Enable */
58745 #define PWM_DMAEN_CX1DE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX1DE_SHIFT)) & PWM_DMAEN_CX1DE_MASK)
58746 
58747 #define PWM_DMAEN_CB0DE_MASK                     (0x4U)
58748 #define PWM_DMAEN_CB0DE_SHIFT                    (2U)
58749 /*! CB0DE - Capture B0 FIFO DMA Enable */
58750 #define PWM_DMAEN_CB0DE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CB0DE_SHIFT)) & PWM_DMAEN_CB0DE_MASK)
58751 
58752 #define PWM_DMAEN_CB1DE_MASK                     (0x8U)
58753 #define PWM_DMAEN_CB1DE_SHIFT                    (3U)
58754 /*! CB1DE - Capture B1 FIFO DMA Enable */
58755 #define PWM_DMAEN_CB1DE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CB1DE_SHIFT)) & PWM_DMAEN_CB1DE_MASK)
58756 
58757 #define PWM_DMAEN_CA0DE_MASK                     (0x10U)
58758 #define PWM_DMAEN_CA0DE_SHIFT                    (4U)
58759 /*! CA0DE - Capture A0 FIFO DMA Enable */
58760 #define PWM_DMAEN_CA0DE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CA0DE_SHIFT)) & PWM_DMAEN_CA0DE_MASK)
58761 
58762 #define PWM_DMAEN_CA1DE_MASK                     (0x20U)
58763 #define PWM_DMAEN_CA1DE_SHIFT                    (5U)
58764 /*! CA1DE - Capture A1 FIFO DMA Enable */
58765 #define PWM_DMAEN_CA1DE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CA1DE_SHIFT)) & PWM_DMAEN_CA1DE_MASK)
58766 
58767 #define PWM_DMAEN_CAPTDE_MASK                    (0xC0U)
58768 #define PWM_DMAEN_CAPTDE_SHIFT                   (6U)
58769 /*! CAPTDE - Capture DMA Enable Source Select
58770  *  0b00..Read DMA requests disabled.
58771  *  0b01..Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN[CA1DE],
58772  *        DMAEN[CA0DE], DMAEN[CB1DE], DMAEN[CB0DE], DMAEN[CX1DE], or DMAEN[CX0DE] to be set to determine which
58773  *        watermark(s) the DMA request is sensitive.
58774  *  0b10..A local synchronization (VAL1 matches counter) sets the read DMA request.
58775  *  0b11..A local reload (STS[RF] being set) sets the read DMA request.
58776  */
58777 #define PWM_DMAEN_CAPTDE(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CAPTDE_SHIFT)) & PWM_DMAEN_CAPTDE_MASK)
58778 
58779 #define PWM_DMAEN_FAND_MASK                      (0x100U)
58780 #define PWM_DMAEN_FAND_SHIFT                     (8U)
58781 /*! FAND - FIFO Watermark AND Control
58782  *  0b0..Selected FIFO watermarks are OR'ed together.
58783  *  0b1..Selected FIFO watermarks are AND'ed together.
58784  */
58785 #define PWM_DMAEN_FAND(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_FAND_SHIFT)) & PWM_DMAEN_FAND_MASK)
58786 
58787 #define PWM_DMAEN_VALDE_MASK                     (0x200U)
58788 #define PWM_DMAEN_VALDE_SHIFT                    (9U)
58789 /*! VALDE - Value Registers DMA Enable
58790  *  0b0..DMA write requests disabled
58791  *  0b1..Enabled
58792  */
58793 #define PWM_DMAEN_VALDE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_VALDE_SHIFT)) & PWM_DMAEN_VALDE_MASK)
58794 /*! @} */
58795 
58796 /* The count of PWM_DMAEN */
58797 #define PWM_DMAEN_COUNT                          (4U)
58798 
58799 /*! @name TCTRL - Output Trigger Control Register */
58800 /*! @{ */
58801 
58802 #define PWM_TCTRL_OUT_TRIG_EN_MASK               (0x3FU)
58803 #define PWM_TCTRL_OUT_TRIG_EN_SHIFT              (0U)
58804 /*! OUT_TRIG_EN - Output Trigger Enables
58805  *  0bxxxxx1..PWM_OUT_TRIG0 will set when the counter value matches the VAL0 value.
58806  *  0bxxxx1x..PWM_OUT_TRIG1 will set when the counter value matches the VAL1 value.
58807  *  0bxxx1xx..PWM_OUT_TRIG0 will set when the counter value matches the VAL2 value.
58808  *  0bxx1xxx..PWM_OUT_TRIG1 will set when the counter value matches the VAL3 value.
58809  *  0bx1xxxx..PWM_OUT_TRIG0 will set when the counter value matches the VAL4 value.
58810  *  0b1xxxxx..PWM_OUT_TRIG1 will set when the counter value matches the VAL5 value.
58811  */
58812 #define PWM_TCTRL_OUT_TRIG_EN(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_OUT_TRIG_EN_SHIFT)) & PWM_TCTRL_OUT_TRIG_EN_MASK)
58813 
58814 #define PWM_TCTRL_TRGFRQ_MASK                    (0x1000U)
58815 #define PWM_TCTRL_TRGFRQ_SHIFT                   (12U)
58816 /*! TRGFRQ - Trigger Frequency
58817  *  0b0..Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero.
58818  *  0b1..Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM
58819  *       is not reloaded every period due to CTRL[LDFQ] being non-zero.
58820  */
58821 #define PWM_TCTRL_TRGFRQ(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_TRGFRQ_SHIFT)) & PWM_TCTRL_TRGFRQ_MASK)
58822 
58823 #define PWM_TCTRL_PWBOT1_MASK                    (0x4000U)
58824 #define PWM_TCTRL_PWBOT1_SHIFT                   (14U)
58825 /*! PWBOT1 - Mux Output Trigger 1 Source Select
58826  *  0b0..Route the PWM_OUT_TRIG1 signal to PWM_MUX_TRIG1 port.
58827  *  0b1..Route the PWM_B output to the PWM_MUX_TRIG1 port.
58828  */
58829 #define PWM_TCTRL_PWBOT1(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWBOT1_SHIFT)) & PWM_TCTRL_PWBOT1_MASK)
58830 
58831 #define PWM_TCTRL_PWAOT0_MASK                    (0x8000U)
58832 #define PWM_TCTRL_PWAOT0_SHIFT                   (15U)
58833 /*! PWAOT0 - Mux Output Trigger 0 Source Select
58834  *  0b0..Route the PWM_OUT_TRIG0 signal to PWM_MUX_TRIG0 port.
58835  *  0b1..Route the PWM_A output to the PWM_MUX_TRIG0 port.
58836  */
58837 #define PWM_TCTRL_PWAOT0(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWAOT0_SHIFT)) & PWM_TCTRL_PWAOT0_MASK)
58838 /*! @} */
58839 
58840 /* The count of PWM_TCTRL */
58841 #define PWM_TCTRL_COUNT                          (4U)
58842 
58843 /*! @name DISMAP - Fault Disable Mapping Register 0 */
58844 /*! @{ */
58845 
58846 #define PWM_DISMAP_DIS0A_MASK                    (0xFU)
58847 #define PWM_DISMAP_DIS0A_SHIFT                   (0U)
58848 /*! DIS0A - PWM_A Fault Disable Mask 0 */
58849 #define PWM_DISMAP_DIS0A(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0A_SHIFT)) & PWM_DISMAP_DIS0A_MASK)
58850 
58851 #define PWM_DISMAP_DIS0B_MASK                    (0xF0U)
58852 #define PWM_DISMAP_DIS0B_SHIFT                   (4U)
58853 /*! DIS0B - PWM_B Fault Disable Mask 0 */
58854 #define PWM_DISMAP_DIS0B(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0B_SHIFT)) & PWM_DISMAP_DIS0B_MASK)
58855 
58856 #define PWM_DISMAP_DIS0X_MASK                    (0xF00U)
58857 #define PWM_DISMAP_DIS0X_SHIFT                   (8U)
58858 /*! DIS0X - PWM_X Fault Disable Mask 0 */
58859 #define PWM_DISMAP_DIS0X(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0X_SHIFT)) & PWM_DISMAP_DIS0X_MASK)
58860 /*! @} */
58861 
58862 /* The count of PWM_DISMAP */
58863 #define PWM_DISMAP_COUNT                         (4U)
58864 
58865 /* The count of PWM_DISMAP */
58866 #define PWM_DISMAP_COUNT2                        (1U)
58867 
58868 /*! @name DTCNT0 - Deadtime Count Register 0 */
58869 /*! @{ */
58870 
58871 #define PWM_DTCNT0_DTCNT0_MASK                   (0x7FFU)
58872 #define PWM_DTCNT0_DTCNT0_SHIFT                  (0U)
58873 /*! DTCNT0 - Deadtime Count Register 0 */
58874 #define PWM_DTCNT0_DTCNT0(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT0_DTCNT0_SHIFT)) & PWM_DTCNT0_DTCNT0_MASK)
58875 /*! @} */
58876 
58877 /* The count of PWM_DTCNT0 */
58878 #define PWM_DTCNT0_COUNT                         (4U)
58879 
58880 /*! @name DTCNT1 - Deadtime Count Register 1 */
58881 /*! @{ */
58882 
58883 #define PWM_DTCNT1_DTCNT1_MASK                   (0x7FFU)
58884 #define PWM_DTCNT1_DTCNT1_SHIFT                  (0U)
58885 /*! DTCNT1 - Deadtime Count Register 1 */
58886 #define PWM_DTCNT1_DTCNT1(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT1_DTCNT1_SHIFT)) & PWM_DTCNT1_DTCNT1_MASK)
58887 /*! @} */
58888 
58889 /* The count of PWM_DTCNT1 */
58890 #define PWM_DTCNT1_COUNT                         (4U)
58891 
58892 /*! @name CAPTCTRLA - Capture Control A Register */
58893 /*! @{ */
58894 
58895 #define PWM_CAPTCTRLA_ARMA_MASK                  (0x1U)
58896 #define PWM_CAPTCTRLA_ARMA_SHIFT                 (0U)
58897 /*! ARMA - Arm A
58898  *  0b0..Input capture operation is disabled.
58899  *  0b1..Input capture operation as specified by CAPTCTRLA[EDGAx] is enabled.
58900  */
58901 #define PWM_CAPTCTRLA_ARMA(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ARMA_SHIFT)) & PWM_CAPTCTRLA_ARMA_MASK)
58902 
58903 #define PWM_CAPTCTRLA_ONESHOTA_MASK              (0x2U)
58904 #define PWM_CAPTCTRLA_ONESHOTA_SHIFT             (1U)
58905 /*! ONESHOTA - One Shot Mode A
58906  *  0b0..Free Running
58907  *  0b1..One Shot
58908  */
58909 #define PWM_CAPTCTRLA_ONESHOTA(x)                (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ONESHOTA_SHIFT)) & PWM_CAPTCTRLA_ONESHOTA_MASK)
58910 
58911 #define PWM_CAPTCTRLA_EDGA0_MASK                 (0xCU)
58912 #define PWM_CAPTCTRLA_EDGA0_SHIFT                (2U)
58913 /*! EDGA0 - Edge A 0
58914  *  0b00..Disabled
58915  *  0b01..Capture falling edges
58916  *  0b10..Capture rising edges
58917  *  0b11..Capture any edge
58918  */
58919 #define PWM_CAPTCTRLA_EDGA0(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGA0_SHIFT)) & PWM_CAPTCTRLA_EDGA0_MASK)
58920 
58921 #define PWM_CAPTCTRLA_EDGA1_MASK                 (0x30U)
58922 #define PWM_CAPTCTRLA_EDGA1_SHIFT                (4U)
58923 /*! EDGA1 - Edge A 1
58924  *  0b00..Disabled
58925  *  0b01..Capture falling edges
58926  *  0b10..Capture rising edges
58927  *  0b11..Capture any edge
58928  */
58929 #define PWM_CAPTCTRLA_EDGA1(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGA1_SHIFT)) & PWM_CAPTCTRLA_EDGA1_MASK)
58930 
58931 #define PWM_CAPTCTRLA_INP_SELA_MASK              (0x40U)
58932 #define PWM_CAPTCTRLA_INP_SELA_SHIFT             (6U)
58933 /*! INP_SELA - Input Select A
58934  *  0b0..Raw PWM_A input signal selected as source.
58935  *  0b1..Edge Counter
58936  */
58937 #define PWM_CAPTCTRLA_INP_SELA(x)                (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_INP_SELA_SHIFT)) & PWM_CAPTCTRLA_INP_SELA_MASK)
58938 
58939 #define PWM_CAPTCTRLA_EDGCNTA_EN_MASK            (0x80U)
58940 #define PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT           (7U)
58941 /*! EDGCNTA_EN - Edge Counter A Enable
58942  *  0b0..Edge counter disabled and held in reset
58943  *  0b1..Edge counter enabled
58944  */
58945 #define PWM_CAPTCTRLA_EDGCNTA_EN(x)              (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT)) & PWM_CAPTCTRLA_EDGCNTA_EN_MASK)
58946 
58947 #define PWM_CAPTCTRLA_CFAWM_MASK                 (0x300U)
58948 #define PWM_CAPTCTRLA_CFAWM_SHIFT                (8U)
58949 /*! CFAWM - Capture A FIFOs Water Mark */
58950 #define PWM_CAPTCTRLA_CFAWM(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CFAWM_SHIFT)) & PWM_CAPTCTRLA_CFAWM_MASK)
58951 
58952 #define PWM_CAPTCTRLA_CA0CNT_MASK                (0x1C00U)
58953 #define PWM_CAPTCTRLA_CA0CNT_SHIFT               (10U)
58954 /*! CA0CNT - Capture A0 FIFO Word Count */
58955 #define PWM_CAPTCTRLA_CA0CNT(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CA0CNT_SHIFT)) & PWM_CAPTCTRLA_CA0CNT_MASK)
58956 
58957 #define PWM_CAPTCTRLA_CA1CNT_MASK                (0xE000U)
58958 #define PWM_CAPTCTRLA_CA1CNT_SHIFT               (13U)
58959 /*! CA1CNT - Capture A1 FIFO Word Count */
58960 #define PWM_CAPTCTRLA_CA1CNT(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CA1CNT_SHIFT)) & PWM_CAPTCTRLA_CA1CNT_MASK)
58961 /*! @} */
58962 
58963 /* The count of PWM_CAPTCTRLA */
58964 #define PWM_CAPTCTRLA_COUNT                      (4U)
58965 
58966 /*! @name CAPTCOMPA - Capture Compare A Register */
58967 /*! @{ */
58968 
58969 #define PWM_CAPTCOMPA_EDGCMPA_MASK               (0xFFU)
58970 #define PWM_CAPTCOMPA_EDGCMPA_SHIFT              (0U)
58971 /*! EDGCMPA - Edge Compare A */
58972 #define PWM_CAPTCOMPA_EDGCMPA(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPA_EDGCMPA_SHIFT)) & PWM_CAPTCOMPA_EDGCMPA_MASK)
58973 
58974 #define PWM_CAPTCOMPA_EDGCNTA_MASK               (0xFF00U)
58975 #define PWM_CAPTCOMPA_EDGCNTA_SHIFT              (8U)
58976 /*! EDGCNTA - Edge Counter A */
58977 #define PWM_CAPTCOMPA_EDGCNTA(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPA_EDGCNTA_SHIFT)) & PWM_CAPTCOMPA_EDGCNTA_MASK)
58978 /*! @} */
58979 
58980 /* The count of PWM_CAPTCOMPA */
58981 #define PWM_CAPTCOMPA_COUNT                      (4U)
58982 
58983 /*! @name CAPTCTRLB - Capture Control B Register */
58984 /*! @{ */
58985 
58986 #define PWM_CAPTCTRLB_ARMB_MASK                  (0x1U)
58987 #define PWM_CAPTCTRLB_ARMB_SHIFT                 (0U)
58988 /*! ARMB - Arm B
58989  *  0b0..Input capture operation is disabled.
58990  *  0b1..Input capture operation as specified by CAPTCTRLB[EDGBx] is enabled.
58991  */
58992 #define PWM_CAPTCTRLB_ARMB(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ARMB_SHIFT)) & PWM_CAPTCTRLB_ARMB_MASK)
58993 
58994 #define PWM_CAPTCTRLB_ONESHOTB_MASK              (0x2U)
58995 #define PWM_CAPTCTRLB_ONESHOTB_SHIFT             (1U)
58996 /*! ONESHOTB - One Shot Mode B
58997  *  0b0..Free Running
58998  *  0b1..One Shot
58999  */
59000 #define PWM_CAPTCTRLB_ONESHOTB(x)                (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ONESHOTB_SHIFT)) & PWM_CAPTCTRLB_ONESHOTB_MASK)
59001 
59002 #define PWM_CAPTCTRLB_EDGB0_MASK                 (0xCU)
59003 #define PWM_CAPTCTRLB_EDGB0_SHIFT                (2U)
59004 /*! EDGB0 - Edge B 0
59005  *  0b00..Disabled
59006  *  0b01..Capture falling edges
59007  *  0b10..Capture rising edges
59008  *  0b11..Capture any edge
59009  */
59010 #define PWM_CAPTCTRLB_EDGB0(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGB0_SHIFT)) & PWM_CAPTCTRLB_EDGB0_MASK)
59011 
59012 #define PWM_CAPTCTRLB_EDGB1_MASK                 (0x30U)
59013 #define PWM_CAPTCTRLB_EDGB1_SHIFT                (4U)
59014 /*! EDGB1 - Edge B 1
59015  *  0b00..Disabled
59016  *  0b01..Capture falling edges
59017  *  0b10..Capture rising edges
59018  *  0b11..Capture any edge
59019  */
59020 #define PWM_CAPTCTRLB_EDGB1(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGB1_SHIFT)) & PWM_CAPTCTRLB_EDGB1_MASK)
59021 
59022 #define PWM_CAPTCTRLB_INP_SELB_MASK              (0x40U)
59023 #define PWM_CAPTCTRLB_INP_SELB_SHIFT             (6U)
59024 /*! INP_SELB - Input Select B
59025  *  0b0..Raw PWM_B input signal selected as source.
59026  *  0b1..Edge Counter
59027  */
59028 #define PWM_CAPTCTRLB_INP_SELB(x)                (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_INP_SELB_SHIFT)) & PWM_CAPTCTRLB_INP_SELB_MASK)
59029 
59030 #define PWM_CAPTCTRLB_EDGCNTB_EN_MASK            (0x80U)
59031 #define PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT           (7U)
59032 /*! EDGCNTB_EN - Edge Counter B Enable
59033  *  0b0..Edge counter disabled and held in reset
59034  *  0b1..Edge counter enabled
59035  */
59036 #define PWM_CAPTCTRLB_EDGCNTB_EN(x)              (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT)) & PWM_CAPTCTRLB_EDGCNTB_EN_MASK)
59037 
59038 #define PWM_CAPTCTRLB_CFBWM_MASK                 (0x300U)
59039 #define PWM_CAPTCTRLB_CFBWM_SHIFT                (8U)
59040 /*! CFBWM - Capture B FIFOs Water Mark */
59041 #define PWM_CAPTCTRLB_CFBWM(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CFBWM_SHIFT)) & PWM_CAPTCTRLB_CFBWM_MASK)
59042 
59043 #define PWM_CAPTCTRLB_CB0CNT_MASK                (0x1C00U)
59044 #define PWM_CAPTCTRLB_CB0CNT_SHIFT               (10U)
59045 /*! CB0CNT - Capture B0 FIFO Word Count */
59046 #define PWM_CAPTCTRLB_CB0CNT(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CB0CNT_SHIFT)) & PWM_CAPTCTRLB_CB0CNT_MASK)
59047 
59048 #define PWM_CAPTCTRLB_CB1CNT_MASK                (0xE000U)
59049 #define PWM_CAPTCTRLB_CB1CNT_SHIFT               (13U)
59050 /*! CB1CNT - Capture B1 FIFO Word Count */
59051 #define PWM_CAPTCTRLB_CB1CNT(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CB1CNT_SHIFT)) & PWM_CAPTCTRLB_CB1CNT_MASK)
59052 /*! @} */
59053 
59054 /* The count of PWM_CAPTCTRLB */
59055 #define PWM_CAPTCTRLB_COUNT                      (4U)
59056 
59057 /*! @name CAPTCOMPB - Capture Compare B Register */
59058 /*! @{ */
59059 
59060 #define PWM_CAPTCOMPB_EDGCMPB_MASK               (0xFFU)
59061 #define PWM_CAPTCOMPB_EDGCMPB_SHIFT              (0U)
59062 /*! EDGCMPB - Edge Compare B */
59063 #define PWM_CAPTCOMPB_EDGCMPB(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPB_EDGCMPB_SHIFT)) & PWM_CAPTCOMPB_EDGCMPB_MASK)
59064 
59065 #define PWM_CAPTCOMPB_EDGCNTB_MASK               (0xFF00U)
59066 #define PWM_CAPTCOMPB_EDGCNTB_SHIFT              (8U)
59067 /*! EDGCNTB - Edge Counter B */
59068 #define PWM_CAPTCOMPB_EDGCNTB(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPB_EDGCNTB_SHIFT)) & PWM_CAPTCOMPB_EDGCNTB_MASK)
59069 /*! @} */
59070 
59071 /* The count of PWM_CAPTCOMPB */
59072 #define PWM_CAPTCOMPB_COUNT                      (4U)
59073 
59074 /*! @name CAPTCTRLX - Capture Control X Register */
59075 /*! @{ */
59076 
59077 #define PWM_CAPTCTRLX_ARMX_MASK                  (0x1U)
59078 #define PWM_CAPTCTRLX_ARMX_SHIFT                 (0U)
59079 /*! ARMX - Arm X
59080  *  0b0..Input capture operation is disabled.
59081  *  0b1..Input capture operation as specified by CAPTCTRLX[EDGXx] is enabled.
59082  */
59083 #define PWM_CAPTCTRLX_ARMX(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ARMX_SHIFT)) & PWM_CAPTCTRLX_ARMX_MASK)
59084 
59085 #define PWM_CAPTCTRLX_ONESHOTX_MASK              (0x2U)
59086 #define PWM_CAPTCTRLX_ONESHOTX_SHIFT             (1U)
59087 /*! ONESHOTX - One Shot Mode Aux
59088  *  0b0..Free Running
59089  *  0b1..One Shot
59090  */
59091 #define PWM_CAPTCTRLX_ONESHOTX(x)                (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ONESHOTX_SHIFT)) & PWM_CAPTCTRLX_ONESHOTX_MASK)
59092 
59093 #define PWM_CAPTCTRLX_EDGX0_MASK                 (0xCU)
59094 #define PWM_CAPTCTRLX_EDGX0_SHIFT                (2U)
59095 /*! EDGX0 - Edge X 0
59096  *  0b00..Disabled
59097  *  0b01..Capture falling edges
59098  *  0b10..Capture rising edges
59099  *  0b11..Capture any edge
59100  */
59101 #define PWM_CAPTCTRLX_EDGX0(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX0_SHIFT)) & PWM_CAPTCTRLX_EDGX0_MASK)
59102 
59103 #define PWM_CAPTCTRLX_EDGX1_MASK                 (0x30U)
59104 #define PWM_CAPTCTRLX_EDGX1_SHIFT                (4U)
59105 /*! EDGX1 - Edge X 1
59106  *  0b00..Disabled
59107  *  0b01..Capture falling edges
59108  *  0b10..Capture rising edges
59109  *  0b11..Capture any edge
59110  */
59111 #define PWM_CAPTCTRLX_EDGX1(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX1_SHIFT)) & PWM_CAPTCTRLX_EDGX1_MASK)
59112 
59113 #define PWM_CAPTCTRLX_INP_SELX_MASK              (0x40U)
59114 #define PWM_CAPTCTRLX_INP_SELX_SHIFT             (6U)
59115 /*! INP_SELX - Input Select X
59116  *  0b0..Raw PWM_X input signal selected as source.
59117  *  0b1..Edge Counter
59118  */
59119 #define PWM_CAPTCTRLX_INP_SELX(x)                (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_INP_SELX_SHIFT)) & PWM_CAPTCTRLX_INP_SELX_MASK)
59120 
59121 #define PWM_CAPTCTRLX_EDGCNTX_EN_MASK            (0x80U)
59122 #define PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT           (7U)
59123 /*! EDGCNTX_EN - Edge Counter X Enable
59124  *  0b0..Edge counter disabled and held in reset
59125  *  0b1..Edge counter enabled
59126  */
59127 #define PWM_CAPTCTRLX_EDGCNTX_EN(x)              (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT)) & PWM_CAPTCTRLX_EDGCNTX_EN_MASK)
59128 
59129 #define PWM_CAPTCTRLX_CFXWM_MASK                 (0x300U)
59130 #define PWM_CAPTCTRLX_CFXWM_SHIFT                (8U)
59131 /*! CFXWM - Capture X FIFOs Water Mark */
59132 #define PWM_CAPTCTRLX_CFXWM(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CFXWM_SHIFT)) & PWM_CAPTCTRLX_CFXWM_MASK)
59133 
59134 #define PWM_CAPTCTRLX_CX0CNT_MASK                (0x1C00U)
59135 #define PWM_CAPTCTRLX_CX0CNT_SHIFT               (10U)
59136 /*! CX0CNT - Capture X0 FIFO Word Count */
59137 #define PWM_CAPTCTRLX_CX0CNT(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX0CNT_SHIFT)) & PWM_CAPTCTRLX_CX0CNT_MASK)
59138 
59139 #define PWM_CAPTCTRLX_CX1CNT_MASK                (0xE000U)
59140 #define PWM_CAPTCTRLX_CX1CNT_SHIFT               (13U)
59141 /*! CX1CNT - Capture X1 FIFO Word Count */
59142 #define PWM_CAPTCTRLX_CX1CNT(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX1CNT_SHIFT)) & PWM_CAPTCTRLX_CX1CNT_MASK)
59143 /*! @} */
59144 
59145 /* The count of PWM_CAPTCTRLX */
59146 #define PWM_CAPTCTRLX_COUNT                      (4U)
59147 
59148 /*! @name CAPTCOMPX - Capture Compare X Register */
59149 /*! @{ */
59150 
59151 #define PWM_CAPTCOMPX_EDGCMPX_MASK               (0xFFU)
59152 #define PWM_CAPTCOMPX_EDGCMPX_SHIFT              (0U)
59153 /*! EDGCMPX - Edge Compare X */
59154 #define PWM_CAPTCOMPX_EDGCMPX(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCMPX_SHIFT)) & PWM_CAPTCOMPX_EDGCMPX_MASK)
59155 
59156 #define PWM_CAPTCOMPX_EDGCNTX_MASK               (0xFF00U)
59157 #define PWM_CAPTCOMPX_EDGCNTX_SHIFT              (8U)
59158 /*! EDGCNTX - Edge Counter X */
59159 #define PWM_CAPTCOMPX_EDGCNTX(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCNTX_SHIFT)) & PWM_CAPTCOMPX_EDGCNTX_MASK)
59160 /*! @} */
59161 
59162 /* The count of PWM_CAPTCOMPX */
59163 #define PWM_CAPTCOMPX_COUNT                      (4U)
59164 
59165 /*! @name CVAL0 - Capture Value 0 Register */
59166 /*! @{ */
59167 
59168 #define PWM_CVAL0_CAPTVAL0_MASK                  (0xFFFFU)
59169 #define PWM_CVAL0_CAPTVAL0_SHIFT                 (0U)
59170 /*! CAPTVAL0 - Capture Value 0 */
59171 #define PWM_CVAL0_CAPTVAL0(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0_CAPTVAL0_SHIFT)) & PWM_CVAL0_CAPTVAL0_MASK)
59172 /*! @} */
59173 
59174 /* The count of PWM_CVAL0 */
59175 #define PWM_CVAL0_COUNT                          (4U)
59176 
59177 /*! @name CVAL0CYC - Capture Value 0 Cycle Register */
59178 /*! @{ */
59179 
59180 #define PWM_CVAL0CYC_CVAL0CYC_MASK               (0xFU)
59181 #define PWM_CVAL0CYC_CVAL0CYC_SHIFT              (0U)
59182 /*! CVAL0CYC - Capture Value 0 Cycle */
59183 #define PWM_CVAL0CYC_CVAL0CYC(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0CYC_CVAL0CYC_SHIFT)) & PWM_CVAL0CYC_CVAL0CYC_MASK)
59184 /*! @} */
59185 
59186 /* The count of PWM_CVAL0CYC */
59187 #define PWM_CVAL0CYC_COUNT                       (4U)
59188 
59189 /*! @name CVAL1 - Capture Value 1 Register */
59190 /*! @{ */
59191 
59192 #define PWM_CVAL1_CAPTVAL1_MASK                  (0xFFFFU)
59193 #define PWM_CVAL1_CAPTVAL1_SHIFT                 (0U)
59194 /*! CAPTVAL1 - Capture Value 1 */
59195 #define PWM_CVAL1_CAPTVAL1(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1_CAPTVAL1_SHIFT)) & PWM_CVAL1_CAPTVAL1_MASK)
59196 /*! @} */
59197 
59198 /* The count of PWM_CVAL1 */
59199 #define PWM_CVAL1_COUNT                          (4U)
59200 
59201 /*! @name CVAL1CYC - Capture Value 1 Cycle Register */
59202 /*! @{ */
59203 
59204 #define PWM_CVAL1CYC_CVAL1CYC_MASK               (0xFU)
59205 #define PWM_CVAL1CYC_CVAL1CYC_SHIFT              (0U)
59206 /*! CVAL1CYC - Capture Value 1 Cycle */
59207 #define PWM_CVAL1CYC_CVAL1CYC(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1CYC_CVAL1CYC_SHIFT)) & PWM_CVAL1CYC_CVAL1CYC_MASK)
59208 /*! @} */
59209 
59210 /* The count of PWM_CVAL1CYC */
59211 #define PWM_CVAL1CYC_COUNT                       (4U)
59212 
59213 /*! @name CVAL2 - Capture Value 2 Register */
59214 /*! @{ */
59215 
59216 #define PWM_CVAL2_CAPTVAL2_MASK                  (0xFFFFU)
59217 #define PWM_CVAL2_CAPTVAL2_SHIFT                 (0U)
59218 /*! CAPTVAL2 - Capture Value 2 */
59219 #define PWM_CVAL2_CAPTVAL2(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_CVAL2_CAPTVAL2_SHIFT)) & PWM_CVAL2_CAPTVAL2_MASK)
59220 /*! @} */
59221 
59222 /* The count of PWM_CVAL2 */
59223 #define PWM_CVAL2_COUNT                          (4U)
59224 
59225 /*! @name CVAL2CYC - Capture Value 2 Cycle Register */
59226 /*! @{ */
59227 
59228 #define PWM_CVAL2CYC_CVAL2CYC_MASK               (0xFU)
59229 #define PWM_CVAL2CYC_CVAL2CYC_SHIFT              (0U)
59230 /*! CVAL2CYC - Capture Value 2 Cycle */
59231 #define PWM_CVAL2CYC_CVAL2CYC(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CVAL2CYC_CVAL2CYC_SHIFT)) & PWM_CVAL2CYC_CVAL2CYC_MASK)
59232 /*! @} */
59233 
59234 /* The count of PWM_CVAL2CYC */
59235 #define PWM_CVAL2CYC_COUNT                       (4U)
59236 
59237 /*! @name CVAL3 - Capture Value 3 Register */
59238 /*! @{ */
59239 
59240 #define PWM_CVAL3_CAPTVAL3_MASK                  (0xFFFFU)
59241 #define PWM_CVAL3_CAPTVAL3_SHIFT                 (0U)
59242 /*! CAPTVAL3 - Capture Value 3 */
59243 #define PWM_CVAL3_CAPTVAL3(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_CVAL3_CAPTVAL3_SHIFT)) & PWM_CVAL3_CAPTVAL3_MASK)
59244 /*! @} */
59245 
59246 /* The count of PWM_CVAL3 */
59247 #define PWM_CVAL3_COUNT                          (4U)
59248 
59249 /*! @name CVAL3CYC - Capture Value 3 Cycle Register */
59250 /*! @{ */
59251 
59252 #define PWM_CVAL3CYC_CVAL3CYC_MASK               (0xFU)
59253 #define PWM_CVAL3CYC_CVAL3CYC_SHIFT              (0U)
59254 /*! CVAL3CYC - Capture Value 3 Cycle */
59255 #define PWM_CVAL3CYC_CVAL3CYC(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CVAL3CYC_CVAL3CYC_SHIFT)) & PWM_CVAL3CYC_CVAL3CYC_MASK)
59256 /*! @} */
59257 
59258 /* The count of PWM_CVAL3CYC */
59259 #define PWM_CVAL3CYC_COUNT                       (4U)
59260 
59261 /*! @name CVAL4 - Capture Value 4 Register */
59262 /*! @{ */
59263 
59264 #define PWM_CVAL4_CAPTVAL4_MASK                  (0xFFFFU)
59265 #define PWM_CVAL4_CAPTVAL4_SHIFT                 (0U)
59266 /*! CAPTVAL4 - Capture Value 4 */
59267 #define PWM_CVAL4_CAPTVAL4(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_CVAL4_CAPTVAL4_SHIFT)) & PWM_CVAL4_CAPTVAL4_MASK)
59268 /*! @} */
59269 
59270 /* The count of PWM_CVAL4 */
59271 #define PWM_CVAL4_COUNT                          (4U)
59272 
59273 /*! @name CVAL4CYC - Capture Value 4 Cycle Register */
59274 /*! @{ */
59275 
59276 #define PWM_CVAL4CYC_CVAL4CYC_MASK               (0xFU)
59277 #define PWM_CVAL4CYC_CVAL4CYC_SHIFT              (0U)
59278 /*! CVAL4CYC - Capture Value 4 Cycle */
59279 #define PWM_CVAL4CYC_CVAL4CYC(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CVAL4CYC_CVAL4CYC_SHIFT)) & PWM_CVAL4CYC_CVAL4CYC_MASK)
59280 /*! @} */
59281 
59282 /* The count of PWM_CVAL4CYC */
59283 #define PWM_CVAL4CYC_COUNT                       (4U)
59284 
59285 /*! @name CVAL5 - Capture Value 5 Register */
59286 /*! @{ */
59287 
59288 #define PWM_CVAL5_CAPTVAL5_MASK                  (0xFFFFU)
59289 #define PWM_CVAL5_CAPTVAL5_SHIFT                 (0U)
59290 /*! CAPTVAL5 - Capture Value 5 */
59291 #define PWM_CVAL5_CAPTVAL5(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_CVAL5_CAPTVAL5_SHIFT)) & PWM_CVAL5_CAPTVAL5_MASK)
59292 /*! @} */
59293 
59294 /* The count of PWM_CVAL5 */
59295 #define PWM_CVAL5_COUNT                          (4U)
59296 
59297 /*! @name CVAL5CYC - Capture Value 5 Cycle Register */
59298 /*! @{ */
59299 
59300 #define PWM_CVAL5CYC_CVAL5CYC_MASK               (0xFU)
59301 #define PWM_CVAL5CYC_CVAL5CYC_SHIFT              (0U)
59302 /*! CVAL5CYC - Capture Value 5 Cycle */
59303 #define PWM_CVAL5CYC_CVAL5CYC(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CVAL5CYC_CVAL5CYC_SHIFT)) & PWM_CVAL5CYC_CVAL5CYC_MASK)
59304 /*! @} */
59305 
59306 /* The count of PWM_CVAL5CYC */
59307 #define PWM_CVAL5CYC_COUNT                       (4U)
59308 
59309 /*! @name PHASEDLY - Phase Delay Register */
59310 /*! @{ */
59311 
59312 #define PWM_PHASEDLY_PHASEDLY_MASK               (0xFFFFU)
59313 #define PWM_PHASEDLY_PHASEDLY_SHIFT              (0U)
59314 /*! PHASEDLY - Initial Count Register Bits */
59315 #define PWM_PHASEDLY_PHASEDLY(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_PHASEDLY_PHASEDLY_SHIFT)) & PWM_PHASEDLY_PHASEDLY_MASK)
59316 /*! @} */
59317 
59318 /* The count of PWM_PHASEDLY */
59319 #define PWM_PHASEDLY_COUNT                       (4U)
59320 
59321 /*! @name CAPTFILTA - Capture PWM_A Input Filter Register */
59322 /*! @{ */
59323 
59324 #define PWM_CAPTFILTA_CAPTA_FILT_PER_MASK        (0xFFU)
59325 #define PWM_CAPTFILTA_CAPTA_FILT_PER_SHIFT       (0U)
59326 /*! CAPTA_FILT_PER - Input Capture Filter Period */
59327 #define PWM_CAPTFILTA_CAPTA_FILT_PER(x)          (((uint16_t)(((uint16_t)(x)) << PWM_CAPTFILTA_CAPTA_FILT_PER_SHIFT)) & PWM_CAPTFILTA_CAPTA_FILT_PER_MASK)
59328 
59329 #define PWM_CAPTFILTA_CAPTA_FILT_CNT_MASK        (0x700U)
59330 #define PWM_CAPTFILTA_CAPTA_FILT_CNT_SHIFT       (8U)
59331 /*! CAPTA_FILT_CNT - Input Capture Filter Count */
59332 #define PWM_CAPTFILTA_CAPTA_FILT_CNT(x)          (((uint16_t)(((uint16_t)(x)) << PWM_CAPTFILTA_CAPTA_FILT_CNT_SHIFT)) & PWM_CAPTFILTA_CAPTA_FILT_CNT_MASK)
59333 /*! @} */
59334 
59335 /* The count of PWM_CAPTFILTA */
59336 #define PWM_CAPTFILTA_COUNT                      (4U)
59337 
59338 /*! @name CAPTFILTB - Capture PWM_B Input Filter Register */
59339 /*! @{ */
59340 
59341 #define PWM_CAPTFILTB_CAPTB_FILT_PER_MASK        (0xFFU)
59342 #define PWM_CAPTFILTB_CAPTB_FILT_PER_SHIFT       (0U)
59343 /*! CAPTB_FILT_PER - Input Capture Filter Period */
59344 #define PWM_CAPTFILTB_CAPTB_FILT_PER(x)          (((uint16_t)(((uint16_t)(x)) << PWM_CAPTFILTB_CAPTB_FILT_PER_SHIFT)) & PWM_CAPTFILTB_CAPTB_FILT_PER_MASK)
59345 
59346 #define PWM_CAPTFILTB_CAPTB_FILT_CNT_MASK        (0x700U)
59347 #define PWM_CAPTFILTB_CAPTB_FILT_CNT_SHIFT       (8U)
59348 /*! CAPTB_FILT_CNT - Input Capture Filter Count */
59349 #define PWM_CAPTFILTB_CAPTB_FILT_CNT(x)          (((uint16_t)(((uint16_t)(x)) << PWM_CAPTFILTB_CAPTB_FILT_CNT_SHIFT)) & PWM_CAPTFILTB_CAPTB_FILT_CNT_MASK)
59350 /*! @} */
59351 
59352 /* The count of PWM_CAPTFILTB */
59353 #define PWM_CAPTFILTB_COUNT                      (4U)
59354 
59355 /*! @name CAPTFILTX - Capture PWM_X Input Filter Register */
59356 /*! @{ */
59357 
59358 #define PWM_CAPTFILTX_CAPTX_FILT_PER_MASK        (0xFFU)
59359 #define PWM_CAPTFILTX_CAPTX_FILT_PER_SHIFT       (0U)
59360 /*! CAPTX_FILT_PER - Input Capture Filter Period */
59361 #define PWM_CAPTFILTX_CAPTX_FILT_PER(x)          (((uint16_t)(((uint16_t)(x)) << PWM_CAPTFILTX_CAPTX_FILT_PER_SHIFT)) & PWM_CAPTFILTX_CAPTX_FILT_PER_MASK)
59362 
59363 #define PWM_CAPTFILTX_CAPTX_FILT_CNT_MASK        (0x700U)
59364 #define PWM_CAPTFILTX_CAPTX_FILT_CNT_SHIFT       (8U)
59365 /*! CAPTX_FILT_CNT - Input Capture Filter Count */
59366 #define PWM_CAPTFILTX_CAPTX_FILT_CNT(x)          (((uint16_t)(((uint16_t)(x)) << PWM_CAPTFILTX_CAPTX_FILT_CNT_SHIFT)) & PWM_CAPTFILTX_CAPTX_FILT_CNT_MASK)
59367 /*! @} */
59368 
59369 /* The count of PWM_CAPTFILTX */
59370 #define PWM_CAPTFILTX_COUNT                      (4U)
59371 
59372 /*! @name OUTEN - Output Enable Register */
59373 /*! @{ */
59374 
59375 #define PWM_OUTEN_PWMX_EN_MASK                   (0xFU)
59376 #define PWM_OUTEN_PWMX_EN_SHIFT                  (0U)
59377 /*! PWMX_EN - PWM_X Output Enables */
59378 #define PWM_OUTEN_PWMX_EN(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMX_EN_SHIFT)) & PWM_OUTEN_PWMX_EN_MASK)
59379 
59380 #define PWM_OUTEN_PWMB_EN_MASK                   (0xF0U)
59381 #define PWM_OUTEN_PWMB_EN_SHIFT                  (4U)
59382 /*! PWMB_EN - PWM_B Output Enables */
59383 #define PWM_OUTEN_PWMB_EN(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMB_EN_SHIFT)) & PWM_OUTEN_PWMB_EN_MASK)
59384 
59385 #define PWM_OUTEN_PWMA_EN_MASK                   (0xF00U)
59386 #define PWM_OUTEN_PWMA_EN_SHIFT                  (8U)
59387 /*! PWMA_EN - PWM_A Output Enables */
59388 #define PWM_OUTEN_PWMA_EN(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMA_EN_SHIFT)) & PWM_OUTEN_PWMA_EN_MASK)
59389 /*! @} */
59390 
59391 /*! @name MASK - Mask Register */
59392 /*! @{ */
59393 
59394 #define PWM_MASK_MASKX_MASK                      (0xFU)
59395 #define PWM_MASK_MASKX_SHIFT                     (0U)
59396 /*! MASKX - PWM_X Masks */
59397 #define PWM_MASK_MASKX(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKX_SHIFT)) & PWM_MASK_MASKX_MASK)
59398 
59399 #define PWM_MASK_MASKB_MASK                      (0xF0U)
59400 #define PWM_MASK_MASKB_SHIFT                     (4U)
59401 /*! MASKB - PWM_B Masks */
59402 #define PWM_MASK_MASKB(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKB_SHIFT)) & PWM_MASK_MASKB_MASK)
59403 
59404 #define PWM_MASK_MASKA_MASK                      (0xF00U)
59405 #define PWM_MASK_MASKA_SHIFT                     (8U)
59406 /*! MASKA - PWM_A Masks */
59407 #define PWM_MASK_MASKA(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKA_SHIFT)) & PWM_MASK_MASKA_MASK)
59408 
59409 #define PWM_MASK_UPDATE_MASK_MASK                (0xF000U)
59410 #define PWM_MASK_UPDATE_MASK_SHIFT               (12U)
59411 /*! UPDATE_MASK - Update Mask Bits Immediately */
59412 #define PWM_MASK_UPDATE_MASK(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_MASK_UPDATE_MASK_SHIFT)) & PWM_MASK_UPDATE_MASK_MASK)
59413 /*! @} */
59414 
59415 /*! @name SWCOUT - Software Controlled Output Register */
59416 /*! @{ */
59417 
59418 #define PWM_SWCOUT_SM0OUT45_MASK                 (0x1U)
59419 #define PWM_SWCOUT_SM0OUT45_SHIFT                (0U)
59420 /*! SM0OUT45 - Submodule 0 Software Controlled Output 45
59421  *  0b0..A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM45.
59422  *  0b1..A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM45.
59423  */
59424 #define PWM_SWCOUT_SM0OUT45(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT45_SHIFT)) & PWM_SWCOUT_SM0OUT45_MASK)
59425 
59426 #define PWM_SWCOUT_SM0OUT23_MASK                 (0x2U)
59427 #define PWM_SWCOUT_SM0OUT23_SHIFT                (1U)
59428 /*! SM0OUT23 - Submodule 0 Software Controlled Output 23
59429  *  0b0..A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM23.
59430  *  0b1..A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM23.
59431  */
59432 #define PWM_SWCOUT_SM0OUT23(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT23_SHIFT)) & PWM_SWCOUT_SM0OUT23_MASK)
59433 
59434 #define PWM_SWCOUT_SM1OUT45_MASK                 (0x4U)
59435 #define PWM_SWCOUT_SM1OUT45_SHIFT                (2U)
59436 /*! SM1OUT45 - Submodule 1 Software Controlled Output 45
59437  *  0b0..A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM45.
59438  *  0b1..A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM45.
59439  */
59440 #define PWM_SWCOUT_SM1OUT45(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT45_SHIFT)) & PWM_SWCOUT_SM1OUT45_MASK)
59441 
59442 #define PWM_SWCOUT_SM1OUT23_MASK                 (0x8U)
59443 #define PWM_SWCOUT_SM1OUT23_SHIFT                (3U)
59444 /*! SM1OUT23 - Submodule 1 Software Controlled Output 23
59445  *  0b0..A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM23.
59446  *  0b1..A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM23.
59447  */
59448 #define PWM_SWCOUT_SM1OUT23(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT23_SHIFT)) & PWM_SWCOUT_SM1OUT23_MASK)
59449 
59450 #define PWM_SWCOUT_SM2OUT45_MASK                 (0x10U)
59451 #define PWM_SWCOUT_SM2OUT45_SHIFT                (4U)
59452 /*! SM2OUT45 - Submodule 2 Software Controlled Output 45
59453  *  0b0..A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM45.
59454  *  0b1..A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM45.
59455  */
59456 #define PWM_SWCOUT_SM2OUT45(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT45_SHIFT)) & PWM_SWCOUT_SM2OUT45_MASK)
59457 
59458 #define PWM_SWCOUT_SM2OUT23_MASK                 (0x20U)
59459 #define PWM_SWCOUT_SM2OUT23_SHIFT                (5U)
59460 /*! SM2OUT23 - Submodule 2 Software Controlled Output 23
59461  *  0b0..A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM23.
59462  *  0b1..A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM23.
59463  */
59464 #define PWM_SWCOUT_SM2OUT23(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT23_SHIFT)) & PWM_SWCOUT_SM2OUT23_MASK)
59465 
59466 #define PWM_SWCOUT_SM3OUT45_MASK                 (0x40U)
59467 #define PWM_SWCOUT_SM3OUT45_SHIFT                (6U)
59468 /*! SM3OUT45 - Submodule 3 Software Controlled Output 45
59469  *  0b0..A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM45.
59470  *  0b1..A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM45.
59471  */
59472 #define PWM_SWCOUT_SM3OUT45(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT45_SHIFT)) & PWM_SWCOUT_SM3OUT45_MASK)
59473 
59474 #define PWM_SWCOUT_SM3OUT23_MASK                 (0x80U)
59475 #define PWM_SWCOUT_SM3OUT23_SHIFT                (7U)
59476 /*! SM3OUT23 - Submodule 3 Software Controlled Output 23
59477  *  0b0..A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM23.
59478  *  0b1..A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM23.
59479  */
59480 #define PWM_SWCOUT_SM3OUT23(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT23_SHIFT)) & PWM_SWCOUT_SM3OUT23_MASK)
59481 /*! @} */
59482 
59483 /*! @name DTSRCSEL - PWM Source Select Register */
59484 /*! @{ */
59485 
59486 #define PWM_DTSRCSEL_SM0SEL45_MASK               (0x3U)
59487 #define PWM_DTSRCSEL_SM0SEL45_SHIFT              (0U)
59488 /*! SM0SEL45 - Submodule 0 PWM45 Control Select
59489  *  0b00..Generated SM0PWM45 signal used by the deadtime logic.
59490  *  0b01..Inverted generated SM0PWM45 signal used by the deadtime logic.
59491  *  0b10..SWCOUT[SM0OUT45] used by the deadtime logic.
59492  *  0b11..Reserved
59493  */
59494 #define PWM_DTSRCSEL_SM0SEL45(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL45_SHIFT)) & PWM_DTSRCSEL_SM0SEL45_MASK)
59495 
59496 #define PWM_DTSRCSEL_SM0SEL23_MASK               (0xCU)
59497 #define PWM_DTSRCSEL_SM0SEL23_SHIFT              (2U)
59498 /*! SM0SEL23 - Submodule 0 PWM23 Control Select
59499  *  0b00..Generated SM0PWM23 signal used by the deadtime logic.
59500  *  0b01..Inverted generated SM0PWM23 signal used by the deadtime logic.
59501  *  0b10..SWCOUT[SM0OUT23] used by the deadtime logic.
59502  *  0b11..PWM0_EXTA signal used by the deadtime logic.
59503  */
59504 #define PWM_DTSRCSEL_SM0SEL23(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL23_SHIFT)) & PWM_DTSRCSEL_SM0SEL23_MASK)
59505 
59506 #define PWM_DTSRCSEL_SM1SEL45_MASK               (0x30U)
59507 #define PWM_DTSRCSEL_SM1SEL45_SHIFT              (4U)
59508 /*! SM1SEL45 - Submodule 1 PWM45 Control Select
59509  *  0b00..Generated SM1PWM45 signal used by the deadtime logic.
59510  *  0b01..Inverted generated SM1PWM45 signal used by the deadtime logic.
59511  *  0b10..SWCOUT[SM1OUT45] used by the deadtime logic.
59512  *  0b11..Reserved
59513  */
59514 #define PWM_DTSRCSEL_SM1SEL45(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL45_SHIFT)) & PWM_DTSRCSEL_SM1SEL45_MASK)
59515 
59516 #define PWM_DTSRCSEL_SM1SEL23_MASK               (0xC0U)
59517 #define PWM_DTSRCSEL_SM1SEL23_SHIFT              (6U)
59518 /*! SM1SEL23 - Submodule 1 PWM23 Control Select
59519  *  0b00..Generated SM1PWM23 signal used by the deadtime logic.
59520  *  0b01..Inverted generated SM1PWM23 signal used by the deadtime logic.
59521  *  0b10..SWCOUT[SM1OUT23] used by the deadtime logic.
59522  *  0b11..PWM1_EXTA signal used by the deadtime logic.
59523  */
59524 #define PWM_DTSRCSEL_SM1SEL23(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL23_SHIFT)) & PWM_DTSRCSEL_SM1SEL23_MASK)
59525 
59526 #define PWM_DTSRCSEL_SM2SEL45_MASK               (0x300U)
59527 #define PWM_DTSRCSEL_SM2SEL45_SHIFT              (8U)
59528 /*! SM2SEL45 - Submodule 2 PWM45 Control Select
59529  *  0b00..Generated SM2PWM45 signal used by the deadtime logic.
59530  *  0b01..Inverted generated SM2PWM45 signal used by the deadtime logic.
59531  *  0b10..SWCOUT[SM2OUT45] used by the deadtime logic.
59532  *  0b11..Reserved
59533  */
59534 #define PWM_DTSRCSEL_SM2SEL45(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL45_SHIFT)) & PWM_DTSRCSEL_SM2SEL45_MASK)
59535 
59536 #define PWM_DTSRCSEL_SM2SEL23_MASK               (0xC00U)
59537 #define PWM_DTSRCSEL_SM2SEL23_SHIFT              (10U)
59538 /*! SM2SEL23 - Submodule 2 PWM23 Control Select
59539  *  0b00..Generated SM2PWM23 signal used by the deadtime logic.
59540  *  0b01..Inverted generated SM2PWM23 signal used by the deadtime logic.
59541  *  0b10..SWCOUT[SM2OUT23] used by the deadtime logic.
59542  *  0b11..PWM2_EXTA signal used by the deadtime logic.
59543  */
59544 #define PWM_DTSRCSEL_SM2SEL23(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL23_SHIFT)) & PWM_DTSRCSEL_SM2SEL23_MASK)
59545 
59546 #define PWM_DTSRCSEL_SM3SEL45_MASK               (0x3000U)
59547 #define PWM_DTSRCSEL_SM3SEL45_SHIFT              (12U)
59548 /*! SM3SEL45 - Submodule 3 PWM45 Control Select
59549  *  0b00..Generated SM3PWM45 signal used by the deadtime logic.
59550  *  0b01..Inverted generated SM3PWM45 signal used by the deadtime logic.
59551  *  0b10..SWCOUT[SM3OUT45] used by the deadtime logic.
59552  *  0b11..Reserved
59553  */
59554 #define PWM_DTSRCSEL_SM3SEL45(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL45_SHIFT)) & PWM_DTSRCSEL_SM3SEL45_MASK)
59555 
59556 #define PWM_DTSRCSEL_SM3SEL23_MASK               (0xC000U)
59557 #define PWM_DTSRCSEL_SM3SEL23_SHIFT              (14U)
59558 /*! SM3SEL23 - Submodule 3 PWM23 Control Select
59559  *  0b00..Generated SM3PWM23 signal used by the deadtime logic.
59560  *  0b01..Inverted generated SM3PWM23 signal used by the deadtime logic.
59561  *  0b10..SWCOUT[SM3OUT23] used by the deadtime logic.
59562  *  0b11..PWM3_EXTA signal used by the deadtime logic.
59563  */
59564 #define PWM_DTSRCSEL_SM3SEL23(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL23_SHIFT)) & PWM_DTSRCSEL_SM3SEL23_MASK)
59565 /*! @} */
59566 
59567 /*! @name MCTRL - Master Control Register */
59568 /*! @{ */
59569 
59570 #define PWM_MCTRL_LDOK_MASK                      (0xFU)
59571 #define PWM_MCTRL_LDOK_SHIFT                     (0U)
59572 /*! LDOK - Load Okay
59573  *  0b0000..Do not load new values.
59574  *  0b0001..Load prescaler, modulus, and PWM values of the corresponding submodule.
59575  */
59576 #define PWM_MCTRL_LDOK(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_LDOK_SHIFT)) & PWM_MCTRL_LDOK_MASK)
59577 
59578 #define PWM_MCTRL_CLDOK_MASK                     (0xF0U)
59579 #define PWM_MCTRL_CLDOK_SHIFT                    (4U)
59580 /*! CLDOK - Clear Load Okay */
59581 #define PWM_MCTRL_CLDOK(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_CLDOK_SHIFT)) & PWM_MCTRL_CLDOK_MASK)
59582 
59583 #define PWM_MCTRL_RUN_MASK                       (0xF00U)
59584 #define PWM_MCTRL_RUN_SHIFT                      (8U)
59585 /*! RUN - Run
59586  *  0b0000..PWM counter is stopped, but PWM outputs hold the current state.
59587  *  0b0001..PWM counter is started in the corresponding submodule.
59588  */
59589 #define PWM_MCTRL_RUN(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_RUN_SHIFT)) & PWM_MCTRL_RUN_MASK)
59590 
59591 #define PWM_MCTRL_IPOL_MASK                      (0xF000U)
59592 #define PWM_MCTRL_IPOL_SHIFT                     (12U)
59593 /*! IPOL - Current Polarity
59594  *  0b0000..PWM23 is used to generate complementary PWM pair in the corresponding submodule.
59595  *  0b0001..PWM45 is used to generate complementary PWM pair in the corresponding submodule.
59596  */
59597 #define PWM_MCTRL_IPOL(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_IPOL_SHIFT)) & PWM_MCTRL_IPOL_MASK)
59598 /*! @} */
59599 
59600 /*! @name MCTRL2 - Master Control 2 Register */
59601 /*! @{ */
59602 
59603 #define PWM_MCTRL2_WRPROT_MASK                   (0xCU)
59604 #define PWM_MCTRL2_WRPROT_SHIFT                  (2U)
59605 /*! WRPROT - Write protect
59606  *  0b00..Write protection off (default).
59607  *  0b01..Write protection on.
59608  *  0b10..Write protection off and locked until chip reset.
59609  *  0b11..Write protection on and locked until chip reset.
59610  */
59611 #define PWM_MCTRL2_WRPROT(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL2_WRPROT_SHIFT)) & PWM_MCTRL2_WRPROT_MASK)
59612 
59613 #define PWM_MCTRL2_STRETCH_CNT_PRSC_MASK         (0xC0U)
59614 #define PWM_MCTRL2_STRETCH_CNT_PRSC_SHIFT        (6U)
59615 /*! STRETCH_CNT_PRSC - Stretch IPBus clock count prescaler for mux0_trig/mux1_trig/out0_trig/out1_trig/pwma_trig/pwmb_trig
59616  *  0b00..Stretch count is zero, no stretch.
59617  *  0b01..Stretch mux0_trig/mux1_trig/out0_trig/out1_trig/pwma_trig/pwmb_trig for 2 IPBus clock period.
59618  *  0b10..Stretch mux0_trig/mux1_trig/out0_trig/out1_trig/pwma_trig/pwmb_trig for 4 IPBus clock period.
59619  *  0b11..Stretch mux0_trig/mux1_trig/out0_trig/out1_trig/pwma_trig/pwmb_trig for 8 IPBus clock period.
59620  */
59621 #define PWM_MCTRL2_STRETCH_CNT_PRSC(x)           (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL2_STRETCH_CNT_PRSC_SHIFT)) & PWM_MCTRL2_STRETCH_CNT_PRSC_MASK)
59622 /*! @} */
59623 
59624 /*! @name FCTRL - Fault Control Register */
59625 /*! @{ */
59626 
59627 #define PWM_FCTRL_FIE_MASK                       (0xFU)
59628 #define PWM_FCTRL_FIE_SHIFT                      (0U)
59629 /*! FIE - Fault Interrupt Enables
59630  *  0b0000..FAULTx CPU interrupt requests disabled.
59631  *  0b0001..FAULTx CPU interrupt requests enabled.
59632  */
59633 #define PWM_FCTRL_FIE(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FIE_SHIFT)) & PWM_FCTRL_FIE_MASK)
59634 
59635 #define PWM_FCTRL_FSAFE_MASK                     (0xF0U)
59636 #define PWM_FCTRL_FSAFE_SHIFT                    (4U)
59637 /*! FSAFE - Fault Safety Mode
59638  *  0b0000..Normal mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear at the
59639  *          start of a half cycle or full cycle depending on the states of FSTS[FHALF] and FSTS[FFULL] without regard
59640  *          to the state of FSTS[FFPINx]. If neither FHALF nor FFULL is set, then the fault condition cannot be
59641  *          cleared. The PWM outputs disabled by this fault input will not be re-enabled until the actual FAULTx input
59642  *          signal de-asserts since the fault input will combinationally disable the PWM outputs (as programmed in
59643  *          DISMAPn).
59644  *  0b0001..Safe mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear and
59645  *          FSTS[FFPINx] is clear at the start of a half cycle or full cycle depending on the states of FSTS[FHALF] and
59646  *          FSTS[FFULL]. If neither FHLAF nor FFULL is set, then the fault condition cannot be cleared.
59647  */
59648 #define PWM_FCTRL_FSAFE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FSAFE_SHIFT)) & PWM_FCTRL_FSAFE_MASK)
59649 
59650 #define PWM_FCTRL_FAUTO_MASK                     (0xF00U)
59651 #define PWM_FCTRL_FAUTO_SHIFT                    (8U)
59652 /*! FAUTO - Automatic Fault Clearing
59653  *  0b0000..Manual fault clearing. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear
59654  *          at the start of a half cycle or full cycle depending on the states of FSTS[FHALF] and FSTS[FFULL]. If
59655  *          neither FFULL nor FHALF is set, then the fault condition cannot be cleared. This is further controlled
59656  *          by FCTRL[FSAFE].
59657  *  0b0001..Automatic fault clearing. PWM outputs disabled by this fault are enabled when FSTS[FFPINx] is clear at
59658  *          the start of a half cycle or full cycle depending on the states of FSTS[FHALF] and FSTS[FFULL] without
59659  *          regard to the state of FSTS[FFLAGx]. If neither FFULL nor FHALF is set, then the fault condition
59660  *          cannot be cleared.
59661  */
59662 #define PWM_FCTRL_FAUTO(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FAUTO_SHIFT)) & PWM_FCTRL_FAUTO_MASK)
59663 
59664 #define PWM_FCTRL_FLVL_MASK                      (0xF000U)
59665 #define PWM_FCTRL_FLVL_SHIFT                     (12U)
59666 /*! FLVL - Fault Level
59667  *  0b0000..A logic 0 on the fault input indicates a fault condition.
59668  *  0b0001..A logic 1 on the fault input indicates a fault condition.
59669  */
59670 #define PWM_FCTRL_FLVL(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FLVL_SHIFT)) & PWM_FCTRL_FLVL_MASK)
59671 /*! @} */
59672 
59673 /*! @name FSTS - Fault Status Register */
59674 /*! @{ */
59675 
59676 #define PWM_FSTS_FFLAG_MASK                      (0xFU)
59677 #define PWM_FSTS_FFLAG_SHIFT                     (0U)
59678 /*! FFLAG - Fault Flags
59679  *  0b0000..No fault on the FAULTx pin.
59680  *  0b0001..Fault on the FAULTx pin.
59681  */
59682 #define PWM_FSTS_FFLAG(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFLAG_SHIFT)) & PWM_FSTS_FFLAG_MASK)
59683 
59684 #define PWM_FSTS_FFULL_MASK                      (0xF0U)
59685 #define PWM_FSTS_FFULL_SHIFT                     (4U)
59686 /*! FFULL - Full Cycle
59687  *  0b0000..PWM outputs are not re-enabled at the start of a full cycle
59688  *  0b0001..PWM outputs are re-enabled at the start of a full cycle
59689  */
59690 #define PWM_FSTS_FFULL(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFULL_SHIFT)) & PWM_FSTS_FFULL_MASK)
59691 
59692 #define PWM_FSTS_FFPIN_MASK                      (0xF00U)
59693 #define PWM_FSTS_FFPIN_SHIFT                     (8U)
59694 /*! FFPIN - Filtered Fault Pins */
59695 #define PWM_FSTS_FFPIN(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFPIN_SHIFT)) & PWM_FSTS_FFPIN_MASK)
59696 
59697 #define PWM_FSTS_FHALF_MASK                      (0xF000U)
59698 #define PWM_FSTS_FHALF_SHIFT                     (12U)
59699 /*! FHALF - Half Cycle Fault Recovery
59700  *  0b0000..PWM outputs are not re-enabled at the start of a half cycle.
59701  *  0b0001..PWM outputs are re-enabled at the start of a half cycle (as defined by VAL0).
59702  */
59703 #define PWM_FSTS_FHALF(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FHALF_SHIFT)) & PWM_FSTS_FHALF_MASK)
59704 /*! @} */
59705 
59706 /*! @name FFILT - Fault Filter Register */
59707 /*! @{ */
59708 
59709 #define PWM_FFILT_FILT_PER_MASK                  (0xFFU)
59710 #define PWM_FFILT_FILT_PER_SHIFT                 (0U)
59711 /*! FILT_PER - Fault Filter Period */
59712 #define PWM_FFILT_FILT_PER(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_PER_SHIFT)) & PWM_FFILT_FILT_PER_MASK)
59713 
59714 #define PWM_FFILT_FILT_CNT_MASK                  (0x700U)
59715 #define PWM_FFILT_FILT_CNT_SHIFT                 (8U)
59716 /*! FILT_CNT - Fault Filter Count */
59717 #define PWM_FFILT_FILT_CNT(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_CNT_SHIFT)) & PWM_FFILT_FILT_CNT_MASK)
59718 
59719 #define PWM_FFILT_GSTR_MASK                      (0x8000U)
59720 #define PWM_FFILT_GSTR_SHIFT                     (15U)
59721 /*! GSTR - Fault Glitch Stretch Enable
59722  *  0b0..Fault input glitch stretching is disabled.
59723  *  0b1..Input fault signals are stretched to at least 2 IPBus clock cycles.
59724  */
59725 #define PWM_FFILT_GSTR(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_GSTR_SHIFT)) & PWM_FFILT_GSTR_MASK)
59726 /*! @} */
59727 
59728 /*! @name FTST - Fault Test Register */
59729 /*! @{ */
59730 
59731 #define PWM_FTST_FTEST_MASK                      (0x1U)
59732 #define PWM_FTST_FTEST_SHIFT                     (0U)
59733 /*! FTEST - Fault Test
59734  *  0b0..No fault
59735  *  0b1..Cause a simulated fault
59736  */
59737 #define PWM_FTST_FTEST(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_FTST_FTEST_SHIFT)) & PWM_FTST_FTEST_MASK)
59738 /*! @} */
59739 
59740 /*! @name FCTRL2 - Fault Control 2 Register */
59741 /*! @{ */
59742 
59743 #define PWM_FCTRL2_NOCOMB_MASK                   (0xFU)
59744 #define PWM_FCTRL2_NOCOMB_SHIFT                  (0U)
59745 /*! NOCOMB - No Combinational Path From Fault Input To PWM Output
59746  *  0b0000..There is a combinational link from the fault inputs to the PWM outputs. The fault inputs are combined
59747  *          with the filtered and latched fault signals to disable the PWM outputs.
59748  *  0b0001..The direct combinational path from the fault inputs to the PWM outputs is disabled and the filtered
59749  *          and latched fault signals are used to disable the PWM outputs.
59750  */
59751 #define PWM_FCTRL2_NOCOMB(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL2_NOCOMB_SHIFT)) & PWM_FCTRL2_NOCOMB_MASK)
59752 /*! @} */
59753 
59754 
59755 /*!
59756  * @}
59757  */ /* end of group PWM_Register_Masks */
59758 
59759 
59760 /* PWM - Peripheral instance base addresses */
59761 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
59762   /** Peripheral PWM0 base address */
59763   #define PWM0_BASE                                (0x500CE000u)
59764   /** Peripheral PWM0 base address */
59765   #define PWM0_BASE_NS                             (0x400CE000u)
59766   /** Peripheral PWM0 base pointer */
59767   #define PWM0                                     ((PWM_Type *)PWM0_BASE)
59768   /** Peripheral PWM0 base pointer */
59769   #define PWM0_NS                                  ((PWM_Type *)PWM0_BASE_NS)
59770   /** Array initializer of PWM peripheral base addresses */
59771   #define PWM_BASE_ADDRS                           { PWM0_BASE }
59772   /** Array initializer of PWM peripheral base pointers */
59773   #define PWM_BASE_PTRS                            { PWM0 }
59774   /** Array initializer of PWM peripheral base addresses */
59775   #define PWM_BASE_ADDRS_NS                        { PWM0_BASE_NS }
59776   /** Array initializer of PWM peripheral base pointers */
59777   #define PWM_BASE_PTRS_NS                         { PWM0_NS }
59778 #else
59779   /** Peripheral PWM0 base address */
59780   #define PWM0_BASE                                (0x400CE000u)
59781   /** Peripheral PWM0 base pointer */
59782   #define PWM0                                     ((PWM_Type *)PWM0_BASE)
59783   /** Array initializer of PWM peripheral base addresses */
59784   #define PWM_BASE_ADDRS                           { PWM0_BASE }
59785   /** Array initializer of PWM peripheral base pointers */
59786   #define PWM_BASE_PTRS                            { PWM0 }
59787 #endif
59788 /** Interrupt vectors for the PWM peripheral type */
59789 #define PWM_CMP_IRQS                             { { FLEXPWM0_SUBMODULE0_IRQn, FLEXPWM0_SUBMODULE1_IRQn, FLEXPWM0_SUBMODULE2_IRQn, FLEXPWM0_SUBMODULE3_IRQn } }
59790 #define PWM_RELOAD_IRQS                          { { FLEXPWM0_SUBMODULE0_IRQn, FLEXPWM0_SUBMODULE1_IRQn, FLEXPWM0_SUBMODULE2_IRQn, FLEXPWM0_SUBMODULE3_IRQn } }
59791 #define PWM_CAPTURE_IRQS                         { { FLEXPWM0_SUBMODULE0_IRQn, FLEXPWM0_SUBMODULE1_IRQn, FLEXPWM0_SUBMODULE2_IRQn, FLEXPWM0_SUBMODULE3_IRQn } }
59792 #define PWM_FAULT_IRQS                           { FLEXPWM0_FAULT_IRQn }
59793 #define PWM_RELOAD_ERROR_IRQS                    { FLEXPWM0_RELOAD_ERROR_IRQn }
59794 
59795 /*!
59796  * @}
59797  */ /* end of group PWM_Peripheral_Access_Layer */
59798 
59799 
59800 /* ----------------------------------------------------------------------------
59801    -- QDC Peripheral Access Layer
59802    ---------------------------------------------------------------------------- */
59803 
59804 /*!
59805  * @addtogroup QDC_Peripheral_Access_Layer QDC Peripheral Access Layer
59806  * @{
59807  */
59808 
59809 /** QDC - Register Layout Typedef */
59810 typedef struct {
59811   __IO uint16_t CTRL;                              /**< Control, offset: 0x0 */
59812   __IO uint16_t FILT;                              /**< Input Filter, offset: 0x2 */
59813   __IO uint16_t WTR;                               /**< Watchdog Timeout, offset: 0x4 */
59814   __IO uint16_t POSD;                              /**< Position Difference Counter, offset: 0x6 */
59815   __I  uint16_t POSDH;                             /**< Position Difference Hold, offset: 0x8 */
59816   __IO uint16_t REV;                               /**< Revolution Counter, offset: 0xA */
59817   __I  uint16_t REVH;                              /**< Revolution Hold, offset: 0xC */
59818   __IO uint16_t UPOS;                              /**< Upper Position Counter, offset: 0xE */
59819   __IO uint16_t LPOS;                              /**< Lower Position Counter, offset: 0x10 */
59820   __I  uint16_t UPOSH;                             /**< Upper Position Hold, offset: 0x12 */
59821   __I  uint16_t LPOSH;                             /**< Lower Position Hold, offset: 0x14 */
59822   __IO uint16_t UINIT;                             /**< Upper Initialization, offset: 0x16 */
59823   __IO uint16_t LINIT;                             /**< Lower Initialization, offset: 0x18 */
59824   __I  uint16_t IMR;                               /**< Input Monitor, offset: 0x1A */
59825   __IO uint16_t TST;                               /**< Test, offset: 0x1C */
59826   __IO uint16_t CTRL2;                             /**< Control 2, offset: 0x1E */
59827   __IO uint16_t UMOD;                              /**< Upper Modulus, offset: 0x20 */
59828   __IO uint16_t LMOD;                              /**< Lower Modulus, offset: 0x22 */
59829   __IO uint16_t UCOMP;                             /**< Upper Position Compare, offset: 0x24 */
59830   __IO uint16_t LCOMP;                             /**< Lower Position Compare, offset: 0x26 */
59831   __I  uint16_t LASTEDGE;                          /**< Last Edge Time, offset: 0x28 */
59832   __I  uint16_t LASTEDGEH;                         /**< Last Edge Time Hold, offset: 0x2A */
59833   __I  uint16_t POSDPER;                           /**< Position Difference Period Counter, offset: 0x2C */
59834   __I  uint16_t POSDPERBFR;                        /**< Position Difference Period Buffer, offset: 0x2E */
59835   __I  uint16_t POSDPERH;                          /**< Position Difference Period Hold, offset: 0x30 */
59836   __IO uint16_t CTRL3;                             /**< Control 3, offset: 0x32 */
59837 } QDC_Type;
59838 
59839 /* ----------------------------------------------------------------------------
59840    -- QDC Register Masks
59841    ---------------------------------------------------------------------------- */
59842 
59843 /*!
59844  * @addtogroup QDC_Register_Masks QDC Register Masks
59845  * @{
59846  */
59847 
59848 /*! @name CTRL - Control */
59849 /*! @{ */
59850 
59851 #define QDC_CTRL_CMPIE_MASK                      (0x1U)
59852 #define QDC_CTRL_CMPIE_SHIFT                     (0U)
59853 /*! CMPIE - Compare Interrupt Enable
59854  *  0b0..Disable
59855  *  0b1..Enable
59856  */
59857 #define QDC_CTRL_CMPIE(x)                        (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_CMPIE_SHIFT)) & QDC_CTRL_CMPIE_MASK)
59858 
59859 #define QDC_CTRL_CMPIRQ_MASK                     (0x2U)
59860 #define QDC_CTRL_CMPIRQ_SHIFT                    (1U)
59861 /*! CMPIRQ - Compare Interrupt Request
59862  *  0b0..No match has occurred
59863  *  0b1..COMP match has occurred
59864  */
59865 #define QDC_CTRL_CMPIRQ(x)                       (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_CMPIRQ_SHIFT)) & QDC_CTRL_CMPIRQ_MASK)
59866 
59867 #define QDC_CTRL_WDE_MASK                        (0x4U)
59868 #define QDC_CTRL_WDE_SHIFT                       (2U)
59869 /*! WDE - Watchdog Enable
59870  *  0b0..Disable
59871  *  0b1..Enable
59872  */
59873 #define QDC_CTRL_WDE(x)                          (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_WDE_SHIFT)) & QDC_CTRL_WDE_MASK)
59874 
59875 #define QDC_CTRL_DIE_MASK                        (0x8U)
59876 #define QDC_CTRL_DIE_SHIFT                       (3U)
59877 /*! DIE - Watchdog Timeout Interrupt Enable
59878  *  0b0..Disable
59879  *  0b1..Enable
59880  */
59881 #define QDC_CTRL_DIE(x)                          (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_DIE_SHIFT)) & QDC_CTRL_DIE_MASK)
59882 
59883 #define QDC_CTRL_DIRQ_MASK                       (0x10U)
59884 #define QDC_CTRL_DIRQ_SHIFT                      (4U)
59885 /*! DIRQ - Watchdog Timeout Interrupt Request
59886  *  0b0..Not occurred
59887  *  0b1..Occurred
59888  */
59889 #define QDC_CTRL_DIRQ(x)                         (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_DIRQ_SHIFT)) & QDC_CTRL_DIRQ_MASK)
59890 
59891 #define QDC_CTRL_XNE_MASK                        (0x20U)
59892 #define QDC_CTRL_XNE_SHIFT                       (5U)
59893 /*! XNE - Select Positive and Negative Edge of INDEX Pulse
59894  *  0b0..Use positive edge
59895  *  0b1..Use negative edge
59896  */
59897 #define QDC_CTRL_XNE(x)                          (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_XNE_SHIFT)) & QDC_CTRL_XNE_MASK)
59898 
59899 #define QDC_CTRL_XIP_MASK                        (0x40U)
59900 #define QDC_CTRL_XIP_SHIFT                       (6U)
59901 /*! XIP - INDEX Triggered Initialization of Position Counters UPOS and LPOS
59902  *  0b0..Does not initialize
59903  *  0b1..Initializes
59904  */
59905 #define QDC_CTRL_XIP(x)                          (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_XIP_SHIFT)) & QDC_CTRL_XIP_MASK)
59906 
59907 #define QDC_CTRL_XIE_MASK                        (0x80U)
59908 #define QDC_CTRL_XIE_SHIFT                       (7U)
59909 /*! XIE - INDEX Pulse Interrupt Enable
59910  *  0b0..Disable
59911  *  0b1..Enable
59912  */
59913 #define QDC_CTRL_XIE(x)                          (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_XIE_SHIFT)) & QDC_CTRL_XIE_MASK)
59914 
59915 #define QDC_CTRL_XIRQ_MASK                       (0x100U)
59916 #define QDC_CTRL_XIRQ_SHIFT                      (8U)
59917 /*! XIRQ - INDEX Pulse Interrupt Request
59918  *  0b0..Not occurred
59919  *  0b1..Occurred
59920  */
59921 #define QDC_CTRL_XIRQ(x)                         (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_XIRQ_SHIFT)) & QDC_CTRL_XIRQ_MASK)
59922 
59923 #define QDC_CTRL_PH1_MASK                        (0x200U)
59924 #define QDC_CTRL_PH1_SHIFT                       (9U)
59925 /*! PH1 - Enable Signal Phase Count Mode
59926  *  0b0..Uses the standard quadrature decoder, where PHASEA and PHASEB represent a two-phase quadrature signal.
59927  *  0b1..Bypasses the quadrature decoder. A positive transition of the PHASEA input generates a count signal.
59928  *       PHASEB input and CTRL[REV] controls the counter direction. If the value of CTRL[REV] and PHASEB are identical;
59929  *       then count is up. If the value of CTRL[REV] and PHASEB is different, then count is down.
59930  */
59931 #define QDC_CTRL_PH1(x)                          (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_PH1_SHIFT)) & QDC_CTRL_PH1_MASK)
59932 
59933 #define QDC_CTRL_REV_MASK                        (0x400U)
59934 #define QDC_CTRL_REV_SHIFT                       (10U)
59935 /*! REV - Enable Reverse Direction Counting
59936  *  0b0..Counts normally
59937  *  0b1..Counts in the reverse direction
59938  */
59939 #define QDC_CTRL_REV(x)                          (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_REV_SHIFT)) & QDC_CTRL_REV_MASK)
59940 
59941 #define QDC_CTRL_SWIP_MASK                       (0x800U)
59942 #define QDC_CTRL_SWIP_SHIFT                      (11U)
59943 /*! SWIP - Software-Triggered Initialization of Position Counters UPOS and LPOS
59944  *  0b0..No action
59945  *  0b1..Initialize position counter
59946  */
59947 #define QDC_CTRL_SWIP(x)                         (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_SWIP_SHIFT)) & QDC_CTRL_SWIP_MASK)
59948 
59949 #define QDC_CTRL_HNE_MASK                        (0x1000U)
59950 #define QDC_CTRL_HNE_SHIFT                       (12U)
59951 /*! HNE - Use Negative Edge of HOME Input
59952  *  0b0..Use positive-going edge-to-trigger initialization of position counters UPOS and LPOS
59953  *  0b1..Use negative-going edge-to-trigger initialization of position counters UPOS and LPOS
59954  */
59955 #define QDC_CTRL_HNE(x)                          (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_HNE_SHIFT)) & QDC_CTRL_HNE_MASK)
59956 
59957 #define QDC_CTRL_HIP_MASK                        (0x2000U)
59958 #define QDC_CTRL_HIP_SHIFT                       (13U)
59959 /*! HIP - Enable HOME to Initialize Position Counters UPOS and LPOS
59960  *  0b0..No action
59961  *  0b1..HOME signal initializes the position counter
59962  */
59963 #define QDC_CTRL_HIP(x)                          (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_HIP_SHIFT)) & QDC_CTRL_HIP_MASK)
59964 
59965 #define QDC_CTRL_HIE_MASK                        (0x4000U)
59966 #define QDC_CTRL_HIE_SHIFT                       (14U)
59967 /*! HIE - HOME Interrupt Enable
59968  *  0b0..Disable
59969  *  0b1..Enable
59970  */
59971 #define QDC_CTRL_HIE(x)                          (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_HIE_SHIFT)) & QDC_CTRL_HIE_MASK)
59972 
59973 #define QDC_CTRL_HIRQ_MASK                       (0x8000U)
59974 #define QDC_CTRL_HIRQ_SHIFT                      (15U)
59975 /*! HIRQ - HOME Signal Transition Interrupt Request
59976  *  0b0..Not occurred
59977  *  0b1..Occurred
59978  */
59979 #define QDC_CTRL_HIRQ(x)                         (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_HIRQ_SHIFT)) & QDC_CTRL_HIRQ_MASK)
59980 /*! @} */
59981 
59982 /*! @name FILT - Input Filter */
59983 /*! @{ */
59984 
59985 #define QDC_FILT_FILT_PER_MASK                   (0xFFU)
59986 #define QDC_FILT_FILT_PER_SHIFT                  (0U)
59987 /*! FILT_PER - Input Filter Sample Period */
59988 #define QDC_FILT_FILT_PER(x)                     (((uint16_t)(((uint16_t)(x)) << QDC_FILT_FILT_PER_SHIFT)) & QDC_FILT_FILT_PER_MASK)
59989 
59990 #define QDC_FILT_FILT_CNT_MASK                   (0x700U)
59991 #define QDC_FILT_FILT_CNT_SHIFT                  (8U)
59992 /*! FILT_CNT - Input Filter Sample Count */
59993 #define QDC_FILT_FILT_CNT(x)                     (((uint16_t)(((uint16_t)(x)) << QDC_FILT_FILT_CNT_SHIFT)) & QDC_FILT_FILT_CNT_MASK)
59994 
59995 #define QDC_FILT_FILT_PRSC_MASK                  (0xE000U)
59996 #define QDC_FILT_FILT_PRSC_SHIFT                 (13U)
59997 /*! FILT_PRSC - Prescaler Divide IPBus Clock to FILT Clock */
59998 #define QDC_FILT_FILT_PRSC(x)                    (((uint16_t)(((uint16_t)(x)) << QDC_FILT_FILT_PRSC_SHIFT)) & QDC_FILT_FILT_PRSC_MASK)
59999 /*! @} */
60000 
60001 /*! @name WTR - Watchdog Timeout */
60002 /*! @{ */
60003 
60004 #define QDC_WTR_WDOG_MASK                        (0xFFFFU)
60005 #define QDC_WTR_WDOG_SHIFT                       (0U)
60006 /*! WDOG - WDOG */
60007 #define QDC_WTR_WDOG(x)                          (((uint16_t)(((uint16_t)(x)) << QDC_WTR_WDOG_SHIFT)) & QDC_WTR_WDOG_MASK)
60008 /*! @} */
60009 
60010 /*! @name POSD - Position Difference Counter */
60011 /*! @{ */
60012 
60013 #define QDC_POSD_POSD_MASK                       (0xFFFFU)
60014 #define QDC_POSD_POSD_SHIFT                      (0U)
60015 /*! POSD - POSD */
60016 #define QDC_POSD_POSD(x)                         (((uint16_t)(((uint16_t)(x)) << QDC_POSD_POSD_SHIFT)) & QDC_POSD_POSD_MASK)
60017 /*! @} */
60018 
60019 /*! @name POSDH - Position Difference Hold */
60020 /*! @{ */
60021 
60022 #define QDC_POSDH_POSDH_MASK                     (0xFFFFU)
60023 #define QDC_POSDH_POSDH_SHIFT                    (0U)
60024 /*! POSDH - POSDH */
60025 #define QDC_POSDH_POSDH(x)                       (((uint16_t)(((uint16_t)(x)) << QDC_POSDH_POSDH_SHIFT)) & QDC_POSDH_POSDH_MASK)
60026 /*! @} */
60027 
60028 /*! @name REV - Revolution Counter */
60029 /*! @{ */
60030 
60031 #define QDC_REV_REV_MASK                         (0xFFFFU)
60032 #define QDC_REV_REV_SHIFT                        (0U)
60033 /*! REV - REV */
60034 #define QDC_REV_REV(x)                           (((uint16_t)(((uint16_t)(x)) << QDC_REV_REV_SHIFT)) & QDC_REV_REV_MASK)
60035 /*! @} */
60036 
60037 /*! @name REVH - Revolution Hold */
60038 /*! @{ */
60039 
60040 #define QDC_REVH_REVH_MASK                       (0xFFFFU)
60041 #define QDC_REVH_REVH_SHIFT                      (0U)
60042 /*! REVH - REVH */
60043 #define QDC_REVH_REVH(x)                         (((uint16_t)(((uint16_t)(x)) << QDC_REVH_REVH_SHIFT)) & QDC_REVH_REVH_MASK)
60044 /*! @} */
60045 
60046 /*! @name UPOS - Upper Position Counter */
60047 /*! @{ */
60048 
60049 #define QDC_UPOS_POS_MASK                        (0xFFFFU)
60050 #define QDC_UPOS_POS_SHIFT                       (0U)
60051 /*! POS - POS */
60052 #define QDC_UPOS_POS(x)                          (((uint16_t)(((uint16_t)(x)) << QDC_UPOS_POS_SHIFT)) & QDC_UPOS_POS_MASK)
60053 /*! @} */
60054 
60055 /*! @name LPOS - Lower Position Counter */
60056 /*! @{ */
60057 
60058 #define QDC_LPOS_POS_MASK                        (0xFFFFU)
60059 #define QDC_LPOS_POS_SHIFT                       (0U)
60060 /*! POS - POS */
60061 #define QDC_LPOS_POS(x)                          (((uint16_t)(((uint16_t)(x)) << QDC_LPOS_POS_SHIFT)) & QDC_LPOS_POS_MASK)
60062 /*! @} */
60063 
60064 /*! @name UPOSH - Upper Position Hold */
60065 /*! @{ */
60066 
60067 #define QDC_UPOSH_POSH_MASK                      (0xFFFFU)
60068 #define QDC_UPOSH_POSH_SHIFT                     (0U)
60069 /*! POSH - POSH */
60070 #define QDC_UPOSH_POSH(x)                        (((uint16_t)(((uint16_t)(x)) << QDC_UPOSH_POSH_SHIFT)) & QDC_UPOSH_POSH_MASK)
60071 /*! @} */
60072 
60073 /*! @name LPOSH - Lower Position Hold */
60074 /*! @{ */
60075 
60076 #define QDC_LPOSH_POSH_MASK                      (0xFFFFU)
60077 #define QDC_LPOSH_POSH_SHIFT                     (0U)
60078 /*! POSH - POSH */
60079 #define QDC_LPOSH_POSH(x)                        (((uint16_t)(((uint16_t)(x)) << QDC_LPOSH_POSH_SHIFT)) & QDC_LPOSH_POSH_MASK)
60080 /*! @} */
60081 
60082 /*! @name UINIT - Upper Initialization */
60083 /*! @{ */
60084 
60085 #define QDC_UINIT_INIT_MASK                      (0xFFFFU)
60086 #define QDC_UINIT_INIT_SHIFT                     (0U)
60087 /*! INIT - INIT */
60088 #define QDC_UINIT_INIT(x)                        (((uint16_t)(((uint16_t)(x)) << QDC_UINIT_INIT_SHIFT)) & QDC_UINIT_INIT_MASK)
60089 /*! @} */
60090 
60091 /*! @name LINIT - Lower Initialization */
60092 /*! @{ */
60093 
60094 #define QDC_LINIT_INIT_MASK                      (0xFFFFU)
60095 #define QDC_LINIT_INIT_SHIFT                     (0U)
60096 /*! INIT - INIT */
60097 #define QDC_LINIT_INIT(x)                        (((uint16_t)(((uint16_t)(x)) << QDC_LINIT_INIT_SHIFT)) & QDC_LINIT_INIT_MASK)
60098 /*! @} */
60099 
60100 /*! @name IMR - Input Monitor */
60101 /*! @{ */
60102 
60103 #define QDC_IMR_HOME_MASK                        (0x1U)
60104 #define QDC_IMR_HOME_SHIFT                       (0U)
60105 /*! HOME - HOME */
60106 #define QDC_IMR_HOME(x)                          (((uint16_t)(((uint16_t)(x)) << QDC_IMR_HOME_SHIFT)) & QDC_IMR_HOME_MASK)
60107 
60108 #define QDC_IMR_INDEX_MASK                       (0x2U)
60109 #define QDC_IMR_INDEX_SHIFT                      (1U)
60110 /*! INDEX - INDEX */
60111 #define QDC_IMR_INDEX(x)                         (((uint16_t)(((uint16_t)(x)) << QDC_IMR_INDEX_SHIFT)) & QDC_IMR_INDEX_MASK)
60112 
60113 #define QDC_IMR_PHB_MASK                         (0x4U)
60114 #define QDC_IMR_PHB_SHIFT                        (2U)
60115 /*! PHB - PHB */
60116 #define QDC_IMR_PHB(x)                           (((uint16_t)(((uint16_t)(x)) << QDC_IMR_PHB_SHIFT)) & QDC_IMR_PHB_MASK)
60117 
60118 #define QDC_IMR_PHA_MASK                         (0x8U)
60119 #define QDC_IMR_PHA_SHIFT                        (3U)
60120 /*! PHA - PHA */
60121 #define QDC_IMR_PHA(x)                           (((uint16_t)(((uint16_t)(x)) << QDC_IMR_PHA_SHIFT)) & QDC_IMR_PHA_MASK)
60122 
60123 #define QDC_IMR_FHOM_MASK                        (0x10U)
60124 #define QDC_IMR_FHOM_SHIFT                       (4U)
60125 /*! FHOM - FHOM */
60126 #define QDC_IMR_FHOM(x)                          (((uint16_t)(((uint16_t)(x)) << QDC_IMR_FHOM_SHIFT)) & QDC_IMR_FHOM_MASK)
60127 
60128 #define QDC_IMR_FIND_MASK                        (0x20U)
60129 #define QDC_IMR_FIND_SHIFT                       (5U)
60130 /*! FIND - FIND */
60131 #define QDC_IMR_FIND(x)                          (((uint16_t)(((uint16_t)(x)) << QDC_IMR_FIND_SHIFT)) & QDC_IMR_FIND_MASK)
60132 
60133 #define QDC_IMR_FPHB_MASK                        (0x40U)
60134 #define QDC_IMR_FPHB_SHIFT                       (6U)
60135 /*! FPHB - FPHB */
60136 #define QDC_IMR_FPHB(x)                          (((uint16_t)(((uint16_t)(x)) << QDC_IMR_FPHB_SHIFT)) & QDC_IMR_FPHB_MASK)
60137 
60138 #define QDC_IMR_FPHA_MASK                        (0x80U)
60139 #define QDC_IMR_FPHA_SHIFT                       (7U)
60140 /*! FPHA - FPHA */
60141 #define QDC_IMR_FPHA(x)                          (((uint16_t)(((uint16_t)(x)) << QDC_IMR_FPHA_SHIFT)) & QDC_IMR_FPHA_MASK)
60142 /*! @} */
60143 
60144 /*! @name TST - Test */
60145 /*! @{ */
60146 
60147 #define QDC_TST_TEST_COUNT_MASK                  (0xFFU)
60148 #define QDC_TST_TEST_COUNT_SHIFT                 (0U)
60149 /*! TEST_COUNT - TEST_COUNT */
60150 #define QDC_TST_TEST_COUNT(x)                    (((uint16_t)(((uint16_t)(x)) << QDC_TST_TEST_COUNT_SHIFT)) & QDC_TST_TEST_COUNT_MASK)
60151 
60152 #define QDC_TST_TEST_PERIOD_MASK                 (0x1F00U)
60153 #define QDC_TST_TEST_PERIOD_SHIFT                (8U)
60154 /*! TEST_PERIOD - TEST_PERIOD */
60155 #define QDC_TST_TEST_PERIOD(x)                   (((uint16_t)(((uint16_t)(x)) << QDC_TST_TEST_PERIOD_SHIFT)) & QDC_TST_TEST_PERIOD_MASK)
60156 
60157 #define QDC_TST_QDN_MASK                         (0x2000U)
60158 #define QDC_TST_QDN_SHIFT                        (13U)
60159 /*! QDN - Quadrature Decoder Negative Signal
60160  *  0b0..Positive quadrature decoder signal
60161  *  0b1..Negative quadrature decoder signal
60162  */
60163 #define QDC_TST_QDN(x)                           (((uint16_t)(((uint16_t)(x)) << QDC_TST_QDN_SHIFT)) & QDC_TST_QDN_MASK)
60164 
60165 #define QDC_TST_TCE_MASK                         (0x4000U)
60166 #define QDC_TST_TCE_SHIFT                        (14U)
60167 /*! TCE - Test Counter Enable
60168  *  0b0..Disable
60169  *  0b1..Enable
60170  */
60171 #define QDC_TST_TCE(x)                           (((uint16_t)(((uint16_t)(x)) << QDC_TST_TCE_SHIFT)) & QDC_TST_TCE_MASK)
60172 
60173 #define QDC_TST_TEN_MASK                         (0x8000U)
60174 #define QDC_TST_TEN_SHIFT                        (15U)
60175 /*! TEN - Test Mode Enable
60176  *  0b0..Disable
60177  *  0b1..Enable
60178  */
60179 #define QDC_TST_TEN(x)                           (((uint16_t)(((uint16_t)(x)) << QDC_TST_TEN_SHIFT)) & QDC_TST_TEN_MASK)
60180 /*! @} */
60181 
60182 /*! @name CTRL2 - Control 2 */
60183 /*! @{ */
60184 
60185 #define QDC_CTRL2_UPDHLD_MASK                    (0x1U)
60186 #define QDC_CTRL2_UPDHLD_SHIFT                   (0U)
60187 /*! UPDHLD - Update Hold Registers
60188  *  0b0..Disable
60189  *  0b1..Enable
60190  */
60191 #define QDC_CTRL2_UPDHLD(x)                      (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_UPDHLD_SHIFT)) & QDC_CTRL2_UPDHLD_MASK)
60192 
60193 #define QDC_CTRL2_UPDPOS_MASK                    (0x2U)
60194 #define QDC_CTRL2_UPDPOS_SHIFT                   (1U)
60195 /*! UPDPOS - Update Position Registers
60196  *  0b0..No action
60197  *  0b1..Clear
60198  */
60199 #define QDC_CTRL2_UPDPOS(x)                      (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_UPDPOS_SHIFT)) & QDC_CTRL2_UPDPOS_MASK)
60200 
60201 #define QDC_CTRL2_MOD_MASK                       (0x4U)
60202 #define QDC_CTRL2_MOD_SHIFT                      (2U)
60203 /*! MOD - Enable Modulo Counting
60204  *  0b0..Disable
60205  *  0b1..Enable
60206  */
60207 #define QDC_CTRL2_MOD(x)                         (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_MOD_SHIFT)) & QDC_CTRL2_MOD_MASK)
60208 
60209 #define QDC_CTRL2_DIR_MASK                       (0x8U)
60210 #define QDC_CTRL2_DIR_SHIFT                      (3U)
60211 /*! DIR - Count Direction Flag
60212  *  0b0..Down direction
60213  *  0b1..Up direction
60214  */
60215 #define QDC_CTRL2_DIR(x)                         (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_DIR_SHIFT)) & QDC_CTRL2_DIR_MASK)
60216 
60217 #define QDC_CTRL2_RUIE_MASK                      (0x10U)
60218 #define QDC_CTRL2_RUIE_SHIFT                     (4U)
60219 /*! RUIE - Roll-under Interrupt Enable
60220  *  0b0..Disable
60221  *  0b1..Enable
60222  */
60223 #define QDC_CTRL2_RUIE(x)                        (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_RUIE_SHIFT)) & QDC_CTRL2_RUIE_MASK)
60224 
60225 #define QDC_CTRL2_RUIRQ_MASK                     (0x20U)
60226 #define QDC_CTRL2_RUIRQ_SHIFT                    (5U)
60227 /*! RUIRQ - Roll-under Interrupt Request
60228  *  0b0..No roll-under has occurred
60229  *  0b1..Roll-under has occurred
60230  */
60231 #define QDC_CTRL2_RUIRQ(x)                       (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_RUIRQ_SHIFT)) & QDC_CTRL2_RUIRQ_MASK)
60232 
60233 #define QDC_CTRL2_ROIE_MASK                      (0x40U)
60234 #define QDC_CTRL2_ROIE_SHIFT                     (6U)
60235 /*! ROIE - Roll-over Interrupt Enable
60236  *  0b0..Disable
60237  *  0b1..Enable
60238  */
60239 #define QDC_CTRL2_ROIE(x)                        (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_ROIE_SHIFT)) & QDC_CTRL2_ROIE_MASK)
60240 
60241 #define QDC_CTRL2_ROIRQ_MASK                     (0x80U)
60242 #define QDC_CTRL2_ROIRQ_SHIFT                    (7U)
60243 /*! ROIRQ - Roll-over Interrupt Request
60244  *  0b0..Did not occur
60245  *  0b1..Occurred
60246  */
60247 #define QDC_CTRL2_ROIRQ(x)                       (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_ROIRQ_SHIFT)) & QDC_CTRL2_ROIRQ_MASK)
60248 
60249 #define QDC_CTRL2_REVMOD_MASK                    (0x100U)
60250 #define QDC_CTRL2_REVMOD_SHIFT                   (8U)
60251 /*! REVMOD - Revolution Counter Modulus Enable
60252  *  0b0..Use INDEX pulse
60253  *  0b1..Use modulus counting roll-over or roll-under
60254  */
60255 #define QDC_CTRL2_REVMOD(x)                      (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_REVMOD_SHIFT)) & QDC_CTRL2_REVMOD_MASK)
60256 
60257 #define QDC_CTRL2_OUTCTL_MASK                    (0x200U)
60258 #define QDC_CTRL2_OUTCTL_SHIFT                   (9U)
60259 /*! OUTCTL - Output Control
60260  *  0b0..POSMATCH pulses when a match occurs between the position counters (POS) and the corresponding compare value (COMP )
60261  *  0b1..POSMATCH pulses when the UPOS, LPOS, REV, or POSD registers are read
60262  */
60263 #define QDC_CTRL2_OUTCTL(x)                      (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_OUTCTL_SHIFT)) & QDC_CTRL2_OUTCTL_MASK)
60264 
60265 #define QDC_CTRL2_SABIE_MASK                     (0x400U)
60266 #define QDC_CTRL2_SABIE_SHIFT                    (10U)
60267 /*! SABIE - Simultaneous PHASEA and PHASEB Change Interrupt Enable
60268  *  0b0..Disable
60269  *  0b1..Enable
60270  */
60271 #define QDC_CTRL2_SABIE(x)                       (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_SABIE_SHIFT)) & QDC_CTRL2_SABIE_MASK)
60272 
60273 #define QDC_CTRL2_SABIRQ_MASK                    (0x800U)
60274 #define QDC_CTRL2_SABIRQ_SHIFT                   (11U)
60275 /*! SABIRQ - Simultaneous PHASEA and PHASEB Change Interrupt Request
60276  *  0b0..No simultaneous change has occurred
60277  *  0b1..A simultaneous change has occurred
60278  */
60279 #define QDC_CTRL2_SABIRQ(x)                      (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_SABIRQ_SHIFT)) & QDC_CTRL2_SABIRQ_MASK)
60280 
60281 #define QDC_CTRL2_INITPOS_MASK                   (0x1000U)
60282 #define QDC_CTRL2_INITPOS_SHIFT                  (12U)
60283 /*! INITPOS - Initialize Position Registers
60284  *  0b0..Don't initialize position counter
60285  *  0b1..Initialize position counter
60286  */
60287 #define QDC_CTRL2_INITPOS(x)                     (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_INITPOS_SHIFT)) & QDC_CTRL2_INITPOS_MASK)
60288 /*! @} */
60289 
60290 /*! @name UMOD - Upper Modulus */
60291 /*! @{ */
60292 
60293 #define QDC_UMOD_MOD_MASK                        (0xFFFFU)
60294 #define QDC_UMOD_MOD_SHIFT                       (0U)
60295 /*! MOD - MOD */
60296 #define QDC_UMOD_MOD(x)                          (((uint16_t)(((uint16_t)(x)) << QDC_UMOD_MOD_SHIFT)) & QDC_UMOD_MOD_MASK)
60297 /*! @} */
60298 
60299 /*! @name LMOD - Lower Modulus */
60300 /*! @{ */
60301 
60302 #define QDC_LMOD_MOD_MASK                        (0xFFFFU)
60303 #define QDC_LMOD_MOD_SHIFT                       (0U)
60304 /*! MOD - MOD */
60305 #define QDC_LMOD_MOD(x)                          (((uint16_t)(((uint16_t)(x)) << QDC_LMOD_MOD_SHIFT)) & QDC_LMOD_MOD_MASK)
60306 /*! @} */
60307 
60308 /*! @name UCOMP - Upper Position Compare */
60309 /*! @{ */
60310 
60311 #define QDC_UCOMP_COMP_MASK                      (0xFFFFU)
60312 #define QDC_UCOMP_COMP_SHIFT                     (0U)
60313 /*! COMP - COMP */
60314 #define QDC_UCOMP_COMP(x)                        (((uint16_t)(((uint16_t)(x)) << QDC_UCOMP_COMP_SHIFT)) & QDC_UCOMP_COMP_MASK)
60315 /*! @} */
60316 
60317 /*! @name LCOMP - Lower Position Compare */
60318 /*! @{ */
60319 
60320 #define QDC_LCOMP_COMP_MASK                      (0xFFFFU)
60321 #define QDC_LCOMP_COMP_SHIFT                     (0U)
60322 /*! COMP - COMP */
60323 #define QDC_LCOMP_COMP(x)                        (((uint16_t)(((uint16_t)(x)) << QDC_LCOMP_COMP_SHIFT)) & QDC_LCOMP_COMP_MASK)
60324 /*! @} */
60325 
60326 /*! @name LASTEDGE - Last Edge Time */
60327 /*! @{ */
60328 
60329 #define QDC_LASTEDGE_LASTEDGE_MASK               (0xFFFFU)
60330 #define QDC_LASTEDGE_LASTEDGE_SHIFT              (0U)
60331 /*! LASTEDGE - Last Edge Time Counter */
60332 #define QDC_LASTEDGE_LASTEDGE(x)                 (((uint16_t)(((uint16_t)(x)) << QDC_LASTEDGE_LASTEDGE_SHIFT)) & QDC_LASTEDGE_LASTEDGE_MASK)
60333 /*! @} */
60334 
60335 /*! @name LASTEDGEH - Last Edge Time Hold */
60336 /*! @{ */
60337 
60338 #define QDC_LASTEDGEH_LASTEDGEH_MASK             (0xFFFFU)
60339 #define QDC_LASTEDGEH_LASTEDGEH_SHIFT            (0U)
60340 /*! LASTEDGEH - Last Edge Time Hold */
60341 #define QDC_LASTEDGEH_LASTEDGEH(x)               (((uint16_t)(((uint16_t)(x)) << QDC_LASTEDGEH_LASTEDGEH_SHIFT)) & QDC_LASTEDGEH_LASTEDGEH_MASK)
60342 /*! @} */
60343 
60344 /*! @name POSDPER - Position Difference Period Counter */
60345 /*! @{ */
60346 
60347 #define QDC_POSDPER_POSDPER_MASK                 (0xFFFFU)
60348 #define QDC_POSDPER_POSDPER_SHIFT                (0U)
60349 /*! POSDPER - Position difference period */
60350 #define QDC_POSDPER_POSDPER(x)                   (((uint16_t)(((uint16_t)(x)) << QDC_POSDPER_POSDPER_SHIFT)) & QDC_POSDPER_POSDPER_MASK)
60351 /*! @} */
60352 
60353 /*! @name POSDPERBFR - Position Difference Period Buffer */
60354 /*! @{ */
60355 
60356 #define QDC_POSDPERBFR_POSDPERBFR_MASK           (0xFFFFU)
60357 #define QDC_POSDPERBFR_POSDPERBFR_SHIFT          (0U)
60358 /*! POSDPERBFR - Position difference period buffer */
60359 #define QDC_POSDPERBFR_POSDPERBFR(x)             (((uint16_t)(((uint16_t)(x)) << QDC_POSDPERBFR_POSDPERBFR_SHIFT)) & QDC_POSDPERBFR_POSDPERBFR_MASK)
60360 /*! @} */
60361 
60362 /*! @name POSDPERH - Position Difference Period Hold */
60363 /*! @{ */
60364 
60365 #define QDC_POSDPERH_POSDPERH_MASK               (0xFFFFU)
60366 #define QDC_POSDPERH_POSDPERH_SHIFT              (0U)
60367 /*! POSDPERH - Position difference period hold */
60368 #define QDC_POSDPERH_POSDPERH(x)                 (((uint16_t)(((uint16_t)(x)) << QDC_POSDPERH_POSDPERH_SHIFT)) & QDC_POSDPERH_POSDPERH_MASK)
60369 /*! @} */
60370 
60371 /*! @name CTRL3 - Control 3 */
60372 /*! @{ */
60373 
60374 #define QDC_CTRL3_PMEN_MASK                      (0x1U)
60375 #define QDC_CTRL3_PMEN_SHIFT                     (0U)
60376 /*! PMEN - Period Measurement Function Enable
60377  *  0b0..Not used
60378  *  0b1..Used
60379  */
60380 #define QDC_CTRL3_PMEN(x)                        (((uint16_t)(((uint16_t)(x)) << QDC_CTRL3_PMEN_SHIFT)) & QDC_CTRL3_PMEN_MASK)
60381 
60382 #define QDC_CTRL3_PRSC_MASK                      (0xF0U)
60383 #define QDC_CTRL3_PRSC_SHIFT                     (4U)
60384 /*! PRSC - Prescaler */
60385 #define QDC_CTRL3_PRSC(x)                        (((uint16_t)(((uint16_t)(x)) << QDC_CTRL3_PRSC_SHIFT)) & QDC_CTRL3_PRSC_MASK)
60386 /*! @} */
60387 
60388 
60389 /*!
60390  * @}
60391  */ /* end of group QDC_Register_Masks */
60392 
60393 
60394 /* QDC - Peripheral instance base addresses */
60395 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
60396   /** Peripheral QDC0 base address */
60397   #define QDC0_BASE                                (0x500CF000u)
60398   /** Peripheral QDC0 base address */
60399   #define QDC0_BASE_NS                             (0x400CF000u)
60400   /** Peripheral QDC0 base pointer */
60401   #define QDC0                                     ((QDC_Type *)QDC0_BASE)
60402   /** Peripheral QDC0 base pointer */
60403   #define QDC0_NS                                  ((QDC_Type *)QDC0_BASE_NS)
60404   /** Peripheral QDC1 base address */
60405   #define QDC1_BASE                                (0x500D1000u)
60406   /** Peripheral QDC1 base address */
60407   #define QDC1_BASE_NS                             (0x400D1000u)
60408   /** Peripheral QDC1 base pointer */
60409   #define QDC1                                     ((QDC_Type *)QDC1_BASE)
60410   /** Peripheral QDC1 base pointer */
60411   #define QDC1_NS                                  ((QDC_Type *)QDC1_BASE_NS)
60412   /** Array initializer of QDC peripheral base addresses */
60413   #define QDC_BASE_ADDRS                           { QDC0_BASE, QDC1_BASE }
60414   /** Array initializer of QDC peripheral base pointers */
60415   #define QDC_BASE_PTRS                            { QDC0, QDC1 }
60416   /** Array initializer of QDC peripheral base addresses */
60417   #define QDC_BASE_ADDRS_NS                        { QDC0_BASE_NS, QDC1_BASE_NS }
60418   /** Array initializer of QDC peripheral base pointers */
60419   #define QDC_BASE_PTRS_NS                         { QDC0_NS, QDC1_NS }
60420 #else
60421   /** Peripheral QDC0 base address */
60422   #define QDC0_BASE                                (0x400CF000u)
60423   /** Peripheral QDC0 base pointer */
60424   #define QDC0                                     ((QDC_Type *)QDC0_BASE)
60425   /** Peripheral QDC1 base address */
60426   #define QDC1_BASE                                (0x400D1000u)
60427   /** Peripheral QDC1 base pointer */
60428   #define QDC1                                     ((QDC_Type *)QDC1_BASE)
60429   /** Array initializer of QDC peripheral base addresses */
60430   #define QDC_BASE_ADDRS                           { QDC0_BASE, QDC1_BASE }
60431   /** Array initializer of QDC peripheral base pointers */
60432   #define QDC_BASE_PTRS                            { QDC0, QDC1 }
60433 #endif
60434 /** Interrupt vectors for the QDC peripheral type */
60435 #define QDC_COMPARE_IRQS                         { QDC0_COMPARE_IRQn, QDC1_COMPARE_IRQn }
60436 #define QDC_HOME_IRQS                            { QDC0_HOME_IRQn, QDC1_HOME_IRQn }
60437 #define QDC_WDOG_IRQS                            { QDC0_WDG_SAB_IRQn, QDC1_WDG_SAB_IRQn }
60438 #define QDC_INDEX_IRQS                           { QDC0_IDX_IRQn, QDC1_IDX_IRQn }
60439 
60440 /*!
60441  * @}
60442  */ /* end of group QDC_Peripheral_Access_Layer */
60443 
60444 
60445 /* ----------------------------------------------------------------------------
60446    -- RTC Peripheral Access Layer
60447    ---------------------------------------------------------------------------- */
60448 
60449 /*!
60450  * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
60451  * @{
60452  */
60453 
60454 /** RTC - Register Layout Typedef */
60455 typedef struct {
60456   __IO uint16_t YEARMON;                           /**< Year and Month Counters, offset: 0x0 */
60457   __IO uint16_t DAYS;                              /**< Days and Day-of-Week Counters, offset: 0x2 */
60458   __IO uint16_t HOURMIN;                           /**< Hours and Minutes Counters, offset: 0x4 */
60459   __IO uint16_t SECONDS;                           /**< Seconds Counters, offset: 0x6 */
60460   __IO uint16_t ALM_YEARMON;                       /**< Year and Months Alarm, offset: 0x8 */
60461   __IO uint16_t ALM_DAYS;                          /**< Days Alarm, offset: 0xA */
60462   __IO uint16_t ALM_HOURMIN;                       /**< Hours and Minutes Alarm, offset: 0xC */
60463   __IO uint16_t ALM_SECONDS;                       /**< Seconds Alarm, offset: 0xE */
60464   __IO uint16_t CTRL;                              /**< Control, offset: 0x10 */
60465   __IO uint16_t STATUS;                            /**< Status, offset: 0x12 */
60466   __IO uint16_t ISR;                               /**< Interrupt Status, offset: 0x14 */
60467   __IO uint16_t IER;                               /**< Interrupt Enable, offset: 0x16 */
60468        uint8_t RESERVED_0[4];
60469   __I  uint16_t RTC_TEST2;                         /**< Sub Second Counter, offset: 0x1C */
60470        uint8_t RESERVED_1[4];
60471   __IO uint16_t DST_HOUR;                          /**< Daylight Saving Hour, offset: 0x22 */
60472   __IO uint16_t DST_MONTH;                         /**< Daylight Saving Month, offset: 0x24 */
60473   __IO uint16_t DST_DAY;                           /**< Daylight Saving Day, offset: 0x26 */
60474   __IO uint16_t COMPEN;                            /**< Compensation, offset: 0x28 */
60475        uint8_t RESERVED_2[2006];
60476   __IO uint32_t SUBSECOND_CTRL;                    /**< Subsecond Control, offset: 0x800 */
60477   __I  uint32_t SUBSECOND_CNT;                     /**< Subsecond Counter, offset: 0x804 */
60478        uint8_t RESERVED_3[1016];
60479   __IO uint32_t WAKE_TIMER_CTRL;                   /**< Wake Timer Control, offset: 0xC00 */
60480        uint8_t RESERVED_4[8];
60481   __IO uint32_t WAKE_TIMER_CNT;                    /**< Wake Timer Counter, offset: 0xC0C */
60482 } RTC_Type;
60483 
60484 /* ----------------------------------------------------------------------------
60485    -- RTC Register Masks
60486    ---------------------------------------------------------------------------- */
60487 
60488 /*!
60489  * @addtogroup RTC_Register_Masks RTC Register Masks
60490  * @{
60491  */
60492 
60493 /*! @name YEARMON - Year and Month Counters */
60494 /*! @{ */
60495 
60496 #define RTC_YEARMON_MON_CNT_MASK                 (0xFU)
60497 #define RTC_YEARMON_MON_CNT_SHIFT                (0U)
60498 /*! MON_CNT - Month Counter
60499  *  0b0000, 0b1101, 0b1110, 0b1111..Illegal Value
60500  *  0b0001..January
60501  *  0b0010..February
60502  *  0b0011..March
60503  *  0b0100..April
60504  *  0b0101..May
60505  *  0b0110..June
60506  *  0b0111..July
60507  *  0b1000..August
60508  *  0b1001..September
60509  *  0b1010..October
60510  *  0b1011..November
60511  *  0b1100..December
60512  */
60513 #define RTC_YEARMON_MON_CNT(x)                   (((uint16_t)(((uint16_t)(x)) << RTC_YEARMON_MON_CNT_SHIFT)) & RTC_YEARMON_MON_CNT_MASK)
60514 
60515 #define RTC_YEARMON_YROFST_MASK                  (0xFF00U)
60516 #define RTC_YEARMON_YROFST_SHIFT                 (8U)
60517 /*! YROFST - Year Offset Count Value */
60518 #define RTC_YEARMON_YROFST(x)                    (((uint16_t)(((uint16_t)(x)) << RTC_YEARMON_YROFST_SHIFT)) & RTC_YEARMON_YROFST_MASK)
60519 /*! @} */
60520 
60521 /*! @name DAYS - Days and Day-of-Week Counters */
60522 /*! @{ */
60523 
60524 #define RTC_DAYS_DAY_CNT_MASK                    (0x1FU)
60525 #define RTC_DAYS_DAY_CNT_SHIFT                   (0U)
60526 /*! DAY_CNT - Days Counter Value */
60527 #define RTC_DAYS_DAY_CNT(x)                      (((uint16_t)(((uint16_t)(x)) << RTC_DAYS_DAY_CNT_SHIFT)) & RTC_DAYS_DAY_CNT_MASK)
60528 
60529 #define RTC_DAYS_DOW_MASK                        (0x700U)
60530 #define RTC_DAYS_DOW_SHIFT                       (8U)
60531 /*! DOW - Day of Week Counter Value
60532  *  0b000..Sunday
60533  *  0b001..Monday
60534  *  0b010..Tuesday
60535  *  0b011..Wednesday
60536  *  0b100..Thursday
60537  *  0b101..Friday
60538  *  0b110..Saturday
60539  *  0b111..
60540  */
60541 #define RTC_DAYS_DOW(x)                          (((uint16_t)(((uint16_t)(x)) << RTC_DAYS_DOW_SHIFT)) & RTC_DAYS_DOW_MASK)
60542 /*! @} */
60543 
60544 /*! @name HOURMIN - Hours and Minutes Counters */
60545 /*! @{ */
60546 
60547 #define RTC_HOURMIN_MIN_CNT_MASK                 (0x3FU)
60548 #define RTC_HOURMIN_MIN_CNT_SHIFT                (0U)
60549 /*! MIN_CNT - Minutes Counter Value */
60550 #define RTC_HOURMIN_MIN_CNT(x)                   (((uint16_t)(((uint16_t)(x)) << RTC_HOURMIN_MIN_CNT_SHIFT)) & RTC_HOURMIN_MIN_CNT_MASK)
60551 
60552 #define RTC_HOURMIN_HOUR_CNT_MASK                (0x1F00U)
60553 #define RTC_HOURMIN_HOUR_CNT_SHIFT               (8U)
60554 /*! HOUR_CNT - Hours Counter Value */
60555 #define RTC_HOURMIN_HOUR_CNT(x)                  (((uint16_t)(((uint16_t)(x)) << RTC_HOURMIN_HOUR_CNT_SHIFT)) & RTC_HOURMIN_HOUR_CNT_MASK)
60556 /*! @} */
60557 
60558 /*! @name SECONDS - Seconds Counters */
60559 /*! @{ */
60560 
60561 #define RTC_SECONDS_SEC_CNT_MASK                 (0x3FU)
60562 #define RTC_SECONDS_SEC_CNT_SHIFT                (0U)
60563 /*! SEC_CNT - Seconds Counter Value */
60564 #define RTC_SECONDS_SEC_CNT(x)                   (((uint16_t)(((uint16_t)(x)) << RTC_SECONDS_SEC_CNT_SHIFT)) & RTC_SECONDS_SEC_CNT_MASK)
60565 /*! @} */
60566 
60567 /*! @name ALM_YEARMON - Year and Months Alarm */
60568 /*! @{ */
60569 
60570 #define RTC_ALM_YEARMON_ALM_MON_MASK             (0xFU)
60571 #define RTC_ALM_YEARMON_ALM_MON_SHIFT            (0U)
60572 /*! ALM_MON - Months Value for Alarm */
60573 #define RTC_ALM_YEARMON_ALM_MON(x)               (((uint16_t)(((uint16_t)(x)) << RTC_ALM_YEARMON_ALM_MON_SHIFT)) & RTC_ALM_YEARMON_ALM_MON_MASK)
60574 
60575 #define RTC_ALM_YEARMON_ALM_YEAR_MASK            (0xFF00U)
60576 #define RTC_ALM_YEARMON_ALM_YEAR_SHIFT           (8U)
60577 /*! ALM_YEAR - Year Value for Alarm */
60578 #define RTC_ALM_YEARMON_ALM_YEAR(x)              (((uint16_t)(((uint16_t)(x)) << RTC_ALM_YEARMON_ALM_YEAR_SHIFT)) & RTC_ALM_YEARMON_ALM_YEAR_MASK)
60579 /*! @} */
60580 
60581 /*! @name ALM_DAYS - Days Alarm */
60582 /*! @{ */
60583 
60584 #define RTC_ALM_DAYS_ALM_DAY_MASK                (0x1FU)
60585 #define RTC_ALM_DAYS_ALM_DAY_SHIFT               (0U)
60586 /*! ALM_DAY - Days Value for Alarm */
60587 #define RTC_ALM_DAYS_ALM_DAY(x)                  (((uint16_t)(((uint16_t)(x)) << RTC_ALM_DAYS_ALM_DAY_SHIFT)) & RTC_ALM_DAYS_ALM_DAY_MASK)
60588 /*! @} */
60589 
60590 /*! @name ALM_HOURMIN - Hours and Minutes Alarm */
60591 /*! @{ */
60592 
60593 #define RTC_ALM_HOURMIN_ALM_MIN_MASK             (0x3FU)
60594 #define RTC_ALM_HOURMIN_ALM_MIN_SHIFT            (0U)
60595 /*! ALM_MIN - Minutes Value for Alarm */
60596 #define RTC_ALM_HOURMIN_ALM_MIN(x)               (((uint16_t)(((uint16_t)(x)) << RTC_ALM_HOURMIN_ALM_MIN_SHIFT)) & RTC_ALM_HOURMIN_ALM_MIN_MASK)
60597 
60598 #define RTC_ALM_HOURMIN_ALM_HOUR_MASK            (0x1F00U)
60599 #define RTC_ALM_HOURMIN_ALM_HOUR_SHIFT           (8U)
60600 /*! ALM_HOUR - Hours Value for Alarm */
60601 #define RTC_ALM_HOURMIN_ALM_HOUR(x)              (((uint16_t)(((uint16_t)(x)) << RTC_ALM_HOURMIN_ALM_HOUR_SHIFT)) & RTC_ALM_HOURMIN_ALM_HOUR_MASK)
60602 /*! @} */
60603 
60604 /*! @name ALM_SECONDS - Seconds Alarm */
60605 /*! @{ */
60606 
60607 #define RTC_ALM_SECONDS_ALM_SEC_MASK             (0x3FU)
60608 #define RTC_ALM_SECONDS_ALM_SEC_SHIFT            (0U)
60609 /*! ALM_SEC - Seconds Alarm Value */
60610 #define RTC_ALM_SECONDS_ALM_SEC(x)               (((uint16_t)(((uint16_t)(x)) << RTC_ALM_SECONDS_ALM_SEC_SHIFT)) & RTC_ALM_SECONDS_ALM_SEC_MASK)
60611 
60612 #define RTC_ALM_SECONDS_DEC_SEC_MASK             (0x100U)
60613 #define RTC_ALM_SECONDS_DEC_SEC_SHIFT            (8U)
60614 /*! DEC_SEC - Decrement Seconds Counter by 1. */
60615 #define RTC_ALM_SECONDS_DEC_SEC(x)               (((uint16_t)(((uint16_t)(x)) << RTC_ALM_SECONDS_DEC_SEC_SHIFT)) & RTC_ALM_SECONDS_DEC_SEC_MASK)
60616 
60617 #define RTC_ALM_SECONDS_INC_SEC_MASK             (0x200U)
60618 #define RTC_ALM_SECONDS_INC_SEC_SHIFT            (9U)
60619 /*! INC_SEC - Increment Seconds Counter by 1. */
60620 #define RTC_ALM_SECONDS_INC_SEC(x)               (((uint16_t)(((uint16_t)(x)) << RTC_ALM_SECONDS_INC_SEC_SHIFT)) & RTC_ALM_SECONDS_INC_SEC_MASK)
60621 /*! @} */
60622 
60623 /*! @name CTRL - Control */
60624 /*! @{ */
60625 
60626 #define RTC_CTRL_FINEEN_MASK                     (0x1U)
60627 #define RTC_CTRL_FINEEN_SHIFT                    (0U)
60628 /*! FINEEN - Fine Compensation Enable
60629  *  0b1..Fine compensation is enabled.
60630  *  0b0..Fine compensation is disabled
60631  */
60632 #define RTC_CTRL_FINEEN(x)                       (((uint16_t)(((uint16_t)(x)) << RTC_CTRL_FINEEN_SHIFT)) & RTC_CTRL_FINEEN_MASK)
60633 
60634 #define RTC_CTRL_COMP_EN_MASK                    (0x2U)
60635 #define RTC_CTRL_COMP_EN_SHIFT                   (1U)
60636 /*! COMP_EN - Compensation Enable
60637  *  0b0..Coarse compensation is disabled.
60638  *  0b1..Coarse compensation is enabled.
60639  */
60640 #define RTC_CTRL_COMP_EN(x)                      (((uint16_t)(((uint16_t)(x)) << RTC_CTRL_COMP_EN_SHIFT)) & RTC_CTRL_COMP_EN_MASK)
60641 
60642 #define RTC_CTRL_ALM_MATCH_MASK                  (0xCU)
60643 #define RTC_CTRL_ALM_MATCH_SHIFT                 (2U)
60644 /*! ALM_MATCH - Alarm Match
60645  *  0b00..Only seconds, minutes, and hours matched.
60646  *  0b01..Only seconds, minutes, hours, and days matched.
60647  *  0b10..Only seconds, minutes, hours, days, and months matched.
60648  *  0b11..Only seconds, minutes, hours, days, months, and year (offset) matched.
60649  */
60650 #define RTC_CTRL_ALM_MATCH(x)                    (((uint16_t)(((uint16_t)(x)) << RTC_CTRL_ALM_MATCH_SHIFT)) & RTC_CTRL_ALM_MATCH_MASK)
60651 
60652 #define RTC_CTRL_DST_EN_MASK                     (0x40U)
60653 #define RTC_CTRL_DST_EN_SHIFT                    (6U)
60654 /*! DST_EN - Daylight Saving Enable
60655  *  0b0..Disabled
60656  *  0b1..Enabled
60657  */
60658 #define RTC_CTRL_DST_EN(x)                       (((uint16_t)(((uint16_t)(x)) << RTC_CTRL_DST_EN_SHIFT)) & RTC_CTRL_DST_EN_MASK)
60659 
60660 #define RTC_CTRL_SWR_MASK                        (0x100U)
60661 #define RTC_CTRL_SWR_SHIFT                       (8U)
60662 /*! SWR - Software Reset
60663  *  0b0..Software Reset cleared
60664  *  0b1..Software Reset asserted
60665  */
60666 #define RTC_CTRL_SWR(x)                          (((uint16_t)(((uint16_t)(x)) << RTC_CTRL_SWR_SHIFT)) & RTC_CTRL_SWR_MASK)
60667 
60668 #define RTC_CTRL_CLK_SEL_MASK                    (0x200U)
60669 #define RTC_CTRL_CLK_SEL_SHIFT                   (9U)
60670 /*! CLK_SEL - RTC Clock Select
60671  *  0b0..16.384 kHz clock is selected
60672  *  0b1..32.768 kHz clock is selected
60673  */
60674 #define RTC_CTRL_CLK_SEL(x)                      (((uint16_t)(((uint16_t)(x)) << RTC_CTRL_CLK_SEL_SHIFT)) & RTC_CTRL_CLK_SEL_MASK)
60675 
60676 #define RTC_CTRL_CLKO_DIS_MASK                   (0x400U)
60677 #define RTC_CTRL_CLKO_DIS_SHIFT                  (10U)
60678 /*! CLKO_DIS - Clock Output Disable
60679  *  0b0..The selected clock is output to other peripherals.
60680  *  0b1..The selected clock is not output to other peripherals.
60681  */
60682 #define RTC_CTRL_CLKO_DIS(x)                     (((uint16_t)(((uint16_t)(x)) << RTC_CTRL_CLKO_DIS_SHIFT)) & RTC_CTRL_CLKO_DIS_MASK)
60683 
60684 #define RTC_CTRL_CLKOUT_MASK                     (0x6000U)
60685 #define RTC_CTRL_CLKOUT_SHIFT                    (13U)
60686 /*! CLKOUT - RTC Clock Output Selection
60687  *  0b00..No output clock
60688  *  0b01..Fine 1 Hz clock with both precise edges
60689  *  0b10..32.768 or 16.384 kHz clock
60690  *  0b11..Coarse 1 Hz clock with both precise edges
60691  */
60692 #define RTC_CTRL_CLKOUT(x)                       (((uint16_t)(((uint16_t)(x)) << RTC_CTRL_CLKOUT_SHIFT)) & RTC_CTRL_CLKOUT_MASK)
60693 /*! @} */
60694 
60695 /*! @name STATUS - Status */
60696 /*! @{ */
60697 
60698 #define RTC_STATUS_INVAL_BIT_MASK                (0x1U)
60699 #define RTC_STATUS_INVAL_BIT_SHIFT               (0U)
60700 /*! INVAL_BIT - Invalidate CPU Read/Write Access
60701  *  0b0..Time and date counters can be read or written. Time and date is valid.
60702  *  0b1..Time and date counter values are changing or time and date is invalid and cannot be read or written.
60703  */
60704 #define RTC_STATUS_INVAL_BIT(x)                  (((uint16_t)(((uint16_t)(x)) << RTC_STATUS_INVAL_BIT_SHIFT)) & RTC_STATUS_INVAL_BIT_MASK)
60705 
60706 #define RTC_STATUS_WRITE_PROT_EN_MASK            (0x2U)
60707 #define RTC_STATUS_WRITE_PROT_EN_SHIFT           (1U)
60708 /*! WRITE_PROT_EN - Write Protect Enable Status
60709  *  0b0..Registers are unlocked and can be accessed.
60710  *  0b1..Registers are locked and in read-only mode.
60711  */
60712 #define RTC_STATUS_WRITE_PROT_EN(x)              (((uint16_t)(((uint16_t)(x)) << RTC_STATUS_WRITE_PROT_EN_SHIFT)) & RTC_STATUS_WRITE_PROT_EN_MASK)
60713 
60714 #define RTC_STATUS_CMP_INT_MASK                  (0x20U)
60715 #define RTC_STATUS_CMP_INT_SHIFT                 (5U)
60716 /*! CMP_INT - Compensation Interval */
60717 #define RTC_STATUS_CMP_INT(x)                    (((uint16_t)(((uint16_t)(x)) << RTC_STATUS_CMP_INT_SHIFT)) & RTC_STATUS_CMP_INT_MASK)
60718 
60719 #define RTC_STATUS_WE_MASK                       (0xC0U)
60720 #define RTC_STATUS_WE_SHIFT                      (6U)
60721 /*! WE - Write Enable
60722  *  0b10..Enable Write Protection - Registers are locked.
60723  */
60724 #define RTC_STATUS_WE(x)                         (((uint16_t)(((uint16_t)(x)) << RTC_STATUS_WE_SHIFT)) & RTC_STATUS_WE_MASK)
60725 
60726 #define RTC_STATUS_BUS_ERR_MASK                  (0x100U)
60727 #define RTC_STATUS_BUS_ERR_SHIFT                 (8U)
60728 /*! BUS_ERR - Bus Error
60729  *  0b0..Read and write accesses are normal.
60730  *  0b1..Read or write accesses occurred when STATUS[INVAL_BIT] was asserted.
60731  */
60732 #define RTC_STATUS_BUS_ERR(x)                    (((uint16_t)(((uint16_t)(x)) << RTC_STATUS_BUS_ERR_SHIFT)) & RTC_STATUS_BUS_ERR_MASK)
60733 
60734 #define RTC_STATUS_CMP_DONE_MASK                 (0x800U)
60735 #define RTC_STATUS_CMP_DONE_SHIFT                (11U)
60736 /*! CMP_DONE - Compensation Done
60737  *  0b0..Compensation busy or not enabled
60738  *  0b1..Compensation completed
60739  */
60740 #define RTC_STATUS_CMP_DONE(x)                   (((uint16_t)(((uint16_t)(x)) << RTC_STATUS_CMP_DONE_SHIFT)) & RTC_STATUS_CMP_DONE_MASK)
60741 /*! @} */
60742 
60743 /*! @name ISR - Interrupt Status */
60744 /*! @{ */
60745 
60746 #define RTC_ISR_ALM_IS_MASK                      (0x4U)
60747 #define RTC_ISR_ALM_IS_SHIFT                     (2U)
60748 /*! ALM_IS - Alarm Interrupt Status
60749  *  0b0..Interrupt is de-asserted.
60750  *  0b1..Interrupt is asserted.
60751  */
60752 #define RTC_ISR_ALM_IS(x)                        (((uint16_t)(((uint16_t)(x)) << RTC_ISR_ALM_IS_SHIFT)) & RTC_ISR_ALM_IS_MASK)
60753 
60754 #define RTC_ISR_DAY_IS_MASK                      (0x8U)
60755 #define RTC_ISR_DAY_IS_SHIFT                     (3U)
60756 /*! DAY_IS - Days Interrupt Status
60757  *  0b0..Interrupt is de-asserted.
60758  *  0b1..Interrupt is asserted.
60759  */
60760 #define RTC_ISR_DAY_IS(x)                        (((uint16_t)(((uint16_t)(x)) << RTC_ISR_DAY_IS_SHIFT)) & RTC_ISR_DAY_IS_MASK)
60761 
60762 #define RTC_ISR_HOUR_IS_MASK                     (0x10U)
60763 #define RTC_ISR_HOUR_IS_SHIFT                    (4U)
60764 /*! HOUR_IS - Hours Interrupt Status
60765  *  0b0..Interrupt is de-asserted.
60766  *  0b1..Interrupt is asserted.
60767  */
60768 #define RTC_ISR_HOUR_IS(x)                       (((uint16_t)(((uint16_t)(x)) << RTC_ISR_HOUR_IS_SHIFT)) & RTC_ISR_HOUR_IS_MASK)
60769 
60770 #define RTC_ISR_MIN_IS_MASK                      (0x20U)
60771 #define RTC_ISR_MIN_IS_SHIFT                     (5U)
60772 /*! MIN_IS - Minutes Interrupt Status
60773  *  0b0..Interrupt is de-asserted.
60774  *  0b1..Interrupt is asserted.
60775  */
60776 #define RTC_ISR_MIN_IS(x)                        (((uint16_t)(((uint16_t)(x)) << RTC_ISR_MIN_IS_SHIFT)) & RTC_ISR_MIN_IS_MASK)
60777 
60778 #define RTC_ISR_IS_1HZ_MASK                      (0x40U)
60779 #define RTC_ISR_IS_1HZ_SHIFT                     (6U)
60780 /*! IS_1HZ - 1 Hz Interval Interrupt Status
60781  *  0b0..Interrupt is de-asserted.
60782  *  0b1..Interrupt is asserted.
60783  */
60784 #define RTC_ISR_IS_1HZ(x)                        (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_1HZ_SHIFT)) & RTC_ISR_IS_1HZ_MASK)
60785 
60786 #define RTC_ISR_IS_2HZ_MASK                      (0x80U)
60787 #define RTC_ISR_IS_2HZ_SHIFT                     (7U)
60788 /*! IS_2HZ - 2 Hz Interval Interrupt Status
60789  *  0b0..Interrupt is de-asserted.
60790  *  0b1..Interrupt is asserted.
60791  */
60792 #define RTC_ISR_IS_2HZ(x)                        (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_2HZ_SHIFT)) & RTC_ISR_IS_2HZ_MASK)
60793 
60794 #define RTC_ISR_IS_4HZ_MASK                      (0x100U)
60795 #define RTC_ISR_IS_4HZ_SHIFT                     (8U)
60796 /*! IS_4HZ - 4 Hz Interval Interrupt Status
60797  *  0b0..Interrupt is de-asserted.
60798  *  0b1..Interrupt is asserted.
60799  */
60800 #define RTC_ISR_IS_4HZ(x)                        (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_4HZ_SHIFT)) & RTC_ISR_IS_4HZ_MASK)
60801 
60802 #define RTC_ISR_IS_8HZ_MASK                      (0x200U)
60803 #define RTC_ISR_IS_8HZ_SHIFT                     (9U)
60804 /*! IS_8HZ - 8 Hz Interval Interrupt Status
60805  *  0b0..Interrupt is de-asserted.
60806  *  0b1..Interrupt is asserted.
60807  */
60808 #define RTC_ISR_IS_8HZ(x)                        (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_8HZ_SHIFT)) & RTC_ISR_IS_8HZ_MASK)
60809 
60810 #define RTC_ISR_IS_16HZ_MASK                     (0x400U)
60811 #define RTC_ISR_IS_16HZ_SHIFT                    (10U)
60812 /*! IS_16HZ - 16 Hz Interval Interrupt Status
60813  *  0b0..Interrupt is de-asserted.
60814  *  0b1..Interrupt is asserted.
60815  */
60816 #define RTC_ISR_IS_16HZ(x)                       (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_16HZ_SHIFT)) & RTC_ISR_IS_16HZ_MASK)
60817 
60818 #define RTC_ISR_IS_32HZ_MASK                     (0x800U)
60819 #define RTC_ISR_IS_32HZ_SHIFT                    (11U)
60820 /*! IS_32HZ - 32 Hz Interval Interrupt Status
60821  *  0b0..Interrupt is de-asserted.
60822  *  0b1..Interrupt is asserted.
60823  */
60824 #define RTC_ISR_IS_32HZ(x)                       (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_32HZ_SHIFT)) & RTC_ISR_IS_32HZ_MASK)
60825 
60826 #define RTC_ISR_IS_64HZ_MASK                     (0x1000U)
60827 #define RTC_ISR_IS_64HZ_SHIFT                    (12U)
60828 /*! IS_64HZ - 64 Hz Interval Interrupt Status
60829  *  0b0..Interrupt is de-asserted.
60830  *  0b1..Interrupt is asserted.
60831  */
60832 #define RTC_ISR_IS_64HZ(x)                       (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_64HZ_SHIFT)) & RTC_ISR_IS_64HZ_MASK)
60833 
60834 #define RTC_ISR_IS_128HZ_MASK                    (0x2000U)
60835 #define RTC_ISR_IS_128HZ_SHIFT                   (13U)
60836 /*! IS_128HZ - 128 Hz Interval Interrupt Status
60837  *  0b0..Interrupt is de-asserted.
60838  *  0b1..Interrupt is asserted.
60839  */
60840 #define RTC_ISR_IS_128HZ(x)                      (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_128HZ_SHIFT)) & RTC_ISR_IS_128HZ_MASK)
60841 
60842 #define RTC_ISR_IS_256HZ_MASK                    (0x4000U)
60843 #define RTC_ISR_IS_256HZ_SHIFT                   (14U)
60844 /*! IS_256HZ - 256 Hz Interval Interrupt Status
60845  *  0b0..Interrupt is de-asserted.
60846  *  0b1..Interrupt is asserted.
60847  */
60848 #define RTC_ISR_IS_256HZ(x)                      (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_256HZ_SHIFT)) & RTC_ISR_IS_256HZ_MASK)
60849 
60850 #define RTC_ISR_IS_512HZ_MASK                    (0x8000U)
60851 #define RTC_ISR_IS_512HZ_SHIFT                   (15U)
60852 /*! IS_512HZ - 512 Hz Interval Interrupt Status
60853  *  0b0..Interrupt is de-asserted.
60854  *  0b1..Interrupt is asserted.
60855  */
60856 #define RTC_ISR_IS_512HZ(x)                      (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_512HZ_SHIFT)) & RTC_ISR_IS_512HZ_MASK)
60857 /*! @} */
60858 
60859 /*! @name IER - Interrupt Enable */
60860 /*! @{ */
60861 
60862 #define RTC_IER_ALM_IE_MASK                      (0x4U)
60863 #define RTC_IER_ALM_IE_SHIFT                     (2U)
60864 /*! ALM_IE - Alarm Interrupt Enable
60865  *  0b0..Interrupt is disabled.
60866  *  0b1..Interrupt is enabled.
60867  */
60868 #define RTC_IER_ALM_IE(x)                        (((uint16_t)(((uint16_t)(x)) << RTC_IER_ALM_IE_SHIFT)) & RTC_IER_ALM_IE_MASK)
60869 
60870 #define RTC_IER_DAY_IE_MASK                      (0x8U)
60871 #define RTC_IER_DAY_IE_SHIFT                     (3U)
60872 /*! DAY_IE - Days Interrupt Enable
60873  *  0b0..Interrupt is disabled.
60874  *  0b1..Interrupt is enabled.
60875  */
60876 #define RTC_IER_DAY_IE(x)                        (((uint16_t)(((uint16_t)(x)) << RTC_IER_DAY_IE_SHIFT)) & RTC_IER_DAY_IE_MASK)
60877 
60878 #define RTC_IER_HOUR_IE_MASK                     (0x10U)
60879 #define RTC_IER_HOUR_IE_SHIFT                    (4U)
60880 /*! HOUR_IE - Hours Interrupt Enable
60881  *  0b0..Interrupt is disabled.
60882  *  0b1..Interrupt is enabled.
60883  */
60884 #define RTC_IER_HOUR_IE(x)                       (((uint16_t)(((uint16_t)(x)) << RTC_IER_HOUR_IE_SHIFT)) & RTC_IER_HOUR_IE_MASK)
60885 
60886 #define RTC_IER_MIN_IE_MASK                      (0x20U)
60887 #define RTC_IER_MIN_IE_SHIFT                     (5U)
60888 /*! MIN_IE - Minutes Interrupt Enable
60889  *  0b0..Interrupt is disabled.
60890  *  0b1..Interrupt is enabled.
60891  */
60892 #define RTC_IER_MIN_IE(x)                        (((uint16_t)(((uint16_t)(x)) << RTC_IER_MIN_IE_SHIFT)) & RTC_IER_MIN_IE_MASK)
60893 
60894 #define RTC_IER_IE_1HZ_MASK                      (0x40U)
60895 #define RTC_IER_IE_1HZ_SHIFT                     (6U)
60896 /*! IE_1HZ - 1 Hz Interval Interrupt Enable
60897  *  0b0..Interrupt is disabled.
60898  *  0b1..Interrupt is enabled.
60899  */
60900 #define RTC_IER_IE_1HZ(x)                        (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_1HZ_SHIFT)) & RTC_IER_IE_1HZ_MASK)
60901 
60902 #define RTC_IER_IE_2HZ_MASK                      (0x80U)
60903 #define RTC_IER_IE_2HZ_SHIFT                     (7U)
60904 /*! IE_2HZ - 2 Hz Interval Interrupt Enable
60905  *  0b0..Interrupt is disabled.
60906  *  0b1..Interrupt is enabled.
60907  */
60908 #define RTC_IER_IE_2HZ(x)                        (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_2HZ_SHIFT)) & RTC_IER_IE_2HZ_MASK)
60909 
60910 #define RTC_IER_IE_4HZ_MASK                      (0x100U)
60911 #define RTC_IER_IE_4HZ_SHIFT                     (8U)
60912 /*! IE_4HZ - 4 Hz Interval Interrupt Enable
60913  *  0b0..Interrupt is disabled.
60914  *  0b1..Interrupt is enabled.
60915  */
60916 #define RTC_IER_IE_4HZ(x)                        (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_4HZ_SHIFT)) & RTC_IER_IE_4HZ_MASK)
60917 
60918 #define RTC_IER_IE_8HZ_MASK                      (0x200U)
60919 #define RTC_IER_IE_8HZ_SHIFT                     (9U)
60920 /*! IE_8HZ - 8 Hz Interval Interrupt Enable
60921  *  0b0..Interrupt is disabled.
60922  *  0b1..Interrupt is enabled.
60923  */
60924 #define RTC_IER_IE_8HZ(x)                        (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_8HZ_SHIFT)) & RTC_IER_IE_8HZ_MASK)
60925 
60926 #define RTC_IER_IE_16HZ_MASK                     (0x400U)
60927 #define RTC_IER_IE_16HZ_SHIFT                    (10U)
60928 /*! IE_16HZ - 16 Hz Interval Interrupt Enable
60929  *  0b0..Interrupt is disabled.
60930  *  0b1..Interrupt is enabled.
60931  */
60932 #define RTC_IER_IE_16HZ(x)                       (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_16HZ_SHIFT)) & RTC_IER_IE_16HZ_MASK)
60933 
60934 #define RTC_IER_IE_32HZ_MASK                     (0x800U)
60935 #define RTC_IER_IE_32HZ_SHIFT                    (11U)
60936 /*! IE_32HZ - 32 Hz Interval Interrupt Enable
60937  *  0b0..Interrupt is disabled.
60938  *  0b1..Interrupt is enabled.
60939  */
60940 #define RTC_IER_IE_32HZ(x)                       (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_32HZ_SHIFT)) & RTC_IER_IE_32HZ_MASK)
60941 
60942 #define RTC_IER_IE_64HZ_MASK                     (0x1000U)
60943 #define RTC_IER_IE_64HZ_SHIFT                    (12U)
60944 /*! IE_64HZ - 64 Hz Interval Interrupt Enable
60945  *  0b0..Interrupt is disabled.
60946  *  0b1..Interrupt is enabled.
60947  */
60948 #define RTC_IER_IE_64HZ(x)                       (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_64HZ_SHIFT)) & RTC_IER_IE_64HZ_MASK)
60949 
60950 #define RTC_IER_IE_128HZ_MASK                    (0x2000U)
60951 #define RTC_IER_IE_128HZ_SHIFT                   (13U)
60952 /*! IE_128HZ - 128 Hz Interval Interrupt Enable
60953  *  0b0..Interrupt is disabled.
60954  *  0b1..Interrupt is enabled.
60955  */
60956 #define RTC_IER_IE_128HZ(x)                      (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_128HZ_SHIFT)) & RTC_IER_IE_128HZ_MASK)
60957 
60958 #define RTC_IER_IE_256HZ_MASK                    (0x4000U)
60959 #define RTC_IER_IE_256HZ_SHIFT                   (14U)
60960 /*! IE_256HZ - 256 Hz Interval Interrupt Enable
60961  *  0b0..Interrupt is disabled.
60962  *  0b1..Interrupt is enabled.
60963  */
60964 #define RTC_IER_IE_256HZ(x)                      (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_256HZ_SHIFT)) & RTC_IER_IE_256HZ_MASK)
60965 
60966 #define RTC_IER_IE_512HZ_MASK                    (0x8000U)
60967 #define RTC_IER_IE_512HZ_SHIFT                   (15U)
60968 /*! IE_512HZ - 512 Hz Interval Interrupt Enable
60969  *  0b0..Interrupt is disabled.
60970  *  0b1..Interrupt is enabled.
60971  */
60972 #define RTC_IER_IE_512HZ(x)                      (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_512HZ_SHIFT)) & RTC_IER_IE_512HZ_MASK)
60973 /*! @} */
60974 
60975 /*! @name RTC_TEST2 - Sub Second Counter */
60976 /*! @{ */
60977 
60978 #define RTC_RTC_TEST2_SUB_SECOND_COUNT_MASK      (0xFFFFU)
60979 #define RTC_RTC_TEST2_SUB_SECOND_COUNT_SHIFT     (0U)
60980 /*! SUB_SECOND_COUNT - Sub Second Counter Value */
60981 #define RTC_RTC_TEST2_SUB_SECOND_COUNT(x)        (((uint16_t)(((uint16_t)(x)) << RTC_RTC_TEST2_SUB_SECOND_COUNT_SHIFT)) & RTC_RTC_TEST2_SUB_SECOND_COUNT_MASK)
60982 /*! @} */
60983 
60984 /*! @name DST_HOUR - Daylight Saving Hour */
60985 /*! @{ */
60986 
60987 #define RTC_DST_HOUR_DST_END_HOUR_MASK           (0x1FU)
60988 #define RTC_DST_HOUR_DST_END_HOUR_SHIFT          (0U)
60989 /*! DST_END_HOUR - Daylight Saving Time (DST) Hours End Value */
60990 #define RTC_DST_HOUR_DST_END_HOUR(x)             (((uint16_t)(((uint16_t)(x)) << RTC_DST_HOUR_DST_END_HOUR_SHIFT)) & RTC_DST_HOUR_DST_END_HOUR_MASK)
60991 
60992 #define RTC_DST_HOUR_DST_START_HOUR_MASK         (0x1F00U)
60993 #define RTC_DST_HOUR_DST_START_HOUR_SHIFT        (8U)
60994 /*! DST_START_HOUR - Daylight Saving Time (DST) Hours Start Value */
60995 #define RTC_DST_HOUR_DST_START_HOUR(x)           (((uint16_t)(((uint16_t)(x)) << RTC_DST_HOUR_DST_START_HOUR_SHIFT)) & RTC_DST_HOUR_DST_START_HOUR_MASK)
60996 /*! @} */
60997 
60998 /*! @name DST_MONTH - Daylight Saving Month */
60999 /*! @{ */
61000 
61001 #define RTC_DST_MONTH_DST_END_MONTH_MASK         (0xFU)
61002 #define RTC_DST_MONTH_DST_END_MONTH_SHIFT        (0U)
61003 /*! DST_END_MONTH - Daylight Saving Time (DST) Month End Value */
61004 #define RTC_DST_MONTH_DST_END_MONTH(x)           (((uint16_t)(((uint16_t)(x)) << RTC_DST_MONTH_DST_END_MONTH_SHIFT)) & RTC_DST_MONTH_DST_END_MONTH_MASK)
61005 
61006 #define RTC_DST_MONTH_DST_START_MONTH_MASK       (0xF00U)
61007 #define RTC_DST_MONTH_DST_START_MONTH_SHIFT      (8U)
61008 /*! DST_START_MONTH - Daylight Saving Time (DST) Month Start Value */
61009 #define RTC_DST_MONTH_DST_START_MONTH(x)         (((uint16_t)(((uint16_t)(x)) << RTC_DST_MONTH_DST_START_MONTH_SHIFT)) & RTC_DST_MONTH_DST_START_MONTH_MASK)
61010 /*! @} */
61011 
61012 /*! @name DST_DAY - Daylight Saving Day */
61013 /*! @{ */
61014 
61015 #define RTC_DST_DAY_DST_END_DAY_MASK             (0x1FU)
61016 #define RTC_DST_DAY_DST_END_DAY_SHIFT            (0U)
61017 /*! DST_END_DAY - Daylight Saving Time (DST) Day End Value */
61018 #define RTC_DST_DAY_DST_END_DAY(x)               (((uint16_t)(((uint16_t)(x)) << RTC_DST_DAY_DST_END_DAY_SHIFT)) & RTC_DST_DAY_DST_END_DAY_MASK)
61019 
61020 #define RTC_DST_DAY_DST_START_DAY_MASK           (0x1F00U)
61021 #define RTC_DST_DAY_DST_START_DAY_SHIFT          (8U)
61022 /*! DST_START_DAY - Daylight Saving Time (DST) Day Start Value */
61023 #define RTC_DST_DAY_DST_START_DAY(x)             (((uint16_t)(((uint16_t)(x)) << RTC_DST_DAY_DST_START_DAY_SHIFT)) & RTC_DST_DAY_DST_START_DAY_MASK)
61024 /*! @} */
61025 
61026 /*! @name COMPEN - Compensation */
61027 /*! @{ */
61028 
61029 #define RTC_COMPEN_COMPEN_VAL_MASK               (0xFFFFU)
61030 #define RTC_COMPEN_COMPEN_VAL_SHIFT              (0U)
61031 /*! COMPEN_VAL - Compensation Value */
61032 #define RTC_COMPEN_COMPEN_VAL(x)                 (((uint16_t)(((uint16_t)(x)) << RTC_COMPEN_COMPEN_VAL_SHIFT)) & RTC_COMPEN_COMPEN_VAL_MASK)
61033 /*! @} */
61034 
61035 /*! @name SUBSECOND_CTRL - Subsecond Control */
61036 /*! @{ */
61037 
61038 #define RTC_SUBSECOND_CTRL_SUB_SECOND_CNT_EN_MASK (0x1U)
61039 #define RTC_SUBSECOND_CTRL_SUB_SECOND_CNT_EN_SHIFT (0U)
61040 /*! SUB_SECOND_CNT_EN - Subsecond Counter Enable
61041  *  0b0..Disable
61042  *  0b1..Enable
61043  */
61044 #define RTC_SUBSECOND_CTRL_SUB_SECOND_CNT_EN(x)  (((uint32_t)(((uint32_t)(x)) << RTC_SUBSECOND_CTRL_SUB_SECOND_CNT_EN_SHIFT)) & RTC_SUBSECOND_CTRL_SUB_SECOND_CNT_EN_MASK)
61045 /*! @} */
61046 
61047 /*! @name SUBSECOND_CNT - Subsecond Counter */
61048 /*! @{ */
61049 
61050 #define RTC_SUBSECOND_CNT_SUBSECOND_CNT_MASK     (0xFFFFU)
61051 #define RTC_SUBSECOND_CNT_SUBSECOND_CNT_SHIFT    (0U)
61052 /*! SUBSECOND_CNT - Current Subsecond Counter Value */
61053 #define RTC_SUBSECOND_CNT_SUBSECOND_CNT(x)       (((uint32_t)(((uint32_t)(x)) << RTC_SUBSECOND_CNT_SUBSECOND_CNT_SHIFT)) & RTC_SUBSECOND_CNT_SUBSECOND_CNT_MASK)
61054 /*! @} */
61055 
61056 /*! @name WAKE_TIMER_CTRL - Wake Timer Control */
61057 /*! @{ */
61058 
61059 #define RTC_WAKE_TIMER_CTRL_WAKE_FLAG_MASK       (0x2U)
61060 #define RTC_WAKE_TIMER_CTRL_WAKE_FLAG_SHIFT      (1U)
61061 /*! WAKE_FLAG - Wake Timer Status Flag
61062  *  0b0..Not timed out
61063  *  0b1..Timed out
61064  */
61065 #define RTC_WAKE_TIMER_CTRL_WAKE_FLAG(x)         (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_TIMER_CTRL_WAKE_FLAG_SHIFT)) & RTC_WAKE_TIMER_CTRL_WAKE_FLAG_MASK)
61066 
61067 #define RTC_WAKE_TIMER_CTRL_CLR_WAKE_TIMER_MASK  (0x4U)
61068 #define RTC_WAKE_TIMER_CTRL_CLR_WAKE_TIMER_SHIFT (2U)
61069 /*! CLR_WAKE_TIMER - Clear Wake Timer
61070  *  0b0..No effect
61071  *  0b1..Clear the wake timer counter
61072  */
61073 #define RTC_WAKE_TIMER_CTRL_CLR_WAKE_TIMER(x)    (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_TIMER_CTRL_CLR_WAKE_TIMER_SHIFT)) & RTC_WAKE_TIMER_CTRL_CLR_WAKE_TIMER_MASK)
61074 
61075 #define RTC_WAKE_TIMER_CTRL_OSC_DIV_ENA_MASK     (0x10U)
61076 #define RTC_WAKE_TIMER_CTRL_OSC_DIV_ENA_SHIFT    (4U)
61077 /*! OSC_DIV_ENA - OSC Divide Enable
61078  *  0b0..Disable
61079  *  0b1..Enable
61080  */
61081 #define RTC_WAKE_TIMER_CTRL_OSC_DIV_ENA(x)       (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_TIMER_CTRL_OSC_DIV_ENA_SHIFT)) & RTC_WAKE_TIMER_CTRL_OSC_DIV_ENA_MASK)
61082 
61083 #define RTC_WAKE_TIMER_CTRL_INTR_EN_MASK         (0x20U)
61084 #define RTC_WAKE_TIMER_CTRL_INTR_EN_SHIFT        (5U)
61085 /*! INTR_EN - Enable Interrupt
61086  *  0b0..Disable
61087  *  0b1..Enable
61088  */
61089 #define RTC_WAKE_TIMER_CTRL_INTR_EN(x)           (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_TIMER_CTRL_INTR_EN_SHIFT)) & RTC_WAKE_TIMER_CTRL_INTR_EN_MASK)
61090 /*! @} */
61091 
61092 /*! @name WAKE_TIMER_CNT - Wake Timer Counter */
61093 /*! @{ */
61094 
61095 #define RTC_WAKE_TIMER_CNT_WAKE_CNT_MASK         (0xFFFFFFFFU)
61096 #define RTC_WAKE_TIMER_CNT_WAKE_CNT_SHIFT        (0U)
61097 /*! WAKE_CNT - Wake Counter */
61098 #define RTC_WAKE_TIMER_CNT_WAKE_CNT(x)           (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_TIMER_CNT_WAKE_CNT_SHIFT)) & RTC_WAKE_TIMER_CNT_WAKE_CNT_MASK)
61099 /*! @} */
61100 
61101 
61102 /*!
61103  * @}
61104  */ /* end of group RTC_Register_Masks */
61105 
61106 
61107 /* RTC - Peripheral instance base addresses */
61108 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
61109   /** Peripheral RTC0 base address */
61110   #define RTC0_BASE                                (0x5004C000u)
61111   /** Peripheral RTC0 base address */
61112   #define RTC0_BASE_NS                             (0x4004C000u)
61113   /** Peripheral RTC0 base pointer */
61114   #define RTC0                                     ((RTC_Type *)RTC0_BASE)
61115   /** Peripheral RTC0 base pointer */
61116   #define RTC0_NS                                  ((RTC_Type *)RTC0_BASE_NS)
61117   /** Array initializer of RTC peripheral base addresses */
61118   #define RTC_BASE_ADDRS                           { RTC0_BASE }
61119   /** Array initializer of RTC peripheral base pointers */
61120   #define RTC_BASE_PTRS                            { RTC0 }
61121   /** Array initializer of RTC peripheral base addresses */
61122   #define RTC_BASE_ADDRS_NS                        { RTC0_BASE_NS }
61123   /** Array initializer of RTC peripheral base pointers */
61124   #define RTC_BASE_PTRS_NS                         { RTC0_NS }
61125 #else
61126   /** Peripheral RTC0 base address */
61127   #define RTC0_BASE                                (0x4004C000u)
61128   /** Peripheral RTC0 base pointer */
61129   #define RTC0                                     ((RTC_Type *)RTC0_BASE)
61130   /** Array initializer of RTC peripheral base addresses */
61131   #define RTC_BASE_ADDRS                           { RTC0_BASE }
61132   /** Array initializer of RTC peripheral base pointers */
61133   #define RTC_BASE_PTRS                            { RTC0 }
61134 #endif
61135 /** Interrupt vectors for the RTC peripheral type */
61136 #define RTC_IRQS                                 { RTC_IRQn }
61137 /* Backward compatibility for RTC */
61138 #define RTC    RTC0
61139 
61140 
61141 /*!
61142  * @}
61143  */ /* end of group RTC_Peripheral_Access_Layer */
61144 
61145 
61146 /* ----------------------------------------------------------------------------
61147    -- S50 Peripheral Access Layer
61148    ---------------------------------------------------------------------------- */
61149 
61150 /*!
61151  * @addtogroup S50_Peripheral_Access_Layer S50 Peripheral Access Layer
61152  * @{
61153  */
61154 
61155 /** S50 - Register Layout Typedef */
61156 typedef struct {
61157   __I  uint32_t ELS_STATUS;                        /**< Status Register, offset: 0x0 */
61158   __IO uint32_t ELS_CTRL;                          /**< Control Register, offset: 0x4 */
61159   __IO uint32_t ELS_CMDCFG0;                       /**< Command Configuration, offset: 0x8 */
61160   __IO uint32_t ELS_CFG;                           /**< Configuration Register, offset: 0xC */
61161   __IO uint32_t ELS_KIDX0;                         /**< Keystore Index 0, offset: 0x10 */
61162   __IO uint32_t ELS_KIDX1;                         /**< Keystore Index 1, offset: 0x14 */
61163   __IO uint32_t ELS_KPROPIN;                       /**< Key Properties Request, offset: 0x18 */
61164        uint8_t RESERVED_0[4];
61165   __IO uint32_t ELS_DMA_SRC0;                      /**< DMA Source 0, offset: 0x20 */
61166   __IO uint32_t ELS_DMA_SRC0_LEN;                  /**< DMA Source 0 Length, offset: 0x24 */
61167   __IO uint32_t ELS_DMA_SRC1;                      /**< DMA Source 1, offset: 0x28 */
61168        uint8_t RESERVED_1[4];
61169   __IO uint32_t ELS_DMA_SRC2;                      /**< DMA Source 2, offset: 0x30 */
61170   __IO uint32_t ELS_DMA_SRC2_LEN;                  /**< DMA Source 2 Length, offset: 0x34 */
61171   __IO uint32_t ELS_DMA_RES0;                      /**< DMA Result 0, offset: 0x38 */
61172   __IO uint32_t ELS_DMA_RES0_LEN;                  /**< DMA Result 0 Length, offset: 0x3C */
61173   __IO uint32_t ELS_INT_ENABLE;                    /**< Interrupt Enable, offset: 0x40 */
61174   __O  uint32_t ELS_INT_STATUS_CLR;                /**< Interrupt Status Clear, offset: 0x44 */
61175   __O  uint32_t ELS_INT_STATUS_SET;                /**< Interrupt Status Set, offset: 0x48 */
61176   __I  uint32_t ELS_ERR_STATUS;                    /**< Error Status, offset: 0x4C */
61177   __O  uint32_t ELS_ERR_STATUS_CLR;                /**< Error Status Clear, offset: 0x50 */
61178   __I  uint32_t ELS_VERSION;                       /**< Version Register, offset: 0x54 */
61179        uint8_t RESERVED_2[4];
61180   __I  uint32_t ELS_PRNG_DATOUT;                   /**< PRNG SW Read Out, offset: 0x5C */
61181   __IO uint32_t ELS_CMDCRC_CTRL;                   /**< CRC Configuration, offset: 0x60 */
61182   __I  uint32_t ELS_CMDCRC;                        /**< Command CRC Value, offset: 0x64 */
61183   __IO uint32_t ELS_SESSION_ID;                    /**< Session ID, offset: 0x68 */
61184        uint8_t RESERVED_3[4];
61185   __I  uint32_t ELS_DMA_FIN_ADDR;                  /**< Final DMA Address, offset: 0x70 */
61186   __IO uint32_t ELS_MASTER_ID;                     /**< Master ID, offset: 0x74 */
61187   __IO uint32_t ELS_KIDX2;                         /**< Keystore Index 2, offset: 0x78 */
61188        uint8_t RESERVED_4[212];
61189   __I  uint32_t ELS_KS0;                           /**< Status Register, offset: 0x150 */
61190   __I  uint32_t ELS_KS1;                           /**< Status Register, offset: 0x154 */
61191   __I  uint32_t ELS_KS2;                           /**< Status Register, offset: 0x158 */
61192   __I  uint32_t ELS_KS3;                           /**< Status Register, offset: 0x15C */
61193   __I  uint32_t ELS_KS4;                           /**< Status Register, offset: 0x160 */
61194   __I  uint32_t ELS_KS5;                           /**< Status Register, offset: 0x164 */
61195   __I  uint32_t ELS_KS6;                           /**< Status Register, offset: 0x168 */
61196   __I  uint32_t ELS_KS7;                           /**< Status Register, offset: 0x16C */
61197   __I  uint32_t ELS_KS8;                           /**< Status Register, offset: 0x170 */
61198   __I  uint32_t ELS_KS9;                           /**< Status Register, offset: 0x174 */
61199   __I  uint32_t ELS_KS10;                          /**< Status Register, offset: 0x178 */
61200   __I  uint32_t ELS_KS11;                          /**< Status Register, offset: 0x17C */
61201   __I  uint32_t ELS_KS12;                          /**< Status Register, offset: 0x180 */
61202   __I  uint32_t ELS_KS13;                          /**< Status Register, offset: 0x184 */
61203   __I  uint32_t ELS_KS14;                          /**< Status Register, offset: 0x188 */
61204   __I  uint32_t ELS_KS15;                          /**< Status Register, offset: 0x18C */
61205   __I  uint32_t ELS_KS16;                          /**< Status Register, offset: 0x190 */
61206   __I  uint32_t ELS_KS17;                          /**< Status Register, offset: 0x194 */
61207   __I  uint32_t ELS_KS18;                          /**< Status Register, offset: 0x198 */
61208   __I  uint32_t ELS_KS19;                          /**< Status Register, offset: 0x19C */
61209 } S50_Type;
61210 
61211 /* ----------------------------------------------------------------------------
61212    -- S50 Register Masks
61213    ---------------------------------------------------------------------------- */
61214 
61215 /*!
61216  * @addtogroup S50_Register_Masks S50 Register Masks
61217  * @{
61218  */
61219 
61220 /*! @name ELS_STATUS - Status Register */
61221 /*! @{ */
61222 
61223 #define S50_ELS_STATUS_ELS_BUSY_MASK             (0x1U)
61224 #define S50_ELS_STATUS_ELS_BUSY_SHIFT            (0U)
61225 /*! ELS_BUSY
61226  *  0b1..Crypto sequence executing
61227  *  0b0..Crypto sequence not executing
61228  */
61229 #define S50_ELS_STATUS_ELS_BUSY(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_STATUS_ELS_BUSY_SHIFT)) & S50_ELS_STATUS_ELS_BUSY_MASK)
61230 
61231 #define S50_ELS_STATUS_ELS_IRQ_MASK              (0x2U)
61232 #define S50_ELS_STATUS_ELS_IRQ_SHIFT             (1U)
61233 /*! ELS_IRQ
61234  *  0b1..Active interrupt
61235  *  0b0..No active interrupt
61236  */
61237 #define S50_ELS_STATUS_ELS_IRQ(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_STATUS_ELS_IRQ_SHIFT)) & S50_ELS_STATUS_ELS_IRQ_MASK)
61238 
61239 #define S50_ELS_STATUS_ELS_ERR_MASK              (0x4U)
61240 #define S50_ELS_STATUS_ELS_ERR_SHIFT             (2U)
61241 /*! ELS_ERR
61242  *  0b1..Internal error detected
61243  *  0b0..Internal error not detected
61244  */
61245 #define S50_ELS_STATUS_ELS_ERR(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_STATUS_ELS_ERR_SHIFT)) & S50_ELS_STATUS_ELS_ERR_MASK)
61246 
61247 #define S50_ELS_STATUS_PRNG_RDY_MASK             (0x8U)
61248 #define S50_ELS_STATUS_PRNG_RDY_SHIFT            (3U)
61249 /*! PRNG_RDY
61250  *  0b0..Internal PRNG not ready
61251  *  0b1..Internal PRNG ready
61252  */
61253 #define S50_ELS_STATUS_PRNG_RDY(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_STATUS_PRNG_RDY_SHIFT)) & S50_ELS_STATUS_PRNG_RDY_MASK)
61254 
61255 #define S50_ELS_STATUS_ECDSA_VFY_STATUS_MASK     (0x30U)
61256 #define S50_ELS_STATUS_ECDSA_VFY_STATUS_SHIFT    (4U)
61257 /*! ECDSA_VFY_STATUS
61258  *  0b11..Invalid, Error
61259  *  0b00..No verify run
61260  *  0b01..Signature verify failed
61261  *  0b10..Signature verify passed
61262  */
61263 #define S50_ELS_STATUS_ECDSA_VFY_STATUS(x)       (((uint32_t)(((uint32_t)(x)) << S50_ELS_STATUS_ECDSA_VFY_STATUS_SHIFT)) & S50_ELS_STATUS_ECDSA_VFY_STATUS_MASK)
61264 
61265 #define S50_ELS_STATUS_PPROT_MASK                (0xC0U)
61266 #define S50_ELS_STATUS_PPROT_SHIFT               (6U)
61267 /*! PPROT
61268  *  0b10..Non-secure, non-privileged
61269  *  0b11..Non-secure, privileged
61270  *  0b00..Secure, non-privileged
61271  *  0b01..Secure, privileged
61272  */
61273 #define S50_ELS_STATUS_PPROT(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_STATUS_PPROT_SHIFT)) & S50_ELS_STATUS_PPROT_MASK)
61274 
61275 #define S50_ELS_STATUS_DRBG_ENT_LVL_MASK         (0x300U)
61276 #define S50_ELS_STATUS_DRBG_ENT_LVL_SHIFT        (8U)
61277 /*! DRBG_ENT_LVL
61278  *  0b10..HIGH, DRBG generates random numbers of high quality entropy
61279  *  0b01..LOW, DRBG generates random numbers of low quality entropy
61280  *  0b00..NONE
61281  *  0b11..RFU, Reserved for Future Use
61282  */
61283 #define S50_ELS_STATUS_DRBG_ENT_LVL(x)           (((uint32_t)(((uint32_t)(x)) << S50_ELS_STATUS_DRBG_ENT_LVL_SHIFT)) & S50_ELS_STATUS_DRBG_ENT_LVL_MASK)
61284 
61285 #define S50_ELS_STATUS_DTRNG_BUSY_MASK           (0x400U)
61286 #define S50_ELS_STATUS_DTRNG_BUSY_SHIFT          (10U)
61287 /*! DTRNG_BUSY
61288  *  0b1..Gathering entropy
61289  *  0b0..Not gathering entropy
61290  */
61291 #define S50_ELS_STATUS_DTRNG_BUSY(x)             (((uint32_t)(((uint32_t)(x)) << S50_ELS_STATUS_DTRNG_BUSY_SHIFT)) & S50_ELS_STATUS_DTRNG_BUSY_MASK)
61292 
61293 #define S50_ELS_STATUS_ELS_LOCKED_MASK           (0x10000U)
61294 #define S50_ELS_STATUS_ELS_LOCKED_SHIFT          (16U)
61295 /*! ELS_LOCKED
61296  *  0b1..Locked by master
61297  *  0b0..Not locked by master
61298  */
61299 #define S50_ELS_STATUS_ELS_LOCKED(x)             (((uint32_t)(((uint32_t)(x)) << S50_ELS_STATUS_ELS_LOCKED_SHIFT)) & S50_ELS_STATUS_ELS_LOCKED_MASK)
61300 /*! @} */
61301 
61302 /*! @name ELS_CTRL - Control Register */
61303 /*! @{ */
61304 
61305 #define S50_ELS_CTRL_ELS_EN_MASK                 (0x1U)
61306 #define S50_ELS_CTRL_ELS_EN_SHIFT                (0U)
61307 /*! ELS_EN
61308  *  0b0..Disabled
61309  *  0b1..Enabled
61310  */
61311 #define S50_ELS_CTRL_ELS_EN(x)                   (((uint32_t)(((uint32_t)(x)) << S50_ELS_CTRL_ELS_EN_SHIFT)) & S50_ELS_CTRL_ELS_EN_MASK)
61312 
61313 #define S50_ELS_CTRL_ELS_START_MASK              (0x2U)
61314 #define S50_ELS_CTRL_ELS_START_SHIFT             (1U)
61315 #define S50_ELS_CTRL_ELS_START(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_CTRL_ELS_START_SHIFT)) & S50_ELS_CTRL_ELS_START_MASK)
61316 
61317 #define S50_ELS_CTRL_ELS_RESET_MASK              (0x4U)
61318 #define S50_ELS_CTRL_ELS_RESET_SHIFT             (2U)
61319 #define S50_ELS_CTRL_ELS_RESET(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_CTRL_ELS_RESET_SHIFT)) & S50_ELS_CTRL_ELS_RESET_MASK)
61320 
61321 #define S50_ELS_CTRL_ELS_CMD_MASK                (0xF8U)
61322 #define S50_ELS_CTRL_ELS_CMD_SHIFT               (3U)
61323 /*! ELS_CMD - ELS Command ID */
61324 #define S50_ELS_CTRL_ELS_CMD(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_CTRL_ELS_CMD_SHIFT)) & S50_ELS_CTRL_ELS_CMD_MASK)
61325 
61326 #define S50_ELS_CTRL_BYTE_ORDER_MASK             (0x100U)
61327 #define S50_ELS_CTRL_BYTE_ORDER_SHIFT            (8U)
61328 /*! BYTE_ORDER
61329  *  0b1..Big endian
61330  *  0b0..Little endian
61331  */
61332 #define S50_ELS_CTRL_BYTE_ORDER(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_CTRL_BYTE_ORDER_SHIFT)) & S50_ELS_CTRL_BYTE_ORDER_MASK)
61333 /*! @} */
61334 
61335 /*! @name ELS_CMDCFG0 - Command Configuration */
61336 /*! @{ */
61337 
61338 #define S50_ELS_CMDCFG0_CMDCFG0_MASK             (0xFFFFFFFFU)
61339 #define S50_ELS_CMDCFG0_CMDCFG0_SHIFT            (0U)
61340 #define S50_ELS_CMDCFG0_CMDCFG0(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_CMDCFG0_CMDCFG0_SHIFT)) & S50_ELS_CMDCFG0_CMDCFG0_MASK)
61341 /*! @} */
61342 
61343 /*! @name ELS_CFG - Configuration Register */
61344 /*! @{ */
61345 
61346 #define S50_ELS_CFG_ADCTRL_MASK                  (0x3FF0000U)
61347 #define S50_ELS_CFG_ADCTRL_SHIFT                 (16U)
61348 #define S50_ELS_CFG_ADCTRL(x)                    (((uint32_t)(((uint32_t)(x)) << S50_ELS_CFG_ADCTRL_SHIFT)) & S50_ELS_CFG_ADCTRL_MASK)
61349 /*! @} */
61350 
61351 /*! @name ELS_KIDX0 - Keystore Index 0 */
61352 /*! @{ */
61353 
61354 #define S50_ELS_KIDX0_KIDX0_MASK                 (0x1FU)
61355 #define S50_ELS_KIDX0_KIDX0_SHIFT                (0U)
61356 #define S50_ELS_KIDX0_KIDX0(x)                   (((uint32_t)(((uint32_t)(x)) << S50_ELS_KIDX0_KIDX0_SHIFT)) & S50_ELS_KIDX0_KIDX0_MASK)
61357 /*! @} */
61358 
61359 /*! @name ELS_KIDX1 - Keystore Index 1 */
61360 /*! @{ */
61361 
61362 #define S50_ELS_KIDX1_KIDX1_MASK                 (0x1FU)
61363 #define S50_ELS_KIDX1_KIDX1_SHIFT                (0U)
61364 #define S50_ELS_KIDX1_KIDX1(x)                   (((uint32_t)(((uint32_t)(x)) << S50_ELS_KIDX1_KIDX1_SHIFT)) & S50_ELS_KIDX1_KIDX1_MASK)
61365 /*! @} */
61366 
61367 /*! @name ELS_KPROPIN - Key Properties Request */
61368 /*! @{ */
61369 
61370 #define S50_ELS_KPROPIN_KPROPIN_MASK             (0xFFFFFFFFU)
61371 #define S50_ELS_KPROPIN_KPROPIN_SHIFT            (0U)
61372 #define S50_ELS_KPROPIN_KPROPIN(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KPROPIN_KPROPIN_SHIFT)) & S50_ELS_KPROPIN_KPROPIN_MASK)
61373 /*! @} */
61374 
61375 /*! @name ELS_DMA_SRC0 - DMA Source 0 */
61376 /*! @{ */
61377 
61378 #define S50_ELS_DMA_SRC0_ADDR_SRC0_MASK          (0xFFFFFFFFU)
61379 #define S50_ELS_DMA_SRC0_ADDR_SRC0_SHIFT         (0U)
61380 #define S50_ELS_DMA_SRC0_ADDR_SRC0(x)            (((uint32_t)(((uint32_t)(x)) << S50_ELS_DMA_SRC0_ADDR_SRC0_SHIFT)) & S50_ELS_DMA_SRC0_ADDR_SRC0_MASK)
61381 /*! @} */
61382 
61383 /*! @name ELS_DMA_SRC0_LEN - DMA Source 0 Length */
61384 /*! @{ */
61385 
61386 #define S50_ELS_DMA_SRC0_LEN_SIZE_SRC0_LEN_MASK  (0xFFFFFFFFU)
61387 #define S50_ELS_DMA_SRC0_LEN_SIZE_SRC0_LEN_SHIFT (0U)
61388 #define S50_ELS_DMA_SRC0_LEN_SIZE_SRC0_LEN(x)    (((uint32_t)(((uint32_t)(x)) << S50_ELS_DMA_SRC0_LEN_SIZE_SRC0_LEN_SHIFT)) & S50_ELS_DMA_SRC0_LEN_SIZE_SRC0_LEN_MASK)
61389 /*! @} */
61390 
61391 /*! @name ELS_DMA_SRC1 - DMA Source 1 */
61392 /*! @{ */
61393 
61394 #define S50_ELS_DMA_SRC1_ADDR_SRC1_MASK          (0xFFFFFFFFU)
61395 #define S50_ELS_DMA_SRC1_ADDR_SRC1_SHIFT         (0U)
61396 #define S50_ELS_DMA_SRC1_ADDR_SRC1(x)            (((uint32_t)(((uint32_t)(x)) << S50_ELS_DMA_SRC1_ADDR_SRC1_SHIFT)) & S50_ELS_DMA_SRC1_ADDR_SRC1_MASK)
61397 /*! @} */
61398 
61399 /*! @name ELS_DMA_SRC2 - DMA Source 2 */
61400 /*! @{ */
61401 
61402 #define S50_ELS_DMA_SRC2_ADDR_SRC2_MASK          (0xFFFFFFFFU)
61403 #define S50_ELS_DMA_SRC2_ADDR_SRC2_SHIFT         (0U)
61404 #define S50_ELS_DMA_SRC2_ADDR_SRC2(x)            (((uint32_t)(((uint32_t)(x)) << S50_ELS_DMA_SRC2_ADDR_SRC2_SHIFT)) & S50_ELS_DMA_SRC2_ADDR_SRC2_MASK)
61405 /*! @} */
61406 
61407 /*! @name ELS_DMA_SRC2_LEN - DMA Source 2 Length */
61408 /*! @{ */
61409 
61410 #define S50_ELS_DMA_SRC2_LEN_SIZE_SRC2_LEN_MASK  (0xFFFFFFFFU)
61411 #define S50_ELS_DMA_SRC2_LEN_SIZE_SRC2_LEN_SHIFT (0U)
61412 #define S50_ELS_DMA_SRC2_LEN_SIZE_SRC2_LEN(x)    (((uint32_t)(((uint32_t)(x)) << S50_ELS_DMA_SRC2_LEN_SIZE_SRC2_LEN_SHIFT)) & S50_ELS_DMA_SRC2_LEN_SIZE_SRC2_LEN_MASK)
61413 /*! @} */
61414 
61415 /*! @name ELS_DMA_RES0 - DMA Result 0 */
61416 /*! @{ */
61417 
61418 #define S50_ELS_DMA_RES0_ADDR_RES0_MASK          (0xFFFFFFFFU)
61419 #define S50_ELS_DMA_RES0_ADDR_RES0_SHIFT         (0U)
61420 #define S50_ELS_DMA_RES0_ADDR_RES0(x)            (((uint32_t)(((uint32_t)(x)) << S50_ELS_DMA_RES0_ADDR_RES0_SHIFT)) & S50_ELS_DMA_RES0_ADDR_RES0_MASK)
61421 /*! @} */
61422 
61423 /*! @name ELS_DMA_RES0_LEN - DMA Result 0 Length */
61424 /*! @{ */
61425 
61426 #define S50_ELS_DMA_RES0_LEN_SIZE_RES0_LEN_MASK  (0xFFFFFFFFU)
61427 #define S50_ELS_DMA_RES0_LEN_SIZE_RES0_LEN_SHIFT (0U)
61428 #define S50_ELS_DMA_RES0_LEN_SIZE_RES0_LEN(x)    (((uint32_t)(((uint32_t)(x)) << S50_ELS_DMA_RES0_LEN_SIZE_RES0_LEN_SHIFT)) & S50_ELS_DMA_RES0_LEN_SIZE_RES0_LEN_MASK)
61429 /*! @} */
61430 
61431 /*! @name ELS_INT_ENABLE - Interrupt Enable */
61432 /*! @{ */
61433 
61434 #define S50_ELS_INT_ENABLE_INT_EN_MASK           (0x1U)
61435 #define S50_ELS_INT_ENABLE_INT_EN_SHIFT          (0U)
61436 /*! INT_EN
61437  *  0b0..Disables
61438  *  0b1..Enables
61439  */
61440 #define S50_ELS_INT_ENABLE_INT_EN(x)             (((uint32_t)(((uint32_t)(x)) << S50_ELS_INT_ENABLE_INT_EN_SHIFT)) & S50_ELS_INT_ENABLE_INT_EN_MASK)
61441 /*! @} */
61442 
61443 /*! @name ELS_INT_STATUS_CLR - Interrupt Status Clear */
61444 /*! @{ */
61445 
61446 #define S50_ELS_INT_STATUS_CLR_INT_CLR_MASK      (0x1U)
61447 #define S50_ELS_INT_STATUS_CLR_INT_CLR_SHIFT     (0U)
61448 #define S50_ELS_INT_STATUS_CLR_INT_CLR(x)        (((uint32_t)(((uint32_t)(x)) << S50_ELS_INT_STATUS_CLR_INT_CLR_SHIFT)) & S50_ELS_INT_STATUS_CLR_INT_CLR_MASK)
61449 /*! @} */
61450 
61451 /*! @name ELS_INT_STATUS_SET - Interrupt Status Set */
61452 /*! @{ */
61453 
61454 #define S50_ELS_INT_STATUS_SET_INT_SET_MASK      (0x1U)
61455 #define S50_ELS_INT_STATUS_SET_INT_SET_SHIFT     (0U)
61456 #define S50_ELS_INT_STATUS_SET_INT_SET(x)        (((uint32_t)(((uint32_t)(x)) << S50_ELS_INT_STATUS_SET_INT_SET_SHIFT)) & S50_ELS_INT_STATUS_SET_INT_SET_MASK)
61457 /*! @} */
61458 
61459 /*! @name ELS_ERR_STATUS - Error Status */
61460 /*! @{ */
61461 
61462 #define S50_ELS_ERR_STATUS_BUS_ERR_MASK          (0x1U)
61463 #define S50_ELS_ERR_STATUS_BUS_ERR_SHIFT         (0U)
61464 /*! BUS_ERR
61465  *  0b0..No error
61466  *  0b1..Error occurred
61467  */
61468 #define S50_ELS_ERR_STATUS_BUS_ERR(x)            (((uint32_t)(((uint32_t)(x)) << S50_ELS_ERR_STATUS_BUS_ERR_SHIFT)) & S50_ELS_ERR_STATUS_BUS_ERR_MASK)
61469 
61470 #define S50_ELS_ERR_STATUS_OPN_ERR_MASK          (0x2U)
61471 #define S50_ELS_ERR_STATUS_OPN_ERR_SHIFT         (1U)
61472 /*! OPN_ERR
61473  *  0b0..No error
61474  *  0b1..Error occurred
61475  */
61476 #define S50_ELS_ERR_STATUS_OPN_ERR(x)            (((uint32_t)(((uint32_t)(x)) << S50_ELS_ERR_STATUS_OPN_ERR_SHIFT)) & S50_ELS_ERR_STATUS_OPN_ERR_MASK)
61477 
61478 #define S50_ELS_ERR_STATUS_ALG_ERR_MASK          (0x4U)
61479 #define S50_ELS_ERR_STATUS_ALG_ERR_SHIFT         (2U)
61480 /*! ALG_ERR
61481  *  0b0..No error
61482  *  0b1..Error occurred
61483  */
61484 #define S50_ELS_ERR_STATUS_ALG_ERR(x)            (((uint32_t)(((uint32_t)(x)) << S50_ELS_ERR_STATUS_ALG_ERR_SHIFT)) & S50_ELS_ERR_STATUS_ALG_ERR_MASK)
61485 
61486 #define S50_ELS_ERR_STATUS_ITG_ERR_MASK          (0x8U)
61487 #define S50_ELS_ERR_STATUS_ITG_ERR_SHIFT         (3U)
61488 /*! ITG_ERR
61489  *  0b0..No error
61490  *  0b1..Error occurred
61491  */
61492 #define S50_ELS_ERR_STATUS_ITG_ERR(x)            (((uint32_t)(((uint32_t)(x)) << S50_ELS_ERR_STATUS_ITG_ERR_SHIFT)) & S50_ELS_ERR_STATUS_ITG_ERR_MASK)
61493 
61494 #define S50_ELS_ERR_STATUS_FLT_ERR_MASK          (0x10U)
61495 #define S50_ELS_ERR_STATUS_FLT_ERR_SHIFT         (4U)
61496 /*! FLT_ERR
61497  *  0b0..No error
61498  *  0b1..Error occurred
61499  */
61500 #define S50_ELS_ERR_STATUS_FLT_ERR(x)            (((uint32_t)(((uint32_t)(x)) << S50_ELS_ERR_STATUS_FLT_ERR_SHIFT)) & S50_ELS_ERR_STATUS_FLT_ERR_MASK)
61501 
61502 #define S50_ELS_ERR_STATUS_PRNG_ERR_MASK         (0x20U)
61503 #define S50_ELS_ERR_STATUS_PRNG_ERR_SHIFT        (5U)
61504 /*! PRNG_ERR
61505  *  0b0..No error
61506  *  0b1..Error occurred
61507  */
61508 #define S50_ELS_ERR_STATUS_PRNG_ERR(x)           (((uint32_t)(((uint32_t)(x)) << S50_ELS_ERR_STATUS_PRNG_ERR_SHIFT)) & S50_ELS_ERR_STATUS_PRNG_ERR_MASK)
61509 
61510 #define S50_ELS_ERR_STATUS_ERR_LVL_MASK          (0xC0U)
61511 #define S50_ELS_ERR_STATUS_ERR_LVL_SHIFT         (6U)
61512 #define S50_ELS_ERR_STATUS_ERR_LVL(x)            (((uint32_t)(((uint32_t)(x)) << S50_ELS_ERR_STATUS_ERR_LVL_SHIFT)) & S50_ELS_ERR_STATUS_ERR_LVL_MASK)
61513 
61514 #define S50_ELS_ERR_STATUS_DTRNG_ERR_MASK        (0x100U)
61515 #define S50_ELS_ERR_STATUS_DTRNG_ERR_SHIFT       (8U)
61516 /*! DTRNG_ERR
61517  *  0b0..No error
61518  *  0b1..TRNG error occurred
61519  */
61520 #define S50_ELS_ERR_STATUS_DTRNG_ERR(x)          (((uint32_t)(((uint32_t)(x)) << S50_ELS_ERR_STATUS_DTRNG_ERR_SHIFT)) & S50_ELS_ERR_STATUS_DTRNG_ERR_MASK)
61521 /*! @} */
61522 
61523 /*! @name ELS_ERR_STATUS_CLR - Error Status Clear */
61524 /*! @{ */
61525 
61526 #define S50_ELS_ERR_STATUS_CLR_ERR_CLR_MASK      (0x1U)
61527 #define S50_ELS_ERR_STATUS_CLR_ERR_CLR_SHIFT     (0U)
61528 /*! ERR_CLR
61529  *  0b1..Clears ELS error state
61530  *  0b0..Exits ELS error state
61531  */
61532 #define S50_ELS_ERR_STATUS_CLR_ERR_CLR(x)        (((uint32_t)(((uint32_t)(x)) << S50_ELS_ERR_STATUS_CLR_ERR_CLR_SHIFT)) & S50_ELS_ERR_STATUS_CLR_ERR_CLR_MASK)
61533 /*! @} */
61534 
61535 /*! @name ELS_VERSION - Version Register */
61536 /*! @{ */
61537 
61538 #define S50_ELS_VERSION_Z_MASK                   (0xFU)
61539 #define S50_ELS_VERSION_Z_SHIFT                  (0U)
61540 #define S50_ELS_VERSION_Z(x)                     (((uint32_t)(((uint32_t)(x)) << S50_ELS_VERSION_Z_SHIFT)) & S50_ELS_VERSION_Z_MASK)
61541 
61542 #define S50_ELS_VERSION_Y2_MASK                  (0xF0U)
61543 #define S50_ELS_VERSION_Y2_SHIFT                 (4U)
61544 #define S50_ELS_VERSION_Y2(x)                    (((uint32_t)(((uint32_t)(x)) << S50_ELS_VERSION_Y2_SHIFT)) & S50_ELS_VERSION_Y2_MASK)
61545 
61546 #define S50_ELS_VERSION_Y1_MASK                  (0xF00U)
61547 #define S50_ELS_VERSION_Y1_SHIFT                 (8U)
61548 #define S50_ELS_VERSION_Y1(x)                    (((uint32_t)(((uint32_t)(x)) << S50_ELS_VERSION_Y1_SHIFT)) & S50_ELS_VERSION_Y1_MASK)
61549 
61550 #define S50_ELS_VERSION_X_MASK                   (0xF000U)
61551 #define S50_ELS_VERSION_X_SHIFT                  (12U)
61552 #define S50_ELS_VERSION_X(x)                     (((uint32_t)(((uint32_t)(x)) << S50_ELS_VERSION_X_SHIFT)) & S50_ELS_VERSION_X_MASK)
61553 
61554 #define S50_ELS_VERSION_SW_Z_MASK                (0xF0000U)
61555 #define S50_ELS_VERSION_SW_Z_SHIFT               (16U)
61556 #define S50_ELS_VERSION_SW_Z(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_VERSION_SW_Z_SHIFT)) & S50_ELS_VERSION_SW_Z_MASK)
61557 
61558 #define S50_ELS_VERSION_SW_Y2_MASK               (0xF00000U)
61559 #define S50_ELS_VERSION_SW_Y2_SHIFT              (20U)
61560 #define S50_ELS_VERSION_SW_Y2(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_VERSION_SW_Y2_SHIFT)) & S50_ELS_VERSION_SW_Y2_MASK)
61561 
61562 #define S50_ELS_VERSION_SW_Y1_MASK               (0xF000000U)
61563 #define S50_ELS_VERSION_SW_Y1_SHIFT              (24U)
61564 #define S50_ELS_VERSION_SW_Y1(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_VERSION_SW_Y1_SHIFT)) & S50_ELS_VERSION_SW_Y1_MASK)
61565 
61566 #define S50_ELS_VERSION_SW_X_MASK                (0xF0000000U)
61567 #define S50_ELS_VERSION_SW_X_SHIFT               (28U)
61568 #define S50_ELS_VERSION_SW_X(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_VERSION_SW_X_SHIFT)) & S50_ELS_VERSION_SW_X_MASK)
61569 /*! @} */
61570 
61571 /*! @name ELS_PRNG_DATOUT - PRNG SW Read Out */
61572 /*! @{ */
61573 
61574 #define S50_ELS_PRNG_DATOUT_PRNG_DATOUT_MASK     (0xFFFFFFFFU)
61575 #define S50_ELS_PRNG_DATOUT_PRNG_DATOUT_SHIFT    (0U)
61576 #define S50_ELS_PRNG_DATOUT_PRNG_DATOUT(x)       (((uint32_t)(((uint32_t)(x)) << S50_ELS_PRNG_DATOUT_PRNG_DATOUT_SHIFT)) & S50_ELS_PRNG_DATOUT_PRNG_DATOUT_MASK)
61577 /*! @} */
61578 
61579 /*! @name ELS_CMDCRC_CTRL - CRC Configuration */
61580 /*! @{ */
61581 
61582 #define S50_ELS_CMDCRC_CTRL_CMDCRC_RST_MASK      (0x1U)
61583 #define S50_ELS_CMDCRC_CTRL_CMDCRC_RST_SHIFT     (0U)
61584 /*! CMDCRC_RST
61585  *  0b1..Resets the CRC command to its default value
61586  *  0b0..No effect
61587  */
61588 #define S50_ELS_CMDCRC_CTRL_CMDCRC_RST(x)        (((uint32_t)(((uint32_t)(x)) << S50_ELS_CMDCRC_CTRL_CMDCRC_RST_SHIFT)) & S50_ELS_CMDCRC_CTRL_CMDCRC_RST_MASK)
61589 
61590 #define S50_ELS_CMDCRC_CTRL_CMDCRC_EN_MASK       (0x2U)
61591 #define S50_ELS_CMDCRC_CTRL_CMDCRC_EN_SHIFT      (1U)
61592 /*! CMDCRC_EN
61593  *  0b1..Enables the CRC command. The CRC command will be updated on completion of each ELS command.
61594  *  0b0..Disables the CRC command CRC. The CRC command will not be updated on completion of each ELS command.
61595  */
61596 #define S50_ELS_CMDCRC_CTRL_CMDCRC_EN(x)         (((uint32_t)(((uint32_t)(x)) << S50_ELS_CMDCRC_CTRL_CMDCRC_EN_SHIFT)) & S50_ELS_CMDCRC_CTRL_CMDCRC_EN_MASK)
61597 /*! @} */
61598 
61599 /*! @name ELS_CMDCRC - Command CRC Value */
61600 /*! @{ */
61601 
61602 #define S50_ELS_CMDCRC_CMDCRC_MASK               (0xFFFFFFFFU)
61603 #define S50_ELS_CMDCRC_CMDCRC_SHIFT              (0U)
61604 #define S50_ELS_CMDCRC_CMDCRC(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_CMDCRC_CMDCRC_SHIFT)) & S50_ELS_CMDCRC_CMDCRC_MASK)
61605 /*! @} */
61606 
61607 /*! @name ELS_SESSION_ID - Session ID */
61608 /*! @{ */
61609 
61610 #define S50_ELS_SESSION_ID_SESSION_ID_MASK       (0xFFFFFFFFU)
61611 #define S50_ELS_SESSION_ID_SESSION_ID_SHIFT      (0U)
61612 #define S50_ELS_SESSION_ID_SESSION_ID(x)         (((uint32_t)(((uint32_t)(x)) << S50_ELS_SESSION_ID_SESSION_ID_SHIFT)) & S50_ELS_SESSION_ID_SESSION_ID_MASK)
61613 /*! @} */
61614 
61615 /*! @name ELS_DMA_FIN_ADDR - Final DMA Address */
61616 /*! @{ */
61617 
61618 #define S50_ELS_DMA_FIN_ADDR_DMA_FIN_ADDR_MASK   (0xFFFFFFFFU)
61619 #define S50_ELS_DMA_FIN_ADDR_DMA_FIN_ADDR_SHIFT  (0U)
61620 #define S50_ELS_DMA_FIN_ADDR_DMA_FIN_ADDR(x)     (((uint32_t)(((uint32_t)(x)) << S50_ELS_DMA_FIN_ADDR_DMA_FIN_ADDR_SHIFT)) & S50_ELS_DMA_FIN_ADDR_DMA_FIN_ADDR_MASK)
61621 /*! @} */
61622 
61623 /*! @name ELS_MASTER_ID - Master ID */
61624 /*! @{ */
61625 
61626 #define S50_ELS_MASTER_ID_MASTER_ID_MASK         (0x1FU)
61627 #define S50_ELS_MASTER_ID_MASTER_ID_SHIFT        (0U)
61628 #define S50_ELS_MASTER_ID_MASTER_ID(x)           (((uint32_t)(((uint32_t)(x)) << S50_ELS_MASTER_ID_MASTER_ID_SHIFT)) & S50_ELS_MASTER_ID_MASTER_ID_MASK)
61629 /*! @} */
61630 
61631 /*! @name ELS_KIDX2 - Keystore Index 2 */
61632 /*! @{ */
61633 
61634 #define S50_ELS_KIDX2_KIDX2_MASK                 (0x1FU)
61635 #define S50_ELS_KIDX2_KIDX2_SHIFT                (0U)
61636 #define S50_ELS_KIDX2_KIDX2(x)                   (((uint32_t)(((uint32_t)(x)) << S50_ELS_KIDX2_KIDX2_SHIFT)) & S50_ELS_KIDX2_KIDX2_MASK)
61637 /*! @} */
61638 
61639 /*! @name ELS_KS0 - Status Register */
61640 /*! @{ */
61641 
61642 #define S50_ELS_KS0_KS0_KSIZE_MASK               (0x3U)
61643 #define S50_ELS_KS0_KS0_KSIZE_SHIFT              (0U)
61644 /*! KS0_KSIZE
61645  *  0b00..128
61646  *  0b01..256
61647  */
61648 #define S50_ELS_KS0_KS0_KSIZE(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_KSIZE_SHIFT)) & S50_ELS_KS0_KS0_KSIZE_MASK)
61649 
61650 #define S50_ELS_KS0_KS0_KACT_MASK                (0x20U)
61651 #define S50_ELS_KS0_KS0_KACT_SHIFT               (5U)
61652 #define S50_ELS_KS0_KS0_KACT(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_KACT_SHIFT)) & S50_ELS_KS0_KS0_KACT_MASK)
61653 
61654 #define S50_ELS_KS0_KS0_KBASE_MASK               (0x40U)
61655 #define S50_ELS_KS0_KS0_KBASE_SHIFT              (6U)
61656 #define S50_ELS_KS0_KS0_KBASE(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_KBASE_SHIFT)) & S50_ELS_KS0_KS0_KBASE_MASK)
61657 
61658 #define S50_ELS_KS0_KS0_FGP_MASK                 (0x80U)
61659 #define S50_ELS_KS0_KS0_FGP_SHIFT                (7U)
61660 #define S50_ELS_KS0_KS0_FGP(x)                   (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_FGP_SHIFT)) & S50_ELS_KS0_KS0_FGP_MASK)
61661 
61662 #define S50_ELS_KS0_KS0_FRTN_MASK                (0x100U)
61663 #define S50_ELS_KS0_KS0_FRTN_SHIFT               (8U)
61664 #define S50_ELS_KS0_KS0_FRTN(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_FRTN_SHIFT)) & S50_ELS_KS0_KS0_FRTN_MASK)
61665 
61666 #define S50_ELS_KS0_KS0_FHWO_MASK                (0x200U)
61667 #define S50_ELS_KS0_KS0_FHWO_SHIFT               (9U)
61668 #define S50_ELS_KS0_KS0_FHWO(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_FHWO_SHIFT)) & S50_ELS_KS0_KS0_FHWO_MASK)
61669 
61670 #define S50_ELS_KS0_KS0_UKPUK_MASK               (0x800U)
61671 #define S50_ELS_KS0_KS0_UKPUK_SHIFT              (11U)
61672 #define S50_ELS_KS0_KS0_UKPUK(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UKPUK_SHIFT)) & S50_ELS_KS0_KS0_UKPUK_MASK)
61673 
61674 #define S50_ELS_KS0_KS0_UTECDH_MASK              (0x1000U)
61675 #define S50_ELS_KS0_KS0_UTECDH_SHIFT             (12U)
61676 #define S50_ELS_KS0_KS0_UTECDH(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UTECDH_SHIFT)) & S50_ELS_KS0_KS0_UTECDH_MASK)
61677 
61678 #define S50_ELS_KS0_KS0_UCMAC_MASK               (0x2000U)
61679 #define S50_ELS_KS0_KS0_UCMAC_SHIFT              (13U)
61680 #define S50_ELS_KS0_KS0_UCMAC(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UCMAC_SHIFT)) & S50_ELS_KS0_KS0_UCMAC_MASK)
61681 
61682 #define S50_ELS_KS0_KS0_UKSK_MASK                (0x4000U)
61683 #define S50_ELS_KS0_KS0_UKSK_SHIFT               (14U)
61684 #define S50_ELS_KS0_KS0_UKSK(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UKSK_SHIFT)) & S50_ELS_KS0_KS0_UKSK_MASK)
61685 
61686 #define S50_ELS_KS0_KS0_URTF_MASK                (0x8000U)
61687 #define S50_ELS_KS0_KS0_URTF_SHIFT               (15U)
61688 #define S50_ELS_KS0_KS0_URTF(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_URTF_SHIFT)) & S50_ELS_KS0_KS0_URTF_MASK)
61689 
61690 #define S50_ELS_KS0_KS0_UCKDF_MASK               (0x10000U)
61691 #define S50_ELS_KS0_KS0_UCKDF_SHIFT              (16U)
61692 #define S50_ELS_KS0_KS0_UCKDF(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UCKDF_SHIFT)) & S50_ELS_KS0_KS0_UCKDF_MASK)
61693 
61694 #define S50_ELS_KS0_KS0_UHKDF_MASK               (0x20000U)
61695 #define S50_ELS_KS0_KS0_UHKDF_SHIFT              (17U)
61696 #define S50_ELS_KS0_KS0_UHKDF(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UHKDF_SHIFT)) & S50_ELS_KS0_KS0_UHKDF_MASK)
61697 
61698 #define S50_ELS_KS0_KS0_UECSG_MASK               (0x40000U)
61699 #define S50_ELS_KS0_KS0_UECSG_SHIFT              (18U)
61700 #define S50_ELS_KS0_KS0_UECSG(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UECSG_SHIFT)) & S50_ELS_KS0_KS0_UECSG_MASK)
61701 
61702 #define S50_ELS_KS0_KS0_UECDH_MASK               (0x80000U)
61703 #define S50_ELS_KS0_KS0_UECDH_SHIFT              (19U)
61704 #define S50_ELS_KS0_KS0_UECDH(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UECDH_SHIFT)) & S50_ELS_KS0_KS0_UECDH_MASK)
61705 
61706 #define S50_ELS_KS0_KS0_UAES_MASK                (0x100000U)
61707 #define S50_ELS_KS0_KS0_UAES_SHIFT               (20U)
61708 #define S50_ELS_KS0_KS0_UAES(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UAES_SHIFT)) & S50_ELS_KS0_KS0_UAES_MASK)
61709 
61710 #define S50_ELS_KS0_KS0_UHMAC_MASK               (0x200000U)
61711 #define S50_ELS_KS0_KS0_UHMAC_SHIFT              (21U)
61712 #define S50_ELS_KS0_KS0_UHMAC(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UHMAC_SHIFT)) & S50_ELS_KS0_KS0_UHMAC_MASK)
61713 
61714 #define S50_ELS_KS0_KS0_UKWK_MASK                (0x400000U)
61715 #define S50_ELS_KS0_KS0_UKWK_SHIFT               (22U)
61716 #define S50_ELS_KS0_KS0_UKWK(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UKWK_SHIFT)) & S50_ELS_KS0_KS0_UKWK_MASK)
61717 
61718 #define S50_ELS_KS0_KS0_UKUOK_MASK               (0x800000U)
61719 #define S50_ELS_KS0_KS0_UKUOK_SHIFT              (23U)
61720 #define S50_ELS_KS0_KS0_UKUOK(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UKUOK_SHIFT)) & S50_ELS_KS0_KS0_UKUOK_MASK)
61721 
61722 #define S50_ELS_KS0_KS0_UTLSPMS_MASK             (0x1000000U)
61723 #define S50_ELS_KS0_KS0_UTLSPMS_SHIFT            (24U)
61724 #define S50_ELS_KS0_KS0_UTLSPMS(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UTLSPMS_SHIFT)) & S50_ELS_KS0_KS0_UTLSPMS_MASK)
61725 
61726 #define S50_ELS_KS0_KS0_UTLSMS_MASK              (0x2000000U)
61727 #define S50_ELS_KS0_KS0_UTLSMS_SHIFT             (25U)
61728 #define S50_ELS_KS0_KS0_UTLSMS(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UTLSMS_SHIFT)) & S50_ELS_KS0_KS0_UTLSMS_MASK)
61729 
61730 #define S50_ELS_KS0_KS0_UKGSRC_MASK              (0x4000000U)
61731 #define S50_ELS_KS0_KS0_UKGSRC_SHIFT             (26U)
61732 #define S50_ELS_KS0_KS0_UKGSRC(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UKGSRC_SHIFT)) & S50_ELS_KS0_KS0_UKGSRC_MASK)
61733 
61734 #define S50_ELS_KS0_KS0_UHWO_MASK                (0x8000000U)
61735 #define S50_ELS_KS0_KS0_UHWO_SHIFT               (27U)
61736 #define S50_ELS_KS0_KS0_UHWO(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UHWO_SHIFT)) & S50_ELS_KS0_KS0_UHWO_MASK)
61737 
61738 #define S50_ELS_KS0_KS0_UWRPOK_MASK              (0x10000000U)
61739 #define S50_ELS_KS0_KS0_UWRPOK_SHIFT             (28U)
61740 #define S50_ELS_KS0_KS0_UWRPOK(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UWRPOK_SHIFT)) & S50_ELS_KS0_KS0_UWRPOK_MASK)
61741 
61742 #define S50_ELS_KS0_KS0_UDUK_MASK                (0x20000000U)
61743 #define S50_ELS_KS0_KS0_UDUK_SHIFT               (29U)
61744 #define S50_ELS_KS0_KS0_UDUK(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UDUK_SHIFT)) & S50_ELS_KS0_KS0_UDUK_MASK)
61745 
61746 #define S50_ELS_KS0_KS0_UPPROT_MASK              (0xC0000000U)
61747 #define S50_ELS_KS0_KS0_UPPROT_SHIFT             (30U)
61748 #define S50_ELS_KS0_KS0_UPPROT(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UPPROT_SHIFT)) & S50_ELS_KS0_KS0_UPPROT_MASK)
61749 /*! @} */
61750 
61751 /*! @name ELS_KS1 - Status Register */
61752 /*! @{ */
61753 
61754 #define S50_ELS_KS1_KS1_KSIZE_MASK               (0x3U)
61755 #define S50_ELS_KS1_KS1_KSIZE_SHIFT              (0U)
61756 /*! KS1_KSIZE
61757  *  0b00..128
61758  *  0b01..256
61759  */
61760 #define S50_ELS_KS1_KS1_KSIZE(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_KSIZE_SHIFT)) & S50_ELS_KS1_KS1_KSIZE_MASK)
61761 
61762 #define S50_ELS_KS1_KS1_KACT_MASK                (0x20U)
61763 #define S50_ELS_KS1_KS1_KACT_SHIFT               (5U)
61764 #define S50_ELS_KS1_KS1_KACT(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_KACT_SHIFT)) & S50_ELS_KS1_KS1_KACT_MASK)
61765 
61766 #define S50_ELS_KS1_KS1_KBASE_MASK               (0x40U)
61767 #define S50_ELS_KS1_KS1_KBASE_SHIFT              (6U)
61768 #define S50_ELS_KS1_KS1_KBASE(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_KBASE_SHIFT)) & S50_ELS_KS1_KS1_KBASE_MASK)
61769 
61770 #define S50_ELS_KS1_KS1_FGP_MASK                 (0x80U)
61771 #define S50_ELS_KS1_KS1_FGP_SHIFT                (7U)
61772 #define S50_ELS_KS1_KS1_FGP(x)                   (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_FGP_SHIFT)) & S50_ELS_KS1_KS1_FGP_MASK)
61773 
61774 #define S50_ELS_KS1_KS1_FRTN_MASK                (0x100U)
61775 #define S50_ELS_KS1_KS1_FRTN_SHIFT               (8U)
61776 #define S50_ELS_KS1_KS1_FRTN(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_FRTN_SHIFT)) & S50_ELS_KS1_KS1_FRTN_MASK)
61777 
61778 #define S50_ELS_KS1_KS1_FHWO_MASK                (0x200U)
61779 #define S50_ELS_KS1_KS1_FHWO_SHIFT               (9U)
61780 #define S50_ELS_KS1_KS1_FHWO(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_FHWO_SHIFT)) & S50_ELS_KS1_KS1_FHWO_MASK)
61781 
61782 #define S50_ELS_KS1_KS1_UKPUK_MASK               (0x800U)
61783 #define S50_ELS_KS1_KS1_UKPUK_SHIFT              (11U)
61784 #define S50_ELS_KS1_KS1_UKPUK(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UKPUK_SHIFT)) & S50_ELS_KS1_KS1_UKPUK_MASK)
61785 
61786 #define S50_ELS_KS1_KS1_UTECDH_MASK              (0x1000U)
61787 #define S50_ELS_KS1_KS1_UTECDH_SHIFT             (12U)
61788 #define S50_ELS_KS1_KS1_UTECDH(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UTECDH_SHIFT)) & S50_ELS_KS1_KS1_UTECDH_MASK)
61789 
61790 #define S50_ELS_KS1_KS1_UCMAC_MASK               (0x2000U)
61791 #define S50_ELS_KS1_KS1_UCMAC_SHIFT              (13U)
61792 #define S50_ELS_KS1_KS1_UCMAC(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UCMAC_SHIFT)) & S50_ELS_KS1_KS1_UCMAC_MASK)
61793 
61794 #define S50_ELS_KS1_KS1_UKSK_MASK                (0x4000U)
61795 #define S50_ELS_KS1_KS1_UKSK_SHIFT               (14U)
61796 #define S50_ELS_KS1_KS1_UKSK(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UKSK_SHIFT)) & S50_ELS_KS1_KS1_UKSK_MASK)
61797 
61798 #define S50_ELS_KS1_KS1_URTF_MASK                (0x8000U)
61799 #define S50_ELS_KS1_KS1_URTF_SHIFT               (15U)
61800 #define S50_ELS_KS1_KS1_URTF(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_URTF_SHIFT)) & S50_ELS_KS1_KS1_URTF_MASK)
61801 
61802 #define S50_ELS_KS1_KS1_UCKDF_MASK               (0x10000U)
61803 #define S50_ELS_KS1_KS1_UCKDF_SHIFT              (16U)
61804 #define S50_ELS_KS1_KS1_UCKDF(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UCKDF_SHIFT)) & S50_ELS_KS1_KS1_UCKDF_MASK)
61805 
61806 #define S50_ELS_KS1_KS1_UHKDF_MASK               (0x20000U)
61807 #define S50_ELS_KS1_KS1_UHKDF_SHIFT              (17U)
61808 #define S50_ELS_KS1_KS1_UHKDF(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UHKDF_SHIFT)) & S50_ELS_KS1_KS1_UHKDF_MASK)
61809 
61810 #define S50_ELS_KS1_KS1_UECSG_MASK               (0x40000U)
61811 #define S50_ELS_KS1_KS1_UECSG_SHIFT              (18U)
61812 #define S50_ELS_KS1_KS1_UECSG(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UECSG_SHIFT)) & S50_ELS_KS1_KS1_UECSG_MASK)
61813 
61814 #define S50_ELS_KS1_KS1_UECDH_MASK               (0x80000U)
61815 #define S50_ELS_KS1_KS1_UECDH_SHIFT              (19U)
61816 #define S50_ELS_KS1_KS1_UECDH(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UECDH_SHIFT)) & S50_ELS_KS1_KS1_UECDH_MASK)
61817 
61818 #define S50_ELS_KS1_KS1_UAES_MASK                (0x100000U)
61819 #define S50_ELS_KS1_KS1_UAES_SHIFT               (20U)
61820 #define S50_ELS_KS1_KS1_UAES(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UAES_SHIFT)) & S50_ELS_KS1_KS1_UAES_MASK)
61821 
61822 #define S50_ELS_KS1_KS1_UHMAC_MASK               (0x200000U)
61823 #define S50_ELS_KS1_KS1_UHMAC_SHIFT              (21U)
61824 #define S50_ELS_KS1_KS1_UHMAC(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UHMAC_SHIFT)) & S50_ELS_KS1_KS1_UHMAC_MASK)
61825 
61826 #define S50_ELS_KS1_KS1_UKWK_MASK                (0x400000U)
61827 #define S50_ELS_KS1_KS1_UKWK_SHIFT               (22U)
61828 #define S50_ELS_KS1_KS1_UKWK(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UKWK_SHIFT)) & S50_ELS_KS1_KS1_UKWK_MASK)
61829 
61830 #define S50_ELS_KS1_KS1_UKUOK_MASK               (0x800000U)
61831 #define S50_ELS_KS1_KS1_UKUOK_SHIFT              (23U)
61832 #define S50_ELS_KS1_KS1_UKUOK(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UKUOK_SHIFT)) & S50_ELS_KS1_KS1_UKUOK_MASK)
61833 
61834 #define S50_ELS_KS1_KS1_UTLSPMS_MASK             (0x1000000U)
61835 #define S50_ELS_KS1_KS1_UTLSPMS_SHIFT            (24U)
61836 #define S50_ELS_KS1_KS1_UTLSPMS(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UTLSPMS_SHIFT)) & S50_ELS_KS1_KS1_UTLSPMS_MASK)
61837 
61838 #define S50_ELS_KS1_KS1_UTLSMS_MASK              (0x2000000U)
61839 #define S50_ELS_KS1_KS1_UTLSMS_SHIFT             (25U)
61840 #define S50_ELS_KS1_KS1_UTLSMS(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UTLSMS_SHIFT)) & S50_ELS_KS1_KS1_UTLSMS_MASK)
61841 
61842 #define S50_ELS_KS1_KS1_UKGSRC_MASK              (0x4000000U)
61843 #define S50_ELS_KS1_KS1_UKGSRC_SHIFT             (26U)
61844 #define S50_ELS_KS1_KS1_UKGSRC(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UKGSRC_SHIFT)) & S50_ELS_KS1_KS1_UKGSRC_MASK)
61845 
61846 #define S50_ELS_KS1_KS1_UHWO_MASK                (0x8000000U)
61847 #define S50_ELS_KS1_KS1_UHWO_SHIFT               (27U)
61848 #define S50_ELS_KS1_KS1_UHWO(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UHWO_SHIFT)) & S50_ELS_KS1_KS1_UHWO_MASK)
61849 
61850 #define S50_ELS_KS1_KS1_UWRPOK_MASK              (0x10000000U)
61851 #define S50_ELS_KS1_KS1_UWRPOK_SHIFT             (28U)
61852 #define S50_ELS_KS1_KS1_UWRPOK(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UWRPOK_SHIFT)) & S50_ELS_KS1_KS1_UWRPOK_MASK)
61853 
61854 #define S50_ELS_KS1_KS1_UDUK_MASK                (0x20000000U)
61855 #define S50_ELS_KS1_KS1_UDUK_SHIFT               (29U)
61856 #define S50_ELS_KS1_KS1_UDUK(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UDUK_SHIFT)) & S50_ELS_KS1_KS1_UDUK_MASK)
61857 
61858 #define S50_ELS_KS1_KS1_UPPROT_MASK              (0xC0000000U)
61859 #define S50_ELS_KS1_KS1_UPPROT_SHIFT             (30U)
61860 #define S50_ELS_KS1_KS1_UPPROT(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UPPROT_SHIFT)) & S50_ELS_KS1_KS1_UPPROT_MASK)
61861 /*! @} */
61862 
61863 /*! @name ELS_KS2 - Status Register */
61864 /*! @{ */
61865 
61866 #define S50_ELS_KS2_KS2_KSIZE_MASK               (0x3U)
61867 #define S50_ELS_KS2_KS2_KSIZE_SHIFT              (0U)
61868 /*! KS2_KSIZE
61869  *  0b00..128
61870  *  0b01..256
61871  */
61872 #define S50_ELS_KS2_KS2_KSIZE(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_KSIZE_SHIFT)) & S50_ELS_KS2_KS2_KSIZE_MASK)
61873 
61874 #define S50_ELS_KS2_KS2_KACT_MASK                (0x20U)
61875 #define S50_ELS_KS2_KS2_KACT_SHIFT               (5U)
61876 #define S50_ELS_KS2_KS2_KACT(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_KACT_SHIFT)) & S50_ELS_KS2_KS2_KACT_MASK)
61877 
61878 #define S50_ELS_KS2_KS2_KBASE_MASK               (0x40U)
61879 #define S50_ELS_KS2_KS2_KBASE_SHIFT              (6U)
61880 #define S50_ELS_KS2_KS2_KBASE(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_KBASE_SHIFT)) & S50_ELS_KS2_KS2_KBASE_MASK)
61881 
61882 #define S50_ELS_KS2_KS2_FGP_MASK                 (0x80U)
61883 #define S50_ELS_KS2_KS2_FGP_SHIFT                (7U)
61884 #define S50_ELS_KS2_KS2_FGP(x)                   (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_FGP_SHIFT)) & S50_ELS_KS2_KS2_FGP_MASK)
61885 
61886 #define S50_ELS_KS2_KS2_FRTN_MASK                (0x100U)
61887 #define S50_ELS_KS2_KS2_FRTN_SHIFT               (8U)
61888 #define S50_ELS_KS2_KS2_FRTN(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_FRTN_SHIFT)) & S50_ELS_KS2_KS2_FRTN_MASK)
61889 
61890 #define S50_ELS_KS2_KS2_FHWO_MASK                (0x200U)
61891 #define S50_ELS_KS2_KS2_FHWO_SHIFT               (9U)
61892 #define S50_ELS_KS2_KS2_FHWO(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_FHWO_SHIFT)) & S50_ELS_KS2_KS2_FHWO_MASK)
61893 
61894 #define S50_ELS_KS2_KS2_UKPUK_MASK               (0x800U)
61895 #define S50_ELS_KS2_KS2_UKPUK_SHIFT              (11U)
61896 #define S50_ELS_KS2_KS2_UKPUK(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UKPUK_SHIFT)) & S50_ELS_KS2_KS2_UKPUK_MASK)
61897 
61898 #define S50_ELS_KS2_KS2_UTECDH_MASK              (0x1000U)
61899 #define S50_ELS_KS2_KS2_UTECDH_SHIFT             (12U)
61900 #define S50_ELS_KS2_KS2_UTECDH(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UTECDH_SHIFT)) & S50_ELS_KS2_KS2_UTECDH_MASK)
61901 
61902 #define S50_ELS_KS2_KS2_UCMAC_MASK               (0x2000U)
61903 #define S50_ELS_KS2_KS2_UCMAC_SHIFT              (13U)
61904 #define S50_ELS_KS2_KS2_UCMAC(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UCMAC_SHIFT)) & S50_ELS_KS2_KS2_UCMAC_MASK)
61905 
61906 #define S50_ELS_KS2_KS2_UKSK_MASK                (0x4000U)
61907 #define S50_ELS_KS2_KS2_UKSK_SHIFT               (14U)
61908 #define S50_ELS_KS2_KS2_UKSK(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UKSK_SHIFT)) & S50_ELS_KS2_KS2_UKSK_MASK)
61909 
61910 #define S50_ELS_KS2_KS2_URTF_MASK                (0x8000U)
61911 #define S50_ELS_KS2_KS2_URTF_SHIFT               (15U)
61912 #define S50_ELS_KS2_KS2_URTF(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_URTF_SHIFT)) & S50_ELS_KS2_KS2_URTF_MASK)
61913 
61914 #define S50_ELS_KS2_KS2_UCKDF_MASK               (0x10000U)
61915 #define S50_ELS_KS2_KS2_UCKDF_SHIFT              (16U)
61916 #define S50_ELS_KS2_KS2_UCKDF(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UCKDF_SHIFT)) & S50_ELS_KS2_KS2_UCKDF_MASK)
61917 
61918 #define S50_ELS_KS2_KS2_UHKDF_MASK               (0x20000U)
61919 #define S50_ELS_KS2_KS2_UHKDF_SHIFT              (17U)
61920 #define S50_ELS_KS2_KS2_UHKDF(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UHKDF_SHIFT)) & S50_ELS_KS2_KS2_UHKDF_MASK)
61921 
61922 #define S50_ELS_KS2_KS2_UECSG_MASK               (0x40000U)
61923 #define S50_ELS_KS2_KS2_UECSG_SHIFT              (18U)
61924 #define S50_ELS_KS2_KS2_UECSG(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UECSG_SHIFT)) & S50_ELS_KS2_KS2_UECSG_MASK)
61925 
61926 #define S50_ELS_KS2_KS2_UECDH_MASK               (0x80000U)
61927 #define S50_ELS_KS2_KS2_UECDH_SHIFT              (19U)
61928 #define S50_ELS_KS2_KS2_UECDH(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UECDH_SHIFT)) & S50_ELS_KS2_KS2_UECDH_MASK)
61929 
61930 #define S50_ELS_KS2_KS2_UAES_MASK                (0x100000U)
61931 #define S50_ELS_KS2_KS2_UAES_SHIFT               (20U)
61932 #define S50_ELS_KS2_KS2_UAES(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UAES_SHIFT)) & S50_ELS_KS2_KS2_UAES_MASK)
61933 
61934 #define S50_ELS_KS2_KS2_UHMAC_MASK               (0x200000U)
61935 #define S50_ELS_KS2_KS2_UHMAC_SHIFT              (21U)
61936 #define S50_ELS_KS2_KS2_UHMAC(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UHMAC_SHIFT)) & S50_ELS_KS2_KS2_UHMAC_MASK)
61937 
61938 #define S50_ELS_KS2_KS2_UKWK_MASK                (0x400000U)
61939 #define S50_ELS_KS2_KS2_UKWK_SHIFT               (22U)
61940 #define S50_ELS_KS2_KS2_UKWK(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UKWK_SHIFT)) & S50_ELS_KS2_KS2_UKWK_MASK)
61941 
61942 #define S50_ELS_KS2_KS2_UKUOK_MASK               (0x800000U)
61943 #define S50_ELS_KS2_KS2_UKUOK_SHIFT              (23U)
61944 #define S50_ELS_KS2_KS2_UKUOK(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UKUOK_SHIFT)) & S50_ELS_KS2_KS2_UKUOK_MASK)
61945 
61946 #define S50_ELS_KS2_KS2_UTLSPMS_MASK             (0x1000000U)
61947 #define S50_ELS_KS2_KS2_UTLSPMS_SHIFT            (24U)
61948 #define S50_ELS_KS2_KS2_UTLSPMS(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UTLSPMS_SHIFT)) & S50_ELS_KS2_KS2_UTLSPMS_MASK)
61949 
61950 #define S50_ELS_KS2_KS2_UTLSMS_MASK              (0x2000000U)
61951 #define S50_ELS_KS2_KS2_UTLSMS_SHIFT             (25U)
61952 #define S50_ELS_KS2_KS2_UTLSMS(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UTLSMS_SHIFT)) & S50_ELS_KS2_KS2_UTLSMS_MASK)
61953 
61954 #define S50_ELS_KS2_KS2_UKGSRC_MASK              (0x4000000U)
61955 #define S50_ELS_KS2_KS2_UKGSRC_SHIFT             (26U)
61956 #define S50_ELS_KS2_KS2_UKGSRC(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UKGSRC_SHIFT)) & S50_ELS_KS2_KS2_UKGSRC_MASK)
61957 
61958 #define S50_ELS_KS2_KS2_UHWO_MASK                (0x8000000U)
61959 #define S50_ELS_KS2_KS2_UHWO_SHIFT               (27U)
61960 #define S50_ELS_KS2_KS2_UHWO(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UHWO_SHIFT)) & S50_ELS_KS2_KS2_UHWO_MASK)
61961 
61962 #define S50_ELS_KS2_KS2_UWRPOK_MASK              (0x10000000U)
61963 #define S50_ELS_KS2_KS2_UWRPOK_SHIFT             (28U)
61964 #define S50_ELS_KS2_KS2_UWRPOK(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UWRPOK_SHIFT)) & S50_ELS_KS2_KS2_UWRPOK_MASK)
61965 
61966 #define S50_ELS_KS2_KS2_UDUK_MASK                (0x20000000U)
61967 #define S50_ELS_KS2_KS2_UDUK_SHIFT               (29U)
61968 #define S50_ELS_KS2_KS2_UDUK(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UDUK_SHIFT)) & S50_ELS_KS2_KS2_UDUK_MASK)
61969 
61970 #define S50_ELS_KS2_KS2_UPPROT_MASK              (0xC0000000U)
61971 #define S50_ELS_KS2_KS2_UPPROT_SHIFT             (30U)
61972 #define S50_ELS_KS2_KS2_UPPROT(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UPPROT_SHIFT)) & S50_ELS_KS2_KS2_UPPROT_MASK)
61973 /*! @} */
61974 
61975 /*! @name ELS_KS3 - Status Register */
61976 /*! @{ */
61977 
61978 #define S50_ELS_KS3_KS3_KSIZE_MASK               (0x3U)
61979 #define S50_ELS_KS3_KS3_KSIZE_SHIFT              (0U)
61980 /*! KS3_KSIZE
61981  *  0b00..128
61982  *  0b01..256
61983  */
61984 #define S50_ELS_KS3_KS3_KSIZE(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_KSIZE_SHIFT)) & S50_ELS_KS3_KS3_KSIZE_MASK)
61985 
61986 #define S50_ELS_KS3_KS3_KACT_MASK                (0x20U)
61987 #define S50_ELS_KS3_KS3_KACT_SHIFT               (5U)
61988 #define S50_ELS_KS3_KS3_KACT(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_KACT_SHIFT)) & S50_ELS_KS3_KS3_KACT_MASK)
61989 
61990 #define S50_ELS_KS3_KS3_KBASE_MASK               (0x40U)
61991 #define S50_ELS_KS3_KS3_KBASE_SHIFT              (6U)
61992 #define S50_ELS_KS3_KS3_KBASE(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_KBASE_SHIFT)) & S50_ELS_KS3_KS3_KBASE_MASK)
61993 
61994 #define S50_ELS_KS3_KS3_FGP_MASK                 (0x80U)
61995 #define S50_ELS_KS3_KS3_FGP_SHIFT                (7U)
61996 #define S50_ELS_KS3_KS3_FGP(x)                   (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_FGP_SHIFT)) & S50_ELS_KS3_KS3_FGP_MASK)
61997 
61998 #define S50_ELS_KS3_KS3_FRTN_MASK                (0x100U)
61999 #define S50_ELS_KS3_KS3_FRTN_SHIFT               (8U)
62000 #define S50_ELS_KS3_KS3_FRTN(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_FRTN_SHIFT)) & S50_ELS_KS3_KS3_FRTN_MASK)
62001 
62002 #define S50_ELS_KS3_KS3_FHWO_MASK                (0x200U)
62003 #define S50_ELS_KS3_KS3_FHWO_SHIFT               (9U)
62004 #define S50_ELS_KS3_KS3_FHWO(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_FHWO_SHIFT)) & S50_ELS_KS3_KS3_FHWO_MASK)
62005 
62006 #define S50_ELS_KS3_KS3_UKPUK_MASK               (0x800U)
62007 #define S50_ELS_KS3_KS3_UKPUK_SHIFT              (11U)
62008 #define S50_ELS_KS3_KS3_UKPUK(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UKPUK_SHIFT)) & S50_ELS_KS3_KS3_UKPUK_MASK)
62009 
62010 #define S50_ELS_KS3_KS3_UTECDH_MASK              (0x1000U)
62011 #define S50_ELS_KS3_KS3_UTECDH_SHIFT             (12U)
62012 #define S50_ELS_KS3_KS3_UTECDH(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UTECDH_SHIFT)) & S50_ELS_KS3_KS3_UTECDH_MASK)
62013 
62014 #define S50_ELS_KS3_KS3_UCMAC_MASK               (0x2000U)
62015 #define S50_ELS_KS3_KS3_UCMAC_SHIFT              (13U)
62016 #define S50_ELS_KS3_KS3_UCMAC(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UCMAC_SHIFT)) & S50_ELS_KS3_KS3_UCMAC_MASK)
62017 
62018 #define S50_ELS_KS3_KS3_UKSK_MASK                (0x4000U)
62019 #define S50_ELS_KS3_KS3_UKSK_SHIFT               (14U)
62020 #define S50_ELS_KS3_KS3_UKSK(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UKSK_SHIFT)) & S50_ELS_KS3_KS3_UKSK_MASK)
62021 
62022 #define S50_ELS_KS3_KS3_URTF_MASK                (0x8000U)
62023 #define S50_ELS_KS3_KS3_URTF_SHIFT               (15U)
62024 #define S50_ELS_KS3_KS3_URTF(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_URTF_SHIFT)) & S50_ELS_KS3_KS3_URTF_MASK)
62025 
62026 #define S50_ELS_KS3_KS3_UCKDF_MASK               (0x10000U)
62027 #define S50_ELS_KS3_KS3_UCKDF_SHIFT              (16U)
62028 #define S50_ELS_KS3_KS3_UCKDF(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UCKDF_SHIFT)) & S50_ELS_KS3_KS3_UCKDF_MASK)
62029 
62030 #define S50_ELS_KS3_KS3_UHKDF_MASK               (0x20000U)
62031 #define S50_ELS_KS3_KS3_UHKDF_SHIFT              (17U)
62032 #define S50_ELS_KS3_KS3_UHKDF(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UHKDF_SHIFT)) & S50_ELS_KS3_KS3_UHKDF_MASK)
62033 
62034 #define S50_ELS_KS3_KS3_UECSG_MASK               (0x40000U)
62035 #define S50_ELS_KS3_KS3_UECSG_SHIFT              (18U)
62036 #define S50_ELS_KS3_KS3_UECSG(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UECSG_SHIFT)) & S50_ELS_KS3_KS3_UECSG_MASK)
62037 
62038 #define S50_ELS_KS3_KS3_UECDH_MASK               (0x80000U)
62039 #define S50_ELS_KS3_KS3_UECDH_SHIFT              (19U)
62040 #define S50_ELS_KS3_KS3_UECDH(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UECDH_SHIFT)) & S50_ELS_KS3_KS3_UECDH_MASK)
62041 
62042 #define S50_ELS_KS3_KS3_UAES_MASK                (0x100000U)
62043 #define S50_ELS_KS3_KS3_UAES_SHIFT               (20U)
62044 #define S50_ELS_KS3_KS3_UAES(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UAES_SHIFT)) & S50_ELS_KS3_KS3_UAES_MASK)
62045 
62046 #define S50_ELS_KS3_KS3_UHMAC_MASK               (0x200000U)
62047 #define S50_ELS_KS3_KS3_UHMAC_SHIFT              (21U)
62048 #define S50_ELS_KS3_KS3_UHMAC(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UHMAC_SHIFT)) & S50_ELS_KS3_KS3_UHMAC_MASK)
62049 
62050 #define S50_ELS_KS3_KS3_UKWK_MASK                (0x400000U)
62051 #define S50_ELS_KS3_KS3_UKWK_SHIFT               (22U)
62052 #define S50_ELS_KS3_KS3_UKWK(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UKWK_SHIFT)) & S50_ELS_KS3_KS3_UKWK_MASK)
62053 
62054 #define S50_ELS_KS3_KS3_UKUOK_MASK               (0x800000U)
62055 #define S50_ELS_KS3_KS3_UKUOK_SHIFT              (23U)
62056 #define S50_ELS_KS3_KS3_UKUOK(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UKUOK_SHIFT)) & S50_ELS_KS3_KS3_UKUOK_MASK)
62057 
62058 #define S50_ELS_KS3_KS3_UTLSPMS_MASK             (0x1000000U)
62059 #define S50_ELS_KS3_KS3_UTLSPMS_SHIFT            (24U)
62060 #define S50_ELS_KS3_KS3_UTLSPMS(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UTLSPMS_SHIFT)) & S50_ELS_KS3_KS3_UTLSPMS_MASK)
62061 
62062 #define S50_ELS_KS3_KS3_UTLSMS_MASK              (0x2000000U)
62063 #define S50_ELS_KS3_KS3_UTLSMS_SHIFT             (25U)
62064 #define S50_ELS_KS3_KS3_UTLSMS(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UTLSMS_SHIFT)) & S50_ELS_KS3_KS3_UTLSMS_MASK)
62065 
62066 #define S50_ELS_KS3_KS3_UKGSRC_MASK              (0x4000000U)
62067 #define S50_ELS_KS3_KS3_UKGSRC_SHIFT             (26U)
62068 #define S50_ELS_KS3_KS3_UKGSRC(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UKGSRC_SHIFT)) & S50_ELS_KS3_KS3_UKGSRC_MASK)
62069 
62070 #define S50_ELS_KS3_KS3_UHWO_MASK                (0x8000000U)
62071 #define S50_ELS_KS3_KS3_UHWO_SHIFT               (27U)
62072 #define S50_ELS_KS3_KS3_UHWO(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UHWO_SHIFT)) & S50_ELS_KS3_KS3_UHWO_MASK)
62073 
62074 #define S50_ELS_KS3_KS3_UWRPOK_MASK              (0x10000000U)
62075 #define S50_ELS_KS3_KS3_UWRPOK_SHIFT             (28U)
62076 #define S50_ELS_KS3_KS3_UWRPOK(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UWRPOK_SHIFT)) & S50_ELS_KS3_KS3_UWRPOK_MASK)
62077 
62078 #define S50_ELS_KS3_KS3_UDUK_MASK                (0x20000000U)
62079 #define S50_ELS_KS3_KS3_UDUK_SHIFT               (29U)
62080 #define S50_ELS_KS3_KS3_UDUK(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UDUK_SHIFT)) & S50_ELS_KS3_KS3_UDUK_MASK)
62081 
62082 #define S50_ELS_KS3_KS3_UPPROT_MASK              (0xC0000000U)
62083 #define S50_ELS_KS3_KS3_UPPROT_SHIFT             (30U)
62084 #define S50_ELS_KS3_KS3_UPPROT(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UPPROT_SHIFT)) & S50_ELS_KS3_KS3_UPPROT_MASK)
62085 /*! @} */
62086 
62087 /*! @name ELS_KS4 - Status Register */
62088 /*! @{ */
62089 
62090 #define S50_ELS_KS4_KS4_KSIZE_MASK               (0x3U)
62091 #define S50_ELS_KS4_KS4_KSIZE_SHIFT              (0U)
62092 /*! KS4_KSIZE
62093  *  0b00..128
62094  *  0b01..256
62095  */
62096 #define S50_ELS_KS4_KS4_KSIZE(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_KSIZE_SHIFT)) & S50_ELS_KS4_KS4_KSIZE_MASK)
62097 
62098 #define S50_ELS_KS4_KS4_KACT_MASK                (0x20U)
62099 #define S50_ELS_KS4_KS4_KACT_SHIFT               (5U)
62100 #define S50_ELS_KS4_KS4_KACT(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_KACT_SHIFT)) & S50_ELS_KS4_KS4_KACT_MASK)
62101 
62102 #define S50_ELS_KS4_KS4_KBASE_MASK               (0x40U)
62103 #define S50_ELS_KS4_KS4_KBASE_SHIFT              (6U)
62104 #define S50_ELS_KS4_KS4_KBASE(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_KBASE_SHIFT)) & S50_ELS_KS4_KS4_KBASE_MASK)
62105 
62106 #define S50_ELS_KS4_KS4_FGP_MASK                 (0x80U)
62107 #define S50_ELS_KS4_KS4_FGP_SHIFT                (7U)
62108 #define S50_ELS_KS4_KS4_FGP(x)                   (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_FGP_SHIFT)) & S50_ELS_KS4_KS4_FGP_MASK)
62109 
62110 #define S50_ELS_KS4_KS4_FRTN_MASK                (0x100U)
62111 #define S50_ELS_KS4_KS4_FRTN_SHIFT               (8U)
62112 #define S50_ELS_KS4_KS4_FRTN(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_FRTN_SHIFT)) & S50_ELS_KS4_KS4_FRTN_MASK)
62113 
62114 #define S50_ELS_KS4_KS4_FHWO_MASK                (0x200U)
62115 #define S50_ELS_KS4_KS4_FHWO_SHIFT               (9U)
62116 #define S50_ELS_KS4_KS4_FHWO(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_FHWO_SHIFT)) & S50_ELS_KS4_KS4_FHWO_MASK)
62117 
62118 #define S50_ELS_KS4_KS4_UKPUK_MASK               (0x800U)
62119 #define S50_ELS_KS4_KS4_UKPUK_SHIFT              (11U)
62120 #define S50_ELS_KS4_KS4_UKPUK(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UKPUK_SHIFT)) & S50_ELS_KS4_KS4_UKPUK_MASK)
62121 
62122 #define S50_ELS_KS4_KS4_UTECDH_MASK              (0x1000U)
62123 #define S50_ELS_KS4_KS4_UTECDH_SHIFT             (12U)
62124 #define S50_ELS_KS4_KS4_UTECDH(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UTECDH_SHIFT)) & S50_ELS_KS4_KS4_UTECDH_MASK)
62125 
62126 #define S50_ELS_KS4_KS4_UCMAC_MASK               (0x2000U)
62127 #define S50_ELS_KS4_KS4_UCMAC_SHIFT              (13U)
62128 #define S50_ELS_KS4_KS4_UCMAC(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UCMAC_SHIFT)) & S50_ELS_KS4_KS4_UCMAC_MASK)
62129 
62130 #define S50_ELS_KS4_KS4_UKSK_MASK                (0x4000U)
62131 #define S50_ELS_KS4_KS4_UKSK_SHIFT               (14U)
62132 #define S50_ELS_KS4_KS4_UKSK(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UKSK_SHIFT)) & S50_ELS_KS4_KS4_UKSK_MASK)
62133 
62134 #define S50_ELS_KS4_KS4_URTF_MASK                (0x8000U)
62135 #define S50_ELS_KS4_KS4_URTF_SHIFT               (15U)
62136 #define S50_ELS_KS4_KS4_URTF(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_URTF_SHIFT)) & S50_ELS_KS4_KS4_URTF_MASK)
62137 
62138 #define S50_ELS_KS4_KS4_UCKDF_MASK               (0x10000U)
62139 #define S50_ELS_KS4_KS4_UCKDF_SHIFT              (16U)
62140 #define S50_ELS_KS4_KS4_UCKDF(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UCKDF_SHIFT)) & S50_ELS_KS4_KS4_UCKDF_MASK)
62141 
62142 #define S50_ELS_KS4_KS4_UHKDF_MASK               (0x20000U)
62143 #define S50_ELS_KS4_KS4_UHKDF_SHIFT              (17U)
62144 #define S50_ELS_KS4_KS4_UHKDF(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UHKDF_SHIFT)) & S50_ELS_KS4_KS4_UHKDF_MASK)
62145 
62146 #define S50_ELS_KS4_KS4_UECSG_MASK               (0x40000U)
62147 #define S50_ELS_KS4_KS4_UECSG_SHIFT              (18U)
62148 #define S50_ELS_KS4_KS4_UECSG(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UECSG_SHIFT)) & S50_ELS_KS4_KS4_UECSG_MASK)
62149 
62150 #define S50_ELS_KS4_KS4_UECDH_MASK               (0x80000U)
62151 #define S50_ELS_KS4_KS4_UECDH_SHIFT              (19U)
62152 #define S50_ELS_KS4_KS4_UECDH(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UECDH_SHIFT)) & S50_ELS_KS4_KS4_UECDH_MASK)
62153 
62154 #define S50_ELS_KS4_KS4_UAES_MASK                (0x100000U)
62155 #define S50_ELS_KS4_KS4_UAES_SHIFT               (20U)
62156 #define S50_ELS_KS4_KS4_UAES(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UAES_SHIFT)) & S50_ELS_KS4_KS4_UAES_MASK)
62157 
62158 #define S50_ELS_KS4_KS4_UHMAC_MASK               (0x200000U)
62159 #define S50_ELS_KS4_KS4_UHMAC_SHIFT              (21U)
62160 #define S50_ELS_KS4_KS4_UHMAC(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UHMAC_SHIFT)) & S50_ELS_KS4_KS4_UHMAC_MASK)
62161 
62162 #define S50_ELS_KS4_KS4_UKWK_MASK                (0x400000U)
62163 #define S50_ELS_KS4_KS4_UKWK_SHIFT               (22U)
62164 #define S50_ELS_KS4_KS4_UKWK(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UKWK_SHIFT)) & S50_ELS_KS4_KS4_UKWK_MASK)
62165 
62166 #define S50_ELS_KS4_KS4_UKUOK_MASK               (0x800000U)
62167 #define S50_ELS_KS4_KS4_UKUOK_SHIFT              (23U)
62168 #define S50_ELS_KS4_KS4_UKUOK(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UKUOK_SHIFT)) & S50_ELS_KS4_KS4_UKUOK_MASK)
62169 
62170 #define S50_ELS_KS4_KS4_UTLSPMS_MASK             (0x1000000U)
62171 #define S50_ELS_KS4_KS4_UTLSPMS_SHIFT            (24U)
62172 #define S50_ELS_KS4_KS4_UTLSPMS(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UTLSPMS_SHIFT)) & S50_ELS_KS4_KS4_UTLSPMS_MASK)
62173 
62174 #define S50_ELS_KS4_KS4_UTLSMS_MASK              (0x2000000U)
62175 #define S50_ELS_KS4_KS4_UTLSMS_SHIFT             (25U)
62176 #define S50_ELS_KS4_KS4_UTLSMS(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UTLSMS_SHIFT)) & S50_ELS_KS4_KS4_UTLSMS_MASK)
62177 
62178 #define S50_ELS_KS4_KS4_UKGSRC_MASK              (0x4000000U)
62179 #define S50_ELS_KS4_KS4_UKGSRC_SHIFT             (26U)
62180 #define S50_ELS_KS4_KS4_UKGSRC(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UKGSRC_SHIFT)) & S50_ELS_KS4_KS4_UKGSRC_MASK)
62181 
62182 #define S50_ELS_KS4_KS4_UHWO_MASK                (0x8000000U)
62183 #define S50_ELS_KS4_KS4_UHWO_SHIFT               (27U)
62184 #define S50_ELS_KS4_KS4_UHWO(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UHWO_SHIFT)) & S50_ELS_KS4_KS4_UHWO_MASK)
62185 
62186 #define S50_ELS_KS4_KS4_UWRPOK_MASK              (0x10000000U)
62187 #define S50_ELS_KS4_KS4_UWRPOK_SHIFT             (28U)
62188 #define S50_ELS_KS4_KS4_UWRPOK(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UWRPOK_SHIFT)) & S50_ELS_KS4_KS4_UWRPOK_MASK)
62189 
62190 #define S50_ELS_KS4_KS4_UDUK_MASK                (0x20000000U)
62191 #define S50_ELS_KS4_KS4_UDUK_SHIFT               (29U)
62192 #define S50_ELS_KS4_KS4_UDUK(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UDUK_SHIFT)) & S50_ELS_KS4_KS4_UDUK_MASK)
62193 
62194 #define S50_ELS_KS4_KS4_UPPROT_MASK              (0xC0000000U)
62195 #define S50_ELS_KS4_KS4_UPPROT_SHIFT             (30U)
62196 #define S50_ELS_KS4_KS4_UPPROT(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UPPROT_SHIFT)) & S50_ELS_KS4_KS4_UPPROT_MASK)
62197 /*! @} */
62198 
62199 /*! @name ELS_KS5 - Status Register */
62200 /*! @{ */
62201 
62202 #define S50_ELS_KS5_KS5_KSIZE_MASK               (0x3U)
62203 #define S50_ELS_KS5_KS5_KSIZE_SHIFT              (0U)
62204 /*! KS5_KSIZE
62205  *  0b00..128
62206  *  0b01..256
62207  */
62208 #define S50_ELS_KS5_KS5_KSIZE(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_KSIZE_SHIFT)) & S50_ELS_KS5_KS5_KSIZE_MASK)
62209 
62210 #define S50_ELS_KS5_KS5_KACT_MASK                (0x20U)
62211 #define S50_ELS_KS5_KS5_KACT_SHIFT               (5U)
62212 #define S50_ELS_KS5_KS5_KACT(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_KACT_SHIFT)) & S50_ELS_KS5_KS5_KACT_MASK)
62213 
62214 #define S50_ELS_KS5_KS5_KBASE_MASK               (0x40U)
62215 #define S50_ELS_KS5_KS5_KBASE_SHIFT              (6U)
62216 #define S50_ELS_KS5_KS5_KBASE(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_KBASE_SHIFT)) & S50_ELS_KS5_KS5_KBASE_MASK)
62217 
62218 #define S50_ELS_KS5_KS5_FGP_MASK                 (0x80U)
62219 #define S50_ELS_KS5_KS5_FGP_SHIFT                (7U)
62220 #define S50_ELS_KS5_KS5_FGP(x)                   (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_FGP_SHIFT)) & S50_ELS_KS5_KS5_FGP_MASK)
62221 
62222 #define S50_ELS_KS5_KS5_FRTN_MASK                (0x100U)
62223 #define S50_ELS_KS5_KS5_FRTN_SHIFT               (8U)
62224 #define S50_ELS_KS5_KS5_FRTN(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_FRTN_SHIFT)) & S50_ELS_KS5_KS5_FRTN_MASK)
62225 
62226 #define S50_ELS_KS5_KS5_FHWO_MASK                (0x200U)
62227 #define S50_ELS_KS5_KS5_FHWO_SHIFT               (9U)
62228 #define S50_ELS_KS5_KS5_FHWO(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_FHWO_SHIFT)) & S50_ELS_KS5_KS5_FHWO_MASK)
62229 
62230 #define S50_ELS_KS5_KS5_UKPUK_MASK               (0x800U)
62231 #define S50_ELS_KS5_KS5_UKPUK_SHIFT              (11U)
62232 #define S50_ELS_KS5_KS5_UKPUK(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UKPUK_SHIFT)) & S50_ELS_KS5_KS5_UKPUK_MASK)
62233 
62234 #define S50_ELS_KS5_KS5_UTECDH_MASK              (0x1000U)
62235 #define S50_ELS_KS5_KS5_UTECDH_SHIFT             (12U)
62236 #define S50_ELS_KS5_KS5_UTECDH(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UTECDH_SHIFT)) & S50_ELS_KS5_KS5_UTECDH_MASK)
62237 
62238 #define S50_ELS_KS5_KS5_UCMAC_MASK               (0x2000U)
62239 #define S50_ELS_KS5_KS5_UCMAC_SHIFT              (13U)
62240 #define S50_ELS_KS5_KS5_UCMAC(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UCMAC_SHIFT)) & S50_ELS_KS5_KS5_UCMAC_MASK)
62241 
62242 #define S50_ELS_KS5_KS5_UKSK_MASK                (0x4000U)
62243 #define S50_ELS_KS5_KS5_UKSK_SHIFT               (14U)
62244 #define S50_ELS_KS5_KS5_UKSK(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UKSK_SHIFT)) & S50_ELS_KS5_KS5_UKSK_MASK)
62245 
62246 #define S50_ELS_KS5_KS5_URTF_MASK                (0x8000U)
62247 #define S50_ELS_KS5_KS5_URTF_SHIFT               (15U)
62248 #define S50_ELS_KS5_KS5_URTF(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_URTF_SHIFT)) & S50_ELS_KS5_KS5_URTF_MASK)
62249 
62250 #define S50_ELS_KS5_KS5_UCKDF_MASK               (0x10000U)
62251 #define S50_ELS_KS5_KS5_UCKDF_SHIFT              (16U)
62252 #define S50_ELS_KS5_KS5_UCKDF(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UCKDF_SHIFT)) & S50_ELS_KS5_KS5_UCKDF_MASK)
62253 
62254 #define S50_ELS_KS5_KS5_UHKDF_MASK               (0x20000U)
62255 #define S50_ELS_KS5_KS5_UHKDF_SHIFT              (17U)
62256 #define S50_ELS_KS5_KS5_UHKDF(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UHKDF_SHIFT)) & S50_ELS_KS5_KS5_UHKDF_MASK)
62257 
62258 #define S50_ELS_KS5_KS5_UECSG_MASK               (0x40000U)
62259 #define S50_ELS_KS5_KS5_UECSG_SHIFT              (18U)
62260 #define S50_ELS_KS5_KS5_UECSG(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UECSG_SHIFT)) & S50_ELS_KS5_KS5_UECSG_MASK)
62261 
62262 #define S50_ELS_KS5_KS5_UECDH_MASK               (0x80000U)
62263 #define S50_ELS_KS5_KS5_UECDH_SHIFT              (19U)
62264 #define S50_ELS_KS5_KS5_UECDH(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UECDH_SHIFT)) & S50_ELS_KS5_KS5_UECDH_MASK)
62265 
62266 #define S50_ELS_KS5_KS5_UAES_MASK                (0x100000U)
62267 #define S50_ELS_KS5_KS5_UAES_SHIFT               (20U)
62268 #define S50_ELS_KS5_KS5_UAES(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UAES_SHIFT)) & S50_ELS_KS5_KS5_UAES_MASK)
62269 
62270 #define S50_ELS_KS5_KS5_UHMAC_MASK               (0x200000U)
62271 #define S50_ELS_KS5_KS5_UHMAC_SHIFT              (21U)
62272 #define S50_ELS_KS5_KS5_UHMAC(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UHMAC_SHIFT)) & S50_ELS_KS5_KS5_UHMAC_MASK)
62273 
62274 #define S50_ELS_KS5_KS5_UKWK_MASK                (0x400000U)
62275 #define S50_ELS_KS5_KS5_UKWK_SHIFT               (22U)
62276 #define S50_ELS_KS5_KS5_UKWK(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UKWK_SHIFT)) & S50_ELS_KS5_KS5_UKWK_MASK)
62277 
62278 #define S50_ELS_KS5_KS5_UKUOK_MASK               (0x800000U)
62279 #define S50_ELS_KS5_KS5_UKUOK_SHIFT              (23U)
62280 #define S50_ELS_KS5_KS5_UKUOK(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UKUOK_SHIFT)) & S50_ELS_KS5_KS5_UKUOK_MASK)
62281 
62282 #define S50_ELS_KS5_KS5_UTLSPMS_MASK             (0x1000000U)
62283 #define S50_ELS_KS5_KS5_UTLSPMS_SHIFT            (24U)
62284 #define S50_ELS_KS5_KS5_UTLSPMS(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UTLSPMS_SHIFT)) & S50_ELS_KS5_KS5_UTLSPMS_MASK)
62285 
62286 #define S50_ELS_KS5_KS5_UTLSMS_MASK              (0x2000000U)
62287 #define S50_ELS_KS5_KS5_UTLSMS_SHIFT             (25U)
62288 #define S50_ELS_KS5_KS5_UTLSMS(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UTLSMS_SHIFT)) & S50_ELS_KS5_KS5_UTLSMS_MASK)
62289 
62290 #define S50_ELS_KS5_KS5_UKGSRC_MASK              (0x4000000U)
62291 #define S50_ELS_KS5_KS5_UKGSRC_SHIFT             (26U)
62292 #define S50_ELS_KS5_KS5_UKGSRC(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UKGSRC_SHIFT)) & S50_ELS_KS5_KS5_UKGSRC_MASK)
62293 
62294 #define S50_ELS_KS5_KS5_UHWO_MASK                (0x8000000U)
62295 #define S50_ELS_KS5_KS5_UHWO_SHIFT               (27U)
62296 #define S50_ELS_KS5_KS5_UHWO(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UHWO_SHIFT)) & S50_ELS_KS5_KS5_UHWO_MASK)
62297 
62298 #define S50_ELS_KS5_KS5_UWRPOK_MASK              (0x10000000U)
62299 #define S50_ELS_KS5_KS5_UWRPOK_SHIFT             (28U)
62300 #define S50_ELS_KS5_KS5_UWRPOK(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UWRPOK_SHIFT)) & S50_ELS_KS5_KS5_UWRPOK_MASK)
62301 
62302 #define S50_ELS_KS5_KS5_UDUK_MASK                (0x20000000U)
62303 #define S50_ELS_KS5_KS5_UDUK_SHIFT               (29U)
62304 #define S50_ELS_KS5_KS5_UDUK(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UDUK_SHIFT)) & S50_ELS_KS5_KS5_UDUK_MASK)
62305 
62306 #define S50_ELS_KS5_KS5_UPPROT_MASK              (0xC0000000U)
62307 #define S50_ELS_KS5_KS5_UPPROT_SHIFT             (30U)
62308 #define S50_ELS_KS5_KS5_UPPROT(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UPPROT_SHIFT)) & S50_ELS_KS5_KS5_UPPROT_MASK)
62309 /*! @} */
62310 
62311 /*! @name ELS_KS6 - Status Register */
62312 /*! @{ */
62313 
62314 #define S50_ELS_KS6_KS6_KSIZE_MASK               (0x3U)
62315 #define S50_ELS_KS6_KS6_KSIZE_SHIFT              (0U)
62316 /*! KS6_KSIZE
62317  *  0b00..128
62318  *  0b01..256
62319  */
62320 #define S50_ELS_KS6_KS6_KSIZE(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_KSIZE_SHIFT)) & S50_ELS_KS6_KS6_KSIZE_MASK)
62321 
62322 #define S50_ELS_KS6_KS6_KACT_MASK                (0x20U)
62323 #define S50_ELS_KS6_KS6_KACT_SHIFT               (5U)
62324 #define S50_ELS_KS6_KS6_KACT(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_KACT_SHIFT)) & S50_ELS_KS6_KS6_KACT_MASK)
62325 
62326 #define S50_ELS_KS6_KS6_KBASE_MASK               (0x40U)
62327 #define S50_ELS_KS6_KS6_KBASE_SHIFT              (6U)
62328 #define S50_ELS_KS6_KS6_KBASE(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_KBASE_SHIFT)) & S50_ELS_KS6_KS6_KBASE_MASK)
62329 
62330 #define S50_ELS_KS6_KS6_FGP_MASK                 (0x80U)
62331 #define S50_ELS_KS6_KS6_FGP_SHIFT                (7U)
62332 #define S50_ELS_KS6_KS6_FGP(x)                   (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_FGP_SHIFT)) & S50_ELS_KS6_KS6_FGP_MASK)
62333 
62334 #define S50_ELS_KS6_KS6_FRTN_MASK                (0x100U)
62335 #define S50_ELS_KS6_KS6_FRTN_SHIFT               (8U)
62336 #define S50_ELS_KS6_KS6_FRTN(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_FRTN_SHIFT)) & S50_ELS_KS6_KS6_FRTN_MASK)
62337 
62338 #define S50_ELS_KS6_KS6_FHWO_MASK                (0x200U)
62339 #define S50_ELS_KS6_KS6_FHWO_SHIFT               (9U)
62340 #define S50_ELS_KS6_KS6_FHWO(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_FHWO_SHIFT)) & S50_ELS_KS6_KS6_FHWO_MASK)
62341 
62342 #define S50_ELS_KS6_KS6_UKPUK_MASK               (0x800U)
62343 #define S50_ELS_KS6_KS6_UKPUK_SHIFT              (11U)
62344 #define S50_ELS_KS6_KS6_UKPUK(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UKPUK_SHIFT)) & S50_ELS_KS6_KS6_UKPUK_MASK)
62345 
62346 #define S50_ELS_KS6_KS6_UTECDH_MASK              (0x1000U)
62347 #define S50_ELS_KS6_KS6_UTECDH_SHIFT             (12U)
62348 #define S50_ELS_KS6_KS6_UTECDH(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UTECDH_SHIFT)) & S50_ELS_KS6_KS6_UTECDH_MASK)
62349 
62350 #define S50_ELS_KS6_KS6_UCMAC_MASK               (0x2000U)
62351 #define S50_ELS_KS6_KS6_UCMAC_SHIFT              (13U)
62352 #define S50_ELS_KS6_KS6_UCMAC(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UCMAC_SHIFT)) & S50_ELS_KS6_KS6_UCMAC_MASK)
62353 
62354 #define S50_ELS_KS6_KS6_UKSK_MASK                (0x4000U)
62355 #define S50_ELS_KS6_KS6_UKSK_SHIFT               (14U)
62356 #define S50_ELS_KS6_KS6_UKSK(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UKSK_SHIFT)) & S50_ELS_KS6_KS6_UKSK_MASK)
62357 
62358 #define S50_ELS_KS6_KS6_URTF_MASK                (0x8000U)
62359 #define S50_ELS_KS6_KS6_URTF_SHIFT               (15U)
62360 #define S50_ELS_KS6_KS6_URTF(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_URTF_SHIFT)) & S50_ELS_KS6_KS6_URTF_MASK)
62361 
62362 #define S50_ELS_KS6_KS6_UCKDF_MASK               (0x10000U)
62363 #define S50_ELS_KS6_KS6_UCKDF_SHIFT              (16U)
62364 #define S50_ELS_KS6_KS6_UCKDF(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UCKDF_SHIFT)) & S50_ELS_KS6_KS6_UCKDF_MASK)
62365 
62366 #define S50_ELS_KS6_KS6_UHKDF_MASK               (0x20000U)
62367 #define S50_ELS_KS6_KS6_UHKDF_SHIFT              (17U)
62368 #define S50_ELS_KS6_KS6_UHKDF(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UHKDF_SHIFT)) & S50_ELS_KS6_KS6_UHKDF_MASK)
62369 
62370 #define S50_ELS_KS6_KS6_UECSG_MASK               (0x40000U)
62371 #define S50_ELS_KS6_KS6_UECSG_SHIFT              (18U)
62372 #define S50_ELS_KS6_KS6_UECSG(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UECSG_SHIFT)) & S50_ELS_KS6_KS6_UECSG_MASK)
62373 
62374 #define S50_ELS_KS6_KS6_UECDH_MASK               (0x80000U)
62375 #define S50_ELS_KS6_KS6_UECDH_SHIFT              (19U)
62376 #define S50_ELS_KS6_KS6_UECDH(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UECDH_SHIFT)) & S50_ELS_KS6_KS6_UECDH_MASK)
62377 
62378 #define S50_ELS_KS6_KS6_UAES_MASK                (0x100000U)
62379 #define S50_ELS_KS6_KS6_UAES_SHIFT               (20U)
62380 #define S50_ELS_KS6_KS6_UAES(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UAES_SHIFT)) & S50_ELS_KS6_KS6_UAES_MASK)
62381 
62382 #define S50_ELS_KS6_KS6_UHMAC_MASK               (0x200000U)
62383 #define S50_ELS_KS6_KS6_UHMAC_SHIFT              (21U)
62384 #define S50_ELS_KS6_KS6_UHMAC(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UHMAC_SHIFT)) & S50_ELS_KS6_KS6_UHMAC_MASK)
62385 
62386 #define S50_ELS_KS6_KS6_UKWK_MASK                (0x400000U)
62387 #define S50_ELS_KS6_KS6_UKWK_SHIFT               (22U)
62388 #define S50_ELS_KS6_KS6_UKWK(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UKWK_SHIFT)) & S50_ELS_KS6_KS6_UKWK_MASK)
62389 
62390 #define S50_ELS_KS6_KS6_UKUOK_MASK               (0x800000U)
62391 #define S50_ELS_KS6_KS6_UKUOK_SHIFT              (23U)
62392 #define S50_ELS_KS6_KS6_UKUOK(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UKUOK_SHIFT)) & S50_ELS_KS6_KS6_UKUOK_MASK)
62393 
62394 #define S50_ELS_KS6_KS6_UTLSPMS_MASK             (0x1000000U)
62395 #define S50_ELS_KS6_KS6_UTLSPMS_SHIFT            (24U)
62396 #define S50_ELS_KS6_KS6_UTLSPMS(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UTLSPMS_SHIFT)) & S50_ELS_KS6_KS6_UTLSPMS_MASK)
62397 
62398 #define S50_ELS_KS6_KS6_UTLSMS_MASK              (0x2000000U)
62399 #define S50_ELS_KS6_KS6_UTLSMS_SHIFT             (25U)
62400 #define S50_ELS_KS6_KS6_UTLSMS(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UTLSMS_SHIFT)) & S50_ELS_KS6_KS6_UTLSMS_MASK)
62401 
62402 #define S50_ELS_KS6_KS6_UKGSRC_MASK              (0x4000000U)
62403 #define S50_ELS_KS6_KS6_UKGSRC_SHIFT             (26U)
62404 #define S50_ELS_KS6_KS6_UKGSRC(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UKGSRC_SHIFT)) & S50_ELS_KS6_KS6_UKGSRC_MASK)
62405 
62406 #define S50_ELS_KS6_KS6_UHWO_MASK                (0x8000000U)
62407 #define S50_ELS_KS6_KS6_UHWO_SHIFT               (27U)
62408 #define S50_ELS_KS6_KS6_UHWO(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UHWO_SHIFT)) & S50_ELS_KS6_KS6_UHWO_MASK)
62409 
62410 #define S50_ELS_KS6_KS6_UWRPOK_MASK              (0x10000000U)
62411 #define S50_ELS_KS6_KS6_UWRPOK_SHIFT             (28U)
62412 #define S50_ELS_KS6_KS6_UWRPOK(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UWRPOK_SHIFT)) & S50_ELS_KS6_KS6_UWRPOK_MASK)
62413 
62414 #define S50_ELS_KS6_KS6_UDUK_MASK                (0x20000000U)
62415 #define S50_ELS_KS6_KS6_UDUK_SHIFT               (29U)
62416 #define S50_ELS_KS6_KS6_UDUK(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UDUK_SHIFT)) & S50_ELS_KS6_KS6_UDUK_MASK)
62417 
62418 #define S50_ELS_KS6_KS6_UPPROT_MASK              (0xC0000000U)
62419 #define S50_ELS_KS6_KS6_UPPROT_SHIFT             (30U)
62420 #define S50_ELS_KS6_KS6_UPPROT(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UPPROT_SHIFT)) & S50_ELS_KS6_KS6_UPPROT_MASK)
62421 /*! @} */
62422 
62423 /*! @name ELS_KS7 - Status Register */
62424 /*! @{ */
62425 
62426 #define S50_ELS_KS7_KS7_KSIZE_MASK               (0x3U)
62427 #define S50_ELS_KS7_KS7_KSIZE_SHIFT              (0U)
62428 /*! KS7_KSIZE
62429  *  0b00..128
62430  *  0b01..256
62431  */
62432 #define S50_ELS_KS7_KS7_KSIZE(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_KSIZE_SHIFT)) & S50_ELS_KS7_KS7_KSIZE_MASK)
62433 
62434 #define S50_ELS_KS7_KS7_KACT_MASK                (0x20U)
62435 #define S50_ELS_KS7_KS7_KACT_SHIFT               (5U)
62436 #define S50_ELS_KS7_KS7_KACT(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_KACT_SHIFT)) & S50_ELS_KS7_KS7_KACT_MASK)
62437 
62438 #define S50_ELS_KS7_KS7_KBASE_MASK               (0x40U)
62439 #define S50_ELS_KS7_KS7_KBASE_SHIFT              (6U)
62440 #define S50_ELS_KS7_KS7_KBASE(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_KBASE_SHIFT)) & S50_ELS_KS7_KS7_KBASE_MASK)
62441 
62442 #define S50_ELS_KS7_KS7_FGP_MASK                 (0x80U)
62443 #define S50_ELS_KS7_KS7_FGP_SHIFT                (7U)
62444 #define S50_ELS_KS7_KS7_FGP(x)                   (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_FGP_SHIFT)) & S50_ELS_KS7_KS7_FGP_MASK)
62445 
62446 #define S50_ELS_KS7_KS7_FRTN_MASK                (0x100U)
62447 #define S50_ELS_KS7_KS7_FRTN_SHIFT               (8U)
62448 #define S50_ELS_KS7_KS7_FRTN(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_FRTN_SHIFT)) & S50_ELS_KS7_KS7_FRTN_MASK)
62449 
62450 #define S50_ELS_KS7_KS7_FHWO_MASK                (0x200U)
62451 #define S50_ELS_KS7_KS7_FHWO_SHIFT               (9U)
62452 #define S50_ELS_KS7_KS7_FHWO(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_FHWO_SHIFT)) & S50_ELS_KS7_KS7_FHWO_MASK)
62453 
62454 #define S50_ELS_KS7_KS7_UKPUK_MASK               (0x800U)
62455 #define S50_ELS_KS7_KS7_UKPUK_SHIFT              (11U)
62456 #define S50_ELS_KS7_KS7_UKPUK(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UKPUK_SHIFT)) & S50_ELS_KS7_KS7_UKPUK_MASK)
62457 
62458 #define S50_ELS_KS7_KS7_UTECDH_MASK              (0x1000U)
62459 #define S50_ELS_KS7_KS7_UTECDH_SHIFT             (12U)
62460 #define S50_ELS_KS7_KS7_UTECDH(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UTECDH_SHIFT)) & S50_ELS_KS7_KS7_UTECDH_MASK)
62461 
62462 #define S50_ELS_KS7_KS7_UCMAC_MASK               (0x2000U)
62463 #define S50_ELS_KS7_KS7_UCMAC_SHIFT              (13U)
62464 #define S50_ELS_KS7_KS7_UCMAC(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UCMAC_SHIFT)) & S50_ELS_KS7_KS7_UCMAC_MASK)
62465 
62466 #define S50_ELS_KS7_KS7_UKSK_MASK                (0x4000U)
62467 #define S50_ELS_KS7_KS7_UKSK_SHIFT               (14U)
62468 #define S50_ELS_KS7_KS7_UKSK(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UKSK_SHIFT)) & S50_ELS_KS7_KS7_UKSK_MASK)
62469 
62470 #define S50_ELS_KS7_KS7_URTF_MASK                (0x8000U)
62471 #define S50_ELS_KS7_KS7_URTF_SHIFT               (15U)
62472 #define S50_ELS_KS7_KS7_URTF(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_URTF_SHIFT)) & S50_ELS_KS7_KS7_URTF_MASK)
62473 
62474 #define S50_ELS_KS7_KS7_UCKDF_MASK               (0x10000U)
62475 #define S50_ELS_KS7_KS7_UCKDF_SHIFT              (16U)
62476 #define S50_ELS_KS7_KS7_UCKDF(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UCKDF_SHIFT)) & S50_ELS_KS7_KS7_UCKDF_MASK)
62477 
62478 #define S50_ELS_KS7_KS7_UHKDF_MASK               (0x20000U)
62479 #define S50_ELS_KS7_KS7_UHKDF_SHIFT              (17U)
62480 #define S50_ELS_KS7_KS7_UHKDF(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UHKDF_SHIFT)) & S50_ELS_KS7_KS7_UHKDF_MASK)
62481 
62482 #define S50_ELS_KS7_KS7_UECSG_MASK               (0x40000U)
62483 #define S50_ELS_KS7_KS7_UECSG_SHIFT              (18U)
62484 #define S50_ELS_KS7_KS7_UECSG(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UECSG_SHIFT)) & S50_ELS_KS7_KS7_UECSG_MASK)
62485 
62486 #define S50_ELS_KS7_KS7_UECDH_MASK               (0x80000U)
62487 #define S50_ELS_KS7_KS7_UECDH_SHIFT              (19U)
62488 #define S50_ELS_KS7_KS7_UECDH(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UECDH_SHIFT)) & S50_ELS_KS7_KS7_UECDH_MASK)
62489 
62490 #define S50_ELS_KS7_KS7_UAES_MASK                (0x100000U)
62491 #define S50_ELS_KS7_KS7_UAES_SHIFT               (20U)
62492 #define S50_ELS_KS7_KS7_UAES(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UAES_SHIFT)) & S50_ELS_KS7_KS7_UAES_MASK)
62493 
62494 #define S50_ELS_KS7_KS7_UHMAC_MASK               (0x200000U)
62495 #define S50_ELS_KS7_KS7_UHMAC_SHIFT              (21U)
62496 #define S50_ELS_KS7_KS7_UHMAC(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UHMAC_SHIFT)) & S50_ELS_KS7_KS7_UHMAC_MASK)
62497 
62498 #define S50_ELS_KS7_KS7_UKWK_MASK                (0x400000U)
62499 #define S50_ELS_KS7_KS7_UKWK_SHIFT               (22U)
62500 #define S50_ELS_KS7_KS7_UKWK(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UKWK_SHIFT)) & S50_ELS_KS7_KS7_UKWK_MASK)
62501 
62502 #define S50_ELS_KS7_KS7_UKUOK_MASK               (0x800000U)
62503 #define S50_ELS_KS7_KS7_UKUOK_SHIFT              (23U)
62504 #define S50_ELS_KS7_KS7_UKUOK(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UKUOK_SHIFT)) & S50_ELS_KS7_KS7_UKUOK_MASK)
62505 
62506 #define S50_ELS_KS7_KS7_UTLSPMS_MASK             (0x1000000U)
62507 #define S50_ELS_KS7_KS7_UTLSPMS_SHIFT            (24U)
62508 #define S50_ELS_KS7_KS7_UTLSPMS(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UTLSPMS_SHIFT)) & S50_ELS_KS7_KS7_UTLSPMS_MASK)
62509 
62510 #define S50_ELS_KS7_KS7_UTLSMS_MASK              (0x2000000U)
62511 #define S50_ELS_KS7_KS7_UTLSMS_SHIFT             (25U)
62512 #define S50_ELS_KS7_KS7_UTLSMS(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UTLSMS_SHIFT)) & S50_ELS_KS7_KS7_UTLSMS_MASK)
62513 
62514 #define S50_ELS_KS7_KS7_UKGSRC_MASK              (0x4000000U)
62515 #define S50_ELS_KS7_KS7_UKGSRC_SHIFT             (26U)
62516 #define S50_ELS_KS7_KS7_UKGSRC(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UKGSRC_SHIFT)) & S50_ELS_KS7_KS7_UKGSRC_MASK)
62517 
62518 #define S50_ELS_KS7_KS7_UHWO_MASK                (0x8000000U)
62519 #define S50_ELS_KS7_KS7_UHWO_SHIFT               (27U)
62520 #define S50_ELS_KS7_KS7_UHWO(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UHWO_SHIFT)) & S50_ELS_KS7_KS7_UHWO_MASK)
62521 
62522 #define S50_ELS_KS7_KS7_UWRPOK_MASK              (0x10000000U)
62523 #define S50_ELS_KS7_KS7_UWRPOK_SHIFT             (28U)
62524 #define S50_ELS_KS7_KS7_UWRPOK(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UWRPOK_SHIFT)) & S50_ELS_KS7_KS7_UWRPOK_MASK)
62525 
62526 #define S50_ELS_KS7_KS7_UDUK_MASK                (0x20000000U)
62527 #define S50_ELS_KS7_KS7_UDUK_SHIFT               (29U)
62528 #define S50_ELS_KS7_KS7_UDUK(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UDUK_SHIFT)) & S50_ELS_KS7_KS7_UDUK_MASK)
62529 
62530 #define S50_ELS_KS7_KS7_UPPROT_MASK              (0xC0000000U)
62531 #define S50_ELS_KS7_KS7_UPPROT_SHIFT             (30U)
62532 #define S50_ELS_KS7_KS7_UPPROT(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UPPROT_SHIFT)) & S50_ELS_KS7_KS7_UPPROT_MASK)
62533 /*! @} */
62534 
62535 /*! @name ELS_KS8 - Status Register */
62536 /*! @{ */
62537 
62538 #define S50_ELS_KS8_KS8_KSIZE_MASK               (0x3U)
62539 #define S50_ELS_KS8_KS8_KSIZE_SHIFT              (0U)
62540 /*! KS8_KSIZE
62541  *  0b00..128
62542  *  0b01..256
62543  */
62544 #define S50_ELS_KS8_KS8_KSIZE(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_KSIZE_SHIFT)) & S50_ELS_KS8_KS8_KSIZE_MASK)
62545 
62546 #define S50_ELS_KS8_KS8_KACT_MASK                (0x20U)
62547 #define S50_ELS_KS8_KS8_KACT_SHIFT               (5U)
62548 #define S50_ELS_KS8_KS8_KACT(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_KACT_SHIFT)) & S50_ELS_KS8_KS8_KACT_MASK)
62549 
62550 #define S50_ELS_KS8_KS8_KBASE_MASK               (0x40U)
62551 #define S50_ELS_KS8_KS8_KBASE_SHIFT              (6U)
62552 #define S50_ELS_KS8_KS8_KBASE(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_KBASE_SHIFT)) & S50_ELS_KS8_KS8_KBASE_MASK)
62553 
62554 #define S50_ELS_KS8_KS8_FGP_MASK                 (0x80U)
62555 #define S50_ELS_KS8_KS8_FGP_SHIFT                (7U)
62556 #define S50_ELS_KS8_KS8_FGP(x)                   (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_FGP_SHIFT)) & S50_ELS_KS8_KS8_FGP_MASK)
62557 
62558 #define S50_ELS_KS8_KS8_FRTN_MASK                (0x100U)
62559 #define S50_ELS_KS8_KS8_FRTN_SHIFT               (8U)
62560 #define S50_ELS_KS8_KS8_FRTN(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_FRTN_SHIFT)) & S50_ELS_KS8_KS8_FRTN_MASK)
62561 
62562 #define S50_ELS_KS8_KS8_FHWO_MASK                (0x200U)
62563 #define S50_ELS_KS8_KS8_FHWO_SHIFT               (9U)
62564 #define S50_ELS_KS8_KS8_FHWO(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_FHWO_SHIFT)) & S50_ELS_KS8_KS8_FHWO_MASK)
62565 
62566 #define S50_ELS_KS8_KS8_UKPUK_MASK               (0x800U)
62567 #define S50_ELS_KS8_KS8_UKPUK_SHIFT              (11U)
62568 #define S50_ELS_KS8_KS8_UKPUK(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UKPUK_SHIFT)) & S50_ELS_KS8_KS8_UKPUK_MASK)
62569 
62570 #define S50_ELS_KS8_KS8_UTECDH_MASK              (0x1000U)
62571 #define S50_ELS_KS8_KS8_UTECDH_SHIFT             (12U)
62572 #define S50_ELS_KS8_KS8_UTECDH(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UTECDH_SHIFT)) & S50_ELS_KS8_KS8_UTECDH_MASK)
62573 
62574 #define S50_ELS_KS8_KS8_UCMAC_MASK               (0x2000U)
62575 #define S50_ELS_KS8_KS8_UCMAC_SHIFT              (13U)
62576 #define S50_ELS_KS8_KS8_UCMAC(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UCMAC_SHIFT)) & S50_ELS_KS8_KS8_UCMAC_MASK)
62577 
62578 #define S50_ELS_KS8_KS8_UKSK_MASK                (0x4000U)
62579 #define S50_ELS_KS8_KS8_UKSK_SHIFT               (14U)
62580 #define S50_ELS_KS8_KS8_UKSK(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UKSK_SHIFT)) & S50_ELS_KS8_KS8_UKSK_MASK)
62581 
62582 #define S50_ELS_KS8_KS8_URTF_MASK                (0x8000U)
62583 #define S50_ELS_KS8_KS8_URTF_SHIFT               (15U)
62584 #define S50_ELS_KS8_KS8_URTF(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_URTF_SHIFT)) & S50_ELS_KS8_KS8_URTF_MASK)
62585 
62586 #define S50_ELS_KS8_KS8_UCKDF_MASK               (0x10000U)
62587 #define S50_ELS_KS8_KS8_UCKDF_SHIFT              (16U)
62588 #define S50_ELS_KS8_KS8_UCKDF(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UCKDF_SHIFT)) & S50_ELS_KS8_KS8_UCKDF_MASK)
62589 
62590 #define S50_ELS_KS8_KS8_UHKDF_MASK               (0x20000U)
62591 #define S50_ELS_KS8_KS8_UHKDF_SHIFT              (17U)
62592 #define S50_ELS_KS8_KS8_UHKDF(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UHKDF_SHIFT)) & S50_ELS_KS8_KS8_UHKDF_MASK)
62593 
62594 #define S50_ELS_KS8_KS8_UECSG_MASK               (0x40000U)
62595 #define S50_ELS_KS8_KS8_UECSG_SHIFT              (18U)
62596 #define S50_ELS_KS8_KS8_UECSG(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UECSG_SHIFT)) & S50_ELS_KS8_KS8_UECSG_MASK)
62597 
62598 #define S50_ELS_KS8_KS8_UECDH_MASK               (0x80000U)
62599 #define S50_ELS_KS8_KS8_UECDH_SHIFT              (19U)
62600 #define S50_ELS_KS8_KS8_UECDH(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UECDH_SHIFT)) & S50_ELS_KS8_KS8_UECDH_MASK)
62601 
62602 #define S50_ELS_KS8_KS8_UAES_MASK                (0x100000U)
62603 #define S50_ELS_KS8_KS8_UAES_SHIFT               (20U)
62604 #define S50_ELS_KS8_KS8_UAES(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UAES_SHIFT)) & S50_ELS_KS8_KS8_UAES_MASK)
62605 
62606 #define S50_ELS_KS8_KS8_UHMAC_MASK               (0x200000U)
62607 #define S50_ELS_KS8_KS8_UHMAC_SHIFT              (21U)
62608 #define S50_ELS_KS8_KS8_UHMAC(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UHMAC_SHIFT)) & S50_ELS_KS8_KS8_UHMAC_MASK)
62609 
62610 #define S50_ELS_KS8_KS8_UKWK_MASK                (0x400000U)
62611 #define S50_ELS_KS8_KS8_UKWK_SHIFT               (22U)
62612 #define S50_ELS_KS8_KS8_UKWK(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UKWK_SHIFT)) & S50_ELS_KS8_KS8_UKWK_MASK)
62613 
62614 #define S50_ELS_KS8_KS8_UKUOK_MASK               (0x800000U)
62615 #define S50_ELS_KS8_KS8_UKUOK_SHIFT              (23U)
62616 #define S50_ELS_KS8_KS8_UKUOK(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UKUOK_SHIFT)) & S50_ELS_KS8_KS8_UKUOK_MASK)
62617 
62618 #define S50_ELS_KS8_KS8_UTLSPMS_MASK             (0x1000000U)
62619 #define S50_ELS_KS8_KS8_UTLSPMS_SHIFT            (24U)
62620 #define S50_ELS_KS8_KS8_UTLSPMS(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UTLSPMS_SHIFT)) & S50_ELS_KS8_KS8_UTLSPMS_MASK)
62621 
62622 #define S50_ELS_KS8_KS8_UTLSMS_MASK              (0x2000000U)
62623 #define S50_ELS_KS8_KS8_UTLSMS_SHIFT             (25U)
62624 #define S50_ELS_KS8_KS8_UTLSMS(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UTLSMS_SHIFT)) & S50_ELS_KS8_KS8_UTLSMS_MASK)
62625 
62626 #define S50_ELS_KS8_KS8_UKGSRC_MASK              (0x4000000U)
62627 #define S50_ELS_KS8_KS8_UKGSRC_SHIFT             (26U)
62628 #define S50_ELS_KS8_KS8_UKGSRC(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UKGSRC_SHIFT)) & S50_ELS_KS8_KS8_UKGSRC_MASK)
62629 
62630 #define S50_ELS_KS8_KS8_UHWO_MASK                (0x8000000U)
62631 #define S50_ELS_KS8_KS8_UHWO_SHIFT               (27U)
62632 #define S50_ELS_KS8_KS8_UHWO(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UHWO_SHIFT)) & S50_ELS_KS8_KS8_UHWO_MASK)
62633 
62634 #define S50_ELS_KS8_KS8_UWRPOK_MASK              (0x10000000U)
62635 #define S50_ELS_KS8_KS8_UWRPOK_SHIFT             (28U)
62636 #define S50_ELS_KS8_KS8_UWRPOK(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UWRPOK_SHIFT)) & S50_ELS_KS8_KS8_UWRPOK_MASK)
62637 
62638 #define S50_ELS_KS8_KS8_UDUK_MASK                (0x20000000U)
62639 #define S50_ELS_KS8_KS8_UDUK_SHIFT               (29U)
62640 #define S50_ELS_KS8_KS8_UDUK(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UDUK_SHIFT)) & S50_ELS_KS8_KS8_UDUK_MASK)
62641 
62642 #define S50_ELS_KS8_KS8_UPPROT_MASK              (0xC0000000U)
62643 #define S50_ELS_KS8_KS8_UPPROT_SHIFT             (30U)
62644 #define S50_ELS_KS8_KS8_UPPROT(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UPPROT_SHIFT)) & S50_ELS_KS8_KS8_UPPROT_MASK)
62645 /*! @} */
62646 
62647 /*! @name ELS_KS9 - Status Register */
62648 /*! @{ */
62649 
62650 #define S50_ELS_KS9_KS9_KSIZE_MASK               (0x3U)
62651 #define S50_ELS_KS9_KS9_KSIZE_SHIFT              (0U)
62652 /*! KS9_KSIZE
62653  *  0b00..128
62654  *  0b01..256
62655  */
62656 #define S50_ELS_KS9_KS9_KSIZE(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_KSIZE_SHIFT)) & S50_ELS_KS9_KS9_KSIZE_MASK)
62657 
62658 #define S50_ELS_KS9_KS9_KACT_MASK                (0x20U)
62659 #define S50_ELS_KS9_KS9_KACT_SHIFT               (5U)
62660 #define S50_ELS_KS9_KS9_KACT(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_KACT_SHIFT)) & S50_ELS_KS9_KS9_KACT_MASK)
62661 
62662 #define S50_ELS_KS9_KS9_KBASE_MASK               (0x40U)
62663 #define S50_ELS_KS9_KS9_KBASE_SHIFT              (6U)
62664 #define S50_ELS_KS9_KS9_KBASE(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_KBASE_SHIFT)) & S50_ELS_KS9_KS9_KBASE_MASK)
62665 
62666 #define S50_ELS_KS9_KS9_FGP_MASK                 (0x80U)
62667 #define S50_ELS_KS9_KS9_FGP_SHIFT                (7U)
62668 #define S50_ELS_KS9_KS9_FGP(x)                   (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_FGP_SHIFT)) & S50_ELS_KS9_KS9_FGP_MASK)
62669 
62670 #define S50_ELS_KS9_KS9_FRTN_MASK                (0x100U)
62671 #define S50_ELS_KS9_KS9_FRTN_SHIFT               (8U)
62672 #define S50_ELS_KS9_KS9_FRTN(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_FRTN_SHIFT)) & S50_ELS_KS9_KS9_FRTN_MASK)
62673 
62674 #define S50_ELS_KS9_KS9_FHWO_MASK                (0x200U)
62675 #define S50_ELS_KS9_KS9_FHWO_SHIFT               (9U)
62676 #define S50_ELS_KS9_KS9_FHWO(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_FHWO_SHIFT)) & S50_ELS_KS9_KS9_FHWO_MASK)
62677 
62678 #define S50_ELS_KS9_KS9_UKPUK_MASK               (0x800U)
62679 #define S50_ELS_KS9_KS9_UKPUK_SHIFT              (11U)
62680 #define S50_ELS_KS9_KS9_UKPUK(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UKPUK_SHIFT)) & S50_ELS_KS9_KS9_UKPUK_MASK)
62681 
62682 #define S50_ELS_KS9_KS9_UTECDH_MASK              (0x1000U)
62683 #define S50_ELS_KS9_KS9_UTECDH_SHIFT             (12U)
62684 #define S50_ELS_KS9_KS9_UTECDH(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UTECDH_SHIFT)) & S50_ELS_KS9_KS9_UTECDH_MASK)
62685 
62686 #define S50_ELS_KS9_KS9_UCMAC_MASK               (0x2000U)
62687 #define S50_ELS_KS9_KS9_UCMAC_SHIFT              (13U)
62688 #define S50_ELS_KS9_KS9_UCMAC(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UCMAC_SHIFT)) & S50_ELS_KS9_KS9_UCMAC_MASK)
62689 
62690 #define S50_ELS_KS9_KS9_UKSK_MASK                (0x4000U)
62691 #define S50_ELS_KS9_KS9_UKSK_SHIFT               (14U)
62692 #define S50_ELS_KS9_KS9_UKSK(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UKSK_SHIFT)) & S50_ELS_KS9_KS9_UKSK_MASK)
62693 
62694 #define S50_ELS_KS9_KS9_URTF_MASK                (0x8000U)
62695 #define S50_ELS_KS9_KS9_URTF_SHIFT               (15U)
62696 #define S50_ELS_KS9_KS9_URTF(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_URTF_SHIFT)) & S50_ELS_KS9_KS9_URTF_MASK)
62697 
62698 #define S50_ELS_KS9_KS9_UCKDF_MASK               (0x10000U)
62699 #define S50_ELS_KS9_KS9_UCKDF_SHIFT              (16U)
62700 #define S50_ELS_KS9_KS9_UCKDF(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UCKDF_SHIFT)) & S50_ELS_KS9_KS9_UCKDF_MASK)
62701 
62702 #define S50_ELS_KS9_KS9_UHKDF_MASK               (0x20000U)
62703 #define S50_ELS_KS9_KS9_UHKDF_SHIFT              (17U)
62704 #define S50_ELS_KS9_KS9_UHKDF(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UHKDF_SHIFT)) & S50_ELS_KS9_KS9_UHKDF_MASK)
62705 
62706 #define S50_ELS_KS9_KS9_UECSG_MASK               (0x40000U)
62707 #define S50_ELS_KS9_KS9_UECSG_SHIFT              (18U)
62708 #define S50_ELS_KS9_KS9_UECSG(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UECSG_SHIFT)) & S50_ELS_KS9_KS9_UECSG_MASK)
62709 
62710 #define S50_ELS_KS9_KS9_UECDH_MASK               (0x80000U)
62711 #define S50_ELS_KS9_KS9_UECDH_SHIFT              (19U)
62712 #define S50_ELS_KS9_KS9_UECDH(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UECDH_SHIFT)) & S50_ELS_KS9_KS9_UECDH_MASK)
62713 
62714 #define S50_ELS_KS9_KS9_UAES_MASK                (0x100000U)
62715 #define S50_ELS_KS9_KS9_UAES_SHIFT               (20U)
62716 #define S50_ELS_KS9_KS9_UAES(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UAES_SHIFT)) & S50_ELS_KS9_KS9_UAES_MASK)
62717 
62718 #define S50_ELS_KS9_KS9_UHMAC_MASK               (0x200000U)
62719 #define S50_ELS_KS9_KS9_UHMAC_SHIFT              (21U)
62720 #define S50_ELS_KS9_KS9_UHMAC(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UHMAC_SHIFT)) & S50_ELS_KS9_KS9_UHMAC_MASK)
62721 
62722 #define S50_ELS_KS9_KS9_UKWK_MASK                (0x400000U)
62723 #define S50_ELS_KS9_KS9_UKWK_SHIFT               (22U)
62724 #define S50_ELS_KS9_KS9_UKWK(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UKWK_SHIFT)) & S50_ELS_KS9_KS9_UKWK_MASK)
62725 
62726 #define S50_ELS_KS9_KS9_UKUOK_MASK               (0x800000U)
62727 #define S50_ELS_KS9_KS9_UKUOK_SHIFT              (23U)
62728 #define S50_ELS_KS9_KS9_UKUOK(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UKUOK_SHIFT)) & S50_ELS_KS9_KS9_UKUOK_MASK)
62729 
62730 #define S50_ELS_KS9_KS9_UTLSPMS_MASK             (0x1000000U)
62731 #define S50_ELS_KS9_KS9_UTLSPMS_SHIFT            (24U)
62732 #define S50_ELS_KS9_KS9_UTLSPMS(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UTLSPMS_SHIFT)) & S50_ELS_KS9_KS9_UTLSPMS_MASK)
62733 
62734 #define S50_ELS_KS9_KS9_UTLSMS_MASK              (0x2000000U)
62735 #define S50_ELS_KS9_KS9_UTLSMS_SHIFT             (25U)
62736 #define S50_ELS_KS9_KS9_UTLSMS(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UTLSMS_SHIFT)) & S50_ELS_KS9_KS9_UTLSMS_MASK)
62737 
62738 #define S50_ELS_KS9_KS9_UKGSRC_MASK              (0x4000000U)
62739 #define S50_ELS_KS9_KS9_UKGSRC_SHIFT             (26U)
62740 #define S50_ELS_KS9_KS9_UKGSRC(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UKGSRC_SHIFT)) & S50_ELS_KS9_KS9_UKGSRC_MASK)
62741 
62742 #define S50_ELS_KS9_KS9_UHWO_MASK                (0x8000000U)
62743 #define S50_ELS_KS9_KS9_UHWO_SHIFT               (27U)
62744 #define S50_ELS_KS9_KS9_UHWO(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UHWO_SHIFT)) & S50_ELS_KS9_KS9_UHWO_MASK)
62745 
62746 #define S50_ELS_KS9_KS9_UWRPOK_MASK              (0x10000000U)
62747 #define S50_ELS_KS9_KS9_UWRPOK_SHIFT             (28U)
62748 #define S50_ELS_KS9_KS9_UWRPOK(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UWRPOK_SHIFT)) & S50_ELS_KS9_KS9_UWRPOK_MASK)
62749 
62750 #define S50_ELS_KS9_KS9_UDUK_MASK                (0x20000000U)
62751 #define S50_ELS_KS9_KS9_UDUK_SHIFT               (29U)
62752 #define S50_ELS_KS9_KS9_UDUK(x)                  (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UDUK_SHIFT)) & S50_ELS_KS9_KS9_UDUK_MASK)
62753 
62754 #define S50_ELS_KS9_KS9_UPPROT_MASK              (0xC0000000U)
62755 #define S50_ELS_KS9_KS9_UPPROT_SHIFT             (30U)
62756 #define S50_ELS_KS9_KS9_UPPROT(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UPPROT_SHIFT)) & S50_ELS_KS9_KS9_UPPROT_MASK)
62757 /*! @} */
62758 
62759 /*! @name ELS_KS10 - Status Register */
62760 /*! @{ */
62761 
62762 #define S50_ELS_KS10_KS10_KSIZE_MASK             (0x3U)
62763 #define S50_ELS_KS10_KS10_KSIZE_SHIFT            (0U)
62764 /*! KS10_KSIZE
62765  *  0b00..128
62766  *  0b01..256
62767  */
62768 #define S50_ELS_KS10_KS10_KSIZE(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_KSIZE_SHIFT)) & S50_ELS_KS10_KS10_KSIZE_MASK)
62769 
62770 #define S50_ELS_KS10_KS10_KACT_MASK              (0x20U)
62771 #define S50_ELS_KS10_KS10_KACT_SHIFT             (5U)
62772 #define S50_ELS_KS10_KS10_KACT(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_KACT_SHIFT)) & S50_ELS_KS10_KS10_KACT_MASK)
62773 
62774 #define S50_ELS_KS10_KS10_KBASE_MASK             (0x40U)
62775 #define S50_ELS_KS10_KS10_KBASE_SHIFT            (6U)
62776 #define S50_ELS_KS10_KS10_KBASE(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_KBASE_SHIFT)) & S50_ELS_KS10_KS10_KBASE_MASK)
62777 
62778 #define S50_ELS_KS10_KS10_FGP_MASK               (0x80U)
62779 #define S50_ELS_KS10_KS10_FGP_SHIFT              (7U)
62780 #define S50_ELS_KS10_KS10_FGP(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_FGP_SHIFT)) & S50_ELS_KS10_KS10_FGP_MASK)
62781 
62782 #define S50_ELS_KS10_KS10_FRTN_MASK              (0x100U)
62783 #define S50_ELS_KS10_KS10_FRTN_SHIFT             (8U)
62784 #define S50_ELS_KS10_KS10_FRTN(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_FRTN_SHIFT)) & S50_ELS_KS10_KS10_FRTN_MASK)
62785 
62786 #define S50_ELS_KS10_KS10_FHWO_MASK              (0x200U)
62787 #define S50_ELS_KS10_KS10_FHWO_SHIFT             (9U)
62788 #define S50_ELS_KS10_KS10_FHWO(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_FHWO_SHIFT)) & S50_ELS_KS10_KS10_FHWO_MASK)
62789 
62790 #define S50_ELS_KS10_KS10_UKPUK_MASK             (0x800U)
62791 #define S50_ELS_KS10_KS10_UKPUK_SHIFT            (11U)
62792 #define S50_ELS_KS10_KS10_UKPUK(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UKPUK_SHIFT)) & S50_ELS_KS10_KS10_UKPUK_MASK)
62793 
62794 #define S50_ELS_KS10_KS10_UTECDH_MASK            (0x1000U)
62795 #define S50_ELS_KS10_KS10_UTECDH_SHIFT           (12U)
62796 #define S50_ELS_KS10_KS10_UTECDH(x)              (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UTECDH_SHIFT)) & S50_ELS_KS10_KS10_UTECDH_MASK)
62797 
62798 #define S50_ELS_KS10_KS10_UCMAC_MASK             (0x2000U)
62799 #define S50_ELS_KS10_KS10_UCMAC_SHIFT            (13U)
62800 #define S50_ELS_KS10_KS10_UCMAC(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UCMAC_SHIFT)) & S50_ELS_KS10_KS10_UCMAC_MASK)
62801 
62802 #define S50_ELS_KS10_KS10_UKSK_MASK              (0x4000U)
62803 #define S50_ELS_KS10_KS10_UKSK_SHIFT             (14U)
62804 #define S50_ELS_KS10_KS10_UKSK(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UKSK_SHIFT)) & S50_ELS_KS10_KS10_UKSK_MASK)
62805 
62806 #define S50_ELS_KS10_KS10_URTF_MASK              (0x8000U)
62807 #define S50_ELS_KS10_KS10_URTF_SHIFT             (15U)
62808 #define S50_ELS_KS10_KS10_URTF(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_URTF_SHIFT)) & S50_ELS_KS10_KS10_URTF_MASK)
62809 
62810 #define S50_ELS_KS10_KS10_UCKDF_MASK             (0x10000U)
62811 #define S50_ELS_KS10_KS10_UCKDF_SHIFT            (16U)
62812 #define S50_ELS_KS10_KS10_UCKDF(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UCKDF_SHIFT)) & S50_ELS_KS10_KS10_UCKDF_MASK)
62813 
62814 #define S50_ELS_KS10_KS10_UHKDF_MASK             (0x20000U)
62815 #define S50_ELS_KS10_KS10_UHKDF_SHIFT            (17U)
62816 #define S50_ELS_KS10_KS10_UHKDF(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UHKDF_SHIFT)) & S50_ELS_KS10_KS10_UHKDF_MASK)
62817 
62818 #define S50_ELS_KS10_KS10_UECSG_MASK             (0x40000U)
62819 #define S50_ELS_KS10_KS10_UECSG_SHIFT            (18U)
62820 #define S50_ELS_KS10_KS10_UECSG(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UECSG_SHIFT)) & S50_ELS_KS10_KS10_UECSG_MASK)
62821 
62822 #define S50_ELS_KS10_KS10_UECDH_MASK             (0x80000U)
62823 #define S50_ELS_KS10_KS10_UECDH_SHIFT            (19U)
62824 #define S50_ELS_KS10_KS10_UECDH(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UECDH_SHIFT)) & S50_ELS_KS10_KS10_UECDH_MASK)
62825 
62826 #define S50_ELS_KS10_KS10_UAES_MASK              (0x100000U)
62827 #define S50_ELS_KS10_KS10_UAES_SHIFT             (20U)
62828 #define S50_ELS_KS10_KS10_UAES(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UAES_SHIFT)) & S50_ELS_KS10_KS10_UAES_MASK)
62829 
62830 #define S50_ELS_KS10_KS10_UHMAC_MASK             (0x200000U)
62831 #define S50_ELS_KS10_KS10_UHMAC_SHIFT            (21U)
62832 #define S50_ELS_KS10_KS10_UHMAC(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UHMAC_SHIFT)) & S50_ELS_KS10_KS10_UHMAC_MASK)
62833 
62834 #define S50_ELS_KS10_KS10_UKWK_MASK              (0x400000U)
62835 #define S50_ELS_KS10_KS10_UKWK_SHIFT             (22U)
62836 #define S50_ELS_KS10_KS10_UKWK(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UKWK_SHIFT)) & S50_ELS_KS10_KS10_UKWK_MASK)
62837 
62838 #define S50_ELS_KS10_KS10_UKUOK_MASK             (0x800000U)
62839 #define S50_ELS_KS10_KS10_UKUOK_SHIFT            (23U)
62840 #define S50_ELS_KS10_KS10_UKUOK(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UKUOK_SHIFT)) & S50_ELS_KS10_KS10_UKUOK_MASK)
62841 
62842 #define S50_ELS_KS10_KS10_UTLSPMS_MASK           (0x1000000U)
62843 #define S50_ELS_KS10_KS10_UTLSPMS_SHIFT          (24U)
62844 #define S50_ELS_KS10_KS10_UTLSPMS(x)             (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UTLSPMS_SHIFT)) & S50_ELS_KS10_KS10_UTLSPMS_MASK)
62845 
62846 #define S50_ELS_KS10_KS10_UTLSMS_MASK            (0x2000000U)
62847 #define S50_ELS_KS10_KS10_UTLSMS_SHIFT           (25U)
62848 #define S50_ELS_KS10_KS10_UTLSMS(x)              (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UTLSMS_SHIFT)) & S50_ELS_KS10_KS10_UTLSMS_MASK)
62849 
62850 #define S50_ELS_KS10_KS10_UKGSRC_MASK            (0x4000000U)
62851 #define S50_ELS_KS10_KS10_UKGSRC_SHIFT           (26U)
62852 #define S50_ELS_KS10_KS10_UKGSRC(x)              (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UKGSRC_SHIFT)) & S50_ELS_KS10_KS10_UKGSRC_MASK)
62853 
62854 #define S50_ELS_KS10_KS10_UHWO_MASK              (0x8000000U)
62855 #define S50_ELS_KS10_KS10_UHWO_SHIFT             (27U)
62856 #define S50_ELS_KS10_KS10_UHWO(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UHWO_SHIFT)) & S50_ELS_KS10_KS10_UHWO_MASK)
62857 
62858 #define S50_ELS_KS10_KS10_UWRPOK_MASK            (0x10000000U)
62859 #define S50_ELS_KS10_KS10_UWRPOK_SHIFT           (28U)
62860 #define S50_ELS_KS10_KS10_UWRPOK(x)              (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UWRPOK_SHIFT)) & S50_ELS_KS10_KS10_UWRPOK_MASK)
62861 
62862 #define S50_ELS_KS10_KS10_UDUK_MASK              (0x20000000U)
62863 #define S50_ELS_KS10_KS10_UDUK_SHIFT             (29U)
62864 #define S50_ELS_KS10_KS10_UDUK(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UDUK_SHIFT)) & S50_ELS_KS10_KS10_UDUK_MASK)
62865 
62866 #define S50_ELS_KS10_KS10_UPPROT_MASK            (0xC0000000U)
62867 #define S50_ELS_KS10_KS10_UPPROT_SHIFT           (30U)
62868 #define S50_ELS_KS10_KS10_UPPROT(x)              (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UPPROT_SHIFT)) & S50_ELS_KS10_KS10_UPPROT_MASK)
62869 /*! @} */
62870 
62871 /*! @name ELS_KS11 - Status Register */
62872 /*! @{ */
62873 
62874 #define S50_ELS_KS11_KS11_KSIZE_MASK             (0x3U)
62875 #define S50_ELS_KS11_KS11_KSIZE_SHIFT            (0U)
62876 /*! KS11_KSIZE
62877  *  0b00..128
62878  *  0b01..256
62879  */
62880 #define S50_ELS_KS11_KS11_KSIZE(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_KSIZE_SHIFT)) & S50_ELS_KS11_KS11_KSIZE_MASK)
62881 
62882 #define S50_ELS_KS11_KS11_KACT_MASK              (0x20U)
62883 #define S50_ELS_KS11_KS11_KACT_SHIFT             (5U)
62884 #define S50_ELS_KS11_KS11_KACT(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_KACT_SHIFT)) & S50_ELS_KS11_KS11_KACT_MASK)
62885 
62886 #define S50_ELS_KS11_KS11_KBASE_MASK             (0x40U)
62887 #define S50_ELS_KS11_KS11_KBASE_SHIFT            (6U)
62888 #define S50_ELS_KS11_KS11_KBASE(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_KBASE_SHIFT)) & S50_ELS_KS11_KS11_KBASE_MASK)
62889 
62890 #define S50_ELS_KS11_KS11_FGP_MASK               (0x80U)
62891 #define S50_ELS_KS11_KS11_FGP_SHIFT              (7U)
62892 #define S50_ELS_KS11_KS11_FGP(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_FGP_SHIFT)) & S50_ELS_KS11_KS11_FGP_MASK)
62893 
62894 #define S50_ELS_KS11_KS11_FRTN_MASK              (0x100U)
62895 #define S50_ELS_KS11_KS11_FRTN_SHIFT             (8U)
62896 #define S50_ELS_KS11_KS11_FRTN(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_FRTN_SHIFT)) & S50_ELS_KS11_KS11_FRTN_MASK)
62897 
62898 #define S50_ELS_KS11_KS11_FHWO_MASK              (0x200U)
62899 #define S50_ELS_KS11_KS11_FHWO_SHIFT             (9U)
62900 #define S50_ELS_KS11_KS11_FHWO(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_FHWO_SHIFT)) & S50_ELS_KS11_KS11_FHWO_MASK)
62901 
62902 #define S50_ELS_KS11_KS11_UKPUK_MASK             (0x800U)
62903 #define S50_ELS_KS11_KS11_UKPUK_SHIFT            (11U)
62904 #define S50_ELS_KS11_KS11_UKPUK(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UKPUK_SHIFT)) & S50_ELS_KS11_KS11_UKPUK_MASK)
62905 
62906 #define S50_ELS_KS11_KS11_UTECDH_MASK            (0x1000U)
62907 #define S50_ELS_KS11_KS11_UTECDH_SHIFT           (12U)
62908 #define S50_ELS_KS11_KS11_UTECDH(x)              (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UTECDH_SHIFT)) & S50_ELS_KS11_KS11_UTECDH_MASK)
62909 
62910 #define S50_ELS_KS11_KS11_UCMAC_MASK             (0x2000U)
62911 #define S50_ELS_KS11_KS11_UCMAC_SHIFT            (13U)
62912 #define S50_ELS_KS11_KS11_UCMAC(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UCMAC_SHIFT)) & S50_ELS_KS11_KS11_UCMAC_MASK)
62913 
62914 #define S50_ELS_KS11_KS11_UKSK_MASK              (0x4000U)
62915 #define S50_ELS_KS11_KS11_UKSK_SHIFT             (14U)
62916 #define S50_ELS_KS11_KS11_UKSK(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UKSK_SHIFT)) & S50_ELS_KS11_KS11_UKSK_MASK)
62917 
62918 #define S50_ELS_KS11_KS11_URTF_MASK              (0x8000U)
62919 #define S50_ELS_KS11_KS11_URTF_SHIFT             (15U)
62920 #define S50_ELS_KS11_KS11_URTF(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_URTF_SHIFT)) & S50_ELS_KS11_KS11_URTF_MASK)
62921 
62922 #define S50_ELS_KS11_KS11_UCKDF_MASK             (0x10000U)
62923 #define S50_ELS_KS11_KS11_UCKDF_SHIFT            (16U)
62924 #define S50_ELS_KS11_KS11_UCKDF(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UCKDF_SHIFT)) & S50_ELS_KS11_KS11_UCKDF_MASK)
62925 
62926 #define S50_ELS_KS11_KS11_UHKDF_MASK             (0x20000U)
62927 #define S50_ELS_KS11_KS11_UHKDF_SHIFT            (17U)
62928 #define S50_ELS_KS11_KS11_UHKDF(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UHKDF_SHIFT)) & S50_ELS_KS11_KS11_UHKDF_MASK)
62929 
62930 #define S50_ELS_KS11_KS11_UECSG_MASK             (0x40000U)
62931 #define S50_ELS_KS11_KS11_UECSG_SHIFT            (18U)
62932 #define S50_ELS_KS11_KS11_UECSG(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UECSG_SHIFT)) & S50_ELS_KS11_KS11_UECSG_MASK)
62933 
62934 #define S50_ELS_KS11_KS11_UECDH_MASK             (0x80000U)
62935 #define S50_ELS_KS11_KS11_UECDH_SHIFT            (19U)
62936 #define S50_ELS_KS11_KS11_UECDH(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UECDH_SHIFT)) & S50_ELS_KS11_KS11_UECDH_MASK)
62937 
62938 #define S50_ELS_KS11_KS11_UAES_MASK              (0x100000U)
62939 #define S50_ELS_KS11_KS11_UAES_SHIFT             (20U)
62940 #define S50_ELS_KS11_KS11_UAES(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UAES_SHIFT)) & S50_ELS_KS11_KS11_UAES_MASK)
62941 
62942 #define S50_ELS_KS11_KS11_UHMAC_MASK             (0x200000U)
62943 #define S50_ELS_KS11_KS11_UHMAC_SHIFT            (21U)
62944 #define S50_ELS_KS11_KS11_UHMAC(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UHMAC_SHIFT)) & S50_ELS_KS11_KS11_UHMAC_MASK)
62945 
62946 #define S50_ELS_KS11_KS11_UKWK_MASK              (0x400000U)
62947 #define S50_ELS_KS11_KS11_UKWK_SHIFT             (22U)
62948 #define S50_ELS_KS11_KS11_UKWK(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UKWK_SHIFT)) & S50_ELS_KS11_KS11_UKWK_MASK)
62949 
62950 #define S50_ELS_KS11_KS11_UKUOK_MASK             (0x800000U)
62951 #define S50_ELS_KS11_KS11_UKUOK_SHIFT            (23U)
62952 #define S50_ELS_KS11_KS11_UKUOK(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UKUOK_SHIFT)) & S50_ELS_KS11_KS11_UKUOK_MASK)
62953 
62954 #define S50_ELS_KS11_KS11_UTLSPMS_MASK           (0x1000000U)
62955 #define S50_ELS_KS11_KS11_UTLSPMS_SHIFT          (24U)
62956 #define S50_ELS_KS11_KS11_UTLSPMS(x)             (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UTLSPMS_SHIFT)) & S50_ELS_KS11_KS11_UTLSPMS_MASK)
62957 
62958 #define S50_ELS_KS11_KS11_UTLSMS_MASK            (0x2000000U)
62959 #define S50_ELS_KS11_KS11_UTLSMS_SHIFT           (25U)
62960 #define S50_ELS_KS11_KS11_UTLSMS(x)              (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UTLSMS_SHIFT)) & S50_ELS_KS11_KS11_UTLSMS_MASK)
62961 
62962 #define S50_ELS_KS11_KS11_UKGSRC_MASK            (0x4000000U)
62963 #define S50_ELS_KS11_KS11_UKGSRC_SHIFT           (26U)
62964 #define S50_ELS_KS11_KS11_UKGSRC(x)              (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UKGSRC_SHIFT)) & S50_ELS_KS11_KS11_UKGSRC_MASK)
62965 
62966 #define S50_ELS_KS11_KS11_UHWO_MASK              (0x8000000U)
62967 #define S50_ELS_KS11_KS11_UHWO_SHIFT             (27U)
62968 #define S50_ELS_KS11_KS11_UHWO(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UHWO_SHIFT)) & S50_ELS_KS11_KS11_UHWO_MASK)
62969 
62970 #define S50_ELS_KS11_KS11_UWRPOK_MASK            (0x10000000U)
62971 #define S50_ELS_KS11_KS11_UWRPOK_SHIFT           (28U)
62972 #define S50_ELS_KS11_KS11_UWRPOK(x)              (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UWRPOK_SHIFT)) & S50_ELS_KS11_KS11_UWRPOK_MASK)
62973 
62974 #define S50_ELS_KS11_KS11_UDUK_MASK              (0x20000000U)
62975 #define S50_ELS_KS11_KS11_UDUK_SHIFT             (29U)
62976 #define S50_ELS_KS11_KS11_UDUK(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UDUK_SHIFT)) & S50_ELS_KS11_KS11_UDUK_MASK)
62977 
62978 #define S50_ELS_KS11_KS11_UPPROT_MASK            (0xC0000000U)
62979 #define S50_ELS_KS11_KS11_UPPROT_SHIFT           (30U)
62980 #define S50_ELS_KS11_KS11_UPPROT(x)              (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UPPROT_SHIFT)) & S50_ELS_KS11_KS11_UPPROT_MASK)
62981 /*! @} */
62982 
62983 /*! @name ELS_KS12 - Status Register */
62984 /*! @{ */
62985 
62986 #define S50_ELS_KS12_KS12_KSIZE_MASK             (0x3U)
62987 #define S50_ELS_KS12_KS12_KSIZE_SHIFT            (0U)
62988 /*! KS12_KSIZE
62989  *  0b00..128
62990  *  0b01..256
62991  */
62992 #define S50_ELS_KS12_KS12_KSIZE(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_KSIZE_SHIFT)) & S50_ELS_KS12_KS12_KSIZE_MASK)
62993 
62994 #define S50_ELS_KS12_KS12_KACT_MASK              (0x20U)
62995 #define S50_ELS_KS12_KS12_KACT_SHIFT             (5U)
62996 #define S50_ELS_KS12_KS12_KACT(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_KACT_SHIFT)) & S50_ELS_KS12_KS12_KACT_MASK)
62997 
62998 #define S50_ELS_KS12_KS12_KBASE_MASK             (0x40U)
62999 #define S50_ELS_KS12_KS12_KBASE_SHIFT            (6U)
63000 #define S50_ELS_KS12_KS12_KBASE(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_KBASE_SHIFT)) & S50_ELS_KS12_KS12_KBASE_MASK)
63001 
63002 #define S50_ELS_KS12_KS12_FGP_MASK               (0x80U)
63003 #define S50_ELS_KS12_KS12_FGP_SHIFT              (7U)
63004 #define S50_ELS_KS12_KS12_FGP(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_FGP_SHIFT)) & S50_ELS_KS12_KS12_FGP_MASK)
63005 
63006 #define S50_ELS_KS12_KS12_FRTN_MASK              (0x100U)
63007 #define S50_ELS_KS12_KS12_FRTN_SHIFT             (8U)
63008 #define S50_ELS_KS12_KS12_FRTN(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_FRTN_SHIFT)) & S50_ELS_KS12_KS12_FRTN_MASK)
63009 
63010 #define S50_ELS_KS12_KS12_FHWO_MASK              (0x200U)
63011 #define S50_ELS_KS12_KS12_FHWO_SHIFT             (9U)
63012 #define S50_ELS_KS12_KS12_FHWO(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_FHWO_SHIFT)) & S50_ELS_KS12_KS12_FHWO_MASK)
63013 
63014 #define S50_ELS_KS12_KS12_UKPUK_MASK             (0x800U)
63015 #define S50_ELS_KS12_KS12_UKPUK_SHIFT            (11U)
63016 #define S50_ELS_KS12_KS12_UKPUK(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UKPUK_SHIFT)) & S50_ELS_KS12_KS12_UKPUK_MASK)
63017 
63018 #define S50_ELS_KS12_KS12_UTECDH_MASK            (0x1000U)
63019 #define S50_ELS_KS12_KS12_UTECDH_SHIFT           (12U)
63020 #define S50_ELS_KS12_KS12_UTECDH(x)              (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UTECDH_SHIFT)) & S50_ELS_KS12_KS12_UTECDH_MASK)
63021 
63022 #define S50_ELS_KS12_KS12_UCMAC_MASK             (0x2000U)
63023 #define S50_ELS_KS12_KS12_UCMAC_SHIFT            (13U)
63024 #define S50_ELS_KS12_KS12_UCMAC(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UCMAC_SHIFT)) & S50_ELS_KS12_KS12_UCMAC_MASK)
63025 
63026 #define S50_ELS_KS12_KS12_UKSK_MASK              (0x4000U)
63027 #define S50_ELS_KS12_KS12_UKSK_SHIFT             (14U)
63028 #define S50_ELS_KS12_KS12_UKSK(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UKSK_SHIFT)) & S50_ELS_KS12_KS12_UKSK_MASK)
63029 
63030 #define S50_ELS_KS12_KS12_URTF_MASK              (0x8000U)
63031 #define S50_ELS_KS12_KS12_URTF_SHIFT             (15U)
63032 #define S50_ELS_KS12_KS12_URTF(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_URTF_SHIFT)) & S50_ELS_KS12_KS12_URTF_MASK)
63033 
63034 #define S50_ELS_KS12_KS12_UCKDF_MASK             (0x10000U)
63035 #define S50_ELS_KS12_KS12_UCKDF_SHIFT            (16U)
63036 #define S50_ELS_KS12_KS12_UCKDF(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UCKDF_SHIFT)) & S50_ELS_KS12_KS12_UCKDF_MASK)
63037 
63038 #define S50_ELS_KS12_KS12_UHKDF_MASK             (0x20000U)
63039 #define S50_ELS_KS12_KS12_UHKDF_SHIFT            (17U)
63040 #define S50_ELS_KS12_KS12_UHKDF(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UHKDF_SHIFT)) & S50_ELS_KS12_KS12_UHKDF_MASK)
63041 
63042 #define S50_ELS_KS12_KS12_UECSG_MASK             (0x40000U)
63043 #define S50_ELS_KS12_KS12_UECSG_SHIFT            (18U)
63044 #define S50_ELS_KS12_KS12_UECSG(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UECSG_SHIFT)) & S50_ELS_KS12_KS12_UECSG_MASK)
63045 
63046 #define S50_ELS_KS12_KS12_UECDH_MASK             (0x80000U)
63047 #define S50_ELS_KS12_KS12_UECDH_SHIFT            (19U)
63048 #define S50_ELS_KS12_KS12_UECDH(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UECDH_SHIFT)) & S50_ELS_KS12_KS12_UECDH_MASK)
63049 
63050 #define S50_ELS_KS12_KS12_UAES_MASK              (0x100000U)
63051 #define S50_ELS_KS12_KS12_UAES_SHIFT             (20U)
63052 #define S50_ELS_KS12_KS12_UAES(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UAES_SHIFT)) & S50_ELS_KS12_KS12_UAES_MASK)
63053 
63054 #define S50_ELS_KS12_KS12_UHMAC_MASK             (0x200000U)
63055 #define S50_ELS_KS12_KS12_UHMAC_SHIFT            (21U)
63056 #define S50_ELS_KS12_KS12_UHMAC(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UHMAC_SHIFT)) & S50_ELS_KS12_KS12_UHMAC_MASK)
63057 
63058 #define S50_ELS_KS12_KS12_UKWK_MASK              (0x400000U)
63059 #define S50_ELS_KS12_KS12_UKWK_SHIFT             (22U)
63060 #define S50_ELS_KS12_KS12_UKWK(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UKWK_SHIFT)) & S50_ELS_KS12_KS12_UKWK_MASK)
63061 
63062 #define S50_ELS_KS12_KS12_UKUOK_MASK             (0x800000U)
63063 #define S50_ELS_KS12_KS12_UKUOK_SHIFT            (23U)
63064 #define S50_ELS_KS12_KS12_UKUOK(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UKUOK_SHIFT)) & S50_ELS_KS12_KS12_UKUOK_MASK)
63065 
63066 #define S50_ELS_KS12_KS12_UTLSPMS_MASK           (0x1000000U)
63067 #define S50_ELS_KS12_KS12_UTLSPMS_SHIFT          (24U)
63068 #define S50_ELS_KS12_KS12_UTLSPMS(x)             (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UTLSPMS_SHIFT)) & S50_ELS_KS12_KS12_UTLSPMS_MASK)
63069 
63070 #define S50_ELS_KS12_KS12_UTLSMS_MASK            (0x2000000U)
63071 #define S50_ELS_KS12_KS12_UTLSMS_SHIFT           (25U)
63072 #define S50_ELS_KS12_KS12_UTLSMS(x)              (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UTLSMS_SHIFT)) & S50_ELS_KS12_KS12_UTLSMS_MASK)
63073 
63074 #define S50_ELS_KS12_KS12_UKGSRC_MASK            (0x4000000U)
63075 #define S50_ELS_KS12_KS12_UKGSRC_SHIFT           (26U)
63076 #define S50_ELS_KS12_KS12_UKGSRC(x)              (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UKGSRC_SHIFT)) & S50_ELS_KS12_KS12_UKGSRC_MASK)
63077 
63078 #define S50_ELS_KS12_KS12_UHWO_MASK              (0x8000000U)
63079 #define S50_ELS_KS12_KS12_UHWO_SHIFT             (27U)
63080 #define S50_ELS_KS12_KS12_UHWO(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UHWO_SHIFT)) & S50_ELS_KS12_KS12_UHWO_MASK)
63081 
63082 #define S50_ELS_KS12_KS12_UWRPOK_MASK            (0x10000000U)
63083 #define S50_ELS_KS12_KS12_UWRPOK_SHIFT           (28U)
63084 #define S50_ELS_KS12_KS12_UWRPOK(x)              (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UWRPOK_SHIFT)) & S50_ELS_KS12_KS12_UWRPOK_MASK)
63085 
63086 #define S50_ELS_KS12_KS12_UDUK_MASK              (0x20000000U)
63087 #define S50_ELS_KS12_KS12_UDUK_SHIFT             (29U)
63088 #define S50_ELS_KS12_KS12_UDUK(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UDUK_SHIFT)) & S50_ELS_KS12_KS12_UDUK_MASK)
63089 
63090 #define S50_ELS_KS12_KS12_UPPROT_MASK            (0xC0000000U)
63091 #define S50_ELS_KS12_KS12_UPPROT_SHIFT           (30U)
63092 #define S50_ELS_KS12_KS12_UPPROT(x)              (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UPPROT_SHIFT)) & S50_ELS_KS12_KS12_UPPROT_MASK)
63093 /*! @} */
63094 
63095 /*! @name ELS_KS13 - Status Register */
63096 /*! @{ */
63097 
63098 #define S50_ELS_KS13_KS13_KSIZE_MASK             (0x3U)
63099 #define S50_ELS_KS13_KS13_KSIZE_SHIFT            (0U)
63100 /*! KS13_KSIZE
63101  *  0b00..128
63102  *  0b01..256
63103  */
63104 #define S50_ELS_KS13_KS13_KSIZE(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_KSIZE_SHIFT)) & S50_ELS_KS13_KS13_KSIZE_MASK)
63105 
63106 #define S50_ELS_KS13_KS13_KACT_MASK              (0x20U)
63107 #define S50_ELS_KS13_KS13_KACT_SHIFT             (5U)
63108 #define S50_ELS_KS13_KS13_KACT(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_KACT_SHIFT)) & S50_ELS_KS13_KS13_KACT_MASK)
63109 
63110 #define S50_ELS_KS13_KS13_KBASE_MASK             (0x40U)
63111 #define S50_ELS_KS13_KS13_KBASE_SHIFT            (6U)
63112 #define S50_ELS_KS13_KS13_KBASE(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_KBASE_SHIFT)) & S50_ELS_KS13_KS13_KBASE_MASK)
63113 
63114 #define S50_ELS_KS13_KS13_FGP_MASK               (0x80U)
63115 #define S50_ELS_KS13_KS13_FGP_SHIFT              (7U)
63116 #define S50_ELS_KS13_KS13_FGP(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_FGP_SHIFT)) & S50_ELS_KS13_KS13_FGP_MASK)
63117 
63118 #define S50_ELS_KS13_KS13_FRTN_MASK              (0x100U)
63119 #define S50_ELS_KS13_KS13_FRTN_SHIFT             (8U)
63120 #define S50_ELS_KS13_KS13_FRTN(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_FRTN_SHIFT)) & S50_ELS_KS13_KS13_FRTN_MASK)
63121 
63122 #define S50_ELS_KS13_KS13_FHWO_MASK              (0x200U)
63123 #define S50_ELS_KS13_KS13_FHWO_SHIFT             (9U)
63124 #define S50_ELS_KS13_KS13_FHWO(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_FHWO_SHIFT)) & S50_ELS_KS13_KS13_FHWO_MASK)
63125 
63126 #define S50_ELS_KS13_KS13_UKPUK_MASK             (0x800U)
63127 #define S50_ELS_KS13_KS13_UKPUK_SHIFT            (11U)
63128 #define S50_ELS_KS13_KS13_UKPUK(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UKPUK_SHIFT)) & S50_ELS_KS13_KS13_UKPUK_MASK)
63129 
63130 #define S50_ELS_KS13_KS13_UTECDH_MASK            (0x1000U)
63131 #define S50_ELS_KS13_KS13_UTECDH_SHIFT           (12U)
63132 #define S50_ELS_KS13_KS13_UTECDH(x)              (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UTECDH_SHIFT)) & S50_ELS_KS13_KS13_UTECDH_MASK)
63133 
63134 #define S50_ELS_KS13_KS13_UCMAC_MASK             (0x2000U)
63135 #define S50_ELS_KS13_KS13_UCMAC_SHIFT            (13U)
63136 #define S50_ELS_KS13_KS13_UCMAC(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UCMAC_SHIFT)) & S50_ELS_KS13_KS13_UCMAC_MASK)
63137 
63138 #define S50_ELS_KS13_KS13_UKSK_MASK              (0x4000U)
63139 #define S50_ELS_KS13_KS13_UKSK_SHIFT             (14U)
63140 #define S50_ELS_KS13_KS13_UKSK(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UKSK_SHIFT)) & S50_ELS_KS13_KS13_UKSK_MASK)
63141 
63142 #define S50_ELS_KS13_KS13_URTF_MASK              (0x8000U)
63143 #define S50_ELS_KS13_KS13_URTF_SHIFT             (15U)
63144 #define S50_ELS_KS13_KS13_URTF(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_URTF_SHIFT)) & S50_ELS_KS13_KS13_URTF_MASK)
63145 
63146 #define S50_ELS_KS13_KS13_UCKDF_MASK             (0x10000U)
63147 #define S50_ELS_KS13_KS13_UCKDF_SHIFT            (16U)
63148 #define S50_ELS_KS13_KS13_UCKDF(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UCKDF_SHIFT)) & S50_ELS_KS13_KS13_UCKDF_MASK)
63149 
63150 #define S50_ELS_KS13_KS13_UHKDF_MASK             (0x20000U)
63151 #define S50_ELS_KS13_KS13_UHKDF_SHIFT            (17U)
63152 #define S50_ELS_KS13_KS13_UHKDF(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UHKDF_SHIFT)) & S50_ELS_KS13_KS13_UHKDF_MASK)
63153 
63154 #define S50_ELS_KS13_KS13_UECSG_MASK             (0x40000U)
63155 #define S50_ELS_KS13_KS13_UECSG_SHIFT            (18U)
63156 #define S50_ELS_KS13_KS13_UECSG(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UECSG_SHIFT)) & S50_ELS_KS13_KS13_UECSG_MASK)
63157 
63158 #define S50_ELS_KS13_KS13_UECDH_MASK             (0x80000U)
63159 #define S50_ELS_KS13_KS13_UECDH_SHIFT            (19U)
63160 #define S50_ELS_KS13_KS13_UECDH(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UECDH_SHIFT)) & S50_ELS_KS13_KS13_UECDH_MASK)
63161 
63162 #define S50_ELS_KS13_KS13_UAES_MASK              (0x100000U)
63163 #define S50_ELS_KS13_KS13_UAES_SHIFT             (20U)
63164 #define S50_ELS_KS13_KS13_UAES(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UAES_SHIFT)) & S50_ELS_KS13_KS13_UAES_MASK)
63165 
63166 #define S50_ELS_KS13_KS13_UHMAC_MASK             (0x200000U)
63167 #define S50_ELS_KS13_KS13_UHMAC_SHIFT            (21U)
63168 #define S50_ELS_KS13_KS13_UHMAC(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UHMAC_SHIFT)) & S50_ELS_KS13_KS13_UHMAC_MASK)
63169 
63170 #define S50_ELS_KS13_KS13_UKWK_MASK              (0x400000U)
63171 #define S50_ELS_KS13_KS13_UKWK_SHIFT             (22U)
63172 #define S50_ELS_KS13_KS13_UKWK(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UKWK_SHIFT)) & S50_ELS_KS13_KS13_UKWK_MASK)
63173 
63174 #define S50_ELS_KS13_KS13_UKUOK_MASK             (0x800000U)
63175 #define S50_ELS_KS13_KS13_UKUOK_SHIFT            (23U)
63176 #define S50_ELS_KS13_KS13_UKUOK(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UKUOK_SHIFT)) & S50_ELS_KS13_KS13_UKUOK_MASK)
63177 
63178 #define S50_ELS_KS13_KS13_UTLSPMS_MASK           (0x1000000U)
63179 #define S50_ELS_KS13_KS13_UTLSPMS_SHIFT          (24U)
63180 #define S50_ELS_KS13_KS13_UTLSPMS(x)             (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UTLSPMS_SHIFT)) & S50_ELS_KS13_KS13_UTLSPMS_MASK)
63181 
63182 #define S50_ELS_KS13_KS13_UTLSMS_MASK            (0x2000000U)
63183 #define S50_ELS_KS13_KS13_UTLSMS_SHIFT           (25U)
63184 #define S50_ELS_KS13_KS13_UTLSMS(x)              (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UTLSMS_SHIFT)) & S50_ELS_KS13_KS13_UTLSMS_MASK)
63185 
63186 #define S50_ELS_KS13_KS13_UKGSRC_MASK            (0x4000000U)
63187 #define S50_ELS_KS13_KS13_UKGSRC_SHIFT           (26U)
63188 #define S50_ELS_KS13_KS13_UKGSRC(x)              (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UKGSRC_SHIFT)) & S50_ELS_KS13_KS13_UKGSRC_MASK)
63189 
63190 #define S50_ELS_KS13_KS13_UHWO_MASK              (0x8000000U)
63191 #define S50_ELS_KS13_KS13_UHWO_SHIFT             (27U)
63192 #define S50_ELS_KS13_KS13_UHWO(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UHWO_SHIFT)) & S50_ELS_KS13_KS13_UHWO_MASK)
63193 
63194 #define S50_ELS_KS13_KS13_UWRPOK_MASK            (0x10000000U)
63195 #define S50_ELS_KS13_KS13_UWRPOK_SHIFT           (28U)
63196 #define S50_ELS_KS13_KS13_UWRPOK(x)              (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UWRPOK_SHIFT)) & S50_ELS_KS13_KS13_UWRPOK_MASK)
63197 
63198 #define S50_ELS_KS13_KS13_UDUK_MASK              (0x20000000U)
63199 #define S50_ELS_KS13_KS13_UDUK_SHIFT             (29U)
63200 #define S50_ELS_KS13_KS13_UDUK(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UDUK_SHIFT)) & S50_ELS_KS13_KS13_UDUK_MASK)
63201 
63202 #define S50_ELS_KS13_KS13_UPPROT_MASK            (0xC0000000U)
63203 #define S50_ELS_KS13_KS13_UPPROT_SHIFT           (30U)
63204 #define S50_ELS_KS13_KS13_UPPROT(x)              (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UPPROT_SHIFT)) & S50_ELS_KS13_KS13_UPPROT_MASK)
63205 /*! @} */
63206 
63207 /*! @name ELS_KS14 - Status Register */
63208 /*! @{ */
63209 
63210 #define S50_ELS_KS14_KS14_KSIZE_MASK             (0x3U)
63211 #define S50_ELS_KS14_KS14_KSIZE_SHIFT            (0U)
63212 /*! KS14_KSIZE
63213  *  0b00..128
63214  *  0b01..256
63215  */
63216 #define S50_ELS_KS14_KS14_KSIZE(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_KSIZE_SHIFT)) & S50_ELS_KS14_KS14_KSIZE_MASK)
63217 
63218 #define S50_ELS_KS14_KS14_KACT_MASK              (0x20U)
63219 #define S50_ELS_KS14_KS14_KACT_SHIFT             (5U)
63220 #define S50_ELS_KS14_KS14_KACT(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_KACT_SHIFT)) & S50_ELS_KS14_KS14_KACT_MASK)
63221 
63222 #define S50_ELS_KS14_KS14_KBASE_MASK             (0x40U)
63223 #define S50_ELS_KS14_KS14_KBASE_SHIFT            (6U)
63224 #define S50_ELS_KS14_KS14_KBASE(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_KBASE_SHIFT)) & S50_ELS_KS14_KS14_KBASE_MASK)
63225 
63226 #define S50_ELS_KS14_KS14_FGP_MASK               (0x80U)
63227 #define S50_ELS_KS14_KS14_FGP_SHIFT              (7U)
63228 #define S50_ELS_KS14_KS14_FGP(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_FGP_SHIFT)) & S50_ELS_KS14_KS14_FGP_MASK)
63229 
63230 #define S50_ELS_KS14_KS14_FRTN_MASK              (0x100U)
63231 #define S50_ELS_KS14_KS14_FRTN_SHIFT             (8U)
63232 #define S50_ELS_KS14_KS14_FRTN(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_FRTN_SHIFT)) & S50_ELS_KS14_KS14_FRTN_MASK)
63233 
63234 #define S50_ELS_KS14_KS14_FHWO_MASK              (0x200U)
63235 #define S50_ELS_KS14_KS14_FHWO_SHIFT             (9U)
63236 #define S50_ELS_KS14_KS14_FHWO(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_FHWO_SHIFT)) & S50_ELS_KS14_KS14_FHWO_MASK)
63237 
63238 #define S50_ELS_KS14_KS14_UKPUK_MASK             (0x800U)
63239 #define S50_ELS_KS14_KS14_UKPUK_SHIFT            (11U)
63240 #define S50_ELS_KS14_KS14_UKPUK(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UKPUK_SHIFT)) & S50_ELS_KS14_KS14_UKPUK_MASK)
63241 
63242 #define S50_ELS_KS14_KS14_UTECDH_MASK            (0x1000U)
63243 #define S50_ELS_KS14_KS14_UTECDH_SHIFT           (12U)
63244 #define S50_ELS_KS14_KS14_UTECDH(x)              (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UTECDH_SHIFT)) & S50_ELS_KS14_KS14_UTECDH_MASK)
63245 
63246 #define S50_ELS_KS14_KS14_UCMAC_MASK             (0x2000U)
63247 #define S50_ELS_KS14_KS14_UCMAC_SHIFT            (13U)
63248 #define S50_ELS_KS14_KS14_UCMAC(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UCMAC_SHIFT)) & S50_ELS_KS14_KS14_UCMAC_MASK)
63249 
63250 #define S50_ELS_KS14_KS14_UKSK_MASK              (0x4000U)
63251 #define S50_ELS_KS14_KS14_UKSK_SHIFT             (14U)
63252 #define S50_ELS_KS14_KS14_UKSK(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UKSK_SHIFT)) & S50_ELS_KS14_KS14_UKSK_MASK)
63253 
63254 #define S50_ELS_KS14_KS14_URTF_MASK              (0x8000U)
63255 #define S50_ELS_KS14_KS14_URTF_SHIFT             (15U)
63256 #define S50_ELS_KS14_KS14_URTF(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_URTF_SHIFT)) & S50_ELS_KS14_KS14_URTF_MASK)
63257 
63258 #define S50_ELS_KS14_KS14_UCKDF_MASK             (0x10000U)
63259 #define S50_ELS_KS14_KS14_UCKDF_SHIFT            (16U)
63260 #define S50_ELS_KS14_KS14_UCKDF(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UCKDF_SHIFT)) & S50_ELS_KS14_KS14_UCKDF_MASK)
63261 
63262 #define S50_ELS_KS14_KS14_UHKDF_MASK             (0x20000U)
63263 #define S50_ELS_KS14_KS14_UHKDF_SHIFT            (17U)
63264 #define S50_ELS_KS14_KS14_UHKDF(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UHKDF_SHIFT)) & S50_ELS_KS14_KS14_UHKDF_MASK)
63265 
63266 #define S50_ELS_KS14_KS14_UECSG_MASK             (0x40000U)
63267 #define S50_ELS_KS14_KS14_UECSG_SHIFT            (18U)
63268 #define S50_ELS_KS14_KS14_UECSG(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UECSG_SHIFT)) & S50_ELS_KS14_KS14_UECSG_MASK)
63269 
63270 #define S50_ELS_KS14_KS14_UECDH_MASK             (0x80000U)
63271 #define S50_ELS_KS14_KS14_UECDH_SHIFT            (19U)
63272 #define S50_ELS_KS14_KS14_UECDH(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UECDH_SHIFT)) & S50_ELS_KS14_KS14_UECDH_MASK)
63273 
63274 #define S50_ELS_KS14_KS14_UAES_MASK              (0x100000U)
63275 #define S50_ELS_KS14_KS14_UAES_SHIFT             (20U)
63276 #define S50_ELS_KS14_KS14_UAES(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UAES_SHIFT)) & S50_ELS_KS14_KS14_UAES_MASK)
63277 
63278 #define S50_ELS_KS14_KS14_UHMAC_MASK             (0x200000U)
63279 #define S50_ELS_KS14_KS14_UHMAC_SHIFT            (21U)
63280 #define S50_ELS_KS14_KS14_UHMAC(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UHMAC_SHIFT)) & S50_ELS_KS14_KS14_UHMAC_MASK)
63281 
63282 #define S50_ELS_KS14_KS14_UKWK_MASK              (0x400000U)
63283 #define S50_ELS_KS14_KS14_UKWK_SHIFT             (22U)
63284 #define S50_ELS_KS14_KS14_UKWK(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UKWK_SHIFT)) & S50_ELS_KS14_KS14_UKWK_MASK)
63285 
63286 #define S50_ELS_KS14_KS14_UKUOK_MASK             (0x800000U)
63287 #define S50_ELS_KS14_KS14_UKUOK_SHIFT            (23U)
63288 #define S50_ELS_KS14_KS14_UKUOK(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UKUOK_SHIFT)) & S50_ELS_KS14_KS14_UKUOK_MASK)
63289 
63290 #define S50_ELS_KS14_KS14_UTLSPMS_MASK           (0x1000000U)
63291 #define S50_ELS_KS14_KS14_UTLSPMS_SHIFT          (24U)
63292 #define S50_ELS_KS14_KS14_UTLSPMS(x)             (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UTLSPMS_SHIFT)) & S50_ELS_KS14_KS14_UTLSPMS_MASK)
63293 
63294 #define S50_ELS_KS14_KS14_UTLSMS_MASK            (0x2000000U)
63295 #define S50_ELS_KS14_KS14_UTLSMS_SHIFT           (25U)
63296 #define S50_ELS_KS14_KS14_UTLSMS(x)              (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UTLSMS_SHIFT)) & S50_ELS_KS14_KS14_UTLSMS_MASK)
63297 
63298 #define S50_ELS_KS14_KS14_UKGSRC_MASK            (0x4000000U)
63299 #define S50_ELS_KS14_KS14_UKGSRC_SHIFT           (26U)
63300 #define S50_ELS_KS14_KS14_UKGSRC(x)              (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UKGSRC_SHIFT)) & S50_ELS_KS14_KS14_UKGSRC_MASK)
63301 
63302 #define S50_ELS_KS14_KS14_UHWO_MASK              (0x8000000U)
63303 #define S50_ELS_KS14_KS14_UHWO_SHIFT             (27U)
63304 #define S50_ELS_KS14_KS14_UHWO(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UHWO_SHIFT)) & S50_ELS_KS14_KS14_UHWO_MASK)
63305 
63306 #define S50_ELS_KS14_KS14_UWRPOK_MASK            (0x10000000U)
63307 #define S50_ELS_KS14_KS14_UWRPOK_SHIFT           (28U)
63308 #define S50_ELS_KS14_KS14_UWRPOK(x)              (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UWRPOK_SHIFT)) & S50_ELS_KS14_KS14_UWRPOK_MASK)
63309 
63310 #define S50_ELS_KS14_KS14_UDUK_MASK              (0x20000000U)
63311 #define S50_ELS_KS14_KS14_UDUK_SHIFT             (29U)
63312 #define S50_ELS_KS14_KS14_UDUK(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UDUK_SHIFT)) & S50_ELS_KS14_KS14_UDUK_MASK)
63313 
63314 #define S50_ELS_KS14_KS14_UPPROT_MASK            (0xC0000000U)
63315 #define S50_ELS_KS14_KS14_UPPROT_SHIFT           (30U)
63316 #define S50_ELS_KS14_KS14_UPPROT(x)              (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UPPROT_SHIFT)) & S50_ELS_KS14_KS14_UPPROT_MASK)
63317 /*! @} */
63318 
63319 /*! @name ELS_KS15 - Status Register */
63320 /*! @{ */
63321 
63322 #define S50_ELS_KS15_KS15_KSIZE_MASK             (0x3U)
63323 #define S50_ELS_KS15_KS15_KSIZE_SHIFT            (0U)
63324 /*! KS15_KSIZE
63325  *  0b00..128
63326  *  0b01..256
63327  */
63328 #define S50_ELS_KS15_KS15_KSIZE(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_KSIZE_SHIFT)) & S50_ELS_KS15_KS15_KSIZE_MASK)
63329 
63330 #define S50_ELS_KS15_KS15_KACT_MASK              (0x20U)
63331 #define S50_ELS_KS15_KS15_KACT_SHIFT             (5U)
63332 #define S50_ELS_KS15_KS15_KACT(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_KACT_SHIFT)) & S50_ELS_KS15_KS15_KACT_MASK)
63333 
63334 #define S50_ELS_KS15_KS15_KBASE_MASK             (0x40U)
63335 #define S50_ELS_KS15_KS15_KBASE_SHIFT            (6U)
63336 #define S50_ELS_KS15_KS15_KBASE(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_KBASE_SHIFT)) & S50_ELS_KS15_KS15_KBASE_MASK)
63337 
63338 #define S50_ELS_KS15_KS15_FGP_MASK               (0x80U)
63339 #define S50_ELS_KS15_KS15_FGP_SHIFT              (7U)
63340 #define S50_ELS_KS15_KS15_FGP(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_FGP_SHIFT)) & S50_ELS_KS15_KS15_FGP_MASK)
63341 
63342 #define S50_ELS_KS15_KS15_FRTN_MASK              (0x100U)
63343 #define S50_ELS_KS15_KS15_FRTN_SHIFT             (8U)
63344 #define S50_ELS_KS15_KS15_FRTN(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_FRTN_SHIFT)) & S50_ELS_KS15_KS15_FRTN_MASK)
63345 
63346 #define S50_ELS_KS15_KS15_FHWO_MASK              (0x200U)
63347 #define S50_ELS_KS15_KS15_FHWO_SHIFT             (9U)
63348 #define S50_ELS_KS15_KS15_FHWO(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_FHWO_SHIFT)) & S50_ELS_KS15_KS15_FHWO_MASK)
63349 
63350 #define S50_ELS_KS15_KS15_UKPUK_MASK             (0x800U)
63351 #define S50_ELS_KS15_KS15_UKPUK_SHIFT            (11U)
63352 #define S50_ELS_KS15_KS15_UKPUK(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UKPUK_SHIFT)) & S50_ELS_KS15_KS15_UKPUK_MASK)
63353 
63354 #define S50_ELS_KS15_KS15_UTECDH_MASK            (0x1000U)
63355 #define S50_ELS_KS15_KS15_UTECDH_SHIFT           (12U)
63356 #define S50_ELS_KS15_KS15_UTECDH(x)              (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UTECDH_SHIFT)) & S50_ELS_KS15_KS15_UTECDH_MASK)
63357 
63358 #define S50_ELS_KS15_KS15_UCMAC_MASK             (0x2000U)
63359 #define S50_ELS_KS15_KS15_UCMAC_SHIFT            (13U)
63360 #define S50_ELS_KS15_KS15_UCMAC(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UCMAC_SHIFT)) & S50_ELS_KS15_KS15_UCMAC_MASK)
63361 
63362 #define S50_ELS_KS15_KS15_UKSK_MASK              (0x4000U)
63363 #define S50_ELS_KS15_KS15_UKSK_SHIFT             (14U)
63364 #define S50_ELS_KS15_KS15_UKSK(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UKSK_SHIFT)) & S50_ELS_KS15_KS15_UKSK_MASK)
63365 
63366 #define S50_ELS_KS15_KS15_URTF_MASK              (0x8000U)
63367 #define S50_ELS_KS15_KS15_URTF_SHIFT             (15U)
63368 #define S50_ELS_KS15_KS15_URTF(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_URTF_SHIFT)) & S50_ELS_KS15_KS15_URTF_MASK)
63369 
63370 #define S50_ELS_KS15_KS15_UCKDF_MASK             (0x10000U)
63371 #define S50_ELS_KS15_KS15_UCKDF_SHIFT            (16U)
63372 #define S50_ELS_KS15_KS15_UCKDF(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UCKDF_SHIFT)) & S50_ELS_KS15_KS15_UCKDF_MASK)
63373 
63374 #define S50_ELS_KS15_KS15_UHKDF_MASK             (0x20000U)
63375 #define S50_ELS_KS15_KS15_UHKDF_SHIFT            (17U)
63376 #define S50_ELS_KS15_KS15_UHKDF(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UHKDF_SHIFT)) & S50_ELS_KS15_KS15_UHKDF_MASK)
63377 
63378 #define S50_ELS_KS15_KS15_UECSG_MASK             (0x40000U)
63379 #define S50_ELS_KS15_KS15_UECSG_SHIFT            (18U)
63380 #define S50_ELS_KS15_KS15_UECSG(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UECSG_SHIFT)) & S50_ELS_KS15_KS15_UECSG_MASK)
63381 
63382 #define S50_ELS_KS15_KS15_UECDH_MASK             (0x80000U)
63383 #define S50_ELS_KS15_KS15_UECDH_SHIFT            (19U)
63384 #define S50_ELS_KS15_KS15_UECDH(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UECDH_SHIFT)) & S50_ELS_KS15_KS15_UECDH_MASK)
63385 
63386 #define S50_ELS_KS15_KS15_UAES_MASK              (0x100000U)
63387 #define S50_ELS_KS15_KS15_UAES_SHIFT             (20U)
63388 #define S50_ELS_KS15_KS15_UAES(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UAES_SHIFT)) & S50_ELS_KS15_KS15_UAES_MASK)
63389 
63390 #define S50_ELS_KS15_KS15_UHMAC_MASK             (0x200000U)
63391 #define S50_ELS_KS15_KS15_UHMAC_SHIFT            (21U)
63392 #define S50_ELS_KS15_KS15_UHMAC(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UHMAC_SHIFT)) & S50_ELS_KS15_KS15_UHMAC_MASK)
63393 
63394 #define S50_ELS_KS15_KS15_UKWK_MASK              (0x400000U)
63395 #define S50_ELS_KS15_KS15_UKWK_SHIFT             (22U)
63396 #define S50_ELS_KS15_KS15_UKWK(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UKWK_SHIFT)) & S50_ELS_KS15_KS15_UKWK_MASK)
63397 
63398 #define S50_ELS_KS15_KS15_UKUOK_MASK             (0x800000U)
63399 #define S50_ELS_KS15_KS15_UKUOK_SHIFT            (23U)
63400 #define S50_ELS_KS15_KS15_UKUOK(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UKUOK_SHIFT)) & S50_ELS_KS15_KS15_UKUOK_MASK)
63401 
63402 #define S50_ELS_KS15_KS15_UTLSPMS_MASK           (0x1000000U)
63403 #define S50_ELS_KS15_KS15_UTLSPMS_SHIFT          (24U)
63404 #define S50_ELS_KS15_KS15_UTLSPMS(x)             (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UTLSPMS_SHIFT)) & S50_ELS_KS15_KS15_UTLSPMS_MASK)
63405 
63406 #define S50_ELS_KS15_KS15_UTLSMS_MASK            (0x2000000U)
63407 #define S50_ELS_KS15_KS15_UTLSMS_SHIFT           (25U)
63408 #define S50_ELS_KS15_KS15_UTLSMS(x)              (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UTLSMS_SHIFT)) & S50_ELS_KS15_KS15_UTLSMS_MASK)
63409 
63410 #define S50_ELS_KS15_KS15_UKGSRC_MASK            (0x4000000U)
63411 #define S50_ELS_KS15_KS15_UKGSRC_SHIFT           (26U)
63412 #define S50_ELS_KS15_KS15_UKGSRC(x)              (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UKGSRC_SHIFT)) & S50_ELS_KS15_KS15_UKGSRC_MASK)
63413 
63414 #define S50_ELS_KS15_KS15_UHWO_MASK              (0x8000000U)
63415 #define S50_ELS_KS15_KS15_UHWO_SHIFT             (27U)
63416 #define S50_ELS_KS15_KS15_UHWO(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UHWO_SHIFT)) & S50_ELS_KS15_KS15_UHWO_MASK)
63417 
63418 #define S50_ELS_KS15_KS15_UWRPOK_MASK            (0x10000000U)
63419 #define S50_ELS_KS15_KS15_UWRPOK_SHIFT           (28U)
63420 #define S50_ELS_KS15_KS15_UWRPOK(x)              (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UWRPOK_SHIFT)) & S50_ELS_KS15_KS15_UWRPOK_MASK)
63421 
63422 #define S50_ELS_KS15_KS15_UDUK_MASK              (0x20000000U)
63423 #define S50_ELS_KS15_KS15_UDUK_SHIFT             (29U)
63424 #define S50_ELS_KS15_KS15_UDUK(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UDUK_SHIFT)) & S50_ELS_KS15_KS15_UDUK_MASK)
63425 
63426 #define S50_ELS_KS15_KS15_UPPROT_MASK            (0xC0000000U)
63427 #define S50_ELS_KS15_KS15_UPPROT_SHIFT           (30U)
63428 #define S50_ELS_KS15_KS15_UPPROT(x)              (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UPPROT_SHIFT)) & S50_ELS_KS15_KS15_UPPROT_MASK)
63429 /*! @} */
63430 
63431 /*! @name ELS_KS16 - Status Register */
63432 /*! @{ */
63433 
63434 #define S50_ELS_KS16_KS16_KSIZE_MASK             (0x3U)
63435 #define S50_ELS_KS16_KS16_KSIZE_SHIFT            (0U)
63436 /*! KS16_KSIZE
63437  *  0b00..128
63438  *  0b01..256
63439  */
63440 #define S50_ELS_KS16_KS16_KSIZE(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_KSIZE_SHIFT)) & S50_ELS_KS16_KS16_KSIZE_MASK)
63441 
63442 #define S50_ELS_KS16_KS16_KACT_MASK              (0x20U)
63443 #define S50_ELS_KS16_KS16_KACT_SHIFT             (5U)
63444 #define S50_ELS_KS16_KS16_KACT(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_KACT_SHIFT)) & S50_ELS_KS16_KS16_KACT_MASK)
63445 
63446 #define S50_ELS_KS16_KS16_KBASE_MASK             (0x40U)
63447 #define S50_ELS_KS16_KS16_KBASE_SHIFT            (6U)
63448 #define S50_ELS_KS16_KS16_KBASE(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_KBASE_SHIFT)) & S50_ELS_KS16_KS16_KBASE_MASK)
63449 
63450 #define S50_ELS_KS16_KS16_FGP_MASK               (0x80U)
63451 #define S50_ELS_KS16_KS16_FGP_SHIFT              (7U)
63452 #define S50_ELS_KS16_KS16_FGP(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_FGP_SHIFT)) & S50_ELS_KS16_KS16_FGP_MASK)
63453 
63454 #define S50_ELS_KS16_KS16_FRTN_MASK              (0x100U)
63455 #define S50_ELS_KS16_KS16_FRTN_SHIFT             (8U)
63456 #define S50_ELS_KS16_KS16_FRTN(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_FRTN_SHIFT)) & S50_ELS_KS16_KS16_FRTN_MASK)
63457 
63458 #define S50_ELS_KS16_KS16_FHWO_MASK              (0x200U)
63459 #define S50_ELS_KS16_KS16_FHWO_SHIFT             (9U)
63460 #define S50_ELS_KS16_KS16_FHWO(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_FHWO_SHIFT)) & S50_ELS_KS16_KS16_FHWO_MASK)
63461 
63462 #define S50_ELS_KS16_KS16_UKPUK_MASK             (0x800U)
63463 #define S50_ELS_KS16_KS16_UKPUK_SHIFT            (11U)
63464 #define S50_ELS_KS16_KS16_UKPUK(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UKPUK_SHIFT)) & S50_ELS_KS16_KS16_UKPUK_MASK)
63465 
63466 #define S50_ELS_KS16_KS16_UTECDH_MASK            (0x1000U)
63467 #define S50_ELS_KS16_KS16_UTECDH_SHIFT           (12U)
63468 #define S50_ELS_KS16_KS16_UTECDH(x)              (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UTECDH_SHIFT)) & S50_ELS_KS16_KS16_UTECDH_MASK)
63469 
63470 #define S50_ELS_KS16_KS16_UCMAC_MASK             (0x2000U)
63471 #define S50_ELS_KS16_KS16_UCMAC_SHIFT            (13U)
63472 #define S50_ELS_KS16_KS16_UCMAC(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UCMAC_SHIFT)) & S50_ELS_KS16_KS16_UCMAC_MASK)
63473 
63474 #define S50_ELS_KS16_KS16_UKSK_MASK              (0x4000U)
63475 #define S50_ELS_KS16_KS16_UKSK_SHIFT             (14U)
63476 #define S50_ELS_KS16_KS16_UKSK(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UKSK_SHIFT)) & S50_ELS_KS16_KS16_UKSK_MASK)
63477 
63478 #define S50_ELS_KS16_KS16_URTF_MASK              (0x8000U)
63479 #define S50_ELS_KS16_KS16_URTF_SHIFT             (15U)
63480 #define S50_ELS_KS16_KS16_URTF(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_URTF_SHIFT)) & S50_ELS_KS16_KS16_URTF_MASK)
63481 
63482 #define S50_ELS_KS16_KS16_UCKDF_MASK             (0x10000U)
63483 #define S50_ELS_KS16_KS16_UCKDF_SHIFT            (16U)
63484 #define S50_ELS_KS16_KS16_UCKDF(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UCKDF_SHIFT)) & S50_ELS_KS16_KS16_UCKDF_MASK)
63485 
63486 #define S50_ELS_KS16_KS16_UHKDF_MASK             (0x20000U)
63487 #define S50_ELS_KS16_KS16_UHKDF_SHIFT            (17U)
63488 #define S50_ELS_KS16_KS16_UHKDF(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UHKDF_SHIFT)) & S50_ELS_KS16_KS16_UHKDF_MASK)
63489 
63490 #define S50_ELS_KS16_KS16_UECSG_MASK             (0x40000U)
63491 #define S50_ELS_KS16_KS16_UECSG_SHIFT            (18U)
63492 #define S50_ELS_KS16_KS16_UECSG(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UECSG_SHIFT)) & S50_ELS_KS16_KS16_UECSG_MASK)
63493 
63494 #define S50_ELS_KS16_KS16_UECDH_MASK             (0x80000U)
63495 #define S50_ELS_KS16_KS16_UECDH_SHIFT            (19U)
63496 #define S50_ELS_KS16_KS16_UECDH(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UECDH_SHIFT)) & S50_ELS_KS16_KS16_UECDH_MASK)
63497 
63498 #define S50_ELS_KS16_KS16_UAES_MASK              (0x100000U)
63499 #define S50_ELS_KS16_KS16_UAES_SHIFT             (20U)
63500 #define S50_ELS_KS16_KS16_UAES(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UAES_SHIFT)) & S50_ELS_KS16_KS16_UAES_MASK)
63501 
63502 #define S50_ELS_KS16_KS16_UHMAC_MASK             (0x200000U)
63503 #define S50_ELS_KS16_KS16_UHMAC_SHIFT            (21U)
63504 #define S50_ELS_KS16_KS16_UHMAC(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UHMAC_SHIFT)) & S50_ELS_KS16_KS16_UHMAC_MASK)
63505 
63506 #define S50_ELS_KS16_KS16_UKWK_MASK              (0x400000U)
63507 #define S50_ELS_KS16_KS16_UKWK_SHIFT             (22U)
63508 #define S50_ELS_KS16_KS16_UKWK(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UKWK_SHIFT)) & S50_ELS_KS16_KS16_UKWK_MASK)
63509 
63510 #define S50_ELS_KS16_KS16_UKUOK_MASK             (0x800000U)
63511 #define S50_ELS_KS16_KS16_UKUOK_SHIFT            (23U)
63512 #define S50_ELS_KS16_KS16_UKUOK(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UKUOK_SHIFT)) & S50_ELS_KS16_KS16_UKUOK_MASK)
63513 
63514 #define S50_ELS_KS16_KS16_UTLSPMS_MASK           (0x1000000U)
63515 #define S50_ELS_KS16_KS16_UTLSPMS_SHIFT          (24U)
63516 #define S50_ELS_KS16_KS16_UTLSPMS(x)             (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UTLSPMS_SHIFT)) & S50_ELS_KS16_KS16_UTLSPMS_MASK)
63517 
63518 #define S50_ELS_KS16_KS16_UTLSMS_MASK            (0x2000000U)
63519 #define S50_ELS_KS16_KS16_UTLSMS_SHIFT           (25U)
63520 #define S50_ELS_KS16_KS16_UTLSMS(x)              (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UTLSMS_SHIFT)) & S50_ELS_KS16_KS16_UTLSMS_MASK)
63521 
63522 #define S50_ELS_KS16_KS16_UKGSRC_MASK            (0x4000000U)
63523 #define S50_ELS_KS16_KS16_UKGSRC_SHIFT           (26U)
63524 #define S50_ELS_KS16_KS16_UKGSRC(x)              (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UKGSRC_SHIFT)) & S50_ELS_KS16_KS16_UKGSRC_MASK)
63525 
63526 #define S50_ELS_KS16_KS16_UHWO_MASK              (0x8000000U)
63527 #define S50_ELS_KS16_KS16_UHWO_SHIFT             (27U)
63528 #define S50_ELS_KS16_KS16_UHWO(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UHWO_SHIFT)) & S50_ELS_KS16_KS16_UHWO_MASK)
63529 
63530 #define S50_ELS_KS16_KS16_UWRPOK_MASK            (0x10000000U)
63531 #define S50_ELS_KS16_KS16_UWRPOK_SHIFT           (28U)
63532 #define S50_ELS_KS16_KS16_UWRPOK(x)              (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UWRPOK_SHIFT)) & S50_ELS_KS16_KS16_UWRPOK_MASK)
63533 
63534 #define S50_ELS_KS16_KS16_UDUK_MASK              (0x20000000U)
63535 #define S50_ELS_KS16_KS16_UDUK_SHIFT             (29U)
63536 #define S50_ELS_KS16_KS16_UDUK(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UDUK_SHIFT)) & S50_ELS_KS16_KS16_UDUK_MASK)
63537 
63538 #define S50_ELS_KS16_KS16_UPPROT_MASK            (0xC0000000U)
63539 #define S50_ELS_KS16_KS16_UPPROT_SHIFT           (30U)
63540 #define S50_ELS_KS16_KS16_UPPROT(x)              (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UPPROT_SHIFT)) & S50_ELS_KS16_KS16_UPPROT_MASK)
63541 /*! @} */
63542 
63543 /*! @name ELS_KS17 - Status Register */
63544 /*! @{ */
63545 
63546 #define S50_ELS_KS17_KS17_KSIZE_MASK             (0x3U)
63547 #define S50_ELS_KS17_KS17_KSIZE_SHIFT            (0U)
63548 /*! KS17_KSIZE
63549  *  0b00..128
63550  *  0b01..256
63551  */
63552 #define S50_ELS_KS17_KS17_KSIZE(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_KSIZE_SHIFT)) & S50_ELS_KS17_KS17_KSIZE_MASK)
63553 
63554 #define S50_ELS_KS17_KS17_KACT_MASK              (0x20U)
63555 #define S50_ELS_KS17_KS17_KACT_SHIFT             (5U)
63556 #define S50_ELS_KS17_KS17_KACT(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_KACT_SHIFT)) & S50_ELS_KS17_KS17_KACT_MASK)
63557 
63558 #define S50_ELS_KS17_KS17_KBASE_MASK             (0x40U)
63559 #define S50_ELS_KS17_KS17_KBASE_SHIFT            (6U)
63560 #define S50_ELS_KS17_KS17_KBASE(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_KBASE_SHIFT)) & S50_ELS_KS17_KS17_KBASE_MASK)
63561 
63562 #define S50_ELS_KS17_KS17_FGP_MASK               (0x80U)
63563 #define S50_ELS_KS17_KS17_FGP_SHIFT              (7U)
63564 #define S50_ELS_KS17_KS17_FGP(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_FGP_SHIFT)) & S50_ELS_KS17_KS17_FGP_MASK)
63565 
63566 #define S50_ELS_KS17_KS17_FRTN_MASK              (0x100U)
63567 #define S50_ELS_KS17_KS17_FRTN_SHIFT             (8U)
63568 #define S50_ELS_KS17_KS17_FRTN(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_FRTN_SHIFT)) & S50_ELS_KS17_KS17_FRTN_MASK)
63569 
63570 #define S50_ELS_KS17_KS17_FHWO_MASK              (0x200U)
63571 #define S50_ELS_KS17_KS17_FHWO_SHIFT             (9U)
63572 #define S50_ELS_KS17_KS17_FHWO(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_FHWO_SHIFT)) & S50_ELS_KS17_KS17_FHWO_MASK)
63573 
63574 #define S50_ELS_KS17_KS17_UKPUK_MASK             (0x800U)
63575 #define S50_ELS_KS17_KS17_UKPUK_SHIFT            (11U)
63576 #define S50_ELS_KS17_KS17_UKPUK(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UKPUK_SHIFT)) & S50_ELS_KS17_KS17_UKPUK_MASK)
63577 
63578 #define S50_ELS_KS17_KS17_UTECDH_MASK            (0x1000U)
63579 #define S50_ELS_KS17_KS17_UTECDH_SHIFT           (12U)
63580 #define S50_ELS_KS17_KS17_UTECDH(x)              (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UTECDH_SHIFT)) & S50_ELS_KS17_KS17_UTECDH_MASK)
63581 
63582 #define S50_ELS_KS17_KS17_UCMAC_MASK             (0x2000U)
63583 #define S50_ELS_KS17_KS17_UCMAC_SHIFT            (13U)
63584 #define S50_ELS_KS17_KS17_UCMAC(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UCMAC_SHIFT)) & S50_ELS_KS17_KS17_UCMAC_MASK)
63585 
63586 #define S50_ELS_KS17_KS17_UKSK_MASK              (0x4000U)
63587 #define S50_ELS_KS17_KS17_UKSK_SHIFT             (14U)
63588 #define S50_ELS_KS17_KS17_UKSK(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UKSK_SHIFT)) & S50_ELS_KS17_KS17_UKSK_MASK)
63589 
63590 #define S50_ELS_KS17_KS17_URTF_MASK              (0x8000U)
63591 #define S50_ELS_KS17_KS17_URTF_SHIFT             (15U)
63592 #define S50_ELS_KS17_KS17_URTF(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_URTF_SHIFT)) & S50_ELS_KS17_KS17_URTF_MASK)
63593 
63594 #define S50_ELS_KS17_KS17_UCKDF_MASK             (0x10000U)
63595 #define S50_ELS_KS17_KS17_UCKDF_SHIFT            (16U)
63596 #define S50_ELS_KS17_KS17_UCKDF(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UCKDF_SHIFT)) & S50_ELS_KS17_KS17_UCKDF_MASK)
63597 
63598 #define S50_ELS_KS17_KS17_UHKDF_MASK             (0x20000U)
63599 #define S50_ELS_KS17_KS17_UHKDF_SHIFT            (17U)
63600 #define S50_ELS_KS17_KS17_UHKDF(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UHKDF_SHIFT)) & S50_ELS_KS17_KS17_UHKDF_MASK)
63601 
63602 #define S50_ELS_KS17_KS17_UECSG_MASK             (0x40000U)
63603 #define S50_ELS_KS17_KS17_UECSG_SHIFT            (18U)
63604 #define S50_ELS_KS17_KS17_UECSG(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UECSG_SHIFT)) & S50_ELS_KS17_KS17_UECSG_MASK)
63605 
63606 #define S50_ELS_KS17_KS17_UECDH_MASK             (0x80000U)
63607 #define S50_ELS_KS17_KS17_UECDH_SHIFT            (19U)
63608 #define S50_ELS_KS17_KS17_UECDH(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UECDH_SHIFT)) & S50_ELS_KS17_KS17_UECDH_MASK)
63609 
63610 #define S50_ELS_KS17_KS17_UAES_MASK              (0x100000U)
63611 #define S50_ELS_KS17_KS17_UAES_SHIFT             (20U)
63612 #define S50_ELS_KS17_KS17_UAES(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UAES_SHIFT)) & S50_ELS_KS17_KS17_UAES_MASK)
63613 
63614 #define S50_ELS_KS17_KS17_UHMAC_MASK             (0x200000U)
63615 #define S50_ELS_KS17_KS17_UHMAC_SHIFT            (21U)
63616 #define S50_ELS_KS17_KS17_UHMAC(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UHMAC_SHIFT)) & S50_ELS_KS17_KS17_UHMAC_MASK)
63617 
63618 #define S50_ELS_KS17_KS17_UKWK_MASK              (0x400000U)
63619 #define S50_ELS_KS17_KS17_UKWK_SHIFT             (22U)
63620 #define S50_ELS_KS17_KS17_UKWK(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UKWK_SHIFT)) & S50_ELS_KS17_KS17_UKWK_MASK)
63621 
63622 #define S50_ELS_KS17_KS17_UKUOK_MASK             (0x800000U)
63623 #define S50_ELS_KS17_KS17_UKUOK_SHIFT            (23U)
63624 #define S50_ELS_KS17_KS17_UKUOK(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UKUOK_SHIFT)) & S50_ELS_KS17_KS17_UKUOK_MASK)
63625 
63626 #define S50_ELS_KS17_KS17_UTLSPMS_MASK           (0x1000000U)
63627 #define S50_ELS_KS17_KS17_UTLSPMS_SHIFT          (24U)
63628 #define S50_ELS_KS17_KS17_UTLSPMS(x)             (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UTLSPMS_SHIFT)) & S50_ELS_KS17_KS17_UTLSPMS_MASK)
63629 
63630 #define S50_ELS_KS17_KS17_UTLSMS_MASK            (0x2000000U)
63631 #define S50_ELS_KS17_KS17_UTLSMS_SHIFT           (25U)
63632 #define S50_ELS_KS17_KS17_UTLSMS(x)              (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UTLSMS_SHIFT)) & S50_ELS_KS17_KS17_UTLSMS_MASK)
63633 
63634 #define S50_ELS_KS17_KS17_UKGSRC_MASK            (0x4000000U)
63635 #define S50_ELS_KS17_KS17_UKGSRC_SHIFT           (26U)
63636 #define S50_ELS_KS17_KS17_UKGSRC(x)              (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UKGSRC_SHIFT)) & S50_ELS_KS17_KS17_UKGSRC_MASK)
63637 
63638 #define S50_ELS_KS17_KS17_UHWO_MASK              (0x8000000U)
63639 #define S50_ELS_KS17_KS17_UHWO_SHIFT             (27U)
63640 #define S50_ELS_KS17_KS17_UHWO(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UHWO_SHIFT)) & S50_ELS_KS17_KS17_UHWO_MASK)
63641 
63642 #define S50_ELS_KS17_KS17_UWRPOK_MASK            (0x10000000U)
63643 #define S50_ELS_KS17_KS17_UWRPOK_SHIFT           (28U)
63644 #define S50_ELS_KS17_KS17_UWRPOK(x)              (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UWRPOK_SHIFT)) & S50_ELS_KS17_KS17_UWRPOK_MASK)
63645 
63646 #define S50_ELS_KS17_KS17_UDUK_MASK              (0x20000000U)
63647 #define S50_ELS_KS17_KS17_UDUK_SHIFT             (29U)
63648 #define S50_ELS_KS17_KS17_UDUK(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UDUK_SHIFT)) & S50_ELS_KS17_KS17_UDUK_MASK)
63649 
63650 #define S50_ELS_KS17_KS17_UPPROT_MASK            (0xC0000000U)
63651 #define S50_ELS_KS17_KS17_UPPROT_SHIFT           (30U)
63652 #define S50_ELS_KS17_KS17_UPPROT(x)              (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UPPROT_SHIFT)) & S50_ELS_KS17_KS17_UPPROT_MASK)
63653 /*! @} */
63654 
63655 /*! @name ELS_KS18 - Status Register */
63656 /*! @{ */
63657 
63658 #define S50_ELS_KS18_KS18_KSIZE_MASK             (0x3U)
63659 #define S50_ELS_KS18_KS18_KSIZE_SHIFT            (0U)
63660 /*! KS18_KSIZE
63661  *  0b00..128
63662  *  0b01..256
63663  */
63664 #define S50_ELS_KS18_KS18_KSIZE(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_KSIZE_SHIFT)) & S50_ELS_KS18_KS18_KSIZE_MASK)
63665 
63666 #define S50_ELS_KS18_KS18_KACT_MASK              (0x20U)
63667 #define S50_ELS_KS18_KS18_KACT_SHIFT             (5U)
63668 #define S50_ELS_KS18_KS18_KACT(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_KACT_SHIFT)) & S50_ELS_KS18_KS18_KACT_MASK)
63669 
63670 #define S50_ELS_KS18_KS18_KBASE_MASK             (0x40U)
63671 #define S50_ELS_KS18_KS18_KBASE_SHIFT            (6U)
63672 #define S50_ELS_KS18_KS18_KBASE(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_KBASE_SHIFT)) & S50_ELS_KS18_KS18_KBASE_MASK)
63673 
63674 #define S50_ELS_KS18_KS18_FGP_MASK               (0x80U)
63675 #define S50_ELS_KS18_KS18_FGP_SHIFT              (7U)
63676 #define S50_ELS_KS18_KS18_FGP(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_FGP_SHIFT)) & S50_ELS_KS18_KS18_FGP_MASK)
63677 
63678 #define S50_ELS_KS18_KS18_FRTN_MASK              (0x100U)
63679 #define S50_ELS_KS18_KS18_FRTN_SHIFT             (8U)
63680 #define S50_ELS_KS18_KS18_FRTN(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_FRTN_SHIFT)) & S50_ELS_KS18_KS18_FRTN_MASK)
63681 
63682 #define S50_ELS_KS18_KS18_FHWO_MASK              (0x200U)
63683 #define S50_ELS_KS18_KS18_FHWO_SHIFT             (9U)
63684 #define S50_ELS_KS18_KS18_FHWO(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_FHWO_SHIFT)) & S50_ELS_KS18_KS18_FHWO_MASK)
63685 
63686 #define S50_ELS_KS18_KS18_UKPUK_MASK             (0x800U)
63687 #define S50_ELS_KS18_KS18_UKPUK_SHIFT            (11U)
63688 #define S50_ELS_KS18_KS18_UKPUK(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UKPUK_SHIFT)) & S50_ELS_KS18_KS18_UKPUK_MASK)
63689 
63690 #define S50_ELS_KS18_KS18_UTECDH_MASK            (0x1000U)
63691 #define S50_ELS_KS18_KS18_UTECDH_SHIFT           (12U)
63692 #define S50_ELS_KS18_KS18_UTECDH(x)              (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UTECDH_SHIFT)) & S50_ELS_KS18_KS18_UTECDH_MASK)
63693 
63694 #define S50_ELS_KS18_KS18_UCMAC_MASK             (0x2000U)
63695 #define S50_ELS_KS18_KS18_UCMAC_SHIFT            (13U)
63696 #define S50_ELS_KS18_KS18_UCMAC(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UCMAC_SHIFT)) & S50_ELS_KS18_KS18_UCMAC_MASK)
63697 
63698 #define S50_ELS_KS18_KS18_UKSK_MASK              (0x4000U)
63699 #define S50_ELS_KS18_KS18_UKSK_SHIFT             (14U)
63700 #define S50_ELS_KS18_KS18_UKSK(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UKSK_SHIFT)) & S50_ELS_KS18_KS18_UKSK_MASK)
63701 
63702 #define S50_ELS_KS18_KS18_URTF_MASK              (0x8000U)
63703 #define S50_ELS_KS18_KS18_URTF_SHIFT             (15U)
63704 #define S50_ELS_KS18_KS18_URTF(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_URTF_SHIFT)) & S50_ELS_KS18_KS18_URTF_MASK)
63705 
63706 #define S50_ELS_KS18_KS18_UCKDF_MASK             (0x10000U)
63707 #define S50_ELS_KS18_KS18_UCKDF_SHIFT            (16U)
63708 #define S50_ELS_KS18_KS18_UCKDF(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UCKDF_SHIFT)) & S50_ELS_KS18_KS18_UCKDF_MASK)
63709 
63710 #define S50_ELS_KS18_KS18_UHKDF_MASK             (0x20000U)
63711 #define S50_ELS_KS18_KS18_UHKDF_SHIFT            (17U)
63712 #define S50_ELS_KS18_KS18_UHKDF(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UHKDF_SHIFT)) & S50_ELS_KS18_KS18_UHKDF_MASK)
63713 
63714 #define S50_ELS_KS18_KS18_UECSG_MASK             (0x40000U)
63715 #define S50_ELS_KS18_KS18_UECSG_SHIFT            (18U)
63716 #define S50_ELS_KS18_KS18_UECSG(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UECSG_SHIFT)) & S50_ELS_KS18_KS18_UECSG_MASK)
63717 
63718 #define S50_ELS_KS18_KS18_UECDH_MASK             (0x80000U)
63719 #define S50_ELS_KS18_KS18_UECDH_SHIFT            (19U)
63720 #define S50_ELS_KS18_KS18_UECDH(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UECDH_SHIFT)) & S50_ELS_KS18_KS18_UECDH_MASK)
63721 
63722 #define S50_ELS_KS18_KS18_UAES_MASK              (0x100000U)
63723 #define S50_ELS_KS18_KS18_UAES_SHIFT             (20U)
63724 #define S50_ELS_KS18_KS18_UAES(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UAES_SHIFT)) & S50_ELS_KS18_KS18_UAES_MASK)
63725 
63726 #define S50_ELS_KS18_KS18_UHMAC_MASK             (0x200000U)
63727 #define S50_ELS_KS18_KS18_UHMAC_SHIFT            (21U)
63728 #define S50_ELS_KS18_KS18_UHMAC(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UHMAC_SHIFT)) & S50_ELS_KS18_KS18_UHMAC_MASK)
63729 
63730 #define S50_ELS_KS18_KS18_UKWK_MASK              (0x400000U)
63731 #define S50_ELS_KS18_KS18_UKWK_SHIFT             (22U)
63732 #define S50_ELS_KS18_KS18_UKWK(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UKWK_SHIFT)) & S50_ELS_KS18_KS18_UKWK_MASK)
63733 
63734 #define S50_ELS_KS18_KS18_UKUOK_MASK             (0x800000U)
63735 #define S50_ELS_KS18_KS18_UKUOK_SHIFT            (23U)
63736 #define S50_ELS_KS18_KS18_UKUOK(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UKUOK_SHIFT)) & S50_ELS_KS18_KS18_UKUOK_MASK)
63737 
63738 #define S50_ELS_KS18_KS18_UTLSPMS_MASK           (0x1000000U)
63739 #define S50_ELS_KS18_KS18_UTLSPMS_SHIFT          (24U)
63740 #define S50_ELS_KS18_KS18_UTLSPMS(x)             (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UTLSPMS_SHIFT)) & S50_ELS_KS18_KS18_UTLSPMS_MASK)
63741 
63742 #define S50_ELS_KS18_KS18_UTLSMS_MASK            (0x2000000U)
63743 #define S50_ELS_KS18_KS18_UTLSMS_SHIFT           (25U)
63744 #define S50_ELS_KS18_KS18_UTLSMS(x)              (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UTLSMS_SHIFT)) & S50_ELS_KS18_KS18_UTLSMS_MASK)
63745 
63746 #define S50_ELS_KS18_KS18_UKGSRC_MASK            (0x4000000U)
63747 #define S50_ELS_KS18_KS18_UKGSRC_SHIFT           (26U)
63748 #define S50_ELS_KS18_KS18_UKGSRC(x)              (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UKGSRC_SHIFT)) & S50_ELS_KS18_KS18_UKGSRC_MASK)
63749 
63750 #define S50_ELS_KS18_KS18_UHWO_MASK              (0x8000000U)
63751 #define S50_ELS_KS18_KS18_UHWO_SHIFT             (27U)
63752 #define S50_ELS_KS18_KS18_UHWO(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UHWO_SHIFT)) & S50_ELS_KS18_KS18_UHWO_MASK)
63753 
63754 #define S50_ELS_KS18_KS18_UWRPOK_MASK            (0x10000000U)
63755 #define S50_ELS_KS18_KS18_UWRPOK_SHIFT           (28U)
63756 #define S50_ELS_KS18_KS18_UWRPOK(x)              (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UWRPOK_SHIFT)) & S50_ELS_KS18_KS18_UWRPOK_MASK)
63757 
63758 #define S50_ELS_KS18_KS18_UDUK_MASK              (0x20000000U)
63759 #define S50_ELS_KS18_KS18_UDUK_SHIFT             (29U)
63760 #define S50_ELS_KS18_KS18_UDUK(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UDUK_SHIFT)) & S50_ELS_KS18_KS18_UDUK_MASK)
63761 
63762 #define S50_ELS_KS18_KS18_UPPROT_MASK            (0xC0000000U)
63763 #define S50_ELS_KS18_KS18_UPPROT_SHIFT           (30U)
63764 #define S50_ELS_KS18_KS18_UPPROT(x)              (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UPPROT_SHIFT)) & S50_ELS_KS18_KS18_UPPROT_MASK)
63765 /*! @} */
63766 
63767 /*! @name ELS_KS19 - Status Register */
63768 /*! @{ */
63769 
63770 #define S50_ELS_KS19_KS19_KSIZE_MASK             (0x3U)
63771 #define S50_ELS_KS19_KS19_KSIZE_SHIFT            (0U)
63772 /*! KS19_KSIZE
63773  *  0b00..128
63774  *  0b01..256
63775  */
63776 #define S50_ELS_KS19_KS19_KSIZE(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_KSIZE_SHIFT)) & S50_ELS_KS19_KS19_KSIZE_MASK)
63777 
63778 #define S50_ELS_KS19_KS19_KACT_MASK              (0x20U)
63779 #define S50_ELS_KS19_KS19_KACT_SHIFT             (5U)
63780 #define S50_ELS_KS19_KS19_KACT(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_KACT_SHIFT)) & S50_ELS_KS19_KS19_KACT_MASK)
63781 
63782 #define S50_ELS_KS19_KS19_KBASE_MASK             (0x40U)
63783 #define S50_ELS_KS19_KS19_KBASE_SHIFT            (6U)
63784 #define S50_ELS_KS19_KS19_KBASE(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_KBASE_SHIFT)) & S50_ELS_KS19_KS19_KBASE_MASK)
63785 
63786 #define S50_ELS_KS19_KS19_FGP_MASK               (0x80U)
63787 #define S50_ELS_KS19_KS19_FGP_SHIFT              (7U)
63788 #define S50_ELS_KS19_KS19_FGP(x)                 (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_FGP_SHIFT)) & S50_ELS_KS19_KS19_FGP_MASK)
63789 
63790 #define S50_ELS_KS19_KS19_FRTN_MASK              (0x100U)
63791 #define S50_ELS_KS19_KS19_FRTN_SHIFT             (8U)
63792 #define S50_ELS_KS19_KS19_FRTN(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_FRTN_SHIFT)) & S50_ELS_KS19_KS19_FRTN_MASK)
63793 
63794 #define S50_ELS_KS19_KS19_FHWO_MASK              (0x200U)
63795 #define S50_ELS_KS19_KS19_FHWO_SHIFT             (9U)
63796 #define S50_ELS_KS19_KS19_FHWO(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_FHWO_SHIFT)) & S50_ELS_KS19_KS19_FHWO_MASK)
63797 
63798 #define S50_ELS_KS19_KS19_UKPUK_MASK             (0x800U)
63799 #define S50_ELS_KS19_KS19_UKPUK_SHIFT            (11U)
63800 #define S50_ELS_KS19_KS19_UKPUK(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UKPUK_SHIFT)) & S50_ELS_KS19_KS19_UKPUK_MASK)
63801 
63802 #define S50_ELS_KS19_KS19_UTECDH_MASK            (0x1000U)
63803 #define S50_ELS_KS19_KS19_UTECDH_SHIFT           (12U)
63804 #define S50_ELS_KS19_KS19_UTECDH(x)              (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UTECDH_SHIFT)) & S50_ELS_KS19_KS19_UTECDH_MASK)
63805 
63806 #define S50_ELS_KS19_KS19_UCMAC_MASK             (0x2000U)
63807 #define S50_ELS_KS19_KS19_UCMAC_SHIFT            (13U)
63808 #define S50_ELS_KS19_KS19_UCMAC(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UCMAC_SHIFT)) & S50_ELS_KS19_KS19_UCMAC_MASK)
63809 
63810 #define S50_ELS_KS19_KS19_UKSK_MASK              (0x4000U)
63811 #define S50_ELS_KS19_KS19_UKSK_SHIFT             (14U)
63812 #define S50_ELS_KS19_KS19_UKSK(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UKSK_SHIFT)) & S50_ELS_KS19_KS19_UKSK_MASK)
63813 
63814 #define S50_ELS_KS19_KS19_URTF_MASK              (0x8000U)
63815 #define S50_ELS_KS19_KS19_URTF_SHIFT             (15U)
63816 #define S50_ELS_KS19_KS19_URTF(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_URTF_SHIFT)) & S50_ELS_KS19_KS19_URTF_MASK)
63817 
63818 #define S50_ELS_KS19_KS19_UCKDF_MASK             (0x10000U)
63819 #define S50_ELS_KS19_KS19_UCKDF_SHIFT            (16U)
63820 #define S50_ELS_KS19_KS19_UCKDF(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UCKDF_SHIFT)) & S50_ELS_KS19_KS19_UCKDF_MASK)
63821 
63822 #define S50_ELS_KS19_KS19_UHKDF_MASK             (0x20000U)
63823 #define S50_ELS_KS19_KS19_UHKDF_SHIFT            (17U)
63824 #define S50_ELS_KS19_KS19_UHKDF(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UHKDF_SHIFT)) & S50_ELS_KS19_KS19_UHKDF_MASK)
63825 
63826 #define S50_ELS_KS19_KS19_UECSG_MASK             (0x40000U)
63827 #define S50_ELS_KS19_KS19_UECSG_SHIFT            (18U)
63828 #define S50_ELS_KS19_KS19_UECSG(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UECSG_SHIFT)) & S50_ELS_KS19_KS19_UECSG_MASK)
63829 
63830 #define S50_ELS_KS19_KS19_UECDH_MASK             (0x80000U)
63831 #define S50_ELS_KS19_KS19_UECDH_SHIFT            (19U)
63832 #define S50_ELS_KS19_KS19_UECDH(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UECDH_SHIFT)) & S50_ELS_KS19_KS19_UECDH_MASK)
63833 
63834 #define S50_ELS_KS19_KS19_UAES_MASK              (0x100000U)
63835 #define S50_ELS_KS19_KS19_UAES_SHIFT             (20U)
63836 #define S50_ELS_KS19_KS19_UAES(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UAES_SHIFT)) & S50_ELS_KS19_KS19_UAES_MASK)
63837 
63838 #define S50_ELS_KS19_KS19_UHMAC_MASK             (0x200000U)
63839 #define S50_ELS_KS19_KS19_UHMAC_SHIFT            (21U)
63840 #define S50_ELS_KS19_KS19_UHMAC(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UHMAC_SHIFT)) & S50_ELS_KS19_KS19_UHMAC_MASK)
63841 
63842 #define S50_ELS_KS19_KS19_UKWK_MASK              (0x400000U)
63843 #define S50_ELS_KS19_KS19_UKWK_SHIFT             (22U)
63844 #define S50_ELS_KS19_KS19_UKWK(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UKWK_SHIFT)) & S50_ELS_KS19_KS19_UKWK_MASK)
63845 
63846 #define S50_ELS_KS19_KS19_UKUOK_MASK             (0x800000U)
63847 #define S50_ELS_KS19_KS19_UKUOK_SHIFT            (23U)
63848 #define S50_ELS_KS19_KS19_UKUOK(x)               (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UKUOK_SHIFT)) & S50_ELS_KS19_KS19_UKUOK_MASK)
63849 
63850 #define S50_ELS_KS19_KS19_UTLSPMS_MASK           (0x1000000U)
63851 #define S50_ELS_KS19_KS19_UTLSPMS_SHIFT          (24U)
63852 #define S50_ELS_KS19_KS19_UTLSPMS(x)             (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UTLSPMS_SHIFT)) & S50_ELS_KS19_KS19_UTLSPMS_MASK)
63853 
63854 #define S50_ELS_KS19_KS19_UTLSMS_MASK            (0x2000000U)
63855 #define S50_ELS_KS19_KS19_UTLSMS_SHIFT           (25U)
63856 #define S50_ELS_KS19_KS19_UTLSMS(x)              (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UTLSMS_SHIFT)) & S50_ELS_KS19_KS19_UTLSMS_MASK)
63857 
63858 #define S50_ELS_KS19_KS19_UKGSRC_MASK            (0x4000000U)
63859 #define S50_ELS_KS19_KS19_UKGSRC_SHIFT           (26U)
63860 #define S50_ELS_KS19_KS19_UKGSRC(x)              (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UKGSRC_SHIFT)) & S50_ELS_KS19_KS19_UKGSRC_MASK)
63861 
63862 #define S50_ELS_KS19_KS19_UHWO_MASK              (0x8000000U)
63863 #define S50_ELS_KS19_KS19_UHWO_SHIFT             (27U)
63864 #define S50_ELS_KS19_KS19_UHWO(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UHWO_SHIFT)) & S50_ELS_KS19_KS19_UHWO_MASK)
63865 
63866 #define S50_ELS_KS19_KS19_UWRPOK_MASK            (0x10000000U)
63867 #define S50_ELS_KS19_KS19_UWRPOK_SHIFT           (28U)
63868 #define S50_ELS_KS19_KS19_UWRPOK(x)              (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UWRPOK_SHIFT)) & S50_ELS_KS19_KS19_UWRPOK_MASK)
63869 
63870 #define S50_ELS_KS19_KS19_UDUK_MASK              (0x20000000U)
63871 #define S50_ELS_KS19_KS19_UDUK_SHIFT             (29U)
63872 #define S50_ELS_KS19_KS19_UDUK(x)                (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UDUK_SHIFT)) & S50_ELS_KS19_KS19_UDUK_MASK)
63873 
63874 #define S50_ELS_KS19_KS19_UPPROT_MASK            (0xC0000000U)
63875 #define S50_ELS_KS19_KS19_UPPROT_SHIFT           (30U)
63876 #define S50_ELS_KS19_KS19_UPPROT(x)              (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UPPROT_SHIFT)) & S50_ELS_KS19_KS19_UPPROT_MASK)
63877 /*! @} */
63878 
63879 
63880 /*!
63881  * @}
63882  */ /* end of group S50_Register_Masks */
63883 
63884 
63885 /* S50 - Peripheral instance base addresses */
63886 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
63887   /** Peripheral ELS base address */
63888   #define ELS_BASE                                 (0x50054000u)
63889   /** Peripheral ELS base address */
63890   #define ELS_BASE_NS                              (0x40054000u)
63891   /** Peripheral ELS base pointer */
63892   #define ELS                                      ((S50_Type *)ELS_BASE)
63893   /** Peripheral ELS base pointer */
63894   #define ELS_NS                                   ((S50_Type *)ELS_BASE_NS)
63895   /** Peripheral ELS_ALIAS1 base address */
63896   #define ELS_ALIAS1_BASE                          (0x50055000u)
63897   /** Peripheral ELS_ALIAS1 base address */
63898   #define ELS_ALIAS1_BASE_NS                       (0x40055000u)
63899   /** Peripheral ELS_ALIAS1 base pointer */
63900   #define ELS_ALIAS1                               ((S50_Type *)ELS_ALIAS1_BASE)
63901   /** Peripheral ELS_ALIAS1 base pointer */
63902   #define ELS_ALIAS1_NS                            ((S50_Type *)ELS_ALIAS1_BASE_NS)
63903   /** Peripheral ELS_ALIAS2 base address */
63904   #define ELS_ALIAS2_BASE                          (0x50056000u)
63905   /** Peripheral ELS_ALIAS2 base address */
63906   #define ELS_ALIAS2_BASE_NS                       (0x40056000u)
63907   /** Peripheral ELS_ALIAS2 base pointer */
63908   #define ELS_ALIAS2                               ((S50_Type *)ELS_ALIAS2_BASE)
63909   /** Peripheral ELS_ALIAS2 base pointer */
63910   #define ELS_ALIAS2_NS                            ((S50_Type *)ELS_ALIAS2_BASE_NS)
63911   /** Peripheral ELS_ALIAS3 base address */
63912   #define ELS_ALIAS3_BASE                          (0x50057000u)
63913   /** Peripheral ELS_ALIAS3 base address */
63914   #define ELS_ALIAS3_BASE_NS                       (0x40057000u)
63915   /** Peripheral ELS_ALIAS3 base pointer */
63916   #define ELS_ALIAS3                               ((S50_Type *)ELS_ALIAS3_BASE)
63917   /** Peripheral ELS_ALIAS3 base pointer */
63918   #define ELS_ALIAS3_NS                            ((S50_Type *)ELS_ALIAS3_BASE_NS)
63919   /** Array initializer of S50 peripheral base addresses */
63920   #define S50_BASE_ADDRS                           { ELS_BASE, ELS_ALIAS1_BASE, ELS_ALIAS2_BASE, ELS_ALIAS3_BASE }
63921   /** Array initializer of S50 peripheral base pointers */
63922   #define S50_BASE_PTRS                            { ELS, ELS_ALIAS1, ELS_ALIAS2, ELS_ALIAS3 }
63923   /** Array initializer of S50 peripheral base addresses */
63924   #define S50_BASE_ADDRS_NS                        { ELS_BASE_NS, ELS_ALIAS1_BASE_NS, ELS_ALIAS2_BASE_NS, ELS_ALIAS3_BASE_NS }
63925   /** Array initializer of S50 peripheral base pointers */
63926   #define S50_BASE_PTRS_NS                         { ELS_NS, ELS_ALIAS1_NS, ELS_ALIAS2_NS, ELS_ALIAS3_NS }
63927 #else
63928   /** Peripheral ELS base address */
63929   #define ELS_BASE                                 (0x40054000u)
63930   /** Peripheral ELS base pointer */
63931   #define ELS                                      ((S50_Type *)ELS_BASE)
63932   /** Peripheral ELS_ALIAS1 base address */
63933   #define ELS_ALIAS1_BASE                          (0x40055000u)
63934   /** Peripheral ELS_ALIAS1 base pointer */
63935   #define ELS_ALIAS1                               ((S50_Type *)ELS_ALIAS1_BASE)
63936   /** Peripheral ELS_ALIAS2 base address */
63937   #define ELS_ALIAS2_BASE                          (0x40056000u)
63938   /** Peripheral ELS_ALIAS2 base pointer */
63939   #define ELS_ALIAS2                               ((S50_Type *)ELS_ALIAS2_BASE)
63940   /** Peripheral ELS_ALIAS3 base address */
63941   #define ELS_ALIAS3_BASE                          (0x40057000u)
63942   /** Peripheral ELS_ALIAS3 base pointer */
63943   #define ELS_ALIAS3                               ((S50_Type *)ELS_ALIAS3_BASE)
63944   /** Array initializer of S50 peripheral base addresses */
63945   #define S50_BASE_ADDRS                           { ELS_BASE, ELS_ALIAS1_BASE, ELS_ALIAS2_BASE, ELS_ALIAS3_BASE }
63946   /** Array initializer of S50 peripheral base pointers */
63947   #define S50_BASE_PTRS                            { ELS, ELS_ALIAS1, ELS_ALIAS2, ELS_ALIAS3 }
63948 #endif
63949 
63950 /*!
63951  * @}
63952  */ /* end of group S50_Peripheral_Access_Layer */
63953 
63954 
63955 /* ----------------------------------------------------------------------------
63956    -- SCG Peripheral Access Layer
63957    ---------------------------------------------------------------------------- */
63958 
63959 /*!
63960  * @addtogroup SCG_Peripheral_Access_Layer SCG Peripheral Access Layer
63961  * @{
63962  */
63963 
63964 /** SCG - Register Layout Typedef */
63965 typedef struct {
63966   __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
63967   __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
63968   __IO uint32_t TRIM_LOCK;                         /**< Trim Lock register, offset: 0x8 */
63969        uint8_t RESERVED_0[4];
63970   __I  uint32_t CSR;                               /**< Clock Status Register, offset: 0x10 */
63971   __IO uint32_t RCCR;                              /**< Run Clock Control Register, offset: 0x14 */
63972        uint8_t RESERVED_1[232];
63973   __IO uint32_t SOSCCSR;                           /**< SOSC Control Status Register, offset: 0x100 */
63974        uint8_t RESERVED_2[4];
63975   __IO uint32_t SOSCCFG;                           /**< SOSC Configuration Register, offset: 0x108 */
63976        uint8_t RESERVED_3[244];
63977   __IO uint32_t SIRCCSR;                           /**< SIRC Control Status Register, offset: 0x200 */
63978        uint8_t RESERVED_4[8];
63979   __IO uint32_t SIRCTCFG;                          /**< SIRC Trim Configuration Register, offset: 0x20C */
63980   __IO uint32_t SIRCTRIM;                          /**< SIRC Trim Register, offset: 0x210 */
63981        uint8_t RESERVED_5[4];
63982   __IO uint32_t SIRCSTAT;                          /**< SIRC Auto-trimming Status Register, offset: 0x218 */
63983        uint8_t RESERVED_6[228];
63984   __IO uint32_t FIRCCSR;                           /**< FIRC Control Status Register, offset: 0x300 */
63985        uint8_t RESERVED_7[4];
63986   __IO uint32_t FIRCCFG;                           /**< FIRC Configuration Register, offset: 0x308 */
63987   __IO uint32_t FIRCTCFG;                          /**< FIRC Trim Configuration Register, offset: 0x30C */
63988   __IO uint32_t FIRCTRIM;                          /**< FIRC Trim Register, offset: 0x310 */
63989        uint8_t RESERVED_8[4];
63990   __IO uint32_t FIRCSTAT;                          /**< FIRC Auto-trimming Status Register, offset: 0x318 */
63991        uint8_t RESERVED_9[228];
63992   __IO uint32_t ROSCCSR;                           /**< ROSC Control Status Register, offset: 0x400 */
63993        uint8_t RESERVED_10[252];
63994   __IO uint32_t APLLCSR;                           /**< APLL Control Status Register, offset: 0x500 */
63995   __IO uint32_t APLLCTRL;                          /**< APLL Control Register, offset: 0x504 */
63996   __I  uint32_t APLLSTAT;                          /**< APLL Status Register, offset: 0x508 */
63997   __IO uint32_t APLLNDIV;                          /**< APLL N Divider Register, offset: 0x50C */
63998   __IO uint32_t APLLMDIV;                          /**< APLL M Divider Register, offset: 0x510 */
63999   __IO uint32_t APLLPDIV;                          /**< APLL P Divider Register, offset: 0x514 */
64000   __IO uint32_t APLLLOCK_CNFG;                     /**< APLL LOCK Configuration Register, offset: 0x518 */
64001        uint8_t RESERVED_11[4];
64002   __I  uint32_t APLLSSCGSTAT;                      /**< APLL SSCG Status Register, offset: 0x520 */
64003   __IO uint32_t APLLSSCG0;                         /**< APLL Spread Spectrum Control 0 Register, offset: 0x524 */
64004   __IO uint32_t APLLSSCG1;                         /**< APLL Spread Spectrum Control 1 Register, offset: 0x528 */
64005        uint8_t RESERVED_12[200];
64006   __IO uint32_t APLL_OVRD;                         /**< APLL Override Register, offset: 0x5F4 */
64007        uint8_t RESERVED_13[8];
64008   __IO uint32_t SPLLCSR;                           /**< SPLL Control Status Register, offset: 0x600 */
64009   __IO uint32_t SPLLCTRL;                          /**< SPLL Control Register, offset: 0x604 */
64010   __I  uint32_t SPLLSTAT;                          /**< SPLL Status Register, offset: 0x608 */
64011   __IO uint32_t SPLLNDIV;                          /**< SPLL N Divider Register, offset: 0x60C */
64012   __IO uint32_t SPLLMDIV;                          /**< SPLL M Divider Register, offset: 0x610 */
64013   __IO uint32_t SPLLPDIV;                          /**< SPLL P Divider Register, offset: 0x614 */
64014   __IO uint32_t SPLLLOCK_CNFG;                     /**< SPLL LOCK Configuration Register, offset: 0x618 */
64015        uint8_t RESERVED_14[4];
64016   __I  uint32_t SPLLSSCGSTAT;                      /**< SPLL SSCG Status Register, offset: 0x620 */
64017   __IO uint32_t SPLLSSCG0;                         /**< SPLL Spread Spectrum Control 0 Register, offset: 0x624 */
64018   __IO uint32_t SPLLSSCG1;                         /**< SPLL Spread Spectrum Control 1 Register, offset: 0x628 */
64019        uint8_t RESERVED_15[200];
64020   __IO uint32_t SPLL_OVRD;                         /**< SPLL Override Register, offset: 0x6F4 */
64021        uint8_t RESERVED_16[8];
64022   __IO uint32_t UPLLCSR;                           /**< UPLL Control Status Register, offset: 0x700 */
64023        uint8_t RESERVED_17[252];
64024   __IO uint32_t LDOCSR;                            /**< LDO Control and Status Register, offset: 0x800 */
64025 } SCG_Type;
64026 
64027 /* ----------------------------------------------------------------------------
64028    -- SCG Register Masks
64029    ---------------------------------------------------------------------------- */
64030 
64031 /*!
64032  * @addtogroup SCG_Register_Masks SCG Register Masks
64033  * @{
64034  */
64035 
64036 /*! @name VERID - Version ID Register */
64037 /*! @{ */
64038 
64039 #define SCG_VERID_VERSION_MASK                   (0xFFFFFFFFU)
64040 #define SCG_VERID_VERSION_SHIFT                  (0U)
64041 /*! VERSION - SCG Version Number */
64042 #define SCG_VERID_VERSION(x)                     (((uint32_t)(((uint32_t)(x)) << SCG_VERID_VERSION_SHIFT)) & SCG_VERID_VERSION_MASK)
64043 /*! @} */
64044 
64045 /*! @name PARAM - Parameter Register */
64046 /*! @{ */
64047 
64048 #define SCG_PARAM_SOSCCLKPRES_MASK               (0x2U)
64049 #define SCG_PARAM_SOSCCLKPRES_SHIFT              (1U)
64050 /*! SOSCCLKPRES - SOSC Clock Present
64051  *  0b1..SOSC clock source is present
64052  *  0b0..SOSC clock source is not present
64053  */
64054 #define SCG_PARAM_SOSCCLKPRES(x)                 (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_SOSCCLKPRES_SHIFT)) & SCG_PARAM_SOSCCLKPRES_MASK)
64055 
64056 #define SCG_PARAM_SIRCCLKPRES_MASK               (0x4U)
64057 #define SCG_PARAM_SIRCCLKPRES_SHIFT              (2U)
64058 /*! SIRCCLKPRES - SIRC Clock Present
64059  *  0b1..SIRC clock source is present
64060  *  0b0..SIRC clock source is not present
64061  */
64062 #define SCG_PARAM_SIRCCLKPRES(x)                 (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_SIRCCLKPRES_SHIFT)) & SCG_PARAM_SIRCCLKPRES_MASK)
64063 
64064 #define SCG_PARAM_FIRCCLKPRES_MASK               (0x8U)
64065 #define SCG_PARAM_FIRCCLKPRES_SHIFT              (3U)
64066 /*! FIRCCLKPRES - FIRC Clock Present
64067  *  0b1..FIRC clock source is present
64068  *  0b0..FIRC clock source is not present
64069  */
64070 #define SCG_PARAM_FIRCCLKPRES(x)                 (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_FIRCCLKPRES_SHIFT)) & SCG_PARAM_FIRCCLKPRES_MASK)
64071 
64072 #define SCG_PARAM_ROSCCLKPRES_MASK               (0x10U)
64073 #define SCG_PARAM_ROSCCLKPRES_SHIFT              (4U)
64074 /*! ROSCCLKPRES - ROSC Clock Present
64075  *  0b1..ROSC clock source is present
64076  *  0b0..ROSC clock source is not present
64077  */
64078 #define SCG_PARAM_ROSCCLKPRES(x)                 (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_ROSCCLKPRES_SHIFT)) & SCG_PARAM_ROSCCLKPRES_MASK)
64079 
64080 #define SCG_PARAM_APLLCLKPRES_MASK               (0x20U)
64081 #define SCG_PARAM_APLLCLKPRES_SHIFT              (5U)
64082 /*! APLLCLKPRES - APLL Clock Present
64083  *  0b1..APLL clock source is present
64084  *  0b0..APLL clock source is not present
64085  */
64086 #define SCG_PARAM_APLLCLKPRES(x)                 (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_APLLCLKPRES_SHIFT)) & SCG_PARAM_APLLCLKPRES_MASK)
64087 
64088 #define SCG_PARAM_SPLLCLKPRES_MASK               (0x40U)
64089 #define SCG_PARAM_SPLLCLKPRES_SHIFT              (6U)
64090 /*! SPLLCLKPRES - SPLL Clock Present
64091  *  0b1..SPLL clock source is present
64092  *  0b0..SPLL clock source is not present
64093  */
64094 #define SCG_PARAM_SPLLCLKPRES(x)                 (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_SPLLCLKPRES_SHIFT)) & SCG_PARAM_SPLLCLKPRES_MASK)
64095 
64096 #define SCG_PARAM_UPLLCLKPRES_MASK               (0x80U)
64097 #define SCG_PARAM_UPLLCLKPRES_SHIFT              (7U)
64098 /*! UPLLCLKPRES - UPLL Clock Present
64099  *  0b1..UPLL clock source is present
64100  *  0b0..UPLL clock source is not present
64101  */
64102 #define SCG_PARAM_UPLLCLKPRES(x)                 (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_UPLLCLKPRES_SHIFT)) & SCG_PARAM_UPLLCLKPRES_MASK)
64103 /*! @} */
64104 
64105 /*! @name TRIM_LOCK - Trim Lock register */
64106 /*! @{ */
64107 
64108 #define SCG_TRIM_LOCK_TRIM_UNLOCK_MASK           (0x1U)
64109 #define SCG_TRIM_LOCK_TRIM_UNLOCK_SHIFT          (0U)
64110 /*! TRIM_UNLOCK - TRIM_UNLOCK
64111  *  0b0..SCG Trim registers are locked and not writable.
64112  *  0b1..SCG Trim registers are unlocked and writable.
64113  */
64114 #define SCG_TRIM_LOCK_TRIM_UNLOCK(x)             (((uint32_t)(((uint32_t)(x)) << SCG_TRIM_LOCK_TRIM_UNLOCK_SHIFT)) & SCG_TRIM_LOCK_TRIM_UNLOCK_MASK)
64115 
64116 #define SCG_TRIM_LOCK_IFR_DISABLE_MASK           (0x2U)
64117 #define SCG_TRIM_LOCK_IFR_DISABLE_SHIFT          (1U)
64118 /*! IFR_DISABLE - IFR_DISABLE
64119  *  0b0..IFR write access to SCG trim registers not disabled. The SCG Trim registers are reprogrammed with the IFR values after any system reset.
64120  *  0b1..IFR write access to SCG trim registers during system reset is blocked.
64121  */
64122 #define SCG_TRIM_LOCK_IFR_DISABLE(x)             (((uint32_t)(((uint32_t)(x)) << SCG_TRIM_LOCK_IFR_DISABLE_SHIFT)) & SCG_TRIM_LOCK_IFR_DISABLE_MASK)
64123 
64124 #define SCG_TRIM_LOCK_TRIM_LOCK_KEY_MASK         (0xFFFF0000U)
64125 #define SCG_TRIM_LOCK_TRIM_LOCK_KEY_SHIFT        (16U)
64126 /*! TRIM_LOCK_KEY - TRIM_LOCK_KEY */
64127 #define SCG_TRIM_LOCK_TRIM_LOCK_KEY(x)           (((uint32_t)(((uint32_t)(x)) << SCG_TRIM_LOCK_TRIM_LOCK_KEY_SHIFT)) & SCG_TRIM_LOCK_TRIM_LOCK_KEY_MASK)
64128 /*! @} */
64129 
64130 /*! @name CSR - Clock Status Register */
64131 /*! @{ */
64132 
64133 #define SCG_CSR_SCS_MASK                         (0xF000000U)
64134 #define SCG_CSR_SCS_SHIFT                        (24U)
64135 /*! SCS - System Clock Source
64136  *  0b0000..Reserved
64137  *  0b0001..SOSC
64138  *  0b0010..SIRC
64139  *  0b0011..FIRC
64140  *  0b0100..ROSC
64141  *  0b0101..APLL
64142  *  0b0110..SPLL
64143  *  0b0111..UPLL
64144  *  0b1000-0b1111..Reserved
64145  */
64146 #define SCG_CSR_SCS(x)                           (((uint32_t)(((uint32_t)(x)) << SCG_CSR_SCS_SHIFT)) & SCG_CSR_SCS_MASK)
64147 /*! @} */
64148 
64149 /*! @name RCCR - Run Clock Control Register */
64150 /*! @{ */
64151 
64152 #define SCG_RCCR_SCS_MASK                        (0xF000000U)
64153 #define SCG_RCCR_SCS_SHIFT                       (24U)
64154 /*! SCS - System Clock Source
64155  *  0b0000..Reserved
64156  *  0b0001..SOSC
64157  *  0b0010..SIRC
64158  *  0b0011..FIRC
64159  *  0b0100..ROSC
64160  *  0b0101..APLL
64161  *  0b0110..SPLL
64162  *  0b0111..UPLL
64163  *  0b1000-0b1111..Reserved
64164  */
64165 #define SCG_RCCR_SCS(x)                          (((uint32_t)(((uint32_t)(x)) << SCG_RCCR_SCS_SHIFT)) & SCG_RCCR_SCS_MASK)
64166 /*! @} */
64167 
64168 /*! @name SOSCCSR - SOSC Control Status Register */
64169 /*! @{ */
64170 
64171 #define SCG_SOSCCSR_SOSCEN_MASK                  (0x1U)
64172 #define SCG_SOSCCSR_SOSCEN_SHIFT                 (0U)
64173 /*! SOSCEN - SOSC Enable
64174  *  0b0..SOSC is disabled
64175  *  0b1..SOSC is enabled
64176  */
64177 #define SCG_SOSCCSR_SOSCEN(x)                    (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCEN_SHIFT)) & SCG_SOSCCSR_SOSCEN_MASK)
64178 
64179 #define SCG_SOSCCSR_SOSCSTEN_MASK                (0x2U)
64180 #define SCG_SOSCCSR_SOSCSTEN_SHIFT               (1U)
64181 /*! SOSCSTEN - SOSC Stop Enable
64182  *  0b0..SOSC is disabled in Deep Sleep mode
64183  *  0b1..SOSC is enabled in Deep Sleep mode only if SOSCEN is set
64184  */
64185 #define SCG_SOSCCSR_SOSCSTEN(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCSTEN_SHIFT)) & SCG_SOSCCSR_SOSCSTEN_MASK)
64186 
64187 #define SCG_SOSCCSR_SOSCCM_MASK                  (0x10000U)
64188 #define SCG_SOSCCSR_SOSCCM_SHIFT                 (16U)
64189 /*! SOSCCM - SOSC Clock Monitor Enable
64190  *  0b0..SOSC Clock Monitor is disabled
64191  *  0b1..SOSC Clock Monitor is enabled
64192  */
64193 #define SCG_SOSCCSR_SOSCCM(x)                    (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCCM_SHIFT)) & SCG_SOSCCSR_SOSCCM_MASK)
64194 
64195 #define SCG_SOSCCSR_SOSCCMRE_MASK                (0x20000U)
64196 #define SCG_SOSCCSR_SOSCCMRE_SHIFT               (17U)
64197 /*! SOSCCMRE - SOSC Clock Monitor Reset Enable
64198  *  0b0..Clock monitor generates an interrupt when an error is detected
64199  *  0b1..Clock monitor generates a reset when an error is detected
64200  */
64201 #define SCG_SOSCCSR_SOSCCMRE(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCCMRE_SHIFT)) & SCG_SOSCCSR_SOSCCMRE_MASK)
64202 
64203 #define SCG_SOSCCSR_LK_MASK                      (0x800000U)
64204 #define SCG_SOSCCSR_LK_SHIFT                     (23U)
64205 /*! LK - Lock Register
64206  *  0b0..This Control Status Register can be written
64207  *  0b1..This Control Status Register cannot be written
64208  */
64209 #define SCG_SOSCCSR_LK(x)                        (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_LK_SHIFT)) & SCG_SOSCCSR_LK_MASK)
64210 
64211 #define SCG_SOSCCSR_SOSCVLD_MASK                 (0x1000000U)
64212 #define SCG_SOSCCSR_SOSCVLD_SHIFT                (24U)
64213 /*! SOSCVLD - SOSC Valid
64214  *  0b0..SOSC is not enabled or clock is not valid
64215  *  0b1..SOSC is enabled and output clock is valid
64216  */
64217 #define SCG_SOSCCSR_SOSCVLD(x)                   (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCVLD_SHIFT)) & SCG_SOSCCSR_SOSCVLD_MASK)
64218 
64219 #define SCG_SOSCCSR_SOSCSEL_MASK                 (0x2000000U)
64220 #define SCG_SOSCCSR_SOSCSEL_SHIFT                (25U)
64221 /*! SOSCSEL - SOSC Selected
64222  *  0b0..SOSC is not the system clock source
64223  *  0b1..SOSC is the system clock source
64224  */
64225 #define SCG_SOSCCSR_SOSCSEL(x)                   (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCSEL_SHIFT)) & SCG_SOSCCSR_SOSCSEL_MASK)
64226 
64227 #define SCG_SOSCCSR_SOSCERR_MASK                 (0x4000000U)
64228 #define SCG_SOSCCSR_SOSCERR_SHIFT                (26U)
64229 /*! SOSCERR - SOSC Clock Error
64230  *  0b0..SOSC Clock Monitor is disabled or has not detected an error
64231  *  0b1..SOSC Clock Monitor is enabled and detected an error
64232  */
64233 #define SCG_SOSCCSR_SOSCERR(x)                   (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCERR_SHIFT)) & SCG_SOSCCSR_SOSCERR_MASK)
64234 
64235 #define SCG_SOSCCSR_SOSCVLD_IE_MASK              (0x40000000U)
64236 #define SCG_SOSCCSR_SOSCVLD_IE_SHIFT             (30U)
64237 /*! SOSCVLD_IE - SOSC Valid Interrupt Enable
64238  *  0b0..SOSCVLD interrupt is not enabled
64239  *  0b1..SOSCVLD interrupt is enabled
64240  */
64241 #define SCG_SOSCCSR_SOSCVLD_IE(x)                (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCVLD_IE_SHIFT)) & SCG_SOSCCSR_SOSCVLD_IE_MASK)
64242 /*! @} */
64243 
64244 /*! @name SOSCCFG - SOSC Configuration Register */
64245 /*! @{ */
64246 
64247 #define SCG_SOSCCFG_EREFS_MASK                   (0x4U)
64248 #define SCG_SOSCCFG_EREFS_SHIFT                  (2U)
64249 /*! EREFS - External Reference Select
64250  *  0b0..External reference clock selected. LDO can be disabled in this case.
64251  *  0b1..Internal crystal oscillator of OSC selected.
64252  */
64253 #define SCG_SOSCCFG_EREFS(x)                     (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCFG_EREFS_SHIFT)) & SCG_SOSCCFG_EREFS_MASK)
64254 
64255 #define SCG_SOSCCFG_RANGE_MASK                   (0x30U)
64256 #define SCG_SOSCCFG_RANGE_SHIFT                  (4U)
64257 /*! RANGE - SOSC Range Select
64258  *  0b00..Frequency range select of 16-20 MHz.
64259  *  0b01..Frequency range select of 20-30 MHz.
64260  *  0b10..Frequency range select of 30-50 MHz.
64261  *  0b11..Frequency range select of 50-66 MHz.
64262  */
64263 #define SCG_SOSCCFG_RANGE(x)                     (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCFG_RANGE_SHIFT)) & SCG_SOSCCFG_RANGE_MASK)
64264 /*! @} */
64265 
64266 /*! @name SIRCCSR - SIRC Control Status Register */
64267 /*! @{ */
64268 
64269 #define SCG_SIRCCSR_SIRCSTEN_MASK                (0x2U)
64270 #define SCG_SIRCCSR_SIRCSTEN_SHIFT               (1U)
64271 /*! SIRCSTEN - SIRC Stop Enable
64272  *  0b0..SIRC is disabled in Deep Sleep mode
64273  *  0b1..SIRC is enabled in Deep Sleep mode
64274  */
64275 #define SCG_SIRCCSR_SIRCSTEN(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCSTEN_SHIFT)) & SCG_SIRCCSR_SIRCSTEN_MASK)
64276 
64277 #define SCG_SIRCCSR_SIRC_CLK_PERIPH_EN_MASK      (0x20U)
64278 #define SCG_SIRCCSR_SIRC_CLK_PERIPH_EN_SHIFT     (5U)
64279 /*! SIRC_CLK_PERIPH_EN - SIRC Clock to Peripherals Enable
64280  *  0b0..SIRC clock to peripherals is disabled
64281  *  0b1..SIRC clock to peripherals is enabled
64282  */
64283 #define SCG_SIRCCSR_SIRC_CLK_PERIPH_EN(x)        (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRC_CLK_PERIPH_EN_SHIFT)) & SCG_SIRCCSR_SIRC_CLK_PERIPH_EN_MASK)
64284 
64285 #define SCG_SIRCCSR_SIRCTREN_MASK                (0x100U)
64286 #define SCG_SIRCCSR_SIRCTREN_SHIFT               (8U)
64287 /*! SIRCTREN - SIRC 12 MHz Trim Enable (SIRCCFG[RANGE]=1)
64288  *  0b0..Disables trimming SIRC to an external clock source
64289  *  0b1..Enables trimming SIRC to an external clock source
64290  */
64291 #define SCG_SIRCCSR_SIRCTREN(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCTREN_SHIFT)) & SCG_SIRCCSR_SIRCTREN_MASK)
64292 
64293 #define SCG_SIRCCSR_SIRCTRUP_MASK                (0x200U)
64294 #define SCG_SIRCCSR_SIRCTRUP_SHIFT               (9U)
64295 /*! SIRCTRUP - SIRC Trim Update
64296  *  0b0..Disables SIRC trimming updates
64297  *  0b1..Enables SIRC trimming updates
64298  */
64299 #define SCG_SIRCCSR_SIRCTRUP(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCTRUP_SHIFT)) & SCG_SIRCCSR_SIRCTRUP_MASK)
64300 
64301 #define SCG_SIRCCSR_TRIM_LOCK_MASK               (0x400U)
64302 #define SCG_SIRCCSR_TRIM_LOCK_SHIFT              (10U)
64303 /*! TRIM_LOCK - SIRC TRIM LOCK
64304  *  0b0..SIRC auto trim not locked to target frequency range
64305  *  0b1..SIRC auto trim locked to target frequency range
64306  */
64307 #define SCG_SIRCCSR_TRIM_LOCK(x)                 (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_TRIM_LOCK_SHIFT)) & SCG_SIRCCSR_TRIM_LOCK_MASK)
64308 
64309 #define SCG_SIRCCSR_COARSE_TRIM_BYPASS_MASK      (0x800U)
64310 #define SCG_SIRCCSR_COARSE_TRIM_BYPASS_SHIFT     (11U)
64311 /*! COARSE_TRIM_BYPASS - Coarse Auto Trim Bypass
64312  *  0b0..SIRC coarse auto-trim is not bypassed
64313  *  0b1..SIRC coarse auto-trim is bypassed
64314  */
64315 #define SCG_SIRCCSR_COARSE_TRIM_BYPASS(x)        (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_COARSE_TRIM_BYPASS_SHIFT)) & SCG_SIRCCSR_COARSE_TRIM_BYPASS_MASK)
64316 
64317 #define SCG_SIRCCSR_LK_MASK                      (0x800000U)
64318 #define SCG_SIRCCSR_LK_SHIFT                     (23U)
64319 /*! LK - Lock Register
64320  *  0b0..Control Status Register can be written
64321  *  0b1..Control Status Register cannot be written
64322  */
64323 #define SCG_SIRCCSR_LK(x)                        (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_LK_SHIFT)) & SCG_SIRCCSR_LK_MASK)
64324 
64325 #define SCG_SIRCCSR_SIRCVLD_MASK                 (0x1000000U)
64326 #define SCG_SIRCCSR_SIRCVLD_SHIFT                (24U)
64327 /*! SIRCVLD - SIRC Valid
64328  *  0b0..SIRC is not enabled or clock is not valid
64329  *  0b1..SIRC is enabled and output clock is valid
64330  */
64331 #define SCG_SIRCCSR_SIRCVLD(x)                   (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCVLD_SHIFT)) & SCG_SIRCCSR_SIRCVLD_MASK)
64332 
64333 #define SCG_SIRCCSR_SIRCSEL_MASK                 (0x2000000U)
64334 #define SCG_SIRCCSR_SIRCSEL_SHIFT                (25U)
64335 /*! SIRCSEL - SIRC Selected
64336  *  0b0..SIRC is not the system clock source
64337  *  0b1..SIRC is the system clock source
64338  */
64339 #define SCG_SIRCCSR_SIRCSEL(x)                   (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCSEL_SHIFT)) & SCG_SIRCCSR_SIRCSEL_MASK)
64340 
64341 #define SCG_SIRCCSR_SIRCERR_MASK                 (0x4000000U)
64342 #define SCG_SIRCCSR_SIRCERR_SHIFT                (26U)
64343 /*! SIRCERR - SIRC Clock Error
64344  *  0b0..Error not detected with the SIRC trimming
64345  *  0b1..Error detected with the SIRC trimming
64346  */
64347 #define SCG_SIRCCSR_SIRCERR(x)                   (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCERR_SHIFT)) & SCG_SIRCCSR_SIRCERR_MASK)
64348 
64349 #define SCG_SIRCCSR_SIRCERR_IE_MASK              (0x8000000U)
64350 #define SCG_SIRCCSR_SIRCERR_IE_SHIFT             (27U)
64351 /*! SIRCERR_IE - SIRC Clock Error Interrupt Enable
64352  *  0b0..SIRCERR interrupt is not enabled
64353  *  0b1..SIRCERR interrupt is enabled
64354  */
64355 #define SCG_SIRCCSR_SIRCERR_IE(x)                (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCERR_IE_SHIFT)) & SCG_SIRCCSR_SIRCERR_IE_MASK)
64356 /*! @} */
64357 
64358 /*! @name SIRCTCFG - SIRC Trim Configuration Register */
64359 /*! @{ */
64360 
64361 #define SCG_SIRCTCFG_TRIMSRC_MASK                (0x3U)
64362 #define SCG_SIRCTCFG_TRIMSRC_SHIFT               (0U)
64363 /*! TRIMSRC - Trim Source
64364  *  0b00..Reserved
64365  *  0b01..Reserved
64366  *  0b10..SOSC
64367  *  0b11..ROSC (32.768 kHz)
64368  */
64369 #define SCG_SIRCTCFG_TRIMSRC(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_SIRCTCFG_TRIMSRC_SHIFT)) & SCG_SIRCTCFG_TRIMSRC_MASK)
64370 
64371 #define SCG_SIRCTCFG_TRIMDIV_MASK                (0x7F0000U)
64372 #define SCG_SIRCTCFG_TRIMDIV_SHIFT               (16U)
64373 /*! TRIMDIV - SIRC Trim Predivider */
64374 #define SCG_SIRCTCFG_TRIMDIV(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_SIRCTCFG_TRIMDIV_SHIFT)) & SCG_SIRCTCFG_TRIMDIV_MASK)
64375 /*! @} */
64376 
64377 /*! @name SIRCTRIM - SIRC Trim Register */
64378 /*! @{ */
64379 
64380 #define SCG_SIRCTRIM_CCOTRIM_MASK                (0x3FU)
64381 #define SCG_SIRCTRIM_CCOTRIM_SHIFT               (0U)
64382 /*! CCOTRIM - CCO Trim */
64383 #define SCG_SIRCTRIM_CCOTRIM(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_SIRCTRIM_CCOTRIM_SHIFT)) & SCG_SIRCTRIM_CCOTRIM_MASK)
64384 
64385 #define SCG_SIRCTRIM_CLTRIM_MASK                 (0x3F00U)
64386 #define SCG_SIRCTRIM_CLTRIM_SHIFT                (8U)
64387 /*! CLTRIM - CL Trim */
64388 #define SCG_SIRCTRIM_CLTRIM(x)                   (((uint32_t)(((uint32_t)(x)) << SCG_SIRCTRIM_CLTRIM_SHIFT)) & SCG_SIRCTRIM_CLTRIM_MASK)
64389 
64390 #define SCG_SIRCTRIM_TCTRIM_MASK                 (0x1F0000U)
64391 #define SCG_SIRCTRIM_TCTRIM_SHIFT                (16U)
64392 /*! TCTRIM - Trim Temp */
64393 #define SCG_SIRCTRIM_TCTRIM(x)                   (((uint32_t)(((uint32_t)(x)) << SCG_SIRCTRIM_TCTRIM_SHIFT)) & SCG_SIRCTRIM_TCTRIM_MASK)
64394 
64395 #define SCG_SIRCTRIM_FVCHTRIM_MASK               (0x1F000000U)
64396 #define SCG_SIRCTRIM_FVCHTRIM_SHIFT              (24U)
64397 #define SCG_SIRCTRIM_FVCHTRIM(x)                 (((uint32_t)(((uint32_t)(x)) << SCG_SIRCTRIM_FVCHTRIM_SHIFT)) & SCG_SIRCTRIM_FVCHTRIM_MASK)
64398 /*! @} */
64399 
64400 /*! @name SIRCSTAT - SIRC Auto-trimming Status Register */
64401 /*! @{ */
64402 
64403 #define SCG_SIRCSTAT_CCOTRIM_MASK                (0x3FU)
64404 #define SCG_SIRCSTAT_CCOTRIM_SHIFT               (0U)
64405 /*! CCOTRIM - CCO Trim */
64406 #define SCG_SIRCSTAT_CCOTRIM(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_SIRCSTAT_CCOTRIM_SHIFT)) & SCG_SIRCSTAT_CCOTRIM_MASK)
64407 
64408 #define SCG_SIRCSTAT_CLTRIM_MASK                 (0x3F00U)
64409 #define SCG_SIRCSTAT_CLTRIM_SHIFT                (8U)
64410 /*! CLTRIM - CL Trim */
64411 #define SCG_SIRCSTAT_CLTRIM(x)                   (((uint32_t)(((uint32_t)(x)) << SCG_SIRCSTAT_CLTRIM_SHIFT)) & SCG_SIRCSTAT_CLTRIM_MASK)
64412 /*! @} */
64413 
64414 /*! @name FIRCCSR - FIRC Control Status Register */
64415 /*! @{ */
64416 
64417 #define SCG_FIRCCSR_FIRCEN_MASK                  (0x1U)
64418 #define SCG_FIRCCSR_FIRCEN_SHIFT                 (0U)
64419 /*! FIRCEN - FIRC Enable
64420  *  0b0..FIRC is disabled
64421  *  0b1..FIRC is enabled
64422  */
64423 #define SCG_FIRCCSR_FIRCEN(x)                    (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCEN_SHIFT)) & SCG_FIRCCSR_FIRCEN_MASK)
64424 
64425 #define SCG_FIRCCSR_FIRCSTEN_MASK                (0x2U)
64426 #define SCG_FIRCCSR_FIRCSTEN_SHIFT               (1U)
64427 /*! FIRCSTEN - FIRC Stop Enable
64428  *  0b0..FIRC is disabled in Deep Sleep mode
64429  *  0b1..FIRC is enabled in Deep Sleep mode
64430  */
64431 #define SCG_FIRCCSR_FIRCSTEN(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCSTEN_SHIFT)) & SCG_FIRCCSR_FIRCSTEN_MASK)
64432 
64433 #define SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_MASK     (0x10U)
64434 #define SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_SHIFT    (4U)
64435 /*! FIRC_SCLK_PERIPH_EN - FIRC 48 MHz Clock to peripherals Enable
64436  *  0b0..FIRC 48 MHz to peripherals is disabled
64437  *  0b1..FIRC 48 MHz to peripherals is enabled
64438  */
64439 #define SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN(x)       (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_SHIFT)) & SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_MASK)
64440 
64441 #define SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_MASK     (0x20U)
64442 #define SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_SHIFT    (5U)
64443 /*! FIRC_FCLK_PERIPH_EN - FIRC 144 MHz Clock to peripherals Enable
64444  *  0b0..FIRC 144 MHz to peripherals is disabled
64445  *  0b1..FIRC 144 MHz to peripherals is enabled
64446  */
64447 #define SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN(x)       (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_SHIFT)) & SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_MASK)
64448 
64449 #define SCG_FIRCCSR_FIRCTREN_MASK                (0x100U)
64450 #define SCG_FIRCCSR_FIRCTREN_SHIFT               (8U)
64451 /*! FIRCTREN - FIRC 144 MHz Trim Enable (FIRCCFG[RANGE]=1)
64452  *  0b0..Disables trimming FIRC to an external clock source
64453  *  0b1..Enables trimming FIRC to an external clock source
64454  */
64455 #define SCG_FIRCCSR_FIRCTREN(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCTREN_SHIFT)) & SCG_FIRCCSR_FIRCTREN_MASK)
64456 
64457 #define SCG_FIRCCSR_FIRCTRUP_MASK                (0x200U)
64458 #define SCG_FIRCCSR_FIRCTRUP_SHIFT               (9U)
64459 /*! FIRCTRUP - FIRC Trim Update
64460  *  0b0..Disables FIRC trimming updates
64461  *  0b1..Enables FIRC trimming updates
64462  */
64463 #define SCG_FIRCCSR_FIRCTRUP(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCTRUP_SHIFT)) & SCG_FIRCCSR_FIRCTRUP_MASK)
64464 
64465 #define SCG_FIRCCSR_TRIM_LOCK_MASK               (0x400U)
64466 #define SCG_FIRCCSR_TRIM_LOCK_SHIFT              (10U)
64467 /*! TRIM_LOCK - FIRC TRIM LOCK
64468  *  0b0..FIRC auto trim not locked to target frequency range
64469  *  0b1..FIRC auto trim locked to target frequency range
64470  */
64471 #define SCG_FIRCCSR_TRIM_LOCK(x)                 (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_TRIM_LOCK_SHIFT)) & SCG_FIRCCSR_TRIM_LOCK_MASK)
64472 
64473 #define SCG_FIRCCSR_COARSE_TRIM_BYPASS_MASK      (0x800U)
64474 #define SCG_FIRCCSR_COARSE_TRIM_BYPASS_SHIFT     (11U)
64475 /*! COARSE_TRIM_BYPASS - Coarse Auto Trim Bypass
64476  *  0b0..FIRC coarse auto trim is not bypassed
64477  *  0b1..FIRC coarse auto trim is bypassed
64478  */
64479 #define SCG_FIRCCSR_COARSE_TRIM_BYPASS(x)        (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_COARSE_TRIM_BYPASS_SHIFT)) & SCG_FIRCCSR_COARSE_TRIM_BYPASS_MASK)
64480 
64481 #define SCG_FIRCCSR_LK_MASK                      (0x800000U)
64482 #define SCG_FIRCCSR_LK_SHIFT                     (23U)
64483 /*! LK - Lock Register
64484  *  0b0..Control Status Register can be written
64485  *  0b1..Control Status Register cannot be written
64486  */
64487 #define SCG_FIRCCSR_LK(x)                        (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_LK_SHIFT)) & SCG_FIRCCSR_LK_MASK)
64488 
64489 #define SCG_FIRCCSR_FIRCVLD_MASK                 (0x1000000U)
64490 #define SCG_FIRCCSR_FIRCVLD_SHIFT                (24U)
64491 /*! FIRCVLD - FIRC Valid status
64492  *  0b0..FIRC is not enabled or clock is not valid.
64493  *  0b1..FIRC is enabled and output clock is valid. The clock is valid after there is an output clock from the FIRC analog.
64494  */
64495 #define SCG_FIRCCSR_FIRCVLD(x)                   (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCVLD_SHIFT)) & SCG_FIRCCSR_FIRCVLD_MASK)
64496 
64497 #define SCG_FIRCCSR_FIRCSEL_MASK                 (0x2000000U)
64498 #define SCG_FIRCCSR_FIRCSEL_SHIFT                (25U)
64499 /*! FIRCSEL - FIRC Selected
64500  *  0b0..FIRC is not the system clock source
64501  *  0b1..FIRC is the system clock source
64502  */
64503 #define SCG_FIRCCSR_FIRCSEL(x)                   (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCSEL_SHIFT)) & SCG_FIRCCSR_FIRCSEL_MASK)
64504 
64505 #define SCG_FIRCCSR_FIRCERR_MASK                 (0x4000000U)
64506 #define SCG_FIRCCSR_FIRCERR_SHIFT                (26U)
64507 /*! FIRCERR - FIRC Clock Error
64508  *  0b0..Error not detected with the FIRC trimming
64509  *  0b1..Error detected with the FIRC trimming
64510  */
64511 #define SCG_FIRCCSR_FIRCERR(x)                   (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCERR_SHIFT)) & SCG_FIRCCSR_FIRCERR_MASK)
64512 
64513 #define SCG_FIRCCSR_FIRCERR_IE_MASK              (0x8000000U)
64514 #define SCG_FIRCCSR_FIRCERR_IE_SHIFT             (27U)
64515 /*! FIRCERR_IE - FIRC Clock Error Interrupt Enable
64516  *  0b0..FIRCERR interrupt is not enabled
64517  *  0b1..FIRCERR interrupt is enabled
64518  */
64519 #define SCG_FIRCCSR_FIRCERR_IE(x)                (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCERR_IE_SHIFT)) & SCG_FIRCCSR_FIRCERR_IE_MASK)
64520 
64521 #define SCG_FIRCCSR_FIRCACC_IE_MASK              (0x40000000U)
64522 #define SCG_FIRCCSR_FIRCACC_IE_SHIFT             (30U)
64523 /*! FIRCACC_IE - FIRC Accurate Interrupt Enable
64524  *  0b0..FIRCACC interrupt is not enabled
64525  *  0b1..FIRCACC interrupt is enabled
64526  */
64527 #define SCG_FIRCCSR_FIRCACC_IE(x)                (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCACC_IE_SHIFT)) & SCG_FIRCCSR_FIRCACC_IE_MASK)
64528 
64529 #define SCG_FIRCCSR_FIRCACC_MASK                 (0x80000000U)
64530 #define SCG_FIRCCSR_FIRCACC_SHIFT                (31U)
64531 /*! FIRCACC - FIRC Frequency Accurate
64532  *  0b0..FIRC is not enabled or clock is not accurate.
64533  *  0b1..FIRC is enabled and output clock is accurate. The clock is accurate after 4096 clock cycles of 144 MHz
64534  *       (RANGE=1) or 1365 clock cycles of 48 MHz(RANGE=0) from the FIRC analog.
64535  */
64536 #define SCG_FIRCCSR_FIRCACC(x)                   (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCACC_SHIFT)) & SCG_FIRCCSR_FIRCACC_MASK)
64537 /*! @} */
64538 
64539 /*! @name FIRCCFG - FIRC Configuration Register */
64540 /*! @{ */
64541 
64542 #define SCG_FIRCCFG_RANGE_MASK                   (0x1U)
64543 #define SCG_FIRCCFG_RANGE_SHIFT                  (0U)
64544 /*! RANGE - Frequency Range
64545  *  0b0..48 MHz FIRC clock selected
64546  *  0b1..144 MHz FIRC clock selected
64547  */
64548 #define SCG_FIRCCFG_RANGE(x)                     (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCFG_RANGE_SHIFT)) & SCG_FIRCCFG_RANGE_MASK)
64549 /*! @} */
64550 
64551 /*! @name FIRCTCFG - FIRC Trim Configuration Register */
64552 /*! @{ */
64553 
64554 #define SCG_FIRCTCFG_TRIMSRC_MASK                (0x3U)
64555 #define SCG_FIRCTCFG_TRIMSRC_SHIFT               (0U)
64556 /*! TRIMSRC - Trim Source
64557  *  0b00..USB0 Start of Frame (1 kHz). This option does not use TRIMDIV
64558  *  0b01..Reserved
64559  *  0b10..SOSC
64560  *  0b11..ROSC
64561  */
64562 #define SCG_FIRCTCFG_TRIMSRC(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_FIRCTCFG_TRIMSRC_SHIFT)) & SCG_FIRCTCFG_TRIMSRC_MASK)
64563 
64564 #define SCG_FIRCTCFG_TRIMDIV_MASK                (0x7F0000U)
64565 #define SCG_FIRCTCFG_TRIMDIV_SHIFT               (16U)
64566 /*! TRIMDIV - FIRC Trim Predivider */
64567 #define SCG_FIRCTCFG_TRIMDIV(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_FIRCTCFG_TRIMDIV_SHIFT)) & SCG_FIRCTCFG_TRIMDIV_MASK)
64568 /*! @} */
64569 
64570 /*! @name FIRCTRIM - FIRC Trim Register */
64571 /*! @{ */
64572 
64573 #define SCG_FIRCTRIM_TRIMFINE_MASK               (0xFFU)
64574 #define SCG_FIRCTRIM_TRIMFINE_SHIFT              (0U)
64575 /*! TRIMFINE - Trim Fine */
64576 #define SCG_FIRCTRIM_TRIMFINE(x)                 (((uint32_t)(((uint32_t)(x)) << SCG_FIRCTRIM_TRIMFINE_SHIFT)) & SCG_FIRCTRIM_TRIMFINE_MASK)
64577 
64578 #define SCG_FIRCTRIM_TRIMCOAR_MASK               (0x3F00U)
64579 #define SCG_FIRCTRIM_TRIMCOAR_SHIFT              (8U)
64580 /*! TRIMCOAR - Trim Coarse */
64581 #define SCG_FIRCTRIM_TRIMCOAR(x)                 (((uint32_t)(((uint32_t)(x)) << SCG_FIRCTRIM_TRIMCOAR_SHIFT)) & SCG_FIRCTRIM_TRIMCOAR_MASK)
64582 
64583 #define SCG_FIRCTRIM_TRIMTEMP_MASK               (0x30000U)
64584 #define SCG_FIRCTRIM_TRIMTEMP_SHIFT              (16U)
64585 /*! TRIMTEMP - Trim Temperature */
64586 #define SCG_FIRCTRIM_TRIMTEMP(x)                 (((uint32_t)(((uint32_t)(x)) << SCG_FIRCTRIM_TRIMTEMP_SHIFT)) & SCG_FIRCTRIM_TRIMTEMP_MASK)
64587 
64588 #define SCG_FIRCTRIM_TRIMSTART_MASK              (0x3F000000U)
64589 #define SCG_FIRCTRIM_TRIMSTART_SHIFT             (24U)
64590 /*! TRIMSTART - Trim Start */
64591 #define SCG_FIRCTRIM_TRIMSTART(x)                (((uint32_t)(((uint32_t)(x)) << SCG_FIRCTRIM_TRIMSTART_SHIFT)) & SCG_FIRCTRIM_TRIMSTART_MASK)
64592 /*! @} */
64593 
64594 /*! @name FIRCSTAT - FIRC Auto-trimming Status Register */
64595 /*! @{ */
64596 
64597 #define SCG_FIRCSTAT_TRIMFINE_MASK               (0xFFU)
64598 #define SCG_FIRCSTAT_TRIMFINE_SHIFT              (0U)
64599 /*! TRIMFINE - Trim Fine */
64600 #define SCG_FIRCSTAT_TRIMFINE(x)                 (((uint32_t)(((uint32_t)(x)) << SCG_FIRCSTAT_TRIMFINE_SHIFT)) & SCG_FIRCSTAT_TRIMFINE_MASK)
64601 
64602 #define SCG_FIRCSTAT_TRIMCOAR_MASK               (0x3F00U)
64603 #define SCG_FIRCSTAT_TRIMCOAR_SHIFT              (8U)
64604 /*! TRIMCOAR - Trim Coarse */
64605 #define SCG_FIRCSTAT_TRIMCOAR(x)                 (((uint32_t)(((uint32_t)(x)) << SCG_FIRCSTAT_TRIMCOAR_SHIFT)) & SCG_FIRCSTAT_TRIMCOAR_MASK)
64606 /*! @} */
64607 
64608 /*! @name ROSCCSR - ROSC Control Status Register */
64609 /*! @{ */
64610 
64611 #define SCG_ROSCCSR_ROSCCM_MASK                  (0x10000U)
64612 #define SCG_ROSCCSR_ROSCCM_SHIFT                 (16U)
64613 /*! ROSCCM - ROSC Clock Monitor
64614  *  0b0..ROSC clock monitor is disabled
64615  *  0b1..ROSC clock monitor is enabled
64616  */
64617 #define SCG_ROSCCSR_ROSCCM(x)                    (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_ROSCCM_SHIFT)) & SCG_ROSCCSR_ROSCCM_MASK)
64618 
64619 #define SCG_ROSCCSR_ROSCCMRE_MASK                (0x20000U)
64620 #define SCG_ROSCCSR_ROSCCMRE_SHIFT               (17U)
64621 /*! ROSCCMRE - ROSC Clock Monitor Reset Enable
64622  *  0b0..Clock monitor generates an interrupt when an error is detected
64623  *  0b1..Clock monitor generates a reset when an error is detected
64624  */
64625 #define SCG_ROSCCSR_ROSCCMRE(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_ROSCCMRE_SHIFT)) & SCG_ROSCCSR_ROSCCMRE_MASK)
64626 
64627 #define SCG_ROSCCSR_LK_MASK                      (0x800000U)
64628 #define SCG_ROSCCSR_LK_SHIFT                     (23U)
64629 /*! LK - Lock Register
64630  *  0b0..Control Status Register can be written
64631  *  0b1..Control Status Register cannot be written
64632  */
64633 #define SCG_ROSCCSR_LK(x)                        (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_LK_SHIFT)) & SCG_ROSCCSR_LK_MASK)
64634 
64635 #define SCG_ROSCCSR_ROSCVLD_MASK                 (0x1000000U)
64636 #define SCG_ROSCCSR_ROSCVLD_SHIFT                (24U)
64637 /*! ROSCVLD - ROSC Valid
64638  *  0b0..ROSC is not enabled or clock is not valid
64639  *  0b1..ROSC is enabled and output clock is valid
64640  */
64641 #define SCG_ROSCCSR_ROSCVLD(x)                   (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_ROSCVLD_SHIFT)) & SCG_ROSCCSR_ROSCVLD_MASK)
64642 
64643 #define SCG_ROSCCSR_ROSCSEL_MASK                 (0x2000000U)
64644 #define SCG_ROSCCSR_ROSCSEL_SHIFT                (25U)
64645 /*! ROSCSEL - ROSC Selected
64646  *  0b0..ROSC is not the system clock source
64647  *  0b1..ROSC is the system clock source
64648  */
64649 #define SCG_ROSCCSR_ROSCSEL(x)                   (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_ROSCSEL_SHIFT)) & SCG_ROSCCSR_ROSCSEL_MASK)
64650 
64651 #define SCG_ROSCCSR_ROSCERR_MASK                 (0x4000000U)
64652 #define SCG_ROSCCSR_ROSCERR_SHIFT                (26U)
64653 /*! ROSCERR - ROSC Clock Error
64654  *  0b0..ROSC Clock Monitor is disabled or has not detected an error
64655  *  0b1..ROSC Clock Monitor is enabled and detected an RTC loss of clock error
64656  */
64657 #define SCG_ROSCCSR_ROSCERR(x)                   (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_ROSCERR_SHIFT)) & SCG_ROSCCSR_ROSCERR_MASK)
64658 /*! @} */
64659 
64660 /*! @name APLLCSR - APLL Control Status Register */
64661 /*! @{ */
64662 
64663 #define SCG_APLLCSR_APLLPWREN_MASK               (0x1U)
64664 #define SCG_APLLCSR_APLLPWREN_SHIFT              (0U)
64665 /*! APLLPWREN - APLL Power Enable
64666  *  0b0..APLL clock is powered off
64667  *  0b1..APLL clock is powered on
64668  */
64669 #define SCG_APLLCSR_APLLPWREN(x)                 (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_APLLPWREN_SHIFT)) & SCG_APLLCSR_APLLPWREN_MASK)
64670 
64671 #define SCG_APLLCSR_APLLCLKEN_MASK               (0x2U)
64672 #define SCG_APLLCSR_APLLCLKEN_SHIFT              (1U)
64673 /*! APLLCLKEN - APLL Clock Enable
64674  *  0b0..APLL clock is disabled
64675  *  0b1..APLL clock is enabled
64676  */
64677 #define SCG_APLLCSR_APLLCLKEN(x)                 (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_APLLCLKEN_SHIFT)) & SCG_APLLCSR_APLLCLKEN_MASK)
64678 
64679 #define SCG_APLLCSR_APLLSTEN_MASK                (0x4U)
64680 #define SCG_APLLCSR_APLLSTEN_SHIFT               (2U)
64681 /*! APLLSTEN - APLL Stop Enable
64682  *  0b0..APLL is disabled in Deep Sleep mode
64683  *  0b1..APLL is enabled in Deep Sleep mode
64684  */
64685 #define SCG_APLLCSR_APLLSTEN(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_APLLSTEN_SHIFT)) & SCG_APLLCSR_APLLSTEN_MASK)
64686 
64687 #define SCG_APLLCSR_APLLCM_MASK                  (0x10000U)
64688 #define SCG_APLLCSR_APLLCM_SHIFT                 (16U)
64689 /*! APLLCM - APLL Clock Monitor
64690  *  0b0..APLL Clock Monitor is disabled
64691  *  0b1..APLL Clock Monitor is enabled
64692  */
64693 #define SCG_APLLCSR_APLLCM(x)                    (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_APLLCM_SHIFT)) & SCG_APLLCSR_APLLCM_MASK)
64694 
64695 #define SCG_APLLCSR_APLLCMRE_MASK                (0x20000U)
64696 #define SCG_APLLCSR_APLLCMRE_SHIFT               (17U)
64697 /*! APLLCMRE - APLL Clock Monitor Reset Enable
64698  *  0b0..Clock monitor generates an interrupt when an error is detected
64699  *  0b1..Clock monitor generates a reset when an error is detected
64700  */
64701 #define SCG_APLLCSR_APLLCMRE(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_APLLCMRE_SHIFT)) & SCG_APLLCSR_APLLCMRE_MASK)
64702 
64703 #define SCG_APLLCSR_LK_MASK                      (0x800000U)
64704 #define SCG_APLLCSR_LK_SHIFT                     (23U)
64705 /*! LK - Lock Register
64706  *  0b0..Control Status Register can be written
64707  *  0b1..Control Status Register cannot be written
64708  */
64709 #define SCG_APLLCSR_LK(x)                        (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_LK_SHIFT)) & SCG_APLLCSR_LK_MASK)
64710 
64711 #define SCG_APLLCSR_APLL_LOCK_MASK               (0x1000000U)
64712 #define SCG_APLLCSR_APLL_LOCK_SHIFT              (24U)
64713 /*! APLL_LOCK - APLL LOCK
64714  *  0b0..APLL is not powered on or not locked
64715  *  0b1..APLL is locked
64716  */
64717 #define SCG_APLLCSR_APLL_LOCK(x)                 (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_APLL_LOCK_SHIFT)) & SCG_APLLCSR_APLL_LOCK_MASK)
64718 
64719 #define SCG_APLLCSR_APLLSEL_MASK                 (0x2000000U)
64720 #define SCG_APLLCSR_APLLSEL_SHIFT                (25U)
64721 /*! APLLSEL - APLL Selected
64722  *  0b0..APLL is not the system clock source
64723  *  0b1..APLL is the system clock source
64724  */
64725 #define SCG_APLLCSR_APLLSEL(x)                   (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_APLLSEL_SHIFT)) & SCG_APLLCSR_APLLSEL_MASK)
64726 
64727 #define SCG_APLLCSR_APLLERR_MASK                 (0x4000000U)
64728 #define SCG_APLLCSR_APLLERR_SHIFT                (26U)
64729 /*! APLLERR - APLL Clock Error
64730  *  0b0..APLL Clock Monitor is disabled or has not detected an error
64731  *  0b1..APLL Clock Monitor is enabled and detected an error
64732  */
64733 #define SCG_APLLCSR_APLLERR(x)                   (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_APLLERR_SHIFT)) & SCG_APLLCSR_APLLERR_MASK)
64734 
64735 #define SCG_APLLCSR_APLL_LOCK_IE_MASK            (0x40000000U)
64736 #define SCG_APLLCSR_APLL_LOCK_IE_SHIFT           (30U)
64737 /*! APLL_LOCK_IE - APLL LOCK Interrupt Enable
64738  *  0b0..APLL_LOCK interrupt is not enabled
64739  *  0b1..APLL_LOCK interrupt is enabled
64740  */
64741 #define SCG_APLLCSR_APLL_LOCK_IE(x)              (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_APLL_LOCK_IE_SHIFT)) & SCG_APLLCSR_APLL_LOCK_IE_MASK)
64742 /*! @} */
64743 
64744 /*! @name APLLCTRL - APLL Control Register */
64745 /*! @{ */
64746 
64747 #define SCG_APLLCTRL_SELR_MASK                   (0xFU)
64748 #define SCG_APLLCTRL_SELR_SHIFT                  (0U)
64749 /*! SELR - Bandwidth select R (resistor) value. */
64750 #define SCG_APLLCTRL_SELR(x)                     (((uint32_t)(((uint32_t)(x)) << SCG_APLLCTRL_SELR_SHIFT)) & SCG_APLLCTRL_SELR_MASK)
64751 
64752 #define SCG_APLLCTRL_SELI_MASK                   (0x3F0U)
64753 #define SCG_APLLCTRL_SELI_SHIFT                  (4U)
64754 /*! SELI - Bandwidth select I (integration) value. */
64755 #define SCG_APLLCTRL_SELI(x)                     (((uint32_t)(((uint32_t)(x)) << SCG_APLLCTRL_SELI_SHIFT)) & SCG_APLLCTRL_SELI_MASK)
64756 
64757 #define SCG_APLLCTRL_SELP_MASK                   (0x7C00U)
64758 #define SCG_APLLCTRL_SELP_SHIFT                  (10U)
64759 /*! SELP - Bandwidth select P (proportional) value. */
64760 #define SCG_APLLCTRL_SELP(x)                     (((uint32_t)(((uint32_t)(x)) << SCG_APLLCTRL_SELP_SHIFT)) & SCG_APLLCTRL_SELP_MASK)
64761 
64762 #define SCG_APLLCTRL_BYPASSPOSTDIV2_MASK         (0x10000U)
64763 #define SCG_APLLCTRL_BYPASSPOSTDIV2_SHIFT        (16U)
64764 /*! BYPASSPOSTDIV2 - Bypass of Divide-by-2 Divider
64765  *  0b0..Use the divide-by-2 divider in the postdivider
64766  *  0b1..Bypass of the divide-by-2 divider in the postdivider
64767  */
64768 #define SCG_APLLCTRL_BYPASSPOSTDIV2(x)           (((uint32_t)(((uint32_t)(x)) << SCG_APLLCTRL_BYPASSPOSTDIV2_SHIFT)) & SCG_APLLCTRL_BYPASSPOSTDIV2_MASK)
64769 
64770 #define SCG_APLLCTRL_LIMUPOFF_MASK               (0x20000U)
64771 #define SCG_APLLCTRL_LIMUPOFF_SHIFT              (17U)
64772 /*! LIMUPOFF - Up Limiter
64773  *  0b0..Application set to non-Spectrum and Fractional applications.
64774  *  0b1..Application set to Spectrum and Fractional applications.
64775  */
64776 #define SCG_APLLCTRL_LIMUPOFF(x)                 (((uint32_t)(((uint32_t)(x)) << SCG_APLLCTRL_LIMUPOFF_SHIFT)) & SCG_APLLCTRL_LIMUPOFF_MASK)
64777 
64778 #define SCG_APLLCTRL_BANDDIRECT_MASK             (0x40000U)
64779 #define SCG_APLLCTRL_BANDDIRECT_SHIFT            (18U)
64780 /*! BANDDIRECT - Control of the bandwidth of the PLL.
64781  *  0b0..The bandwidth is changed synchronously with the feedback-divider
64782  *  0b1..Modifies the bandwidth of the PLL directly
64783  */
64784 #define SCG_APLLCTRL_BANDDIRECT(x)               (((uint32_t)(((uint32_t)(x)) << SCG_APLLCTRL_BANDDIRECT_SHIFT)) & SCG_APLLCTRL_BANDDIRECT_MASK)
64785 
64786 #define SCG_APLLCTRL_BYPASSPREDIV_MASK           (0x80000U)
64787 #define SCG_APLLCTRL_BYPASSPREDIV_SHIFT          (19U)
64788 /*! BYPASSPREDIV - Bypass of the predivider
64789  *  0b0..Use the predivider.
64790  *  0b1..Bypass of the predivider.
64791  */
64792 #define SCG_APLLCTRL_BYPASSPREDIV(x)             (((uint32_t)(((uint32_t)(x)) << SCG_APLLCTRL_BYPASSPREDIV_SHIFT)) & SCG_APLLCTRL_BYPASSPREDIV_MASK)
64793 
64794 #define SCG_APLLCTRL_BYPASSPOSTDIV_MASK          (0x100000U)
64795 #define SCG_APLLCTRL_BYPASSPOSTDIV_SHIFT         (20U)
64796 /*! BYPASSPOSTDIV - Bypass of the postdivider
64797  *  0b0..Use the postdivider.
64798  *  0b1..Bypass of the postdivider
64799  */
64800 #define SCG_APLLCTRL_BYPASSPOSTDIV(x)            (((uint32_t)(((uint32_t)(x)) << SCG_APLLCTRL_BYPASSPOSTDIV_SHIFT)) & SCG_APLLCTRL_BYPASSPOSTDIV_MASK)
64801 
64802 #define SCG_APLLCTRL_SOURCE_MASK                 (0x6000000U)
64803 #define SCG_APLLCTRL_SOURCE_SHIFT                (25U)
64804 /*! SOURCE - Clock Source
64805  *  0b00..SOSC
64806  *  0b01..FIRC 48 MHz clock. FIRC_SCLK_PERIPH_EN must be set to use FIRC 48 MHz clock.
64807  *  0b10..Reserved
64808  *  0b11..No clock
64809  */
64810 #define SCG_APLLCTRL_SOURCE(x)                   (((uint32_t)(((uint32_t)(x)) << SCG_APLLCTRL_SOURCE_SHIFT)) & SCG_APLLCTRL_SOURCE_MASK)
64811 /*! @} */
64812 
64813 /*! @name APLLSTAT - APLL Status Register */
64814 /*! @{ */
64815 
64816 #define SCG_APLLSTAT_NDIVACK_MASK                (0x2U)
64817 #define SCG_APLLSTAT_NDIVACK_SHIFT               (1U)
64818 /*! NDIVACK - Predivider(N) ratio change acknowledge.
64819  *  0b0..The predivider (N) ratio change is not accepted by the analog PLL
64820  *  0b1..The predivider (N) ratio change is accepted by the analog PLL
64821  */
64822 #define SCG_APLLSTAT_NDIVACK(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_APLLSTAT_NDIVACK_SHIFT)) & SCG_APLLSTAT_NDIVACK_MASK)
64823 
64824 #define SCG_APLLSTAT_MDIVACK_MASK                (0x4U)
64825 #define SCG_APLLSTAT_MDIVACK_SHIFT               (2U)
64826 /*! MDIVACK - Feedback(M) divider ratio change acknowledge.
64827  *  0b0..The feedback (M) ratio change is not accepted by the analog PLL
64828  *  0b1..The feedback (M) ratio change is accepted by the analog PLL
64829  */
64830 #define SCG_APLLSTAT_MDIVACK(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_APLLSTAT_MDIVACK_SHIFT)) & SCG_APLLSTAT_MDIVACK_MASK)
64831 
64832 #define SCG_APLLSTAT_PDIVACK_MASK                (0x8U)
64833 #define SCG_APLLSTAT_PDIVACK_SHIFT               (3U)
64834 /*! PDIVACK - Postdivider(P) ratio change acknowledge.
64835  *  0b0..The postdivider (P) ratio change is not accepted by the analog PLL
64836  *  0b1..The postdivider (P) ratio change is accepted by the analog PLL
64837  */
64838 #define SCG_APLLSTAT_PDIVACK(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_APLLSTAT_PDIVACK_SHIFT)) & SCG_APLLSTAT_PDIVACK_MASK)
64839 /*! @} */
64840 
64841 /*! @name APLLNDIV - APLL N Divider Register */
64842 /*! @{ */
64843 
64844 #define SCG_APLLNDIV_NDIV_MASK                   (0xFFU)
64845 #define SCG_APLLNDIV_NDIV_SHIFT                  (0U)
64846 /*! NDIV - Predivider divider ratio (N-divider). */
64847 #define SCG_APLLNDIV_NDIV(x)                     (((uint32_t)(((uint32_t)(x)) << SCG_APLLNDIV_NDIV_SHIFT)) & SCG_APLLNDIV_NDIV_MASK)
64848 
64849 #define SCG_APLLNDIV_NREQ_MASK                   (0x80000000U)
64850 #define SCG_APLLNDIV_NREQ_SHIFT                  (31U)
64851 /*! NREQ - Predivider ratio change request.
64852  *  0b0..Predivider ratio change is not requested
64853  *  0b1..Predivider ratio change is requested
64854  */
64855 #define SCG_APLLNDIV_NREQ(x)                     (((uint32_t)(((uint32_t)(x)) << SCG_APLLNDIV_NREQ_SHIFT)) & SCG_APLLNDIV_NREQ_MASK)
64856 /*! @} */
64857 
64858 /*! @name APLLMDIV - APLL M Divider Register */
64859 /*! @{ */
64860 
64861 #define SCG_APLLMDIV_MDIV_MASK                   (0xFFFFU)
64862 #define SCG_APLLMDIV_MDIV_SHIFT                  (0U)
64863 /*! MDIV - Feedback divider divider ratio (M-divider). */
64864 #define SCG_APLLMDIV_MDIV(x)                     (((uint32_t)(((uint32_t)(x)) << SCG_APLLMDIV_MDIV_SHIFT)) & SCG_APLLMDIV_MDIV_MASK)
64865 
64866 #define SCG_APLLMDIV_MREQ_MASK                   (0x80000000U)
64867 #define SCG_APLLMDIV_MREQ_SHIFT                  (31U)
64868 /*! MREQ - Feedback ratio change request.
64869  *  0b0..Feedback ratio change is not requested
64870  *  0b1..Feedback ratio change is requested
64871  */
64872 #define SCG_APLLMDIV_MREQ(x)                     (((uint32_t)(((uint32_t)(x)) << SCG_APLLMDIV_MREQ_SHIFT)) & SCG_APLLMDIV_MREQ_MASK)
64873 /*! @} */
64874 
64875 /*! @name APLLPDIV - APLL P Divider Register */
64876 /*! @{ */
64877 
64878 #define SCG_APLLPDIV_PDIV_MASK                   (0x1FU)
64879 #define SCG_APLLPDIV_PDIV_SHIFT                  (0U)
64880 /*! PDIV - Postdivider divider ratio (P-divider) */
64881 #define SCG_APLLPDIV_PDIV(x)                     (((uint32_t)(((uint32_t)(x)) << SCG_APLLPDIV_PDIV_SHIFT)) & SCG_APLLPDIV_PDIV_MASK)
64882 
64883 #define SCG_APLLPDIV_PREQ_MASK                   (0x80000000U)
64884 #define SCG_APLLPDIV_PREQ_SHIFT                  (31U)
64885 /*! PREQ - Postdivider ratio change request
64886  *  0b0..Postdivider ratio change is not requested
64887  *  0b1..Postdivider ratio change is requested
64888  */
64889 #define SCG_APLLPDIV_PREQ(x)                     (((uint32_t)(((uint32_t)(x)) << SCG_APLLPDIV_PREQ_SHIFT)) & SCG_APLLPDIV_PREQ_MASK)
64890 /*! @} */
64891 
64892 /*! @name APLLLOCK_CNFG - APLL LOCK Configuration Register */
64893 /*! @{ */
64894 
64895 #define SCG_APLLLOCK_CNFG_LOCK_TIME_MASK         (0x1FFFFU)
64896 #define SCG_APLLLOCK_CNFG_LOCK_TIME_SHIFT        (0U)
64897 /*! LOCK_TIME - Configures the number of reference clocks to count before APLL is considered locked. */
64898 #define SCG_APLLLOCK_CNFG_LOCK_TIME(x)           (((uint32_t)(((uint32_t)(x)) << SCG_APLLLOCK_CNFG_LOCK_TIME_SHIFT)) & SCG_APLLLOCK_CNFG_LOCK_TIME_MASK)
64899 /*! @} */
64900 
64901 /*! @name APLLSSCGSTAT - APLL SSCG Status Register */
64902 /*! @{ */
64903 
64904 #define SCG_APLLSSCGSTAT_SS_MDIV_ACK_MASK        (0x1U)
64905 #define SCG_APLLSSCGSTAT_SS_MDIV_ACK_SHIFT       (0U)
64906 /*! SS_MDIV_ACK - SS_MDIV change acknowledge
64907  *  0b0..The SS_MDIV, MF, MR, and MC ratio change is not accepted by the analog PLL
64908  *  0b1..The SS_MDIV, MF, MR, and MC ratio change is accepted by the analog PLL
64909  */
64910 #define SCG_APLLSSCGSTAT_SS_MDIV_ACK(x)          (((uint32_t)(((uint32_t)(x)) << SCG_APLLSSCGSTAT_SS_MDIV_ACK_SHIFT)) & SCG_APLLSSCGSTAT_SS_MDIV_ACK_MASK)
64911 /*! @} */
64912 
64913 /*! @name APLLSSCG0 - APLL Spread Spectrum Control 0 Register */
64914 /*! @{ */
64915 
64916 #define SCG_APLLSSCG0_SS_MDIV_LSB_MASK           (0xFFFFFFFFU)
64917 #define SCG_APLLSSCG0_SS_MDIV_LSB_SHIFT          (0U)
64918 /*! SS_MDIV_LSB - SS_MDIV */
64919 #define SCG_APLLSSCG0_SS_MDIV_LSB(x)             (((uint32_t)(((uint32_t)(x)) << SCG_APLLSSCG0_SS_MDIV_LSB_SHIFT)) & SCG_APLLSSCG0_SS_MDIV_LSB_MASK)
64920 /*! @} */
64921 
64922 /*! @name APLLSSCG1 - APLL Spread Spectrum Control 1 Register */
64923 /*! @{ */
64924 
64925 #define SCG_APLLSSCG1_SS_MDIV_MSB_MASK           (0x1U)
64926 #define SCG_APLLSSCG1_SS_MDIV_MSB_SHIFT          (0U)
64927 /*! SS_MDIV_MSB - SS_MDIV[32] */
64928 #define SCG_APLLSSCG1_SS_MDIV_MSB(x)             (((uint32_t)(((uint32_t)(x)) << SCG_APLLSSCG1_SS_MDIV_MSB_SHIFT)) & SCG_APLLSSCG1_SS_MDIV_MSB_MASK)
64929 
64930 #define SCG_APLLSSCG1_SS_MDIV_REQ_MASK           (0x2U)
64931 #define SCG_APLLSSCG1_SS_MDIV_REQ_SHIFT          (1U)
64932 /*! SS_MDIV_REQ - SS_MDIV[32:0] change request.
64933  *  0b0..SS_MDIV change is not requested
64934  *  0b1..SS_MDIV change is requested
64935  */
64936 #define SCG_APLLSSCG1_SS_MDIV_REQ(x)             (((uint32_t)(((uint32_t)(x)) << SCG_APLLSSCG1_SS_MDIV_REQ_SHIFT)) & SCG_APLLSSCG1_SS_MDIV_REQ_MASK)
64937 
64938 #define SCG_APLLSSCG1_MF_MASK                    (0x1CU)
64939 #define SCG_APLLSSCG1_MF_SHIFT                   (2U)
64940 /*! MF - Modulation Frequency Control */
64941 #define SCG_APLLSSCG1_MF(x)                      (((uint32_t)(((uint32_t)(x)) << SCG_APLLSSCG1_MF_SHIFT)) & SCG_APLLSSCG1_MF_MASK)
64942 
64943 #define SCG_APLLSSCG1_MR_MASK                    (0xE0U)
64944 #define SCG_APLLSSCG1_MR_SHIFT                   (5U)
64945 /*! MR - Modulation Depth Control */
64946 #define SCG_APLLSSCG1_MR(x)                      (((uint32_t)(((uint32_t)(x)) << SCG_APLLSSCG1_MR_SHIFT)) & SCG_APLLSSCG1_MR_MASK)
64947 
64948 #define SCG_APLLSSCG1_MC_MASK                    (0x300U)
64949 #define SCG_APLLSSCG1_MC_SHIFT                   (8U)
64950 /*! MC - Modulation Waveform Control
64951  *  0b00..MC[1:0] no compensation
64952  *  0b11..MC[1:0] maximum compensation
64953  */
64954 #define SCG_APLLSSCG1_MC(x)                      (((uint32_t)(((uint32_t)(x)) << SCG_APLLSSCG1_MC_SHIFT)) & SCG_APLLSSCG1_MC_MASK)
64955 
64956 #define SCG_APLLSSCG1_DITHER_MASK                (0x400U)
64957 #define SCG_APLLSSCG1_DITHER_SHIFT               (10U)
64958 /*! DITHER - Dither Enable
64959  *  0b0..Dither is not enabled
64960  *  0b1..Dither is enabled
64961  */
64962 #define SCG_APLLSSCG1_DITHER(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_APLLSSCG1_DITHER_SHIFT)) & SCG_APLLSSCG1_DITHER_MASK)
64963 
64964 #define SCG_APLLSSCG1_SEL_SS_MDIV_MASK           (0x800U)
64965 #define SCG_APLLSSCG1_SEL_SS_MDIV_SHIFT          (11U)
64966 /*! SEL_SS_MDIV - SS_MDIV select.
64967  *  0b0..Feedback divider ratio is MDIV[15:0]
64968  *  0b1..Feedback divider ratio is SS_MDIV[32:0]
64969  */
64970 #define SCG_APLLSSCG1_SEL_SS_MDIV(x)             (((uint32_t)(((uint32_t)(x)) << SCG_APLLSSCG1_SEL_SS_MDIV_SHIFT)) & SCG_APLLSSCG1_SEL_SS_MDIV_MASK)
64971 
64972 #define SCG_APLLSSCG1_SS_PD_MASK                 (0x80000000U)
64973 #define SCG_APLLSSCG1_SS_PD_SHIFT                (31U)
64974 /*! SS_PD - SSCG Power Down
64975  *  0b0..SSCG is powered on
64976  *  0b1..SSCG is powered off
64977  */
64978 #define SCG_APLLSSCG1_SS_PD(x)                   (((uint32_t)(((uint32_t)(x)) << SCG_APLLSSCG1_SS_PD_SHIFT)) & SCG_APLLSSCG1_SS_PD_MASK)
64979 /*! @} */
64980 
64981 /*! @name APLL_OVRD - APLL Override Register */
64982 /*! @{ */
64983 
64984 #define SCG_APLL_OVRD_APLLPWREN_OVRD_MASK        (0x1U)
64985 #define SCG_APLL_OVRD_APLLPWREN_OVRD_SHIFT       (0U)
64986 /*! APLLPWREN_OVRD - APLL Power Enable Override if APLL_OVRD_EN=1
64987  *  0b0..APLL clock is powered off
64988  *  0b1..APLL clock is powered on
64989  */
64990 #define SCG_APLL_OVRD_APLLPWREN_OVRD(x)          (((uint32_t)(((uint32_t)(x)) << SCG_APLL_OVRD_APLLPWREN_OVRD_SHIFT)) & SCG_APLL_OVRD_APLLPWREN_OVRD_MASK)
64991 
64992 #define SCG_APLL_OVRD_APLLCLKEN_OVRD_MASK        (0x2U)
64993 #define SCG_APLL_OVRD_APLLCLKEN_OVRD_SHIFT       (1U)
64994 /*! APLLCLKEN_OVRD - APLL Clock Enable Override if APLL_OVRD_EN=1
64995  *  0b0..APLL clock is disabled
64996  *  0b1..APLL clock is enabled
64997  */
64998 #define SCG_APLL_OVRD_APLLCLKEN_OVRD(x)          (((uint32_t)(((uint32_t)(x)) << SCG_APLL_OVRD_APLLCLKEN_OVRD_SHIFT)) & SCG_APLL_OVRD_APLLCLKEN_OVRD_MASK)
64999 
65000 #define SCG_APLL_OVRD_APLL_OVRD_EN_MASK          (0x80000000U)
65001 #define SCG_APLL_OVRD_APLL_OVRD_EN_SHIFT         (31U)
65002 /*! APLL_OVRD_EN - APLL Override Enable
65003  *  0b0..APLL override is disabled
65004  *  0b1..APLL override is enabled
65005  */
65006 #define SCG_APLL_OVRD_APLL_OVRD_EN(x)            (((uint32_t)(((uint32_t)(x)) << SCG_APLL_OVRD_APLL_OVRD_EN_SHIFT)) & SCG_APLL_OVRD_APLL_OVRD_EN_MASK)
65007 /*! @} */
65008 
65009 /*! @name SPLLCSR - SPLL Control Status Register */
65010 /*! @{ */
65011 
65012 #define SCG_SPLLCSR_SPLLPWREN_MASK               (0x1U)
65013 #define SCG_SPLLCSR_SPLLPWREN_SHIFT              (0U)
65014 /*! SPLLPWREN - SPLL Power Enable
65015  *  0b0..SPLL clock is powered off
65016  *  0b1..SPLL clock is powered on
65017  */
65018 #define SCG_SPLLCSR_SPLLPWREN(x)                 (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLPWREN_SHIFT)) & SCG_SPLLCSR_SPLLPWREN_MASK)
65019 
65020 #define SCG_SPLLCSR_SPLLCLKEN_MASK               (0x2U)
65021 #define SCG_SPLLCSR_SPLLCLKEN_SHIFT              (1U)
65022 /*! SPLLCLKEN - SPLL Clock Enable
65023  *  0b0..SPLL clock is disabled
65024  *  0b1..SPLL clock is enabled
65025  */
65026 #define SCG_SPLLCSR_SPLLCLKEN(x)                 (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLCLKEN_SHIFT)) & SCG_SPLLCSR_SPLLCLKEN_MASK)
65027 
65028 #define SCG_SPLLCSR_SPLLSTEN_MASK                (0x4U)
65029 #define SCG_SPLLCSR_SPLLSTEN_SHIFT               (2U)
65030 /*! SPLLSTEN - SPLL Stop Enable
65031  *  0b0..SPLL is disabled in Deep Sleep mode
65032  *  0b1..SPLL is enabled in Deep Sleep mode
65033  */
65034 #define SCG_SPLLCSR_SPLLSTEN(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLSTEN_SHIFT)) & SCG_SPLLCSR_SPLLSTEN_MASK)
65035 
65036 #define SCG_SPLLCSR_SPLLCM_MASK                  (0x10000U)
65037 #define SCG_SPLLCSR_SPLLCM_SHIFT                 (16U)
65038 /*! SPLLCM - SPLL Clock Monitor
65039  *  0b0..SPLL Clock Monitor is disabled
65040  *  0b1..SPLL Clock Monitor is enabled
65041  */
65042 #define SCG_SPLLCSR_SPLLCM(x)                    (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLCM_SHIFT)) & SCG_SPLLCSR_SPLLCM_MASK)
65043 
65044 #define SCG_SPLLCSR_SPLLCMRE_MASK                (0x20000U)
65045 #define SCG_SPLLCSR_SPLLCMRE_SHIFT               (17U)
65046 /*! SPLLCMRE - SPLL Clock Monitor Reset Enable
65047  *  0b0..Clock monitor generates an interrupt when an error is detected
65048  *  0b1..Clock monitor generates a reset when an error is detected
65049  */
65050 #define SCG_SPLLCSR_SPLLCMRE(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLCMRE_SHIFT)) & SCG_SPLLCSR_SPLLCMRE_MASK)
65051 
65052 #define SCG_SPLLCSR_LK_MASK                      (0x800000U)
65053 #define SCG_SPLLCSR_LK_SHIFT                     (23U)
65054 /*! LK - Lock Register
65055  *  0b0..Control Status Register can be written
65056  *  0b1..Control Status Register cannot be written
65057  */
65058 #define SCG_SPLLCSR_LK(x)                        (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_LK_SHIFT)) & SCG_SPLLCSR_LK_MASK)
65059 
65060 #define SCG_SPLLCSR_SPLL_LOCK_MASK               (0x1000000U)
65061 #define SCG_SPLLCSR_SPLL_LOCK_SHIFT              (24U)
65062 /*! SPLL_LOCK - SPLL LOCK
65063  *  0b0..SPLL is not powered on or not locked
65064  *  0b1..SPLL is locked
65065  */
65066 #define SCG_SPLLCSR_SPLL_LOCK(x)                 (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLL_LOCK_SHIFT)) & SCG_SPLLCSR_SPLL_LOCK_MASK)
65067 
65068 #define SCG_SPLLCSR_SPLLSEL_MASK                 (0x2000000U)
65069 #define SCG_SPLLCSR_SPLLSEL_SHIFT                (25U)
65070 /*! SPLLSEL - SPLL Selected
65071  *  0b0..SPLL is not the system clock source
65072  *  0b1..SPLL is the system clock source
65073  */
65074 #define SCG_SPLLCSR_SPLLSEL(x)                   (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLSEL_SHIFT)) & SCG_SPLLCSR_SPLLSEL_MASK)
65075 
65076 #define SCG_SPLLCSR_SPLLERR_MASK                 (0x4000000U)
65077 #define SCG_SPLLCSR_SPLLERR_SHIFT                (26U)
65078 /*! SPLLERR - SPLL Clock Error
65079  *  0b0..SPLL Clock Monitor is disabled or has not detected an error
65080  *  0b1..SPLL Clock Monitor is enabled and detected an error
65081  */
65082 #define SCG_SPLLCSR_SPLLERR(x)                   (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLERR_SHIFT)) & SCG_SPLLCSR_SPLLERR_MASK)
65083 
65084 #define SCG_SPLLCSR_SPLL_LOCK_IE_MASK            (0x40000000U)
65085 #define SCG_SPLLCSR_SPLL_LOCK_IE_SHIFT           (30U)
65086 /*! SPLL_LOCK_IE - SPLL LOCK Interrupt Enable
65087  *  0b0..SPLL_LOCK interrupt is not enabled
65088  *  0b1..SPLL_LOCK interrupt is enabled
65089  */
65090 #define SCG_SPLLCSR_SPLL_LOCK_IE(x)              (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLL_LOCK_IE_SHIFT)) & SCG_SPLLCSR_SPLL_LOCK_IE_MASK)
65091 /*! @} */
65092 
65093 /*! @name SPLLCTRL - SPLL Control Register */
65094 /*! @{ */
65095 
65096 #define SCG_SPLLCTRL_SELR_MASK                   (0xFU)
65097 #define SCG_SPLLCTRL_SELR_SHIFT                  (0U)
65098 /*! SELR - Bandwidth select R (resistor) value. */
65099 #define SCG_SPLLCTRL_SELR(x)                     (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCTRL_SELR_SHIFT)) & SCG_SPLLCTRL_SELR_MASK)
65100 
65101 #define SCG_SPLLCTRL_SELI_MASK                   (0x3F0U)
65102 #define SCG_SPLLCTRL_SELI_SHIFT                  (4U)
65103 /*! SELI - Bandwidth select I (integration) value. */
65104 #define SCG_SPLLCTRL_SELI(x)                     (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCTRL_SELI_SHIFT)) & SCG_SPLLCTRL_SELI_MASK)
65105 
65106 #define SCG_SPLLCTRL_SELP_MASK                   (0x7C00U)
65107 #define SCG_SPLLCTRL_SELP_SHIFT                  (10U)
65108 /*! SELP - Bandwidth select P (proportional) value. */
65109 #define SCG_SPLLCTRL_SELP(x)                     (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCTRL_SELP_SHIFT)) & SCG_SPLLCTRL_SELP_MASK)
65110 
65111 #define SCG_SPLLCTRL_BYPASSPOSTDIV2_MASK         (0x10000U)
65112 #define SCG_SPLLCTRL_BYPASSPOSTDIV2_SHIFT        (16U)
65113 /*! BYPASSPOSTDIV2 - Bypass of Divide-by-2 Divider
65114  *  0b0..Use the divide-by-2 divider in the postdivider.
65115  *  0b1..Bypass of the divide-by-2 divider in the postdivider
65116  */
65117 #define SCG_SPLLCTRL_BYPASSPOSTDIV2(x)           (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCTRL_BYPASSPOSTDIV2_SHIFT)) & SCG_SPLLCTRL_BYPASSPOSTDIV2_MASK)
65118 
65119 #define SCG_SPLLCTRL_LIMUPOFF_MASK               (0x20000U)
65120 #define SCG_SPLLCTRL_LIMUPOFF_SHIFT              (17U)
65121 /*! LIMUPOFF - Up Limiter.
65122  *  0b0..Application set to non-Spectrum and Fractional applications.
65123  *  0b1..Application set to Spectrum and Fractional applications.
65124  */
65125 #define SCG_SPLLCTRL_LIMUPOFF(x)                 (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCTRL_LIMUPOFF_SHIFT)) & SCG_SPLLCTRL_LIMUPOFF_MASK)
65126 
65127 #define SCG_SPLLCTRL_BANDDIRECT_MASK             (0x40000U)
65128 #define SCG_SPLLCTRL_BANDDIRECT_SHIFT            (18U)
65129 /*! BANDDIRECT - Control of the bandwidth of the PLL.
65130  *  0b0..The bandwidth is changed synchronously with the feedback-divider
65131  *  0b1..Modifies the bandwidth of the PLL directly
65132  */
65133 #define SCG_SPLLCTRL_BANDDIRECT(x)               (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCTRL_BANDDIRECT_SHIFT)) & SCG_SPLLCTRL_BANDDIRECT_MASK)
65134 
65135 #define SCG_SPLLCTRL_BYPASSPREDIV_MASK           (0x80000U)
65136 #define SCG_SPLLCTRL_BYPASSPREDIV_SHIFT          (19U)
65137 /*! BYPASSPREDIV - Bypass of the predivider.
65138  *  0b0..Use the predivider
65139  *  0b1..Bypass of the predivider
65140  */
65141 #define SCG_SPLLCTRL_BYPASSPREDIV(x)             (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCTRL_BYPASSPREDIV_SHIFT)) & SCG_SPLLCTRL_BYPASSPREDIV_MASK)
65142 
65143 #define SCG_SPLLCTRL_BYPASSPOSTDIV_MASK          (0x100000U)
65144 #define SCG_SPLLCTRL_BYPASSPOSTDIV_SHIFT         (20U)
65145 /*! BYPASSPOSTDIV - Bypass of the postdivider.
65146  *  0b0..Use the postdivider
65147  *  0b1..Bypass of the postdivider
65148  */
65149 #define SCG_SPLLCTRL_BYPASSPOSTDIV(x)            (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCTRL_BYPASSPOSTDIV_SHIFT)) & SCG_SPLLCTRL_BYPASSPOSTDIV_MASK)
65150 
65151 #define SCG_SPLLCTRL_SOURCE_MASK                 (0x6000000U)
65152 #define SCG_SPLLCTRL_SOURCE_SHIFT                (25U)
65153 /*! SOURCE - Clock Source
65154  *  0b00..SOSC
65155  *  0b01..FIRC 48 MHz clock. FIRC_SCLK_PERIPH_EN must be set to use FIRC 48 MHz clock.
65156  *  0b10..Reserved
65157  *  0b11..No clock
65158  */
65159 #define SCG_SPLLCTRL_SOURCE(x)                   (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCTRL_SOURCE_SHIFT)) & SCG_SPLLCTRL_SOURCE_MASK)
65160 /*! @} */
65161 
65162 /*! @name SPLLSTAT - SPLL Status Register */
65163 /*! @{ */
65164 
65165 #define SCG_SPLLSTAT_NDIVACK_MASK                (0x2U)
65166 #define SCG_SPLLSTAT_NDIVACK_SHIFT               (1U)
65167 /*! NDIVACK - Predivider (N) ratio change acknowledge
65168  *  0b0..The predivider (N) ratio change is not accepted by the analog PLL.
65169  *  0b1..The predivider (N) ratio change is accepted by the analog PLL.
65170  */
65171 #define SCG_SPLLSTAT_NDIVACK(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSTAT_NDIVACK_SHIFT)) & SCG_SPLLSTAT_NDIVACK_MASK)
65172 
65173 #define SCG_SPLLSTAT_MDIVACK_MASK                (0x4U)
65174 #define SCG_SPLLSTAT_MDIVACK_SHIFT               (2U)
65175 /*! MDIVACK - Feedback (M) divider ratio change acknowledge
65176  *  0b0..The feedback (M) ratio change is not accepted by the analog PLL.
65177  *  0b1..The feedback (M) ratio change is accepted by the analog PLL.
65178  */
65179 #define SCG_SPLLSTAT_MDIVACK(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSTAT_MDIVACK_SHIFT)) & SCG_SPLLSTAT_MDIVACK_MASK)
65180 
65181 #define SCG_SPLLSTAT_PDIVACK_MASK                (0x8U)
65182 #define SCG_SPLLSTAT_PDIVACK_SHIFT               (3U)
65183 /*! PDIVACK - Postdivider (P) ratio change acknowledge
65184  *  0b0..The postdivider (P) ratio change is not accepted by the analog PLL
65185  *  0b1..The postdivider (P) ratio change is accepted by the analog PLL
65186  */
65187 #define SCG_SPLLSTAT_PDIVACK(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSTAT_PDIVACK_SHIFT)) & SCG_SPLLSTAT_PDIVACK_MASK)
65188 /*! @} */
65189 
65190 /*! @name SPLLNDIV - SPLL N Divider Register */
65191 /*! @{ */
65192 
65193 #define SCG_SPLLNDIV_NDIV_MASK                   (0xFFU)
65194 #define SCG_SPLLNDIV_NDIV_SHIFT                  (0U)
65195 /*! NDIV - Predivider divider ratio (N-divider). */
65196 #define SCG_SPLLNDIV_NDIV(x)                     (((uint32_t)(((uint32_t)(x)) << SCG_SPLLNDIV_NDIV_SHIFT)) & SCG_SPLLNDIV_NDIV_MASK)
65197 
65198 #define SCG_SPLLNDIV_NREQ_MASK                   (0x80000000U)
65199 #define SCG_SPLLNDIV_NREQ_SHIFT                  (31U)
65200 /*! NREQ - Predivider ratio change request.
65201  *  0b0..Predivider ratio change is not requested
65202  *  0b1..Predivider ratio change is requested
65203  */
65204 #define SCG_SPLLNDIV_NREQ(x)                     (((uint32_t)(((uint32_t)(x)) << SCG_SPLLNDIV_NREQ_SHIFT)) & SCG_SPLLNDIV_NREQ_MASK)
65205 /*! @} */
65206 
65207 /*! @name SPLLMDIV - SPLL M Divider Register */
65208 /*! @{ */
65209 
65210 #define SCG_SPLLMDIV_MDIV_MASK                   (0xFFFFU)
65211 #define SCG_SPLLMDIV_MDIV_SHIFT                  (0U)
65212 /*! MDIV - Feedback divider divider ratio (M-divider). */
65213 #define SCG_SPLLMDIV_MDIV(x)                     (((uint32_t)(((uint32_t)(x)) << SCG_SPLLMDIV_MDIV_SHIFT)) & SCG_SPLLMDIV_MDIV_MASK)
65214 
65215 #define SCG_SPLLMDIV_MREQ_MASK                   (0x80000000U)
65216 #define SCG_SPLLMDIV_MREQ_SHIFT                  (31U)
65217 /*! MREQ - Feedback ratio change request.
65218  *  0b0..Feedback ratio change is not requested
65219  *  0b1..Feedback ratio change is requested
65220  */
65221 #define SCG_SPLLMDIV_MREQ(x)                     (((uint32_t)(((uint32_t)(x)) << SCG_SPLLMDIV_MREQ_SHIFT)) & SCG_SPLLMDIV_MREQ_MASK)
65222 /*! @} */
65223 
65224 /*! @name SPLLPDIV - SPLL P Divider Register */
65225 /*! @{ */
65226 
65227 #define SCG_SPLLPDIV_PDIV_MASK                   (0x1FU)
65228 #define SCG_SPLLPDIV_PDIV_SHIFT                  (0U)
65229 /*! PDIV - Postdivider divider ratio (P-divider) */
65230 #define SCG_SPLLPDIV_PDIV(x)                     (((uint32_t)(((uint32_t)(x)) << SCG_SPLLPDIV_PDIV_SHIFT)) & SCG_SPLLPDIV_PDIV_MASK)
65231 
65232 #define SCG_SPLLPDIV_PREQ_MASK                   (0x80000000U)
65233 #define SCG_SPLLPDIV_PREQ_SHIFT                  (31U)
65234 /*! PREQ - Postdivider ratio change request
65235  *  0b0..Postdivider ratio change is not requested
65236  *  0b1..Postdivider ratio change is requested
65237  */
65238 #define SCG_SPLLPDIV_PREQ(x)                     (((uint32_t)(((uint32_t)(x)) << SCG_SPLLPDIV_PREQ_SHIFT)) & SCG_SPLLPDIV_PREQ_MASK)
65239 /*! @} */
65240 
65241 /*! @name SPLLLOCK_CNFG - SPLL LOCK Configuration Register */
65242 /*! @{ */
65243 
65244 #define SCG_SPLLLOCK_CNFG_LOCK_TIME_MASK         (0x1FFFFU)
65245 #define SCG_SPLLLOCK_CNFG_LOCK_TIME_SHIFT        (0U)
65246 /*! LOCK_TIME - Configures the number of reference clocks to count before SPLL is considered locked. */
65247 #define SCG_SPLLLOCK_CNFG_LOCK_TIME(x)           (((uint32_t)(((uint32_t)(x)) << SCG_SPLLLOCK_CNFG_LOCK_TIME_SHIFT)) & SCG_SPLLLOCK_CNFG_LOCK_TIME_MASK)
65248 /*! @} */
65249 
65250 /*! @name SPLLSSCGSTAT - SPLL SSCG Status Register */
65251 /*! @{ */
65252 
65253 #define SCG_SPLLSSCGSTAT_SS_MDIV_ACK_MASK        (0x1U)
65254 #define SCG_SPLLSSCGSTAT_SS_MDIV_ACK_SHIFT       (0U)
65255 /*! SS_MDIV_ACK - SS_MDIV change acknowledge
65256  *  0b0..The SS_MDIV, MF, MR, and MC ratio change is not accepted by the analog PLL
65257  *  0b1..The SS_MDIV, MF, MR, and MC ratio change is accepted by the analog PLL
65258  */
65259 #define SCG_SPLLSSCGSTAT_SS_MDIV_ACK(x)          (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSSCGSTAT_SS_MDIV_ACK_SHIFT)) & SCG_SPLLSSCGSTAT_SS_MDIV_ACK_MASK)
65260 /*! @} */
65261 
65262 /*! @name SPLLSSCG0 - SPLL Spread Spectrum Control 0 Register */
65263 /*! @{ */
65264 
65265 #define SCG_SPLLSSCG0_SS_MDIV_LSB_MASK           (0xFFFFFFFFU)
65266 #define SCG_SPLLSSCG0_SS_MDIV_LSB_SHIFT          (0U)
65267 /*! SS_MDIV_LSB - SS_MDIV[31:0] */
65268 #define SCG_SPLLSSCG0_SS_MDIV_LSB(x)             (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSSCG0_SS_MDIV_LSB_SHIFT)) & SCG_SPLLSSCG0_SS_MDIV_LSB_MASK)
65269 /*! @} */
65270 
65271 /*! @name SPLLSSCG1 - SPLL Spread Spectrum Control 1 Register */
65272 /*! @{ */
65273 
65274 #define SCG_SPLLSSCG1_SS_MDIV_MSB_MASK           (0x1U)
65275 #define SCG_SPLLSSCG1_SS_MDIV_MSB_SHIFT          (0U)
65276 /*! SS_MDIV_MSB - SS_MDIV[32] */
65277 #define SCG_SPLLSSCG1_SS_MDIV_MSB(x)             (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSSCG1_SS_MDIV_MSB_SHIFT)) & SCG_SPLLSSCG1_SS_MDIV_MSB_MASK)
65278 
65279 #define SCG_SPLLSSCG1_SS_MDIV_REQ_MASK           (0x2U)
65280 #define SCG_SPLLSSCG1_SS_MDIV_REQ_SHIFT          (1U)
65281 /*! SS_MDIV_REQ - SS_MDIV[32:0] change request.
65282  *  0b0..SS_MDIV change is not requested
65283  *  0b1..SS_MDIV change is requested
65284  */
65285 #define SCG_SPLLSSCG1_SS_MDIV_REQ(x)             (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSSCG1_SS_MDIV_REQ_SHIFT)) & SCG_SPLLSSCG1_SS_MDIV_REQ_MASK)
65286 
65287 #define SCG_SPLLSSCG1_MF_MASK                    (0x1CU)
65288 #define SCG_SPLLSSCG1_MF_SHIFT                   (2U)
65289 /*! MF - Modulation Frequency Control */
65290 #define SCG_SPLLSSCG1_MF(x)                      (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSSCG1_MF_SHIFT)) & SCG_SPLLSSCG1_MF_MASK)
65291 
65292 #define SCG_SPLLSSCG1_MR_MASK                    (0xE0U)
65293 #define SCG_SPLLSSCG1_MR_SHIFT                   (5U)
65294 /*! MR - Modulation Depth Control */
65295 #define SCG_SPLLSSCG1_MR(x)                      (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSSCG1_MR_SHIFT)) & SCG_SPLLSSCG1_MR_MASK)
65296 
65297 #define SCG_SPLLSSCG1_MC_MASK                    (0x300U)
65298 #define SCG_SPLLSSCG1_MC_SHIFT                   (8U)
65299 /*! MC - Modulation Waveform Control
65300  *  0b00..MC[1:0] no compensation
65301  *  0b11..MC[1:0] maximum compensation
65302  */
65303 #define SCG_SPLLSSCG1_MC(x)                      (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSSCG1_MC_SHIFT)) & SCG_SPLLSSCG1_MC_MASK)
65304 
65305 #define SCG_SPLLSSCG1_DITHER_MASK                (0x400U)
65306 #define SCG_SPLLSSCG1_DITHER_SHIFT               (10U)
65307 /*! DITHER - Dither Enable
65308  *  0b0..Dither is not enabled
65309  *  0b1..Dither is enabled
65310  */
65311 #define SCG_SPLLSSCG1_DITHER(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSSCG1_DITHER_SHIFT)) & SCG_SPLLSSCG1_DITHER_MASK)
65312 
65313 #define SCG_SPLLSSCG1_SEL_SS_MDIV_MASK           (0x800U)
65314 #define SCG_SPLLSSCG1_SEL_SS_MDIV_SHIFT          (11U)
65315 /*! SEL_SS_MDIV - SS_MDIV select.
65316  *  0b0..Feedback divider ratio is MDIV[15:0]
65317  *  0b1..Feedback divider ratio is SS_MDIV[32:0]
65318  */
65319 #define SCG_SPLLSSCG1_SEL_SS_MDIV(x)             (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSSCG1_SEL_SS_MDIV_SHIFT)) & SCG_SPLLSSCG1_SEL_SS_MDIV_MASK)
65320 
65321 #define SCG_SPLLSSCG1_SS_PD_MASK                 (0x80000000U)
65322 #define SCG_SPLLSSCG1_SS_PD_SHIFT                (31U)
65323 /*! SS_PD - SSCG Power Down
65324  *  0b0..SSCG is powered on
65325  *  0b1..SSCG is powered off
65326  */
65327 #define SCG_SPLLSSCG1_SS_PD(x)                   (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSSCG1_SS_PD_SHIFT)) & SCG_SPLLSSCG1_SS_PD_MASK)
65328 /*! @} */
65329 
65330 /*! @name SPLL_OVRD - SPLL Override Register */
65331 /*! @{ */
65332 
65333 #define SCG_SPLL_OVRD_SPLLPWREN_OVRD_MASK        (0x1U)
65334 #define SCG_SPLL_OVRD_SPLLPWREN_OVRD_SHIFT       (0U)
65335 /*! SPLLPWREN_OVRD - SPLL Power Enable Override if SPLL_OVRD_EN=1
65336  *  0b0..SPLL clock is powered off
65337  *  0b1..SPLL clock is powered on
65338  */
65339 #define SCG_SPLL_OVRD_SPLLPWREN_OVRD(x)          (((uint32_t)(((uint32_t)(x)) << SCG_SPLL_OVRD_SPLLPWREN_OVRD_SHIFT)) & SCG_SPLL_OVRD_SPLLPWREN_OVRD_MASK)
65340 
65341 #define SCG_SPLL_OVRD_SPLLCLKEN_OVRD_MASK        (0x2U)
65342 #define SCG_SPLL_OVRD_SPLLCLKEN_OVRD_SHIFT       (1U)
65343 /*! SPLLCLKEN_OVRD - SPLL Clock Enable Override if SPLL_OVRD_EN=1
65344  *  0b0..SPLL clock is disabled
65345  *  0b1..SPLL clock is enabled
65346  */
65347 #define SCG_SPLL_OVRD_SPLLCLKEN_OVRD(x)          (((uint32_t)(((uint32_t)(x)) << SCG_SPLL_OVRD_SPLLCLKEN_OVRD_SHIFT)) & SCG_SPLL_OVRD_SPLLCLKEN_OVRD_MASK)
65348 
65349 #define SCG_SPLL_OVRD_SPLL_OVRD_EN_MASK          (0x80000000U)
65350 #define SCG_SPLL_OVRD_SPLL_OVRD_EN_SHIFT         (31U)
65351 /*! SPLL_OVRD_EN - SPLL Override Enable
65352  *  0b0..SPLL override is disabled
65353  *  0b1..SPLL override is enabled
65354  */
65355 #define SCG_SPLL_OVRD_SPLL_OVRD_EN(x)            (((uint32_t)(((uint32_t)(x)) << SCG_SPLL_OVRD_SPLL_OVRD_EN_SHIFT)) & SCG_SPLL_OVRD_SPLL_OVRD_EN_MASK)
65356 /*! @} */
65357 
65358 /*! @name UPLLCSR - UPLL Control Status Register */
65359 /*! @{ */
65360 
65361 #define SCG_UPLLCSR_UPLLCM_MASK                  (0x10000U)
65362 #define SCG_UPLLCSR_UPLLCM_SHIFT                 (16U)
65363 /*! UPLLCM - UPLL Clock Monitor
65364  *  0b0..UPLL Clock Monitor is disabled
65365  *  0b1..UPLL Clock Monitor is enabled
65366  */
65367 #define SCG_UPLLCSR_UPLLCM(x)                    (((uint32_t)(((uint32_t)(x)) << SCG_UPLLCSR_UPLLCM_SHIFT)) & SCG_UPLLCSR_UPLLCM_MASK)
65368 
65369 #define SCG_UPLLCSR_UPLLCMRE_MASK                (0x20000U)
65370 #define SCG_UPLLCSR_UPLLCMRE_SHIFT               (17U)
65371 /*! UPLLCMRE - UPLL Clock Monitor Reset Enable
65372  *  0b0..Clock monitor generates an interrupt when an error is detected
65373  *  0b1..Clock monitor generates a reset when an error is detected
65374  */
65375 #define SCG_UPLLCSR_UPLLCMRE(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_UPLLCSR_UPLLCMRE_SHIFT)) & SCG_UPLLCSR_UPLLCMRE_MASK)
65376 
65377 #define SCG_UPLLCSR_LK_MASK                      (0x800000U)
65378 #define SCG_UPLLCSR_LK_SHIFT                     (23U)
65379 /*! LK - Lock Register
65380  *  0b0..Control Status Register can be written
65381  *  0b1..Control Status Register cannot be written
65382  */
65383 #define SCG_UPLLCSR_LK(x)                        (((uint32_t)(((uint32_t)(x)) << SCG_UPLLCSR_LK_SHIFT)) & SCG_UPLLCSR_LK_MASK)
65384 
65385 #define SCG_UPLLCSR_UPLLVLD_MASK                 (0x1000000U)
65386 #define SCG_UPLLCSR_UPLLVLD_SHIFT                (24U)
65387 /*! UPLLVLD - UPLL Valid
65388  *  0b0..UPLL is not enabled or clock is not valid
65389  *  0b1..UPLL is enabled and output clock is valid
65390  */
65391 #define SCG_UPLLCSR_UPLLVLD(x)                   (((uint32_t)(((uint32_t)(x)) << SCG_UPLLCSR_UPLLVLD_SHIFT)) & SCG_UPLLCSR_UPLLVLD_MASK)
65392 
65393 #define SCG_UPLLCSR_UPLLSEL_MASK                 (0x2000000U)
65394 #define SCG_UPLLCSR_UPLLSEL_SHIFT                (25U)
65395 /*! UPLLSEL - UPLL Selected
65396  *  0b0..UPLL is not the system clock source
65397  *  0b1..UPLL is the system clock source
65398  */
65399 #define SCG_UPLLCSR_UPLLSEL(x)                   (((uint32_t)(((uint32_t)(x)) << SCG_UPLLCSR_UPLLSEL_SHIFT)) & SCG_UPLLCSR_UPLLSEL_MASK)
65400 
65401 #define SCG_UPLLCSR_UPLLERR_MASK                 (0x4000000U)
65402 #define SCG_UPLLCSR_UPLLERR_SHIFT                (26U)
65403 /*! UPLLERR - UPLL Clock Error
65404  *  0b0..UPLL Clock Monitor is disabled or has not detected an error
65405  *  0b1..UPLL Clock Monitor is enabled and detected an error
65406  */
65407 #define SCG_UPLLCSR_UPLLERR(x)                   (((uint32_t)(((uint32_t)(x)) << SCG_UPLLCSR_UPLLERR_SHIFT)) & SCG_UPLLCSR_UPLLERR_MASK)
65408 /*! @} */
65409 
65410 /*! @name LDOCSR - LDO Control and Status Register */
65411 /*! @{ */
65412 
65413 #define SCG_LDOCSR_LDOEN_MASK                    (0x1U)
65414 #define SCG_LDOCSR_LDOEN_SHIFT                   (0U)
65415 /*! LDOEN - LDO Enable
65416  *  0b0..LDO is disabled
65417  *  0b1..LDO is enabled
65418  */
65419 #define SCG_LDOCSR_LDOEN(x)                      (((uint32_t)(((uint32_t)(x)) << SCG_LDOCSR_LDOEN_SHIFT)) & SCG_LDOCSR_LDOEN_MASK)
65420 
65421 #define SCG_LDOCSR_VOUT_SEL_MASK                 (0xEU)
65422 #define SCG_LDOCSR_VOUT_SEL_SHIFT                (1U)
65423 /*! VOUT_SEL - LDO output voltage select
65424  *  0b000..VOUT = 1V
65425  *  0b001..VOUT = 1V
65426  *  0b010..VOUT = 1V
65427  *  0b011..VOUT = 1.05V
65428  *  0b100..VOUT = 1.1V
65429  *  0b101..VOUT = 1.15V
65430  *  0b110..VOUT = 1.2V
65431  *  0b111..VOUT = 1.25V
65432  */
65433 #define SCG_LDOCSR_VOUT_SEL(x)                   (((uint32_t)(((uint32_t)(x)) << SCG_LDOCSR_VOUT_SEL_SHIFT)) & SCG_LDOCSR_VOUT_SEL_MASK)
65434 
65435 #define SCG_LDOCSR_LDOBYPASS_MASK                (0x10U)
65436 #define SCG_LDOCSR_LDOBYPASS_SHIFT               (4U)
65437 /*! LDOBYPASS - LDO Bypass
65438  *  0b0..LDO is not bypassed
65439  *  0b1..LDO is bypassed
65440  */
65441 #define SCG_LDOCSR_LDOBYPASS(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_LDOCSR_LDOBYPASS_SHIFT)) & SCG_LDOCSR_LDOBYPASS_MASK)
65442 
65443 #define SCG_LDOCSR_VOUT_OK_MASK                  (0x80000000U)
65444 #define SCG_LDOCSR_VOUT_OK_SHIFT                 (31U)
65445 /*! VOUT_OK - LDO VOUT OK Inform.
65446  *  0b0..LDO output VOUT is not OK
65447  *  0b1..LDO output VOUT is OK
65448  */
65449 #define SCG_LDOCSR_VOUT_OK(x)                    (((uint32_t)(((uint32_t)(x)) << SCG_LDOCSR_VOUT_OK_SHIFT)) & SCG_LDOCSR_VOUT_OK_MASK)
65450 /*! @} */
65451 
65452 
65453 /*!
65454  * @}
65455  */ /* end of group SCG_Register_Masks */
65456 
65457 
65458 /* SCG - Peripheral instance base addresses */
65459 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
65460   /** Peripheral SCG0 base address */
65461   #define SCG0_BASE                                (0x50044000u)
65462   /** Peripheral SCG0 base address */
65463   #define SCG0_BASE_NS                             (0x40044000u)
65464   /** Peripheral SCG0 base pointer */
65465   #define SCG0                                     ((SCG_Type *)SCG0_BASE)
65466   /** Peripheral SCG0 base pointer */
65467   #define SCG0_NS                                  ((SCG_Type *)SCG0_BASE_NS)
65468   /** Array initializer of SCG peripheral base addresses */
65469   #define SCG_BASE_ADDRS                           { SCG0_BASE }
65470   /** Array initializer of SCG peripheral base pointers */
65471   #define SCG_BASE_PTRS                            { SCG0 }
65472   /** Array initializer of SCG peripheral base addresses */
65473   #define SCG_BASE_ADDRS_NS                        { SCG0_BASE_NS }
65474   /** Array initializer of SCG peripheral base pointers */
65475   #define SCG_BASE_PTRS_NS                         { SCG0_NS }
65476 #else
65477   /** Peripheral SCG0 base address */
65478   #define SCG0_BASE                                (0x40044000u)
65479   /** Peripheral SCG0 base pointer */
65480   #define SCG0                                     ((SCG_Type *)SCG0_BASE)
65481   /** Array initializer of SCG peripheral base addresses */
65482   #define SCG_BASE_ADDRS                           { SCG0_BASE }
65483   /** Array initializer of SCG peripheral base pointers */
65484   #define SCG_BASE_PTRS                            { SCG0 }
65485 #endif
65486 
65487 /*!
65488  * @}
65489  */ /* end of group SCG_Peripheral_Access_Layer */
65490 
65491 
65492 /* ----------------------------------------------------------------------------
65493    -- SCT Peripheral Access Layer
65494    ---------------------------------------------------------------------------- */
65495 
65496 /*!
65497  * @addtogroup SCT_Peripheral_Access_Layer SCT Peripheral Access Layer
65498  * @{
65499  */
65500 
65501 /** SCT - Register Layout Typedef */
65502 typedef struct {
65503   __IO uint32_t CONFIG;                            /**< SCT Configuration, offset: 0x0 */
65504   union {                                          /* offset: 0x4 */
65505     struct {                                         /* offset: 0x4 */
65506       __IO uint16_t CTRLL;                             /**< SCT_CTRLL register, offset: 0x4 */
65507       __IO uint16_t CTRLH;                             /**< SCT_CTRLH register, offset: 0x6 */
65508     } CTRL_ACCESS16BIT;
65509     __IO uint32_t CTRL;                              /**< SCT Control, offset: 0x4 */
65510   };
65511   union {                                          /* offset: 0x8 */
65512     struct {                                         /* offset: 0x8 */
65513       __IO uint16_t LIMITL;                            /**< SCT_LIMITL register, offset: 0x8 */
65514       __IO uint16_t LIMITH;                            /**< SCT_LIMITH register, offset: 0xA */
65515     } LIMIT_ACCESS16BIT;
65516     __IO uint32_t LIMIT;                             /**< SCT Limit Event Select, offset: 0x8 */
65517   };
65518   union {                                          /* offset: 0xC */
65519     struct {                                         /* offset: 0xC */
65520       __IO uint16_t HALTL;                             /**< SCT_HALTL register, offset: 0xC */
65521       __IO uint16_t HALTH;                             /**< SCT_HALTH register, offset: 0xE */
65522     } HALT_ACCESS16BIT;
65523     __IO uint32_t HALT;                              /**< Halt Event Select, offset: 0xC */
65524   };
65525   union {                                          /* offset: 0x10 */
65526     struct {                                         /* offset: 0x10 */
65527       __IO uint16_t STOPL;                             /**< SCT_STOPL register, offset: 0x10 */
65528       __IO uint16_t STOPH;                             /**< SCT_STOPH register, offset: 0x12 */
65529     } STOP_ACCESS16BIT;
65530     __IO uint32_t STOP;                              /**< Stop Event Select, offset: 0x10 */
65531   };
65532   union {                                          /* offset: 0x14 */
65533     struct {                                         /* offset: 0x14 */
65534       __IO uint16_t STARTL;                            /**< SCT_STARTL register, offset: 0x14 */
65535       __IO uint16_t STARTH;                            /**< SCT_STARTH register, offset: 0x16 */
65536     } START_ACCESS16BIT;
65537     __IO uint32_t START;                             /**< Start Event Select, offset: 0x14 */
65538   };
65539   __IO uint32_t DITHER;                            /**< Dither Condition, offset: 0x18 */
65540        uint8_t RESERVED_0[36];
65541   union {                                          /* offset: 0x40 */
65542     struct {                                         /* offset: 0x40 */
65543       __IO uint16_t COUNTL;                            /**< SCT_COUNTL register, offset: 0x40 */
65544       __IO uint16_t COUNTH;                            /**< SCT_COUNTH register, offset: 0x42 */
65545     } COUNT_ACCESS16BIT;
65546     __IO uint32_t COUNT;                             /**< Counter Value, offset: 0x40 */
65547   };
65548   union {                                          /* offset: 0x44 */
65549     struct {                                         /* offset: 0x44 */
65550       __IO uint16_t STATEL;                            /**< SCT_STATEL register, offset: 0x44 */
65551       __IO uint16_t STATEH;                            /**< SCT_STATEH register, offset: 0x46 */
65552     } STATE_ACCESS16BIT;
65553     __IO uint32_t STATE;                             /**< State Variable, offset: 0x44 */
65554   };
65555   __I  uint32_t INPUT;                             /**< Input State, offset: 0x48 */
65556   union {                                          /* offset: 0x4C */
65557     struct {                                         /* offset: 0x4C */
65558       __IO uint16_t REGMODEL;                          /**< SCT_REGMODEL register, offset: 0x4C */
65559       __IO uint16_t REGMODEH;                          /**< SCT_REGMODEH register, offset: 0x4E */
65560     } REGMODE_ACCESS16BIT;
65561     __IO uint32_t REGMODE;                           /**< Match and Capture Register Mode, offset: 0x4C */
65562   };
65563   __IO uint32_t OUTPUT;                            /**< Output State, offset: 0x50 */
65564   __IO uint32_t OUTPUTDIRCTRL;                     /**< Output Counter Direction Control, offset: 0x54 */
65565   __IO uint32_t RES;                               /**< Output Conflict Resolution, offset: 0x58 */
65566   __IO uint32_t DMAREQ0;                           /**< DMA Request 0, offset: 0x5C */
65567   __IO uint32_t DMAREQ1;                           /**< DMA Request 1, offset: 0x60 */
65568        uint8_t RESERVED_1[140];
65569   __IO uint32_t EVEN;                              /**< Event Interrupt Enable, offset: 0xF0 */
65570   __IO uint32_t EVFLAG;                            /**< Event Flag, offset: 0xF4 */
65571   __IO uint32_t CONEN;                             /**< Conflict Interrupt Enable, offset: 0xF8 */
65572   __IO uint32_t CONFLAG;                           /**< Conflict Flag, offset: 0xFC */
65573   union {                                          /* offset: 0x100 */
65574     union {                                          /* offset: 0x100, array step: 0x4 */
65575       struct {                                         /* offset: 0x100, array step: 0x4 */
65576         __IO uint16_t CAPL;                              /**< SCT_CAPL register, array offset: 0x100, array step: 0x4 */
65577         __IO uint16_t CAPH;                              /**< SCT_CAPH register, array offset: 0x102, array step: 0x4 */
65578       } CAP_ACCESS16BIT[16];
65579       __IO uint32_t CAP[16];                           /**< Capture Value, array offset: 0x100, array step: 0x4 */
65580     };
65581     union {                                          /* offset: 0x100, array step: 0x4 */
65582       struct {                                         /* offset: 0x100, array step: 0x4 */
65583         __IO uint16_t MATCHL;                            /**< SCT_MATCHL register, array offset: 0x100, array step: 0x4 */
65584         __IO uint16_t MATCHH;                            /**< SCT_MATCHH register, array offset: 0x102, array step: 0x4 */
65585       } MATCH_ACCESS16BIT[16];
65586       __IO uint32_t MATCH[16];                         /**< Match Value, array offset: 0x100, array step: 0x4 */
65587     };
65588   };
65589   __IO uint32_t FRACMAT[6];                        /**< Fractional Match, array offset: 0x140, array step: 0x4 */
65590        uint8_t RESERVED_2[168];
65591   union {                                          /* offset: 0x200 */
65592     union {                                          /* offset: 0x200, array step: 0x4 */
65593       struct {                                         /* offset: 0x200, array step: 0x4 */
65594         __IO uint16_t CAPCTRLL;                          /**< SCT_CAPCTRLL register, array offset: 0x200, array step: 0x4 */
65595         __IO uint16_t CAPCTRLH;                          /**< SCT_CAPCTRLH register, array offset: 0x202, array step: 0x4 */
65596       } CAPCTRL_ACCESS16BIT[16];
65597       __IO uint32_t CAPCTRL[16];                       /**< Capture Control, array offset: 0x200, array step: 0x4 */
65598     };
65599     union {                                          /* offset: 0x200, array step: 0x4 */
65600       struct {                                         /* offset: 0x200, array step: 0x4 */
65601         __IO uint16_t MATCHRELL;                         /**< SCT_MATCHRELL register, array offset: 0x200, array step: 0x4 */
65602         __IO uint16_t MATCHRELH;                         /**< SCT_MATCHRELH register, array offset: 0x202, array step: 0x4 */
65603       } MATCHREL_ACCESS16BIT[16];
65604       __IO uint32_t MATCHREL[16];                      /**< Match Reload Value, array offset: 0x200, array step: 0x4 */
65605     };
65606   };
65607   __IO uint32_t FRACMATREL[6];                     /**< Fractional Match Reload, array offset: 0x240, array step: 0x4 */
65608        uint8_t RESERVED_3[168];
65609   struct {                                         /* offset: 0x300, array step: 0x8 */
65610     __IO uint32_t STATE;                             /**< Event n State, array offset: 0x300, array step: 0x8 */
65611     __IO uint32_t CTRL;                              /**< Event n Control, array offset: 0x304, array step: 0x8 */
65612   } EV[16];
65613        uint8_t RESERVED_4[384];
65614   struct {                                         /* offset: 0x500, array step: 0x8 */
65615     __IO uint32_t SET;                               /**< Output n Set, array offset: 0x500, array step: 0x8 */
65616     __IO uint32_t CLR;                               /**< Output n Clear, array offset: 0x504, array step: 0x8 */
65617   } OUT[10];
65618 } SCT_Type;
65619 
65620 /* ----------------------------------------------------------------------------
65621    -- SCT Register Masks
65622    ---------------------------------------------------------------------------- */
65623 
65624 /*!
65625  * @addtogroup SCT_Register_Masks SCT Register Masks
65626  * @{
65627  */
65628 
65629 /*! @name CONFIG - SCT Configuration */
65630 /*! @{ */
65631 
65632 #define SCT_CONFIG_UNIFY_MASK                    (0x1U)
65633 #define SCT_CONFIG_UNIFY_SHIFT                   (0U)
65634 /*! UNIFY - SCT Operation
65635  *  0b0..Dual counters, COUNTER_L and COUNTER_H
65636  *  0b1..Unified counter
65637  */
65638 #define SCT_CONFIG_UNIFY(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_UNIFY_SHIFT)) & SCT_CONFIG_UNIFY_MASK)
65639 
65640 #define SCT_CONFIG_CLKMODE_MASK                  (0x6U)
65641 #define SCT_CONFIG_CLKMODE_SHIFT                 (1U)
65642 /*! CLKMODE - SCT Clock Mode
65643  *  0b00..System Clock mode
65644  *  0b01..Sampled System Clock mode
65645  *  0b10..SCT Input Clock mode
65646  *  0b11..Asynchronous mode
65647  */
65648 #define SCT_CONFIG_CLKMODE(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CLKMODE_SHIFT)) & SCT_CONFIG_CLKMODE_MASK)
65649 
65650 #define SCT_CONFIG_CKSEL_MASK                    (0x78U)
65651 #define SCT_CONFIG_CKSEL_SHIFT                   (3U)
65652 /*! CKSEL - SCT Clock Select
65653  *  0b0000..Rising edges on input 0
65654  *  0b0001..Falling edges on input 0
65655  *  0b0010..Rising edges on input 1
65656  *  0b0011..Falling edges on input 1
65657  *  0b0100..Rising edges on input 2
65658  *  0b0101..Falling edges on input 2
65659  *  0b0110..Rising edges on input 3
65660  *  0b0111..Falling edges on input 3
65661  *  0b1000..Rising edges on input 4
65662  *  0b1001..Falling edges on input 4
65663  *  0b1010..Rising edges on input 5
65664  *  0b1011..Falling edges on input 5
65665  *  0b1100..Rising edges on input 6
65666  *  0b1101..Falling edges on input 6
65667  *  0b1110..Rising edges on input 7
65668  *  0b1111..Falling edges on input 7
65669  */
65670 #define SCT_CONFIG_CKSEL(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CKSEL_SHIFT)) & SCT_CONFIG_CKSEL_MASK)
65671 
65672 #define SCT_CONFIG_NORELOAD_L_MASK               (0x80U)
65673 #define SCT_CONFIG_NORELOAD_L_SHIFT              (7U)
65674 /*! NORELOAD_L - No Reload Lower Match
65675  *  0b0..Reloaded
65676  *  0b1..Not reloaded
65677  */
65678 #define SCT_CONFIG_NORELOAD_L(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_L_SHIFT)) & SCT_CONFIG_NORELOAD_L_MASK)
65679 
65680 #define SCT_CONFIG_NORELOAD_H_MASK               (0x100U)
65681 #define SCT_CONFIG_NORELOAD_H_SHIFT              (8U)
65682 /*! NORELOAD_H - No Reload Higher Match
65683  *  0b0..Reloaded
65684  *  0b1..Not reloaded
65685  */
65686 #define SCT_CONFIG_NORELOAD_H(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_H_SHIFT)) & SCT_CONFIG_NORELOAD_H_MASK)
65687 
65688 #define SCT_CONFIG_INSYNC_MASK                   (0x1FE00U)
65689 #define SCT_CONFIG_INSYNC_SHIFT                  (9U)
65690 /*! INSYNC - Input Synchronization */
65691 #define SCT_CONFIG_INSYNC(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_INSYNC_SHIFT)) & SCT_CONFIG_INSYNC_MASK)
65692 
65693 #define SCT_CONFIG_AUTOLIMIT_L_MASK              (0x20000U)
65694 #define SCT_CONFIG_AUTOLIMIT_L_SHIFT             (17U)
65695 /*! AUTOLIMIT_L - Auto Limit Lower
65696  *  0b0..Disables
65697  *  0b1..Enables
65698  */
65699 #define SCT_CONFIG_AUTOLIMIT_L(x)                (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_L_SHIFT)) & SCT_CONFIG_AUTOLIMIT_L_MASK)
65700 
65701 #define SCT_CONFIG_AUTOLIMIT_H_MASK              (0x40000U)
65702 #define SCT_CONFIG_AUTOLIMIT_H_SHIFT             (18U)
65703 /*! AUTOLIMIT_H - Auto Limit Higher
65704  *  0b0..Disables
65705  *  0b1..Enables
65706  */
65707 #define SCT_CONFIG_AUTOLIMIT_H(x)                (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_H_SHIFT)) & SCT_CONFIG_AUTOLIMIT_H_MASK)
65708 /*! @} */
65709 
65710 /*! @name CTRLL - SCT_CTRLL register */
65711 /*! @{ */
65712 
65713 #define SCT_CTRLL_DOWN_L_MASK                    (0x1U)
65714 #define SCT_CTRLL_DOWN_L_SHIFT                   (0U)
65715 /*! DOWN_L - Down Counter Low
65716  *  0b0..Up
65717  *  0b1..Down
65718  */
65719 #define SCT_CTRLL_DOWN_L(x)                      (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_DOWN_L_SHIFT)) & SCT_CTRLL_DOWN_L_MASK)
65720 
65721 #define SCT_CTRLL_STOP_L_MASK                    (0x2U)
65722 #define SCT_CTRLL_STOP_L_SHIFT                   (1U)
65723 /*! STOP_L - Stop Counter Low
65724  *  0b0..Disabled
65725  *  0b1..Enabled
65726  */
65727 #define SCT_CTRLL_STOP_L(x)                      (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_STOP_L_SHIFT)) & SCT_CTRLL_STOP_L_MASK)
65728 
65729 #define SCT_CTRLL_HALT_L_MASK                    (0x4U)
65730 #define SCT_CTRLL_HALT_L_SHIFT                   (2U)
65731 /*! HALT_L - Halt Counter Low
65732  *  0b0..Disabled
65733  *  0b1..Enabled
65734  */
65735 #define SCT_CTRLL_HALT_L(x)                      (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_HALT_L_SHIFT)) & SCT_CTRLL_HALT_L_MASK)
65736 
65737 #define SCT_CTRLL_CLRCTR_L_MASK                  (0x8U)
65738 #define SCT_CTRLL_CLRCTR_L_SHIFT                 (3U)
65739 /*! CLRCTR_L - Clear Counter Low */
65740 #define SCT_CTRLL_CLRCTR_L(x)                    (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_CLRCTR_L_SHIFT)) & SCT_CTRLL_CLRCTR_L_MASK)
65741 
65742 #define SCT_CTRLL_BIDIR_L_MASK                   (0x10U)
65743 #define SCT_CTRLL_BIDIR_L_SHIFT                  (4U)
65744 /*! BIDIR_L - Bidirectional Select Low
65745  *  0b0..Up
65746  *  0b1..Up-down
65747  */
65748 #define SCT_CTRLL_BIDIR_L(x)                     (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_BIDIR_L_SHIFT)) & SCT_CTRLL_BIDIR_L_MASK)
65749 
65750 #define SCT_CTRLL_PRE_L_MASK                     (0x1FE0U)
65751 #define SCT_CTRLL_PRE_L_SHIFT                    (5U)
65752 /*! PRE_L - Prescaler for Low Counter */
65753 #define SCT_CTRLL_PRE_L(x)                       (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_PRE_L_SHIFT)) & SCT_CTRLL_PRE_L_MASK)
65754 /*! @} */
65755 
65756 /*! @name CTRLH - SCT_CTRLH register */
65757 /*! @{ */
65758 
65759 #define SCT_CTRLH_DOWN_H_MASK                    (0x1U)
65760 #define SCT_CTRLH_DOWN_H_SHIFT                   (0U)
65761 /*! DOWN_H - Down Counter High
65762  *  0b0..Up
65763  *  0b1..Down
65764  */
65765 #define SCT_CTRLH_DOWN_H(x)                      (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_DOWN_H_SHIFT)) & SCT_CTRLH_DOWN_H_MASK)
65766 
65767 #define SCT_CTRLH_STOP_H_MASK                    (0x2U)
65768 #define SCT_CTRLH_STOP_H_SHIFT                   (1U)
65769 /*! STOP_H - Stop Counter High
65770  *  0b0..Disabled
65771  *  0b1..Enabled
65772  */
65773 #define SCT_CTRLH_STOP_H(x)                      (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_STOP_H_SHIFT)) & SCT_CTRLH_STOP_H_MASK)
65774 
65775 #define SCT_CTRLH_HALT_H_MASK                    (0x4U)
65776 #define SCT_CTRLH_HALT_H_SHIFT                   (2U)
65777 /*! HALT_H - Halt Counter High
65778  *  0b0..Disable
65779  *  0b1..Enable
65780  */
65781 #define SCT_CTRLH_HALT_H(x)                      (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_HALT_H_SHIFT)) & SCT_CTRLH_HALT_H_MASK)
65782 
65783 #define SCT_CTRLH_CLRCTR_H_MASK                  (0x8U)
65784 #define SCT_CTRLH_CLRCTR_H_SHIFT                 (3U)
65785 /*! CLRCTR_H - Clear Counter High */
65786 #define SCT_CTRLH_CLRCTR_H(x)                    (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_CLRCTR_H_SHIFT)) & SCT_CTRLH_CLRCTR_H_MASK)
65787 
65788 #define SCT_CTRLH_BIDIR_H_MASK                   (0x10U)
65789 #define SCT_CTRLH_BIDIR_H_SHIFT                  (4U)
65790 /*! BIDIR_H - Bidirectional Select High
65791  *  0b0..Up
65792  *  0b1..Up-down
65793  */
65794 #define SCT_CTRLH_BIDIR_H(x)                     (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_BIDIR_H_SHIFT)) & SCT_CTRLH_BIDIR_H_MASK)
65795 
65796 #define SCT_CTRLH_PRE_H_MASK                     (0x1FE0U)
65797 #define SCT_CTRLH_PRE_H_SHIFT                    (5U)
65798 /*! PRE_H - Prescaler for High Counter */
65799 #define SCT_CTRLH_PRE_H(x)                       (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_PRE_H_SHIFT)) & SCT_CTRLH_PRE_H_MASK)
65800 /*! @} */
65801 
65802 /*! @name CTRL - SCT Control */
65803 /*! @{ */
65804 
65805 #define SCT_CTRL_DOWN_L_MASK                     (0x1U)
65806 #define SCT_CTRL_DOWN_L_SHIFT                    (0U)
65807 /*! DOWN_L - Down Counter Low
65808  *  0b0..Up
65809  *  0b1..Down
65810  */
65811 #define SCT_CTRL_DOWN_L(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_L_SHIFT)) & SCT_CTRL_DOWN_L_MASK)
65812 
65813 #define SCT_CTRL_STOP_L_MASK                     (0x2U)
65814 #define SCT_CTRL_STOP_L_SHIFT                    (1U)
65815 /*! STOP_L - Stop Counter Low
65816  *  0b0..Disabled
65817  *  0b1..Enabled
65818  */
65819 #define SCT_CTRL_STOP_L(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_L_SHIFT)) & SCT_CTRL_STOP_L_MASK)
65820 
65821 #define SCT_CTRL_HALT_L_MASK                     (0x4U)
65822 #define SCT_CTRL_HALT_L_SHIFT                    (2U)
65823 /*! HALT_L - Halt Counter Low
65824  *  0b0..Disabled
65825  *  0b1..Enabled
65826  */
65827 #define SCT_CTRL_HALT_L(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_L_SHIFT)) & SCT_CTRL_HALT_L_MASK)
65828 
65829 #define SCT_CTRL_CLRCTR_L_MASK                   (0x8U)
65830 #define SCT_CTRL_CLRCTR_L_SHIFT                  (3U)
65831 /*! CLRCTR_L - Clear Counter Low */
65832 #define SCT_CTRL_CLRCTR_L(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_L_SHIFT)) & SCT_CTRL_CLRCTR_L_MASK)
65833 
65834 #define SCT_CTRL_BIDIR_L_MASK                    (0x10U)
65835 #define SCT_CTRL_BIDIR_L_SHIFT                   (4U)
65836 /*! BIDIR_L - Bidirectional Select Low
65837  *  0b0..Up
65838  *  0b1..Up-down
65839  */
65840 #define SCT_CTRL_BIDIR_L(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_L_SHIFT)) & SCT_CTRL_BIDIR_L_MASK)
65841 
65842 #define SCT_CTRL_PRE_L_MASK                      (0x1FE0U)
65843 #define SCT_CTRL_PRE_L_SHIFT                     (5U)
65844 /*! PRE_L - Prescaler for Low Counter */
65845 #define SCT_CTRL_PRE_L(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_L_SHIFT)) & SCT_CTRL_PRE_L_MASK)
65846 
65847 #define SCT_CTRL_DOWN_H_MASK                     (0x10000U)
65848 #define SCT_CTRL_DOWN_H_SHIFT                    (16U)
65849 /*! DOWN_H - Down Counter High
65850  *  0b0..Up
65851  *  0b1..Down
65852  */
65853 #define SCT_CTRL_DOWN_H(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_H_SHIFT)) & SCT_CTRL_DOWN_H_MASK)
65854 
65855 #define SCT_CTRL_STOP_H_MASK                     (0x20000U)
65856 #define SCT_CTRL_STOP_H_SHIFT                    (17U)
65857 /*! STOP_H - Stop Counter High
65858  *  0b0..Disabled
65859  *  0b1..Enabled
65860  */
65861 #define SCT_CTRL_STOP_H(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_H_SHIFT)) & SCT_CTRL_STOP_H_MASK)
65862 
65863 #define SCT_CTRL_HALT_H_MASK                     (0x40000U)
65864 #define SCT_CTRL_HALT_H_SHIFT                    (18U)
65865 /*! HALT_H - Halt Counter High
65866  *  0b0..Disable
65867  *  0b1..Enable
65868  */
65869 #define SCT_CTRL_HALT_H(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_H_SHIFT)) & SCT_CTRL_HALT_H_MASK)
65870 
65871 #define SCT_CTRL_CLRCTR_H_MASK                   (0x80000U)
65872 #define SCT_CTRL_CLRCTR_H_SHIFT                  (19U)
65873 /*! CLRCTR_H - Clear Counter High */
65874 #define SCT_CTRL_CLRCTR_H(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_H_SHIFT)) & SCT_CTRL_CLRCTR_H_MASK)
65875 
65876 #define SCT_CTRL_BIDIR_H_MASK                    (0x100000U)
65877 #define SCT_CTRL_BIDIR_H_SHIFT                   (20U)
65878 /*! BIDIR_H - Bidirectional Select High
65879  *  0b0..Up
65880  *  0b1..Up-down
65881  */
65882 #define SCT_CTRL_BIDIR_H(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_H_SHIFT)) & SCT_CTRL_BIDIR_H_MASK)
65883 
65884 #define SCT_CTRL_PRE_H_MASK                      (0x1FE00000U)
65885 #define SCT_CTRL_PRE_H_SHIFT                     (21U)
65886 /*! PRE_H - Prescaler for High Counter */
65887 #define SCT_CTRL_PRE_H(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_H_SHIFT)) & SCT_CTRL_PRE_H_MASK)
65888 /*! @} */
65889 
65890 /*! @name LIMITL - SCT_LIMITL register */
65891 /*! @{ */
65892 
65893 #define SCT_LIMITL_LIMITL_MASK                   (0xFFFFU)
65894 #define SCT_LIMITL_LIMITL_SHIFT                  (0U)
65895 #define SCT_LIMITL_LIMITL(x)                     (((uint16_t)(((uint16_t)(x)) << SCT_LIMITL_LIMITL_SHIFT)) & SCT_LIMITL_LIMITL_MASK)
65896 /*! @} */
65897 
65898 /*! @name LIMITH - SCT_LIMITH register */
65899 /*! @{ */
65900 
65901 #define SCT_LIMITH_LIMITH_MASK                   (0xFFFFU)
65902 #define SCT_LIMITH_LIMITH_SHIFT                  (0U)
65903 #define SCT_LIMITH_LIMITH(x)                     (((uint16_t)(((uint16_t)(x)) << SCT_LIMITH_LIMITH_SHIFT)) & SCT_LIMITH_LIMITH_MASK)
65904 /*! @} */
65905 
65906 /*! @name LIMIT - SCT Limit Event Select */
65907 /*! @{ */
65908 
65909 #define SCT_LIMIT_LIMMSK_L_MASK                  (0xFFFFU)
65910 #define SCT_LIMIT_LIMMSK_L_SHIFT                 (0U)
65911 /*! LIMMSK_L - Limit Event Counter Low */
65912 #define SCT_LIMIT_LIMMSK_L(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_L_SHIFT)) & SCT_LIMIT_LIMMSK_L_MASK)
65913 
65914 #define SCT_LIMIT_LIMMSK_H_MASK                  (0xFFFF0000U)
65915 #define SCT_LIMIT_LIMMSK_H_SHIFT                 (16U)
65916 /*! LIMMSK_H - Limit Event Counter High */
65917 #define SCT_LIMIT_LIMMSK_H(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_H_SHIFT)) & SCT_LIMIT_LIMMSK_H_MASK)
65918 /*! @} */
65919 
65920 /*! @name HALTL - SCT_HALTL register */
65921 /*! @{ */
65922 
65923 #define SCT_HALTL_HALTL_MASK                     (0xFFFFU)
65924 #define SCT_HALTL_HALTL_SHIFT                    (0U)
65925 #define SCT_HALTL_HALTL(x)                       (((uint16_t)(((uint16_t)(x)) << SCT_HALTL_HALTL_SHIFT)) & SCT_HALTL_HALTL_MASK)
65926 /*! @} */
65927 
65928 /*! @name HALTH - SCT_HALTH register */
65929 /*! @{ */
65930 
65931 #define SCT_HALTH_HALTH_MASK                     (0xFFFFU)
65932 #define SCT_HALTH_HALTH_SHIFT                    (0U)
65933 #define SCT_HALTH_HALTH(x)                       (((uint16_t)(((uint16_t)(x)) << SCT_HALTH_HALTH_SHIFT)) & SCT_HALTH_HALTH_MASK)
65934 /*! @} */
65935 
65936 /*! @name HALT - Halt Event Select */
65937 /*! @{ */
65938 
65939 #define SCT_HALT_HALTMSK_L_MASK                  (0xFFFFU)
65940 #define SCT_HALT_HALTMSK_L_SHIFT                 (0U)
65941 /*! HALTMSK_L - Halt Event Low */
65942 #define SCT_HALT_HALTMSK_L(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_L_SHIFT)) & SCT_HALT_HALTMSK_L_MASK)
65943 
65944 #define SCT_HALT_HALTMSK_H_MASK                  (0xFFFF0000U)
65945 #define SCT_HALT_HALTMSK_H_SHIFT                 (16U)
65946 /*! HALTMSK_H - Halt Event High */
65947 #define SCT_HALT_HALTMSK_H(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_H_SHIFT)) & SCT_HALT_HALTMSK_H_MASK)
65948 /*! @} */
65949 
65950 /*! @name STOPL - SCT_STOPL register */
65951 /*! @{ */
65952 
65953 #define SCT_STOPL_STOPL_MASK                     (0xFFFFU)
65954 #define SCT_STOPL_STOPL_SHIFT                    (0U)
65955 #define SCT_STOPL_STOPL(x)                       (((uint16_t)(((uint16_t)(x)) << SCT_STOPL_STOPL_SHIFT)) & SCT_STOPL_STOPL_MASK)
65956 /*! @} */
65957 
65958 /*! @name STOPH - SCT_STOPH register */
65959 /*! @{ */
65960 
65961 #define SCT_STOPH_STOPH_MASK                     (0xFFFFU)
65962 #define SCT_STOPH_STOPH_SHIFT                    (0U)
65963 #define SCT_STOPH_STOPH(x)                       (((uint16_t)(((uint16_t)(x)) << SCT_STOPH_STOPH_SHIFT)) & SCT_STOPH_STOPH_MASK)
65964 /*! @} */
65965 
65966 /*! @name STOP - Stop Event Select */
65967 /*! @{ */
65968 
65969 #define SCT_STOP_STOPMSK_L_MASK                  (0xFFFFU)
65970 #define SCT_STOP_STOPMSK_L_SHIFT                 (0U)
65971 /*! STOPMSK_L - Stop Event Low */
65972 #define SCT_STOP_STOPMSK_L(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_L_SHIFT)) & SCT_STOP_STOPMSK_L_MASK)
65973 
65974 #define SCT_STOP_STOPMSK_H_MASK                  (0xFFFF0000U)
65975 #define SCT_STOP_STOPMSK_H_SHIFT                 (16U)
65976 /*! STOPMSK_H - Stop Event High */
65977 #define SCT_STOP_STOPMSK_H(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_H_SHIFT)) & SCT_STOP_STOPMSK_H_MASK)
65978 /*! @} */
65979 
65980 /*! @name STARTL - SCT_STARTL register */
65981 /*! @{ */
65982 
65983 #define SCT_STARTL_STARTL_MASK                   (0xFFFFU)
65984 #define SCT_STARTL_STARTL_SHIFT                  (0U)
65985 #define SCT_STARTL_STARTL(x)                     (((uint16_t)(((uint16_t)(x)) << SCT_STARTL_STARTL_SHIFT)) & SCT_STARTL_STARTL_MASK)
65986 /*! @} */
65987 
65988 /*! @name STARTH - SCT_STARTH register */
65989 /*! @{ */
65990 
65991 #define SCT_STARTH_STARTH_MASK                   (0xFFFFU)
65992 #define SCT_STARTH_STARTH_SHIFT                  (0U)
65993 #define SCT_STARTH_STARTH(x)                     (((uint16_t)(((uint16_t)(x)) << SCT_STARTH_STARTH_SHIFT)) & SCT_STARTH_STARTH_MASK)
65994 /*! @} */
65995 
65996 /*! @name START - Start Event Select */
65997 /*! @{ */
65998 
65999 #define SCT_START_STARTMSK_L_MASK                (0xFFFFU)
66000 #define SCT_START_STARTMSK_L_SHIFT               (0U)
66001 /*! STARTMSK_L - Start Event Low */
66002 #define SCT_START_STARTMSK_L(x)                  (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_L_SHIFT)) & SCT_START_STARTMSK_L_MASK)
66003 
66004 #define SCT_START_STARTMSK_H_MASK                (0xFFFF0000U)
66005 #define SCT_START_STARTMSK_H_SHIFT               (16U)
66006 /*! STARTMSK_H - Start Event High */
66007 #define SCT_START_STARTMSK_H(x)                  (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_H_SHIFT)) & SCT_START_STARTMSK_H_MASK)
66008 /*! @} */
66009 
66010 /*! @name DITHER - Dither Condition */
66011 /*! @{ */
66012 
66013 #define SCT_DITHER_DITHER_L_MASK                 (0xFFFFU)
66014 #define SCT_DITHER_DITHER_L_SHIFT                (0U)
66015 /*! DITHER_L - Dither Low */
66016 #define SCT_DITHER_DITHER_L(x)                   (((uint32_t)(((uint32_t)(x)) << SCT_DITHER_DITHER_L_SHIFT)) & SCT_DITHER_DITHER_L_MASK)
66017 
66018 #define SCT_DITHER_DITHER_H_MASK                 (0xFFFF0000U)
66019 #define SCT_DITHER_DITHER_H_SHIFT                (16U)
66020 /*! DITHER_H - Dither High */
66021 #define SCT_DITHER_DITHER_H(x)                   (((uint32_t)(((uint32_t)(x)) << SCT_DITHER_DITHER_H_SHIFT)) & SCT_DITHER_DITHER_H_MASK)
66022 /*! @} */
66023 
66024 /*! @name COUNTL - SCT_COUNTL register */
66025 /*! @{ */
66026 
66027 #define SCT_COUNTL_COUNTL_MASK                   (0xFFFFU)
66028 #define SCT_COUNTL_COUNTL_SHIFT                  (0U)
66029 #define SCT_COUNTL_COUNTL(x)                     (((uint16_t)(((uint16_t)(x)) << SCT_COUNTL_COUNTL_SHIFT)) & SCT_COUNTL_COUNTL_MASK)
66030 /*! @} */
66031 
66032 /*! @name COUNTH - SCT_COUNTH register */
66033 /*! @{ */
66034 
66035 #define SCT_COUNTH_COUNTH_MASK                   (0xFFFFU)
66036 #define SCT_COUNTH_COUNTH_SHIFT                  (0U)
66037 #define SCT_COUNTH_COUNTH(x)                     (((uint16_t)(((uint16_t)(x)) << SCT_COUNTH_COUNTH_SHIFT)) & SCT_COUNTH_COUNTH_MASK)
66038 /*! @} */
66039 
66040 /*! @name COUNT - Counter Value */
66041 /*! @{ */
66042 
66043 #define SCT_COUNT_CTR_L_MASK                     (0xFFFFU)
66044 #define SCT_COUNT_CTR_L_SHIFT                    (0U)
66045 /*! CTR_L - Counter Low */
66046 #define SCT_COUNT_CTR_L(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_L_SHIFT)) & SCT_COUNT_CTR_L_MASK)
66047 
66048 #define SCT_COUNT_CTR_H_MASK                     (0xFFFF0000U)
66049 #define SCT_COUNT_CTR_H_SHIFT                    (16U)
66050 /*! CTR_H - Counter High */
66051 #define SCT_COUNT_CTR_H(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_H_SHIFT)) & SCT_COUNT_CTR_H_MASK)
66052 /*! @} */
66053 
66054 /*! @name STATEL - SCT_STATEL register */
66055 /*! @{ */
66056 
66057 #define SCT_STATEL_STATEL_MASK                   (0xFFFFU)
66058 #define SCT_STATEL_STATEL_SHIFT                  (0U)
66059 #define SCT_STATEL_STATEL(x)                     (((uint16_t)(((uint16_t)(x)) << SCT_STATEL_STATEL_SHIFT)) & SCT_STATEL_STATEL_MASK)
66060 /*! @} */
66061 
66062 /*! @name STATEH - SCT_STATEH register */
66063 /*! @{ */
66064 
66065 #define SCT_STATEH_STATEH_MASK                   (0xFFFFU)
66066 #define SCT_STATEH_STATEH_SHIFT                  (0U)
66067 #define SCT_STATEH_STATEH(x)                     (((uint16_t)(((uint16_t)(x)) << SCT_STATEH_STATEH_SHIFT)) & SCT_STATEH_STATEH_MASK)
66068 /*! @} */
66069 
66070 /*! @name STATE - State Variable */
66071 /*! @{ */
66072 
66073 #define SCT_STATE_STATE_L_MASK                   (0x1FU)
66074 #define SCT_STATE_STATE_L_SHIFT                  (0U)
66075 /*! STATE_L - State Variable Low */
66076 #define SCT_STATE_STATE_L(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_L_SHIFT)) & SCT_STATE_STATE_L_MASK)
66077 
66078 #define SCT_STATE_STATE_H_MASK                   (0x1F0000U)
66079 #define SCT_STATE_STATE_H_SHIFT                  (16U)
66080 /*! STATE_H - State Variable High */
66081 #define SCT_STATE_STATE_H(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_H_SHIFT)) & SCT_STATE_STATE_H_MASK)
66082 /*! @} */
66083 
66084 /*! @name INPUT - Input State */
66085 /*! @{ */
66086 
66087 #define SCT_INPUT_AIN0_MASK                      (0x1U)
66088 #define SCT_INPUT_AIN0_SHIFT                     (0U)
66089 /*! AIN0 - Input 0 state */
66090 #define SCT_INPUT_AIN0(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN0_SHIFT)) & SCT_INPUT_AIN0_MASK)
66091 
66092 #define SCT_INPUT_AIN1_MASK                      (0x2U)
66093 #define SCT_INPUT_AIN1_SHIFT                     (1U)
66094 /*! AIN1 - Input 1 state */
66095 #define SCT_INPUT_AIN1(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN1_SHIFT)) & SCT_INPUT_AIN1_MASK)
66096 
66097 #define SCT_INPUT_AIN2_MASK                      (0x4U)
66098 #define SCT_INPUT_AIN2_SHIFT                     (2U)
66099 /*! AIN2 - Input 2 state */
66100 #define SCT_INPUT_AIN2(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN2_SHIFT)) & SCT_INPUT_AIN2_MASK)
66101 
66102 #define SCT_INPUT_AIN3_MASK                      (0x8U)
66103 #define SCT_INPUT_AIN3_SHIFT                     (3U)
66104 /*! AIN3 - Input 3 state */
66105 #define SCT_INPUT_AIN3(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN3_SHIFT)) & SCT_INPUT_AIN3_MASK)
66106 
66107 #define SCT_INPUT_AIN4_MASK                      (0x10U)
66108 #define SCT_INPUT_AIN4_SHIFT                     (4U)
66109 /*! AIN4 - Input 4 state */
66110 #define SCT_INPUT_AIN4(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN4_SHIFT)) & SCT_INPUT_AIN4_MASK)
66111 
66112 #define SCT_INPUT_AIN5_MASK                      (0x20U)
66113 #define SCT_INPUT_AIN5_SHIFT                     (5U)
66114 /*! AIN5 - Input 5 state */
66115 #define SCT_INPUT_AIN5(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN5_SHIFT)) & SCT_INPUT_AIN5_MASK)
66116 
66117 #define SCT_INPUT_AIN6_MASK                      (0x40U)
66118 #define SCT_INPUT_AIN6_SHIFT                     (6U)
66119 /*! AIN6 - Input 6 state */
66120 #define SCT_INPUT_AIN6(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN6_SHIFT)) & SCT_INPUT_AIN6_MASK)
66121 
66122 #define SCT_INPUT_AIN7_MASK                      (0x80U)
66123 #define SCT_INPUT_AIN7_SHIFT                     (7U)
66124 /*! AIN7 - Input 7 state */
66125 #define SCT_INPUT_AIN7(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN7_SHIFT)) & SCT_INPUT_AIN7_MASK)
66126 
66127 #define SCT_INPUT_AIN8_MASK                      (0x100U)
66128 #define SCT_INPUT_AIN8_SHIFT                     (8U)
66129 /*! AIN8 - Input 8 state */
66130 #define SCT_INPUT_AIN8(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN8_SHIFT)) & SCT_INPUT_AIN8_MASK)
66131 
66132 #define SCT_INPUT_AIN9_MASK                      (0x200U)
66133 #define SCT_INPUT_AIN9_SHIFT                     (9U)
66134 /*! AIN9 - Input 9 state */
66135 #define SCT_INPUT_AIN9(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN9_SHIFT)) & SCT_INPUT_AIN9_MASK)
66136 
66137 #define SCT_INPUT_AIN10_MASK                     (0x400U)
66138 #define SCT_INPUT_AIN10_SHIFT                    (10U)
66139 /*! AIN10 - Input 10 state */
66140 #define SCT_INPUT_AIN10(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN10_SHIFT)) & SCT_INPUT_AIN10_MASK)
66141 
66142 #define SCT_INPUT_AIN11_MASK                     (0x800U)
66143 #define SCT_INPUT_AIN11_SHIFT                    (11U)
66144 /*! AIN11 - Input 11 state */
66145 #define SCT_INPUT_AIN11(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN11_SHIFT)) & SCT_INPUT_AIN11_MASK)
66146 
66147 #define SCT_INPUT_AIN12_MASK                     (0x1000U)
66148 #define SCT_INPUT_AIN12_SHIFT                    (12U)
66149 /*! AIN12 - Input 12 state */
66150 #define SCT_INPUT_AIN12(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN12_SHIFT)) & SCT_INPUT_AIN12_MASK)
66151 
66152 #define SCT_INPUT_AIN13_MASK                     (0x2000U)
66153 #define SCT_INPUT_AIN13_SHIFT                    (13U)
66154 /*! AIN13 - Input 13 state */
66155 #define SCT_INPUT_AIN13(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN13_SHIFT)) & SCT_INPUT_AIN13_MASK)
66156 
66157 #define SCT_INPUT_AIN14_MASK                     (0x4000U)
66158 #define SCT_INPUT_AIN14_SHIFT                    (14U)
66159 /*! AIN14 - Input 14 state */
66160 #define SCT_INPUT_AIN14(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN14_SHIFT)) & SCT_INPUT_AIN14_MASK)
66161 
66162 #define SCT_INPUT_AIN15_MASK                     (0x8000U)
66163 #define SCT_INPUT_AIN15_SHIFT                    (15U)
66164 /*! AIN15 - Input 15 state */
66165 #define SCT_INPUT_AIN15(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN15_SHIFT)) & SCT_INPUT_AIN15_MASK)
66166 
66167 #define SCT_INPUT_SIN0_MASK                      (0x10000U)
66168 #define SCT_INPUT_SIN0_SHIFT                     (16U)
66169 /*! SIN0 - Input 0 state */
66170 #define SCT_INPUT_SIN0(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN0_SHIFT)) & SCT_INPUT_SIN0_MASK)
66171 
66172 #define SCT_INPUT_SIN1_MASK                      (0x20000U)
66173 #define SCT_INPUT_SIN1_SHIFT                     (17U)
66174 /*! SIN1 - Input 1 state */
66175 #define SCT_INPUT_SIN1(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN1_SHIFT)) & SCT_INPUT_SIN1_MASK)
66176 
66177 #define SCT_INPUT_SIN2_MASK                      (0x40000U)
66178 #define SCT_INPUT_SIN2_SHIFT                     (18U)
66179 /*! SIN2 - Input 2 state */
66180 #define SCT_INPUT_SIN2(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN2_SHIFT)) & SCT_INPUT_SIN2_MASK)
66181 
66182 #define SCT_INPUT_SIN3_MASK                      (0x80000U)
66183 #define SCT_INPUT_SIN3_SHIFT                     (19U)
66184 /*! SIN3 - Input 3 state */
66185 #define SCT_INPUT_SIN3(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN3_SHIFT)) & SCT_INPUT_SIN3_MASK)
66186 
66187 #define SCT_INPUT_SIN4_MASK                      (0x100000U)
66188 #define SCT_INPUT_SIN4_SHIFT                     (20U)
66189 /*! SIN4 - Input 4 state */
66190 #define SCT_INPUT_SIN4(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN4_SHIFT)) & SCT_INPUT_SIN4_MASK)
66191 
66192 #define SCT_INPUT_SIN5_MASK                      (0x200000U)
66193 #define SCT_INPUT_SIN5_SHIFT                     (21U)
66194 /*! SIN5 - Input 5 state */
66195 #define SCT_INPUT_SIN5(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN5_SHIFT)) & SCT_INPUT_SIN5_MASK)
66196 
66197 #define SCT_INPUT_SIN6_MASK                      (0x400000U)
66198 #define SCT_INPUT_SIN6_SHIFT                     (22U)
66199 /*! SIN6 - Input 6 state */
66200 #define SCT_INPUT_SIN6(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN6_SHIFT)) & SCT_INPUT_SIN6_MASK)
66201 
66202 #define SCT_INPUT_SIN7_MASK                      (0x800000U)
66203 #define SCT_INPUT_SIN7_SHIFT                     (23U)
66204 /*! SIN7 - Input 7 state */
66205 #define SCT_INPUT_SIN7(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN7_SHIFT)) & SCT_INPUT_SIN7_MASK)
66206 
66207 #define SCT_INPUT_SIN8_MASK                      (0x1000000U)
66208 #define SCT_INPUT_SIN8_SHIFT                     (24U)
66209 /*! SIN8 - Input 8 state */
66210 #define SCT_INPUT_SIN8(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN8_SHIFT)) & SCT_INPUT_SIN8_MASK)
66211 
66212 #define SCT_INPUT_SIN9_MASK                      (0x2000000U)
66213 #define SCT_INPUT_SIN9_SHIFT                     (25U)
66214 /*! SIN9 - Input 9 state */
66215 #define SCT_INPUT_SIN9(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN9_SHIFT)) & SCT_INPUT_SIN9_MASK)
66216 
66217 #define SCT_INPUT_SIN10_MASK                     (0x4000000U)
66218 #define SCT_INPUT_SIN10_SHIFT                    (26U)
66219 /*! SIN10 - Input 10 state */
66220 #define SCT_INPUT_SIN10(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN10_SHIFT)) & SCT_INPUT_SIN10_MASK)
66221 
66222 #define SCT_INPUT_SIN11_MASK                     (0x8000000U)
66223 #define SCT_INPUT_SIN11_SHIFT                    (27U)
66224 /*! SIN11 - Input 11 state */
66225 #define SCT_INPUT_SIN11(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN11_SHIFT)) & SCT_INPUT_SIN11_MASK)
66226 
66227 #define SCT_INPUT_SIN12_MASK                     (0x10000000U)
66228 #define SCT_INPUT_SIN12_SHIFT                    (28U)
66229 /*! SIN12 - Input 12 state */
66230 #define SCT_INPUT_SIN12(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN12_SHIFT)) & SCT_INPUT_SIN12_MASK)
66231 
66232 #define SCT_INPUT_SIN13_MASK                     (0x20000000U)
66233 #define SCT_INPUT_SIN13_SHIFT                    (29U)
66234 /*! SIN13 - Input 13 state */
66235 #define SCT_INPUT_SIN13(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN13_SHIFT)) & SCT_INPUT_SIN13_MASK)
66236 
66237 #define SCT_INPUT_SIN14_MASK                     (0x40000000U)
66238 #define SCT_INPUT_SIN14_SHIFT                    (30U)
66239 /*! SIN14 - Input 14 state */
66240 #define SCT_INPUT_SIN14(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN14_SHIFT)) & SCT_INPUT_SIN14_MASK)
66241 
66242 #define SCT_INPUT_SIN15_MASK                     (0x80000000U)
66243 #define SCT_INPUT_SIN15_SHIFT                    (31U)
66244 /*! SIN15 - Input 15 state */
66245 #define SCT_INPUT_SIN15(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN15_SHIFT)) & SCT_INPUT_SIN15_MASK)
66246 /*! @} */
66247 
66248 /*! @name REGMODEL - SCT_REGMODEL register */
66249 /*! @{ */
66250 
66251 #define SCT_REGMODEL_REGMODEL_MASK               (0xFFFFU)
66252 #define SCT_REGMODEL_REGMODEL_SHIFT              (0U)
66253 /*! REGMODEL
66254  *  0b0..Match
66255  *  0b1..Capture
66256  */
66257 #define SCT_REGMODEL_REGMODEL(x)                 (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEL_REGMODEL_SHIFT)) & SCT_REGMODEL_REGMODEL_MASK)
66258 
66259 #define SCT_REGMODEL_REGMOD_L_MASK               (0xFFFFU)
66260 #define SCT_REGMODEL_REGMOD_L_SHIFT              (0U)
66261 #define SCT_REGMODEL_REGMOD_L(x)                 (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEL_REGMOD_L_SHIFT)) & SCT_REGMODEL_REGMOD_L_MASK)
66262 
66263 #define SCT_REGMODEL_REGMOD_H_MASK               (0xFFFF0000U)
66264 #define SCT_REGMODEL_REGMOD_H_SHIFT              (16U)
66265 #define SCT_REGMODEL_REGMOD_H(x)                 (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEL_REGMOD_H_SHIFT)) & SCT_REGMODEL_REGMOD_H_MASK)
66266 /*! @} */
66267 
66268 /*! @name REGMODEH - SCT_REGMODEH register */
66269 /*! @{ */
66270 
66271 #define SCT_REGMODEH_REGMODEH_MASK               (0xFFFFU)
66272 #define SCT_REGMODEH_REGMODEH_SHIFT              (0U)
66273 /*! REGMODEH
66274  *  0b0..Match
66275  *  0b1..Capture
66276  */
66277 #define SCT_REGMODEH_REGMODEH(x)                 (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEH_REGMODEH_SHIFT)) & SCT_REGMODEH_REGMODEH_MASK)
66278 
66279 #define SCT_REGMODEH_REGMOD_L_MASK               (0xFFFFU)
66280 #define SCT_REGMODEH_REGMOD_L_SHIFT              (0U)
66281 #define SCT_REGMODEH_REGMOD_L(x)                 (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEH_REGMOD_L_SHIFT)) & SCT_REGMODEH_REGMOD_L_MASK)
66282 
66283 #define SCT_REGMODEH_REGMOD_H_MASK               (0xFFFF0000U)
66284 #define SCT_REGMODEH_REGMOD_H_SHIFT              (16U)
66285 #define SCT_REGMODEH_REGMOD_H(x)                 (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEH_REGMOD_H_SHIFT)) & SCT_REGMODEH_REGMOD_H_MASK)
66286 /*! @} */
66287 
66288 /*! @name REGMODE - Match and Capture Register Mode */
66289 /*! @{ */
66290 
66291 #define SCT_REGMODE_REGMOD_L_MASK                (0xFFFFU)
66292 #define SCT_REGMODE_REGMOD_L_SHIFT               (0U)
66293 #define SCT_REGMODE_REGMOD_L(x)                  (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L_SHIFT)) & SCT_REGMODE_REGMOD_L_MASK)
66294 
66295 #define SCT_REGMODE_REGMOD_L0_MASK               (0x1U)
66296 #define SCT_REGMODE_REGMOD_L0_SHIFT              (0U)
66297 /*! REGMOD_L0 - Register Mode Low
66298  *  0b0..Match
66299  *  0b1..Capture
66300  */
66301 #define SCT_REGMODE_REGMOD_L0(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L0_SHIFT)) & SCT_REGMODE_REGMOD_L0_MASK)
66302 
66303 #define SCT_REGMODE_REGMOD_L1_MASK               (0x2U)
66304 #define SCT_REGMODE_REGMOD_L1_SHIFT              (1U)
66305 /*! REGMOD_L1 - Register Mode Low
66306  *  0b0..Match
66307  *  0b1..Capture
66308  */
66309 #define SCT_REGMODE_REGMOD_L1(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L1_SHIFT)) & SCT_REGMODE_REGMOD_L1_MASK)
66310 
66311 #define SCT_REGMODE_REGMOD_L2_MASK               (0x4U)
66312 #define SCT_REGMODE_REGMOD_L2_SHIFT              (2U)
66313 /*! REGMOD_L2 - Register Mode Low
66314  *  0b0..Match
66315  *  0b1..Capture
66316  */
66317 #define SCT_REGMODE_REGMOD_L2(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L2_SHIFT)) & SCT_REGMODE_REGMOD_L2_MASK)
66318 
66319 #define SCT_REGMODE_REGMOD_L3_MASK               (0x8U)
66320 #define SCT_REGMODE_REGMOD_L3_SHIFT              (3U)
66321 /*! REGMOD_L3 - Register Mode Low
66322  *  0b0..Match
66323  *  0b1..Capture
66324  */
66325 #define SCT_REGMODE_REGMOD_L3(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L3_SHIFT)) & SCT_REGMODE_REGMOD_L3_MASK)
66326 
66327 #define SCT_REGMODE_REGMOD_L4_MASK               (0x10U)
66328 #define SCT_REGMODE_REGMOD_L4_SHIFT              (4U)
66329 /*! REGMOD_L4 - Register Mode Low
66330  *  0b0..Match
66331  *  0b1..Capture
66332  */
66333 #define SCT_REGMODE_REGMOD_L4(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L4_SHIFT)) & SCT_REGMODE_REGMOD_L4_MASK)
66334 
66335 #define SCT_REGMODE_REGMOD_L5_MASK               (0x20U)
66336 #define SCT_REGMODE_REGMOD_L5_SHIFT              (5U)
66337 /*! REGMOD_L5 - Register Mode Low
66338  *  0b0..Match
66339  *  0b1..Capture
66340  */
66341 #define SCT_REGMODE_REGMOD_L5(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L5_SHIFT)) & SCT_REGMODE_REGMOD_L5_MASK)
66342 
66343 #define SCT_REGMODE_REGMOD_L6_MASK               (0x40U)
66344 #define SCT_REGMODE_REGMOD_L6_SHIFT              (6U)
66345 /*! REGMOD_L6 - Register Mode Low
66346  *  0b0..Match
66347  *  0b1..Capture
66348  */
66349 #define SCT_REGMODE_REGMOD_L6(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L6_SHIFT)) & SCT_REGMODE_REGMOD_L6_MASK)
66350 
66351 #define SCT_REGMODE_REGMOD_L7_MASK               (0x80U)
66352 #define SCT_REGMODE_REGMOD_L7_SHIFT              (7U)
66353 /*! REGMOD_L7 - Register Mode Low
66354  *  0b0..Match
66355  *  0b1..Capture
66356  */
66357 #define SCT_REGMODE_REGMOD_L7(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L7_SHIFT)) & SCT_REGMODE_REGMOD_L7_MASK)
66358 
66359 #define SCT_REGMODE_REGMOD_L8_MASK               (0x100U)
66360 #define SCT_REGMODE_REGMOD_L8_SHIFT              (8U)
66361 /*! REGMOD_L8 - Register Mode Low
66362  *  0b0..Match
66363  *  0b1..Capture
66364  */
66365 #define SCT_REGMODE_REGMOD_L8(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L8_SHIFT)) & SCT_REGMODE_REGMOD_L8_MASK)
66366 
66367 #define SCT_REGMODE_REGMOD_L9_MASK               (0x200U)
66368 #define SCT_REGMODE_REGMOD_L9_SHIFT              (9U)
66369 /*! REGMOD_L9 - Register Mode Low
66370  *  0b0..Match
66371  *  0b1..Capture
66372  */
66373 #define SCT_REGMODE_REGMOD_L9(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L9_SHIFT)) & SCT_REGMODE_REGMOD_L9_MASK)
66374 
66375 #define SCT_REGMODE_REGMOD_L10_MASK              (0x400U)
66376 #define SCT_REGMODE_REGMOD_L10_SHIFT             (10U)
66377 /*! REGMOD_L10 - Register Mode Low
66378  *  0b0..Match
66379  *  0b1..Capture
66380  */
66381 #define SCT_REGMODE_REGMOD_L10(x)                (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L10_SHIFT)) & SCT_REGMODE_REGMOD_L10_MASK)
66382 
66383 #define SCT_REGMODE_REGMOD_L11_MASK              (0x800U)
66384 #define SCT_REGMODE_REGMOD_L11_SHIFT             (11U)
66385 /*! REGMOD_L11 - Register Mode Low
66386  *  0b0..Match
66387  *  0b1..Capture
66388  */
66389 #define SCT_REGMODE_REGMOD_L11(x)                (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L11_SHIFT)) & SCT_REGMODE_REGMOD_L11_MASK)
66390 
66391 #define SCT_REGMODE_REGMOD_L12_MASK              (0x1000U)
66392 #define SCT_REGMODE_REGMOD_L12_SHIFT             (12U)
66393 /*! REGMOD_L12 - Register Mode Low
66394  *  0b0..Match
66395  *  0b1..Capture
66396  */
66397 #define SCT_REGMODE_REGMOD_L12(x)                (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L12_SHIFT)) & SCT_REGMODE_REGMOD_L12_MASK)
66398 
66399 #define SCT_REGMODE_REGMOD_L13_MASK              (0x2000U)
66400 #define SCT_REGMODE_REGMOD_L13_SHIFT             (13U)
66401 /*! REGMOD_L13 - Register Mode Low
66402  *  0b0..Match
66403  *  0b1..Capture
66404  */
66405 #define SCT_REGMODE_REGMOD_L13(x)                (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L13_SHIFT)) & SCT_REGMODE_REGMOD_L13_MASK)
66406 
66407 #define SCT_REGMODE_REGMOD_L14_MASK              (0x4000U)
66408 #define SCT_REGMODE_REGMOD_L14_SHIFT             (14U)
66409 /*! REGMOD_L14 - Register Mode Low
66410  *  0b0..Match
66411  *  0b1..Capture
66412  */
66413 #define SCT_REGMODE_REGMOD_L14(x)                (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L14_SHIFT)) & SCT_REGMODE_REGMOD_L14_MASK)
66414 
66415 #define SCT_REGMODE_REGMOD_L15_MASK              (0x8000U)
66416 #define SCT_REGMODE_REGMOD_L15_SHIFT             (15U)
66417 /*! REGMOD_L15 - Register Mode Low
66418  *  0b0..Match
66419  *  0b1..Capture
66420  */
66421 #define SCT_REGMODE_REGMOD_L15(x)                (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L15_SHIFT)) & SCT_REGMODE_REGMOD_L15_MASK)
66422 
66423 #define SCT_REGMODE_REGMOD_H_MASK                (0xFFFF0000U)
66424 #define SCT_REGMODE_REGMOD_H_SHIFT               (16U)
66425 #define SCT_REGMODE_REGMOD_H(x)                  (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H_SHIFT)) & SCT_REGMODE_REGMOD_H_MASK)
66426 
66427 #define SCT_REGMODE_REGMOD_H0_MASK               (0x10000U)
66428 #define SCT_REGMODE_REGMOD_H0_SHIFT              (16U)
66429 /*! REGMOD_H0 - Register Mode High
66430  *  0b0..Match
66431  *  0b1..Capture
66432  */
66433 #define SCT_REGMODE_REGMOD_H0(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H0_SHIFT)) & SCT_REGMODE_REGMOD_H0_MASK)
66434 
66435 #define SCT_REGMODE_REGMOD_H1_MASK               (0x20000U)
66436 #define SCT_REGMODE_REGMOD_H1_SHIFT              (17U)
66437 /*! REGMOD_H1 - Register Mode High
66438  *  0b0..Match
66439  *  0b1..Capture
66440  */
66441 #define SCT_REGMODE_REGMOD_H1(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H1_SHIFT)) & SCT_REGMODE_REGMOD_H1_MASK)
66442 
66443 #define SCT_REGMODE_REGMOD_H2_MASK               (0x40000U)
66444 #define SCT_REGMODE_REGMOD_H2_SHIFT              (18U)
66445 /*! REGMOD_H2 - Register Mode High
66446  *  0b0..Match
66447  *  0b1..Capture
66448  */
66449 #define SCT_REGMODE_REGMOD_H2(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H2_SHIFT)) & SCT_REGMODE_REGMOD_H2_MASK)
66450 
66451 #define SCT_REGMODE_REGMOD_H3_MASK               (0x80000U)
66452 #define SCT_REGMODE_REGMOD_H3_SHIFT              (19U)
66453 /*! REGMOD_H3 - Register Mode High
66454  *  0b0..Match
66455  *  0b1..Capture
66456  */
66457 #define SCT_REGMODE_REGMOD_H3(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H3_SHIFT)) & SCT_REGMODE_REGMOD_H3_MASK)
66458 
66459 #define SCT_REGMODE_REGMOD_H4_MASK               (0x100000U)
66460 #define SCT_REGMODE_REGMOD_H4_SHIFT              (20U)
66461 /*! REGMOD_H4 - Register Mode High
66462  *  0b0..Match
66463  *  0b1..Capture
66464  */
66465 #define SCT_REGMODE_REGMOD_H4(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H4_SHIFT)) & SCT_REGMODE_REGMOD_H4_MASK)
66466 
66467 #define SCT_REGMODE_REGMOD_H5_MASK               (0x200000U)
66468 #define SCT_REGMODE_REGMOD_H5_SHIFT              (21U)
66469 /*! REGMOD_H5 - Register Mode High
66470  *  0b0..Match
66471  *  0b1..Capture
66472  */
66473 #define SCT_REGMODE_REGMOD_H5(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H5_SHIFT)) & SCT_REGMODE_REGMOD_H5_MASK)
66474 
66475 #define SCT_REGMODE_REGMOD_H6_MASK               (0x400000U)
66476 #define SCT_REGMODE_REGMOD_H6_SHIFT              (22U)
66477 /*! REGMOD_H6 - Register Mode High
66478  *  0b0..Match
66479  *  0b1..Capture
66480  */
66481 #define SCT_REGMODE_REGMOD_H6(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H6_SHIFT)) & SCT_REGMODE_REGMOD_H6_MASK)
66482 
66483 #define SCT_REGMODE_REGMOD_H7_MASK               (0x800000U)
66484 #define SCT_REGMODE_REGMOD_H7_SHIFT              (23U)
66485 /*! REGMOD_H7 - Register Mode High
66486  *  0b0..Match
66487  *  0b1..Capture
66488  */
66489 #define SCT_REGMODE_REGMOD_H7(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H7_SHIFT)) & SCT_REGMODE_REGMOD_H7_MASK)
66490 
66491 #define SCT_REGMODE_REGMOD_H8_MASK               (0x1000000U)
66492 #define SCT_REGMODE_REGMOD_H8_SHIFT              (24U)
66493 /*! REGMOD_H8 - Register Mode High
66494  *  0b0..Match
66495  *  0b1..Capture
66496  */
66497 #define SCT_REGMODE_REGMOD_H8(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H8_SHIFT)) & SCT_REGMODE_REGMOD_H8_MASK)
66498 
66499 #define SCT_REGMODE_REGMOD_H9_MASK               (0x2000000U)
66500 #define SCT_REGMODE_REGMOD_H9_SHIFT              (25U)
66501 /*! REGMOD_H9 - Register Mode High
66502  *  0b0..Match
66503  *  0b1..Capture
66504  */
66505 #define SCT_REGMODE_REGMOD_H9(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H9_SHIFT)) & SCT_REGMODE_REGMOD_H9_MASK)
66506 
66507 #define SCT_REGMODE_REGMOD_H10_MASK              (0x4000000U)
66508 #define SCT_REGMODE_REGMOD_H10_SHIFT             (26U)
66509 /*! REGMOD_H10 - Register Mode High
66510  *  0b0..Match
66511  *  0b1..Capture
66512  */
66513 #define SCT_REGMODE_REGMOD_H10(x)                (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H10_SHIFT)) & SCT_REGMODE_REGMOD_H10_MASK)
66514 
66515 #define SCT_REGMODE_REGMOD_H11_MASK              (0x8000000U)
66516 #define SCT_REGMODE_REGMOD_H11_SHIFT             (27U)
66517 /*! REGMOD_H11 - Register Mode High
66518  *  0b0..Match
66519  *  0b1..Capture
66520  */
66521 #define SCT_REGMODE_REGMOD_H11(x)                (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H11_SHIFT)) & SCT_REGMODE_REGMOD_H11_MASK)
66522 
66523 #define SCT_REGMODE_REGMOD_H12_MASK              (0x10000000U)
66524 #define SCT_REGMODE_REGMOD_H12_SHIFT             (28U)
66525 /*! REGMOD_H12 - Register Mode High
66526  *  0b0..Match
66527  *  0b1..Capture
66528  */
66529 #define SCT_REGMODE_REGMOD_H12(x)                (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H12_SHIFT)) & SCT_REGMODE_REGMOD_H12_MASK)
66530 
66531 #define SCT_REGMODE_REGMOD_H13_MASK              (0x20000000U)
66532 #define SCT_REGMODE_REGMOD_H13_SHIFT             (29U)
66533 /*! REGMOD_H13 - Register Mode High
66534  *  0b0..Match
66535  *  0b1..Capture
66536  */
66537 #define SCT_REGMODE_REGMOD_H13(x)                (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H13_SHIFT)) & SCT_REGMODE_REGMOD_H13_MASK)
66538 
66539 #define SCT_REGMODE_REGMOD_H14_MASK              (0x40000000U)
66540 #define SCT_REGMODE_REGMOD_H14_SHIFT             (30U)
66541 /*! REGMOD_H14 - Register Mode High
66542  *  0b0..Match
66543  *  0b1..Capture
66544  */
66545 #define SCT_REGMODE_REGMOD_H14(x)                (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H14_SHIFT)) & SCT_REGMODE_REGMOD_H14_MASK)
66546 
66547 #define SCT_REGMODE_REGMOD_H15_MASK              (0x80000000U)
66548 #define SCT_REGMODE_REGMOD_H15_SHIFT             (31U)
66549 /*! REGMOD_H15 - Register Mode High
66550  *  0b0..Match
66551  *  0b1..Capture
66552  */
66553 #define SCT_REGMODE_REGMOD_H15(x)                (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H15_SHIFT)) & SCT_REGMODE_REGMOD_H15_MASK)
66554 /*! @} */
66555 
66556 /*! @name OUTPUT - Output State */
66557 /*! @{ */
66558 
66559 #define SCT_OUTPUT_OUT0_MASK                     (0x1U)
66560 #define SCT_OUTPUT_OUT0_SHIFT                    (0U)
66561 /*! OUT0 - Output Low and High
66562  *  0b0..Forces the corresponding output low
66563  *  0b1..Forces the corresponding output high
66564  */
66565 #define SCT_OUTPUT_OUT0(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT0_SHIFT)) & SCT_OUTPUT_OUT0_MASK)
66566 
66567 #define SCT_OUTPUT_OUT1_MASK                     (0x2U)
66568 #define SCT_OUTPUT_OUT1_SHIFT                    (1U)
66569 /*! OUT1 - Output Low and High
66570  *  0b0..Forces the corresponding output low
66571  *  0b1..Forces the corresponding output high
66572  */
66573 #define SCT_OUTPUT_OUT1(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT1_SHIFT)) & SCT_OUTPUT_OUT1_MASK)
66574 
66575 #define SCT_OUTPUT_OUT2_MASK                     (0x4U)
66576 #define SCT_OUTPUT_OUT2_SHIFT                    (2U)
66577 /*! OUT2 - Output Low and High
66578  *  0b0..Forces the corresponding output low
66579  *  0b1..Forces the corresponding output high
66580  */
66581 #define SCT_OUTPUT_OUT2(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT2_SHIFT)) & SCT_OUTPUT_OUT2_MASK)
66582 
66583 #define SCT_OUTPUT_OUT3_MASK                     (0x8U)
66584 #define SCT_OUTPUT_OUT3_SHIFT                    (3U)
66585 /*! OUT3 - Output Low and High
66586  *  0b0..Forces the corresponding output low
66587  *  0b1..Forces the corresponding output high
66588  */
66589 #define SCT_OUTPUT_OUT3(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT3_SHIFT)) & SCT_OUTPUT_OUT3_MASK)
66590 
66591 #define SCT_OUTPUT_OUT4_MASK                     (0x10U)
66592 #define SCT_OUTPUT_OUT4_SHIFT                    (4U)
66593 /*! OUT4 - Output Low and High
66594  *  0b0..Forces the corresponding output low
66595  *  0b1..Forces the corresponding output high
66596  */
66597 #define SCT_OUTPUT_OUT4(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT4_SHIFT)) & SCT_OUTPUT_OUT4_MASK)
66598 
66599 #define SCT_OUTPUT_OUT5_MASK                     (0x20U)
66600 #define SCT_OUTPUT_OUT5_SHIFT                    (5U)
66601 /*! OUT5 - Output Low and High
66602  *  0b0..Forces the corresponding output low
66603  *  0b1..Forces the corresponding output high
66604  */
66605 #define SCT_OUTPUT_OUT5(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT5_SHIFT)) & SCT_OUTPUT_OUT5_MASK)
66606 
66607 #define SCT_OUTPUT_OUT6_MASK                     (0x40U)
66608 #define SCT_OUTPUT_OUT6_SHIFT                    (6U)
66609 /*! OUT6 - Output Low and High
66610  *  0b0..Forces the corresponding output low
66611  *  0b1..Forces the corresponding output high
66612  */
66613 #define SCT_OUTPUT_OUT6(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT6_SHIFT)) & SCT_OUTPUT_OUT6_MASK)
66614 
66615 #define SCT_OUTPUT_OUT7_MASK                     (0x80U)
66616 #define SCT_OUTPUT_OUT7_SHIFT                    (7U)
66617 /*! OUT7 - Output Low and High
66618  *  0b0..Forces the corresponding output low
66619  *  0b1..Forces the corresponding output high
66620  */
66621 #define SCT_OUTPUT_OUT7(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT7_SHIFT)) & SCT_OUTPUT_OUT7_MASK)
66622 
66623 #define SCT_OUTPUT_OUT8_MASK                     (0x100U)
66624 #define SCT_OUTPUT_OUT8_SHIFT                    (8U)
66625 /*! OUT8 - Output Low and High
66626  *  0b0..Forces the corresponding output low
66627  *  0b1..Forces the corresponding output high
66628  */
66629 #define SCT_OUTPUT_OUT8(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT8_SHIFT)) & SCT_OUTPUT_OUT8_MASK)
66630 
66631 #define SCT_OUTPUT_OUT9_MASK                     (0x200U)
66632 #define SCT_OUTPUT_OUT9_SHIFT                    (9U)
66633 /*! OUT9 - Output Low and High
66634  *  0b0..Forces the corresponding output low
66635  *  0b1..Forces the corresponding output high
66636  */
66637 #define SCT_OUTPUT_OUT9(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT9_SHIFT)) & SCT_OUTPUT_OUT9_MASK)
66638 /*! @} */
66639 
66640 /*! @name OUTPUTDIRCTRL - Output Counter Direction Control */
66641 /*! @{ */
66642 
66643 #define SCT_OUTPUTDIRCTRL_SETCLR0_MASK           (0x3U)
66644 #define SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT          (0U)
66645 /*! SETCLR0 - Set and Clear Operation on Output
66646  *  0b00..Not dependent on the direction of any counter
66647  *  0b01..Reversed when counter L or the unified counter is counting down
66648  *  0b10..Reversed when counter H is counting down (do not use this value when CONFIG[UNIFY] = 1)
66649  *  0b11..Reserved (do not program this value)
66650  */
66651 #define SCT_OUTPUTDIRCTRL_SETCLR0(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR0_MASK)
66652 
66653 #define SCT_OUTPUTDIRCTRL_SETCLR1_MASK           (0xCU)
66654 #define SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT          (2U)
66655 /*! SETCLR1 - Set and Clear Operation on Output
66656  *  0b00..Not dependent on the direction of any counter
66657  *  0b01..Reversed when counter L or the unified counter is counting down
66658  *  0b10..Reversed when counter H is counting down (do not use this value when CONFIG[UNIFY] = 1)
66659  *  0b11..Reserved (do not program this value)
66660  */
66661 #define SCT_OUTPUTDIRCTRL_SETCLR1(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR1_MASK)
66662 
66663 #define SCT_OUTPUTDIRCTRL_SETCLR2_MASK           (0x30U)
66664 #define SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT          (4U)
66665 /*! SETCLR2 - Set and Clear Operation on Output
66666  *  0b00..Not dependent on the direction of any counter
66667  *  0b01..Reversed when counter L or the unified counter is counting down
66668  *  0b10..Reversed when counter H is counting down (do not use this value when CONFIG[UNIFY] = 1)
66669  *  0b11..Reserved (do not program this value)
66670  */
66671 #define SCT_OUTPUTDIRCTRL_SETCLR2(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR2_MASK)
66672 
66673 #define SCT_OUTPUTDIRCTRL_SETCLR3_MASK           (0xC0U)
66674 #define SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT          (6U)
66675 /*! SETCLR3 - Set and Clear Operation on Output
66676  *  0b00..Not dependent on the direction of any counter
66677  *  0b01..Reversed when counter L or the unified counter is counting down
66678  *  0b10..Reversed when counter H is counting down (do not use this value when CONFIG[UNIFY] = 1)
66679  *  0b11..Reserved (do not program this value)
66680  */
66681 #define SCT_OUTPUTDIRCTRL_SETCLR3(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR3_MASK)
66682 
66683 #define SCT_OUTPUTDIRCTRL_SETCLR4_MASK           (0x300U)
66684 #define SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT          (8U)
66685 /*! SETCLR4 - Set and Clear Operation on Output
66686  *  0b00..Not dependent on the direction of any counter
66687  *  0b01..Reversed when counter L or the unified counter is counting down
66688  *  0b10..Reversed when counter H is counting down (do not use this value when CONFIG[UNIFY] = 1)
66689  *  0b11..Reserved (do not program this value)
66690  */
66691 #define SCT_OUTPUTDIRCTRL_SETCLR4(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR4_MASK)
66692 
66693 #define SCT_OUTPUTDIRCTRL_SETCLR5_MASK           (0xC00U)
66694 #define SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT          (10U)
66695 /*! SETCLR5 - Set and Clear Operation on Output
66696  *  0b00..Not dependent on the direction of any counter
66697  *  0b01..Reversed when counter L or the unified counter is counting down
66698  *  0b10..Reversed when counter H is counting down (do not use this value when CONFIG[UNIFY] = 1)
66699  *  0b11..Reserved (do not program this value)
66700  */
66701 #define SCT_OUTPUTDIRCTRL_SETCLR5(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR5_MASK)
66702 
66703 #define SCT_OUTPUTDIRCTRL_SETCLR6_MASK           (0x3000U)
66704 #define SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT          (12U)
66705 /*! SETCLR6 - Set and Clear Operation on Output
66706  *  0b00..Not dependent on the direction of any counter
66707  *  0b01..Reversed when counter L or the unified counter is counting down
66708  *  0b10..Reversed when counter H is counting down (do not use this value when CONFIG[UNIFY] = 1)
66709  *  0b11..Reserved (do not program this value)
66710  */
66711 #define SCT_OUTPUTDIRCTRL_SETCLR6(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR6_MASK)
66712 
66713 #define SCT_OUTPUTDIRCTRL_SETCLR7_MASK           (0xC000U)
66714 #define SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT          (14U)
66715 /*! SETCLR7 - Set and Clear Operation on Output
66716  *  0b00..Not dependent on the direction of any counter
66717  *  0b01..Reversed when counter L or the unified counter is counting down
66718  *  0b10..Reversed when counter H is counting down (do not use this value when CONFIG[UNIFY] = 1)
66719  *  0b11..Reserved (do not program this value)
66720  */
66721 #define SCT_OUTPUTDIRCTRL_SETCLR7(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR7_MASK)
66722 
66723 #define SCT_OUTPUTDIRCTRL_SETCLR8_MASK           (0x30000U)
66724 #define SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT          (16U)
66725 /*! SETCLR8 - Set and Clear Operation on Output
66726  *  0b00..Not dependent on the direction of any counter
66727  *  0b01..Reversed when counter L or the unified counter is counting down
66728  *  0b10..Reversed when counter H is counting down (do not use this value when CONFIG[UNIFY] = 1)
66729  *  0b11..Reserved (do not program this value)
66730  */
66731 #define SCT_OUTPUTDIRCTRL_SETCLR8(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR8_MASK)
66732 
66733 #define SCT_OUTPUTDIRCTRL_SETCLR9_MASK           (0xC0000U)
66734 #define SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT          (18U)
66735 /*! SETCLR9 - Set and Clear Operation on Output
66736  *  0b00..Not dependent on the direction of any counter
66737  *  0b01..Reversed when counter L or the unified counter is counting down
66738  *  0b10..Reversed when counter H is counting down (do not use this value when CONFIG[UNIFY] = 1)
66739  *  0b11..Reserved (do not program this value)
66740  */
66741 #define SCT_OUTPUTDIRCTRL_SETCLR9(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR9_MASK)
66742 /*! @} */
66743 
66744 /*! @name RES - Output Conflict Resolution */
66745 /*! @{ */
66746 
66747 #define SCT_RES_O0RES_MASK                       (0x3U)
66748 #define SCT_RES_O0RES_SHIFT                      (0U)
66749 /*! O0RES - Output Resolution
66750  *  0b00..No change
66751  *  0b01..Set output (or clear, based on OUTPUTDIRCTRL[SETCLRn])
66752  *  0b10..Clear output (or set, based on OUTPUTDIRCTRL[SETCLRn])
66753  *  0b11..Toggle output
66754  */
66755 #define SCT_RES_O0RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O0RES_SHIFT)) & SCT_RES_O0RES_MASK)
66756 
66757 #define SCT_RES_O1RES_MASK                       (0xCU)
66758 #define SCT_RES_O1RES_SHIFT                      (2U)
66759 /*! O1RES - Output Resolution
66760  *  0b00..No change
66761  *  0b01..Set output (or clear, based on OUTPUTDIRCTRL[SETCLRn])
66762  *  0b10..Clear output (or set, based on OUTPUTDIRCTRL[SETCLRn])
66763  *  0b11..Toggle output
66764  */
66765 #define SCT_RES_O1RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O1RES_SHIFT)) & SCT_RES_O1RES_MASK)
66766 
66767 #define SCT_RES_O2RES_MASK                       (0x30U)
66768 #define SCT_RES_O2RES_SHIFT                      (4U)
66769 /*! O2RES - Output Resolution
66770  *  0b00..No change
66771  *  0b01..Set output (or clear, based on OUTPUTDIRCTRL[SETCLRn])
66772  *  0b10..Clear output (or set, based on OUTPUTDIRCTRL[SETCLRn])
66773  *  0b11..Toggle output
66774  */
66775 #define SCT_RES_O2RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O2RES_SHIFT)) & SCT_RES_O2RES_MASK)
66776 
66777 #define SCT_RES_O3RES_MASK                       (0xC0U)
66778 #define SCT_RES_O3RES_SHIFT                      (6U)
66779 /*! O3RES - Output Resolution
66780  *  0b00..No change
66781  *  0b01..Set output (or clear, based on OUTPUTDIRCTRL[SETCLRn])
66782  *  0b10..Clear output (or set, based on OUTPUTDIRCTRL[SETCLRn])
66783  *  0b11..Toggle output
66784  */
66785 #define SCT_RES_O3RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O3RES_SHIFT)) & SCT_RES_O3RES_MASK)
66786 
66787 #define SCT_RES_O4RES_MASK                       (0x300U)
66788 #define SCT_RES_O4RES_SHIFT                      (8U)
66789 /*! O4RES - Output Resolution
66790  *  0b00..No change
66791  *  0b01..Set output (or clear, based on OUTPUTDIRCTRL[SETCLRn])
66792  *  0b10..Clear output (or set, based on OUTPUTDIRCTRL[SETCLRn])
66793  *  0b11..Toggle output
66794  */
66795 #define SCT_RES_O4RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O4RES_SHIFT)) & SCT_RES_O4RES_MASK)
66796 
66797 #define SCT_RES_O5RES_MASK                       (0xC00U)
66798 #define SCT_RES_O5RES_SHIFT                      (10U)
66799 /*! O5RES - Output Resolution
66800  *  0b00..No change
66801  *  0b01..Set output (or clear, based on OUTPUTDIRCTRL[SETCLRn])
66802  *  0b10..Clear output (or set, based on OUTPUTDIRCTRL[SETCLRn])
66803  *  0b11..Toggle output
66804  */
66805 #define SCT_RES_O5RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O5RES_SHIFT)) & SCT_RES_O5RES_MASK)
66806 
66807 #define SCT_RES_O6RES_MASK                       (0x3000U)
66808 #define SCT_RES_O6RES_SHIFT                      (12U)
66809 /*! O6RES - Output Resolution
66810  *  0b00..No change
66811  *  0b01..Set output (or clear, based on OUTPUTDIRCTRL[SETCLRn])
66812  *  0b10..Clear output (or set, based on OUTPUTDIRCTRL[SETCLRn])
66813  *  0b11..Toggle output
66814  */
66815 #define SCT_RES_O6RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O6RES_SHIFT)) & SCT_RES_O6RES_MASK)
66816 
66817 #define SCT_RES_O7RES_MASK                       (0xC000U)
66818 #define SCT_RES_O7RES_SHIFT                      (14U)
66819 /*! O7RES - Output Resolution
66820  *  0b00..No change
66821  *  0b01..Set output (or clear, based on OUTPUTDIRCTRL[SETCLRn])
66822  *  0b10..Clear output (or set, based on OUTPUTDIRCTRL[SETCLRn])
66823  *  0b11..Toggle output
66824  */
66825 #define SCT_RES_O7RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O7RES_SHIFT)) & SCT_RES_O7RES_MASK)
66826 
66827 #define SCT_RES_O8RES_MASK                       (0x30000U)
66828 #define SCT_RES_O8RES_SHIFT                      (16U)
66829 /*! O8RES - Output Resolution
66830  *  0b00..No change
66831  *  0b01..Set output (or clear, based on OUTPUTDIRCTRL[SETCLRn])
66832  *  0b10..Clear output (or set, based on OUTPUTDIRCTRL[SETCLRn])
66833  *  0b11..Toggle output
66834  */
66835 #define SCT_RES_O8RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O8RES_SHIFT)) & SCT_RES_O8RES_MASK)
66836 
66837 #define SCT_RES_O9RES_MASK                       (0xC0000U)
66838 #define SCT_RES_O9RES_SHIFT                      (18U)
66839 /*! O9RES - Output Resolution
66840  *  0b00..No change
66841  *  0b01..Set output (or clear, based on OUTPUTDIRCTRL[SETCLRn])
66842  *  0b10..Clear output (or set, based on OUTPUTDIRCTRL[SETCLRn])
66843  *  0b11..Toggle output
66844  */
66845 #define SCT_RES_O9RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O9RES_SHIFT)) & SCT_RES_O9RES_MASK)
66846 /*! @} */
66847 
66848 /*! @name DMAREQ0 - DMA Request 0 */
66849 /*! @{ */
66850 
66851 #define SCT_DMAREQ0_DEV_0_MASK                   (0x1U)
66852 #define SCT_DMAREQ0_DEV_0_SHIFT                  (0U)
66853 /*! DEV_0 - DMA Request Event */
66854 #define SCT_DMAREQ0_DEV_0(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_0_SHIFT)) & SCT_DMAREQ0_DEV_0_MASK)
66855 
66856 #define SCT_DMAREQ0_DEV_1_MASK                   (0x2U)
66857 #define SCT_DMAREQ0_DEV_1_SHIFT                  (1U)
66858 /*! DEV_1 - DMA Request Event */
66859 #define SCT_DMAREQ0_DEV_1(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_1_SHIFT)) & SCT_DMAREQ0_DEV_1_MASK)
66860 
66861 #define SCT_DMAREQ0_DEV_2_MASK                   (0x4U)
66862 #define SCT_DMAREQ0_DEV_2_SHIFT                  (2U)
66863 /*! DEV_2 - DMA Request Event */
66864 #define SCT_DMAREQ0_DEV_2(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_2_SHIFT)) & SCT_DMAREQ0_DEV_2_MASK)
66865 
66866 #define SCT_DMAREQ0_DEV_3_MASK                   (0x8U)
66867 #define SCT_DMAREQ0_DEV_3_SHIFT                  (3U)
66868 /*! DEV_3 - DMA Request Event */
66869 #define SCT_DMAREQ0_DEV_3(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_3_SHIFT)) & SCT_DMAREQ0_DEV_3_MASK)
66870 
66871 #define SCT_DMAREQ0_DEV_4_MASK                   (0x10U)
66872 #define SCT_DMAREQ0_DEV_4_SHIFT                  (4U)
66873 /*! DEV_4 - DMA Request Event */
66874 #define SCT_DMAREQ0_DEV_4(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_4_SHIFT)) & SCT_DMAREQ0_DEV_4_MASK)
66875 
66876 #define SCT_DMAREQ0_DEV_5_MASK                   (0x20U)
66877 #define SCT_DMAREQ0_DEV_5_SHIFT                  (5U)
66878 /*! DEV_5 - DMA Request Event */
66879 #define SCT_DMAREQ0_DEV_5(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_5_SHIFT)) & SCT_DMAREQ0_DEV_5_MASK)
66880 
66881 #define SCT_DMAREQ0_DEV_6_MASK                   (0x40U)
66882 #define SCT_DMAREQ0_DEV_6_SHIFT                  (6U)
66883 /*! DEV_6 - DMA Request Event */
66884 #define SCT_DMAREQ0_DEV_6(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_6_SHIFT)) & SCT_DMAREQ0_DEV_6_MASK)
66885 
66886 #define SCT_DMAREQ0_DEV_7_MASK                   (0x80U)
66887 #define SCT_DMAREQ0_DEV_7_SHIFT                  (7U)
66888 /*! DEV_7 - DMA Request Event */
66889 #define SCT_DMAREQ0_DEV_7(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_7_SHIFT)) & SCT_DMAREQ0_DEV_7_MASK)
66890 
66891 #define SCT_DMAREQ0_DEV_8_MASK                   (0x100U)
66892 #define SCT_DMAREQ0_DEV_8_SHIFT                  (8U)
66893 /*! DEV_8 - DMA Request Event */
66894 #define SCT_DMAREQ0_DEV_8(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_8_SHIFT)) & SCT_DMAREQ0_DEV_8_MASK)
66895 
66896 #define SCT_DMAREQ0_DEV_9_MASK                   (0x200U)
66897 #define SCT_DMAREQ0_DEV_9_SHIFT                  (9U)
66898 /*! DEV_9 - DMA Request Event */
66899 #define SCT_DMAREQ0_DEV_9(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_9_SHIFT)) & SCT_DMAREQ0_DEV_9_MASK)
66900 
66901 #define SCT_DMAREQ0_DEV_10_MASK                  (0x400U)
66902 #define SCT_DMAREQ0_DEV_10_SHIFT                 (10U)
66903 /*! DEV_10 - DMA Request Event */
66904 #define SCT_DMAREQ0_DEV_10(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_10_SHIFT)) & SCT_DMAREQ0_DEV_10_MASK)
66905 
66906 #define SCT_DMAREQ0_DEV_11_MASK                  (0x800U)
66907 #define SCT_DMAREQ0_DEV_11_SHIFT                 (11U)
66908 /*! DEV_11 - DMA Request Event */
66909 #define SCT_DMAREQ0_DEV_11(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_11_SHIFT)) & SCT_DMAREQ0_DEV_11_MASK)
66910 
66911 #define SCT_DMAREQ0_DEV_12_MASK                  (0x1000U)
66912 #define SCT_DMAREQ0_DEV_12_SHIFT                 (12U)
66913 /*! DEV_12 - DMA Request Event */
66914 #define SCT_DMAREQ0_DEV_12(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_12_SHIFT)) & SCT_DMAREQ0_DEV_12_MASK)
66915 
66916 #define SCT_DMAREQ0_DEV_13_MASK                  (0x2000U)
66917 #define SCT_DMAREQ0_DEV_13_SHIFT                 (13U)
66918 /*! DEV_13 - DMA Request Event */
66919 #define SCT_DMAREQ0_DEV_13(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_13_SHIFT)) & SCT_DMAREQ0_DEV_13_MASK)
66920 
66921 #define SCT_DMAREQ0_DEV_14_MASK                  (0x4000U)
66922 #define SCT_DMAREQ0_DEV_14_SHIFT                 (14U)
66923 /*! DEV_14 - DMA Request Event */
66924 #define SCT_DMAREQ0_DEV_14(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_14_SHIFT)) & SCT_DMAREQ0_DEV_14_MASK)
66925 
66926 #define SCT_DMAREQ0_DEV_15_MASK                  (0x8000U)
66927 #define SCT_DMAREQ0_DEV_15_SHIFT                 (15U)
66928 /*! DEV_15 - DMA Request Event */
66929 #define SCT_DMAREQ0_DEV_15(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_15_SHIFT)) & SCT_DMAREQ0_DEV_15_MASK)
66930 
66931 #define SCT_DMAREQ0_DRL0_MASK                    (0x40000000U)
66932 #define SCT_DMAREQ0_DRL0_SHIFT                   (30U)
66933 /*! DRL0 - DMA Request Low 0 */
66934 #define SCT_DMAREQ0_DRL0(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DRL0_SHIFT)) & SCT_DMAREQ0_DRL0_MASK)
66935 
66936 #define SCT_DMAREQ0_DRQ0_MASK                    (0x80000000U)
66937 #define SCT_DMAREQ0_DRQ0_SHIFT                   (31U)
66938 /*! DRQ0 - DMA Request 0 State */
66939 #define SCT_DMAREQ0_DRQ0(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DRQ0_SHIFT)) & SCT_DMAREQ0_DRQ0_MASK)
66940 /*! @} */
66941 
66942 /*! @name DMAREQ1 - DMA Request 1 */
66943 /*! @{ */
66944 
66945 #define SCT_DMAREQ1_DEV_0_MASK                   (0x1U)
66946 #define SCT_DMAREQ1_DEV_0_SHIFT                  (0U)
66947 /*! DEV_0 - DMA Request Event */
66948 #define SCT_DMAREQ1_DEV_0(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_0_SHIFT)) & SCT_DMAREQ1_DEV_0_MASK)
66949 
66950 #define SCT_DMAREQ1_DEV_1_MASK                   (0x2U)
66951 #define SCT_DMAREQ1_DEV_1_SHIFT                  (1U)
66952 /*! DEV_1 - DMA Request Event */
66953 #define SCT_DMAREQ1_DEV_1(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_1_SHIFT)) & SCT_DMAREQ1_DEV_1_MASK)
66954 
66955 #define SCT_DMAREQ1_DEV_2_MASK                   (0x4U)
66956 #define SCT_DMAREQ1_DEV_2_SHIFT                  (2U)
66957 /*! DEV_2 - DMA Request Event */
66958 #define SCT_DMAREQ1_DEV_2(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_2_SHIFT)) & SCT_DMAREQ1_DEV_2_MASK)
66959 
66960 #define SCT_DMAREQ1_DEV_3_MASK                   (0x8U)
66961 #define SCT_DMAREQ1_DEV_3_SHIFT                  (3U)
66962 /*! DEV_3 - DMA Request Event */
66963 #define SCT_DMAREQ1_DEV_3(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_3_SHIFT)) & SCT_DMAREQ1_DEV_3_MASK)
66964 
66965 #define SCT_DMAREQ1_DEV_4_MASK                   (0x10U)
66966 #define SCT_DMAREQ1_DEV_4_SHIFT                  (4U)
66967 /*! DEV_4 - DMA Request Event */
66968 #define SCT_DMAREQ1_DEV_4(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_4_SHIFT)) & SCT_DMAREQ1_DEV_4_MASK)
66969 
66970 #define SCT_DMAREQ1_DEV_5_MASK                   (0x20U)
66971 #define SCT_DMAREQ1_DEV_5_SHIFT                  (5U)
66972 /*! DEV_5 - DMA Request Event */
66973 #define SCT_DMAREQ1_DEV_5(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_5_SHIFT)) & SCT_DMAREQ1_DEV_5_MASK)
66974 
66975 #define SCT_DMAREQ1_DEV_6_MASK                   (0x40U)
66976 #define SCT_DMAREQ1_DEV_6_SHIFT                  (6U)
66977 /*! DEV_6 - DMA Request Event */
66978 #define SCT_DMAREQ1_DEV_6(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_6_SHIFT)) & SCT_DMAREQ1_DEV_6_MASK)
66979 
66980 #define SCT_DMAREQ1_DEV_7_MASK                   (0x80U)
66981 #define SCT_DMAREQ1_DEV_7_SHIFT                  (7U)
66982 /*! DEV_7 - DMA Request Event */
66983 #define SCT_DMAREQ1_DEV_7(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_7_SHIFT)) & SCT_DMAREQ1_DEV_7_MASK)
66984 
66985 #define SCT_DMAREQ1_DEV_8_MASK                   (0x100U)
66986 #define SCT_DMAREQ1_DEV_8_SHIFT                  (8U)
66987 /*! DEV_8 - DMA Request Event */
66988 #define SCT_DMAREQ1_DEV_8(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_8_SHIFT)) & SCT_DMAREQ1_DEV_8_MASK)
66989 
66990 #define SCT_DMAREQ1_DEV_9_MASK                   (0x200U)
66991 #define SCT_DMAREQ1_DEV_9_SHIFT                  (9U)
66992 /*! DEV_9 - DMA Request Event */
66993 #define SCT_DMAREQ1_DEV_9(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_9_SHIFT)) & SCT_DMAREQ1_DEV_9_MASK)
66994 
66995 #define SCT_DMAREQ1_DEV_10_MASK                  (0x400U)
66996 #define SCT_DMAREQ1_DEV_10_SHIFT                 (10U)
66997 /*! DEV_10 - DMA Request Event */
66998 #define SCT_DMAREQ1_DEV_10(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_10_SHIFT)) & SCT_DMAREQ1_DEV_10_MASK)
66999 
67000 #define SCT_DMAREQ1_DEV_11_MASK                  (0x800U)
67001 #define SCT_DMAREQ1_DEV_11_SHIFT                 (11U)
67002 /*! DEV_11 - DMA Request Event */
67003 #define SCT_DMAREQ1_DEV_11(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_11_SHIFT)) & SCT_DMAREQ1_DEV_11_MASK)
67004 
67005 #define SCT_DMAREQ1_DEV_12_MASK                  (0x1000U)
67006 #define SCT_DMAREQ1_DEV_12_SHIFT                 (12U)
67007 /*! DEV_12 - DMA Request Event */
67008 #define SCT_DMAREQ1_DEV_12(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_12_SHIFT)) & SCT_DMAREQ1_DEV_12_MASK)
67009 
67010 #define SCT_DMAREQ1_DEV_13_MASK                  (0x2000U)
67011 #define SCT_DMAREQ1_DEV_13_SHIFT                 (13U)
67012 /*! DEV_13 - DMA Request Event */
67013 #define SCT_DMAREQ1_DEV_13(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_13_SHIFT)) & SCT_DMAREQ1_DEV_13_MASK)
67014 
67015 #define SCT_DMAREQ1_DEV_14_MASK                  (0x4000U)
67016 #define SCT_DMAREQ1_DEV_14_SHIFT                 (14U)
67017 /*! DEV_14 - DMA Request Event */
67018 #define SCT_DMAREQ1_DEV_14(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_14_SHIFT)) & SCT_DMAREQ1_DEV_14_MASK)
67019 
67020 #define SCT_DMAREQ1_DEV_15_MASK                  (0x8000U)
67021 #define SCT_DMAREQ1_DEV_15_SHIFT                 (15U)
67022 /*! DEV_15 - DMA Request Event */
67023 #define SCT_DMAREQ1_DEV_15(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_15_SHIFT)) & SCT_DMAREQ1_DEV_15_MASK)
67024 
67025 #define SCT_DMAREQ1_DRL1_MASK                    (0x40000000U)
67026 #define SCT_DMAREQ1_DRL1_SHIFT                   (30U)
67027 /*! DRL1 - DMA Request Low 1 */
67028 #define SCT_DMAREQ1_DRL1(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DRL1_SHIFT)) & SCT_DMAREQ1_DRL1_MASK)
67029 
67030 #define SCT_DMAREQ1_DRQ1_MASK                    (0x80000000U)
67031 #define SCT_DMAREQ1_DRQ1_SHIFT                   (31U)
67032 /*! DRQ1 - DMA Request 1 State */
67033 #define SCT_DMAREQ1_DRQ1(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DRQ1_SHIFT)) & SCT_DMAREQ1_DRQ1_MASK)
67034 /*! @} */
67035 
67036 /*! @name EVEN - Event Interrupt Enable */
67037 /*! @{ */
67038 
67039 #define SCT_EVEN_IEN0_MASK                       (0x1U)
67040 #define SCT_EVEN_IEN0_SHIFT                      (0U)
67041 /*! IEN0 - Event Interrupt Enable
67042  *  0b0..Disables
67043  *  0b1..Enables
67044  */
67045 #define SCT_EVEN_IEN0(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN0_SHIFT)) & SCT_EVEN_IEN0_MASK)
67046 
67047 #define SCT_EVEN_IEN1_MASK                       (0x2U)
67048 #define SCT_EVEN_IEN1_SHIFT                      (1U)
67049 /*! IEN1 - Event Interrupt Enable
67050  *  0b0..Disables
67051  *  0b1..Enables
67052  */
67053 #define SCT_EVEN_IEN1(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN1_SHIFT)) & SCT_EVEN_IEN1_MASK)
67054 
67055 #define SCT_EVEN_IEN2_MASK                       (0x4U)
67056 #define SCT_EVEN_IEN2_SHIFT                      (2U)
67057 /*! IEN2 - Event Interrupt Enable
67058  *  0b0..Disables
67059  *  0b1..Enables
67060  */
67061 #define SCT_EVEN_IEN2(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN2_SHIFT)) & SCT_EVEN_IEN2_MASK)
67062 
67063 #define SCT_EVEN_IEN3_MASK                       (0x8U)
67064 #define SCT_EVEN_IEN3_SHIFT                      (3U)
67065 /*! IEN3 - Event Interrupt Enable
67066  *  0b0..Disables
67067  *  0b1..Enables
67068  */
67069 #define SCT_EVEN_IEN3(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN3_SHIFT)) & SCT_EVEN_IEN3_MASK)
67070 
67071 #define SCT_EVEN_IEN4_MASK                       (0x10U)
67072 #define SCT_EVEN_IEN4_SHIFT                      (4U)
67073 /*! IEN4 - Event Interrupt Enable
67074  *  0b0..Disables
67075  *  0b1..Enables
67076  */
67077 #define SCT_EVEN_IEN4(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN4_SHIFT)) & SCT_EVEN_IEN4_MASK)
67078 
67079 #define SCT_EVEN_IEN5_MASK                       (0x20U)
67080 #define SCT_EVEN_IEN5_SHIFT                      (5U)
67081 /*! IEN5 - Event Interrupt Enable
67082  *  0b0..Disables
67083  *  0b1..Enables
67084  */
67085 #define SCT_EVEN_IEN5(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN5_SHIFT)) & SCT_EVEN_IEN5_MASK)
67086 
67087 #define SCT_EVEN_IEN6_MASK                       (0x40U)
67088 #define SCT_EVEN_IEN6_SHIFT                      (6U)
67089 /*! IEN6 - Event Interrupt Enable
67090  *  0b0..Disables
67091  *  0b1..Enables
67092  */
67093 #define SCT_EVEN_IEN6(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN6_SHIFT)) & SCT_EVEN_IEN6_MASK)
67094 
67095 #define SCT_EVEN_IEN7_MASK                       (0x80U)
67096 #define SCT_EVEN_IEN7_SHIFT                      (7U)
67097 /*! IEN7 - Event Interrupt Enable
67098  *  0b0..Disables
67099  *  0b1..Enables
67100  */
67101 #define SCT_EVEN_IEN7(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN7_SHIFT)) & SCT_EVEN_IEN7_MASK)
67102 
67103 #define SCT_EVEN_IEN8_MASK                       (0x100U)
67104 #define SCT_EVEN_IEN8_SHIFT                      (8U)
67105 /*! IEN8 - Event Interrupt Enable
67106  *  0b0..Disables
67107  *  0b1..Enables
67108  */
67109 #define SCT_EVEN_IEN8(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN8_SHIFT)) & SCT_EVEN_IEN8_MASK)
67110 
67111 #define SCT_EVEN_IEN9_MASK                       (0x200U)
67112 #define SCT_EVEN_IEN9_SHIFT                      (9U)
67113 /*! IEN9 - Event Interrupt Enable
67114  *  0b0..Disables
67115  *  0b1..Enables
67116  */
67117 #define SCT_EVEN_IEN9(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN9_SHIFT)) & SCT_EVEN_IEN9_MASK)
67118 
67119 #define SCT_EVEN_IEN10_MASK                      (0x400U)
67120 #define SCT_EVEN_IEN10_SHIFT                     (10U)
67121 /*! IEN10 - Event Interrupt Enable
67122  *  0b0..Disables
67123  *  0b1..Enables
67124  */
67125 #define SCT_EVEN_IEN10(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN10_SHIFT)) & SCT_EVEN_IEN10_MASK)
67126 
67127 #define SCT_EVEN_IEN11_MASK                      (0x800U)
67128 #define SCT_EVEN_IEN11_SHIFT                     (11U)
67129 /*! IEN11 - Event Interrupt Enable
67130  *  0b0..Disables
67131  *  0b1..Enables
67132  */
67133 #define SCT_EVEN_IEN11(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN11_SHIFT)) & SCT_EVEN_IEN11_MASK)
67134 
67135 #define SCT_EVEN_IEN12_MASK                      (0x1000U)
67136 #define SCT_EVEN_IEN12_SHIFT                     (12U)
67137 /*! IEN12 - Event Interrupt Enable
67138  *  0b0..Disables
67139  *  0b1..Enables
67140  */
67141 #define SCT_EVEN_IEN12(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN12_SHIFT)) & SCT_EVEN_IEN12_MASK)
67142 
67143 #define SCT_EVEN_IEN13_MASK                      (0x2000U)
67144 #define SCT_EVEN_IEN13_SHIFT                     (13U)
67145 /*! IEN13 - Event Interrupt Enable
67146  *  0b0..Disables
67147  *  0b1..Enables
67148  */
67149 #define SCT_EVEN_IEN13(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN13_SHIFT)) & SCT_EVEN_IEN13_MASK)
67150 
67151 #define SCT_EVEN_IEN14_MASK                      (0x4000U)
67152 #define SCT_EVEN_IEN14_SHIFT                     (14U)
67153 /*! IEN14 - Event Interrupt Enable
67154  *  0b0..Disables
67155  *  0b1..Enables
67156  */
67157 #define SCT_EVEN_IEN14(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN14_SHIFT)) & SCT_EVEN_IEN14_MASK)
67158 
67159 #define SCT_EVEN_IEN15_MASK                      (0x8000U)
67160 #define SCT_EVEN_IEN15_SHIFT                     (15U)
67161 /*! IEN15 - Event Interrupt Enable
67162  *  0b0..Disables
67163  *  0b1..Enables
67164  */
67165 #define SCT_EVEN_IEN15(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN15_SHIFT)) & SCT_EVEN_IEN15_MASK)
67166 /*! @} */
67167 
67168 /*! @name EVFLAG - Event Flag */
67169 /*! @{ */
67170 
67171 #define SCT_EVFLAG_FLAG0_MASK                    (0x1U)
67172 #define SCT_EVFLAG_FLAG0_SHIFT                   (0U)
67173 /*! FLAG0 - Event Flag
67174  *  0b0..No flag
67175  *  0b1..Event n flag
67176  */
67177 #define SCT_EVFLAG_FLAG0(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG0_SHIFT)) & SCT_EVFLAG_FLAG0_MASK)
67178 
67179 #define SCT_EVFLAG_FLAG1_MASK                    (0x2U)
67180 #define SCT_EVFLAG_FLAG1_SHIFT                   (1U)
67181 /*! FLAG1 - Event Flag
67182  *  0b0..No flag
67183  *  0b1..Event n flag
67184  */
67185 #define SCT_EVFLAG_FLAG1(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG1_SHIFT)) & SCT_EVFLAG_FLAG1_MASK)
67186 
67187 #define SCT_EVFLAG_FLAG2_MASK                    (0x4U)
67188 #define SCT_EVFLAG_FLAG2_SHIFT                   (2U)
67189 /*! FLAG2 - Event Flag
67190  *  0b0..No flag
67191  *  0b1..Event n flag
67192  */
67193 #define SCT_EVFLAG_FLAG2(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG2_SHIFT)) & SCT_EVFLAG_FLAG2_MASK)
67194 
67195 #define SCT_EVFLAG_FLAG3_MASK                    (0x8U)
67196 #define SCT_EVFLAG_FLAG3_SHIFT                   (3U)
67197 /*! FLAG3 - Event Flag
67198  *  0b0..No flag
67199  *  0b1..Event n flag
67200  */
67201 #define SCT_EVFLAG_FLAG3(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG3_SHIFT)) & SCT_EVFLAG_FLAG3_MASK)
67202 
67203 #define SCT_EVFLAG_FLAG4_MASK                    (0x10U)
67204 #define SCT_EVFLAG_FLAG4_SHIFT                   (4U)
67205 /*! FLAG4 - Event Flag
67206  *  0b0..No flag
67207  *  0b1..Event n flag
67208  */
67209 #define SCT_EVFLAG_FLAG4(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG4_SHIFT)) & SCT_EVFLAG_FLAG4_MASK)
67210 
67211 #define SCT_EVFLAG_FLAG5_MASK                    (0x20U)
67212 #define SCT_EVFLAG_FLAG5_SHIFT                   (5U)
67213 /*! FLAG5 - Event Flag
67214  *  0b0..No flag
67215  *  0b1..Event n flag
67216  */
67217 #define SCT_EVFLAG_FLAG5(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG5_SHIFT)) & SCT_EVFLAG_FLAG5_MASK)
67218 
67219 #define SCT_EVFLAG_FLAG6_MASK                    (0x40U)
67220 #define SCT_EVFLAG_FLAG6_SHIFT                   (6U)
67221 /*! FLAG6 - Event Flag
67222  *  0b0..No flag
67223  *  0b1..Event n flag
67224  */
67225 #define SCT_EVFLAG_FLAG6(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG6_SHIFT)) & SCT_EVFLAG_FLAG6_MASK)
67226 
67227 #define SCT_EVFLAG_FLAG7_MASK                    (0x80U)
67228 #define SCT_EVFLAG_FLAG7_SHIFT                   (7U)
67229 /*! FLAG7 - Event Flag
67230  *  0b0..No flag
67231  *  0b1..Event n flag
67232  */
67233 #define SCT_EVFLAG_FLAG7(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG7_SHIFT)) & SCT_EVFLAG_FLAG7_MASK)
67234 
67235 #define SCT_EVFLAG_FLAG8_MASK                    (0x100U)
67236 #define SCT_EVFLAG_FLAG8_SHIFT                   (8U)
67237 /*! FLAG8 - Event Flag
67238  *  0b0..No flag
67239  *  0b1..Event n flag
67240  */
67241 #define SCT_EVFLAG_FLAG8(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG8_SHIFT)) & SCT_EVFLAG_FLAG8_MASK)
67242 
67243 #define SCT_EVFLAG_FLAG9_MASK                    (0x200U)
67244 #define SCT_EVFLAG_FLAG9_SHIFT                   (9U)
67245 /*! FLAG9 - Event Flag
67246  *  0b0..No flag
67247  *  0b1..Event n flag
67248  */
67249 #define SCT_EVFLAG_FLAG9(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG9_SHIFT)) & SCT_EVFLAG_FLAG9_MASK)
67250 
67251 #define SCT_EVFLAG_FLAG10_MASK                   (0x400U)
67252 #define SCT_EVFLAG_FLAG10_SHIFT                  (10U)
67253 /*! FLAG10 - Event Flag
67254  *  0b0..No flag
67255  *  0b1..Event n flag
67256  */
67257 #define SCT_EVFLAG_FLAG10(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG10_SHIFT)) & SCT_EVFLAG_FLAG10_MASK)
67258 
67259 #define SCT_EVFLAG_FLAG11_MASK                   (0x800U)
67260 #define SCT_EVFLAG_FLAG11_SHIFT                  (11U)
67261 /*! FLAG11 - Event Flag
67262  *  0b0..No flag
67263  *  0b1..Event n flag
67264  */
67265 #define SCT_EVFLAG_FLAG11(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG11_SHIFT)) & SCT_EVFLAG_FLAG11_MASK)
67266 
67267 #define SCT_EVFLAG_FLAG12_MASK                   (0x1000U)
67268 #define SCT_EVFLAG_FLAG12_SHIFT                  (12U)
67269 /*! FLAG12 - Event Flag
67270  *  0b0..No flag
67271  *  0b1..Event n flag
67272  */
67273 #define SCT_EVFLAG_FLAG12(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG12_SHIFT)) & SCT_EVFLAG_FLAG12_MASK)
67274 
67275 #define SCT_EVFLAG_FLAG13_MASK                   (0x2000U)
67276 #define SCT_EVFLAG_FLAG13_SHIFT                  (13U)
67277 /*! FLAG13 - Event Flag
67278  *  0b0..No flag
67279  *  0b1..Event n flag
67280  */
67281 #define SCT_EVFLAG_FLAG13(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG13_SHIFT)) & SCT_EVFLAG_FLAG13_MASK)
67282 
67283 #define SCT_EVFLAG_FLAG14_MASK                   (0x4000U)
67284 #define SCT_EVFLAG_FLAG14_SHIFT                  (14U)
67285 /*! FLAG14 - Event Flag
67286  *  0b0..No flag
67287  *  0b1..Event n flag
67288  */
67289 #define SCT_EVFLAG_FLAG14(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG14_SHIFT)) & SCT_EVFLAG_FLAG14_MASK)
67290 
67291 #define SCT_EVFLAG_FLAG15_MASK                   (0x8000U)
67292 #define SCT_EVFLAG_FLAG15_SHIFT                  (15U)
67293 /*! FLAG15 - Event Flag
67294  *  0b0..No flag
67295  *  0b1..Event n flag
67296  */
67297 #define SCT_EVFLAG_FLAG15(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG15_SHIFT)) & SCT_EVFLAG_FLAG15_MASK)
67298 /*! @} */
67299 
67300 /*! @name CONEN - Conflict Interrupt Enable */
67301 /*! @{ */
67302 
67303 #define SCT_CONEN_NCEN0_MASK                     (0x1U)
67304 #define SCT_CONEN_NCEN0_SHIFT                    (0U)
67305 /*! NCEN0 - No Change Conflict Event and Interrupt Enable
67306  *  0b0..No interrupt
67307  *  0b1..Interrupt
67308  */
67309 #define SCT_CONEN_NCEN0(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN0_SHIFT)) & SCT_CONEN_NCEN0_MASK)
67310 
67311 #define SCT_CONEN_NCEN1_MASK                     (0x2U)
67312 #define SCT_CONEN_NCEN1_SHIFT                    (1U)
67313 /*! NCEN1 - No Change Conflict Event and Interrupt Enable
67314  *  0b0..No interrupt
67315  *  0b1..Interrupt
67316  */
67317 #define SCT_CONEN_NCEN1(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN1_SHIFT)) & SCT_CONEN_NCEN1_MASK)
67318 
67319 #define SCT_CONEN_NCEN2_MASK                     (0x4U)
67320 #define SCT_CONEN_NCEN2_SHIFT                    (2U)
67321 /*! NCEN2 - No Change Conflict Event and Interrupt Enable
67322  *  0b0..No interrupt
67323  *  0b1..Interrupt
67324  */
67325 #define SCT_CONEN_NCEN2(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN2_SHIFT)) & SCT_CONEN_NCEN2_MASK)
67326 
67327 #define SCT_CONEN_NCEN3_MASK                     (0x8U)
67328 #define SCT_CONEN_NCEN3_SHIFT                    (3U)
67329 /*! NCEN3 - No Change Conflict Event and Interrupt Enable
67330  *  0b0..No interrupt
67331  *  0b1..Interrupt
67332  */
67333 #define SCT_CONEN_NCEN3(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN3_SHIFT)) & SCT_CONEN_NCEN3_MASK)
67334 
67335 #define SCT_CONEN_NCEN4_MASK                     (0x10U)
67336 #define SCT_CONEN_NCEN4_SHIFT                    (4U)
67337 /*! NCEN4 - No Change Conflict Event and Interrupt Enable
67338  *  0b0..No interrupt
67339  *  0b1..Interrupt
67340  */
67341 #define SCT_CONEN_NCEN4(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN4_SHIFT)) & SCT_CONEN_NCEN4_MASK)
67342 
67343 #define SCT_CONEN_NCEN5_MASK                     (0x20U)
67344 #define SCT_CONEN_NCEN5_SHIFT                    (5U)
67345 /*! NCEN5 - No Change Conflict Event and Interrupt Enable
67346  *  0b0..No interrupt
67347  *  0b1..Interrupt
67348  */
67349 #define SCT_CONEN_NCEN5(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN5_SHIFT)) & SCT_CONEN_NCEN5_MASK)
67350 
67351 #define SCT_CONEN_NCEN6_MASK                     (0x40U)
67352 #define SCT_CONEN_NCEN6_SHIFT                    (6U)
67353 /*! NCEN6 - No Change Conflict Event and Interrupt Enable
67354  *  0b0..No interrupt
67355  *  0b1..Interrupt
67356  */
67357 #define SCT_CONEN_NCEN6(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN6_SHIFT)) & SCT_CONEN_NCEN6_MASK)
67358 
67359 #define SCT_CONEN_NCEN7_MASK                     (0x80U)
67360 #define SCT_CONEN_NCEN7_SHIFT                    (7U)
67361 /*! NCEN7 - No Change Conflict Event and Interrupt Enable
67362  *  0b0..No interrupt
67363  *  0b1..Interrupt
67364  */
67365 #define SCT_CONEN_NCEN7(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN7_SHIFT)) & SCT_CONEN_NCEN7_MASK)
67366 
67367 #define SCT_CONEN_NCEN8_MASK                     (0x100U)
67368 #define SCT_CONEN_NCEN8_SHIFT                    (8U)
67369 /*! NCEN8 - No Change Conflict Event and Interrupt Enable
67370  *  0b0..No interrupt
67371  *  0b1..Interrupt
67372  */
67373 #define SCT_CONEN_NCEN8(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN8_SHIFT)) & SCT_CONEN_NCEN8_MASK)
67374 
67375 #define SCT_CONEN_NCEN9_MASK                     (0x200U)
67376 #define SCT_CONEN_NCEN9_SHIFT                    (9U)
67377 /*! NCEN9 - No Change Conflict Event and Interrupt Enable
67378  *  0b0..No interrupt
67379  *  0b1..Interrupt
67380  */
67381 #define SCT_CONEN_NCEN9(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN9_SHIFT)) & SCT_CONEN_NCEN9_MASK)
67382 /*! @} */
67383 
67384 /*! @name CONFLAG - Conflict Flag */
67385 /*! @{ */
67386 
67387 #define SCT_CONFLAG_NCFLAG0_MASK                 (0x1U)
67388 #define SCT_CONFLAG_NCFLAG0_SHIFT                (0U)
67389 /*! NCFLAG0 - No Change Conflict Event Flag
67390  *  0b0..Did not occur
67391  *  0b1..Occurred
67392  */
67393 #define SCT_CONFLAG_NCFLAG0(x)                   (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG0_SHIFT)) & SCT_CONFLAG_NCFLAG0_MASK)
67394 
67395 #define SCT_CONFLAG_NCFLAG1_MASK                 (0x2U)
67396 #define SCT_CONFLAG_NCFLAG1_SHIFT                (1U)
67397 /*! NCFLAG1 - No Change Conflict Event Flag
67398  *  0b0..Did not occur
67399  *  0b1..Occurred
67400  */
67401 #define SCT_CONFLAG_NCFLAG1(x)                   (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG1_SHIFT)) & SCT_CONFLAG_NCFLAG1_MASK)
67402 
67403 #define SCT_CONFLAG_NCFLAG2_MASK                 (0x4U)
67404 #define SCT_CONFLAG_NCFLAG2_SHIFT                (2U)
67405 /*! NCFLAG2 - No Change Conflict Event Flag
67406  *  0b0..Did not occur
67407  *  0b1..Occurred
67408  */
67409 #define SCT_CONFLAG_NCFLAG2(x)                   (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG2_SHIFT)) & SCT_CONFLAG_NCFLAG2_MASK)
67410 
67411 #define SCT_CONFLAG_NCFLAG3_MASK                 (0x8U)
67412 #define SCT_CONFLAG_NCFLAG3_SHIFT                (3U)
67413 /*! NCFLAG3 - No Change Conflict Event Flag
67414  *  0b0..Did not occur
67415  *  0b1..Occurred
67416  */
67417 #define SCT_CONFLAG_NCFLAG3(x)                   (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG3_SHIFT)) & SCT_CONFLAG_NCFLAG3_MASK)
67418 
67419 #define SCT_CONFLAG_NCFLAG4_MASK                 (0x10U)
67420 #define SCT_CONFLAG_NCFLAG4_SHIFT                (4U)
67421 /*! NCFLAG4 - No Change Conflict Event Flag
67422  *  0b0..Did not occur
67423  *  0b1..Occurred
67424  */
67425 #define SCT_CONFLAG_NCFLAG4(x)                   (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG4_SHIFT)) & SCT_CONFLAG_NCFLAG4_MASK)
67426 
67427 #define SCT_CONFLAG_NCFLAG5_MASK                 (0x20U)
67428 #define SCT_CONFLAG_NCFLAG5_SHIFT                (5U)
67429 /*! NCFLAG5 - No Change Conflict Event Flag
67430  *  0b0..Did not occur
67431  *  0b1..Occurred
67432  */
67433 #define SCT_CONFLAG_NCFLAG5(x)                   (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG5_SHIFT)) & SCT_CONFLAG_NCFLAG5_MASK)
67434 
67435 #define SCT_CONFLAG_NCFLAG6_MASK                 (0x40U)
67436 #define SCT_CONFLAG_NCFLAG6_SHIFT                (6U)
67437 /*! NCFLAG6 - No Change Conflict Event Flag
67438  *  0b0..Did not occur
67439  *  0b1..Occurred
67440  */
67441 #define SCT_CONFLAG_NCFLAG6(x)                   (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG6_SHIFT)) & SCT_CONFLAG_NCFLAG6_MASK)
67442 
67443 #define SCT_CONFLAG_NCFLAG7_MASK                 (0x80U)
67444 #define SCT_CONFLAG_NCFLAG7_SHIFT                (7U)
67445 /*! NCFLAG7 - No Change Conflict Event Flag
67446  *  0b0..Did not occur
67447  *  0b1..Occurred
67448  */
67449 #define SCT_CONFLAG_NCFLAG7(x)                   (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG7_SHIFT)) & SCT_CONFLAG_NCFLAG7_MASK)
67450 
67451 #define SCT_CONFLAG_NCFLAG8_MASK                 (0x100U)
67452 #define SCT_CONFLAG_NCFLAG8_SHIFT                (8U)
67453 /*! NCFLAG8 - No Change Conflict Event Flag
67454  *  0b0..Did not occur
67455  *  0b1..Occurred
67456  */
67457 #define SCT_CONFLAG_NCFLAG8(x)                   (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG8_SHIFT)) & SCT_CONFLAG_NCFLAG8_MASK)
67458 
67459 #define SCT_CONFLAG_NCFLAG9_MASK                 (0x200U)
67460 #define SCT_CONFLAG_NCFLAG9_SHIFT                (9U)
67461 /*! NCFLAG9 - No Change Conflict Event Flag
67462  *  0b0..Did not occur
67463  *  0b1..Occurred
67464  */
67465 #define SCT_CONFLAG_NCFLAG9(x)                   (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG9_SHIFT)) & SCT_CONFLAG_NCFLAG9_MASK)
67466 
67467 #define SCT_CONFLAG_BUSERRL_MASK                 (0x40000000U)
67468 #define SCT_CONFLAG_BUSERRL_SHIFT                (30U)
67469 /*! BUSERRL - Bus Error Low or Unified */
67470 #define SCT_CONFLAG_BUSERRL(x)                   (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRL_SHIFT)) & SCT_CONFLAG_BUSERRL_MASK)
67471 
67472 #define SCT_CONFLAG_BUSERRH_MASK                 (0x80000000U)
67473 #define SCT_CONFLAG_BUSERRH_SHIFT                (31U)
67474 /*! BUSERRH - Bus Error High */
67475 #define SCT_CONFLAG_BUSERRH(x)                   (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRH_SHIFT)) & SCT_CONFLAG_BUSERRH_MASK)
67476 /*! @} */
67477 
67478 /*! @name CAPL - SCT_CAPL register */
67479 /*! @{ */
67480 
67481 #define SCT_CAPL_CAPL_MASK                       (0xFFFFU)
67482 #define SCT_CAPL_CAPL_SHIFT                      (0U)
67483 #define SCT_CAPL_CAPL(x)                         (((uint16_t)(((uint16_t)(x)) << SCT_CAPL_CAPL_SHIFT)) & SCT_CAPL_CAPL_MASK)
67484 /*! @} */
67485 
67486 /* The count of SCT_CAPL */
67487 #define SCT_CAPL_COUNT                           (16U)
67488 
67489 /*! @name CAPH - SCT_CAPH register */
67490 /*! @{ */
67491 
67492 #define SCT_CAPH_CAPH_MASK                       (0xFFFFU)
67493 #define SCT_CAPH_CAPH_SHIFT                      (0U)
67494 #define SCT_CAPH_CAPH(x)                         (((uint16_t)(((uint16_t)(x)) << SCT_CAPH_CAPH_SHIFT)) & SCT_CAPH_CAPH_MASK)
67495 /*! @} */
67496 
67497 /* The count of SCT_CAPH */
67498 #define SCT_CAPH_COUNT                           (16U)
67499 
67500 /*! @name CAP - Capture Value */
67501 /*! @{ */
67502 
67503 #define SCT_CAP_CAPn_L_MASK                      (0xFFFFU)
67504 #define SCT_CAP_CAPn_L_SHIFT                     (0U)
67505 /*! CAPn_L - Capture Low */
67506 #define SCT_CAP_CAPn_L(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_CAP_CAPn_L_SHIFT)) & SCT_CAP_CAPn_L_MASK)
67507 
67508 #define SCT_CAP_CAPn_H_MASK                      (0xFFFF0000U)
67509 #define SCT_CAP_CAPn_H_SHIFT                     (16U)
67510 /*! CAPn_H - Capture High */
67511 #define SCT_CAP_CAPn_H(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_CAP_CAPn_H_SHIFT)) & SCT_CAP_CAPn_H_MASK)
67512 /*! @} */
67513 
67514 /* The count of SCT_CAP */
67515 #define SCT_CAP_COUNT                            (16U)
67516 
67517 /*! @name MATCHL - SCT_MATCHL register */
67518 /*! @{ */
67519 
67520 #define SCT_MATCHL_MATCHL_MASK                   (0xFFFFU)
67521 #define SCT_MATCHL_MATCHL_SHIFT                  (0U)
67522 #define SCT_MATCHL_MATCHL(x)                     (((uint16_t)(((uint16_t)(x)) << SCT_MATCHL_MATCHL_SHIFT)) & SCT_MATCHL_MATCHL_MASK)
67523 /*! @} */
67524 
67525 /* The count of SCT_MATCHL */
67526 #define SCT_MATCHL_COUNT                         (16U)
67527 
67528 /*! @name MATCHH - SCT_MATCHH register */
67529 /*! @{ */
67530 
67531 #define SCT_MATCHH_MATCHH_MASK                   (0xFFFFU)
67532 #define SCT_MATCHH_MATCHH_SHIFT                  (0U)
67533 #define SCT_MATCHH_MATCHH(x)                     (((uint16_t)(((uint16_t)(x)) << SCT_MATCHH_MATCHH_SHIFT)) & SCT_MATCHH_MATCHH_MASK)
67534 /*! @} */
67535 
67536 /* The count of SCT_MATCHH */
67537 #define SCT_MATCHH_COUNT                         (16U)
67538 
67539 /*! @name MATCH - Match Value */
67540 /*! @{ */
67541 
67542 #define SCT_MATCH_MATCHn_L_MASK                  (0xFFFFU)
67543 #define SCT_MATCH_MATCHn_L_SHIFT                 (0U)
67544 /*! MATCHn_L - Match Low */
67545 #define SCT_MATCH_MATCHn_L(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_MATCH_MATCHn_L_SHIFT)) & SCT_MATCH_MATCHn_L_MASK)
67546 
67547 #define SCT_MATCH_MATCHn_H_MASK                  (0xFFFF0000U)
67548 #define SCT_MATCH_MATCHn_H_SHIFT                 (16U)
67549 /*! MATCHn_H - Match High */
67550 #define SCT_MATCH_MATCHn_H(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_MATCH_MATCHn_H_SHIFT)) & SCT_MATCH_MATCHn_H_MASK)
67551 /*! @} */
67552 
67553 /* The count of SCT_MATCH */
67554 #define SCT_MATCH_COUNT                          (16U)
67555 
67556 /*! @name FRACMAT - Fractional Match */
67557 /*! @{ */
67558 
67559 #define SCT_FRACMAT_FRACMAT_L_MASK               (0xFU)
67560 #define SCT_FRACMAT_FRACMAT_L_SHIFT              (0U)
67561 /*! FRACMAT_L - Fractional Match Low */
67562 #define SCT_FRACMAT_FRACMAT_L(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_FRACMAT_FRACMAT_L_SHIFT)) & SCT_FRACMAT_FRACMAT_L_MASK)
67563 
67564 #define SCT_FRACMAT_FRACMAT_H_MASK               (0xF0000U)
67565 #define SCT_FRACMAT_FRACMAT_H_SHIFT              (16U)
67566 /*! FRACMAT_H - Fractional Match High */
67567 #define SCT_FRACMAT_FRACMAT_H(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_FRACMAT_FRACMAT_H_SHIFT)) & SCT_FRACMAT_FRACMAT_H_MASK)
67568 /*! @} */
67569 
67570 /* The count of SCT_FRACMAT */
67571 #define SCT_FRACMAT_COUNT                        (6U)
67572 
67573 /*! @name CAPCTRLL - SCT_CAPCTRLL register */
67574 /*! @{ */
67575 
67576 #define SCT_CAPCTRLL_CAPCTRLL_MASK               (0xFFFFU)
67577 #define SCT_CAPCTRLL_CAPCTRLL_SHIFT              (0U)
67578 #define SCT_CAPCTRLL_CAPCTRLL(x)                 (((uint16_t)(((uint16_t)(x)) << SCT_CAPCTRLL_CAPCTRLL_SHIFT)) & SCT_CAPCTRLL_CAPCTRLL_MASK)
67579 /*! @} */
67580 
67581 /* The count of SCT_CAPCTRLL */
67582 #define SCT_CAPCTRLL_COUNT                       (16U)
67583 
67584 /*! @name CAPCTRLH - SCT_CAPCTRLH register */
67585 /*! @{ */
67586 
67587 #define SCT_CAPCTRLH_CAPCTRLH_MASK               (0xFFFFU)
67588 #define SCT_CAPCTRLH_CAPCTRLH_SHIFT              (0U)
67589 #define SCT_CAPCTRLH_CAPCTRLH(x)                 (((uint16_t)(((uint16_t)(x)) << SCT_CAPCTRLH_CAPCTRLH_SHIFT)) & SCT_CAPCTRLH_CAPCTRLH_MASK)
67590 /*! @} */
67591 
67592 /* The count of SCT_CAPCTRLH */
67593 #define SCT_CAPCTRLH_COUNT                       (16U)
67594 
67595 /*! @name SCTCAPCTRL_CAPCTRL - Capture Control */
67596 /*! @{ */
67597 
67598 #define SCT_SCTCAPCTRL_CAPCTRL_CAPCONn_L_MASK    (0xFFFFU)
67599 #define SCT_SCTCAPCTRL_CAPCTRL_CAPCONn_L_SHIFT   (0U)
67600 /*! CAPCONn_L - Capture Control Low */
67601 #define SCT_SCTCAPCTRL_CAPCTRL_CAPCONn_L(x)      (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAPCTRL_CAPCTRL_CAPCONn_L_SHIFT)) & SCT_SCTCAPCTRL_CAPCTRL_CAPCONn_L_MASK)
67602 
67603 #define SCT_SCTCAPCTRL_CAPCTRL_CAPCONn_H_MASK    (0xFFFF0000U)
67604 #define SCT_SCTCAPCTRL_CAPCTRL_CAPCONn_H_SHIFT   (16U)
67605 /*! CAPCONn_H - Capture Control High */
67606 #define SCT_SCTCAPCTRL_CAPCTRL_CAPCONn_H(x)      (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAPCTRL_CAPCTRL_CAPCONn_H_SHIFT)) & SCT_SCTCAPCTRL_CAPCTRL_CAPCONn_H_MASK)
67607 /*! @} */
67608 
67609 /* The count of SCT_SCTCAPCTRL_CAPCTRL */
67610 #define SCT_SCTCAPCTRL_CAPCTRL_COUNT             (16U)
67611 
67612 /*! @name MATCHRELL - SCT_MATCHRELL register */
67613 /*! @{ */
67614 
67615 #define SCT_MATCHRELL_MATCHRELL_MASK             (0xFFFFU)
67616 #define SCT_MATCHRELL_MATCHRELL_SHIFT            (0U)
67617 #define SCT_MATCHRELL_MATCHRELL(x)               (((uint16_t)(((uint16_t)(x)) << SCT_MATCHRELL_MATCHRELL_SHIFT)) & SCT_MATCHRELL_MATCHRELL_MASK)
67618 /*! @} */
67619 
67620 /* The count of SCT_MATCHRELL */
67621 #define SCT_MATCHRELL_COUNT                      (16U)
67622 
67623 /*! @name MATCHRELH - SCT_MATCHRELH register */
67624 /*! @{ */
67625 
67626 #define SCT_MATCHRELH_MATCHRELH_MASK             (0xFFFFU)
67627 #define SCT_MATCHRELH_MATCHRELH_SHIFT            (0U)
67628 #define SCT_MATCHRELH_MATCHRELH(x)               (((uint16_t)(((uint16_t)(x)) << SCT_MATCHRELH_MATCHRELH_SHIFT)) & SCT_MATCHRELH_MATCHRELH_MASK)
67629 /*! @} */
67630 
67631 /* The count of SCT_MATCHRELH */
67632 #define SCT_MATCHRELH_COUNT                      (16U)
67633 
67634 /*! @name MATCHREL - Match Reload Value */
67635 /*! @{ */
67636 
67637 #define SCT_MATCHREL_RELOADn_L_MASK              (0xFFFFU)
67638 #define SCT_MATCHREL_RELOADn_L_SHIFT             (0U)
67639 /*! RELOADn_L - Reload Low */
67640 #define SCT_MATCHREL_RELOADn_L(x)                (((uint32_t)(((uint32_t)(x)) << SCT_MATCHREL_RELOADn_L_SHIFT)) & SCT_MATCHREL_RELOADn_L_MASK)
67641 
67642 #define SCT_MATCHREL_RELOADn_H_MASK              (0xFFFF0000U)
67643 #define SCT_MATCHREL_RELOADn_H_SHIFT             (16U)
67644 /*! RELOADn_H - Reload High */
67645 #define SCT_MATCHREL_RELOADn_H(x)                (((uint32_t)(((uint32_t)(x)) << SCT_MATCHREL_RELOADn_H_SHIFT)) & SCT_MATCHREL_RELOADn_H_MASK)
67646 /*! @} */
67647 
67648 /* The count of SCT_MATCHREL */
67649 #define SCT_MATCHREL_COUNT                       (16U)
67650 
67651 /*! @name FRACMATREL - Fractional Match Reload */
67652 /*! @{ */
67653 
67654 #define SCT_FRACMATREL_RELFRAC_L_MASK            (0xFU)
67655 #define SCT_FRACMATREL_RELFRAC_L_SHIFT           (0U)
67656 /*! RELFRAC_L - Reload Fractional Match Low */
67657 #define SCT_FRACMATREL_RELFRAC_L(x)              (((uint32_t)(((uint32_t)(x)) << SCT_FRACMATREL_RELFRAC_L_SHIFT)) & SCT_FRACMATREL_RELFRAC_L_MASK)
67658 
67659 #define SCT_FRACMATREL_RELFRAC_H_MASK            (0xF0000U)
67660 #define SCT_FRACMATREL_RELFRAC_H_SHIFT           (16U)
67661 /*! RELFRAC_H - Reload Fractional Match High */
67662 #define SCT_FRACMATREL_RELFRAC_H(x)              (((uint32_t)(((uint32_t)(x)) << SCT_FRACMATREL_RELFRAC_H_SHIFT)) & SCT_FRACMATREL_RELFRAC_H_MASK)
67663 /*! @} */
67664 
67665 /* The count of SCT_FRACMATREL */
67666 #define SCT_FRACMATREL_COUNT                     (6U)
67667 
67668 /*! @name EV_STATE - Event n State */
67669 /*! @{ */
67670 
67671 #define SCT_EV_STATE_STATEMSKn_MASK              (0xFFFFFFFFU)
67672 #define SCT_EV_STATE_STATEMSKn_SHIFT             (0U)
67673 /*! STATEMSKn - Event State Mask */
67674 #define SCT_EV_STATE_STATEMSKn(x)                (((uint32_t)(((uint32_t)(x)) << SCT_EV_STATE_STATEMSKn_SHIFT)) & SCT_EV_STATE_STATEMSKn_MASK)
67675 /*! @} */
67676 
67677 /* The count of SCT_EV_STATE */
67678 #define SCT_EV_STATE_COUNT                       (16U)
67679 
67680 /*! @name EV_CTRL - Event n Control */
67681 /*! @{ */
67682 
67683 #define SCT_EV_CTRL_MATCHSEL_MASK                (0xFU)
67684 #define SCT_EV_CTRL_MATCHSEL_SHIFT               (0U)
67685 /*! MATCHSEL - Match Select */
67686 #define SCT_EV_CTRL_MATCHSEL(x)                  (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_MATCHSEL_SHIFT)) & SCT_EV_CTRL_MATCHSEL_MASK)
67687 
67688 #define SCT_EV_CTRL_HEVENT_MASK                  (0x10U)
67689 #define SCT_EV_CTRL_HEVENT_SHIFT                 (4U)
67690 /*! HEVENT - High Event
67691  *  0b0..Low counter (selects the L state and the L match register that the MATCHSEL field specifies)
67692  *  0b1..High counter (selects the H state and the H match register that the MATCHSEL field specifies)
67693  */
67694 #define SCT_EV_CTRL_HEVENT(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_HEVENT_SHIFT)) & SCT_EV_CTRL_HEVENT_MASK)
67695 
67696 #define SCT_EV_CTRL_OUTSEL_MASK                  (0x20U)
67697 #define SCT_EV_CTRL_OUTSEL_SHIFT                 (5U)
67698 /*! OUTSEL - Input and Output Select
67699  *  0b0..Inputs
67700  *  0b1..Outputs
67701  */
67702 #define SCT_EV_CTRL_OUTSEL(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_OUTSEL_SHIFT)) & SCT_EV_CTRL_OUTSEL_MASK)
67703 
67704 #define SCT_EV_CTRL_IOSEL_MASK                   (0x3C0U)
67705 #define SCT_EV_CTRL_IOSEL_SHIFT                  (6U)
67706 /*! IOSEL - Input or Output Signal Select */
67707 #define SCT_EV_CTRL_IOSEL(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_IOSEL_SHIFT)) & SCT_EV_CTRL_IOSEL_MASK)
67708 
67709 #define SCT_EV_CTRL_IOCOND_MASK                  (0xC00U)
67710 #define SCT_EV_CTRL_IOCOND_SHIFT                 (10U)
67711 /*! IOCOND - Input or Output Condition
67712  *  0b00..Low
67713  *  0b01..Rise
67714  *  0b10..Fall
67715  *  0b11..High
67716  */
67717 #define SCT_EV_CTRL_IOCOND(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_IOCOND_SHIFT)) & SCT_EV_CTRL_IOCOND_MASK)
67718 
67719 #define SCT_EV_CTRL_COMBMODE_MASK                (0x3000U)
67720 #define SCT_EV_CTRL_COMBMODE_SHIFT               (12U)
67721 /*! COMBMODE - Combination Mode
67722  *  0b00..OR (the event occurs when either the specified match or I/O condition occurs)
67723  *  0b01..MATCH (uses the specified match only)
67724  *  0b10..IO (uses the specified I/O condition only)
67725  *  0b11..AND (the event occurs when the specified match and I/O condition occur simultaneously)
67726  */
67727 #define SCT_EV_CTRL_COMBMODE(x)                  (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_COMBMODE_SHIFT)) & SCT_EV_CTRL_COMBMODE_MASK)
67728 
67729 #define SCT_EV_CTRL_STATELD_MASK                 (0x4000U)
67730 #define SCT_EV_CTRL_STATELD_SHIFT                (14U)
67731 /*! STATELD - State Load
67732  *  0b0..Value of STATEV added to that of STATE (the carry out is ignored)
67733  *  0b1..Value of STATEV loaded into that of STATE
67734  */
67735 #define SCT_EV_CTRL_STATELD(x)                   (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_STATELD_SHIFT)) & SCT_EV_CTRL_STATELD_MASK)
67736 
67737 #define SCT_EV_CTRL_STATEV_MASK                  (0xF8000U)
67738 #define SCT_EV_CTRL_STATEV_SHIFT                 (15U)
67739 /*! STATEV - State Value */
67740 #define SCT_EV_CTRL_STATEV(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_STATEV_SHIFT)) & SCT_EV_CTRL_STATEV_MASK)
67741 
67742 #define SCT_EV_CTRL_MATCHMEM_MASK                (0x100000U)
67743 #define SCT_EV_CTRL_MATCHMEM_SHIFT               (20U)
67744 /*! MATCHMEM - Match Mem */
67745 #define SCT_EV_CTRL_MATCHMEM(x)                  (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_MATCHMEM_SHIFT)) & SCT_EV_CTRL_MATCHMEM_MASK)
67746 
67747 #define SCT_EV_CTRL_DIRECTION_MASK               (0x600000U)
67748 #define SCT_EV_CTRL_DIRECTION_SHIFT              (21U)
67749 /*! DIRECTION - Direction
67750  *  0b00..Direction independent (event triggered regardless of the count direction)
67751  *  0b01..Counting up (event triggered only during up-counting when CTRL[BIDIR] = 1)
67752  *  0b10..Counting down (event triggered only during down-counting when CTRL[BIDIR] = 1)
67753  *  0b11..Reserved
67754  */
67755 #define SCT_EV_CTRL_DIRECTION(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_DIRECTION_SHIFT)) & SCT_EV_CTRL_DIRECTION_MASK)
67756 /*! @} */
67757 
67758 /* The count of SCT_EV_CTRL */
67759 #define SCT_EV_CTRL_COUNT                        (16U)
67760 
67761 /*! @name OUT_SET - Output n Set */
67762 /*! @{ */
67763 
67764 #define SCT_OUT_SET_SET_MASK                     (0xFFFFU)
67765 #define SCT_OUT_SET_SET_SHIFT                    (0U)
67766 /*! SET - Set Output */
67767 #define SCT_OUT_SET_SET(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_OUT_SET_SET_SHIFT)) & SCT_OUT_SET_SET_MASK)
67768 /*! @} */
67769 
67770 /* The count of SCT_OUT_SET */
67771 #define SCT_OUT_SET_COUNT                        (10U)
67772 
67773 /*! @name OUT_CLR - Output n Clear */
67774 /*! @{ */
67775 
67776 #define SCT_OUT_CLR_CLR_MASK                     (0xFFFFU)
67777 #define SCT_OUT_CLR_CLR_SHIFT                    (0U)
67778 /*! CLR - Clear Output */
67779 #define SCT_OUT_CLR_CLR(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_OUT_CLR_CLR_SHIFT)) & SCT_OUT_CLR_CLR_MASK)
67780 /*! @} */
67781 
67782 /* The count of SCT_OUT_CLR */
67783 #define SCT_OUT_CLR_COUNT                        (10U)
67784 
67785 
67786 /*!
67787  * @}
67788  */ /* end of group SCT_Register_Masks */
67789 
67790 
67791 /* SCT - Peripheral instance base addresses */
67792 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
67793   /** Peripheral SCT0 base address */
67794   #define SCT0_BASE                                (0x50091000u)
67795   /** Peripheral SCT0 base address */
67796   #define SCT0_BASE_NS                             (0x40091000u)
67797   /** Peripheral SCT0 base pointer */
67798   #define SCT0                                     ((SCT_Type *)SCT0_BASE)
67799   /** Peripheral SCT0 base pointer */
67800   #define SCT0_NS                                  ((SCT_Type *)SCT0_BASE_NS)
67801   /** Array initializer of SCT peripheral base addresses */
67802   #define SCT_BASE_ADDRS                           { SCT0_BASE }
67803   /** Array initializer of SCT peripheral base pointers */
67804   #define SCT_BASE_PTRS                            { SCT0 }
67805   /** Array initializer of SCT peripheral base addresses */
67806   #define SCT_BASE_ADDRS_NS                        { SCT0_BASE_NS }
67807   /** Array initializer of SCT peripheral base pointers */
67808   #define SCT_BASE_PTRS_NS                         { SCT0_NS }
67809 #else
67810   /** Peripheral SCT0 base address */
67811   #define SCT0_BASE                                (0x40091000u)
67812   /** Peripheral SCT0 base pointer */
67813   #define SCT0                                     ((SCT_Type *)SCT0_BASE)
67814   /** Array initializer of SCT peripheral base addresses */
67815   #define SCT_BASE_ADDRS                           { SCT0_BASE }
67816   /** Array initializer of SCT peripheral base pointers */
67817   #define SCT_BASE_PTRS                            { SCT0 }
67818 #endif
67819 /** Interrupt vectors for the SCT peripheral type */
67820 #define SCT_IRQS                                 { SCT0_IRQn }
67821 
67822 /*!
67823  * @}
67824  */ /* end of group SCT_Peripheral_Access_Layer */
67825 
67826 
67827 /* ----------------------------------------------------------------------------
67828    -- SEMA42 Peripheral Access Layer
67829    ---------------------------------------------------------------------------- */
67830 
67831 /*!
67832  * @addtogroup SEMA42_Peripheral_Access_Layer SEMA42 Peripheral Access Layer
67833  * @{
67834  */
67835 
67836 /** SEMA42 - Register Layout Typedef */
67837 typedef struct {
67838   __IO uint8_t GATE3;                              /**< Gate, offset: 0x0 */
67839   __IO uint8_t GATE2;                              /**< Gate, offset: 0x1 */
67840   __IO uint8_t GATE1;                              /**< Gate, offset: 0x2 */
67841   __IO uint8_t GATE0;                              /**< Gate, offset: 0x3 */
67842   __IO uint8_t GATE7;                              /**< Gate, offset: 0x4 */
67843   __IO uint8_t GATE6;                              /**< Gate, offset: 0x5 */
67844   __IO uint8_t GATE5;                              /**< Gate, offset: 0x6 */
67845   __IO uint8_t GATE4;                              /**< Gate, offset: 0x7 */
67846   __IO uint8_t GATE11;                             /**< Gate, offset: 0x8 */
67847   __IO uint8_t GATE10;                             /**< Gate, offset: 0x9 */
67848   __IO uint8_t GATE9;                              /**< Gate, offset: 0xA */
67849   __IO uint8_t GATE8;                              /**< Gate, offset: 0xB */
67850   __IO uint8_t GATE15;                             /**< Gate, offset: 0xC */
67851   __IO uint8_t GATE14;                             /**< Gate, offset: 0xD */
67852   __IO uint8_t GATE13;                             /**< Gate, offset: 0xE */
67853   __IO uint8_t GATE12;                             /**< Gate, offset: 0xF */
67854        uint8_t RESERVED_0[50];
67855   union {                                          /* offset: 0x42 */
67856     __I  uint16_t RSTGT_R;                           /**< Reset Gate Read, offset: 0x42 */
67857     __O  uint16_t RSTGT_W;                           /**< Reset Gate Write, offset: 0x42 */
67858   };
67859 } SEMA42_Type;
67860 
67861 /* ----------------------------------------------------------------------------
67862    -- SEMA42 Register Masks
67863    ---------------------------------------------------------------------------- */
67864 
67865 /*!
67866  * @addtogroup SEMA42_Register_Masks SEMA42 Register Masks
67867  * @{
67868  */
67869 
67870 /*! @name GATE3 - Gate */
67871 /*! @{ */
67872 
67873 #define SEMA42_GATE3_GTFSM_MASK                  (0xFU)
67874 #define SEMA42_GATE3_GTFSM_SHIFT                 (0U)
67875 /*! GTFSM - Gate Finite State Machine
67876  *  0b0000..The gate is unlocked (free).
67877  *  0b0001..Domain 0 locked the gate.
67878  *  0b0010..Domain 1 locked the gate.
67879  *  0b0011..Domain 2 locked the gate.
67880  *  0b0100..Domain 3 locked the gate.
67881  *  0b0101..Domain 4 locked the gate.
67882  *  0b0110..Domain 5 locked the gate.
67883  *  0b0111..Domain 6 locked the gate.
67884  *  0b1000..Domain 7 locked the gate.
67885  *  0b1001..Domain 8 locked the gate.
67886  *  0b1010..Domain 9 locked the gate.
67887  *  0b1011..Domain 10 locked the gate.
67888  *  0b1100..Domain 11 locked the gate.
67889  *  0b1101..Domain 12 locked the gate.
67890  *  0b1110..Domain 13 locked the gate.
67891  *  0b1111..Domain 14 locked the gate.
67892  */
67893 #define SEMA42_GATE3_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE3_GTFSM_SHIFT)) & SEMA42_GATE3_GTFSM_MASK)
67894 /*! @} */
67895 
67896 /*! @name GATE2 - Gate */
67897 /*! @{ */
67898 
67899 #define SEMA42_GATE2_GTFSM_MASK                  (0xFU)
67900 #define SEMA42_GATE2_GTFSM_SHIFT                 (0U)
67901 /*! GTFSM - Gate Finite State Machine
67902  *  0b0000..The gate is unlocked (free).
67903  *  0b0001..Domain 0 locked the gate.
67904  *  0b0010..Domain 1 locked the gate.
67905  *  0b0011..Domain 2 locked the gate.
67906  *  0b0100..Domain 3 locked the gate.
67907  *  0b0101..Domain 4 locked the gate.
67908  *  0b0110..Domain 5 locked the gate.
67909  *  0b0111..Domain 6 locked the gate.
67910  *  0b1000..Domain 7 locked the gate.
67911  *  0b1001..Domain 8 locked the gate.
67912  *  0b1010..Domain 9 locked the gate.
67913  *  0b1011..Domain 10 locked the gate.
67914  *  0b1100..Domain 11 locked the gate.
67915  *  0b1101..Domain 12 locked the gate.
67916  *  0b1110..Domain 13 locked the gate.
67917  *  0b1111..Domain 14 locked the gate.
67918  */
67919 #define SEMA42_GATE2_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE2_GTFSM_SHIFT)) & SEMA42_GATE2_GTFSM_MASK)
67920 /*! @} */
67921 
67922 /*! @name GATE1 - Gate */
67923 /*! @{ */
67924 
67925 #define SEMA42_GATE1_GTFSM_MASK                  (0xFU)
67926 #define SEMA42_GATE1_GTFSM_SHIFT                 (0U)
67927 /*! GTFSM - Gate Finite State Machine
67928  *  0b0000..The gate is unlocked (free).
67929  *  0b0001..Domain 0 locked the gate.
67930  *  0b0010..Domain 1 locked the gate.
67931  *  0b0011..Domain 2 locked the gate.
67932  *  0b0100..Domain 3 locked the gate.
67933  *  0b0101..Domain 4 locked the gate.
67934  *  0b0110..Domain 5 locked the gate.
67935  *  0b0111..Domain 6 locked the gate.
67936  *  0b1000..Domain 7 locked the gate.
67937  *  0b1001..Domain 8 locked the gate.
67938  *  0b1010..Domain 9 locked the gate.
67939  *  0b1011..Domain 10 locked the gate.
67940  *  0b1100..Domain 11 locked the gate.
67941  *  0b1101..Domain 12 locked the gate.
67942  *  0b1110..Domain 13 locked the gate.
67943  *  0b1111..Domain 14 locked the gate.
67944  */
67945 #define SEMA42_GATE1_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE1_GTFSM_SHIFT)) & SEMA42_GATE1_GTFSM_MASK)
67946 /*! @} */
67947 
67948 /*! @name GATE0 - Gate */
67949 /*! @{ */
67950 
67951 #define SEMA42_GATE0_GTFSM_MASK                  (0xFU)
67952 #define SEMA42_GATE0_GTFSM_SHIFT                 (0U)
67953 /*! GTFSM - Gate Finite State Machine
67954  *  0b0000..The gate is unlocked (free).
67955  *  0b0001..Domain 0 locked the gate.
67956  *  0b0010..Domain 1 locked the gate.
67957  *  0b0011..Domain 2 locked the gate.
67958  *  0b0100..Domain 3 locked the gate.
67959  *  0b0101..Domain 4 locked the gate.
67960  *  0b0110..Domain 5 locked the gate.
67961  *  0b0111..Domain 6 locked the gate.
67962  *  0b1000..Domain 7 locked the gate.
67963  *  0b1001..Domain 8 locked the gate.
67964  *  0b1010..Domain 9 locked the gate.
67965  *  0b1011..Domain 10 locked the gate.
67966  *  0b1100..Domain 11 locked the gate.
67967  *  0b1101..Domain 12 locked the gate.
67968  *  0b1110..Domain 13 locked the gate.
67969  *  0b1111..Domain 14 locked the gate.
67970  */
67971 #define SEMA42_GATE0_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE0_GTFSM_SHIFT)) & SEMA42_GATE0_GTFSM_MASK)
67972 /*! @} */
67973 
67974 /*! @name GATE7 - Gate */
67975 /*! @{ */
67976 
67977 #define SEMA42_GATE7_GTFSM_MASK                  (0xFU)
67978 #define SEMA42_GATE7_GTFSM_SHIFT                 (0U)
67979 /*! GTFSM - Gate Finite State Machine
67980  *  0b0000..The gate is unlocked (free).
67981  *  0b0001..Domain 0 locked the gate.
67982  *  0b0010..Domain 1 locked the gate.
67983  *  0b0011..Domain 2 locked the gate.
67984  *  0b0100..Domain 3 locked the gate.
67985  *  0b0101..Domain 4 locked the gate.
67986  *  0b0110..Domain 5 locked the gate.
67987  *  0b0111..Domain 6 locked the gate.
67988  *  0b1000..Domain 7 locked the gate.
67989  *  0b1001..Domain 8 locked the gate.
67990  *  0b1010..Domain 9 locked the gate.
67991  *  0b1011..Domain 10 locked the gate.
67992  *  0b1100..Domain 11 locked the gate.
67993  *  0b1101..Domain 12 locked the gate.
67994  *  0b1110..Domain 13 locked the gate.
67995  *  0b1111..Domain 14 locked the gate.
67996  */
67997 #define SEMA42_GATE7_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE7_GTFSM_SHIFT)) & SEMA42_GATE7_GTFSM_MASK)
67998 /*! @} */
67999 
68000 /*! @name GATE6 - Gate */
68001 /*! @{ */
68002 
68003 #define SEMA42_GATE6_GTFSM_MASK                  (0xFU)
68004 #define SEMA42_GATE6_GTFSM_SHIFT                 (0U)
68005 /*! GTFSM - Gate Finite State Machine
68006  *  0b0000..The gate is unlocked (free).
68007  *  0b0001..Domain 0 locked the gate.
68008  *  0b0010..Domain 1 locked the gate.
68009  *  0b0011..Domain 2 locked the gate.
68010  *  0b0100..Domain 3 locked the gate.
68011  *  0b0101..Domain 4 locked the gate.
68012  *  0b0110..Domain 5 locked the gate.
68013  *  0b0111..Domain 6 locked the gate.
68014  *  0b1000..Domain 7 locked the gate.
68015  *  0b1001..Domain 8 locked the gate.
68016  *  0b1010..Domain 9 locked the gate.
68017  *  0b1011..Domain 10 locked the gate.
68018  *  0b1100..Domain 11 locked the gate.
68019  *  0b1101..Domain 12 locked the gate.
68020  *  0b1110..Domain 13 locked the gate.
68021  *  0b1111..Domain 14 locked the gate.
68022  */
68023 #define SEMA42_GATE6_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE6_GTFSM_SHIFT)) & SEMA42_GATE6_GTFSM_MASK)
68024 /*! @} */
68025 
68026 /*! @name GATE5 - Gate */
68027 /*! @{ */
68028 
68029 #define SEMA42_GATE5_GTFSM_MASK                  (0xFU)
68030 #define SEMA42_GATE5_GTFSM_SHIFT                 (0U)
68031 /*! GTFSM - Gate Finite State Machine
68032  *  0b0000..The gate is unlocked (free).
68033  *  0b0001..Domain 0 locked the gate.
68034  *  0b0010..Domain 1 locked the gate.
68035  *  0b0011..Domain 2 locked the gate.
68036  *  0b0100..Domain 3 locked the gate.
68037  *  0b0101..Domain 4 locked the gate.
68038  *  0b0110..Domain 5 locked the gate.
68039  *  0b0111..Domain 6 locked the gate.
68040  *  0b1000..Domain 7 locked the gate.
68041  *  0b1001..Domain 8 locked the gate.
68042  *  0b1010..Domain 9 locked the gate.
68043  *  0b1011..Domain 10 locked the gate.
68044  *  0b1100..Domain 11 locked the gate.
68045  *  0b1101..Domain 12 locked the gate.
68046  *  0b1110..Domain 13 locked the gate.
68047  *  0b1111..Domain 14 locked the gate.
68048  */
68049 #define SEMA42_GATE5_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE5_GTFSM_SHIFT)) & SEMA42_GATE5_GTFSM_MASK)
68050 /*! @} */
68051 
68052 /*! @name GATE4 - Gate */
68053 /*! @{ */
68054 
68055 #define SEMA42_GATE4_GTFSM_MASK                  (0xFU)
68056 #define SEMA42_GATE4_GTFSM_SHIFT                 (0U)
68057 /*! GTFSM - Gate Finite State Machine
68058  *  0b0000..The gate is unlocked (free).
68059  *  0b0001..Domain 0 locked the gate.
68060  *  0b0010..Domain 1 locked the gate.
68061  *  0b0011..Domain 2 locked the gate.
68062  *  0b0100..Domain 3 locked the gate.
68063  *  0b0101..Domain 4 locked the gate.
68064  *  0b0110..Domain 5 locked the gate.
68065  *  0b0111..Domain 6 locked the gate.
68066  *  0b1000..Domain 7 locked the gate.
68067  *  0b1001..Domain 8 locked the gate.
68068  *  0b1010..Domain 9 locked the gate.
68069  *  0b1011..Domain 10 locked the gate.
68070  *  0b1100..Domain 11 locked the gate.
68071  *  0b1101..Domain 12 locked the gate.
68072  *  0b1110..Domain 13 locked the gate.
68073  *  0b1111..Domain 14 locked the gate.
68074  */
68075 #define SEMA42_GATE4_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE4_GTFSM_SHIFT)) & SEMA42_GATE4_GTFSM_MASK)
68076 /*! @} */
68077 
68078 /*! @name GATE11 - Gate */
68079 /*! @{ */
68080 
68081 #define SEMA42_GATE11_GTFSM_MASK                 (0xFU)
68082 #define SEMA42_GATE11_GTFSM_SHIFT                (0U)
68083 /*! GTFSM - Gate Finite State Machine
68084  *  0b0000..The gate is unlocked (free).
68085  *  0b0001..Domain 0 locked the gate.
68086  *  0b0010..Domain 1 locked the gate.
68087  *  0b0011..Domain 2 locked the gate.
68088  *  0b0100..Domain 3 locked the gate.
68089  *  0b0101..Domain 4 locked the gate.
68090  *  0b0110..Domain 5 locked the gate.
68091  *  0b0111..Domain 6 locked the gate.
68092  *  0b1000..Domain 7 locked the gate.
68093  *  0b1001..Domain 8 locked the gate.
68094  *  0b1010..Domain 9 locked the gate.
68095  *  0b1011..Domain 10 locked the gate.
68096  *  0b1100..Domain 11 locked the gate.
68097  *  0b1101..Domain 12 locked the gate.
68098  *  0b1110..Domain 13 locked the gate.
68099  *  0b1111..Domain 14 locked the gate.
68100  */
68101 #define SEMA42_GATE11_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE11_GTFSM_SHIFT)) & SEMA42_GATE11_GTFSM_MASK)
68102 /*! @} */
68103 
68104 /*! @name GATE10 - Gate */
68105 /*! @{ */
68106 
68107 #define SEMA42_GATE10_GTFSM_MASK                 (0xFU)
68108 #define SEMA42_GATE10_GTFSM_SHIFT                (0U)
68109 /*! GTFSM - Gate Finite State Machine
68110  *  0b0000..The gate is unlocked (free).
68111  *  0b0001..Domain 0 locked the gate.
68112  *  0b0010..Domain 1 locked the gate.
68113  *  0b0011..Domain 2 locked the gate.
68114  *  0b0100..Domain 3 locked the gate.
68115  *  0b0101..Domain 4 locked the gate.
68116  *  0b0110..Domain 5 locked the gate.
68117  *  0b0111..Domain 6 locked the gate.
68118  *  0b1000..Domain 7 locked the gate.
68119  *  0b1001..Domain 8 locked the gate.
68120  *  0b1010..Domain 9 locked the gate.
68121  *  0b1011..Domain 10 locked the gate.
68122  *  0b1100..Domain 11 locked the gate.
68123  *  0b1101..Domain 12 locked the gate.
68124  *  0b1110..Domain 13 locked the gate.
68125  *  0b1111..Domain 14 locked the gate.
68126  */
68127 #define SEMA42_GATE10_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE10_GTFSM_SHIFT)) & SEMA42_GATE10_GTFSM_MASK)
68128 /*! @} */
68129 
68130 /*! @name GATE9 - Gate */
68131 /*! @{ */
68132 
68133 #define SEMA42_GATE9_GTFSM_MASK                  (0xFU)
68134 #define SEMA42_GATE9_GTFSM_SHIFT                 (0U)
68135 /*! GTFSM - Gate Finite State Machine
68136  *  0b0000..The gate is unlocked (free).
68137  *  0b0001..Domain 0 locked the gate.
68138  *  0b0010..Domain 1 locked the gate.
68139  *  0b0011..Domain 2 locked the gate.
68140  *  0b0100..Domain 3 locked the gate.
68141  *  0b0101..Domain 4 locked the gate.
68142  *  0b0110..Domain 5 locked the gate.
68143  *  0b0111..Domain 6 locked the gate.
68144  *  0b1000..Domain 7 locked the gate.
68145  *  0b1001..Domain 8 locked the gate.
68146  *  0b1010..Domain 9 locked the gate.
68147  *  0b1011..Domain 10 locked the gate.
68148  *  0b1100..Domain 11 locked the gate.
68149  *  0b1101..Domain 12 locked the gate.
68150  *  0b1110..Domain 13 locked the gate.
68151  *  0b1111..Domain 14 locked the gate.
68152  */
68153 #define SEMA42_GATE9_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE9_GTFSM_SHIFT)) & SEMA42_GATE9_GTFSM_MASK)
68154 /*! @} */
68155 
68156 /*! @name GATE8 - Gate */
68157 /*! @{ */
68158 
68159 #define SEMA42_GATE8_GTFSM_MASK                  (0xFU)
68160 #define SEMA42_GATE8_GTFSM_SHIFT                 (0U)
68161 /*! GTFSM - Gate Finite State Machine
68162  *  0b0000..The gate is unlocked (free).
68163  *  0b0001..Domain 0 locked the gate.
68164  *  0b0010..Domain 1 locked the gate.
68165  *  0b0011..Domain 2 locked the gate.
68166  *  0b0100..Domain 3 locked the gate.
68167  *  0b0101..Domain 4 locked the gate.
68168  *  0b0110..Domain 5 locked the gate.
68169  *  0b0111..Domain 6 locked the gate.
68170  *  0b1000..Domain 7 locked the gate.
68171  *  0b1001..Domain 8 locked the gate.
68172  *  0b1010..Domain 9 locked the gate.
68173  *  0b1011..Domain 10 locked the gate.
68174  *  0b1100..Domain 11 locked the gate.
68175  *  0b1101..Domain 12 locked the gate.
68176  *  0b1110..Domain 13 locked the gate.
68177  *  0b1111..Domain 14 locked the gate.
68178  */
68179 #define SEMA42_GATE8_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE8_GTFSM_SHIFT)) & SEMA42_GATE8_GTFSM_MASK)
68180 /*! @} */
68181 
68182 /*! @name GATE15 - Gate */
68183 /*! @{ */
68184 
68185 #define SEMA42_GATE15_GTFSM_MASK                 (0xFU)
68186 #define SEMA42_GATE15_GTFSM_SHIFT                (0U)
68187 /*! GTFSM - Gate Finite State Machine
68188  *  0b0000..The gate is unlocked (free).
68189  *  0b0001..Domain 0 locked the gate.
68190  *  0b0010..Domain 1 locked the gate.
68191  *  0b0011..Domain 2 locked the gate.
68192  *  0b0100..Domain 3 locked the gate.
68193  *  0b0101..Domain 4 locked the gate.
68194  *  0b0110..Domain 5 locked the gate.
68195  *  0b0111..Domain 6 locked the gate.
68196  *  0b1000..Domain 7 locked the gate.
68197  *  0b1001..Domain 8 locked the gate.
68198  *  0b1010..Domain 9 locked the gate.
68199  *  0b1011..Domain 10 locked the gate.
68200  *  0b1100..Domain 11 locked the gate.
68201  *  0b1101..Domain 12 locked the gate.
68202  *  0b1110..Domain 13 locked the gate.
68203  *  0b1111..Domain 14 locked the gate.
68204  */
68205 #define SEMA42_GATE15_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE15_GTFSM_SHIFT)) & SEMA42_GATE15_GTFSM_MASK)
68206 /*! @} */
68207 
68208 /*! @name GATE14 - Gate */
68209 /*! @{ */
68210 
68211 #define SEMA42_GATE14_GTFSM_MASK                 (0xFU)
68212 #define SEMA42_GATE14_GTFSM_SHIFT                (0U)
68213 /*! GTFSM - Gate Finite State Machine
68214  *  0b0000..The gate is unlocked (free).
68215  *  0b0001..Domain 0 locked the gate.
68216  *  0b0010..Domain 1 locked the gate.
68217  *  0b0011..Domain 2 locked the gate.
68218  *  0b0100..Domain 3 locked the gate.
68219  *  0b0101..Domain 4 locked the gate.
68220  *  0b0110..Domain 5 locked the gate.
68221  *  0b0111..Domain 6 locked the gate.
68222  *  0b1000..Domain 7 locked the gate.
68223  *  0b1001..Domain 8 locked the gate.
68224  *  0b1010..Domain 9 locked the gate.
68225  *  0b1011..Domain 10 locked the gate.
68226  *  0b1100..Domain 11 locked the gate.
68227  *  0b1101..Domain 12 locked the gate.
68228  *  0b1110..Domain 13 locked the gate.
68229  *  0b1111..Domain 14 locked the gate.
68230  */
68231 #define SEMA42_GATE14_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE14_GTFSM_SHIFT)) & SEMA42_GATE14_GTFSM_MASK)
68232 /*! @} */
68233 
68234 /*! @name GATE13 - Gate */
68235 /*! @{ */
68236 
68237 #define SEMA42_GATE13_GTFSM_MASK                 (0xFU)
68238 #define SEMA42_GATE13_GTFSM_SHIFT                (0U)
68239 /*! GTFSM - Gate Finite State Machine
68240  *  0b0000..The gate is unlocked (free).
68241  *  0b0001..Domain 0 locked the gate.
68242  *  0b0010..Domain 1 locked the gate.
68243  *  0b0011..Domain 2 locked the gate.
68244  *  0b0100..Domain 3 locked the gate.
68245  *  0b0101..Domain 4 locked the gate.
68246  *  0b0110..Domain 5 locked the gate.
68247  *  0b0111..Domain 6 locked the gate.
68248  *  0b1000..Domain 7 locked the gate.
68249  *  0b1001..Domain 8 locked the gate.
68250  *  0b1010..Domain 9 locked the gate.
68251  *  0b1011..Domain 10 locked the gate.
68252  *  0b1100..Domain 11 locked the gate.
68253  *  0b1101..Domain 12 locked the gate.
68254  *  0b1110..Domain 13 locked the gate.
68255  *  0b1111..Domain 14 locked the gate.
68256  */
68257 #define SEMA42_GATE13_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE13_GTFSM_SHIFT)) & SEMA42_GATE13_GTFSM_MASK)
68258 /*! @} */
68259 
68260 /*! @name GATE12 - Gate */
68261 /*! @{ */
68262 
68263 #define SEMA42_GATE12_GTFSM_MASK                 (0xFU)
68264 #define SEMA42_GATE12_GTFSM_SHIFT                (0U)
68265 /*! GTFSM - Gate Finite State Machine
68266  *  0b0000..The gate is unlocked (free).
68267  *  0b0001..Domain 0 locked the gate.
68268  *  0b0010..Domain 1 locked the gate.
68269  *  0b0011..Domain 2 locked the gate.
68270  *  0b0100..Domain 3 locked the gate.
68271  *  0b0101..Domain 4 locked the gate.
68272  *  0b0110..Domain 5 locked the gate.
68273  *  0b0111..Domain 6 locked the gate.
68274  *  0b1000..Domain 7 locked the gate.
68275  *  0b1001..Domain 8 locked the gate.
68276  *  0b1010..Domain 9 locked the gate.
68277  *  0b1011..Domain 10 locked the gate.
68278  *  0b1100..Domain 11 locked the gate.
68279  *  0b1101..Domain 12 locked the gate.
68280  *  0b1110..Domain 13 locked the gate.
68281  *  0b1111..Domain 14 locked the gate.
68282  */
68283 #define SEMA42_GATE12_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE12_GTFSM_SHIFT)) & SEMA42_GATE12_GTFSM_MASK)
68284 /*! @} */
68285 
68286 /*! @name RSTGT_R - Reset Gate Read */
68287 /*! @{ */
68288 
68289 #define SEMA42_RSTGT_R_RSTGTN_MASK               (0xFFU)
68290 #define SEMA42_RSTGT_R_RSTGTN_SHIFT              (0U)
68291 /*! RSTGTN - Reset Gate Number */
68292 #define SEMA42_RSTGT_R_RSTGTN(x)                 (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_R_RSTGTN_SHIFT)) & SEMA42_RSTGT_R_RSTGTN_MASK)
68293 
68294 #define SEMA42_RSTGT_R_RSTGMS_MASK               (0xF00U)
68295 #define SEMA42_RSTGT_R_RSTGMS_SHIFT              (8U)
68296 /*! RSTGMS - Reset Gate Domain */
68297 #define SEMA42_RSTGT_R_RSTGMS(x)                 (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_R_RSTGMS_SHIFT)) & SEMA42_RSTGT_R_RSTGMS_MASK)
68298 
68299 #define SEMA42_RSTGT_R_RSTGSM_MASK               (0x3000U)
68300 #define SEMA42_RSTGT_R_RSTGSM_SHIFT              (12U)
68301 /*! RSTGSM - Reset Gate Finite State Machine
68302  *  0b00..Idle, waiting for the first data pattern write.
68303  *  0b01..Waiting for the second data pattern write
68304  *  0b10..The 2-write sequence has completed. Generate the specified gate reset(s). After the reset is performed,
68305  *        this machine returns to the idle (waiting for first data pattern write) state.
68306  *  0b11..This state encoding is never used and therefore reserved.
68307  */
68308 #define SEMA42_RSTGT_R_RSTGSM(x)                 (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_R_RSTGSM_SHIFT)) & SEMA42_RSTGT_R_RSTGSM_MASK)
68309 /*! @} */
68310 
68311 /*! @name RSTGT_W - Reset Gate Write */
68312 /*! @{ */
68313 
68314 #define SEMA42_RSTGT_W_RSTGTN_MASK               (0xFFU)
68315 #define SEMA42_RSTGT_W_RSTGTN_SHIFT              (0U)
68316 /*! RSTGTN - Reset Gate Number */
68317 #define SEMA42_RSTGT_W_RSTGTN(x)                 (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_W_RSTGTN_SHIFT)) & SEMA42_RSTGT_W_RSTGTN_MASK)
68318 
68319 #define SEMA42_RSTGT_W_RSTGDP_MASK               (0xFF00U)
68320 #define SEMA42_RSTGT_W_RSTGDP_SHIFT              (8U)
68321 /*! RSTGDP - Reset Gate Data Pattern */
68322 #define SEMA42_RSTGT_W_RSTGDP(x)                 (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_W_RSTGDP_SHIFT)) & SEMA42_RSTGT_W_RSTGDP_MASK)
68323 /*! @} */
68324 
68325 
68326 /*!
68327  * @}
68328  */ /* end of group SEMA42_Register_Masks */
68329 
68330 
68331 /* SEMA42 - Peripheral instance base addresses */
68332 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
68333   /** Peripheral SEMA42_0 base address */
68334   #define SEMA42_0_BASE                            (0x500B1000u)
68335   /** Peripheral SEMA42_0 base address */
68336   #define SEMA42_0_BASE_NS                         (0x400B1000u)
68337   /** Peripheral SEMA42_0 base pointer */
68338   #define SEMA42_0                                 ((SEMA42_Type *)SEMA42_0_BASE)
68339   /** Peripheral SEMA42_0 base pointer */
68340   #define SEMA42_0_NS                              ((SEMA42_Type *)SEMA42_0_BASE_NS)
68341   /** Array initializer of SEMA42 peripheral base addresses */
68342   #define SEMA42_BASE_ADDRS                        { SEMA42_0_BASE }
68343   /** Array initializer of SEMA42 peripheral base pointers */
68344   #define SEMA42_BASE_PTRS                         { SEMA42_0 }
68345   /** Array initializer of SEMA42 peripheral base addresses */
68346   #define SEMA42_BASE_ADDRS_NS                     { SEMA42_0_BASE_NS }
68347   /** Array initializer of SEMA42 peripheral base pointers */
68348   #define SEMA42_BASE_PTRS_NS                      { SEMA42_0_NS }
68349 #else
68350   /** Peripheral SEMA42_0 base address */
68351   #define SEMA42_0_BASE                            (0x400B1000u)
68352   /** Peripheral SEMA42_0 base pointer */
68353   #define SEMA42_0                                 ((SEMA42_Type *)SEMA42_0_BASE)
68354   /** Array initializer of SEMA42 peripheral base addresses */
68355   #define SEMA42_BASE_ADDRS                        { SEMA42_0_BASE }
68356   /** Array initializer of SEMA42 peripheral base pointers */
68357   #define SEMA42_BASE_PTRS                         { SEMA42_0 }
68358 #endif
68359 
68360 /*!
68361  * @}
68362  */ /* end of group SEMA42_Peripheral_Access_Layer */
68363 
68364 
68365 /* ----------------------------------------------------------------------------
68366    -- SMARTDMA Peripheral Access Layer
68367    ---------------------------------------------------------------------------- */
68368 
68369 /*!
68370  * @addtogroup SMARTDMA_Peripheral_Access_Layer SMARTDMA Peripheral Access Layer
68371  * @{
68372  */
68373 
68374 /** SMARTDMA - Register Layout Typedef */
68375 typedef struct {
68376        uint8_t RESERVED_0[32];
68377   __IO uint32_t BOOTADR;                           /**< Boot Address, offset: 0x20 */
68378   __IO uint32_t CTRL;                              /**< Control, offset: 0x24 */
68379   __I  uint32_t PC;                                /**< Program Counter, offset: 0x28 */
68380   __I  uint32_t SP;                                /**< Stack Pointer, offset: 0x2C */
68381   __IO uint32_t BREAK_ADDR;                        /**< Breakpoint Address, offset: 0x30 */
68382   __IO uint32_t BREAK_VECT;                        /**< Breakpoint Vector, offset: 0x34 */
68383   __IO uint32_t EMER_VECT;                         /**< Emergency Vector, offset: 0x38 */
68384   __IO uint32_t EMER_SEL;                          /**< Emergency Select, offset: 0x3C */
68385   __IO uint32_t ARM2EZH;                           /**< ARM to EZH Interrupt Control, offset: 0x40 */
68386   __IO uint32_t EZH2ARM;                           /**< EZH to ARM Trigger, offset: 0x44 */
68387   __IO uint32_t PENDTRAP;                          /**< Pending Trap Control, offset: 0x48 */
68388 } SMARTDMA_Type;
68389 
68390 /* ----------------------------------------------------------------------------
68391    -- SMARTDMA Register Masks
68392    ---------------------------------------------------------------------------- */
68393 
68394 /*!
68395  * @addtogroup SMARTDMA_Register_Masks SMARTDMA Register Masks
68396  * @{
68397  */
68398 
68399 /*! @name BOOTADR - Boot Address */
68400 /*! @{ */
68401 
68402 #define SMARTDMA_BOOTADR_ADDR_MASK               (0xFFFFFFFCU)
68403 #define SMARTDMA_BOOTADR_ADDR_SHIFT              (2U)
68404 /*! ADDR - 32-bit boot address, the boot address should be 4-byte aligned. */
68405 #define SMARTDMA_BOOTADR_ADDR(x)                 (((uint32_t)(((uint32_t)(x)) << SMARTDMA_BOOTADR_ADDR_SHIFT)) & SMARTDMA_BOOTADR_ADDR_MASK)
68406 /*! @} */
68407 
68408 /*! @name CTRL - Control */
68409 /*! @{ */
68410 
68411 #define SMARTDMA_CTRL_START_MASK                 (0x1U)
68412 #define SMARTDMA_CTRL_START_SHIFT                (0U)
68413 /*! START - Start Bit Ignition */
68414 #define SMARTDMA_CTRL_START(x)                   (((uint32_t)(((uint32_t)(x)) << SMARTDMA_CTRL_START_SHIFT)) & SMARTDMA_CTRL_START_MASK)
68415 
68416 #define SMARTDMA_CTRL_EXF_MASK                   (0x2U)
68417 #define SMARTDMA_CTRL_EXF_SHIFT                  (1U)
68418 /*! EXF - External Flag */
68419 #define SMARTDMA_CTRL_EXF(x)                     (((uint32_t)(((uint32_t)(x)) << SMARTDMA_CTRL_EXF_SHIFT)) & SMARTDMA_CTRL_EXF_MASK)
68420 
68421 #define SMARTDMA_CTRL_ERRDIS_MASK                (0x4U)
68422 #define SMARTDMA_CTRL_ERRDIS_SHIFT               (2U)
68423 /*! ERRDIS - Error Disable */
68424 #define SMARTDMA_CTRL_ERRDIS(x)                  (((uint32_t)(((uint32_t)(x)) << SMARTDMA_CTRL_ERRDIS_SHIFT)) & SMARTDMA_CTRL_ERRDIS_MASK)
68425 
68426 #define SMARTDMA_CTRL_BUFEN_MASK                 (0x8U)
68427 #define SMARTDMA_CTRL_BUFEN_SHIFT                (3U)
68428 /*! BUFEN - Buffer Enable */
68429 #define SMARTDMA_CTRL_BUFEN(x)                   (((uint32_t)(((uint32_t)(x)) << SMARTDMA_CTRL_BUFEN_SHIFT)) & SMARTDMA_CTRL_BUFEN_MASK)
68430 
68431 #define SMARTDMA_CTRL_SYNCEN_MASK                (0x10U)
68432 #define SMARTDMA_CTRL_SYNCEN_SHIFT               (4U)
68433 /*! SYNCEN - Sync Enable */
68434 #define SMARTDMA_CTRL_SYNCEN(x)                  (((uint32_t)(((uint32_t)(x)) << SMARTDMA_CTRL_SYNCEN_SHIFT)) & SMARTDMA_CTRL_SYNCEN_MASK)
68435 
68436 #define SMARTDMA_CTRL_WKEY_MASK                  (0xFFFF0000U)
68437 #define SMARTDMA_CTRL_WKEY_SHIFT                 (16U)
68438 /*! WKEY - Write Key */
68439 #define SMARTDMA_CTRL_WKEY(x)                    (((uint32_t)(((uint32_t)(x)) << SMARTDMA_CTRL_WKEY_SHIFT)) & SMARTDMA_CTRL_WKEY_MASK)
68440 /*! @} */
68441 
68442 /*! @name PC - Program Counter */
68443 /*! @{ */
68444 
68445 #define SMARTDMA_PC_PC_MASK                      (0xFFFFFFFFU)
68446 #define SMARTDMA_PC_PC_SHIFT                     (0U)
68447 /*! PC - Program Counter */
68448 #define SMARTDMA_PC_PC(x)                        (((uint32_t)(((uint32_t)(x)) << SMARTDMA_PC_PC_SHIFT)) & SMARTDMA_PC_PC_MASK)
68449 /*! @} */
68450 
68451 /*! @name SP - Stack Pointer */
68452 /*! @{ */
68453 
68454 #define SMARTDMA_SP_SP_MASK                      (0xFFFFFFFFU)
68455 #define SMARTDMA_SP_SP_SHIFT                     (0U)
68456 /*! SP - Stack Pointer */
68457 #define SMARTDMA_SP_SP(x)                        (((uint32_t)(((uint32_t)(x)) << SMARTDMA_SP_SP_SHIFT)) & SMARTDMA_SP_SP_MASK)
68458 /*! @} */
68459 
68460 /*! @name BREAK_ADDR - Breakpoint Address */
68461 /*! @{ */
68462 
68463 #define SMARTDMA_BREAK_ADDR_ADDR_MASK            (0xFFFFFFFCU)
68464 #define SMARTDMA_BREAK_ADDR_ADDR_SHIFT           (2U)
68465 /*! ADDR - 32-bit address to swap to EZHB_BREAK_VECT location */
68466 #define SMARTDMA_BREAK_ADDR_ADDR(x)              (((uint32_t)(((uint32_t)(x)) << SMARTDMA_BREAK_ADDR_ADDR_SHIFT)) & SMARTDMA_BREAK_ADDR_ADDR_MASK)
68467 /*! @} */
68468 
68469 /*! @name BREAK_VECT - Breakpoint Vector */
68470 /*! @{ */
68471 
68472 #define SMARTDMA_BREAK_VECT_VEC_MASK             (0xFFFFFFFCU)
68473 #define SMARTDMA_BREAK_VECT_VEC_SHIFT            (2U)
68474 /*! VEC - Vector address of user debug routine. */
68475 #define SMARTDMA_BREAK_VECT_VEC(x)               (((uint32_t)(((uint32_t)(x)) << SMARTDMA_BREAK_VECT_VEC_SHIFT)) & SMARTDMA_BREAK_VECT_VEC_MASK)
68476 /*! @} */
68477 
68478 /*! @name EMER_VECT - Emergency Vector */
68479 /*! @{ */
68480 
68481 #define SMARTDMA_EMER_VECT_VEC_MASK              (0xFFFFFFFCU)
68482 #define SMARTDMA_EMER_VECT_VEC_SHIFT             (2U)
68483 /*! VEC - Vector address of emergency code routine */
68484 #define SMARTDMA_EMER_VECT_VEC(x)                (((uint32_t)(((uint32_t)(x)) << SMARTDMA_EMER_VECT_VEC_SHIFT)) & SMARTDMA_EMER_VECT_VEC_MASK)
68485 /*! @} */
68486 
68487 /*! @name EMER_SEL - Emergency Select */
68488 /*! @{ */
68489 
68490 #define SMARTDMA_EMER_SEL_EN_MASK                (0x100U)
68491 #define SMARTDMA_EMER_SEL_EN_SHIFT               (8U)
68492 /*! EN - Emergency code routine */
68493 #define SMARTDMA_EMER_SEL_EN(x)                  (((uint32_t)(((uint32_t)(x)) << SMARTDMA_EMER_SEL_EN_SHIFT)) & SMARTDMA_EMER_SEL_EN_MASK)
68494 
68495 #define SMARTDMA_EMER_SEL_RQ_MASK                (0x200U)
68496 #define SMARTDMA_EMER_SEL_RQ_SHIFT               (9U)
68497 /*! RQ - Software emergency request */
68498 #define SMARTDMA_EMER_SEL_RQ(x)                  (((uint32_t)(((uint32_t)(x)) << SMARTDMA_EMER_SEL_RQ_SHIFT)) & SMARTDMA_EMER_SEL_RQ_MASK)
68499 /*! @} */
68500 
68501 /*! @name ARM2EZH - ARM to EZH Interrupt Control */
68502 /*! @{ */
68503 
68504 #define SMARTDMA_ARM2EZH_IE_MASK                 (0x3U)
68505 #define SMARTDMA_ARM2EZH_IE_SHIFT                (0U)
68506 /*! IE - Interrupt Enable */
68507 #define SMARTDMA_ARM2EZH_IE(x)                   (((uint32_t)(((uint32_t)(x)) << SMARTDMA_ARM2EZH_IE_SHIFT)) & SMARTDMA_ARM2EZH_IE_MASK)
68508 
68509 #define SMARTDMA_ARM2EZH_GP_MASK                 (0xFFFFFFFCU)
68510 #define SMARTDMA_ARM2EZH_GP_SHIFT                (2U)
68511 /*! GP - General purpose register bits */
68512 #define SMARTDMA_ARM2EZH_GP(x)                   (((uint32_t)(((uint32_t)(x)) << SMARTDMA_ARM2EZH_GP_SHIFT)) & SMARTDMA_ARM2EZH_GP_MASK)
68513 /*! @} */
68514 
68515 /*! @name EZH2ARM - EZH to ARM Trigger */
68516 /*! @{ */
68517 
68518 #define SMARTDMA_EZH2ARM_GP_MASK                 (0xFFFFFFFFU)
68519 #define SMARTDMA_EZH2ARM_GP_SHIFT                (0U)
68520 /*! GP - General purpose register bits Writing to EZH2ARM triggers the ARM interrupt when ARM2EZH [1:0] == 2h */
68521 #define SMARTDMA_EZH2ARM_GP(x)                   (((uint32_t)(((uint32_t)(x)) << SMARTDMA_EZH2ARM_GP_SHIFT)) & SMARTDMA_EZH2ARM_GP_MASK)
68522 /*! @} */
68523 
68524 /*! @name PENDTRAP - Pending Trap Control */
68525 /*! @{ */
68526 
68527 #define SMARTDMA_PENDTRAP_STATUS_MASK            (0xFFU)
68528 #define SMARTDMA_PENDTRAP_STATUS_SHIFT           (0U)
68529 /*! STATUS - Status Flag or Pending Trap Request */
68530 #define SMARTDMA_PENDTRAP_STATUS(x)              (((uint32_t)(((uint32_t)(x)) << SMARTDMA_PENDTRAP_STATUS_SHIFT)) & SMARTDMA_PENDTRAP_STATUS_MASK)
68531 
68532 #define SMARTDMA_PENDTRAP_POL_MASK               (0xFF00U)
68533 #define SMARTDMA_PENDTRAP_POL_SHIFT              (8U)
68534 /*! POL - Polarity */
68535 #define SMARTDMA_PENDTRAP_POL(x)                 (((uint32_t)(((uint32_t)(x)) << SMARTDMA_PENDTRAP_POL_SHIFT)) & SMARTDMA_PENDTRAP_POL_MASK)
68536 
68537 #define SMARTDMA_PENDTRAP_EN_MASK                (0xFF0000U)
68538 #define SMARTDMA_PENDTRAP_EN_SHIFT               (16U)
68539 /*! EN - Enable Pending Trap */
68540 #define SMARTDMA_PENDTRAP_EN(x)                  (((uint32_t)(((uint32_t)(x)) << SMARTDMA_PENDTRAP_EN_SHIFT)) & SMARTDMA_PENDTRAP_EN_MASK)
68541 /*! @} */
68542 
68543 
68544 /*!
68545  * @}
68546  */ /* end of group SMARTDMA_Register_Masks */
68547 
68548 
68549 /* SMARTDMA - Peripheral instance base addresses */
68550 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
68551   /** Peripheral SMARTDMA0 base address */
68552   #define SMARTDMA0_BASE                           (0x50033000u)
68553   /** Peripheral SMARTDMA0 base address */
68554   #define SMARTDMA0_BASE_NS                        (0x40033000u)
68555   /** Peripheral SMARTDMA0 base pointer */
68556   #define SMARTDMA0                                ((SMARTDMA_Type *)SMARTDMA0_BASE)
68557   /** Peripheral SMARTDMA0 base pointer */
68558   #define SMARTDMA0_NS                             ((SMARTDMA_Type *)SMARTDMA0_BASE_NS)
68559   /** Array initializer of SMARTDMA peripheral base addresses */
68560   #define SMARTDMA_BASE_ADDRS                      { SMARTDMA0_BASE }
68561   /** Array initializer of SMARTDMA peripheral base pointers */
68562   #define SMARTDMA_BASE_PTRS                       { SMARTDMA0 }
68563   /** Array initializer of SMARTDMA peripheral base addresses */
68564   #define SMARTDMA_BASE_ADDRS_NS                   { SMARTDMA0_BASE_NS }
68565   /** Array initializer of SMARTDMA peripheral base pointers */
68566   #define SMARTDMA_BASE_PTRS_NS                    { SMARTDMA0_NS }
68567 #else
68568   /** Peripheral SMARTDMA0 base address */
68569   #define SMARTDMA0_BASE                           (0x40033000u)
68570   /** Peripheral SMARTDMA0 base pointer */
68571   #define SMARTDMA0                                ((SMARTDMA_Type *)SMARTDMA0_BASE)
68572   /** Array initializer of SMARTDMA peripheral base addresses */
68573   #define SMARTDMA_BASE_ADDRS                      { SMARTDMA0_BASE }
68574   /** Array initializer of SMARTDMA peripheral base pointers */
68575   #define SMARTDMA_BASE_PTRS                       { SMARTDMA0 }
68576 #endif
68577 
68578 /*!
68579  * @}
68580  */ /* end of group SMARTDMA_Peripheral_Access_Layer */
68581 
68582 
68583 /* ----------------------------------------------------------------------------
68584    -- SPC Peripheral Access Layer
68585    ---------------------------------------------------------------------------- */
68586 
68587 /*!
68588  * @addtogroup SPC_Peripheral_Access_Layer SPC Peripheral Access Layer
68589  * @{
68590  */
68591 
68592 /** SPC - Register Layout Typedef */
68593 typedef struct {
68594   __I  uint32_t VERID;                             /**< Version ID, offset: 0x0 */
68595        uint8_t RESERVED_0[12];
68596   __IO uint32_t SC;                                /**< Status Control, offset: 0x10 */
68597   __IO uint32_t CNTRL;                             /**< SPC Regulator Control, offset: 0x14 */
68598        uint8_t RESERVED_1[4];
68599   __IO uint32_t LPREQ_CFG;                         /**< Low-Power Request Configuration, offset: 0x1C */
68600        uint8_t RESERVED_2[16];
68601   __IO uint32_t PD_STATUS[2];                      /**< SPC Power Domain Mode Status, array offset: 0x30, array step: 0x4 */
68602        uint8_t RESERVED_3[8];
68603   __IO uint32_t SRAMCTL;                           /**< SRAM Control, offset: 0x40 */
68604        uint8_t RESERVED_4[188];
68605   __IO uint32_t ACTIVE_CFG;                        /**< Active Power Mode Configuration, offset: 0x100 */
68606   __IO uint32_t ACTIVE_CFG1;                       /**< Active Power Mode Configuration 1, offset: 0x104 */
68607   __IO uint32_t LP_CFG;                            /**< Low-Power Mode Configuration, offset: 0x108 */
68608   __IO uint32_t LP_CFG1;                           /**< Low Power Mode Configuration 1, offset: 0x10C */
68609        uint8_t RESERVED_5[16];
68610   __IO uint32_t LPWKUP_DELAY;                      /**< Low Power Wake-Up Delay, offset: 0x120 */
68611   __IO uint32_t ACTIVE_VDELAY;                     /**< Active Voltage Trim Delay, offset: 0x124 */
68612        uint8_t RESERVED_6[8];
68613   __IO uint32_t VD_STAT;                           /**< Voltage Detect Status, offset: 0x130 */
68614   __IO uint32_t VD_CORE_CFG;                       /**< Core Voltage Detect Configuration, offset: 0x134 */
68615   __IO uint32_t VD_SYS_CFG;                        /**< System Voltage Detect Configuration, offset: 0x138 */
68616   __IO uint32_t VD_IO_CFG;                         /**< IO Voltage Detect Configuration, offset: 0x13C */
68617   __IO uint32_t EVD_CFG;                           /**< External Voltage Domain Configuration, offset: 0x140 */
68618   __IO uint32_t GLITCH_DETECT_SC;                  /**< Glitch Detect Status Control, offset: 0x144 */
68619        uint8_t RESERVED_7[440];
68620   __IO uint32_t CORELDO_CFG;                       /**< LDO_CORE Configuration, offset: 0x300 */
68621        uint8_t RESERVED_8[252];
68622   __IO uint32_t SYSLDO_CFG;                        /**< LDO_SYS Configuration, offset: 0x400 */
68623        uint8_t RESERVED_9[252];
68624   __IO uint32_t DCDC_CFG;                          /**< DCDC Configuration, offset: 0x500 */
68625   __IO uint32_t DCDC_BURST_CFG;                    /**< DCDC Burst Configuration, offset: 0x504 */
68626 } SPC_Type;
68627 
68628 /* ----------------------------------------------------------------------------
68629    -- SPC Register Masks
68630    ---------------------------------------------------------------------------- */
68631 
68632 /*!
68633  * @addtogroup SPC_Register_Masks SPC Register Masks
68634  * @{
68635  */
68636 
68637 /*! @name VERID - Version ID */
68638 /*! @{ */
68639 
68640 #define SPC_VERID_FEATURE_MASK                   (0xFFFFU)
68641 #define SPC_VERID_FEATURE_SHIFT                  (0U)
68642 /*! FEATURE - Feature Specification Number
68643  *  0b0000000000000000..Standard features
68644  *  *..
68645  */
68646 #define SPC_VERID_FEATURE(x)                     (((uint32_t)(((uint32_t)(x)) << SPC_VERID_FEATURE_SHIFT)) & SPC_VERID_FEATURE_MASK)
68647 
68648 #define SPC_VERID_MINOR_MASK                     (0xFF0000U)
68649 #define SPC_VERID_MINOR_SHIFT                    (16U)
68650 /*! MINOR - Minor Version Number */
68651 #define SPC_VERID_MINOR(x)                       (((uint32_t)(((uint32_t)(x)) << SPC_VERID_MINOR_SHIFT)) & SPC_VERID_MINOR_MASK)
68652 
68653 #define SPC_VERID_MAJOR_MASK                     (0xFF000000U)
68654 #define SPC_VERID_MAJOR_SHIFT                    (24U)
68655 /*! MAJOR - Major Version Number */
68656 #define SPC_VERID_MAJOR(x)                       (((uint32_t)(((uint32_t)(x)) << SPC_VERID_MAJOR_SHIFT)) & SPC_VERID_MAJOR_MASK)
68657 /*! @} */
68658 
68659 /*! @name SC - Status Control */
68660 /*! @{ */
68661 
68662 #define SPC_SC_BUSY_MASK                         (0x1U)
68663 #define SPC_SC_BUSY_SHIFT                        (0U)
68664 /*! BUSY - SPC Busy Status Flag
68665  *  0b0..Not busy
68666  *  0b1..Busy
68667  */
68668 #define SPC_SC_BUSY(x)                           (((uint32_t)(((uint32_t)(x)) << SPC_SC_BUSY_SHIFT)) & SPC_SC_BUSY_MASK)
68669 
68670 #define SPC_SC_SPC_LP_REQ_MASK                   (0x2U)
68671 #define SPC_SC_SPC_LP_REQ_SHIFT                  (1U)
68672 /*! SPC_LP_REQ - SPC Power Mode Configuration Status Flag
68673  *  0b0..SPC is in Active or Sleep mode; the ACTIVE_CFG register has control
68674  *  0b1..All power domains requested low-power mode; SPC entered a low-power state; power-mode configuration based on the LP_CFG register
68675  *  0b0..No effect
68676  *  0b1..Clear the flag
68677  */
68678 #define SPC_SC_SPC_LP_REQ(x)                     (((uint32_t)(((uint32_t)(x)) << SPC_SC_SPC_LP_REQ_SHIFT)) & SPC_SC_SPC_LP_REQ_MASK)
68679 
68680 #define SPC_SC_SPC_LP_MODE_MASK                  (0xF0U)
68681 #define SPC_SC_SPC_LP_MODE_SHIFT                 (4U)
68682 /*! SPC_LP_MODE - Power Domain Low-Power Mode Request
68683  *  0b0000..Sleep mode with system clock running
68684  *  0b0001..DSLEEP with system clock off
68685  *  0b0010..PDOWN with system clock off
68686  *  0b0100..
68687  *  0b1000..DPDOWN with system clock off
68688  */
68689 #define SPC_SC_SPC_LP_MODE(x)                    (((uint32_t)(((uint32_t)(x)) << SPC_SC_SPC_LP_MODE_SHIFT)) & SPC_SC_SPC_LP_MODE_MASK)
68690 
68691 #define SPC_SC_ISO_CLR_MASK                      (0x30000U)
68692 #define SPC_SC_ISO_CLR_SHIFT                     (16U)
68693 /*! ISO_CLR - Isolation Clear Flags */
68694 #define SPC_SC_ISO_CLR(x)                        (((uint32_t)(((uint32_t)(x)) << SPC_SC_ISO_CLR_SHIFT)) & SPC_SC_ISO_CLR_MASK)
68695 /*! @} */
68696 
68697 /*! @name CNTRL - SPC Regulator Control */
68698 /*! @{ */
68699 
68700 #define SPC_CNTRL_CORELDO_EN_MASK                (0x1U)
68701 #define SPC_CNTRL_CORELDO_EN_SHIFT               (0U)
68702 /*! CORELDO_EN - LDO_CORE Regulator Enable
68703  *  0b0..Disable
68704  *  0b1..Enable
68705  */
68706 #define SPC_CNTRL_CORELDO_EN(x)                  (((uint32_t)(((uint32_t)(x)) << SPC_CNTRL_CORELDO_EN_SHIFT)) & SPC_CNTRL_CORELDO_EN_MASK)
68707 
68708 #define SPC_CNTRL_SYSLDO_EN_MASK                 (0x2U)
68709 #define SPC_CNTRL_SYSLDO_EN_SHIFT                (1U)
68710 /*! SYSLDO_EN - LDO_SYS Regulator Enable
68711  *  0b0..Disable
68712  *  0b1..Enable
68713  */
68714 #define SPC_CNTRL_SYSLDO_EN(x)                   (((uint32_t)(((uint32_t)(x)) << SPC_CNTRL_SYSLDO_EN_SHIFT)) & SPC_CNTRL_SYSLDO_EN_MASK)
68715 
68716 #define SPC_CNTRL_DCDC_EN_MASK                   (0x4U)
68717 #define SPC_CNTRL_DCDC_EN_SHIFT                  (2U)
68718 /*! DCDC_EN - DCDC_CORE Regulator Enable
68719  *  0b0..Disable
68720  *  0b1..Enable
68721  */
68722 #define SPC_CNTRL_DCDC_EN(x)                     (((uint32_t)(((uint32_t)(x)) << SPC_CNTRL_DCDC_EN_SHIFT)) & SPC_CNTRL_DCDC_EN_MASK)
68723 /*! @} */
68724 
68725 /*! @name LPREQ_CFG - Low-Power Request Configuration */
68726 /*! @{ */
68727 
68728 #define SPC_LPREQ_CFG_LPREQOE_MASK               (0x1U)
68729 #define SPC_LPREQ_CFG_LPREQOE_SHIFT              (0U)
68730 /*! LPREQOE - Low-Power Request Output Enable
68731  *  0b0..Disable
68732  *  0b1..Enable
68733  */
68734 #define SPC_LPREQ_CFG_LPREQOE(x)                 (((uint32_t)(((uint32_t)(x)) << SPC_LPREQ_CFG_LPREQOE_SHIFT)) & SPC_LPREQ_CFG_LPREQOE_MASK)
68735 
68736 #define SPC_LPREQ_CFG_LPREQPOL_MASK              (0x2U)
68737 #define SPC_LPREQ_CFG_LPREQPOL_SHIFT             (1U)
68738 /*! LPREQPOL - Low-Power Request Output Pin Polarity Control
68739  *  0b0..High
68740  *  0b1..Low
68741  */
68742 #define SPC_LPREQ_CFG_LPREQPOL(x)                (((uint32_t)(((uint32_t)(x)) << SPC_LPREQ_CFG_LPREQPOL_SHIFT)) & SPC_LPREQ_CFG_LPREQPOL_MASK)
68743 
68744 #define SPC_LPREQ_CFG_LPREQOV_MASK               (0xCU)
68745 #define SPC_LPREQ_CFG_LPREQOV_SHIFT              (2U)
68746 /*! LPREQOV - Low-Power Request Output Override
68747  *  0b00..Not forced
68748  *  0b01..
68749  *  0b10..Forced low (ignore LPREQPOL settings)
68750  *  0b11..Forced high (ignore LPREQPOL settings)
68751  */
68752 #define SPC_LPREQ_CFG_LPREQOV(x)                 (((uint32_t)(((uint32_t)(x)) << SPC_LPREQ_CFG_LPREQOV_SHIFT)) & SPC_LPREQ_CFG_LPREQOV_MASK)
68753 /*! @} */
68754 
68755 /*! @name PD_STATUS - SPC Power Domain Mode Status */
68756 /*! @{ */
68757 
68758 #define SPC_PD_STATUS_PWR_REQ_STATUS_MASK        (0x1U)
68759 #define SPC_PD_STATUS_PWR_REQ_STATUS_SHIFT       (0U)
68760 /*! PWR_REQ_STATUS - Power Request Status Flag
68761  *  0b0..Did not request
68762  *  0b1..Requested
68763  */
68764 #define SPC_PD_STATUS_PWR_REQ_STATUS(x)          (((uint32_t)(((uint32_t)(x)) << SPC_PD_STATUS_PWR_REQ_STATUS_SHIFT)) & SPC_PD_STATUS_PWR_REQ_STATUS_MASK)
68765 
68766 #define SPC_PD_STATUS_PD_LP_REQ_MASK             (0x10U)
68767 #define SPC_PD_STATUS_PD_LP_REQ_SHIFT            (4U)
68768 /*! PD_LP_REQ - Power Domain Low Power Request Flag
68769  *  0b0..Did not request
68770  *  0b1..Requested
68771  */
68772 #define SPC_PD_STATUS_PD_LP_REQ(x)               (((uint32_t)(((uint32_t)(x)) << SPC_PD_STATUS_PD_LP_REQ_SHIFT)) & SPC_PD_STATUS_PD_LP_REQ_MASK)
68773 
68774 #define SPC_PD_STATUS_LP_MODE_MASK               (0xF00U)
68775 #define SPC_PD_STATUS_LP_MODE_SHIFT              (8U)
68776 /*! LP_MODE - Power Domain Low Power Mode Request
68777  *  0b0000..SLEEP with system clock running
68778  *  0b0001..DSLEEP with system clock off
68779  *  0b0010..PDOWN with system clock off
68780  *  0b0100..
68781  *  0b1000..DPDOWN with system clock off
68782  */
68783 #define SPC_PD_STATUS_LP_MODE(x)                 (((uint32_t)(((uint32_t)(x)) << SPC_PD_STATUS_LP_MODE_SHIFT)) & SPC_PD_STATUS_LP_MODE_MASK)
68784 /*! @} */
68785 
68786 /* The count of SPC_PD_STATUS */
68787 #define SPC_PD_STATUS_COUNT                      (2U)
68788 
68789 /*! @name SRAMCTL - SRAM Control */
68790 /*! @{ */
68791 
68792 #define SPC_SRAMCTL_VSM_MASK                     (0x3U)
68793 #define SPC_SRAMCTL_VSM_SHIFT                    (0U)
68794 /*! VSM - Voltage Select Margin
68795  *  0b00..
68796  *  0b01..1.0 V
68797  *  0b10..1.1 V
68798  *  0b11..
68799  */
68800 #define SPC_SRAMCTL_VSM(x)                       (((uint32_t)(((uint32_t)(x)) << SPC_SRAMCTL_VSM_SHIFT)) & SPC_SRAMCTL_VSM_MASK)
68801 
68802 #define SPC_SRAMCTL_REQ_MASK                     (0x40000000U)
68803 #define SPC_SRAMCTL_REQ_SHIFT                    (30U)
68804 /*! REQ - SRAM Voltage Update Request
68805  *  0b0..Do not request
68806  *  0b1..Request
68807  */
68808 #define SPC_SRAMCTL_REQ(x)                       (((uint32_t)(((uint32_t)(x)) << SPC_SRAMCTL_REQ_SHIFT)) & SPC_SRAMCTL_REQ_MASK)
68809 
68810 #define SPC_SRAMCTL_ACK_MASK                     (0x80000000U)
68811 #define SPC_SRAMCTL_ACK_SHIFT                    (31U)
68812 /*! ACK - SRAM Voltage Update Request Acknowledge
68813  *  0b0..Not acknowledged
68814  *  0b1..Acknowledged
68815  */
68816 #define SPC_SRAMCTL_ACK(x)                       (((uint32_t)(((uint32_t)(x)) << SPC_SRAMCTL_ACK_SHIFT)) & SPC_SRAMCTL_ACK_MASK)
68817 /*! @} */
68818 
68819 /*! @name ACTIVE_CFG - Active Power Mode Configuration */
68820 /*! @{ */
68821 
68822 #define SPC_ACTIVE_CFG_CORELDO_VDD_DS_MASK       (0x1U)
68823 #define SPC_ACTIVE_CFG_CORELDO_VDD_DS_SHIFT      (0U)
68824 /*! CORELDO_VDD_DS - LDO_CORE VDD Drive Strength
68825  *  0b0..Low
68826  *  0b1..Normal
68827  */
68828 #define SPC_ACTIVE_CFG_CORELDO_VDD_DS(x)         (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_CORELDO_VDD_DS_SHIFT)) & SPC_ACTIVE_CFG_CORELDO_VDD_DS_MASK)
68829 
68830 #define SPC_ACTIVE_CFG_CORELDO_VDD_LVL_MASK      (0xCU)
68831 #define SPC_ACTIVE_CFG_CORELDO_VDD_LVL_SHIFT     (2U)
68832 /*! CORELDO_VDD_LVL - LDO_CORE VDD Regulator Voltage Level
68833  *  0b00..
68834  *  0b01..Regulate to mid voltage (1.0 V)
68835  *  0b10..Regulate to normal voltage (1.1 V)
68836  *  0b11..Regulate to overdrive voltage (1.2 V)
68837  */
68838 #define SPC_ACTIVE_CFG_CORELDO_VDD_LVL(x)        (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_CORELDO_VDD_LVL_SHIFT)) & SPC_ACTIVE_CFG_CORELDO_VDD_LVL_MASK)
68839 
68840 #define SPC_ACTIVE_CFG_SYSLDO_VDD_DS_MASK        (0x10U)
68841 #define SPC_ACTIVE_CFG_SYSLDO_VDD_DS_SHIFT       (4U)
68842 /*! SYSLDO_VDD_DS - LDO_SYS VDD Drive Strength
68843  *  0b0..Low
68844  *  0b1..Normal
68845  */
68846 #define SPC_ACTIVE_CFG_SYSLDO_VDD_DS(x)          (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_SYSLDO_VDD_DS_SHIFT)) & SPC_ACTIVE_CFG_SYSLDO_VDD_DS_MASK)
68847 
68848 #define SPC_ACTIVE_CFG_SYSLDO_VDD_LVL_MASK       (0x40U)
68849 #define SPC_ACTIVE_CFG_SYSLDO_VDD_LVL_SHIFT      (6U)
68850 /*! SYSLDO_VDD_LVL - LDO_SYS VDD Regulator Voltage Level
68851  *  0b0..Normal voltage (1.8 V)
68852  *  0b1..Overdrive voltage (2.5 V)
68853  */
68854 #define SPC_ACTIVE_CFG_SYSLDO_VDD_LVL(x)         (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_SYSLDO_VDD_LVL_SHIFT)) & SPC_ACTIVE_CFG_SYSLDO_VDD_LVL_MASK)
68855 
68856 #define SPC_ACTIVE_CFG_DCDC_VDD_DS_MASK          (0x300U)
68857 #define SPC_ACTIVE_CFG_DCDC_VDD_DS_SHIFT         (8U)
68858 /*! DCDC_VDD_DS - DCDC VDD Drive Strength
68859  *  0b01..Low
68860  *  0b10..Normal
68861  *  *..
68862  */
68863 #define SPC_ACTIVE_CFG_DCDC_VDD_DS(x)            (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_DCDC_VDD_DS_SHIFT)) & SPC_ACTIVE_CFG_DCDC_VDD_DS_MASK)
68864 
68865 #define SPC_ACTIVE_CFG_DCDC_VDD_LVL_MASK         (0xC00U)
68866 #define SPC_ACTIVE_CFG_DCDC_VDD_LVL_SHIFT        (10U)
68867 /*! DCDC_VDD_LVL - DCDC VDD Regulator Voltage Level
68868  *  0b00..Reserved
68869  *  0b01..Midvoltage (1.0 V)
68870  *  0b10..Normal voltage (1.1 V)
68871  *  0b11..Overdrive voltage (1.2 V)
68872  */
68873 #define SPC_ACTIVE_CFG_DCDC_VDD_LVL(x)           (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_DCDC_VDD_LVL_SHIFT)) & SPC_ACTIVE_CFG_DCDC_VDD_LVL_MASK)
68874 
68875 #define SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_MASK (0x1000U)
68876 #define SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_SHIFT (12U)
68877 /*! GLITCH_DETECT_DISABLE - Glitch Detect Disable
68878  *  0b0..Low Voltage Glitch Detect enabled
68879  *  0b1..Low Voltage Glitch Detect disabled
68880  */
68881 #define SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE(x)  (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_SHIFT)) & SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_MASK)
68882 
68883 #define SPC_ACTIVE_CFG_LPBUFF_EN_MASK            (0x40000U)
68884 #define SPC_ACTIVE_CFG_LPBUFF_EN_SHIFT           (18U)
68885 /*! LPBUFF_EN - CMP Bandgap Buffer Enable
68886  *  0b0..Disable
68887  *  0b1..Enable
68888  */
68889 #define SPC_ACTIVE_CFG_LPBUFF_EN(x)              (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_LPBUFF_EN_SHIFT)) & SPC_ACTIVE_CFG_LPBUFF_EN_MASK)
68890 
68891 #define SPC_ACTIVE_CFG_BGMODE_MASK               (0x300000U)
68892 #define SPC_ACTIVE_CFG_BGMODE_SHIFT              (20U)
68893 /*! BGMODE - Bandgap Mode
68894  *  0b00..Bandgap disabled
68895  *  0b01..Bandgap enabled, buffer disabled
68896  *  0b10..Bandgap enabled, buffer enabled
68897  *  0b11..
68898  */
68899 #define SPC_ACTIVE_CFG_BGMODE(x)                 (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_BGMODE_SHIFT)) & SPC_ACTIVE_CFG_BGMODE_MASK)
68900 
68901 #define SPC_ACTIVE_CFG_VDD_VD_DISABLE_MASK       (0x800000U)
68902 #define SPC_ACTIVE_CFG_VDD_VD_DISABLE_SHIFT      (23U)
68903 /*! VDD_VD_DISABLE - VDD Voltage Detect Disable
68904  *  0b0..Enable
68905  *  0b1..Disable
68906  */
68907 #define SPC_ACTIVE_CFG_VDD_VD_DISABLE(x)         (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_VDD_VD_DISABLE_SHIFT)) & SPC_ACTIVE_CFG_VDD_VD_DISABLE_MASK)
68908 
68909 #define SPC_ACTIVE_CFG_CORE_LVDE_MASK            (0x1000000U)
68910 #define SPC_ACTIVE_CFG_CORE_LVDE_SHIFT           (24U)
68911 /*! CORE_LVDE - Core Low-Voltage Detection Enable
68912  *  0b0..Disable
68913  *  0b1..Enable
68914  */
68915 #define SPC_ACTIVE_CFG_CORE_LVDE(x)              (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_CORE_LVDE_SHIFT)) & SPC_ACTIVE_CFG_CORE_LVDE_MASK)
68916 
68917 #define SPC_ACTIVE_CFG_SYS_LVDE_MASK             (0x2000000U)
68918 #define SPC_ACTIVE_CFG_SYS_LVDE_SHIFT            (25U)
68919 /*! SYS_LVDE - System Low-Voltage Detection Enable
68920  *  0b0..Disable
68921  *  0b1..Enable
68922  */
68923 #define SPC_ACTIVE_CFG_SYS_LVDE(x)               (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_SYS_LVDE_SHIFT)) & SPC_ACTIVE_CFG_SYS_LVDE_MASK)
68924 
68925 #define SPC_ACTIVE_CFG_IO_LVDE_MASK              (0x4000000U)
68926 #define SPC_ACTIVE_CFG_IO_LVDE_SHIFT             (26U)
68927 /*! IO_LVDE - IO Low-Voltage Detection Enable
68928  *  0b0..Disable
68929  *  0b1..Enable
68930  */
68931 #define SPC_ACTIVE_CFG_IO_LVDE(x)                (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_IO_LVDE_SHIFT)) & SPC_ACTIVE_CFG_IO_LVDE_MASK)
68932 
68933 #define SPC_ACTIVE_CFG_CORE_HVDE_MASK            (0x8000000U)
68934 #define SPC_ACTIVE_CFG_CORE_HVDE_SHIFT           (27U)
68935 /*! CORE_HVDE - Core High-Voltage Detection Enable
68936  *  0b0..Disable
68937  *  0b1..Enable
68938  */
68939 #define SPC_ACTIVE_CFG_CORE_HVDE(x)              (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_CORE_HVDE_SHIFT)) & SPC_ACTIVE_CFG_CORE_HVDE_MASK)
68940 
68941 #define SPC_ACTIVE_CFG_SYS_HVDE_MASK             (0x10000000U)
68942 #define SPC_ACTIVE_CFG_SYS_HVDE_SHIFT            (28U)
68943 /*! SYS_HVDE - System High-Voltage Detection Enable
68944  *  0b0..Disable
68945  *  0b1..Enable
68946  */
68947 #define SPC_ACTIVE_CFG_SYS_HVDE(x)               (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_SYS_HVDE_SHIFT)) & SPC_ACTIVE_CFG_SYS_HVDE_MASK)
68948 
68949 #define SPC_ACTIVE_CFG_IO_HVDE_MASK              (0x20000000U)
68950 #define SPC_ACTIVE_CFG_IO_HVDE_SHIFT             (29U)
68951 /*! IO_HVDE - IO High-Voltage Detection Enable
68952  *  0b0..Disable
68953  *  0b1..Enable
68954  */
68955 #define SPC_ACTIVE_CFG_IO_HVDE(x)                (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_IO_HVDE_SHIFT)) & SPC_ACTIVE_CFG_IO_HVDE_MASK)
68956 /*! @} */
68957 
68958 /*! @name ACTIVE_CFG1 - Active Power Mode Configuration 1 */
68959 /*! @{ */
68960 
68961 #define SPC_ACTIVE_CFG1_SOC_CNTRL_MASK           (0xFFFFFFFFU)
68962 #define SPC_ACTIVE_CFG1_SOC_CNTRL_SHIFT          (0U)
68963 /*! SOC_CNTRL - Active Config Chip Control */
68964 #define SPC_ACTIVE_CFG1_SOC_CNTRL(x)             (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG1_SOC_CNTRL_SHIFT)) & SPC_ACTIVE_CFG1_SOC_CNTRL_MASK)
68965 /*! @} */
68966 
68967 /*! @name LP_CFG - Low-Power Mode Configuration */
68968 /*! @{ */
68969 
68970 #define SPC_LP_CFG_CORELDO_VDD_DS_MASK           (0x1U)
68971 #define SPC_LP_CFG_CORELDO_VDD_DS_SHIFT          (0U)
68972 /*! CORELDO_VDD_DS - LDO_CORE VDD Drive Strength
68973  *  0b0..Low
68974  *  0b1..Normal
68975  */
68976 #define SPC_LP_CFG_CORELDO_VDD_DS(x)             (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_CORELDO_VDD_DS_SHIFT)) & SPC_LP_CFG_CORELDO_VDD_DS_MASK)
68977 
68978 #define SPC_LP_CFG_CORELDO_VDD_LVL_MASK          (0xCU)
68979 #define SPC_LP_CFG_CORELDO_VDD_LVL_SHIFT         (2U)
68980 /*! CORELDO_VDD_LVL - LDO_CORE VDD Regulator Voltage Level
68981  *  0b00..Retention voltage
68982  *  0b01..Mid voltage (1.0 V)
68983  *  0b10..Normal voltage (1.1 V)
68984  *  0b11..Overdrive voltage (1.2 V)
68985  */
68986 #define SPC_LP_CFG_CORELDO_VDD_LVL(x)            (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_CORELDO_VDD_LVL_SHIFT)) & SPC_LP_CFG_CORELDO_VDD_LVL_MASK)
68987 
68988 #define SPC_LP_CFG_SYSLDO_VDD_DS_MASK            (0x10U)
68989 #define SPC_LP_CFG_SYSLDO_VDD_DS_SHIFT           (4U)
68990 /*! SYSLDO_VDD_DS - LDO_SYS VDD Drive Strength
68991  *  0b0..Low
68992  *  0b1..Normal
68993  */
68994 #define SPC_LP_CFG_SYSLDO_VDD_DS(x)              (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_SYSLDO_VDD_DS_SHIFT)) & SPC_LP_CFG_SYSLDO_VDD_DS_MASK)
68995 
68996 #define SPC_LP_CFG_DCDC_VDD_DS_MASK              (0x300U)
68997 #define SPC_LP_CFG_DCDC_VDD_DS_SHIFT             (8U)
68998 /*! DCDC_VDD_DS - DCDC VDD Drive Strength
68999  *  0b00..Pulse refresh
69000  *  0b01..Low
69001  *  0b10..Normal
69002  *  0b11..
69003  */
69004 #define SPC_LP_CFG_DCDC_VDD_DS(x)                (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_DCDC_VDD_DS_SHIFT)) & SPC_LP_CFG_DCDC_VDD_DS_MASK)
69005 
69006 #define SPC_LP_CFG_DCDC_VDD_LVL_MASK             (0xC00U)
69007 #define SPC_LP_CFG_DCDC_VDD_LVL_SHIFT            (10U)
69008 /*! DCDC_VDD_LVL - DCDC VDD Regulator Voltage Level
69009  *  0b00..Retention voltage (0.7 V)
69010  *  0b01..Mid voltage (1.0 V)
69011  *  0b10..Normal voltage (1.1 V)
69012  *  0b11..Overdrive voltage (1.2 V)
69013  */
69014 #define SPC_LP_CFG_DCDC_VDD_LVL(x)               (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_DCDC_VDD_LVL_SHIFT)) & SPC_LP_CFG_DCDC_VDD_LVL_MASK)
69015 
69016 #define SPC_LP_CFG_GLITCH_DETECT_DISABLE_MASK    (0x1000U)
69017 #define SPC_LP_CFG_GLITCH_DETECT_DISABLE_SHIFT   (12U)
69018 /*! GLITCH_DETECT_DISABLE - Glitch Detect Disable
69019  *  0b0..Enable
69020  *  0b1..Disable
69021  */
69022 #define SPC_LP_CFG_GLITCH_DETECT_DISABLE(x)      (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_GLITCH_DETECT_DISABLE_SHIFT)) & SPC_LP_CFG_GLITCH_DETECT_DISABLE_MASK)
69023 
69024 #define SPC_LP_CFG_COREVDD_IVS_EN_MASK           (0x20000U)
69025 #define SPC_LP_CFG_COREVDD_IVS_EN_SHIFT          (17U)
69026 /*! COREVDD_IVS_EN - CORE VDD Internal Voltage Scaling (IVS) Enable
69027  *  0b0..Disable
69028  *  0b1..Enable
69029  */
69030 #define SPC_LP_CFG_COREVDD_IVS_EN(x)             (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_COREVDD_IVS_EN_SHIFT)) & SPC_LP_CFG_COREVDD_IVS_EN_MASK)
69031 
69032 #define SPC_LP_CFG_LPBUFF_EN_MASK                (0x40000U)
69033 #define SPC_LP_CFG_LPBUFF_EN_SHIFT               (18U)
69034 /*! LPBUFF_EN - CMP Bandgap Buffer Enable
69035  *  0b0..Disable
69036  *  0b1..Enable
69037  */
69038 #define SPC_LP_CFG_LPBUFF_EN(x)                  (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_LPBUFF_EN_SHIFT)) & SPC_LP_CFG_LPBUFF_EN_MASK)
69039 
69040 #define SPC_LP_CFG_BGMODE_MASK                   (0x300000U)
69041 #define SPC_LP_CFG_BGMODE_SHIFT                  (20U)
69042 /*! BGMODE - Bandgap Mode
69043  *  0b00..Bandgap disabled
69044  *  0b01..Bandgap enabled, buffer disabled
69045  *  0b10..Bandgap enabled, buffer enabled
69046  *  0b11..
69047  */
69048 #define SPC_LP_CFG_BGMODE(x)                     (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_BGMODE_SHIFT)) & SPC_LP_CFG_BGMODE_MASK)
69049 
69050 #define SPC_LP_CFG_LP_IREFEN_MASK                (0x800000U)
69051 #define SPC_LP_CFG_LP_IREFEN_SHIFT               (23U)
69052 /*! LP_IREFEN - Low-Power IREF Enable
69053  *  0b0..Disable for power saving in Deep Power Down mode
69054  *  0b1..Enable
69055  */
69056 #define SPC_LP_CFG_LP_IREFEN(x)                  (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_LP_IREFEN_SHIFT)) & SPC_LP_CFG_LP_IREFEN_MASK)
69057 
69058 #define SPC_LP_CFG_CORE_LVDE_MASK                (0x1000000U)
69059 #define SPC_LP_CFG_CORE_LVDE_SHIFT               (24U)
69060 /*! CORE_LVDE - Core Low Voltage Detect Enable
69061  *  0b0..Disable
69062  *  0b1..Enable
69063  */
69064 #define SPC_LP_CFG_CORE_LVDE(x)                  (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_CORE_LVDE_SHIFT)) & SPC_LP_CFG_CORE_LVDE_MASK)
69065 
69066 #define SPC_LP_CFG_SYS_LVDE_MASK                 (0x2000000U)
69067 #define SPC_LP_CFG_SYS_LVDE_SHIFT                (25U)
69068 /*! SYS_LVDE - System Low Voltage Detect Enable
69069  *  0b0..Disable
69070  *  0b1..Enable
69071  */
69072 #define SPC_LP_CFG_SYS_LVDE(x)                   (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_SYS_LVDE_SHIFT)) & SPC_LP_CFG_SYS_LVDE_MASK)
69073 
69074 #define SPC_LP_CFG_IO_LVDE_MASK                  (0x4000000U)
69075 #define SPC_LP_CFG_IO_LVDE_SHIFT                 (26U)
69076 /*! IO_LVDE - IO Low Voltage Detect Enable
69077  *  0b0..Disable
69078  *  0b1..Enable
69079  */
69080 #define SPC_LP_CFG_IO_LVDE(x)                    (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_IO_LVDE_SHIFT)) & SPC_LP_CFG_IO_LVDE_MASK)
69081 
69082 #define SPC_LP_CFG_CORE_HVDE_MASK                (0x8000000U)
69083 #define SPC_LP_CFG_CORE_HVDE_SHIFT               (27U)
69084 /*! CORE_HVDE - Core High Voltage Detect Enable
69085  *  0b0..Disable
69086  *  0b1..Enable
69087  */
69088 #define SPC_LP_CFG_CORE_HVDE(x)                  (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_CORE_HVDE_SHIFT)) & SPC_LP_CFG_CORE_HVDE_MASK)
69089 
69090 #define SPC_LP_CFG_SYS_HVDE_MASK                 (0x10000000U)
69091 #define SPC_LP_CFG_SYS_HVDE_SHIFT                (28U)
69092 /*! SYS_HVDE - System High Voltage Detect Enable
69093  *  0b0..Disable
69094  *  0b1..Enable
69095  */
69096 #define SPC_LP_CFG_SYS_HVDE(x)                   (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_SYS_HVDE_SHIFT)) & SPC_LP_CFG_SYS_HVDE_MASK)
69097 
69098 #define SPC_LP_CFG_IO_HVDE_MASK                  (0x20000000U)
69099 #define SPC_LP_CFG_IO_HVDE_SHIFT                 (29U)
69100 /*! IO_HVDE - IO High Voltage Detect Enable
69101  *  0b0..Disable
69102  *  0b1..Enable
69103  */
69104 #define SPC_LP_CFG_IO_HVDE(x)                    (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_IO_HVDE_SHIFT)) & SPC_LP_CFG_IO_HVDE_MASK)
69105 /*! @} */
69106 
69107 /*! @name LP_CFG1 - Low Power Mode Configuration 1 */
69108 /*! @{ */
69109 
69110 #define SPC_LP_CFG1_SOC_CNTRL_MASK               (0xFFFFFFFFU)
69111 #define SPC_LP_CFG1_SOC_CNTRL_SHIFT              (0U)
69112 /*! SOC_CNTRL - Low-Power Configuration Chip Control */
69113 #define SPC_LP_CFG1_SOC_CNTRL(x)                 (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG1_SOC_CNTRL_SHIFT)) & SPC_LP_CFG1_SOC_CNTRL_MASK)
69114 /*! @} */
69115 
69116 /*! @name LPWKUP_DELAY - Low Power Wake-Up Delay */
69117 /*! @{ */
69118 
69119 #define SPC_LPWKUP_DELAY_LPWKUP_DELAY_MASK       (0xFFFFU)
69120 #define SPC_LPWKUP_DELAY_LPWKUP_DELAY_SHIFT      (0U)
69121 /*! LPWKUP_DELAY - Low-Power Wake-Up Delay */
69122 #define SPC_LPWKUP_DELAY_LPWKUP_DELAY(x)         (((uint32_t)(((uint32_t)(x)) << SPC_LPWKUP_DELAY_LPWKUP_DELAY_SHIFT)) & SPC_LPWKUP_DELAY_LPWKUP_DELAY_MASK)
69123 /*! @} */
69124 
69125 /*! @name ACTIVE_VDELAY - Active Voltage Trim Delay */
69126 /*! @{ */
69127 
69128 #define SPC_ACTIVE_VDELAY_ACTIVE_VDELAY_MASK     (0xFFFFU)
69129 #define SPC_ACTIVE_VDELAY_ACTIVE_VDELAY_SHIFT    (0U)
69130 /*! ACTIVE_VDELAY - Active Voltage Delay */
69131 #define SPC_ACTIVE_VDELAY_ACTIVE_VDELAY(x)       (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_VDELAY_ACTIVE_VDELAY_SHIFT)) & SPC_ACTIVE_VDELAY_ACTIVE_VDELAY_MASK)
69132 /*! @} */
69133 
69134 /*! @name VD_STAT - Voltage Detect Status */
69135 /*! @{ */
69136 
69137 #define SPC_VD_STAT_COREVDD_LVDF_MASK            (0x1U)
69138 #define SPC_VD_STAT_COREVDD_LVDF_SHIFT           (0U)
69139 /*! COREVDD_LVDF - Core Low-Voltage Detect Flag
69140  *  0b0..Event not detected
69141  *  0b1..Event detected
69142  *  0b0..No effect
69143  *  0b1..Clear the flag
69144  */
69145 #define SPC_VD_STAT_COREVDD_LVDF(x)              (((uint32_t)(((uint32_t)(x)) << SPC_VD_STAT_COREVDD_LVDF_SHIFT)) & SPC_VD_STAT_COREVDD_LVDF_MASK)
69146 
69147 #define SPC_VD_STAT_SYSVDD_LVDF_MASK             (0x2U)
69148 #define SPC_VD_STAT_SYSVDD_LVDF_SHIFT            (1U)
69149 /*! SYSVDD_LVDF - System Low-Voltage Detect Flag
69150  *  0b0..Event not detected
69151  *  0b1..Event detected
69152  *  0b0..No effect
69153  *  0b1..Clear the flag
69154  */
69155 #define SPC_VD_STAT_SYSVDD_LVDF(x)               (((uint32_t)(((uint32_t)(x)) << SPC_VD_STAT_SYSVDD_LVDF_SHIFT)) & SPC_VD_STAT_SYSVDD_LVDF_MASK)
69156 
69157 #define SPC_VD_STAT_IOVDD_LVDF_MASK              (0x4U)
69158 #define SPC_VD_STAT_IOVDD_LVDF_SHIFT             (2U)
69159 /*! IOVDD_LVDF - IO VDD LVD Flag
69160  *  0b0..Event not detected
69161  *  0b1..Event detected
69162  *  0b0..No effect
69163  *  0b1..Clear the flag
69164  */
69165 #define SPC_VD_STAT_IOVDD_LVDF(x)                (((uint32_t)(((uint32_t)(x)) << SPC_VD_STAT_IOVDD_LVDF_SHIFT)) & SPC_VD_STAT_IOVDD_LVDF_MASK)
69166 
69167 #define SPC_VD_STAT_COREVDD_HVDF_MASK            (0x10U)
69168 #define SPC_VD_STAT_COREVDD_HVDF_SHIFT           (4U)
69169 /*! COREVDD_HVDF - Core VDD HVD Flag
69170  *  0b0..Event not detected
69171  *  0b1..Event detected
69172  *  0b0..No effect
69173  *  0b1..Clear the flag
69174  */
69175 #define SPC_VD_STAT_COREVDD_HVDF(x)              (((uint32_t)(((uint32_t)(x)) << SPC_VD_STAT_COREVDD_HVDF_SHIFT)) & SPC_VD_STAT_COREVDD_HVDF_MASK)
69176 
69177 #define SPC_VD_STAT_SYSVDD_HVDF_MASK             (0x20U)
69178 #define SPC_VD_STAT_SYSVDD_HVDF_SHIFT            (5U)
69179 /*! SYSVDD_HVDF - System HVD Flag
69180  *  0b0..Event not detected
69181  *  0b1..Event detected
69182  *  0b0..No effect
69183  *  0b1..Clear the flag
69184  */
69185 #define SPC_VD_STAT_SYSVDD_HVDF(x)               (((uint32_t)(((uint32_t)(x)) << SPC_VD_STAT_SYSVDD_HVDF_SHIFT)) & SPC_VD_STAT_SYSVDD_HVDF_MASK)
69186 
69187 #define SPC_VD_STAT_IOVDD_HVDF_MASK              (0x40U)
69188 #define SPC_VD_STAT_IOVDD_HVDF_SHIFT             (6U)
69189 /*! IOVDD_HVDF - IO VDD HVD Flag
69190  *  0b0..Event not detected
69191  *  0b1..Event detected
69192  *  0b0..No effect
69193  *  0b1..Clear the flag
69194  */
69195 #define SPC_VD_STAT_IOVDD_HVDF(x)                (((uint32_t)(((uint32_t)(x)) << SPC_VD_STAT_IOVDD_HVDF_SHIFT)) & SPC_VD_STAT_IOVDD_HVDF_MASK)
69196 /*! @} */
69197 
69198 /*! @name VD_CORE_CFG - Core Voltage Detect Configuration */
69199 /*! @{ */
69200 
69201 #define SPC_VD_CORE_CFG_LVDRE_MASK               (0x1U)
69202 #define SPC_VD_CORE_CFG_LVDRE_SHIFT              (0U)
69203 /*! LVDRE - Core LVD Reset Enable
69204  *  0b0..Disable
69205  *  0b1..Enable
69206  */
69207 #define SPC_VD_CORE_CFG_LVDRE(x)                 (((uint32_t)(((uint32_t)(x)) << SPC_VD_CORE_CFG_LVDRE_SHIFT)) & SPC_VD_CORE_CFG_LVDRE_MASK)
69208 
69209 #define SPC_VD_CORE_CFG_LVDIE_MASK               (0x2U)
69210 #define SPC_VD_CORE_CFG_LVDIE_SHIFT              (1U)
69211 /*! LVDIE - Core LVD Interrupt Enable
69212  *  0b0..Disable
69213  *  0b1..Enable
69214  */
69215 #define SPC_VD_CORE_CFG_LVDIE(x)                 (((uint32_t)(((uint32_t)(x)) << SPC_VD_CORE_CFG_LVDIE_SHIFT)) & SPC_VD_CORE_CFG_LVDIE_MASK)
69216 
69217 #define SPC_VD_CORE_CFG_HVDRE_MASK               (0x4U)
69218 #define SPC_VD_CORE_CFG_HVDRE_SHIFT              (2U)
69219 /*! HVDRE - Core VDD HVD Reset Enable
69220  *  0b0..Disable
69221  *  0b1..Enable
69222  */
69223 #define SPC_VD_CORE_CFG_HVDRE(x)                 (((uint32_t)(((uint32_t)(x)) << SPC_VD_CORE_CFG_HVDRE_SHIFT)) & SPC_VD_CORE_CFG_HVDRE_MASK)
69224 
69225 #define SPC_VD_CORE_CFG_HVDIE_MASK               (0x8U)
69226 #define SPC_VD_CORE_CFG_HVDIE_SHIFT              (3U)
69227 /*! HVDIE - Core VDD HVD Interrupt Enable
69228  *  0b0..Disable
69229  *  0b1..Enable
69230  */
69231 #define SPC_VD_CORE_CFG_HVDIE(x)                 (((uint32_t)(((uint32_t)(x)) << SPC_VD_CORE_CFG_HVDIE_SHIFT)) & SPC_VD_CORE_CFG_HVDIE_MASK)
69232 
69233 #define SPC_VD_CORE_CFG_LOCK_MASK                (0x10000U)
69234 #define SPC_VD_CORE_CFG_LOCK_SHIFT               (16U)
69235 /*! LOCK - Core Voltage Detect Reset Enable Lock
69236  *  0b0..Allow
69237  *  0b1..Deny
69238  */
69239 #define SPC_VD_CORE_CFG_LOCK(x)                  (((uint32_t)(((uint32_t)(x)) << SPC_VD_CORE_CFG_LOCK_SHIFT)) & SPC_VD_CORE_CFG_LOCK_MASK)
69240 /*! @} */
69241 
69242 /*! @name VD_SYS_CFG - System Voltage Detect Configuration */
69243 /*! @{ */
69244 
69245 #define SPC_VD_SYS_CFG_LVDRE_MASK                (0x1U)
69246 #define SPC_VD_SYS_CFG_LVDRE_SHIFT               (0U)
69247 /*! LVDRE - System LVD Reset Enable
69248  *  0b0..Disable
69249  *  0b1..Enable
69250  */
69251 #define SPC_VD_SYS_CFG_LVDRE(x)                  (((uint32_t)(((uint32_t)(x)) << SPC_VD_SYS_CFG_LVDRE_SHIFT)) & SPC_VD_SYS_CFG_LVDRE_MASK)
69252 
69253 #define SPC_VD_SYS_CFG_LVDIE_MASK                (0x2U)
69254 #define SPC_VD_SYS_CFG_LVDIE_SHIFT               (1U)
69255 /*! LVDIE - System LVD Interrupt Enable
69256  *  0b0..Disable
69257  *  0b1..Enable
69258  */
69259 #define SPC_VD_SYS_CFG_LVDIE(x)                  (((uint32_t)(((uint32_t)(x)) << SPC_VD_SYS_CFG_LVDIE_SHIFT)) & SPC_VD_SYS_CFG_LVDIE_MASK)
69260 
69261 #define SPC_VD_SYS_CFG_HVDRE_MASK                (0x4U)
69262 #define SPC_VD_SYS_CFG_HVDRE_SHIFT               (2U)
69263 /*! HVDRE - System HVD Reset Enable
69264  *  0b0..Disable
69265  *  0b1..Enable
69266  */
69267 #define SPC_VD_SYS_CFG_HVDRE(x)                  (((uint32_t)(((uint32_t)(x)) << SPC_VD_SYS_CFG_HVDRE_SHIFT)) & SPC_VD_SYS_CFG_HVDRE_MASK)
69268 
69269 #define SPC_VD_SYS_CFG_HVDIE_MASK                (0x8U)
69270 #define SPC_VD_SYS_CFG_HVDIE_SHIFT               (3U)
69271 /*! HVDIE - System HVD Interrupt Enable
69272  *  0b0..Disable
69273  *  0b1..Enable
69274  */
69275 #define SPC_VD_SYS_CFG_HVDIE(x)                  (((uint32_t)(((uint32_t)(x)) << SPC_VD_SYS_CFG_HVDIE_SHIFT)) & SPC_VD_SYS_CFG_HVDIE_MASK)
69276 
69277 #define SPC_VD_SYS_CFG_LOCK_MASK                 (0x10000U)
69278 #define SPC_VD_SYS_CFG_LOCK_SHIFT                (16U)
69279 /*! LOCK - System Voltage Detect Reset Enable Lock
69280  *  0b0..Allow
69281  *  0b1..Deny
69282  */
69283 #define SPC_VD_SYS_CFG_LOCK(x)                   (((uint32_t)(((uint32_t)(x)) << SPC_VD_SYS_CFG_LOCK_SHIFT)) & SPC_VD_SYS_CFG_LOCK_MASK)
69284 /*! @} */
69285 
69286 /*! @name VD_IO_CFG - IO Voltage Detect Configuration */
69287 /*! @{ */
69288 
69289 #define SPC_VD_IO_CFG_LVDRE_MASK                 (0x1U)
69290 #define SPC_VD_IO_CFG_LVDRE_SHIFT                (0U)
69291 /*! LVDRE - IO VDD LVD Reset Enable
69292  *  0b0..Disable
69293  *  0b1..Enable
69294  */
69295 #define SPC_VD_IO_CFG_LVDRE(x)                   (((uint32_t)(((uint32_t)(x)) << SPC_VD_IO_CFG_LVDRE_SHIFT)) & SPC_VD_IO_CFG_LVDRE_MASK)
69296 
69297 #define SPC_VD_IO_CFG_LVDIE_MASK                 (0x2U)
69298 #define SPC_VD_IO_CFG_LVDIE_SHIFT                (1U)
69299 /*! LVDIE - IO VDD LVD Interrupt Enable
69300  *  0b0..Disable
69301  *  0b1..Enable
69302  */
69303 #define SPC_VD_IO_CFG_LVDIE(x)                   (((uint32_t)(((uint32_t)(x)) << SPC_VD_IO_CFG_LVDIE_SHIFT)) & SPC_VD_IO_CFG_LVDIE_MASK)
69304 
69305 #define SPC_VD_IO_CFG_HVDRE_MASK                 (0x4U)
69306 #define SPC_VD_IO_CFG_HVDRE_SHIFT                (2U)
69307 /*! HVDRE - IO VDD HVD Reset Enable
69308  *  0b0..Disable
69309  *  0b1..Enable
69310  */
69311 #define SPC_VD_IO_CFG_HVDRE(x)                   (((uint32_t)(((uint32_t)(x)) << SPC_VD_IO_CFG_HVDRE_SHIFT)) & SPC_VD_IO_CFG_HVDRE_MASK)
69312 
69313 #define SPC_VD_IO_CFG_HVDIE_MASK                 (0x8U)
69314 #define SPC_VD_IO_CFG_HVDIE_SHIFT                (3U)
69315 /*! HVDIE - IO VDD HVD Interrupt Enable
69316  *  0b0..Disable
69317  *  0b1..Enable
69318  */
69319 #define SPC_VD_IO_CFG_HVDIE(x)                   (((uint32_t)(((uint32_t)(x)) << SPC_VD_IO_CFG_HVDIE_SHIFT)) & SPC_VD_IO_CFG_HVDIE_MASK)
69320 
69321 #define SPC_VD_IO_CFG_LVSEL_MASK                 (0x100U)
69322 #define SPC_VD_IO_CFG_LVSEL_SHIFT                (8U)
69323 /*! LVSEL - IO VDD Low-Voltage Level Select
69324  *  0b0..High range
69325  *  0b1..Low range
69326  */
69327 #define SPC_VD_IO_CFG_LVSEL(x)                   (((uint32_t)(((uint32_t)(x)) << SPC_VD_IO_CFG_LVSEL_SHIFT)) & SPC_VD_IO_CFG_LVSEL_MASK)
69328 
69329 #define SPC_VD_IO_CFG_LOCK_MASK                  (0x10000U)
69330 #define SPC_VD_IO_CFG_LOCK_SHIFT                 (16U)
69331 /*! LOCK - IO Voltage Detect Reset Enable Lock
69332  *  0b0..Allow
69333  *  0b1..Deny
69334  */
69335 #define SPC_VD_IO_CFG_LOCK(x)                    (((uint32_t)(((uint32_t)(x)) << SPC_VD_IO_CFG_LOCK_SHIFT)) & SPC_VD_IO_CFG_LOCK_MASK)
69336 /*! @} */
69337 
69338 /*! @name EVD_CFG - External Voltage Domain Configuration */
69339 /*! @{ */
69340 
69341 #define SPC_EVD_CFG_EVDISO_MASK                  (0x3FU)
69342 #define SPC_EVD_CFG_EVDISO_SHIFT                 (0U)
69343 /*! EVDISO - External Voltage Domain Isolation */
69344 #define SPC_EVD_CFG_EVDISO(x)                    (((uint32_t)(((uint32_t)(x)) << SPC_EVD_CFG_EVDISO_SHIFT)) & SPC_EVD_CFG_EVDISO_MASK)
69345 
69346 #define SPC_EVD_CFG_EVDLPISO_MASK                (0x3F00U)
69347 #define SPC_EVD_CFG_EVDLPISO_SHIFT               (8U)
69348 /*! EVDLPISO - External Voltage Domain Low-Power Isolation */
69349 #define SPC_EVD_CFG_EVDLPISO(x)                  (((uint32_t)(((uint32_t)(x)) << SPC_EVD_CFG_EVDLPISO_SHIFT)) & SPC_EVD_CFG_EVDLPISO_MASK)
69350 
69351 #define SPC_EVD_CFG_EVDSTAT_MASK                 (0x3F0000U)
69352 #define SPC_EVD_CFG_EVDSTAT_SHIFT                (16U)
69353 /*! EVDSTAT - External Voltage Domain Status */
69354 #define SPC_EVD_CFG_EVDSTAT(x)                   (((uint32_t)(((uint32_t)(x)) << SPC_EVD_CFG_EVDSTAT_SHIFT)) & SPC_EVD_CFG_EVDSTAT_MASK)
69355 /*! @} */
69356 
69357 /*! @name GLITCH_DETECT_SC - Glitch Detect Status Control */
69358 /*! @{ */
69359 
69360 #define SPC_GLITCH_DETECT_SC_CNT_SELECT_MASK     (0x3U)
69361 #define SPC_GLITCH_DETECT_SC_CNT_SELECT_SHIFT    (0U)
69362 /*! CNT_SELECT - Counter Select
69363  *  0b00..0
69364  *  0b01..1
69365  *  0b10..2
69366  *  0b11..3
69367  */
69368 #define SPC_GLITCH_DETECT_SC_CNT_SELECT(x)       (((uint32_t)(((uint32_t)(x)) << SPC_GLITCH_DETECT_SC_CNT_SELECT_SHIFT)) & SPC_GLITCH_DETECT_SC_CNT_SELECT_MASK)
69369 
69370 #define SPC_GLITCH_DETECT_SC_TIMEOUT_MASK        (0x3CU)
69371 #define SPC_GLITCH_DETECT_SC_TIMEOUT_SHIFT       (2U)
69372 /*! TIMEOUT - Timeout */
69373 #define SPC_GLITCH_DETECT_SC_TIMEOUT(x)          (((uint32_t)(((uint32_t)(x)) << SPC_GLITCH_DETECT_SC_TIMEOUT_SHIFT)) & SPC_GLITCH_DETECT_SC_TIMEOUT_MASK)
69374 
69375 #define SPC_GLITCH_DETECT_SC_RE_MASK             (0x40U)
69376 #define SPC_GLITCH_DETECT_SC_RE_SHIFT            (6U)
69377 /*! RE - Glitch Detect Reset Enable
69378  *  0b0..GLITCH_DETECT_FLAG[CNT_SELECT] does not generate POR/LVD reset
69379  *  0b1..GLITCH_DETECT_FLAG[CNT_SELECT] does generate POR/LVD reset
69380  */
69381 #define SPC_GLITCH_DETECT_SC_RE(x)               (((uint32_t)(((uint32_t)(x)) << SPC_GLITCH_DETECT_SC_RE_SHIFT)) & SPC_GLITCH_DETECT_SC_RE_MASK)
69382 
69383 #define SPC_GLITCH_DETECT_SC_IE_MASK             (0x80U)
69384 #define SPC_GLITCH_DETECT_SC_IE_SHIFT            (7U)
69385 /*! IE - Glitch Detect Interrupt Enable
69386  *  0b0..GLITCH_DETECT_FLAG[CNT_SELECT] does not generate hardware interrupt (user polling)
69387  *  0b1..GLITCH_DETECT_FLAG[CNT_SELECT] does generate hardware interrupt
69388  */
69389 #define SPC_GLITCH_DETECT_SC_IE(x)               (((uint32_t)(((uint32_t)(x)) << SPC_GLITCH_DETECT_SC_IE_SHIFT)) & SPC_GLITCH_DETECT_SC_IE_MASK)
69390 
69391 #define SPC_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG_MASK (0xF00U)
69392 #define SPC_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG_SHIFT (8U)
69393 /*! GLITCH_DETECT_FLAG - GLITCH_DETECT_FLAG */
69394 #define SPC_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG(x) (((uint32_t)(((uint32_t)(x)) << SPC_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG_SHIFT)) & SPC_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG_MASK)
69395 
69396 #define SPC_GLITCH_DETECT_SC_LOCK_MASK           (0x10000U)
69397 #define SPC_GLITCH_DETECT_SC_LOCK_SHIFT          (16U)
69398 /*! LOCK - Glitch Detect Reset Enable Lock Bit
69399  *  0b0..Writes to RE are allowed.
69400  *  0b1..Writes to RE are ignored.
69401  */
69402 #define SPC_GLITCH_DETECT_SC_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << SPC_GLITCH_DETECT_SC_LOCK_SHIFT)) & SPC_GLITCH_DETECT_SC_LOCK_MASK)
69403 /*! @} */
69404 
69405 /*! @name CORELDO_CFG - LDO_CORE Configuration */
69406 /*! @{ */
69407 
69408 #define SPC_CORELDO_CFG_DPDOWN_PULLDOWN_DISABLE_MASK (0x10000U)
69409 #define SPC_CORELDO_CFG_DPDOWN_PULLDOWN_DISABLE_SHIFT (16U)
69410 /*! DPDOWN_PULLDOWN_DISABLE - LDO_CORE Deep Power Down Pulldown Disable
69411  *  0b0..LDO_CORE pulldown in Deep Power Down not disabled
69412  *  0b1..LDO_CORE pulldown in Deep Power Down disabled
69413  */
69414 #define SPC_CORELDO_CFG_DPDOWN_PULLDOWN_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << SPC_CORELDO_CFG_DPDOWN_PULLDOWN_DISABLE_SHIFT)) & SPC_CORELDO_CFG_DPDOWN_PULLDOWN_DISABLE_MASK)
69415 /*! @} */
69416 
69417 /*! @name SYSLDO_CFG - LDO_SYS Configuration */
69418 /*! @{ */
69419 
69420 #define SPC_SYSLDO_CFG_ISINKEN_MASK              (0x1U)
69421 #define SPC_SYSLDO_CFG_ISINKEN_SHIFT             (0U)
69422 /*! ISINKEN - Current Sink Enable
69423  *  0b0..Disable
69424  *  0b1..Enable
69425  */
69426 #define SPC_SYSLDO_CFG_ISINKEN(x)                (((uint32_t)(((uint32_t)(x)) << SPC_SYSLDO_CFG_ISINKEN_SHIFT)) & SPC_SYSLDO_CFG_ISINKEN_MASK)
69427 /*! @} */
69428 
69429 /*! @name DCDC_CFG - DCDC Configuration */
69430 /*! @{ */
69431 
69432 #define SPC_DCDC_CFG_FREQ_CNTRL_ON_MASK          (0x1U)
69433 #define SPC_DCDC_CFG_FREQ_CNTRL_ON_SHIFT         (0U)
69434 /*! FREQ_CNTRL_ON - DCDC Burst Frequency Control Enable
69435  *  0b0..Disable
69436  *  0b1..Enable
69437  */
69438 #define SPC_DCDC_CFG_FREQ_CNTRL_ON(x)            (((uint32_t)(((uint32_t)(x)) << SPC_DCDC_CFG_FREQ_CNTRL_ON_SHIFT)) & SPC_DCDC_CFG_FREQ_CNTRL_ON_MASK)
69439 
69440 #define SPC_DCDC_CFG_FREQ_CNTRL_MASK             (0x3F00U)
69441 #define SPC_DCDC_CFG_FREQ_CNTRL_SHIFT            (8U)
69442 /*! FREQ_CNTRL - DCDC Burst Frequency Control */
69443 #define SPC_DCDC_CFG_FREQ_CNTRL(x)               (((uint32_t)(((uint32_t)(x)) << SPC_DCDC_CFG_FREQ_CNTRL_SHIFT)) & SPC_DCDC_CFG_FREQ_CNTRL_MASK)
69444 
69445 #define SPC_DCDC_CFG_BLEED_EN_MASK               (0x80000U)
69446 #define SPC_DCDC_CFG_BLEED_EN_SHIFT              (19U)
69447 /*! BLEED_EN - DCDC Bleed Enable
69448  *  0b0..Do not add
69449  *  0b1..Add
69450  */
69451 #define SPC_DCDC_CFG_BLEED_EN(x)                 (((uint32_t)(((uint32_t)(x)) << SPC_DCDC_CFG_BLEED_EN_SHIFT)) & SPC_DCDC_CFG_BLEED_EN_MASK)
69452 /*! @} */
69453 
69454 /*! @name DCDC_BURST_CFG - DCDC Burst Configuration */
69455 /*! @{ */
69456 
69457 #define SPC_DCDC_BURST_CFG_BURST_REQ_MASK        (0x1U)
69458 #define SPC_DCDC_BURST_CFG_BURST_REQ_SHIFT       (0U)
69459 /*! BURST_REQ - Software Burst Request
69460  *  0b0..Do not generate
69461  *  0b1..Generate
69462  */
69463 #define SPC_DCDC_BURST_CFG_BURST_REQ(x)          (((uint32_t)(((uint32_t)(x)) << SPC_DCDC_BURST_CFG_BURST_REQ_SHIFT)) & SPC_DCDC_BURST_CFG_BURST_REQ_MASK)
69464 
69465 #define SPC_DCDC_BURST_CFG_EXT_BURST_EN_MASK     (0x2U)
69466 #define SPC_DCDC_BURST_CFG_EXT_BURST_EN_SHIFT    (1U)
69467 /*! EXT_BURST_EN - External Burst Request Enable
69468  *  0b0..Disable
69469  *  0b1..Enable
69470  */
69471 #define SPC_DCDC_BURST_CFG_EXT_BURST_EN(x)       (((uint32_t)(((uint32_t)(x)) << SPC_DCDC_BURST_CFG_EXT_BURST_EN_SHIFT)) & SPC_DCDC_BURST_CFG_EXT_BURST_EN_MASK)
69472 
69473 #define SPC_DCDC_BURST_CFG_BURST_ACK_MASK        (0x8U)
69474 #define SPC_DCDC_BURST_CFG_BURST_ACK_SHIFT       (3U)
69475 /*! BURST_ACK - Burst Acknowledge Flag
69476  *  0b0..Did not complete
69477  *  0b1..Completed
69478  *  0b0..No effect
69479  *  0b1..Clear the flag
69480  */
69481 #define SPC_DCDC_BURST_CFG_BURST_ACK(x)          (((uint32_t)(((uint32_t)(x)) << SPC_DCDC_BURST_CFG_BURST_ACK_SHIFT)) & SPC_DCDC_BURST_CFG_BURST_ACK_MASK)
69482 
69483 #define SPC_DCDC_BURST_CFG_PULSE_REFRESH_CNT_MASK (0xFFFF0000U)
69484 #define SPC_DCDC_BURST_CFG_PULSE_REFRESH_CNT_SHIFT (16U)
69485 /*! PULSE_REFRESH_CNT - Refresh Count Value */
69486 #define SPC_DCDC_BURST_CFG_PULSE_REFRESH_CNT(x)  (((uint32_t)(((uint32_t)(x)) << SPC_DCDC_BURST_CFG_PULSE_REFRESH_CNT_SHIFT)) & SPC_DCDC_BURST_CFG_PULSE_REFRESH_CNT_MASK)
69487 /*! @} */
69488 
69489 
69490 /*!
69491  * @}
69492  */ /* end of group SPC_Register_Masks */
69493 
69494 
69495 /* SPC - Peripheral instance base addresses */
69496 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
69497   /** Peripheral SPC0 base address */
69498   #define SPC0_BASE                                (0x50045000u)
69499   /** Peripheral SPC0 base address */
69500   #define SPC0_BASE_NS                             (0x40045000u)
69501   /** Peripheral SPC0 base pointer */
69502   #define SPC0                                     ((SPC_Type *)SPC0_BASE)
69503   /** Peripheral SPC0 base pointer */
69504   #define SPC0_NS                                  ((SPC_Type *)SPC0_BASE_NS)
69505   /** Array initializer of SPC peripheral base addresses */
69506   #define SPC_BASE_ADDRS                           { SPC0_BASE }
69507   /** Array initializer of SPC peripheral base pointers */
69508   #define SPC_BASE_PTRS                            { SPC0 }
69509   /** Array initializer of SPC peripheral base addresses */
69510   #define SPC_BASE_ADDRS_NS                        { SPC0_BASE_NS }
69511   /** Array initializer of SPC peripheral base pointers */
69512   #define SPC_BASE_PTRS_NS                         { SPC0_NS }
69513 #else
69514   /** Peripheral SPC0 base address */
69515   #define SPC0_BASE                                (0x40045000u)
69516   /** Peripheral SPC0 base pointer */
69517   #define SPC0                                     ((SPC_Type *)SPC0_BASE)
69518   /** Array initializer of SPC peripheral base addresses */
69519   #define SPC_BASE_ADDRS                           { SPC0_BASE }
69520   /** Array initializer of SPC peripheral base pointers */
69521   #define SPC_BASE_PTRS                            { SPC0 }
69522 #endif
69523 
69524 /*!
69525  * @}
69526  */ /* end of group SPC_Peripheral_Access_Layer */
69527 
69528 
69529 /* ----------------------------------------------------------------------------
69530    -- SYSCON Peripheral Access Layer
69531    ---------------------------------------------------------------------------- */
69532 
69533 /*!
69534  * @addtogroup SYSCON_Peripheral_Access_Layer SYSCON Peripheral Access Layer
69535  * @{
69536  */
69537 
69538 /** SYSCON - Register Layout Typedef */
69539 typedef struct {
69540        uint8_t RESERVED_0[16];
69541   __IO uint32_t AHBMATPRIO;                        /**< AHB Matrix Priority Control, offset: 0x10 */
69542        uint8_t RESERVED_1[36];
69543   __IO uint32_t CPU0STCKCAL;                       /**< Secure CPU0 System Tick Calibration, offset: 0x38 */
69544   __IO uint32_t CPU0NSTCKCAL;                      /**< Non-Secure CPU0 System Tick Calibration, offset: 0x3C */
69545   __IO uint32_t CPU1STCKCAL;                       /**< System tick calibration for CPU1, offset: 0x40 */
69546        uint8_t RESERVED_2[4];
69547   __IO uint32_t NMISRC;                            /**< NMI Source Select, offset: 0x48 */
69548        uint8_t RESERVED_3[180];
69549   __IO uint32_t PRESETCTRL0;                       /**< Peripheral Reset Control 0, offset: 0x100 */
69550   __IO uint32_t PRESETCTRL1;                       /**< Peripheral Reset Control 1, offset: 0x104 */
69551   __IO uint32_t PRESETCTRL2;                       /**< Peripheral Reset Control 2, offset: 0x108 */
69552   __IO uint32_t PRESETCTRL3;                       /**< Peripheral Reset Control 3, offset: 0x10C */
69553        uint8_t RESERVED_4[16];
69554   __O  uint32_t PRESETCTRLSET[4];                  /**< Peripheral Reset Control Set, array offset: 0x120, array step: 0x4 */
69555        uint8_t RESERVED_5[16];
69556   __O  uint32_t PRESETCTRLCLR[4];                  /**< Peripheral Reset Control Clear, array offset: 0x140, array step: 0x4 */
69557        uint8_t RESERVED_6[176];
69558   __IO uint32_t AHBCLKCTRL0;                       /**< AHB Clock Control 0, offset: 0x200 */
69559   __IO uint32_t AHBCLKCTRL1;                       /**< AHB Clock Control 1, offset: 0x204 */
69560   __IO uint32_t AHBCLKCTRL2;                       /**< AHB Clock Control 2, offset: 0x208 */
69561   __IO uint32_t AHBCLKCTRL3;                       /**< AHB Clock Control 3, offset: 0x20C */
69562        uint8_t RESERVED_7[16];
69563   __O  uint32_t AHBCLKCTRLSET[4];                  /**< AHB Clock Control Set, array offset: 0x220, array step: 0x4 */
69564        uint8_t RESERVED_8[16];
69565   __O  uint32_t AHBCLKCTRLCLR[4];                  /**< AHB Clock Control Clear, array offset: 0x240, array step: 0x4 */
69566        uint8_t RESERVED_9[16];
69567   __IO uint32_t SYSTICKCLKSEL0;                    /**< CPU0 System Tick Timer Source Select, offset: 0x260 */
69568   __IO uint32_t SYSTICKCLKSEL1;                    /**< CPU1 System Tick Timer Source Select, offset: 0x264 */
69569   __IO uint32_t TRACECLKSEL;                       /**< Trace Clock Source Select, offset: 0x268 */
69570   __IO uint32_t CTIMERCLKSEL[5];                   /**< CTIMER Clock Source Select, array offset: 0x26C, array step: 0x4 */
69571        uint8_t RESERVED_10[8];
69572   __IO uint32_t CLKOUTSEL;                         /**< CLKOUT Clock Source Select, offset: 0x288 */
69573        uint8_t RESERVED_11[24];
69574   __IO uint32_t ADC0CLKSEL;                        /**< ADC0 Clock Source Select, offset: 0x2A4 */
69575   __IO uint32_t USB0CLKSEL;                        /**< USB-FS Clock Source Select, offset: 0x2A8 */
69576        uint8_t RESERVED_12[4];
69577   __IO uint32_t FCCLKSEL[10];                      /**< LP_FLEXCOMM Clock Source Select for Fractional Rate Divider, array offset: 0x2B0, array step: 0x4 */
69578        uint8_t RESERVED_13[24];
69579   __IO uint32_t SCTCLKSEL;                         /**< SCTimer/PWM Clock Source Select, offset: 0x2F0 */
69580        uint8_t RESERVED_14[12];
69581   __IO uint32_t SYSTICKCLKDIV[2];                  /**< CPU0 System Tick Timer Divider..CPU1 System Tick Timer Divider, array offset: 0x300, array step: 0x4 */
69582   __IO uint32_t TRACECLKDIV;                       /**< TRACE Clock Divider, offset: 0x308 */
69583        uint8_t RESERVED_15[68];
69584   __IO uint32_t TSICLKSEL;                         /**< TSI Function Clock Source Select, offset: 0x350 */
69585        uint8_t RESERVED_16[12];
69586   __IO uint32_t SINCFILTCLKSEL;                    /**< SINC FILTER Function Clock Source Select, offset: 0x360 */
69587        uint8_t RESERVED_17[20];
69588   __IO uint32_t SLOWCLKDIV;                        /**< SLOW_CLK Clock Divider, offset: 0x378 */
69589   __IO uint32_t TSICLKDIV;                         /**< TSI Function Clock Divider, offset: 0x37C */
69590   __IO uint32_t AHBCLKDIV;                         /**< System Clock Divider, offset: 0x380 */
69591   __IO uint32_t CLKOUTDIV;                         /**< CLKOUT Clock Divider, offset: 0x384 */
69592   __IO uint32_t FROHFDIV;                          /**< FRO_HF_DIV Clock Divider, offset: 0x388 */
69593   __IO uint32_t WDT0CLKDIV;                        /**< WDT0 Clock Divider, offset: 0x38C */
69594        uint8_t RESERVED_18[4];
69595   __IO uint32_t ADC0CLKDIV;                        /**< ADC0 Clock Divider, offset: 0x394 */
69596   __IO uint32_t USB0CLKDIV;                        /**< USB-FS Clock Divider, offset: 0x398 */
69597        uint8_t RESERVED_19[24];
69598   __IO uint32_t SCTCLKDIV;                         /**< SCT/PWM Clock Divider, offset: 0x3B4 */
69599        uint8_t RESERVED_20[12];
69600   __IO uint32_t PLLCLKDIV;                         /**< PLL Clock Divider, offset: 0x3C4 */
69601        uint8_t RESERVED_21[8];
69602   __IO uint32_t CTIMERCLKDIV[5];                   /**< CTimer Clock Divider, array offset: 0x3D0, array step: 0x4 */
69603   __IO uint32_t PLL1CLK0DIV;                       /**< PLL1 Clock 0 Divider, offset: 0x3E4 */
69604   __IO uint32_t PLL1CLK1DIV;                       /**< PLL1 Clock 1 Divider, offset: 0x3E8 */
69605        uint8_t RESERVED_22[4];
69606   __IO uint32_t UTICKCLKDIV;                       /**< UTICK Clock Divider, offset: 0x3F0 */
69607   __IO uint32_t CLKOUT_FRGCTRL;                    /**< CLKOUT FRG Control, offset: 0x3F4 */
69608        uint8_t RESERVED_23[4];
69609   __IO uint32_t CLKUNLOCK;                         /**< Clock Configuration Unlock, offset: 0x3FC */
69610   __IO uint32_t NVM_CTRL;                          /**< NVM Control, offset: 0x400 */
69611   __IO uint32_t ROMCR;                             /**< ROM Wait State, offset: 0x404 */
69612        uint8_t RESERVED_24[12];
69613   __IO uint32_t SMARTDMAINT;                       /**< SmartDMA Interrupt Hijack, offset: 0x414 */
69614        uint8_t RESERVED_25[76];
69615   __IO uint32_t ADC1CLKSEL;                        /**< ADC1 Clock Source Select, offset: 0x464 */
69616   __IO uint32_t ADC1CLKDIV;                        /**< ADC1 Clock Divider, offset: 0x468 */
69617        uint8_t RESERVED_26[4];
69618   __IO uint32_t RAM_INTERLEAVE;                    /**< Control PKC RAM Interleave Access, offset: 0x470 */
69619        uint8_t RESERVED_27[28];
69620   struct {                                         /* offset: 0x490, array step: 0x8 */
69621     __IO uint32_t CLKSEL;                            /**< DAC0 Functional Clock Selection..DAC2 Functional Clock Selection, array offset: 0x490, array step: 0x8 */
69622     __IO uint32_t CLKDIV;                            /**< DAC0 functional clock divider..DAC2 functional clock divider, array offset: 0x494, array step: 0x8 */
69623   } DAC[3];
69624   __IO uint32_t FLEXSPICLKSEL;                     /**< FlexSPI Clock Selection, offset: 0x4A8 */
69625   __IO uint32_t FLEXSPICLKDIV;                     /**< FlexSPI Clock Divider, offset: 0x4AC */
69626        uint8_t RESERVED_28[124];
69627   __IO uint32_t PLLCLKDIVSEL;                      /**< PLL Clock Divider Clock Selection, offset: 0x52C */
69628   __IO uint32_t I3C0FCLKSEL;                       /**< I3C0 Functional Clock Selection, offset: 0x530 */
69629   __IO uint32_t I3C0FCLKSTCSEL;                    /**< I3C0 FCLK_STC Clock Selection, offset: 0x534 */
69630   __IO uint32_t I3C0FCLKSTCDIV;                    /**< I3C0 FCLK_STC Clock Divider, offset: 0x538 */
69631   __IO uint32_t I3C0FCLKSDIV;                      /**< I3C0 FCLK Slow Clock Divider, offset: 0x53C */
69632   __IO uint32_t I3C0FCLKDIV;                       /**< I3C0 Functional Clock FCLK Divider, offset: 0x540 */
69633   __IO uint32_t I3C0FCLKSSEL;                      /**< I3C0 FCLK Slow Selection, offset: 0x544 */
69634   __IO uint32_t MICFILFCLKSEL;                     /**< MICFIL Clock Selection, offset: 0x548 */
69635   __IO uint32_t MICFILFCLKDIV;                     /**< MICFIL Clock Division, offset: 0x54C */
69636        uint8_t RESERVED_29[8];
69637   __IO uint32_t USDHCCLKSEL;                       /**< uSDHC Clock Selection, offset: 0x558 */
69638   __IO uint32_t USDHCCLKDIV;                       /**< uSDHC Function Clock Divider, offset: 0x55C */
69639   __IO uint32_t FLEXIOCLKSEL;                      /**< FLEXIO Clock Selection, offset: 0x560 */
69640   __IO uint32_t FLEXIOCLKDIV;                      /**< FLEXIO Function Clock Divider, offset: 0x564 */
69641        uint8_t RESERVED_30[56];
69642   __IO uint32_t FLEXCAN0CLKSEL;                    /**< FLEXCAN0 Clock Selection, offset: 0x5A0 */
69643   __IO uint32_t FLEXCAN0CLKDIV;                    /**< FLEXCAN0 Function Clock Divider, offset: 0x5A4 */
69644   __IO uint32_t FLEXCAN1CLKSEL;                    /**< FLEXCAN1 Clock Selection, offset: 0x5A8 */
69645   __IO uint32_t FLEXCAN1CLKDIV;                    /**< FLEXCAN1 Function Clock Divider, offset: 0x5AC */
69646   __IO uint32_t ENETRMIICLKSEL;                    /**< Ethernet RMII Clock Selection, offset: 0x5B0 */
69647   __IO uint32_t ENETRMIICLKDIV;                    /**< Ethernet RMII Function Clock Divider, offset: 0x5B4 */
69648   __IO uint32_t ENETPTPREFCLKSEL;                  /**< Ethernet PTP REF Clock Selection, offset: 0x5B8 */
69649   __IO uint32_t ENETPTPREFCLKDIV;                  /**< Ethernet PTP REF Function Clock Divider, offset: 0x5BC */
69650   __IO uint32_t ENET_PHY_INTF_SEL;                 /**< Ethernet PHY Interface Select, offset: 0x5C0 */
69651   __IO uint32_t ENET_SBD_FLOW_CTRL;                /**< Sideband Flow Control, offset: 0x5C4 */
69652        uint8_t RESERVED_31[12];
69653   __IO uint32_t EWM0CLKSEL;                        /**< EWM0 Clock Selection, offset: 0x5D4 */
69654   __IO uint32_t WDT1CLKSEL;                        /**< WDT1 Clock Selection, offset: 0x5D8 */
69655   __IO uint32_t WDT1CLKDIV;                        /**< WDT1 Function Clock Divider, offset: 0x5DC */
69656   __IO uint32_t OSTIMERCLKSEL;                     /**< OSTIMER Clock Selection, offset: 0x5E0 */
69657        uint8_t RESERVED_32[12];
69658   __IO uint32_t CMP0FCLKSEL;                       /**< CMP0 Function Clock Selection, offset: 0x5F0 */
69659   __IO uint32_t CMP0FCLKDIV;                       /**< CMP0 Function Clock Divider, offset: 0x5F4 */
69660   __IO uint32_t CMP0RRCLKSEL;                      /**< CMP0 Round Robin Clock Selection, offset: 0x5F8 */
69661   __IO uint32_t CMP0RRCLKDIV;                      /**< CMP0 Round Robin Clock Divider, offset: 0x5FC */
69662   __IO uint32_t CMP1FCLKSEL;                       /**< CMP1 Function Clock Selection, offset: 0x600 */
69663   __IO uint32_t CMP1FCLKDIV;                       /**< CMP1 Function Clock Divider, offset: 0x604 */
69664   __IO uint32_t CMP1RRCLKSEL;                      /**< CMP1 Round Robin Clock Source Select, offset: 0x608 */
69665   __IO uint32_t CMP1RRCLKDIV;                      /**< CMP1 Round Robin Clock Division, offset: 0x60C */
69666   __IO uint32_t CMP2FCLKSEL;                       /**< CMP2 Function Clock Source Select, offset: 0x610 */
69667   __IO uint32_t CMP2FCLKDIV;                       /**< CMP2 Function Clock Division, offset: 0x614 */
69668   __IO uint32_t CMP2RRCLKSEL;                      /**< CMP2 Round Robin Clock Source Select, offset: 0x618 */
69669   __IO uint32_t CMP2RRCLKDIV;                      /**< CMP2 Round Robin Clock Division, offset: 0x61C */
69670        uint8_t RESERVED_33[480];
69671   __IO uint32_t CPUCTRL;                           /**< CPU Control for Multiple Processors, offset: 0x800 */
69672   __IO uint32_t CPBOOT;                            /**< Coprocessor Boot Address, offset: 0x804 */
69673        uint8_t RESERVED_34[4];
69674   __I  uint32_t CPUSTAT;                           /**< CPU Status, offset: 0x80C */
69675        uint8_t RESERVED_35[20];
69676   __IO uint32_t LPCAC_CTRL;                        /**< LPCAC Control, offset: 0x824 */
69677        uint8_t RESERVED_36[40];
69678   __IO uint32_t FLEXCOMMCLKDIV[10];                /**< LP_FLEXCOMM Clock Divider, array offset: 0x850, array step: 0x4 */
69679   __IO uint32_t UTICKCLKSEL;                       /**< UTICK Function Clock Source Select, offset: 0x878 */
69680        uint8_t RESERVED_37[4];
69681   __IO uint32_t SAI0CLKSEL;                        /**< SAI0 Function Clock Source Select, offset: 0x880 */
69682   __IO uint32_t SAI1CLKSEL;                        /**< SAI1 Function Clock Source Select, offset: 0x884 */
69683   __IO uint32_t SAI0CLKDIV;                        /**< SAI0 Function Clock Division, offset: 0x888 */
69684   __IO uint32_t SAI1CLKDIV;                        /**< SAI1 Function Clock Division, offset: 0x88C */
69685   __IO uint32_t EMVSIM0CLKSEL;                     /**< EMVSIM0 Clock Source Select, offset: 0x890 */
69686   __IO uint32_t EMVSIM1CLKSEL;                     /**< EMVSIM1 Clock Source Select, offset: 0x894 */
69687   __IO uint32_t EMVSIM0CLKDIV;                     /**< EMVSIM0 Function Clock Division, offset: 0x898 */
69688   __IO uint32_t EMVSIM1CLKDIV;                     /**< EMVSIM1 Function Clock Division, offset: 0x89C */
69689        uint8_t RESERVED_38[176];
69690   __IO uint32_t KEY_RETAIN_CTRL;                   /**< Key Retain Control, offset: 0x950 */
69691        uint8_t RESERVED_39[12];
69692   __IO uint32_t REF_CLK_CTRL;                      /**< FRO 48MHz Reference Clock Control, offset: 0x960 */
69693   __O  uint32_t REF_CLK_CTRL_SET;                  /**< FRO 48MHz Reference Clock Control Set, offset: 0x964 */
69694   __O  uint32_t REF_CLK_CTRL_CLR;                  /**< FRO 48MHz Reference Clock Control Clear, offset: 0x968 */
69695   __IO uint32_t GDET_CTRL[2];                      /**< GDET Control Register, array offset: 0x96C, array step: 0x4 */
69696   __IO uint32_t ELS_ASSET_PROT;                    /**< ELS Asset Protection Register, offset: 0x974 */
69697   __IO uint32_t ELS_LOCK_CTRL;                     /**< ELS Lock Control, offset: 0x978 */
69698   __IO uint32_t ELS_LOCK_CTRL_DP;                  /**< ELS Lock Control DP, offset: 0x97C */
69699   __I  uint32_t ELS_OTP_LC_STATE;                  /**< Life Cycle State Register, offset: 0x980 */
69700   __I  uint32_t ELS_OTP_LC_STATE_DP;               /**< Life Cycle State Register (Duplicate), offset: 0x984 */
69701   __IO uint32_t ELS_TEMPORAL_STATE;                /**< ELS Temporal State, offset: 0x988 */
69702   __IO uint32_t ELS_KDF_MASK;                      /**< Key Derivation Function Mask, offset: 0x98C */
69703        uint8_t RESERVED_40[64];
69704   __I  uint32_t ELS_AS_CFG0;                       /**< ELS AS Configuration, offset: 0x9D0 */
69705   __I  uint32_t ELS_AS_CFG1;                       /**< ELS AS Configuration1, offset: 0x9D4 */
69706   __I  uint32_t ELS_AS_CFG2;                       /**< ELS AS Configuration2, offset: 0x9D8 */
69707   __I  uint32_t ELS_AS_CFG3;                       /**< ELS AS Configuration3, offset: 0x9DC */
69708   __I  uint32_t ELS_AS_ST0;                        /**< ELS AS State Register, offset: 0x9E0 */
69709   __I  uint32_t ELS_AS_ST1;                        /**< ELS AS State1, offset: 0x9E4 */
69710   __I  uint32_t ELS_AS_BOOT_LOG0;                  /**< Boot state captured during boot: Main ROM log, offset: 0x9E8 */
69711   __I  uint32_t ELS_AS_BOOT_LOG1;                  /**< Boot state captured during boot: Library log, offset: 0x9EC */
69712   __I  uint32_t ELS_AS_BOOT_LOG2;                  /**< Boot state captured during boot: Hardware status signals log, offset: 0x9F0 */
69713   __I  uint32_t ELS_AS_BOOT_LOG3;                  /**< Boot state captured during boot: Security log, offset: 0x9F4 */
69714   __I  uint32_t ELS_AS_FLAG0;                      /**< ELS AS Flag0, offset: 0x9F8 */
69715   __I  uint32_t ELS_AS_FLAG1;                      /**< ELS AS Flag1, offset: 0x9FC */
69716        uint8_t RESERVED_41[24];
69717   __IO uint32_t CLOCK_CTRL;                        /**< Clock Control, offset: 0xA18 */
69718        uint8_t RESERVED_42[276];
69719   __IO uint32_t I3C1FCLKSEL;                       /**< I3C1 Functional Clock Selection, offset: 0xB30 */
69720   __IO uint32_t I3C1FCLKSTCSEL;                    /**< Selects the I3C1 Time Control clock, offset: 0xB34 */
69721   __IO uint32_t I3C1FCLKSTCDIV;                    /**< I3C1 FCLK_STC Clock Divider, offset: 0xB38 */
69722   __IO uint32_t I3C1FCLKSDIV;                      /**< I3C1 FCLK Slow clock Divider, offset: 0xB3C */
69723   __IO uint32_t I3C1FCLKDIV;                       /**< I3C1 Functional Clock FCLK Divider, offset: 0xB40 */
69724   __IO uint32_t I3C1FCLKSSEL;                      /**< I3C1 FCLK Slow Selection, offset: 0xB44 */
69725        uint8_t RESERVED_43[8];
69726   __IO uint32_t ETB_STATUS;                        /**< ETB Counter Status Register, offset: 0xB50 */
69727   __IO uint32_t ETB_COUNTER_CTRL;                  /**< ETB Counter Control Register, offset: 0xB54 */
69728   __IO uint32_t ETB_COUNTER_RELOAD;                /**< ETB Counter Reload Register, offset: 0xB58 */
69729   __I  uint32_t ETB_COUNTER_VALUE;                 /**< ETB Counter Value Register, offset: 0xB5C */
69730   __IO uint32_t GRAY_CODE_LSB;                     /**< Gray to Binary Converter Gray code_gray[31:0], offset: 0xB60 */
69731   __IO uint32_t GRAY_CODE_MSB;                     /**< Gray to Binary Converter Gray code_gray[41:32], offset: 0xB64 */
69732   __I  uint32_t BINARY_CODE_LSB;                   /**< Gray to Binary Converter Binary Code [31:0], offset: 0xB68 */
69733   __I  uint32_t BINARY_CODE_MSB;                   /**< Gray to Binary Converter Binary Code [41:32], offset: 0xB6C */
69734        uint8_t RESERVED_44[660];
69735   __IO uint32_t AUTOCLKGATEOVERRIDE;               /**< Control Automatic Clock Gating, offset: 0xE04 */
69736        uint8_t RESERVED_45[36];
69737   __IO uint32_t AUTOCLKGATEOVERRIDEC;              /**< Control Automatic Clock Gating C, offset: 0xE2C */
69738        uint8_t RESERVED_46[8];
69739   __IO uint32_t PWM0SUBCTL;                        /**< PWM0 Submodule Control, offset: 0xE38 */
69740   __IO uint32_t PWM1SUBCTL;                        /**< PWM1 Submodule Control, offset: 0xE3C */
69741   __IO uint32_t CTIMERGLOBALSTARTEN;               /**< CTIMER Global Start Enable, offset: 0xE40 */
69742   __IO uint32_t ECC_ENABLE_CTRL;                   /**< RAM ECC Enable Control, offset: 0xE44 */
69743        uint8_t RESERVED_47[344];
69744   __IO uint32_t DEBUG_LOCK_EN;                     /**< Control Write Access to Security, offset: 0xFA0 */
69745   __IO uint32_t DEBUG_FEATURES;                    /**< Cortex Debug Features Control, offset: 0xFA4 */
69746   __IO uint32_t DEBUG_FEATURES_DP;                 /**< Cortex Debug Features Control (Duplicate), offset: 0xFA8 */
69747        uint8_t RESERVED_48[8];
69748   __IO uint32_t SWD_ACCESS_CPU[2];                 /**< CPU0 Software Debug Access..CPU1 Software Debug Access, array offset: 0xFB4, array step: 0x4 */
69749        uint8_t RESERVED_49[4];
69750   __IO uint32_t DEBUG_AUTH_BEACON;                 /**< Debug Authentication BEACON, offset: 0xFC0 */
69751   __IO uint32_t SWD_ACCESS_DSP;                    /**< DSP Software Debug Access, offset: 0xFC4 */
69752        uint8_t RESERVED_50[40];
69753   __I  uint32_t JTAG_ID;                           /**< JTAG Chip ID, offset: 0xFF0 */
69754   __I  uint32_t DEVICE_TYPE;                       /**< Device Type, offset: 0xFF4 */
69755   __I  uint32_t DEVICE_ID0;                        /**< Device ID, offset: 0xFF8 */
69756   __I  uint32_t DIEID;                             /**< Chip Revision ID and Number, offset: 0xFFC */
69757 } SYSCON_Type;
69758 
69759 /* ----------------------------------------------------------------------------
69760    -- SYSCON Register Masks
69761    ---------------------------------------------------------------------------- */
69762 
69763 /*!
69764  * @addtogroup SYSCON_Register_Masks SYSCON Register Masks
69765  * @{
69766  */
69767 
69768 /*! @name AHBMATPRIO - AHB Matrix Priority Control */
69769 /*! @{ */
69770 
69771 #define SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_MASK     (0x3U)
69772 #define SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_SHIFT    (0U)
69773 /*! PRI_CPU0_CBUS - CPU0 C-AHB bus master priority level
69774  *  0b00..level 0
69775  *  0b01..level 1
69776  *  0b10..level 2
69777  *  0b11..level 3
69778  */
69779 #define SYSCON_AHBMATPRIO_PRI_CPU0_CBUS(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_MASK)
69780 
69781 #define SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_MASK     (0xCU)
69782 #define SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_SHIFT    (2U)
69783 /*! PRI_CPU0_SBUS - CPU0 S-AHB bus master priority level
69784  *  0b00..level 0
69785  *  0b01..level 1
69786  *  0b10..level 2
69787  *  0b11..level 3
69788  */
69789 #define SYSCON_AHBMATPRIO_PRI_CPU0_SBUS(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_MASK)
69790 
69791 #define SYSCON_AHBMATPRIO_PRI_CPU1_SBUS_SmartDMA_D_MASK (0x30U)
69792 #define SYSCON_AHBMATPRIO_PRI_CPU1_SBUS_SmartDMA_D_SHIFT (4U)
69793 /*! PRI_CPU1_SBUS_SmartDMA_D - CPU1 S-AHB/SmartDMA-D bus master priority level
69794  *  0b00..level 0
69795  *  0b01..level 1
69796  *  0b10..level 2
69797  *  0b11..level 3
69798  */
69799 #define SYSCON_AHBMATPRIO_PRI_CPU1_SBUS_SmartDMA_D(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_CPU1_SBUS_SmartDMA_D_SHIFT)) & SYSCON_AHBMATPRIO_PRI_CPU1_SBUS_SmartDMA_D_MASK)
69800 
69801 #define SYSCON_AHBMATPRIO_PRI_CPU1_CBUS_SmartDMA_I_MASK (0xC0U)
69802 #define SYSCON_AHBMATPRIO_PRI_CPU1_CBUS_SmartDMA_I_SHIFT (6U)
69803 /*! PRI_CPU1_CBUS_SmartDMA_I - CPU1 C-AHB/SmartDMA-I bus master priority level
69804  *  0b00..level 0
69805  *  0b01..level 1
69806  *  0b10..level 2
69807  *  0b11..level 3
69808  */
69809 #define SYSCON_AHBMATPRIO_PRI_CPU1_CBUS_SmartDMA_I(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_CPU1_CBUS_SmartDMA_I_SHIFT)) & SYSCON_AHBMATPRIO_PRI_CPU1_CBUS_SmartDMA_I_MASK)
69810 
69811 #define SYSCON_AHBMATPRIO_DMA0_MASK              (0x300U)
69812 #define SYSCON_AHBMATPRIO_DMA0_SHIFT             (8U)
69813 /*! DMA0 - DMA0 controller bus master priority level
69814  *  0b00..level 0
69815  *  0b01..level 1
69816  *  0b10..level 2
69817  *  0b11..level 3
69818  */
69819 #define SYSCON_AHBMATPRIO_DMA0(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_DMA0_SHIFT)) & SYSCON_AHBMATPRIO_DMA0_MASK)
69820 
69821 #define SYSCON_AHBMATPRIO_DMA1_MASK              (0xC00U)
69822 #define SYSCON_AHBMATPRIO_DMA1_SHIFT             (10U)
69823 /*! DMA1 - DMA1 controller bus master priority level
69824  *  0b00..level 0
69825  *  0b01..level 1
69826  *  0b10..level 2
69827  *  0b11..level 3
69828  */
69829 #define SYSCON_AHBMATPRIO_DMA1(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_DMA1_SHIFT)) & SYSCON_AHBMATPRIO_DMA1_MASK)
69830 
69831 #define SYSCON_AHBMATPRIO_PRI_PKC_ELS_MASK       (0x3000U)
69832 #define SYSCON_AHBMATPRIO_PRI_PKC_ELS_SHIFT      (12U)
69833 /*! PRI_PKC_ELS - PKC and ELS bus master priority level
69834  *  0b00..level 0
69835  *  0b01..level 1
69836  *  0b10..level 2
69837  *  0b11..level 3
69838  */
69839 #define SYSCON_AHBMATPRIO_PRI_PKC_ELS(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_PKC_ELS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_PKC_ELS_MASK)
69840 
69841 #define SYSCON_AHBMATPRIO_PRI_NPU_PQ_MASK        (0xC000U)
69842 #define SYSCON_AHBMATPRIO_PRI_NPU_PQ_SHIFT       (14U)
69843 /*! PRI_NPU_PQ - NPU O bus and Powerquad bus master priority level
69844  *  0b00..level 0
69845  *  0b01..level 1
69846  *  0b10..level 2
69847  *  0b11..level 3
69848  */
69849 #define SYSCON_AHBMATPRIO_PRI_NPU_PQ(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_NPU_PQ_SHIFT)) & SYSCON_AHBMATPRIO_PRI_NPU_PQ_MASK)
69850 
69851 #define SYSCON_AHBMATPRIO_PRI_COOLFLUX_I_MASK    (0x30000U)
69852 #define SYSCON_AHBMATPRIO_PRI_COOLFLUX_I_SHIFT   (16U)
69853 /*! PRI_COOLFLUX_I - CoolFlux I bus master priority level
69854  *  0b00..level 0
69855  *  0b01..level 1
69856  *  0b10..level 2
69857  *  0b11..level 3
69858  */
69859 #define SYSCON_AHBMATPRIO_PRI_COOLFLUX_I(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_COOLFLUX_I_SHIFT)) & SYSCON_AHBMATPRIO_PRI_COOLFLUX_I_MASK)
69860 
69861 #define SYSCON_AHBMATPRIO_PRI_COOLFLUX_X_MASK    (0xC0000U)
69862 #define SYSCON_AHBMATPRIO_PRI_COOLFLUX_X_SHIFT   (18U)
69863 /*! PRI_COOLFLUX_X - CoolFlux X bus master priority level
69864  *  0b00..level 0
69865  *  0b01..level 1
69866  *  0b10..level 2
69867  *  0b11..level 3
69868  */
69869 #define SYSCON_AHBMATPRIO_PRI_COOLFLUX_X(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_COOLFLUX_X_SHIFT)) & SYSCON_AHBMATPRIO_PRI_COOLFLUX_X_MASK)
69870 
69871 #define SYSCON_AHBMATPRIO_PRI_COOLFLUX_Y_ESPI_MASK (0x300000U)
69872 #define SYSCON_AHBMATPRIO_PRI_COOLFLUX_Y_ESPI_SHIFT (20U)
69873 /*! PRI_COOLFLUX_Y_ESPI - CoolFlux Y bus master priority level
69874  *  0b00..level 0
69875  *  0b01..level 1
69876  *  0b10..level 2
69877  *  0b11..level 3
69878  */
69879 #define SYSCON_AHBMATPRIO_PRI_COOLFLUX_Y_ESPI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_COOLFLUX_Y_ESPI_SHIFT)) & SYSCON_AHBMATPRIO_PRI_COOLFLUX_Y_ESPI_MASK)
69880 
69881 #define SYSCON_AHBMATPRIO_PRI_NPU_D_MASK         (0xC00000U)
69882 #define SYSCON_AHBMATPRIO_PRI_NPU_D_SHIFT        (22U)
69883 /*! PRI_NPU_D - NPU D bus master priority level
69884  *  0b00..level 0
69885  *  0b01..level 1
69886  *  0b10..level 2
69887  *  0b11..level 3
69888  */
69889 #define SYSCON_AHBMATPRIO_PRI_NPU_D(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_NPU_D_SHIFT)) & SYSCON_AHBMATPRIO_PRI_NPU_D_MASK)
69890 
69891 #define SYSCON_AHBMATPRIO_PRI_USB_FS_ENET_MASK   (0x3000000U)
69892 #define SYSCON_AHBMATPRIO_PRI_USB_FS_ENET_SHIFT  (24U)
69893 /*! PRI_USB_FS_ENET - USB-FS and ENET bus master priority level
69894  *  0b00..level 0
69895  *  0b01..level 1
69896  *  0b10..level 2
69897  *  0b11..level 3
69898  */
69899 #define SYSCON_AHBMATPRIO_PRI_USB_FS_ENET(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB_FS_ENET_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB_FS_ENET_MASK)
69900 
69901 #define SYSCON_AHBMATPRIO_PRI_USB_HS_MASK        (0xC000000U)
69902 #define SYSCON_AHBMATPRIO_PRI_USB_HS_SHIFT       (26U)
69903 /*! PRI_USB_HS - USB-HS bus master priority level
69904  *  0b00..level 0
69905  *  0b01..level 1
69906  *  0b10..level 2
69907  *  0b11..level 3
69908  */
69909 #define SYSCON_AHBMATPRIO_PRI_USB_HS(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB_HS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB_HS_MASK)
69910 
69911 #define SYSCON_AHBMATPRIO_PRI_USDHC_MASK         (0x30000000U)
69912 #define SYSCON_AHBMATPRIO_PRI_USDHC_SHIFT        (28U)
69913 /*! PRI_USDHC - USDHC bus master priority level
69914  *  0b00..level 0
69915  *  0b01..level 1
69916  *  0b10..level 2
69917  *  0b11..level 3
69918  */
69919 #define SYSCON_AHBMATPRIO_PRI_USDHC(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USDHC_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USDHC_MASK)
69920 /*! @} */
69921 
69922 /*! @name CPU0STCKCAL - Secure CPU0 System Tick Calibration */
69923 /*! @{ */
69924 
69925 #define SYSCON_CPU0STCKCAL_TENMS_MASK            (0xFFFFFFU)
69926 #define SYSCON_CPU0STCKCAL_TENMS_SHIFT           (0U)
69927 /*! TENMS - Reload value for 10 ms (100 Hz) timing, subject to system clock skew errors. If the
69928  *    value reads as zero, the calibration value is not known.
69929  */
69930 #define SYSCON_CPU0STCKCAL_TENMS(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_TENMS_SHIFT)) & SYSCON_CPU0STCKCAL_TENMS_MASK)
69931 
69932 #define SYSCON_CPU0STCKCAL_SKEW_MASK             (0x1000000U)
69933 #define SYSCON_CPU0STCKCAL_SKEW_SHIFT            (24U)
69934 /*! SKEW - Whether the TENMS value is exact.
69935  *  0b0..TENMS value is exact
69936  *  0b1..TENMS value is not exact or not given
69937  */
69938 #define SYSCON_CPU0STCKCAL_SKEW(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_SKEW_SHIFT)) & SYSCON_CPU0STCKCAL_SKEW_MASK)
69939 
69940 #define SYSCON_CPU0STCKCAL_NOREF_MASK            (0x2000000U)
69941 #define SYSCON_CPU0STCKCAL_NOREF_SHIFT           (25U)
69942 /*! NOREF - Whether the device provides a reference clock to the processor.
69943  *  0b0..Reference clock is provided
69944  *  0b1..No reference clock is provided
69945  */
69946 #define SYSCON_CPU0STCKCAL_NOREF(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_NOREF_SHIFT)) & SYSCON_CPU0STCKCAL_NOREF_MASK)
69947 /*! @} */
69948 
69949 /*! @name CPU0NSTCKCAL - Non-Secure CPU0 System Tick Calibration */
69950 /*! @{ */
69951 
69952 #define SYSCON_CPU0NSTCKCAL_TENMS_MASK           (0xFFFFFFU)
69953 #define SYSCON_CPU0NSTCKCAL_TENMS_SHIFT          (0U)
69954 /*! TENMS - Reload value for 10 ms (100 Hz) timing, subject to system clock skew errors. If the
69955  *    value reads as zero, the calibration value is not known.
69956  */
69957 #define SYSCON_CPU0NSTCKCAL_TENMS(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_TENMS_SHIFT)) & SYSCON_CPU0NSTCKCAL_TENMS_MASK)
69958 
69959 #define SYSCON_CPU0NSTCKCAL_SKEW_MASK            (0x1000000U)
69960 #define SYSCON_CPU0NSTCKCAL_SKEW_SHIFT           (24U)
69961 /*! SKEW - Indicates whether the TENMS value is exact.
69962  *  0b0..TENMS value is exact
69963  *  0b1..TENMS value is not exact or not given
69964  */
69965 #define SYSCON_CPU0NSTCKCAL_SKEW(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_SKEW_SHIFT)) & SYSCON_CPU0NSTCKCAL_SKEW_MASK)
69966 
69967 #define SYSCON_CPU0NSTCKCAL_NOREF_MASK           (0x2000000U)
69968 #define SYSCON_CPU0NSTCKCAL_NOREF_SHIFT          (25U)
69969 /*! NOREF - Indicates whether the device provides a reference clock to the processor.
69970  *  0b0..Reference clock is provided
69971  *  0b1..No reference clock is provided
69972  */
69973 #define SYSCON_CPU0NSTCKCAL_NOREF(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_NOREF_SHIFT)) & SYSCON_CPU0NSTCKCAL_NOREF_MASK)
69974 /*! @} */
69975 
69976 /*! @name CPU1STCKCAL - System tick calibration for CPU1 */
69977 /*! @{ */
69978 
69979 #define SYSCON_CPU1STCKCAL_TENMS_MASK            (0xFFFFFFU)
69980 #define SYSCON_CPU1STCKCAL_TENMS_SHIFT           (0U)
69981 /*! TENMS - Reload value for 10 ms (100 Hz) timing, subject to system clock skew errors. If the
69982  *    value reads as zero, the calibration value is not known.
69983  */
69984 #define SYSCON_CPU1STCKCAL_TENMS(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU1STCKCAL_TENMS_SHIFT)) & SYSCON_CPU1STCKCAL_TENMS_MASK)
69985 
69986 #define SYSCON_CPU1STCKCAL_SKEW_MASK             (0x1000000U)
69987 #define SYSCON_CPU1STCKCAL_SKEW_SHIFT            (24U)
69988 /*! SKEW - Indicates whether the TENMS value is exact.
69989  *  0b0..TENMS value is exact
69990  *  0b1..TENMS value is not exact or not given
69991  */
69992 #define SYSCON_CPU1STCKCAL_SKEW(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU1STCKCAL_SKEW_SHIFT)) & SYSCON_CPU1STCKCAL_SKEW_MASK)
69993 
69994 #define SYSCON_CPU1STCKCAL_NOREF_MASK            (0x2000000U)
69995 #define SYSCON_CPU1STCKCAL_NOREF_SHIFT           (25U)
69996 /*! NOREF - Indicates whether the device provides a reference clock to the processor.
69997  *  0b0..Reference clock is provided
69998  *  0b1..No reference clock is provided
69999  */
70000 #define SYSCON_CPU1STCKCAL_NOREF(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU1STCKCAL_NOREF_SHIFT)) & SYSCON_CPU1STCKCAL_NOREF_MASK)
70001 /*! @} */
70002 
70003 /*! @name NMISRC - NMI Source Select */
70004 /*! @{ */
70005 
70006 #define SYSCON_NMISRC_IRQCPU0_MASK               (0xFFU)
70007 #define SYSCON_NMISRC_IRQCPU0_SHIFT              (0U)
70008 /*! IRQCPU0 - The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for CPU0, if enabled by NMIENCPU0. */
70009 #define SYSCON_NMISRC_IRQCPU0(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQCPU0_SHIFT)) & SYSCON_NMISRC_IRQCPU0_MASK)
70010 
70011 #define SYSCON_NMISRC_IRQCPU1_MASK               (0xFF00U)
70012 #define SYSCON_NMISRC_IRQCPU1_SHIFT              (8U)
70013 /*! IRQCPU1 - The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for CPU1, if enabled by NMIENCPU1. */
70014 #define SYSCON_NMISRC_IRQCPU1(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQCPU1_SHIFT)) & SYSCON_NMISRC_IRQCPU1_MASK)
70015 
70016 #define SYSCON_NMISRC_NMIENCPU1_MASK             (0x40000000U)
70017 #define SYSCON_NMISRC_NMIENCPU1_SHIFT            (30U)
70018 /*! NMIENCPU1 - Enables the Non-Maskable Interrupt (NMI) source selected by IRQCPU1.
70019  *  0b1..Enable.
70020  *  0b0..Disable.
70021  */
70022 #define SYSCON_NMISRC_NMIENCPU1(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENCPU1_SHIFT)) & SYSCON_NMISRC_NMIENCPU1_MASK)
70023 
70024 #define SYSCON_NMISRC_NMIENCPU0_MASK             (0x80000000U)
70025 #define SYSCON_NMISRC_NMIENCPU0_SHIFT            (31U)
70026 /*! NMIENCPU0 - Enables the Non-Maskable Interrupt (NMI) source selected by IRQCPU0.
70027  *  0b1..Enable.
70028  *  0b0..Disable.
70029  */
70030 #define SYSCON_NMISRC_NMIENCPU0(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENCPU0_SHIFT)) & SYSCON_NMISRC_NMIENCPU0_MASK)
70031 /*! @} */
70032 
70033 /*! @name PRESETCTRL0 - Peripheral Reset Control 0 */
70034 /*! @{ */
70035 
70036 #define SYSCON_PRESETCTRL0_FMU_RST_MASK          (0x200U)
70037 #define SYSCON_PRESETCTRL0_FMU_RST_SHIFT         (9U)
70038 /*! FMU_RST - Flash management unit reset control
70039  *  0b1..Block is reset
70040  *  0b0..Block is not reset
70041  */
70042 #define SYSCON_PRESETCTRL0_FMU_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_FMU_RST_SHIFT)) & SYSCON_PRESETCTRL0_FMU_RST_MASK)
70043 
70044 #define SYSCON_PRESETCTRL0_FLEXSPI_RST_MASK      (0x800U)
70045 #define SYSCON_PRESETCTRL0_FLEXSPI_RST_SHIFT     (11U)
70046 /*! FLEXSPI_RST - FlexSPI reset control
70047  *  0b1..Block is reset
70048  *  0b0..Block is not reset
70049  */
70050 #define SYSCON_PRESETCTRL0_FLEXSPI_RST(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_FLEXSPI_RST_SHIFT)) & SYSCON_PRESETCTRL0_FLEXSPI_RST_MASK)
70051 
70052 #define SYSCON_PRESETCTRL0_MUX_RST_MASK          (0x1000U)
70053 #define SYSCON_PRESETCTRL0_MUX_RST_SHIFT         (12U)
70054 /*! MUX_RST - INPUTMUX reset control
70055  *  0b1..Block is reset
70056  *  0b0..Block is not reset
70057  */
70058 #define SYSCON_PRESETCTRL0_MUX_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_MUX_RST_SHIFT)) & SYSCON_PRESETCTRL0_MUX_RST_MASK)
70059 
70060 #define SYSCON_PRESETCTRL0_PORT0_RST_MASK        (0x2000U)
70061 #define SYSCON_PRESETCTRL0_PORT0_RST_SHIFT       (13U)
70062 /*! PORT0_RST - PORT0 controller reset control
70063  *  0b1..Block is reset
70064  *  0b0..Block is not reset
70065  */
70066 #define SYSCON_PRESETCTRL0_PORT0_RST(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_PORT0_RST_SHIFT)) & SYSCON_PRESETCTRL0_PORT0_RST_MASK)
70067 
70068 #define SYSCON_PRESETCTRL0_PORT1_RST_MASK        (0x4000U)
70069 #define SYSCON_PRESETCTRL0_PORT1_RST_SHIFT       (14U)
70070 /*! PORT1_RST - PORT1 reset control
70071  *  0b1..Block is reset
70072  *  0b0..Block is not reset
70073  */
70074 #define SYSCON_PRESETCTRL0_PORT1_RST(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_PORT1_RST_SHIFT)) & SYSCON_PRESETCTRL0_PORT1_RST_MASK)
70075 
70076 #define SYSCON_PRESETCTRL0_PORT2_RST_MASK        (0x8000U)
70077 #define SYSCON_PRESETCTRL0_PORT2_RST_SHIFT       (15U)
70078 /*! PORT2_RST - PORT2 reset control
70079  *  0b1..Block is reset
70080  *  0b0..Block is not reset
70081  */
70082 #define SYSCON_PRESETCTRL0_PORT2_RST(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_PORT2_RST_SHIFT)) & SYSCON_PRESETCTRL0_PORT2_RST_MASK)
70083 
70084 #define SYSCON_PRESETCTRL0_PORT3_RST_MASK        (0x10000U)
70085 #define SYSCON_PRESETCTRL0_PORT3_RST_SHIFT       (16U)
70086 /*! PORT3_RST - PORT3 reset control
70087  *  0b1..Block is reset
70088  *  0b0..Block is not reset
70089  */
70090 #define SYSCON_PRESETCTRL0_PORT3_RST(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_PORT3_RST_SHIFT)) & SYSCON_PRESETCTRL0_PORT3_RST_MASK)
70091 
70092 #define SYSCON_PRESETCTRL0_PORT4_RST_MASK        (0x20000U)
70093 #define SYSCON_PRESETCTRL0_PORT4_RST_SHIFT       (17U)
70094 /*! PORT4_RST - PORT4 reset control
70095  *  0b1..Block is reset
70096  *  0b0..Block is not reset
70097  */
70098 #define SYSCON_PRESETCTRL0_PORT4_RST(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_PORT4_RST_SHIFT)) & SYSCON_PRESETCTRL0_PORT4_RST_MASK)
70099 
70100 #define SYSCON_PRESETCTRL0_GPIO0_RST_MASK        (0x80000U)
70101 #define SYSCON_PRESETCTRL0_GPIO0_RST_SHIFT       (19U)
70102 /*! GPIO0_RST - GPIO0 reset control
70103  *  0b1..Block is reset
70104  *  0b0..Block is not reset
70105  */
70106 #define SYSCON_PRESETCTRL0_GPIO0_RST(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO0_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO0_RST_MASK)
70107 
70108 #define SYSCON_PRESETCTRL0_GPIO1_RST_MASK        (0x100000U)
70109 #define SYSCON_PRESETCTRL0_GPIO1_RST_SHIFT       (20U)
70110 /*! GPIO1_RST - GPIO1 reset control
70111  *  0b1..Block is reset
70112  *  0b0..Block is not reset
70113  */
70114 #define SYSCON_PRESETCTRL0_GPIO1_RST(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO1_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO1_RST_MASK)
70115 
70116 #define SYSCON_PRESETCTRL0_GPIO2_RST_MASK        (0x200000U)
70117 #define SYSCON_PRESETCTRL0_GPIO2_RST_SHIFT       (21U)
70118 /*! GPIO2_RST - GPIO2 reset control
70119  *  0b1..Block is reset
70120  *  0b0..Block is not reset
70121  */
70122 #define SYSCON_PRESETCTRL0_GPIO2_RST(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO2_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO2_RST_MASK)
70123 
70124 #define SYSCON_PRESETCTRL0_GPIO3_RST_MASK        (0x400000U)
70125 #define SYSCON_PRESETCTRL0_GPIO3_RST_SHIFT       (22U)
70126 /*! GPIO3_RST - GPIO3 reset control
70127  *  0b1..Block is reset
70128  *  0b0..Block is not reset
70129  */
70130 #define SYSCON_PRESETCTRL0_GPIO3_RST(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO3_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO3_RST_MASK)
70131 
70132 #define SYSCON_PRESETCTRL0_GPIO4_RST_MASK        (0x800000U)
70133 #define SYSCON_PRESETCTRL0_GPIO4_RST_SHIFT       (23U)
70134 /*! GPIO4_RST - GPIO4 reset control
70135  *  0b1..Block is reset
70136  *  0b0..Block is not reset
70137  */
70138 #define SYSCON_PRESETCTRL0_GPIO4_RST(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO4_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO4_RST_MASK)
70139 
70140 #define SYSCON_PRESETCTRL0_PINT_RST_MASK         (0x2000000U)
70141 #define SYSCON_PRESETCTRL0_PINT_RST_SHIFT        (25U)
70142 /*! PINT_RST - PINT reset control
70143  *  0b1..Block is reset
70144  *  0b0..Block is not reset
70145  */
70146 #define SYSCON_PRESETCTRL0_PINT_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_PINT_RST_SHIFT)) & SYSCON_PRESETCTRL0_PINT_RST_MASK)
70147 
70148 #define SYSCON_PRESETCTRL0_DMA0_RST_MASK         (0x4000000U)
70149 #define SYSCON_PRESETCTRL0_DMA0_RST_SHIFT        (26U)
70150 /*! DMA0_RST - DMA0 reset control
70151  *  0b1..Block is reset
70152  *  0b0..Block is not reset
70153  */
70154 #define SYSCON_PRESETCTRL0_DMA0_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_DMA0_RST_SHIFT)) & SYSCON_PRESETCTRL0_DMA0_RST_MASK)
70155 
70156 #define SYSCON_PRESETCTRL0_CRC_RST_MASK          (0x8000000U)
70157 #define SYSCON_PRESETCTRL0_CRC_RST_SHIFT         (27U)
70158 /*! CRC_RST - CRC reset control
70159  *  0b1..Block is reset
70160  *  0b0..Block is not reset
70161  */
70162 #define SYSCON_PRESETCTRL0_CRC_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_CRC_RST_SHIFT)) & SYSCON_PRESETCTRL0_CRC_RST_MASK)
70163 
70164 #define SYSCON_PRESETCTRL0_MAILBOX_RST_MASK      (0x80000000U)
70165 #define SYSCON_PRESETCTRL0_MAILBOX_RST_SHIFT     (31U)
70166 /*! MAILBOX_RST - Inter-CPU communication Mailbox reset control
70167  *  0b1..Block is reset
70168  *  0b0..Block is not reset
70169  */
70170 #define SYSCON_PRESETCTRL0_MAILBOX_RST(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_MAILBOX_RST_SHIFT)) & SYSCON_PRESETCTRL0_MAILBOX_RST_MASK)
70171 /*! @} */
70172 
70173 /*! @name PRESETCTRL1 - Peripheral Reset Control 1 */
70174 /*! @{ */
70175 
70176 #define SYSCON_PRESETCTRL1_MRT_RST_MASK          (0x1U)
70177 #define SYSCON_PRESETCTRL1_MRT_RST_SHIFT         (0U)
70178 /*! MRT_RST - MRT reset control
70179  *  0b1..Block is reset
70180  *  0b0..Block is not reset
70181  */
70182 #define SYSCON_PRESETCTRL1_MRT_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_MRT_RST_SHIFT)) & SYSCON_PRESETCTRL1_MRT_RST_MASK)
70183 
70184 #define SYSCON_PRESETCTRL1_OSTIMER_RST_MASK      (0x2U)
70185 #define SYSCON_PRESETCTRL1_OSTIMER_RST_SHIFT     (1U)
70186 /*! OSTIMER_RST - OS Event Timer reset control
70187  *  0b1..Block is reset
70188  *  0b0..Block is not reset
70189  */
70190 #define SYSCON_PRESETCTRL1_OSTIMER_RST(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_OSTIMER_RST_SHIFT)) & SYSCON_PRESETCTRL1_OSTIMER_RST_MASK)
70191 
70192 #define SYSCON_PRESETCTRL1_SCT_RST_MASK          (0x4U)
70193 #define SYSCON_PRESETCTRL1_SCT_RST_SHIFT         (2U)
70194 /*! SCT_RST - SCT reset control
70195  *  0b1..Block is reset
70196  *  0b0..Block is not reset
70197  */
70198 #define SYSCON_PRESETCTRL1_SCT_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_SCT_RST_SHIFT)) & SYSCON_PRESETCTRL1_SCT_RST_MASK)
70199 
70200 #define SYSCON_PRESETCTRL1_ADC0_RST_MASK         (0x8U)
70201 #define SYSCON_PRESETCTRL1_ADC0_RST_SHIFT        (3U)
70202 /*! ADC0_RST - ADC0 reset control
70203  *  0b1..Block is reset
70204  *  0b0..Block is not reset
70205  */
70206 #define SYSCON_PRESETCTRL1_ADC0_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_ADC0_RST_SHIFT)) & SYSCON_PRESETCTRL1_ADC0_RST_MASK)
70207 
70208 #define SYSCON_PRESETCTRL1_ADC1_RST_MASK         (0x10U)
70209 #define SYSCON_PRESETCTRL1_ADC1_RST_SHIFT        (4U)
70210 /*! ADC1_RST - ADC1 reset control
70211  *  0b1..Block is reset
70212  *  0b0..Block is not reset
70213  */
70214 #define SYSCON_PRESETCTRL1_ADC1_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_ADC1_RST_SHIFT)) & SYSCON_PRESETCTRL1_ADC1_RST_MASK)
70215 
70216 #define SYSCON_PRESETCTRL1_DAC0_RST_MASK         (0x20U)
70217 #define SYSCON_PRESETCTRL1_DAC0_RST_SHIFT        (5U)
70218 /*! DAC0_RST - DAC0 reset control
70219  *  0b1..Block is reset
70220  *  0b0..Block is not reset
70221  */
70222 #define SYSCON_PRESETCTRL1_DAC0_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_DAC0_RST_SHIFT)) & SYSCON_PRESETCTRL1_DAC0_RST_MASK)
70223 
70224 #define SYSCON_PRESETCTRL1_RTC_RST_MASK          (0x40U)
70225 #define SYSCON_PRESETCTRL1_RTC_RST_SHIFT         (6U)
70226 /*! RTC_RST - RTC reset control
70227  *  0b1..Block is reset
70228  *  0b0..Block is not reset
70229  */
70230 #define SYSCON_PRESETCTRL1_RTC_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_RTC_RST_SHIFT)) & SYSCON_PRESETCTRL1_RTC_RST_MASK)
70231 
70232 #define SYSCON_PRESETCTRL1_EVSIM0_RST_MASK       (0x100U)
70233 #define SYSCON_PRESETCTRL1_EVSIM0_RST_SHIFT      (8U)
70234 /*! EVSIM0_RST - EVSIM0 reset control
70235  *  0b1..Block is reset
70236  *  0b0..Block is not reset
70237  */
70238 #define SYSCON_PRESETCTRL1_EVSIM0_RST(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_EVSIM0_RST_SHIFT)) & SYSCON_PRESETCTRL1_EVSIM0_RST_MASK)
70239 
70240 #define SYSCON_PRESETCTRL1_EVSIM1_RST_MASK       (0x200U)
70241 #define SYSCON_PRESETCTRL1_EVSIM1_RST_SHIFT      (9U)
70242 /*! EVSIM1_RST - EVSIM1 reset control
70243  *  0b1..Block is reset
70244  *  0b0..Block is not reset
70245  */
70246 #define SYSCON_PRESETCTRL1_EVSIM1_RST(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_EVSIM1_RST_SHIFT)) & SYSCON_PRESETCTRL1_EVSIM1_RST_MASK)
70247 
70248 #define SYSCON_PRESETCTRL1_UTICK_RST_MASK        (0x400U)
70249 #define SYSCON_PRESETCTRL1_UTICK_RST_SHIFT       (10U)
70250 /*! UTICK_RST - UTICK reset control
70251  *  0b1..Block is reset
70252  *  0b0..Block is not reset
70253  */
70254 #define SYSCON_PRESETCTRL1_UTICK_RST(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_UTICK_RST_SHIFT)) & SYSCON_PRESETCTRL1_UTICK_RST_MASK)
70255 
70256 #define SYSCON_PRESETCTRL1_FC0_RST_MASK          (0x800U)
70257 #define SYSCON_PRESETCTRL1_FC0_RST_SHIFT         (11U)
70258 /*! FC0_RST - LP_FLEXCOMM0 reset control
70259  *  0b1..Block is reset
70260  *  0b0..Block is not reset
70261  */
70262 #define SYSCON_PRESETCTRL1_FC0_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC0_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC0_RST_MASK)
70263 
70264 #define SYSCON_PRESETCTRL1_FC1_RST_MASK          (0x1000U)
70265 #define SYSCON_PRESETCTRL1_FC1_RST_SHIFT         (12U)
70266 /*! FC1_RST - LP_FLEXCOMM1 reset control
70267  *  0b1..Block is reset
70268  *  0b0..Block is not reset
70269  */
70270 #define SYSCON_PRESETCTRL1_FC1_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC1_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC1_RST_MASK)
70271 
70272 #define SYSCON_PRESETCTRL1_FC2_RST_MASK          (0x2000U)
70273 #define SYSCON_PRESETCTRL1_FC2_RST_SHIFT         (13U)
70274 /*! FC2_RST - LP_FLEXCOMM2 reset control
70275  *  0b1..Block is reset
70276  *  0b0..Block is not reset
70277  */
70278 #define SYSCON_PRESETCTRL1_FC2_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC2_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC2_RST_MASK)
70279 
70280 #define SYSCON_PRESETCTRL1_FC3_RST_MASK          (0x4000U)
70281 #define SYSCON_PRESETCTRL1_FC3_RST_SHIFT         (14U)
70282 /*! FC3_RST - LP_FLEXCOMM3 reset control
70283  *  0b1..Block is reset
70284  *  0b0..Block is not reset
70285  */
70286 #define SYSCON_PRESETCTRL1_FC3_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC3_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC3_RST_MASK)
70287 
70288 #define SYSCON_PRESETCTRL1_FC4_RST_MASK          (0x8000U)
70289 #define SYSCON_PRESETCTRL1_FC4_RST_SHIFT         (15U)
70290 /*! FC4_RST - LP_FLEXCOMM4 reset control
70291  *  0b1..Block is reset
70292  *  0b0..Block is not reset
70293  */
70294 #define SYSCON_PRESETCTRL1_FC4_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC4_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC4_RST_MASK)
70295 
70296 #define SYSCON_PRESETCTRL1_FC5_RST_MASK          (0x10000U)
70297 #define SYSCON_PRESETCTRL1_FC5_RST_SHIFT         (16U)
70298 /*! FC5_RST - LP_FLEXCOMM5 reset control
70299  *  0b1..Block is reset
70300  *  0b0..Block is not reset
70301  */
70302 #define SYSCON_PRESETCTRL1_FC5_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC5_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC5_RST_MASK)
70303 
70304 #define SYSCON_PRESETCTRL1_FC6_RST_MASK          (0x20000U)
70305 #define SYSCON_PRESETCTRL1_FC6_RST_SHIFT         (17U)
70306 /*! FC6_RST - LP_FLEXCOMM6 reset control
70307  *  0b1..Block is reset
70308  *  0b0..Block is not reset
70309  */
70310 #define SYSCON_PRESETCTRL1_FC6_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC6_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC6_RST_MASK)
70311 
70312 #define SYSCON_PRESETCTRL1_FC7_RST_MASK          (0x40000U)
70313 #define SYSCON_PRESETCTRL1_FC7_RST_SHIFT         (18U)
70314 /*! FC7_RST - LP_FLEXCOMM7 reset control
70315  *  0b1..Block is reset
70316  *  0b0..Block is not reset
70317  */
70318 #define SYSCON_PRESETCTRL1_FC7_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC7_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC7_RST_MASK)
70319 
70320 #define SYSCON_PRESETCTRL1_FC8_RST_MASK          (0x80000U)
70321 #define SYSCON_PRESETCTRL1_FC8_RST_SHIFT         (19U)
70322 /*! FC8_RST - LP_FLEXCOMM8 reset control
70323  *  0b1..Block is reset
70324  *  0b0..Block is not reset
70325  */
70326 #define SYSCON_PRESETCTRL1_FC8_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC8_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC8_RST_MASK)
70327 
70328 #define SYSCON_PRESETCTRL1_FC9_RST_MASK          (0x100000U)
70329 #define SYSCON_PRESETCTRL1_FC9_RST_SHIFT         (20U)
70330 /*! FC9_RST - LP_FLEXCOMM9 reset control
70331  *  0b1..Block is reset
70332  *  0b0..Block is not reset
70333  */
70334 #define SYSCON_PRESETCTRL1_FC9_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC9_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC9_RST_MASK)
70335 
70336 #define SYSCON_PRESETCTRL1_MICFIL_RST_MASK       (0x200000U)
70337 #define SYSCON_PRESETCTRL1_MICFIL_RST_SHIFT      (21U)
70338 /*! MICFIL_RST - MICFIL reset control
70339  *  0b1..Block is reset
70340  *  0b0..Block is not reset
70341  */
70342 #define SYSCON_PRESETCTRL1_MICFIL_RST(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_MICFIL_RST_SHIFT)) & SYSCON_PRESETCTRL1_MICFIL_RST_MASK)
70343 
70344 #define SYSCON_PRESETCTRL1_TIMER2_RST_MASK       (0x400000U)
70345 #define SYSCON_PRESETCTRL1_TIMER2_RST_SHIFT      (22U)
70346 /*! TIMER2_RST - CTIMER2 reset control
70347  *  0b1..Block is reset
70348  *  0b0..Block is not reset
70349  */
70350 #define SYSCON_PRESETCTRL1_TIMER2_RST(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER2_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER2_RST_MASK)
70351 
70352 #define SYSCON_PRESETCTRL1_USB0_FS_DCD_RST_MASK  (0x1000000U)
70353 #define SYSCON_PRESETCTRL1_USB0_FS_DCD_RST_SHIFT (24U)
70354 /*! USB0_FS_DCD_RST - USB FS DCD reset control
70355  *  0b1..Block is reset
70356  *  0b0..Block is not reset
70357  */
70358 #define SYSCON_PRESETCTRL1_USB0_FS_DCD_RST(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_USB0_FS_DCD_RST_SHIFT)) & SYSCON_PRESETCTRL1_USB0_FS_DCD_RST_MASK)
70359 
70360 #define SYSCON_PRESETCTRL1_USB0_FS_RST_MASK      (0x2000000U)
70361 #define SYSCON_PRESETCTRL1_USB0_FS_RST_SHIFT     (25U)
70362 /*! USB0_FS_RST - USB FS reset control
70363  *  0b1..Block is reset
70364  *  0b0..Block is not reset
70365  */
70366 #define SYSCON_PRESETCTRL1_USB0_FS_RST(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_USB0_FS_RST_SHIFT)) & SYSCON_PRESETCTRL1_USB0_FS_RST_MASK)
70367 
70368 #define SYSCON_PRESETCTRL1_TIMER0_RST_MASK       (0x4000000U)
70369 #define SYSCON_PRESETCTRL1_TIMER0_RST_SHIFT      (26U)
70370 /*! TIMER0_RST - CTIMER0 reset control
70371  *  0b1..Block is reset
70372  *  0b0..Block is not reset
70373  */
70374 #define SYSCON_PRESETCTRL1_TIMER0_RST(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER0_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER0_RST_MASK)
70375 
70376 #define SYSCON_PRESETCTRL1_TIMER1_RST_MASK       (0x8000000U)
70377 #define SYSCON_PRESETCTRL1_TIMER1_RST_SHIFT      (27U)
70378 /*! TIMER1_RST - CTIMER1 reset control
70379  *  0b1..Block is reset
70380  *  0b0..Block is not reset
70381  */
70382 #define SYSCON_PRESETCTRL1_TIMER1_RST(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER1_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER1_RST_MASK)
70383 
70384 #define SYSCON_PRESETCTRL1_SmartDMA_RST_MASK     (0x80000000U)
70385 #define SYSCON_PRESETCTRL1_SmartDMA_RST_SHIFT    (31U)
70386 /*! SmartDMA_RST - SmartDMA reset control
70387  *  0b1..Block is reset
70388  *  0b0..Block is not reset
70389  */
70390 #define SYSCON_PRESETCTRL1_SmartDMA_RST(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_SmartDMA_RST_SHIFT)) & SYSCON_PRESETCTRL1_SmartDMA_RST_MASK)
70391 /*! @} */
70392 
70393 /*! @name PRESETCTRL2 - Peripheral Reset Control 2 */
70394 /*! @{ */
70395 
70396 #define SYSCON_PRESETCTRL2_DMA1_RST_MASK         (0x2U)
70397 #define SYSCON_PRESETCTRL2_DMA1_RST_SHIFT        (1U)
70398 /*! DMA1_RST - DMA1 reset control
70399  *  0b1..Block is reset
70400  *  0b0..Block is not reset
70401  */
70402 #define SYSCON_PRESETCTRL2_DMA1_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_DMA1_RST_SHIFT)) & SYSCON_PRESETCTRL2_DMA1_RST_MASK)
70403 
70404 #define SYSCON_PRESETCTRL2_ENET_RST_MASK         (0x4U)
70405 #define SYSCON_PRESETCTRL2_ENET_RST_SHIFT        (2U)
70406 /*! ENET_RST - Ethernet reset control
70407  *  0b1..Block is reset
70408  *  0b0..Block is not reset
70409  */
70410 #define SYSCON_PRESETCTRL2_ENET_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_ENET_RST_SHIFT)) & SYSCON_PRESETCTRL2_ENET_RST_MASK)
70411 
70412 #define SYSCON_PRESETCTRL2_USDHC_RST_MASK        (0x8U)
70413 #define SYSCON_PRESETCTRL2_USDHC_RST_SHIFT       (3U)
70414 /*! USDHC_RST - uSDHC reset control
70415  *  0b1..Block is reset
70416  *  0b0..Block is not reset
70417  */
70418 #define SYSCON_PRESETCTRL2_USDHC_RST(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USDHC_RST_SHIFT)) & SYSCON_PRESETCTRL2_USDHC_RST_MASK)
70419 
70420 #define SYSCON_PRESETCTRL2_FLEXIO_RST_MASK       (0x10U)
70421 #define SYSCON_PRESETCTRL2_FLEXIO_RST_SHIFT      (4U)
70422 /*! FLEXIO_RST - FLEXIO reset control
70423  *  0b1..Block is reset
70424  *  0b0..Block is not reset
70425  */
70426 #define SYSCON_PRESETCTRL2_FLEXIO_RST(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_FLEXIO_RST_SHIFT)) & SYSCON_PRESETCTRL2_FLEXIO_RST_MASK)
70427 
70428 #define SYSCON_PRESETCTRL2_SAI0_RST_MASK         (0x20U)
70429 #define SYSCON_PRESETCTRL2_SAI0_RST_SHIFT        (5U)
70430 /*! SAI0_RST - SAI0 reset control
70431  *  0b1..Block is reset
70432  *  0b0..Block is not reset
70433  */
70434 #define SYSCON_PRESETCTRL2_SAI0_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_SAI0_RST_SHIFT)) & SYSCON_PRESETCTRL2_SAI0_RST_MASK)
70435 
70436 #define SYSCON_PRESETCTRL2_SAI1_RST_MASK         (0x40U)
70437 #define SYSCON_PRESETCTRL2_SAI1_RST_SHIFT        (6U)
70438 /*! SAI1_RST - SAI1 reset control
70439  *  0b1..Block is reset
70440  *  0b0..Block is not reset
70441  */
70442 #define SYSCON_PRESETCTRL2_SAI1_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_SAI1_RST_SHIFT)) & SYSCON_PRESETCTRL2_SAI1_RST_MASK)
70443 
70444 #define SYSCON_PRESETCTRL2_TRO_RST_MASK          (0x80U)
70445 #define SYSCON_PRESETCTRL2_TRO_RST_SHIFT         (7U)
70446 /*! TRO_RST - TRO reset control
70447  *  0b1..Block is reset
70448  *  0b0..Block is not reset
70449  */
70450 #define SYSCON_PRESETCTRL2_TRO_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_TRO_RST_SHIFT)) & SYSCON_PRESETCTRL2_TRO_RST_MASK)
70451 
70452 #define SYSCON_PRESETCTRL2_FREQME_RST_MASK       (0x100U)
70453 #define SYSCON_PRESETCTRL2_FREQME_RST_SHIFT      (8U)
70454 /*! FREQME_RST - FREQME reset control
70455  *  0b1..Block is reset
70456  *  0b0..Block is not reset
70457  */
70458 #define SYSCON_PRESETCTRL2_FREQME_RST(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_FREQME_RST_SHIFT)) & SYSCON_PRESETCTRL2_FREQME_RST_MASK)
70459 
70460 #define SYSCON_PRESETCTRL2_TRNG_RST_MASK         (0x2000U)
70461 #define SYSCON_PRESETCTRL2_TRNG_RST_SHIFT        (13U)
70462 /*! TRNG_RST - TRNG reset control
70463  *  0b1..Block is reset
70464  *  0b0..Block is not reset
70465  */
70466 #define SYSCON_PRESETCTRL2_TRNG_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_TRNG_RST_SHIFT)) & SYSCON_PRESETCTRL2_TRNG_RST_MASK)
70467 
70468 #define SYSCON_PRESETCTRL2_FLEXCAN0_RST_MASK     (0x4000U)
70469 #define SYSCON_PRESETCTRL2_FLEXCAN0_RST_SHIFT    (14U)
70470 /*! FLEXCAN0_RST - CAN0 reset control
70471  *  0b1..Block is reset
70472  *  0b0..Block is not reset
70473  */
70474 #define SYSCON_PRESETCTRL2_FLEXCAN0_RST(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_FLEXCAN0_RST_SHIFT)) & SYSCON_PRESETCTRL2_FLEXCAN0_RST_MASK)
70475 
70476 #define SYSCON_PRESETCTRL2_FLEXCAN1_RST_MASK     (0x8000U)
70477 #define SYSCON_PRESETCTRL2_FLEXCAN1_RST_SHIFT    (15U)
70478 /*! FLEXCAN1_RST - CAN1 reset control
70479  *  0b1..Block is reset
70480  *  0b0..Block is not reset
70481  */
70482 #define SYSCON_PRESETCTRL2_FLEXCAN1_RST(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_FLEXCAN1_RST_SHIFT)) & SYSCON_PRESETCTRL2_FLEXCAN1_RST_MASK)
70483 
70484 #define SYSCON_PRESETCTRL2_USB_HS_RST_MASK       (0x10000U)
70485 #define SYSCON_PRESETCTRL2_USB_HS_RST_SHIFT      (16U)
70486 /*! USB_HS_RST - USB HS reset control
70487  *  0b1..Block is reset
70488  *  0b0..Block is not reset
70489  */
70490 #define SYSCON_PRESETCTRL2_USB_HS_RST(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB_HS_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB_HS_RST_MASK)
70491 
70492 #define SYSCON_PRESETCTRL2_USB_HS_PHY_RST_MASK   (0x20000U)
70493 #define SYSCON_PRESETCTRL2_USB_HS_PHY_RST_SHIFT  (17U)
70494 /*! USB_HS_PHY_RST - USB HS PHY reset control
70495  *  0b1..Block is reset
70496  *  0b0..Block is not reset
70497  */
70498 #define SYSCON_PRESETCTRL2_USB_HS_PHY_RST(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB_HS_PHY_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB_HS_PHY_RST_MASK)
70499 
70500 #define SYSCON_PRESETCTRL2_PQ_RST_MASK           (0x80000U)
70501 #define SYSCON_PRESETCTRL2_PQ_RST_SHIFT          (19U)
70502 /*! PQ_RST - PowerQuad reset control
70503  *  0b1..Block is reset
70504  *  0b0..Block is not reset
70505  */
70506 #define SYSCON_PRESETCTRL2_PQ_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_PQ_RST_SHIFT)) & SYSCON_PRESETCTRL2_PQ_RST_MASK)
70507 
70508 #define SYSCON_PRESETCTRL2_PLU_RST_MASK          (0x100000U)
70509 #define SYSCON_PRESETCTRL2_PLU_RST_SHIFT         (20U)
70510 /*! PLU_RST - PLU reset control
70511  *  0b1..Block is reset
70512  *  0b0..Block is not reset
70513  */
70514 #define SYSCON_PRESETCTRL2_PLU_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_PLU_RST_SHIFT)) & SYSCON_PRESETCTRL2_PLU_RST_MASK)
70515 
70516 #define SYSCON_PRESETCTRL2_TIMER3_RST_MASK       (0x200000U)
70517 #define SYSCON_PRESETCTRL2_TIMER3_RST_SHIFT      (21U)
70518 /*! TIMER3_RST - CTIMER3 reset control
70519  *  0b1..Block is reset
70520  *  0b0..Block is not reset
70521  */
70522 #define SYSCON_PRESETCTRL2_TIMER3_RST(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_TIMER3_RST_SHIFT)) & SYSCON_PRESETCTRL2_TIMER3_RST_MASK)
70523 
70524 #define SYSCON_PRESETCTRL2_TIMER4_RST_MASK       (0x400000U)
70525 #define SYSCON_PRESETCTRL2_TIMER4_RST_SHIFT      (22U)
70526 /*! TIMER4_RST - CTIMER4 reset control
70527  *  0b1..Block is reset
70528  *  0b0..Block is not reset
70529  */
70530 #define SYSCON_PRESETCTRL2_TIMER4_RST(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_TIMER4_RST_SHIFT)) & SYSCON_PRESETCTRL2_TIMER4_RST_MASK)
70531 
70532 #define SYSCON_PRESETCTRL2_PUF_RST_MASK          (0x800000U)
70533 #define SYSCON_PRESETCTRL2_PUF_RST_SHIFT         (23U)
70534 /*! PUF_RST - PUF reset control
70535  *  0b1..Block is reset
70536  *  0b0..Block is not reset
70537  */
70538 #define SYSCON_PRESETCTRL2_PUF_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_PUF_RST_SHIFT)) & SYSCON_PRESETCTRL2_PUF_RST_MASK)
70539 
70540 #define SYSCON_PRESETCTRL2_PKC_RST_MASK          (0x1000000U)
70541 #define SYSCON_PRESETCTRL2_PKC_RST_SHIFT         (24U)
70542 /*! PKC_RST - PKC reset control
70543  *  0b1..Block is reset
70544  *  0b0..Block is not reset
70545  */
70546 #define SYSCON_PRESETCTRL2_PKC_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_PKC_RST_SHIFT)) & SYSCON_PRESETCTRL2_PKC_RST_MASK)
70547 
70548 #define SYSCON_PRESETCTRL2_SM3_RST_MASK          (0x40000000U)
70549 #define SYSCON_PRESETCTRL2_SM3_RST_SHIFT         (30U)
70550 /*! SM3_RST - SM3 reset control
70551  *  0b1..Block is reset
70552  *  0b0..Block is not reset
70553  */
70554 #define SYSCON_PRESETCTRL2_SM3_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_SM3_RST_SHIFT)) & SYSCON_PRESETCTRL2_SM3_RST_MASK)
70555 /*! @} */
70556 
70557 /*! @name PRESETCTRL3 - Peripheral Reset Control 3 */
70558 /*! @{ */
70559 
70560 #define SYSCON_PRESETCTRL3_I3C0_RST_MASK         (0x1U)
70561 #define SYSCON_PRESETCTRL3_I3C0_RST_SHIFT        (0U)
70562 /*! I3C0_RST - I3C0 reset control
70563  *  0b1..Block is reset
70564  *  0b0..Block is not reset
70565  */
70566 #define SYSCON_PRESETCTRL3_I3C0_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_I3C0_RST_SHIFT)) & SYSCON_PRESETCTRL3_I3C0_RST_MASK)
70567 
70568 #define SYSCON_PRESETCTRL3_I3C1_RST_MASK         (0x2U)
70569 #define SYSCON_PRESETCTRL3_I3C1_RST_SHIFT        (1U)
70570 /*! I3C1_RST - I3C1 reset control
70571  *  0b1..Block is reset
70572  *  0b0..Block is not reset
70573  */
70574 #define SYSCON_PRESETCTRL3_I3C1_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_I3C1_RST_SHIFT)) & SYSCON_PRESETCTRL3_I3C1_RST_MASK)
70575 
70576 #define SYSCON_PRESETCTRL3_SINC_RST_MASK         (0x4U)
70577 #define SYSCON_PRESETCTRL3_SINC_RST_SHIFT        (2U)
70578 /*! SINC_RST - SINC reset control
70579  *  0b1..Block is reset
70580  *  0b0..Block is not reset
70581  */
70582 #define SYSCON_PRESETCTRL3_SINC_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_SINC_RST_SHIFT)) & SYSCON_PRESETCTRL3_SINC_RST_MASK)
70583 
70584 #define SYSCON_PRESETCTRL3_COOLFLUX_RST_MASK     (0x8U)
70585 #define SYSCON_PRESETCTRL3_COOLFLUX_RST_SHIFT    (3U)
70586 /*! COOLFLUX_RST - CoolFlux reset control
70587  *  0b1..Block is reset
70588  *  0b0..Block is not reset
70589  */
70590 #define SYSCON_PRESETCTRL3_COOLFLUX_RST(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_COOLFLUX_RST_SHIFT)) & SYSCON_PRESETCTRL3_COOLFLUX_RST_MASK)
70591 
70592 #define SYSCON_PRESETCTRL3_QDC0_RST_MASK         (0x10U)
70593 #define SYSCON_PRESETCTRL3_QDC0_RST_SHIFT        (4U)
70594 /*! QDC0_RST - QDC0 reset control
70595  *  0b1..Block is reset
70596  *  0b0..Block is not reset
70597  */
70598 #define SYSCON_PRESETCTRL3_QDC0_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_QDC0_RST_SHIFT)) & SYSCON_PRESETCTRL3_QDC0_RST_MASK)
70599 
70600 #define SYSCON_PRESETCTRL3_QDC1_RST_MASK         (0x20U)
70601 #define SYSCON_PRESETCTRL3_QDC1_RST_SHIFT        (5U)
70602 /*! QDC1_RST - QDC1 reset control
70603  *  0b1..Block is reset
70604  *  0b0..Block is not reset
70605  */
70606 #define SYSCON_PRESETCTRL3_QDC1_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_QDC1_RST_SHIFT)) & SYSCON_PRESETCTRL3_QDC1_RST_MASK)
70607 
70608 #define SYSCON_PRESETCTRL3_PWM0_RST_MASK         (0x40U)
70609 #define SYSCON_PRESETCTRL3_PWM0_RST_SHIFT        (6U)
70610 /*! PWM0_RST - PWM0 reset control
70611  *  0b1..Block is reset
70612  *  0b0..Block is not reset
70613  */
70614 #define SYSCON_PRESETCTRL3_PWM0_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_PWM0_RST_SHIFT)) & SYSCON_PRESETCTRL3_PWM0_RST_MASK)
70615 
70616 #define SYSCON_PRESETCTRL3_PWM1_RST_MASK         (0x80U)
70617 #define SYSCON_PRESETCTRL3_PWM1_RST_SHIFT        (7U)
70618 /*! PWM1_RST - PWM1 reset control
70619  *  0b1..Block is reset
70620  *  0b0..Block is not reset
70621  */
70622 #define SYSCON_PRESETCTRL3_PWM1_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_PWM1_RST_SHIFT)) & SYSCON_PRESETCTRL3_PWM1_RST_MASK)
70623 
70624 #define SYSCON_PRESETCTRL3_AOI0_RST_MASK         (0x100U)
70625 #define SYSCON_PRESETCTRL3_AOI0_RST_SHIFT        (8U)
70626 /*! AOI0_RST - AOI0 reset control
70627  *  0b1..Block is reset
70628  *  0b0..Block is not reset
70629  */
70630 #define SYSCON_PRESETCTRL3_AOI0_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_AOI0_RST_SHIFT)) & SYSCON_PRESETCTRL3_AOI0_RST_MASK)
70631 
70632 #define SYSCON_PRESETCTRL3_DAC1_RST_MASK         (0x800U)
70633 #define SYSCON_PRESETCTRL3_DAC1_RST_SHIFT        (11U)
70634 /*! DAC1_RST - DAC1 reset control
70635  *  0b1..Block is reset
70636  *  0b0..Block is not reset
70637  */
70638 #define SYSCON_PRESETCTRL3_DAC1_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_DAC1_RST_SHIFT)) & SYSCON_PRESETCTRL3_DAC1_RST_MASK)
70639 
70640 #define SYSCON_PRESETCTRL3_DAC2_RST_MASK         (0x1000U)
70641 #define SYSCON_PRESETCTRL3_DAC2_RST_SHIFT        (12U)
70642 /*! DAC2_RST - DAC2 reset control
70643  *  0b1..Block is reset
70644  *  0b0..Block is not reset
70645  */
70646 #define SYSCON_PRESETCTRL3_DAC2_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_DAC2_RST_SHIFT)) & SYSCON_PRESETCTRL3_DAC2_RST_MASK)
70647 
70648 #define SYSCON_PRESETCTRL3_OPAMP0_RST_MASK       (0x2000U)
70649 #define SYSCON_PRESETCTRL3_OPAMP0_RST_SHIFT      (13U)
70650 /*! OPAMP0_RST - OPAMP0 reset control
70651  *  0b1..Block is reset
70652  *  0b0..Block is not reset
70653  */
70654 #define SYSCON_PRESETCTRL3_OPAMP0_RST(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_OPAMP0_RST_SHIFT)) & SYSCON_PRESETCTRL3_OPAMP0_RST_MASK)
70655 
70656 #define SYSCON_PRESETCTRL3_OPAMP1_RST_MASK       (0x4000U)
70657 #define SYSCON_PRESETCTRL3_OPAMP1_RST_SHIFT      (14U)
70658 /*! OPAMP1_RST - OPAMP1 reset control
70659  *  0b1..Block is reset
70660  *  0b0..Block is not reset
70661  */
70662 #define SYSCON_PRESETCTRL3_OPAMP1_RST(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_OPAMP1_RST_SHIFT)) & SYSCON_PRESETCTRL3_OPAMP1_RST_MASK)
70663 
70664 #define SYSCON_PRESETCTRL3_OPAMP2_RST_MASK       (0x8000U)
70665 #define SYSCON_PRESETCTRL3_OPAMP2_RST_SHIFT      (15U)
70666 /*! OPAMP2_RST - OPAMP2 reset control
70667  *  0b1..Block is reset
70668  *  0b0..Block is not reset
70669  */
70670 #define SYSCON_PRESETCTRL3_OPAMP2_RST(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_OPAMP2_RST_SHIFT)) & SYSCON_PRESETCTRL3_OPAMP2_RST_MASK)
70671 
70672 #define SYSCON_PRESETCTRL3_CMP2_RST_MASK         (0x40000U)
70673 #define SYSCON_PRESETCTRL3_CMP2_RST_SHIFT        (18U)
70674 /*! CMP2_RST - CMP2 reset control
70675  *  0b1..Block is reset
70676  *  0b0..Block is not reset
70677  */
70678 #define SYSCON_PRESETCTRL3_CMP2_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_CMP2_RST_SHIFT)) & SYSCON_PRESETCTRL3_CMP2_RST_MASK)
70679 
70680 #define SYSCON_PRESETCTRL3_VREF_RST_MASK         (0x80000U)
70681 #define SYSCON_PRESETCTRL3_VREF_RST_SHIFT        (19U)
70682 /*! VREF_RST - VREF reset control
70683  *  0b1..Block is reset
70684  *  0b0..Block is not reset
70685  */
70686 #define SYSCON_PRESETCTRL3_VREF_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_VREF_RST_SHIFT)) & SYSCON_PRESETCTRL3_VREF_RST_MASK)
70687 
70688 #define SYSCON_PRESETCTRL3_COOLFLUX_APB_RST_MASK (0x100000U)
70689 #define SYSCON_PRESETCTRL3_COOLFLUX_APB_RST_SHIFT (20U)
70690 /*! COOLFLUX_APB_RST - CoolFlux APB reset control
70691  *  0b1..Block is reset
70692  *  0b0..Block is not reset
70693  */
70694 #define SYSCON_PRESETCTRL3_COOLFLUX_APB_RST(x)   (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_COOLFLUX_APB_RST_SHIFT)) & SYSCON_PRESETCTRL3_COOLFLUX_APB_RST_MASK)
70695 
70696 #define SYSCON_PRESETCTRL3_NPU_RST_MASK          (0x200000U)
70697 #define SYSCON_PRESETCTRL3_NPU_RST_SHIFT         (21U)
70698 /*! NPU_RST - NPU reset control
70699  *  0b1..Block is reset
70700  *  0b0..Block is not reset
70701  */
70702 #define SYSCON_PRESETCTRL3_NPU_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_NPU_RST_SHIFT)) & SYSCON_PRESETCTRL3_NPU_RST_MASK)
70703 
70704 #define SYSCON_PRESETCTRL3_TSI_RST_MASK          (0x400000U)
70705 #define SYSCON_PRESETCTRL3_TSI_RST_SHIFT         (22U)
70706 /*! TSI_RST - TSI reset control
70707  *  0b1..Block is reset
70708  *  0b0..Block is not reset
70709  */
70710 #define SYSCON_PRESETCTRL3_TSI_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_TSI_RST_SHIFT)) & SYSCON_PRESETCTRL3_TSI_RST_MASK)
70711 
70712 #define SYSCON_PRESETCTRL3_EWM_RST_MASK          (0x800000U)
70713 #define SYSCON_PRESETCTRL3_EWM_RST_SHIFT         (23U)
70714 /*! EWM_RST - EWM reset control
70715  *  0b1..Block is reset
70716  *  0b0..Block is not reset
70717  */
70718 #define SYSCON_PRESETCTRL3_EWM_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_EWM_RST_SHIFT)) & SYSCON_PRESETCTRL3_EWM_RST_MASK)
70719 
70720 #define SYSCON_PRESETCTRL3_EIM_RST_MASK          (0x1000000U)
70721 #define SYSCON_PRESETCTRL3_EIM_RST_SHIFT         (24U)
70722 /*! EIM_RST - EIM reset control
70723  *  0b1..Block is reset
70724  *  0b0..Block is not reset
70725  */
70726 #define SYSCON_PRESETCTRL3_EIM_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_EIM_RST_SHIFT)) & SYSCON_PRESETCTRL3_EIM_RST_MASK)
70727 
70728 #define SYSCON_PRESETCTRL3_SEMA42_RST_MASK       (0x8000000U)
70729 #define SYSCON_PRESETCTRL3_SEMA42_RST_SHIFT      (27U)
70730 /*! SEMA42_RST - Semaphore reset control
70731  *  0b1..Block is reset
70732  *  0b0..Block is not reset
70733  */
70734 #define SYSCON_PRESETCTRL3_SEMA42_RST(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_SEMA42_RST_SHIFT)) & SYSCON_PRESETCTRL3_SEMA42_RST_MASK)
70735 /*! @} */
70736 
70737 /*! @name PRESETCTRLSET - Peripheral Reset Control Set */
70738 /*! @{ */
70739 
70740 #define SYSCON_PRESETCTRLSET_DATA_MASK           (0xFFFFFFFFU)
70741 #define SYSCON_PRESETCTRLSET_DATA_SHIFT          (0U)
70742 /*! DATA - Data array value, refer to corresponding position in PRESETCTRLn. */
70743 #define SYSCON_PRESETCTRLSET_DATA(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLSET_DATA_SHIFT)) & SYSCON_PRESETCTRLSET_DATA_MASK)
70744 /*! @} */
70745 
70746 /* The count of SYSCON_PRESETCTRLSET */
70747 #define SYSCON_PRESETCTRLSET_COUNT               (4U)
70748 
70749 /*! @name PRESETCTRLCLR - Peripheral Reset Control Clear */
70750 /*! @{ */
70751 
70752 #define SYSCON_PRESETCTRLCLR_DATA_MASK           (0xFFFFFFFFU)
70753 #define SYSCON_PRESETCTRLCLR_DATA_SHIFT          (0U)
70754 /*! DATA - Data array value, refer to corresponding position in PRESETCTRLn. */
70755 #define SYSCON_PRESETCTRLCLR_DATA(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLCLR_DATA_SHIFT)) & SYSCON_PRESETCTRLCLR_DATA_MASK)
70756 /*! @} */
70757 
70758 /* The count of SYSCON_PRESETCTRLCLR */
70759 #define SYSCON_PRESETCTRLCLR_COUNT               (4U)
70760 
70761 /*! @name AHBCLKCTRL0 - AHB Clock Control 0 */
70762 /*! @{ */
70763 
70764 #define SYSCON_AHBCLKCTRL0_ROM_MASK              (0x2U)
70765 #define SYSCON_AHBCLKCTRL0_ROM_SHIFT             (1U)
70766 /*! ROM - Enables the clock for the ROM
70767  *  0b1..Enables clock
70768  *  0b0..Disables clock
70769  */
70770 #define SYSCON_AHBCLKCTRL0_ROM(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_ROM_SHIFT)) & SYSCON_AHBCLKCTRL0_ROM_MASK)
70771 
70772 #define SYSCON_AHBCLKCTRL0_RAMB_CTRL_MASK        (0x4U)
70773 #define SYSCON_AHBCLKCTRL0_RAMB_CTRL_SHIFT       (2U)
70774 /*! RAMB_CTRL - Enables the clock for the RAMB Controller
70775  *  0b1..Enables clock
70776  *  0b0..Disables clock
70777  */
70778 #define SYSCON_AHBCLKCTRL0_RAMB_CTRL(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_RAMB_CTRL_SHIFT)) & SYSCON_AHBCLKCTRL0_RAMB_CTRL_MASK)
70779 
70780 #define SYSCON_AHBCLKCTRL0_RAMC_CTRL_MASK        (0x8U)
70781 #define SYSCON_AHBCLKCTRL0_RAMC_CTRL_SHIFT       (3U)
70782 /*! RAMC_CTRL - Enables the clock for the RAMC Controller
70783  *  0b1..Enables clock
70784  *  0b0..Disables clock
70785  */
70786 #define SYSCON_AHBCLKCTRL0_RAMC_CTRL(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_RAMC_CTRL_SHIFT)) & SYSCON_AHBCLKCTRL0_RAMC_CTRL_MASK)
70787 
70788 #define SYSCON_AHBCLKCTRL0_RAMD_CTRL_MASK        (0x10U)
70789 #define SYSCON_AHBCLKCTRL0_RAMD_CTRL_SHIFT       (4U)
70790 /*! RAMD_CTRL - Enables the clock for the RAMD Controller
70791  *  0b1..Enables clock
70792  *  0b0..Disables clock
70793  */
70794 #define SYSCON_AHBCLKCTRL0_RAMD_CTRL(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_RAMD_CTRL_SHIFT)) & SYSCON_AHBCLKCTRL0_RAMD_CTRL_MASK)
70795 
70796 #define SYSCON_AHBCLKCTRL0_RAME_CTRL_MASK        (0x20U)
70797 #define SYSCON_AHBCLKCTRL0_RAME_CTRL_SHIFT       (5U)
70798 /*! RAME_CTRL - Enables the clock for the RAME Controller
70799  *  0b1..Enables clock
70800  *  0b0..Disables clock
70801  */
70802 #define SYSCON_AHBCLKCTRL0_RAME_CTRL(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_RAME_CTRL_SHIFT)) & SYSCON_AHBCLKCTRL0_RAME_CTRL_MASK)
70803 
70804 #define SYSCON_AHBCLKCTRL0_RAMF_CTRL_MASK        (0x40U)
70805 #define SYSCON_AHBCLKCTRL0_RAMF_CTRL_SHIFT       (6U)
70806 /*! RAMF_CTRL - Enables the clock for the RAMF Controller
70807  *  0b1..Enables clock
70808  *  0b0..Disables clock
70809  */
70810 #define SYSCON_AHBCLKCTRL0_RAMF_CTRL(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_RAMF_CTRL_SHIFT)) & SYSCON_AHBCLKCTRL0_RAMF_CTRL_MASK)
70811 
70812 #define SYSCON_AHBCLKCTRL0_RAMG_CTRL_MASK        (0x80U)
70813 #define SYSCON_AHBCLKCTRL0_RAMG_CTRL_SHIFT       (7U)
70814 /*! RAMG_CTRL - Enables the clock for the RAMG Controller
70815  *  0b1..Enables clock
70816  *  0b0..Disables clock
70817  */
70818 #define SYSCON_AHBCLKCTRL0_RAMG_CTRL(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_RAMG_CTRL_SHIFT)) & SYSCON_AHBCLKCTRL0_RAMG_CTRL_MASK)
70819 
70820 #define SYSCON_AHBCLKCTRL0_RAMH_CTRL_MASK        (0x100U)
70821 #define SYSCON_AHBCLKCTRL0_RAMH_CTRL_SHIFT       (8U)
70822 /*! RAMH_CTRL - Enables the clock for the RAMH Controller
70823  *  0b1..Enables clock
70824  *  0b0..Disables clock
70825  */
70826 #define SYSCON_AHBCLKCTRL0_RAMH_CTRL(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_RAMH_CTRL_SHIFT)) & SYSCON_AHBCLKCTRL0_RAMH_CTRL_MASK)
70827 
70828 #define SYSCON_AHBCLKCTRL0_FMU_MASK              (0x200U)
70829 #define SYSCON_AHBCLKCTRL0_FMU_SHIFT             (9U)
70830 /*! FMU - Enables the clock for the Flash Management Unit
70831  *  0b1..Enables clock
70832  *  0b0..Disables clock
70833  */
70834 #define SYSCON_AHBCLKCTRL0_FMU(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_FMU_SHIFT)) & SYSCON_AHBCLKCTRL0_FMU_MASK)
70835 
70836 #define SYSCON_AHBCLKCTRL0_FMC_MASK              (0x400U)
70837 #define SYSCON_AHBCLKCTRL0_FMC_SHIFT             (10U)
70838 /*! FMC - Enables the clock for the Flash Memory Controller
70839  *  0b1..Enables clock
70840  *  0b0..Disables clock
70841  */
70842 #define SYSCON_AHBCLKCTRL0_FMC(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_FMC_SHIFT)) & SYSCON_AHBCLKCTRL0_FMC_MASK)
70843 
70844 #define SYSCON_AHBCLKCTRL0_FLEXSPI_MASK          (0x800U)
70845 #define SYSCON_AHBCLKCTRL0_FLEXSPI_SHIFT         (11U)
70846 /*! FLEXSPI - Enables the clock for FlexSPI
70847  *  0b1..Enables clock
70848  *  0b0..Disables clock
70849  */
70850 #define SYSCON_AHBCLKCTRL0_FLEXSPI(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_FLEXSPI_SHIFT)) & SYSCON_AHBCLKCTRL0_FLEXSPI_MASK)
70851 
70852 #define SYSCON_AHBCLKCTRL0_MUX_MASK              (0x1000U)
70853 #define SYSCON_AHBCLKCTRL0_MUX_SHIFT             (12U)
70854 /*! MUX - Enables the clock for INPUTMUX
70855  *  0b1..Enables clock
70856  *  0b0..Disables clock
70857  */
70858 #define SYSCON_AHBCLKCTRL0_MUX(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_MUX_SHIFT)) & SYSCON_AHBCLKCTRL0_MUX_MASK)
70859 
70860 #define SYSCON_AHBCLKCTRL0_PORT0_MASK            (0x2000U)
70861 #define SYSCON_AHBCLKCTRL0_PORT0_SHIFT           (13U)
70862 /*! PORT0 - Enables the clock for PORT0 controller
70863  *  0b1..Enables clock
70864  *  0b0..Disables clock
70865  */
70866 #define SYSCON_AHBCLKCTRL0_PORT0(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_PORT0_SHIFT)) & SYSCON_AHBCLKCTRL0_PORT0_MASK)
70867 
70868 #define SYSCON_AHBCLKCTRL0_PORT1_MASK            (0x4000U)
70869 #define SYSCON_AHBCLKCTRL0_PORT1_SHIFT           (14U)
70870 /*! PORT1 - Enables the clock for PORT1
70871  *  0b1..Enables clock
70872  *  0b0..Disables clock
70873  */
70874 #define SYSCON_AHBCLKCTRL0_PORT1(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_PORT1_SHIFT)) & SYSCON_AHBCLKCTRL0_PORT1_MASK)
70875 
70876 #define SYSCON_AHBCLKCTRL0_PORT2_MASK            (0x8000U)
70877 #define SYSCON_AHBCLKCTRL0_PORT2_SHIFT           (15U)
70878 /*! PORT2 - Enables the clock for PORT2
70879  *  0b1..Enables clock
70880  *  0b0..Disables clock
70881  */
70882 #define SYSCON_AHBCLKCTRL0_PORT2(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_PORT2_SHIFT)) & SYSCON_AHBCLKCTRL0_PORT2_MASK)
70883 
70884 #define SYSCON_AHBCLKCTRL0_PORT3_MASK            (0x10000U)
70885 #define SYSCON_AHBCLKCTRL0_PORT3_SHIFT           (16U)
70886 /*! PORT3 - Enables the clock for PORT3
70887  *  0b1..Enables clock
70888  *  0b0..Disables clock
70889  */
70890 #define SYSCON_AHBCLKCTRL0_PORT3(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_PORT3_SHIFT)) & SYSCON_AHBCLKCTRL0_PORT3_MASK)
70891 
70892 #define SYSCON_AHBCLKCTRL0_PORT4_MASK            (0x20000U)
70893 #define SYSCON_AHBCLKCTRL0_PORT4_SHIFT           (17U)
70894 /*! PORT4 - Enables the clock for PORT4
70895  *  0b1..Enables clock
70896  *  0b0..Disables clock
70897  */
70898 #define SYSCON_AHBCLKCTRL0_PORT4(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_PORT4_SHIFT)) & SYSCON_AHBCLKCTRL0_PORT4_MASK)
70899 
70900 #define SYSCON_AHBCLKCTRL0_GPIO0_MASK            (0x80000U)
70901 #define SYSCON_AHBCLKCTRL0_GPIO0_SHIFT           (19U)
70902 /*! GPIO0 - Enables the clock for GPIO0
70903  *  0b1..Enables clock
70904  *  0b0..Disables clock
70905  */
70906 #define SYSCON_AHBCLKCTRL0_GPIO0(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO0_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO0_MASK)
70907 
70908 #define SYSCON_AHBCLKCTRL0_GPIO1_MASK            (0x100000U)
70909 #define SYSCON_AHBCLKCTRL0_GPIO1_SHIFT           (20U)
70910 /*! GPIO1 - Enables the clock for GPIO1
70911  *  0b1..Enables clock
70912  *  0b0..Disables clock
70913  */
70914 #define SYSCON_AHBCLKCTRL0_GPIO1(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO1_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO1_MASK)
70915 
70916 #define SYSCON_AHBCLKCTRL0_GPIO2_MASK            (0x200000U)
70917 #define SYSCON_AHBCLKCTRL0_GPIO2_SHIFT           (21U)
70918 /*! GPIO2 - Enables the clock for GPIO2
70919  *  0b1..Enables clock
70920  *  0b0..Disables clock
70921  */
70922 #define SYSCON_AHBCLKCTRL0_GPIO2(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO2_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO2_MASK)
70923 
70924 #define SYSCON_AHBCLKCTRL0_GPIO3_MASK            (0x400000U)
70925 #define SYSCON_AHBCLKCTRL0_GPIO3_SHIFT           (22U)
70926 /*! GPIO3 - Enables the clock for GPIO3
70927  *  0b1..Enables clock
70928  *  0b0..Disables clock
70929  */
70930 #define SYSCON_AHBCLKCTRL0_GPIO3(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO3_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO3_MASK)
70931 
70932 #define SYSCON_AHBCLKCTRL0_GPIO4_MASK            (0x800000U)
70933 #define SYSCON_AHBCLKCTRL0_GPIO4_SHIFT           (23U)
70934 /*! GPIO4 - Enables the clock for GPIO4
70935  *  0b1..Enables clock
70936  *  0b0..Disables clock
70937  */
70938 #define SYSCON_AHBCLKCTRL0_GPIO4(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO4_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO4_MASK)
70939 
70940 #define SYSCON_AHBCLKCTRL0_PINT_MASK             (0x2000000U)
70941 #define SYSCON_AHBCLKCTRL0_PINT_SHIFT            (25U)
70942 /*! PINT - Enables the clock for PINT
70943  *  0b1..Enables clock
70944  *  0b0..Disables clock
70945  */
70946 #define SYSCON_AHBCLKCTRL0_PINT(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_PINT_SHIFT)) & SYSCON_AHBCLKCTRL0_PINT_MASK)
70947 
70948 #define SYSCON_AHBCLKCTRL0_DMA0_MASK             (0x4000000U)
70949 #define SYSCON_AHBCLKCTRL0_DMA0_SHIFT            (26U)
70950 /*! DMA0 - Enables the clock for DMA0
70951  *  0b1..Enables clock
70952  *  0b0..Disables clock
70953  */
70954 #define SYSCON_AHBCLKCTRL0_DMA0(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_DMA0_SHIFT)) & SYSCON_AHBCLKCTRL0_DMA0_MASK)
70955 
70956 #define SYSCON_AHBCLKCTRL0_CRC_MASK              (0x8000000U)
70957 #define SYSCON_AHBCLKCTRL0_CRC_SHIFT             (27U)
70958 /*! CRC - Enables the clock for CRC
70959  *  0b1..Enables clock
70960  *  0b0..Disables clock
70961  */
70962 #define SYSCON_AHBCLKCTRL0_CRC(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_CRC_SHIFT)) & SYSCON_AHBCLKCTRL0_CRC_MASK)
70963 
70964 #define SYSCON_AHBCLKCTRL0_WWDT0_MASK            (0x10000000U)
70965 #define SYSCON_AHBCLKCTRL0_WWDT0_SHIFT           (28U)
70966 /*! WWDT0 - Enables the clock for WWDT0
70967  *  0b1..Enables clock
70968  *  0b0..Disables clock
70969  */
70970 #define SYSCON_AHBCLKCTRL0_WWDT0(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_WWDT0_SHIFT)) & SYSCON_AHBCLKCTRL0_WWDT0_MASK)
70971 
70972 #define SYSCON_AHBCLKCTRL0_WWDT1_MASK            (0x20000000U)
70973 #define SYSCON_AHBCLKCTRL0_WWDT1_SHIFT           (29U)
70974 /*! WWDT1 - Enables the clock for WWDT1
70975  *  0b1..Enables clock
70976  *  0b0..Disables clock
70977  */
70978 #define SYSCON_AHBCLKCTRL0_WWDT1(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_WWDT1_SHIFT)) & SYSCON_AHBCLKCTRL0_WWDT1_MASK)
70979 
70980 #define SYSCON_AHBCLKCTRL0_MAILBOX_MASK          (0x80000000U)
70981 #define SYSCON_AHBCLKCTRL0_MAILBOX_SHIFT         (31U)
70982 /*! MAILBOX - Enables the clock for the Inter CPU communication Mailbox.
70983  *  0b1..Enables clock
70984  *  0b0..Disables clock
70985  */
70986 #define SYSCON_AHBCLKCTRL0_MAILBOX(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_MAILBOX_SHIFT)) & SYSCON_AHBCLKCTRL0_MAILBOX_MASK)
70987 /*! @} */
70988 
70989 /*! @name AHBCLKCTRL1 - AHB Clock Control 1 */
70990 /*! @{ */
70991 
70992 #define SYSCON_AHBCLKCTRL1_MRT_MASK              (0x1U)
70993 #define SYSCON_AHBCLKCTRL1_MRT_SHIFT             (0U)
70994 /*! MRT - Enables the clock for MRT
70995  *  0b1..Enables clock
70996  *  0b0..Disables clock
70997  */
70998 #define SYSCON_AHBCLKCTRL1_MRT(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_MRT_SHIFT)) & SYSCON_AHBCLKCTRL1_MRT_MASK)
70999 
71000 #define SYSCON_AHBCLKCTRL1_OSTIMER_MASK          (0x2U)
71001 #define SYSCON_AHBCLKCTRL1_OSTIMER_SHIFT         (1U)
71002 /*! OSTIMER - Enables the clock for the OS Event Timer
71003  *  0b1..Enables clock
71004  *  0b0..Disables clock
71005  */
71006 #define SYSCON_AHBCLKCTRL1_OSTIMER(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_OSTIMER_SHIFT)) & SYSCON_AHBCLKCTRL1_OSTIMER_MASK)
71007 
71008 #define SYSCON_AHBCLKCTRL1_SCT_MASK              (0x4U)
71009 #define SYSCON_AHBCLKCTRL1_SCT_SHIFT             (2U)
71010 /*! SCT - Enables the clock for SCT
71011  *  0b1..Enables clock
71012  *  0b0..Disables clock
71013  */
71014 #define SYSCON_AHBCLKCTRL1_SCT(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_SCT_SHIFT)) & SYSCON_AHBCLKCTRL1_SCT_MASK)
71015 
71016 #define SYSCON_AHBCLKCTRL1_ADC0_MASK             (0x8U)
71017 #define SYSCON_AHBCLKCTRL1_ADC0_SHIFT            (3U)
71018 /*! ADC0 - Enables the clock for ADC0
71019  *  0b1..Enables clock
71020  *  0b0..Disables clock
71021  */
71022 #define SYSCON_AHBCLKCTRL1_ADC0(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_ADC0_SHIFT)) & SYSCON_AHBCLKCTRL1_ADC0_MASK)
71023 
71024 #define SYSCON_AHBCLKCTRL1_ADC1_MASK             (0x10U)
71025 #define SYSCON_AHBCLKCTRL1_ADC1_SHIFT            (4U)
71026 /*! ADC1 - Enables the clock for ADC1
71027  *  0b1..Enables clock
71028  *  0b0..Disables clock
71029  */
71030 #define SYSCON_AHBCLKCTRL1_ADC1(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_ADC1_SHIFT)) & SYSCON_AHBCLKCTRL1_ADC1_MASK)
71031 
71032 #define SYSCON_AHBCLKCTRL1_DAC0_MASK             (0x20U)
71033 #define SYSCON_AHBCLKCTRL1_DAC0_SHIFT            (5U)
71034 /*! DAC0 - Enables the clock for DAC0
71035  *  0b1..Enables clock
71036  *  0b0..Disables clock
71037  */
71038 #define SYSCON_AHBCLKCTRL1_DAC0(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_DAC0_SHIFT)) & SYSCON_AHBCLKCTRL1_DAC0_MASK)
71039 
71040 #define SYSCON_AHBCLKCTRL1_RTC_MASK              (0x40U)
71041 #define SYSCON_AHBCLKCTRL1_RTC_SHIFT             (6U)
71042 /*! RTC - Enables the clock for RTC
71043  *  0b1..Enables clock
71044  *  0b0..Disables clock
71045  */
71046 #define SYSCON_AHBCLKCTRL1_RTC(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_RTC_SHIFT)) & SYSCON_AHBCLKCTRL1_RTC_MASK)
71047 
71048 #define SYSCON_AHBCLKCTRL1_EVSIM0_MASK           (0x100U)
71049 #define SYSCON_AHBCLKCTRL1_EVSIM0_SHIFT          (8U)
71050 /*! EVSIM0 - Enables the clock for EVSIM0
71051  *  0b1..Enables clock
71052  *  0b0..Disables clock
71053  */
71054 #define SYSCON_AHBCLKCTRL1_EVSIM0(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_EVSIM0_SHIFT)) & SYSCON_AHBCLKCTRL1_EVSIM0_MASK)
71055 
71056 #define SYSCON_AHBCLKCTRL1_EVSIM1_MASK           (0x200U)
71057 #define SYSCON_AHBCLKCTRL1_EVSIM1_SHIFT          (9U)
71058 /*! EVSIM1 - Enables the clock for EVSIM1
71059  *  0b1..Enables clock
71060  *  0b0..Disables clock
71061  */
71062 #define SYSCON_AHBCLKCTRL1_EVSIM1(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_EVSIM1_SHIFT)) & SYSCON_AHBCLKCTRL1_EVSIM1_MASK)
71063 
71064 #define SYSCON_AHBCLKCTRL1_UTICK_MASK            (0x400U)
71065 #define SYSCON_AHBCLKCTRL1_UTICK_SHIFT           (10U)
71066 /*! UTICK - Enables the clock for UTICK
71067  *  0b1..Enables clock
71068  *  0b0..Disables clock
71069  */
71070 #define SYSCON_AHBCLKCTRL1_UTICK(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_UTICK_SHIFT)) & SYSCON_AHBCLKCTRL1_UTICK_MASK)
71071 
71072 #define SYSCON_AHBCLKCTRL1_FC0_MASK              (0x800U)
71073 #define SYSCON_AHBCLKCTRL1_FC0_SHIFT             (11U)
71074 /*! FC0 - Enables the clock for LP_FLEXCOMM0
71075  *  0b1..Enables clock
71076  *  0b0..Disables clock
71077  */
71078 #define SYSCON_AHBCLKCTRL1_FC0(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC0_SHIFT)) & SYSCON_AHBCLKCTRL1_FC0_MASK)
71079 
71080 #define SYSCON_AHBCLKCTRL1_FC1_MASK              (0x1000U)
71081 #define SYSCON_AHBCLKCTRL1_FC1_SHIFT             (12U)
71082 /*! FC1 - Enables the clock for LP_FLEXCOMM1
71083  *  0b1..Enables clock
71084  *  0b0..Disables clock
71085  */
71086 #define SYSCON_AHBCLKCTRL1_FC1(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC1_SHIFT)) & SYSCON_AHBCLKCTRL1_FC1_MASK)
71087 
71088 #define SYSCON_AHBCLKCTRL1_FC2_MASK              (0x2000U)
71089 #define SYSCON_AHBCLKCTRL1_FC2_SHIFT             (13U)
71090 /*! FC2 - Enables the clock for LP_FLEXCOMM2
71091  *  0b1..Enables clock
71092  *  0b0..Disables clock
71093  */
71094 #define SYSCON_AHBCLKCTRL1_FC2(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC2_SHIFT)) & SYSCON_AHBCLKCTRL1_FC2_MASK)
71095 
71096 #define SYSCON_AHBCLKCTRL1_FC3_MASK              (0x4000U)
71097 #define SYSCON_AHBCLKCTRL1_FC3_SHIFT             (14U)
71098 /*! FC3 - Enables the clock for LP_FLEXCOMM3
71099  *  0b1..Enables clock
71100  *  0b0..Disables clock
71101  */
71102 #define SYSCON_AHBCLKCTRL1_FC3(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC3_SHIFT)) & SYSCON_AHBCLKCTRL1_FC3_MASK)
71103 
71104 #define SYSCON_AHBCLKCTRL1_FC4_MASK              (0x8000U)
71105 #define SYSCON_AHBCLKCTRL1_FC4_SHIFT             (15U)
71106 /*! FC4 - Enables the clock for LP_FLEXCOMM4
71107  *  0b1..Enables clock
71108  *  0b0..Disables clock
71109  */
71110 #define SYSCON_AHBCLKCTRL1_FC4(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC4_SHIFT)) & SYSCON_AHBCLKCTRL1_FC4_MASK)
71111 
71112 #define SYSCON_AHBCLKCTRL1_FC5_MASK              (0x10000U)
71113 #define SYSCON_AHBCLKCTRL1_FC5_SHIFT             (16U)
71114 /*! FC5 - Enables the clock for LP_FLEXCOMM5
71115  *  0b1..Enables clock
71116  *  0b0..Disables clock
71117  */
71118 #define SYSCON_AHBCLKCTRL1_FC5(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC5_SHIFT)) & SYSCON_AHBCLKCTRL1_FC5_MASK)
71119 
71120 #define SYSCON_AHBCLKCTRL1_FC6_MASK              (0x20000U)
71121 #define SYSCON_AHBCLKCTRL1_FC6_SHIFT             (17U)
71122 /*! FC6 - Enables the clock for LP_FLEXCOMM6
71123  *  0b1..Enables clock
71124  *  0b0..Disables clock
71125  */
71126 #define SYSCON_AHBCLKCTRL1_FC6(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC6_SHIFT)) & SYSCON_AHBCLKCTRL1_FC6_MASK)
71127 
71128 #define SYSCON_AHBCLKCTRL1_FC7_MASK              (0x40000U)
71129 #define SYSCON_AHBCLKCTRL1_FC7_SHIFT             (18U)
71130 /*! FC7 - Enables the clock for LP_FLEXCOMM7
71131  *  0b1..Enables clock
71132  *  0b0..Disables clock
71133  */
71134 #define SYSCON_AHBCLKCTRL1_FC7(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC7_SHIFT)) & SYSCON_AHBCLKCTRL1_FC7_MASK)
71135 
71136 #define SYSCON_AHBCLKCTRL1_FC8_MASK              (0x80000U)
71137 #define SYSCON_AHBCLKCTRL1_FC8_SHIFT             (19U)
71138 /*! FC8 - Enables the clock for LP_FLEXCOMM8
71139  *  0b1..Enables clock
71140  *  0b0..Disables clock
71141  */
71142 #define SYSCON_AHBCLKCTRL1_FC8(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC8_SHIFT)) & SYSCON_AHBCLKCTRL1_FC8_MASK)
71143 
71144 #define SYSCON_AHBCLKCTRL1_FC9_MASK              (0x100000U)
71145 #define SYSCON_AHBCLKCTRL1_FC9_SHIFT             (20U)
71146 /*! FC9 - Enables the clock for LP_FLEXCOMM9
71147  *  0b1..Enables clock
71148  *  0b0..Disables clock
71149  */
71150 #define SYSCON_AHBCLKCTRL1_FC9(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC9_SHIFT)) & SYSCON_AHBCLKCTRL1_FC9_MASK)
71151 
71152 #define SYSCON_AHBCLKCTRL1_MICFIL_MASK           (0x200000U)
71153 #define SYSCON_AHBCLKCTRL1_MICFIL_SHIFT          (21U)
71154 /*! MICFIL - Enables the clock for MICFIL
71155  *  0b1..Enables clock
71156  *  0b0..Disables clock
71157  */
71158 #define SYSCON_AHBCLKCTRL1_MICFIL(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_MICFIL_SHIFT)) & SYSCON_AHBCLKCTRL1_MICFIL_MASK)
71159 
71160 #define SYSCON_AHBCLKCTRL1_TIMER2_MASK           (0x400000U)
71161 #define SYSCON_AHBCLKCTRL1_TIMER2_SHIFT          (22U)
71162 /*! TIMER2 - Enables the clock for CTIMER2
71163  *  0b1..Enables clock
71164  *  0b0..Disables clock
71165  */
71166 #define SYSCON_AHBCLKCTRL1_TIMER2(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER2_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER2_MASK)
71167 
71168 #define SYSCON_AHBCLKCTRL1_USB0_FS_DCD_MASK      (0x1000000U)
71169 #define SYSCON_AHBCLKCTRL1_USB0_FS_DCD_SHIFT     (24U)
71170 /*! USB0_FS_DCD - Enables the clock for USB-FS DCD
71171  *  0b1..Enables clock
71172  *  0b0..Disables clock
71173  */
71174 #define SYSCON_AHBCLKCTRL1_USB0_FS_DCD(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_USB0_FS_DCD_SHIFT)) & SYSCON_AHBCLKCTRL1_USB0_FS_DCD_MASK)
71175 
71176 #define SYSCON_AHBCLKCTRL1_USB0_FS_MASK          (0x2000000U)
71177 #define SYSCON_AHBCLKCTRL1_USB0_FS_SHIFT         (25U)
71178 /*! USB0_FS - Enables the clock for USB-FS
71179  *  0b1..Enables clock
71180  *  0b0..Disables clock
71181  */
71182 #define SYSCON_AHBCLKCTRL1_USB0_FS(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_USB0_FS_SHIFT)) & SYSCON_AHBCLKCTRL1_USB0_FS_MASK)
71183 
71184 #define SYSCON_AHBCLKCTRL1_TIMER0_MASK           (0x4000000U)
71185 #define SYSCON_AHBCLKCTRL1_TIMER0_SHIFT          (26U)
71186 /*! TIMER0 - Enables the clock for CTIMER0
71187  *  0b1..Enables clock
71188  *  0b0..Disables clock
71189  */
71190 #define SYSCON_AHBCLKCTRL1_TIMER0(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER0_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER0_MASK)
71191 
71192 #define SYSCON_AHBCLKCTRL1_TIMER1_MASK           (0x8000000U)
71193 #define SYSCON_AHBCLKCTRL1_TIMER1_SHIFT          (27U)
71194 /*! TIMER1 - Enables the clock for CTIMER1
71195  *  0b1..Enables clock
71196  *  0b0..Disables clock
71197  */
71198 #define SYSCON_AHBCLKCTRL1_TIMER1(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER1_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER1_MASK)
71199 
71200 #define SYSCON_AHBCLKCTRL1_PKC_RAM_MASK          (0x20000000U)
71201 #define SYSCON_AHBCLKCTRL1_PKC_RAM_SHIFT         (29U)
71202 /*! PKC_RAM - Enables the clock for PKC RAM
71203  *  0b1..Enables clock
71204  *  0b0..Disables clock
71205  */
71206 #define SYSCON_AHBCLKCTRL1_PKC_RAM(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_PKC_RAM_SHIFT)) & SYSCON_AHBCLKCTRL1_PKC_RAM_MASK)
71207 
71208 #define SYSCON_AHBCLKCTRL1_SmartDMA_MASK         (0x80000000U)
71209 #define SYSCON_AHBCLKCTRL1_SmartDMA_SHIFT        (31U)
71210 /*! SmartDMA - Enables the clock for SmartDMA
71211  *  0b1..Enables clock
71212  *  0b0..Disables clock
71213  */
71214 #define SYSCON_AHBCLKCTRL1_SmartDMA(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_SmartDMA_SHIFT)) & SYSCON_AHBCLKCTRL1_SmartDMA_MASK)
71215 /*! @} */
71216 
71217 /*! @name AHBCLKCTRL2 - AHB Clock Control 2 */
71218 /*! @{ */
71219 
71220 #define SYSCON_AHBCLKCTRL2_DMA1_MASK             (0x2U)
71221 #define SYSCON_AHBCLKCTRL2_DMA1_SHIFT            (1U)
71222 /*! DMA1 - Enables the clock for DMA1
71223  *  0b1..Enables clock
71224  *  0b0..Disables clock
71225  */
71226 #define SYSCON_AHBCLKCTRL2_DMA1(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_DMA1_SHIFT)) & SYSCON_AHBCLKCTRL2_DMA1_MASK)
71227 
71228 #define SYSCON_AHBCLKCTRL2_ENET_MASK             (0x4U)
71229 #define SYSCON_AHBCLKCTRL2_ENET_SHIFT            (2U)
71230 /*! ENET - Enables the clock for Ethernet
71231  *  0b1..Enables clock
71232  *  0b0..Disables clock
71233  */
71234 #define SYSCON_AHBCLKCTRL2_ENET(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_ENET_SHIFT)) & SYSCON_AHBCLKCTRL2_ENET_MASK)
71235 
71236 #define SYSCON_AHBCLKCTRL2_uSDHC_MASK            (0x8U)
71237 #define SYSCON_AHBCLKCTRL2_uSDHC_SHIFT           (3U)
71238 /*! uSDHC - Enables the clock for uSDHC
71239  *  0b1..Enables clock
71240  *  0b0..Disables clock
71241  */
71242 #define SYSCON_AHBCLKCTRL2_uSDHC(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_uSDHC_SHIFT)) & SYSCON_AHBCLKCTRL2_uSDHC_MASK)
71243 
71244 #define SYSCON_AHBCLKCTRL2_FLEXIO_MASK           (0x10U)
71245 #define SYSCON_AHBCLKCTRL2_FLEXIO_SHIFT          (4U)
71246 /*! FLEXIO - Enables the clock for Flexio
71247  *  0b1..Enable clock
71248  *  0b0..Disables clock
71249  */
71250 #define SYSCON_AHBCLKCTRL2_FLEXIO(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_FLEXIO_SHIFT)) & SYSCON_AHBCLKCTRL2_FLEXIO_MASK)
71251 
71252 #define SYSCON_AHBCLKCTRL2_SAI0_MASK             (0x20U)
71253 #define SYSCON_AHBCLKCTRL2_SAI0_SHIFT            (5U)
71254 /*! SAI0 - Enables the clock for SAI0
71255  *  0b1..Enables clock
71256  *  0b0..Disables clock
71257  */
71258 #define SYSCON_AHBCLKCTRL2_SAI0(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_SAI0_SHIFT)) & SYSCON_AHBCLKCTRL2_SAI0_MASK)
71259 
71260 #define SYSCON_AHBCLKCTRL2_SAI1_MASK             (0x40U)
71261 #define SYSCON_AHBCLKCTRL2_SAI1_SHIFT            (6U)
71262 /*! SAI1 - Enables the clock for SAI1
71263  *  0b1..Enables clock
71264  *  0b0..Disables clock
71265  */
71266 #define SYSCON_AHBCLKCTRL2_SAI1(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_SAI1_SHIFT)) & SYSCON_AHBCLKCTRL2_SAI1_MASK)
71267 
71268 #define SYSCON_AHBCLKCTRL2_TRO_MASK              (0x80U)
71269 #define SYSCON_AHBCLKCTRL2_TRO_SHIFT             (7U)
71270 /*! TRO - Enables the clock for TRO
71271  *  0b1..Enables clock
71272  *  0b0..Disables clock
71273  */
71274 #define SYSCON_AHBCLKCTRL2_TRO(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_TRO_SHIFT)) & SYSCON_AHBCLKCTRL2_TRO_MASK)
71275 
71276 #define SYSCON_AHBCLKCTRL2_FREQME_MASK           (0x100U)
71277 #define SYSCON_AHBCLKCTRL2_FREQME_SHIFT          (8U)
71278 /*! FREQME - Enables the clock for the Frequency meter
71279  *  0b1..Enables clock
71280  *  0b0..Disables clock
71281  */
71282 #define SYSCON_AHBCLKCTRL2_FREQME(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_FREQME_SHIFT)) & SYSCON_AHBCLKCTRL2_FREQME_MASK)
71283 
71284 #define SYSCON_AHBCLKCTRL2_TRNG_MASK             (0x2000U)
71285 #define SYSCON_AHBCLKCTRL2_TRNG_SHIFT            (13U)
71286 /*! TRNG - Enables the clock for TRNG
71287  *  0b1..Enables clock
71288  *  0b0..Disables clock
71289  */
71290 #define SYSCON_AHBCLKCTRL2_TRNG(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_TRNG_SHIFT)) & SYSCON_AHBCLKCTRL2_TRNG_MASK)
71291 
71292 #define SYSCON_AHBCLKCTRL2_FLEXCAN0_MASK         (0x4000U)
71293 #define SYSCON_AHBCLKCTRL2_FLEXCAN0_SHIFT        (14U)
71294 /*! FLEXCAN0 - Enables the clock for FLEXCAN0
71295  *  0b1..Enables clock
71296  *  0b0..Disables clock
71297  */
71298 #define SYSCON_AHBCLKCTRL2_FLEXCAN0(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_FLEXCAN0_SHIFT)) & SYSCON_AHBCLKCTRL2_FLEXCAN0_MASK)
71299 
71300 #define SYSCON_AHBCLKCTRL2_FLEXCAN1_MASK         (0x8000U)
71301 #define SYSCON_AHBCLKCTRL2_FLEXCAN1_SHIFT        (15U)
71302 /*! FLEXCAN1 - Enables the clock for FLEXCAN1
71303  *  0b1..Enables clock
71304  *  0b0..Disables clock
71305  */
71306 #define SYSCON_AHBCLKCTRL2_FLEXCAN1(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_FLEXCAN1_SHIFT)) & SYSCON_AHBCLKCTRL2_FLEXCAN1_MASK)
71307 
71308 #define SYSCON_AHBCLKCTRL2_USB_HS_MASK           (0x10000U)
71309 #define SYSCON_AHBCLKCTRL2_USB_HS_SHIFT          (16U)
71310 /*! USB_HS - Enables the clock for USB HS
71311  *  0b1..Enables clock
71312  *  0b0..Disables clock
71313  */
71314 #define SYSCON_AHBCLKCTRL2_USB_HS(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB_HS_SHIFT)) & SYSCON_AHBCLKCTRL2_USB_HS_MASK)
71315 
71316 #define SYSCON_AHBCLKCTRL2_USB_HS_PHY_MASK       (0x20000U)
71317 #define SYSCON_AHBCLKCTRL2_USB_HS_PHY_SHIFT      (17U)
71318 /*! USB_HS_PHY - Enables the clock for USB HS PHY
71319  *  0b1..Enables clock
71320  *  0b0..Disables clock
71321  */
71322 #define SYSCON_AHBCLKCTRL2_USB_HS_PHY(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB_HS_PHY_SHIFT)) & SYSCON_AHBCLKCTRL2_USB_HS_PHY_MASK)
71323 
71324 #define SYSCON_AHBCLKCTRL2_ELS_MASK              (0x40000U)
71325 #define SYSCON_AHBCLKCTRL2_ELS_SHIFT             (18U)
71326 /*! ELS - Enables the clock for ELS
71327  *  0b1..Enables clock
71328  *  0b0..Disables clock
71329  */
71330 #define SYSCON_AHBCLKCTRL2_ELS(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_ELS_SHIFT)) & SYSCON_AHBCLKCTRL2_ELS_MASK)
71331 
71332 #define SYSCON_AHBCLKCTRL2_PQ_MASK               (0x80000U)
71333 #define SYSCON_AHBCLKCTRL2_PQ_SHIFT              (19U)
71334 /*! PQ - Enables the clock for Powerquad
71335  *  0b1..Enables clock
71336  *  0b0..Disables clock
71337  */
71338 #define SYSCON_AHBCLKCTRL2_PQ(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PQ_SHIFT)) & SYSCON_AHBCLKCTRL2_PQ_MASK)
71339 
71340 #define SYSCON_AHBCLKCTRL2_PLU_LUT_MASK          (0x100000U)
71341 #define SYSCON_AHBCLKCTRL2_PLU_LUT_SHIFT         (20U)
71342 /*! PLU_LUT - Enables the clock for PLU_LUT
71343  *  0b1..Enables clock
71344  *  0b0..Disables clock
71345  */
71346 #define SYSCON_AHBCLKCTRL2_PLU_LUT(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PLU_LUT_SHIFT)) & SYSCON_AHBCLKCTRL2_PLU_LUT_MASK)
71347 
71348 #define SYSCON_AHBCLKCTRL2_TIMER3_MASK           (0x200000U)
71349 #define SYSCON_AHBCLKCTRL2_TIMER3_SHIFT          (21U)
71350 /*! TIMER3 - Enables the clock for CTIMER3
71351  *  0b1..Enables clock
71352  *  0b0..Disables clock
71353  */
71354 #define SYSCON_AHBCLKCTRL2_TIMER3(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_TIMER3_SHIFT)) & SYSCON_AHBCLKCTRL2_TIMER3_MASK)
71355 
71356 #define SYSCON_AHBCLKCTRL2_TIMER4_MASK           (0x400000U)
71357 #define SYSCON_AHBCLKCTRL2_TIMER4_SHIFT          (22U)
71358 /*! TIMER4 - Enables the clock for CTIMER4
71359  *  0b1..Enables clock
71360  *  0b0..Disables clock
71361  */
71362 #define SYSCON_AHBCLKCTRL2_TIMER4(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_TIMER4_SHIFT)) & SYSCON_AHBCLKCTRL2_TIMER4_MASK)
71363 
71364 #define SYSCON_AHBCLKCTRL2_PUF_MASK              (0x800000U)
71365 #define SYSCON_AHBCLKCTRL2_PUF_SHIFT             (23U)
71366 /*! PUF - Enables the clock for PUF
71367  *  0b1..Enables clock
71368  *  0b0..Disables clock
71369  */
71370 #define SYSCON_AHBCLKCTRL2_PUF(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PUF_SHIFT)) & SYSCON_AHBCLKCTRL2_PUF_MASK)
71371 
71372 #define SYSCON_AHBCLKCTRL2_PKC_MASK              (0x1000000U)
71373 #define SYSCON_AHBCLKCTRL2_PKC_SHIFT             (24U)
71374 /*! PKC - Enables the clock for PKC
71375  *  0b1..Enables clock
71376  *  0b0..Disables clock
71377  */
71378 #define SYSCON_AHBCLKCTRL2_PKC(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PKC_SHIFT)) & SYSCON_AHBCLKCTRL2_PKC_MASK)
71379 
71380 #define SYSCON_AHBCLKCTRL2_SCG_MASK              (0x4000000U)
71381 #define SYSCON_AHBCLKCTRL2_SCG_SHIFT             (26U)
71382 /*! SCG - Enables the clock for SCG
71383  *  0b1..Enables clock
71384  *  0b0..Disables clock
71385  */
71386 #define SYSCON_AHBCLKCTRL2_SCG(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_SCG_SHIFT)) & SYSCON_AHBCLKCTRL2_SCG_MASK)
71387 
71388 #define SYSCON_AHBCLKCTRL2_GDET_MASK             (0x20000000U)
71389 #define SYSCON_AHBCLKCTRL2_GDET_SHIFT            (29U)
71390 /*! GDET - Enables the clock for GDET0 and GDET1
71391  *  0b1..Enables clock
71392  *  0b0..Disables clock
71393  */
71394 #define SYSCON_AHBCLKCTRL2_GDET(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_GDET_SHIFT)) & SYSCON_AHBCLKCTRL2_GDET_MASK)
71395 
71396 #define SYSCON_AHBCLKCTRL2_SM3_MASK              (0x40000000U)
71397 #define SYSCON_AHBCLKCTRL2_SM3_SHIFT             (30U)
71398 /*! SM3 - Enables the clock for SM3
71399  *  0b1..Enables clock
71400  *  0b0..Disables clock
71401  */
71402 #define SYSCON_AHBCLKCTRL2_SM3(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_SM3_SHIFT)) & SYSCON_AHBCLKCTRL2_SM3_MASK)
71403 /*! @} */
71404 
71405 /*! @name AHBCLKCTRL3 - AHB Clock Control 3 */
71406 /*! @{ */
71407 
71408 #define SYSCON_AHBCLKCTRL3_I3C0_MASK             (0x1U)
71409 #define SYSCON_AHBCLKCTRL3_I3C0_SHIFT            (0U)
71410 /*! I3C0 - Enables the clock for I3C0
71411  *  0b1..Enables clock
71412  *  0b0..Disables clock
71413  */
71414 #define SYSCON_AHBCLKCTRL3_I3C0(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_I3C0_SHIFT)) & SYSCON_AHBCLKCTRL3_I3C0_MASK)
71415 
71416 #define SYSCON_AHBCLKCTRL3_I3C1_MASK             (0x2U)
71417 #define SYSCON_AHBCLKCTRL3_I3C1_SHIFT            (1U)
71418 /*! I3C1 - Enables the clock for I3C1
71419  *  0b1..Enables clock
71420  *  0b0..Disables clock
71421  */
71422 #define SYSCON_AHBCLKCTRL3_I3C1(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_I3C1_SHIFT)) & SYSCON_AHBCLKCTRL3_I3C1_MASK)
71423 
71424 #define SYSCON_AHBCLKCTRL3_SINC_MASK             (0x4U)
71425 #define SYSCON_AHBCLKCTRL3_SINC_SHIFT            (2U)
71426 /*! SINC - Enables the clock for SINC
71427  *  0b1..Enables clock
71428  *  0b0..Disables clock
71429  */
71430 #define SYSCON_AHBCLKCTRL3_SINC(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_SINC_SHIFT)) & SYSCON_AHBCLKCTRL3_SINC_MASK)
71431 
71432 #define SYSCON_AHBCLKCTRL3_COOLFLUX_MASK         (0x8U)
71433 #define SYSCON_AHBCLKCTRL3_COOLFLUX_SHIFT        (3U)
71434 /*! COOLFLUX - Enables the clock for CoolFlux
71435  *  0b1..Enables clock
71436  *  0b0..Disables clock
71437  */
71438 #define SYSCON_AHBCLKCTRL3_COOLFLUX(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_COOLFLUX_SHIFT)) & SYSCON_AHBCLKCTRL3_COOLFLUX_MASK)
71439 
71440 #define SYSCON_AHBCLKCTRL3_QDC0_MASK             (0x10U)
71441 #define SYSCON_AHBCLKCTRL3_QDC0_SHIFT            (4U)
71442 /*! QDC0 - Enables the clock for QDC0
71443  *  0b1..Enables clock
71444  *  0b0..Disables clock
71445  */
71446 #define SYSCON_AHBCLKCTRL3_QDC0(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_QDC0_SHIFT)) & SYSCON_AHBCLKCTRL3_QDC0_MASK)
71447 
71448 #define SYSCON_AHBCLKCTRL3_QDC1_MASK             (0x20U)
71449 #define SYSCON_AHBCLKCTRL3_QDC1_SHIFT            (5U)
71450 /*! QDC1 - Enables the clock for QDC1
71451  *  0b1..Enables clock
71452  *  0b0..Disables clock
71453  */
71454 #define SYSCON_AHBCLKCTRL3_QDC1(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_QDC1_SHIFT)) & SYSCON_AHBCLKCTRL3_QDC1_MASK)
71455 
71456 #define SYSCON_AHBCLKCTRL3_PWM0_MASK             (0x40U)
71457 #define SYSCON_AHBCLKCTRL3_PWM0_SHIFT            (6U)
71458 /*! PWM0 - Enables the clock for PWM0
71459  *  0b1..Enables clock
71460  *  0b0..Disables clock
71461  */
71462 #define SYSCON_AHBCLKCTRL3_PWM0(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_PWM0_SHIFT)) & SYSCON_AHBCLKCTRL3_PWM0_MASK)
71463 
71464 #define SYSCON_AHBCLKCTRL3_PWM1_MASK             (0x80U)
71465 #define SYSCON_AHBCLKCTRL3_PWM1_SHIFT            (7U)
71466 /*! PWM1 - Enables the clock for PWM1
71467  *  0b1..Enables clock
71468  *  0b0..Disables clock
71469  */
71470 #define SYSCON_AHBCLKCTRL3_PWM1(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_PWM1_SHIFT)) & SYSCON_AHBCLKCTRL3_PWM1_MASK)
71471 
71472 #define SYSCON_AHBCLKCTRL3_EVTG_MASK             (0x100U)
71473 #define SYSCON_AHBCLKCTRL3_EVTG_SHIFT            (8U)
71474 /*! EVTG - Enables the clock for EVTG
71475  *  0b1..Enables clock
71476  *  0b0..Disables clock
71477  */
71478 #define SYSCON_AHBCLKCTRL3_EVTG(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_EVTG_SHIFT)) & SYSCON_AHBCLKCTRL3_EVTG_MASK)
71479 
71480 #define SYSCON_AHBCLKCTRL3_DAC1_MASK             (0x800U)
71481 #define SYSCON_AHBCLKCTRL3_DAC1_SHIFT            (11U)
71482 /*! DAC1 - Enables the clock for DAC1
71483  *  0b1..Enables clock
71484  *  0b0..Disables clock
71485  */
71486 #define SYSCON_AHBCLKCTRL3_DAC1(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_DAC1_SHIFT)) & SYSCON_AHBCLKCTRL3_DAC1_MASK)
71487 
71488 #define SYSCON_AHBCLKCTRL3_DAC2_MASK             (0x1000U)
71489 #define SYSCON_AHBCLKCTRL3_DAC2_SHIFT            (12U)
71490 /*! DAC2 - Enables the clock for DAC2
71491  *  0b1..Enables clock
71492  *  0b0..Disables clock
71493  */
71494 #define SYSCON_AHBCLKCTRL3_DAC2(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_DAC2_SHIFT)) & SYSCON_AHBCLKCTRL3_DAC2_MASK)
71495 
71496 #define SYSCON_AHBCLKCTRL3_OPAMP0_MASK           (0x2000U)
71497 #define SYSCON_AHBCLKCTRL3_OPAMP0_SHIFT          (13U)
71498 /*! OPAMP0 - Enables the clock for OPAMP0
71499  *  0b1..Enables clock
71500  *  0b0..Disables clock
71501  */
71502 #define SYSCON_AHBCLKCTRL3_OPAMP0(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_OPAMP0_SHIFT)) & SYSCON_AHBCLKCTRL3_OPAMP0_MASK)
71503 
71504 #define SYSCON_AHBCLKCTRL3_OPAMP1_MASK           (0x4000U)
71505 #define SYSCON_AHBCLKCTRL3_OPAMP1_SHIFT          (14U)
71506 /*! OPAMP1 - Enables the clock for OPAMP1
71507  *  0b1..Enables clock
71508  *  0b0..Disables clock
71509  */
71510 #define SYSCON_AHBCLKCTRL3_OPAMP1(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_OPAMP1_SHIFT)) & SYSCON_AHBCLKCTRL3_OPAMP1_MASK)
71511 
71512 #define SYSCON_AHBCLKCTRL3_OPAMP2_MASK           (0x8000U)
71513 #define SYSCON_AHBCLKCTRL3_OPAMP2_SHIFT          (15U)
71514 /*! OPAMP2 - Enables the clock for OPAMP2
71515  *  0b1..Enables clock
71516  *  0b0..Disables clock
71517  */
71518 #define SYSCON_AHBCLKCTRL3_OPAMP2(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_OPAMP2_SHIFT)) & SYSCON_AHBCLKCTRL3_OPAMP2_MASK)
71519 
71520 #define SYSCON_AHBCLKCTRL3_CMP2_MASK             (0x40000U)
71521 #define SYSCON_AHBCLKCTRL3_CMP2_SHIFT            (18U)
71522 /*! CMP2 - Enables the clock for CMP2
71523  *  0b1..Enables clock
71524  *  0b0..Disables clock
71525  */
71526 #define SYSCON_AHBCLKCTRL3_CMP2(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_CMP2_SHIFT)) & SYSCON_AHBCLKCTRL3_CMP2_MASK)
71527 
71528 #define SYSCON_AHBCLKCTRL3_VREF_MASK             (0x80000U)
71529 #define SYSCON_AHBCLKCTRL3_VREF_SHIFT            (19U)
71530 /*! VREF - Enables the clock for VREF
71531  *  0b1..Enables clock
71532  *  0b0..Disables clock
71533  */
71534 #define SYSCON_AHBCLKCTRL3_VREF(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_VREF_SHIFT)) & SYSCON_AHBCLKCTRL3_VREF_MASK)
71535 
71536 #define SYSCON_AHBCLKCTRL3_COOLFLUX_APB_MASK     (0x100000U)
71537 #define SYSCON_AHBCLKCTRL3_COOLFLUX_APB_SHIFT    (20U)
71538 /*! COOLFLUX_APB - Enables the clock for CoolFlux APB
71539  *  0b1..Enables clock (CoolFlux needs to be properly programmed before the clock enabled.)
71540  *  0b0..Disables clock
71541  */
71542 #define SYSCON_AHBCLKCTRL3_COOLFLUX_APB(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_COOLFLUX_APB_SHIFT)) & SYSCON_AHBCLKCTRL3_COOLFLUX_APB_MASK)
71543 
71544 #define SYSCON_AHBCLKCTRL3_NPU_MASK              (0x200000U)
71545 #define SYSCON_AHBCLKCTRL3_NPU_SHIFT             (21U)
71546 /*! NPU - Enables the clock for NPU
71547  *  0b1..Enables clock
71548  *  0b0..Disables clock
71549  */
71550 #define SYSCON_AHBCLKCTRL3_NPU(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_NPU_SHIFT)) & SYSCON_AHBCLKCTRL3_NPU_MASK)
71551 
71552 #define SYSCON_AHBCLKCTRL3_TSI_MASK              (0x400000U)
71553 #define SYSCON_AHBCLKCTRL3_TSI_SHIFT             (22U)
71554 /*! TSI - Enables the clock for TSI
71555  *  0b1..Enables clock
71556  *  0b0..Disables clock
71557  */
71558 #define SYSCON_AHBCLKCTRL3_TSI(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_TSI_SHIFT)) & SYSCON_AHBCLKCTRL3_TSI_MASK)
71559 
71560 #define SYSCON_AHBCLKCTRL3_EWM_MASK              (0x800000U)
71561 #define SYSCON_AHBCLKCTRL3_EWM_SHIFT             (23U)
71562 /*! EWM - Enables the clock for EWM
71563  *  0b1..Enables clock
71564  *  0b0..Disables clock
71565  */
71566 #define SYSCON_AHBCLKCTRL3_EWM(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_EWM_SHIFT)) & SYSCON_AHBCLKCTRL3_EWM_MASK)
71567 
71568 #define SYSCON_AHBCLKCTRL3_EIM_MASK              (0x1000000U)
71569 #define SYSCON_AHBCLKCTRL3_EIM_SHIFT             (24U)
71570 /*! EIM - Enables the clock for EIM
71571  *  0b1..Enables clock
71572  *  0b0..Disables clock
71573  */
71574 #define SYSCON_AHBCLKCTRL3_EIM(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_EIM_SHIFT)) & SYSCON_AHBCLKCTRL3_EIM_MASK)
71575 
71576 #define SYSCON_AHBCLKCTRL3_ERM_MASK              (0x2000000U)
71577 #define SYSCON_AHBCLKCTRL3_ERM_SHIFT             (25U)
71578 /*! ERM - Enables the clock for ERM
71579  *  0b1..Enables clock
71580  *  0b0..Disables clock
71581  */
71582 #define SYSCON_AHBCLKCTRL3_ERM(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_ERM_SHIFT)) & SYSCON_AHBCLKCTRL3_ERM_MASK)
71583 
71584 #define SYSCON_AHBCLKCTRL3_INTM_MASK             (0x4000000U)
71585 #define SYSCON_AHBCLKCTRL3_INTM_SHIFT            (26U)
71586 /*! INTM - Enables the clock for INTM
71587  *  0b1..Enables clock
71588  *  0b0..Disables clock
71589  */
71590 #define SYSCON_AHBCLKCTRL3_INTM(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_INTM_SHIFT)) & SYSCON_AHBCLKCTRL3_INTM_MASK)
71591 
71592 #define SYSCON_AHBCLKCTRL3_SEMA42_MASK           (0x8000000U)
71593 #define SYSCON_AHBCLKCTRL3_SEMA42_SHIFT          (27U)
71594 /*! SEMA42 - Enables the clock for Semaphore
71595  *  0b1..Enables clock
71596  *  0b0..Disables clock
71597  */
71598 #define SYSCON_AHBCLKCTRL3_SEMA42(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_SEMA42_SHIFT)) & SYSCON_AHBCLKCTRL3_SEMA42_MASK)
71599 /*! @} */
71600 
71601 /*! @name AHBCLKCTRLSET - AHB Clock Control Set */
71602 /*! @{ */
71603 
71604 #define SYSCON_AHBCLKCTRLSET_DATA_MASK           (0xFFFFFFFFU)
71605 #define SYSCON_AHBCLKCTRLSET_DATA_SHIFT          (0U)
71606 /*! DATA - Data array value */
71607 #define SYSCON_AHBCLKCTRLSET_DATA(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLSET_DATA_SHIFT)) & SYSCON_AHBCLKCTRLSET_DATA_MASK)
71608 /*! @} */
71609 
71610 /* The count of SYSCON_AHBCLKCTRLSET */
71611 #define SYSCON_AHBCLKCTRLSET_COUNT               (4U)
71612 
71613 /*! @name AHBCLKCTRLCLR - AHB Clock Control Clear */
71614 /*! @{ */
71615 
71616 #define SYSCON_AHBCLKCTRLCLR_DATA_MASK           (0xFFFFFFFFU)
71617 #define SYSCON_AHBCLKCTRLCLR_DATA_SHIFT          (0U)
71618 /*! DATA - Data array value */
71619 #define SYSCON_AHBCLKCTRLCLR_DATA(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLCLR_DATA_SHIFT)) & SYSCON_AHBCLKCTRLCLR_DATA_MASK)
71620 /*! @} */
71621 
71622 /* The count of SYSCON_AHBCLKCTRLCLR */
71623 #define SYSCON_AHBCLKCTRLCLR_COUNT               (4U)
71624 
71625 /*! @name SYSTICKCLKSEL0 - CPU0 System Tick Timer Source Select */
71626 /*! @{ */
71627 
71628 #define SYSCON_SYSTICKCLKSEL0_SEL_MASK           (0x7U)
71629 #define SYSCON_SYSTICKCLKSEL0_SEL_SHIFT          (0U)
71630 /*! SEL - Selects the System Tick Timer for CPU0 source
71631  *  0b000..SYSTICKCLKDIV0 output
71632  *  0b001..Clk 1 MHz clock
71633  *  0b010..LP Oscillator clock
71634  *  0b011..No clock
71635  *  0b100..No clock
71636  *  0b101..No clock
71637  *  0b110..No clock
71638  *  0b111..No clock
71639  */
71640 #define SYSCON_SYSTICKCLKSEL0_SEL(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKSEL0_SEL_SHIFT)) & SYSCON_SYSTICKCLKSEL0_SEL_MASK)
71641 /*! @} */
71642 
71643 /*! @name SYSTICKCLKSEL1 - CPU1 System Tick Timer Source Select */
71644 /*! @{ */
71645 
71646 #define SYSCON_SYSTICKCLKSEL1_SEL_MASK           (0x7U)
71647 #define SYSCON_SYSTICKCLKSEL1_SEL_SHIFT          (0U)
71648 /*! SEL - Selects the System Tick Timer for CPU1 source.
71649  *  0b000..SYSTICKCLKDIV1 output
71650  *  0b001..Clk 1 MHz clock
71651  *  0b010..LP Oscillator clock
71652  *  0b011..No clock
71653  *  0b100..No clock
71654  *  0b101..No clock
71655  *  0b110..No clock
71656  *  0b111..No clock
71657  */
71658 #define SYSCON_SYSTICKCLKSEL1_SEL(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKSEL1_SEL_SHIFT)) & SYSCON_SYSTICKCLKSEL1_SEL_MASK)
71659 /*! @} */
71660 
71661 /*! @name TRACECLKSEL - Trace Clock Source Select */
71662 /*! @{ */
71663 
71664 #define SYSCON_TRACECLKSEL_SEL_MASK              (0x7U)
71665 #define SYSCON_TRACECLKSEL_SEL_SHIFT             (0U)
71666 /*! SEL - Selects the trace clock source.
71667  *  0b000..TRACECLKDIV output
71668  *  0b001..Clk 1 MHz clock
71669  *  0b010..LP Oscillator clock
71670  *  0b011..No clock
71671  *  0b100..No clock
71672  *  0b101..No clock
71673  *  0b110..No clock
71674  *  0b111..No clock
71675  */
71676 #define SYSCON_TRACECLKSEL_SEL(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKSEL_SEL_SHIFT)) & SYSCON_TRACECLKSEL_SEL_MASK)
71677 /*! @} */
71678 
71679 /*! @name CTIMERCLKSEL - CTIMER Clock Source Select */
71680 /*! @{ */
71681 
71682 #define SYSCON_CTIMERCLKSEL_SEL_MASK             (0xFU)
71683 #define SYSCON_CTIMERCLKSEL_SEL_SHIFT            (0U)
71684 /*! SEL - Selects the CTIMER clock source.
71685  *  0b0000..FRO_1M clock
71686  *  0b0001..PLL0 clock
71687  *  0b0010..PLL1_clk0 clock
71688  *  0b0011..FRO_HF clock
71689  *  0b0100..FRO 12MHz clock
71690  *  0b0101..SAI0 MCLK IN clock
71691  *  0b0110..LP Oscillator clock
71692  *  0b0111..No clock
71693  *  0b1000..SAI1 MCLK IN clock
71694  *  0b1001..SAI0 TX_BCLK clock
71695  *  0b1010..SAI0 RX_BCLK clock
71696  *  0b1011..SAI1 TX_BCLK clock
71697  *  0b1100..SAI1 RX_BCLK clock
71698  *  0b1101..No clock
71699  *  0b1110..No clock
71700  *  0b1111..No clock
71701  */
71702 #define SYSCON_CTIMERCLKSEL_SEL(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL_SEL_MASK)
71703 /*! @} */
71704 
71705 /* The count of SYSCON_CTIMERCLKSEL */
71706 #define SYSCON_CTIMERCLKSEL_COUNT                (5U)
71707 
71708 /*! @name CLKOUTSEL - CLKOUT Clock Source Select */
71709 /*! @{ */
71710 
71711 #define SYSCON_CLKOUTSEL_SEL_MASK                (0xFU)
71712 #define SYSCON_CLKOUTSEL_SEL_SHIFT               (0U)
71713 /*! SEL - Selects the CLKOUT clock source.
71714  *  0b0000..Main clock (main_clk)
71715  *  0b0001..PLL0 clock (pll0_clk)
71716  *  0b0010..CLKIN clock (clk_in)
71717  *  0b0011..FRO_HF clock (fro_hf)
71718  *  0b0100..FRO 12 MHz clock (fro_12m)
71719  *  0b0101..PLL1_clk0 clock (pll1_clk)
71720  *  0b0110..LP Oscillator clock (lp_osc)
71721  *  0b0111..USB PLL clock (usb_pll_clk)
71722  *  0b1000..No clock
71723  *  0b1001..No clock
71724  *  0b1010..No clock
71725  *  0b1011..No clock
71726  *  0b1100..No clock
71727  *  0b1101..No clock
71728  *  0b1110..No clock
71729  *  0b1111..No clock
71730  */
71731 #define SYSCON_CLKOUTSEL_SEL(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTSEL_SEL_SHIFT)) & SYSCON_CLKOUTSEL_SEL_MASK)
71732 /*! @} */
71733 
71734 /*! @name ADC0CLKSEL - ADC0 Clock Source Select */
71735 /*! @{ */
71736 
71737 #define SYSCON_ADC0CLKSEL_SEL_MASK               (0x7U)
71738 #define SYSCON_ADC0CLKSEL_SEL_SHIFT              (0U)
71739 /*! SEL - Selects the ADC0 clock source.
71740  *  0b000..No clock
71741  *  0b001..PLL0 clock
71742  *  0b010..FRO_HF clock
71743  *  0b011..FRO 12 MHz clock
71744  *  0b100..Clk_in
71745  *  0b101..PLL1_clk0 clock
71746  *  0b110..USB PLL clock
71747  *  0b111..No clock
71748  */
71749 #define SYSCON_ADC0CLKSEL_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_ADC0CLKSEL_SEL_SHIFT)) & SYSCON_ADC0CLKSEL_SEL_MASK)
71750 /*! @} */
71751 
71752 /*! @name USB0CLKSEL - USB-FS Clock Source Select */
71753 /*! @{ */
71754 
71755 #define SYSCON_USB0CLKSEL_SEL_MASK               (0x7U)
71756 #define SYSCON_USB0CLKSEL_SEL_SHIFT              (0U)
71757 /*! SEL - Selects the USB-FS clock source.
71758  *  0b000..No clock
71759  *  0b001..PLL0 clock
71760  *  0b010..No clock
71761  *  0b011..Clk 48 MHz clock
71762  *  0b100..Clk_in
71763  *  0b101..PLL1_clk0 clock
71764  *  0b110..USB PLL clock
71765  *  0b111..No clock
71766  */
71767 #define SYSCON_USB0CLKSEL_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKSEL_SEL_SHIFT)) & SYSCON_USB0CLKSEL_SEL_MASK)
71768 /*! @} */
71769 
71770 /*! @name FCCLKSEL - LP_FLEXCOMM Clock Source Select for Fractional Rate Divider */
71771 /*! @{ */
71772 
71773 #define SYSCON_FCCLKSEL_SEL_MASK                 (0x7U)
71774 #define SYSCON_FCCLKSEL_SEL_SHIFT                (0U)
71775 /*! SEL - Selects the LP_FLEXCOMM clock source for Fractional Rate Divider.
71776  *  0b000..No clock
71777  *  0b001..PLL divided clock
71778  *  0b010..FRO 12 MHz clock
71779  *  0b011..fro_hf_div clock
71780  *  0b100..clk_1m clock
71781  *  0b101..USB PLL clock
71782  *  0b110..LP Oscillator clock
71783  *  0b111..No clock
71784  */
71785 #define SYSCON_FCCLKSEL_SEL(x)                   (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL_SEL_SHIFT)) & SYSCON_FCCLKSEL_SEL_MASK)
71786 /*! @} */
71787 
71788 /* The count of SYSCON_FCCLKSEL */
71789 #define SYSCON_FCCLKSEL_COUNT                    (10U)
71790 
71791 /*! @name SCTCLKSEL - SCTimer/PWM Clock Source Select */
71792 /*! @{ */
71793 
71794 #define SYSCON_SCTCLKSEL_SEL_MASK                (0xFU)
71795 #define SYSCON_SCTCLKSEL_SEL_SHIFT               (0U)
71796 /*! SEL - Selects the SCTimer/PWM clock source.
71797  *  0b0000..No clock
71798  *  0b0001..PLL0 clock
71799  *  0b0010..CLKIN clock
71800  *  0b0011..FRO_HF clock
71801  *  0b0100..PLL1_clk0 clock
71802  *  0b0101..SAI0 MCLK_IN clock
71803  *  0b0110..USB PLL clock
71804  *  0b0111..No clock
71805  *  0b1000..SAI1 MCLK_IN clock
71806  *  0b1001..No clock
71807  *  0b1010..No clock
71808  *  0b1011..No clock
71809  *  0b1100..No clock
71810  *  0b1101..No clock
71811  *  0b1110..No clock
71812  *  0b1111..No clock
71813  */
71814 #define SYSCON_SCTCLKSEL_SEL(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKSEL_SEL_SHIFT)) & SYSCON_SCTCLKSEL_SEL_MASK)
71815 /*! @} */
71816 
71817 /*! @name SYSTICKCLKDIV - CPU0 System Tick Timer Divider..CPU1 System Tick Timer Divider */
71818 /*! @{ */
71819 
71820 #define SYSCON_SYSTICKCLKDIV_DIV_MASK            (0xFFU)
71821 #define SYSCON_SYSTICKCLKDIV_DIV_SHIFT           (0U)
71822 /*! DIV - Clock divider value */
71823 #define SYSCON_SYSTICKCLKDIV_DIV(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_DIV_SHIFT)) & SYSCON_SYSTICKCLKDIV_DIV_MASK)
71824 
71825 #define SYSCON_SYSTICKCLKDIV_RESET_MASK          (0x20000000U)
71826 #define SYSCON_SYSTICKCLKDIV_RESET_SHIFT         (29U)
71827 /*! RESET - Resets the divider counter
71828  *  0b1..Divider is reset.
71829  *  0b0..Divider is not reset
71830  */
71831 #define SYSCON_SYSTICKCLKDIV_RESET(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_RESET_SHIFT)) & SYSCON_SYSTICKCLKDIV_RESET_MASK)
71832 
71833 #define SYSCON_SYSTICKCLKDIV_HALT_MASK           (0x40000000U)
71834 #define SYSCON_SYSTICKCLKDIV_HALT_SHIFT          (30U)
71835 /*! HALT - Halts the divider counter
71836  *  0b1..Divider clock is stopped
71837  *  0b0..Divider clock is running
71838  */
71839 #define SYSCON_SYSTICKCLKDIV_HALT(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_HALT_SHIFT)) & SYSCON_SYSTICKCLKDIV_HALT_MASK)
71840 
71841 #define SYSCON_SYSTICKCLKDIV_UNSTAB_MASK         (0x80000000U)
71842 #define SYSCON_SYSTICKCLKDIV_UNSTAB_SHIFT        (31U)
71843 /*! UNSTAB - Divider status flag
71844  *  0b1..Clock frequency is not stable
71845  *  0b0..Divider clock is stable
71846  */
71847 #define SYSCON_SYSTICKCLKDIV_UNSTAB(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_UNSTAB_SHIFT)) & SYSCON_SYSTICKCLKDIV_UNSTAB_MASK)
71848 /*! @} */
71849 
71850 /* The count of SYSCON_SYSTICKCLKDIV */
71851 #define SYSCON_SYSTICKCLKDIV_COUNT               (2U)
71852 
71853 /*! @name TRACECLKDIV - TRACE Clock Divider */
71854 /*! @{ */
71855 
71856 #define SYSCON_TRACECLKDIV_DIV_MASK              (0xFFU)
71857 #define SYSCON_TRACECLKDIV_DIV_SHIFT             (0U)
71858 /*! DIV - Clock divider value */
71859 #define SYSCON_TRACECLKDIV_DIV(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_DIV_SHIFT)) & SYSCON_TRACECLKDIV_DIV_MASK)
71860 
71861 #define SYSCON_TRACECLKDIV_RESET_MASK            (0x20000000U)
71862 #define SYSCON_TRACECLKDIV_RESET_SHIFT           (29U)
71863 /*! RESET - Resets the divider counter
71864  *  0b1..Divider is reset
71865  *  0b0..Divider is not reset
71866  */
71867 #define SYSCON_TRACECLKDIV_RESET(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_RESET_SHIFT)) & SYSCON_TRACECLKDIV_RESET_MASK)
71868 
71869 #define SYSCON_TRACECLKDIV_HALT_MASK             (0x40000000U)
71870 #define SYSCON_TRACECLKDIV_HALT_SHIFT            (30U)
71871 /*! HALT - Halts the divider counter
71872  *  0b1..Divider clock is stopped
71873  *  0b0..Divider clock is running
71874  */
71875 #define SYSCON_TRACECLKDIV_HALT(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_HALT_SHIFT)) & SYSCON_TRACECLKDIV_HALT_MASK)
71876 
71877 #define SYSCON_TRACECLKDIV_UNSTAB_MASK           (0x80000000U)
71878 #define SYSCON_TRACECLKDIV_UNSTAB_SHIFT          (31U)
71879 /*! UNSTAB - Divider status flag
71880  *  0b1..Clock frequency is not stable
71881  *  0b0..Divider clock is stable
71882  */
71883 #define SYSCON_TRACECLKDIV_UNSTAB(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_UNSTAB_SHIFT)) & SYSCON_TRACECLKDIV_UNSTAB_MASK)
71884 /*! @} */
71885 
71886 /*! @name TSICLKSEL - TSI Function Clock Source Select */
71887 /*! @{ */
71888 
71889 #define SYSCON_TSICLKSEL_SEL_MASK                (0x7U)
71890 #define SYSCON_TSICLKSEL_SEL_SHIFT               (0U)
71891 /*! SEL - Selects the TSI function clock source.
71892  *  0b000..No clock
71893  *  0b001..No clock
71894  *  0b010..clk_in
71895  *  0b011..No clock
71896  *  0b100..FRO_12Mhz clock
71897  *  0b101..No clock
71898  *  0b110..No clock
71899  *  0b111..No clock
71900  */
71901 #define SYSCON_TSICLKSEL_SEL(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_TSICLKSEL_SEL_SHIFT)) & SYSCON_TSICLKSEL_SEL_MASK)
71902 /*! @} */
71903 
71904 /*! @name SINCFILTCLKSEL - SINC FILTER Function Clock Source Select */
71905 /*! @{ */
71906 
71907 #define SYSCON_SINCFILTCLKSEL_SEL_MASK           (0x7U)
71908 #define SYSCON_SINCFILTCLKSEL_SEL_SHIFT          (0U)
71909 /*! SEL - Selects the SINC FILTER function clock source.
71910  *  0b000..No clock
71911  *  0b001..PLL0 clock
71912  *  0b010..clk_in
71913  *  0b011..FRO_HF clock
71914  *  0b100..FRO_12Mhz clock
71915  *  0b101..PLL1_clk0 clock
71916  *  0b110..USB PLL clock
71917  *  0b111..No clock
71918  */
71919 #define SYSCON_SINCFILTCLKSEL_SEL(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_SINCFILTCLKSEL_SEL_SHIFT)) & SYSCON_SINCFILTCLKSEL_SEL_MASK)
71920 /*! @} */
71921 
71922 /*! @name SLOWCLKDIV - SLOW_CLK Clock Divider */
71923 /*! @{ */
71924 
71925 #define SYSCON_SLOWCLKDIV_RESET_MASK             (0x20000000U)
71926 #define SYSCON_SLOWCLKDIV_RESET_SHIFT            (29U)
71927 /*! RESET - Resets the divider counter
71928  *  0b1..Divider is reset
71929  *  0b0..Divider is not reset
71930  */
71931 #define SYSCON_SLOWCLKDIV_RESET(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_SLOWCLKDIV_RESET_SHIFT)) & SYSCON_SLOWCLKDIV_RESET_MASK)
71932 
71933 #define SYSCON_SLOWCLKDIV_HALT_MASK              (0x40000000U)
71934 #define SYSCON_SLOWCLKDIV_HALT_SHIFT             (30U)
71935 /*! HALT - Halts the divider counter
71936  *  0b1..Divider clock is stopped
71937  *  0b0..Divider clock is running
71938  */
71939 #define SYSCON_SLOWCLKDIV_HALT(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SLOWCLKDIV_HALT_SHIFT)) & SYSCON_SLOWCLKDIV_HALT_MASK)
71940 
71941 #define SYSCON_SLOWCLKDIV_UNSTAB_MASK            (0x80000000U)
71942 #define SYSCON_SLOWCLKDIV_UNSTAB_SHIFT           (31U)
71943 /*! UNSTAB - Divider status flag
71944  *  0b1..Clock frequency is not stable
71945  *  0b0..Divider clock is stable
71946  */
71947 #define SYSCON_SLOWCLKDIV_UNSTAB(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_SLOWCLKDIV_UNSTAB_SHIFT)) & SYSCON_SLOWCLKDIV_UNSTAB_MASK)
71948 /*! @} */
71949 
71950 /*! @name TSICLKDIV - TSI Function Clock Divider */
71951 /*! @{ */
71952 
71953 #define SYSCON_TSICLKDIV_DIV_MASK                (0xFFU)
71954 #define SYSCON_TSICLKDIV_DIV_SHIFT               (0U)
71955 /*! DIV - Clock divider value: */
71956 #define SYSCON_TSICLKDIV_DIV(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_TSICLKDIV_DIV_SHIFT)) & SYSCON_TSICLKDIV_DIV_MASK)
71957 
71958 #define SYSCON_TSICLKDIV_RESET_MASK              (0x20000000U)
71959 #define SYSCON_TSICLKDIV_RESET_SHIFT             (29U)
71960 /*! RESET - Resets the divider counter
71961  *  0b1..Divider is reset
71962  *  0b0..Divider is not reset
71963  */
71964 #define SYSCON_TSICLKDIV_RESET(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_TSICLKDIV_RESET_SHIFT)) & SYSCON_TSICLKDIV_RESET_MASK)
71965 
71966 #define SYSCON_TSICLKDIV_HALT_MASK               (0x40000000U)
71967 #define SYSCON_TSICLKDIV_HALT_SHIFT              (30U)
71968 /*! HALT - Halts the divider counter
71969  *  0b1..Divider clock is stopped
71970  *  0b0..Divider clock is running
71971  */
71972 #define SYSCON_TSICLKDIV_HALT(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_TSICLKDIV_HALT_SHIFT)) & SYSCON_TSICLKDIV_HALT_MASK)
71973 
71974 #define SYSCON_TSICLKDIV_UNSTAB_MASK             (0x80000000U)
71975 #define SYSCON_TSICLKDIV_UNSTAB_SHIFT            (31U)
71976 /*! UNSTAB - Divider status flag
71977  *  0b1..Clock frequency is not stable
71978  *  0b0..Divider clock is stable
71979  */
71980 #define SYSCON_TSICLKDIV_UNSTAB(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_TSICLKDIV_UNSTAB_SHIFT)) & SYSCON_TSICLKDIV_UNSTAB_MASK)
71981 /*! @} */
71982 
71983 /*! @name AHBCLKDIV - System Clock Divider */
71984 /*! @{ */
71985 
71986 #define SYSCON_AHBCLKDIV_DIV_MASK                (0xFFU)
71987 #define SYSCON_AHBCLKDIV_DIV_SHIFT               (0U)
71988 /*! DIV - Clock divider value */
71989 #define SYSCON_AHBCLKDIV_DIV(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_DIV_SHIFT)) & SYSCON_AHBCLKDIV_DIV_MASK)
71990 
71991 #define SYSCON_AHBCLKDIV_UNSTAB_MASK             (0x80000000U)
71992 #define SYSCON_AHBCLKDIV_UNSTAB_SHIFT            (31U)
71993 /*! UNSTAB - Divider status flag
71994  *  0b1..Clock frequency is not stable
71995  *  0b0..Divider clock is stable
71996  */
71997 #define SYSCON_AHBCLKDIV_UNSTAB(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_UNSTAB_SHIFT)) & SYSCON_AHBCLKDIV_UNSTAB_MASK)
71998 /*! @} */
71999 
72000 /*! @name CLKOUTDIV - CLKOUT Clock Divider */
72001 /*! @{ */
72002 
72003 #define SYSCON_CLKOUTDIV_DIV_MASK                (0xFFU)
72004 #define SYSCON_CLKOUTDIV_DIV_SHIFT               (0U)
72005 /*! DIV - Clock divider value */
72006 #define SYSCON_CLKOUTDIV_DIV(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_DIV_SHIFT)) & SYSCON_CLKOUTDIV_DIV_MASK)
72007 
72008 #define SYSCON_CLKOUTDIV_RESET_MASK              (0x20000000U)
72009 #define SYSCON_CLKOUTDIV_RESET_SHIFT             (29U)
72010 /*! RESET - Resets the divider counter
72011  *  0b1..Divider is reset
72012  *  0b0..Divider is not reset
72013  */
72014 #define SYSCON_CLKOUTDIV_RESET(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_RESET_SHIFT)) & SYSCON_CLKOUTDIV_RESET_MASK)
72015 
72016 #define SYSCON_CLKOUTDIV_HALT_MASK               (0x40000000U)
72017 #define SYSCON_CLKOUTDIV_HALT_SHIFT              (30U)
72018 /*! HALT - Halts the divider counter
72019  *  0b1..Divider clock is stopped
72020  *  0b0..Divider clock is running
72021  */
72022 #define SYSCON_CLKOUTDIV_HALT(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_HALT_SHIFT)) & SYSCON_CLKOUTDIV_HALT_MASK)
72023 
72024 #define SYSCON_CLKOUTDIV_UNSTAB_MASK             (0x80000000U)
72025 #define SYSCON_CLKOUTDIV_UNSTAB_SHIFT            (31U)
72026 /*! UNSTAB - Divider status flag
72027  *  0b1..Clock frequency is not stable
72028  *  0b0..Divider clock is stable
72029  */
72030 #define SYSCON_CLKOUTDIV_UNSTAB(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_UNSTAB_SHIFT)) & SYSCON_CLKOUTDIV_UNSTAB_MASK)
72031 /*! @} */
72032 
72033 /*! @name FROHFDIV - FRO_HF_DIV Clock Divider */
72034 /*! @{ */
72035 
72036 #define SYSCON_FROHFDIV_DIV_MASK                 (0xFFU)
72037 #define SYSCON_FROHFDIV_DIV_SHIFT                (0U)
72038 /*! DIV - Clock divider value */
72039 #define SYSCON_FROHFDIV_DIV(x)                   (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_DIV_SHIFT)) & SYSCON_FROHFDIV_DIV_MASK)
72040 
72041 #define SYSCON_FROHFDIV_HALT_MASK                (0x40000000U)
72042 #define SYSCON_FROHFDIV_HALT_SHIFT               (30U)
72043 /*! HALT - Halts the divider counter
72044  *  0b1..Divider clock is stopped
72045  *  0b0..Divider clock is running, this bit is set to 0 when the register is written.
72046  */
72047 #define SYSCON_FROHFDIV_HALT(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_HALT_SHIFT)) & SYSCON_FROHFDIV_HALT_MASK)
72048 
72049 #define SYSCON_FROHFDIV_UNSTAB_MASK              (0x80000000U)
72050 #define SYSCON_FROHFDIV_UNSTAB_SHIFT             (31U)
72051 /*! UNSTAB - Divider status flag
72052  *  0b1..Clock frequency is not stable
72053  *  0b0..Divider clock is stable
72054  */
72055 #define SYSCON_FROHFDIV_UNSTAB(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_UNSTAB_SHIFT)) & SYSCON_FROHFDIV_UNSTAB_MASK)
72056 /*! @} */
72057 
72058 /*! @name WDT0CLKDIV - WDT0 Clock Divider */
72059 /*! @{ */
72060 
72061 #define SYSCON_WDT0CLKDIV_DIV_MASK               (0x3FU)
72062 #define SYSCON_WDT0CLKDIV_DIV_SHIFT              (0U)
72063 /*! DIV - Clock divider value */
72064 #define SYSCON_WDT0CLKDIV_DIV(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_WDT0CLKDIV_DIV_SHIFT)) & SYSCON_WDT0CLKDIV_DIV_MASK)
72065 
72066 #define SYSCON_WDT0CLKDIV_RESET_MASK             (0x20000000U)
72067 #define SYSCON_WDT0CLKDIV_RESET_SHIFT            (29U)
72068 /*! RESET - Resets the divider counter
72069  *  0b1..Divider is reset
72070  *  0b0..Divider is not reset
72071  */
72072 #define SYSCON_WDT0CLKDIV_RESET(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_WDT0CLKDIV_RESET_SHIFT)) & SYSCON_WDT0CLKDIV_RESET_MASK)
72073 
72074 #define SYSCON_WDT0CLKDIV_HALT_MASK              (0x40000000U)
72075 #define SYSCON_WDT0CLKDIV_HALT_SHIFT             (30U)
72076 /*! HALT - Halts the divider counter
72077  *  0b1..Divider clock is stopped
72078  *  0b0..Divider clock is running
72079  */
72080 #define SYSCON_WDT0CLKDIV_HALT(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_WDT0CLKDIV_HALT_SHIFT)) & SYSCON_WDT0CLKDIV_HALT_MASK)
72081 
72082 #define SYSCON_WDT0CLKDIV_UNSTAB_MASK            (0x80000000U)
72083 #define SYSCON_WDT0CLKDIV_UNSTAB_SHIFT           (31U)
72084 /*! UNSTAB - Divider status flag
72085  *  0b1..Clock frequency is not stable
72086  *  0b0..Divider clock is stable
72087  */
72088 #define SYSCON_WDT0CLKDIV_UNSTAB(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_WDT0CLKDIV_UNSTAB_SHIFT)) & SYSCON_WDT0CLKDIV_UNSTAB_MASK)
72089 /*! @} */
72090 
72091 /*! @name ADC0CLKDIV - ADC0 Clock Divider */
72092 /*! @{ */
72093 
72094 #define SYSCON_ADC0CLKDIV_DIV_MASK               (0x7U)
72095 #define SYSCON_ADC0CLKDIV_DIV_SHIFT              (0U)
72096 /*! DIV - Clock divider value */
72097 #define SYSCON_ADC0CLKDIV_DIV(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_ADC0CLKDIV_DIV_SHIFT)) & SYSCON_ADC0CLKDIV_DIV_MASK)
72098 
72099 #define SYSCON_ADC0CLKDIV_RESET_MASK             (0x20000000U)
72100 #define SYSCON_ADC0CLKDIV_RESET_SHIFT            (29U)
72101 /*! RESET - Resets the divider counter
72102  *  0b1..Divider is reset
72103  *  0b0..Divider is not reset
72104  */
72105 #define SYSCON_ADC0CLKDIV_RESET(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_ADC0CLKDIV_RESET_SHIFT)) & SYSCON_ADC0CLKDIV_RESET_MASK)
72106 
72107 #define SYSCON_ADC0CLKDIV_HALT_MASK              (0x40000000U)
72108 #define SYSCON_ADC0CLKDIV_HALT_SHIFT             (30U)
72109 /*! HALT - Halts the divider counter
72110  *  0b1..Divider clock is stopped
72111  *  0b0..Divider clock is running
72112  */
72113 #define SYSCON_ADC0CLKDIV_HALT(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_ADC0CLKDIV_HALT_SHIFT)) & SYSCON_ADC0CLKDIV_HALT_MASK)
72114 
72115 #define SYSCON_ADC0CLKDIV_UNSTAB_MASK            (0x80000000U)
72116 #define SYSCON_ADC0CLKDIV_UNSTAB_SHIFT           (31U)
72117 /*! UNSTAB - Divider status flag
72118  *  0b1..Clock frequency is not stable
72119  *  0b0..Divider clock is stable
72120  */
72121 #define SYSCON_ADC0CLKDIV_UNSTAB(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_ADC0CLKDIV_UNSTAB_SHIFT)) & SYSCON_ADC0CLKDIV_UNSTAB_MASK)
72122 /*! @} */
72123 
72124 /*! @name USB0CLKDIV - USB-FS Clock Divider */
72125 /*! @{ */
72126 
72127 #define SYSCON_USB0CLKDIV_DIV_MASK               (0xFFU)
72128 #define SYSCON_USB0CLKDIV_DIV_SHIFT              (0U)
72129 /*! DIV - Clock divider value */
72130 #define SYSCON_USB0CLKDIV_DIV(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_DIV_SHIFT)) & SYSCON_USB0CLKDIV_DIV_MASK)
72131 
72132 #define SYSCON_USB0CLKDIV_RESET_MASK             (0x20000000U)
72133 #define SYSCON_USB0CLKDIV_RESET_SHIFT            (29U)
72134 /*! RESET - Resets the divider counter
72135  *  0b1..Divider is reset
72136  *  0b0..Divider is not reset
72137  */
72138 #define SYSCON_USB0CLKDIV_RESET(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_RESET_SHIFT)) & SYSCON_USB0CLKDIV_RESET_MASK)
72139 
72140 #define SYSCON_USB0CLKDIV_HALT_MASK              (0x40000000U)
72141 #define SYSCON_USB0CLKDIV_HALT_SHIFT             (30U)
72142 /*! HALT - Halts the divider counter
72143  *  0b1..Divider clock is stopped
72144  *  0b0..Divider clock is running
72145  */
72146 #define SYSCON_USB0CLKDIV_HALT(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_HALT_SHIFT)) & SYSCON_USB0CLKDIV_HALT_MASK)
72147 
72148 #define SYSCON_USB0CLKDIV_UNSTAB_MASK            (0x80000000U)
72149 #define SYSCON_USB0CLKDIV_UNSTAB_SHIFT           (31U)
72150 /*! UNSTAB - Divider status flag
72151  *  0b1..Clock frequency is not stable
72152  *  0b0..Divider clock is stable
72153  */
72154 #define SYSCON_USB0CLKDIV_UNSTAB(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_UNSTAB_SHIFT)) & SYSCON_USB0CLKDIV_UNSTAB_MASK)
72155 /*! @} */
72156 
72157 /*! @name SCTCLKDIV - SCT/PWM Clock Divider */
72158 /*! @{ */
72159 
72160 #define SYSCON_SCTCLKDIV_DIV_MASK                (0xFFU)
72161 #define SYSCON_SCTCLKDIV_DIV_SHIFT               (0U)
72162 /*! DIV - Clock divider value */
72163 #define SYSCON_SCTCLKDIV_DIV(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_DIV_SHIFT)) & SYSCON_SCTCLKDIV_DIV_MASK)
72164 
72165 #define SYSCON_SCTCLKDIV_RESET_MASK              (0x20000000U)
72166 #define SYSCON_SCTCLKDIV_RESET_SHIFT             (29U)
72167 /*! RESET - Resets the divider counter
72168  *  0b1..Divider is reset
72169  *  0b0..Divider is not reset
72170  */
72171 #define SYSCON_SCTCLKDIV_RESET(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_RESET_SHIFT)) & SYSCON_SCTCLKDIV_RESET_MASK)
72172 
72173 #define SYSCON_SCTCLKDIV_HALT_MASK               (0x40000000U)
72174 #define SYSCON_SCTCLKDIV_HALT_SHIFT              (30U)
72175 /*! HALT - Halts the divider counter
72176  *  0b1..Divider clock is stopped
72177  *  0b0..Divider clock is running
72178  */
72179 #define SYSCON_SCTCLKDIV_HALT(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_HALT_SHIFT)) & SYSCON_SCTCLKDIV_HALT_MASK)
72180 
72181 #define SYSCON_SCTCLKDIV_UNSTAB_MASK             (0x80000000U)
72182 #define SYSCON_SCTCLKDIV_UNSTAB_SHIFT            (31U)
72183 /*! UNSTAB - Divider status flag
72184  *  0b1..Clock frequency is not stable
72185  *  0b0..Divider clock is stable
72186  */
72187 #define SYSCON_SCTCLKDIV_UNSTAB(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_UNSTAB_SHIFT)) & SYSCON_SCTCLKDIV_UNSTAB_MASK)
72188 /*! @} */
72189 
72190 /*! @name PLLCLKDIV - PLL Clock Divider */
72191 /*! @{ */
72192 
72193 #define SYSCON_PLLCLKDIV_DIV_MASK                (0xFFU)
72194 #define SYSCON_PLLCLKDIV_DIV_SHIFT               (0U)
72195 /*! DIV - Clock divider value */
72196 #define SYSCON_PLLCLKDIV_DIV(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_PLLCLKDIV_DIV_SHIFT)) & SYSCON_PLLCLKDIV_DIV_MASK)
72197 
72198 #define SYSCON_PLLCLKDIV_RESET_MASK              (0x20000000U)
72199 #define SYSCON_PLLCLKDIV_RESET_SHIFT             (29U)
72200 /*! RESET - Resets the divider counter
72201  *  0b1..Divider is reset
72202  *  0b0..Divider is not reset
72203  */
72204 #define SYSCON_PLLCLKDIV_RESET(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_PLLCLKDIV_RESET_SHIFT)) & SYSCON_PLLCLKDIV_RESET_MASK)
72205 
72206 #define SYSCON_PLLCLKDIV_HALT_MASK               (0x40000000U)
72207 #define SYSCON_PLLCLKDIV_HALT_SHIFT              (30U)
72208 /*! HALT - Halts the divider counter
72209  *  0b1..Divider clock is stopped
72210  *  0b0..Divider clock is running
72211  */
72212 #define SYSCON_PLLCLKDIV_HALT(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_PLLCLKDIV_HALT_SHIFT)) & SYSCON_PLLCLKDIV_HALT_MASK)
72213 
72214 #define SYSCON_PLLCLKDIV_UNSTAB_MASK             (0x80000000U)
72215 #define SYSCON_PLLCLKDIV_UNSTAB_SHIFT            (31U)
72216 /*! UNSTAB - Divider status flag
72217  *  0b1..Clock frequency is not stable
72218  *  0b0..Divider clock is stable
72219  */
72220 #define SYSCON_PLLCLKDIV_UNSTAB(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_PLLCLKDIV_UNSTAB_SHIFT)) & SYSCON_PLLCLKDIV_UNSTAB_MASK)
72221 /*! @} */
72222 
72223 /*! @name CTIMERXCLKDIV_CTIMERCLKDIV - CTimer Clock Divider */
72224 /*! @{ */
72225 
72226 #define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_DIV_MASK (0xFFU)
72227 #define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_DIV_SHIFT (0U)
72228 /*! DIV - Clock divider value */
72229 #define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_DIV_SHIFT)) & SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_DIV_MASK)
72230 
72231 #define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_RESET_MASK (0x20000000U)
72232 #define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_RESET_SHIFT (29U)
72233 /*! RESET - Resets the divider counter
72234  *  0b0..Divider is not reset
72235  *  0b1..Divider is reset
72236  */
72237 #define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_RESET_SHIFT)) & SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_RESET_MASK)
72238 
72239 #define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_HALT_MASK (0x40000000U)
72240 #define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_HALT_SHIFT (30U)
72241 /*! HALT - Halts the divider counter
72242  *  0b0..Divider clock is running
72243  *  0b1..Divider clock has stopped
72244  */
72245 #define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_HALT_SHIFT)) & SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_HALT_MASK)
72246 
72247 #define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_UNSTAB_MASK (0x80000000U)
72248 #define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_UNSTAB_SHIFT (31U)
72249 /*! UNSTAB - Divider status flag
72250  *  0b0..Stable divider clock
72251  *  0b1..Unstable clock frequency
72252  */
72253 #define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_UNSTAB_SHIFT)) & SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_UNSTAB_MASK)
72254 /*! @} */
72255 
72256 /* The count of SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV */
72257 #define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_COUNT  (5U)
72258 
72259 /*! @name PLL1CLK0DIV - PLL1 Clock 0 Divider */
72260 /*! @{ */
72261 
72262 #define SYSCON_PLL1CLK0DIV_DIV_MASK              (0xFFU)
72263 #define SYSCON_PLL1CLK0DIV_DIV_SHIFT             (0U)
72264 /*! DIV - Clock divider value */
72265 #define SYSCON_PLL1CLK0DIV_DIV(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CLK0DIV_DIV_SHIFT)) & SYSCON_PLL1CLK0DIV_DIV_MASK)
72266 
72267 #define SYSCON_PLL1CLK0DIV_RESET_MASK            (0x20000000U)
72268 #define SYSCON_PLL1CLK0DIV_RESET_SHIFT           (29U)
72269 /*! RESET - Resets the divider counter
72270  *  0b1..Divider is reset
72271  *  0b0..Divider is not reset
72272  */
72273 #define SYSCON_PLL1CLK0DIV_RESET(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CLK0DIV_RESET_SHIFT)) & SYSCON_PLL1CLK0DIV_RESET_MASK)
72274 
72275 #define SYSCON_PLL1CLK0DIV_HALT_MASK             (0x40000000U)
72276 #define SYSCON_PLL1CLK0DIV_HALT_SHIFT            (30U)
72277 /*! HALT - Halts the divider counter
72278  *  0b1..Divider clock is stopped
72279  *  0b0..Divider clock is running
72280  */
72281 #define SYSCON_PLL1CLK0DIV_HALT(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CLK0DIV_HALT_SHIFT)) & SYSCON_PLL1CLK0DIV_HALT_MASK)
72282 
72283 #define SYSCON_PLL1CLK0DIV_UNSTAB_MASK           (0x80000000U)
72284 #define SYSCON_PLL1CLK0DIV_UNSTAB_SHIFT          (31U)
72285 /*! UNSTAB - Divider status flag
72286  *  0b1..Clock frequency is not stable
72287  *  0b0..Divider clock is stable
72288  */
72289 #define SYSCON_PLL1CLK0DIV_UNSTAB(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CLK0DIV_UNSTAB_SHIFT)) & SYSCON_PLL1CLK0DIV_UNSTAB_MASK)
72290 /*! @} */
72291 
72292 /*! @name PLL1CLK1DIV - PLL1 Clock 1 Divider */
72293 /*! @{ */
72294 
72295 #define SYSCON_PLL1CLK1DIV_DIV_MASK              (0xFFU)
72296 #define SYSCON_PLL1CLK1DIV_DIV_SHIFT             (0U)
72297 /*! DIV - Clock divider value */
72298 #define SYSCON_PLL1CLK1DIV_DIV(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CLK1DIV_DIV_SHIFT)) & SYSCON_PLL1CLK1DIV_DIV_MASK)
72299 
72300 #define SYSCON_PLL1CLK1DIV_RESET_MASK            (0x20000000U)
72301 #define SYSCON_PLL1CLK1DIV_RESET_SHIFT           (29U)
72302 /*! RESET - Resets the divider counter
72303  *  0b1..Divider is reset
72304  *  0b0..Divider is not reset
72305  */
72306 #define SYSCON_PLL1CLK1DIV_RESET(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CLK1DIV_RESET_SHIFT)) & SYSCON_PLL1CLK1DIV_RESET_MASK)
72307 
72308 #define SYSCON_PLL1CLK1DIV_HALT_MASK             (0x40000000U)
72309 #define SYSCON_PLL1CLK1DIV_HALT_SHIFT            (30U)
72310 /*! HALT - Halts the divider counter
72311  *  0b1..Divider clock is stopped
72312  *  0b0..Divider clock is running
72313  */
72314 #define SYSCON_PLL1CLK1DIV_HALT(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CLK1DIV_HALT_SHIFT)) & SYSCON_PLL1CLK1DIV_HALT_MASK)
72315 
72316 #define SYSCON_PLL1CLK1DIV_UNSTAB_MASK           (0x80000000U)
72317 #define SYSCON_PLL1CLK1DIV_UNSTAB_SHIFT          (31U)
72318 /*! UNSTAB - Divider status flag
72319  *  0b1..Clock frequency is not stable
72320  *  0b0..Divider clock is stable
72321  */
72322 #define SYSCON_PLL1CLK1DIV_UNSTAB(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CLK1DIV_UNSTAB_SHIFT)) & SYSCON_PLL1CLK1DIV_UNSTAB_MASK)
72323 /*! @} */
72324 
72325 /*! @name UTICKCLKDIV - UTICK Clock Divider */
72326 /*! @{ */
72327 
72328 #define SYSCON_UTICKCLKDIV_DIV_MASK              (0x3FU)
72329 #define SYSCON_UTICKCLKDIV_DIV_SHIFT             (0U)
72330 /*! DIV - Clock divider value */
72331 #define SYSCON_UTICKCLKDIV_DIV(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_UTICKCLKDIV_DIV_SHIFT)) & SYSCON_UTICKCLKDIV_DIV_MASK)
72332 
72333 #define SYSCON_UTICKCLKDIV_RESET_MASK            (0x20000000U)
72334 #define SYSCON_UTICKCLKDIV_RESET_SHIFT           (29U)
72335 /*! RESET - Resets the divider counter
72336  *  0b1..Divider is reset
72337  *  0b0..Divider is not reset
72338  */
72339 #define SYSCON_UTICKCLKDIV_RESET(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_UTICKCLKDIV_RESET_SHIFT)) & SYSCON_UTICKCLKDIV_RESET_MASK)
72340 
72341 #define SYSCON_UTICKCLKDIV_HALT_MASK             (0x40000000U)
72342 #define SYSCON_UTICKCLKDIV_HALT_SHIFT            (30U)
72343 /*! HALT - Halts the divider counter
72344  *  0b1..Divider clock is stopped
72345  *  0b0..Divider clock is running
72346  */
72347 #define SYSCON_UTICKCLKDIV_HALT(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_UTICKCLKDIV_HALT_SHIFT)) & SYSCON_UTICKCLKDIV_HALT_MASK)
72348 
72349 #define SYSCON_UTICKCLKDIV_UNSTAB_MASK           (0x80000000U)
72350 #define SYSCON_UTICKCLKDIV_UNSTAB_SHIFT          (31U)
72351 /*! UNSTAB - Divider status flag
72352  *  0b1..Clock frequency is not stable
72353  *  0b0..Divider clock is stable
72354  */
72355 #define SYSCON_UTICKCLKDIV_UNSTAB(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_UTICKCLKDIV_UNSTAB_SHIFT)) & SYSCON_UTICKCLKDIV_UNSTAB_MASK)
72356 /*! @} */
72357 
72358 /*! @name CLKOUT_FRGCTRL - CLKOUT FRG Control */
72359 /*! @{ */
72360 
72361 #define SYSCON_CLKOUT_FRGCTRL_DIV_MASK           (0xFFU)
72362 #define SYSCON_CLKOUT_FRGCTRL_DIV_SHIFT          (0U)
72363 /*! DIV - Divider value */
72364 #define SYSCON_CLKOUT_FRGCTRL_DIV(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUT_FRGCTRL_DIV_SHIFT)) & SYSCON_CLKOUT_FRGCTRL_DIV_MASK)
72365 
72366 #define SYSCON_CLKOUT_FRGCTRL_MULT_MASK          (0xFF00U)
72367 #define SYSCON_CLKOUT_FRGCTRL_MULT_SHIFT         (8U)
72368 /*! MULT - Numerator value */
72369 #define SYSCON_CLKOUT_FRGCTRL_MULT(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUT_FRGCTRL_MULT_SHIFT)) & SYSCON_CLKOUT_FRGCTRL_MULT_MASK)
72370 /*! @} */
72371 
72372 /*! @name CLKUNLOCK - Clock Configuration Unlock */
72373 /*! @{ */
72374 
72375 #define SYSCON_CLKUNLOCK_UNLOCK_MASK             (0x1U)
72376 #define SYSCON_CLKUNLOCK_UNLOCK_SHIFT            (0U)
72377 /*! UNLOCK - Controls clock configuration registers access (for example, xxxDIV, xxxSEL)
72378  *  0b1..Freezes all clock configuration registers update
72379  *  0b0..Updates are allowed to all clock configuration registers
72380  */
72381 #define SYSCON_CLKUNLOCK_UNLOCK(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKUNLOCK_UNLOCK_SHIFT)) & SYSCON_CLKUNLOCK_UNLOCK_MASK)
72382 /*! @} */
72383 
72384 /*! @name NVM_CTRL - NVM Control */
72385 /*! @{ */
72386 
72387 #define SYSCON_NVM_CTRL_DIS_FLASH_SPEC_MASK      (0x1U)
72388 #define SYSCON_NVM_CTRL_DIS_FLASH_SPEC_SHIFT     (0U)
72389 /*! DIS_FLASH_SPEC - Flash speculation control
72390  *  0b0..Enables flash speculation
72391  *  0b1..Disables flash speculation
72392  */
72393 #define SYSCON_NVM_CTRL_DIS_FLASH_SPEC(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_NVM_CTRL_DIS_FLASH_SPEC_SHIFT)) & SYSCON_NVM_CTRL_DIS_FLASH_SPEC_MASK)
72394 
72395 #define SYSCON_NVM_CTRL_DIS_DATA_SPEC_MASK       (0x2U)
72396 #define SYSCON_NVM_CTRL_DIS_DATA_SPEC_SHIFT      (1U)
72397 /*! DIS_DATA_SPEC - Flash data speculation control
72398  *  0b0..Enables data speculation
72399  *  0b1..Disables data speculation
72400  */
72401 #define SYSCON_NVM_CTRL_DIS_DATA_SPEC(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_NVM_CTRL_DIS_DATA_SPEC_SHIFT)) & SYSCON_NVM_CTRL_DIS_DATA_SPEC_MASK)
72402 
72403 #define SYSCON_NVM_CTRL_DIS_FLASH_CACHE_MASK     (0x4U)
72404 #define SYSCON_NVM_CTRL_DIS_FLASH_CACHE_SHIFT    (2U)
72405 /*! DIS_FLASH_CACHE - Flash cache control
72406  *  0b0..Enables flash cache
72407  *  0b1..Disables flash cache
72408  */
72409 #define SYSCON_NVM_CTRL_DIS_FLASH_CACHE(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_NVM_CTRL_DIS_FLASH_CACHE_SHIFT)) & SYSCON_NVM_CTRL_DIS_FLASH_CACHE_MASK)
72410 
72411 #define SYSCON_NVM_CTRL_DIS_FLASH_INST_MASK      (0x8U)
72412 #define SYSCON_NVM_CTRL_DIS_FLASH_INST_SHIFT     (3U)
72413 /*! DIS_FLASH_INST - Flash instruction cache control
72414  *  0b0..Enables flash instruction cache when DIS_FLASH_CACHE=0
72415  *  0b1..Disables flash instruction cache
72416  */
72417 #define SYSCON_NVM_CTRL_DIS_FLASH_INST(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_NVM_CTRL_DIS_FLASH_INST_SHIFT)) & SYSCON_NVM_CTRL_DIS_FLASH_INST_MASK)
72418 
72419 #define SYSCON_NVM_CTRL_DIS_FLASH_DATA_MASK      (0x10U)
72420 #define SYSCON_NVM_CTRL_DIS_FLASH_DATA_SHIFT     (4U)
72421 /*! DIS_FLASH_DATA - Flash data cache control
72422  *  0b0..Enables flash data cache when DIS_FLASH_CACHE=0
72423  *  0b1..Disables flash data cache
72424  */
72425 #define SYSCON_NVM_CTRL_DIS_FLASH_DATA(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_NVM_CTRL_DIS_FLASH_DATA_SHIFT)) & SYSCON_NVM_CTRL_DIS_FLASH_DATA_MASK)
72426 
72427 #define SYSCON_NVM_CTRL_CLR_FLASH_CACHE_MASK     (0x20U)
72428 #define SYSCON_NVM_CTRL_CLR_FLASH_CACHE_SHIFT    (5U)
72429 /*! CLR_FLASH_CACHE - Clear flash cache control
72430  *  0b0..No clear flash cache
72431  *  0b1..Clears flash cache
72432  */
72433 #define SYSCON_NVM_CTRL_CLR_FLASH_CACHE(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_NVM_CTRL_CLR_FLASH_CACHE_SHIFT)) & SYSCON_NVM_CTRL_CLR_FLASH_CACHE_MASK)
72434 
72435 #define SYSCON_NVM_CTRL_FLASH_STALL_EN_MASK      (0x400U)
72436 #define SYSCON_NVM_CTRL_FLASH_STALL_EN_SHIFT     (10U)
72437 /*! FLASH_STALL_EN - FLASH stall on busy control
72438  *  0b0..No stall on FLASH busy
72439  *  0b1..Stall on FLASH busy
72440  */
72441 #define SYSCON_NVM_CTRL_FLASH_STALL_EN(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_NVM_CTRL_FLASH_STALL_EN_SHIFT)) & SYSCON_NVM_CTRL_FLASH_STALL_EN_MASK)
72442 
72443 #define SYSCON_NVM_CTRL_DIS_MBECC_ERR_INST_MASK  (0x10000U)
72444 #define SYSCON_NVM_CTRL_DIS_MBECC_ERR_INST_SHIFT (16U)
72445 /*! DIS_MBECC_ERR_INST
72446  *  0b0..Enables bus error on multi-bit ECC error for instruction
72447  *  0b1..Disables bus error on multi-bit ECC error for instruction
72448  */
72449 #define SYSCON_NVM_CTRL_DIS_MBECC_ERR_INST(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON_NVM_CTRL_DIS_MBECC_ERR_INST_SHIFT)) & SYSCON_NVM_CTRL_DIS_MBECC_ERR_INST_MASK)
72450 
72451 #define SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA_MASK  (0x20000U)
72452 #define SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA_SHIFT (17U)
72453 /*! DIS_MBECC_ERR_DATA
72454  *  0b0..Enables bus error on multi-bit ECC error for data
72455  *  0b1..Disables bus error on multi-bit ECC error for data
72456  */
72457 #define SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA_SHIFT)) & SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA_MASK)
72458 /*! @} */
72459 
72460 /*! @name ROMCR - ROM Wait State */
72461 /*! @{ */
72462 
72463 #define SYSCON_ROMCR_ROM_WAIT_MASK               (0x1U)
72464 #define SYSCON_ROMCR_ROM_WAIT_SHIFT              (0U)
72465 /*! ROM_WAIT - ROM waiting Arm core and other masters for one cycle
72466  *  0b0..Disabled
72467  *  0b1..Enabled
72468  */
72469 #define SYSCON_ROMCR_ROM_WAIT(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_ROMCR_ROM_WAIT_SHIFT)) & SYSCON_ROMCR_ROM_WAIT_MASK)
72470 /*! @} */
72471 
72472 /*! @name SMARTDMAINT - SmartDMA Interrupt Hijack */
72473 /*! @{ */
72474 
72475 #define SYSCON_SMARTDMAINT_INT0_MASK             (0x1U)
72476 #define SYSCON_SMARTDMAINT_INT0_SHIFT            (0U)
72477 /*! INT0 - SmartDMA hijack NVIC IRQ1
72478  *  0b0..Disable
72479  *  0b1..Enable
72480  */
72481 #define SYSCON_SMARTDMAINT_INT0(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT0_SHIFT)) & SYSCON_SMARTDMAINT_INT0_MASK)
72482 
72483 #define SYSCON_SMARTDMAINT_INT1_MASK             (0x2U)
72484 #define SYSCON_SMARTDMAINT_INT1_SHIFT            (1U)
72485 /*! INT1 - SmartDMA hijack NVIC IRQ17
72486  *  0b0..Disable
72487  *  0b1..Enable
72488  */
72489 #define SYSCON_SMARTDMAINT_INT1(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT1_SHIFT)) & SYSCON_SMARTDMAINT_INT1_MASK)
72490 
72491 #define SYSCON_SMARTDMAINT_INT2_MASK             (0x4U)
72492 #define SYSCON_SMARTDMAINT_INT2_SHIFT            (2U)
72493 /*! INT2 - SmartDMA hijack NVIC IRQ18
72494  *  0b0..Disable
72495  *  0b1..Enable
72496  */
72497 #define SYSCON_SMARTDMAINT_INT2(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT2_SHIFT)) & SYSCON_SMARTDMAINT_INT2_MASK)
72498 
72499 #define SYSCON_SMARTDMAINT_INT3_MASK             (0x8U)
72500 #define SYSCON_SMARTDMAINT_INT3_SHIFT            (3U)
72501 /*! INT3 - SmartDMA hijack NVIC IRQ29
72502  *  0b0..Disable
72503  *  0b1..Enable
72504  */
72505 #define SYSCON_SMARTDMAINT_INT3(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT3_SHIFT)) & SYSCON_SMARTDMAINT_INT3_MASK)
72506 
72507 #define SYSCON_SMARTDMAINT_INT4_MASK             (0x10U)
72508 #define SYSCON_SMARTDMAINT_INT4_SHIFT            (4U)
72509 /*! INT4 - SmartDMA hijack NVIC IRQ30
72510  *  0b0..Disable
72511  *  0b1..Enable
72512  */
72513 #define SYSCON_SMARTDMAINT_INT4(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT4_SHIFT)) & SYSCON_SMARTDMAINT_INT4_MASK)
72514 
72515 #define SYSCON_SMARTDMAINT_INT5_MASK             (0x20U)
72516 #define SYSCON_SMARTDMAINT_INT5_SHIFT            (5U)
72517 /*! INT5 - SmartDMA hijack NVIC IRQ31
72518  *  0b0..Disable
72519  *  0b1..Enable
72520  */
72521 #define SYSCON_SMARTDMAINT_INT5(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT5_SHIFT)) & SYSCON_SMARTDMAINT_INT5_MASK)
72522 
72523 #define SYSCON_SMARTDMAINT_INT6_MASK             (0x40U)
72524 #define SYSCON_SMARTDMAINT_INT6_SHIFT            (6U)
72525 /*! INT6 - SmartDMA hijack NVIC IRQ32
72526  *  0b0..Disable
72527  *  0b1..Enable
72528  */
72529 #define SYSCON_SMARTDMAINT_INT6(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT6_SHIFT)) & SYSCON_SMARTDMAINT_INT6_MASK)
72530 
72531 #define SYSCON_SMARTDMAINT_INT7_MASK             (0x80U)
72532 #define SYSCON_SMARTDMAINT_INT7_SHIFT            (7U)
72533 /*! INT7 - SmartDMA hijack NVIC IRQ33
72534  *  0b0..Disable
72535  *  0b1..Enable
72536  */
72537 #define SYSCON_SMARTDMAINT_INT7(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT7_SHIFT)) & SYSCON_SMARTDMAINT_INT7_MASK)
72538 
72539 #define SYSCON_SMARTDMAINT_INT8_MASK             (0x100U)
72540 #define SYSCON_SMARTDMAINT_INT8_SHIFT            (8U)
72541 /*! INT8 - SmartDMA hijack NVIC IRQ34
72542  *  0b0..Disable
72543  *  0b1..Enable
72544  */
72545 #define SYSCON_SMARTDMAINT_INT8(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT8_SHIFT)) & SYSCON_SMARTDMAINT_INT8_MASK)
72546 
72547 #define SYSCON_SMARTDMAINT_INT9_MASK             (0x200U)
72548 #define SYSCON_SMARTDMAINT_INT9_SHIFT            (9U)
72549 /*! INT9 - SmartDMA hijack NVIC IRQ35
72550  *  0b0..Disable
72551  *  0b1..Enable
72552  */
72553 #define SYSCON_SMARTDMAINT_INT9(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT9_SHIFT)) & SYSCON_SMARTDMAINT_INT9_MASK)
72554 
72555 #define SYSCON_SMARTDMAINT_INT10_MASK            (0x400U)
72556 #define SYSCON_SMARTDMAINT_INT10_SHIFT           (10U)
72557 /*! INT10 - SmartDMA hijack NVIC IRQ36
72558  *  0b0..Disable
72559  *  0b1..Enable
72560  */
72561 #define SYSCON_SMARTDMAINT_INT10(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT10_SHIFT)) & SYSCON_SMARTDMAINT_INT10_MASK)
72562 
72563 #define SYSCON_SMARTDMAINT_INT11_MASK            (0x800U)
72564 #define SYSCON_SMARTDMAINT_INT11_SHIFT           (11U)
72565 /*! INT11 - SmartDMA hijack NVIC IRQ37
72566  *  0b0..Disable
72567  *  0b1..Enable
72568  */
72569 #define SYSCON_SMARTDMAINT_INT11(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT11_SHIFT)) & SYSCON_SMARTDMAINT_INT11_MASK)
72570 
72571 #define SYSCON_SMARTDMAINT_INT12_MASK            (0x1000U)
72572 #define SYSCON_SMARTDMAINT_INT12_SHIFT           (12U)
72573 /*! INT12 - SmartDMA hijack NVIC IRQ38
72574  *  0b0..Disable
72575  *  0b1..Enable
72576  */
72577 #define SYSCON_SMARTDMAINT_INT12(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT12_SHIFT)) & SYSCON_SMARTDMAINT_INT12_MASK)
72578 
72579 #define SYSCON_SMARTDMAINT_INT13_MASK            (0x2000U)
72580 #define SYSCON_SMARTDMAINT_INT13_SHIFT           (13U)
72581 /*! INT13 - SmartDMA hijack NVIC IRQ39
72582  *  0b0..Disable
72583  *  0b1..Enable
72584  */
72585 #define SYSCON_SMARTDMAINT_INT13(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT13_SHIFT)) & SYSCON_SMARTDMAINT_INT13_MASK)
72586 
72587 #define SYSCON_SMARTDMAINT_INT14_MASK            (0x4000U)
72588 #define SYSCON_SMARTDMAINT_INT14_SHIFT           (14U)
72589 /*! INT14 - SmartDMA hijack NVIC IRQ40
72590  *  0b0..Disable
72591  *  0b1..Enable
72592  */
72593 #define SYSCON_SMARTDMAINT_INT14(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT14_SHIFT)) & SYSCON_SMARTDMAINT_INT14_MASK)
72594 
72595 #define SYSCON_SMARTDMAINT_INT15_MASK            (0x8000U)
72596 #define SYSCON_SMARTDMAINT_INT15_SHIFT           (15U)
72597 /*! INT15 - SmartDMA hijack NVIC IRQ41
72598  *  0b0..Disable
72599  *  0b1..Enable
72600  */
72601 #define SYSCON_SMARTDMAINT_INT15(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT15_SHIFT)) & SYSCON_SMARTDMAINT_INT15_MASK)
72602 
72603 #define SYSCON_SMARTDMAINT_INT16_MASK            (0x10000U)
72604 #define SYSCON_SMARTDMAINT_INT16_SHIFT           (16U)
72605 /*! INT16 - SmartDMA hijack NVIC IRQ42
72606  *  0b0..Disable
72607  *  0b1..Enable
72608  */
72609 #define SYSCON_SMARTDMAINT_INT16(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT16_SHIFT)) & SYSCON_SMARTDMAINT_INT16_MASK)
72610 
72611 #define SYSCON_SMARTDMAINT_INT17_MASK            (0x20000U)
72612 #define SYSCON_SMARTDMAINT_INT17_SHIFT           (17U)
72613 /*! INT17 - SmartDMA hijack NVIC IRQ45
72614  *  0b0..Disable
72615  *  0b1..Enable
72616  */
72617 #define SYSCON_SMARTDMAINT_INT17(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT17_SHIFT)) & SYSCON_SMARTDMAINT_INT17_MASK)
72618 
72619 #define SYSCON_SMARTDMAINT_INT18_MASK            (0x40000U)
72620 #define SYSCON_SMARTDMAINT_INT18_SHIFT           (18U)
72621 /*! INT18 - SmartDMA hijack NVIC IRQ47
72622  *  0b0..Disable
72623  *  0b1..Enable
72624  */
72625 #define SYSCON_SMARTDMAINT_INT18(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT18_SHIFT)) & SYSCON_SMARTDMAINT_INT18_MASK)
72626 
72627 #define SYSCON_SMARTDMAINT_INT19_MASK            (0x80000U)
72628 #define SYSCON_SMARTDMAINT_INT19_SHIFT           (19U)
72629 /*! INT19 - SmartDMA hijack NVIC IRQ50
72630  *  0b0..Disable
72631  *  0b1..Enable
72632  */
72633 #define SYSCON_SMARTDMAINT_INT19(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT19_SHIFT)) & SYSCON_SMARTDMAINT_INT19_MASK)
72634 
72635 #define SYSCON_SMARTDMAINT_INT20_MASK            (0x100000U)
72636 #define SYSCON_SMARTDMAINT_INT20_SHIFT           (20U)
72637 /*! INT20 - SmartDMA hijack NVIC IRQ51
72638  *  0b0..Disable
72639  *  0b1..Enable
72640  */
72641 #define SYSCON_SMARTDMAINT_INT20(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT20_SHIFT)) & SYSCON_SMARTDMAINT_INT20_MASK)
72642 
72643 #define SYSCON_SMARTDMAINT_INT21_MASK            (0x200000U)
72644 #define SYSCON_SMARTDMAINT_INT21_SHIFT           (21U)
72645 /*! INT21 - SmartDMA hijack NVIC IRQ66
72646  *  0b0..Disable
72647  *  0b1..Enable
72648  */
72649 #define SYSCON_SMARTDMAINT_INT21(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT21_SHIFT)) & SYSCON_SMARTDMAINT_INT21_MASK)
72650 
72651 #define SYSCON_SMARTDMAINT_INT22_MASK            (0x400000U)
72652 #define SYSCON_SMARTDMAINT_INT22_SHIFT           (22U)
72653 /*! INT22 - SmartDMA hijack NVIC IRQ67
72654  *  0b0..Disable
72655  *  0b1..Enable
72656  */
72657 #define SYSCON_SMARTDMAINT_INT22(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT22_SHIFT)) & SYSCON_SMARTDMAINT_INT22_MASK)
72658 
72659 #define SYSCON_SMARTDMAINT_INT23_MASK            (0x800000U)
72660 #define SYSCON_SMARTDMAINT_INT23_SHIFT           (23U)
72661 /*! INT23 - SmartDMA hijack NVIC IRQ77
72662  *  0b0..Disable
72663  *  0b1..Enable
72664  */
72665 #define SYSCON_SMARTDMAINT_INT23(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT23_SHIFT)) & SYSCON_SMARTDMAINT_INT23_MASK)
72666 /*! @} */
72667 
72668 /*! @name ADC1CLKSEL - ADC1 Clock Source Select */
72669 /*! @{ */
72670 
72671 #define SYSCON_ADC1CLKSEL_SEL_MASK               (0x7U)
72672 #define SYSCON_ADC1CLKSEL_SEL_SHIFT              (0U)
72673 /*! SEL - Selects the ADC1 clock source
72674  *  0b000..No clock
72675  *  0b001..PLL0 clock
72676  *  0b010..FRO_HF clock
72677  *  0b011..FRO 12 MHz clock
72678  *  0b100..Clk_in clock
72679  *  0b101..PLL1_clk0 clock
72680  *  0b110..USB PLL clock
72681  *  0b111..No clock
72682  */
72683 #define SYSCON_ADC1CLKSEL_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_ADC1CLKSEL_SEL_SHIFT)) & SYSCON_ADC1CLKSEL_SEL_MASK)
72684 /*! @} */
72685 
72686 /*! @name ADC1CLKDIV - ADC1 Clock Divider */
72687 /*! @{ */
72688 
72689 #define SYSCON_ADC1CLKDIV_DIV_MASK               (0x7U)
72690 #define SYSCON_ADC1CLKDIV_DIV_SHIFT              (0U)
72691 /*! DIV - Clock divider value */
72692 #define SYSCON_ADC1CLKDIV_DIV(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_ADC1CLKDIV_DIV_SHIFT)) & SYSCON_ADC1CLKDIV_DIV_MASK)
72693 
72694 #define SYSCON_ADC1CLKDIV_RESET_MASK             (0x20000000U)
72695 #define SYSCON_ADC1CLKDIV_RESET_SHIFT            (29U)
72696 /*! RESET - Resets the divider counter
72697  *  0b1..Divider is reset
72698  *  0b0..Divider is not reset
72699  */
72700 #define SYSCON_ADC1CLKDIV_RESET(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_ADC1CLKDIV_RESET_SHIFT)) & SYSCON_ADC1CLKDIV_RESET_MASK)
72701 
72702 #define SYSCON_ADC1CLKDIV_HALT_MASK              (0x40000000U)
72703 #define SYSCON_ADC1CLKDIV_HALT_SHIFT             (30U)
72704 /*! HALT - Halts the divider counter
72705  *  0b1..Divider clock is stopped
72706  *  0b0..Divider clock is running
72707  */
72708 #define SYSCON_ADC1CLKDIV_HALT(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_ADC1CLKDIV_HALT_SHIFT)) & SYSCON_ADC1CLKDIV_HALT_MASK)
72709 
72710 #define SYSCON_ADC1CLKDIV_UNSTAB_MASK            (0x80000000U)
72711 #define SYSCON_ADC1CLKDIV_UNSTAB_SHIFT           (31U)
72712 /*! UNSTAB - Divider status flag
72713  *  0b1..Clock frequency is not stable
72714  *  0b0..Divider clock is stable
72715  */
72716 #define SYSCON_ADC1CLKDIV_UNSTAB(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_ADC1CLKDIV_UNSTAB_SHIFT)) & SYSCON_ADC1CLKDIV_UNSTAB_MASK)
72717 /*! @} */
72718 
72719 /*! @name RAM_INTERLEAVE - Control PKC RAM Interleave Access */
72720 /*! @{ */
72721 
72722 #define SYSCON_RAM_INTERLEAVE_INTERLEAVE_MASK    (0x1U)
72723 #define SYSCON_RAM_INTERLEAVE_INTERLEAVE_SHIFT   (0U)
72724 /*! INTERLEAVE - Controls PKC RAM access for PKC RAM 0 and PKC RAM 1
72725  *  0b1..RAM access to PKC RAM 0 and PKC RAM 1 is interleaved. This setting is need for PKC L0 memory access.
72726  *  0b0..RAM access to PKC RAM 0 and PKC RAM 1 is consecutive.
72727  */
72728 #define SYSCON_RAM_INTERLEAVE_INTERLEAVE(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_RAM_INTERLEAVE_INTERLEAVE_SHIFT)) & SYSCON_RAM_INTERLEAVE_INTERLEAVE_MASK)
72729 /*! @} */
72730 
72731 /*! @name DAC_CLKSEL - DAC0 Functional Clock Selection..DAC2 Functional Clock Selection */
72732 /*! @{ */
72733 
72734 #define SYSCON_DAC_CLKSEL_SEL_MASK               (0x7U)
72735 #define SYSCON_DAC_CLKSEL_SEL_SHIFT              (0U)
72736 /*! SEL - Selects the DAC clock source
72737  *  0b000..No clock
72738  *  0b001..PLL0 clock
72739  *  0b010..Clk_in
72740  *  0b011..FRO_HF
72741  *  0b100..FRO_12M
72742  *  0b101..PLL1_clk0 clock
72743  *  0b110..No clock
72744  *  0b111..No clock
72745  */
72746 #define SYSCON_DAC_CLKSEL_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_DAC_CLKSEL_SEL_SHIFT)) & SYSCON_DAC_CLKSEL_SEL_MASK)
72747 /*! @} */
72748 
72749 /* The count of SYSCON_DAC_CLKSEL */
72750 #define SYSCON_DAC_CLKSEL_COUNT                  (3U)
72751 
72752 /*! @name DAC_CLKDIV - DAC0 functional clock divider..DAC2 functional clock divider */
72753 /*! @{ */
72754 
72755 #define SYSCON_DAC_CLKDIV_DIV_MASK               (0x7U)
72756 #define SYSCON_DAC_CLKDIV_DIV_SHIFT              (0U)
72757 /*! DIV - Clock divider value */
72758 #define SYSCON_DAC_CLKDIV_DIV(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_DAC_CLKDIV_DIV_SHIFT)) & SYSCON_DAC_CLKDIV_DIV_MASK)
72759 
72760 #define SYSCON_DAC_CLKDIV_RESET_MASK             (0x20000000U)
72761 #define SYSCON_DAC_CLKDIV_RESET_SHIFT            (29U)
72762 /*! RESET - Resets the divider counter
72763  *  0b1..Divider is reset
72764  *  0b0..Divider is not reset
72765  */
72766 #define SYSCON_DAC_CLKDIV_RESET(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_DAC_CLKDIV_RESET_SHIFT)) & SYSCON_DAC_CLKDIV_RESET_MASK)
72767 
72768 #define SYSCON_DAC_CLKDIV_HALT_MASK              (0x40000000U)
72769 #define SYSCON_DAC_CLKDIV_HALT_SHIFT             (30U)
72770 /*! HALT - Halts the divider counter
72771  *  0b1..Divider clock is stopped
72772  *  0b0..Divider clock is running
72773  */
72774 #define SYSCON_DAC_CLKDIV_HALT(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_DAC_CLKDIV_HALT_SHIFT)) & SYSCON_DAC_CLKDIV_HALT_MASK)
72775 
72776 #define SYSCON_DAC_CLKDIV_UNSTAB_MASK            (0x80000000U)
72777 #define SYSCON_DAC_CLKDIV_UNSTAB_SHIFT           (31U)
72778 /*! UNSTAB - Divider status flag
72779  *  0b1..Clock frequency is not stable
72780  *  0b0..Divider clock is stable
72781  */
72782 #define SYSCON_DAC_CLKDIV_UNSTAB(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_DAC_CLKDIV_UNSTAB_SHIFT)) & SYSCON_DAC_CLKDIV_UNSTAB_MASK)
72783 /*! @} */
72784 
72785 /* The count of SYSCON_DAC_CLKDIV */
72786 #define SYSCON_DAC_CLKDIV_COUNT                  (3U)
72787 
72788 /*! @name FLEXSPICLKSEL - FlexSPI Clock Selection */
72789 /*! @{ */
72790 
72791 #define SYSCON_FLEXSPICLKSEL_SEL_MASK            (0xFU)
72792 #define SYSCON_FLEXSPICLKSEL_SEL_SHIFT           (0U)
72793 /*! SEL - Selects the FlexSPI clock
72794  *  0b0000..No clock
72795  *  0b0001..PLL0 clock
72796  *  0b0010..No clock
72797  *  0b0011..FRO_HF
72798  *  0b0100..No clock
72799  *  0b0101..pll1_clock
72800  *  0b0110..USB PLL clock
72801  *  0b0111..No clock
72802  *  0b1000..No clock
72803  *  0b1001..No clock
72804  *  0b1010..No clock
72805  *  0b1011..No clock
72806  *  0b1100..No clock
72807  *  0b1101..No clock
72808  *  0b1110..No clock
72809  *  0b1111..No clock
72810  */
72811 #define SYSCON_FLEXSPICLKSEL_SEL(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXSPICLKSEL_SEL_SHIFT)) & SYSCON_FLEXSPICLKSEL_SEL_MASK)
72812 /*! @} */
72813 
72814 /*! @name FLEXSPICLKDIV - FlexSPI Clock Divider */
72815 /*! @{ */
72816 
72817 #define SYSCON_FLEXSPICLKDIV_DIV_MASK            (0x7U)
72818 #define SYSCON_FLEXSPICLKDIV_DIV_SHIFT           (0U)
72819 /*! DIV - Clock divider value */
72820 #define SYSCON_FLEXSPICLKDIV_DIV(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXSPICLKDIV_DIV_SHIFT)) & SYSCON_FLEXSPICLKDIV_DIV_MASK)
72821 
72822 #define SYSCON_FLEXSPICLKDIV_RESET_MASK          (0x20000000U)
72823 #define SYSCON_FLEXSPICLKDIV_RESET_SHIFT         (29U)
72824 /*! RESET - Resets the divider counter
72825  *  0b1..Divider is reset
72826  *  0b0..Divider is not reset
72827  */
72828 #define SYSCON_FLEXSPICLKDIV_RESET(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXSPICLKDIV_RESET_SHIFT)) & SYSCON_FLEXSPICLKDIV_RESET_MASK)
72829 
72830 #define SYSCON_FLEXSPICLKDIV_HALT_MASK           (0x40000000U)
72831 #define SYSCON_FLEXSPICLKDIV_HALT_SHIFT          (30U)
72832 /*! HALT - Halts the divider counter
72833  *  0b1..Divider clock is stopped
72834  *  0b0..Divider clock is running
72835  */
72836 #define SYSCON_FLEXSPICLKDIV_HALT(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXSPICLKDIV_HALT_SHIFT)) & SYSCON_FLEXSPICLKDIV_HALT_MASK)
72837 
72838 #define SYSCON_FLEXSPICLKDIV_UNSTAB_MASK         (0x80000000U)
72839 #define SYSCON_FLEXSPICLKDIV_UNSTAB_SHIFT        (31U)
72840 /*! UNSTAB - Divider status flag
72841  *  0b1..Clock frequency is not stable
72842  *  0b0..Divider clock is stable
72843  */
72844 #define SYSCON_FLEXSPICLKDIV_UNSTAB(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXSPICLKDIV_UNSTAB_SHIFT)) & SYSCON_FLEXSPICLKDIV_UNSTAB_MASK)
72845 /*! @} */
72846 
72847 /*! @name PLLCLKDIVSEL - PLL Clock Divider Clock Selection */
72848 /*! @{ */
72849 
72850 #define SYSCON_PLLCLKDIVSEL_SEL_MASK             (0x7U)
72851 #define SYSCON_PLLCLKDIVSEL_SEL_SHIFT            (0U)
72852 /*! SEL - Selects the PLL Clock Divider source clock
72853  *  0b000..PLL0 clock
72854  *  0b001..pll1_clk0
72855  *  0b010..No clock
72856  *  0b011..No clock
72857  *  0b100..No clock
72858  *  0b101..No clock
72859  *  0b110..No clock
72860  *  0b111..No clock
72861  */
72862 #define SYSCON_PLLCLKDIVSEL_SEL(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_PLLCLKDIVSEL_SEL_SHIFT)) & SYSCON_PLLCLKDIVSEL_SEL_MASK)
72863 /*! @} */
72864 
72865 /*! @name I3C0FCLKSEL - I3C0 Functional Clock Selection */
72866 /*! @{ */
72867 
72868 #define SYSCON_I3C0FCLKSEL_SEL_MASK              (0x7U)
72869 #define SYSCON_I3C0FCLKSEL_SEL_SHIFT             (0U)
72870 /*! SEL - Selects the I3C0 clock
72871  *  0b000..No clock
72872  *  0b001..PLL0 clock
72873  *  0b010..CLKIN clock
72874  *  0b011..FRO_HF clock
72875  *  0b100..No clock
72876  *  0b101..PLL1_clk0 clock
72877  *  0b110..USB PLL clock
72878  *  0b111..No clock
72879  */
72880 #define SYSCON_I3C0FCLKSEL_SEL(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C0FCLKSEL_SEL_SHIFT)) & SYSCON_I3C0FCLKSEL_SEL_MASK)
72881 /*! @} */
72882 
72883 /*! @name I3C0FCLKSTCSEL - I3C0 FCLK_STC Clock Selection */
72884 /*! @{ */
72885 
72886 #define SYSCON_I3C0FCLKSTCSEL_SEL_MASK           (0x7U)
72887 #define SYSCON_I3C0FCLKSTCSEL_SEL_SHIFT          (0U)
72888 /*! SEL - Selects the I3C0 Time Control clock
72889  *  0b000..I3C0 functional clock I3C0FCLK
72890  *  0b001..FRO_1M clock
72891  *  0b010..No clock
72892  *  0b011..No clock
72893  *  0b100..No clock
72894  *  0b101..No clock
72895  *  0b110..No clock
72896  *  0b111..No clock
72897  */
72898 #define SYSCON_I3C0FCLKSTCSEL_SEL(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C0FCLKSTCSEL_SEL_SHIFT)) & SYSCON_I3C0FCLKSTCSEL_SEL_MASK)
72899 /*! @} */
72900 
72901 /*! @name I3C0FCLKSTCDIV - I3C0 FCLK_STC Clock Divider */
72902 /*! @{ */
72903 
72904 #define SYSCON_I3C0FCLKSTCDIV_DIV_MASK           (0xFFU)
72905 #define SYSCON_I3C0FCLKSTCDIV_DIV_SHIFT          (0U)
72906 /*! DIV - Clock divider value */
72907 #define SYSCON_I3C0FCLKSTCDIV_DIV(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C0FCLKSTCDIV_DIV_SHIFT)) & SYSCON_I3C0FCLKSTCDIV_DIV_MASK)
72908 
72909 #define SYSCON_I3C0FCLKSTCDIV_RESET_MASK         (0x20000000U)
72910 #define SYSCON_I3C0FCLKSTCDIV_RESET_SHIFT        (29U)
72911 /*! RESET - Resets the divider counter
72912  *  0b1..Divider is reset
72913  *  0b0..Divider is not reset
72914  */
72915 #define SYSCON_I3C0FCLKSTCDIV_RESET(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C0FCLKSTCDIV_RESET_SHIFT)) & SYSCON_I3C0FCLKSTCDIV_RESET_MASK)
72916 
72917 #define SYSCON_I3C0FCLKSTCDIV_HALT_MASK          (0x40000000U)
72918 #define SYSCON_I3C0FCLKSTCDIV_HALT_SHIFT         (30U)
72919 /*! HALT - Halts the divider counter
72920  *  0b1..Divider clock is stopped
72921  *  0b0..Divider clock is running
72922  */
72923 #define SYSCON_I3C0FCLKSTCDIV_HALT(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C0FCLKSTCDIV_HALT_SHIFT)) & SYSCON_I3C0FCLKSTCDIV_HALT_MASK)
72924 
72925 #define SYSCON_I3C0FCLKSTCDIV_UNSTAB_MASK        (0x80000000U)
72926 #define SYSCON_I3C0FCLKSTCDIV_UNSTAB_SHIFT       (31U)
72927 /*! UNSTAB - Divider status flag
72928  *  0b1..Clock frequency is not stable
72929  *  0b0..Divider clock is stable
72930  */
72931 #define SYSCON_I3C0FCLKSTCDIV_UNSTAB(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C0FCLKSTCDIV_UNSTAB_SHIFT)) & SYSCON_I3C0FCLKSTCDIV_UNSTAB_MASK)
72932 /*! @} */
72933 
72934 /*! @name I3C0FCLKSDIV - I3C0 FCLK Slow Clock Divider */
72935 /*! @{ */
72936 
72937 #define SYSCON_I3C0FCLKSDIV_DIV_MASK             (0xFFU)
72938 #define SYSCON_I3C0FCLKSDIV_DIV_SHIFT            (0U)
72939 /*! DIV - Clock divider value */
72940 #define SYSCON_I3C0FCLKSDIV_DIV(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C0FCLKSDIV_DIV_SHIFT)) & SYSCON_I3C0FCLKSDIV_DIV_MASK)
72941 
72942 #define SYSCON_I3C0FCLKSDIV_RESET_MASK           (0x20000000U)
72943 #define SYSCON_I3C0FCLKSDIV_RESET_SHIFT          (29U)
72944 /*! RESET - Resets the divider counter
72945  *  0b1..Divider is reset
72946  *  0b0..Divider is not reset
72947  */
72948 #define SYSCON_I3C0FCLKSDIV_RESET(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C0FCLKSDIV_RESET_SHIFT)) & SYSCON_I3C0FCLKSDIV_RESET_MASK)
72949 
72950 #define SYSCON_I3C0FCLKSDIV_HALT_MASK            (0x40000000U)
72951 #define SYSCON_I3C0FCLKSDIV_HALT_SHIFT           (30U)
72952 /*! HALT - Halts the divider counter
72953  *  0b1..Divider clock is stopped
72954  *  0b0..Divider clock is running
72955  */
72956 #define SYSCON_I3C0FCLKSDIV_HALT(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C0FCLKSDIV_HALT_SHIFT)) & SYSCON_I3C0FCLKSDIV_HALT_MASK)
72957 
72958 #define SYSCON_I3C0FCLKSDIV_UNSTAB_MASK          (0x80000000U)
72959 #define SYSCON_I3C0FCLKSDIV_UNSTAB_SHIFT         (31U)
72960 /*! UNSTAB - Divider status flag
72961  *  0b1..Clock frequency is not stable
72962  *  0b0..Divider clock is stable
72963  */
72964 #define SYSCON_I3C0FCLKSDIV_UNSTAB(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C0FCLKSDIV_UNSTAB_SHIFT)) & SYSCON_I3C0FCLKSDIV_UNSTAB_MASK)
72965 /*! @} */
72966 
72967 /*! @name I3C0FCLKDIV - I3C0 Functional Clock FCLK Divider */
72968 /*! @{ */
72969 
72970 #define SYSCON_I3C0FCLKDIV_DIV_MASK              (0xFFU)
72971 #define SYSCON_I3C0FCLKDIV_DIV_SHIFT             (0U)
72972 /*! DIV - Clock divider value */
72973 #define SYSCON_I3C0FCLKDIV_DIV(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C0FCLKDIV_DIV_SHIFT)) & SYSCON_I3C0FCLKDIV_DIV_MASK)
72974 
72975 #define SYSCON_I3C0FCLKDIV_RESET_MASK            (0x20000000U)
72976 #define SYSCON_I3C0FCLKDIV_RESET_SHIFT           (29U)
72977 /*! RESET - Resets the divider counter
72978  *  0b1..Divider is reset
72979  *  0b0..Divider is not reset
72980  */
72981 #define SYSCON_I3C0FCLKDIV_RESET(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C0FCLKDIV_RESET_SHIFT)) & SYSCON_I3C0FCLKDIV_RESET_MASK)
72982 
72983 #define SYSCON_I3C0FCLKDIV_HALT_MASK             (0x40000000U)
72984 #define SYSCON_I3C0FCLKDIV_HALT_SHIFT            (30U)
72985 /*! HALT - Halts the divider counter
72986  *  0b1..Divider clock is stopped
72987  *  0b0..Divider clock is running
72988  */
72989 #define SYSCON_I3C0FCLKDIV_HALT(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C0FCLKDIV_HALT_SHIFT)) & SYSCON_I3C0FCLKDIV_HALT_MASK)
72990 
72991 #define SYSCON_I3C0FCLKDIV_UNSTAB_MASK           (0x80000000U)
72992 #define SYSCON_I3C0FCLKDIV_UNSTAB_SHIFT          (31U)
72993 /*! UNSTAB - Divider status flag
72994  *  0b1..Clock frequency is not stable
72995  *  0b0..Divider clock is stable
72996  */
72997 #define SYSCON_I3C0FCLKDIV_UNSTAB(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C0FCLKDIV_UNSTAB_SHIFT)) & SYSCON_I3C0FCLKDIV_UNSTAB_MASK)
72998 /*! @} */
72999 
73000 /*! @name I3C0FCLKSSEL - I3C0 FCLK Slow Selection */
73001 /*! @{ */
73002 
73003 #define SYSCON_I3C0FCLKSSEL_SEL_MASK             (0x7U)
73004 #define SYSCON_I3C0FCLKSSEL_SEL_SHIFT            (0U)
73005 /*! SEL - Selects the I3C FCLK Slow clock
73006  *  0b000..FRO_1M clock
73007  *  0b001..No clock
73008  *  0b010..No clock
73009  *  0b011..No clock
73010  *  0b100..No clock
73011  *  0b101..No clock
73012  *  0b110..No clock
73013  *  0b111..No clock
73014  */
73015 #define SYSCON_I3C0FCLKSSEL_SEL(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C0FCLKSSEL_SEL_SHIFT)) & SYSCON_I3C0FCLKSSEL_SEL_MASK)
73016 /*! @} */
73017 
73018 /*! @name MICFILFCLKSEL - MICFIL Clock Selection */
73019 /*! @{ */
73020 
73021 #define SYSCON_MICFILFCLKSEL_SEL_MASK            (0xFU)
73022 #define SYSCON_MICFILFCLKSEL_SEL_SHIFT           (0U)
73023 /*! SEL - Selects the MICFIL clock
73024  *  0b0000..FRO_12M clock
73025  *  0b0001..PLL0 clock
73026  *  0b0010..CLKIN clock
73027  *  0b0011..FRO_HF clock
73028  *  0b0100..PLL1_clk0 clock
73029  *  0b0101..SAI0_MCLK clock
73030  *  0b0110..USB PLL clock
73031  *  0b0111..No clock
73032  *  0b1000..SAI1_MCLK clock
73033  *  0b1001..No clock
73034  *  0b1010..No clock
73035  *  0b1011..No clock
73036  *  0b1100..No clock
73037  *  0b1101..No clock
73038  *  0b1110..No clock
73039  *  0b1111..No clock
73040  */
73041 #define SYSCON_MICFILFCLKSEL_SEL(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_MICFILFCLKSEL_SEL_SHIFT)) & SYSCON_MICFILFCLKSEL_SEL_MASK)
73042 /*! @} */
73043 
73044 /*! @name MICFILFCLKDIV - MICFIL Clock Division */
73045 /*! @{ */
73046 
73047 #define SYSCON_MICFILFCLKDIV_DIV_MASK            (0x7U)
73048 #define SYSCON_MICFILFCLKDIV_DIV_SHIFT           (0U)
73049 /*! DIV - Clock divider value */
73050 #define SYSCON_MICFILFCLKDIV_DIV(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_MICFILFCLKDIV_DIV_SHIFT)) & SYSCON_MICFILFCLKDIV_DIV_MASK)
73051 
73052 #define SYSCON_MICFILFCLKDIV_RESET_MASK          (0x20000000U)
73053 #define SYSCON_MICFILFCLKDIV_RESET_SHIFT         (29U)
73054 /*! RESET - Resets the divider counter
73055  *  0b1..Divider is reset
73056  *  0b0..Divider is not reset
73057  */
73058 #define SYSCON_MICFILFCLKDIV_RESET(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_MICFILFCLKDIV_RESET_SHIFT)) & SYSCON_MICFILFCLKDIV_RESET_MASK)
73059 
73060 #define SYSCON_MICFILFCLKDIV_HALT_MASK           (0x40000000U)
73061 #define SYSCON_MICFILFCLKDIV_HALT_SHIFT          (30U)
73062 /*! HALT - Halts the divider counter
73063  *  0b1..Divider clock is stopped
73064  *  0b0..Divider clock is running
73065  */
73066 #define SYSCON_MICFILFCLKDIV_HALT(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_MICFILFCLKDIV_HALT_SHIFT)) & SYSCON_MICFILFCLKDIV_HALT_MASK)
73067 
73068 #define SYSCON_MICFILFCLKDIV_UNSTAB_MASK         (0x80000000U)
73069 #define SYSCON_MICFILFCLKDIV_UNSTAB_SHIFT        (31U)
73070 /*! UNSTAB - Divider status flag
73071  *  0b1..Clock frequency is not stable
73072  *  0b0..Divider clock is stable
73073  */
73074 #define SYSCON_MICFILFCLKDIV_UNSTAB(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_MICFILFCLKDIV_UNSTAB_SHIFT)) & SYSCON_MICFILFCLKDIV_UNSTAB_MASK)
73075 /*! @} */
73076 
73077 /*! @name USDHCCLKSEL - uSDHC Clock Selection */
73078 /*! @{ */
73079 
73080 #define SYSCON_USDHCCLKSEL_SEL_MASK              (0x7U)
73081 #define SYSCON_USDHCCLKSEL_SEL_SHIFT             (0U)
73082 /*! SEL - Selects the uSDHC clock
73083  *  0b000..No clock
73084  *  0b001..PLL0 clock
73085  *  0b010..CLKIN clock
73086  *  0b011..FRO_HF clock
73087  *  0b100..FRO_12M clock
73088  *  0b101..pll1_clk1 clock
73089  *  0b110..USB PLL clock
73090  *  0b111..No clock
73091  */
73092 #define SYSCON_USDHCCLKSEL_SEL(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_USDHCCLKSEL_SEL_SHIFT)) & SYSCON_USDHCCLKSEL_SEL_MASK)
73093 /*! @} */
73094 
73095 /*! @name USDHCCLKDIV - uSDHC Function Clock Divider */
73096 /*! @{ */
73097 
73098 #define SYSCON_USDHCCLKDIV_DIV_MASK              (0xFFU)
73099 #define SYSCON_USDHCCLKDIV_DIV_SHIFT             (0U)
73100 /*! DIV - Clock divider value */
73101 #define SYSCON_USDHCCLKDIV_DIV(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_USDHCCLKDIV_DIV_SHIFT)) & SYSCON_USDHCCLKDIV_DIV_MASK)
73102 
73103 #define SYSCON_USDHCCLKDIV_RESET_MASK            (0x20000000U)
73104 #define SYSCON_USDHCCLKDIV_RESET_SHIFT           (29U)
73105 /*! RESET - Resets the divider counter
73106  *  0b1..Divider is reset
73107  *  0b0..Divider is not reset
73108  */
73109 #define SYSCON_USDHCCLKDIV_RESET(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_USDHCCLKDIV_RESET_SHIFT)) & SYSCON_USDHCCLKDIV_RESET_MASK)
73110 
73111 #define SYSCON_USDHCCLKDIV_HALT_MASK             (0x40000000U)
73112 #define SYSCON_USDHCCLKDIV_HALT_SHIFT            (30U)
73113 /*! HALT - Halts the divider counter
73114  *  0b1..Divider clock is stopped
73115  *  0b0..Divider clock is running
73116  */
73117 #define SYSCON_USDHCCLKDIV_HALT(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_USDHCCLKDIV_HALT_SHIFT)) & SYSCON_USDHCCLKDIV_HALT_MASK)
73118 
73119 #define SYSCON_USDHCCLKDIV_UNSTAB_MASK           (0x80000000U)
73120 #define SYSCON_USDHCCLKDIV_UNSTAB_SHIFT          (31U)
73121 /*! UNSTAB - Divider status flag
73122  *  0b1..Clock frequency is not stable
73123  *  0b0..Divider clock is stable
73124  */
73125 #define SYSCON_USDHCCLKDIV_UNSTAB(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_USDHCCLKDIV_UNSTAB_SHIFT)) & SYSCON_USDHCCLKDIV_UNSTAB_MASK)
73126 /*! @} */
73127 
73128 /*! @name FLEXIOCLKSEL - FLEXIO Clock Selection */
73129 /*! @{ */
73130 
73131 #define SYSCON_FLEXIOCLKSEL_SEL_MASK             (0x7U)
73132 #define SYSCON_FLEXIOCLKSEL_SEL_SHIFT            (0U)
73133 /*! SEL - Selects the FLEXIO clock
73134  *  0b000..No clock
73135  *  0b001..PLL0 clock
73136  *  0b010..CLKIN clock
73137  *  0b011..FRO_HF clock
73138  *  0b100..FRO_12M clock
73139  *  0b101..PLL1_clk0 clock
73140  *  0b110..USB PLL clock
73141  *  0b111..No clock
73142  */
73143 #define SYSCON_FLEXIOCLKSEL_SEL(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXIOCLKSEL_SEL_SHIFT)) & SYSCON_FLEXIOCLKSEL_SEL_MASK)
73144 /*! @} */
73145 
73146 /*! @name FLEXIOCLKDIV - FLEXIO Function Clock Divider */
73147 /*! @{ */
73148 
73149 #define SYSCON_FLEXIOCLKDIV_DIV_MASK             (0xFFU)
73150 #define SYSCON_FLEXIOCLKDIV_DIV_SHIFT            (0U)
73151 /*! DIV - Clock divider value */
73152 #define SYSCON_FLEXIOCLKDIV_DIV(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXIOCLKDIV_DIV_SHIFT)) & SYSCON_FLEXIOCLKDIV_DIV_MASK)
73153 
73154 #define SYSCON_FLEXIOCLKDIV_RESET_MASK           (0x20000000U)
73155 #define SYSCON_FLEXIOCLKDIV_RESET_SHIFT          (29U)
73156 /*! RESET - Resets the divider counter
73157  *  0b1..Divider is reset
73158  *  0b0..Divider is not reset
73159  */
73160 #define SYSCON_FLEXIOCLKDIV_RESET(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXIOCLKDIV_RESET_SHIFT)) & SYSCON_FLEXIOCLKDIV_RESET_MASK)
73161 
73162 #define SYSCON_FLEXIOCLKDIV_HALT_MASK            (0x40000000U)
73163 #define SYSCON_FLEXIOCLKDIV_HALT_SHIFT           (30U)
73164 /*! HALT - Halts the divider counter
73165  *  0b1..Divider clock is stopped
73166  *  0b0..Divider clock is running
73167  */
73168 #define SYSCON_FLEXIOCLKDIV_HALT(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXIOCLKDIV_HALT_SHIFT)) & SYSCON_FLEXIOCLKDIV_HALT_MASK)
73169 
73170 #define SYSCON_FLEXIOCLKDIV_UNSTAB_MASK          (0x80000000U)
73171 #define SYSCON_FLEXIOCLKDIV_UNSTAB_SHIFT         (31U)
73172 /*! UNSTAB - Divider status flag
73173  *  0b1..Clock frequency is not stable
73174  *  0b0..Divider clock is stable
73175  */
73176 #define SYSCON_FLEXIOCLKDIV_UNSTAB(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXIOCLKDIV_UNSTAB_SHIFT)) & SYSCON_FLEXIOCLKDIV_UNSTAB_MASK)
73177 /*! @} */
73178 
73179 /*! @name FLEXCAN0CLKSEL - FLEXCAN0 Clock Selection */
73180 /*! @{ */
73181 
73182 #define SYSCON_FLEXCAN0CLKSEL_SEL_MASK           (0x7U)
73183 #define SYSCON_FLEXCAN0CLKSEL_SEL_SHIFT          (0U)
73184 /*! SEL - Selects the FLEXCAN0 clock
73185  *  0b000..No clock
73186  *  0b001..PLL0 clock
73187  *  0b010..CLKIN clock
73188  *  0b011..FRO_HF clock
73189  *  0b100..No clock
73190  *  0b101..PLL1_clk0 clock
73191  *  0b110..USB PLL clock
73192  *  0b111..No clock
73193  */
73194 #define SYSCON_FLEXCAN0CLKSEL_SEL(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXCAN0CLKSEL_SEL_SHIFT)) & SYSCON_FLEXCAN0CLKSEL_SEL_MASK)
73195 /*! @} */
73196 
73197 /*! @name FLEXCAN0CLKDIV - FLEXCAN0 Function Clock Divider */
73198 /*! @{ */
73199 
73200 #define SYSCON_FLEXCAN0CLKDIV_DIV_MASK           (0xFFU)
73201 #define SYSCON_FLEXCAN0CLKDIV_DIV_SHIFT          (0U)
73202 /*! DIV - Clock divider value */
73203 #define SYSCON_FLEXCAN0CLKDIV_DIV(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXCAN0CLKDIV_DIV_SHIFT)) & SYSCON_FLEXCAN0CLKDIV_DIV_MASK)
73204 
73205 #define SYSCON_FLEXCAN0CLKDIV_RESET_MASK         (0x20000000U)
73206 #define SYSCON_FLEXCAN0CLKDIV_RESET_SHIFT        (29U)
73207 /*! RESET - Resets the divider counter
73208  *  0b1..Divider is reset
73209  *  0b0..Divider is not reset
73210  */
73211 #define SYSCON_FLEXCAN0CLKDIV_RESET(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXCAN0CLKDIV_RESET_SHIFT)) & SYSCON_FLEXCAN0CLKDIV_RESET_MASK)
73212 
73213 #define SYSCON_FLEXCAN0CLKDIV_HALT_MASK          (0x40000000U)
73214 #define SYSCON_FLEXCAN0CLKDIV_HALT_SHIFT         (30U)
73215 /*! HALT - Halts the divider counter
73216  *  0b1..Divider clock is stopped
73217  *  0b0..Divider clock is running
73218  */
73219 #define SYSCON_FLEXCAN0CLKDIV_HALT(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXCAN0CLKDIV_HALT_SHIFT)) & SYSCON_FLEXCAN0CLKDIV_HALT_MASK)
73220 
73221 #define SYSCON_FLEXCAN0CLKDIV_UNSTAB_MASK        (0x80000000U)
73222 #define SYSCON_FLEXCAN0CLKDIV_UNSTAB_SHIFT       (31U)
73223 /*! UNSTAB - Divider status flag
73224  *  0b1..Clock frequency is not stable
73225  *  0b0..Divider clock is stable
73226  */
73227 #define SYSCON_FLEXCAN0CLKDIV_UNSTAB(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXCAN0CLKDIV_UNSTAB_SHIFT)) & SYSCON_FLEXCAN0CLKDIV_UNSTAB_MASK)
73228 /*! @} */
73229 
73230 /*! @name FLEXCAN1CLKSEL - FLEXCAN1 Clock Selection */
73231 /*! @{ */
73232 
73233 #define SYSCON_FLEXCAN1CLKSEL_SEL_MASK           (0x7U)
73234 #define SYSCON_FLEXCAN1CLKSEL_SEL_SHIFT          (0U)
73235 /*! SEL - Selects the FLEXCAN1 clock
73236  *  0b000..No clock
73237  *  0b001..PLL0 clock
73238  *  0b010..CLKIN clock
73239  *  0b011..FRO_HF clock
73240  *  0b100..No clock
73241  *  0b101..PLL1_clk0 clock
73242  *  0b110..USB PLL clock
73243  *  0b111..No clock
73244  */
73245 #define SYSCON_FLEXCAN1CLKSEL_SEL(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXCAN1CLKSEL_SEL_SHIFT)) & SYSCON_FLEXCAN1CLKSEL_SEL_MASK)
73246 /*! @} */
73247 
73248 /*! @name FLEXCAN1CLKDIV - FLEXCAN1 Function Clock Divider */
73249 /*! @{ */
73250 
73251 #define SYSCON_FLEXCAN1CLKDIV_DIV_MASK           (0xFFU)
73252 #define SYSCON_FLEXCAN1CLKDIV_DIV_SHIFT          (0U)
73253 /*! DIV - Clock divider value */
73254 #define SYSCON_FLEXCAN1CLKDIV_DIV(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXCAN1CLKDIV_DIV_SHIFT)) & SYSCON_FLEXCAN1CLKDIV_DIV_MASK)
73255 
73256 #define SYSCON_FLEXCAN1CLKDIV_RESET_MASK         (0x20000000U)
73257 #define SYSCON_FLEXCAN1CLKDIV_RESET_SHIFT        (29U)
73258 /*! RESET - Resets the divider counter
73259  *  0b1..Divider is reset
73260  *  0b0..Divider is not reset
73261  */
73262 #define SYSCON_FLEXCAN1CLKDIV_RESET(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXCAN1CLKDIV_RESET_SHIFT)) & SYSCON_FLEXCAN1CLKDIV_RESET_MASK)
73263 
73264 #define SYSCON_FLEXCAN1CLKDIV_HALT_MASK          (0x40000000U)
73265 #define SYSCON_FLEXCAN1CLKDIV_HALT_SHIFT         (30U)
73266 /*! HALT - Halts the divider counter
73267  *  0b1..Divider clock is stopped
73268  *  0b0..Divider clock is running
73269  */
73270 #define SYSCON_FLEXCAN1CLKDIV_HALT(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXCAN1CLKDIV_HALT_SHIFT)) & SYSCON_FLEXCAN1CLKDIV_HALT_MASK)
73271 
73272 #define SYSCON_FLEXCAN1CLKDIV_UNSTAB_MASK        (0x80000000U)
73273 #define SYSCON_FLEXCAN1CLKDIV_UNSTAB_SHIFT       (31U)
73274 /*! UNSTAB - Divider status flag
73275  *  0b1..Clock frequency is not stable
73276  *  0b0..Divider clock is stable
73277  */
73278 #define SYSCON_FLEXCAN1CLKDIV_UNSTAB(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXCAN1CLKDIV_UNSTAB_SHIFT)) & SYSCON_FLEXCAN1CLKDIV_UNSTAB_MASK)
73279 /*! @} */
73280 
73281 /*! @name ENETRMIICLKSEL - Ethernet RMII Clock Selection */
73282 /*! @{ */
73283 
73284 #define SYSCON_ENETRMIICLKSEL_SEL_MASK           (0x7U)
73285 #define SYSCON_ENETRMIICLKSEL_SEL_SHIFT          (0U)
73286 /*! SEL - Selects the Ethernet RMII clock
73287  *  0b000..No clock
73288  *  0b001..PLL0 clock
73289  *  0b010..CLKIN clock
73290  *  0b011..No clock
73291  *  0b100..No clock
73292  *  0b101..PLL1_clk0 clock
73293  *  0b110..No clock
73294  *  0b111..No clock
73295  */
73296 #define SYSCON_ENETRMIICLKSEL_SEL(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_ENETRMIICLKSEL_SEL_SHIFT)) & SYSCON_ENETRMIICLKSEL_SEL_MASK)
73297 /*! @} */
73298 
73299 /*! @name ENETRMIICLKDIV - Ethernet RMII Function Clock Divider */
73300 /*! @{ */
73301 
73302 #define SYSCON_ENETRMIICLKDIV_DIV_MASK           (0xFFU)
73303 #define SYSCON_ENETRMIICLKDIV_DIV_SHIFT          (0U)
73304 /*! DIV - Clock divider value */
73305 #define SYSCON_ENETRMIICLKDIV_DIV(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_ENETRMIICLKDIV_DIV_SHIFT)) & SYSCON_ENETRMIICLKDIV_DIV_MASK)
73306 
73307 #define SYSCON_ENETRMIICLKDIV_RESET_MASK         (0x20000000U)
73308 #define SYSCON_ENETRMIICLKDIV_RESET_SHIFT        (29U)
73309 /*! RESET - Resets the divider counter
73310  *  0b1..Divider is reset
73311  *  0b0..Divider is not reset
73312  */
73313 #define SYSCON_ENETRMIICLKDIV_RESET(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_ENETRMIICLKDIV_RESET_SHIFT)) & SYSCON_ENETRMIICLKDIV_RESET_MASK)
73314 
73315 #define SYSCON_ENETRMIICLKDIV_HALT_MASK          (0x40000000U)
73316 #define SYSCON_ENETRMIICLKDIV_HALT_SHIFT         (30U)
73317 /*! HALT - Halts the divider counter
73318  *  0b1..Divider clock is stopped
73319  *  0b0..Divider clock is running
73320  */
73321 #define SYSCON_ENETRMIICLKDIV_HALT(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_ENETRMIICLKDIV_HALT_SHIFT)) & SYSCON_ENETRMIICLKDIV_HALT_MASK)
73322 
73323 #define SYSCON_ENETRMIICLKDIV_UNSTAB_MASK        (0x80000000U)
73324 #define SYSCON_ENETRMIICLKDIV_UNSTAB_SHIFT       (31U)
73325 /*! UNSTAB - Divider status flag
73326  *  0b1..Clock frequency is not stable
73327  *  0b0..Divider clock is stable
73328  */
73329 #define SYSCON_ENETRMIICLKDIV_UNSTAB(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_ENETRMIICLKDIV_UNSTAB_SHIFT)) & SYSCON_ENETRMIICLKDIV_UNSTAB_MASK)
73330 /*! @} */
73331 
73332 /*! @name ENETPTPREFCLKSEL - Ethernet PTP REF Clock Selection */
73333 /*! @{ */
73334 
73335 #define SYSCON_ENETPTPREFCLKSEL_SEL_MASK         (0x7U)
73336 #define SYSCON_ENETPTPREFCLKSEL_SEL_SHIFT        (0U)
73337 /*! SEL - Selects the Ethernet PTP REF clock
73338  *  0b000..No clock
73339  *  0b001..PLL0 clock
73340  *  0b010..CLKIN clock
73341  *  0b011..No clock
73342  *  0b100..enet0_tx_clk clock
73343  *  0b101..pll1_clk1 clock
73344  *  0b110..No clock
73345  *  0b111..No clock
73346  */
73347 #define SYSCON_ENETPTPREFCLKSEL_SEL(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_ENETPTPREFCLKSEL_SEL_SHIFT)) & SYSCON_ENETPTPREFCLKSEL_SEL_MASK)
73348 /*! @} */
73349 
73350 /*! @name ENETPTPREFCLKDIV - Ethernet PTP REF Function Clock Divider */
73351 /*! @{ */
73352 
73353 #define SYSCON_ENETPTPREFCLKDIV_DIV_MASK         (0xFFU)
73354 #define SYSCON_ENETPTPREFCLKDIV_DIV_SHIFT        (0U)
73355 /*! DIV - Clock divider value */
73356 #define SYSCON_ENETPTPREFCLKDIV_DIV(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_ENETPTPREFCLKDIV_DIV_SHIFT)) & SYSCON_ENETPTPREFCLKDIV_DIV_MASK)
73357 
73358 #define SYSCON_ENETPTPREFCLKDIV_RESET_MASK       (0x20000000U)
73359 #define SYSCON_ENETPTPREFCLKDIV_RESET_SHIFT      (29U)
73360 /*! RESET - Resets the divider counter
73361  *  0b1..Divider is reset
73362  *  0b0..Divider is not reset
73363  */
73364 #define SYSCON_ENETPTPREFCLKDIV_RESET(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_ENETPTPREFCLKDIV_RESET_SHIFT)) & SYSCON_ENETPTPREFCLKDIV_RESET_MASK)
73365 
73366 #define SYSCON_ENETPTPREFCLKDIV_HALT_MASK        (0x40000000U)
73367 #define SYSCON_ENETPTPREFCLKDIV_HALT_SHIFT       (30U)
73368 /*! HALT - Halts the divider counter
73369  *  0b1..Divider clock is stopped
73370  *  0b0..Divider clock is running
73371  */
73372 #define SYSCON_ENETPTPREFCLKDIV_HALT(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_ENETPTPREFCLKDIV_HALT_SHIFT)) & SYSCON_ENETPTPREFCLKDIV_HALT_MASK)
73373 
73374 #define SYSCON_ENETPTPREFCLKDIV_UNSTAB_MASK      (0x80000000U)
73375 #define SYSCON_ENETPTPREFCLKDIV_UNSTAB_SHIFT     (31U)
73376 /*! UNSTAB - Divider status flag
73377  *  0b1..Clock frequency is not stable
73378  *  0b0..Divider clock is stable
73379  */
73380 #define SYSCON_ENETPTPREFCLKDIV_UNSTAB(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_ENETPTPREFCLKDIV_UNSTAB_SHIFT)) & SYSCON_ENETPTPREFCLKDIV_UNSTAB_MASK)
73381 /*! @} */
73382 
73383 /*! @name ENET_PHY_INTF_SEL - Ethernet PHY Interface Select */
73384 /*! @{ */
73385 
73386 #define SYSCON_ENET_PHY_INTF_SEL_PHY_SEL_MASK    (0x4U)
73387 #define SYSCON_ENET_PHY_INTF_SEL_PHY_SEL_SHIFT   (2U)
73388 /*! PHY_SEL - Selects the PHY interface
73389  *  0b1..Selects RMII PHY Interface
73390  *  0b0..Selects MII PHY Interface
73391  */
73392 #define SYSCON_ENET_PHY_INTF_SEL_PHY_SEL(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_ENET_PHY_INTF_SEL_PHY_SEL_SHIFT)) & SYSCON_ENET_PHY_INTF_SEL_PHY_SEL_MASK)
73393 /*! @} */
73394 
73395 /*! @name ENET_SBD_FLOW_CTRL - Sideband Flow Control */
73396 /*! @{ */
73397 
73398 #define SYSCON_ENET_SBD_FLOW_CTRL_SEL_ch0_MASK   (0x1U)
73399 #define SYSCON_ENET_SBD_FLOW_CTRL_SEL_ch0_SHIFT  (0U)
73400 /*! SEL_ch0 - Sideband Flow Control for channel0
73401  *  0b1..Trigger flow control
73402  *  0b0..No trigger flow control
73403  */
73404 #define SYSCON_ENET_SBD_FLOW_CTRL_SEL_ch0(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_ENET_SBD_FLOW_CTRL_SEL_ch0_SHIFT)) & SYSCON_ENET_SBD_FLOW_CTRL_SEL_ch0_MASK)
73405 
73406 #define SYSCON_ENET_SBD_FLOW_CTRL_SEL_ch1_MASK   (0x2U)
73407 #define SYSCON_ENET_SBD_FLOW_CTRL_SEL_ch1_SHIFT  (1U)
73408 /*! SEL_ch1 - Sideband Flow Control for channel1
73409  *  0b1..Trigger flow control
73410  *  0b0..No trigger flow control
73411  */
73412 #define SYSCON_ENET_SBD_FLOW_CTRL_SEL_ch1(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_ENET_SBD_FLOW_CTRL_SEL_ch1_SHIFT)) & SYSCON_ENET_SBD_FLOW_CTRL_SEL_ch1_MASK)
73413 /*! @} */
73414 
73415 /*! @name EWM0CLKSEL - EWM0 Clock Selection */
73416 /*! @{ */
73417 
73418 #define SYSCON_EWM0CLKSEL_SEL_MASK               (0x1U)
73419 #define SYSCON_EWM0CLKSEL_SEL_SHIFT              (0U)
73420 /*! SEL - Selects the EWM0 clock
73421  *  0b0..clk_16k[2]
73422  *  0b1..xtal32k[2]
73423  */
73424 #define SYSCON_EWM0CLKSEL_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_EWM0CLKSEL_SEL_SHIFT)) & SYSCON_EWM0CLKSEL_SEL_MASK)
73425 /*! @} */
73426 
73427 /*! @name WDT1CLKSEL - WDT1 Clock Selection */
73428 /*! @{ */
73429 
73430 #define SYSCON_WDT1CLKSEL_SEL_MASK               (0x3U)
73431 #define SYSCON_WDT1CLKSEL_SEL_SHIFT              (0U)
73432 /*! SEL - Selects the WDT1 clock
73433  *  0b00..FRO16K clock 2
73434  *  0b01..fro_hf_div clock
73435  *  0b10..clk_1m clock
73436  *  0b11..clk_1m clock
73437  */
73438 #define SYSCON_WDT1CLKSEL_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_WDT1CLKSEL_SEL_SHIFT)) & SYSCON_WDT1CLKSEL_SEL_MASK)
73439 /*! @} */
73440 
73441 /*! @name WDT1CLKDIV - WDT1 Function Clock Divider */
73442 /*! @{ */
73443 
73444 #define SYSCON_WDT1CLKDIV_DIV_MASK               (0x3FU)
73445 #define SYSCON_WDT1CLKDIV_DIV_SHIFT              (0U)
73446 /*! DIV - Clock divider value */
73447 #define SYSCON_WDT1CLKDIV_DIV(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_WDT1CLKDIV_DIV_SHIFT)) & SYSCON_WDT1CLKDIV_DIV_MASK)
73448 
73449 #define SYSCON_WDT1CLKDIV_RESET_MASK             (0x20000000U)
73450 #define SYSCON_WDT1CLKDIV_RESET_SHIFT            (29U)
73451 /*! RESET - Resets the divider counter
73452  *  0b1..Divider is reset
73453  *  0b0..Divider is not reset
73454  */
73455 #define SYSCON_WDT1CLKDIV_RESET(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_WDT1CLKDIV_RESET_SHIFT)) & SYSCON_WDT1CLKDIV_RESET_MASK)
73456 
73457 #define SYSCON_WDT1CLKDIV_HALT_MASK              (0x40000000U)
73458 #define SYSCON_WDT1CLKDIV_HALT_SHIFT             (30U)
73459 /*! HALT - Halts the divider counter
73460  *  0b1..Divider clock is stopped
73461  *  0b0..Divider clock is running
73462  */
73463 #define SYSCON_WDT1CLKDIV_HALT(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_WDT1CLKDIV_HALT_SHIFT)) & SYSCON_WDT1CLKDIV_HALT_MASK)
73464 
73465 #define SYSCON_WDT1CLKDIV_UNSTAB_MASK            (0x80000000U)
73466 #define SYSCON_WDT1CLKDIV_UNSTAB_SHIFT           (31U)
73467 /*! UNSTAB - Divider status flag
73468  *  0b1..Clock frequency is not stable
73469  *  0b0..Divider clock is stable
73470  */
73471 #define SYSCON_WDT1CLKDIV_UNSTAB(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_WDT1CLKDIV_UNSTAB_SHIFT)) & SYSCON_WDT1CLKDIV_UNSTAB_MASK)
73472 /*! @} */
73473 
73474 /*! @name OSTIMERCLKSEL - OSTIMER Clock Selection */
73475 /*! @{ */
73476 
73477 #define SYSCON_OSTIMERCLKSEL_SEL_MASK            (0x3U)
73478 #define SYSCON_OSTIMERCLKSEL_SEL_SHIFT           (0U)
73479 /*! SEL - Selects the OS Event Timer clock
73480  *  0b00..clk_16k[2]
73481  *  0b01..xtal32k[2]
73482  *  0b10..clk_1m clock
73483  *  0b11..No clock
73484  */
73485 #define SYSCON_OSTIMERCLKSEL_SEL(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_OSTIMERCLKSEL_SEL_SHIFT)) & SYSCON_OSTIMERCLKSEL_SEL_MASK)
73486 /*! @} */
73487 
73488 /*! @name CMP0FCLKSEL - CMP0 Function Clock Selection */
73489 /*! @{ */
73490 
73491 #define SYSCON_CMP0FCLKSEL_SEL_MASK              (0x7U)
73492 #define SYSCON_CMP0FCLKSEL_SEL_SHIFT             (0U)
73493 /*! SEL - Selects the CMP0 function clock
73494  *  0b000..No clock
73495  *  0b001..PLL0 clock
73496  *  0b010..FRO_HF clock
73497  *  0b011..FRO_12M clock
73498  *  0b100..CLKIN clock
73499  *  0b101..PLL1_clk0 clock
73500  *  0b110..USB PLL clock
73501  *  0b111..No clock
73502  */
73503 #define SYSCON_CMP0FCLKSEL_SEL(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP0FCLKSEL_SEL_SHIFT)) & SYSCON_CMP0FCLKSEL_SEL_MASK)
73504 /*! @} */
73505 
73506 /*! @name CMP0FCLKDIV - CMP0 Function Clock Divider */
73507 /*! @{ */
73508 
73509 #define SYSCON_CMP0FCLKDIV_DIV_MASK              (0xFU)
73510 #define SYSCON_CMP0FCLKDIV_DIV_SHIFT             (0U)
73511 /*! DIV - Clock divider value */
73512 #define SYSCON_CMP0FCLKDIV_DIV(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP0FCLKDIV_DIV_SHIFT)) & SYSCON_CMP0FCLKDIV_DIV_MASK)
73513 
73514 #define SYSCON_CMP0FCLKDIV_RESET_MASK            (0x20000000U)
73515 #define SYSCON_CMP0FCLKDIV_RESET_SHIFT           (29U)
73516 /*! RESET - Resets the divider counter
73517  *  0b1..Divider is reset
73518  *  0b0..Divider is not reset
73519  */
73520 #define SYSCON_CMP0FCLKDIV_RESET(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP0FCLKDIV_RESET_SHIFT)) & SYSCON_CMP0FCLKDIV_RESET_MASK)
73521 
73522 #define SYSCON_CMP0FCLKDIV_HALT_MASK             (0x40000000U)
73523 #define SYSCON_CMP0FCLKDIV_HALT_SHIFT            (30U)
73524 /*! HALT - Halts the divider counter
73525  *  0b1..Divider clock is stopped
73526  *  0b0..Divider clock is running
73527  */
73528 #define SYSCON_CMP0FCLKDIV_HALT(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP0FCLKDIV_HALT_SHIFT)) & SYSCON_CMP0FCLKDIV_HALT_MASK)
73529 
73530 #define SYSCON_CMP0FCLKDIV_UNSTAB_MASK           (0x80000000U)
73531 #define SYSCON_CMP0FCLKDIV_UNSTAB_SHIFT          (31U)
73532 /*! UNSTAB - Divider status flag
73533  *  0b1..Clock frequency is not stable
73534  *  0b0..Divider clock is stable
73535  */
73536 #define SYSCON_CMP0FCLKDIV_UNSTAB(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP0FCLKDIV_UNSTAB_SHIFT)) & SYSCON_CMP0FCLKDIV_UNSTAB_MASK)
73537 /*! @} */
73538 
73539 /*! @name CMP0RRCLKSEL - CMP0 Round Robin Clock Selection */
73540 /*! @{ */
73541 
73542 #define SYSCON_CMP0RRCLKSEL_SEL_MASK             (0x7U)
73543 #define SYSCON_CMP0RRCLKSEL_SEL_SHIFT            (0U)
73544 /*! SEL - Selects the CMP0 round robin clock
73545  *  0b000..No clock
73546  *  0b001..PLL0 clock
73547  *  0b010..FRO_HF clock
73548  *  0b011..FRO_12M clock
73549  *  0b100..CLKIN clock
73550  *  0b101..PLL1_clk0 clock
73551  *  0b110..USB PLL clock
73552  *  0b111..No clock
73553  */
73554 #define SYSCON_CMP0RRCLKSEL_SEL(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP0RRCLKSEL_SEL_SHIFT)) & SYSCON_CMP0RRCLKSEL_SEL_MASK)
73555 /*! @} */
73556 
73557 /*! @name CMP0RRCLKDIV - CMP0 Round Robin Clock Divider */
73558 /*! @{ */
73559 
73560 #define SYSCON_CMP0RRCLKDIV_DIV_MASK             (0xFU)
73561 #define SYSCON_CMP0RRCLKDIV_DIV_SHIFT            (0U)
73562 /*! DIV - Clock divider value */
73563 #define SYSCON_CMP0RRCLKDIV_DIV(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP0RRCLKDIV_DIV_SHIFT)) & SYSCON_CMP0RRCLKDIV_DIV_MASK)
73564 
73565 #define SYSCON_CMP0RRCLKDIV_RESET_MASK           (0x20000000U)
73566 #define SYSCON_CMP0RRCLKDIV_RESET_SHIFT          (29U)
73567 /*! RESET - Resets the divider counter
73568  *  0b1..Divider is reset
73569  *  0b0..Divider is not reset
73570  */
73571 #define SYSCON_CMP0RRCLKDIV_RESET(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP0RRCLKDIV_RESET_SHIFT)) & SYSCON_CMP0RRCLKDIV_RESET_MASK)
73572 
73573 #define SYSCON_CMP0RRCLKDIV_HALT_MASK            (0x40000000U)
73574 #define SYSCON_CMP0RRCLKDIV_HALT_SHIFT           (30U)
73575 /*! HALT - Halts the divider counter
73576  *  0b1..Divider clock is stopped
73577  *  0b0..Divider clock is running
73578  */
73579 #define SYSCON_CMP0RRCLKDIV_HALT(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP0RRCLKDIV_HALT_SHIFT)) & SYSCON_CMP0RRCLKDIV_HALT_MASK)
73580 
73581 #define SYSCON_CMP0RRCLKDIV_UNSTAB_MASK          (0x80000000U)
73582 #define SYSCON_CMP0RRCLKDIV_UNSTAB_SHIFT         (31U)
73583 /*! UNSTAB - Divider status flag
73584  *  0b1..Clock frequency is not stable
73585  *  0b0..Divider clock is stable
73586  */
73587 #define SYSCON_CMP0RRCLKDIV_UNSTAB(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP0RRCLKDIV_UNSTAB_SHIFT)) & SYSCON_CMP0RRCLKDIV_UNSTAB_MASK)
73588 /*! @} */
73589 
73590 /*! @name CMP1FCLKSEL - CMP1 Function Clock Selection */
73591 /*! @{ */
73592 
73593 #define SYSCON_CMP1FCLKSEL_SEL_MASK              (0x7U)
73594 #define SYSCON_CMP1FCLKSEL_SEL_SHIFT             (0U)
73595 /*! SEL - Selects the CMP1 function clock
73596  *  0b000..No clock
73597  *  0b001..PLL0 clock
73598  *  0b010..FRO_HF clock
73599  *  0b011..FRO_12M clock
73600  *  0b100..CLKIN clock
73601  *  0b101..PLL1_clk0 clock
73602  *  0b110..USB PLL clock
73603  *  0b111..No clock
73604  */
73605 #define SYSCON_CMP1FCLKSEL_SEL(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP1FCLKSEL_SEL_SHIFT)) & SYSCON_CMP1FCLKSEL_SEL_MASK)
73606 /*! @} */
73607 
73608 /*! @name CMP1FCLKDIV - CMP1 Function Clock Divider */
73609 /*! @{ */
73610 
73611 #define SYSCON_CMP1FCLKDIV_DIV_MASK              (0xFU)
73612 #define SYSCON_CMP1FCLKDIV_DIV_SHIFT             (0U)
73613 /*! DIV - Clock divider value */
73614 #define SYSCON_CMP1FCLKDIV_DIV(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP1FCLKDIV_DIV_SHIFT)) & SYSCON_CMP1FCLKDIV_DIV_MASK)
73615 
73616 #define SYSCON_CMP1FCLKDIV_RESET_MASK            (0x20000000U)
73617 #define SYSCON_CMP1FCLKDIV_RESET_SHIFT           (29U)
73618 /*! RESET - Resets the divider counter
73619  *  0b1..Divider is reset
73620  *  0b0..Divider is not reset
73621  */
73622 #define SYSCON_CMP1FCLKDIV_RESET(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP1FCLKDIV_RESET_SHIFT)) & SYSCON_CMP1FCLKDIV_RESET_MASK)
73623 
73624 #define SYSCON_CMP1FCLKDIV_HALT_MASK             (0x40000000U)
73625 #define SYSCON_CMP1FCLKDIV_HALT_SHIFT            (30U)
73626 /*! HALT - Halts the divider counter
73627  *  0b1..Divider clock is stopped
73628  *  0b0..Divider clock is running
73629  */
73630 #define SYSCON_CMP1FCLKDIV_HALT(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP1FCLKDIV_HALT_SHIFT)) & SYSCON_CMP1FCLKDIV_HALT_MASK)
73631 
73632 #define SYSCON_CMP1FCLKDIV_UNSTAB_MASK           (0x80000000U)
73633 #define SYSCON_CMP1FCLKDIV_UNSTAB_SHIFT          (31U)
73634 /*! UNSTAB - Divider status flag
73635  *  0b1..Clock frequency is not stable
73636  *  0b0..Divider clock is stable
73637  */
73638 #define SYSCON_CMP1FCLKDIV_UNSTAB(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP1FCLKDIV_UNSTAB_SHIFT)) & SYSCON_CMP1FCLKDIV_UNSTAB_MASK)
73639 /*! @} */
73640 
73641 /*! @name CMP1RRCLKSEL - CMP1 Round Robin Clock Source Select */
73642 /*! @{ */
73643 
73644 #define SYSCON_CMP1RRCLKSEL_SEL_MASK             (0x7U)
73645 #define SYSCON_CMP1RRCLKSEL_SEL_SHIFT            (0U)
73646 /*! SEL - Selects the CMP1 round robin clock
73647  *  0b000..No clock
73648  *  0b001..PLL0 clock
73649  *  0b010..FRO_HF clock
73650  *  0b011..FRO_12M clock
73651  *  0b100..CLKIN clock
73652  *  0b101..PLL1_clk0 clock
73653  *  0b110..USB PLL clock
73654  *  0b111..No clock
73655  */
73656 #define SYSCON_CMP1RRCLKSEL_SEL(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP1RRCLKSEL_SEL_SHIFT)) & SYSCON_CMP1RRCLKSEL_SEL_MASK)
73657 /*! @} */
73658 
73659 /*! @name CMP1RRCLKDIV - CMP1 Round Robin Clock Division */
73660 /*! @{ */
73661 
73662 #define SYSCON_CMP1RRCLKDIV_DIV_MASK             (0xFU)
73663 #define SYSCON_CMP1RRCLKDIV_DIV_SHIFT            (0U)
73664 /*! DIV - Clock divider value */
73665 #define SYSCON_CMP1RRCLKDIV_DIV(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP1RRCLKDIV_DIV_SHIFT)) & SYSCON_CMP1RRCLKDIV_DIV_MASK)
73666 
73667 #define SYSCON_CMP1RRCLKDIV_RESET_MASK           (0x20000000U)
73668 #define SYSCON_CMP1RRCLKDIV_RESET_SHIFT          (29U)
73669 /*! RESET - Resets the divider counter
73670  *  0b1..Divider is reset
73671  *  0b0..Divider is not reset
73672  */
73673 #define SYSCON_CMP1RRCLKDIV_RESET(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP1RRCLKDIV_RESET_SHIFT)) & SYSCON_CMP1RRCLKDIV_RESET_MASK)
73674 
73675 #define SYSCON_CMP1RRCLKDIV_HALT_MASK            (0x40000000U)
73676 #define SYSCON_CMP1RRCLKDIV_HALT_SHIFT           (30U)
73677 /*! HALT - Halts the divider counter
73678  *  0b1..Divider clock is stopped
73679  *  0b0..Divider clock is running
73680  */
73681 #define SYSCON_CMP1RRCLKDIV_HALT(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP1RRCLKDIV_HALT_SHIFT)) & SYSCON_CMP1RRCLKDIV_HALT_MASK)
73682 
73683 #define SYSCON_CMP1RRCLKDIV_UNSTAB_MASK          (0x80000000U)
73684 #define SYSCON_CMP1RRCLKDIV_UNSTAB_SHIFT         (31U)
73685 /*! UNSTAB - Divider status flag
73686  *  0b1..Clock frequency is not stable
73687  *  0b0..Divider clock is stable
73688  */
73689 #define SYSCON_CMP1RRCLKDIV_UNSTAB(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP1RRCLKDIV_UNSTAB_SHIFT)) & SYSCON_CMP1RRCLKDIV_UNSTAB_MASK)
73690 /*! @} */
73691 
73692 /*! @name CMP2FCLKSEL - CMP2 Function Clock Source Select */
73693 /*! @{ */
73694 
73695 #define SYSCON_CMP2FCLKSEL_SEL_MASK              (0x7U)
73696 #define SYSCON_CMP2FCLKSEL_SEL_SHIFT             (0U)
73697 /*! SEL - Selects the CMP2 function clock
73698  *  0b000..No clock
73699  *  0b001..PLL0 clock
73700  *  0b010..FRO_HF clock
73701  *  0b011..FRO_12M clock
73702  *  0b100..CLKIN clock
73703  *  0b101..PLL1_clk0 clock
73704  *  0b110..USB PLL clock
73705  *  0b111..No clock
73706  */
73707 #define SYSCON_CMP2FCLKSEL_SEL(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP2FCLKSEL_SEL_SHIFT)) & SYSCON_CMP2FCLKSEL_SEL_MASK)
73708 /*! @} */
73709 
73710 /*! @name CMP2FCLKDIV - CMP2 Function Clock Division */
73711 /*! @{ */
73712 
73713 #define SYSCON_CMP2FCLKDIV_DIV_MASK              (0xFU)
73714 #define SYSCON_CMP2FCLKDIV_DIV_SHIFT             (0U)
73715 /*! DIV - Clock divider value */
73716 #define SYSCON_CMP2FCLKDIV_DIV(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP2FCLKDIV_DIV_SHIFT)) & SYSCON_CMP2FCLKDIV_DIV_MASK)
73717 
73718 #define SYSCON_CMP2FCLKDIV_RESET_MASK            (0x20000000U)
73719 #define SYSCON_CMP2FCLKDIV_RESET_SHIFT           (29U)
73720 /*! RESET - Resets the divider counter
73721  *  0b1..Divider is reset
73722  *  0b0..Divider is not reset
73723  */
73724 #define SYSCON_CMP2FCLKDIV_RESET(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP2FCLKDIV_RESET_SHIFT)) & SYSCON_CMP2FCLKDIV_RESET_MASK)
73725 
73726 #define SYSCON_CMP2FCLKDIV_HALT_MASK             (0x40000000U)
73727 #define SYSCON_CMP2FCLKDIV_HALT_SHIFT            (30U)
73728 /*! HALT - Halts the divider counter
73729  *  0b1..Divider clock is stopped
73730  *  0b0..Divider clock is running
73731  */
73732 #define SYSCON_CMP2FCLKDIV_HALT(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP2FCLKDIV_HALT_SHIFT)) & SYSCON_CMP2FCLKDIV_HALT_MASK)
73733 
73734 #define SYSCON_CMP2FCLKDIV_UNSTAB_MASK           (0x80000000U)
73735 #define SYSCON_CMP2FCLKDIV_UNSTAB_SHIFT          (31U)
73736 /*! UNSTAB - Divider status flag
73737  *  0b1..Clock frequency is not stable
73738  *  0b0..Divider clock is stable
73739  */
73740 #define SYSCON_CMP2FCLKDIV_UNSTAB(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP2FCLKDIV_UNSTAB_SHIFT)) & SYSCON_CMP2FCLKDIV_UNSTAB_MASK)
73741 /*! @} */
73742 
73743 /*! @name CMP2RRCLKSEL - CMP2 Round Robin Clock Source Select */
73744 /*! @{ */
73745 
73746 #define SYSCON_CMP2RRCLKSEL_SEL_MASK             (0x7U)
73747 #define SYSCON_CMP2RRCLKSEL_SEL_SHIFT            (0U)
73748 /*! SEL - Selects the CMP2 round robin clock
73749  *  0b000..No clock
73750  *  0b001..PLL0 clock
73751  *  0b010..FRO_HF clock
73752  *  0b011..FRO_12M clock
73753  *  0b100..CLKIN clock
73754  *  0b101..PLL1_clk0 clock0
73755  *  0b110..USB PLL clock
73756  *  0b111..No clock
73757  */
73758 #define SYSCON_CMP2RRCLKSEL_SEL(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP2RRCLKSEL_SEL_SHIFT)) & SYSCON_CMP2RRCLKSEL_SEL_MASK)
73759 /*! @} */
73760 
73761 /*! @name CMP2RRCLKDIV - CMP2 Round Robin Clock Division */
73762 /*! @{ */
73763 
73764 #define SYSCON_CMP2RRCLKDIV_DIV_MASK             (0xFU)
73765 #define SYSCON_CMP2RRCLKDIV_DIV_SHIFT            (0U)
73766 /*! DIV - Clock divider value */
73767 #define SYSCON_CMP2RRCLKDIV_DIV(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP2RRCLKDIV_DIV_SHIFT)) & SYSCON_CMP2RRCLKDIV_DIV_MASK)
73768 
73769 #define SYSCON_CMP2RRCLKDIV_RESET_MASK           (0x20000000U)
73770 #define SYSCON_CMP2RRCLKDIV_RESET_SHIFT          (29U)
73771 /*! RESET - Resets the divider counter
73772  *  0b1..Divider is reset
73773  *  0b0..Divider is not reset
73774  */
73775 #define SYSCON_CMP2RRCLKDIV_RESET(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP2RRCLKDIV_RESET_SHIFT)) & SYSCON_CMP2RRCLKDIV_RESET_MASK)
73776 
73777 #define SYSCON_CMP2RRCLKDIV_HALT_MASK            (0x40000000U)
73778 #define SYSCON_CMP2RRCLKDIV_HALT_SHIFT           (30U)
73779 /*! HALT - Halts the divider counter
73780  *  0b1..Divider clock is stopped
73781  *  0b0..Divider clock is running
73782  */
73783 #define SYSCON_CMP2RRCLKDIV_HALT(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP2RRCLKDIV_HALT_SHIFT)) & SYSCON_CMP2RRCLKDIV_HALT_MASK)
73784 
73785 #define SYSCON_CMP2RRCLKDIV_UNSTAB_MASK          (0x80000000U)
73786 #define SYSCON_CMP2RRCLKDIV_UNSTAB_SHIFT         (31U)
73787 /*! UNSTAB - Divider status flag
73788  *  0b1..Clock frequency is not stable
73789  *  0b0..Divider clock is stable
73790  */
73791 #define SYSCON_CMP2RRCLKDIV_UNSTAB(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP2RRCLKDIV_UNSTAB_SHIFT)) & SYSCON_CMP2RRCLKDIV_UNSTAB_MASK)
73792 /*! @} */
73793 
73794 /*! @name CPUCTRL - CPU Control for Multiple Processors */
73795 /*! @{ */
73796 
73797 #define SYSCON_CPUCTRL_CPU1CLKEN_MASK            (0x8U)
73798 #define SYSCON_CPUCTRL_CPU1CLKEN_SHIFT           (3U)
73799 /*! CPU1CLKEN - Enables the CPU1 clock
73800  *  0b1..The CPU1 clock is enabled
73801  *  0b0..The CPU1 clock is not enabled
73802  */
73803 #define SYSCON_CPUCTRL_CPU1CLKEN(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_CPU1CLKEN_SHIFT)) & SYSCON_CPUCTRL_CPU1CLKEN_MASK)
73804 
73805 #define SYSCON_CPUCTRL_CPU1RSTEN_MASK            (0x20U)
73806 #define SYSCON_CPUCTRL_CPU1RSTEN_SHIFT           (5U)
73807 /*! CPU1RSTEN - CPU1 reset
73808  *  0b1..The CPU1 is reset.
73809  *  0b0..The CPU1 is not reset.
73810  */
73811 #define SYSCON_CPUCTRL_CPU1RSTEN(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_CPU1RSTEN_SHIFT)) & SYSCON_CPUCTRL_CPU1RSTEN_MASK)
73812 
73813 #define SYSCON_CPUCTRL_PROT_MASK                 (0xFFFF0000U)
73814 #define SYSCON_CPUCTRL_PROT_SHIFT                (16U)
73815 /*! PROT - Write Protect
73816  *  0b1100000011000100..For write operation to have an effect.
73817  */
73818 #define SYSCON_CPUCTRL_PROT(x)                   (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_PROT_SHIFT)) & SYSCON_CPUCTRL_PROT_MASK)
73819 /*! @} */
73820 
73821 /*! @name CPBOOT - Coprocessor Boot Address */
73822 /*! @{ */
73823 
73824 #define SYSCON_CPBOOT_CPBOOT_MASK                (0xFFFFFF80U)
73825 #define SYSCON_CPBOOT_CPBOOT_SHIFT               (7U)
73826 /*! CPBOOT - Coprocessor Boot VTOR Address [31:7] for CPU1 */
73827 #define SYSCON_CPBOOT_CPBOOT(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_CPBOOT_CPBOOT_SHIFT)) & SYSCON_CPBOOT_CPBOOT_MASK)
73828 /*! @} */
73829 
73830 /*! @name CPUSTAT - CPU Status */
73831 /*! @{ */
73832 
73833 #define SYSCON_CPUSTAT_CPU0SLEEPING_MASK         (0x1U)
73834 #define SYSCON_CPUSTAT_CPU0SLEEPING_SHIFT        (0U)
73835 /*! CPU0SLEEPING - CPU0 sleeping state
73836  *  0b1..CPU is sleeping
73837  *  0b0..CPU is not sleeping
73838  */
73839 #define SYSCON_CPUSTAT_CPU0SLEEPING(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUSTAT_CPU0SLEEPING_SHIFT)) & SYSCON_CPUSTAT_CPU0SLEEPING_MASK)
73840 
73841 #define SYSCON_CPUSTAT_CPU1SLEEPING_MASK         (0x2U)
73842 #define SYSCON_CPUSTAT_CPU1SLEEPING_SHIFT        (1U)
73843 /*! CPU1SLEEPING - CPU1 sleeping state
73844  *  0b1..CPU is sleeping
73845  *  0b0..CPU is not sleeping
73846  */
73847 #define SYSCON_CPUSTAT_CPU1SLEEPING(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUSTAT_CPU1SLEEPING_SHIFT)) & SYSCON_CPUSTAT_CPU1SLEEPING_MASK)
73848 
73849 #define SYSCON_CPUSTAT_CPU0LOCKUP_MASK           (0x4U)
73850 #define SYSCON_CPUSTAT_CPU0LOCKUP_SHIFT          (2U)
73851 /*! CPU0LOCKUP - CPU0 lockup state
73852  *  0b1..CPU is in lockup
73853  *  0b0..CPU is not in lockup
73854  */
73855 #define SYSCON_CPUSTAT_CPU0LOCKUP(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUSTAT_CPU0LOCKUP_SHIFT)) & SYSCON_CPUSTAT_CPU0LOCKUP_MASK)
73856 
73857 #define SYSCON_CPUSTAT_CPU1LOCKUP_MASK           (0x8U)
73858 #define SYSCON_CPUSTAT_CPU1LOCKUP_SHIFT          (3U)
73859 /*! CPU1LOCKUP - CPU1 lockup state
73860  *  0b1..CPU is in lockup
73861  *  0b0..CPU is not in lockup
73862  */
73863 #define SYSCON_CPUSTAT_CPU1LOCKUP(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUSTAT_CPU1LOCKUP_SHIFT)) & SYSCON_CPUSTAT_CPU1LOCKUP_MASK)
73864 /*! @} */
73865 
73866 /*! @name LPCAC_CTRL - LPCAC Control */
73867 /*! @{ */
73868 
73869 #define SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK         (0x1U)
73870 #define SYSCON_LPCAC_CTRL_DIS_LPCAC_SHIFT        (0U)
73871 /*! DIS_LPCAC - Disables/enables the cache function.
73872  *  0b0..Enabled
73873  *  0b1..Disabled
73874  */
73875 #define SYSCON_LPCAC_CTRL_DIS_LPCAC(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_DIS_LPCAC_SHIFT)) & SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK)
73876 
73877 #define SYSCON_LPCAC_CTRL_CLR_LPCAC_MASK         (0x2U)
73878 #define SYSCON_LPCAC_CTRL_CLR_LPCAC_SHIFT        (1U)
73879 /*! CLR_LPCAC - Clears the cache function.
73880  *  0b0..Unclears the cache
73881  *  0b1..Clears the cache
73882  */
73883 #define SYSCON_LPCAC_CTRL_CLR_LPCAC(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_CLR_LPCAC_SHIFT)) & SYSCON_LPCAC_CTRL_CLR_LPCAC_MASK)
73884 
73885 #define SYSCON_LPCAC_CTRL_FRC_NO_ALLOC_MASK      (0x4U)
73886 #define SYSCON_LPCAC_CTRL_FRC_NO_ALLOC_SHIFT     (2U)
73887 /*! FRC_NO_ALLOC - Forces no allocation.
73888  *  0b0..Forces allocation
73889  *  0b1..Forces no allocation
73890  */
73891 #define SYSCON_LPCAC_CTRL_FRC_NO_ALLOC(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_FRC_NO_ALLOC_SHIFT)) & SYSCON_LPCAC_CTRL_FRC_NO_ALLOC_MASK)
73892 
73893 #define SYSCON_LPCAC_CTRL_PARITY_MISS_EN_MASK    (0x8U)
73894 #define SYSCON_LPCAC_CTRL_PARITY_MISS_EN_SHIFT   (3U)
73895 /*! PARITY_MISS_EN - Enables parity miss.
73896  *  0b0..Disabled
73897  *  0b1..Enables parity, miss on parity error
73898  */
73899 #define SYSCON_LPCAC_CTRL_PARITY_MISS_EN(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_PARITY_MISS_EN_SHIFT)) & SYSCON_LPCAC_CTRL_PARITY_MISS_EN_MASK)
73900 
73901 #define SYSCON_LPCAC_CTRL_DIS_LPCAC_WTBF_MASK    (0x10U)
73902 #define SYSCON_LPCAC_CTRL_DIS_LPCAC_WTBF_SHIFT   (4U)
73903 /*! DIS_LPCAC_WTBF - Disable LPCAC Write Through Buffer.
73904  *  0b1..Disables write through buffer
73905  *  0b0..Enables write through buffer
73906  */
73907 #define SYSCON_LPCAC_CTRL_DIS_LPCAC_WTBF(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_DIS_LPCAC_WTBF_SHIFT)) & SYSCON_LPCAC_CTRL_DIS_LPCAC_WTBF_MASK)
73908 
73909 #define SYSCON_LPCAC_CTRL_LIM_LPCAC_WTBF_MASK    (0x20U)
73910 #define SYSCON_LPCAC_CTRL_LIM_LPCAC_WTBF_SHIFT   (5U)
73911 /*! LIM_LPCAC_WTBF - Limit LPCAC Write Through Buffer.
73912  *  0b1..Write buffer enabled when transaction is cacheable and bufferable
73913  *  0b0..Write buffer enabled when transaction is bufferable.
73914  */
73915 #define SYSCON_LPCAC_CTRL_LIM_LPCAC_WTBF(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_LIM_LPCAC_WTBF_SHIFT)) & SYSCON_LPCAC_CTRL_LIM_LPCAC_WTBF_MASK)
73916 
73917 #define SYSCON_LPCAC_CTRL_PARITY_FAULT_EN_MASK   (0x40U)
73918 #define SYSCON_LPCAC_CTRL_PARITY_FAULT_EN_SHIFT  (6U)
73919 /*! PARITY_FAULT_EN - Enable parity error report.
73920  *  0b1..Enables parity error report
73921  *  0b0..Disables parity error report
73922  */
73923 #define SYSCON_LPCAC_CTRL_PARITY_FAULT_EN(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_PARITY_FAULT_EN_SHIFT)) & SYSCON_LPCAC_CTRL_PARITY_FAULT_EN_MASK)
73924 
73925 #define SYSCON_LPCAC_CTRL_LPCAC_XOM_MASK         (0x80U)
73926 #define SYSCON_LPCAC_CTRL_LPCAC_XOM_SHIFT        (7U)
73927 /*! LPCAC_XOM - LPCAC XOM(eXecute-Only-Memory) attribute control
73928  *  0b1..Enabled.
73929  *  0b0..Disabled.
73930  */
73931 #define SYSCON_LPCAC_CTRL_LPCAC_XOM(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_LPCAC_XOM_SHIFT)) & SYSCON_LPCAC_CTRL_LPCAC_XOM_MASK)
73932 /*! @} */
73933 
73934 /*! @name FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV - LP_FLEXCOMM Clock Divider */
73935 /*! @{ */
73936 
73937 #define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_DIV_MASK (0xFFU)
73938 #define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_DIV_SHIFT (0U)
73939 /*! DIV - Clock divider value */
73940 #define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_DIV_SHIFT)) & SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_DIV_MASK)
73941 
73942 #define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_RESET_MASK (0x20000000U)
73943 #define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_RESET_SHIFT (29U)
73944 /*! RESET - Resets the divider counter
73945  *  0b1..Divider is reset
73946  *  0b0..Divider is not reset
73947  */
73948 #define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_RESET_SHIFT)) & SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_RESET_MASK)
73949 
73950 #define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_HALT_MASK (0x40000000U)
73951 #define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_HALT_SHIFT (30U)
73952 /*! HALT - Halts the divider counter
73953  *  0b1..Divider clock is stopped
73954  *  0b0..Divider clock is running
73955  */
73956 #define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_HALT_SHIFT)) & SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_HALT_MASK)
73957 
73958 #define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_UNSTAB_MASK (0x80000000U)
73959 #define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_UNSTAB_SHIFT (31U)
73960 /*! UNSTAB - Divider status flag
73961  *  0b1..Clock frequency is not stable
73962  *  0b0..Divider clock is stable
73963  */
73964 #define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_UNSTAB_SHIFT)) & SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_UNSTAB_MASK)
73965 /*! @} */
73966 
73967 /* The count of SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV */
73968 #define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_COUNT (10U)
73969 
73970 /*! @name UTICKCLKSEL - UTICK Function Clock Source Select */
73971 /*! @{ */
73972 
73973 #define SYSCON_UTICKCLKSEL_SEL_MASK              (0x3U)
73974 #define SYSCON_UTICKCLKSEL_SEL_SHIFT             (0U)
73975 /*! SEL - Selects the clock source
73976  *  0b00..clk_in
73977  *  0b01..xtal32k[2]
73978  *  0b10..clk_1m clock
73979  *  0b11..No clock
73980  */
73981 #define SYSCON_UTICKCLKSEL_SEL(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_UTICKCLKSEL_SEL_SHIFT)) & SYSCON_UTICKCLKSEL_SEL_MASK)
73982 /*! @} */
73983 
73984 /*! @name SAI0CLKSEL - SAI0 Function Clock Source Select */
73985 /*! @{ */
73986 
73987 #define SYSCON_SAI0CLKSEL_SEL_MASK               (0x7U)
73988 #define SYSCON_SAI0CLKSEL_SEL_SHIFT              (0U)
73989 /*! SEL - Selects the clock source
73990  *  0b000..No clock
73991  *  0b001..PLL0 clock
73992  *  0b010..CLKIN clock
73993  *  0b011..FRO_HF clock
73994  *  0b100..PLL1_CLK0 clock
73995  *  0b101..No clock
73996  *  0b110..USB PLL clock
73997  *  0b111..No clock
73998  */
73999 #define SYSCON_SAI0CLKSEL_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_SAI0CLKSEL_SEL_SHIFT)) & SYSCON_SAI0CLKSEL_SEL_MASK)
74000 /*! @} */
74001 
74002 /*! @name SAI1CLKSEL - SAI1 Function Clock Source Select */
74003 /*! @{ */
74004 
74005 #define SYSCON_SAI1CLKSEL_SEL_MASK               (0x7U)
74006 #define SYSCON_SAI1CLKSEL_SEL_SHIFT              (0U)
74007 /*! SEL - Selects the clock source
74008  *  0b000..No clock
74009  *  0b001..PLL0 clock
74010  *  0b010..CLKIN clock
74011  *  0b011..FRO_HF clock
74012  *  0b100..PLL1_CLK0 clock
74013  *  0b101..No clock
74014  *  0b110..USB PLL clock
74015  *  0b111..No clock
74016  */
74017 #define SYSCON_SAI1CLKSEL_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_SAI1CLKSEL_SEL_SHIFT)) & SYSCON_SAI1CLKSEL_SEL_MASK)
74018 /*! @} */
74019 
74020 /*! @name SAI0CLKDIV - SAI0 Function Clock Division */
74021 /*! @{ */
74022 
74023 #define SYSCON_SAI0CLKDIV_DIV_MASK               (0x7U)
74024 #define SYSCON_SAI0CLKDIV_DIV_SHIFT              (0U)
74025 /*! DIV - Clock divider value */
74026 #define SYSCON_SAI0CLKDIV_DIV(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_SAI0CLKDIV_DIV_SHIFT)) & SYSCON_SAI0CLKDIV_DIV_MASK)
74027 
74028 #define SYSCON_SAI0CLKDIV_RESET_MASK             (0x20000000U)
74029 #define SYSCON_SAI0CLKDIV_RESET_SHIFT            (29U)
74030 /*! RESET - Resets the divider counter
74031  *  0b1..Divider is reset
74032  *  0b0..Divider is not reset
74033  */
74034 #define SYSCON_SAI0CLKDIV_RESET(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_SAI0CLKDIV_RESET_SHIFT)) & SYSCON_SAI0CLKDIV_RESET_MASK)
74035 
74036 #define SYSCON_SAI0CLKDIV_HALT_MASK              (0x40000000U)
74037 #define SYSCON_SAI0CLKDIV_HALT_SHIFT             (30U)
74038 /*! HALT - Halts the divider counter
74039  *  0b1..Divider clock is stopped
74040  *  0b0..Divider clock is running
74041  */
74042 #define SYSCON_SAI0CLKDIV_HALT(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SAI0CLKDIV_HALT_SHIFT)) & SYSCON_SAI0CLKDIV_HALT_MASK)
74043 
74044 #define SYSCON_SAI0CLKDIV_UNSTAB_MASK            (0x80000000U)
74045 #define SYSCON_SAI0CLKDIV_UNSTAB_SHIFT           (31U)
74046 /*! UNSTAB - Divider status flag
74047  *  0b1..Clock frequency is not stable
74048  *  0b0..Divider clock is stable
74049  */
74050 #define SYSCON_SAI0CLKDIV_UNSTAB(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_SAI0CLKDIV_UNSTAB_SHIFT)) & SYSCON_SAI0CLKDIV_UNSTAB_MASK)
74051 /*! @} */
74052 
74053 /*! @name SAI1CLKDIV - SAI1 Function Clock Division */
74054 /*! @{ */
74055 
74056 #define SYSCON_SAI1CLKDIV_DIV_MASK               (0x7U)
74057 #define SYSCON_SAI1CLKDIV_DIV_SHIFT              (0U)
74058 /*! DIV - Clock divider value */
74059 #define SYSCON_SAI1CLKDIV_DIV(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_SAI1CLKDIV_DIV_SHIFT)) & SYSCON_SAI1CLKDIV_DIV_MASK)
74060 
74061 #define SYSCON_SAI1CLKDIV_RESET_MASK             (0x20000000U)
74062 #define SYSCON_SAI1CLKDIV_RESET_SHIFT            (29U)
74063 /*! RESET - Resets the divider counter
74064  *  0b1..Divider is reset
74065  *  0b0..Divider is not reset
74066  */
74067 #define SYSCON_SAI1CLKDIV_RESET(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_SAI1CLKDIV_RESET_SHIFT)) & SYSCON_SAI1CLKDIV_RESET_MASK)
74068 
74069 #define SYSCON_SAI1CLKDIV_HALT_MASK              (0x40000000U)
74070 #define SYSCON_SAI1CLKDIV_HALT_SHIFT             (30U)
74071 /*! HALT - Halts the divider counter
74072  *  0b1..Divider clock is stopped
74073  *  0b0..Divider clock is running
74074  */
74075 #define SYSCON_SAI1CLKDIV_HALT(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SAI1CLKDIV_HALT_SHIFT)) & SYSCON_SAI1CLKDIV_HALT_MASK)
74076 
74077 #define SYSCON_SAI1CLKDIV_UNSTAB_MASK            (0x80000000U)
74078 #define SYSCON_SAI1CLKDIV_UNSTAB_SHIFT           (31U)
74079 /*! UNSTAB - Divider status flag
74080  *  0b1..Clock frequency is not stable
74081  *  0b0..Divider clock is stable
74082  */
74083 #define SYSCON_SAI1CLKDIV_UNSTAB(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_SAI1CLKDIV_UNSTAB_SHIFT)) & SYSCON_SAI1CLKDIV_UNSTAB_MASK)
74084 /*! @} */
74085 
74086 /*! @name EMVSIM0CLKSEL - EMVSIM0 Clock Source Select */
74087 /*! @{ */
74088 
74089 #define SYSCON_EMVSIM0CLKSEL_SEL_MASK            (0x7U)
74090 #define SYSCON_EMVSIM0CLKSEL_SEL_SHIFT           (0U)
74091 /*! SEL - Selects the EMVSIM0 function clock source
74092  *  0b000..No clock
74093  *  0b001..PLL0 clock
74094  *  0b010..CLKIN clock
74095  *  0b011..FRO_HF clock
74096  *  0b100..FRO_12M clock
74097  *  0b101..PLL1_clk0 clock0
74098  *  0b110..No clock
74099  *  0b111..No clock
74100  */
74101 #define SYSCON_EMVSIM0CLKSEL_SEL(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_EMVSIM0CLKSEL_SEL_SHIFT)) & SYSCON_EMVSIM0CLKSEL_SEL_MASK)
74102 /*! @} */
74103 
74104 /*! @name EMVSIM1CLKSEL - EMVSIM1 Clock Source Select */
74105 /*! @{ */
74106 
74107 #define SYSCON_EMVSIM1CLKSEL_SEL_MASK            (0x7U)
74108 #define SYSCON_EMVSIM1CLKSEL_SEL_SHIFT           (0U)
74109 /*! SEL - Selects the EMVSIM1 function clock source
74110  *  0b000..No clock
74111  *  0b001..PLL0 clock
74112  *  0b010..CLKIN clock
74113  *  0b011..FRO_HF clock
74114  *  0b100..FRO_12M clock
74115  *  0b101..PLL1_clk0 clock0
74116  *  0b110..No clock
74117  *  0b111..No clock
74118  */
74119 #define SYSCON_EMVSIM1CLKSEL_SEL(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_EMVSIM1CLKSEL_SEL_SHIFT)) & SYSCON_EMVSIM1CLKSEL_SEL_MASK)
74120 /*! @} */
74121 
74122 /*! @name EMVSIM0CLKDIV - EMVSIM0 Function Clock Division */
74123 /*! @{ */
74124 
74125 #define SYSCON_EMVSIM0CLKDIV_DIV_MASK            (0x7U)
74126 #define SYSCON_EMVSIM0CLKDIV_DIV_SHIFT           (0U)
74127 /*! DIV - Clock divider value */
74128 #define SYSCON_EMVSIM0CLKDIV_DIV(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_EMVSIM0CLKDIV_DIV_SHIFT)) & SYSCON_EMVSIM0CLKDIV_DIV_MASK)
74129 
74130 #define SYSCON_EMVSIM0CLKDIV_RESET_MASK          (0x20000000U)
74131 #define SYSCON_EMVSIM0CLKDIV_RESET_SHIFT         (29U)
74132 /*! RESET - Resets the divider counter
74133  *  0b1..Divider is reset
74134  *  0b0..Divider is not reset
74135  */
74136 #define SYSCON_EMVSIM0CLKDIV_RESET(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_EMVSIM0CLKDIV_RESET_SHIFT)) & SYSCON_EMVSIM0CLKDIV_RESET_MASK)
74137 
74138 #define SYSCON_EMVSIM0CLKDIV_HALT_MASK           (0x40000000U)
74139 #define SYSCON_EMVSIM0CLKDIV_HALT_SHIFT          (30U)
74140 /*! HALT - Halts the divider counter
74141  *  0b1..Divider clock is stopped
74142  *  0b0..Divider clock is running
74143  */
74144 #define SYSCON_EMVSIM0CLKDIV_HALT(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_EMVSIM0CLKDIV_HALT_SHIFT)) & SYSCON_EMVSIM0CLKDIV_HALT_MASK)
74145 
74146 #define SYSCON_EMVSIM0CLKDIV_UNSTAB_MASK         (0x80000000U)
74147 #define SYSCON_EMVSIM0CLKDIV_UNSTAB_SHIFT        (31U)
74148 /*! UNSTAB - Divider status flag
74149  *  0b1..Clock frequency is not stable
74150  *  0b0..Divider clock is stable
74151  */
74152 #define SYSCON_EMVSIM0CLKDIV_UNSTAB(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_EMVSIM0CLKDIV_UNSTAB_SHIFT)) & SYSCON_EMVSIM0CLKDIV_UNSTAB_MASK)
74153 /*! @} */
74154 
74155 /*! @name EMVSIM1CLKDIV - EMVSIM1 Function Clock Division */
74156 /*! @{ */
74157 
74158 #define SYSCON_EMVSIM1CLKDIV_DIV_MASK            (0x7U)
74159 #define SYSCON_EMVSIM1CLKDIV_DIV_SHIFT           (0U)
74160 /*! DIV - Clock divider value */
74161 #define SYSCON_EMVSIM1CLKDIV_DIV(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_EMVSIM1CLKDIV_DIV_SHIFT)) & SYSCON_EMVSIM1CLKDIV_DIV_MASK)
74162 
74163 #define SYSCON_EMVSIM1CLKDIV_RESET_MASK          (0x20000000U)
74164 #define SYSCON_EMVSIM1CLKDIV_RESET_SHIFT         (29U)
74165 /*! RESET - Resets the divider counter
74166  *  0b1..Divider is reset
74167  *  0b0..Divider is not reset
74168  */
74169 #define SYSCON_EMVSIM1CLKDIV_RESET(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_EMVSIM1CLKDIV_RESET_SHIFT)) & SYSCON_EMVSIM1CLKDIV_RESET_MASK)
74170 
74171 #define SYSCON_EMVSIM1CLKDIV_HALT_MASK           (0x40000000U)
74172 #define SYSCON_EMVSIM1CLKDIV_HALT_SHIFT          (30U)
74173 /*! HALT - Halts the divider counter
74174  *  0b1..Divider clock is stopped
74175  *  0b0..Divider clock is running
74176  */
74177 #define SYSCON_EMVSIM1CLKDIV_HALT(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_EMVSIM1CLKDIV_HALT_SHIFT)) & SYSCON_EMVSIM1CLKDIV_HALT_MASK)
74178 
74179 #define SYSCON_EMVSIM1CLKDIV_UNSTAB_MASK         (0x80000000U)
74180 #define SYSCON_EMVSIM1CLKDIV_UNSTAB_SHIFT        (31U)
74181 /*! UNSTAB - Divider status flag
74182  *  0b1..Clock frequency is not stable
74183  *  0b0..Divider clock is stable
74184  */
74185 #define SYSCON_EMVSIM1CLKDIV_UNSTAB(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_EMVSIM1CLKDIV_UNSTAB_SHIFT)) & SYSCON_EMVSIM1CLKDIV_UNSTAB_MASK)
74186 /*! @} */
74187 
74188 /*! @name KEY_RETAIN_CTRL - Key Retain Control */
74189 /*! @{ */
74190 
74191 #define SYSCON_KEY_RETAIN_CTRL_KEY_RETAIN_VALID_MASK (0x1U)
74192 #define SYSCON_KEY_RETAIN_CTRL_KEY_RETAIN_VALID_SHIFT (0U)
74193 /*! KEY_RETAIN_VALID - Indicates if the PUF key has been retained in the VBAT domain and has not
74194  *    been reset or otherwise invalidated by software.
74195  *  0b0..PUF key is not retained in VBAT domain.
74196  *  0b1..PUF key is retained in VBAT domain.
74197  */
74198 #define SYSCON_KEY_RETAIN_CTRL_KEY_RETAIN_VALID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_KEY_RETAIN_CTRL_KEY_RETAIN_VALID_SHIFT)) & SYSCON_KEY_RETAIN_CTRL_KEY_RETAIN_VALID_MASK)
74199 
74200 #define SYSCON_KEY_RETAIN_CTRL_KEY_RETAIN_DONE_MASK (0x2U)
74201 #define SYSCON_KEY_RETAIN_CTRL_KEY_RETAIN_DONE_SHIFT (1U)
74202 /*! KEY_RETAIN_DONE - Indicates the successful completion of the key_save or key_load routine. Once
74203  *    set, to clear the key_retain_done flag, both key_save and key_load should be cleared by
74204  *    software.
74205  *  0b0..Key save / load sequence has not completed.
74206  *  0b1..Key save / load sequence has completed.
74207  */
74208 #define SYSCON_KEY_RETAIN_CTRL_KEY_RETAIN_DONE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_KEY_RETAIN_CTRL_KEY_RETAIN_DONE_SHIFT)) & SYSCON_KEY_RETAIN_CTRL_KEY_RETAIN_DONE_MASK)
74209 
74210 #define SYSCON_KEY_RETAIN_CTRL_KEY_SAVE_MASK     (0x10000U)
74211 #define SYSCON_KEY_RETAIN_CTRL_KEY_SAVE_SHIFT    (16U)
74212 /*! KEY_SAVE
74213  *  0b0..Key save sequence is disabled.
74214  *  0b1..Key save sequence is enabled.
74215  */
74216 #define SYSCON_KEY_RETAIN_CTRL_KEY_SAVE(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_KEY_RETAIN_CTRL_KEY_SAVE_SHIFT)) & SYSCON_KEY_RETAIN_CTRL_KEY_SAVE_MASK)
74217 
74218 #define SYSCON_KEY_RETAIN_CTRL_KEY_LOAD_MASK     (0x20000U)
74219 #define SYSCON_KEY_RETAIN_CTRL_KEY_LOAD_SHIFT    (17U)
74220 /*! KEY_LOAD
74221  *  0b0..Key load sequence is disabled.
74222  *  0b1..Key load sequence is enabled.
74223  */
74224 #define SYSCON_KEY_RETAIN_CTRL_KEY_LOAD(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_KEY_RETAIN_CTRL_KEY_LOAD_SHIFT)) & SYSCON_KEY_RETAIN_CTRL_KEY_LOAD_MASK)
74225 /*! @} */
74226 
74227 /*! @name REF_CLK_CTRL - FRO 48MHz Reference Clock Control */
74228 /*! @{ */
74229 
74230 #define SYSCON_REF_CLK_CTRL_GDET_REFCLK_EN_MASK  (0x1U)
74231 #define SYSCON_REF_CLK_CTRL_GDET_REFCLK_EN_SHIFT (0U)
74232 /*! GDET_REFCLK_EN - GDET reference clock enable bit
74233  *  0b1..Enabled
74234  *  0b0..Disabled.
74235  */
74236 #define SYSCON_REF_CLK_CTRL_GDET_REFCLK_EN(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON_REF_CLK_CTRL_GDET_REFCLK_EN_SHIFT)) & SYSCON_REF_CLK_CTRL_GDET_REFCLK_EN_MASK)
74237 
74238 #define SYSCON_REF_CLK_CTRL_TRNG_REFCLK_EN_MASK  (0x2U)
74239 #define SYSCON_REF_CLK_CTRL_TRNG_REFCLK_EN_SHIFT (1U)
74240 /*! TRNG_REFCLK_EN - ELS TRNG reference clock enable bit
74241  *  0b1..Enabled
74242  *  0b0..Disabled.
74243  */
74244 #define SYSCON_REF_CLK_CTRL_TRNG_REFCLK_EN(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON_REF_CLK_CTRL_TRNG_REFCLK_EN_SHIFT)) & SYSCON_REF_CLK_CTRL_TRNG_REFCLK_EN_MASK)
74245 /*! @} */
74246 
74247 /*! @name REF_CLK_CTRL_SET - FRO 48MHz Reference Clock Control Set */
74248 /*! @{ */
74249 
74250 #define SYSCON_REF_CLK_CTRL_SET_GDET_REFCLK_EN_SET_MASK (0x1U)
74251 #define SYSCON_REF_CLK_CTRL_SET_GDET_REFCLK_EN_SET_SHIFT (0U)
74252 /*! GDET_REFCLK_EN_SET - GDET reference clock enable set bit
74253  *  0b1..Set to 1
74254  *  0b0..No effect.
74255  */
74256 #define SYSCON_REF_CLK_CTRL_SET_GDET_REFCLK_EN_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_REF_CLK_CTRL_SET_GDET_REFCLK_EN_SET_SHIFT)) & SYSCON_REF_CLK_CTRL_SET_GDET_REFCLK_EN_SET_MASK)
74257 
74258 #define SYSCON_REF_CLK_CTRL_SET_TRNG_REFCLK_EN_SET_MASK (0x2U)
74259 #define SYSCON_REF_CLK_CTRL_SET_TRNG_REFCLK_EN_SET_SHIFT (1U)
74260 /*! TRNG_REFCLK_EN_SET - ELS TRNG reference clock enable set bit
74261  *  0b1..Set to 1
74262  *  0b0..No effect.
74263  */
74264 #define SYSCON_REF_CLK_CTRL_SET_TRNG_REFCLK_EN_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_REF_CLK_CTRL_SET_TRNG_REFCLK_EN_SET_SHIFT)) & SYSCON_REF_CLK_CTRL_SET_TRNG_REFCLK_EN_SET_MASK)
74265 /*! @} */
74266 
74267 /*! @name REF_CLK_CTRL_CLR - FRO 48MHz Reference Clock Control Clear */
74268 /*! @{ */
74269 
74270 #define SYSCON_REF_CLK_CTRL_CLR_GDET_REFCLK_EN_CLR_MASK (0x1U)
74271 #define SYSCON_REF_CLK_CTRL_CLR_GDET_REFCLK_EN_CLR_SHIFT (0U)
74272 /*! GDET_REFCLK_EN_CLR - GDET reference clock enable clear bit
74273  *  0b1..Set to 0
74274  *  0b0..No effect.
74275  */
74276 #define SYSCON_REF_CLK_CTRL_CLR_GDET_REFCLK_EN_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_REF_CLK_CTRL_CLR_GDET_REFCLK_EN_CLR_SHIFT)) & SYSCON_REF_CLK_CTRL_CLR_GDET_REFCLK_EN_CLR_MASK)
74277 
74278 #define SYSCON_REF_CLK_CTRL_CLR_TRNG_REFCLK_EN_CLR_MASK (0x2U)
74279 #define SYSCON_REF_CLK_CTRL_CLR_TRNG_REFCLK_EN_CLR_SHIFT (1U)
74280 /*! TRNG_REFCLK_EN_CLR - ELS TRNG reference clock enable clear bit
74281  *  0b1..Set to 0
74282  *  0b0..No effect.
74283  */
74284 #define SYSCON_REF_CLK_CTRL_CLR_TRNG_REFCLK_EN_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_REF_CLK_CTRL_CLR_TRNG_REFCLK_EN_CLR_SHIFT)) & SYSCON_REF_CLK_CTRL_CLR_TRNG_REFCLK_EN_CLR_MASK)
74285 /*! @} */
74286 
74287 /*! @name GDETX_CTRL_GDET_CTRL - GDET Control Register */
74288 /*! @{ */
74289 
74290 #define SYSCON_GDETX_CTRL_GDET_CTRL_GDET_EVTCNT_CLR_MASK (0x1U)
74291 #define SYSCON_GDETX_CTRL_GDET_CTRL_GDET_EVTCNT_CLR_SHIFT (0U)
74292 /*! GDET_EVTCNT_CLR - Controls the GDET clean event counter
74293  *  0b1..Clears event counter
74294  *  0b0..Event counter not cleared
74295  */
74296 #define SYSCON_GDETX_CTRL_GDET_CTRL_GDET_EVTCNT_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_GDETX_CTRL_GDET_CTRL_GDET_EVTCNT_CLR_SHIFT)) & SYSCON_GDETX_CTRL_GDET_CTRL_GDET_EVTCNT_CLR_MASK)
74297 
74298 #define SYSCON_GDETX_CTRL_GDET_CTRL_GDET_ERR_CLR_MASK (0x2U)
74299 #define SYSCON_GDETX_CTRL_GDET_CTRL_GDET_ERR_CLR_SHIFT (1U)
74300 /*! GDET_ERR_CLR - Clears GDET error status
74301  *  0b1..Clears error status
74302  *  0b0..Error status not cleared
74303  */
74304 #define SYSCON_GDETX_CTRL_GDET_CTRL_GDET_ERR_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_GDETX_CTRL_GDET_CTRL_GDET_ERR_CLR_SHIFT)) & SYSCON_GDETX_CTRL_GDET_CTRL_GDET_ERR_CLR_MASK)
74305 
74306 #define SYSCON_GDETX_CTRL_GDET_CTRL_GDET_ISO_SW_MASK (0xCU)
74307 #define SYSCON_GDETX_CTRL_GDET_CTRL_GDET_ISO_SW_SHIFT (2U)
74308 /*! GDET_ISO_SW - GDET isolation control
74309  *  0b10..Isolation is enabled. When both GDET0_CTRL/GDET1_CTRL GDET_ISO_SW are "10", isolation_on is asserted.
74310  *  0b00..Isolation is disabled
74311  *  0b01..Isolation is disabled
74312  *  0b11..Isolation is disabled
74313  */
74314 #define SYSCON_GDETX_CTRL_GDET_CTRL_GDET_ISO_SW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_GDETX_CTRL_GDET_CTRL_GDET_ISO_SW_SHIFT)) & SYSCON_GDETX_CTRL_GDET_CTRL_GDET_ISO_SW_MASK)
74315 
74316 #define SYSCON_GDETX_CTRL_GDET_CTRL_EVENT_CNT_MASK (0xFF00U)
74317 #define SYSCON_GDETX_CTRL_GDET_CTRL_EVENT_CNT_SHIFT (8U)
74318 /*! EVENT_CNT - Event count value */
74319 #define SYSCON_GDETX_CTRL_GDET_CTRL_EVENT_CNT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_GDETX_CTRL_GDET_CTRL_EVENT_CNT_SHIFT)) & SYSCON_GDETX_CTRL_GDET_CTRL_EVENT_CNT_MASK)
74320 
74321 #define SYSCON_GDETX_CTRL_GDET_CTRL_POS_SYNC_MASK (0x10000U)
74322 #define SYSCON_GDETX_CTRL_GDET_CTRL_POS_SYNC_SHIFT (16U)
74323 /*! POS_SYNC - Positive glitch detected
74324  *  0b1..Positive glitch detected
74325  *  0b0..Positive glitch not detected
74326  */
74327 #define SYSCON_GDETX_CTRL_GDET_CTRL_POS_SYNC(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON_GDETX_CTRL_GDET_CTRL_POS_SYNC_SHIFT)) & SYSCON_GDETX_CTRL_GDET_CTRL_POS_SYNC_MASK)
74328 
74329 #define SYSCON_GDETX_CTRL_GDET_CTRL_NEG_SYNC_MASK (0x20000U)
74330 #define SYSCON_GDETX_CTRL_GDET_CTRL_NEG_SYNC_SHIFT (17U)
74331 /*! NEG_SYNC - Negative glitch detected
74332  *  0b1..Negative glitch detected
74333  *  0b0..Negative glitch not detected
74334  */
74335 #define SYSCON_GDETX_CTRL_GDET_CTRL_NEG_SYNC(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON_GDETX_CTRL_GDET_CTRL_NEG_SYNC_SHIFT)) & SYSCON_GDETX_CTRL_GDET_CTRL_NEG_SYNC_MASK)
74336 
74337 #define SYSCON_GDETX_CTRL_GDET_CTRL_EVENT_CLR_FLAG_MASK (0x40000U)
74338 #define SYSCON_GDETX_CTRL_GDET_CTRL_EVENT_CLR_FLAG_SHIFT (18U)
74339 /*! EVENT_CLR_FLAG - Event counter cleared
74340  *  0b1..Event counter cleared
74341  *  0b0..Event counter not cleared
74342  */
74343 #define SYSCON_GDETX_CTRL_GDET_CTRL_EVENT_CLR_FLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_GDETX_CTRL_GDET_CTRL_EVENT_CLR_FLAG_SHIFT)) & SYSCON_GDETX_CTRL_GDET_CTRL_EVENT_CLR_FLAG_MASK)
74344 /*! @} */
74345 
74346 /* The count of SYSCON_GDETX_CTRL_GDET_CTRL */
74347 #define SYSCON_GDETX_CTRL_GDET_CTRL_COUNT        (2U)
74348 
74349 /*! @name ELS_ASSET_PROT - ELS Asset Protection Register */
74350 /*! @{ */
74351 
74352 #define SYSCON_ELS_ASSET_PROT_ASSET_PROTECTION_MASK (0x3U)
74353 #define SYSCON_ELS_ASSET_PROT_ASSET_PROTECTION_SHIFT (0U)
74354 /*! ASSET_PROTECTION - ELS asset protection. This field controls the asset protection port to the
74355  *    ELS module. Refer to the ELS chapter in the SRM for more details.
74356  *  0b00..ELS asset is protected
74357  *  0b10..ELS asset is protected
74358  *  0b11..ELS asset is protected
74359  *  0b01..ELS asset is not protected
74360  */
74361 #define SYSCON_ELS_ASSET_PROT_ASSET_PROTECTION(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_ASSET_PROT_ASSET_PROTECTION_SHIFT)) & SYSCON_ELS_ASSET_PROT_ASSET_PROTECTION_MASK)
74362 /*! @} */
74363 
74364 /*! @name ELS_LOCK_CTRL - ELS Lock Control */
74365 /*! @{ */
74366 
74367 #define SYSCON_ELS_LOCK_CTRL_LOCK_CTRL_MASK      (0x3U)
74368 #define SYSCON_ELS_LOCK_CTRL_LOCK_CTRL_SHIFT     (0U)
74369 /*! LOCK_CTRL - ELS Lock Control */
74370 #define SYSCON_ELS_LOCK_CTRL_LOCK_CTRL(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_LOCK_CTRL_LOCK_CTRL_SHIFT)) & SYSCON_ELS_LOCK_CTRL_LOCK_CTRL_MASK)
74371 /*! @} */
74372 
74373 /*! @name ELS_LOCK_CTRL_DP - ELS Lock Control DP */
74374 /*! @{ */
74375 
74376 #define SYSCON_ELS_LOCK_CTRL_DP_LOCK_CTRL_DP_MASK (0x3U)
74377 #define SYSCON_ELS_LOCK_CTRL_DP_LOCK_CTRL_DP_SHIFT (0U)
74378 /*! LOCK_CTRL_DP - Refer to ELS_LOCK_CTRL[1:0] */
74379 #define SYSCON_ELS_LOCK_CTRL_DP_LOCK_CTRL_DP(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_LOCK_CTRL_DP_LOCK_CTRL_DP_SHIFT)) & SYSCON_ELS_LOCK_CTRL_DP_LOCK_CTRL_DP_MASK)
74380 /*! @} */
74381 
74382 /*! @name ELS_OTP_LC_STATE - Life Cycle State Register */
74383 /*! @{ */
74384 
74385 #define SYSCON_ELS_OTP_LC_STATE_OTP_LC_STATE_MASK (0xFFU)
74386 #define SYSCON_ELS_OTP_LC_STATE_OTP_LC_STATE_SHIFT (0U)
74387 /*! OTP_LC_STATE - OTP life cycle state */
74388 #define SYSCON_ELS_OTP_LC_STATE_OTP_LC_STATE(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_OTP_LC_STATE_OTP_LC_STATE_SHIFT)) & SYSCON_ELS_OTP_LC_STATE_OTP_LC_STATE_MASK)
74389 /*! @} */
74390 
74391 /*! @name ELS_OTP_LC_STATE_DP - Life Cycle State Register (Duplicate) */
74392 /*! @{ */
74393 
74394 #define SYSCON_ELS_OTP_LC_STATE_DP_OTP_LC_STATE_DP_MASK (0xFFU)
74395 #define SYSCON_ELS_OTP_LC_STATE_DP_OTP_LC_STATE_DP_SHIFT (0U)
74396 /*! OTP_LC_STATE_DP - OTP life cycle state */
74397 #define SYSCON_ELS_OTP_LC_STATE_DP_OTP_LC_STATE_DP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_OTP_LC_STATE_DP_OTP_LC_STATE_DP_SHIFT)) & SYSCON_ELS_OTP_LC_STATE_DP_OTP_LC_STATE_DP_MASK)
74398 /*! @} */
74399 
74400 /*! @name ELS_TEMPORAL_STATE - ELS Temporal State */
74401 /*! @{ */
74402 
74403 #define SYSCON_ELS_TEMPORAL_STATE_TEMPORAL_STATE_MASK (0xFU)
74404 #define SYSCON_ELS_TEMPORAL_STATE_TEMPORAL_STATE_SHIFT (0U)
74405 /*! TEMPORAL_STATE - Temporal state */
74406 #define SYSCON_ELS_TEMPORAL_STATE_TEMPORAL_STATE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_TEMPORAL_STATE_TEMPORAL_STATE_SHIFT)) & SYSCON_ELS_TEMPORAL_STATE_TEMPORAL_STATE_MASK)
74407 /*! @} */
74408 
74409 /*! @name ELS_KDF_MASK - Key Derivation Function Mask */
74410 /*! @{ */
74411 
74412 #define SYSCON_ELS_KDF_MASK_KDF_MASK_MASK        (0xFFFFFFFFU)
74413 #define SYSCON_ELS_KDF_MASK_KDF_MASK_SHIFT       (0U)
74414 /*! KDF_MASK - Key derivation function mask */
74415 #define SYSCON_ELS_KDF_MASK_KDF_MASK(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_KDF_MASK_KDF_MASK_SHIFT)) & SYSCON_ELS_KDF_MASK_KDF_MASK_MASK)
74416 /*! @} */
74417 
74418 /*! @name ELS_AS_CFG0 - ELS AS Configuration */
74419 /*! @{ */
74420 
74421 #define SYSCON_ELS_AS_CFG0_CFG_LC_STATE_MASK     (0xFFU)
74422 #define SYSCON_ELS_AS_CFG0_CFG_LC_STATE_SHIFT    (0U)
74423 /*! CFG_LC_STATE - LC state configuration bit */
74424 #define SYSCON_ELS_AS_CFG0_CFG_LC_STATE(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_LC_STATE_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_LC_STATE_MASK)
74425 
74426 #define SYSCON_ELS_AS_CFG0_CFG_LVD_CORE_RESET_ENABLED_MASK (0x200U)
74427 #define SYSCON_ELS_AS_CFG0_CFG_LVD_CORE_RESET_ENABLED_SHIFT (9U)
74428 /*! CFG_LVD_CORE_RESET_ENABLED - When SPC CORE LVD analog detector are turned on, and CORE LVD reset are enabled, this bit indicates state 1. */
74429 #define SYSCON_ELS_AS_CFG0_CFG_LVD_CORE_RESET_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_LVD_CORE_RESET_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_LVD_CORE_RESET_ENABLED_MASK)
74430 
74431 #define SYSCON_ELS_AS_CFG0_CFG_LVD_CORE_IRQ_ENABLED_MASK (0x800U)
74432 #define SYSCON_ELS_AS_CFG0_CFG_LVD_CORE_IRQ_ENABLED_SHIFT (11U)
74433 /*! CFG_LVD_CORE_IRQ_ENABLED - When SPC CORE LVD analog detector are turned on, and CORE LVD IRQ are enabled, this bit indicates state 1. */
74434 #define SYSCON_ELS_AS_CFG0_CFG_LVD_CORE_IRQ_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_LVD_CORE_IRQ_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_LVD_CORE_IRQ_ENABLED_MASK)
74435 
74436 #define SYSCON_ELS_AS_CFG0_CFG_WDT0_ENABLED_MASK (0x1000U)
74437 #define SYSCON_ELS_AS_CFG0_CFG_WDT0_ENABLED_SHIFT (12U)
74438 /*! CFG_WDT0_ENABLED - When WatchDog Timer 0 is activated, this bit indicates state 1 */
74439 #define SYSCON_ELS_AS_CFG0_CFG_WDT0_ENABLED(x)   (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_WDT0_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_WDT0_ENABLED_MASK)
74440 
74441 #define SYSCON_ELS_AS_CFG0_CFG_CWDT0_ENABLED_MASK (0x2000U)
74442 #define SYSCON_ELS_AS_CFG0_CFG_CWDT0_ENABLED_SHIFT (13U)
74443 /*! CFG_CWDT0_ENABLED - When Code WatchDog Timer 0 is activated, this bit indicates state 1 */
74444 #define SYSCON_ELS_AS_CFG0_CFG_CWDT0_ENABLED(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_CWDT0_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_CWDT0_ENABLED_MASK)
74445 
74446 #define SYSCON_ELS_AS_CFG0_CFG_ELS_GDET_ENABLED_MASK (0x4000U)
74447 #define SYSCON_ELS_AS_CFG0_CFG_ELS_GDET_ENABLED_SHIFT (14U)
74448 /*! CFG_ELS_GDET_ENABLED - When either GDET is enabled, this bit indicates state 1. */
74449 #define SYSCON_ELS_AS_CFG0_CFG_ELS_GDET_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_ELS_GDET_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_ELS_GDET_ENABLED_MASK)
74450 
74451 #define SYSCON_ELS_AS_CFG0_CFG_ANA_GDET_RESET_ENABLED_MASK (0x8000U)
74452 #define SYSCON_ELS_AS_CFG0_CFG_ANA_GDET_RESET_ENABLED_SHIFT (15U)
74453 /*! CFG_ANA_GDET_RESET_ENABLED - When SPC analog glitch detect reset is enabled, this bit indicates state 1 */
74454 #define SYSCON_ELS_AS_CFG0_CFG_ANA_GDET_RESET_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_ANA_GDET_RESET_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_ANA_GDET_RESET_ENABLED_MASK)
74455 
74456 #define SYSCON_ELS_AS_CFG0_CFG_ANA_GDET_IRQ_ENABLED_MASK (0x10000U)
74457 #define SYSCON_ELS_AS_CFG0_CFG_ANA_GDET_IRQ_ENABLED_SHIFT (16U)
74458 /*! CFG_ANA_GDET_IRQ_ENABLED - When SPC analog glitch detect IRQ is enabled, this bit indicates state 1 */
74459 #define SYSCON_ELS_AS_CFG0_CFG_ANA_GDET_IRQ_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_ANA_GDET_IRQ_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_ANA_GDET_IRQ_ENABLED_MASK)
74460 
74461 #define SYSCON_ELS_AS_CFG0_CFG_TAMPER_DET_ENABLED_MASK (0x20000U)
74462 #define SYSCON_ELS_AS_CFG0_CFG_TAMPER_DET_ENABLED_SHIFT (17U)
74463 /*! CFG_TAMPER_DET_ENABLED - When tamper detector is enabled in TDET, this bit indicates state 1. */
74464 #define SYSCON_ELS_AS_CFG0_CFG_TAMPER_DET_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_TAMPER_DET_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_TAMPER_DET_ENABLED_MASK)
74465 
74466 #define SYSCON_ELS_AS_CFG0_CFG_LVD_VSYS_RESET_ENABLED_MASK (0x40000U)
74467 #define SYSCON_ELS_AS_CFG0_CFG_LVD_VSYS_RESET_ENABLED_SHIFT (18U)
74468 /*! CFG_LVD_VSYS_RESET_ENABLED - When SPC VSYS LVD analog detector are turned on and VSYS LVD reset are enabled, this bit indicates state 1. */
74469 #define SYSCON_ELS_AS_CFG0_CFG_LVD_VSYS_RESET_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_LVD_VSYS_RESET_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_LVD_VSYS_RESET_ENABLED_MASK)
74470 
74471 #define SYSCON_ELS_AS_CFG0_CFG_LVD_VDDIO_RESET_ENABLED_MASK (0x80000U)
74472 #define SYSCON_ELS_AS_CFG0_CFG_LVD_VDDIO_RESET_ENABLED_SHIFT (19U)
74473 /*! CFG_LVD_VDDIO_RESET_ENABLED - When SPC VDDIO LVD analog detector are turned on and VDDIO LVD reset are enabled, this bit indicates state 1. */
74474 #define SYSCON_ELS_AS_CFG0_CFG_LVD_VDDIO_RESET_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_LVD_VDDIO_RESET_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_LVD_VDDIO_RESET_ENABLED_MASK)
74475 
74476 #define SYSCON_ELS_AS_CFG0_CFG_LVD_VSYS_IRQ_ENABLED_MASK (0x100000U)
74477 #define SYSCON_ELS_AS_CFG0_CFG_LVD_VSYS_IRQ_ENABLED_SHIFT (20U)
74478 /*! CFG_LVD_VSYS_IRQ_ENABLED - When SPC VSYS LVD analog detector are turned on and VSYS LVD irq are enabled, this bit indicates state 1. */
74479 #define SYSCON_ELS_AS_CFG0_CFG_LVD_VSYS_IRQ_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_LVD_VSYS_IRQ_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_LVD_VSYS_IRQ_ENABLED_MASK)
74480 
74481 #define SYSCON_ELS_AS_CFG0_CFG_LVD_VDDIO_IRQ_ENABLED_MASK (0x200000U)
74482 #define SYSCON_ELS_AS_CFG0_CFG_LVD_VDDIO_IRQ_ENABLED_SHIFT (21U)
74483 /*! CFG_LVD_VDDIO_IRQ_ENABLED - When SPC VDDIO LVD analog detector are turned on and VDDIO LVD irq are enabled, this bit indicates state 1. */
74484 #define SYSCON_ELS_AS_CFG0_CFG_LVD_VDDIO_IRQ_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_LVD_VDDIO_IRQ_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_LVD_VDDIO_IRQ_ENABLED_MASK)
74485 
74486 #define SYSCON_ELS_AS_CFG0_CFG_WDT1_ENABLED_MASK (0x400000U)
74487 #define SYSCON_ELS_AS_CFG0_CFG_WDT1_ENABLED_SHIFT (22U)
74488 /*! CFG_WDT1_ENABLED - When WatchDog Timer 1 is activated, this bit indicates state 1. */
74489 #define SYSCON_ELS_AS_CFG0_CFG_WDT1_ENABLED(x)   (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_WDT1_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_WDT1_ENABLED_MASK)
74490 
74491 #define SYSCON_ELS_AS_CFG0_CFG_CWDT1_ENABLED_MASK (0x800000U)
74492 #define SYSCON_ELS_AS_CFG0_CFG_CWDT1_ENABLED_SHIFT (23U)
74493 /*! CFG_CWDT1_ENABLED - When Code WatchDog Timer 1 is activated, this bit indicates state 1. */
74494 #define SYSCON_ELS_AS_CFG0_CFG_CWDT1_ENABLED(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_CWDT1_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_CWDT1_ENABLED_MASK)
74495 
74496 #define SYSCON_ELS_AS_CFG0_CFG_TEMPTAMPER_DET_ENABLED_MASK (0x1000000U)
74497 #define SYSCON_ELS_AS_CFG0_CFG_TEMPTAMPER_DET_ENABLED_SHIFT (24U)
74498 /*! CFG_TEMPTAMPER_DET_ENABLED - When temperature tamper detector is enabled in VBAT, this bit indicates state 1. */
74499 #define SYSCON_ELS_AS_CFG0_CFG_TEMPTAMPER_DET_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_TEMPTAMPER_DET_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_TEMPTAMPER_DET_ENABLED_MASK)
74500 
74501 #define SYSCON_ELS_AS_CFG0_CFG_VOLTAMPER_DET_ENABLED_MASK (0x2000000U)
74502 #define SYSCON_ELS_AS_CFG0_CFG_VOLTAMPER_DET_ENABLED_SHIFT (25U)
74503 /*! CFG_VOLTAMPER_DET_ENABLED - When voltage tamper detector is enabled in VBAT, this bit indicates state 1. */
74504 #define SYSCON_ELS_AS_CFG0_CFG_VOLTAMPER_DET_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_VOLTAMPER_DET_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_VOLTAMPER_DET_ENABLED_MASK)
74505 
74506 #define SYSCON_ELS_AS_CFG0_CFG_LHTTAMPER_DET_ENABLED_MASK (0x4000000U)
74507 #define SYSCON_ELS_AS_CFG0_CFG_LHTTAMPER_DET_ENABLED_SHIFT (26U)
74508 /*! CFG_LHTTAMPER_DET_ENABLED - When light tamper detector is enabled in VBAT, this bit indicates state 1. */
74509 #define SYSCON_ELS_AS_CFG0_CFG_LHTTAMPER_DET_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_LHTTAMPER_DET_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_LHTTAMPER_DET_ENABLED_MASK)
74510 
74511 #define SYSCON_ELS_AS_CFG0_CFG_CLKTAMPER_DET_ENABLED_MASK (0x8000000U)
74512 #define SYSCON_ELS_AS_CFG0_CFG_CLKTAMPER_DET_ENABLED_SHIFT (27U)
74513 /*! CFG_CLKTAMPER_DET_ENABLED - When clk tamper detector is enabled in VBAT, this bit indicates state 1. */
74514 #define SYSCON_ELS_AS_CFG0_CFG_CLKTAMPER_DET_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_CLKTAMPER_DET_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_CLKTAMPER_DET_ENABLED_MASK)
74515 
74516 #define SYSCON_ELS_AS_CFG0_CFG_QK_DISABLE_ENROLL_MASK (0x10000000U)
74517 #define SYSCON_ELS_AS_CFG0_CFG_QK_DISABLE_ENROLL_SHIFT (28U)
74518 /*! CFG_QK_DISABLE_ENROLL - When QK PUF "qk_disable_enroll" input is driven 1, this bit indicates state 1 */
74519 #define SYSCON_ELS_AS_CFG0_CFG_QK_DISABLE_ENROLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_QK_DISABLE_ENROLL_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_QK_DISABLE_ENROLL_MASK)
74520 
74521 #define SYSCON_ELS_AS_CFG0_CFG_QK_DISABLE_WRAP_MASK (0x20000000U)
74522 #define SYSCON_ELS_AS_CFG0_CFG_QK_DISABLE_WRAP_SHIFT (29U)
74523 /*! CFG_QK_DISABLE_WRAP - When QK PUF "qk_disable_wrap" input is driven 1, this bit indicates state 1 */
74524 #define SYSCON_ELS_AS_CFG0_CFG_QK_DISABLE_WRAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_QK_DISABLE_WRAP_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_QK_DISABLE_WRAP_MASK)
74525 /*! @} */
74526 
74527 /*! @name ELS_AS_CFG1 - ELS AS Configuration1 */
74528 /*! @{ */
74529 
74530 #define SYSCON_ELS_AS_CFG1_CFG_SEC_DIS_STRICT_MODE_MASK (0x2U)
74531 #define SYSCON_ELS_AS_CFG1_CFG_SEC_DIS_STRICT_MODE_SHIFT (1U)
74532 /*! CFG_SEC_DIS_STRICT_MODE - When CFG_SEC_ENA_SEC_CHK indicates state 0 or when DISABLE_STRICT_MODE
74533  *    bits in MISC_CTRL_REG and MISC_CTRL_DP_REG on the AHB secure controller are equal to 01, this
74534  *    bit indicates state 1
74535  */
74536 #define SYSCON_ELS_AS_CFG1_CFG_SEC_DIS_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_CFG_SEC_DIS_STRICT_MODE_SHIFT)) & SYSCON_ELS_AS_CFG1_CFG_SEC_DIS_STRICT_MODE_MASK)
74537 
74538 #define SYSCON_ELS_AS_CFG1_CFG_SEC_DIS_VIOL_ABORT_MASK (0x4U)
74539 #define SYSCON_ELS_AS_CFG1_CFG_SEC_DIS_VIOL_ABORT_SHIFT (2U)
74540 /*! CFG_SEC_DIS_VIOL_ABORT - When the DISABLE_VIOLATION_ABORT bits in MISC_CTRL_REG and
74541  *    MISC_CTRL_DP_REG on the AHB secure controller are not equal to 10, this bit indicates state 1
74542  */
74543 #define SYSCON_ELS_AS_CFG1_CFG_SEC_DIS_VIOL_ABORT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_CFG_SEC_DIS_VIOL_ABORT_SHIFT)) & SYSCON_ELS_AS_CFG1_CFG_SEC_DIS_VIOL_ABORT_MASK)
74544 
74545 #define SYSCON_ELS_AS_CFG1_CFG_SEC_ENA_NS_PRIV_CHK_MASK (0x8U)
74546 #define SYSCON_ELS_AS_CFG1_CFG_SEC_ENA_NS_PRIV_CHK_SHIFT (3U)
74547 /*! CFG_SEC_ENA_NS_PRIV_CHK - When the ENABLE_NS_PRIV_CHECK bits in MISC_CTRL_REG and
74548  *    MISC_CTRL_DP_REG on the AHB secure controller are not equal to 10, this bit indicates state 1
74549  */
74550 #define SYSCON_ELS_AS_CFG1_CFG_SEC_ENA_NS_PRIV_CHK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_CFG_SEC_ENA_NS_PRIV_CHK_SHIFT)) & SYSCON_ELS_AS_CFG1_CFG_SEC_ENA_NS_PRIV_CHK_MASK)
74551 
74552 #define SYSCON_ELS_AS_CFG1_CFG_SEC_ENA_S_PRIV_CHK_MASK (0x10U)
74553 #define SYSCON_ELS_AS_CFG1_CFG_SEC_ENA_S_PRIV_CHK_SHIFT (4U)
74554 /*! CFG_SEC_ENA_S_PRIV_CHK - When the ENABLE_S_PRIV_CHECK bits in MISC_CTRL_REG and MISC_CTRL_DP_REG
74555  *    on the AHB secure controller are not equal to 10, this bit indicates state 1
74556  */
74557 #define SYSCON_ELS_AS_CFG1_CFG_SEC_ENA_S_PRIV_CHK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_CFG_SEC_ENA_S_PRIV_CHK_SHIFT)) & SYSCON_ELS_AS_CFG1_CFG_SEC_ENA_S_PRIV_CHK_MASK)
74558 
74559 #define SYSCON_ELS_AS_CFG1_CFG_SEC_ENA_SEC_CHK_MASK (0x20U)
74560 #define SYSCON_ELS_AS_CFG1_CFG_SEC_ENA_SEC_CHK_SHIFT (5U)
74561 /*! CFG_SEC_ENA_SEC_CHK - When the ENABLE_SECURE_CHECKING bits in MISC_CTRL_REG and MISC_CTRL_DP_REG
74562  *    on the AHB secure controller are not equal to 10, this bit indicates state 1
74563  */
74564 #define SYSCON_ELS_AS_CFG1_CFG_SEC_ENA_SEC_CHK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_CFG_SEC_ENA_SEC_CHK_SHIFT)) & SYSCON_ELS_AS_CFG1_CFG_SEC_ENA_SEC_CHK_MASK)
74565 
74566 #define SYSCON_ELS_AS_CFG1_CFG_SEC_IDAU_ALLNS_MASK (0x40U)
74567 #define SYSCON_ELS_AS_CFG1_CFG_SEC_IDAU_ALLNS_SHIFT (6U)
74568 /*! CFG_SEC_IDAU_ALLNS - When the IDAU_ALL_NS bits in MISC_CTRL_REG and MISC_CTRL_DP_REG on the AHB
74569  *    secure controller are equal to 01, this bit indicates state 1
74570  */
74571 #define SYSCON_ELS_AS_CFG1_CFG_SEC_IDAU_ALLNS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_CFG_SEC_IDAU_ALLNS_SHIFT)) & SYSCON_ELS_AS_CFG1_CFG_SEC_IDAU_ALLNS_MASK)
74572 
74573 #define SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_NS_MPU_MASK (0x100U)
74574 #define SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_NS_MPU_SHIFT (8U)
74575 /*! CFG_SEC_LOCK_NS_MPU - When the LOCK_NS_MPU bits in CPU0_LOCK_REG on the AHB secure controller are not equal to 10, this bit indicates state 1 */
74576 #define SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_NS_MPU(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_NS_MPU_SHIFT)) & SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_NS_MPU_MASK)
74577 
74578 #define SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_NS_VTOR_MASK (0x200U)
74579 #define SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_NS_VTOR_SHIFT (9U)
74580 /*! CFG_SEC_LOCK_NS_VTOR - When the LOCK_NS_VTOR bits in CPU0_LOCK_REG on the AHB secure controller are not equal to 10, this bit indicates state 1 */
74581 #define SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_NS_VTOR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_NS_VTOR_SHIFT)) & SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_NS_VTOR_MASK)
74582 
74583 #define SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_S_MPU_MASK (0x400U)
74584 #define SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_S_MPU_SHIFT (10U)
74585 /*! CFG_SEC_LOCK_S_MPU - When the LOCK_S_MPU bits in CPU0_LOCK_REG on the AHB secure controller are not equal to 10, this bit indicates state 1 */
74586 #define SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_S_MPU(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_S_MPU_SHIFT)) & SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_S_MPU_MASK)
74587 
74588 #define SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_S_VTAIRCR_MASK (0x800U)
74589 #define SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_S_VTAIRCR_SHIFT (11U)
74590 /*! CFG_SEC_LOCK_S_VTAIRCR - When the LOCK_S_VTAIRCR bits in CPU0_LOCK_REG on the AHB secure
74591  *    controller are not equal to 10, this bit indicates state 1
74592  */
74593 #define SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_S_VTAIRCR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_S_VTAIRCR_SHIFT)) & SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_S_VTAIRCR_MASK)
74594 
74595 #define SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_SAU_MASK (0x1000U)
74596 #define SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_SAU_SHIFT (12U)
74597 /*! CFG_SEC_LOCK_SAU - When the LOCK_SAU bits in CPU0_LOCK_REG on the AHB secure controller are not equal to 10, this bit indicates state 1 */
74598 #define SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_SAU(x)   (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_SAU_SHIFT)) & SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_SAU_MASK)
74599 
74600 #define SYSCON_ELS_AS_CFG1_METAL_VERSION_MASK    (0x1FE000U)
74601 #define SYSCON_ELS_AS_CFG1_METAL_VERSION_SHIFT   (13U)
74602 /*! METAL_VERSION - metal version */
74603 #define SYSCON_ELS_AS_CFG1_METAL_VERSION(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_METAL_VERSION_SHIFT)) & SYSCON_ELS_AS_CFG1_METAL_VERSION_MASK)
74604 
74605 #define SYSCON_ELS_AS_CFG1_ROM_PATCH_VERSION_MASK (0x1E00000U)
74606 #define SYSCON_ELS_AS_CFG1_ROM_PATCH_VERSION_SHIFT (21U)
74607 /*! ROM_PATCH_VERSION - ROM patch version */
74608 #define SYSCON_ELS_AS_CFG1_ROM_PATCH_VERSION(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_ROM_PATCH_VERSION_SHIFT)) & SYSCON_ELS_AS_CFG1_ROM_PATCH_VERSION_MASK)
74609 
74610 #define SYSCON_ELS_AS_CFG1_CFG_HVD_CORE_RESET_ENABLED_MASK (0x4000000U)
74611 #define SYSCON_ELS_AS_CFG1_CFG_HVD_CORE_RESET_ENABLED_SHIFT (26U)
74612 /*! CFG_HVD_CORE_RESET_ENABLED - When SPC CORE HVD analog detector are turned on, and CORE HVD reset are enabled, this bit indicates state 1. */
74613 #define SYSCON_ELS_AS_CFG1_CFG_HVD_CORE_RESET_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_CFG_HVD_CORE_RESET_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG1_CFG_HVD_CORE_RESET_ENABLED_MASK)
74614 
74615 #define SYSCON_ELS_AS_CFG1_CFG_HVD_CORE_IRQ_ENABLED_MASK (0x8000000U)
74616 #define SYSCON_ELS_AS_CFG1_CFG_HVD_CORE_IRQ_ENABLED_SHIFT (27U)
74617 /*! CFG_HVD_CORE_IRQ_ENABLED - When SPC CORE HVD analog detector are turned on, and CORE HVD IRQ are enabled, this bit indicates state 1. */
74618 #define SYSCON_ELS_AS_CFG1_CFG_HVD_CORE_IRQ_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_CFG_HVD_CORE_IRQ_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG1_CFG_HVD_CORE_IRQ_ENABLED_MASK)
74619 
74620 #define SYSCON_ELS_AS_CFG1_CFG_HVD_VSYS_RESET_ENABLED_MASK (0x10000000U)
74621 #define SYSCON_ELS_AS_CFG1_CFG_HVD_VSYS_RESET_ENABLED_SHIFT (28U)
74622 /*! CFG_HVD_VSYS_RESET_ENABLED - When SPC VSYS HVD analog detector are turned on and VSYS HVD reset are enabled, this bit indicates state 1. */
74623 #define SYSCON_ELS_AS_CFG1_CFG_HVD_VSYS_RESET_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_CFG_HVD_VSYS_RESET_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG1_CFG_HVD_VSYS_RESET_ENABLED_MASK)
74624 
74625 #define SYSCON_ELS_AS_CFG1_CFG_HVD_VDDIO_RESET_ENABLED_MASK (0x20000000U)
74626 #define SYSCON_ELS_AS_CFG1_CFG_HVD_VDDIO_RESET_ENABLED_SHIFT (29U)
74627 /*! CFG_HVD_VDDIO_RESET_ENABLED - When SPC VDDIO HVD analog detector are turned on and VDDIO HVD reset are enabled, this bit indicates state 1. */
74628 #define SYSCON_ELS_AS_CFG1_CFG_HVD_VDDIO_RESET_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_CFG_HVD_VDDIO_RESET_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG1_CFG_HVD_VDDIO_RESET_ENABLED_MASK)
74629 
74630 #define SYSCON_ELS_AS_CFG1_CFG_HVD_VSYS_IRQ_ENABLED_MASK (0x40000000U)
74631 #define SYSCON_ELS_AS_CFG1_CFG_HVD_VSYS_IRQ_ENABLED_SHIFT (30U)
74632 /*! CFG_HVD_VSYS_IRQ_ENABLED - When SPC VSYS HVD analog detector are turned on and VSYS HVD irq are enabled, this bit indicates state 1. */
74633 #define SYSCON_ELS_AS_CFG1_CFG_HVD_VSYS_IRQ_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_CFG_HVD_VSYS_IRQ_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG1_CFG_HVD_VSYS_IRQ_ENABLED_MASK)
74634 
74635 #define SYSCON_ELS_AS_CFG1_CFG_HVD_VDDIO_IRQ_ENABLED_MASK (0x80000000U)
74636 #define SYSCON_ELS_AS_CFG1_CFG_HVD_VDDIO_IRQ_ENABLED_SHIFT (31U)
74637 /*! CFG_HVD_VDDIO_IRQ_ENABLED - When SPC VDDIO HVD analog detector are turned on and VDDIO HVD irq are enabled, this bit indicates state 1. */
74638 #define SYSCON_ELS_AS_CFG1_CFG_HVD_VDDIO_IRQ_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_CFG_HVD_VDDIO_IRQ_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG1_CFG_HVD_VDDIO_IRQ_ENABLED_MASK)
74639 /*! @} */
74640 
74641 /*! @name ELS_AS_CFG2 - ELS AS Configuration2 */
74642 /*! @{ */
74643 
74644 #define SYSCON_ELS_AS_CFG2_CFG_ELS_CMD_EN_MASK   (0xFFFFFFFFU)
74645 #define SYSCON_ELS_AS_CFG2_CFG_ELS_CMD_EN_SHIFT  (0U)
74646 /*! CFG_ELS_CMD_EN - ELS configuration command enable bit */
74647 #define SYSCON_ELS_AS_CFG2_CFG_ELS_CMD_EN(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG2_CFG_ELS_CMD_EN_SHIFT)) & SYSCON_ELS_AS_CFG2_CFG_ELS_CMD_EN_MASK)
74648 /*! @} */
74649 
74650 /*! @name ELS_AS_CFG3 - ELS AS Configuration3 */
74651 /*! @{ */
74652 
74653 #define SYSCON_ELS_AS_CFG3_DEVICE_TYPE_MASK      (0xFFFFFFFFU)
74654 #define SYSCON_ELS_AS_CFG3_DEVICE_TYPE_SHIFT     (0U)
74655 /*! DEVICE_TYPE - Device type identification data */
74656 #define SYSCON_ELS_AS_CFG3_DEVICE_TYPE(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG3_DEVICE_TYPE_SHIFT)) & SYSCON_ELS_AS_CFG3_DEVICE_TYPE_MASK)
74657 /*! @} */
74658 
74659 /*! @name ELS_AS_ST0 - ELS AS State Register */
74660 /*! @{ */
74661 
74662 #define SYSCON_ELS_AS_ST0_ST_TEMPORAL_STATE_MASK (0xFU)
74663 #define SYSCON_ELS_AS_ST0_ST_TEMPORAL_STATE_SHIFT (0U)
74664 /*! ST_TEMPORAL_STATE - TEMPORAL_STATE[3:0] in the ELS_TEMPORAL_STATE register reflects this register */
74665 #define SYSCON_ELS_AS_ST0_ST_TEMPORAL_STATE(x)   (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST0_ST_TEMPORAL_STATE_SHIFT)) & SYSCON_ELS_AS_ST0_ST_TEMPORAL_STATE_MASK)
74666 
74667 #define SYSCON_ELS_AS_ST0_ST_CPU0_DBGEN_MASK     (0x10U)
74668 #define SYSCON_ELS_AS_ST0_ST_CPU0_DBGEN_SHIFT    (4U)
74669 /*! ST_CPU0_DBGEN - When CPU0 (CM33) "deben" input is state 1, this bit indicates state 1 */
74670 #define SYSCON_ELS_AS_ST0_ST_CPU0_DBGEN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST0_ST_CPU0_DBGEN_SHIFT)) & SYSCON_ELS_AS_ST0_ST_CPU0_DBGEN_MASK)
74671 
74672 #define SYSCON_ELS_AS_ST0_ST_CPU0_NIDEN_MASK     (0x20U)
74673 #define SYSCON_ELS_AS_ST0_ST_CPU0_NIDEN_SHIFT    (5U)
74674 /*! ST_CPU0_NIDEN - When CPU0 (CM33) "niden" input is state 1, this bit indicates state 1 */
74675 #define SYSCON_ELS_AS_ST0_ST_CPU0_NIDEN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST0_ST_CPU0_NIDEN_SHIFT)) & SYSCON_ELS_AS_ST0_ST_CPU0_NIDEN_MASK)
74676 
74677 #define SYSCON_ELS_AS_ST0_ST_CPU0_SPIDEN_MASK    (0x40U)
74678 #define SYSCON_ELS_AS_ST0_ST_CPU0_SPIDEN_SHIFT   (6U)
74679 /*! ST_CPU0_SPIDEN - When CPU0 (CM33) "spiden" input is state 1, this bit indicates state 1 */
74680 #define SYSCON_ELS_AS_ST0_ST_CPU0_SPIDEN(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST0_ST_CPU0_SPIDEN_SHIFT)) & SYSCON_ELS_AS_ST0_ST_CPU0_SPIDEN_MASK)
74681 
74682 #define SYSCON_ELS_AS_ST0_ST_CPU0_SPNIDEN_MASK   (0x80U)
74683 #define SYSCON_ELS_AS_ST0_ST_CPU0_SPNIDEN_SHIFT  (7U)
74684 /*! ST_CPU0_SPNIDEN - When CPU0 (CM33) "spniden" input is state 1, this bit indicates state 1 */
74685 #define SYSCON_ELS_AS_ST0_ST_CPU0_SPNIDEN(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST0_ST_CPU0_SPNIDEN_SHIFT)) & SYSCON_ELS_AS_ST0_ST_CPU0_SPNIDEN_MASK)
74686 
74687 #define SYSCON_ELS_AS_ST0_ST_CPU1_DBGEN_MASK     (0x100U)
74688 #define SYSCON_ELS_AS_ST0_ST_CPU1_DBGEN_SHIFT    (8U)
74689 /*! ST_CPU1_DBGEN - When CPU1 (CM33) "deben" input is state 1, this bit indicates state 1. */
74690 #define SYSCON_ELS_AS_ST0_ST_CPU1_DBGEN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST0_ST_CPU1_DBGEN_SHIFT)) & SYSCON_ELS_AS_ST0_ST_CPU1_DBGEN_MASK)
74691 
74692 #define SYSCON_ELS_AS_ST0_ST_CPU1_NIDEN_MASK     (0x200U)
74693 #define SYSCON_ELS_AS_ST0_ST_CPU1_NIDEN_SHIFT    (9U)
74694 /*! ST_CPU1_NIDEN - When CPU1 (CM33) "niden" input is state 1, this bit indicates state 1. */
74695 #define SYSCON_ELS_AS_ST0_ST_CPU1_NIDEN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST0_ST_CPU1_NIDEN_SHIFT)) & SYSCON_ELS_AS_ST0_ST_CPU1_NIDEN_MASK)
74696 
74697 #define SYSCON_ELS_AS_ST0_ST_DAP_ENABLE_CPU0_MASK (0x400U)
74698 #define SYSCON_ELS_AS_ST0_ST_DAP_ENABLE_CPU0_SHIFT (10U)
74699 /*! ST_DAP_ENABLE_CPU0 - When DAP to AP0 for CPU0 (CM33) debug access is allowed, this bit indicates state 1 */
74700 #define SYSCON_ELS_AS_ST0_ST_DAP_ENABLE_CPU0(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST0_ST_DAP_ENABLE_CPU0_SHIFT)) & SYSCON_ELS_AS_ST0_ST_DAP_ENABLE_CPU0_MASK)
74701 
74702 #define SYSCON_ELS_AS_ST0_ST_DAP_ENABLE_CPU1_MASK (0x800U)
74703 #define SYSCON_ELS_AS_ST0_ST_DAP_ENABLE_CPU1_SHIFT (11U)
74704 /*! ST_DAP_ENABLE_CPU1 - When DAP to AP1 for CPU1 (CM33) debug access is allowed, this bit indicates state 1. */
74705 #define SYSCON_ELS_AS_ST0_ST_DAP_ENABLE_CPU1(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST0_ST_DAP_ENABLE_CPU1_SHIFT)) & SYSCON_ELS_AS_ST0_ST_DAP_ENABLE_CPU1_MASK)
74706 
74707 #define SYSCON_ELS_AS_ST0_ST_DAP_ENABLE_DSP_MASK (0x1000U)
74708 #define SYSCON_ELS_AS_ST0_ST_DAP_ENABLE_DSP_SHIFT (12U)
74709 /*! ST_DAP_ENABLE_DSP - When DAP to AP3 for DSP (CoolFlux) debug access is allowed, this bit indicates state 1 */
74710 #define SYSCON_ELS_AS_ST0_ST_DAP_ENABLE_DSP(x)   (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST0_ST_DAP_ENABLE_DSP_SHIFT)) & SYSCON_ELS_AS_ST0_ST_DAP_ENABLE_DSP_MASK)
74711 
74712 #define SYSCON_ELS_AS_ST0_ST_ALLOW_TEST_ACCESS_MASK (0x4000U)
74713 #define SYSCON_ELS_AS_ST0_ST_ALLOW_TEST_ACCESS_SHIFT (14U)
74714 /*! ST_ALLOW_TEST_ACCESS - When JTAG TAP access is allowed, this bit indicates state 1. */
74715 #define SYSCON_ELS_AS_ST0_ST_ALLOW_TEST_ACCESS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST0_ST_ALLOW_TEST_ACCESS_SHIFT)) & SYSCON_ELS_AS_ST0_ST_ALLOW_TEST_ACCESS_MASK)
74716 
74717 #define SYSCON_ELS_AS_ST0_ST_XO32K_FAILED_MASK   (0x8000U)
74718 #define SYSCON_ELS_AS_ST0_ST_XO32K_FAILED_SHIFT  (15U)
74719 /*! ST_XO32K_FAILED - When XO32K oscillation fail flag is state 1, this bit indicates state 1 */
74720 #define SYSCON_ELS_AS_ST0_ST_XO32K_FAILED(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST0_ST_XO32K_FAILED_SHIFT)) & SYSCON_ELS_AS_ST0_ST_XO32K_FAILED_MASK)
74721 
74722 #define SYSCON_ELS_AS_ST0_ST_XO40M_FAILED_MASK   (0x10000U)
74723 #define SYSCON_ELS_AS_ST0_ST_XO40M_FAILED_SHIFT  (16U)
74724 /*! ST_XO40M_FAILED - When XO40M oscillation fail flag is state 1, this bit indicates state 1 */
74725 #define SYSCON_ELS_AS_ST0_ST_XO40M_FAILED(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST0_ST_XO40M_FAILED_SHIFT)) & SYSCON_ELS_AS_ST0_ST_XO40M_FAILED_MASK)
74726 
74727 #define SYSCON_ELS_AS_ST0_ST_IFR_LOAD_FAILED_MASK (0x20000U)
74728 #define SYSCON_ELS_AS_ST0_ST_IFR_LOAD_FAILED_SHIFT (17U)
74729 /*! ST_IFR_LOAD_FAILED - When IFR load fail flag is state 1, this bit indicates state 1 */
74730 #define SYSCON_ELS_AS_ST0_ST_IFR_LOAD_FAILED(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST0_ST_IFR_LOAD_FAILED_SHIFT)) & SYSCON_ELS_AS_ST0_ST_IFR_LOAD_FAILED_MASK)
74731 
74732 #define SYSCON_ELS_AS_ST0_ST_GLITCH_DETECT_FLAG_MASK (0x3C0000U)
74733 #define SYSCON_ELS_AS_ST0_ST_GLITCH_DETECT_FLAG_SHIFT (18U)
74734 /*! ST_GLITCH_DETECT_FLAG - GLITCH_DETECT_FLAG is state of 4-bit Glitch Ripple Counter output. */
74735 #define SYSCON_ELS_AS_ST0_ST_GLITCH_DETECT_FLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST0_ST_GLITCH_DETECT_FLAG_SHIFT)) & SYSCON_ELS_AS_ST0_ST_GLITCH_DETECT_FLAG_MASK)
74736 /*! @} */
74737 
74738 /*! @name ELS_AS_ST1 - ELS AS State1 */
74739 /*! @{ */
74740 
74741 #define SYSCON_ELS_AS_ST1_ST_QK_PUF_SCORE_MASK   (0xFU)
74742 #define SYSCON_ELS_AS_ST1_ST_QK_PUF_SCORE_SHIFT  (0U)
74743 /*! ST_QK_PUF_SCORE - These register bits indicate the state of "qk_puf_score[3:0]" outputs from QK PUF block */
74744 #define SYSCON_ELS_AS_ST1_ST_QK_PUF_SCORE(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST1_ST_QK_PUF_SCORE_SHIFT)) & SYSCON_ELS_AS_ST1_ST_QK_PUF_SCORE_MASK)
74745 
74746 #define SYSCON_ELS_AS_ST1_ST_QK_ZEROIZED_MASK    (0x10U)
74747 #define SYSCON_ELS_AS_ST1_ST_QK_ZEROIZED_SHIFT   (4U)
74748 /*! ST_QK_ZEROIZED - This register bit indicates the state of "qk_zeroized" output from QK PUF block */
74749 #define SYSCON_ELS_AS_ST1_ST_QK_ZEROIZED(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST1_ST_QK_ZEROIZED_SHIFT)) & SYSCON_ELS_AS_ST1_ST_QK_ZEROIZED_MASK)
74750 
74751 #define SYSCON_ELS_AS_ST1_ST_MAIN_CLK_IS_EXT_MASK (0x20U)
74752 #define SYSCON_ELS_AS_ST1_ST_MAIN_CLK_IS_EXT_SHIFT (5U)
74753 /*! ST_MAIN_CLK_IS_EXT - When MAIN_CLK is running from external clock source either XO32M, XO32K or GPIO CLKIN, this bit indicates state 1 */
74754 #define SYSCON_ELS_AS_ST1_ST_MAIN_CLK_IS_EXT(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST1_ST_MAIN_CLK_IS_EXT_SHIFT)) & SYSCON_ELS_AS_ST1_ST_MAIN_CLK_IS_EXT_MASK)
74755 
74756 #define SYSCON_ELS_AS_ST1_ST_DCDC_VOUT_MASK      (0xC0U)
74757 #define SYSCON_ELS_AS_ST1_ST_DCDC_VOUT_SHIFT     (6U)
74758 /*! ST_DCDC_VOUT - VOUT[1:0] setting on DCDC0 register in SPC block will reflect to this register. Default is 1.0V */
74759 #define SYSCON_ELS_AS_ST1_ST_DCDC_VOUT(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST1_ST_DCDC_VOUT_SHIFT)) & SYSCON_ELS_AS_ST1_ST_DCDC_VOUT_MASK)
74760 
74761 #define SYSCON_ELS_AS_ST1_ST_DCDC_DS_MASK        (0x300U)
74762 #define SYSCON_ELS_AS_ST1_ST_DCDC_DS_SHIFT       (8U)
74763 /*! ST_DCDC_DS - DCDC drive strength setting. Default is normal drive. */
74764 #define SYSCON_ELS_AS_ST1_ST_DCDC_DS(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST1_ST_DCDC_DS_SHIFT)) & SYSCON_ELS_AS_ST1_ST_DCDC_DS_MASK)
74765 
74766 #define SYSCON_ELS_AS_ST1_ST_BOOT_MODE_MASK      (0xC00U)
74767 #define SYSCON_ELS_AS_ST1_ST_BOOT_MODE_SHIFT     (10U)
74768 /*! ST_BOOT_MODE - ISP pin status during boot. By default ISP pin is pulled up. If want to enter ISP
74769  *    mode during boot, ISP pin should be pull down when out of reset.
74770  */
74771 #define SYSCON_ELS_AS_ST1_ST_BOOT_MODE(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST1_ST_BOOT_MODE_SHIFT)) & SYSCON_ELS_AS_ST1_ST_BOOT_MODE_MASK)
74772 
74773 #define SYSCON_ELS_AS_ST1_ST_BOOT_RETRY_CNT_MASK (0xF000U)
74774 #define SYSCON_ELS_AS_ST1_ST_BOOT_RETRY_CNT_SHIFT (12U)
74775 /*! ST_BOOT_RETRY_CNT - BOOT_RETRY_CNT[3:0] in the ELS_BOOT_RETRY_CNT register reflects this register */
74776 #define SYSCON_ELS_AS_ST1_ST_BOOT_RETRY_CNT(x)   (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST1_ST_BOOT_RETRY_CNT_SHIFT)) & SYSCON_ELS_AS_ST1_ST_BOOT_RETRY_CNT_MASK)
74777 
74778 #define SYSCON_ELS_AS_ST1_ST_LDO_CORE_VOUT_MASK  (0x30000U)
74779 #define SYSCON_ELS_AS_ST1_ST_LDO_CORE_VOUT_SHIFT (16U)
74780 /*! ST_LDO_CORE_VOUT - VOUT[1:0] setting on LDO Core register in SPC block will reflect to this register. Default is 1.0V */
74781 #define SYSCON_ELS_AS_ST1_ST_LDO_CORE_VOUT(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST1_ST_LDO_CORE_VOUT_SHIFT)) & SYSCON_ELS_AS_ST1_ST_LDO_CORE_VOUT_MASK)
74782 
74783 #define SYSCON_ELS_AS_ST1_ST_LDO_CORE_DS_MASK    (0xC0000U)
74784 #define SYSCON_ELS_AS_ST1_ST_LDO_CORE_DS_SHIFT   (18U)
74785 /*! ST_LDO_CORE_DS - LDO_CORE drive strength setting. Default is normal drive. */
74786 #define SYSCON_ELS_AS_ST1_ST_LDO_CORE_DS(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST1_ST_LDO_CORE_DS_SHIFT)) & SYSCON_ELS_AS_ST1_ST_LDO_CORE_DS_MASK)
74787 /*! @} */
74788 
74789 /*! @name ELS_AS_BOOT_LOG0 - Boot state captured during boot: Main ROM log */
74790 /*! @{ */
74791 
74792 #define SYSCON_ELS_AS_BOOT_LOG0_BOOT_IMAGE_MASK  (0xFU)
74793 #define SYSCON_ELS_AS_BOOT_LOG0_BOOT_IMAGE_SHIFT (0U)
74794 /*! BOOT_IMAGE - Boot image source used during this boot.
74795  *  0b0000..Internal flash image 0
74796  *  0b0001..Internal flash image 1
74797  *  0b0010..FlexSPI flash image 0
74798  *  0b0011..FlexSPI flash image 1
74799  *  0b0100..Recovery SPI flash image
74800  *  0b0101..Serial boot image (write-memory and execute ISP command used)
74801  *  0b0110..Receive SB3 containing SB_JUMP command is used.
74802  *  0b0111..Customer SBL/recovery image (Bank1 IFR0).
74803  *  0b1000..NXP MAD recovery image (Bank1 IFR0).
74804  *  0b1001..NXP ROM extension (NMPA - Bank0 IFR0).
74805  *  0b1010..Reserved.
74806  *  0b1011..Reserved.
74807  *  0b1100..Reserved.
74808  *  0b1101..Reserved.
74809  *  0b1110..Reserved.
74810  *  0b1111..Reserved.
74811  */
74812 #define SYSCON_ELS_AS_BOOT_LOG0_BOOT_IMAGE(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG0_BOOT_IMAGE_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG0_BOOT_IMAGE_MASK)
74813 
74814 #define SYSCON_ELS_AS_BOOT_LOG0_CMAC_MASK        (0x10U)
74815 #define SYSCON_ELS_AS_BOOT_LOG0_CMAC_SHIFT       (4U)
74816 /*! CMAC - CMAC verify is used instead of ECDSA verify on this boot. */
74817 #define SYSCON_ELS_AS_BOOT_LOG0_CMAC(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG0_CMAC_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG0_CMAC_MASK)
74818 
74819 #define SYSCON_ELS_AS_BOOT_LOG0_ECDSA_MASK       (0x40U)
74820 #define SYSCON_ELS_AS_BOOT_LOG0_ECDSA_SHIFT      (6U)
74821 /*! ECDSA - ECDSA P-384 verification is done on this boot. */
74822 #define SYSCON_ELS_AS_BOOT_LOG0_ECDSA(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG0_ECDSA_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG0_ECDSA_MASK)
74823 
74824 #define SYSCON_ELS_AS_BOOT_LOG0_OFF_CHIP_MASK    (0x80U)
74825 #define SYSCON_ELS_AS_BOOT_LOG0_OFF_CHIP_SHIFT   (7U)
74826 /*! OFF_CHIP - Off-chip Prince is enabled during boot. */
74827 #define SYSCON_ELS_AS_BOOT_LOG0_OFF_CHIP(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG0_OFF_CHIP_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG0_OFF_CHIP_MASK)
74828 
74829 #define SYSCON_ELS_AS_BOOT_LOG0_ON_CHIP_MASK     (0x100U)
74830 #define SYSCON_ELS_AS_BOOT_LOG0_ON_CHIP_SHIFT    (8U)
74831 /*! ON_CHIP - On-chip Prince is enabled during boot. */
74832 #define SYSCON_ELS_AS_BOOT_LOG0_ON_CHIP(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG0_ON_CHIP_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG0_ON_CHIP_MASK)
74833 
74834 #define SYSCON_ELS_AS_BOOT_LOG0_CDI_CSR_MASK     (0x200U)
74835 #define SYSCON_ELS_AS_BOOT_LOG0_CDI_CSR_SHIFT    (9U)
74836 /*! CDI_CSR - CDI based device keys are derived for CSR harvesting on this boot. */
74837 #define SYSCON_ELS_AS_BOOT_LOG0_CDI_CSR(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG0_CDI_CSR_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG0_CDI_CSR_MASK)
74838 
74839 #define SYSCON_ELS_AS_BOOT_LOG0_CDI_DICE_MASK    (0x400U)
74840 #define SYSCON_ELS_AS_BOOT_LOG0_CDI_DICE_SHIFT   (10U)
74841 /*! CDI_DICE - CDI per DICE specification is computed on this boot. */
74842 #define SYSCON_ELS_AS_BOOT_LOG0_CDI_DICE(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG0_CDI_DICE_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG0_CDI_DICE_MASK)
74843 
74844 #define SYSCON_ELS_AS_BOOT_LOG0_TRUSTZONE_MASK   (0x800U)
74845 #define SYSCON_ELS_AS_BOOT_LOG0_TRUSTZONE_SHIFT  (11U)
74846 /*! TRUSTZONE - TrustZone preset data is loaded during this boot. */
74847 #define SYSCON_ELS_AS_BOOT_LOG0_TRUSTZONE(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG0_TRUSTZONE_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG0_TRUSTZONE_MASK)
74848 
74849 #define SYSCON_ELS_AS_BOOT_LOG0_DEBUG_AUTH_MASK  (0x1000U)
74850 #define SYSCON_ELS_AS_BOOT_LOG0_DEBUG_AUTH_SHIFT (12U)
74851 /*! DEBUG_AUTH - Debug authentication done in this session prior to boot. */
74852 #define SYSCON_ELS_AS_BOOT_LOG0_DEBUG_AUTH(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG0_DEBUG_AUTH_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG0_DEBUG_AUTH_MASK)
74853 
74854 #define SYSCON_ELS_AS_BOOT_LOG0_ITRC_MASK        (0x2000U)
74855 #define SYSCON_ELS_AS_BOOT_LOG0_ITRC_SHIFT       (13U)
74856 /*! ITRC - ITRC zeroize event is handled in this session of boot. */
74857 #define SYSCON_ELS_AS_BOOT_LOG0_ITRC(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG0_ITRC_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG0_ITRC_MASK)
74858 
74859 #define SYSCON_ELS_AS_BOOT_LOG0_DIG_GDET_MASK    (0x4000U)
74860 #define SYSCON_ELS_AS_BOOT_LOG0_DIG_GDET_SHIFT   (14U)
74861 /*! DIG_GDET - Digital glitch detector is enabled during boot. */
74862 #define SYSCON_ELS_AS_BOOT_LOG0_DIG_GDET(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG0_DIG_GDET_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG0_DIG_GDET_MASK)
74863 
74864 #define SYSCON_ELS_AS_BOOT_LOG0_ANA_GDET_MASK    (0x8000U)
74865 #define SYSCON_ELS_AS_BOOT_LOG0_ANA_GDET_SHIFT   (15U)
74866 /*! ANA_GDET - Analog glitch detector is enabled during boot. */
74867 #define SYSCON_ELS_AS_BOOT_LOG0_ANA_GDET(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG0_ANA_GDET_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG0_ANA_GDET_MASK)
74868 
74869 #define SYSCON_ELS_AS_BOOT_LOG0_DEEP_PD_MASK     (0x10000U)
74870 #define SYSCON_ELS_AS_BOOT_LOG0_DEEP_PD_SHIFT    (16U)
74871 /*! DEEP_PD - Boot from deep-power down state. */
74872 #define SYSCON_ELS_AS_BOOT_LOG0_DEEP_PD(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG0_DEEP_PD_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG0_DEEP_PD_MASK)
74873 
74874 #define SYSCON_ELS_AS_BOOT_LOG0_LOW_POWER_MASK   (0xF000000U)
74875 #define SYSCON_ELS_AS_BOOT_LOG0_LOW_POWER_SHIFT  (24U)
74876 /*! LOW_POWER - Last low-power mode value. ROM copies SPC_LP_MODE field from SPC->SC[7:4]. */
74877 #define SYSCON_ELS_AS_BOOT_LOG0_LOW_POWER(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG0_LOW_POWER_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG0_LOW_POWER_MASK)
74878 
74879 #define SYSCON_ELS_AS_BOOT_LOG0_ISP_MASK         (0x80000000U)
74880 #define SYSCON_ELS_AS_BOOT_LOG0_ISP_SHIFT        (31U)
74881 /*! ISP - ISP pin state at boot time. ROM copies CMC->MR0[0]. */
74882 #define SYSCON_ELS_AS_BOOT_LOG0_ISP(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG0_ISP_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG0_ISP_MASK)
74883 /*! @} */
74884 
74885 /*! @name ELS_AS_BOOT_LOG1 - Boot state captured during boot: Library log */
74886 /*! @{ */
74887 
74888 #define SYSCON_ELS_AS_BOOT_LOG1_RoTK_MASK        (0x3U)
74889 #define SYSCON_ELS_AS_BOOT_LOG1_RoTK_SHIFT       (0U)
74890 /*! RoTK - RoTK index used for this boot. */
74891 #define SYSCON_ELS_AS_BOOT_LOG1_RoTK(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG1_RoTK_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG1_RoTK_MASK)
74892 
74893 #define SYSCON_ELS_AS_BOOT_LOG1_FIPS_MASK        (0x3FCU)
74894 #define SYSCON_ELS_AS_BOOT_LOG1_FIPS_SHIFT       (2U)
74895 /*! FIPS - FIPS self-test is executed and PASS during this boot. When a bit is set, means self-test
74896  *    is executed and it FAILS. When a bit is clear, means corresponding self-test is executed and
74897  *    PASS or it is not executed.
74898  */
74899 #define SYSCON_ELS_AS_BOOT_LOG1_FIPS(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG1_FIPS_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG1_FIPS_MASK)
74900 
74901 #define SYSCON_ELS_AS_BOOT_LOG1_SB3_MASK         (0xC00U)
74902 #define SYSCON_ELS_AS_BOOT_LOG1_SB3_SHIFT        (10U)
74903 /*! SB3 - SB3 type (valid after nboot_sb3_load_manifest()).
74904  *  0b00..customer fw load/update file.
74905  *  0b01..NXP Provisioning FW.
74906  *  0b10..ELS signed OEM Provisioning FW.
74907  */
74908 #define SYSCON_ELS_AS_BOOT_LOG1_SB3(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG1_SB3_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG1_SB3_MASK)
74909 /*! @} */
74910 
74911 /*! @name ELS_AS_BOOT_LOG2 - Boot state captured during boot: Hardware status signals log */
74912 /*! @{ */
74913 
74914 #define SYSCON_ELS_AS_BOOT_LOG2_CMC_SRS0_MASK    (0x3FU)
74915 #define SYSCON_ELS_AS_BOOT_LOG2_CMC_SRS0_SHIFT   (0U)
74916 /*! CMC_SRS0 - CMC->SRS[5:0] */
74917 #define SYSCON_ELS_AS_BOOT_LOG2_CMC_SRS0(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG2_CMC_SRS0_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG2_CMC_SRS0_MASK)
74918 
74919 #define SYSCON_ELS_AS_BOOT_LOG2_VBAT_STATUS0_MASK (0xC0U)
74920 #define SYSCON_ELS_AS_BOOT_LOG2_VBAT_STATUS0_SHIFT (6U)
74921 /*! VBAT_STATUS0 - VBAT->STATUSA[1:0] | ~VBAT->STATUSB[1:0] */
74922 #define SYSCON_ELS_AS_BOOT_LOG2_VBAT_STATUS0(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG2_VBAT_STATUS0_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG2_VBAT_STATUS0_MASK)
74923 
74924 #define SYSCON_ELS_AS_BOOT_LOG2_CMC_SRS1_MASK    (0x1FF00U)
74925 #define SYSCON_ELS_AS_BOOT_LOG2_CMC_SRS1_SHIFT   (8U)
74926 /*! CMC_SRS1 - CMC->SRS[16:8] */
74927 #define SYSCON_ELS_AS_BOOT_LOG2_CMC_SRS1(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG2_CMC_SRS1_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG2_CMC_SRS1_MASK)
74928 
74929 #define SYSCON_ELS_AS_BOOT_LOG2_VBAT_STATUS1_MASK (0xFC0000U)
74930 #define SYSCON_ELS_AS_BOOT_LOG2_VBAT_STATUS1_SHIFT (18U)
74931 /*! VBAT_STATUS1 - VBAT->STATUSA[11:6] | ~VBAT->STATUSB[11:6] */
74932 #define SYSCON_ELS_AS_BOOT_LOG2_VBAT_STATUS1(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG2_VBAT_STATUS1_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG2_VBAT_STATUS1_MASK)
74933 
74934 #define SYSCON_ELS_AS_BOOT_LOG2_CMC_SRS2_MASK    (0xFF000000U)
74935 #define SYSCON_ELS_AS_BOOT_LOG2_CMC_SRS2_SHIFT   (24U)
74936 /*! CMC_SRS2 - CMC->SRS[31:24] */
74937 #define SYSCON_ELS_AS_BOOT_LOG2_CMC_SRS2(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG2_CMC_SRS2_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG2_CMC_SRS2_MASK)
74938 /*! @} */
74939 
74940 /*! @name ELS_AS_BOOT_LOG3 - Boot state captured during boot: Security log */
74941 /*! @{ */
74942 
74943 #define SYSCON_ELS_AS_BOOT_LOG3_ERR_AUTH_FAIL_COUNT_MASK (0xFFU)
74944 #define SYSCON_ELS_AS_BOOT_LOG3_ERR_AUTH_FAIL_COUNT_SHIFT (0U)
74945 /*! ERR_AUTH_FAIL_COUNT - CFPA->ERR_AUTH_FAIL_COUNT[7:0] */
74946 #define SYSCON_ELS_AS_BOOT_LOG3_ERR_AUTH_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG3_ERR_AUTH_FAIL_COUNT_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG3_ERR_AUTH_FAIL_COUNT_MASK)
74947 
74948 #define SYSCON_ELS_AS_BOOT_LOG3_ERR_ITRC_COUNT_MASK (0xFF00U)
74949 #define SYSCON_ELS_AS_BOOT_LOG3_ERR_ITRC_COUNT_SHIFT (8U)
74950 /*! ERR_ITRC_COUNT - CFPA->ERR_ITRC_COUNT[7:0] */
74951 #define SYSCON_ELS_AS_BOOT_LOG3_ERR_ITRC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG3_ERR_ITRC_COUNT_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG3_ERR_ITRC_COUNT_MASK)
74952 /*! @} */
74953 
74954 /*! @name ELS_AS_FLAG0 - ELS AS Flag0 */
74955 /*! @{ */
74956 
74957 #define SYSCON_ELS_AS_FLAG0_FLAG_AP_ENABLE_CPU0_MASK (0x1U)
74958 #define SYSCON_ELS_AS_FLAG0_FLAG_AP_ENABLE_CPU0_SHIFT (0U)
74959 /*! FLAG_AP_ENABLE_CPU0 - This flag bit is set as 1 when DAP enables AP0 for CPU0 (CM33) debug
74960  *    access. The register is cleared 0 by PMC reset event.
74961  *  0b1..Triggered
74962  *  0b0..Not Triggered
74963  */
74964 #define SYSCON_ELS_AS_FLAG0_FLAG_AP_ENABLE_CPU0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_AP_ENABLE_CPU0_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_AP_ENABLE_CPU0_MASK)
74965 
74966 #define SYSCON_ELS_AS_FLAG0_FLAG_AP_ENABLE_CPU1_MASK (0x2U)
74967 #define SYSCON_ELS_AS_FLAG0_FLAG_AP_ENABLE_CPU1_SHIFT (1U)
74968 /*! FLAG_AP_ENABLE_CPU1 - This flag bit is set as 1 when DAP enables AP1 for CPU1 (CM33) debug
74969  *    access. The register is cleared 0 by PMC reset event.
74970  *  0b1..Triggered
74971  *  0b0..Not Triggered
74972  */
74973 #define SYSCON_ELS_AS_FLAG0_FLAG_AP_ENABLE_CPU1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_AP_ENABLE_CPU1_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_AP_ENABLE_CPU1_MASK)
74974 
74975 #define SYSCON_ELS_AS_FLAG0_FLAG_AP_ENABLE_DSP_MASK (0x4U)
74976 #define SYSCON_ELS_AS_FLAG0_FLAG_AP_ENABLE_DSP_SHIFT (2U)
74977 /*! FLAG_AP_ENABLE_DSP - This flag bit is set as 1 when DAP enables AP3 for DSP (CoolFlux) debug
74978  *    access. The register is cleared 0 by PMC reset event.
74979  *  0b1..Triggered
74980  *  0b0..Not Triggered
74981  */
74982 #define SYSCON_ELS_AS_FLAG0_FLAG_AP_ENABLE_DSP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_AP_ENABLE_DSP_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_AP_ENABLE_DSP_MASK)
74983 
74984 #define SYSCON_ELS_AS_FLAG0_EFUSE_ATTACK_DETECT_MASK (0x8U)
74985 #define SYSCON_ELS_AS_FLAG0_EFUSE_ATTACK_DETECT_SHIFT (3U)
74986 /*! EFUSE_ATTACK_DETECT - OTPC can output attack_detect signal when it detects attack when load
74987  *    shadow registers. The output will be cleared by reset. ELS_AS_FLAG is reset by PoR, so the status
74988  *    can be recorded.
74989  *  0b1..Triggered
74990  *  0b0..Not Triggered
74991  */
74992 #define SYSCON_ELS_AS_FLAG0_EFUSE_ATTACK_DETECT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_EFUSE_ATTACK_DETECT_SHIFT)) & SYSCON_ELS_AS_FLAG0_EFUSE_ATTACK_DETECT_MASK)
74993 
74994 #define SYSCON_ELS_AS_FLAG0_FLAG_LVD_CORE_OCCURED_MASK (0x20U)
74995 #define SYSCON_ELS_AS_FLAG0_FLAG_LVD_CORE_OCCURED_SHIFT (5U)
74996 /*! FLAG_LVD_CORE_OCCURED - This flag register is set 1 when VDD_CORE LVD event is triggered. This register is cleared 0 by PMC reset event.
74997  *  0b1..Triggered
74998  *  0b0..Not Triggered
74999  */
75000 #define SYSCON_ELS_AS_FLAG0_FLAG_LVD_CORE_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_LVD_CORE_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_LVD_CORE_OCCURED_MASK)
75001 
75002 #define SYSCON_ELS_AS_FLAG0_FLAG_WDT0_RESET_OCCURED_MASK (0x100U)
75003 #define SYSCON_ELS_AS_FLAG0_FLAG_WDT0_RESET_OCCURED_SHIFT (8U)
75004 /*! FLAG_WDT0_RESET_OCCURED - This flag bit is set as 1 when WatchDog Timer 0 reset is enabled and
75005  *    reset event is triggered. This register is cleared 0 by AO domain POR.
75006  *  0b1..Triggered
75007  *  0b0..Not Triggered
75008  */
75009 #define SYSCON_ELS_AS_FLAG0_FLAG_WDT0_RESET_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_WDT0_RESET_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_WDT0_RESET_OCCURED_MASK)
75010 
75011 #define SYSCON_ELS_AS_FLAG0_FLAG_CWDT0_RESET_OCCURED_MASK (0x200U)
75012 #define SYSCON_ELS_AS_FLAG0_FLAG_CWDT0_RESET_OCCURED_SHIFT (9U)
75013 /*! FLAG_CWDT0_RESET_OCCURED - This flag bit is set as 1 when Code WatchDog Timer 0 reset is enabled
75014  *    and reset event is triggered. This register is cleared 0 by AO domain POR.
75015  *  0b1..Triggered
75016  *  0b0..Not Triggered
75017  */
75018 #define SYSCON_ELS_AS_FLAG0_FLAG_CWDT0_RESET_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_CWDT0_RESET_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_CWDT0_RESET_OCCURED_MASK)
75019 
75020 #define SYSCON_ELS_AS_FLAG0_FLAG_WDT0_IRQ_OCCURED_MASK (0x400U)
75021 #define SYSCON_ELS_AS_FLAG0_FLAG_WDT0_IRQ_OCCURED_SHIFT (10U)
75022 /*! FLAG_WDT0_IRQ_OCCURED - This flag bit is set as 1 when WatchDog Timer 0 IRQ is enabled and IRQ
75023  *    event is triggered. This register is cleared 0 by PMC reset event.
75024  *  0b1..Triggered
75025  *  0b0..Not Triggered
75026  */
75027 #define SYSCON_ELS_AS_FLAG0_FLAG_WDT0_IRQ_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_WDT0_IRQ_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_WDT0_IRQ_OCCURED_MASK)
75028 
75029 #define SYSCON_ELS_AS_FLAG0_FLAG_CWDT0_IRQ_OCCURED_MASK (0x800U)
75030 #define SYSCON_ELS_AS_FLAG0_FLAG_CWDT0_IRQ_OCCURED_SHIFT (11U)
75031 /*! FLAG_CWDT0_IRQ_OCCURED - This flag bit is set as 1 when Code WatchDog Timer 0 IRQ is enabled and
75032  *    IRQ event is triggered. This register is cleared 0 by PMC reset event.
75033  *  0b1..Triggered
75034  *  0b0..Not Triggered
75035  */
75036 #define SYSCON_ELS_AS_FLAG0_FLAG_CWDT0_IRQ_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_CWDT0_IRQ_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_CWDT0_IRQ_OCCURED_MASK)
75037 
75038 #define SYSCON_ELS_AS_FLAG0_FLAG_QK_ERROR_MASK   (0x1000U)
75039 #define SYSCON_ELS_AS_FLAG0_FLAG_QK_ERROR_SHIFT  (12U)
75040 /*! FLAG_QK_ERROR - This flag bit is set as 1 when QK_ERROR is flagged from QK PUF block. This register is cleared 0 by PMC reset event.
75041  *  0b1..Triggered
75042  *  0b0..Not Triggered
75043  */
75044 #define SYSCON_ELS_AS_FLAG0_FLAG_QK_ERROR(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_QK_ERROR_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_QK_ERROR_MASK)
75045 
75046 #define SYSCON_ELS_AS_FLAG0_FLAG_ELS_GLITCH_DETECTED_MASK (0x2000U)
75047 #define SYSCON_ELS_AS_FLAG0_FLAG_ELS_GLITCH_DETECTED_SHIFT (13U)
75048 /*! FLAG_ELS_GLITCH_DETECTED - This flag bit is set as 1 when GDET error is flagged. This register is cleared 0 by PMC reset event.
75049  *  0b1..Triggered
75050  *  0b0..Not Triggered
75051  */
75052 #define SYSCON_ELS_AS_FLAG0_FLAG_ELS_GLITCH_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_ELS_GLITCH_DETECTED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_ELS_GLITCH_DETECTED_MASK)
75053 
75054 #define SYSCON_ELS_AS_FLAG0_FLAG_ANA_GLITCH_DETECTED_MASK (0x4000U)
75055 #define SYSCON_ELS_AS_FLAG0_FLAG_ANA_GLITCH_DETECTED_SHIFT (14U)
75056 /*! FLAG_ANA_GLITCH_DETECTED - This flag bit is set as 1 when ANALOG GDET error is flagged in SYSCON
75057  *    block. This register is cleared 0 by PMC reset event.
75058  *  0b1..Triggered
75059  *  0b0..Not Triggered
75060  */
75061 #define SYSCON_ELS_AS_FLAG0_FLAG_ANA_GLITCH_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_ANA_GLITCH_DETECTED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_ANA_GLITCH_DETECTED_MASK)
75062 
75063 #define SYSCON_ELS_AS_FLAG0_FLAG_TAMPER_EVENT_DETECTED_MASK (0x8000U)
75064 #define SYSCON_ELS_AS_FLAG0_FLAG_TAMPER_EVENT_DETECTED_SHIFT (15U)
75065 /*! FLAG_TAMPER_EVENT_DETECTED - This flag bit is set as 1 when tamper event is flagged from TDET.
75066  *    This register is cleared 0 by AO domain POR or by PMC reset event, if tamper detection event is
75067  *    cleared by software.
75068  *  0b1..Triggered
75069  *  0b0..Not Triggered
75070  */
75071 #define SYSCON_ELS_AS_FLAG0_FLAG_TAMPER_EVENT_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_TAMPER_EVENT_DETECTED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_TAMPER_EVENT_DETECTED_MASK)
75072 
75073 #define SYSCON_ELS_AS_FLAG0_FLAG_FLASH_ECC_INVALID_MASK (0x10000U)
75074 #define SYSCON_ELS_AS_FLAG0_FLAG_FLASH_ECC_INVALID_SHIFT (16U)
75075 /*! FLAG_FLASH_ECC_INVALID - This flag bit is set as 1 when FLASH controller indicates ECC error. This register is cleared 0 by PMC reset event.
75076  *  0b1..Triggered
75077  *  0b0..Not Triggered
75078  */
75079 #define SYSCON_ELS_AS_FLAG0_FLAG_FLASH_ECC_INVALID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_FLASH_ECC_INVALID_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_FLASH_ECC_INVALID_MASK)
75080 
75081 #define SYSCON_ELS_AS_FLAG0_FLAG_SEC_VIOL_IRQ_OCURRED_MASK (0x20000U)
75082 #define SYSCON_ELS_AS_FLAG0_FLAG_SEC_VIOL_IRQ_OCURRED_SHIFT (17U)
75083 /*! FLAG_SEC_VIOL_IRQ_OCURRED - This flag bit is set as 1 when security violation is indicated from FLASH sub-system or AHB bus matrix.
75084  *  0b1..Triggered
75085  *  0b0..Not Triggered
75086  */
75087 #define SYSCON_ELS_AS_FLAG0_FLAG_SEC_VIOL_IRQ_OCURRED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_SEC_VIOL_IRQ_OCURRED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_SEC_VIOL_IRQ_OCURRED_MASK)
75088 
75089 #define SYSCON_ELS_AS_FLAG0_FLAG_CPU0_NS_C_ACC_OCCURED_MASK (0x40000U)
75090 #define SYSCON_ELS_AS_FLAG0_FLAG_CPU0_NS_C_ACC_OCCURED_SHIFT (18U)
75091 /*! FLAG_CPU0_NS_C_ACC_OCCURED - This flag bit is set as 1 when CPU0 (CM33) makes non-secure code
75092  *    transactions. This register is cleared 0 by PMC reset event.
75093  *  0b1..Triggered
75094  *  0b0..Not Triggered
75095  */
75096 #define SYSCON_ELS_AS_FLAG0_FLAG_CPU0_NS_C_ACC_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_CPU0_NS_C_ACC_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_CPU0_NS_C_ACC_OCCURED_MASK)
75097 
75098 #define SYSCON_ELS_AS_FLAG0_FLAG_CPU0_NS_D_ACC_OCCURED_MASK (0x80000U)
75099 #define SYSCON_ELS_AS_FLAG0_FLAG_CPU0_NS_D_ACC_OCCURED_SHIFT (19U)
75100 /*! FLAG_CPU0_NS_D_ACC_OCCURED - This flag bit is set as 1 when CPU0 (CM33) makes non-secure data
75101  *    transactions. This register is cleared 0 by PMC reset event.
75102  *  0b1..Triggered
75103  *  0b0..Not Triggered
75104  */
75105 #define SYSCON_ELS_AS_FLAG0_FLAG_CPU0_NS_D_ACC_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_CPU0_NS_D_ACC_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_CPU0_NS_D_ACC_OCCURED_MASK)
75106 
75107 #define SYSCON_ELS_AS_FLAG0_FLAG_LVD_VSYS_OCCURED_MASK (0x100000U)
75108 #define SYSCON_ELS_AS_FLAG0_FLAG_LVD_VSYS_OCCURED_SHIFT (20U)
75109 /*! FLAG_LVD_VSYS_OCCURED - This flag register is set 1 when VDD_SYS LVD event is triggered. This register is cleared 0 by PMC reset event.
75110  *  0b1..Triggered
75111  *  0b0..Not Triggered
75112  */
75113 #define SYSCON_ELS_AS_FLAG0_FLAG_LVD_VSYS_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_LVD_VSYS_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_LVD_VSYS_OCCURED_MASK)
75114 
75115 #define SYSCON_ELS_AS_FLAG0_FLAG_LVD_VDDIO_OCCURED_MASK (0x200000U)
75116 #define SYSCON_ELS_AS_FLAG0_FLAG_LVD_VDDIO_OCCURED_SHIFT (21U)
75117 /*! FLAG_LVD_VDDIO_OCCURED - This flag register is set 1 when VDD LVD event is triggered. This register is cleared 0 by PMC reset event.
75118  *  0b1..Triggered
75119  *  0b0..Not Triggered
75120  */
75121 #define SYSCON_ELS_AS_FLAG0_FLAG_LVD_VDDIO_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_LVD_VDDIO_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_LVD_VDDIO_OCCURED_MASK)
75122 
75123 #define SYSCON_ELS_AS_FLAG0_FLAG_WDT1_RESET_OCCURED_MASK (0x400000U)
75124 #define SYSCON_ELS_AS_FLAG0_FLAG_WDT1_RESET_OCCURED_SHIFT (22U)
75125 /*! FLAG_WDT1_RESET_OCCURED - This flag bit is set as 1 when WatchDog Timer 1 reset is enabled and
75126  *    reset event is triggered. This register is cleared 0 by AO domain POR.
75127  *  0b1..Triggered
75128  *  0b0..Not Triggered
75129  */
75130 #define SYSCON_ELS_AS_FLAG0_FLAG_WDT1_RESET_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_WDT1_RESET_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_WDT1_RESET_OCCURED_MASK)
75131 
75132 #define SYSCON_ELS_AS_FLAG0_FLAG_CWDT1_RESET_OCCURED_MASK (0x800000U)
75133 #define SYSCON_ELS_AS_FLAG0_FLAG_CWDT1_RESET_OCCURED_SHIFT (23U)
75134 /*! FLAG_CWDT1_RESET_OCCURED - This flag bit is set as 1 when Code WatchDog Timer 1 reset is enabled
75135  *    and reset event is triggered. This register is cleared 0 by AO domain POR.
75136  *  0b1..Triggered
75137  *  0b0..Not Triggered
75138  */
75139 #define SYSCON_ELS_AS_FLAG0_FLAG_CWDT1_RESET_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_CWDT1_RESET_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_CWDT1_RESET_OCCURED_MASK)
75140 
75141 #define SYSCON_ELS_AS_FLAG0_FLAG_WDT1_IRQ_OCCURED_MASK (0x1000000U)
75142 #define SYSCON_ELS_AS_FLAG0_FLAG_WDT1_IRQ_OCCURED_SHIFT (24U)
75143 /*! FLAG_WDT1_IRQ_OCCURED - This flag bit is set as 1 when WatchDog Timer 1 IRQ is enabled and IRQ
75144  *    event is triggered. This register is cleared 0 by PMC reset event.
75145  *  0b1..Triggered
75146  *  0b0..Not Triggered
75147  */
75148 #define SYSCON_ELS_AS_FLAG0_FLAG_WDT1_IRQ_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_WDT1_IRQ_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_WDT1_IRQ_OCCURED_MASK)
75149 
75150 #define SYSCON_ELS_AS_FLAG0_FLAG_CWDT1_IRQ_OCCURED_MASK (0x2000000U)
75151 #define SYSCON_ELS_AS_FLAG0_FLAG_CWDT1_IRQ_OCCURED_SHIFT (25U)
75152 /*! FLAG_CWDT1_IRQ_OCCURED - This flag bit is set as 1 when Code WatchDog Timer 1 IRQ is enabled and
75153  *    IRQ event is triggered. This register is cleared 0 by PMC reset event.
75154  *  0b1..Triggered
75155  *  0b0..Not Triggered
75156  */
75157 #define SYSCON_ELS_AS_FLAG0_FLAG_CWDT1_IRQ_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_CWDT1_IRQ_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_CWDT1_IRQ_OCCURED_MASK)
75158 
75159 #define SYSCON_ELS_AS_FLAG0_FLAG_TEMPTAMPER_DET_IRQ_OCCURED_MASK (0x4000000U)
75160 #define SYSCON_ELS_AS_FLAG0_FLAG_TEMPTAMPER_DET_IRQ_OCCURED_SHIFT (26U)
75161 /*! FLAG_TEMPTAMPER_DET_IRQ_OCCURED - This flag bit is set as 1 when temperature temper IRQ is
75162  *    enabled and IRQ event is triggered. This register is cleared 0 by PMC reset event.
75163  *  0b1..Triggered
75164  *  0b0..Not Triggered
75165  */
75166 #define SYSCON_ELS_AS_FLAG0_FLAG_TEMPTAMPER_DET_IRQ_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_TEMPTAMPER_DET_IRQ_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_TEMPTAMPER_DET_IRQ_OCCURED_MASK)
75167 
75168 #define SYSCON_ELS_AS_FLAG0_FLAG_VOLTAMPER_DET_IRQ_OCCURED_MASK (0x8000000U)
75169 #define SYSCON_ELS_AS_FLAG0_FLAG_VOLTAMPER_DET_IRQ_OCCURED_SHIFT (27U)
75170 /*! FLAG_VOLTAMPER_DET_IRQ_OCCURED - This flag bit is set as 1 when voltage temper IRQ is enabled
75171  *    and IRQ event is triggered. This register is cleared 0 by PMC reset event.
75172  *  0b1..Triggered
75173  *  0b0..Not Triggered
75174  */
75175 #define SYSCON_ELS_AS_FLAG0_FLAG_VOLTAMPER_DET_IRQ_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_VOLTAMPER_DET_IRQ_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_VOLTAMPER_DET_IRQ_OCCURED_MASK)
75176 
75177 #define SYSCON_ELS_AS_FLAG0_FLAG_LHTTAMPER_DET_IRQ_OCCURED_MASK (0x10000000U)
75178 #define SYSCON_ELS_AS_FLAG0_FLAG_LHTTAMPER_DET_IRQ_OCCURED_SHIFT (28U)
75179 /*! FLAG_LHTTAMPER_DET_IRQ_OCCURED - This flag bit is set as 1 when light temper IRQ is enabled and
75180  *    IRQ event is triggered. This register is cleared 0 by PMC reset event.
75181  *  0b1..Triggered
75182  *  0b0..Not Triggered
75183  */
75184 #define SYSCON_ELS_AS_FLAG0_FLAG_LHTTAMPER_DET_IRQ_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_LHTTAMPER_DET_IRQ_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_LHTTAMPER_DET_IRQ_OCCURED_MASK)
75185 
75186 #define SYSCON_ELS_AS_FLAG0_FLAG_CLKTAMPER_DET_IRQ_OCCURED_MASK (0x20000000U)
75187 #define SYSCON_ELS_AS_FLAG0_FLAG_CLKTAMPER_DET_IRQ_OCCURED_SHIFT (29U)
75188 /*! FLAG_CLKTAMPER_DET_IRQ_OCCURED - This flag bit is set as 1 when clock temper IRQ is enabled and
75189  *    IRQ event is triggered. This register is cleared 0 by PMC reset event.
75190  *  0b1..Triggered
75191  *  0b0..Not Triggered
75192  */
75193 #define SYSCON_ELS_AS_FLAG0_FLAG_CLKTAMPER_DET_IRQ_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_CLKTAMPER_DET_IRQ_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_CLKTAMPER_DET_IRQ_OCCURED_MASK)
75194 /*! @} */
75195 
75196 /*! @name ELS_AS_FLAG1 - ELS AS Flag1 */
75197 /*! @{ */
75198 
75199 #define SYSCON_ELS_AS_FLAG1_FLAG_HVD_CORE_OCCURED_MASK (0x20000000U)
75200 #define SYSCON_ELS_AS_FLAG1_FLAG_HVD_CORE_OCCURED_SHIFT (29U)
75201 /*! FLAG_HVD_CORE_OCCURED - This flag bit is set as 1 when HVD from VDD_CORE power domain is triggered.
75202  *  0b1..Triggered
75203  *  0b0..Not Triggered
75204  */
75205 #define SYSCON_ELS_AS_FLAG1_FLAG_HVD_CORE_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG1_FLAG_HVD_CORE_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG1_FLAG_HVD_CORE_OCCURED_MASK)
75206 
75207 #define SYSCON_ELS_AS_FLAG1_FLAG_HVD_VSYS_OCCURED_MASK (0x40000000U)
75208 #define SYSCON_ELS_AS_FLAG1_FLAG_HVD_VSYS_OCCURED_SHIFT (30U)
75209 /*! FLAG_HVD_VSYS_OCCURED - This flag bit is set as 1 when HVD from VDD_SYS power domain is triggered
75210  *  0b1..Triggered
75211  *  0b0..Not Triggered
75212  */
75213 #define SYSCON_ELS_AS_FLAG1_FLAG_HVD_VSYS_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG1_FLAG_HVD_VSYS_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG1_FLAG_HVD_VSYS_OCCURED_MASK)
75214 
75215 #define SYSCON_ELS_AS_FLAG1_FLAG_HVD_VDDIO_OCCURED_MASK (0x80000000U)
75216 #define SYSCON_ELS_AS_FLAG1_FLAG_HVD_VDDIO_OCCURED_SHIFT (31U)
75217 /*! FLAG_HVD_VDDIO_OCCURED - This flag bit is set as 1 when HVD from VDD power domain is triggered
75218  *  0b1..Triggered
75219  *  0b0..Not Triggered
75220  */
75221 #define SYSCON_ELS_AS_FLAG1_FLAG_HVD_VDDIO_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG1_FLAG_HVD_VDDIO_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG1_FLAG_HVD_VDDIO_OCCURED_MASK)
75222 /*! @} */
75223 
75224 /*! @name CLOCK_CTRL - Clock Control */
75225 /*! @{ */
75226 
75227 #define SYSCON_CLOCK_CTRL_CLKIN_ENA_FM_USBH_LPT_MASK (0x2U)
75228 #define SYSCON_CLOCK_CTRL_CLKIN_ENA_FM_USBH_LPT_SHIFT (1U)
75229 /*! CLKIN_ENA_FM_USBH_LPT - Enables the clk_in clock for the Frequency Measurement, USB HS and LPTMR0/1 modules.
75230  *  0b1..Clock is enabled
75231  *  0b0..Clock is not enabled
75232  */
75233 #define SYSCON_CLOCK_CTRL_CLKIN_ENA_FM_USBH_LPT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_CLKIN_ENA_FM_USBH_LPT_SHIFT)) & SYSCON_CLOCK_CTRL_CLKIN_ENA_FM_USBH_LPT_MASK)
75234 
75235 #define SYSCON_CLOCK_CTRL_FRO1MHZ_ENA_MASK       (0x4U)
75236 #define SYSCON_CLOCK_CTRL_FRO1MHZ_ENA_SHIFT      (2U)
75237 /*! FRO1MHZ_ENA - Enables the FRO_1MHz clock for RTC module and for UTICK
75238  *  0b1..Clock is enabled
75239  *  0b0..Clock is not enabled
75240  */
75241 #define SYSCON_CLOCK_CTRL_FRO1MHZ_ENA(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO1MHZ_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO1MHZ_ENA_MASK)
75242 
75243 #define SYSCON_CLOCK_CTRL_FRO12MHZ_ENA_MASK      (0x8U)
75244 #define SYSCON_CLOCK_CTRL_FRO12MHZ_ENA_SHIFT     (3U)
75245 /*! FRO12MHZ_ENA - Enables the FRO_12MHz clock for the Flash, LPTMR0/1, and Frequency Measurement modules
75246  *  0b1..Clock is enabled
75247  *  0b0..Clock is not enabled
75248  */
75249 #define SYSCON_CLOCK_CTRL_FRO12MHZ_ENA(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO12MHZ_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO12MHZ_ENA_MASK)
75250 
75251 #define SYSCON_CLOCK_CTRL_FRO_HF_ENA_MASK        (0x10U)
75252 #define SYSCON_CLOCK_CTRL_FRO_HF_ENA_SHIFT       (4U)
75253 /*! FRO_HF_ENA - Enables FRO HF clock for the Frequency Measure module
75254  *  0b1..Clock is enabled
75255  *  0b0..Clock is not enabled
75256  */
75257 #define SYSCON_CLOCK_CTRL_FRO_HF_ENA(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO_HF_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO_HF_ENA_MASK)
75258 
75259 #define SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK         (0x20U)
75260 #define SYSCON_CLOCK_CTRL_CLKIN_ENA_SHIFT        (5U)
75261 /*! CLKIN_ENA - Enables clk_in clock for MICFIL, CAN0/1, I3C0/1, SAI0/1, clkout.
75262  *  0b1..Clock is enabled
75263  *  0b0..Clock is not enabled
75264  */
75265 #define SYSCON_CLOCK_CTRL_CLKIN_ENA(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_CLKIN_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK)
75266 
75267 #define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK   (0x40U)
75268 #define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_SHIFT  (6U)
75269 /*! FRO1MHZ_CLK_ENA - Enables FRO_1MHz clock for clock muxing in clock gen
75270  *  0b1..Clock is enabled
75271  *  0b0..Clock is not enabled
75272  */
75273 #define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK)
75274 
75275 #define SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_MASK (0x200U)
75276 #define SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_SHIFT (9U)
75277 /*! PLU_DEGLITCH_CLK_ENA - Enables clocks FRO_1MHz and FRO_12MHz for PLU deglitching.
75278  *  0b1..Clock is enabled
75279  *  0b0..Clock is not enabled
75280  */
75281 #define SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_MASK)
75282 /*! @} */
75283 
75284 /*! @name I3C1FCLKSEL - I3C1 Functional Clock Selection */
75285 /*! @{ */
75286 
75287 #define SYSCON_I3C1FCLKSEL_SEL_MASK              (0x7U)
75288 #define SYSCON_I3C1FCLKSEL_SEL_SHIFT             (0U)
75289 /*! SEL - I3C1 clock select
75290  *  0b000..No clock
75291  *  0b001..PLL0 clock
75292  *  0b010..CLKIN clock
75293  *  0b011..FRO_HF clock
75294  *  0b100..No clock
75295  *  0b101..PLL1_clk0 clock
75296  *  0b110..USB PLL clock
75297  *  0b111..No clock
75298  */
75299 #define SYSCON_I3C1FCLKSEL_SEL(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C1FCLKSEL_SEL_SHIFT)) & SYSCON_I3C1FCLKSEL_SEL_MASK)
75300 /*! @} */
75301 
75302 /*! @name I3C1FCLKSTCSEL - Selects the I3C1 Time Control clock */
75303 /*! @{ */
75304 
75305 #define SYSCON_I3C1FCLKSTCSEL_SEL_MASK           (0x7U)
75306 #define SYSCON_I3C1FCLKSTCSEL_SEL_SHIFT          (0U)
75307 /*! SEL - I3C1 FCLK_STC clock select
75308  *  0b000..I3C1 functional clock I3C1FCLK
75309  *  0b001..FRO_1M clock
75310  *  0b010..No clock
75311  *  0b011..No clock
75312  *  0b100..No clock
75313  *  0b101..No clock
75314  *  0b110..No clock
75315  *  0b111..No clock
75316  */
75317 #define SYSCON_I3C1FCLKSTCSEL_SEL(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C1FCLKSTCSEL_SEL_SHIFT)) & SYSCON_I3C1FCLKSTCSEL_SEL_MASK)
75318 /*! @} */
75319 
75320 /*! @name I3C1FCLKSTCDIV - I3C1 FCLK_STC Clock Divider */
75321 /*! @{ */
75322 
75323 #define SYSCON_I3C1FCLKSTCDIV_DIV_MASK           (0xFFU)
75324 #define SYSCON_I3C1FCLKSTCDIV_DIV_SHIFT          (0U)
75325 /*! DIV - Clock divider value */
75326 #define SYSCON_I3C1FCLKSTCDIV_DIV(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C1FCLKSTCDIV_DIV_SHIFT)) & SYSCON_I3C1FCLKSTCDIV_DIV_MASK)
75327 
75328 #define SYSCON_I3C1FCLKSTCDIV_RESET_MASK         (0x20000000U)
75329 #define SYSCON_I3C1FCLKSTCDIV_RESET_SHIFT        (29U)
75330 /*! RESET - Resets the divider counter
75331  *  0b1..Divider is reset
75332  *  0b0..Divider is not reset
75333  */
75334 #define SYSCON_I3C1FCLKSTCDIV_RESET(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C1FCLKSTCDIV_RESET_SHIFT)) & SYSCON_I3C1FCLKSTCDIV_RESET_MASK)
75335 
75336 #define SYSCON_I3C1FCLKSTCDIV_HALT_MASK          (0x40000000U)
75337 #define SYSCON_I3C1FCLKSTCDIV_HALT_SHIFT         (30U)
75338 /*! HALT - Halts the divider counter
75339  *  0b1..Divider clock is stopped
75340  *  0b0..Divider clock is running
75341  */
75342 #define SYSCON_I3C1FCLKSTCDIV_HALT(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C1FCLKSTCDIV_HALT_SHIFT)) & SYSCON_I3C1FCLKSTCDIV_HALT_MASK)
75343 
75344 #define SYSCON_I3C1FCLKSTCDIV_UNSTAB_MASK        (0x80000000U)
75345 #define SYSCON_I3C1FCLKSTCDIV_UNSTAB_SHIFT       (31U)
75346 /*! UNSTAB - Divider status flag
75347  *  0b1..Clock frequency is not stable
75348  *  0b0..Divider clock is stable
75349  */
75350 #define SYSCON_I3C1FCLKSTCDIV_UNSTAB(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C1FCLKSTCDIV_UNSTAB_SHIFT)) & SYSCON_I3C1FCLKSTCDIV_UNSTAB_MASK)
75351 /*! @} */
75352 
75353 /*! @name I3C1FCLKSDIV - I3C1 FCLK Slow clock Divider */
75354 /*! @{ */
75355 
75356 #define SYSCON_I3C1FCLKSDIV_DIV_MASK             (0xFFU)
75357 #define SYSCON_I3C1FCLKSDIV_DIV_SHIFT            (0U)
75358 /*! DIV - Clock divider value */
75359 #define SYSCON_I3C1FCLKSDIV_DIV(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C1FCLKSDIV_DIV_SHIFT)) & SYSCON_I3C1FCLKSDIV_DIV_MASK)
75360 
75361 #define SYSCON_I3C1FCLKSDIV_RESET_MASK           (0x20000000U)
75362 #define SYSCON_I3C1FCLKSDIV_RESET_SHIFT          (29U)
75363 /*! RESET - Resets the divider counter
75364  *  0b1..Divider is reset
75365  *  0b0..Divider is not reset
75366  */
75367 #define SYSCON_I3C1FCLKSDIV_RESET(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C1FCLKSDIV_RESET_SHIFT)) & SYSCON_I3C1FCLKSDIV_RESET_MASK)
75368 
75369 #define SYSCON_I3C1FCLKSDIV_HALT_MASK            (0x40000000U)
75370 #define SYSCON_I3C1FCLKSDIV_HALT_SHIFT           (30U)
75371 /*! HALT - Halts the divider counter
75372  *  0b1..Divider clock is stopped
75373  *  0b0..Divider clock is running
75374  */
75375 #define SYSCON_I3C1FCLKSDIV_HALT(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C1FCLKSDIV_HALT_SHIFT)) & SYSCON_I3C1FCLKSDIV_HALT_MASK)
75376 
75377 #define SYSCON_I3C1FCLKSDIV_UNSTAB_MASK          (0x80000000U)
75378 #define SYSCON_I3C1FCLKSDIV_UNSTAB_SHIFT         (31U)
75379 /*! UNSTAB - Divider status flag
75380  *  0b1..Clock frequency is not stable
75381  *  0b0..Divider clock is stable
75382  */
75383 #define SYSCON_I3C1FCLKSDIV_UNSTAB(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C1FCLKSDIV_UNSTAB_SHIFT)) & SYSCON_I3C1FCLKSDIV_UNSTAB_MASK)
75384 /*! @} */
75385 
75386 /*! @name I3C1FCLKDIV - I3C1 Functional Clock FCLK Divider */
75387 /*! @{ */
75388 
75389 #define SYSCON_I3C1FCLKDIV_DIV_MASK              (0xFFU)
75390 #define SYSCON_I3C1FCLKDIV_DIV_SHIFT             (0U)
75391 /*! DIV - Clock divider value */
75392 #define SYSCON_I3C1FCLKDIV_DIV(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C1FCLKDIV_DIV_SHIFT)) & SYSCON_I3C1FCLKDIV_DIV_MASK)
75393 
75394 #define SYSCON_I3C1FCLKDIV_RESET_MASK            (0x20000000U)
75395 #define SYSCON_I3C1FCLKDIV_RESET_SHIFT           (29U)
75396 /*! RESET - Resets the divider counter
75397  *  0b1..Divider is reset
75398  *  0b0..Divider is not reset
75399  */
75400 #define SYSCON_I3C1FCLKDIV_RESET(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C1FCLKDIV_RESET_SHIFT)) & SYSCON_I3C1FCLKDIV_RESET_MASK)
75401 
75402 #define SYSCON_I3C1FCLKDIV_HALT_MASK             (0x40000000U)
75403 #define SYSCON_I3C1FCLKDIV_HALT_SHIFT            (30U)
75404 /*! HALT - Halts the divider counter
75405  *  0b1..Divider clock is stopped
75406  *  0b0..Divider clock is running
75407  */
75408 #define SYSCON_I3C1FCLKDIV_HALT(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C1FCLKDIV_HALT_SHIFT)) & SYSCON_I3C1FCLKDIV_HALT_MASK)
75409 
75410 #define SYSCON_I3C1FCLKDIV_UNSTAB_MASK           (0x80000000U)
75411 #define SYSCON_I3C1FCLKDIV_UNSTAB_SHIFT          (31U)
75412 /*! UNSTAB - Divider status flag
75413  *  0b1..Clock frequency is not stable
75414  *  0b0..Divider clock is stable
75415  */
75416 #define SYSCON_I3C1FCLKDIV_UNSTAB(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C1FCLKDIV_UNSTAB_SHIFT)) & SYSCON_I3C1FCLKDIV_UNSTAB_MASK)
75417 /*! @} */
75418 
75419 /*! @name I3C1FCLKSSEL - I3C1 FCLK Slow Selection */
75420 /*! @{ */
75421 
75422 #define SYSCON_I3C1FCLKSSEL_SEL_MASK             (0x7U)
75423 #define SYSCON_I3C1FCLKSSEL_SEL_SHIFT            (0U)
75424 /*! SEL - I3C1 FCLK Slow Clock Select
75425  *  0b000..FRO_1M clock
75426  *  0b001..No clock
75427  *  0b010..No clock
75428  *  0b011..No clock
75429  *  0b100..No clock
75430  *  0b101..No clock
75431  *  0b110..No clock
75432  *  0b111..No clock
75433  */
75434 #define SYSCON_I3C1FCLKSSEL_SEL(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C1FCLKSSEL_SEL_SHIFT)) & SYSCON_I3C1FCLKSSEL_SEL_MASK)
75435 /*! @} */
75436 
75437 /*! @name ETB_STATUS - ETB Counter Status Register */
75438 /*! @{ */
75439 
75440 #define SYSCON_ETB_STATUS_IRQ_MASK               (0x2U)
75441 #define SYSCON_ETB_STATUS_IRQ_SHIFT              (1U)
75442 /*! IRQ - ETB Interrupt
75443  *  0b1..ETB interrupt is asserted when ETB count expires. Write 1 to clear it.
75444  *  0b0..ETB interrupt is not asserted
75445  */
75446 #define SYSCON_ETB_STATUS_IRQ(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_ETB_STATUS_IRQ_SHIFT)) & SYSCON_ETB_STATUS_IRQ_MASK)
75447 
75448 #define SYSCON_ETB_STATUS_NMI_MASK               (0x4U)
75449 #define SYSCON_ETB_STATUS_NMI_SHIFT              (2U)
75450 /*! NMI - ETB NMI
75451  *  0b1..ETB NMI is asserted. Write 1 to clear it.
75452  *  0b0..ETB NMI is not asserted
75453  */
75454 #define SYSCON_ETB_STATUS_NMI(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_ETB_STATUS_NMI_SHIFT)) & SYSCON_ETB_STATUS_NMI_MASK)
75455 
75456 #define SYSCON_ETB_STATUS_DBG_HALT_REQ_MASK      (0x8U)
75457 #define SYSCON_ETB_STATUS_DBG_HALT_REQ_SHIFT     (3U)
75458 /*! DBG_HALT_REQ - Debug halt request
75459  *  0b1..The debug halt request signal is asserted when the ETB count expires
75460  *  0b0..The debug halt request signal is not asserted
75461  */
75462 #define SYSCON_ETB_STATUS_DBG_HALT_REQ(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_ETB_STATUS_DBG_HALT_REQ_SHIFT)) & SYSCON_ETB_STATUS_DBG_HALT_REQ_MASK)
75463 /*! @} */
75464 
75465 /*! @name ETB_COUNTER_CTRL - ETB Counter Control Register */
75466 /*! @{ */
75467 
75468 #define SYSCON_ETB_COUNTER_CTRL_CNTEN_MASK       (0x1U)
75469 #define SYSCON_ETB_COUNTER_CTRL_CNTEN_SHIFT      (0U)
75470 /*! CNTEN - Enables the ETB counter
75471  *  0b1..ETB counter is enabled
75472  *  0b0..ETB counter is disabled
75473  */
75474 #define SYSCON_ETB_COUNTER_CTRL_CNTEN(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_ETB_COUNTER_CTRL_CNTEN_SHIFT)) & SYSCON_ETB_COUNTER_CTRL_CNTEN_MASK)
75475 
75476 #define SYSCON_ETB_COUNTER_CTRL_RSPT_MASK        (0x6U)
75477 #define SYSCON_ETB_COUNTER_CTRL_RSPT_SHIFT       (1U)
75478 /*! RSPT - Response Type
75479  *  0b11..Generates a debug halt when the ETB count expires via CPU0 CTICHIN[2]
75480  *  0b10..Generates an NMI interrupt when the ETB count expires
75481  *  0b01..Generates a normal interrupt when the ETB count expires
75482  *  0b00..No response when the ETB count expires
75483  */
75484 #define SYSCON_ETB_COUNTER_CTRL_RSPT(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_ETB_COUNTER_CTRL_RSPT_SHIFT)) & SYSCON_ETB_COUNTER_CTRL_RSPT_MASK)
75485 
75486 #define SYSCON_ETB_COUNTER_CTRL_RLRQ_MASK        (0x8U)
75487 #define SYSCON_ETB_COUNTER_CTRL_RLRQ_SHIFT       (3U)
75488 /*! RLRQ - Reload request
75489  *  0b1..Clears pending debug halt, NMI, or IRQ interrupt requests
75490  *  0b0..No effect
75491  */
75492 #define SYSCON_ETB_COUNTER_CTRL_RLRQ(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_ETB_COUNTER_CTRL_RLRQ_SHIFT)) & SYSCON_ETB_COUNTER_CTRL_RLRQ_MASK)
75493 /*! @} */
75494 
75495 /*! @name ETB_COUNTER_RELOAD - ETB Counter Reload Register */
75496 /*! @{ */
75497 
75498 #define SYSCON_ETB_COUNTER_RELOAD_RELOAD_MASK    (0x7FFU)
75499 #define SYSCON_ETB_COUNTER_RELOAD_RELOAD_SHIFT   (0U)
75500 /*! RELOAD - Byte count reload value */
75501 #define SYSCON_ETB_COUNTER_RELOAD_RELOAD(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_ETB_COUNTER_RELOAD_RELOAD_SHIFT)) & SYSCON_ETB_COUNTER_RELOAD_RELOAD_MASK)
75502 /*! @} */
75503 
75504 /*! @name ETB_COUNTER_VALUE - ETB Counter Value Register */
75505 /*! @{ */
75506 
75507 #define SYSCON_ETB_COUNTER_VALUE_COUNTER_VALUE_MASK (0x7FFU)
75508 #define SYSCON_ETB_COUNTER_VALUE_COUNTER_VALUE_SHIFT (0U)
75509 /*! COUNTER_VALUE - Byte count counter value */
75510 #define SYSCON_ETB_COUNTER_VALUE_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ETB_COUNTER_VALUE_COUNTER_VALUE_SHIFT)) & SYSCON_ETB_COUNTER_VALUE_COUNTER_VALUE_MASK)
75511 /*! @} */
75512 
75513 /*! @name GRAY_CODE_LSB - Gray to Binary Converter Gray code_gray[31:0] */
75514 /*! @{ */
75515 
75516 #define SYSCON_GRAY_CODE_LSB_code_gray_31_0_MASK (0xFFFFFFFFU)
75517 #define SYSCON_GRAY_CODE_LSB_code_gray_31_0_SHIFT (0U)
75518 /*! code_gray_31_0 - Gray code [31:0] */
75519 #define SYSCON_GRAY_CODE_LSB_code_gray_31_0(x)   (((uint32_t)(((uint32_t)(x)) << SYSCON_GRAY_CODE_LSB_code_gray_31_0_SHIFT)) & SYSCON_GRAY_CODE_LSB_code_gray_31_0_MASK)
75520 /*! @} */
75521 
75522 /*! @name GRAY_CODE_MSB - Gray to Binary Converter Gray code_gray[41:32] */
75523 /*! @{ */
75524 
75525 #define SYSCON_GRAY_CODE_MSB_code_gray_41_32_MASK (0x3FFU)
75526 #define SYSCON_GRAY_CODE_MSB_code_gray_41_32_SHIFT (0U)
75527 /*! code_gray_41_32 - Gray code [41:32] */
75528 #define SYSCON_GRAY_CODE_MSB_code_gray_41_32(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON_GRAY_CODE_MSB_code_gray_41_32_SHIFT)) & SYSCON_GRAY_CODE_MSB_code_gray_41_32_MASK)
75529 /*! @} */
75530 
75531 /*! @name BINARY_CODE_LSB - Gray to Binary Converter Binary Code [31:0] */
75532 /*! @{ */
75533 
75534 #define SYSCON_BINARY_CODE_LSB_code_bin_31_0_MASK (0xFFFFFFFFU)
75535 #define SYSCON_BINARY_CODE_LSB_code_bin_31_0_SHIFT (0U)
75536 /*! code_bin_31_0 - Binary code [31:0] */
75537 #define SYSCON_BINARY_CODE_LSB_code_bin_31_0(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON_BINARY_CODE_LSB_code_bin_31_0_SHIFT)) & SYSCON_BINARY_CODE_LSB_code_bin_31_0_MASK)
75538 /*! @} */
75539 
75540 /*! @name BINARY_CODE_MSB - Gray to Binary Converter Binary Code [41:32] */
75541 /*! @{ */
75542 
75543 #define SYSCON_BINARY_CODE_MSB_code_bin_41_32_MASK (0x3FFU)
75544 #define SYSCON_BINARY_CODE_MSB_code_bin_41_32_SHIFT (0U)
75545 /*! code_bin_41_32 - Binary code [41:32] */
75546 #define SYSCON_BINARY_CODE_MSB_code_bin_41_32(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BINARY_CODE_MSB_code_bin_41_32_SHIFT)) & SYSCON_BINARY_CODE_MSB_code_bin_41_32_MASK)
75547 /*! @} */
75548 
75549 /*! @name AUTOCLKGATEOVERRIDE - Control Automatic Clock Gating */
75550 /*! @{ */
75551 
75552 #define SYSCON_AUTOCLKGATEOVERRIDE_RAMB_CTRL_MASK (0x4U)
75553 #define SYSCON_AUTOCLKGATEOVERRIDE_RAMB_CTRL_SHIFT (2U)
75554 /*! RAMB_CTRL - Controls automatic clock gating for the RAMB Controller
75555  *  0b1..Automatic clock gating is overridden (Automatic clock gating is disabled).
75556  *  0b0..Automatic clock gating is not overridden
75557  */
75558 #define SYSCON_AUTOCLKGATEOVERRIDE_RAMB_CTRL(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAMB_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAMB_CTRL_MASK)
75559 
75560 #define SYSCON_AUTOCLKGATEOVERRIDE_RAMC_CTRL_MASK (0x8U)
75561 #define SYSCON_AUTOCLKGATEOVERRIDE_RAMC_CTRL_SHIFT (3U)
75562 /*! RAMC_CTRL - Controls automatic clock gating for the RAMC Controller
75563  *  0b1..Automatic clock gating is overridden (Automatic clock gating is disabled).
75564  *  0b0..Automatic clock gating is not overridden
75565  */
75566 #define SYSCON_AUTOCLKGATEOVERRIDE_RAMC_CTRL(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAMC_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAMC_CTRL_MASK)
75567 
75568 #define SYSCON_AUTOCLKGATEOVERRIDE_RAMD_CTRL_MASK (0x10U)
75569 #define SYSCON_AUTOCLKGATEOVERRIDE_RAMD_CTRL_SHIFT (4U)
75570 /*! RAMD_CTRL - Controls automatic clock gating for the RAMD Controller
75571  *  0b1..Automatic clock gating is overridden (Automatic clock gating is disabled).
75572  *  0b0..Automatic clock gating is not overridden
75573  */
75574 #define SYSCON_AUTOCLKGATEOVERRIDE_RAMD_CTRL(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAMD_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAMD_CTRL_MASK)
75575 
75576 #define SYSCON_AUTOCLKGATEOVERRIDE_RAME_CTRL_MASK (0x20U)
75577 #define SYSCON_AUTOCLKGATEOVERRIDE_RAME_CTRL_SHIFT (5U)
75578 /*! RAME_CTRL - Controls automatic clock gating for the RAMD Controller.
75579  *  0b1..Automatic clock gating is overridden (Automatic clock gating is disabled).
75580  *  0b0..Automatic clock gating is not overridden
75581  */
75582 #define SYSCON_AUTOCLKGATEOVERRIDE_RAME_CTRL(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAME_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAME_CTRL_MASK)
75583 
75584 #define SYSCON_AUTOCLKGATEOVERRIDE_RAMF_CTRL_MASK (0x40U)
75585 #define SYSCON_AUTOCLKGATEOVERRIDE_RAMF_CTRL_SHIFT (6U)
75586 /*! RAMF_CTRL - Controls automatic clock gating for the RAMF Controller
75587  *  0b1..Automatic clock gating is overridden (Automatic clock gating is disabled).
75588  *  0b0..Automatic clock gating is not overridden
75589  */
75590 #define SYSCON_AUTOCLKGATEOVERRIDE_RAMF_CTRL(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAMF_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAMF_CTRL_MASK)
75591 
75592 #define SYSCON_AUTOCLKGATEOVERRIDE_RAMG_CTRL_MASK (0x80U)
75593 #define SYSCON_AUTOCLKGATEOVERRIDE_RAMG_CTRL_SHIFT (7U)
75594 /*! RAMG_CTRL - Controls automatic clock gating for the RAMG Controller
75595  *  0b1..Automatic clock gating is overridden (Automatic clock gating is disabled).
75596  *  0b0..Automatic clock gating is not overridden
75597  */
75598 #define SYSCON_AUTOCLKGATEOVERRIDE_RAMG_CTRL(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAMG_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAMG_CTRL_MASK)
75599 
75600 #define SYSCON_AUTOCLKGATEOVERRIDE_RAMH_CTRL_MASK (0x100U)
75601 #define SYSCON_AUTOCLKGATEOVERRIDE_RAMH_CTRL_SHIFT (8U)
75602 /*! RAMH_CTRL - Controls automatic clock gating for the RAMG Controller
75603  *  0b1..Automatic clock gating is overridden (Automatic clock gating is disabled).
75604  *  0b0..Automatic clock gating is not overridden
75605  */
75606 #define SYSCON_AUTOCLKGATEOVERRIDE_RAMH_CTRL(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAMH_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAMH_CTRL_MASK)
75607 /*! @} */
75608 
75609 /*! @name AUTOCLKGATEOVERRIDEC - Control Automatic Clock Gating C */
75610 /*! @{ */
75611 
75612 #define SYSCON_AUTOCLKGATEOVERRIDEC_RAMX_MASK    (0x40000000U)
75613 #define SYSCON_AUTOCLKGATEOVERRIDEC_RAMX_SHIFT   (30U)
75614 /*! RAMX - Controls automatic clock gating of the RAMX controller
75615  *  0b1..Automatic clock gating is overridden (Automatic clock gating is disabled).
75616  *  0b0..Automatic clock gating is not overridden
75617  */
75618 #define SYSCON_AUTOCLKGATEOVERRIDEC_RAMX(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDEC_RAMX_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDEC_RAMX_MASK)
75619 
75620 #define SYSCON_AUTOCLKGATEOVERRIDEC_RAMA_MASK    (0x80000000U)
75621 #define SYSCON_AUTOCLKGATEOVERRIDEC_RAMA_SHIFT   (31U)
75622 /*! RAMA - Controls automatic clock gating of the RAMA controller
75623  *  0b1..Automatic clock gating is overridden (Automatic clock gating is disabled).
75624  *  0b0..Automatic clock gating is not overridden
75625  */
75626 #define SYSCON_AUTOCLKGATEOVERRIDEC_RAMA(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDEC_RAMA_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDEC_RAMA_MASK)
75627 /*! @} */
75628 
75629 /*! @name PWM0SUBCTL - PWM0 Submodule Control */
75630 /*! @{ */
75631 
75632 #define SYSCON_PWM0SUBCTL_CLK0_EN_MASK           (0x1U)
75633 #define SYSCON_PWM0SUBCTL_CLK0_EN_SHIFT          (0U)
75634 /*! CLK0_EN - Enables PWM0 SUB Clock0 */
75635 #define SYSCON_PWM0SUBCTL_CLK0_EN(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM0SUBCTL_CLK0_EN_SHIFT)) & SYSCON_PWM0SUBCTL_CLK0_EN_MASK)
75636 
75637 #define SYSCON_PWM0SUBCTL_CLK1_EN_MASK           (0x2U)
75638 #define SYSCON_PWM0SUBCTL_CLK1_EN_SHIFT          (1U)
75639 /*! CLK1_EN - Enables PWM0 SUB Clock1 */
75640 #define SYSCON_PWM0SUBCTL_CLK1_EN(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM0SUBCTL_CLK1_EN_SHIFT)) & SYSCON_PWM0SUBCTL_CLK1_EN_MASK)
75641 
75642 #define SYSCON_PWM0SUBCTL_CLK2_EN_MASK           (0x4U)
75643 #define SYSCON_PWM0SUBCTL_CLK2_EN_SHIFT          (2U)
75644 /*! CLK2_EN - Enables PWM0 SUB Clock2 */
75645 #define SYSCON_PWM0SUBCTL_CLK2_EN(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM0SUBCTL_CLK2_EN_SHIFT)) & SYSCON_PWM0SUBCTL_CLK2_EN_MASK)
75646 
75647 #define SYSCON_PWM0SUBCTL_CLK3_EN_MASK           (0x8U)
75648 #define SYSCON_PWM0SUBCTL_CLK3_EN_SHIFT          (3U)
75649 /*! CLK3_EN - Enables PWM0 SUB Clock3 */
75650 #define SYSCON_PWM0SUBCTL_CLK3_EN(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM0SUBCTL_CLK3_EN_SHIFT)) & SYSCON_PWM0SUBCTL_CLK3_EN_MASK)
75651 
75652 #define SYSCON_PWM0SUBCTL_DMAVALM0_MASK          (0x1000U)
75653 #define SYSCON_PWM0SUBCTL_DMAVALM0_SHIFT         (12U)
75654 /*! DMAVALM0 - PWM0 submodule 0 DMA compare value done mask */
75655 #define SYSCON_PWM0SUBCTL_DMAVALM0(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM0SUBCTL_DMAVALM0_SHIFT)) & SYSCON_PWM0SUBCTL_DMAVALM0_MASK)
75656 
75657 #define SYSCON_PWM0SUBCTL_DMAVALM1_MASK          (0x2000U)
75658 #define SYSCON_PWM0SUBCTL_DMAVALM1_SHIFT         (13U)
75659 /*! DMAVALM1 - PWM0 submodule 1 DMA compare value done mask */
75660 #define SYSCON_PWM0SUBCTL_DMAVALM1(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM0SUBCTL_DMAVALM1_SHIFT)) & SYSCON_PWM0SUBCTL_DMAVALM1_MASK)
75661 
75662 #define SYSCON_PWM0SUBCTL_DMAVALM2_MASK          (0x4000U)
75663 #define SYSCON_PWM0SUBCTL_DMAVALM2_SHIFT         (14U)
75664 /*! DMAVALM2 - PWM0 submodule 2 DMA compare value done mask */
75665 #define SYSCON_PWM0SUBCTL_DMAVALM2(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM0SUBCTL_DMAVALM2_SHIFT)) & SYSCON_PWM0SUBCTL_DMAVALM2_MASK)
75666 
75667 #define SYSCON_PWM0SUBCTL_DMAVALM3_MASK          (0x8000U)
75668 #define SYSCON_PWM0SUBCTL_DMAVALM3_SHIFT         (15U)
75669 /*! DMAVALM3 - PWM0 submodule 3 DMA compare value done mask */
75670 #define SYSCON_PWM0SUBCTL_DMAVALM3(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM0SUBCTL_DMAVALM3_SHIFT)) & SYSCON_PWM0SUBCTL_DMAVALM3_MASK)
75671 /*! @} */
75672 
75673 /*! @name PWM1SUBCTL - PWM1 Submodule Control */
75674 /*! @{ */
75675 
75676 #define SYSCON_PWM1SUBCTL_CLK0_EN_MASK           (0x1U)
75677 #define SYSCON_PWM1SUBCTL_CLK0_EN_SHIFT          (0U)
75678 /*! CLK0_EN - Enables PWM1 SUB Clock0 */
75679 #define SYSCON_PWM1SUBCTL_CLK0_EN(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM1SUBCTL_CLK0_EN_SHIFT)) & SYSCON_PWM1SUBCTL_CLK0_EN_MASK)
75680 
75681 #define SYSCON_PWM1SUBCTL_CLK1_EN_MASK           (0x2U)
75682 #define SYSCON_PWM1SUBCTL_CLK1_EN_SHIFT          (1U)
75683 /*! CLK1_EN - Enables PWM1 SUB Clock1 */
75684 #define SYSCON_PWM1SUBCTL_CLK1_EN(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM1SUBCTL_CLK1_EN_SHIFT)) & SYSCON_PWM1SUBCTL_CLK1_EN_MASK)
75685 
75686 #define SYSCON_PWM1SUBCTL_CLK2_EN_MASK           (0x4U)
75687 #define SYSCON_PWM1SUBCTL_CLK2_EN_SHIFT          (2U)
75688 /*! CLK2_EN - Enables PWM1 SUB Clock2 */
75689 #define SYSCON_PWM1SUBCTL_CLK2_EN(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM1SUBCTL_CLK2_EN_SHIFT)) & SYSCON_PWM1SUBCTL_CLK2_EN_MASK)
75690 
75691 #define SYSCON_PWM1SUBCTL_CLK3_EN_MASK           (0x8U)
75692 #define SYSCON_PWM1SUBCTL_CLK3_EN_SHIFT          (3U)
75693 /*! CLK3_EN - Enables PWM1 SUB Clock3 */
75694 #define SYSCON_PWM1SUBCTL_CLK3_EN(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM1SUBCTL_CLK3_EN_SHIFT)) & SYSCON_PWM1SUBCTL_CLK3_EN_MASK)
75695 
75696 #define SYSCON_PWM1SUBCTL_DMAVALM0_MASK          (0x1000U)
75697 #define SYSCON_PWM1SUBCTL_DMAVALM0_SHIFT         (12U)
75698 /*! DMAVALM0 - PWM1 submodule 0 DMA compare value done mask */
75699 #define SYSCON_PWM1SUBCTL_DMAVALM0(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM1SUBCTL_DMAVALM0_SHIFT)) & SYSCON_PWM1SUBCTL_DMAVALM0_MASK)
75700 
75701 #define SYSCON_PWM1SUBCTL_DMAVALM1_MASK          (0x2000U)
75702 #define SYSCON_PWM1SUBCTL_DMAVALM1_SHIFT         (13U)
75703 /*! DMAVALM1 - PWM1 submodule 1 DMA compare value done mask */
75704 #define SYSCON_PWM1SUBCTL_DMAVALM1(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM1SUBCTL_DMAVALM1_SHIFT)) & SYSCON_PWM1SUBCTL_DMAVALM1_MASK)
75705 
75706 #define SYSCON_PWM1SUBCTL_DMAVALM2_MASK          (0x4000U)
75707 #define SYSCON_PWM1SUBCTL_DMAVALM2_SHIFT         (14U)
75708 /*! DMAVALM2 - PWM1 submodule 2 DMA compare value done mask */
75709 #define SYSCON_PWM1SUBCTL_DMAVALM2(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM1SUBCTL_DMAVALM2_SHIFT)) & SYSCON_PWM1SUBCTL_DMAVALM2_MASK)
75710 
75711 #define SYSCON_PWM1SUBCTL_DMAVALM3_MASK          (0x8000U)
75712 #define SYSCON_PWM1SUBCTL_DMAVALM3_SHIFT         (15U)
75713 /*! DMAVALM3 - PWM1 submodule 3 DMA compare value done mask */
75714 #define SYSCON_PWM1SUBCTL_DMAVALM3(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM1SUBCTL_DMAVALM3_SHIFT)) & SYSCON_PWM1SUBCTL_DMAVALM3_MASK)
75715 /*! @} */
75716 
75717 /*! @name CTIMERGLOBALSTARTEN - CTIMER Global Start Enable */
75718 /*! @{ */
75719 
75720 #define SYSCON_CTIMERGLOBALSTARTEN_CTIMER0_CLK_EN_MASK (0x1U)
75721 #define SYSCON_CTIMERGLOBALSTARTEN_CTIMER0_CLK_EN_SHIFT (0U)
75722 /*! CTIMER0_CLK_EN - Enables the CTIMER0 function clock
75723  *  0b1..Enable
75724  *  0b0..Disable
75725  */
75726 #define SYSCON_CTIMERGLOBALSTARTEN_CTIMER0_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERGLOBALSTARTEN_CTIMER0_CLK_EN_SHIFT)) & SYSCON_CTIMERGLOBALSTARTEN_CTIMER0_CLK_EN_MASK)
75727 
75728 #define SYSCON_CTIMERGLOBALSTARTEN_CTIMER1_CLK_EN_MASK (0x2U)
75729 #define SYSCON_CTIMERGLOBALSTARTEN_CTIMER1_CLK_EN_SHIFT (1U)
75730 /*! CTIMER1_CLK_EN - Enables the CTIMER1 function clock
75731  *  0b1..Enable
75732  *  0b0..Disable
75733  */
75734 #define SYSCON_CTIMERGLOBALSTARTEN_CTIMER1_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERGLOBALSTARTEN_CTIMER1_CLK_EN_SHIFT)) & SYSCON_CTIMERGLOBALSTARTEN_CTIMER1_CLK_EN_MASK)
75735 
75736 #define SYSCON_CTIMERGLOBALSTARTEN_CTIMER2_CLK_EN_MASK (0x4U)
75737 #define SYSCON_CTIMERGLOBALSTARTEN_CTIMER2_CLK_EN_SHIFT (2U)
75738 /*! CTIMER2_CLK_EN - Enables the CTIMER2 function clock
75739  *  0b1..Enable
75740  *  0b0..Disable
75741  */
75742 #define SYSCON_CTIMERGLOBALSTARTEN_CTIMER2_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERGLOBALSTARTEN_CTIMER2_CLK_EN_SHIFT)) & SYSCON_CTIMERGLOBALSTARTEN_CTIMER2_CLK_EN_MASK)
75743 
75744 #define SYSCON_CTIMERGLOBALSTARTEN_CTIMER3_CLK_EN_MASK (0x8U)
75745 #define SYSCON_CTIMERGLOBALSTARTEN_CTIMER3_CLK_EN_SHIFT (3U)
75746 /*! CTIMER3_CLK_EN - Enables the CTIMER3 function clock
75747  *  0b1..Enable
75748  *  0b0..Disable
75749  */
75750 #define SYSCON_CTIMERGLOBALSTARTEN_CTIMER3_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERGLOBALSTARTEN_CTIMER3_CLK_EN_SHIFT)) & SYSCON_CTIMERGLOBALSTARTEN_CTIMER3_CLK_EN_MASK)
75751 
75752 #define SYSCON_CTIMERGLOBALSTARTEN_CTIMER4_CLK_EN_MASK (0x10U)
75753 #define SYSCON_CTIMERGLOBALSTARTEN_CTIMER4_CLK_EN_SHIFT (4U)
75754 /*! CTIMER4_CLK_EN - Enables the CTIMER4 function clock
75755  *  0b1..Enable
75756  *  0b0..Disable
75757  */
75758 #define SYSCON_CTIMERGLOBALSTARTEN_CTIMER4_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERGLOBALSTARTEN_CTIMER4_CLK_EN_SHIFT)) & SYSCON_CTIMERGLOBALSTARTEN_CTIMER4_CLK_EN_MASK)
75759 /*! @} */
75760 
75761 /*! @name ECC_ENABLE_CTRL - RAM ECC Enable Control */
75762 /*! @{ */
75763 
75764 #define SYSCON_ECC_ENABLE_CTRL_RAMA_ECC_ENABLE_MASK (0x1U)
75765 #define SYSCON_ECC_ENABLE_CTRL_RAMA_ECC_ENABLE_SHIFT (0U)
75766 /*! RAMA_ECC_ENABLE - RAMA ECC enable
75767  *  0b1..ECC is enabled
75768  *  0b0..ECC is disabled
75769  */
75770 #define SYSCON_ECC_ENABLE_CTRL_RAMA_ECC_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ECC_ENABLE_CTRL_RAMA_ECC_ENABLE_SHIFT)) & SYSCON_ECC_ENABLE_CTRL_RAMA_ECC_ENABLE_MASK)
75771 
75772 #define SYSCON_ECC_ENABLE_CTRL_RAMB_RAMX_ECC_ENABLE_MASK (0x2U)
75773 #define SYSCON_ECC_ENABLE_CTRL_RAMB_RAMX_ECC_ENABLE_SHIFT (1U)
75774 /*! RAMB_RAMX_ECC_ENABLE - RAMB and RAMX ECC enable
75775  *  0b1..ECC is enabled
75776  *  0b0..ECC is disabled
75777  */
75778 #define SYSCON_ECC_ENABLE_CTRL_RAMB_RAMX_ECC_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ECC_ENABLE_CTRL_RAMB_RAMX_ECC_ENABLE_SHIFT)) & SYSCON_ECC_ENABLE_CTRL_RAMB_RAMX_ECC_ENABLE_MASK)
75779 
75780 #define SYSCON_ECC_ENABLE_CTRL_RAMD_RAMC_ECC_ENABLE_MASK (0x4U)
75781 #define SYSCON_ECC_ENABLE_CTRL_RAMD_RAMC_ECC_ENABLE_SHIFT (2U)
75782 /*! RAMD_RAMC_ECC_ENABLE - RAMD and RAMC ECC enable
75783  *  0b1..ECC is enabled
75784  *  0b0..ECC is disabled
75785  */
75786 #define SYSCON_ECC_ENABLE_CTRL_RAMD_RAMC_ECC_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ECC_ENABLE_CTRL_RAMD_RAMC_ECC_ENABLE_SHIFT)) & SYSCON_ECC_ENABLE_CTRL_RAMD_RAMC_ECC_ENABLE_MASK)
75787 
75788 #define SYSCON_ECC_ENABLE_CTRL_RAMF_RAME_ECC_ENABLE_MASK (0x8U)
75789 #define SYSCON_ECC_ENABLE_CTRL_RAMF_RAME_ECC_ENABLE_SHIFT (3U)
75790 /*! RAMF_RAME_ECC_ENABLE - RAMF and RAME ECC enable
75791  *  0b1..ECC is enabled
75792  *  0b0..ECC is disabled
75793  */
75794 #define SYSCON_ECC_ENABLE_CTRL_RAMF_RAME_ECC_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ECC_ENABLE_CTRL_RAMF_RAME_ECC_ENABLE_SHIFT)) & SYSCON_ECC_ENABLE_CTRL_RAMF_RAME_ECC_ENABLE_MASK)
75795 /*! @} */
75796 
75797 /*! @name DEBUG_LOCK_EN - Control Write Access to Security */
75798 /*! @{ */
75799 
75800 #define SYSCON_DEBUG_LOCK_EN_LOCK_ALL_MASK       (0xFU)
75801 #define SYSCON_DEBUG_LOCK_EN_LOCK_ALL_SHIFT      (0U)
75802 /*! LOCK_ALL - Controls write access to the security registers
75803  *  0b1010..Enables write access to all registers
75804  *  0b0000..Any other value than b1010: disables write access to all registers
75805  */
75806 #define SYSCON_DEBUG_LOCK_EN_LOCK_ALL(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_LOCK_EN_LOCK_ALL_SHIFT)) & SYSCON_DEBUG_LOCK_EN_LOCK_ALL_MASK)
75807 /*! @} */
75808 
75809 /*! @name DEBUG_FEATURES - Cortex Debug Features Control */
75810 /*! @{ */
75811 
75812 #define SYSCON_DEBUG_FEATURES_CPU0_DBGEN_MASK    (0x3U)
75813 #define SYSCON_DEBUG_FEATURES_CPU0_DBGEN_SHIFT   (0U)
75814 /*! CPU0_DBGEN - CPU0 invasive debug control
75815  *  0b01..Disables debug
75816  *  0b10..Enables debug
75817  */
75818 #define SYSCON_DEBUG_FEATURES_CPU0_DBGEN(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_DBGEN_MASK)
75819 
75820 #define SYSCON_DEBUG_FEATURES_CPU0_NIDEN_MASK    (0xCU)
75821 #define SYSCON_DEBUG_FEATURES_CPU0_NIDEN_SHIFT   (2U)
75822 /*! CPU0_NIDEN - CPU0 non-invasive debug control
75823  *  0b01..Disables debug
75824  *  0b10..Enables debug
75825  */
75826 #define SYSCON_DEBUG_FEATURES_CPU0_NIDEN(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_NIDEN_MASK)
75827 
75828 #define SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_MASK   (0x30U)
75829 #define SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_SHIFT  (4U)
75830 /*! CPU0_SPIDEN - CPU0 secure privileged invasive debug control
75831  *  0b01..Disables debug
75832  *  0b10..Enables debug
75833  */
75834 #define SYSCON_DEBUG_FEATURES_CPU0_SPIDEN(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_MASK)
75835 
75836 #define SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_MASK  (0xC0U)
75837 #define SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_SHIFT (6U)
75838 /*! CPU0_SPNIDEN - CPU0 secure privileged non-invasive debug control
75839  *  0b01..Disables debug
75840  *  0b10..Enables debug
75841  */
75842 #define SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_MASK)
75843 
75844 #define SYSCON_DEBUG_FEATURES_CPU1_DBGEN_MASK    (0x300U)
75845 #define SYSCON_DEBUG_FEATURES_CPU1_DBGEN_SHIFT   (8U)
75846 /*! CPU1_DBGEN - CPU1 invasive debug control
75847  *  0b01..Disables debug
75848  *  0b10..Enables debug
75849  */
75850 #define SYSCON_DEBUG_FEATURES_CPU1_DBGEN(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU1_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU1_DBGEN_MASK)
75851 
75852 #define SYSCON_DEBUG_FEATURES_CPU1_NIDEN_MASK    (0xC00U)
75853 #define SYSCON_DEBUG_FEATURES_CPU1_NIDEN_SHIFT   (10U)
75854 /*! CPU1_NIDEN - CPU1 non-invasive debug control
75855  *  0b01..Disables debug
75856  *  0b10..Enables debug
75857  */
75858 #define SYSCON_DEBUG_FEATURES_CPU1_NIDEN(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU1_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU1_NIDEN_MASK)
75859 
75860 #define SYSCON_DEBUG_FEATURES_DSP_DBGDEN_MASK    (0x3000U)
75861 #define SYSCON_DEBUG_FEATURES_DSP_DBGDEN_SHIFT   (12U)
75862 /*! DSP_DBGDEN - DSP invasive debug control
75863  *  0b01..Disables debug
75864  *  0b10..Enables debug
75865  */
75866 #define SYSCON_DEBUG_FEATURES_DSP_DBGDEN(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DSP_DBGDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DSP_DBGDEN_MASK)
75867 /*! @} */
75868 
75869 /*! @name DEBUG_FEATURES_DP - Cortex Debug Features Control (Duplicate) */
75870 /*! @{ */
75871 
75872 #define SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_MASK (0x3U)
75873 #define SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_SHIFT (0U)
75874 /*! CPU0_DBGEN - CPU0 invasive debug control
75875  *  0b01..Disables debug
75876  *  0b10..Enables debug
75877  */
75878 #define SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN(x)   (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_MASK)
75879 
75880 #define SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_MASK (0xCU)
75881 #define SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_SHIFT (2U)
75882 /*! CPU0_NIDEN - CPU0 non-invasive debug control
75883  *  0b01..Disables debug
75884  *  0b10..Enables debug
75885  */
75886 #define SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN(x)   (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_MASK)
75887 
75888 #define SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_MASK (0x30U)
75889 #define SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_SHIFT (4U)
75890 /*! CPU0_SPIDEN - CPU0 secure privileged invasive debug control
75891  *  0b01..Disables debug
75892  *  0b10..Enables debug
75893  */
75894 #define SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_MASK)
75895 
75896 #define SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_MASK (0xC0U)
75897 #define SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_SHIFT (6U)
75898 /*! CPU0_SPNIDEN - CPU0 secure privileged non-invasive debug control
75899  *  0b01..Disables debug
75900  *  0b10..Enables debug
75901  */
75902 #define SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_MASK)
75903 
75904 #define SYSCON_DEBUG_FEATURES_DP_CPU1_DBGEN_MASK (0x300U)
75905 #define SYSCON_DEBUG_FEATURES_DP_CPU1_DBGEN_SHIFT (8U)
75906 /*! CPU1_DBGEN - CPU1 invasive debug control
75907  *  0b01..Disables debug
75908  *  0b10..Enables debug
75909  */
75910 #define SYSCON_DEBUG_FEATURES_DP_CPU1_DBGEN(x)   (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU1_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU1_DBGEN_MASK)
75911 
75912 #define SYSCON_DEBUG_FEATURES_DP_CPU1_NIDEN_MASK (0xC00U)
75913 #define SYSCON_DEBUG_FEATURES_DP_CPU1_NIDEN_SHIFT (10U)
75914 /*! CPU1_NIDEN - CPU1 non-invasive debug control
75915  *  0b01..Disables debug
75916  *  0b10..Enables debug
75917  */
75918 #define SYSCON_DEBUG_FEATURES_DP_CPU1_NIDEN(x)   (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU1_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU1_NIDEN_MASK)
75919 
75920 #define SYSCON_DEBUG_FEATURES_DP_DSP_DBGEN_MASK  (0x3000U)
75921 #define SYSCON_DEBUG_FEATURES_DP_DSP_DBGEN_SHIFT (12U)
75922 /*! DSP_DBGEN - DSP invasive debug control
75923  *  0b01..Disables debug
75924  *  0b10..Enables debug
75925  */
75926 #define SYSCON_DEBUG_FEATURES_DP_DSP_DBGEN(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_DSP_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_DSP_DBGEN_MASK)
75927 /*! @} */
75928 
75929 /*! @name SWD_ACCESS_CPU - CPU0 Software Debug Access..CPU1 Software Debug Access */
75930 /*! @{ */
75931 
75932 #define SYSCON_SWD_ACCESS_CPU_SEC_CODE_MASK      (0xFFFFFFFFU)
75933 #define SYSCON_SWD_ACCESS_CPU_SEC_CODE_SHIFT     (0U)
75934 /*! SEC_CODE - Security code to allow CPU1 DAP: 0x12345678
75935  *  0b00010010001101000101011001111000..Value to write to enable CPU0 SWD access. Reading back register is read as 0xA.
75936  *  0b00000000000000000000000000000000..CPU0 DAP is not allowed. Reading back register is read as 0x5.
75937  */
75938 #define SYSCON_SWD_ACCESS_CPU_SEC_CODE(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_SWD_ACCESS_CPU_SEC_CODE_SHIFT)) & SYSCON_SWD_ACCESS_CPU_SEC_CODE_MASK)
75939 /*! @} */
75940 
75941 /* The count of SYSCON_SWD_ACCESS_CPU */
75942 #define SYSCON_SWD_ACCESS_CPU_COUNT              (2U)
75943 
75944 /*! @name DEBUG_AUTH_BEACON - Debug Authentication BEACON */
75945 /*! @{ */
75946 
75947 #define SYSCON_DEBUG_AUTH_BEACON_BEACON_MASK     (0xFFFFFFFFU)
75948 #define SYSCON_DEBUG_AUTH_BEACON_BEACON_SHIFT    (0U)
75949 /*! BEACON - Sets by the debug authentication code in ROM to pass the debug beacons (Credential
75950  *    Beacon and Authentication Beacon) to the application code.
75951  */
75952 #define SYSCON_DEBUG_AUTH_BEACON_BEACON(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_AUTH_BEACON_BEACON_SHIFT)) & SYSCON_DEBUG_AUTH_BEACON_BEACON_MASK)
75953 /*! @} */
75954 
75955 /*! @name SWD_ACCESS_DSP - DSP Software Debug Access */
75956 /*! @{ */
75957 
75958 #define SYSCON_SWD_ACCESS_DSP_SEC_CODE_MASK      (0xFFFFFFFFU)
75959 #define SYSCON_SWD_ACCESS_DSP_SEC_CODE_SHIFT     (0U)
75960 /*! SEC_CODE - DSP SWD-AP: 0x12345678
75961  *  0b00010010001101000101011001111000..Value to write to enable DSP SWD access. Reading back register is read as 0xA.
75962  *  0b00000000000000000000000000000000..DSP DAP is not allowed. Reading back register is read as 0x5.
75963  */
75964 #define SYSCON_SWD_ACCESS_DSP_SEC_CODE(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_SWD_ACCESS_DSP_SEC_CODE_SHIFT)) & SYSCON_SWD_ACCESS_DSP_SEC_CODE_MASK)
75965 /*! @} */
75966 
75967 /*! @name JTAG_ID - JTAG Chip ID */
75968 /*! @{ */
75969 
75970 #define SYSCON_JTAG_ID_JTAG_ID_MASK              (0xFFFFFFFFU)
75971 #define SYSCON_JTAG_ID_JTAG_ID_SHIFT             (0U)
75972 /*! JTAG_ID - Indicates the device ID */
75973 #define SYSCON_JTAG_ID_JTAG_ID(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_JTAG_ID_JTAG_ID_SHIFT)) & SYSCON_JTAG_ID_JTAG_ID_MASK)
75974 /*! @} */
75975 
75976 /*! @name DEVICE_TYPE - Device Type */
75977 /*! @{ */
75978 
75979 #define SYSCON_DEVICE_TYPE_DEVICE_TYPE_MASK      (0xFFFFFFFFU)
75980 #define SYSCON_DEVICE_TYPE_DEVICE_TYPE_SHIFT     (0U)
75981 /*! DEVICE_TYPE - Indicates DEVICE TYPE. */
75982 #define SYSCON_DEVICE_TYPE_DEVICE_TYPE(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_TYPE_DEVICE_TYPE_SHIFT)) & SYSCON_DEVICE_TYPE_DEVICE_TYPE_MASK)
75983 /*! @} */
75984 
75985 /*! @name DEVICE_ID0 - Device ID */
75986 /*! @{ */
75987 
75988 #define SYSCON_DEVICE_ID0_ROM_REV_MINOR_MASK     (0xF00000U)
75989 #define SYSCON_DEVICE_ID0_ROM_REV_MINOR_SHIFT    (20U)
75990 /*! ROM_REV_MINOR - ROM revision. */
75991 #define SYSCON_DEVICE_ID0_ROM_REV_MINOR(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_ROM_REV_MINOR_SHIFT)) & SYSCON_DEVICE_ID0_ROM_REV_MINOR_MASK)
75992 /*! @} */
75993 
75994 /*! @name DIEID - Chip Revision ID and Number */
75995 /*! @{ */
75996 
75997 #define SYSCON_DIEID_MINOR_REVISION_MASK         (0xFU)
75998 #define SYSCON_DIEID_MINOR_REVISION_SHIFT        (0U)
75999 /*! MINOR_REVISION - Chip minor revision */
76000 #define SYSCON_DIEID_MINOR_REVISION(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_DIEID_MINOR_REVISION_SHIFT)) & SYSCON_DIEID_MINOR_REVISION_MASK)
76001 
76002 #define SYSCON_DIEID_MAJOR_REVISION_MASK         (0xF0U)
76003 #define SYSCON_DIEID_MAJOR_REVISION_SHIFT        (4U)
76004 /*! MAJOR_REVISION - Chip major revision */
76005 #define SYSCON_DIEID_MAJOR_REVISION(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_DIEID_MAJOR_REVISION_SHIFT)) & SYSCON_DIEID_MAJOR_REVISION_MASK)
76006 
76007 #define SYSCON_DIEID_MCO_NUM_IN_DIE_ID_MASK      (0xFFFFF00U)
76008 #define SYSCON_DIEID_MCO_NUM_IN_DIE_ID_SHIFT     (8U)
76009 /*! MCO_NUM_IN_DIE_ID - Chip number */
76010 #define SYSCON_DIEID_MCO_NUM_IN_DIE_ID(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_DIEID_MCO_NUM_IN_DIE_ID_SHIFT)) & SYSCON_DIEID_MCO_NUM_IN_DIE_ID_MASK)
76011 /*! @} */
76012 
76013 
76014 /*!
76015  * @}
76016  */ /* end of group SYSCON_Register_Masks */
76017 
76018 
76019 /* SYSCON - Peripheral instance base addresses */
76020 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
76021   /** Peripheral SYSCON0 base address */
76022   #define SYSCON0_BASE                             (0x50000000u)
76023   /** Peripheral SYSCON0 base address */
76024   #define SYSCON0_BASE_NS                          (0x40000000u)
76025   /** Peripheral SYSCON0 base pointer */
76026   #define SYSCON0                                  ((SYSCON_Type *)SYSCON0_BASE)
76027   /** Peripheral SYSCON0 base pointer */
76028   #define SYSCON0_NS                               ((SYSCON_Type *)SYSCON0_BASE_NS)
76029   /** Array initializer of SYSCON peripheral base addresses */
76030   #define SYSCON_BASE_ADDRS                        { SYSCON0_BASE }
76031   /** Array initializer of SYSCON peripheral base pointers */
76032   #define SYSCON_BASE_PTRS                         { SYSCON0 }
76033   /** Array initializer of SYSCON peripheral base addresses */
76034   #define SYSCON_BASE_ADDRS_NS                     { SYSCON0_BASE_NS }
76035   /** Array initializer of SYSCON peripheral base pointers */
76036   #define SYSCON_BASE_PTRS_NS                      { SYSCON0_NS }
76037 #else
76038   /** Peripheral SYSCON0 base address */
76039   #define SYSCON0_BASE                             (0x40000000u)
76040   /** Peripheral SYSCON0 base pointer */
76041   #define SYSCON0                                  ((SYSCON_Type *)SYSCON0_BASE)
76042   /** Array initializer of SYSCON peripheral base addresses */
76043   #define SYSCON_BASE_ADDRS                        { SYSCON0_BASE }
76044   /** Array initializer of SYSCON peripheral base pointers */
76045   #define SYSCON_BASE_PTRS                         { SYSCON0 }
76046 #endif
76047 /* Backward compatibility */
76048 #define SYSCON                               SYSCON0
76049 
76050 
76051 /*!
76052  * @}
76053  */ /* end of group SYSCON_Peripheral_Access_Layer */
76054 
76055 
76056 /* ----------------------------------------------------------------------------
76057    -- SYSPM Peripheral Access Layer
76058    ---------------------------------------------------------------------------- */
76059 
76060 /*!
76061  * @addtogroup SYSPM_Peripheral_Access_Layer SYSPM Peripheral Access Layer
76062  * @{
76063  */
76064 
76065 /** SYSPM - Register Layout Typedef */
76066 typedef struct {
76067   struct {                                         /* offset: 0x0, array step: 0x30 */
76068     __IO uint32_t PMCR;                              /**< Performance Monitor Control, array offset: 0x0, array step: 0x30 */
76069          uint8_t RESERVED_0[20];
76070     struct {                                         /* offset: 0x18, array step: index*0x30, index2*0x8 */
76071       __I  uint8_t HI;                                 /**< Performance Monitor Event Counter, array offset: 0x18, array step: index*0x30, index2*0x8 */
76072            uint8_t RESERVED_0[3];
76073       __I  uint32_t LO;                                /**< Performance Monitor Event Counter, array offset: 0x1C, array step: index*0x30, index2*0x8 */
76074     } PMECTR[3];
76075   } PMCR[1];
76076 } SYSPM_Type;
76077 
76078 /* ----------------------------------------------------------------------------
76079    -- SYSPM Register Masks
76080    ---------------------------------------------------------------------------- */
76081 
76082 /*!
76083  * @addtogroup SYSPM_Register_Masks SYSPM Register Masks
76084  * @{
76085  */
76086 
76087 /*! @name PMCR - Performance Monitor Control */
76088 /*! @{ */
76089 
76090 #define SYSPM_PMCR_MENB_MASK                     (0x1U)
76091 #define SYSPM_PMCR_MENB_SHIFT                    (0U)
76092 /*! MENB - Module Is Enabled
76093  *  0b0..Disabled
76094  *  0b1..Enabled
76095  */
76096 #define SYSPM_PMCR_MENB(x)                       (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_MENB_SHIFT)) & SYSPM_PMCR_MENB_MASK)
76097 
76098 #define SYSPM_PMCR_SSC_MASK                      (0xEU)
76099 #define SYSPM_PMCR_SSC_SHIFT                     (1U)
76100 /*! SSC - Start and Stop Control
76101  *  0b000..Idle or no-op
76102  *  0b001..Local stop
76103  *  0b010, 0b011..Local start
76104  *  0b100..
76105  *  0b101..
76106  *  0b110, 0b111..
76107  */
76108 #define SYSPM_PMCR_SSC(x)                        (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_SSC_SHIFT)) & SYSPM_PMCR_SSC_MASK)
76109 
76110 #define SYSPM_PMCR_CMODE_MASK                    (0x30U)
76111 #define SYSPM_PMCR_CMODE_SHIFT                   (4U)
76112 /*! CMODE - Count Mode
76113  *  0b00..Counted in both User and Privileged modes
76114  *  0b01..
76115  *  0b10..Counted only in User mode
76116  *  0b11..Counted only in Privileged mode
76117  */
76118 #define SYSPM_PMCR_CMODE(x)                      (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_CMODE_SHIFT)) & SYSPM_PMCR_CMODE_MASK)
76119 
76120 #define SYSPM_PMCR_RECTR1_MASK                   (0x100U)
76121 #define SYSPM_PMCR_RECTR1_SHIFT                  (8U)
76122 /*! RECTR1 - Reset Event Counter 1
76123  *  0b0..Run normally
76124  *  0b1..Reset
76125  */
76126 #define SYSPM_PMCR_RECTR1(x)                     (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_RECTR1_SHIFT)) & SYSPM_PMCR_RECTR1_MASK)
76127 
76128 #define SYSPM_PMCR_RECTR2_MASK                   (0x200U)
76129 #define SYSPM_PMCR_RECTR2_SHIFT                  (9U)
76130 /*! RECTR2 - Reset Event Counter 2
76131  *  0b0..Run normally
76132  *  0b1..Reset
76133  */
76134 #define SYSPM_PMCR_RECTR2(x)                     (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_RECTR2_SHIFT)) & SYSPM_PMCR_RECTR2_MASK)
76135 
76136 #define SYSPM_PMCR_RECTR3_MASK                   (0x400U)
76137 #define SYSPM_PMCR_RECTR3_SHIFT                  (10U)
76138 /*! RECTR3 - Reset Event Counter 3
76139  *  0b0..Run normally
76140  *  0b1..Reset
76141  */
76142 #define SYSPM_PMCR_RECTR3(x)                     (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_RECTR3_SHIFT)) & SYSPM_PMCR_RECTR3_MASK)
76143 
76144 #define SYSPM_PMCR_SELEVT1_MASK                  (0x3F800U)
76145 #define SYSPM_PMCR_SELEVT1_SHIFT                 (11U)
76146 /*! SELEVT1 - Select Event 1 */
76147 #define SYSPM_PMCR_SELEVT1(x)                    (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_SELEVT1_SHIFT)) & SYSPM_PMCR_SELEVT1_MASK)
76148 
76149 #define SYSPM_PMCR_SELEVT2_MASK                  (0x1FC0000U)
76150 #define SYSPM_PMCR_SELEVT2_SHIFT                 (18U)
76151 /*! SELEVT2 - Select Event 2 */
76152 #define SYSPM_PMCR_SELEVT2(x)                    (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_SELEVT2_SHIFT)) & SYSPM_PMCR_SELEVT2_MASK)
76153 
76154 #define SYSPM_PMCR_SELEVT3_MASK                  (0xFE000000U)
76155 #define SYSPM_PMCR_SELEVT3_SHIFT                 (25U)
76156 /*! SELEVT3 - Select Event 3 */
76157 #define SYSPM_PMCR_SELEVT3(x)                    (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_SELEVT3_SHIFT)) & SYSPM_PMCR_SELEVT3_MASK)
76158 /*! @} */
76159 
76160 /* The count of SYSPM_PMCR */
76161 #define SYSPM_PMCR_COUNT                         (1U)
76162 
76163 /*! @name PMCR_PMECTR_HI - Performance Monitor Event Counter */
76164 /*! @{ */
76165 
76166 #define SYSPM_PMCR_PMECTR_HI_ECTR_MASK           (0xFFU)
76167 #define SYSPM_PMCR_PMECTR_HI_ECTR_SHIFT          (0U)
76168 /*! ECTR - Event Counter */
76169 #define SYSPM_PMCR_PMECTR_HI_ECTR(x)             (((uint8_t)(((uint8_t)(x)) << SYSPM_PMCR_PMECTR_HI_ECTR_SHIFT)) & SYSPM_PMCR_PMECTR_HI_ECTR_MASK)
76170 /*! @} */
76171 
76172 /* The count of SYSPM_PMCR_PMECTR_HI */
76173 #define SYSPM_PMCR_PMECTR_HI_COUNT               (1U)
76174 
76175 /* The count of SYSPM_PMCR_PMECTR_HI */
76176 #define SYSPM_PMCR_PMECTR_HI_COUNT2              (3U)
76177 
76178 /*! @name PMCR_PMECTR_LO - Performance Monitor Event Counter */
76179 /*! @{ */
76180 
76181 #define SYSPM_PMCR_PMECTR_LO_ECTR_MASK           (0xFFFFFFFFU)
76182 #define SYSPM_PMCR_PMECTR_LO_ECTR_SHIFT          (0U)
76183 /*! ECTR - Event Counter */
76184 #define SYSPM_PMCR_PMECTR_LO_ECTR(x)             (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_PMECTR_LO_ECTR_SHIFT)) & SYSPM_PMCR_PMECTR_LO_ECTR_MASK)
76185 /*! @} */
76186 
76187 /* The count of SYSPM_PMCR_PMECTR_LO */
76188 #define SYSPM_PMCR_PMECTR_LO_COUNT               (1U)
76189 
76190 /* The count of SYSPM_PMCR_PMECTR_LO */
76191 #define SYSPM_PMCR_PMECTR_LO_COUNT2              (3U)
76192 
76193 
76194 /*!
76195  * @}
76196  */ /* end of group SYSPM_Register_Masks */
76197 
76198 
76199 /* SYSPM - Peripheral instance base addresses */
76200 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
76201   /** Peripheral CMX_PERFMON0 base address */
76202   #define CMX_PERFMON0_BASE                        (0x500C1000u)
76203   /** Peripheral CMX_PERFMON0 base address */
76204   #define CMX_PERFMON0_BASE_NS                     (0x400C1000u)
76205   /** Peripheral CMX_PERFMON0 base pointer */
76206   #define CMX_PERFMON0                             ((SYSPM_Type *)CMX_PERFMON0_BASE)
76207   /** Peripheral CMX_PERFMON0 base pointer */
76208   #define CMX_PERFMON0_NS                          ((SYSPM_Type *)CMX_PERFMON0_BASE_NS)
76209   /** Peripheral CMX_PERFMON1 base address */
76210   #define CMX_PERFMON1_BASE                        (0x500C2000u)
76211   /** Peripheral CMX_PERFMON1 base address */
76212   #define CMX_PERFMON1_BASE_NS                     (0x400C2000u)
76213   /** Peripheral CMX_PERFMON1 base pointer */
76214   #define CMX_PERFMON1                             ((SYSPM_Type *)CMX_PERFMON1_BASE)
76215   /** Peripheral CMX_PERFMON1 base pointer */
76216   #define CMX_PERFMON1_NS                          ((SYSPM_Type *)CMX_PERFMON1_BASE_NS)
76217   /** Array initializer of SYSPM peripheral base addresses */
76218   #define SYSPM_BASE_ADDRS                         { CMX_PERFMON0_BASE, CMX_PERFMON1_BASE }
76219   /** Array initializer of SYSPM peripheral base pointers */
76220   #define SYSPM_BASE_PTRS                          { CMX_PERFMON0, CMX_PERFMON1 }
76221   /** Array initializer of SYSPM peripheral base addresses */
76222   #define SYSPM_BASE_ADDRS_NS                      { CMX_PERFMON0_BASE_NS, CMX_PERFMON1_BASE_NS }
76223   /** Array initializer of SYSPM peripheral base pointers */
76224   #define SYSPM_BASE_PTRS_NS                       { CMX_PERFMON0_NS, CMX_PERFMON1_NS }
76225 #else
76226   /** Peripheral CMX_PERFMON0 base address */
76227   #define CMX_PERFMON0_BASE                        (0x400C1000u)
76228   /** Peripheral CMX_PERFMON0 base pointer */
76229   #define CMX_PERFMON0                             ((SYSPM_Type *)CMX_PERFMON0_BASE)
76230   /** Peripheral CMX_PERFMON1 base address */
76231   #define CMX_PERFMON1_BASE                        (0x400C2000u)
76232   /** Peripheral CMX_PERFMON1 base pointer */
76233   #define CMX_PERFMON1                             ((SYSPM_Type *)CMX_PERFMON1_BASE)
76234   /** Array initializer of SYSPM peripheral base addresses */
76235   #define SYSPM_BASE_ADDRS                         { CMX_PERFMON0_BASE, CMX_PERFMON1_BASE }
76236   /** Array initializer of SYSPM peripheral base pointers */
76237   #define SYSPM_BASE_PTRS                          { CMX_PERFMON0, CMX_PERFMON1 }
76238 #endif
76239 
76240 /*!
76241  * @}
76242  */ /* end of group SYSPM_Peripheral_Access_Layer */
76243 
76244 
76245 /* ----------------------------------------------------------------------------
76246    -- TRDC Peripheral Access Layer
76247    ---------------------------------------------------------------------------- */
76248 
76249 /*!
76250  * @addtogroup TRDC_Peripheral_Access_Layer TRDC Peripheral Access Layer
76251  * @{
76252  */
76253 
76254 /** TRDC - Register Layout Typedef */
76255 typedef struct {
76256   struct {                                         /* offset: 0x0, array step: 0x1CC */
76257     __IO uint32_t MBC_MEM_GLBCFG[4];                 /**< MBC Global Configuration Register, array offset: 0x0, array step: index*0x1CC, index2*0x4 */
76258     __IO uint32_t MBC_NSE_BLK_INDEX;                 /**< MBC NonSecure Enable Block Index, array offset: 0x10, array step: 0x1CC */
76259     __O  uint32_t MBC_NSE_BLK_SET;                   /**< MBC NonSecure Enable Block Set, array offset: 0x14, array step: 0x1CC */
76260     __O  uint32_t MBC_NSE_BLK_CLR;                   /**< MBC NonSecure Enable Block Clear, array offset: 0x18, array step: 0x1CC */
76261     __O  uint32_t MBC_NSE_BLK_CLR_ALL;               /**< MBC NonSecure Enable Block Clear All, array offset: 0x1C, array step: 0x1CC */
76262     __IO uint32_t MBC_MEMN_GLBAC[8];                 /**< MBC Global Access Control, array offset: 0x20, array step: index*0x1CC, index2*0x4 */
76263     __IO uint32_t MBC_DOM0_MEM0_BLK_CFG_W[8];        /**< MBC Memory Block Configuration Word, array offset: 0x40, array step: index*0x1CC, index2*0x4 */
76264          uint8_t RESERVED_0[224];
76265     __IO uint32_t MBC_DOM0_MEM0_BLK_NSE_W[2];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x140, array step: index*0x1CC, index2*0x4 */
76266          uint8_t RESERVED_1[56];
76267     __IO uint32_t MBC_DOM0_MEM1_BLK_CFG_W[1];        /**< MBC Memory Block Configuration Word, array offset: 0x180, array step: index*0x1CC, index2*0x4 */
76268          uint8_t RESERVED_2[28];
76269     __IO uint32_t MBC_DOM0_MEM1_BLK_NSE_W[1];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x1A0, array step: index*0x1CC, index2*0x4 */
76270          uint8_t RESERVED_3[4];
76271     __IO uint32_t MBC_DOM0_MEM2_BLK_CFG_W[1];        /**< MBC Memory Block Configuration Word, array offset: 0x1A8, array step: index*0x1CC, index2*0x4 */
76272          uint8_t RESERVED_4[28];
76273     __IO uint32_t MBC_DOM0_MEM2_BLK_NSE_W[1];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x1C8, array step: index*0x1CC, index2*0x4 */
76274   } MBC_INDEX[1];
76275 } TRDC_Type;
76276 
76277 /* ----------------------------------------------------------------------------
76278    -- TRDC Register Masks
76279    ---------------------------------------------------------------------------- */
76280 
76281 /*!
76282  * @addtogroup TRDC_Register_Masks TRDC Register Masks
76283  * @{
76284  */
76285 
76286 /*! @name MBC_INDEX_MBC_MEM_GLBCFG - MBC Global Configuration Register */
76287 /*! @{ */
76288 
76289 #define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_NBLKS_MASK (0x3FFU)
76290 #define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_NBLKS_SHIFT (0U)
76291 /*! NBLKS - Number of blocks in this memory */
76292 #define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_NBLKS(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEM_GLBCFG_NBLKS_SHIFT)) & TRDC_MBC_INDEX_MBC_MEM_GLBCFG_NBLKS_MASK)
76293 
76294 #define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_SIZE_LOG2_MASK (0x1F0000U)
76295 #define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_SIZE_LOG2_SHIFT (16U)
76296 /*! SIZE_LOG2 - Log2 size per block */
76297 #define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_SIZE_LOG2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEM_GLBCFG_SIZE_LOG2_SHIFT)) & TRDC_MBC_INDEX_MBC_MEM_GLBCFG_SIZE_LOG2_MASK)
76298 
76299 #define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_CLRE_MASK  (0xC0000000U)
76300 #define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_CLRE_SHIFT (30U)
76301 /*! CLRE - Clear Error */
76302 #define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_CLRE(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEM_GLBCFG_CLRE_SHIFT)) & TRDC_MBC_INDEX_MBC_MEM_GLBCFG_CLRE_MASK)
76303 /*! @} */
76304 
76305 /* The count of TRDC_MBC_INDEX_MBC_MEM_GLBCFG */
76306 #define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_COUNT      (1U)
76307 
76308 /* The count of TRDC_MBC_INDEX_MBC_MEM_GLBCFG */
76309 #define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_COUNT2     (4U)
76310 
76311 /*! @name MBC_INDEX_MBC_NSE_BLK_INDEX - MBC NonSecure Enable Block Index */
76312 /*! @{ */
76313 
76314 #define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_WNDX_MASK (0x3CU)
76315 #define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_WNDX_SHIFT (2U)
76316 /*! WNDX - Word index into the block NSE bitmap. It selects the BLK_NSE_Wn register, where WNDX determines the value of n. */
76317 #define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_WNDX(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_WNDX_SHIFT)) & TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_WNDX_MASK)
76318 
76319 #define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_MEM_SEL_MASK (0xF00U)
76320 #define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_MEM_SEL_SHIFT (8U)
76321 /*! MEM_SEL - Memory Select */
76322 #define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_MEM_SEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_MEM_SEL_SHIFT)) & TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_MEM_SEL_MASK)
76323 
76324 #define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_DID_SEL0_MASK (0x10000U)
76325 #define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_DID_SEL0_SHIFT (16U)
76326 /*! DID_SEL0 - DID Select
76327  *  0b0..No effect.
76328  *  0b1..Selects NSE bits for this domain.
76329  */
76330 #define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_DID_SEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_DID_SEL0_SHIFT)) & TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_DID_SEL0_MASK)
76331 
76332 #define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_AI_MASK (0x80000000U)
76333 #define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_AI_SHIFT (31U)
76334 /*! AI - Auto Increment
76335  *  0b0..No effect.
76336  *  0b1..Add 1 to the WNDX field after the register write.
76337  */
76338 #define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_AI(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_AI_SHIFT)) & TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_AI_MASK)
76339 /*! @} */
76340 
76341 /* The count of TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX */
76342 #define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_COUNT   (1U)
76343 
76344 /*! @name MBC_INDEX_MBC_NSE_BLK_SET - MBC NonSecure Enable Block Set */
76345 /*! @{ */
76346 
76347 #define TRDC_MBC_INDEX_MBC_NSE_BLK_SET_W1SET_MASK (0xFFFFFFFFU)
76348 #define TRDC_MBC_INDEX_MBC_NSE_BLK_SET_W1SET_SHIFT (0U)
76349 /*! W1SET - Write-1 Set */
76350 #define TRDC_MBC_INDEX_MBC_NSE_BLK_SET_W1SET(x)  (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_NSE_BLK_SET_W1SET_SHIFT)) & TRDC_MBC_INDEX_MBC_NSE_BLK_SET_W1SET_MASK)
76351 /*! @} */
76352 
76353 /* The count of TRDC_MBC_INDEX_MBC_NSE_BLK_SET */
76354 #define TRDC_MBC_INDEX_MBC_NSE_BLK_SET_COUNT     (1U)
76355 
76356 /*! @name MBC_INDEX_MBC_NSE_BLK_CLR - MBC NonSecure Enable Block Clear */
76357 /*! @{ */
76358 
76359 #define TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_W1CLR_MASK (0xFFFFFFFFU)
76360 #define TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_W1CLR_SHIFT (0U)
76361 /*! W1CLR - Write-1 Clear */
76362 #define TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_W1CLR(x)  (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_W1CLR_SHIFT)) & TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_W1CLR_MASK)
76363 /*! @} */
76364 
76365 /* The count of TRDC_MBC_INDEX_MBC_NSE_BLK_CLR */
76366 #define TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_COUNT     (1U)
76367 
76368 /*! @name MBC_INDEX_MBC_NSE_BLK_CLR_ALL - MBC NonSecure Enable Block Clear All */
76369 /*! @{ */
76370 
76371 #define TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL_MEMSEL_MASK (0xF00U)
76372 #define TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL_MEMSEL_SHIFT (8U)
76373 /*! MEMSEL - Memory Select */
76374 #define TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL_MEMSEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL_MEMSEL_SHIFT)) & TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL_MEMSEL_MASK)
76375 
76376 #define TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL_DID_SEL0_MASK (0x10000U)
76377 #define TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL_DID_SEL0_SHIFT (16U)
76378 /*! DID_SEL0 - DID Select
76379  *  0b0..No effect.
76380  *  0b1..Clear all NSE bits for this domain.
76381  */
76382 #define TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL_DID_SEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL_DID_SEL0_SHIFT)) & TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL_DID_SEL0_MASK)
76383 /*! @} */
76384 
76385 /* The count of TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL */
76386 #define TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL_COUNT (1U)
76387 
76388 /*! @name MBC_INDEX_MBC_MEMN_GLBAC - MBC Global Access Control */
76389 /*! @{ */
76390 
76391 #define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUX_MASK   (0x1U)
76392 #define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUX_SHIFT  (0U)
76393 /*! NUX - NonsecureUser Execute
76394  *  0b0..Execute access is not allowed in Nonsecure User mode.
76395  *  0b1..Execute access is allowed in Nonsecure User mode.
76396  */
76397 #define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUX(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUX_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUX_MASK)
76398 
76399 #define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUW_MASK   (0x2U)
76400 #define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUW_SHIFT  (1U)
76401 /*! NUW - NonsecureUser Write
76402  *  0b0..Write access is not allowed in Nonsecure User mode.
76403  *  0b1..Write access is allowed in Nonsecure User mode.
76404  */
76405 #define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUW(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUW_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUW_MASK)
76406 
76407 #define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUR_MASK   (0x4U)
76408 #define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUR_SHIFT  (2U)
76409 /*! NUR - NonsecureUser Read
76410  *  0b0..Read access is not allowed in Nonsecure User mode.
76411  *  0b1..Read access is allowed in Nonsecure User mode.
76412  */
76413 #define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUR(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUR_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUR_MASK)
76414 
76415 #define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPX_MASK   (0x10U)
76416 #define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPX_SHIFT  (4U)
76417 /*! NPX - NonsecurePriv Execute
76418  *  0b0..Execute access is not allowed in Nonsecure Privilege mode.
76419  *  0b1..Execute access is allowed in Nonsecure Privilege mode.
76420  */
76421 #define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPX(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPX_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPX_MASK)
76422 
76423 #define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPW_MASK   (0x20U)
76424 #define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPW_SHIFT  (5U)
76425 /*! NPW - NonsecurePriv Write
76426  *  0b0..Write access is not allowed in Nonsecure Privilege mode.
76427  *  0b1..Write access is allowed in Nonsecure Privilege mode.
76428  */
76429 #define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPW(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPW_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPW_MASK)
76430 
76431 #define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPR_MASK   (0x40U)
76432 #define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPR_SHIFT  (6U)
76433 /*! NPR - NonsecurePriv Read
76434  *  0b0..Read access is not allowed in Nonsecure Privilege mode.
76435  *  0b1..Read access is allowed in Nonsecure Privilege mode.
76436  */
76437 #define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPR(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPR_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPR_MASK)
76438 
76439 #define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUX_MASK   (0x100U)
76440 #define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUX_SHIFT  (8U)
76441 /*! SUX - SecureUser Execute
76442  *  0b0..Execute access is not allowed in Secure User mode.
76443  *  0b1..Execute access is allowed in Secure User mode.
76444  */
76445 #define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUX(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUX_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUX_MASK)
76446 
76447 #define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUW_MASK   (0x200U)
76448 #define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUW_SHIFT  (9U)
76449 /*! SUW - SecureUser Write
76450  *  0b0..Write access is not allowed in Secure User mode.
76451  *  0b1..Write access is allowed in Secure User mode.
76452  */
76453 #define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUW(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUW_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUW_MASK)
76454 
76455 #define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUR_MASK   (0x400U)
76456 #define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUR_SHIFT  (10U)
76457 /*! SUR - SecureUser Read
76458  *  0b0..Read access is not allowed in Secure User mode.
76459  *  0b1..Read access is allowed in Secure User mode.
76460  */
76461 #define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUR(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUR_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUR_MASK)
76462 
76463 #define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPX_MASK   (0x1000U)
76464 #define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPX_SHIFT  (12U)
76465 /*! SPX - SecurePriv Execute
76466  *  0b0..Execute access is not allowed in Secure Privilege mode.
76467  *  0b1..Execute access is allowed in Secure Privilege mode.
76468  */
76469 #define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPX(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPX_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPX_MASK)
76470 
76471 #define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPW_MASK   (0x2000U)
76472 #define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPW_SHIFT  (13U)
76473 /*! SPW - SecurePriv Write
76474  *  0b0..Write access is not allowed in Secure Privilege mode.
76475  *  0b1..Write access is allowed in Secure Privilege mode.
76476  */
76477 #define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPW(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPW_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPW_MASK)
76478 
76479 #define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPR_MASK   (0x4000U)
76480 #define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPR_SHIFT  (14U)
76481 /*! SPR - SecurePriv Read
76482  *  0b0..Read access is not allowed in Secure Privilege mode.
76483  *  0b1..Read access is allowed in Secure Privilege mode.
76484  */
76485 #define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPR(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPR_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPR_MASK)
76486 
76487 #define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_LK_MASK    (0x80000000U)
76488 #define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_LK_SHIFT   (31U)
76489 /*! LK - LOCK
76490  *  0b0..This register is not locked and can be altered.
76491  *  0b1..This register is locked and cannot be altered.
76492  */
76493 #define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_LK(x)      (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_LK_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_LK_MASK)
76494 /*! @} */
76495 
76496 /* The count of TRDC_MBC_INDEX_MBC_MEMN_GLBAC */
76497 #define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_COUNT      (1U)
76498 
76499 /* The count of TRDC_MBC_INDEX_MBC_MEMN_GLBAC */
76500 #define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_COUNT2     (8U)
76501 
76502 /*! @name MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */
76503 /*! @{ */
76504 
76505 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U)
76506 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U)
76507 /*! MBACSEL0 - Memory Block Access Control Select for block B
76508  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
76509  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
76510  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
76511  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
76512  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
76513  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
76514  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
76515  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
76516  */
76517 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0_MASK)
76518 
76519 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE0_MASK (0x8U)
76520 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE0_SHIFT (3U)
76521 /*! NSE0 - NonSecure Enable for block B
76522  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
76523  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
76524  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
76525  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
76526  */
76527 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE0_MASK)
76528 
76529 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U)
76530 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U)
76531 /*! MBACSEL1 - Memory Block Access Control Select for block B
76532  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
76533  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
76534  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
76535  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
76536  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
76537  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
76538  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
76539  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
76540  */
76541 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1_MASK)
76542 
76543 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE1_MASK (0x80U)
76544 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE1_SHIFT (7U)
76545 /*! NSE1 - NonSecure Enable for block B
76546  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
76547  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
76548  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
76549  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
76550  */
76551 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE1_MASK)
76552 
76553 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U)
76554 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U)
76555 /*! MBACSEL2 - Memory Block Access Control Select for block B
76556  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
76557  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
76558  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
76559  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
76560  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
76561  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
76562  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
76563  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
76564  */
76565 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2_MASK)
76566 
76567 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE2_MASK (0x800U)
76568 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE2_SHIFT (11U)
76569 /*! NSE2 - NonSecure Enable for block B
76570  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
76571  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
76572  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
76573  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
76574  */
76575 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE2_MASK)
76576 
76577 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
76578 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U)
76579 /*! MBACSEL3 - Memory Block Access Control Select for block B
76580  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
76581  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
76582  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
76583  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
76584  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
76585  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
76586  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
76587  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
76588  */
76589 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3_MASK)
76590 
76591 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE3_MASK (0x8000U)
76592 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE3_SHIFT (15U)
76593 /*! NSE3 - NonSecure Enable for block B
76594  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
76595  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
76596  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
76597  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
76598  */
76599 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE3_MASK)
76600 
76601 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
76602 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U)
76603 /*! MBACSEL4 - Memory Block Access Control Select for block B
76604  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
76605  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
76606  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
76607  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
76608  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
76609  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
76610  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
76611  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
76612  */
76613 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4_MASK)
76614 
76615 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE4_MASK (0x80000U)
76616 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE4_SHIFT (19U)
76617 /*! NSE4 - NonSecure Enable for block B
76618  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
76619  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
76620  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
76621  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
76622  */
76623 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE4_MASK)
76624 
76625 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
76626 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U)
76627 /*! MBACSEL5 - Memory Block Access Control Select for block B
76628  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
76629  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
76630  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
76631  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
76632  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
76633  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
76634  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
76635  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
76636  */
76637 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5_MASK)
76638 
76639 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE5_MASK (0x800000U)
76640 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE5_SHIFT (23U)
76641 /*! NSE5 - NonSecure Enable for block B
76642  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
76643  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
76644  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
76645  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
76646  */
76647 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE5_MASK)
76648 
76649 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
76650 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U)
76651 /*! MBACSEL6 - Memory Block Access Control Select for block B
76652  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
76653  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
76654  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
76655  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
76656  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
76657  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
76658  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
76659  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
76660  */
76661 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6_MASK)
76662 
76663 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE6_MASK (0x8000000U)
76664 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE6_SHIFT (27U)
76665 /*! NSE6 - NonSecure Enable for block B
76666  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
76667  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
76668  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
76669  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
76670  */
76671 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE6_MASK)
76672 
76673 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
76674 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U)
76675 /*! MBACSEL7 - Memory Block Access Control Select for block B
76676  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
76677  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
76678  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
76679  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
76680  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
76681  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
76682  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
76683  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
76684  */
76685 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7_MASK)
76686 
76687 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE7_MASK (0x80000000U)
76688 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE7_SHIFT (31U)
76689 /*! NSE7 - NonSecure Enable for block B
76690  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
76691  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
76692  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
76693  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
76694  */
76695 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE7_MASK)
76696 /*! @} */
76697 
76698 /* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W */
76699 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_COUNT (1U)
76700 
76701 /* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W */
76702 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_COUNT2 (8U)
76703 
76704 /*! @name MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
76705 /*! @{ */
76706 
76707 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT0_MASK (0x1U)
76708 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT0_SHIFT (0U)
76709 /*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
76710  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
76711  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
76712  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
76713  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
76714  */
76715 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT0_MASK)
76716 
76717 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT1_MASK (0x2U)
76718 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT1_SHIFT (1U)
76719 /*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
76720  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
76721  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
76722  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
76723  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
76724  */
76725 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT1_MASK)
76726 
76727 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT2_MASK (0x4U)
76728 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT2_SHIFT (2U)
76729 /*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
76730  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
76731  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
76732  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
76733  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
76734  */
76735 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT2_MASK)
76736 
76737 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT3_MASK (0x8U)
76738 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT3_SHIFT (3U)
76739 /*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
76740  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
76741  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
76742  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
76743  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
76744  */
76745 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT3_MASK)
76746 
76747 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT4_MASK (0x10U)
76748 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT4_SHIFT (4U)
76749 /*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
76750  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
76751  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
76752  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
76753  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
76754  */
76755 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT4_MASK)
76756 
76757 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT5_MASK (0x20U)
76758 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT5_SHIFT (5U)
76759 /*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
76760  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
76761  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
76762  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
76763  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
76764  */
76765 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT5_MASK)
76766 
76767 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT6_MASK (0x40U)
76768 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT6_SHIFT (6U)
76769 /*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
76770  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
76771  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
76772  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
76773  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
76774  */
76775 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT6_MASK)
76776 
76777 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT7_MASK (0x80U)
76778 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT7_SHIFT (7U)
76779 /*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
76780  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
76781  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
76782  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
76783  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
76784  */
76785 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT7_MASK)
76786 
76787 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT8_MASK (0x100U)
76788 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT8_SHIFT (8U)
76789 /*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
76790  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
76791  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
76792  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
76793  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
76794  */
76795 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT8_MASK)
76796 
76797 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT9_MASK (0x200U)
76798 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT9_SHIFT (9U)
76799 /*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
76800  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
76801  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
76802  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
76803  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
76804  */
76805 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT9_MASK)
76806 
76807 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT10_MASK (0x400U)
76808 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT10_SHIFT (10U)
76809 /*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
76810  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
76811  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
76812  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
76813  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
76814  */
76815 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT10_MASK)
76816 
76817 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT11_MASK (0x800U)
76818 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT11_SHIFT (11U)
76819 /*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
76820  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
76821  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
76822  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
76823  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
76824  */
76825 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT11_MASK)
76826 
76827 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT12_MASK (0x1000U)
76828 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT12_SHIFT (12U)
76829 /*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
76830  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
76831  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
76832  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
76833  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
76834  */
76835 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT12_MASK)
76836 
76837 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT13_MASK (0x2000U)
76838 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT13_SHIFT (13U)
76839 /*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
76840  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
76841  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
76842  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
76843  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
76844  */
76845 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT13_MASK)
76846 
76847 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT14_MASK (0x4000U)
76848 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT14_SHIFT (14U)
76849 /*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
76850  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
76851  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
76852  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
76853  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
76854  */
76855 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT14_MASK)
76856 
76857 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT15_MASK (0x8000U)
76858 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT15_SHIFT (15U)
76859 /*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
76860  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
76861  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
76862  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
76863  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
76864  */
76865 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT15_MASK)
76866 
76867 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT16_MASK (0x10000U)
76868 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT16_SHIFT (16U)
76869 /*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
76870  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
76871  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
76872  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
76873  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
76874  */
76875 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT16_MASK)
76876 
76877 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT17_MASK (0x20000U)
76878 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT17_SHIFT (17U)
76879 /*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
76880  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
76881  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
76882  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
76883  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
76884  */
76885 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT17_MASK)
76886 
76887 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT18_MASK (0x40000U)
76888 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT18_SHIFT (18U)
76889 /*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
76890  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
76891  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
76892  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
76893  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
76894  */
76895 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT18_MASK)
76896 
76897 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT19_MASK (0x80000U)
76898 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT19_SHIFT (19U)
76899 /*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
76900  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
76901  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
76902  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
76903  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
76904  */
76905 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT19_MASK)
76906 
76907 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT20_MASK (0x100000U)
76908 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT20_SHIFT (20U)
76909 /*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
76910  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
76911  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
76912  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
76913  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
76914  */
76915 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT20_MASK)
76916 
76917 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT21_MASK (0x200000U)
76918 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT21_SHIFT (21U)
76919 /*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
76920  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
76921  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
76922  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
76923  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
76924  */
76925 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT21_MASK)
76926 
76927 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT22_MASK (0x400000U)
76928 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT22_SHIFT (22U)
76929 /*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
76930  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
76931  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
76932  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
76933  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
76934  */
76935 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT22_MASK)
76936 
76937 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT23_MASK (0x800000U)
76938 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT23_SHIFT (23U)
76939 /*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
76940  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
76941  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
76942  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
76943  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
76944  */
76945 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT23_MASK)
76946 
76947 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT24_MASK (0x1000000U)
76948 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT24_SHIFT (24U)
76949 /*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
76950  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
76951  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
76952  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
76953  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
76954  */
76955 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT24_MASK)
76956 
76957 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT25_MASK (0x2000000U)
76958 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT25_SHIFT (25U)
76959 /*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
76960  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
76961  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
76962  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
76963  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
76964  */
76965 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT25_MASK)
76966 
76967 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT26_MASK (0x4000000U)
76968 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT26_SHIFT (26U)
76969 /*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
76970  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
76971  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
76972  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
76973  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
76974  */
76975 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT26_MASK)
76976 
76977 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT27_MASK (0x8000000U)
76978 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT27_SHIFT (27U)
76979 /*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
76980  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
76981  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
76982  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
76983  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
76984  */
76985 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT27_MASK)
76986 
76987 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT28_MASK (0x10000000U)
76988 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT28_SHIFT (28U)
76989 /*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
76990  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
76991  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
76992  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
76993  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
76994  */
76995 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT28_MASK)
76996 
76997 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT29_MASK (0x20000000U)
76998 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT29_SHIFT (29U)
76999 /*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
77000  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
77001  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
77002  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
77003  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
77004  */
77005 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT29_MASK)
77006 
77007 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT30_MASK (0x40000000U)
77008 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT30_SHIFT (30U)
77009 /*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
77010  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
77011  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
77012  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
77013  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
77014  */
77015 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT30_MASK)
77016 
77017 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT31_MASK (0x80000000U)
77018 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT31_SHIFT (31U)
77019 /*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
77020  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
77021  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
77022  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
77023  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
77024  */
77025 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT31_MASK)
77026 /*! @} */
77027 
77028 /* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W */
77029 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_COUNT (1U)
77030 
77031 /* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W */
77032 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_COUNT2 (2U)
77033 
77034 /*! @name MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */
77035 /*! @{ */
77036 
77037 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U)
77038 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U)
77039 /*! MBACSEL0 - Memory Block Access Control Select for block B
77040  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
77041  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
77042  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
77043  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
77044  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
77045  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
77046  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
77047  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
77048  */
77049 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0_MASK)
77050 
77051 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE0_MASK (0x8U)
77052 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE0_SHIFT (3U)
77053 /*! NSE0 - NonSecure Enable for block B
77054  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
77055  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
77056  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
77057  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
77058  */
77059 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE0_MASK)
77060 
77061 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U)
77062 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U)
77063 /*! MBACSEL1 - Memory Block Access Control Select for block B
77064  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
77065  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
77066  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
77067  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
77068  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
77069  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
77070  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
77071  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
77072  */
77073 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1_MASK)
77074 
77075 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE1_MASK (0x80U)
77076 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE1_SHIFT (7U)
77077 /*! NSE1 - NonSecure Enable for block B
77078  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
77079  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
77080  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
77081  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
77082  */
77083 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE1_MASK)
77084 
77085 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U)
77086 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U)
77087 /*! MBACSEL2 - Memory Block Access Control Select for block B
77088  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
77089  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
77090  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
77091  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
77092  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
77093  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
77094  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
77095  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
77096  */
77097 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2_MASK)
77098 
77099 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE2_MASK (0x800U)
77100 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE2_SHIFT (11U)
77101 /*! NSE2 - NonSecure Enable for block B
77102  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
77103  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
77104  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
77105  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
77106  */
77107 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE2_MASK)
77108 
77109 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
77110 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U)
77111 /*! MBACSEL3 - Memory Block Access Control Select for block B
77112  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
77113  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
77114  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
77115  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
77116  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
77117  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
77118  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
77119  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
77120  */
77121 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3_MASK)
77122 
77123 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE3_MASK (0x8000U)
77124 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE3_SHIFT (15U)
77125 /*! NSE3 - NonSecure Enable for block B
77126  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
77127  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
77128  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
77129  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
77130  */
77131 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE3_MASK)
77132 
77133 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
77134 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U)
77135 /*! MBACSEL4 - Memory Block Access Control Select for block B
77136  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
77137  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
77138  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
77139  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
77140  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
77141  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
77142  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
77143  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
77144  */
77145 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4_MASK)
77146 
77147 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE4_MASK (0x80000U)
77148 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE4_SHIFT (19U)
77149 /*! NSE4 - NonSecure Enable for block B
77150  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
77151  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
77152  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
77153  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
77154  */
77155 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE4_MASK)
77156 
77157 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
77158 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U)
77159 /*! MBACSEL5 - Memory Block Access Control Select for block B
77160  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
77161  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
77162  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
77163  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
77164  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
77165  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
77166  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
77167  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
77168  */
77169 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5_MASK)
77170 
77171 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE5_MASK (0x800000U)
77172 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE5_SHIFT (23U)
77173 /*! NSE5 - NonSecure Enable for block B
77174  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
77175  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
77176  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
77177  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
77178  */
77179 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE5_MASK)
77180 
77181 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
77182 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U)
77183 /*! MBACSEL6 - Memory Block Access Control Select for block B
77184  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
77185  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
77186  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
77187  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
77188  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
77189  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
77190  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
77191  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
77192  */
77193 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6_MASK)
77194 
77195 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE6_MASK (0x8000000U)
77196 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE6_SHIFT (27U)
77197 /*! NSE6 - NonSecure Enable for block B
77198  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
77199  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
77200  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
77201  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
77202  */
77203 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE6_MASK)
77204 
77205 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
77206 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U)
77207 /*! MBACSEL7 - Memory Block Access Control Select for block B
77208  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
77209  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
77210  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
77211  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
77212  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
77213  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
77214  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
77215  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
77216  */
77217 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7_MASK)
77218 
77219 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE7_MASK (0x80000000U)
77220 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE7_SHIFT (31U)
77221 /*! NSE7 - NonSecure Enable for block B
77222  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
77223  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
77224  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
77225  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
77226  */
77227 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE7_MASK)
77228 /*! @} */
77229 
77230 /* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W */
77231 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_COUNT (1U)
77232 
77233 /* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W */
77234 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_COUNT2 (1U)
77235 
77236 /*! @name MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
77237 /*! @{ */
77238 
77239 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT0_MASK (0x1U)
77240 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT0_SHIFT (0U)
77241 /*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
77242  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
77243  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
77244  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
77245  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
77246  */
77247 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT0_MASK)
77248 
77249 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT1_MASK (0x2U)
77250 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT1_SHIFT (1U)
77251 /*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
77252  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
77253  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
77254  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
77255  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
77256  */
77257 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT1_MASK)
77258 
77259 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT2_MASK (0x4U)
77260 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT2_SHIFT (2U)
77261 /*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
77262  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
77263  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
77264  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
77265  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
77266  */
77267 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT2_MASK)
77268 
77269 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT3_MASK (0x8U)
77270 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT3_SHIFT (3U)
77271 /*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
77272  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
77273  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
77274  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
77275  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
77276  */
77277 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT3_MASK)
77278 
77279 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT4_MASK (0x10U)
77280 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT4_SHIFT (4U)
77281 /*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
77282  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
77283  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
77284  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
77285  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
77286  */
77287 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT4_MASK)
77288 
77289 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT5_MASK (0x20U)
77290 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT5_SHIFT (5U)
77291 /*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
77292  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
77293  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
77294  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
77295  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
77296  */
77297 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT5_MASK)
77298 
77299 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT6_MASK (0x40U)
77300 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT6_SHIFT (6U)
77301 /*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
77302  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
77303  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
77304  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
77305  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
77306  */
77307 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT6_MASK)
77308 
77309 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT7_MASK (0x80U)
77310 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT7_SHIFT (7U)
77311 /*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
77312  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
77313  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
77314  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
77315  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
77316  */
77317 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT7_MASK)
77318 
77319 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT8_MASK (0x100U)
77320 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT8_SHIFT (8U)
77321 /*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
77322  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
77323  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
77324  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
77325  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
77326  */
77327 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT8_MASK)
77328 
77329 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT9_MASK (0x200U)
77330 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT9_SHIFT (9U)
77331 /*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
77332  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
77333  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
77334  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
77335  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
77336  */
77337 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT9_MASK)
77338 
77339 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT10_MASK (0x400U)
77340 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT10_SHIFT (10U)
77341 /*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
77342  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
77343  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
77344  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
77345  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
77346  */
77347 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT10_MASK)
77348 
77349 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT11_MASK (0x800U)
77350 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT11_SHIFT (11U)
77351 /*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
77352  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
77353  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
77354  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
77355  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
77356  */
77357 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT11_MASK)
77358 
77359 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT12_MASK (0x1000U)
77360 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT12_SHIFT (12U)
77361 /*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
77362  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
77363  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
77364  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
77365  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
77366  */
77367 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT12_MASK)
77368 
77369 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT13_MASK (0x2000U)
77370 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT13_SHIFT (13U)
77371 /*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
77372  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
77373  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
77374  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
77375  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
77376  */
77377 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT13_MASK)
77378 
77379 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT14_MASK (0x4000U)
77380 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT14_SHIFT (14U)
77381 /*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
77382  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
77383  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
77384  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
77385  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
77386  */
77387 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT14_MASK)
77388 
77389 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT15_MASK (0x8000U)
77390 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT15_SHIFT (15U)
77391 /*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
77392  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
77393  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
77394  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
77395  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
77396  */
77397 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT15_MASK)
77398 
77399 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT16_MASK (0x10000U)
77400 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT16_SHIFT (16U)
77401 /*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
77402  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
77403  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
77404  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
77405  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
77406  */
77407 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT16_MASK)
77408 
77409 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT17_MASK (0x20000U)
77410 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT17_SHIFT (17U)
77411 /*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
77412  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
77413  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
77414  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
77415  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
77416  */
77417 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT17_MASK)
77418 
77419 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT18_MASK (0x40000U)
77420 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT18_SHIFT (18U)
77421 /*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
77422  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
77423  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
77424  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
77425  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
77426  */
77427 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT18_MASK)
77428 
77429 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT19_MASK (0x80000U)
77430 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT19_SHIFT (19U)
77431 /*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
77432  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
77433  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
77434  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
77435  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
77436  */
77437 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT19_MASK)
77438 
77439 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT20_MASK (0x100000U)
77440 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT20_SHIFT (20U)
77441 /*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
77442  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
77443  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
77444  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
77445  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
77446  */
77447 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT20_MASK)
77448 
77449 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT21_MASK (0x200000U)
77450 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT21_SHIFT (21U)
77451 /*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
77452  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
77453  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
77454  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
77455  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
77456  */
77457 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT21_MASK)
77458 
77459 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT22_MASK (0x400000U)
77460 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT22_SHIFT (22U)
77461 /*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
77462  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
77463  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
77464  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
77465  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
77466  */
77467 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT22_MASK)
77468 
77469 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT23_MASK (0x800000U)
77470 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT23_SHIFT (23U)
77471 /*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
77472  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
77473  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
77474  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
77475  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
77476  */
77477 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT23_MASK)
77478 
77479 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT24_MASK (0x1000000U)
77480 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT24_SHIFT (24U)
77481 /*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
77482  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
77483  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
77484  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
77485  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
77486  */
77487 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT24_MASK)
77488 
77489 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT25_MASK (0x2000000U)
77490 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT25_SHIFT (25U)
77491 /*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
77492  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
77493  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
77494  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
77495  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
77496  */
77497 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT25_MASK)
77498 
77499 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT26_MASK (0x4000000U)
77500 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT26_SHIFT (26U)
77501 /*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
77502  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
77503  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
77504  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
77505  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
77506  */
77507 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT26_MASK)
77508 
77509 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT27_MASK (0x8000000U)
77510 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT27_SHIFT (27U)
77511 /*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
77512  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
77513  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
77514  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
77515  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
77516  */
77517 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT27_MASK)
77518 
77519 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT28_MASK (0x10000000U)
77520 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT28_SHIFT (28U)
77521 /*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
77522  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
77523  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
77524  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
77525  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
77526  */
77527 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT28_MASK)
77528 
77529 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT29_MASK (0x20000000U)
77530 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT29_SHIFT (29U)
77531 /*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
77532  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
77533  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
77534  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
77535  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
77536  */
77537 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT29_MASK)
77538 
77539 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT30_MASK (0x40000000U)
77540 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT30_SHIFT (30U)
77541 /*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
77542  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
77543  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
77544  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
77545  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
77546  */
77547 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT30_MASK)
77548 
77549 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT31_MASK (0x80000000U)
77550 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT31_SHIFT (31U)
77551 /*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
77552  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
77553  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
77554  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
77555  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
77556  */
77557 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT31_MASK)
77558 /*! @} */
77559 
77560 /* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W */
77561 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_COUNT (1U)
77562 
77563 /* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W */
77564 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_COUNT2 (1U)
77565 
77566 /*! @name MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */
77567 /*! @{ */
77568 
77569 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U)
77570 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U)
77571 /*! MBACSEL0 - Memory Block Access Control Select for block B
77572  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
77573  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
77574  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
77575  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
77576  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
77577  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
77578  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
77579  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
77580  */
77581 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0_MASK)
77582 
77583 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE0_MASK (0x8U)
77584 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE0_SHIFT (3U)
77585 /*! NSE0 - NonSecure Enable for block B
77586  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
77587  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
77588  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
77589  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
77590  */
77591 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE0_MASK)
77592 
77593 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U)
77594 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U)
77595 /*! MBACSEL1 - Memory Block Access Control Select for block B
77596  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
77597  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
77598  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
77599  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
77600  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
77601  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
77602  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
77603  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
77604  */
77605 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1_MASK)
77606 
77607 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE1_MASK (0x80U)
77608 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE1_SHIFT (7U)
77609 /*! NSE1 - NonSecure Enable for block B
77610  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
77611  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
77612  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
77613  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
77614  */
77615 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE1_MASK)
77616 
77617 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U)
77618 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U)
77619 /*! MBACSEL2 - Memory Block Access Control Select for block B
77620  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
77621  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
77622  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
77623  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
77624  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
77625  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
77626  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
77627  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
77628  */
77629 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2_MASK)
77630 
77631 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE2_MASK (0x800U)
77632 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE2_SHIFT (11U)
77633 /*! NSE2 - NonSecure Enable for block B
77634  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
77635  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
77636  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
77637  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
77638  */
77639 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE2_MASK)
77640 
77641 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
77642 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U)
77643 /*! MBACSEL3 - Memory Block Access Control Select for block B
77644  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
77645  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
77646  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
77647  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
77648  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
77649  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
77650  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
77651  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
77652  */
77653 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3_MASK)
77654 
77655 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE3_MASK (0x8000U)
77656 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE3_SHIFT (15U)
77657 /*! NSE3 - NonSecure Enable for block B
77658  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
77659  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
77660  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
77661  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
77662  */
77663 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE3_MASK)
77664 
77665 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
77666 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U)
77667 /*! MBACSEL4 - Memory Block Access Control Select for block B
77668  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
77669  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
77670  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
77671  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
77672  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
77673  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
77674  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
77675  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
77676  */
77677 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4_MASK)
77678 
77679 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE4_MASK (0x80000U)
77680 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE4_SHIFT (19U)
77681 /*! NSE4 - NonSecure Enable for block B
77682  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
77683  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
77684  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
77685  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
77686  */
77687 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE4_MASK)
77688 
77689 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
77690 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U)
77691 /*! MBACSEL5 - Memory Block Access Control Select for block B
77692  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
77693  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
77694  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
77695  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
77696  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
77697  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
77698  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
77699  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
77700  */
77701 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5_MASK)
77702 
77703 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE5_MASK (0x800000U)
77704 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE5_SHIFT (23U)
77705 /*! NSE5 - NonSecure Enable for block B
77706  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
77707  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
77708  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
77709  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
77710  */
77711 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE5_MASK)
77712 
77713 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
77714 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U)
77715 /*! MBACSEL6 - Memory Block Access Control Select for block B
77716  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
77717  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
77718  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
77719  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
77720  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
77721  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
77722  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
77723  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
77724  */
77725 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6_MASK)
77726 
77727 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE6_MASK (0x8000000U)
77728 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE6_SHIFT (27U)
77729 /*! NSE6 - NonSecure Enable for block B
77730  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
77731  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
77732  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
77733  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
77734  */
77735 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE6_MASK)
77736 
77737 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
77738 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U)
77739 /*! MBACSEL7 - Memory Block Access Control Select for block B
77740  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
77741  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
77742  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
77743  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
77744  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
77745  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
77746  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
77747  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
77748  */
77749 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7_MASK)
77750 
77751 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE7_MASK (0x80000000U)
77752 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE7_SHIFT (31U)
77753 /*! NSE7 - NonSecure Enable for block B
77754  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
77755  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
77756  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
77757  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
77758  */
77759 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE7_MASK)
77760 /*! @} */
77761 
77762 /* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W */
77763 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_COUNT (1U)
77764 
77765 /* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W */
77766 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_COUNT2 (1U)
77767 
77768 /*! @name MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
77769 /*! @{ */
77770 
77771 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT0_MASK (0x1U)
77772 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT0_SHIFT (0U)
77773 /*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
77774  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
77775  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
77776  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
77777  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
77778  */
77779 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT0_MASK)
77780 
77781 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT1_MASK (0x2U)
77782 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT1_SHIFT (1U)
77783 /*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
77784  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
77785  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
77786  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
77787  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
77788  */
77789 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT1_MASK)
77790 
77791 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT2_MASK (0x4U)
77792 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT2_SHIFT (2U)
77793 /*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
77794  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
77795  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
77796  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
77797  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
77798  */
77799 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT2_MASK)
77800 
77801 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT3_MASK (0x8U)
77802 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT3_SHIFT (3U)
77803 /*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
77804  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
77805  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
77806  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
77807  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
77808  */
77809 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT3_MASK)
77810 
77811 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT4_MASK (0x10U)
77812 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT4_SHIFT (4U)
77813 /*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
77814  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
77815  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
77816  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
77817  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
77818  */
77819 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT4_MASK)
77820 
77821 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT5_MASK (0x20U)
77822 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT5_SHIFT (5U)
77823 /*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
77824  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
77825  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
77826  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
77827  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
77828  */
77829 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT5_MASK)
77830 
77831 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT6_MASK (0x40U)
77832 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT6_SHIFT (6U)
77833 /*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
77834  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
77835  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
77836  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
77837  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
77838  */
77839 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT6_MASK)
77840 
77841 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT7_MASK (0x80U)
77842 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT7_SHIFT (7U)
77843 /*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
77844  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
77845  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
77846  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
77847  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
77848  */
77849 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT7_MASK)
77850 
77851 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT8_MASK (0x100U)
77852 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT8_SHIFT (8U)
77853 /*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
77854  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
77855  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
77856  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
77857  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
77858  */
77859 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT8_MASK)
77860 
77861 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT9_MASK (0x200U)
77862 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT9_SHIFT (9U)
77863 /*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
77864  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
77865  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
77866  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
77867  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
77868  */
77869 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT9_MASK)
77870 
77871 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT10_MASK (0x400U)
77872 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT10_SHIFT (10U)
77873 /*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
77874  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
77875  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
77876  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
77877  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
77878  */
77879 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT10_MASK)
77880 
77881 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT11_MASK (0x800U)
77882 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT11_SHIFT (11U)
77883 /*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
77884  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
77885  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
77886  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
77887  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
77888  */
77889 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT11_MASK)
77890 
77891 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT12_MASK (0x1000U)
77892 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT12_SHIFT (12U)
77893 /*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
77894  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
77895  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
77896  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
77897  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
77898  */
77899 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT12_MASK)
77900 
77901 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT13_MASK (0x2000U)
77902 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT13_SHIFT (13U)
77903 /*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
77904  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
77905  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
77906  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
77907  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
77908  */
77909 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT13_MASK)
77910 
77911 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT14_MASK (0x4000U)
77912 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT14_SHIFT (14U)
77913 /*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
77914  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
77915  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
77916  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
77917  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
77918  */
77919 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT14_MASK)
77920 
77921 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT15_MASK (0x8000U)
77922 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT15_SHIFT (15U)
77923 /*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
77924  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
77925  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
77926  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
77927  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
77928  */
77929 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT15_MASK)
77930 
77931 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT16_MASK (0x10000U)
77932 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT16_SHIFT (16U)
77933 /*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
77934  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
77935  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
77936  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
77937  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
77938  */
77939 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT16_MASK)
77940 
77941 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT17_MASK (0x20000U)
77942 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT17_SHIFT (17U)
77943 /*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
77944  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
77945  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
77946  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
77947  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
77948  */
77949 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT17_MASK)
77950 
77951 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT18_MASK (0x40000U)
77952 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT18_SHIFT (18U)
77953 /*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
77954  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
77955  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
77956  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
77957  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
77958  */
77959 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT18_MASK)
77960 
77961 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT19_MASK (0x80000U)
77962 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT19_SHIFT (19U)
77963 /*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
77964  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
77965  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
77966  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
77967  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
77968  */
77969 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT19_MASK)
77970 
77971 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT20_MASK (0x100000U)
77972 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT20_SHIFT (20U)
77973 /*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
77974  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
77975  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
77976  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
77977  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
77978  */
77979 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT20_MASK)
77980 
77981 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT21_MASK (0x200000U)
77982 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT21_SHIFT (21U)
77983 /*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
77984  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
77985  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
77986  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
77987  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
77988  */
77989 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT21_MASK)
77990 
77991 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT22_MASK (0x400000U)
77992 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT22_SHIFT (22U)
77993 /*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
77994  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
77995  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
77996  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
77997  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
77998  */
77999 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT22_MASK)
78000 
78001 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT23_MASK (0x800000U)
78002 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT23_SHIFT (23U)
78003 /*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
78004  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
78005  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
78006  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
78007  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
78008  */
78009 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT23_MASK)
78010 
78011 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT24_MASK (0x1000000U)
78012 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT24_SHIFT (24U)
78013 /*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
78014  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
78015  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
78016  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
78017  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
78018  */
78019 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT24_MASK)
78020 
78021 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT25_MASK (0x2000000U)
78022 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT25_SHIFT (25U)
78023 /*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
78024  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
78025  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
78026  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
78027  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
78028  */
78029 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT25_MASK)
78030 
78031 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT26_MASK (0x4000000U)
78032 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT26_SHIFT (26U)
78033 /*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
78034  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
78035  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
78036  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
78037  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
78038  */
78039 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT26_MASK)
78040 
78041 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT27_MASK (0x8000000U)
78042 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT27_SHIFT (27U)
78043 /*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
78044  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
78045  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
78046  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
78047  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
78048  */
78049 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT27_MASK)
78050 
78051 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT28_MASK (0x10000000U)
78052 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT28_SHIFT (28U)
78053 /*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
78054  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
78055  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
78056  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
78057  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
78058  */
78059 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT28_MASK)
78060 
78061 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT29_MASK (0x20000000U)
78062 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT29_SHIFT (29U)
78063 /*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
78064  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
78065  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
78066  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
78067  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
78068  */
78069 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT29_MASK)
78070 
78071 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT30_MASK (0x40000000U)
78072 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT30_SHIFT (30U)
78073 /*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
78074  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
78075  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
78076  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
78077  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
78078  */
78079 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT30_MASK)
78080 
78081 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT31_MASK (0x80000000U)
78082 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT31_SHIFT (31U)
78083 /*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
78084  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
78085  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
78086  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
78087  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
78088  */
78089 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT31_MASK)
78090 /*! @} */
78091 
78092 /* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W */
78093 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_COUNT (1U)
78094 
78095 /* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W */
78096 #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_COUNT2 (1U)
78097 
78098 
78099 /*!
78100  * @}
78101  */ /* end of group TRDC_Register_Masks */
78102 
78103 
78104 /* TRDC - Peripheral instance base addresses */
78105 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
78106   /** Peripheral TRDC base address */
78107   #define TRDC_BASE                                (0x500C7000u)
78108   /** Peripheral TRDC base address */
78109   #define TRDC_BASE_NS                             (0x400C7000u)
78110   /** Peripheral TRDC base pointer */
78111   #define TRDC                                     ((TRDC_Type *)TRDC_BASE)
78112   /** Peripheral TRDC base pointer */
78113   #define TRDC_NS                                  ((TRDC_Type *)TRDC_BASE_NS)
78114   /** Array initializer of TRDC peripheral base addresses */
78115   #define TRDC_BASE_ADDRS                          { TRDC_BASE }
78116   /** Array initializer of TRDC peripheral base pointers */
78117   #define TRDC_BASE_PTRS                           { TRDC }
78118   /** Array initializer of TRDC peripheral base addresses */
78119   #define TRDC_BASE_ADDRS_NS                       { TRDC_BASE_NS }
78120   /** Array initializer of TRDC peripheral base pointers */
78121   #define TRDC_BASE_PTRS_NS                        { TRDC_NS }
78122 #else
78123   /** Peripheral TRDC base address */
78124   #define TRDC_BASE                                (0x400C7000u)
78125   /** Peripheral TRDC base pointer */
78126   #define TRDC                                     ((TRDC_Type *)TRDC_BASE)
78127   /** Array initializer of TRDC peripheral base addresses */
78128   #define TRDC_BASE_ADDRS                          { TRDC_BASE }
78129   /** Array initializer of TRDC peripheral base pointers */
78130   #define TRDC_BASE_PTRS                           { TRDC }
78131 #endif
78132 #define MBC0_MEMORY_CFG_WORD_COUNT {1,2,4,1}
78133 #define MBC1_MEMORY_CFG_WORD_COUNT {1,1,1,1}
78134 #define MBC2_MEMORY_CFG_WORD_COUNT {9,6,1,1}
78135 #define MBC3_MEMORY_CFG_WORD_COUNT {3,0,0,0}
78136 #define MBC_MEMORY_CFG_WORD_COUNT {MBC0_MEMORY_CFG_WORD_COUNT , MBC1_MEMORY_CFG_WORD_COUNT, MBC2_MEMORY_CFG_WORD_COUNT, MBC3_MEMORY_CFG_WORD_COUNT}
78137 #define MBC0_MEMORY_NSE_WORD_COUNT {1,1,1,1}
78138 #define MBC1_MEMORY_NSE_WORD_COUNT {1,1,1,1}
78139 #define MBC2_MEMORY_NSE_WORD_COUNT {3,2,1,1}
78140 #define MBC3_MEMORY_NSE_WORD_COUNT {1,0,0,0}
78141 #define MBC_MEMORY_NSE_WORD_COUNT {MBC0_MEMORY_NSE_WORD_COUNT , MBC1_MEMORY_NSE_WORD_COUNT, MBC2_MEMORY_NSE_WORD_COUNT, MBC3_MEMORY_NSE_WORD_COUNT}
78142 
78143 
78144 /*!
78145  * @}
78146  */ /* end of group TRDC_Peripheral_Access_Layer */
78147 
78148 
78149 /* ----------------------------------------------------------------------------
78150    -- TSI Peripheral Access Layer
78151    ---------------------------------------------------------------------------- */
78152 
78153 /*!
78154  * @addtogroup TSI_Peripheral_Access_Layer TSI Peripheral Access Layer
78155  * @{
78156  */
78157 
78158 /** TSI - Register Layout Typedef */
78159 typedef struct {
78160   union {                                          /* offset: 0x0 */
78161     __IO uint32_t CONFIG_MUTUAL;                     /**< TSI CONFIG (TSI_CONFIG) for Mutual-Capacitor, offset: 0x0 */
78162     __IO uint32_t CONFIG;                            /**< TSI CONFIG (TSI_CONFIG) for Self-Capacitor, offset: 0x0 */
78163   };
78164   __IO uint32_t TSHD;                              /**< TSI Threshold, offset: 0x4 */
78165   __IO uint32_t GENCS;                             /**< TSI General Control and Status, offset: 0x8 */
78166   __IO uint32_t MUL;                               /**< TSI Mutual-Capacitance, offset: 0xC */
78167   __IO uint32_t SINC;                              /**< TSI SINC Filter, offset: 0x10 */
78168   __IO uint32_t SSC0;                              /**< TSI SSC 0, offset: 0x14 */
78169   __IO uint32_t SSC1;                              /**< TSI SSC 1, offset: 0x18 */
78170   __IO uint32_t SSC2;                              /**< TSI SSC 2, offset: 0x1C */
78171   __IO uint32_t BASELINE;                          /**< TSI Baseline, offset: 0x20 */
78172   __IO uint32_t CHMERGE;                           /**< TSI Channel Merge, offset: 0x24 */
78173   __IO uint32_t SHIELD;                            /**< TSI Shield, offset: 0x28 */
78174        uint8_t RESERVED_0[212];
78175   __IO uint32_t DATA;                              /**< TSI Data and Status, offset: 0x100 */
78176        uint8_t RESERVED_1[4];
78177   __IO uint32_t MISC;                              /**< TSI Miscellaneous, offset: 0x108 */
78178   __IO uint32_t TRIG;                              /**< TSI AUTO TRIG, offset: 0x10C */
78179 } TSI_Type;
78180 
78181 /* ----------------------------------------------------------------------------
78182    -- TSI Register Masks
78183    ---------------------------------------------------------------------------- */
78184 
78185 /*!
78186  * @addtogroup TSI_Register_Masks TSI Register Masks
78187  * @{
78188  */
78189 
78190 /*! @name CONFIG_MUTUAL - TSI CONFIG (TSI_CONFIG) for Mutual-Capacitor */
78191 /*! @{ */
78192 
78193 #define TSI_CONFIG_MUTUAL_MODE_MASK              (0x1U)
78194 #define TSI_CONFIG_MUTUAL_MODE_SHIFT             (0U)
78195 /*! MODE - Mode
78196  *  0b0..Self capacitance
78197  *  0b1..Mutual capacitance
78198  */
78199 #define TSI_CONFIG_MUTUAL_MODE(x)                (((uint32_t)(((uint32_t)(x)) << TSI_CONFIG_MUTUAL_MODE_SHIFT)) & TSI_CONFIG_MUTUAL_MODE_MASK)
78200 
78201 #define TSI_CONFIG_MUTUAL_M_NMIRROR_MASK         (0x6U)
78202 #define TSI_CONFIG_MUTUAL_M_NMIRROR_SHIFT        (1U)
78203 /*! M_NMIRROR - NMOS Current Mirror
78204  *  0b00..m = 1
78205  *  0b01..m = 2
78206  *  0b10..m = 3
78207  *  0b11..m = 4
78208  */
78209 #define TSI_CONFIG_MUTUAL_M_NMIRROR(x)           (((uint32_t)(((uint32_t)(x)) << TSI_CONFIG_MUTUAL_M_NMIRROR_SHIFT)) & TSI_CONFIG_MUTUAL_M_NMIRROR_MASK)
78210 
78211 #define TSI_CONFIG_MUTUAL_M_PMIRRORR_MASK        (0x18U)
78212 #define TSI_CONFIG_MUTUAL_M_PMIRRORR_SHIFT       (3U)
78213 /*! M_PMIRRORR - PMOS Current Mirror on Right Side
78214  *  0b00..m = 1
78215  *  0b01..m = 2
78216  *  0b10..m = 3
78217  *  0b11..m = 4
78218  */
78219 #define TSI_CONFIG_MUTUAL_M_PMIRRORR(x)          (((uint32_t)(((uint32_t)(x)) << TSI_CONFIG_MUTUAL_M_PMIRRORR_SHIFT)) & TSI_CONFIG_MUTUAL_M_PMIRRORR_MASK)
78220 
78221 #define TSI_CONFIG_MUTUAL_M_PMIRRORL_MASK        (0xE0U)
78222 #define TSI_CONFIG_MUTUAL_M_PMIRRORL_SHIFT       (5U)
78223 /*! M_PMIRRORL - PMOS Current Mirror on Left Side
78224  *  0b000..m = 4
78225  *  0b001..m = 8
78226  *  0b010..m = 12
78227  *  0b011..m = 16
78228  *  0b100..m = 20
78229  *  0b101..m = 24
78230  *  0b110..m = 28
78231  *  0b111..m = 32
78232  */
78233 #define TSI_CONFIG_MUTUAL_M_PMIRRORL(x)          (((uint32_t)(((uint32_t)(x)) << TSI_CONFIG_MUTUAL_M_PMIRRORL_SHIFT)) & TSI_CONFIG_MUTUAL_M_PMIRRORL_MASK)
78234 
78235 #define TSI_CONFIG_MUTUAL_M_SEL_RX_MASK          (0x1F00U)
78236 #define TSI_CONFIG_MUTUAL_M_SEL_RX_SHIFT         (8U)
78237 /*! M_SEL_RX - Mutual-Capacitance RX Channel Selection
78238  *  0b00000..TSI[8]
78239  *  0b00001..TSI[9]
78240  *  0b00010..TSI[10]
78241  *  0b00011..TSI[11]
78242  *  0b00100..TSI[12]
78243  *  0b00101..TSI[13]
78244  *  0b00110..TSI[14]
78245  *  0b00111..TSI[15]
78246  *  0b01000..TSI[16]
78247  *  0b01001..TSI[17]
78248  *  0b01010..TSI[18]
78249  *  0b01011..TSI[19]
78250  *  0b01100..TSI[20]
78251  *  0b01101..TSI[21]
78252  *  0b01110..TSI[22]
78253  *  0b01111..TSI[23]
78254  *  0b10000..TSI[24]
78255  */
78256 #define TSI_CONFIG_MUTUAL_M_SEL_RX(x)            (((uint32_t)(((uint32_t)(x)) << TSI_CONFIG_MUTUAL_M_SEL_RX_SHIFT)) & TSI_CONFIG_MUTUAL_M_SEL_RX_MASK)
78257 
78258 #define TSI_CONFIG_MUTUAL_M_SEL_TX_MASK          (0xE000U)
78259 #define TSI_CONFIG_MUTUAL_M_SEL_TX_SHIFT         (13U)
78260 /*! M_SEL_TX - Mutual-Capacitance TX Channel Selection
78261  *  0b000..TSI[0]
78262  *  0b001..TSI[1]
78263  *  0b010..TSI[2]
78264  *  0b011..TSI[3]
78265  *  0b100..TSI[4]
78266  *  0b101..TSI[5]
78267  *  0b110..TSI[6]
78268  *  0b111..TSI[7]
78269  */
78270 #define TSI_CONFIG_MUTUAL_M_SEL_TX(x)            (((uint32_t)(((uint32_t)(x)) << TSI_CONFIG_MUTUAL_M_SEL_TX_SHIFT)) & TSI_CONFIG_MUTUAL_M_SEL_TX_MASK)
78271 
78272 #define TSI_CONFIG_MUTUAL_M_CNT_EN_MASK          (0x10000U)
78273 #define TSI_CONFIG_MUTUAL_M_CNT_EN_SHIFT         (16U)
78274 /*! M_CNT_EN - Mutual-Capacitance Counter Enable
78275  *  0b0..Disables
78276  *  0b1..Enables
78277  */
78278 #define TSI_CONFIG_MUTUAL_M_CNT_EN(x)            (((uint32_t)(((uint32_t)(x)) << TSI_CONFIG_MUTUAL_M_CNT_EN_SHIFT)) & TSI_CONFIG_MUTUAL_M_CNT_EN_MASK)
78279 
78280 #define TSI_CONFIG_MUTUAL_M_TX_PD_EN_MASK        (0x20000U)
78281 #define TSI_CONFIG_MUTUAL_M_TX_PD_EN_SHIFT       (17U)
78282 /*! M_TX_PD_EN - Mutual-Capacitance TX Pulldown Enable
78283  *  0b0..Disables
78284  *  0b1..Enables
78285  */
78286 #define TSI_CONFIG_MUTUAL_M_TX_PD_EN(x)          (((uint32_t)(((uint32_t)(x)) << TSI_CONFIG_MUTUAL_M_TX_PD_EN_SHIFT)) & TSI_CONFIG_MUTUAL_M_TX_PD_EN_MASK)
78287 
78288 #define TSI_CONFIG_MUTUAL_M_SEN_BOOST_MASK       (0x7C0000U)
78289 #define TSI_CONFIG_MUTUAL_M_SEN_BOOST_SHIFT      (18U)
78290 /*! M_SEN_BOOST - Mutual-Capacitance Sensitivity Boost
78291  *  0b00000..0 uA
78292  *  0b00001..2 uA
78293  *  0b00010..4 uA
78294  *  0b00011..6 uA
78295  *  0b00100..8 uA
78296  *  0b00101..10 uA
78297  *  0b00110..12 uA
78298  *  0b00111..14 uA
78299  *  0b1xxxx..2 * n uA
78300  *  0b11111..62 uA
78301  */
78302 #define TSI_CONFIG_MUTUAL_M_SEN_BOOST(x)         (((uint32_t)(((uint32_t)(x)) << TSI_CONFIG_MUTUAL_M_SEN_BOOST_SHIFT)) & TSI_CONFIG_MUTUAL_M_SEN_BOOST_MASK)
78303 
78304 #define TSI_CONFIG_MUTUAL_M_PRE_RES_MASK         (0x1C000000U)
78305 #define TSI_CONFIG_MUTUAL_M_PRE_RES_SHIFT        (26U)
78306 /*! M_PRE_RES - Mutual-Capacitance Precharge Resistor
78307  *  0b000..1 kΩ
78308  *  0b001..2 kΩ
78309  *  0b010..3 kΩ
78310  *  0b011..4 kΩ
78311  *  0b100..5 kΩ
78312  *  0b101..6 kΩ
78313  *  0b110..7 kΩ
78314  *  0b111..8 kΩ
78315  */
78316 #define TSI_CONFIG_MUTUAL_M_PRE_RES(x)           (((uint32_t)(((uint32_t)(x)) << TSI_CONFIG_MUTUAL_M_PRE_RES_SHIFT)) & TSI_CONFIG_MUTUAL_M_PRE_RES_MASK)
78317 
78318 #define TSI_CONFIG_MUTUAL_M_PRE_CURRENT_MASK     (0xE0000000U)
78319 #define TSI_CONFIG_MUTUAL_M_PRE_CURRENT_SHIFT    (29U)
78320 /*! M_PRE_CURRENT - Mutual-Capacitance Precharge Current
78321  *  0b000..1 uA
78322  *  0b001..2 uA
78323  *  0b010..3 uA
78324  *  0b011..4 uA
78325  *  0b100..5 uA
78326  *  0b101..6 uA
78327  *  0b110..7 uA
78328  *  0b111..8 uA
78329  */
78330 #define TSI_CONFIG_MUTUAL_M_PRE_CURRENT(x)       (((uint32_t)(((uint32_t)(x)) << TSI_CONFIG_MUTUAL_M_PRE_CURRENT_SHIFT)) & TSI_CONFIG_MUTUAL_M_PRE_CURRENT_MASK)
78331 /*! @} */
78332 
78333 /*! @name CONFIG - TSI CONFIG (TSI_CONFIG) for Self-Capacitor */
78334 /*! @{ */
78335 
78336 #define TSI_CONFIG_MODE_MASK                     (0x1U)
78337 #define TSI_CONFIG_MODE_SHIFT                    (0U)
78338 /*! MODE - Mode
78339  *  0b0..Self capacitance
78340  *  0b1..Mutual capacitance
78341  */
78342 #define TSI_CONFIG_MODE(x)                       (((uint32_t)(((uint32_t)(x)) << TSI_CONFIG_MODE_SHIFT)) & TSI_CONFIG_MODE_MASK)
78343 
78344 #define TSI_CONFIG_TSICH_MASK                    (0x3EU)
78345 #define TSI_CONFIG_TSICH_SHIFT                   (1U)
78346 /*! TSICH - TSI Channel
78347  *  0b00000..Channel 0
78348  *  0b00001..Channel 1
78349  *  0b00010..Channel 2
78350  *  0b00011..Channel 3
78351  *  0b00100..Channel 4
78352  *  0b00101..Channel 5
78353  *  0b00110..Channel 6
78354  *  0b00111..Channel 7
78355  *  0b01000..Channel 8
78356  *  0b01001..Channel 9
78357  *  0b01010..Channel 10
78358  *  0b01011..Channel 11
78359  *  0b01100..Channel 12
78360  *  0b01101..Channel 13
78361  *  0b01110..Channel 14
78362  *  0b01111..Channel 15
78363  *  0b10000..Channel 16
78364  *  0b10001..Channel 17
78365  *  0b10010..Channel 18
78366  *  0b10011..Channel 19
78367  *  0b10100..Channel 20
78368  *  0b10101..Channel 21
78369  *  0b10110..Channel 22
78370  *  0b10111..Channel 23
78371  *  0b11000..Channel 24
78372  */
78373 #define TSI_CONFIG_TSICH(x)                      (((uint32_t)(((uint32_t)(x)) << TSI_CONFIG_TSICH_SHIFT)) & TSI_CONFIG_TSICH_MASK)
78374 
78375 #define TSI_CONFIG_S_NOISE_MASK                  (0x80000U)
78376 #define TSI_CONFIG_S_NOISE_SHIFT                 (19U)
78377 /*! S_NOISE - Self-Capacitance Noise Cancelation
78378  *  0b0..Disables
78379  *  0b1..Enables
78380  */
78381 #define TSI_CONFIG_S_NOISE(x)                    (((uint32_t)(((uint32_t)(x)) << TSI_CONFIG_S_NOISE_SHIFT)) & TSI_CONFIG_S_NOISE_MASK)
78382 
78383 #define TSI_CONFIG_S_XCH_MASK                    (0x700000U)
78384 #define TSI_CONFIG_S_XCH_SHIFT                   (20U)
78385 /*! S_XCH - Self-Capacitance Charge Current Multiple
78386  *  0b000..1 / 16
78387  *  0b001..1 / 8
78388  *  0b010..1 / 4
78389  *  0b011..1 / 2
78390  */
78391 #define TSI_CONFIG_S_XCH(x)                      (((uint32_t)(((uint32_t)(x)) << TSI_CONFIG_S_XCH_SHIFT)) & TSI_CONFIG_S_XCH_MASK)
78392 
78393 #define TSI_CONFIG_S_XIN_MASK                    (0x800000U)
78394 #define TSI_CONFIG_S_XIN_SHIFT                   (23U)
78395 /*! S_XIN - Self-Capacitance Input Current Multiple
78396  *  0b0..1 / 8
78397  *  0b1..1 / 4
78398  */
78399 #define TSI_CONFIG_S_XIN(x)                      (((uint32_t)(((uint32_t)(x)) << TSI_CONFIG_S_XIN_SHIFT)) & TSI_CONFIG_S_XIN_MASK)
78400 
78401 #define TSI_CONFIG_S_CTRIM_MASK                  (0x7000000U)
78402 #define TSI_CONFIG_S_CTRIM_SHIFT                 (24U)
78403 /*! S_CTRIM - Capacitor Trim Setting
78404  *  0b000..2.5 pF
78405  *  0b001..5.0 pF
78406  *  0b010..7.5 pF
78407  *  0b011..10 pF
78408  *  0b100..12.5 pF
78409  *  0b101..15.0 pF
78410  *  0b110..17.5 pF
78411  *  0b111..20 pF
78412  */
78413 #define TSI_CONFIG_S_CTRIM(x)                    (((uint32_t)(((uint32_t)(x)) << TSI_CONFIG_S_CTRIM_SHIFT)) & TSI_CONFIG_S_CTRIM_MASK)
78414 
78415 #define TSI_CONFIG_S_SEN_MASK                    (0x8000000U)
78416 #define TSI_CONFIG_S_SEN_SHIFT                   (27U)
78417 /*! S_SEN - Self-Capacitance Sensitivity Boost
78418  *  0b0..Disables
78419  *  0b1..Enables
78420  */
78421 #define TSI_CONFIG_S_SEN(x)                      (((uint32_t)(((uint32_t)(x)) << TSI_CONFIG_S_SEN_SHIFT)) & TSI_CONFIG_S_SEN_MASK)
78422 
78423 #define TSI_CONFIG_S_XDN_MASK                    (0x70000000U)
78424 #define TSI_CONFIG_S_XDN_SHIFT                   (28U)
78425 /*! S_XDN - Self-Capacitance Discharge Current Multiple
78426  *  0b000..1 / 16
78427  *  0b001..1 / 8
78428  *  0b010..1 / 4
78429  *  0b011..1 / 2
78430  */
78431 #define TSI_CONFIG_S_XDN(x)                      (((uint32_t)(((uint32_t)(x)) << TSI_CONFIG_S_XDN_SHIFT)) & TSI_CONFIG_S_XDN_MASK)
78432 
78433 #define TSI_CONFIG_S_XIN_ADD_MASK                (0x80000000U)
78434 #define TSI_CONFIG_S_XIN_ADD_SHIFT               (31U)
78435 /*! S_XIN_ADD - S_XIN Adjust Ratio
78436  *  0b0..Disables; S_XIN = 0 for 1 / 4, S_XIN = 1 for 1 / 8
78437  *  0b1..Enables; S_XIN = 0 for 1 / 8, S_XIN = 1 for 1 / 16
78438  */
78439 #define TSI_CONFIG_S_XIN_ADD(x)                  (((uint32_t)(((uint32_t)(x)) << TSI_CONFIG_S_XIN_ADD_SHIFT)) & TSI_CONFIG_S_XIN_ADD_MASK)
78440 /*! @} */
78441 
78442 /*! @name TSHD - TSI Threshold */
78443 /*! @{ */
78444 
78445 #define TSI_TSHD_THRESL_MASK                     (0xFFFFU)
78446 #define TSI_TSHD_THRESL_SHIFT                    (0U)
78447 /*! THRESL - TSI Wakeup Channel Low Threshold */
78448 #define TSI_TSHD_THRESL(x)                       (((uint32_t)(((uint32_t)(x)) << TSI_TSHD_THRESL_SHIFT)) & TSI_TSHD_THRESL_MASK)
78449 
78450 #define TSI_TSHD_THRESH_MASK                     (0xFFFF0000U)
78451 #define TSI_TSHD_THRESH_SHIFT                    (16U)
78452 /*! THRESH - TSI Wakeup Channel High Threshold */
78453 #define TSI_TSHD_THRESH(x)                       (((uint32_t)(((uint32_t)(x)) << TSI_TSHD_THRESH_SHIFT)) & TSI_TSHD_THRESH_MASK)
78454 /*! @} */
78455 
78456 /*! @name GENCS - TSI General Control and Status */
78457 /*! @{ */
78458 
78459 #define TSI_GENCS_DMAEN_EOS_MASK                 (0x1U)
78460 #define TSI_GENCS_DMAEN_EOS_SHIFT                (0U)
78461 /*! DMAEN_EOS - In-Progress DMA Transfer Request Enable
78462  *  0b0..Disables
78463  *  0b1..Enables
78464  */
78465 #define TSI_GENCS_DMAEN_EOS(x)                   (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_DMAEN_EOS_SHIFT)) & TSI_GENCS_DMAEN_EOS_MASK)
78466 
78467 #define TSI_GENCS_DMAEN_OUTRG_MASK               (0x4U)
78468 #define TSI_GENCS_DMAEN_OUTRG_SHIFT              (2U)
78469 /*! DMAEN_OUTRG - Out-of-Range DMA Transfer Request Enable
78470  *  0b0..Disables
78471  *  0b1..Enables
78472  */
78473 #define TSI_GENCS_DMAEN_OUTRG(x)                 (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_DMAEN_OUTRG_SHIFT)) & TSI_GENCS_DMAEN_OUTRG_MASK)
78474 
78475 #define TSI_GENCS_STM_MASK                       (0x8U)
78476 #define TSI_GENCS_STM_SHIFT                      (3U)
78477 /*! STM - Scan Trigger Mode
78478  *  0b0..Software trigger scan
78479  *  0b1..Hardware trigger scan
78480  */
78481 #define TSI_GENCS_STM(x)                         (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_STM_SHIFT)) & TSI_GENCS_STM_MASK)
78482 
78483 #define TSI_GENCS_STPE_MASK                      (0x10U)
78484 #define TSI_GENCS_STPE_SHIFT                     (4U)
78485 /*! STPE - TSI Stop Enable
78486  *  0b0..Disables
78487  *  0b1..Enables
78488  */
78489 #define TSI_GENCS_STPE(x)                        (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_STPE_SHIFT)) & TSI_GENCS_STPE_MASK)
78490 
78491 #define TSI_GENCS_TSIEN_MASK                     (0x20U)
78492 #define TSI_GENCS_TSIEN_SHIFT                    (5U)
78493 /*! TSIEN - TSI Enable
78494  *  0b0..Disables
78495  *  0b1..Enables
78496  */
78497 #define TSI_GENCS_TSIEN(x)                       (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_TSIEN_SHIFT)) & TSI_GENCS_TSIEN_MASK)
78498 
78499 #define TSI_GENCS_SWTS_MASK                      (0x80U)
78500 #define TSI_GENCS_SWTS_SHIFT                     (7U)
78501 /*! SWTS - Software Trigger Start
78502  *  0b0..No effect
78503  *  0b1..Takes effect
78504  */
78505 #define TSI_GENCS_SWTS(x)                        (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_SWTS_SHIFT)) & TSI_GENCS_SWTS_MASK)
78506 
78507 #define TSI_GENCS_CTRIM_FINE_MASK                (0xE00U)
78508 #define TSI_GENCS_CTRIM_FINE_SHIFT               (9U)
78509 /*! CTRIM_FINE - Capacitor Fine Trim
78510  *  0b000..0.3125 pF
78511  *  0b001..0.625 pF
78512  *  0b010..0.3125 * 3 pF
78513  *  0b011..0.3125 * 4 pF
78514  *  0b100..0.3125 * 5 pF
78515  *  0b101..0.3125 * 6 pF
78516  *  0b110..2.1875 pF
78517  *  0b111..2.5 pF
78518  */
78519 #define TSI_GENCS_CTRIM_FINE(x)                  (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_CTRIM_FINE_SHIFT)) & TSI_GENCS_CTRIM_FINE_MASK)
78520 
78521 #define TSI_GENCS_DVOLT_MASK                     (0x7000U)
78522 #define TSI_GENCS_DVOLT_SHIFT                    (12U)
78523 /*! DVOLT - Delta Voltage
78524  *  0b000..Vm = 0.6 V, Vp = 1.7 V
78525  *  0b001..Vm = 0.6 V, Vp = 1.9 V
78526  *  0b010..Vm = 0.6 V, Vp = 2.1 V
78527  *  0b011..Vm = 0.6 V, Vp = 2.3 V
78528  *  0b100..Vm = 0.6 V, Vp = 2.5 V
78529  *  0b101..Vm = 0.6 V, Vp = 2.7 V
78530  */
78531 #define TSI_GENCS_DVOLT(x)                       (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_DVOLT_SHIFT)) & TSI_GENCS_DVOLT_MASK)
78532 
78533 #define TSI_GENCS_DEBOUNCE_MASK                  (0x1F0000U)
78534 #define TSI_GENCS_DEBOUNCE_SHIFT                 (16U)
78535 /*! DEBOUNCE - Debounce
78536  *  0b00000..1
78537  *  0b00001..2
78538  *  0b1xxxx..n
78539  *  0b11111..31
78540  */
78541 #define TSI_GENCS_DEBOUNCE(x)                    (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_DEBOUNCE_SHIFT)) & TSI_GENCS_DEBOUNCE_MASK)
78542 
78543 #define TSI_GENCS_S_PROX_EN_MASK                 (0x400000U)
78544 #define TSI_GENCS_S_PROX_EN_SHIFT                (22U)
78545 /*! S_PROX_EN - Proximity Enable Signal
78546  *  0b0..Disables
78547  *  0b1..Enables
78548  */
78549 #define TSI_GENCS_S_PROX_EN(x)                   (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_S_PROX_EN_SHIFT)) & TSI_GENCS_S_PROX_EN_MASK)
78550 
78551 #define TSI_GENCS_SETCLK_MASK                    (0x7000000U)
78552 #define TSI_GENCS_SETCLK_SHIFT                   (24U)
78553 /*! SETCLK - Set Clock
78554  *  0b000..27.37 MHz
78555  *  0b001..22.23 MHz
78556  *  0b010..18.73 MHz
78557  *  0b011..16.65 MHz
78558  *  0b100..14.27 MHz
78559  *  0b101..12.73 MHz
78560  *  0b110..11.49 MHz
78561  *  0b111..10.46 MHz
78562  */
78563 #define TSI_GENCS_SETCLK(x)                      (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_SETCLK_SHIFT)) & TSI_GENCS_SETCLK_MASK)
78564 
78565 #define TSI_GENCS_ESOR_MASK                      (0x8000000U)
78566 #define TSI_GENCS_ESOR_SHIFT                     (27U)
78567 /*! ESOR - End-of-Scan Interrupt Enable
78568  *  0b0..Disables
78569  *  0b1..Enables
78570  */
78571 #define TSI_GENCS_ESOR(x)                        (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_ESOR_SHIFT)) & TSI_GENCS_ESOR_MASK)
78572 
78573 #define TSI_GENCS_OUTRG_EN_MASK                  (0x40000000U)
78574 #define TSI_GENCS_OUTRG_EN_SHIFT                 (30U)
78575 /*! OUTRG_EN - Out-of-Range Interrupt Enable
78576  *  0b0..Disables
78577  *  0b1..Enables
78578  */
78579 #define TSI_GENCS_OUTRG_EN(x)                    (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_OUTRG_EN_SHIFT)) & TSI_GENCS_OUTRG_EN_MASK)
78580 /*! @} */
78581 
78582 /*! @name MUL - TSI Mutual-Capacitance */
78583 /*! @{ */
78584 
78585 #define TSI_MUL_M_VPRE_CHOOSE_MASK               (0x2U)
78586 #define TSI_MUL_M_VPRE_CHOOSE_SHIFT              (1U)
78587 /*! M_VPRE_CHOOSE - Mutual-Capacitance Prevoltage
78588  *  0b0..Internal 1.2 V
78589  *  0b1..External 1.2 V from PMC
78590  */
78591 #define TSI_MUL_M_VPRE_CHOOSE(x)                 (((uint32_t)(((uint32_t)(x)) << TSI_MUL_M_VPRE_CHOOSE_SHIFT)) & TSI_MUL_M_VPRE_CHOOSE_MASK)
78592 
78593 #define TSI_MUL_M_MODE_MASK                      (0x4U)
78594 #define TSI_MUL_M_MODE_SHIFT                     (2U)
78595 /*! M_MODE - Mutual-Capacitance Mode
78596  *  0b0..- 5 V ~ + 5 V
78597  *  0b1..0 V ~ + 5 V
78598  */
78599 #define TSI_MUL_M_MODE(x)                        (((uint32_t)(((uint32_t)(x)) << TSI_MUL_M_MODE_SHIFT)) & TSI_MUL_M_MODE_MASK)
78600 
78601 #define TSI_MUL_M_TRIM_CAP_MASK                  (0x18U)
78602 #define TSI_MUL_M_TRIM_CAP_SHIFT                 (3U)
78603 /*! M_TRIM_CAP - Mutual-Capacitance Trim Cap
78604  *  0b00..0 pF
78605  *  0b01..10 pF
78606  *  0b10..10 pF
78607  *  0b11..20 pF
78608  */
78609 #define TSI_MUL_M_TRIM_CAP(x)                    (((uint32_t)(((uint32_t)(x)) << TSI_MUL_M_TRIM_CAP_SHIFT)) & TSI_MUL_M_TRIM_CAP_MASK)
78610 
78611 #define TSI_MUL_M_TX_USED_MASK                   (0x1FE0U)
78612 #define TSI_MUL_M_TX_USED_SHIFT                  (5U)
78613 /*! M_TX_USED - Mutual-Capacitance TX Used
78614  *  0b00000000..GPIO
78615  *  0b00000001..Mutual capacitance
78616  */
78617 #define TSI_MUL_M_TX_USED(x)                     (((uint32_t)(((uint32_t)(x)) << TSI_MUL_M_TX_USED_SHIFT)) & TSI_MUL_M_TX_USED_MASK)
78618 
78619 #define TSI_MUL_M_TRIM_MASK                      (0xFFFF0000U)
78620 #define TSI_MUL_M_TRIM_SHIFT                     (16U)
78621 /*! M_TRIM - Mutual-Capacitance Trim */
78622 #define TSI_MUL_M_TRIM(x)                        (((uint32_t)(((uint32_t)(x)) << TSI_MUL_M_TRIM_SHIFT)) & TSI_MUL_M_TRIM_MASK)
78623 /*! @} */
78624 
78625 /*! @name SINC - TSI SINC Filter */
78626 /*! @{ */
78627 
78628 #define TSI_SINC_SSC_CONTROL_OUT_MASK            (0x1U)
78629 #define TSI_SINC_SSC_CONTROL_OUT_SHIFT           (0U)
78630 /*! SSC_CONTROL_OUT - SSC Output Control
78631  *  0b0..0
78632  *  0b1..1
78633  */
78634 #define TSI_SINC_SSC_CONTROL_OUT(x)              (((uint32_t)(((uint32_t)(x)) << TSI_SINC_SSC_CONTROL_OUT_SHIFT)) & TSI_SINC_SSC_CONTROL_OUT_MASK)
78635 
78636 #define TSI_SINC_SINC_VALID_MASK                 (0x2U)
78637 #define TSI_SINC_SINC_VALID_SHIFT                (1U)
78638 /*! SINC_VALID - SINC Valid
78639  *  0b0..Disabled
78640  *  0b1..Enabled
78641  */
78642 #define TSI_SINC_SINC_VALID(x)                   (((uint32_t)(((uint32_t)(x)) << TSI_SINC_SINC_VALID_SHIFT)) & TSI_SINC_SINC_VALID_MASK)
78643 
78644 #define TSI_SINC_SINC_OVERFLOW_FLAG_MASK         (0x4U)
78645 #define TSI_SINC_SINC_OVERFLOW_FLAG_SHIFT        (2U)
78646 /*! SINC_OVERFLOW_FLAG - SINC Overflow Flag
78647  *  0b0..No overflow
78648  *  0b1..Overflow
78649  */
78650 #define TSI_SINC_SINC_OVERFLOW_FLAG(x)           (((uint32_t)(((uint32_t)(x)) << TSI_SINC_SINC_OVERFLOW_FLAG_SHIFT)) & TSI_SINC_SINC_OVERFLOW_FLAG_MASK)
78651 
78652 #define TSI_SINC_SWITCH_ENABLE_MASK              (0x8U)
78653 #define TSI_SINC_SWITCH_ENABLE_SHIFT             (3U)
78654 /*! SWITCH_ENABLE - Switch Enable
78655  *  0b0..Disabled
78656  *  0b1..Enabled
78657  */
78658 #define TSI_SINC_SWITCH_ENABLE(x)                (((uint32_t)(((uint32_t)(x)) << TSI_SINC_SWITCH_ENABLE_SHIFT)) & TSI_SINC_SWITCH_ENABLE_MASK)
78659 
78660 #define TSI_SINC_DECIMATION_MASK                 (0x1F0000U)
78661 #define TSI_SINC_DECIMATION_SHIFT                (16U)
78662 /*! DECIMATION - Decimation
78663  *  0b00000..1
78664  *  0b00001..2
78665  *  0b00010..3
78666  *  0b00011..4
78667  *  0b00100..5
78668  *  0b00101..6
78669  *  0b00110..7
78670  *  0b00111..8
78671  *  0b01000..9
78672  *  0b01001..10
78673  *  0b01010..11
78674  *  0b01011..12
78675  *  0b01100..13
78676  *  0b01101..14
78677  *  0b01110..15
78678  *  0b01111..16
78679  *  0b10000..17
78680  *  0b10001..18
78681  *  0b10010..19
78682  *  0b10011..20
78683  *  0b10100..21
78684  *  0b10101..22
78685  *  0b10110..23
78686  *  0b10111..24
78687  *  0b11000..25
78688  *  0b11001..26
78689  *  0b11010..27
78690  *  0b11011..28
78691  *  0b11100..29
78692  *  0b11101..30
78693  *  0b11110..31
78694  *  0b11111..32
78695  */
78696 #define TSI_SINC_DECIMATION(x)                   (((uint32_t)(((uint32_t)(x)) << TSI_SINC_DECIMATION_SHIFT)) & TSI_SINC_DECIMATION_MASK)
78697 
78698 #define TSI_SINC_ORDER_MASK                      (0x200000U)
78699 #define TSI_SINC_ORDER_SHIFT                     (21U)
78700 /*! ORDER - Order
78701  *  0b0..Order 1
78702  *  0b1..Order 2
78703  */
78704 #define TSI_SINC_ORDER(x)                        (((uint32_t)(((uint32_t)(x)) << TSI_SINC_ORDER_SHIFT)) & TSI_SINC_ORDER_MASK)
78705 
78706 #define TSI_SINC_CUTOFF_MASK                     (0xF000000U)
78707 #define TSI_SINC_CUTOFF_SHIFT                    (24U)
78708 /*! CUTOFF - Cutoff
78709  *  0b0000..div = 1
78710  *  0b0001..div = 2
78711  *  0b0010..div = 4
78712  *  0b0011..div = 8
78713  *  0b0100..div = 16
78714  *  0b0101..div = 32
78715  *  0b0110..div = 64
78716  *  0b0111..div = 128
78717  *  0b1000..Do not use
78718  *  0b1001..Do not use
78719  *  0b1010..Do not use
78720  *  0b1011..Do not use
78721  *  0b1100..Do not use
78722  *  0b1101..Do not use
78723  *  0b1110..Do not use
78724  *  0b1111..Do not use
78725  */
78726 #define TSI_SINC_CUTOFF(x)                       (((uint32_t)(((uint32_t)(x)) << TSI_SINC_CUTOFF_SHIFT)) & TSI_SINC_CUTOFF_MASK)
78727 /*! @} */
78728 
78729 /*! @name SSC0 - TSI SSC 0 */
78730 /*! @{ */
78731 
78732 #define TSI_SSC0_SSC_PRESCALE_NUM_MASK           (0xFFU)
78733 #define TSI_SSC0_SSC_PRESCALE_NUM_SHIFT          (0U)
78734 /*! SSC_PRESCALE_NUM - SSC Prescale Number
78735  *  0b00000000..div = 1
78736  *  0b00000001..div = 2
78737  *  0b00000011..div = 4
78738  *  0b00000111..div = 8
78739  *  0b00001111..div = 16
78740  *  0b00011111..div = 32
78741  *  0b00111111..div = 64
78742  *  0b01111111..div = 128
78743  *  0b11111111..div = 256
78744  */
78745 #define TSI_SSC0_SSC_PRESCALE_NUM(x)             (((uint32_t)(((uint32_t)(x)) << TSI_SSC0_SSC_PRESCALE_NUM_SHIFT)) & TSI_SSC0_SSC_PRESCALE_NUM_MASK)
78746 
78747 #define TSI_SSC0_BASE_NOCHARGE_NUM_MASK          (0xF0000U)
78748 #define TSI_SSC0_BASE_NOCHARGE_NUM_SHIFT         (16U)
78749 /*! BASE_NOCHARGE_NUM - Base Nocharge Number
78750  *  0b0000..1
78751  *  0b0001..2
78752  *  0b0010..3
78753  *  0b0011..4
78754  *  0b0100..5
78755  *  0b0101..6
78756  *  0b0110..7
78757  *  0b0111..8
78758  *  0b1000..9
78759  *  0b1001..10
78760  *  0b1010..11
78761  *  0b1011..12
78762  *  0b1100..13
78763  *  0b1101..14
78764  *  0b1110..15
78765  *  0b1111..16
78766  */
78767 #define TSI_SSC0_BASE_NOCHARGE_NUM(x)            (((uint32_t)(((uint32_t)(x)) << TSI_SSC0_BASE_NOCHARGE_NUM_SHIFT)) & TSI_SSC0_BASE_NOCHARGE_NUM_MASK)
78768 
78769 #define TSI_SSC0_CHARGE_NUM_MASK                 (0xF00000U)
78770 #define TSI_SSC0_CHARGE_NUM_SHIFT                (20U)
78771 /*! CHARGE_NUM - Charge Number
78772  *  0b0000..1
78773  *  0b0001..2
78774  *  0b0010..3
78775  *  0b0011..4
78776  *  0b0100..5
78777  *  0b0101..6
78778  *  0b0110..7
78779  *  0b0111..8
78780  *  0b1000..9
78781  *  0b1001..10
78782  *  0b1010..11
78783  *  0b1011..12
78784  *  0b1100..13
78785  *  0b1101..14
78786  *  0b1110..15
78787  *  0b1111..16
78788  */
78789 #define TSI_SSC0_CHARGE_NUM(x)                   (((uint32_t)(((uint32_t)(x)) << TSI_SSC0_CHARGE_NUM_SHIFT)) & TSI_SSC0_CHARGE_NUM_MASK)
78790 
78791 #define TSI_SSC0_SSC_CONTROL_REVERSE_MASK        (0x1000000U)
78792 #define TSI_SSC0_SSC_CONTROL_REVERSE_SHIFT       (24U)
78793 /*! SSC_CONTROL_REVERSE - SSC Control Reverse
78794  *  0b0..Polarity retained
78795  *  0b1..Polarity reversed
78796  */
78797 #define TSI_SSC0_SSC_CONTROL_REVERSE(x)          (((uint32_t)(((uint32_t)(x)) << TSI_SSC0_SSC_CONTROL_REVERSE_SHIFT)) & TSI_SSC0_SSC_CONTROL_REVERSE_MASK)
78798 
78799 #define TSI_SSC0_SSC_MODE_MASK                   (0x6000000U)
78800 #define TSI_SSC0_SSC_MODE_SHIFT                  (25U)
78801 /*! SSC_MODE - SSC Mode
78802  *  0b00..PRBS mode
78803  *  0b01..Up-Down Counter mode
78804  *  0b10..Disables SSC function
78805  *  0b11..Do not use
78806  */
78807 #define TSI_SSC0_SSC_MODE(x)                     (((uint32_t)(((uint32_t)(x)) << TSI_SSC0_SSC_MODE_SHIFT)) & TSI_SSC0_SSC_MODE_MASK)
78808 
78809 #define TSI_SSC0_PRBS_OUTSEL_MASK                (0xF0000000U)
78810 #define TSI_SSC0_PRBS_OUTSEL_SHIFT               (28U)
78811 /*! PRBS_OUTSEL - PRBS Output Selection
78812  *  0b0000..Do not use
78813  *  0b0001..Do not use
78814  *  0b0010..2
78815  *  0b0011..3
78816  *  0b0100..4
78817  *  0b0101..5
78818  *  0b0110..6
78819  *  0b0111..7
78820  *  0b1000..8
78821  *  0b1001..9
78822  *  0b1010..10
78823  *  0b1011..11
78824  *  0b1100..12
78825  *  0b1101..13
78826  *  0b1110..14
78827  *  0b1111..15
78828  */
78829 #define TSI_SSC0_PRBS_OUTSEL(x)                  (((uint32_t)(((uint32_t)(x)) << TSI_SSC0_PRBS_OUTSEL_SHIFT)) & TSI_SSC0_PRBS_OUTSEL_MASK)
78830 /*! @} */
78831 
78832 /*! @name SSC1 - TSI SSC 1 */
78833 /*! @{ */
78834 
78835 #define TSI_SSC1_PRBS_SEED_LO_MASK               (0xFFU)
78836 #define TSI_SSC1_PRBS_SEED_LO_SHIFT              (0U)
78837 /*! PRBS_SEED_LO - PRBS Low Seed */
78838 #define TSI_SSC1_PRBS_SEED_LO(x)                 (((uint32_t)(((uint32_t)(x)) << TSI_SSC1_PRBS_SEED_LO_SHIFT)) & TSI_SSC1_PRBS_SEED_LO_MASK)
78839 
78840 #define TSI_SSC1_PRBS_SEED_HI_MASK               (0xFF00U)
78841 #define TSI_SSC1_PRBS_SEED_HI_SHIFT              (8U)
78842 /*! PRBS_SEED_HI - PRBS High Seed */
78843 #define TSI_SSC1_PRBS_SEED_HI(x)                 (((uint32_t)(((uint32_t)(x)) << TSI_SSC1_PRBS_SEED_HI_SHIFT)) & TSI_SSC1_PRBS_SEED_HI_MASK)
78844 
78845 #define TSI_SSC1_PRBS_WEIGHT_LO_MASK             (0xFF0000U)
78846 #define TSI_SSC1_PRBS_WEIGHT_LO_SHIFT            (16U)
78847 /*! PRBS_WEIGHT_LO - PRBS Low Weight */
78848 #define TSI_SSC1_PRBS_WEIGHT_LO(x)               (((uint32_t)(((uint32_t)(x)) << TSI_SSC1_PRBS_WEIGHT_LO_SHIFT)) & TSI_SSC1_PRBS_WEIGHT_LO_MASK)
78849 
78850 #define TSI_SSC1_PRBS_WEIGHT_HI_MASK             (0xFF000000U)
78851 #define TSI_SSC1_PRBS_WEIGHT_HI_SHIFT            (24U)
78852 /*! PRBS_WEIGHT_HI - PRBS High Weight */
78853 #define TSI_SSC1_PRBS_WEIGHT_HI(x)               (((uint32_t)(((uint32_t)(x)) << TSI_SSC1_PRBS_WEIGHT_HI_SHIFT)) & TSI_SSC1_PRBS_WEIGHT_HI_MASK)
78854 /*! @} */
78855 
78856 /*! @name SSC2 - TSI SSC 2 */
78857 /*! @{ */
78858 
78859 #define TSI_SSC2_MOVE_REPEAT_NUM_MASK            (0x1FU)
78860 #define TSI_SSC2_MOVE_REPEAT_NUM_SHIFT           (0U)
78861 /*! MOVE_REPEAT_NUM - Move Repeat Number
78862  *  0b00000..1
78863  *  0b00001..2
78864  *  0b00010..3
78865  *  0b00011..4
78866  *  0b00100..5
78867  *  0b00101..6
78868  *  0b00110..7
78869  */
78870 #define TSI_SSC2_MOVE_REPEAT_NUM(x)              (((uint32_t)(((uint32_t)(x)) << TSI_SSC2_MOVE_REPEAT_NUM_SHIFT)) & TSI_SSC2_MOVE_REPEAT_NUM_MASK)
78871 
78872 #define TSI_SSC2_MOVE_STEPS_NUM_MASK             (0x700U)
78873 #define TSI_SSC2_MOVE_STEPS_NUM_SHIFT            (8U)
78874 /*! MOVE_STEPS_NUM - Move Steps Number
78875  *  0b000..0
78876  *  0b001..1
78877  *  0b010..2
78878  *  0b011..3
78879  *  0b100..4
78880  *  0b101..5
78881  *  0b110..6
78882  *  0b111..7
78883  */
78884 #define TSI_SSC2_MOVE_STEPS_NUM(x)               (((uint32_t)(((uint32_t)(x)) << TSI_SSC2_MOVE_STEPS_NUM_SHIFT)) & TSI_SSC2_MOVE_STEPS_NUM_MASK)
78885 
78886 #define TSI_SSC2_MOVE_NOCHARGE_MAX_MASK          (0x3F0000U)
78887 #define TSI_SSC2_MOVE_NOCHARGE_MAX_SHIFT         (16U)
78888 /*! MOVE_NOCHARGE_MAX - Move Nocharge Maximum */
78889 #define TSI_SSC2_MOVE_NOCHARGE_MAX(x)            (((uint32_t)(((uint32_t)(x)) << TSI_SSC2_MOVE_NOCHARGE_MAX_SHIFT)) & TSI_SSC2_MOVE_NOCHARGE_MAX_MASK)
78890 
78891 #define TSI_SSC2_MOVE_NOCHARGE_MIN_MASK          (0xF0000000U)
78892 #define TSI_SSC2_MOVE_NOCHARGE_MIN_SHIFT         (28U)
78893 /*! MOVE_NOCHARGE_MIN - Move Nocharge Minimum
78894  *  0b0000..(1 + SSC0[BASE_NOCHARGE_NUM])
78895  *  0b0001..(2 + SSC0[BASE_NOCHARGE_NUM])
78896  *  0b0010..(3 + SSC0[BASE_NOCHARGE_NUM])
78897  *  0b0011..(4 + SSC0[BASE_NOCHARGE_NUM])
78898  *  0b0100..(5 + SSC0[BASE_NOCHARGE_NUM])
78899  *  0b0101..(6 + SSC0[BASE_NOCHARGE_NUM])
78900  *  0b0110..(7 + SSC0[BASE_NOCHARGE_NUM])
78901  *  0b0111..(8 + SSC0[BASE_NOCHARGE_NUM])
78902  *  0b1000..(9 + SSC0[BASE_NOCHARGE_NUM])
78903  *  0b1001..(10 + SSC0[BASE_NOCHARGE_NUM])
78904  *  0b1010..(11 + SSC0[BASE_NOCHARGE_NUM])
78905  *  0b1011..(12 + SSC0[BASE_NOCHARGE_NUM])
78906  *  0b1100..(13 + SSC0[BASE_NOCHARGE_NUM])
78907  *  0b1101..(14 + SSC0[BASE_NOCHARGE_NUM])
78908  *  0b1110..(15 + SSC0[BASE_NOCHARGE_NUM])
78909  *  0b1111..(16 + SSC0[BASE_NOCHARGE_NUM])
78910  */
78911 #define TSI_SSC2_MOVE_NOCHARGE_MIN(x)            (((uint32_t)(((uint32_t)(x)) << TSI_SSC2_MOVE_NOCHARGE_MIN_SHIFT)) & TSI_SSC2_MOVE_NOCHARGE_MIN_MASK)
78912 /*! @} */
78913 
78914 /*! @name BASELINE - TSI Baseline */
78915 /*! @{ */
78916 
78917 #define TSI_BASELINE_BASELINE_MASK               (0xFFFFU)
78918 #define TSI_BASELINE_BASELINE_SHIFT              (0U)
78919 /*! BASELINE - Baseline */
78920 #define TSI_BASELINE_BASELINE(x)                 (((uint32_t)(((uint32_t)(x)) << TSI_BASELINE_BASELINE_SHIFT)) & TSI_BASELINE_BASELINE_MASK)
78921 
78922 #define TSI_BASELINE_BASE_TRACE_DEBOUNCE_MASK    (0xF0000U)
78923 #define TSI_BASELINE_BASE_TRACE_DEBOUNCE_SHIFT   (16U)
78924 /*! BASE_TRACE_DEBOUNCE - Base Trace Debounce
78925  *  0b0000..0
78926  *  0b0001..1 / 16
78927  *  0b0010..2 / 16
78928  *  0b0011..3 / 16
78929  *  0b1xxx..n / 16
78930  *  0b1111..15 / 16
78931  */
78932 #define TSI_BASELINE_BASE_TRACE_DEBOUNCE(x)      (((uint32_t)(((uint32_t)(x)) << TSI_BASELINE_BASE_TRACE_DEBOUNCE_SHIFT)) & TSI_BASELINE_BASE_TRACE_DEBOUNCE_MASK)
78933 
78934 #define TSI_BASELINE_BASE_TRACE_EN_MASK          (0x100000U)
78935 #define TSI_BASELINE_BASE_TRACE_EN_SHIFT         (20U)
78936 /*! BASE_TRACE_EN - Baseline Trace Enable */
78937 #define TSI_BASELINE_BASE_TRACE_EN(x)            (((uint32_t)(((uint32_t)(x)) << TSI_BASELINE_BASE_TRACE_EN_SHIFT)) & TSI_BASELINE_BASE_TRACE_EN_MASK)
78938 
78939 #define TSI_BASELINE_THESHOLD_RATIO_MASK         (0x70000000U)
78940 #define TSI_BASELINE_THESHOLD_RATIO_SHIFT        (28U)
78941 /*! THESHOLD_RATIO - Threshold Ratio
78942  *  0b000..thresholdh = (baseline + counter) / 2 and thresholdl = (baseline - counter) / 2
78943  *  0b001..thresholdh = (baseline + counter) / 4 and thresholdl = (baseline - counter) / 4
78944  *  0b010..thresholdh = (baseline + counter) / 8 and thresholdl = (baseline - counter) / 8
78945  *  0b011..thresholdh = (baseline + counter) / 16 and thresholdl = (baseline - counter) / 16
78946  *  0b100..thresholdh = (baseline + counter) / 32 and thresholdl = (baseline - counter) / 32
78947  *  0b101..thresholdh = (baseline + counter) / 64 and thresholdl = (baseline - counter) / 64
78948  *  0b110..thresholdh = (baseline + counter) / 128 and thresholdl = (baseline - counter) / 128
78949  *  0b111..thresholdh = (baseline + counter) / 256 and thresholdl = (baseline - counter) / 256
78950  */
78951 #define TSI_BASELINE_THESHOLD_RATIO(x)           (((uint32_t)(((uint32_t)(x)) << TSI_BASELINE_THESHOLD_RATIO_SHIFT)) & TSI_BASELINE_THESHOLD_RATIO_MASK)
78952 
78953 #define TSI_BASELINE_THRESHOLD_TRACE_EN_MASK     (0x80000000U)
78954 #define TSI_BASELINE_THRESHOLD_TRACE_EN_SHIFT    (31U)
78955 /*! THRESHOLD_TRACE_EN - Threshold Trace Enable
78956  *  0b0..Disables
78957  *  0b1..Enables
78958  */
78959 #define TSI_BASELINE_THRESHOLD_TRACE_EN(x)       (((uint32_t)(((uint32_t)(x)) << TSI_BASELINE_THRESHOLD_TRACE_EN_SHIFT)) & TSI_BASELINE_THRESHOLD_TRACE_EN_MASK)
78960 /*! @} */
78961 
78962 /*! @name CHMERGE - TSI Channel Merge */
78963 /*! @{ */
78964 
78965 #define TSI_CHMERGE_CHANNEL_ENABLE_MASK          (0x1FFFFFFU)
78966 #define TSI_CHMERGE_CHANNEL_ENABLE_SHIFT         (0U)
78967 /*! CHANNEL_ENABLE - Channel Enable
78968  *  0b0000000000000000000000000..Channel not chosen for proximity pad
78969  *  0b0000000000000000000000001..Channel chosen for proximity pad
78970  */
78971 #define TSI_CHMERGE_CHANNEL_ENABLE(x)            (((uint32_t)(((uint32_t)(x)) << TSI_CHMERGE_CHANNEL_ENABLE_SHIFT)) & TSI_CHMERGE_CHANNEL_ENABLE_MASK)
78972 /*! @} */
78973 
78974 /*! @name SHIELD - TSI Shield */
78975 /*! @{ */
78976 
78977 #define TSI_SHIELD_SHIELD_ENABLE_MASK            (0xFU)
78978 #define TSI_SHIELD_SHIELD_ENABLE_SHIFT           (0U)
78979 /*! SHIELD_ENABLE - Shield Enable
78980  *  0b0000..Disables
78981  *  0b0001..Enables
78982  */
78983 #define TSI_SHIELD_SHIELD_ENABLE(x)              (((uint32_t)(((uint32_t)(x)) << TSI_SHIELD_SHIELD_ENABLE_SHIFT)) & TSI_SHIELD_SHIELD_ENABLE_MASK)
78984 
78985 #define TSI_SHIELD_M_SEN_RES_MASK                (0x7E000000U)
78986 #define TSI_SHIELD_M_SEN_RES_SHIFT               (25U)
78987 /*! M_SEN_RES - Mutual-Capacitance Sensitivity Resistor
78988  *  0b000000..10 kΩ
78989  *  0b000001..10 kΩ + (2.5 / 3) kΩ (just for auto-calibration)
78990  *  0b000010..12.5 kΩ (default)
78991  *  0b001110..25 kΩ
78992  */
78993 #define TSI_SHIELD_M_SEN_RES(x)                  (((uint32_t)(((uint32_t)(x)) << TSI_SHIELD_M_SEN_RES_SHIFT)) & TSI_SHIELD_M_SEN_RES_MASK)
78994 /*! @} */
78995 
78996 /*! @name DATA - TSI Data and Status */
78997 /*! @{ */
78998 
78999 #define TSI_DATA_TSICNT_MASK                     (0xFFFFU)
79000 #define TSI_DATA_TSICNT_SHIFT                    (0U)
79001 /*! TSICNT - TSI Conversion Counter Value */
79002 #define TSI_DATA_TSICNT(x)                       (((uint32_t)(((uint32_t)(x)) << TSI_DATA_TSICNT_SHIFT)) & TSI_DATA_TSICNT_MASK)
79003 
79004 #define TSI_DATA_EOSF_MASK                       (0x8000000U)
79005 #define TSI_DATA_EOSF_SHIFT                      (27U)
79006 /*! EOSF - End-of-Scan Flag */
79007 #define TSI_DATA_EOSF(x)                         (((uint32_t)(((uint32_t)(x)) << TSI_DATA_EOSF_SHIFT)) & TSI_DATA_EOSF_MASK)
79008 
79009 #define TSI_DATA_OVERRUNF_MASK                   (0x20000000U)
79010 #define TSI_DATA_OVERRUNF_SHIFT                  (29U)
79011 /*! OVERRUNF - Overrun Flag
79012  *  0b0..No
79013  *  0b1..Yes
79014  */
79015 #define TSI_DATA_OVERRUNF(x)                     (((uint32_t)(((uint32_t)(x)) << TSI_DATA_OVERRUNF_SHIFT)) & TSI_DATA_OVERRUNF_MASK)
79016 
79017 #define TSI_DATA_OUTRGF_MASK                     (0x40000000U)
79018 #define TSI_DATA_OUTRGF_SHIFT                    (30U)
79019 /*! OUTRGF - Out-of-Range Flag */
79020 #define TSI_DATA_OUTRGF(x)                       (((uint32_t)(((uint32_t)(x)) << TSI_DATA_OUTRGF_SHIFT)) & TSI_DATA_OUTRGF_MASK)
79021 /*! @} */
79022 
79023 /*! @name MISC - TSI Miscellaneous */
79024 /*! @{ */
79025 
79026 #define TSI_MISC_OSC_CLK_SEL_MASK                (0x80000U)
79027 #define TSI_MISC_OSC_CLK_SEL_SHIFT               (19U)
79028 /*! OSC_CLK_SEL - Oscillator Clock Select
79029  *  0b0..Analog oscillator
79030  *  0b1..Chip
79031  */
79032 #define TSI_MISC_OSC_CLK_SEL(x)                  (((uint32_t)(((uint32_t)(x)) << TSI_MISC_OSC_CLK_SEL_SHIFT)) & TSI_MISC_OSC_CLK_SEL_MASK)
79033 
79034 #define TSI_MISC_TEST_FINGER_MASK                (0x700000U)
79035 #define TSI_MISC_TEST_FINGER_SHIFT               (20U)
79036 /*! TEST_FINGER - Test Finger
79037  *  0b000..Finger capacitor is 148 pF
79038  *  0b001..Finger capacitor is 296 pF
79039  *  0b010..Finger capacitor is 444 pF
79040  *  0b011..Finger capacitor is 592 pF
79041  *  0b100..Finger capacitor is 740 pF
79042  *  0b101..Finger capacitor is 888 pF
79043  *  0b110..Finger capacitor is 1036 pF
79044  *  0b111..Finger capacitor is 1184 pF
79045  */
79046 #define TSI_MISC_TEST_FINGER(x)                  (((uint32_t)(((uint32_t)(x)) << TSI_MISC_TEST_FINGER_SHIFT)) & TSI_MISC_TEST_FINGER_MASK)
79047 
79048 #define TSI_MISC_TEST_FINGER_EN_MASK             (0x800000U)
79049 #define TSI_MISC_TEST_FINGER_EN_SHIFT            (23U)
79050 /*! TEST_FINGER_EN - Test Finger Function Enable Signals
79051  *  0b0..Disables
79052  *  0b1..Enables
79053  */
79054 #define TSI_MISC_TEST_FINGER_EN(x)               (((uint32_t)(((uint32_t)(x)) << TSI_MISC_TEST_FINGER_EN_SHIFT)) & TSI_MISC_TEST_FINGER_EN_MASK)
79055 
79056 #define TSI_MISC_CLKDIVIDER_MASK                 (0x1F000000U)
79057 #define TSI_MISC_CLKDIVIDER_SHIFT                (24U)
79058 /*! CLKDIVIDER - TSI Clock Divider */
79059 #define TSI_MISC_CLKDIVIDER(x)                   (((uint32_t)(((uint32_t)(x)) << TSI_MISC_CLKDIVIDER_SHIFT)) & TSI_MISC_CLKDIVIDER_MASK)
79060 /*! @} */
79061 
79062 /*! @name TRIG - TSI AUTO TRIG */
79063 /*! @{ */
79064 
79065 #define TSI_TRIG_TRIG_PERIOD_COUNTER_MASK        (0xFFFFFU)
79066 #define TSI_TRIG_TRIG_PERIOD_COUNTER_SHIFT       (0U)
79067 /*! TRIG_PERIOD_COUNTER - Trigger Period Counter */
79068 #define TSI_TRIG_TRIG_PERIOD_COUNTER(x)          (((uint32_t)(((uint32_t)(x)) << TSI_TRIG_TRIG_PERIOD_COUNTER_SHIFT)) & TSI_TRIG_TRIG_PERIOD_COUNTER_MASK)
79069 
79070 #define TSI_TRIG_TRIG_CLK_DIVIDER_MASK           (0x1F000000U)
79071 #define TSI_TRIG_TRIG_CLK_DIVIDER_SHIFT          (24U)
79072 /*! TRIG_CLK_DIVIDER - Trigger Clock Divider
79073  *  0b00000..No divider
79074  *  0b00001..Divided by 2
79075  *  0b00010..Divided by 3
79076  *  0b00011..Divided by 4
79077  *  0b1xxxx..Divided by n
79078  */
79079 #define TSI_TRIG_TRIG_CLK_DIVIDER(x)             (((uint32_t)(((uint32_t)(x)) << TSI_TRIG_TRIG_CLK_DIVIDER_SHIFT)) & TSI_TRIG_TRIG_CLK_DIVIDER_MASK)
79080 
79081 #define TSI_TRIG_TRIG_EN_MASK                    (0x40000000U)
79082 #define TSI_TRIG_TRIG_EN_SHIFT                   (30U)
79083 /*! TRIG_EN - Trigger Enable
79084  *  0b0..Disabled
79085  *  0b1..Enabled
79086  */
79087 #define TSI_TRIG_TRIG_EN(x)                      (((uint32_t)(((uint32_t)(x)) << TSI_TRIG_TRIG_EN_SHIFT)) & TSI_TRIG_TRIG_EN_MASK)
79088 
79089 #define TSI_TRIG_TRIG_CLK_SEL_MASK               (0x80000000U)
79090 #define TSI_TRIG_TRIG_CLK_SEL_SHIFT              (31U)
79091 /*! TRIG_CLK_SEL - Trigger Clock Select
79092  *  0b0..32 k clock
79093  *  0b1..clksoc
79094  */
79095 #define TSI_TRIG_TRIG_CLK_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << TSI_TRIG_TRIG_CLK_SEL_SHIFT)) & TSI_TRIG_TRIG_CLK_SEL_MASK)
79096 /*! @} */
79097 
79098 
79099 /*!
79100  * @}
79101  */ /* end of group TSI_Register_Masks */
79102 
79103 
79104 /* TSI - Peripheral instance base addresses */
79105 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
79106   /** Peripheral TSI0 base address */
79107   #define TSI0_BASE                                (0x50050000u)
79108   /** Peripheral TSI0 base address */
79109   #define TSI0_BASE_NS                             (0x40050000u)
79110   /** Peripheral TSI0 base pointer */
79111   #define TSI0                                     ((TSI_Type *)TSI0_BASE)
79112   /** Peripheral TSI0 base pointer */
79113   #define TSI0_NS                                  ((TSI_Type *)TSI0_BASE_NS)
79114   /** Array initializer of TSI peripheral base addresses */
79115   #define TSI_BASE_ADDRS                           { TSI0_BASE }
79116   /** Array initializer of TSI peripheral base pointers */
79117   #define TSI_BASE_PTRS                            { TSI0 }
79118   /** Array initializer of TSI peripheral base addresses */
79119   #define TSI_BASE_ADDRS_NS                        { TSI0_BASE_NS }
79120   /** Array initializer of TSI peripheral base pointers */
79121   #define TSI_BASE_PTRS_NS                         { TSI0_NS }
79122 #else
79123   /** Peripheral TSI0 base address */
79124   #define TSI0_BASE                                (0x40050000u)
79125   /** Peripheral TSI0 base pointer */
79126   #define TSI0                                     ((TSI_Type *)TSI0_BASE)
79127   /** Array initializer of TSI peripheral base addresses */
79128   #define TSI_BASE_ADDRS                           { TSI0_BASE }
79129   /** Array initializer of TSI peripheral base pointers */
79130   #define TSI_BASE_PTRS                            { TSI0 }
79131 #endif
79132 
79133 /*!
79134  * @}
79135  */ /* end of group TSI_Peripheral_Access_Layer */
79136 
79137 
79138 /* ----------------------------------------------------------------------------
79139    -- USB Peripheral Access Layer
79140    ---------------------------------------------------------------------------- */
79141 
79142 /*!
79143  * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
79144  * @{
79145  */
79146 
79147 /** USB - Register Layout Typedef */
79148 typedef struct {
79149   __I  uint8_t PERID;                              /**< Peripheral ID, offset: 0x0 */
79150        uint8_t RESERVED_0[3];
79151   __I  uint8_t IDCOMP;                             /**< Peripheral ID Complement, offset: 0x4 */
79152        uint8_t RESERVED_1[3];
79153   __I  uint8_t REV;                                /**< Peripheral Revision, offset: 0x8 */
79154        uint8_t RESERVED_2[3];
79155   __I  uint8_t ADDINFO;                            /**< Peripheral Additional Information, offset: 0xC */
79156        uint8_t RESERVED_3[3];
79157   __IO uint8_t OTGISTAT;                           /**< OTG Interrupt Status, offset: 0x10 */
79158        uint8_t RESERVED_4[3];
79159   __IO uint8_t OTGICR;                             /**< OTG Interrupt Control, offset: 0x14 */
79160        uint8_t RESERVED_5[3];
79161   __I  uint8_t OTGSTAT;                            /**< OTG Status, offset: 0x18 */
79162        uint8_t RESERVED_6[3];
79163   __IO uint8_t OTGCTL;                             /**< OTG Control, offset: 0x1C */
79164        uint8_t RESERVED_7[99];
79165   __IO uint8_t ISTAT;                              /**< Interrupt Status, offset: 0x80 */
79166        uint8_t RESERVED_8[3];
79167   __IO uint8_t INTEN;                              /**< Interrupt Enable, offset: 0x84 */
79168        uint8_t RESERVED_9[3];
79169   __IO uint8_t ERRSTAT;                            /**< Error Interrupt Status, offset: 0x88 */
79170        uint8_t RESERVED_10[3];
79171   __IO uint8_t ERREN;                              /**< Error Interrupt Enable, offset: 0x8C */
79172        uint8_t RESERVED_11[3];
79173   __I  uint8_t STAT;                               /**< Status, offset: 0x90 */
79174        uint8_t RESERVED_12[3];
79175   __IO uint8_t CTL;                                /**< Control, offset: 0x94 */
79176        uint8_t RESERVED_13[3];
79177   __IO uint8_t ADDR;                               /**< Address, offset: 0x98 */
79178        uint8_t RESERVED_14[3];
79179   __IO uint8_t BDTPAGE1;                           /**< BDT Page 1, offset: 0x9C */
79180        uint8_t RESERVED_15[3];
79181   __I  uint8_t FRMNUML;                            /**< Frame Number Register Low, offset: 0xA0 */
79182        uint8_t RESERVED_16[3];
79183   __I  uint8_t FRMNUMH;                            /**< Frame Number Register High, offset: 0xA4 */
79184        uint8_t RESERVED_17[3];
79185   __IO uint8_t TOKEN;                              /**< Token, offset: 0xA8 */
79186        uint8_t RESERVED_18[3];
79187   __IO uint8_t SOFTHLD;                            /**< SOF Threshold, offset: 0xAC */
79188        uint8_t RESERVED_19[3];
79189   __IO uint8_t BDTPAGE2;                           /**< BDT Page 2, offset: 0xB0 */
79190        uint8_t RESERVED_20[3];
79191   __IO uint8_t BDTPAGE3;                           /**< BDT Page 3, offset: 0xB4 */
79192        uint8_t RESERVED_21[11];
79193   struct {                                         /* offset: 0xC0, array step: 0x4 */
79194     __IO uint8_t ENDPT;                              /**< Endpoint Control, array offset: 0xC0, array step: 0x4 */
79195          uint8_t RESERVED_0[3];
79196   } ENDPOINT[16];
79197   __IO uint8_t USBCTRL;                            /**< USB Control, offset: 0x100 */
79198        uint8_t RESERVED_22[3];
79199   __I  uint8_t OBSERVE;                            /**< USB OTG Observe, offset: 0x104 */
79200        uint8_t RESERVED_23[3];
79201   __IO uint8_t CONTROL;                            /**< USB OTG Control, offset: 0x108 */
79202        uint8_t RESERVED_24[3];
79203   __IO uint8_t USBTRC0;                            /**< USB Transceiver Control 0, offset: 0x10C */
79204        uint8_t RESERVED_25[7];
79205   __IO uint8_t USBFRMADJUST;                       /**< Frame Adjust, offset: 0x114 */
79206        uint8_t RESERVED_26[15];
79207   __IO uint8_t KEEP_ALIVE_CTRL;                    /**< Keep Alive Mode Control, offset: 0x124 */
79208        uint8_t RESERVED_27[3];
79209   __IO uint8_t KEEP_ALIVE_WKCTRL;                  /**< Keep Alive Mode Wakeup Control, offset: 0x128 */
79210        uint8_t RESERVED_28[3];
79211   __IO uint8_t MISCCTRL;                           /**< Miscellaneous Control, offset: 0x12C */
79212        uint8_t RESERVED_29[3];
79213   __IO uint8_t STALL_IL_DIS;                       /**< Peripheral Mode Stall Disable for Endpoints 7 to 0 in IN Direction, offset: 0x130 */
79214        uint8_t RESERVED_30[3];
79215   __IO uint8_t STALL_IH_DIS;                       /**< Peripheral Mode Stall Disable for Endpoints 15 to 8 in IN Direction, offset: 0x134 */
79216        uint8_t RESERVED_31[3];
79217   __IO uint8_t STALL_OL_DIS;                       /**< Peripheral Mode Stall Disable for Endpoints 7 to 0 in OUT Direction, offset: 0x138 */
79218        uint8_t RESERVED_32[3];
79219   __IO uint8_t STALL_OH_DIS;                       /**< Peripheral Mode Stall Disable for Endpoints 15 to 8 in OUT Direction, offset: 0x13C */
79220        uint8_t RESERVED_33[3];
79221   __IO uint8_t CLK_RECOVER_CTRL;                   /**< USB Clock Recovery Control, offset: 0x140 */
79222        uint8_t RESERVED_34[3];
79223   __IO uint8_t CLK_RECOVER_IRC_EN;                 /**< FIRC Oscillator Enable, offset: 0x144 */
79224        uint8_t RESERVED_35[15];
79225   __IO uint8_t CLK_RECOVER_INT_EN;                 /**< Clock Recovery Combined Interrupt Enable, offset: 0x154 */
79226        uint8_t RESERVED_36[7];
79227   __IO uint8_t CLK_RECOVER_INT_STATUS;             /**< Clock Recovery Separated Interrupt Status, offset: 0x15C */
79228 } USB_Type;
79229 
79230 /* ----------------------------------------------------------------------------
79231    -- USB Register Masks
79232    ---------------------------------------------------------------------------- */
79233 
79234 /*!
79235  * @addtogroup USB_Register_Masks USB Register Masks
79236  * @{
79237  */
79238 
79239 /*! @name PERID - Peripheral ID */
79240 /*! @{ */
79241 
79242 #define USB_PERID_ID_MASK                        (0x3FU)
79243 #define USB_PERID_ID_SHIFT                       (0U)
79244 /*! ID - Peripheral Identification */
79245 #define USB_PERID_ID(x)                          (((uint8_t)(((uint8_t)(x)) << USB_PERID_ID_SHIFT)) & USB_PERID_ID_MASK)
79246 /*! @} */
79247 
79248 /*! @name IDCOMP - Peripheral ID Complement */
79249 /*! @{ */
79250 
79251 #define USB_IDCOMP_NID_MASK                      (0x3FU)
79252 #define USB_IDCOMP_NID_SHIFT                     (0U)
79253 /*! NID - Negative Peripheral ID */
79254 #define USB_IDCOMP_NID(x)                        (((uint8_t)(((uint8_t)(x)) << USB_IDCOMP_NID_SHIFT)) & USB_IDCOMP_NID_MASK)
79255 /*! @} */
79256 
79257 /*! @name REV - Peripheral Revision */
79258 /*! @{ */
79259 
79260 #define USB_REV_REV_MASK                         (0xFFU)
79261 #define USB_REV_REV_SHIFT                        (0U)
79262 /*! REV - Revision */
79263 #define USB_REV_REV(x)                           (((uint8_t)(((uint8_t)(x)) << USB_REV_REV_SHIFT)) & USB_REV_REV_MASK)
79264 /*! @} */
79265 
79266 /*! @name ADDINFO - Peripheral Additional Information */
79267 /*! @{ */
79268 
79269 #define USB_ADDINFO_IEHOST_MASK                  (0x1U)
79270 #define USB_ADDINFO_IEHOST_SHIFT                 (0U)
79271 /*! IEHOST - Host Mode Enable
79272  *  0b0..Disabled
79273  *  0b1..Enabled
79274  */
79275 #define USB_ADDINFO_IEHOST(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ADDINFO_IEHOST_SHIFT)) & USB_ADDINFO_IEHOST_MASK)
79276 /*! @} */
79277 
79278 /*! @name OTGISTAT - OTG Interrupt Status */
79279 /*! @{ */
79280 
79281 #define USB_OTGISTAT_LINE_STATE_CHG_MASK         (0x20U)
79282 #define USB_OTGISTAT_LINE_STATE_CHG_SHIFT        (5U)
79283 /*! LINE_STATE_CHG - Line State Change Interrupt Flag
79284  *  0b0..Interrupt did not occur
79285  *  0b1..Interrupt occurred
79286  *  0b0..No effect
79287  *  0b1..Clear the flag
79288  */
79289 #define USB_OTGISTAT_LINE_STATE_CHG(x)           (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_LINE_STATE_CHG_SHIFT)) & USB_OTGISTAT_LINE_STATE_CHG_MASK)
79290 
79291 #define USB_OTGISTAT_ONEMSEC_MASK                (0x40U)
79292 #define USB_OTGISTAT_ONEMSEC_SHIFT               (6U)
79293 /*! ONEMSEC - One Millisecond Timer Timeout Flag
79294  *  0b0..Not timed out
79295  *  0b1..Timed out
79296  *  0b0..No effect
79297  *  0b1..Clear the flag
79298  */
79299 #define USB_OTGISTAT_ONEMSEC(x)                  (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_ONEMSEC_SHIFT)) & USB_OTGISTAT_ONEMSEC_MASK)
79300 /*! @} */
79301 
79302 /*! @name OTGICR - OTG Interrupt Control */
79303 /*! @{ */
79304 
79305 #define USB_OTGICR_LINESTATEEN_MASK              (0x20U)
79306 #define USB_OTGICR_LINESTATEEN_SHIFT             (5U)
79307 /*! LINESTATEEN - Line State Change Interrupt Enable
79308  *  0b0..Disable
79309  *  0b1..Enable
79310  */
79311 #define USB_OTGICR_LINESTATEEN(x)                (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_LINESTATEEN_SHIFT)) & USB_OTGICR_LINESTATEEN_MASK)
79312 
79313 #define USB_OTGICR_ONEMSECEN_MASK                (0x40U)
79314 #define USB_OTGICR_ONEMSECEN_SHIFT               (6U)
79315 /*! ONEMSECEN - 1-Millisecond Interrupt Enable
79316  *  0b0..Disable
79317  *  0b1..Enable
79318  */
79319 #define USB_OTGICR_ONEMSECEN(x)                  (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_ONEMSECEN_SHIFT)) & USB_OTGICR_ONEMSECEN_MASK)
79320 /*! @} */
79321 
79322 /*! @name OTGSTAT - OTG Status */
79323 /*! @{ */
79324 
79325 #define USB_OTGSTAT_LINESTATESTABLE_MASK         (0x20U)
79326 #define USB_OTGSTAT_LINESTATESTABLE_SHIFT        (5U)
79327 /*! LINESTATESTABLE - Line State Stable
79328  *  0b0..Unstable
79329  *  0b1..Stable
79330  */
79331 #define USB_OTGSTAT_LINESTATESTABLE(x)           (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_LINESTATESTABLE_SHIFT)) & USB_OTGSTAT_LINESTATESTABLE_MASK)
79332 
79333 #define USB_OTGSTAT_ONEMSEC_MASK                 (0x40U)
79334 #define USB_OTGSTAT_ONEMSEC_SHIFT                (6U)
79335 /*! ONEMSEC - Reserved for 1 ms count */
79336 #define USB_OTGSTAT_ONEMSEC(x)                   (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_ONEMSEC_SHIFT)) & USB_OTGSTAT_ONEMSEC_MASK)
79337 /*! @} */
79338 
79339 /*! @name OTGCTL - OTG Control */
79340 /*! @{ */
79341 
79342 #define USB_OTGCTL_OTGEN_MASK                    (0x4U)
79343 #define USB_OTGCTL_OTGEN_SHIFT                   (2U)
79344 /*! OTGEN - On-The-Go Pullup and Pulldown Resistor Enable
79345  *  0b0..If USBENSOFEN is 1 and HOSTMODEEN is 0 in the Control Register (CTL), then the D+ Data line pullup
79346  *       resistors are enabled. If HOSTMODEEN is 1, then the D+ and D- Data line pulldown resistors are engaged.
79347  *  0b1..Uses the pullup and pulldown controls in this register.
79348  */
79349 #define USB_OTGCTL_OTGEN(x)                      (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_OTGEN_SHIFT)) & USB_OTGCTL_OTGEN_MASK)
79350 
79351 #define USB_OTGCTL_DMLOW_MASK                    (0x10U)
79352 #define USB_OTGCTL_DMLOW_SHIFT                   (4U)
79353 /*! DMLOW - D- Data Line Pulldown Resistor Enable
79354  *  0b0..Disable
79355  *  0b1..Enable
79356  */
79357 #define USB_OTGCTL_DMLOW(x)                      (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DMLOW_SHIFT)) & USB_OTGCTL_DMLOW_MASK)
79358 
79359 #define USB_OTGCTL_DPLOW_MASK                    (0x20U)
79360 #define USB_OTGCTL_DPLOW_SHIFT                   (5U)
79361 /*! DPLOW - D+ Data Line pulldown Resistor Enable
79362  *  0b0..Disable
79363  *  0b1..Enable
79364  */
79365 #define USB_OTGCTL_DPLOW(x)                      (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPLOW_SHIFT)) & USB_OTGCTL_DPLOW_MASK)
79366 
79367 #define USB_OTGCTL_DPHIGH_MASK                   (0x80U)
79368 #define USB_OTGCTL_DPHIGH_SHIFT                  (7U)
79369 /*! DPHIGH - D+ Data Line Pullup Resistor Enable
79370  *  0b0..Disable
79371  *  0b1..Enable
79372  */
79373 #define USB_OTGCTL_DPHIGH(x)                     (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPHIGH_SHIFT)) & USB_OTGCTL_DPHIGH_MASK)
79374 /*! @} */
79375 
79376 /*! @name ISTAT - Interrupt Status */
79377 /*! @{ */
79378 
79379 #define USB_ISTAT_USBRST_MASK                    (0x1U)
79380 #define USB_ISTAT_USBRST_SHIFT                   (0U)
79381 /*! USBRST - USB Reset Flag
79382  *  0b0..Not detected
79383  *  0b1..Detected
79384  *  0b0..No effect
79385  *  0b1..Clear the flag
79386  */
79387 #define USB_ISTAT_USBRST(x)                      (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_USBRST_SHIFT)) & USB_ISTAT_USBRST_MASK)
79388 
79389 #define USB_ISTAT_ERROR_MASK                     (0x2U)
79390 #define USB_ISTAT_ERROR_SHIFT                    (1U)
79391 /*! ERROR - Error Flag
79392  *  0b0..Error did not occur
79393  *  0b1..Error occurred
79394  *  0b0..No effect
79395  *  0b1..Clear the flag
79396  */
79397 #define USB_ISTAT_ERROR(x)                       (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ERROR_SHIFT)) & USB_ISTAT_ERROR_MASK)
79398 
79399 #define USB_ISTAT_SOFTOK_MASK                    (0x4U)
79400 #define USB_ISTAT_SOFTOK_SHIFT                   (2U)
79401 /*! SOFTOK - Start Of Frame (SOF) Token Flag
79402  *  0b0..Did not receive
79403  *  0b1..Received
79404  *  0b0..No effect
79405  *  0b1..Clear the flag
79406  */
79407 #define USB_ISTAT_SOFTOK(x)                      (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SOFTOK_SHIFT)) & USB_ISTAT_SOFTOK_MASK)
79408 
79409 #define USB_ISTAT_TOKDNE_MASK                    (0x8U)
79410 #define USB_ISTAT_TOKDNE_SHIFT                   (3U)
79411 /*! TOKDNE - Current Token Processing Flag
79412  *  0b0..Not processed
79413  *  0b1..Processed
79414  *  0b0..No effect
79415  *  0b1..Clear the flag
79416  */
79417 #define USB_ISTAT_TOKDNE(x)                      (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_TOKDNE_SHIFT)) & USB_ISTAT_TOKDNE_MASK)
79418 
79419 #define USB_ISTAT_SLEEP_MASK                     (0x10U)
79420 #define USB_ISTAT_SLEEP_SHIFT                    (4U)
79421 /*! SLEEP - Sleep Flag
79422  *  0b0..Interrupt did not occur
79423  *  0b1..Interrupt occurred
79424  *  0b0..No effect
79425  *  0b1..Clear the flag
79426  */
79427 #define USB_ISTAT_SLEEP(x)                       (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SLEEP_SHIFT)) & USB_ISTAT_SLEEP_MASK)
79428 
79429 #define USB_ISTAT_RESUME_MASK                    (0x20U)
79430 #define USB_ISTAT_RESUME_SHIFT                   (5U)
79431 /*! RESUME - Resume Flag
79432  *  0b0..Interrupt did not occur
79433  *  0b1..Interrupt occurred
79434  *  0b0..No effect
79435  *  0b1..Clear the flag
79436  */
79437 #define USB_ISTAT_RESUME(x)                      (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_RESUME_SHIFT)) & USB_ISTAT_RESUME_MASK)
79438 
79439 #define USB_ISTAT_ATTACH_MASK                    (0x40U)
79440 #define USB_ISTAT_ATTACH_SHIFT                   (6U)
79441 /*! ATTACH - Attach Interrupt Flag
79442  *  0b0..Not detected
79443  *  0b1..Detected
79444  *  0b0..No effect
79445  *  0b1..Clear the flag
79446  */
79447 #define USB_ISTAT_ATTACH(x)                      (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ATTACH_SHIFT)) & USB_ISTAT_ATTACH_MASK)
79448 
79449 #define USB_ISTAT_STALL_MASK                     (0x80U)
79450 #define USB_ISTAT_STALL_SHIFT                    (7U)
79451 /*! STALL - Stall Interrupt Flag
79452  *  0b0..Interrupt did not occur
79453  *  0b1..Interrupt occurred
79454  *  0b0..No effect
79455  *  0b1..Clear the flag
79456  */
79457 #define USB_ISTAT_STALL(x)                       (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_STALL_SHIFT)) & USB_ISTAT_STALL_MASK)
79458 /*! @} */
79459 
79460 /*! @name INTEN - Interrupt Enable */
79461 /*! @{ */
79462 
79463 #define USB_INTEN_USBRSTEN_MASK                  (0x1U)
79464 #define USB_INTEN_USBRSTEN_SHIFT                 (0U)
79465 /*! USBRSTEN - USBRST Interrupt Enable
79466  *  0b0..Disable
79467  *  0b1..Enable
79468  */
79469 #define USB_INTEN_USBRSTEN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_INTEN_USBRSTEN_SHIFT)) & USB_INTEN_USBRSTEN_MASK)
79470 
79471 #define USB_INTEN_ERROREN_MASK                   (0x2U)
79472 #define USB_INTEN_ERROREN_SHIFT                  (1U)
79473 /*! ERROREN - ERROR Interrupt Enable
79474  *  0b0..Disable
79475  *  0b1..Enable
79476  */
79477 #define USB_INTEN_ERROREN(x)                     (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ERROREN_SHIFT)) & USB_INTEN_ERROREN_MASK)
79478 
79479 #define USB_INTEN_SOFTOKEN_MASK                  (0x4U)
79480 #define USB_INTEN_SOFTOKEN_SHIFT                 (2U)
79481 /*! SOFTOKEN - SOFTOK Interrupt Enable
79482  *  0b0..Disable
79483  *  0b1..Enable
79484  */
79485 #define USB_INTEN_SOFTOKEN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SOFTOKEN_SHIFT)) & USB_INTEN_SOFTOKEN_MASK)
79486 
79487 #define USB_INTEN_TOKDNEEN_MASK                  (0x8U)
79488 #define USB_INTEN_TOKDNEEN_SHIFT                 (3U)
79489 /*! TOKDNEEN - TOKDNE Interrupt Enable
79490  *  0b0..Disable
79491  *  0b1..Enable
79492  */
79493 #define USB_INTEN_TOKDNEEN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_INTEN_TOKDNEEN_SHIFT)) & USB_INTEN_TOKDNEEN_MASK)
79494 
79495 #define USB_INTEN_SLEEPEN_MASK                   (0x10U)
79496 #define USB_INTEN_SLEEPEN_SHIFT                  (4U)
79497 /*! SLEEPEN - SLEEP Interrupt Enable
79498  *  0b0..Disable
79499  *  0b1..Enable
79500  */
79501 #define USB_INTEN_SLEEPEN(x)                     (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SLEEPEN_SHIFT)) & USB_INTEN_SLEEPEN_MASK)
79502 
79503 #define USB_INTEN_RESUMEEN_MASK                  (0x20U)
79504 #define USB_INTEN_RESUMEEN_SHIFT                 (5U)
79505 /*! RESUMEEN - RESUME Interrupt Enable
79506  *  0b0..Disable
79507  *  0b1..Enable
79508  */
79509 #define USB_INTEN_RESUMEEN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_INTEN_RESUMEEN_SHIFT)) & USB_INTEN_RESUMEEN_MASK)
79510 
79511 #define USB_INTEN_ATTACHEN_MASK                  (0x40U)
79512 #define USB_INTEN_ATTACHEN_SHIFT                 (6U)
79513 /*! ATTACHEN - ATTACH Interrupt Enable
79514  *  0b0..Disable
79515  *  0b1..Enable
79516  */
79517 #define USB_INTEN_ATTACHEN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ATTACHEN_SHIFT)) & USB_INTEN_ATTACHEN_MASK)
79518 
79519 #define USB_INTEN_STALLEN_MASK                   (0x80U)
79520 #define USB_INTEN_STALLEN_SHIFT                  (7U)
79521 /*! STALLEN - STALL Interrupt Enable
79522  *  0b0..Disable
79523  *  0b1..Enable
79524  */
79525 #define USB_INTEN_STALLEN(x)                     (((uint8_t)(((uint8_t)(x)) << USB_INTEN_STALLEN_SHIFT)) & USB_INTEN_STALLEN_MASK)
79526 /*! @} */
79527 
79528 /*! @name ERRSTAT - Error Interrupt Status */
79529 /*! @{ */
79530 
79531 #define USB_ERRSTAT_PIDERR_MASK                  (0x1U)
79532 #define USB_ERRSTAT_PIDERR_SHIFT                 (0U)
79533 /*! PIDERR - PID Error Flag
79534  *  0b0..Did not fail
79535  *  0b1..Failed
79536  *  0b0..No effect
79537  *  0b1..Clear the flag
79538  */
79539 #define USB_ERRSTAT_PIDERR(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_PIDERR_SHIFT)) & USB_ERRSTAT_PIDERR_MASK)
79540 
79541 #define USB_ERRSTAT_CRC5EOF_MASK                 (0x2U)
79542 #define USB_ERRSTAT_CRC5EOF_SHIFT                (1U)
79543 /*! CRC5EOF - CRC5 Error or End of Frame Error Flag
79544  *  0b0..Interrupt did not occur
79545  *  0b1..Interrupt occurred
79546  *  0b0..No effect
79547  *  0b1..Clear the flag
79548  */
79549 #define USB_ERRSTAT_CRC5EOF(x)                   (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC5EOF_SHIFT)) & USB_ERRSTAT_CRC5EOF_MASK)
79550 
79551 #define USB_ERRSTAT_CRC16_MASK                   (0x4U)
79552 #define USB_ERRSTAT_CRC16_SHIFT                  (2U)
79553 /*! CRC16 - CRC16 Error Flag
79554  *  0b0..Not rejected
79555  *  0b1..Rejected
79556  *  0b0..No effect
79557  *  0b1..Clear the flag
79558  */
79559 #define USB_ERRSTAT_CRC16(x)                     (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC16_SHIFT)) & USB_ERRSTAT_CRC16_MASK)
79560 
79561 #define USB_ERRSTAT_DFN8_MASK                    (0x8U)
79562 #define USB_ERRSTAT_DFN8_SHIFT                   (3U)
79563 /*! DFN8 - Data Field Not 8 Bits Flag
79564  *  0b0..Integer number of bytes
79565  *  0b1..Not an integer number of bytes
79566  *  0b0..No effect
79567  *  0b1..Clear the flag
79568  */
79569 #define USB_ERRSTAT_DFN8(x)                      (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DFN8_SHIFT)) & USB_ERRSTAT_DFN8_MASK)
79570 
79571 #define USB_ERRSTAT_BTOERR_MASK                  (0x10U)
79572 #define USB_ERRSTAT_BTOERR_SHIFT                 (4U)
79573 /*! BTOERR - Bus Turnaround Timeout Error Flag
79574  *  0b0..Not timed out
79575  *  0b1..Timed out
79576  *  0b0..No effect
79577  *  0b1..Clear the flag
79578  */
79579 #define USB_ERRSTAT_BTOERR(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTOERR_SHIFT)) & USB_ERRSTAT_BTOERR_MASK)
79580 
79581 #define USB_ERRSTAT_DMAERR_MASK                  (0x20U)
79582 #define USB_ERRSTAT_DMAERR_SHIFT                 (5U)
79583 /*! DMAERR - DMA Access Error Flag
79584  *  0b0..Interrupt did not occur
79585  *  0b1..Interrupt occurred
79586  *  0b0..No effect
79587  *  0b1..Clear the flag
79588  */
79589 #define USB_ERRSTAT_DMAERR(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DMAERR_SHIFT)) & USB_ERRSTAT_DMAERR_MASK)
79590 
79591 #define USB_ERRSTAT_OWNERR_MASK                  (0x40U)
79592 #define USB_ERRSTAT_OWNERR_SHIFT                 (6U)
79593 /*! OWNERR - BD Unavailable Error Flag
79594  *  0b0..Interrupt did not occur
79595  *  0b1..Interrupt occurred
79596  *  0b0..No effect
79597  *  0b1..Clear the flag
79598  */
79599 #define USB_ERRSTAT_OWNERR(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_OWNERR_SHIFT)) & USB_ERRSTAT_OWNERR_MASK)
79600 
79601 #define USB_ERRSTAT_BTSERR_MASK                  (0x80U)
79602 #define USB_ERRSTAT_BTSERR_SHIFT                 (7U)
79603 /*! BTSERR - Bit Stuff Error Flag
79604  *  0b0..Packet not rejected due to the error
79605  *  0b1..Packet rejected due to the error
79606  *  0b0..No effect
79607  *  0b1..Clear the flag
79608  */
79609 #define USB_ERRSTAT_BTSERR(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTSERR_SHIFT)) & USB_ERRSTAT_BTSERR_MASK)
79610 /*! @} */
79611 
79612 /*! @name ERREN - Error Interrupt Enable */
79613 /*! @{ */
79614 
79615 #define USB_ERREN_PIDERREN_MASK                  (0x1U)
79616 #define USB_ERREN_PIDERREN_SHIFT                 (0U)
79617 /*! PIDERREN - PIDERR Interrupt Enable
79618  *  0b0..Disable
79619  *  0b1..Enable
79620  */
79621 #define USB_ERREN_PIDERREN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ERREN_PIDERREN_SHIFT)) & USB_ERREN_PIDERREN_MASK)
79622 
79623 #define USB_ERREN_CRC5EOFEN_MASK                 (0x2U)
79624 #define USB_ERREN_CRC5EOFEN_SHIFT                (1U)
79625 /*! CRC5EOFEN - CRC5/EOF Interrupt Enable
79626  *  0b0..Disable
79627  *  0b1..Enable
79628  */
79629 #define USB_ERREN_CRC5EOFEN(x)                   (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC5EOFEN_SHIFT)) & USB_ERREN_CRC5EOFEN_MASK)
79630 
79631 #define USB_ERREN_CRC16EN_MASK                   (0x4U)
79632 #define USB_ERREN_CRC16EN_SHIFT                  (2U)
79633 /*! CRC16EN - CRC16 Interrupt Enable
79634  *  0b0..Disable
79635  *  0b1..Enable
79636  */
79637 #define USB_ERREN_CRC16EN(x)                     (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC16EN_SHIFT)) & USB_ERREN_CRC16EN_MASK)
79638 
79639 #define USB_ERREN_DFN8EN_MASK                    (0x8U)
79640 #define USB_ERREN_DFN8EN_SHIFT                   (3U)
79641 /*! DFN8EN - DFN8 (Data Field Not Integer Number of Bytes) Interrupt Enable
79642  *  0b0..Disable
79643  *  0b1..Enable
79644  */
79645 #define USB_ERREN_DFN8EN(x)                      (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DFN8EN_SHIFT)) & USB_ERREN_DFN8EN_MASK)
79646 
79647 #define USB_ERREN_BTOERREN_MASK                  (0x10U)
79648 #define USB_ERREN_BTOERREN_SHIFT                 (4U)
79649 /*! BTOERREN - BTOERR (Bus Timeout Error) Interrupt Enable
79650  *  0b0..Disable
79651  *  0b1..Enable
79652  */
79653 #define USB_ERREN_BTOERREN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTOERREN_SHIFT)) & USB_ERREN_BTOERREN_MASK)
79654 
79655 #define USB_ERREN_DMAERREN_MASK                  (0x20U)
79656 #define USB_ERREN_DMAERREN_SHIFT                 (5U)
79657 /*! DMAERREN - DMAERR Interrupt Enable
79658  *  0b0..Disable
79659  *  0b1..Enable
79660  */
79661 #define USB_ERREN_DMAERREN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DMAERREN_SHIFT)) & USB_ERREN_DMAERREN_MASK)
79662 
79663 #define USB_ERREN_OWNERREN_MASK                  (0x40U)
79664 #define USB_ERREN_OWNERREN_SHIFT                 (6U)
79665 /*! OWNERREN - OWNERR Interrupt Enable
79666  *  0b0..Disable
79667  *  0b1..Enable
79668  */
79669 #define USB_ERREN_OWNERREN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ERREN_OWNERREN_SHIFT)) & USB_ERREN_OWNERREN_MASK)
79670 
79671 #define USB_ERREN_BTSERREN_MASK                  (0x80U)
79672 #define USB_ERREN_BTSERREN_SHIFT                 (7U)
79673 /*! BTSERREN - BTSERR (Bit Stuff Error) Interrupt Enable
79674  *  0b0..Disable
79675  *  0b1..Enable
79676  */
79677 #define USB_ERREN_BTSERREN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTSERREN_SHIFT)) & USB_ERREN_BTSERREN_MASK)
79678 /*! @} */
79679 
79680 /*! @name STAT - Status */
79681 /*! @{ */
79682 
79683 #define USB_STAT_ODD_MASK                        (0x4U)
79684 #define USB_STAT_ODD_SHIFT                       (2U)
79685 /*! ODD - Odd Bank
79686  *  0b0..Not in the odd bank
79687  *  0b1..In the odd bank
79688  */
79689 #define USB_STAT_ODD(x)                          (((uint8_t)(((uint8_t)(x)) << USB_STAT_ODD_SHIFT)) & USB_STAT_ODD_MASK)
79690 
79691 #define USB_STAT_TX_MASK                         (0x8U)
79692 #define USB_STAT_TX_SHIFT                        (3U)
79693 /*! TX - Transmit Indicator
79694  *  0b0..Receive
79695  *  0b1..Transmit
79696  */
79697 #define USB_STAT_TX(x)                           (((uint8_t)(((uint8_t)(x)) << USB_STAT_TX_SHIFT)) & USB_STAT_TX_MASK)
79698 
79699 #define USB_STAT_ENDP_MASK                       (0xF0U)
79700 #define USB_STAT_ENDP_SHIFT                      (4U)
79701 /*! ENDP - Endpoint address */
79702 #define USB_STAT_ENDP(x)                         (((uint8_t)(((uint8_t)(x)) << USB_STAT_ENDP_SHIFT)) & USB_STAT_ENDP_MASK)
79703 /*! @} */
79704 
79705 /*! @name CTL - Control */
79706 /*! @{ */
79707 
79708 #define USB_CTL_USBENSOFEN_MASK                  (0x1U)
79709 #define USB_CTL_USBENSOFEN_SHIFT                 (0U)
79710 /*! USBENSOFEN - USB Enable
79711  *  0b0..Disable
79712  *  0b1..Enable
79713  */
79714 #define USB_CTL_USBENSOFEN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_CTL_USBENSOFEN_SHIFT)) & USB_CTL_USBENSOFEN_MASK)
79715 
79716 #define USB_CTL_ODDRST_MASK                      (0x2U)
79717 #define USB_CTL_ODDRST_SHIFT                     (1U)
79718 /*! ODDRST - Odd Reset */
79719 #define USB_CTL_ODDRST(x)                        (((uint8_t)(((uint8_t)(x)) << USB_CTL_ODDRST_SHIFT)) & USB_CTL_ODDRST_MASK)
79720 
79721 #define USB_CTL_RESUME_MASK                      (0x4U)
79722 #define USB_CTL_RESUME_SHIFT                     (2U)
79723 /*! RESUME - Resume */
79724 #define USB_CTL_RESUME(x)                        (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESUME_SHIFT)) & USB_CTL_RESUME_MASK)
79725 
79726 #define USB_CTL_HOSTMODEEN_MASK                  (0x8U)
79727 #define USB_CTL_HOSTMODEEN_SHIFT                 (3U)
79728 /*! HOSTMODEEN - Host Mode Enable
79729  *  0b0..USBFS operates in Device mode.
79730  *  0b1..USBFS operates in Host mode. In Host mode, USBFS performs USB transactions under the programmed control of the host processor.
79731  */
79732 #define USB_CTL_HOSTMODEEN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_CTL_HOSTMODEEN_SHIFT)) & USB_CTL_HOSTMODEEN_MASK)
79733 
79734 #define USB_CTL_RESET_MASK                       (0x10U)
79735 #define USB_CTL_RESET_SHIFT                      (4U)
79736 /*! RESET - Reset Signaling Enable
79737  *  0b0..Disable
79738  *  0b1..Enable
79739  */
79740 #define USB_CTL_RESET(x)                         (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESET_SHIFT)) & USB_CTL_RESET_MASK)
79741 
79742 #define USB_CTL_TXSUSPENDTOKENBUSY_MASK          (0x20U)
79743 #define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT         (5U)
79744 /*! TXSUSPENDTOKENBUSY - TXD Suspend And Token Busy */
79745 #define USB_CTL_TXSUSPENDTOKENBUSY(x)            (((uint8_t)(((uint8_t)(x)) << USB_CTL_TXSUSPENDTOKENBUSY_SHIFT)) & USB_CTL_TXSUSPENDTOKENBUSY_MASK)
79746 
79747 #define USB_CTL_SE0_MASK                         (0x40U)
79748 #define USB_CTL_SE0_SHIFT                        (6U)
79749 /*! SE0 - Live USB Single-Ended Zero signal */
79750 #define USB_CTL_SE0(x)                           (((uint8_t)(((uint8_t)(x)) << USB_CTL_SE0_SHIFT)) & USB_CTL_SE0_MASK)
79751 
79752 #define USB_CTL_JSTATE_MASK                      (0x80U)
79753 #define USB_CTL_JSTATE_SHIFT                     (7U)
79754 /*! JSTATE - Live USB Differential Receiver JSTATE Signal */
79755 #define USB_CTL_JSTATE(x)                        (((uint8_t)(((uint8_t)(x)) << USB_CTL_JSTATE_SHIFT)) & USB_CTL_JSTATE_MASK)
79756 /*! @} */
79757 
79758 /*! @name ADDR - Address */
79759 /*! @{ */
79760 
79761 #define USB_ADDR_ADDR_MASK                       (0x7FU)
79762 #define USB_ADDR_ADDR_SHIFT                      (0U)
79763 /*! ADDR - USB Address */
79764 #define USB_ADDR_ADDR(x)                         (((uint8_t)(((uint8_t)(x)) << USB_ADDR_ADDR_SHIFT)) & USB_ADDR_ADDR_MASK)
79765 
79766 #define USB_ADDR_LSEN_MASK                       (0x80U)
79767 #define USB_ADDR_LSEN_SHIFT                      (7U)
79768 /*! LSEN - Low Speed Enable */
79769 #define USB_ADDR_LSEN(x)                         (((uint8_t)(((uint8_t)(x)) << USB_ADDR_LSEN_SHIFT)) & USB_ADDR_LSEN_MASK)
79770 /*! @} */
79771 
79772 /*! @name BDTPAGE1 - BDT Page 1 */
79773 /*! @{ */
79774 
79775 #define USB_BDTPAGE1_BDTBA_MASK                  (0xFEU)
79776 #define USB_BDTPAGE1_BDTBA_SHIFT                 (1U)
79777 /*! BDTBA - BDT Base Address */
79778 #define USB_BDTPAGE1_BDTBA(x)                    (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE1_BDTBA_SHIFT)) & USB_BDTPAGE1_BDTBA_MASK)
79779 /*! @} */
79780 
79781 /*! @name FRMNUML - Frame Number Register Low */
79782 /*! @{ */
79783 
79784 #define USB_FRMNUML_FRM_MASK                     (0xFFU)
79785 #define USB_FRMNUML_FRM_SHIFT                    (0U)
79786 /*! FRM - Frame Number, Bits 0-7 */
79787 #define USB_FRMNUML_FRM(x)                       (((uint8_t)(((uint8_t)(x)) << USB_FRMNUML_FRM_SHIFT)) & USB_FRMNUML_FRM_MASK)
79788 /*! @} */
79789 
79790 /*! @name FRMNUMH - Frame Number Register High */
79791 /*! @{ */
79792 
79793 #define USB_FRMNUMH_FRM_MASK                     (0x7U)
79794 #define USB_FRMNUMH_FRM_SHIFT                    (0U)
79795 /*! FRM - Frame Number, Bits 8-10 */
79796 #define USB_FRMNUMH_FRM(x)                       (((uint8_t)(((uint8_t)(x)) << USB_FRMNUMH_FRM_SHIFT)) & USB_FRMNUMH_FRM_MASK)
79797 /*! @} */
79798 
79799 /*! @name TOKEN - Token */
79800 /*! @{ */
79801 
79802 #define USB_TOKEN_TOKENENDPT_MASK                (0xFU)
79803 #define USB_TOKEN_TOKENENDPT_SHIFT               (0U)
79804 /*! TOKENENDPT - Token Endpoint Address */
79805 #define USB_TOKEN_TOKENENDPT(x)                  (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENENDPT_SHIFT)) & USB_TOKEN_TOKENENDPT_MASK)
79806 
79807 #define USB_TOKEN_TOKENPID_MASK                  (0xF0U)
79808 #define USB_TOKEN_TOKENPID_SHIFT                 (4U)
79809 /*! TOKENPID - Token Type
79810  *  0b0001..OUT token. USBFS performs an OUT (TX) transaction.
79811  *  0b1001..IN token. USBFS performs an IN (RX) transaction.
79812  *  0b1101..SETUP token. USBFS performs a SETUP (TX) transaction
79813  */
79814 #define USB_TOKEN_TOKENPID(x)                    (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENPID_SHIFT)) & USB_TOKEN_TOKENPID_MASK)
79815 /*! @} */
79816 
79817 /*! @name SOFTHLD - SOF Threshold */
79818 /*! @{ */
79819 
79820 #define USB_SOFTHLD_CNT_MASK                     (0xFFU)
79821 #define USB_SOFTHLD_CNT_SHIFT                    (0U)
79822 /*! CNT - SOF Count Threshold */
79823 #define USB_SOFTHLD_CNT(x)                       (((uint8_t)(((uint8_t)(x)) << USB_SOFTHLD_CNT_SHIFT)) & USB_SOFTHLD_CNT_MASK)
79824 /*! @} */
79825 
79826 /*! @name BDTPAGE2 - BDT Page 2 */
79827 /*! @{ */
79828 
79829 #define USB_BDTPAGE2_BDTBA_MASK                  (0xFFU)
79830 #define USB_BDTPAGE2_BDTBA_SHIFT                 (0U)
79831 /*! BDTBA - BDT Base Address */
79832 #define USB_BDTPAGE2_BDTBA(x)                    (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE2_BDTBA_SHIFT)) & USB_BDTPAGE2_BDTBA_MASK)
79833 /*! @} */
79834 
79835 /*! @name BDTPAGE3 - BDT Page 3 */
79836 /*! @{ */
79837 
79838 #define USB_BDTPAGE3_BDTBA_MASK                  (0xFFU)
79839 #define USB_BDTPAGE3_BDTBA_SHIFT                 (0U)
79840 /*! BDTBA - BDT Base Address */
79841 #define USB_BDTPAGE3_BDTBA(x)                    (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE3_BDTBA_SHIFT)) & USB_BDTPAGE3_BDTBA_MASK)
79842 /*! @} */
79843 
79844 /*! @name ENDPT - Endpoint Control */
79845 /*! @{ */
79846 
79847 #define USB_ENDPT_EPHSHK_MASK                    (0x1U)
79848 #define USB_ENDPT_EPHSHK_SHIFT                   (0U)
79849 /*! EPHSHK - Endpoint Handshaking Enable */
79850 #define USB_ENDPT_EPHSHK(x)                      (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPHSHK_SHIFT)) & USB_ENDPT_EPHSHK_MASK)
79851 
79852 #define USB_ENDPT_EPSTALL_MASK                   (0x2U)
79853 #define USB_ENDPT_EPSTALL_SHIFT                  (1U)
79854 /*! EPSTALL - Endpoint Stalled */
79855 #define USB_ENDPT_EPSTALL(x)                     (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPSTALL_SHIFT)) & USB_ENDPT_EPSTALL_MASK)
79856 
79857 #define USB_ENDPT_EPTXEN_MASK                    (0x4U)
79858 #define USB_ENDPT_EPTXEN_SHIFT                   (2U)
79859 /*! EPTXEN - Endpoint for TX transfers enable */
79860 #define USB_ENDPT_EPTXEN(x)                      (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPTXEN_SHIFT)) & USB_ENDPT_EPTXEN_MASK)
79861 
79862 #define USB_ENDPT_EPRXEN_MASK                    (0x8U)
79863 #define USB_ENDPT_EPRXEN_SHIFT                   (3U)
79864 /*! EPRXEN - Endpoint for RX transfers enable */
79865 #define USB_ENDPT_EPRXEN(x)                      (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPRXEN_SHIFT)) & USB_ENDPT_EPRXEN_MASK)
79866 
79867 #define USB_ENDPT_EPCTLDIS_MASK                  (0x10U)
79868 #define USB_ENDPT_EPCTLDIS_SHIFT                 (4U)
79869 /*! EPCTLDIS - Control Transfer Disable
79870  *  0b0..Enable
79871  *  0b1..Disable
79872  */
79873 #define USB_ENDPT_EPCTLDIS(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPCTLDIS_SHIFT)) & USB_ENDPT_EPCTLDIS_MASK)
79874 
79875 #define USB_ENDPT_RETRYDIS_MASK                  (0x40U)
79876 #define USB_ENDPT_RETRYDIS_SHIFT                 (6U)
79877 /*! RETRYDIS - Retry Disable
79878  *  0b0..Retried NAK'ed transactions in hardware.
79879  *  0b1..Do not retry NAK'ed transactions. When a transaction is NAK'ed, the BDT PID field is updated with the NAK
79880  *       PID, and the TOKEN_DNE interrupt becomes 1.
79881  */
79882 #define USB_ENDPT_RETRYDIS(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_RETRYDIS_SHIFT)) & USB_ENDPT_RETRYDIS_MASK)
79883 
79884 #define USB_ENDPT_HOSTWOHUB_MASK                 (0x80U)
79885 #define USB_ENDPT_HOSTWOHUB_SHIFT                (7U)
79886 /*! HOSTWOHUB - Host Without A Hub
79887  *  0b0..Connected using a hub (USBFS generates PRE_PID as required)
79888  *  0b1..Connected directly to host without a hub, or was used to attach
79889  */
79890 #define USB_ENDPT_HOSTWOHUB(x)                   (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_HOSTWOHUB_SHIFT)) & USB_ENDPT_HOSTWOHUB_MASK)
79891 /*! @} */
79892 
79893 /* The count of USB_ENDPT */
79894 #define USB_ENDPT_COUNT                          (16U)
79895 
79896 /*! @name USBCTRL - USB Control */
79897 /*! @{ */
79898 
79899 #define USB_USBCTRL_DPDM_LANE_REVERSE_MASK       (0x4U)
79900 #define USB_USBCTRL_DPDM_LANE_REVERSE_SHIFT      (2U)
79901 /*! DPDM_LANE_REVERSE - DP and DM Lane Reversal Control
79902  *  0b0..Standard USB DP and DM package pin assignment
79903  *  0b1..Reverse roles of USB DP and DM package pins
79904  */
79905 #define USB_USBCTRL_DPDM_LANE_REVERSE(x)         (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_DPDM_LANE_REVERSE_SHIFT)) & USB_USBCTRL_DPDM_LANE_REVERSE_MASK)
79906 
79907 #define USB_USBCTRL_HOST_LS_EOP_MASK             (0x8U)
79908 #define USB_USBCTRL_HOST_LS_EOP_SHIFT            (3U)
79909 /*! HOST_LS_EOP - Host-Mode-Only Low-Speed Device EOP Signaling
79910  *  0b0..Full-speed device or a low-speed device through a hub
79911  *  0b1..Directly-connected low-speed device
79912  */
79913 #define USB_USBCTRL_HOST_LS_EOP(x)               (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_HOST_LS_EOP_SHIFT)) & USB_USBCTRL_HOST_LS_EOP_MASK)
79914 
79915 #define USB_USBCTRL_UARTSEL_MASK                 (0x10U)
79916 #define USB_USBCTRL_UARTSEL_SHIFT                (4U)
79917 /*! UARTSEL - UART Select
79918  *  0b0..USB DP and DM external package pins are used for USB signaling.
79919  *  0b1..USB DP and DM external package pins are used for UART signaling.
79920  */
79921 #define USB_USBCTRL_UARTSEL(x)                   (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_UARTSEL_SHIFT)) & USB_USBCTRL_UARTSEL_MASK)
79922 
79923 #define USB_USBCTRL_UARTCHLS_MASK                (0x20U)
79924 #define USB_USBCTRL_UARTCHLS_SHIFT               (5U)
79925 /*! UARTCHLS - UART Signal Channel Select
79926  *  0b0..USB DP and DM signals are used as UART TX/RX.
79927  *  0b1..USB DP and DM signals are used as UART RX/TX.
79928  */
79929 #define USB_USBCTRL_UARTCHLS(x)                  (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_UARTCHLS_SHIFT)) & USB_USBCTRL_UARTCHLS_MASK)
79930 
79931 #define USB_USBCTRL_PDE_MASK                     (0x40U)
79932 #define USB_USBCTRL_PDE_SHIFT                    (6U)
79933 /*! PDE - Pulldown Enable
79934  *  0b0..Disable on D+ and D-
79935  *  0b1..Enable on D+ and D-
79936  */
79937 #define USB_USBCTRL_PDE(x)                       (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_PDE_SHIFT)) & USB_USBCTRL_PDE_MASK)
79938 
79939 #define USB_USBCTRL_SUSP_MASK                    (0x80U)
79940 #define USB_USBCTRL_SUSP_SHIFT                   (7U)
79941 /*! SUSP - Suspend
79942  *  0b0..Not in Suspend state
79943  *  0b1..In Suspend state
79944  */
79945 #define USB_USBCTRL_SUSP(x)                      (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_SUSP_SHIFT)) & USB_USBCTRL_SUSP_MASK)
79946 /*! @} */
79947 
79948 /*! @name OBSERVE - USB OTG Observe */
79949 /*! @{ */
79950 
79951 #define USB_OBSERVE_DMPD_MASK                    (0x10U)
79952 #define USB_OBSERVE_DMPD_SHIFT                   (4U)
79953 /*! DMPD - D- Pulldown
79954  *  0b0..Disabled
79955  *  0b1..Enabled
79956  */
79957 #define USB_OBSERVE_DMPD(x)                      (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DMPD_SHIFT)) & USB_OBSERVE_DMPD_MASK)
79958 
79959 #define USB_OBSERVE_DPPD_MASK                    (0x40U)
79960 #define USB_OBSERVE_DPPD_SHIFT                   (6U)
79961 /*! DPPD - D+ Pulldown
79962  *  0b0..Disabled
79963  *  0b1..Enabled
79964  */
79965 #define USB_OBSERVE_DPPD(x)                      (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPD_SHIFT)) & USB_OBSERVE_DPPD_MASK)
79966 
79967 #define USB_OBSERVE_DPPU_MASK                    (0x80U)
79968 #define USB_OBSERVE_DPPU_SHIFT                   (7U)
79969 /*! DPPU - D+ Pullup
79970  *  0b0..Disabled
79971  *  0b1..Enabled
79972  */
79973 #define USB_OBSERVE_DPPU(x)                      (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPU_SHIFT)) & USB_OBSERVE_DPPU_MASK)
79974 /*! @} */
79975 
79976 /*! @name CONTROL - USB OTG Control */
79977 /*! @{ */
79978 
79979 #define USB_CONTROL_VBUS_SOURCE_SEL_MASK         (0x1U)
79980 #define USB_CONTROL_VBUS_SOURCE_SEL_SHIFT        (0U)
79981 /*! VBUS_SOURCE_SEL - VBUS Monitoring Source Select
79982  *  0b0..Reserved
79983  *  0b1..Resistive divider attached to a GPIO pin
79984  */
79985 #define USB_CONTROL_VBUS_SOURCE_SEL(x)           (((uint8_t)(((uint8_t)(x)) << USB_CONTROL_VBUS_SOURCE_SEL_SHIFT)) & USB_CONTROL_VBUS_SOURCE_SEL_MASK)
79986 
79987 #define USB_CONTROL_SESS_VLD_MASK                (0x2U)
79988 #define USB_CONTROL_SESS_VLD_SHIFT               (1U)
79989 /*! SESS_VLD - VBUS Session Valid status
79990  *  0b1..Above
79991  *  0b0..Below
79992  */
79993 #define USB_CONTROL_SESS_VLD(x)                  (((uint8_t)(((uint8_t)(x)) << USB_CONTROL_SESS_VLD_SHIFT)) & USB_CONTROL_SESS_VLD_MASK)
79994 
79995 #define USB_CONTROL_DPPULLUPNONOTG_MASK          (0x10U)
79996 #define USB_CONTROL_DPPULLUPNONOTG_SHIFT         (4U)
79997 /*! DPPULLUPNONOTG - DP Pullup in Non-OTG Device Mode
79998  *  0b0..Disable
79999  *  0b1..Enabled
80000  */
80001 #define USB_CONTROL_DPPULLUPNONOTG(x)            (((uint8_t)(((uint8_t)(x)) << USB_CONTROL_DPPULLUPNONOTG_SHIFT)) & USB_CONTROL_DPPULLUPNONOTG_MASK)
80002 /*! @} */
80003 
80004 /*! @name USBTRC0 - USB Transceiver Control 0 */
80005 /*! @{ */
80006 
80007 #define USB_USBTRC0_USB_RESUME_INT_MASK          (0x1U)
80008 #define USB_USBTRC0_USB_RESUME_INT_SHIFT         (0U)
80009 /*! USB_RESUME_INT - USB Asynchronous Interrupt
80010  *  0b0..Not generated
80011  *  0b1..Generated because of the USB asynchronous interrupt
80012  */
80013 #define USB_USBTRC0_USB_RESUME_INT(x)            (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_RESUME_INT_SHIFT)) & USB_USBTRC0_USB_RESUME_INT_MASK)
80014 
80015 #define USB_USBTRC0_SYNC_DET_MASK                (0x2U)
80016 #define USB_USBTRC0_SYNC_DET_SHIFT               (1U)
80017 /*! SYNC_DET - Synchronous USB Interrupt Detect
80018  *  0b0..Not detected
80019  *  0b1..Detected
80020  */
80021 #define USB_USBTRC0_SYNC_DET(x)                  (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_SYNC_DET_SHIFT)) & USB_USBTRC0_SYNC_DET_MASK)
80022 
80023 #define USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK    (0x4U)
80024 #define USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT   (2U)
80025 /*! USB_CLK_RECOVERY_INT - Combined USB Clock Recovery interrupt status */
80026 #define USB_USBTRC0_USB_CLK_RECOVERY_INT(x)      (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT)) & USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK)
80027 
80028 #define USB_USBTRC0_VREDG_DET_MASK               (0x8U)
80029 #define USB_USBTRC0_VREDG_DET_SHIFT              (3U)
80030 /*! VREDG_DET - VREGIN Rising Edge Interrupt Detect
80031  *  0b0..Not detected
80032  *  0b1..Detected
80033  */
80034 #define USB_USBTRC0_VREDG_DET(x)                 (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_VREDG_DET_SHIFT)) & USB_USBTRC0_VREDG_DET_MASK)
80035 
80036 #define USB_USBTRC0_VFEDG_DET_MASK               (0x10U)
80037 #define USB_USBTRC0_VFEDG_DET_SHIFT              (4U)
80038 /*! VFEDG_DET - VREGIN Falling Edge Interrupt Detect
80039  *  0b0..Not detected
80040  *  0b1..Detected
80041  */
80042 #define USB_USBTRC0_VFEDG_DET(x)                 (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_VFEDG_DET_SHIFT)) & USB_USBTRC0_VFEDG_DET_MASK)
80043 
80044 #define USB_USBTRC0_USBRESMEN_MASK               (0x20U)
80045 #define USB_USBTRC0_USBRESMEN_SHIFT              (5U)
80046 /*! USBRESMEN - Asynchronous Resume Interrupt Enable
80047  *  0b0..Disable
80048  *  0b1..Enable
80049  */
80050 #define USB_USBTRC0_USBRESMEN(x)                 (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESMEN_SHIFT)) & USB_USBTRC0_USBRESMEN_MASK)
80051 
80052 #define USB_USBTRC0_VREGIN_STS_MASK              (0x40U)
80053 #define USB_USBTRC0_VREGIN_STS_SHIFT             (6U)
80054 /*! VREGIN_STS - VREGIN Status */
80055 #define USB_USBTRC0_VREGIN_STS(x)                (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_VREGIN_STS_SHIFT)) & USB_USBTRC0_VREGIN_STS_MASK)
80056 
80057 #define USB_USBTRC0_USBRESET_MASK                (0x80U)
80058 #define USB_USBTRC0_USBRESET_SHIFT               (7U)
80059 /*! USBRESET - USB Reset
80060  *  0b0..Normal USBFS operation
80061  *  0b1..Returns USBFS to its reset state
80062  */
80063 #define USB_USBTRC0_USBRESET(x)                  (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESET_SHIFT)) & USB_USBTRC0_USBRESET_MASK)
80064 /*! @} */
80065 
80066 /*! @name USBFRMADJUST - Frame Adjust */
80067 /*! @{ */
80068 
80069 #define USB_USBFRMADJUST_ADJ_MASK                (0xFFU)
80070 #define USB_USBFRMADJUST_ADJ_SHIFT               (0U)
80071 /*! ADJ - Frame Adjustment */
80072 #define USB_USBFRMADJUST_ADJ(x)                  (((uint8_t)(((uint8_t)(x)) << USB_USBFRMADJUST_ADJ_SHIFT)) & USB_USBFRMADJUST_ADJ_MASK)
80073 /*! @} */
80074 
80075 /*! @name KEEP_ALIVE_CTRL - Keep Alive Mode Control */
80076 /*! @{ */
80077 
80078 #define USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_EN_MASK   (0x1U)
80079 #define USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_EN_SHIFT  (0U)
80080 /*! KEEP_ALIVE_EN - Keep Alive Mode Enable
80081  *  0b0..Everything remains same as before.
80082  *  0b1..USB shall enter USB_KEEP_ALIVE mode after asserting ipg_stop.
80083  */
80084 #define USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_EN(x)     (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_EN_SHIFT)) & USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_EN_MASK)
80085 
80086 #define USB_KEEP_ALIVE_CTRL_OWN_OVERRD_EN_MASK   (0x2U)
80087 #define USB_KEEP_ALIVE_CTRL_OWN_OVERRD_EN_SHIFT  (1U)
80088 /*! OWN_OVERRD_EN - OWN Bit Override Enable */
80089 #define USB_KEEP_ALIVE_CTRL_OWN_OVERRD_EN(x)     (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_OWN_OVERRD_EN_SHIFT)) & USB_KEEP_ALIVE_CTRL_OWN_OVERRD_EN_MASK)
80090 
80091 #define USB_KEEP_ALIVE_CTRL_STOP_ACK_DLY_EN_MASK (0x4U)
80092 #define USB_KEEP_ALIVE_CTRL_STOP_ACK_DLY_EN_SHIFT (2U)
80093 /*! STOP_ACK_DLY_EN - Stop Acknowledge Delay Enable
80094  *  0b0..Enter KEEP_ALIVE mode immediately when there is no USB AHB transfer.
80095  *  0b1..Enter KEEP_ALIVE mode until the USB core is idle and there is no USB AHB transfer.
80096  */
80097 #define USB_KEEP_ALIVE_CTRL_STOP_ACK_DLY_EN(x)   (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_STOP_ACK_DLY_EN_SHIFT)) & USB_KEEP_ALIVE_CTRL_STOP_ACK_DLY_EN_MASK)
80098 
80099 #define USB_KEEP_ALIVE_CTRL_WAKE_REQ_EN_MASK     (0x8U)
80100 #define USB_KEEP_ALIVE_CTRL_WAKE_REQ_EN_SHIFT    (3U)
80101 /*! WAKE_REQ_EN - Wakeup Request Enable
80102  *  0b0..Disable
80103  *  0b1..Enable
80104  */
80105 #define USB_KEEP_ALIVE_CTRL_WAKE_REQ_EN(x)       (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_WAKE_REQ_EN_SHIFT)) & USB_KEEP_ALIVE_CTRL_WAKE_REQ_EN_MASK)
80106 
80107 #define USB_KEEP_ALIVE_CTRL_WAKE_INT_EN_MASK     (0x10U)
80108 #define USB_KEEP_ALIVE_CTRL_WAKE_INT_EN_SHIFT    (4U)
80109 /*! WAKE_INT_EN - Wakeup Interrupt Enable */
80110 #define USB_KEEP_ALIVE_CTRL_WAKE_INT_EN(x)       (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_WAKE_INT_EN_SHIFT)) & USB_KEEP_ALIVE_CTRL_WAKE_INT_EN_MASK)
80111 
80112 #define USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_STS_MASK  (0x40U)
80113 #define USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_STS_SHIFT (6U)
80114 /*! KEEP_ALIVE_STS - Keep Alive Status
80115  *  0b0..Not in Keep Alive mode
80116  *  0b1..In Keep Alive mode
80117  */
80118 #define USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_STS(x)    (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_STS_SHIFT)) & USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_STS_MASK)
80119 
80120 #define USB_KEEP_ALIVE_CTRL_WAKE_INT_STS_MASK    (0x80U)
80121 #define USB_KEEP_ALIVE_CTRL_WAKE_INT_STS_SHIFT   (7U)
80122 /*! WAKE_INT_STS - Wakeup Interrupt Status Flag
80123  *  0b0..Interrupt did not occur
80124  *  0b1..Interrupt occurred
80125  *  0b0..No effect
80126  *  0b1..Clear the flag
80127  */
80128 #define USB_KEEP_ALIVE_CTRL_WAKE_INT_STS(x)      (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_WAKE_INT_STS_SHIFT)) & USB_KEEP_ALIVE_CTRL_WAKE_INT_STS_MASK)
80129 /*! @} */
80130 
80131 /*! @name KEEP_ALIVE_WKCTRL - Keep Alive Mode Wakeup Control */
80132 /*! @{ */
80133 
80134 #define USB_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS_MASK  (0xFU)
80135 #define USB_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS_SHIFT (0U)
80136 /*! WAKE_ON_THIS - Token PID for the wakeup request
80137  *  0b0001..Wake up after receiving OUT or SETUP token packet.
80138  *  0b1101..Wake up after receiving SETUP token packet. All other values are reserved.
80139  */
80140 #define USB_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS(x)    (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS_SHIFT)) & USB_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS_MASK)
80141 
80142 #define USB_KEEP_ALIVE_WKCTRL_WAKE_ENDPT_MASK    (0xF0U)
80143 #define USB_KEEP_ALIVE_WKCTRL_WAKE_ENDPT_SHIFT   (4U)
80144 /*! WAKE_ENDPT - Endpoint address for the wakeup request */
80145 #define USB_KEEP_ALIVE_WKCTRL_WAKE_ENDPT(x)      (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_WKCTRL_WAKE_ENDPT_SHIFT)) & USB_KEEP_ALIVE_WKCTRL_WAKE_ENDPT_MASK)
80146 /*! @} */
80147 
80148 /*! @name MISCCTRL - Miscellaneous Control */
80149 /*! @{ */
80150 
80151 #define USB_MISCCTRL_SOFDYNTHLD_MASK             (0x1U)
80152 #define USB_MISCCTRL_SOFDYNTHLD_SHIFT            (0U)
80153 /*! SOFDYNTHLD - Dynamic SOF Threshold Compare mode
80154  *  0b0..When the byte-times SOF threshold is reached
80155  *  0b1..When 8 byte-times SOF threshold is reached or overstepped
80156  */
80157 #define USB_MISCCTRL_SOFDYNTHLD(x)               (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_SOFDYNTHLD_SHIFT)) & USB_MISCCTRL_SOFDYNTHLD_MASK)
80158 
80159 #define USB_MISCCTRL_SOFBUSSET_MASK              (0x2U)
80160 #define USB_MISCCTRL_SOFBUSSET_SHIFT             (1U)
80161 /*! SOFBUSSET - SOF_TOK Interrupt Generation Mode Select
80162  *  0b0..According to the SOF threshold value
80163  *  0b1..When the SOF counter reaches 0
80164  */
80165 #define USB_MISCCTRL_SOFBUSSET(x)                (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_SOFBUSSET_SHIFT)) & USB_MISCCTRL_SOFBUSSET_MASK)
80166 
80167 #define USB_MISCCTRL_OWNERRISODIS_MASK           (0x4U)
80168 #define USB_MISCCTRL_OWNERRISODIS_SHIFT          (2U)
80169 /*! OWNERRISODIS - OWN Error Detect for ISO IN and ISO OUT Disable
80170  *  0b0..Enable
80171  *  0b1..Disable
80172  */
80173 #define USB_MISCCTRL_OWNERRISODIS(x)             (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_OWNERRISODIS_SHIFT)) & USB_MISCCTRL_OWNERRISODIS_MASK)
80174 
80175 #define USB_MISCCTRL_VREDG_EN_MASK               (0x8U)
80176 #define USB_MISCCTRL_VREDG_EN_SHIFT              (3U)
80177 /*! VREDG_EN - VREGIN Rising Edge Interrupt Enable
80178  *  0b0..Disable
80179  *  0b1..Enable
80180  */
80181 #define USB_MISCCTRL_VREDG_EN(x)                 (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_VREDG_EN_SHIFT)) & USB_MISCCTRL_VREDG_EN_MASK)
80182 
80183 #define USB_MISCCTRL_VFEDG_EN_MASK               (0x10U)
80184 #define USB_MISCCTRL_VFEDG_EN_SHIFT              (4U)
80185 /*! VFEDG_EN - VREGIN Falling Edge Interrupt Enable
80186  *  0b0..Disable
80187  *  0b1..Enable
80188  */
80189 #define USB_MISCCTRL_VFEDG_EN(x)                 (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_VFEDG_EN_SHIFT)) & USB_MISCCTRL_VFEDG_EN_MASK)
80190 
80191 #define USB_MISCCTRL_STL_ADJ_EN_MASK             (0x80U)
80192 #define USB_MISCCTRL_STL_ADJ_EN_SHIFT            (7U)
80193 /*! STL_ADJ_EN - USB Peripheral Mode Stall Adjust Enable
80194  *  0b0..If ENDPTn[END_STALL] = 1, both IN and OUT directions for the associated endpoint stalls.
80195  *  0b1..If ENDPTn[END_STALL] = 1, the STALL_xx_DIS registers control which directions for the associated endpoint stalls.
80196  */
80197 #define USB_MISCCTRL_STL_ADJ_EN(x)               (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_STL_ADJ_EN_SHIFT)) & USB_MISCCTRL_STL_ADJ_EN_MASK)
80198 /*! @} */
80199 
80200 /*! @name STALL_IL_DIS - Peripheral Mode Stall Disable for Endpoints 7 to 0 in IN Direction */
80201 /*! @{ */
80202 
80203 #define USB_STALL_IL_DIS_STALL_I_DIS0_MASK       (0x1U)
80204 #define USB_STALL_IL_DIS_STALL_I_DIS0_SHIFT      (0U)
80205 /*! STALL_I_DIS0 - Disable Endpoint 0 IN Direction
80206  *  0b0..Enable
80207  *  0b1..Disable
80208  */
80209 #define USB_STALL_IL_DIS_STALL_I_DIS0(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS0_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS0_MASK)
80210 
80211 #define USB_STALL_IL_DIS_STALL_I_DIS1_MASK       (0x2U)
80212 #define USB_STALL_IL_DIS_STALL_I_DIS1_SHIFT      (1U)
80213 /*! STALL_I_DIS1 - Disable Endpoint 1 IN Direction
80214  *  0b0..Enable
80215  *  0b1..Disable
80216  */
80217 #define USB_STALL_IL_DIS_STALL_I_DIS1(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS1_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS1_MASK)
80218 
80219 #define USB_STALL_IL_DIS_STALL_I_DIS2_MASK       (0x4U)
80220 #define USB_STALL_IL_DIS_STALL_I_DIS2_SHIFT      (2U)
80221 /*! STALL_I_DIS2 - Disable Endpoint 2 IN Direction
80222  *  0b0..Enable
80223  *  0b1..Disable
80224  */
80225 #define USB_STALL_IL_DIS_STALL_I_DIS2(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS2_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS2_MASK)
80226 
80227 #define USB_STALL_IL_DIS_STALL_I_DIS3_MASK       (0x8U)
80228 #define USB_STALL_IL_DIS_STALL_I_DIS3_SHIFT      (3U)
80229 /*! STALL_I_DIS3 - Disable Endpoint 3 IN Direction
80230  *  0b0..Enable
80231  *  0b1..Disable
80232  */
80233 #define USB_STALL_IL_DIS_STALL_I_DIS3(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS3_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS3_MASK)
80234 
80235 #define USB_STALL_IL_DIS_STALL_I_DIS4_MASK       (0x10U)
80236 #define USB_STALL_IL_DIS_STALL_I_DIS4_SHIFT      (4U)
80237 /*! STALL_I_DIS4 - Disable Endpoint 4 IN Direction
80238  *  0b0..Enable
80239  *  0b1..Disable
80240  */
80241 #define USB_STALL_IL_DIS_STALL_I_DIS4(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS4_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS4_MASK)
80242 
80243 #define USB_STALL_IL_DIS_STALL_I_DIS5_MASK       (0x20U)
80244 #define USB_STALL_IL_DIS_STALL_I_DIS5_SHIFT      (5U)
80245 /*! STALL_I_DIS5 - Disable Endpoint 5 IN Direction
80246  *  0b0..Enable
80247  *  0b1..Disable
80248  */
80249 #define USB_STALL_IL_DIS_STALL_I_DIS5(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS5_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS5_MASK)
80250 
80251 #define USB_STALL_IL_DIS_STALL_I_DIS6_MASK       (0x40U)
80252 #define USB_STALL_IL_DIS_STALL_I_DIS6_SHIFT      (6U)
80253 /*! STALL_I_DIS6 - Disable Endpoint 6 IN Direction
80254  *  0b0..Enable
80255  *  0b1..Disable
80256  */
80257 #define USB_STALL_IL_DIS_STALL_I_DIS6(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS6_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS6_MASK)
80258 
80259 #define USB_STALL_IL_DIS_STALL_I_DIS7_MASK       (0x80U)
80260 #define USB_STALL_IL_DIS_STALL_I_DIS7_SHIFT      (7U)
80261 /*! STALL_I_DIS7 - Disable Endpoint 7 IN Direction
80262  *  0b0..Enable
80263  *  0b1..Disable
80264  */
80265 #define USB_STALL_IL_DIS_STALL_I_DIS7(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS7_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS7_MASK)
80266 /*! @} */
80267 
80268 /*! @name STALL_IH_DIS - Peripheral Mode Stall Disable for Endpoints 15 to 8 in IN Direction */
80269 /*! @{ */
80270 
80271 #define USB_STALL_IH_DIS_STALL_I_DIS8_MASK       (0x1U)
80272 #define USB_STALL_IH_DIS_STALL_I_DIS8_SHIFT      (0U)
80273 /*! STALL_I_DIS8 - Disable Endpoint 8 IN Direction
80274  *  0b0..Enable
80275  *  0b1..Disable
80276  */
80277 #define USB_STALL_IH_DIS_STALL_I_DIS8(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS8_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS8_MASK)
80278 
80279 #define USB_STALL_IH_DIS_STALL_I_DIS9_MASK       (0x2U)
80280 #define USB_STALL_IH_DIS_STALL_I_DIS9_SHIFT      (1U)
80281 /*! STALL_I_DIS9 - Disable Endpoint 9 IN Direction
80282  *  0b0..Enable
80283  *  0b1..Disable
80284  */
80285 #define USB_STALL_IH_DIS_STALL_I_DIS9(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS9_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS9_MASK)
80286 
80287 #define USB_STALL_IH_DIS_STALL_I_DIS10_MASK      (0x4U)
80288 #define USB_STALL_IH_DIS_STALL_I_DIS10_SHIFT     (2U)
80289 /*! STALL_I_DIS10 - Disable Endpoint 10 IN Direction
80290  *  0b0..Enable
80291  *  0b1..Disable
80292  */
80293 #define USB_STALL_IH_DIS_STALL_I_DIS10(x)        (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS10_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS10_MASK)
80294 
80295 #define USB_STALL_IH_DIS_STALL_I_DIS11_MASK      (0x8U)
80296 #define USB_STALL_IH_DIS_STALL_I_DIS11_SHIFT     (3U)
80297 /*! STALL_I_DIS11 - Disable Endpoint 11 IN Direction
80298  *  0b0..Enable
80299  *  0b1..Disable
80300  */
80301 #define USB_STALL_IH_DIS_STALL_I_DIS11(x)        (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS11_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS11_MASK)
80302 
80303 #define USB_STALL_IH_DIS_STALL_I_DIS12_MASK      (0x10U)
80304 #define USB_STALL_IH_DIS_STALL_I_DIS12_SHIFT     (4U)
80305 /*! STALL_I_DIS12 - Disable Endpoint 12 IN Direction
80306  *  0b0..Enable
80307  *  0b1..Disable
80308  */
80309 #define USB_STALL_IH_DIS_STALL_I_DIS12(x)        (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS12_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS12_MASK)
80310 
80311 #define USB_STALL_IH_DIS_STALL_I_DIS13_MASK      (0x20U)
80312 #define USB_STALL_IH_DIS_STALL_I_DIS13_SHIFT     (5U)
80313 /*! STALL_I_DIS13 - Disable Endpoint 13 IN Direction
80314  *  0b0..Enable
80315  *  0b1..Disable
80316  */
80317 #define USB_STALL_IH_DIS_STALL_I_DIS13(x)        (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS13_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS13_MASK)
80318 
80319 #define USB_STALL_IH_DIS_STALL_I_DIS14_MASK      (0x40U)
80320 #define USB_STALL_IH_DIS_STALL_I_DIS14_SHIFT     (6U)
80321 /*! STALL_I_DIS14 - Disable Endpoint 14 IN Direction
80322  *  0b0..Enable
80323  *  0b1..Disable
80324  */
80325 #define USB_STALL_IH_DIS_STALL_I_DIS14(x)        (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS14_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS14_MASK)
80326 
80327 #define USB_STALL_IH_DIS_STALL_I_DIS15_MASK      (0x80U)
80328 #define USB_STALL_IH_DIS_STALL_I_DIS15_SHIFT     (7U)
80329 /*! STALL_I_DIS15 - Disable Endpoint 15 IN Direction
80330  *  0b0..Enable
80331  *  0b1..Disable
80332  */
80333 #define USB_STALL_IH_DIS_STALL_I_DIS15(x)        (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS15_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS15_MASK)
80334 /*! @} */
80335 
80336 /*! @name STALL_OL_DIS - Peripheral Mode Stall Disable for Endpoints 7 to 0 in OUT Direction */
80337 /*! @{ */
80338 
80339 #define USB_STALL_OL_DIS_STALL_O_DIS0_MASK       (0x1U)
80340 #define USB_STALL_OL_DIS_STALL_O_DIS0_SHIFT      (0U)
80341 /*! STALL_O_DIS0 - Disable Endpoint 0 OUT Direction
80342  *  0b0..Enable
80343  *  0b1..Disable
80344  */
80345 #define USB_STALL_OL_DIS_STALL_O_DIS0(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS0_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS0_MASK)
80346 
80347 #define USB_STALL_OL_DIS_STALL_O_DIS1_MASK       (0x2U)
80348 #define USB_STALL_OL_DIS_STALL_O_DIS1_SHIFT      (1U)
80349 /*! STALL_O_DIS1 - Disable Endpoint 1 OUT Direction
80350  *  0b0..Enable
80351  *  0b1..Disable
80352  */
80353 #define USB_STALL_OL_DIS_STALL_O_DIS1(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS1_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS1_MASK)
80354 
80355 #define USB_STALL_OL_DIS_STALL_O_DIS2_MASK       (0x4U)
80356 #define USB_STALL_OL_DIS_STALL_O_DIS2_SHIFT      (2U)
80357 /*! STALL_O_DIS2 - Disable Endpoint 2 OUT Direction
80358  *  0b0..Enable
80359  *  0b1..Disable
80360  */
80361 #define USB_STALL_OL_DIS_STALL_O_DIS2(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS2_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS2_MASK)
80362 
80363 #define USB_STALL_OL_DIS_STALL_O_DIS3_MASK       (0x8U)
80364 #define USB_STALL_OL_DIS_STALL_O_DIS3_SHIFT      (3U)
80365 /*! STALL_O_DIS3 - Disable Endpoint 3 OUT Direction
80366  *  0b0..Enable
80367  *  0b1..Disable
80368  */
80369 #define USB_STALL_OL_DIS_STALL_O_DIS3(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS3_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS3_MASK)
80370 
80371 #define USB_STALL_OL_DIS_STALL_O_DIS4_MASK       (0x10U)
80372 #define USB_STALL_OL_DIS_STALL_O_DIS4_SHIFT      (4U)
80373 /*! STALL_O_DIS4 - Disable Endpoint 4 OUT Direction
80374  *  0b0..Enable
80375  *  0b1..Disable
80376  */
80377 #define USB_STALL_OL_DIS_STALL_O_DIS4(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS4_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS4_MASK)
80378 
80379 #define USB_STALL_OL_DIS_STALL_O_DIS5_MASK       (0x20U)
80380 #define USB_STALL_OL_DIS_STALL_O_DIS5_SHIFT      (5U)
80381 /*! STALL_O_DIS5 - Disable Endpoint 5 OUT Direction
80382  *  0b0..Enable
80383  *  0b1..Disable
80384  */
80385 #define USB_STALL_OL_DIS_STALL_O_DIS5(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS5_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS5_MASK)
80386 
80387 #define USB_STALL_OL_DIS_STALL_O_DIS6_MASK       (0x40U)
80388 #define USB_STALL_OL_DIS_STALL_O_DIS6_SHIFT      (6U)
80389 /*! STALL_O_DIS6 - Disable Endpoint 6 OUT Direction
80390  *  0b0..Enable
80391  *  0b1..Disable
80392  */
80393 #define USB_STALL_OL_DIS_STALL_O_DIS6(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS6_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS6_MASK)
80394 
80395 #define USB_STALL_OL_DIS_STALL_O_DIS7_MASK       (0x80U)
80396 #define USB_STALL_OL_DIS_STALL_O_DIS7_SHIFT      (7U)
80397 /*! STALL_O_DIS7 - Disable Endpoint 7 OUT Direction
80398  *  0b0..Enable
80399  *  0b1..Disable
80400  */
80401 #define USB_STALL_OL_DIS_STALL_O_DIS7(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS7_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS7_MASK)
80402 /*! @} */
80403 
80404 /*! @name STALL_OH_DIS - Peripheral Mode Stall Disable for Endpoints 15 to 8 in OUT Direction */
80405 /*! @{ */
80406 
80407 #define USB_STALL_OH_DIS_STALL_O_DIS8_MASK       (0x1U)
80408 #define USB_STALL_OH_DIS_STALL_O_DIS8_SHIFT      (0U)
80409 /*! STALL_O_DIS8 - Disable Endpoint 8 OUT Direction
80410  *  0b0..Enable
80411  *  0b1..Disable
80412  */
80413 #define USB_STALL_OH_DIS_STALL_O_DIS8(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS8_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS8_MASK)
80414 
80415 #define USB_STALL_OH_DIS_STALL_O_DIS9_MASK       (0x2U)
80416 #define USB_STALL_OH_DIS_STALL_O_DIS9_SHIFT      (1U)
80417 /*! STALL_O_DIS9 - Disable Endpoint 9 OUT Direction
80418  *  0b0..Enable
80419  *  0b1..Disable
80420  */
80421 #define USB_STALL_OH_DIS_STALL_O_DIS9(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS9_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS9_MASK)
80422 
80423 #define USB_STALL_OH_DIS_STALL_O_DIS10_MASK      (0x4U)
80424 #define USB_STALL_OH_DIS_STALL_O_DIS10_SHIFT     (2U)
80425 /*! STALL_O_DIS10 - Disable Endpoint 10 OUT Direction
80426  *  0b0..Enable
80427  *  0b1..Disable
80428  */
80429 #define USB_STALL_OH_DIS_STALL_O_DIS10(x)        (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS10_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS10_MASK)
80430 
80431 #define USB_STALL_OH_DIS_STALL_O_DIS11_MASK      (0x8U)
80432 #define USB_STALL_OH_DIS_STALL_O_DIS11_SHIFT     (3U)
80433 /*! STALL_O_DIS11 - Disable Endpoint 11 OUT Direction
80434  *  0b0..Enable
80435  *  0b1..Disable
80436  */
80437 #define USB_STALL_OH_DIS_STALL_O_DIS11(x)        (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS11_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS11_MASK)
80438 
80439 #define USB_STALL_OH_DIS_STALL_O_DIS12_MASK      (0x10U)
80440 #define USB_STALL_OH_DIS_STALL_O_DIS12_SHIFT     (4U)
80441 /*! STALL_O_DIS12 - Disable endpoint 12 OUT direction
80442  *  0b0..Enable
80443  *  0b1..Disable
80444  */
80445 #define USB_STALL_OH_DIS_STALL_O_DIS12(x)        (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS12_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS12_MASK)
80446 
80447 #define USB_STALL_OH_DIS_STALL_O_DIS13_MASK      (0x20U)
80448 #define USB_STALL_OH_DIS_STALL_O_DIS13_SHIFT     (5U)
80449 /*! STALL_O_DIS13 - Disable Endpoint 13 OUT Direction
80450  *  0b0..Enable
80451  *  0b1..Disable
80452  */
80453 #define USB_STALL_OH_DIS_STALL_O_DIS13(x)        (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS13_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS13_MASK)
80454 
80455 #define USB_STALL_OH_DIS_STALL_O_DIS14_MASK      (0x40U)
80456 #define USB_STALL_OH_DIS_STALL_O_DIS14_SHIFT     (6U)
80457 /*! STALL_O_DIS14 - Disable Endpoint 14 OUT Direction
80458  *  0b0..Enable
80459  *  0b1..Disable
80460  */
80461 #define USB_STALL_OH_DIS_STALL_O_DIS14(x)        (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS14_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS14_MASK)
80462 
80463 #define USB_STALL_OH_DIS_STALL_O_DIS15_MASK      (0x80U)
80464 #define USB_STALL_OH_DIS_STALL_O_DIS15_SHIFT     (7U)
80465 /*! STALL_O_DIS15 - Disable Endpoint 15 OUT Direction
80466  *  0b0..Enable
80467  *  0b1..Disable
80468  */
80469 #define USB_STALL_OH_DIS_STALL_O_DIS15(x)        (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS15_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS15_MASK)
80470 /*! @} */
80471 
80472 /*! @name CLK_RECOVER_CTRL - USB Clock Recovery Control */
80473 /*! @{ */
80474 
80475 #define USB_CLK_RECOVER_CTRL_TRIM_INIT_VAL_SEL_MASK (0x8U)
80476 #define USB_CLK_RECOVER_CTRL_TRIM_INIT_VAL_SEL_SHIFT (3U)
80477 /*! TRIM_INIT_VAL_SEL - Selects the source for the initial FIRC trim fine value used after a reset.
80478  *  0b0..Mid-scale
80479  *  0b1..IFR
80480  */
80481 #define USB_CLK_RECOVER_CTRL_TRIM_INIT_VAL_SEL(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_TRIM_INIT_VAL_SEL_SHIFT)) & USB_CLK_RECOVER_CTRL_TRIM_INIT_VAL_SEL_MASK)
80482 
80483 #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK (0x20U)
80484 #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT (5U)
80485 /*! RESTART_IFRTRIM_EN - Restart from IFR Trim Value
80486  *  0b0..Trim fine adjustment always works based on the previous updated trim fine value.
80487  *  0b1..Trim fine restarts from the IFR trim value whenever you detect bus_reset or bus_resume or deassert module enable.
80488  */
80489 #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK)
80490 
80491 #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK (0x40U)
80492 #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT (6U)
80493 /*! RESET_RESUME_ROUGH_EN - Reset or Resume to Rough Phase Enable
80494  *  0b0..Always works in tracking phase after the first time rough phase, to track transition.
80495  *  0b1..Go back to rough stage whenever a bus reset or bus resume occurs.
80496  */
80497 #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK)
80498 
80499 #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK (0x80U)
80500 #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT (7U)
80501 /*! CLOCK_RECOVER_EN - Crystal-Less USB Enable
80502  *  0b0..Disable
80503  *  0b1..Enable
80504  */
80505 #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK)
80506 /*! @} */
80507 
80508 /*! @name CLK_RECOVER_IRC_EN - FIRC Oscillator Enable */
80509 /*! @{ */
80510 
80511 #define USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK       (0x2U)
80512 #define USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT      (1U)
80513 /*! IRC_EN - Fast IRC enable
80514  *  0b0..Disable
80515  *  0b1..Enable
80516  */
80517 #define USB_CLK_RECOVER_IRC_EN_IRC_EN(x)         (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT)) & USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK)
80518 /*! @} */
80519 
80520 /*! @name CLK_RECOVER_INT_EN - Clock Recovery Combined Interrupt Enable */
80521 /*! @{ */
80522 
80523 #define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK (0x10U)
80524 #define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT (4U)
80525 /*! OVF_ERROR_EN - Overflow error interrupt enable
80526  *  0b0..The interrupt is masked
80527  *  0b1..The interrupt is enabled
80528  */
80529 #define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN(x)   (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT)) & USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK)
80530 /*! @} */
80531 
80532 /*! @name CLK_RECOVER_INT_STATUS - Clock Recovery Separated Interrupt Status */
80533 /*! @{ */
80534 
80535 #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK (0x10U)
80536 #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT (4U)
80537 /*! OVF_ERROR - Overflow Error Interrupt Status Flag
80538  *  0b0..Interrupt did not occur
80539  *  0b1..Unmasked interrupt occurred
80540  *  0b0..No effect
80541  *  0b1..Clear the flag
80542  */
80543 #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(x)  (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT)) & USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK)
80544 /*! @} */
80545 
80546 
80547 /*!
80548  * @}
80549  */ /* end of group USB_Register_Masks */
80550 
80551 
80552 /* USB - Peripheral instance base addresses */
80553 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
80554   /** Peripheral USBFS0 base address */
80555   #define USBFS0_BASE                              (0x500DD000u)
80556   /** Peripheral USBFS0 base address */
80557   #define USBFS0_BASE_NS                           (0x400DD000u)
80558   /** Peripheral USBFS0 base pointer */
80559   #define USBFS0                                   ((USB_Type *)USBFS0_BASE)
80560   /** Peripheral USBFS0 base pointer */
80561   #define USBFS0_NS                                ((USB_Type *)USBFS0_BASE_NS)
80562   /** Array initializer of USB peripheral base addresses */
80563   #define USB_BASE_ADDRS                           { USBFS0_BASE }
80564   /** Array initializer of USB peripheral base pointers */
80565   #define USB_BASE_PTRS                            { USBFS0 }
80566   /** Array initializer of USB peripheral base addresses */
80567   #define USB_BASE_ADDRS_NS                        { USBFS0_BASE_NS }
80568   /** Array initializer of USB peripheral base pointers */
80569   #define USB_BASE_PTRS_NS                         { USBFS0_NS }
80570 #else
80571   /** Peripheral USBFS0 base address */
80572   #define USBFS0_BASE                              (0x400DD000u)
80573   /** Peripheral USBFS0 base pointer */
80574   #define USBFS0                                   ((USB_Type *)USBFS0_BASE)
80575   /** Array initializer of USB peripheral base addresses */
80576   #define USB_BASE_ADDRS                           { USBFS0_BASE }
80577   /** Array initializer of USB peripheral base pointers */
80578   #define USB_BASE_PTRS                            { USBFS0 }
80579 #endif
80580 /** Interrupt vectors for the USB peripheral type */
80581 #define USB_IRQS                                 { USB0_FS_IRQn }
80582 /* Backward compatibility */
80583 #define USBFS_IRQS                               USB_IRQS
80584 #define USBFS_IRQHandler                         USB0_FS_IRQHandler
80585 
80586 
80587 /*!
80588  * @}
80589  */ /* end of group USB_Peripheral_Access_Layer */
80590 
80591 
80592 /* ----------------------------------------------------------------------------
80593    -- USBDCD Peripheral Access Layer
80594    ---------------------------------------------------------------------------- */
80595 
80596 /*!
80597  * @addtogroup USBDCD_Peripheral_Access_Layer USBDCD Peripheral Access Layer
80598  * @{
80599  */
80600 
80601 /** USBDCD - Register Layout Typedef */
80602 typedef struct {
80603   __IO uint32_t CONTROL;                           /**< Control, offset: 0x0 */
80604   __IO uint32_t CLOCK;                             /**< Clock, offset: 0x4 */
80605   __I  uint32_t STATUS;                            /**< Status, offset: 0x8 */
80606   __IO uint32_t SIGNAL_OVERRIDE;                   /**< Signal Override, offset: 0xC */
80607   __IO uint32_t TIMER0;                            /**< TIMER0, offset: 0x10 */
80608   __IO uint32_t TIMER1;                            /**< TIMER1, offset: 0x14 */
80609   union {                                          /* offset: 0x18 */
80610     __IO uint32_t TIMER2_BC11;                       /**< TIMER2_BC11, offset: 0x18 */
80611     __IO uint32_t TIMER2_BC12;                       /**< TIMER2_BC12, offset: 0x18 */
80612   };
80613 } USBDCD_Type;
80614 
80615 /* ----------------------------------------------------------------------------
80616    -- USBDCD Register Masks
80617    ---------------------------------------------------------------------------- */
80618 
80619 /*!
80620  * @addtogroup USBDCD_Register_Masks USBDCD Register Masks
80621  * @{
80622  */
80623 
80624 /*! @name CONTROL - Control */
80625 /*! @{ */
80626 
80627 #define USBDCD_CONTROL_IACK_MASK                 (0x1U)
80628 #define USBDCD_CONTROL_IACK_SHIFT                (0U)
80629 /*! IACK - Interrupt Acknowledge
80630  *  0b0..Do not clear the interrupt.
80631  *  0b1..Clear the IF field (interrupt flag).
80632  */
80633 #define USBDCD_CONTROL_IACK(x)                   (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IACK_SHIFT)) & USBDCD_CONTROL_IACK_MASK)
80634 
80635 #define USBDCD_CONTROL_IF_MASK                   (0x100U)
80636 #define USBDCD_CONTROL_IF_SHIFT                  (8U)
80637 /*! IF - Interrupt Flag
80638  *  0b0..No interrupt is pending.
80639  *  0b1..An interrupt is pending.
80640  */
80641 #define USBDCD_CONTROL_IF(x)                     (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IF_SHIFT)) & USBDCD_CONTROL_IF_MASK)
80642 
80643 #define USBDCD_CONTROL_IE_MASK                   (0x10000U)
80644 #define USBDCD_CONTROL_IE_SHIFT                  (16U)
80645 /*! IE - Interrupt Enable
80646  *  0b0..Disable interrupts to the system.
80647  *  0b1..Enable interrupts to the system.
80648  */
80649 #define USBDCD_CONTROL_IE(x)                     (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IE_SHIFT)) & USBDCD_CONTROL_IE_MASK)
80650 
80651 #define USBDCD_CONTROL_BC12_MASK                 (0x20000U)
80652 #define USBDCD_CONTROL_BC12_SHIFT                (17U)
80653 /*! BC12 - Battery Charging Revision 1.2 Compatibility
80654  *  0b0..Compatible with BC1.1
80655  *  0b1..Compatible with BC1.2 (default)
80656  */
80657 #define USBDCD_CONTROL_BC12(x)                   (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_BC12_SHIFT)) & USBDCD_CONTROL_BC12_MASK)
80658 
80659 #define USBDCD_CONTROL_START_MASK                (0x1000000U)
80660 #define USBDCD_CONTROL_START_SHIFT               (24U)
80661 /*! START - Start Change Detection Sequence
80662  *  0b0..Do not start the sequence. Writes of this value have no effect.
80663  *  0b1..Initiate the charger detection sequence. If the sequence is already running, writes of this value have no effect.
80664  */
80665 #define USBDCD_CONTROL_START(x)                  (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_START_SHIFT)) & USBDCD_CONTROL_START_MASK)
80666 
80667 #define USBDCD_CONTROL_SR_MASK                   (0x2000000U)
80668 #define USBDCD_CONTROL_SR_SHIFT                  (25U)
80669 /*! SR - Software Reset
80670  *  0b0..Do not perform a software reset.
80671  *  0b1..Perform a software reset.
80672  */
80673 #define USBDCD_CONTROL_SR(x)                     (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_SR_SHIFT)) & USBDCD_CONTROL_SR_MASK)
80674 /*! @} */
80675 
80676 /*! @name CLOCK - Clock */
80677 /*! @{ */
80678 
80679 #define USBDCD_CLOCK_CLOCK_UNIT_MASK             (0x1U)
80680 #define USBDCD_CLOCK_CLOCK_UNIT_SHIFT            (0U)
80681 /*! CLOCK_UNIT - Unit of Measurement Encoding for Clock Speed
80682  *  0b0..kHz Speed (between 4 kHz and 1023 kHz)
80683  *  0b1..MHz Speed (between 1 MHz and 1023 MHz)
80684  */
80685 #define USBDCD_CLOCK_CLOCK_UNIT(x)               (((uint32_t)(((uint32_t)(x)) << USBDCD_CLOCK_CLOCK_UNIT_SHIFT)) & USBDCD_CLOCK_CLOCK_UNIT_MASK)
80686 
80687 #define USBDCD_CLOCK_CLOCK_SPEED_MASK            (0xFFCU)
80688 #define USBDCD_CLOCK_CLOCK_SPEED_SHIFT           (2U)
80689 /*! CLOCK_SPEED - Numerical Value of Clock Speed in Binary */
80690 #define USBDCD_CLOCK_CLOCK_SPEED(x)              (((uint32_t)(((uint32_t)(x)) << USBDCD_CLOCK_CLOCK_SPEED_SHIFT)) & USBDCD_CLOCK_CLOCK_SPEED_MASK)
80691 /*! @} */
80692 
80693 /*! @name STATUS - Status */
80694 /*! @{ */
80695 
80696 #define USBDCD_STATUS_SEQ_RES_MASK               (0x30000U)
80697 #define USBDCD_STATUS_SEQ_RES_SHIFT              (16U)
80698 /*! SEQ_RES - Charger Detection Sequence Results
80699  *  0b00..No results to report.
80700  *  0b01..Attached to an SDP. Must comply with USB 2.0 by drawing only 2.5 mA (max) until connected.
80701  *  0b10..Attached to a charging port. The exact meaning depends on the STATUS[SEQ_STAT] field (value 0: Attached
80702  *        to either a CDP or a DCP. The charger type detection has not completed. value 1: Attached to a CDP. The
80703  *        charger type detection has completed.)
80704  *  0b11..Attached to a DCP.
80705  */
80706 #define USBDCD_STATUS_SEQ_RES(x)                 (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_SEQ_RES_SHIFT)) & USBDCD_STATUS_SEQ_RES_MASK)
80707 
80708 #define USBDCD_STATUS_SEQ_STAT_MASK              (0xC0000U)
80709 #define USBDCD_STATUS_SEQ_STAT_SHIFT             (18U)
80710 /*! SEQ_STAT - Charger Detection Sequence Status
80711  *  0b00..The module is either not enabled, or the module is enabled but the data pins have not yet been detected.
80712  *  0b01..Data pin contact detection is complete.
80713  *  0b10..Charging port detection is complete.
80714  *  0b11..Charger type detection is complete.
80715  */
80716 #define USBDCD_STATUS_SEQ_STAT(x)                (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_SEQ_STAT_SHIFT)) & USBDCD_STATUS_SEQ_STAT_MASK)
80717 
80718 #define USBDCD_STATUS_ERR_MASK                   (0x100000U)
80719 #define USBDCD_STATUS_ERR_SHIFT                  (20U)
80720 /*! ERR - Error Flag
80721  *  0b0..No sequence errors.
80722  *  0b1..Error in the detection sequence.
80723  */
80724 #define USBDCD_STATUS_ERR(x)                     (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_ERR_SHIFT)) & USBDCD_STATUS_ERR_MASK)
80725 
80726 #define USBDCD_STATUS_TO_MASK                    (0x200000U)
80727 #define USBDCD_STATUS_TO_SHIFT                   (21U)
80728 /*! TO - Timeout Flag
80729  *  0b0..The detection sequence is not running for over 1 s.
80730  *  0b1..It is over 1 s since the data pin contact was detected and debounced.
80731  */
80732 #define USBDCD_STATUS_TO(x)                      (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_TO_SHIFT)) & USBDCD_STATUS_TO_MASK)
80733 
80734 #define USBDCD_STATUS_ACTIVE_MASK                (0x400000U)
80735 #define USBDCD_STATUS_ACTIVE_SHIFT               (22U)
80736 /*! ACTIVE - Active Status Indicator
80737  *  0b0..The sequence is not running.
80738  *  0b1..The sequence is running.
80739  */
80740 #define USBDCD_STATUS_ACTIVE(x)                  (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_ACTIVE_SHIFT)) & USBDCD_STATUS_ACTIVE_MASK)
80741 /*! @} */
80742 
80743 /*! @name SIGNAL_OVERRIDE - Signal Override */
80744 /*! @{ */
80745 
80746 #define USBDCD_SIGNAL_OVERRIDE_PS_MASK           (0x7U)
80747 #define USBDCD_SIGNAL_OVERRIDE_PS_SHIFT          (0U)
80748 /*! PS - Phase Selection
80749  *  0b000..No overrides. Field must remain at this value during normal USB data communication to prevent
80750  *         unexpected conditions on USB_DP and USB_DM pins. (Default)
80751  *  0b001..Reserved, not for customer use.
80752  *  0b010..Enables VDP_SRC voltage source for the USB_DP pin and IDM_SINK current source for the USB_DM pin.
80753  *  0b011..Reserved, not for customer use.
80754  *  0b100..Enables VDM_SRC voltage source only.
80755  *  0b101..Reserved, not for customer use.
80756  *  0b110..Reserved, not for customer use.
80757  *  0b111..Reserved, not for customer use.
80758  */
80759 #define USBDCD_SIGNAL_OVERRIDE_PS(x)             (((uint32_t)(((uint32_t)(x)) << USBDCD_SIGNAL_OVERRIDE_PS_SHIFT)) & USBDCD_SIGNAL_OVERRIDE_PS_MASK)
80760 /*! @} */
80761 
80762 /*! @name TIMER0 - TIMER0 */
80763 /*! @{ */
80764 
80765 #define USBDCD_TIMER0_TUNITCON_MASK              (0xFFFU)
80766 #define USBDCD_TIMER0_TUNITCON_SHIFT             (0U)
80767 /*! TUNITCON - Unit Connection Timer Elapse (in ms) */
80768 #define USBDCD_TIMER0_TUNITCON(x)                (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER0_TUNITCON_SHIFT)) & USBDCD_TIMER0_TUNITCON_MASK)
80769 
80770 #define USBDCD_TIMER0_TSEQ_INIT_MASK             (0x3FF0000U)
80771 #define USBDCD_TIMER0_TSEQ_INIT_SHIFT            (16U)
80772 /*! TSEQ_INIT - Sequence Initiation Time
80773  *  0b0000000000-0b1111111111..0 ms - 1023 ms
80774  */
80775 #define USBDCD_TIMER0_TSEQ_INIT(x)               (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER0_TSEQ_INIT_SHIFT)) & USBDCD_TIMER0_TSEQ_INIT_MASK)
80776 /*! @} */
80777 
80778 /*! @name TIMER1 - TIMER1 */
80779 /*! @{ */
80780 
80781 #define USBDCD_TIMER1_TVDPSRC_ON_MASK            (0x3FFU)
80782 #define USBDCD_TIMER1_TVDPSRC_ON_SHIFT           (0U)
80783 /*! TVDPSRC_ON - Time Period Comparator Enabled
80784  *  0b0000000001-0b1111111111..1 ms - 1023 ms
80785  */
80786 #define USBDCD_TIMER1_TVDPSRC_ON(x)              (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER1_TVDPSRC_ON_SHIFT)) & USBDCD_TIMER1_TVDPSRC_ON_MASK)
80787 
80788 #define USBDCD_TIMER1_TDCD_DBNC_MASK             (0x3FF0000U)
80789 #define USBDCD_TIMER1_TDCD_DBNC_SHIFT            (16U)
80790 /*! TDCD_DBNC - Time Period to Debounce D+ Signal
80791  *  0b0000000001-0b1111111111..1 ms - 1023 ms
80792  */
80793 #define USBDCD_TIMER1_TDCD_DBNC(x)               (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER1_TDCD_DBNC_SHIFT)) & USBDCD_TIMER1_TDCD_DBNC_MASK)
80794 /*! @} */
80795 
80796 /*! @name TIMER2_BC11 - TIMER2_BC11 */
80797 /*! @{ */
80798 
80799 #define USBDCD_TIMER2_BC11_CHECK_DM_MASK         (0xFU)
80800 #define USBDCD_TIMER2_BC11_CHECK_DM_SHIFT        (0U)
80801 /*! CHECK_DM - Time Before Check of D- Line
80802  *  0b0001-0b1111..1 ms - 15 ms
80803  */
80804 #define USBDCD_TIMER2_BC11_CHECK_DM(x)           (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC11_CHECK_DM_SHIFT)) & USBDCD_TIMER2_BC11_CHECK_DM_MASK)
80805 
80806 #define USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK      (0x3FF0000U)
80807 #define USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT     (16U)
80808 /*! TVDPSRC_CON - Time Period Before Enabling D+ Pullup
80809  *  0b0000000001-0b1111111111..1 ms - 1023 ms
80810  */
80811 #define USBDCD_TIMER2_BC11_TVDPSRC_CON(x)        (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT)) & USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK)
80812 /*! @} */
80813 
80814 /*! @name TIMER2_BC12 - TIMER2_BC12 */
80815 /*! @{ */
80816 
80817 #define USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK       (0x3FFU)
80818 #define USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT      (0U)
80819 /*! TVDMSRC_ON - TVDMSRC_ON
80820  *  0b0000000000-0b0000101000..0 ms - 40 ms
80821  */
80822 #define USBDCD_TIMER2_BC12_TVDMSRC_ON(x)         (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT)) & USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK)
80823 
80824 #define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK  (0x3FF0000U)
80825 #define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT (16U)
80826 /*! TWAIT_AFTER_PRD - TWAIT_AFTER_PRD
80827  *  0b0000000001-0b1111111111..1 ms - 1023 ms
80828  */
80829 #define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x)    (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT)) & USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK)
80830 /*! @} */
80831 
80832 
80833 /*!
80834  * @}
80835  */ /* end of group USBDCD_Register_Masks */
80836 
80837 
80838 /* USBDCD - Peripheral instance base addresses */
80839 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
80840   /** Peripheral USBDCD0 base address */
80841   #define USBDCD0_BASE                             (0x500DC000u)
80842   /** Peripheral USBDCD0 base address */
80843   #define USBDCD0_BASE_NS                          (0x400DC000u)
80844   /** Peripheral USBDCD0 base pointer */
80845   #define USBDCD0                                  ((USBDCD_Type *)USBDCD0_BASE)
80846   /** Peripheral USBDCD0 base pointer */
80847   #define USBDCD0_NS                               ((USBDCD_Type *)USBDCD0_BASE_NS)
80848   /** Array initializer of USBDCD peripheral base addresses */
80849   #define USBDCD_BASE_ADDRS                        { USBDCD0_BASE }
80850   /** Array initializer of USBDCD peripheral base pointers */
80851   #define USBDCD_BASE_PTRS                         { USBDCD0 }
80852   /** Array initializer of USBDCD peripheral base addresses */
80853   #define USBDCD_BASE_ADDRS_NS                     { USBDCD0_BASE_NS }
80854   /** Array initializer of USBDCD peripheral base pointers */
80855   #define USBDCD_BASE_PTRS_NS                      { USBDCD0_NS }
80856 #else
80857   /** Peripheral USBDCD0 base address */
80858   #define USBDCD0_BASE                             (0x400DC000u)
80859   /** Peripheral USBDCD0 base pointer */
80860   #define USBDCD0                                  ((USBDCD_Type *)USBDCD0_BASE)
80861   /** Array initializer of USBDCD peripheral base addresses */
80862   #define USBDCD_BASE_ADDRS                        { USBDCD0_BASE }
80863   /** Array initializer of USBDCD peripheral base pointers */
80864   #define USBDCD_BASE_PTRS                         { USBDCD0 }
80865 #endif
80866 /** Interrupt vectors for the USBDCD peripheral type */
80867 #define USBDCD_IRQS                              { USB0_DCD_IRQn }
80868 
80869 /*!
80870  * @}
80871  */ /* end of group USBDCD_Peripheral_Access_Layer */
80872 
80873 
80874 /* ----------------------------------------------------------------------------
80875    -- USBHS Peripheral Access Layer
80876    ---------------------------------------------------------------------------- */
80877 
80878 /*!
80879  * @addtogroup USBHS_Peripheral_Access_Layer USBHS Peripheral Access Layer
80880  * @{
80881  */
80882 
80883 /** USBHS - Register Layout Typedef */
80884 typedef struct {
80885   __I  uint32_t ID;                                /**< Identification, offset: 0x0 */
80886   __I  uint32_t HWGENERAL;                         /**< Hardware General, offset: 0x4 */
80887   __I  uint32_t HWHOST;                            /**< Host Hardware Parameters, offset: 0x8 */
80888   __I  uint32_t HWDEVICE;                          /**< Device Hardware Parameters, offset: 0xC */
80889   __I  uint32_t HWTXBUF;                           /**< TX Buffer Hardware Parameters, offset: 0x10 */
80890   __I  uint32_t HWRXBUF;                           /**< RX Buffer Hardware Parameters, offset: 0x14 */
80891        uint8_t RESERVED_0[104];
80892   __IO uint32_t GPTIMER0LD;                        /**< General Purpose Timer #0 Load, offset: 0x80 */
80893   __IO uint32_t GPTIMER0CTRL;                      /**< General Purpose Timer #0 Controller, offset: 0x84 */
80894   __IO uint32_t GPTIMER1LD;                        /**< General Purpose Timer #1 Load, offset: 0x88 */
80895   __IO uint32_t GPTIMER1CTRL;                      /**< General Purpose Timer #1 Controller, offset: 0x8C */
80896   __IO uint32_t SBUSCFG;                           /**< System Bus Config, offset: 0x90 */
80897        uint8_t RESERVED_1[108];
80898   __I  uint8_t CAPLENGTH;                          /**< Capability Registers Length, offset: 0x100 */
80899        uint8_t RESERVED_2[1];
80900   __I  uint16_t HCIVERSION;                        /**< Host Controller Interface Version, offset: 0x102 */
80901   __I  uint32_t HCSPARAMS;                         /**< Host Controller Structural Parameters, offset: 0x104 */
80902   __I  uint32_t HCCPARAMS;                         /**< Host Controller Capability Parameters, offset: 0x108 */
80903        uint8_t RESERVED_3[20];
80904   __I  uint16_t DCIVERSION;                        /**< Device Controller Interface Version, offset: 0x120 */
80905        uint8_t RESERVED_4[2];
80906   __I  uint32_t DCCPARAMS;                         /**< Device Controller Capability Parameters, offset: 0x124 */
80907        uint8_t RESERVED_5[24];
80908   __IO uint32_t USBCMD;                            /**< USB Command, offset: 0x140 */
80909   __IO uint32_t USBSTS;                            /**< USB Status, offset: 0x144 */
80910   __IO uint32_t USBINTR;                           /**< Interrupt Enable, offset: 0x148 */
80911   __IO uint32_t FRINDEX;                           /**< USB Frame Index, offset: 0x14C */
80912        uint8_t RESERVED_6[4];
80913   union {                                          /* offset: 0x154 */
80914     __IO uint32_t DEVICEADDR;                        /**< Device Address, offset: 0x154 */
80915     __IO uint32_t PERIODICLISTBASE;                  /**< Frame List Base Address, offset: 0x154 */
80916   };
80917   union {                                          /* offset: 0x158 */
80918     __IO uint32_t ASYNCLISTADDR;                     /**< Next Asynch. Address, offset: 0x158 */
80919     __IO uint32_t ENDPTLISTADDR;                     /**< Endpoint List Address, offset: 0x158 */
80920   };
80921        uint8_t RESERVED_7[4];
80922   __IO uint32_t BURSTSIZE;                         /**< Programmable Burst Size, offset: 0x160 */
80923   __IO uint32_t TXFILLTUNING;                      /**< TX FIFO Fill Tuning, offset: 0x164 */
80924        uint8_t RESERVED_8[16];
80925   __IO uint32_t ENDPTNAK;                          /**< Endpoint NAK, offset: 0x178 */
80926   __IO uint32_t ENDPTNAKEN;                        /**< Endpoint NAK Enable, offset: 0x17C */
80927   __I  uint32_t CONFIGFLAG;                        /**< Configure Flag, offset: 0x180 */
80928   __IO uint32_t PORTSC1;                           /**< Port Status & Control, offset: 0x184 */
80929        uint8_t RESERVED_9[28];
80930   __IO uint32_t OTGSC;                             /**< On-The-Go Status & Control, offset: 0x1A4 */
80931   __IO uint32_t USBMODE;                           /**< USB Device Mode, offset: 0x1A8 */
80932   __IO uint32_t ENDPTSETUPSTAT;                    /**< Endpoint Setup Status, offset: 0x1AC */
80933   __IO uint32_t ENDPTPRIME;                        /**< Endpoint Prime, offset: 0x1B0 */
80934   __IO uint32_t ENDPTFLUSH;                        /**< Endpoint Flush, offset: 0x1B4 */
80935   __I  uint32_t ENDPTSTAT;                         /**< Endpoint Status, offset: 0x1B8 */
80936   __IO uint32_t ENDPTCOMPLETE;                     /**< Endpoint Complete, offset: 0x1BC */
80937   __IO uint32_t ENDPTCTRL0;                        /**< Endpoint Control 0, offset: 0x1C0 */
80938   __IO uint32_t ENDPTCTRL[7];                      /**< Endpoint Control 1..Endpoint Control 7, array offset: 0x1C4, array step: 0x4 */
80939 } USBHS_Type;
80940 
80941 /* ----------------------------------------------------------------------------
80942    -- USBHS Register Masks
80943    ---------------------------------------------------------------------------- */
80944 
80945 /*!
80946  * @addtogroup USBHS_Register_Masks USBHS Register Masks
80947  * @{
80948  */
80949 
80950 /*! @name ID - Identification */
80951 /*! @{ */
80952 
80953 #define USBHS_ID_ID_MASK                         (0x3FU)
80954 #define USBHS_ID_ID_SHIFT                        (0U)
80955 /*! ID - Configuration Number */
80956 #define USBHS_ID_ID(x)                           (((uint32_t)(((uint32_t)(x)) << USBHS_ID_ID_SHIFT)) & USBHS_ID_ID_MASK)
80957 
80958 #define USBHS_ID_NID_MASK                        (0x3F00U)
80959 #define USBHS_ID_NID_SHIFT                       (8U)
80960 /*! NID - Complement Version of ID */
80961 #define USBHS_ID_NID(x)                          (((uint32_t)(((uint32_t)(x)) << USBHS_ID_NID_SHIFT)) & USBHS_ID_NID_MASK)
80962 
80963 #define USBHS_ID_REVISION_MASK                   (0xFF0000U)
80964 #define USBHS_ID_REVISION_SHIFT                  (16U)
80965 /*! REVISION - Revision Number of the Controller Core */
80966 #define USBHS_ID_REVISION(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_ID_REVISION_SHIFT)) & USBHS_ID_REVISION_MASK)
80967 /*! @} */
80968 
80969 /*! @name HWGENERAL - Hardware General */
80970 /*! @{ */
80971 
80972 #define USBHS_HWGENERAL_PHYW_MASK                (0x30U)
80973 #define USBHS_HWGENERAL_PHYW_SHIFT               (4U)
80974 /*! PHYW - Data width of the transceiver connected to the controller core
80975  *  0b00..8 bit wide data bus (Software non-programmable)
80976  *  0b01..16 bit wide data bus (Software non-programmable)
80977  *  0b10..Reset to 8 bit wide data bus (Software programmable)
80978  *  0b11..Reset to 16 bit wide data bus (Software programmable)
80979  */
80980 #define USBHS_HWGENERAL_PHYW(x)                  (((uint32_t)(((uint32_t)(x)) << USBHS_HWGENERAL_PHYW_SHIFT)) & USBHS_HWGENERAL_PHYW_MASK)
80981 
80982 #define USBHS_HWGENERAL_PHYM_MASK                (0x1C0U)
80983 #define USBHS_HWGENERAL_PHYM_SHIFT               (6U)
80984 /*! PHYM - Transceiver Type
80985  *  0b000..UTMI/UMTI+
80986  *  0b001..ULPI DDR
80987  *  0b010..ULPI
80988  *  0b011..Serial Only
80989  *  0b100..Software programmable - reset to UTMI/UTMI+
80990  *  0b101..Software programmable - reset to ULPI DDR
80991  *  0b110..Software programmable - reset to ULPI
80992  *  0b111..Software programmable - reset to Serial
80993  */
80994 #define USBHS_HWGENERAL_PHYM(x)                  (((uint32_t)(((uint32_t)(x)) << USBHS_HWGENERAL_PHYM_SHIFT)) & USBHS_HWGENERAL_PHYM_MASK)
80995 
80996 #define USBHS_HWGENERAL_SM_MASK                  (0x600U)
80997 #define USBHS_HWGENERAL_SM_SHIFT                 (9U)
80998 /*! SM - Serial interface mode capability
80999  *  0b00..No Serial Engine, always use parallel signalling
81000  *  0b01..Serial Engine present, always use serial signalling for FS/LS
81001  *  0b10..Software programmable - Reset to use parallel signalling for FS/LS
81002  *  0b11..Software programmable - Reset to use serial signalling for FS/LS
81003  */
81004 #define USBHS_HWGENERAL_SM(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_HWGENERAL_SM_SHIFT)) & USBHS_HWGENERAL_SM_MASK)
81005 /*! @} */
81006 
81007 /*! @name HWHOST - Host Hardware Parameters */
81008 /*! @{ */
81009 
81010 #define USBHS_HWHOST_HC_MASK                     (0x1U)
81011 #define USBHS_HWHOST_HC_SHIFT                    (0U)
81012 /*! HC - Host Capable
81013  *  0b1..Supported
81014  *  0b0..Not supported
81015  */
81016 #define USBHS_HWHOST_HC(x)                       (((uint32_t)(((uint32_t)(x)) << USBHS_HWHOST_HC_SHIFT)) & USBHS_HWHOST_HC_MASK)
81017 
81018 #define USBHS_HWHOST_NPORT_MASK                  (0xEU)
81019 #define USBHS_HWHOST_NPORT_SHIFT                 (1U)
81020 /*! NPORT - The Number of downstream ports supported by the host controller is (NPORT+1) */
81021 #define USBHS_HWHOST_NPORT(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_HWHOST_NPORT_SHIFT)) & USBHS_HWHOST_NPORT_MASK)
81022 /*! @} */
81023 
81024 /*! @name HWDEVICE - Device Hardware Parameters */
81025 /*! @{ */
81026 
81027 #define USBHS_HWDEVICE_DC_MASK                   (0x1U)
81028 #define USBHS_HWDEVICE_DC_SHIFT                  (0U)
81029 /*! DC - Device Capable
81030  *  0b1..Supported
81031  *  0b0..Not supported
81032  */
81033 #define USBHS_HWDEVICE_DC(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_HWDEVICE_DC_SHIFT)) & USBHS_HWDEVICE_DC_MASK)
81034 
81035 #define USBHS_HWDEVICE_DEVEP_MASK                (0x3EU)
81036 #define USBHS_HWDEVICE_DEVEP_SHIFT               (1U)
81037 /*! DEVEP - Device Endpoint Number */
81038 #define USBHS_HWDEVICE_DEVEP(x)                  (((uint32_t)(((uint32_t)(x)) << USBHS_HWDEVICE_DEVEP_SHIFT)) & USBHS_HWDEVICE_DEVEP_MASK)
81039 /*! @} */
81040 
81041 /*! @name HWTXBUF - TX Buffer Hardware Parameters */
81042 /*! @{ */
81043 
81044 #define USBHS_HWTXBUF_TXBURST_MASK               (0xFFU)
81045 #define USBHS_HWTXBUF_TXBURST_SHIFT              (0U)
81046 /*! TXBURST - Default burst size for memory to TX buffer transfer */
81047 #define USBHS_HWTXBUF_TXBURST(x)                 (((uint32_t)(((uint32_t)(x)) << USBHS_HWTXBUF_TXBURST_SHIFT)) & USBHS_HWTXBUF_TXBURST_MASK)
81048 
81049 #define USBHS_HWTXBUF_TXCHANADD_MASK             (0xFF0000U)
81050 #define USBHS_HWTXBUF_TXCHANADD_SHIFT            (16U)
81051 /*! TXCHANADD - TX FIFO Buffer size is: (2^TXCHANADD) * 4 Bytes */
81052 #define USBHS_HWTXBUF_TXCHANADD(x)               (((uint32_t)(((uint32_t)(x)) << USBHS_HWTXBUF_TXCHANADD_SHIFT)) & USBHS_HWTXBUF_TXCHANADD_MASK)
81053 /*! @} */
81054 
81055 /*! @name HWRXBUF - RX Buffer Hardware Parameters */
81056 /*! @{ */
81057 
81058 #define USBHS_HWRXBUF_RXBURST_MASK               (0xFFU)
81059 #define USBHS_HWRXBUF_RXBURST_SHIFT              (0U)
81060 /*! RXBURST - Default burst size for memory to RX buffer transfer */
81061 #define USBHS_HWRXBUF_RXBURST(x)                 (((uint32_t)(((uint32_t)(x)) << USBHS_HWRXBUF_RXBURST_SHIFT)) & USBHS_HWRXBUF_RXBURST_MASK)
81062 
81063 #define USBHS_HWRXBUF_RXADD_MASK                 (0xFF00U)
81064 #define USBHS_HWRXBUF_RXADD_SHIFT                (8U)
81065 /*! RXADD - Buffer total size for all receive endpoints is (2^RXADD) */
81066 #define USBHS_HWRXBUF_RXADD(x)                   (((uint32_t)(((uint32_t)(x)) << USBHS_HWRXBUF_RXADD_SHIFT)) & USBHS_HWRXBUF_RXADD_MASK)
81067 /*! @} */
81068 
81069 /*! @name GPTIMER0LD - General Purpose Timer #0 Load */
81070 /*! @{ */
81071 
81072 #define USBHS_GPTIMER0LD_GPTLD_MASK              (0xFFFFFFU)
81073 #define USBHS_GPTIMER0LD_GPTLD_SHIFT             (0U)
81074 /*! GPTLD - General Purpose Timer Load Value */
81075 #define USBHS_GPTIMER0LD_GPTLD(x)                (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER0LD_GPTLD_SHIFT)) & USBHS_GPTIMER0LD_GPTLD_MASK)
81076 /*! @} */
81077 
81078 /*! @name GPTIMER0CTRL - General Purpose Timer #0 Controller */
81079 /*! @{ */
81080 
81081 #define USBHS_GPTIMER0CTRL_GPTCNT_MASK           (0xFFFFFFU)
81082 #define USBHS_GPTIMER0CTRL_GPTCNT_SHIFT          (0U)
81083 /*! GPTCNT - General Purpose Timer Counter */
81084 #define USBHS_GPTIMER0CTRL_GPTCNT(x)             (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER0CTRL_GPTCNT_SHIFT)) & USBHS_GPTIMER0CTRL_GPTCNT_MASK)
81085 
81086 #define USBHS_GPTIMER0CTRL_GPTMODE_MASK          (0x1000000U)
81087 #define USBHS_GPTIMER0CTRL_GPTMODE_SHIFT         (24U)
81088 /*! GPTMODE - General Purpose Timer Mode
81089  *  0b0..One Shot Mode
81090  *  0b1..Repeat Mode
81091  */
81092 #define USBHS_GPTIMER0CTRL_GPTMODE(x)            (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER0CTRL_GPTMODE_SHIFT)) & USBHS_GPTIMER0CTRL_GPTMODE_MASK)
81093 
81094 #define USBHS_GPTIMER0CTRL_GPTRST_MASK           (0x40000000U)
81095 #define USBHS_GPTIMER0CTRL_GPTRST_SHIFT          (30U)
81096 /*! GPTRST - General Purpose Timer Reset
81097  *  0b0..No action
81098  *  0b1..Load counter value from GPTLD bits in n_GPTIMER0LD
81099  */
81100 #define USBHS_GPTIMER0CTRL_GPTRST(x)             (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER0CTRL_GPTRST_SHIFT)) & USBHS_GPTIMER0CTRL_GPTRST_MASK)
81101 
81102 #define USBHS_GPTIMER0CTRL_GPTRUN_MASK           (0x80000000U)
81103 #define USBHS_GPTIMER0CTRL_GPTRUN_SHIFT          (31U)
81104 /*! GPTRUN - General Purpose Timer Run
81105  *  0b0..Stop counting
81106  *  0b1..Run
81107  */
81108 #define USBHS_GPTIMER0CTRL_GPTRUN(x)             (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER0CTRL_GPTRUN_SHIFT)) & USBHS_GPTIMER0CTRL_GPTRUN_MASK)
81109 /*! @} */
81110 
81111 /*! @name GPTIMER1LD - General Purpose Timer #1 Load */
81112 /*! @{ */
81113 
81114 #define USBHS_GPTIMER1LD_GPTLD_MASK              (0xFFFFFFU)
81115 #define USBHS_GPTIMER1LD_GPTLD_SHIFT             (0U)
81116 /*! GPTLD - General Purpose Timer Load Value */
81117 #define USBHS_GPTIMER1LD_GPTLD(x)                (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER1LD_GPTLD_SHIFT)) & USBHS_GPTIMER1LD_GPTLD_MASK)
81118 /*! @} */
81119 
81120 /*! @name GPTIMER1CTRL - General Purpose Timer #1 Controller */
81121 /*! @{ */
81122 
81123 #define USBHS_GPTIMER1CTRL_GPTCNT_MASK           (0xFFFFFFU)
81124 #define USBHS_GPTIMER1CTRL_GPTCNT_SHIFT          (0U)
81125 /*! GPTCNT - General Purpose Timer Counter */
81126 #define USBHS_GPTIMER1CTRL_GPTCNT(x)             (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER1CTRL_GPTCNT_SHIFT)) & USBHS_GPTIMER1CTRL_GPTCNT_MASK)
81127 
81128 #define USBHS_GPTIMER1CTRL_GPTMODE_MASK          (0x1000000U)
81129 #define USBHS_GPTIMER1CTRL_GPTMODE_SHIFT         (24U)
81130 /*! GPTMODE - General Purpose Timer Mode
81131  *  0b0..One Shot Mode
81132  *  0b1..Repeat Mode
81133  */
81134 #define USBHS_GPTIMER1CTRL_GPTMODE(x)            (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER1CTRL_GPTMODE_SHIFT)) & USBHS_GPTIMER1CTRL_GPTMODE_MASK)
81135 
81136 #define USBHS_GPTIMER1CTRL_GPTRST_MASK           (0x40000000U)
81137 #define USBHS_GPTIMER1CTRL_GPTRST_SHIFT          (30U)
81138 /*! GPTRST - General Purpose Timer Reset
81139  *  0b0..No action
81140  *  0b1..Load counter value from GPTLD bits in USB_n_GPTIMER0LD
81141  */
81142 #define USBHS_GPTIMER1CTRL_GPTRST(x)             (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER1CTRL_GPTRST_SHIFT)) & USBHS_GPTIMER1CTRL_GPTRST_MASK)
81143 
81144 #define USBHS_GPTIMER1CTRL_GPTRUN_MASK           (0x80000000U)
81145 #define USBHS_GPTIMER1CTRL_GPTRUN_SHIFT          (31U)
81146 /*! GPTRUN - General Purpose Timer Run
81147  *  0b0..Stop counting
81148  *  0b1..Run
81149  */
81150 #define USBHS_GPTIMER1CTRL_GPTRUN(x)             (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER1CTRL_GPTRUN_SHIFT)) & USBHS_GPTIMER1CTRL_GPTRUN_MASK)
81151 /*! @} */
81152 
81153 /*! @name SBUSCFG - System Bus Config */
81154 /*! @{ */
81155 
81156 #define USBHS_SBUSCFG_AHBBRST_MASK               (0x7U)
81157 #define USBHS_SBUSCFG_AHBBRST_SHIFT              (0U)
81158 /*! AHBBRST - AHB master interface Burst configuration
81159  *  0b000..Incremental burst of unspecified length only
81160  *  0b001..INCR4 burst, then single transfer
81161  *  0b010..INCR8 burst, INCR4 burst, then single transfer
81162  *  0b011..INCR16 burst, INCR8 burst, INCR4 burst, then single transfer
81163  *  0b100..Reserved, don't use
81164  *  0b101..INCR4 burst, then incremental burst of unspecified length
81165  *  0b110..INCR8 burst, INCR4 burst, then incremental burst of unspecified length
81166  *  0b111..INCR16 burst, INCR8 burst, INCR4 burst, then incremental burst of unspecified length
81167  */
81168 #define USBHS_SBUSCFG_AHBBRST(x)                 (((uint32_t)(((uint32_t)(x)) << USBHS_SBUSCFG_AHBBRST_SHIFT)) & USBHS_SBUSCFG_AHBBRST_MASK)
81169 /*! @} */
81170 
81171 /*! @name CAPLENGTH - Capability Registers Length */
81172 /*! @{ */
81173 
81174 #define USBHS_CAPLENGTH_CAPLENGTH_MASK           (0xFFU)
81175 #define USBHS_CAPLENGTH_CAPLENGTH_SHIFT          (0U)
81176 /*! CAPLENGTH - These bits are used as an offset to add to register base to find the beginning of
81177  *    the Operational Register. Default value is '40h'.
81178  */
81179 #define USBHS_CAPLENGTH_CAPLENGTH(x)             (((uint8_t)(((uint8_t)(x)) << USBHS_CAPLENGTH_CAPLENGTH_SHIFT)) & USBHS_CAPLENGTH_CAPLENGTH_MASK)
81180 /*! @} */
81181 
81182 /*! @name HCIVERSION - Host Controller Interface Version */
81183 /*! @{ */
81184 
81185 #define USBHS_HCIVERSION_HCIVERSION_MASK         (0xFFFFU)
81186 #define USBHS_HCIVERSION_HCIVERSION_SHIFT        (0U)
81187 /*! HCIVERSION - Host Controller Interface Version Number */
81188 #define USBHS_HCIVERSION_HCIVERSION(x)           (((uint16_t)(((uint16_t)(x)) << USBHS_HCIVERSION_HCIVERSION_SHIFT)) & USBHS_HCIVERSION_HCIVERSION_MASK)
81189 /*! @} */
81190 
81191 /*! @name HCSPARAMS - Host Controller Structural Parameters */
81192 /*! @{ */
81193 
81194 #define USBHS_HCSPARAMS_N_PORTS_MASK             (0xFU)
81195 #define USBHS_HCSPARAMS_N_PORTS_SHIFT            (0U)
81196 /*! N_PORTS - Number of Downstream Ports */
81197 #define USBHS_HCSPARAMS_N_PORTS(x)               (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_N_PORTS_SHIFT)) & USBHS_HCSPARAMS_N_PORTS_MASK)
81198 
81199 #define USBHS_HCSPARAMS_PPC_MASK                 (0x10U)
81200 #define USBHS_HCSPARAMS_PPC_SHIFT                (4U)
81201 /*! PPC - Port Power Control */
81202 #define USBHS_HCSPARAMS_PPC(x)                   (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_PPC_SHIFT)) & USBHS_HCSPARAMS_PPC_MASK)
81203 
81204 #define USBHS_HCSPARAMS_N_PCC_MASK               (0xF00U)
81205 #define USBHS_HCSPARAMS_N_PCC_SHIFT              (8U)
81206 /*! N_PCC - Number of Ports per Companion Controller */
81207 #define USBHS_HCSPARAMS_N_PCC(x)                 (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_N_PCC_SHIFT)) & USBHS_HCSPARAMS_N_PCC_MASK)
81208 
81209 #define USBHS_HCSPARAMS_N_CC_MASK                (0xF000U)
81210 #define USBHS_HCSPARAMS_N_CC_SHIFT               (12U)
81211 /*! N_CC - Number of Companion Controller
81212  *  0b0000..There is no internal Companion Controller and port-ownership hand-off is not supported
81213  *  0b0001..There are internal companion controller(s) and port-ownership hand-offs is supported
81214  */
81215 #define USBHS_HCSPARAMS_N_CC(x)                  (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_N_CC_SHIFT)) & USBHS_HCSPARAMS_N_CC_MASK)
81216 
81217 #define USBHS_HCSPARAMS_PI_MASK                  (0x10000U)
81218 #define USBHS_HCSPARAMS_PI_SHIFT                 (16U)
81219 /*! PI - Port Indicators (P INDICATOR) */
81220 #define USBHS_HCSPARAMS_PI(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_PI_SHIFT)) & USBHS_HCSPARAMS_PI_MASK)
81221 
81222 #define USBHS_HCSPARAMS_N_PTT_MASK               (0xF00000U)
81223 #define USBHS_HCSPARAMS_N_PTT_SHIFT              (20U)
81224 /*! N_PTT - Number of Ports per Transaction Translator */
81225 #define USBHS_HCSPARAMS_N_PTT(x)                 (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_N_PTT_SHIFT)) & USBHS_HCSPARAMS_N_PTT_MASK)
81226 
81227 #define USBHS_HCSPARAMS_N_TT_MASK                (0xF000000U)
81228 #define USBHS_HCSPARAMS_N_TT_SHIFT               (24U)
81229 /*! N_TT - Number of Transaction Translators */
81230 #define USBHS_HCSPARAMS_N_TT(x)                  (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_N_TT_SHIFT)) & USBHS_HCSPARAMS_N_TT_MASK)
81231 /*! @} */
81232 
81233 /*! @name HCCPARAMS - Host Controller Capability Parameters */
81234 /*! @{ */
81235 
81236 #define USBHS_HCCPARAMS_ADC_MASK                 (0x1U)
81237 #define USBHS_HCCPARAMS_ADC_SHIFT                (0U)
81238 /*! ADC - 64-bit Addressing Capability */
81239 #define USBHS_HCCPARAMS_ADC(x)                   (((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_ADC_SHIFT)) & USBHS_HCCPARAMS_ADC_MASK)
81240 
81241 #define USBHS_HCCPARAMS_PFL_MASK                 (0x2U)
81242 #define USBHS_HCCPARAMS_PFL_SHIFT                (1U)
81243 /*! PFL - Programmable Frame List Flag */
81244 #define USBHS_HCCPARAMS_PFL(x)                   (((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_PFL_SHIFT)) & USBHS_HCCPARAMS_PFL_MASK)
81245 
81246 #define USBHS_HCCPARAMS_ASP_MASK                 (0x4U)
81247 #define USBHS_HCCPARAMS_ASP_SHIFT                (2U)
81248 /*! ASP - Asynchronous Schedule Park Capability */
81249 #define USBHS_HCCPARAMS_ASP(x)                   (((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_ASP_SHIFT)) & USBHS_HCCPARAMS_ASP_MASK)
81250 
81251 #define USBHS_HCCPARAMS_IST_MASK                 (0xF0U)
81252 #define USBHS_HCCPARAMS_IST_SHIFT                (4U)
81253 /*! IST - Isochronous Scheduling Threshold */
81254 #define USBHS_HCCPARAMS_IST(x)                   (((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_IST_SHIFT)) & USBHS_HCCPARAMS_IST_MASK)
81255 
81256 #define USBHS_HCCPARAMS_EECP_MASK                (0xFF00U)
81257 #define USBHS_HCCPARAMS_EECP_SHIFT               (8U)
81258 /*! EECP - EHCI Extended Capabilities Pointer */
81259 #define USBHS_HCCPARAMS_EECP(x)                  (((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_EECP_SHIFT)) & USBHS_HCCPARAMS_EECP_MASK)
81260 /*! @} */
81261 
81262 /*! @name DCIVERSION - Device Controller Interface Version */
81263 /*! @{ */
81264 
81265 #define USBHS_DCIVERSION_DCIVERSION_MASK         (0xFFFFU)
81266 #define USBHS_DCIVERSION_DCIVERSION_SHIFT        (0U)
81267 /*! DCIVERSION - Device Controller Interface Version Number */
81268 #define USBHS_DCIVERSION_DCIVERSION(x)           (((uint16_t)(((uint16_t)(x)) << USBHS_DCIVERSION_DCIVERSION_SHIFT)) & USBHS_DCIVERSION_DCIVERSION_MASK)
81269 /*! @} */
81270 
81271 /*! @name DCCPARAMS - Device Controller Capability Parameters */
81272 /*! @{ */
81273 
81274 #define USBHS_DCCPARAMS_DEN_MASK                 (0x1FU)
81275 #define USBHS_DCCPARAMS_DEN_SHIFT                (0U)
81276 /*! DEN - Device Endpoint Number */
81277 #define USBHS_DCCPARAMS_DEN(x)                   (((uint32_t)(((uint32_t)(x)) << USBHS_DCCPARAMS_DEN_SHIFT)) & USBHS_DCCPARAMS_DEN_MASK)
81278 
81279 #define USBHS_DCCPARAMS_DC_MASK                  (0x80U)
81280 #define USBHS_DCCPARAMS_DC_SHIFT                 (7U)
81281 /*! DC - Device Capable */
81282 #define USBHS_DCCPARAMS_DC(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_DCCPARAMS_DC_SHIFT)) & USBHS_DCCPARAMS_DC_MASK)
81283 
81284 #define USBHS_DCCPARAMS_HC_MASK                  (0x100U)
81285 #define USBHS_DCCPARAMS_HC_SHIFT                 (8U)
81286 /*! HC - Host Capable */
81287 #define USBHS_DCCPARAMS_HC(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_DCCPARAMS_HC_SHIFT)) & USBHS_DCCPARAMS_HC_MASK)
81288 /*! @} */
81289 
81290 /*! @name USBCMD - USB Command */
81291 /*! @{ */
81292 
81293 #define USBHS_USBCMD_RS_MASK                     (0x1U)
81294 #define USBHS_USBCMD_RS_SHIFT                    (0U)
81295 /*! RS - Run/Stop
81296  *  0b0..Stop
81297  *  0b1..Run
81298  */
81299 #define USBHS_USBCMD_RS(x)                       (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_RS_SHIFT)) & USBHS_USBCMD_RS_MASK)
81300 
81301 #define USBHS_USBCMD_RST_MASK                    (0x2U)
81302 #define USBHS_USBCMD_RST_SHIFT                   (1U)
81303 /*! RST - Controller Reset */
81304 #define USBHS_USBCMD_RST(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_RST_SHIFT)) & USBHS_USBCMD_RST_MASK)
81305 
81306 #define USBHS_USBCMD_FS_1_MASK                   (0xCU)
81307 #define USBHS_USBCMD_FS_1_SHIFT                  (2U)
81308 /*! FS_1 - Frame List Size */
81309 #define USBHS_USBCMD_FS_1(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_FS_1_SHIFT)) & USBHS_USBCMD_FS_1_MASK)
81310 
81311 #define USBHS_USBCMD_PSE_MASK                    (0x10U)
81312 #define USBHS_USBCMD_PSE_SHIFT                   (4U)
81313 /*! PSE - Periodic Schedule Enable
81314  *  0b0..Do not process the Periodic Schedule
81315  *  0b1..Use the PERIODICLISTBASE register to access the Periodic Schedule
81316  */
81317 #define USBHS_USBCMD_PSE(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_PSE_SHIFT)) & USBHS_USBCMD_PSE_MASK)
81318 
81319 #define USBHS_USBCMD_ASE_MASK                    (0x20U)
81320 #define USBHS_USBCMD_ASE_SHIFT                   (5U)
81321 /*! ASE - Asynchronous Schedule Enable
81322  *  0b0..Do not process the Asynchronous Schedule
81323  *  0b1..Use the ASYNCLISTADDR register to access the Asynchronous Schedule
81324  */
81325 #define USBHS_USBCMD_ASE(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ASE_SHIFT)) & USBHS_USBCMD_ASE_MASK)
81326 
81327 #define USBHS_USBCMD_IAA_MASK                    (0x40U)
81328 #define USBHS_USBCMD_IAA_SHIFT                   (6U)
81329 /*! IAA - Interrupt on Async Advance Doorbell */
81330 #define USBHS_USBCMD_IAA(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_IAA_SHIFT)) & USBHS_USBCMD_IAA_MASK)
81331 
81332 #define USBHS_USBCMD_ASP_MASK                    (0x300U)
81333 #define USBHS_USBCMD_ASP_SHIFT                   (8U)
81334 /*! ASP - Asynchronous Schedule Park Mode Count */
81335 #define USBHS_USBCMD_ASP(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ASP_SHIFT)) & USBHS_USBCMD_ASP_MASK)
81336 
81337 #define USBHS_USBCMD_ASPE_MASK                   (0x800U)
81338 #define USBHS_USBCMD_ASPE_SHIFT                  (11U)
81339 /*! ASPE - Asynchronous Schedule Park Mode Enable */
81340 #define USBHS_USBCMD_ASPE(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ASPE_SHIFT)) & USBHS_USBCMD_ASPE_MASK)
81341 
81342 #define USBHS_USBCMD_SUTW_MASK                   (0x2000U)
81343 #define USBHS_USBCMD_SUTW_SHIFT                  (13U)
81344 /*! SUTW - Setup TripWire [device mode only] */
81345 #define USBHS_USBCMD_SUTW(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_SUTW_SHIFT)) & USBHS_USBCMD_SUTW_MASK)
81346 
81347 #define USBHS_USBCMD_ATDTW_MASK                  (0x4000U)
81348 #define USBHS_USBCMD_ATDTW_SHIFT                 (14U)
81349 /*! ATDTW - Add dTD TripWire[device mode only] */
81350 #define USBHS_USBCMD_ATDTW(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ATDTW_SHIFT)) & USBHS_USBCMD_ATDTW_MASK)
81351 
81352 #define USBHS_USBCMD_FS_2_MASK                   (0x8000U)
81353 #define USBHS_USBCMD_FS_2_SHIFT                  (15U)
81354 /*! FS_2 - Frame List Size [host mode only] */
81355 #define USBHS_USBCMD_FS_2(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_FS_2_SHIFT)) & USBHS_USBCMD_FS_2_MASK)
81356 
81357 #define USBHS_USBCMD_ITC_MASK                    (0xFF0000U)
81358 #define USBHS_USBCMD_ITC_SHIFT                   (16U)
81359 /*! ITC - Interrupt Threshold Control
81360  *  0b00000000..Immediate (no threshold)
81361  *  0b00000001..1 micro-frame
81362  *  0b00000010..2 micro-frames
81363  *  0b00000100..4 micro-frames
81364  *  0b00001000..8 micro-frames
81365  *  0b00010000..16 micro-frames
81366  *  0b00100000..32 micro-frames
81367  *  0b01000000..64 micro-frames
81368  */
81369 #define USBHS_USBCMD_ITC(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ITC_SHIFT)) & USBHS_USBCMD_ITC_MASK)
81370 /*! @} */
81371 
81372 /*! @name USBSTS - USB Status */
81373 /*! @{ */
81374 
81375 #define USBHS_USBSTS_UI_MASK                     (0x1U)
81376 #define USBHS_USBSTS_UI_SHIFT                    (0U)
81377 /*! UI - USB Interrupt (USBINT) */
81378 #define USBHS_USBSTS_UI(x)                       (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_UI_SHIFT)) & USBHS_USBSTS_UI_MASK)
81379 
81380 #define USBHS_USBSTS_UEI_MASK                    (0x2U)
81381 #define USBHS_USBSTS_UEI_SHIFT                   (1U)
81382 /*! UEI - USB Error Interrupt (USBERRINT) */
81383 #define USBHS_USBSTS_UEI(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_UEI_SHIFT)) & USBHS_USBSTS_UEI_MASK)
81384 
81385 #define USBHS_USBSTS_PCI_MASK                    (0x4U)
81386 #define USBHS_USBSTS_PCI_SHIFT                   (2U)
81387 /*! PCI - Port Change Detect */
81388 #define USBHS_USBSTS_PCI(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_PCI_SHIFT)) & USBHS_USBSTS_PCI_MASK)
81389 
81390 #define USBHS_USBSTS_FRI_MASK                    (0x8U)
81391 #define USBHS_USBSTS_FRI_SHIFT                   (3U)
81392 /*! FRI - Frame List Rollover */
81393 #define USBHS_USBSTS_FRI(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_FRI_SHIFT)) & USBHS_USBSTS_FRI_MASK)
81394 
81395 #define USBHS_USBSTS_SEI_MASK                    (0x10U)
81396 #define USBHS_USBSTS_SEI_SHIFT                   (4U)
81397 /*! SEI - System Error */
81398 #define USBHS_USBSTS_SEI(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_SEI_SHIFT)) & USBHS_USBSTS_SEI_MASK)
81399 
81400 #define USBHS_USBSTS_AAI_MASK                    (0x20U)
81401 #define USBHS_USBSTS_AAI_SHIFT                   (5U)
81402 /*! AAI - Interrupt on Async Advance */
81403 #define USBHS_USBSTS_AAI(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_AAI_SHIFT)) & USBHS_USBSTS_AAI_MASK)
81404 
81405 #define USBHS_USBSTS_URI_MASK                    (0x40U)
81406 #define USBHS_USBSTS_URI_SHIFT                   (6U)
81407 /*! URI - USB Reset Received */
81408 #define USBHS_USBSTS_URI(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_URI_SHIFT)) & USBHS_USBSTS_URI_MASK)
81409 
81410 #define USBHS_USBSTS_SRI_MASK                    (0x80U)
81411 #define USBHS_USBSTS_SRI_SHIFT                   (7U)
81412 /*! SRI - SOF Received */
81413 #define USBHS_USBSTS_SRI(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_SRI_SHIFT)) & USBHS_USBSTS_SRI_MASK)
81414 
81415 #define USBHS_USBSTS_SLI_MASK                    (0x100U)
81416 #define USBHS_USBSTS_SLI_SHIFT                   (8U)
81417 /*! SLI - DCSuspend */
81418 #define USBHS_USBSTS_SLI(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_SLI_SHIFT)) & USBHS_USBSTS_SLI_MASK)
81419 
81420 #define USBHS_USBSTS_ULPII_MASK                  (0x400U)
81421 #define USBHS_USBSTS_ULPII_SHIFT                 (10U)
81422 /*! ULPII - ULPI Interrupt */
81423 #define USBHS_USBSTS_ULPII(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_ULPII_SHIFT)) & USBHS_USBSTS_ULPII_MASK)
81424 
81425 #define USBHS_USBSTS_HCH_MASK                    (0x1000U)
81426 #define USBHS_USBSTS_HCH_SHIFT                   (12U)
81427 /*! HCH - HCHaIted */
81428 #define USBHS_USBSTS_HCH(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_HCH_SHIFT)) & USBHS_USBSTS_HCH_MASK)
81429 
81430 #define USBHS_USBSTS_RCL_MASK                    (0x2000U)
81431 #define USBHS_USBSTS_RCL_SHIFT                   (13U)
81432 /*! RCL - Reclamation */
81433 #define USBHS_USBSTS_RCL(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_RCL_SHIFT)) & USBHS_USBSTS_RCL_MASK)
81434 
81435 #define USBHS_USBSTS_PS_MASK                     (0x4000U)
81436 #define USBHS_USBSTS_PS_SHIFT                    (14U)
81437 /*! PS - Periodic Schedule Status */
81438 #define USBHS_USBSTS_PS(x)                       (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_PS_SHIFT)) & USBHS_USBSTS_PS_MASK)
81439 
81440 #define USBHS_USBSTS_AS_MASK                     (0x8000U)
81441 #define USBHS_USBSTS_AS_SHIFT                    (15U)
81442 /*! AS - Asynchronous Schedule Status */
81443 #define USBHS_USBSTS_AS(x)                       (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_AS_SHIFT)) & USBHS_USBSTS_AS_MASK)
81444 
81445 #define USBHS_USBSTS_NAKI_MASK                   (0x10000U)
81446 #define USBHS_USBSTS_NAKI_SHIFT                  (16U)
81447 /*! NAKI - NAK Interrupt Bit */
81448 #define USBHS_USBSTS_NAKI(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_NAKI_SHIFT)) & USBHS_USBSTS_NAKI_MASK)
81449 
81450 #define USBHS_USBSTS_TI0_MASK                    (0x1000000U)
81451 #define USBHS_USBSTS_TI0_SHIFT                   (24U)
81452 /*! TI0 - General Purpose Timer Interrupt 0 (GPTINT0) */
81453 #define USBHS_USBSTS_TI0(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_TI0_SHIFT)) & USBHS_USBSTS_TI0_MASK)
81454 
81455 #define USBHS_USBSTS_TI1_MASK                    (0x2000000U)
81456 #define USBHS_USBSTS_TI1_SHIFT                   (25U)
81457 /*! TI1 - General Purpose Timer Interrupt 1 (GPTINT1) */
81458 #define USBHS_USBSTS_TI1(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_TI1_SHIFT)) & USBHS_USBSTS_TI1_MASK)
81459 /*! @} */
81460 
81461 /*! @name USBINTR - Interrupt Enable */
81462 /*! @{ */
81463 
81464 #define USBHS_USBINTR_UE_MASK                    (0x1U)
81465 #define USBHS_USBINTR_UE_SHIFT                   (0U)
81466 /*! UE - USB Interrupt Enable */
81467 #define USBHS_USBINTR_UE(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_UE_SHIFT)) & USBHS_USBINTR_UE_MASK)
81468 
81469 #define USBHS_USBINTR_UEE_MASK                   (0x2U)
81470 #define USBHS_USBINTR_UEE_SHIFT                  (1U)
81471 /*! UEE - USB Error Interrupt Enable */
81472 #define USBHS_USBINTR_UEE(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_UEE_SHIFT)) & USBHS_USBINTR_UEE_MASK)
81473 
81474 #define USBHS_USBINTR_PCE_MASK                   (0x4U)
81475 #define USBHS_USBINTR_PCE_SHIFT                  (2U)
81476 /*! PCE - Port Change Detect Interrupt Enable */
81477 #define USBHS_USBINTR_PCE(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_PCE_SHIFT)) & USBHS_USBINTR_PCE_MASK)
81478 
81479 #define USBHS_USBINTR_FRE_MASK                   (0x8U)
81480 #define USBHS_USBINTR_FRE_SHIFT                  (3U)
81481 /*! FRE - Frame List Rollover Interrupt Enable */
81482 #define USBHS_USBINTR_FRE(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_FRE_SHIFT)) & USBHS_USBINTR_FRE_MASK)
81483 
81484 #define USBHS_USBINTR_SEE_MASK                   (0x10U)
81485 #define USBHS_USBINTR_SEE_SHIFT                  (4U)
81486 /*! SEE - System Error Interrupt Enable */
81487 #define USBHS_USBINTR_SEE(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_SEE_SHIFT)) & USBHS_USBINTR_SEE_MASK)
81488 
81489 #define USBHS_USBINTR_AAE_MASK                   (0x20U)
81490 #define USBHS_USBINTR_AAE_SHIFT                  (5U)
81491 /*! AAE - Async Advance Interrupt Enable */
81492 #define USBHS_USBINTR_AAE(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_AAE_SHIFT)) & USBHS_USBINTR_AAE_MASK)
81493 
81494 #define USBHS_USBINTR_URE_MASK                   (0x40U)
81495 #define USBHS_USBINTR_URE_SHIFT                  (6U)
81496 /*! URE - USB Reset Interrupt Enable */
81497 #define USBHS_USBINTR_URE(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_URE_SHIFT)) & USBHS_USBINTR_URE_MASK)
81498 
81499 #define USBHS_USBINTR_SRE_MASK                   (0x80U)
81500 #define USBHS_USBINTR_SRE_SHIFT                  (7U)
81501 /*! SRE - SOF Received Interrupt Enable */
81502 #define USBHS_USBINTR_SRE(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_SRE_SHIFT)) & USBHS_USBINTR_SRE_MASK)
81503 
81504 #define USBHS_USBINTR_SLE_MASK                   (0x100U)
81505 #define USBHS_USBINTR_SLE_SHIFT                  (8U)
81506 /*! SLE - Sleep Interrupt Enable */
81507 #define USBHS_USBINTR_SLE(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_SLE_SHIFT)) & USBHS_USBINTR_SLE_MASK)
81508 
81509 #define USBHS_USBINTR_NAKE_MASK                  (0x10000U)
81510 #define USBHS_USBINTR_NAKE_SHIFT                 (16U)
81511 /*! NAKE - NAK Interrupt Enable */
81512 #define USBHS_USBINTR_NAKE(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_NAKE_SHIFT)) & USBHS_USBINTR_NAKE_MASK)
81513 
81514 #define USBHS_USBINTR_UAIE_MASK                  (0x40000U)
81515 #define USBHS_USBINTR_UAIE_SHIFT                 (18U)
81516 /*! UAIE - USB Host Asynchronous Interrupt Enable */
81517 #define USBHS_USBINTR_UAIE(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_UAIE_SHIFT)) & USBHS_USBINTR_UAIE_MASK)
81518 
81519 #define USBHS_USBINTR_UPIE_MASK                  (0x80000U)
81520 #define USBHS_USBINTR_UPIE_SHIFT                 (19U)
81521 /*! UPIE - USB Host Periodic Interrupt Enable */
81522 #define USBHS_USBINTR_UPIE(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_UPIE_SHIFT)) & USBHS_USBINTR_UPIE_MASK)
81523 
81524 #define USBHS_USBINTR_TIE0_MASK                  (0x1000000U)
81525 #define USBHS_USBINTR_TIE0_SHIFT                 (24U)
81526 /*! TIE0 - General Purpose Timer #0 Interrupt Enable */
81527 #define USBHS_USBINTR_TIE0(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_TIE0_SHIFT)) & USBHS_USBINTR_TIE0_MASK)
81528 
81529 #define USBHS_USBINTR_TIE1_MASK                  (0x2000000U)
81530 #define USBHS_USBINTR_TIE1_SHIFT                 (25U)
81531 /*! TIE1 - General Purpose Timer #1 Interrupt Enable */
81532 #define USBHS_USBINTR_TIE1(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_TIE1_SHIFT)) & USBHS_USBINTR_TIE1_MASK)
81533 /*! @} */
81534 
81535 /*! @name FRINDEX - USB Frame Index */
81536 /*! @{ */
81537 
81538 #define USBHS_FRINDEX_FRINDEX_MASK               (0x3FFFU)
81539 #define USBHS_FRINDEX_FRINDEX_SHIFT              (0U)
81540 /*! FRINDEX - Frame Index
81541  *  0b00000000000000..(1024) 12
81542  *  0b00000000000001..(512) 11
81543  *  0b00000000000010..(256) 10
81544  *  0b00000000000011..(128) 9
81545  *  0b00000000000100..(64) 8
81546  *  0b00000000000101..(32) 7
81547  *  0b00000000000110..(16) 6
81548  *  0b00000000000111..(8) 5
81549  */
81550 #define USBHS_FRINDEX_FRINDEX(x)                 (((uint32_t)(((uint32_t)(x)) << USBHS_FRINDEX_FRINDEX_SHIFT)) & USBHS_FRINDEX_FRINDEX_MASK)
81551 /*! @} */
81552 
81553 /*! @name DEVICEADDR - Device Address */
81554 /*! @{ */
81555 
81556 #define USBHS_DEVICEADDR_USBADRA_MASK            (0x1000000U)
81557 #define USBHS_DEVICEADDR_USBADRA_SHIFT           (24U)
81558 /*! USBADRA - Device Address Advance */
81559 #define USBHS_DEVICEADDR_USBADRA(x)              (((uint32_t)(((uint32_t)(x)) << USBHS_DEVICEADDR_USBADRA_SHIFT)) & USBHS_DEVICEADDR_USBADRA_MASK)
81560 
81561 #define USBHS_DEVICEADDR_USBADR_MASK             (0xFE000000U)
81562 #define USBHS_DEVICEADDR_USBADR_SHIFT            (25U)
81563 /*! USBADR - Device Address */
81564 #define USBHS_DEVICEADDR_USBADR(x)               (((uint32_t)(((uint32_t)(x)) << USBHS_DEVICEADDR_USBADR_SHIFT)) & USBHS_DEVICEADDR_USBADR_MASK)
81565 /*! @} */
81566 
81567 /*! @name PERIODICLISTBASE - Frame List Base Address */
81568 /*! @{ */
81569 
81570 #define USBHS_PERIODICLISTBASE_BASEADR_MASK      (0xFFFFF000U)
81571 #define USBHS_PERIODICLISTBASE_BASEADR_SHIFT     (12U)
81572 /*! BASEADR - Base Address (Low) */
81573 #define USBHS_PERIODICLISTBASE_BASEADR(x)        (((uint32_t)(((uint32_t)(x)) << USBHS_PERIODICLISTBASE_BASEADR_SHIFT)) & USBHS_PERIODICLISTBASE_BASEADR_MASK)
81574 /*! @} */
81575 
81576 /*! @name ASYNCLISTADDR - Next Asynch. Address */
81577 /*! @{ */
81578 
81579 #define USBHS_ASYNCLISTADDR_ASYBASE_MASK         (0xFFFFFFE0U)
81580 #define USBHS_ASYNCLISTADDR_ASYBASE_SHIFT        (5U)
81581 /*! ASYBASE - Link Pointer Low (LPL) */
81582 #define USBHS_ASYNCLISTADDR_ASYBASE(x)           (((uint32_t)(((uint32_t)(x)) << USBHS_ASYNCLISTADDR_ASYBASE_SHIFT)) & USBHS_ASYNCLISTADDR_ASYBASE_MASK)
81583 /*! @} */
81584 
81585 /*! @name ENDPTLISTADDR - Endpoint List Address */
81586 /*! @{ */
81587 
81588 #define USBHS_ENDPTLISTADDR_EPBASE_MASK          (0xFFFFF800U)
81589 #define USBHS_ENDPTLISTADDR_EPBASE_SHIFT         (11U)
81590 /*! EPBASE - Endpoint List Pointer (Low) */
81591 #define USBHS_ENDPTLISTADDR_EPBASE(x)            (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTLISTADDR_EPBASE_SHIFT)) & USBHS_ENDPTLISTADDR_EPBASE_MASK)
81592 /*! @} */
81593 
81594 /*! @name BURSTSIZE - Programmable Burst Size */
81595 /*! @{ */
81596 
81597 #define USBHS_BURSTSIZE_RXPBURST_MASK            (0xFFU)
81598 #define USBHS_BURSTSIZE_RXPBURST_SHIFT           (0U)
81599 /*! RXPBURST - Programmable RX Burst Size */
81600 #define USBHS_BURSTSIZE_RXPBURST(x)              (((uint32_t)(((uint32_t)(x)) << USBHS_BURSTSIZE_RXPBURST_SHIFT)) & USBHS_BURSTSIZE_RXPBURST_MASK)
81601 
81602 #define USBHS_BURSTSIZE_TXPBURST_MASK            (0xFF00U)
81603 #define USBHS_BURSTSIZE_TXPBURST_SHIFT           (8U)
81604 /*! TXPBURST - Programmable TX Burst Size */
81605 #define USBHS_BURSTSIZE_TXPBURST(x)              (((uint32_t)(((uint32_t)(x)) << USBHS_BURSTSIZE_TXPBURST_SHIFT)) & USBHS_BURSTSIZE_TXPBURST_MASK)
81606 /*! @} */
81607 
81608 /*! @name TXFILLTUNING - TX FIFO Fill Tuning */
81609 /*! @{ */
81610 
81611 #define USBHS_TXFILLTUNING_TXSCHOH_MASK          (0x7FU)
81612 #define USBHS_TXFILLTUNING_TXSCHOH_SHIFT         (0U)
81613 /*! TXSCHOH - Scheduler Overhead */
81614 #define USBHS_TXFILLTUNING_TXSCHOH(x)            (((uint32_t)(((uint32_t)(x)) << USBHS_TXFILLTUNING_TXSCHOH_SHIFT)) & USBHS_TXFILLTUNING_TXSCHOH_MASK)
81615 
81616 #define USBHS_TXFILLTUNING_TXSCHHEALTH_MASK      (0x1F00U)
81617 #define USBHS_TXFILLTUNING_TXSCHHEALTH_SHIFT     (8U)
81618 /*! TXSCHHEALTH - Scheduler Health Counter */
81619 #define USBHS_TXFILLTUNING_TXSCHHEALTH(x)        (((uint32_t)(((uint32_t)(x)) << USBHS_TXFILLTUNING_TXSCHHEALTH_SHIFT)) & USBHS_TXFILLTUNING_TXSCHHEALTH_MASK)
81620 
81621 #define USBHS_TXFILLTUNING_TXFIFOTHRES_MASK      (0x3F0000U)
81622 #define USBHS_TXFILLTUNING_TXFIFOTHRES_SHIFT     (16U)
81623 /*! TXFIFOTHRES - FIFO Burst Threshold */
81624 #define USBHS_TXFILLTUNING_TXFIFOTHRES(x)        (((uint32_t)(((uint32_t)(x)) << USBHS_TXFILLTUNING_TXFIFOTHRES_SHIFT)) & USBHS_TXFILLTUNING_TXFIFOTHRES_MASK)
81625 /*! @} */
81626 
81627 /*! @name ENDPTNAK - Endpoint NAK */
81628 /*! @{ */
81629 
81630 #define USBHS_ENDPTNAK_EPRN_MASK                 (0xFFU)
81631 #define USBHS_ENDPTNAK_EPRN_SHIFT                (0U)
81632 /*! EPRN - RX Endpoint NAK */
81633 #define USBHS_ENDPTNAK_EPRN(x)                   (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTNAK_EPRN_SHIFT)) & USBHS_ENDPTNAK_EPRN_MASK)
81634 
81635 #define USBHS_ENDPTNAK_EPTN_MASK                 (0xFF0000U)
81636 #define USBHS_ENDPTNAK_EPTN_SHIFT                (16U)
81637 /*! EPTN - TX Endpoint NAK */
81638 #define USBHS_ENDPTNAK_EPTN(x)                   (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTNAK_EPTN_SHIFT)) & USBHS_ENDPTNAK_EPTN_MASK)
81639 /*! @} */
81640 
81641 /*! @name ENDPTNAKEN - Endpoint NAK Enable */
81642 /*! @{ */
81643 
81644 #define USBHS_ENDPTNAKEN_EPRNE_MASK              (0xFFU)
81645 #define USBHS_ENDPTNAKEN_EPRNE_SHIFT             (0U)
81646 /*! EPRNE - RX Endpoint NAK Enable */
81647 #define USBHS_ENDPTNAKEN_EPRNE(x)                (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTNAKEN_EPRNE_SHIFT)) & USBHS_ENDPTNAKEN_EPRNE_MASK)
81648 
81649 #define USBHS_ENDPTNAKEN_EPTNE_MASK              (0xFF0000U)
81650 #define USBHS_ENDPTNAKEN_EPTNE_SHIFT             (16U)
81651 /*! EPTNE - TX Endpoint NAK Enable */
81652 #define USBHS_ENDPTNAKEN_EPTNE(x)                (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTNAKEN_EPTNE_SHIFT)) & USBHS_ENDPTNAKEN_EPTNE_MASK)
81653 /*! @} */
81654 
81655 /*! @name CONFIGFLAG - Configure Flag */
81656 /*! @{ */
81657 
81658 #define USBHS_CONFIGFLAG_CF_MASK                 (0x1U)
81659 #define USBHS_CONFIGFLAG_CF_SHIFT                (0U)
81660 /*! CF - Configure Flag
81661  *  0b0..Port routing control logic default-routes each port to an implementation dependent classic host controller
81662  *  0b1..Port routing control logic default-routes all ports to this host controller
81663  */
81664 #define USBHS_CONFIGFLAG_CF(x)                   (((uint32_t)(((uint32_t)(x)) << USBHS_CONFIGFLAG_CF_SHIFT)) & USBHS_CONFIGFLAG_CF_MASK)
81665 /*! @} */
81666 
81667 /*! @name PORTSC1 - Port Status & Control */
81668 /*! @{ */
81669 
81670 #define USBHS_PORTSC1_CCS_MASK                   (0x1U)
81671 #define USBHS_PORTSC1_CCS_SHIFT                  (0U)
81672 /*! CCS - Current Connect Status
81673  *  0b0..In Host mode: No device is present. In Device mode: Not attached
81674  *  0b1..In Host mode: Device is present on port. In Device mode: Attached
81675  */
81676 #define USBHS_PORTSC1_CCS(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_CCS_SHIFT)) & USBHS_PORTSC1_CCS_MASK)
81677 
81678 #define USBHS_PORTSC1_CSC_MASK                   (0x2U)
81679 #define USBHS_PORTSC1_CSC_SHIFT                  (1U)
81680 /*! CSC - Connect Status Change
81681  *  0b0..No change
81682  *  0b1..Change in current connect status
81683  */
81684 #define USBHS_PORTSC1_CSC(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_CSC_SHIFT)) & USBHS_PORTSC1_CSC_MASK)
81685 
81686 #define USBHS_PORTSC1_PE_MASK                    (0x4U)
81687 #define USBHS_PORTSC1_PE_SHIFT                   (2U)
81688 /*! PE - Port Enabled/Disabled
81689  *  0b0..Disable
81690  *  0b1..Enable
81691  */
81692 #define USBHS_PORTSC1_PE(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PE_SHIFT)) & USBHS_PORTSC1_PE_MASK)
81693 
81694 #define USBHS_PORTSC1_PEC_MASK                   (0x8U)
81695 #define USBHS_PORTSC1_PEC_SHIFT                  (3U)
81696 /*! PEC - Port Enable/Disable Change
81697  *  0b0..No change
81698  *  0b1..Port enabled/disabled status has changed
81699  */
81700 #define USBHS_PORTSC1_PEC(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PEC_SHIFT)) & USBHS_PORTSC1_PEC_MASK)
81701 
81702 #define USBHS_PORTSC1_OCA_MASK                   (0x10U)
81703 #define USBHS_PORTSC1_OCA_SHIFT                  (4U)
81704 /*! OCA - Over-Current Active
81705  *  0b1..This port currently has an over-current condition
81706  *  0b0..This port does not have an over-current condition
81707  */
81708 #define USBHS_PORTSC1_OCA(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_OCA_SHIFT)) & USBHS_PORTSC1_OCA_MASK)
81709 
81710 #define USBHS_PORTSC1_OCC_MASK                   (0x20U)
81711 #define USBHS_PORTSC1_OCC_SHIFT                  (5U)
81712 /*! OCC - Over-current Change */
81713 #define USBHS_PORTSC1_OCC(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_OCC_SHIFT)) & USBHS_PORTSC1_OCC_MASK)
81714 
81715 #define USBHS_PORTSC1_FPR_MASK                   (0x40U)
81716 #define USBHS_PORTSC1_FPR_SHIFT                  (6U)
81717 /*! FPR - Force Port Resume
81718  *  0b0..No resume (K-state) detected/driven on port
81719  *  0b1..Resume detected/driven on port
81720  */
81721 #define USBHS_PORTSC1_FPR(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_FPR_SHIFT)) & USBHS_PORTSC1_FPR_MASK)
81722 
81723 #define USBHS_PORTSC1_SUSP_MASK                  (0x80U)
81724 #define USBHS_PORTSC1_SUSP_SHIFT                 (7U)
81725 /*! SUSP - Suspend
81726  *  0b0..Port not in suspend state
81727  *  0b1..Port in suspend state
81728  */
81729 #define USBHS_PORTSC1_SUSP(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_SUSP_SHIFT)) & USBHS_PORTSC1_SUSP_MASK)
81730 
81731 #define USBHS_PORTSC1_PR_MASK                    (0x100U)
81732 #define USBHS_PORTSC1_PR_SHIFT                   (8U)
81733 /*! PR - Port Reset
81734  *  0b0..Port is not in reset
81735  *  0b1..Port is in reset
81736  */
81737 #define USBHS_PORTSC1_PR(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PR_SHIFT)) & USBHS_PORTSC1_PR_MASK)
81738 
81739 #define USBHS_PORTSC1_HSP_MASK                   (0x200U)
81740 #define USBHS_PORTSC1_HSP_SHIFT                  (9U)
81741 /*! HSP - High-Speed Port */
81742 #define USBHS_PORTSC1_HSP(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_HSP_SHIFT)) & USBHS_PORTSC1_HSP_MASK)
81743 
81744 #define USBHS_PORTSC1_LS_MASK                    (0xC00U)
81745 #define USBHS_PORTSC1_LS_SHIFT                   (10U)
81746 /*! LS - Line Status
81747  *  0b00..SE0
81748  *  0b10..J-state
81749  *  0b01..K-state
81750  *  0b11..Undefined
81751  */
81752 #define USBHS_PORTSC1_LS(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_LS_SHIFT)) & USBHS_PORTSC1_LS_MASK)
81753 
81754 #define USBHS_PORTSC1_PP_MASK                    (0x1000U)
81755 #define USBHS_PORTSC1_PP_SHIFT                   (12U)
81756 /*! PP - Port Power */
81757 #define USBHS_PORTSC1_PP(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PP_SHIFT)) & USBHS_PORTSC1_PP_MASK)
81758 
81759 #define USBHS_PORTSC1_PO_MASK                    (0x2000U)
81760 #define USBHS_PORTSC1_PO_SHIFT                   (13U)
81761 /*! PO - Port Owner */
81762 #define USBHS_PORTSC1_PO(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PO_SHIFT)) & USBHS_PORTSC1_PO_MASK)
81763 
81764 #define USBHS_PORTSC1_PIC_MASK                   (0xC000U)
81765 #define USBHS_PORTSC1_PIC_SHIFT                  (14U)
81766 /*! PIC - Port Indicator Control
81767  *  0b00..Port indicators are off
81768  *  0b01..Amber
81769  *  0b10..Green
81770  *  0b11..Undefined
81771  */
81772 #define USBHS_PORTSC1_PIC(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PIC_SHIFT)) & USBHS_PORTSC1_PIC_MASK)
81773 
81774 #define USBHS_PORTSC1_PTC_MASK                   (0xF0000U)
81775 #define USBHS_PORTSC1_PTC_SHIFT                  (16U)
81776 /*! PTC - Port Test Control
81777  *  0b0000..TEST_MODE_DISABLE
81778  *  0b0001..J_STATE
81779  *  0b0010..K_STATE
81780  *  0b0011..SE0 (host) / NAK (device)
81781  *  0b0100..Packet
81782  *  0b0101..FORCE_ENABLE_HS
81783  *  0b0110..FORCE_ENABLE_FS
81784  *  0b0111..FORCE_ENABLE_LS
81785  *  0b1000-0b1111..Reserved
81786  */
81787 #define USBHS_PORTSC1_PTC(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PTC_SHIFT)) & USBHS_PORTSC1_PTC_MASK)
81788 
81789 #define USBHS_PORTSC1_WKCN_MASK                  (0x100000U)
81790 #define USBHS_PORTSC1_WKCN_SHIFT                 (20U)
81791 /*! WKCN - Wake on Connect Enable (WKCNNT_E) */
81792 #define USBHS_PORTSC1_WKCN(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_WKCN_SHIFT)) & USBHS_PORTSC1_WKCN_MASK)
81793 
81794 #define USBHS_PORTSC1_WKDC_MASK                  (0x200000U)
81795 #define USBHS_PORTSC1_WKDC_SHIFT                 (21U)
81796 /*! WKDC - Wake on Disconnect Enable (WKDSCNNT_E) */
81797 #define USBHS_PORTSC1_WKDC(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_WKDC_SHIFT)) & USBHS_PORTSC1_WKDC_MASK)
81798 
81799 #define USBHS_PORTSC1_WKOC_MASK                  (0x400000U)
81800 #define USBHS_PORTSC1_WKOC_SHIFT                 (22U)
81801 /*! WKOC - Wake on Over-current Enable (WKOC_E) */
81802 #define USBHS_PORTSC1_WKOC(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_WKOC_SHIFT)) & USBHS_PORTSC1_WKOC_MASK)
81803 
81804 #define USBHS_PORTSC1_PHCD_MASK                  (0x800000U)
81805 #define USBHS_PORTSC1_PHCD_SHIFT                 (23U)
81806 /*! PHCD - PHY Low Power Suspend - Clock Disable (PLPSCD)
81807  *  0b1..Disable PHY clock
81808  *  0b0..Enable PHY clock
81809  */
81810 #define USBHS_PORTSC1_PHCD(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PHCD_SHIFT)) & USBHS_PORTSC1_PHCD_MASK)
81811 
81812 #define USBHS_PORTSC1_PFSC_MASK                  (0x1000000U)
81813 #define USBHS_PORTSC1_PFSC_SHIFT                 (24U)
81814 /*! PFSC - Port Force Full Speed Connect
81815  *  0b1..Forced to full speed
81816  *  0b0..Normal operation
81817  */
81818 #define USBHS_PORTSC1_PFSC(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PFSC_SHIFT)) & USBHS_PORTSC1_PFSC_MASK)
81819 
81820 #define USBHS_PORTSC1_PTS_2_MASK                 (0x2000000U)
81821 #define USBHS_PORTSC1_PTS_2_SHIFT                (25U)
81822 /*! PTS_2 - Parallel Transceiver Select */
81823 #define USBHS_PORTSC1_PTS_2(x)                   (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PTS_2_SHIFT)) & USBHS_PORTSC1_PTS_2_MASK)
81824 
81825 #define USBHS_PORTSC1_PSPD_MASK                  (0xC000000U)
81826 #define USBHS_PORTSC1_PSPD_SHIFT                 (26U)
81827 /*! PSPD - Port Speed
81828  *  0b00..Full Speed
81829  *  0b01..Low Speed
81830  *  0b10..High Speed
81831  *  0b11..Undefined
81832  */
81833 #define USBHS_PORTSC1_PSPD(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PSPD_SHIFT)) & USBHS_PORTSC1_PSPD_MASK)
81834 
81835 #define USBHS_PORTSC1_PTW_MASK                   (0x10000000U)
81836 #define USBHS_PORTSC1_PTW_SHIFT                  (28U)
81837 /*! PTW - Parallel Transceiver Width - Read/Write
81838  *  0b0..Select the 8-bit UTMI interface [60 MHz]
81839  *  0b1..Select the 16-bit UTMI interface [30 MHz]
81840  */
81841 #define USBHS_PORTSC1_PTW(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PTW_SHIFT)) & USBHS_PORTSC1_PTW_MASK)
81842 
81843 #define USBHS_PORTSC1_STS_MASK                   (0x20000000U)
81844 #define USBHS_PORTSC1_STS_SHIFT                  (29U)
81845 /*! STS - Serial Transceiver Select
81846  *  0b0..Parallel Interface signals is selected
81847  *  0b1..Serial Interface Engine is selected
81848  */
81849 #define USBHS_PORTSC1_STS(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_STS_SHIFT)) & USBHS_PORTSC1_STS_MASK)
81850 
81851 #define USBHS_PORTSC1_PTS_1_MASK                 (0xC0000000U)
81852 #define USBHS_PORTSC1_PTS_1_SHIFT                (30U)
81853 /*! PTS_1 - Parallel Transceiver Select */
81854 #define USBHS_PORTSC1_PTS_1(x)                   (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PTS_1_SHIFT)) & USBHS_PORTSC1_PTS_1_MASK)
81855 /*! @} */
81856 
81857 /*! @name OTGSC - On-The-Go Status & Control */
81858 /*! @{ */
81859 
81860 #define USBHS_OTGSC_VD_MASK                      (0x1U)
81861 #define USBHS_OTGSC_VD_SHIFT                     (0U)
81862 /*! VD - VBUS Discharge */
81863 #define USBHS_OTGSC_VD(x)                        (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_VD_SHIFT)) & USBHS_OTGSC_VD_MASK)
81864 
81865 #define USBHS_OTGSC_VC_MASK                      (0x2U)
81866 #define USBHS_OTGSC_VC_SHIFT                     (1U)
81867 /*! VC - VBUS Charge */
81868 #define USBHS_OTGSC_VC(x)                        (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_VC_SHIFT)) & USBHS_OTGSC_VC_MASK)
81869 
81870 #define USBHS_OTGSC_OT_MASK                      (0x8U)
81871 #define USBHS_OTGSC_OT_SHIFT                     (3U)
81872 /*! OT - OTG Termination */
81873 #define USBHS_OTGSC_OT(x)                        (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_OT_SHIFT)) & USBHS_OTGSC_OT_MASK)
81874 
81875 #define USBHS_OTGSC_DP_MASK                      (0x10U)
81876 #define USBHS_OTGSC_DP_SHIFT                     (4U)
81877 /*! DP - Data Pulsing */
81878 #define USBHS_OTGSC_DP(x)                        (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_DP_SHIFT)) & USBHS_OTGSC_DP_MASK)
81879 
81880 #define USBHS_OTGSC_IDPU_MASK                    (0x20U)
81881 #define USBHS_OTGSC_IDPU_SHIFT                   (5U)
81882 /*! IDPU - ID Pullup
81883  *  0b0..Off
81884  *  0b1..On
81885  */
81886 #define USBHS_OTGSC_IDPU(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_IDPU_SHIFT)) & USBHS_OTGSC_IDPU_MASK)
81887 
81888 #define USBHS_OTGSC_ID_MASK                      (0x100U)
81889 #define USBHS_OTGSC_ID_SHIFT                     (8U)
81890 /*! ID - USB ID
81891  *  0b0..A device
81892  *  0b1..B device
81893  */
81894 #define USBHS_OTGSC_ID(x)                        (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_ID_SHIFT)) & USBHS_OTGSC_ID_MASK)
81895 
81896 #define USBHS_OTGSC_AVV_MASK                     (0x200U)
81897 #define USBHS_OTGSC_AVV_SHIFT                    (9U)
81898 /*! AVV - A VBus Valid */
81899 #define USBHS_OTGSC_AVV(x)                       (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_AVV_SHIFT)) & USBHS_OTGSC_AVV_MASK)
81900 
81901 #define USBHS_OTGSC_ASV_MASK                     (0x400U)
81902 #define USBHS_OTGSC_ASV_SHIFT                    (10U)
81903 /*! ASV - A Session Valid */
81904 #define USBHS_OTGSC_ASV(x)                       (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_ASV_SHIFT)) & USBHS_OTGSC_ASV_MASK)
81905 
81906 #define USBHS_OTGSC_BSV_MASK                     (0x800U)
81907 #define USBHS_OTGSC_BSV_SHIFT                    (11U)
81908 /*! BSV - B Session Valid */
81909 #define USBHS_OTGSC_BSV(x)                       (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSV_SHIFT)) & USBHS_OTGSC_BSV_MASK)
81910 
81911 #define USBHS_OTGSC_BSE_MASK                     (0x1000U)
81912 #define USBHS_OTGSC_BSE_SHIFT                    (12U)
81913 /*! BSE - B Session End */
81914 #define USBHS_OTGSC_BSE(x)                       (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSE_SHIFT)) & USBHS_OTGSC_BSE_MASK)
81915 
81916 #define USBHS_OTGSC_TOG_1MS_MASK                 (0x2000U)
81917 #define USBHS_OTGSC_TOG_1MS_SHIFT                (13U)
81918 /*! TOG_1MS - 1 Millisecond Timer Toggle */
81919 #define USBHS_OTGSC_TOG_1MS(x)                   (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_TOG_1MS_SHIFT)) & USBHS_OTGSC_TOG_1MS_MASK)
81920 
81921 #define USBHS_OTGSC_DPS_MASK                     (0x4000U)
81922 #define USBHS_OTGSC_DPS_SHIFT                    (14U)
81923 /*! DPS - Data Bus Pulsing Status */
81924 #define USBHS_OTGSC_DPS(x)                       (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_DPS_SHIFT)) & USBHS_OTGSC_DPS_MASK)
81925 
81926 #define USBHS_OTGSC_IDIS_MASK                    (0x10000U)
81927 #define USBHS_OTGSC_IDIS_SHIFT                   (16U)
81928 /*! IDIS - USB ID Interrupt Status */
81929 #define USBHS_OTGSC_IDIS(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_IDIS_SHIFT)) & USBHS_OTGSC_IDIS_MASK)
81930 
81931 #define USBHS_OTGSC_AVVIS_MASK                   (0x20000U)
81932 #define USBHS_OTGSC_AVVIS_SHIFT                  (17U)
81933 /*! AVVIS - A VBus Valid Interrupt Status */
81934 #define USBHS_OTGSC_AVVIS(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_AVVIS_SHIFT)) & USBHS_OTGSC_AVVIS_MASK)
81935 
81936 #define USBHS_OTGSC_ASVIS_MASK                   (0x40000U)
81937 #define USBHS_OTGSC_ASVIS_SHIFT                  (18U)
81938 /*! ASVIS - A Session Valid Interrupt Status */
81939 #define USBHS_OTGSC_ASVIS(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_ASVIS_SHIFT)) & USBHS_OTGSC_ASVIS_MASK)
81940 
81941 #define USBHS_OTGSC_BSVIS_MASK                   (0x80000U)
81942 #define USBHS_OTGSC_BSVIS_SHIFT                  (19U)
81943 /*! BSVIS - B Session Valid Interrupt Status */
81944 #define USBHS_OTGSC_BSVIS(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSVIS_SHIFT)) & USBHS_OTGSC_BSVIS_MASK)
81945 
81946 #define USBHS_OTGSC_BSEIS_MASK                   (0x100000U)
81947 #define USBHS_OTGSC_BSEIS_SHIFT                  (20U)
81948 /*! BSEIS - B Session End Interrupt Status */
81949 #define USBHS_OTGSC_BSEIS(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSEIS_SHIFT)) & USBHS_OTGSC_BSEIS_MASK)
81950 
81951 #define USBHS_OTGSC_STATUS_1MS_MASK              (0x200000U)
81952 #define USBHS_OTGSC_STATUS_1MS_SHIFT             (21U)
81953 /*! STATUS_1MS - 1 Millisecond Timer Interrupt Status */
81954 #define USBHS_OTGSC_STATUS_1MS(x)                (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_STATUS_1MS_SHIFT)) & USBHS_OTGSC_STATUS_1MS_MASK)
81955 
81956 #define USBHS_OTGSC_DPIS_MASK                    (0x400000U)
81957 #define USBHS_OTGSC_DPIS_SHIFT                   (22U)
81958 /*! DPIS - Data Pulse Interrupt Status */
81959 #define USBHS_OTGSC_DPIS(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_DPIS_SHIFT)) & USBHS_OTGSC_DPIS_MASK)
81960 
81961 #define USBHS_OTGSC_IDIE_MASK                    (0x1000000U)
81962 #define USBHS_OTGSC_IDIE_SHIFT                   (24U)
81963 /*! IDIE - USB ID Interrupt Enable */
81964 #define USBHS_OTGSC_IDIE(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_IDIE_SHIFT)) & USBHS_OTGSC_IDIE_MASK)
81965 
81966 #define USBHS_OTGSC_AVVIE_MASK                   (0x2000000U)
81967 #define USBHS_OTGSC_AVVIE_SHIFT                  (25U)
81968 /*! AVVIE - A VBus Valid Interrupt Enable */
81969 #define USBHS_OTGSC_AVVIE(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_AVVIE_SHIFT)) & USBHS_OTGSC_AVVIE_MASK)
81970 
81971 #define USBHS_OTGSC_ASVIE_MASK                   (0x4000000U)
81972 #define USBHS_OTGSC_ASVIE_SHIFT                  (26U)
81973 /*! ASVIE - A Session Valid Interrupt Enable */
81974 #define USBHS_OTGSC_ASVIE(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_ASVIE_SHIFT)) & USBHS_OTGSC_ASVIE_MASK)
81975 
81976 #define USBHS_OTGSC_BSVIE_MASK                   (0x8000000U)
81977 #define USBHS_OTGSC_BSVIE_SHIFT                  (27U)
81978 /*! BSVIE - B Session Valid Interrupt Enable */
81979 #define USBHS_OTGSC_BSVIE(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSVIE_SHIFT)) & USBHS_OTGSC_BSVIE_MASK)
81980 
81981 #define USBHS_OTGSC_BSEIE_MASK                   (0x10000000U)
81982 #define USBHS_OTGSC_BSEIE_SHIFT                  (28U)
81983 /*! BSEIE - B Session End Interrupt Enable */
81984 #define USBHS_OTGSC_BSEIE(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSEIE_SHIFT)) & USBHS_OTGSC_BSEIE_MASK)
81985 
81986 #define USBHS_OTGSC_EN_1MS_MASK                  (0x20000000U)
81987 #define USBHS_OTGSC_EN_1MS_SHIFT                 (29U)
81988 /*! EN_1MS - 1 Millisecond Timer Interrupt Enable */
81989 #define USBHS_OTGSC_EN_1MS(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_EN_1MS_SHIFT)) & USBHS_OTGSC_EN_1MS_MASK)
81990 
81991 #define USBHS_OTGSC_DPIE_MASK                    (0x40000000U)
81992 #define USBHS_OTGSC_DPIE_SHIFT                   (30U)
81993 /*! DPIE - Data Pulse Interrupt Enable */
81994 #define USBHS_OTGSC_DPIE(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_DPIE_SHIFT)) & USBHS_OTGSC_DPIE_MASK)
81995 /*! @} */
81996 
81997 /*! @name USBMODE - USB Device Mode */
81998 /*! @{ */
81999 
82000 #define USBHS_USBMODE_CM_MASK                    (0x3U)
82001 #define USBHS_USBMODE_CM_SHIFT                   (0U)
82002 /*! CM - Controller Mode
82003  *  0b00..Idle [Default for combination host/device]
82004  *  0b01..Reserved
82005  *  0b10..Device Controller [Default for device only controller]
82006  *  0b11..Host Controller [Default for host only controller]
82007  */
82008 #define USBHS_USBMODE_CM(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_USBMODE_CM_SHIFT)) & USBHS_USBMODE_CM_MASK)
82009 
82010 #define USBHS_USBMODE_ES_MASK                    (0x4U)
82011 #define USBHS_USBMODE_ES_SHIFT                   (2U)
82012 /*! ES - Endian Select
82013  *  0b0..Little Endian
82014  *  0b1..Big Endian
82015  */
82016 #define USBHS_USBMODE_ES(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_USBMODE_ES_SHIFT)) & USBHS_USBMODE_ES_MASK)
82017 
82018 #define USBHS_USBMODE_SLOM_MASK                  (0x8U)
82019 #define USBHS_USBMODE_SLOM_SHIFT                 (3U)
82020 /*! SLOM - Setup Lockout Mode
82021  *  0b0..Setup Lockouts On (default);
82022  *  0b1..Setup Lockouts Off
82023  */
82024 #define USBHS_USBMODE_SLOM(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_USBMODE_SLOM_SHIFT)) & USBHS_USBMODE_SLOM_MASK)
82025 
82026 #define USBHS_USBMODE_SDIS_MASK                  (0x10U)
82027 #define USBHS_USBMODE_SDIS_SHIFT                 (4U)
82028 /*! SDIS - Stream Disable Mode
82029  *  0b0..Inactive
82030  *  0b1..Active
82031  */
82032 #define USBHS_USBMODE_SDIS(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_USBMODE_SDIS_SHIFT)) & USBHS_USBMODE_SDIS_MASK)
82033 /*! @} */
82034 
82035 /*! @name ENDPTSETUPSTAT - Endpoint Setup Status */
82036 /*! @{ */
82037 
82038 #define USBHS_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK (0xFFFFU)
82039 #define USBHS_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT (0U)
82040 /*! ENDPTSETUPSTAT - Setup Endpoint Status */
82041 #define USBHS_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT)) & USBHS_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK)
82042 /*! @} */
82043 
82044 /*! @name ENDPTPRIME - Endpoint Prime */
82045 /*! @{ */
82046 
82047 #define USBHS_ENDPTPRIME_PERB_MASK               (0xFFU)
82048 #define USBHS_ENDPTPRIME_PERB_SHIFT              (0U)
82049 /*! PERB - Prime Endpoint Receive Buffer */
82050 #define USBHS_ENDPTPRIME_PERB(x)                 (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTPRIME_PERB_SHIFT)) & USBHS_ENDPTPRIME_PERB_MASK)
82051 
82052 #define USBHS_ENDPTPRIME_PETB_MASK               (0xFF0000U)
82053 #define USBHS_ENDPTPRIME_PETB_SHIFT              (16U)
82054 /*! PETB - Prime Endpoint Transmit Buffer */
82055 #define USBHS_ENDPTPRIME_PETB(x)                 (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTPRIME_PETB_SHIFT)) & USBHS_ENDPTPRIME_PETB_MASK)
82056 /*! @} */
82057 
82058 /*! @name ENDPTFLUSH - Endpoint Flush */
82059 /*! @{ */
82060 
82061 #define USBHS_ENDPTFLUSH_FERB_MASK               (0xFFU)
82062 #define USBHS_ENDPTFLUSH_FERB_SHIFT              (0U)
82063 /*! FERB - Flush Endpoint Receive Buffer */
82064 #define USBHS_ENDPTFLUSH_FERB(x)                 (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTFLUSH_FERB_SHIFT)) & USBHS_ENDPTFLUSH_FERB_MASK)
82065 
82066 #define USBHS_ENDPTFLUSH_FETB_MASK               (0xFF0000U)
82067 #define USBHS_ENDPTFLUSH_FETB_SHIFT              (16U)
82068 /*! FETB - Flush Endpoint Transmit Buffer */
82069 #define USBHS_ENDPTFLUSH_FETB(x)                 (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTFLUSH_FETB_SHIFT)) & USBHS_ENDPTFLUSH_FETB_MASK)
82070 /*! @} */
82071 
82072 /*! @name ENDPTSTAT - Endpoint Status */
82073 /*! @{ */
82074 
82075 #define USBHS_ENDPTSTAT_ERBR_MASK                (0xFFU)
82076 #define USBHS_ENDPTSTAT_ERBR_SHIFT               (0U)
82077 /*! ERBR - Endpoint Receive Buffer Ready */
82078 #define USBHS_ENDPTSTAT_ERBR(x)                  (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTSTAT_ERBR_SHIFT)) & USBHS_ENDPTSTAT_ERBR_MASK)
82079 
82080 #define USBHS_ENDPTSTAT_ETBR_MASK                (0xFF0000U)
82081 #define USBHS_ENDPTSTAT_ETBR_SHIFT               (16U)
82082 /*! ETBR - Endpoint Transmit Buffer Ready */
82083 #define USBHS_ENDPTSTAT_ETBR(x)                  (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTSTAT_ETBR_SHIFT)) & USBHS_ENDPTSTAT_ETBR_MASK)
82084 /*! @} */
82085 
82086 /*! @name ENDPTCOMPLETE - Endpoint Complete */
82087 /*! @{ */
82088 
82089 #define USBHS_ENDPTCOMPLETE_ERCE_MASK            (0xFFU)
82090 #define USBHS_ENDPTCOMPLETE_ERCE_SHIFT           (0U)
82091 /*! ERCE - Endpoint Receive Complete Event */
82092 #define USBHS_ENDPTCOMPLETE_ERCE(x)              (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCOMPLETE_ERCE_SHIFT)) & USBHS_ENDPTCOMPLETE_ERCE_MASK)
82093 
82094 #define USBHS_ENDPTCOMPLETE_ETCE_MASK            (0xFF0000U)
82095 #define USBHS_ENDPTCOMPLETE_ETCE_SHIFT           (16U)
82096 /*! ETCE - Endpoint Transmit Complete Event */
82097 #define USBHS_ENDPTCOMPLETE_ETCE(x)              (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCOMPLETE_ETCE_SHIFT)) & USBHS_ENDPTCOMPLETE_ETCE_MASK)
82098 /*! @} */
82099 
82100 /*! @name ENDPTCTRL0 - Endpoint Control 0 */
82101 /*! @{ */
82102 
82103 #define USBHS_ENDPTCTRL0_RXS_MASK                (0x1U)
82104 #define USBHS_ENDPTCTRL0_RXS_SHIFT               (0U)
82105 /*! RXS - RX Endpoint Stall
82106  *  0b0..Endpoint OK
82107  *  0b1..Endpoint stalled
82108  */
82109 #define USBHS_ENDPTCTRL0_RXS(x)                  (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL0_RXS_SHIFT)) & USBHS_ENDPTCTRL0_RXS_MASK)
82110 
82111 #define USBHS_ENDPTCTRL0_RXT_MASK                (0xCU)
82112 #define USBHS_ENDPTCTRL0_RXT_SHIFT               (2U)
82113 /*! RXT - RX Endpoint Type
82114  *  0b00..Control
82115  */
82116 #define USBHS_ENDPTCTRL0_RXT(x)                  (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL0_RXT_SHIFT)) & USBHS_ENDPTCTRL0_RXT_MASK)
82117 
82118 #define USBHS_ENDPTCTRL0_RXE_MASK                (0x80U)
82119 #define USBHS_ENDPTCTRL0_RXE_SHIFT               (7U)
82120 /*! RXE - RX Endpoint Enable
82121  *  0b0..Disabled
82122  *  0b1..Enabled
82123  */
82124 #define USBHS_ENDPTCTRL0_RXE(x)                  (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL0_RXE_SHIFT)) & USBHS_ENDPTCTRL0_RXE_MASK)
82125 
82126 #define USBHS_ENDPTCTRL0_TXS_MASK                (0x10000U)
82127 #define USBHS_ENDPTCTRL0_TXS_SHIFT               (16U)
82128 /*! TXS - TX Endpoint Stall
82129  *  0b0..Endpoint OK
82130  *  0b1..Endpoint stalled
82131  */
82132 #define USBHS_ENDPTCTRL0_TXS(x)                  (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL0_TXS_SHIFT)) & USBHS_ENDPTCTRL0_TXS_MASK)
82133 
82134 #define USBHS_ENDPTCTRL0_TXT_MASK                (0xC0000U)
82135 #define USBHS_ENDPTCTRL0_TXT_SHIFT               (18U)
82136 /*! TXT - TX Endpoint Type
82137  *  0b00..Control
82138  */
82139 #define USBHS_ENDPTCTRL0_TXT(x)                  (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL0_TXT_SHIFT)) & USBHS_ENDPTCTRL0_TXT_MASK)
82140 
82141 #define USBHS_ENDPTCTRL0_TXE_MASK                (0x800000U)
82142 #define USBHS_ENDPTCTRL0_TXE_SHIFT               (23U)
82143 /*! TXE - TX Endpoint Enable
82144  *  0b0..Disabled
82145  *  0b1..Enabled
82146  */
82147 #define USBHS_ENDPTCTRL0_TXE(x)                  (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL0_TXE_SHIFT)) & USBHS_ENDPTCTRL0_TXE_MASK)
82148 /*! @} */
82149 
82150 /*! @name ENDPTCTRL - Endpoint Control 1..Endpoint Control 7 */
82151 /*! @{ */
82152 
82153 #define USBHS_ENDPTCTRL_RXS_MASK                 (0x1U)
82154 #define USBHS_ENDPTCTRL_RXS_SHIFT                (0U)
82155 /*! RXS - RX Endpoint Stall
82156  *  0b0..Endpoint OK
82157  *  0b1..Endpoint stalled
82158  */
82159 #define USBHS_ENDPTCTRL_RXS(x)                   (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL_RXS_SHIFT)) & USBHS_ENDPTCTRL_RXS_MASK)
82160 
82161 #define USBHS_ENDPTCTRL_RXD_MASK                 (0x2U)
82162 #define USBHS_ENDPTCTRL_RXD_SHIFT                (1U)
82163 /*! RXD - RX Endpoint Data Sink
82164  *  0b0..Dual Port Memory Buffer/DMA Engine
82165  */
82166 #define USBHS_ENDPTCTRL_RXD(x)                   (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL_RXD_SHIFT)) & USBHS_ENDPTCTRL_RXD_MASK)
82167 
82168 #define USBHS_ENDPTCTRL_RXT_MASK                 (0xCU)
82169 #define USBHS_ENDPTCTRL_RXT_SHIFT                (2U)
82170 /*! RXT - RX Endpoint Type
82171  *  0b00..Control
82172  *  0b01..Isochronous
82173  *  0b10..Bulk
82174  *  0b11..Interrupt
82175  */
82176 #define USBHS_ENDPTCTRL_RXT(x)                   (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL_RXT_SHIFT)) & USBHS_ENDPTCTRL_RXT_MASK)
82177 
82178 #define USBHS_ENDPTCTRL_RXI_MASK                 (0x20U)
82179 #define USBHS_ENDPTCTRL_RXI_SHIFT                (5U)
82180 /*! RXI - RX Data Toggle Inhibit
82181  *  0b0..Disabled
82182  *  0b1..Enabled
82183  */
82184 #define USBHS_ENDPTCTRL_RXI(x)                   (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL_RXI_SHIFT)) & USBHS_ENDPTCTRL_RXI_MASK)
82185 
82186 #define USBHS_ENDPTCTRL_RXR_MASK                 (0x40U)
82187 #define USBHS_ENDPTCTRL_RXR_SHIFT                (6U)
82188 /*! RXR - RX Data Toggle Reset (WS)
82189  *  0b1..Reset PID sequence
82190  */
82191 #define USBHS_ENDPTCTRL_RXR(x)                   (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL_RXR_SHIFT)) & USBHS_ENDPTCTRL_RXR_MASK)
82192 
82193 #define USBHS_ENDPTCTRL_RXE_MASK                 (0x80U)
82194 #define USBHS_ENDPTCTRL_RXE_SHIFT                (7U)
82195 /*! RXE - RX Endpoint Enable
82196  *  0b0..Disabled
82197  *  0b1..Enabled
82198  */
82199 #define USBHS_ENDPTCTRL_RXE(x)                   (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL_RXE_SHIFT)) & USBHS_ENDPTCTRL_RXE_MASK)
82200 
82201 #define USBHS_ENDPTCTRL_TXS_MASK                 (0x10000U)
82202 #define USBHS_ENDPTCTRL_TXS_SHIFT                (16U)
82203 /*! TXS - TX Endpoint Stall
82204  *  0b0..Endpoint OK
82205  *  0b1..Endpoint stalled
82206  */
82207 #define USBHS_ENDPTCTRL_TXS(x)                   (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL_TXS_SHIFT)) & USBHS_ENDPTCTRL_TXS_MASK)
82208 
82209 #define USBHS_ENDPTCTRL_TXD_MASK                 (0x20000U)
82210 #define USBHS_ENDPTCTRL_TXD_SHIFT                (17U)
82211 /*! TXD - TX Endpoint Data Source
82212  *  0b0..Dual Port Memory Buffer/DMA Engine
82213  */
82214 #define USBHS_ENDPTCTRL_TXD(x)                   (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL_TXD_SHIFT)) & USBHS_ENDPTCTRL_TXD_MASK)
82215 
82216 #define USBHS_ENDPTCTRL_TXT_MASK                 (0xC0000U)
82217 #define USBHS_ENDPTCTRL_TXT_SHIFT                (18U)
82218 /*! TXT - TX Endpoint Type
82219  *  0b00..Control
82220  *  0b01..Isochronous
82221  *  0b10..Bulk
82222  *  0b11..Interrupt
82223  */
82224 #define USBHS_ENDPTCTRL_TXT(x)                   (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL_TXT_SHIFT)) & USBHS_ENDPTCTRL_TXT_MASK)
82225 
82226 #define USBHS_ENDPTCTRL_TXI_MASK                 (0x200000U)
82227 #define USBHS_ENDPTCTRL_TXI_SHIFT                (21U)
82228 /*! TXI - TX Data Toggle Inhibit
82229  *  0b0..PID sequencing enabled
82230  *  0b1..PID sequencing disabled
82231  */
82232 #define USBHS_ENDPTCTRL_TXI(x)                   (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL_TXI_SHIFT)) & USBHS_ENDPTCTRL_TXI_MASK)
82233 
82234 #define USBHS_ENDPTCTRL_TXR_MASK                 (0x400000U)
82235 #define USBHS_ENDPTCTRL_TXR_SHIFT                (22U)
82236 /*! TXR - TX Data Toggle Reset (WS)
82237  *  0b1..Reset PID sequence
82238  */
82239 #define USBHS_ENDPTCTRL_TXR(x)                   (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL_TXR_SHIFT)) & USBHS_ENDPTCTRL_TXR_MASK)
82240 
82241 #define USBHS_ENDPTCTRL_TXE_MASK                 (0x800000U)
82242 #define USBHS_ENDPTCTRL_TXE_SHIFT                (23U)
82243 /*! TXE - TX Endpoint Enable
82244  *  0b0..Disabled
82245  *  0b1..Enabled
82246  */
82247 #define USBHS_ENDPTCTRL_TXE(x)                   (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL_TXE_SHIFT)) & USBHS_ENDPTCTRL_TXE_MASK)
82248 /*! @} */
82249 
82250 /* The count of USBHS_ENDPTCTRL */
82251 #define USBHS_ENDPTCTRL_COUNT                    (7U)
82252 
82253 
82254 /*!
82255  * @}
82256  */ /* end of group USBHS_Register_Masks */
82257 
82258 
82259 /* USBHS - Peripheral instance base addresses */
82260 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
82261   /** Peripheral USBHS1__USBC base address */
82262   #define USBHS1__USBC_BASE                        (0x5010B000u)
82263   /** Peripheral USBHS1__USBC base address */
82264   #define USBHS1__USBC_BASE_NS                     (0x4010B000u)
82265   /** Peripheral USBHS1__USBC base pointer */
82266   #define USBHS1__USBC                             ((USBHS_Type *)USBHS1__USBC_BASE)
82267   /** Peripheral USBHS1__USBC base pointer */
82268   #define USBHS1__USBC_NS                          ((USBHS_Type *)USBHS1__USBC_BASE_NS)
82269   /** Array initializer of USBHS peripheral base addresses */
82270   #define USBHS_BASE_ADDRS                         { USBHS1__USBC_BASE }
82271   /** Array initializer of USBHS peripheral base pointers */
82272   #define USBHS_BASE_PTRS                          { USBHS1__USBC }
82273   /** Array initializer of USBHS peripheral base addresses */
82274   #define USBHS_BASE_ADDRS_NS                      { USBHS1__USBC_BASE_NS }
82275   /** Array initializer of USBHS peripheral base pointers */
82276   #define USBHS_BASE_PTRS_NS                       { USBHS1__USBC_NS }
82277 #else
82278   /** Peripheral USBHS1__USBC base address */
82279   #define USBHS1__USBC_BASE                        (0x4010B000u)
82280   /** Peripheral USBHS1__USBC base pointer */
82281   #define USBHS1__USBC                             ((USBHS_Type *)USBHS1__USBC_BASE)
82282   /** Array initializer of USBHS peripheral base addresses */
82283   #define USBHS_BASE_ADDRS                         { USBHS1__USBC_BASE }
82284   /** Array initializer of USBHS peripheral base pointers */
82285   #define USBHS_BASE_PTRS                          { USBHS1__USBC }
82286 #endif
82287 /** Interrupt vectors for the USBHS peripheral type */
82288 #define USBHS_IRQS                               { USB1_HS_IRQn }
82289 /* Backward compatibility */
82290 #define GPTIMER0CTL                              GPTIMER0CTRL
82291 #define GPTIMER1CTL                              GPTIMER1CTRL
82292 #define USB_SBUSCFG                              SBUSCFG
82293 #define EPLISTADDR                               ENDPTLISTADDR
82294 #define EPSETUPSR                                ENDPTSETUPSTAT
82295 #define EPPRIME                                  ENDPTPRIME
82296 #define EPFLUSH                                  ENDPTFLUSH
82297 #define EPSR                                     ENDPTSTAT
82298 #define EPCOMPLETE                               ENDPTCOMPLETE
82299 #define EPCR                                     ENDPTCTRL
82300 #define EPCR0                                    ENDPTCTRL0
82301 #define USBHS_GPTIMER0CTL_GPTCNT_MASK            USBHS_GPTIMER0CTRL_GPTCNT_MASK
82302 #define USBHS_GPTIMER0CTL_GPTCNT_SHIFT           USBHS_GPTIMER0CTRL_GPTCNT_SHIFT
82303 #define USBHS_GPTIMER0CTL_GPTCNT(x)              USBHS_GPTIMER0CTRL_GPTCNT(x)
82304 #define USBHS_GPTIMER0CTL_MODE_MASK              USBHS_GPTIMER0CTRL_GPTMODE_MASK
82305 #define USBHS_GPTIMER0CTL_MODE_SHIFT             USBHS_GPTIMER0CTRL_GPTMODE_SHIFT
82306 #define USBHS_GPTIMER0CTL_MODE(x)                USBHS_GPTIMER0CTRL_GPTMODE(x)
82307 #define USBHS_GPTIMER0CTL_RST_MASK               USBHS_GPTIMER0CTRL_GPTRST_MASK
82308 #define USBHS_GPTIMER0CTL_RST_SHIFT              USBHS_GPTIMER0CTRL_GPTRST_SHIFT
82309 #define USBHS_GPTIMER0CTL_RST(x)                 USBHS_GPTIMER0CTRL_GPTRST(x)
82310 #define USBHS_GPTIMER0CTL_RUN_MASK               USBHS_GPTIMER0CTRL_GPTRUN_MASK
82311 #define USBHS_GPTIMER0CTL_RUN_SHIFT              USBHS_GPTIMER0CTRL_GPTRUN_SHIFT
82312 #define USBHS_GPTIMER0CTL_RUN(x)                 USBHS_GPTIMER0CTRL_GPTRUN(x)
82313 #define USBHS_GPTIMER1CTL_GPTCNT_MASK            USBHS_GPTIMER1CTRL_GPTCNT_MASK
82314 #define USBHS_GPTIMER1CTL_GPTCNT_SHIFT           USBHS_GPTIMER1CTRL_GPTCNT_SHIFT
82315 #define USBHS_GPTIMER1CTL_GPTCNT(x)              USBHS_GPTIMER1CTRL_GPTCNT(x)
82316 #define USBHS_GPTIMER1CTL_MODE_MASK              USBHS_GPTIMER1CTRL_GPTMODE_MASK
82317 #define USBHS_GPTIMER1CTL_MODE_SHIFT             USBHS_GPTIMER1CTRL_GPTMODE_SHIFT
82318 #define USBHS_GPTIMER1CTL_MODE(x)                USBHS_GPTIMER1CTRL_GPTMODE(x)
82319 #define USBHS_GPTIMER1CTL_RST_MASK               USBHS_GPTIMER1CTRL_GPTRST_MASK
82320 #define USBHS_GPTIMER1CTL_RST_SHIFT              USBHS_GPTIMER1CTRL_GPTRST_SHIFT
82321 #define USBHS_GPTIMER1CTL_RST(x)                 USBHS_GPTIMER1CTRL_GPTRST(x)
82322 #define USBHS_GPTIMER1CTL_RUN_MASK               USBHS_GPTIMER1CTRL_GPTRUN_MASK
82323 #define USBHS_GPTIMER1CTL_RUN_SHIFT              USBHS_GPTIMER1CTRL_GPTRUN_SHIFT
82324 #define USBHS_GPTIMER1CTL_RUN(x)                 USBHS_GPTIMER1CTRL_GPTRUN(x)
82325 #define USBHS_USB_SBUSCFG_BURSTMODE_MASK         USBHS_SBUSCFG_AHBBRST_MASK
82326 #define USBHS_USB_SBUSCFG_BURSTMODE_SHIFT        USBHS_SBUSCFG_AHBBRST_SHIFT
82327 #define USBHS_USB_SBUSCFG_BURSTMODE(x)           USBHS_SBUSCFG_AHBBRST(x)
82328 #define USBHS_USBCMD_FS_MASK                     USBHS_USBCMD_FS_1_MASK
82329 #define USBHS_USBCMD_FS_SHIFT                    USBHS_USBCMD_FS_1_SHIFT
82330 #define USBHS_USBCMD_FS(x)                       USBHS_USBCMD_FS_1(x)
82331 #define USBHS_EPLISTADDR_EPBASE_MASK             USBHS_ENDPTLISTADDR_EPBASE_MASK
82332 #define USBHS_EPLISTADDR_EPBASE_SHIFT            USBHS_ENDPTLISTADDR_EPBASE_SHIFT
82333 #define USBHS_EPLISTADDR_EPBASE(x)               USBHS_ENDPTLISTADDR_EPBASE(x)
82334 #define USBHS_EPSETUPSR_EPSETUPSTAT_MASK         USBHS_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK
82335 #define USBHS_EPSETUPSR_EPSETUPSTAT_SHIFT        USBHS_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT
82336 #define USBHS_EPSETUPSR_EPSETUPSTAT(x)           USBHS_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x)
82337 #define USBHS_EPPRIME_PERB_MASK                  USBHS_ENDPTPRIME_PERB_MASK
82338 #define USBHS_EPPRIME_PERB_SHIFT                 USBHS_ENDPTPRIME_PERB_SHIFT
82339 #define USBHS_EPPRIME_PERB(x)                    USBHS_ENDPTPRIME_PERB(x)
82340 #define USBHS_EPPRIME_PETB_MASK                  USBHS_ENDPTPRIME_PETB_MASK
82341 #define USBHS_EPPRIME_PETB_SHIFT                 USBHS_ENDPTPRIME_PETB_SHIFT
82342 #define USBHS_EPPRIME_PETB(x)                    USBHS_ENDPTPRIME_PETB(x)
82343 #define USBHS_EPFLUSH_FERB_MASK                  USBHS_ENDPTFLUSH_FERB_MASK
82344 #define USBHS_EPFLUSH_FERB_SHIFT                 USBHS_ENDPTFLUSH_FERB_SHIFT
82345 #define USBHS_EPFLUSH_FERB(x)                    USBHS_ENDPTFLUSH_FERB(x)
82346 #define USBHS_EPFLUSH_FETB_MASK                  USBHS_ENDPTFLUSH_FETB_MASK
82347 #define USBHS_EPFLUSH_FETB_SHIFT                 USBHS_ENDPTFLUSH_FETB_SHIFT
82348 #define USBHS_EPFLUSH_FETB(x)                    USBHS_ENDPTFLUSH_FETB(x)
82349 #define USBHS_EPSR_ERBR_MASK                     USBHS_ENDPTSTAT_ERBR_MASK
82350 #define USBHS_EPSR_ERBR_SHIFT                    USBHS_ENDPTSTAT_ERBR_SHIFT
82351 #define USBHS_EPSR_ERBR(x)                       USBHS_ENDPTSTAT_ERBR(x)
82352 #define USBHS_EPSR_ETBR_MASK                     USBHS_ENDPTSTAT_ETBR_MASK
82353 #define USBHS_EPSR_ETBR_SHIFT                    USBHS_ENDPTSTAT_ETBR_SHIFT
82354 #define USBHS_EPSR_ETBR(x)                       USBHS_ENDPTSTAT_ETBR(x)
82355 #define USBHS_EPCOMPLETE_ERCE_MASK               USBHS_ENDPTCOMPLETE_ERCE_MASK
82356 #define USBHS_EPCOMPLETE_ERCE_SHIFT              USBHS_ENDPTCOMPLETE_ERCE_SHIFT
82357 #define USBHS_EPCOMPLETE_ERCE(x)                 USBHS_ENDPTCOMPLETE_ERCE(x)
82358 #define USBHS_EPCOMPLETE_ETCE_MASK               USBHS_ENDPTCOMPLETE_ETCE_MASK
82359 #define USBHS_EPCOMPLETE_ETCE_SHIFT              USBHS_ENDPTCOMPLETE_ETCE_SHIFT
82360 #define USBHS_EPCOMPLETE_ETCE(x)                 USBHS_ENDPTCOMPLETE_ETCE(x)
82361 #define USBHS_EPCR0_RXS_MASK                     USBHS_ENDPTCTRL0_RXS_MASK
82362 #define USBHS_EPCR0_RXS_SHIFT                    USBHS_ENDPTCTRL0_RXS_SHIFT
82363 #define USBHS_EPCR0_RXS(x)                       USBHS_ENDPTCTRL0_RXS(x)
82364 #define USBHS_EPCR0_RXT_MASK                     USBHS_ENDPTCTRL0_RXT_MASK
82365 #define USBHS_EPCR0_RXT_SHIFT                    USBHS_ENDPTCTRL0_RXT_SHIFT
82366 #define USBHS_EPCR0_RXT(x)                       USBHS_ENDPTCTRL0_RXT(x)
82367 #define USBHS_EPCR0_RXE_MASK                     USBHS_ENDPTCTRL0_RXE_MASK
82368 #define USBHS_EPCR0_RXE_SHIFT                    USBHS_ENDPTCTRL0_RXE_SHIFT
82369 #define USBHS_EPCR0_RXE(x)                       USBHS_ENDPTCTRL0_RXE(x)
82370 #define USBHS_EPCR0_TXS_MASK                     USBHS_ENDPTCTRL0_TXS_MASK
82371 #define USBHS_EPCR0_TXS_SHIFT                    USBHS_ENDPTCTRL0_TXS_SHIFT
82372 #define USBHS_EPCR0_TXS(x)                       USBHS_ENDPTCTRL0_TXS(x)
82373 #define USBHS_EPCR0_TXT_MASK                     USBHS_ENDPTCTRL0_TXT_MASK
82374 #define USBHS_EPCR0_TXT_SHIFT                    USBHS_ENDPTCTRL0_TXT_SHIFT
82375 #define USBHS_EPCR0_TXT(x)                       USBHS_ENDPTCTRL0_TXT(x)
82376 #define USBHS_EPCR0_TXE_MASK                     USBHS_ENDPTCTRL0_TXE_MASK
82377 #define USBHS_EPCR0_TXE_SHIFT                    USBHS_ENDPTCTRL0_TXE_SHIFT
82378 #define USBHS_EPCR0_TXE(x)                       USBHS_ENDPTCTRL0_TXE(x)
82379 #define USBHS_EPCR_RXS_MASK                      USBHS_ENDPTCTRL_RXS_MASK
82380 #define USBHS_EPCR_RXS_SHIFT                     USBHS_ENDPTCTRL_RXS_SHIFT
82381 #define USBHS_EPCR_RXS(x)                        USBHS_ENDPTCTRL_RXS(x)
82382 #define USBHS_EPCR_RXD_MASK                      USBHS_ENDPTCTRL_RXD_MASK
82383 #define USBHS_EPCR_RXD_SHIFT                     USBHS_ENDPTCTRL_RXD_SHIFT
82384 #define USBHS_EPCR_RXD(x)                        USBHS_ENDPTCTRL_RXD(x)
82385 #define USBHS_EPCR_RXT_MASK                      USBHS_ENDPTCTRL_RXT_MASK
82386 #define USBHS_EPCR_RXT_SHIFT                     USBHS_ENDPTCTRL_RXT_SHIFT
82387 #define USBHS_EPCR_RXT(x)                        USBHS_ENDPTCTRL_RXT(x)
82388 #define USBHS_EPCR_RXI_MASK                      USBHS_ENDPTCTRL_RXI_MASK
82389 #define USBHS_EPCR_RXI_SHIFT                     USBHS_ENDPTCTRL_RXI_SHIFT
82390 #define USBHS_EPCR_RXI(x)                        USBHS_ENDPTCTRL_RXI(x)
82391 #define USBHS_EPCR_RXR_MASK                      USBHS_ENDPTCTRL_RXR_MASK
82392 #define USBHS_EPCR_RXR_SHIFT                     USBHS_ENDPTCTRL_RXR_SHIFT
82393 #define USBHS_EPCR_RXR(x)                        USBHS_ENDPTCTRL_RXR(x)
82394 #define USBHS_EPCR_RXE_MASK                      USBHS_ENDPTCTRL_RXE_MASK
82395 #define USBHS_EPCR_RXE_SHIFT                     USBHS_ENDPTCTRL_RXE_SHIFT
82396 #define USBHS_EPCR_RXE(x)                        USBHS_ENDPTCTRL_RXE(x)
82397 #define USBHS_EPCR_TXS_MASK                      USBHS_ENDPTCTRL_TXS_MASK
82398 #define USBHS_EPCR_TXS_SHIFT                     USBHS_ENDPTCTRL_TXS_SHIFT
82399 #define USBHS_EPCR_TXS(x)                        USBHS_ENDPTCTRL_TXS(x)
82400 #define USBHS_EPCR_TXD_MASK                      USBHS_ENDPTCTRL_TXD_MASK
82401 #define USBHS_EPCR_TXD_SHIFT                     USBHS_ENDPTCTRL_TXD_SHIFT
82402 #define USBHS_EPCR_TXD(x)                        USBHS_ENDPTCTRL_TXD(x)
82403 #define USBHS_EPCR_TXT_MASK                      USBHS_ENDPTCTRL_TXT_MASK
82404 #define USBHS_EPCR_TXT_SHIFT                     USBHS_ENDPTCTRL_TXT_SHIFT
82405 #define USBHS_EPCR_TXT(x)                        USBHS_ENDPTCTRL_TXT(x)
82406 #define USBHS_EPCR_TXI_MASK                      USBHS_ENDPTCTRL_TXI_MASK
82407 #define USBHS_EPCR_TXI_SHIFT                     USBHS_ENDPTCTRL_TXI_SHIFT
82408 #define USBHS_EPCR_TXI(x)                        USBHS_ENDPTCTRL_TXI(x)
82409 #define USBHS_EPCR_TXR_MASK                      USBHS_ENDPTCTRL_TXR_MASK
82410 #define USBHS_EPCR_TXR_SHIFT                     USBHS_ENDPTCTRL_TXR_SHIFT
82411 #define USBHS_EPCR_TXR(x)                        USBHS_ENDPTCTRL_TXR(x)
82412 #define USBHS_EPCR_TXE_MASK                      USBHS_ENDPTCTRL_TXE_MASK
82413 #define USBHS_EPCR_TXE_SHIFT                     USBHS_ENDPTCTRL_TXE_SHIFT
82414 #define USBHS_EPCR_TXE(x)                        USBHS_ENDPTCTRL_TXE(x)
82415 #define USBHS_EPCR_COUNT                         USBHS_ENDPTCTRL_COUNT
82416 #define USBHS_PORTSC1_WKDS_MASK                  USBHS_PORTSC1_WKDC_MASK
82417 #define USBHS_PORTSC1_WKDS_SHIFT                 USBHS_PORTSC1_WKDC_SHIFT
82418 #define USBHS_PORTSC1_WKDS(x)                    USBHS_PORTSC1_WKDC(x)
82419 #define USBHS_IRQHandler                         USB1_HS_IRQHandler
82420 
82421 
82422 /*!
82423  * @}
82424  */ /* end of group USBHS_Peripheral_Access_Layer */
82425 
82426 
82427 /* ----------------------------------------------------------------------------
82428    -- USBHSDCD Peripheral Access Layer
82429    ---------------------------------------------------------------------------- */
82430 
82431 /*!
82432  * @addtogroup USBHSDCD_Peripheral_Access_Layer USBHSDCD Peripheral Access Layer
82433  * @{
82434  */
82435 
82436 /** USBHSDCD - Register Layout Typedef */
82437 typedef struct {
82438   __IO uint32_t CONTROL;                           /**< Control, offset: 0x0 */
82439   __IO uint32_t CLOCK;                             /**< Clock, offset: 0x4 */
82440   __I  uint32_t STATUS;                            /**< Status, offset: 0x8 */
82441   __IO uint32_t SIGNAL_OVERRIDE;                   /**< Signal Override, offset: 0xC */
82442   __IO uint32_t TIMER0;                            /**< TIMER0, offset: 0x10 */
82443   __IO uint32_t TIMER1;                            /**< TIMER1, offset: 0x14 */
82444   union {                                          /* offset: 0x18 */
82445     __IO uint32_t TIMER2_BC11;                       /**< TIMER2_BC11, offset: 0x18 */
82446     __IO uint32_t TIMER2_BC12;                       /**< TIMER2_BC12, offset: 0x18 */
82447   };
82448 } USBHSDCD_Type;
82449 
82450 /* ----------------------------------------------------------------------------
82451    -- USBHSDCD Register Masks
82452    ---------------------------------------------------------------------------- */
82453 
82454 /*!
82455  * @addtogroup USBHSDCD_Register_Masks USBHSDCD Register Masks
82456  * @{
82457  */
82458 
82459 /*! @name CONTROL - Control */
82460 /*! @{ */
82461 
82462 #define USBHSDCD_CONTROL_IACK_MASK               (0x1U)
82463 #define USBHSDCD_CONTROL_IACK_SHIFT              (0U)
82464 /*! IACK - Interrupt Acknowledge
82465  *  0b0..Do not clear the interrupt.
82466  *  0b1..Clear the IF field (interrupt flag).
82467  */
82468 #define USBHSDCD_CONTROL_IACK(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IACK_SHIFT)) & USBHSDCD_CONTROL_IACK_MASK)
82469 
82470 #define USBHSDCD_CONTROL_IF_MASK                 (0x100U)
82471 #define USBHSDCD_CONTROL_IF_SHIFT                (8U)
82472 /*! IF - Interrupt Flag
82473  *  0b0..No interrupt is pending.
82474  *  0b1..An interrupt is pending.
82475  */
82476 #define USBHSDCD_CONTROL_IF(x)                   (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IF_SHIFT)) & USBHSDCD_CONTROL_IF_MASK)
82477 
82478 #define USBHSDCD_CONTROL_IE_MASK                 (0x10000U)
82479 #define USBHSDCD_CONTROL_IE_SHIFT                (16U)
82480 /*! IE - Interrupt Enable
82481  *  0b0..Disable interrupts to the system.
82482  *  0b1..Enable interrupts to the system.
82483  */
82484 #define USBHSDCD_CONTROL_IE(x)                   (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IE_SHIFT)) & USBHSDCD_CONTROL_IE_MASK)
82485 
82486 #define USBHSDCD_CONTROL_BC12_MASK               (0x20000U)
82487 #define USBHSDCD_CONTROL_BC12_SHIFT              (17U)
82488 /*! BC12 - Battery Charging Revision 1.2 Compatibility
82489  *  0b0..Compatible with BC1.1
82490  *  0b1..Compatible with BC1.2 (default)
82491  */
82492 #define USBHSDCD_CONTROL_BC12(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_BC12_SHIFT)) & USBHSDCD_CONTROL_BC12_MASK)
82493 
82494 #define USBHSDCD_CONTROL_START_MASK              (0x1000000U)
82495 #define USBHSDCD_CONTROL_START_SHIFT             (24U)
82496 /*! START - Start Change Detection Sequence
82497  *  0b0..Do not start the sequence. Writes of this value have no effect.
82498  *  0b1..Initiate the charger detection sequence. If the sequence is already running, writes of this value have no effect.
82499  */
82500 #define USBHSDCD_CONTROL_START(x)                (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_START_SHIFT)) & USBHSDCD_CONTROL_START_MASK)
82501 
82502 #define USBHSDCD_CONTROL_SR_MASK                 (0x2000000U)
82503 #define USBHSDCD_CONTROL_SR_SHIFT                (25U)
82504 /*! SR - Software Reset
82505  *  0b0..Do not perform a software reset.
82506  *  0b1..Perform a software reset.
82507  */
82508 #define USBHSDCD_CONTROL_SR(x)                   (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_SR_SHIFT)) & USBHSDCD_CONTROL_SR_MASK)
82509 /*! @} */
82510 
82511 /*! @name CLOCK - Clock */
82512 /*! @{ */
82513 
82514 #define USBHSDCD_CLOCK_CLOCK_UNIT_MASK           (0x1U)
82515 #define USBHSDCD_CLOCK_CLOCK_UNIT_SHIFT          (0U)
82516 /*! CLOCK_UNIT - Unit of Measurement Encoding for Clock Speed
82517  *  0b0..kHz Speed (between 4 kHz and 1023 kHz)
82518  *  0b1..MHz Speed (between 1 MHz and 1023 MHz)
82519  */
82520 #define USBHSDCD_CLOCK_CLOCK_UNIT(x)             (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CLOCK_CLOCK_UNIT_SHIFT)) & USBHSDCD_CLOCK_CLOCK_UNIT_MASK)
82521 
82522 #define USBHSDCD_CLOCK_CLOCK_SPEED_MASK          (0xFFCU)
82523 #define USBHSDCD_CLOCK_CLOCK_SPEED_SHIFT         (2U)
82524 /*! CLOCK_SPEED - Numerical Value of Clock Speed in Binary */
82525 #define USBHSDCD_CLOCK_CLOCK_SPEED(x)            (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CLOCK_CLOCK_SPEED_SHIFT)) & USBHSDCD_CLOCK_CLOCK_SPEED_MASK)
82526 /*! @} */
82527 
82528 /*! @name STATUS - Status */
82529 /*! @{ */
82530 
82531 #define USBHSDCD_STATUS_SEQ_RES_MASK             (0x30000U)
82532 #define USBHSDCD_STATUS_SEQ_RES_SHIFT            (16U)
82533 /*! SEQ_RES - Charger Detection Sequence Results
82534  *  0b00..No results to report.
82535  *  0b01..Attached to an SDP. Must comply with USB 2.0 by drawing only 2.5 mA (max) until connected.
82536  *  0b10..Attached to a charging port. The exact meaning depends on the STATUS[SEQ_STAT] field (value 0: Attached
82537  *        to either a CDP or a DCP. The charger type detection has not completed. value 1: Attached to a CDP. The
82538  *        charger type detection has completed.)
82539  *  0b11..Attached to a DCP.
82540  */
82541 #define USBHSDCD_STATUS_SEQ_RES(x)               (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_SEQ_RES_SHIFT)) & USBHSDCD_STATUS_SEQ_RES_MASK)
82542 
82543 #define USBHSDCD_STATUS_SEQ_STAT_MASK            (0xC0000U)
82544 #define USBHSDCD_STATUS_SEQ_STAT_SHIFT           (18U)
82545 /*! SEQ_STAT - Charger Detection Sequence Status
82546  *  0b00..The module is either not enabled, or the module is enabled but the data pins have not yet been detected.
82547  *  0b01..Data pin contact detection is complete.
82548  *  0b10..Charging port detection is complete.
82549  *  0b11..Charger type detection is complete.
82550  */
82551 #define USBHSDCD_STATUS_SEQ_STAT(x)              (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_SEQ_STAT_SHIFT)) & USBHSDCD_STATUS_SEQ_STAT_MASK)
82552 
82553 #define USBHSDCD_STATUS_ERR_MASK                 (0x100000U)
82554 #define USBHSDCD_STATUS_ERR_SHIFT                (20U)
82555 /*! ERR - Error Flag
82556  *  0b0..No sequence errors.
82557  *  0b1..Error in the detection sequence.
82558  */
82559 #define USBHSDCD_STATUS_ERR(x)                   (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_ERR_SHIFT)) & USBHSDCD_STATUS_ERR_MASK)
82560 
82561 #define USBHSDCD_STATUS_TO_MASK                  (0x200000U)
82562 #define USBHSDCD_STATUS_TO_SHIFT                 (21U)
82563 /*! TO - Timeout Flag
82564  *  0b0..The detection sequence is not running for over 1 s.
82565  *  0b1..It is over 1 s since the data pin contact was detected and debounced.
82566  */
82567 #define USBHSDCD_STATUS_TO(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_TO_SHIFT)) & USBHSDCD_STATUS_TO_MASK)
82568 
82569 #define USBHSDCD_STATUS_ACTIVE_MASK              (0x400000U)
82570 #define USBHSDCD_STATUS_ACTIVE_SHIFT             (22U)
82571 /*! ACTIVE - Active Status Indicator
82572  *  0b0..The sequence is not running.
82573  *  0b1..The sequence is running.
82574  */
82575 #define USBHSDCD_STATUS_ACTIVE(x)                (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_ACTIVE_SHIFT)) & USBHSDCD_STATUS_ACTIVE_MASK)
82576 /*! @} */
82577 
82578 /*! @name SIGNAL_OVERRIDE - Signal Override */
82579 /*! @{ */
82580 
82581 #define USBHSDCD_SIGNAL_OVERRIDE_PS_MASK         (0x7U)
82582 #define USBHSDCD_SIGNAL_OVERRIDE_PS_SHIFT        (0U)
82583 /*! PS - Phase Selection
82584  *  0b000..No overrides. Field must remain at this value during normal USB data communication to prevent
82585  *         unexpected conditions on USB_DP and USB_DM pins. (Default)
82586  *  0b001..Reserved, not for customer use.
82587  *  0b010..Enables VDP_SRC voltage source for the USB_DP pin and IDM_SINK current source for the USB_DM pin.
82588  *  0b011..Reserved, not for customer use.
82589  *  0b100..Enables VDM_SRC voltage source only.
82590  *  0b101..Reserved, not for customer use.
82591  *  0b110..Reserved, not for customer use.
82592  *  0b111..Reserved, not for customer use.
82593  */
82594 #define USBHSDCD_SIGNAL_OVERRIDE_PS(x)           (((uint32_t)(((uint32_t)(x)) << USBHSDCD_SIGNAL_OVERRIDE_PS_SHIFT)) & USBHSDCD_SIGNAL_OVERRIDE_PS_MASK)
82595 /*! @} */
82596 
82597 /*! @name TIMER0 - TIMER0 */
82598 /*! @{ */
82599 
82600 #define USBHSDCD_TIMER0_TUNITCON_MASK            (0xFFFU)
82601 #define USBHSDCD_TIMER0_TUNITCON_SHIFT           (0U)
82602 /*! TUNITCON - Unit Connection Timer Elapse (in ms) */
82603 #define USBHSDCD_TIMER0_TUNITCON(x)              (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER0_TUNITCON_SHIFT)) & USBHSDCD_TIMER0_TUNITCON_MASK)
82604 
82605 #define USBHSDCD_TIMER0_TSEQ_INIT_MASK           (0x3FF0000U)
82606 #define USBHSDCD_TIMER0_TSEQ_INIT_SHIFT          (16U)
82607 /*! TSEQ_INIT - Sequence Initiation Time
82608  *  0b0000000000-0b1111111111..0 ms - 1023 ms
82609  */
82610 #define USBHSDCD_TIMER0_TSEQ_INIT(x)             (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER0_TSEQ_INIT_SHIFT)) & USBHSDCD_TIMER0_TSEQ_INIT_MASK)
82611 /*! @} */
82612 
82613 /*! @name TIMER1 - TIMER1 */
82614 /*! @{ */
82615 
82616 #define USBHSDCD_TIMER1_TVDPSRC_ON_MASK          (0x3FFU)
82617 #define USBHSDCD_TIMER1_TVDPSRC_ON_SHIFT         (0U)
82618 /*! TVDPSRC_ON - Time Period Comparator Enabled
82619  *  0b0000000001-0b1111111111..1 ms - 1023 ms
82620  */
82621 #define USBHSDCD_TIMER1_TVDPSRC_ON(x)            (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER1_TVDPSRC_ON_SHIFT)) & USBHSDCD_TIMER1_TVDPSRC_ON_MASK)
82622 
82623 #define USBHSDCD_TIMER1_TDCD_DBNC_MASK           (0x3FF0000U)
82624 #define USBHSDCD_TIMER1_TDCD_DBNC_SHIFT          (16U)
82625 /*! TDCD_DBNC - Time Period to Debounce D+ Signal
82626  *  0b0000000001-0b1111111111..1 ms - 1023 ms
82627  */
82628 #define USBHSDCD_TIMER1_TDCD_DBNC(x)             (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER1_TDCD_DBNC_SHIFT)) & USBHSDCD_TIMER1_TDCD_DBNC_MASK)
82629 /*! @} */
82630 
82631 /*! @name TIMER2_BC11 - TIMER2_BC11 */
82632 /*! @{ */
82633 
82634 #define USBHSDCD_TIMER2_BC11_CHECK_DM_MASK       (0xFU)
82635 #define USBHSDCD_TIMER2_BC11_CHECK_DM_SHIFT      (0U)
82636 /*! CHECK_DM - Time Before Check of D- Line
82637  *  0b0001-0b1111..1 ms - 15 ms
82638  */
82639 #define USBHSDCD_TIMER2_BC11_CHECK_DM(x)         (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC11_CHECK_DM_SHIFT)) & USBHSDCD_TIMER2_BC11_CHECK_DM_MASK)
82640 
82641 #define USBHSDCD_TIMER2_BC11_TVDPSRC_CON_MASK    (0x3FF0000U)
82642 #define USBHSDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT   (16U)
82643 /*! TVDPSRC_CON - Time Period Before Enabling D+ Pullup
82644  *  0b0000000001-0b1111111111..1 ms - 1023 ms
82645  */
82646 #define USBHSDCD_TIMER2_BC11_TVDPSRC_CON(x)      (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT)) & USBHSDCD_TIMER2_BC11_TVDPSRC_CON_MASK)
82647 /*! @} */
82648 
82649 /*! @name TIMER2_BC12 - TIMER2_BC12 */
82650 /*! @{ */
82651 
82652 #define USBHSDCD_TIMER2_BC12_TVDMSRC_ON_MASK     (0x3FFU)
82653 #define USBHSDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT    (0U)
82654 /*! TVDMSRC_ON - TVDMSRC_ON
82655  *  0b0000000000-0b0000101000..0 ms - 40 ms
82656  */
82657 #define USBHSDCD_TIMER2_BC12_TVDMSRC_ON(x)       (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT)) & USBHSDCD_TIMER2_BC12_TVDMSRC_ON_MASK)
82658 
82659 #define USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK (0x3FF0000U)
82660 #define USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT (16U)
82661 /*! TWAIT_AFTER_PRD - TWAIT_AFTER_PRD
82662  *  0b0000000001-0b1111111111..1 ms - 1023 ms
82663  */
82664 #define USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x)  (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT)) & USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK)
82665 /*! @} */
82666 
82667 
82668 /*!
82669  * @}
82670  */ /* end of group USBHSDCD_Register_Masks */
82671 
82672 
82673 /* USBHSDCD - Peripheral instance base addresses */
82674 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
82675   /** Peripheral USBHS1_PHY_DCD base address */
82676   #define USBHS1_PHY_DCD_BASE                      (0x5010A800u)
82677   /** Peripheral USBHS1_PHY_DCD base address */
82678   #define USBHS1_PHY_DCD_BASE_NS                   (0x4010A800u)
82679   /** Peripheral USBHS1_PHY_DCD base pointer */
82680   #define USBHS1_PHY_DCD                           ((USBHSDCD_Type *)USBHS1_PHY_DCD_BASE)
82681   /** Peripheral USBHS1_PHY_DCD base pointer */
82682   #define USBHS1_PHY_DCD_NS                        ((USBHSDCD_Type *)USBHS1_PHY_DCD_BASE_NS)
82683   /** Array initializer of USBHSDCD peripheral base addresses */
82684   #define USBHSDCD_BASE_ADDRS                      { USBHS1_PHY_DCD_BASE }
82685   /** Array initializer of USBHSDCD peripheral base pointers */
82686   #define USBHSDCD_BASE_PTRS                       { USBHS1_PHY_DCD }
82687   /** Array initializer of USBHSDCD peripheral base addresses */
82688   #define USBHSDCD_BASE_ADDRS_NS                   { USBHS1_PHY_DCD_BASE_NS }
82689   /** Array initializer of USBHSDCD peripheral base pointers */
82690   #define USBHSDCD_BASE_PTRS_NS                    { USBHS1_PHY_DCD_NS }
82691 #else
82692   /** Peripheral USBHS1_PHY_DCD base address */
82693   #define USBHS1_PHY_DCD_BASE                      (0x4010A800u)
82694   /** Peripheral USBHS1_PHY_DCD base pointer */
82695   #define USBHS1_PHY_DCD                           ((USBHSDCD_Type *)USBHS1_PHY_DCD_BASE)
82696   /** Array initializer of USBHSDCD peripheral base addresses */
82697   #define USBHSDCD_BASE_ADDRS                      { USBHS1_PHY_DCD_BASE }
82698   /** Array initializer of USBHSDCD peripheral base pointers */
82699   #define USBHSDCD_BASE_PTRS                       { USBHS1_PHY_DCD }
82700 #endif
82701 /* Backward compatibility */
82702 #define USBHSDCD_IRQS                            { USB1_HS_PHY_IRQn }
82703 #define USB1_HS_PHY_IRQS                         USBPHY_IRQS
82704 
82705 
82706 /*!
82707  * @}
82708  */ /* end of group USBHSDCD_Peripheral_Access_Layer */
82709 
82710 
82711 /* ----------------------------------------------------------------------------
82712    -- USBNC Peripheral Access Layer
82713    ---------------------------------------------------------------------------- */
82714 
82715 /*!
82716  * @addtogroup USBNC_Peripheral_Access_Layer USBNC Peripheral Access Layer
82717  * @{
82718  */
82719 
82720 /** USBNC - Register Layout Typedef */
82721 typedef struct {
82722   __IO uint32_t CTRL1;                             /**< USB OTG Control 1, offset: 0x0 */
82723   __IO uint32_t CTRL2;                             /**< USB OTG Control 2, offset: 0x4 */
82724        uint8_t RESERVED_0[8];
82725   __IO uint32_t HSIC_CTRL;                         /**< USB Host HSIC Control, offset: 0x10 */
82726 } USBNC_Type;
82727 
82728 /* ----------------------------------------------------------------------------
82729    -- USBNC Register Masks
82730    ---------------------------------------------------------------------------- */
82731 
82732 /*!
82733  * @addtogroup USBNC_Register_Masks USBNC Register Masks
82734  * @{
82735  */
82736 
82737 /*! @name CTRL1 - USB OTG Control 1 */
82738 /*! @{ */
82739 
82740 #define USBNC_CTRL1_OVER_CUR_DIS_MASK            (0x80U)
82741 #define USBNC_CTRL1_OVER_CUR_DIS_SHIFT           (7U)
82742 /*! OVER_CUR_DIS - Disable Overcurrent Detection
82743  *  0b1..Disables
82744  *  0b0..Enables
82745  */
82746 #define USBNC_CTRL1_OVER_CUR_DIS(x)              (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_OVER_CUR_DIS_SHIFT)) & USBNC_CTRL1_OVER_CUR_DIS_MASK)
82747 
82748 #define USBNC_CTRL1_OVER_CUR_POL_MASK            (0x100U)
82749 #define USBNC_CTRL1_OVER_CUR_POL_SHIFT           (8U)
82750 /*! OVER_CUR_POL - Polarity of Overcurrent
82751  *  0b1..Low active (low on this signal represents an overcurrent condition)
82752  *  0b0..High active (high on this signal represents an overcurrent condition)
82753  */
82754 #define USBNC_CTRL1_OVER_CUR_POL(x)              (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_OVER_CUR_POL_SHIFT)) & USBNC_CTRL1_OVER_CUR_POL_MASK)
82755 
82756 #define USBNC_CTRL1_PWR_POL_MASK                 (0x200U)
82757 #define USBNC_CTRL1_PWR_POL_SHIFT                (9U)
82758 /*! PWR_POL - Power Polarity
82759  *  0b1..PMIC Power Pin is High active.
82760  *  0b0..PMIC Power Pin is Low active.
82761  */
82762 #define USBNC_CTRL1_PWR_POL(x)                   (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_PWR_POL_SHIFT)) & USBNC_CTRL1_PWR_POL_MASK)
82763 
82764 #define USBNC_CTRL1_WIE_MASK                     (0x400U)
82765 #define USBNC_CTRL1_WIE_SHIFT                    (10U)
82766 /*! WIE - Wake-up Interrupt Enable
82767  *  0b1..Interrupt Enabled
82768  *  0b0..Interrupt Disabled
82769  */
82770 #define USBNC_CTRL1_WIE(x)                       (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WIE_SHIFT)) & USBNC_CTRL1_WIE_MASK)
82771 
82772 #define USBNC_CTRL1_WKUP_SW_EN_MASK              (0x4000U)
82773 #define USBNC_CTRL1_WKUP_SW_EN_SHIFT             (14U)
82774 /*! WKUP_SW_EN - Software Wake-up Enable
82775  *  0b1..Enables
82776  *  0b0..Disables
82777  */
82778 #define USBNC_CTRL1_WKUP_SW_EN(x)                (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_SW_EN_SHIFT)) & USBNC_CTRL1_WKUP_SW_EN_MASK)
82779 
82780 #define USBNC_CTRL1_WKUP_SW_MASK                 (0x8000U)
82781 #define USBNC_CTRL1_WKUP_SW_SHIFT                (15U)
82782 /*! WKUP_SW - Software Wake-up
82783  *  0b1..Force wake-up
82784  *  0b0..Inactive
82785  */
82786 #define USBNC_CTRL1_WKUP_SW(x)                   (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_SW_SHIFT)) & USBNC_CTRL1_WKUP_SW_MASK)
82787 
82788 #define USBNC_CTRL1_WKUP_ID_EN_MASK              (0x10000U)
82789 #define USBNC_CTRL1_WKUP_ID_EN_SHIFT             (16U)
82790 /*! WKUP_ID_EN - Wake-up on ID Change Enable
82791  *  0b1..Enables
82792  *  0b0..Disables
82793  */
82794 #define USBNC_CTRL1_WKUP_ID_EN(x)                (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_ID_EN_SHIFT)) & USBNC_CTRL1_WKUP_ID_EN_MASK)
82795 
82796 #define USBNC_CTRL1_WKUP_VBUS_EN_MASK            (0x20000U)
82797 #define USBNC_CTRL1_WKUP_VBUS_EN_SHIFT           (17U)
82798 /*! WKUP_VBUS_EN - Wake-up on VBUS Change Enable
82799  *  0b1..Enables
82800  *  0b0..Disables
82801  */
82802 #define USBNC_CTRL1_WKUP_VBUS_EN(x)              (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_VBUS_EN_SHIFT)) & USBNC_CTRL1_WKUP_VBUS_EN_MASK)
82803 
82804 #define USBNC_CTRL1_WKUP_DPDM_EN_MASK            (0x20000000U)
82805 #define USBNC_CTRL1_WKUP_DPDM_EN_SHIFT           (29U)
82806 /*! WKUP_DPDM_EN - Wake-up on DPDM Change Enable
82807  *  0b1..DPDM changes wake-up to be enabled, it is for device only
82808  *  0b0..DPDM changes wake-up to be disabled only when VBUS is 0
82809  */
82810 #define USBNC_CTRL1_WKUP_DPDM_EN(x)              (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_DPDM_EN_SHIFT)) & USBNC_CTRL1_WKUP_DPDM_EN_MASK)
82811 
82812 #define USBNC_CTRL1_WIR_MASK                     (0x80000000U)
82813 #define USBNC_CTRL1_WIR_SHIFT                    (31U)
82814 /*! WIR - Wake-up Interrupt Request
82815  *  0b1..Request received
82816  *  0b0..No request received
82817  */
82818 #define USBNC_CTRL1_WIR(x)                       (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WIR_SHIFT)) & USBNC_CTRL1_WIR_MASK)
82819 /*! @} */
82820 
82821 /*! @name CTRL2 - USB OTG Control 2 */
82822 /*! @{ */
82823 
82824 #define USBNC_CTRL2_VBUS_SOURCE_SEL_MASK         (0x3U)
82825 #define USBNC_CTRL2_VBUS_SOURCE_SEL_SHIFT        (0U)
82826 /*! VBUS_SOURCE_SEL - VBUS Source Select
82827  *  0b00..vbus_valid
82828  *  0b01..sess_valid
82829  *  0b10..sess_valid
82830  *  0b11..sess_valid
82831  */
82832 #define USBNC_CTRL2_VBUS_SOURCE_SEL(x)           (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_VBUS_SOURCE_SEL_SHIFT)) & USBNC_CTRL2_VBUS_SOURCE_SEL_MASK)
82833 
82834 #define USBNC_CTRL2_AUTURESUME_EN_MASK           (0x4U)
82835 #define USBNC_CTRL2_AUTURESUME_EN_SHIFT          (2U)
82836 /*! AUTURESUME_EN - Auto Resume Enable
82837  *  0b0..Default
82838  */
82839 #define USBNC_CTRL2_AUTURESUME_EN(x)             (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_AUTURESUME_EN_SHIFT)) & USBNC_CTRL2_AUTURESUME_EN_MASK)
82840 
82841 #define USBNC_CTRL2_LOWSPEED_EN_MASK             (0x8U)
82842 #define USBNC_CTRL2_LOWSPEED_EN_SHIFT            (3U)
82843 /*! LOWSPEED_EN - Low Speed Enable
82844  *  0b0..Default
82845  */
82846 #define USBNC_CTRL2_LOWSPEED_EN(x)               (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_LOWSPEED_EN_SHIFT)) & USBNC_CTRL2_LOWSPEED_EN_MASK)
82847 
82848 #define USBNC_CTRL2_UTMI_CLK_VLD_MASK            (0x80000000U)
82849 #define USBNC_CTRL2_UTMI_CLK_VLD_SHIFT           (31U)
82850 /*! UTMI_CLK_VLD - UTMI Clock Valid
82851  *  0b0..Default
82852  */
82853 #define USBNC_CTRL2_UTMI_CLK_VLD(x)              (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_UTMI_CLK_VLD_SHIFT)) & USBNC_CTRL2_UTMI_CLK_VLD_MASK)
82854 /*! @} */
82855 
82856 /*! @name HSIC_CTRL - USB Host HSIC Control */
82857 /*! @{ */
82858 
82859 #define USBNC_HSIC_CTRL_HSIC_CLK_ON_MASK         (0x800U)
82860 #define USBNC_HSIC_CTRL_HSIC_CLK_ON_SHIFT        (11U)
82861 /*! HSIC_CLK_ON - HSIC Clock ON
82862  *  0b1..Active
82863  *  0b0..Inactive
82864  */
82865 #define USBNC_HSIC_CTRL_HSIC_CLK_ON(x)           (((uint32_t)(((uint32_t)(x)) << USBNC_HSIC_CTRL_HSIC_CLK_ON_SHIFT)) & USBNC_HSIC_CTRL_HSIC_CLK_ON_MASK)
82866 
82867 #define USBNC_HSIC_CTRL_HSIC_EN_MASK             (0x1000U)
82868 #define USBNC_HSIC_CTRL_HSIC_EN_SHIFT            (12U)
82869 /*! HSIC_EN - Host HSIC Enable
82870  *  0b1..Enabled
82871  *  0b0..Disabled
82872  */
82873 #define USBNC_HSIC_CTRL_HSIC_EN(x)               (((uint32_t)(((uint32_t)(x)) << USBNC_HSIC_CTRL_HSIC_EN_SHIFT)) & USBNC_HSIC_CTRL_HSIC_EN_MASK)
82874 
82875 #define USBNC_HSIC_CTRL_CLK_VLD_MASK             (0x80000000U)
82876 #define USBNC_HSIC_CTRL_CLK_VLD_SHIFT            (31U)
82877 /*! CLK_VLD - Clock Valid
82878  *  0b1..Valid
82879  *  0b0..Invalid
82880  */
82881 #define USBNC_HSIC_CTRL_CLK_VLD(x)               (((uint32_t)(((uint32_t)(x)) << USBNC_HSIC_CTRL_CLK_VLD_SHIFT)) & USBNC_HSIC_CTRL_CLK_VLD_MASK)
82882 /*! @} */
82883 
82884 
82885 /*!
82886  * @}
82887  */ /* end of group USBNC_Register_Masks */
82888 
82889 
82890 /* USBNC - Peripheral instance base addresses */
82891 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
82892   /** Peripheral USBHS1__USBNC base address */
82893   #define USBHS1__USBNC_BASE                       (0x5010B200u)
82894   /** Peripheral USBHS1__USBNC base address */
82895   #define USBHS1__USBNC_BASE_NS                    (0x4010B200u)
82896   /** Peripheral USBHS1__USBNC base pointer */
82897   #define USBHS1__USBNC                            ((USBNC_Type *)USBHS1__USBNC_BASE)
82898   /** Peripheral USBHS1__USBNC base pointer */
82899   #define USBHS1__USBNC_NS                         ((USBNC_Type *)USBHS1__USBNC_BASE_NS)
82900   /** Array initializer of USBNC peripheral base addresses */
82901   #define USBNC_BASE_ADDRS                         { USBHS1__USBNC_BASE }
82902   /** Array initializer of USBNC peripheral base pointers */
82903   #define USBNC_BASE_PTRS                          { USBHS1__USBNC }
82904   /** Array initializer of USBNC peripheral base addresses */
82905   #define USBNC_BASE_ADDRS_NS                      { USBHS1__USBNC_BASE_NS }
82906   /** Array initializer of USBNC peripheral base pointers */
82907   #define USBNC_BASE_PTRS_NS                       { USBHS1__USBNC_NS }
82908 #else
82909   /** Peripheral USBHS1__USBNC base address */
82910   #define USBHS1__USBNC_BASE                       (0x4010B200u)
82911   /** Peripheral USBHS1__USBNC base pointer */
82912   #define USBHS1__USBNC                            ((USBNC_Type *)USBHS1__USBNC_BASE)
82913   /** Array initializer of USBNC peripheral base addresses */
82914   #define USBNC_BASE_ADDRS                         { USBHS1__USBNC_BASE }
82915   /** Array initializer of USBNC peripheral base pointers */
82916   #define USBNC_BASE_PTRS                          { USBHS1__USBNC }
82917 #endif
82918 /* Backward compatibility */
82919 #define USB_OTGn_CTRL     CTRL1
82920 #define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_MASK     USBNC_CTRL1_OVER_CUR_DIS_MASK
82921 #define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_SHIFT     USBNC_CTRL1_OVER_CUR_DIS_SHIFT
82922 #define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS(x)     USBNC_CTRL1_OVER_CUR_DIS(x)
82923 #define USBNC_USB_OTGn_CTRL_OVER_CUR_POL_MASK     USBNC_CTRL1_OVER_CUR_POL_MASK
82924 #define USBNC_USB_OTGn_CTRL_OVER_CUR_POL_SHIFT     USBNC_CTRL1_OVER_CUR_POL_SHIFT
82925 #define USBNC_USB_OTGn_CTRL_OVER_CUR_POL(x)     USBNC_CTRL1_OVER_CUR_POL(x)
82926 #define USBNC_USB_OTGn_CTRL_PWR_POL_MASK     USBNC_CTRL1_PWR_POL_MASK
82927 #define USBNC_USB_OTGn_CTRL_PWR_POL_SHIFT     USBNC_CTRL1_PWR_POL_SHIFT
82928 #define USBNC_USB_OTGn_CTRL_PWR_POL(x)     USBNC_CTRL1_PWR_POL(x)
82929 #define USBNC_USB_OTGn_CTRL_WIE_MASK     USBNC_CTRL1_WIE_MASK
82930 #define USBNC_USB_OTGn_CTRL_WIE_SHIFT     USBNC_CTRL1_WIE_SHIFT
82931 #define USBNC_USB_OTGn_CTRL_WIE(x)     USBNC_CTRL1_WIE(x)
82932 #define USBNC_USB_OTGn_CTRL_WKUP_SW_EN_MASK     USBNC_CTRL1_WKUP_SW_EN_MASK
82933 #define USBNC_USB_OTGn_CTRL_WKUP_SW_EN_SHIFT     USBNC_CTRL1_WKUP_SW_EN_SHIFT
82934 #define USBNC_USB_OTGn_CTRL_WKUP_SW_EN(x)     USBNC_CTRL1_WKUP_SW_EN(x)
82935 #define USBNC_USB_OTGn_CTRL_WKUP_SW_MASK     USBNC_CTRL1_WKUP_SW_MASK
82936 #define USBNC_USB_OTGn_CTRL_WKUP_SW_SHIFT     USBNC_CTRL1_WKUP_SW_SHIFT
82937 #define USBNC_USB_OTGn_CTRL_WKUP_SW(x)     USBNC_CTRL1_WKUP_SW(x)
82938 #define USBNC_USB_OTGn_CTRL_WKUP_ID_EN_MASK     USBNC_CTRL1_WKUP_ID_EN_MASK
82939 #define USBNC_USB_OTGn_CTRL_WKUP_ID_EN_SHIFT     USBNC_CTRL1_WKUP_ID_EN_SHIFT
82940 #define USBNC_USB_OTGn_CTRL_WKUP_ID_EN(x)     USBNC_CTRL1_WKUP_ID_EN(x)
82941 #define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_MASK     USBNC_CTRL1_WKUP_VBUS_EN_MASK
82942 #define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_SHIFT     USBNC_CTRL1_WKUP_VBUS_EN_SHIFT
82943 #define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN(x)     USBNC_CTRL1_WKUP_VBUS_EN(x)
82944 #define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_MASK     USBNC_CTRL1_WKUP_DPDM_EN_MASK
82945 #define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_SHIFT     USBNC_CTRL1_WKUP_DPDM_EN_SHIFT
82946 #define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN(x)     USBNC_CTRL1_WKUP_DPDM_EN(x)
82947 #define USBNC_USB_OTGn_CTRL_WIR_MASK     USBNC_CTRL1_WIR_MASK
82948 #define USBNC_USB_OTGn_CTRL_WIR_SHIFT     USBNC_CTRL1_WIR_SHIFT
82949 #define USBNC_USB_OTGn_CTRL_WIR(x)     USBNC_CTRL1_WIR(x)
82950 
82951 
82952 /*!
82953  * @}
82954  */ /* end of group USBNC_Peripheral_Access_Layer */
82955 
82956 
82957 /* ----------------------------------------------------------------------------
82958    -- USBPHY Peripheral Access Layer
82959    ---------------------------------------------------------------------------- */
82960 
82961 /*!
82962  * @addtogroup USBPHY_Peripheral_Access_Layer USBPHY Peripheral Access Layer
82963  * @{
82964  */
82965 
82966 /** USBPHY - Register Layout Typedef */
82967 typedef struct {
82968   __IO uint32_t PWD;                               /**< Power Down, offset: 0x0 */
82969   __IO uint32_t PWD_SET;                           /**< Power Down, offset: 0x4 */
82970   __IO uint32_t PWD_CLR;                           /**< Power Down, offset: 0x8 */
82971   __IO uint32_t PWD_TOG;                           /**< Power Down, offset: 0xC */
82972   __IO uint32_t TX;                                /**< TX Control, offset: 0x10 */
82973   __IO uint32_t TX_SET;                            /**< TX Control, offset: 0x14 */
82974   __IO uint32_t TX_CLR;                            /**< TX Control, offset: 0x18 */
82975   __IO uint32_t TX_TOG;                            /**< TX Control, offset: 0x1C */
82976   __IO uint32_t RX;                                /**< RX Control, offset: 0x20 */
82977   __IO uint32_t RX_SET;                            /**< RX Control, offset: 0x24 */
82978   __IO uint32_t RX_CLR;                            /**< RX Control, offset: 0x28 */
82979   __IO uint32_t RX_TOG;                            /**< RX Control, offset: 0x2C */
82980   __IO uint32_t CTRL;                              /**< General Purpose Control, offset: 0x30 */
82981   __IO uint32_t CTRL_SET;                          /**< General Purpose Control, offset: 0x34 */
82982   __IO uint32_t CTRL_CLR;                          /**< General Purpose Control, offset: 0x38 */
82983   __IO uint32_t CTRL_TOG;                          /**< General Purpose Control, offset: 0x3C */
82984   __IO uint32_t STATUS;                            /**< Status, offset: 0x40 */
82985        uint8_t RESERVED_0[12];
82986   __IO uint32_t DEBUG0;                            /**< Debug 0, offset: 0x50 */
82987   __IO uint32_t DEBUG0_SET;                        /**< Debug 0, offset: 0x54 */
82988   __IO uint32_t DEBUG0_CLR;                        /**< Debug 0, offset: 0x58 */
82989   __IO uint32_t DEBUG0_TOG;                        /**< Debug 0, offset: 0x5C */
82990        uint8_t RESERVED_1[32];
82991   __I  uint32_t VERSION;                           /**< Version, offset: 0x80 */
82992        uint8_t RESERVED_2[12];
82993   __IO uint32_t IP;                                /**< IP Block, offset: 0x90 */
82994   __IO uint32_t IP_SET;                            /**< IP Block, offset: 0x94 */
82995   __IO uint32_t IP_CLR;                            /**< IP Block, offset: 0x98 */
82996   __IO uint32_t IP_TOG;                            /**< IP Block, offset: 0x9C */
82997   __IO uint32_t PLL_SIC;                           /**< PLL SIC, offset: 0xA0 */
82998   __IO uint32_t PLL_SIC_SET;                       /**< PLL SIC, offset: 0xA4 */
82999   __IO uint32_t PLL_SIC_CLR;                       /**< PLL SIC, offset: 0xA8 */
83000   __IO uint32_t PLL_SIC_TOG;                       /**< PLL SIC, offset: 0xAC */
83001        uint8_t RESERVED_3[16];
83002   __IO uint32_t USB1_VBUS_DETECT;                  /**< VBUS Detect, offset: 0xC0 */
83003   __IO uint32_t USB1_VBUS_DETECT_SET;              /**< VBUS Detect, offset: 0xC4 */
83004   __IO uint32_t USB1_VBUS_DETECT_CLR;              /**< VBUS Detect, offset: 0xC8 */
83005   __IO uint32_t USB1_VBUS_DETECT_TOG;              /**< VBUS Detect, offset: 0xCC */
83006   __I  uint32_t USB1_VBUS_DET_STAT;                /**< VBUS Detect Status, offset: 0xD0 */
83007   __I  uint32_t USB1_VBUS_DET_STAT_SET;            /**< VBUS Detect Status, offset: 0xD4 */
83008   __I  uint32_t USB1_VBUS_DET_STAT_CLR;            /**< VBUS Detect Status, offset: 0xD8 */
83009   __I  uint32_t USB1_VBUS_DET_STAT_TOG;            /**< VBUS Detect Status, offset: 0xDC */
83010   __IO uint32_t USB1_CHRG_DETECT;                  /**< Charger Detect, offset: 0xE0 */
83011   __IO uint32_t USB1_CHRG_DETECT_SET;              /**< Charger Detect, offset: 0xE4 */
83012   __IO uint32_t USB1_CHRG_DETECT_CLR;              /**< Charger Detect, offset: 0xE8 */
83013   __IO uint32_t USB1_CHRG_DETECT_TOG;              /**< Charger Detect, offset: 0xEC */
83014   __I  uint32_t USB1_CHRG_DET_STAT;                /**< Charger Detect Status, offset: 0xF0 */
83015   __I  uint32_t USB1_CHRG_DET_STAT_SET;            /**< Charger Detect Status, offset: 0xF4 */
83016   __I  uint32_t USB1_CHRG_DET_STAT_CLR;            /**< Charger Detect Status, offset: 0xF8 */
83017   __I  uint32_t USB1_CHRG_DET_STAT_TOG;            /**< Charger Detect Status, offset: 0xFC */
83018   __IO uint32_t ANACTRL;                           /**< Analog Control, offset: 0x100 */
83019   __IO uint32_t ANACTRL_SET;                       /**< Analog Control, offset: 0x104 */
83020   __IO uint32_t ANACTRL_CLR;                       /**< Analog Control, offset: 0x108 */
83021   __IO uint32_t ANACTRL_TOG;                       /**< Analog Control, offset: 0x10C */
83022        uint8_t RESERVED_4[32];
83023   __IO uint32_t TRIM_OVERRIDE_EN;                  /**< Trim, offset: 0x130 */
83024   __IO uint32_t TRIM_OVERRIDE_EN_SET;              /**< Trim, offset: 0x134 */
83025   __IO uint32_t TRIM_OVERRIDE_EN_CLR;              /**< Trim, offset: 0x138 */
83026   __IO uint32_t TRIM_OVERRIDE_EN_TOG;              /**< Trim, offset: 0x13C */
83027   __IO uint32_t PFDA;                              /**< PFD A, offset: 0x140 */
83028   __IO uint32_t PFDA_SET;                          /**< PFD A, offset: 0x144 */
83029   __IO uint32_t PFDA_CLR;                          /**< PFD A, offset: 0x148 */
83030   __IO uint32_t PFDA_TOG;                          /**< PFD A, offset: 0x14C */
83031 } USBPHY_Type;
83032 
83033 /* ----------------------------------------------------------------------------
83034    -- USBPHY Register Masks
83035    ---------------------------------------------------------------------------- */
83036 
83037 /*!
83038  * @addtogroup USBPHY_Register_Masks USBPHY Register Masks
83039  * @{
83040  */
83041 
83042 /*! @name PWD - Power Down */
83043 /*! @{ */
83044 
83045 #define USBPHY_PWD_TXPWDFS_MASK                  (0x400U)
83046 #define USBPHY_PWD_TXPWDFS_SHIFT                 (10U)
83047 /*! TXPWDFS - Power Down USB FS TX Drivers
83048  *  0b0..Provide bias to enable
83049  *  0b1..Disable or power down
83050  */
83051 #define USBPHY_PWD_TXPWDFS(x)                    (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDFS_SHIFT)) & USBPHY_PWD_TXPWDFS_MASK)
83052 
83053 #define USBPHY_PWD_TXPWDIBIAS_MASK               (0x800U)
83054 #define USBPHY_PWD_TXPWDIBIAS_SHIFT              (11U)
83055 /*! TXPWDIBIAS - Power Down USBPHY TX Current Bias Block
83056  *  0b0..Enable
83057  *  0b1..Disable or power down
83058  */
83059 #define USBPHY_PWD_TXPWDIBIAS(x)                 (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TXPWDIBIAS_MASK)
83060 
83061 #define USBPHY_PWD_TXPWDV2I_MASK                 (0x1000U)
83062 #define USBPHY_PWD_TXPWDV2I_SHIFT                (12U)
83063 /*! TXPWDV2I - Power Down USBPHY TX V-I Converter and Current Mirror
83064  *  0b0..Enable
83065  *  0b1..Disable or power down
83066  */
83067 #define USBPHY_PWD_TXPWDV2I(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDV2I_SHIFT)) & USBPHY_PWD_TXPWDV2I_MASK)
83068 
83069 #define USBPHY_PWD_RXPWDENV_MASK                 (0x20000U)
83070 #define USBPHY_PWD_RXPWDENV_SHIFT                (17U)
83071 /*! RXPWDENV - Power Down USB HS RX Envelope Detector
83072  *  0b0..Enable
83073  *  0b1..Disable or power down
83074  */
83075 #define USBPHY_PWD_RXPWDENV(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDENV_SHIFT)) & USBPHY_PWD_RXPWDENV_MASK)
83076 
83077 #define USBPHY_PWD_RXPWD1PT1_MASK                (0x40000U)
83078 #define USBPHY_PWD_RXPWD1PT1_SHIFT               (18U)
83079 /*! RXPWD1PT1 - Power Down USB FS Differential Receiver
83080  *  0b0..Enable
83081  *  0b1..Disable or power down
83082  */
83083 #define USBPHY_PWD_RXPWD1PT1(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWD1PT1_SHIFT)) & USBPHY_PWD_RXPWD1PT1_MASK)
83084 
83085 #define USBPHY_PWD_RXPWDDIFF_MASK                (0x80000U)
83086 #define USBPHY_PWD_RXPWDDIFF_SHIFT               (19U)
83087 /*! RXPWDDIFF - Power Down USB HS Differential Receiver
83088  *  0b0..Enable
83089  *  0b1..Disable or power down
83090  */
83091 #define USBPHY_PWD_RXPWDDIFF(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDDIFF_SHIFT)) & USBPHY_PWD_RXPWDDIFF_MASK)
83092 
83093 #define USBPHY_PWD_RXPWDRX_MASK                  (0x100000U)
83094 #define USBPHY_PWD_RXPWDRX_SHIFT                 (20U)
83095 /*! RXPWDRX - Power Down USBPHY Receiver Circuits
83096  *  0b0..Enable
83097  *  0b1..Disable or power down
83098  */
83099 #define USBPHY_PWD_RXPWDRX(x)                    (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDRX_SHIFT)) & USBPHY_PWD_RXPWDRX_MASK)
83100 /*! @} */
83101 
83102 /*! @name PWD_SET - Power Down */
83103 /*! @{ */
83104 
83105 #define USBPHY_PWD_SET_TXPWDFS_MASK              (0x400U)
83106 #define USBPHY_PWD_SET_TXPWDFS_SHIFT             (10U)
83107 /*! TXPWDFS - Power Down USB FS TX Drivers */
83108 #define USBPHY_PWD_SET_TXPWDFS(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDFS_SHIFT)) & USBPHY_PWD_SET_TXPWDFS_MASK)
83109 
83110 #define USBPHY_PWD_SET_TXPWDIBIAS_MASK           (0x800U)
83111 #define USBPHY_PWD_SET_TXPWDIBIAS_SHIFT          (11U)
83112 /*! TXPWDIBIAS - Power Down USBPHY TX Current Bias Block */
83113 #define USBPHY_PWD_SET_TXPWDIBIAS(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_SET_TXPWDIBIAS_MASK)
83114 
83115 #define USBPHY_PWD_SET_TXPWDV2I_MASK             (0x1000U)
83116 #define USBPHY_PWD_SET_TXPWDV2I_SHIFT            (12U)
83117 /*! TXPWDV2I - Power Down USBPHY TX V-I Converter and Current Mirror */
83118 #define USBPHY_PWD_SET_TXPWDV2I(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDV2I_SHIFT)) & USBPHY_PWD_SET_TXPWDV2I_MASK)
83119 
83120 #define USBPHY_PWD_SET_RXPWDENV_MASK             (0x20000U)
83121 #define USBPHY_PWD_SET_RXPWDENV_SHIFT            (17U)
83122 /*! RXPWDENV - Power Down USB HS RX Envelope Detector */
83123 #define USBPHY_PWD_SET_RXPWDENV(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDENV_SHIFT)) & USBPHY_PWD_SET_RXPWDENV_MASK)
83124 
83125 #define USBPHY_PWD_SET_RXPWD1PT1_MASK            (0x40000U)
83126 #define USBPHY_PWD_SET_RXPWD1PT1_SHIFT           (18U)
83127 /*! RXPWD1PT1 - Power Down USB FS Differential Receiver */
83128 #define USBPHY_PWD_SET_RXPWD1PT1(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWD1PT1_SHIFT)) & USBPHY_PWD_SET_RXPWD1PT1_MASK)
83129 
83130 #define USBPHY_PWD_SET_RXPWDDIFF_MASK            (0x80000U)
83131 #define USBPHY_PWD_SET_RXPWDDIFF_SHIFT           (19U)
83132 /*! RXPWDDIFF - Power Down USB HS Differential Receiver */
83133 #define USBPHY_PWD_SET_RXPWDDIFF(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDDIFF_SHIFT)) & USBPHY_PWD_SET_RXPWDDIFF_MASK)
83134 
83135 #define USBPHY_PWD_SET_RXPWDRX_MASK              (0x100000U)
83136 #define USBPHY_PWD_SET_RXPWDRX_SHIFT             (20U)
83137 /*! RXPWDRX - Power Down USBPHY Receiver Circuits */
83138 #define USBPHY_PWD_SET_RXPWDRX(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDRX_SHIFT)) & USBPHY_PWD_SET_RXPWDRX_MASK)
83139 /*! @} */
83140 
83141 /*! @name PWD_CLR - Power Down */
83142 /*! @{ */
83143 
83144 #define USBPHY_PWD_CLR_TXPWDFS_MASK              (0x400U)
83145 #define USBPHY_PWD_CLR_TXPWDFS_SHIFT             (10U)
83146 /*! TXPWDFS - Power Down USB FS TX Drivers */
83147 #define USBPHY_PWD_CLR_TXPWDFS(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDFS_SHIFT)) & USBPHY_PWD_CLR_TXPWDFS_MASK)
83148 
83149 #define USBPHY_PWD_CLR_TXPWDIBIAS_MASK           (0x800U)
83150 #define USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT          (11U)
83151 /*! TXPWDIBIAS - Power Down USBPHY TX Current Bias Block */
83152 #define USBPHY_PWD_CLR_TXPWDIBIAS(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_CLR_TXPWDIBIAS_MASK)
83153 
83154 #define USBPHY_PWD_CLR_TXPWDV2I_MASK             (0x1000U)
83155 #define USBPHY_PWD_CLR_TXPWDV2I_SHIFT            (12U)
83156 /*! TXPWDV2I - Power Down USBPHY TX V-I Converter and Current Mirror */
83157 #define USBPHY_PWD_CLR_TXPWDV2I(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDV2I_SHIFT)) & USBPHY_PWD_CLR_TXPWDV2I_MASK)
83158 
83159 #define USBPHY_PWD_CLR_RXPWDENV_MASK             (0x20000U)
83160 #define USBPHY_PWD_CLR_RXPWDENV_SHIFT            (17U)
83161 /*! RXPWDENV - Power Down USB HS RX Envelope Detector */
83162 #define USBPHY_PWD_CLR_RXPWDENV(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDENV_SHIFT)) & USBPHY_PWD_CLR_RXPWDENV_MASK)
83163 
83164 #define USBPHY_PWD_CLR_RXPWD1PT1_MASK            (0x40000U)
83165 #define USBPHY_PWD_CLR_RXPWD1PT1_SHIFT           (18U)
83166 /*! RXPWD1PT1 - Power Down USB FS Differential Receiver */
83167 #define USBPHY_PWD_CLR_RXPWD1PT1(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWD1PT1_SHIFT)) & USBPHY_PWD_CLR_RXPWD1PT1_MASK)
83168 
83169 #define USBPHY_PWD_CLR_RXPWDDIFF_MASK            (0x80000U)
83170 #define USBPHY_PWD_CLR_RXPWDDIFF_SHIFT           (19U)
83171 /*! RXPWDDIFF - Power Down USB HS Differential Receiver */
83172 #define USBPHY_PWD_CLR_RXPWDDIFF(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDDIFF_SHIFT)) & USBPHY_PWD_CLR_RXPWDDIFF_MASK)
83173 
83174 #define USBPHY_PWD_CLR_RXPWDRX_MASK              (0x100000U)
83175 #define USBPHY_PWD_CLR_RXPWDRX_SHIFT             (20U)
83176 /*! RXPWDRX - Power Down USBPHY Receiver Circuits */
83177 #define USBPHY_PWD_CLR_RXPWDRX(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDRX_SHIFT)) & USBPHY_PWD_CLR_RXPWDRX_MASK)
83178 /*! @} */
83179 
83180 /*! @name PWD_TOG - Power Down */
83181 /*! @{ */
83182 
83183 #define USBPHY_PWD_TOG_TXPWDFS_MASK              (0x400U)
83184 #define USBPHY_PWD_TOG_TXPWDFS_SHIFT             (10U)
83185 /*! TXPWDFS - Power Down USB FS TX Drivers */
83186 #define USBPHY_PWD_TOG_TXPWDFS(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDFS_SHIFT)) & USBPHY_PWD_TOG_TXPWDFS_MASK)
83187 
83188 #define USBPHY_PWD_TOG_TXPWDIBIAS_MASK           (0x800U)
83189 #define USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT          (11U)
83190 /*! TXPWDIBIAS - Power Down USBPHY TX Current Bias Block */
83191 #define USBPHY_PWD_TOG_TXPWDIBIAS(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TOG_TXPWDIBIAS_MASK)
83192 
83193 #define USBPHY_PWD_TOG_TXPWDV2I_MASK             (0x1000U)
83194 #define USBPHY_PWD_TOG_TXPWDV2I_SHIFT            (12U)
83195 /*! TXPWDV2I - Power Down USBPHY TX V-I Converter and Current Mirror */
83196 #define USBPHY_PWD_TOG_TXPWDV2I(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDV2I_SHIFT)) & USBPHY_PWD_TOG_TXPWDV2I_MASK)
83197 
83198 #define USBPHY_PWD_TOG_RXPWDENV_MASK             (0x20000U)
83199 #define USBPHY_PWD_TOG_RXPWDENV_SHIFT            (17U)
83200 /*! RXPWDENV - Power Down USB HS RX Envelope Detector */
83201 #define USBPHY_PWD_TOG_RXPWDENV(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDENV_SHIFT)) & USBPHY_PWD_TOG_RXPWDENV_MASK)
83202 
83203 #define USBPHY_PWD_TOG_RXPWD1PT1_MASK            (0x40000U)
83204 #define USBPHY_PWD_TOG_RXPWD1PT1_SHIFT           (18U)
83205 /*! RXPWD1PT1 - Power Down USB FS Differential Receiver */
83206 #define USBPHY_PWD_TOG_RXPWD1PT1(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWD1PT1_SHIFT)) & USBPHY_PWD_TOG_RXPWD1PT1_MASK)
83207 
83208 #define USBPHY_PWD_TOG_RXPWDDIFF_MASK            (0x80000U)
83209 #define USBPHY_PWD_TOG_RXPWDDIFF_SHIFT           (19U)
83210 /*! RXPWDDIFF - Power Down USB HS Differential Receiver */
83211 #define USBPHY_PWD_TOG_RXPWDDIFF(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDDIFF_SHIFT)) & USBPHY_PWD_TOG_RXPWDDIFF_MASK)
83212 
83213 #define USBPHY_PWD_TOG_RXPWDRX_MASK              (0x100000U)
83214 #define USBPHY_PWD_TOG_RXPWDRX_SHIFT             (20U)
83215 /*! RXPWDRX - Power Down USBPHY Receiver Circuits */
83216 #define USBPHY_PWD_TOG_RXPWDRX(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDRX_SHIFT)) & USBPHY_PWD_TOG_RXPWDRX_MASK)
83217 /*! @} */
83218 
83219 /*! @name TX - TX Control */
83220 /*! @{ */
83221 
83222 #define USBPHY_TX_D_CAL_MASK                     (0xFU)
83223 #define USBPHY_TX_D_CAL_SHIFT                    (0U)
83224 /*! D_CAL - HS TX Output Current Trim
83225  *  0b0000..Maximum current, approximately 19% above nominal
83226  *  0b0111..Nominal
83227  *  0b1111..Minimum current, approximately 19% below nominal
83228  */
83229 #define USBPHY_TX_D_CAL(x)                       (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TX_D_CAL_MASK)
83230 
83231 #define USBPHY_TX_TXCAL45DN_MASK                 (0xF00U)
83232 #define USBPHY_TX_TXCAL45DN_SHIFT                (8U)
83233 /*! TXCAL45DN - DM Series Termination Resistance Trim */
83234 #define USBPHY_TX_TXCAL45DN(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DN_SHIFT)) & USBPHY_TX_TXCAL45DN_MASK)
83235 
83236 #define USBPHY_TX_TXCAL45DP_MASK                 (0xF0000U)
83237 #define USBPHY_TX_TXCAL45DP_SHIFT                (16U)
83238 /*! TXCAL45DP - DP Series Termination Resistance Trim */
83239 #define USBPHY_TX_TXCAL45DP(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DP_SHIFT)) & USBPHY_TX_TXCAL45DP_MASK)
83240 /*! @} */
83241 
83242 /*! @name TX_SET - TX Control */
83243 /*! @{ */
83244 
83245 #define USBPHY_TX_SET_D_CAL_MASK                 (0xFU)
83246 #define USBPHY_TX_SET_D_CAL_SHIFT                (0U)
83247 /*! D_CAL - HS TX Output Current Trim */
83248 #define USBPHY_TX_SET_D_CAL(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_D_CAL_SHIFT)) & USBPHY_TX_SET_D_CAL_MASK)
83249 
83250 #define USBPHY_TX_SET_TXCAL45DN_MASK             (0xF00U)
83251 #define USBPHY_TX_SET_TXCAL45DN_SHIFT            (8U)
83252 /*! TXCAL45DN - DM Series Termination Resistance Trim */
83253 #define USBPHY_TX_SET_TXCAL45DN(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DN_SHIFT)) & USBPHY_TX_SET_TXCAL45DN_MASK)
83254 
83255 #define USBPHY_TX_SET_TXCAL45DP_MASK             (0xF0000U)
83256 #define USBPHY_TX_SET_TXCAL45DP_SHIFT            (16U)
83257 /*! TXCAL45DP - DP Series Termination Resistance Trim */
83258 #define USBPHY_TX_SET_TXCAL45DP(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DP_SHIFT)) & USBPHY_TX_SET_TXCAL45DP_MASK)
83259 /*! @} */
83260 
83261 /*! @name TX_CLR - TX Control */
83262 /*! @{ */
83263 
83264 #define USBPHY_TX_CLR_D_CAL_MASK                 (0xFU)
83265 #define USBPHY_TX_CLR_D_CAL_SHIFT                (0U)
83266 /*! D_CAL - HS TX Output Current Trim */
83267 #define USBPHY_TX_CLR_D_CAL(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_D_CAL_SHIFT)) & USBPHY_TX_CLR_D_CAL_MASK)
83268 
83269 #define USBPHY_TX_CLR_TXCAL45DN_MASK             (0xF00U)
83270 #define USBPHY_TX_CLR_TXCAL45DN_SHIFT            (8U)
83271 /*! TXCAL45DN - DM Series Termination Resistance Trim */
83272 #define USBPHY_TX_CLR_TXCAL45DN(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DN_SHIFT)) & USBPHY_TX_CLR_TXCAL45DN_MASK)
83273 
83274 #define USBPHY_TX_CLR_TXCAL45DP_MASK             (0xF0000U)
83275 #define USBPHY_TX_CLR_TXCAL45DP_SHIFT            (16U)
83276 /*! TXCAL45DP - DP Series Termination Resistance Trim */
83277 #define USBPHY_TX_CLR_TXCAL45DP(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXCAL45DP_MASK)
83278 /*! @} */
83279 
83280 /*! @name TX_TOG - TX Control */
83281 /*! @{ */
83282 
83283 #define USBPHY_TX_TOG_D_CAL_MASK                 (0xFU)
83284 #define USBPHY_TX_TOG_D_CAL_SHIFT                (0U)
83285 /*! D_CAL - HS TX Output Current Trim */
83286 #define USBPHY_TX_TOG_D_CAL(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_D_CAL_SHIFT)) & USBPHY_TX_TOG_D_CAL_MASK)
83287 
83288 #define USBPHY_TX_TOG_TXCAL45DN_MASK             (0xF00U)
83289 #define USBPHY_TX_TOG_TXCAL45DN_SHIFT            (8U)
83290 /*! TXCAL45DN - DM Series Termination Resistance Trim */
83291 #define USBPHY_TX_TOG_TXCAL45DN(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DN_SHIFT)) & USBPHY_TX_TOG_TXCAL45DN_MASK)
83292 
83293 #define USBPHY_TX_TOG_TXCAL45DP_MASK             (0xF0000U)
83294 #define USBPHY_TX_TOG_TXCAL45DP_SHIFT            (16U)
83295 /*! TXCAL45DP - DP Series Termination Resistance Trim */
83296 #define USBPHY_TX_TOG_TXCAL45DP(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXCAL45DP_MASK)
83297 /*! @} */
83298 
83299 /*! @name RX - RX Control */
83300 /*! @{ */
83301 
83302 #define USBPHY_RX_ENVADJ_MASK                    (0x7U)
83303 #define USBPHY_RX_ENVADJ_SHIFT                   (0U)
83304 /*! ENVADJ - Envelope Detector Trip Point
83305  *  0b000..0.1000 V
83306  *  0b001..0.1125 V
83307  *  0b010..0.1250 V
83308  *  0b011..0.0875 V
83309  *  0b1xx..
83310  */
83311 #define USBPHY_RX_ENVADJ(x)                      (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_ENVADJ_SHIFT)) & USBPHY_RX_ENVADJ_MASK)
83312 
83313 #define USBPHY_RX_DISCONADJ_MASK                 (0x70U)
83314 #define USBPHY_RX_DISCONADJ_SHIFT                (4U)
83315 /*! DISCONADJ - Disconnect Detector Trip Point
83316  *  0b000..0.56875 V
83317  *  0b001..0.55000 V
83318  *  0b010..0.58125 V
83319  *  0b011..0.60000 V
83320  *  0b1xx..
83321  */
83322 #define USBPHY_RX_DISCONADJ(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_DISCONADJ_SHIFT)) & USBPHY_RX_DISCONADJ_MASK)
83323 /*! @} */
83324 
83325 /*! @name RX_SET - RX Control */
83326 /*! @{ */
83327 
83328 #define USBPHY_RX_SET_ENVADJ_MASK                (0x7U)
83329 #define USBPHY_RX_SET_ENVADJ_SHIFT               (0U)
83330 /*! ENVADJ - Envelope Detector Trip Point */
83331 #define USBPHY_RX_SET_ENVADJ(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_ENVADJ_SHIFT)) & USBPHY_RX_SET_ENVADJ_MASK)
83332 
83333 #define USBPHY_RX_SET_DISCONADJ_MASK             (0x70U)
83334 #define USBPHY_RX_SET_DISCONADJ_SHIFT            (4U)
83335 /*! DISCONADJ - Disconnect Detector Trip Point */
83336 #define USBPHY_RX_SET_DISCONADJ(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_DISCONADJ_SHIFT)) & USBPHY_RX_SET_DISCONADJ_MASK)
83337 /*! @} */
83338 
83339 /*! @name RX_CLR - RX Control */
83340 /*! @{ */
83341 
83342 #define USBPHY_RX_CLR_ENVADJ_MASK                (0x7U)
83343 #define USBPHY_RX_CLR_ENVADJ_SHIFT               (0U)
83344 /*! ENVADJ - Envelope Detector Trip Point */
83345 #define USBPHY_RX_CLR_ENVADJ(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_ENVADJ_SHIFT)) & USBPHY_RX_CLR_ENVADJ_MASK)
83346 
83347 #define USBPHY_RX_CLR_DISCONADJ_MASK             (0x70U)
83348 #define USBPHY_RX_CLR_DISCONADJ_SHIFT            (4U)
83349 /*! DISCONADJ - Disconnect Detector Trip Point */
83350 #define USBPHY_RX_CLR_DISCONADJ(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_DISCONADJ_SHIFT)) & USBPHY_RX_CLR_DISCONADJ_MASK)
83351 /*! @} */
83352 
83353 /*! @name RX_TOG - RX Control */
83354 /*! @{ */
83355 
83356 #define USBPHY_RX_TOG_ENVADJ_MASK                (0x7U)
83357 #define USBPHY_RX_TOG_ENVADJ_SHIFT               (0U)
83358 /*! ENVADJ - Envelope Detector Trip Point */
83359 #define USBPHY_RX_TOG_ENVADJ(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_ENVADJ_SHIFT)) & USBPHY_RX_TOG_ENVADJ_MASK)
83360 
83361 #define USBPHY_RX_TOG_DISCONADJ_MASK             (0x70U)
83362 #define USBPHY_RX_TOG_DISCONADJ_SHIFT            (4U)
83363 /*! DISCONADJ - Disconnect Detector Trip Point */
83364 #define USBPHY_RX_TOG_DISCONADJ(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_DISCONADJ_SHIFT)) & USBPHY_RX_TOG_DISCONADJ_MASK)
83365 /*! @} */
83366 
83367 /*! @name CTRL - General Purpose Control */
83368 /*! @{ */
83369 
83370 #define USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK        (0x1U)
83371 #define USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT       (0U)
83372 /*! ENOTG_ID_CHG_IRQ - OTG ID Change Interrupt Enable
83373  *  0b0..Disable
83374  *  0b1..Enable
83375  */
83376 #define USBPHY_CTRL_ENOTG_ID_CHG_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK)
83377 
83378 #define USBPHY_CTRL_ENHOSTDISCONDETECT_MASK      (0x2U)
83379 #define USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT     (1U)
83380 /*! ENHOSTDISCONDETECT - Host Disconnect Detection Enable
83381  *  0b0..Disable
83382  *  0b1..Enable
83383  */
83384 #define USBPHY_CTRL_ENHOSTDISCONDETECT(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_ENHOSTDISCONDETECT_MASK)
83385 
83386 #define USBPHY_CTRL_ENIRQHOSTDISCON_MASK         (0x4U)
83387 #define USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT        (2U)
83388 /*! ENIRQHOSTDISCON - Enable Interrupt for Host Disconnect
83389  *  0b0..Disable
83390  *  0b1..Enable
83391  */
83392 #define USBPHY_CTRL_ENIRQHOSTDISCON(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_ENIRQHOSTDISCON_MASK)
83393 
83394 #define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK    (0x8U)
83395 #define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT   (3U)
83396 /*! HOSTDISCONDETECT_IRQ - Host Disconnect Detection Interrupt
83397  *  0b0..Connected
83398  *  0b1..Disconnected
83399  */
83400 #define USBPHY_CTRL_HOSTDISCONDETECT_IRQ(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK)
83401 
83402 #define USBPHY_CTRL_ENDEVPLUGINDETECT_MASK       (0x10U)
83403 #define USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT      (4U)
83404 /*! ENDEVPLUGINDETECT - Enable Nonstandard Resistive Plugged-In Detection
83405  *  0b0..Disable
83406  *  0b1..Enable
83407  */
83408 #define USBPHY_CTRL_ENDEVPLUGINDETECT(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_ENDEVPLUGINDETECT_MASK)
83409 
83410 #define USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK      (0x20U)
83411 #define USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT     (5U)
83412 /*! DEVPLUGIN_POLARITY - Device Plug-In Polarity
83413  *  0b0..Plugged in
83414  *  0b1..Unplugged
83415  */
83416 #define USBPHY_CTRL_DEVPLUGIN_POLARITY(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK)
83417 
83418 #define USBPHY_CTRL_OTG_ID_CHG_IRQ_MASK          (0x40U)
83419 #define USBPHY_CTRL_OTG_ID_CHG_IRQ_SHIFT         (6U)
83420 /*! OTG_ID_CHG_IRQ - OTG ID Change Interrupt
83421  *  0b0..No ID change interrupt
83422  *  0b1..ID change interrupt
83423  */
83424 #define USBPHY_CTRL_OTG_ID_CHG_IRQ(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_OTG_ID_CHG_IRQ_MASK)
83425 
83426 #define USBPHY_CTRL_ENOTGIDDETECT_MASK           (0x80U)
83427 #define USBPHY_CTRL_ENOTGIDDETECT_SHIFT          (7U)
83428 /*! ENOTGIDDETECT - Enable Internal OTG ID Detector
83429  *  0b0..Disable
83430  *  0b1..Enable
83431  */
83432 #define USBPHY_CTRL_ENOTGIDDETECT(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_ENOTGIDDETECT_MASK)
83433 
83434 #define USBPHY_CTRL_RESUMEIRQSTICKY_MASK         (0x100U)
83435 #define USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT        (8U)
83436 /*! RESUMEIRQSTICKY - Resume Interrupt Sticky
83437  *  0b0..During the resume or reset state signaling period
83438  *  0b1..Until you write 0 to it
83439  */
83440 #define USBPHY_CTRL_RESUMEIRQSTICKY(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_RESUMEIRQSTICKY_MASK)
83441 
83442 #define USBPHY_CTRL_ENIRQRESUMEDETECT_MASK       (0x200U)
83443 #define USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT      (9U)
83444 /*! ENIRQRESUMEDETECT - Resume Detection Interrupt Enable
83445  *  0b0..Disable
83446  *  0b1..Enable
83447  */
83448 #define USBPHY_CTRL_ENIRQRESUMEDETECT(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_ENIRQRESUMEDETECT_MASK)
83449 
83450 #define USBPHY_CTRL_RESUME_IRQ_MASK              (0x400U)
83451 #define USBPHY_CTRL_RESUME_IRQ_SHIFT             (10U)
83452 /*! RESUME_IRQ - Resume Interrupt
83453  *  0b0..No resume interrupt
83454  *  0b1..Resume interrupt
83455  */
83456 #define USBPHY_CTRL_RESUME_IRQ(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_RESUME_IRQ_MASK)
83457 
83458 #define USBPHY_CTRL_ENIRQDEVPLUGIN_MASK          (0x800U)
83459 #define USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT         (11U)
83460 /*! ENIRQDEVPLUGIN - Enable Interrupt for Nonstandard Resistive Plugged-In Detection
83461  *  0b0..Disable
83462  *  0b1..Enable
83463  */
83464 #define USBPHY_CTRL_ENIRQDEVPLUGIN(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_ENIRQDEVPLUGIN_MASK)
83465 
83466 #define USBPHY_CTRL_DEVPLUGIN_IRQ_MASK           (0x1000U)
83467 #define USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT          (12U)
83468 /*! DEVPLUGIN_IRQ - Device Plug-In Interrupt */
83469 #define USBPHY_CTRL_DEVPLUGIN_IRQ(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_IRQ_MASK)
83470 
83471 #define USBPHY_CTRL_DATA_ON_LRADC_MASK           (0x2000U)
83472 #define USBPHY_CTRL_DATA_ON_LRADC_SHIFT          (13U)
83473 /*! DATA_ON_LRADC - APB Clock Switch Option */
83474 #define USBPHY_CTRL_DATA_ON_LRADC(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_DATA_ON_LRADC_MASK)
83475 
83476 #define USBPHY_CTRL_ENUTMILEVEL2_MASK            (0x4000U)
83477 #define USBPHY_CTRL_ENUTMILEVEL2_SHIFT           (14U)
83478 /*! ENUTMILEVEL2 - UTMI Level 2 Enable
83479  *  0b0..Disable
83480  *  0b1..Enable
83481  */
83482 #define USBPHY_CTRL_ENUTMILEVEL2(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL2_MASK)
83483 
83484 #define USBPHY_CTRL_ENUTMILEVEL3_MASK            (0x8000U)
83485 #define USBPHY_CTRL_ENUTMILEVEL3_SHIFT           (15U)
83486 /*! ENUTMILEVEL3 - UTMI Level 3 Enable
83487  *  0b0..Disable
83488  *  0b1..Enable
83489  */
83490 #define USBPHY_CTRL_ENUTMILEVEL3(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL3_MASK)
83491 
83492 #define USBPHY_CTRL_ENIRQWAKEUP_MASK             (0x10000U)
83493 #define USBPHY_CTRL_ENIRQWAKEUP_SHIFT            (16U)
83494 /*! ENIRQWAKEUP - Wake-Up Interrupt Enable
83495  *  0b0..Disable
83496  *  0b1..Enable
83497  */
83498 #define USBPHY_CTRL_ENIRQWAKEUP(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_ENIRQWAKEUP_MASK)
83499 
83500 #define USBPHY_CTRL_WAKEUP_IRQ_MASK              (0x20000U)
83501 #define USBPHY_CTRL_WAKEUP_IRQ_SHIFT             (17U)
83502 /*! WAKEUP_IRQ - Wake-Up Interrupt */
83503 #define USBPHY_CTRL_WAKEUP_IRQ(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_WAKEUP_IRQ_MASK)
83504 
83505 #define USBPHY_CTRL_AUTORESUME_EN_MASK           (0x40000U)
83506 #define USBPHY_CTRL_AUTORESUME_EN_SHIFT          (18U)
83507 /*! AUTORESUME_EN - Autoresume Enable
83508  *  0b0..Disable
83509  *  0b1..Enable
83510  */
83511 #define USBPHY_CTRL_AUTORESUME_EN(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_AUTORESUME_EN_MASK)
83512 
83513 #define USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK       (0x80000U)
83514 #define USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT      (19U)
83515 /*! ENAUTOCLR_CLKGATE - Autoclear Clock Gate Enable
83516  *  0b0..Disable
83517  *  0b1..Enable
83518  */
83519 #define USBPHY_CTRL_ENAUTOCLR_CLKGATE(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK)
83520 
83521 #define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK       (0x100000U)
83522 #define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT      (20U)
83523 /*! ENAUTOCLR_PHY_PWD - PHY PWD Autoclear Enable
83524  *  0b0..Disable
83525  *  0b1..Enable
83526  */
83527 #define USBPHY_CTRL_ENAUTOCLR_PHY_PWD(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK)
83528 
83529 #define USBPHY_CTRL_OTG_ID_VALUE_MASK            (0x8000000U)
83530 #define USBPHY_CTRL_OTG_ID_VALUE_SHIFT           (27U)
83531 /*! OTG_ID_VALUE - OTG ID Value
83532  *  0b0..Host
83533  *  0b1..Device
83534  */
83535 #define USBPHY_CTRL_OTG_ID_VALUE(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_OTG_ID_VALUE_MASK)
83536 
83537 #define USBPHY_CTRL_UTMI_SUSPENDM_MASK           (0x20000000U)
83538 #define USBPHY_CTRL_UTMI_SUSPENDM_SHIFT          (29U)
83539 /*! UTMI_SUSPENDM - UTMI Suspend
83540  *  0b0..Not suspended
83541  *  0b1..Suspended
83542  */
83543 #define USBPHY_CTRL_UTMI_SUSPENDM(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_UTMI_SUSPENDM_MASK)
83544 
83545 #define USBPHY_CTRL_CLKGATE_MASK                 (0x40000000U)
83546 #define USBPHY_CTRL_CLKGATE_SHIFT                (30U)
83547 /*! CLKGATE - UTMI Clock Gate
83548  *  0b0..Run clocks
83549  *  0b1..Gate clocks
83550  */
83551 #define USBPHY_CTRL_CLKGATE(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLKGATE_SHIFT)) & USBPHY_CTRL_CLKGATE_MASK)
83552 
83553 #define USBPHY_CTRL_SFTRST_MASK                  (0x80000000U)
83554 #define USBPHY_CTRL_SFTRST_SHIFT                 (31U)
83555 /*! SFTRST - Software Reset
83556  *  0b0..Release from reset
83557  *  0b1..Soft-reset
83558  */
83559 #define USBPHY_CTRL_SFTRST(x)                    (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SFTRST_SHIFT)) & USBPHY_CTRL_SFTRST_MASK)
83560 /*! @} */
83561 
83562 /*! @name CTRL_SET - General Purpose Control */
83563 /*! @{ */
83564 
83565 #define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK    (0x1U)
83566 #define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT   (0U)
83567 /*! ENOTG_ID_CHG_IRQ - OTG ID Change Interrupt Enable */
83568 #define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK)
83569 
83570 #define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK  (0x2U)
83571 #define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT (1U)
83572 /*! ENHOSTDISCONDETECT - Host Disconnect Detection Enable */
83573 #define USBPHY_CTRL_SET_ENHOSTDISCONDETECT(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK)
83574 
83575 #define USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK     (0x4U)
83576 #define USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT    (2U)
83577 /*! ENIRQHOSTDISCON - Enable Interrupt for Host Disconnect */
83578 #define USBPHY_CTRL_SET_ENIRQHOSTDISCON(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK)
83579 
83580 #define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK (0x8U)
83581 #define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT (3U)
83582 /*! HOSTDISCONDETECT_IRQ - Host Disconnect Detection Interrupt */
83583 #define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK)
83584 
83585 #define USBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK   (0x10U)
83586 #define USBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT  (4U)
83587 /*! ENDEVPLUGINDETECT - Enable Nonstandard Resistive Plugged-In Detection */
83588 #define USBPHY_CTRL_SET_ENDEVPLUGINDETECT(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK)
83589 
83590 #define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK  (0x20U)
83591 #define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT (5U)
83592 /*! DEVPLUGIN_POLARITY - Device Plug-In Polarity */
83593 #define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK)
83594 
83595 #define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_MASK      (0x40U)
83596 #define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_SHIFT     (6U)
83597 /*! OTG_ID_CHG_IRQ - OTG ID Change Interrupt */
83598 #define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_MASK)
83599 
83600 #define USBPHY_CTRL_SET_ENOTGIDDETECT_MASK       (0x80U)
83601 #define USBPHY_CTRL_SET_ENOTGIDDETECT_SHIFT      (7U)
83602 /*! ENOTGIDDETECT - Enable Internal OTG ID Detector */
83603 #define USBPHY_CTRL_SET_ENOTGIDDETECT(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_SET_ENOTGIDDETECT_MASK)
83604 
83605 #define USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK     (0x100U)
83606 #define USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT    (8U)
83607 /*! RESUMEIRQSTICKY - Resume Interrupt Sticky */
83608 #define USBPHY_CTRL_SET_RESUMEIRQSTICKY(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK)
83609 
83610 #define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK   (0x200U)
83611 #define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT  (9U)
83612 /*! ENIRQRESUMEDETECT - Resume Detection Interrupt Enable */
83613 #define USBPHY_CTRL_SET_ENIRQRESUMEDETECT(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK)
83614 
83615 #define USBPHY_CTRL_SET_RESUME_IRQ_MASK          (0x400U)
83616 #define USBPHY_CTRL_SET_RESUME_IRQ_SHIFT         (10U)
83617 /*! RESUME_IRQ - Resume Interrupt */
83618 #define USBPHY_CTRL_SET_RESUME_IRQ(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_SET_RESUME_IRQ_MASK)
83619 
83620 #define USBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK      (0x800U)
83621 #define USBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT     (11U)
83622 /*! ENIRQDEVPLUGIN - Enable Interrupt for Nonstandard Resistive Plugged-In Detection */
83623 #define USBPHY_CTRL_SET_ENIRQDEVPLUGIN(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK)
83624 
83625 #define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK       (0x1000U)
83626 #define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT      (12U)
83627 /*! DEVPLUGIN_IRQ - Device Plug-In Interrupt */
83628 #define USBPHY_CTRL_SET_DEVPLUGIN_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK)
83629 
83630 #define USBPHY_CTRL_SET_DATA_ON_LRADC_MASK       (0x2000U)
83631 #define USBPHY_CTRL_SET_DATA_ON_LRADC_SHIFT      (13U)
83632 /*! DATA_ON_LRADC - APB Clock Switch Option */
83633 #define USBPHY_CTRL_SET_DATA_ON_LRADC(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_SET_DATA_ON_LRADC_MASK)
83634 
83635 #define USBPHY_CTRL_SET_ENUTMILEVEL2_MASK        (0x4000U)
83636 #define USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT       (14U)
83637 /*! ENUTMILEVEL2 - UTMI Level 2 Enable */
83638 #define USBPHY_CTRL_SET_ENUTMILEVEL2(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL2_MASK)
83639 
83640 #define USBPHY_CTRL_SET_ENUTMILEVEL3_MASK        (0x8000U)
83641 #define USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT       (15U)
83642 /*! ENUTMILEVEL3 - UTMI Level 3 Enable */
83643 #define USBPHY_CTRL_SET_ENUTMILEVEL3(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL3_MASK)
83644 
83645 #define USBPHY_CTRL_SET_ENIRQWAKEUP_MASK         (0x10000U)
83646 #define USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT        (16U)
83647 /*! ENIRQWAKEUP - Wake-Up Interrupt Enable */
83648 #define USBPHY_CTRL_SET_ENIRQWAKEUP(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_SET_ENIRQWAKEUP_MASK)
83649 
83650 #define USBPHY_CTRL_SET_WAKEUP_IRQ_MASK          (0x20000U)
83651 #define USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT         (17U)
83652 /*! WAKEUP_IRQ - Wake-Up Interrupt */
83653 #define USBPHY_CTRL_SET_WAKEUP_IRQ(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_SET_WAKEUP_IRQ_MASK)
83654 
83655 #define USBPHY_CTRL_SET_AUTORESUME_EN_MASK       (0x40000U)
83656 #define USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT      (18U)
83657 /*! AUTORESUME_EN - Autoresume Enable */
83658 #define USBPHY_CTRL_SET_AUTORESUME_EN(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_SET_AUTORESUME_EN_MASK)
83659 
83660 #define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK   (0x80000U)
83661 #define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT  (19U)
83662 /*! ENAUTOCLR_CLKGATE - Autoclear Clock Gate Enable */
83663 #define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK)
83664 
83665 #define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK   (0x100000U)
83666 #define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT  (20U)
83667 /*! ENAUTOCLR_PHY_PWD - PHY PWD Autoclear Enable */
83668 #define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK)
83669 
83670 #define USBPHY_CTRL_SET_OTG_ID_VALUE_MASK        (0x8000000U)
83671 #define USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT       (27U)
83672 /*! OTG_ID_VALUE - OTG ID Value */
83673 #define USBPHY_CTRL_SET_OTG_ID_VALUE(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_VALUE_MASK)
83674 
83675 #define USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK       (0x20000000U)
83676 #define USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT      (29U)
83677 /*! UTMI_SUSPENDM - UTMI Suspend */
83678 #define USBPHY_CTRL_SET_UTMI_SUSPENDM(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK)
83679 
83680 #define USBPHY_CTRL_SET_CLKGATE_MASK             (0x40000000U)
83681 #define USBPHY_CTRL_SET_CLKGATE_SHIFT            (30U)
83682 /*! CLKGATE - UTMI Clock Gate */
83683 #define USBPHY_CTRL_SET_CLKGATE(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_CLKGATE_MASK)
83684 
83685 #define USBPHY_CTRL_SET_SFTRST_MASK              (0x80000000U)
83686 #define USBPHY_CTRL_SET_SFTRST_SHIFT             (31U)
83687 /*! SFTRST - Software Reset */
83688 #define USBPHY_CTRL_SET_SFTRST(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_SFTRST_SHIFT)) & USBPHY_CTRL_SET_SFTRST_MASK)
83689 /*! @} */
83690 
83691 /*! @name CTRL_CLR - General Purpose Control */
83692 /*! @{ */
83693 
83694 #define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK    (0x1U)
83695 #define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT   (0U)
83696 /*! ENOTG_ID_CHG_IRQ - OTG ID Change Interrupt Enable */
83697 #define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK)
83698 
83699 #define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK  (0x2U)
83700 #define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT (1U)
83701 /*! ENHOSTDISCONDETECT - Host Disconnect Detection Enable */
83702 #define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK)
83703 
83704 #define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK     (0x4U)
83705 #define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT    (2U)
83706 /*! ENIRQHOSTDISCON - Enable Interrupt for Host Disconnect */
83707 #define USBPHY_CTRL_CLR_ENIRQHOSTDISCON(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK)
83708 
83709 #define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK (0x8U)
83710 #define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT (3U)
83711 /*! HOSTDISCONDETECT_IRQ - Host Disconnect Detection Interrupt */
83712 #define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK)
83713 
83714 #define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK   (0x10U)
83715 #define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT  (4U)
83716 /*! ENDEVPLUGINDETECT - Enable Nonstandard Resistive Plugged-In Detection */
83717 #define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK)
83718 
83719 #define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK  (0x20U)
83720 #define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT (5U)
83721 /*! DEVPLUGIN_POLARITY - Device Plug-In Polarity */
83722 #define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK)
83723 
83724 #define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_MASK      (0x40U)
83725 #define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_SHIFT     (6U)
83726 /*! OTG_ID_CHG_IRQ - OTG ID Change Interrupt */
83727 #define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_MASK)
83728 
83729 #define USBPHY_CTRL_CLR_ENOTGIDDETECT_MASK       (0x80U)
83730 #define USBPHY_CTRL_CLR_ENOTGIDDETECT_SHIFT      (7U)
83731 /*! ENOTGIDDETECT - Enable Internal OTG ID Detector */
83732 #define USBPHY_CTRL_CLR_ENOTGIDDETECT(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENOTGIDDETECT_MASK)
83733 
83734 #define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK     (0x100U)
83735 #define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT    (8U)
83736 /*! RESUMEIRQSTICKY - Resume Interrupt Sticky */
83737 #define USBPHY_CTRL_CLR_RESUMEIRQSTICKY(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK)
83738 
83739 #define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK   (0x200U)
83740 #define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT  (9U)
83741 /*! ENIRQRESUMEDETECT - Resume Detection Interrupt Enable */
83742 #define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK)
83743 
83744 #define USBPHY_CTRL_CLR_RESUME_IRQ_MASK          (0x400U)
83745 #define USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT         (10U)
83746 /*! RESUME_IRQ - Resume Interrupt */
83747 #define USBPHY_CTRL_CLR_RESUME_IRQ(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_CLR_RESUME_IRQ_MASK)
83748 
83749 #define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK      (0x800U)
83750 #define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT     (11U)
83751 /*! ENIRQDEVPLUGIN - Enable Interrupt for Nonstandard Resistive Plugged-In Detection */
83752 #define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK)
83753 
83754 #define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK       (0x1000U)
83755 #define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT      (12U)
83756 /*! DEVPLUGIN_IRQ - Device Plug-In Interrupt */
83757 #define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK)
83758 
83759 #define USBPHY_CTRL_CLR_DATA_ON_LRADC_MASK       (0x2000U)
83760 #define USBPHY_CTRL_CLR_DATA_ON_LRADC_SHIFT      (13U)
83761 /*! DATA_ON_LRADC - APB Clock Switch Option */
83762 #define USBPHY_CTRL_CLR_DATA_ON_LRADC(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_CLR_DATA_ON_LRADC_MASK)
83763 
83764 #define USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK        (0x4000U)
83765 #define USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT       (14U)
83766 /*! ENUTMILEVEL2 - UTMI Level 2 Enable */
83767 #define USBPHY_CTRL_CLR_ENUTMILEVEL2(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK)
83768 
83769 #define USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK        (0x8000U)
83770 #define USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT       (15U)
83771 /*! ENUTMILEVEL3 - UTMI Level 3 Enable */
83772 #define USBPHY_CTRL_CLR_ENUTMILEVEL3(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK)
83773 
83774 #define USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK         (0x10000U)
83775 #define USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT        (16U)
83776 /*! ENIRQWAKEUP - Wake-Up Interrupt Enable */
83777 #define USBPHY_CTRL_CLR_ENIRQWAKEUP(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK)
83778 
83779 #define USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK          (0x20000U)
83780 #define USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT         (17U)
83781 /*! WAKEUP_IRQ - Wake-Up Interrupt */
83782 #define USBPHY_CTRL_CLR_WAKEUP_IRQ(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK)
83783 
83784 #define USBPHY_CTRL_CLR_AUTORESUME_EN_MASK       (0x40000U)
83785 #define USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT      (18U)
83786 /*! AUTORESUME_EN - Autoresume Enable */
83787 #define USBPHY_CTRL_CLR_AUTORESUME_EN(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_CLR_AUTORESUME_EN_MASK)
83788 
83789 #define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK   (0x80000U)
83790 #define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT  (19U)
83791 /*! ENAUTOCLR_CLKGATE - Autoclear Clock Gate Enable */
83792 #define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK)
83793 
83794 #define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK   (0x100000U)
83795 #define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT  (20U)
83796 /*! ENAUTOCLR_PHY_PWD - PHY PWD Autoclear Enable */
83797 #define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK)
83798 
83799 #define USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK        (0x8000000U)
83800 #define USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT       (27U)
83801 /*! OTG_ID_VALUE - OTG ID Value */
83802 #define USBPHY_CTRL_CLR_OTG_ID_VALUE(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK)
83803 
83804 #define USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK       (0x20000000U)
83805 #define USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT      (29U)
83806 /*! UTMI_SUSPENDM - UTMI Suspend */
83807 #define USBPHY_CTRL_CLR_UTMI_SUSPENDM(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK)
83808 
83809 #define USBPHY_CTRL_CLR_CLKGATE_MASK             (0x40000000U)
83810 #define USBPHY_CTRL_CLR_CLKGATE_SHIFT            (30U)
83811 /*! CLKGATE - UTMI Clock Gate */
83812 #define USBPHY_CTRL_CLR_CLKGATE(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_CLKGATE_MASK)
83813 
83814 #define USBPHY_CTRL_CLR_SFTRST_MASK              (0x80000000U)
83815 #define USBPHY_CTRL_CLR_SFTRST_SHIFT             (31U)
83816 /*! SFTRST - Software Reset */
83817 #define USBPHY_CTRL_CLR_SFTRST(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_SFTRST_SHIFT)) & USBPHY_CTRL_CLR_SFTRST_MASK)
83818 /*! @} */
83819 
83820 /*! @name CTRL_TOG - General Purpose Control */
83821 /*! @{ */
83822 
83823 #define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK    (0x1U)
83824 #define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT   (0U)
83825 /*! ENOTG_ID_CHG_IRQ - OTG ID Change Interrupt Enable */
83826 #define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK)
83827 
83828 #define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK  (0x2U)
83829 #define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT (1U)
83830 /*! ENHOSTDISCONDETECT - Host Disconnect Detection Enable */
83831 #define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK)
83832 
83833 #define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK     (0x4U)
83834 #define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT    (2U)
83835 /*! ENIRQHOSTDISCON - Enable Interrupt for Host Disconnect */
83836 #define USBPHY_CTRL_TOG_ENIRQHOSTDISCON(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK)
83837 
83838 #define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK (0x8U)
83839 #define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT (3U)
83840 /*! HOSTDISCONDETECT_IRQ - Host Disconnect Detection Interrupt */
83841 #define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK)
83842 
83843 #define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK   (0x10U)
83844 #define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT  (4U)
83845 /*! ENDEVPLUGINDETECT - Enable Nonstandard Resistive Plugged-In Detection */
83846 #define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK)
83847 
83848 #define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK  (0x20U)
83849 #define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT (5U)
83850 /*! DEVPLUGIN_POLARITY - Device Plug-In Polarity */
83851 #define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK)
83852 
83853 #define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_MASK      (0x40U)
83854 #define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_SHIFT     (6U)
83855 /*! OTG_ID_CHG_IRQ - OTG ID Change Interrupt */
83856 #define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_MASK)
83857 
83858 #define USBPHY_CTRL_TOG_ENOTGIDDETECT_MASK       (0x80U)
83859 #define USBPHY_CTRL_TOG_ENOTGIDDETECT_SHIFT      (7U)
83860 /*! ENOTGIDDETECT - Enable Internal OTG ID Detector */
83861 #define USBPHY_CTRL_TOG_ENOTGIDDETECT(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENOTGIDDETECT_MASK)
83862 
83863 #define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK     (0x100U)
83864 #define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT    (8U)
83865 /*! RESUMEIRQSTICKY - Resume Interrupt Sticky */
83866 #define USBPHY_CTRL_TOG_RESUMEIRQSTICKY(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK)
83867 
83868 #define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK   (0x200U)
83869 #define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT  (9U)
83870 /*! ENIRQRESUMEDETECT - Resume Detection Interrupt Enable */
83871 #define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK)
83872 
83873 #define USBPHY_CTRL_TOG_RESUME_IRQ_MASK          (0x400U)
83874 #define USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT         (10U)
83875 /*! RESUME_IRQ - Resume Interrupt */
83876 #define USBPHY_CTRL_TOG_RESUME_IRQ(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_TOG_RESUME_IRQ_MASK)
83877 
83878 #define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK      (0x800U)
83879 #define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT     (11U)
83880 /*! ENIRQDEVPLUGIN - Enable Interrupt for Nonstandard Resistive Plugged-In Detection */
83881 #define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK)
83882 
83883 #define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK       (0x1000U)
83884 #define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT      (12U)
83885 /*! DEVPLUGIN_IRQ - Device Plug-In Interrupt */
83886 #define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK)
83887 
83888 #define USBPHY_CTRL_TOG_DATA_ON_LRADC_MASK       (0x2000U)
83889 #define USBPHY_CTRL_TOG_DATA_ON_LRADC_SHIFT      (13U)
83890 /*! DATA_ON_LRADC - APB Clock Switch Option */
83891 #define USBPHY_CTRL_TOG_DATA_ON_LRADC(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_TOG_DATA_ON_LRADC_MASK)
83892 
83893 #define USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK        (0x4000U)
83894 #define USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT       (14U)
83895 /*! ENUTMILEVEL2 - UTMI Level 2 Enable */
83896 #define USBPHY_CTRL_TOG_ENUTMILEVEL2(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK)
83897 
83898 #define USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK        (0x8000U)
83899 #define USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT       (15U)
83900 /*! ENUTMILEVEL3 - UTMI Level 3 Enable */
83901 #define USBPHY_CTRL_TOG_ENUTMILEVEL3(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK)
83902 
83903 #define USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK         (0x10000U)
83904 #define USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT        (16U)
83905 /*! ENIRQWAKEUP - Wake-Up Interrupt Enable */
83906 #define USBPHY_CTRL_TOG_ENIRQWAKEUP(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK)
83907 
83908 #define USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK          (0x20000U)
83909 #define USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT         (17U)
83910 /*! WAKEUP_IRQ - Wake-Up Interrupt */
83911 #define USBPHY_CTRL_TOG_WAKEUP_IRQ(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK)
83912 
83913 #define USBPHY_CTRL_TOG_AUTORESUME_EN_MASK       (0x40000U)
83914 #define USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT      (18U)
83915 /*! AUTORESUME_EN - Autoresume Enable */
83916 #define USBPHY_CTRL_TOG_AUTORESUME_EN(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_TOG_AUTORESUME_EN_MASK)
83917 
83918 #define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK   (0x80000U)
83919 #define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT  (19U)
83920 /*! ENAUTOCLR_CLKGATE - Autoclear Clock Gate Enable */
83921 #define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK)
83922 
83923 #define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK   (0x100000U)
83924 #define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT  (20U)
83925 /*! ENAUTOCLR_PHY_PWD - PHY PWD Autoclear Enable */
83926 #define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK)
83927 
83928 #define USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK        (0x8000000U)
83929 #define USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT       (27U)
83930 /*! OTG_ID_VALUE - OTG ID Value */
83931 #define USBPHY_CTRL_TOG_OTG_ID_VALUE(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK)
83932 
83933 #define USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK       (0x20000000U)
83934 #define USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT      (29U)
83935 /*! UTMI_SUSPENDM - UTMI Suspend */
83936 #define USBPHY_CTRL_TOG_UTMI_SUSPENDM(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK)
83937 
83938 #define USBPHY_CTRL_TOG_CLKGATE_MASK             (0x40000000U)
83939 #define USBPHY_CTRL_TOG_CLKGATE_SHIFT            (30U)
83940 /*! CLKGATE - UTMI Clock Gate */
83941 #define USBPHY_CTRL_TOG_CLKGATE(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_CLKGATE_MASK)
83942 
83943 #define USBPHY_CTRL_TOG_SFTRST_MASK              (0x80000000U)
83944 #define USBPHY_CTRL_TOG_SFTRST_SHIFT             (31U)
83945 /*! SFTRST - Software Reset */
83946 #define USBPHY_CTRL_TOG_SFTRST(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_SFTRST_SHIFT)) & USBPHY_CTRL_TOG_SFTRST_MASK)
83947 /*! @} */
83948 
83949 /*! @name STATUS - Status */
83950 /*! @{ */
83951 
83952 #define USBPHY_STATUS_OK_STATUS_3V_MASK          (0x1U)
83953 #define USBPHY_STATUS_OK_STATUS_3V_SHIFT         (0U)
83954 /*! OK_STATUS_3V - USB 3.3 V and 1.8 V Supply Status
83955  *  0b0..Not powered
83956  *  0b1..Powered
83957  */
83958 #define USBPHY_STATUS_OK_STATUS_3V(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_OK_STATUS_3V_SHIFT)) & USBPHY_STATUS_OK_STATUS_3V_MASK)
83959 
83960 #define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK (0x8U)
83961 #define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT (3U)
83962 /*! HOSTDISCONDETECT_STATUS - Host Disconnect Status
83963  *  0b0..Not detected
83964  *  0b1..Detected
83965  */
83966 #define USBPHY_STATUS_HOSTDISCONDETECT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT)) & USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK)
83967 
83968 #define USBPHY_STATUS_DEVPLUGIN_STATUS_MASK      (0x40U)
83969 #define USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT     (6U)
83970 /*! DEVPLUGIN_STATUS - Status Indicator for Nonstandard Resistive Plugged-In Detection
83971  *  0b0..No attachment detected
83972  *  0b1..Cable attachment detected
83973  */
83974 #define USBPHY_STATUS_DEVPLUGIN_STATUS(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT)) & USBPHY_STATUS_DEVPLUGIN_STATUS_MASK)
83975 
83976 #define USBPHY_STATUS_OTGID_STATUS_MASK          (0x100U)
83977 #define USBPHY_STATUS_OTGID_STATUS_SHIFT         (8U)
83978 /*! OTGID_STATUS - OTG ID Status
83979  *  0b0..Host
83980  *  0b1..Device
83981  */
83982 #define USBPHY_STATUS_OTGID_STATUS(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_OTGID_STATUS_SHIFT)) & USBPHY_STATUS_OTGID_STATUS_MASK)
83983 
83984 #define USBPHY_STATUS_RESUME_STATUS_MASK         (0x400U)
83985 #define USBPHY_STATUS_RESUME_STATUS_SHIFT        (10U)
83986 /*! RESUME_STATUS - Resume Status */
83987 #define USBPHY_STATUS_RESUME_STATUS(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RESUME_STATUS_SHIFT)) & USBPHY_STATUS_RESUME_STATUS_MASK)
83988 /*! @} */
83989 
83990 /*! @name DEBUG0 - Debug 0 */
83991 /*! @{ */
83992 
83993 #define USBPHY_DEBUG0_OTGIDPIOLOCK_MASK          (0x1U)
83994 #define USBPHY_DEBUG0_OTGIDPIOLOCK_SHIFT         (0U)
83995 /*! OTGIDPIOLOCK - Hold OTG_ID */
83996 #define USBPHY_DEBUG0_OTGIDPIOLOCK(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG0_OTGIDPIOLOCK_MASK)
83997 
83998 #define USBPHY_DEBUG0_HSTPULLDOWN_MASK           (0xCU)
83999 #define USBPHY_DEBUG0_HSTPULLDOWN_SHIFT          (2U)
84000 /*! HSTPULLDOWN - Host Pulldown Overdrive Mode
84001  *  0b00..Disconnect
84002  *  0b01..Connect
84003  */
84004 #define USBPHY_DEBUG0_HSTPULLDOWN(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_HSTPULLDOWN_MASK)
84005 
84006 #define USBPHY_DEBUG0_ENHSTPULLDOWN_MASK         (0x30U)
84007 #define USBPHY_DEBUG0_ENHSTPULLDOWN_SHIFT        (4U)
84008 /*! ENHSTPULLDOWN - Enable Host Pulldown Overdrive Mode
84009  *  0b00..Disable
84010  *  0b01..Enable
84011  */
84012 #define USBPHY_DEBUG0_ENHSTPULLDOWN(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_ENHSTPULLDOWN_MASK)
84013 /*! @} */
84014 
84015 /*! @name DEBUG0_SET - Debug 0 */
84016 /*! @{ */
84017 
84018 #define USBPHY_DEBUG0_SET_OTGIDPIOLOCK_MASK      (0x1U)
84019 #define USBPHY_DEBUG0_SET_OTGIDPIOLOCK_SHIFT     (0U)
84020 /*! OTGIDPIOLOCK - Hold OTG_ID */
84021 #define USBPHY_DEBUG0_SET_OTGIDPIOLOCK(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG0_SET_OTGIDPIOLOCK_MASK)
84022 
84023 #define USBPHY_DEBUG0_SET_HSTPULLDOWN_MASK       (0xCU)
84024 #define USBPHY_DEBUG0_SET_HSTPULLDOWN_SHIFT      (2U)
84025 /*! HSTPULLDOWN - Host Pulldown Overdrive Mode */
84026 #define USBPHY_DEBUG0_SET_HSTPULLDOWN(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_SET_HSTPULLDOWN_MASK)
84027 
84028 #define USBPHY_DEBUG0_SET_ENHSTPULLDOWN_MASK     (0x30U)
84029 #define USBPHY_DEBUG0_SET_ENHSTPULLDOWN_SHIFT    (4U)
84030 /*! ENHSTPULLDOWN - Enable Host Pulldown Overdrive Mode */
84031 #define USBPHY_DEBUG0_SET_ENHSTPULLDOWN(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_SET_ENHSTPULLDOWN_MASK)
84032 /*! @} */
84033 
84034 /*! @name DEBUG0_CLR - Debug 0 */
84035 /*! @{ */
84036 
84037 #define USBPHY_DEBUG0_CLR_OTGIDPIOLOCK_MASK      (0x1U)
84038 #define USBPHY_DEBUG0_CLR_OTGIDPIOLOCK_SHIFT     (0U)
84039 /*! OTGIDPIOLOCK - Hold OTG_ID */
84040 #define USBPHY_DEBUG0_CLR_OTGIDPIOLOCK(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG0_CLR_OTGIDPIOLOCK_MASK)
84041 
84042 #define USBPHY_DEBUG0_CLR_HSTPULLDOWN_MASK       (0xCU)
84043 #define USBPHY_DEBUG0_CLR_HSTPULLDOWN_SHIFT      (2U)
84044 /*! HSTPULLDOWN - Host Pulldown Overdrive Mode */
84045 #define USBPHY_DEBUG0_CLR_HSTPULLDOWN(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_CLR_HSTPULLDOWN_MASK)
84046 
84047 #define USBPHY_DEBUG0_CLR_ENHSTPULLDOWN_MASK     (0x30U)
84048 #define USBPHY_DEBUG0_CLR_ENHSTPULLDOWN_SHIFT    (4U)
84049 /*! ENHSTPULLDOWN - Enable Host Pulldown Overdrive Mode */
84050 #define USBPHY_DEBUG0_CLR_ENHSTPULLDOWN(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_CLR_ENHSTPULLDOWN_MASK)
84051 /*! @} */
84052 
84053 /*! @name DEBUG0_TOG - Debug 0 */
84054 /*! @{ */
84055 
84056 #define USBPHY_DEBUG0_TOG_OTGIDPIOLOCK_MASK      (0x1U)
84057 #define USBPHY_DEBUG0_TOG_OTGIDPIOLOCK_SHIFT     (0U)
84058 /*! OTGIDPIOLOCK - Hold OTG_ID */
84059 #define USBPHY_DEBUG0_TOG_OTGIDPIOLOCK(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG0_TOG_OTGIDPIOLOCK_MASK)
84060 
84061 #define USBPHY_DEBUG0_TOG_HSTPULLDOWN_MASK       (0xCU)
84062 #define USBPHY_DEBUG0_TOG_HSTPULLDOWN_SHIFT      (2U)
84063 /*! HSTPULLDOWN - Host Pulldown Overdrive Mode */
84064 #define USBPHY_DEBUG0_TOG_HSTPULLDOWN(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_TOG_HSTPULLDOWN_MASK)
84065 
84066 #define USBPHY_DEBUG0_TOG_ENHSTPULLDOWN_MASK     (0x30U)
84067 #define USBPHY_DEBUG0_TOG_ENHSTPULLDOWN_SHIFT    (4U)
84068 /*! ENHSTPULLDOWN - Enable Host Pulldown Overdrive Mode */
84069 #define USBPHY_DEBUG0_TOG_ENHSTPULLDOWN(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_TOG_ENHSTPULLDOWN_MASK)
84070 /*! @} */
84071 
84072 /*! @name VERSION - Version */
84073 /*! @{ */
84074 
84075 #define USBPHY_VERSION_STEP_MASK                 (0xFFFFU)
84076 #define USBPHY_VERSION_STEP_SHIFT                (0U)
84077 /*! STEP - Step */
84078 #define USBPHY_VERSION_STEP(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_STEP_SHIFT)) & USBPHY_VERSION_STEP_MASK)
84079 
84080 #define USBPHY_VERSION_MINOR_MASK                (0xFF0000U)
84081 #define USBPHY_VERSION_MINOR_SHIFT               (16U)
84082 /*! MINOR - Minor */
84083 #define USBPHY_VERSION_MINOR(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MINOR_SHIFT)) & USBPHY_VERSION_MINOR_MASK)
84084 
84085 #define USBPHY_VERSION_MAJOR_MASK                (0xFF000000U)
84086 #define USBPHY_VERSION_MAJOR_SHIFT               (24U)
84087 /*! MAJOR - Major */
84088 #define USBPHY_VERSION_MAJOR(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MAJOR_SHIFT)) & USBPHY_VERSION_MAJOR_MASK)
84089 /*! @} */
84090 
84091 /*! @name IP - IP Block */
84092 /*! @{ */
84093 
84094 #define USBPHY_IP_POWER_CONTROL_SUSPEND_OPTION_MASK (0x1U)
84095 #define USBPHY_IP_POWER_CONTROL_SUSPEND_OPTION_SHIFT (0U)
84096 /*! POWER_CONTROL_SUSPEND_OPTION - Power Control Suspend Option */
84097 #define USBPHY_IP_POWER_CONTROL_SUSPEND_OPTION(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_IP_POWER_CONTROL_SUSPEND_OPTION_SHIFT)) & USBPHY_IP_POWER_CONTROL_SUSPEND_OPTION_MASK)
84098 /*! @} */
84099 
84100 /*! @name IP_SET - IP Block */
84101 /*! @{ */
84102 
84103 #define USBPHY_IP_SET_POWER_CONTROL_SUSPEND_OPTION_MASK (0x1U)
84104 #define USBPHY_IP_SET_POWER_CONTROL_SUSPEND_OPTION_SHIFT (0U)
84105 /*! POWER_CONTROL_SUSPEND_OPTION - Power Control Suspend Option */
84106 #define USBPHY_IP_SET_POWER_CONTROL_SUSPEND_OPTION(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_IP_SET_POWER_CONTROL_SUSPEND_OPTION_SHIFT)) & USBPHY_IP_SET_POWER_CONTROL_SUSPEND_OPTION_MASK)
84107 /*! @} */
84108 
84109 /*! @name IP_CLR - IP Block */
84110 /*! @{ */
84111 
84112 #define USBPHY_IP_CLR_POWER_CONTROL_SUSPEND_OPTION_MASK (0x1U)
84113 #define USBPHY_IP_CLR_POWER_CONTROL_SUSPEND_OPTION_SHIFT (0U)
84114 /*! POWER_CONTROL_SUSPEND_OPTION - Power Control Suspend Option */
84115 #define USBPHY_IP_CLR_POWER_CONTROL_SUSPEND_OPTION(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_IP_CLR_POWER_CONTROL_SUSPEND_OPTION_SHIFT)) & USBPHY_IP_CLR_POWER_CONTROL_SUSPEND_OPTION_MASK)
84116 /*! @} */
84117 
84118 /*! @name IP_TOG - IP Block */
84119 /*! @{ */
84120 
84121 #define USBPHY_IP_TOG_POWER_CONTROL_SUSPEND_OPTION_MASK (0x1U)
84122 #define USBPHY_IP_TOG_POWER_CONTROL_SUSPEND_OPTION_SHIFT (0U)
84123 /*! POWER_CONTROL_SUSPEND_OPTION - Power Control Suspend Option */
84124 #define USBPHY_IP_TOG_POWER_CONTROL_SUSPEND_OPTION(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_IP_TOG_POWER_CONTROL_SUSPEND_OPTION_SHIFT)) & USBPHY_IP_TOG_POWER_CONTROL_SUSPEND_OPTION_MASK)
84125 /*! @} */
84126 
84127 /*! @name PLL_SIC - PLL SIC */
84128 /*! @{ */
84129 
84130 #define USBPHY_PLL_SIC_MISC2_CONTROL0_MASK       (0x20U)
84131 #define USBPHY_PLL_SIC_MISC2_CONTROL0_SHIFT      (5U)
84132 /*! MISC2_CONTROL0 - Miscellaneous Control
84133  *  0b0..Power up PLL
84134  *  0b1..Power down PLL
84135  */
84136 #define USBPHY_PLL_SIC_MISC2_CONTROL0(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_MISC2_CONTROL0_SHIFT)) & USBPHY_PLL_SIC_MISC2_CONTROL0_MASK)
84137 
84138 #define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK      (0x40U)
84139 #define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT     (6U)
84140 /*! PLL_EN_USB_CLKS - PLL Multi-Phase Clock Outputs Enable
84141  *  0b0..Disable
84142  *  0b1..Enable
84143  */
84144 #define USBPHY_PLL_SIC_PLL_EN_USB_CLKS(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK)
84145 
84146 #define USBPHY_PLL_SIC_PLL_POWER_MASK            (0x1000U)
84147 #define USBPHY_PLL_SIC_PLL_POWER_SHIFT           (12U)
84148 /*! PLL_POWER - USB PLL Powerup Control
84149  *  0b0..Power down
84150  *  0b1..Allow powerup
84151  */
84152 #define USBPHY_PLL_SIC_PLL_POWER(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_PLL_POWER_MASK)
84153 
84154 #define USBPHY_PLL_SIC_PLL_ENABLE_MASK           (0x2000U)
84155 #define USBPHY_PLL_SIC_PLL_ENABLE_SHIFT          (13U)
84156 /*! PLL_ENABLE - PLL Output Clock Enable
84157  *  0b0..Disable
84158  *  0b1..Enable
84159  */
84160 #define USBPHY_PLL_SIC_PLL_ENABLE(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_ENABLE_MASK)
84161 
84162 #define USBPHY_PLL_SIC_PLL_BYPASS_MASK           (0x10000U)
84163 #define USBPHY_PLL_SIC_PLL_BYPASS_SHIFT          (16U)
84164 /*! PLL_BYPASS - Bypass USB PLL
84165  *  0b0..480 MHz output clock
84166  *  0b1..Input reference clock
84167  */
84168 #define USBPHY_PLL_SIC_PLL_BYPASS(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_PLL_BYPASS_MASK)
84169 
84170 #define USBPHY_PLL_SIC_REFBIAS_PWD_SEL_MASK      (0x80000U)
84171 #define USBPHY_PLL_SIC_REFBIAS_PWD_SEL_SHIFT     (19U)
84172 /*! REFBIAS_PWD_SEL - Reference Bias Power Control
84173  *  0b0..PLL_POWER internal state signal
84174  *  0b1..REFBIAS_PWD
84175  */
84176 #define USBPHY_PLL_SIC_REFBIAS_PWD_SEL(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_REFBIAS_PWD_SEL_MASK)
84177 
84178 #define USBPHY_PLL_SIC_REFBIAS_PWD_MASK          (0x100000U)
84179 #define USBPHY_PLL_SIC_REFBIAS_PWD_SHIFT         (20U)
84180 /*! REFBIAS_PWD - Power Down Reference Bias
84181  *  0b0..Enable
84182  *  0b1..Disable or power down
84183  */
84184 #define USBPHY_PLL_SIC_REFBIAS_PWD(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_REFBIAS_PWD_MASK)
84185 
84186 #define USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK       (0x200000U)
84187 #define USBPHY_PLL_SIC_PLL_REG_ENABLE_SHIFT      (21U)
84188 /*! PLL_REG_ENABLE - Enable PLL Regulator
84189  *  0b0..Disable
84190  *  0b1..Enable
84191  */
84192 #define USBPHY_PLL_SIC_PLL_REG_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK)
84193 
84194 #define USBPHY_PLL_SIC_PLL_DIV_SEL_MASK          (0x1C00000U)
84195 #define USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT         (22U)
84196 /*! PLL_DIV_SEL - PLL Divider Value Configuration
84197  *  0b000..Configure for a 32 MHz input clock (divide by 15)
84198  *  0b001..Configure for a 30 MHz input clock (divide by 16)
84199  *  0b010..Configure for a 24 MHz input clock (divide by 20)
84200  *  0b011..Reserved, not usable for USB operation (divide by 22)
84201  *  0b100..Configure for a 20 MHz input clock (divide by 24)
84202  *  0b101..Configure for a 19.2 MHz input clock (divide by 25)
84203  *  0b110..Configure for a 16 MHz input clock (divide by 30)
84204  *  0b111..Configure for a 12 MHz input clock (divide by 40)
84205  */
84206 #define USBPHY_PLL_SIC_PLL_DIV_SEL(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_PLL_DIV_SEL_MASK)
84207 
84208 #define USBPHY_PLL_SIC_PLL_LOCK_MASK             (0x80000000U)
84209 #define USBPHY_PLL_SIC_PLL_LOCK_SHIFT            (31U)
84210 /*! PLL_LOCK - USB PLL Lock Status Indicator
84211  *  0b0..Not locked
84212  *  0b1..Locked
84213  */
84214 #define USBPHY_PLL_SIC_PLL_LOCK(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_PLL_LOCK_MASK)
84215 /*! @} */
84216 
84217 /*! @name PLL_SIC_SET - PLL SIC */
84218 /*! @{ */
84219 
84220 #define USBPHY_PLL_SIC_SET_MISC2_CONTROL0_MASK   (0x20U)
84221 #define USBPHY_PLL_SIC_SET_MISC2_CONTROL0_SHIFT  (5U)
84222 /*! MISC2_CONTROL0 - Miscellaneous Control */
84223 #define USBPHY_PLL_SIC_SET_MISC2_CONTROL0(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_MISC2_CONTROL0_SHIFT)) & USBPHY_PLL_SIC_SET_MISC2_CONTROL0_MASK)
84224 
84225 #define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK  (0x40U)
84226 #define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT (6U)
84227 /*! PLL_EN_USB_CLKS - PLL Multi-Phase Clock Outputs Enable */
84228 #define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK)
84229 
84230 #define USBPHY_PLL_SIC_SET_PLL_POWER_MASK        (0x1000U)
84231 #define USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT       (12U)
84232 /*! PLL_POWER - USB PLL Powerup Control */
84233 #define USBPHY_PLL_SIC_SET_PLL_POWER(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_POWER_MASK)
84234 
84235 #define USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK       (0x2000U)
84236 #define USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT      (13U)
84237 /*! PLL_ENABLE - PLL Output Clock Enable */
84238 #define USBPHY_PLL_SIC_SET_PLL_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK)
84239 
84240 #define USBPHY_PLL_SIC_SET_PLL_BYPASS_MASK       (0x10000U)
84241 #define USBPHY_PLL_SIC_SET_PLL_BYPASS_SHIFT      (16U)
84242 /*! PLL_BYPASS - Bypass USB PLL */
84243 #define USBPHY_PLL_SIC_SET_PLL_BYPASS(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_BYPASS_MASK)
84244 
84245 #define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_MASK  (0x80000U)
84246 #define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_SHIFT (19U)
84247 /*! REFBIAS_PWD_SEL - Reference Bias Power Control */
84248 #define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_MASK)
84249 
84250 #define USBPHY_PLL_SIC_SET_REFBIAS_PWD_MASK      (0x100000U)
84251 #define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SHIFT     (20U)
84252 /*! REFBIAS_PWD - Power Down Reference Bias */
84253 #define USBPHY_PLL_SIC_SET_REFBIAS_PWD(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_SET_REFBIAS_PWD_MASK)
84254 
84255 #define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK   (0x200000U)
84256 #define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_SHIFT  (21U)
84257 /*! PLL_REG_ENABLE - Enable PLL Regulator */
84258 #define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK)
84259 
84260 #define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK      (0x1C00000U)
84261 #define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT     (22U)
84262 /*! PLL_DIV_SEL - PLL Divider Value Configuration */
84263 #define USBPHY_PLL_SIC_SET_PLL_DIV_SEL(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK)
84264 
84265 #define USBPHY_PLL_SIC_SET_PLL_LOCK_MASK         (0x80000000U)
84266 #define USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT        (31U)
84267 /*! PLL_LOCK - USB PLL Lock Status Indicator */
84268 #define USBPHY_PLL_SIC_SET_PLL_LOCK(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_LOCK_MASK)
84269 /*! @} */
84270 
84271 /*! @name PLL_SIC_CLR - PLL SIC */
84272 /*! @{ */
84273 
84274 #define USBPHY_PLL_SIC_CLR_MISC2_CONTROL0_MASK   (0x20U)
84275 #define USBPHY_PLL_SIC_CLR_MISC2_CONTROL0_SHIFT  (5U)
84276 /*! MISC2_CONTROL0 - Miscellaneous Control */
84277 #define USBPHY_PLL_SIC_CLR_MISC2_CONTROL0(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_MISC2_CONTROL0_SHIFT)) & USBPHY_PLL_SIC_CLR_MISC2_CONTROL0_MASK)
84278 
84279 #define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK  (0x40U)
84280 #define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT (6U)
84281 /*! PLL_EN_USB_CLKS - PLL Multi-Phase Clock Outputs Enable */
84282 #define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK)
84283 
84284 #define USBPHY_PLL_SIC_CLR_PLL_POWER_MASK        (0x1000U)
84285 #define USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT       (12U)
84286 /*! PLL_POWER - USB PLL Powerup Control */
84287 #define USBPHY_PLL_SIC_CLR_PLL_POWER(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_POWER_MASK)
84288 
84289 #define USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK       (0x2000U)
84290 #define USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT      (13U)
84291 /*! PLL_ENABLE - PLL Output Clock Enable */
84292 #define USBPHY_PLL_SIC_CLR_PLL_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK)
84293 
84294 #define USBPHY_PLL_SIC_CLR_PLL_BYPASS_MASK       (0x10000U)
84295 #define USBPHY_PLL_SIC_CLR_PLL_BYPASS_SHIFT      (16U)
84296 /*! PLL_BYPASS - Bypass USB PLL */
84297 #define USBPHY_PLL_SIC_CLR_PLL_BYPASS(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_BYPASS_MASK)
84298 
84299 #define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_MASK  (0x80000U)
84300 #define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_SHIFT (19U)
84301 /*! REFBIAS_PWD_SEL - Reference Bias Power Control */
84302 #define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_MASK)
84303 
84304 #define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_MASK      (0x100000U)
84305 #define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SHIFT     (20U)
84306 /*! REFBIAS_PWD - Power Down Reference Bias */
84307 #define USBPHY_PLL_SIC_CLR_REFBIAS_PWD(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_CLR_REFBIAS_PWD_MASK)
84308 
84309 #define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_MASK   (0x200000U)
84310 #define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_SHIFT  (21U)
84311 /*! PLL_REG_ENABLE - Enable PLL Regulator */
84312 #define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_MASK)
84313 
84314 #define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK      (0x1C00000U)
84315 #define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT     (22U)
84316 /*! PLL_DIV_SEL - PLL Divider Value Configuration */
84317 #define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK)
84318 
84319 #define USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK         (0x80000000U)
84320 #define USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT        (31U)
84321 /*! PLL_LOCK - USB PLL Lock Status Indicator */
84322 #define USBPHY_PLL_SIC_CLR_PLL_LOCK(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK)
84323 /*! @} */
84324 
84325 /*! @name PLL_SIC_TOG - PLL SIC */
84326 /*! @{ */
84327 
84328 #define USBPHY_PLL_SIC_TOG_MISC2_CONTROL0_MASK   (0x20U)
84329 #define USBPHY_PLL_SIC_TOG_MISC2_CONTROL0_SHIFT  (5U)
84330 /*! MISC2_CONTROL0 - Miscellaneous Control */
84331 #define USBPHY_PLL_SIC_TOG_MISC2_CONTROL0(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_MISC2_CONTROL0_SHIFT)) & USBPHY_PLL_SIC_TOG_MISC2_CONTROL0_MASK)
84332 
84333 #define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK  (0x40U)
84334 #define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT (6U)
84335 /*! PLL_EN_USB_CLKS - PLL Multi-Phase Clock Outputs Enable */
84336 #define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK)
84337 
84338 #define USBPHY_PLL_SIC_TOG_PLL_POWER_MASK        (0x1000U)
84339 #define USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT       (12U)
84340 /*! PLL_POWER - USB PLL Powerup Control */
84341 #define USBPHY_PLL_SIC_TOG_PLL_POWER(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_POWER_MASK)
84342 
84343 #define USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK       (0x2000U)
84344 #define USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT      (13U)
84345 /*! PLL_ENABLE - PLL Output Clock Enable */
84346 #define USBPHY_PLL_SIC_TOG_PLL_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK)
84347 
84348 #define USBPHY_PLL_SIC_TOG_PLL_BYPASS_MASK       (0x10000U)
84349 #define USBPHY_PLL_SIC_TOG_PLL_BYPASS_SHIFT      (16U)
84350 /*! PLL_BYPASS - Bypass USB PLL */
84351 #define USBPHY_PLL_SIC_TOG_PLL_BYPASS(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_BYPASS_MASK)
84352 
84353 #define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_MASK  (0x80000U)
84354 #define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_SHIFT (19U)
84355 /*! REFBIAS_PWD_SEL - Reference Bias Power Control */
84356 #define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_MASK)
84357 
84358 #define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_MASK      (0x100000U)
84359 #define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SHIFT     (20U)
84360 /*! REFBIAS_PWD - Power Down Reference Bias */
84361 #define USBPHY_PLL_SIC_TOG_REFBIAS_PWD(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_TOG_REFBIAS_PWD_MASK)
84362 
84363 #define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_MASK   (0x200000U)
84364 #define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_SHIFT  (21U)
84365 /*! PLL_REG_ENABLE - Enable PLL Regulator */
84366 #define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_MASK)
84367 
84368 #define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK      (0x1C00000U)
84369 #define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT     (22U)
84370 /*! PLL_DIV_SEL - PLL Divider Value Configuration */
84371 #define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK)
84372 
84373 #define USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK         (0x80000000U)
84374 #define USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT        (31U)
84375 /*! PLL_LOCK - USB PLL Lock Status Indicator */
84376 #define USBPHY_PLL_SIC_TOG_PLL_LOCK(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK)
84377 /*! @} */
84378 
84379 /*! @name USB1_VBUS_DETECT - VBUS Detect */
84380 /*! @{ */
84381 
84382 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK (0x7U)
84383 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT (0U)
84384 /*! VBUSVALID_THRESH - VBUS Comparator Threshold
84385  *  0b000..4.0 V
84386  *  0b001..4.1 V
84387  *  0b010..4.2 V
84388  *  0b011..4.3 V
84389  *  0b100..4.4 V
84390  *  0b101..4.5 V
84391  *  0b110..4.6 V
84392  *  0b111..4.7 V
84393  */
84394 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK)
84395 
84396 #define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK (0x8U)
84397 #define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT (3U)
84398 /*! VBUS_OVERRIDE_EN - VBUS Detect Signal Local Override Enable
84399  *  0b0..Results of VBUS_VALID and session valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND
84400  *  0b1..Override values for VBUS_VALID, AVALID, BVALID, and SESSEND
84401  */
84402 #define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK)
84403 
84404 #define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK (0x10U)
84405 #define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT (4U)
84406 /*! SESSEND_OVERRIDE - Override Value for SESSEND */
84407 #define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK)
84408 
84409 #define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK (0x20U)
84410 #define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT (5U)
84411 /*! BVALID_OVERRIDE - Override Value for B-Device Session Valid */
84412 #define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK)
84413 
84414 #define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK (0x40U)
84415 #define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT (6U)
84416 /*! AVALID_OVERRIDE - Override Value for A-Device Session Valid */
84417 #define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK)
84418 
84419 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK (0x80U)
84420 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT (7U)
84421 /*! VBUSVALID_OVERRIDE - Override Value for the VBUS_VALID Signal */
84422 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK)
84423 
84424 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK (0x100U)
84425 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT (8U)
84426 /*! VBUSVALID_SEL - VBUS_VALID Selection
84427  *  0b0..VBUS_VALID comparator result
84428  *  0b1..VBUS_VALID_3V comparator result
84429  */
84430 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK)
84431 
84432 #define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK (0x600U)
84433 #define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT (9U)
84434 /*! VBUS_SOURCE_SEL - VBUS_VALID Source Selection
84435  *  0b00..VBUS_VALID comparator result
84436  *  0b01..Session valid comparator result
84437  *  0b10..Session valid comparator result
84438  *  0b11..
84439  */
84440 #define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK)
84441 
84442 #define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_MASK (0x800U)
84443 #define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_SHIFT (11U)
84444 /*! ID_OVERRIDE_EN - Enable Local ID Pin Status Override
84445  *  0b0..Use ID pin detector or external override
84446  *  0b1..Allow local override of ID pin detection status
84447  */
84448 #define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_MASK)
84449 
84450 #define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_MASK (0x1000U)
84451 #define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_SHIFT (12U)
84452 /*! ID_OVERRIDE - ID Pin Status Local Override */
84453 #define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE(x)   (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_MASK)
84454 
84455 #define USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN_MASK (0x2000U)
84456 #define USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN_SHIFT (13U)
84457 /*! EXT_ID_OVERRIDE_EN - External ID Override Enable
84458  *  0b0..Internal detector or local override
84459  *  0b1..External ID signal value
84460  */
84461 #define USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN_MASK)
84462 
84463 #define USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN_MASK (0x4000U)
84464 #define USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN_SHIFT (14U)
84465 /*! EXT_VBUS_OVERRIDE_EN - External VBUS Override Enable
84466  *  0b0..Internal detector or local override
84467  *  0b1..External VBUS_VALID value
84468  */
84469 #define USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN_MASK)
84470 
84471 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_B_MASK (0x40000U)
84472 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_B_SHIFT (18U)
84473 /*! VBUSVALID_TO_B - VBUS_VALID Comparator Selection
84474  *  0b0..VBUS_VALID comparator
84475  *  0b1..Session valid detector
84476  */
84477 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_B(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_B_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_B_MASK)
84478 
84479 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_MASK (0x700000U)
84480 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_SHIFT (20U)
84481 /*! VBUSVALID_PWRUP_CMPS - VBUS_VALID Comparator Enable
84482  *  0bxx0..Disable or power down the VBUS_VALID comparator
84483  *  0bxx1..Enable the VBUS_VALID comparator
84484  *  0bx0x..Disable or power down the session valid detector
84485  *  0bx1x..Enable the session valid detector
84486  *  0b0xx..Disable or power down the VBUS_VALID_3V detector
84487  *  0b1xx..Enable the VBUS_VALID_3V detector
84488  */
84489 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_MASK)
84490 
84491 #define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK (0x4000000U)
84492 #define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT (26U)
84493 /*! DISCHARGE_VBUS - VBUS Discharge Resistor
84494  *  0b0..Disable
84495  *  0b1..Enable
84496  */
84497 #define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK)
84498 /*! @} */
84499 
84500 /*! @name USB1_VBUS_DETECT_SET - VBUS Detect */
84501 /*! @{ */
84502 
84503 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK (0x7U)
84504 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT (0U)
84505 /*! VBUSVALID_THRESH - VBUS Comparator Threshold */
84506 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK)
84507 
84508 #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK (0x8U)
84509 #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT (3U)
84510 /*! VBUS_OVERRIDE_EN - VBUS Detect Signal Local Override Enable */
84511 #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK)
84512 
84513 #define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK (0x10U)
84514 #define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT (4U)
84515 /*! SESSEND_OVERRIDE - Override Value for SESSEND */
84516 #define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK)
84517 
84518 #define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK (0x20U)
84519 #define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT (5U)
84520 /*! BVALID_OVERRIDE - Override Value for B-Device Session Valid */
84521 #define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK)
84522 
84523 #define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK (0x40U)
84524 #define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT (6U)
84525 /*! AVALID_OVERRIDE - Override Value for A-Device Session Valid */
84526 #define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK)
84527 
84528 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK (0x80U)
84529 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT (7U)
84530 /*! VBUSVALID_OVERRIDE - Override Value for the VBUS_VALID Signal */
84531 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK)
84532 
84533 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK (0x100U)
84534 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT (8U)
84535 /*! VBUSVALID_SEL - VBUS_VALID Selection */
84536 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK)
84537 
84538 #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK (0x600U)
84539 #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT (9U)
84540 /*! VBUS_SOURCE_SEL - VBUS_VALID Source Selection */
84541 #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK)
84542 
84543 #define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_MASK (0x800U)
84544 #define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_SHIFT (11U)
84545 /*! ID_OVERRIDE_EN - Enable Local ID Pin Status Override */
84546 #define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_MASK)
84547 
84548 #define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_MASK (0x1000U)
84549 #define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_SHIFT (12U)
84550 /*! ID_OVERRIDE - ID Pin Status Local Override */
84551 #define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_MASK)
84552 
84553 #define USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN_MASK (0x2000U)
84554 #define USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN_SHIFT (13U)
84555 /*! EXT_ID_OVERRIDE_EN - External ID Override Enable */
84556 #define USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN_MASK)
84557 
84558 #define USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN_MASK (0x4000U)
84559 #define USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN_SHIFT (14U)
84560 /*! EXT_VBUS_OVERRIDE_EN - External VBUS Override Enable */
84561 #define USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN_MASK)
84562 
84563 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_B_MASK (0x40000U)
84564 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_B_SHIFT (18U)
84565 /*! VBUSVALID_TO_B - VBUS_VALID Comparator Selection */
84566 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_B(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_B_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_B_MASK)
84567 
84568 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_MASK (0x700000U)
84569 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_SHIFT (20U)
84570 /*! VBUSVALID_PWRUP_CMPS - VBUS_VALID Comparator Enable */
84571 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_MASK)
84572 
84573 #define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK (0x4000000U)
84574 #define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT (26U)
84575 /*! DISCHARGE_VBUS - VBUS Discharge Resistor */
84576 #define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK)
84577 /*! @} */
84578 
84579 /*! @name USB1_VBUS_DETECT_CLR - VBUS Detect */
84580 /*! @{ */
84581 
84582 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK (0x7U)
84583 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT (0U)
84584 /*! VBUSVALID_THRESH - VBUS Comparator Threshold */
84585 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK)
84586 
84587 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK (0x8U)
84588 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT (3U)
84589 /*! VBUS_OVERRIDE_EN - VBUS Detect Signal Local Override Enable */
84590 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK)
84591 
84592 #define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK (0x10U)
84593 #define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT (4U)
84594 /*! SESSEND_OVERRIDE - Override Value for SESSEND */
84595 #define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK)
84596 
84597 #define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK (0x20U)
84598 #define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT (5U)
84599 /*! BVALID_OVERRIDE - Override Value for B-Device Session Valid */
84600 #define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK)
84601 
84602 #define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK (0x40U)
84603 #define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT (6U)
84604 /*! AVALID_OVERRIDE - Override Value for A-Device Session Valid */
84605 #define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK)
84606 
84607 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK (0x80U)
84608 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT (7U)
84609 /*! VBUSVALID_OVERRIDE - Override Value for the VBUS_VALID Signal */
84610 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK)
84611 
84612 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK (0x100U)
84613 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT (8U)
84614 /*! VBUSVALID_SEL - VBUS_VALID Selection */
84615 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK)
84616 
84617 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK (0x600U)
84618 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT (9U)
84619 /*! VBUS_SOURCE_SEL - VBUS_VALID Source Selection */
84620 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK)
84621 
84622 #define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_MASK (0x800U)
84623 #define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_SHIFT (11U)
84624 /*! ID_OVERRIDE_EN - Enable Local ID Pin Status Override */
84625 #define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_MASK)
84626 
84627 #define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_MASK (0x1000U)
84628 #define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_SHIFT (12U)
84629 /*! ID_OVERRIDE - ID Pin Status Local Override */
84630 #define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_MASK)
84631 
84632 #define USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN_MASK (0x2000U)
84633 #define USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN_SHIFT (13U)
84634 /*! EXT_ID_OVERRIDE_EN - External ID Override Enable */
84635 #define USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN_MASK)
84636 
84637 #define USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN_MASK (0x4000U)
84638 #define USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN_SHIFT (14U)
84639 /*! EXT_VBUS_OVERRIDE_EN - External VBUS Override Enable */
84640 #define USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN_MASK)
84641 
84642 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_B_MASK (0x40000U)
84643 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_B_SHIFT (18U)
84644 /*! VBUSVALID_TO_B - VBUS_VALID Comparator Selection */
84645 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_B(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_B_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_B_MASK)
84646 
84647 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_MASK (0x700000U)
84648 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_SHIFT (20U)
84649 /*! VBUSVALID_PWRUP_CMPS - VBUS_VALID Comparator Enable */
84650 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_MASK)
84651 
84652 #define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK (0x4000000U)
84653 #define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT (26U)
84654 /*! DISCHARGE_VBUS - VBUS Discharge Resistor */
84655 #define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK)
84656 /*! @} */
84657 
84658 /*! @name USB1_VBUS_DETECT_TOG - VBUS Detect */
84659 /*! @{ */
84660 
84661 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK (0x7U)
84662 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT (0U)
84663 /*! VBUSVALID_THRESH - VBUS Comparator Threshold */
84664 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK)
84665 
84666 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK (0x8U)
84667 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT (3U)
84668 /*! VBUS_OVERRIDE_EN - VBUS Detect Signal Local Override Enable */
84669 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK)
84670 
84671 #define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK (0x10U)
84672 #define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT (4U)
84673 /*! SESSEND_OVERRIDE - Override Value for SESSEND */
84674 #define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK)
84675 
84676 #define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK (0x20U)
84677 #define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT (5U)
84678 /*! BVALID_OVERRIDE - Override Value for B-Device Session Valid */
84679 #define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK)
84680 
84681 #define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK (0x40U)
84682 #define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT (6U)
84683 /*! AVALID_OVERRIDE - Override Value for A-Device Session Valid */
84684 #define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK)
84685 
84686 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK (0x80U)
84687 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT (7U)
84688 /*! VBUSVALID_OVERRIDE - Override Value for the VBUS_VALID Signal */
84689 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK)
84690 
84691 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK (0x100U)
84692 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT (8U)
84693 /*! VBUSVALID_SEL - VBUS_VALID Selection */
84694 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK)
84695 
84696 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK (0x600U)
84697 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT (9U)
84698 /*! VBUS_SOURCE_SEL - VBUS_VALID Source Selection */
84699 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK)
84700 
84701 #define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_MASK (0x800U)
84702 #define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_SHIFT (11U)
84703 /*! ID_OVERRIDE_EN - Enable Local ID Pin Status Override */
84704 #define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_MASK)
84705 
84706 #define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_MASK (0x1000U)
84707 #define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_SHIFT (12U)
84708 /*! ID_OVERRIDE - ID Pin Status Local Override */
84709 #define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_MASK)
84710 
84711 #define USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN_MASK (0x2000U)
84712 #define USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN_SHIFT (13U)
84713 /*! EXT_ID_OVERRIDE_EN - External ID Override Enable */
84714 #define USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN_MASK)
84715 
84716 #define USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN_MASK (0x4000U)
84717 #define USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN_SHIFT (14U)
84718 /*! EXT_VBUS_OVERRIDE_EN - External VBUS Override Enable */
84719 #define USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN_MASK)
84720 
84721 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_B_MASK (0x40000U)
84722 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_B_SHIFT (18U)
84723 /*! VBUSVALID_TO_B - VBUS_VALID Comparator Selection */
84724 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_B(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_B_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_B_MASK)
84725 
84726 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_MASK (0x700000U)
84727 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_SHIFT (20U)
84728 /*! VBUSVALID_PWRUP_CMPS - VBUS_VALID Comparator Enable */
84729 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_MASK)
84730 
84731 #define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK (0x4000000U)
84732 #define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT (26U)
84733 /*! DISCHARGE_VBUS - VBUS Discharge Resistor */
84734 #define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK)
84735 /*! @} */
84736 
84737 /*! @name USB1_VBUS_DET_STAT - VBUS Detect Status */
84738 /*! @{ */
84739 
84740 #define USBPHY_USB1_VBUS_DET_STAT_SESSEND_MASK   (0x1U)
84741 #define USBPHY_USB1_VBUS_DET_STAT_SESSEND_SHIFT  (0U)
84742 /*! SESSEND - Session End Indicator
84743  *  0b0..Above threshold
84744  *  0b1..Below threshold
84745  */
84746 #define USBPHY_USB1_VBUS_DET_STAT_SESSEND(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_SESSEND_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_SESSEND_MASK)
84747 
84748 #define USBPHY_USB1_VBUS_DET_STAT_BVALID_MASK    (0x2U)
84749 #define USBPHY_USB1_VBUS_DET_STAT_BVALID_SHIFT   (1U)
84750 /*! BVALID - B-Device Session Valid Status
84751  *  0b0..Below threshold
84752  *  0b1..Above threshold
84753  */
84754 #define USBPHY_USB1_VBUS_DET_STAT_BVALID(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_BVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_BVALID_MASK)
84755 
84756 #define USBPHY_USB1_VBUS_DET_STAT_AVALID_MASK    (0x4U)
84757 #define USBPHY_USB1_VBUS_DET_STAT_AVALID_SHIFT   (2U)
84758 /*! AVALID - A-Device Session Valid Status
84759  *  0b0..Below threshold
84760  *  0b1..Above threshold
84761  */
84762 #define USBPHY_USB1_VBUS_DET_STAT_AVALID(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_AVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_AVALID_MASK)
84763 
84764 #define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_MASK (0x8U)
84765 #define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_SHIFT (3U)
84766 /*! VBUS_VALID - VBUS Voltage Status
84767  *  0b0..Below threshold
84768  *  0b1..Above threshold
84769  */
84770 #define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_MASK)
84771 
84772 #define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_MASK (0x10U)
84773 #define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_SHIFT (4U)
84774 /*! VBUS_VALID_3V - VBUS_VALID_3V Detector Status
84775  *  0b0..Below threshold
84776  *  0b1..Above threshold
84777  */
84778 #define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_MASK)
84779 
84780 #define USBPHY_USB1_VBUS_DET_STAT_EXT_ID_MASK    (0x20U)
84781 #define USBPHY_USB1_VBUS_DET_STAT_EXT_ID_SHIFT   (5U)
84782 /*! EXT_ID - OTG ID External Override Status */
84783 #define USBPHY_USB1_VBUS_DET_STAT_EXT_ID(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_EXT_ID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_EXT_ID_MASK)
84784 /*! @} */
84785 
84786 /*! @name USB1_VBUS_DET_STAT_SET - VBUS Detect Status */
84787 /*! @{ */
84788 
84789 #define USBPHY_USB1_VBUS_DET_STAT_SET_SESSEND_MASK (0x1U)
84790 #define USBPHY_USB1_VBUS_DET_STAT_SET_SESSEND_SHIFT (0U)
84791 /*! SESSEND - Session End Indicator */
84792 #define USBPHY_USB1_VBUS_DET_STAT_SET_SESSEND(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_SET_SESSEND_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_SET_SESSEND_MASK)
84793 
84794 #define USBPHY_USB1_VBUS_DET_STAT_SET_BVALID_MASK (0x2U)
84795 #define USBPHY_USB1_VBUS_DET_STAT_SET_BVALID_SHIFT (1U)
84796 /*! BVALID - B-Device Session Valid Status */
84797 #define USBPHY_USB1_VBUS_DET_STAT_SET_BVALID(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_SET_BVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_SET_BVALID_MASK)
84798 
84799 #define USBPHY_USB1_VBUS_DET_STAT_SET_AVALID_MASK (0x4U)
84800 #define USBPHY_USB1_VBUS_DET_STAT_SET_AVALID_SHIFT (2U)
84801 /*! AVALID - A-Device Session Valid Status */
84802 #define USBPHY_USB1_VBUS_DET_STAT_SET_AVALID(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_SET_AVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_SET_AVALID_MASK)
84803 
84804 #define USBPHY_USB1_VBUS_DET_STAT_SET_VBUS_VALID_MASK (0x8U)
84805 #define USBPHY_USB1_VBUS_DET_STAT_SET_VBUS_VALID_SHIFT (3U)
84806 /*! VBUS_VALID - VBUS Voltage Status */
84807 #define USBPHY_USB1_VBUS_DET_STAT_SET_VBUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_SET_VBUS_VALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_SET_VBUS_VALID_MASK)
84808 
84809 #define USBPHY_USB1_VBUS_DET_STAT_SET_VBUS_VALID_3V_MASK (0x10U)
84810 #define USBPHY_USB1_VBUS_DET_STAT_SET_VBUS_VALID_3V_SHIFT (4U)
84811 /*! VBUS_VALID_3V - VBUS_VALID_3V Detector Status */
84812 #define USBPHY_USB1_VBUS_DET_STAT_SET_VBUS_VALID_3V(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_SET_VBUS_VALID_3V_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_SET_VBUS_VALID_3V_MASK)
84813 
84814 #define USBPHY_USB1_VBUS_DET_STAT_SET_EXT_ID_MASK (0x20U)
84815 #define USBPHY_USB1_VBUS_DET_STAT_SET_EXT_ID_SHIFT (5U)
84816 /*! EXT_ID - OTG ID External Override Status */
84817 #define USBPHY_USB1_VBUS_DET_STAT_SET_EXT_ID(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_SET_EXT_ID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_SET_EXT_ID_MASK)
84818 /*! @} */
84819 
84820 /*! @name USB1_VBUS_DET_STAT_CLR - VBUS Detect Status */
84821 /*! @{ */
84822 
84823 #define USBPHY_USB1_VBUS_DET_STAT_CLR_SESSEND_MASK (0x1U)
84824 #define USBPHY_USB1_VBUS_DET_STAT_CLR_SESSEND_SHIFT (0U)
84825 /*! SESSEND - Session End Indicator */
84826 #define USBPHY_USB1_VBUS_DET_STAT_CLR_SESSEND(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_CLR_SESSEND_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_CLR_SESSEND_MASK)
84827 
84828 #define USBPHY_USB1_VBUS_DET_STAT_CLR_BVALID_MASK (0x2U)
84829 #define USBPHY_USB1_VBUS_DET_STAT_CLR_BVALID_SHIFT (1U)
84830 /*! BVALID - B-Device Session Valid Status */
84831 #define USBPHY_USB1_VBUS_DET_STAT_CLR_BVALID(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_CLR_BVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_CLR_BVALID_MASK)
84832 
84833 #define USBPHY_USB1_VBUS_DET_STAT_CLR_AVALID_MASK (0x4U)
84834 #define USBPHY_USB1_VBUS_DET_STAT_CLR_AVALID_SHIFT (2U)
84835 /*! AVALID - A-Device Session Valid Status */
84836 #define USBPHY_USB1_VBUS_DET_STAT_CLR_AVALID(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_CLR_AVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_CLR_AVALID_MASK)
84837 
84838 #define USBPHY_USB1_VBUS_DET_STAT_CLR_VBUS_VALID_MASK (0x8U)
84839 #define USBPHY_USB1_VBUS_DET_STAT_CLR_VBUS_VALID_SHIFT (3U)
84840 /*! VBUS_VALID - VBUS Voltage Status */
84841 #define USBPHY_USB1_VBUS_DET_STAT_CLR_VBUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_CLR_VBUS_VALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_CLR_VBUS_VALID_MASK)
84842 
84843 #define USBPHY_USB1_VBUS_DET_STAT_CLR_VBUS_VALID_3V_MASK (0x10U)
84844 #define USBPHY_USB1_VBUS_DET_STAT_CLR_VBUS_VALID_3V_SHIFT (4U)
84845 /*! VBUS_VALID_3V - VBUS_VALID_3V Detector Status */
84846 #define USBPHY_USB1_VBUS_DET_STAT_CLR_VBUS_VALID_3V(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_CLR_VBUS_VALID_3V_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_CLR_VBUS_VALID_3V_MASK)
84847 
84848 #define USBPHY_USB1_VBUS_DET_STAT_CLR_EXT_ID_MASK (0x20U)
84849 #define USBPHY_USB1_VBUS_DET_STAT_CLR_EXT_ID_SHIFT (5U)
84850 /*! EXT_ID - OTG ID External Override Status */
84851 #define USBPHY_USB1_VBUS_DET_STAT_CLR_EXT_ID(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_CLR_EXT_ID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_CLR_EXT_ID_MASK)
84852 /*! @} */
84853 
84854 /*! @name USB1_VBUS_DET_STAT_TOG - VBUS Detect Status */
84855 /*! @{ */
84856 
84857 #define USBPHY_USB1_VBUS_DET_STAT_TOG_SESSEND_MASK (0x1U)
84858 #define USBPHY_USB1_VBUS_DET_STAT_TOG_SESSEND_SHIFT (0U)
84859 /*! SESSEND - Session End Indicator */
84860 #define USBPHY_USB1_VBUS_DET_STAT_TOG_SESSEND(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_TOG_SESSEND_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_TOG_SESSEND_MASK)
84861 
84862 #define USBPHY_USB1_VBUS_DET_STAT_TOG_BVALID_MASK (0x2U)
84863 #define USBPHY_USB1_VBUS_DET_STAT_TOG_BVALID_SHIFT (1U)
84864 /*! BVALID - B-Device Session Valid Status */
84865 #define USBPHY_USB1_VBUS_DET_STAT_TOG_BVALID(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_TOG_BVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_TOG_BVALID_MASK)
84866 
84867 #define USBPHY_USB1_VBUS_DET_STAT_TOG_AVALID_MASK (0x4U)
84868 #define USBPHY_USB1_VBUS_DET_STAT_TOG_AVALID_SHIFT (2U)
84869 /*! AVALID - A-Device Session Valid Status */
84870 #define USBPHY_USB1_VBUS_DET_STAT_TOG_AVALID(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_TOG_AVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_TOG_AVALID_MASK)
84871 
84872 #define USBPHY_USB1_VBUS_DET_STAT_TOG_VBUS_VALID_MASK (0x8U)
84873 #define USBPHY_USB1_VBUS_DET_STAT_TOG_VBUS_VALID_SHIFT (3U)
84874 /*! VBUS_VALID - VBUS Voltage Status */
84875 #define USBPHY_USB1_VBUS_DET_STAT_TOG_VBUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_TOG_VBUS_VALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_TOG_VBUS_VALID_MASK)
84876 
84877 #define USBPHY_USB1_VBUS_DET_STAT_TOG_VBUS_VALID_3V_MASK (0x10U)
84878 #define USBPHY_USB1_VBUS_DET_STAT_TOG_VBUS_VALID_3V_SHIFT (4U)
84879 /*! VBUS_VALID_3V - VBUS_VALID_3V Detector Status */
84880 #define USBPHY_USB1_VBUS_DET_STAT_TOG_VBUS_VALID_3V(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_TOG_VBUS_VALID_3V_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_TOG_VBUS_VALID_3V_MASK)
84881 
84882 #define USBPHY_USB1_VBUS_DET_STAT_TOG_EXT_ID_MASK (0x20U)
84883 #define USBPHY_USB1_VBUS_DET_STAT_TOG_EXT_ID_SHIFT (5U)
84884 /*! EXT_ID - OTG ID External Override Status */
84885 #define USBPHY_USB1_VBUS_DET_STAT_TOG_EXT_ID(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_TOG_EXT_ID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_TOG_EXT_ID_MASK)
84886 /*! @} */
84887 
84888 /*! @name USB1_CHRG_DETECT - Charger Detect */
84889 /*! @{ */
84890 
84891 #define USBPHY_USB1_CHRG_DETECT_DETECT_SEC_MASK  (0x2U)
84892 #define USBPHY_USB1_CHRG_DETECT_DETECT_SEC_SHIFT (1U)
84893 /*! DETECT_SEC - Secondary Detection Function Enable
84894  *  0b0..Disable
84895  *  0b1..Enable
84896  */
84897 #define USBPHY_USB1_CHRG_DETECT_DETECT_SEC(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_DETECT_SEC_SHIFT)) & USBPHY_USB1_CHRG_DETECT_DETECT_SEC_MASK)
84898 
84899 #define USBPHY_USB1_CHRG_DETECT_PULLUP_DP_MASK   (0x4U)
84900 #define USBPHY_USB1_CHRG_DETECT_PULLUP_DP_SHIFT  (2U)
84901 /*! PULLUP_DP - DP Pullup Resistor Enable Override Control
84902  *  0b0..Disable
84903  *  0b1..Enable
84904  */
84905 #define USBPHY_USB1_CHRG_DETECT_PULLUP_DP(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_PULLUP_DP_MASK)
84906 
84907 #define USBPHY_USB1_CHRG_DETECT_VDM_SRC_ENABLE_MASK (0x10U)
84908 #define USBPHY_USB1_CHRG_DETECT_VDM_SRC_ENABLE_SHIFT (4U)
84909 /*! VDM_SRC_ENABLE - VDM_SRC Function Enable
84910  *  0b0..Disable
84911  *  0b1..Enable
84912  */
84913 #define USBPHY_USB1_CHRG_DETECT_VDM_SRC_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_VDM_SRC_ENABLE_SHIFT)) & USBPHY_USB1_CHRG_DETECT_VDM_SRC_ENABLE_MASK)
84914 
84915 #define USBPHY_USB1_CHRG_DETECT_CHK_CONTACT_MASK (0x40000U)
84916 #define USBPHY_USB1_CHRG_DETECT_CHK_CONTACT_SHIFT (18U)
84917 /*! CHK_CONTACT - BC Data Contact Detect Function Enable
84918  *  0b0..Disable
84919  *  0b1..Enable
84920  */
84921 #define USBPHY_USB1_CHRG_DETECT_CHK_CONTACT(x)   (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CHK_CONTACT_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CHK_CONTACT_MASK)
84922 
84923 #define USBPHY_USB1_CHRG_DETECT_CHK_CHRG_B_MASK  (0x80000U)
84924 #define USBPHY_USB1_CHRG_DETECT_CHK_CHRG_B_SHIFT (19U)
84925 /*! CHK_CHRG_B - BC Charger Detection Function Enable
84926  *  0b0..Enable
84927  *  0b1..Disable
84928  */
84929 #define USBPHY_USB1_CHRG_DETECT_CHK_CHRG_B(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CHK_CHRG_B_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CHK_CHRG_B_MASK)
84930 
84931 #define USBPHY_USB1_CHRG_DETECT_EN_B_MASK        (0x100000U)
84932 #define USBPHY_USB1_CHRG_DETECT_EN_B_SHIFT       (20U)
84933 /*! EN_B - Selection of BC v1.2 Function Enable
84934  *  0b0..Enable
84935  *  0b1..Disable
84936  */
84937 #define USBPHY_USB1_CHRG_DETECT_EN_B(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_EN_B_SHIFT)) & USBPHY_USB1_CHRG_DETECT_EN_B_MASK)
84938 
84939 #define USBPHY_USB1_CHRG_DETECT_DCDSEL_MASK      (0x80000000U)
84940 #define USBPHY_USB1_CHRG_DETECT_DCDSEL_SHIFT     (31U)
84941 /*! DCDSEL - DCD Selection
84942  *  0b0..Fields in USB1_CHRG_DETECT
84943  *  0b1..Fields and state machines in the USBHSDCD module
84944  */
84945 #define USBPHY_USB1_CHRG_DETECT_DCDSEL(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_DCDSEL_SHIFT)) & USBPHY_USB1_CHRG_DETECT_DCDSEL_MASK)
84946 /*! @} */
84947 
84948 /*! @name USB1_CHRG_DETECT_SET - Charger Detect */
84949 /*! @{ */
84950 
84951 #define USBPHY_USB1_CHRG_DETECT_SET_DETECT_SEC_MASK (0x2U)
84952 #define USBPHY_USB1_CHRG_DETECT_SET_DETECT_SEC_SHIFT (1U)
84953 /*! DETECT_SEC - Secondary Detection Function Enable */
84954 #define USBPHY_USB1_CHRG_DETECT_SET_DETECT_SEC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_DETECT_SEC_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_DETECT_SEC_MASK)
84955 
84956 #define USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_MASK (0x4U)
84957 #define USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_SHIFT (2U)
84958 /*! PULLUP_DP - DP Pullup Resistor Enable Override Control */
84959 #define USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_MASK)
84960 
84961 #define USBPHY_USB1_CHRG_DETECT_SET_VDM_SRC_ENABLE_MASK (0x10U)
84962 #define USBPHY_USB1_CHRG_DETECT_SET_VDM_SRC_ENABLE_SHIFT (4U)
84963 /*! VDM_SRC_ENABLE - VDM_SRC Function Enable */
84964 #define USBPHY_USB1_CHRG_DETECT_SET_VDM_SRC_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_VDM_SRC_ENABLE_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_VDM_SRC_ENABLE_MASK)
84965 
84966 #define USBPHY_USB1_CHRG_DETECT_SET_CHK_CONTACT_MASK (0x40000U)
84967 #define USBPHY_USB1_CHRG_DETECT_SET_CHK_CONTACT_SHIFT (18U)
84968 /*! CHK_CONTACT - BC Data Contact Detect Function Enable */
84969 #define USBPHY_USB1_CHRG_DETECT_SET_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_CHK_CONTACT_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_CHK_CONTACT_MASK)
84970 
84971 #define USBPHY_USB1_CHRG_DETECT_SET_CHK_CHRG_B_MASK (0x80000U)
84972 #define USBPHY_USB1_CHRG_DETECT_SET_CHK_CHRG_B_SHIFT (19U)
84973 /*! CHK_CHRG_B - BC Charger Detection Function Enable */
84974 #define USBPHY_USB1_CHRG_DETECT_SET_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_CHK_CHRG_B_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_CHK_CHRG_B_MASK)
84975 
84976 #define USBPHY_USB1_CHRG_DETECT_SET_EN_B_MASK    (0x100000U)
84977 #define USBPHY_USB1_CHRG_DETECT_SET_EN_B_SHIFT   (20U)
84978 /*! EN_B - Selection of BC v1.2 Function Enable */
84979 #define USBPHY_USB1_CHRG_DETECT_SET_EN_B(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_EN_B_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_EN_B_MASK)
84980 
84981 #define USBPHY_USB1_CHRG_DETECT_SET_DCDSEL_MASK  (0x80000000U)
84982 #define USBPHY_USB1_CHRG_DETECT_SET_DCDSEL_SHIFT (31U)
84983 /*! DCDSEL - DCD Selection */
84984 #define USBPHY_USB1_CHRG_DETECT_SET_DCDSEL(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_DCDSEL_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_DCDSEL_MASK)
84985 /*! @} */
84986 
84987 /*! @name USB1_CHRG_DETECT_CLR - Charger Detect */
84988 /*! @{ */
84989 
84990 #define USBPHY_USB1_CHRG_DETECT_CLR_DETECT_SEC_MASK (0x2U)
84991 #define USBPHY_USB1_CHRG_DETECT_CLR_DETECT_SEC_SHIFT (1U)
84992 /*! DETECT_SEC - Secondary Detection Function Enable */
84993 #define USBPHY_USB1_CHRG_DETECT_CLR_DETECT_SEC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_DETECT_SEC_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_DETECT_SEC_MASK)
84994 
84995 #define USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_MASK (0x4U)
84996 #define USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_SHIFT (2U)
84997 /*! PULLUP_DP - DP Pullup Resistor Enable Override Control */
84998 #define USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_MASK)
84999 
85000 #define USBPHY_USB1_CHRG_DETECT_CLR_VDM_SRC_ENABLE_MASK (0x10U)
85001 #define USBPHY_USB1_CHRG_DETECT_CLR_VDM_SRC_ENABLE_SHIFT (4U)
85002 /*! VDM_SRC_ENABLE - VDM_SRC Function Enable */
85003 #define USBPHY_USB1_CHRG_DETECT_CLR_VDM_SRC_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_VDM_SRC_ENABLE_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_VDM_SRC_ENABLE_MASK)
85004 
85005 #define USBPHY_USB1_CHRG_DETECT_CLR_CHK_CONTACT_MASK (0x40000U)
85006 #define USBPHY_USB1_CHRG_DETECT_CLR_CHK_CONTACT_SHIFT (18U)
85007 /*! CHK_CONTACT - BC Data Contact Detect Function Enable */
85008 #define USBPHY_USB1_CHRG_DETECT_CLR_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_CHK_CONTACT_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_CHK_CONTACT_MASK)
85009 
85010 #define USBPHY_USB1_CHRG_DETECT_CLR_CHK_CHRG_B_MASK (0x80000U)
85011 #define USBPHY_USB1_CHRG_DETECT_CLR_CHK_CHRG_B_SHIFT (19U)
85012 /*! CHK_CHRG_B - BC Charger Detection Function Enable */
85013 #define USBPHY_USB1_CHRG_DETECT_CLR_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_CHK_CHRG_B_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_CHK_CHRG_B_MASK)
85014 
85015 #define USBPHY_USB1_CHRG_DETECT_CLR_EN_B_MASK    (0x100000U)
85016 #define USBPHY_USB1_CHRG_DETECT_CLR_EN_B_SHIFT   (20U)
85017 /*! EN_B - Selection of BC v1.2 Function Enable */
85018 #define USBPHY_USB1_CHRG_DETECT_CLR_EN_B(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_EN_B_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_EN_B_MASK)
85019 
85020 #define USBPHY_USB1_CHRG_DETECT_CLR_DCDSEL_MASK  (0x80000000U)
85021 #define USBPHY_USB1_CHRG_DETECT_CLR_DCDSEL_SHIFT (31U)
85022 /*! DCDSEL - DCD Selection */
85023 #define USBPHY_USB1_CHRG_DETECT_CLR_DCDSEL(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_DCDSEL_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_DCDSEL_MASK)
85024 /*! @} */
85025 
85026 /*! @name USB1_CHRG_DETECT_TOG - Charger Detect */
85027 /*! @{ */
85028 
85029 #define USBPHY_USB1_CHRG_DETECT_TOG_DETECT_SEC_MASK (0x2U)
85030 #define USBPHY_USB1_CHRG_DETECT_TOG_DETECT_SEC_SHIFT (1U)
85031 /*! DETECT_SEC - Secondary Detection Function Enable */
85032 #define USBPHY_USB1_CHRG_DETECT_TOG_DETECT_SEC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_DETECT_SEC_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_DETECT_SEC_MASK)
85033 
85034 #define USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_MASK (0x4U)
85035 #define USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_SHIFT (2U)
85036 /*! PULLUP_DP - DP Pullup Resistor Enable Override Control */
85037 #define USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_MASK)
85038 
85039 #define USBPHY_USB1_CHRG_DETECT_TOG_VDM_SRC_ENABLE_MASK (0x10U)
85040 #define USBPHY_USB1_CHRG_DETECT_TOG_VDM_SRC_ENABLE_SHIFT (4U)
85041 /*! VDM_SRC_ENABLE - VDM_SRC Function Enable */
85042 #define USBPHY_USB1_CHRG_DETECT_TOG_VDM_SRC_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_VDM_SRC_ENABLE_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_VDM_SRC_ENABLE_MASK)
85043 
85044 #define USBPHY_USB1_CHRG_DETECT_TOG_CHK_CONTACT_MASK (0x40000U)
85045 #define USBPHY_USB1_CHRG_DETECT_TOG_CHK_CONTACT_SHIFT (18U)
85046 /*! CHK_CONTACT - BC Data Contact Detect Function Enable */
85047 #define USBPHY_USB1_CHRG_DETECT_TOG_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_CHK_CONTACT_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_CHK_CONTACT_MASK)
85048 
85049 #define USBPHY_USB1_CHRG_DETECT_TOG_CHK_CHRG_B_MASK (0x80000U)
85050 #define USBPHY_USB1_CHRG_DETECT_TOG_CHK_CHRG_B_SHIFT (19U)
85051 /*! CHK_CHRG_B - BC Charger Detection Function Enable */
85052 #define USBPHY_USB1_CHRG_DETECT_TOG_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_CHK_CHRG_B_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_CHK_CHRG_B_MASK)
85053 
85054 #define USBPHY_USB1_CHRG_DETECT_TOG_EN_B_MASK    (0x100000U)
85055 #define USBPHY_USB1_CHRG_DETECT_TOG_EN_B_SHIFT   (20U)
85056 /*! EN_B - Selection of BC v1.2 Function Enable */
85057 #define USBPHY_USB1_CHRG_DETECT_TOG_EN_B(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_EN_B_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_EN_B_MASK)
85058 
85059 #define USBPHY_USB1_CHRG_DETECT_TOG_DCDSEL_MASK  (0x80000000U)
85060 #define USBPHY_USB1_CHRG_DETECT_TOG_DCDSEL_SHIFT (31U)
85061 /*! DCDSEL - DCD Selection */
85062 #define USBPHY_USB1_CHRG_DETECT_TOG_DCDSEL(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_DCDSEL_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_DCDSEL_MASK)
85063 /*! @} */
85064 
85065 /*! @name USB1_CHRG_DET_STAT - Charger Detect Status */
85066 /*! @{ */
85067 
85068 #define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_MASK (0x1U)
85069 #define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_SHIFT (0U)
85070 /*! PLUG_CONTACT - Battery Charging Data Contact Detection Phase Output
85071  *  0b0..Not detected
85072  *  0b1..Detected
85073  */
85074 #define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_MASK)
85075 
85076 #define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_MASK (0x2U)
85077 #define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_SHIFT (1U)
85078 /*! CHRG_DETECTED - Battery Charging Primary Detection Phase Output
85079  *  0b0..SDP detected
85080  *  0b1..Charging port detected
85081  */
85082 #define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_MASK)
85083 
85084 #define USBPHY_USB1_CHRG_DET_STAT_DM_STATE_MASK  (0x4U)
85085 #define USBPHY_USB1_CHRG_DET_STAT_DM_STATE_SHIFT (2U)
85086 /*! DM_STATE - DM Voltage
85087  *  0b0..USB_DM pin voltage is <= 0.8 V
85088  *  0b1..USB_DM pin voltage is >= 2.0 V
85089  */
85090 #define USBPHY_USB1_CHRG_DET_STAT_DM_STATE(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_DM_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_DM_STATE_MASK)
85091 
85092 #define USBPHY_USB1_CHRG_DET_STAT_DP_STATE_MASK  (0x8U)
85093 #define USBPHY_USB1_CHRG_DET_STAT_DP_STATE_SHIFT (3U)
85094 /*! DP_STATE - DP Voltage
85095  *  0b0..USB_DP pin voltage is <= 0.8 V
85096  *  0b1..USB_DP pin voltage is >= 2.0 V
85097  */
85098 #define USBPHY_USB1_CHRG_DET_STAT_DP_STATE(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_DP_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_DP_STATE_MASK)
85099 
85100 #define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_MASK (0x10U)
85101 #define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_SHIFT (4U)
85102 /*! SECDET_DCP - Battery Charging Secondary Detection Phase Output
85103  *  0b0..CDP detected
85104  *  0b1..DCP detected
85105  */
85106 #define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_MASK)
85107 /*! @} */
85108 
85109 /*! @name USB1_CHRG_DET_STAT_SET - Charger Detect Status */
85110 /*! @{ */
85111 
85112 #define USBPHY_USB1_CHRG_DET_STAT_SET_PLUG_CONTACT_MASK (0x1U)
85113 #define USBPHY_USB1_CHRG_DET_STAT_SET_PLUG_CONTACT_SHIFT (0U)
85114 /*! PLUG_CONTACT - Battery Charging Data Contact Detection Phase Output */
85115 #define USBPHY_USB1_CHRG_DET_STAT_SET_PLUG_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_SET_PLUG_CONTACT_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_SET_PLUG_CONTACT_MASK)
85116 
85117 #define USBPHY_USB1_CHRG_DET_STAT_SET_CHRG_DETECTED_MASK (0x2U)
85118 #define USBPHY_USB1_CHRG_DET_STAT_SET_CHRG_DETECTED_SHIFT (1U)
85119 /*! CHRG_DETECTED - Battery Charging Primary Detection Phase Output */
85120 #define USBPHY_USB1_CHRG_DET_STAT_SET_CHRG_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_SET_CHRG_DETECTED_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_SET_CHRG_DETECTED_MASK)
85121 
85122 #define USBPHY_USB1_CHRG_DET_STAT_SET_DM_STATE_MASK (0x4U)
85123 #define USBPHY_USB1_CHRG_DET_STAT_SET_DM_STATE_SHIFT (2U)
85124 /*! DM_STATE - DM Voltage */
85125 #define USBPHY_USB1_CHRG_DET_STAT_SET_DM_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_SET_DM_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_SET_DM_STATE_MASK)
85126 
85127 #define USBPHY_USB1_CHRG_DET_STAT_SET_DP_STATE_MASK (0x8U)
85128 #define USBPHY_USB1_CHRG_DET_STAT_SET_DP_STATE_SHIFT (3U)
85129 /*! DP_STATE - DP Voltage */
85130 #define USBPHY_USB1_CHRG_DET_STAT_SET_DP_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_SET_DP_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_SET_DP_STATE_MASK)
85131 
85132 #define USBPHY_USB1_CHRG_DET_STAT_SET_SECDET_DCP_MASK (0x10U)
85133 #define USBPHY_USB1_CHRG_DET_STAT_SET_SECDET_DCP_SHIFT (4U)
85134 /*! SECDET_DCP - Battery Charging Secondary Detection Phase Output */
85135 #define USBPHY_USB1_CHRG_DET_STAT_SET_SECDET_DCP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_SET_SECDET_DCP_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_SET_SECDET_DCP_MASK)
85136 /*! @} */
85137 
85138 /*! @name USB1_CHRG_DET_STAT_CLR - Charger Detect Status */
85139 /*! @{ */
85140 
85141 #define USBPHY_USB1_CHRG_DET_STAT_CLR_PLUG_CONTACT_MASK (0x1U)
85142 #define USBPHY_USB1_CHRG_DET_STAT_CLR_PLUG_CONTACT_SHIFT (0U)
85143 /*! PLUG_CONTACT - Battery Charging Data Contact Detection Phase Output */
85144 #define USBPHY_USB1_CHRG_DET_STAT_CLR_PLUG_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_CLR_PLUG_CONTACT_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_CLR_PLUG_CONTACT_MASK)
85145 
85146 #define USBPHY_USB1_CHRG_DET_STAT_CLR_CHRG_DETECTED_MASK (0x2U)
85147 #define USBPHY_USB1_CHRG_DET_STAT_CLR_CHRG_DETECTED_SHIFT (1U)
85148 /*! CHRG_DETECTED - Battery Charging Primary Detection Phase Output */
85149 #define USBPHY_USB1_CHRG_DET_STAT_CLR_CHRG_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_CLR_CHRG_DETECTED_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_CLR_CHRG_DETECTED_MASK)
85150 
85151 #define USBPHY_USB1_CHRG_DET_STAT_CLR_DM_STATE_MASK (0x4U)
85152 #define USBPHY_USB1_CHRG_DET_STAT_CLR_DM_STATE_SHIFT (2U)
85153 /*! DM_STATE - DM Voltage */
85154 #define USBPHY_USB1_CHRG_DET_STAT_CLR_DM_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_CLR_DM_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_CLR_DM_STATE_MASK)
85155 
85156 #define USBPHY_USB1_CHRG_DET_STAT_CLR_DP_STATE_MASK (0x8U)
85157 #define USBPHY_USB1_CHRG_DET_STAT_CLR_DP_STATE_SHIFT (3U)
85158 /*! DP_STATE - DP Voltage */
85159 #define USBPHY_USB1_CHRG_DET_STAT_CLR_DP_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_CLR_DP_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_CLR_DP_STATE_MASK)
85160 
85161 #define USBPHY_USB1_CHRG_DET_STAT_CLR_SECDET_DCP_MASK (0x10U)
85162 #define USBPHY_USB1_CHRG_DET_STAT_CLR_SECDET_DCP_SHIFT (4U)
85163 /*! SECDET_DCP - Battery Charging Secondary Detection Phase Output */
85164 #define USBPHY_USB1_CHRG_DET_STAT_CLR_SECDET_DCP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_CLR_SECDET_DCP_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_CLR_SECDET_DCP_MASK)
85165 /*! @} */
85166 
85167 /*! @name USB1_CHRG_DET_STAT_TOG - Charger Detect Status */
85168 /*! @{ */
85169 
85170 #define USBPHY_USB1_CHRG_DET_STAT_TOG_PLUG_CONTACT_MASK (0x1U)
85171 #define USBPHY_USB1_CHRG_DET_STAT_TOG_PLUG_CONTACT_SHIFT (0U)
85172 /*! PLUG_CONTACT - Battery Charging Data Contact Detection Phase Output */
85173 #define USBPHY_USB1_CHRG_DET_STAT_TOG_PLUG_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_TOG_PLUG_CONTACT_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_TOG_PLUG_CONTACT_MASK)
85174 
85175 #define USBPHY_USB1_CHRG_DET_STAT_TOG_CHRG_DETECTED_MASK (0x2U)
85176 #define USBPHY_USB1_CHRG_DET_STAT_TOG_CHRG_DETECTED_SHIFT (1U)
85177 /*! CHRG_DETECTED - Battery Charging Primary Detection Phase Output */
85178 #define USBPHY_USB1_CHRG_DET_STAT_TOG_CHRG_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_TOG_CHRG_DETECTED_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_TOG_CHRG_DETECTED_MASK)
85179 
85180 #define USBPHY_USB1_CHRG_DET_STAT_TOG_DM_STATE_MASK (0x4U)
85181 #define USBPHY_USB1_CHRG_DET_STAT_TOG_DM_STATE_SHIFT (2U)
85182 /*! DM_STATE - DM Voltage */
85183 #define USBPHY_USB1_CHRG_DET_STAT_TOG_DM_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_TOG_DM_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_TOG_DM_STATE_MASK)
85184 
85185 #define USBPHY_USB1_CHRG_DET_STAT_TOG_DP_STATE_MASK (0x8U)
85186 #define USBPHY_USB1_CHRG_DET_STAT_TOG_DP_STATE_SHIFT (3U)
85187 /*! DP_STATE - DP Voltage */
85188 #define USBPHY_USB1_CHRG_DET_STAT_TOG_DP_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_TOG_DP_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_TOG_DP_STATE_MASK)
85189 
85190 #define USBPHY_USB1_CHRG_DET_STAT_TOG_SECDET_DCP_MASK (0x10U)
85191 #define USBPHY_USB1_CHRG_DET_STAT_TOG_SECDET_DCP_SHIFT (4U)
85192 /*! SECDET_DCP - Battery Charging Secondary Detection Phase Output */
85193 #define USBPHY_USB1_CHRG_DET_STAT_TOG_SECDET_DCP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_TOG_SECDET_DCP_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_TOG_SECDET_DCP_MASK)
85194 /*! @} */
85195 
85196 /*! @name ANACTRL - Analog Control */
85197 /*! @{ */
85198 
85199 #define USBPHY_ANACTRL_LVI_EN_MASK               (0x2U)
85200 #define USBPHY_ANACTRL_LVI_EN_SHIFT              (1U)
85201 /*! LVI_EN - Internal Low Voltage Detector Enable
85202  *  0b0..Disable
85203  *  0b1..Enable
85204  */
85205 #define USBPHY_ANACTRL_LVI_EN(x)                 (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_LVI_EN_SHIFT)) & USBPHY_ANACTRL_LVI_EN_MASK)
85206 
85207 #define USBPHY_ANACTRL_PFD_CLK_SEL_MASK          (0xCU)
85208 #define USBPHY_ANACTRL_PFD_CLK_SEL_SHIFT         (2U)
85209 /*! PFD_CLK_SEL - PFD Clock Selection
85210  *  0b00..USB1PFDCLK = USB PLL reference clock
85211  *  0b01..USB1PFDCLK = pfd_clk / 4
85212  *  0b10..USB1PFDCLK frequency = pfd_clk / 2
85213  *  0b11..USB1PFDCLK = pfd_clk
85214  */
85215 #define USBPHY_ANACTRL_PFD_CLK_SEL(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_PFD_CLK_SEL_MASK)
85216 
85217 #define USBPHY_ANACTRL_DEV_PULLDOWN_MASK         (0x400U)
85218 #define USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT        (10U)
85219 /*! DEV_PULLDOWN - Device Pulldown Enable
85220  *  0b0..Disable
85221  *  0b1..Enable
85222  */
85223 #define USBPHY_ANACTRL_DEV_PULLDOWN(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_DEV_PULLDOWN_MASK)
85224 /*! @} */
85225 
85226 /*! @name ANACTRL_SET - Analog Control */
85227 /*! @{ */
85228 
85229 #define USBPHY_ANACTRL_SET_LVI_EN_MASK           (0x2U)
85230 #define USBPHY_ANACTRL_SET_LVI_EN_SHIFT          (1U)
85231 /*! LVI_EN - Internal Low Voltage Detector Enable */
85232 #define USBPHY_ANACTRL_SET_LVI_EN(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_LVI_EN_SHIFT)) & USBPHY_ANACTRL_SET_LVI_EN_MASK)
85233 
85234 #define USBPHY_ANACTRL_SET_PFD_CLK_SEL_MASK      (0xCU)
85235 #define USBPHY_ANACTRL_SET_PFD_CLK_SEL_SHIFT     (2U)
85236 /*! PFD_CLK_SEL - PFD Clock Selection */
85237 #define USBPHY_ANACTRL_SET_PFD_CLK_SEL(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_SET_PFD_CLK_SEL_MASK)
85238 
85239 #define USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK     (0x400U)
85240 #define USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT    (10U)
85241 /*! DEV_PULLDOWN - Device Pulldown Enable */
85242 #define USBPHY_ANACTRL_SET_DEV_PULLDOWN(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK)
85243 /*! @} */
85244 
85245 /*! @name ANACTRL_CLR - Analog Control */
85246 /*! @{ */
85247 
85248 #define USBPHY_ANACTRL_CLR_LVI_EN_MASK           (0x2U)
85249 #define USBPHY_ANACTRL_CLR_LVI_EN_SHIFT          (1U)
85250 /*! LVI_EN - Internal Low Voltage Detector Enable */
85251 #define USBPHY_ANACTRL_CLR_LVI_EN(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_LVI_EN_SHIFT)) & USBPHY_ANACTRL_CLR_LVI_EN_MASK)
85252 
85253 #define USBPHY_ANACTRL_CLR_PFD_CLK_SEL_MASK      (0xCU)
85254 #define USBPHY_ANACTRL_CLR_PFD_CLK_SEL_SHIFT     (2U)
85255 /*! PFD_CLK_SEL - PFD Clock Selection */
85256 #define USBPHY_ANACTRL_CLR_PFD_CLK_SEL(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_CLR_PFD_CLK_SEL_MASK)
85257 
85258 #define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK     (0x400U)
85259 #define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT    (10U)
85260 /*! DEV_PULLDOWN - Device Pulldown Enable */
85261 #define USBPHY_ANACTRL_CLR_DEV_PULLDOWN(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK)
85262 /*! @} */
85263 
85264 /*! @name ANACTRL_TOG - Analog Control */
85265 /*! @{ */
85266 
85267 #define USBPHY_ANACTRL_TOG_LVI_EN_MASK           (0x2U)
85268 #define USBPHY_ANACTRL_TOG_LVI_EN_SHIFT          (1U)
85269 /*! LVI_EN - Internal Low Voltage Detector Enable */
85270 #define USBPHY_ANACTRL_TOG_LVI_EN(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_LVI_EN_SHIFT)) & USBPHY_ANACTRL_TOG_LVI_EN_MASK)
85271 
85272 #define USBPHY_ANACTRL_TOG_PFD_CLK_SEL_MASK      (0xCU)
85273 #define USBPHY_ANACTRL_TOG_PFD_CLK_SEL_SHIFT     (2U)
85274 /*! PFD_CLK_SEL - PFD Clock Selection */
85275 #define USBPHY_ANACTRL_TOG_PFD_CLK_SEL(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_TOG_PFD_CLK_SEL_MASK)
85276 
85277 #define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK     (0x400U)
85278 #define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT    (10U)
85279 /*! DEV_PULLDOWN - Device Pulldown Enable */
85280 #define USBPHY_ANACTRL_TOG_DEV_PULLDOWN(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK)
85281 /*! @} */
85282 
85283 /*! @name TRIM_OVERRIDE_EN - Trim */
85284 /*! @{ */
85285 
85286 #define USBPHY_TRIM_OVERRIDE_EN_DIV_SEL_OVERRIDE_MASK (0x1U)
85287 #define USBPHY_TRIM_OVERRIDE_EN_DIV_SEL_OVERRIDE_SHIFT (0U)
85288 /*! DIV_SEL_OVERRIDE - Override Enable for PLL Divider Value
85289  *  0b0..TRIM_OVERRIDE_EN
85290  *  0b1..PLL_SIC
85291  */
85292 #define USBPHY_TRIM_OVERRIDE_EN_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_DIV_SEL_OVERRIDE_MASK)
85293 
85294 #define USBPHY_TRIM_OVERRIDE_EN_TX_D_CAL_OVERRIDE_MASK (0x4U)
85295 #define USBPHY_TRIM_OVERRIDE_EN_TX_D_CAL_OVERRIDE_SHIFT (2U)
85296 /*! TX_D_CAL_OVERRIDE - Override Enable for HS TX Output Current Trim
85297  *  0b0..TRIM_OVERRIDE_EN
85298  *  0b1..TX
85299  */
85300 #define USBPHY_TRIM_OVERRIDE_EN_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TX_D_CAL_OVERRIDE_MASK)
85301 
85302 #define USBPHY_TRIM_OVERRIDE_EN_TX_CAL45DP_OVERRIDE_MASK (0x8U)
85303 #define USBPHY_TRIM_OVERRIDE_EN_TX_CAL45DP_OVERRIDE_SHIFT (3U)
85304 /*! TX_CAL45DP_OVERRIDE - Override Enable for USB_DP Series Termination Trim
85305  *  0b0..TRIM_OVERRIDE_EN
85306  *  0b1..TX
85307  */
85308 #define USBPHY_TRIM_OVERRIDE_EN_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TX_CAL45DP_OVERRIDE_MASK)
85309 
85310 #define USBPHY_TRIM_OVERRIDE_EN_TX_CAL45DM_OVERRIDE_MASK (0x10U)
85311 #define USBPHY_TRIM_OVERRIDE_EN_TX_CAL45DM_OVERRIDE_SHIFT (4U)
85312 /*! TX_CAL45DM_OVERRIDE - Override Enable for USB_DM Series Termination Trim
85313  *  0b0..TRIM_OVERRIDE_EN
85314  *  0b1..TX
85315  */
85316 #define USBPHY_TRIM_OVERRIDE_EN_TX_CAL45DM_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TX_CAL45DM_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TX_CAL45DM_OVERRIDE_MASK)
85317 
85318 #define USBPHY_TRIM_OVERRIDE_EN_PLL_CTRL0_DIV_SEL_MASK (0x38000U)
85319 #define USBPHY_TRIM_OVERRIDE_EN_PLL_CTRL0_DIV_SEL_SHIFT (15U)
85320 /*! PLL_CTRL0_DIV_SEL - PLL Divider Value Configuration Bits from Outside USBPHY */
85321 #define USBPHY_TRIM_OVERRIDE_EN_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_PLL_CTRL0_DIV_SEL_MASK)
85322 
85323 #define USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_D_CAL_MASK (0xF00000U)
85324 #define USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_D_CAL_SHIFT (20U)
85325 /*! USBPHY_TX_D_CAL - HS TX Output Current Trim Bits from Outside USBPHY
85326  *  0b0000..Maximum current, approximately 19% above nominal
85327  *  0b0111..Nominal
85328  *  0b1111..Minimum current, approximately 19% below nominal
85329  */
85330 #define USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_D_CAL_MASK)
85331 
85332 #define USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_CAL45DP_MASK (0xF000000U)
85333 #define USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_CAL45DP_SHIFT (24U)
85334 /*! USBPHY_TX_CAL45DP - DP Series Termination Resistance Trim Bits from Outside USBPHY */
85335 #define USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_CAL45DP_MASK)
85336 
85337 #define USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_CAL45DN_MASK (0xF0000000U)
85338 #define USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_CAL45DN_SHIFT (28U)
85339 /*! USBPHY_TX_CAL45DN - DM Series Termination Resistance Trim Bits from Outside USBPHY */
85340 #define USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_CAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_CAL45DN_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_CAL45DN_MASK)
85341 /*! @} */
85342 
85343 /*! @name TRIM_OVERRIDE_EN_SET - Trim */
85344 /*! @{ */
85345 
85346 #define USBPHY_TRIM_OVERRIDE_EN_SET_DIV_SEL_OVERRIDE_MASK (0x1U)
85347 #define USBPHY_TRIM_OVERRIDE_EN_SET_DIV_SEL_OVERRIDE_SHIFT (0U)
85348 /*! DIV_SEL_OVERRIDE - Override Enable for PLL Divider Value */
85349 #define USBPHY_TRIM_OVERRIDE_EN_SET_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_DIV_SEL_OVERRIDE_MASK)
85350 
85351 #define USBPHY_TRIM_OVERRIDE_EN_SET_TX_D_CAL_OVERRIDE_MASK (0x4U)
85352 #define USBPHY_TRIM_OVERRIDE_EN_SET_TX_D_CAL_OVERRIDE_SHIFT (2U)
85353 /*! TX_D_CAL_OVERRIDE - Override Enable for HS TX Output Current Trim */
85354 #define USBPHY_TRIM_OVERRIDE_EN_SET_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TX_D_CAL_OVERRIDE_MASK)
85355 
85356 #define USBPHY_TRIM_OVERRIDE_EN_SET_TX_CAL45DP_OVERRIDE_MASK (0x8U)
85357 #define USBPHY_TRIM_OVERRIDE_EN_SET_TX_CAL45DP_OVERRIDE_SHIFT (3U)
85358 /*! TX_CAL45DP_OVERRIDE - Override Enable for USB_DP Series Termination Trim */
85359 #define USBPHY_TRIM_OVERRIDE_EN_SET_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TX_CAL45DP_OVERRIDE_MASK)
85360 
85361 #define USBPHY_TRIM_OVERRIDE_EN_SET_TX_CAL45DM_OVERRIDE_MASK (0x10U)
85362 #define USBPHY_TRIM_OVERRIDE_EN_SET_TX_CAL45DM_OVERRIDE_SHIFT (4U)
85363 /*! TX_CAL45DM_OVERRIDE - Override Enable for USB_DM Series Termination Trim */
85364 #define USBPHY_TRIM_OVERRIDE_EN_SET_TX_CAL45DM_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TX_CAL45DM_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TX_CAL45DM_OVERRIDE_MASK)
85365 
85366 #define USBPHY_TRIM_OVERRIDE_EN_SET_PLL_CTRL0_DIV_SEL_MASK (0x38000U)
85367 #define USBPHY_TRIM_OVERRIDE_EN_SET_PLL_CTRL0_DIV_SEL_SHIFT (15U)
85368 /*! PLL_CTRL0_DIV_SEL - PLL Divider Value Configuration Bits from Outside USBPHY */
85369 #define USBPHY_TRIM_OVERRIDE_EN_SET_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_PLL_CTRL0_DIV_SEL_MASK)
85370 
85371 #define USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_D_CAL_MASK (0xF00000U)
85372 #define USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_D_CAL_SHIFT (20U)
85373 /*! USBPHY_TX_D_CAL - HS TX Output Current Trim Bits from Outside USBPHY */
85374 #define USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_D_CAL_MASK)
85375 
85376 #define USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_CAL45DP_MASK (0xF000000U)
85377 #define USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_CAL45DP_SHIFT (24U)
85378 /*! USBPHY_TX_CAL45DP - DP Series Termination Resistance Trim Bits from Outside USBPHY */
85379 #define USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_CAL45DP_MASK)
85380 
85381 #define USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_CAL45DN_MASK (0xF0000000U)
85382 #define USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_CAL45DN_SHIFT (28U)
85383 /*! USBPHY_TX_CAL45DN - DM Series Termination Resistance Trim Bits from Outside USBPHY */
85384 #define USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_CAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_CAL45DN_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_CAL45DN_MASK)
85385 /*! @} */
85386 
85387 /*! @name TRIM_OVERRIDE_EN_CLR - Trim */
85388 /*! @{ */
85389 
85390 #define USBPHY_TRIM_OVERRIDE_EN_CLR_DIV_SEL_OVERRIDE_MASK (0x1U)
85391 #define USBPHY_TRIM_OVERRIDE_EN_CLR_DIV_SEL_OVERRIDE_SHIFT (0U)
85392 /*! DIV_SEL_OVERRIDE - Override Enable for PLL Divider Value */
85393 #define USBPHY_TRIM_OVERRIDE_EN_CLR_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_DIV_SEL_OVERRIDE_MASK)
85394 
85395 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TX_D_CAL_OVERRIDE_MASK (0x4U)
85396 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TX_D_CAL_OVERRIDE_SHIFT (2U)
85397 /*! TX_D_CAL_OVERRIDE - Override Enable for HS TX Output Current Trim */
85398 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TX_D_CAL_OVERRIDE_MASK)
85399 
85400 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TX_CAL45DP_OVERRIDE_MASK (0x8U)
85401 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TX_CAL45DP_OVERRIDE_SHIFT (3U)
85402 /*! TX_CAL45DP_OVERRIDE - Override Enable for USB_DP Series Termination Trim */
85403 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TX_CAL45DP_OVERRIDE_MASK)
85404 
85405 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TX_CAL45DM_OVERRIDE_MASK (0x10U)
85406 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TX_CAL45DM_OVERRIDE_SHIFT (4U)
85407 /*! TX_CAL45DM_OVERRIDE - Override Enable for USB_DM Series Termination Trim */
85408 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TX_CAL45DM_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TX_CAL45DM_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TX_CAL45DM_OVERRIDE_MASK)
85409 
85410 #define USBPHY_TRIM_OVERRIDE_EN_CLR_PLL_CTRL0_DIV_SEL_MASK (0x38000U)
85411 #define USBPHY_TRIM_OVERRIDE_EN_CLR_PLL_CTRL0_DIV_SEL_SHIFT (15U)
85412 /*! PLL_CTRL0_DIV_SEL - PLL Divider Value Configuration Bits from Outside USBPHY */
85413 #define USBPHY_TRIM_OVERRIDE_EN_CLR_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_PLL_CTRL0_DIV_SEL_MASK)
85414 
85415 #define USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_D_CAL_MASK (0xF00000U)
85416 #define USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_D_CAL_SHIFT (20U)
85417 /*! USBPHY_TX_D_CAL - HS TX Output Current Trim Bits from Outside USBPHY */
85418 #define USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_D_CAL_MASK)
85419 
85420 #define USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_CAL45DP_MASK (0xF000000U)
85421 #define USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_CAL45DP_SHIFT (24U)
85422 /*! USBPHY_TX_CAL45DP - DP Series Termination Resistance Trim Bits from Outside USBPHY */
85423 #define USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_CAL45DP_MASK)
85424 
85425 #define USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_CAL45DN_MASK (0xF0000000U)
85426 #define USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_CAL45DN_SHIFT (28U)
85427 /*! USBPHY_TX_CAL45DN - DM Series Termination Resistance Trim Bits from Outside USBPHY */
85428 #define USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_CAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_CAL45DN_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_CAL45DN_MASK)
85429 /*! @} */
85430 
85431 /*! @name TRIM_OVERRIDE_EN_TOG - Trim */
85432 /*! @{ */
85433 
85434 #define USBPHY_TRIM_OVERRIDE_EN_TOG_DIV_SEL_OVERRIDE_MASK (0x1U)
85435 #define USBPHY_TRIM_OVERRIDE_EN_TOG_DIV_SEL_OVERRIDE_SHIFT (0U)
85436 /*! DIV_SEL_OVERRIDE - Override Enable for PLL Divider Value */
85437 #define USBPHY_TRIM_OVERRIDE_EN_TOG_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_DIV_SEL_OVERRIDE_MASK)
85438 
85439 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TX_D_CAL_OVERRIDE_MASK (0x4U)
85440 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TX_D_CAL_OVERRIDE_SHIFT (2U)
85441 /*! TX_D_CAL_OVERRIDE - Override Enable for HS TX Output Current Trim */
85442 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TX_D_CAL_OVERRIDE_MASK)
85443 
85444 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TX_CAL45DP_OVERRIDE_MASK (0x8U)
85445 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TX_CAL45DP_OVERRIDE_SHIFT (3U)
85446 /*! TX_CAL45DP_OVERRIDE - Override Enable for USB_DP Series Termination Trim */
85447 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TX_CAL45DP_OVERRIDE_MASK)
85448 
85449 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TX_CAL45DM_OVERRIDE_MASK (0x10U)
85450 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TX_CAL45DM_OVERRIDE_SHIFT (4U)
85451 /*! TX_CAL45DM_OVERRIDE - Override Enable for USB_DM Series Termination Trim */
85452 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TX_CAL45DM_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TX_CAL45DM_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TX_CAL45DM_OVERRIDE_MASK)
85453 
85454 #define USBPHY_TRIM_OVERRIDE_EN_TOG_PLL_CTRL0_DIV_SEL_MASK (0x38000U)
85455 #define USBPHY_TRIM_OVERRIDE_EN_TOG_PLL_CTRL0_DIV_SEL_SHIFT (15U)
85456 /*! PLL_CTRL0_DIV_SEL - PLL Divider Value Configuration Bits from Outside USBPHY */
85457 #define USBPHY_TRIM_OVERRIDE_EN_TOG_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_PLL_CTRL0_DIV_SEL_MASK)
85458 
85459 #define USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_D_CAL_MASK (0xF00000U)
85460 #define USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_D_CAL_SHIFT (20U)
85461 /*! USBPHY_TX_D_CAL - HS TX Output Current Trim Bits from Outside USBPHY */
85462 #define USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_D_CAL_MASK)
85463 
85464 #define USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_CAL45DP_MASK (0xF000000U)
85465 #define USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_CAL45DP_SHIFT (24U)
85466 /*! USBPHY_TX_CAL45DP - DP Series Termination Resistance Trim Bits from Outside USBPHY */
85467 #define USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_CAL45DP_MASK)
85468 
85469 #define USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_CAL45DN_MASK (0xF0000000U)
85470 #define USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_CAL45DN_SHIFT (28U)
85471 /*! USBPHY_TX_CAL45DN - DM Series Termination Resistance Trim Bits from Outside USBPHY */
85472 #define USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_CAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_CAL45DN_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_CAL45DN_MASK)
85473 /*! @} */
85474 
85475 /*! @name PFDA - PFD A */
85476 /*! @{ */
85477 
85478 #define USBPHY_PFDA_PFD0_CLKGATE_MASK            (0x1U)
85479 #define USBPHY_PFDA_PFD0_CLKGATE_SHIFT           (0U)
85480 /*! PFD0_CLKGATE - PFD0 Clock Gate
85481  *  0b0..Enable
85482  *  0b1..Disable
85483  */
85484 #define USBPHY_PFDA_PFD0_CLKGATE(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_PFDA_PFD0_CLKGATE_SHIFT)) & USBPHY_PFDA_PFD0_CLKGATE_MASK)
85485 
85486 #define USBPHY_PFDA_PFD0_FRAC_MASK               (0x7EU)
85487 #define USBPHY_PFDA_PFD0_FRAC_SHIFT              (1U)
85488 /*! PFD0_FRAC - PFD0 Fractional Divider */
85489 #define USBPHY_PFDA_PFD0_FRAC(x)                 (((uint32_t)(((uint32_t)(x)) << USBPHY_PFDA_PFD0_FRAC_SHIFT)) & USBPHY_PFDA_PFD0_FRAC_MASK)
85490 
85491 #define USBPHY_PFDA_PFD0_STABLE_MASK             (0x80U)
85492 #define USBPHY_PFDA_PFD0_STABLE_SHIFT            (7U)
85493 /*! PFD0_STABLE - PFD0 Stable Signal
85494  *  0b0..Not stable
85495  *  0b1..Stable
85496  */
85497 #define USBPHY_PFDA_PFD0_STABLE(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_PFDA_PFD0_STABLE_SHIFT)) & USBPHY_PFDA_PFD0_STABLE_MASK)
85498 /*! @} */
85499 
85500 /*! @name PFDA_SET - PFD A */
85501 /*! @{ */
85502 
85503 #define USBPHY_PFDA_SET_PFD0_CLKGATE_MASK        (0x1U)
85504 #define USBPHY_PFDA_SET_PFD0_CLKGATE_SHIFT       (0U)
85505 /*! PFD0_CLKGATE - PFD0 Clock Gate */
85506 #define USBPHY_PFDA_SET_PFD0_CLKGATE(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_PFDA_SET_PFD0_CLKGATE_SHIFT)) & USBPHY_PFDA_SET_PFD0_CLKGATE_MASK)
85507 
85508 #define USBPHY_PFDA_SET_PFD0_FRAC_MASK           (0x7EU)
85509 #define USBPHY_PFDA_SET_PFD0_FRAC_SHIFT          (1U)
85510 /*! PFD0_FRAC - PFD0 Fractional Divider */
85511 #define USBPHY_PFDA_SET_PFD0_FRAC(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_PFDA_SET_PFD0_FRAC_SHIFT)) & USBPHY_PFDA_SET_PFD0_FRAC_MASK)
85512 
85513 #define USBPHY_PFDA_SET_PFD0_STABLE_MASK         (0x80U)
85514 #define USBPHY_PFDA_SET_PFD0_STABLE_SHIFT        (7U)
85515 /*! PFD0_STABLE - PFD0 Stable Signal */
85516 #define USBPHY_PFDA_SET_PFD0_STABLE(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_PFDA_SET_PFD0_STABLE_SHIFT)) & USBPHY_PFDA_SET_PFD0_STABLE_MASK)
85517 /*! @} */
85518 
85519 /*! @name PFDA_CLR - PFD A */
85520 /*! @{ */
85521 
85522 #define USBPHY_PFDA_CLR_PFD0_CLKGATE_MASK        (0x1U)
85523 #define USBPHY_PFDA_CLR_PFD0_CLKGATE_SHIFT       (0U)
85524 /*! PFD0_CLKGATE - PFD0 Clock Gate */
85525 #define USBPHY_PFDA_CLR_PFD0_CLKGATE(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_PFDA_CLR_PFD0_CLKGATE_SHIFT)) & USBPHY_PFDA_CLR_PFD0_CLKGATE_MASK)
85526 
85527 #define USBPHY_PFDA_CLR_PFD0_FRAC_MASK           (0x7EU)
85528 #define USBPHY_PFDA_CLR_PFD0_FRAC_SHIFT          (1U)
85529 /*! PFD0_FRAC - PFD0 Fractional Divider */
85530 #define USBPHY_PFDA_CLR_PFD0_FRAC(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_PFDA_CLR_PFD0_FRAC_SHIFT)) & USBPHY_PFDA_CLR_PFD0_FRAC_MASK)
85531 
85532 #define USBPHY_PFDA_CLR_PFD0_STABLE_MASK         (0x80U)
85533 #define USBPHY_PFDA_CLR_PFD0_STABLE_SHIFT        (7U)
85534 /*! PFD0_STABLE - PFD0 Stable Signal */
85535 #define USBPHY_PFDA_CLR_PFD0_STABLE(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_PFDA_CLR_PFD0_STABLE_SHIFT)) & USBPHY_PFDA_CLR_PFD0_STABLE_MASK)
85536 /*! @} */
85537 
85538 /*! @name PFDA_TOG - PFD A */
85539 /*! @{ */
85540 
85541 #define USBPHY_PFDA_TOG_PFD0_CLKGATE_MASK        (0x1U)
85542 #define USBPHY_PFDA_TOG_PFD0_CLKGATE_SHIFT       (0U)
85543 /*! PFD0_CLKGATE - PFD0 Clock Gate */
85544 #define USBPHY_PFDA_TOG_PFD0_CLKGATE(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_PFDA_TOG_PFD0_CLKGATE_SHIFT)) & USBPHY_PFDA_TOG_PFD0_CLKGATE_MASK)
85545 
85546 #define USBPHY_PFDA_TOG_PFD0_FRAC_MASK           (0x7EU)
85547 #define USBPHY_PFDA_TOG_PFD0_FRAC_SHIFT          (1U)
85548 /*! PFD0_FRAC - PFD0 Fractional Divider */
85549 #define USBPHY_PFDA_TOG_PFD0_FRAC(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_PFDA_TOG_PFD0_FRAC_SHIFT)) & USBPHY_PFDA_TOG_PFD0_FRAC_MASK)
85550 
85551 #define USBPHY_PFDA_TOG_PFD0_STABLE_MASK         (0x80U)
85552 #define USBPHY_PFDA_TOG_PFD0_STABLE_SHIFT        (7U)
85553 /*! PFD0_STABLE - PFD0 Stable Signal */
85554 #define USBPHY_PFDA_TOG_PFD0_STABLE(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_PFDA_TOG_PFD0_STABLE_SHIFT)) & USBPHY_PFDA_TOG_PFD0_STABLE_MASK)
85555 /*! @} */
85556 
85557 
85558 /*!
85559  * @}
85560  */ /* end of group USBPHY_Register_Masks */
85561 
85562 
85563 /* USBPHY - Peripheral instance base addresses */
85564 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
85565   /** Peripheral USBPHY base address */
85566   #define USBPHY_BASE                              (0x5010A000u)
85567   /** Peripheral USBPHY base address */
85568   #define USBPHY_BASE_NS                           (0x4010A000u)
85569   /** Peripheral USBPHY base pointer */
85570   #define USBPHY                                   ((USBPHY_Type *)USBPHY_BASE)
85571   /** Peripheral USBPHY base pointer */
85572   #define USBPHY_NS                                ((USBPHY_Type *)USBPHY_BASE_NS)
85573   /** Array initializer of USBPHY peripheral base addresses */
85574   #define USBPHY_BASE_ADDRS                        { USBPHY_BASE }
85575   /** Array initializer of USBPHY peripheral base pointers */
85576   #define USBPHY_BASE_PTRS                         { USBPHY }
85577   /** Array initializer of USBPHY peripheral base addresses */
85578   #define USBPHY_BASE_ADDRS_NS                     { USBPHY_BASE_NS }
85579   /** Array initializer of USBPHY peripheral base pointers */
85580   #define USBPHY_BASE_PTRS_NS                      { USBPHY_NS }
85581 #else
85582   /** Peripheral USBPHY base address */
85583   #define USBPHY_BASE                              (0x4010A000u)
85584   /** Peripheral USBPHY base pointer */
85585   #define USBPHY                                   ((USBPHY_Type *)USBPHY_BASE)
85586   /** Array initializer of USBPHY peripheral base addresses */
85587   #define USBPHY_BASE_ADDRS                        { USBPHY_BASE }
85588   /** Array initializer of USBPHY peripheral base pointers */
85589   #define USBPHY_BASE_PTRS                         { USBPHY }
85590 #endif
85591 /** Interrupt vectors for the USBPHY peripheral type */
85592 #define USBPHY_IRQS                              { USB1_HS_PHY_IRQn }
85593 /* Backward compatibility */
85594 #define USBPHY_CTRL_ENDEVPLUGINDET_MASK     USBPHY_CTRL_ENDEVPLUGINDETECT_MASK
85595 #define USBPHY_CTRL_ENDEVPLUGINDET_SHIFT    USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT
85596 #define USBPHY_CTRL_ENDEVPLUGINDET(x)       USBPHY_CTRL_ENDEVPLUGINDETECT(x)
85597 #define USBPHY_TX_TXCAL45DM_MASK            USBPHY_TX_TXCAL45DN_MASK
85598 #define USBPHY_TX_TXCAL45DM_SHIFT           USBPHY_TX_TXCAL45DN_SHIFT
85599 #define USBPHY_TX_TXCAL45DM(x)              USBPHY_TX_TXCAL45DN(x)
85600 
85601 
85602 /*!
85603  * @}
85604  */ /* end of group USBPHY_Peripheral_Access_Layer */
85605 
85606 
85607 /* ----------------------------------------------------------------------------
85608    -- USDHC Peripheral Access Layer
85609    ---------------------------------------------------------------------------- */
85610 
85611 /*!
85612  * @addtogroup USDHC_Peripheral_Access_Layer USDHC Peripheral Access Layer
85613  * @{
85614  */
85615 
85616 /** USDHC - Register Layout Typedef */
85617 typedef struct {
85618   __IO uint32_t DS_ADDR;                           /**< DMA System Address, offset: 0x0 */
85619   __IO uint32_t BLK_ATT;                           /**< Block Attributes, offset: 0x4 */
85620   __IO uint32_t CMD_ARG;                           /**< Command Argument, offset: 0x8 */
85621   __IO uint32_t CMD_XFR_TYP;                       /**< Command Transfer Type, offset: 0xC */
85622   __I  uint32_t CMD_RSP0;                          /**< Command Response0, offset: 0x10 */
85623   __I  uint32_t CMD_RSP1;                          /**< Command Response1, offset: 0x14 */
85624   __I  uint32_t CMD_RSP2;                          /**< Command Response2, offset: 0x18 */
85625   __I  uint32_t CMD_RSP3;                          /**< Command Response3, offset: 0x1C */
85626   __IO uint32_t DATA_BUFF_ACC_PORT;                /**< Data Buffer Access Port, offset: 0x20 */
85627   __I  uint32_t PRES_STATE;                        /**< Present State, offset: 0x24 */
85628   __IO uint32_t PROT_CTRL;                         /**< Protocol Control, offset: 0x28 */
85629   __IO uint32_t SYS_CTRL;                          /**< System Control, offset: 0x2C */
85630   __IO uint32_t INT_STATUS;                        /**< Interrupt Status, offset: 0x30 */
85631   __IO uint32_t INT_STATUS_EN;                     /**< Interrupt Status Enable, offset: 0x34 */
85632   __IO uint32_t INT_SIGNAL_EN;                     /**< Interrupt Signal Enable, offset: 0x38 */
85633   __IO uint32_t AUTOCMD12_ERR_STATUS;              /**< Auto CMD12 Error Status, offset: 0x3C */
85634   __IO uint32_t HOST_CTRL_CAP;                     /**< Host Controller Capabilities, offset: 0x40 */
85635   __IO uint32_t WTMK_LVL;                          /**< Watermark Level, offset: 0x44 */
85636   __IO uint32_t MIX_CTRL;                          /**< Mixer Control, offset: 0x48 */
85637        uint8_t RESERVED_0[4];
85638   __O  uint32_t FORCE_EVENT;                       /**< Force Event, offset: 0x50 */
85639   __I  uint32_t ADMA_ERR_STATUS;                   /**< ADMA Error Status, offset: 0x54 */
85640   __IO uint32_t ADMA_SYS_ADDR;                     /**< ADMA System Address, offset: 0x58 */
85641        uint8_t RESERVED_1[4];
85642   __IO uint32_t DLL_CTRL;                          /**< DLL (Delay Line) Control, offset: 0x60 */
85643   __I  uint32_t DLL_STATUS;                        /**< DLL Status, offset: 0x64 */
85644   __IO uint32_t CLK_TUNE_CTRL_STATUS;              /**< CLK Tuning Control and Status, offset: 0x68 */
85645        uint8_t RESERVED_2[84];
85646   __IO uint32_t VEND_SPEC;                         /**< Vendor Specific Register, offset: 0xC0 */
85647   __IO uint32_t MMC_BOOT;                          /**< eMMC Boot, offset: 0xC4 */
85648   __IO uint32_t VEND_SPEC2;                        /**< Vendor Specific 2 Register, offset: 0xC8 */
85649   __IO uint32_t TUNING_CTRL;                       /**< Tuning Control, offset: 0xCC */
85650 } USDHC_Type;
85651 
85652 /* ----------------------------------------------------------------------------
85653    -- USDHC Register Masks
85654    ---------------------------------------------------------------------------- */
85655 
85656 /*!
85657  * @addtogroup USDHC_Register_Masks USDHC Register Masks
85658  * @{
85659  */
85660 
85661 /*! @name DS_ADDR - DMA System Address */
85662 /*! @{ */
85663 
85664 #define USDHC_DS_ADDR_DS_ADDR_MASK               (0xFFFFFFFFU)
85665 #define USDHC_DS_ADDR_DS_ADDR_SHIFT              (0U)
85666 /*! DS_ADDR - System address */
85667 #define USDHC_DS_ADDR_DS_ADDR(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_DS_ADDR_DS_ADDR_SHIFT)) & USDHC_DS_ADDR_DS_ADDR_MASK)
85668 /*! @} */
85669 
85670 /*! @name BLK_ATT - Block Attributes */
85671 /*! @{ */
85672 
85673 #define USDHC_BLK_ATT_BLKSIZE_MASK               (0x1FFFU)
85674 #define USDHC_BLK_ATT_BLKSIZE_SHIFT              (0U)
85675 /*! BLKSIZE - Transfer block size
85676  *  0b1000000000000..4096 bytes
85677  *  0b0100000000000..2048 bytes
85678  *  0b0001000000000..512 bytes
85679  *  0b0000111111111..511 bytes
85680  *  0b0000000000100..4 bytes
85681  *  0b0000000000011..3 bytes
85682  *  0b0000000000010..2 bytes
85683  *  0b0000000000001..1 byte
85684  *  0b0000000000000..No data transfer
85685  */
85686 #define USDHC_BLK_ATT_BLKSIZE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKSIZE_SHIFT)) & USDHC_BLK_ATT_BLKSIZE_MASK)
85687 
85688 #define USDHC_BLK_ATT_BLKCNT_MASK                (0xFFFF0000U)
85689 #define USDHC_BLK_ATT_BLKCNT_SHIFT               (16U)
85690 /*! BLKCNT - Blocks count for current transfer
85691  *  0b1111111111111111..65535 blocks
85692  *  0b0000000000000010..2 blocks
85693  *  0b0000000000000001..1 block
85694  *  0b0000000000000000..Stop count
85695  */
85696 #define USDHC_BLK_ATT_BLKCNT(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKCNT_SHIFT)) & USDHC_BLK_ATT_BLKCNT_MASK)
85697 /*! @} */
85698 
85699 /*! @name CMD_ARG - Command Argument */
85700 /*! @{ */
85701 
85702 #define USDHC_CMD_ARG_CMDARG_MASK                (0xFFFFFFFFU)
85703 #define USDHC_CMD_ARG_CMDARG_SHIFT               (0U)
85704 /*! CMDARG - Command argument */
85705 #define USDHC_CMD_ARG_CMDARG(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_ARG_CMDARG_SHIFT)) & USDHC_CMD_ARG_CMDARG_MASK)
85706 /*! @} */
85707 
85708 /*! @name CMD_XFR_TYP - Command Transfer Type */
85709 /*! @{ */
85710 
85711 #define USDHC_CMD_XFR_TYP_DMAEN_MASK             (0x1U)
85712 #define USDHC_CMD_XFR_TYP_DMAEN_SHIFT            (0U)
85713 /*! DMAEN - DMAEN
85714  *  0b0..Disable
85715  *  0b1..Enable
85716  */
85717 #define USDHC_CMD_XFR_TYP_DMAEN(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DMAEN_SHIFT)) & USDHC_CMD_XFR_TYP_DMAEN_MASK)
85718 
85719 #define USDHC_CMD_XFR_TYP_BCEN_MASK              (0x2U)
85720 #define USDHC_CMD_XFR_TYP_BCEN_SHIFT             (1U)
85721 /*! BCEN - BCEN
85722  *  0b0..Disable
85723  *  0b1..Enable
85724  */
85725 #define USDHC_CMD_XFR_TYP_BCEN(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_BCEN_SHIFT)) & USDHC_CMD_XFR_TYP_BCEN_MASK)
85726 
85727 #define USDHC_CMD_XFR_TYP_AC12EN_MASK            (0x4U)
85728 #define USDHC_CMD_XFR_TYP_AC12EN_SHIFT           (2U)
85729 /*! AC12EN - AC12EN
85730  *  0b0..Disable
85731  *  0b1..Enable
85732  */
85733 #define USDHC_CMD_XFR_TYP_AC12EN(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_AC12EN_SHIFT)) & USDHC_CMD_XFR_TYP_AC12EN_MASK)
85734 
85735 #define USDHC_CMD_XFR_TYP_DDR_EN_MASK            (0x8U)
85736 #define USDHC_CMD_XFR_TYP_DDR_EN_SHIFT           (3U)
85737 /*! DDR_EN - DDR_EN
85738  *  0b0..Disable
85739  *  0b1..Enable
85740  */
85741 #define USDHC_CMD_XFR_TYP_DDR_EN(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DDR_EN_SHIFT)) & USDHC_CMD_XFR_TYP_DDR_EN_MASK)
85742 
85743 #define USDHC_CMD_XFR_TYP_DTDSEL_MASK            (0x10U)
85744 #define USDHC_CMD_XFR_TYP_DTDSEL_SHIFT           (4U)
85745 /*! DTDSEL - DTDSEL
85746  *  0b0..Disable
85747  *  0b1..Enable
85748  */
85749 #define USDHC_CMD_XFR_TYP_DTDSEL(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DTDSEL_SHIFT)) & USDHC_CMD_XFR_TYP_DTDSEL_MASK)
85750 
85751 #define USDHC_CMD_XFR_TYP_MSBSEL_MASK            (0x20U)
85752 #define USDHC_CMD_XFR_TYP_MSBSEL_SHIFT           (5U)
85753 /*! MSBSEL - MSBSEL
85754  *  0b0..Disable
85755  *  0b1..Enable
85756  */
85757 #define USDHC_CMD_XFR_TYP_MSBSEL(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_MSBSEL_SHIFT)) & USDHC_CMD_XFR_TYP_MSBSEL_MASK)
85758 
85759 #define USDHC_CMD_XFR_TYP_NIBBLE_POS_MASK        (0x40U)
85760 #define USDHC_CMD_XFR_TYP_NIBBLE_POS_SHIFT       (6U)
85761 /*! NIBBLE_POS - NIBBLE_POS
85762  *  0b0..Disable
85763  *  0b1..Enable
85764  */
85765 #define USDHC_CMD_XFR_TYP_NIBBLE_POS(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_NIBBLE_POS_SHIFT)) & USDHC_CMD_XFR_TYP_NIBBLE_POS_MASK)
85766 
85767 #define USDHC_CMD_XFR_TYP_AC23EN_MASK            (0x80U)
85768 #define USDHC_CMD_XFR_TYP_AC23EN_SHIFT           (7U)
85769 /*! AC23EN - AC23EN
85770  *  0b0..Disable
85771  *  0b1..Enable
85772  */
85773 #define USDHC_CMD_XFR_TYP_AC23EN(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_AC23EN_SHIFT)) & USDHC_CMD_XFR_TYP_AC23EN_MASK)
85774 
85775 #define USDHC_CMD_XFR_TYP_RSPTYP_MASK            (0x30000U)
85776 #define USDHC_CMD_XFR_TYP_RSPTYP_SHIFT           (16U)
85777 /*! RSPTYP - Response type select
85778  *  0b00..No response
85779  *  0b01..Response length 136
85780  *  0b10..Response length 48
85781  *  0b11..Response length 48, check busy after response
85782  */
85783 #define USDHC_CMD_XFR_TYP_RSPTYP(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_RSPTYP_SHIFT)) & USDHC_CMD_XFR_TYP_RSPTYP_MASK)
85784 
85785 #define USDHC_CMD_XFR_TYP_CCCEN_MASK             (0x80000U)
85786 #define USDHC_CMD_XFR_TYP_CCCEN_SHIFT            (19U)
85787 /*! CCCEN - Command CRC check enable
85788  *  0b1..Enables command CRC check
85789  *  0b0..Disables command CRC check
85790  */
85791 #define USDHC_CMD_XFR_TYP_CCCEN(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CCCEN_SHIFT)) & USDHC_CMD_XFR_TYP_CCCEN_MASK)
85792 
85793 #define USDHC_CMD_XFR_TYP_CICEN_MASK             (0x100000U)
85794 #define USDHC_CMD_XFR_TYP_CICEN_SHIFT            (20U)
85795 /*! CICEN - Command index check enable
85796  *  0b1..Enables command index check
85797  *  0b0..Disable command index check
85798  */
85799 #define USDHC_CMD_XFR_TYP_CICEN(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CICEN_SHIFT)) & USDHC_CMD_XFR_TYP_CICEN_MASK)
85800 
85801 #define USDHC_CMD_XFR_TYP_DPSEL_MASK             (0x200000U)
85802 #define USDHC_CMD_XFR_TYP_DPSEL_SHIFT            (21U)
85803 /*! DPSEL - Data present select
85804  *  0b1..Data present
85805  *  0b0..No data present
85806  */
85807 #define USDHC_CMD_XFR_TYP_DPSEL(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DPSEL_SHIFT)) & USDHC_CMD_XFR_TYP_DPSEL_MASK)
85808 
85809 #define USDHC_CMD_XFR_TYP_CMDTYP_MASK            (0xC00000U)
85810 #define USDHC_CMD_XFR_TYP_CMDTYP_SHIFT           (22U)
85811 /*! CMDTYP - Command type
85812  *  0b11..Abort CMD12, CMD52 for writing I/O Abort in CCCR
85813  *  0b10..Resume CMD52 for writing function select in CCCR
85814  *  0b01..Suspend CMD52 for writing bus suspend in CCCR
85815  *  0b00..Normal other commands
85816  */
85817 #define USDHC_CMD_XFR_TYP_CMDTYP(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDTYP_SHIFT)) & USDHC_CMD_XFR_TYP_CMDTYP_MASK)
85818 
85819 #define USDHC_CMD_XFR_TYP_CMDINX_MASK            (0x3F000000U)
85820 #define USDHC_CMD_XFR_TYP_CMDINX_SHIFT           (24U)
85821 /*! CMDINX - Command index */
85822 #define USDHC_CMD_XFR_TYP_CMDINX(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDINX_SHIFT)) & USDHC_CMD_XFR_TYP_CMDINX_MASK)
85823 /*! @} */
85824 
85825 /*! @name CMD_RSP0 - Command Response0 */
85826 /*! @{ */
85827 
85828 #define USDHC_CMD_RSP0_CMDRSP0_MASK              (0xFFFFFFFFU)
85829 #define USDHC_CMD_RSP0_CMDRSP0_SHIFT             (0U)
85830 /*! CMDRSP0 - Command response 0 */
85831 #define USDHC_CMD_RSP0_CMDRSP0(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP0_CMDRSP0_SHIFT)) & USDHC_CMD_RSP0_CMDRSP0_MASK)
85832 /*! @} */
85833 
85834 /*! @name CMD_RSP1 - Command Response1 */
85835 /*! @{ */
85836 
85837 #define USDHC_CMD_RSP1_CMDRSP1_MASK              (0xFFFFFFFFU)
85838 #define USDHC_CMD_RSP1_CMDRSP1_SHIFT             (0U)
85839 /*! CMDRSP1 - Command response 1 */
85840 #define USDHC_CMD_RSP1_CMDRSP1(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK)
85841 /*! @} */
85842 
85843 /*! @name CMD_RSP2 - Command Response2 */
85844 /*! @{ */
85845 
85846 #define USDHC_CMD_RSP2_CMDRSP2_MASK              (0xFFFFFFFFU)
85847 #define USDHC_CMD_RSP2_CMDRSP2_SHIFT             (0U)
85848 /*! CMDRSP2 - Command response 2 */
85849 #define USDHC_CMD_RSP2_CMDRSP2(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK)
85850 /*! @} */
85851 
85852 /*! @name CMD_RSP3 - Command Response3 */
85853 /*! @{ */
85854 
85855 #define USDHC_CMD_RSP3_CMDRSP3_MASK              (0xFFFFFFFFU)
85856 #define USDHC_CMD_RSP3_CMDRSP3_SHIFT             (0U)
85857 /*! CMDRSP3 - Command response 3 */
85858 #define USDHC_CMD_RSP3_CMDRSP3(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP3_CMDRSP3_SHIFT)) & USDHC_CMD_RSP3_CMDRSP3_MASK)
85859 /*! @} */
85860 
85861 /*! @name DATA_BUFF_ACC_PORT - Data Buffer Access Port */
85862 /*! @{ */
85863 
85864 #define USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK    (0xFFFFFFFFU)
85865 #define USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT   (0U)
85866 /*! DATCONT - Data content */
85867 #define USDHC_DATA_BUFF_ACC_PORT_DATCONT(x)      (((uint32_t)(((uint32_t)(x)) << USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT)) & USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK)
85868 /*! @} */
85869 
85870 /*! @name PRES_STATE - Present State */
85871 /*! @{ */
85872 
85873 #define USDHC_PRES_STATE_CIHB_MASK               (0x1U)
85874 #define USDHC_PRES_STATE_CIHB_SHIFT              (0U)
85875 /*! CIHB - Command inhibit (CMD)
85876  *  0b1..Cannot issue command
85877  *  0b0..Can issue command using only CMD line
85878  */
85879 #define USDHC_PRES_STATE_CIHB(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CIHB_SHIFT)) & USDHC_PRES_STATE_CIHB_MASK)
85880 
85881 #define USDHC_PRES_STATE_CDIHB_MASK              (0x2U)
85882 #define USDHC_PRES_STATE_CDIHB_SHIFT             (1U)
85883 /*! CDIHB - Command Inhibit Data (DATA)
85884  *  0b1..Cannot issue command that uses the DATA line
85885  *  0b0..Can issue command that uses the DATA line
85886  */
85887 #define USDHC_PRES_STATE_CDIHB(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDIHB_SHIFT)) & USDHC_PRES_STATE_CDIHB_MASK)
85888 
85889 #define USDHC_PRES_STATE_DLA_MASK                (0x4U)
85890 #define USDHC_PRES_STATE_DLA_SHIFT               (2U)
85891 /*! DLA - Data line active
85892  *  0b1..DATA line active
85893  *  0b0..DATA line inactive
85894  */
85895 #define USDHC_PRES_STATE_DLA(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLA_SHIFT)) & USDHC_PRES_STATE_DLA_MASK)
85896 
85897 #define USDHC_PRES_STATE_SDSTB_MASK              (0x8U)
85898 #define USDHC_PRES_STATE_SDSTB_SHIFT             (3U)
85899 /*! SDSTB - SD clock stable
85900  *  0b1..Clock is stable.
85901  *  0b0..Clock is changing frequency and not stable.
85902  */
85903 #define USDHC_PRES_STATE_SDSTB(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDSTB_SHIFT)) & USDHC_PRES_STATE_SDSTB_MASK)
85904 
85905 #define USDHC_PRES_STATE_WTA_MASK                (0x100U)
85906 #define USDHC_PRES_STATE_WTA_SHIFT               (8U)
85907 /*! WTA - Write transfer active
85908  *  0b1..Transferring data
85909  *  0b0..No valid data
85910  */
85911 #define USDHC_PRES_STATE_WTA(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WTA_SHIFT)) & USDHC_PRES_STATE_WTA_MASK)
85912 
85913 #define USDHC_PRES_STATE_RTA_MASK                (0x200U)
85914 #define USDHC_PRES_STATE_RTA_SHIFT               (9U)
85915 /*! RTA - Read transfer active
85916  *  0b1..Transferring data
85917  *  0b0..No valid data
85918  */
85919 #define USDHC_PRES_STATE_RTA(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTA_SHIFT)) & USDHC_PRES_STATE_RTA_MASK)
85920 
85921 #define USDHC_PRES_STATE_BWEN_MASK               (0x400U)
85922 #define USDHC_PRES_STATE_BWEN_SHIFT              (10U)
85923 /*! BWEN - Buffer write enable
85924  *  0b1..Write enable
85925  *  0b0..Write disable
85926  */
85927 #define USDHC_PRES_STATE_BWEN(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BWEN_SHIFT)) & USDHC_PRES_STATE_BWEN_MASK)
85928 
85929 #define USDHC_PRES_STATE_BREN_MASK               (0x800U)
85930 #define USDHC_PRES_STATE_BREN_SHIFT              (11U)
85931 /*! BREN - Buffer read enable
85932  *  0b1..Read enable
85933  *  0b0..Read disable
85934  */
85935 #define USDHC_PRES_STATE_BREN(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BREN_SHIFT)) & USDHC_PRES_STATE_BREN_MASK)
85936 
85937 #define USDHC_PRES_STATE_RTR_MASK                (0x1000U)
85938 #define USDHC_PRES_STATE_RTR_SHIFT               (12U)
85939 /*! RTR - Re-Tuning Request (only for SD3.0 SDR104 mode)
85940  *  0b1..Sampling clock needs re-tuning
85941  *  0b0..Fixed or well tuned sampling clock
85942  */
85943 #define USDHC_PRES_STATE_RTR(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTR_SHIFT)) & USDHC_PRES_STATE_RTR_MASK)
85944 
85945 #define USDHC_PRES_STATE_TSCD_MASK               (0x8000U)
85946 #define USDHC_PRES_STATE_TSCD_SHIFT              (15U)
85947 /*! TSCD - Tap select change done
85948  *  0b1..Delay cell select change is finished.
85949  *  0b0..Delay cell select change is not finished.
85950  */
85951 #define USDHC_PRES_STATE_TSCD(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_TSCD_SHIFT)) & USDHC_PRES_STATE_TSCD_MASK)
85952 
85953 #define USDHC_PRES_STATE_CINST_MASK              (0x10000U)
85954 #define USDHC_PRES_STATE_CINST_SHIFT             (16U)
85955 /*! CINST - Card inserted
85956  *  0b1..Card inserted
85957  *  0b0..Power on reset or no card
85958  */
85959 #define USDHC_PRES_STATE_CINST(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CINST_SHIFT)) & USDHC_PRES_STATE_CINST_MASK)
85960 
85961 #define USDHC_PRES_STATE_CLSL_MASK               (0x800000U)
85962 #define USDHC_PRES_STATE_CLSL_SHIFT              (23U)
85963 /*! CLSL - CMD line signal level */
85964 #define USDHC_PRES_STATE_CLSL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CLSL_SHIFT)) & USDHC_PRES_STATE_CLSL_MASK)
85965 
85966 #define USDHC_PRES_STATE_DLSL_MASK               (0xFF000000U)
85967 #define USDHC_PRES_STATE_DLSL_SHIFT              (24U)
85968 /*! DLSL - DATA[7:0] line signal level
85969  *  0b10000000..Data 7 line signal level
85970  *  0b01000000..Data 6 line signal level
85971  *  0b00100000..Data 5 line signal level
85972  *  0b00010000..Data 4 line signal level
85973  *  0b00001000..Data 3 line signal level
85974  *  0b00000100..Data 2 line signal level
85975  *  0b00000010..Data 1 line signal level
85976  *  0b00000001..Data 0 line signal level
85977  */
85978 #define USDHC_PRES_STATE_DLSL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLSL_SHIFT)) & USDHC_PRES_STATE_DLSL_MASK)
85979 /*! @} */
85980 
85981 /*! @name PROT_CTRL - Protocol Control */
85982 /*! @{ */
85983 
85984 #define USDHC_PROT_CTRL_DTW_MASK                 (0x6U)
85985 #define USDHC_PROT_CTRL_DTW_SHIFT                (1U)
85986 /*! DTW - Data transfer width
85987  *  0b10..8-bit mode
85988  *  0b01..4-bit mode
85989  *  0b00..1-bit mode
85990  *  0b11..Reserved
85991  */
85992 #define USDHC_PROT_CTRL_DTW(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DTW_SHIFT)) & USDHC_PROT_CTRL_DTW_MASK)
85993 
85994 #define USDHC_PROT_CTRL_D3CD_MASK                (0x8U)
85995 #define USDHC_PROT_CTRL_D3CD_SHIFT               (3U)
85996 /*! D3CD - DATA3 as card detection pin
85997  *  0b1..DATA3 as card detection pin
85998  *  0b0..DATA3 does not monitor card insertion
85999  */
86000 #define USDHC_PROT_CTRL_D3CD(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_D3CD_SHIFT)) & USDHC_PROT_CTRL_D3CD_MASK)
86001 
86002 #define USDHC_PROT_CTRL_EMODE_MASK               (0x30U)
86003 #define USDHC_PROT_CTRL_EMODE_SHIFT              (4U)
86004 /*! EMODE - Endian mode
86005  *  0b00..Big endian mode
86006  *  0b01..Half word big endian mode
86007  *  0b10..Little endian mode
86008  *  0b11..Reserved
86009  */
86010 #define USDHC_PROT_CTRL_EMODE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_EMODE_SHIFT)) & USDHC_PROT_CTRL_EMODE_MASK)
86011 
86012 #define USDHC_PROT_CTRL_DMASEL_MASK              (0x300U)
86013 #define USDHC_PROT_CTRL_DMASEL_SHIFT             (8U)
86014 /*! DMASEL - DMA select
86015  *  0b00..No DMA or simple DMA is selected.
86016  *  0b01..ADMA1 is selected.
86017  *  0b10..ADMA2 is selected.
86018  *  0b11..Reserved
86019  */
86020 #define USDHC_PROT_CTRL_DMASEL(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DMASEL_SHIFT)) & USDHC_PROT_CTRL_DMASEL_MASK)
86021 
86022 #define USDHC_PROT_CTRL_SABGREQ_MASK             (0x10000U)
86023 #define USDHC_PROT_CTRL_SABGREQ_SHIFT            (16U)
86024 /*! SABGREQ - Stop at block gap request
86025  *  0b1..Stop
86026  *  0b0..Transfer
86027  */
86028 #define USDHC_PROT_CTRL_SABGREQ(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_SABGREQ_SHIFT)) & USDHC_PROT_CTRL_SABGREQ_MASK)
86029 
86030 #define USDHC_PROT_CTRL_CREQ_MASK                (0x20000U)
86031 #define USDHC_PROT_CTRL_CREQ_SHIFT               (17U)
86032 /*! CREQ - Continue request
86033  *  0b1..Restart
86034  *  0b0..No effect
86035  */
86036 #define USDHC_PROT_CTRL_CREQ(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CREQ_SHIFT)) & USDHC_PROT_CTRL_CREQ_MASK)
86037 
86038 #define USDHC_PROT_CTRL_RWCTL_MASK               (0x40000U)
86039 #define USDHC_PROT_CTRL_RWCTL_SHIFT              (18U)
86040 /*! RWCTL - Read wait control
86041  *  0b1..Enables read wait control and assert read wait without stopping SD clock at block gap when SABGREQ field is set
86042  *  0b0..Disables read wait control and stop SD clock at block gap when SABGREQ field is set
86043  */
86044 #define USDHC_PROT_CTRL_RWCTL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RWCTL_SHIFT)) & USDHC_PROT_CTRL_RWCTL_MASK)
86045 
86046 #define USDHC_PROT_CTRL_IABG_MASK                (0x80000U)
86047 #define USDHC_PROT_CTRL_IABG_SHIFT               (19U)
86048 /*! IABG - Interrupt at block gap
86049  *  0b1..Enables interrupt at block gap
86050  *  0b0..Disables interrupt at block gap
86051  */
86052 #define USDHC_PROT_CTRL_IABG(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_IABG_SHIFT)) & USDHC_PROT_CTRL_IABG_MASK)
86053 
86054 #define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK     (0x100000U)
86055 #define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT    (20U)
86056 /*! RD_DONE_NO_8CLK - Read performed number 8 clock */
86057 #define USDHC_PROT_CTRL_RD_DONE_NO_8CLK(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT)) & USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK)
86058 
86059 #define USDHC_PROT_CTRL_WECINT_MASK              (0x1000000U)
86060 #define USDHC_PROT_CTRL_WECINT_SHIFT             (24U)
86061 /*! WECINT - Wakeup event enable on card interrupt
86062  *  0b1..Enables wakeup event enable on card interrupt
86063  *  0b0..Disables wakeup event enable on card interrupt
86064  */
86065 #define USDHC_PROT_CTRL_WECINT(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINT_SHIFT)) & USDHC_PROT_CTRL_WECINT_MASK)
86066 
86067 #define USDHC_PROT_CTRL_WECINS_MASK              (0x2000000U)
86068 #define USDHC_PROT_CTRL_WECINS_SHIFT             (25U)
86069 /*! WECINS - Wakeup event enable on SD card insertion
86070  *  0b1..Enable wakeup event enable on SD card insertion
86071  *  0b0..Disable wakeup event enable on SD card insertion
86072  */
86073 #define USDHC_PROT_CTRL_WECINS(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINS_SHIFT)) & USDHC_PROT_CTRL_WECINS_MASK)
86074 
86075 #define USDHC_PROT_CTRL_WECRM_MASK               (0x4000000U)
86076 #define USDHC_PROT_CTRL_WECRM_SHIFT              (26U)
86077 /*! WECRM - Wakeup event enable on SD card removal
86078  *  0b1..Enables wakeup event enable on SD card removal
86079  *  0b0..Disables wakeup event enable on SD card removal
86080  */
86081 #define USDHC_PROT_CTRL_WECRM(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECRM_SHIFT)) & USDHC_PROT_CTRL_WECRM_MASK)
86082 
86083 #define USDHC_PROT_CTRL_BURST_LEN_EN_MASK        (0x38000000U)
86084 #define USDHC_PROT_CTRL_BURST_LEN_EN_SHIFT       (27U)
86085 /*! BURST_LEN_EN - BURST length enable for INCR, INCR4 / INCR8 / INCR16, INCR4-WRAP / INCR8-WRAP / INCR16-WRAP
86086  *  0bxx1..Burst length is enabled for INCR.
86087  *  0bx1x..Burst length is enabled for INCR4 / INCR8 / INCR16.
86088  *  0b1xx..Burst length is enabled for INCR4-WRAP / INCR8-WRAP / INCR16-WRAP.
86089  */
86090 #define USDHC_PROT_CTRL_BURST_LEN_EN(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_BURST_LEN_EN_SHIFT)) & USDHC_PROT_CTRL_BURST_LEN_EN_MASK)
86091 
86092 #define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK    (0x40000000U)
86093 #define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT   (30U)
86094 /*! NON_EXACT_BLK_RD - Non-exact block read
86095  *  0b1..The block read is non-exact block read. Host driver needs to issue abort command to terminate this multi-block read.
86096  *  0b0..The block read is exact block read. Host driver does not need to issue abort command to terminate this multi-block read.
86097  */
86098 #define USDHC_PROT_CTRL_NON_EXACT_BLK_RD(x)      (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT)) & USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK)
86099 /*! @} */
86100 
86101 /*! @name SYS_CTRL - System Control */
86102 /*! @{ */
86103 
86104 #define USDHC_SYS_CTRL_DVS_MASK                  (0xF0U)
86105 #define USDHC_SYS_CTRL_DVS_SHIFT                 (4U)
86106 /*! DVS - Divisor
86107  *  0b0000..Divide-by-1
86108  *  0b0001..Divide-by-2
86109  *  0b1110..Divide-by-15
86110  *  0b1111..Divide-by-16
86111  */
86112 #define USDHC_SYS_CTRL_DVS(x)                    (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DVS_SHIFT)) & USDHC_SYS_CTRL_DVS_MASK)
86113 
86114 #define USDHC_SYS_CTRL_SDCLKFS_MASK              (0xFF00U)
86115 #define USDHC_SYS_CTRL_SDCLKFS_SHIFT             (8U)
86116 /*! SDCLKFS - SDCLK frequency select */
86117 #define USDHC_SYS_CTRL_SDCLKFS(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_SDCLKFS_SHIFT)) & USDHC_SYS_CTRL_SDCLKFS_MASK)
86118 
86119 #define USDHC_SYS_CTRL_DTOCV_MASK                (0xF0000U)
86120 #define USDHC_SYS_CTRL_DTOCV_SHIFT               (16U)
86121 /*! DTOCV - Data timeout counter value
86122  *  0b1110..SDCLK x 2 30, recommend to use for SDR104 mode
86123  *  0b1101..SDCLK x 2 29, recommend to use for supported speed modes except SDR104 mode
86124  *  0b0011..SDCLK x 2 19
86125  *  0b0010..SDCLK x 2 18
86126  *  0b0001..SDCLK x 2 33
86127  *  0b0000..SDCLK x 2 32
86128  */
86129 #define USDHC_SYS_CTRL_DTOCV(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DTOCV_SHIFT)) & USDHC_SYS_CTRL_DTOCV_MASK)
86130 
86131 #define USDHC_SYS_CTRL_RST_FIFO_MASK             (0x400000U)
86132 #define USDHC_SYS_CTRL_RST_FIFO_SHIFT            (22U)
86133 /*! RST_FIFO - Reset the async FIFO */
86134 #define USDHC_SYS_CTRL_RST_FIFO(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RST_FIFO_SHIFT)) & USDHC_SYS_CTRL_RST_FIFO_MASK)
86135 
86136 #define USDHC_SYS_CTRL_IPP_RST_N_MASK            (0x800000U)
86137 #define USDHC_SYS_CTRL_IPP_RST_N_SHIFT           (23U)
86138 /*! IPP_RST_N - Hardware reset */
86139 #define USDHC_SYS_CTRL_IPP_RST_N(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_IPP_RST_N_SHIFT)) & USDHC_SYS_CTRL_IPP_RST_N_MASK)
86140 
86141 #define USDHC_SYS_CTRL_RSTA_MASK                 (0x1000000U)
86142 #define USDHC_SYS_CTRL_RSTA_SHIFT                (24U)
86143 /*! RSTA - Software reset for all
86144  *  0b1..Reset
86145  *  0b0..No reset
86146  */
86147 #define USDHC_SYS_CTRL_RSTA(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTA_SHIFT)) & USDHC_SYS_CTRL_RSTA_MASK)
86148 
86149 #define USDHC_SYS_CTRL_RSTC_MASK                 (0x2000000U)
86150 #define USDHC_SYS_CTRL_RSTC_SHIFT                (25U)
86151 /*! RSTC - Software reset for CMD line
86152  *  0b1..Reset
86153  *  0b0..No reset
86154  */
86155 #define USDHC_SYS_CTRL_RSTC(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTC_SHIFT)) & USDHC_SYS_CTRL_RSTC_MASK)
86156 
86157 #define USDHC_SYS_CTRL_RSTD_MASK                 (0x4000000U)
86158 #define USDHC_SYS_CTRL_RSTD_SHIFT                (26U)
86159 /*! RSTD - Software reset for data line
86160  *  0b1..Reset
86161  *  0b0..No reset
86162  */
86163 #define USDHC_SYS_CTRL_RSTD(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTD_SHIFT)) & USDHC_SYS_CTRL_RSTD_MASK)
86164 
86165 #define USDHC_SYS_CTRL_INITA_MASK                (0x8000000U)
86166 #define USDHC_SYS_CTRL_INITA_SHIFT               (27U)
86167 /*! INITA - Initialization active */
86168 #define USDHC_SYS_CTRL_INITA(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_INITA_SHIFT)) & USDHC_SYS_CTRL_INITA_MASK)
86169 
86170 #define USDHC_SYS_CTRL_RSTT_MASK                 (0x10000000U)
86171 #define USDHC_SYS_CTRL_RSTT_SHIFT                (28U)
86172 /*! RSTT - Reset tuning */
86173 #define USDHC_SYS_CTRL_RSTT(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTT_SHIFT)) & USDHC_SYS_CTRL_RSTT_MASK)
86174 /*! @} */
86175 
86176 /*! @name INT_STATUS - Interrupt Status */
86177 /*! @{ */
86178 
86179 #define USDHC_INT_STATUS_CC_MASK                 (0x1U)
86180 #define USDHC_INT_STATUS_CC_SHIFT                (0U)
86181 /*! CC - Command complete
86182  *  0b1..Command complete
86183  *  0b0..Command not complete
86184  */
86185 #define USDHC_INT_STATUS_CC(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CC_SHIFT)) & USDHC_INT_STATUS_CC_MASK)
86186 
86187 #define USDHC_INT_STATUS_TC_MASK                 (0x2U)
86188 #define USDHC_INT_STATUS_TC_SHIFT                (1U)
86189 /*! TC - Transfer complete
86190  *  0b1..Transfer complete
86191  *  0b0..Transfer does not complete
86192  */
86193 #define USDHC_INT_STATUS_TC(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TC_SHIFT)) & USDHC_INT_STATUS_TC_MASK)
86194 
86195 #define USDHC_INT_STATUS_BGE_MASK                (0x4U)
86196 #define USDHC_INT_STATUS_BGE_SHIFT               (2U)
86197 /*! BGE - Block gap event
86198  *  0b1..Transaction stopped at block gap
86199  *  0b0..No block gap event
86200  */
86201 #define USDHC_INT_STATUS_BGE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BGE_SHIFT)) & USDHC_INT_STATUS_BGE_MASK)
86202 
86203 #define USDHC_INT_STATUS_DINT_MASK               (0x8U)
86204 #define USDHC_INT_STATUS_DINT_SHIFT              (3U)
86205 /*! DINT - DMA interrupt
86206  *  0b1..DMA interrupt is generated.
86207  *  0b0..No DMA interrupt
86208  */
86209 #define USDHC_INT_STATUS_DINT(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DINT_SHIFT)) & USDHC_INT_STATUS_DINT_MASK)
86210 
86211 #define USDHC_INT_STATUS_BWR_MASK                (0x10U)
86212 #define USDHC_INT_STATUS_BWR_SHIFT               (4U)
86213 /*! BWR - Buffer write ready
86214  *  0b1..Ready to write buffer
86215  *  0b0..Not ready to write buffer
86216  */
86217 #define USDHC_INT_STATUS_BWR(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BWR_SHIFT)) & USDHC_INT_STATUS_BWR_MASK)
86218 
86219 #define USDHC_INT_STATUS_BRR_MASK                (0x20U)
86220 #define USDHC_INT_STATUS_BRR_SHIFT               (5U)
86221 /*! BRR - Buffer read ready
86222  *  0b1..Ready to read buffer
86223  *  0b0..Not ready to read buffer
86224  */
86225 #define USDHC_INT_STATUS_BRR(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BRR_SHIFT)) & USDHC_INT_STATUS_BRR_MASK)
86226 
86227 #define USDHC_INT_STATUS_CINS_MASK               (0x40U)
86228 #define USDHC_INT_STATUS_CINS_SHIFT              (6U)
86229 /*! CINS - Card insertion
86230  *  0b1..Card inserted
86231  *  0b0..Card state unstable or removed
86232  */
86233 #define USDHC_INT_STATUS_CINS(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINS_SHIFT)) & USDHC_INT_STATUS_CINS_MASK)
86234 
86235 #define USDHC_INT_STATUS_CRM_MASK                (0x80U)
86236 #define USDHC_INT_STATUS_CRM_SHIFT               (7U)
86237 /*! CRM - Card removal
86238  *  0b1..Card removed
86239  *  0b0..Card state unstable or inserted
86240  */
86241 #define USDHC_INT_STATUS_CRM(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CRM_SHIFT)) & USDHC_INT_STATUS_CRM_MASK)
86242 
86243 #define USDHC_INT_STATUS_CINT_MASK               (0x100U)
86244 #define USDHC_INT_STATUS_CINT_SHIFT              (8U)
86245 /*! CINT - Card interrupt
86246  *  0b1..Generate card interrupt
86247  *  0b0..No card interrupt
86248  */
86249 #define USDHC_INT_STATUS_CINT(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINT_SHIFT)) & USDHC_INT_STATUS_CINT_MASK)
86250 
86251 #define USDHC_INT_STATUS_RTE_MASK                (0x1000U)
86252 #define USDHC_INT_STATUS_RTE_SHIFT               (12U)
86253 /*! RTE - Re-tuning event: (only for SD3.0 SDR104 mode)
86254  *  0b1..Re-tuning should be performed.
86255  *  0b0..Re-tuning is not required.
86256  */
86257 #define USDHC_INT_STATUS_RTE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_RTE_SHIFT)) & USDHC_INT_STATUS_RTE_MASK)
86258 
86259 #define USDHC_INT_STATUS_TP_MASK                 (0x4000U)
86260 #define USDHC_INT_STATUS_TP_SHIFT                (14U)
86261 /*! TP - Tuning pass:(only for SD3.0 SDR104 mode) */
86262 #define USDHC_INT_STATUS_TP(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TP_SHIFT)) & USDHC_INT_STATUS_TP_MASK)
86263 
86264 #define USDHC_INT_STATUS_ERR_INT_STATUS_MASK     (0x8000U)
86265 #define USDHC_INT_STATUS_ERR_INT_STATUS_SHIFT    (15U)
86266 /*! ERR_INT_STATUS - Error Interrupt Status */
86267 #define USDHC_INT_STATUS_ERR_INT_STATUS(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_ERR_INT_STATUS_SHIFT)) & USDHC_INT_STATUS_ERR_INT_STATUS_MASK)
86268 
86269 #define USDHC_INT_STATUS_CTOE_MASK               (0x10000U)
86270 #define USDHC_INT_STATUS_CTOE_SHIFT              (16U)
86271 /*! CTOE - Command timeout error
86272  *  0b1..Time out
86273  *  0b0..No error
86274  */
86275 #define USDHC_INT_STATUS_CTOE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CTOE_SHIFT)) & USDHC_INT_STATUS_CTOE_MASK)
86276 
86277 #define USDHC_INT_STATUS_CCE_MASK                (0x20000U)
86278 #define USDHC_INT_STATUS_CCE_SHIFT               (17U)
86279 /*! CCE - Command CRC error
86280  *  0b1..CRC error generated
86281  *  0b0..No error
86282  */
86283 #define USDHC_INT_STATUS_CCE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CCE_SHIFT)) & USDHC_INT_STATUS_CCE_MASK)
86284 
86285 #define USDHC_INT_STATUS_CEBE_MASK               (0x40000U)
86286 #define USDHC_INT_STATUS_CEBE_SHIFT              (18U)
86287 /*! CEBE - Command end bit error
86288  *  0b1..End bit error generated
86289  *  0b0..No error
86290  */
86291 #define USDHC_INT_STATUS_CEBE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CEBE_SHIFT)) & USDHC_INT_STATUS_CEBE_MASK)
86292 
86293 #define USDHC_INT_STATUS_CIE_MASK                (0x80000U)
86294 #define USDHC_INT_STATUS_CIE_SHIFT               (19U)
86295 /*! CIE - Command index error
86296  *  0b1..Error
86297  *  0b0..No error
86298  */
86299 #define USDHC_INT_STATUS_CIE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CIE_SHIFT)) & USDHC_INT_STATUS_CIE_MASK)
86300 
86301 #define USDHC_INT_STATUS_DTOE_MASK               (0x100000U)
86302 #define USDHC_INT_STATUS_DTOE_SHIFT              (20U)
86303 /*! DTOE - Data timeout error
86304  *  0b1..Time out
86305  *  0b0..No error
86306  */
86307 #define USDHC_INT_STATUS_DTOE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DTOE_SHIFT)) & USDHC_INT_STATUS_DTOE_MASK)
86308 
86309 #define USDHC_INT_STATUS_DCE_MASK                (0x200000U)
86310 #define USDHC_INT_STATUS_DCE_SHIFT               (21U)
86311 /*! DCE - Data CRC error
86312  *  0b1..Error
86313  *  0b0..No error
86314  */
86315 #define USDHC_INT_STATUS_DCE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DCE_SHIFT)) & USDHC_INT_STATUS_DCE_MASK)
86316 
86317 #define USDHC_INT_STATUS_DEBE_MASK               (0x400000U)
86318 #define USDHC_INT_STATUS_DEBE_SHIFT              (22U)
86319 /*! DEBE - Data end bit error
86320  *  0b1..Error
86321  *  0b0..No error
86322  */
86323 #define USDHC_INT_STATUS_DEBE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DEBE_SHIFT)) & USDHC_INT_STATUS_DEBE_MASK)
86324 
86325 #define USDHC_INT_STATUS_AC12E_MASK              (0x1000000U)
86326 #define USDHC_INT_STATUS_AC12E_SHIFT             (24U)
86327 /*! AC12E - Auto CMD12 error
86328  *  0b1..Error
86329  *  0b0..No error
86330  */
86331 #define USDHC_INT_STATUS_AC12E(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_AC12E_SHIFT)) & USDHC_INT_STATUS_AC12E_MASK)
86332 
86333 #define USDHC_INT_STATUS_TNE_MASK                (0x4000000U)
86334 #define USDHC_INT_STATUS_TNE_SHIFT               (26U)
86335 /*! TNE - Tuning error: (only for SD3.0 SDR104 mode) */
86336 #define USDHC_INT_STATUS_TNE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TNE_SHIFT)) & USDHC_INT_STATUS_TNE_MASK)
86337 
86338 #define USDHC_INT_STATUS_DMAE_MASK               (0x10000000U)
86339 #define USDHC_INT_STATUS_DMAE_SHIFT              (28U)
86340 /*! DMAE - DMA error
86341  *  0b1..Error
86342  *  0b0..No error
86343  */
86344 #define USDHC_INT_STATUS_DMAE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DMAE_SHIFT)) & USDHC_INT_STATUS_DMAE_MASK)
86345 /*! @} */
86346 
86347 /*! @name INT_STATUS_EN - Interrupt Status Enable */
86348 /*! @{ */
86349 
86350 #define USDHC_INT_STATUS_EN_CCSEN_MASK           (0x1U)
86351 #define USDHC_INT_STATUS_EN_CCSEN_SHIFT          (0U)
86352 /*! CCSEN - Command complete status enable
86353  *  0b1..Enabled
86354  *  0b0..Masked
86355  */
86356 #define USDHC_INT_STATUS_EN_CCSEN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCSEN_SHIFT)) & USDHC_INT_STATUS_EN_CCSEN_MASK)
86357 
86358 #define USDHC_INT_STATUS_EN_TCSEN_MASK           (0x2U)
86359 #define USDHC_INT_STATUS_EN_TCSEN_SHIFT          (1U)
86360 /*! TCSEN - Transfer complete status enable
86361  *  0b1..Enabled
86362  *  0b0..Masked
86363  */
86364 #define USDHC_INT_STATUS_EN_TCSEN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TCSEN_SHIFT)) & USDHC_INT_STATUS_EN_TCSEN_MASK)
86365 
86366 #define USDHC_INT_STATUS_EN_BGESEN_MASK          (0x4U)
86367 #define USDHC_INT_STATUS_EN_BGESEN_SHIFT         (2U)
86368 /*! BGESEN - Block gap event status enable
86369  *  0b1..Enabled
86370  *  0b0..Masked
86371  */
86372 #define USDHC_INT_STATUS_EN_BGESEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BGESEN_SHIFT)) & USDHC_INT_STATUS_EN_BGESEN_MASK)
86373 
86374 #define USDHC_INT_STATUS_EN_DINTSEN_MASK         (0x8U)
86375 #define USDHC_INT_STATUS_EN_DINTSEN_SHIFT        (3U)
86376 /*! DINTSEN - DMA interrupt status enable
86377  *  0b1..Enabled
86378  *  0b0..Masked
86379  */
86380 #define USDHC_INT_STATUS_EN_DINTSEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_DINTSEN_MASK)
86381 
86382 #define USDHC_INT_STATUS_EN_BWRSEN_MASK          (0x10U)
86383 #define USDHC_INT_STATUS_EN_BWRSEN_SHIFT         (4U)
86384 /*! BWRSEN - Buffer write ready status enable
86385  *  0b1..Enabled
86386  *  0b0..Masked
86387  */
86388 #define USDHC_INT_STATUS_EN_BWRSEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BWRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BWRSEN_MASK)
86389 
86390 #define USDHC_INT_STATUS_EN_BRRSEN_MASK          (0x20U)
86391 #define USDHC_INT_STATUS_EN_BRRSEN_SHIFT         (5U)
86392 /*! BRRSEN - Buffer read ready status enable
86393  *  0b1..Enabled
86394  *  0b0..Masked
86395  */
86396 #define USDHC_INT_STATUS_EN_BRRSEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BRRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BRRSEN_MASK)
86397 
86398 #define USDHC_INT_STATUS_EN_CINSSEN_MASK         (0x40U)
86399 #define USDHC_INT_STATUS_EN_CINSSEN_SHIFT        (6U)
86400 /*! CINSSEN - Card insertion status enable
86401  *  0b1..Enabled
86402  *  0b0..Masked
86403  */
86404 #define USDHC_INT_STATUS_EN_CINSSEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINSSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINSSEN_MASK)
86405 
86406 #define USDHC_INT_STATUS_EN_CRMSEN_MASK          (0x80U)
86407 #define USDHC_INT_STATUS_EN_CRMSEN_SHIFT         (7U)
86408 /*! CRMSEN - Card removal status enable
86409  *  0b1..Enabled
86410  *  0b0..Masked
86411  */
86412 #define USDHC_INT_STATUS_EN_CRMSEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CRMSEN_SHIFT)) & USDHC_INT_STATUS_EN_CRMSEN_MASK)
86413 
86414 #define USDHC_INT_STATUS_EN_CINTSEN_MASK         (0x100U)
86415 #define USDHC_INT_STATUS_EN_CINTSEN_SHIFT        (8U)
86416 /*! CINTSEN - Card interrupt status enable
86417  *  0b1..Enabled
86418  *  0b0..Masked
86419  */
86420 #define USDHC_INT_STATUS_EN_CINTSEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINTSEN_MASK)
86421 
86422 #define USDHC_INT_STATUS_EN_RTESEN_MASK          (0x1000U)
86423 #define USDHC_INT_STATUS_EN_RTESEN_SHIFT         (12U)
86424 /*! RTESEN - Re-tuning event status enable
86425  *  0b1..Enabled
86426  *  0b0..Masked
86427  */
86428 #define USDHC_INT_STATUS_EN_RTESEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_RTESEN_SHIFT)) & USDHC_INT_STATUS_EN_RTESEN_MASK)
86429 
86430 #define USDHC_INT_STATUS_EN_TPSEN_MASK           (0x4000U)
86431 #define USDHC_INT_STATUS_EN_TPSEN_SHIFT          (14U)
86432 /*! TPSEN - Tuning pass status enable
86433  *  0b1..Enabled
86434  *  0b0..Masked
86435  */
86436 #define USDHC_INT_STATUS_EN_TPSEN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TPSEN_SHIFT)) & USDHC_INT_STATUS_EN_TPSEN_MASK)
86437 
86438 #define USDHC_INT_STATUS_EN_CTOESEN_MASK         (0x10000U)
86439 #define USDHC_INT_STATUS_EN_CTOESEN_SHIFT        (16U)
86440 /*! CTOESEN - Command timeout error status enable
86441  *  0b1..Enabled
86442  *  0b0..Masked
86443  */
86444 #define USDHC_INT_STATUS_EN_CTOESEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_CTOESEN_MASK)
86445 
86446 #define USDHC_INT_STATUS_EN_CCESEN_MASK          (0x20000U)
86447 #define USDHC_INT_STATUS_EN_CCESEN_SHIFT         (17U)
86448 /*! CCESEN - Command CRC error status enable
86449  *  0b1..Enabled
86450  *  0b0..Masked
86451  */
86452 #define USDHC_INT_STATUS_EN_CCESEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCESEN_SHIFT)) & USDHC_INT_STATUS_EN_CCESEN_MASK)
86453 
86454 #define USDHC_INT_STATUS_EN_CEBESEN_MASK         (0x40000U)
86455 #define USDHC_INT_STATUS_EN_CEBESEN_SHIFT        (18U)
86456 /*! CEBESEN - Command end bit error status enable
86457  *  0b1..Enabled
86458  *  0b0..Masked
86459  */
86460 #define USDHC_INT_STATUS_EN_CEBESEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_CEBESEN_MASK)
86461 
86462 #define USDHC_INT_STATUS_EN_CIESEN_MASK          (0x80000U)
86463 #define USDHC_INT_STATUS_EN_CIESEN_SHIFT         (19U)
86464 /*! CIESEN - Command index error status enable
86465  *  0b1..Enabled
86466  *  0b0..Masked
86467  */
86468 #define USDHC_INT_STATUS_EN_CIESEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CIESEN_SHIFT)) & USDHC_INT_STATUS_EN_CIESEN_MASK)
86469 
86470 #define USDHC_INT_STATUS_EN_DTOESEN_MASK         (0x100000U)
86471 #define USDHC_INT_STATUS_EN_DTOESEN_SHIFT        (20U)
86472 /*! DTOESEN - Data timeout error status enable
86473  *  0b1..Enabled
86474  *  0b0..Masked
86475  */
86476 #define USDHC_INT_STATUS_EN_DTOESEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_DTOESEN_MASK)
86477 
86478 #define USDHC_INT_STATUS_EN_DCESEN_MASK          (0x200000U)
86479 #define USDHC_INT_STATUS_EN_DCESEN_SHIFT         (21U)
86480 /*! DCESEN - Data CRC error status enable
86481  *  0b1..Enabled
86482  *  0b0..Masked
86483  */
86484 #define USDHC_INT_STATUS_EN_DCESEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DCESEN_SHIFT)) & USDHC_INT_STATUS_EN_DCESEN_MASK)
86485 
86486 #define USDHC_INT_STATUS_EN_DEBESEN_MASK         (0x400000U)
86487 #define USDHC_INT_STATUS_EN_DEBESEN_SHIFT        (22U)
86488 /*! DEBESEN - Data end bit error status enable
86489  *  0b1..Enabled
86490  *  0b0..Masked
86491  */
86492 #define USDHC_INT_STATUS_EN_DEBESEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_DEBESEN_MASK)
86493 
86494 #define USDHC_INT_STATUS_EN_AC12ESEN_MASK        (0x1000000U)
86495 #define USDHC_INT_STATUS_EN_AC12ESEN_SHIFT       (24U)
86496 /*! AC12ESEN - Auto CMD12 error status enable
86497  *  0b1..Enabled
86498  *  0b0..Masked
86499  */
86500 #define USDHC_INT_STATUS_EN_AC12ESEN(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_AC12ESEN_SHIFT)) & USDHC_INT_STATUS_EN_AC12ESEN_MASK)
86501 
86502 #define USDHC_INT_STATUS_EN_TNESEN_MASK          (0x4000000U)
86503 #define USDHC_INT_STATUS_EN_TNESEN_SHIFT         (26U)
86504 /*! TNESEN - Tuning error status enable
86505  *  0b1..Enabled
86506  *  0b0..Masked
86507  */
86508 #define USDHC_INT_STATUS_EN_TNESEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TNESEN_SHIFT)) & USDHC_INT_STATUS_EN_TNESEN_MASK)
86509 
86510 #define USDHC_INT_STATUS_EN_DMAESEN_MASK         (0x10000000U)
86511 #define USDHC_INT_STATUS_EN_DMAESEN_SHIFT        (28U)
86512 /*! DMAESEN - DMA error status enable
86513  *  0b1..Enabled
86514  *  0b0..Masked
86515  */
86516 #define USDHC_INT_STATUS_EN_DMAESEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DMAESEN_SHIFT)) & USDHC_INT_STATUS_EN_DMAESEN_MASK)
86517 /*! @} */
86518 
86519 /*! @name INT_SIGNAL_EN - Interrupt Signal Enable */
86520 /*! @{ */
86521 
86522 #define USDHC_INT_SIGNAL_EN_CCIEN_MASK           (0x1U)
86523 #define USDHC_INT_SIGNAL_EN_CCIEN_SHIFT          (0U)
86524 /*! CCIEN - Command complete interrupt enable
86525  *  0b1..Enabled
86526  *  0b0..Masked
86527  */
86528 #define USDHC_INT_SIGNAL_EN_CCIEN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCIEN_MASK)
86529 
86530 #define USDHC_INT_SIGNAL_EN_TCIEN_MASK           (0x2U)
86531 #define USDHC_INT_SIGNAL_EN_TCIEN_SHIFT          (1U)
86532 /*! TCIEN - Transfer complete interrupt enable
86533  *  0b1..Enabled
86534  *  0b0..Masked
86535  */
86536 #define USDHC_INT_SIGNAL_EN_TCIEN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TCIEN_MASK)
86537 
86538 #define USDHC_INT_SIGNAL_EN_BGEIEN_MASK          (0x4U)
86539 #define USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT         (2U)
86540 /*! BGEIEN - Block gap event interrupt enable
86541  *  0b1..Enabled
86542  *  0b0..Masked
86543  */
86544 #define USDHC_INT_SIGNAL_EN_BGEIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BGEIEN_MASK)
86545 
86546 #define USDHC_INT_SIGNAL_EN_DINTIEN_MASK         (0x8U)
86547 #define USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT        (3U)
86548 /*! DINTIEN - DMA interrupt enable
86549  *  0b1..Enabled
86550  *  0b0..Masked
86551  */
86552 #define USDHC_INT_SIGNAL_EN_DINTIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DINTIEN_MASK)
86553 
86554 #define USDHC_INT_SIGNAL_EN_BWRIEN_MASK          (0x10U)
86555 #define USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT         (4U)
86556 /*! BWRIEN - Buffer write ready interrupt enable
86557  *  0b1..Enabled
86558  *  0b0..Masked
86559  */
86560 #define USDHC_INT_SIGNAL_EN_BWRIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BWRIEN_MASK)
86561 
86562 #define USDHC_INT_SIGNAL_EN_BRRIEN_MASK          (0x20U)
86563 #define USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT         (5U)
86564 /*! BRRIEN - Buffer read ready interrupt enable
86565  *  0b1..Enabled
86566  *  0b0..Masked
86567  */
86568 #define USDHC_INT_SIGNAL_EN_BRRIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BRRIEN_MASK)
86569 
86570 #define USDHC_INT_SIGNAL_EN_CINSIEN_MASK         (0x40U)
86571 #define USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT        (6U)
86572 /*! CINSIEN - Card insertion interrupt enable
86573  *  0b1..Enabled
86574  *  0b0..Masked
86575  */
86576 #define USDHC_INT_SIGNAL_EN_CINSIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINSIEN_MASK)
86577 
86578 #define USDHC_INT_SIGNAL_EN_CRMIEN_MASK          (0x80U)
86579 #define USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT         (7U)
86580 /*! CRMIEN - Card removal interrupt enable
86581  *  0b1..Enabled
86582  *  0b0..Masked
86583  */
86584 #define USDHC_INT_SIGNAL_EN_CRMIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CRMIEN_MASK)
86585 
86586 #define USDHC_INT_SIGNAL_EN_CINTIEN_MASK         (0x100U)
86587 #define USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT        (8U)
86588 /*! CINTIEN - Card interrupt enable
86589  *  0b1..Enabled
86590  *  0b0..Masked
86591  */
86592 #define USDHC_INT_SIGNAL_EN_CINTIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINTIEN_MASK)
86593 
86594 #define USDHC_INT_SIGNAL_EN_RTEIEN_MASK          (0x1000U)
86595 #define USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT         (12U)
86596 /*! RTEIEN - Re-tuning event interrupt enable
86597  *  0b1..Enabled
86598  *  0b0..Masked
86599  */
86600 #define USDHC_INT_SIGNAL_EN_RTEIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_RTEIEN_MASK)
86601 
86602 #define USDHC_INT_SIGNAL_EN_TPIEN_MASK           (0x4000U)
86603 #define USDHC_INT_SIGNAL_EN_TPIEN_SHIFT          (14U)
86604 /*! TPIEN - Tuning Pass interrupt enable
86605  *  0b1..Enabled
86606  *  0b0..Masked
86607  */
86608 #define USDHC_INT_SIGNAL_EN_TPIEN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TPIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TPIEN_MASK)
86609 
86610 #define USDHC_INT_SIGNAL_EN_CTOEIEN_MASK         (0x10000U)
86611 #define USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT        (16U)
86612 /*! CTOEIEN - Command timeout error interrupt enable
86613  *  0b1..Enabled
86614  *  0b0..Masked
86615  */
86616 #define USDHC_INT_SIGNAL_EN_CTOEIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CTOEIEN_MASK)
86617 
86618 #define USDHC_INT_SIGNAL_EN_CCEIEN_MASK          (0x20000U)
86619 #define USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT         (17U)
86620 /*! CCEIEN - Command CRC error interrupt enable
86621  *  0b1..Enabled
86622  *  0b0..Masked
86623  */
86624 #define USDHC_INT_SIGNAL_EN_CCEIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCEIEN_MASK)
86625 
86626 #define USDHC_INT_SIGNAL_EN_CEBEIEN_MASK         (0x40000U)
86627 #define USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT        (18U)
86628 /*! CEBEIEN - Command end bit error interrupt enable
86629  *  0b1..Enabled
86630  *  0b0..Masked
86631  */
86632 #define USDHC_INT_SIGNAL_EN_CEBEIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CEBEIEN_MASK)
86633 
86634 #define USDHC_INT_SIGNAL_EN_CIEIEN_MASK          (0x80000U)
86635 #define USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT         (19U)
86636 /*! CIEIEN - Command index error interrupt enable
86637  *  0b1..Enabled
86638  *  0b0..Masked
86639  */
86640 #define USDHC_INT_SIGNAL_EN_CIEIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CIEIEN_MASK)
86641 
86642 #define USDHC_INT_SIGNAL_EN_DTOEIEN_MASK         (0x100000U)
86643 #define USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT        (20U)
86644 /*! DTOEIEN - Data timeout error interrupt enable
86645  *  0b1..Enabled
86646  *  0b0..Masked
86647  */
86648 #define USDHC_INT_SIGNAL_EN_DTOEIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DTOEIEN_MASK)
86649 
86650 #define USDHC_INT_SIGNAL_EN_DCEIEN_MASK          (0x200000U)
86651 #define USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT         (21U)
86652 /*! DCEIEN - Data CRC error interrupt enable
86653  *  0b1..Enabled
86654  *  0b0..Masked
86655  */
86656 #define USDHC_INT_SIGNAL_EN_DCEIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DCEIEN_MASK)
86657 
86658 #define USDHC_INT_SIGNAL_EN_DEBEIEN_MASK         (0x400000U)
86659 #define USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT        (22U)
86660 /*! DEBEIEN - Data end bit error interrupt enable
86661  *  0b1..Enabled
86662  *  0b0..Masked
86663  */
86664 #define USDHC_INT_SIGNAL_EN_DEBEIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DEBEIEN_MASK)
86665 
86666 #define USDHC_INT_SIGNAL_EN_AC12EIEN_MASK        (0x1000000U)
86667 #define USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT       (24U)
86668 /*! AC12EIEN - Auto CMD12 error interrupt enable
86669  *  0b1..Enabled
86670  *  0b0..Masked
86671  */
86672 #define USDHC_INT_SIGNAL_EN_AC12EIEN(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_AC12EIEN_MASK)
86673 
86674 #define USDHC_INT_SIGNAL_EN_TNEIEN_MASK          (0x4000000U)
86675 #define USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT         (26U)
86676 /*! TNEIEN - Tuning error interrupt enable
86677  *  0b1..Enabled
86678  *  0b0..Masked
86679  */
86680 #define USDHC_INT_SIGNAL_EN_TNEIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TNEIEN_MASK)
86681 
86682 #define USDHC_INT_SIGNAL_EN_DMAEIEN_MASK         (0x10000000U)
86683 #define USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT        (28U)
86684 /*! DMAEIEN - DMA error interrupt enable
86685  *  0b1..Enable
86686  *  0b0..Masked
86687  */
86688 #define USDHC_INT_SIGNAL_EN_DMAEIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DMAEIEN_MASK)
86689 /*! @} */
86690 
86691 /*! @name AUTOCMD12_ERR_STATUS - Auto CMD12 Error Status */
86692 /*! @{ */
86693 
86694 #define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK   (0x1U)
86695 #define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT  (0U)
86696 /*! AC12NE - Auto CMD12 not executed
86697  *  0b1..Not executed
86698  *  0b0..Executed
86699  */
86700 #define USDHC_AUTOCMD12_ERR_STATUS_AC12NE(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK)
86701 
86702 #define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK  (0x2U)
86703 #define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT (1U)
86704 /*! AC12TOE - Auto CMD12 / 23 timeout error
86705  *  0b1..Time out
86706  *  0b0..No error
86707  */
86708 #define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK)
86709 
86710 #define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK   (0x4U)
86711 #define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT  (2U)
86712 /*! AC12CE - Auto CMD12 / 23 CRC error
86713  *  0b1..CRC error met in Auto CMD12/23 response
86714  *  0b0..No CRC error
86715  */
86716 #define USDHC_AUTOCMD12_ERR_STATUS_AC12CE(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK)
86717 
86718 #define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK  (0x8U)
86719 #define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT (3U)
86720 /*! AC12EBE - Auto CMD12 / 23 end bit error
86721  *  0b1..End bit error generated
86722  *  0b0..No error
86723  */
86724 #define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK)
86725 
86726 #define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK   (0x10U)
86727 #define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT  (4U)
86728 /*! AC12IE - Auto CMD12 / 23 index error
86729  *  0b1..Error, the CMD index in response is not CMD12/23
86730  *  0b0..No error
86731  */
86732 #define USDHC_AUTOCMD12_ERR_STATUS_AC12IE(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK)
86733 
86734 #define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK (0x80U)
86735 #define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT (7U)
86736 /*! CNIBAC12E - Command not issued by Auto CMD12 error
86737  *  0b1..Not issued
86738  *  0b0..No error
86739  */
86740 #define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E(x)  (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK)
86741 
86742 #define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK (0x400000U)
86743 #define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT (22U)
86744 /*! EXECUTE_TUNING - Execute tuning
86745  *  0b1..Start tuning procedure
86746  *  0b0..Tuning procedure is aborted
86747  */
86748 #define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK)
86749 
86750 #define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK (0x800000U)
86751 #define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT (23U)
86752 /*! SMP_CLK_SEL - Sample clock select
86753  *  0b1..Tuned clock is used to sample data
86754  *  0b0..Fixed clock is used to sample data
86755  */
86756 #define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK)
86757 /*! @} */
86758 
86759 /*! @name HOST_CTRL_CAP - Host Controller Capabilities */
86760 /*! @{ */
86761 
86762 #define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK   (0x1U)
86763 #define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT  (0U)
86764 /*! SDR50_SUPPORT - SDR50 support */
86765 #define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK)
86766 
86767 #define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK  (0x2U)
86768 #define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT (1U)
86769 /*! SDR104_SUPPORT - SDR104 support */
86770 #define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK)
86771 
86772 #define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK   (0x4U)
86773 #define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT  (2U)
86774 /*! DDR50_SUPPORT - DDR50 support */
86775 #define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK)
86776 
86777 #define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK (0x2000U)
86778 #define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT (13U)
86779 /*! USE_TUNING_SDR50 - Use Tuning for SDR50
86780  *  0b1..SDR50 supports tuning
86781  *  0b0..SDR50 does not support tuning
86782  */
86783 #define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50(x)  (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT)) & USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK)
86784 
86785 #define USDHC_HOST_CTRL_CAP_MBL_MASK             (0x70000U)
86786 #define USDHC_HOST_CTRL_CAP_MBL_SHIFT            (16U)
86787 /*! MBL - Max block length
86788  *  0b000..512 bytes
86789  *  0b001..1024 bytes
86790  *  0b010..2048 bytes
86791  *  0b011..4096 bytes
86792  */
86793 #define USDHC_HOST_CTRL_CAP_MBL(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_MBL_SHIFT)) & USDHC_HOST_CTRL_CAP_MBL_MASK)
86794 
86795 #define USDHC_HOST_CTRL_CAP_ADMAS_MASK           (0x100000U)
86796 #define USDHC_HOST_CTRL_CAP_ADMAS_SHIFT          (20U)
86797 /*! ADMAS - ADMA support
86798  *  0b1..Advanced DMA supported
86799  *  0b0..Advanced DMA not supported
86800  */
86801 #define USDHC_HOST_CTRL_CAP_ADMAS(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_ADMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_ADMAS_MASK)
86802 
86803 #define USDHC_HOST_CTRL_CAP_HSS_MASK             (0x200000U)
86804 #define USDHC_HOST_CTRL_CAP_HSS_SHIFT            (21U)
86805 /*! HSS - High speed support
86806  *  0b1..High speed supported
86807  *  0b0..High speed not supported
86808  */
86809 #define USDHC_HOST_CTRL_CAP_HSS(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_HSS_SHIFT)) & USDHC_HOST_CTRL_CAP_HSS_MASK)
86810 
86811 #define USDHC_HOST_CTRL_CAP_DMAS_MASK            (0x400000U)
86812 #define USDHC_HOST_CTRL_CAP_DMAS_SHIFT           (22U)
86813 /*! DMAS - DMA support
86814  *  0b1..DMA supported
86815  *  0b0..DMA not supported
86816  */
86817 #define USDHC_HOST_CTRL_CAP_DMAS(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_DMAS_MASK)
86818 
86819 #define USDHC_HOST_CTRL_CAP_SRS_MASK             (0x800000U)
86820 #define USDHC_HOST_CTRL_CAP_SRS_SHIFT            (23U)
86821 /*! SRS - Suspend / resume support
86822  *  0b1..Supported
86823  *  0b0..Not supported
86824  */
86825 #define USDHC_HOST_CTRL_CAP_SRS(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SRS_SHIFT)) & USDHC_HOST_CTRL_CAP_SRS_MASK)
86826 
86827 #define USDHC_HOST_CTRL_CAP_VS33_MASK            (0x1000000U)
86828 #define USDHC_HOST_CTRL_CAP_VS33_SHIFT           (24U)
86829 /*! VS33 - Voltage support 3.3 V
86830  *  0b1..3.3 V supported
86831  *  0b0..3.3 V not supported
86832  */
86833 #define USDHC_HOST_CTRL_CAP_VS33(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS33_SHIFT)) & USDHC_HOST_CTRL_CAP_VS33_MASK)
86834 
86835 #define USDHC_HOST_CTRL_CAP_VS30_MASK            (0x2000000U)
86836 #define USDHC_HOST_CTRL_CAP_VS30_SHIFT           (25U)
86837 /*! VS30 - Voltage support 3.0 V
86838  *  0b1..3.0 V supported
86839  *  0b0..3.0 V not supported
86840  */
86841 #define USDHC_HOST_CTRL_CAP_VS30(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS30_SHIFT)) & USDHC_HOST_CTRL_CAP_VS30_MASK)
86842 
86843 #define USDHC_HOST_CTRL_CAP_VS18_MASK            (0x4000000U)
86844 #define USDHC_HOST_CTRL_CAP_VS18_SHIFT           (26U)
86845 /*! VS18 - Voltage support 1.8 V
86846  *  0b1..1.8 V supported
86847  *  0b0..1.8 V not supported
86848  */
86849 #define USDHC_HOST_CTRL_CAP_VS18(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS18_SHIFT)) & USDHC_HOST_CTRL_CAP_VS18_MASK)
86850 /*! @} */
86851 
86852 /*! @name WTMK_LVL - Watermark Level */
86853 /*! @{ */
86854 
86855 #define USDHC_WTMK_LVL_RD_WML_MASK               (0xFFU)
86856 #define USDHC_WTMK_LVL_RD_WML_SHIFT              (0U)
86857 /*! RD_WML - Read watermark level */
86858 #define USDHC_WTMK_LVL_RD_WML(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_WML_SHIFT)) & USDHC_WTMK_LVL_RD_WML_MASK)
86859 
86860 #define USDHC_WTMK_LVL_RD_BRST_LEN_MASK          (0x1F00U)
86861 #define USDHC_WTMK_LVL_RD_BRST_LEN_SHIFT         (8U)
86862 /*! RD_BRST_LEN - Read burst length due to system restriction, the actual burst length might not exceed 16 */
86863 #define USDHC_WTMK_LVL_RD_BRST_LEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_BRST_LEN_SHIFT)) & USDHC_WTMK_LVL_RD_BRST_LEN_MASK)
86864 
86865 #define USDHC_WTMK_LVL_WR_WML_MASK               (0xFF0000U)
86866 #define USDHC_WTMK_LVL_WR_WML_SHIFT              (16U)
86867 /*! WR_WML - Write watermark level */
86868 #define USDHC_WTMK_LVL_WR_WML(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_WML_SHIFT)) & USDHC_WTMK_LVL_WR_WML_MASK)
86869 
86870 #define USDHC_WTMK_LVL_WR_BRST_LEN_MASK          (0x1F000000U)
86871 #define USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT         (24U)
86872 /*! WR_BRST_LEN - Write burst length due to system restriction, the actual burst length might not exceed 16 */
86873 #define USDHC_WTMK_LVL_WR_BRST_LEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT)) & USDHC_WTMK_LVL_WR_BRST_LEN_MASK)
86874 /*! @} */
86875 
86876 /*! @name MIX_CTRL - Mixer Control */
86877 /*! @{ */
86878 
86879 #define USDHC_MIX_CTRL_DMAEN_MASK                (0x1U)
86880 #define USDHC_MIX_CTRL_DMAEN_SHIFT               (0U)
86881 /*! DMAEN - DMA enable
86882  *  0b1..Enable
86883  *  0b0..Disable
86884  */
86885 #define USDHC_MIX_CTRL_DMAEN(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DMAEN_SHIFT)) & USDHC_MIX_CTRL_DMAEN_MASK)
86886 
86887 #define USDHC_MIX_CTRL_BCEN_MASK                 (0x2U)
86888 #define USDHC_MIX_CTRL_BCEN_SHIFT                (1U)
86889 /*! BCEN - Block count enable
86890  *  0b1..Enable
86891  *  0b0..Disable
86892  */
86893 #define USDHC_MIX_CTRL_BCEN(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_BCEN_SHIFT)) & USDHC_MIX_CTRL_BCEN_MASK)
86894 
86895 #define USDHC_MIX_CTRL_AC12EN_MASK               (0x4U)
86896 #define USDHC_MIX_CTRL_AC12EN_SHIFT              (2U)
86897 /*! AC12EN - Auto CMD12 enable
86898  *  0b1..Enable
86899  *  0b0..Disable
86900  */
86901 #define USDHC_MIX_CTRL_AC12EN(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC12EN_SHIFT)) & USDHC_MIX_CTRL_AC12EN_MASK)
86902 
86903 #define USDHC_MIX_CTRL_DDR_EN_MASK               (0x8U)
86904 #define USDHC_MIX_CTRL_DDR_EN_SHIFT              (3U)
86905 /*! DDR_EN - Dual data rate mode selection */
86906 #define USDHC_MIX_CTRL_DDR_EN(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DDR_EN_SHIFT)) & USDHC_MIX_CTRL_DDR_EN_MASK)
86907 
86908 #define USDHC_MIX_CTRL_DTDSEL_MASK               (0x10U)
86909 #define USDHC_MIX_CTRL_DTDSEL_SHIFT              (4U)
86910 /*! DTDSEL - Data transfer direction select
86911  *  0b1..Read (Card to host)
86912  *  0b0..Write (Host to card)
86913  */
86914 #define USDHC_MIX_CTRL_DTDSEL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DTDSEL_SHIFT)) & USDHC_MIX_CTRL_DTDSEL_MASK)
86915 
86916 #define USDHC_MIX_CTRL_MSBSEL_MASK               (0x20U)
86917 #define USDHC_MIX_CTRL_MSBSEL_SHIFT              (5U)
86918 /*! MSBSEL - Multi / Single block select
86919  *  0b1..Multiple blocks
86920  *  0b0..Single block
86921  */
86922 #define USDHC_MIX_CTRL_MSBSEL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_MSBSEL_SHIFT)) & USDHC_MIX_CTRL_MSBSEL_MASK)
86923 
86924 #define USDHC_MIX_CTRL_NIBBLE_POS_MASK           (0x40U)
86925 #define USDHC_MIX_CTRL_NIBBLE_POS_SHIFT          (6U)
86926 /*! NIBBLE_POS - Nibble position indication */
86927 #define USDHC_MIX_CTRL_NIBBLE_POS(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK)
86928 
86929 #define USDHC_MIX_CTRL_AC23EN_MASK               (0x80U)
86930 #define USDHC_MIX_CTRL_AC23EN_SHIFT              (7U)
86931 /*! AC23EN - Auto CMD23 enable */
86932 #define USDHC_MIX_CTRL_AC23EN(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC23EN_SHIFT)) & USDHC_MIX_CTRL_AC23EN_MASK)
86933 
86934 #define USDHC_MIX_CTRL_EXE_TUNE_MASK             (0x400000U)
86935 #define USDHC_MIX_CTRL_EXE_TUNE_SHIFT            (22U)
86936 /*! EXE_TUNE - Execute tuning: (Only used for SD3.0, SDR104 mode)
86937  *  0b1..Execute tuning
86938  *  0b0..Not tuned or tuning completed
86939  */
86940 #define USDHC_MIX_CTRL_EXE_TUNE(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_EXE_TUNE_SHIFT)) & USDHC_MIX_CTRL_EXE_TUNE_MASK)
86941 
86942 #define USDHC_MIX_CTRL_SMP_CLK_SEL_MASK          (0x800000U)
86943 #define USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT         (23U)
86944 /*! SMP_CLK_SEL - Clock selection
86945  *  0b1..Tuned clock is used to sample data / cmd
86946  *  0b0..Fixed clock is used to sample data / cmd
86947  */
86948 #define USDHC_MIX_CTRL_SMP_CLK_SEL(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT)) & USDHC_MIX_CTRL_SMP_CLK_SEL_MASK)
86949 
86950 #define USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK         (0x1000000U)
86951 #define USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT        (24U)
86952 /*! AUTO_TUNE_EN - Auto tuning enable (Only used for SD3.0, SDR104 mode)
86953  *  0b1..Enable auto tuning
86954  *  0b0..Disable auto tuning
86955  */
86956 #define USDHC_MIX_CTRL_AUTO_TUNE_EN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT)) & USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK)
86957 
86958 #define USDHC_MIX_CTRL_FBCLK_SEL_MASK            (0x2000000U)
86959 #define USDHC_MIX_CTRL_FBCLK_SEL_SHIFT           (25U)
86960 /*! FBCLK_SEL - Feedback clock source selection (Only used for SD3.0, SDR104 mode)
86961  *  0b1..Feedback clock comes from the ipp_card_clk_out
86962  *  0b0..Feedback clock comes from the loopback CLK
86963  */
86964 #define USDHC_MIX_CTRL_FBCLK_SEL(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_FBCLK_SEL_SHIFT)) & USDHC_MIX_CTRL_FBCLK_SEL_MASK)
86965 /*! @} */
86966 
86967 /*! @name FORCE_EVENT - Force Event */
86968 /*! @{ */
86969 
86970 #define USDHC_FORCE_EVENT_FEVTAC12NE_MASK        (0x1U)
86971 #define USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT       (0U)
86972 /*! FEVTAC12NE - Force event auto command 12 not executed */
86973 #define USDHC_FORCE_EVENT_FEVTAC12NE(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12NE_MASK)
86974 
86975 #define USDHC_FORCE_EVENT_FEVTAC12TOE_MASK       (0x2U)
86976 #define USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT      (1U)
86977 /*! FEVTAC12TOE - Force event auto command 12 time out error */
86978 #define USDHC_FORCE_EVENT_FEVTAC12TOE(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12TOE_MASK)
86979 
86980 #define USDHC_FORCE_EVENT_FEVTAC12CE_MASK        (0x4U)
86981 #define USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT       (2U)
86982 /*! FEVTAC12CE - Force event auto command 12 CRC error */
86983 #define USDHC_FORCE_EVENT_FEVTAC12CE(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12CE_MASK)
86984 
86985 #define USDHC_FORCE_EVENT_FEVTAC12EBE_MASK       (0x8U)
86986 #define USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT      (3U)
86987 /*! FEVTAC12EBE - Force event Auto Command 12 end bit error */
86988 #define USDHC_FORCE_EVENT_FEVTAC12EBE(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12EBE_MASK)
86989 
86990 #define USDHC_FORCE_EVENT_FEVTAC12IE_MASK        (0x10U)
86991 #define USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT       (4U)
86992 /*! FEVTAC12IE - Force event Auto Command 12 index error */
86993 #define USDHC_FORCE_EVENT_FEVTAC12IE(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12IE_MASK)
86994 
86995 #define USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK     (0x80U)
86996 #define USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT    (7U)
86997 /*! FEVTCNIBAC12E - Force event command not executed by Auto Command 12 error */
86998 #define USDHC_FORCE_EVENT_FEVTCNIBAC12E(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK)
86999 
87000 #define USDHC_FORCE_EVENT_FEVTCTOE_MASK          (0x10000U)
87001 #define USDHC_FORCE_EVENT_FEVTCTOE_SHIFT         (16U)
87002 /*! FEVTCTOE - Force event command time out error */
87003 #define USDHC_FORCE_EVENT_FEVTCTOE(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCTOE_MASK)
87004 
87005 #define USDHC_FORCE_EVENT_FEVTCCE_MASK           (0x20000U)
87006 #define USDHC_FORCE_EVENT_FEVTCCE_SHIFT          (17U)
87007 /*! FEVTCCE - Force event command CRC error */
87008 #define USDHC_FORCE_EVENT_FEVTCCE(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCCE_MASK)
87009 
87010 #define USDHC_FORCE_EVENT_FEVTCEBE_MASK          (0x40000U)
87011 #define USDHC_FORCE_EVENT_FEVTCEBE_SHIFT         (18U)
87012 /*! FEVTCEBE - Force event command end bit error */
87013 #define USDHC_FORCE_EVENT_FEVTCEBE(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCEBE_MASK)
87014 
87015 #define USDHC_FORCE_EVENT_FEVTCIE_MASK           (0x80000U)
87016 #define USDHC_FORCE_EVENT_FEVTCIE_SHIFT          (19U)
87017 /*! FEVTCIE - Force event command index error */
87018 #define USDHC_FORCE_EVENT_FEVTCIE(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCIE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCIE_MASK)
87019 
87020 #define USDHC_FORCE_EVENT_FEVTDTOE_MASK          (0x100000U)
87021 #define USDHC_FORCE_EVENT_FEVTDTOE_SHIFT         (20U)
87022 /*! FEVTDTOE - Force event data time out error */
87023 #define USDHC_FORCE_EVENT_FEVTDTOE(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDTOE_MASK)
87024 
87025 #define USDHC_FORCE_EVENT_FEVTDCE_MASK           (0x200000U)
87026 #define USDHC_FORCE_EVENT_FEVTDCE_SHIFT          (21U)
87027 /*! FEVTDCE - Force event data CRC error */
87028 #define USDHC_FORCE_EVENT_FEVTDCE(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDCE_MASK)
87029 
87030 #define USDHC_FORCE_EVENT_FEVTDEBE_MASK          (0x400000U)
87031 #define USDHC_FORCE_EVENT_FEVTDEBE_SHIFT         (22U)
87032 /*! FEVTDEBE - Force event data end bit error */
87033 #define USDHC_FORCE_EVENT_FEVTDEBE(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDEBE_MASK)
87034 
87035 #define USDHC_FORCE_EVENT_FEVTAC12E_MASK         (0x1000000U)
87036 #define USDHC_FORCE_EVENT_FEVTAC12E_SHIFT        (24U)
87037 /*! FEVTAC12E - Force event Auto Command 12 error */
87038 #define USDHC_FORCE_EVENT_FEVTAC12E(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12E_MASK)
87039 
87040 #define USDHC_FORCE_EVENT_FEVTTNE_MASK           (0x4000000U)
87041 #define USDHC_FORCE_EVENT_FEVTTNE_SHIFT          (26U)
87042 /*! FEVTTNE - Force tuning error */
87043 #define USDHC_FORCE_EVENT_FEVTTNE(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTTNE_SHIFT)) & USDHC_FORCE_EVENT_FEVTTNE_MASK)
87044 
87045 #define USDHC_FORCE_EVENT_FEVTDMAE_MASK          (0x10000000U)
87046 #define USDHC_FORCE_EVENT_FEVTDMAE_SHIFT         (28U)
87047 /*! FEVTDMAE - Force event DMA error */
87048 #define USDHC_FORCE_EVENT_FEVTDMAE(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDMAE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDMAE_MASK)
87049 
87050 #define USDHC_FORCE_EVENT_FEVTCINT_MASK          (0x80000000U)
87051 #define USDHC_FORCE_EVENT_FEVTCINT_SHIFT         (31U)
87052 /*! FEVTCINT - Force event card interrupt */
87053 #define USDHC_FORCE_EVENT_FEVTCINT(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCINT_SHIFT)) & USDHC_FORCE_EVENT_FEVTCINT_MASK)
87054 /*! @} */
87055 
87056 /*! @name ADMA_ERR_STATUS - ADMA Error Status */
87057 /*! @{ */
87058 
87059 #define USDHC_ADMA_ERR_STATUS_ADMAES_MASK        (0x3U)
87060 #define USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT       (0U)
87061 /*! ADMAES - ADMA error state (when ADMA error is occurred) */
87062 #define USDHC_ADMA_ERR_STATUS_ADMAES(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMAES_MASK)
87063 
87064 #define USDHC_ADMA_ERR_STATUS_ADMALME_MASK       (0x4U)
87065 #define USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT      (2U)
87066 /*! ADMALME - ADMA length mismatch error
87067  *  0b1..Error
87068  *  0b0..No error
87069  */
87070 #define USDHC_ADMA_ERR_STATUS_ADMALME(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMALME_MASK)
87071 
87072 #define USDHC_ADMA_ERR_STATUS_ADMADCE_MASK       (0x8U)
87073 #define USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT      (3U)
87074 /*! ADMADCE - ADMA descriptor error
87075  *  0b1..Error
87076  *  0b0..No error
87077  */
87078 #define USDHC_ADMA_ERR_STATUS_ADMADCE(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMADCE_MASK)
87079 /*! @} */
87080 
87081 /*! @name ADMA_SYS_ADDR - ADMA System Address */
87082 /*! @{ */
87083 
87084 #define USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK        (0xFFFFFFFCU)
87085 #define USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT       (2U)
87086 /*! ADS_ADDR - ADMA system address */
87087 #define USDHC_ADMA_SYS_ADDR_ADS_ADDR(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT)) & USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK)
87088 /*! @} */
87089 
87090 /*! @name DLL_CTRL - DLL (Delay Line) Control */
87091 /*! @{ */
87092 
87093 #define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK      (0x1U)
87094 #define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT     (0U)
87095 /*! DLL_CTRL_ENABLE - DLL and delay chain */
87096 #define USDHC_DLL_CTRL_DLL_CTRL_ENABLE(x)        (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK)
87097 
87098 #define USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK       (0x2U)
87099 #define USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT      (1U)
87100 /*! DLL_CTRL_RESET - DLL reset */
87101 #define USDHC_DLL_CTRL_DLL_CTRL_RESET(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK)
87102 
87103 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U)
87104 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U)
87105 /*! DLL_CTRL_SLV_FORCE_UPD - DLL slave delay line */
87106 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK)
87107 
87108 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK (0x78U)
87109 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT (3U)
87110 /*! DLL_CTRL_SLV_DLY_TARGET0 - DLL slave delay target0 */
87111 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK)
87112 
87113 #define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK (0x80U)
87114 #define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT (7U)
87115 /*! DLL_CTRL_GATE_UPDATE - DLL gate update */
87116 #define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE(x)   (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK)
87117 
87118 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK (0x100U)
87119 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT (8U)
87120 /*! DLL_CTRL_SLV_OVERRIDE - DLL slave override */
87121 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE(x)  (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK)
87122 
87123 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0xFE00U)
87124 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (9U)
87125 /*! DLL_CTRL_SLV_OVERRIDE_VAL - DLL slave override val */
87126 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK)
87127 
87128 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK (0x70000U)
87129 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT (16U)
87130 /*! DLL_CTRL_SLV_DLY_TARGET1 - DLL slave delay target1 */
87131 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK)
87132 
87133 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U)
87134 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U)
87135 /*! DLL_CTRL_SLV_UPDATE_INT - Slave delay line update interval */
87136 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK)
87137 
87138 #define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U)
87139 #define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U)
87140 /*! DLL_CTRL_REF_UPDATE_INT - DLL control loop update interval */
87141 #define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK)
87142 /*! @} */
87143 
87144 /*! @name DLL_STATUS - DLL Status */
87145 /*! @{ */
87146 
87147 #define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK   (0x1U)
87148 #define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT  (0U)
87149 /*! DLL_STS_SLV_LOCK - Slave delay-line lock status */
87150 #define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK)
87151 
87152 #define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK   (0x2U)
87153 #define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT  (1U)
87154 /*! DLL_STS_REF_LOCK - Reference DLL lock status */
87155 #define USDHC_DLL_STATUS_DLL_STS_REF_LOCK(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK)
87156 
87157 #define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK    (0x1FCU)
87158 #define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT   (2U)
87159 /*! DLL_STS_SLV_SEL - Slave delay line select status */
87160 #define USDHC_DLL_STATUS_DLL_STS_SLV_SEL(x)      (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK)
87161 
87162 #define USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK    (0xFE00U)
87163 #define USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT   (9U)
87164 /*! DLL_STS_REF_SEL - Reference delay line select taps */
87165 #define USDHC_DLL_STATUS_DLL_STS_REF_SEL(x)      (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK)
87166 /*! @} */
87167 
87168 /*! @name CLK_TUNE_CTRL_STATUS - CLK Tuning Control and Status */
87169 /*! @{ */
87170 
87171 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK (0xFU)
87172 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT (0U)
87173 /*! DLY_CELL_SET_POST - Delay cells on the feedback clock between CLK_OUT and CLK_POST */
87174 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK)
87175 
87176 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK (0xF0U)
87177 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT (4U)
87178 /*! DLY_CELL_SET_OUT - Delay cells on the feedback clock between CLK_PRE and CLK_OUT */
87179 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK)
87180 
87181 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK (0x7F00U)
87182 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT (8U)
87183 /*! DLY_CELL_SET_PRE - delay cells on the feedback clock between the feedback clock and CLK_PRE */
87184 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK)
87185 
87186 #define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK  (0x8000U)
87187 #define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT (15U)
87188 /*! NXT_ERR - NXT error */
87189 #define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK)
87190 
87191 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK (0xF0000U)
87192 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT (16U)
87193 /*! TAP_SEL_POST - Delay cells added on the feedback clock between CLK_OUT and CLK_POST */
87194 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK)
87195 
87196 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK (0xF00000U)
87197 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT (20U)
87198 /*! TAP_SEL_OUT - Delay cells added on the feedback clock between CLK_PRE and CLK_OUT */
87199 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK)
87200 
87201 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK (0x7F000000U)
87202 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT (24U)
87203 /*! TAP_SEL_PRE - TAP_SEL_PRE */
87204 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK)
87205 
87206 #define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK  (0x80000000U)
87207 #define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT (31U)
87208 /*! PRE_ERR - PRE error */
87209 #define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK)
87210 /*! @} */
87211 
87212 /*! @name VEND_SPEC - Vendor Specific Register */
87213 /*! @{ */
87214 
87215 #define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK  (0x8U)
87216 #define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT (3U)
87217 /*! AC12_WR_CHKBUSY_EN - Check busy enable
87218  *  0b0..Do not check busy after auto CMD12 for write data packet
87219  *  0b1..Check busy after auto CMD12 for write data packet
87220  */
87221 #define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT)) & USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK)
87222 
87223 #define USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK        (0x100U)
87224 #define USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT       (8U)
87225 /*! FRC_SDCLK_ON - Force CLK
87226  *  0b0..CLK active or inactive is fully controlled by the hardware.
87227  *  0b1..Force CLK active
87228  */
87229 #define USDHC_VEND_SPEC_FRC_SDCLK_ON(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT)) & USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK)
87230 
87231 #define USDHC_VEND_SPEC_CRC_CHK_DIS_MASK         (0x8000U)
87232 #define USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT        (15U)
87233 /*! CRC_CHK_DIS - CRC Check Disable
87234  *  0b0..Check CRC16 for every read data packet and check CRC fields for every write data packet
87235  *  0b1..Ignore CRC16 check for every read data packet and ignore CRC fields check for every write data packet
87236  */
87237 #define USDHC_VEND_SPEC_CRC_CHK_DIS(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT)) & USDHC_VEND_SPEC_CRC_CHK_DIS_MASK)
87238 
87239 #define USDHC_VEND_SPEC_CMD_BYTE_EN_MASK         (0x80000000U)
87240 #define USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT        (31U)
87241 /*! CMD_BYTE_EN - Register byte access for CMD_XFR_TYP
87242  *  0b0..Disable. MIX_CTRL[7:0] is read/write and CMD_XFR_TYP[7:0] is read-only.
87243  *  0b1..Enable. MIX_CTRL[7:0] is read-only and CMD_XFR_TYP[7:0] is read/write.
87244  */
87245 #define USDHC_VEND_SPEC_CMD_BYTE_EN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT)) & USDHC_VEND_SPEC_CMD_BYTE_EN_MASK)
87246 /*! @} */
87247 
87248 /*! @name MMC_BOOT - eMMC Boot */
87249 /*! @{ */
87250 
87251 #define USDHC_MMC_BOOT_DTOCV_ACK_MASK            (0xFU)
87252 #define USDHC_MMC_BOOT_DTOCV_ACK_SHIFT           (0U)
87253 /*! DTOCV_ACK - Boot ACK time out
87254  *  0b0000..SDCLK x 2^14
87255  *  0b0001..SDCLK x 2^15
87256  *  0b0010..SDCLK x 2^16
87257  *  0b0011..SDCLK x 2^17
87258  *  0b0100..SDCLK x 2^18
87259  *  0b0101..SDCLK x 2^19
87260  *  0b0110..SDCLK x 2^20
87261  *  0b0111..SDCLK x 2^21
87262  *  0b1110..SDCLK x 2^28
87263  *  0b1111..SDCLK x 2^29
87264  */
87265 #define USDHC_MMC_BOOT_DTOCV_ACK(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DTOCV_ACK_SHIFT)) & USDHC_MMC_BOOT_DTOCV_ACK_MASK)
87266 
87267 #define USDHC_MMC_BOOT_BOOT_ACK_MASK             (0x10U)
87268 #define USDHC_MMC_BOOT_BOOT_ACK_SHIFT            (4U)
87269 /*! BOOT_ACK - BOOT ACK
87270  *  0b0..No ack
87271  *  0b1..Ack
87272  */
87273 #define USDHC_MMC_BOOT_BOOT_ACK(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_ACK_SHIFT)) & USDHC_MMC_BOOT_BOOT_ACK_MASK)
87274 
87275 #define USDHC_MMC_BOOT_BOOT_MODE_MASK            (0x20U)
87276 #define USDHC_MMC_BOOT_BOOT_MODE_SHIFT           (5U)
87277 /*! BOOT_MODE - Boot mode
87278  *  0b0..Normal boot
87279  *  0b1..Alternative boot
87280  */
87281 #define USDHC_MMC_BOOT_BOOT_MODE(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_MODE_SHIFT)) & USDHC_MMC_BOOT_BOOT_MODE_MASK)
87282 
87283 #define USDHC_MMC_BOOT_BOOT_EN_MASK              (0x40U)
87284 #define USDHC_MMC_BOOT_BOOT_EN_SHIFT             (6U)
87285 /*! BOOT_EN - Boot enable
87286  *  0b0..Fast boot disable
87287  *  0b1..Fast boot enable
87288  */
87289 #define USDHC_MMC_BOOT_BOOT_EN(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_EN_SHIFT)) & USDHC_MMC_BOOT_BOOT_EN_MASK)
87290 
87291 #define USDHC_MMC_BOOT_AUTO_SABG_EN_MASK         (0x80U)
87292 #define USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT        (7U)
87293 /*! AUTO_SABG_EN - Auto stop at block gap */
87294 #define USDHC_MMC_BOOT_AUTO_SABG_EN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT)) & USDHC_MMC_BOOT_AUTO_SABG_EN_MASK)
87295 
87296 #define USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK     (0x100U)
87297 #define USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT    (8U)
87298 /*! DISABLE_TIME_OUT - Time out
87299  *  0b0..Enable time out
87300  *  0b1..Disable time out
87301  */
87302 #define USDHC_MMC_BOOT_DISABLE_TIME_OUT(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT)) & USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK)
87303 
87304 #define USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK         (0xFFFF0000U)
87305 #define USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT        (16U)
87306 /*! BOOT_BLK_CNT - Stop At Block Gap value of automatic mode */
87307 #define USDHC_MMC_BOOT_BOOT_BLK_CNT(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT)) & USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK)
87308 /*! @} */
87309 
87310 /*! @name VEND_SPEC2 - Vendor Specific 2 Register */
87311 /*! @{ */
87312 
87313 #define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK   (0x8U)
87314 #define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT  (3U)
87315 /*! CARD_INT_D3_TEST - Card interrupt detection test
87316  *  0b0..Check the card interrupt only when DATA3 is high.
87317  *  0b1..Check the card interrupt by ignoring the status of DATA3.
87318  */
87319 #define USDHC_VEND_SPEC2_CARD_INT_D3_TEST(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT)) & USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK)
87320 
87321 #define USDHC_VEND_SPEC2_TUNING_BIT_EN_MASK      (0x30U)
87322 #define USDHC_VEND_SPEC2_TUNING_BIT_EN_SHIFT     (4U)
87323 /*! TUNING_BIT_EN - Tuning bit enable
87324  *  0b00..Enable Tuning circuit for DATA[3:0]
87325  *  0b01..Enable Tuning circuit for DATA[7:0]
87326  *  0b10..Enable Tuning circuit for DATA[0]
87327  *  0b11..Invalid
87328  */
87329 #define USDHC_VEND_SPEC2_TUNING_BIT_EN(x)        (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_BIT_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_BIT_EN_MASK)
87330 
87331 #define USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK      (0x40U)
87332 #define USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT     (6U)
87333 /*! TUNING_CMD_EN - Tuning command enable
87334  *  0b0..Auto tuning circuit does not check the CMD line.
87335  *  0b1..Auto tuning circuit checks the CMD line.
87336  */
87337 #define USDHC_VEND_SPEC2_TUNING_CMD_EN(x)        (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK)
87338 
87339 #define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK    (0x1000U)
87340 #define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT   (12U)
87341 /*! ACMD23_ARGU2_EN - Argument2 register enable for ACMD23
87342  *  0b1..Argument2 register enable for ACMD23 sharing with SDMA system address register. Default is enabled.
87343  *  0b0..Disable
87344  */
87345 #define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN(x)      (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT)) & USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK)
87346 
87347 #define USDHC_VEND_SPEC2_EN_32K_CLK_MASK         (0x8000U)
87348 #define USDHC_VEND_SPEC2_EN_32K_CLK_SHIFT        (15U)
87349 /*! EN_32K_CLK - Select the clock source for host card detection.
87350  *  0b0..Use the peripheral clock (ipg_clk) for card detection.
87351  *  0b1..Use the low power clock (ipg_clk_lp) for card detection.
87352  */
87353 #define USDHC_VEND_SPEC2_EN_32K_CLK(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_EN_32K_CLK_SHIFT)) & USDHC_VEND_SPEC2_EN_32K_CLK_MASK)
87354 /*! @} */
87355 
87356 /*! @name TUNING_CTRL - Tuning Control */
87357 /*! @{ */
87358 
87359 #define USDHC_TUNING_CTRL_TUNING_START_TAP_MASK  (0x7FU)
87360 #define USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT (0U)
87361 /*! TUNING_START_TAP - Tuning start */
87362 #define USDHC_TUNING_CTRL_TUNING_START_TAP(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_START_TAP_MASK)
87363 
87364 #define USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_MASK (0x80U)
87365 #define USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_SHIFT (7U)
87366 /*! DIS_CMD_CHK_FOR_STD_TUNING - Disable command check for standard tuning */
87367 #define USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_SHIFT)) & USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_MASK)
87368 
87369 #define USDHC_TUNING_CTRL_TUNING_COUNTER_MASK    (0xFF00U)
87370 #define USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT   (8U)
87371 /*! TUNING_COUNTER - Tuning counter */
87372 #define USDHC_TUNING_CTRL_TUNING_COUNTER(x)      (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT)) & USDHC_TUNING_CTRL_TUNING_COUNTER_MASK)
87373 
87374 #define USDHC_TUNING_CTRL_TUNING_STEP_MASK       (0x70000U)
87375 #define USDHC_TUNING_CTRL_TUNING_STEP_SHIFT      (16U)
87376 /*! TUNING_STEP - TUNING_STEP */
87377 #define USDHC_TUNING_CTRL_TUNING_STEP(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_STEP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_STEP_MASK)
87378 
87379 #define USDHC_TUNING_CTRL_TUNING_WINDOW_MASK     (0x700000U)
87380 #define USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT    (20U)
87381 /*! TUNING_WINDOW - Data window */
87382 #define USDHC_TUNING_CTRL_TUNING_WINDOW(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT)) & USDHC_TUNING_CTRL_TUNING_WINDOW_MASK)
87383 
87384 #define USDHC_TUNING_CTRL_STD_TUNING_EN_MASK     (0x1000000U)
87385 #define USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT    (24U)
87386 /*! STD_TUNING_EN - Standard tuning circuit and procedure enable */
87387 #define USDHC_TUNING_CTRL_STD_TUNING_EN(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT)) & USDHC_TUNING_CTRL_STD_TUNING_EN_MASK)
87388 /*! @} */
87389 
87390 
87391 /*!
87392  * @}
87393  */ /* end of group USDHC_Register_Masks */
87394 
87395 
87396 /* USDHC - Peripheral instance base addresses */
87397 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
87398   /** Peripheral USDHC0 base address */
87399   #define USDHC0_BASE                              (0x50109000u)
87400   /** Peripheral USDHC0 base address */
87401   #define USDHC0_BASE_NS                           (0x40109000u)
87402   /** Peripheral USDHC0 base pointer */
87403   #define USDHC0                                   ((USDHC_Type *)USDHC0_BASE)
87404   /** Peripheral USDHC0 base pointer */
87405   #define USDHC0_NS                                ((USDHC_Type *)USDHC0_BASE_NS)
87406   /** Array initializer of USDHC peripheral base addresses */
87407   #define USDHC_BASE_ADDRS                         { USDHC0_BASE }
87408   /** Array initializer of USDHC peripheral base pointers */
87409   #define USDHC_BASE_PTRS                          { USDHC0 }
87410   /** Array initializer of USDHC peripheral base addresses */
87411   #define USDHC_BASE_ADDRS_NS                      { USDHC0_BASE_NS }
87412   /** Array initializer of USDHC peripheral base pointers */
87413   #define USDHC_BASE_PTRS_NS                       { USDHC0_NS }
87414 #else
87415   /** Peripheral USDHC0 base address */
87416   #define USDHC0_BASE                              (0x40109000u)
87417   /** Peripheral USDHC0 base pointer */
87418   #define USDHC0                                   ((USDHC_Type *)USDHC0_BASE)
87419   /** Array initializer of USDHC peripheral base addresses */
87420   #define USDHC_BASE_ADDRS                         { USDHC0_BASE }
87421   /** Array initializer of USDHC peripheral base pointers */
87422   #define USDHC_BASE_PTRS                          { USDHC0 }
87423 #endif
87424 /** Interrupt vectors for the USDHC peripheral type */
87425 #define USDHC_IRQS                               { USDHC0_IRQn }
87426 
87427 /*!
87428  * @}
87429  */ /* end of group USDHC_Peripheral_Access_Layer */
87430 
87431 
87432 /* ----------------------------------------------------------------------------
87433    -- UTICK Peripheral Access Layer
87434    ---------------------------------------------------------------------------- */
87435 
87436 /*!
87437  * @addtogroup UTICK_Peripheral_Access_Layer UTICK Peripheral Access Layer
87438  * @{
87439  */
87440 
87441 /** UTICK - Register Layout Typedef */
87442 typedef struct {
87443   __IO uint32_t CTRL;                              /**< Control, offset: 0x0 */
87444   __IO uint32_t STAT;                              /**< Status, offset: 0x4 */
87445   __IO uint32_t CFG;                               /**< Capture Configuration, offset: 0x8 */
87446   __O  uint32_t CAPCLR;                            /**< Capture Clear, offset: 0xC */
87447   __I  uint32_t CAP[4];                            /**< Capture, array offset: 0x10, array step: 0x4 */
87448 } UTICK_Type;
87449 
87450 /* ----------------------------------------------------------------------------
87451    -- UTICK Register Masks
87452    ---------------------------------------------------------------------------- */
87453 
87454 /*!
87455  * @addtogroup UTICK_Register_Masks UTICK Register Masks
87456  * @{
87457  */
87458 
87459 /*! @name CTRL - Control */
87460 /*! @{ */
87461 
87462 #define UTICK_CTRL_DELAYVAL_MASK                 (0x7FFFFFFFU)
87463 #define UTICK_CTRL_DELAYVAL_SHIFT                (0U)
87464 /*! DELAYVAL - Tick Interval
87465  *  0b0000000000000000000000000000000..
87466  *  *..Clock cycles as defined in the description
87467  */
87468 #define UTICK_CTRL_DELAYVAL(x)                   (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_DELAYVAL_SHIFT)) & UTICK_CTRL_DELAYVAL_MASK)
87469 
87470 #define UTICK_CTRL_REPEAT_MASK                   (0x80000000U)
87471 #define UTICK_CTRL_REPEAT_SHIFT                  (31U)
87472 /*! REPEAT - Repeat Delay
87473  *  0b0..One-time delay
87474  *  0b1..Delay repeats continuously
87475  */
87476 #define UTICK_CTRL_REPEAT(x)                     (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_REPEAT_SHIFT)) & UTICK_CTRL_REPEAT_MASK)
87477 /*! @} */
87478 
87479 /*! @name STAT - Status */
87480 /*! @{ */
87481 
87482 #define UTICK_STAT_INTR_MASK                     (0x1U)
87483 #define UTICK_STAT_INTR_SHIFT                    (0U)
87484 /*! INTR - Interrupt Flag
87485  *  0b0..Not pending
87486  *  0b1..Pending
87487  */
87488 #define UTICK_STAT_INTR(x)                       (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_INTR_SHIFT)) & UTICK_STAT_INTR_MASK)
87489 
87490 #define UTICK_STAT_ACTIVE_MASK                   (0x2U)
87491 #define UTICK_STAT_ACTIVE_SHIFT                  (1U)
87492 /*! ACTIVE - Timer Active Flag
87493  *  0b0..Inactive (stopped)
87494  *  0b1..Active
87495  */
87496 #define UTICK_STAT_ACTIVE(x)                     (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_ACTIVE_SHIFT)) & UTICK_STAT_ACTIVE_MASK)
87497 /*! @} */
87498 
87499 /*! @name CFG - Capture Configuration */
87500 /*! @{ */
87501 
87502 #define UTICK_CFG_CAPEN0_MASK                    (0x1U)
87503 #define UTICK_CFG_CAPEN0_SHIFT                   (0U)
87504 /*! CAPEN0 - Enable Capture 0
87505  *  0b0..Disable
87506  *  0b1..Enable
87507  */
87508 #define UTICK_CFG_CAPEN0(x)                      (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN0_SHIFT)) & UTICK_CFG_CAPEN0_MASK)
87509 
87510 #define UTICK_CFG_CAPEN1_MASK                    (0x2U)
87511 #define UTICK_CFG_CAPEN1_SHIFT                   (1U)
87512 /*! CAPEN1 - Enable Capture 1
87513  *  0b0..Disable
87514  *  0b1..Enable
87515  */
87516 #define UTICK_CFG_CAPEN1(x)                      (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN1_SHIFT)) & UTICK_CFG_CAPEN1_MASK)
87517 
87518 #define UTICK_CFG_CAPEN2_MASK                    (0x4U)
87519 #define UTICK_CFG_CAPEN2_SHIFT                   (2U)
87520 /*! CAPEN2 - Enable Capture 2
87521  *  0b0..Disable
87522  *  0b1..Enable
87523  */
87524 #define UTICK_CFG_CAPEN2(x)                      (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN2_SHIFT)) & UTICK_CFG_CAPEN2_MASK)
87525 
87526 #define UTICK_CFG_CAPEN3_MASK                    (0x8U)
87527 #define UTICK_CFG_CAPEN3_SHIFT                   (3U)
87528 /*! CAPEN3 - Enable Capture 3
87529  *  0b0..Disable
87530  *  0b1..Enable
87531  */
87532 #define UTICK_CFG_CAPEN3(x)                      (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN3_SHIFT)) & UTICK_CFG_CAPEN3_MASK)
87533 
87534 #define UTICK_CFG_CAPPOL0_MASK                   (0x100U)
87535 #define UTICK_CFG_CAPPOL0_SHIFT                  (8U)
87536 /*! CAPPOL0 - Capture Polarity 0
87537  *  0b0..Positive
87538  *  0b1..Negative
87539  */
87540 #define UTICK_CFG_CAPPOL0(x)                     (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL0_SHIFT)) & UTICK_CFG_CAPPOL0_MASK)
87541 
87542 #define UTICK_CFG_CAPPOL1_MASK                   (0x200U)
87543 #define UTICK_CFG_CAPPOL1_SHIFT                  (9U)
87544 /*! CAPPOL1 - Capture-Polarity 1
87545  *  0b0..Positive
87546  *  0b1..Negative
87547  */
87548 #define UTICK_CFG_CAPPOL1(x)                     (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL1_SHIFT)) & UTICK_CFG_CAPPOL1_MASK)
87549 
87550 #define UTICK_CFG_CAPPOL2_MASK                   (0x400U)
87551 #define UTICK_CFG_CAPPOL2_SHIFT                  (10U)
87552 /*! CAPPOL2 - Capture Polarity 2
87553  *  0b0..Positive
87554  *  0b1..Negative
87555  */
87556 #define UTICK_CFG_CAPPOL2(x)                     (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL2_SHIFT)) & UTICK_CFG_CAPPOL2_MASK)
87557 
87558 #define UTICK_CFG_CAPPOL3_MASK                   (0x800U)
87559 #define UTICK_CFG_CAPPOL3_SHIFT                  (11U)
87560 /*! CAPPOL3 - Capture Polarity 3
87561  *  0b0..Positive
87562  *  0b1..Negative
87563  */
87564 #define UTICK_CFG_CAPPOL3(x)                     (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL3_SHIFT)) & UTICK_CFG_CAPPOL3_MASK)
87565 /*! @} */
87566 
87567 /*! @name CAPCLR - Capture Clear */
87568 /*! @{ */
87569 
87570 #define UTICK_CAPCLR_CAPCLR0_MASK                (0x1U)
87571 #define UTICK_CAPCLR_CAPCLR0_SHIFT               (0U)
87572 /*! CAPCLR0 - Clear Capture 0
87573  *  0b0..Does nothing
87574  *  0b1..Clears the CAP0 register value
87575  */
87576 #define UTICK_CAPCLR_CAPCLR0(x)                  (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR0_SHIFT)) & UTICK_CAPCLR_CAPCLR0_MASK)
87577 
87578 #define UTICK_CAPCLR_CAPCLR1_MASK                (0x2U)
87579 #define UTICK_CAPCLR_CAPCLR1_SHIFT               (1U)
87580 /*! CAPCLR1 - Clear Capture 1
87581  *  0b0..Does nothing
87582  *  0b1..Clears the CAP1 register value
87583  */
87584 #define UTICK_CAPCLR_CAPCLR1(x)                  (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR1_SHIFT)) & UTICK_CAPCLR_CAPCLR1_MASK)
87585 
87586 #define UTICK_CAPCLR_CAPCLR2_MASK                (0x4U)
87587 #define UTICK_CAPCLR_CAPCLR2_SHIFT               (2U)
87588 /*! CAPCLR2 - Clear Capture 2
87589  *  0b0..Does nothing
87590  *  0b1..Clears the CAP2 register value
87591  */
87592 #define UTICK_CAPCLR_CAPCLR2(x)                  (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR2_SHIFT)) & UTICK_CAPCLR_CAPCLR2_MASK)
87593 
87594 #define UTICK_CAPCLR_CAPCLR3_MASK                (0x8U)
87595 #define UTICK_CAPCLR_CAPCLR3_SHIFT               (3U)
87596 /*! CAPCLR3 - Clear Capture 3
87597  *  0b0..Does nothing
87598  *  0b1..Clears the CAP3 register value
87599  */
87600 #define UTICK_CAPCLR_CAPCLR3(x)                  (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR3_SHIFT)) & UTICK_CAPCLR_CAPCLR3_MASK)
87601 /*! @} */
87602 
87603 /*! @name CAP - Capture */
87604 /*! @{ */
87605 
87606 #define UTICK_CAP_CAP_VALUE_MASK                 (0x7FFFFFFFU)
87607 #define UTICK_CAP_CAP_VALUE_SHIFT                (0U)
87608 /*! CAP_VALUE - Captured Value for the Related Capture Event */
87609 #define UTICK_CAP_CAP_VALUE(x)                   (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_CAP_VALUE_SHIFT)) & UTICK_CAP_CAP_VALUE_MASK)
87610 
87611 #define UTICK_CAP_VALID_MASK                     (0x80000000U)
87612 #define UTICK_CAP_VALID_SHIFT                    (31U)
87613 /*! VALID - Captured Value Valid Flag
87614  *  0b0..Valid value not captured
87615  *  0b1..Valid value captured
87616  */
87617 #define UTICK_CAP_VALID(x)                       (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_VALID_SHIFT)) & UTICK_CAP_VALID_MASK)
87618 /*! @} */
87619 
87620 /* The count of UTICK_CAP */
87621 #define UTICK_CAP_COUNT                          (4U)
87622 
87623 
87624 /*!
87625  * @}
87626  */ /* end of group UTICK_Register_Masks */
87627 
87628 
87629 /* UTICK - Peripheral instance base addresses */
87630 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
87631   /** Peripheral UTICK0 base address */
87632   #define UTICK0_BASE                              (0x50012000u)
87633   /** Peripheral UTICK0 base address */
87634   #define UTICK0_BASE_NS                           (0x40012000u)
87635   /** Peripheral UTICK0 base pointer */
87636   #define UTICK0                                   ((UTICK_Type *)UTICK0_BASE)
87637   /** Peripheral UTICK0 base pointer */
87638   #define UTICK0_NS                                ((UTICK_Type *)UTICK0_BASE_NS)
87639   /** Array initializer of UTICK peripheral base addresses */
87640   #define UTICK_BASE_ADDRS                         { UTICK0_BASE }
87641   /** Array initializer of UTICK peripheral base pointers */
87642   #define UTICK_BASE_PTRS                          { UTICK0 }
87643   /** Array initializer of UTICK peripheral base addresses */
87644   #define UTICK_BASE_ADDRS_NS                      { UTICK0_BASE_NS }
87645   /** Array initializer of UTICK peripheral base pointers */
87646   #define UTICK_BASE_PTRS_NS                       { UTICK0_NS }
87647 #else
87648   /** Peripheral UTICK0 base address */
87649   #define UTICK0_BASE                              (0x40012000u)
87650   /** Peripheral UTICK0 base pointer */
87651   #define UTICK0                                   ((UTICK_Type *)UTICK0_BASE)
87652   /** Array initializer of UTICK peripheral base addresses */
87653   #define UTICK_BASE_ADDRS                         { UTICK0_BASE }
87654   /** Array initializer of UTICK peripheral base pointers */
87655   #define UTICK_BASE_PTRS                          { UTICK0 }
87656 #endif
87657 /** Interrupt vectors for the UTICK peripheral type */
87658 #define UTICK_IRQS                               { UTICK0_IRQn }
87659 
87660 /*!
87661  * @}
87662  */ /* end of group UTICK_Peripheral_Access_Layer */
87663 
87664 
87665 /* ----------------------------------------------------------------------------
87666    -- VBAT Peripheral Access Layer
87667    ---------------------------------------------------------------------------- */
87668 
87669 /*!
87670  * @addtogroup VBAT_Peripheral_Access_Layer VBAT Peripheral Access Layer
87671  * @{
87672  */
87673 
87674 /** VBAT - Register Layout Typedef */
87675 typedef struct {
87676   __I  uint32_t VERID;                             /**< Version ID, offset: 0x0 */
87677        uint8_t RESERVED_0[12];
87678   __IO uint32_t STATUSA;                           /**< Status A, offset: 0x10 */
87679   __IO uint32_t STATUSB;                           /**< Status B, offset: 0x14 */
87680   __IO uint32_t IRQENA;                            /**< Interrupt Enable A, offset: 0x18 */
87681   __IO uint32_t IRQENB;                            /**< Interrupt Enable B, offset: 0x1C */
87682   __IO uint32_t WAKENA;                            /**< Wake-up Enable A, offset: 0x20 */
87683   __IO uint32_t WAKENB;                            /**< Wake-up Enable B, offset: 0x24 */
87684   __IO uint32_t TAMPERA;                           /**< Tamper Enable A, offset: 0x28 */
87685   __IO uint32_t TAMPERB;                           /**< Tamper Enable B, offset: 0x2C */
87686   __IO uint32_t LOCKA;                             /**< Lock A, offset: 0x30 */
87687   __IO uint32_t LOCKB;                             /**< Lock B, offset: 0x34 */
87688   __IO uint32_t WAKECFG;                           /**< Wake-up Configuration, offset: 0x38 */
87689        uint8_t RESERVED_1[196];
87690   __IO uint32_t OSCCTLA;                           /**< Oscillator Control A, offset: 0x100 */
87691   __IO uint32_t OSCCTLB;                           /**< Oscillator Control B, offset: 0x104 */
87692   __IO uint32_t OSCCFGA;                           /**< Oscillator Configuration A, offset: 0x108 */
87693   __IO uint32_t OSCCFGB;                           /**< Oscillator Configuration B, offset: 0x10C */
87694        uint8_t RESERVED_2[8];
87695   __IO uint32_t OSCLCKA;                           /**< Oscillator Lock A, offset: 0x118 */
87696   __IO uint32_t OSCLCKB;                           /**< Oscillator Lock B, offset: 0x11C */
87697   __IO uint32_t OSCCLKE;                           /**< Oscillator Clock Enable, offset: 0x120 */
87698        uint8_t RESERVED_3[220];
87699   __IO uint32_t FROCTLA;                           /**< FRO16K Control A, offset: 0x200 */
87700   __IO uint32_t FROCTLB;                           /**< FRO16K Control B, offset: 0x204 */
87701        uint8_t RESERVED_4[16];
87702   __IO uint32_t FROLCKA;                           /**< FRO16K Lock A, offset: 0x218 */
87703   __IO uint32_t FROLCKB;                           /**< FRO16K Lock B, offset: 0x21C */
87704   __IO uint32_t FROCLKE;                           /**< FRO16K Clock Enable, offset: 0x220 */
87705        uint8_t RESERVED_5[220];
87706   __IO uint32_t LDOCTLA;                           /**< LDO_RAM Control A, offset: 0x300 */
87707   __IO uint32_t LDOCTLB;                           /**< LDO_RAM Control B, offset: 0x304 */
87708        uint8_t RESERVED_6[16];
87709   __IO uint32_t LDOLCKA;                           /**< LDO_RAM Lock A, offset: 0x318 */
87710   __IO uint32_t LDOLCKB;                           /**< LDO_RAM Lock B, offset: 0x31C */
87711   __IO uint32_t LDORAMC;                           /**< RAM Control, offset: 0x320 */
87712        uint8_t RESERVED_7[12];
87713   __IO uint32_t LDOTIMER0;                         /**< Bandgap Timer 0, offset: 0x330 */
87714        uint8_t RESERVED_8[4];
87715   __IO uint32_t LDOTIMER1;                         /**< Bandgap Timer 1, offset: 0x338 */
87716        uint8_t RESERVED_9[196];
87717   __IO uint32_t MONCTLA;                           /**< CLKMON Control A, offset: 0x400 */
87718   __IO uint32_t MONCTLB;                           /**< CLKMON Control B, offset: 0x404 */
87719   __IO uint32_t MONCFGA;                           /**< CLKMON Configuration A, offset: 0x408 */
87720   __IO uint32_t MONCFGB;                           /**< CLKMON Configuration B, offset: 0x40C */
87721        uint8_t RESERVED_10[8];
87722   __IO uint32_t MONLCKA;                           /**< CLKMON Lock A, offset: 0x418 */
87723   __IO uint32_t MONLCKB;                           /**< CLKMON Lock B, offset: 0x41C */
87724        uint8_t RESERVED_11[224];
87725   __IO uint32_t TAMCTLA;                           /**< TAMPER Control A, offset: 0x500 */
87726   __IO uint32_t TAMCTLB;                           /**< TAMPER Control B, offset: 0x504 */
87727        uint8_t RESERVED_12[16];
87728   __IO uint32_t TAMLCKA;                           /**< TAMPER Lock A, offset: 0x518 */
87729   __IO uint32_t TAMLCKB;                           /**< TAMPER Lock B, offset: 0x51C */
87730        uint8_t RESERVED_13[224];
87731   __IO uint32_t SWICTLA;                           /**< Switch Control A, offset: 0x600 */
87732   __IO uint32_t SWICTLB;                           /**< Switch Control B, offset: 0x604 */
87733        uint8_t RESERVED_14[16];
87734   __IO uint32_t SWILCKA;                           /**< Switch Lock A, offset: 0x618 */
87735   __IO uint32_t SWILCKB;                           /**< Switch Lock B, offset: 0x61C */
87736        uint8_t RESERVED_15[224];
87737   struct {                                         /* offset: 0x700, array step: 0x8 */
87738     __IO uint32_t WAKEUPA;                           /**< Wakeup 0 Register A, array offset: 0x700, array step: 0x8 */
87739     __IO uint32_t WAKEUPB;                           /**< Wakeup 0 Register B, array offset: 0x704, array step: 0x8 */
87740   } WAKEUP[2];
87741        uint8_t RESERVED_16[232];
87742   __IO uint32_t WAKLCKA;                           /**< Wakeup Lock A, offset: 0x7F8 */
87743   __IO uint32_t WAKLCKB;                           /**< Wakeup Lock B, offset: 0x7FC */
87744 } VBAT_Type;
87745 
87746 /* ----------------------------------------------------------------------------
87747    -- VBAT Register Masks
87748    ---------------------------------------------------------------------------- */
87749 
87750 /*!
87751  * @addtogroup VBAT_Register_Masks VBAT Register Masks
87752  * @{
87753  */
87754 
87755 /*! @name VERID - Version ID */
87756 /*! @{ */
87757 
87758 #define VBAT_VERID_FEATURE_MASK                  (0xFFFFU)
87759 #define VBAT_VERID_FEATURE_SHIFT                 (0U)
87760 /*! FEATURE - Feature Specification Number */
87761 #define VBAT_VERID_FEATURE(x)                    (((uint32_t)(((uint32_t)(x)) << VBAT_VERID_FEATURE_SHIFT)) & VBAT_VERID_FEATURE_MASK)
87762 
87763 #define VBAT_VERID_MINOR_MASK                    (0xFF0000U)
87764 #define VBAT_VERID_MINOR_SHIFT                   (16U)
87765 /*! MINOR - Minor Version Number */
87766 #define VBAT_VERID_MINOR(x)                      (((uint32_t)(((uint32_t)(x)) << VBAT_VERID_MINOR_SHIFT)) & VBAT_VERID_MINOR_MASK)
87767 
87768 #define VBAT_VERID_MAJOR_MASK                    (0xFF000000U)
87769 #define VBAT_VERID_MAJOR_SHIFT                   (24U)
87770 /*! MAJOR - Major Version Number */
87771 #define VBAT_VERID_MAJOR(x)                      (((uint32_t)(((uint32_t)(x)) << VBAT_VERID_MAJOR_SHIFT)) & VBAT_VERID_MAJOR_MASK)
87772 /*! @} */
87773 
87774 /*! @name STATUSA - Status A */
87775 /*! @{ */
87776 
87777 #define VBAT_STATUSA_POR_DET_MASK                (0x1U)
87778 #define VBAT_STATUSA_POR_DET_SHIFT               (0U)
87779 /*! POR_DET - POR Detect Flag
87780  *  0b0..Not reset
87781  *  0b1..Reset
87782  *  0b0..No effect
87783  *  0b1..Clear the flag
87784  */
87785 #define VBAT_STATUSA_POR_DET(x)                  (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_POR_DET_SHIFT)) & VBAT_STATUSA_POR_DET_MASK)
87786 
87787 #define VBAT_STATUSA_WAKEUP_FLAG_MASK            (0x2U)
87788 #define VBAT_STATUSA_WAKEUP_FLAG_SHIFT           (1U)
87789 /*! WAKEUP_FLAG - Wakeup Pin Flag
87790  *  0b0..Not asserted
87791  *  0b1..Asserted
87792  *  0b0..No effect
87793  *  0b1..Clear the flag
87794  */
87795 #define VBAT_STATUSA_WAKEUP_FLAG(x)              (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_WAKEUP_FLAG_SHIFT)) & VBAT_STATUSA_WAKEUP_FLAG_MASK)
87796 
87797 #define VBAT_STATUSA_TIMER0_FLAG_MASK            (0x4U)
87798 #define VBAT_STATUSA_TIMER0_FLAG_SHIFT           (2U)
87799 /*! TIMER0_FLAG - Bandgap Timer 0 Flag
87800  *  0b0..Not reached
87801  *  0b1..Reached
87802  *  0b0..No effect
87803  *  0b1..Clear the flag
87804  */
87805 #define VBAT_STATUSA_TIMER0_FLAG(x)              (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_TIMER0_FLAG_SHIFT)) & VBAT_STATUSA_TIMER0_FLAG_MASK)
87806 
87807 #define VBAT_STATUSA_TIMER1_FLAG_MASK            (0x8U)
87808 #define VBAT_STATUSA_TIMER1_FLAG_SHIFT           (3U)
87809 /*! TIMER1_FLAG - Bandgap Timer 1 Flag
87810  *  0b0..Not reached
87811  *  0b1..Reached
87812  *  0b0..No effect
87813  *  0b1..Clear the flag
87814  */
87815 #define VBAT_STATUSA_TIMER1_FLAG(x)              (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_TIMER1_FLAG_SHIFT)) & VBAT_STATUSA_TIMER1_FLAG_MASK)
87816 
87817 #define VBAT_STATUSA_LDO_RDY_MASK                (0x10U)
87818 #define VBAT_STATUSA_LDO_RDY_SHIFT               (4U)
87819 /*! LDO_RDY - LDO Ready
87820  *  0b0..Disabled (not ready)
87821  *  0b1..Enabled (ready)
87822  */
87823 #define VBAT_STATUSA_LDO_RDY(x)                  (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_LDO_RDY_SHIFT)) & VBAT_STATUSA_LDO_RDY_MASK)
87824 
87825 #define VBAT_STATUSA_OSC_RDY_MASK                (0x20U)
87826 #define VBAT_STATUSA_OSC_RDY_SHIFT               (5U)
87827 /*! OSC_RDY - OSC32k Ready
87828  *  0b0..Disabled (clock not ready)
87829  *  0b1..Enabled (clock ready)
87830  */
87831 #define VBAT_STATUSA_OSC_RDY(x)                  (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_OSC_RDY_SHIFT)) & VBAT_STATUSA_OSC_RDY_MASK)
87832 
87833 #define VBAT_STATUSA_CLOCK_DET_MASK              (0x40U)
87834 #define VBAT_STATUSA_CLOCK_DET_SHIFT             (6U)
87835 /*! CLOCK_DET - Clock Detect
87836  *  0b0..Clock error not detected
87837  *  0b1..Clock error detected
87838  */
87839 #define VBAT_STATUSA_CLOCK_DET(x)                (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_CLOCK_DET_SHIFT)) & VBAT_STATUSA_CLOCK_DET_MASK)
87840 
87841 #define VBAT_STATUSA_CONFIG_DET_MASK             (0x80U)
87842 #define VBAT_STATUSA_CONFIG_DET_SHIFT            (7U)
87843 /*! CONFIG_DET - Configuration Detect Flag
87844  *  0b0..Not detected
87845  *  0b1..Detected
87846  *  0b0..No effect
87847  *  0b1..Clear the flag
87848  */
87849 #define VBAT_STATUSA_CONFIG_DET(x)               (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_CONFIG_DET_SHIFT)) & VBAT_STATUSA_CONFIG_DET_MASK)
87850 
87851 #define VBAT_STATUSA_VOLT_DET_MASK               (0x100U)
87852 #define VBAT_STATUSA_VOLT_DET_SHIFT              (8U)
87853 /*! VOLT_DET - Voltage Detect
87854  *  0b0..Not detected
87855  *  0b1..Detected
87856  *  0b0..No effect
87857  *  0b1..Clear the flag
87858  */
87859 #define VBAT_STATUSA_VOLT_DET(x)                 (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_VOLT_DET_SHIFT)) & VBAT_STATUSA_VOLT_DET_MASK)
87860 
87861 #define VBAT_STATUSA_TEMP_DET_MASK               (0x200U)
87862 #define VBAT_STATUSA_TEMP_DET_SHIFT              (9U)
87863 /*! TEMP_DET - Temperature Detect
87864  *  0b0..Temperature error not detected
87865  *  0b1..Temperature error detected
87866  */
87867 #define VBAT_STATUSA_TEMP_DET(x)                 (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_TEMP_DET_SHIFT)) & VBAT_STATUSA_TEMP_DET_MASK)
87868 
87869 #define VBAT_STATUSA_LIGHT_DET_MASK              (0x400U)
87870 #define VBAT_STATUSA_LIGHT_DET_SHIFT             (10U)
87871 /*! LIGHT_DET - Light Detect
87872  *  0b0..Light error not detected
87873  *  0b1..Light error detected
87874  */
87875 #define VBAT_STATUSA_LIGHT_DET(x)                (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_LIGHT_DET_SHIFT)) & VBAT_STATUSA_LIGHT_DET_MASK)
87876 
87877 #define VBAT_STATUSA_SEC0_DET_MASK               (0x1000U)
87878 #define VBAT_STATUSA_SEC0_DET_SHIFT              (12U)
87879 /*! SEC0_DET - Input 0 Detect
87880  *  0b0..Security input 0 not detected
87881  *  0b1..Security input 0 detected
87882  */
87883 #define VBAT_STATUSA_SEC0_DET(x)                 (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_SEC0_DET_SHIFT)) & VBAT_STATUSA_SEC0_DET_MASK)
87884 
87885 #define VBAT_STATUSA_IRQ0_DET_MASK               (0x10000U)
87886 #define VBAT_STATUSA_IRQ0_DET_SHIFT              (16U)
87887 /*! IRQ0_DET - Interrupt 0 Detect
87888  *  0b0..Not asserted
87889  *  0b1..Asserted
87890  */
87891 #define VBAT_STATUSA_IRQ0_DET(x)                 (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_IRQ0_DET_SHIFT)) & VBAT_STATUSA_IRQ0_DET_MASK)
87892 
87893 #define VBAT_STATUSA_IRQ1_DET_MASK               (0x20000U)
87894 #define VBAT_STATUSA_IRQ1_DET_SHIFT              (17U)
87895 /*! IRQ1_DET - Interrupt 1 Detect
87896  *  0b0..Not asserted
87897  *  0b1..Asserted
87898  */
87899 #define VBAT_STATUSA_IRQ1_DET(x)                 (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_IRQ1_DET_SHIFT)) & VBAT_STATUSA_IRQ1_DET_MASK)
87900 
87901 #define VBAT_STATUSA_IRQ2_DET_MASK               (0x40000U)
87902 #define VBAT_STATUSA_IRQ2_DET_SHIFT              (18U)
87903 /*! IRQ2_DET - Interrupt 2 Detect
87904  *  0b0..Not asserted
87905  *  0b1..Asserted
87906  */
87907 #define VBAT_STATUSA_IRQ2_DET(x)                 (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_IRQ2_DET_SHIFT)) & VBAT_STATUSA_IRQ2_DET_MASK)
87908 
87909 #define VBAT_STATUSA_IRQ3_DET_MASK               (0x80000U)
87910 #define VBAT_STATUSA_IRQ3_DET_SHIFT              (19U)
87911 /*! IRQ3_DET - Interrupt 3 Detect
87912  *  0b0..Not asserted
87913  *  0b1..Asserted
87914  */
87915 #define VBAT_STATUSA_IRQ3_DET(x)                 (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_IRQ3_DET_SHIFT)) & VBAT_STATUSA_IRQ3_DET_MASK)
87916 /*! @} */
87917 
87918 /*! @name STATUSB - Status B */
87919 /*! @{ */
87920 
87921 #define VBAT_STATUSB_INVERSE_MASK                (0xFFFFFU)
87922 #define VBAT_STATUSB_INVERSE_SHIFT               (0U)
87923 /*! INVERSE - Inverse value */
87924 #define VBAT_STATUSB_INVERSE(x)                  (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSB_INVERSE_SHIFT)) & VBAT_STATUSB_INVERSE_MASK)
87925 /*! @} */
87926 
87927 /*! @name IRQENA - Interrupt Enable A */
87928 /*! @{ */
87929 
87930 #define VBAT_IRQENA_POR_DET_MASK                 (0x1U)
87931 #define VBAT_IRQENA_POR_DET_SHIFT                (0U)
87932 /*! POR_DET - POR Detect
87933  *  0b0..Disable
87934  *  0b1..Enable
87935  */
87936 #define VBAT_IRQENA_POR_DET(x)                   (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_POR_DET_SHIFT)) & VBAT_IRQENA_POR_DET_MASK)
87937 
87938 #define VBAT_IRQENA_WAKEUP_FLAG_MASK             (0x2U)
87939 #define VBAT_IRQENA_WAKEUP_FLAG_SHIFT            (1U)
87940 /*! WAKEUP_FLAG - Wakeup Pin Flag
87941  *  0b0..Disable
87942  *  0b1..Enable
87943  */
87944 #define VBAT_IRQENA_WAKEUP_FLAG(x)               (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_WAKEUP_FLAG_SHIFT)) & VBAT_IRQENA_WAKEUP_FLAG_MASK)
87945 
87946 #define VBAT_IRQENA_TIMER0_FLAG_MASK             (0x4U)
87947 #define VBAT_IRQENA_TIMER0_FLAG_SHIFT            (2U)
87948 /*! TIMER0_FLAG - Bandgap Timer 0
87949  *  0b0..Disable
87950  *  0b1..Enable
87951  */
87952 #define VBAT_IRQENA_TIMER0_FLAG(x)               (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_TIMER0_FLAG_SHIFT)) & VBAT_IRQENA_TIMER0_FLAG_MASK)
87953 
87954 #define VBAT_IRQENA_TIMER1_FLAG_MASK             (0x8U)
87955 #define VBAT_IRQENA_TIMER1_FLAG_SHIFT            (3U)
87956 /*! TIMER1_FLAG - Bandgap Timer 2
87957  *  0b0..Disable
87958  *  0b1..Enable
87959  */
87960 #define VBAT_IRQENA_TIMER1_FLAG(x)               (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_TIMER1_FLAG_SHIFT)) & VBAT_IRQENA_TIMER1_FLAG_MASK)
87961 
87962 #define VBAT_IRQENA_LDO_RDY_MASK                 (0x10U)
87963 #define VBAT_IRQENA_LDO_RDY_SHIFT                (4U)
87964 /*! LDO_RDY - LDO Ready
87965  *  0b0..Disable
87966  *  0b1..Enable
87967  */
87968 #define VBAT_IRQENA_LDO_RDY(x)                   (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_LDO_RDY_SHIFT)) & VBAT_IRQENA_LDO_RDY_MASK)
87969 
87970 #define VBAT_IRQENA_OSC_RDY_MASK                 (0x20U)
87971 #define VBAT_IRQENA_OSC_RDY_SHIFT                (5U)
87972 /*! OSC_RDY - OSC32k Ready
87973  *  0b0..Disable
87974  *  0b1..Enable
87975  */
87976 #define VBAT_IRQENA_OSC_RDY(x)                   (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_OSC_RDY_SHIFT)) & VBAT_IRQENA_OSC_RDY_MASK)
87977 
87978 #define VBAT_IRQENA_CLOCK_DET_MASK               (0x40U)
87979 #define VBAT_IRQENA_CLOCK_DET_SHIFT              (6U)
87980 /*! CLOCK_DET - Clock Detect
87981  *  0b0..Disable
87982  *  0b1..Enable
87983  */
87984 #define VBAT_IRQENA_CLOCK_DET(x)                 (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_CLOCK_DET_SHIFT)) & VBAT_IRQENA_CLOCK_DET_MASK)
87985 
87986 #define VBAT_IRQENA_CONFIG_DET_MASK              (0x80U)
87987 #define VBAT_IRQENA_CONFIG_DET_SHIFT             (7U)
87988 /*! CONFIG_DET - Configuration Detect
87989  *  0b0..Disable
87990  *  0b1..Enable
87991  */
87992 #define VBAT_IRQENA_CONFIG_DET(x)                (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_CONFIG_DET_SHIFT)) & VBAT_IRQENA_CONFIG_DET_MASK)
87993 
87994 #define VBAT_IRQENA_VOLT_DET_MASK                (0x100U)
87995 #define VBAT_IRQENA_VOLT_DET_SHIFT               (8U)
87996 /*! VOLT_DET - Voltage Detect
87997  *  0b0..Disable
87998  *  0b1..Enable
87999  */
88000 #define VBAT_IRQENA_VOLT_DET(x)                  (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_VOLT_DET_SHIFT)) & VBAT_IRQENA_VOLT_DET_MASK)
88001 
88002 #define VBAT_IRQENA_TEMP_DET_MASK                (0x200U)
88003 #define VBAT_IRQENA_TEMP_DET_SHIFT               (9U)
88004 /*! TEMP_DET - Temperature Detect
88005  *  0b0..Interrupt disabled
88006  *  0b1..Interrupt enabled
88007  */
88008 #define VBAT_IRQENA_TEMP_DET(x)                  (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_TEMP_DET_SHIFT)) & VBAT_IRQENA_TEMP_DET_MASK)
88009 
88010 #define VBAT_IRQENA_LIGHT_DET_MASK               (0x400U)
88011 #define VBAT_IRQENA_LIGHT_DET_SHIFT              (10U)
88012 /*! LIGHT_DET - Light Detect
88013  *  0b0..Disable
88014  *  0b1..Enable
88015  */
88016 #define VBAT_IRQENA_LIGHT_DET(x)                 (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_LIGHT_DET_SHIFT)) & VBAT_IRQENA_LIGHT_DET_MASK)
88017 
88018 #define VBAT_IRQENA_SEC0_DET_MASK                (0x1000U)
88019 #define VBAT_IRQENA_SEC0_DET_SHIFT               (12U)
88020 /*! SEC0_DET - Input 0 Detect
88021  *  0b0..Disable
88022  *  0b1..Enable
88023  */
88024 #define VBAT_IRQENA_SEC0_DET(x)                  (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_SEC0_DET_SHIFT)) & VBAT_IRQENA_SEC0_DET_MASK)
88025 
88026 #define VBAT_IRQENA_IRQ0_DET_MASK                (0x10000U)
88027 #define VBAT_IRQENA_IRQ0_DET_SHIFT               (16U)
88028 /*! IRQ0_DET - Interrupt 0 Detect
88029  *  0b0..Disable
88030  *  0b1..Enable
88031  */
88032 #define VBAT_IRQENA_IRQ0_DET(x)                  (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_IRQ0_DET_SHIFT)) & VBAT_IRQENA_IRQ0_DET_MASK)
88033 
88034 #define VBAT_IRQENA_IRQ1_DET_MASK                (0x20000U)
88035 #define VBAT_IRQENA_IRQ1_DET_SHIFT               (17U)
88036 /*! IRQ1_DET - Interrupt 1 Detect
88037  *  0b0..Disable
88038  *  0b1..Enable
88039  */
88040 #define VBAT_IRQENA_IRQ1_DET(x)                  (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_IRQ1_DET_SHIFT)) & VBAT_IRQENA_IRQ1_DET_MASK)
88041 
88042 #define VBAT_IRQENA_IRQ2_DET_MASK                (0x40000U)
88043 #define VBAT_IRQENA_IRQ2_DET_SHIFT               (18U)
88044 /*! IRQ2_DET - Interrupt 2 Detect
88045  *  0b0..Disable
88046  *  0b1..Enable
88047  */
88048 #define VBAT_IRQENA_IRQ2_DET(x)                  (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_IRQ2_DET_SHIFT)) & VBAT_IRQENA_IRQ2_DET_MASK)
88049 
88050 #define VBAT_IRQENA_IRQ3_DET_MASK                (0x80000U)
88051 #define VBAT_IRQENA_IRQ3_DET_SHIFT               (19U)
88052 /*! IRQ3_DET - Interrupt 3 Detect
88053  *  0b0..Disable
88054  *  0b1..Enable
88055  */
88056 #define VBAT_IRQENA_IRQ3_DET(x)                  (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_IRQ3_DET_SHIFT)) & VBAT_IRQENA_IRQ3_DET_MASK)
88057 /*! @} */
88058 
88059 /*! @name IRQENB - Interrupt Enable B */
88060 /*! @{ */
88061 
88062 #define VBAT_IRQENB_INVERSE_MASK                 (0xFFFFFU)
88063 #define VBAT_IRQENB_INVERSE_SHIFT                (0U)
88064 /*! INVERSE - Inverse Value */
88065 #define VBAT_IRQENB_INVERSE(x)                   (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENB_INVERSE_SHIFT)) & VBAT_IRQENB_INVERSE_MASK)
88066 /*! @} */
88067 
88068 /*! @name WAKENA - Wake-up Enable A */
88069 /*! @{ */
88070 
88071 #define VBAT_WAKENA_POR_DET_MASK                 (0x1U)
88072 #define VBAT_WAKENA_POR_DET_SHIFT                (0U)
88073 /*! POR_DET - POR Detect
88074  *  0b0..Disable
88075  *  0b1..Enable
88076  */
88077 #define VBAT_WAKENA_POR_DET(x)                   (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_POR_DET_SHIFT)) & VBAT_WAKENA_POR_DET_MASK)
88078 
88079 #define VBAT_WAKENA_WAKEUP_FLAG_MASK             (0x2U)
88080 #define VBAT_WAKENA_WAKEUP_FLAG_SHIFT            (1U)
88081 /*! WAKEUP_FLAG - Wake-up Pin Flag
88082  *  0b0..Disable
88083  *  0b1..Enable
88084  */
88085 #define VBAT_WAKENA_WAKEUP_FLAG(x)               (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_WAKEUP_FLAG_SHIFT)) & VBAT_WAKENA_WAKEUP_FLAG_MASK)
88086 
88087 #define VBAT_WAKENA_TIMER0_FLAG_MASK             (0x4U)
88088 #define VBAT_WAKENA_TIMER0_FLAG_SHIFT            (2U)
88089 /*! TIMER0_FLAG - Bandgap Timer 0
88090  *  0b0..Disable
88091  *  0b1..Enable
88092  */
88093 #define VBAT_WAKENA_TIMER0_FLAG(x)               (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_TIMER0_FLAG_SHIFT)) & VBAT_WAKENA_TIMER0_FLAG_MASK)
88094 
88095 #define VBAT_WAKENA_TIMER1_FLAG_MASK             (0x8U)
88096 #define VBAT_WAKENA_TIMER1_FLAG_SHIFT            (3U)
88097 /*! TIMER1_FLAG - Bandgap Timer 2
88098  *  0b0..Disable
88099  *  0b1..Enable
88100  */
88101 #define VBAT_WAKENA_TIMER1_FLAG(x)               (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_TIMER1_FLAG_SHIFT)) & VBAT_WAKENA_TIMER1_FLAG_MASK)
88102 
88103 #define VBAT_WAKENA_LDO_RDY_MASK                 (0x10U)
88104 #define VBAT_WAKENA_LDO_RDY_SHIFT                (4U)
88105 /*! LDO_RDY - LDO Ready
88106  *  0b0..Disable
88107  *  0b1..Enable
88108  */
88109 #define VBAT_WAKENA_LDO_RDY(x)                   (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_LDO_RDY_SHIFT)) & VBAT_WAKENA_LDO_RDY_MASK)
88110 
88111 #define VBAT_WAKENA_OSC_RDY_MASK                 (0x20U)
88112 #define VBAT_WAKENA_OSC_RDY_SHIFT                (5U)
88113 /*! OSC_RDY - OSC32K Ready
88114  *  0b0..Disable
88115  *  0b1..Enable
88116  */
88117 #define VBAT_WAKENA_OSC_RDY(x)                   (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_OSC_RDY_SHIFT)) & VBAT_WAKENA_OSC_RDY_MASK)
88118 
88119 #define VBAT_WAKENA_CLOCK_DET_MASK               (0x40U)
88120 #define VBAT_WAKENA_CLOCK_DET_SHIFT              (6U)
88121 /*! CLOCK_DET - Clock Detect
88122  *  0b0..Disable
88123  *  0b1..Enable
88124  */
88125 #define VBAT_WAKENA_CLOCK_DET(x)                 (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_CLOCK_DET_SHIFT)) & VBAT_WAKENA_CLOCK_DET_MASK)
88126 
88127 #define VBAT_WAKENA_CONFIG_DET_MASK              (0x80U)
88128 #define VBAT_WAKENA_CONFIG_DET_SHIFT             (7U)
88129 /*! CONFIG_DET - Configuration Detect
88130  *  0b0..Disable
88131  *  0b1..Enable
88132  */
88133 #define VBAT_WAKENA_CONFIG_DET(x)                (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_CONFIG_DET_SHIFT)) & VBAT_WAKENA_CONFIG_DET_MASK)
88134 
88135 #define VBAT_WAKENA_VOLT_DET_MASK                (0x100U)
88136 #define VBAT_WAKENA_VOLT_DET_SHIFT               (8U)
88137 /*! VOLT_DET - Voltage Detect
88138  *  0b0..Disable
88139  *  0b1..Enable
88140  */
88141 #define VBAT_WAKENA_VOLT_DET(x)                  (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_VOLT_DET_SHIFT)) & VBAT_WAKENA_VOLT_DET_MASK)
88142 
88143 #define VBAT_WAKENA_TEMP_DET_MASK                (0x200U)
88144 #define VBAT_WAKENA_TEMP_DET_SHIFT               (9U)
88145 /*! TEMP_DET - Temperature Detect
88146  *  0b0..Disable
88147  *  0b1..Enable
88148  */
88149 #define VBAT_WAKENA_TEMP_DET(x)                  (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_TEMP_DET_SHIFT)) & VBAT_WAKENA_TEMP_DET_MASK)
88150 
88151 #define VBAT_WAKENA_LIGHT_DET_MASK               (0x400U)
88152 #define VBAT_WAKENA_LIGHT_DET_SHIFT              (10U)
88153 /*! LIGHT_DET - Light Detect
88154  *  0b0..Disable
88155  *  0b1..Enable
88156  */
88157 #define VBAT_WAKENA_LIGHT_DET(x)                 (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_LIGHT_DET_SHIFT)) & VBAT_WAKENA_LIGHT_DET_MASK)
88158 
88159 #define VBAT_WAKENA_SEC0_DET_MASK                (0x1000U)
88160 #define VBAT_WAKENA_SEC0_DET_SHIFT               (12U)
88161 /*! SEC0_DET - Input 0 Detect
88162  *  0b0..Disabled
88163  *  0b1..Enabled
88164  */
88165 #define VBAT_WAKENA_SEC0_DET(x)                  (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_SEC0_DET_SHIFT)) & VBAT_WAKENA_SEC0_DET_MASK)
88166 
88167 #define VBAT_WAKENA_IRQ0_DET_MASK                (0x10000U)
88168 #define VBAT_WAKENA_IRQ0_DET_SHIFT               (16U)
88169 /*! IRQ0_DET - Interrupt 0 Detect
88170  *  0b0..Disable
88171  *  0b1..Enable
88172  */
88173 #define VBAT_WAKENA_IRQ0_DET(x)                  (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_IRQ0_DET_SHIFT)) & VBAT_WAKENA_IRQ0_DET_MASK)
88174 
88175 #define VBAT_WAKENA_IRQ1_DET_MASK                (0x20000U)
88176 #define VBAT_WAKENA_IRQ1_DET_SHIFT               (17U)
88177 /*! IRQ1_DET - Interrupt 1 Detect
88178  *  0b0..Disable
88179  *  0b1..Enable
88180  */
88181 #define VBAT_WAKENA_IRQ1_DET(x)                  (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_IRQ1_DET_SHIFT)) & VBAT_WAKENA_IRQ1_DET_MASK)
88182 
88183 #define VBAT_WAKENA_IRQ2_DET_MASK                (0x40000U)
88184 #define VBAT_WAKENA_IRQ2_DET_SHIFT               (18U)
88185 /*! IRQ2_DET - Interrupt 2 Detect
88186  *  0b0..Disable
88187  *  0b1..Enable
88188  */
88189 #define VBAT_WAKENA_IRQ2_DET(x)                  (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_IRQ2_DET_SHIFT)) & VBAT_WAKENA_IRQ2_DET_MASK)
88190 
88191 #define VBAT_WAKENA_IRQ3_DET_MASK                (0x80000U)
88192 #define VBAT_WAKENA_IRQ3_DET_SHIFT               (19U)
88193 /*! IRQ3_DET - Interrupt 3 Detect
88194  *  0b0..Disable
88195  *  0b1..Enable
88196  */
88197 #define VBAT_WAKENA_IRQ3_DET(x)                  (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_IRQ3_DET_SHIFT)) & VBAT_WAKENA_IRQ3_DET_MASK)
88198 /*! @} */
88199 
88200 /*! @name WAKENB - Wake-up Enable B */
88201 /*! @{ */
88202 
88203 #define VBAT_WAKENB_INVERSE_MASK                 (0xFFFFFU)
88204 #define VBAT_WAKENB_INVERSE_SHIFT                (0U)
88205 /*! INVERSE - Inverse Value */
88206 #define VBAT_WAKENB_INVERSE(x)                   (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENB_INVERSE_SHIFT)) & VBAT_WAKENB_INVERSE_MASK)
88207 /*! @} */
88208 
88209 /*! @name TAMPERA - Tamper Enable A */
88210 /*! @{ */
88211 
88212 #define VBAT_TAMPERA_POR_DET_MASK                (0x1U)
88213 #define VBAT_TAMPERA_POR_DET_SHIFT               (0U)
88214 /*! POR_DET - POR Detect
88215  *  0b0..Tamper disabled
88216  *  0b1..Tamper enabled
88217  */
88218 #define VBAT_TAMPERA_POR_DET(x)                  (((uint32_t)(((uint32_t)(x)) << VBAT_TAMPERA_POR_DET_SHIFT)) & VBAT_TAMPERA_POR_DET_MASK)
88219 
88220 #define VBAT_TAMPERA_CLOCK_DET_MASK              (0x40U)
88221 #define VBAT_TAMPERA_CLOCK_DET_SHIFT             (6U)
88222 /*! CLOCK_DET - Clock Detect
88223  *  0b0..Tamper disabled
88224  *  0b1..Tamper enabled
88225  */
88226 #define VBAT_TAMPERA_CLOCK_DET(x)                (((uint32_t)(((uint32_t)(x)) << VBAT_TAMPERA_CLOCK_DET_SHIFT)) & VBAT_TAMPERA_CLOCK_DET_MASK)
88227 
88228 #define VBAT_TAMPERA_CONFIG_DET_MASK             (0x80U)
88229 #define VBAT_TAMPERA_CONFIG_DET_SHIFT            (7U)
88230 /*! CONFIG_DET - Configuration Detect
88231  *  0b0..Tamper disabled
88232  *  0b1..Tamper enabled
88233  */
88234 #define VBAT_TAMPERA_CONFIG_DET(x)               (((uint32_t)(((uint32_t)(x)) << VBAT_TAMPERA_CONFIG_DET_SHIFT)) & VBAT_TAMPERA_CONFIG_DET_MASK)
88235 
88236 #define VBAT_TAMPERA_VOLT_DET_MASK               (0x100U)
88237 #define VBAT_TAMPERA_VOLT_DET_SHIFT              (8U)
88238 /*! VOLT_DET - Voltage Detect
88239  *  0b0..Tamper disabled
88240  *  0b1..Tamper enabled
88241  */
88242 #define VBAT_TAMPERA_VOLT_DET(x)                 (((uint32_t)(((uint32_t)(x)) << VBAT_TAMPERA_VOLT_DET_SHIFT)) & VBAT_TAMPERA_VOLT_DET_MASK)
88243 
88244 #define VBAT_TAMPERA_TEMP_DET_MASK               (0x200U)
88245 #define VBAT_TAMPERA_TEMP_DET_SHIFT              (9U)
88246 /*! TEMP_DET - Temperature Detect
88247  *  0b0..Tamper disabled
88248  *  0b1..Tamper enabled
88249  */
88250 #define VBAT_TAMPERA_TEMP_DET(x)                 (((uint32_t)(((uint32_t)(x)) << VBAT_TAMPERA_TEMP_DET_SHIFT)) & VBAT_TAMPERA_TEMP_DET_MASK)
88251 
88252 #define VBAT_TAMPERA_LIGHT_DET_MASK              (0x400U)
88253 #define VBAT_TAMPERA_LIGHT_DET_SHIFT             (10U)
88254 /*! LIGHT_DET - Light Detect
88255  *  0b0..Tamper disabled
88256  *  0b1..Tamper enabled
88257  */
88258 #define VBAT_TAMPERA_LIGHT_DET(x)                (((uint32_t)(((uint32_t)(x)) << VBAT_TAMPERA_LIGHT_DET_SHIFT)) & VBAT_TAMPERA_LIGHT_DET_MASK)
88259 
88260 #define VBAT_TAMPERA_SEC0_DET_MASK               (0x1000U)
88261 #define VBAT_TAMPERA_SEC0_DET_SHIFT              (12U)
88262 /*! SEC0_DET - Input 0 Detect
88263  *  0b0..Tamper disabled
88264  *  0b1..Tamper enabled
88265  */
88266 #define VBAT_TAMPERA_SEC0_DET(x)                 (((uint32_t)(((uint32_t)(x)) << VBAT_TAMPERA_SEC0_DET_SHIFT)) & VBAT_TAMPERA_SEC0_DET_MASK)
88267 /*! @} */
88268 
88269 /*! @name TAMPERB - Tamper Enable B */
88270 /*! @{ */
88271 
88272 #define VBAT_TAMPERB_INVERSE_MASK                (0xFFFFU)
88273 #define VBAT_TAMPERB_INVERSE_SHIFT               (0U)
88274 /*! INVERSE - Inverse value */
88275 #define VBAT_TAMPERB_INVERSE(x)                  (((uint32_t)(((uint32_t)(x)) << VBAT_TAMPERB_INVERSE_SHIFT)) & VBAT_TAMPERB_INVERSE_MASK)
88276 /*! @} */
88277 
88278 /*! @name LOCKA - Lock A */
88279 /*! @{ */
88280 
88281 #define VBAT_LOCKA_LOCK_MASK                     (0x1U)
88282 #define VBAT_LOCKA_LOCK_SHIFT                    (0U)
88283 /*! LOCK - Lock
88284  *  0b0..Disables lock
88285  *  0b1..Enables lock. Cleared by VBAT POR.
88286  */
88287 #define VBAT_LOCKA_LOCK(x)                       (((uint32_t)(((uint32_t)(x)) << VBAT_LOCKA_LOCK_SHIFT)) & VBAT_LOCKA_LOCK_MASK)
88288 /*! @} */
88289 
88290 /*! @name LOCKB - Lock B */
88291 /*! @{ */
88292 
88293 #define VBAT_LOCKB_LOCK_MASK                     (0x1U)
88294 #define VBAT_LOCKB_LOCK_SHIFT                    (0U)
88295 /*! LOCK - Lock
88296  *  0b1..Disables lock
88297  *  0b0..Enables lock
88298  */
88299 #define VBAT_LOCKB_LOCK(x)                       (((uint32_t)(((uint32_t)(x)) << VBAT_LOCKB_LOCK_SHIFT)) & VBAT_LOCKB_LOCK_MASK)
88300 /*! @} */
88301 
88302 /*! @name WAKECFG - Wake-up Configuration */
88303 /*! @{ */
88304 
88305 #define VBAT_WAKECFG_OUT_MASK                    (0x1U)
88306 #define VBAT_WAKECFG_OUT_SHIFT                   (0U)
88307 /*! OUT - Output
88308  *  0b0..Logic zero (asserted)
88309  *  0b1..Logic one
88310  */
88311 #define VBAT_WAKECFG_OUT(x)                      (((uint32_t)(((uint32_t)(x)) << VBAT_WAKECFG_OUT_SHIFT)) & VBAT_WAKECFG_OUT_MASK)
88312 /*! @} */
88313 
88314 /*! @name OSCCTLA - Oscillator Control A */
88315 /*! @{ */
88316 
88317 #define VBAT_OSCCTLA_OSC_EN_MASK                 (0x1U)
88318 #define VBAT_OSCCTLA_OSC_EN_SHIFT                (0U)
88319 /*! OSC_EN - Crystal Oscillator Enable
88320  *  0b0..Disable
88321  *  0b1..Enable
88322  */
88323 #define VBAT_OSCCTLA_OSC_EN(x)                   (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCTLA_OSC_EN_SHIFT)) & VBAT_OSCCTLA_OSC_EN_MASK)
88324 
88325 #define VBAT_OSCCTLA_OSC_BYP_EN_MASK             (0x2U)
88326 #define VBAT_OSCCTLA_OSC_BYP_EN_SHIFT            (1U)
88327 /*! OSC_BYP_EN - Crystal Oscillator Bypass Enable
88328  *  0b0..Does not bypass
88329  *  0b1..Bypass
88330  */
88331 #define VBAT_OSCCTLA_OSC_BYP_EN(x)               (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCTLA_OSC_BYP_EN_SHIFT)) & VBAT_OSCCTLA_OSC_BYP_EN_MASK)
88332 
88333 #define VBAT_OSCCTLA_COARSE_AMP_GAIN_MASK        (0xCU)
88334 #define VBAT_OSCCTLA_COARSE_AMP_GAIN_SHIFT       (2U)
88335 /*! COARSE_AMP_GAIN - Amplifier gain adjustment bits to allow the use of a wide range of external
88336  *    crystal ESR values See the device datasheet for the ranges supported by this device
88337  *  0b00..ESR Range 0
88338  *  0b01..ESR Range 1
88339  *  0b10..ESR Range 2
88340  *  0b11..ESR Range 3
88341  */
88342 #define VBAT_OSCCTLA_COARSE_AMP_GAIN(x)          (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCTLA_COARSE_AMP_GAIN_SHIFT)) & VBAT_OSCCTLA_COARSE_AMP_GAIN_MASK)
88343 
88344 #define VBAT_OSCCTLA_CAP_SEL_EN_MASK             (0x80U)
88345 #define VBAT_OSCCTLA_CAP_SEL_EN_SHIFT            (7U)
88346 /*! CAP_SEL_EN - Crystal Load Capacitance Selection Enable
88347  *  0b0..Disable
88348  *  0b1..Enable
88349  */
88350 #define VBAT_OSCCTLA_CAP_SEL_EN(x)               (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCTLA_CAP_SEL_EN_SHIFT)) & VBAT_OSCCTLA_CAP_SEL_EN_MASK)
88351 
88352 #define VBAT_OSCCTLA_EXTAL_CAP_SEL_MASK          (0xF00U)
88353 #define VBAT_OSCCTLA_EXTAL_CAP_SEL_SHIFT         (8U)
88354 /*! EXTAL_CAP_SEL - Crystal Load Capacitance Selection
88355  *  0b0000..0 pF
88356  *  0b0001..2 pF
88357  *  0b0010..4 pF
88358  *  0b0011..6 pF
88359  *  0b0100..8 pF
88360  *  0b0101..10 pF
88361  *  0b0110..12 pF
88362  *  0b0111..14 pF
88363  *  0b1000..16 pF
88364  *  0b1001..18 pF
88365  *  0b1010..20 pF
88366  *  0b1011..22 pF
88367  *  0b1100..24 pF
88368  *  0b1101..26 pF
88369  *  0b1110..28 pF
88370  *  0b1111..30 pF
88371  */
88372 #define VBAT_OSCCTLA_EXTAL_CAP_SEL(x)            (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCTLA_EXTAL_CAP_SEL_SHIFT)) & VBAT_OSCCTLA_EXTAL_CAP_SEL_MASK)
88373 
88374 #define VBAT_OSCCTLA_XTAL_CAP_SEL_MASK           (0xF000U)
88375 #define VBAT_OSCCTLA_XTAL_CAP_SEL_SHIFT          (12U)
88376 /*! XTAL_CAP_SEL - Crystal Load Capacitance Selection
88377  *  0b0000..0 pF
88378  *  0b0001..2 pF
88379  *  0b0010..4 pF
88380  *  0b0011..6 pF
88381  *  0b0100..8 pF
88382  *  0b0101..10 pF
88383  *  0b0110..12 pF
88384  *  0b0111..14 pF
88385  *  0b1000..16 pF
88386  *  0b1001..18 pF
88387  *  0b1010..20 pF
88388  *  0b1011..22 pF
88389  *  0b1100..24 pF
88390  *  0b1101..26 pF
88391  *  0b1110..28 pF
88392  *  0b1111..30 pF
88393  */
88394 #define VBAT_OSCCTLA_XTAL_CAP_SEL(x)             (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCTLA_XTAL_CAP_SEL_SHIFT)) & VBAT_OSCCTLA_XTAL_CAP_SEL_MASK)
88395 
88396 #define VBAT_OSCCTLA_MODE_EN_MASK                (0x30000U)
88397 #define VBAT_OSCCTLA_MODE_EN_SHIFT               (16U)
88398 /*! MODE_EN - Mode Enable
88399  *  0b00..Normal mode
88400  *  0b01..Startup mode
88401  *  0b11..Low power mode
88402  */
88403 #define VBAT_OSCCTLA_MODE_EN(x)                  (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCTLA_MODE_EN_SHIFT)) & VBAT_OSCCTLA_MODE_EN_MASK)
88404 
88405 #define VBAT_OSCCTLA_SUPPLY_DET_MASK             (0xC0000U)
88406 #define VBAT_OSCCTLA_SUPPLY_DET_SHIFT            (18U)
88407 /*! SUPPLY_DET - Supply Detector Trim
88408  *  0b00..VBAT supply is less than 3V
88409  *  0b01..VBAT supply is greater than 3V
88410  */
88411 #define VBAT_OSCCTLA_SUPPLY_DET(x)               (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCTLA_SUPPLY_DET_SHIFT)) & VBAT_OSCCTLA_SUPPLY_DET_MASK)
88412 /*! @} */
88413 
88414 /*! @name OSCCTLB - Oscillator Control B */
88415 /*! @{ */
88416 
88417 #define VBAT_OSCCTLB_INVERSE_MASK                (0xFFFFFU)
88418 #define VBAT_OSCCTLB_INVERSE_SHIFT               (0U)
88419 /*! INVERSE - Inverse Value */
88420 #define VBAT_OSCCTLB_INVERSE(x)                  (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCTLB_INVERSE_SHIFT)) & VBAT_OSCCTLB_INVERSE_MASK)
88421 /*! @} */
88422 
88423 /*! @name OSCCFGA - Oscillator Configuration A */
88424 /*! @{ */
88425 
88426 #define VBAT_OSCCFGA_CMP_TRIM_MASK               (0x3U)
88427 #define VBAT_OSCCFGA_CMP_TRIM_SHIFT              (0U)
88428 /*! CMP_TRIM - Comparator Trim
88429  *  0b00..760 mV
88430  *  0b01..770 mV
88431  *  0b11..740 mV
88432  */
88433 #define VBAT_OSCCFGA_CMP_TRIM(x)                 (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCFGA_CMP_TRIM_SHIFT)) & VBAT_OSCCFGA_CMP_TRIM_MASK)
88434 
88435 #define VBAT_OSCCFGA_CAP2_TRIM_MASK              (0x4U)
88436 #define VBAT_OSCCFGA_CAP2_TRIM_SHIFT             (2U)
88437 /*! CAP2_TRIM - CAP2_TRIM */
88438 #define VBAT_OSCCFGA_CAP2_TRIM(x)                (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCFGA_CAP2_TRIM_SHIFT)) & VBAT_OSCCFGA_CAP2_TRIM_MASK)
88439 
88440 #define VBAT_OSCCFGA_DLY_TRIM_MASK               (0x78U)
88441 #define VBAT_OSCCFGA_DLY_TRIM_SHIFT              (3U)
88442 /*! DLY_TRIM - Delay Trim
88443  *  0b0000..P current 9(nA) and N Current 6(nA)
88444  *  0b0001..P current 13(nA) and N Current 6(nA)
88445  *  0b0011..P current 4(nA) and N Current 6(nA)
88446  *  0b0100..P current 9(nA) and N Current 4(nA)
88447  *  0b0101..P current 13(nA) and N Current 4(nA)
88448  *  0b0111..P current 4(nA) and N Current 4(nA)
88449  *  0b1000..P current 9(nA) and N Current 2(nA)
88450  *  0b1001..P current 13(nA) and N Current 2(nA)
88451  *  0b1011..P current 4(nA) and N Current 2(nA)
88452  */
88453 #define VBAT_OSCCFGA_DLY_TRIM(x)                 (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCFGA_DLY_TRIM_SHIFT)) & VBAT_OSCCFGA_DLY_TRIM_MASK)
88454 
88455 #define VBAT_OSCCFGA_CAP_TRIM_MASK               (0x180U)
88456 #define VBAT_OSCCFGA_CAP_TRIM_SHIFT              (7U)
88457 /*! CAP_TRIM - Capacitor Trim
88458  *  0b00..Default (when CAP2_TRIM = 0 and CAP_TRIM[1:0] = 00 )
88459  *  0b01..-1us (when CAP2_TRIM = 0 and CAP_TRIM[1:0] = 01)
88460  *  0b10..-2us (when CAP2_TRIM = 0 and CAP_TRIM[1:0] = 10) or or +3.5us (when CAP2_TRIM = 1 and CAP_TRIM[1:0] = 10)
88461  *  0b11..-2.5us (when CAP2_TRIM = 0 and CAP_TRIM[1:0] = 11) or +1us (when CAP2_TRIM = 1 and CAP_TRIM[1:0] = 11)
88462  */
88463 #define VBAT_OSCCFGA_CAP_TRIM(x)                 (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCFGA_CAP_TRIM_SHIFT)) & VBAT_OSCCFGA_CAP_TRIM_MASK)
88464 
88465 #define VBAT_OSCCFGA_INIT_TRIM_MASK              (0xE00U)
88466 #define VBAT_OSCCFGA_INIT_TRIM_SHIFT             (9U)
88467 /*! INIT_TRIM - Initialization Trim
88468  *  0b000..8 s
88469  *  0b001..4 s
88470  *  0b010..2 s
88471  *  0b011..1 s
88472  *  0b100..0.5 s
88473  *  0b101..0.25 s
88474  *  0b110..0.125 s
88475  *  0b111..0.5 ms
88476  */
88477 #define VBAT_OSCCFGA_INIT_TRIM(x)                (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCFGA_INIT_TRIM_SHIFT)) & VBAT_OSCCFGA_INIT_TRIM_MASK)
88478 /*! @} */
88479 
88480 /*! @name OSCCFGB - Oscillator Configuration B */
88481 /*! @{ */
88482 
88483 #define VBAT_OSCCFGB_INVERSE_MASK                (0xFFFU)
88484 #define VBAT_OSCCFGB_INVERSE_SHIFT               (0U)
88485 /*! INVERSE - Inverse Value */
88486 #define VBAT_OSCCFGB_INVERSE(x)                  (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCFGB_INVERSE_SHIFT)) & VBAT_OSCCFGB_INVERSE_MASK)
88487 /*! @} */
88488 
88489 /*! @name OSCLCKA - Oscillator Lock A */
88490 /*! @{ */
88491 
88492 #define VBAT_OSCLCKA_LOCK_MASK                   (0x1U)
88493 #define VBAT_OSCLCKA_LOCK_SHIFT                  (0U)
88494 /*! LOCK - Lock
88495  *  0b0..Do not block
88496  *  0b1..Block
88497  */
88498 #define VBAT_OSCLCKA_LOCK(x)                     (((uint32_t)(((uint32_t)(x)) << VBAT_OSCLCKA_LOCK_SHIFT)) & VBAT_OSCLCKA_LOCK_MASK)
88499 /*! @} */
88500 
88501 /*! @name OSCLCKB - Oscillator Lock B */
88502 /*! @{ */
88503 
88504 #define VBAT_OSCLCKB_LOCK_MASK                   (0x1U)
88505 #define VBAT_OSCLCKB_LOCK_SHIFT                  (0U)
88506 /*! LOCK - Lock
88507  *  0b1..Do not block
88508  *  0b0..Block
88509  */
88510 #define VBAT_OSCLCKB_LOCK(x)                     (((uint32_t)(((uint32_t)(x)) << VBAT_OSCLCKB_LOCK_SHIFT)) & VBAT_OSCLCKB_LOCK_MASK)
88511 /*! @} */
88512 
88513 /*! @name OSCCLKE - Oscillator Clock Enable */
88514 /*! @{ */
88515 
88516 #define VBAT_OSCCLKE_CLKE_MASK                   (0xFU)
88517 #define VBAT_OSCCLKE_CLKE_SHIFT                  (0U)
88518 /*! CLKE - Clock Enable */
88519 #define VBAT_OSCCLKE_CLKE(x)                     (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCLKE_CLKE_SHIFT)) & VBAT_OSCCLKE_CLKE_MASK)
88520 /*! @} */
88521 
88522 /*! @name FROCTLA - FRO16K Control A */
88523 /*! @{ */
88524 
88525 #define VBAT_FROCTLA_FRO_EN_MASK                 (0x1U)
88526 #define VBAT_FROCTLA_FRO_EN_SHIFT                (0U)
88527 /*! FRO_EN - FRO16K Enable
88528  *  0b0..Disable
88529  *  0b1..Enable
88530  */
88531 #define VBAT_FROCTLA_FRO_EN(x)                   (((uint32_t)(((uint32_t)(x)) << VBAT_FROCTLA_FRO_EN_SHIFT)) & VBAT_FROCTLA_FRO_EN_MASK)
88532 /*! @} */
88533 
88534 /*! @name FROCTLB - FRO16K Control B */
88535 /*! @{ */
88536 
88537 #define VBAT_FROCTLB_INVERSE_MASK                (0x1U)
88538 #define VBAT_FROCTLB_INVERSE_SHIFT               (0U)
88539 /*! INVERSE - Inverse Value */
88540 #define VBAT_FROCTLB_INVERSE(x)                  (((uint32_t)(((uint32_t)(x)) << VBAT_FROCTLB_INVERSE_SHIFT)) & VBAT_FROCTLB_INVERSE_MASK)
88541 /*! @} */
88542 
88543 /*! @name FROLCKA - FRO16K Lock A */
88544 /*! @{ */
88545 
88546 #define VBAT_FROLCKA_LOCK_MASK                   (0x1U)
88547 #define VBAT_FROLCKA_LOCK_SHIFT                  (0U)
88548 /*! LOCK - Lock
88549  *  0b0..Do not block
88550  *  0b1..Block
88551  */
88552 #define VBAT_FROLCKA_LOCK(x)                     (((uint32_t)(((uint32_t)(x)) << VBAT_FROLCKA_LOCK_SHIFT)) & VBAT_FROLCKA_LOCK_MASK)
88553 /*! @} */
88554 
88555 /*! @name FROLCKB - FRO16K Lock B */
88556 /*! @{ */
88557 
88558 #define VBAT_FROLCKB_LOCK_MASK                   (0x1U)
88559 #define VBAT_FROLCKB_LOCK_SHIFT                  (0U)
88560 /*! LOCK - Lock
88561  *  0b1..Do not block
88562  *  0b0..Block
88563  */
88564 #define VBAT_FROLCKB_LOCK(x)                     (((uint32_t)(((uint32_t)(x)) << VBAT_FROLCKB_LOCK_SHIFT)) & VBAT_FROLCKB_LOCK_MASK)
88565 /*! @} */
88566 
88567 /*! @name FROCLKE - FRO16K Clock Enable */
88568 /*! @{ */
88569 
88570 #define VBAT_FROCLKE_CLKE_MASK                   (0xFU)
88571 #define VBAT_FROCLKE_CLKE_SHIFT                  (0U)
88572 /*! CLKE - Clock Enable */
88573 #define VBAT_FROCLKE_CLKE(x)                     (((uint32_t)(((uint32_t)(x)) << VBAT_FROCLKE_CLKE_SHIFT)) & VBAT_FROCLKE_CLKE_MASK)
88574 /*! @} */
88575 
88576 /*! @name LDOCTLA - LDO_RAM Control A */
88577 /*! @{ */
88578 
88579 #define VBAT_LDOCTLA_BG_EN_MASK                  (0x1U)
88580 #define VBAT_LDOCTLA_BG_EN_SHIFT                 (0U)
88581 /*! BG_EN - Bandgap Enable
88582  *  0b0..Disable
88583  *  0b1..Enable
88584  */
88585 #define VBAT_LDOCTLA_BG_EN(x)                    (((uint32_t)(((uint32_t)(x)) << VBAT_LDOCTLA_BG_EN_SHIFT)) & VBAT_LDOCTLA_BG_EN_MASK)
88586 
88587 #define VBAT_LDOCTLA_LDO_EN_MASK                 (0x2U)
88588 #define VBAT_LDOCTLA_LDO_EN_SHIFT                (1U)
88589 /*! LDO_EN - LDO Enable
88590  *  0b0..Disable
88591  *  0b1..Enable
88592  */
88593 #define VBAT_LDOCTLA_LDO_EN(x)                   (((uint32_t)(((uint32_t)(x)) << VBAT_LDOCTLA_LDO_EN_SHIFT)) & VBAT_LDOCTLA_LDO_EN_MASK)
88594 
88595 #define VBAT_LDOCTLA_REFRESH_EN_MASK             (0x4U)
88596 #define VBAT_LDOCTLA_REFRESH_EN_SHIFT            (2U)
88597 /*! REFRESH_EN - Refresh Enable
88598  *  0b0..Refresh mode is disabled
88599  *  0b1..Refresh mode is enabled for low power operation
88600  */
88601 #define VBAT_LDOCTLA_REFRESH_EN(x)               (((uint32_t)(((uint32_t)(x)) << VBAT_LDOCTLA_REFRESH_EN_SHIFT)) & VBAT_LDOCTLA_REFRESH_EN_MASK)
88602 /*! @} */
88603 
88604 /*! @name LDOCTLB - LDO_RAM Control B */
88605 /*! @{ */
88606 
88607 #define VBAT_LDOCTLB_INVERSE_MASK                (0x7U)
88608 #define VBAT_LDOCTLB_INVERSE_SHIFT               (0U)
88609 /*! INVERSE - Inverse Value */
88610 #define VBAT_LDOCTLB_INVERSE(x)                  (((uint32_t)(((uint32_t)(x)) << VBAT_LDOCTLB_INVERSE_SHIFT)) & VBAT_LDOCTLB_INVERSE_MASK)
88611 /*! @} */
88612 
88613 /*! @name LDOLCKA - LDO_RAM Lock A */
88614 /*! @{ */
88615 
88616 #define VBAT_LDOLCKA_LOCK_MASK                   (0x1U)
88617 #define VBAT_LDOLCKA_LOCK_SHIFT                  (0U)
88618 /*! LOCK - Lock
88619  *  0b0..Do not block
88620  *  0b1..Block
88621  */
88622 #define VBAT_LDOLCKA_LOCK(x)                     (((uint32_t)(((uint32_t)(x)) << VBAT_LDOLCKA_LOCK_SHIFT)) & VBAT_LDOLCKA_LOCK_MASK)
88623 /*! @} */
88624 
88625 /*! @name LDOLCKB - LDO_RAM Lock B */
88626 /*! @{ */
88627 
88628 #define VBAT_LDOLCKB_LOCK_MASK                   (0x1U)
88629 #define VBAT_LDOLCKB_LOCK_SHIFT                  (0U)
88630 /*! LOCK - Lock
88631  *  0b1..Do not block
88632  *  0b0..Block
88633  */
88634 #define VBAT_LDOLCKB_LOCK(x)                     (((uint32_t)(((uint32_t)(x)) << VBAT_LDOLCKB_LOCK_SHIFT)) & VBAT_LDOLCKB_LOCK_MASK)
88635 /*! @} */
88636 
88637 /*! @name LDORAMC - RAM Control */
88638 /*! @{ */
88639 
88640 #define VBAT_LDORAMC_ISO_MASK                    (0x1U)
88641 #define VBAT_LDORAMC_ISO_SHIFT                   (0U)
88642 /*! ISO - Isolate SRAM
88643  *  0b0..State follows the chip power modes
88644  *  0b1..Isolates SRAM and places it in Low-Power Retention mode
88645  */
88646 #define VBAT_LDORAMC_ISO(x)                      (((uint32_t)(((uint32_t)(x)) << VBAT_LDORAMC_ISO_SHIFT)) & VBAT_LDORAMC_ISO_MASK)
88647 
88648 #define VBAT_LDORAMC_SWI_MASK                    (0x2U)
88649 #define VBAT_LDORAMC_SWI_SHIFT                   (1U)
88650 /*! SWI - Switch SRAM
88651  *  0b0..Supply follows the chip power modes
88652  *  0b1..LDO_RAM powers the array
88653  */
88654 #define VBAT_LDORAMC_SWI(x)                      (((uint32_t)(((uint32_t)(x)) << VBAT_LDORAMC_SWI_SHIFT)) & VBAT_LDORAMC_SWI_MASK)
88655 
88656 #define VBAT_LDORAMC_RET0_MASK                   (0x100U)
88657 #define VBAT_LDORAMC_RET0_SHIFT                  (8U)
88658 /*! RET0 - Retention
88659  *  0b0..Corresponding SRAM array is retained in low-power modes
88660  *  0b1..Corresponding SRAM array is not retained in low-power modes
88661  */
88662 #define VBAT_LDORAMC_RET0(x)                     (((uint32_t)(((uint32_t)(x)) << VBAT_LDORAMC_RET0_SHIFT)) & VBAT_LDORAMC_RET0_MASK)
88663 
88664 #define VBAT_LDORAMC_RET1_MASK                   (0x200U)
88665 #define VBAT_LDORAMC_RET1_SHIFT                  (9U)
88666 /*! RET1 - Retention
88667  *  0b0..Corresponding SRAM array is retained in low-power modes
88668  *  0b1..Corresponding SRAM array is not retained in low-power modes
88669  */
88670 #define VBAT_LDORAMC_RET1(x)                     (((uint32_t)(((uint32_t)(x)) << VBAT_LDORAMC_RET1_SHIFT)) & VBAT_LDORAMC_RET1_MASK)
88671 
88672 #define VBAT_LDORAMC_RET2_MASK                   (0x400U)
88673 #define VBAT_LDORAMC_RET2_SHIFT                  (10U)
88674 /*! RET2 - Retention
88675  *  0b0..Corresponding SRAM array is retained in low-power modes
88676  *  0b1..Corresponding SRAM array is not retained in low-power modes
88677  */
88678 #define VBAT_LDORAMC_RET2(x)                     (((uint32_t)(((uint32_t)(x)) << VBAT_LDORAMC_RET2_SHIFT)) & VBAT_LDORAMC_RET2_MASK)
88679 
88680 #define VBAT_LDORAMC_RET3_MASK                   (0x800U)
88681 #define VBAT_LDORAMC_RET3_SHIFT                  (11U)
88682 /*! RET3 - Retention
88683  *  0b0..Corresponding SRAM array is retained in low-power modes
88684  *  0b1..Corresponding SRAM array is not retained in low-power modes
88685  */
88686 #define VBAT_LDORAMC_RET3(x)                     (((uint32_t)(((uint32_t)(x)) << VBAT_LDORAMC_RET3_SHIFT)) & VBAT_LDORAMC_RET3_MASK)
88687 /*! @} */
88688 
88689 /*! @name LDOTIMER0 - Bandgap Timer 0 */
88690 /*! @{ */
88691 
88692 #define VBAT_LDOTIMER0_TIMCFG_MASK               (0x7U)
88693 #define VBAT_LDOTIMER0_TIMCFG_SHIFT              (0U)
88694 /*! TIMCFG - Timeout Configuration
88695  *  0b111..7.8125 ms
88696  *  0b110..15.625 ms
88697  *  0b101..31.25 ms
88698  *  0b100..62.5 ms
88699  *  0b011..125 ms
88700  *  0b010..250 ms
88701  *  0b001..500 ms
88702  *  0b000..1 s
88703  */
88704 #define VBAT_LDOTIMER0_TIMCFG(x)                 (((uint32_t)(((uint32_t)(x)) << VBAT_LDOTIMER0_TIMCFG_SHIFT)) & VBAT_LDOTIMER0_TIMCFG_MASK)
88705 
88706 #define VBAT_LDOTIMER0_TIMEN_MASK                (0x80000000U)
88707 #define VBAT_LDOTIMER0_TIMEN_SHIFT               (31U)
88708 /*! TIMEN - Bandgap Timeout Period Enable
88709  *  0b0..Disable
88710  *  0b1..Enable
88711  */
88712 #define VBAT_LDOTIMER0_TIMEN(x)                  (((uint32_t)(((uint32_t)(x)) << VBAT_LDOTIMER0_TIMEN_SHIFT)) & VBAT_LDOTIMER0_TIMEN_MASK)
88713 /*! @} */
88714 
88715 /*! @name LDOTIMER1 - Bandgap Timer 1 */
88716 /*! @{ */
88717 
88718 #define VBAT_LDOTIMER1_TIMCFG_MASK               (0xFFFFFFU)
88719 #define VBAT_LDOTIMER1_TIMCFG_SHIFT              (0U)
88720 /*! TIMCFG - Timeout Configuration */
88721 #define VBAT_LDOTIMER1_TIMCFG(x)                 (((uint32_t)(((uint32_t)(x)) << VBAT_LDOTIMER1_TIMCFG_SHIFT)) & VBAT_LDOTIMER1_TIMCFG_MASK)
88722 
88723 #define VBAT_LDOTIMER1_TIMEN_MASK                (0x80000000U)
88724 #define VBAT_LDOTIMER1_TIMEN_SHIFT               (31U)
88725 /*! TIMEN - Bandgap Timeout Period Enable
88726  *  0b0..Disable
88727  *  0b1..Enable
88728  */
88729 #define VBAT_LDOTIMER1_TIMEN(x)                  (((uint32_t)(((uint32_t)(x)) << VBAT_LDOTIMER1_TIMEN_SHIFT)) & VBAT_LDOTIMER1_TIMEN_MASK)
88730 /*! @} */
88731 
88732 /*! @name MONCTLA - CLKMON Control A */
88733 /*! @{ */
88734 
88735 #define VBAT_MONCTLA_MON_EN_MASK                 (0x1U)
88736 #define VBAT_MONCTLA_MON_EN_SHIFT                (0U)
88737 /*! MON_EN - CLKMON Enable
88738  *  0b0..CLKMON is disabled
88739  *  0b1..CLKMON is enabled
88740  */
88741 #define VBAT_MONCTLA_MON_EN(x)                   (((uint32_t)(((uint32_t)(x)) << VBAT_MONCTLA_MON_EN_SHIFT)) & VBAT_MONCTLA_MON_EN_MASK)
88742 /*! @} */
88743 
88744 /*! @name MONCTLB - CLKMON Control B */
88745 /*! @{ */
88746 
88747 #define VBAT_MONCTLB_INVERSE_MASK                (0x1U)
88748 #define VBAT_MONCTLB_INVERSE_SHIFT               (0U)
88749 /*! INVERSE - Inverse value */
88750 #define VBAT_MONCTLB_INVERSE(x)                  (((uint32_t)(((uint32_t)(x)) << VBAT_MONCTLB_INVERSE_SHIFT)) & VBAT_MONCTLB_INVERSE_MASK)
88751 /*! @} */
88752 
88753 /*! @name MONCFGA - CLKMON Configuration A */
88754 /*! @{ */
88755 
88756 #define VBAT_MONCFGA_FREQ_TRIM_MASK              (0x3U)
88757 #define VBAT_MONCFGA_FREQ_TRIM_SHIFT             (0U)
88758 /*! FREQ_TRIM - Frequency Trim
88759  *  0b00..Clock monitor asserts 2 cycle after expected edge
88760  *  0b01..Clock monitor asserts 4 cycles after expected edge
88761  *  0b10..Clock monitor asserts 6 cycles after expected edge
88762  *  0b11..Clock monitor asserts 8 cycles after expected edge
88763  */
88764 #define VBAT_MONCFGA_FREQ_TRIM(x)                (((uint32_t)(((uint32_t)(x)) << VBAT_MONCFGA_FREQ_TRIM_SHIFT)) & VBAT_MONCFGA_FREQ_TRIM_MASK)
88765 
88766 #define VBAT_MONCFGA_DIVIDE_TRIM_MASK            (0x4U)
88767 #define VBAT_MONCFGA_DIVIDE_TRIM_SHIFT           (2U)
88768 /*! DIVIDE_TRIM - Divide Trim
88769  *  0b0..Clock monitor operates at 1 kHz
88770  *  0b1..Clock monitor operates at 64 Hz
88771  */
88772 #define VBAT_MONCFGA_DIVIDE_TRIM(x)              (((uint32_t)(((uint32_t)(x)) << VBAT_MONCFGA_DIVIDE_TRIM_SHIFT)) & VBAT_MONCFGA_DIVIDE_TRIM_MASK)
88773 
88774 #define VBAT_MONCFGA_RSVD_TRIM_MASK              (0xF8U)
88775 #define VBAT_MONCFGA_RSVD_TRIM_SHIFT             (3U)
88776 /*! RSVD_TRIM - Reserved Trim */
88777 #define VBAT_MONCFGA_RSVD_TRIM(x)                (((uint32_t)(((uint32_t)(x)) << VBAT_MONCFGA_RSVD_TRIM_SHIFT)) & VBAT_MONCFGA_RSVD_TRIM_MASK)
88778 /*! @} */
88779 
88780 /*! @name MONCFGB - CLKMON Configuration B */
88781 /*! @{ */
88782 
88783 #define VBAT_MONCFGB_INVERSE_MASK                (0xFFU)
88784 #define VBAT_MONCFGB_INVERSE_SHIFT               (0U)
88785 /*! INVERSE - Inverse value */
88786 #define VBAT_MONCFGB_INVERSE(x)                  (((uint32_t)(((uint32_t)(x)) << VBAT_MONCFGB_INVERSE_SHIFT)) & VBAT_MONCFGB_INVERSE_MASK)
88787 /*! @} */
88788 
88789 /*! @name MONLCKA - CLKMON Lock A */
88790 /*! @{ */
88791 
88792 #define VBAT_MONLCKA_LOCK_MASK                   (0x1U)
88793 #define VBAT_MONLCKA_LOCK_SHIFT                  (0U)
88794 /*! LOCK - Lock
88795  *  0b0..Lock is disabled
88796  *  0b1..Lock is enabled
88797  */
88798 #define VBAT_MONLCKA_LOCK(x)                     (((uint32_t)(((uint32_t)(x)) << VBAT_MONLCKA_LOCK_SHIFT)) & VBAT_MONLCKA_LOCK_MASK)
88799 /*! @} */
88800 
88801 /*! @name MONLCKB - CLKMON Lock B */
88802 /*! @{ */
88803 
88804 #define VBAT_MONLCKB_LOCK_MASK                   (0x1U)
88805 #define VBAT_MONLCKB_LOCK_SHIFT                  (0U)
88806 /*! LOCK - Lock
88807  *  0b1..Lock is disabled
88808  *  0b0..Lock is enabled
88809  */
88810 #define VBAT_MONLCKB_LOCK(x)                     (((uint32_t)(((uint32_t)(x)) << VBAT_MONLCKB_LOCK_SHIFT)) & VBAT_MONLCKB_LOCK_MASK)
88811 /*! @} */
88812 
88813 /*! @name TAMCTLA - TAMPER Control A */
88814 /*! @{ */
88815 
88816 #define VBAT_TAMCTLA_VOLT_EN_MASK                (0x1U)
88817 #define VBAT_TAMCTLA_VOLT_EN_SHIFT               (0U)
88818 /*! VOLT_EN - Voltage Detect Enable
88819  *  0b0..Voltage detect is disabled
88820  *  0b1..Voltage detect is enabled
88821  */
88822 #define VBAT_TAMCTLA_VOLT_EN(x)                  (((uint32_t)(((uint32_t)(x)) << VBAT_TAMCTLA_VOLT_EN_SHIFT)) & VBAT_TAMCTLA_VOLT_EN_MASK)
88823 
88824 #define VBAT_TAMCTLA_TEMP_EN_MASK                (0x2U)
88825 #define VBAT_TAMCTLA_TEMP_EN_SHIFT               (1U)
88826 /*! TEMP_EN - Temperature Detect Enable
88827  *  0b0..Temperature detect is disabled
88828  *  0b1..Temperature detect is enabled
88829  */
88830 #define VBAT_TAMCTLA_TEMP_EN(x)                  (((uint32_t)(((uint32_t)(x)) << VBAT_TAMCTLA_TEMP_EN_SHIFT)) & VBAT_TAMCTLA_TEMP_EN_MASK)
88831 
88832 #define VBAT_TAMCTLA_LIGHT_EN_MASK               (0x4U)
88833 #define VBAT_TAMCTLA_LIGHT_EN_SHIFT              (2U)
88834 /*! LIGHT_EN - Light Detect Enable
88835  *  0b0..Light detect is disabled
88836  *  0b1..Light detect is enabled
88837  */
88838 #define VBAT_TAMCTLA_LIGHT_EN(x)                 (((uint32_t)(((uint32_t)(x)) << VBAT_TAMCTLA_LIGHT_EN_SHIFT)) & VBAT_TAMCTLA_LIGHT_EN_MASK)
88839 /*! @} */
88840 
88841 /*! @name TAMCTLB - TAMPER Control B */
88842 /*! @{ */
88843 
88844 #define VBAT_TAMCTLB_INVERSE_MASK                (0xFU)
88845 #define VBAT_TAMCTLB_INVERSE_SHIFT               (0U)
88846 /*! INVERSE - Inverse value */
88847 #define VBAT_TAMCTLB_INVERSE(x)                  (((uint32_t)(((uint32_t)(x)) << VBAT_TAMCTLB_INVERSE_SHIFT)) & VBAT_TAMCTLB_INVERSE_MASK)
88848 /*! @} */
88849 
88850 /*! @name TAMLCKA - TAMPER Lock A */
88851 /*! @{ */
88852 
88853 #define VBAT_TAMLCKA_LOCK_MASK                   (0x1U)
88854 #define VBAT_TAMLCKA_LOCK_SHIFT                  (0U)
88855 /*! LOCK - Lock
88856  *  0b0..Lock is disabled
88857  *  0b1..Lock is enabled
88858  */
88859 #define VBAT_TAMLCKA_LOCK(x)                     (((uint32_t)(((uint32_t)(x)) << VBAT_TAMLCKA_LOCK_SHIFT)) & VBAT_TAMLCKA_LOCK_MASK)
88860 /*! @} */
88861 
88862 /*! @name TAMLCKB - TAMPER Lock B */
88863 /*! @{ */
88864 
88865 #define VBAT_TAMLCKB_LOCK_MASK                   (0x1U)
88866 #define VBAT_TAMLCKB_LOCK_SHIFT                  (0U)
88867 /*! LOCK - Lock
88868  *  0b1..Lock is disabled
88869  *  0b0..Lock is enabled
88870  */
88871 #define VBAT_TAMLCKB_LOCK(x)                     (((uint32_t)(((uint32_t)(x)) << VBAT_TAMLCKB_LOCK_SHIFT)) & VBAT_TAMLCKB_LOCK_MASK)
88872 /*! @} */
88873 
88874 /*! @name SWICTLA - Switch Control A */
88875 /*! @{ */
88876 
88877 #define VBAT_SWICTLA_SWI_EN_MASK                 (0x1U)
88878 #define VBAT_SWICTLA_SWI_EN_SHIFT                (0U)
88879 /*! SWI_EN - Switch Enable
88880  *  0b0..VDD_BAT
88881  *  0b1..VDD_SYS
88882  */
88883 #define VBAT_SWICTLA_SWI_EN(x)                   (((uint32_t)(((uint32_t)(x)) << VBAT_SWICTLA_SWI_EN_SHIFT)) & VBAT_SWICTLA_SWI_EN_MASK)
88884 
88885 #define VBAT_SWICTLA_LP_EN_MASK                  (0x2U)
88886 #define VBAT_SWICTLA_LP_EN_SHIFT                 (1U)
88887 /*! LP_EN - Low Power Enable
88888  *  0b0..VDD_BAT always supplies VBAT modules in low-power modes
88889  *  0b1..VDD_SYS always supplies VBAT modules if SWI_EN is also 1
88890  */
88891 #define VBAT_SWICTLA_LP_EN(x)                    (((uint32_t)(((uint32_t)(x)) << VBAT_SWICTLA_LP_EN_SHIFT)) & VBAT_SWICTLA_LP_EN_MASK)
88892 /*! @} */
88893 
88894 /*! @name SWICTLB - Switch Control B */
88895 /*! @{ */
88896 
88897 #define VBAT_SWICTLB_INVERSE_MASK                (0x3U)
88898 #define VBAT_SWICTLB_INVERSE_SHIFT               (0U)
88899 /*! INVERSE - Inverse Value */
88900 #define VBAT_SWICTLB_INVERSE(x)                  (((uint32_t)(((uint32_t)(x)) << VBAT_SWICTLB_INVERSE_SHIFT)) & VBAT_SWICTLB_INVERSE_MASK)
88901 /*! @} */
88902 
88903 /*! @name SWILCKA - Switch Lock A */
88904 /*! @{ */
88905 
88906 #define VBAT_SWILCKA_LOCK_MASK                   (0x1U)
88907 #define VBAT_SWILCKA_LOCK_SHIFT                  (0U)
88908 /*! LOCK - Lock
88909  *  0b0..Do not block
88910  *  0b1..Block
88911  */
88912 #define VBAT_SWILCKA_LOCK(x)                     (((uint32_t)(((uint32_t)(x)) << VBAT_SWILCKA_LOCK_SHIFT)) & VBAT_SWILCKA_LOCK_MASK)
88913 /*! @} */
88914 
88915 /*! @name SWILCKB - Switch Lock B */
88916 /*! @{ */
88917 
88918 #define VBAT_SWILCKB_LOCK_MASK                   (0x1U)
88919 #define VBAT_SWILCKB_LOCK_SHIFT                  (0U)
88920 /*! LOCK - Lock
88921  *  0b1..Do not block
88922  *  0b0..Block
88923  */
88924 #define VBAT_SWILCKB_LOCK(x)                     (((uint32_t)(((uint32_t)(x)) << VBAT_SWILCKB_LOCK_SHIFT)) & VBAT_SWILCKB_LOCK_MASK)
88925 /*! @} */
88926 
88927 /*! @name WAKEUP_WAKEUPA - Wakeup 0 Register A */
88928 /*! @{ */
88929 
88930 #define VBAT_WAKEUP_WAKEUPA_REG_MASK             (0xFFFFFFFFU)
88931 #define VBAT_WAKEUP_WAKEUPA_REG_SHIFT            (0U)
88932 /*! REG - Register */
88933 #define VBAT_WAKEUP_WAKEUPA_REG(x)               (((uint32_t)(((uint32_t)(x)) << VBAT_WAKEUP_WAKEUPA_REG_SHIFT)) & VBAT_WAKEUP_WAKEUPA_REG_MASK)
88934 /*! @} */
88935 
88936 /* The count of VBAT_WAKEUP_WAKEUPA */
88937 #define VBAT_WAKEUP_WAKEUPA_COUNT                (2U)
88938 
88939 /*! @name WAKEUP_WAKEUPB - Wakeup 0 Register B */
88940 /*! @{ */
88941 
88942 #define VBAT_WAKEUP_WAKEUPB_INVERSE_MASK         (0xFFFFFFFFU)
88943 #define VBAT_WAKEUP_WAKEUPB_INVERSE_SHIFT        (0U)
88944 /*! INVERSE - Inverse value */
88945 #define VBAT_WAKEUP_WAKEUPB_INVERSE(x)           (((uint32_t)(((uint32_t)(x)) << VBAT_WAKEUP_WAKEUPB_INVERSE_SHIFT)) & VBAT_WAKEUP_WAKEUPB_INVERSE_MASK)
88946 /*! @} */
88947 
88948 /* The count of VBAT_WAKEUP_WAKEUPB */
88949 #define VBAT_WAKEUP_WAKEUPB_COUNT                (2U)
88950 
88951 /*! @name WAKLCKA - Wakeup Lock A */
88952 /*! @{ */
88953 
88954 #define VBAT_WAKLCKA_LOCK_MASK                   (0x1U)
88955 #define VBAT_WAKLCKA_LOCK_SHIFT                  (0U)
88956 /*! LOCK - Lock
88957  *  0b0..Lock is disabled
88958  *  0b1..Lock is enabled
88959  */
88960 #define VBAT_WAKLCKA_LOCK(x)                     (((uint32_t)(((uint32_t)(x)) << VBAT_WAKLCKA_LOCK_SHIFT)) & VBAT_WAKLCKA_LOCK_MASK)
88961 /*! @} */
88962 
88963 /*! @name WAKLCKB - Wakeup Lock B */
88964 /*! @{ */
88965 
88966 #define VBAT_WAKLCKB_LOCK_MASK                   (0x1U)
88967 #define VBAT_WAKLCKB_LOCK_SHIFT                  (0U)
88968 /*! LOCK - Lock
88969  *  0b1..Lock is disabled
88970  *  0b0..Lock is enabled
88971  */
88972 #define VBAT_WAKLCKB_LOCK(x)                     (((uint32_t)(((uint32_t)(x)) << VBAT_WAKLCKB_LOCK_SHIFT)) & VBAT_WAKLCKB_LOCK_MASK)
88973 /*! @} */
88974 
88975 
88976 /*!
88977  * @}
88978  */ /* end of group VBAT_Register_Masks */
88979 
88980 
88981 /* VBAT - Peripheral instance base addresses */
88982 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
88983   /** Peripheral VBAT0 base address */
88984   #define VBAT0_BASE                               (0x50059000u)
88985   /** Peripheral VBAT0 base address */
88986   #define VBAT0_BASE_NS                            (0x40059000u)
88987   /** Peripheral VBAT0 base pointer */
88988   #define VBAT0                                    ((VBAT_Type *)VBAT0_BASE)
88989   /** Peripheral VBAT0 base pointer */
88990   #define VBAT0_NS                                 ((VBAT_Type *)VBAT0_BASE_NS)
88991   /** Array initializer of VBAT peripheral base addresses */
88992   #define VBAT_BASE_ADDRS                          { VBAT0_BASE }
88993   /** Array initializer of VBAT peripheral base pointers */
88994   #define VBAT_BASE_PTRS                           { VBAT0 }
88995   /** Array initializer of VBAT peripheral base addresses */
88996   #define VBAT_BASE_ADDRS_NS                       { VBAT0_BASE_NS }
88997   /** Array initializer of VBAT peripheral base pointers */
88998   #define VBAT_BASE_PTRS_NS                        { VBAT0_NS }
88999 #else
89000   /** Peripheral VBAT0 base address */
89001   #define VBAT0_BASE                               (0x40059000u)
89002   /** Peripheral VBAT0 base pointer */
89003   #define VBAT0                                    ((VBAT_Type *)VBAT0_BASE)
89004   /** Array initializer of VBAT peripheral base addresses */
89005   #define VBAT_BASE_ADDRS                          { VBAT0_BASE }
89006   /** Array initializer of VBAT peripheral base pointers */
89007   #define VBAT_BASE_PTRS                           { VBAT0 }
89008 #endif
89009 
89010 /*!
89011  * @}
89012  */ /* end of group VBAT_Peripheral_Access_Layer */
89013 
89014 
89015 /* ----------------------------------------------------------------------------
89016    -- VREF Peripheral Access Layer
89017    ---------------------------------------------------------------------------- */
89018 
89019 /*!
89020  * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer
89021  * @{
89022  */
89023 
89024 /** VREF - Register Layout Typedef */
89025 typedef struct {
89026   __I  uint32_t VERID;                             /**< Version ID, offset: 0x0 */
89027        uint8_t RESERVED_0[4];
89028   __IO uint32_t CSR;                               /**< Control and Status, offset: 0x8 */
89029        uint8_t RESERVED_1[4];
89030   __IO uint32_t UTRIM;                             /**< User Trim, offset: 0x10 */
89031 } VREF_Type;
89032 
89033 /* ----------------------------------------------------------------------------
89034    -- VREF Register Masks
89035    ---------------------------------------------------------------------------- */
89036 
89037 /*!
89038  * @addtogroup VREF_Register_Masks VREF Register Masks
89039  * @{
89040  */
89041 
89042 /*! @name VERID - Version ID */
89043 /*! @{ */
89044 
89045 #define VREF_VERID_FEATURE_MASK                  (0xFFFFU)
89046 #define VREF_VERID_FEATURE_SHIFT                 (0U)
89047 /*! FEATURE - Feature Specification Number */
89048 #define VREF_VERID_FEATURE(x)                    (((uint32_t)(((uint32_t)(x)) << VREF_VERID_FEATURE_SHIFT)) & VREF_VERID_FEATURE_MASK)
89049 
89050 #define VREF_VERID_MINOR_MASK                    (0xFF0000U)
89051 #define VREF_VERID_MINOR_SHIFT                   (16U)
89052 /*! MINOR - Minor Version Number */
89053 #define VREF_VERID_MINOR(x)                      (((uint32_t)(((uint32_t)(x)) << VREF_VERID_MINOR_SHIFT)) & VREF_VERID_MINOR_MASK)
89054 
89055 #define VREF_VERID_MAJOR_MASK                    (0xFF000000U)
89056 #define VREF_VERID_MAJOR_SHIFT                   (24U)
89057 /*! MAJOR - Major Version Number */
89058 #define VREF_VERID_MAJOR(x)                      (((uint32_t)(((uint32_t)(x)) << VREF_VERID_MAJOR_SHIFT)) & VREF_VERID_MAJOR_MASK)
89059 /*! @} */
89060 
89061 /*! @name CSR - Control and Status */
89062 /*! @{ */
89063 
89064 #define VREF_CSR_HCBGEN_MASK                     (0x1U)
89065 #define VREF_CSR_HCBGEN_SHIFT                    (0U)
89066 /*! HCBGEN - HC Bandgap Enabled
89067  *  0b0..Disables
89068  *  0b1..Enables
89069  */
89070 #define VREF_CSR_HCBGEN(x)                       (((uint32_t)(((uint32_t)(x)) << VREF_CSR_HCBGEN_SHIFT)) & VREF_CSR_HCBGEN_MASK)
89071 
89072 #define VREF_CSR_LPBGEN_MASK                     (0x2U)
89073 #define VREF_CSR_LPBGEN_SHIFT                    (1U)
89074 /*! LPBGEN - Low-Power Bandgap Enable
89075  *  0b0..Disables
89076  *  0b1..Enables
89077  */
89078 #define VREF_CSR_LPBGEN(x)                       (((uint32_t)(((uint32_t)(x)) << VREF_CSR_LPBGEN_SHIFT)) & VREF_CSR_LPBGEN_MASK)
89079 
89080 #define VREF_CSR_LPBG_BUF_EN_MASK                (0x4U)
89081 #define VREF_CSR_LPBG_BUF_EN_SHIFT               (2U)
89082 /*! LPBG_BUF_EN - Low-Power Bandgap Buffer Enable
89083  *  0b0..Disables
89084  *  0b1..Enables
89085  */
89086 #define VREF_CSR_LPBG_BUF_EN(x)                  (((uint32_t)(((uint32_t)(x)) << VREF_CSR_LPBG_BUF_EN_SHIFT)) & VREF_CSR_LPBG_BUF_EN_MASK)
89087 
89088 #define VREF_CSR_CHOPEN_MASK                     (0x8U)
89089 #define VREF_CSR_CHOPEN_SHIFT                    (3U)
89090 /*! CHOPEN - Chop Oscillator Enable
89091  *  0b0..Disables
89092  *  0b1..Enables
89093  */
89094 #define VREF_CSR_CHOPEN(x)                       (((uint32_t)(((uint32_t)(x)) << VREF_CSR_CHOPEN_SHIFT)) & VREF_CSR_CHOPEN_MASK)
89095 
89096 #define VREF_CSR_ICOMPEN_MASK                    (0x10U)
89097 #define VREF_CSR_ICOMPEN_SHIFT                   (4U)
89098 /*! ICOMPEN - Current Compensation Enable
89099  *  0b0..Disables
89100  *  0b1..Enables
89101  */
89102 #define VREF_CSR_ICOMPEN(x)                      (((uint32_t)(((uint32_t)(x)) << VREF_CSR_ICOMPEN_SHIFT)) & VREF_CSR_ICOMPEN_MASK)
89103 
89104 #define VREF_CSR_REGEN_MASK                      (0x20U)
89105 #define VREF_CSR_REGEN_SHIFT                     (5U)
89106 /*! REGEN - Regulator Enable
89107  *  0b0..Disables
89108  *  0b1..Enables
89109  */
89110 #define VREF_CSR_REGEN(x)                        (((uint32_t)(((uint32_t)(x)) << VREF_CSR_REGEN_SHIFT)) & VREF_CSR_REGEN_MASK)
89111 
89112 #define VREF_CSR_HI_PWR_LV_MASK                  (0x800U)
89113 #define VREF_CSR_HI_PWR_LV_SHIFT                 (11U)
89114 /*! HI_PWR_LV - High-Power Level
89115  *  0b0..Low-power
89116  *  0b1..High-power
89117  */
89118 #define VREF_CSR_HI_PWR_LV(x)                    (((uint32_t)(((uint32_t)(x)) << VREF_CSR_HI_PWR_LV_SHIFT)) & VREF_CSR_HI_PWR_LV_MASK)
89119 
89120 #define VREF_CSR_BUF21EN_MASK                    (0x10000U)
89121 #define VREF_CSR_BUF21EN_SHIFT                   (16U)
89122 /*! BUF21EN - Internal Buffer21 Enable
89123  *  0b0..Disables
89124  *  0b1..Enables
89125  */
89126 #define VREF_CSR_BUF21EN(x)                      (((uint32_t)(((uint32_t)(x)) << VREF_CSR_BUF21EN_SHIFT)) & VREF_CSR_BUF21EN_MASK)
89127 
89128 #define VREF_CSR_VREFST_MASK                     (0x80000000U)
89129 #define VREF_CSR_VREFST_SHIFT                    (31U)
89130 /*! VREFST - Internal HC Voltage Reference Stable
89131  *  0b0..Disabled and unstable
89132  *  0b1..Stable
89133  */
89134 #define VREF_CSR_VREFST(x)                       (((uint32_t)(((uint32_t)(x)) << VREF_CSR_VREFST_SHIFT)) & VREF_CSR_VREFST_MASK)
89135 /*! @} */
89136 
89137 /*! @name UTRIM - User Trim */
89138 /*! @{ */
89139 
89140 #define VREF_UTRIM_TRIM2V1_MASK                  (0xFU)
89141 #define VREF_UTRIM_TRIM2V1_SHIFT                 (0U)
89142 /*! TRIM2V1 - VREF 2.1 V Trim */
89143 #define VREF_UTRIM_TRIM2V1(x)                    (((uint32_t)(((uint32_t)(x)) << VREF_UTRIM_TRIM2V1_SHIFT)) & VREF_UTRIM_TRIM2V1_MASK)
89144 
89145 #define VREF_UTRIM_VREFTRIM_MASK                 (0x3F00U)
89146 #define VREF_UTRIM_VREFTRIM_SHIFT                (8U)
89147 /*! VREFTRIM - VREF Trim */
89148 #define VREF_UTRIM_VREFTRIM(x)                   (((uint32_t)(((uint32_t)(x)) << VREF_UTRIM_VREFTRIM_SHIFT)) & VREF_UTRIM_VREFTRIM_MASK)
89149 /*! @} */
89150 
89151 
89152 /*!
89153  * @}
89154  */ /* end of group VREF_Register_Masks */
89155 
89156 
89157 /* VREF - Peripheral instance base addresses */
89158 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
89159   /** Peripheral VREF0 base address */
89160   #define VREF0_BASE                               (0x50111000u)
89161   /** Peripheral VREF0 base address */
89162   #define VREF0_BASE_NS                            (0x40111000u)
89163   /** Peripheral VREF0 base pointer */
89164   #define VREF0                                    ((VREF_Type *)VREF0_BASE)
89165   /** Peripheral VREF0 base pointer */
89166   #define VREF0_NS                                 ((VREF_Type *)VREF0_BASE_NS)
89167   /** Array initializer of VREF peripheral base addresses */
89168   #define VREF_BASE_ADDRS                          { VREF0_BASE }
89169   /** Array initializer of VREF peripheral base pointers */
89170   #define VREF_BASE_PTRS                           { VREF0 }
89171   /** Array initializer of VREF peripheral base addresses */
89172   #define VREF_BASE_ADDRS_NS                       { VREF0_BASE_NS }
89173   /** Array initializer of VREF peripheral base pointers */
89174   #define VREF_BASE_PTRS_NS                        { VREF0_NS }
89175 #else
89176   /** Peripheral VREF0 base address */
89177   #define VREF0_BASE                               (0x40111000u)
89178   /** Peripheral VREF0 base pointer */
89179   #define VREF0                                    ((VREF_Type *)VREF0_BASE)
89180   /** Array initializer of VREF peripheral base addresses */
89181   #define VREF_BASE_ADDRS                          { VREF0_BASE }
89182   /** Array initializer of VREF peripheral base pointers */
89183   #define VREF_BASE_PTRS                           { VREF0 }
89184 #endif
89185 
89186 /*!
89187  * @}
89188  */ /* end of group VREF_Peripheral_Access_Layer */
89189 
89190 
89191 /* ----------------------------------------------------------------------------
89192    -- WUU Peripheral Access Layer
89193    ---------------------------------------------------------------------------- */
89194 
89195 /*!
89196  * @addtogroup WUU_Peripheral_Access_Layer WUU Peripheral Access Layer
89197  * @{
89198  */
89199 
89200 /** WUU - Register Layout Typedef */
89201 typedef struct {
89202   __I  uint32_t VERID;                             /**< Version ID, offset: 0x0 */
89203   __I  uint32_t PARAM;                             /**< Parameter, offset: 0x4 */
89204   __IO uint32_t PE1;                               /**< Pin Enable 1, offset: 0x8 */
89205   __IO uint32_t PE2;                               /**< Pin Enable 2, offset: 0xC */
89206        uint8_t RESERVED_0[8];
89207   __IO uint32_t ME;                                /**< Module Interrupt Enable, offset: 0x18 */
89208   __IO uint32_t DE;                                /**< Module DMA/Trigger Enable, offset: 0x1C */
89209   __IO uint32_t PF;                                /**< Pin Flag, offset: 0x20 */
89210        uint8_t RESERVED_1[12];
89211   __IO uint32_t FILT;                              /**< Pin Filter, offset: 0x30 */
89212        uint8_t RESERVED_2[4];
89213   __IO uint32_t PDC1;                              /**< Pin DMA/Trigger Configuration 1, offset: 0x38 */
89214   __IO uint32_t PDC2;                              /**< Pin DMA/Trigger Configuration 2, offset: 0x3C */
89215        uint8_t RESERVED_3[8];
89216   __IO uint32_t FDC;                               /**< Pin Filter DMA/Trigger Configuration, offset: 0x48 */
89217        uint8_t RESERVED_4[4];
89218   __IO uint32_t PMC;                               /**< Pin Mode Configuration, offset: 0x50 */
89219        uint8_t RESERVED_5[4];
89220   __IO uint32_t FMC;                               /**< Pin Filter Mode Configuration, offset: 0x58 */
89221 } WUU_Type;
89222 
89223 /* ----------------------------------------------------------------------------
89224    -- WUU Register Masks
89225    ---------------------------------------------------------------------------- */
89226 
89227 /*!
89228  * @addtogroup WUU_Register_Masks WUU Register Masks
89229  * @{
89230  */
89231 
89232 /*! @name VERID - Version ID */
89233 /*! @{ */
89234 
89235 #define WUU_VERID_FEATURE_MASK                   (0xFFFFU)
89236 #define WUU_VERID_FEATURE_SHIFT                  (0U)
89237 /*! FEATURE - Feature Specification Number
89238  *  0b0000000000000000..Standard features implemented
89239  *  0b0000000000000001..Support for DMA/Trigger generation from wake-up pins and filters enabled. Support for
89240  *                      external pin/filter detection during all power modes enabled.
89241  *  *..
89242  */
89243 #define WUU_VERID_FEATURE(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_VERID_FEATURE_SHIFT)) & WUU_VERID_FEATURE_MASK)
89244 
89245 #define WUU_VERID_MINOR_MASK                     (0xFF0000U)
89246 #define WUU_VERID_MINOR_SHIFT                    (16U)
89247 /*! MINOR - Minor Version Number */
89248 #define WUU_VERID_MINOR(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_VERID_MINOR_SHIFT)) & WUU_VERID_MINOR_MASK)
89249 
89250 #define WUU_VERID_MAJOR_MASK                     (0xFF000000U)
89251 #define WUU_VERID_MAJOR_SHIFT                    (24U)
89252 /*! MAJOR - Major Version Number */
89253 #define WUU_VERID_MAJOR(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_VERID_MAJOR_SHIFT)) & WUU_VERID_MAJOR_MASK)
89254 /*! @} */
89255 
89256 /*! @name PARAM - Parameter */
89257 /*! @{ */
89258 
89259 #define WUU_PARAM_FILTERS_MASK                   (0xFFU)
89260 #define WUU_PARAM_FILTERS_SHIFT                  (0U)
89261 /*! FILTERS - Filter Number */
89262 #define WUU_PARAM_FILTERS(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_PARAM_FILTERS_SHIFT)) & WUU_PARAM_FILTERS_MASK)
89263 
89264 #define WUU_PARAM_DMAS_MASK                      (0xFF00U)
89265 #define WUU_PARAM_DMAS_SHIFT                     (8U)
89266 /*! DMAS - DMA Number */
89267 #define WUU_PARAM_DMAS(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PARAM_DMAS_SHIFT)) & WUU_PARAM_DMAS_MASK)
89268 
89269 #define WUU_PARAM_MODULES_MASK                   (0xFF0000U)
89270 #define WUU_PARAM_MODULES_SHIFT                  (16U)
89271 /*! MODULES - Module Number */
89272 #define WUU_PARAM_MODULES(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_PARAM_MODULES_SHIFT)) & WUU_PARAM_MODULES_MASK)
89273 
89274 #define WUU_PARAM_PINS_MASK                      (0xFF000000U)
89275 #define WUU_PARAM_PINS_SHIFT                     (24U)
89276 /*! PINS - Pin Number */
89277 #define WUU_PARAM_PINS(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PARAM_PINS_SHIFT)) & WUU_PARAM_PINS_MASK)
89278 /*! @} */
89279 
89280 /*! @name PE1 - Pin Enable 1 */
89281 /*! @{ */
89282 
89283 #define WUU_PE1_WUPE0_MASK                       (0x3U)
89284 #define WUU_PE1_WUPE0_SHIFT                      (0U)
89285 /*! WUPE0 - Wake-up Pin Enable for WUU_Pn
89286  *  0b00..Disable
89287  *  0b01..Enable (detect on rising edge or high level)
89288  *  0b10..Enable (detect on falling edge or low level)
89289  *  0b11..Enable (detect on any edge)
89290  */
89291 #define WUU_PE1_WUPE0(x)                         (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE0_SHIFT)) & WUU_PE1_WUPE0_MASK)
89292 
89293 #define WUU_PE1_WUPE1_MASK                       (0xCU)
89294 #define WUU_PE1_WUPE1_SHIFT                      (2U)
89295 /*! WUPE1 - Wake-up Pin Enable for WUU_Pn
89296  *  0b00..Disable
89297  *  0b01..Enable (detect on rising edge or high level)
89298  *  0b10..Enable (detect on falling edge or low level)
89299  *  0b11..Enable (detect on any edge)
89300  */
89301 #define WUU_PE1_WUPE1(x)                         (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE1_SHIFT)) & WUU_PE1_WUPE1_MASK)
89302 
89303 #define WUU_PE1_WUPE2_MASK                       (0x30U)
89304 #define WUU_PE1_WUPE2_SHIFT                      (4U)
89305 /*! WUPE2 - Wake-up Pin Enable for WUU_Pn
89306  *  0b00..Disable
89307  *  0b01..Enable (detect on rising edge or high level)
89308  *  0b10..Enable (detect on falling edge or low level)
89309  *  0b11..Enable (detect on any edge)
89310  */
89311 #define WUU_PE1_WUPE2(x)                         (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE2_SHIFT)) & WUU_PE1_WUPE2_MASK)
89312 
89313 #define WUU_PE1_WUPE3_MASK                       (0xC0U)
89314 #define WUU_PE1_WUPE3_SHIFT                      (6U)
89315 /*! WUPE3 - Wake-up Pin Enable for WUU_Pn
89316  *  0b00..Disable
89317  *  0b01..Enable (detect on rising edge or high level)
89318  *  0b10..Enable (detect on falling edge or low level)
89319  *  0b11..Enable (detect on any edge)
89320  */
89321 #define WUU_PE1_WUPE3(x)                         (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE3_SHIFT)) & WUU_PE1_WUPE3_MASK)
89322 
89323 #define WUU_PE1_WUPE4_MASK                       (0x300U)
89324 #define WUU_PE1_WUPE4_SHIFT                      (8U)
89325 /*! WUPE4 - Wake-up Pin Enable for WUU_Pn
89326  *  0b00..Disable
89327  *  0b01..Enable (detect on rising edge or high level)
89328  *  0b10..Enable (detect on falling edge or low level)
89329  *  0b11..Enable (detect on any edge)
89330  */
89331 #define WUU_PE1_WUPE4(x)                         (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE4_SHIFT)) & WUU_PE1_WUPE4_MASK)
89332 
89333 #define WUU_PE1_WUPE5_MASK                       (0xC00U)
89334 #define WUU_PE1_WUPE5_SHIFT                      (10U)
89335 /*! WUPE5 - Wake-up Pin Enable for WUU_Pn
89336  *  0b00..Disable
89337  *  0b01..Enable (detect on rising edge or high level)
89338  *  0b10..Enable (detect on falling edge or low level)
89339  *  0b11..Enable (detect on any edge)
89340  */
89341 #define WUU_PE1_WUPE5(x)                         (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE5_SHIFT)) & WUU_PE1_WUPE5_MASK)
89342 
89343 #define WUU_PE1_WUPE6_MASK                       (0x3000U)
89344 #define WUU_PE1_WUPE6_SHIFT                      (12U)
89345 /*! WUPE6 - Wake-up Pin Enable for WUU_Pn
89346  *  0b00..Disable
89347  *  0b01..Enable (detect on rising edge or high level)
89348  *  0b10..Enable (detect on falling edge or low level)
89349  *  0b11..Enable (detect on any edge)
89350  */
89351 #define WUU_PE1_WUPE6(x)                         (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE6_SHIFT)) & WUU_PE1_WUPE6_MASK)
89352 
89353 #define WUU_PE1_WUPE7_MASK                       (0xC000U)
89354 #define WUU_PE1_WUPE7_SHIFT                      (14U)
89355 /*! WUPE7 - Wake-up Pin Enable for WUU_Pn
89356  *  0b00..Disable
89357  *  0b01..Enable (detect on rising edge or high level)
89358  *  0b10..Enable (detect on falling edge or low level)
89359  *  0b11..Enable (detect on any edge)
89360  */
89361 #define WUU_PE1_WUPE7(x)                         (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE7_SHIFT)) & WUU_PE1_WUPE7_MASK)
89362 
89363 #define WUU_PE1_WUPE8_MASK                       (0x30000U)
89364 #define WUU_PE1_WUPE8_SHIFT                      (16U)
89365 /*! WUPE8 - Wake-up Pin Enable for WUU_Pn
89366  *  0b00..Disable
89367  *  0b01..Enable (detect on rising edge or high level)
89368  *  0b10..Enable (detect on falling edge or low level)
89369  *  0b11..Enable (detect on any edge)
89370  */
89371 #define WUU_PE1_WUPE8(x)                         (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE8_SHIFT)) & WUU_PE1_WUPE8_MASK)
89372 
89373 #define WUU_PE1_WUPE9_MASK                       (0xC0000U)
89374 #define WUU_PE1_WUPE9_SHIFT                      (18U)
89375 /*! WUPE9 - Wake-up Pin Enable for WUU_Pn
89376  *  0b00..Disable
89377  *  0b01..Enable (detect on rising edge or high level)
89378  *  0b10..Enable (detect on falling edge or low level)
89379  *  0b11..Enable (detect on any edge)
89380  */
89381 #define WUU_PE1_WUPE9(x)                         (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE9_SHIFT)) & WUU_PE1_WUPE9_MASK)
89382 
89383 #define WUU_PE1_WUPE10_MASK                      (0x300000U)
89384 #define WUU_PE1_WUPE10_SHIFT                     (20U)
89385 /*! WUPE10 - Wake-up Pin Enable for WUU_Pn
89386  *  0b00..Disable
89387  *  0b01..Enable (detect on rising edge or high level)
89388  *  0b10..Enable (detect on falling edge or low level)
89389  *  0b11..Enable (detect on any edge)
89390  */
89391 #define WUU_PE1_WUPE10(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE10_SHIFT)) & WUU_PE1_WUPE10_MASK)
89392 
89393 #define WUU_PE1_WUPE11_MASK                      (0xC00000U)
89394 #define WUU_PE1_WUPE11_SHIFT                     (22U)
89395 /*! WUPE11 - Wake-up Pin Enable for WUU_Pn
89396  *  0b00..Disable
89397  *  0b01..Enable (detect on rising edge or high level)
89398  *  0b10..Enable (detect on falling edge or low level)
89399  *  0b11..Enable (detect on any edge)
89400  */
89401 #define WUU_PE1_WUPE11(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE11_SHIFT)) & WUU_PE1_WUPE11_MASK)
89402 
89403 #define WUU_PE1_WUPE12_MASK                      (0x3000000U)
89404 #define WUU_PE1_WUPE12_SHIFT                     (24U)
89405 /*! WUPE12 - Wake-up Pin Enable for WUU_Pn
89406  *  0b00..Disable
89407  *  0b01..Enable (detect on rising edge or high level)
89408  *  0b10..Enable (detect on falling edge or low level)
89409  *  0b11..Enable (detect on any edge)
89410  */
89411 #define WUU_PE1_WUPE12(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE12_SHIFT)) & WUU_PE1_WUPE12_MASK)
89412 
89413 #define WUU_PE1_WUPE13_MASK                      (0xC000000U)
89414 #define WUU_PE1_WUPE13_SHIFT                     (26U)
89415 /*! WUPE13 - Wake-up Pin Enable for WUU_Pn
89416  *  0b00..Disable
89417  *  0b01..Enable (detect on rising edge or high level)
89418  *  0b10..Enable (detect on falling edge or low level)
89419  *  0b11..Enable (detect on any edge)
89420  */
89421 #define WUU_PE1_WUPE13(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE13_SHIFT)) & WUU_PE1_WUPE13_MASK)
89422 
89423 #define WUU_PE1_WUPE14_MASK                      (0x30000000U)
89424 #define WUU_PE1_WUPE14_SHIFT                     (28U)
89425 /*! WUPE14 - Wake-up Pin Enable for WUU_Pn
89426  *  0b00..Disable
89427  *  0b01..Enable (detect on rising edge or high level)
89428  *  0b10..Enable (detect on falling edge or low level)
89429  *  0b11..Enable (detect on any edge)
89430  */
89431 #define WUU_PE1_WUPE14(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE14_SHIFT)) & WUU_PE1_WUPE14_MASK)
89432 
89433 #define WUU_PE1_WUPE15_MASK                      (0xC0000000U)
89434 #define WUU_PE1_WUPE15_SHIFT                     (30U)
89435 /*! WUPE15 - Wake-up Pin Enable for WUU_Pn
89436  *  0b00..Disable
89437  *  0b01..Enable (detect on rising edge or high level)
89438  *  0b10..Enable (detect on falling edge or low level)
89439  *  0b11..Enable (detect on any edge)
89440  */
89441 #define WUU_PE1_WUPE15(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE15_SHIFT)) & WUU_PE1_WUPE15_MASK)
89442 /*! @} */
89443 
89444 /*! @name PE2 - Pin Enable 2 */
89445 /*! @{ */
89446 
89447 #define WUU_PE2_WUPE16_MASK                      (0x3U)
89448 #define WUU_PE2_WUPE16_SHIFT                     (0U)
89449 /*! WUPE16 - Wake-up Pin Enable for WUU_Pn
89450  *  0b00..Disable
89451  *  0b01..Enable (detect on rising edge or high level)
89452  *  0b10..Enable (detect on falling edge or low level)
89453  *  0b11..Enable (detect on any edge)
89454  */
89455 #define WUU_PE2_WUPE16(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE16_SHIFT)) & WUU_PE2_WUPE16_MASK)
89456 
89457 #define WUU_PE2_WUPE17_MASK                      (0xCU)
89458 #define WUU_PE2_WUPE17_SHIFT                     (2U)
89459 /*! WUPE17 - Wake-up Pin Enable for WUU_Pn
89460  *  0b00..Disable
89461  *  0b01..Enable (detect on rising edge or high level)
89462  *  0b10..Enable (detect on falling edge or low level)
89463  *  0b11..Enable (detect on any edge)
89464  */
89465 #define WUU_PE2_WUPE17(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE17_SHIFT)) & WUU_PE2_WUPE17_MASK)
89466 
89467 #define WUU_PE2_WUPE18_MASK                      (0x30U)
89468 #define WUU_PE2_WUPE18_SHIFT                     (4U)
89469 /*! WUPE18 - Wake-up Pin Enable for WUU_Pn
89470  *  0b00..Disable
89471  *  0b01..Enable (detect on rising edge or high level)
89472  *  0b10..Enable (detect on falling edge or low level)
89473  *  0b11..Enable (detect on any edge)
89474  */
89475 #define WUU_PE2_WUPE18(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE18_SHIFT)) & WUU_PE2_WUPE18_MASK)
89476 
89477 #define WUU_PE2_WUPE19_MASK                      (0xC0U)
89478 #define WUU_PE2_WUPE19_SHIFT                     (6U)
89479 /*! WUPE19 - Wake-up Pin Enable for WUU_Pn
89480  *  0b00..Disable
89481  *  0b01..Enable (detect on rising edge or high level)
89482  *  0b10..Enable (detect on falling edge or low level)
89483  *  0b11..Enable (detect on any edge)
89484  */
89485 #define WUU_PE2_WUPE19(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE19_SHIFT)) & WUU_PE2_WUPE19_MASK)
89486 
89487 #define WUU_PE2_WUPE20_MASK                      (0x300U)
89488 #define WUU_PE2_WUPE20_SHIFT                     (8U)
89489 /*! WUPE20 - Wake-up Pin Enable for WUU_Pn
89490  *  0b00..Disable
89491  *  0b01..Enable (detect on rising edge or high level)
89492  *  0b10..Enable (detect on falling edge or low level)
89493  *  0b11..Enable (detect on any edge)
89494  */
89495 #define WUU_PE2_WUPE20(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE20_SHIFT)) & WUU_PE2_WUPE20_MASK)
89496 
89497 #define WUU_PE2_WUPE21_MASK                      (0xC00U)
89498 #define WUU_PE2_WUPE21_SHIFT                     (10U)
89499 /*! WUPE21 - Wake-up Pin Enable for WUU_Pn
89500  *  0b00..Disable
89501  *  0b01..Enable (detect on rising edge or high level)
89502  *  0b10..Enable (detect on falling edge or low level)
89503  *  0b11..Enable (detect on any edge)
89504  */
89505 #define WUU_PE2_WUPE21(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE21_SHIFT)) & WUU_PE2_WUPE21_MASK)
89506 
89507 #define WUU_PE2_WUPE22_MASK                      (0x3000U)
89508 #define WUU_PE2_WUPE22_SHIFT                     (12U)
89509 /*! WUPE22 - Wake-up Pin Enable for WUU_Pn
89510  *  0b00..Disable
89511  *  0b01..Enable (detect on rising edge or high level)
89512  *  0b10..Enable (detect on falling edge or low level)
89513  *  0b11..Enable (detect on any edge)
89514  */
89515 #define WUU_PE2_WUPE22(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE22_SHIFT)) & WUU_PE2_WUPE22_MASK)
89516 
89517 #define WUU_PE2_WUPE23_MASK                      (0xC000U)
89518 #define WUU_PE2_WUPE23_SHIFT                     (14U)
89519 /*! WUPE23 - Wake-up Pin Enable for WUU_Pn
89520  *  0b00..Disable
89521  *  0b01..Enable (detect on rising edge or high level)
89522  *  0b10..Enable (detect on falling edge or low level)
89523  *  0b11..Enable (detect on any edge)
89524  */
89525 #define WUU_PE2_WUPE23(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE23_SHIFT)) & WUU_PE2_WUPE23_MASK)
89526 
89527 #define WUU_PE2_WUPE24_MASK                      (0x30000U)
89528 #define WUU_PE2_WUPE24_SHIFT                     (16U)
89529 /*! WUPE24 - Wake-up Pin Enable for WUU_Pn
89530  *  0b00..Disable
89531  *  0b01..Enable (detect on rising edge or high level)
89532  *  0b10..Enable (detect on falling edge or low level)
89533  *  0b11..Enable (detect on any edge)
89534  */
89535 #define WUU_PE2_WUPE24(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE24_SHIFT)) & WUU_PE2_WUPE24_MASK)
89536 
89537 #define WUU_PE2_WUPE25_MASK                      (0xC0000U)
89538 #define WUU_PE2_WUPE25_SHIFT                     (18U)
89539 /*! WUPE25 - Wake-up Pin Enable for WUU_Pn
89540  *  0b00..Disable
89541  *  0b01..Enable (detect on rising edge or high level)
89542  *  0b10..Enable (detect on falling edge or low level)
89543  *  0b11..Enable (detect on any edge)
89544  */
89545 #define WUU_PE2_WUPE25(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE25_SHIFT)) & WUU_PE2_WUPE25_MASK)
89546 
89547 #define WUU_PE2_WUPE26_MASK                      (0x300000U)
89548 #define WUU_PE2_WUPE26_SHIFT                     (20U)
89549 /*! WUPE26 - Wake-up Pin Enable for WUU_Pn
89550  *  0b00..Disable
89551  *  0b01..Enable (detect on rising edge or high level)
89552  *  0b10..Enable (detect on falling edge or low level)
89553  *  0b11..Enable (detect on any edge)
89554  */
89555 #define WUU_PE2_WUPE26(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE26_SHIFT)) & WUU_PE2_WUPE26_MASK)
89556 
89557 #define WUU_PE2_WUPE27_MASK                      (0xC00000U)
89558 #define WUU_PE2_WUPE27_SHIFT                     (22U)
89559 /*! WUPE27 - Wake-up Pin Enable for WUU_Pn
89560  *  0b00..Disable
89561  *  0b01..Enable (detect on rising edge or high level)
89562  *  0b10..Enable (detect on falling edge or low level)
89563  *  0b11..Enable (detect on any edge)
89564  */
89565 #define WUU_PE2_WUPE27(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE27_SHIFT)) & WUU_PE2_WUPE27_MASK)
89566 
89567 #define WUU_PE2_WUPE28_MASK                      (0x3000000U)
89568 #define WUU_PE2_WUPE28_SHIFT                     (24U)
89569 /*! WUPE28 - Wake-up Pin Enable for WUU_Pn
89570  *  0b00..Disable
89571  *  0b01..Enable (detect on rising edge or high level)
89572  *  0b10..Enable (detect on falling edge or low level)
89573  *  0b11..Enable (detect on any edge)
89574  */
89575 #define WUU_PE2_WUPE28(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE28_SHIFT)) & WUU_PE2_WUPE28_MASK)
89576 
89577 #define WUU_PE2_WUPE29_MASK                      (0xC000000U)
89578 #define WUU_PE2_WUPE29_SHIFT                     (26U)
89579 /*! WUPE29 - Wake-up Pin Enable for WUU_Pn
89580  *  0b00..Disable
89581  *  0b01..Enable (detect on rising edge or high level)
89582  *  0b10..Enable (detect on falling edge or low level)
89583  *  0b11..Enable (detect on any edge)
89584  */
89585 #define WUU_PE2_WUPE29(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE29_SHIFT)) & WUU_PE2_WUPE29_MASK)
89586 
89587 #define WUU_PE2_WUPE30_MASK                      (0x30000000U)
89588 #define WUU_PE2_WUPE30_SHIFT                     (28U)
89589 /*! WUPE30 - Wake-up Pin Enable for WUU_Pn
89590  *  0b00..Disable
89591  *  0b01..Enable (detect on rising edge or high level)
89592  *  0b10..Enable (detect on falling edge or low level)
89593  *  0b11..Enable (detect on any edge)
89594  */
89595 #define WUU_PE2_WUPE30(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE30_SHIFT)) & WUU_PE2_WUPE30_MASK)
89596 
89597 #define WUU_PE2_WUPE31_MASK                      (0xC0000000U)
89598 #define WUU_PE2_WUPE31_SHIFT                     (30U)
89599 /*! WUPE31 - Wake-up Pin Enable for WUU_Pn
89600  *  0b00..Disable
89601  *  0b01..Enable (detect on rising edge or high level)
89602  *  0b10..Enable (detect on falling edge or low level)
89603  *  0b11..Enable (detect on any edge)
89604  */
89605 #define WUU_PE2_WUPE31(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE31_SHIFT)) & WUU_PE2_WUPE31_MASK)
89606 /*! @} */
89607 
89608 /*! @name ME - Module Interrupt Enable */
89609 /*! @{ */
89610 
89611 #define WUU_ME_WUME0_MASK                        (0x1U)
89612 #define WUU_ME_WUME0_SHIFT                       (0U)
89613 /*! WUME0 - Module Interrupt Wake-up Enable for Module 0
89614  *  0b0..Disable
89615  *  0b1..Enable
89616  */
89617 #define WUU_ME_WUME0(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME0_SHIFT)) & WUU_ME_WUME0_MASK)
89618 
89619 #define WUU_ME_WUME1_MASK                        (0x2U)
89620 #define WUU_ME_WUME1_SHIFT                       (1U)
89621 /*! WUME1 - Module Interrupt Wake-up Enable for Module 1
89622  *  0b0..Disable
89623  *  0b1..Enable
89624  */
89625 #define WUU_ME_WUME1(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME1_SHIFT)) & WUU_ME_WUME1_MASK)
89626 
89627 #define WUU_ME_WUME2_MASK                        (0x4U)
89628 #define WUU_ME_WUME2_SHIFT                       (2U)
89629 /*! WUME2 - Module Interrupt Wake-up Enable for Module 2
89630  *  0b0..Disable
89631  *  0b1..Enable
89632  */
89633 #define WUU_ME_WUME2(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME2_SHIFT)) & WUU_ME_WUME2_MASK)
89634 
89635 #define WUU_ME_WUME3_MASK                        (0x8U)
89636 #define WUU_ME_WUME3_SHIFT                       (3U)
89637 /*! WUME3 - Module Interrupt Wake-up Enable for Module 3
89638  *  0b0..Disable
89639  *  0b1..Enable
89640  */
89641 #define WUU_ME_WUME3(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME3_SHIFT)) & WUU_ME_WUME3_MASK)
89642 
89643 #define WUU_ME_WUME4_MASK                        (0x10U)
89644 #define WUU_ME_WUME4_SHIFT                       (4U)
89645 /*! WUME4 - Module Interrupt Wake-up Enable for Module 4
89646  *  0b0..Disable
89647  *  0b1..Enable
89648  */
89649 #define WUU_ME_WUME4(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME4_SHIFT)) & WUU_ME_WUME4_MASK)
89650 
89651 #define WUU_ME_WUME5_MASK                        (0x20U)
89652 #define WUU_ME_WUME5_SHIFT                       (5U)
89653 /*! WUME5 - Module Interrupt Wake-up Enable for Module 5
89654  *  0b0..Disable
89655  *  0b1..Enable
89656  */
89657 #define WUU_ME_WUME5(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME5_SHIFT)) & WUU_ME_WUME5_MASK)
89658 
89659 #define WUU_ME_WUME6_MASK                        (0x40U)
89660 #define WUU_ME_WUME6_SHIFT                       (6U)
89661 /*! WUME6 - Module Interrupt Wake-up Enable for Module 6
89662  *  0b0..Disable
89663  *  0b1..Enable
89664  */
89665 #define WUU_ME_WUME6(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME6_SHIFT)) & WUU_ME_WUME6_MASK)
89666 
89667 #define WUU_ME_WUME7_MASK                        (0x80U)
89668 #define WUU_ME_WUME7_SHIFT                       (7U)
89669 /*! WUME7 - Module Interrupt Wake-up Enable for Module 7
89670  *  0b0..Disable
89671  *  0b1..Enable
89672  */
89673 #define WUU_ME_WUME7(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME7_SHIFT)) & WUU_ME_WUME7_MASK)
89674 
89675 #define WUU_ME_WUME8_MASK                        (0x100U)
89676 #define WUU_ME_WUME8_SHIFT                       (8U)
89677 /*! WUME8 - Module Interrupt Wake-up Enable for Module 8
89678  *  0b0..Disable
89679  *  0b1..Enable
89680  */
89681 #define WUU_ME_WUME8(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME8_SHIFT)) & WUU_ME_WUME8_MASK)
89682 
89683 #define WUU_ME_WUME9_MASK                        (0x200U)
89684 #define WUU_ME_WUME9_SHIFT                       (9U)
89685 /*! WUME9 - Module Interrupt Wake-up Enable for Module 9
89686  *  0b0..Disable
89687  *  0b1..Enable
89688  */
89689 #define WUU_ME_WUME9(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME9_SHIFT)) & WUU_ME_WUME9_MASK)
89690 /*! @} */
89691 
89692 /*! @name DE - Module DMA/Trigger Enable */
89693 /*! @{ */
89694 
89695 #define WUU_DE_WUDE0_MASK                        (0x1U)
89696 #define WUU_DE_WUDE0_SHIFT                       (0U)
89697 /*! WUDE0 - DMA/Trigger Wake-up Enable for Module 0
89698  *  0b0..Disable
89699  *  0b1..Enable
89700  */
89701 #define WUU_DE_WUDE0(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE0_SHIFT)) & WUU_DE_WUDE0_MASK)
89702 
89703 #define WUU_DE_WUDE1_MASK                        (0x2U)
89704 #define WUU_DE_WUDE1_SHIFT                       (1U)
89705 /*! WUDE1 - DMA/Trigger Wake-up Enable for Module 1
89706  *  0b0..Disable
89707  *  0b1..Enable
89708  */
89709 #define WUU_DE_WUDE1(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE1_SHIFT)) & WUU_DE_WUDE1_MASK)
89710 
89711 #define WUU_DE_WUDE2_MASK                        (0x4U)
89712 #define WUU_DE_WUDE2_SHIFT                       (2U)
89713 /*! WUDE2 - DMA/Trigger Wake-up Enable for Module 2
89714  *  0b0..Disable
89715  *  0b1..Enable
89716  */
89717 #define WUU_DE_WUDE2(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE2_SHIFT)) & WUU_DE_WUDE2_MASK)
89718 
89719 #define WUU_DE_WUDE3_MASK                        (0x8U)
89720 #define WUU_DE_WUDE3_SHIFT                       (3U)
89721 /*! WUDE3 - DMA/Trigger Wake-up Enable for Module 3
89722  *  0b0..Disable
89723  *  0b1..Enable
89724  */
89725 #define WUU_DE_WUDE3(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE3_SHIFT)) & WUU_DE_WUDE3_MASK)
89726 
89727 #define WUU_DE_WUDE4_MASK                        (0x10U)
89728 #define WUU_DE_WUDE4_SHIFT                       (4U)
89729 /*! WUDE4 - DMA/Trigger Wake-up Enable for Module 4
89730  *  0b0..Disable
89731  *  0b1..Enable
89732  */
89733 #define WUU_DE_WUDE4(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE4_SHIFT)) & WUU_DE_WUDE4_MASK)
89734 
89735 #define WUU_DE_WUDE5_MASK                        (0x20U)
89736 #define WUU_DE_WUDE5_SHIFT                       (5U)
89737 /*! WUDE5 - DMA/Trigger Wake-up Enable for Module 5
89738  *  0b0..Disable
89739  *  0b1..Enable
89740  */
89741 #define WUU_DE_WUDE5(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE5_SHIFT)) & WUU_DE_WUDE5_MASK)
89742 
89743 #define WUU_DE_WUDE6_MASK                        (0x40U)
89744 #define WUU_DE_WUDE6_SHIFT                       (6U)
89745 /*! WUDE6 - DMA/Trigger Wake-up Enable for Module 6
89746  *  0b0..Disable
89747  *  0b1..Enable
89748  */
89749 #define WUU_DE_WUDE6(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE6_SHIFT)) & WUU_DE_WUDE6_MASK)
89750 
89751 #define WUU_DE_WUDE7_MASK                        (0x80U)
89752 #define WUU_DE_WUDE7_SHIFT                       (7U)
89753 /*! WUDE7 - DMA/Trigger Wake-up Enable for Module 7
89754  *  0b0..Disable
89755  *  0b1..Enable
89756  */
89757 #define WUU_DE_WUDE7(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE7_SHIFT)) & WUU_DE_WUDE7_MASK)
89758 
89759 #define WUU_DE_WUDE8_MASK                        (0x100U)
89760 #define WUU_DE_WUDE8_SHIFT                       (8U)
89761 /*! WUDE8 - DMA/Trigger Wake-up Enable for Module 8
89762  *  0b0..Disable
89763  *  0b1..Enable
89764  */
89765 #define WUU_DE_WUDE8(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE8_SHIFT)) & WUU_DE_WUDE8_MASK)
89766 
89767 #define WUU_DE_WUDE9_MASK                        (0x200U)
89768 #define WUU_DE_WUDE9_SHIFT                       (9U)
89769 /*! WUDE9 - DMA/Trigger Wake-up Enable for Module 9
89770  *  0b0..Disable
89771  *  0b1..Enable
89772  */
89773 #define WUU_DE_WUDE9(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE9_SHIFT)) & WUU_DE_WUDE9_MASK)
89774 /*! @} */
89775 
89776 /*! @name PF - Pin Flag */
89777 /*! @{ */
89778 
89779 #define WUU_PF_WUF0_MASK                         (0x1U)
89780 #define WUU_PF_WUF0_SHIFT                        (0U)
89781 /*! WUF0 - Wake-up Flag for WUU_Pn
89782  *  0b0..No
89783  *  0b1..Yes
89784  */
89785 #define WUU_PF_WUF0(x)                           (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF0_SHIFT)) & WUU_PF_WUF0_MASK)
89786 
89787 #define WUU_PF_WUF1_MASK                         (0x2U)
89788 #define WUU_PF_WUF1_SHIFT                        (1U)
89789 /*! WUF1 - Wake-up Flag for WUU_Pn
89790  *  0b0..No
89791  *  0b1..Yes
89792  */
89793 #define WUU_PF_WUF1(x)                           (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF1_SHIFT)) & WUU_PF_WUF1_MASK)
89794 
89795 #define WUU_PF_WUF2_MASK                         (0x4U)
89796 #define WUU_PF_WUF2_SHIFT                        (2U)
89797 /*! WUF2 - Wake-up Flag for WUU_Pn
89798  *  0b0..No
89799  *  0b1..Yes
89800  */
89801 #define WUU_PF_WUF2(x)                           (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF2_SHIFT)) & WUU_PF_WUF2_MASK)
89802 
89803 #define WUU_PF_WUF3_MASK                         (0x8U)
89804 #define WUU_PF_WUF3_SHIFT                        (3U)
89805 /*! WUF3 - Wake-up Flag for WUU_Pn
89806  *  0b0..No
89807  *  0b1..Yes
89808  */
89809 #define WUU_PF_WUF3(x)                           (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF3_SHIFT)) & WUU_PF_WUF3_MASK)
89810 
89811 #define WUU_PF_WUF4_MASK                         (0x10U)
89812 #define WUU_PF_WUF4_SHIFT                        (4U)
89813 /*! WUF4 - Wake-up Flag for WUU_Pn
89814  *  0b0..No
89815  *  0b1..Yes
89816  */
89817 #define WUU_PF_WUF4(x)                           (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF4_SHIFT)) & WUU_PF_WUF4_MASK)
89818 
89819 #define WUU_PF_WUF5_MASK                         (0x20U)
89820 #define WUU_PF_WUF5_SHIFT                        (5U)
89821 /*! WUF5 - Wake-up Flag for WUU_Pn
89822  *  0b0..No
89823  *  0b1..Yes
89824  */
89825 #define WUU_PF_WUF5(x)                           (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF5_SHIFT)) & WUU_PF_WUF5_MASK)
89826 
89827 #define WUU_PF_WUF6_MASK                         (0x40U)
89828 #define WUU_PF_WUF6_SHIFT                        (6U)
89829 /*! WUF6 - Wake-up Flag for WUU_Pn
89830  *  0b0..No
89831  *  0b1..Yes
89832  */
89833 #define WUU_PF_WUF6(x)                           (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF6_SHIFT)) & WUU_PF_WUF6_MASK)
89834 
89835 #define WUU_PF_WUF7_MASK                         (0x80U)
89836 #define WUU_PF_WUF7_SHIFT                        (7U)
89837 /*! WUF7 - Wake-up Flag for WUU_Pn
89838  *  0b0..No
89839  *  0b1..Yes
89840  */
89841 #define WUU_PF_WUF7(x)                           (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF7_SHIFT)) & WUU_PF_WUF7_MASK)
89842 
89843 #define WUU_PF_WUF8_MASK                         (0x100U)
89844 #define WUU_PF_WUF8_SHIFT                        (8U)
89845 /*! WUF8 - Wake-up Flag for WUU_Pn
89846  *  0b0..No
89847  *  0b1..Yes
89848  */
89849 #define WUU_PF_WUF8(x)                           (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF8_SHIFT)) & WUU_PF_WUF8_MASK)
89850 
89851 #define WUU_PF_WUF9_MASK                         (0x200U)
89852 #define WUU_PF_WUF9_SHIFT                        (9U)
89853 /*! WUF9 - Wake-up Flag for WUU_Pn
89854  *  0b0..No
89855  *  0b1..Yes
89856  */
89857 #define WUU_PF_WUF9(x)                           (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF9_SHIFT)) & WUU_PF_WUF9_MASK)
89858 
89859 #define WUU_PF_WUF10_MASK                        (0x400U)
89860 #define WUU_PF_WUF10_SHIFT                       (10U)
89861 /*! WUF10 - Wake-up Flag for WUU_Pn
89862  *  0b0..No
89863  *  0b1..Yes
89864  */
89865 #define WUU_PF_WUF10(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF10_SHIFT)) & WUU_PF_WUF10_MASK)
89866 
89867 #define WUU_PF_WUF11_MASK                        (0x800U)
89868 #define WUU_PF_WUF11_SHIFT                       (11U)
89869 /*! WUF11 - Wake-up Flag for WUU_Pn
89870  *  0b0..No
89871  *  0b1..Yes
89872  */
89873 #define WUU_PF_WUF11(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF11_SHIFT)) & WUU_PF_WUF11_MASK)
89874 
89875 #define WUU_PF_WUF12_MASK                        (0x1000U)
89876 #define WUU_PF_WUF12_SHIFT                       (12U)
89877 /*! WUF12 - Wake-up Flag for WUU_Pn
89878  *  0b0..No
89879  *  0b1..Yes
89880  */
89881 #define WUU_PF_WUF12(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF12_SHIFT)) & WUU_PF_WUF12_MASK)
89882 
89883 #define WUU_PF_WUF13_MASK                        (0x2000U)
89884 #define WUU_PF_WUF13_SHIFT                       (13U)
89885 /*! WUF13 - Wake-up Flag for WUU_Pn
89886  *  0b0..No
89887  *  0b1..Yes
89888  */
89889 #define WUU_PF_WUF13(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF13_SHIFT)) & WUU_PF_WUF13_MASK)
89890 
89891 #define WUU_PF_WUF14_MASK                        (0x4000U)
89892 #define WUU_PF_WUF14_SHIFT                       (14U)
89893 /*! WUF14 - Wake-up Flag for WUU_Pn
89894  *  0b0..No
89895  *  0b1..Yes
89896  */
89897 #define WUU_PF_WUF14(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF14_SHIFT)) & WUU_PF_WUF14_MASK)
89898 
89899 #define WUU_PF_WUF15_MASK                        (0x8000U)
89900 #define WUU_PF_WUF15_SHIFT                       (15U)
89901 /*! WUF15 - Wake-up Flag for WUU_Pn
89902  *  0b0..No
89903  *  0b1..Yes
89904  */
89905 #define WUU_PF_WUF15(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF15_SHIFT)) & WUU_PF_WUF15_MASK)
89906 
89907 #define WUU_PF_WUF16_MASK                        (0x10000U)
89908 #define WUU_PF_WUF16_SHIFT                       (16U)
89909 /*! WUF16 - Wake-up Flag for WUU_Pn
89910  *  0b0..No
89911  *  0b1..Yes
89912  */
89913 #define WUU_PF_WUF16(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF16_SHIFT)) & WUU_PF_WUF16_MASK)
89914 
89915 #define WUU_PF_WUF17_MASK                        (0x20000U)
89916 #define WUU_PF_WUF17_SHIFT                       (17U)
89917 /*! WUF17 - Wake-up Flag for WUU_Pn
89918  *  0b0..No
89919  *  0b1..Yes
89920  */
89921 #define WUU_PF_WUF17(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF17_SHIFT)) & WUU_PF_WUF17_MASK)
89922 
89923 #define WUU_PF_WUF18_MASK                        (0x40000U)
89924 #define WUU_PF_WUF18_SHIFT                       (18U)
89925 /*! WUF18 - Wake-up Flag for WUU_Pn
89926  *  0b0..No
89927  *  0b1..Yes
89928  */
89929 #define WUU_PF_WUF18(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF18_SHIFT)) & WUU_PF_WUF18_MASK)
89930 
89931 #define WUU_PF_WUF19_MASK                        (0x80000U)
89932 #define WUU_PF_WUF19_SHIFT                       (19U)
89933 /*! WUF19 - Wake-up Flag for WUU_Pn
89934  *  0b0..No
89935  *  0b1..Yes
89936  */
89937 #define WUU_PF_WUF19(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF19_SHIFT)) & WUU_PF_WUF19_MASK)
89938 
89939 #define WUU_PF_WUF20_MASK                        (0x100000U)
89940 #define WUU_PF_WUF20_SHIFT                       (20U)
89941 /*! WUF20 - Wake-up Flag for WUU_Pn
89942  *  0b0..No
89943  *  0b1..Yes
89944  */
89945 #define WUU_PF_WUF20(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF20_SHIFT)) & WUU_PF_WUF20_MASK)
89946 
89947 #define WUU_PF_WUF21_MASK                        (0x200000U)
89948 #define WUU_PF_WUF21_SHIFT                       (21U)
89949 /*! WUF21 - Wake-up Flag for WUU_Pn
89950  *  0b0..No
89951  *  0b1..Yes
89952  */
89953 #define WUU_PF_WUF21(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF21_SHIFT)) & WUU_PF_WUF21_MASK)
89954 
89955 #define WUU_PF_WUF22_MASK                        (0x400000U)
89956 #define WUU_PF_WUF22_SHIFT                       (22U)
89957 /*! WUF22 - Wake-up Flag for WUU_Pn
89958  *  0b0..No
89959  *  0b1..Yes
89960  */
89961 #define WUU_PF_WUF22(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF22_SHIFT)) & WUU_PF_WUF22_MASK)
89962 
89963 #define WUU_PF_WUF23_MASK                        (0x800000U)
89964 #define WUU_PF_WUF23_SHIFT                       (23U)
89965 /*! WUF23 - Wake-up Flag for WUU_Pn
89966  *  0b0..No
89967  *  0b1..Yes
89968  */
89969 #define WUU_PF_WUF23(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF23_SHIFT)) & WUU_PF_WUF23_MASK)
89970 
89971 #define WUU_PF_WUF24_MASK                        (0x1000000U)
89972 #define WUU_PF_WUF24_SHIFT                       (24U)
89973 /*! WUF24 - Wake-up Flag for WUU_Pn
89974  *  0b0..No
89975  *  0b1..Yes
89976  */
89977 #define WUU_PF_WUF24(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF24_SHIFT)) & WUU_PF_WUF24_MASK)
89978 
89979 #define WUU_PF_WUF25_MASK                        (0x2000000U)
89980 #define WUU_PF_WUF25_SHIFT                       (25U)
89981 /*! WUF25 - Wake-up Flag for WUU_Pn
89982  *  0b0..No
89983  *  0b1..Yes
89984  */
89985 #define WUU_PF_WUF25(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF25_SHIFT)) & WUU_PF_WUF25_MASK)
89986 
89987 #define WUU_PF_WUF26_MASK                        (0x4000000U)
89988 #define WUU_PF_WUF26_SHIFT                       (26U)
89989 /*! WUF26 - Wake-up Flag for WUU_Pn
89990  *  0b0..No
89991  *  0b1..Yes
89992  */
89993 #define WUU_PF_WUF26(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF26_SHIFT)) & WUU_PF_WUF26_MASK)
89994 
89995 #define WUU_PF_WUF27_MASK                        (0x8000000U)
89996 #define WUU_PF_WUF27_SHIFT                       (27U)
89997 /*! WUF27 - Wake-up Flag for WUU_Pn
89998  *  0b0..No
89999  *  0b1..Yes
90000  */
90001 #define WUU_PF_WUF27(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF27_SHIFT)) & WUU_PF_WUF27_MASK)
90002 
90003 #define WUU_PF_WUF28_MASK                        (0x10000000U)
90004 #define WUU_PF_WUF28_SHIFT                       (28U)
90005 /*! WUF28 - Wake-up Flag for WUU_Pn
90006  *  0b0..No
90007  *  0b1..Yes
90008  */
90009 #define WUU_PF_WUF28(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF28_SHIFT)) & WUU_PF_WUF28_MASK)
90010 
90011 #define WUU_PF_WUF29_MASK                        (0x20000000U)
90012 #define WUU_PF_WUF29_SHIFT                       (29U)
90013 /*! WUF29 - Wake-up Flag for WUU_Pn
90014  *  0b0..No
90015  *  0b1..Yes
90016  */
90017 #define WUU_PF_WUF29(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF29_SHIFT)) & WUU_PF_WUF29_MASK)
90018 
90019 #define WUU_PF_WUF30_MASK                        (0x40000000U)
90020 #define WUU_PF_WUF30_SHIFT                       (30U)
90021 /*! WUF30 - Wake-up Flag for WUU_Pn
90022  *  0b0..No
90023  *  0b1..Yes
90024  */
90025 #define WUU_PF_WUF30(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF30_SHIFT)) & WUU_PF_WUF30_MASK)
90026 
90027 #define WUU_PF_WUF31_MASK                        (0x80000000U)
90028 #define WUU_PF_WUF31_SHIFT                       (31U)
90029 /*! WUF31 - Wake-up Flag for WUU_Pn
90030  *  0b0..No
90031  *  0b1..Yes
90032  */
90033 #define WUU_PF_WUF31(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF31_SHIFT)) & WUU_PF_WUF31_MASK)
90034 /*! @} */
90035 
90036 /*! @name FILT - Pin Filter */
90037 /*! @{ */
90038 
90039 #define WUU_FILT_FILTSEL1_MASK                   (0x1FU)
90040 #define WUU_FILT_FILTSEL1_SHIFT                  (0U)
90041 /*! FILTSEL1 - Filter 1 Pin Select */
90042 #define WUU_FILT_FILTSEL1(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_FILT_FILTSEL1_SHIFT)) & WUU_FILT_FILTSEL1_MASK)
90043 
90044 #define WUU_FILT_FILTE1_MASK                     (0x60U)
90045 #define WUU_FILT_FILTE1_SHIFT                    (5U)
90046 /*! FILTE1 - Filter 1 Enable
90047  *  0b00..Disable
90048  *  0b01..Enable (Detect on rising edge or high level)
90049  *  0b10..Enable (Detect on falling edge or low level)
90050  *  0b11..Enable (Detect on any edge)
90051  */
90052 #define WUU_FILT_FILTE1(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_FILT_FILTE1_SHIFT)) & WUU_FILT_FILTE1_MASK)
90053 
90054 #define WUU_FILT_FILTF1_MASK                     (0x80U)
90055 #define WUU_FILT_FILTF1_SHIFT                    (7U)
90056 /*! FILTF1 - Filter 1 Flag
90057  *  0b0..No
90058  *  0b1..Yes
90059  */
90060 #define WUU_FILT_FILTF1(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_FILT_FILTF1_SHIFT)) & WUU_FILT_FILTF1_MASK)
90061 
90062 #define WUU_FILT_FILTSEL2_MASK                   (0x1F00U)
90063 #define WUU_FILT_FILTSEL2_SHIFT                  (8U)
90064 /*! FILTSEL2 - Filter 2 Pin Select */
90065 #define WUU_FILT_FILTSEL2(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_FILT_FILTSEL2_SHIFT)) & WUU_FILT_FILTSEL2_MASK)
90066 
90067 #define WUU_FILT_FILTE2_MASK                     (0x6000U)
90068 #define WUU_FILT_FILTE2_SHIFT                    (13U)
90069 /*! FILTE2 - Filter 2 Enable
90070  *  0b00..Disable
90071  *  0b01..Enable (Detect on rising edge or high level)
90072  *  0b10..Enable (Detect on falling edge or low level)
90073  *  0b11..Enable (Detect on any edge)
90074  */
90075 #define WUU_FILT_FILTE2(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_FILT_FILTE2_SHIFT)) & WUU_FILT_FILTE2_MASK)
90076 
90077 #define WUU_FILT_FILTF2_MASK                     (0x8000U)
90078 #define WUU_FILT_FILTF2_SHIFT                    (15U)
90079 /*! FILTF2 - Filter 2 Flag
90080  *  0b0..No
90081  *  0b1..Yes
90082  */
90083 #define WUU_FILT_FILTF2(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_FILT_FILTF2_SHIFT)) & WUU_FILT_FILTF2_MASK)
90084 /*! @} */
90085 
90086 /*! @name PDC1 - Pin DMA/Trigger Configuration 1 */
90087 /*! @{ */
90088 
90089 #define WUU_PDC1_WUPDC0_MASK                     (0x3U)
90090 #define WUU_PDC1_WUPDC0_SHIFT                    (0U)
90091 /*! WUPDC0 - Wake-up Pin Configuration for WUU_Pn
90092  *  0b00..Interrupt
90093  *  0b01..DMA request
90094  *  0b10..Trigger event
90095  *  0b11..Reserved
90096  */
90097 #define WUU_PDC1_WUPDC0(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC0_SHIFT)) & WUU_PDC1_WUPDC0_MASK)
90098 
90099 #define WUU_PDC1_WUPDC1_MASK                     (0xCU)
90100 #define WUU_PDC1_WUPDC1_SHIFT                    (2U)
90101 /*! WUPDC1 - Wake-up Pin Configuration for WUU_Pn
90102  *  0b00..Interrupt
90103  *  0b01..DMA request
90104  *  0b10..Trigger event
90105  *  0b11..Reserved
90106  */
90107 #define WUU_PDC1_WUPDC1(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC1_SHIFT)) & WUU_PDC1_WUPDC1_MASK)
90108 
90109 #define WUU_PDC1_WUPDC2_MASK                     (0x30U)
90110 #define WUU_PDC1_WUPDC2_SHIFT                    (4U)
90111 /*! WUPDC2 - Wake-up Pin Configuration for WUU_Pn
90112  *  0b00..Interrupt
90113  *  0b01..DMA request
90114  *  0b10..Trigger event
90115  *  0b11..Reserved
90116  */
90117 #define WUU_PDC1_WUPDC2(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC2_SHIFT)) & WUU_PDC1_WUPDC2_MASK)
90118 
90119 #define WUU_PDC1_WUPDC3_MASK                     (0xC0U)
90120 #define WUU_PDC1_WUPDC3_SHIFT                    (6U)
90121 /*! WUPDC3 - Wake-up Pin Configuration for WUU_Pn
90122  *  0b00..Interrupt
90123  *  0b01..DMA request
90124  *  0b10..Trigger event
90125  *  0b11..Reserved
90126  */
90127 #define WUU_PDC1_WUPDC3(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC3_SHIFT)) & WUU_PDC1_WUPDC3_MASK)
90128 
90129 #define WUU_PDC1_WUPDC4_MASK                     (0x300U)
90130 #define WUU_PDC1_WUPDC4_SHIFT                    (8U)
90131 /*! WUPDC4 - Wake-up Pin Configuration for WUU_Pn
90132  *  0b00..Interrupt
90133  *  0b01..DMA request
90134  *  0b10..Trigger event
90135  *  0b11..Reserved
90136  */
90137 #define WUU_PDC1_WUPDC4(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC4_SHIFT)) & WUU_PDC1_WUPDC4_MASK)
90138 
90139 #define WUU_PDC1_WUPDC5_MASK                     (0xC00U)
90140 #define WUU_PDC1_WUPDC5_SHIFT                    (10U)
90141 /*! WUPDC5 - Wake-up Pin Configuration for WUU_Pn
90142  *  0b00..Interrupt
90143  *  0b01..DMA request
90144  *  0b10..Trigger event
90145  *  0b11..Reserved
90146  */
90147 #define WUU_PDC1_WUPDC5(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC5_SHIFT)) & WUU_PDC1_WUPDC5_MASK)
90148 
90149 #define WUU_PDC1_WUPDC6_MASK                     (0x3000U)
90150 #define WUU_PDC1_WUPDC6_SHIFT                    (12U)
90151 /*! WUPDC6 - Wake-up Pin Configuration for WUU_Pn
90152  *  0b00..Interrupt
90153  *  0b01..DMA request
90154  *  0b10..Trigger event
90155  *  0b11..Reserved
90156  */
90157 #define WUU_PDC1_WUPDC6(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC6_SHIFT)) & WUU_PDC1_WUPDC6_MASK)
90158 
90159 #define WUU_PDC1_WUPDC7_MASK                     (0xC000U)
90160 #define WUU_PDC1_WUPDC7_SHIFT                    (14U)
90161 /*! WUPDC7 - Wake-up Pin Configuration for WUU_Pn
90162  *  0b00..Interrupt
90163  *  0b01..DMA request
90164  *  0b10..Trigger event
90165  *  0b11..Reserved
90166  */
90167 #define WUU_PDC1_WUPDC7(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC7_SHIFT)) & WUU_PDC1_WUPDC7_MASK)
90168 
90169 #define WUU_PDC1_WUPDC8_MASK                     (0x30000U)
90170 #define WUU_PDC1_WUPDC8_SHIFT                    (16U)
90171 /*! WUPDC8 - Wake-up Pin Configuration for WUU_Pn
90172  *  0b00..Interrupt
90173  *  0b01..DMA request
90174  *  0b10..Trigger event
90175  *  0b11..Reserved
90176  */
90177 #define WUU_PDC1_WUPDC8(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC8_SHIFT)) & WUU_PDC1_WUPDC8_MASK)
90178 
90179 #define WUU_PDC1_WUPDC9_MASK                     (0xC0000U)
90180 #define WUU_PDC1_WUPDC9_SHIFT                    (18U)
90181 /*! WUPDC9 - Wake-up Pin Configuration for WUU_Pn
90182  *  0b00..Interrupt
90183  *  0b01..DMA request
90184  *  0b10..Trigger event
90185  *  0b11..Reserved
90186  */
90187 #define WUU_PDC1_WUPDC9(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC9_SHIFT)) & WUU_PDC1_WUPDC9_MASK)
90188 
90189 #define WUU_PDC1_WUPDC10_MASK                    (0x300000U)
90190 #define WUU_PDC1_WUPDC10_SHIFT                   (20U)
90191 /*! WUPDC10 - Wake-up Pin Configuration for WUU_Pn
90192  *  0b00..Interrupt
90193  *  0b01..DMA request
90194  *  0b10..Trigger event
90195  *  0b11..Reserved
90196  */
90197 #define WUU_PDC1_WUPDC10(x)                      (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC10_SHIFT)) & WUU_PDC1_WUPDC10_MASK)
90198 
90199 #define WUU_PDC1_WUPDC11_MASK                    (0xC00000U)
90200 #define WUU_PDC1_WUPDC11_SHIFT                   (22U)
90201 /*! WUPDC11 - Wake-up Pin Configuration for WUU_Pn
90202  *  0b00..Interrupt
90203  *  0b01..DMA request
90204  *  0b10..Trigger event
90205  *  0b11..Reserved
90206  */
90207 #define WUU_PDC1_WUPDC11(x)                      (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC11_SHIFT)) & WUU_PDC1_WUPDC11_MASK)
90208 
90209 #define WUU_PDC1_WUPDC12_MASK                    (0x3000000U)
90210 #define WUU_PDC1_WUPDC12_SHIFT                   (24U)
90211 /*! WUPDC12 - Wake-up Pin Configuration for WUU_Pn
90212  *  0b00..Interrupt
90213  *  0b01..DMA request
90214  *  0b10..Trigger event
90215  *  0b11..Reserved
90216  */
90217 #define WUU_PDC1_WUPDC12(x)                      (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC12_SHIFT)) & WUU_PDC1_WUPDC12_MASK)
90218 
90219 #define WUU_PDC1_WUPDC13_MASK                    (0xC000000U)
90220 #define WUU_PDC1_WUPDC13_SHIFT                   (26U)
90221 /*! WUPDC13 - Wake-up Pin Configuration for WUU_Pn
90222  *  0b00..Interrupt
90223  *  0b01..DMA request
90224  *  0b10..Trigger event
90225  *  0b11..Reserved
90226  */
90227 #define WUU_PDC1_WUPDC13(x)                      (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC13_SHIFT)) & WUU_PDC1_WUPDC13_MASK)
90228 
90229 #define WUU_PDC1_WUPDC14_MASK                    (0x30000000U)
90230 #define WUU_PDC1_WUPDC14_SHIFT                   (28U)
90231 /*! WUPDC14 - Wake-up Pin Configuration for WUU_Pn
90232  *  0b00..Interrupt
90233  *  0b01..DMA request
90234  *  0b10..Trigger event
90235  *  0b11..Reserved
90236  */
90237 #define WUU_PDC1_WUPDC14(x)                      (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC14_SHIFT)) & WUU_PDC1_WUPDC14_MASK)
90238 
90239 #define WUU_PDC1_WUPDC15_MASK                    (0xC0000000U)
90240 #define WUU_PDC1_WUPDC15_SHIFT                   (30U)
90241 /*! WUPDC15 - Wake-up Pin Configuration for WUU_Pn
90242  *  0b00..Interrupt
90243  *  0b01..DMA request
90244  *  0b10..Trigger event
90245  *  0b11..Reserved
90246  */
90247 #define WUU_PDC1_WUPDC15(x)                      (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC15_SHIFT)) & WUU_PDC1_WUPDC15_MASK)
90248 /*! @} */
90249 
90250 /*! @name PDC2 - Pin DMA/Trigger Configuration 2 */
90251 /*! @{ */
90252 
90253 #define WUU_PDC2_WUPDC16_MASK                    (0x3U)
90254 #define WUU_PDC2_WUPDC16_SHIFT                   (0U)
90255 /*! WUPDC16 - Wake-up Pin Configuration for WUU_Pn
90256  *  0b00..Interrupt
90257  *  0b01..DMA request
90258  *  0b10..Trigger event
90259  *  0b11..Reserved
90260  */
90261 #define WUU_PDC2_WUPDC16(x)                      (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC16_SHIFT)) & WUU_PDC2_WUPDC16_MASK)
90262 
90263 #define WUU_PDC2_WUPDC17_MASK                    (0xCU)
90264 #define WUU_PDC2_WUPDC17_SHIFT                   (2U)
90265 /*! WUPDC17 - Wake-up Pin Configuration for WUU_Pn
90266  *  0b00..Interrupt
90267  *  0b01..DMA request
90268  *  0b10..Trigger event
90269  *  0b11..Reserved
90270  */
90271 #define WUU_PDC2_WUPDC17(x)                      (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC17_SHIFT)) & WUU_PDC2_WUPDC17_MASK)
90272 
90273 #define WUU_PDC2_WUPDC18_MASK                    (0x30U)
90274 #define WUU_PDC2_WUPDC18_SHIFT                   (4U)
90275 /*! WUPDC18 - Wake-up Pin Configuration for WUU_Pn
90276  *  0b00..Interrupt
90277  *  0b01..DMA request
90278  *  0b10..Trigger event
90279  *  0b11..Reserved
90280  */
90281 #define WUU_PDC2_WUPDC18(x)                      (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC18_SHIFT)) & WUU_PDC2_WUPDC18_MASK)
90282 
90283 #define WUU_PDC2_WUPDC19_MASK                    (0xC0U)
90284 #define WUU_PDC2_WUPDC19_SHIFT                   (6U)
90285 /*! WUPDC19 - Wake-up Pin Configuration for WUU_Pn
90286  *  0b00..Interrupt
90287  *  0b01..DMA request
90288  *  0b10..Trigger event
90289  *  0b11..Reserved
90290  */
90291 #define WUU_PDC2_WUPDC19(x)                      (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC19_SHIFT)) & WUU_PDC2_WUPDC19_MASK)
90292 
90293 #define WUU_PDC2_WUPDC20_MASK                    (0x300U)
90294 #define WUU_PDC2_WUPDC20_SHIFT                   (8U)
90295 /*! WUPDC20 - Wake-up Pin Configuration for WUU_Pn
90296  *  0b00..Interrupt
90297  *  0b01..DMA request
90298  *  0b10..Trigger event
90299  *  0b11..Reserved
90300  */
90301 #define WUU_PDC2_WUPDC20(x)                      (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC20_SHIFT)) & WUU_PDC2_WUPDC20_MASK)
90302 
90303 #define WUU_PDC2_WUPDC21_MASK                    (0xC00U)
90304 #define WUU_PDC2_WUPDC21_SHIFT                   (10U)
90305 /*! WUPDC21 - Wake-up Pin Configuration for WUU_Pn
90306  *  0b00..Interrupt
90307  *  0b01..DMA request
90308  *  0b10..Trigger event
90309  *  0b11..Reserved
90310  */
90311 #define WUU_PDC2_WUPDC21(x)                      (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC21_SHIFT)) & WUU_PDC2_WUPDC21_MASK)
90312 
90313 #define WUU_PDC2_WUPDC22_MASK                    (0x3000U)
90314 #define WUU_PDC2_WUPDC22_SHIFT                   (12U)
90315 /*! WUPDC22 - Wake-up Pin Configuration for WUU_Pn
90316  *  0b00..Interrupt
90317  *  0b01..DMA request
90318  *  0b10..Trigger event
90319  *  0b11..Reserved
90320  */
90321 #define WUU_PDC2_WUPDC22(x)                      (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC22_SHIFT)) & WUU_PDC2_WUPDC22_MASK)
90322 
90323 #define WUU_PDC2_WUPDC23_MASK                    (0xC000U)
90324 #define WUU_PDC2_WUPDC23_SHIFT                   (14U)
90325 /*! WUPDC23 - Wake-up Pin Configuration for WUU_Pn
90326  *  0b00..Interrupt
90327  *  0b01..DMA request
90328  *  0b10..Trigger event
90329  *  0b11..Reserved
90330  */
90331 #define WUU_PDC2_WUPDC23(x)                      (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC23_SHIFT)) & WUU_PDC2_WUPDC23_MASK)
90332 
90333 #define WUU_PDC2_WUPDC24_MASK                    (0x30000U)
90334 #define WUU_PDC2_WUPDC24_SHIFT                   (16U)
90335 /*! WUPDC24 - Wake-up Pin Configuration for WUU_Pn
90336  *  0b00..Interrupt
90337  *  0b01..DMA request
90338  *  0b10..Trigger event
90339  *  0b11..Reserved
90340  */
90341 #define WUU_PDC2_WUPDC24(x)                      (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC24_SHIFT)) & WUU_PDC2_WUPDC24_MASK)
90342 
90343 #define WUU_PDC2_WUPDC25_MASK                    (0xC0000U)
90344 #define WUU_PDC2_WUPDC25_SHIFT                   (18U)
90345 /*! WUPDC25 - Wake-up Pin Configuration for WUU_Pn
90346  *  0b00..Interrupt
90347  *  0b01..DMA request
90348  *  0b10..Trigger event
90349  *  0b11..Reserved
90350  */
90351 #define WUU_PDC2_WUPDC25(x)                      (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC25_SHIFT)) & WUU_PDC2_WUPDC25_MASK)
90352 
90353 #define WUU_PDC2_WUPDC26_MASK                    (0x300000U)
90354 #define WUU_PDC2_WUPDC26_SHIFT                   (20U)
90355 /*! WUPDC26 - Wake-up Pin Configuration for WUU_Pn
90356  *  0b00..Interrupt
90357  *  0b01..DMA request
90358  *  0b10..Trigger event
90359  *  0b11..Reserved
90360  */
90361 #define WUU_PDC2_WUPDC26(x)                      (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC26_SHIFT)) & WUU_PDC2_WUPDC26_MASK)
90362 
90363 #define WUU_PDC2_WUPDC27_MASK                    (0xC00000U)
90364 #define WUU_PDC2_WUPDC27_SHIFT                   (22U)
90365 /*! WUPDC27 - Wake-up Pin Configuration for WUU_Pn
90366  *  0b00..Interrupt
90367  *  0b01..DMA request
90368  *  0b10..Trigger event
90369  *  0b11..Reserved
90370  */
90371 #define WUU_PDC2_WUPDC27(x)                      (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC27_SHIFT)) & WUU_PDC2_WUPDC27_MASK)
90372 
90373 #define WUU_PDC2_WUPDC28_MASK                    (0x3000000U)
90374 #define WUU_PDC2_WUPDC28_SHIFT                   (24U)
90375 /*! WUPDC28 - Wake-up Pin Configuration for WUU_Pn
90376  *  0b00..Interrupt
90377  *  0b01..DMA request
90378  *  0b10..Trigger event
90379  *  0b11..Reserved
90380  */
90381 #define WUU_PDC2_WUPDC28(x)                      (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC28_SHIFT)) & WUU_PDC2_WUPDC28_MASK)
90382 
90383 #define WUU_PDC2_WUPDC29_MASK                    (0xC000000U)
90384 #define WUU_PDC2_WUPDC29_SHIFT                   (26U)
90385 /*! WUPDC29 - Wake-up Pin Configuration for WUU_Pn
90386  *  0b00..Interrupt
90387  *  0b01..DMA request
90388  *  0b10..Trigger event
90389  *  0b11..Reserved
90390  */
90391 #define WUU_PDC2_WUPDC29(x)                      (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC29_SHIFT)) & WUU_PDC2_WUPDC29_MASK)
90392 
90393 #define WUU_PDC2_WUPDC30_MASK                    (0x30000000U)
90394 #define WUU_PDC2_WUPDC30_SHIFT                   (28U)
90395 /*! WUPDC30 - Wake-up Pin Configuration for WUU_Pn
90396  *  0b00..Interrupt
90397  *  0b01..DMA request
90398  *  0b10..Trigger event
90399  *  0b11..Reserved
90400  */
90401 #define WUU_PDC2_WUPDC30(x)                      (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC30_SHIFT)) & WUU_PDC2_WUPDC30_MASK)
90402 
90403 #define WUU_PDC2_WUPDC31_MASK                    (0xC0000000U)
90404 #define WUU_PDC2_WUPDC31_SHIFT                   (30U)
90405 /*! WUPDC31 - Wake-up Pin Configuration for WUU_Pn
90406  *  0b00..Interrupt
90407  *  0b01..DMA request
90408  *  0b10..Trigger event
90409  *  0b11..Reserved
90410  */
90411 #define WUU_PDC2_WUPDC31(x)                      (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC31_SHIFT)) & WUU_PDC2_WUPDC31_MASK)
90412 /*! @} */
90413 
90414 /*! @name FDC - Pin Filter DMA/Trigger Configuration */
90415 /*! @{ */
90416 
90417 #define WUU_FDC_FILTC1_MASK                      (0x3U)
90418 #define WUU_FDC_FILTC1_SHIFT                     (0U)
90419 /*! FILTC1 - Filter Configuration for FILTn
90420  *  0b00..Interrupt
90421  *  0b01..DMA request
90422  *  0b10..Trigger event
90423  *  0b11..Reserved
90424  */
90425 #define WUU_FDC_FILTC1(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_FDC_FILTC1_SHIFT)) & WUU_FDC_FILTC1_MASK)
90426 
90427 #define WUU_FDC_FILTC2_MASK                      (0xCU)
90428 #define WUU_FDC_FILTC2_SHIFT                     (2U)
90429 /*! FILTC2 - Filter Configuration for FILTn
90430  *  0b00..Interrupt
90431  *  0b01..DMA request
90432  *  0b10..Trigger event
90433  *  0b11..Reserved
90434  */
90435 #define WUU_FDC_FILTC2(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_FDC_FILTC2_SHIFT)) & WUU_FDC_FILTC2_MASK)
90436 /*! @} */
90437 
90438 /*! @name PMC - Pin Mode Configuration */
90439 /*! @{ */
90440 
90441 #define WUU_PMC_WUPMC0_MASK                      (0x1U)
90442 #define WUU_PMC_WUPMC0_SHIFT                     (0U)
90443 /*! WUPMC0 - Wake-up Pin Mode Configuration for WUU_Pn
90444  *  0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or
90445  *       Pin DMA/Trigger Configuration (PDCn).
90446  *  0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
90447  */
90448 #define WUU_PMC_WUPMC0(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC0_SHIFT)) & WUU_PMC_WUPMC0_MASK)
90449 
90450 #define WUU_PMC_WUPMC1_MASK                      (0x2U)
90451 #define WUU_PMC_WUPMC1_SHIFT                     (1U)
90452 /*! WUPMC1 - Wake-up Pin Mode Configuration for WUU_Pn
90453  *  0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or
90454  *       Pin DMA/Trigger Configuration (PDCn).
90455  *  0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
90456  */
90457 #define WUU_PMC_WUPMC1(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC1_SHIFT)) & WUU_PMC_WUPMC1_MASK)
90458 
90459 #define WUU_PMC_WUPMC2_MASK                      (0x4U)
90460 #define WUU_PMC_WUPMC2_SHIFT                     (2U)
90461 /*! WUPMC2 - Wake-up Pin Mode Configuration for WUU_Pn
90462  *  0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or
90463  *       Pin DMA/Trigger Configuration (PDCn).
90464  *  0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
90465  */
90466 #define WUU_PMC_WUPMC2(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC2_SHIFT)) & WUU_PMC_WUPMC2_MASK)
90467 
90468 #define WUU_PMC_WUPMC3_MASK                      (0x8U)
90469 #define WUU_PMC_WUPMC3_SHIFT                     (3U)
90470 /*! WUPMC3 - Wake-up Pin Mode Configuration for WUU_Pn
90471  *  0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or
90472  *       Pin DMA/Trigger Configuration (PDCn).
90473  *  0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
90474  */
90475 #define WUU_PMC_WUPMC3(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC3_SHIFT)) & WUU_PMC_WUPMC3_MASK)
90476 
90477 #define WUU_PMC_WUPMC4_MASK                      (0x10U)
90478 #define WUU_PMC_WUPMC4_SHIFT                     (4U)
90479 /*! WUPMC4 - Wake-up Pin Mode Configuration for WUU_Pn
90480  *  0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or
90481  *       Pin DMA/Trigger Configuration (PDCn).
90482  *  0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
90483  */
90484 #define WUU_PMC_WUPMC4(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC4_SHIFT)) & WUU_PMC_WUPMC4_MASK)
90485 
90486 #define WUU_PMC_WUPMC5_MASK                      (0x20U)
90487 #define WUU_PMC_WUPMC5_SHIFT                     (5U)
90488 /*! WUPMC5 - Wake-up Pin Mode Configuration for WUU_Pn
90489  *  0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or
90490  *       Pin DMA/Trigger Configuration (PDCn).
90491  *  0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
90492  */
90493 #define WUU_PMC_WUPMC5(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC5_SHIFT)) & WUU_PMC_WUPMC5_MASK)
90494 
90495 #define WUU_PMC_WUPMC6_MASK                      (0x40U)
90496 #define WUU_PMC_WUPMC6_SHIFT                     (6U)
90497 /*! WUPMC6 - Wake-up Pin Mode Configuration for WUU_Pn
90498  *  0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or
90499  *       Pin DMA/Trigger Configuration (PDCn).
90500  *  0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
90501  */
90502 #define WUU_PMC_WUPMC6(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC6_SHIFT)) & WUU_PMC_WUPMC6_MASK)
90503 
90504 #define WUU_PMC_WUPMC7_MASK                      (0x80U)
90505 #define WUU_PMC_WUPMC7_SHIFT                     (7U)
90506 /*! WUPMC7 - Wake-up Pin Mode Configuration for WUU_Pn
90507  *  0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or
90508  *       Pin DMA/Trigger Configuration (PDCn).
90509  *  0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
90510  */
90511 #define WUU_PMC_WUPMC7(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC7_SHIFT)) & WUU_PMC_WUPMC7_MASK)
90512 
90513 #define WUU_PMC_WUPMC8_MASK                      (0x100U)
90514 #define WUU_PMC_WUPMC8_SHIFT                     (8U)
90515 /*! WUPMC8 - Wake-up Pin Mode Configuration for WUU_Pn
90516  *  0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or
90517  *       Pin DMA/Trigger Configuration (PDCn).
90518  *  0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
90519  */
90520 #define WUU_PMC_WUPMC8(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC8_SHIFT)) & WUU_PMC_WUPMC8_MASK)
90521 
90522 #define WUU_PMC_WUPMC9_MASK                      (0x200U)
90523 #define WUU_PMC_WUPMC9_SHIFT                     (9U)
90524 /*! WUPMC9 - Wake-up Pin Mode Configuration for WUU_Pn
90525  *  0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or
90526  *       Pin DMA/Trigger Configuration (PDCn).
90527  *  0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
90528  */
90529 #define WUU_PMC_WUPMC9(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC9_SHIFT)) & WUU_PMC_WUPMC9_MASK)
90530 
90531 #define WUU_PMC_WUPMC10_MASK                     (0x400U)
90532 #define WUU_PMC_WUPMC10_SHIFT                    (10U)
90533 /*! WUPMC10 - Wake-up Pin Mode Configuration for WUU_Pn
90534  *  0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or
90535  *       Pin DMA/Trigger Configuration (PDCn).
90536  *  0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
90537  */
90538 #define WUU_PMC_WUPMC10(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC10_SHIFT)) & WUU_PMC_WUPMC10_MASK)
90539 
90540 #define WUU_PMC_WUPMC11_MASK                     (0x800U)
90541 #define WUU_PMC_WUPMC11_SHIFT                    (11U)
90542 /*! WUPMC11 - Wake-up Pin Mode Configuration for WUU_Pn
90543  *  0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or
90544  *       Pin DMA/Trigger Configuration (PDCn).
90545  *  0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
90546  */
90547 #define WUU_PMC_WUPMC11(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC11_SHIFT)) & WUU_PMC_WUPMC11_MASK)
90548 
90549 #define WUU_PMC_WUPMC12_MASK                     (0x1000U)
90550 #define WUU_PMC_WUPMC12_SHIFT                    (12U)
90551 /*! WUPMC12 - Wake-up Pin Mode Configuration for WUU_Pn
90552  *  0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or
90553  *       Pin DMA/Trigger Configuration (PDCn).
90554  *  0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
90555  */
90556 #define WUU_PMC_WUPMC12(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC12_SHIFT)) & WUU_PMC_WUPMC12_MASK)
90557 
90558 #define WUU_PMC_WUPMC13_MASK                     (0x2000U)
90559 #define WUU_PMC_WUPMC13_SHIFT                    (13U)
90560 /*! WUPMC13 - Wake-up Pin Mode Configuration for WUU_Pn
90561  *  0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or
90562  *       Pin DMA/Trigger Configuration (PDCn).
90563  *  0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
90564  */
90565 #define WUU_PMC_WUPMC13(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC13_SHIFT)) & WUU_PMC_WUPMC13_MASK)
90566 
90567 #define WUU_PMC_WUPMC14_MASK                     (0x4000U)
90568 #define WUU_PMC_WUPMC14_SHIFT                    (14U)
90569 /*! WUPMC14 - Wake-up Pin Mode Configuration for WUU_Pn
90570  *  0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or
90571  *       Pin DMA/Trigger Configuration (PDCn).
90572  *  0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
90573  */
90574 #define WUU_PMC_WUPMC14(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC14_SHIFT)) & WUU_PMC_WUPMC14_MASK)
90575 
90576 #define WUU_PMC_WUPMC15_MASK                     (0x8000U)
90577 #define WUU_PMC_WUPMC15_SHIFT                    (15U)
90578 /*! WUPMC15 - Wake-up Pin Mode Configuration for WUU_Pn
90579  *  0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or
90580  *       Pin DMA/Trigger Configuration (PDCn).
90581  *  0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
90582  */
90583 #define WUU_PMC_WUPMC15(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC15_SHIFT)) & WUU_PMC_WUPMC15_MASK)
90584 
90585 #define WUU_PMC_WUPMC16_MASK                     (0x10000U)
90586 #define WUU_PMC_WUPMC16_SHIFT                    (16U)
90587 /*! WUPMC16 - Wake-up Pin Mode Configuration for WUU_Pn
90588  *  0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or
90589  *       Pin DMA/Trigger Configuration (PDCn).
90590  *  0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
90591  */
90592 #define WUU_PMC_WUPMC16(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC16_SHIFT)) & WUU_PMC_WUPMC16_MASK)
90593 
90594 #define WUU_PMC_WUPMC17_MASK                     (0x20000U)
90595 #define WUU_PMC_WUPMC17_SHIFT                    (17U)
90596 /*! WUPMC17 - Wake-up Pin Mode Configuration for WUU_Pn
90597  *  0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or
90598  *       Pin DMA/Trigger Configuration (PDCn).
90599  *  0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
90600  */
90601 #define WUU_PMC_WUPMC17(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC17_SHIFT)) & WUU_PMC_WUPMC17_MASK)
90602 
90603 #define WUU_PMC_WUPMC18_MASK                     (0x40000U)
90604 #define WUU_PMC_WUPMC18_SHIFT                    (18U)
90605 /*! WUPMC18 - Wake-up Pin Mode Configuration for WUU_Pn
90606  *  0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or
90607  *       Pin DMA/Trigger Configuration (PDCn).
90608  *  0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
90609  */
90610 #define WUU_PMC_WUPMC18(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC18_SHIFT)) & WUU_PMC_WUPMC18_MASK)
90611 
90612 #define WUU_PMC_WUPMC19_MASK                     (0x80000U)
90613 #define WUU_PMC_WUPMC19_SHIFT                    (19U)
90614 /*! WUPMC19 - Wake-up Pin Mode Configuration for WUU_Pn
90615  *  0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or
90616  *       Pin DMA/Trigger Configuration (PDCn).
90617  *  0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
90618  */
90619 #define WUU_PMC_WUPMC19(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC19_SHIFT)) & WUU_PMC_WUPMC19_MASK)
90620 
90621 #define WUU_PMC_WUPMC20_MASK                     (0x100000U)
90622 #define WUU_PMC_WUPMC20_SHIFT                    (20U)
90623 /*! WUPMC20 - Wake-up Pin Mode Configuration for WUU_Pn
90624  *  0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or
90625  *       Pin DMA/Trigger Configuration (PDCn).
90626  *  0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
90627  */
90628 #define WUU_PMC_WUPMC20(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC20_SHIFT)) & WUU_PMC_WUPMC20_MASK)
90629 
90630 #define WUU_PMC_WUPMC21_MASK                     (0x200000U)
90631 #define WUU_PMC_WUPMC21_SHIFT                    (21U)
90632 /*! WUPMC21 - Wake-up Pin Mode Configuration for WUU_Pn
90633  *  0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or
90634  *       Pin DMA/Trigger Configuration (PDCn).
90635  *  0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
90636  */
90637 #define WUU_PMC_WUPMC21(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC21_SHIFT)) & WUU_PMC_WUPMC21_MASK)
90638 
90639 #define WUU_PMC_WUPMC22_MASK                     (0x400000U)
90640 #define WUU_PMC_WUPMC22_SHIFT                    (22U)
90641 /*! WUPMC22 - Wake-up Pin Mode Configuration for WUU_Pn
90642  *  0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or
90643  *       Pin DMA/Trigger Configuration (PDCn).
90644  *  0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
90645  */
90646 #define WUU_PMC_WUPMC22(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC22_SHIFT)) & WUU_PMC_WUPMC22_MASK)
90647 
90648 #define WUU_PMC_WUPMC23_MASK                     (0x800000U)
90649 #define WUU_PMC_WUPMC23_SHIFT                    (23U)
90650 /*! WUPMC23 - Wake-up Pin Mode Configuration for WUU_Pn
90651  *  0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or
90652  *       Pin DMA/Trigger Configuration (PDCn).
90653  *  0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
90654  */
90655 #define WUU_PMC_WUPMC23(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC23_SHIFT)) & WUU_PMC_WUPMC23_MASK)
90656 
90657 #define WUU_PMC_WUPMC24_MASK                     (0x1000000U)
90658 #define WUU_PMC_WUPMC24_SHIFT                    (24U)
90659 /*! WUPMC24 - Wake-up Pin Mode Configuration for WUU_Pn
90660  *  0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or
90661  *       Pin DMA/Trigger Configuration (PDCn).
90662  *  0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
90663  */
90664 #define WUU_PMC_WUPMC24(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC24_SHIFT)) & WUU_PMC_WUPMC24_MASK)
90665 
90666 #define WUU_PMC_WUPMC25_MASK                     (0x2000000U)
90667 #define WUU_PMC_WUPMC25_SHIFT                    (25U)
90668 /*! WUPMC25 - Wake-up Pin Mode Configuration for WUU_Pn
90669  *  0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or
90670  *       Pin DMA/Trigger Configuration (PDCn).
90671  *  0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
90672  */
90673 #define WUU_PMC_WUPMC25(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC25_SHIFT)) & WUU_PMC_WUPMC25_MASK)
90674 
90675 #define WUU_PMC_WUPMC26_MASK                     (0x4000000U)
90676 #define WUU_PMC_WUPMC26_SHIFT                    (26U)
90677 /*! WUPMC26 - Wake-up Pin Mode Configuration for WUU_Pn
90678  *  0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or
90679  *       Pin DMA/Trigger Configuration (PDCn).
90680  *  0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
90681  */
90682 #define WUU_PMC_WUPMC26(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC26_SHIFT)) & WUU_PMC_WUPMC26_MASK)
90683 
90684 #define WUU_PMC_WUPMC27_MASK                     (0x8000000U)
90685 #define WUU_PMC_WUPMC27_SHIFT                    (27U)
90686 /*! WUPMC27 - Wake-up Pin Mode Configuration for WUU_Pn
90687  *  0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or
90688  *       Pin DMA/Trigger Configuration (PDCn).
90689  *  0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
90690  */
90691 #define WUU_PMC_WUPMC27(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC27_SHIFT)) & WUU_PMC_WUPMC27_MASK)
90692 
90693 #define WUU_PMC_WUPMC28_MASK                     (0x10000000U)
90694 #define WUU_PMC_WUPMC28_SHIFT                    (28U)
90695 /*! WUPMC28 - Wake-up Pin Mode Configuration for WUU_Pn
90696  *  0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or
90697  *       Pin DMA/Trigger Configuration (PDCn).
90698  *  0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
90699  */
90700 #define WUU_PMC_WUPMC28(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC28_SHIFT)) & WUU_PMC_WUPMC28_MASK)
90701 
90702 #define WUU_PMC_WUPMC29_MASK                     (0x20000000U)
90703 #define WUU_PMC_WUPMC29_SHIFT                    (29U)
90704 /*! WUPMC29 - Wake-up Pin Mode Configuration for WUU_Pn
90705  *  0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or
90706  *       Pin DMA/Trigger Configuration (PDCn).
90707  *  0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
90708  */
90709 #define WUU_PMC_WUPMC29(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC29_SHIFT)) & WUU_PMC_WUPMC29_MASK)
90710 
90711 #define WUU_PMC_WUPMC30_MASK                     (0x40000000U)
90712 #define WUU_PMC_WUPMC30_SHIFT                    (30U)
90713 /*! WUPMC30 - Wake-up Pin Mode Configuration for WUU_Pn
90714  *  0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or
90715  *       Pin DMA/Trigger Configuration (PDCn).
90716  *  0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
90717  */
90718 #define WUU_PMC_WUPMC30(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC30_SHIFT)) & WUU_PMC_WUPMC30_MASK)
90719 
90720 #define WUU_PMC_WUPMC31_MASK                     (0x80000000U)
90721 #define WUU_PMC_WUPMC31_SHIFT                    (31U)
90722 /*! WUPMC31 - Wake-up Pin Mode Configuration for WUU_Pn
90723  *  0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or
90724  *       Pin DMA/Trigger Configuration (PDCn).
90725  *  0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn).
90726  */
90727 #define WUU_PMC_WUPMC31(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC31_SHIFT)) & WUU_PMC_WUPMC31_MASK)
90728 /*! @} */
90729 
90730 /*! @name FMC - Pin Filter Mode Configuration */
90731 /*! @{ */
90732 
90733 #define WUU_FMC_FILTM1_MASK                      (0x1U)
90734 #define WUU_FMC_FILTM1_SHIFT                     (0U)
90735 /*! FILTM1 - Filter Mode for FILTn
90736  *  0b0..Active only during Power Down/Deep Power Down mode
90737  *  0b1..Active during all power modes
90738  */
90739 #define WUU_FMC_FILTM1(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_FMC_FILTM1_SHIFT)) & WUU_FMC_FILTM1_MASK)
90740 
90741 #define WUU_FMC_FILTM2_MASK                      (0x2U)
90742 #define WUU_FMC_FILTM2_SHIFT                     (1U)
90743 /*! FILTM2 - Filter Mode for FILTn
90744  *  0b0..Active only during Power Down/Deep Power Down mode
90745  *  0b1..Active during all power modes
90746  */
90747 #define WUU_FMC_FILTM2(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_FMC_FILTM2_SHIFT)) & WUU_FMC_FILTM2_MASK)
90748 /*! @} */
90749 
90750 
90751 /*!
90752  * @}
90753  */ /* end of group WUU_Register_Masks */
90754 
90755 
90756 /* WUU - Peripheral instance base addresses */
90757 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
90758   /** Peripheral WUU0 base address */
90759   #define WUU0_BASE                                (0x50046000u)
90760   /** Peripheral WUU0 base address */
90761   #define WUU0_BASE_NS                             (0x40046000u)
90762   /** Peripheral WUU0 base pointer */
90763   #define WUU0                                     ((WUU_Type *)WUU0_BASE)
90764   /** Peripheral WUU0 base pointer */
90765   #define WUU0_NS                                  ((WUU_Type *)WUU0_BASE_NS)
90766   /** Array initializer of WUU peripheral base addresses */
90767   #define WUU_BASE_ADDRS                           { WUU0_BASE }
90768   /** Array initializer of WUU peripheral base pointers */
90769   #define WUU_BASE_PTRS                            { WUU0 }
90770   /** Array initializer of WUU peripheral base addresses */
90771   #define WUU_BASE_ADDRS_NS                        { WUU0_BASE_NS }
90772   /** Array initializer of WUU peripheral base pointers */
90773   #define WUU_BASE_PTRS_NS                         { WUU0_NS }
90774 #else
90775   /** Peripheral WUU0 base address */
90776   #define WUU0_BASE                                (0x40046000u)
90777   /** Peripheral WUU0 base pointer */
90778   #define WUU0                                     ((WUU_Type *)WUU0_BASE)
90779   /** Array initializer of WUU peripheral base addresses */
90780   #define WUU_BASE_ADDRS                           { WUU0_BASE }
90781   /** Array initializer of WUU peripheral base pointers */
90782   #define WUU_BASE_PTRS                            { WUU0 }
90783 #endif
90784 
90785 /*!
90786  * @}
90787  */ /* end of group WUU_Peripheral_Access_Layer */
90788 
90789 
90790 /* ----------------------------------------------------------------------------
90791    -- WWDT Peripheral Access Layer
90792    ---------------------------------------------------------------------------- */
90793 
90794 /*!
90795  * @addtogroup WWDT_Peripheral_Access_Layer WWDT Peripheral Access Layer
90796  * @{
90797  */
90798 
90799 /** WWDT - Register Layout Typedef */
90800 typedef struct {
90801   __IO uint32_t MOD;                               /**< Mode, offset: 0x0 */
90802   __IO uint32_t TC;                                /**< Timer Constant, offset: 0x4 */
90803   __O  uint32_t FEED;                              /**< Feed Sequence, offset: 0x8 */
90804   __I  uint32_t TV;                                /**< Timer Value, offset: 0xC */
90805        uint8_t RESERVED_0[4];
90806   __IO uint32_t WARNINT;                           /**< Warning Interrupt Compare Value, offset: 0x14 */
90807   __IO uint32_t WINDOW;                            /**< Window Compare Value, offset: 0x18 */
90808 } WWDT_Type;
90809 
90810 /* ----------------------------------------------------------------------------
90811    -- WWDT Register Masks
90812    ---------------------------------------------------------------------------- */
90813 
90814 /*!
90815  * @addtogroup WWDT_Register_Masks WWDT Register Masks
90816  * @{
90817  */
90818 
90819 /*! @name MOD - Mode */
90820 /*! @{ */
90821 
90822 #define WWDT_MOD_WDEN_MASK                       (0x1U)
90823 #define WWDT_MOD_WDEN_SHIFT                      (0U)
90824 /*! WDEN - Watchdog Enable
90825  *  0b0..Timer stopped
90826  *  0b1..Timer running
90827  */
90828 #define WWDT_MOD_WDEN(x)                         (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDEN_SHIFT)) & WWDT_MOD_WDEN_MASK)
90829 
90830 #define WWDT_MOD_WDRESET_MASK                    (0x2U)
90831 #define WWDT_MOD_WDRESET_SHIFT                   (1U)
90832 /*! WDRESET - Watchdog Reset Enable
90833  *  0b0..Interrupt
90834  *  0b1..Reset
90835  */
90836 #define WWDT_MOD_WDRESET(x)                      (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDRESET_SHIFT)) & WWDT_MOD_WDRESET_MASK)
90837 
90838 #define WWDT_MOD_WDTOF_MASK                      (0x4U)
90839 #define WWDT_MOD_WDTOF_SHIFT                     (2U)
90840 /*! WDTOF - Watchdog Timeout Flag
90841  *  0b0..Watchdog event has not occurred.
90842  *  0b1..Watchdog event has occurred (causes a chip reset if WDRESET = 1).
90843  */
90844 #define WWDT_MOD_WDTOF(x)                        (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDTOF_SHIFT)) & WWDT_MOD_WDTOF_MASK)
90845 
90846 #define WWDT_MOD_WDINT_MASK                      (0x8U)
90847 #define WWDT_MOD_WDINT_SHIFT                     (3U)
90848 /*! WDINT - Warning Interrupt Flag
90849  *  0b0..No flag
90850  *  0b1..Flag
90851  */
90852 #define WWDT_MOD_WDINT(x)                        (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDINT_SHIFT)) & WWDT_MOD_WDINT_MASK)
90853 
90854 #define WWDT_MOD_WDPROTECT_MASK                  (0x10U)
90855 #define WWDT_MOD_WDPROTECT_SHIFT                 (4U)
90856 /*! WDPROTECT - Watchdog Update Mode
90857  *  0b0..Flexible
90858  *  0b1..Threshold
90859  */
90860 #define WWDT_MOD_WDPROTECT(x)                    (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDPROTECT_SHIFT)) & WWDT_MOD_WDPROTECT_MASK)
90861 
90862 #define WWDT_MOD_LOCK_MASK                       (0x20U)
90863 #define WWDT_MOD_LOCK_SHIFT                      (5U)
90864 /*! LOCK - Lock
90865  *  0b0..No Lock
90866  *  0b1..Lock
90867  */
90868 #define WWDT_MOD_LOCK(x)                         (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_LOCK_SHIFT)) & WWDT_MOD_LOCK_MASK)
90869 
90870 #define WWDT_MOD_DEBUG_EN_MASK                   (0x40U)
90871 #define WWDT_MOD_DEBUG_EN_SHIFT                  (6U)
90872 /*! DEBUG_EN - Debug Enable
90873  *  0b0..Disabled
90874  *  0b1..Enabled
90875  */
90876 #define WWDT_MOD_DEBUG_EN(x)                     (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_DEBUG_EN_SHIFT)) & WWDT_MOD_DEBUG_EN_MASK)
90877 /*! @} */
90878 
90879 /*! @name TC - Timer Constant */
90880 /*! @{ */
90881 
90882 #define WWDT_TC_COUNT_MASK                       (0xFFFFFFU)
90883 #define WWDT_TC_COUNT_SHIFT                      (0U)
90884 /*! COUNT - Watchdog Timeout Value */
90885 #define WWDT_TC_COUNT(x)                         (((uint32_t)(((uint32_t)(x)) << WWDT_TC_COUNT_SHIFT)) & WWDT_TC_COUNT_MASK)
90886 /*! @} */
90887 
90888 /*! @name FEED - Feed Sequence */
90889 /*! @{ */
90890 
90891 #define WWDT_FEED_FEED_MASK                      (0xFFU)
90892 #define WWDT_FEED_FEED_SHIFT                     (0U)
90893 /*! FEED - Feed Value */
90894 #define WWDT_FEED_FEED(x)                        (((uint32_t)(((uint32_t)(x)) << WWDT_FEED_FEED_SHIFT)) & WWDT_FEED_FEED_MASK)
90895 /*! @} */
90896 
90897 /*! @name TV - Timer Value */
90898 /*! @{ */
90899 
90900 #define WWDT_TV_COUNT_MASK                       (0xFFFFFFU)
90901 #define WWDT_TV_COUNT_SHIFT                      (0U)
90902 /*! COUNT - Counter Timer Value */
90903 #define WWDT_TV_COUNT(x)                         (((uint32_t)(((uint32_t)(x)) << WWDT_TV_COUNT_SHIFT)) & WWDT_TV_COUNT_MASK)
90904 /*! @} */
90905 
90906 /*! @name WARNINT - Warning Interrupt Compare Value */
90907 /*! @{ */
90908 
90909 #define WWDT_WARNINT_WARNINT_MASK                (0x3FFU)
90910 #define WWDT_WARNINT_WARNINT_SHIFT               (0U)
90911 /*! WARNINT - Watchdog Warning Interrupt Compare Value */
90912 #define WWDT_WARNINT_WARNINT(x)                  (((uint32_t)(((uint32_t)(x)) << WWDT_WARNINT_WARNINT_SHIFT)) & WWDT_WARNINT_WARNINT_MASK)
90913 /*! @} */
90914 
90915 /*! @name WINDOW - Window Compare Value */
90916 /*! @{ */
90917 
90918 #define WWDT_WINDOW_WINDOW_MASK                  (0xFFFFFFU)
90919 #define WWDT_WINDOW_WINDOW_SHIFT                 (0U)
90920 /*! WINDOW - Watchdog Window Value */
90921 #define WWDT_WINDOW_WINDOW(x)                    (((uint32_t)(((uint32_t)(x)) << WWDT_WINDOW_WINDOW_SHIFT)) & WWDT_WINDOW_WINDOW_MASK)
90922 /*! @} */
90923 
90924 
90925 /*!
90926  * @}
90927  */ /* end of group WWDT_Register_Masks */
90928 
90929 
90930 /* WWDT - Peripheral instance base addresses */
90931 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
90932   /** Peripheral WWDT0 base address */
90933   #define WWDT0_BASE                               (0x50016000u)
90934   /** Peripheral WWDT0 base address */
90935   #define WWDT0_BASE_NS                            (0x40016000u)
90936   /** Peripheral WWDT0 base pointer */
90937   #define WWDT0                                    ((WWDT_Type *)WWDT0_BASE)
90938   /** Peripheral WWDT0 base pointer */
90939   #define WWDT0_NS                                 ((WWDT_Type *)WWDT0_BASE_NS)
90940   /** Peripheral WWDT1 base address */
90941   #define WWDT1_BASE                               (0x50017000u)
90942   /** Peripheral WWDT1 base address */
90943   #define WWDT1_BASE_NS                            (0x40017000u)
90944   /** Peripheral WWDT1 base pointer */
90945   #define WWDT1                                    ((WWDT_Type *)WWDT1_BASE)
90946   /** Peripheral WWDT1 base pointer */
90947   #define WWDT1_NS                                 ((WWDT_Type *)WWDT1_BASE_NS)
90948   /** Array initializer of WWDT peripheral base addresses */
90949   #define WWDT_BASE_ADDRS                          { WWDT0_BASE, WWDT1_BASE }
90950   /** Array initializer of WWDT peripheral base pointers */
90951   #define WWDT_BASE_PTRS                           { WWDT0, WWDT1 }
90952   /** Array initializer of WWDT peripheral base addresses */
90953   #define WWDT_BASE_ADDRS_NS                       { WWDT0_BASE_NS, WWDT1_BASE_NS }
90954   /** Array initializer of WWDT peripheral base pointers */
90955   #define WWDT_BASE_PTRS_NS                        { WWDT0_NS, WWDT1_NS }
90956 #else
90957   /** Peripheral WWDT0 base address */
90958   #define WWDT0_BASE                               (0x40016000u)
90959   /** Peripheral WWDT0 base pointer */
90960   #define WWDT0                                    ((WWDT_Type *)WWDT0_BASE)
90961   /** Peripheral WWDT1 base address */
90962   #define WWDT1_BASE                               (0x40017000u)
90963   /** Peripheral WWDT1 base pointer */
90964   #define WWDT1                                    ((WWDT_Type *)WWDT1_BASE)
90965   /** Array initializer of WWDT peripheral base addresses */
90966   #define WWDT_BASE_ADDRS                          { WWDT0_BASE, WWDT1_BASE }
90967   /** Array initializer of WWDT peripheral base pointers */
90968   #define WWDT_BASE_PTRS                           { WWDT0, WWDT1 }
90969 #endif
90970 /** Interrupt vectors for the WWDT peripheral type */
90971 #define WWDT_IRQS                                { WWDT0_IRQn, WWDT1_IRQn }
90972 
90973 /*!
90974  * @}
90975  */ /* end of group WWDT_Peripheral_Access_Layer */
90976 
90977 
90978 /*
90979 ** End of section using anonymous unions
90980 */
90981 
90982 #if defined(__ARMCC_VERSION)
90983   #if (__ARMCC_VERSION >= 6010050)
90984     #pragma clang diagnostic pop
90985   #else
90986     #pragma pop
90987   #endif
90988 #elif defined(__GNUC__)
90989   /* leave anonymous unions enabled */
90990 #elif defined(__IAR_SYSTEMS_ICC__)
90991   #pragma language=default
90992 #else
90993   #error Not supported compiler type
90994 #endif
90995 
90996 /*!
90997  * @}
90998  */ /* end of group Peripheral_access_layer */
90999 
91000 
91001 /* ----------------------------------------------------------------------------
91002    -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
91003    ---------------------------------------------------------------------------- */
91004 
91005 /*!
91006  * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
91007  * @{
91008  */
91009 
91010 #if defined(__ARMCC_VERSION)
91011   #if (__ARMCC_VERSION >= 6010050)
91012     #pragma clang system_header
91013   #endif
91014 #elif defined(__IAR_SYSTEMS_ICC__)
91015   #pragma system_include
91016 #endif
91017 
91018 /**
91019  * @brief Mask and left-shift a bit field value for use in a register bit range.
91020  * @param field Name of the register bit field.
91021  * @param value Value of the bit field.
91022  * @return Masked and shifted value.
91023  */
91024 #define NXP_VAL2FLD(field, value)    (((value) << (field ## _SHIFT)) & (field ## _MASK))
91025 /**
91026  * @brief Mask and right-shift a register value to extract a bit field value.
91027  * @param field Name of the register bit field.
91028  * @param value Value of the register.
91029  * @return Masked and shifted bit field value.
91030  */
91031 #define NXP_FLD2VAL(field, value)    (((value) & (field ## _MASK)) >> (field ## _SHIFT))
91032 
91033 /*!
91034  * @}
91035  */ /* end of group Bit_Field_Generic_Macros */
91036 
91037 
91038 /* ----------------------------------------------------------------------------
91039    -- SDK Compatibility
91040    ---------------------------------------------------------------------------- */
91041 
91042 /*!
91043  * @addtogroup SDK_Compatibility_Symbols SDK Compatibility
91044  * @{
91045  */
91046 
91047 /*!
91048  * @brief Get the chip value.
91049  *
91050  * @return chip version, 0x0: A0 version chip, 0x1: A1 version chip, 0xFF: invalid version.
91051  */
Chip_GetVersion(void)91052 static inline uint32_t Chip_GetVersion(void)
91053 {
91054     uint32_t deviceRevision;
91055 
91056     deviceRevision = SYSCON->DIEID & SYSCON_DIEID_MINOR_REVISION_MASK;
91057 
91058     if(0UL == deviceRevision) /* A0 device revision is 0 */
91059     {
91060         return 0x0;
91061     }
91062     else if(1UL == deviceRevision) /* A1 device revision is 1 */
91063     {
91064         return 0x1;
91065     }
91066     else
91067     {
91068         return 0xFF;
91069     }
91070 }
91071 
91072 
91073 /*!
91074  * @}
91075  */ /* end of group SDK_Compatibility_Symbols */
91076 
91077 
91078 #endif  /* MCXN547_CM33_CORE0_H_ */
91079 
91080