1 /* 2 ** ################################################################### 3 ** Processors: MKE04Z8VFK4 4 ** MKE04Z8VTG4 5 ** MKE04Z8VWJ4 6 ** 7 ** Compilers: Keil ARM C/C++ Compiler 8 ** Freescale C/C++ for Embedded ARM 9 ** GNU C Compiler 10 ** IAR ANSI C/C++ Compiler for ARM 11 ** MCUXpresso Compiler 12 ** 13 ** Reference manual: MKE04P24M48SF0RM Rev 4 14 ** Version: rev. 1.0, 2017-05-19 15 ** Build: b180802 16 ** 17 ** Abstract: 18 ** CMSIS Peripheral Access Layer for MKE04Z4 19 ** 20 ** Copyright 1997-2016 Freescale Semiconductor, Inc. 21 ** Copyright 2016-2018 NXP 22 ** 23 ** SPDX-License-Identifier: BSD-3-Clause 24 ** 25 ** http: www.nxp.com 26 ** mail: support@nxp.com 27 ** 28 ** Revisions: 29 ** - rev. 1.0 (2017-05-19) 30 ** Initial version. 31 ** 32 ** ################################################################### 33 */ 34 35 /*! 36 * @file MKE04Z4.h 37 * @version 1.0 38 * @date 2017-05-19 39 * @brief CMSIS Peripheral Access Layer for MKE04Z4 40 * 41 * CMSIS Peripheral Access Layer for MKE04Z4 42 */ 43 44 #ifndef _MKE04Z4_H_ 45 #define _MKE04Z4_H_ /**< Symbol preventing repeated inclusion */ 46 47 /** Memory map major version (memory maps with equal major version number are 48 * compatible) */ 49 #define MCU_MEM_MAP_VERSION 0x0100U 50 /** Memory map minor version */ 51 #define MCU_MEM_MAP_VERSION_MINOR 0x0000U 52 53 54 /* ---------------------------------------------------------------------------- 55 -- Interrupt vector numbers 56 ---------------------------------------------------------------------------- */ 57 58 /*! 59 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers 60 * @{ 61 */ 62 63 /** Interrupt Number Definitions */ 64 #define NUMBER_OF_INT_VECTORS 48 /**< Number of interrupts in the Vector table */ 65 66 typedef enum IRQn { 67 /* Auxiliary constants */ 68 NotAvail_IRQn = -128, /**< Not available device specific interrupt */ 69 70 /* Core interrupts */ 71 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ 72 HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */ 73 SVCall_IRQn = -5, /**< Cortex-M0 SV Call Interrupt */ 74 PendSV_IRQn = -2, /**< Cortex-M0 Pend SV Interrupt */ 75 SysTick_IRQn = -1, /**< Cortex-M0 System Tick Interrupt */ 76 77 /* Device specific interrupts */ 78 Reserved16_IRQn = 0, /**< Reserved interrupt */ 79 Reserved17_IRQn = 1, /**< Reserved interrupt */ 80 Reserved18_IRQn = 2, /**< Reserved interrupt */ 81 Reserved19_IRQn = 3, /**< Reserved interrupt */ 82 Reserved20_IRQn = 4, /**< Reserved interrupt */ 83 FTMRE_IRQn = 5, /**< Command complete */ 84 PMC_IRQn = 6, /**< Low-voltage warning */ 85 IRQ_IRQn = 7, /**< External interrupt */ 86 I2C0_IRQn = 8, /**< Single interrupt vector for all sources */ 87 Reserved25_IRQn = 9, /**< Reserved interrupt */ 88 SPI0_IRQn = 10, /**< Single interrupt vector for all sources */ 89 Reserved27_IRQn = 11, /**< Reserved interrupt */ 90 UART0_IRQn = 12, /**< Status and error */ 91 Reserved29_IRQn = 13, /**< Reserved interrupt */ 92 Reserved30_IRQn = 14, /**< Reserved interrupt */ 93 ADC_IRQn = 15, /**< ADC conversion complete interrupt */ 94 ACMP0_IRQn = 16, /**< Analog comparator 0 interrupt */ 95 FTM0_IRQn = 17, /**< FTM0 single interrupt vector for all sources */ 96 Reserved34_IRQn = 18, /**< Reserved interrupt */ 97 FTM2_IRQn = 19, /**< FTM2 single interrupt vector for all sources */ 98 RTC_IRQn = 20, /**< RTC overflow */ 99 ACMP1_IRQn = 21, /**< Analog comparator 1 interrupt */ 100 PIT_CH0_IRQn = 22, /**< PIT CH0 overflow */ 101 PIT_CH1_IRQn = 23, /**< PIT CH1 overflow */ 102 KBI0_IRQn = 24, /**< Keyboard interrupt0 */ 103 KBI1_IRQn = 25, /**< Keyboard interrupt1 */ 104 Reserved42_IRQn = 26, /**< Reserved interrupt */ 105 ICS_IRQn = 27, /**< Clock loss of lock */ 106 WDOG_IRQn = 28, /**< Watchdog timeout */ 107 PWT_IRQn = 29, /**< Single interrupt vector for all sources */ 108 Reserved46_IRQn = 30, /**< Reserved interrupt */ 109 Reserved47_IRQn = 31 /**< Reserved interrupt */ 110 } IRQn_Type; 111 112 /*! 113 * @} 114 */ /* end of group Interrupt_vector_numbers */ 115 116 117 /* ---------------------------------------------------------------------------- 118 -- Cortex M0 Core Configuration 119 ---------------------------------------------------------------------------- */ 120 121 /*! 122 * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration 123 * @{ 124 */ 125 126 #define __CM0PLUS_REV 0x0000 /**< Core revision r0p0 */ 127 #define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */ 128 #define __VTOR_PRESENT 1 /**< Defines if VTOR is present or not */ 129 #define __NVIC_PRIO_BITS 2 /**< Number of priority bits implemented in the NVIC */ 130 #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ 131 132 #include "core_cm0plus.h" /* Core Peripheral Access Layer */ 133 #include "system_MKE04Z4.h" /* Device specific configuration file */ 134 135 /*! 136 * @} 137 */ /* end of group Cortex_Core_Configuration */ 138 139 140 /* ---------------------------------------------------------------------------- 141 -- Device Peripheral Access Layer 142 ---------------------------------------------------------------------------- */ 143 144 /*! 145 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer 146 * @{ 147 */ 148 149 150 /* 151 ** Start of section using anonymous unions 152 */ 153 154 #if defined(__ARMCC_VERSION) 155 #if (__ARMCC_VERSION >= 6010050) 156 #pragma clang diagnostic push 157 #else 158 #pragma push 159 #pragma anon_unions 160 #endif 161 #elif defined(__CWCC__) 162 #pragma push 163 #pragma cpp_extensions on 164 #elif defined(__GNUC__) 165 /* anonymous unions are enabled by default */ 166 #elif defined(__IAR_SYSTEMS_ICC__) 167 #pragma language=extended 168 #else 169 #error Not supported compiler type 170 #endif 171 172 /* ---------------------------------------------------------------------------- 173 -- ACMP Peripheral Access Layer 174 ---------------------------------------------------------------------------- */ 175 176 /*! 177 * @addtogroup ACMP_Peripheral_Access_Layer ACMP Peripheral Access Layer 178 * @{ 179 */ 180 181 /** ACMP - Register Layout Typedef */ 182 typedef struct { 183 __IO uint8_t CS; /**< ACMP Control and Status Register, offset: 0x0 */ 184 __IO uint8_t C0; /**< ACMP Control Register 0, offset: 0x1 */ 185 __IO uint8_t C1; /**< ACMP Control Register 1, offset: 0x2 */ 186 __IO uint8_t C2; /**< ACMP Control Register 2, offset: 0x3 */ 187 } ACMP_Type; 188 189 /* ---------------------------------------------------------------------------- 190 -- ACMP Register Masks 191 ---------------------------------------------------------------------------- */ 192 193 /*! 194 * @addtogroup ACMP_Register_Masks ACMP Register Masks 195 * @{ 196 */ 197 198 /*! @name CS - ACMP Control and Status Register */ 199 /*! @{ */ 200 #define ACMP_CS_ACMOD_MASK (0x3U) 201 #define ACMP_CS_ACMOD_SHIFT (0U) 202 /*! ACMOD - ACMP MOD 203 * 0b00..ACMP interrupt on output falling edge. 204 * 0b01..ACMP interrupt on output rising edge. 205 * 0b10..ACMP interrupt on output falling edge. 206 * 0b11..ACMP interrupt on output falling or rising edge. 207 */ 208 #define ACMP_CS_ACMOD(x) (((uint8_t)(((uint8_t)(x)) << ACMP_CS_ACMOD_SHIFT)) & ACMP_CS_ACMOD_MASK) 209 #define ACMP_CS_ACOPE_MASK (0x4U) 210 #define ACMP_CS_ACOPE_SHIFT (2U) 211 /*! ACOPE - ACMP Output Pin Enable 212 * 0b0..ACMP output cannot be placed onto external pin. 213 * 0b1..ACMP output can be placed onto external pin. 214 */ 215 #define ACMP_CS_ACOPE(x) (((uint8_t)(((uint8_t)(x)) << ACMP_CS_ACOPE_SHIFT)) & ACMP_CS_ACOPE_MASK) 216 #define ACMP_CS_ACO_MASK (0x8U) 217 #define ACMP_CS_ACO_SHIFT (3U) 218 #define ACMP_CS_ACO(x) (((uint8_t)(((uint8_t)(x)) << ACMP_CS_ACO_SHIFT)) & ACMP_CS_ACO_MASK) 219 #define ACMP_CS_ACIE_MASK (0x10U) 220 #define ACMP_CS_ACIE_SHIFT (4U) 221 /*! ACIE - ACMP Interrupt Enable 222 * 0b0..Disable the ACMP Interrupt. 223 * 0b1..Enable the ACMP Interrupt. 224 */ 225 #define ACMP_CS_ACIE(x) (((uint8_t)(((uint8_t)(x)) << ACMP_CS_ACIE_SHIFT)) & ACMP_CS_ACIE_MASK) 226 #define ACMP_CS_ACF_MASK (0x20U) 227 #define ACMP_CS_ACF_SHIFT (5U) 228 #define ACMP_CS_ACF(x) (((uint8_t)(((uint8_t)(x)) << ACMP_CS_ACF_SHIFT)) & ACMP_CS_ACF_MASK) 229 #define ACMP_CS_HYST_MASK (0x40U) 230 #define ACMP_CS_HYST_SHIFT (6U) 231 /*! HYST - Analog Comparator Hysterisis Selection 232 * 0b0..20 mV. 233 * 0b1..30 mV. 234 */ 235 #define ACMP_CS_HYST(x) (((uint8_t)(((uint8_t)(x)) << ACMP_CS_HYST_SHIFT)) & ACMP_CS_HYST_MASK) 236 #define ACMP_CS_ACE_MASK (0x80U) 237 #define ACMP_CS_ACE_SHIFT (7U) 238 /*! ACE - Analog Comparator Enable 239 * 0b0..The ACMP is disabled. 240 * 0b1..The ACMP is enabled. 241 */ 242 #define ACMP_CS_ACE(x) (((uint8_t)(((uint8_t)(x)) << ACMP_CS_ACE_SHIFT)) & ACMP_CS_ACE_MASK) 243 /*! @} */ 244 245 /*! @name C0 - ACMP Control Register 0 */ 246 /*! @{ */ 247 #define ACMP_C0_ACNSEL_MASK (0x3U) 248 #define ACMP_C0_ACNSEL_SHIFT (0U) 249 /*! ACNSEL - ACMP Negative Input Select 250 * 0b00..External reference 0 251 * 0b01..External reference 1 252 * 0b10..External reference 2 253 * 0b11..DAC output 254 */ 255 #define ACMP_C0_ACNSEL(x) (((uint8_t)(((uint8_t)(x)) << ACMP_C0_ACNSEL_SHIFT)) & ACMP_C0_ACNSEL_MASK) 256 #define ACMP_C0_ACPSEL_MASK (0x30U) 257 #define ACMP_C0_ACPSEL_SHIFT (4U) 258 /*! ACPSEL - ACMP Positive Input Select 259 * 0b00..External reference 0 260 * 0b01..External reference 1 261 * 0b10..External reference 2 262 * 0b11..DAC output 263 */ 264 #define ACMP_C0_ACPSEL(x) (((uint8_t)(((uint8_t)(x)) << ACMP_C0_ACPSEL_SHIFT)) & ACMP_C0_ACPSEL_MASK) 265 /*! @} */ 266 267 /*! @name C1 - ACMP Control Register 1 */ 268 /*! @{ */ 269 #define ACMP_C1_DACVAL_MASK (0x3FU) 270 #define ACMP_C1_DACVAL_SHIFT (0U) 271 #define ACMP_C1_DACVAL(x) (((uint8_t)(((uint8_t)(x)) << ACMP_C1_DACVAL_SHIFT)) & ACMP_C1_DACVAL_MASK) 272 #define ACMP_C1_DACREF_MASK (0x40U) 273 #define ACMP_C1_DACREF_SHIFT (6U) 274 /*! DACREF - DAC Reference Select 275 * 0b0..The DAC selects Bandgap as the reference. 276 * 0b1..The DAC selects VDDA as the reference. 277 */ 278 #define ACMP_C1_DACREF(x) (((uint8_t)(((uint8_t)(x)) << ACMP_C1_DACREF_SHIFT)) & ACMP_C1_DACREF_MASK) 279 #define ACMP_C1_DACEN_MASK (0x80U) 280 #define ACMP_C1_DACEN_SHIFT (7U) 281 /*! DACEN - DAC Enable 282 * 0b0..The DAC is disabled. 283 * 0b1..The DAC is enabled. 284 */ 285 #define ACMP_C1_DACEN(x) (((uint8_t)(((uint8_t)(x)) << ACMP_C1_DACEN_SHIFT)) & ACMP_C1_DACEN_MASK) 286 /*! @} */ 287 288 /*! @name C2 - ACMP Control Register 2 */ 289 /*! @{ */ 290 #define ACMP_C2_ACIPE_MASK (0x7U) 291 #define ACMP_C2_ACIPE_SHIFT (0U) 292 /*! ACIPE - ACMP Input Pin Enable 293 * 0b000..The corresponding external analog input is not allowed. 294 * 0b001..The corresponding external analog input is allowed. 295 */ 296 #define ACMP_C2_ACIPE(x) (((uint8_t)(((uint8_t)(x)) << ACMP_C2_ACIPE_SHIFT)) & ACMP_C2_ACIPE_MASK) 297 /*! @} */ 298 299 300 /*! 301 * @} 302 */ /* end of group ACMP_Register_Masks */ 303 304 305 /* ACMP - Peripheral instance base addresses */ 306 /** Peripheral ACMP0 base address */ 307 #define ACMP0_BASE (0x40073000u) 308 /** Peripheral ACMP0 base pointer */ 309 #define ACMP0 ((ACMP_Type *)ACMP0_BASE) 310 /** Peripheral ACMP1 base address */ 311 #define ACMP1_BASE (0x40074000u) 312 /** Peripheral ACMP1 base pointer */ 313 #define ACMP1 ((ACMP_Type *)ACMP1_BASE) 314 /** Array initializer of ACMP peripheral base addresses */ 315 #define ACMP_BASE_ADDRS { ACMP0_BASE, ACMP1_BASE } 316 /** Array initializer of ACMP peripheral base pointers */ 317 #define ACMP_BASE_PTRS { ACMP0, ACMP1 } 318 /** Interrupt vectors for the ACMP peripheral type */ 319 #define ACMP_IRQS { ACMP0_IRQn, ACMP1_IRQn } 320 321 /*! 322 * @} 323 */ /* end of group ACMP_Peripheral_Access_Layer */ 324 325 326 /* ---------------------------------------------------------------------------- 327 -- ADC Peripheral Access Layer 328 ---------------------------------------------------------------------------- */ 329 330 /*! 331 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer 332 * @{ 333 */ 334 335 /** ADC - Register Layout Typedef */ 336 typedef struct { 337 __IO uint32_t SC1; /**< Status and Control Register 1, offset: 0x0 */ 338 __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x4 */ 339 __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x8 */ 340 __IO uint32_t SC4; /**< Status and Control Register 4, offset: 0xC */ 341 __I uint32_t R; /**< Conversion Result Register, offset: 0x10 */ 342 __IO uint32_t CV; /**< Compare Value Register, offset: 0x14 */ 343 __IO uint32_t APCTL1; /**< Pin Control 1 Register, offset: 0x18 */ 344 __IO uint32_t SC5; /**< Status and Control Register 5, offset: 0x1C */ 345 } ADC_Type; 346 347 /* ---------------------------------------------------------------------------- 348 -- ADC Register Masks 349 ---------------------------------------------------------------------------- */ 350 351 /*! 352 * @addtogroup ADC_Register_Masks ADC Register Masks 353 * @{ 354 */ 355 356 /*! @name SC1 - Status and Control Register 1 */ 357 /*! @{ */ 358 #define ADC_SC1_ADCH_MASK (0x1FU) 359 #define ADC_SC1_ADCH_SHIFT (0U) 360 /*! ADCH - Input Channel Select 361 * 0b10110..Temperature Sensor 362 * 0b10111..Bandgap 363 * 0b11101..VREFH 364 * 0b11110..VREFL 365 * 0b11111..Module disabled Reset FIFO in FIFO mode. 366 */ 367 #define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK) 368 #define ADC_SC1_ADCO_MASK (0x20U) 369 #define ADC_SC1_ADCO_SHIFT (5U) 370 /*! ADCO - Continuous Conversion Enable 371 * 0b0..One conversion following a write to the ADC_SC1 when software triggered operation is selected, or one conversion following assertion of ADHWT when hardware triggered operation is selected. When the FIFO function is enabled (AFDEP > 0), a set of conversion are triggered when ADC_SC2[ADTRG]=0 or both ADC_SC2[ADTRG]=1 and ADC_SC4[HTRGME]=1. 372 * 0b1..Continuous conversions are initiated following a write to ADC_SC1 when software triggered operation is selected. Continuous conversions are initiated by an ADHWT event when hardware triggered operation is selected. When the FIFO function is enabled (AFDEP > 0), a set of conversions are loop triggered. 373 */ 374 #define ADC_SC1_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCO_SHIFT)) & ADC_SC1_ADCO_MASK) 375 #define ADC_SC1_AIEN_MASK (0x40U) 376 #define ADC_SC1_AIEN_SHIFT (6U) 377 /*! AIEN - Interrupt Enable 378 * 0b0..Conversion complete interrupt disabled. 379 * 0b1..Conversion complete interrupt enabled. 380 */ 381 #define ADC_SC1_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_AIEN_SHIFT)) & ADC_SC1_AIEN_MASK) 382 #define ADC_SC1_COCO_MASK (0x80U) 383 #define ADC_SC1_COCO_SHIFT (7U) 384 /*! COCO - Conversion Complete Flag 385 * 0b0..Conversion not completed. 386 * 0b1..Conversion completed. 387 */ 388 #define ADC_SC1_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_COCO_SHIFT)) & ADC_SC1_COCO_MASK) 389 /*! @} */ 390 391 /*! @name SC2 - Status and Control Register 2 */ 392 /*! @{ */ 393 #define ADC_SC2_REFSEL_MASK (0x3U) 394 #define ADC_SC2_REFSEL_SHIFT (0U) 395 /*! REFSEL - Voltage Reference Selection 396 * 0b00..Default voltage reference pin pair (VREFH/VREFL). 397 * 0b01..Analog supply pin pair (VDDA/VSSA). 398 * 0b10..Reserved. 399 * 0b11..Reserved - Selects default voltage reference (VREFH/VREFL) pin pair. 400 */ 401 #define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_REFSEL_SHIFT)) & ADC_SC2_REFSEL_MASK) 402 #define ADC_SC2_FFULL_MASK (0x4U) 403 #define ADC_SC2_FFULL_SHIFT (2U) 404 /*! FFULL - Result FIFO full 405 * 0b0..Indicates that ADC result FIFO is not full and next conversion data still can be stored into FIFO. 406 * 0b1..Indicates that ADC result FIFO is full and next conversion will override old data in case of no read action. 407 */ 408 #define ADC_SC2_FFULL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_FFULL_SHIFT)) & ADC_SC2_FFULL_MASK) 409 #define ADC_SC2_FEMPTY_MASK (0x8U) 410 #define ADC_SC2_FEMPTY_SHIFT (3U) 411 /*! FEMPTY - Result FIFO empty 412 * 0b0..Indicates that ADC result FIFO have at least one valid new data. 413 * 0b1..Indicates that ADC result FIFO have no valid new data. 414 */ 415 #define ADC_SC2_FEMPTY(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_FEMPTY_SHIFT)) & ADC_SC2_FEMPTY_MASK) 416 #define ADC_SC2_ACFGT_MASK (0x10U) 417 #define ADC_SC2_ACFGT_SHIFT (4U) 418 /*! ACFGT - Compare Function Greater Than Enable 419 * 0b0..Compare triggers when input is less than compare level. 420 * 0b1..Compare triggers when input is greater than or equal to compare level. 421 */ 422 #define ADC_SC2_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFGT_SHIFT)) & ADC_SC2_ACFGT_MASK) 423 #define ADC_SC2_ACFE_MASK (0x20U) 424 #define ADC_SC2_ACFE_SHIFT (5U) 425 /*! ACFE - Compare Function Enable 426 * 0b0..Compare function disabled. 427 * 0b1..Compare function enabled. 428 */ 429 #define ADC_SC2_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFE_SHIFT)) & ADC_SC2_ACFE_MASK) 430 #define ADC_SC2_ADTRG_MASK (0x40U) 431 #define ADC_SC2_ADTRG_SHIFT (6U) 432 /*! ADTRG - Conversion Trigger Select 433 * 0b0..Software trigger selected. 434 * 0b1..Hardware trigger selected. 435 */ 436 #define ADC_SC2_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADTRG_SHIFT)) & ADC_SC2_ADTRG_MASK) 437 #define ADC_SC2_ADACT_MASK (0x80U) 438 #define ADC_SC2_ADACT_SHIFT (7U) 439 /*! ADACT - Conversion Active 440 * 0b0..Conversion not in progress. 441 * 0b1..Conversion in progress. 442 */ 443 #define ADC_SC2_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADACT_SHIFT)) & ADC_SC2_ADACT_MASK) 444 /*! @} */ 445 446 /*! @name SC3 - Status and Control Register 3 */ 447 /*! @{ */ 448 #define ADC_SC3_ADICLK_MASK (0x3U) 449 #define ADC_SC3_ADICLK_SHIFT (0U) 450 /*! ADICLK - Input Clock Select 451 * 0b00..Bus clock 452 * 0b01..Bus clock divided by 2 453 * 0b10..Alternate clock (ALTCLK) 454 * 0b11..Asynchronous clock (ADACK) 455 */ 456 #define ADC_SC3_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADICLK_SHIFT)) & ADC_SC3_ADICLK_MASK) 457 #define ADC_SC3_MODE_MASK (0xCU) 458 #define ADC_SC3_MODE_SHIFT (2U) 459 /*! MODE - Conversion Mode Selection 460 * 0b00..8-bit conversion (N = 8) 461 * 0b01..10-bit conversion (N = 10) 462 * 0b10..12-bit conversion (N = 12) 463 * 0b11..Reserved 464 */ 465 #define ADC_SC3_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_MODE_SHIFT)) & ADC_SC3_MODE_MASK) 466 #define ADC_SC3_ADLSMP_MASK (0x10U) 467 #define ADC_SC3_ADLSMP_SHIFT (4U) 468 /*! ADLSMP - Long Sample Time Configuration 469 * 0b0..Short sample time. 470 * 0b1..Long sample time. 471 */ 472 #define ADC_SC3_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADLSMP_SHIFT)) & ADC_SC3_ADLSMP_MASK) 473 #define ADC_SC3_ADIV_MASK (0x60U) 474 #define ADC_SC3_ADIV_SHIFT (5U) 475 /*! ADIV - Clock Divide Select 476 * 0b00..Divide ration = 1, and clock rate = Input clock. 477 * 0b01..Divide ration = 2, and clock rate = Input clock * 2. 478 * 0b10..Divide ration = 3, and clock rate = Input clock * 4. 479 * 0b11..Divide ration = 4, and clock rate = Input clock * 8. 480 */ 481 #define ADC_SC3_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADIV_SHIFT)) & ADC_SC3_ADIV_MASK) 482 #define ADC_SC3_ADLPC_MASK (0x80U) 483 #define ADC_SC3_ADLPC_SHIFT (7U) 484 /*! ADLPC - Low-Power Configuration 485 * 0b0..High speed configuration. 486 * 0b1..Low power configuration:The power is reduced at the expense of maximum clock speed. 487 */ 488 #define ADC_SC3_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADLPC_SHIFT)) & ADC_SC3_ADLPC_MASK) 489 /*! @} */ 490 491 /*! @name SC4 - Status and Control Register 4 */ 492 /*! @{ */ 493 #define ADC_SC4_AFDEP_MASK (0x7U) 494 #define ADC_SC4_AFDEP_SHIFT (0U) 495 /*! AFDEP - FIFO Depth 496 * 0b000..FIFO is disabled. 497 * 0b001..2-level FIFO is enabled. 498 * 0b010..3-level FIFO is enabled.. 499 * 0b011..4-level FIFO is enabled. 500 * 0b100..5-level FIFO is enabled. 501 * 0b101..6-level FIFO is enabled. 502 * 0b110..7-level FIFO is enabled. 503 * 0b111..8-level FIFO is enabled. 504 */ 505 #define ADC_SC4_AFDEP(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC4_AFDEP_SHIFT)) & ADC_SC4_AFDEP_MASK) 506 #define ADC_SC4_ACFSEL_MASK (0x20U) 507 #define ADC_SC4_ACFSEL_SHIFT (5U) 508 /*! ACFSEL - Compare Function Selection 509 * 0b0..OR all of compare trigger. 510 * 0b1..AND all of compare trigger. 511 */ 512 #define ADC_SC4_ACFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC4_ACFSEL_SHIFT)) & ADC_SC4_ACFSEL_MASK) 513 #define ADC_SC4_ASCANE_MASK (0x40U) 514 #define ADC_SC4_ASCANE_SHIFT (6U) 515 /*! ASCANE - FIFO Scan Mode Enable 516 * 0b0..FIFO scan mode disabled. 517 * 0b1..FIFO scan mode enabled. 518 */ 519 #define ADC_SC4_ASCANE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC4_ASCANE_SHIFT)) & ADC_SC4_ASCANE_MASK) 520 #define ADC_SC4_HTRGME_MASK (0x100U) 521 #define ADC_SC4_HTRGME_SHIFT (8U) 522 /*! HTRGME - Hardware Trigger Multiple Conversion Enable 523 * 0b0..One hardware trigger pulse triggers one conversion. 524 * 0b1..One hardware trigger pulse triggers multiple conversions in fifo mode. 525 */ 526 #define ADC_SC4_HTRGME(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC4_HTRGME_SHIFT)) & ADC_SC4_HTRGME_MASK) 527 /*! @} */ 528 529 /*! @name R - Conversion Result Register */ 530 /*! @{ */ 531 #define ADC_R_ADR_MASK (0xFFFU) 532 #define ADC_R_ADR_SHIFT (0U) 533 #define ADC_R_ADR(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_ADR_SHIFT)) & ADC_R_ADR_MASK) 534 /*! @} */ 535 536 /*! @name CV - Compare Value Register */ 537 /*! @{ */ 538 #define ADC_CV_CV_MASK (0xFFFU) 539 #define ADC_CV_CV_SHIFT (0U) 540 #define ADC_CV_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CV_SHIFT)) & ADC_CV_CV_MASK) 541 /*! @} */ 542 543 /*! @name APCTL1 - Pin Control 1 Register */ 544 /*! @{ */ 545 #define ADC_APCTL1_ADPC_MASK (0xFFFFU) 546 #define ADC_APCTL1_ADPC_SHIFT (0U) 547 /*! ADPC - ADC Pin Control 548 * 0b0000000000000000..ADx pin I/O control enabled. 549 * 0b0000000000000001..ADx pin I/O control disabled. 550 */ 551 #define ADC_APCTL1_ADPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_APCTL1_ADPC_SHIFT)) & ADC_APCTL1_ADPC_MASK) 552 /*! @} */ 553 554 /*! @name SC5 - Status and Control Register 5 */ 555 /*! @{ */ 556 #define ADC_SC5_HTRGMASKSEL_MASK (0x1U) 557 #define ADC_SC5_HTRGMASKSEL_SHIFT (0U) 558 /*! HTRGMASKSEL - Hardware Trigger Mask Mode Select 559 * 0b0..Hardware trigger mask with HTRGMASKE. 560 * 0b1..Hardware trigger mask automatically when data fifo is not empty. 561 */ 562 #define ADC_SC5_HTRGMASKSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC5_HTRGMASKSEL_SHIFT)) & ADC_SC5_HTRGMASKSEL_MASK) 563 #define ADC_SC5_HTRGMASKE_MASK (0x2U) 564 #define ADC_SC5_HTRGMASKE_SHIFT (1U) 565 /*! HTRGMASKE - Hardware Trigger Mask Enable 566 * 0b0..Hardware trigger mask disable. 567 * 0b1..Hardware trigger mask enable and hardware trigger cannot trigger ADC conversion.. 568 */ 569 #define ADC_SC5_HTRGMASKE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC5_HTRGMASKE_SHIFT)) & ADC_SC5_HTRGMASKE_MASK) 570 /*! @} */ 571 572 573 /*! 574 * @} 575 */ /* end of group ADC_Register_Masks */ 576 577 578 /* ADC - Peripheral instance base addresses */ 579 /** Peripheral ADC base address */ 580 #define ADC_BASE (0x4003B000u) 581 /** Peripheral ADC base pointer */ 582 #define ADC ((ADC_Type *)ADC_BASE) 583 /** Array initializer of ADC peripheral base addresses */ 584 #define ADC_BASE_ADDRS { ADC_BASE } 585 /** Array initializer of ADC peripheral base pointers */ 586 #define ADC_BASE_PTRS { ADC } 587 /** Interrupt vectors for the ADC peripheral type */ 588 #define ADC_IRQS { ADC_IRQn } 589 590 /*! 591 * @} 592 */ /* end of group ADC_Peripheral_Access_Layer */ 593 594 595 /* ---------------------------------------------------------------------------- 596 -- CRC Peripheral Access Layer 597 ---------------------------------------------------------------------------- */ 598 599 /*! 600 * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer 601 * @{ 602 */ 603 604 /** CRC - Register Layout Typedef */ 605 typedef struct { 606 union { /* offset: 0x0 */ 607 struct { /* offset: 0x0 */ 608 __IO uint16_t DATAL; /**< CRC_DATAL register., offset: 0x0 */ 609 __IO uint16_t DATAH; /**< CRC_DATAH register., offset: 0x2 */ 610 } ACCESS16BIT; 611 __IO uint32_t DATA; /**< CRC Data register, offset: 0x0 */ 612 struct { /* offset: 0x0 */ 613 __IO uint8_t DATALL; /**< CRC_DATALL register., offset: 0x0 */ 614 __IO uint8_t DATALU; /**< CRC_DATALU register., offset: 0x1 */ 615 __IO uint8_t DATAHL; /**< CRC_DATAHL register., offset: 0x2 */ 616 __IO uint8_t DATAHU; /**< CRC_DATAHU register., offset: 0x3 */ 617 } ACCESS8BIT; 618 }; 619 union { /* offset: 0x4 */ 620 struct { /* offset: 0x4 */ 621 __IO uint16_t GPOLYL; /**< CRC_GPOLYL register., offset: 0x4 */ 622 __IO uint16_t GPOLYH; /**< CRC_GPOLYH register., offset: 0x6 */ 623 } GPOLY_ACCESS16BIT; 624 __IO uint32_t GPOLY; /**< CRC Polynomial register, offset: 0x4 */ 625 struct { /* offset: 0x4 */ 626 __IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register., offset: 0x4 */ 627 __IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register., offset: 0x5 */ 628 __IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register., offset: 0x6 */ 629 __IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register., offset: 0x7 */ 630 } GPOLY_ACCESS8BIT; 631 }; 632 union { /* offset: 0x8 */ 633 __IO uint32_t CTRL; /**< CRC Control register, offset: 0x8 */ 634 struct { /* offset: 0x8 */ 635 uint8_t RESERVED_0[3]; 636 __IO uint8_t CTRLHU; /**< CRC_CTRLHU register., offset: 0xB */ 637 } CTRL_ACCESS8BIT; 638 }; 639 } CRC_Type; 640 641 /* ---------------------------------------------------------------------------- 642 -- CRC Register Masks 643 ---------------------------------------------------------------------------- */ 644 645 /*! 646 * @addtogroup CRC_Register_Masks CRC Register Masks 647 * @{ 648 */ 649 650 /*! @name DATAL - CRC_DATAL register. */ 651 /*! @{ */ 652 #define CRC_DATAL_DATAL_MASK (0xFFFFU) 653 #define CRC_DATAL_DATAL_SHIFT (0U) 654 #define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAL_DATAL_SHIFT)) & CRC_DATAL_DATAL_MASK) 655 /*! @} */ 656 657 /*! @name DATAH - CRC_DATAH register. */ 658 /*! @{ */ 659 #define CRC_DATAH_DATAH_MASK (0xFFFFU) 660 #define CRC_DATAH_DATAH_SHIFT (0U) 661 #define CRC_DATAH_DATAH(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAH_DATAH_SHIFT)) & CRC_DATAH_DATAH_MASK) 662 /*! @} */ 663 664 /*! @name DATA - CRC Data register */ 665 /*! @{ */ 666 #define CRC_DATA_LL_MASK (0xFFU) 667 #define CRC_DATA_LL_SHIFT (0U) 668 #define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LL_SHIFT)) & CRC_DATA_LL_MASK) 669 #define CRC_DATA_LU_MASK (0xFF00U) 670 #define CRC_DATA_LU_SHIFT (8U) 671 #define CRC_DATA_LU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LU_SHIFT)) & CRC_DATA_LU_MASK) 672 #define CRC_DATA_HL_MASK (0xFF0000U) 673 #define CRC_DATA_HL_SHIFT (16U) 674 #define CRC_DATA_HL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HL_SHIFT)) & CRC_DATA_HL_MASK) 675 #define CRC_DATA_HU_MASK (0xFF000000U) 676 #define CRC_DATA_HU_SHIFT (24U) 677 #define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HU_SHIFT)) & CRC_DATA_HU_MASK) 678 /*! @} */ 679 680 /*! @name DATALL - CRC_DATALL register. */ 681 /*! @{ */ 682 #define CRC_DATALL_DATALL_MASK (0xFFU) 683 #define CRC_DATALL_DATALL_SHIFT (0U) 684 #define CRC_DATALL_DATALL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALL_DATALL_SHIFT)) & CRC_DATALL_DATALL_MASK) 685 /*! @} */ 686 687 /*! @name DATALU - CRC_DATALU register. */ 688 /*! @{ */ 689 #define CRC_DATALU_DATALU_MASK (0xFFU) 690 #define CRC_DATALU_DATALU_SHIFT (0U) 691 #define CRC_DATALU_DATALU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALU_DATALU_SHIFT)) & CRC_DATALU_DATALU_MASK) 692 /*! @} */ 693 694 /*! @name DATAHL - CRC_DATAHL register. */ 695 /*! @{ */ 696 #define CRC_DATAHL_DATAHL_MASK (0xFFU) 697 #define CRC_DATAHL_DATAHL_SHIFT (0U) 698 #define CRC_DATAHL_DATAHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHL_DATAHL_SHIFT)) & CRC_DATAHL_DATAHL_MASK) 699 /*! @} */ 700 701 /*! @name DATAHU - CRC_DATAHU register. */ 702 /*! @{ */ 703 #define CRC_DATAHU_DATAHU_MASK (0xFFU) 704 #define CRC_DATAHU_DATAHU_SHIFT (0U) 705 #define CRC_DATAHU_DATAHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHU_DATAHU_SHIFT)) & CRC_DATAHU_DATAHU_MASK) 706 /*! @} */ 707 708 /*! @name GPOLYL - CRC_GPOLYL register. */ 709 /*! @{ */ 710 #define CRC_GPOLYL_GPOLYL_MASK (0xFFFFU) 711 #define CRC_GPOLYL_GPOLYL_SHIFT (0U) 712 #define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYL_GPOLYL_SHIFT)) & CRC_GPOLYL_GPOLYL_MASK) 713 /*! @} */ 714 715 /*! @name GPOLYH - CRC_GPOLYH register. */ 716 /*! @{ */ 717 #define CRC_GPOLYH_GPOLYH_MASK (0xFFFFU) 718 #define CRC_GPOLYH_GPOLYH_SHIFT (0U) 719 #define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYH_GPOLYH_SHIFT)) & CRC_GPOLYH_GPOLYH_MASK) 720 /*! @} */ 721 722 /*! @name GPOLY - CRC Polynomial register */ 723 /*! @{ */ 724 #define CRC_GPOLY_LOW_MASK (0xFFFFU) 725 #define CRC_GPOLY_LOW_SHIFT (0U) 726 #define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_LOW_SHIFT)) & CRC_GPOLY_LOW_MASK) 727 #define CRC_GPOLY_HIGH_MASK (0xFFFF0000U) 728 #define CRC_GPOLY_HIGH_SHIFT (16U) 729 #define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_HIGH_SHIFT)) & CRC_GPOLY_HIGH_MASK) 730 /*! @} */ 731 732 /*! @name GPOLYLL - CRC_GPOLYLL register. */ 733 /*! @{ */ 734 #define CRC_GPOLYLL_GPOLYLL_MASK (0xFFU) 735 #define CRC_GPOLYLL_GPOLYLL_SHIFT (0U) 736 #define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLL_GPOLYLL_SHIFT)) & CRC_GPOLYLL_GPOLYLL_MASK) 737 /*! @} */ 738 739 /*! @name GPOLYLU - CRC_GPOLYLU register. */ 740 /*! @{ */ 741 #define CRC_GPOLYLU_GPOLYLU_MASK (0xFFU) 742 #define CRC_GPOLYLU_GPOLYLU_SHIFT (0U) 743 #define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLU_GPOLYLU_SHIFT)) & CRC_GPOLYLU_GPOLYLU_MASK) 744 /*! @} */ 745 746 /*! @name GPOLYHL - CRC_GPOLYHL register. */ 747 /*! @{ */ 748 #define CRC_GPOLYHL_GPOLYHL_MASK (0xFFU) 749 #define CRC_GPOLYHL_GPOLYHL_SHIFT (0U) 750 #define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHL_GPOLYHL_SHIFT)) & CRC_GPOLYHL_GPOLYHL_MASK) 751 /*! @} */ 752 753 /*! @name GPOLYHU - CRC_GPOLYHU register. */ 754 /*! @{ */ 755 #define CRC_GPOLYHU_GPOLYHU_MASK (0xFFU) 756 #define CRC_GPOLYHU_GPOLYHU_SHIFT (0U) 757 #define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHU_GPOLYHU_SHIFT)) & CRC_GPOLYHU_GPOLYHU_MASK) 758 /*! @} */ 759 760 /*! @name CTRL - CRC Control register */ 761 /*! @{ */ 762 #define CRC_CTRL_TCRC_MASK (0x1000000U) 763 #define CRC_CTRL_TCRC_SHIFT (24U) 764 /*! TCRC 765 * 0b0..16-bit CRC protocol. 766 * 0b1..32-bit CRC protocol. 767 */ 768 #define CRC_CTRL_TCRC(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TCRC_SHIFT)) & CRC_CTRL_TCRC_MASK) 769 #define CRC_CTRL_WAS_MASK (0x2000000U) 770 #define CRC_CTRL_WAS_SHIFT (25U) 771 /*! WAS - Write CRC Data Register As Seed 772 * 0b0..Writes to the CRC data register are data values. 773 * 0b1..Writes to the CRC data register are seed values. 774 */ 775 #define CRC_CTRL_WAS(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_WAS_SHIFT)) & CRC_CTRL_WAS_MASK) 776 #define CRC_CTRL_FXOR_MASK (0x4000000U) 777 #define CRC_CTRL_FXOR_SHIFT (26U) 778 /*! FXOR - Complement Read Of CRC Data Register 779 * 0b0..No XOR on reading. 780 * 0b1..Invert or complement the read value of the CRC Data register. 781 */ 782 #define CRC_CTRL_FXOR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_FXOR_SHIFT)) & CRC_CTRL_FXOR_MASK) 783 #define CRC_CTRL_TOTR_MASK (0x30000000U) 784 #define CRC_CTRL_TOTR_SHIFT (28U) 785 /*! TOTR - Type Of Transpose For Read 786 * 0b00..No transposition. 787 * 0b01..Bits in bytes are transposed; bytes are not transposed. 788 * 0b10..Both bits in bytes and bytes are transposed. 789 * 0b11..Only bytes are transposed; no bits in a byte are transposed. 790 */ 791 #define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOTR_SHIFT)) & CRC_CTRL_TOTR_MASK) 792 #define CRC_CTRL_TOT_MASK (0xC0000000U) 793 #define CRC_CTRL_TOT_SHIFT (30U) 794 /*! TOT - Type Of Transpose For Writes 795 * 0b00..No transposition. 796 * 0b01..Bits in bytes are transposed; bytes are not transposed. 797 * 0b10..Both bits in bytes and bytes are transposed. 798 * 0b11..Only bytes are transposed; no bits in a byte are transposed. 799 */ 800 #define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOT_SHIFT)) & CRC_CTRL_TOT_MASK) 801 /*! @} */ 802 803 /*! @name CTRLHU - CRC_CTRLHU register. */ 804 /*! @{ */ 805 #define CRC_CTRLHU_TCRC_MASK (0x1U) 806 #define CRC_CTRLHU_TCRC_SHIFT (0U) 807 /*! TCRC 808 * 0b0..16-bit CRC protocol. 809 * 0b1..32-bit CRC protocol. 810 */ 811 #define CRC_CTRLHU_TCRC(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TCRC_SHIFT)) & CRC_CTRLHU_TCRC_MASK) 812 #define CRC_CTRLHU_WAS_MASK (0x2U) 813 #define CRC_CTRLHU_WAS_SHIFT (1U) 814 /*! WAS 815 * 0b0..Writes to CRC data register are data values. 816 * 0b1..Writes to CRC data reguster are seed values. 817 */ 818 #define CRC_CTRLHU_WAS(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_WAS_SHIFT)) & CRC_CTRLHU_WAS_MASK) 819 #define CRC_CTRLHU_FXOR_MASK (0x4U) 820 #define CRC_CTRLHU_FXOR_SHIFT (2U) 821 /*! FXOR 822 * 0b0..No XOR on reading. 823 * 0b1..Invert or complement the read value of CRC data register. 824 */ 825 #define CRC_CTRLHU_FXOR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_FXOR_SHIFT)) & CRC_CTRLHU_FXOR_MASK) 826 #define CRC_CTRLHU_TOTR_MASK (0x30U) 827 #define CRC_CTRLHU_TOTR_SHIFT (4U) 828 /*! TOTR 829 * 0b00..No Transposition. 830 * 0b01..Bits in bytes are transposed, bytes are not transposed. 831 * 0b10..Both bits in bytes and bytes are transposed. 832 * 0b11..Only bytes are transposed; no bits in a byte are transposed. 833 */ 834 #define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOTR_SHIFT)) & CRC_CTRLHU_TOTR_MASK) 835 #define CRC_CTRLHU_TOT_MASK (0xC0U) 836 #define CRC_CTRLHU_TOT_SHIFT (6U) 837 /*! TOT 838 * 0b00..No Transposition. 839 * 0b01..Bits in bytes are transposed, bytes are not transposed. 840 * 0b10..Both bits in bytes and bytes are transposed. 841 * 0b11..Only bytes are transposed; no bits in a byte are transposed. 842 */ 843 #define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOT_SHIFT)) & CRC_CTRLHU_TOT_MASK) 844 /*! @} */ 845 846 847 /*! 848 * @} 849 */ /* end of group CRC_Register_Masks */ 850 851 852 /* CRC - Peripheral instance base addresses */ 853 /** Peripheral CRC base address */ 854 #define CRC_BASE (0x40032000u) 855 /** Peripheral CRC base pointer */ 856 #define CRC0 ((CRC_Type *)CRC_BASE) 857 /** Array initializer of CRC peripheral base addresses */ 858 #define CRC_BASE_ADDRS { CRC_BASE } 859 /** Array initializer of CRC peripheral base pointers */ 860 #define CRC_BASE_PTRS { CRC0 } 861 862 /*! 863 * @} 864 */ /* end of group CRC_Peripheral_Access_Layer */ 865 866 867 /* ---------------------------------------------------------------------------- 868 -- FGPIO Peripheral Access Layer 869 ---------------------------------------------------------------------------- */ 870 871 /*! 872 * @addtogroup FGPIO_Peripheral_Access_Layer FGPIO Peripheral Access Layer 873 * @{ 874 */ 875 876 /** FGPIO - Register Layout Typedef */ 877 typedef struct { 878 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */ 879 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */ 880 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */ 881 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */ 882 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */ 883 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */ 884 __IO uint32_t PIDR; /**< Port Input Disable Register, offset: 0x18 */ 885 } FGPIO_Type; 886 887 /* ---------------------------------------------------------------------------- 888 -- FGPIO Register Masks 889 ---------------------------------------------------------------------------- */ 890 891 /*! 892 * @addtogroup FGPIO_Register_Masks FGPIO Register Masks 893 * @{ 894 */ 895 896 /*! @name PDOR - Port Data Output Register */ 897 /*! @{ */ 898 #define FGPIO_PDOR_PDO_MASK (0xFFFFFFFFU) 899 #define FGPIO_PDOR_PDO_SHIFT (0U) 900 /*! PDO - Port Data Output 901 * 0b00000000000000000000000000000000..Logic level 0 is driven on pin, provided pin is configured for general-purpose output. 902 * 0b00000000000000000000000000000001..Logic level 1 is driven on pin, provided pin is configured for general-purpose output. 903 */ 904 #define FGPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PDOR_PDO_SHIFT)) & FGPIO_PDOR_PDO_MASK) 905 /*! @} */ 906 907 /*! @name PSOR - Port Set Output Register */ 908 /*! @{ */ 909 #define FGPIO_PSOR_PTSO_MASK (0xFFFFFFFFU) 910 #define FGPIO_PSOR_PTSO_SHIFT (0U) 911 /*! PTSO - Port Set Output 912 * 0b00000000000000000000000000000000..Corresponding bit in PDORn does not change. 913 * 0b00000000000000000000000000000001..Corresponding bit in PDORn is set to logic 1. 914 */ 915 #define FGPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PSOR_PTSO_SHIFT)) & FGPIO_PSOR_PTSO_MASK) 916 /*! @} */ 917 918 /*! @name PCOR - Port Clear Output Register */ 919 /*! @{ */ 920 #define FGPIO_PCOR_PTCO_MASK (0xFFFFFFFFU) 921 #define FGPIO_PCOR_PTCO_SHIFT (0U) 922 /*! PTCO - Port Clear Output 923 * 0b00000000000000000000000000000000..Corresponding bit in PDORn does not change. 924 * 0b00000000000000000000000000000001..Corresponding bit in PDORn is cleared to logic 0. 925 */ 926 #define FGPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PCOR_PTCO_SHIFT)) & FGPIO_PCOR_PTCO_MASK) 927 /*! @} */ 928 929 /*! @name PTOR - Port Toggle Output Register */ 930 /*! @{ */ 931 #define FGPIO_PTOR_PTTO_MASK (0xFFFFFFFFU) 932 #define FGPIO_PTOR_PTTO_SHIFT (0U) 933 /*! PTTO - Port Toggle Output 934 * 0b00000000000000000000000000000000..Corresponding bit in PDORn does not change. 935 * 0b00000000000000000000000000000001..Corresponding bit in PDORn is set to the inverse of its existing logic state. 936 */ 937 #define FGPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PTOR_PTTO_SHIFT)) & FGPIO_PTOR_PTTO_MASK) 938 /*! @} */ 939 940 /*! @name PDIR - Port Data Input Register */ 941 /*! @{ */ 942 #define FGPIO_PDIR_PDI_MASK (0xFFFFFFFFU) 943 #define FGPIO_PDIR_PDI_SHIFT (0U) 944 /*! PDI - Port Data Input 945 * 0b00000000000000000000000000000000..Pin logic level is logic 0, or is not configured for use by digital function. 946 * 0b00000000000000000000000000000001..Pin logic level is logic 1. 947 */ 948 #define FGPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PDIR_PDI_SHIFT)) & FGPIO_PDIR_PDI_MASK) 949 /*! @} */ 950 951 /*! @name PDDR - Port Data Direction Register */ 952 /*! @{ */ 953 #define FGPIO_PDDR_PDD_MASK (0xFFFFFFFFU) 954 #define FGPIO_PDDR_PDD_SHIFT (0U) 955 /*! PDD - Port Data Direction 956 * 0b00000000000000000000000000000000..Pin is configured as general-purpose input, for the GPIO function. The pin will be high-Z if the port input is disabled in FPIOx_PIDR register. 957 * 0b00000000000000000000000000000001..Pin is configured as general-purpose output, for the GPIO function. 958 */ 959 #define FGPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PDDR_PDD_SHIFT)) & FGPIO_PDDR_PDD_MASK) 960 /*! @} */ 961 962 /*! @name PIDR - Port Input Disable Register */ 963 /*! @{ */ 964 #define FGPIO_PIDR_PID_MASK (0xFFFFFFFFU) 965 #define FGPIO_PIDR_PID_SHIFT (0U) 966 /*! PID - Port Input Disable 967 * 0b00000000000000000000000000000000..Pin is configured for General Purpose Input, provided the pin is configured for any digital function. 968 * 0b00000000000000000000000000000001..Pin is not configured as General Purpose Input. Corresponding Port Data Input Register bit will read zero. 969 */ 970 #define FGPIO_PIDR_PID(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PIDR_PID_SHIFT)) & FGPIO_PIDR_PID_MASK) 971 /*! @} */ 972 973 974 /*! 975 * @} 976 */ /* end of group FGPIO_Register_Masks */ 977 978 979 /* FGPIO - Peripheral instance base addresses */ 980 /** Peripheral FGPIOA base address */ 981 #define FGPIOA_BASE (0xF8000000u) 982 /** Peripheral FGPIOA base pointer */ 983 #define FGPIOA ((FGPIO_Type *)FGPIOA_BASE) 984 /** Array initializer of FGPIO peripheral base addresses */ 985 #define FGPIO_BASE_ADDRS { FGPIOA_BASE } 986 /** Array initializer of FGPIO peripheral base pointers */ 987 #define FGPIO_BASE_PTRS { FGPIOA } 988 989 /*! 990 * @} 991 */ /* end of group FGPIO_Peripheral_Access_Layer */ 992 993 994 /* ---------------------------------------------------------------------------- 995 -- FTM Peripheral Access Layer 996 ---------------------------------------------------------------------------- */ 997 998 /*! 999 * @addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer 1000 * @{ 1001 */ 1002 1003 /** FTM - Register Layout Typedef */ 1004 typedef struct { 1005 __IO uint32_t SC; /**< Status And Control, offset: 0x0 */ 1006 __IO uint32_t CNT; /**< Counter, offset: 0x4 */ 1007 __IO uint32_t MOD; /**< Modulo, offset: 0x8 */ 1008 struct { /* offset: 0xC, array step: 0x8 */ 1009 __IO uint32_t CnSC; /**< Channel (n) Status And Control, array offset: 0xC, array step: 0x8 */ 1010 __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */ 1011 } CONTROLS[8]; 1012 __IO uint32_t CNTIN; /**< Counter Initial Value, offset: 0x4C */ 1013 __IO uint32_t STATUS; /**< Capture And Compare Status, offset: 0x50 */ 1014 __IO uint32_t MODE; /**< Features Mode Selection, offset: 0x54 */ 1015 __IO uint32_t SYNC; /**< Synchronization, offset: 0x58 */ 1016 __IO uint32_t OUTINIT; /**< Initial State For Channels Output, offset: 0x5C */ 1017 __IO uint32_t OUTMASK; /**< Output Mask, offset: 0x60 */ 1018 __IO uint32_t COMBINE; /**< Function For Linked Channels, offset: 0x64 */ 1019 __IO uint32_t DEADTIME; /**< Deadtime Insertion Control, offset: 0x68 */ 1020 __IO uint32_t EXTTRIG; /**< FTM External Trigger, offset: 0x6C */ 1021 __IO uint32_t POL; /**< Channels Polarity, offset: 0x70 */ 1022 __IO uint32_t FMS; /**< Fault Mode Status, offset: 0x74 */ 1023 __IO uint32_t FILTER; /**< Input Capture Filter Control, offset: 0x78 */ 1024 __IO uint32_t FLTCTRL; /**< Fault Control, offset: 0x7C */ 1025 uint8_t RESERVED_0[4]; 1026 __IO uint32_t CONF; /**< Configuration, offset: 0x84 */ 1027 __IO uint32_t FLTPOL; /**< FTM Fault Input Polarity, offset: 0x88 */ 1028 __IO uint32_t SYNCONF; /**< Synchronization Configuration, offset: 0x8C */ 1029 __IO uint32_t INVCTRL; /**< FTM Inverting Control, offset: 0x90 */ 1030 __IO uint32_t SWOCTRL; /**< FTM Software Output Control, offset: 0x94 */ 1031 __IO uint32_t PWMLOAD; /**< FTM PWM Load, offset: 0x98 */ 1032 } FTM_Type; 1033 1034 /* ---------------------------------------------------------------------------- 1035 -- FTM Register Masks 1036 ---------------------------------------------------------------------------- */ 1037 1038 /*! 1039 * @addtogroup FTM_Register_Masks FTM Register Masks 1040 * @{ 1041 */ 1042 1043 /*! @name SC - Status And Control */ 1044 /*! @{ */ 1045 #define FTM_SC_PS_MASK (0x7U) 1046 #define FTM_SC_PS_SHIFT (0U) 1047 /*! PS - Prescale Factor Selection 1048 * 0b000..Divide by 1 1049 * 0b001..Divide by 2 1050 * 0b010..Divide by 4 1051 * 0b011..Divide by 8 1052 * 0b100..Divide by 16 1053 * 0b101..Divide by 32 1054 * 0b110..Divide by 64 1055 * 0b111..Divide by 128 1056 */ 1057 #define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PS_SHIFT)) & FTM_SC_PS_MASK) 1058 #define FTM_SC_CLKS_MASK (0x18U) 1059 #define FTM_SC_CLKS_SHIFT (3U) 1060 /*! CLKS - Clock Source Selection 1061 * 0b00..No clock selected. This in effect disables the FTM counter. 1062 * 0b01..System clock 1063 * 0b10..Fixed frequency clock 1064 * 0b11..External clock 1065 */ 1066 #define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_CLKS_SHIFT)) & FTM_SC_CLKS_MASK) 1067 #define FTM_SC_CPWMS_MASK (0x20U) 1068 #define FTM_SC_CPWMS_SHIFT (5U) 1069 /*! CPWMS - Center-Aligned PWM Select 1070 * 0b0..FTM counter operates in Up Counting mode. 1071 * 0b1..FTM counter operates in Up-Down Counting mode. 1072 */ 1073 #define FTM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_CPWMS_SHIFT)) & FTM_SC_CPWMS_MASK) 1074 #define FTM_SC_TOIE_MASK (0x40U) 1075 #define FTM_SC_TOIE_SHIFT (6U) 1076 /*! TOIE - Timer Overflow Interrupt Enable 1077 * 0b0..Disable TOF interrupts. Use software polling. 1078 * 0b1..Enable TOF interrupts. An interrupt is generated when TOF equals one. 1079 */ 1080 #define FTM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOIE_SHIFT)) & FTM_SC_TOIE_MASK) 1081 #define FTM_SC_TOF_MASK (0x80U) 1082 #define FTM_SC_TOF_SHIFT (7U) 1083 /*! TOF - Timer Overflow Flag 1084 * 0b0..FTM counter has not overflowed. 1085 * 0b1..FTM counter has overflowed. 1086 */ 1087 #define FTM_SC_TOF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOF_SHIFT)) & FTM_SC_TOF_MASK) 1088 /*! @} */ 1089 1090 /*! @name CNT - Counter */ 1091 /*! @{ */ 1092 #define FTM_CNT_COUNT_MASK (0xFFFFU) 1093 #define FTM_CNT_COUNT_SHIFT (0U) 1094 #define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CNT_COUNT_SHIFT)) & FTM_CNT_COUNT_MASK) 1095 /*! @} */ 1096 1097 /*! @name MOD - Modulo */ 1098 /*! @{ */ 1099 #define FTM_MOD_MOD_MASK (0xFFFFU) 1100 #define FTM_MOD_MOD_SHIFT (0U) 1101 #define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << FTM_MOD_MOD_SHIFT)) & FTM_MOD_MOD_MASK) 1102 /*! @} */ 1103 1104 /*! @name CnSC - Channel (n) Status And Control */ 1105 /*! @{ */ 1106 #define FTM_CnSC_ELSA_MASK (0x4U) 1107 #define FTM_CnSC_ELSA_SHIFT (2U) 1108 #define FTM_CnSC_ELSA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSA_SHIFT)) & FTM_CnSC_ELSA_MASK) 1109 #define FTM_CnSC_ELSB_MASK (0x8U) 1110 #define FTM_CnSC_ELSB_SHIFT (3U) 1111 #define FTM_CnSC_ELSB(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSB_SHIFT)) & FTM_CnSC_ELSB_MASK) 1112 #define FTM_CnSC_MSA_MASK (0x10U) 1113 #define FTM_CnSC_MSA_SHIFT (4U) 1114 #define FTM_CnSC_MSA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSA_SHIFT)) & FTM_CnSC_MSA_MASK) 1115 #define FTM_CnSC_MSB_MASK (0x20U) 1116 #define FTM_CnSC_MSB_SHIFT (5U) 1117 #define FTM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSB_SHIFT)) & FTM_CnSC_MSB_MASK) 1118 #define FTM_CnSC_CHIE_MASK (0x40U) 1119 #define FTM_CnSC_CHIE_SHIFT (6U) 1120 /*! CHIE - Channel Interrupt Enable 1121 * 0b0..Disable channel interrupts. Use software polling. 1122 * 0b1..Enable channel interrupts. 1123 */ 1124 #define FTM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHIE_SHIFT)) & FTM_CnSC_CHIE_MASK) 1125 #define FTM_CnSC_CHF_MASK (0x80U) 1126 #define FTM_CnSC_CHF_SHIFT (7U) 1127 /*! CHF - Channel Flag 1128 * 0b0..No channel event has occurred. 1129 * 0b1..A channel event has occurred. 1130 */ 1131 #define FTM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHF_SHIFT)) & FTM_CnSC_CHF_MASK) 1132 /*! @} */ 1133 1134 /* The count of FTM_CnSC */ 1135 #define FTM_CnSC_COUNT (8U) 1136 1137 /*! @name CnV - Channel (n) Value */ 1138 /*! @{ */ 1139 #define FTM_CnV_VAL_MASK (0xFFFFU) 1140 #define FTM_CnV_VAL_SHIFT (0U) 1141 #define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnV_VAL_SHIFT)) & FTM_CnV_VAL_MASK) 1142 /*! @} */ 1143 1144 /* The count of FTM_CnV */ 1145 #define FTM_CnV_COUNT (8U) 1146 1147 /*! @name CNTIN - Counter Initial Value */ 1148 /*! @{ */ 1149 #define FTM_CNTIN_INIT_MASK (0xFFFFU) 1150 #define FTM_CNTIN_INIT_SHIFT (0U) 1151 #define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CNTIN_INIT_SHIFT)) & FTM_CNTIN_INIT_MASK) 1152 /*! @} */ 1153 1154 /*! @name STATUS - Capture And Compare Status */ 1155 /*! @{ */ 1156 #define FTM_STATUS_CH0F_MASK (0x1U) 1157 #define FTM_STATUS_CH0F_SHIFT (0U) 1158 /*! CH0F - Channel 0 Flag 1159 * 0b0..No channel event has occurred. 1160 * 0b1..A channel event has occurred. 1161 */ 1162 #define FTM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH0F_SHIFT)) & FTM_STATUS_CH0F_MASK) 1163 #define FTM_STATUS_CH1F_MASK (0x2U) 1164 #define FTM_STATUS_CH1F_SHIFT (1U) 1165 /*! CH1F - Channel 1 Flag 1166 * 0b0..No channel event has occurred. 1167 * 0b1..A channel event has occurred. 1168 */ 1169 #define FTM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH1F_SHIFT)) & FTM_STATUS_CH1F_MASK) 1170 #define FTM_STATUS_CH2F_MASK (0x4U) 1171 #define FTM_STATUS_CH2F_SHIFT (2U) 1172 /*! CH2F - Channel 2 Flag 1173 * 0b0..No channel event has occurred. 1174 * 0b1..A channel event has occurred. 1175 */ 1176 #define FTM_STATUS_CH2F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH2F_SHIFT)) & FTM_STATUS_CH2F_MASK) 1177 #define FTM_STATUS_CH3F_MASK (0x8U) 1178 #define FTM_STATUS_CH3F_SHIFT (3U) 1179 /*! CH3F - Channel 3 Flag 1180 * 0b0..No channel event has occurred. 1181 * 0b1..A channel event has occurred. 1182 */ 1183 #define FTM_STATUS_CH3F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH3F_SHIFT)) & FTM_STATUS_CH3F_MASK) 1184 #define FTM_STATUS_CH4F_MASK (0x10U) 1185 #define FTM_STATUS_CH4F_SHIFT (4U) 1186 /*! CH4F - Channel 4 Flag 1187 * 0b0..No channel event has occurred. 1188 * 0b1..A channel event has occurred. 1189 */ 1190 #define FTM_STATUS_CH4F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH4F_SHIFT)) & FTM_STATUS_CH4F_MASK) 1191 #define FTM_STATUS_CH5F_MASK (0x20U) 1192 #define FTM_STATUS_CH5F_SHIFT (5U) 1193 /*! CH5F - Channel 5 Flag 1194 * 0b0..No channel event has occurred. 1195 * 0b1..A channel event has occurred. 1196 */ 1197 #define FTM_STATUS_CH5F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH5F_SHIFT)) & FTM_STATUS_CH5F_MASK) 1198 #define FTM_STATUS_CH6F_MASK (0x40U) 1199 #define FTM_STATUS_CH6F_SHIFT (6U) 1200 /*! CH6F - Channel 6 Flag 1201 * 0b0..No channel event has occurred. 1202 * 0b1..A channel event has occurred. 1203 */ 1204 #define FTM_STATUS_CH6F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH6F_SHIFT)) & FTM_STATUS_CH6F_MASK) 1205 #define FTM_STATUS_CH7F_MASK (0x80U) 1206 #define FTM_STATUS_CH7F_SHIFT (7U) 1207 /*! CH7F - Channel 7 Flag 1208 * 0b0..No channel event has occurred. 1209 * 0b1..A channel event has occurred. 1210 */ 1211 #define FTM_STATUS_CH7F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH7F_SHIFT)) & FTM_STATUS_CH7F_MASK) 1212 /*! @} */ 1213 1214 /*! @name MODE - Features Mode Selection */ 1215 /*! @{ */ 1216 #define FTM_MODE_FTMEN_MASK (0x1U) 1217 #define FTM_MODE_FTMEN_SHIFT (0U) 1218 /*! FTMEN - FTM Enable 1219 * 0b0..Only the TPM-compatible registers (first set of registers) can be used without any restriction. Do not use the FTM-specific registers. 1220 * 0b1..All registers including the FTM-specific registers (second set of registers) are available for use with no restrictions. 1221 */ 1222 #define FTM_MODE_FTMEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FTMEN_SHIFT)) & FTM_MODE_FTMEN_MASK) 1223 #define FTM_MODE_INIT_MASK (0x2U) 1224 #define FTM_MODE_INIT_SHIFT (1U) 1225 #define FTM_MODE_INIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_INIT_SHIFT)) & FTM_MODE_INIT_MASK) 1226 #define FTM_MODE_WPDIS_MASK (0x4U) 1227 #define FTM_MODE_WPDIS_SHIFT (2U) 1228 /*! WPDIS - Write Protection Disable 1229 * 0b0..Write protection is enabled. 1230 * 0b1..Write protection is disabled. 1231 */ 1232 #define FTM_MODE_WPDIS(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_WPDIS_SHIFT)) & FTM_MODE_WPDIS_MASK) 1233 #define FTM_MODE_PWMSYNC_MASK (0x8U) 1234 #define FTM_MODE_PWMSYNC_SHIFT (3U) 1235 /*! PWMSYNC - PWM Synchronization Mode 1236 * 0b0..No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization. 1237 * 0b1..Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used by OUTMASK and FTM counter synchronization. 1238 */ 1239 #define FTM_MODE_PWMSYNC(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_PWMSYNC_SHIFT)) & FTM_MODE_PWMSYNC_MASK) 1240 #define FTM_MODE_CAPTEST_MASK (0x10U) 1241 #define FTM_MODE_CAPTEST_SHIFT (4U) 1242 /*! CAPTEST - Capture Test Mode Enable 1243 * 0b0..Capture test mode is disabled. 1244 * 0b1..Capture test mode is enabled. 1245 */ 1246 #define FTM_MODE_CAPTEST(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_CAPTEST_SHIFT)) & FTM_MODE_CAPTEST_MASK) 1247 #define FTM_MODE_FAULTM_MASK (0x60U) 1248 #define FTM_MODE_FAULTM_SHIFT (5U) 1249 /*! FAULTM - Fault Control Mode 1250 * 0b00..Fault control is disabled for all channels. 1251 * 0b01..Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing. 1252 * 0b10..Fault control is enabled for all channels, and the selected mode is the manual fault clearing. 1253 * 0b11..Fault control is enabled for all channels, and the selected mode is the automatic fault clearing. 1254 */ 1255 #define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTM_SHIFT)) & FTM_MODE_FAULTM_MASK) 1256 #define FTM_MODE_FAULTIE_MASK (0x80U) 1257 #define FTM_MODE_FAULTIE_SHIFT (7U) 1258 /*! FAULTIE - Fault Interrupt Enable 1259 * 0b0..Fault control interrupt is disabled. 1260 * 0b1..Fault control interrupt is enabled. 1261 */ 1262 #define FTM_MODE_FAULTIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTIE_SHIFT)) & FTM_MODE_FAULTIE_MASK) 1263 /*! @} */ 1264 1265 /*! @name SYNC - Synchronization */ 1266 /*! @{ */ 1267 #define FTM_SYNC_CNTMIN_MASK (0x1U) 1268 #define FTM_SYNC_CNTMIN_SHIFT (0U) 1269 /*! CNTMIN - Minimum Loading Point Enable 1270 * 0b0..The minimum loading point is disabled. 1271 * 0b1..The minimum loading point is enabled. 1272 */ 1273 #define FTM_SYNC_CNTMIN(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMIN_SHIFT)) & FTM_SYNC_CNTMIN_MASK) 1274 #define FTM_SYNC_CNTMAX_MASK (0x2U) 1275 #define FTM_SYNC_CNTMAX_SHIFT (1U) 1276 /*! CNTMAX - Maximum Loading Point Enable 1277 * 0b0..The maximum loading point is disabled. 1278 * 0b1..The maximum loading point is enabled. 1279 */ 1280 #define FTM_SYNC_CNTMAX(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMAX_SHIFT)) & FTM_SYNC_CNTMAX_MASK) 1281 #define FTM_SYNC_REINIT_MASK (0x4U) 1282 #define FTM_SYNC_REINIT_SHIFT (2U) 1283 /*! REINIT - FTM Counter Reinitialization By Synchronization (FTM counter synchronization) 1284 * 0b0..FTM counter continues to count normally. 1285 * 0b1..FTM counter is updated with its initial value when the selected trigger is detected. 1286 */ 1287 #define FTM_SYNC_REINIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_REINIT_SHIFT)) & FTM_SYNC_REINIT_MASK) 1288 #define FTM_SYNC_SYNCHOM_MASK (0x8U) 1289 #define FTM_SYNC_SYNCHOM_SHIFT (3U) 1290 /*! SYNCHOM - Output Mask Synchronization 1291 * 0b0..OUTMASK register is updated with the value of its buffer in all rising edges of the system clock. 1292 * 0b1..OUTMASK register is updated with the value of its buffer only by the PWM synchronization. 1293 */ 1294 #define FTM_SYNC_SYNCHOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SYNCHOM_SHIFT)) & FTM_SYNC_SYNCHOM_MASK) 1295 #define FTM_SYNC_TRIG0_MASK (0x10U) 1296 #define FTM_SYNC_TRIG0_SHIFT (4U) 1297 /*! TRIG0 - PWM Synchronization Hardware Trigger 0 1298 * 0b0..Trigger is disabled. 1299 * 0b1..Trigger is enabled. 1300 */ 1301 #define FTM_SYNC_TRIG0(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG0_SHIFT)) & FTM_SYNC_TRIG0_MASK) 1302 #define FTM_SYNC_TRIG1_MASK (0x20U) 1303 #define FTM_SYNC_TRIG1_SHIFT (5U) 1304 /*! TRIG1 - PWM Synchronization Hardware Trigger 1 1305 * 0b0..Trigger is disabled. 1306 * 0b1..Trigger is enabled. 1307 */ 1308 #define FTM_SYNC_TRIG1(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG1_SHIFT)) & FTM_SYNC_TRIG1_MASK) 1309 #define FTM_SYNC_TRIG2_MASK (0x40U) 1310 #define FTM_SYNC_TRIG2_SHIFT (6U) 1311 /*! TRIG2 - PWM Synchronization Hardware Trigger 2 1312 * 0b0..Trigger is disabled. 1313 * 0b1..Trigger is enabled. 1314 */ 1315 #define FTM_SYNC_TRIG2(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG2_SHIFT)) & FTM_SYNC_TRIG2_MASK) 1316 #define FTM_SYNC_SWSYNC_MASK (0x80U) 1317 #define FTM_SYNC_SWSYNC_SHIFT (7U) 1318 /*! SWSYNC - PWM Synchronization Software Trigger 1319 * 0b0..Software trigger is not selected. 1320 * 0b1..Software trigger is selected. 1321 */ 1322 #define FTM_SYNC_SWSYNC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SWSYNC_SHIFT)) & FTM_SYNC_SWSYNC_MASK) 1323 /*! @} */ 1324 1325 /*! @name OUTINIT - Initial State For Channels Output */ 1326 /*! @{ */ 1327 #define FTM_OUTINIT_CH0OI_MASK (0x1U) 1328 #define FTM_OUTINIT_CH0OI_SHIFT (0U) 1329 /*! CH0OI - Channel 0 Output Initialization Value 1330 * 0b0..The initialization value is 0. 1331 * 0b1..The initialization value is 1. 1332 */ 1333 #define FTM_OUTINIT_CH0OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH0OI_SHIFT)) & FTM_OUTINIT_CH0OI_MASK) 1334 #define FTM_OUTINIT_CH1OI_MASK (0x2U) 1335 #define FTM_OUTINIT_CH1OI_SHIFT (1U) 1336 /*! CH1OI - Channel 1 Output Initialization Value 1337 * 0b0..The initialization value is 0. 1338 * 0b1..The initialization value is 1. 1339 */ 1340 #define FTM_OUTINIT_CH1OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH1OI_SHIFT)) & FTM_OUTINIT_CH1OI_MASK) 1341 #define FTM_OUTINIT_CH2OI_MASK (0x4U) 1342 #define FTM_OUTINIT_CH2OI_SHIFT (2U) 1343 /*! CH2OI - Channel 2 Output Initialization Value 1344 * 0b0..The initialization value is 0. 1345 * 0b1..The initialization value is 1. 1346 */ 1347 #define FTM_OUTINIT_CH2OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH2OI_SHIFT)) & FTM_OUTINIT_CH2OI_MASK) 1348 #define FTM_OUTINIT_CH3OI_MASK (0x8U) 1349 #define FTM_OUTINIT_CH3OI_SHIFT (3U) 1350 /*! CH3OI - Channel 3 Output Initialization Value 1351 * 0b0..The initialization value is 0. 1352 * 0b1..The initialization value is 1. 1353 */ 1354 #define FTM_OUTINIT_CH3OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH3OI_SHIFT)) & FTM_OUTINIT_CH3OI_MASK) 1355 #define FTM_OUTINIT_CH4OI_MASK (0x10U) 1356 #define FTM_OUTINIT_CH4OI_SHIFT (4U) 1357 /*! CH4OI - Channel 4 Output Initialization Value 1358 * 0b0..The initialization value is 0. 1359 * 0b1..The initialization value is 1. 1360 */ 1361 #define FTM_OUTINIT_CH4OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH4OI_SHIFT)) & FTM_OUTINIT_CH4OI_MASK) 1362 #define FTM_OUTINIT_CH5OI_MASK (0x20U) 1363 #define FTM_OUTINIT_CH5OI_SHIFT (5U) 1364 /*! CH5OI - Channel 5 Output Initialization Value 1365 * 0b0..The initialization value is 0. 1366 * 0b1..The initialization value is 1. 1367 */ 1368 #define FTM_OUTINIT_CH5OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH5OI_SHIFT)) & FTM_OUTINIT_CH5OI_MASK) 1369 #define FTM_OUTINIT_CH6OI_MASK (0x40U) 1370 #define FTM_OUTINIT_CH6OI_SHIFT (6U) 1371 /*! CH6OI - Channel 6 Output Initialization Value 1372 * 0b0..The initialization value is 0. 1373 * 0b1..The initialization value is 1. 1374 */ 1375 #define FTM_OUTINIT_CH6OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH6OI_SHIFT)) & FTM_OUTINIT_CH6OI_MASK) 1376 #define FTM_OUTINIT_CH7OI_MASK (0x80U) 1377 #define FTM_OUTINIT_CH7OI_SHIFT (7U) 1378 /*! CH7OI - Channel 7 Output Initialization Value 1379 * 0b0..The initialization value is 0. 1380 * 0b1..The initialization value is 1. 1381 */ 1382 #define FTM_OUTINIT_CH7OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH7OI_SHIFT)) & FTM_OUTINIT_CH7OI_MASK) 1383 /*! @} */ 1384 1385 /*! @name OUTMASK - Output Mask */ 1386 /*! @{ */ 1387 #define FTM_OUTMASK_CH0OM_MASK (0x1U) 1388 #define FTM_OUTMASK_CH0OM_SHIFT (0U) 1389 /*! CH0OM - Channel 0 Output Mask 1390 * 0b0..Channel output is not masked. It continues to operate normally. 1391 * 0b1..Channel output is masked. It is forced to its inactive state. 1392 */ 1393 #define FTM_OUTMASK_CH0OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH0OM_SHIFT)) & FTM_OUTMASK_CH0OM_MASK) 1394 #define FTM_OUTMASK_CH1OM_MASK (0x2U) 1395 #define FTM_OUTMASK_CH1OM_SHIFT (1U) 1396 /*! CH1OM - Channel 1 Output Mask 1397 * 0b0..Channel output is not masked. It continues to operate normally. 1398 * 0b1..Channel output is masked. It is forced to its inactive state. 1399 */ 1400 #define FTM_OUTMASK_CH1OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH1OM_SHIFT)) & FTM_OUTMASK_CH1OM_MASK) 1401 #define FTM_OUTMASK_CH2OM_MASK (0x4U) 1402 #define FTM_OUTMASK_CH2OM_SHIFT (2U) 1403 /*! CH2OM - Channel 2 Output Mask 1404 * 0b0..Channel output is not masked. It continues to operate normally. 1405 * 0b1..Channel output is masked. It is forced to its inactive state. 1406 */ 1407 #define FTM_OUTMASK_CH2OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH2OM_SHIFT)) & FTM_OUTMASK_CH2OM_MASK) 1408 #define FTM_OUTMASK_CH3OM_MASK (0x8U) 1409 #define FTM_OUTMASK_CH3OM_SHIFT (3U) 1410 /*! CH3OM - Channel 3 Output Mask 1411 * 0b0..Channel output is not masked. It continues to operate normally. 1412 * 0b1..Channel output is masked. It is forced to its inactive state. 1413 */ 1414 #define FTM_OUTMASK_CH3OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH3OM_SHIFT)) & FTM_OUTMASK_CH3OM_MASK) 1415 #define FTM_OUTMASK_CH4OM_MASK (0x10U) 1416 #define FTM_OUTMASK_CH4OM_SHIFT (4U) 1417 /*! CH4OM - Channel 4 Output Mask 1418 * 0b0..Channel output is not masked. It continues to operate normally. 1419 * 0b1..Channel output is masked. It is forced to its inactive state. 1420 */ 1421 #define FTM_OUTMASK_CH4OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH4OM_SHIFT)) & FTM_OUTMASK_CH4OM_MASK) 1422 #define FTM_OUTMASK_CH5OM_MASK (0x20U) 1423 #define FTM_OUTMASK_CH5OM_SHIFT (5U) 1424 /*! CH5OM - Channel 5 Output Mask 1425 * 0b0..Channel output is not masked. It continues to operate normally. 1426 * 0b1..Channel output is masked. It is forced to its inactive state. 1427 */ 1428 #define FTM_OUTMASK_CH5OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH5OM_SHIFT)) & FTM_OUTMASK_CH5OM_MASK) 1429 #define FTM_OUTMASK_CH6OM_MASK (0x40U) 1430 #define FTM_OUTMASK_CH6OM_SHIFT (6U) 1431 /*! CH6OM - Channel 6 Output Mask 1432 * 0b0..Channel output is not masked. It continues to operate normally. 1433 * 0b1..Channel output is masked. It is forced to its inactive state. 1434 */ 1435 #define FTM_OUTMASK_CH6OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH6OM_SHIFT)) & FTM_OUTMASK_CH6OM_MASK) 1436 #define FTM_OUTMASK_CH7OM_MASK (0x80U) 1437 #define FTM_OUTMASK_CH7OM_SHIFT (7U) 1438 /*! CH7OM - Channel 7 Output Mask 1439 * 0b0..Channel output is not masked. It continues to operate normally. 1440 * 0b1..Channel output is masked. It is forced to its inactive state. 1441 */ 1442 #define FTM_OUTMASK_CH7OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH7OM_SHIFT)) & FTM_OUTMASK_CH7OM_MASK) 1443 /*! @} */ 1444 1445 /*! @name COMBINE - Function For Linked Channels */ 1446 /*! @{ */ 1447 #define FTM_COMBINE_COMBINE0_MASK (0x1U) 1448 #define FTM_COMBINE_COMBINE0_SHIFT (0U) 1449 /*! COMBINE0 - Combine Channels For n = 0 1450 * 0b0..Channels (n) and (n+1) are independent. 1451 * 0b1..Channels (n) and (n+1) are combined. 1452 */ 1453 #define FTM_COMBINE_COMBINE0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE0_SHIFT)) & FTM_COMBINE_COMBINE0_MASK) 1454 #define FTM_COMBINE_COMP0_MASK (0x2U) 1455 #define FTM_COMBINE_COMP0_SHIFT (1U) 1456 /*! COMP0 - Complement Of Channel (n) For n = 0 1457 * 0b0..The channel (n+1) output is the same as the channel (n) output. 1458 * 0b1..The channel (n+1) output is the complement of the channel (n) output. 1459 */ 1460 #define FTM_COMBINE_COMP0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP0_SHIFT)) & FTM_COMBINE_COMP0_MASK) 1461 #define FTM_COMBINE_DECAPEN0_MASK (0x4U) 1462 #define FTM_COMBINE_DECAPEN0_SHIFT (2U) 1463 /*! DECAPEN0 - Dual Edge Capture Mode Enable For n = 0 1464 * 0b0..The Dual Edge Capture mode in this pair of channels is disabled. 1465 * 0b1..The Dual Edge Capture mode in this pair of channels is enabled. 1466 */ 1467 #define FTM_COMBINE_DECAPEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN0_SHIFT)) & FTM_COMBINE_DECAPEN0_MASK) 1468 #define FTM_COMBINE_DECAP0_MASK (0x8U) 1469 #define FTM_COMBINE_DECAP0_SHIFT (3U) 1470 /*! DECAP0 - Dual Edge Capture Mode Captures For n = 0 1471 * 0b0..The dual edge captures are inactive. 1472 * 0b1..The dual edge captures are active. 1473 */ 1474 #define FTM_COMBINE_DECAP0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP0_SHIFT)) & FTM_COMBINE_DECAP0_MASK) 1475 #define FTM_COMBINE_DTEN0_MASK (0x10U) 1476 #define FTM_COMBINE_DTEN0_SHIFT (4U) 1477 /*! DTEN0 - Deadtime Enable For n = 0 1478 * 0b0..The deadtime insertion in this pair of channels is disabled. 1479 * 0b1..The deadtime insertion in this pair of channels is enabled. 1480 */ 1481 #define FTM_COMBINE_DTEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN0_SHIFT)) & FTM_COMBINE_DTEN0_MASK) 1482 #define FTM_COMBINE_SYNCEN0_MASK (0x20U) 1483 #define FTM_COMBINE_SYNCEN0_SHIFT (5U) 1484 /*! SYNCEN0 - Synchronization Enable For n = 0 1485 * 0b0..The PWM synchronization in this pair of channels is disabled. 1486 * 0b1..The PWM synchronization in this pair of channels is enabled. 1487 */ 1488 #define FTM_COMBINE_SYNCEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN0_SHIFT)) & FTM_COMBINE_SYNCEN0_MASK) 1489 #define FTM_COMBINE_FAULTEN0_MASK (0x40U) 1490 #define FTM_COMBINE_FAULTEN0_SHIFT (6U) 1491 /*! FAULTEN0 - Fault Control Enable For n = 0 1492 * 0b0..The fault control in this pair of channels is disabled. 1493 * 0b1..The fault control in this pair of channels is enabled. 1494 */ 1495 #define FTM_COMBINE_FAULTEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN0_SHIFT)) & FTM_COMBINE_FAULTEN0_MASK) 1496 #define FTM_COMBINE_COMBINE1_MASK (0x100U) 1497 #define FTM_COMBINE_COMBINE1_SHIFT (8U) 1498 /*! COMBINE1 - Combine Channels For n = 2 1499 * 0b0..Channels (n) and (n+1) are independent. 1500 * 0b1..Channels (n) and (n+1) are combined. 1501 */ 1502 #define FTM_COMBINE_COMBINE1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE1_SHIFT)) & FTM_COMBINE_COMBINE1_MASK) 1503 #define FTM_COMBINE_COMP1_MASK (0x200U) 1504 #define FTM_COMBINE_COMP1_SHIFT (9U) 1505 /*! COMP1 - Complement Of Channel (n) For n = 2 1506 * 0b0..The channel (n+1) output is the same as the channel (n) output. 1507 * 0b1..The channel (n+1) output is the complement of the channel (n) output. 1508 */ 1509 #define FTM_COMBINE_COMP1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP1_SHIFT)) & FTM_COMBINE_COMP1_MASK) 1510 #define FTM_COMBINE_DECAPEN1_MASK (0x400U) 1511 #define FTM_COMBINE_DECAPEN1_SHIFT (10U) 1512 /*! DECAPEN1 - Dual Edge Capture Mode Enable For n = 2 1513 * 0b0..The Dual Edge Capture mode in this pair of channels is disabled. 1514 * 0b1..The Dual Edge Capture mode in this pair of channels is enabled. 1515 */ 1516 #define FTM_COMBINE_DECAPEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN1_SHIFT)) & FTM_COMBINE_DECAPEN1_MASK) 1517 #define FTM_COMBINE_DECAP1_MASK (0x800U) 1518 #define FTM_COMBINE_DECAP1_SHIFT (11U) 1519 /*! DECAP1 - Dual Edge Capture Mode Captures For n = 2 1520 * 0b0..The dual edge captures are inactive. 1521 * 0b1..The dual edge captures are active. 1522 */ 1523 #define FTM_COMBINE_DECAP1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP1_SHIFT)) & FTM_COMBINE_DECAP1_MASK) 1524 #define FTM_COMBINE_DTEN1_MASK (0x1000U) 1525 #define FTM_COMBINE_DTEN1_SHIFT (12U) 1526 /*! DTEN1 - Deadtime Enable For n = 2 1527 * 0b0..The deadtime insertion in this pair of channels is disabled. 1528 * 0b1..The deadtime insertion in this pair of channels is enabled. 1529 */ 1530 #define FTM_COMBINE_DTEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN1_SHIFT)) & FTM_COMBINE_DTEN1_MASK) 1531 #define FTM_COMBINE_SYNCEN1_MASK (0x2000U) 1532 #define FTM_COMBINE_SYNCEN1_SHIFT (13U) 1533 /*! SYNCEN1 - Synchronization Enable For n = 2 1534 * 0b0..The PWM synchronization in this pair of channels is disabled. 1535 * 0b1..The PWM synchronization in this pair of channels is enabled. 1536 */ 1537 #define FTM_COMBINE_SYNCEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN1_SHIFT)) & FTM_COMBINE_SYNCEN1_MASK) 1538 #define FTM_COMBINE_FAULTEN1_MASK (0x4000U) 1539 #define FTM_COMBINE_FAULTEN1_SHIFT (14U) 1540 /*! FAULTEN1 - Fault Control Enable For n = 2 1541 * 0b0..The fault control in this pair of channels is disabled. 1542 * 0b1..The fault control in this pair of channels is enabled. 1543 */ 1544 #define FTM_COMBINE_FAULTEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN1_SHIFT)) & FTM_COMBINE_FAULTEN1_MASK) 1545 #define FTM_COMBINE_COMBINE2_MASK (0x10000U) 1546 #define FTM_COMBINE_COMBINE2_SHIFT (16U) 1547 /*! COMBINE2 - Combine Channels For n = 4 1548 * 0b0..Channels (n) and (n+1) are independent. 1549 * 0b1..Channels (n) and (n+1) are combined. 1550 */ 1551 #define FTM_COMBINE_COMBINE2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE2_SHIFT)) & FTM_COMBINE_COMBINE2_MASK) 1552 #define FTM_COMBINE_COMP2_MASK (0x20000U) 1553 #define FTM_COMBINE_COMP2_SHIFT (17U) 1554 /*! COMP2 - Complement Of Channel (n) For n = 4 1555 * 0b0..The channel (n+1) output is the same as the channel (n) output. 1556 * 0b1..The channel (n+1) output is the complement of the channel (n) output. 1557 */ 1558 #define FTM_COMBINE_COMP2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP2_SHIFT)) & FTM_COMBINE_COMP2_MASK) 1559 #define FTM_COMBINE_DECAPEN2_MASK (0x40000U) 1560 #define FTM_COMBINE_DECAPEN2_SHIFT (18U) 1561 /*! DECAPEN2 - Dual Edge Capture Mode Enable For n = 4 1562 * 0b0..The Dual Edge Capture mode in this pair of channels is disabled. 1563 * 0b1..The Dual Edge Capture mode in this pair of channels is enabled. 1564 */ 1565 #define FTM_COMBINE_DECAPEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN2_SHIFT)) & FTM_COMBINE_DECAPEN2_MASK) 1566 #define FTM_COMBINE_DECAP2_MASK (0x80000U) 1567 #define FTM_COMBINE_DECAP2_SHIFT (19U) 1568 /*! DECAP2 - Dual Edge Capture Mode Captures For n = 4 1569 * 0b0..The dual edge captures are inactive. 1570 * 0b1..The dual edge captures are active. 1571 */ 1572 #define FTM_COMBINE_DECAP2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP2_SHIFT)) & FTM_COMBINE_DECAP2_MASK) 1573 #define FTM_COMBINE_DTEN2_MASK (0x100000U) 1574 #define FTM_COMBINE_DTEN2_SHIFT (20U) 1575 /*! DTEN2 - Deadtime Enable For n = 4 1576 * 0b0..The deadtime insertion in this pair of channels is disabled. 1577 * 0b1..The deadtime insertion in this pair of channels is enabled. 1578 */ 1579 #define FTM_COMBINE_DTEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN2_SHIFT)) & FTM_COMBINE_DTEN2_MASK) 1580 #define FTM_COMBINE_SYNCEN2_MASK (0x200000U) 1581 #define FTM_COMBINE_SYNCEN2_SHIFT (21U) 1582 /*! SYNCEN2 - Synchronization Enable For n = 4 1583 * 0b0..The PWM synchronization in this pair of channels is disabled. 1584 * 0b1..The PWM synchronization in this pair of channels is enabled. 1585 */ 1586 #define FTM_COMBINE_SYNCEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN2_SHIFT)) & FTM_COMBINE_SYNCEN2_MASK) 1587 #define FTM_COMBINE_FAULTEN2_MASK (0x400000U) 1588 #define FTM_COMBINE_FAULTEN2_SHIFT (22U) 1589 /*! FAULTEN2 - Fault Control Enable For n = 4 1590 * 0b0..The fault control in this pair of channels is disabled. 1591 * 0b1..The fault control in this pair of channels is enabled. 1592 */ 1593 #define FTM_COMBINE_FAULTEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN2_SHIFT)) & FTM_COMBINE_FAULTEN2_MASK) 1594 #define FTM_COMBINE_COMBINE3_MASK (0x1000000U) 1595 #define FTM_COMBINE_COMBINE3_SHIFT (24U) 1596 /*! COMBINE3 - Combine Channels For n = 6 1597 * 0b0..Channels (n) and (n+1) are independent. 1598 * 0b1..Channels (n) and (n+1) are combined. 1599 */ 1600 #define FTM_COMBINE_COMBINE3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE3_SHIFT)) & FTM_COMBINE_COMBINE3_MASK) 1601 #define FTM_COMBINE_COMP3_MASK (0x2000000U) 1602 #define FTM_COMBINE_COMP3_SHIFT (25U) 1603 /*! COMP3 - Complement Of Channel (n) for n = 6 1604 * 0b0..The channel (n+1) output is the same as the channel (n) output. 1605 * 0b1..The channel (n+1) output is the complement of the channel (n) output. 1606 */ 1607 #define FTM_COMBINE_COMP3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP3_SHIFT)) & FTM_COMBINE_COMP3_MASK) 1608 #define FTM_COMBINE_DECAPEN3_MASK (0x4000000U) 1609 #define FTM_COMBINE_DECAPEN3_SHIFT (26U) 1610 /*! DECAPEN3 - Dual Edge Capture Mode Enable For n = 6 1611 * 0b0..The Dual Edge Capture mode in this pair of channels is disabled. 1612 * 0b1..The Dual Edge Capture mode in this pair of channels is enabled. 1613 */ 1614 #define FTM_COMBINE_DECAPEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN3_SHIFT)) & FTM_COMBINE_DECAPEN3_MASK) 1615 #define FTM_COMBINE_DECAP3_MASK (0x8000000U) 1616 #define FTM_COMBINE_DECAP3_SHIFT (27U) 1617 /*! DECAP3 - Dual Edge Capture Mode Captures For n = 6 1618 * 0b0..The dual edge captures are inactive. 1619 * 0b1..The dual edge captures are active. 1620 */ 1621 #define FTM_COMBINE_DECAP3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP3_SHIFT)) & FTM_COMBINE_DECAP3_MASK) 1622 #define FTM_COMBINE_DTEN3_MASK (0x10000000U) 1623 #define FTM_COMBINE_DTEN3_SHIFT (28U) 1624 /*! DTEN3 - Deadtime Enable For n = 6 1625 * 0b0..The deadtime insertion in this pair of channels is disabled. 1626 * 0b1..The deadtime insertion in this pair of channels is enabled. 1627 */ 1628 #define FTM_COMBINE_DTEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN3_SHIFT)) & FTM_COMBINE_DTEN3_MASK) 1629 #define FTM_COMBINE_SYNCEN3_MASK (0x20000000U) 1630 #define FTM_COMBINE_SYNCEN3_SHIFT (29U) 1631 /*! SYNCEN3 - Synchronization Enable For n = 6 1632 * 0b0..The PWM synchronization in this pair of channels is disabled. 1633 * 0b1..The PWM synchronization in this pair of channels is enabled. 1634 */ 1635 #define FTM_COMBINE_SYNCEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN3_SHIFT)) & FTM_COMBINE_SYNCEN3_MASK) 1636 #define FTM_COMBINE_FAULTEN3_MASK (0x40000000U) 1637 #define FTM_COMBINE_FAULTEN3_SHIFT (30U) 1638 /*! FAULTEN3 - Fault Control Enable For n = 6 1639 * 0b0..The fault control in this pair of channels is disabled. 1640 * 0b1..The fault control in this pair of channels is enabled. 1641 */ 1642 #define FTM_COMBINE_FAULTEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN3_SHIFT)) & FTM_COMBINE_FAULTEN3_MASK) 1643 /*! @} */ 1644 1645 /*! @name DEADTIME - Deadtime Insertion Control */ 1646 /*! @{ */ 1647 #define FTM_DEADTIME_DTVAL_MASK (0x3FU) 1648 #define FTM_DEADTIME_DTVAL_SHIFT (0U) 1649 #define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTVAL_SHIFT)) & FTM_DEADTIME_DTVAL_MASK) 1650 #define FTM_DEADTIME_DTPS_MASK (0xC0U) 1651 #define FTM_DEADTIME_DTPS_SHIFT (6U) 1652 /*! DTPS - Deadtime Prescaler Value 1653 * 0b0x..Divide the system clock by 1. 1654 * 0b10..Divide the system clock by 4. 1655 * 0b11..Divide the system clock by 16. 1656 */ 1657 #define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTPS_SHIFT)) & FTM_DEADTIME_DTPS_MASK) 1658 /*! @} */ 1659 1660 /*! @name EXTTRIG - FTM External Trigger */ 1661 /*! @{ */ 1662 #define FTM_EXTTRIG_CH2TRIG_MASK (0x1U) 1663 #define FTM_EXTTRIG_CH2TRIG_SHIFT (0U) 1664 /*! CH2TRIG - Channel 2 Trigger Enable 1665 * 0b0..The generation of the channel trigger is disabled. 1666 * 0b1..The generation of the channel trigger is enabled. 1667 */ 1668 #define FTM_EXTTRIG_CH2TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH2TRIG_SHIFT)) & FTM_EXTTRIG_CH2TRIG_MASK) 1669 #define FTM_EXTTRIG_CH3TRIG_MASK (0x2U) 1670 #define FTM_EXTTRIG_CH3TRIG_SHIFT (1U) 1671 /*! CH3TRIG - Channel 3 Trigger Enable 1672 * 0b0..The generation of the channel trigger is disabled. 1673 * 0b1..The generation of the channel trigger is enabled. 1674 */ 1675 #define FTM_EXTTRIG_CH3TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH3TRIG_SHIFT)) & FTM_EXTTRIG_CH3TRIG_MASK) 1676 #define FTM_EXTTRIG_CH4TRIG_MASK (0x4U) 1677 #define FTM_EXTTRIG_CH4TRIG_SHIFT (2U) 1678 /*! CH4TRIG - Channel 4 Trigger Enable 1679 * 0b0..The generation of the channel trigger is disabled. 1680 * 0b1..The generation of the channel trigger is enabled. 1681 */ 1682 #define FTM_EXTTRIG_CH4TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH4TRIG_SHIFT)) & FTM_EXTTRIG_CH4TRIG_MASK) 1683 #define FTM_EXTTRIG_CH5TRIG_MASK (0x8U) 1684 #define FTM_EXTTRIG_CH5TRIG_SHIFT (3U) 1685 /*! CH5TRIG - Channel 5 Trigger Enable 1686 * 0b0..The generation of the channel trigger is disabled. 1687 * 0b1..The generation of the channel trigger is enabled. 1688 */ 1689 #define FTM_EXTTRIG_CH5TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH5TRIG_SHIFT)) & FTM_EXTTRIG_CH5TRIG_MASK) 1690 #define FTM_EXTTRIG_CH0TRIG_MASK (0x10U) 1691 #define FTM_EXTTRIG_CH0TRIG_SHIFT (4U) 1692 /*! CH0TRIG - Channel 0 Trigger Enable 1693 * 0b0..The generation of the channel trigger is disabled. 1694 * 0b1..The generation of the channel trigger is enabled. 1695 */ 1696 #define FTM_EXTTRIG_CH0TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH0TRIG_SHIFT)) & FTM_EXTTRIG_CH0TRIG_MASK) 1697 #define FTM_EXTTRIG_CH1TRIG_MASK (0x20U) 1698 #define FTM_EXTTRIG_CH1TRIG_SHIFT (5U) 1699 /*! CH1TRIG - Channel 1 Trigger Enable 1700 * 0b0..The generation of the channel trigger is disabled. 1701 * 0b1..The generation of the channel trigger is enabled. 1702 */ 1703 #define FTM_EXTTRIG_CH1TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH1TRIG_SHIFT)) & FTM_EXTTRIG_CH1TRIG_MASK) 1704 #define FTM_EXTTRIG_INITTRIGEN_MASK (0x40U) 1705 #define FTM_EXTTRIG_INITTRIGEN_SHIFT (6U) 1706 /*! INITTRIGEN - Initialization Trigger Enable 1707 * 0b0..The generation of initialization trigger is disabled. 1708 * 0b1..The generation of initialization trigger is enabled. 1709 */ 1710 #define FTM_EXTTRIG_INITTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_INITTRIGEN_SHIFT)) & FTM_EXTTRIG_INITTRIGEN_MASK) 1711 #define FTM_EXTTRIG_TRIGF_MASK (0x80U) 1712 #define FTM_EXTTRIG_TRIGF_SHIFT (7U) 1713 /*! TRIGF - Channel Trigger Flag 1714 * 0b0..No channel trigger was generated. 1715 * 0b1..A channel trigger was generated. 1716 */ 1717 #define FTM_EXTTRIG_TRIGF(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_TRIGF_SHIFT)) & FTM_EXTTRIG_TRIGF_MASK) 1718 /*! @} */ 1719 1720 /*! @name POL - Channels Polarity */ 1721 /*! @{ */ 1722 #define FTM_POL_POL0_MASK (0x1U) 1723 #define FTM_POL_POL0_SHIFT (0U) 1724 /*! POL0 - Channel 0 Polarity 1725 * 0b0..The channel polarity is active high. 1726 * 0b1..The channel polarity is active low. 1727 */ 1728 #define FTM_POL_POL0(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL0_SHIFT)) & FTM_POL_POL0_MASK) 1729 #define FTM_POL_POL1_MASK (0x2U) 1730 #define FTM_POL_POL1_SHIFT (1U) 1731 /*! POL1 - Channel 1 Polarity 1732 * 0b0..The channel polarity is active high. 1733 * 0b1..The channel polarity is active low. 1734 */ 1735 #define FTM_POL_POL1(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL1_SHIFT)) & FTM_POL_POL1_MASK) 1736 #define FTM_POL_POL2_MASK (0x4U) 1737 #define FTM_POL_POL2_SHIFT (2U) 1738 /*! POL2 - Channel 2 Polarity 1739 * 0b0..The channel polarity is active high. 1740 * 0b1..The channel polarity is active low. 1741 */ 1742 #define FTM_POL_POL2(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL2_SHIFT)) & FTM_POL_POL2_MASK) 1743 #define FTM_POL_POL3_MASK (0x8U) 1744 #define FTM_POL_POL3_SHIFT (3U) 1745 /*! POL3 - Channel 3 Polarity 1746 * 0b0..The channel polarity is active high. 1747 * 0b1..The channel polarity is active low. 1748 */ 1749 #define FTM_POL_POL3(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL3_SHIFT)) & FTM_POL_POL3_MASK) 1750 #define FTM_POL_POL4_MASK (0x10U) 1751 #define FTM_POL_POL4_SHIFT (4U) 1752 /*! POL4 - Channel 4 Polarity 1753 * 0b0..The channel polarity is active high. 1754 * 0b1..The channel polarity is active low. 1755 */ 1756 #define FTM_POL_POL4(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL4_SHIFT)) & FTM_POL_POL4_MASK) 1757 #define FTM_POL_POL5_MASK (0x20U) 1758 #define FTM_POL_POL5_SHIFT (5U) 1759 /*! POL5 - Channel 5 Polarity 1760 * 0b0..The channel polarity is active high. 1761 * 0b1..The channel polarity is active low. 1762 */ 1763 #define FTM_POL_POL5(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL5_SHIFT)) & FTM_POL_POL5_MASK) 1764 #define FTM_POL_POL6_MASK (0x40U) 1765 #define FTM_POL_POL6_SHIFT (6U) 1766 /*! POL6 - Channel 6 Polarity 1767 * 0b0..The channel polarity is active high. 1768 * 0b1..The channel polarity is active low. 1769 */ 1770 #define FTM_POL_POL6(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL6_SHIFT)) & FTM_POL_POL6_MASK) 1771 #define FTM_POL_POL7_MASK (0x80U) 1772 #define FTM_POL_POL7_SHIFT (7U) 1773 /*! POL7 - Channel 7 Polarity 1774 * 0b0..The channel polarity is active high. 1775 * 0b1..The channel polarity is active low. 1776 */ 1777 #define FTM_POL_POL7(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL7_SHIFT)) & FTM_POL_POL7_MASK) 1778 /*! @} */ 1779 1780 /*! @name FMS - Fault Mode Status */ 1781 /*! @{ */ 1782 #define FTM_FMS_FAULTF0_MASK (0x1U) 1783 #define FTM_FMS_FAULTF0_SHIFT (0U) 1784 /*! FAULTF0 - Fault Detection Flag 0 1785 * 0b0..No fault condition was detected at the fault input. 1786 * 0b1..A fault condition was detected at the fault input. 1787 */ 1788 #define FTM_FMS_FAULTF0(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF0_SHIFT)) & FTM_FMS_FAULTF0_MASK) 1789 #define FTM_FMS_FAULTF1_MASK (0x2U) 1790 #define FTM_FMS_FAULTF1_SHIFT (1U) 1791 /*! FAULTF1 - Fault Detection Flag 1 1792 * 0b0..No fault condition was detected at the fault input. 1793 * 0b1..A fault condition was detected at the fault input. 1794 */ 1795 #define FTM_FMS_FAULTF1(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF1_SHIFT)) & FTM_FMS_FAULTF1_MASK) 1796 #define FTM_FMS_FAULTF2_MASK (0x4U) 1797 #define FTM_FMS_FAULTF2_SHIFT (2U) 1798 /*! FAULTF2 - Fault Detection Flag 2 1799 * 0b0..No fault condition was detected at the fault input. 1800 * 0b1..A fault condition was detected at the fault input. 1801 */ 1802 #define FTM_FMS_FAULTF2(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF2_SHIFT)) & FTM_FMS_FAULTF2_MASK) 1803 #define FTM_FMS_FAULTF3_MASK (0x8U) 1804 #define FTM_FMS_FAULTF3_SHIFT (3U) 1805 /*! FAULTF3 - Fault Detection Flag 3 1806 * 0b0..No fault condition was detected at the fault input. 1807 * 0b1..A fault condition was detected at the fault input. 1808 */ 1809 #define FTM_FMS_FAULTF3(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF3_SHIFT)) & FTM_FMS_FAULTF3_MASK) 1810 #define FTM_FMS_FAULTIN_MASK (0x20U) 1811 #define FTM_FMS_FAULTIN_SHIFT (5U) 1812 /*! FAULTIN - Fault Inputs 1813 * 0b0..The logic OR of the enabled fault inputs is 0. 1814 * 0b1..The logic OR of the enabled fault inputs is 1. 1815 */ 1816 #define FTM_FMS_FAULTIN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTIN_SHIFT)) & FTM_FMS_FAULTIN_MASK) 1817 #define FTM_FMS_WPEN_MASK (0x40U) 1818 #define FTM_FMS_WPEN_SHIFT (6U) 1819 /*! WPEN - Write Protection Enable 1820 * 0b0..Write protection is disabled. Write protected bits can be written. 1821 * 0b1..Write protection is enabled. Write protected bits cannot be written. 1822 */ 1823 #define FTM_FMS_WPEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_WPEN_SHIFT)) & FTM_FMS_WPEN_MASK) 1824 #define FTM_FMS_FAULTF_MASK (0x80U) 1825 #define FTM_FMS_FAULTF_SHIFT (7U) 1826 /*! FAULTF - Fault Detection Flag 1827 * 0b0..No fault condition was detected. 1828 * 0b1..A fault condition was detected. 1829 */ 1830 #define FTM_FMS_FAULTF(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF_SHIFT)) & FTM_FMS_FAULTF_MASK) 1831 /*! @} */ 1832 1833 /*! @name FILTER - Input Capture Filter Control */ 1834 /*! @{ */ 1835 #define FTM_FILTER_CH0FVAL_MASK (0xFU) 1836 #define FTM_FILTER_CH0FVAL_SHIFT (0U) 1837 #define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH0FVAL_SHIFT)) & FTM_FILTER_CH0FVAL_MASK) 1838 #define FTM_FILTER_CH1FVAL_MASK (0xF0U) 1839 #define FTM_FILTER_CH1FVAL_SHIFT (4U) 1840 #define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH1FVAL_SHIFT)) & FTM_FILTER_CH1FVAL_MASK) 1841 #define FTM_FILTER_CH2FVAL_MASK (0xF00U) 1842 #define FTM_FILTER_CH2FVAL_SHIFT (8U) 1843 #define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH2FVAL_SHIFT)) & FTM_FILTER_CH2FVAL_MASK) 1844 #define FTM_FILTER_CH3FVAL_MASK (0xF000U) 1845 #define FTM_FILTER_CH3FVAL_SHIFT (12U) 1846 #define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH3FVAL_SHIFT)) & FTM_FILTER_CH3FVAL_MASK) 1847 /*! @} */ 1848 1849 /*! @name FLTCTRL - Fault Control */ 1850 /*! @{ */ 1851 #define FTM_FLTCTRL_FAULT0EN_MASK (0x1U) 1852 #define FTM_FLTCTRL_FAULT0EN_SHIFT (0U) 1853 /*! FAULT0EN - Fault Input 0 Enable 1854 * 0b0..Fault input is disabled. 1855 * 0b1..Fault input is enabled. 1856 */ 1857 #define FTM_FLTCTRL_FAULT0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT0EN_SHIFT)) & FTM_FLTCTRL_FAULT0EN_MASK) 1858 #define FTM_FLTCTRL_FAULT1EN_MASK (0x2U) 1859 #define FTM_FLTCTRL_FAULT1EN_SHIFT (1U) 1860 /*! FAULT1EN - Fault Input 1 Enable 1861 * 0b0..Fault input is disabled. 1862 * 0b1..Fault input is enabled. 1863 */ 1864 #define FTM_FLTCTRL_FAULT1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT1EN_SHIFT)) & FTM_FLTCTRL_FAULT1EN_MASK) 1865 #define FTM_FLTCTRL_FAULT2EN_MASK (0x4U) 1866 #define FTM_FLTCTRL_FAULT2EN_SHIFT (2U) 1867 /*! FAULT2EN - Fault Input 2 Enable 1868 * 0b0..Fault input is disabled. 1869 * 0b1..Fault input is enabled. 1870 */ 1871 #define FTM_FLTCTRL_FAULT2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT2EN_SHIFT)) & FTM_FLTCTRL_FAULT2EN_MASK) 1872 #define FTM_FLTCTRL_FAULT3EN_MASK (0x8U) 1873 #define FTM_FLTCTRL_FAULT3EN_SHIFT (3U) 1874 /*! FAULT3EN - Fault Input 3 Enable 1875 * 0b0..Fault input is disabled. 1876 * 0b1..Fault input is enabled. 1877 */ 1878 #define FTM_FLTCTRL_FAULT3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT3EN_SHIFT)) & FTM_FLTCTRL_FAULT3EN_MASK) 1879 #define FTM_FLTCTRL_FFLTR0EN_MASK (0x10U) 1880 #define FTM_FLTCTRL_FFLTR0EN_SHIFT (4U) 1881 /*! FFLTR0EN - Fault Input 0 Filter Enable 1882 * 0b0..Fault input filter is disabled. 1883 * 0b1..Fault input filter is enabled. 1884 */ 1885 #define FTM_FLTCTRL_FFLTR0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR0EN_SHIFT)) & FTM_FLTCTRL_FFLTR0EN_MASK) 1886 #define FTM_FLTCTRL_FFLTR1EN_MASK (0x20U) 1887 #define FTM_FLTCTRL_FFLTR1EN_SHIFT (5U) 1888 /*! FFLTR1EN - Fault Input 1 Filter Enable 1889 * 0b0..Fault input filter is disabled. 1890 * 0b1..Fault input filter is enabled. 1891 */ 1892 #define FTM_FLTCTRL_FFLTR1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR1EN_SHIFT)) & FTM_FLTCTRL_FFLTR1EN_MASK) 1893 #define FTM_FLTCTRL_FFLTR2EN_MASK (0x40U) 1894 #define FTM_FLTCTRL_FFLTR2EN_SHIFT (6U) 1895 /*! FFLTR2EN - Fault Input 2 Filter Enable 1896 * 0b0..Fault input filter is disabled. 1897 * 0b1..Fault input filter is enabled. 1898 */ 1899 #define FTM_FLTCTRL_FFLTR2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR2EN_SHIFT)) & FTM_FLTCTRL_FFLTR2EN_MASK) 1900 #define FTM_FLTCTRL_FFLTR3EN_MASK (0x80U) 1901 #define FTM_FLTCTRL_FFLTR3EN_SHIFT (7U) 1902 /*! FFLTR3EN - Fault Input 3 Filter Enable 1903 * 0b0..Fault input filter is disabled. 1904 * 0b1..Fault input filter is enabled. 1905 */ 1906 #define FTM_FLTCTRL_FFLTR3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR3EN_SHIFT)) & FTM_FLTCTRL_FFLTR3EN_MASK) 1907 #define FTM_FLTCTRL_FFVAL_MASK (0xF00U) 1908 #define FTM_FLTCTRL_FFVAL_SHIFT (8U) 1909 #define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFVAL_SHIFT)) & FTM_FLTCTRL_FFVAL_MASK) 1910 /*! @} */ 1911 1912 /*! @name CONF - Configuration */ 1913 /*! @{ */ 1914 #define FTM_CONF_NUMTOF_MASK (0x1FU) 1915 #define FTM_CONF_NUMTOF_SHIFT (0U) 1916 #define FTM_CONF_NUMTOF(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_NUMTOF_SHIFT)) & FTM_CONF_NUMTOF_MASK) 1917 #define FTM_CONF_BDMMODE_MASK (0xC0U) 1918 #define FTM_CONF_BDMMODE_SHIFT (6U) 1919 #define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_BDMMODE_SHIFT)) & FTM_CONF_BDMMODE_MASK) 1920 #define FTM_CONF_GTBEEN_MASK (0x200U) 1921 #define FTM_CONF_GTBEEN_SHIFT (9U) 1922 /*! GTBEEN - Global Time Base Enable 1923 * 0b0..Use of an external global time base is disabled. 1924 * 0b1..Use of an external global time base is enabled. 1925 */ 1926 #define FTM_CONF_GTBEEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEEN_SHIFT)) & FTM_CONF_GTBEEN_MASK) 1927 #define FTM_CONF_GTBEOUT_MASK (0x400U) 1928 #define FTM_CONF_GTBEOUT_SHIFT (10U) 1929 /*! GTBEOUT - Global Time Base Output 1930 * 0b0..A global time base signal generation is disabled. 1931 * 0b1..A global time base signal generation is enabled. 1932 */ 1933 #define FTM_CONF_GTBEOUT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEOUT_SHIFT)) & FTM_CONF_GTBEOUT_MASK) 1934 /*! @} */ 1935 1936 /*! @name FLTPOL - FTM Fault Input Polarity */ 1937 /*! @{ */ 1938 #define FTM_FLTPOL_FLT0POL_MASK (0x1U) 1939 #define FTM_FLTPOL_FLT0POL_SHIFT (0U) 1940 /*! FLT0POL - Fault Input 0 Polarity 1941 * 0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault. 1942 * 0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault. 1943 */ 1944 #define FTM_FLTPOL_FLT0POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT0POL_SHIFT)) & FTM_FLTPOL_FLT0POL_MASK) 1945 #define FTM_FLTPOL_FLT1POL_MASK (0x2U) 1946 #define FTM_FLTPOL_FLT1POL_SHIFT (1U) 1947 /*! FLT1POL - Fault Input 1 Polarity 1948 * 0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault. 1949 * 0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault. 1950 */ 1951 #define FTM_FLTPOL_FLT1POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT1POL_SHIFT)) & FTM_FLTPOL_FLT1POL_MASK) 1952 #define FTM_FLTPOL_FLT2POL_MASK (0x4U) 1953 #define FTM_FLTPOL_FLT2POL_SHIFT (2U) 1954 /*! FLT2POL - Fault Input 2 Polarity 1955 * 0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault. 1956 * 0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault. 1957 */ 1958 #define FTM_FLTPOL_FLT2POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT2POL_SHIFT)) & FTM_FLTPOL_FLT2POL_MASK) 1959 #define FTM_FLTPOL_FLT3POL_MASK (0x8U) 1960 #define FTM_FLTPOL_FLT3POL_SHIFT (3U) 1961 /*! FLT3POL - Fault Input 3 Polarity 1962 * 0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault. 1963 * 0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault. 1964 */ 1965 #define FTM_FLTPOL_FLT3POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT3POL_SHIFT)) & FTM_FLTPOL_FLT3POL_MASK) 1966 /*! @} */ 1967 1968 /*! @name SYNCONF - Synchronization Configuration */ 1969 /*! @{ */ 1970 #define FTM_SYNCONF_HWTRIGMODE_MASK (0x1U) 1971 #define FTM_SYNCONF_HWTRIGMODE_SHIFT (0U) 1972 /*! HWTRIGMODE - Hardware Trigger Mode 1973 * 0b0..FTM clears the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2. 1974 * 0b1..FTM does not clear the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2. 1975 */ 1976 #define FTM_SYNCONF_HWTRIGMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWTRIGMODE_SHIFT)) & FTM_SYNCONF_HWTRIGMODE_MASK) 1977 #define FTM_SYNCONF_CNTINC_MASK (0x4U) 1978 #define FTM_SYNCONF_CNTINC_SHIFT (2U) 1979 /*! CNTINC - CNTIN Register Synchronization 1980 * 0b0..CNTIN register is updated with its buffer value at all rising edges of system clock. 1981 * 0b1..CNTIN register is updated with its buffer value by the PWM synchronization. 1982 */ 1983 #define FTM_SYNCONF_CNTINC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_CNTINC_SHIFT)) & FTM_SYNCONF_CNTINC_MASK) 1984 #define FTM_SYNCONF_INVC_MASK (0x10U) 1985 #define FTM_SYNCONF_INVC_SHIFT (4U) 1986 /*! INVC - INVCTRL Register Synchronization 1987 * 0b0..INVCTRL register is updated with its buffer value at all rising edges of system clock. 1988 * 0b1..INVCTRL register is updated with its buffer value by the PWM synchronization. 1989 */ 1990 #define FTM_SYNCONF_INVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_INVC_SHIFT)) & FTM_SYNCONF_INVC_MASK) 1991 #define FTM_SYNCONF_SWOC_MASK (0x20U) 1992 #define FTM_SYNCONF_SWOC_SHIFT (5U) 1993 /*! SWOC - SWOCTRL Register Synchronization 1994 * 0b0..SWOCTRL register is updated with its buffer value at all rising edges of system clock. 1995 * 0b1..SWOCTRL register is updated with its buffer value by the PWM synchronization. 1996 */ 1997 #define FTM_SYNCONF_SWOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOC_SHIFT)) & FTM_SYNCONF_SWOC_MASK) 1998 #define FTM_SYNCONF_SYNCMODE_MASK (0x80U) 1999 #define FTM_SYNCONF_SYNCMODE_SHIFT (7U) 2000 /*! SYNCMODE - Synchronization Mode 2001 * 0b0..Legacy PWM synchronization is selected. 2002 * 0b1..Enhanced PWM synchronization is selected. 2003 */ 2004 #define FTM_SYNCONF_SYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SYNCMODE_SHIFT)) & FTM_SYNCONF_SYNCMODE_MASK) 2005 #define FTM_SYNCONF_SWRSTCNT_MASK (0x100U) 2006 #define FTM_SYNCONF_SWRSTCNT_SHIFT (8U) 2007 /*! SWRSTCNT 2008 * 0b0..The software trigger does not activate the FTM counter synchronization. 2009 * 0b1..The software trigger activates the FTM counter synchronization. 2010 */ 2011 #define FTM_SYNCONF_SWRSTCNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWRSTCNT_SHIFT)) & FTM_SYNCONF_SWRSTCNT_MASK) 2012 #define FTM_SYNCONF_SWWRBUF_MASK (0x200U) 2013 #define FTM_SYNCONF_SWWRBUF_SHIFT (9U) 2014 /*! SWWRBUF 2015 * 0b0..The software trigger does not activate MOD, CNTIN, and CV registers synchronization. 2016 * 0b1..The software trigger activates MOD, CNTIN, and CV registers synchronization. 2017 */ 2018 #define FTM_SYNCONF_SWWRBUF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWWRBUF_SHIFT)) & FTM_SYNCONF_SWWRBUF_MASK) 2019 #define FTM_SYNCONF_SWOM_MASK (0x400U) 2020 #define FTM_SYNCONF_SWOM_SHIFT (10U) 2021 /*! SWOM 2022 * 0b0..The software trigger does not activate the OUTMASK register synchronization. 2023 * 0b1..The software trigger activates the OUTMASK register synchronization. 2024 */ 2025 #define FTM_SYNCONF_SWOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOM_SHIFT)) & FTM_SYNCONF_SWOM_MASK) 2026 #define FTM_SYNCONF_SWINVC_MASK (0x800U) 2027 #define FTM_SYNCONF_SWINVC_SHIFT (11U) 2028 /*! SWINVC 2029 * 0b0..The software trigger does not activate the INVCTRL register synchronization. 2030 * 0b1..The software trigger activates the INVCTRL register synchronization. 2031 */ 2032 #define FTM_SYNCONF_SWINVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWINVC_SHIFT)) & FTM_SYNCONF_SWINVC_MASK) 2033 #define FTM_SYNCONF_SWSOC_MASK (0x1000U) 2034 #define FTM_SYNCONF_SWSOC_SHIFT (12U) 2035 /*! SWSOC 2036 * 0b0..The software trigger does not activate the SWOCTRL register synchronization. 2037 * 0b1..The software trigger activates the SWOCTRL register synchronization. 2038 */ 2039 #define FTM_SYNCONF_SWSOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWSOC_SHIFT)) & FTM_SYNCONF_SWSOC_MASK) 2040 #define FTM_SYNCONF_HWRSTCNT_MASK (0x10000U) 2041 #define FTM_SYNCONF_HWRSTCNT_SHIFT (16U) 2042 /*! HWRSTCNT 2043 * 0b0..A hardware trigger does not activate the FTM counter synchronization. 2044 * 0b1..A hardware trigger activates the FTM counter synchronization. 2045 */ 2046 #define FTM_SYNCONF_HWRSTCNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWRSTCNT_SHIFT)) & FTM_SYNCONF_HWRSTCNT_MASK) 2047 #define FTM_SYNCONF_HWWRBUF_MASK (0x20000U) 2048 #define FTM_SYNCONF_HWWRBUF_SHIFT (17U) 2049 /*! HWWRBUF 2050 * 0b0..A hardware trigger does not activate MOD, CNTIN, and CV registers synchronization. 2051 * 0b1..A hardware trigger activates MOD, CNTIN, and CV registers synchronization. 2052 */ 2053 #define FTM_SYNCONF_HWWRBUF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWWRBUF_SHIFT)) & FTM_SYNCONF_HWWRBUF_MASK) 2054 #define FTM_SYNCONF_HWOM_MASK (0x40000U) 2055 #define FTM_SYNCONF_HWOM_SHIFT (18U) 2056 /*! HWOM 2057 * 0b0..A hardware trigger does not activate the OUTMASK register synchronization. 2058 * 0b1..A hardware trigger activates the OUTMASK register synchronization. 2059 */ 2060 #define FTM_SYNCONF_HWOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWOM_SHIFT)) & FTM_SYNCONF_HWOM_MASK) 2061 #define FTM_SYNCONF_HWINVC_MASK (0x80000U) 2062 #define FTM_SYNCONF_HWINVC_SHIFT (19U) 2063 /*! HWINVC 2064 * 0b0..A hardware trigger does not activate the INVCTRL register synchronization. 2065 * 0b1..A hardware trigger activates the INVCTRL register synchronization. 2066 */ 2067 #define FTM_SYNCONF_HWINVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWINVC_SHIFT)) & FTM_SYNCONF_HWINVC_MASK) 2068 #define FTM_SYNCONF_HWSOC_MASK (0x100000U) 2069 #define FTM_SYNCONF_HWSOC_SHIFT (20U) 2070 /*! HWSOC 2071 * 0b0..A hardware trigger does not activate the SWOCTRL register synchronization. 2072 * 0b1..A hardware trigger activates the SWOCTRL register synchronization. 2073 */ 2074 #define FTM_SYNCONF_HWSOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWSOC_SHIFT)) & FTM_SYNCONF_HWSOC_MASK) 2075 /*! @} */ 2076 2077 /*! @name INVCTRL - FTM Inverting Control */ 2078 /*! @{ */ 2079 #define FTM_INVCTRL_INV0EN_MASK (0x1U) 2080 #define FTM_INVCTRL_INV0EN_SHIFT (0U) 2081 /*! INV0EN - Pair Channels 0 Inverting Enable 2082 * 0b0..Inverting is disabled. 2083 * 0b1..Inverting is enabled. 2084 */ 2085 #define FTM_INVCTRL_INV0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV0EN_SHIFT)) & FTM_INVCTRL_INV0EN_MASK) 2086 #define FTM_INVCTRL_INV1EN_MASK (0x2U) 2087 #define FTM_INVCTRL_INV1EN_SHIFT (1U) 2088 /*! INV1EN - Pair Channels 1 Inverting Enable 2089 * 0b0..Inverting is disabled. 2090 * 0b1..Inverting is enabled. 2091 */ 2092 #define FTM_INVCTRL_INV1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV1EN_SHIFT)) & FTM_INVCTRL_INV1EN_MASK) 2093 #define FTM_INVCTRL_INV2EN_MASK (0x4U) 2094 #define FTM_INVCTRL_INV2EN_SHIFT (2U) 2095 /*! INV2EN - Pair Channels 2 Inverting Enable 2096 * 0b0..Inverting is disabled. 2097 * 0b1..Inverting is enabled. 2098 */ 2099 #define FTM_INVCTRL_INV2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV2EN_SHIFT)) & FTM_INVCTRL_INV2EN_MASK) 2100 #define FTM_INVCTRL_INV3EN_MASK (0x8U) 2101 #define FTM_INVCTRL_INV3EN_SHIFT (3U) 2102 /*! INV3EN - Pair Channels 3 Inverting Enable 2103 * 0b0..Inverting is disabled. 2104 * 0b1..Inverting is enabled. 2105 */ 2106 #define FTM_INVCTRL_INV3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV3EN_SHIFT)) & FTM_INVCTRL_INV3EN_MASK) 2107 /*! @} */ 2108 2109 /*! @name SWOCTRL - FTM Software Output Control */ 2110 /*! @{ */ 2111 #define FTM_SWOCTRL_CH0OC_MASK (0x1U) 2112 #define FTM_SWOCTRL_CH0OC_SHIFT (0U) 2113 /*! CH0OC - Channel 0 Software Output Control Enable 2114 * 0b0..The channel output is not affected by software output control. 2115 * 0b1..The channel output is affected by software output control. 2116 */ 2117 #define FTM_SWOCTRL_CH0OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OC_SHIFT)) & FTM_SWOCTRL_CH0OC_MASK) 2118 #define FTM_SWOCTRL_CH1OC_MASK (0x2U) 2119 #define FTM_SWOCTRL_CH1OC_SHIFT (1U) 2120 /*! CH1OC - Channel 1 Software Output Control Enable 2121 * 0b0..The channel output is not affected by software output control. 2122 * 0b1..The channel output is affected by software output control. 2123 */ 2124 #define FTM_SWOCTRL_CH1OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OC_SHIFT)) & FTM_SWOCTRL_CH1OC_MASK) 2125 #define FTM_SWOCTRL_CH2OC_MASK (0x4U) 2126 #define FTM_SWOCTRL_CH2OC_SHIFT (2U) 2127 /*! CH2OC - Channel 2 Software Output Control Enable 2128 * 0b0..The channel output is not affected by software output control. 2129 * 0b1..The channel output is affected by software output control. 2130 */ 2131 #define FTM_SWOCTRL_CH2OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OC_SHIFT)) & FTM_SWOCTRL_CH2OC_MASK) 2132 #define FTM_SWOCTRL_CH3OC_MASK (0x8U) 2133 #define FTM_SWOCTRL_CH3OC_SHIFT (3U) 2134 /*! CH3OC - Channel 3 Software Output Control Enable 2135 * 0b0..The channel output is not affected by software output control. 2136 * 0b1..The channel output is affected by software output control. 2137 */ 2138 #define FTM_SWOCTRL_CH3OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OC_SHIFT)) & FTM_SWOCTRL_CH3OC_MASK) 2139 #define FTM_SWOCTRL_CH4OC_MASK (0x10U) 2140 #define FTM_SWOCTRL_CH4OC_SHIFT (4U) 2141 /*! CH4OC - Channel 4 Software Output Control Enable 2142 * 0b0..The channel output is not affected by software output control. 2143 * 0b1..The channel output is affected by software output control. 2144 */ 2145 #define FTM_SWOCTRL_CH4OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OC_SHIFT)) & FTM_SWOCTRL_CH4OC_MASK) 2146 #define FTM_SWOCTRL_CH5OC_MASK (0x20U) 2147 #define FTM_SWOCTRL_CH5OC_SHIFT (5U) 2148 /*! CH5OC - Channel 5 Software Output Control Enable 2149 * 0b0..The channel output is not affected by software output control. 2150 * 0b1..The channel output is affected by software output control. 2151 */ 2152 #define FTM_SWOCTRL_CH5OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OC_SHIFT)) & FTM_SWOCTRL_CH5OC_MASK) 2153 #define FTM_SWOCTRL_CH6OC_MASK (0x40U) 2154 #define FTM_SWOCTRL_CH6OC_SHIFT (6U) 2155 /*! CH6OC - Channel 6 Software Output Control Enable 2156 * 0b0..The channel output is not affected by software output control. 2157 * 0b1..The channel output is affected by software output control. 2158 */ 2159 #define FTM_SWOCTRL_CH6OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OC_SHIFT)) & FTM_SWOCTRL_CH6OC_MASK) 2160 #define FTM_SWOCTRL_CH7OC_MASK (0x80U) 2161 #define FTM_SWOCTRL_CH7OC_SHIFT (7U) 2162 /*! CH7OC - Channel 7 Software Output Control Enable 2163 * 0b0..The channel output is not affected by software output control. 2164 * 0b1..The channel output is affected by software output control. 2165 */ 2166 #define FTM_SWOCTRL_CH7OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OC_SHIFT)) & FTM_SWOCTRL_CH7OC_MASK) 2167 #define FTM_SWOCTRL_CH0OCV_MASK (0x100U) 2168 #define FTM_SWOCTRL_CH0OCV_SHIFT (8U) 2169 /*! CH0OCV - Channel 0 Software Output Control Value 2170 * 0b0..The software output control forces 0 to the channel output. 2171 * 0b1..The software output control forces 1 to the channel output. 2172 */ 2173 #define FTM_SWOCTRL_CH0OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OCV_SHIFT)) & FTM_SWOCTRL_CH0OCV_MASK) 2174 #define FTM_SWOCTRL_CH1OCV_MASK (0x200U) 2175 #define FTM_SWOCTRL_CH1OCV_SHIFT (9U) 2176 /*! CH1OCV - Channel 1 Software Output Control Value 2177 * 0b0..The software output control forces 0 to the channel output. 2178 * 0b1..The software output control forces 1 to the channel output. 2179 */ 2180 #define FTM_SWOCTRL_CH1OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OCV_SHIFT)) & FTM_SWOCTRL_CH1OCV_MASK) 2181 #define FTM_SWOCTRL_CH2OCV_MASK (0x400U) 2182 #define FTM_SWOCTRL_CH2OCV_SHIFT (10U) 2183 /*! CH2OCV - Channel 2 Software Output Control Value 2184 * 0b0..The software output control forces 0 to the channel output. 2185 * 0b1..The software output control forces 1 to the channel output. 2186 */ 2187 #define FTM_SWOCTRL_CH2OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OCV_SHIFT)) & FTM_SWOCTRL_CH2OCV_MASK) 2188 #define FTM_SWOCTRL_CH3OCV_MASK (0x800U) 2189 #define FTM_SWOCTRL_CH3OCV_SHIFT (11U) 2190 /*! CH3OCV - Channel 3 Software Output Control Value 2191 * 0b0..The software output control forces 0 to the channel output. 2192 * 0b1..The software output control forces 1 to the channel output. 2193 */ 2194 #define FTM_SWOCTRL_CH3OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OCV_SHIFT)) & FTM_SWOCTRL_CH3OCV_MASK) 2195 #define FTM_SWOCTRL_CH4OCV_MASK (0x1000U) 2196 #define FTM_SWOCTRL_CH4OCV_SHIFT (12U) 2197 /*! CH4OCV - Channel 4 Software Output Control Value 2198 * 0b0..The software output control forces 0 to the channel output. 2199 * 0b1..The software output control forces 1 to the channel output. 2200 */ 2201 #define FTM_SWOCTRL_CH4OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OCV_SHIFT)) & FTM_SWOCTRL_CH4OCV_MASK) 2202 #define FTM_SWOCTRL_CH5OCV_MASK (0x2000U) 2203 #define FTM_SWOCTRL_CH5OCV_SHIFT (13U) 2204 /*! CH5OCV - Channel 5 Software Output Control Value 2205 * 0b0..The software output control forces 0 to the channel output. 2206 * 0b1..The software output control forces 1 to the channel output. 2207 */ 2208 #define FTM_SWOCTRL_CH5OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OCV_SHIFT)) & FTM_SWOCTRL_CH5OCV_MASK) 2209 #define FTM_SWOCTRL_CH6OCV_MASK (0x4000U) 2210 #define FTM_SWOCTRL_CH6OCV_SHIFT (14U) 2211 /*! CH6OCV - Channel 6 Software Output Control Value 2212 * 0b0..The software output control forces 0 to the channel output. 2213 * 0b1..The software output control forces 1 to the channel output. 2214 */ 2215 #define FTM_SWOCTRL_CH6OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OCV_SHIFT)) & FTM_SWOCTRL_CH6OCV_MASK) 2216 #define FTM_SWOCTRL_CH7OCV_MASK (0x8000U) 2217 #define FTM_SWOCTRL_CH7OCV_SHIFT (15U) 2218 /*! CH7OCV - Channel 7 Software Output Control Value 2219 * 0b0..The software output control forces 0 to the channel output. 2220 * 0b1..The software output control forces 1 to the channel output. 2221 */ 2222 #define FTM_SWOCTRL_CH7OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OCV_SHIFT)) & FTM_SWOCTRL_CH7OCV_MASK) 2223 /*! @} */ 2224 2225 /*! @name PWMLOAD - FTM PWM Load */ 2226 /*! @{ */ 2227 #define FTM_PWMLOAD_CH0SEL_MASK (0x1U) 2228 #define FTM_PWMLOAD_CH0SEL_SHIFT (0U) 2229 /*! CH0SEL - Channel 0 Select 2230 * 0b0..Do not include the channel in the matching process. 2231 * 0b1..Include the channel in the matching process. 2232 */ 2233 #define FTM_PWMLOAD_CH0SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH0SEL_SHIFT)) & FTM_PWMLOAD_CH0SEL_MASK) 2234 #define FTM_PWMLOAD_CH1SEL_MASK (0x2U) 2235 #define FTM_PWMLOAD_CH1SEL_SHIFT (1U) 2236 /*! CH1SEL - Channel 1 Select 2237 * 0b0..Do not include the channel in the matching process. 2238 * 0b1..Include the channel in the matching process. 2239 */ 2240 #define FTM_PWMLOAD_CH1SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH1SEL_SHIFT)) & FTM_PWMLOAD_CH1SEL_MASK) 2241 #define FTM_PWMLOAD_CH2SEL_MASK (0x4U) 2242 #define FTM_PWMLOAD_CH2SEL_SHIFT (2U) 2243 /*! CH2SEL - Channel 2 Select 2244 * 0b0..Do not include the channel in the matching process. 2245 * 0b1..Include the channel in the matching process. 2246 */ 2247 #define FTM_PWMLOAD_CH2SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH2SEL_SHIFT)) & FTM_PWMLOAD_CH2SEL_MASK) 2248 #define FTM_PWMLOAD_CH3SEL_MASK (0x8U) 2249 #define FTM_PWMLOAD_CH3SEL_SHIFT (3U) 2250 /*! CH3SEL - Channel 3 Select 2251 * 0b0..Do not include the channel in the matching process. 2252 * 0b1..Include the channel in the matching process. 2253 */ 2254 #define FTM_PWMLOAD_CH3SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH3SEL_SHIFT)) & FTM_PWMLOAD_CH3SEL_MASK) 2255 #define FTM_PWMLOAD_CH4SEL_MASK (0x10U) 2256 #define FTM_PWMLOAD_CH4SEL_SHIFT (4U) 2257 /*! CH4SEL - Channel 4 Select 2258 * 0b0..Do not include the channel in the matching process. 2259 * 0b1..Include the channel in the matching process. 2260 */ 2261 #define FTM_PWMLOAD_CH4SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH4SEL_SHIFT)) & FTM_PWMLOAD_CH4SEL_MASK) 2262 #define FTM_PWMLOAD_CH5SEL_MASK (0x20U) 2263 #define FTM_PWMLOAD_CH5SEL_SHIFT (5U) 2264 /*! CH5SEL - Channel 5 Select 2265 * 0b0..Do not include the channel in the matching process. 2266 * 0b1..Include the channel in the matching process. 2267 */ 2268 #define FTM_PWMLOAD_CH5SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH5SEL_SHIFT)) & FTM_PWMLOAD_CH5SEL_MASK) 2269 #define FTM_PWMLOAD_CH6SEL_MASK (0x40U) 2270 #define FTM_PWMLOAD_CH6SEL_SHIFT (6U) 2271 /*! CH6SEL - Channel 6 Select 2272 * 0b0..Do not include the channel in the matching process. 2273 * 0b1..Include the channel in the matching process. 2274 */ 2275 #define FTM_PWMLOAD_CH6SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH6SEL_SHIFT)) & FTM_PWMLOAD_CH6SEL_MASK) 2276 #define FTM_PWMLOAD_CH7SEL_MASK (0x80U) 2277 #define FTM_PWMLOAD_CH7SEL_SHIFT (7U) 2278 /*! CH7SEL - Channel 7 Select 2279 * 0b0..Do not include the channel in the matching process. 2280 * 0b1..Include the channel in the matching process. 2281 */ 2282 #define FTM_PWMLOAD_CH7SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH7SEL_SHIFT)) & FTM_PWMLOAD_CH7SEL_MASK) 2283 #define FTM_PWMLOAD_LDOK_MASK (0x200U) 2284 #define FTM_PWMLOAD_LDOK_SHIFT (9U) 2285 /*! LDOK - Load Enable 2286 * 0b0..Loading updated values is disabled. 2287 * 0b1..Loading updated values is enabled. 2288 */ 2289 #define FTM_PWMLOAD_LDOK(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_LDOK_SHIFT)) & FTM_PWMLOAD_LDOK_MASK) 2290 /*! @} */ 2291 2292 2293 /*! 2294 * @} 2295 */ /* end of group FTM_Register_Masks */ 2296 2297 2298 /* FTM - Peripheral instance base addresses */ 2299 /** Peripheral FTM0 base address */ 2300 #define FTM0_BASE (0x40038000u) 2301 /** Peripheral FTM0 base pointer */ 2302 #define FTM0 ((FTM_Type *)FTM0_BASE) 2303 /** Peripheral FTM2 base address */ 2304 #define FTM2_BASE (0x4003A000u) 2305 /** Peripheral FTM2 base pointer */ 2306 #define FTM2 ((FTM_Type *)FTM2_BASE) 2307 /** Array initializer of FTM peripheral base addresses */ 2308 #define FTM_BASE_ADDRS { FTM0_BASE, 0u, FTM2_BASE } 2309 /** Array initializer of FTM peripheral base pointers */ 2310 #define FTM_BASE_PTRS { FTM0, (FTM_Type *)0u, FTM2 } 2311 /** Interrupt vectors for the FTM peripheral type */ 2312 #define FTM_IRQS { FTM0_IRQn, NotAvail_IRQn, FTM2_IRQn } 2313 /* Backward compatibility */ 2314 /*! @name SC - Status And Control */ 2315 #define TPM_SC_PS_MASK FTM_SC_PS_MASK 2316 #define TPM_SC_PS_SHIFT FTM_SC_PS_SHIFT 2317 #define TPM_SC_PS(x) FTM_SC_PS(x) 2318 #define TPM_SC_CLKS_MASK FTM_SC_CLKS_MASK 2319 #define TPM_SC_CLKS_SHIFT FTM_SC_CLKS_SHIFT 2320 #define TPM_SC_CLKS(x) FTM_SC_CLKS(x) 2321 #define TPM_SC_CPWMS_MASK FTM_SC_CPWMS_MASK 2322 #define TPM_SC_CPWMS_SHIFT FTM_SC_CPWMS_SHIFT 2323 #define TPM_SC_CPWMS(x) FTM_SC_CPWMS(x) 2324 #define TPM_SC_TOIE_MASK FTM_SC_TOIE_MASK 2325 #define TPM_SC_TOIE_SHIFT FTM_SC_TOIE_SHIFT 2326 #define TPM_SC_TOIE(x) FTM_SC_TOIE(x) 2327 #define TPM_SC_TOF_MASK FTM_SC_TOF_MASK 2328 #define TPM_SC_TOF_SHIFT FTM_SC_TOF_SHIFT 2329 #define TPM_SC_TOF(x) FTM_SC_TOF(x) 2330 /*! @name CNT - Counter */ 2331 #define TPM_CNT_COUNT_MASK FTM_CNT_COUNT_MASK 2332 #define TPM_CNT_COUNT_SHIFT FTM_CNT_COUNT_SHIFT 2333 #define TPM_CNT_COUNT(x) FTM_CNT_COUNT(x) 2334 /*! @name MOD - Modulo */ 2335 #define TPM_MOD_MOD_MASK FTM_MOD_MOD_MASK 2336 #define TPM_MOD_MOD_SHIFT FTM_MOD_MOD_SHIFT 2337 #define TPM_MOD_MOD(x) FTM_MOD_MOD(x) 2338 /*! @name CnSC - Channel (n) Status And Control */ 2339 #define TPM_CnSC_ELSA_MASK FTM_CnSC_ELSA_MASK 2340 #define TPM_CnSC_ELSA_SHIFT FTM_CnSC_ELSA_SHIFT 2341 #define TPM_CnSC_ELSA(x) FTM_CnSC_ELSA(x) 2342 #define TPM_CnSC_ELSB_MASK FTM_CnSC_ELSB_MASK 2343 #define TPM_CnSC_ELSB_SHIFT FTM_CnSC_ELSB_SHIFT 2344 #define TPM_CnSC_ELSB(x) FTM_CnSC_ELSB(x) 2345 #define TPM_CnSC_MSA_MASK FTM_CnSC_MSA_MASK 2346 #define TPM_CnSC_MSA_SHIFT FTM_CnSC_MSA_SHIFT 2347 #define TPM_CnSC_MSA(x) FTM_CnSC_MSA(x) 2348 #define TPM_CnSC_MSB_MASK FTM_CnSC_MSB_MASK 2349 #define TPM_CnSC_MSB_SHIFT FTM_CnSC_MSB_SHIFT 2350 #define TPM_CnSC_MSB(x) FTM_CnSC_MSB(x) 2351 #define TPM_CnSC_CHIE_MASK FTM_CnSC_CHIE_MASK 2352 #define TPM_CnSC_CHIE_SHIFT FTM_CnSC_CHIE_SHIFT 2353 #define TPM_CnSC_CHIE(x) FTM_CnSC_CHIE(x) 2354 #define TPM_CnSC_CHF_MASK FTM_CnSC_CHF_MASK 2355 #define TPM_CnSC_CHF_SHIFT FTM_CnSC_CHF_SHIFT 2356 #define TPM_CnSC_CHF(x) FTM_CnSC_CHF(x) 2357 /* The count of FTM_CnSC */ 2358 #define TPM_CnSC_COUNT (2U) 2359 /*! @name CnV - Channel (n) Value */ 2360 #define TPM_CnV_VAL_MASK FTM_CnV_VAL_MASK 2361 #define TPM_CnV_VAL_SHIFT FTM_CnV_VAL_SHIFT 2362 #define TPM_CnV_VAL(x) FTM_CnV_VAL(x) 2363 /* The count of FTM_CnSC */ 2364 #define TPM_CnV_COUNT (2U) 2365 /** TPM - Register Layout Typedef */ 2366 typedef FTM_Type TPM_Type; 2367 #define TPM0_IRQn FTM0_IRQn 2368 #define TPM0_IRQHandler FTM0_IRQHandler 2369 #define TPM_CLOCKS FTM_CLOCKS 2370 /* TPM - Peripheral instance base addresses */ 2371 /** Peripheral TPM0 base address */ 2372 #define TPM0_BASE FTM0_BASE 2373 /** Peripheral TPM0 base pointer */ 2374 #define TPM0 ((TPM_Type *)TPM0_BASE) 2375 /** Array initializer of TPM peripheral base addresses */ 2376 #define TPM_BASE_ADDRS { TPM0_BASE } 2377 /** Array initializer of TPM peripheral base pointers */ 2378 #define TPM_BASE_PTRS { TPM0 } 2379 /** Interrupt vectors for the TPM peripheral type */ 2380 #define TPM_IRQS { TPM0_IRQn } 2381 2382 2383 /*! 2384 * @} 2385 */ /* end of group FTM_Peripheral_Access_Layer */ 2386 2387 2388 /* ---------------------------------------------------------------------------- 2389 -- FTMRE Peripheral Access Layer 2390 ---------------------------------------------------------------------------- */ 2391 2392 /*! 2393 * @addtogroup FTMRE_Peripheral_Access_Layer FTMRE Peripheral Access Layer 2394 * @{ 2395 */ 2396 2397 /** FTMRE - Register Layout Typedef */ 2398 typedef struct { 2399 uint8_t RESERVED_0[1]; 2400 __IO uint8_t FCCOBIX; /**< Flash CCOB Index Register, offset: 0x1 */ 2401 __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */ 2402 __IO uint8_t FCLKDIV; /**< Flash Clock Divider Register, offset: 0x3 */ 2403 uint8_t RESERVED_1[1]; 2404 __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x5 */ 2405 uint8_t RESERVED_2[1]; 2406 __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x7 */ 2407 __IO uint8_t FCCOBLO; /**< Flash Common Command Object Register: Low, offset: 0x8 */ 2408 __IO uint8_t FCCOBHI; /**< Flash Common Command Object Register:High, offset: 0x9 */ 2409 uint8_t RESERVED_3[1]; 2410 __IO uint8_t FPROT; /**< Flash Protection Register, offset: 0xB */ 2411 uint8_t RESERVED_4[3]; 2412 __I uint8_t FOPT; /**< Flash Option Register, offset: 0xF */ 2413 } FTMRE_Type; 2414 2415 /* ---------------------------------------------------------------------------- 2416 -- FTMRE Register Masks 2417 ---------------------------------------------------------------------------- */ 2418 2419 /*! 2420 * @addtogroup FTMRE_Register_Masks FTMRE Register Masks 2421 * @{ 2422 */ 2423 2424 /*! @name FCCOBIX - Flash CCOB Index Register */ 2425 /*! @{ */ 2426 #define FTMRE_FCCOBIX_CCOBIX_MASK (0x7U) 2427 #define FTMRE_FCCOBIX_CCOBIX_SHIFT (0U) 2428 #define FTMRE_FCCOBIX_CCOBIX(x) (((uint8_t)(((uint8_t)(x)) << FTMRE_FCCOBIX_CCOBIX_SHIFT)) & FTMRE_FCCOBIX_CCOBIX_MASK) 2429 /*! @} */ 2430 2431 /*! @name FSEC - Flash Security Register */ 2432 /*! @{ */ 2433 #define FTMRE_FSEC_SEC_MASK (0x3U) 2434 #define FTMRE_FSEC_SEC_SHIFT (0U) 2435 /*! SEC - Flash Security Bits 2436 * 0b00..Secured 2437 * 0b01..Secured 2438 * 0b10..Unsecured 2439 * 0b11..Secured 2440 */ 2441 #define FTMRE_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << FTMRE_FSEC_SEC_SHIFT)) & FTMRE_FSEC_SEC_MASK) 2442 #define FTMRE_FSEC_KEYEN_MASK (0xC0U) 2443 #define FTMRE_FSEC_KEYEN_SHIFT (6U) 2444 /*! KEYEN - Backdoor Key Security Enable Bits 2445 * 0b00..Disabled 2446 * 0b01..Disabled 2447 * 0b10..Enabled 2448 * 0b11..Disabled 2449 */ 2450 #define FTMRE_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << FTMRE_FSEC_KEYEN_SHIFT)) & FTMRE_FSEC_KEYEN_MASK) 2451 /*! @} */ 2452 2453 /*! @name FCLKDIV - Flash Clock Divider Register */ 2454 /*! @{ */ 2455 #define FTMRE_FCLKDIV_FDIV_MASK (0x3FU) 2456 #define FTMRE_FCLKDIV_FDIV_SHIFT (0U) 2457 #define FTMRE_FCLKDIV_FDIV(x) (((uint8_t)(((uint8_t)(x)) << FTMRE_FCLKDIV_FDIV_SHIFT)) & FTMRE_FCLKDIV_FDIV_MASK) 2458 #define FTMRE_FCLKDIV_FDIVLCK_MASK (0x40U) 2459 #define FTMRE_FCLKDIV_FDIVLCK_SHIFT (6U) 2460 /*! FDIVLCK - Clock Divider Locked 2461 * 0b0..FDIV field is open for writing. 2462 * 0b1..FDIV value is locked and cannot be changed. After the lock bit is set high, only reset can clear this bit and restore writability to the FDIV field in user mode. 2463 */ 2464 #define FTMRE_FCLKDIV_FDIVLCK(x) (((uint8_t)(((uint8_t)(x)) << FTMRE_FCLKDIV_FDIVLCK_SHIFT)) & FTMRE_FCLKDIV_FDIVLCK_MASK) 2465 #define FTMRE_FCLKDIV_FDIVLD_MASK (0x80U) 2466 #define FTMRE_FCLKDIV_FDIVLD_SHIFT (7U) 2467 /*! FDIVLD - Clock Divider Loaded 2468 * 0b0..FCLKDIV register has not been written since the last reset. 2469 * 0b1..FCLKDIV register has been written since the last reset. 2470 */ 2471 #define FTMRE_FCLKDIV_FDIVLD(x) (((uint8_t)(((uint8_t)(x)) << FTMRE_FCLKDIV_FDIVLD_SHIFT)) & FTMRE_FCLKDIV_FDIVLD_MASK) 2472 /*! @} */ 2473 2474 /*! @name FSTAT - Flash Status Register */ 2475 /*! @{ */ 2476 #define FTMRE_FSTAT_MGSTAT_MASK (0x3U) 2477 #define FTMRE_FSTAT_MGSTAT_SHIFT (0U) 2478 #define FTMRE_FSTAT_MGSTAT(x) (((uint8_t)(((uint8_t)(x)) << FTMRE_FSTAT_MGSTAT_SHIFT)) & FTMRE_FSTAT_MGSTAT_MASK) 2479 #define FTMRE_FSTAT_MGBUSY_MASK (0x8U) 2480 #define FTMRE_FSTAT_MGBUSY_SHIFT (3U) 2481 /*! MGBUSY - Memory Controller Busy Flag 2482 * 0b0..Memory controller is idle. 2483 * 0b1..Memory controller is busy executing a flash command (CCIF = 0). 2484 */ 2485 #define FTMRE_FSTAT_MGBUSY(x) (((uint8_t)(((uint8_t)(x)) << FTMRE_FSTAT_MGBUSY_SHIFT)) & FTMRE_FSTAT_MGBUSY_MASK) 2486 #define FTMRE_FSTAT_FPVIOL_MASK (0x10U) 2487 #define FTMRE_FSTAT_FPVIOL_SHIFT (4U) 2488 /*! FPVIOL - Flash Protection Violation Flag 2489 * 0b0..No protection violation is detected. 2490 * 0b1..Protection violation is detected. 2491 */ 2492 #define FTMRE_FSTAT_FPVIOL(x) (((uint8_t)(((uint8_t)(x)) << FTMRE_FSTAT_FPVIOL_SHIFT)) & FTMRE_FSTAT_FPVIOL_MASK) 2493 #define FTMRE_FSTAT_ACCERR_MASK (0x20U) 2494 #define FTMRE_FSTAT_ACCERR_SHIFT (5U) 2495 /*! ACCERR - Flash Access Error Flag 2496 * 0b0..No access error is detected. 2497 * 0b1..Access error is detected. 2498 */ 2499 #define FTMRE_FSTAT_ACCERR(x) (((uint8_t)(((uint8_t)(x)) << FTMRE_FSTAT_ACCERR_SHIFT)) & FTMRE_FSTAT_ACCERR_MASK) 2500 #define FTMRE_FSTAT_CCIF_MASK (0x80U) 2501 #define FTMRE_FSTAT_CCIF_SHIFT (7U) 2502 /*! CCIF - Command Complete Interrupt Flag 2503 * 0b0..Flash command is in progress. 2504 * 0b1..Flash command has completed. 2505 */ 2506 #define FTMRE_FSTAT_CCIF(x) (((uint8_t)(((uint8_t)(x)) << FTMRE_FSTAT_CCIF_SHIFT)) & FTMRE_FSTAT_CCIF_MASK) 2507 /*! @} */ 2508 2509 /*! @name FCNFG - Flash Configuration Register */ 2510 /*! @{ */ 2511 #define FTMRE_FCNFG_ERSAREQ_MASK (0x20U) 2512 #define FTMRE_FCNFG_ERSAREQ_SHIFT (5U) 2513 /*! ERSAREQ - Debugger Mass Erase Request 2514 * 0b0..No request or request complete 2515 * 0b1..Request to run the Erase All Blocks command verify the erased state program the security byte in the Flash Configuration Field to the unsecure state release MCU security by setting FSEC[SEC] to the unsecure state 2516 */ 2517 #define FTMRE_FCNFG_ERSAREQ(x) (((uint8_t)(((uint8_t)(x)) << FTMRE_FCNFG_ERSAREQ_SHIFT)) & FTMRE_FCNFG_ERSAREQ_MASK) 2518 #define FTMRE_FCNFG_CCIE_MASK (0x80U) 2519 #define FTMRE_FCNFG_CCIE_SHIFT (7U) 2520 /*! CCIE - Command Complete Interrupt Enable 2521 * 0b0..Command complete interrupt is disabled. 2522 * 0b1..An interrupt will be requested whenever the CCIF flag in the FSTAT register is set. 2523 */ 2524 #define FTMRE_FCNFG_CCIE(x) (((uint8_t)(((uint8_t)(x)) << FTMRE_FCNFG_CCIE_SHIFT)) & FTMRE_FCNFG_CCIE_MASK) 2525 /*! @} */ 2526 2527 /*! @name FCCOBLO - Flash Common Command Object Register: Low */ 2528 /*! @{ */ 2529 #define FTMRE_FCCOBLO_CCOB_MASK (0xFFU) 2530 #define FTMRE_FCCOBLO_CCOB_SHIFT (0U) 2531 #define FTMRE_FCCOBLO_CCOB(x) (((uint8_t)(((uint8_t)(x)) << FTMRE_FCCOBLO_CCOB_SHIFT)) & FTMRE_FCCOBLO_CCOB_MASK) 2532 /*! @} */ 2533 2534 /*! @name FCCOBHI - Flash Common Command Object Register:High */ 2535 /*! @{ */ 2536 #define FTMRE_FCCOBHI_CCOB_MASK (0xFFU) 2537 #define FTMRE_FCCOBHI_CCOB_SHIFT (0U) 2538 #define FTMRE_FCCOBHI_CCOB(x) (((uint8_t)(((uint8_t)(x)) << FTMRE_FCCOBHI_CCOB_SHIFT)) & FTMRE_FCCOBHI_CCOB_MASK) 2539 /*! @} */ 2540 2541 /*! @name FPROT - Flash Protection Register */ 2542 /*! @{ */ 2543 #define FTMRE_FPROT_FPLS_MASK (0x3U) 2544 #define FTMRE_FPROT_FPLS_SHIFT (0U) 2545 #define FTMRE_FPROT_FPLS(x) (((uint8_t)(((uint8_t)(x)) << FTMRE_FPROT_FPLS_SHIFT)) & FTMRE_FPROT_FPLS_MASK) 2546 #define FTMRE_FPROT_FPLDIS_MASK (0x4U) 2547 #define FTMRE_FPROT_FPLDIS_SHIFT (2U) 2548 /*! FPLDIS - Flash Protection Lower Address Range Disable 2549 * 0b0..Protection/Unprotection enabled. 2550 * 0b1..Protection/Unprotection disabled. 2551 */ 2552 #define FTMRE_FPROT_FPLDIS(x) (((uint8_t)(((uint8_t)(x)) << FTMRE_FPROT_FPLDIS_SHIFT)) & FTMRE_FPROT_FPLDIS_MASK) 2553 #define FTMRE_FPROT_RNV_MASK (0x38U) 2554 #define FTMRE_FPROT_RNV_SHIFT (3U) 2555 #define FTMRE_FPROT_RNV(x) (((uint8_t)(((uint8_t)(x)) << FTMRE_FPROT_RNV_SHIFT)) & FTMRE_FPROT_RNV_MASK) 2556 #define FTMRE_FPROT_RNV6_MASK (0x40U) 2557 #define FTMRE_FPROT_RNV6_SHIFT (6U) 2558 #define FTMRE_FPROT_RNV6(x) (((uint8_t)(((uint8_t)(x)) << FTMRE_FPROT_RNV6_SHIFT)) & FTMRE_FPROT_RNV6_MASK) 2559 #define FTMRE_FPROT_FPOPEN_MASK (0x80U) 2560 #define FTMRE_FPROT_FPOPEN_SHIFT (7U) 2561 /*! FPOPEN - Flash Protection Operation Enable 2562 * 0b0..When FPOPEN is clear, the FPLDIS field defines unprotected address ranges as specified by the corresponding FPLS field. 2563 * 0b1..When FPOPEN is set, the FPLDIS field enables protection for the address range specified by the corresponding FPLS field. 2564 */ 2565 #define FTMRE_FPROT_FPOPEN(x) (((uint8_t)(((uint8_t)(x)) << FTMRE_FPROT_FPOPEN_SHIFT)) & FTMRE_FPROT_FPOPEN_MASK) 2566 /*! @} */ 2567 2568 /*! @name FOPT - Flash Option Register */ 2569 /*! @{ */ 2570 #define FTMRE_FOPT_NV_MASK (0xFFU) 2571 #define FTMRE_FOPT_NV_SHIFT (0U) 2572 #define FTMRE_FOPT_NV(x) (((uint8_t)(((uint8_t)(x)) << FTMRE_FOPT_NV_SHIFT)) & FTMRE_FOPT_NV_MASK) 2573 /*! @} */ 2574 2575 2576 /*! 2577 * @} 2578 */ /* end of group FTMRE_Register_Masks */ 2579 2580 2581 /* FTMRE - Peripheral instance base addresses */ 2582 /** Peripheral FTMRE base address */ 2583 #define FTMRE_BASE (0x40020000u) 2584 /** Peripheral FTMRE base pointer */ 2585 #define FTMRE ((FTMRE_Type *)FTMRE_BASE) 2586 /** Array initializer of FTMRE peripheral base addresses */ 2587 #define FTMRE_BASE_ADDRS { FTMRE_BASE } 2588 /** Array initializer of FTMRE peripheral base pointers */ 2589 #define FTMRE_BASE_PTRS { FTMRE } 2590 /** Interrupt vectors for the FTMRE peripheral type */ 2591 #define FTMRE_IRQS { FTMRE_IRQn } 2592 2593 /*! 2594 * @} 2595 */ /* end of group FTMRE_Peripheral_Access_Layer */ 2596 2597 2598 /* ---------------------------------------------------------------------------- 2599 -- GPIO Peripheral Access Layer 2600 ---------------------------------------------------------------------------- */ 2601 2602 /*! 2603 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer 2604 * @{ 2605 */ 2606 2607 /** GPIO - Register Layout Typedef */ 2608 typedef struct { 2609 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */ 2610 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */ 2611 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */ 2612 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */ 2613 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */ 2614 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */ 2615 __IO uint32_t PIDR; /**< Port Input Disable Register, offset: 0x18 */ 2616 } GPIO_Type; 2617 2618 /* ---------------------------------------------------------------------------- 2619 -- GPIO Register Masks 2620 ---------------------------------------------------------------------------- */ 2621 2622 /*! 2623 * @addtogroup GPIO_Register_Masks GPIO Register Masks 2624 * @{ 2625 */ 2626 2627 /*! @name PDOR - Port Data Output Register */ 2628 /*! @{ */ 2629 #define GPIO_PDOR_PDO_MASK (0xFFFFFFFFU) 2630 #define GPIO_PDOR_PDO_SHIFT (0U) 2631 /*! PDO - Port Data Output 2632 * 0b00000000000000000000000000000000..Logic level 0 is driven on pin, provided pin is configured for general-purpose output. 2633 * 0b00000000000000000000000000000001..Logic level 1 is driven on pin, provided pin is configured for general-purpose output. 2634 */ 2635 #define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO_SHIFT)) & GPIO_PDOR_PDO_MASK) 2636 /*! @} */ 2637 2638 /*! @name PSOR - Port Set Output Register */ 2639 /*! @{ */ 2640 #define GPIO_PSOR_PTSO_MASK (0xFFFFFFFFU) 2641 #define GPIO_PSOR_PTSO_SHIFT (0U) 2642 /*! PTSO - Port Set Output 2643 * 0b00000000000000000000000000000000..Corresponding bit in PDORn does not change. 2644 * 0b00000000000000000000000000000001..Corresponding bit in PDORn is set to logic 1. 2645 */ 2646 #define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO_SHIFT)) & GPIO_PSOR_PTSO_MASK) 2647 /*! @} */ 2648 2649 /*! @name PCOR - Port Clear Output Register */ 2650 /*! @{ */ 2651 #define GPIO_PCOR_PTCO_MASK (0xFFFFFFFFU) 2652 #define GPIO_PCOR_PTCO_SHIFT (0U) 2653 /*! PTCO - Port Clear Output 2654 * 0b00000000000000000000000000000000..Corresponding bit in PDORn does not change. 2655 * 0b00000000000000000000000000000001..Corresponding bit in PDORn is cleared to logic 0. 2656 */ 2657 #define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO_SHIFT)) & GPIO_PCOR_PTCO_MASK) 2658 /*! @} */ 2659 2660 /*! @name PTOR - Port Toggle Output Register */ 2661 /*! @{ */ 2662 #define GPIO_PTOR_PTTO_MASK (0xFFFFFFFFU) 2663 #define GPIO_PTOR_PTTO_SHIFT (0U) 2664 /*! PTTO - Port Toggle Output 2665 * 0b00000000000000000000000000000000..Corresponding bit in PDORn does not change. 2666 * 0b00000000000000000000000000000001..Corresponding bit in PDORn is set to the inverse of its existing logic state. 2667 */ 2668 #define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO_SHIFT)) & GPIO_PTOR_PTTO_MASK) 2669 /*! @} */ 2670 2671 /*! @name PDIR - Port Data Input Register */ 2672 /*! @{ */ 2673 #define GPIO_PDIR_PDI_MASK (0xFFFFFFFFU) 2674 #define GPIO_PDIR_PDI_SHIFT (0U) 2675 /*! PDI - Port Data Input 2676 * 0b00000000000000000000000000000000..Pin logic level is logic 0, or is not configured for use by digital function. 2677 * 0b00000000000000000000000000000001..Pin logic level is logic 1. 2678 */ 2679 #define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI_SHIFT)) & GPIO_PDIR_PDI_MASK) 2680 /*! @} */ 2681 2682 /*! @name PDDR - Port Data Direction Register */ 2683 /*! @{ */ 2684 #define GPIO_PDDR_PDD_MASK (0xFFFFFFFFU) 2685 #define GPIO_PDDR_PDD_SHIFT (0U) 2686 /*! PDD - Port Data Direction 2687 * 0b00000000000000000000000000000000..Pin is configured as general-purpose input, for the GPIO function. The pin will be high-Z if the port input is disabled in GPIOx_PIDR register. 2688 * 0b00000000000000000000000000000001..Pin is configured as general-purpose output, for the GPIO function. 2689 */ 2690 #define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD_SHIFT)) & GPIO_PDDR_PDD_MASK) 2691 /*! @} */ 2692 2693 /*! @name PIDR - Port Input Disable Register */ 2694 /*! @{ */ 2695 #define GPIO_PIDR_PID_MASK (0xFFFFFFFFU) 2696 #define GPIO_PIDR_PID_SHIFT (0U) 2697 /*! PID - Port Input Disable 2698 * 0b00000000000000000000000000000000..Pin is configured for General Purpose Input, provided the pin is configured for any digital function. 2699 * 0b00000000000000000000000000000001..Pin is not configured as General Purpose Input.Corresponding Port Data Input Register bit will read zero. 2700 */ 2701 #define GPIO_PIDR_PID(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID_SHIFT)) & GPIO_PIDR_PID_MASK) 2702 /*! @} */ 2703 2704 2705 /*! 2706 * @} 2707 */ /* end of group GPIO_Register_Masks */ 2708 2709 2710 /* GPIO - Peripheral instance base addresses */ 2711 /** Peripheral GPIOA base address */ 2712 #define GPIOA_BASE (0x400FF000u) 2713 /** Peripheral GPIOA base pointer */ 2714 #define GPIOA ((GPIO_Type *)GPIOA_BASE) 2715 /** Array initializer of GPIO peripheral base addresses */ 2716 #define GPIO_BASE_ADDRS { GPIOA_BASE } 2717 /** Array initializer of GPIO peripheral base pointers */ 2718 #define GPIO_BASE_PTRS { GPIOA } 2719 2720 /*! 2721 * @} 2722 */ /* end of group GPIO_Peripheral_Access_Layer */ 2723 2724 2725 /* ---------------------------------------------------------------------------- 2726 -- I2C Peripheral Access Layer 2727 ---------------------------------------------------------------------------- */ 2728 2729 /*! 2730 * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer 2731 * @{ 2732 */ 2733 2734 /** I2C - Register Layout Typedef */ 2735 typedef struct { 2736 __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */ 2737 __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */ 2738 __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */ 2739 __IO uint8_t S; /**< I2C Status register, offset: 0x3 */ 2740 __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */ 2741 __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */ 2742 __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */ 2743 __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */ 2744 __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */ 2745 __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */ 2746 __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */ 2747 __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */ 2748 } I2C_Type; 2749 2750 /* ---------------------------------------------------------------------------- 2751 -- I2C Register Masks 2752 ---------------------------------------------------------------------------- */ 2753 2754 /*! 2755 * @addtogroup I2C_Register_Masks I2C Register Masks 2756 * @{ 2757 */ 2758 2759 /*! @name A1 - I2C Address Register 1 */ 2760 /*! @{ */ 2761 #define I2C_A1_AD_MASK (0xFEU) 2762 #define I2C_A1_AD_SHIFT (1U) 2763 #define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A1_AD_SHIFT)) & I2C_A1_AD_MASK) 2764 /*! @} */ 2765 2766 /*! @name F - I2C Frequency Divider register */ 2767 /*! @{ */ 2768 #define I2C_F_ICR_MASK (0x3FU) 2769 #define I2C_F_ICR_SHIFT (0U) 2770 #define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_ICR_SHIFT)) & I2C_F_ICR_MASK) 2771 #define I2C_F_MULT_MASK (0xC0U) 2772 #define I2C_F_MULT_SHIFT (6U) 2773 /*! MULT - Multiplier Factor 2774 * 0b00..mul = 1 2775 * 0b01..mul = 2 2776 * 0b10..mul = 4 2777 * 0b11..Reserved 2778 */ 2779 #define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_MULT_SHIFT)) & I2C_F_MULT_MASK) 2780 /*! @} */ 2781 2782 /*! @name C1 - I2C Control Register 1 */ 2783 /*! @{ */ 2784 #define I2C_C1_WUEN_MASK (0x2U) 2785 #define I2C_C1_WUEN_SHIFT (1U) 2786 /*! WUEN - Wakeup Enable 2787 * 0b0..Normal operation. No interrupt generated when address matching in low power mode. 2788 * 0b1..Enables the wakeup function in low power mode. 2789 */ 2790 #define I2C_C1_WUEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_WUEN_SHIFT)) & I2C_C1_WUEN_MASK) 2791 #define I2C_C1_RSTA_MASK (0x4U) 2792 #define I2C_C1_RSTA_SHIFT (2U) 2793 #define I2C_C1_RSTA(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_RSTA_SHIFT)) & I2C_C1_RSTA_MASK) 2794 #define I2C_C1_TXAK_MASK (0x8U) 2795 #define I2C_C1_TXAK_SHIFT (3U) 2796 /*! TXAK - Transmit Acknowledge Enable 2797 * 0b0..An acknowledge signal is sent to the bus on the following receiving byte (if FACK is cleared) or the current receiving byte (if FACK is set). 2798 * 0b1..No acknowledge signal is sent to the bus on the following receiving data byte (if FACK is cleared) or the current receiving data byte (if FACK is set). 2799 */ 2800 #define I2C_C1_TXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TXAK_SHIFT)) & I2C_C1_TXAK_MASK) 2801 #define I2C_C1_TX_MASK (0x10U) 2802 #define I2C_C1_TX_SHIFT (4U) 2803 /*! TX - Transmit Mode Select 2804 * 0b0..Receive 2805 * 0b1..Transmit 2806 */ 2807 #define I2C_C1_TX(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TX_SHIFT)) & I2C_C1_TX_MASK) 2808 #define I2C_C1_MST_MASK (0x20U) 2809 #define I2C_C1_MST_SHIFT (5U) 2810 /*! MST - Master Mode Select 2811 * 0b0..Slave mode 2812 * 0b1..Master mode 2813 */ 2814 #define I2C_C1_MST(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_MST_SHIFT)) & I2C_C1_MST_MASK) 2815 #define I2C_C1_IICIE_MASK (0x40U) 2816 #define I2C_C1_IICIE_SHIFT (6U) 2817 /*! IICIE - I2C Interrupt Enable 2818 * 0b0..Disabled 2819 * 0b1..Enabled 2820 */ 2821 #define I2C_C1_IICIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICIE_SHIFT)) & I2C_C1_IICIE_MASK) 2822 #define I2C_C1_IICEN_MASK (0x80U) 2823 #define I2C_C1_IICEN_SHIFT (7U) 2824 /*! IICEN - I2C Enable 2825 * 0b0..Disabled 2826 * 0b1..Enabled 2827 */ 2828 #define I2C_C1_IICEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICEN_SHIFT)) & I2C_C1_IICEN_MASK) 2829 /*! @} */ 2830 2831 /*! @name S - I2C Status register */ 2832 /*! @{ */ 2833 #define I2C_S_RXAK_MASK (0x1U) 2834 #define I2C_S_RXAK_SHIFT (0U) 2835 /*! RXAK - Receive Acknowledge 2836 * 0b0..Acknowledge signal was received after the completion of one byte of data transmission on the bus 2837 * 0b1..No acknowledge signal detected 2838 */ 2839 #define I2C_S_RXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RXAK_SHIFT)) & I2C_S_RXAK_MASK) 2840 #define I2C_S_IICIF_MASK (0x2U) 2841 #define I2C_S_IICIF_SHIFT (1U) 2842 /*! IICIF - Interrupt Flag 2843 * 0b0..No interrupt pending 2844 * 0b1..Interrupt pending 2845 */ 2846 #define I2C_S_IICIF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IICIF_SHIFT)) & I2C_S_IICIF_MASK) 2847 #define I2C_S_SRW_MASK (0x4U) 2848 #define I2C_S_SRW_SHIFT (2U) 2849 /*! SRW - Slave Read/Write 2850 * 0b0..Slave receive, master writing to slave 2851 * 0b1..Slave transmit, master reading from slave 2852 */ 2853 #define I2C_S_SRW(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_SRW_SHIFT)) & I2C_S_SRW_MASK) 2854 #define I2C_S_RAM_MASK (0x8U) 2855 #define I2C_S_RAM_SHIFT (3U) 2856 /*! RAM - Range Address Match 2857 * 0b0..Not addressed 2858 * 0b1..Addressed as a slave 2859 */ 2860 #define I2C_S_RAM(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RAM_SHIFT)) & I2C_S_RAM_MASK) 2861 #define I2C_S_ARBL_MASK (0x10U) 2862 #define I2C_S_ARBL_SHIFT (4U) 2863 /*! ARBL - Arbitration Lost 2864 * 0b0..Standard bus operation. 2865 * 0b1..Loss of arbitration. 2866 */ 2867 #define I2C_S_ARBL(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_ARBL_SHIFT)) & I2C_S_ARBL_MASK) 2868 #define I2C_S_BUSY_MASK (0x20U) 2869 #define I2C_S_BUSY_SHIFT (5U) 2870 /*! BUSY - Bus Busy 2871 * 0b0..Bus is idle 2872 * 0b1..Bus is busy 2873 */ 2874 #define I2C_S_BUSY(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_BUSY_SHIFT)) & I2C_S_BUSY_MASK) 2875 #define I2C_S_IAAS_MASK (0x40U) 2876 #define I2C_S_IAAS_SHIFT (6U) 2877 /*! IAAS - Addressed As A Slave 2878 * 0b0..Not addressed 2879 * 0b1..Addressed as a slave 2880 */ 2881 #define I2C_S_IAAS(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IAAS_SHIFT)) & I2C_S_IAAS_MASK) 2882 #define I2C_S_TCF_MASK (0x80U) 2883 #define I2C_S_TCF_SHIFT (7U) 2884 /*! TCF - Transfer Complete Flag 2885 * 0b0..Transfer in progress 2886 * 0b1..Transfer complete 2887 */ 2888 #define I2C_S_TCF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_TCF_SHIFT)) & I2C_S_TCF_MASK) 2889 /*! @} */ 2890 2891 /*! @name D - I2C Data I/O register */ 2892 /*! @{ */ 2893 #define I2C_D_DATA_MASK (0xFFU) 2894 #define I2C_D_DATA_SHIFT (0U) 2895 #define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x)) << I2C_D_DATA_SHIFT)) & I2C_D_DATA_MASK) 2896 /*! @} */ 2897 2898 /*! @name C2 - I2C Control Register 2 */ 2899 /*! @{ */ 2900 #define I2C_C2_AD_MASK (0x7U) 2901 #define I2C_C2_AD_SHIFT (0U) 2902 #define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_AD_SHIFT)) & I2C_C2_AD_MASK) 2903 #define I2C_C2_RMEN_MASK (0x8U) 2904 #define I2C_C2_RMEN_SHIFT (3U) 2905 /*! RMEN - Range Address Matching Enable 2906 * 0b0..Range mode disabled. No address matching occurs for an address within the range of values of the A1 and RA registers. 2907 * 0b1..Range mode enabled. Address matching occurs when a slave receives an address within the range of values of the A1 and RA registers. 2908 */ 2909 #define I2C_C2_RMEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_RMEN_SHIFT)) & I2C_C2_RMEN_MASK) 2910 #define I2C_C2_SBRC_MASK (0x10U) 2911 #define I2C_C2_SBRC_SHIFT (4U) 2912 /*! SBRC - Slave Baud Rate Control 2913 * 0b0..The slave baud rate follows the master baud rate and clock stretching may occur 2914 * 0b1..Slave baud rate is independent of the master baud rate 2915 */ 2916 #define I2C_C2_SBRC(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_SBRC_SHIFT)) & I2C_C2_SBRC_MASK) 2917 #define I2C_C2_ADEXT_MASK (0x40U) 2918 #define I2C_C2_ADEXT_SHIFT (6U) 2919 /*! ADEXT - Address Extension 2920 * 0b0..7-bit address scheme 2921 * 0b1..10-bit address scheme 2922 */ 2923 #define I2C_C2_ADEXT(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_ADEXT_SHIFT)) & I2C_C2_ADEXT_MASK) 2924 #define I2C_C2_GCAEN_MASK (0x80U) 2925 #define I2C_C2_GCAEN_SHIFT (7U) 2926 /*! GCAEN - General Call Address Enable 2927 * 0b0..Disabled 2928 * 0b1..Enabled 2929 */ 2930 #define I2C_C2_GCAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_GCAEN_SHIFT)) & I2C_C2_GCAEN_MASK) 2931 /*! @} */ 2932 2933 /*! @name FLT - I2C Programmable Input Glitch Filter register */ 2934 /*! @{ */ 2935 #define I2C_FLT_FLT_MASK (0xFU) 2936 #define I2C_FLT_FLT_SHIFT (0U) 2937 /*! FLT - I2C Programmable Filter Factor 2938 * 0b0000..No filter/bypass 2939 */ 2940 #define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_FLT_SHIFT)) & I2C_FLT_FLT_MASK) 2941 #define I2C_FLT_STARTF_MASK (0x10U) 2942 #define I2C_FLT_STARTF_SHIFT (4U) 2943 /*! STARTF - I2C Bus Start Detect Flag 2944 * 0b0..No start happens on I2C bus 2945 * 0b1..Start detected on I2C bus 2946 */ 2947 #define I2C_FLT_STARTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STARTF_SHIFT)) & I2C_FLT_STARTF_MASK) 2948 #define I2C_FLT_SSIE_MASK (0x20U) 2949 #define I2C_FLT_SSIE_SHIFT (5U) 2950 /*! SSIE - I2C Bus Stop or Start Interrupt Enable 2951 * 0b0..Stop or start detection interrupt is disabled 2952 * 0b1..Stop or start detection interrupt is enabled 2953 */ 2954 #define I2C_FLT_SSIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SSIE_SHIFT)) & I2C_FLT_SSIE_MASK) 2955 #define I2C_FLT_STOPF_MASK (0x40U) 2956 #define I2C_FLT_STOPF_SHIFT (6U) 2957 /*! STOPF - I2C Bus Stop Detect Flag 2958 * 0b0..No stop happens on I2C bus 2959 * 0b1..Stop detected on I2C bus 2960 */ 2961 #define I2C_FLT_STOPF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STOPF_SHIFT)) & I2C_FLT_STOPF_MASK) 2962 #define I2C_FLT_SHEN_MASK (0x80U) 2963 #define I2C_FLT_SHEN_SHIFT (7U) 2964 /*! SHEN - Stop Hold Enable 2965 * 0b0..Stop holdoff is disabled. The MCU's entry to stop mode is not gated. 2966 * 0b1..Stop holdoff is enabled. 2967 */ 2968 #define I2C_FLT_SHEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SHEN_SHIFT)) & I2C_FLT_SHEN_MASK) 2969 /*! @} */ 2970 2971 /*! @name RA - I2C Range Address register */ 2972 /*! @{ */ 2973 #define I2C_RA_RAD_MASK (0xFEU) 2974 #define I2C_RA_RAD_SHIFT (1U) 2975 #define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_RA_RAD_SHIFT)) & I2C_RA_RAD_MASK) 2976 /*! @} */ 2977 2978 /*! @name SMB - I2C SMBus Control and Status register */ 2979 /*! @{ */ 2980 #define I2C_SMB_SHTF2IE_MASK (0x1U) 2981 #define I2C_SMB_SHTF2IE_SHIFT (0U) 2982 /*! SHTF2IE - SHTF2 Interrupt Enable 2983 * 0b0..SHTF2 interrupt is disabled 2984 * 0b1..SHTF2 interrupt is enabled 2985 */ 2986 #define I2C_SMB_SHTF2IE(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2IE_SHIFT)) & I2C_SMB_SHTF2IE_MASK) 2987 #define I2C_SMB_SHTF2_MASK (0x2U) 2988 #define I2C_SMB_SHTF2_SHIFT (1U) 2989 /*! SHTF2 - SCL High Timeout Flag 2 2990 * 0b0..No SCL high and SDA low timeout occurs 2991 * 0b1..SCL high and SDA low timeout occurs 2992 */ 2993 #define I2C_SMB_SHTF2(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2_SHIFT)) & I2C_SMB_SHTF2_MASK) 2994 #define I2C_SMB_SHTF1_MASK (0x4U) 2995 #define I2C_SMB_SHTF1_SHIFT (2U) 2996 /*! SHTF1 - SCL High Timeout Flag 1 2997 * 0b0..No SCL high and SDA high timeout occurs 2998 * 0b1..SCL high and SDA high timeout occurs 2999 */ 3000 #define I2C_SMB_SHTF1(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF1_SHIFT)) & I2C_SMB_SHTF1_MASK) 3001 #define I2C_SMB_SLTF_MASK (0x8U) 3002 #define I2C_SMB_SLTF_SHIFT (3U) 3003 /*! SLTF - SCL Low Timeout Flag 3004 * 0b0..No low timeout occurs 3005 * 0b1..Low timeout occurs 3006 */ 3007 #define I2C_SMB_SLTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SLTF_SHIFT)) & I2C_SMB_SLTF_MASK) 3008 #define I2C_SMB_TCKSEL_MASK (0x10U) 3009 #define I2C_SMB_TCKSEL_SHIFT (4U) 3010 /*! TCKSEL - Timeout Counter Clock Select 3011 * 0b0..Timeout counter counts at the frequency of the I2C module clock / 64 3012 * 0b1..Timeout counter counts at the frequency of the I2C module clock 3013 */ 3014 #define I2C_SMB_TCKSEL(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_TCKSEL_SHIFT)) & I2C_SMB_TCKSEL_MASK) 3015 #define I2C_SMB_SIICAEN_MASK (0x20U) 3016 #define I2C_SMB_SIICAEN_SHIFT (5U) 3017 /*! SIICAEN - Second I2C Address Enable 3018 * 0b0..I2C address register 2 matching is disabled 3019 * 0b1..I2C address register 2 matching is enabled 3020 */ 3021 #define I2C_SMB_SIICAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SIICAEN_SHIFT)) & I2C_SMB_SIICAEN_MASK) 3022 #define I2C_SMB_ALERTEN_MASK (0x40U) 3023 #define I2C_SMB_ALERTEN_SHIFT (6U) 3024 /*! ALERTEN - SMBus Alert Response Address Enable 3025 * 0b0..SMBus alert response address matching is disabled 3026 * 0b1..SMBus alert response address matching is enabled 3027 */ 3028 #define I2C_SMB_ALERTEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_ALERTEN_SHIFT)) & I2C_SMB_ALERTEN_MASK) 3029 #define I2C_SMB_FACK_MASK (0x80U) 3030 #define I2C_SMB_FACK_SHIFT (7U) 3031 /*! FACK - Fast NACK/ACK Enable 3032 * 0b0..An ACK or NACK is sent on the following receiving data byte 3033 * 0b1..Writing 0 to TXAK after receiving a data byte generates an ACK. Writing 1 to TXAK after receiving a data byte generates a NACK. 3034 */ 3035 #define I2C_SMB_FACK(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_FACK_SHIFT)) & I2C_SMB_FACK_MASK) 3036 /*! @} */ 3037 3038 /*! @name A2 - I2C Address Register 2 */ 3039 /*! @{ */ 3040 #define I2C_A2_SAD_MASK (0xFEU) 3041 #define I2C_A2_SAD_SHIFT (1U) 3042 #define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A2_SAD_SHIFT)) & I2C_A2_SAD_MASK) 3043 /*! @} */ 3044 3045 /*! @name SLTH - I2C SCL Low Timeout Register High */ 3046 /*! @{ */ 3047 #define I2C_SLTH_SSLT_MASK (0xFFU) 3048 #define I2C_SLTH_SSLT_SHIFT (0U) 3049 #define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTH_SSLT_SHIFT)) & I2C_SLTH_SSLT_MASK) 3050 /*! @} */ 3051 3052 /*! @name SLTL - I2C SCL Low Timeout Register Low */ 3053 /*! @{ */ 3054 #define I2C_SLTL_SSLT_MASK (0xFFU) 3055 #define I2C_SLTL_SSLT_SHIFT (0U) 3056 #define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTL_SSLT_SHIFT)) & I2C_SLTL_SSLT_MASK) 3057 /*! @} */ 3058 3059 3060 /*! 3061 * @} 3062 */ /* end of group I2C_Register_Masks */ 3063 3064 3065 /* I2C - Peripheral instance base addresses */ 3066 /** Peripheral I2C0 base address */ 3067 #define I2C0_BASE (0x40066000u) 3068 /** Peripheral I2C0 base pointer */ 3069 #define I2C0 ((I2C_Type *)I2C0_BASE) 3070 /** Array initializer of I2C peripheral base addresses */ 3071 #define I2C_BASE_ADDRS { I2C0_BASE } 3072 /** Array initializer of I2C peripheral base pointers */ 3073 #define I2C_BASE_PTRS { I2C0 } 3074 /** Interrupt vectors for the I2C peripheral type */ 3075 #define I2C_IRQS { I2C0_IRQn } 3076 3077 /*! 3078 * @} 3079 */ /* end of group I2C_Peripheral_Access_Layer */ 3080 3081 3082 /* ---------------------------------------------------------------------------- 3083 -- ICS Peripheral Access Layer 3084 ---------------------------------------------------------------------------- */ 3085 3086 /*! 3087 * @addtogroup ICS_Peripheral_Access_Layer ICS Peripheral Access Layer 3088 * @{ 3089 */ 3090 3091 /** ICS - Register Layout Typedef */ 3092 typedef struct { 3093 __IO uint8_t C1; /**< ICS Control Register 1, offset: 0x0 */ 3094 __IO uint8_t C2; /**< ICS Control Register 2, offset: 0x1 */ 3095 __IO uint8_t C3; /**< ICS Control Register 3, offset: 0x2 */ 3096 __IO uint8_t C4; /**< ICS Control Register 4, offset: 0x3 */ 3097 __IO uint8_t S; /**< ICS Status Register, offset: 0x4 */ 3098 } ICS_Type; 3099 3100 /* ---------------------------------------------------------------------------- 3101 -- ICS Register Masks 3102 ---------------------------------------------------------------------------- */ 3103 3104 /*! 3105 * @addtogroup ICS_Register_Masks ICS Register Masks 3106 * @{ 3107 */ 3108 3109 /*! @name C1 - ICS Control Register 1 */ 3110 /*! @{ */ 3111 #define ICS_C1_IREFSTEN_MASK (0x1U) 3112 #define ICS_C1_IREFSTEN_SHIFT (0U) 3113 /*! IREFSTEN - Internal Reference Stop Enable 3114 * 0b0..Internal reference clock is disabled in Stop mode. 3115 * 0b1..Internal reference clock stays enabled in Stop mode if IRCLKEN is set, or if ICS is in FEI, FBI, or FBILP mode before entering Stop. 3116 */ 3117 #define ICS_C1_IREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << ICS_C1_IREFSTEN_SHIFT)) & ICS_C1_IREFSTEN_MASK) 3118 #define ICS_C1_IRCLKEN_MASK (0x2U) 3119 #define ICS_C1_IRCLKEN_SHIFT (1U) 3120 /*! IRCLKEN - Internal Reference Clock Enable 3121 * 0b0..ICSIRCLK is inactive. 3122 * 0b1..ICSIRCLK is active. 3123 */ 3124 #define ICS_C1_IRCLKEN(x) (((uint8_t)(((uint8_t)(x)) << ICS_C1_IRCLKEN_SHIFT)) & ICS_C1_IRCLKEN_MASK) 3125 #define ICS_C1_IREFS_MASK (0x4U) 3126 #define ICS_C1_IREFS_SHIFT (2U) 3127 /*! IREFS - Internal Reference Select 3128 * 0b0..External reference clock is selected. 3129 * 0b1..Internal reference clock is selected. 3130 */ 3131 #define ICS_C1_IREFS(x) (((uint8_t)(((uint8_t)(x)) << ICS_C1_IREFS_SHIFT)) & ICS_C1_IREFS_MASK) 3132 #define ICS_C1_RDIV_MASK (0x38U) 3133 #define ICS_C1_RDIV_SHIFT (3U) 3134 #define ICS_C1_RDIV(x) (((uint8_t)(((uint8_t)(x)) << ICS_C1_RDIV_SHIFT)) & ICS_C1_RDIV_MASK) 3135 #define ICS_C1_CLKS_MASK (0xC0U) 3136 #define ICS_C1_CLKS_SHIFT (6U) 3137 /*! CLKS - Clock Source Select 3138 * 0b00..Output of FLL is selected. 3139 * 0b01..Internal reference clock is selected. 3140 * 0b10..External reference clock is selected. 3141 * 0b11..Reserved, defaults to 00. 3142 */ 3143 #define ICS_C1_CLKS(x) (((uint8_t)(((uint8_t)(x)) << ICS_C1_CLKS_SHIFT)) & ICS_C1_CLKS_MASK) 3144 /*! @} */ 3145 3146 /*! @name C2 - ICS Control Register 2 */ 3147 /*! @{ */ 3148 #define ICS_C2_LP_MASK (0x10U) 3149 #define ICS_C2_LP_SHIFT (4U) 3150 /*! LP - Low Power Select 3151 * 0b0..FLL is not disabled in bypass mode. 3152 * 0b1..FLL is disabled in bypass modes unless debug is active. 3153 */ 3154 #define ICS_C2_LP(x) (((uint8_t)(((uint8_t)(x)) << ICS_C2_LP_SHIFT)) & ICS_C2_LP_MASK) 3155 #define ICS_C2_BDIV_MASK (0xE0U) 3156 #define ICS_C2_BDIV_SHIFT (5U) 3157 /*! BDIV - Bus Frequency Divider 3158 * 0b000..Encoding 0-Divides the selected clock by 1. 3159 * 0b001..Encoding 1-Divides the selected clock by 2 (reset default). 3160 * 0b010..Encoding 2-Divides the selected clock by 4. 3161 * 0b011..Encoding 3-Divides the selected clock by 8. 3162 * 0b100..Encoding 4-Divides the selected clock by 16. 3163 * 0b101..Encoding 5-Divides the selected clock by 32. 3164 * 0b110..Encoding 6-Divides the selected clock by 64. 3165 * 0b111..Encoding 7-Divides the selected clock by 128. 3166 */ 3167 #define ICS_C2_BDIV(x) (((uint8_t)(((uint8_t)(x)) << ICS_C2_BDIV_SHIFT)) & ICS_C2_BDIV_MASK) 3168 /*! @} */ 3169 3170 /*! @name C3 - ICS Control Register 3 */ 3171 /*! @{ */ 3172 #define ICS_C3_SCTRIM_MASK (0xFFU) 3173 #define ICS_C3_SCTRIM_SHIFT (0U) 3174 #define ICS_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x)) << ICS_C3_SCTRIM_SHIFT)) & ICS_C3_SCTRIM_MASK) 3175 /*! @} */ 3176 3177 /*! @name C4 - ICS Control Register 4 */ 3178 /*! @{ */ 3179 #define ICS_C4_SCFTRIM_MASK (0x1U) 3180 #define ICS_C4_SCFTRIM_SHIFT (0U) 3181 #define ICS_C4_SCFTRIM(x) (((uint8_t)(((uint8_t)(x)) << ICS_C4_SCFTRIM_SHIFT)) & ICS_C4_SCFTRIM_MASK) 3182 #define ICS_C4_CME_MASK (0x20U) 3183 #define ICS_C4_CME_SHIFT (5U) 3184 /*! CME - Clock Monitor Enable 3185 * 0b0..Clock monitor is disabled. 3186 * 0b1..Generates a reset request on loss of external clock. 3187 */ 3188 #define ICS_C4_CME(x) (((uint8_t)(((uint8_t)(x)) << ICS_C4_CME_SHIFT)) & ICS_C4_CME_MASK) 3189 #define ICS_C4_LOLIE_MASK (0x80U) 3190 #define ICS_C4_LOLIE_SHIFT (7U) 3191 /*! LOLIE - Loss of Lock Interrupt 3192 * 0b0..No request on loss of lock. 3193 * 0b1..Generates an interrupt request on loss of lock. 3194 */ 3195 #define ICS_C4_LOLIE(x) (((uint8_t)(((uint8_t)(x)) << ICS_C4_LOLIE_SHIFT)) & ICS_C4_LOLIE_MASK) 3196 /*! @} */ 3197 3198 /*! @name S - ICS Status Register */ 3199 /*! @{ */ 3200 #define ICS_S_CLKST_MASK (0xCU) 3201 #define ICS_S_CLKST_SHIFT (2U) 3202 /*! CLKST - Clock Mode Status 3203 * 0b00..Output of FLL is selected. 3204 * 0b01..FLL Bypassed, internal reference clock is selected. 3205 * 0b10..FLL Bypassed, external reference clock is selected. 3206 * 0b11..Reserved. 3207 */ 3208 #define ICS_S_CLKST(x) (((uint8_t)(((uint8_t)(x)) << ICS_S_CLKST_SHIFT)) & ICS_S_CLKST_MASK) 3209 #define ICS_S_IREFST_MASK (0x10U) 3210 #define ICS_S_IREFST_SHIFT (4U) 3211 /*! IREFST - Internal Reference Status 3212 * 0b0..Source of reference clock is external clock. 3213 * 0b1..Source of reference clock is internal clock. 3214 */ 3215 #define ICS_S_IREFST(x) (((uint8_t)(((uint8_t)(x)) << ICS_S_IREFST_SHIFT)) & ICS_S_IREFST_MASK) 3216 #define ICS_S_LOCK_MASK (0x40U) 3217 #define ICS_S_LOCK_SHIFT (6U) 3218 /*! LOCK - Lock Status 3219 * 0b0..FLL is currently unlocked. 3220 * 0b1..FLL is currently locked. 3221 */ 3222 #define ICS_S_LOCK(x) (((uint8_t)(((uint8_t)(x)) << ICS_S_LOCK_SHIFT)) & ICS_S_LOCK_MASK) 3223 #define ICS_S_LOLS_MASK (0x80U) 3224 #define ICS_S_LOLS_SHIFT (7U) 3225 /*! LOLS - Loss of Lock Status 3226 * 0b0..FLL has not lost lock since LOLS was last cleared. 3227 * 0b1..FLL has lost lock since LOLS was last cleared. 3228 */ 3229 #define ICS_S_LOLS(x) (((uint8_t)(((uint8_t)(x)) << ICS_S_LOLS_SHIFT)) & ICS_S_LOLS_MASK) 3230 /*! @} */ 3231 3232 3233 /*! 3234 * @} 3235 */ /* end of group ICS_Register_Masks */ 3236 3237 3238 /* ICS - Peripheral instance base addresses */ 3239 /** Peripheral ICS base address */ 3240 #define ICS_BASE (0x40064000u) 3241 /** Peripheral ICS base pointer */ 3242 #define ICS ((ICS_Type *)ICS_BASE) 3243 /** Array initializer of ICS peripheral base addresses */ 3244 #define ICS_BASE_ADDRS { ICS_BASE } 3245 /** Array initializer of ICS peripheral base pointers */ 3246 #define ICS_BASE_PTRS { ICS } 3247 /** Interrupt vectors for the ICS peripheral type */ 3248 #define ICS_IRQS { ICS_IRQn } 3249 3250 /*! 3251 * @} 3252 */ /* end of group ICS_Peripheral_Access_Layer */ 3253 3254 3255 /* ---------------------------------------------------------------------------- 3256 -- IRQ Peripheral Access Layer 3257 ---------------------------------------------------------------------------- */ 3258 3259 /*! 3260 * @addtogroup IRQ_Peripheral_Access_Layer IRQ Peripheral Access Layer 3261 * @{ 3262 */ 3263 3264 /** IRQ - Register Layout Typedef */ 3265 typedef struct { 3266 __IO uint8_t SC; /**< Interrupt Pin Request Status and Control Register, offset: 0x0 */ 3267 } IRQ_Type; 3268 3269 /* ---------------------------------------------------------------------------- 3270 -- IRQ Register Masks 3271 ---------------------------------------------------------------------------- */ 3272 3273 /*! 3274 * @addtogroup IRQ_Register_Masks IRQ Register Masks 3275 * @{ 3276 */ 3277 3278 /*! @name SC - Interrupt Pin Request Status and Control Register */ 3279 /*! @{ */ 3280 #define IRQ_SC_IRQMOD_MASK (0x1U) 3281 #define IRQ_SC_IRQMOD_SHIFT (0U) 3282 /*! IRQMOD - IRQ Detection Mode 3283 * 0b0..IRQ event is detected only on falling/rising edges. 3284 * 0b1..IRQ event is detected on falling/rising edges and low/high levels. 3285 */ 3286 #define IRQ_SC_IRQMOD(x) (((uint8_t)(((uint8_t)(x)) << IRQ_SC_IRQMOD_SHIFT)) & IRQ_SC_IRQMOD_MASK) 3287 #define IRQ_SC_IRQIE_MASK (0x2U) 3288 #define IRQ_SC_IRQIE_SHIFT (1U) 3289 /*! IRQIE - IRQ Interrupt Enable 3290 * 0b0..Interrupt request when IRQF set is disabled (use polling). 3291 * 0b1..Interrupt requested whenever IRQF = 1. 3292 */ 3293 #define IRQ_SC_IRQIE(x) (((uint8_t)(((uint8_t)(x)) << IRQ_SC_IRQIE_SHIFT)) & IRQ_SC_IRQIE_MASK) 3294 #define IRQ_SC_IRQACK_MASK (0x4U) 3295 #define IRQ_SC_IRQACK_SHIFT (2U) 3296 #define IRQ_SC_IRQACK(x) (((uint8_t)(((uint8_t)(x)) << IRQ_SC_IRQACK_SHIFT)) & IRQ_SC_IRQACK_MASK) 3297 #define IRQ_SC_IRQF_MASK (0x8U) 3298 #define IRQ_SC_IRQF_SHIFT (3U) 3299 /*! IRQF - IRQ Flag 3300 * 0b0..No IRQ request 3301 * 0b1..IRQ event is detected. 3302 */ 3303 #define IRQ_SC_IRQF(x) (((uint8_t)(((uint8_t)(x)) << IRQ_SC_IRQF_SHIFT)) & IRQ_SC_IRQF_MASK) 3304 #define IRQ_SC_IRQPE_MASK (0x10U) 3305 #define IRQ_SC_IRQPE_SHIFT (4U) 3306 /*! IRQPE - IRQ Pin Enable 3307 * 0b0..IRQ pin function is disabled. 3308 * 0b1..IRQ pin function is enabled. 3309 */ 3310 #define IRQ_SC_IRQPE(x) (((uint8_t)(((uint8_t)(x)) << IRQ_SC_IRQPE_SHIFT)) & IRQ_SC_IRQPE_MASK) 3311 #define IRQ_SC_IRQEDG_MASK (0x20U) 3312 #define IRQ_SC_IRQEDG_SHIFT (5U) 3313 /*! IRQEDG - Interrupt Request (IRQ) Edge Select 3314 * 0b0..IRQ is falling-edge or falling-edge/low-level sensitive. 3315 * 0b1..IRQ is rising-edge or rising-edge/high-level sensitive. 3316 */ 3317 #define IRQ_SC_IRQEDG(x) (((uint8_t)(((uint8_t)(x)) << IRQ_SC_IRQEDG_SHIFT)) & IRQ_SC_IRQEDG_MASK) 3318 #define IRQ_SC_IRQPDD_MASK (0x40U) 3319 #define IRQ_SC_IRQPDD_SHIFT (6U) 3320 /*! IRQPDD - Interrupt Request (IRQ) Pull Device Disable 3321 * 0b0..IRQ pull device enabled if IRQPE = 1. 3322 * 0b1..IRQ pull device disabled if IRQPE = 1. 3323 */ 3324 #define IRQ_SC_IRQPDD(x) (((uint8_t)(((uint8_t)(x)) << IRQ_SC_IRQPDD_SHIFT)) & IRQ_SC_IRQPDD_MASK) 3325 /*! @} */ 3326 3327 3328 /*! 3329 * @} 3330 */ /* end of group IRQ_Register_Masks */ 3331 3332 3333 /* IRQ - Peripheral instance base addresses */ 3334 /** Peripheral IRQ base address */ 3335 #define IRQ_BASE (0x40031000u) 3336 /** Peripheral IRQ base pointer */ 3337 #define IRQ ((IRQ_Type *)IRQ_BASE) 3338 /** Array initializer of IRQ peripheral base addresses */ 3339 #define IRQ_BASE_ADDRS { IRQ_BASE } 3340 /** Array initializer of IRQ peripheral base pointers */ 3341 #define IRQ_BASE_PTRS { IRQ } 3342 3343 /*! 3344 * @} 3345 */ /* end of group IRQ_Peripheral_Access_Layer */ 3346 3347 3348 /* ---------------------------------------------------------------------------- 3349 -- KBI Peripheral Access Layer 3350 ---------------------------------------------------------------------------- */ 3351 3352 /*! 3353 * @addtogroup KBI_Peripheral_Access_Layer KBI Peripheral Access Layer 3354 * @{ 3355 */ 3356 3357 /** KBI - Register Layout Typedef */ 3358 typedef struct { 3359 __IO uint8_t SC; /**< KBI Status and Control Register, offset: 0x0 */ 3360 __IO uint8_t PE; /**< KBIx Pin Enable Register, offset: 0x1 */ 3361 __IO uint8_t ES; /**< KBIx Edge Select Register, offset: 0x2 */ 3362 } KBI_Type; 3363 3364 /* ---------------------------------------------------------------------------- 3365 -- KBI Register Masks 3366 ---------------------------------------------------------------------------- */ 3367 3368 /*! 3369 * @addtogroup KBI_Register_Masks KBI Register Masks 3370 * @{ 3371 */ 3372 3373 /*! @name SC - KBI Status and Control Register */ 3374 /*! @{ */ 3375 #define KBI_SC_KBMOD_MASK (0x1U) 3376 #define KBI_SC_KBMOD_SHIFT (0U) 3377 /*! KBMOD - KBI Detection Mode 3378 * 0b0..Keyboard detects edges only. 3379 * 0b1..Keyboard detects both edges and levels. 3380 */ 3381 #define KBI_SC_KBMOD(x) (((uint8_t)(((uint8_t)(x)) << KBI_SC_KBMOD_SHIFT)) & KBI_SC_KBMOD_MASK) 3382 #define KBI_SC_KBIE_MASK (0x2U) 3383 #define KBI_SC_KBIE_SHIFT (1U) 3384 /*! KBIE - KBI Interrupt Enable 3385 * 0b0..KBI interrupt not enabled. 3386 * 0b1..KBI interrupt enabled. 3387 */ 3388 #define KBI_SC_KBIE(x) (((uint8_t)(((uint8_t)(x)) << KBI_SC_KBIE_SHIFT)) & KBI_SC_KBIE_MASK) 3389 #define KBI_SC_KBACK_MASK (0x4U) 3390 #define KBI_SC_KBACK_SHIFT (2U) 3391 #define KBI_SC_KBACK(x) (((uint8_t)(((uint8_t)(x)) << KBI_SC_KBACK_SHIFT)) & KBI_SC_KBACK_MASK) 3392 #define KBI_SC_KBF_MASK (0x8U) 3393 #define KBI_SC_KBF_SHIFT (3U) 3394 /*! KBF - KBI Interrupt Flag 3395 * 0b0..KBI interrupt request not detected. 3396 * 0b1..KBI interrupt request detected. 3397 */ 3398 #define KBI_SC_KBF(x) (((uint8_t)(((uint8_t)(x)) << KBI_SC_KBF_SHIFT)) & KBI_SC_KBF_MASK) 3399 /*! @} */ 3400 3401 /*! @name PE - KBIx Pin Enable Register */ 3402 /*! @{ */ 3403 #define KBI_PE_KBIPE_MASK (0xFFU) 3404 #define KBI_PE_KBIPE_SHIFT (0U) 3405 /*! KBIPE - KBI Pin Enables 3406 * 0b00000000..Pin is not enabled as KBI interrupt. 3407 * 0b00000001..Pin is enabled as KBI interrupt. 3408 */ 3409 #define KBI_PE_KBIPE(x) (((uint8_t)(((uint8_t)(x)) << KBI_PE_KBIPE_SHIFT)) & KBI_PE_KBIPE_MASK) 3410 /*! @} */ 3411 3412 /*! @name ES - KBIx Edge Select Register */ 3413 /*! @{ */ 3414 #define KBI_ES_KBEDG_MASK (0xFFU) 3415 #define KBI_ES_KBEDG_SHIFT (0U) 3416 /*! KBEDG - KBI Edge Selects 3417 * 0b00000000..Falling edge/low level. 3418 * 0b00000001..Rising edge/high level. 3419 */ 3420 #define KBI_ES_KBEDG(x) (((uint8_t)(((uint8_t)(x)) << KBI_ES_KBEDG_SHIFT)) & KBI_ES_KBEDG_MASK) 3421 /*! @} */ 3422 3423 3424 /*! 3425 * @} 3426 */ /* end of group KBI_Register_Masks */ 3427 3428 3429 /* KBI - Peripheral instance base addresses */ 3430 /** Peripheral KBI0 base address */ 3431 #define KBI0_BASE (0x40079000u) 3432 /** Peripheral KBI0 base pointer */ 3433 #define KBI0 ((KBI_Type *)KBI0_BASE) 3434 /** Peripheral KBI1 base address */ 3435 #define KBI1_BASE (0x4007A000u) 3436 /** Peripheral KBI1 base pointer */ 3437 #define KBI1 ((KBI_Type *)KBI1_BASE) 3438 /** Array initializer of KBI peripheral base addresses */ 3439 #define KBI_BASE_ADDRS { KBI0_BASE, KBI1_BASE } 3440 /** Array initializer of KBI peripheral base pointers */ 3441 #define KBI_BASE_PTRS { KBI0, KBI1 } 3442 /** Interrupt vectors for the KBI peripheral type */ 3443 #define KBI_IRQS { KBI0_IRQn, KBI1_IRQn } 3444 3445 /*! 3446 * @} 3447 */ /* end of group KBI_Peripheral_Access_Layer */ 3448 3449 3450 /* ---------------------------------------------------------------------------- 3451 -- MCM Peripheral Access Layer 3452 ---------------------------------------------------------------------------- */ 3453 3454 /*! 3455 * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer 3456 * @{ 3457 */ 3458 3459 /** MCM - Register Layout Typedef */ 3460 typedef struct { 3461 uint8_t RESERVED_0[8]; 3462 __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */ 3463 __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */ 3464 __IO uint32_t PLACR; /**< Platform Control Register, offset: 0xC */ 3465 } MCM_Type; 3466 3467 /* ---------------------------------------------------------------------------- 3468 -- MCM Register Masks 3469 ---------------------------------------------------------------------------- */ 3470 3471 /*! 3472 * @addtogroup MCM_Register_Masks MCM Register Masks 3473 * @{ 3474 */ 3475 3476 /*! @name PLASC - Crossbar Switch (AXBS) Slave Configuration */ 3477 /*! @{ */ 3478 #define MCM_PLASC_ASC_MASK (0xFFU) 3479 #define MCM_PLASC_ASC_SHIFT (0U) 3480 /*! ASC - Each bit in the ASC field indicates whether there is a corresponding connection to the crossbar switch's slave input port. 3481 * 0b00000000..A bus slave connection to AXBS input port n is absent. 3482 * 0b00000001..A bus slave connection to AXBS input port n is present. 3483 */ 3484 #define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK) 3485 /*! @} */ 3486 3487 /*! @name PLAMC - Crossbar Switch (AXBS) Master Configuration */ 3488 /*! @{ */ 3489 #define MCM_PLAMC_AMC_MASK (0xFFU) 3490 #define MCM_PLAMC_AMC_SHIFT (0U) 3491 /*! AMC - Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port. 3492 * 0b00000000..A bus master connection to AXBS input port n is absent 3493 * 0b00000001..A bus master connection to AXBS input port n is present 3494 */ 3495 #define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK) 3496 /*! @} */ 3497 3498 /*! @name PLACR - Platform Control Register */ 3499 /*! @{ */ 3500 #define MCM_PLACR_CFCC_MASK (0x400U) 3501 #define MCM_PLACR_CFCC_SHIFT (10U) 3502 #define MCM_PLACR_CFCC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_CFCC_SHIFT)) & MCM_PLACR_CFCC_MASK) 3503 #define MCM_PLACR_DFCDA_MASK (0x800U) 3504 #define MCM_PLACR_DFCDA_SHIFT (11U) 3505 /*! DFCDA - Disable Flash Controller Data Caching 3506 * 0b0..Enable flash controller data caching 3507 * 0b1..Disable flash controller data caching. 3508 */ 3509 #define MCM_PLACR_DFCDA(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCDA_SHIFT)) & MCM_PLACR_DFCDA_MASK) 3510 #define MCM_PLACR_DFCIC_MASK (0x1000U) 3511 #define MCM_PLACR_DFCIC_SHIFT (12U) 3512 /*! DFCIC - Disable Flash Controller Instruction Caching 3513 * 0b0..Enable flash controller instruction caching. 3514 * 0b1..Disable flash controller instruction caching. 3515 */ 3516 #define MCM_PLACR_DFCIC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCIC_SHIFT)) & MCM_PLACR_DFCIC_MASK) 3517 #define MCM_PLACR_DFCC_MASK (0x2000U) 3518 #define MCM_PLACR_DFCC_SHIFT (13U) 3519 /*! DFCC - Disable Flash Controller Cache 3520 * 0b0..Enable flash controller cache. 3521 * 0b1..Disable flash controller cache. 3522 */ 3523 #define MCM_PLACR_DFCC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCC_SHIFT)) & MCM_PLACR_DFCC_MASK) 3524 #define MCM_PLACR_EFDS_MASK (0x4000U) 3525 #define MCM_PLACR_EFDS_SHIFT (14U) 3526 /*! EFDS - Enable Flash Data Speculation 3527 * 0b0..Disable flash data speculation. 3528 * 0b1..Enable flash data speculation. 3529 */ 3530 #define MCM_PLACR_EFDS(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_EFDS_SHIFT)) & MCM_PLACR_EFDS_MASK) 3531 #define MCM_PLACR_DFCS_MASK (0x8000U) 3532 #define MCM_PLACR_DFCS_SHIFT (15U) 3533 /*! DFCS - Disable Flash Controller Speculation 3534 * 0b0..Enable flash controller speculation. 3535 * 0b1..Disable flash controller speculation. 3536 */ 3537 #define MCM_PLACR_DFCS(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCS_SHIFT)) & MCM_PLACR_DFCS_MASK) 3538 #define MCM_PLACR_ESFC_MASK (0x10000U) 3539 #define MCM_PLACR_ESFC_SHIFT (16U) 3540 /*! ESFC - Enable Stalling Flash Controller 3541 * 0b0..Disable stalling flash controller when flash is busy. 3542 * 0b1..Enable stalling flash controller when flash is busy. 3543 */ 3544 #define MCM_PLACR_ESFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_ESFC_SHIFT)) & MCM_PLACR_ESFC_MASK) 3545 /*! @} */ 3546 3547 3548 /*! 3549 * @} 3550 */ /* end of group MCM_Register_Masks */ 3551 3552 3553 /* MCM - Peripheral instance base addresses */ 3554 /** Peripheral MCM base address */ 3555 #define MCM_BASE (0xF0003000u) 3556 /** Peripheral MCM base pointer */ 3557 #define MCM ((MCM_Type *)MCM_BASE) 3558 /** Array initializer of MCM peripheral base addresses */ 3559 #define MCM_BASE_ADDRS { MCM_BASE } 3560 /** Array initializer of MCM peripheral base pointers */ 3561 #define MCM_BASE_PTRS { MCM } 3562 3563 /*! 3564 * @} 3565 */ /* end of group MCM_Peripheral_Access_Layer */ 3566 3567 3568 /* ---------------------------------------------------------------------------- 3569 -- OSC Peripheral Access Layer 3570 ---------------------------------------------------------------------------- */ 3571 3572 /*! 3573 * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer 3574 * @{ 3575 */ 3576 3577 /** OSC - Register Layout Typedef */ 3578 typedef struct { 3579 __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */ 3580 } OSC_Type; 3581 3582 /* ---------------------------------------------------------------------------- 3583 -- OSC Register Masks 3584 ---------------------------------------------------------------------------- */ 3585 3586 /*! 3587 * @addtogroup OSC_Register_Masks OSC Register Masks 3588 * @{ 3589 */ 3590 3591 /*! @name CR - OSC Control Register */ 3592 /*! @{ */ 3593 #define OSC_CR_OSCINIT_MASK (0x1U) 3594 #define OSC_CR_OSCINIT_SHIFT (0U) 3595 /*! OSCINIT - OSC Initialization 3596 * 0b0..Oscillator initialization is not complete. 3597 * 0b1..Oscillator initialization is completed. 3598 */ 3599 #define OSC_CR_OSCINIT(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_OSCINIT_SHIFT)) & OSC_CR_OSCINIT_MASK) 3600 #define OSC_CR_HGO_MASK (0x2U) 3601 #define OSC_CR_HGO_SHIFT (1U) 3602 /*! HGO - High Gain Oscillator Select 3603 * 0b0..Low-power mode 3604 * 0b1..High-gain mode 3605 */ 3606 #define OSC_CR_HGO(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_HGO_SHIFT)) & OSC_CR_HGO_MASK) 3607 #define OSC_CR_RANGE_MASK (0x4U) 3608 #define OSC_CR_RANGE_SHIFT (2U) 3609 /*! RANGE - Frequency Range Select 3610 * 0b0..Low frequency range of 32 kHz. 3611 * 0b1..High frequency range of 4-24 MHz. 3612 */ 3613 #define OSC_CR_RANGE(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_RANGE_SHIFT)) & OSC_CR_RANGE_MASK) 3614 #define OSC_CR_OSCOS_MASK (0x10U) 3615 #define OSC_CR_OSCOS_SHIFT (4U) 3616 /*! OSCOS - OSC Output Select 3617 * 0b0..External clock source from EXTAL pin is selected. 3618 * 0b1..Oscillator clock source is selected. 3619 */ 3620 #define OSC_CR_OSCOS(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_OSCOS_SHIFT)) & OSC_CR_OSCOS_MASK) 3621 #define OSC_CR_OSCSTEN_MASK (0x20U) 3622 #define OSC_CR_OSCSTEN_SHIFT (5U) 3623 /*! OSCSTEN - OSC Enable in Stop mode 3624 * 0b0..OSC clock is disabled in Stop mode. 3625 * 0b1..OSC clock stays enabled in Stop mode. 3626 */ 3627 #define OSC_CR_OSCSTEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_OSCSTEN_SHIFT)) & OSC_CR_OSCSTEN_MASK) 3628 #define OSC_CR_OSCEN_MASK (0x80U) 3629 #define OSC_CR_OSCEN_SHIFT (7U) 3630 /*! OSCEN - OSC Enable 3631 * 0b0..OSC module is disabled. 3632 * 0b1..OSC module is enabled. 3633 */ 3634 #define OSC_CR_OSCEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_OSCEN_SHIFT)) & OSC_CR_OSCEN_MASK) 3635 /*! @} */ 3636 3637 3638 /*! 3639 * @} 3640 */ /* end of group OSC_Register_Masks */ 3641 3642 3643 /* OSC - Peripheral instance base addresses */ 3644 /** Peripheral OSC base address */ 3645 #define OSC_BASE (0x40065000u) 3646 /** Peripheral OSC base pointer */ 3647 #define OSC ((OSC_Type *)OSC_BASE) 3648 /** Array initializer of OSC peripheral base addresses */ 3649 #define OSC_BASE_ADDRS { OSC_BASE } 3650 /** Array initializer of OSC peripheral base pointers */ 3651 #define OSC_BASE_PTRS { OSC } 3652 3653 /*! 3654 * @} 3655 */ /* end of group OSC_Peripheral_Access_Layer */ 3656 3657 3658 /* ---------------------------------------------------------------------------- 3659 -- PIT Peripheral Access Layer 3660 ---------------------------------------------------------------------------- */ 3661 3662 /*! 3663 * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer 3664 * @{ 3665 */ 3666 3667 /** PIT - Register Layout Typedef */ 3668 typedef struct { 3669 __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */ 3670 uint8_t RESERVED_0[252]; 3671 struct { /* offset: 0x100, array step: 0x10 */ 3672 __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */ 3673 __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */ 3674 __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */ 3675 __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */ 3676 } CHANNEL[2]; 3677 } PIT_Type; 3678 3679 /* ---------------------------------------------------------------------------- 3680 -- PIT Register Masks 3681 ---------------------------------------------------------------------------- */ 3682 3683 /*! 3684 * @addtogroup PIT_Register_Masks PIT Register Masks 3685 * @{ 3686 */ 3687 3688 /*! @name MCR - PIT Module Control Register */ 3689 /*! @{ */ 3690 #define PIT_MCR_FRZ_MASK (0x1U) 3691 #define PIT_MCR_FRZ_SHIFT (0U) 3692 /*! FRZ - Freeze 3693 * 0b0..Timers continue to run in Debug mode. 3694 * 0b1..Timers are stopped in Debug mode. 3695 */ 3696 #define PIT_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK) 3697 #define PIT_MCR_MDIS_MASK (0x2U) 3698 #define PIT_MCR_MDIS_SHIFT (1U) 3699 /*! MDIS - Module Disable - (PIT section) 3700 * 0b0..Clock for standard PIT timers is enabled. 3701 * 0b1..Clock for standard PIT timers is disabled. 3702 */ 3703 #define PIT_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK) 3704 /*! @} */ 3705 3706 /*! @name LDVAL - Timer Load Value Register */ 3707 /*! @{ */ 3708 #define PIT_LDVAL_TSV_MASK (0xFFFFFFFFU) 3709 #define PIT_LDVAL_TSV_SHIFT (0U) 3710 #define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK) 3711 /*! @} */ 3712 3713 /* The count of PIT_LDVAL */ 3714 #define PIT_LDVAL_COUNT (2U) 3715 3716 /*! @name CVAL - Current Timer Value Register */ 3717 /*! @{ */ 3718 #define PIT_CVAL_TVL_MASK (0xFFFFFFFFU) 3719 #define PIT_CVAL_TVL_SHIFT (0U) 3720 #define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK) 3721 /*! @} */ 3722 3723 /* The count of PIT_CVAL */ 3724 #define PIT_CVAL_COUNT (2U) 3725 3726 /*! @name TCTRL - Timer Control Register */ 3727 /*! @{ */ 3728 #define PIT_TCTRL_TEN_MASK (0x1U) 3729 #define PIT_TCTRL_TEN_SHIFT (0U) 3730 /*! TEN - Timer Enable 3731 * 0b0..Timer n is disabled. 3732 * 0b1..Timer n is enabled. 3733 */ 3734 #define PIT_TCTRL_TEN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK) 3735 #define PIT_TCTRL_TIE_MASK (0x2U) 3736 #define PIT_TCTRL_TIE_SHIFT (1U) 3737 /*! TIE - Timer Interrupt Enable 3738 * 0b0..Interrupt requests from Timer n are disabled. 3739 * 0b1..Interrupt will be requested whenever TIF is set. 3740 */ 3741 #define PIT_TCTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK) 3742 #define PIT_TCTRL_CHN_MASK (0x4U) 3743 #define PIT_TCTRL_CHN_SHIFT (2U) 3744 /*! CHN - Chain Mode 3745 * 0b0..Timer is not chained. 3746 * 0b1..Timer is chained to previous timer. For example, for Channel 2, if this field is set, Timer 2 is chained to Timer 1. 3747 */ 3748 #define PIT_TCTRL_CHN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK) 3749 /*! @} */ 3750 3751 /* The count of PIT_TCTRL */ 3752 #define PIT_TCTRL_COUNT (2U) 3753 3754 /*! @name TFLG - Timer Flag Register */ 3755 /*! @{ */ 3756 #define PIT_TFLG_TIF_MASK (0x1U) 3757 #define PIT_TFLG_TIF_SHIFT (0U) 3758 /*! TIF - Timer Interrupt Flag 3759 * 0b0..Timeout has not yet occurred. 3760 * 0b1..Timeout has occurred. 3761 */ 3762 #define PIT_TFLG_TIF(x) (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK) 3763 /*! @} */ 3764 3765 /* The count of PIT_TFLG */ 3766 #define PIT_TFLG_COUNT (2U) 3767 3768 3769 /*! 3770 * @} 3771 */ /* end of group PIT_Register_Masks */ 3772 3773 3774 /* PIT - Peripheral instance base addresses */ 3775 /** Peripheral PIT base address */ 3776 #define PIT_BASE (0x40037000u) 3777 /** Peripheral PIT base pointer */ 3778 #define PIT ((PIT_Type *)PIT_BASE) 3779 /** Array initializer of PIT peripheral base addresses */ 3780 #define PIT_BASE_ADDRS { PIT_BASE } 3781 /** Array initializer of PIT peripheral base pointers */ 3782 #define PIT_BASE_PTRS { PIT } 3783 /** Interrupt vectors for the PIT peripheral type */ 3784 #define PIT_IRQS { { PIT_CH0_IRQn, PIT_CH1_IRQn } } 3785 3786 /*! 3787 * @} 3788 */ /* end of group PIT_Peripheral_Access_Layer */ 3789 3790 3791 /* ---------------------------------------------------------------------------- 3792 -- PMC Peripheral Access Layer 3793 ---------------------------------------------------------------------------- */ 3794 3795 /*! 3796 * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer 3797 * @{ 3798 */ 3799 3800 /** PMC - Register Layout Typedef */ 3801 typedef struct { 3802 __IO uint8_t SPMSC1; /**< System Power Management Status and Control 1 Register, offset: 0x0 */ 3803 __IO uint8_t SPMSC2; /**< System Power Management Status and Control 2 Register, offset: 0x1 */ 3804 } PMC_Type; 3805 3806 /* ---------------------------------------------------------------------------- 3807 -- PMC Register Masks 3808 ---------------------------------------------------------------------------- */ 3809 3810 /*! 3811 * @addtogroup PMC_Register_Masks PMC Register Masks 3812 * @{ 3813 */ 3814 3815 /*! @name SPMSC1 - System Power Management Status and Control 1 Register */ 3816 /*! @{ */ 3817 #define PMC_SPMSC1_BGBE_MASK (0x1U) 3818 #define PMC_SPMSC1_BGBE_SHIFT (0U) 3819 /*! BGBE - Bandgap Buffer Enable 3820 * 0b0..Bandgap buffer is disabled. 3821 * 0b1..Bandgap buffer is enabled. 3822 */ 3823 #define PMC_SPMSC1_BGBE(x) (((uint8_t)(((uint8_t)(x)) << PMC_SPMSC1_BGBE_SHIFT)) & PMC_SPMSC1_BGBE_MASK) 3824 #define PMC_SPMSC1_LVDE_MASK (0x4U) 3825 #define PMC_SPMSC1_LVDE_SHIFT (2U) 3826 /*! LVDE - Low-Voltage Detect Enable 3827 * 0b0..LVD logic is disabled. 3828 * 0b1..LVD logic is enabled. 3829 */ 3830 #define PMC_SPMSC1_LVDE(x) (((uint8_t)(((uint8_t)(x)) << PMC_SPMSC1_LVDE_SHIFT)) & PMC_SPMSC1_LVDE_MASK) 3831 #define PMC_SPMSC1_LVDSE_MASK (0x8U) 3832 #define PMC_SPMSC1_LVDSE_SHIFT (3U) 3833 /*! LVDSE - Low-Voltage Detect Stop Enable 3834 * 0b0..Low-voltage detect is disabled during Stop mode. 3835 * 0b1..Low-voltage detect is enabled during Stop mode. 3836 */ 3837 #define PMC_SPMSC1_LVDSE(x) (((uint8_t)(((uint8_t)(x)) << PMC_SPMSC1_LVDSE_SHIFT)) & PMC_SPMSC1_LVDSE_MASK) 3838 #define PMC_SPMSC1_LVDRE_MASK (0x10U) 3839 #define PMC_SPMSC1_LVDRE_SHIFT (4U) 3840 /*! LVDRE - Low-Voltage Detect Reset Enable 3841 * 0b0..LVD events do not generate hardware resets. 3842 * 0b1..Forces an MCU reset when an enabled low-voltage detect event occurs. 3843 */ 3844 #define PMC_SPMSC1_LVDRE(x) (((uint8_t)(((uint8_t)(x)) << PMC_SPMSC1_LVDRE_SHIFT)) & PMC_SPMSC1_LVDRE_MASK) 3845 #define PMC_SPMSC1_LVWIE_MASK (0x20U) 3846 #define PMC_SPMSC1_LVWIE_SHIFT (5U) 3847 /*! LVWIE - Low-Voltage Warning Interrupt Enable 3848 * 0b0..Hardware interrupt is disabled (use polling). 3849 * 0b1..Requests a hardware interrupt when LVWF = 1. 3850 */ 3851 #define PMC_SPMSC1_LVWIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_SPMSC1_LVWIE_SHIFT)) & PMC_SPMSC1_LVWIE_MASK) 3852 #define PMC_SPMSC1_LVWACK_MASK (0x40U) 3853 #define PMC_SPMSC1_LVWACK_SHIFT (6U) 3854 #define PMC_SPMSC1_LVWACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_SPMSC1_LVWACK_SHIFT)) & PMC_SPMSC1_LVWACK_MASK) 3855 #define PMC_SPMSC1_LVWF_MASK (0x80U) 3856 #define PMC_SPMSC1_LVWF_SHIFT (7U) 3857 /*! LVWF - Low-Voltage Warning Flag 3858 * 0b0..Low-voltage warning is not present. 3859 * 0b1..Low-voltage warning is present or was present. 3860 */ 3861 #define PMC_SPMSC1_LVWF(x) (((uint8_t)(((uint8_t)(x)) << PMC_SPMSC1_LVWF_SHIFT)) & PMC_SPMSC1_LVWF_MASK) 3862 /*! @} */ 3863 3864 /*! @name SPMSC2 - System Power Management Status and Control 2 Register */ 3865 /*! @{ */ 3866 #define PMC_SPMSC2_LVWV_MASK (0x30U) 3867 #define PMC_SPMSC2_LVWV_SHIFT (4U) 3868 /*! LVWV - Low-Voltage Warning Voltage Select 3869 * 0b00..Low trip point is selected (VLVW = VLVW1). 3870 * 0b01..Middle 1 trip point is selected (VLVW = VLVW2). 3871 * 0b10..Middle 2 trip point is selected (VLVW = VLVW3). 3872 * 0b11..High trip point is selected (VLVW = VLVW4). 3873 */ 3874 #define PMC_SPMSC2_LVWV(x) (((uint8_t)(((uint8_t)(x)) << PMC_SPMSC2_LVWV_SHIFT)) & PMC_SPMSC2_LVWV_MASK) 3875 #define PMC_SPMSC2_LVDV_MASK (0x40U) 3876 #define PMC_SPMSC2_LVDV_SHIFT (6U) 3877 /*! LVDV - Low-Voltage Detect Voltage Select 3878 * 0b0..Low trip point is selected (VLVD = VLVDL). 3879 * 0b1..High trip point is selected (VLVD = VLVDH). 3880 */ 3881 #define PMC_SPMSC2_LVDV(x) (((uint8_t)(((uint8_t)(x)) << PMC_SPMSC2_LVDV_SHIFT)) & PMC_SPMSC2_LVDV_MASK) 3882 /*! @} */ 3883 3884 3885 /*! 3886 * @} 3887 */ /* end of group PMC_Register_Masks */ 3888 3889 3890 /* PMC - Peripheral instance base addresses */ 3891 /** Peripheral PMC base address */ 3892 #define PMC_BASE (0x4007D000u) 3893 /** Peripheral PMC base pointer */ 3894 #define PMC ((PMC_Type *)PMC_BASE) 3895 /** Array initializer of PMC peripheral base addresses */ 3896 #define PMC_BASE_ADDRS { PMC_BASE } 3897 /** Array initializer of PMC peripheral base pointers */ 3898 #define PMC_BASE_PTRS { PMC } 3899 /** Interrupt vectors for the PMC peripheral type */ 3900 #define PMC_IRQS { PMC_IRQn } 3901 3902 /*! 3903 * @} 3904 */ /* end of group PMC_Peripheral_Access_Layer */ 3905 3906 3907 /* ---------------------------------------------------------------------------- 3908 -- PORT Peripheral Access Layer 3909 ---------------------------------------------------------------------------- */ 3910 3911 /*! 3912 * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer 3913 * @{ 3914 */ 3915 3916 /** PORT - Register Layout Typedef */ 3917 typedef struct { 3918 __IO uint32_t IOFLT; /**< Port Filter Register, offset: 0x0 */ 3919 __IO uint32_t PUEL; /**< Port Pullup Enable Low Register, offset: 0x4 */ 3920 uint8_t RESERVED_0[4]; 3921 __IO uint32_t HDRVE; /**< Port High Drive Enable Register, offset: 0xC */ 3922 } PORT_Type; 3923 3924 /* ---------------------------------------------------------------------------- 3925 -- PORT Register Masks 3926 ---------------------------------------------------------------------------- */ 3927 3928 /*! 3929 * @addtogroup PORT_Register_Masks PORT Register Masks 3930 * @{ 3931 */ 3932 3933 /*! @name IOFLT - Port Filter Register */ 3934 /*! @{ */ 3935 #define PORT_IOFLT_FLTA_MASK (0x3U) 3936 #define PORT_IOFLT_FLTA_SHIFT (0U) 3937 /*! FLTA - Filter Selection for Input from PTA 3938 * 0b00..BUSCLK 3939 * 0b01..FLTDIV1 3940 * 0b10..FLTDIV2 3941 * 0b11..FLTDIV3 3942 */ 3943 #define PORT_IOFLT_FLTA(x) (((uint32_t)(((uint32_t)(x)) << PORT_IOFLT_FLTA_SHIFT)) & PORT_IOFLT_FLTA_MASK) 3944 #define PORT_IOFLT_FLTB_MASK (0xCU) 3945 #define PORT_IOFLT_FLTB_SHIFT (2U) 3946 /*! FLTB - Filter Selection for Input from PTB 3947 * 0b00..BUSCLK 3948 * 0b01..FLTDIV1 3949 * 0b10..FLTDIV2 3950 * 0b11..FLTDIV3 3951 */ 3952 #define PORT_IOFLT_FLTB(x) (((uint32_t)(((uint32_t)(x)) << PORT_IOFLT_FLTB_SHIFT)) & PORT_IOFLT_FLTB_MASK) 3953 #define PORT_IOFLT_FLTC_MASK (0x30U) 3954 #define PORT_IOFLT_FLTC_SHIFT (4U) 3955 /*! FLTC - Filter Selection for Input from PTC 3956 * 0b00..BUSCLK 3957 * 0b01..FLTDIV1 3958 * 0b10..FLTDIV2 3959 * 0b11..FLTDIV3 3960 */ 3961 #define PORT_IOFLT_FLTC(x) (((uint32_t)(((uint32_t)(x)) << PORT_IOFLT_FLTC_SHIFT)) & PORT_IOFLT_FLTC_MASK) 3962 #define PORT_IOFLT_FLTIIC_MASK (0xC00U) 3963 #define PORT_IOFLT_FLTIIC_SHIFT (10U) 3964 /*! FLTIIC - Filter Selection For Input from SCL/SDA 3965 * 0b00..No filter 3966 * 0b01..Select FLTDIV1 3967 * 0b10..Select FLTDIV2 3968 * 0b11..Select BUSCLK 3969 */ 3970 #define PORT_IOFLT_FLTIIC(x) (((uint32_t)(((uint32_t)(x)) << PORT_IOFLT_FLTIIC_SHIFT)) & PORT_IOFLT_FLTIIC_MASK) 3971 #define PORT_IOFLT_FLTFTM0_MASK (0x3000U) 3972 #define PORT_IOFLT_FLTFTM0_SHIFT (12U) 3973 /*! FLTFTM0 - Filter Selection For Input from FTM0CH0/FTM0CH1 3974 * 0b00..No filter 3975 * 0b01..Select FLTDIV1 3976 * 0b10..Select FLTDIV2 3977 * 0b11..Select FLTDIV3 3978 */ 3979 #define PORT_IOFLT_FLTFTM0(x) (((uint32_t)(((uint32_t)(x)) << PORT_IOFLT_FLTFTM0_SHIFT)) & PORT_IOFLT_FLTFTM0_MASK) 3980 #define PORT_IOFLT_FLTPWT_MASK (0xC000U) 3981 #define PORT_IOFLT_FLTPWT_SHIFT (14U) 3982 /*! FLTPWT - Filter Selection For Input from PWT_IN1/PWT_IN0 3983 * 0b00..No filter 3984 * 0b01..Select FLTDIV1 3985 * 0b10..Select FLTDIV2 3986 * 0b11..Select FLTDIV3 3987 */ 3988 #define PORT_IOFLT_FLTPWT(x) (((uint32_t)(((uint32_t)(x)) << PORT_IOFLT_FLTPWT_SHIFT)) & PORT_IOFLT_FLTPWT_MASK) 3989 #define PORT_IOFLT_FLTRST_MASK (0x30000U) 3990 #define PORT_IOFLT_FLTRST_SHIFT (16U) 3991 /*! FLTRST - Filter Selection for Input from RESET/IRQ 3992 * 0b00..No filter. 3993 * 0b01..Selects FLTDIV1, and will switch to FLTDIV3 in Stop mode automatically. 3994 * 0b10..Selects FLTDIV2, and will switch to FLTDIV3 in Stop mode automatically. 3995 * 0b11..FLTDIV3 3996 */ 3997 #define PORT_IOFLT_FLTRST(x) (((uint32_t)(((uint32_t)(x)) << PORT_IOFLT_FLTRST_SHIFT)) & PORT_IOFLT_FLTRST_MASK) 3998 #define PORT_IOFLT_FLTKBI0_MASK (0xC0000U) 3999 #define PORT_IOFLT_FLTKBI0_SHIFT (18U) 4000 /*! FLTKBI0 - Filter selection for Input from KBI0 4001 * 0b00..No filter. 4002 * 0b01..Selects FLTDIV1, and will switch to FLTDIV3 in Stop mode automatically. 4003 * 0b10..Selects FLTDIV2, and will switch to FLTDIV3 in Stop mode automatically. 4004 * 0b11..FLTDIV3 4005 */ 4006 #define PORT_IOFLT_FLTKBI0(x) (((uint32_t)(((uint32_t)(x)) << PORT_IOFLT_FLTKBI0_SHIFT)) & PORT_IOFLT_FLTKBI0_MASK) 4007 #define PORT_IOFLT_FLTKBI1_MASK (0x300000U) 4008 #define PORT_IOFLT_FLTKBI1_SHIFT (20U) 4009 /*! FLTKBI1 - Filter Selection for Input from KBI1 4010 * 0b00..No filter 4011 * 0b01..Selects FLTDIV1, and will switch to FLTDIV3 in Stop mode automatically. 4012 * 0b10..Selects FLTDIV2, and will switch to FLTDIV3 in Stop mode automatically. 4013 * 0b11..FLTDIV3 4014 */ 4015 #define PORT_IOFLT_FLTKBI1(x) (((uint32_t)(((uint32_t)(x)) << PORT_IOFLT_FLTKBI1_SHIFT)) & PORT_IOFLT_FLTKBI1_MASK) 4016 #define PORT_IOFLT_FLTNMI_MASK (0xC00000U) 4017 #define PORT_IOFLT_FLTNMI_SHIFT (22U) 4018 /*! FLTNMI - Filter Selection for Input from NMI 4019 * 0b00..No filter. 4020 * 0b01..Selects FLTDIV1, and will switch to FLTDIV3 in Stop mode automatically. 4021 * 0b10..Selects FLTDIV2, and will switch to FLTDIV3 in Stop mode automatically. 4022 * 0b11..FLTDIV3 4023 */ 4024 #define PORT_IOFLT_FLTNMI(x) (((uint32_t)(((uint32_t)(x)) << PORT_IOFLT_FLTNMI_SHIFT)) & PORT_IOFLT_FLTNMI_MASK) 4025 #define PORT_IOFLT_FLTDIV1_MASK (0x3000000U) 4026 #define PORT_IOFLT_FLTDIV1_SHIFT (24U) 4027 /*! FLTDIV1 - Filter Division Set 1 4028 * 0b00..BUSCLK/2 4029 * 0b01..BUSCLK/4 4030 * 0b10..BUSCLK/8 4031 * 0b11..BUSCLK/16 4032 */ 4033 #define PORT_IOFLT_FLTDIV1(x) (((uint32_t)(((uint32_t)(x)) << PORT_IOFLT_FLTDIV1_SHIFT)) & PORT_IOFLT_FLTDIV1_MASK) 4034 #define PORT_IOFLT_FLTDIV2_MASK (0x1C000000U) 4035 #define PORT_IOFLT_FLTDIV2_SHIFT (26U) 4036 /*! FLTDIV2 - Filter Division Set 2 4037 * 0b000..BUSCLK/32 4038 * 0b001..BUSCLK/64 4039 * 0b010..BUSCLK/128 4040 * 0b011..BUSCLK/256 4041 * 0b100..BUSCLK/512 4042 * 0b101..BUSCLK/1024 4043 * 0b110..BUSCLK/2048 4044 * 0b111..BUSCLK/4096 4045 */ 4046 #define PORT_IOFLT_FLTDIV2(x) (((uint32_t)(((uint32_t)(x)) << PORT_IOFLT_FLTDIV2_SHIFT)) & PORT_IOFLT_FLTDIV2_MASK) 4047 #define PORT_IOFLT_FLTDIV3_MASK (0xE0000000U) 4048 #define PORT_IOFLT_FLTDIV3_SHIFT (29U) 4049 /*! FLTDIV3 - Filter Division Set 3 4050 * 0b000..LPOCLK 4051 * 0b001..LPOCLK/2 4052 * 0b010..LPOCLK/4 4053 * 0b011..LPOCLK/8 4054 * 0b100..LPOCLK/16 4055 * 0b101..LPOCLK/32 4056 * 0b110..LPOCLK/64 4057 * 0b111..LPOCLK/128 4058 */ 4059 #define PORT_IOFLT_FLTDIV3(x) (((uint32_t)(((uint32_t)(x)) << PORT_IOFLT_FLTDIV3_SHIFT)) & PORT_IOFLT_FLTDIV3_MASK) 4060 /*! @} */ 4061 4062 /*! @name PUEL - Port Pullup Enable Low Register */ 4063 /*! @{ */ 4064 #define PORT_PUEL_PTAPE0_MASK (0x1U) 4065 #define PORT_PUEL_PTAPE0_SHIFT (0U) 4066 /*! PTAPE0 - Pull Enable for Port A Bit 0 4067 * 0b0..Pullup is disabled for port A bit 0. 4068 * 0b1..Pullup is enabled for port A bit 0. 4069 */ 4070 #define PORT_PUEL_PTAPE0(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUEL_PTAPE0_SHIFT)) & PORT_PUEL_PTAPE0_MASK) 4071 #define PORT_PUEL_PTAPE1_MASK (0x2U) 4072 #define PORT_PUEL_PTAPE1_SHIFT (1U) 4073 /*! PTAPE1 - Pull Enable for Port A Bit 1 4074 * 0b0..Pullup is disabled for port A bit 1. 4075 * 0b1..Pullup is enabled for port A bit 1. 4076 */ 4077 #define PORT_PUEL_PTAPE1(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUEL_PTAPE1_SHIFT)) & PORT_PUEL_PTAPE1_MASK) 4078 #define PORT_PUEL_PTAPE2_MASK (0x4U) 4079 #define PORT_PUEL_PTAPE2_SHIFT (2U) 4080 /*! PTAPE2 - Pull Enable for Port A Bit 2 4081 * 0b0..Pullup is disabled for port A bit 2. 4082 * 0b1..Pullup is enabled for port A bit 2. 4083 */ 4084 #define PORT_PUEL_PTAPE2(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUEL_PTAPE2_SHIFT)) & PORT_PUEL_PTAPE2_MASK) 4085 #define PORT_PUEL_PTAPE3_MASK (0x8U) 4086 #define PORT_PUEL_PTAPE3_SHIFT (3U) 4087 /*! PTAPE3 - Pull Enable for Port A Bit 3 4088 * 0b0..Pullup is disabled for port A bit 3. 4089 * 0b1..Pullup is enabled for port A bit 3. 4090 */ 4091 #define PORT_PUEL_PTAPE3(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUEL_PTAPE3_SHIFT)) & PORT_PUEL_PTAPE3_MASK) 4092 #define PORT_PUEL_PTAPE4_MASK (0x10U) 4093 #define PORT_PUEL_PTAPE4_SHIFT (4U) 4094 /*! PTAPE4 - Pull Enable for Port A Bit 4 4095 * 0b0..Pullup is disabled for port A bit 4. 4096 * 0b1..Pullup is enabled for port A bit 4. 4097 */ 4098 #define PORT_PUEL_PTAPE4(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUEL_PTAPE4_SHIFT)) & PORT_PUEL_PTAPE4_MASK) 4099 #define PORT_PUEL_PTAPE5_MASK (0x20U) 4100 #define PORT_PUEL_PTAPE5_SHIFT (5U) 4101 /*! PTAPE5 - Pull Enable for Port A Bit 5 4102 * 0b0..Pullup is disabled for port A bit 5. 4103 * 0b1..Pullup is enabled for port A bit 5. 4104 */ 4105 #define PORT_PUEL_PTAPE5(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUEL_PTAPE5_SHIFT)) & PORT_PUEL_PTAPE5_MASK) 4106 #define PORT_PUEL_PTAPE6_MASK (0x40U) 4107 #define PORT_PUEL_PTAPE6_SHIFT (6U) 4108 /*! PTAPE6 - Pull Enable for Port A Bit 6 4109 * 0b0..Pullup is disabled for port A bit 6. 4110 * 0b1..Pullup is enabled for port A bit 6. 4111 */ 4112 #define PORT_PUEL_PTAPE6(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUEL_PTAPE6_SHIFT)) & PORT_PUEL_PTAPE6_MASK) 4113 #define PORT_PUEL_PTAPE7_MASK (0x80U) 4114 #define PORT_PUEL_PTAPE7_SHIFT (7U) 4115 /*! PTAPE7 - Pull Enable for Port A Bit 7 4116 * 0b0..Pullup is disabled for port A bit 7. 4117 * 0b1..Pullup is enabled for port A bit 7. 4118 */ 4119 #define PORT_PUEL_PTAPE7(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUEL_PTAPE7_SHIFT)) & PORT_PUEL_PTAPE7_MASK) 4120 #define PORT_PUEL_PTBPE0_MASK (0x100U) 4121 #define PORT_PUEL_PTBPE0_SHIFT (8U) 4122 /*! PTBPE0 - Pull Enable for Port B Bit 0 4123 * 0b0..Pullup is disabled for port B bit 0. 4124 * 0b1..Pullup is enabled for port B bit 0. 4125 */ 4126 #define PORT_PUEL_PTBPE0(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUEL_PTBPE0_SHIFT)) & PORT_PUEL_PTBPE0_MASK) 4127 #define PORT_PUEL_PTBPE1_MASK (0x200U) 4128 #define PORT_PUEL_PTBPE1_SHIFT (9U) 4129 /*! PTBPE1 - Pull Enable for Port B Bit 1 4130 * 0b0..Pullup is disabled for port B bit 1. 4131 * 0b1..Pullup is enabled for port B bit 1. 4132 */ 4133 #define PORT_PUEL_PTBPE1(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUEL_PTBPE1_SHIFT)) & PORT_PUEL_PTBPE1_MASK) 4134 #define PORT_PUEL_PTBPE2_MASK (0x400U) 4135 #define PORT_PUEL_PTBPE2_SHIFT (10U) 4136 /*! PTBPE2 - Pull Enable for Port B Bit 2 4137 * 0b0..Pullup is disabled for port B bit 2. 4138 * 0b1..Pullup is enabled for port B bit 2. 4139 */ 4140 #define PORT_PUEL_PTBPE2(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUEL_PTBPE2_SHIFT)) & PORT_PUEL_PTBPE2_MASK) 4141 #define PORT_PUEL_PTBPE3_MASK (0x800U) 4142 #define PORT_PUEL_PTBPE3_SHIFT (11U) 4143 /*! PTBPE3 - Pull Enable for Port B Bit 3 4144 * 0b0..Pullup is disabled for port B bit 3. 4145 * 0b1..Pullup is enabled for port B bit 3. 4146 */ 4147 #define PORT_PUEL_PTBPE3(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUEL_PTBPE3_SHIFT)) & PORT_PUEL_PTBPE3_MASK) 4148 #define PORT_PUEL_PTBPE4_MASK (0x1000U) 4149 #define PORT_PUEL_PTBPE4_SHIFT (12U) 4150 /*! PTBPE4 - Pull Enable for Port B Bit 4 4151 * 0b0..Pullup is disabled for port B bit 4. 4152 * 0b1..Pullup is enabled for port B bit 4. 4153 */ 4154 #define PORT_PUEL_PTBPE4(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUEL_PTBPE4_SHIFT)) & PORT_PUEL_PTBPE4_MASK) 4155 #define PORT_PUEL_PTBPE5_MASK (0x2000U) 4156 #define PORT_PUEL_PTBPE5_SHIFT (13U) 4157 /*! PTBPE5 - Pull Enable for Port B Bit 5 4158 * 0b0..Pullup is disabled for port B bit 5. 4159 * 0b1..Pullup is enabled for port B bit 5. 4160 */ 4161 #define PORT_PUEL_PTBPE5(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUEL_PTBPE5_SHIFT)) & PORT_PUEL_PTBPE5_MASK) 4162 #define PORT_PUEL_PTBPE6_MASK (0x4000U) 4163 #define PORT_PUEL_PTBPE6_SHIFT (14U) 4164 /*! PTBPE6 - Pull Enable for Port B Bit 6 4165 * 0b0..Pullup is disabled for port B bit 6. 4166 * 0b1..Pullup is enabled for port B bit 6. 4167 */ 4168 #define PORT_PUEL_PTBPE6(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUEL_PTBPE6_SHIFT)) & PORT_PUEL_PTBPE6_MASK) 4169 #define PORT_PUEL_PTBPE7_MASK (0x8000U) 4170 #define PORT_PUEL_PTBPE7_SHIFT (15U) 4171 /*! PTBPE7 - Pull Enable for Port B Bit 7 4172 * 0b0..Pullup is disabled for port B bit 7. 4173 * 0b1..Pullup is enabled for port B bit 7. 4174 */ 4175 #define PORT_PUEL_PTBPE7(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUEL_PTBPE7_SHIFT)) & PORT_PUEL_PTBPE7_MASK) 4176 #define PORT_PUEL_PTCPE0_MASK (0x10000U) 4177 #define PORT_PUEL_PTCPE0_SHIFT (16U) 4178 /*! PTCPE0 - Pull Enable for Port C Bit 0 4179 * 0b0..Pullup is disabled for port C bit 0. 4180 * 0b1..Pullup is enabled for port C bit 0. 4181 */ 4182 #define PORT_PUEL_PTCPE0(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUEL_PTCPE0_SHIFT)) & PORT_PUEL_PTCPE0_MASK) 4183 #define PORT_PUEL_PTCPE1_MASK (0x20000U) 4184 #define PORT_PUEL_PTCPE1_SHIFT (17U) 4185 /*! PTCPE1 - Pull Enable for Port C Bit 1 4186 * 0b0..Pullup is disabled for port C bit 1. 4187 * 0b1..Pullup is enabled for port C bit 1. 4188 */ 4189 #define PORT_PUEL_PTCPE1(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUEL_PTCPE1_SHIFT)) & PORT_PUEL_PTCPE1_MASK) 4190 #define PORT_PUEL_PTCPE2_MASK (0x40000U) 4191 #define PORT_PUEL_PTCPE2_SHIFT (18U) 4192 /*! PTCPE2 - Pull Enable for Port C Bit 2 4193 * 0b0..Pullup is disabled for port C bit 2. 4194 * 0b1..Pullup is enabled for port C bit 2. 4195 */ 4196 #define PORT_PUEL_PTCPE2(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUEL_PTCPE2_SHIFT)) & PORT_PUEL_PTCPE2_MASK) 4197 #define PORT_PUEL_PTCPE3_MASK (0x80000U) 4198 #define PORT_PUEL_PTCPE3_SHIFT (19U) 4199 /*! PTCPE3 - Pull Enable for Port C Bit 3 4200 * 0b0..Pullup is disabled for port C bit 3. 4201 * 0b1..Pullup is enabled for port C bit 3. 4202 */ 4203 #define PORT_PUEL_PTCPE3(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUEL_PTCPE3_SHIFT)) & PORT_PUEL_PTCPE3_MASK) 4204 #define PORT_PUEL_PTCPE4_MASK (0x100000U) 4205 #define PORT_PUEL_PTCPE4_SHIFT (20U) 4206 /*! PTCPE4 - Pull Enable for Port C Bit 4 4207 * 0b0..Pullup is disabled for port C bit 4. 4208 * 0b1..Pullup is enabled for port C bit 4. 4209 */ 4210 #define PORT_PUEL_PTCPE4(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUEL_PTCPE4_SHIFT)) & PORT_PUEL_PTCPE4_MASK) 4211 #define PORT_PUEL_PTCPE5_MASK (0x200000U) 4212 #define PORT_PUEL_PTCPE5_SHIFT (21U) 4213 /*! PTCPE5 - Pull Enable for Port C Bit 5 4214 * 0b0..Pullup is disabled for port C bit 5. 4215 * 0b1..Pullup is enabled for port C bit 5. 4216 */ 4217 #define PORT_PUEL_PTCPE5(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUEL_PTCPE5_SHIFT)) & PORT_PUEL_PTCPE5_MASK) 4218 /*! @} */ 4219 4220 /*! @name HDRVE - Port High Drive Enable Register */ 4221 /*! @{ */ 4222 #define PORT_HDRVE_PTB5_MASK (0x2U) 4223 #define PORT_HDRVE_PTB5_SHIFT (1U) 4224 /*! PTB5 - High Current Drive Capability of PTB5 4225 * 0b0..PTB5 is disabled to offer high current drive capability. 4226 * 0b1..PTB5 is enabled to offer high current drive capability. 4227 */ 4228 #define PORT_HDRVE_PTB5(x) (((uint32_t)(((uint32_t)(x)) << PORT_HDRVE_PTB5_SHIFT)) & PORT_HDRVE_PTB5_MASK) 4229 #define PORT_HDRVE_PTC1_MASK (0x4U) 4230 #define PORT_HDRVE_PTC1_SHIFT (2U) 4231 /*! PTC1 - High Current Drive Capability of PTC1 4232 * 0b0..PTC1 is disabled to offer high current drive capability. 4233 * 0b1..PTC1 is enabled to offer high current drive capability. 4234 */ 4235 #define PORT_HDRVE_PTC1(x) (((uint32_t)(((uint32_t)(x)) << PORT_HDRVE_PTC1_SHIFT)) & PORT_HDRVE_PTC1_MASK) 4236 #define PORT_HDRVE_PTC5_MASK (0x8U) 4237 #define PORT_HDRVE_PTC5_SHIFT (3U) 4238 /*! PTC5 - High Current Drive Capability of PTC5 4239 * 0b0..PTC5 is disabled to offer high current drive capability. 4240 * 0b1..PTC5 is enabled to offer high current drive capability. 4241 */ 4242 #define PORT_HDRVE_PTC5(x) (((uint32_t)(((uint32_t)(x)) << PORT_HDRVE_PTC5_SHIFT)) & PORT_HDRVE_PTC5_MASK) 4243 /*! @} */ 4244 4245 4246 /*! 4247 * @} 4248 */ /* end of group PORT_Register_Masks */ 4249 4250 4251 /* PORT - Peripheral instance base addresses */ 4252 /** Peripheral PORT base address */ 4253 #define PORT_BASE (0x40049000u) 4254 /** Peripheral PORT base pointer */ 4255 #define PORT ((PORT_Type *)PORT_BASE) 4256 /** Array initializer of PORT peripheral base addresses */ 4257 #define PORT_BASE_ADDRS { PORT_BASE } 4258 /** Array initializer of PORT peripheral base pointers */ 4259 #define PORT_BASE_PTRS { PORT } 4260 4261 /*! 4262 * @} 4263 */ /* end of group PORT_Peripheral_Access_Layer */ 4264 4265 4266 /* ---------------------------------------------------------------------------- 4267 -- PWT Peripheral Access Layer 4268 ---------------------------------------------------------------------------- */ 4269 4270 /*! 4271 * @addtogroup PWT_Peripheral_Access_Layer PWT Peripheral Access Layer 4272 * @{ 4273 */ 4274 4275 /** PWT - Register Layout Typedef */ 4276 typedef struct { 4277 __IO uint32_t R1; /**< Pulse Width Timer Register 1, offset: 0x0 */ 4278 __I uint32_t R2; /**< Pulse Width Timer Register 2, offset: 0x4 */ 4279 } PWT_Type; 4280 4281 /* ---------------------------------------------------------------------------- 4282 -- PWT Register Masks 4283 ---------------------------------------------------------------------------- */ 4284 4285 /*! 4286 * @addtogroup PWT_Register_Masks PWT Register Masks 4287 * @{ 4288 */ 4289 4290 /*! @name R1 - Pulse Width Timer Register 1 */ 4291 /*! @{ */ 4292 #define PWT_R1_PWTOV_MASK (0x1U) 4293 #define PWT_R1_PWTOV_SHIFT (0U) 4294 /*! PWTOV - PWT Counter Overflow 4295 * 0b0..PWT counter no overflow. 4296 * 0b1..PWT counter runs from 0xFFFF to 0x0000. 4297 */ 4298 #define PWT_R1_PWTOV(x) (((uint32_t)(((uint32_t)(x)) << PWT_R1_PWTOV_SHIFT)) & PWT_R1_PWTOV_MASK) 4299 #define PWT_R1_PWTRDY_MASK (0x2U) 4300 #define PWT_R1_PWTRDY_SHIFT (1U) 4301 /*! PWTRDY - PWT Pulse Width Valid 4302 * 0b0..PWT pulse width register(s) is not up-to-date. 4303 * 0b1..PWT pulse width register(s) has been updated. 4304 */ 4305 #define PWT_R1_PWTRDY(x) (((uint32_t)(((uint32_t)(x)) << PWT_R1_PWTRDY_SHIFT)) & PWT_R1_PWTRDY_MASK) 4306 #define PWT_R1_PWTSR_MASK (0x8U) 4307 #define PWT_R1_PWTSR_SHIFT (3U) 4308 /*! PWTSR - PWT Soft Reset 4309 * 0b0..No action taken. 4310 * 0b1..Writing 1 to this field will perform soft reset to PWT. 4311 */ 4312 #define PWT_R1_PWTSR(x) (((uint32_t)(((uint32_t)(x)) << PWT_R1_PWTSR_SHIFT)) & PWT_R1_PWTSR_MASK) 4313 #define PWT_R1_POVIE_MASK (0x10U) 4314 #define PWT_R1_POVIE_SHIFT (4U) 4315 /*! POVIE - PWT Counter Overflow Interrupt Enable 4316 * 0b0..Disable PWT to generate interrupt when PWTOV is set. 4317 * 0b1..Enable PWT to generate interrupt when PWTOV is set. 4318 */ 4319 #define PWT_R1_POVIE(x) (((uint32_t)(((uint32_t)(x)) << PWT_R1_POVIE_SHIFT)) & PWT_R1_POVIE_MASK) 4320 #define PWT_R1_PRDYIE_MASK (0x20U) 4321 #define PWT_R1_PRDYIE_SHIFT (5U) 4322 /*! PRDYIE - PWT Pulse Width Data Ready Interrupt Enable 4323 * 0b0..Disable PWT to generate interrupt when PWTRDY is set. 4324 * 0b1..Enable PWT to generate interrupt when PWTRDY is set. 4325 */ 4326 #define PWT_R1_PRDYIE(x) (((uint32_t)(((uint32_t)(x)) << PWT_R1_PRDYIE_SHIFT)) & PWT_R1_PRDYIE_MASK) 4327 #define PWT_R1_PWTIE_MASK (0x40U) 4328 #define PWT_R1_PWTIE_SHIFT (6U) 4329 /*! PWTIE - PWT Module Interrupt Enable 4330 * 0b0..Disables the PWT to generate interrupt. 4331 * 0b1..Enables the PWT to generate interrupt. 4332 */ 4333 #define PWT_R1_PWTIE(x) (((uint32_t)(((uint32_t)(x)) << PWT_R1_PWTIE_SHIFT)) & PWT_R1_PWTIE_MASK) 4334 #define PWT_R1_PWTEN_MASK (0x80U) 4335 #define PWT_R1_PWTEN_SHIFT (7U) 4336 /*! PWTEN - PWT Module Enable 4337 * 0b0..The PWT is disabled. 4338 * 0b1..The PWT is enabled. 4339 */ 4340 #define PWT_R1_PWTEN(x) (((uint32_t)(((uint32_t)(x)) << PWT_R1_PWTEN_SHIFT)) & PWT_R1_PWTEN_MASK) 4341 #define PWT_R1_PRE_MASK (0x700U) 4342 #define PWT_R1_PRE_SHIFT (8U) 4343 /*! PRE - PWT Clock Prescaler (CLKPRE) Setting 4344 * 0b000..Clock divided by 1. 4345 * 0b001..Clock divided by 2. 4346 * 0b010..Clock divided by 4. 4347 * 0b011..Clock divided by 8. 4348 * 0b100..Clock divided by 16. 4349 * 0b101..Clock divided by 32. 4350 * 0b110..Clock divided by 64. 4351 * 0b111..Clock divided by 128. 4352 */ 4353 #define PWT_R1_PRE(x) (((uint32_t)(((uint32_t)(x)) << PWT_R1_PRE_SHIFT)) & PWT_R1_PRE_MASK) 4354 #define PWT_R1_EDGE_MASK (0x1800U) 4355 #define PWT_R1_EDGE_SHIFT (11U) 4356 /*! EDGE - PWT Input Edge Sensitivity 4357 * 0b00..The first falling-edge starts the pulse width measurement, and on all the subsequent falling edges, the pulse width is captured. 4358 * 0b01..The first rising edge starts the pulse width measurement, and on all the subsequent rising and falling edges, the pulse width is captured. 4359 * 0b10..The first falling edge starts the pulse width measurement, and on all the subsequent rising and falling edges, the pulse width is captured. 4360 * 0b11..The first-rising edge starts the pulse width measurement, and on all the subsequent rising edges, the pulse width is captured. 4361 */ 4362 #define PWT_R1_EDGE(x) (((uint32_t)(((uint32_t)(x)) << PWT_R1_EDGE_SHIFT)) & PWT_R1_EDGE_MASK) 4363 #define PWT_R1_PINSEL_MASK (0x6000U) 4364 #define PWT_R1_PINSEL_SHIFT (13U) 4365 /*! PINSEL - PWT Pulse Inputs Selection 4366 * 0b00..PWTIN[0] is enabled. 4367 * 0b01..PWTIN[1] is enabled. 4368 * 0b10..PWTIN[2] enabled. 4369 * 0b11..PWTIN[3] enabled. 4370 */ 4371 #define PWT_R1_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << PWT_R1_PINSEL_SHIFT)) & PWT_R1_PINSEL_MASK) 4372 #define PWT_R1_PCLKS_MASK (0x8000U) 4373 #define PWT_R1_PCLKS_SHIFT (15U) 4374 /*! PCLKS - PWT Clock Source Selection 4375 * 0b0..TIMER_CLK is selected as the clock source of PWT counter. 4376 * 0b1..Alternative clock is selected as the clock source of PWT counter. 4377 */ 4378 #define PWT_R1_PCLKS(x) (((uint32_t)(((uint32_t)(x)) << PWT_R1_PCLKS_SHIFT)) & PWT_R1_PCLKS_MASK) 4379 #define PWT_R1_PPW_MASK (0xFFFF0000U) 4380 #define PWT_R1_PPW_SHIFT (16U) 4381 #define PWT_R1_PPW(x) (((uint32_t)(((uint32_t)(x)) << PWT_R1_PPW_SHIFT)) & PWT_R1_PPW_MASK) 4382 /*! @} */ 4383 4384 /*! @name R2 - Pulse Width Timer Register 2 */ 4385 /*! @{ */ 4386 #define PWT_R2_NPW_MASK (0xFFFFU) 4387 #define PWT_R2_NPW_SHIFT (0U) 4388 #define PWT_R2_NPW(x) (((uint32_t)(((uint32_t)(x)) << PWT_R2_NPW_SHIFT)) & PWT_R2_NPW_MASK) 4389 #define PWT_R2_PWTC_MASK (0xFFFF0000U) 4390 #define PWT_R2_PWTC_SHIFT (16U) 4391 #define PWT_R2_PWTC(x) (((uint32_t)(((uint32_t)(x)) << PWT_R2_PWTC_SHIFT)) & PWT_R2_PWTC_MASK) 4392 /*! @} */ 4393 4394 4395 /*! 4396 * @} 4397 */ /* end of group PWT_Register_Masks */ 4398 4399 4400 /* PWT - Peripheral instance base addresses */ 4401 /** Peripheral PWT base address */ 4402 #define PWT_BASE (0x40033000u) 4403 /** Peripheral PWT base pointer */ 4404 #define PWT ((PWT_Type *)PWT_BASE) 4405 /** Array initializer of PWT peripheral base addresses */ 4406 #define PWT_BASE_ADDRS { PWT_BASE } 4407 /** Array initializer of PWT peripheral base pointers */ 4408 #define PWT_BASE_PTRS { PWT } 4409 /** Interrupt vectors for the PWT peripheral type */ 4410 #define PWT_IRQS { PWT_IRQn } 4411 4412 /*! 4413 * @} 4414 */ /* end of group PWT_Peripheral_Access_Layer */ 4415 4416 4417 /* ---------------------------------------------------------------------------- 4418 -- ROM Peripheral Access Layer 4419 ---------------------------------------------------------------------------- */ 4420 4421 /*! 4422 * @addtogroup ROM_Peripheral_Access_Layer ROM Peripheral Access Layer 4423 * @{ 4424 */ 4425 4426 /** ROM - Register Layout Typedef */ 4427 typedef struct { 4428 __I uint32_t ENTRY[1]; /**< Entry, array offset: 0x0, array step: 0x4 */ 4429 __I uint32_t TABLEMARK; /**< End of Table Marker Register, offset: 0x4 */ 4430 uint8_t RESERVED_0[4036]; 4431 __I uint32_t SYSACCESS; /**< System Access Register, offset: 0xFCC */ 4432 __I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */ 4433 __I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */ 4434 __I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */ 4435 __I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */ 4436 __I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */ 4437 __I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */ 4438 __I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */ 4439 __I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */ 4440 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */ 4441 } ROM_Type; 4442 4443 /* ---------------------------------------------------------------------------- 4444 -- ROM Register Masks 4445 ---------------------------------------------------------------------------- */ 4446 4447 /*! 4448 * @addtogroup ROM_Register_Masks ROM Register Masks 4449 * @{ 4450 */ 4451 4452 /*! @name ENTRY - Entry */ 4453 /*! @{ */ 4454 #define ROM_ENTRY_ENTRY_MASK (0xFFFFFFFFU) 4455 #define ROM_ENTRY_ENTRY_SHIFT (0U) 4456 #define ROM_ENTRY_ENTRY(x) (((uint32_t)(((uint32_t)(x)) << ROM_ENTRY_ENTRY_SHIFT)) & ROM_ENTRY_ENTRY_MASK) 4457 /*! @} */ 4458 4459 /* The count of ROM_ENTRY */ 4460 #define ROM_ENTRY_COUNT (1U) 4461 4462 /*! @name TABLEMARK - End of Table Marker Register */ 4463 /*! @{ */ 4464 #define ROM_TABLEMARK_MARK_MASK (0xFFFFFFFFU) 4465 #define ROM_TABLEMARK_MARK_SHIFT (0U) 4466 #define ROM_TABLEMARK_MARK(x) (((uint32_t)(((uint32_t)(x)) << ROM_TABLEMARK_MARK_SHIFT)) & ROM_TABLEMARK_MARK_MASK) 4467 /*! @} */ 4468 4469 /*! @name SYSACCESS - System Access Register */ 4470 /*! @{ */ 4471 #define ROM_SYSACCESS_SYSACCESS_MASK (0xFFFFFFFFU) 4472 #define ROM_SYSACCESS_SYSACCESS_SHIFT (0U) 4473 #define ROM_SYSACCESS_SYSACCESS(x) (((uint32_t)(((uint32_t)(x)) << ROM_SYSACCESS_SYSACCESS_SHIFT)) & ROM_SYSACCESS_SYSACCESS_MASK) 4474 /*! @} */ 4475 4476 /*! @name PERIPHID4 - Peripheral ID Register */ 4477 /*! @{ */ 4478 #define ROM_PERIPHID4_PERIPHID_MASK (0xFFFFFFFFU) 4479 #define ROM_PERIPHID4_PERIPHID_SHIFT (0U) 4480 #define ROM_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID4_PERIPHID_SHIFT)) & ROM_PERIPHID4_PERIPHID_MASK) 4481 /*! @} */ 4482 4483 /*! @name PERIPHID5 - Peripheral ID Register */ 4484 /*! @{ */ 4485 #define ROM_PERIPHID5_PERIPHID_MASK (0xFFFFFFFFU) 4486 #define ROM_PERIPHID5_PERIPHID_SHIFT (0U) 4487 #define ROM_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID5_PERIPHID_SHIFT)) & ROM_PERIPHID5_PERIPHID_MASK) 4488 /*! @} */ 4489 4490 /*! @name PERIPHID6 - Peripheral ID Register */ 4491 /*! @{ */ 4492 #define ROM_PERIPHID6_PERIPHID_MASK (0xFFFFFFFFU) 4493 #define ROM_PERIPHID6_PERIPHID_SHIFT (0U) 4494 #define ROM_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID6_PERIPHID_SHIFT)) & ROM_PERIPHID6_PERIPHID_MASK) 4495 /*! @} */ 4496 4497 /*! @name PERIPHID7 - Peripheral ID Register */ 4498 /*! @{ */ 4499 #define ROM_PERIPHID7_PERIPHID_MASK (0xFFFFFFFFU) 4500 #define ROM_PERIPHID7_PERIPHID_SHIFT (0U) 4501 #define ROM_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID7_PERIPHID_SHIFT)) & ROM_PERIPHID7_PERIPHID_MASK) 4502 /*! @} */ 4503 4504 /*! @name PERIPHID0 - Peripheral ID Register */ 4505 /*! @{ */ 4506 #define ROM_PERIPHID0_PERIPHID_MASK (0xFFFFFFFFU) 4507 #define ROM_PERIPHID0_PERIPHID_SHIFT (0U) 4508 #define ROM_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID0_PERIPHID_SHIFT)) & ROM_PERIPHID0_PERIPHID_MASK) 4509 /*! @} */ 4510 4511 /*! @name PERIPHID1 - Peripheral ID Register */ 4512 /*! @{ */ 4513 #define ROM_PERIPHID1_PERIPHID_MASK (0xFFFFFFFFU) 4514 #define ROM_PERIPHID1_PERIPHID_SHIFT (0U) 4515 #define ROM_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID1_PERIPHID_SHIFT)) & ROM_PERIPHID1_PERIPHID_MASK) 4516 /*! @} */ 4517 4518 /*! @name PERIPHID2 - Peripheral ID Register */ 4519 /*! @{ */ 4520 #define ROM_PERIPHID2_PERIPHID_MASK (0xFFFFFFFFU) 4521 #define ROM_PERIPHID2_PERIPHID_SHIFT (0U) 4522 #define ROM_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID2_PERIPHID_SHIFT)) & ROM_PERIPHID2_PERIPHID_MASK) 4523 /*! @} */ 4524 4525 /*! @name PERIPHID3 - Peripheral ID Register */ 4526 /*! @{ */ 4527 #define ROM_PERIPHID3_PERIPHID_MASK (0xFFFFFFFFU) 4528 #define ROM_PERIPHID3_PERIPHID_SHIFT (0U) 4529 #define ROM_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID3_PERIPHID_SHIFT)) & ROM_PERIPHID3_PERIPHID_MASK) 4530 /*! @} */ 4531 4532 /*! @name COMPID - Component ID Register */ 4533 /*! @{ */ 4534 #define ROM_COMPID_COMPID_MASK (0xFFFFFFFFU) 4535 #define ROM_COMPID_COMPID_SHIFT (0U) 4536 #define ROM_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x)) << ROM_COMPID_COMPID_SHIFT)) & ROM_COMPID_COMPID_MASK) 4537 /*! @} */ 4538 4539 /* The count of ROM_COMPID */ 4540 #define ROM_COMPID_COUNT (4U) 4541 4542 4543 /*! 4544 * @} 4545 */ /* end of group ROM_Register_Masks */ 4546 4547 4548 /* ROM - Peripheral instance base addresses */ 4549 /** Peripheral ROM base address */ 4550 #define ROM_BASE (0xF0002000u) 4551 /** Peripheral ROM base pointer */ 4552 #define ROM ((ROM_Type *)ROM_BASE) 4553 /** Array initializer of ROM peripheral base addresses */ 4554 #define ROM_BASE_ADDRS { ROM_BASE } 4555 /** Array initializer of ROM peripheral base pointers */ 4556 #define ROM_BASE_PTRS { ROM } 4557 4558 /*! 4559 * @} 4560 */ /* end of group ROM_Peripheral_Access_Layer */ 4561 4562 4563 /* ---------------------------------------------------------------------------- 4564 -- RTC Peripheral Access Layer 4565 ---------------------------------------------------------------------------- */ 4566 4567 /*! 4568 * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer 4569 * @{ 4570 */ 4571 4572 /** RTC - Register Layout Typedef */ 4573 typedef struct { 4574 __IO uint32_t SC; /**< RTC Status and Control Register, offset: 0x0 */ 4575 __IO uint32_t MOD; /**< RTC Modulo Register, offset: 0x4 */ 4576 __I uint32_t CNT; /**< RTC Counter Register, offset: 0x8 */ 4577 } RTC_Type; 4578 4579 /* ---------------------------------------------------------------------------- 4580 -- RTC Register Masks 4581 ---------------------------------------------------------------------------- */ 4582 4583 /*! 4584 * @addtogroup RTC_Register_Masks RTC Register Masks 4585 * @{ 4586 */ 4587 4588 /*! @name SC - RTC Status and Control Register */ 4589 /*! @{ */ 4590 #define RTC_SC_RTCO_MASK (0x10U) 4591 #define RTC_SC_RTCO_SHIFT (4U) 4592 /*! RTCO - Real-Time Counter Output 4593 * 0b0..Real-time counter output disabled. 4594 * 0b1..Real-time counter output enabled. 4595 */ 4596 #define RTC_SC_RTCO(x) (((uint32_t)(((uint32_t)(x)) << RTC_SC_RTCO_SHIFT)) & RTC_SC_RTCO_MASK) 4597 #define RTC_SC_RTIE_MASK (0x40U) 4598 #define RTC_SC_RTIE_SHIFT (6U) 4599 /*! RTIE - Real-Time Interrupt Enable 4600 * 0b0..Real-time interrupt requests are disabled. Use software polling. 4601 * 0b1..Real-time interrupt requests are enabled. 4602 */ 4603 #define RTC_SC_RTIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_SC_RTIE_SHIFT)) & RTC_SC_RTIE_MASK) 4604 #define RTC_SC_RTIF_MASK (0x80U) 4605 #define RTC_SC_RTIF_SHIFT (7U) 4606 /*! RTIF - Real-Time Interrupt Flag 4607 * 0b0..RTC counter has not reached the value in the RTC modulo register. 4608 * 0b1..RTC counter has reached the value in the RTC modulo register. 4609 */ 4610 #define RTC_SC_RTIF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SC_RTIF_SHIFT)) & RTC_SC_RTIF_MASK) 4611 #define RTC_SC_RTCPS_MASK (0x700U) 4612 #define RTC_SC_RTCPS_SHIFT (8U) 4613 /*! RTCPS - Real-Time Clock Prescaler Select 4614 * 0b000..Off 4615 * 0b001..If RTCLKS = x0, it is 1; if RTCLKS = x1, it is 128. 4616 * 0b010..If RTCLKS = x0, it is 2; if RTCLKS = x1, it is 256. 4617 * 0b011..If RTCLKS = x0, it is 4; if RTCLKS = x1, it is 512. 4618 * 0b100..If RTCLKS = x0, it is 8; if RTCLKS = x1, it is 1024. 4619 * 0b101..If RTCLKS = x0, it is 16; if RTCLKS = x1, it is 2048. 4620 * 0b110..If RTCLKS = x0, it is 32; if RTCLKS = x1, it is 100. 4621 * 0b111..If RTCLKS = x0, it is 64; if RTCLKS = x1, it is 1000. 4622 */ 4623 #define RTC_SC_RTCPS(x) (((uint32_t)(((uint32_t)(x)) << RTC_SC_RTCPS_SHIFT)) & RTC_SC_RTCPS_MASK) 4624 #define RTC_SC_RTCLKS_MASK (0xC000U) 4625 #define RTC_SC_RTCLKS_SHIFT (14U) 4626 /*! RTCLKS - Real-Time Clock Source Select 4627 * 0b00..External clock source. 4628 * 0b01..Real-time clock source is 1 kHz (LPOCLK). 4629 * 0b10..Internal reference clock (ICSIRCLK). 4630 * 0b11..Bus clock. 4631 */ 4632 #define RTC_SC_RTCLKS(x) (((uint32_t)(((uint32_t)(x)) << RTC_SC_RTCLKS_SHIFT)) & RTC_SC_RTCLKS_MASK) 4633 /*! @} */ 4634 4635 /*! @name MOD - RTC Modulo Register */ 4636 /*! @{ */ 4637 #define RTC_MOD_MOD_MASK (0xFFFFU) 4638 #define RTC_MOD_MOD_SHIFT (0U) 4639 #define RTC_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << RTC_MOD_MOD_SHIFT)) & RTC_MOD_MOD_MASK) 4640 /*! @} */ 4641 4642 /*! @name CNT - RTC Counter Register */ 4643 /*! @{ */ 4644 #define RTC_CNT_CNT_MASK (0xFFFFU) 4645 #define RTC_CNT_CNT_SHIFT (0U) 4646 #define RTC_CNT_CNT(x) (((uint32_t)(((uint32_t)(x)) << RTC_CNT_CNT_SHIFT)) & RTC_CNT_CNT_MASK) 4647 /*! @} */ 4648 4649 4650 /*! 4651 * @} 4652 */ /* end of group RTC_Register_Masks */ 4653 4654 4655 /* RTC - Peripheral instance base addresses */ 4656 /** Peripheral RTC base address */ 4657 #define RTC_BASE (0x4003D000u) 4658 /** Peripheral RTC base pointer */ 4659 #define RTC ((RTC_Type *)RTC_BASE) 4660 /** Array initializer of RTC peripheral base addresses */ 4661 #define RTC_BASE_ADDRS { RTC_BASE } 4662 /** Array initializer of RTC peripheral base pointers */ 4663 #define RTC_BASE_PTRS { RTC } 4664 /** Interrupt vectors for the RTC peripheral type */ 4665 #define RTC_IRQS { RTC_IRQn } 4666 4667 /*! 4668 * @} 4669 */ /* end of group RTC_Peripheral_Access_Layer */ 4670 4671 4672 /* ---------------------------------------------------------------------------- 4673 -- SIM Peripheral Access Layer 4674 ---------------------------------------------------------------------------- */ 4675 4676 /*! 4677 * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer 4678 * @{ 4679 */ 4680 4681 /** SIM - Register Layout Typedef */ 4682 typedef struct { 4683 __I uint32_t SRSID; /**< System Reset Status and ID Register, offset: 0x0 */ 4684 __IO uint32_t SOPT; /**< System Options Register, offset: 0x4 */ 4685 __IO uint32_t PINSEL; /**< Pin Selection Register, offset: 0x8 */ 4686 __IO uint32_t SCGC; /**< System Clock Gating Control Register, offset: 0xC */ 4687 __I uint32_t UUIDL; /**< Universally Unique Identifier Low Register, offset: 0x10 */ 4688 __I uint32_t UUIDML; /**< Universally Unique Identifier Middle Low Register, offset: 0x14 */ 4689 __I uint32_t UUIDMH; /**< Universally Unique Identifier Middle High Register, offset: 0x18 */ 4690 __IO uint32_t CLKDIV; /**< Clock Divider Register, offset: 0x1C */ 4691 } SIM_Type; 4692 4693 /* ---------------------------------------------------------------------------- 4694 -- SIM Register Masks 4695 ---------------------------------------------------------------------------- */ 4696 4697 /*! 4698 * @addtogroup SIM_Register_Masks SIM Register Masks 4699 * @{ 4700 */ 4701 4702 /*! @name SRSID - System Reset Status and ID Register */ 4703 /*! @{ */ 4704 #define SIM_SRSID_LVD_MASK (0x2U) 4705 #define SIM_SRSID_LVD_SHIFT (1U) 4706 /*! LVD - Low Voltage Detect 4707 * 0b0..Reset is not caused by LVD trip or POR. 4708 * 0b1..Reset is caused by LVD trip or POR. 4709 */ 4710 #define SIM_SRSID_LVD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SRSID_LVD_SHIFT)) & SIM_SRSID_LVD_MASK) 4711 #define SIM_SRSID_LOC_MASK (0x4U) 4712 #define SIM_SRSID_LOC_SHIFT (2U) 4713 /*! LOC - Internal Clock Source Module Reset 4714 * 0b0..Reset is not caused by the ICS module. 4715 * 0b1..Reset is caused by the ICS module. 4716 */ 4717 #define SIM_SRSID_LOC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SRSID_LOC_SHIFT)) & SIM_SRSID_LOC_MASK) 4718 #define SIM_SRSID_WDOG_MASK (0x20U) 4719 #define SIM_SRSID_WDOG_SHIFT (5U) 4720 /*! WDOG - Watchdog (WDOG) 4721 * 0b0..Reset is not caused by WDOG timeout. 4722 * 0b1..Reset is caused by WDOG timeout. 4723 */ 4724 #define SIM_SRSID_WDOG(x) (((uint32_t)(((uint32_t)(x)) << SIM_SRSID_WDOG_SHIFT)) & SIM_SRSID_WDOG_MASK) 4725 #define SIM_SRSID_PIN_MASK (0x40U) 4726 #define SIM_SRSID_PIN_SHIFT (6U) 4727 /*! PIN - External Reset Pin 4728 * 0b0..Reset is not caused by external reset pin. 4729 * 0b1..Reset came from external reset pin. 4730 */ 4731 #define SIM_SRSID_PIN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SRSID_PIN_SHIFT)) & SIM_SRSID_PIN_MASK) 4732 #define SIM_SRSID_POR_MASK (0x80U) 4733 #define SIM_SRSID_POR_SHIFT (7U) 4734 /*! POR - Power-On Reset 4735 * 0b0..Reset not caused by POR. 4736 * 0b1..POR caused reset. 4737 */ 4738 #define SIM_SRSID_POR(x) (((uint32_t)(((uint32_t)(x)) << SIM_SRSID_POR_SHIFT)) & SIM_SRSID_POR_MASK) 4739 #define SIM_SRSID_LOCKUP_MASK (0x200U) 4740 #define SIM_SRSID_LOCKUP_SHIFT (9U) 4741 /*! LOCKUP - Core Lockup 4742 * 0b0..Reset is not caused by core LOCKUP event. 4743 * 0b1..Reset is caused by core LOCKUP event. 4744 */ 4745 #define SIM_SRSID_LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << SIM_SRSID_LOCKUP_SHIFT)) & SIM_SRSID_LOCKUP_MASK) 4746 #define SIM_SRSID_SW_MASK (0x400U) 4747 #define SIM_SRSID_SW_SHIFT (10U) 4748 /*! SW - Software 4749 * 0b0..Reset is not caused by software setting of SYSRESETREQ bit. 4750 * 0b1..Reset caused by software setting of SYSRESETREQ bit 4751 */ 4752 #define SIM_SRSID_SW(x) (((uint32_t)(((uint32_t)(x)) << SIM_SRSID_SW_SHIFT)) & SIM_SRSID_SW_MASK) 4753 #define SIM_SRSID_MDMAP_MASK (0x800U) 4754 #define SIM_SRSID_MDMAP_SHIFT (11U) 4755 /*! MDMAP - MDM-AP System Reset Request 4756 * 0b0..Reset is not caused by host debugger system setting of the System Reset Request bit. 4757 * 0b1..Reset is caused by host debugger system setting of the System Reset Request bit. 4758 */ 4759 #define SIM_SRSID_MDMAP(x) (((uint32_t)(((uint32_t)(x)) << SIM_SRSID_MDMAP_SHIFT)) & SIM_SRSID_MDMAP_MASK) 4760 #define SIM_SRSID_SACKERR_MASK (0x2000U) 4761 #define SIM_SRSID_SACKERR_SHIFT (13U) 4762 /*! SACKERR - Stop Mode Acknowledge Error Reset 4763 * 0b0..Reset is not caused by peripheral failure to acknowledge attempt to enter Stop mode. 4764 * 0b1..Reset is caused by peripheral failure to acknowledge attempt to enter Stop mode. 4765 */ 4766 #define SIM_SRSID_SACKERR(x) (((uint32_t)(((uint32_t)(x)) << SIM_SRSID_SACKERR_SHIFT)) & SIM_SRSID_SACKERR_MASK) 4767 #define SIM_SRSID_PINID_MASK (0xF0000U) 4768 #define SIM_SRSID_PINID_SHIFT (16U) 4769 /*! PINID - Device Pin ID 4770 * 0b0000..8-pin 4771 * 0b0001..16-pin 4772 * 0b0010..20-pin 4773 * 0b0011..24-pin 4774 * 0b0100..32-pin 4775 * 0b0101..44-pin 4776 * 0b0110..48-pin 4777 * 0b0111..64-pin 4778 * 0b1000..80-pin 4779 * 0b1010..100-pin 4780 */ 4781 #define SIM_SRSID_PINID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SRSID_PINID_SHIFT)) & SIM_SRSID_PINID_MASK) 4782 #define SIM_SRSID_RevID_MASK (0xF00000U) 4783 #define SIM_SRSID_RevID_SHIFT (20U) 4784 #define SIM_SRSID_RevID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SRSID_RevID_SHIFT)) & SIM_SRSID_RevID_MASK) 4785 #define SIM_SRSID_SUBFAMID_MASK (0xF000000U) 4786 #define SIM_SRSID_SUBFAMID_SHIFT (24U) 4787 /*! SUBFAMID - Kinetis sub-family ID 4788 * 0b0100..KEx4 sub-family 4789 */ 4790 #define SIM_SRSID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SRSID_SUBFAMID_SHIFT)) & SIM_SRSID_SUBFAMID_MASK) 4791 #define SIM_SRSID_FAMID_MASK (0xF0000000U) 4792 #define SIM_SRSID_FAMID_SHIFT (28U) 4793 /*! FAMID - Kinetis family ID 4794 * 0b0000..KE0x family. 4795 */ 4796 #define SIM_SRSID_FAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SRSID_FAMID_SHIFT)) & SIM_SRSID_FAMID_MASK) 4797 /*! @} */ 4798 4799 /*! @name SOPT - System Options Register */ 4800 /*! @{ */ 4801 #define SIM_SOPT_NMIE_MASK (0x2U) 4802 #define SIM_SOPT_NMIE_SHIFT (1U) 4803 /*! NMIE - NMI Pin Enable 4804 * 0b0..PTB4/KBI1_P6/FTM2_CH4/SPI0_MISO/ACMP1_IN2/NMI pin functions as PTB4, KBI1_P6, FTM2_CH4, SPI0_MISO or ACMP1_IN2. 4805 * 0b1..PTB4/KBI1_P6/FTM2_CH4/SPI0_MISO/ACMP1_IN2/NMI pin functions as NMI. 4806 */ 4807 #define SIM_SOPT_NMIE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT_NMIE_SHIFT)) & SIM_SOPT_NMIE_MASK) 4808 #define SIM_SOPT_RSTPE_MASK (0x4U) 4809 #define SIM_SOPT_RSTPE_SHIFT (2U) 4810 /*! RSTPE - RESET Pin Enable 4811 * 0b0..PTA5/IRQ/TCLK1/RESET pin functions as PTA5, IRQ, or TCLK1. 4812 * 0b1..PTA5/IRQ/TCLK1/RESET pin functions as RESET. 4813 */ 4814 #define SIM_SOPT_RSTPE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT_RSTPE_SHIFT)) & SIM_SOPT_RSTPE_MASK) 4815 #define SIM_SOPT_SWDE_MASK (0x8U) 4816 #define SIM_SOPT_SWDE_SHIFT (3U) 4817 /*! SWDE - Single Wire Debug Port Pin Enable 4818 * 0b0..PTA4/ACMP0_OUT/SWD_DIO as PTA4 or ACMP0_OUT function, PTA0/KBI0_P0/FTM0_CH0/RTCO/ACMP0_IN2/ADC0_SE0/SWD_CLK as PTA0, KBI0_P0, FTM0_CH0, RTCO, ACMP0_IN2 or ADC0_SE0 function. 4819 * 0b1..PTA4/ACMP0_OUT/SWD_DIO as SWD_DIO function, PTA0/KBI0_P0/FTM0_CH0/RTCO/ACMP0_IN2/ADC0_SE0/SWD_CLK as SWD_CLK function. 4820 */ 4821 #define SIM_SOPT_SWDE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT_SWDE_SHIFT)) & SIM_SOPT_SWDE_MASK) 4822 #define SIM_SOPT_ACTRG_MASK (0x20U) 4823 #define SIM_SOPT_ACTRG_SHIFT (5U) 4824 /*! ACTRG - ACMP Trigger FTM2 selection 4825 * 0b0..ACMP0 out 4826 * 0b1..ACMP1 out 4827 */ 4828 #define SIM_SOPT_ACTRG(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT_ACTRG_SHIFT)) & SIM_SOPT_ACTRG_MASK) 4829 #define SIM_SOPT_FTMIC_MASK (0xC0U) 4830 #define SIM_SOPT_FTMIC_SHIFT (6U) 4831 /*! FTMIC - FTM0CH0 Input Capture Source 4832 * 0b00..FTM0_CH0 pin 4833 * 0b01..ACMP0 OUT 4834 * 0b10..ACMP1 OUT 4835 * 0b11..RTC overflow 4836 */ 4837 #define SIM_SOPT_FTMIC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT_FTMIC_SHIFT)) & SIM_SOPT_FTMIC_MASK) 4838 #define SIM_SOPT_RXDFE_MASK (0x300U) 4839 #define SIM_SOPT_RXDFE_SHIFT (8U) 4840 /*! RXDFE - UART0 RxD Filter Select 4841 * 0b00..RXD0 input signal is connected to UART0 module directly. 4842 * 0b01..RXD0 input signal is filtered by ACMP0, then injected to UART0. 4843 * 0b10..RXD0 input signal is filtered by ACMP1, then injected to UART0. 4844 * 0b11..Reserved. 4845 */ 4846 #define SIM_SOPT_RXDFE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT_RXDFE_SHIFT)) & SIM_SOPT_RXDFE_MASK) 4847 #define SIM_SOPT_RXDCE_MASK (0x1000U) 4848 #define SIM_SOPT_RXDCE_SHIFT (12U) 4849 /*! RXDCE - UART0_RX Capture Select 4850 * 0b0..UART0_RX input signal is connected to the UART0 module only. 4851 * 0b1..UART0_RX input signal is connected to the UART0 module and FTM0 channel 1. 4852 */ 4853 #define SIM_SOPT_RXDCE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT_RXDCE_SHIFT)) & SIM_SOPT_RXDCE_MASK) 4854 #define SIM_SOPT_FTMSYNC_MASK (0x4000U) 4855 #define SIM_SOPT_FTMSYNC_SHIFT (14U) 4856 /*! FTMSYNC - FTM2 Synchronization Select 4857 * 0b0..No synchronization triggered. 4858 * 0b1..Generates a PWM synchronization trigger to the FTM2 modules. 4859 */ 4860 #define SIM_SOPT_FTMSYNC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT_FTMSYNC_SHIFT)) & SIM_SOPT_FTMSYNC_MASK) 4861 #define SIM_SOPT_TXDME_MASK (0x8000U) 4862 #define SIM_SOPT_TXDME_SHIFT (15U) 4863 /*! TXDME - UART0_TX Modulation Select 4864 * 0b0..UART0_TX output is connected to pinout directly. 4865 * 0b1..UART0_TX output is modulated by FTM0 channel 0 before mapped to pinout. 4866 */ 4867 #define SIM_SOPT_TXDME(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT_TXDME_SHIFT)) & SIM_SOPT_TXDME_MASK) 4868 #define SIM_SOPT_BUSREF_MASK (0x70000U) 4869 #define SIM_SOPT_BUSREF_SHIFT (16U) 4870 /*! BUSREF - BUS Clock Output select 4871 * 0b000..Bus 4872 * 0b001..Bus divided by 2 4873 * 0b010..Bus divided by 4 4874 * 0b011..Bus divided by 8 4875 * 0b100..Bus divided by 16 4876 * 0b101..Bus divided by 32 4877 * 0b110..Bus divided by 64 4878 * 0b111..Bus divided by 128 4879 */ 4880 #define SIM_SOPT_BUSREF(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT_BUSREF_SHIFT)) & SIM_SOPT_BUSREF_MASK) 4881 #define SIM_SOPT_CLKOE_MASK (0x80000U) 4882 #define SIM_SOPT_CLKOE_SHIFT (19U) 4883 /*! CLKOE - Bus Clock Output Enable 4884 * 0b0..Bus clock output is disabled on PTC5. 4885 * 0b1..Bus clock output is enabled on PTC5. 4886 */ 4887 #define SIM_SOPT_CLKOE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT_CLKOE_SHIFT)) & SIM_SOPT_CLKOE_MASK) 4888 #define SIM_SOPT_ADHWT_MASK (0x700000U) 4889 #define SIM_SOPT_ADHWT_SHIFT (20U) 4890 /*! ADHWT - ADC Hardware Trigger Source 4891 * 0b000..RTC overflow as the ADC hardware trigger 4892 * 0b001..FTM0 init trigger as the ADC hardware trigger 4893 * 0b010..FTM2 init trigger with 8-bit programmable counter delay 4894 * 0b011..FTM2 match trigger with 8-bit programmable counter delay 4895 * 0b100..PIT channel0 overflow as the ADC hardware trigger 4896 * 0b101..PIT channel1 overflow as the ADC hardware trigger 4897 * 0b110..ACMP0 out as the ADC hardware trigger. 4898 * 0b111..ACMP1 out as the ADC hardware trigger 4899 */ 4900 #define SIM_SOPT_ADHWT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT_ADHWT_SHIFT)) & SIM_SOPT_ADHWT_MASK) 4901 #define SIM_SOPT_DLYACT_MASK (0x800000U) 4902 #define SIM_SOPT_DLYACT_SHIFT (23U) 4903 /*! DLYACT - FTM2 Trigger Delay Active 4904 * 0b0..The delay is inactive. 4905 * 0b1..The delay is active. 4906 */ 4907 #define SIM_SOPT_DLYACT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT_DLYACT_SHIFT)) & SIM_SOPT_DLYACT_MASK) 4908 #define SIM_SOPT_DELAY_MASK (0xFF000000U) 4909 #define SIM_SOPT_DELAY_SHIFT (24U) 4910 #define SIM_SOPT_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT_DELAY_SHIFT)) & SIM_SOPT_DELAY_MASK) 4911 /*! @} */ 4912 4913 /*! @name PINSEL - Pin Selection Register */ 4914 /*! @{ */ 4915 #define SIM_PINSEL_I2C0PS_MASK (0x20U) 4916 #define SIM_PINSEL_I2C0PS_SHIFT (5U) 4917 /*! I2C0PS - I2C0 Port Pin Select 4918 * 0b0..I2C0_SCL and I2C0_SDA are mapped on PTA3 and PTA2, respectively. 4919 * 0b1..I2C0_SCL and I2C0_SDA are mapped on PTB7 and PTB6, respectively. 4920 */ 4921 #define SIM_PINSEL_I2C0PS(x) (((uint32_t)(((uint32_t)(x)) << SIM_PINSEL_I2C0PS_SHIFT)) & SIM_PINSEL_I2C0PS_MASK) 4922 #define SIM_PINSEL_SPI0PS_MASK (0x40U) 4923 #define SIM_PINSEL_SPI0PS_SHIFT (6U) 4924 /*! SPI0PS - SPI0 Pin Select 4925 * 0b0..SPI0_SCK, SPI0_MOSI, SPI0_MISO, and SPI0_PCS are mapped on PTB2, PTB3, PTB4, and PTB5. 4926 * 0b1..SPI0_SCK, SPI0_MOSI, SPI0_MISO, and SPI0_PCS are mapped on PTA6, PTA7, PTB1, and PTB0. 4927 */ 4928 #define SIM_PINSEL_SPI0PS(x) (((uint32_t)(((uint32_t)(x)) << SIM_PINSEL_SPI0PS_SHIFT)) & SIM_PINSEL_SPI0PS_MASK) 4929 #define SIM_PINSEL_UART0PS_MASK (0x80U) 4930 #define SIM_PINSEL_UART0PS_SHIFT (7U) 4931 /*! UART0PS - UART0 Pin Select 4932 * 0b0..UART0_RX and UART0_TX are mapped on PTB0 and PTB1. 4933 * 0b1..UART0_RX and UART0_TX are mapped on PTA2 and PTA3. 4934 */ 4935 #define SIM_PINSEL_UART0PS(x) (((uint32_t)(((uint32_t)(x)) << SIM_PINSEL_UART0PS_SHIFT)) & SIM_PINSEL_UART0PS_MASK) 4936 #define SIM_PINSEL_FTM0PS0_MASK (0x100U) 4937 #define SIM_PINSEL_FTM0PS0_SHIFT (8U) 4938 /*! FTM0PS0 - FTM0_CH0 Port Pin Select 4939 * 0b0..FTM0_CH0 channels are mapped on PTA0. 4940 * 0b1..FTM0_CH0 channels are mapped on PTB2. 4941 */ 4942 #define SIM_PINSEL_FTM0PS0(x) (((uint32_t)(((uint32_t)(x)) << SIM_PINSEL_FTM0PS0_SHIFT)) & SIM_PINSEL_FTM0PS0_MASK) 4943 #define SIM_PINSEL_FTM0PS1_MASK (0x200U) 4944 #define SIM_PINSEL_FTM0PS1_SHIFT (9U) 4945 /*! FTM0PS1 - FTM0_CH1 Port Pin Select 4946 * 0b0..FTM0_CH1 channels are mapped on PTA1. 4947 * 0b1..FTM0_CH1 channels are mapped on PTB3. 4948 */ 4949 #define SIM_PINSEL_FTM0PS1(x) (((uint32_t)(((uint32_t)(x)) << SIM_PINSEL_FTM0PS1_SHIFT)) & SIM_PINSEL_FTM0PS1_MASK) 4950 #define SIM_PINSEL_FTM2PS2_MASK (0x4000U) 4951 #define SIM_PINSEL_FTM2PS2_SHIFT (14U) 4952 /*! FTM2PS2 - FTM2_CH2 Port Pin Select 4953 * 0b0..FTM2_CH2 channels are mapped on PTC2. 4954 * 0b1..FTM2_CH2 channels are mapped on PTC4. 4955 */ 4956 #define SIM_PINSEL_FTM2PS2(x) (((uint32_t)(((uint32_t)(x)) << SIM_PINSEL_FTM2PS2_SHIFT)) & SIM_PINSEL_FTM2PS2_MASK) 4957 #define SIM_PINSEL_FTM2PS3_MASK (0x8000U) 4958 #define SIM_PINSEL_FTM2PS3_SHIFT (15U) 4959 /*! FTM2PS3 - FTM2_CH3 Port Pin Select 4960 * 0b0..FTM2_CH3 channels are mapped on PTC3. 4961 * 0b1..FTM2_CH3 channels are mapped on PTC5. 4962 */ 4963 #define SIM_PINSEL_FTM2PS3(x) (((uint32_t)(((uint32_t)(x)) << SIM_PINSEL_FTM2PS3_SHIFT)) & SIM_PINSEL_FTM2PS3_MASK) 4964 #define SIM_PINSEL_FTM0CLKPS_MASK (0x10000000U) 4965 #define SIM_PINSEL_FTM0CLKPS_SHIFT (28U) 4966 /*! FTM0CLKPS - FTM0 TCLK Pin Select 4967 * 0b0..Selects TCLK1 for FTM0 module. 4968 * 0b1..Selects TCLK2 for FTM0 module. 4969 */ 4970 #define SIM_PINSEL_FTM0CLKPS(x) (((uint32_t)(((uint32_t)(x)) << SIM_PINSEL_FTM0CLKPS_SHIFT)) & SIM_PINSEL_FTM0CLKPS_MASK) 4971 #define SIM_PINSEL_FTM2CLKPS_MASK (0x40000000U) 4972 #define SIM_PINSEL_FTM2CLKPS_SHIFT (30U) 4973 /*! FTM2CLKPS - FTM2 TCLK Pin Select 4974 * 0b0..Selects TCLK1 for FTM2 module. 4975 * 0b1..Selects TCLK2 for FTM2 module. 4976 */ 4977 #define SIM_PINSEL_FTM2CLKPS(x) (((uint32_t)(((uint32_t)(x)) << SIM_PINSEL_FTM2CLKPS_SHIFT)) & SIM_PINSEL_FTM2CLKPS_MASK) 4978 #define SIM_PINSEL_PWTCLKPS_MASK (0x80000000U) 4979 #define SIM_PINSEL_PWTCLKPS_SHIFT (31U) 4980 /*! PWTCLKPS - PWT TCLK Pin Select 4981 * 0b0..Selects TCLK1 for PWT module. 4982 * 0b1..Selects TCLK2 for PWT module. 4983 */ 4984 #define SIM_PINSEL_PWTCLKPS(x) (((uint32_t)(((uint32_t)(x)) << SIM_PINSEL_PWTCLKPS_SHIFT)) & SIM_PINSEL_PWTCLKPS_MASK) 4985 /*! @} */ 4986 4987 /*! @name SCGC - System Clock Gating Control Register */ 4988 /*! @{ */ 4989 #define SIM_SCGC_RTC_MASK (0x1U) 4990 #define SIM_SCGC_RTC_SHIFT (0U) 4991 /*! RTC - RTC Clock Gate Control 4992 * 0b0..Bus clock to the RTC module is disabled. 4993 * 0b1..Bus clock to the RTC module is enabled. 4994 */ 4995 #define SIM_SCGC_RTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC_RTC_SHIFT)) & SIM_SCGC_RTC_MASK) 4996 #define SIM_SCGC_PIT_MASK (0x2U) 4997 #define SIM_SCGC_PIT_SHIFT (1U) 4998 /*! PIT - PIT Clock Gate Control 4999 * 0b0..Bus clock to the PIT module is disabled. 5000 * 0b1..Bus clock to the PIT module is enabled. 5001 */ 5002 #define SIM_SCGC_PIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC_PIT_SHIFT)) & SIM_SCGC_PIT_MASK) 5003 #define SIM_SCGC_PWT_MASK (0x10U) 5004 #define SIM_SCGC_PWT_SHIFT (4U) 5005 /*! PWT - PWT Clock Gate Control 5006 * 0b0..Timer clock to the PWT module is disabled. 5007 * 0b1..Timer clock to the PWT module is enabled. 5008 */ 5009 #define SIM_SCGC_PWT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC_PWT_SHIFT)) & SIM_SCGC_PWT_MASK) 5010 #define SIM_SCGC_FTM0_MASK (0x20U) 5011 #define SIM_SCGC_FTM0_SHIFT (5U) 5012 /*! FTM0 - FTM0 Clock Gate Control 5013 * 0b0..Bus clock to the FTM0 module is disabled. 5014 * 0b1..Bus clock to the FTM0 module is enabled. 5015 */ 5016 #define SIM_SCGC_FTM0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC_FTM0_SHIFT)) & SIM_SCGC_FTM0_MASK) 5017 #define SIM_SCGC_FTM2_MASK (0x80U) 5018 #define SIM_SCGC_FTM2_SHIFT (7U) 5019 /*! FTM2 - FTM2 Clock Gate Control 5020 * 0b0..Bus clock to the FTM2 module is disabled. 5021 * 0b1..Bus clock to the FTM2 module is enabled. 5022 */ 5023 #define SIM_SCGC_FTM2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC_FTM2_SHIFT)) & SIM_SCGC_FTM2_MASK) 5024 #define SIM_SCGC_CRC_MASK (0x400U) 5025 #define SIM_SCGC_CRC_SHIFT (10U) 5026 /*! CRC - CRC Clock Gate Control 5027 * 0b0..Bus clock to the CRC module is disabled. 5028 * 0b1..Bus clock to the CRC module is enabled. 5029 */ 5030 #define SIM_SCGC_CRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC_CRC_SHIFT)) & SIM_SCGC_CRC_MASK) 5031 #define SIM_SCGC_FLASH_MASK (0x1000U) 5032 #define SIM_SCGC_FLASH_SHIFT (12U) 5033 /*! FLASH - Flash Clock Gate Control 5034 * 0b0..Bus clock to the flash module is disabled. 5035 * 0b1..Bus clock to the flash module is enabled. 5036 */ 5037 #define SIM_SCGC_FLASH(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC_FLASH_SHIFT)) & SIM_SCGC_FLASH_MASK) 5038 #define SIM_SCGC_SWD_MASK (0x2000U) 5039 #define SIM_SCGC_SWD_SHIFT (13U) 5040 /*! SWD - SWD (single wire debugger) Clock Gate Control 5041 * 0b0..Bus clock to the SWD module is disabled. 5042 * 0b1..Bus clock to the SWD module is enabled. 5043 */ 5044 #define SIM_SCGC_SWD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC_SWD_SHIFT)) & SIM_SCGC_SWD_MASK) 5045 #define SIM_SCGC_I2C_MASK (0x20000U) 5046 #define SIM_SCGC_I2C_SHIFT (17U) 5047 /*! I2C - I2C Clock Gate Control 5048 * 0b0..Bus clock to the IIC module is disabled. 5049 * 0b1..Bus clock to the IIC module is enabled. 5050 */ 5051 #define SIM_SCGC_I2C(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC_I2C_SHIFT)) & SIM_SCGC_I2C_MASK) 5052 #define SIM_SCGC_SPI0_MASK (0x40000U) 5053 #define SIM_SCGC_SPI0_SHIFT (18U) 5054 /*! SPI0 - SPI0 Clock Gate Control 5055 * 0b0..Bus clock to the SPI0 module is disabled. 5056 * 0b1..Bus clock to the SPI0 module is enabled. 5057 */ 5058 #define SIM_SCGC_SPI0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC_SPI0_SHIFT)) & SIM_SCGC_SPI0_MASK) 5059 #define SIM_SCGC_UART0_MASK (0x100000U) 5060 #define SIM_SCGC_UART0_SHIFT (20U) 5061 /*! UART0 - UART0 Clock Gate Control 5062 * 0b0..Bus clock to the UART0 module is disabled. 5063 * 0b1..Bus clock to the UART0 module is enabled. 5064 */ 5065 #define SIM_SCGC_UART0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC_UART0_SHIFT)) & SIM_SCGC_UART0_MASK) 5066 #define SIM_SCGC_KBI0_MASK (0x1000000U) 5067 #define SIM_SCGC_KBI0_SHIFT (24U) 5068 /*! KBI0 - KBI0 Clock Gate Control 5069 * 0b0..Bus clock to the KBI0 module is disabled. 5070 * 0b1..Bus clock to the KBI0 module is enabled. 5071 */ 5072 #define SIM_SCGC_KBI0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC_KBI0_SHIFT)) & SIM_SCGC_KBI0_MASK) 5073 #define SIM_SCGC_KBI1_MASK (0x2000000U) 5074 #define SIM_SCGC_KBI1_SHIFT (25U) 5075 /*! KBI1 - KBI1 Clock Gate Control 5076 * 0b0..Bus clock to the KBI1 module is disabled. 5077 * 0b1..Bus clock to the KBI1 module is enabled. 5078 */ 5079 #define SIM_SCGC_KBI1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC_KBI1_SHIFT)) & SIM_SCGC_KBI1_MASK) 5080 #define SIM_SCGC_IRQ_MASK (0x8000000U) 5081 #define SIM_SCGC_IRQ_SHIFT (27U) 5082 /*! IRQ - IRQ Clock Gate Control 5083 * 0b0..Bus clock to the IRQ module is disabled. 5084 * 0b1..Bus clock to the IRQ module is enabled. 5085 */ 5086 #define SIM_SCGC_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC_IRQ_SHIFT)) & SIM_SCGC_IRQ_MASK) 5087 #define SIM_SCGC_ADC_MASK (0x20000000U) 5088 #define SIM_SCGC_ADC_SHIFT (29U) 5089 /*! ADC - ADC Clock Gate Control 5090 * 0b0..Bus clock to the ADC module is disabled. 5091 * 0b1..Bus clock to the ADC module is enabled. 5092 */ 5093 #define SIM_SCGC_ADC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC_ADC_SHIFT)) & SIM_SCGC_ADC_MASK) 5094 #define SIM_SCGC_ACMP0_MASK (0x40000000U) 5095 #define SIM_SCGC_ACMP0_SHIFT (30U) 5096 /*! ACMP0 - ACMP0 Clock Gate Control 5097 * 0b0..Bus clock to the ACMP0 module is disabled. 5098 * 0b1..Bus clock to the ACMP0 module is enabled. 5099 */ 5100 #define SIM_SCGC_ACMP0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC_ACMP0_SHIFT)) & SIM_SCGC_ACMP0_MASK) 5101 #define SIM_SCGC_ACMP1_MASK (0x80000000U) 5102 #define SIM_SCGC_ACMP1_SHIFT (31U) 5103 /*! ACMP1 - ACMP1 Clock Gate Control 5104 * 0b0..Bus clock to the ACMP1 module is disabled. 5105 * 0b1..Bus clock to the ACMP1 module is enabled. 5106 */ 5107 #define SIM_SCGC_ACMP1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC_ACMP1_SHIFT)) & SIM_SCGC_ACMP1_MASK) 5108 /*! @} */ 5109 5110 /*! @name UUIDL - Universally Unique Identifier Low Register */ 5111 /*! @{ */ 5112 #define SIM_UUIDL_ID_MASK (0xFFFFFFFFU) 5113 #define SIM_UUIDL_ID_SHIFT (0U) 5114 #define SIM_UUIDL_ID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UUIDL_ID_SHIFT)) & SIM_UUIDL_ID_MASK) 5115 /*! @} */ 5116 5117 /*! @name UUIDML - Universally Unique Identifier Middle Low Register */ 5118 /*! @{ */ 5119 #define SIM_UUIDML_ID_MASK (0xFFFFFFFFU) 5120 #define SIM_UUIDML_ID_SHIFT (0U) 5121 #define SIM_UUIDML_ID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UUIDML_ID_SHIFT)) & SIM_UUIDML_ID_MASK) 5122 /*! @} */ 5123 5124 /*! @name UUIDMH - Universally Unique Identifier Middle High Register */ 5125 /*! @{ */ 5126 #define SIM_UUIDMH_ID_MASK (0xFFFFU) 5127 #define SIM_UUIDMH_ID_SHIFT (0U) 5128 #define SIM_UUIDMH_ID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UUIDMH_ID_SHIFT)) & SIM_UUIDMH_ID_MASK) 5129 /*! @} */ 5130 5131 /*! @name CLKDIV - Clock Divider Register */ 5132 /*! @{ */ 5133 #define SIM_CLKDIV_OUTDIV3_MASK (0x100000U) 5134 #define SIM_CLKDIV_OUTDIV3_SHIFT (20U) 5135 /*! OUTDIV3 - Clock 3 output divider value 5136 * 0b0..Same as ICSOUTCLK. 5137 * 0b1..ICSOUTCLK divides by 2. 5138 */ 5139 #define SIM_CLKDIV_OUTDIV3(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV_OUTDIV3_SHIFT)) & SIM_CLKDIV_OUTDIV3_MASK) 5140 #define SIM_CLKDIV_OUTDIV2_MASK (0x1000000U) 5141 #define SIM_CLKDIV_OUTDIV2_SHIFT (24U) 5142 /*! OUTDIV2 - Clock 2 output divider value 5143 * 0b0..Not divided from divider1. 5144 * 0b1..Divide by 2 from divider1. 5145 */ 5146 #define SIM_CLKDIV_OUTDIV2(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV_OUTDIV2_SHIFT)) & SIM_CLKDIV_OUTDIV2_MASK) 5147 #define SIM_CLKDIV_OUTDIV1_MASK (0x30000000U) 5148 #define SIM_CLKDIV_OUTDIV1_SHIFT (28U) 5149 /*! OUTDIV1 - Clock 1 output divider value 5150 * 0b00..Same as ICSOUTCLK. 5151 * 0b01..ICSOUTCLK divides by 2. 5152 * 0b10..ICSOUTCLK divides by 3. 5153 * 0b11..ICSOUTCLK divides by 4. 5154 */ 5155 #define SIM_CLKDIV_OUTDIV1(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV_OUTDIV1_SHIFT)) & SIM_CLKDIV_OUTDIV1_MASK) 5156 /*! @} */ 5157 5158 5159 /*! 5160 * @} 5161 */ /* end of group SIM_Register_Masks */ 5162 5163 5164 /* SIM - Peripheral instance base addresses */ 5165 /** Peripheral SIM base address */ 5166 #define SIM_BASE (0x40048000u) 5167 /** Peripheral SIM base pointer */ 5168 #define SIM ((SIM_Type *)SIM_BASE) 5169 /** Array initializer of SIM peripheral base addresses */ 5170 #define SIM_BASE_ADDRS { SIM_BASE } 5171 /** Array initializer of SIM peripheral base pointers */ 5172 #define SIM_BASE_PTRS { SIM } 5173 5174 /*! 5175 * @} 5176 */ /* end of group SIM_Peripheral_Access_Layer */ 5177 5178 5179 /* ---------------------------------------------------------------------------- 5180 -- SPI Peripheral Access Layer 5181 ---------------------------------------------------------------------------- */ 5182 5183 /*! 5184 * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer 5185 * @{ 5186 */ 5187 5188 /** SPI - Register Layout Typedef */ 5189 typedef struct { 5190 __IO uint8_t C1; /**< SPI Control Register 1, offset: 0x0 */ 5191 __IO uint8_t C2; /**< SPI Control Register 2, offset: 0x1 */ 5192 __IO uint8_t BR; /**< SPI Baud Rate Register, offset: 0x2 */ 5193 __IO uint8_t S; /**< SPI Status Register, offset: 0x3 */ 5194 uint8_t RESERVED_0[1]; 5195 __IO uint8_t D; /**< SPI Data Register, offset: 0x5 */ 5196 uint8_t RESERVED_1[1]; 5197 __IO uint8_t M; /**< SPI Match Register, offset: 0x7 */ 5198 } SPI_Type; 5199 5200 /* ---------------------------------------------------------------------------- 5201 -- SPI Register Masks 5202 ---------------------------------------------------------------------------- */ 5203 5204 /*! 5205 * @addtogroup SPI_Register_Masks SPI Register Masks 5206 * @{ 5207 */ 5208 5209 /*! @name C1 - SPI Control Register 1 */ 5210 /*! @{ */ 5211 #define SPI_C1_LSBFE_MASK (0x1U) 5212 #define SPI_C1_LSBFE_SHIFT (0U) 5213 /*! LSBFE - LSB First (shifter direction) 5214 * 0b0..SPI serial data transfers start with the most significant bit. 5215 * 0b1..SPI serial data transfers start with the least significant bit. 5216 */ 5217 #define SPI_C1_LSBFE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_LSBFE_SHIFT)) & SPI_C1_LSBFE_MASK) 5218 #define SPI_C1_SSOE_MASK (0x2U) 5219 #define SPI_C1_SSOE_SHIFT (1U) 5220 /*! SSOE - Slave Select Output Enable 5221 * 0b0..When C2[MODFEN] is 0: In master mode, SS pin function is general-purpose I/O (not SPI). In slave mode, SS pin function is slave select input. When C2[MODFEN] is 1: In master mode, SS pin function is SS input for mode fault. In slave mode, SS pin function is slave select input. 5222 * 0b1..When C2[MODFEN] is 0: In master mode, SS pin function is general-purpose I/O (not SPI). In slave mode, SS pin function is slave select input. When C2[MODFEN] is 1: In master mode, SS pin function is automatic SS output. In slave mode: SS pin function is slave select input. 5223 */ 5224 #define SPI_C1_SSOE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_SSOE_SHIFT)) & SPI_C1_SSOE_MASK) 5225 #define SPI_C1_CPHA_MASK (0x4U) 5226 #define SPI_C1_CPHA_SHIFT (2U) 5227 /*! CPHA - Clock Phase 5228 * 0b0..First edge on SPSCK occurs at the middle of the first cycle of a data transfer. 5229 * 0b1..First edge on SPSCK occurs at the start of the first cycle of a data transfer. 5230 */ 5231 #define SPI_C1_CPHA(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_CPHA_SHIFT)) & SPI_C1_CPHA_MASK) 5232 #define SPI_C1_CPOL_MASK (0x8U) 5233 #define SPI_C1_CPOL_SHIFT (3U) 5234 /*! CPOL - Clock Polarity 5235 * 0b0..Active-high SPI clock (idles low) 5236 * 0b1..Active-low SPI clock (idles high) 5237 */ 5238 #define SPI_C1_CPOL(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_CPOL_SHIFT)) & SPI_C1_CPOL_MASK) 5239 #define SPI_C1_MSTR_MASK (0x10U) 5240 #define SPI_C1_MSTR_SHIFT (4U) 5241 /*! MSTR - Master/Slave Mode Select 5242 * 0b0..SPI module configured as a slave SPI device 5243 * 0b1..SPI module configured as a master SPI device 5244 */ 5245 #define SPI_C1_MSTR(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_MSTR_SHIFT)) & SPI_C1_MSTR_MASK) 5246 #define SPI_C1_SPTIE_MASK (0x20U) 5247 #define SPI_C1_SPTIE_SHIFT (5U) 5248 /*! SPTIE - SPI Transmit Interrupt Enable 5249 * 0b0..Interrupts from SPTEF inhibited (use polling) 5250 * 0b1..When SPTEF is 1, hardware interrupt requested 5251 */ 5252 #define SPI_C1_SPTIE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_SPTIE_SHIFT)) & SPI_C1_SPTIE_MASK) 5253 #define SPI_C1_SPE_MASK (0x40U) 5254 #define SPI_C1_SPE_SHIFT (6U) 5255 /*! SPE - SPI System Enable 5256 * 0b0..SPI system inactive 5257 * 0b1..SPI system enabled 5258 */ 5259 #define SPI_C1_SPE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_SPE_SHIFT)) & SPI_C1_SPE_MASK) 5260 #define SPI_C1_SPIE_MASK (0x80U) 5261 #define SPI_C1_SPIE_SHIFT (7U) 5262 /*! SPIE - SPI Interrupt Enable: for SPRF and MODF 5263 * 0b0..Interrupts from SPRF and MODF are inhibited-use polling 5264 * 0b1..Request a hardware interrupt when SPRF or MODF is 1 5265 */ 5266 #define SPI_C1_SPIE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_SPIE_SHIFT)) & SPI_C1_SPIE_MASK) 5267 /*! @} */ 5268 5269 /*! @name C2 - SPI Control Register 2 */ 5270 /*! @{ */ 5271 #define SPI_C2_SPC0_MASK (0x1U) 5272 #define SPI_C2_SPC0_SHIFT (0U) 5273 /*! SPC0 - SPI Pin Control 0 5274 * 0b0..SPI uses separate pins for data input and data output (pin mode is normal). In master mode of operation: MISO is master in and MOSI is master out. In slave mode of operation: MISO is slave out and MOSI is slave in. 5275 * 0b1..SPI configured for single-wire bidirectional operation (pin mode is bidirectional). In master mode of operation: MISO is not used by SPI; MOSI is master in when BIDIROE is 0 or master I/O when BIDIROE is 1. In slave mode of operation: MISO is slave in when BIDIROE is 0 or slave I/O when BIDIROE is 1; MOSI is not used by SPI. 5276 */ 5277 #define SPI_C2_SPC0(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_SPC0_SHIFT)) & SPI_C2_SPC0_MASK) 5278 #define SPI_C2_SPISWAI_MASK (0x2U) 5279 #define SPI_C2_SPISWAI_SHIFT (1U) 5280 /*! SPISWAI - SPI Stop in Wait Mode 5281 * 0b0..SPI clocks continue to operate in Wait mode. 5282 * 0b1..SPI clocks stop when the MCU enters Wait mode. 5283 */ 5284 #define SPI_C2_SPISWAI(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_SPISWAI_SHIFT)) & SPI_C2_SPISWAI_MASK) 5285 #define SPI_C2_BIDIROE_MASK (0x8U) 5286 #define SPI_C2_BIDIROE_SHIFT (3U) 5287 /*! BIDIROE - Bidirectional Mode Output Enable 5288 * 0b0..Output driver disabled so SPI data I/O pin acts as an input 5289 * 0b1..SPI I/O pin enabled as an output 5290 */ 5291 #define SPI_C2_BIDIROE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_BIDIROE_SHIFT)) & SPI_C2_BIDIROE_MASK) 5292 #define SPI_C2_MODFEN_MASK (0x10U) 5293 #define SPI_C2_MODFEN_SHIFT (4U) 5294 /*! MODFEN - Master Mode-Fault Function Enable 5295 * 0b0..Mode fault function disabled, master SS pin reverts to general-purpose I/O not controlled by SPI 5296 * 0b1..Mode fault function enabled, master SS pin acts as the mode fault input or the slave select output 5297 */ 5298 #define SPI_C2_MODFEN(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_MODFEN_SHIFT)) & SPI_C2_MODFEN_MASK) 5299 #define SPI_C2_SPMIE_MASK (0x80U) 5300 #define SPI_C2_SPMIE_SHIFT (7U) 5301 /*! SPMIE - SPI Match Interrupt Enable 5302 * 0b0..Interrupts from SPMF inhibited (use polling) 5303 * 0b1..When SPMF is 1, requests a hardware interrupt 5304 */ 5305 #define SPI_C2_SPMIE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_SPMIE_SHIFT)) & SPI_C2_SPMIE_MASK) 5306 /*! @} */ 5307 5308 /*! @name BR - SPI Baud Rate Register */ 5309 /*! @{ */ 5310 #define SPI_BR_SPR_MASK (0xFU) 5311 #define SPI_BR_SPR_SHIFT (0U) 5312 /*! SPR - SPI Baud Rate Divisor 5313 * 0b0000..Baud rate divisor is 2. 5314 * 0b0001..Baud rate divisor is 4. 5315 * 0b0010..Baud rate divisor is 8. 5316 * 0b0011..Baud rate divisor is 16. 5317 * 0b0100..Baud rate divisor is 32. 5318 * 0b0101..Baud rate divisor is 64. 5319 * 0b0110..Baud rate divisor is 128. 5320 * 0b0111..Baud rate divisor is 256. 5321 * 0b1000..Baud rate divisor is 512. 5322 */ 5323 #define SPI_BR_SPR(x) (((uint8_t)(((uint8_t)(x)) << SPI_BR_SPR_SHIFT)) & SPI_BR_SPR_MASK) 5324 #define SPI_BR_SPPR_MASK (0x70U) 5325 #define SPI_BR_SPPR_SHIFT (4U) 5326 /*! SPPR - SPI Baud Rate Prescale Divisor 5327 * 0b000..Baud rate prescaler divisor is 1. 5328 * 0b001..Baud rate prescaler divisor is 2. 5329 * 0b010..Baud rate prescaler divisor is 3. 5330 * 0b011..Baud rate prescaler divisor is 4. 5331 * 0b100..Baud rate prescaler divisor is 5. 5332 * 0b101..Baud rate prescaler divisor is 6. 5333 * 0b110..Baud rate prescaler divisor is 7. 5334 * 0b111..Baud rate prescaler divisor is 8. 5335 */ 5336 #define SPI_BR_SPPR(x) (((uint8_t)(((uint8_t)(x)) << SPI_BR_SPPR_SHIFT)) & SPI_BR_SPPR_MASK) 5337 /*! @} */ 5338 5339 /*! @name S - SPI Status Register */ 5340 /*! @{ */ 5341 #define SPI_S_MODF_MASK (0x10U) 5342 #define SPI_S_MODF_SHIFT (4U) 5343 /*! MODF - Master Mode Fault Flag 5344 * 0b0..No mode fault error 5345 * 0b1..Mode fault error detected 5346 */ 5347 #define SPI_S_MODF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_MODF_SHIFT)) & SPI_S_MODF_MASK) 5348 #define SPI_S_SPTEF_MASK (0x20U) 5349 #define SPI_S_SPTEF_SHIFT (5U) 5350 /*! SPTEF - SPI Transmit Buffer Empty Flag 5351 * 0b0..SPI transmit buffer not empty 5352 * 0b1..SPI transmit buffer empty 5353 */ 5354 #define SPI_S_SPTEF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_SPTEF_SHIFT)) & SPI_S_SPTEF_MASK) 5355 #define SPI_S_SPMF_MASK (0x40U) 5356 #define SPI_S_SPMF_SHIFT (6U) 5357 /*! SPMF - SPI Match Flag 5358 * 0b0..Value in the receive data buffer does not match the value in the M register 5359 * 0b1..Value in the receive data buffer matches the value in the M register 5360 */ 5361 #define SPI_S_SPMF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_SPMF_SHIFT)) & SPI_S_SPMF_MASK) 5362 #define SPI_S_SPRF_MASK (0x80U) 5363 #define SPI_S_SPRF_SHIFT (7U) 5364 /*! SPRF - SPI Read Buffer Full Flag 5365 * 0b0..No data available in the receive data buffer 5366 * 0b1..Data available in the receive data buffer 5367 */ 5368 #define SPI_S_SPRF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_SPRF_SHIFT)) & SPI_S_SPRF_MASK) 5369 /*! @} */ 5370 5371 /*! @name D - SPI Data Register */ 5372 /*! @{ */ 5373 #define SPI_D_Bits_MASK (0xFFU) 5374 #define SPI_D_Bits_SHIFT (0U) 5375 #define SPI_D_Bits(x) (((uint8_t)(((uint8_t)(x)) << SPI_D_Bits_SHIFT)) & SPI_D_Bits_MASK) 5376 /*! @} */ 5377 5378 /*! @name M - SPI Match Register */ 5379 /*! @{ */ 5380 #define SPI_M_Bits_MASK (0xFFU) 5381 #define SPI_M_Bits_SHIFT (0U) 5382 #define SPI_M_Bits(x) (((uint8_t)(((uint8_t)(x)) << SPI_M_Bits_SHIFT)) & SPI_M_Bits_MASK) 5383 /*! @} */ 5384 5385 5386 /*! 5387 * @} 5388 */ /* end of group SPI_Register_Masks */ 5389 5390 5391 /* SPI - Peripheral instance base addresses */ 5392 /** Peripheral SPI0 base address */ 5393 #define SPI0_BASE (0x40076000u) 5394 /** Peripheral SPI0 base pointer */ 5395 #define SPI0 ((SPI_Type *)SPI0_BASE) 5396 /** Array initializer of SPI peripheral base addresses */ 5397 #define SPI_BASE_ADDRS { SPI0_BASE } 5398 /** Array initializer of SPI peripheral base pointers */ 5399 #define SPI_BASE_PTRS { SPI0 } 5400 /** Interrupt vectors for the SPI peripheral type */ 5401 #define SPI_IRQS { SPI0_IRQn } 5402 5403 /*! 5404 * @} 5405 */ /* end of group SPI_Peripheral_Access_Layer */ 5406 5407 5408 /* ---------------------------------------------------------------------------- 5409 -- UART Peripheral Access Layer 5410 ---------------------------------------------------------------------------- */ 5411 5412 /*! 5413 * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer 5414 * @{ 5415 */ 5416 5417 /** UART - Register Layout Typedef */ 5418 typedef struct { 5419 __IO uint8_t BDH; /**< UART Baud Rate Register: High, offset: 0x0 */ 5420 __IO uint8_t BDL; /**< UART Baud Rate Register: Low, offset: 0x1 */ 5421 __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */ 5422 __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */ 5423 __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */ 5424 __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */ 5425 __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */ 5426 __IO uint8_t D; /**< UART Data Register, offset: 0x7 */ 5427 } UART_Type; 5428 5429 /* ---------------------------------------------------------------------------- 5430 -- UART Register Masks 5431 ---------------------------------------------------------------------------- */ 5432 5433 /*! 5434 * @addtogroup UART_Register_Masks UART Register Masks 5435 * @{ 5436 */ 5437 5438 /*! @name BDH - UART Baud Rate Register: High */ 5439 /*! @{ */ 5440 #define UART_BDH_SBR_MASK (0x1FU) 5441 #define UART_BDH_SBR_SHIFT (0U) 5442 #define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_SBR_SHIFT)) & UART_BDH_SBR_MASK) 5443 #define UART_BDH_SBNS_MASK (0x20U) 5444 #define UART_BDH_SBNS_SHIFT (5U) 5445 /*! SBNS - Stop Bit Number Select 5446 * 0b0..One stop bit. 5447 * 0b1..Two stop bit. 5448 */ 5449 #define UART_BDH_SBNS(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_SBNS_SHIFT)) & UART_BDH_SBNS_MASK) 5450 #define UART_BDH_RXEDGIE_MASK (0x40U) 5451 #define UART_BDH_RXEDGIE_SHIFT (6U) 5452 /*! RXEDGIE - RxD Input Active Edge Interrupt Enable (for RXEDGIF) 5453 * 0b0..Hardware interrupts from UART_S2[RXEDGIF] disabled (use polling). 5454 * 0b1..Hardware interrupt requested when UART_S2[RXEDGIF] flag is 1. 5455 */ 5456 #define UART_BDH_RXEDGIE(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_RXEDGIE_SHIFT)) & UART_BDH_RXEDGIE_MASK) 5457 #define UART_BDH_LBKDIE_MASK (0x80U) 5458 #define UART_BDH_LBKDIE_SHIFT (7U) 5459 /*! LBKDIE - LIN Break Detect Interrupt Enable (for LBKDIF) 5460 * 0b0..Hardware interrupts from UART_S2[LBKDIF] disabled (use polling). 5461 * 0b1..Hardware interrupt requested when UART_S2[LBKDIF] flag is 1. 5462 */ 5463 #define UART_BDH_LBKDIE(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_LBKDIE_SHIFT)) & UART_BDH_LBKDIE_MASK) 5464 /*! @} */ 5465 5466 /*! @name BDL - UART Baud Rate Register: Low */ 5467 /*! @{ */ 5468 #define UART_BDL_SBR_MASK (0xFFU) 5469 #define UART_BDL_SBR_SHIFT (0U) 5470 #define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART_BDL_SBR_SHIFT)) & UART_BDL_SBR_MASK) 5471 /*! @} */ 5472 5473 /*! @name C1 - UART Control Register 1 */ 5474 /*! @{ */ 5475 #define UART_C1_PT_MASK (0x1U) 5476 #define UART_C1_PT_SHIFT (0U) 5477 /*! PT - Parity Type 5478 * 0b0..Even parity. 5479 * 0b1..Odd parity. 5480 */ 5481 #define UART_C1_PT(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_PT_SHIFT)) & UART_C1_PT_MASK) 5482 #define UART_C1_PE_MASK (0x2U) 5483 #define UART_C1_PE_SHIFT (1U) 5484 /*! PE - Parity Enable 5485 * 0b0..No hardware parity generation or checking. 5486 * 0b1..Parity enabled. 5487 */ 5488 #define UART_C1_PE(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_PE_SHIFT)) & UART_C1_PE_MASK) 5489 #define UART_C1_ILT_MASK (0x4U) 5490 #define UART_C1_ILT_SHIFT (2U) 5491 /*! ILT - Idle Line Type Select 5492 * 0b0..Idle character bit count starts after start bit. 5493 * 0b1..Idle character bit count starts after stop bit. 5494 */ 5495 #define UART_C1_ILT(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_ILT_SHIFT)) & UART_C1_ILT_MASK) 5496 #define UART_C1_WAKE_MASK (0x8U) 5497 #define UART_C1_WAKE_SHIFT (3U) 5498 /*! WAKE - Receiver Wakeup Method Select 5499 * 0b0..Idle-line wake-up. 5500 * 0b1..Address-mark wake-up. 5501 */ 5502 #define UART_C1_WAKE(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_WAKE_SHIFT)) & UART_C1_WAKE_MASK) 5503 #define UART_C1_M_MASK (0x10U) 5504 #define UART_C1_M_SHIFT (4U) 5505 /*! M - 9-Bit or 8-Bit Mode Select 5506 * 0b0..Normal - start + 8 data bits (lsb first) + stop. 5507 * 0b1..Receiver and transmitter use 9-bit data characters start + 8 data bits (lsb first) + 9th data bit + stop. 5508 */ 5509 #define UART_C1_M(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_M_SHIFT)) & UART_C1_M_MASK) 5510 #define UART_C1_RSRC_MASK (0x20U) 5511 #define UART_C1_RSRC_SHIFT (5U) 5512 /*! RSRC - Receiver Source Select 5513 * 0b0..Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the UART does not use the RxD pins. 5514 * 0b1..Single-wire UART mode where the TxD pin is connected to the transmitter output and receiver input. 5515 */ 5516 #define UART_C1_RSRC(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_RSRC_SHIFT)) & UART_C1_RSRC_MASK) 5517 #define UART_C1_UARTSWAI_MASK (0x40U) 5518 #define UART_C1_UARTSWAI_SHIFT (6U) 5519 /*! UARTSWAI - UART Stops in Wait Mode 5520 * 0b0..UART clocks continue to run in Wait mode so the UART can be the source of an interrupt that wakes up the CPU. 5521 * 0b1..UART clocks freeze while CPU is in Wait mode. 5522 */ 5523 #define UART_C1_UARTSWAI(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_UARTSWAI_SHIFT)) & UART_C1_UARTSWAI_MASK) 5524 #define UART_C1_LOOPS_MASK (0x80U) 5525 #define UART_C1_LOOPS_SHIFT (7U) 5526 /*! LOOPS - Loop Mode Select 5527 * 0b0..Normal operation - RxD and TxD use separate pins. 5528 * 0b1..Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input. (See RSRC bit.) RxD pin is not used by UART. 5529 */ 5530 #define UART_C1_LOOPS(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_LOOPS_SHIFT)) & UART_C1_LOOPS_MASK) 5531 /*! @} */ 5532 5533 /*! @name C2 - UART Control Register 2 */ 5534 /*! @{ */ 5535 #define UART_C2_SBK_MASK (0x1U) 5536 #define UART_C2_SBK_SHIFT (0U) 5537 /*! SBK - Send Break 5538 * 0b0..Normal transmitter operation. 5539 * 0b1..Queue break character(s) to be sent. 5540 */ 5541 #define UART_C2_SBK(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_SBK_SHIFT)) & UART_C2_SBK_MASK) 5542 #define UART_C2_RWU_MASK (0x2U) 5543 #define UART_C2_RWU_SHIFT (1U) 5544 /*! RWU - Receiver Wakeup Control 5545 * 0b0..Normal UART receiver operation. 5546 * 0b1..UART receiver in standby waiting for wake-up condition. 5547 */ 5548 #define UART_C2_RWU(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RWU_SHIFT)) & UART_C2_RWU_MASK) 5549 #define UART_C2_RE_MASK (0x4U) 5550 #define UART_C2_RE_SHIFT (2U) 5551 /*! RE - Receiver Enable 5552 * 0b0..Receiver off. 5553 * 0b1..Receiver on. 5554 */ 5555 #define UART_C2_RE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RE_SHIFT)) & UART_C2_RE_MASK) 5556 #define UART_C2_TE_MASK (0x8U) 5557 #define UART_C2_TE_SHIFT (3U) 5558 /*! TE - Transmitter Enable 5559 * 0b0..Transmitter off. 5560 * 0b1..Transmitter on. 5561 */ 5562 #define UART_C2_TE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TE_SHIFT)) & UART_C2_TE_MASK) 5563 #define UART_C2_ILIE_MASK (0x10U) 5564 #define UART_C2_ILIE_SHIFT (4U) 5565 /*! ILIE - Idle Line Interrupt Enable for IDLE 5566 * 0b0..Hardware interrupts from S1[IDLE] disabled; use polling. 5567 * 0b1..Hardware interrupt requested when S1[IDLE] flag is 1. 5568 */ 5569 #define UART_C2_ILIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_ILIE_SHIFT)) & UART_C2_ILIE_MASK) 5570 #define UART_C2_RIE_MASK (0x20U) 5571 #define UART_C2_RIE_SHIFT (5U) 5572 /*! RIE - Receiver Interrupt Enable for RDRF 5573 * 0b0..Hardware interrupts from S1[RDRF] disabled; use polling. 5574 * 0b1..Hardware interrupt requested when S1[RDRF] flag is 1. 5575 */ 5576 #define UART_C2_RIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RIE_SHIFT)) & UART_C2_RIE_MASK) 5577 #define UART_C2_TCIE_MASK (0x40U) 5578 #define UART_C2_TCIE_SHIFT (6U) 5579 /*! TCIE - Transmission Complete Interrupt Enable for TC 5580 * 0b0..Hardware interrupts from TC disabled; use polling. 5581 * 0b1..Hardware interrupt requested when TC flag is 1. 5582 */ 5583 #define UART_C2_TCIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TCIE_SHIFT)) & UART_C2_TCIE_MASK) 5584 #define UART_C2_TIE_MASK (0x80U) 5585 #define UART_C2_TIE_SHIFT (7U) 5586 /*! TIE - Transmit Interrupt Enable for TDRE 5587 * 0b0..Hardware interrupts from TDRE disabled; use polling. 5588 * 0b1..Hardware interrupt requested when TDRE flag is 1. 5589 */ 5590 #define UART_C2_TIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TIE_SHIFT)) & UART_C2_TIE_MASK) 5591 /*! @} */ 5592 5593 /*! @name S1 - UART Status Register 1 */ 5594 /*! @{ */ 5595 #define UART_S1_PF_MASK (0x1U) 5596 #define UART_S1_PF_SHIFT (0U) 5597 /*! PF - Parity Error Flag 5598 * 0b0..No parity error. 5599 * 0b1..Parity error. 5600 */ 5601 #define UART_S1_PF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_PF_SHIFT)) & UART_S1_PF_MASK) 5602 #define UART_S1_FE_MASK (0x2U) 5603 #define UART_S1_FE_SHIFT (1U) 5604 /*! FE - Framing Error Flag 5605 * 0b0..No framing error detected. This does not guarantee the framing is correct. 5606 * 0b1..Framing error. 5607 */ 5608 #define UART_S1_FE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_FE_SHIFT)) & UART_S1_FE_MASK) 5609 #define UART_S1_NF_MASK (0x4U) 5610 #define UART_S1_NF_SHIFT (2U) 5611 /*! NF - Noise Flag 5612 * 0b0..No noise detected. 5613 * 0b1..Noise detected in the received character in UART_D. 5614 */ 5615 #define UART_S1_NF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_NF_SHIFT)) & UART_S1_NF_MASK) 5616 #define UART_S1_OR_MASK (0x8U) 5617 #define UART_S1_OR_SHIFT (3U) 5618 /*! OR - Receiver Overrun Flag 5619 * 0b0..No overrun. 5620 * 0b1..Receive overrun (new UART data lost). 5621 */ 5622 #define UART_S1_OR(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_OR_SHIFT)) & UART_S1_OR_MASK) 5623 #define UART_S1_IDLE_MASK (0x10U) 5624 #define UART_S1_IDLE_SHIFT (4U) 5625 /*! IDLE - Idle Line Flag 5626 * 0b0..No idle line detected. 5627 * 0b1..Idle line was detected. 5628 */ 5629 #define UART_S1_IDLE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_IDLE_SHIFT)) & UART_S1_IDLE_MASK) 5630 #define UART_S1_RDRF_MASK (0x20U) 5631 #define UART_S1_RDRF_SHIFT (5U) 5632 /*! RDRF - Receive Data Register Full Flag 5633 * 0b0..Receive data register empty. 5634 * 0b1..Receive data register full. 5635 */ 5636 #define UART_S1_RDRF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_RDRF_SHIFT)) & UART_S1_RDRF_MASK) 5637 #define UART_S1_TC_MASK (0x40U) 5638 #define UART_S1_TC_SHIFT (6U) 5639 /*! TC - Transmission Complete Flag 5640 * 0b0..Transmitter active (sending data, a preamble, or a break). 5641 * 0b1..Transmitter idle (transmission activity complete). 5642 */ 5643 #define UART_S1_TC(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_TC_SHIFT)) & UART_S1_TC_MASK) 5644 #define UART_S1_TDRE_MASK (0x80U) 5645 #define UART_S1_TDRE_SHIFT (7U) 5646 /*! TDRE - Transmit Data Register Empty Flag 5647 * 0b0..Transmit data register (buffer) full. 5648 * 0b1..Transmit data register (buffer) empty. 5649 */ 5650 #define UART_S1_TDRE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_TDRE_SHIFT)) & UART_S1_TDRE_MASK) 5651 /*! @} */ 5652 5653 /*! @name S2 - UART Status Register 2 */ 5654 /*! @{ */ 5655 #define UART_S2_RAF_MASK (0x1U) 5656 #define UART_S2_RAF_SHIFT (0U) 5657 /*! RAF - Receiver Active Flag 5658 * 0b0..UART receiver idle waiting for a start bit. 5659 * 0b1..UART receiver active (RxD input not idle). 5660 */ 5661 #define UART_S2_RAF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RAF_SHIFT)) & UART_S2_RAF_MASK) 5662 #define UART_S2_LBKDE_MASK (0x2U) 5663 #define UART_S2_LBKDE_SHIFT (1U) 5664 /*! LBKDE - LIN Break Detection Enable 5665 * 0b0..Break detection is disabled. 5666 * 0b1..Break detection is enabled (Break character is detected at length 11 bit times (if C1[M] = 0, BDH[SBNS] = 0) or 12 (if C1[M] = 1, BDH[SBNS] = 0 or C1[M] = 0, BDH[SBNS] = 1) or 13 (if C1[M] = 1, BDH[SBNS] = 1)). 5667 */ 5668 #define UART_S2_LBKDE(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_LBKDE_SHIFT)) & UART_S2_LBKDE_MASK) 5669 #define UART_S2_BRK13_MASK (0x4U) 5670 #define UART_S2_BRK13_SHIFT (2U) 5671 /*! BRK13 - Break Character Generation Length 5672 * 0b0..Break character is transmitted with length of 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1). 5673 * 0b1..Break character is transmitted with length of 13 bit times (if M = 0, SBNS = 0) or 14 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 15 (if M = 1, SBNS = 1). 5674 */ 5675 #define UART_S2_BRK13(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_BRK13_SHIFT)) & UART_S2_BRK13_MASK) 5676 #define UART_S2_RWUID_MASK (0x8U) 5677 #define UART_S2_RWUID_SHIFT (3U) 5678 /*! RWUID - Receive Wake Up Idle Detect 5679 * 0b0..During receive standby state (RWU = 1), S1[IDLE] does not get set upon detection of an idle character. 5680 * 0b1..During receive standby state (RWU = 1), S1[IDLE] gets set upon detection of an idle character. 5681 */ 5682 #define UART_S2_RWUID(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RWUID_SHIFT)) & UART_S2_RWUID_MASK) 5683 #define UART_S2_RXINV_MASK (0x10U) 5684 #define UART_S2_RXINV_SHIFT (4U) 5685 /*! RXINV - Receive Data Inversion 5686 * 0b0..Receive data not inverted. 5687 * 0b1..Receive data inverted. 5688 */ 5689 #define UART_S2_RXINV(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RXINV_SHIFT)) & UART_S2_RXINV_MASK) 5690 #define UART_S2_RXEDGIF_MASK (0x40U) 5691 #define UART_S2_RXEDGIF_SHIFT (6U) 5692 /*! RXEDGIF - RxD Pin Active Edge Interrupt Flag 5693 * 0b0..No active edge on the receive pin has occurred. 5694 * 0b1..An active edge on the receive pin has occurred. 5695 */ 5696 #define UART_S2_RXEDGIF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RXEDGIF_SHIFT)) & UART_S2_RXEDGIF_MASK) 5697 #define UART_S2_LBKDIF_MASK (0x80U) 5698 #define UART_S2_LBKDIF_SHIFT (7U) 5699 /*! LBKDIF - LIN Break Detect Interrupt Flag 5700 * 0b0..No LIN break character has been detected. 5701 * 0b1..LIN break character has been detected. 5702 */ 5703 #define UART_S2_LBKDIF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_LBKDIF_SHIFT)) & UART_S2_LBKDIF_MASK) 5704 /*! @} */ 5705 5706 /*! @name C3 - UART Control Register 3 */ 5707 /*! @{ */ 5708 #define UART_C3_PEIE_MASK (0x1U) 5709 #define UART_C3_PEIE_SHIFT (0U) 5710 /*! PEIE - Parity Error Interrupt Enable 5711 * 0b0..PF interrupts disabled; use polling). 5712 * 0b1..Hardware interrupt requested when PF is set. 5713 */ 5714 #define UART_C3_PEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_PEIE_SHIFT)) & UART_C3_PEIE_MASK) 5715 #define UART_C3_FEIE_MASK (0x2U) 5716 #define UART_C3_FEIE_SHIFT (1U) 5717 /*! FEIE - Framing Error Interrupt Enable 5718 * 0b0..FE interrupts disabled; use polling). 5719 * 0b1..Hardware interrupt requested when FE is set. 5720 */ 5721 #define UART_C3_FEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_FEIE_SHIFT)) & UART_C3_FEIE_MASK) 5722 #define UART_C3_NEIE_MASK (0x4U) 5723 #define UART_C3_NEIE_SHIFT (2U) 5724 /*! NEIE - Noise Error Interrupt Enable 5725 * 0b0..NF interrupts disabled; use polling). 5726 * 0b1..Hardware interrupt requested when NF is set. 5727 */ 5728 #define UART_C3_NEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_NEIE_SHIFT)) & UART_C3_NEIE_MASK) 5729 #define UART_C3_ORIE_MASK (0x8U) 5730 #define UART_C3_ORIE_SHIFT (3U) 5731 /*! ORIE - Overrun Interrupt Enable 5732 * 0b0..OR interrupts disabled; use polling. 5733 * 0b1..Hardware interrupt requested when OR is set. 5734 */ 5735 #define UART_C3_ORIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_ORIE_SHIFT)) & UART_C3_ORIE_MASK) 5736 #define UART_C3_TXINV_MASK (0x10U) 5737 #define UART_C3_TXINV_SHIFT (4U) 5738 /*! TXINV - Transmit Data Inversion 5739 * 0b0..Transmit data not inverted. 5740 * 0b1..Transmit data inverted. 5741 */ 5742 #define UART_C3_TXINV(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_TXINV_SHIFT)) & UART_C3_TXINV_MASK) 5743 #define UART_C3_TXDIR_MASK (0x20U) 5744 #define UART_C3_TXDIR_SHIFT (5U) 5745 /*! TXDIR - TxD Pin Direction in Single-Wire Mode 5746 * 0b0..TxD pin is an input in single-wire mode. 5747 * 0b1..TxD pin is an output in single-wire mode. 5748 */ 5749 #define UART_C3_TXDIR(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_TXDIR_SHIFT)) & UART_C3_TXDIR_MASK) 5750 #define UART_C3_T8_MASK (0x40U) 5751 #define UART_C3_T8_SHIFT (6U) 5752 #define UART_C3_T8(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_T8_SHIFT)) & UART_C3_T8_MASK) 5753 #define UART_C3_R8_MASK (0x80U) 5754 #define UART_C3_R8_SHIFT (7U) 5755 #define UART_C3_R8(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_R8_SHIFT)) & UART_C3_R8_MASK) 5756 /*! @} */ 5757 5758 /*! @name D - UART Data Register */ 5759 /*! @{ */ 5760 #define UART_D_R0T0_MASK (0x1U) 5761 #define UART_D_R0T0_SHIFT (0U) 5762 #define UART_D_R0T0(x) (((uint8_t)(((uint8_t)(x)) << UART_D_R0T0_SHIFT)) & UART_D_R0T0_MASK) 5763 #define UART_D_R1T1_MASK (0x2U) 5764 #define UART_D_R1T1_SHIFT (1U) 5765 #define UART_D_R1T1(x) (((uint8_t)(((uint8_t)(x)) << UART_D_R1T1_SHIFT)) & UART_D_R1T1_MASK) 5766 #define UART_D_R2T2_MASK (0x4U) 5767 #define UART_D_R2T2_SHIFT (2U) 5768 #define UART_D_R2T2(x) (((uint8_t)(((uint8_t)(x)) << UART_D_R2T2_SHIFT)) & UART_D_R2T2_MASK) 5769 #define UART_D_R3T3_MASK (0x8U) 5770 #define UART_D_R3T3_SHIFT (3U) 5771 #define UART_D_R3T3(x) (((uint8_t)(((uint8_t)(x)) << UART_D_R3T3_SHIFT)) & UART_D_R3T3_MASK) 5772 #define UART_D_R4T4_MASK (0x10U) 5773 #define UART_D_R4T4_SHIFT (4U) 5774 #define UART_D_R4T4(x) (((uint8_t)(((uint8_t)(x)) << UART_D_R4T4_SHIFT)) & UART_D_R4T4_MASK) 5775 #define UART_D_R5T5_MASK (0x20U) 5776 #define UART_D_R5T5_SHIFT (5U) 5777 #define UART_D_R5T5(x) (((uint8_t)(((uint8_t)(x)) << UART_D_R5T5_SHIFT)) & UART_D_R5T5_MASK) 5778 #define UART_D_R6T6_MASK (0x40U) 5779 #define UART_D_R6T6_SHIFT (6U) 5780 #define UART_D_R6T6(x) (((uint8_t)(((uint8_t)(x)) << UART_D_R6T6_SHIFT)) & UART_D_R6T6_MASK) 5781 #define UART_D_R7T7_MASK (0x80U) 5782 #define UART_D_R7T7_SHIFT (7U) 5783 #define UART_D_R7T7(x) (((uint8_t)(((uint8_t)(x)) << UART_D_R7T7_SHIFT)) & UART_D_R7T7_MASK) 5784 /*! @} */ 5785 5786 5787 /*! 5788 * @} 5789 */ /* end of group UART_Register_Masks */ 5790 5791 5792 /* UART - Peripheral instance base addresses */ 5793 /** Peripheral UART0 base address */ 5794 #define UART0_BASE (0x4006A000u) 5795 /** Peripheral UART0 base pointer */ 5796 #define UART0 ((UART_Type *)UART0_BASE) 5797 /** Array initializer of UART peripheral base addresses */ 5798 #define UART_BASE_ADDRS { UART0_BASE } 5799 /** Array initializer of UART peripheral base pointers */ 5800 #define UART_BASE_PTRS { UART0 } 5801 /** Interrupt vectors for the UART peripheral type */ 5802 #define UART_RX_TX_IRQS { UART0_IRQn } 5803 #define UART_ERR_IRQS { UART0_IRQn } 5804 5805 /*! 5806 * @} 5807 */ /* end of group UART_Peripheral_Access_Layer */ 5808 5809 5810 /* ---------------------------------------------------------------------------- 5811 -- WDOG Peripheral Access Layer 5812 ---------------------------------------------------------------------------- */ 5813 5814 /*! 5815 * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer 5816 * @{ 5817 */ 5818 5819 /** WDOG - Register Layout Typedef */ 5820 typedef struct { 5821 __IO uint8_t CS1; /**< Watchdog Control and Status Register 1, offset: 0x0 */ 5822 __IO uint8_t CS2; /**< Watchdog Control and Status Register 2, offset: 0x1 */ 5823 union { /* offset: 0x2 */ 5824 __IO uint16_t CNT; /**< WDOG_CNT register., offset: 0x2 */ 5825 struct { /* offset: 0x2 */ 5826 __IO uint8_t CNTH; /**< Watchdog Counter Register: High, offset: 0x2 */ 5827 __IO uint8_t CNTL; /**< Watchdog Counter Register: Low, offset: 0x3 */ 5828 } CNT8B; 5829 }; 5830 union { /* offset: 0x4 */ 5831 __IO uint16_t TOVAL; /**< WDOG_TOVAL register., offset: 0x4 */ 5832 struct { /* offset: 0x4 */ 5833 __IO uint8_t TOVALH; /**< Watchdog Timeout Value Register: High, offset: 0x4 */ 5834 __IO uint8_t TOVALL; /**< Watchdog Timeout Value Register: Low, offset: 0x5 */ 5835 } TOVAL8B; 5836 }; 5837 union { /* offset: 0x6 */ 5838 __IO uint16_t WIN; /**< WDOG_WIN register., offset: 0x6 */ 5839 struct { /* offset: 0x6 */ 5840 __IO uint8_t WINH; /**< Watchdog Window Register: High, offset: 0x6 */ 5841 __IO uint8_t WINL; /**< Watchdog Window Register: Low, offset: 0x7 */ 5842 } WIN8B; 5843 }; 5844 } WDOG_Type; 5845 5846 /* ---------------------------------------------------------------------------- 5847 -- WDOG Register Masks 5848 ---------------------------------------------------------------------------- */ 5849 5850 /*! 5851 * @addtogroup WDOG_Register_Masks WDOG Register Masks 5852 * @{ 5853 */ 5854 5855 /*! @name CS1 - Watchdog Control and Status Register 1 */ 5856 /*! @{ */ 5857 #define WDOG_CS1_STOP_MASK (0x1U) 5858 #define WDOG_CS1_STOP_SHIFT (0U) 5859 /*! STOP - Stop Enable 5860 * 0b0..Watchdog disabled in chip stop mode. 5861 * 0b1..Watchdog enabled in chip stop mode. 5862 */ 5863 #define WDOG_CS1_STOP(x) (((uint8_t)(((uint8_t)(x)) << WDOG_CS1_STOP_SHIFT)) & WDOG_CS1_STOP_MASK) 5864 #define WDOG_CS1_WAIT_MASK (0x2U) 5865 #define WDOG_CS1_WAIT_SHIFT (1U) 5866 /*! WAIT - Wait Enable 5867 * 0b0..Watchdog disabled in chip wait mode. 5868 * 0b1..Watchdog enabled in chip wait mode. 5869 */ 5870 #define WDOG_CS1_WAIT(x) (((uint8_t)(((uint8_t)(x)) << WDOG_CS1_WAIT_SHIFT)) & WDOG_CS1_WAIT_MASK) 5871 #define WDOG_CS1_DBG_MASK (0x4U) 5872 #define WDOG_CS1_DBG_SHIFT (2U) 5873 /*! DBG - Debug Enable 5874 * 0b0..Watchdog disabled in chip debug mode. 5875 * 0b1..Watchdog enabled in chip debug mode. 5876 */ 5877 #define WDOG_CS1_DBG(x) (((uint8_t)(((uint8_t)(x)) << WDOG_CS1_DBG_SHIFT)) & WDOG_CS1_DBG_MASK) 5878 #define WDOG_CS1_TST_MASK (0x18U) 5879 #define WDOG_CS1_TST_SHIFT (3U) 5880 /*! TST - Watchdog Test 5881 * 0b00..Watchdog test mode disabled. 5882 * 0b01..Watchdog user mode enabled. (Watchdog test mode disabled.) After testing the watchdog, software should use this setting to indicate that the watchdog is functioning normally in user mode. 5883 * 0b10..Watchdog test mode enabled, only the low byte is used. WDOG_CNTL is compared with WDOG_TOVALL. 5884 * 0b11..Watchdog test mode enabled, only the high byte is used. WDOG_CNTH is compared with WDOG_TOVALH. 5885 */ 5886 #define WDOG_CS1_TST(x) (((uint8_t)(((uint8_t)(x)) << WDOG_CS1_TST_SHIFT)) & WDOG_CS1_TST_MASK) 5887 #define WDOG_CS1_UPDATE_MASK (0x20U) 5888 #define WDOG_CS1_UPDATE_SHIFT (5U) 5889 /*! UPDATE - Allow updates 5890 * 0b0..Updates not allowed. After the initial configuration, the watchdog cannot be later modified without forcing a reset. 5891 * 0b1..Updates allowed. Software can modify the watchdog configuration registers within 128 bus clocks after performing the unlock write sequence. 5892 */ 5893 #define WDOG_CS1_UPDATE(x) (((uint8_t)(((uint8_t)(x)) << WDOG_CS1_UPDATE_SHIFT)) & WDOG_CS1_UPDATE_MASK) 5894 #define WDOG_CS1_INT_MASK (0x40U) 5895 #define WDOG_CS1_INT_SHIFT (6U) 5896 /*! INT - Watchdog Interrupt 5897 * 0b0..Watchdog interrupts are disabled. Watchdog resets are not delayed. 5898 * 0b1..Watchdog interrupts are enabled. Watchdog resets are delayed by 128 bus clocks. 5899 */ 5900 #define WDOG_CS1_INT(x) (((uint8_t)(((uint8_t)(x)) << WDOG_CS1_INT_SHIFT)) & WDOG_CS1_INT_MASK) 5901 #define WDOG_CS1_EN_MASK (0x80U) 5902 #define WDOG_CS1_EN_SHIFT (7U) 5903 /*! EN - Watchdog Enable 5904 * 0b0..Watchdog disabled. 5905 * 0b1..Watchdog enabled. 5906 */ 5907 #define WDOG_CS1_EN(x) (((uint8_t)(((uint8_t)(x)) << WDOG_CS1_EN_SHIFT)) & WDOG_CS1_EN_MASK) 5908 /*! @} */ 5909 5910 /*! @name CS2 - Watchdog Control and Status Register 2 */ 5911 /*! @{ */ 5912 #define WDOG_CS2_CLK_MASK (0x3U) 5913 #define WDOG_CS2_CLK_SHIFT (0U) 5914 /*! CLK - Watchdog Clock 5915 * 0b00..Bus clock. 5916 * 0b01..1 kHz internal low-power oscillator (LPOCLK). 5917 * 0b10..32 kHz internal oscillator (ICSIRCLK). 5918 * 0b11..External clock source. 5919 */ 5920 #define WDOG_CS2_CLK(x) (((uint8_t)(((uint8_t)(x)) << WDOG_CS2_CLK_SHIFT)) & WDOG_CS2_CLK_MASK) 5921 #define WDOG_CS2_PRES_MASK (0x10U) 5922 #define WDOG_CS2_PRES_SHIFT (4U) 5923 /*! PRES - Watchdog Prescalar 5924 * 0b0..256 prescalar disabled. 5925 * 0b1..256 prescalar enabled. 5926 */ 5927 #define WDOG_CS2_PRES(x) (((uint8_t)(((uint8_t)(x)) << WDOG_CS2_PRES_SHIFT)) & WDOG_CS2_PRES_MASK) 5928 #define WDOG_CS2_FLG_MASK (0x40U) 5929 #define WDOG_CS2_FLG_SHIFT (6U) 5930 /*! FLG - Watchdog Interrupt Flag 5931 * 0b0..No interrupt occurred. 5932 * 0b1..An interrupt occurred. 5933 */ 5934 #define WDOG_CS2_FLG(x) (((uint8_t)(((uint8_t)(x)) << WDOG_CS2_FLG_SHIFT)) & WDOG_CS2_FLG_MASK) 5935 #define WDOG_CS2_WIN_MASK (0x80U) 5936 #define WDOG_CS2_WIN_SHIFT (7U) 5937 /*! WIN - Watchdog Window 5938 * 0b0..Window mode disabled. 5939 * 0b1..Window mode enabled. 5940 */ 5941 #define WDOG_CS2_WIN(x) (((uint8_t)(((uint8_t)(x)) << WDOG_CS2_WIN_SHIFT)) & WDOG_CS2_WIN_MASK) 5942 /*! @} */ 5943 5944 /*! @name CNT - WDOG_CNT register. */ 5945 /*! @{ */ 5946 #define WDOG_CNT_CNTHIGH_MASK (0xFFU) 5947 #define WDOG_CNT_CNTHIGH_SHIFT (0U) 5948 #define WDOG_CNT_CNTHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_CNT_CNTHIGH_SHIFT)) & WDOG_CNT_CNTHIGH_MASK) 5949 #define WDOG_CNT_CNTLOW_MASK (0xFF00U) 5950 #define WDOG_CNT_CNTLOW_SHIFT (8U) 5951 #define WDOG_CNT_CNTLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_CNT_CNTLOW_SHIFT)) & WDOG_CNT_CNTLOW_MASK) 5952 /*! @} */ 5953 5954 /*! @name CNTH - Watchdog Counter Register: High */ 5955 /*! @{ */ 5956 #define WDOG_CNTH_CNTHIGH_MASK (0xFFU) 5957 #define WDOG_CNTH_CNTHIGH_SHIFT (0U) 5958 #define WDOG_CNTH_CNTHIGH(x) (((uint8_t)(((uint8_t)(x)) << WDOG_CNTH_CNTHIGH_SHIFT)) & WDOG_CNTH_CNTHIGH_MASK) 5959 /*! @} */ 5960 5961 /*! @name CNTL - Watchdog Counter Register: Low */ 5962 /*! @{ */ 5963 #define WDOG_CNTL_CNTLOW_MASK (0xFFU) 5964 #define WDOG_CNTL_CNTLOW_SHIFT (0U) 5965 #define WDOG_CNTL_CNTLOW(x) (((uint8_t)(((uint8_t)(x)) << WDOG_CNTL_CNTLOW_SHIFT)) & WDOG_CNTL_CNTLOW_MASK) 5966 /*! @} */ 5967 5968 /*! @name TOVAL - WDOG_TOVAL register. */ 5969 /*! @{ */ 5970 #define WDOG_TOVAL_TOVALHIGH_MASK (0xFFU) 5971 #define WDOG_TOVAL_TOVALHIGH_SHIFT (0U) 5972 #define WDOG_TOVAL_TOVALHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TOVAL_TOVALHIGH_SHIFT)) & WDOG_TOVAL_TOVALHIGH_MASK) 5973 #define WDOG_TOVAL_TOVALLOW_MASK (0xFF00U) 5974 #define WDOG_TOVAL_TOVALLOW_SHIFT (8U) 5975 #define WDOG_TOVAL_TOVALLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TOVAL_TOVALLOW_SHIFT)) & WDOG_TOVAL_TOVALLOW_MASK) 5976 /*! @} */ 5977 5978 /*! @name TOVALH - Watchdog Timeout Value Register: High */ 5979 /*! @{ */ 5980 #define WDOG_TOVALH_TOVALHIGH_MASK (0xFFU) 5981 #define WDOG_TOVALH_TOVALHIGH_SHIFT (0U) 5982 #define WDOG_TOVALH_TOVALHIGH(x) (((uint8_t)(((uint8_t)(x)) << WDOG_TOVALH_TOVALHIGH_SHIFT)) & WDOG_TOVALH_TOVALHIGH_MASK) 5983 /*! @} */ 5984 5985 /*! @name TOVALL - Watchdog Timeout Value Register: Low */ 5986 /*! @{ */ 5987 #define WDOG_TOVALL_TOVALLOW_MASK (0xFFU) 5988 #define WDOG_TOVALL_TOVALLOW_SHIFT (0U) 5989 #define WDOG_TOVALL_TOVALLOW(x) (((uint8_t)(((uint8_t)(x)) << WDOG_TOVALL_TOVALLOW_SHIFT)) & WDOG_TOVALL_TOVALLOW_MASK) 5990 /*! @} */ 5991 5992 /*! @name WIN - WDOG_WIN register. */ 5993 /*! @{ */ 5994 #define WDOG_WIN_WINHIGH_MASK (0xFFU) 5995 #define WDOG_WIN_WINHIGH_SHIFT (0U) 5996 #define WDOG_WIN_WINHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WIN_WINHIGH_SHIFT)) & WDOG_WIN_WINHIGH_MASK) 5997 #define WDOG_WIN_WINLOW_MASK (0xFF00U) 5998 #define WDOG_WIN_WINLOW_SHIFT (8U) 5999 #define WDOG_WIN_WINLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WIN_WINLOW_SHIFT)) & WDOG_WIN_WINLOW_MASK) 6000 /*! @} */ 6001 6002 /*! @name WINH - Watchdog Window Register: High */ 6003 /*! @{ */ 6004 #define WDOG_WINH_WINHIGH_MASK (0xFFU) 6005 #define WDOG_WINH_WINHIGH_SHIFT (0U) 6006 #define WDOG_WINH_WINHIGH(x) (((uint8_t)(((uint8_t)(x)) << WDOG_WINH_WINHIGH_SHIFT)) & WDOG_WINH_WINHIGH_MASK) 6007 /*! @} */ 6008 6009 /*! @name WINL - Watchdog Window Register: Low */ 6010 /*! @{ */ 6011 #define WDOG_WINL_WINLOW_MASK (0xFFU) 6012 #define WDOG_WINL_WINLOW_SHIFT (0U) 6013 #define WDOG_WINL_WINLOW(x) (((uint8_t)(((uint8_t)(x)) << WDOG_WINL_WINLOW_SHIFT)) & WDOG_WINL_WINLOW_MASK) 6014 /*! @} */ 6015 6016 6017 /*! 6018 * @} 6019 */ /* end of group WDOG_Register_Masks */ 6020 6021 6022 /* WDOG - Peripheral instance base addresses */ 6023 /** Peripheral WDOG base address */ 6024 #define WDOG_BASE (0x40052000u) 6025 /** Peripheral WDOG base pointer */ 6026 #define WDOG ((WDOG_Type *)WDOG_BASE) 6027 /** Array initializer of WDOG peripheral base addresses */ 6028 #define WDOG_BASE_ADDRS { WDOG_BASE } 6029 /** Array initializer of WDOG peripheral base pointers */ 6030 #define WDOG_BASE_PTRS { WDOG } 6031 /** Interrupt vectors for the WDOG peripheral type */ 6032 #define WDOG_IRQS { WDOG_IRQn } 6033 #define WDOG_UPDATE_KEY1 (0x20C5U) 6034 #define WDOG_UPDATE_KEY_H1 (0x20U) 6035 #define WDOG_UPDATE_KEY_L1 (0xC5U) 6036 #define WDOG_UPDATE_KEY2 (0x28D9U) 6037 #define WDOG_UPDATE_KEY_H2 (0x28U) 6038 #define WDOG_UPDATE_KEY_L2 (0xD9U) 6039 #define WDOG_REFRESH_KEY1 (0x02A6U) 6040 #define WDOG_REFRESH_KEY_H1 (0x02U) 6041 #define WDOG_REFRESH_KEY_L1 (0xA6U) 6042 #define WDOG_REFRESH_KEY2 (0x80B4U) 6043 #define WDOG_REFRESH_KEY_H2 (0x80U) 6044 #define WDOG_REFRESH_KEY_L2 (0xB4U) 6045 6046 6047 /*! 6048 * @} 6049 */ /* end of group WDOG_Peripheral_Access_Layer */ 6050 6051 6052 /* 6053 ** End of section using anonymous unions 6054 */ 6055 6056 #if defined(__ARMCC_VERSION) 6057 #if (__ARMCC_VERSION >= 6010050) 6058 #pragma clang diagnostic pop 6059 #else 6060 #pragma pop 6061 #endif 6062 #elif defined(__CWCC__) 6063 #pragma pop 6064 #elif defined(__GNUC__) 6065 /* leave anonymous unions enabled */ 6066 #elif defined(__IAR_SYSTEMS_ICC__) 6067 #pragma language=default 6068 #else 6069 #error Not supported compiler type 6070 #endif 6071 6072 /*! 6073 * @} 6074 */ /* end of group Peripheral_access_layer */ 6075 6076 6077 /* ---------------------------------------------------------------------------- 6078 -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). 6079 ---------------------------------------------------------------------------- */ 6080 6081 /*! 6082 * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). 6083 * @{ 6084 */ 6085 6086 #if defined(__ARMCC_VERSION) 6087 #if (__ARMCC_VERSION >= 6010050) 6088 #pragma clang system_header 6089 #endif 6090 #elif defined(__IAR_SYSTEMS_ICC__) 6091 #pragma system_include 6092 #endif 6093 6094 /** 6095 * @brief Mask and left-shift a bit field value for use in a register bit range. 6096 * @param field Name of the register bit field. 6097 * @param value Value of the bit field. 6098 * @return Masked and shifted value. 6099 */ 6100 #define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) 6101 /** 6102 * @brief Mask and right-shift a register value to extract a bit field value. 6103 * @param field Name of the register bit field. 6104 * @param value Value of the register. 6105 * @return Masked and shifted bit field value. 6106 */ 6107 #define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) 6108 6109 /*! 6110 * @} 6111 */ /* end of group Bit_Field_Generic_Macros */ 6112 6113 6114 /* ---------------------------------------------------------------------------- 6115 -- SDK Compatibility 6116 ---------------------------------------------------------------------------- */ 6117 6118 /*! 6119 * @addtogroup SDK_Compatibility_Symbols SDK Compatibility 6120 * @{ 6121 */ 6122 6123 /* No SDK compatibility issues. */ 6124 6125 /*! 6126 * @} 6127 */ /* end of group SDK_Compatibility_Symbols */ 6128 6129 6130 #endif /* _MKE04Z4_H_ */ 6131 6132
