1 /*
2  * Copyright (c) 2016, Freescale Semiconductor, Inc.
3  * Copyright 2016-2023 NXP
4  * All rights reserved.
5  *
6  * SPDX-License-Identifier: BSD-3-Clause
7  */
8 
9 #ifndef FSL_MAILBOX_H_
10 #define FSL_MAILBOX_H_
11 
12 #include "fsl_common.h"
13 
14 /*!
15  * @addtogroup mailbox
16  * @{
17  */
18 
19 /*! @file */
20 
21 /******************************************************************************
22  * Definitions
23  *****************************************************************************/
24 
25 /* Component ID definition, used by tools. */
26 #ifndef FSL_COMPONENT_ID
27 #define FSL_COMPONENT_ID "platform.drivers.mailbox"
28 #endif
29 
30 /*! @name Driver version */
31 /*! @{ */
32 /*! @brief MAILBOX driver version 2.3.0. */
33 #define FSL_MAILBOX_DRIVER_VERSION (MAKE_VERSION(2, 3, 2))
34 /*! @} */
35 
36 /*!
37  * @brief CPU ID.
38  */
39 #if (defined(LPC55S69_cm33_core0_SERIES) || defined(LPC55S69_cm33_core1_SERIES) || \
40      defined(LPC55S66_cm33_core0_SERIES) || defined(LPC55S66_cm33_core1_SERIES))
41 typedef enum _mailbox_cpu_id
42 {
43     kMAILBOX_CM33_Core1 = 0,
44     kMAILBOX_CM33_Core0
45 } mailbox_cpu_id_t;
46 #elif ((defined(LPC54114_cm4_SERIES) || defined(LPC54114_cm0plus_SERIES)))
47 typedef enum _mailbox_cpu_id
48 {
49     kMAILBOX_CM0Plus = 0,
50     kMAILBOX_CM4
51 } mailbox_cpu_id_t;
52 #elif (defined(MCXN947_cm33_core0_SERIES) || defined(MCXN947_cm33_core1_SERIES) || \
53        defined(MCXN946_cm33_core0_SERIES) || defined(MCXN946_cm33_core1_SERIES) || \
54        defined(MCXN547_cm33_core0_SERIES) || defined(MCXN547_cm33_core1_SERIES) || \
55        defined(MCXN546_cm33_core0_SERIES) || defined(MCXN546_cm33_core1_SERIES))
56 typedef enum _mailbox_cpu_id
57 {
58     kMAILBOX_CM33_Core0 = 0,
59     kMAILBOX_CM33_Core1
60 } mailbox_cpu_id_t;
61 #endif
62 
63 #if (defined(CPU_NXH2004J640UK48))
64 typedef enum _mailbox_id
65 {
66     kMAILBOX_CM0Plus_Core0 = 0,
67     kMAILBOX_CM0Plus_Core1,
68     kMAILBOX_CM0Plus_Sw_Irq0,
69     kMAILBOX_CM0Plus_Sw_Irq1,
70     kMAILBOX_CM0Plus_Sw_Irq2,
71     kMAILBOX_CM0Plus_Sw_Irq3
72 } mailbox_id_t;
73 #endif
74 /*******************************************************************************
75  * API
76  ******************************************************************************/
77 
78 #ifdef __cplusplus
79 extern "C" {
80 #endif
81 
82 /*!
83  * @name MAILBOX initialization
84  * @{
85  */
86 
87 /*!
88  * @brief Initializes the MAILBOX module.
89  *
90  * This function enables the MAILBOX clock only.
91  *
92  * @param base MAILBOX peripheral base address.
93  */
MAILBOX_Init(MAILBOX_Type * base)94 static inline void MAILBOX_Init(MAILBOX_Type *base)
95 {
96 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
97     CLOCK_EnableClock(kCLOCK_Mailbox);
98 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
99 #if !(defined(FSL_FEATURE_MAILBOX_HAS_NO_RESET) && FSL_FEATURE_MAILBOX_HAS_NO_RESET)
100     /* Reset the MAILBOX module */
101     RESET_PeripheralReset(kMAILBOX_RST_SHIFT_RSTn);
102 #endif
103 }
104 
105 /*!
106  * @brief De-initializes the MAILBOX module.
107  *
108  * This function disables the MAILBOX clock only.
109  *
110  * @param base MAILBOX peripheral base address.
111  */
MAILBOX_Deinit(MAILBOX_Type * base)112 static inline void MAILBOX_Deinit(MAILBOX_Type *base)
113 {
114 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
115     CLOCK_DisableClock(kCLOCK_Mailbox);
116 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
117 }
118 
119 /*! @} */
120 
121 #if ((defined(LPC55S69_cm33_core0_SERIES) || defined(LPC55S69_cm33_core1_SERIES)) || \
122      defined(LPC55S66_cm33_core0_SERIES) || defined(LPC55S66_cm33_core1_SERIES) || \
123      defined(MCXN947_cm33_core0_SERIES) || defined(MCXN947_cm33_core1_SERIES) || \
124      defined(MCXN946_cm33_core0_SERIES) || defined(MCXN946_cm33_core1_SERIES) || \
125      defined(MCXN547_cm33_core0_SERIES) || defined(MCXN547_cm33_core1_SERIES) || \
126      defined(MCXN546_cm33_core0_SERIES) || defined(MCXN546_cm33_core1_SERIES) || \
127      defined(LPC54114_cm4_SERIES) || defined(LPC54114_cm0plus_SERIES))
128 /*!
129  * @brief Set data value in the mailbox based on the CPU ID.
130  *
131  * @param base MAILBOX peripheral base address.
132  * @param cpu_id CPU id, kMAILBOX_CM0Plus or kMAILBOX_CM4 for LPC5410x and LPC5411x devices,
133  *               kMAILBOX_CM33_Core0 or kMAILBOX_CM33_Core1 for LPC55S69 devices.
134  * @param mboxData Data to send in the mailbox.
135  *
136  * @note Sets a data value to send via the MAILBOX to the other core.
137  */
MAILBOX_SetValue(MAILBOX_Type * base,mailbox_cpu_id_t cpu_id,uint32_t mboxData)138 static inline void MAILBOX_SetValue(MAILBOX_Type *base, mailbox_cpu_id_t cpu_id, uint32_t mboxData)
139 {
140 #if ((defined(LPC55S69_cm33_core0_SERIES) || defined(LPC55S69_cm33_core1_SERIES)) || \
141      defined(LPC55S66_cm33_core0_SERIES) || defined(LPC55S66_cm33_core1_SERIES) || \
142      defined(MCXN947_cm33_core0_SERIES) || defined(MCXN947_cm33_core1_SERIES) || \
143      defined(MCXN946_cm33_core0_SERIES) || defined(MCXN946_cm33_core1_SERIES) || \
144      defined(MCXN547_cm33_core0_SERIES) || defined(MCXN547_cm33_core1_SERIES) || \
145      defined(MCXN546_cm33_core0_SERIES) || defined(MCXN546_cm33_core1_SERIES))
146     assert((cpu_id == kMAILBOX_CM33_Core0) || (cpu_id == kMAILBOX_CM33_Core1));
147 #elif ((defined(LPC54114_cm4_SERIES) || defined(LPC54114_cm0plus_SERIES)))
148     assert((cpu_id == kMAILBOX_CM0Plus) || (cpu_id == kMAILBOX_CM4));
149 #endif
150     base->MBOXIRQ[cpu_id].IRQ = mboxData;
151 }
152 
153 /*!
154  * @brief Get data in the mailbox based on the CPU ID.
155  *
156  * @param base MAILBOX peripheral base address.
157  * @param cpu_id CPU id, kMAILBOX_CM0Plus or kMAILBOX_CM4 for LPC5410x and LPC5411x devices,
158  *               kMAILBOX_CM33_Core0 or kMAILBOX_CM33_Core1 for LPC55S69 devices.
159  *
160  * @return Current mailbox data.
161  */
MAILBOX_GetValue(MAILBOX_Type * base,mailbox_cpu_id_t cpu_id)162 static inline uint32_t MAILBOX_GetValue(MAILBOX_Type *base, mailbox_cpu_id_t cpu_id)
163 {
164 #if ((defined(LPC55S69_cm33_core0_SERIES) || defined(LPC55S69_cm33_core1_SERIES)) || \
165      defined(LPC55S66_cm33_core0_SERIES) || defined(LPC55S66_cm33_core1_SERIES) || \
166      defined(MCXN947_cm33_core0_SERIES) || defined(MCXN947_cm33_core1_SERIES) || \
167      defined(MCXN946_cm33_core0_SERIES) || defined(MCXN946_cm33_core1_SERIES) || \
168      defined(MCXN547_cm33_core0_SERIES) || defined(MCXN547_cm33_core1_SERIES) || \
169      defined(MCXN546_cm33_core0_SERIES) || defined(MCXN546_cm33_core1_SERIES))
170     assert((cpu_id == kMAILBOX_CM33_Core0) || (cpu_id == kMAILBOX_CM33_Core1));
171 #elif ((defined(LPC54114_cm4_SERIES) || defined(LPC54114_cm0plus_SERIES)))
172     assert((cpu_id == kMAILBOX_CM0Plus) || (cpu_id == kMAILBOX_CM4));
173 #endif
174     return base->MBOXIRQ[cpu_id].IRQ;
175 }
176 
177 /*!
178  * @brief Set data bits in the mailbox based on the CPU ID.
179  *
180  * @param base MAILBOX peripheral base address.
181  * @param cpu_id CPU id, kMAILBOX_CM0Plus or kMAILBOX_CM4 for LPC5410x and LPC5411x devices,
182  *               kMAILBOX_CM33_Core0 or kMAILBOX_CM33_Core1 for LPC55S69 devices.
183  * @param mboxSetBits Data bits to set in the mailbox.
184  *
185  * @note Sets data bits to send via the MAILBOX to the other core. A value of 0 will
186  * do nothing. Only sets bits selected with a 1 in it's bit position.
187  */
MAILBOX_SetValueBits(MAILBOX_Type * base,mailbox_cpu_id_t cpu_id,uint32_t mboxSetBits)188 static inline void MAILBOX_SetValueBits(MAILBOX_Type *base, mailbox_cpu_id_t cpu_id, uint32_t mboxSetBits)
189 {
190 #if ((defined(LPC55S69_cm33_core0_SERIES) || defined(LPC55S69_cm33_core1_SERIES)) || \
191      defined(LPC55S66_cm33_core0_SERIES) || defined(LPC55S66_cm33_core1_SERIES) || \
192      defined(MCXN947_cm33_core0_SERIES) || defined(MCXN947_cm33_core1_SERIES) || \
193      defined(MCXN946_cm33_core0_SERIES) || defined(MCXN946_cm33_core1_SERIES) || \
194      defined(MCXN547_cm33_core0_SERIES) || defined(MCXN547_cm33_core1_SERIES) || \
195      defined(MCXN546_cm33_core0_SERIES) || defined(MCXN546_cm33_core1_SERIES))
196     assert((cpu_id == kMAILBOX_CM33_Core0) || (cpu_id == kMAILBOX_CM33_Core1));
197 #elif ((defined(LPC54114_cm4_SERIES) || defined(LPC54114_cm0plus_SERIES)))
198     assert((cpu_id == kMAILBOX_CM0Plus) || (cpu_id == kMAILBOX_CM4));
199 #endif
200     base->MBOXIRQ[cpu_id].IRQSET = mboxSetBits;
201 }
202 
203 /*!
204  * @brief Clear data bits in the mailbox based on the CPU ID.
205  *
206  * @param base MAILBOX peripheral base address.
207  * @param cpu_id CPU id, kMAILBOX_CM0Plus or kMAILBOX_CM4 for LPC5410x and LPC5411x devices,
208  *               kMAILBOX_CM33_Core0 or kMAILBOX_CM33_Core1 for LPC55S69 devices.
209  * @param mboxClrBits Data bits to clear in the mailbox.
210  *
211  * @note Clear data bits to send via the MAILBOX to the other core. A value of 0 will
212  * do nothing. Only clears bits selected with a 1 in it's bit position.
213  */
MAILBOX_ClearValueBits(MAILBOX_Type * base,mailbox_cpu_id_t cpu_id,uint32_t mboxClrBits)214 static inline void MAILBOX_ClearValueBits(MAILBOX_Type *base, mailbox_cpu_id_t cpu_id, uint32_t mboxClrBits)
215 {
216 #if ((defined(LPC55S69_cm33_core0_SERIES) || defined(LPC55S69_cm33_core1_SERIES)) || \
217      defined(LPC55S66_cm33_core0_SERIES) || defined(LPC55S66_cm33_core1_SERIES) || \
218      defined(MCXN947_cm33_core0_SERIES) || defined(MCXN947_cm33_core1_SERIES) || \
219      defined(MCXN946_cm33_core0_SERIES) || defined(MCXN946_cm33_core1_SERIES) || \
220      defined(MCXN547_cm33_core0_SERIES) || defined(MCXN547_cm33_core1_SERIES) || \
221      defined(MCXN546_cm33_core0_SERIES) || defined(MCXN546_cm33_core1_SERIES))
222     assert((cpu_id == kMAILBOX_CM33_Core0) || (cpu_id == kMAILBOX_CM33_Core1));
223 #elif ((defined(LPC54114_cm4_SERIES) || defined(LPC54114_cm0plus_SERIES)))
224     assert((cpu_id == kMAILBOX_CM0Plus) || (cpu_id == kMAILBOX_CM4));
225 #endif
226     base->MBOXIRQ[cpu_id].IRQCLR = mboxClrBits;
227 }
228 
229 #elif (defined(CPU_NXH2004J640UK48))
230 
231 /*!
232  * @brief Set data value in the mailbox based on the Mailbox ID.
233  *
234  * @param base MAILBOX peripheral base address.
235  * @param id Mailbox Index for NXH2004 devices
236  * @param mboxData Data to send in the mailbox.
237  *
238  */
MAILBOX_SetValue(MAILBOX_Type * base,mailbox_id_t id,uint32_t mboxData)239 static inline void MAILBOX_SetValue(MAILBOX_Type *base, mailbox_id_t id, uint32_t mboxData)
240 {
241     assert((id >= kMAILBOX_CM0Plus_Core0) && (id <= kMAILBOX_CM0Plus_Sw_Irq3));
242     base->MBOXIRQ[id].IRQ = mboxData;
243 }
244 
245 /*!
246  * @brief Get data in the mailbox based on the Mailbox ID.
247  *
248  * @param base MAILBOX peripheral base address.
249  * @param id, Mailbox index for NXH2004 devies.
250  *
251  * @return Current mailbox data.
252  */
MAILBOX_GetValue(MAILBOX_Type * base,mailbox_id_t id)253 static inline uint32_t MAILBOX_GetValue(MAILBOX_Type *base, mailbox_id_t id)
254 {
255     assert((id >= kMAILBOX_CM0Plus_Core0) && (id <= kMAILBOX_CM0Plus_Sw_Irq3));
256     return base->MBOXIRQ[id].IRQ;
257 }
258 
259 /*!
260  * @brief Set data bits in the mailbox based on the Mailbox Index.
261  *
262  * @param base MAILBOX peripheral base address.
263  * @param id Mailbox Index for NXH2004 devices
264  * @param mboxSetBits Data bits to set in the mailbox.
265  *
266  * @note Sets data bits to send via the MAILBOX. A value of 0 will
267  * do nothing. Only sets bits selected with a 1 in it's bit position.
268  */
MAILBOX_SetValueBits(MAILBOX_Type * base,mailbox_id_t id,uint32_t mboxSetBits)269 static inline void MAILBOX_SetValueBits(MAILBOX_Type *base, mailbox_id_t id, uint32_t mboxSetBits)
270 {
271     assert((id >= kMAILBOX_CM0Plus_Core0) && (id <= kMAILBOX_CM0Plus_Sw_Irq3));
272     base->MBOXIRQ[id].IRQSET = mboxSetBits;
273 }
274 
275 /*!
276  * @brief Clear data bits in the mailbox based on the Mailbox ID.
277  *
278  * @param base MAILBOX peripheral base address.
279  * @param id, Index to Mailbox for NXH2004 devices.
280  * @param mboxClrBits Data bits to clear in the mailbox.
281  *
282  * @note Clear data bits to send via the MAILBOX. A value of 0 will do
283  * nothing. Only clears bits selected with a 1 in it's bit position.
284  */
MAILBOX_ClearValueBits(MAILBOX_Type * base,mailbox_id_t id,uint32_t mboxClrBits)285 static inline void MAILBOX_ClearValueBits(MAILBOX_Type *base, mailbox_id_t id, uint32_t mboxClrBits)
286 {
287     assert((id >= kMAILBOX_CM0Plus_Core0) && (id <= kMAILBOX_CM0Plus_Sw_Irq3));
288     base->MBOXIRQ[id].IRQCLR = mboxClrBits;
289 }
290 
291 #endif /*CPU_NXH2004J640UK48*/
292 
293 /*!
294  * @brief Get MUTEX state and lock mutex
295  *
296  * @param base MAILBOX peripheral base address.
297  *
298  * @return See note
299  *
300  * @note Returns '1' if the mutex was taken or '0' if another resources has the
301  * mutex locked. Once a mutex is taken, it can be returned with the MAILBOX_SetMutex()
302  * function.
303  */
MAILBOX_GetMutex(MAILBOX_Type * base)304 static inline uint32_t MAILBOX_GetMutex(MAILBOX_Type *base)
305 {
306     return (base->MUTEX & MAILBOX_MUTEX_EX_MASK);
307 }
308 
309 /*!
310  * @brief Set MUTEX state
311  *
312  * @param base MAILBOX peripheral base address.
313  *
314  * @note Sets mutex state to '1' and allows other resources to get the mutex.
315  */
MAILBOX_SetMutex(MAILBOX_Type * base)316 static inline void MAILBOX_SetMutex(MAILBOX_Type *base)
317 {
318     base->MUTEX = MAILBOX_MUTEX_EX_MASK;
319 }
320 
321 #if defined(__cplusplus)
322 }
323 #endif /*_cplusplus*/
324 /*! @} */
325 
326 #endif /* FSL_MAILBOX_H_ */
327