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Searched refs:CLK_CTL1_PSCCTL1 (Results 1 – 15 of 15) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/drivers/
Dfsl_clock.h452 #define CLK_CTL1_PSCCTL1 7 macro
617 …CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 0), /*!< Clock gate name: SENSE_ACCESS_RAM_…
618 kCLOCK_Hifi1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 1), /*!< Clock gate name: HIFI1*/
619 kCLOCK_Dma2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 4), /*!< Clock gate name: DMA2*/
620 kCLOCK_Dma3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 5), /*!< Clock gate name: DMA3*/
621 …kCLOCK_LPFlexComm17 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 6), /*!< Clock gate name: LP_Flexcomm17…
622 …kCLOCK_LPFlexComm18 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 7), /*!< Clock gate name: LP_Flexcomm18…
623 …kCLOCK_LPFlexComm19 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 8), /*!< Clock gate name: LP_Flexcomm19…
624 …kCLOCK_LPFlexComm20 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 9), /*!< Clock gate name: LP_Flexcomm20…
625 kCLOCK_LPI2c17 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 6), /*!< Clock gate name: LPI2C17*/
[all …]
Dfsl_clock.c140 case CLK_CTL1_PSCCTL1: in CLOCK_EnableClock()
245 case CLK_CTL1_PSCCTL1: in CLOCK_DisableClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/drivers/
Dfsl_clock.h452 #define CLK_CTL1_PSCCTL1 7 macro
617 …CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 0), /*!< Clock gate name: SENSE_ACCESS_RAM_…
618 kCLOCK_Hifi1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 1), /*!< Clock gate name: HIFI1*/
619 kCLOCK_Dma2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 4), /*!< Clock gate name: DMA2*/
620 kCLOCK_Dma3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 5), /*!< Clock gate name: DMA3*/
621 …kCLOCK_LPFlexComm17 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 6), /*!< Clock gate name: LP_Flexcomm17…
622 …kCLOCK_LPFlexComm18 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 7), /*!< Clock gate name: LP_Flexcomm18…
623 …kCLOCK_LPFlexComm19 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 8), /*!< Clock gate name: LP_Flexcomm19…
624 …kCLOCK_LPFlexComm20 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 9), /*!< Clock gate name: LP_Flexcomm20…
625 kCLOCK_LPI2c17 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 6), /*!< Clock gate name: LPI2C17*/
[all …]
Dfsl_clock.c140 case CLK_CTL1_PSCCTL1: in CLOCK_EnableClock()
245 case CLK_CTL1_PSCCTL1: in CLOCK_DisableClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/drivers/
Dfsl_clock.h452 #define CLK_CTL1_PSCCTL1 7 macro
617 …CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 0), /*!< Clock gate name: SENSE_ACCESS_RAM_…
618 kCLOCK_Hifi1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 1), /*!< Clock gate name: HIFI1*/
619 kCLOCK_Dma2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 4), /*!< Clock gate name: DMA2*/
620 kCLOCK_Dma3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 5), /*!< Clock gate name: DMA3*/
621 …kCLOCK_LPFlexComm17 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 6), /*!< Clock gate name: LP_Flexcomm17…
622 …kCLOCK_LPFlexComm18 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 7), /*!< Clock gate name: LP_Flexcomm18…
623 …kCLOCK_LPFlexComm19 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 8), /*!< Clock gate name: LP_Flexcomm19…
624 …kCLOCK_LPFlexComm20 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 9), /*!< Clock gate name: LP_Flexcomm20…
625 kCLOCK_LPI2c17 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 6), /*!< Clock gate name: LPI2C17*/
[all …]
Dfsl_clock.c140 case CLK_CTL1_PSCCTL1: in CLOCK_EnableClock()
245 case CLK_CTL1_PSCCTL1: in CLOCK_DisableClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT633S/drivers/
Dfsl_clock.h262 #define CLK_CTL1_PSCCTL1 4 macro
339 kCLOCK_HsGpio0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 0), /*!< Clock gate name: HsGpio0*/
340 kCLOCK_HsGpio1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 1), /*!< Clock gate name: HsGpio1*/
341 kCLOCK_HsGpio2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 2), /*!< Clock gate name: HsGpio2*/
342 kCLOCK_HsGpio3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 3), /*!< Clock gate name: HsGpio3*/
343 kCLOCK_HsGpio4 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 4), /*!< Clock gate name: HsGpio4*/
344 kCLOCK_HsGpio5 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 5), /*!< Clock gate name: HsGpio5*/
345 kCLOCK_HsGpio6 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 6), /*!< Clock gate name: HsGpio6*/
346 kCLOCK_HsGpio7 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 7), /*!< Clock gate name: HsGpio7*/
347 kCLOCK_Crc = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 16), /*!< Clock gate name: Crc*/
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/drivers/
Dfsl_clock.h262 #define CLK_CTL1_PSCCTL1 4 macro
339 kCLOCK_HsGpio0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 0), /*!< Clock gate name: HsGpio0*/
340 kCLOCK_HsGpio1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 1), /*!< Clock gate name: HsGpio1*/
341 kCLOCK_HsGpio2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 2), /*!< Clock gate name: HsGpio2*/
342 kCLOCK_HsGpio3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 3), /*!< Clock gate name: HsGpio3*/
343 kCLOCK_HsGpio4 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 4), /*!< Clock gate name: HsGpio4*/
344 kCLOCK_HsGpio5 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 5), /*!< Clock gate name: HsGpio5*/
345 kCLOCK_HsGpio6 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 6), /*!< Clock gate name: HsGpio6*/
346 kCLOCK_HsGpio7 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 7), /*!< Clock gate name: HsGpio7*/
347 kCLOCK_Crc = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 16), /*!< Clock gate name: Crc*/
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/drivers/
Dfsl_clock.h310 #define CLK_CTL1_PSCCTL1 4 macro
429 kCLOCK_HsGpio0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 0), /*!< Clock gate name: HsGpio0*/
430 kCLOCK_HsGpio1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 1), /*!< Clock gate name: HsGpio1*/
431 kCLOCK_HsGpio2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 2), /*!< Clock gate name: HsGpio2*/
432 kCLOCK_HsGpio3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 3), /*!< Clock gate name: HsGpio3*/
433 kCLOCK_HsGpio4 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 4), /*!< Clock gate name: HsGpio4*/
434 kCLOCK_HsGpio5 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 5), /*!< Clock gate name: HsGpio5*/
435 kCLOCK_HsGpio6 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 6), /*!< Clock gate name: HsGpio6*/
436 kCLOCK_HsGpio7 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 7), /*!< Clock gate name: HsGpio7*/
437 kCLOCK_Crc = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 16), /*!< Clock gate name: Crc*/
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/drivers/
Dfsl_clock.h310 #define CLK_CTL1_PSCCTL1 4 macro
429 kCLOCK_HsGpio0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 0), /*!< Clock gate name: HsGpio0*/
430 kCLOCK_HsGpio1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 1), /*!< Clock gate name: HsGpio1*/
431 kCLOCK_HsGpio2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 2), /*!< Clock gate name: HsGpio2*/
432 kCLOCK_HsGpio3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 3), /*!< Clock gate name: HsGpio3*/
433 kCLOCK_HsGpio4 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 4), /*!< Clock gate name: HsGpio4*/
434 kCLOCK_HsGpio5 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 5), /*!< Clock gate name: HsGpio5*/
435 kCLOCK_HsGpio6 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 6), /*!< Clock gate name: HsGpio6*/
436 kCLOCK_HsGpio7 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 7), /*!< Clock gate name: HsGpio7*/
437 kCLOCK_Crc = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 16), /*!< Clock gate name: Crc*/
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/drivers/
Dfsl_clock.h310 #define CLK_CTL1_PSCCTL1 4 macro
429 kCLOCK_HsGpio0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 0), /*!< Clock gate name: HsGpio0*/
430 kCLOCK_HsGpio1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 1), /*!< Clock gate name: HsGpio1*/
431 kCLOCK_HsGpio2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 2), /*!< Clock gate name: HsGpio2*/
432 kCLOCK_HsGpio3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 3), /*!< Clock gate name: HsGpio3*/
433 kCLOCK_HsGpio4 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 4), /*!< Clock gate name: HsGpio4*/
434 kCLOCK_HsGpio5 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 5), /*!< Clock gate name: HsGpio5*/
435 kCLOCK_HsGpio6 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 6), /*!< Clock gate name: HsGpio6*/
436 kCLOCK_HsGpio7 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 7), /*!< Clock gate name: HsGpio7*/
437 kCLOCK_Crc = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 16), /*!< Clock gate name: Crc*/
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/RW612/drivers/
Dfsl_clock.h223 #define CLK_CTL1_PSCCTL1 4 macro
318 kCLOCK_HsGpio0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 0),
319 kCLOCK_HsGpio1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 1),
320 kCLOCK_Crc = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 16),
321 kCLOCK_Freqme = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 31),
Dfsl_clock.c282 case CLK_CTL1_PSCCTL1: in CLOCK_EnableClock()
336 case CLK_CTL1_PSCCTL1: in CLOCK_DisableClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/RW610/drivers/
Dfsl_clock.h223 #define CLK_CTL1_PSCCTL1 4 macro
318 kCLOCK_HsGpio0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 0),
319 kCLOCK_HsGpio1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 1),
320 kCLOCK_Crc = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 16),
321 kCLOCK_Freqme = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 31),
Dfsl_clock.c282 case CLK_CTL1_PSCCTL1: in CLOCK_EnableClock()
336 case CLK_CTL1_PSCCTL1: in CLOCK_DisableClock()