1 /*
2 * Copyright 2020-2024, NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #ifndef _FSL_CLOCK_H_
9 #define _FSL_CLOCK_H_
10
11 #include "fsl_common.h"
12 #include "fsl_reset.h"
13
14 /*! @addtogroup clock */
15 /*! @{ */
16
17 /*! @file */
18
19 /*******************************************************************************
20 * Configurations
21 ******************************************************************************/
22
23 /*! @brief Configure whether driver controls clock
24 *
25 * When set to 0, peripheral drivers will enable clock in initialize function
26 * and disable clock in de-initialize function. When set to 1, peripheral
27 * driver will not control the clock, application could control the clock out of
28 * the driver.
29 *
30 * @note All drivers share this feature switcher. If it is set to 1, application
31 * should handle clock enable and disable for all drivers.
32 */
33 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL))
34 #define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0
35 #endif
36
37 /*******************************************************************************
38 * Definitions
39 ******************************************************************************/
40
41 /*! @name Driver version */
42 /*@{*/
43 /*! @brief CLOCK driver version 2.3.0. */
44 #define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 3, 0))
45 /*@}*/
46
47 /* Definition for delay API in clock driver, users can redefine it to the real application. */
48 #ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
49 #define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (260000000UL)
50 #endif
51
52 /*! @brief Clock ip name array for GPIO. */
53 #define GPIO_CLOCKS \
54 { \
55 kCLOCK_HsGpio0, kCLOCK_HsGpio1 \
56 }
57
58 /*! @brief Clock ip name array for CACHE64. */
59 #define CACHE64_CLOCKS \
60 { \
61 kCLOCK_Flexspi, kCLOCK_Flexspi \
62 }
63
64 /*! @brief Clock ip name array for FLEXSPI. */
65 #define FLEXSPI_CLOCKS \
66 { \
67 kCLOCK_Flexspi \
68 }
69
70 /*! @brief Clock ip name array for FLEXCOMM. */
71 #define FLEXCOMM_CLOCKS \
72 { \
73 kCLOCK_Flexcomm0, kCLOCK_Flexcomm1, kCLOCK_Flexcomm2, kCLOCK_Flexcomm3, kCLOCK_Flexcomm14 \
74 }
75
76 /*! @brief Clock ip name array for LPUART. */
77 #define USART_CLOCKS \
78 { \
79 kCLOCK_Flexcomm0, kCLOCK_Flexcomm1, kCLOCK_Flexcomm2, kCLOCK_Flexcomm3 \
80 }
81
82 /*! @brief Clock ip name array for I2C. */
83 #define I2C_CLOCKS \
84 { \
85 kCLOCK_Flexcomm0, kCLOCK_Flexcomm1, kCLOCK_Flexcomm2, kCLOCK_Flexcomm3 \
86 }
87
88 /*! @brief Clock ip name array for SPI. */
89 #define SPI_CLOCKS \
90 { \
91 kCLOCK_Flexcomm0, kCLOCK_Flexcomm1, kCLOCK_Flexcomm2, kCLOCK_Flexcomm3, kCLOCK_Flexcomm14 \
92 }
93
94 /*! @brief Clock ip name array for ACOMP. */
95 #define ACOMP_CLOCKS \
96 { \
97 kCLOCK_Gau \
98 }
99
100 /*! @brief Clock ip name array for ADC. */
101 #define ADC_CLOCKS \
102 { \
103 kCLOCK_Gau, kCLOCK_Gau \
104 }
105
106 /*! @brief Clock ip name array for DAC. */
107 #define DAC_CLOCKS \
108 { \
109 kCLOCK_Gau \
110 }
111
112 /*! @brief Clock ip name array for LCDIC. */
113 #define LCDIC_CLOCKS \
114 { \
115 kCLOCK_Lcdic \
116 }
117
118 /*! @brief Clock ip name array for DMA. */
119 #define DMA_CLOCKS \
120 { \
121 kCLOCK_Dma0, kCLOCK_Dma1 \
122 }
123
124 /*! @brief Clock ip name array for DMIC. */
125 #define DMIC_CLOCKS \
126 { \
127 kCLOCK_Dmic0 \
128 }
129
130 /*! @brief Clock ip name array for ENET. */
131 #define ENET_CLOCKS \
132 { \
133 kCLOCK_EnetIpg \
134 }
135
136 /*! @brief Extra clock ip name array for ENET. */
137 #define ENET_EXTRA_CLOCKS \
138 { \
139 kCLOCK_EnetIpgS \
140 }
141
142 /*! @brief Clock ip name array for Powerquad */
143 #define POWERQUAD_CLOCKS \
144 { \
145 kCLOCK_PowerQuad \
146 }
147
148 /*! @brief Clock ip name array for OSTimer */
149 #define OSTIMER_CLOCKS \
150 { \
151 kCLOCK_OsEventTimer \
152 }
153
154 /*! @brief Clock ip name array for CT32B. */
155 #define CTIMER_CLOCKS \
156 { \
157 kCLOCK_Ct32b0, kCLOCK_Ct32b1, kCLOCK_Ct32b2, kCLOCK_Ct32b3, kCLOCK_Ct32b4 \
158 }
159
160 /*! @brief Clock ip name array for UTICK. */
161 #define UTICK_CLOCKS \
162 { \
163 kCLOCK_Utick \
164 }
165
166 /*! @brief Clock ip name array for MRT. */
167 #define MRT_CLOCKS \
168 { \
169 kCLOCK_Mrt, kCLOCK_FreeMrt \
170 }
171
172 /*! @brief Clock ip name array for SCT. */
173 #define SCT_CLOCKS \
174 { \
175 kCLOCK_Sct \
176 }
177
178 /*! @brief Clock ip name array for RTC. */
179 #define RTC_CLOCKS \
180 { \
181 kCLOCK_Rtc \
182 }
183
184 /*! @brief Clock ip name array for WWDT. */
185 #define WWDT_CLOCKS \
186 { \
187 kCLOCK_Wwdt0 \
188 }
189
190 /*! @brief Clock ip name array for TRNG. */
191 #define TRNG_CLOCKS \
192 { \
193 kCLOCK_Trng \
194 }
195
196 /*! @brief Clock ip name array for USIM. */
197 #define USIM_CLOCKS \
198 { \
199 kCLOCK_Usim \
200 }
201
202 /*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
203 /*------------------------------------------------------------------------------
204 clock_ip_name_t definition:
205 ------------------------------------------------------------------------------*/
206
207 #define CLK_GATE_REG_OFFSET_SHIFT 8U
208 #define CLK_GATE_REG_OFFSET_MASK 0xFF00U
209 #define CLK_GATE_BIT_SHIFT_SHIFT 0U
210 #define CLK_GATE_BIT_SHIFT_MASK 0x000000FFU
211
212 #define CLK_GATE_DEFINE(reg_offset, bit_shift) \
213 ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \
214 (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK))
215
216 #define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((uint32_t)(x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT)
217 #define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((uint32_t)(x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT)
218
219 #define CLK_CTL0_PSCCTL0 0
220 #define CLK_CTL0_PSCCTL1 1
221 #define CLK_CTL0_PSCCTL2 2
222 #define CLK_CTL1_PSCCTL0 3
223 #define CLK_CTL1_PSCCTL1 4
224 #define CLK_CTL1_PSCCTL2 5
225
226 #define SYS_CLK_GATE_FLAG_MASK (0x10000UL)
227 #define SYS_CLK_GATE_DEFINE(bit_shift) (((bit_shift)&CLK_GATE_BIT_SHIFT_MASK) | SYS_CLK_GATE_FLAG_MASK)
228 #define SYS_CLK_GATE_BIT_MASK(x) (1UL << (((uint32_t)(x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT))
229
230 #define CLKCTL0_TUPLE_MUXA(reg, choice) (((reg)&0xFFCU) | ((choice) << 12U))
231 #define CLKCTL0_TUPLE_MUXB(reg, choice) ((((reg)&0xFFCU) << 16) | ((choice) << 28U))
232 #define CLKCTL1_TUPLE_FLAG_MASK (0x8000U)
233 #define CLKCTL1_TUPLE_MUXA(reg, choice) (((reg)&0xFFCU) | CLKCTL1_TUPLE_FLAG_MASK | ((choice) << 12U))
234 #define CLKCTL1_TUPLE_MUXB(reg, choice) ((((reg)&0xFFCU) | CLKCTL1_TUPLE_FLAG_MASK | ((choice) << 28U)) << 16)
235 #define CLKCTL_TUPLE_REG(base, tuple) ((volatile uint32_t *)(((uint32_t)(base)) + ((uint32_t)(tuple)&0xFFCU)))
236 #define CLKCTL_TUPLE_SEL(tuple) (((uint32_t)(tuple) >> 12U) & 0x7U)
237
238 #define CLKOUT_TUPLE_MUX_AVAIL (0x2U)
239 #define CLKOUT_TUPLE_MUX(ch0, ch1, ch2) (CLKOUT_TUPLE_MUX_AVAIL | ((ch0) << 4U) | ((ch1) << 8) | ((ch2) << 12))
240
241 #define PMU_TUPLE_MUX_AVAIL (0x1U)
242 #define PMU_TUPLE_MUX(reg, choice) (((reg)&0xFFCU) | ((choice) << 12U) | PMU_TUPLE_MUX_AVAIL)
243 #define PMU_TUPLE_REG(base, tuple) ((volatile uint32_t *)(((uint32_t)(base)) + ((uint32_t)(tuple)&0xFFCU)))
244 #define PMU_TUPLE_SEL(tuple) (((uint32_t)(tuple) >> 12U) & 0x3U)
245
246 /*! @brief Clock name used to get clock frequency. */
247 typedef enum _clock_name
248 {
249 kCLOCK_CoreSysClk, /*!< Core clock (aka HCLK) */
250 kCLOCK_BusClk, /*!< Bus clock (AHB/APB clock, aka HCLK) */
251 kCLOCK_MclkClk, /*!< MCLK, to MCLK pin */
252 } clock_name_t;
253
254 /*!
255 * @brief Peripheral clock name difinition used for
256 * clock gate.
257 */
258 typedef enum _clock_ip_name
259 {
260 kCLOCK_IpInvalid = 0U,
261
262 kCLOCK_TcpuMciClk = SYS_CLK_GATE_DEFINE(0),
263 kCLOCK_TcpuMciFlexspiClk = SYS_CLK_GATE_DEFINE(1),
264 kCLOCK_TddrMciEnetClk = SYS_CLK_GATE_DEFINE(2),
265 kCLOCK_TddrMciFlexspiClk = SYS_CLK_GATE_DEFINE(3),
266 kCLOCK_T3PllMciIrcClk = SYS_CLK_GATE_DEFINE(4),
267 kCLOCK_T3PllMci256mClk = SYS_CLK_GATE_DEFINE(5),
268 kCLOCK_T3PllMci213mClk = SYS_CLK_GATE_DEFINE(6),
269 kCLOCK_T3PllMciFlexspiClk = SYS_CLK_GATE_DEFINE(7),
270 kCLOCK_RefClkSys = SYS_CLK_GATE_DEFINE(9),
271 kCLOCK_RefClkTcpu = SYS_CLK_GATE_DEFINE(28),
272 kCLOCK_RefClkTddr = SYS_CLK_GATE_DEFINE(29),
273 kCLOCK_RefClkAud = SYS_CLK_GATE_DEFINE(30),
274 kCLOCK_RefClkUsb = SYS_CLK_GATE_DEFINE(31),
275 kCLOCK_RefClkCauSlp = SYS_CLK_GATE_DEFINE(32),
276
277 kCLOCK_Cpu = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 0),
278 kCLOCK_Matrix = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 1),
279 kCLOCK_Romcp = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 2),
280 kCLOCK_PowerQuad = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 8),
281 kCLOCK_Pkc = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 9),
282 kCLOCK_Els = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 10),
283 kCLOCK_Puf = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 11),
284 kCLOCK_Flexspi = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 16),
285 kCLOCK_Hpu = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 20),
286 kCLOCK_Usb = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 22),
287 kCLOCK_Sct = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 24),
288 kCLOCK_AonMem = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 25),
289 kCLOCK_Gdma = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 28),
290 kCLOCK_Dma0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 29),
291 kCLOCK_Dma1 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 30),
292 kCLOCK_Sdio = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 31),
293
294 kCLOCK_ElsApb = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 0),
295 kCLOCK_SdioSlv = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 2),
296 kCLOCK_Gau = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 16),
297 kCLOCK_Otp = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 17),
298 kCLOCK_SecureGpio = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 24),
299 kCLOCK_EnetIpg = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 25),
300 kCLOCK_EnetIpgS = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 26),
301 kCLOCK_Trng = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 27),
302
303 kCLOCK_Utick = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 0),
304 kCLOCK_Wwdt0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 1),
305 kCLOCK_Usim = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 2),
306 kCLOCK_Itrc = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 3),
307 kCLOCK_FreeMrt = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 26),
308 kCLOCK_Lcdic = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 27),
309
310 kCLOCK_Flexcomm0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 8),
311 kCLOCK_Flexcomm1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 9),
312 kCLOCK_Flexcomm2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 10),
313 kCLOCK_Flexcomm3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 11),
314 kCLOCK_Flexcomm14 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 22),
315 kCLOCK_Dmic0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 24),
316 kCLOCK_OsEventTimer = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 27),
317
318 kCLOCK_HsGpio0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 0),
319 kCLOCK_HsGpio1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 1),
320 kCLOCK_Crc = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 16),
321 kCLOCK_Freqme = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 31),
322
323 kCLOCK_Ct32b0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 0),
324 kCLOCK_Ct32b1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 1),
325 kCLOCK_Ct32b2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 2),
326 kCLOCK_Ct32b3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 3),
327 kCLOCK_Ct32b4 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 4),
328 kCLOCK_Pmu = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 6),
329 kCLOCK_Rtc = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 7),
330 kCLOCK_Mrt = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 8),
331 kCLOCK_Pint = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 30),
332 kCLOCK_InputMux = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 31),
333 } clock_ip_name_t;
334
335 /*!
336 * @brief Peripheral clock source selection definition.
337 */
338 typedef enum _clock_attach_id
339 {
340 kXTAL_to_SYSOSC_CLK = CLKCTL0_TUPLE_MUXA(0x168U, 0),
341 kCLKIN_to_SYSOSC_CLK = CLKCTL0_TUPLE_MUXA(0x168U, 1),
342 kNONE_to_SYSOSC_CLK = CLKCTL0_TUPLE_MUXA(0x168U, 7),
343
344 kSYSOSC_to_MAIN_CLK = CLKCTL0_TUPLE_MUXA(0x430U, 0) | CLKCTL0_TUPLE_MUXB(0x434U, 0),
345 kFFRO_DIV4_to_MAIN_CLK = CLKCTL0_TUPLE_MUXA(0x430U, 1) | CLKCTL0_TUPLE_MUXB(0x434U, 0),
346 kLPOSC_to_MAIN_CLK = CLKCTL0_TUPLE_MUXA(0x430U, 2) | CLKCTL0_TUPLE_MUXB(0x434U, 0),
347 kFFRO_to_MAIN_CLK = CLKCTL0_TUPLE_MUXA(0x430U, 3) | CLKCTL0_TUPLE_MUXB(0x434U, 0),
348 kSFRO_to_MAIN_CLK = CLKCTL0_TUPLE_MUXA(0x434U, 1),
349 kMAIN_PLL_to_MAIN_CLK = CLKCTL0_TUPLE_MUXA(0x434U, 2),
350 kCLK32K_to_MAIN_CLK = CLKCTL0_TUPLE_MUXA(0x434U, 3),
351
352 kMAIN_CLK_to_FLEXSPI_CLK = CLKCTL0_TUPLE_MUXA(0x620U, 0),
353 kT3PLL_MCI_FLEXSPI_to_FLEXSPI_CLK = CLKCTL0_TUPLE_MUXA(0x620U, 1),
354 kAUX0_PLL_to_FLEXSPI_CLK = CLKCTL0_TUPLE_MUXA(0x620U, 2),
355 kTCPU_MCI_FLEXSPI_to_FLEXSPI_CLK = CLKCTL0_TUPLE_MUXA(0x620U, 3),
356 kAUX1_PLL_to_FLEXSPI_CLK = CLKCTL0_TUPLE_MUXA(0x620U, 4),
357 kTDDR_MCI_FLEXSPI_to_FLEXSPI_CLK = CLKCTL0_TUPLE_MUXA(0x620U, 5),
358 kT3PLL_MCI_256M_to_FLEXSPI_CLK = CLKCTL0_TUPLE_MUXA(0x620U, 6),
359 kNONE_to_FLEXSPI_CLK = CLKCTL0_TUPLE_MUXA(0x620U, 7),
360
361 kMAIN_CLK_to_SCT_CLK = CLKCTL0_TUPLE_MUXA(0x640U, 0),
362 kMAIN_PLL_to_SCT_CLK = CLKCTL0_TUPLE_MUXA(0x640U, 1),
363 kAUX0_PLL_to_SCT_CLK = CLKCTL0_TUPLE_MUXA(0x640U, 2),
364 kFFRO_to_SCT_CLK = CLKCTL0_TUPLE_MUXA(0x640U, 3),
365 kAUX1_PLL_to_SCT_CLK = CLKCTL0_TUPLE_MUXA(0x640U, 4),
366 kAUDIO_PLL_to_SCT_CLK = CLKCTL0_TUPLE_MUXA(0x640U, 5),
367 kNONE_to_SCT_CLK = CLKCTL0_TUPLE_MUXA(0x640U, 7),
368
369 kLPOSC_to_UTICK_CLK = CLKCTL0_TUPLE_MUXA(0x700U, 0),
370 kMAIN_CLK_to_UTICK_CLK = CLKCTL0_TUPLE_MUXA(0x700U, 1),
371 kNONE_to_UTICK_CLK = CLKCTL0_TUPLE_MUXA(0x700U, 3),
372
373 kLPOSC_to_WDT0_CLK = CLKCTL0_TUPLE_MUXA(0x720U, 0),
374 kMAIN_CLK_to_WDT0_CLK = CLKCTL0_TUPLE_MUXA(0x720U, 1),
375 kNONE_to_WDT0_CLK = CLKCTL0_TUPLE_MUXA(0x720U, 3),
376
377 kSYSTICK_DIV_to_SYSTICK_CLK = CLKCTL0_TUPLE_MUXA(0x760U, 0),
378 kLPOSC_to_SYSTICK_CLK = CLKCTL0_TUPLE_MUXA(0x760U, 1),
379 kCLK32K_to_SYSTICK_CLK = CLKCTL0_TUPLE_MUXA(0x760U, 2),
380 kSFRO_to_SYSTICK_CLK = CLKCTL0_TUPLE_MUXA(0x760U, 3),
381 kNONE_to_SYSTICK_CLK = CLKCTL0_TUPLE_MUXA(0x760U, 7),
382
383 kMAIN_CLK_to_USIM_CLK = CLKCTL0_TUPLE_MUXA(0x774U, 0),
384 kAUDIO_PLL_to_USIM_CLK = CLKCTL0_TUPLE_MUXA(0x774U, 1),
385 kFFRO_to_USIM_CLK = CLKCTL0_TUPLE_MUXA(0x774U, 2),
386 kNONE_to_USIM_CLK = CLKCTL0_TUPLE_MUXA(0x774U, 3),
387
388 kMAIN_CLK_to_LCD_CLK = CLKCTL0_TUPLE_MUXA(0x778U, 0),
389 kT3PLL_MCI_FLEXSPI_to_LCD_CLK = CLKCTL0_TUPLE_MUXA(0x778U, 1),
390 kTCPU_MCI_FLEXSPI_to_LCD_CLK = CLKCTL0_TUPLE_MUXA(0x778U, 2),
391 kTDDR_MCI_FLEXSPI_to_LCD_CLK = CLKCTL0_TUPLE_MUXA(0x778U, 3),
392 kNONE_to_LCD_CLK = CLKCTL0_TUPLE_MUXA(0x778U, 7),
393
394 kMAIN_CLK_to_GAU_CLK = CLKCTL0_TUPLE_MUXA(0x77CU, 0),
395 kT3PLL_MCI_256M_to_GAU_CLK = CLKCTL0_TUPLE_MUXA(0x77CU, 1),
396 kAVPLL_CH2_to_GAU_CLK = CLKCTL0_TUPLE_MUXA(0x77CU, 2),
397 kNONE_to_GAU_CLK = CLKCTL0_TUPLE_MUXA(0x77CU, 3),
398
399 kT3PLL_MCI_256M_to_ELS_GDET = CLKCTL0_TUPLE_MUXA(0x7A8U, 0),
400 kELS_128M_to_ELS_GDET = CLKCTL0_TUPLE_MUXA(0x7A8U, 1),
401 kELS_64M_to_ELS_GDET = CLKCTL0_TUPLE_MUXA(0x7A8U, 2),
402 kOTP_FUSE_32M_to_ELS_GDET = CLKCTL0_TUPLE_MUXA(0x7A8U, 3),
403 kNONE_to_ELS_GDET = CLKCTL0_TUPLE_MUXA(0x7A8U, 7),
404
405 kLPOSC_to_OSTIMER_CLK = CLKCTL1_TUPLE_MUXA(0x480U, 0),
406 kCLK32K_to_OSTIMER_CLK = CLKCTL1_TUPLE_MUXA(0x480U, 1),
407 kHCLK_to_OSTIMER_CLK = CLKCTL1_TUPLE_MUXA(0x480U, 2),
408 kMAIN_CLK_to_OSTIMER_CLK = CLKCTL1_TUPLE_MUXA(0x480U, 3),
409 kNONE_to_OSTIMER_CLK = CLKCTL1_TUPLE_MUXA(0x480U, 7),
410
411 kSFRO_to_FLEXCOMM0 = CLKCTL1_TUPLE_MUXA(0x508U, 0),
412 kFFRO_to_FLEXCOMM0 = CLKCTL1_TUPLE_MUXA(0x508U, 1),
413 kAUDIO_PLL_to_FLEXCOMM0 = CLKCTL1_TUPLE_MUXA(0x508U, 2),
414 kMCLK_IN_to_FLEXCOMM0 = CLKCTL1_TUPLE_MUXA(0x508U, 3),
415 kFRG_to_FLEXCOMM0 = CLKCTL1_TUPLE_MUXA(0x508U, 4),
416 kNONE_to_FLEXCOMM0 = CLKCTL1_TUPLE_MUXA(0x508U, 7),
417
418 kSFRO_to_FLEXCOMM1 = CLKCTL1_TUPLE_MUXA(0x528U, 0),
419 kFFRO_to_FLEXCOMM1 = CLKCTL1_TUPLE_MUXA(0x528U, 1),
420 kAUDIO_PLL_to_FLEXCOMM1 = CLKCTL1_TUPLE_MUXA(0x528U, 2),
421 kMCLK_IN_to_FLEXCOMM1 = CLKCTL1_TUPLE_MUXA(0x528U, 3),
422 kFRG_to_FLEXCOMM1 = CLKCTL1_TUPLE_MUXA(0x528U, 4),
423 kNONE_to_FLEXCOMM1 = CLKCTL1_TUPLE_MUXA(0x528U, 7),
424
425 kSFRO_to_FLEXCOMM2 = CLKCTL1_TUPLE_MUXA(0x548U, 0),
426 kFFRO_to_FLEXCOMM2 = CLKCTL1_TUPLE_MUXA(0x548U, 1),
427 kAUDIO_PLL_to_FLEXCOMM2 = CLKCTL1_TUPLE_MUXA(0x548U, 2),
428 kMCLK_IN_to_FLEXCOMM2 = CLKCTL1_TUPLE_MUXA(0x548U, 3),
429 kFRG_to_FLEXCOMM2 = CLKCTL1_TUPLE_MUXA(0x548U, 4),
430 kNONE_to_FLEXCOMM2 = CLKCTL1_TUPLE_MUXA(0x548U, 7),
431
432 kSFRO_to_FLEXCOMM3 = CLKCTL1_TUPLE_MUXA(0x568U, 0),
433 kFFRO_to_FLEXCOMM3 = CLKCTL1_TUPLE_MUXA(0x568U, 1),
434 kAUDIO_PLL_to_FLEXCOMM3 = CLKCTL1_TUPLE_MUXA(0x568U, 2),
435 kMCLK_IN_to_FLEXCOMM3 = CLKCTL1_TUPLE_MUXA(0x568U, 3),
436 kFRG_to_FLEXCOMM3 = CLKCTL1_TUPLE_MUXA(0x568U, 4),
437 kNONE_to_FLEXCOMM3 = CLKCTL1_TUPLE_MUXA(0x568U, 7),
438
439 kSFRO_to_FLEXCOMM14 = CLKCTL1_TUPLE_MUXA(0x6C8U, 0),
440 kFFRO_to_FLEXCOMM14 = CLKCTL1_TUPLE_MUXA(0x6C8U, 1),
441 kAUDIO_PLL_to_FLEXCOMM14 = CLKCTL1_TUPLE_MUXA(0x6C8U, 2),
442 kMCLK_IN_to_FLEXCOMM14 = CLKCTL1_TUPLE_MUXA(0x6C8U, 3),
443 kFRG_to_FLEXCOMM14 = CLKCTL1_TUPLE_MUXA(0x6C8U, 4),
444 kNONE_to_FLEXCOMM14 = CLKCTL1_TUPLE_MUXA(0x6C8U, 7),
445
446 kSFRO_to_DMIC_CLK = CLKCTL1_TUPLE_MUXA(0x700U, 0),
447 kFFRO_to_DMIC_CLK = CLKCTL1_TUPLE_MUXA(0x700U, 1),
448 kAUDIO_PLL_to_DMIC_CLK = CLKCTL1_TUPLE_MUXA(0x700U, 2),
449 kMCLK_IN_to_DMIC_CLK = CLKCTL1_TUPLE_MUXA(0x700U, 3),
450 kLPOSC_to_DMIC_CLK = CLKCTL1_TUPLE_MUXA(0x700U, 4),
451 kCLK32K_to_DMIC_CLK = CLKCTL1_TUPLE_MUXA(0x700U, 5),
452 kMAIN_CLK_to_DMIC_CLK = CLKCTL1_TUPLE_MUXA(0x700U, 6),
453 kNONE_to_DMIC_CLK = CLKCTL1_TUPLE_MUXA(0x700U, 7),
454
455 kMAIN_CLK_to_CTIMER0 = CLKCTL1_TUPLE_MUXA(0x720U, 0),
456 kSFRO_to_CTIMER0 = CLKCTL1_TUPLE_MUXA(0x720U, 1),
457 kFFRO_to_CTIMER0 = CLKCTL1_TUPLE_MUXA(0x720U, 2),
458 kAUDIO_PLL_to_CTIMER0 = CLKCTL1_TUPLE_MUXA(0x720U, 3),
459 kMCLK_IN_to_CTIMER0 = CLKCTL1_TUPLE_MUXA(0x720U, 4),
460 kLPOSC_to_CTIMER0 = CLKCTL1_TUPLE_MUXA(0x720U, 5),
461 kNONE_to_CTIMER0 = CLKCTL1_TUPLE_MUXA(0x720U, 7),
462
463 kMAIN_CLK_to_CTIMER1 = CLKCTL1_TUPLE_MUXA(0x724U, 0),
464 kSFRO_to_CTIMER1 = CLKCTL1_TUPLE_MUXA(0x724U, 1),
465 kFFRO_to_CTIMER1 = CLKCTL1_TUPLE_MUXA(0x724U, 2),
466 kAUDIO_PLL_to_CTIMER1 = CLKCTL1_TUPLE_MUXA(0x724U, 3),
467 kMCLK_IN_to_CTIMER1 = CLKCTL1_TUPLE_MUXA(0x724U, 4),
468 kLPOSC_to_CTIMER1 = CLKCTL1_TUPLE_MUXA(0x724U, 5),
469 kNONE_to_CTIMER1 = CLKCTL1_TUPLE_MUXA(0x724U, 7),
470
471 kMAIN_CLK_to_CTIMER2 = CLKCTL1_TUPLE_MUXA(0x728U, 0),
472 kSFRO_to_CTIMER2 = CLKCTL1_TUPLE_MUXA(0x728U, 1),
473 kFFRO_to_CTIMER2 = CLKCTL1_TUPLE_MUXA(0x728U, 2),
474 kAUDIO_PLL_to_CTIMER2 = CLKCTL1_TUPLE_MUXA(0x728U, 3),
475 kMCLK_IN_to_CTIMER2 = CLKCTL1_TUPLE_MUXA(0x728U, 4),
476 kLPOSC_to_CTIMER2 = CLKCTL1_TUPLE_MUXA(0x728U, 5),
477 kNONE_to_CTIMER2 = CLKCTL1_TUPLE_MUXA(0x728U, 7),
478
479 kMAIN_CLK_to_CTIMER3 = CLKCTL1_TUPLE_MUXA(0x72CU, 0),
480 kSFRO_to_CTIMER3 = CLKCTL1_TUPLE_MUXA(0x72CU, 1),
481 kFFRO_to_CTIMER3 = CLKCTL1_TUPLE_MUXA(0x72CU, 2),
482 kAUDIO_PLL_to_CTIMER3 = CLKCTL1_TUPLE_MUXA(0x72CU, 3),
483 kMCLK_IN_to_CTIMER3 = CLKCTL1_TUPLE_MUXA(0x72CU, 4),
484 kLPOSC_to_CTIMER3 = CLKCTL1_TUPLE_MUXA(0x72CU, 5),
485 kNONE_to_CTIMER3 = CLKCTL1_TUPLE_MUXA(0x72CU, 7),
486
487 kFFRO_to_MCLK_CLK = CLKCTL1_TUPLE_MUXA(0x740U, 0),
488 kAUDIO_PLL_to_MCLK_CLK = CLKCTL1_TUPLE_MUXA(0x740U, 1),
489 kMAIN_CLK_to_MCLK_CLK = CLKCTL1_TUPLE_MUXA(0x740U, 2),
490 kNONE_to_MCLK_CLK = CLKCTL1_TUPLE_MUXA(0x740U, 3),
491
492 kSFRO_to_CLKOUT = CLKOUT_TUPLE_MUX(0U, 0U, 0U),
493 kSYSOSC_to_CLKOUT = CLKOUT_TUPLE_MUX(1U, 0U, 0U),
494 kLPOSC_to_CLKOUT = CLKOUT_TUPLE_MUX(2U, 0U, 0U),
495 kFFRO_to_CLKOUT = CLKOUT_TUPLE_MUX(3U, 0U, 0U),
496 kMAIN_CLK_to_CLKOUT = CLKOUT_TUPLE_MUX(4U, 0U, 0U),
497 kREFCLK_SYS_to_CLKOUT = CLKOUT_TUPLE_MUX(5U, 0U, 0U),
498 kAVPLL_CH2_to_CLKOUT = CLKOUT_TUPLE_MUX(6U, 0U, 0U),
499 kMAIN_PLL_to_CLKOUT = CLKOUT_TUPLE_MUX(7U, 1U, 0U),
500 kAUX0_PLL_to_CLKOUT = CLKOUT_TUPLE_MUX(7U, 2U, 0U),
501 kAUX1_PLL_to_CLKOUT = CLKOUT_TUPLE_MUX(7U, 4U, 0U),
502 kAUDIO_PLL_to_CLKOUT = CLKOUT_TUPLE_MUX(7U, 5U, 0U),
503 kCLK32K_to_CLKOUT = CLKOUT_TUPLE_MUX(7U, 6U, 0U),
504 kTCPU_MCI_FLEXSPI_to_CLKOUT = CLKOUT_TUPLE_MUX(7U, 7U, 1U),
505 kTDDR_MCI_FLEXSPI_to_CLKOUT = CLKOUT_TUPLE_MUX(7U, 7U, 2U),
506 kT3PLL_MCI_FLEXSPI_to_CLKOUT = CLKOUT_TUPLE_MUX(7U, 7U, 3U),
507 kT3PLL_MCI_256M_to_CLKOUT = CLKOUT_TUPLE_MUX(7U, 7U, 4U),
508 kCAU_SLP_REF_CLK_to_CLKOUT = CLKOUT_TUPLE_MUX(7U, 7U, 5U),
509 kTDDR_MCI_ENET_to_CLKOUT = CLKOUT_TUPLE_MUX(7U, 7U, 6U),
510 kNONE_to_CLKOUT = CLKOUT_TUPLE_MUX(7U, 7U, 7U),
511
512 kRC32K_to_CLK32K = PMU_TUPLE_MUX(0x70U, 0),
513 kXTAL32K_to_CLK32K = PMU_TUPLE_MUX(0x70U, 1),
514 kNCO32K_to_CLK32K = PMU_TUPLE_MUX(0x70U, 2),
515 } clock_attach_id_t;
516
517 /*!
518 * @brief Clock divider definition.
519 */
520 typedef enum _clock_div_name
521 {
522 kCLOCK_DivMainPllClk = CLKCTL0_TUPLE_MUXA(0x240U, 0),
523 kCLOCK_DivAux0PllClk = CLKCTL0_TUPLE_MUXA(0x248U, 0),
524 kCLOCK_DivAux1PllClk = CLKCTL0_TUPLE_MUXA(0x24CU, 0),
525 kCLOCK_DivSysCpuAhbClk = CLKCTL0_TUPLE_MUXA(0x400U, 0),
526 kCLOCK_DivPfc1Clk = CLKCTL0_TUPLE_MUXA(0x504U, 0),
527 kCLOCK_DivFlexspiClk = CLKCTL0_TUPLE_MUXA(0x624U, 0),
528 kCLOCK_DivSctClk = CLKCTL0_TUPLE_MUXA(0x644U, 0),
529 kCLOCK_DivUsbHsFclk = CLKCTL0_TUPLE_MUXA(0x664U, 0),
530 kCLOCK_DivSystickClk = CLKCTL0_TUPLE_MUXA(0x764U, 0),
531 kCLOCK_DivLcdClk = CLKCTL0_TUPLE_MUXA(0x768U, 0),
532 kCLOCK_DivGauClk = CLKCTL0_TUPLE_MUXA(0x76CU, 0),
533 kCLOCK_DivUsimClk = CLKCTL0_TUPLE_MUXA(0x770U, 0),
534 kCLOCK_DivPmuFclk = CLKCTL0_TUPLE_MUXA(0x780U, 0),
535
536 kCLOCK_DivAudioPllClk = CLKCTL1_TUPLE_MUXA(0x240U, 0),
537 kCLOCK_DivPllFrgClk = CLKCTL1_TUPLE_MUXA(0x6FCU, 0),
538 kCLOCK_DivDmicClk = CLKCTL1_TUPLE_MUXA(0x704U, 0),
539 kCLOCK_DivMclkClk = CLKCTL1_TUPLE_MUXA(0x744U, 0),
540 kCLOCK_DivClockOut = CLKCTL1_TUPLE_MUXA(0x768U, 0),
541 } clock_div_name_t;
542
543 /*! @brief PLL configuration for FRG */
544 typedef struct _clock_frg_clk_config
545 {
546 uint8_t num; /*!< FRG clock */
547 enum
548 {
549 kCLOCK_FrgMainClk = 0, /*!< Main System clock */
550 kCLOCK_FrgPllDiv, /*!< Main pll clock divider*/
551 kCLOCK_FrgSFro, /*!< 16MHz FRO */
552 kCLOCK_FrgFFro, /*!< FRO48/60 */
553 } sfg_clock_src;
554 uint8_t divider; /*!< Denominator of the fractional divider. */
555 uint8_t mult; /*!< Numerator of the fractional divider. */
556 } clock_frg_clk_config_t;
557
558 /*! @brief TCPU PLL divider for tcpu_mci_flexspi_clk */
559 typedef enum
560 {
561 kCLOCK_TcpuFlexspiDiv12 = 0, /*!< Divided by 12 */
562 kCLOCK_TcpuFlexspiDiv11, /*!< Divided by 11 */
563 kCLOCK_TcpuFlexspiDiv10, /*!< Divided by 10 */
564 kCLOCK_TcpuFlexspiDiv9, /*!< Divided by 9 */
565 } clock_tcpu_flexspi_div_t;
566
567 /*! @brief TDDR PLL divider for tddr_mci_flexspi_clk */
568 typedef enum
569 {
570 kCLOCK_TddrFlexspiDiv11 = 0, /*!< Divided by 11 */
571 kCLOCK_TddrFlexspiDiv10, /*!< Divided by 10 */
572 kCLOCK_TddrFlexspiDiv9, /*!< Divided by 9 */
573 kCLOCK_TddrFlexspiDiv8, /*!< Divided by 8 */
574 } clock_tddr_flexspi_div_t;
575
576 /*! @brief T3 PLL IRC configuration */
577 typedef enum
578 {
579 kCLOCK_T3MciIrc60m = 0, /*!< T3 MCI IRC 59.53MHz */
580 kCLOCK_T3MciIrc48m, /*!< T3 MCI IRC 48.30MHz */
581 } clock_t3_mci_irc_config_t;
582
583 /*! @brief AVPLL channel1 frequency configuration */
584 typedef enum
585 {
586 kCLOCK_AvPllChUnchanged = 0, /*!< AVPLL channel frequency unchanged. */
587 kCLOCK_AvPllChFreq2p048m, /*!< AVPLL channel frequency 2.048MHz */
588 kCLOCK_AvPllChFreq4p096m, /*!< AVPLL channel frequency 4.096MHz */
589 kCLOCK_AvPllChFreq6p144m, /*!< AVPLL channel frequency 6.144MHz */
590 kCLOCK_AvPllChFreq8p192m, /*!< AVPLL channel frequency 8.192MHz */
591 kCLOCK_AvPllChFreq11p2896m, /*!< AVPLL channel frequency 11.2896MHz */
592 kCLOCK_AvPllChFreq12m, /*!< AVPLL channel frequency 12MHz */
593 kCLOCK_AvPllChFreq12p288m, /*!< AVPLL channel frequency 12.288MHz */
594 kCLOCK_AvPllChFreq24p576m, /*!< AVPLL channel frequency 24.576MHz */
595 kCLOCK_AvPllChFreq64m, /*!< AVPLL channel frequency 64MHz */
596 kCLOCK_AvPllChFreq98p304m, /*!< AVPLL channel frequency 98.304MHz */
597 } clock_avpll_ch_freq_t;
598
599 /*! @brief AVPLL configuration */
600 typedef struct
601 {
602 clock_avpll_ch_freq_t ch1Freq; /*!< AVPLL channel 1 frequency configuration */
603 clock_avpll_ch_freq_t ch2Freq; /*!< AVPLL channel 2 frequency configuration */
604 bool enableCali; /*!< Enable calibration */
605 } clock_avpll_config_t;
606
607 /*******************************************************************************
608 * API
609 ******************************************************************************/
610
611 #if defined(__cplusplus)
612 extern "C" {
613 #endif /* __cplusplus */
614
615 /*! @brief External CLK_IN pin clock frequency (clkin) clock frequency.
616 *
617 * The CLK_IN pin (clkin) clock frequency in Hz, when the clock is setup, use the
618 * function CLOCK_SetClkinFreq to set the value in to clock driver. For example,
619 * if CLK_IN is 16MHz,
620 * @code
621 * CLOCK_SetClkinFreq(16000000);
622 * @endcode
623 */
624 extern volatile uint32_t g_clkinFreq;
625 /*! @brief External MCLK IN clock frequency.
626 *
627 * The MCLK in (mclk_in) PIN clock frequency in Hz, when the clock is setup, use the
628 * function CLOCK_SetMclkInFreq to set the value in to clock driver. For example,
629 * if mclk_In is 16MHz,
630 * @code
631 * CLOCK_SetMclkInFreq(16000000);
632 * @endcode
633 */
634 extern volatile uint32_t g_mclkinFreq;
635
636 /*! @brief Return Frequency of t3pll_mci_48_60m_irc
637 * @return Frequency of t3pll_mci_48_60m_irc
638 */
639 uint32_t CLOCK_GetT3PllMciIrcClkFreq(void);
640
641 /*! @brief Return Frequency of t3pll_mci_213p3m
642 * @return Frequency of t3pll_mci_213p3m
643 */
644 uint32_t CLOCK_GetT3PllMci213mClkFreq(void);
645
646 /*! @brief Return Frequency of t3pll_mci_256m
647 * @return Frequency of t3pll_mci_256m
648 */
649 uint32_t CLOCK_GetT3PllMci256mClkFreq(void);
650
651 /*! @brief Return Frequency of t3pll_mci_flexspi_clk
652 * @return Frequency of t3pll_mci_flexspi_clk
653 */
654 uint32_t CLOCK_GetT3PllMciFlexspiClkFreq(void);
655
656 /*! @brief Return Frequency of tcpu_mci_clk
657 * @return Frequency of tcpu_mci_clk
658 */
659 uint32_t CLOCK_GetTcpuMciClkFreq(void);
660
661 /*! @brief Return Frequency of tcpu_mci_flexspi_clk
662 * @return Frequency of tcpu_mci_flexspi_clk
663 */
664 uint32_t CLOCK_GetTcpuMciFlexspiClkFreq(void);
665
666 /*! @brief Return Frequency of tddr_mci_flexspi_clk
667 * @return Frequency of tddr_mci_flexspi_clk
668 */
669 uint32_t CLOCK_GetTddrMciFlexspiClkFreq(void);
670
671 /*! @brief Return Frequency of tddr_mci_enet_clk
672 * @return Frequency of tddr_mci_enet_clk
673 */
674 uint32_t CLOCK_GetTddrMciEnetClkFreq(void);
675
676 /*!
677 * @brief Enable the clock for specific IP.
678 *
679 * @param clk Which clock to enable, see @ref clock_ip_name_t.
680 */
681 void CLOCK_EnableClock(clock_ip_name_t clk);
682
683 /*!
684 * @brief Disable the clock for specific IP.
685 *
686 * @param clk Which clock to disable, see @ref clock_ip_name_t.
687 */
688 void CLOCK_DisableClock(clock_ip_name_t clk);
689
690 /**
691 * @brief Configure the clock selection muxes.
692 * @param connection : Clock to be configured.
693 */
694 void CLOCK_AttachClk(clock_attach_id_t connection);
695
696 /**
697 * @brief Setup clock dividers.
698 * @param name : Clock divider name
699 * @param divider : Value to be divided.
700 */
701 void CLOCK_SetClkDiv(clock_div_name_t name, uint32_t divider);
702
703 /*! @brief Return Frequency of selected clock
704 * @return Frequency of selected clock
705 */
706 uint32_t CLOCK_GetFreq(clock_name_t clockName);
707
708 /*! @brief Return Input frequency for the Fractional baud rate generator
709 * @return Input Frequency for FRG
710 */
711 uint32_t CLOCK_GetFRGClock(uint32_t id);
712
713 /*! @brief Set output of the Fractional baud rate generator
714 * @param config : Configuration to set to FRGn clock.
715 */
716 void CLOCK_SetFRGClock(const clock_frg_clk_config_t *config);
717
718 /*! @brief Return Frequency of FFRO
719 * @return Frequency of FFRO
720 */
721 uint32_t CLOCK_GetFFroFreq(void);
722
723 /*! @brief Return Frequency of SFRO
724 * @return Frequency of SFRO
725 */
726 uint32_t CLOCK_GetSFroFreq(void);
727
728 /*! @brief Return Frequency of AUDIO PLL (AVPLL CH1)
729 * @return Frequency of AUDIO PLL
730 */
731 uint32_t CLOCK_GetAvPllCh1Freq(void);
732
733 /*! @brief Return Frequency of AVPLL CH2
734 * @return Frequency of AVPLL CH2
735 */
736 uint32_t CLOCK_GetAvPllCh2Freq(void);
737
738 /*! @brief Return Frequency of main clk
739 * @return Frequency of main clk
740 */
741 uint32_t CLOCK_GetMainClkFreq(void);
742
743 /*! @brief Return Frequency of core/bus clk
744 * @return Frequency of core/bus clk
745 */
746 uint32_t CLOCK_GetCoreSysClkFreq(void);
747
748 /*! @brief Return Frequency of systick clk
749 * @return Frequency of systick clk
750 */
751 uint32_t CLOCK_GetSystickClkFreq(void);
752
753 /*! @brief Return Frequency of sys osc Clock
754 * @return Frequency of sys osc Clock. Or CLK_IN pin frequency.
755 */
CLOCK_GetSysOscFreq(void)756 static inline uint32_t CLOCK_GetSysOscFreq(void)
757 {
758 return (CLKCTL0->SYSOSCBYPASS == 0U) ? CLK_XTAL_OSC_CLK : ((CLKCTL0->SYSOSCBYPASS == 1U) ? g_clkinFreq : 0U);
759 }
760
761 /*! @brief Return Frequency of MCLK Input Clock
762 * @return Frequency of MCLK input Clock.
763 */
CLOCK_GetMclkInClkFreq(void)764 static inline uint32_t CLOCK_GetMclkInClkFreq(void)
765 {
766 return g_mclkinFreq;
767 }
768
769 /*! @brief Return Frequency of LPOSC
770 * @return Frequency of LPOSC
771 */
CLOCK_GetLpOscFreq(void)772 static inline uint32_t CLOCK_GetLpOscFreq(void)
773 {
774 return CLK_XTAL_OSC_CLK / 40U;
775 }
776
777 /*! @brief Return Frequency of CLK_32K
778 * @return Frequency of 32KHz osc
779 */
CLOCK_GetClk32KFreq(void)780 static inline uint32_t CLOCK_GetClk32KFreq(void)
781 {
782 return CLK_RTC_32K_CLK;
783 }
784
785 /*! @brief Enables and disables 32KHz XTAL
786 * @param enable : true to enable 32k XTAL clock, false to disable clock
787 */
788 void CLOCK_EnableXtal32K(bool enable);
789
790 /*! @brief Enables and disables RTC 32KHz
791 * @param enable : true to enable 32k RTC clock, false to disable clock
792 */
793 void CLOCK_EnableRtc32K(bool enable);
794
795 /*!
796 * @brief Set the CLKIN (CLKIN pin) frequency based on GPIO4 input.
797 *
798 * @param freq : The CLK_IN pin input clock frequency in Hz.
799 */
CLOCK_SetClkinFreq(uint32_t freq)800 static inline void CLOCK_SetClkinFreq(uint32_t freq)
801 {
802 g_clkinFreq = freq;
803 }
804 /*!
805 * @brief Set the MCLK in (mclk_in) clock frequency based on board setting.
806 *
807 * @param freq : The MCLK input clock frequency in Hz.
808 */
CLOCK_SetMclkinFreq(uint32_t freq)809 static inline void CLOCK_SetMclkinFreq(uint32_t freq)
810 {
811 g_mclkinFreq = freq;
812 }
813
814 /*! @brief Return Frequency of DMIC clk
815 * @return Frequency of DMIC clk
816 */
817 uint32_t CLOCK_GetDmicClkFreq(void);
818
819 /*! @brief Return Frequency of LCD clk
820 * @return Frequency of LCD clk
821 */
822 uint32_t CLOCK_GetLcdClkFreq(void);
823
824 /*! @brief Return Frequency of WDT clk
825 * @return Frequency of WDT clk
826 */
827 uint32_t CLOCK_GetWdtClkFreq(void);
828
829 /*! @brief Return Frequency of mclk
830 * @return Frequency of mclk clk
831 */
832 uint32_t CLOCK_GetMclkClkFreq(void);
833
834 /*! @brief Return Frequency of sct
835 * @return Frequency of sct clk
836 */
837 uint32_t CLOCK_GetSctClkFreq(void);
838
839 /*! @brief Return Frequency of Flexcomm functional Clock
840 * @param id : flexcomm index to get frequency.
841 * @return Frequency of Flexcomm functional Clock
842 */
843 uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id);
844
845 /*! @brief Return Frequency of CTimer Clock
846 * @param id : ctimer index to get frequency.
847 * @return Frequency of CTimer Clock
848 */
849 uint32_t CLOCK_GetCTimerClkFreq(uint32_t id);
850
851 /*! @brief Return Frequency of Utick Clock
852 * @return Frequency of Utick Clock
853 */
854 uint32_t CLOCK_GetUtickClkFreq(void);
855
856 /*! @brief Return Frequency of Flexspi Clock
857 * @return Frequency of Flexspi.
858 */
859 uint32_t CLOCK_GetFlexspiClkFreq(void);
860
861 /*! @brief Return Frequency of USIM Clock
862 * @return Frequency of USIM.
863 */
864 uint32_t CLOCK_GetUsimClkFreq(void);
865
866 /*! @brief Return Frequency of GAU Clock
867 * @return Frequency of GAU.
868 */
869 uint32_t CLOCK_GetGauClkFreq(void);
870
871 /*! @brief Return Frequency of OSTimer Clock
872 * @return Frequency of OSTimer.
873 */
874 uint32_t CLOCK_GetOSTimerClkFreq(void);
875
876 /*! @brief Initialize TCPU FVCO to target frequency.
877 * For 40MHz XTAL, FVCO ranges from 3000MHz to 3840MHz.
878 For 38.4MHz XTAL, FVCO ranges from 2995.2MHz to 3840MHz
879 * @param targetHz : Target FVCO frequency in Hz.
880 * @param div : Divider for tcpu_mci_flexspi_clk.
881 * @return Actual FVCO frequency in Hz.
882 */
883 uint32_t CLOCK_InitTcpuRefClk(uint32_t targetHz, clock_tcpu_flexspi_div_t div);
884
885 /*! @brief Deinit the TCPU reference clock.
886 */
887 void CLOCK_DeinitTcpuRefClk(void);
888
889 /*! @brief Initialize the TDDR reference clock.
890 * @param div : Divider for tddr_mci_flexspi_clk.
891 */
892 void CLOCK_InitTddrRefClk(clock_tddr_flexspi_div_t div);
893
894 /*! @brief Deinit the TDDR reference clock.
895 */
896 void CLOCK_DeinitTddrRefClk(void);
897
898 /*! @brief Initialize the T3 reference clock.
899 * @param cnfg : t3pll_mci_48_60m_irc clock configuration
900 */
901 void CLOCK_InitT3RefClk(clock_t3_mci_irc_config_t cnfg);
902
903 /*! @brief Deinit the T3 reference clock. */
904 void CLOCK_DeinitT3RefClk(void);
905
906 /*! @brief Initialize the AVPLL. Both channel 1 and 2 are enabled.
907 * @param cnfg : AVPLL clock configuration
908 */
909 void CLOCK_InitAvPll(const clock_avpll_config_t *cnfg);
910
911 /*! @brief Deinit the AVPLL. All channels are disabled.
912 */
913 void CLOCK_DeinitAvPll(void);
914
915 /*! @brief Update the AVPLL channel configuration. Enable/Disable state keeps unchanged.
916 * @param ch1Freq : Channel 1 frequency to set.
917 * @param ch2Freq : Channel 2 frequency to set.
918 * @param enableCali : Enable AVPLL calibration.
919 */
920 void CLOCK_ConfigAvPllCh(clock_avpll_ch_freq_t ch1Freq, clock_avpll_ch_freq_t ch2Freq, bool enableCali);
921
922 /*! @brief Enable the AVPLL channel.
923 * @param enableCh1 : Enable AVPLL channel1, channel unchanged on false.
924 * @param enableCh2 : Enable AVPLL channel2, channel unchanged on false.
925 * @param enableCali : Enable AVPLL calibration.
926 */
927 void CLOCK_EnableAvPllCh(bool enableCh1, bool enableCh2, bool enableCali);
928
929 /*! @brief Disable the AVPLL.
930 * @param disableCh1 : Disable AVPLL channel1, channel unchanged on false.
931 * @param disableCh2 : Disable AVPLL channel2, channel unchanged on false.
932 */
933 void CLOCK_DisableAvPllCh(bool disableCh1, bool disableCh2);
934
935 /*! @brief Enable USB HS PHY PLL clock.
936 *
937 * This function enables USB HS PHY PLL clock.
938 */
939 void CLOCK_EnableUsbhsPhyClock(void);
940
941 /*! @brief Disable USB HS PHY PLL clock.
942 *
943 * This function disables USB HS PHY PLL clock.
944 */
945 void CLOCK_DisableUsbhsPhyClock(void);
946
947 #if defined(__cplusplus)
948 }
949 #endif /* __cplusplus */
950
951 /*! @} */
952
953 #endif /* _FSL_CLOCK_H_ */
954
