1 /*
2 * Copyright (c) 2016, Freescale Semiconductor, Inc.
3 * Copyright 2016 - 2022 , NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 #ifndef _FSL_CLOCK_H_
10 #define _FSL_CLOCK_H_
11
12 #include "fsl_device_registers.h"
13 #include <stdint.h>
14 #include <stdbool.h>
15 #include <assert.h>
16 #include "fsl_reset.h"
17 #include "fsl_common.h"
18
19 /*! @addtogroup clock */
20 /*! @{ */
21
22 /*! @file */
23
24 /*******************************************************************************
25 * Definitions
26 *****************************************************************************/
27
28 /*! @name Driver version */
29 /*@{*/
30 /*! @brief CLOCK driver version 2.7.2. */
31 #define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 7, 2))
32 /*@}*/
33
34 /* Definition for delay API in clock driver, users can redefine it to the real application. */
35 #ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
36 #ifdef __XTENSA__
37 #define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (600000000UL)
38 #else
39 #define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (300000000UL)
40 #endif
41 #endif
42
43 /* Definition for compatiblity with other platforms. */
44 #define CLOCK_GetCTimerClkFreq CLOCK_GetCtimerClkFreq
45
46 /*! @brief External XTAL (SYSOSC) clock frequency.
47 *
48 * The XTAL (SYSOSC) clock frequency in Hz, when the clock is setup, use the
49 * function CLOCK_SetXtalFreq to set the value in to clock driver. For example,
50 * if XTAL is 16MHz,
51 * @code
52 * CLOCK_SetXtalFreq(160000000);
53 * @endcode
54 */
55 extern volatile uint32_t g_xtalFreq;
56 /*! @brief External CLK_IN pin clock frequency (clkin) clock frequency.
57 *
58 * The CLK_IN pin (clkin) clock frequency in Hz, when the clock is setup, use the
59 * function CLOCK_SetClkinFreq to set the value in to clock driver. For example,
60 * if CLK_IN is 16MHz,
61 * @code
62 * CLOCK_SetClkinFreq(160000000);
63 * @endcode
64 */
65 extern volatile uint32_t g_clkinFreq;
66 /*! @brief External XTAL (SYSOSC) clock frequency.
67 *
68 * The MCLK in (mclk_in) PIN clock frequency in Hz, when the clock is setup, use the
69 * function CLOCK_SetMclkInFreq to set the value in to clock driver. For example,
70 * if mclk_In is 16MHz,
71 * @code
72 * CLOCK_SetMclkInFreq(160000000);
73 * @endcode
74 */
75 extern volatile uint32_t g_mclkFreq;
76
77 /*! @brief Clock ip name array for ACMP. */
78 #define CMP_CLOCKS \
79 { \
80 kCLOCK_Acmp0 \
81 }
82 /*! @brief Clock ip name array for FLEXCOMM. */
83 #define FLEXCOMM_CLOCKS \
84 { \
85 kCLOCK_Flexcomm0, kCLOCK_Flexcomm1, kCLOCK_Flexcomm2, kCLOCK_Flexcomm3, kCLOCK_Flexcomm4, kCLOCK_Flexcomm5, \
86 kCLOCK_Flexcomm6, kCLOCK_Flexcomm7, kCLOCK_Flexcomm14, kCLOCK_Flexcomm15 \
87 }
88 /*! @brief Clock ip name array for LPUART. */
89 #define USART_CLOCKS \
90 { \
91 kCLOCK_Usart0, kCLOCK_Usart1, kCLOCK_Usart2, kCLOCK_Usart3, kCLOCK_Usart4, kCLOCK_Usart5, kCLOCK_Usart6, \
92 kCLOCK_Usart7 \
93 }
94
95 /*! @brief Clock ip name array for I2C. */
96 #define I2C_CLOCKS \
97 { \
98 kCLOCK_I2c0, kCLOCK_I2c1, kCLOCK_I2c2, kCLOCK_I2c3, kCLOCK_I2c4, kCLOCK_I2c5, kCLOCK_I2c6, kCLOCK_I2c7, \
99 kCLOCK_I2c15 \
100 }
101 /*! @brief Clock ip name array for I3C. */
102 #define I3C_CLOCKS \
103 { \
104 kCLOCK_I3c0 \
105 }
106 /*! @brief Clock ip name array for SPI. */
107 #define SPI_CLOCKS \
108 { \
109 kCLOCK_Spi0, kCLOCK_Spi1, kCLOCK_Spi2, kCLOCK_Spi3, kCLOCK_Spi4, kCLOCK_Spi5, kCLOCK_Spi6, kCLOCK_Spi7, \
110 kCLOCK_Spi14 \
111 }
112 /*! @brief Clock ip name array for FLEXI2S. */
113 #define FLEXI2S_CLOCKS \
114 { \
115 kCLOCK_FlexI2s0, kCLOCK_FlexI2s1, kCLOCK_FlexI2s2, kCLOCK_FlexI2s3, kCLOCK_FlexI2s4, kCLOCK_FlexI2s5, \
116 kCLOCK_FlexI2s6, kCLOCK_FlexI2s7 \
117 }
118 /*! @brief Clock ip name array for UTICK. */
119 #define UTICK_CLOCKS \
120 { \
121 kCLOCK_Utick0 \
122 }
123 /*! @brief Clock ip name array for DMIC. */
124 #define DMIC_CLOCKS \
125 { \
126 kCLOCK_Dmic0 \
127 }
128 /*! @brief Clock ip name array for CT32B. */
129 #define CTIMER_CLOCKS \
130 { \
131 kCLOCK_Ct32b0, kCLOCK_Ct32b1, kCLOCK_Ct32b2, kCLOCK_Ct32b3, kCLOCK_Ct32b4 \
132 }
133
134 /*! @brief Clock ip name array for GPIO. */
135 #define GPIO_CLOCKS \
136 { \
137 kCLOCK_HsGpio0, kCLOCK_HsGpio1, kCLOCK_HsGpio2, kCLOCK_HsGpio3, kCLOCK_HsGpio4, kCLOCK_HsGpio5, \
138 kCLOCK_HsGpio6, kCLOCK_HsGpio7 \
139 }
140 /*! @brief Clock ip name array for ADC. */
141 #define LPADC_CLOCKS \
142 { \
143 kCLOCK_Adc0 \
144 }
145 /*! @brief Clock ip name array for MRT. */
146 #define MRT_CLOCKS \
147 { \
148 kCLOCK_Mrt0 \
149 }
150 /*! @brief Clock ip name array for SCT. */
151 #define SCT_CLOCKS \
152 { \
153 kCLOCK_Sct \
154 }
155 /*! @brief Clock ip name array for RTC. */
156 #define RTC_CLOCKS \
157 { \
158 kCLOCK_Rtc \
159 }
160 /*! @brief Clock ip name array for WWDT. */
161 #define WWDT_CLOCKS \
162 { \
163 kCLOCK_Wwdt0, kCLOCK_Wwdt1 \
164 }
165 /*! @brief Clock ip name array for CRC. */
166 #define CRC_CLOCKS \
167 { \
168 kCLOCK_Crc \
169 }
170 /*! @brief Clock ip name array for USBD. */
171 #define USBD_CLOCKS \
172 { \
173 kCLOCK_UsbhsDevice \
174 }
175 /*! @brief Clock ip name array for DMA. */
176 #define DMA_CLOCKS \
177 { \
178 kCLOCK_Dmac0, kCLOCK_Dmac1 \
179 }
180 /*! @brief Clock ip name array for PINT. */
181 #define PINT_CLOCKS \
182 { \
183 kCLOCK_Pint \
184 }
185 /*! @brief Clock ip name array for FLEXSPI */
186 #define FLEXSPI_CLOCKS \
187 { \
188 kCLOCK_Flexspi \
189 }
190 /*! @brief Clock ip name array for Cache64 */
191 #define CACHE64_CLOCKS \
192 { \
193 kCLOCK_Flexspi \
194 }
195 /*! @brief Clock ip name array for MUA */
196 #define MU_CLOCKS \
197 { \
198 kCLOCK_Mu \
199 }
200 /*! @brief Clock ip name array for SEMA */
201 #define SEMA42_CLOCKS \
202 { \
203 kCLOCK_Sema \
204 }
205 /*! @brief Clock ip name array for RNG */
206 #define TRNG_CLOCKS \
207 { \
208 kCLOCK_Rng \
209 }
210 /*! @brief Clock ip name array for PUF */
211 #define PUF_CLOCKS \
212 { \
213 kCLOCK_Puf \
214 }
215 /*! @brief Clock ip name array for HashCrypt */
216 #define HASHCRYPT_CLOCKS \
217 { \
218 kCLOCK_Hashcrypt \
219 }
220 /*! @brief Clock ip name array for Casper */
221 #define CASPER_CLOCKS \
222 { \
223 kCLOCK_Casper \
224 }
225 /*! @brief Clock ip name array for uSDHC */
226 #define USDHC_CLOCKS \
227 { \
228 kCLOCK_Sdio0, kCLOCK_Sdio1 \
229 }
230 /*! @brief Clock ip name array for OSTimer */
231 #define OSTIMER_CLOCKS \
232 { \
233 kCLOCK_OsEventTimer \
234 }
235 /*! @brief Clock ip name array for Powerquad */
236 #define POWERQUAD_CLOCKS \
237 { \
238 kCLOCK_PowerQuad \
239 }
240
241 /*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
242 /*------------------------------------------------------------------------------
243 clock_ip_name_t definition:
244 ------------------------------------------------------------------------------*/
245
246 #define CLK_GATE_REG_OFFSET_SHIFT 8U
247 #define CLK_GATE_REG_OFFSET_MASK 0xFF00U
248 #define CLK_GATE_BIT_SHIFT_SHIFT 0U
249 #define CLK_GATE_BIT_SHIFT_MASK 0x000000FFU
250
251 #define CLK_GATE_DEFINE(reg_offset, bit_shift) \
252 ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \
253 (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK))
254
255 #define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((uint32_t)(x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT)
256 #define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((uint32_t)(x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT)
257
258 #define CLK_CTL0_PSCCTL0 0
259 #define CLK_CTL0_PSCCTL1 1
260 #define CLK_CTL0_PSCCTL2 2
261 #define CLK_CTL1_PSCCTL0 3
262 #define CLK_CTL1_PSCCTL1 4
263 #define CLK_CTL1_PSCCTL2 5
264
265 /*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
266 typedef enum _clock_ip_name
267 {
268 kCLOCK_IpInvalid = 0U, /*!< Invalid Ip Name. */
269 kCLOCK_RomCtrlr = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 2), /*!< Clock gate name: RomCtrlr*/
270 kCLOCK_PowerQuad = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 8), /*!< Clock gate name: PowerQuad*/
271 kCLOCK_Casper = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 9), /*!< Clock gate name: Casper*/
272 kCLOCK_HashCrypt = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 10), /*!< Clock gate name: HashCrypt*/
273 kCLOCK_Puf = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 11), /*!< Clock gate name: Puf*/
274 kCLOCK_Rng = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 12), /*!< Clock gate name: Rng*/
275 kCLOCK_Flexspi = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 16), /*!< Clock gate name: Flexspi*/
276 kCLOCK_OtpCtrl = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 17), /*!< Clock gate name: OtpCtrl*/
277 kCLOCK_UsbhsPhy = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 20), /*!< Clock gate name: UsbhsPhy*/
278 kCLOCK_UsbhsDevice = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 21), /*!< Clock gate name: UsbhsDevice*/
279 kCLOCK_UsbhsHost = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 22), /*!< Clock gate name: UsbhsHost*/
280 kCLOCK_UsbhsSram = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 23), /*!< Clock gate name: UsbhsSram*/
281 kCLOCK_Sct = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 24), /*!< Clock gate name: Sct*/
282
283 kCLOCK_Sdio0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 2), /*!< Clock gate name: Sdio0*/
284 kCLOCK_Sdio1 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 3), /*!< Clock gate name: Sdio1*/
285 kCLOCK_Acmp0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 15), /*!< Clock gate name: Acmp0*/
286 kCLOCK_Adc0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 16), /*!< Clock gate name: Adc0*/
287 kCLOCK_ShsGpio0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 24), /*!< Clock gate name: ShsGpio0*/
288
289 kCLOCK_Utick0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 0), /*!< Clock gate name: Utick0*/
290 kCLOCK_Wwdt0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 1), /*!< Clock gate name: Wwdt0*/
291
292 kCLOCK_Flexcomm0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 8), /*!< Clock gate name: Flexcomm0*/
293 kCLOCK_Flexcomm1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 9), /*!< Clock gate name: Flexcomm1*/
294 kCLOCK_Flexcomm2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 10), /*!< Clock gate name: Flexcomm2*/
295 kCLOCK_Flexcomm3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 11), /*!< Clock gate name: Flexcomm3*/
296 kCLOCK_Flexcomm4 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 12), /*!< Clock gate name: Flexcomm4*/
297 kCLOCK_Flexcomm5 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 13), /*!< Clock gate name: Flexcomm5*/
298 kCLOCK_Flexcomm6 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 14), /*!< Clock gate name: Flexcomm6*/
299 kCLOCK_Flexcomm7 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 15), /*!< Clock gate name: Flexcomm7*/
300 kCLOCK_Flexcomm14 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 22), /*!< Clock gate name: Flexcomm14*/
301 kCLOCK_Flexcomm15 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 23), /*!< Clock gate name: Flexcomm15*/
302 kCLOCK_Usart0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 8), /*!< Clock gate name: Usart0*/
303 kCLOCK_Usart1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 9), /*!< Clock gate name: Usart1*/
304 kCLOCK_Usart2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 10), /*!< Clock gate name: Usart2*/
305 kCLOCK_Usart3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 11), /*!< Clock gate name: Usart3*/
306 kCLOCK_Usart4 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 12), /*!< Clock gate name: Usart4*/
307 kCLOCK_Usart5 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 13), /*!< Clock gate name: Usart5*/
308 kCLOCK_Usart6 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 14), /*!< Clock gate name: Usart6*/
309 kCLOCK_Usart7 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 15), /*!< Clock gate name: Usart7*/
310 kCLOCK_I2s0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 8), /*!< Clock gate name: I2s0*/
311 kCLOCK_I2s1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 9), /*!< Clock gate name: I2s1*/
312 kCLOCK_I2s2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 10), /*!< Clock gate name: I2s2*/
313 kCLOCK_I2s3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 11), /*!< Clock gate name: I2s3*/
314 kCLOCK_I2s4 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 12), /*!< Clock gate name: I2s4*/
315 kCLOCK_I2s5 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 13), /*!< Clock gate name: I2s5*/
316 kCLOCK_I2s6 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 14), /*!< Clock gate name: I2s6*/
317 kCLOCK_I2s7 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 15), /*!< Clock gate name: I2s7*/
318 kCLOCK_I2c0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 8), /*!< Clock gate name: I2c0*/
319 kCLOCK_I2c1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 9), /*!< Clock gate name: I2c1*/
320 kCLOCK_I2c2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 10), /*!< Clock gate name: I2c2*/
321 kCLOCK_I2c3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 11), /*!< Clock gate name: I2c3*/
322 kCLOCK_I2c4 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 12), /*!< Clock gate name: I2c4*/
323 kCLOCK_I2c5 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 13), /*!< Clock gate name: I2c5*/
324 kCLOCK_I2c6 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 14), /*!< Clock gate name: I2c6*/
325 kCLOCK_I2c7 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 15), /*!< Clock gate name: I2c7*/
326 kCLOCK_I2c15 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 23), /*!< Clock gate name: I2c15*/
327 kCLOCK_Spi0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 8), /*!< Clock gate name: Spi0*/
328 kCLOCK_Spi1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 9), /*!< Clock gate name: Spi1*/
329 kCLOCK_Spi2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 10), /*!< Clock gate name: Spi2*/
330 kCLOCK_Spi3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 11), /*!< Clock gate name: Spi3*/
331 kCLOCK_Spi4 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 12), /*!< Clock gate name: Spi4*/
332 kCLOCK_Spi5 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 13), /*!< Clock gate name: Spi5*/
333 kCLOCK_Spi6 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 14), /*!< Clock gate name: Spi6*/
334 kCLOCK_Spi7 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 15), /*!< Clock gate name: Spi7*/
335 kCLOCK_Spi14 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 22), /*!< Clock gate name: Spi14*/
336 kCLOCK_Dmic0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 24), /*!< Clock gate name: Dmic0*/
337 kCLOCK_OsEventTimer = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 27), /*!< Clock gate name: OsEventTimer*/
338
339 kCLOCK_HsGpio0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 0), /*!< Clock gate name: HsGpio0*/
340 kCLOCK_HsGpio1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 1), /*!< Clock gate name: HsGpio1*/
341 kCLOCK_HsGpio2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 2), /*!< Clock gate name: HsGpio2*/
342 kCLOCK_HsGpio3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 3), /*!< Clock gate name: HsGpio3*/
343 kCLOCK_HsGpio4 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 4), /*!< Clock gate name: HsGpio4*/
344 kCLOCK_HsGpio5 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 5), /*!< Clock gate name: HsGpio5*/
345 kCLOCK_HsGpio6 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 6), /*!< Clock gate name: HsGpio6*/
346 kCLOCK_HsGpio7 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 7), /*!< Clock gate name: HsGpio7*/
347 kCLOCK_Crc = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 16), /*!< Clock gate name: Crc*/
348 kCLOCK_Dmac0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 23), /*!< Clock gate name: Dmac0*/
349 kCLOCK_Dmac1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 24), /*!< Clock gate name: Dmac1*/
350 kCLOCK_Mu = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 28), /*!< Clock gate name: Mu*/
351 kCLOCK_Sema = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 29), /*!< Clock gate name: Sema*/
352 kCLOCK_Freqme = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 31), /*!< Clock gate name: Freqme*/
353
354 kCLOCK_Ct32b0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 0), /*!< Clock gate name: Ct32b0*/
355 kCLOCK_Ct32b1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 1), /*!< Clock gate name: Ct32b1*/
356 kCLOCK_Ct32b2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 2), /*!< Clock gate name: Ct32b2*/
357 kCLOCK_Ct32b3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 3), /*!< Clock gate name: Ct32b3*/
358 kCLOCK_Ct32b4 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 4), /*!< Clock gate name: Ct32b4*/
359 kCLOCK_Rtc = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 7), /*!< Clock gate name: Rtc*/
360 kCLOCK_Mrt0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 8), /*!< Clock gate name: Mrt0*/
361 kCLOCK_Wwdt1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 10), /*!< Clock gate name: Wwdt1*/
362 kCLOCK_I3c0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 16), /*!< Clock gate name: I3c0*/
363 kCLOCK_Pint = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 30), /*!< Clock gate name: Pint*/
364 kCLOCK_InputMux = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 31) /*!< Clock gate name: Input Mux. */
365 } clock_ip_name_t;
366
367 /*! @brief Clock name used to get clock frequency. */
368 typedef enum _clock_name
369 {
370 kCLOCK_CoreSysClk, /*!< Core clock (aka HCLK) */
371 kCLOCK_BusClk, /*!< Bus clock (AHB/APB clock, aka HCLK) */
372 kCLOCK_MclkClk, /*!< MCLK, to MCLK pin */
373 kCLOCK_ClockOutClk, /*!< CLOCKOUT */
374 kCLOCK_AdcClk, /*!< ADC */
375 kCLOCK_FlexspiClk, /*!< FLEXSPI */
376 kCLOCK_SctClk, /*!< SCT */
377 kCLOCK_Wdt0Clk, /*!< Watchdog0 */
378 kCLOCK_Wdt1Clk, /*!< Watchdog1 */
379 kCLOCK_SystickClk, /*!< Systick */
380 kCLOCK_Sdio0Clk, /*!< SDIO0 */
381 kCLOCK_Sdio1Clk, /*!< SDIO1 */
382 kCLOCK_I3cClk, /*!< I3C */
383 kCLOCK_UsbClk, /*!< USB */
384 kCLOCK_DmicClk, /*!< Digital Mic clock */
385 kCLOCK_DspCpuClk, /*!< DSP clock */
386 kCLOCK_AcmpClk, /*!< Acmp clock */
387 kCLOCK_Flexcomm0Clk, /*!< Flexcomm0Clock */
388 kCLOCK_Flexcomm1Clk, /*!< Flexcomm1Clock */
389 kCLOCK_Flexcomm2Clk, /*!< Flexcomm2Clock */
390 kCLOCK_Flexcomm3Clk, /*!< Flexcomm3Clock */
391 kCLOCK_Flexcomm4Clk, /*!< Flexcomm4Clock */
392 kCLOCK_Flexcomm5Clk, /*!< Flexcomm5Clock */
393 kCLOCK_Flexcomm6Clk, /*!< Flexcomm6Clock */
394 kCLOCK_Flexcomm7Clk, /*!< Flexcomm7Clock */
395 kCLOCK_Flexcomm14Clk, /*!< Flexcomm14Clock */
396 kCLOCK_Flexcomm15Clk, /*!< Flexcomm15Clock */
397 } clock_name_t;
398
399 /**
400 * @brief PLL PFD clock name
401 */
402 typedef enum _clock_pfd
403 {
404 kCLOCK_Pfd0 = 0U, /*!< PLL PFD0 */
405 kCLOCK_Pfd1 = 1U, /*!< PLL PFD1 */
406 kCLOCK_Pfd2 = 2U, /*!< PLL PFD2 */
407 kCLOCK_Pfd3 = 3U, /*!< PLL PFD3 */
408 } clock_pfd_t;
409
410 /*! @brief Clock Mux Switches
411 * The encoding is as follows each connection identified is 32bits wide
412 * starting from LSB upwards
413 *
414 * [12 bits for reg offset, 0 means end of descriptor, 4 bits for choice] [bit 31 define CLKCTL0 or CLKCTL1]*
415 *
416 */
417 /* CLKCTL0 SEL */
418 #define SYSPLL0CLKSEL_OFFSET 0x200
419 #define MAINCLKSELA_OFFSET 0x430
420 #define MAINCLKSELB_OFFSET 0x434
421 #define FLEXSPIFCLKSEL_OFFSET 0x620
422 #define SCTFCLKSEL_OFFSET 0x640
423 #define USBHSFCLKSEL_OFFSET 0x660
424 #define SDIO0FCLKSEL_OFFSET 0x680
425 #define SDIO1FCLKSEL_OFFSET 0x690
426 #define ADC0FCLKSEL0_OFFSET 0x6D0
427 #define ADC0FCLKSEL1_OFFSET 0x6D4
428 #define UTICKFCLKSEL_OFFSET 0x700
429 #define WDT0FCLKSEL_OFFSET 0x720
430 #define WAKECLK32KHZSEL_OFFSET 0x730
431 #define SYSTICKFCLKSEL_OFFSET 0x760
432 /* CLKCTL1 SEL */
433 #define AUDIOPLL0CLKSEL_OFFSET 0x200
434 #define DSPCPUCLKSELA_OFFSET 0x430
435 #define DSPCPUCLKSELB_OFFSET 0x434
436 #define OSEVENTFCLKSEL_OFFSET 0x480
437 #define FC0FCLKSEL_OFFSET 0x508
438 #define FC1FCLKSEL_OFFSET 0x528
439 #define FC2FCLKSEL_OFFSET 0x548
440 #define FC3FCLKSEL_OFFSET 0x568
441 #define FC4FCLKSEL_OFFSET 0x588
442 #define FC5FCLKSEL_OFFSET 0x5A8
443 #define FC6FCLKSEL_OFFSET 0x5C8
444 #define FC7FCLKSEL_OFFSET 0x5E8
445 #define FC14FCLKSEL_OFFSET 0x6C8
446 #define FC15FCLKSEL_OFFSET 0x6E8
447 #define DMIC0FCLKSEL_OFFSET 0x700
448 #define CT32BIT0FCLKSEL_OFFSET 0x720
449 #define CT32BIT1FCLKSEL_OFFSET 0x724
450 #define CT32BIT2FCLKSEL_OFFSET 0x728
451 #define CT32BIT3FCLKSEL_OFFSET 0x72C
452 #define CT32BIT4FCLKSEL_OFFSET 0x730
453 #define AUDIOMCLKSEL_OFFSET 0x740
454 #define CLKOUTSEL0_OFFSET 0x760
455 #define CLKOUTSEL1_OFFSET 0x764
456 #define I3C0FCLKSEL_OFFSET 0x780
457 #define I3C0FCLKSTCSEL_OFFSET 0x784
458 #define WDT1FCLKSEL_OFFSET 0x7A0
459 #define ACMP0FCLKSEL_OFFSET 0x7C0
460 /* CLKCTL0 DIV */
461 #define MAINPLLCLKDIV_OFFSET 0x240
462 #define DSPPLLCLKDIV_OFFSET 0x244
463 #define AUX0PLLCLKDIV_OFFSET 0x248
464 #define AUX1PLLCLKDIV_OFFSET 0x24C
465 #define SYSCPUAHBCLKDIV_OFFSET 0x400
466 #define PFC0CLKDIV_OFFSET 0x500
467 #define PFC1CLKDIV_OFFSET 0x504
468 #define FLEXSPIFCLKDIV_OFFSET 0x624
469 #define SCTFCLKDIV_OFFSET 0x644
470 #define USBHSFCLKDIV_OFFSET 0x664
471 #define SDIO0FCLKDIV_OFFSET 0x684
472 #define SDIO1FCLKDIV_OFFSET 0x694
473 #define ADC0FCLKDIV_OFFSET 0x6D8
474 #define WAKECLK32KHZDIV_OFFSET 0x734
475 #define SYSTICKFCLKDIV_OFFSET 0x764
476
477 /* CLKCTL1 DIV */
478 #define AUDIOPLLCLKDIV_OFFSET 0x240
479 #define DSPCPUCLKDIV_OFFSET 0x400
480 #define DSPMAINRAMCLKDIV_OFFSET 0x404
481 #define FRGPLLCLKDIV_OFFSET 0x6FC
482 #define DMIC0FCLKDIV_OFFSET 0x704
483 #define AUDIOMCLKDIV_OFFSET 0x744
484 #define CLKOUTDIV_OFFSET 0x768
485 #define I3C0FCLKSTCDIV_OFFSET 0x788
486 #define I3C0FCLKSDIV_OFFSET 0x78C
487 #define I3C0FCLKDIV_OFFSET 0x790
488 #define ACMP0FCLKDIV_OFFSET 0x7C4
489
490 #define CLKCTL0_TUPLE_MUXA(reg, choice) (((reg)&0xFFFU) | ((choice) << 12U))
491 #define CLKCTL0_TUPLE_MUXB(reg, choice) ((((reg)&0xFFFU) << 16) | ((choice) << 28U))
492 #define CLKCTL1_TUPLE_MUXA(reg, choice) (0x80000000U | (((reg)&0xFFFU) | ((choice) << 12U)))
493 #define CLKCTL1_TUPLE_MUXB(reg, choice) (0x80000000U | ((((reg)&0xFFFU) << 16) | ((choice) << 28U)))
494 #define CLKCTL_TUPLE_REG(base, tuple) ((volatile uint32_t *)(((uint32_t)(base)) + ((uint32_t)(tuple)&0xFFFU)))
495 #define CLKCTL_TUPLE_SEL(tuple) (((uint32_t)(tuple) >> 12U) & 0x7U)
496
497 /*!
498 * @brief The enumerator of clock attach Id.
499 */
500 typedef enum _clock_attach_id
501 {
502 kSFRO_to_SYS_PLL = CLKCTL0_TUPLE_MUXA(SYSPLL0CLKSEL_OFFSET, 0), /*!< Attach SFRO to SYS_PLL. */
503 kXTALIN_CLK_to_SYS_PLL = CLKCTL0_TUPLE_MUXA(SYSPLL0CLKSEL_OFFSET, 1), /*!< Attach XTALIN_CLK to SYS_PLL. */
504 kFFRO_DIV2_to_SYS_PLL = CLKCTL0_TUPLE_MUXA(SYSPLL0CLKSEL_OFFSET, 2), /*!< Attach FFRO_DIV2 to SYS_PLL. */
505 kNONE_to_SYS_PLL = CLKCTL0_TUPLE_MUXA(SYSPLL0CLKSEL_OFFSET, 7), /*!< Attach NONE to SYS_PLL. */
506
507 kSFRO_to_AUDIO_PLL = CLKCTL1_TUPLE_MUXA(AUDIOPLL0CLKSEL_OFFSET, 0), /*!< Attach SFRO to AUDIO_PLL. */
508 kXTALIN_CLK_to_AUDIO_PLL = CLKCTL1_TUPLE_MUXA(AUDIOPLL0CLKSEL_OFFSET, 1), /*!< Attach XTALIN_CLK to AUDIO_PLL. */
509 kFFRO_DIV2_to_AUDIO_PLL = CLKCTL1_TUPLE_MUXA(AUDIOPLL0CLKSEL_OFFSET, 2), /*!< Attach FFRO_DIV2 to AUDIO_PLL. */
510 kNONE_to_AUDIO_PLL = CLKCTL1_TUPLE_MUXA(AUDIOPLL0CLKSEL_OFFSET, 7), /*!< Attach NONE to AUDIO_PLL. */
511
512 kFFRO_DIV4_to_MAIN_CLK = CLKCTL0_TUPLE_MUXA(MAINCLKSELA_OFFSET, 0) |
513 CLKCTL0_TUPLE_MUXB(MAINCLKSELB_OFFSET, 0), /*!< Attach FFRO_DIV4 to MAIN_CLK. */
514 kXTALIN_CLK_to_MAIN_CLK = CLKCTL0_TUPLE_MUXA(MAINCLKSELA_OFFSET, 1) |
515 CLKCTL0_TUPLE_MUXB(MAINCLKSELB_OFFSET, 0), /*!< Attach XTALIN_CLK to MAIN_CLK. */
516 kLPOSC_to_MAIN_CLK = CLKCTL0_TUPLE_MUXA(MAINCLKSELA_OFFSET, 2) |
517 CLKCTL0_TUPLE_MUXB(MAINCLKSELB_OFFSET, 0), /*!< Attach LPOSC to MAIN_CLK. */
518 kFFRO_to_MAIN_CLK = CLKCTL0_TUPLE_MUXA(MAINCLKSELA_OFFSET, 3) |
519 CLKCTL0_TUPLE_MUXB(MAINCLKSELB_OFFSET, 0), /*!< Attach FFRO to MAIN_CLK. */
520 kSFRO_to_MAIN_CLK = CLKCTL0_TUPLE_MUXA(MAINCLKSELB_OFFSET, 1), /*!< Attach SFRO to MAIN_CLK. */
521 kMAIN_PLL_to_MAIN_CLK = CLKCTL0_TUPLE_MUXA(MAINCLKSELB_OFFSET, 2), /*!< Attach MAIN_PLL to MAIN_CLK. */
522 kOSC32K_to_MAIN_CLK = CLKCTL0_TUPLE_MUXA(MAINCLKSELB_OFFSET, 3), /*!< Attach OSC32K to MAIN_CLK. */
523
524 kFFRO_to_DSP_MAIN_CLK = CLKCTL1_TUPLE_MUXA(DSPCPUCLKSELA_OFFSET, 0) |
525 CLKCTL1_TUPLE_MUXB(DSPCPUCLKSELB_OFFSET, 0), /*!< Attach FFRO to DSP_MAIN_CLK. */
526 kXTALIN_CLK_to_DSP_MAIN_CLK =
527 CLKCTL1_TUPLE_MUXA(DSPCPUCLKSELA_OFFSET, 1) |
528 CLKCTL1_TUPLE_MUXB(DSPCPUCLKSELB_OFFSET, 0), /*!< Attach XTALIN_CLK to DSP_MAIN_CLK. */
529 kLPOSC_to_DSP_MAIN_CLK = CLKCTL1_TUPLE_MUXA(DSPCPUCLKSELA_OFFSET, 2) |
530 CLKCTL1_TUPLE_MUXB(DSPCPUCLKSELB_OFFSET, 0), /*!< Attach LPOSC to DSP_MAIN_CLK. */
531 kSFRO_to_DSP_MAIN_CLK = CLKCTL1_TUPLE_MUXA(DSPCPUCLKSELA_OFFSET, 3) |
532 CLKCTL1_TUPLE_MUXB(DSPCPUCLKSELB_OFFSET, 0), /*!< Attach SFRO to DSP_MAIN_CLK. */
533 kMAIN_PLL_to_DSP_MAIN_CLK = CLKCTL1_TUPLE_MUXA(DSPCPUCLKSELB_OFFSET, 1), /*!< Attach MAIN_PLL to DSP_MAIN_CLK. */
534 kDSP_PLL_to_DSP_MAIN_CLK = CLKCTL1_TUPLE_MUXA(DSPCPUCLKSELB_OFFSET, 2), /*!< Attach DSP_PLL to DSP_MAIN_CLK. */
535 kOSC32K_to_DSP_MAIN_CLK = CLKCTL1_TUPLE_MUXA(DSPCPUCLKSELB_OFFSET, 3), /*!< Attach OSC32K to DSP_MAIN_CLK. */
536
537 kSFRO_to_ADC_CLK = CLKCTL0_TUPLE_MUXA(ADC0FCLKSEL0_OFFSET, 0) |
538 CLKCTL0_TUPLE_MUXB(ADC0FCLKSEL1_OFFSET, 0), /*!< Attach SFRO to ADC_CLK. */
539 kXTALIN_CLK_to_ADC_CLK = CLKCTL0_TUPLE_MUXA(ADC0FCLKSEL0_OFFSET, 1) |
540 CLKCTL0_TUPLE_MUXB(ADC0FCLKSEL1_OFFSET, 0), /*!< Attach XTALIN_CLK to ADC_CLK. */
541 kLPOSC_to_ADC_CLK = CLKCTL0_TUPLE_MUXA(ADC0FCLKSEL0_OFFSET, 2) |
542 CLKCTL0_TUPLE_MUXB(ADC0FCLKSEL1_OFFSET, 0), /*!< Attach LPOSC to ADC_CLK. */
543 kFFRO_to_ADC_CLK = CLKCTL0_TUPLE_MUXA(ADC0FCLKSEL0_OFFSET, 3) |
544 CLKCTL0_TUPLE_MUXB(ADC0FCLKSEL1_OFFSET, 0), /*!< Attach FFRO to ADC_CLK. */
545 kMAIN_PLL_to_ADC_CLK = CLKCTL0_TUPLE_MUXA(ADC0FCLKSEL1_OFFSET, 1), /*!< Attach MAIN_PLL to ADC_CLK. */
546 kAUX0_PLL_to_ADC_CLK = CLKCTL0_TUPLE_MUXA(ADC0FCLKSEL1_OFFSET, 3), /*!< Attach AUX0_PLL to ADC_CLK. */
547 kAUX1_PLL_to_ADC_CLK = CLKCTL0_TUPLE_MUXA(ADC0FCLKSEL1_OFFSET, 5), /*!< Attach AUX1_PLL to ADC_CLK. */
548
549 kSFRO_to_CLKOUT = CLKCTL1_TUPLE_MUXA(CLKOUTSEL0_OFFSET, 0) |
550 CLKCTL1_TUPLE_MUXB(CLKOUTSEL1_OFFSET, 0), /*!< Attach SFRO to CLKOUT. */
551 kXTALIN_CLK_to_CLKOUT = CLKCTL1_TUPLE_MUXA(CLKOUTSEL0_OFFSET, 1) |
552 CLKCTL1_TUPLE_MUXB(CLKOUTSEL1_OFFSET, 0), /*!< Attach XTALIN_CLK to CLKOUT. */
553 kLPOSC_to_CLKOUT = CLKCTL1_TUPLE_MUXA(CLKOUTSEL0_OFFSET, 2) |
554 CLKCTL1_TUPLE_MUXB(CLKOUTSEL1_OFFSET, 0), /*!< Attach LPOSC to CLKOUT. */
555 kFFRO_to_CLKOUT = CLKCTL1_TUPLE_MUXA(CLKOUTSEL0_OFFSET, 3) |
556 CLKCTL1_TUPLE_MUXB(CLKOUTSEL1_OFFSET, 0), /*!< Attach FFRO to CLKOUT. */
557 kMAIN_CLK_to_CLKOUT = CLKCTL1_TUPLE_MUXA(CLKOUTSEL0_OFFSET, 4) |
558 CLKCTL1_TUPLE_MUXB(CLKOUTSEL1_OFFSET, 0), /*!< Attach MAIN_CLK to CLKOUT. */
559 kDSP_MAIN_to_CLKOUT = CLKCTL1_TUPLE_MUXA(CLKOUTSEL0_OFFSET, 6) |
560 CLKCTL1_TUPLE_MUXB(CLKOUTSEL1_OFFSET, 0), /*!< Attach DSP_MAIN to CLKOUT. */
561 kMAIN_PLL_to_CLKOUT = CLKCTL1_TUPLE_MUXA(CLKOUTSEL1_OFFSET, 1), /*!< Attach MAIN_PLL to CLKOUT. */
562 kAUX0_PLL_to_CLKOUT = CLKCTL1_TUPLE_MUXA(CLKOUTSEL1_OFFSET, 2), /*!< Attach AUX0_PLL to CLKOUT. */
563 kDSP_PLL_to_CLKOUT = CLKCTL1_TUPLE_MUXA(CLKOUTSEL1_OFFSET, 3), /*!< Attach DSP_PLL to CLKOUT. */
564 kAUX1_PLL_to_CLKOUT = CLKCTL1_TUPLE_MUXA(CLKOUTSEL1_OFFSET, 4), /*!< Attach AUX1_PLL to CLKOUT. */
565 kAUDIO_PLL_to_CLKOUT = CLKCTL1_TUPLE_MUXA(CLKOUTSEL1_OFFSET, 5), /*!< Attach AUDIO_PLL to CLKOUT. */
566 kOSC32K_to_CLKOUT = CLKCTL1_TUPLE_MUXA(CLKOUTSEL1_OFFSET, 6), /*!< Attach OSC32K to CLKOUT. */
567 kNONE_to_CLKOUT = CLKCTL1_TUPLE_MUXA(CLKOUTSEL1_OFFSET, 7), /*!< Attach NONE to CLKOUT. */
568
569 kMAIN_CLK_to_I3C_CLK = CLKCTL1_TUPLE_MUXA(I3C0FCLKSEL_OFFSET, 0), /*!< Attach MAIN_CLK to I3C_CLK. */
570 kFFRO_to_I3C_CLK = CLKCTL1_TUPLE_MUXA(I3C0FCLKSEL_OFFSET, 1), /*!< Attach FFRO to I3C_CLK. */
571 kNONE_to_I3C_CLK = CLKCTL1_TUPLE_MUXA(I3C0FCLKSEL_OFFSET, 7), /*!< Attach NONE to I3C_CLK. */
572
573 kI3C_CLK_to_I3C_TC_CLK = CLKCTL1_TUPLE_MUXA(I3C0FCLKSTCSEL_OFFSET, 0), /*!< Attach I3C_CLK to I3C_TC_CLK. */
574 kLPOSC_to_I3C_TC_CLK = CLKCTL1_TUPLE_MUXA(I3C0FCLKSTCSEL_OFFSET, 1), /*!< Attach LPOSC to I3C_TC_CLK. */
575 kNONE_to_I3C_TC_CLK = CLKCTL1_TUPLE_MUXA(I3C0FCLKSTCSEL_OFFSET, 7), /*!< Attach NONE to I3C_TC_CLK. */
576
577 kLPOSC_to_OSTIMER_CLK = CLKCTL1_TUPLE_MUXA(OSEVENTFCLKSEL_OFFSET, 0), /*!< Attach LPOSC to OSTIMER_CLK. */
578 kOSC32K_to_OSTIMER_CLK = CLKCTL1_TUPLE_MUXA(OSEVENTFCLKSEL_OFFSET, 1), /*!< Attach OSC32K to OSTIMER_CLK. */
579 kHCLK_to_OSTIMER_CLK = CLKCTL1_TUPLE_MUXA(OSEVENTFCLKSEL_OFFSET, 2), /*!< Attach HCLK to OSTIMER_CLK. */
580 kNONE_to_OSTIMER_CLK = CLKCTL1_TUPLE_MUXA(OSEVENTFCLKSEL_OFFSET, 7), /*!< Attach NONE to OSTIMER_CLK. */
581
582 kMAIN_CLK_to_FLEXSPI_CLK = CLKCTL0_TUPLE_MUXA(FLEXSPIFCLKSEL_OFFSET, 0), /*!< Attach MAIN_CLK to FLEXSPI_CLK. */
583 kMAIN_PLL_to_FLEXSPI_CLK = CLKCTL0_TUPLE_MUXA(FLEXSPIFCLKSEL_OFFSET, 1), /*!< Attach MAIN_PLL to FLEXSPI_CLK. */
584 kAUX0_PLL_to_FLEXSPI_CLK = CLKCTL0_TUPLE_MUXA(FLEXSPIFCLKSEL_OFFSET, 2), /*!< Attach AUX0_PLL to FLEXSPI_CLK. */
585 kFFRO_to_FLEXSPI_CLK = CLKCTL0_TUPLE_MUXA(FLEXSPIFCLKSEL_OFFSET, 3), /*!< Attach FFRO to FLEXSPI_CLK. */
586 kAUX1_PLL_to_FLEXSPI_CLK = CLKCTL0_TUPLE_MUXA(FLEXSPIFCLKSEL_OFFSET, 4), /*!< Attach AUX1_PLL to FLEXSPI_CLK. */
587 kNONE_to_FLEXSPI_CLK = CLKCTL0_TUPLE_MUXA(FLEXSPIFCLKSEL_OFFSET, 7), /*!< Attach NONE to FLEXSPI_CLK. */
588
589 kMAIN_CLK_to_SCT_CLK = CLKCTL0_TUPLE_MUXA(SCTFCLKSEL_OFFSET, 0), /*!< Attach MAIN_CLK to SCT_CLK. */
590 kMAIN_PLL_to_SCT_CLK = CLKCTL0_TUPLE_MUXA(SCTFCLKSEL_OFFSET, 1), /*!< Attach MAIN_PLL to SCT_CLK. */
591 kAUX0_PLL_to_SCT_CLK = CLKCTL0_TUPLE_MUXA(SCTFCLKSEL_OFFSET, 2), /*!< Attach AUX0_PLL to SCT_CLK. */
592 kFFRO_to_SCT_CLK = CLKCTL0_TUPLE_MUXA(SCTFCLKSEL_OFFSET, 3), /*!< Attach FFRO to SCT_CLK. */
593 kAUX1_PLL_to_SCT_CLK = CLKCTL0_TUPLE_MUXA(SCTFCLKSEL_OFFSET, 4), /*!< Attach AUX1_PLL to SCT_CLK. */
594 kAUDIO_PLL_to_SCT_CLK = CLKCTL0_TUPLE_MUXA(SCTFCLKSEL_OFFSET, 5), /*!< Attach AUDIO_PLL to SCT_CLK. */
595 kNONE_to_SCT_CLK = CLKCTL0_TUPLE_MUXA(SCTFCLKSEL_OFFSET, 7), /*!< Attach NONE to SCT_CLK. */
596
597 kLPOSC_to_UTICK_CLK = CLKCTL0_TUPLE_MUXA(UTICKFCLKSEL_OFFSET, 0), /*!< Attach LPOSC to UTICK_CLK. */
598 kNONE_to_UTICK_CLK = CLKCTL0_TUPLE_MUXA(UTICKFCLKSEL_OFFSET, 7), /*!< Attach NONE to UTICK_CLK. */
599
600 kLPOSC_to_WDT0_CLK = CLKCTL0_TUPLE_MUXA(WDT0FCLKSEL_OFFSET, 0), /*!< Attach LPOSC to WDT0_CLK. */
601 kNONE_to_WDT0_CLK = CLKCTL0_TUPLE_MUXA(WDT0FCLKSEL_OFFSET, 7), /*!< Attach NONE to WDT0_CLK. */
602
603 kLPOSC_to_WDT1_CLK = CLKCTL1_TUPLE_MUXA(WDT1FCLKSEL_OFFSET, 0), /*!< Attach LPOSC to WDT1_CLK. */
604 kNONE_to_WDT1_CLK = CLKCTL1_TUPLE_MUXA(WDT1FCLKSEL_OFFSET, 7), /*!< Attach NONE to WDT1_CLK. */
605
606 kOSC32K_to_32KHZWAKE_CLK = CLKCTL0_TUPLE_MUXA(WAKECLK32KHZSEL_OFFSET, 0), /*!< Attach OSC32K to 32KHZWAKE_CLK. */
607 kLPOSC_DIV32_to_32KHZWAKE_CLK = CLKCTL0_TUPLE_MUXA(WAKECLK32KHZSEL_OFFSET, 1), /*!< Attach LPOSC_DIV32
608 to 32KHZWAKE_CLK. */
609 kNONE_to_32KHZWAKE_CLK = CLKCTL0_TUPLE_MUXA(WAKECLK32KHZSEL_OFFSET, 7), /*!< Attach NONE to 32KHZWAKE_CLK. */
610
611 kMAIN_CLK_DIV_to_SYSTICK_CLK = CLKCTL0_TUPLE_MUXA(SYSTICKFCLKSEL_OFFSET, 0), /*!< Attach MAIN_CLK_DIV
612 to SYSTICK_CLK. */
613 kLPOSC_to_SYSTICK_CLK = CLKCTL0_TUPLE_MUXA(SYSTICKFCLKSEL_OFFSET, 1), /*!< Attach LPOSC to SYSTICK_CLK. */
614 kOSC32K_to_SYSTICK_CLK = CLKCTL0_TUPLE_MUXA(SYSTICKFCLKSEL_OFFSET, 2), /*!< Attach OSC32K to SYSTICK_CLK. */
615 kSFRO_to_SYSTICK_CLK = CLKCTL0_TUPLE_MUXA(SYSTICKFCLKSEL_OFFSET, 3), /*!< Attach SFRO to SYSTICK_CLK. */
616 kNONE_to_SYSTICK_CLK = CLKCTL0_TUPLE_MUXA(SYSTICKFCLKSEL_OFFSET, 7), /*!< Attach NONE to SYSTICK_CLK. */
617
618 kMAIN_CLK_to_SDIO0_CLK = CLKCTL0_TUPLE_MUXA(SDIO0FCLKSEL_OFFSET, 0), /*!< Attach MAIN_CLK to SDIO0_CLK. */
619 kMAIN_PLL_to_SDIO0_CLK = CLKCTL0_TUPLE_MUXA(SDIO0FCLKSEL_OFFSET, 1), /*!< Attach MAIN_PLL to SDIO0_CLK. */
620 kAUX0_PLL_to_SDIO0_CLK = CLKCTL0_TUPLE_MUXA(SDIO0FCLKSEL_OFFSET, 2), /*!< Attach AUX0_PLL to SDIO0_CLK. */
621 kFFRO_to_SDIO0_CLK = CLKCTL0_TUPLE_MUXA(SDIO0FCLKSEL_OFFSET, 3), /*!< Attach FFRO to SDIO0_CLK. */
622 kAUX1_PLL_to_SDIO0_CLK = CLKCTL0_TUPLE_MUXA(SDIO0FCLKSEL_OFFSET, 4), /*!< Attach AUX1_PLL to SDIO0_CLK. */
623 kNONE_to_SDIO0_CLK = CLKCTL0_TUPLE_MUXA(SDIO0FCLKSEL_OFFSET, 7), /*!< Attach NONE to SDIO0_CLK. */
624
625 kMAIN_CLK_to_SDIO1_CLK = CLKCTL0_TUPLE_MUXA(SDIO1FCLKSEL_OFFSET, 0), /*!< Attach MAIN_CLK to SDIO1_CLK. */
626 kMAIN_PLL_to_SDIO1_CLK = CLKCTL0_TUPLE_MUXA(SDIO1FCLKSEL_OFFSET, 1), /*!< Attach MAIN_PLL to SDIO1_CLK. */
627 kAUX0_PLL_to_SDIO1_CLK = CLKCTL0_TUPLE_MUXA(SDIO1FCLKSEL_OFFSET, 2), /*!< Attach AUX0_PLL to SDIO1_CLK. */
628 kFFRO_to_SDIO1_CLK = CLKCTL0_TUPLE_MUXA(SDIO1FCLKSEL_OFFSET, 3), /*!< Attach FFRO to SDIO1_CLK. */
629 kAUX1_PLL_to_SDIO1_CLK = CLKCTL0_TUPLE_MUXA(SDIO1FCLKSEL_OFFSET, 4), /*!< Attach AUX1_PLL to SDIO1_CLK. */
630 kNONE_to_SDIO1_CLK = CLKCTL0_TUPLE_MUXA(SDIO1FCLKSEL_OFFSET, 7), /*!< Attach NONE to SDIO1_CLK. */
631
632 kXTALIN_CLK_to_USB_CLK = CLKCTL0_TUPLE_MUXA(USBHSFCLKSEL_OFFSET, 0), /*!< Attach XTALIN_CLK to USB_CLK. */
633 kMAIN_CLK_to_USB_CLK = CLKCTL0_TUPLE_MUXA(USBHSFCLKSEL_OFFSET, 1), /*!< Attach MAIN_CLK to USB_CLK. */
634 kNONE_to_USB_CLK = CLKCTL0_TUPLE_MUXA(USBHSFCLKSEL_OFFSET, 7), /*!< Attach NONE to USB_CLK. */
635
636 kFFRO_to_MCLK_CLK = CLKCTL1_TUPLE_MUXA(AUDIOMCLKSEL_OFFSET, 0), /*!< Attach FFRO to MCLK_CLK. */
637 kAUDIO_PLL_to_MCLK_CLK = CLKCTL1_TUPLE_MUXA(AUDIOMCLKSEL_OFFSET, 1), /*!< Attach AUDIO_PLL to MCLK_CLK. */
638 kNONE_to_MCLK_CLK = CLKCTL1_TUPLE_MUXA(AUDIOMCLKSEL_OFFSET, 7), /*!< Attach NONE to MCLK_CLK. */
639
640 kSFRO_to_DMIC_CLK = CLKCTL1_TUPLE_MUXA(DMIC0FCLKSEL_OFFSET, 0), /*!< Attach SFRO to DMIC_CLK. */
641 kFFRO_to_DMIC_CLK = CLKCTL1_TUPLE_MUXA(DMIC0FCLKSEL_OFFSET, 1), /*!< Attach FFRO to DMIC_CLK. */
642 kAUDIO_PLL_to_DMIC_CLK = CLKCTL1_TUPLE_MUXA(DMIC0FCLKSEL_OFFSET, 2), /*!< Attach AUDIO_PLL to DMIC_CLK. */
643 kMASTER_CLK_to_DMIC_CLK = CLKCTL1_TUPLE_MUXA(DMIC0FCLKSEL_OFFSET, 3), /*!< Attach MASTER_CLK to DMIC_CLK. */
644 kLPOSC_to_DMIC_CLK = CLKCTL1_TUPLE_MUXA(DMIC0FCLKSEL_OFFSET, 4), /*!< Attach LPOSC to DMIC_CLK. */
645 k32K_WAKE_CLK_to_DMIC_CLK = CLKCTL1_TUPLE_MUXA(DMIC0FCLKSEL_OFFSET, 5), /*!< Attach 32K_WAKE_CLK to DMIC_CLK. */
646 kNONE_to_DMIC_CLK = CLKCTL1_TUPLE_MUXA(DMIC0FCLKSEL_OFFSET, 7), /*!< Attach NONE to DMIC_CLK. */
647
648 kMAIN_CLK_to_ACMP_CLK = CLKCTL1_TUPLE_MUXA(ACMP0FCLKSEL_OFFSET, 0), /*!< Attach MAIN_CLK to ACMP_CLK. */
649 kSFRO_to_ACMP_CLK = CLKCTL1_TUPLE_MUXA(ACMP0FCLKSEL_OFFSET, 1), /*!< Attach SFRO to ACMP_CLK. */
650 kFFRO_to_ACMP_CLK = CLKCTL1_TUPLE_MUXA(ACMP0FCLKSEL_OFFSET, 2), /*!< Attach FFRO to ACMP_CLK. */
651 kAUX0_PLL_to_ACMP_CLK = CLKCTL1_TUPLE_MUXA(ACMP0FCLKSEL_OFFSET, 3), /*!< Attach AUX0_PLL to ACMP_CLK. */
652 kAUX1_PLL_to_ACMP_CLK = CLKCTL1_TUPLE_MUXA(ACMP0FCLKSEL_OFFSET, 4), /*!< Attach AUX1_PLL to ACMP_CLK. */
653 kNONE_to_ACMP_CLK = CLKCTL1_TUPLE_MUXA(ACMP0FCLKSEL_OFFSET, 7), /*!< Attach NONE to ACMP_CLK. */
654
655 kSFRO_to_FLEXCOMM0 = CLKCTL1_TUPLE_MUXA(FC0FCLKSEL_OFFSET, 0), /*!< Attach SFRO to FLEXCOMM0. */
656 kFFRO_to_FLEXCOMM0 = CLKCTL1_TUPLE_MUXA(FC0FCLKSEL_OFFSET, 1), /*!< Attach FFRO to FLEXCOMM0. */
657 kAUDIO_PLL_to_FLEXCOMM0 = CLKCTL1_TUPLE_MUXA(FC0FCLKSEL_OFFSET, 2), /*!< Attach AUDIO_PLL to FLEXCOMM0. */
658 kMASTER_CLK_to_FLEXCOMM0 = CLKCTL1_TUPLE_MUXA(FC0FCLKSEL_OFFSET, 3), /*!< Attach MASTER_CLK to FLEXCOMM0. */
659 kFRG_to_FLEXCOMM0 = CLKCTL1_TUPLE_MUXA(FC0FCLKSEL_OFFSET, 4), /*!< Attach FRG to FLEXCOMM0. */
660 kNONE_to_FLEXCOMM0 = CLKCTL1_TUPLE_MUXA(FC0FCLKSEL_OFFSET, 7), /*!< Attach NONE to FLEXCOMM0. */
661
662 kSFRO_to_FLEXCOMM1 = CLKCTL1_TUPLE_MUXA(FC1FCLKSEL_OFFSET, 0), /*!< Attach SFRO to FLEXCOMM1. */
663 kFFRO_to_FLEXCOMM1 = CLKCTL1_TUPLE_MUXA(FC1FCLKSEL_OFFSET, 1), /*!< Attach FFRO to FLEXCOMM1. */
664 kAUDIO_PLL_to_FLEXCOMM1 = CLKCTL1_TUPLE_MUXA(FC1FCLKSEL_OFFSET, 2), /*!< Attach AUDIO_PLL to FLEXCOMM1. */
665 kMASTER_CLK_to_FLEXCOMM1 = CLKCTL1_TUPLE_MUXA(FC1FCLKSEL_OFFSET, 3), /*!< Attach MASTER_CLK to FLEXCOMM1. */
666 kFRG_to_FLEXCOMM1 = CLKCTL1_TUPLE_MUXA(FC1FCLKSEL_OFFSET, 4), /*!< Attach FRG to FLEXCOMM1. */
667 kNONE_to_FLEXCOMM1 = CLKCTL1_TUPLE_MUXA(FC1FCLKSEL_OFFSET, 7), /*!< Attach NONE to FLEXCOMM1. */
668
669 kSFRO_to_FLEXCOMM2 = CLKCTL1_TUPLE_MUXA(FC2FCLKSEL_OFFSET, 0), /*!< Attach SFRO to FLEXCOMM2. */
670 kFFRO_to_FLEXCOMM2 = CLKCTL1_TUPLE_MUXA(FC2FCLKSEL_OFFSET, 1), /*!< Attach FFRO to FLEXCOMM2. */
671 kAUDIO_PLL_to_FLEXCOMM2 = CLKCTL1_TUPLE_MUXA(FC2FCLKSEL_OFFSET, 2), /*!< Attach AUDIO_PLL to FLEXCOMM2. */
672 kMASTER_CLK_to_FLEXCOMM2 = CLKCTL1_TUPLE_MUXA(FC2FCLKSEL_OFFSET, 3), /*!< Attach MASTER_CLK to FLEXCOMM2. */
673 kFRG_to_FLEXCOMM2 = CLKCTL1_TUPLE_MUXA(FC2FCLKSEL_OFFSET, 4), /*!< Attach FRG to FLEXCOMM2. */
674 kNONE_to_FLEXCOMM2 = CLKCTL1_TUPLE_MUXA(FC2FCLKSEL_OFFSET, 7), /*!< Attach NONE to FLEXCOMM2. */
675
676 kSFRO_to_FLEXCOMM3 = CLKCTL1_TUPLE_MUXA(FC3FCLKSEL_OFFSET, 0), /*!< Attach SFRO to FLEXCOMM3. */
677 kFFRO_to_FLEXCOMM3 = CLKCTL1_TUPLE_MUXA(FC3FCLKSEL_OFFSET, 1), /*!< Attach FFRO to FLEXCOMM3. */
678 kAUDIO_PLL_to_FLEXCOMM3 = CLKCTL1_TUPLE_MUXA(FC3FCLKSEL_OFFSET, 2), /*!< Attach AUDIO_PLL to FLEXCOMM3. */
679 kMASTER_CLK_to_FLEXCOMM3 = CLKCTL1_TUPLE_MUXA(FC3FCLKSEL_OFFSET, 3), /*!< Attach MASTER_CLK to FLEXCOMM3. */
680 kFRG_to_FLEXCOMM3 = CLKCTL1_TUPLE_MUXA(FC3FCLKSEL_OFFSET, 4), /*!< Attach FRG to FLEXCOMM3. */
681 kNONE_to_FLEXCOMM3 = CLKCTL1_TUPLE_MUXA(FC3FCLKSEL_OFFSET, 7), /*!< Attach NONE to FLEXCOMM3. */
682
683 kSFRO_to_FLEXCOMM4 = CLKCTL1_TUPLE_MUXA(FC4FCLKSEL_OFFSET, 0), /*!< Attach SFRO to FLEXCOMM4. */
684 kFFRO_to_FLEXCOMM4 = CLKCTL1_TUPLE_MUXA(FC4FCLKSEL_OFFSET, 1), /*!< Attach FFRO to FLEXCOMM4. */
685 kAUDIO_PLL_to_FLEXCOMM4 = CLKCTL1_TUPLE_MUXA(FC4FCLKSEL_OFFSET, 2), /*!< Attach AUDIO_PLL to FLEXCOMM4. */
686 kMASTER_CLK_to_FLEXCOMM4 = CLKCTL1_TUPLE_MUXA(FC4FCLKSEL_OFFSET, 3), /*!< Attach MASTER_CLK to FLEXCOMM4. */
687 kFRG_to_FLEXCOMM4 = CLKCTL1_TUPLE_MUXA(FC4FCLKSEL_OFFSET, 4), /*!< Attach FRG to FLEXCOMM4. */
688 kNONE_to_FLEXCOMM4 = CLKCTL1_TUPLE_MUXA(FC4FCLKSEL_OFFSET, 7), /*!< Attach NONE to FLEXCOMM4. */
689
690 kSFRO_to_FLEXCOMM5 = CLKCTL1_TUPLE_MUXA(FC5FCLKSEL_OFFSET, 0), /*!< Attach SFRO to FLEXCOMM5. */
691 kFFRO_to_FLEXCOMM5 = CLKCTL1_TUPLE_MUXA(FC5FCLKSEL_OFFSET, 1), /*!< Attach FFRO to FLEXCOMM5. */
692 kAUDIO_PLL_to_FLEXCOMM5 = CLKCTL1_TUPLE_MUXA(FC5FCLKSEL_OFFSET, 2), /*!< Attach AUDIO_PLL to FLEXCOMM5. */
693 kMASTER_CLK_to_FLEXCOMM5 = CLKCTL1_TUPLE_MUXA(FC5FCLKSEL_OFFSET, 3), /*!< Attach MASTER_CLK to FLEXCOMM5. */
694 kFRG_to_FLEXCOMM5 = CLKCTL1_TUPLE_MUXA(FC5FCLKSEL_OFFSET, 4), /*!< Attach FRG to FLEXCOMM5. */
695 kNONE_to_FLEXCOMM5 = CLKCTL1_TUPLE_MUXA(FC5FCLKSEL_OFFSET, 7), /*!< Attach NONE to FLEXCOMM5. */
696
697 kSFRO_to_FLEXCOMM6 = CLKCTL1_TUPLE_MUXA(FC6FCLKSEL_OFFSET, 0), /*!< Attach SFRO to FLEXCOMM6. */
698 kFFRO_to_FLEXCOMM6 = CLKCTL1_TUPLE_MUXA(FC6FCLKSEL_OFFSET, 1), /*!< Attach FFRO to FLEXCOMM6. */
699 kAUDIO_PLL_to_FLEXCOMM6 = CLKCTL1_TUPLE_MUXA(FC6FCLKSEL_OFFSET, 2), /*!< Attach AUDIO_PLL to FLEXCOMM6. */
700 kMASTER_CLK_to_FLEXCOMM6 = CLKCTL1_TUPLE_MUXA(FC6FCLKSEL_OFFSET, 3), /*!< Attach MASTER_CLK to FLEXCOMM6. */
701 kFRG_to_FLEXCOMM6 = CLKCTL1_TUPLE_MUXA(FC6FCLKSEL_OFFSET, 4), /*!< Attach FRG to FLEXCOMM6. */
702 kNONE_to_FLEXCOMM6 = CLKCTL1_TUPLE_MUXA(FC6FCLKSEL_OFFSET, 7), /*!< Attach NONE to FLEXCOMM6. */
703
704 kSFRO_to_FLEXCOMM7 = CLKCTL1_TUPLE_MUXA(FC7FCLKSEL_OFFSET, 0), /*!< Attach SFRO to FLEXCOMM7. */
705 kFFRO_to_FLEXCOMM7 = CLKCTL1_TUPLE_MUXA(FC7FCLKSEL_OFFSET, 1), /*!< Attach FFRO to FLEXCOMM7. */
706 kAUDIO_PLL_to_FLEXCOMM7 = CLKCTL1_TUPLE_MUXA(FC7FCLKSEL_OFFSET, 2), /*!< Attach AUDIO_PLL to FLEXCOMM7. */
707 kMASTER_CLK_to_FLEXCOMM7 = CLKCTL1_TUPLE_MUXA(FC7FCLKSEL_OFFSET, 3), /*!< Attach MASTER_CLK to FLEXCOMM7. */
708 kFRG_to_FLEXCOMM7 = CLKCTL1_TUPLE_MUXA(FC7FCLKSEL_OFFSET, 4), /*!< Attach FRG to FLEXCOMM7. */
709 kNONE_to_FLEXCOMM7 = CLKCTL1_TUPLE_MUXA(FC7FCLKSEL_OFFSET, 7), /*!< Attach NONE to FLEXCOMM7. */
710
711 kSFRO_to_FLEXCOMM14 = CLKCTL1_TUPLE_MUXA(FC14FCLKSEL_OFFSET, 0), /*!< Attach SFRO to FLEXCOMM14. */
712 kFFRO_to_FLEXCOMM14 = CLKCTL1_TUPLE_MUXA(FC14FCLKSEL_OFFSET, 1), /*!< Attach FFRO to FLEXCOMM14. */
713 kAUDIO_PLL_to_FLEXCOMM14 = CLKCTL1_TUPLE_MUXA(FC14FCLKSEL_OFFSET, 2), /*!< Attach AUDIO_PLL to FLEXCOMM14. */
714 kMASTER_CLK_to_FLEXCOMM14 = CLKCTL1_TUPLE_MUXA(FC14FCLKSEL_OFFSET, 3), /*!< Attach MASTER_CLK to FLEXCOMM14. */
715 kFRG_to_FLEXCOMM14 = CLKCTL1_TUPLE_MUXA(FC14FCLKSEL_OFFSET, 4), /*!< Attach FRG to FLEXCOMM14. */
716 kNONE_to_FLEXCOMM14 = CLKCTL1_TUPLE_MUXA(FC14FCLKSEL_OFFSET, 7), /*!< Attach NONE to FLEXCOMM14. */
717
718 kSFRO_to_FLEXCOMM15 = CLKCTL1_TUPLE_MUXA(FC15FCLKSEL_OFFSET, 0), /*!< Attach SFRO to FLEXCOMM15. */
719 kFFRO_to_FLEXCOMM15 = CLKCTL1_TUPLE_MUXA(FC15FCLKSEL_OFFSET, 1), /*!< Attach FFRO to FLEXCOMM15. */
720 kAUDIO_PLL_to_FLEXCOMM15 = CLKCTL1_TUPLE_MUXA(FC15FCLKSEL_OFFSET, 2), /*!< Attach AUDIO_PLL to FLEXCOMM15. */
721 kMASTER_CLK_to_FLEXCOMM15 = CLKCTL1_TUPLE_MUXA(FC15FCLKSEL_OFFSET, 3), /*!< Attach MASTER_CLK to FLEXCOMM15. */
722 kFRG_to_FLEXCOMM15 = CLKCTL1_TUPLE_MUXA(FC15FCLKSEL_OFFSET, 4), /*!< Attach FRG to FLEXCOMM15. */
723 kNONE_to_FLEXCOMM15 = CLKCTL1_TUPLE_MUXA(FC15FCLKSEL_OFFSET, 7), /*!< Attach NONE to FLEXCOMM15. */
724
725 kMAIN_CLK_to_CTIMER0 = CLKCTL1_TUPLE_MUXA(CT32BIT0FCLKSEL_OFFSET, 0), /*!< Attach MAIN_CLK to CTIMER0. */
726 kSFRO_to_CTIMER0 = CLKCTL1_TUPLE_MUXA(CT32BIT0FCLKSEL_OFFSET, 1), /*!< Attach SFRO to CTIMER0. */
727 kFFRO_to_CTIMER0 = CLKCTL1_TUPLE_MUXA(CT32BIT0FCLKSEL_OFFSET, 2), /*!< Attach FFRO to CTIMER0. */
728 kAUDIO_PLL_to_CTIMER0 = CLKCTL1_TUPLE_MUXA(CT32BIT0FCLKSEL_OFFSET, 3), /*!< Attach AUDIO_PLL to CTIMER0. */
729 kMASTER_CLK_to_CTIMER0 = CLKCTL1_TUPLE_MUXA(CT32BIT0FCLKSEL_OFFSET, 4), /*!< Attach MASTER_CLK to CTIMER0. */
730 kLPOSC_to_CTIMER0 = CLKCTL1_TUPLE_MUXA(CT32BIT0FCLKSEL_OFFSET, 5), /*!< Attach LPOSC to CTIMER0. */
731 kNONE_to_CTIMER0 = CLKCTL1_TUPLE_MUXA(CT32BIT0FCLKSEL_OFFSET, 7), /*!< Attach NONE to CTIMER0. */
732
733 kMAIN_CLK_to_CTIMER1 = CLKCTL1_TUPLE_MUXA(CT32BIT1FCLKSEL_OFFSET, 0), /*!< Attach MAIN_CLK to CTIMER1. */
734 kSFRO_to_CTIMER1 = CLKCTL1_TUPLE_MUXA(CT32BIT1FCLKSEL_OFFSET, 1), /*!< Attach SFRO to CTIMER1. */
735 kFFRO_to_CTIMER1 = CLKCTL1_TUPLE_MUXA(CT32BIT1FCLKSEL_OFFSET, 2), /*!< Attach FFRO to CTIMER1. */
736 kAUDIO_PLL_to_CTIMER1 = CLKCTL1_TUPLE_MUXA(CT32BIT1FCLKSEL_OFFSET, 3), /*!< Attach AUDIO_PLL to CTIMER1. */
737 kMASTER_CLK_to_CTIMER1 = CLKCTL1_TUPLE_MUXA(CT32BIT1FCLKSEL_OFFSET, 4), /*!< Attach MASTER_CLK to CTIMER1. */
738 kLPOSC_to_CTIMER1 = CLKCTL1_TUPLE_MUXA(CT32BIT1FCLKSEL_OFFSET, 5), /*!< Attach LPOSC to CTIMER1. */
739 kNONE_to_CTIMER1 = CLKCTL1_TUPLE_MUXA(CT32BIT1FCLKSEL_OFFSET, 7), /*!< Attach NONE to CTIMER1. */
740
741 kMAIN_CLK_to_CTIMER2 = CLKCTL1_TUPLE_MUXA(CT32BIT2FCLKSEL_OFFSET, 0), /*!< Attach MAIN_CLK to CTIMER2. */
742 kSFRO_to_CTIMER2 = CLKCTL1_TUPLE_MUXA(CT32BIT2FCLKSEL_OFFSET, 1), /*!< Attach SFRO to CTIMER2. */
743 kFFRO_to_CTIMER2 = CLKCTL1_TUPLE_MUXA(CT32BIT2FCLKSEL_OFFSET, 2), /*!< Attach FFRO to CTIMER2. */
744 kAUDIO_PLL_to_CTIMER2 = CLKCTL1_TUPLE_MUXA(CT32BIT2FCLKSEL_OFFSET, 3), /*!< Attach AUDIO_PLL to CTIMER2. */
745 kMASTER_CLK_to_CTIMER2 = CLKCTL1_TUPLE_MUXA(CT32BIT2FCLKSEL_OFFSET, 4), /*!< Attach MASTER_CLK to CTIMER2. */
746 kLPOSC_to_CTIMER2 = CLKCTL1_TUPLE_MUXA(CT32BIT2FCLKSEL_OFFSET, 5), /*!< Attach LPOSC to CTIMER2. */
747 kNONE_to_CTIMER2 = CLKCTL1_TUPLE_MUXA(CT32BIT2FCLKSEL_OFFSET, 7), /*!< Attach NONE to CTIMER2. */
748
749 kMAIN_CLK_to_CTIMER3 = CLKCTL1_TUPLE_MUXA(CT32BIT3FCLKSEL_OFFSET, 0), /*!< Attach MAIN_CLK to CTIMER3. */
750 kSFRO_to_CTIMER3 = CLKCTL1_TUPLE_MUXA(CT32BIT3FCLKSEL_OFFSET, 1), /*!< Attach SFRO to CTIMER3. */
751 kFFRO_to_CTIMER3 = CLKCTL1_TUPLE_MUXA(CT32BIT3FCLKSEL_OFFSET, 2), /*!< Attach FFRO to CTIMER3. */
752 kAUDIO_PLL_to_CTIMER3 = CLKCTL1_TUPLE_MUXA(CT32BIT3FCLKSEL_OFFSET, 3), /*!< Attach AUDIO_PLL to CTIMER3. */
753 kMASTER_CLK_to_CTIMER3 = CLKCTL1_TUPLE_MUXA(CT32BIT3FCLKSEL_OFFSET, 4), /*!< Attach MASTER_CLK to CTIMER3. */
754 kLPOSC_to_CTIMER3 = CLKCTL1_TUPLE_MUXA(CT32BIT3FCLKSEL_OFFSET, 5), /*!< Attach LPOSC to CTIMER3. */
755 kNONE_to_CTIMER3 = CLKCTL1_TUPLE_MUXA(CT32BIT3FCLKSEL_OFFSET, 7), /*!< Attach NONE to CTIMER3. */
756
757 kMAIN_CLK_to_CTIMER4 = CLKCTL1_TUPLE_MUXA(CT32BIT4FCLKSEL_OFFSET, 0), /*!< Attach MAIN_CLK to CTIMER4. */
758 kSFRO_to_CTIMER4 = CLKCTL1_TUPLE_MUXA(CT32BIT4FCLKSEL_OFFSET, 1), /*!< Attach SFRO to CTIMER4. */
759 kFFRO_to_CTIMER4 = CLKCTL1_TUPLE_MUXA(CT32BIT4FCLKSEL_OFFSET, 2), /*!< Attach FFRO to CTIMER4. */
760 kAUDIO_PLL_to_CTIMER4 = CLKCTL1_TUPLE_MUXA(CT32BIT4FCLKSEL_OFFSET, 3), /*!< Attach AUDIO_PLL to CTIMER4. */
761 kMASTER_CLK_to_CTIMER4 = CLKCTL1_TUPLE_MUXA(CT32BIT4FCLKSEL_OFFSET, 4), /*!< Attach MASTER_CLK to CTIMER4. */
762 kLPOSC_to_CTIMER4 = CLKCTL1_TUPLE_MUXA(CT32BIT4FCLKSEL_OFFSET, 5), /*!< Attach LPOSC to CTIMER4. */
763 kNONE_to_CTIMER4 = CLKCTL1_TUPLE_MUXA(CT32BIT4FCLKSEL_OFFSET, 7), /*!< Attach NONE to CTIMER4. */
764
765 } clock_attach_id_t;
766
767 /*! @brief Clock dividers */
768 typedef enum _clock_div_name
769 {
770 kCLOCK_DivSysCpuAhbClk = CLKCTL0_TUPLE_MUXA(SYSCPUAHBCLKDIV_OFFSET, 0), /*!< Sys Cpu Ahb Clk Divider. */
771 kCLOCK_DivMainPllClk = CLKCTL0_TUPLE_MUXA(MAINPLLCLKDIV_OFFSET, 0), /*!< Main Pll Clk Divider. */
772 kCLOCK_DivDspPllClk = CLKCTL0_TUPLE_MUXA(DSPPLLCLKDIV_OFFSET, 0), /*!< Dsp Pll Clk Divider. */
773 kCLOCK_DivAux0PllClk = CLKCTL0_TUPLE_MUXA(AUX0PLLCLKDIV_OFFSET, 0), /*!< Aux0 Pll Clk Divider. */
774 kCLOCK_DivAux1PllClk = CLKCTL0_TUPLE_MUXA(AUX1PLLCLKDIV_OFFSET, 0), /*!< Aux1 Pll Clk Divider. */
775 kCLOCK_DivPfc0Clk = CLKCTL0_TUPLE_MUXA(PFC0CLKDIV_OFFSET, 0), /*!< Pfc0 Clk Divider. */
776 kCLOCK_DivPfc1Clk = CLKCTL0_TUPLE_MUXA(PFC1CLKDIV_OFFSET, 0), /*!< Pfc1 Clk Divider. */
777 kCLOCK_DivAdcClk = CLKCTL0_TUPLE_MUXA(ADC0FCLKDIV_OFFSET, 0), /*!< Adc Clk Divider. */
778 kCLOCK_DivFlexspiClk = CLKCTL0_TUPLE_MUXA(FLEXSPIFCLKDIV_OFFSET, 0), /*!< Flexspi Clk Divider. */
779 kCLOCK_DivSctClk = CLKCTL0_TUPLE_MUXA(SCTFCLKDIV_OFFSET, 0), /*!< Sct Clk Divider. */
780 kCLOCK_DivSdio0Clk = CLKCTL0_TUPLE_MUXA(SDIO0FCLKDIV_OFFSET, 0), /*!< Sdio0 Clk Divider. */
781 kCLOCK_DivSdio1Clk = CLKCTL0_TUPLE_MUXA(SDIO1FCLKDIV_OFFSET, 0), /*!< Sdio1 Clk Divider. */
782 kCLOCK_DivSystickClk = CLKCTL0_TUPLE_MUXA(SYSTICKFCLKDIV_OFFSET, 0), /*!< Systick Clk Divider. */
783 kCLOCK_DivUsbHsFclk = CLKCTL0_TUPLE_MUXA(USBHSFCLKDIV_OFFSET, 0), /*!< Usb Hs Fclk Divider. */
784 kCLOCK_DivAudioPllClk = CLKCTL1_TUPLE_MUXA(AUDIOPLLCLKDIV_OFFSET, 0), /*!< Audio Pll Clk Divider. */
785 kCLOCK_DivAcmpClk = CLKCTL1_TUPLE_MUXA(ACMP0FCLKDIV_OFFSET, 0), /*!< Acmp Clk Divider. */
786 kCLOCK_DivClockOut = CLKCTL1_TUPLE_MUXA(CLKOUTDIV_OFFSET, 0), /*!< Clock Out Divider. */
787 kCLOCK_DivDmicClk = CLKCTL1_TUPLE_MUXA(DMIC0FCLKDIV_OFFSET, 0), /*!< Dmic Clk Divider. */
788 kCLOCK_DivDspCpuClk = CLKCTL1_TUPLE_MUXA(DSPCPUCLKDIV_OFFSET, 0), /*!< Dsp Cpu Clk Divider. */
789 kCLOCK_DivDspRamClk = CLKCTL1_TUPLE_MUXA(DSPMAINRAMCLKDIV_OFFSET, 0), /*!< Dsp Ram Clk Divider. */
790 kCLOCK_DivMclkClk = CLKCTL1_TUPLE_MUXA(AUDIOMCLKDIV_OFFSET, 0), /*!< Mclk Clk Divider. */
791 kCLOCK_DivPllFrgClk = CLKCTL1_TUPLE_MUXA(FRGPLLCLKDIV_OFFSET, 0), /*!< Pll Frg Clk Divider. */
792 kCLOCK_DivI3cClk = CLKCTL1_TUPLE_MUXA(I3C0FCLKDIV_OFFSET, 0), /*!< I3c Clk Divider. */
793 kCLOCK_DivI3cTcClk = CLKCTL1_TUPLE_MUXA(I3C0FCLKSTCDIV_OFFSET, 0), /*!< I3c Tc Clk Divider. */
794 kCLOCK_DivI3cSlowClk = CLKCTL1_TUPLE_MUXA(I3C0FCLKSDIV_OFFSET, 0), /*!< I3c Slow Clk Divider. */
795 } clock_div_name_t;
796
797 /*! @brief FFRO frequence configuration */
798 typedef enum _clock_ffro_freq
799 {
800 kCLOCK_Ffro48M, /*!< 48MHz FFRO clock. */
801 kCLOCK_Ffro60M, /*!< 60MHz FFRO clock. */
802 } clock_ffro_freq_t;
803 /*! @brief SysPLL Reference Input Clock Source */
804 typedef enum _sys_pll_src
805 {
806 kCLOCK_SysPllSFroClk = 0, /*!< 16MHz FRO clock */
807 kCLOCK_SysPllXtalIn = 1, /*!< OSC clock */
808 kCLOCK_SysPllFFroDiv2 = 2, /*!< FRO48/60 div2 clock */
809 kCLOCK_SysPllNone = 7 /*!< Gated to reduce power */
810 } sys_pll_src_t;
811
812 /*! @brief SysPLL Multiplication Factor */
813 typedef enum _sys_pll_mult
814 {
815 kCLOCK_SysPllMult16 = 0, /*!< Divide by 16 */
816 kCLOCK_SysPllMult17, /*!< Divide by 17 */
817 kCLOCK_SysPllMult18, /*!< Divide by 18 */
818 kCLOCK_SysPllMult19, /*!< Divide by 19 */
819 kCLOCK_SysPllMult20, /*!< Divide by 20 */
820 kCLOCK_SysPllMult21, /*!< Divide by 21 */
821 kCLOCK_SysPllMult22, /*!< Divide by 22 */
822 } sys_pll_mult_t;
823
824 /*! @brief PLL configuration for SYSPLL */
825 typedef struct _clock_sys_pll_config
826 {
827 sys_pll_src_t sys_pll_src; /*!< Reference Input Clock Source */
828 uint32_t numerator; /*!< 30 bit numerator of fractional loop divider. */
829 uint32_t denominator; /*!< 30 bit numerator of fractional loop divider. */
830 sys_pll_mult_t sys_pll_mult; /*!< Multiplication Factor */
831 } clock_sys_pll_config_t;
832
833 /*! @brief AudioPll Reference Input Clock Source */
834 typedef enum _audio_pll_src
835 {
836 kCLOCK_AudioPllSFroClk = 0, /*!< 16MHz FRO clock */
837 kCLOCK_AudioPllXtalIn = 1, /*!< OSC clock */
838 kCLOCK_AudioPllFFroDiv2 = 2, /*!< FRO48/60 div2 clock */
839 kCLOCK_AudioPllNone = 7 /*!< Gated to reduce power */
840 } audio_pll_src_t;
841
842 /*! @brief AudioPll Multiplication Factor */
843 typedef enum _audio_pll_mult
844 {
845 kCLOCK_AudioPllMult16 = 0, /*!< Divide by 16 */
846 kCLOCK_AudioPllMult17, /*!< Divide by 17 */
847 kCLOCK_AudioPllMult18, /*!< Divide by 18 */
848 kCLOCK_AudioPllMult19, /*!< Divide by 19 */
849 kCLOCK_AudioPllMult20, /*!< Divide by 20 */
850 kCLOCK_AudioPllMult21, /*!< Divide by 21 */
851 kCLOCK_AudioPllMult22, /*!< Divide by 22 */
852 } audio_pll_mult_t;
853
854 /*! @brief PLL configuration for SYSPLL */
855 typedef struct _clock_audio_pll_config
856 {
857 audio_pll_src_t audio_pll_src; /*!< Reference Input Clock Source */
858 uint32_t numerator; /*!< 30 bit numerator of fractional loop divider. */
859 uint32_t denominator; /*!< 30 bit numerator of fractional loop divider. */
860 audio_pll_mult_t audio_pll_mult; /*!< Multiplication Factor */
861 } clock_audio_pll_config_t;
862 /*! @brief PLL configuration for FRG */
863 typedef struct _clock_frg_clk_config
864 {
865 uint8_t num; /*!< FRG clock */
866 enum
867 {
868 kCLOCK_FrgMainClk = 0, /*!< Main System clock */
869 kCLOCK_FrgPllDiv, /*!< Main pll clock divider*/
870 kCLOCK_FrgSFro, /*!< 16MHz FRO */
871 kCLOCK_FrgFFro, /*!< FRO48/60 */
872 } sfg_clock_src;
873 uint8_t divider; /*!< Denominator of the fractional divider. */
874 uint8_t mult; /*!< Numerator of the fractional divider. */
875 } clock_frg_clk_config_t;
876
877 /*******************************************************************************
878 * API
879 ******************************************************************************/
880
881 #if defined(__cplusplus)
882 extern "C" {
883 #endif /* __cplusplus */
884
CLOCK_EnableClock(clock_ip_name_t clk)885 static inline void CLOCK_EnableClock(clock_ip_name_t clk)
886 {
887 uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk);
888
889 switch (index)
890 {
891 case CLK_CTL0_PSCCTL0:
892 CLKCTL0->PSCCTL0_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
893 break;
894 case CLK_CTL0_PSCCTL1:
895 CLKCTL0->PSCCTL1_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
896 break;
897 case CLK_CTL0_PSCCTL2:
898 CLKCTL0->PSCCTL2_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
899 break;
900 case CLK_CTL1_PSCCTL0:
901 CLKCTL1->PSCCTL0_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
902 break;
903 case CLK_CTL1_PSCCTL1:
904 CLKCTL1->PSCCTL1_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
905 break;
906 case CLK_CTL1_PSCCTL2:
907 CLKCTL1->PSCCTL2_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
908 break;
909 default:
910 assert(false);
911 break;
912 }
913 }
914
CLOCK_DisableClock(clock_ip_name_t clk)915 static inline void CLOCK_DisableClock(clock_ip_name_t clk)
916 {
917 uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk);
918 switch (index)
919 {
920 case CLK_CTL0_PSCCTL0:
921 CLKCTL0->PSCCTL0_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
922 break;
923 case CLK_CTL0_PSCCTL1:
924 CLKCTL0->PSCCTL1_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
925 break;
926 case CLK_CTL0_PSCCTL2:
927 CLKCTL0->PSCCTL2_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
928 break;
929 case CLK_CTL1_PSCCTL0:
930 CLKCTL1->PSCCTL0_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
931 break;
932 case CLK_CTL1_PSCCTL1:
933 CLKCTL1->PSCCTL1_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
934 break;
935 case CLK_CTL1_PSCCTL2:
936 CLKCTL1->PSCCTL2_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
937 break;
938 default:
939 assert(false);
940 break;
941 }
942 }
943 /**
944 * @brief Configure the clock selection muxes.
945 * @param connection : Clock to be configured.
946 * @return Nothing
947 */
948 void CLOCK_AttachClk(clock_attach_id_t connection);
949 /**
950 * @brief Setup peripheral clock dividers.
951 * @param div_name : Clock divider name
952 * @param divider : Value to be divided. Divided clock frequency = Undivided clock frequency / divider.
953 * @return Nothing
954 */
955 void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divider);
956 /*! @brief Return Frequency of selected clock
957 * @return Frequency of selected clock
958 */
959 uint32_t CLOCK_GetFreq(clock_name_t clockName);
960
961 /*! @brief Return Input frequency for the Fractional baud rate generator
962 * @return Input Frequency for FRG
963 */
964 uint32_t CLOCK_GetFRGClock(uint32_t id);
965
966 /*! @brief Set output of the Fractional baud rate generator
967 * @param config : Configuration to set to FRGn clock.
968 */
969 void CLOCK_SetFRGClock(const clock_frg_clk_config_t *config);
970
971 /*! @brief Return Frequency of FRO 16MHz
972 * @return Frequency of FRO 16MHz
973 */
CLOCK_GetSFroFreq(void)974 static inline uint32_t CLOCK_GetSFroFreq(void)
975 {
976 return CLK_FRO_16MHZ;
977 }
978 /*! @brief Return Frequency of SYSPLL
979 * @return Frequency of SYSPLL
980 */
981 uint32_t CLOCK_GetSysPllFreq(void);
982 /*! @brief Get current output frequency of specific System PLL PFD.
983 * @param pfd : pfd name to get frequency.
984 * @return Frequency of SYSPLL PFD.
985 */
986 uint32_t CLOCK_GetSysPfdFreq(clock_pfd_t pfd);
987 /*! @brief Return Frequency of AUDIO PLL
988 * @return Frequency of AUDIO PLL
989 */
990 uint32_t CLOCK_GetAudioPllFreq(void);
991 /*! @brief Get current output frequency of specific Audio PLL PFD.
992 * @param pfd : pfd name to get frequency.
993 * @return Frequency of AUDIO PLL PFD.
994 */
995 uint32_t CLOCK_GetAudioPfdFreq(clock_pfd_t pfd);
996 /*! @brief Return Frequency of High-Freq output of FRO
997 * @return Frequency of High-Freq output of FRO
998 */
999 uint32_t CLOCK_GetFFroFreq(void);
1000 /*! @brief Return Frequency of main clk
1001 * @return Frequency of main clk
1002 */
1003 uint32_t CLOCK_GetMainClkFreq(void);
1004 /*! @brief Return Frequency of DSP main clk
1005 * @return Frequency of DSP main clk
1006 */
1007 uint32_t CLOCK_GetDspMainClkFreq(void);
1008 /*! @brief Return Frequency of ACMP clk
1009 * @return Frequency of ACMP clk
1010 */
1011 uint32_t CLOCK_GetAcmpClkFreq(void);
1012 /*! @brief Return Frequency of DMIC clk
1013 * @return Frequency of DMIC clk
1014 */
1015 uint32_t CLOCK_GetDmicClkFreq(void);
1016 /*! @brief Return Frequency of USB clk
1017 * @return Frequency of USB clk
1018 */
1019 uint32_t CLOCK_GetUsbClkFreq(void);
1020 /*! @brief Return Frequency of SDIO clk
1021 * @param id : SDIO index to get frequency.
1022 * @return Frequency of SDIO clk
1023 */
1024 uint32_t CLOCK_GetSdioClkFreq(uint32_t id);
1025 /*! @brief Return Frequency of I3C clk
1026 * @return Frequency of I3C clk
1027 */
1028 uint32_t CLOCK_GetI3cClkFreq(void);
1029 /*! @brief Return Frequency of systick clk
1030 * @return Frequency of systick clk
1031 */
1032 uint32_t CLOCK_GetSystickClkFreq(void);
1033 /*! @brief Return Frequency of WDT clk
1034 * @param id : WDT index to get frequency.
1035 * @return Frequency of WDT clk
1036 */
1037 uint32_t CLOCK_GetWdtClkFreq(uint32_t id);
1038 /*! @brief Return Frequency of mclk
1039 * @return Frequency of mclk clk
1040 */
1041 uint32_t CLOCK_GetMclkClkFreq(void);
1042 /*! @brief Return Frequency of sct
1043 * @return Frequency of sct clk
1044 */
1045 uint32_t CLOCK_GetSctClkFreq(void);
1046 /*! @brief Enable/Disable sys osc clock from external crystal clock.
1047 * @param enable : true to enable system osc clock, false to bypass system osc.
1048 * @param enableLowPower : true to enable low power mode, false to enable high gain mode.
1049 * @param delay_us : Delay time after OSC power up.
1050 */
1051 void CLOCK_EnableSysOscClk(bool enable, bool enableLowPower, uint32_t delay_us);
1052 /*! @brief Return Frequency of sys osc Clock
1053 * @return Frequency of sys osc Clock. Or CLK_IN pin frequency.
1054 */
CLOCK_GetXtalInClkFreq(void)1055 static inline uint32_t CLOCK_GetXtalInClkFreq(void)
1056 {
1057 return (CLKCTL0->SYSOSCBYPASS == 0U) ? g_xtalFreq : ((CLKCTL0->SYSOSCBYPASS == 1U) ? g_clkinFreq : 0U);
1058 }
1059
1060 /*! @brief Return Frequency of MCLK Input Clock
1061 * @return Frequency of MCLK input Clock.
1062 */
CLOCK_GetMclkInClkFreq(void)1063 static inline uint32_t CLOCK_GetMclkInClkFreq(void)
1064 {
1065 return g_mclkFreq;
1066 }
1067
1068 /*! @brief Return Frequency of Lower power osc
1069 * @return Frequency of LPOSC
1070 */
CLOCK_GetLpOscFreq(void)1071 static inline uint32_t CLOCK_GetLpOscFreq(void)
1072 {
1073 return CLK_LPOSC_1MHZ;
1074 }
1075 /*! @brief Return Frequency of 32kHz osc
1076 * @return Frequency of 32kHz osc
1077 */
CLOCK_GetOsc32KFreq(void)1078 static inline uint32_t CLOCK_GetOsc32KFreq(void)
1079 {
1080 return ((CLKCTL0->OSC32KHZCTL0 & CLKCTL0_OSC32KHZCTL0_ENA32KHZ_MASK) != 0UL) ? CLK_RTC_32K_CLK : 0U;
1081 }
1082 /*! @brief Enables and disables 32kHz osc
1083 * @param enable : true to enable 32k osc clock, false to disable clock
1084 */
CLOCK_EnableOsc32K(bool enable)1085 static inline void CLOCK_EnableOsc32K(bool enable)
1086 {
1087 if (enable)
1088 {
1089 CLKCTL0->OSC32KHZCTL0 |= CLKCTL0_OSC32KHZCTL0_ENA32KHZ_MASK;
1090 }
1091 else
1092 {
1093 CLKCTL0->OSC32KHZCTL0 &= ~CLKCTL0_OSC32KHZCTL0_ENA32KHZ_MASK;
1094 }
1095 }
1096
1097 /*! @brief Return Frequency of 32khz wake clk
1098 * @return Frequency of 32kHz wake clk
1099 */
CLOCK_GetWakeClk32KFreq(void)1100 static inline uint32_t CLOCK_GetWakeClk32KFreq(void)
1101 {
1102 return ((CLKCTL0->WAKECLK32KHZSEL & CLKCTL0_WAKECLK32KHZSEL_SEL_MASK) != 0UL) ?
1103 CLOCK_GetLpOscFreq() / ((CLKCTL0->WAKECLK32KHZDIV & 0xffU) + 1U) :
1104 CLOCK_GetOsc32KFreq();
1105 }
1106 /*!
1107 * @brief Set the XTALIN (system OSC) frequency based on board setting.
1108 *
1109 * @param freq : The XTAL input clock frequency in Hz.
1110 */
CLOCK_SetXtalFreq(uint32_t freq)1111 static inline void CLOCK_SetXtalFreq(uint32_t freq)
1112 {
1113 g_xtalFreq = freq;
1114 }
1115 /*!
1116 * @brief Set the CLKIN (CLKIN pin) frequency based on board setting.
1117 *
1118 * @param freq : The CLK_IN pin input clock frequency in Hz.
1119 */
CLOCK_SetClkinFreq(uint32_t freq)1120 static inline void CLOCK_SetClkinFreq(uint32_t freq)
1121 {
1122 g_clkinFreq = freq;
1123 }
1124 /*!
1125 * @brief Set the MCLK in (mclk_in) clock frequency based on board setting.
1126 *
1127 * @param freq : The MCLK input clock frequency in Hz.
1128 */
CLOCK_SetMclkFreq(uint32_t freq)1129 static inline void CLOCK_SetMclkFreq(uint32_t freq)
1130 {
1131 g_mclkFreq = freq;
1132 }
1133
1134 /*! @brief Return Frequency of Flexcomm functional Clock
1135 * @param id : flexcomm index to get frequency.
1136 * @return Frequency of Flexcomm functional Clock
1137 */
1138 uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id);
1139 /*! @brief Return Frequency of Ctimer Clock
1140 * @param id : ctimer index to get frequency.
1141 * @return Frequency of Ctimer Clock
1142 */
1143 uint32_t CLOCK_GetCtimerClkFreq(uint32_t id);
1144 /*! @brief Return Frequency of ClockOut
1145 * @return Frequency of ClockOut
1146 */
1147 uint32_t CLOCK_GetClockOutClkFreq(void);
1148 /*! @brief Return Frequency of Adc Clock
1149 * @return Frequency of Adc Clock.
1150 */
1151 uint32_t CLOCK_GetAdcClkFreq(void);
1152 /*! @brief Return Frequency of Flexspi Clock
1153 * @return Frequency of Flexspi.
1154 */
1155 uint32_t CLOCK_GetFlexspiClkFreq(void);
1156 #ifndef __XTENSA__
1157 /**
1158 * brief Enable FFRO 48M/60M clock.
1159 * param ffroFreq : target fro frequency.
1160 * return Nothing
1161 */
1162 void CLOCK_EnableFfroClk(clock_ffro_freq_t ffroFreq);
1163 /**
1164 * brief Enable SFRO clock.
1165 * param Nothing
1166 * return Nothing
1167 */
1168 void CLOCK_EnableSfroClk(void);
1169 /*! @brief Initialize the System PLL.
1170 * @param config : Configuration to set to PLL.
1171 */
1172 #endif /* __XTENSA__ */
1173
1174 void CLOCK_InitSysPll(const clock_sys_pll_config_t *config);
1175 /*! brief Deinit the System PLL.
1176 * param none.
1177 */
CLOCK_DeinitSysPll(void)1178 static inline void CLOCK_DeinitSysPll(void)
1179 {
1180 /* Set System PLL Reset & HOLDRINGOFF_ENA */
1181 CLKCTL0->SYSPLL0CTL0 |= CLKCTL0_SYSPLL0CTL0_HOLDRINGOFF_ENA_MASK | CLKCTL0_SYSPLL0CTL0_RESET_MASK;
1182 /* Power down System PLL*/
1183 SYSCTL0->PDRUNCFG0_SET = SYSCTL0_PDRUNCFG0_SYSPLLLDO_PD_MASK | SYSCTL0_PDRUNCFG0_SYSPLLANA_PD_MASK;
1184 }
1185 /*! @brief Initialize the System PLL PFD.
1186 * @param pfd : Which PFD clock to enable.
1187 * @param divider : The PFD divider value.
1188 * @note It is recommended that PFD settings are kept between 12-35.
1189 */
1190 void CLOCK_InitSysPfd(clock_pfd_t pfd, uint8_t divider);
1191 /*! brief Disable the audio PLL PFD.
1192 * param pfd : Which PFD clock to disable.
1193 */
CLOCK_DeinitSysPfd(clock_pfd_t pfd)1194 static inline void CLOCK_DeinitSysPfd(clock_pfd_t pfd)
1195 {
1196 CLKCTL0->SYSPLL0PFD |= ((uint32_t)CLKCTL1_AUDIOPLL0PFD_PFD0_CLKGATE_MASK << (8UL * (uint32_t)pfd));
1197 }
1198 /*! @brief Initialize the audio PLL.
1199 * @param config : Configuration to set to PLL.
1200 */
1201 void CLOCK_InitAudioPll(const clock_audio_pll_config_t *config);
1202 /*! brief Deinit the Audio PLL.
1203 * param none.
1204 */
CLOCK_DeinitAudioPll(void)1205 static inline void CLOCK_DeinitAudioPll(void)
1206 {
1207 /* Set Audio PLL Reset & HOLDRINGOFF_ENA */
1208 CLKCTL1->AUDIOPLL0CTL0 |= CLKCTL1_AUDIOPLL0CTL0_HOLDRINGOFF_ENA_MASK | CLKCTL1_AUDIOPLL0CTL0_RESET_MASK;
1209 /* Power down Audio PLL */
1210 SYSCTL0->PDRUNCFG0_SET = SYSCTL0_PDRUNCFG0_AUDPLLLDO_PD_MASK | SYSCTL0_PDRUNCFG0_AUDPLLANA_PD_MASK;
1211 }
1212 /*! @brief Initialize the audio PLL PFD.
1213 * @param pfd : Which PFD clock to enable.
1214 * @param divider : The PFD divider value.
1215 * @note It is recommended that PFD settings are kept between 12-35.
1216 */
1217 void CLOCK_InitAudioPfd(clock_pfd_t pfd, uint8_t divider);
1218 /*! brief Disable the audio PLL PFD.
1219 * param pfd : Which PFD clock to disable.
1220 */
CLOCK_DeinitAudioPfd(uint32_t pfd)1221 static inline void CLOCK_DeinitAudioPfd(uint32_t pfd)
1222 {
1223 CLKCTL1->AUDIOPLL0PFD |= ((uint32_t)CLKCTL1_AUDIOPLL0PFD_PFD0_CLKGATE_MASK << (8UL * (uint32_t)pfd));
1224 }
1225 /*! @brief Enable USB HS device PLL clock.
1226 *
1227 * This function enables USB HS device PLL clock.
1228 */
1229 void CLOCK_EnableUsbhsDeviceClock(void);
1230 /*! @brief Enable USB HS host PLL clock.
1231 *
1232 * This function enables USB HS host PLL clock.
1233 */
1234 void CLOCK_EnableUsbhsHostClock(void);
1235 /*! brief Enable USB hs0PhyPll clock.
1236 *
1237 * param src USB HS clock source.
1238 * param freq The frequency specified by src.
1239 * retval true The clock is set successfully.
1240 * retval false The clock source is invalid to get proper USB HS clock.
1241 */
1242 bool CLOCK_EnableUsbHs0PhyPllClock(clock_attach_id_t src, uint32_t freq);
1243 #if defined(__cplusplus)
1244 }
1245 #endif /* __cplusplus */
1246
1247 /*! @} */
1248
1249 #endif /* _FSL_CLOCK_H_ */
1250
