1 /*
2 * Copyright 2023-2024 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #ifndef FSL_CLOCK_H_
9 #define FSL_CLOCK_H_
10
11 #include "fsl_common.h"
12 #include "fsl_device_registers.h"
13 #include "fsl_reset.h"
14 #include <assert.h>
15 #include <stdbool.h>
16 #include <stdint.h>
17
18 /*! @addtogroup clock */
19 /*! @{ */
20
21 /*! @file */
22
23 /*******************************************************************************
24 * Definitions
25 *****************************************************************************/
26
27 /*! @name Driver version */
28 /*@{*/
29 /*! @brief CLOCK driver version 2.3.1 */
30 #define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 3, 1))
31 /*@}*/
32
33 #if defined(MIMXRT798S_hifi1_SERIES) || defined(MIMXRT798S_cm33_core1_SERIES) || \
34 defined(MIMXRT758S_cm33_core1_SERIES) || defined(MIMXRT735S_cm33_core1_SERIES)
35 #define FSL_CLOCK_DRIVER_SENSE
36 #elif defined(MIMXRT798S_hifi4_SERIES) || defined(MIMXRT798S_cm33_core0_SERIES) || \
37 defined(MIMXRT758S_cm33_core0_SERIES) || defined(MIMXRT735S_cm33_core0_SERIES)
38 #define FSL_CLOCK_DRIVER_COMPUTE
39 #elif defined(MIMXRT798S_ezhv_SERIES) || defined(MIMXRT758S_ezhv_SERIES) || defined(MIMXRT735S_ezhv_SERIES)
40 #define FSL_CLOCK_DRIVER_MEDIA
41 #else
42 #error "Unsupported core!"
43 #endif
44
45 /* Definition for delay API in clock driver, users can redefine it to the real
46 * application. */
47 #ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
48 #if defined(FSL_CLOCK_DRIVER_SENSE)
49 #define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (100000000UL)
50 #elif defined(FSL_CLOCK_DRIVER_COMPUTE)
51 #define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (300000000UL)
52 #elif defined(FSL_CLOCK_DRIVER_MEDIA)
53 /* EZHV process clock is m_clk. */
54 #define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (300UL * 1000UL * 1000UL)
55 #endif /* FSL_CLOCK_DRIVER_SENSE */
56 #endif /* SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY */
57
58 /* Definition for compatiblity. */
59 #define CLOCK_DeinitSysPfd CLOCK_DeinitMainPfd
60 #define CLOCK_InitSysPfd CLOCK_InitMainPfd
61
62 /*! @brief External XTAL (SYSOSC) clock frequency.
63 *
64 * The XTAL (SYSOSC) clock frequency in Hz, when the clock is setup, use the
65 * function CLOCK_SetXtalFreq to set the value in to clock driver. For example,
66 * if XTAL is 16MHz,
67 * @code
68 * CLOCK_SetXtalFreq(160000000);
69 * @endcode
70 */
71 extern volatile uint32_t g_xtalFreq;
72
73 /*! @brief External CLK_IN pin clock frequency (clkin).
74 *
75 * The CLK_IN pin (clkin) clock frequency in Hz, when the clock is setup, use
76 * the function CLOCK_SetClkinFreq to set the value in to clock driver. For
77 * example, if CLK_IN is 16MHz,
78 * @code
79 * CLOCK_SetClkinFreq(160000000);
80 * @endcode
81 */
82 extern volatile uint32_t g_clkinFreq;
83
84 /*! @brief External 32KHz input clock frequency.
85 *
86 * The External 32KHz input clock frequency in Hz, used when OSC32KNP in bypass mode, use
87 * the function CLOCK_Set32kClkinFreq to set the value in to clock driver. For
88 * example, if EXTALIN32K input is 32768,
89 * @code
90 * CLOCK_Set32kClkinFreq(32768);
91 * @endcode
92 */
93 extern volatile uint32_t g_32kClkinFreq;
94
95 /*! @brief External MCLK IN clock frequency.
96 *
97 * The MCLK IN clock frequency in Hz, when the clock is setup, use the
98 * function CLOCK_SetMclkFreq to set the value in to clock driver. For example,
99 * if MCLK IN is 16MHz,
100 * @code
101 * CLOCK_SetMclkFreq(160000000);
102 * @endcode
103 */
104 extern volatile uint32_t g_mclkFreq;
105
106 #if defined(FSL_CLOCK_DRIVER_COMPUTE)
107 /*! @brief VDD1(Sense) audio_clk clock frequency.
108 *
109 *NOTE, The compute domain can't read the Sense VDD1 audio_clk selection. The compute domain need call
110 *CLOCK_SetSenseAudioClkFreq() to tell the clock driver the frequncy of current VDD1 audio_clk, and then
111 *CLOCK_GetSenseAudioClkFreq() can return the correct value.
112 * @code
113 * CLOCK_SetSenseAudioClkFreq(24000000);
114 * @endcode
115 */
116 extern volatile uint32_t g_senseAudioClkFreq;
117 #endif
118
119 /*! @brief Clock ip name array for CDOG. */
120 #define CDOG_CLOCKS \
121 { \
122 kCLOCK_Cdog0, kCLOCK_Cdog1, kCLOCK_Cdog2, kCLOCK_Cdog3, kCLOCK_Cdog4 \
123 }
124
125 /*! @brief Clock ip name array for FREQME. */
126 #define FREQME_CLOCKS \
127 { \
128 kCLOCK_Freqme0 \
129 }
130
131 /*! @brief Clock ip name array for GPU. */
132 #define GPU_CLOCKS \
133 { \
134 kCLOCK_Gpu \
135 }
136
137 /*! @brief Clock ip name array for MIPI DSI. */
138 #define MIPI_DSI_HOST_CLOCKS \
139 { \
140 kCLOCK_MipiDsiCtrl \
141 }
142
143 /*! @brief Clock ip name array for LCDIF. */
144 #define LCDIF_CLOCKS \
145 { \
146 kCLOCK_Lcdif \
147 }
148
149 /*! @brief Clock ip name array for SCT. */
150 #define SCT_CLOCKS \
151 { \
152 kCLOCK_Sct0 \
153 }
154
155 /*! @brief Clock ip name array for USB. */
156 #define USB_CLOCKS \
157 { \
158 kCLOCK_Usb0, kCLOCK_Usb1 \
159 }
160
161 /*! @brief Clock ip name array for USBPHY. */
162 #define USBPHY_CLOCKS \
163 { \
164 kCLOCK_Usbphy0, kCLOCK_Usbphy1 \
165 }
166
167 /*! @brief Clock ip name array for FlexSPI */
168 #define XSPI_CLOCKS \
169 { \
170 kCLOCK_Xspi0, kCLOCK_Xspi1, kCLOCK_Xspi2 \
171 }
172
173 /*! @brief Clock ip name array for MMU */
174 #define MMU_CLOCKS \
175 { \
176 kCLOCK_Mmu0, kCLOCK_Mmu1, kCLOCK_Mmu2 \
177 }
178
179 /*! @brief Clock ip name array for CACHE64 */
180 #define CACHE64_CLOCKS \
181 { \
182 kCLOCK_Cache64ctrl0, kCLOCK_Cache64ctrl1 \
183 }
184
185 /*! @brief Clock ip name array for CACHE64_POLSEL */
186 #define CACHE64POLSEL_CLOCKS \
187 { \
188 kCLOCK_Cache64Polsel0, kCLOCK_Cache64Polsel1 \
189 }
190
191 /*! @brief Clock ip name array for ADC. */
192 #define LPADC_CLOCKS \
193 { \
194 kCLOCK_Adc0 \
195 }
196
197 /*! @brief Clock ip name array for SDADC. */
198 #define SDADC_CLOCKS \
199 { \
200 kCLOCK_Sdadc0 \
201 }
202
203 /*! @brief Clock ip name array for ACMP. */
204 #define CMP_CLOCKS \
205 { \
206 kCLOCK_Acmp0 \
207 }
208
209 /*! @brief Clock ip name array for uSDHC */
210 #define USDHC_CLOCKS \
211 { \
212 kCLOCK_Usdhc0, kCLOCK_Usdhc1 \
213 }
214
215 /*! @brief Clock ip name array for WWDT. */
216 #define WWDT_CLOCKS \
217 { \
218 kCLOCK_Wwdt0, kCLOCK_Wwdt1, kCLOCK_Wwdt2, kCLOCK_Wwdt3 \
219 }
220
221 /*! @brief Clock ip name array for UTICK. */
222 #define UTICK_CLOCKS \
223 { \
224 kCLOCK_Utick0, kCLOCK_Utick1 \
225 }
226
227 /*! @brief Clock ip name array for FlexIO. */
228 #define FLEXIO_CLOCKS \
229 { \
230 kCLOCK_Flexio \
231 }
232
233 /*! @brief Clock ip name array for LP_FLEXCOMM. */
234 #define LP_FLEXCOMM_CLOCKS \
235 { \
236 kCLOCK_LPFlexComm0, kCLOCK_LPFlexComm1, kCLOCK_LPFlexComm2, kCLOCK_LPFlexComm3, kCLOCK_LPFlexComm4, \
237 kCLOCK_LPFlexComm5, kCLOCK_LPFlexComm6, kCLOCK_LPFlexComm7, kCLOCK_LPFlexComm8, kCLOCK_LPFlexComm9, \
238 kCLOCK_LPFlexComm10, kCLOCK_LPFlexComm11, kCLOCK_LPFlexComm12, kCLOCK_LPFlexComm13, kCLOCK_IpInvalid, \
239 kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_LPFlexComm17, kCLOCK_LPFlexComm18, kCLOCK_LPFlexComm19, \
240 kCLOCK_LPFlexComm20 \
241 }
242 /*! @brief Clock ip name array for LPUART. */
243 #define LPUART_CLOCKS \
244 { \
245 kCLOCK_LPUart0, kCLOCK_LPUart1, kCLOCK_LPUart2, kCLOCK_LPUart3, kCLOCK_LPUart4, kCLOCK_LPUart5, \
246 kCLOCK_LPUart6, kCLOCK_LPUart7, kCLOCK_LPUart8, kCLOCK_LPUart9, kCLOCK_LPUart10, kCLOCK_LPUart11, \
247 kCLOCK_LPUart12, kCLOCK_LPUart13, kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_LPUart17, \
248 kCLOCK_LPUart18, kCLOCK_LPUart19, kCLOCK_LPUart20 \
249 }
250 /*! @brief Clock ip name array for LPI2C. */
251 #define LPI2C_CLOCKS \
252 { \
253 kCLOCK_LPI2c0, kCLOCK_LPI2c1, kCLOCK_LPI2c2, kCLOCK_LPI2c3, kCLOCK_LPI2c4, kCLOCK_LPI2c5, kCLOCK_LPI2c6, \
254 kCLOCK_LPI2c7, kCLOCK_LPI2c8, kCLOCK_LPI2c9, kCLOCK_LPI2c10, kCLOCK_LPI2c11, kCLOCK_LPI2c12, \
255 kCLOCK_LPI2c13, kCLOCK_IpInvalid, kCLOCK_LPI2c15, kCLOCK_IpInvalid, kCLOCK_LPI2c17, kCLOCK_LPI2c18, \
256 kCLOCK_LPI2c19, kCLOCK_LPI2c20 \
257 }
258 /*! @brief Clock ip name array for LSPI. */
259 #define LPSPI_CLOCKS \
260 { \
261 kCLOCK_LPSpi0, kCLOCK_LPSpi1, kCLOCK_LPSpi2, kCLOCK_LPSpi3, kCLOCK_LPSpi4, kCLOCK_LPSpi5, kCLOCK_LPSpi6, \
262 kCLOCK_LPSpi7, kCLOCK_LPSpi8, kCLOCK_LPSpi9, kCLOCK_LPSpi10, kCLOCK_LPSpi11, kCLOCK_LPSpi12, \
263 kCLOCK_LPSpi13, kCLOCK_LPSpi14, kCLOCK_IpInvalid, kCLOCK_LPSpi16, kCLOCK_LPSpi17, kCLOCK_LPSpi18, \
264 kCLOCK_LPSpi19, kCLOCK_LPSpi20 \
265 }
266 /*! @brief Clock ip name array for SAI. */
267 #define SAI_CLOCKS \
268 { \
269 kCLOCK_Sai0, kCLOCK_Sai1, kCLOCK_Sai2, kCLOCK_Sai3 \
270 }
271
272 /*! @brief Clock ip name array for SEMA */
273 #define SEMA42_CLOCKS \
274 { \
275 kCLOCK_Sema420, kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_Sema423, kCLOCK_Sema424 \
276 }
277
278 /*! @brief Clock ip name array for MU */
279 #if defined(FSL_CLOCK_DRIVER_COMPUTE)
280 #ifndef __XTENSA__
281 #define MU_CLOCKS \
282 { \
283 kCLOCK_Mu0, kCLOCK_Mu1, kCLOCK_Mu4 \
284 }
285 #else
286 #define MU_CLOCKS \
287 { \
288 kCLOCK_Mu2, kCLOCK_Mu4 \
289 }
290 #endif /* __XTENSA__ */
291
292 /*! @brief Clock ip name array for DMA. */
293 #define EDMA_CLOCKS \
294 { \
295 kCLOCK_Dma0, kCLOCK_Dma1 \
296 }
297
298 /*! @brief Clock ip name array for SYSPM. */
299 #define SYSPM_CLOCKS \
300 { \
301 kCLOCK_Syspm0, kCLOCK_Syspm1, kCLOCK_IpInvalid, kCLOCK_IpInvalid \
302 }
303
304 /*! @brief Clock ip name array for TRNG. */
305 #define TRNG_CLOCKS \
306 { \
307 kCLOCK_TrngRef \
308 }
309
310 #endif /* FSL_CLOCK_DRIVER_COMPUTE */
311
312 #if defined(FSL_CLOCK_DRIVER_SENSE)
313 #ifndef __XTENSA__
314 #define MU_CLOCKS \
315 { \
316 kCLOCK_Mu1, kCLOCK_Mu2, kCLOCK_Mu3 \
317 }
318 #else
319 #define MU_CLOCKS \
320 { \
321 kCLOCK_Mu0, kCLOCK_Mu3 \
322 }
323 #endif /* __XTENSA__ */
324
325 /*! @brief Clock ip name array for DMA. */
326 #define EDMA_CLOCKS \
327 { \
328 kCLOCK_Dma2, kCLOCK_Dma3 \
329 }
330 #endif /* FSL_CLOCK_DRIVER_SENSE */
331
332 /*! @brief Clock ip name array for CRC. */
333 #define CRC_CLOCKS \
334 { \
335 kCLOCK_Crc0 \
336 }
337
338 #if defined(FSL_CLOCK_DRIVER_COMPUTE)
339 /*! @brief Clock ip name array for GDET. */
340 #define GDET_CLOCKS \
341 { \
342 kCLOCK_Gdet0, kCLOCK_Gdet1, kCLOCK_Gdet2, kCLOCK_Gdet3 \
343 }
344
345 /*! @brief Clock ip name array for GDET_REF. */
346 #define GDET_REF_CLOCKS \
347 { \
348 kCLOCK_Gdet0Ref, kCLOCK_Gdet1Ref, kCLOCK_Gdet2Ref, kCLOCK_Gdet3Ref \
349 }
350 #endif
351 #if defined(FSL_CLOCK_DRIVER_SENSE)
352 /*! @brief Clock ip name array for GDET. */
353 #define GDET_CLOCKS \
354 { \
355 kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_Gdet2, kCLOCK_Gdet3 \
356 }
357
358 /*! @brief Clock ip name array for GDET_REF. */
359 #define GDET_REF_CLOCKS \
360 { \
361 kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_Gdet2Ref, kCLOCK_Gdet3Ref \
362 }
363 #endif
364
365 /*! @brief Clock ip name array for GPIO. */
366 #define GPIO_CLOCKS \
367 { \
368 kCLOCK_Gpio0, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3, kCLOCK_Gpio4, kCLOCK_Gpio5, kCLOCK_Gpio6, \
369 kCLOCK_Gpio7, kCLOCK_Gpio8, kCLOCK_Gpio9, kCLOCK_Gpio10, kCLOCK_Gpio0, kCLOCK_Gpio1, kCLOCK_Gpio2, \
370 kCLOCK_Gpio3, kCLOCK_Gpio4, kCLOCK_Gpio5, kCLOCK_Gpio6, kCLOCK_Gpio7, kCLOCK_Gpio8, kCLOCK_Gpio9, \
371 kCLOCK_Gpio10 \
372 }
373
374 /*! @brief Clock ip name array for PDM. */
375 #define PDM_CLOCKS \
376 { \
377 kCLOCK_Pdm \
378 }
379
380 /*! @brief Clock ip name array for PINT. */
381 #define PINT_CLOCKS \
382 { \
383 kCLOCK_Pint \
384 }
385
386 /*! @brief Clock ip name array for PNGDEC. */
387 #define PNGDEC_CLOCKS \
388 { \
389 kCLOCK_PngDecoder \
390 }
391
392 /*! @brief Clock ip name array for JPEGDEC. */
393 #define JPEGDEC_CLOCKS \
394 { \
395 kCLOCK_JpgDecoder \
396 }
397
398 /*! @brief Clock ip name array for I3C. */
399 #define I3C_CLOCKS \
400 { \
401 kCLOCK_I3c0, kCLOCK_I3c1, kCLOCK_I3c2, kCLOCK_I3c3 \
402 }
403
404 /*! @brief Clock ip name array for MRT. */
405 #define MRT_CLOCKS \
406 { \
407 kCLOCK_Mrt0, kCLOCK_Mrt1 \
408 }
409
410 /*! @brief Clock ip name array for CT32B. */
411 #define CTIMER_CLOCKS \
412 { \
413 kCLOCK_Ct32b0, kCLOCK_Ct32b1, kCLOCK_Ct32b2, kCLOCK_Ct32b3, kCLOCK_Ct32b4, kCLOCK_Ct32b5, kCLOCK_Ct32b6, \
414 kCLOCK_Ct32b7 \
415 }
416
417 /*! @brief Clock ip name array for OSTIMER. */
418 #define OSTIMER_CLOCKS \
419 { \
420 kCLOCK_OsTimer \
421 }
422
423 /*! @brief Clock ip name array for RTC. */
424 #define RTC_CLOCKS \
425 { \
426 kCLOCK_Rtc \
427 }
428
429 /*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
430 /*------------------------------------------------------------------------------
431 clock_ip_name_t definition:
432 ------------------------------------------------------------------------------*/
433 #define CLK_GATE_REG_OFFSET_SHIFT 8U
434 #define CLK_GATE_REG_OFFSET_MASK 0xFF00U
435 #define CLK_GATE_BIT_SHIFT_SHIFT 0U
436 #define CLK_GATE_BIT_SHIFT_MASK 0x00FFU
437
438 #define CLK_GATE_DEFINE(reg_offset, bit_shift) \
439 ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \
440 (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK))
441
442 #define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((uint32_t)(x) & CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT)
443 #define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((uint32_t)(x) & CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT)
444
445 #define CLK_CTL0_PSCCTL0 0 /* CLKCTL_COM_VDD2 PSCCTL0 */
446 #define CLK_CTL0_PSCCTL1 1
447 #define CLK_CTL0_PSCCTL2 2
448 #define CLK_CTL0_PSCCTL3 3
449 #define CLK_CTL0_PSCCTL4 4
450 #define CLK_CTL0_PSCCTL5 5
451 #define CLK_CTL1_PSCCTL0 6 /* CLKCTL_VDD1_SENSE PSCCTL0 */
452 #define CLK_CTL1_PSCCTL1 7
453 #define CLK_CTL2_PSCCTL0 8 /* CLKCTL_VDD1_COM PSCCTL0 */
454 #define CLK_CTL3_PSCCTL0 9 /* CLKCTL2 PSCCTL0 */
455 #define CLK_CTL4_PSCCTL0 10 /* CLKCTL_MED_VDD2 PSCCTL0 */
456 #define CLK_CTL4_PSCCTL1 11 /* CLKCTL_MED_VDD2 PSCCTL1 */
457 #if defined(FSL_CLOCK_DRIVER_COMPUTE) || defined(FSL_CLOCK_DRIVER_MEDIA)
458 #define SYSCON0_SEC_CLK_CTRL 12
459 #endif
460 #define SYSCON3_SEC_CLK_CTRL 13
461 #define CLKCTL0_ONE_SRC_CLKSLICE_ENABLE 14
462 #define CLKCTL3_ONE_SRC_CLKSLICE_ENABLE 15
463 #define CLKCTL4_ONE_SRC_CLKSLICE_ENABLE 16
464
465 /*! @brief USB clock source definition. */
466 typedef enum _clock_usb_src
467 {
468 kCLOCK_Usb480M = 0, /*!< Use 480M. */
469 kCLOCK_UsbSrcUnused = (int)0xFFFFFFFFU, /*!< Used when the function does not
470 care the clock source. */
471 } clock_usb_src_t;
472
473 /*! @brief Source of the USB HS PHY. */
474 typedef enum _clock_usb_phy_src
475 {
476 kCLOCK_Usbphy480M = 0, /*!< Use 480M. */
477 } clock_usb_phy_src_t;
478
479 /*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
480 typedef enum _clock_ip_name
481 {
482 kCLOCK_IpInvalid = 0U, /*!< Invalid Ip Name. */
483
484 kCLOCK_Xcache1 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 1), /*!< Clock gate name: Code cache*/
485 kCLOCK_Xcache0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 2), /*!< Clock gate name: System cache*/
486 kCLOCK_Ocotp0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 5), /*!< Clock gate name: VDD2 OTP0*/
487 kCLOCK_Sleepcon0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 12), /*!< Clock gate name: SLEEPCON_CMPT*/
488 kCLOCK_Syscon0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 13), /*!< Clock gate name: SYSCON_CMPT*/
489 kCLOCK_Glikey0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 14), /*!< Clock gate name: GLIKEY0*/
490 kCLOCK_Glikey3 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 15), /*!< Clock gate name: GLIKEY3*/
491
492 kCLOCK_TpiuTraceClkin = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 2), /*!< Clock gate name: TPIU_TRACECLKIN*/
493 kCLOCK_SWOTraceClkin = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 3), /*!< Clock gate name: SWO_TRACECLKIN*/
494 kCLOCK_Tsclk = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 4), /*!< Clock gate name: TRACE*/
495 kCLOCK_Dma0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 5), /*!< Clock gate name: DMA0*/
496 kCLOCK_Dma1 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 6), /*!< Clock gate name: DMA1*/
497 kCLOCK_PkcRam = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 7), /*!< Clock gate name: PKC RAM */
498 kCLOCK_Pkc = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 8), /*!< Clock gate name: PKC*/
499 kCLOCK_Romcp = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 9), /*!< Clock gate name: ROMCP*/
500 kCLOCK_Xspi0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 10), /*!< Clock gate name: XSPI0*/
501 kCLOCK_Xspi1 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 11), /*!< Clock gate name: XSPI1*/
502 kCLOCK_Cache64ctrl0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 12), /*!< Clock gate name: CACHE64_0*/
503 kCLOCK_Cache64ctrl1 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 13), /*!< Clock gate name: CACHE64_1*/
504 kCLOCK_Puf = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 14), /*!< Clock gate name: QK_SUBSYS*/
505 kCLOCK_Mmu0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 16), /*!< Clock gate name: MMU0*/
506 kCLOCK_Mmu1 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 17), /*!< Clock gate name: MMU1*/
507 kCLOCK_Gpio0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 18), /*!< Clock gate name: GPIO0*/
508 kCLOCK_Gpio1 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 19), /*!< Clock gate name: GPIO1*/
509 kCLOCK_Gpio2 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 20), /*!< Clock gate name: GPIO2*/
510 kCLOCK_Gpio3 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 21), /*!< Clock gate name: GPIO3*/
511 kCLOCK_Gpio4 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 22), /*!< Clock gate name: GPIO4*/
512 kCLOCK_Gpio5 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 23), /*!< Clock gate name: GPIO5*/
513 kCLOCK_Gpio6 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 24), /*!< Clock gate name: GPIO6*/
514 kCLOCK_Gpio7 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 25), /*!< Clock gate name: GPIO7*/
515 kCLOCK_Sct0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 26), /*!< Clock gate name: SCT0*/
516 kCLOCK_Cdog0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 27), /*!< Clock gate name: CDOG0*/
517 kCLOCK_Cdog1 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 28), /*!< Clock gate name: CDOG1*/
518 kCLOCK_Cdog2 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 29), /*!< Clock gate name: CDOG2*/
519 kCLOCK_LPFlexComm0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 30), /*!< Clock gate name: LP_Flexcomm0*/
520 kCLOCK_LPFlexComm1 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 31), /*!< Clock gate name: LP_Flexcomm1*/
521 kCLOCK_LPUart0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 30), /*!< Clock gate name: LPUART0*/
522 kCLOCK_LPUart1 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 31), /*!< Clock gate name: LPUART1*/
523 kCLOCK_LPI2c0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 30), /*!< Clock gate name: LPI2C0*/
524 kCLOCK_LPI2c1 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 31), /*!< Clock gate name: LPI2C1*/
525 kCLOCK_LPSpi0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 30), /*!< Clock gate name: LPSPI0*/
526 kCLOCK_LPSpi1 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 31), /*!< Clock gate name: LPSPI1*/
527 kCLOCK_LPFlexComm2 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 0), /*!< Clock gate name: LP_Flexcomm2*/
528 kCLOCK_LPFlexComm3 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 1), /*!< Clock gate name: LP_Flexcomm3*/
529 kCLOCK_LPFlexComm4 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 2), /*!< Clock gate name: LP_Flexcomm4*/
530 kCLOCK_LPFlexComm5 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 3), /*!< Clock gate name: LP_Flexcomm5*/
531 kCLOCK_LPFlexComm6 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 4), /*!< Clock gate name: LP_Flexcomm6*/
532 kCLOCK_LPFlexComm7 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 5), /*!< Clock gate name: LP_Flexcomm7*/
533 kCLOCK_LPFlexComm8 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 6), /*!< Clock gate name: LP_Flexcomm8*/
534 kCLOCK_LPFlexComm9 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 7), /*!< Clock gate name: LP_Flexcomm9*/
535 kCLOCK_LPFlexComm10 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 8), /*!< Clock gate name: LP_Flexcomm10*/
536 kCLOCK_LPFlexComm11 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 9), /*!< Clock gate name: LP_Flexcomm11*/
537 kCLOCK_LPFlexComm12 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 10), /*!< Clock gate name: LP_Flexcomm12*/
538 kCLOCK_LPFlexComm13 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 11), /*!< Clock gate name: LP_Flexcomm13*/
539 kCLOCK_LPUart2 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 0), /*!< Clock gate name: LPUART2*/
540 kCLOCK_LPUart3 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 1), /*!< Clock gate name: LPUART3*/
541 kCLOCK_LPUart4 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 2), /*!< Clock gate name: LPUART4*/
542 kCLOCK_LPUart5 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 3), /*!< Clock gate name: LPUART5*/
543 kCLOCK_LPUart6 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 4), /*!< Clock gate name: LPUART6*/
544 kCLOCK_LPUart7 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 5), /*!< Clock gate name: LPUART7*/
545 kCLOCK_LPUart8 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 6), /*!< Clock gate name: LPUART8*/
546 kCLOCK_LPUart9 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 7), /*!< Clock gate name: LPUART9*/
547 kCLOCK_LPUart10 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 8), /*!< Clock gate name: LPUART10*/
548 kCLOCK_LPUart11 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 9), /*!< Clock gate name: LPUART11*/
549 kCLOCK_LPUart12 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 10), /*!< Clock gate name: LPUART12*/
550 kCLOCK_LPUart13 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 11), /*!< Clock gate name: LPUART13*/
551 kCLOCK_LPI2c2 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 0), /*!< Clock gate name: LPI2C2*/
552 kCLOCK_LPI2c3 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 1), /*!< Clock gate name: LPI2C3*/
553 kCLOCK_LPI2c4 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 2), /*!< Clock gate name: LPI2C4*/
554 kCLOCK_LPI2c5 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 3), /*!< Clock gate name: LPI2C5*/
555 kCLOCK_LPI2c6 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 4), /*!< Clock gate name: LPI2C6*/
556 kCLOCK_LPI2c7 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 5), /*!< Clock gate name: LPI2C7*/
557 kCLOCK_LPI2c8 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 6), /*!< Clock gate name: LPI2C8*/
558 kCLOCK_LPI2c9 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 7), /*!< Clock gate name: LPI2C9*/
559 kCLOCK_LPI2c10 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 8), /*!< Clock gate name: LPI2C10*/
560 kCLOCK_LPI2c11 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 9), /*!< Clock gate name: LPI2C11*/
561 kCLOCK_LPI2c12 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 10), /*!< Clock gate name: LPI2C12*/
562 kCLOCK_LPI2c13 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 11), /*!< Clock gate name: LPI2C13*/
563 kCLOCK_LPSpi2 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 0), /*!< Clock gate name: LPSPI2*/
564 kCLOCK_LPSpi3 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 1), /*!< Clock gate name: LPSPI3*/
565 kCLOCK_LPSpi4 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 2), /*!< Clock gate name: LPSPI4*/
566 kCLOCK_LPSpi5 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 3), /*!< Clock gate name: LPSPI5*/
567 kCLOCK_LPSpi6 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 4), /*!< Clock gate name: LPSPI6*/
568 kCLOCK_LPSpi7 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 5), /*!< Clock gate name: LPSPI7*/
569 kCLOCK_LPSpi8 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 6), /*!< Clock gate name: LPSPI8*/
570 kCLOCK_LPSpi9 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 7), /*!< Clock gate name: LPSPI9*/
571 kCLOCK_LPSpi10 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 8), /*!< Clock gate name: LPSPI10*/
572 kCLOCK_LPSpi11 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 9), /*!< Clock gate name: LPSPI11*/
573 kCLOCK_LPSpi12 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 10), /*!< Clock gate name: LPSPI12*/
574 kCLOCK_LPSpi13 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 11), /*!< Clock gate name: LPSPI13*/
575 kCLOCK_Sai0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 13), /*!< Clock gate name: SAI0*/
576 kCLOCK_Sai1 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 14), /*!< Clock gate name: SAI1*/
577 kCLOCK_Sai2 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 15), /*!< Clock gate name: SAI2*/
578 kCLOCK_I3c0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 16), /*!< Clock gate name: I3C0*/
579 kCLOCK_I3c1 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 17), /*!< Clock gate name: I3C1*/
580 kCLOCK_Crc0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 18), /*!< Clock gate name: CRC0*/
581 kCLOCK_Wwdt0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 19), /*!< Clock gate name: WWDT0*/
582 kCLOCK_Wwdt1 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 20), /*!< Clock gate name: WWDT1*/
583 kCLOCK_Ct32b0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 21), /*!< Clock gate name: CTIMER0*/
584 kCLOCK_Ct32b1 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 22), /*!< Clock gate name: CTIMER1*/
585 kCLOCK_Ct32b2 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 23), /*!< Clock gate name: CTIMER2*/
586 kCLOCK_Ct32b3 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 24), /*!< Clock gate name: CTIMER3*/
587 kCLOCK_Ct32b4 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 25), /*!< Clock gate name: CTIMER4*/
588 kCLOCK_Mrt0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 26), /*!< Clock gate name: Mrt0*/
589 kCLOCK_Utick0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 27), /*!< Clock gate name: Utick0*/
590 kCLOCK_Sema424 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 30), /*!< Clock gate name: SEMA42_4*/
591 kCLOCK_Mu4 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 31), /*!< Clock gate name: MU4*/
592 #if defined(FSL_CLOCK_DRIVER_COMPUTE)
593 kCLOCK_Pint = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL3, 5), /*!< Clock gate name: PINT0*/
594 kCLOCK_InputMux = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL3, 10), /*!< Clock gate name: PMUX_CMPT_SPLITTER*/
595 #endif
596 kCLOCK_Freqme0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL3, 8), /*!< Clock gate name: FREQME0*/
597 kCLOCK_SafoSgi = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL3, 12), /*!< Clock gate name: SAFO_SGI*/
598 kCLOCK_Trace = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL3, 13), /*!< Clock gate name: TRACE*/
599 kCLOCK_Prince0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL3, 15), /*!< Clock gate name: PRINCE0*/
600 kCLOCK_Prince1 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL3, 16), /*!< Clock gate name: PRINCE1*/
601 kCLOCK_PrinceExe = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL3, 17), /*!< Clock gate name: PRINCE_EXE*/
602 kCLOCK_Syspm0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL3, 18), /*!< Clock gate name: CMX_PERFMON0*/
603 kCLOCK_Syspm1 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL3, 19), /*!< Clock gate name: CMX_PERFMON1*/
604 kCLOCK_Hifi4 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL4, 0), /*!< Clock gate name: HIFI4*/
605 kCLOCK_Npu0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL5, 0), /*!< Clock gate name: NPU0*/
606 kCLOCK_CompAccessRamArbiter1 =
607 CLK_GATE_DEFINE(CLK_CTL0_PSCCTL5, 2), /*!< Clock gate name: COMP_ACCESS_RAM_ARBITER1*/
608 kCLOCK_Iopctl0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL5, 3), /*!< Clock gate name: IOMUXC_VDD2*/
609 kCLOCK_Hifi4AccessRamArbiter1 =
610 CLK_GATE_DEFINE(CLK_CTL0_PSCCTL5, 4), /*!< Clock gate name: HIFI4_ACCESS_RAM_ARBITER1*/
611 kCLOCK_MediaAccessRamArbiter0 =
612 CLK_GATE_DEFINE(CLK_CTL0_PSCCTL5, 5), /*!< Clock gate name: MEDIA_ACCESS_RAM_ARBITER0*/
613
614 kCLOCK_Sleepcon1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 6), /*!< Clock gate name: SLEEPCONCPU1*/
615 kCLOCK_Syscon1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 7), /*!< Clock gate name: SYSCONSENSE1*/
616 kCLOCK_SenseAccessRamArbiter0 =
617 CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 0), /*!< Clock gate name: SENSE_ACCESS_RAM_ARBITER0*/
618 kCLOCK_Hifi1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 1), /*!< Clock gate name: HIFI1*/
619 kCLOCK_Dma2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 4), /*!< Clock gate name: DMA2*/
620 kCLOCK_Dma3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 5), /*!< Clock gate name: DMA3*/
621 kCLOCK_LPFlexComm17 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 6), /*!< Clock gate name: LP_Flexcomm17*/
622 kCLOCK_LPFlexComm18 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 7), /*!< Clock gate name: LP_Flexcomm18*/
623 kCLOCK_LPFlexComm19 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 8), /*!< Clock gate name: LP_Flexcomm19*/
624 kCLOCK_LPFlexComm20 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 9), /*!< Clock gate name: LP_Flexcomm20*/
625 kCLOCK_LPI2c17 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 6), /*!< Clock gate name: LPI2C17*/
626 kCLOCK_LPI2c18 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 7), /*!< Clock gate name: LPI2C18*/
627 kCLOCK_LPI2c19 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 8), /*!< Clock gate name: LPI2C19*/
628 kCLOCK_LPI2c20 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 9), /*!< Clock gate name: LPI2C20*/
629 kCLOCK_LPSpi17 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 6), /*!< Clock gate name: LPSPI17*/
630 kCLOCK_LPSpi18 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 7), /*!< Clock gate name: LPSPI18*/
631 kCLOCK_LPSpi19 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 8), /*!< Clock gate name: LPSPI19*/
632 kCLOCK_LPSpi20 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 9), /*!< Clock gate name: LPSPI20*/
633 kCLOCK_LPUart17 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 6), /*!< Clock gate name: LPUART17*/
634 kCLOCK_LPUart18 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 7), /*!< Clock gate name: LPUART18*/
635 kCLOCK_LPUart19 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 8), /*!< Clock gate name: LPUART19*/
636 kCLOCK_LPUart20 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 9), /*!< Clock gate name: LPUART20*/
637 kCLOCK_Sai3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 10), /*!< Clock gate name: SAI3*/
638 kCLOCK_I3c2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 11), /*!< Clock gate name: I3C2*/
639 kCLOCK_I3c3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 12), /*!< Clock gate name: I3C3*/
640 kCLOCK_Gpio8 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 13), /*!< Clock gate name: GPIO8*/
641 kCLOCK_Gpio9 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 14), /*!< Clock gate name: GPIO9*/
642 kCLOCK_Gpio10 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 15), /*!< Clock gate name: GPIO10*/
643 #if defined(FSL_CLOCK_DRIVER_SENSE)
644 kCLOCK_Pint = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 16), /*!< Clock gate name: PINT1*/
645 kCLOCK_InputMux = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 30), /*!< Clock gate name: PMUX_SNS_SPLITTER*/
646 #endif
647 kCLOCK_Ct32b5 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 17), /*!< Clock gate name: CTIMER5*/
648 kCLOCK_Ct32b6 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 18), /*!< Clock gate name: CTIMER6*/
649 kCLOCK_Ct32b7 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 19), /*!< Clock gate name: CTIMER7*/
650 kCLOCK_Mrt1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 20), /*!< Clock gate name: Mrt1*/
651 kCLOCK_Utick1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 21), /*!< Clock gate name: Utick1*/
652 kCLOCK_Cdog3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 22), /*!< Clock gate name: CDOG3*/
653 kCLOCK_Cdog4 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 23), /*!< Clock gate name: CDOG4*/
654 kCLOCK_Mu3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 24), /*!< Clock gate name: MU3*/
655 kCLOCK_Sema423 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 25), /*!< Clock gate name: SEMA42_3*/
656 kCLOCK_Wwdt2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 26), /*!< Clock gate name: WWDT2*/
657 kCLOCK_Wwdt3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 27), /*!< Clock gate name: WWDT3*/
658
659 kCLOCK_Syscon2 = CLK_GATE_DEFINE(CLK_CTL2_PSCCTL0, 3), /*!< Clock gate name: SYSCON_COMM */
660 kCLOCK_Iopctl2 = CLK_GATE_DEFINE(CLK_CTL2_PSCCTL0, 4), /*!< Clock gate name: IOMUXC_VDDN */
661
662 kCLOCK_Cpu1 = CLK_GATE_DEFINE(CLK_CTL3_PSCCTL0, 0), /*!< Clock gate name: CPU1*/
663 kCLOCK_Mu0 = CLK_GATE_DEFINE(CLK_CTL3_PSCCTL0, 4), /*!< Clock gate name: MU0*/
664 kCLOCK_Mu1 = CLK_GATE_DEFINE(CLK_CTL3_PSCCTL0, 5), /*!< Clock gate name: MU1*/
665 kCLOCK_Mu2 = CLK_GATE_DEFINE(CLK_CTL3_PSCCTL0, 6), /*!< Clock gate name: MU2*/
666 kCLOCK_OsTimer = CLK_GATE_DEFINE(CLK_CTL3_PSCCTL0, 7), /*!< Clock gate name: OsTimer*/
667 kCLOCK_Sema420 = CLK_GATE_DEFINE(CLK_CTL3_PSCCTL0, 8), /*!< Clock gate name: SEMA42_0*/
668 kCLOCK_Sdadc0 = CLK_GATE_DEFINE(CLK_CTL3_PSCCTL0, 9), /*!< Clock gate name: SDADC0*/
669 kCLOCK_Adc0 = CLK_GATE_DEFINE(CLK_CTL3_PSCCTL0, 10), /*!< Clock gate name: SARADC0*/
670 kCLOCK_Acmp0 = CLK_GATE_DEFINE(CLK_CTL3_PSCCTL0, 11), /*!< Clock gate name: Acmp0*/
671 kCLOCK_Pdm = CLK_GATE_DEFINE(CLK_CTL3_PSCCTL0, 12), /*!< Clock gate name: MICFIL(PDM)*/
672 kCLOCK_Glikey4 = CLK_GATE_DEFINE(CLK_CTL3_PSCCTL0, 13), /*!< Clock gate name: GLIKEY_SYSCON1*/
673 kCLOCK_Dbg = CLK_GATE_DEFINE(CLK_CTL3_PSCCTL0, 20), /*!< Clock gate name: DBG*/
674 kCLOCK_Syscon3 = CLK_GATE_DEFINE(CLK_CTL3_PSCCTL0, 21), /*!< Clock gate name: SYSCON_SENSE0*/
675 kCLOCK_Iopctl1 = CLK_GATE_DEFINE(CLK_CTL3_PSCCTL0, 22), /*!< Clock gate name: IOMUXC_VDD1*/
676 kCLOCK_Glikey1 = CLK_GATE_DEFINE(CLK_CTL3_PSCCTL0, 23), /*!< Clock gate name: GLIKEY1*/
677 kCLOCK_LPI2c15 = CLK_GATE_DEFINE(CLK_CTL3_PSCCTL0, 24), /*!< Clock gate name: LPI2C*/
678 kCLOCK_MediaAccessRamArbiter1 =
679 CLK_GATE_DEFINE(CLK_CTL3_PSCCTL0, 25), /*!< Clock gate name: MEDIA_ACCESS_RAM_ARBITER1*/
680 kCLOCK_Axi0 = CLK_GATE_DEFINE(CLK_CTL4_PSCCTL0, 0), /*!< Clock gate name: AXI0*/
681 kCLOCK_Gpu = CLK_GATE_DEFINE(CLK_CTL4_PSCCTL0, 2), /*!< Clock gate name: VGPU*/
682 kCLOCK_MipiDsiCtrl = CLK_GATE_DEFINE(CLK_CTL4_PSCCTL0, 4), /*!< Clock gate name: MIPIDSI*/
683 kCLOCK_LPSpi16 = CLK_GATE_DEFINE(CLK_CTL4_PSCCTL0, 5), /*!< Clock gate name: LPSPI16*/
684 kCLOCK_LPSpi14 = CLK_GATE_DEFINE(CLK_CTL4_PSCCTL0, 6), /*!< Clock gate name: LPSPI14*/
685 kCLOCK_Xspi2 = CLK_GATE_DEFINE(CLK_CTL4_PSCCTL0, 8), /*!< Clock gate name: XSPI2*/
686 kCLOCK_Mmu2 = CLK_GATE_DEFINE(CLK_CTL4_PSCCTL0, 11), /*!< Clock gate name: MMU2*/
687 kCLOCK_Glikey5 = CLK_GATE_DEFINE(CLK_CTL4_PSCCTL0, 13), /*!< Clock gate name: GLIKEY_SYSCON2*/
688 kCLOCK_Flexio = CLK_GATE_DEFINE(CLK_CTL4_PSCCTL0, 15), /*!< Clock gate name: FLEXIO0*/
689 kCLOCK_Lcdif = CLK_GATE_DEFINE(CLK_CTL4_PSCCTL0, 22), /*!< Clock gate name: LCDIF(DCN)*/
690 kCLOCK_Syscon4 = CLK_GATE_DEFINE(CLK_CTL4_PSCCTL0, 23), /*!< Clock gate name: SYSCONMEDIA*/
691 kCLOCK_JpgDecoder = CLK_GATE_DEFINE(CLK_CTL4_PSCCTL0, 24), /*!< Clock gate name: JPG_DECODER*/
692 kCLOCK_PngDecoder = CLK_GATE_DEFINE(CLK_CTL4_PSCCTL0, 25), /*!< Clock gate name: PNG_DECODER*/
693 kCLOCK_Ezhv = CLK_GATE_DEFINE(CLK_CTL4_PSCCTL0, 26), /*!< Clock gate name: EZHV*/
694 kCLOCK_AxbsEzh = CLK_GATE_DEFINE(CLK_CTL4_PSCCTL0, 28), /*!< Clock gate name: AXBS_EZH*/
695 kCLOCK_Glikey2 = CLK_GATE_DEFINE(CLK_CTL4_PSCCTL0, 29), /*!< Clock gate name: GLIKEY2*/
696 kCLOCK_Usb0 = CLK_GATE_DEFINE(CLK_CTL4_PSCCTL1, 0), /*!< Clock gate name: USB0*/
697 kCLOCK_Usb1 = CLK_GATE_DEFINE(CLK_CTL4_PSCCTL1, 2), /*!< Clock gate name: USB1*/
698 kCLOCK_Usdhc0 = CLK_GATE_DEFINE(CLK_CTL4_PSCCTL1, 4), /*!< Clock gate name: USHDC0*/
699 kCLOCK_Usdhc1 = CLK_GATE_DEFINE(CLK_CTL4_PSCCTL1, 5), /*!< Clock gate name: USDHC1*/
700
701 /* Control bits in SYSCON. */
702 #if defined(FSL_CLOCK_DRIVER_COMPUTE)
703 kCLOCK_Gdet0Ref = CLK_GATE_DEFINE(SYSCON0_SEC_CLK_CTRL, 0), /*!< Clock gate name: GDET0 Reference clock*/
704 kCLOCK_Gdet1Ref = CLK_GATE_DEFINE(SYSCON0_SEC_CLK_CTRL, 1), /*!< Clock gate name: GDET1 Reference clock*/
705 kCLOCK_TrngRef = CLK_GATE_DEFINE(SYSCON0_SEC_CLK_CTRL, 2), /*!< Clock gate name: TRNG Reference clock*/
706 kCLOCK_Els = CLK_GATE_DEFINE(SYSCON0_SEC_CLK_CTRL, 3), /*!< Clock gate name: ELS clock*/
707 kCLOCK_ItrcRef = CLK_GATE_DEFINE(SYSCON0_SEC_CLK_CTRL, 4), /*!< Clock gate name: ITRC Reference clock*/
708
709 kCLOCK_Gdet0 = CLK_GATE_DEFINE(CLKCTL0_ONE_SRC_CLKSLICE_ENABLE, 0U), /*!< Clock gate name: GDET0. */
710 kCLOCK_Gdet1 = CLK_GATE_DEFINE(CLKCTL0_ONE_SRC_CLKSLICE_ENABLE, 1U), /*!< Clock gate name: GDET1. */
711 #endif
712 kCLOCK_Gdet2Ref = CLK_GATE_DEFINE(SYSCON3_SEC_CLK_CTRL, 0), /*!< Clock gate name: GDET2 Reference clock*/
713 kCLOCK_Gdet3Ref = CLK_GATE_DEFINE(SYSCON3_SEC_CLK_CTRL, 1), /*!< Clock gate name: GDET3 Reference clock*/
714
715 kCLOCK_Rtc = CLK_GATE_DEFINE(CLKCTL3_ONE_SRC_CLKSLICE_ENABLE, 0U), /*!< RTC functional clock gating. */
716 kCLOCK_Gdet2 = CLK_GATE_DEFINE(CLKCTL3_ONE_SRC_CLKSLICE_ENABLE, 1U), /*!< GDET2 functional clock gating. */
717 kCLOCK_Gdet3 = CLK_GATE_DEFINE(CLKCTL3_ONE_SRC_CLKSLICE_ENABLE, 2U), /*!< GDET3 functional clock gating. */
718 kCLOCK_UsbphyRef = CLK_GATE_DEFINE(CLKCTL4_ONE_SRC_CLKSLICE_ENABLE, 0U), /*!< USBPHY referrence clock gating. */
719 } clock_ip_name_t;
720
721 /*! @brief Clock name used to get clock frequency. */
722 typedef enum _clock_name
723 {
724 kCLOCK_CoreSysClk, /*!< Core clock (aka system clock) */
725 kCLOCK_BusClk, /*!< Bus clock (AHB/APB clock, aka HCLK) */
726 kCLOCK_MclkClk, /*!< MCLK, to MCLK pin */
727 #if defined(FSL_CLOCK_DRIVER_COMPUTE)
728 kCLOCK_Vdd2ClockOutClk, /*!< VDD2 CLOCKOUT */
729 kCLOCK_Xspi0Clk, /*!< XSPI0 */
730 kCLOCK_Xspi1Clk, /*!< XSPI1 */
731 kCLOCK_Wdt0Clk, /*!< Watchdog0 */
732 kCLOCK_Wdt1Clk, /*!< Watchdog1 */
733 kCLOCK_Hifi4CpuClk, /*!< Hifi4 DSP clock */
734 kCLOCK_LPFlexComm0Clk, /*!< Flexcomm0Clock */
735 kCLOCK_LPFlexComm1Clk, /*!< Flexcomm1Clock */
736 kCLOCK_LPFlexComm2Clk, /*!< Flexcomm2Clock */
737 kCLOCK_LPFlexComm3Clk, /*!< Flexcomm3Clock */
738 kCLOCK_LPFlexComm4Clk, /*!< Flexcomm4Clock */
739 kCLOCK_LPFlexComm5Clk, /*!< Flexcomm5Clock */
740 kCLOCK_LPFlexComm6Clk, /*!< Flexcomm6Clock */
741 kCLOCK_LPFlexComm7Clk, /*!< Flexcomm7Clock */
742 kCLOCK_LPFlexComm8Clk, /*!< Flexcomm8Clock */
743 kCLOCK_LPFlexComm9Clk, /*!< Flexcomm9Clock */
744 kCLOCK_LPFlexComm10Clk, /*!< Flexcomm10Clock */
745 kCLOCK_LPFlexComm11Clk, /*!< Flexcomm11Clock */
746 kCLOCK_LPFlexComm12Clk, /*!< Flexcomm12Clock */
747 kCLOCK_LPFlexComm13Clk, /*!< Flexcomm13Clock */
748 #else
749 kCLOCK_Wdt2Clk, /*!< Watchdog1 */
750 kCLOCK_Wdt3Clk, /*!< Watchdog1 */
751 kCLOCK_Hifi1CpuClk, /*!< Hifi1 DSP clock */
752 kCLOCK_LPFlexComm17Clk, /*!< Flexcomm17Clock */
753 kCLOCK_LPFlexComm18Clk, /*!< Flexcomm18Clock */
754 kCLOCK_LPFlexComm19Clk, /*!< Flexcomm19Clock */
755 kCLOCK_LPFlexComm20Clk, /*!< Flexcomm20Clock */
756 #endif
757 kCLOCK_Vdd1ClockOutClk, /*!< VDD1 CLOCKOUT */
758 kCLOCK_AdcClk, /*!< ADC */
759 kCLOCK_Xspi2Clk, /*!< XSPI1 */
760 kCLOCK_SctClk, /*!< SCT */
761 kCLOCK_SystickClk, /*!< Systick */
762 kCLOCK_Sdio0Clk, /*!< SDIO0 */
763 kCLOCK_Sdio1Clk, /*!< SDIO1 */
764 kCLOCK_I3cClk, /*!< I3C */
765 kCLOCK_Usb0Clk, /*!< USB0 */
766 kCLOCK_Usb1Clk, /*!< USB1 */
767 kCLOCK_PdmClk, /*!< Digital Mic clock */
768 kCLOCK_AcmpClk, /*!< Acmp clock */
769 kCLOCK_FlexioClk, /*!< FlexIO */
770 kCLOCK_LPSpi14Clk, /*!< LPSPI14 */
771 kCLOCK_LPI2c15Clk, /*!< LPI2C15 */
772 kCLOCK_LPSpi16Clk, /*!< LPSPI16 */
773 kCLOCK_VgpuClk, /*!< VGPU Core */
774 kCLOCK_LcdifClk, /*!< LCDIF Clock */
775 kCLOCK_MipiDphyClk, /*!< MIPI D-PHY Bit Clock */
776 kCLOCK_MipiDphyEscRxClk, /*!< MIPI D-PHY RX Clock */
777 kCLOCK_MipiDphyEscTxClk, /*!< MIPI D-PHY TX Clock */
778 } clock_name_t;
779
780 /*! @brief Clock Mux Switches
781 * The encoding is as follows each connection identified is 32bits wide
782 * starting from LSB upwards
783 *
784 * [ 31-29 14 12:11 10:0 ]
785 [CLKCTL index]: [Disable MUX output]: [MUXA choice]:[MUXA offset]. MUX offset 0 means end of
786 descriptor.
787 */
788 #define CLK_MUX_INST_INDEX_SHIFT 29U
789 #define CLK_MUX_CHOICE_OFFSET_SHIFT 11U
790 #define CLK_MUX_DISABLE_OUTPUT_MASK (1UL << 14U)
791
792 /* CLKCTL0 CLKCTL_COM_VDD2*/
793 #if defined(FSL_CLOCK_DRIVER_COMPUTE)
794 #define CMPTMAINCLKDIV_OFFSET 0x400
795 #define CMPTBASECLKSEL_OFFSET 0x420
796 #define DSPBASECLKSEL_OFFSET 0x424
797 #define VDD2COMBASECLKSEL_OFFSET 0x428
798 #define MAINCLKSEL_OFFSET 0x434
799 #define DSPCPUCLKDIV_OFFSET 0x440
800 #define DSPCPUCLKSEL_OFFSET 0x444
801 #define RAMCLKSEL_OFFSET 0x450
802 #define RAMCLKDIV_OFFSET 0x45C
803 #define TPIUFCLKSEL_OFFSET 0x560
804 #define TPIUCLKDIV_OFFSET 0x564
805 #define XSPI0FCLKSEL_OFFSET 0x600
806 #define XSPI0FCLKDIV_OFFSET 0x604
807 #define XSPI1FCLKSEL_OFFSET 0x620
808 #define XSPI1FCLKDIV_OFFSET 0x624
809 #define SCTFCLKSEL_OFFSET 0x640
810 #define SCTFCLKDIV_OFFSET 0x644
811 #define UTICK0FCLKSEL_OFFSET 0x700
812 #define UTICK0CLKDIV_OFFSET 0x704
813 #define WWDT0FCLKSEL_OFFSET 0x720
814 #define WWDT1FCLKSEL_OFFSET 0x740
815 #define SYSTICKFCLKSEL_OFFSET 0x760
816 #define SYSTICKFCLKDIV_OFFSET 0x764
817 #define FCCLK0SEL_OFFSET 0x800
818 #define FC0FCLKSEL_OFFSET 0x808
819 #define FCCLK1SEL_OFFSET 0x820
820 #define FC1FCLKSEL_OFFSET 0x828
821 #define FCCLK2SEL_OFFSET 0x840
822 #define FC2FCLKSEL_OFFSET 0x848
823 #define FCCLK3SEL_OFFSET 0x860
824 #define FC3FCLKSEL_OFFSET 0x868
825 #define FC4FCLKSEL_OFFSET 0x888
826 #define FC5FCLKSEL_OFFSET 0x8A8
827 #define FC6FCLKSEL_OFFSET 0x8C8
828 #define FC7FCLKSEL_OFFSET 0x8E8
829 #define FC8FCLKSEL_OFFSET 0x908
830 #define FC9FCLKSEL_OFFSET 0x928
831 #define FC10FCLKSEL_OFFSET 0x948
832 #define FC11FCLKSEL_OFFSET 0x968
833 #define FC12FCLKSEL_OFFSET 0x988
834 #define FC13FCLKSEL_OFFSET 0x9A8
835 #define FCCLK0DIV_OFFSET 0x804
836 #define FCCLK1DIV_OFFSET 0x824
837 #define FCCLK2DIV_OFFSET 0x844
838 #define FCCLK3DIV_OFFSET 0x864
839 #define SAI012FCLKSEL_OFFSET 0x9C8
840 #define SAI012CLKDIV_OFFSET 0x9CC
841 #define CTIMER0CLKDIV_OFFSET 0xA00
842 #define CTIMER1CLKDIV_OFFSET 0xA04
843 #define CTIMER2CLKDIV_OFFSET 0xA08
844 #define CTIMER3CLKDIV_OFFSET 0xA0C
845 #define CTIMER4CLKDIV_OFFSET 0xA10
846 #define CTIMER0FCLKSEL_OFFSET 0xAA0
847 #define CTIMER1FCLKSEL_OFFSET 0xAA4
848 #define CTIMER2FCLKSEL_OFFSET 0xAA8
849 #define CTIMER3FCLKSEL_OFFSET 0xAAC
850 #define CTIMER4FCLKSEL_OFFSET 0xAB0
851 #define TRNGFCLKSEL_OFFSET 0xAC0
852 #define TRNGFCLKDIV_OFFSET 0xAC4
853 #define I3C01FCLKSEL_OFFSET 0xB00
854 #define I3C01PCLKSEL_OFFSET 0xB04
855 #define I3C01PCLKDIV_OFFSET 0xB08
856 #define I3C01FCLKDIV_OFFSET 0xB10
857 #define CLKOUTCLKSEL_OFFSET 0xB20
858 #define CLKOUTCLKDIV_OFFSET 0xB24
859 #define AUDIOVDD2CLKSEL_OFFSET 0xB30
860
861 #else
862
863 #define SENSEBASECLKSEL_OFFSET 0x438
864 #define SENSEDSPCPUCLKDIV_OFFSET 0x440
865 #define SENSEDSPCPUCLKSEL_OFFSET 0x444
866 #define SAI3FCLKSEL_OFFSET 0x500
867 #define SAI3CLKDIV_OFFSET 0x504
868 #define UTICK1FCLKSEL_OFFSET 0x700
869 #define UTICK1CLKDIV_OFFSET 0x704
870 #define WWDT2FCLKSEL_OFFSET 0x720
871 #define WWDT3FCLKSEL_OFFSET 0x740
872 #define SYSTICKFCLKSEL_OFFSET 0x760
873 #define SYSTICKFCLKDIV_OFFSET 0x764
874 #define CTIMER5FCLKSEL_OFFSET 0x7A0
875 #define CTIMER6FCLKSEL_OFFSET 0x7A4
876 #define CTIMER7FCLKSEL_OFFSET 0x7A8
877 #define CTIMER5CLKDIV_OFFSET 0x7B0
878 #define CTIMER6CLKDIV_OFFSET 0x7B4
879 #define CTIMER7CLKDIV_OFFSET 0x7B8
880 #define I3C23FCLKSEL_OFFSET 0x800
881 #define I3C23FCLKDIV_OFFSET 0x810
882 #define FC17FCLKSEL_OFFSET 0xA00
883 #define FC18FCLKSEL_OFFSET 0xA20
884 #define FC19FCLKSEL_OFFSET 0xA40
885 #define FC20FCLKSEL_OFFSET 0xA60
886 #define FC17FCLKDIV_OFFSET 0xA04
887 #define FC18FCLKDIV_OFFSET 0xA24
888 #define FC19FCLKDIV_OFFSET 0xA44
889 #define FC20FCLKDIV_OFFSET 0xA64
890 #define AUDIOVDD1CLKSEL_OFFSET 0xAA0
891 #endif
892
893 /* CLKCTL2 */
894 #define USBCLKSRC24MCLKSEL_OFFSET 0x10C
895 #define COMMONVDDNCLKSEL_OFFSET 0xA4
896 #define COMMONVDDNCLKDIV_OFFSET 0xAC
897 #define USBCLKSRC24MCLKSEL_OFFSET 0x10C
898 #define COMNBASECLKSEL_OFFSET 0x110
899 #define EUSBCLKSRC24MCLKSEL_OFFSET 0x11C
900 #define MAINPLL0CLKSEL_OFFSET 0x200
901 #define MAINPLL0LOCKTIMEDIV2_OFFSET 0x20C
902 #define AUDIOPLL0CLKSEL_OFFSET 0x400
903 #define AUDIOPLL0LOCKTIMEDIV2_OFFSET 0x40C
904
905 /* CLKCTL3 CLKCTL_VDD1_COM */
906 #define SENSEMAINCLKDIV_OFFSET 0x400
907 #define SENSE_MAINCLKSEL_OFFSET 0x434
908 #define SENSERAMCLKSEL_OFFSET 0x450
909 #define SENSERAMCLKDIV_OFFSET 0x45C
910 #define OSEVENTTFCLKSEL_OFFSET 0x480
911 #define OSEVENTFCLKDIV_OFFSET 0x484
912 #define SDADCFCLKSEL_OFFSET 0x600
913 #define SDADCFCLKDIV_OFFSET 0x604
914 #define SARADCFCLKSEL_OFFSET 0x620
915 #define SARADCFCLKDIV_OFFSET 0x624
916 #define WAKE32KCLKSEL_OFFSET 0x750
917 #define A32KHZWAKECLKDIV_OFFSET 0x754
918 #define MICFIL0FCLKSEL_OFFSET 0x780
919 #define MICFIL0FCLKDIV_OFFSET 0x784
920 #define LPI2CFCLKSEL_OFFSET 0x788
921 #define LPI2CFCLKDIV_OFFSET 0x78C
922 #define SENSE_CLKOUTCLKSEL_OFFSET 0x800
923 #define SENSE_CLKOUTCLKDIV_OFFSET 0x804
924
925 /* CLKCTL4 CLKCTL_MED_VDD2 */
926 #define MEDIAVDDNCLKSEL_OFFSET 0xA4
927 #define MEDIAVDDNCLKDIV_OFFSET 0xAC
928 #define MEDIAMAINCLKSEL_OFFSET 0x104
929 #define MEDIAMAINCLKDIV_OFFSET 0x10C
930 #define MDNBASECLKSEL_OFFSET 0x110
931 #define MD2BASECLKSEL_OFFSET 0x114
932 #define XSPI2FCLKSEL_OFFSET 0x200
933 #define XSPI2FCLKDIV_OFFSET 0x204
934 #define USBFCLKSEL_OFFSET 0x220
935 #define EUSBFCLKSEL_OFFSET 0x240
936 #define SDIO0FCLKSEL_OFFSET 0x260
937 #define SDIO0FCLKDIV_OFFSET 0x264
938 #define SDIO1FCLKSEL_OFFSET 0x280
939 #define SDIO1FCLKDIV_OFFSET 0x284
940 #define DPHYCLKSEL_OFFSET 0x300
941 #define DPHYCLKDIV_OFFSET 0x304
942 #define DPHYESCCLKSEL_OFFSET 0x308
943 #define DPHYESCRXCLKDIV_OFFSET 0x30C
944 #define DPHYESCTXCLKDIV_OFFSET 0x310
945 #define VGPUCLKSEL_OFFSET 0x320
946 #define VGPUCLKDIV_OFFSET 0x324
947 #define LPSPI14CLKSEL_OFFSET 0x328
948 #define LPSPI14CLKDIV_OFFSET 0x32C
949 #define LPSPI16CLKSEL_OFFSET 0x330
950 #define LPSPI16CLKDIV_OFFSET 0x334
951 #define FLEXIOCLKSEL_OFFSET 0x338
952 #define FLEXIOCLKDIV_OFFSET 0x33C
953 #define LCDIFPIXELCLKSEL_OFFSET 0x340
954 #define LCDIFPIXELCLKDIV_OFFSET 0x344
955 #define LOWFREQCLKDIV_OFFSET 0x700
956
957 #define CLKCTL0_INDEX (0UL << CLK_MUX_INST_INDEX_SHIFT)
958 #define CLKCTL1_INDEX (1UL << CLK_MUX_INST_INDEX_SHIFT)
959 #define CLKCTL2_INDEX (2UL << CLK_MUX_INST_INDEX_SHIFT)
960 #define CLKCTL3_INDEX (3UL << CLK_MUX_INST_INDEX_SHIFT)
961 #define CLKCTL4_INDEX (4UL << CLK_MUX_INST_INDEX_SHIFT)
962
963 #define CLKCTL0_TUPLE_MUXA(reg, choice) ((((reg) >> 2U) & 0x7FFU) | (((choice) & 0x3U) << CLK_MUX_CHOICE_OFFSET_SHIFT))
964 #define CLKCTL1_TUPLE_MUXA(reg, choice) \
965 (CLKCTL1_INDEX | (((reg) >> 2U) & 0x7FFU) | (((choice) & 0x3U) << CLK_MUX_CHOICE_OFFSET_SHIFT))
966 #define CLKCTL2_TUPLE_MUXA(reg, choice) \
967 (CLKCTL2_INDEX | (((reg) >> 2U) & 0x7FFU) | (((choice) & 0x3U) << CLK_MUX_CHOICE_OFFSET_SHIFT))
968 #define CLKCTL3_TUPLE_MUXA(reg, choice) \
969 (CLKCTL3_INDEX | (((reg) >> 2U) & 0x7FFU) | (((choice) & 0x3U) << CLK_MUX_CHOICE_OFFSET_SHIFT))
970 #define CLKCTL4_TUPLE_MUXA(reg, choice) \
971 (CLKCTL4_INDEX | (((reg) >> 2U) & 0x7FFU) | (((choice) & 0x3U) << CLK_MUX_CHOICE_OFFSET_SHIFT))
972 /*! Macro for gated clock mux */
973 #define CLKCTL0_TUPLE_MUXA_NONE(reg, choice) (CLKCTL0_TUPLE_MUXA(reg, choice) | CLK_MUX_DISABLE_OUTPUT_MASK)
974 #define CLKCTL1_TUPLE_MUXA_NONE(reg, choice) (CLKCTL1_TUPLE_MUXA(reg, choice) | CLK_MUX_DISABLE_OUTPUT_MASK)
975 #define CLKCTL2_TUPLE_MUXA_NONE(reg, choice) (CLKCTL2_TUPLE_MUXA(reg, choice) | CLK_MUX_DISABLE_OUTPUT_MASK)
976 #define CLKCTL3_TUPLE_MUXA_NONE(reg, choice) (CLKCTL3_TUPLE_MUXA(reg, choice) | CLK_MUX_DISABLE_OUTPUT_MASK)
977 #define CLKCTL4_TUPLE_MUXA_NONE(reg, choice) (CLKCTL4_TUPLE_MUXA(reg, choice) | CLK_MUX_DISABLE_OUTPUT_MASK)
978
979 #define CLKCTL_TUPLE_REG(base, tuple) ((volatile uint32_t *)(((uint32_t)(base)) + (((uint32_t)(tuple) & 0x7FFU) << 2U)))
980 #define CLKCTL_TUPLE_SEL(tuple) (((uint32_t)(tuple) >> CLK_MUX_CHOICE_OFFSET_SHIFT) & 0x3U)
981
982 /*!
983 * @brief The enumerator of clock attach Id for multi sources clock slices. Not all Muxer has MUX output enable control,
984 * if no mux output enable control, the mux output will be always enabled.
985 */
986 typedef enum _clock_attach_id
987 {
988 #if defined(FSL_CLOCK_DRIVER_COMPUTE)
989 kFRO1_DIV3_to_COMPUTE_BASE =
990 CLKCTL0_TUPLE_MUXA(CMPTBASECLKSEL_OFFSET, 0), /*!< Attach Fro1 Divided-by-3 to Compute Base Clock. */
991 kFRO1_DIV1_to_COMPUTE_BASE =
992 CLKCTL0_TUPLE_MUXA(CMPTBASECLKSEL_OFFSET, 1), /*!< Attach Fro1 Divided-by-1 to Compute Base Clock. */
993 kFRO0_DIV3_to_COMPUTE_BASE =
994 CLKCTL0_TUPLE_MUXA(CMPTBASECLKSEL_OFFSET, 2), /*!< Attach Fro0 Divided-by-3 to Compute Base Clock. */
995 kLPOSC_to_COMPUTE_BASE = CLKCTL0_TUPLE_MUXA(CMPTBASECLKSEL_OFFSET, 3), /*!< Attach LPOSC to Compute Base Clock. */
996
997 kFRO1_DIV3_to_DSP_BASE =
998 CLKCTL0_TUPLE_MUXA(DSPBASECLKSEL_OFFSET, 0), /*!< Attach Fro1 Divided-by-3 to DSP Base Clock. */
999 kFRO1_DIV1_to_DSP_BASE =
1000 CLKCTL0_TUPLE_MUXA(DSPBASECLKSEL_OFFSET, 1), /*!< Attach Fro1 Divided-by-1 to DSP Base Clock. */
1001 kFRO0_DIV3_to_DSP_BASE =
1002 CLKCTL0_TUPLE_MUXA(DSPBASECLKSEL_OFFSET, 2), /*!< Attach Fro0 Divided-by-3 to DSP Base Clock. */
1003 kLPOSC_to_DSP_BASE = CLKCTL0_TUPLE_MUXA(DSPBASECLKSEL_OFFSET, 3), /*!< Attach LPOSC to DSP Base Clock. */
1004
1005 kFRO1_DIV3_to_COMMON_VDD2_BASE =
1006 CLKCTL0_TUPLE_MUXA(VDD2COMBASECLKSEL_OFFSET, 0), /*!< Attach Fro1 Divided-by-3 to VDD2_COM Base Clock. */
1007 kFRO1_DIV1_to_COMMON_VDD2_BASE =
1008 CLKCTL0_TUPLE_MUXA(VDD2COMBASECLKSEL_OFFSET, 1), /*!< Attach Fro1 Divided-by-1 to VDD2_COM Base Clock. */
1009 kFRO0_DIV3_to_COMMON_VDD2_BASE =
1010 CLKCTL0_TUPLE_MUXA(VDD2COMBASECLKSEL_OFFSET, 2), /*!< Attach Fro0 Divided-by-3 to VDD2_COM Base Clock. */
1011 kLPOSC_to_COMMON_VDD2_BASE =
1012 CLKCTL0_TUPLE_MUXA(VDD2COMBASECLKSEL_OFFSET, 3), /*!< Attach LPOSC to VDD2_COM Base Clock. */
1013
1014 kCOMPUTE_BASE_to_COMPUTE_MAIN =
1015 CLKCTL0_TUPLE_MUXA(MAINCLKSEL_OFFSET, 0), /*!< Attach Compute base clock to Compute Main Clock. */
1016 kMAIN_PLL_PFD0_to_COMPUTE_MAIN =
1017 CLKCTL0_TUPLE_MUXA(MAINCLKSEL_OFFSET, 1), /*!< Attach MAIN PLL PFD0 to Compute Main Clock. */
1018 kFRO0_DIV1_to_COMPUTE_MAIN =
1019 CLKCTL0_TUPLE_MUXA(MAINCLKSEL_OFFSET, 2), /*!< Attach FRO0 Max clock to Compute Main Clock. */
1020 kAUDIO_PLL_PFD1_to_COMPUTE_MAIN =
1021 CLKCTL0_TUPLE_MUXA(MAINCLKSEL_OFFSET, 3), /*!< Attach AUDIO_PLL_PFD1 to Compute Main Clock. */
1022
1023 kDSP_BASE_to_DSP = CLKCTL0_TUPLE_MUXA(DSPCPUCLKSEL_OFFSET, 0), /*!< Attach DSP base clock to DSP Clock. */
1024 kMAIN_PLL_PFD0_to_DSP = CLKCTL0_TUPLE_MUXA(DSPCPUCLKSEL_OFFSET, 1), /*!< Attach MAIN PLL PFD0 to DSP Clock. */
1025 kFRO0_DIV1_to_DSP = CLKCTL0_TUPLE_MUXA(DSPCPUCLKSEL_OFFSET, 2), /*!< Attach FRO0 Max clock to DSP Clock. */
1026 kMAIN_PLL_PFD1_to_DSP = CLKCTL0_TUPLE_MUXA(DSPCPUCLKSEL_OFFSET, 3), /*!< Attach MAIN PLL PFD1 to DSP Clock. */
1027 kNONE_to_DSP = CLKCTL0_TUPLE_MUXA_NONE(DSPCPUCLKSEL_OFFSET, 0), /*!< Attach NONE to DSP Clock. */
1028
1029 kCOMMON_VDD2_BASE_to_RAM = CLKCTL0_TUPLE_MUXA(RAMCLKSEL_OFFSET, 0), /*!< Attach baseclk_com2 clock to RAM Clock. */
1030 kMAIN_PLL_PFD0_to_RAM = CLKCTL0_TUPLE_MUXA(RAMCLKSEL_OFFSET, 1), /*!< Attach Main PLL PFD0 to RAM Clock. */
1031 kFRO0_DIV1_to_RAM = CLKCTL0_TUPLE_MUXA(RAMCLKSEL_OFFSET, 2), /*!< Attach FRO0 Max to RAM Clock. */
1032 kFRO1_DIV1_to_RAM = CLKCTL0_TUPLE_MUXA(RAMCLKSEL_OFFSET, 3), /*!< Attach FRO1 Max to RAM Clock. */
1033
1034 kCOMPUTE_BASE_to_TPIU = CLKCTL0_TUPLE_MUXA(
1035 TPIUFCLKSEL_OFFSET, 0), /*!< Attach Compute base clock to TPIU (TRACE_RT700) Functional Clock. */
1036 kMAIN_PLL_PFD0_to_TPIU =
1037 CLKCTL0_TUPLE_MUXA(TPIUFCLKSEL_OFFSET, 1), /*!< Attach main_pll_pfd0 to TPIU (TRACE_RT700) Functional Clock. */
1038 kFRO0_DIV1_to_TPIU =
1039 CLKCTL0_TUPLE_MUXA(TPIUFCLKSEL_OFFSET, 2), /*!< Attach FRO0 Max to TPIU (TRACE_RT700) Functional Clock. */
1040 kFRO0_DIV6_to_TPIU =
1041 CLKCTL0_TUPLE_MUXA(TPIUFCLKSEL_OFFSET, 3), /*!< Attach OSC_CLK clock to TPIU (TRACE_RT700) Functional Clock. */
1042 kNONE_to_TPIU =
1043 CLKCTL0_TUPLE_MUXA_NONE(TPIUFCLKSEL_OFFSET, 0), /*!< Attach NONE to TPIU (TRACE_RT700) Functional Clock. */
1044
1045 kCOMMON_BASE_to_XSPI0 =
1046 CLKCTL0_TUPLE_MUXA(XSPI0FCLKSEL_OFFSET, 0), /*!< Attach Common base clock to XSPI0 Functional Clock. */
1047 kAUDIO_PLL_PFD0_to_XSPI0 =
1048 CLKCTL0_TUPLE_MUXA(XSPI0FCLKSEL_OFFSET, 1), /*!< Attach Audio PLL PFD0 clock to XSPI0 Functional Clock. */
1049 kFRO0_DIV1_to_XSPI0 =
1050 CLKCTL0_TUPLE_MUXA(XSPI0FCLKSEL_OFFSET, 2), /*!< Attach FRO0 Max clock to XSPI0 Functional Clock. */
1051 kMAIN_PLL_PFD1_to_XSPI0 =
1052 CLKCTL0_TUPLE_MUXA(XSPI0FCLKSEL_OFFSET, 3), /*!< Attach MAIN PLL PFD1 clock to XSPI0 Functional Clock. */
1053 kNONE_to_XSPI0 = CLKCTL0_TUPLE_MUXA_NONE(XSPI0FCLKSEL_OFFSET, 0), /*!< Attach NONE to XSPI0 Functional Clock. */
1054
1055 kCOMMON_BASE_to_XSPI1 =
1056 CLKCTL0_TUPLE_MUXA(XSPI1FCLKSEL_OFFSET, 0), /*!< Attach Common base clock to XSPI1 Functional Clock. */
1057 kAUDIO_PLL_PFD1_to_XSPI1 =
1058 CLKCTL0_TUPLE_MUXA(XSPI1FCLKSEL_OFFSET, 1), /*!< Attach Audio PLL PFD1 clock to XSPI1 Functional Clock. */
1059 kFRO0_DIV1_to_XSPI1 =
1060 CLKCTL0_TUPLE_MUXA(XSPI1FCLKSEL_OFFSET, 2), /*!< Attach FRO0 Max clock to XSPI1 Functional Clock. */
1061 kMAIN_PLL_PFD2_to_XSPI1 =
1062 CLKCTL0_TUPLE_MUXA(XSPI1FCLKSEL_OFFSET, 3), /*!< Attach MAIN PLL PFD2 clock to XSPI1 Functional Clock. */
1063 kNONE_to_XSPI1 = CLKCTL0_TUPLE_MUXA_NONE(XSPI1FCLKSEL_OFFSET, 2), /*!< Attach NONE to XSPI1 Functional Clock. */
1064
1065 kCOMPUTE_BASE_to_SCT =
1066 CLKCTL0_TUPLE_MUXA(SCTFCLKSEL_OFFSET, 0), /*!< Attach Compute base clock to SCT Functional Clock. */
1067 kMAIN_PLL_PFD0_SCT = CLKCTL0_TUPLE_MUXA(SCTFCLKSEL_OFFSET, 1), /*!< Attach main_pll_pfd0 to SCT Functional Clock. */
1068 kFRO0_DIV1_to_SCT = CLKCTL0_TUPLE_MUXA(SCTFCLKSEL_OFFSET, 2), /*!< Attach FRO0 Max clock to SCT Functional Clock. */
1069 kFRO0_DIV6_to_SCT =
1070 CLKCTL0_TUPLE_MUXA(SCTFCLKSEL_OFFSET, 3), /*!< Attach FRO0_DIV6 clock to SCT Functional Clock. */
1071 kNONE_to_SCT = CLKCTL0_TUPLE_MUXA_NONE(SCTFCLKSEL_OFFSET, 0), /*!< Attach NONE to SCT Functional Clock. */
1072
1073 kCOMPUTE_BASE_to_UTICK0_CLK =
1074 CLKCTL0_TUPLE_MUXA(UTICK0FCLKSEL_OFFSET, 0), /*!< Attach compute base clock to UTICK0. */
1075 kLPOSC_to_UTICK0_CLK = CLKCTL0_TUPLE_MUXA(UTICK0FCLKSEL_OFFSET, 1), /*!< Attach main_pll_pfd0 to UTICK0. */
1076 kFRO0_DIV1_to_UTICK0_CLK = CLKCTL0_TUPLE_MUXA(UTICK0FCLKSEL_OFFSET, 2), /*!< Attach FRO0 Max to UTICK0. */
1077 kFRO1_DIV2_to_UTICK0_CLK = CLKCTL0_TUPLE_MUXA(UTICK0FCLKSEL_OFFSET, 3), /*!< Attach FRO1_DIV2 to UTICK0. */
1078 kNONE_to_UTICK0_CLK = CLKCTL0_TUPLE_MUXA_NONE(UTICK0FCLKSEL_OFFSET, 0), /*!< Attach NONE to UTICK0. */
1079
1080 kLPOSC_to_WWDT0 = CLKCTL0_TUPLE_MUXA(WWDT0FCLKSEL_OFFSET, 0), /*!< Attach LPOSC to WWDT0 Functional Clock. */
1081 kNONE_to_WWDT0 = CLKCTL0_TUPLE_MUXA_NONE(WWDT0FCLKSEL_OFFSET, 0), /*!< Attach NONE to WWDT0 Functional Clock. */
1082
1083 kLPOSC_to_WWDT1 = CLKCTL0_TUPLE_MUXA(WWDT1FCLKSEL_OFFSET, 0), /*!< Attach LPOSC to WWDT1 Functional Clock. */
1084 kNONE_to_WWDT1 = CLKCTL0_TUPLE_MUXA_NONE(WWDT1FCLKSEL_OFFSET, 0), /*!< Attach NONE to WWDT1 Functional Clock. */
1085
1086 kCOMPUTE_BASE_to_SYSTICK =
1087 CLKCTL0_TUPLE_MUXA(SYSTICKFCLKSEL_OFFSET, 0), /*!< Attach Compute base clock to SYSTICK Functional Clock. */
1088 kLPOSC_to_SYSTICK = CLKCTL0_TUPLE_MUXA(SYSTICKFCLKSEL_OFFSET, 1), /*!< Attach LPOSC to SYSTICK Functional Clock. */
1089 k32KHZ_WAKE_to_SYSTICK =
1090 CLKCTL0_TUPLE_MUXA(SYSTICKFCLKSEL_OFFSET, 2), /*!< Attach 32 KHz wake clock(switch to other clock source before
1091 compute vdd2 enter SRPG mode.) to SYSTICK Functional Clock. */
1092 kOSC_CLK_to_SYSTICK =
1093 CLKCTL0_TUPLE_MUXA(SYSTICKFCLKSEL_OFFSET, 3), /*!< Attach OSC_CLK clock to SYSTICK Functional Clock. */
1094 kNONE_to_SYSTICK =
1095 CLKCTL0_TUPLE_MUXA_NONE(SYSTICKFCLKSEL_OFFSET, 0), /*!< Attach NONE to SYSTICK Functional Clock. */
1096
1097 kCOMPUTE_BASE_to_SAI012 =
1098 CLKCTL0_TUPLE_MUXA(SAI012FCLKSEL_OFFSET, 0), /*!< Attach Compute base clock to SAI012 Clock. */
1099 kFRO2_DIV8_to_SAI012 = CLKCTL0_TUPLE_MUXA(SAI012FCLKSEL_OFFSET, 1), /*!< Attach FRO2_DIV8 to SAI012 Clock. */
1100 kFRO0_DIV1_to_SAI012 = CLKCTL0_TUPLE_MUXA(SAI012FCLKSEL_OFFSET, 2), /*!< Attach FRO0 max clock to SAI012 Clock. */
1101 kAUDIO_VDD2_to_SAI012 =
1102 CLKCTL0_TUPLE_MUXA(SAI012FCLKSEL_OFFSET, 3), /*!< Attach audio_clk_cmpt clock to SAI012 Clock. */
1103 kNONE_to_SAI012 = CLKCTL0_TUPLE_MUXA_NONE(SAI012FCLKSEL_OFFSET, 0), /*!< Attach NONE to SAI012 Clock. */
1104
1105 kCOMPUTE_BASE_to_FCCLK0 = CLKCTL0_TUPLE_MUXA(FCCLK0SEL_OFFSET, 0), /*!< Attach compute base clock to FCCLK0. */
1106 kFRO0_DIV1_to_FCCLK0 = CLKCTL0_TUPLE_MUXA(FCCLK0SEL_OFFSET, 1), /*!< Attach FRO0 max clock to FCCLK0. */
1107 kMAIN_PLL_PFD3_to_FCCLK0 = CLKCTL0_TUPLE_MUXA(FCCLK0SEL_OFFSET, 2), /*!< Attach MAIN PLL PFD3 clock to FCCLK0. */
1108 kOSC_CLK_to_FCCLK0 = CLKCTL0_TUPLE_MUXA(FCCLK0SEL_OFFSET, 3), /*!< Attach OSC clock to FCCLK0. */
1109 kNONE_to_FCCLK0 = CLKCTL0_TUPLE_MUXA_NONE(FCCLK0SEL_OFFSET, 0), /*!< Attach NONE to FCCLK0. */
1110
1111 kCOMPUTE_BASE_to_FCCLK1 = CLKCTL0_TUPLE_MUXA(FCCLK1SEL_OFFSET, 0), /*!< Attach compute base clock to FCCLK1. */
1112 kFRO0_DIV1_to_FCCLK1 = CLKCTL0_TUPLE_MUXA(FCCLK1SEL_OFFSET, 1), /*!< Attach FRO0 max clock to FCCLK1. */
1113 kMAIN_PLL_PFD3_to_FCCLK1 = CLKCTL0_TUPLE_MUXA(FCCLK1SEL_OFFSET, 2), /*!< Attach MAIN PLL PFD3 clock to FCCLK1. */
1114 kOSC_CLK_to_FCCLK1 = CLKCTL0_TUPLE_MUXA(FCCLK1SEL_OFFSET, 3), /*!< Attach OSC clock to FCCLK1. */
1115 kNONE_to_FCCLK1 = CLKCTL0_TUPLE_MUXA_NONE(FCCLK1SEL_OFFSET, 0), /*!< Attach NONE to FCCLK1. */
1116
1117 kCOMPUTE_BASE_to_FCCLK2 = CLKCTL0_TUPLE_MUXA(FCCLK2SEL_OFFSET, 0), /*!< Attach compute base clock to FCCLK2. */
1118 kFRO0_DIV1_to_FCCLK2 = CLKCTL0_TUPLE_MUXA(FCCLK2SEL_OFFSET, 1), /*!< Attach FRO0 max clock to FCCLK2. */
1119 kMAIN_PLL_PFD3_to_FCCLK2 = CLKCTL0_TUPLE_MUXA(FCCLK2SEL_OFFSET, 2), /*!< Attach MAIN PLL PFD3 clock to FCCLK2. */
1120 kOSC_CLK_to_FCCLK2 = CLKCTL0_TUPLE_MUXA(FCCLK2SEL_OFFSET, 3), /*!< Attach OSC clock to FCCLK2. */
1121 kNONE_to_FCCLK2 = CLKCTL0_TUPLE_MUXA_NONE(FCCLK2SEL_OFFSET, 0), /*!< Attach NONE to FCCLK2. */
1122
1123 kCOMPUTE_BASE_to_FCCLK3 = CLKCTL0_TUPLE_MUXA(FCCLK3SEL_OFFSET, 0), /*!< Attach compute base clock to FCCLK3. */
1124 kFRO0_DIV1_to_FCCLK3 = CLKCTL0_TUPLE_MUXA(FCCLK3SEL_OFFSET, 1), /*!< Attach FRO0 max clock to FCCLK3. */
1125 kMAIN_PLL_PFD3_to_FCCLK3 = CLKCTL0_TUPLE_MUXA(FCCLK3SEL_OFFSET, 2), /*!< Attach MAIN PLL PFD3 clock to FCCLK3. */
1126 kOSC_CLK_to_FCCLK3 = CLKCTL0_TUPLE_MUXA(FCCLK3SEL_OFFSET, 3), /*!< Attach OSC clock to FCCLK3. */
1127 kNONE_to_FCCLK3 = CLKCTL0_TUPLE_MUXA_NONE(FCCLK3SEL_OFFSET, 0), /*!< Attach NONE to FCCLK3. */
1128
1129 kFCCLK0_to_FLEXCOMM0 = CLKCTL0_TUPLE_MUXA(FC0FCLKSEL_OFFSET, 0), /*!< Attach FCCLK0 to FLEXCOMM0. */
1130 kFCCLK1_to_FLEXCOMM0 = CLKCTL0_TUPLE_MUXA(FC0FCLKSEL_OFFSET, 1), /*!< Attach FCCLK1 to FLEXCOMM0. */
1131 kFCCLK2_to_FLEXCOMM0 = CLKCTL0_TUPLE_MUXA(FC0FCLKSEL_OFFSET, 2), /*!< Attach FCCLK2 to FLEXCOMM0. */
1132 kFCCLK3_to_FLEXCOMM0 = CLKCTL0_TUPLE_MUXA(FC0FCLKSEL_OFFSET, 3), /*!< Attach FCCLK3 to FLEXCOMM0. */
1133 kNONE_to_FLEXCOMM0 = CLKCTL0_TUPLE_MUXA_NONE(FC0FCLKSEL_OFFSET, 0), /*!< Attach NONE to FLEXCOMM0. */
1134
1135 kFCCLK0_to_FLEXCOMM1 = CLKCTL0_TUPLE_MUXA(FC1FCLKSEL_OFFSET, 0), /*!< Attach FCCLK0 to FLEXCOMM1. */
1136 kFCCLK1_to_FLEXCOMM1 = CLKCTL0_TUPLE_MUXA(FC1FCLKSEL_OFFSET, 1), /*!< Attach FCCLK1 to FLEXCOMM1. */
1137 kFCCLK2_to_FLEXCOMM1 = CLKCTL0_TUPLE_MUXA(FC1FCLKSEL_OFFSET, 2), /*!< Attach FCCLK2 to FLEXCOMM1. */
1138 kFCCLK3_to_FLEXCOMM1 = CLKCTL0_TUPLE_MUXA(FC1FCLKSEL_OFFSET, 3), /*!< Attach FCCLK3 to FLEXCOMM1. */
1139 kNONE_to_FLEXCOMM1 = CLKCTL0_TUPLE_MUXA_NONE(FC1FCLKSEL_OFFSET, 0), /*!< Attach NONE to FLEXCOMM1. */
1140
1141 kFCCLK0_to_FLEXCOMM2 = CLKCTL0_TUPLE_MUXA(FC2FCLKSEL_OFFSET, 0), /*!< Attach FCCLK0 to FLEXCOMM2. */
1142 kFCCLK1_to_FLEXCOMM2 = CLKCTL0_TUPLE_MUXA(FC2FCLKSEL_OFFSET, 1), /*!< Attach FCCLK1 to FLEXCOMM2. */
1143 kFCCLK2_to_FLEXCOMM2 = CLKCTL0_TUPLE_MUXA(FC2FCLKSEL_OFFSET, 2), /*!< Attach FCCLK2 to FLEXCOMM2. */
1144 kFCCLK3_to_FLEXCOMM2 = CLKCTL0_TUPLE_MUXA(FC2FCLKSEL_OFFSET, 3), /*!< Attach FCCLK3 to FLEXCOMM2. */
1145 kNONE_to_FLEXCOMM2 = CLKCTL0_TUPLE_MUXA_NONE(FC2FCLKSEL_OFFSET, 0), /*!< Attach NONE to FLEXCOMM2. */
1146
1147 kFCCLK0_to_FLEXCOMM3 = CLKCTL0_TUPLE_MUXA(FC3FCLKSEL_OFFSET, 0), /*!< Attach FCCLK0 to FLEXCOMM3. */
1148 kFCCLK1_to_FLEXCOMM3 = CLKCTL0_TUPLE_MUXA(FC3FCLKSEL_OFFSET, 1), /*!< Attach FCCLK1 to FLEXCOMM3. */
1149 kFCCLK2_to_FLEXCOMM3 = CLKCTL0_TUPLE_MUXA(FC3FCLKSEL_OFFSET, 2), /*!< Attach FCCLK2 to FLEXCOMM3. */
1150 kFCCLK3_to_FLEXCOMM3 = CLKCTL0_TUPLE_MUXA(FC3FCLKSEL_OFFSET, 3), /*!< Attach FCCLK3 to FLEXCOMM3. */
1151 kNONE_to_FLEXCOMM3 = CLKCTL0_TUPLE_MUXA_NONE(FC3FCLKSEL_OFFSET, 0), /*!< Attach NONE to FLEXCOMM3. */
1152
1153 kFCCLK0_to_FLEXCOMM4 = CLKCTL0_TUPLE_MUXA(FC4FCLKSEL_OFFSET, 0), /*!< Attach FCCLK0 to FLEXCOMM4. */
1154 kFCCLK1_to_FLEXCOMM4 = CLKCTL0_TUPLE_MUXA(FC4FCLKSEL_OFFSET, 1), /*!< Attach FCCLK1 to FLEXCOMM4. */
1155 kFCCLK2_to_FLEXCOMM4 = CLKCTL0_TUPLE_MUXA(FC4FCLKSEL_OFFSET, 2), /*!< Attach FCCLK2 to FLEXCOMM4. */
1156 kFCCLK3_to_FLEXCOMM4 = CLKCTL0_TUPLE_MUXA(FC4FCLKSEL_OFFSET, 3), /*!< Attach FCCLK3 to FLEXCOMM4. */
1157 kNONE_to_FLEXCOMM4 = CLKCTL0_TUPLE_MUXA_NONE(FC4FCLKSEL_OFFSET, 0), /*!< Attach NONE to FLEXCOMM4. */
1158
1159 kFCCLK0_to_FLEXCOMM5 = CLKCTL0_TUPLE_MUXA(FC5FCLKSEL_OFFSET, 0), /*!< Attach FCCLK0 to FLEXCOMM5. */
1160 kFCCLK1_to_FLEXCOMM5 = CLKCTL0_TUPLE_MUXA(FC5FCLKSEL_OFFSET, 1), /*!< Attach FCCLK1 to FLEXCOMM5. */
1161 kFCCLK2_to_FLEXCOMM5 = CLKCTL0_TUPLE_MUXA(FC5FCLKSEL_OFFSET, 2), /*!< Attach FCCLK2 to FLEXCOMM5. */
1162 kFCCLK3_to_FLEXCOMM5 = CLKCTL0_TUPLE_MUXA(FC5FCLKSEL_OFFSET, 3), /*!< Attach FCCLK3 to FLEXCOMM5. */
1163 kNONE_to_FLEXCOMM5 = CLKCTL0_TUPLE_MUXA_NONE(FC5FCLKSEL_OFFSET, 0), /*!< Attach NONE to FLEXCOMM5. */
1164
1165 kFCCLK0_to_FLEXCOMM6 = CLKCTL0_TUPLE_MUXA(FC6FCLKSEL_OFFSET, 0), /*!< Attach FCCLK0 to FLEXCOMM6. */
1166 kFCCLK1_to_FLEXCOMM6 = CLKCTL0_TUPLE_MUXA(FC6FCLKSEL_OFFSET, 1), /*!< Attach FCCLK1 to FLEXCOMM6. */
1167 kFCCLK2_to_FLEXCOMM6 = CLKCTL0_TUPLE_MUXA(FC6FCLKSEL_OFFSET, 2), /*!< Attach FCCLK2 to FLEXCOMM6. */
1168 kFCCLK3_to_FLEXCOMM6 = CLKCTL0_TUPLE_MUXA(FC6FCLKSEL_OFFSET, 3), /*!< Attach FCCLK3 to FLEXCOMM6. */
1169 kNONE_to_FLEXCOMM6 = CLKCTL0_TUPLE_MUXA_NONE(FC6FCLKSEL_OFFSET, 0), /*!< Attach NONE to FLEXCOMM6. */
1170
1171 kFCCLK0_to_FLEXCOMM7 = CLKCTL0_TUPLE_MUXA(FC7FCLKSEL_OFFSET, 0), /*!< Attach FCCLK0 to FLEXCOMM7. */
1172 kFCCLK1_to_FLEXCOMM7 = CLKCTL0_TUPLE_MUXA(FC7FCLKSEL_OFFSET, 1), /*!< Attach FCCLK1 to FLEXCOMM7. */
1173 kFCCLK2_to_FLEXCOMM7 = CLKCTL0_TUPLE_MUXA(FC7FCLKSEL_OFFSET, 2), /*!< Attach FCCLK2 to FLEXCOMM7. */
1174 kFCCLK3_to_FLEXCOMM7 = CLKCTL0_TUPLE_MUXA(FC7FCLKSEL_OFFSET, 3), /*!< Attach FCCLK3 to FLEXCOMM7. */
1175 kNONE_to_FLEXCOMM7 = CLKCTL0_TUPLE_MUXA_NONE(FC7FCLKSEL_OFFSET, 0), /*!< Attach NONE to FLEXCOMM7. */
1176
1177 kFCCLK0_to_FLEXCOMM8 = CLKCTL0_TUPLE_MUXA(FC8FCLKSEL_OFFSET, 0), /*!< Attach FCCLK0 to FLEXCOMM8. */
1178 kFCCLK1_to_FLEXCOMM8 = CLKCTL0_TUPLE_MUXA(FC8FCLKSEL_OFFSET, 1), /*!< Attach FCCLK1 to FLEXCOMM8. */
1179 kFCCLK2_to_FLEXCOMM8 = CLKCTL0_TUPLE_MUXA(FC8FCLKSEL_OFFSET, 2), /*!< Attach FCCLK2 to FLEXCOMM8. */
1180 kFCCLK3_to_FLEXCOMM8 = CLKCTL0_TUPLE_MUXA(FC8FCLKSEL_OFFSET, 3), /*!< Attach FCCLK3 to FLEXCOMM8. */
1181 kNONE_to_FLEXCOMM8 = CLKCTL0_TUPLE_MUXA_NONE(FC8FCLKSEL_OFFSET, 0), /*!< Attach NONE to FLEXCOMM8. */
1182
1183 kFCCLK0_to_FLEXCOMM9 = CLKCTL0_TUPLE_MUXA(FC9FCLKSEL_OFFSET, 0), /*!< Attach FCCLK0 to FLEXCOMM9. */
1184 kFCCLK1_to_FLEXCOMM9 = CLKCTL0_TUPLE_MUXA(FC9FCLKSEL_OFFSET, 1), /*!< Attach FCCLK1 to FLEXCOMM9. */
1185 kFCCLK2_to_FLEXCOMM9 = CLKCTL0_TUPLE_MUXA(FC9FCLKSEL_OFFSET, 2), /*!< Attach FCCLK2 to FLEXCOMM9. */
1186 kFCCLK3_to_FLEXCOMM9 = CLKCTL0_TUPLE_MUXA(FC9FCLKSEL_OFFSET, 3), /*!< Attach FCCLK3 to FLEXCOMM9. */
1187 kNONE_to_FLEXCOMM9 = CLKCTL0_TUPLE_MUXA_NONE(FC9FCLKSEL_OFFSET, 0), /*!< Attach NONE to FLEXCOMM9. */
1188
1189 kFCCLK0_to_FLEXCOMM10 = CLKCTL0_TUPLE_MUXA(FC10FCLKSEL_OFFSET, 0), /*!< Attach FCCLK0 to FLEXCOMM10. */
1190 kFCCLK1_to_FLEXCOMM10 = CLKCTL0_TUPLE_MUXA(FC10FCLKSEL_OFFSET, 1), /*!< Attach FCCLK1 to FLEXCOMM10. */
1191 kFCCLK2_to_FLEXCOMM10 = CLKCTL0_TUPLE_MUXA(FC10FCLKSEL_OFFSET, 2), /*!< Attach FCCLK2 to FLEXCOMM10. */
1192 kFCCLK3_to_FLEXCOMM10 = CLKCTL0_TUPLE_MUXA(FC10FCLKSEL_OFFSET, 3), /*!< Attach FCCLK3 to FLEXCOMM10. */
1193 kNONE_to_FLEXCOMM10 = CLKCTL0_TUPLE_MUXA_NONE(FC10FCLKSEL_OFFSET, 0), /*!< Attach NONE to FLEXCOMM10. */
1194
1195 kFCCLK0_to_FLEXCOMM11 = CLKCTL0_TUPLE_MUXA(FC11FCLKSEL_OFFSET, 0), /*!< Attach FCCLK0 to FLEXCOMM11. */
1196 kFCCLK1_to_FLEXCOMM11 = CLKCTL0_TUPLE_MUXA(FC11FCLKSEL_OFFSET, 1), /*!< Attach FCCLK1 to FLEXCOMM11. */
1197 kFCCLK2_to_FLEXCOMM11 = CLKCTL0_TUPLE_MUXA(FC11FCLKSEL_OFFSET, 2), /*!< Attach FCCLK2 to FLEXCOMM11. */
1198 kFCCLK3_to_FLEXCOMM11 = CLKCTL0_TUPLE_MUXA(FC11FCLKSEL_OFFSET, 3), /*!< Attach FCCLK3 to FLEXCOMM11. */
1199 kNONE_to_FLEXCOMM11 = CLKCTL0_TUPLE_MUXA_NONE(FC11FCLKSEL_OFFSET, 0), /*!< Attach NONE to FLEXCOMM11. */
1200
1201 kFCCLK0_to_FLEXCOMM12 = CLKCTL0_TUPLE_MUXA(FC12FCLKSEL_OFFSET, 0), /*!< Attach FCCLK0 to FLEXCOMM12. */
1202 kFCCLK1_to_FLEXCOMM12 = CLKCTL0_TUPLE_MUXA(FC12FCLKSEL_OFFSET, 1), /*!< Attach FCCLK1 to FLEXCOMM12. */
1203 kFCCLK2_to_FLEXCOMM12 = CLKCTL0_TUPLE_MUXA(FC12FCLKSEL_OFFSET, 2), /*!< Attach FCCLK2 to FLEXCOMM12. */
1204 kFCCLK3_to_FLEXCOMM12 = CLKCTL0_TUPLE_MUXA(FC12FCLKSEL_OFFSET, 3), /*!< Attach FCCLK3 to FLEXCOMM12. */
1205 kNONE_to_FLEXCOMM12 = CLKCTL0_TUPLE_MUXA_NONE(FC12FCLKSEL_OFFSET, 0), /*!< Attach NONE to FLEXCOMM12. */
1206
1207 kFCCLK0_to_FLEXCOMM13 = CLKCTL0_TUPLE_MUXA(FC13FCLKSEL_OFFSET, 0), /*!< Attach FCCLK0 to FLEXCOMM13. */
1208 kFCCLK1_to_FLEXCOMM13 = CLKCTL0_TUPLE_MUXA(FC13FCLKSEL_OFFSET, 1), /*!< Attach FCCLK1 to FLEXCOMM13. */
1209 kFCCLK2_to_FLEXCOMM13 = CLKCTL0_TUPLE_MUXA(FC13FCLKSEL_OFFSET, 2), /*!< Attach FCCLK2 to FLEXCOMM13. */
1210 kFCCLK3_to_FLEXCOMM13 = CLKCTL0_TUPLE_MUXA(FC13FCLKSEL_OFFSET, 3), /*!< Attach FCCLK3 to FLEXCOMM13. */
1211 kNONE_to_FLEXCOMM13 = CLKCTL0_TUPLE_MUXA_NONE(FC13FCLKSEL_OFFSET, 0), /*!< Attach NONE to FLEXCOMM13. */
1212
1213 kCOMPUTE_BASE_to_CTIMER0 =
1214 CLKCTL0_TUPLE_MUXA(CTIMER0FCLKSEL_OFFSET, 0), /*!< Attach Compute base clock to CTIMER0 Clock. */
1215 kAUDIO_VDD2_to_CTIMER0 =
1216 CLKCTL0_TUPLE_MUXA(CTIMER0FCLKSEL_OFFSET, 1), /*!< Attach audio_clk_cmpt clock to CTIMER0 Clock. */
1217 kFRO0_DIV1_to_CTIMER0 =
1218 CLKCTL0_TUPLE_MUXA(CTIMER0FCLKSEL_OFFSET, 2), /*!< Attach FRO0 max clock to CTIMER0 Clock. */
1219 k32KHZ_WAKE_to_CTIMER0 =
1220 CLKCTL0_TUPLE_MUXA(CTIMER0FCLKSEL_OFFSET, 3), /*!< Attach 32KHz wake clock to CTIMER0 Clock. */
1221 kNONE_to_CTIMER0 = CLKCTL0_TUPLE_MUXA_NONE(CTIMER0FCLKSEL_OFFSET, 0), /*!< Attach NONE to CTIMER0 Clock. */
1222
1223 kCOMPUTE_BASE_to_CTIMER1 =
1224 CLKCTL0_TUPLE_MUXA(CTIMER1FCLKSEL_OFFSET, 0), /*!< Attach Compute base clock to CTIMER1 Clock. */
1225 kAUDIO_VDD2_to_CTIMER1 =
1226 CLKCTL0_TUPLE_MUXA(CTIMER1FCLKSEL_OFFSET, 1), /*!< Attach audio_clk_cmpt clock to CTIMER1 Clock. */
1227 kFRO0_DIV1_to_CTIMER1 =
1228 CLKCTL0_TUPLE_MUXA(CTIMER1FCLKSEL_OFFSET, 2), /*!< Attach FRO0 max clock to CTIMER1 Clock. */
1229 k32KHZ_WAKE_to_CTIMER1 =
1230 CLKCTL0_TUPLE_MUXA(CTIMER1FCLKSEL_OFFSET, 3), /*!< Attach 32KHz wake clock to CTIMER1 Clock. */
1231 kNONE_to_CTIMER1 = CLKCTL0_TUPLE_MUXA_NONE(CTIMER1FCLKSEL_OFFSET, 0), /*!< Attach NONE to CTIMER1 Clock. */
1232
1233 kCOMPUTE_BASE_to_CTIMER2 =
1234 CLKCTL0_TUPLE_MUXA(CTIMER2FCLKSEL_OFFSET, 0), /*!< Attach Compute base clock to CTIMER2 Clock. */
1235 kAUDIO_VDD2_to_CTIMER2 =
1236 CLKCTL0_TUPLE_MUXA(CTIMER2FCLKSEL_OFFSET, 1), /*!< Attach audio_clk_cmpt clock to CTIMER2 Clock. */
1237 kFRO0_DIV1_to_CTIMER2 =
1238 CLKCTL0_TUPLE_MUXA(CTIMER2FCLKSEL_OFFSET, 2), /*!< Attach FRO0 max clock to CTIMER2 Clock. */
1239 k32KHZ_WAKE_to_CTIMER2 =
1240 CLKCTL0_TUPLE_MUXA(CTIMER2FCLKSEL_OFFSET, 3), /*!< Attach 32KHz wake clock to CTIMER2 Clock. */
1241 kNONE_to_CTIMER2 = CLKCTL0_TUPLE_MUXA_NONE(CTIMER2FCLKSEL_OFFSET, 0), /*!< Attach NONE to CTIMER2 Clock. */
1242
1243 kCOMPUTE_BASE_to_CTIMER3 =
1244 CLKCTL0_TUPLE_MUXA(CTIMER3FCLKSEL_OFFSET, 0), /*!< Attach Compute base clock to CTIMER3 Clock. */
1245 kAUDIO_VDD2_to_CTIMER3 =
1246 CLKCTL0_TUPLE_MUXA(CTIMER3FCLKSEL_OFFSET, 1), /*!< Attach audio_clk_cmpt clock to CTIMER3 Clock. */
1247 kFRO0_DIV1_to_CTIMER3 =
1248 CLKCTL0_TUPLE_MUXA(CTIMER3FCLKSEL_OFFSET, 2), /*!< Attach FRO0 max clock to CTIMER3 Clock. */
1249 k32KHZ_WAKE_to_CTIMER3 =
1250 CLKCTL0_TUPLE_MUXA(CTIMER3FCLKSEL_OFFSET, 3), /*!< Attach 32KHz wake clock to CTIMER3 Clock. */
1251 kNONE_to_CTIMER3 = CLKCTL0_TUPLE_MUXA_NONE(CTIMER3FCLKSEL_OFFSET, 0), /*!< Attach NONE to CTIMER3 Clock. */
1252
1253 kCOMPUTE_BASE_to_CTIMER4 =
1254 CLKCTL0_TUPLE_MUXA(CTIMER4FCLKSEL_OFFSET, 0), /*!< Attach Compute base clock to CTIMER4 Clock. */
1255 kAUDIO_VDD2_to_CTIMER4 =
1256 CLKCTL0_TUPLE_MUXA(CTIMER4FCLKSEL_OFFSET, 1), /*!< Attach audio_clk_cmpt clock to CTIMER4 Clock. */
1257 kFRO0_DIV1_to_CTIMER4 =
1258 CLKCTL0_TUPLE_MUXA(CTIMER4FCLKSEL_OFFSET, 2), /*!< Attach FRO0 max clock to CTIMER4 Clock. */
1259 k32KHZ_WAKE_to_CTIMER4 =
1260 CLKCTL0_TUPLE_MUXA(CTIMER4FCLKSEL_OFFSET, 3), /*!< Attach 32KHz wake clock to CTIMER4 Clock. */
1261 kNONE_to_CTIMER4 = CLKCTL0_TUPLE_MUXA_NONE(CTIMER4FCLKSEL_OFFSET, 0), /*!< Attach NONE to CTIMER4 Clock. */
1262
1263 kCOMPUTE_BASE_to_TRNG =
1264 CLKCTL0_TUPLE_MUXA(TRNGFCLKSEL_OFFSET, 0), /*!< Attach Compute base clock to TRNG Functional Clock. */
1265 kFRO1_DIV2_to_TRNG =
1266 CLKCTL0_TUPLE_MUXA(TRNGFCLKSEL_OFFSET, 1), /*!< Attach FRO1_DIV2 clock to TRNG Functional Clock. */
1267 kFRO1_DIV8_to_TRNG =
1268 CLKCTL0_TUPLE_MUXA(TRNGFCLKSEL_OFFSET, 2), /*!< Attach FRO1_DIV8 clock to TRNG Functional Clock. */
1269 kFRO1_DIV3_to_TRNG =
1270 CLKCTL0_TUPLE_MUXA(TRNGFCLKSEL_OFFSET, 3), /*!< Attach FRO1_DIV3 clock to TRNG Functional Clock. */
1271 kNONE_to_TRNG = CLKCTL0_TUPLE_MUXA_NONE(TRNGFCLKSEL_OFFSET, 0), /*!< Attach NONE to TRNG Functional Clock. */
1272
1273 kCOMPUTE_BASE_to_I3C01 =
1274 CLKCTL0_TUPLE_MUXA(I3C01FCLKSEL_OFFSET, 0), /*!< Attach Compute base clock to I3C0 and I3C1 Functional Clock. */
1275 kFRO0_DIV1_to_I3C01 =
1276 CLKCTL0_TUPLE_MUXA(I3C01FCLKSEL_OFFSET, 1), /*!< Attach FRO0 MAX to I3C0 and I3C1 Functional Clock. */
1277 kFRO1_DIV8_to_I3C01 =
1278 CLKCTL0_TUPLE_MUXA(I3C01FCLKSEL_OFFSET, 2), /*!< Attach FRO1_DIV8 clock to I3C0 and I3C1 Functional Clock. */
1279 kOSC_CLK_to_I3C01 =
1280 CLKCTL0_TUPLE_MUXA(I3C01FCLKSEL_OFFSET, 3), /*!< Attach OSC_CLK clock to I3C0 and I3C1 Functional Clock. */
1281 kNONE_to_I3C01 =
1282 CLKCTL0_TUPLE_MUXA_NONE(I3C01FCLKSEL_OFFSET, 0), /*!< Attach NONE to I3C0 and I3C1 Functional Clock. */
1283
1284 kCOMPUTE_BASE_to_I3C01_PCLK =
1285 CLKCTL0_TUPLE_MUXA(I3C01PCLKSEL_OFFSET, 0), /*!< Attach Compute base clock to I3C0 and I3C1 P-CLK. */
1286 kMAIN_PLL_PFD0_to_I3C01_PCLK =
1287 CLKCTL0_TUPLE_MUXA(I3C01PCLKSEL_OFFSET, 1), /*!< Attach MAIN PLL PFD0 to I3C0 and I3C1 P-CLK. */
1288 kFRO0_DIV1_to_I3C01_PCLK =
1289 CLKCTL0_TUPLE_MUXA(I3C01PCLKSEL_OFFSET, 2), /*!< Attach FRO0 MAX to I3C0 and I3C1 P-CLK. */
1290 kFRO1_DIV1_to_I3C01_PCLK =
1291 CLKCTL0_TUPLE_MUXA(I3C01PCLKSEL_OFFSET, 3), /*!< Attach FRO1 MAX to I3C0 and I3C1 P-CLK. */
1292 kNONE_to_I3C01_PCLK = CLKCTL0_TUPLE_MUXA_NONE(I3C01PCLKSEL_OFFSET, 0), /*!< Attach NONE to I3C0 and I3C1 P-CLK. */
1293
1294 kCOMMON_VDD2_BASE_to_VDD2_CLKOUT =
1295 CLKCTL0_TUPLE_MUXA(CLKOUTCLKSEL_OFFSET, 0), /*!< Attach Common VDD2 Base Clock to VDD2 CLKOUT Clock. */
1296 kMAIN_PLL_PFD0_to_VDD2_CLKOUT =
1297 CLKCTL0_TUPLE_MUXA(CLKOUTCLKSEL_OFFSET, 1), /*!< Attach MAIN PLL PFD0 Clock to VDD2 CLKOUT Clock. */
1298 kFRO0_DIV1_to_VDD2_CLKOUT =
1299 CLKCTL0_TUPLE_MUXA(CLKOUTCLKSEL_OFFSET, 2), /*!< Attach FRO0 Max Clock to VDD2 CLKOUT Clock. */
1300 kFRO1_DIV1_to_VDD2_CLKOUT =
1301 CLKCTL0_TUPLE_MUXA(CLKOUTCLKSEL_OFFSET, 3), /*!< Attach FRO1 Max Clock to VDD2 CLKOUT Clock. */
1302 kNONE_to_VDD2_CLKOUT = CLKCTL0_TUPLE_MUXA_NONE(CLKOUTCLKSEL_OFFSET, 0), /*!< Attach NONE to VDD2 CLKOUT Clock. */
1303
1304 kMCLK_to_AUDIO_VDD2 =
1305 CLKCTL0_TUPLE_MUXA(AUDIOVDD2CLKSEL_OFFSET, 0), /*!< Attach MCLK IN from Pad to Audio VDD2 Clock. */
1306 kOSC_CLK_to_AUDIO_VDD2 =
1307 CLKCTL0_TUPLE_MUXA(AUDIOVDD2CLKSEL_OFFSET, 1), /*!< Attach OSC clock to Audio VDD2 Clock. */
1308 kFRO2_DIV8_to_AUDIO_VDD2 =
1309 CLKCTL0_TUPLE_MUXA(AUDIOVDD2CLKSEL_OFFSET, 2), /*!< Attach FRO2_DIV8 clock to Audio VDD2 Clock. */
1310 kAUDIO_PLL_PFD3_to_AUDIO_VDD2 =
1311 CLKCTL0_TUPLE_MUXA(AUDIOVDD2CLKSEL_OFFSET, 3), /*!< Attach AUDIO PLL PFD3 clock to Audio VDD2 Clock. */
1312
1313 #else /* Dedicated defination for sense domain */
1314 kFRO1_DIV3_to_SENSE_BASE =
1315 CLKCTL1_TUPLE_MUXA(SENSEBASECLKSEL_OFFSET, 0), /*!< Attach FRO1 divided-by-3 clock to Sense Base Clock. */
1316 kFRO1_DIV1_to_SENSE_BASE =
1317 CLKCTL1_TUPLE_MUXA(SENSEBASECLKSEL_OFFSET, 1), /*!< Attach FRO1 max clock to Sense Base Clock. */
1318 kFRO2_DIV3_to_SENSE_BASE =
1319 CLKCTL1_TUPLE_MUXA(SENSEBASECLKSEL_OFFSET, 2), /*!< Attach FRO2 divided-by-3 clock to Sense Base Clock. */
1320 kLPOSC_to_SENSE_BASE = CLKCTL1_TUPLE_MUXA(SENSEBASECLKSEL_OFFSET, 3), /*!< Attach LPOSC to Sense Base Clock. */
1321
1322 kSENSE_BASE_to_SENSE_DSP =
1323 CLKCTL1_TUPLE_MUXA(SENSEDSPCPUCLKSEL_OFFSET, 0), /*!< Attach Sense base clock to Sense DSP Clock. */
1324 kFRO2_DIV1_to_SENSE_DSP =
1325 CLKCTL1_TUPLE_MUXA(SENSEDSPCPUCLKSEL_OFFSET, 1), /*!< Attach FRO2 max clock to Sense DSP Clock. */
1326 kAUDIO_PLL_PFD1_to_SENSE_DSP =
1327 CLKCTL1_TUPLE_MUXA(SENSEDSPCPUCLKSEL_OFFSET, 2), /*!< Attach Audio PLL PFD1 clock to Sense DSP Clock. */
1328 kFRO1_DIV1_to_SENSE_DSP =
1329 CLKCTL1_TUPLE_MUXA(SENSEDSPCPUCLKSEL_OFFSET, 3), /*!< Attach FRO1 max clock to Sense DSP Clock. */
1330 kNONE_to_SENSE_DSP = CLKCTL1_TUPLE_MUXA_NONE(SENSEDSPCPUCLKSEL_OFFSET, 0), /*!< Attach NONE to Sense DSP Clock. */
1331
1332 kSENSE_BASE_to_SAI3 = CLKCTL1_TUPLE_MUXA(SAI3FCLKSEL_OFFSET, 0), /*!< Attach Sense base clock to SAI3 Clock. */
1333 kFRO2_DIV8_to_SAI3 = CLKCTL1_TUPLE_MUXA(SAI3FCLKSEL_OFFSET, 1), /*!< Attach FRO2_DIV8 clock to SAI3 Clock. */
1334 kFRO2_DIV1_to_SAI3 = CLKCTL1_TUPLE_MUXA(SAI3FCLKSEL_OFFSET, 2), /*!< Attach FRO2 clock to SAI3 Clock. */
1335 kAUDIO_VDD1_to_SAI3 = CLKCTL1_TUPLE_MUXA(SAI3FCLKSEL_OFFSET, 3), /*!< Attach audio_clk to SAI3 Clock. */
1336 kNONE_to_SAI3 = CLKCTL1_TUPLE_MUXA_NONE(SAI3FCLKSEL_OFFSET, 0), /*!< Attach NONE to SAI3 Clock. */
1337
1338 kSENSE_BASE_to_UTICK =
1339 CLKCTL1_TUPLE_MUXA(UTICK1FCLKSEL_OFFSET, 0), /*!< Attach Sense base clock to UTICK Functional Clock. */
1340 kLPOSC_to_UTICK = CLKCTL1_TUPLE_MUXA(UTICK1FCLKSEL_OFFSET, 1), /*!< Attach LPOSC clock to UTICK Functional Clock. */
1341 kFRO2_DIV1_to_UTICK =
1342 CLKCTL1_TUPLE_MUXA(UTICK1FCLKSEL_OFFSET, 2), /*!< Attach FRO2 max clock to UTICK Functional Clock. */
1343 kFRO1_DIV2_to_UTICK =
1344 CLKCTL1_TUPLE_MUXA(UTICK1FCLKSEL_OFFSET, 3), /*!< Attach FRO1_DIV2 clock to UTICK Functional Clock. */
1345 kNONE_to_UTICK = CLKCTL1_TUPLE_MUXA_NONE(UTICK1FCLKSEL_OFFSET, 0), /*!< Attach NONE to UTICK Functional Clock. */
1346
1347 kLPOSC_to_WWDT2 = CLKCTL1_TUPLE_MUXA(WWDT2FCLKSEL_OFFSET, 0), /*!< Attach LPOSC clock to WWDT2 Functional Clock. */
1348 kNONE_to_WWDT2 = CLKCTL1_TUPLE_MUXA_NONE(WWDT2FCLKSEL_OFFSET, 0), /*!< Attach NONE to WWDT2 Functional Clock. */
1349
1350 kLPOSC_to_WWDT3 = CLKCTL1_TUPLE_MUXA(WWDT3FCLKSEL_OFFSET, 0), /*!< Attach LPOSC clock to WWDT3 Functional Clock. */
1351 kNONE_to_WWDT3 = CLKCTL1_TUPLE_MUXA_NONE(WWDT3FCLKSEL_OFFSET, 0), /*!< Attach NONE to WWDT3 Functional Clock. */
1352
1353 kSENSE_BASE_to_SYSTICK =
1354 CLKCTL1_TUPLE_MUXA(SYSTICKFCLKSEL_OFFSET, 0), /*!< Attach Sense base clock to SYSTICK Functional Clock. */
1355 kLPOSC_to_SYSTICK =
1356 CLKCTL1_TUPLE_MUXA(SYSTICKFCLKSEL_OFFSET, 1), /*!< Attach LPOSC clock to SYSTICK Functional Clock. */
1357 k32KHZ_WAKE_to_SYSTICK =
1358 CLKCTL1_TUPLE_MUXA(SYSTICKFCLKSEL_OFFSET, 2), /*!< Attach 32 kHz wake clock(switch to other clock source
1359 before sense vdd1 enter SRPG mode.) to SYSTICK Functional Clock. */
1360 kOSC_CLK_to_SYSTICK =
1361 CLKCTL1_TUPLE_MUXA(SYSTICKFCLKSEL_OFFSET, 3), /*!< Attach OSC clock to SYSTICK Functional Clock. */
1362 kNONE_to_SYSTICK =
1363 CLKCTL1_TUPLE_MUXA_NONE(SYSTICKFCLKSEL_OFFSET, 0), /*!< Attach NONE to SYSTICK Functional Clock. */
1364
1365 kSENSE_BASE_to_CTIMER5 =
1366 CLKCTL1_TUPLE_MUXA(CTIMER5FCLKSEL_OFFSET, 0), /*!< Attach Sense base clock to CTIMER5 Clock. */
1367 kAUDIO_VDD1_to_CTIMER5 = CLKCTL1_TUPLE_MUXA(CTIMER5FCLKSEL_OFFSET, 1), /*!< Attach audio_clk to CTIMER5 Clock. */
1368 kFRO2_DIV1_to_CTIMER5 =
1369 CLKCTL1_TUPLE_MUXA(CTIMER5FCLKSEL_OFFSET, 2), /*!< Attach FRO2 Max clock to CTIMER5 Clock. */
1370 k32KHZ_WAKE_to_CTIMER5 =
1371 CLKCTL1_TUPLE_MUXA(CTIMER5FCLKSEL_OFFSET, 3), /*!< Attach 32KHz wake clock to CTIMER5 Clock. */
1372 kNONE_to_CTIMER5 = CLKCTL1_TUPLE_MUXA_NONE(CTIMER5FCLKSEL_OFFSET, 0), /*!< Attach NONE to CTIMER5 Clock. */
1373
1374 kSENSE_BASE_to_CTIMER6 =
1375 CLKCTL1_TUPLE_MUXA(CTIMER6FCLKSEL_OFFSET, 0), /*!< Attach Sense base clock to CTIMER6 Clock. */
1376 kAUDIO_VDD1_to_CTIMER6 = CLKCTL1_TUPLE_MUXA(CTIMER6FCLKSEL_OFFSET, 1), /*!< Attach audio_clk to CTIMER6 Clock. */
1377 kFRO2_DIV1_to_CTIMER6 =
1378 CLKCTL1_TUPLE_MUXA(CTIMER6FCLKSEL_OFFSET, 2), /*!< Attach FRO2 Max clock to CTIMER6 Clock. */
1379 k32KHZ_WAKE_to_CTIMER6 =
1380 CLKCTL1_TUPLE_MUXA(CTIMER6FCLKSEL_OFFSET, 3), /*!< Attach 32KHz wake clock to CTIMER6 Clock. */
1381 kNONE_to_CTIMER6 = CLKCTL1_TUPLE_MUXA_NONE(CTIMER6FCLKSEL_OFFSET, 0), /*!< Attach NONE to CTIMER6 Clock. */
1382
1383 kSENSE_BASE_to_CTIMER7 =
1384 CLKCTL1_TUPLE_MUXA(CTIMER7FCLKSEL_OFFSET, 0), /*!< Attach Sense base clock to CTIMER7 Clock. */
1385 kAUDIO_VDD1_to_CTIMER7 = CLKCTL1_TUPLE_MUXA(CTIMER7FCLKSEL_OFFSET, 1), /*!< Attach audio_clk to CTIMER7 Clock. */
1386 kFRO2_DIV1_to_CTIMER7 =
1387 CLKCTL1_TUPLE_MUXA(CTIMER7FCLKSEL_OFFSET, 2), /*!< Attach FRO2 Max clock to CTIMER7 Clock. */
1388 k32KHZ_WAKE_to_CTIMER7 =
1389 CLKCTL1_TUPLE_MUXA(CTIMER7FCLKSEL_OFFSET, 3), /*!< Attach 32KHz wake clock to CTIMER7 Clock. */
1390 kNONE_to_CTIMER7 = CLKCTL1_TUPLE_MUXA_NONE(CTIMER7FCLKSEL_OFFSET, 0), /*!< Attach NONE to CTIMER7 Clock. */
1391
1392 kSENSE_BASE_to_I3C23 =
1393 CLKCTL1_TUPLE_MUXA(I3C23FCLKSEL_OFFSET, 0), /*!< Attach Sense base clock to I3C2 and I3C3 Functional Clock. */
1394 kFRO2_DIV1_to_I3C23 =
1395 CLKCTL1_TUPLE_MUXA(I3C23FCLKSEL_OFFSET, 1), /*!< Attach FRO2 max clock to I3C2 and I3C3 Functional Clock. */
1396 kFRO1_DIV8_to_I3C23 =
1397 CLKCTL1_TUPLE_MUXA(I3C23FCLKSEL_OFFSET, 2), /*!< Attach FRO2_DIV8 clock to I3C2 and I3C3 Functional Clock. */
1398 kOSC_CLK_to_I3C23 =
1399 CLKCTL1_TUPLE_MUXA(I3C23FCLKSEL_OFFSET, 3), /*!< Attach OSC clock to I3C2 and I3C3 Functional Clock. */
1400 kNONE_to_I3C23 =
1401 CLKCTL1_TUPLE_MUXA_NONE(I3C23FCLKSEL_OFFSET, 0), /*!< Attach NONE to I3C2 and I3C3 Functional Clock. */
1402
1403 kMCLK_to_AUDIO_VDD1 =
1404 CLKCTL1_TUPLE_MUXA(AUDIOVDD1CLKSEL_OFFSET, 0), /*!< Attach MCLK IN from Pad to Audio VDD1 Clock. */
1405 kOSC_to_AUDIO_VDD1 = CLKCTL1_TUPLE_MUXA(AUDIOVDD1CLKSEL_OFFSET, 1), /*!< Attach OSC clock to Audio VDD1 Clock. */
1406 kFRO2_DIV8_to_AUDIO_VDD1 =
1407 CLKCTL1_TUPLE_MUXA(AUDIOVDD1CLKSEL_OFFSET, 2), /*!< Attach FRO2_DIV8 clock to Audio VDD1 Clock. */
1408 kAUDIO_PLL_PFD3_to_AUDIO_VDD1 =
1409 CLKCTL1_TUPLE_MUXA(AUDIOVDD1CLKSEL_OFFSET, 3), /*!< Attach AUDIO PLL PFD3 clock to Audio VDD1 Clock. */
1410
1411 kSENSE_BASE_to_FLEXCOMM17 =
1412 CLKCTL1_TUPLE_MUXA(FC17FCLKSEL_OFFSET, 0), /*!< Attach Sense base clock to FLEXCOMM17. */
1413 kFRO2_DIV1_to_FLEXCOMM17 = CLKCTL1_TUPLE_MUXA(FC17FCLKSEL_OFFSET, 1), /*!< Attach FRO2 max clock to FLEXCOMM17. */
1414 kFRO1_DIV1_to_FLEXCOMM17 = CLKCTL1_TUPLE_MUXA(FC17FCLKSEL_OFFSET, 2), /*!< Attach FRO1 max clock to FLEXCOMM17. */
1415 k32KHZ_WAKE_to_FLEXCOMM17 = CLKCTL1_TUPLE_MUXA(FC17FCLKSEL_OFFSET, 3), /*!< Attach 32k_wake_clk to FLEXCOMM17. */
1416 kNONE_to_FLEXCOMM17 = CLKCTL1_TUPLE_MUXA_NONE(FC17FCLKSEL_OFFSET, 0), /*!< Attach NONE to FLEXCOMM17. */
1417
1418 kSENSE_BASE_to_FLEXCOMM18 =
1419 CLKCTL1_TUPLE_MUXA(FC18FCLKSEL_OFFSET, 0), /*!< Attach Sense base clock to FLEXCOMM18. */
1420 kFRO2_DIV1_to_FLEXCOMM18 = CLKCTL1_TUPLE_MUXA(FC18FCLKSEL_OFFSET, 1), /*!< Attach FRO2 max clock to FLEXCOMM18. */
1421 kFRO1_DIV1_to_FLEXCOMM18 = CLKCTL1_TUPLE_MUXA(FC18FCLKSEL_OFFSET, 2), /*!< Attach FRO1 max clock to FLEXCOMM18. */
1422 k32KHZ_WAKE_to_FLEXCOMM18 = CLKCTL1_TUPLE_MUXA(FC18FCLKSEL_OFFSET, 3), /*!< Attach 32k_wake_clk to FLEXCOMM18. */
1423 kNONE_to_FLEXCOMM18 = CLKCTL1_TUPLE_MUXA_NONE(FC18FCLKSEL_OFFSET, 0), /*!< Attach NONE to FLEXCOMM18. */
1424
1425 kSENSE_BASE_to_FLEXCOMM19 =
1426 CLKCTL1_TUPLE_MUXA(FC19FCLKSEL_OFFSET, 0), /*!< Attach Sense base clock to FLEXCOMM19. */
1427 kFRO2_DIV1_to_FLEXCOMM19 = CLKCTL1_TUPLE_MUXA(FC19FCLKSEL_OFFSET, 1), /*!< Attach FRO2 max clock to FLEXCOMM19. */
1428 kFRO1_DIV1_to_FLEXCOMM19 = CLKCTL1_TUPLE_MUXA(FC19FCLKSEL_OFFSET, 2), /*!< Attach FRO1 max clock to FLEXCOMM19. */
1429 k32KHZ_WAKE_to_FLEXCOMM19 = CLKCTL1_TUPLE_MUXA(FC19FCLKSEL_OFFSET, 3), /*!< Attach 32k_wake_clk to FLEXCOMM19. */
1430 kNONE_to_FLEXCOMM19 = CLKCTL1_TUPLE_MUXA_NONE(FC19FCLKSEL_OFFSET, 0), /*!< Attach NONE to FLEXCOMM19. */
1431
1432 kSENSE_BASE_to_FLEXCOMM20 =
1433 CLKCTL1_TUPLE_MUXA(FC20FCLKSEL_OFFSET, 0), /*!< Attach Sense base clock to FLEXCOMM20. */
1434 kFRO2_DIV1_to_FLEXCOMM20 = CLKCTL1_TUPLE_MUXA(FC20FCLKSEL_OFFSET, 1), /*!< Attach FRO2 max clock to FLEXCOMM20. */
1435 kFRO1_DIV1_to_FLEXCOMM20 = CLKCTL1_TUPLE_MUXA(FC20FCLKSEL_OFFSET, 2), /*!< Attach FRO1 max clock to FLEXCOMM20. */
1436 k32KHZ_WAKE_to_FLEXCOMM20 = CLKCTL1_TUPLE_MUXA(FC20FCLKSEL_OFFSET, 3), /*!< Attach 32k_wake_clk to FLEXCOMM20. */
1437 kNONE_to_FLEXCOMM20 = CLKCTL1_TUPLE_MUXA_NONE(FC20FCLKSEL_OFFSET, 0), /*!< Attach NONE to FLEXCOMM20. */
1438
1439 #endif /* FSL_CLOCK_DRIVER_COMPUTE */
1440
1441 kCOMMON_BASE_to_COMMON_VDDN =
1442 CLKCTL2_TUPLE_MUXA(COMMONVDDNCLKSEL_OFFSET, 0), /*!< Attach Common base clock to Common VDDN Clock. */
1443 kMAIN_PLL_PFD3_to_COMMON_VDDN =
1444 CLKCTL2_TUPLE_MUXA(COMMONVDDNCLKSEL_OFFSET, 1), /*!< Attach Main PLL PFD3 clock to Common VDDN Clock. */
1445 kFRO1_DIV1_to_COMMON_VDDN =
1446 CLKCTL2_TUPLE_MUXA(COMMONVDDNCLKSEL_OFFSET, 2), /*!< Attach FRO1 max clock to Common VDDN Clock. */
1447 kOSC_CLK_to_COMMON_VDDN =
1448 CLKCTL2_TUPLE_MUXA(COMMONVDDNCLKSEL_OFFSET, 3), /*!< Attach OSC clock to Common VDDN Clock. */
1449
1450 kOSC_CLK_to_USB_24MHZ =
1451 CLKCTL2_TUPLE_MUXA(USBCLKSRC24MCLKSEL_OFFSET, 0), /*!< Attach OSC_CLK clock to 24MHz USB OSC Clock. */
1452 kFRO1_DIV8_to_USB_24MHZ =
1453 CLKCTL2_TUPLE_MUXA(USBCLKSRC24MCLKSEL_OFFSET, 1), /*!< Attach FRO1_DIV8 clock to 24MHz USB OSC Clock. */
1454
1455 kFRO1_DIV3_to_COMMON_BASE =
1456 CLKCTL2_TUPLE_MUXA(COMNBASECLKSEL_OFFSET, 0), /*!< Attach Fro1 divided-by-3 to Common Base Clock. */
1457 kFRO1_DIV1_to_COMMON_BASE =
1458 CLKCTL2_TUPLE_MUXA(COMNBASECLKSEL_OFFSET, 1), /*!< Attach Fro1 divided-by-1 to Common Base Clock. */
1459 kFRO0_DIV3_to_COMMON_BASE =
1460 CLKCTL2_TUPLE_MUXA(COMNBASECLKSEL_OFFSET, 2), /*!< Attach Fro0 divided-by-3 to Common Base Clock. */
1461 kLPOSC_to_COMMON_BASE = CLKCTL2_TUPLE_MUXA(COMNBASECLKSEL_OFFSET, 3), /*!< Attach LPOSC to Common Base Clock. */
1462
1463 kOSC_CLK_to_EUSB_24MHZ =
1464 CLKCTL2_TUPLE_MUXA(EUSBCLKSRC24MCLKSEL_OFFSET, 0), /*!< Attach OSC_CLK clock to 24MHz eUSB OSC Clock. */
1465 kFRO1_DIV8_to_EUSB_24MHZ =
1466 CLKCTL2_TUPLE_MUXA(EUSBCLKSRC24MCLKSEL_OFFSET, 1), /*!< Attach FRO1_DIV8 clock to 24MHz eUSB OSC Clock. */
1467
1468 kFRO1_DIV8_to_MAIN_PLL0 =
1469 CLKCTL2_TUPLE_MUXA(MAINPLL0CLKSEL_OFFSET, 0), /*!< Attach FRO1_DIV8 clock to Main PLL0 Clock. */
1470 kOSC_CLK_to_MAIN_PLL0 =
1471 CLKCTL2_TUPLE_MUXA(MAINPLL0CLKSEL_OFFSET, 1), /*!< Attach OSC_CLK clock to Main PLL0 Clock. */
1472
1473 kFRO1_DIV8_to_AUDIO_PLL0 =
1474 CLKCTL2_TUPLE_MUXA(AUDIOPLL0CLKSEL_OFFSET, 0), /*!< Attach FRO1_DIV8 to Audio PLL0 Clock. */
1475 kOSC_CLK_to_AUDIO_PLL0 = CLKCTL2_TUPLE_MUXA(AUDIOPLL0CLKSEL_OFFSET,
1476 1), /*!< Attach OSC_CLK clock (User-Selectable) to Audio PLL0 Clock. */
1477 kSENSE_BASE_to_SENSE_MAIN =
1478 CLKCTL3_TUPLE_MUXA(SENSE_MAINCLKSEL_OFFSET, 0), /*!< Attach Sense base clock to Sense main clock. */
1479 kFRO2_DIV1_to_SENSE_MAIN =
1480 CLKCTL3_TUPLE_MUXA(SENSE_MAINCLKSEL_OFFSET, 1), /*!< Attach FRO2 max clock to Sense main clock. */
1481 kAUDIO_PLL_PFD3_to_SENSE_MAIN =
1482 CLKCTL3_TUPLE_MUXA(SENSE_MAINCLKSEL_OFFSET, 2), /*!< Attach Audio PLL PFD3 clock to Sense main clock. */
1483 kFRO1_DIV1_to_SENSE_MAIN =
1484 CLKCTL3_TUPLE_MUXA(SENSE_MAINCLKSEL_OFFSET, 3), /*!< Attach FRO1 max clock to Sense main clock. */
1485
1486 kSENSE_BASE_to_SENSE_RAM =
1487 CLKCTL3_TUPLE_MUXA(SENSERAMCLKSEL_OFFSET, 0), /*!< Attach Sense base clock to Sense RAM clock. */
1488 kFRO2_DIV1_to_SENSE_RAM =
1489 CLKCTL3_TUPLE_MUXA(SENSERAMCLKSEL_OFFSET, 1), /*!< Attach FRO2 max clock to Sense RAM clock. */
1490 kAUDIO_PLL_PFD2_to_SENSE_RAM =
1491 CLKCTL3_TUPLE_MUXA(SENSERAMCLKSEL_OFFSET, 2), /*!< Attach Audio PLL PFD2 clock to Sense RAM clock. */
1492 kFRO1_DIV1_to_SENSE_RAM =
1493 CLKCTL3_TUPLE_MUXA(SENSERAMCLKSEL_OFFSET, 3), /*!< Attach FRO1 max clock to Sense RAM clock. */
1494
1495 kSENSE_BASE_to_OSTIMER = CLKCTL3_TUPLE_MUXA(OSEVENTTFCLKSEL_OFFSET, 0), /*!< Attach Sense Base to OSTIMER. */
1496 k32KHZ_WAKE_to_OSTIMER = CLKCTL3_TUPLE_MUXA(OSEVENTTFCLKSEL_OFFSET, 1), /*!< Attach 32k_wake_clk to OSTIMER. */
1497 kLPOSC_to_OSTIMER = CLKCTL3_TUPLE_MUXA(OSEVENTTFCLKSEL_OFFSET, 2), /*!< Attach LPOSC to OSTIMER. */
1498 kOSC_CLK_to_OSTIMER = CLKCTL3_TUPLE_MUXA(OSEVENTTFCLKSEL_OFFSET, 3), /*!< Attach OSC clock to OSTIMER. */
1499 kNONE_to_OSTIMER = CLKCTL3_TUPLE_MUXA_NONE(OSEVENTTFCLKSEL_OFFSET, 0), /*!< Attach NONE to OSTIMER. */
1500
1501 kSENSE_BASE_to_SDADC =
1502 CLKCTL3_TUPLE_MUXA(SDADCFCLKSEL_OFFSET, 0), /*!< Attach Sense base clock to SDADC Functional Clock. */
1503 kFRO2_DIV8_to_SDADC =
1504 CLKCTL3_TUPLE_MUXA(SDADCFCLKSEL_OFFSET, 1), /*!< Attach FRO2_DIV8 clock to SDADC Functional Clock. */
1505 kAUDIO_PLL_to_SDADC =
1506 CLKCTL3_TUPLE_MUXA(SDADCFCLKSEL_OFFSET, 2), /*!< Attach Audio PLL VCO clock to SDADC Functional Clock. */
1507 kAUDIO_VDD1_to_SDADC =
1508 CLKCTL3_TUPLE_MUXA(SDADCFCLKSEL_OFFSET, 3), /*!< Attach audio_clk to SDADC Functional Clock. */
1509 kNONE_to_SDADC = CLKCTL3_TUPLE_MUXA_NONE(SDADCFCLKSEL_OFFSET, 0), /*!< Attach NONE to SDADC Functional Clock. */
1510
1511 kSENSE_BASE_to_ADC =
1512 CLKCTL3_TUPLE_MUXA(SARADCFCLKSEL_OFFSET, 0), /*!< Attach Sense base clock to SARADC Functional Clock. */
1513 kMAIN_PLL_PFD1_to_ADC =
1514 CLKCTL3_TUPLE_MUXA(SARADCFCLKSEL_OFFSET, 1), /*!< Attach main_pll_pfd1 to SARADC Functional Clock. */
1515 kFRO2_DIV1_to_ADC =
1516 CLKCTL3_TUPLE_MUXA(SARADCFCLKSEL_OFFSET, 2), /*!< Attach FRO0 max clock to SARADC Functional Clock. */
1517 kOSC_CLK_to_ADC = CLKCTL3_TUPLE_MUXA(SARADCFCLKSEL_OFFSET, 3), /*!< Attach osc_clk to SARADC Functional Clock. */
1518 kNONE_to_ADC = CLKCTL3_TUPLE_MUXA_NONE(SARADCFCLKSEL_OFFSET, 0), /*!< Attach NONE to SARADC Functional Clock. */
1519
1520 kOSC32K_to_32K_WAKE = CLKCTL3_TUPLE_MUXA(WAKE32KCLKSEL_OFFSET, 0), /*!< Attach OSC 32K to Wake 32k Clock. */
1521 kLPOSC_DIV32_to_32K_WAKE = CLKCTL3_TUPLE_MUXA(
1522 WAKE32KCLKSEL_OFFSET, 1), /*!< Attach LPOSC clock divided by 32 by default to Wake 32k Clock. */
1523 kNONE_to_32K_WAKE = CLKCTL3_TUPLE_MUXA(WAKE32KCLKSEL_OFFSET, 3), /*!< Attach NONE to Wake 32k Clock. */
1524
1525 kSENSE_BASE_to_MICFIL0 =
1526 CLKCTL3_TUPLE_MUXA(MICFIL0FCLKSEL_OFFSET, 0), /*!< Attach Sense base clock to MICFIL0 Functional Clock. */
1527 kAUDIO_PLL_PFD3_to_MICFIL0 =
1528 CLKCTL3_TUPLE_MUXA(MICFIL0FCLKSEL_OFFSET, 1), /*!< Attach Audio PLL PFD3 clock to MICFIL0 Functional Clock. */
1529 kFRO2_DIV1_to_MICFIL0 =
1530 CLKCTL3_TUPLE_MUXA(MICFIL0FCLKSEL_OFFSET, 2), /*!< Attach FRO2 MAX clock to MICFIL0 Functional Clock. */
1531 kAUDIO_VDD1_to_MICFIL0 =
1532 CLKCTL3_TUPLE_MUXA(MICFIL0FCLKSEL_OFFSET, 3), /*!< Attach Audio clock to MICFIL0 Functional Clock. */
1533 kNONE_to_MICFIL0 =
1534 CLKCTL3_TUPLE_MUXA_NONE(MICFIL0FCLKSEL_OFFSET, 0), /*!< Attach NONE to MICFIL0 Functional Clock. */
1535
1536 kSENSE_BASE_to_LPI2C15 =
1537 CLKCTL3_TUPLE_MUXA(LPI2CFCLKSEL_OFFSET, 0), /*!< Attach Sense base clock to LPI2C15 Functional Clock. */
1538 kFRO1_DIV1_to_LPI2C15 =
1539 CLKCTL3_TUPLE_MUXA(LPI2CFCLKSEL_OFFSET, 1), /*!< Attach FRO1 max clock to LPI2C15 Functional Clock. */
1540 kFRO1_DIV2_to_LPI2C15 =
1541 CLKCTL3_TUPLE_MUXA(LPI2CFCLKSEL_OFFSET, 2), /*!< Attach FRO1 divided-by-2 to LPI2C15 Functional Clock. */
1542 kFRO2_DIV1_to_LPI2C15 =
1543 CLKCTL3_TUPLE_MUXA(LPI2CFCLKSEL_OFFSET, 3), /*!< Attach FRO2 max clock to LPI2C15 Functional Clock. */
1544 kNONE_to_LPI2C15 = CLKCTL3_TUPLE_MUXA_NONE(LPI2CFCLKSEL_OFFSET, 0), /*!< Attach NONE to LPI2C15 Functional Clock. */
1545
1546 kSENSE_BASE_to_VDD1_CLKOUT =
1547 CLKCTL3_TUPLE_MUXA(SENSE_CLKOUTCLKSEL_OFFSET, 0), /*!< Attach Sense VDD1 Base Clock to VDD1 CLKOUT Clock. */
1548 kAUDIO_PLL_PFD3_to_VDD1_CLKOUT =
1549 CLKCTL3_TUPLE_MUXA(SENSE_CLKOUTCLKSEL_OFFSET, 1), /*!< Attach AUDIO PLL PFD3 Clock to VDD1 CLKOUT Clock. */
1550 kFRO2_DIV1_to_VDD1_CLKOUT =
1551 CLKCTL3_TUPLE_MUXA(SENSE_CLKOUTCLKSEL_OFFSET, 2), /*!< Attach FRO2 Max Clock to VDD1 CLKOUT Clock. */
1552 kFRO1_DIV1_to_VDD1_CLKOUT =
1553 CLKCTL3_TUPLE_MUXA(SENSE_CLKOUTCLKSEL_OFFSET, 3), /*!< Attach FRO1 Max Clock to VDD1 CLKOUT Clock. */
1554 kNONE_to_VDD1_CLKOUT =
1555 CLKCTL3_TUPLE_MUXA_NONE(SENSE_CLKOUTCLKSEL_OFFSET, 0), /*!< Attach NONE to VDD1 CLKOUT Clock. */
1556
1557 kMEDIA_VDDN_BASE_to_MEDIA_VDDN =
1558 CLKCTL4_TUPLE_MUXA(MEDIAVDDNCLKSEL_OFFSET, 0), /*!< Attach MEDIA VDDN base clock to MEDIA VDDN clock. */
1559 kMAIN_PLL_PFD0_to_MEDIA_VDDN =
1560 CLKCTL4_TUPLE_MUXA(MEDIAVDDNCLKSEL_OFFSET, 1), /*!< Attach MAIN PLL PFD0 to MEDIA VDDN clock. */
1561 kFRO0_DIV1_to_MEDIA_VDDN =
1562 CLKCTL4_TUPLE_MUXA(MEDIAVDDNCLKSEL_OFFSET, 2), /*!< Attach FRO0 max to MEDIA VDDN clock. */
1563 kMAIN_PLL_PFD2_to_MEDIA_VDDN =
1564 CLKCTL4_TUPLE_MUXA(MEDIAVDDNCLKSEL_OFFSET, 3), /*!< Attach MAIN PLL PFD2 to MEDIA VDDN clock. */
1565
1566 kMEDIA_VDD2_BASE_to_MEDIA_MAIN =
1567 CLKCTL4_TUPLE_MUXA(MEDIAMAINCLKSEL_OFFSET, 0), /*!< Attach MEDIA VDD2 base clock to MEDIA MAIN clock. */
1568 kMAIN_PLL_PFD0_to_MEDIA_MAIN =
1569 CLKCTL4_TUPLE_MUXA(MEDIAMAINCLKSEL_OFFSET, 1), /*!< Attach Main PLL PFD0 clock to MEDIA MAIN clock. */
1570 kFRO0_DIV1_to_MEDIA_MAIN = CLKCTL4_TUPLE_MUXA(MEDIAMAINCLKSEL_OFFSET, 2), /*!< Attach FRO0 to MEDIA MAIN clock. */
1571 kMAIN_PLL_PFD2_to_MEDIA_MAIN =
1572 CLKCTL4_TUPLE_MUXA(MEDIAMAINCLKSEL_OFFSET, 3), /*!< Attach Main PLL PFD2 clock to MEDIA MAIN clock. */
1573
1574 kFRO1_DIV3_to_MEDIA_VDDN_BASE =
1575 CLKCTL4_TUPLE_MUXA(MDNBASECLKSEL_OFFSET, 0), /*!< Attach Fro1 divided-by-3 to Media VDDN Base Clock. */
1576 kFRO1_DIV1_to_MEDIA_VDDN_BASE =
1577 CLKCTL4_TUPLE_MUXA(MDNBASECLKSEL_OFFSET, 1), /*!< Attach Fro1 divided-by-1 to Media VDDN Base Clock. */
1578 kFRO0_DIV3_to_MEDIA_VDDN_BASE =
1579 CLKCTL4_TUPLE_MUXA(MDNBASECLKSEL_OFFSET, 2), /*!< Attach Fro0 divided-by-3 to Media VDDN Base Clock. */
1580 kLPOSC_to_MEDIA_VDDN_BASE =
1581 CLKCTL4_TUPLE_MUXA(MDNBASECLKSEL_OFFSET, 3), /*!< Attach LPOSC clock to Media VDDN Base Clock. */
1582
1583 kFRO1_DIV3_to_MEDIA_VDD2_BASE =
1584 CLKCTL4_TUPLE_MUXA(MD2BASECLKSEL_OFFSET, 0), /*!< Attach Fro1 divided-by-3 to Media VDD2 Base Clock. */
1585 kFRO1_DIV1_to_MEDIA_VDD2_BASE =
1586 CLKCTL4_TUPLE_MUXA(MD2BASECLKSEL_OFFSET, 1), /*!< Attach Fro1 divided-by-1 to Media VDD2 Base Clock. */
1587 kFRO0_DIV3_to_MEDIA_VDD2_BASE =
1588 CLKCTL4_TUPLE_MUXA(MD2BASECLKSEL_OFFSET, 2), /*!< Attach Fro0 divided-by-3 to Media VDD2 Base Clock. */
1589 kLPOSC_to_MEDIA_VDD2_BASE =
1590 CLKCTL4_TUPLE_MUXA(MD2BASECLKSEL_OFFSET, 3), /*!< Attach LPOSC clock to Media VDD2 Base Clock. */
1591
1592 kCOMMON_BASE_to_XSPI2 =
1593 CLKCTL4_TUPLE_MUXA(XSPI2FCLKSEL_OFFSET, 0), /*!< Attach Common VDDN base clock to XSPI2 Functional Clock. */
1594 kAUDIO_PLL_PFD1_to_XSPI2 =
1595 CLKCTL4_TUPLE_MUXA(XSPI2FCLKSEL_OFFSET, 1), /*!< Attach Audio PLL PFD1 clock to XSPI2 Functional Clock. */
1596 kFRO0_DIV1_to_XSPI2 =
1597 CLKCTL4_TUPLE_MUXA(XSPI2FCLKSEL_OFFSET, 2), /*!< Attach FRO0 max clock to XSPI2 Functional Clock. */
1598 kMAIN_PLL_PFD3_to_XSPI2 =
1599 CLKCTL4_TUPLE_MUXA(XSPI2FCLKSEL_OFFSET, 3), /*!< Attach Main PLL PFD3 clock to XSPI2 Functional Clock. */
1600 kNONE_to_XSPI2 = CLKCTL4_TUPLE_MUXA_NONE(XSPI2FCLKSEL_OFFSET, 0), /*!< Attach NONE to XSPI2 Functional Clock. */
1601
1602 k32KHZ_WAKE_to_USB = CLKCTL4_TUPLE_MUXA(USBFCLKSEL_OFFSET, 0), /*!< Attach Wakeup 32K to USB Functional Clock. */
1603 kLPOSC_to_USB = CLKCTL4_TUPLE_MUXA(USBFCLKSEL_OFFSET, 1), /*!< Attach LPOSC_1M to USB Functional Clock. */
1604 kUSB_24MHZ_to_USB =
1605 CLKCTL4_TUPLE_MUXA(USBFCLKSEL_OFFSET, 2), /*!< Attach 24MHz USB OSC clock to USB Functional Clock. */
1606 kNONE_to_USB = CLKCTL4_TUPLE_MUXA_NONE(USBFCLKSEL_OFFSET, 0), /*!< Attach NONE to USB Functional Clock. */
1607
1608 k32KHZ_WAKE_to_EUSB = CLKCTL4_TUPLE_MUXA(EUSBFCLKSEL_OFFSET, 0), /*!< Attach Wakeup 32K to eUSB Functional Clock. */
1609 kLPOSC_to_EUSB = CLKCTL4_TUPLE_MUXA(EUSBFCLKSEL_OFFSET, 1), /*!< Attach LPOSC_1M to eUSB Functional Clock. */
1610 kEUSB_24MHZ_to_EUSB =
1611 CLKCTL4_TUPLE_MUXA(EUSBFCLKSEL_OFFSET, 2), /*!< Attach 24MHz eUSB OSC clock to eUSB Functional Clock. */
1612 kNONE_to_EUSB = CLKCTL4_TUPLE_MUXA_NONE(EUSBFCLKSEL_OFFSET, 0), /*!< Attach NONE to eUSB Functional Clock. */
1613
1614 kMEDIA_VDDN_BASE_to_SDIO0 =
1615 CLKCTL4_TUPLE_MUXA(SDIO0FCLKSEL_OFFSET, 0), /*!< Attach Media VDDN base clock to SDIO0 Functional Clock. */
1616 kAUDIO_PLL_PFD0_to_SDIO0 =
1617 CLKCTL4_TUPLE_MUXA(SDIO0FCLKSEL_OFFSET, 1), /*!< Attach Audio PLL PFD0 clock to SDIO0 Functional Clock. */
1618 kFRO0_DIV1_to_SDIO0 =
1619 CLKCTL4_TUPLE_MUXA(SDIO0FCLKSEL_OFFSET, 2), /*!< Attach FRO0 max clock to SDIO0 Functional Clock. */
1620 kMAIN_PLL_PFD2_to_SDIO0 =
1621 CLKCTL4_TUPLE_MUXA(SDIO0FCLKSEL_OFFSET, 3), /*!< Attach Main PLL PFD2 clock to SDIO0 Functional Clock. */
1622 kNONE_to_SDIO0 = CLKCTL4_TUPLE_MUXA_NONE(SDIO0FCLKSEL_OFFSET, 0), /*!< Attach NONE to SDIO0 Functional Clock. */
1623
1624 kMEDIA_VDDN_BASE_to_SDIO1 =
1625 CLKCTL4_TUPLE_MUXA(SDIO1FCLKSEL_OFFSET, 0), /*!< Attach Media VDDN base clock to SDIO1 Functional Clock. */
1626 kAUDIO_PLL_PFD0_to_SDIO1 =
1627 CLKCTL4_TUPLE_MUXA(SDIO1FCLKSEL_OFFSET, 1), /*!< Attach Audio PLL PFD0 clock to SDIO1 Functional Clock. */
1628 kFRO0_DIV1_to_SDIO1 =
1629 CLKCTL4_TUPLE_MUXA(SDIO1FCLKSEL_OFFSET, 2), /*!< Attach FRO0 max clock to SDIO1 Functional Clock. */
1630 kMAIN_PLL_PFD1_to_SDIO1 =
1631 CLKCTL4_TUPLE_MUXA(SDIO1FCLKSEL_OFFSET, 3), /*!< Attach Main PLL PFD1 clock to SDIO1 Functional Clock. */
1632 kNONE_to_SDIO1 = CLKCTL4_TUPLE_MUXA_NONE(SDIO1FCLKSEL_OFFSET, 0), /*!< Attach NONE to SDIO1 Functional Clock. */
1633
1634 kMEDIA_VDD2_BASE_to_MIPI_DSI_HOST_PHY =
1635 CLKCTL4_TUPLE_MUXA(DPHYCLKSEL_OFFSET, 0), /*!< Attach Media VDD2 base clock to MIPI_DSI_Host PHY Clock. */
1636 kFRO0_DIV1_to_MIPI_DSI_HOST_PHY =
1637 CLKCTL4_TUPLE_MUXA(DPHYCLKSEL_OFFSET, 2), /*!< Attach FRO0 max clock to MIPI_DSI_Host PHY Clock. */
1638 kAUDIO_PLL_PFD2_to_MIPI_DSI_HOST_PHY =
1639 CLKCTL4_TUPLE_MUXA(DPHYCLKSEL_OFFSET, 3), /*!< Attach Audio PLL PFD2 clock to MIPI_DSI_Host PHY Clock. */
1640 kNONE_to_MIPI_DSI_HOST_PHY =
1641 CLKCTL4_TUPLE_MUXA_NONE(DPHYCLKSEL_OFFSET, 0), /*!< Attach NONE to MIPI_DSI_Host PHY Clock. */
1642
1643 kMEDIA_VDD2_BASE_to_MIPI_DPHYESC_CLK = CLKCTL4_TUPLE_MUXA(
1644 DPHYESCCLKSEL_OFFSET, 0), /*!< Attach Media VDD2 base clock to MIPI_DSI_Host DPHY Escape Mode Clock. */
1645 kMAIN_PLL_PFD1_to_MIPI_DPHYESC_CLK = CLKCTL4_TUPLE_MUXA(
1646 DPHYESCCLKSEL_OFFSET, 1), /*!< Attach Main PLL PFD1 clock to MIPI_DSI_Host DPHY Escape Mode Clock. */
1647 kFRO0_DIV1_to_MIPI_DPHYESC_CLK = CLKCTL4_TUPLE_MUXA(
1648 DPHYESCCLKSEL_OFFSET, 2), /*!< Attach FRO0 max clock to MIPI_DSI_Host DPHY Escape Mode Clock. */
1649 kAUDIO_PLL_PFD2_to_MIPI_DPHYESC_CLK = CLKCTL4_TUPLE_MUXA(
1650 DPHYESCCLKSEL_OFFSET, 3), /*!< Attach Audio PLL PFD2 clock to MIPI_DSI_Host DPHY Escape Mode Clock. */
1651 kNONE_to_MIPI_DPHYESC_CLK =
1652 CLKCTL4_TUPLE_MUXA_NONE(DPHYESCCLKSEL_OFFSET, 0), /*!< Attach NONE to MIPI_DSI_Host DPHY Escape Mode Clock. */
1653
1654 kMEDIA_VDD2_BASE_to_VGPU =
1655 CLKCTL4_TUPLE_MUXA(VGPUCLKSEL_OFFSET, 0), /*!< Attach Media VDD2 base clock to VGPU Clock. */
1656 kMAIN_PLL_PFD0_to_VGPU = CLKCTL4_TUPLE_MUXA(VGPUCLKSEL_OFFSET, 1), /*!< Attach Main PLL PFD0 clock to VGPU Clock. */
1657 kFRO0_DIV1_to_VGPU = CLKCTL4_TUPLE_MUXA(VGPUCLKSEL_OFFSET, 2), /*!< Attach FRO0 max clock to VGPU Clock. */
1658 kMAIN_PLL_PFD2_to_VGPU = CLKCTL4_TUPLE_MUXA(VGPUCLKSEL_OFFSET, 3), /*!< Attach Main PLL PFD2 clock to VGPU Clock. */
1659 kNONE_to_VGPU = CLKCTL4_TUPLE_MUXA_NONE(VGPUCLKSEL_OFFSET, 0), /*!< Attach NONE to VGPU Clock. */
1660
1661 kMEDIA_VDD2_BASE_to_LPSPI14 =
1662 CLKCTL4_TUPLE_MUXA(LPSPI14CLKSEL_OFFSET, 0), /*!< Attach Media VDD2 base clock to LPSPI14 Clock. */
1663 kFRO0_DIV1_to_LPSPI14 = CLKCTL4_TUPLE_MUXA(LPSPI14CLKSEL_OFFSET, 1), /*!< Attach FRO0 max clock to LPSPI14 Clock. */
1664 kMAIN_PLL_PFD0_to_LPSPI14 =
1665 CLKCTL4_TUPLE_MUXA(LPSPI14CLKSEL_OFFSET, 2), /*!< Attach Main PLL PFD0 clock to LPSPI14 Clock. */
1666 kFRO1_DIV1_to_LPSPI14 = CLKCTL4_TUPLE_MUXA(LPSPI14CLKSEL_OFFSET, 3), /*!< Attach FRO1 max clock to LPSPI14 Clock. */
1667 kNONE_to_LPSPI14 = CLKCTL4_TUPLE_MUXA_NONE(LPSPI14CLKSEL_OFFSET, 0), /*!< Attach NONE to LPSPI14 Clock. */
1668
1669 kMEDIA_VDD2_BASE_to_LPSPI16 =
1670 CLKCTL4_TUPLE_MUXA(LPSPI16CLKSEL_OFFSET, 0), /*!< Attach Media VDD2 base clock to LPSPI16 Clock. */
1671 kFRO0_DIV1_to_LPSPI16 = CLKCTL4_TUPLE_MUXA(LPSPI16CLKSEL_OFFSET, 1), /*!< Attach FRO0 max clock to LPSPI16 Clock. */
1672 kMAIN_PLL_PFD0_to_LPSPI16 =
1673 CLKCTL4_TUPLE_MUXA(LPSPI16CLKSEL_OFFSET, 2), /*!< Attach Main PLL PFD0 clock to LPSPI16 Clock. */
1674 kFRO1_DIV1_to_LPSPI16 = CLKCTL4_TUPLE_MUXA(LPSPI16CLKSEL_OFFSET, 3), /*!< Attach FRO1 max clock to LPSPI16 Clock. */
1675 kNONE_to_LPSPI16 = CLKCTL4_TUPLE_MUXA_NONE(LPSPI16CLKSEL_OFFSET, 0), /*!< Attach NONE to LPSPI16 Clock. */
1676
1677 kMEDIA_VDD2_BASE_to_FLEXIO =
1678 CLKCTL4_TUPLE_MUXA(FLEXIOCLKSEL_OFFSET, 0), /*!< Attach MEDIA VDD2 base clock to FLEXIO. */
1679 kFRO0_DIV1_to_FLEXIO = CLKCTL4_TUPLE_MUXA(FLEXIOCLKSEL_OFFSET, 1), /*!< Attach FRO0 max clock to FLEXIO. */
1680 kFRO1_DIV1_to_FLEXIO = CLKCTL4_TUPLE_MUXA(FLEXIOCLKSEL_OFFSET, 2), /*!< Attach FRO1 max clock to FLEXIO. */
1681 kMAIN_PLL_PFD3_to_FLEXIO = CLKCTL4_TUPLE_MUXA(FLEXIOCLKSEL_OFFSET, 3), /*!< Attach Main PLL PFD3 clock to FLEXIO. */
1682 kNONE_to_FLEXIO = CLKCTL4_TUPLE_MUXA_NONE(FLEXIOCLKSEL_OFFSET, 0), /*!< Attach NONE to FLEXIO. */
1683
1684 kMEDIA_VDD2_BASE_to_LCDIF =
1685 CLKCTL4_TUPLE_MUXA(LCDIFPIXELCLKSEL_OFFSET, 0), /*!< Attach MEDIA VDD2 base clock to LCDIF. */
1686 kMAIN_PLL_PFD2_to_LCDIF =
1687 CLKCTL4_TUPLE_MUXA(LCDIFPIXELCLKSEL_OFFSET, 1), /*!< Attach Main PLL PFD0 clock to LCDIF. */
1688 kFRO0_DIV1_to_LCDIF = CLKCTL4_TUPLE_MUXA(LCDIFPIXELCLKSEL_OFFSET, 2), /*!< Attach FRO0 max clock to LCDIF. */
1689 kAUDIO_PLL_PFD1_to_LCDIF = CLKCTL4_TUPLE_MUXA(LCDIFPIXELCLKSEL_OFFSET, 3), /*!< Attach Audio PLL PFD1 to LCDIF. */
1690 kNONE_to_LCDIF = CLKCTL4_TUPLE_MUXA_NONE(LCDIFPIXELCLKSEL_OFFSET, 0), /*!< Attach NONE to LCDIF. */
1691 } clock_attach_id_t;
1692
1693 /*! @brief Clock dividers */
1694 typedef enum _clock_div_name
1695 {
1696 #if defined(FSL_CLOCK_DRIVER_COMPUTE)
1697 kCLOCK_DivCmptMainClk = CLKCTL0_TUPLE_MUXA(CMPTMAINCLKDIV_OFFSET, 0), /*!< VDD2_COMP Main clock Divider. */
1698 kCLOCK_DivDspClk = CLKCTL0_TUPLE_MUXA(DSPCPUCLKDIV_OFFSET, 0), /*!< DSP CPU Clk Divider. */
1699 kCLOCK_DivComputeRamClk = CLKCTL0_TUPLE_MUXA(RAMCLKDIV_OFFSET, 0), /*!< RAM Clk Divider. */
1700 kCLOCK_DivTpiuClk = CLKCTL0_TUPLE_MUXA(TPIUCLKDIV_OFFSET, 0), /*!< TIPU Clk Divider. */
1701 kCLOCK_DivXspi0Clk = CLKCTL0_TUPLE_MUXA(XSPI0FCLKDIV_OFFSET, 0), /*!< XSPI0 Clk Divider. */
1702 kCLOCK_DivXspi1Clk = CLKCTL0_TUPLE_MUXA(XSPI1FCLKDIV_OFFSET, 0), /*!< XSPI1 Clk Divider. */
1703 kCLOCK_DivSctClk = CLKCTL0_TUPLE_MUXA(SCTFCLKDIV_OFFSET, 0), /*!< SCT functional Clk Divider. */
1704 kCLOCK_DivUtick0Clk = CLKCTL0_TUPLE_MUXA(UTICK0CLKDIV_OFFSET, 0), /*!< UTICK0 Clk Divider. */
1705 kCLOCK_DivSystickClk = CLKCTL0_TUPLE_MUXA(SYSTICKFCLKDIV_OFFSET, 0), /*!< SYSTICK Clk Divider. */
1706 kCLOCK_DivSai012Clk = CLKCTL0_TUPLE_MUXA(SAI012CLKDIV_OFFSET, 0), /*!< SAI0, SAI1 and SAI2 Clk Divider. */
1707 kCLOCK_DivTrngClk = CLKCTL0_TUPLE_MUXA(TRNGFCLKDIV_OFFSET, 0), /*!< TRNG Clk Divider. */
1708 kCLOCK_DivI3c01PClk = CLKCTL0_TUPLE_MUXA(I3C01PCLKDIV_OFFSET, 0), /*!< I3C01 P-Clk Divider. */
1709 kCLOCK_DivI3c01Clk = CLKCTL0_TUPLE_MUXA(I3C01FCLKDIV_OFFSET, 0), /*!< I3C01 functional Clk Divider. */
1710 kCLOCK_DivClockOut = CLKCTL0_TUPLE_MUXA(CLKOUTCLKDIV_OFFSET, 0), /*!< CLKOUT Divider. */
1711 kCLOCK_DivFcclk0Clk = CLKCTL0_TUPLE_MUXA(FCCLK0DIV_OFFSET, 0), /*!< FCCLK0 Clk Divider. */
1712 kCLOCK_DivFcclk1Clk = CLKCTL0_TUPLE_MUXA(FCCLK1DIV_OFFSET, 0), /*!< FCCLK1 Clk Divider. */
1713 kCLOCK_DivFcclk2Clk = CLKCTL0_TUPLE_MUXA(FCCLK2DIV_OFFSET, 0), /*!< FCCLK2 Clk Divider. */
1714 kCLOCK_DivFcclk3Clk = CLKCTL0_TUPLE_MUXA(FCCLK3DIV_OFFSET, 0), /*!< FCCLK3 Clk Divider. */
1715 kCLOCK_DivCtimer0Clk = CLKCTL0_TUPLE_MUXA(CTIMER0CLKDIV_OFFSET, 0), /*!< CTimer0 Clk Divider. */
1716 kCLOCK_DivCtimer1Clk = CLKCTL0_TUPLE_MUXA(CTIMER1CLKDIV_OFFSET, 0), /*!< CTimer1 Clk Divider. */
1717 kCLOCK_DivCtimer2Clk = CLKCTL0_TUPLE_MUXA(CTIMER2CLKDIV_OFFSET, 0), /*!< CTimer2 Clk Divider. */
1718 kCLOCK_DivCtimer3Clk = CLKCTL0_TUPLE_MUXA(CTIMER3CLKDIV_OFFSET, 0), /*!< CTimer3 Clk Divider. */
1719 kCLOCK_DivCtimer4Clk = CLKCTL0_TUPLE_MUXA(CTIMER4CLKDIV_OFFSET, 0), /*!< CTimer4 Clk Divider. */
1720 #else
1721 kCLOCK_DivLPFlexComm17Clk = CLKCTL1_TUPLE_MUXA(FC17FCLKDIV_OFFSET, 0), /*!< LP_FLEXCOMM17 Clk Divider. */
1722 kCLOCK_DivLPFlexComm18Clk = CLKCTL1_TUPLE_MUXA(FC18FCLKDIV_OFFSET, 0), /*!< LP_FLEXCOMM18 Clk Divider. */
1723 kCLOCK_DivLPFlexComm19Clk = CLKCTL1_TUPLE_MUXA(FC19FCLKDIV_OFFSET, 0), /*!< LP_FLEXCOMM19 Clk Divider. */
1724 kCLOCK_DivLPFlexComm20Clk = CLKCTL1_TUPLE_MUXA(FC20FCLKDIV_OFFSET, 0), /*!< LP_FLEXCOMM20 Clk Divider. */
1725 kCLOCK_DivSenseDspClk = CLKCTL1_TUPLE_MUXA(SENSEDSPCPUCLKDIV_OFFSET, 0), /*!< Sense DSP Clk Divider. */
1726 kCLOCK_DivSai3Clk = CLKCTL1_TUPLE_MUXA(SAI3CLKDIV_OFFSET, 0), /*!< SAI3 FCLK Clk Divider. */
1727 kCLOCK_DivUtick1Clk = CLKCTL1_TUPLE_MUXA(UTICK1CLKDIV_OFFSET, 0), /*!< UTICK1 Functional Clk Divider. */
1728 kCLOCK_DivSystickClk = CLKCTL1_TUPLE_MUXA(SYSTICKFCLKDIV_OFFSET, 0), /*!< SYSTICK Functional Clk Divider. */
1729 kCLOCK_DivCtimer5Clk = CLKCTL1_TUPLE_MUXA(CTIMER5CLKDIV_OFFSET, 0), /*!< CTIMER5 FCLK Clk Divider. */
1730 kCLOCK_DivCtimer6Clk = CLKCTL1_TUPLE_MUXA(CTIMER6CLKDIV_OFFSET, 0), /*!< CTIMER6 FCLK Clk Divider. */
1731 kCLOCK_DivCtimer7Clk = CLKCTL1_TUPLE_MUXA(CTIMER7CLKDIV_OFFSET, 0), /*!< CTIMER7 FCLK Clk Divider. */
1732 kCLOCK_DivI3c23Clk = CLKCTL1_TUPLE_MUXA(I3C23FCLKDIV_OFFSET, 0), /*!< I3C2 and I3C3 Functional Clk Divider. */
1733 #endif
1734 kCLOCK_DivCommonVddnClk = CLKCTL2_TUPLE_MUXA(COMMONVDDNCLKDIV_OFFSET, 0), /*!< Common VDDN Clk Divider. */
1735 kCLOCK_DivSenseMainClk = CLKCTL3_TUPLE_MUXA(SENSEMAINCLKDIV_OFFSET, 0), /*!< VDD1_SENSE Main Clock Divider. */
1736 kCLOCK_DivSenseRamClk = CLKCTL3_TUPLE_MUXA(SENSERAMCLKDIV_OFFSET, 0), /*!< Senese RAM Clk Divider. */
1737 kCLOCK_DivOstimerClk = CLKCTL3_TUPLE_MUXA(OSEVENTFCLKDIV_OFFSET, 0), /*!< OSTIMER Clk Divider. */
1738 kCLOCK_DivSdadcClk = CLKCTL3_TUPLE_MUXA(SDADCFCLKDIV_OFFSET, 0), /*!< SDADC Clk Divider. */
1739 kCLOCK_DivAdcClk = CLKCTL3_TUPLE_MUXA(SARADCFCLKDIV_OFFSET, 0), /*!< SARADC Clk Divider. */
1740 kCLOCK_Div32KhzWakeClk = CLKCTL3_TUPLE_MUXA(A32KHZWAKECLKDIV_OFFSET, 0), /*!< 32KHZ Wakeup Clk Divider. */
1741 kCLOCK_DivMicfil0Clk = CLKCTL3_TUPLE_MUXA(MICFIL0FCLKDIV_OFFSET, 0), /*!< DMIC0 Clk Divider. */
1742 kCLOCK_DivLpi2c15Clk = CLKCTL3_TUPLE_MUXA(LPI2CFCLKDIV_OFFSET, 0), /*!< PMIC LPI2C Clk Divider. */
1743 kCLOCK_DivVdd1ClockOut = CLKCTL3_TUPLE_MUXA(SENSE_CLKOUTCLKDIV_OFFSET, 0), /*!< CLKOUT_VDD1 Clk Divider. */
1744
1745 kCLOCK_DivMediaVddnClk = CLKCTL4_TUPLE_MUXA(MEDIAVDDNCLKDIV_OFFSET, 0), /*!< Media VDDN Clk Divider. */
1746 kCLOCK_DivMediaMainClk = CLKCTL4_TUPLE_MUXA(MEDIAMAINCLKDIV_OFFSET, 0), /*!< Media Main Clk Divider. */
1747 kCLOCK_DivXspi2Clk = CLKCTL4_TUPLE_MUXA(XSPI2FCLKDIV_OFFSET, 0), /*!< XSPI2 Clk Divider. */
1748 kCLOCK_DivSdio0Clk = CLKCTL4_TUPLE_MUXA(SDIO0FCLKDIV_OFFSET, 0), /*!< SDIO0 Clk Divider. */
1749 kCLOCK_DivSdio1Clk = CLKCTL4_TUPLE_MUXA(SDIO1FCLKDIV_OFFSET, 0), /*!< SDIO1 Clk Divider. */
1750 kCLOCK_DivDphyClk = CLKCTL4_TUPLE_MUXA(DPHYCLKDIV_OFFSET, 0), /*!< DPHY Clk Divider. */
1751 kCLOCK_DivDphyEscRxClk = CLKCTL4_TUPLE_MUXA(DPHYESCRXCLKDIV_OFFSET, 0), /*!< DphyEscRx Clk Divider. */
1752 kCLOCK_DivDphyEscTxClk = CLKCTL4_TUPLE_MUXA(DPHYESCTXCLKDIV_OFFSET, 0), /*!< DphyEscTx Clk Divider. */
1753 kCLOCK_DivVgpuClk = CLKCTL4_TUPLE_MUXA(VGPUCLKDIV_OFFSET, 0), /*!< VGPU Clk Divider. */
1754 kCLOCK_DivLpspi14Clk = CLKCTL4_TUPLE_MUXA(LPSPI14CLKDIV_OFFSET, 0), /*!< LPSPI14 Clk Divider. */
1755 kCLOCK_DivLpspi16Clk = CLKCTL4_TUPLE_MUXA(LPSPI16CLKDIV_OFFSET, 0), /*!< LPSPI16 Clk Divider. */
1756 kCLOCK_DivFlexioClk = CLKCTL4_TUPLE_MUXA(FLEXIOCLKDIV_OFFSET, 0), /*!< FLEXIO Clk Divider. */
1757 kCLOCK_DivLcdifClk = CLKCTL4_TUPLE_MUXA(LCDIFPIXELCLKDIV_OFFSET, 0), /*!< LCDIF Pixel Clk Divider. */
1758 kCLOCK_DivLowFreqClk = CLKCTL4_TUPLE_MUXA(LOWFREQCLKDIV_OFFSET, 0), /*!< Low frequency Clk Divider. */
1759 } clock_div_name_t;
1760
1761 /*! @brief FRO output enable. */
1762 typedef enum _clock_fro_output_en
1763 {
1764 kCLOCK_FroDiv1OutEn = FRO_CSR_CLKGATE(0x1U), /*!< Enable Fro Div1 output. */
1765 kCLOCK_FroDiv2OutEn = FRO_CSR_CLKGATE(0x2U), /*!< Enable Fro Div2 output. */
1766 kCLOCK_FroDiv3OutEn = FRO_CSR_CLKGATE(0x4U), /*!< Enable Fro Div3 output. */
1767 kCLOCK_FroDiv6OutEn = FRO_CSR_CLKGATE(0x8U), /*!< Enable Fro Div6 output. */
1768 kCLOCK_FroDiv8OutEn = FRO_CSR_CLKGATE(0x10U), /*!< Enable Fro Div8 output. */
1769 kCLOCK_FroAllOutEn = FRO_CSR_CLKGATE_MASK, /*!< Enable all Fro output. */
1770 } clock_fro_output_en_t;
1771
1772 /*! @brief FRO Interrupt control. */
1773 enum _clock_fro_interrupt
1774 {
1775 kCLOCK_FroTrimUpdateReqInt = FRO_CNFG1_TRUPREQ_IE_MASK, /*!< Trim Update Request Interrupt Enable. */
1776 kCLOCK_FroTuneErrInt = FRO_CNFG1_TUNE_ERR_IE_MASK, /*!< Tune Error Interrupt Enable. */
1777 kCLOCK_FroLossOfLockInt = FRO_CNFG1_LOL_ERR_IE_MASK, /*!< Loss-of-Lock Error Interrupt Enable. */
1778 kCLOCK_FroAllIntterrupt =
1779 kCLOCK_FroTrimUpdateReqInt | kCLOCK_FroTuneErrInt | kCLOCK_FroLossOfLockInt, /*!< All Interrupt Enable. */
1780 };
1781
1782 /*! @brief FRO flags. */
1783 enum _clock_fro_flag
1784 {
1785 kCLOCK_FroTuneOnceDone = FRO_CSR_TUNEONCE_DONE_MASK, /*!< FRO Tune Once Done Flag. */
1786 kCLOCK_FroTrimLock = FRO_CSR_TRIM_LOCK_MASK, /*!< FRO Trim Lock Flag. */
1787 kCLOCK_FroTrimUpdateReq = FRO_CSR_TRUPREQ_MASK, /*!< FRO Trim Update Request Flag. */
1788 kCLOCK_FroTuneErr = FRO_CSR_TUNE_ERR_MASK, /*!< FRO Tune Error Flag. */
1789 kCLOCK_FroLossOfLockErr = FRO_CSR_LOL_ERR_MASK, /*!< FRO Loss-of-lock Error Flag. */
1790 };
1791
1792 /*! @brief FRO configuration. */
1793 typedef struct _clock_fro_config
1794 {
1795 uint32_t targetFreq; /*!< Target frequency. */
1796 uint16_t refDiv; /*!< OSC Reference clock divider. 1 for divide ratio 1.*/
1797 uint16_t trim1DelayUs; /*!< Trim 1 delay in us, minimum is 15us. Used when running in Closed Loop mode and trim
1798 values are updated by 1 decimal unit.*/
1799 uint16_t trim2DelayUs; /*!< Trim 2 delay in us. Used at start of closed loop mode when auto tuner is updating trim
1800 values by 16 decimal unit steps */
1801 uint8_t range; /*!< Trim Expected Count Range. Specifies the + or - counts that the FRO frequency can be off from
1802 TEXPCNT to be considerred locked. The value/100 is the % deviation. */
1803 uint32_t enableInt; /*!< Enable interrupts. Bit mask of #_clock_fro_interrupt. */
1804 bool coarseTrimEn; /*!< Coarse Trim Enable. Set to true to allow autotrimming of the FRO high-byte trim bits. */
1805 } clock_fro_config_t;
1806
1807 /*! @brief Clock Control for each power domain. */
1808 typedef enum _clock_domain_enable
1809 {
1810 kCLOCK_Vdd2CompDomainEnable = 0x1U, /*!< Clock Control of VDD2_COMP Domain. */
1811 kCLOCK_Vdd1SenseDomainEnable = 0x2U, /*!< Clock Control of VDD1_SENSE Domain. */
1812 kCLOCK_Vdd2DspDomainEnable = 0x4U, /*!< Clock Control of VDD2_DSP Domain. */
1813 kCLOCK_Vdd2MediaDomainEnable = 0x8U, /*!< Clock Control of VDD2_MEDIA Domain. */
1814 kCLOCK_VddnMediaDomainEnable = 0x10U, /*!< Clock Control of VDDN_MEDIA Domain. */
1815 kCLOCK_Vdd2ComDomainEnable = 0x20U, /*!< Clock Control of VDD2_COM Domain. */
1816 kCLOCK_VddnComDomainEnable = 0x40U, /*!< Clock Control of VDDN_COM Domain. */
1817 kCLOCK_AllDomainEnable = 0x7FU /*!< Clock Control of all Domain. */
1818 } clock_domain_enable_t;
1819
1820 /*!
1821 * @brief PLL PFD clock name
1822 */
1823 typedef enum _clock_pfd
1824 {
1825 kCLOCK_Pfd0 = 0U, /*!< PLL PFD0 */
1826 kCLOCK_Pfd1 = 1U, /*!< PLL PFD1 */
1827 kCLOCK_Pfd2 = 2U, /*!< PLL PFD2 */
1828 kCLOCK_Pfd3 = 3U, /*!< PLL PFD3 */
1829 } clock_pfd_t;
1830
1831 /*! @brief MainPLL Reference Input Clock Source */
1832 typedef enum _main_pll_src
1833 {
1834 kCLOCK_MainPllFro1Div8 = 0, /*!< FRO1_DIV8 clock */
1835 kCLOCK_MainPllOscClk = 1, /*!< OSC clock */
1836 } main_pll_src_t;
1837
1838 /*! @brief MainPLL Multiplication Factor */
1839 typedef enum _main_pll_mult
1840 {
1841 kCLOCK_MainPllMult16 = 16U, /*!< Divide by 16 */
1842 kCLOCK_MainPllMult17 = 17U, /*!< Divide by 17 */
1843 kCLOCK_MainPllMult18 = 18U, /*!< Divide by 18 */
1844 kCLOCK_MainPllMult19 = 19U, /*!< Divide by 19 */
1845 kCLOCK_MainPllMult20 = 20U, /*!< Divide by 20 */
1846 kCLOCK_MainPllMult21 = 21U, /*!< Divide by 21 */
1847 kCLOCK_MainPllMult22 = 22U, /*!< Divide by 22 */
1848 } main_pll_mult_t;
1849
1850 /*! @brief PLL configuration for MAINPLL */
1851 typedef struct _clock_main_pll_config
1852 {
1853 main_pll_src_t main_pll_src; /*!< Reference Input Clock Source. */
1854 uint32_t numerator; /*!< 30 bit numerator of fractional loop divider. */
1855 uint32_t denominator; /*!< 30 bit numerator of fractional loop divider. */
1856 main_pll_mult_t main_pll_mult; /*!< Multiplication Factor. */
1857 } clock_main_pll_config_t;
1858
1859 /*! @brief AudioPll Reference Input Clock Source */
1860 typedef enum _audio_pll_src
1861 {
1862 kCLOCK_AudioPllFro1Div8 = 0, /*!< FRO1_DIV8 clock */
1863 kCLOCK_AudioPllOscClk = 1, /*!< OSC clock */
1864 } audio_pll_src_t;
1865
1866 /*! @brief AudioPll Multiplication Factor */
1867 typedef enum _audio_pll_mult
1868 {
1869 kCLOCK_AudioPllMult16 = 16U, /*!< Divide by 16 */
1870 kCLOCK_AudioPllMult17 = 17U, /*!< Divide by 17 */
1871 kCLOCK_AudioPllMult18 = 18U, /*!< Divide by 18 */
1872 kCLOCK_AudioPllMult19 = 19U, /*!< Divide by 19 */
1873 kCLOCK_AudioPllMult20 = 20U, /*!< Divide by 20 */
1874 kCLOCK_AudioPllMult21 = 21U, /*!< Divide by 21 */
1875 kCLOCK_AudioPllMult22 = 22U, /*!< Divide by 22 */
1876 } audio_pll_mult_t;
1877
1878 /*! @brief PLL configuration for Audio PLL */
1879 typedef struct _clock_audio_pll_config
1880 {
1881 audio_pll_src_t audio_pll_src; /*!< Reference Input Clock Source. */
1882 uint32_t numerator; /*!< 30 bit numerator of fractional loop divider. */
1883 uint32_t denominator; /*!< 30 bit numerator of fractional loop divider. */
1884 audio_pll_mult_t audio_pll_mult; /*!< Multiplication Factor. */
1885 bool enableVcoOut; /*!< Enable VCO output */
1886 } clock_audio_pll_config_t;
1887
1888 /*! @brief Capacitor Trim Value for OSC32KNP */
1889 typedef enum _osc32k_cap_trim
1890 {
1891 kCLOCK_Osc32kCapPf0 = 0U, /*!< Capacitor Trim Value 0pF. */
1892 kCLOCK_Osc32kCapPf2, /*!< Capacitor Trim Value 2pF. */
1893 kCLOCK_Osc32kCapPf4, /*!< Capacitor Trim Value 4pF. */
1894 kCLOCK_Osc32kCapPf6, /*!< Capacitor Trim Value 6pF. */
1895 kCLOCK_Osc32kCapPf8, /*!< Capacitor Trim Value 8pF. */
1896 kCLOCK_Osc32kCapPf10, /*!< Capacitor Trim Value 10pF. */
1897 kCLOCK_Osc32kCapPf12, /*!< Capacitor Trim Value 12pF. */
1898 kCLOCK_Osc32kCapPf14, /*!< Capacitor Trim Value 14pF. */
1899 kCLOCK_Osc32kCapPf16, /*!< Capacitor Trim Value 16pF. */
1900 kCLOCK_Osc32kCapPf18, /*!< Capacitor Trim Value 18pF. */
1901 kCLOCK_Osc32kCapPf20, /*!< Capacitor Trim Value 20pF. */
1902 kCLOCK_Osc32kCapPf22, /*!< Capacitor Trim Value 22pF. */
1903 kCLOCK_Osc32kCapPf24, /*!< Capacitor Trim Value 24pF. */
1904 kCLOCK_Osc32kCapPf26, /*!< Capacitor Trim Value 26pF. */
1905 kCLOCK_Osc32kCapPf28, /*!< Capacitor Trim Value 28pF. */
1906 kCLOCK_Osc32kCapPf30, /*!< Capacitor Trim Value 30pF. */
1907 } osc32k_cap_trim_t;
1908
1909 /*! @brief configuration for 32K OSC */
1910 typedef struct _clock_osc32k_config_t
1911 {
1912 bool bypass; /*!< Bypass enable. */
1913 bool monitorEnable; /*!< Clock Monitor Enable. */
1914 bool lowPowerMode; /*!< Low-Power (Nano-Power) mode enable. NOTE, can only change from High-Power mode to Nano-Power
1915 mode, and not vice versa. */
1916 osc32k_cap_trim_t cap; /*!< Capacitor Trim Value. */
1917 } clock_osc32k_config_t;
1918
1919 /*******************************************************************************
1920 * API
1921 ******************************************************************************/
1922
1923 #if defined(__cplusplus)
1924 extern "C" {
1925 #endif /* __cplusplus */
1926
1927 /**
1928 * @brief Enable the clock for specific IP.
1929 * @param clk : Clock to be enabled.
1930 * @return Nothing
1931 */
1932 void CLOCK_EnableClock(clock_ip_name_t clk);
1933
1934 /**
1935 * @brief Disable the clock for specific IP.
1936 * @param clk : Clock to be disabled.
1937 * @return Nothing
1938 */
1939 void CLOCK_DisableClock(clock_ip_name_t clk);
1940
1941 /**
1942 * brief Configure the clock selection muxes.
1943 *
1944 * For some of the muxes, there's SEL_EN bit to gate the mux ouput to reduce power, using kNONT_to_XXX to gate the mux
1945 * oupput. used by any peripheral.
1946 * @param connection : Clock to be configured.
1947 * @return Nothing
1948 */
1949 void CLOCK_AttachClk(clock_attach_id_t connection);
1950
1951 /**
1952 * @brief Setup peripheral clock dividers.
1953 * @param div_name : Clock divider name
1954 * @param divider : Value to be divided. Divided clock frequency =
1955 * Undivided clock frequency / divider.
1956 * @return Nothing
1957 */
1958 void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divider);
1959
1960 /*! @brief Return Frequency of selected clock
1961 * @return Frequency of selected clock
1962 */
1963 uint32_t CLOCK_GetFreq(clock_name_t clockName);
1964
1965 #if defined(FSL_CLOCK_DRIVER_COMPUTE) /* Compute domain specific APIs */
1966
1967 /*! @brief Return clock frequency of LP_FLEXCOMM 0 to 13 Clock Source FCCLK
1968 * @param id : index of FCCLK
1969 * @return Frequency of FCCLK
1970 */
1971 uint32_t CLOCK_GetFCClkFreq(uint32_t id);
1972
1973 /*! @brief Return Frequency of compute main clk
1974 * @return Frequency of main clk
1975 */
1976 uint32_t CLOCK_GetComputeMainClkFreq(void);
1977
1978 /*! @brief Return Frequency of compute audio clk
1979 * @return Frequency of audio_clk_cmpt
1980 */
1981 uint32_t CLOCK_GetComputeAudioClkFreq(void);
1982
1983 /*! @brief Return Frequency of Compute DSP clk
1984 * @return Frequency of DSP clk
1985 */
1986 uint32_t CLOCK_GetHifi4ClkFreq(void);
1987
1988 /*! @brief Return Frequency of Compute Base clock
1989 * @return Frequency of compute base clk
1990 */
1991 uint32_t CLOCK_GetComputeBaseClkFreq(void);
1992
1993 /*! @brief Return Frequency of Compute DSP Base clock
1994 * @return Frequency of compute dsp base clk
1995 */
1996 uint32_t CLOCK_GetComputeDspBaseClkFreq(void);
1997
1998 /*! @brief Return Frequency of VDD2_COM Base Clock
1999 * @return Frequency of baseclk_com2
2000 */
2001 uint32_t CLOCK_GetVdd2ComBaseClkFreq(void);
2002
2003 /*! @brief Enable/Disable FRO0 clock for various domains.
2004 * @param domainEnable : Or'ed value of #clock_domain_enable_t to enable
2005 * DRFO0 max clock for certain domain.
2006 */
2007 void CLOCK_EnableFro0ClkForDomain(uint32_t domainEnable);
2008
2009 /*! @brief Return Frequency of sct
2010 * @return Frequency of sct clk
2011 */
2012 uint32_t CLOCK_GetSctClkFreq(void);
2013
2014 /*! @brief Set the Sense AUDIO clock frequency based on the setting from Sense Domain.
2015 *
2016 * This API is used to tell the driver of compute domain about the clcok frequency of sense base clock.
2017 * @param freq : The sense base clock frequency in Hz.
2018 */
CLOCK_SetSenseAudioClkFreq(uint32_t freq)2019 static inline void CLOCK_SetSenseAudioClkFreq(uint32_t freq)
2020 {
2021 g_senseAudioClkFreq = freq;
2022 }
2023
2024 /*! @brief Return Frequency of VDD1 audio clk.
2025 * NOTE, when called from Compute Domain, need to use CLOCK_SetSenseAudioClkFreq to tell the clock driver the audio_clk
2026 * frequency before the API is called.
2027 * @return Frequency of audio_clk
2028 */
2029 uint32_t CLOCK_GetSenseAudioClkFreq(void);
2030
2031 /*! @brief Return Frequency of TPIU clk
2032 * @return Frequency of SAI clk
2033 */
2034 uint32_t CLOCK_GetTpiuClkFreq(void);
2035
2036 /*! @brief Return Frequency of TRNG clk
2037 * @return Frequency of SAI clk
2038 */
2039 uint32_t CLOCK_GetTrngClkFreq(void);
2040
2041 #else /* Sense domain specific APIs */
2042
2043 /*! @brief Return Frequency of VDD1 audio clk
2044 * @return Frequency of audio_clk
2045 */
2046 uint32_t CLOCK_GetSenseAudioClkFreq(void);
2047
2048 /*! @brief Return Frequency of Sense DSP clk
2049 * @return Frequency of Sense DSP clk
2050 */
2051 uint32_t CLOCK_GetHifi1ClkFreq(void);
2052
2053 #endif /* FSL_CLOCK_DRIVER_COMPUTE */
2054
2055 /*! @brief Enable/Disable FRO clock output.
2056 * @param base : base address of FRO.
2057 * @param divOutEnable : Or'ed value of #clock_fro_output_en_t to enable certain clock freq output.
2058 */
2059 void CLOCK_EnableFroClkOutput(FRO_Type *base, uint32_t divOutEnable);
2060
2061 /*! @brief Configure FRO trim values when FRO is configured in Open loop mode.
2062 * @param base : base address of FRO.
2063 * @param trimVal : 12bits trim value.
2064 */
2065 void CLOCK_ConfigFroTrim(FRO_Type *base, uint16_t trimVal);
2066
2067 /*! @brief Disable the FRO clock. This API will disable the FRO clock output and power off FRO.
2068 * @param base : base address of FRO.
2069 */
2070 void CLOCK_DisableFro(FRO_Type *base);
2071
2072 /*! @brief Enable/Disable FRO for close loop mode(autotuner).
2073 * @param base : base address of FRO.
2074 * @param config : The configuration for FRO.
2075 * @param enable: Enable auto tuning mode or not.
2076 * @retval kStatus_Success successfully tuned to the target configuration.
2077 * @retval kStatus_InvalidArgument Invalid arguement.
2078 * @retval kStatus_Fail failed to lock to the target frequency.
2079 */
2080 status_t CLOCK_EnableFroAutoTuning(FRO_Type *base, const clock_fro_config_t *config, bool enable);
2081
2082 /*! @brief Enable FRO clock output with specified frequency.
2083 * @param base : base address of FRO.
2084 * @param targetFreq target fro frequency.
2085 * @param divOutEnable Or'ed value of #clock_fro_output_en_t to enable certain clock freq output.
2086 */
2087 void CLOCK_EnableFroClkFreq(FRO_Type *base, uint32_t targetFreq, uint32_t divOutEnable);
2088
2089 /*! @brief Enable FRO clock output with target frequency using FRO close loop mode.
2090 * For example, to enable FRO2 to ouput 200MHZ:
2091 * @code
2092 * const clock_fro_config_t config = {
2093 * .targetFreq = 200000000U,
2094 * .range = 50U,
2095 * .trim1DelayUs = 15U,
2096 * .trim2DelayUs = 150U,
2097 * .refDiv = 0U,
2098 * .enableInt = 0U,
2099 * .coarseTrimEn = true,
2100 * };
2101 * CLOCK_EnableFroClkFreqCloseLoop(FRO2, &config, kCLOCK_FroAllOutEn);
2102 * @endcode
2103 * @param base : base address of FRO.
2104 * @param config : The configuration for FRO.
2105 * @param divOutEnable : Or'ed value of clock_fro_output_en_t to enable certain clock freq output.
2106 * @retval kStatus_Success successfully tuned to the target configuration.
2107 * @retval kStatus_InvalidArgument Invalid arguement.
2108 * @retval kStatus_Fail failed to lock to the target frequency.
2109 */
2110 status_t CLOCK_EnableFroClkFreqCloseLoop(FRO_Type *base, const clock_fro_config_t *config, uint32_t divOutEnable);
2111
2112 /*! @brief Get FRO flags.
2113 * @param base : base address of FRO.
2114 * @param flags Or'ed value of #_clock_fro_flag.
2115 */
2116 uint32_t CLOCK_GetFroFlags(FRO_Type *base);
2117
2118 /*! @brief Clear FRO flags.
2119 * @param base : base address of FRO.
2120 * @param flags Or'ed value of #_clock_fro_flag to clear.
2121 */
CLOCK_ClearFroFlags(FRO_Type * base,uint32_t flags)2122 inline static void CLOCK_ClearFroFlags(FRO_Type *base, uint32_t flags)
2123 {
2124 base->CSR.CLR = flags;
2125 }
2126
2127 /*! @brief Return Frequency of FRO clk
2128 * @param id FRO index
2129 * @return Frequency of FRO clk
2130 */
2131 uint32_t CLOCK_GetFroClkFreq(uint32_t id);
2132
2133 /*! @brief Return Frequency of sense main clk
2134 * @return Frequency of main clk
2135 */
2136 uint32_t CLOCK_GetSenseMainClkFreq(void);
2137
2138 /*! @brief Return Frequency of MAINPLL
2139 * @return Frequency of MAINPLL
2140 */
2141 uint32_t CLOCK_GetMainPllFreq(void);
2142
2143 /*! @brief Get current output frequency of specific Main PLL PFD.
2144 * @param pfd : pfd name to get frequency.
2145 * @return Frequency of MainPLL PFD.
2146 */
2147 uint32_t CLOCK_GetMainPfdFreq(clock_pfd_t pfd);
2148
2149 /*! @brief Return Frequency of AUDIO PLL
2150 * @return Frequency of AUDIO PLL
2151 */
2152 uint32_t CLOCK_GetAudioPllFreq(void);
2153
2154 /*! @brief Get current output frequency of specific Audio PLL PFD.
2155 * @param pfd : pfd name to get frequency.
2156 * @return Frequency of AUDIO PLL PFD.
2157 */
2158
2159 uint32_t CLOCK_GetAudioPfdFreq(clock_pfd_t pfd);
2160 /*! @brief Return Frequency of High-Freq output of FRO
2161 * @return Frequency of High-Freq output of FRO
2162 */
2163
2164 /*! @brief Return Frequency of sys osc Clock
2165 * @return Frequency of sys osc Clock. Or CLK_IN pin frequency.
2166 */
CLOCK_GetXtalInClkFreq(void)2167 static inline uint32_t CLOCK_GetXtalInClkFreq(void)
2168 {
2169 return ((g_xtalFreq != 0U) ? g_xtalFreq : g_clkinFreq);
2170 }
2171
2172 /*! @brief Return Frequency of Sense Base clock
2173 * @return Frequency of sense base clk
2174 */
2175 uint32_t CLOCK_GetSenseBaseClkFreq(void);
2176
2177 /*! @brief Enable/Disable sys osc clock from external crystal clock.
2178 * @param enable : true to enable system osc clock, false to bypass system
2179 * osc.
2180 * @param enableLowPower : true to enable low power mode, false to enable high
2181 * gain mode.
2182 * @param delay_us : Delay time after OSC power up.
2183 */
2184 void CLOCK_EnableSysOscClk(bool enable, bool enableLowPower, uint32_t delay_us);
2185
2186 /*! @brief Return Frequency of VDDN_COM Base Clock
2187 * @return Frequency of baseclk_comn
2188 */
2189 uint32_t CLOCK_GetVddnComBaseClkFreq(void);
2190
2191 /*! @brief Return Frequency of VDDN_MEDIA Base Clock
2192 * @return Frequency of baseclk_mdn
2193 */
2194 uint32_t CLOCK_GetVddnMediaBaseClkFreq(void);
2195
2196 /*! @brief Return Frequency of VDD2_MEDIA Base Clock
2197 * @return Frequency of baseclk_md2
2198 */
2199 uint32_t CLOCK_GetVdd2MediaBaseClkFreq(void);
2200
2201 /*! @brief Return Frequency of MEDIA_MAIN Clock
2202 * @return Frequency of media_main_clk
2203 */
2204 uint32_t CLOCK_GetMediaMainClkFreq(void);
2205
2206 /*! @brief Return Frequency of MEDIA_VDDN Clock
2207 * @return Frequency of media_vddn_clk
2208 */
2209 uint32_t CLOCK_GetMediaVddnClkFreq(void);
2210
2211 /*! @brief Enable/Disable FRO2 clock for various domains.
2212 * @param domainEnable : Or'ed value of #clock_domain_enable_t to enable
2213 * DRFO2 max clock for certain domain.
2214 */
2215 void CLOCK_EnableFro2ClkForDomain(uint32_t domainEnable);
2216
2217 /*! @brief Enable/Disable MainPLL PFD clock for various domains.
2218 *
2219 * Enables PFD clock of MainPLL for various domains. Each PFD clock of MainPLL can be sent to various domain. To reduce
2220 * power consumption, turn off the PFD in the domain when this PFD is not configured.
2221 * @param pfd : Which PFD clock to control.
2222 * @param domainEnable : Or'ed value of #clock_domain_enable_t to enable
2223 * clock for certain domain.
2224 */
2225 void CLOCK_EnableMainPllPfdClkForDomain(clock_pfd_t pfd, uint32_t domainEnable);
2226
2227 /*! @brief Enable/Disable AUDIO PFD clock for various domains.
2228 *
2229 * Enables PFD clock of AUDIO for various domains. Each PFD clock of AUDIO can be sent to various domain. To reduce
2230 * power consumption, turn off the PFD in the domain when this PFD is not configured.
2231 * @param pfd : Which PFD clock to control.
2232 * @param domainEnable : Or'ed value of #clock_domain_enable_t to enable
2233 * clock for certain domain.
2234 */
2235 void CLOCK_EnableAudioPllPfdClkForDomain(clock_pfd_t pfd, uint32_t domainEnable);
2236
2237 /*! @brief Enable/Disable AUDIO VCO clock for various domains.
2238 *
2239 * VCO clock of Audio PLL can be sent to various domains to reduce power consumption when VCO is not set to use in such
2240 * domain. This VCO can be disabled for such domain.
2241 * @param domainEnable : Or'ed value of #clock_domain_enable_t to enable
2242 * clock for certain domain.
2243 */
2244 void CLOCK_EnableAudioPllVcoClkForDomain(uint32_t domainEnable);
2245
2246 /*! @brief Initialize the Main PLL.
2247 * @param config : Configuration to set to PLL.
2248 */
2249 void CLOCK_InitMainPll(const clock_main_pll_config_t *config);
2250
2251 /*! brief Deinit the Main PLL.
2252 * param none.
2253 */
CLOCK_DeinitMainPll(void)2254 static inline void CLOCK_DeinitMainPll(void)
2255 {
2256 /* Set Main PLL Reset & HOLDRING_OFF_ENA */
2257 CLKCTL2->MAINPLL0CTL0 |= CLKCTL2_MAINPLL0CTL0_HOLD_RING_OFF_ENA_MASK | CLKCTL2_MAINPLL0CTL0_RESET_MASK;
2258 /* Power down Main PLL*/
2259 #if defined(FSL_CLOCK_DRIVER_COMPUTE)
2260 SLEEPCON0->RUNCFG_SET = SLEEPCON0_RUNCFG_PLLLDO_PD_MASK | SLEEPCON0_RUNCFG_PLLANA_PD_MASK;
2261 #else
2262 SLEEPCON1->RUNCFG_SET = SLEEPCON1_RUNCFG_PLLLDO_PD_MASK | SLEEPCON1_RUNCFG_PLLANA_PD_MASK;
2263 #endif
2264 }
2265 /*! @brief Initialize the Main PLL PFD.
2266 * @param pfd : Which PFD clock to enable.
2267 * @param divider : The PFD divider value.
2268 * @note It is recommended that PFD settings are kept between 12-35.
2269 */
2270 void CLOCK_InitMainPfd(clock_pfd_t pfd, uint8_t divider);
2271
2272 /*! brief Disable the Main PLL PFD.
2273 * param pfd : Which PFD clock to disable.
2274 */
CLOCK_DeinitMainPfd(clock_pfd_t pfd)2275 static inline void CLOCK_DeinitMainPfd(clock_pfd_t pfd)
2276 {
2277 CLKCTL2->MAINPLL0PFD |= ((uint32_t)CLKCTL2_AUDIOPLL0PFD_PFD0_CLKGATE_MASK << (8UL * (uint32_t)pfd));
2278 }
2279
2280 /*! @brief Initialize the audio PLL.
2281 * @param config : Configuration to set to PLL.
2282 */
2283 void CLOCK_InitAudioPll(const clock_audio_pll_config_t *config);
2284
2285 /*! brief Deinit the Audio PLL.
2286 * param none.
2287 */
CLOCK_DeinitAudioPll(void)2288 static inline void CLOCK_DeinitAudioPll(void)
2289 {
2290 /* Set Audio PLL Reset & HOLDRINGOFF_ENA */
2291 CLKCTL2->AUDIOPLL0CTL0 |= CLKCTL2_AUDIOPLL0CTL0_HOLD_RING_OFF_ENA_MASK | CLKCTL2_AUDIOPLL0CTL0_RESET_MASK;
2292 /* Power down Audio PLL */
2293 #if defined(FSL_CLOCK_DRIVER_COMPUTE)
2294 /* Power down Audio PLL before change fractional settings */
2295 SLEEPCON0->RUNCFG_SET = SLEEPCON0_RUNCFG_AUDPLLLDO_PD_MASK | SLEEPCON0_RUNCFG_AUDPLLANA_PD_MASK;
2296 #else
2297 SLEEPCON1->RUNCFG_SET = SLEEPCON1_RUNCFG_AUDPLLLDO_PD_MASK | SLEEPCON1_RUNCFG_AUDPLLANA_PD_MASK;
2298 #endif
2299 }
2300
2301 /*! @brief Initialize the audio PLL PFD.
2302 * @param pfd : Which PFD clock to enable.
2303 * @param divider : The PFD divider value.
2304 * @note It is recommended that PFD settings are kept between 12-35.
2305 */
2306 void CLOCK_InitAudioPfd(clock_pfd_t pfd, uint8_t divider);
2307 /*! brief Disable the audio PLL PFD.
2308 * param pfd : Which PFD clock to disable.
2309 */
CLOCK_DeinitAudioPfd(uint32_t pfd)2310 static inline void CLOCK_DeinitAudioPfd(uint32_t pfd)
2311 {
2312 CLKCTL2->AUDIOPLL0PFD |= ((uint32_t)CLKCTL2_AUDIOPLL0PFD_PFD0_CLKGATE_MASK << (8UL * (uint32_t)pfd));
2313 }
2314
2315 /*! @brief Return Frequency of Lower power osc
2316 * @return Frequency of LPOSC
2317 */
CLOCK_GetLpOscFreq(void)2318 static inline uint32_t CLOCK_GetLpOscFreq(void)
2319 {
2320 return CLK_LPOSC_1MHZ;
2321 }
2322
2323 /*! @brief Return Frequency of sys osc Clock
2324 * @return Frequency of sys osc Clock. Or CLK_IN pin frequency.
2325 */
CLOCK_GetSysOscFreq(void)2326 static inline uint32_t CLOCK_GetSysOscFreq(void)
2327 {
2328 return (CLKCTL2->SYSOSCBYPASS == 0U) ? g_xtalFreq : ((CLKCTL2->SYSOSCBYPASS == 1U) ? g_clkinFreq : 0U);
2329 }
2330
2331 /*! @brief Return Frequency of MCLK Input Clock
2332 * @return Frequency of MCLK input Clock.
2333 */
CLOCK_GetMclkInClkFreq(void)2334 static inline uint32_t CLOCK_GetMclkInClkFreq(void)
2335 {
2336 return g_mclkFreq;
2337 }
2338
2339 /*! @brief Return Frequency of 32kHz osc
2340 * @return Frequency of 32kHz osc
2341 */
2342 uint32_t CLOCK_GetOsc32KFreq(void);
2343
2344 /*! @brief Enables OSC32KNP
2345 * @param config : configuration set to OSC32KNP
2346 */
2347 void CLOCK_EnableOsc32K(clock_osc32k_config_t *config);
2348
2349 /*! @brief Disable OSC32KNP
2350 */
CLOCK_DisableOsc32K(void)2351 static inline void CLOCK_DisableOsc32K(void)
2352 {
2353 OSC32KNP->CTRL |= OSC32KNP_CTRL_OSC_DIS_MASK;
2354 }
2355
2356 /*! @brief Return Frequency of 32khz wake clk
2357 * @return Frequency of 32kHz wake clk
2358 */
2359 uint32_t CLOCK_GetWakeClk32KFreq(void);
2360
2361 /*!
2362 * @brief Set the XTALIN (system OSC) frequency based on board setting.
2363 * NOTE, when SOSC is used, either CLOCK_SetXtalFreq or CLOCK_SetClkinFreq(But NOT both.) should be called to tell
2364 * driver the clock frequency connected to SOSC module.
2365 *
2366 * @param freq : The XTAL input clock frequency in Hz.
2367 */
CLOCK_SetXtalFreq(uint32_t freq)2368 static inline void CLOCK_SetXtalFreq(uint32_t freq)
2369 {
2370 g_xtalFreq = freq;
2371 g_clkinFreq = 0U;
2372 }
2373
2374 /*!
2375 * @brief Set the CLKIN (CLKIN pin) frequency based on board setting.
2376 *
2377 * @param freq : The CLK_IN pin input clock frequency in Hz.
2378 */
CLOCK_SetClkinFreq(uint32_t freq)2379 static inline void CLOCK_SetClkinFreq(uint32_t freq)
2380 {
2381 g_clkinFreq = freq;
2382 g_xtalFreq = 0U;
2383 }
2384
2385 /*!
2386 * @brief Set the 32KHz external input frequency based on board setting.
2387 *
2388 * @param freq : The 32KHz external pin input clock frequency in Hz.
2389 */
CLOCK_Set32kClkinFreq(uint32_t freq)2390 static inline void CLOCK_Set32kClkinFreq(uint32_t freq)
2391 {
2392 g_32kClkinFreq = freq;
2393 }
2394
2395 /*!
2396 * @brief Set the MCLK IN frequency based on board setting.
2397 *
2398 * @param freq : The MCLK input clock frequency in Hz.
2399 */
CLOCK_SetMclkFreq(uint32_t freq)2400 static inline void CLOCK_SetMclkFreq(uint32_t freq)
2401 {
2402 g_mclkFreq = freq;
2403 }
2404
2405 /*! @brief Return Frequency of Core/system clock
2406 * @return Frequency of core or system Clock
2407 */
CLOCK_GetCoreSysClkFreq(void)2408 static inline uint32_t CLOCK_GetCoreSysClkFreq(void)
2409 {
2410 return CLOCK_GetFreq(kCLOCK_CoreSysClk);
2411 }
2412
2413 /*! @brief Return Frequency of XSPI function clock
2414 * @param id : XSPI index to get frequency.
2415 * @return Frequency of XSPI functional Clock
2416 */
2417 uint32_t CLOCK_GetXspiClkFreq(uint32_t id);
2418
2419 /*! @brief Return Frequency of UTICK function clock
2420 * @return Frequency of UTICK functional Clock
2421 */
2422 uint32_t CLOCK_GetUtickClkFreq(void);
2423
2424 /*! @brief Return Frequency of systick clk
2425 * @return Frequency of systick clk
2426 */
2427 uint32_t CLOCK_GetSystickClkFreq(void);
2428
2429 /*! @brief Return Frequency of WDT clk
2430 * @param id : WDT index to get frequency.
2431 * @return Frequency of WDT clk
2432 */
2433 uint32_t CLOCK_GetWdtClkFreq(uint32_t id);
2434
2435 /*! @brief Return Frequency of ACMP clk
2436 * @return Frequency of ACMP clk
2437 */
2438 uint32_t CLOCK_GetAcmpClkFreq(void);
2439
2440 /*! @brief Return Frequency of SAI clk
2441 * @return Frequency of SAI clk
2442 */
2443 uint32_t CLOCK_GetSaiClkFreq(void);
2444
2445 /*! @brief Return Frequency of USB clk
2446 * @return Frequency of USB clk
2447 */
2448 uint32_t CLOCK_GetUsbClkFreq(void);
2449
2450 /*! @brief Return Frequency of I3C clk
2451 * @return Frequency of I3C clk
2452 */
2453 uint32_t CLOCK_GetI3cClkFreq(void);
2454
2455 /*! @brief Return Frequency of Flexcomm functional Clock
2456 * @param id : flexcomm index to get frequency.
2457 * @return Frequency of Flexcomm functional Clock
2458 */
2459 uint32_t CLOCK_GetLPFlexCommClkFreq(uint32_t id);
2460
2461 /*! @brief Return Frequency of LPI2C functional Clock
2462 * @param id : LPI2C index to get frequency.
2463 * @return Frequency of LPI2C functional Clock
2464 */
2465 uint32_t CLOCK_GetLPI2cClkFreq(uint32_t id);
2466
2467 /*! @brief Return Frequency of LPSPI functional Clock
2468 * @param id : LPSPI index to get frequency.
2469 * @return Frequency of LPSPI functional Clock
2470 */
2471 uint32_t CLOCK_GetLPSpiClkFreq(uint32_t id);
2472
2473 /*! @brief Return Frequency of Flexio functional Clock
2474 * @return Frequency of Flexcomm functional Clock
2475 */
2476 uint32_t CLOCK_GetFlexioClkFreq(void);
2477
2478 /*! @brief Return Frequency of OSTIMER functional Clock
2479 * @return Frequency of OSTIMER functional Clock
2480 */
2481 uint32_t CLOCK_GetOSTimerClkFreq(void);
2482
2483 /*! @brief Return Frequency of MICFIL functional Clock
2484 * @return Frequency of MICFIL functional Clock
2485 */
2486 uint32_t CLOCK_GetMicfilClkFreq(void);
2487
2488 /*! @brief Return Frequency of Ctimer Clock
2489 * @param id : ctimer index to get frequency.
2490 * @return Frequency of Ctimer Clock
2491 */
2492 uint32_t CLOCK_GetCTimerClkFreq(uint32_t id);
2493
2494 /*! @brief Return Frequency of VDD2 ClockOut
2495 * @return Frequency of ClockOut
2496 */
2497 uint32_t CLOCK_GetClockOutClkFreq(void);
2498
2499 /*! @brief Return Frequency of VDD1 Clock Out
2500 * @return Frequency of ClockOut of sense domain
2501 */
2502 uint32_t CLOCK_GetVdd1ClockOutClkFreq(void);
2503
2504 /*! @brief Return Frequency of Adc Clock
2505 * @return Frequency of Adc Clock.
2506 */
2507 uint32_t CLOCK_GetAdcClkFreq(void);
2508
2509 /*! @brief Return Frequency of SDADC Clock
2510 * @return Frequency of SDADC Clock.
2511 */
2512 uint32_t CLOCK_GetSdAdcClkFreq(void);
2513
2514 /*! @brief Return Frequency of VGPU functional Clock
2515 * @return Frequency of VGPU functional Clock
2516 */
2517 uint32_t CLOCK_GetVgpuClkFreq(void);
2518
2519 /*! @brief Return Frequency of LCDIF pixel Clock
2520 * @return Frequency of LCDIF pixel Clock
2521 */
2522 uint32_t CLOCK_GetLcdifClkFreq(void);
2523
2524 /*! @brief Return Frequency of MIPI DPHY functional Clock
2525 * @return Frequency of MIPI DPHY functional Clock
2526 */
2527 uint32_t CLOCK_GetMipiDphyClkFreq(void);
2528
2529 /*! @brief Return Frequency of MIPI DPHY Esc RX functional Clock
2530 * @return Frequency of MIPI DPHY Esc RX functional Clock
2531 */
2532 uint32_t CLOCK_GetMipiDphyEscRxClkFreq(void);
2533
2534 /*! @brief Return Frequency of MIPI DPHY Esc Tx functional Clock
2535 * @return Frequency of MIPI DPHY Esc Tx functional Clock
2536 */
2537 uint32_t CLOCK_GetMipiDphyEscTxClkFreq(void);
2538
2539 /*! @brief Return Frequency of USDHC Clock
2540 * @param id : uSDHC index to get frequency.
2541 * @return Frequency of USDHC Clock
2542 */
2543 uint32_t CLOCK_GetUsdhcClkFreq(uint32_t id);
2544
2545 /*! brief Enable USB HS PHY PLL clock.
2546 *
2547 * This function enables the internal 480MHz USB PHY PLL clock.
2548 *
2549 * param src USB HS PHY PLL clock source.
2550 * param freq The frequency specified by src.
2551 * retval true The clock is set successfully.
2552 * retval false The clock source is invalid to get proper USB HS clock.
2553 */
2554 bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq);
2555
2556 /*! brief Enable USB HS clock.
2557 *
2558 * This function only enables the access to USB HS prepheral, upper layer
2559 * should first call the ref CLOCK_EnableUsbhs0PhyPllClock to enable the PHY
2560 * clock to use USB HS.
2561 *
2562 * param src USB HS does not care about the clock source, here must be ref kCLOCK_UsbSrcUnused.
2563 * param freq USB HS does not care about the clock source, so this parameter is ignored.
2564 * retval true The clock is set successfully.
2565 * retval false The clock source is invalid to get proper USB HS clock.
2566 */
2567 bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq);
2568
2569 /*! brief Disable USB HS PHY PLL clock.
2570 *
2571 * This function disables USB HS PHY PLL clock.
2572 */
2573 void CLOCK_DisableUsbhs0PhyPllClock(void);
2574
2575 #if defined(__cplusplus)
2576 }
2577 #endif /* __cplusplus */
2578
2579 /*! @} */
2580
2581 #endif /* FSL_CLOCK_H_ */
2582
