1 /*
2 * Copyright 2023-2024 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #include "fsl_clock.h"
9 #include "fsl_common.h"
10
11 /*******************************************************************************
12 * Definitions
13 ******************************************************************************/
14 /* Component ID definition, used by tools. */
15 #ifndef FSL_COMPONENT_ID
16 #define FSL_COMPONENT_ID "platform.drivers.clock"
17 #endif
18
19 #define FRO0_DEFAULT_CLOCK_FREQ 300000000U
20 #define FRO1_MAX_CLOCK_FREQ 192000000U
21 #define FRO2_DEFAULT_CLOCK_FREQ 196000000U
22
23 #define FRO_MIN_CLOCK_FREQ 150000000U
24 #define FRO_MAX_CLOCK_FREQ 300000000U
25
26 /*******************************************************************************
27 * Variables
28 ******************************************************************************/
29 #if defined(FSL_CLOCK_DRIVER_COMPUTE)
30 /* Array of LPUART peripheral base address. */
31 static FRO_Type *const s_froBases[] = FRO_BASE_PTRS;
32 volatile uint32_t g_senseAudioClkFreq = 0U;
33 #endif
34
35 /* External XTAL (OSC) clock frequency. */
36 volatile uint32_t g_xtalFreq = 24000000U;
37 /* External CLK_IN pin clock frequency. */
38 volatile uint32_t g_clkinFreq = 0U;
39 /* External MCLK IN clock frequency. */
40 volatile uint32_t g_mclkFreq = 0U;
41 /* External 32 kHz input clock pin clock frequency. */
42 volatile uint32_t g_32kClkinFreq = 0U;
43
44 /*******************************************************************************
45 * Code
46 ******************************************************************************/
CLOCK_EnableClock(clock_ip_name_t clk)47 void CLOCK_EnableClock(clock_ip_name_t clk)
48 {
49 uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk);
50 uint32_t bitMask = 1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk);
51
52 switch (index)
53 {
54 #if defined(FSL_CLOCK_DRIVER_COMPUTE) || defined(FSL_CLOCK_DRIVER_MEDIA)
55 case CLK_CTL0_PSCCTL0:
56 CLKCTL0->PSCCTL0_SET = bitMask;
57 while ((CLKCTL0->PSCCTL0 & bitMask) == 0U)
58 {
59 }
60 break;
61 case CLK_CTL0_PSCCTL1:
62 CLKCTL0->PSCCTL1_SET = bitMask;
63 while ((CLKCTL0->PSCCTL1 & bitMask) == 0U)
64 {
65 }
66 break;
67 case CLK_CTL0_PSCCTL2:
68 CLKCTL0->PSCCTL2_SET = bitMask;
69 while ((CLKCTL0->PSCCTL2 & bitMask) == 0U)
70 {
71 }
72 break;
73 case CLK_CTL0_PSCCTL3:
74 CLKCTL0->PSCCTL3_SET = bitMask;
75 while ((CLKCTL0->PSCCTL3 & bitMask) == 0U)
76 {
77 }
78 break;
79 case CLK_CTL0_PSCCTL4:
80 CLKCTL0->PSCCTL4_SET = bitMask;
81 while ((CLKCTL0->PSCCTL4 & bitMask) == 0U)
82 {
83 }
84 break;
85 case CLK_CTL0_PSCCTL5:
86 CLKCTL0->PSCCTL5_SET = bitMask;
87 while ((CLKCTL0->PSCCTL5 & bitMask) == 0U)
88 {
89 }
90 break;
91 case CLK_CTL3_PSCCTL0:
92 CLKCTL3->PSCCTL0_COMP_SET = bitMask;
93 while ((CLKCTL3->PSCCTL0_COMP & bitMask) == 0U)
94 {
95 }
96 break;
97 case CLK_CTL4_PSCCTL0:
98 CLKCTL4->PSCCTL0_MEDIA_SET = bitMask;
99 while ((CLKCTL4->PSCCTL0_MEDIA & bitMask) == 0U)
100 {
101 }
102 break;
103 case CLK_CTL4_PSCCTL1:
104 CLKCTL4->PSCCTL1_MEDIA_SET = bitMask;
105 while ((CLKCTL4->PSCCTL1_MEDIA & bitMask) == 0U)
106 {
107 }
108 break;
109 case SYSCON0_SEC_CLK_CTRL:
110 SYSCON0->SEC_CLK_CTRL_SET = bitMask;
111 while ((SYSCON0->SEC_CLK_CTRL & bitMask) == 0U)
112 {
113 }
114 break;
115 case CLKCTL0_ONE_SRC_CLKSLICE_ENABLE:
116 CLKCTL0->ONE_SRC_CLKSLICE_ENABLE |= bitMask;
117 while ((CLKCTL0->ONE_SRC_CLKSLICE_ENABLE & bitMask) == 0U)
118 {
119 }
120 break;
121 case CLKCTL3_ONE_SRC_CLKSLICE_ENABLE:
122 CLKCTL3->ONE_SRC_CLKSLICE_ENABLE_COMP |= bitMask;
123 while ((CLKCTL3->ONE_SRC_CLKSLICE_ENABLE_COMP & bitMask) == 0U)
124 {
125 }
126 break;
127 case CLKCTL4_ONE_SRC_CLKSLICE_ENABLE:
128 CLKCTL4->ONE_SRC_CLKSLICE_ENABLE |= bitMask;
129 while ((CLKCTL4->ONE_SRC_CLKSLICE_ENABLE & bitMask) == 0U)
130 {
131 }
132 break;
133 #else /* Sense domain */
134 case CLK_CTL1_PSCCTL0:
135 CLKCTL1->PSCCTL0_SET = bitMask;
136 while ((CLKCTL1->PSCCTL0 & bitMask) == 0U)
137 {
138 }
139 break;
140 case CLK_CTL1_PSCCTL1:
141 CLKCTL1->PSCCTL1_SET = bitMask;
142 while ((CLKCTL1->PSCCTL1 & bitMask) == 0U)
143 {
144 }
145 break;
146 case CLK_CTL3_PSCCTL0:
147 CLKCTL3->PSCCTL0_SENS_SET = bitMask;
148 while ((CLKCTL3->PSCCTL0_SENS & bitMask) == 0U)
149 {
150 }
151 break;
152 case CLK_CTL4_PSCCTL0:
153 CLKCTL4->PSCCTL0_SENS_SET = bitMask;
154 while ((CLKCTL4->PSCCTL0_SENS & bitMask) == 0U)
155 {
156 }
157 break;
158 case CLK_CTL4_PSCCTL1:
159 CLKCTL4->PSCCTL1_SENS_SET = bitMask;
160 while ((CLKCTL4->PSCCTL1_SENS & bitMask) == 0U)
161 {
162 }
163 break;
164 case CLKCTL3_ONE_SRC_CLKSLICE_ENABLE:
165 CLKCTL3->ONE_SRC_CLKSLICE_ENABLE_SENSE |= bitMask;
166 while ((CLKCTL3->ONE_SRC_CLKSLICE_ENABLE_SENSE & bitMask) == 0U)
167 {
168 }
169 break;
170 case CLKCTL4_ONE_SRC_CLKSLICE_ENABLE:
171 CLKCTL4->ONE_SRC_CLKSLICE_ENABLE_SENSE |= bitMask;
172 while ((CLKCTL4->ONE_SRC_CLKSLICE_ENABLE_SENSE & bitMask) == 0U)
173 {
174 }
175 break;
176 #endif /* FSL_CLOCK_DRIVER_COMPUTE */
177 case CLK_CTL2_PSCCTL0:
178 CLKCTL2->PSCCTL0_SET = bitMask;
179 while ((CLKCTL2->PSCCTL0 & bitMask) == 0U)
180 {
181 }
182 break;
183 case SYSCON3_SEC_CLK_CTRL:
184 SYSCON3->SEC_CLK_CTRL_SET = bitMask;
185 while ((SYSCON3->SEC_CLK_CTRL & bitMask) == 0U)
186 {
187 }
188 break;
189 default:
190 /* Should not go here. */
191 assert(false);
192 break;
193 }
194 }
195
CLOCK_DisableClock(clock_ip_name_t clk)196 void CLOCK_DisableClock(clock_ip_name_t clk)
197 {
198 uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk);
199 switch (index)
200 {
201 #if defined(FSL_CLOCK_DRIVER_COMPUTE) || defined(FSL_CLOCK_DRIVER_MEDIA)
202 case CLK_CTL0_PSCCTL0:
203 CLKCTL0->PSCCTL0_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
204 break;
205 case CLK_CTL0_PSCCTL1:
206 CLKCTL0->PSCCTL1_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
207 break;
208 case CLK_CTL0_PSCCTL2:
209 CLKCTL0->PSCCTL2_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
210 break;
211 case CLK_CTL0_PSCCTL3:
212 CLKCTL0->PSCCTL3_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
213 break;
214 case CLK_CTL0_PSCCTL4:
215 CLKCTL0->PSCCTL4_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
216 break;
217 case CLK_CTL0_PSCCTL5:
218 CLKCTL0->PSCCTL5_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
219 break;
220 case CLK_CTL3_PSCCTL0:
221 CLKCTL3->PSCCTL0_COMP_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
222 break;
223 case CLK_CTL4_PSCCTL0:
224 CLKCTL4->PSCCTL0_MEDIA_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
225 break;
226 case CLK_CTL4_PSCCTL1:
227 CLKCTL4->PSCCTL1_MEDIA_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
228 break;
229 case SYSCON0_SEC_CLK_CTRL:
230 SYSCON0->SEC_CLK_CTRL_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
231 break;
232 case CLKCTL0_ONE_SRC_CLKSLICE_ENABLE:
233 CLKCTL0->ONE_SRC_CLKSLICE_ENABLE &= ~(1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
234 break;
235 case CLKCTL3_ONE_SRC_CLKSLICE_ENABLE:
236 CLKCTL3->ONE_SRC_CLKSLICE_ENABLE_COMP &= ~(1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
237 break;
238 case CLKCTL4_ONE_SRC_CLKSLICE_ENABLE:
239 CLKCTL4->ONE_SRC_CLKSLICE_ENABLE &= ~(1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
240 break;
241 #else
242 case CLK_CTL1_PSCCTL0:
243 CLKCTL1->PSCCTL0_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
244 break;
245 case CLK_CTL1_PSCCTL1:
246 CLKCTL1->PSCCTL1_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
247 break;
248 case CLK_CTL3_PSCCTL0:
249 CLKCTL3->PSCCTL0_SENS_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
250 break;
251 case CLK_CTL4_PSCCTL0:
252 CLKCTL4->PSCCTL0_SENS_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
253 break;
254 case CLK_CTL4_PSCCTL1:
255 CLKCTL4->PSCCTL1_SENS_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
256 break;
257 case CLKCTL3_ONE_SRC_CLKSLICE_ENABLE:
258 CLKCTL3->ONE_SRC_CLKSLICE_ENABLE_SENSE &= ~(1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
259 break;
260 case CLKCTL4_ONE_SRC_CLKSLICE_ENABLE:
261 CLKCTL4->ONE_SRC_CLKSLICE_ENABLE_SENSE &= ~(1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
262 break;
263 #endif
264 case CLK_CTL2_PSCCTL0:
265 CLKCTL2->PSCCTL0_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
266 break;
267 case SYSCON3_SEC_CLK_CTRL:
268 SYSCON3->SEC_CLK_CTRL_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
269 break;
270 default:
271 /* Should not go here. */
272 assert(false);
273 break;
274 }
275 }
276
277 /* Clock Selection for IP */
278 /**
279 * brief Configure the clock selection muxes.
280 * param connection : Clock to be configured.
281 * return Nothing
282 */
CLOCK_AttachClk(clock_attach_id_t connection)283 void CLOCK_AttachClk(clock_attach_id_t connection)
284 {
285 volatile uint32_t *pClkSel;
286
287 switch (((uint32_t)connection) & 0xE0000000U)
288 {
289 case CLKCTL4_INDEX:
290 pClkSel = CLKCTL_TUPLE_REG(CLKCTL4, connection);
291 break;
292 case CLKCTL3_INDEX:
293 pClkSel = CLKCTL_TUPLE_REG(CLKCTL3, connection);
294 break;
295 case CLKCTL2_INDEX:
296 pClkSel = CLKCTL_TUPLE_REG(CLKCTL2, connection);
297 break;
298 #if defined(FSL_CLOCK_DRIVER_SENSE)
299 case CLKCTL1_INDEX:
300 pClkSel = CLKCTL_TUPLE_REG(CLKCTL1, connection);
301 break;
302 #else
303 case CLKCTL0_INDEX:
304 pClkSel = CLKCTL_TUPLE_REG(CLKCTL0, connection);
305 break;
306 #endif
307 default:
308 pClkSel = NULL;
309 break;
310 }
311
312 if (pClkSel != NULL)
313 {
314 if (((uint32_t)connection & CLK_MUX_DISABLE_OUTPUT_MASK) != 0U) /* For muxes with SEL_EN bit*/
315 {
316 *pClkSel = (*pClkSel & 0xFFFFFF8UL) | CLKCTL_TUPLE_SEL(connection);
317 }
318 else
319 {
320 *pClkSel = (*pClkSel & 0xFFFFFFCUL) | CLKCTL_TUPLE_SEL(connection) | 0x4U;
321 }
322 }
323 else
324 {
325 /* Unreachable */
326 assert(false);
327 }
328 }
329
330 /* Set IP Clock divider */
331 /**
332 * brief Setup peripheral clock dividers.
333 * param div_name : Clock divider name
334 * param divider : Value to be divided. Divided clock frequency = Undivided clock frequency / divider.
335 * return Nothing
336 */
CLOCK_SetClkDiv(clock_div_name_t div_name,uint32_t divider)337 void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divider)
338 {
339 volatile uint32_t *pClkDiv = NULL;
340
341 switch (((uint32_t)div_name) & 0xE0000000U)
342 {
343 case CLKCTL4_INDEX:
344 pClkDiv = CLKCTL_TUPLE_REG(CLKCTL4, div_name);
345 break;
346 case CLKCTL3_INDEX:
347 pClkDiv = CLKCTL_TUPLE_REG(CLKCTL3, div_name);
348 break;
349 case CLKCTL2_INDEX:
350 pClkDiv = CLKCTL_TUPLE_REG(CLKCTL2, div_name);
351 break;
352 #if defined(FSL_CLOCK_DRIVER_SENSE)
353 case CLKCTL1_INDEX:
354 pClkDiv = CLKCTL_TUPLE_REG(CLKCTL1, div_name);
355 break;
356 #else
357 case CLKCTL0_INDEX:
358 pClkDiv = CLKCTL_TUPLE_REG(CLKCTL0, div_name);
359 break;
360 #endif
361 default:
362 /* Should not go here. */
363 assert(false);
364 break;
365 }
366
367 /* Reset the divider counter */
368 #if defined(FSL_CLOCK_DRIVER_SENSE)
369 if (div_name != kCLOCK_DivSenseMainClk)
370 #endif
371 #if defined(FSL_CLOCK_DRIVER_COMPUTE)
372 if ((div_name != kCLOCK_DivCmptMainClk) && (div_name != kCLOCK_DivSenseMainClk))
373 #endif
374 {
375 *pClkDiv |= 1UL << 29U;
376 }
377
378 if (divider == 0U) /*!< halt */
379 {
380 *pClkDiv |= 1UL << 30U;
381 }
382 else
383 {
384 *pClkDiv = divider - 1U;
385
386 while (((*pClkDiv) & 0x80000000U) != 0U)
387 {
388 }
389 }
390 }
391
CLOCK_GetFreq(clock_name_t clockName)392 uint32_t CLOCK_GetFreq(clock_name_t clockName)
393 {
394 uint32_t freq = 0U;
395
396 switch (clockName)
397 {
398 case kCLOCK_CoreSysClk:
399 #if defined(FSL_CLOCK_DRIVER_COMPUTE)
400 case kCLOCK_BusClk:
401 freq = CLOCK_GetComputeMainClkFreq();
402 break;
403 case kCLOCK_Vdd2ClockOutClk:
404 freq = CLOCK_GetClockOutClkFreq();
405 break;
406 case kCLOCK_Wdt0Clk:
407 freq = CLOCK_GetWdtClkFreq(0U);
408 break;
409 case kCLOCK_Wdt1Clk:
410 freq = CLOCK_GetWdtClkFreq(1U);
411 break;
412 case kCLOCK_Xspi0Clk:
413 freq = CLOCK_GetXspiClkFreq(0U);
414 break;
415 case kCLOCK_Xspi1Clk:
416 freq = CLOCK_GetXspiClkFreq(1U);
417 break;
418 case kCLOCK_SctClk:
419 freq = CLOCK_GetSctClkFreq();
420 break;
421 case kCLOCK_Hifi4CpuClk:
422 freq = CLOCK_GetHifi4ClkFreq();
423 break;
424 case kCLOCK_LPFlexComm0Clk:
425 freq = CLOCK_GetLPFlexCommClkFreq(0U);
426 break;
427 case kCLOCK_LPFlexComm1Clk:
428 freq = CLOCK_GetLPFlexCommClkFreq(1U);
429 break;
430 case kCLOCK_LPFlexComm2Clk:
431 freq = CLOCK_GetLPFlexCommClkFreq(2U);
432 break;
433 case kCLOCK_LPFlexComm3Clk:
434 freq = CLOCK_GetLPFlexCommClkFreq(3U);
435 break;
436 case kCLOCK_LPFlexComm4Clk:
437 freq = CLOCK_GetLPFlexCommClkFreq(4U);
438 break;
439 case kCLOCK_LPFlexComm5Clk:
440 freq = CLOCK_GetLPFlexCommClkFreq(5U);
441 break;
442 case kCLOCK_LPFlexComm6Clk:
443 freq = CLOCK_GetLPFlexCommClkFreq(6U);
444 break;
445 case kCLOCK_LPFlexComm7Clk:
446 freq = CLOCK_GetLPFlexCommClkFreq(7U);
447 break;
448 case kCLOCK_LPFlexComm8Clk:
449 freq = CLOCK_GetLPFlexCommClkFreq(8U);
450 break;
451 case kCLOCK_LPFlexComm9Clk:
452 freq = CLOCK_GetLPFlexCommClkFreq(9U);
453 break;
454 case kCLOCK_LPFlexComm10Clk:
455 freq = CLOCK_GetLPFlexCommClkFreq(10U);
456 break;
457 case kCLOCK_LPFlexComm11Clk:
458 freq = CLOCK_GetLPFlexCommClkFreq(11U);
459 break;
460 case kCLOCK_LPFlexComm12Clk:
461 freq = CLOCK_GetLPFlexCommClkFreq(12U);
462 break;
463 case kCLOCK_LPFlexComm13Clk:
464 freq = CLOCK_GetLPFlexCommClkFreq(13U);
465 break;
466 #else
467 case kCLOCK_BusClk:
468 freq = CLOCK_GetSenseMainClkFreq();
469 break;
470 case kCLOCK_Wdt2Clk:
471 freq = CLOCK_GetWdtClkFreq(2U);
472 break;
473 case kCLOCK_Wdt3Clk:
474 freq = CLOCK_GetWdtClkFreq(3U);
475 break;
476 case kCLOCK_Hifi1CpuClk:
477 freq = CLOCK_GetHifi1ClkFreq();
478 break;
479 case kCLOCK_LPFlexComm17Clk:
480 freq = CLOCK_GetLPFlexCommClkFreq(17U);
481 break;
482 case kCLOCK_LPFlexComm18Clk:
483 freq = CLOCK_GetLPFlexCommClkFreq(18U);
484 break;
485 case kCLOCK_LPFlexComm19Clk:
486 freq = CLOCK_GetLPFlexCommClkFreq(19U);
487 break;
488 case kCLOCK_LPFlexComm20Clk:
489 freq = CLOCK_GetLPFlexCommClkFreq(20U);
490 break;
491 #endif
492
493 case kCLOCK_MclkClk:
494 freq = CLOCK_GetMclkInClkFreq();
495 break;
496 case kCLOCK_Vdd1ClockOutClk:
497 freq = CLOCK_GetVdd1ClockOutClkFreq();
498 break;
499 case kCLOCK_AdcClk:
500 freq = CLOCK_GetAdcClkFreq();
501 break;
502 case kCLOCK_Xspi2Clk:
503 freq = CLOCK_GetXspiClkFreq(2U);
504 break;
505 case kCLOCK_SystickClk:
506 freq = CLOCK_GetSystickClkFreq();
507 break;
508 case kCLOCK_Sdio0Clk:
509 freq = CLOCK_GetUsdhcClkFreq(0U);
510 break;
511 case kCLOCK_Sdio1Clk:
512 freq = CLOCK_GetUsdhcClkFreq(1U);
513 break;
514 case kCLOCK_I3cClk:
515 freq = CLOCK_GetI3cClkFreq();
516 break;
517 case kCLOCK_Usb0Clk:
518 freq = CLOCK_GetMediaVddnClkFreq();
519 break;
520 case kCLOCK_Usb1Clk:
521 freq = CLOCK_GetUsbClkFreq();
522 break;
523 case kCLOCK_PdmClk:
524 freq = CLOCK_GetMicfilClkFreq();
525 break;
526 case kCLOCK_AcmpClk:
527 freq = CLOCK_GetAcmpClkFreq();
528 break;
529 case kCLOCK_LPSpi14Clk:
530 freq = CLOCK_GetLPSpiClkFreq(14U);
531 break;
532 case kCLOCK_LPSpi16Clk:
533 freq = CLOCK_GetLPSpiClkFreq(16U);
534 break;
535 case kCLOCK_LPI2c15Clk:
536 freq = CLOCK_GetLPI2cClkFreq(15U);
537 break;
538 case kCLOCK_FlexioClk:
539 freq = CLOCK_GetFlexioClkFreq();
540 break;
541 case kCLOCK_VgpuClk:
542 freq = CLOCK_GetVgpuClkFreq();
543 break;
544 case kCLOCK_LcdifClk:
545 freq = CLOCK_GetLcdifClkFreq();
546 break;
547 case kCLOCK_MipiDphyClk:
548 freq = CLOCK_GetMipiDphyClkFreq();
549 break;
550 case kCLOCK_MipiDphyEscRxClk:
551 freq = CLOCK_GetMipiDphyEscRxClkFreq();
552 break;
553 case kCLOCK_MipiDphyEscTxClk:
554 freq = CLOCK_GetMipiDphyEscTxClkFreq();
555 break;
556 default:
557 freq = 0U;
558 break;
559 }
560
561 return freq;
562 }
563
564 #if defined(FSL_CLOCK_DRIVER_COMPUTE)
565 /*!
566 * brief Get the FRO instance from peripheral base address.
567 *
568 * param base FRO peripheral base address.
569 * return FRO instance.
570 */
CLOCK_FroGetInstance(FRO_Type * base)571 static uint32_t CLOCK_FroGetInstance(FRO_Type *base)
572 {
573 uint32_t instance;
574
575 /* Find the instance index from base address mappings. */
576 for (instance = 0U; instance < ARRAY_SIZE(s_froBases); instance++)
577 {
578 if (s_froBases[instance] == base)
579 {
580 break;
581 }
582 }
583
584 assert(instance < ARRAY_SIZE(s_froBases));
585
586 return instance;
587 }
588 #endif
589
CLOCK_CalFroFreq(FRO_Type * base)590 static uint32_t CLOCK_CalFroFreq(FRO_Type *base)
591 {
592 uint32_t freq = 0U;
593 bool enabled = false;
594 uint32_t refFreq = 0U;
595
596 #if defined(FSL_CLOCK_DRIVER_COMPUTE)
597 assert(base != FRO1);
598 enabled = ((SLEEPCON0->RUNCFG & ((uint32_t)SLEEPCON0_RUNCFG_FRO0_PD_MASK << CLOCK_FroGetInstance(base))) != 0U) ?
599 false :
600 true;
601 #else
602 enabled = ((SLEEPCON1->RUNCFG & SLEEPCON1_RUNCFG_FRO2_PD_MASK) != 0U) ? false : true;
603 #endif
604 refFreq = (g_xtalFreq != 0U) ? g_xtalFreq : g_clkinFreq;
605
606 if ((base->CSR.RW & FRO_CSR_FROEN_MASK) != 0U || enabled)
607 {
608 if (base == FRO2)
609 {
610 if ((base->TEXPCNT.RW & FRO_TEXPCNT_TEXPCNT_MASK) != 0u)
611 {
612 freq = ((uint32_t)((uint64_t)(base->TRIMCNT.RW) *
613 ((uint64_t)refFreq / (uint64_t)((base->CNFG1.RW & FRO_CNFG1_REFDIV_MASK) + 1UL)) /
614 (uint64_t)((base->CNFG1.RW & FRO_CNFG1_RFCLKCNT_MASK) >> FRO_CNFG1_RFCLKCNT_SHIFT)));
615 }
616 else
617 {
618 freq = FRO2_DEFAULT_CLOCK_FREQ;
619 }
620 }
621 #if defined(FSL_CLOCK_DRIVER_COMPUTE)
622 else
623 {
624 if ((base->TEXPCNT.RW & FRO_TEXPCNT_TEXPCNT_MASK) != 0u)
625 {
626 freq = ((uint32_t)((uint64_t)(base->TRIMCNT.RW) *
627 ((uint64_t)refFreq / (uint64_t)((base->CNFG1.RW & FRO_CNFG1_REFDIV_MASK) + 1UL)) /
628 (uint64_t)((base->CNFG1.RW & FRO_CNFG1_RFCLKCNT_MASK) >> FRO_CNFG1_RFCLKCNT_SHIFT)));
629 }
630 else
631 {
632 freq = FRO0_DEFAULT_CLOCK_FREQ;
633 }
634 }
635 #endif
636 }
637 else
638 {
639 freq = 0U; /* FRO is disabled. */
640 }
641
642 return freq;
643 }
644
CLOCK_GetFroClkFreq(uint32_t id)645 uint32_t CLOCK_GetFroClkFreq(uint32_t id)
646 {
647 uint32_t freq = 0U;
648
649 switch (id)
650 {
651 #if defined(FSL_CLOCK_DRIVER_COMPUTE)
652 case 0U:
653 freq = CLOCK_CalFroFreq(FRO0);
654 break;
655 #endif
656 case 1U:
657 freq = FRO1_MAX_CLOCK_FREQ;
658 break;
659 case 2U:
660 freq = CLOCK_CalFroFreq(FRO2);
661 break;
662 default:
663 /* Added comments to prevent the violation of MISRA C-2012 rule. */
664 break;
665 }
666
667 return freq;
668 }
669
CLOCK_GetFroFlags(FRO_Type * base)670 uint32_t CLOCK_GetFroFlags(FRO_Type *base)
671 {
672 uint32_t flags = 0U;
673
674 flags = base->CSR.RW & (FRO_CSR_TUNE_ERR_MASK | FRO_CSR_LOL_ERR_MASK | FRO_CSR_TRUPREQ_MASK |
675 FRO_CSR_TUNEONCE_DONE_MASK | FRO_CSR_TRIM_LOCK_MASK);
676 return flags;
677 }
678
CLOCK_EnableFroClkOutput(FRO_Type * base,uint32_t divOutEnable)679 void CLOCK_EnableFroClkOutput(FRO_Type *base, uint32_t divOutEnable)
680 {
681 if (divOutEnable != 0U)
682 {
683 /* Wait clock ready. */
684 if (base == FRO2)
685 {
686 while ((CLKCTL3->FRO2CLKSTATUS & CLKCTL3_FRO2CLKSTATUS_CLK_OK_MASK) == 0U)
687 {
688 }
689 }
690 #if defined(FSL_CLOCK_DRIVER_COMPUTE)
691 else if (base == FRO0)
692 {
693 while ((CLKCTL0->FRO01CLKSTATUS & CLKCTL0_FRO01CLKSTATUS_FRO0_CLK_OK_MASK) == 0U)
694 {
695 }
696 }
697 else
698 {
699 while ((CLKCTL0->FRO01CLKSTATUS & CLKCTL0_FRO01CLKSTATUS_FRO1_CLK_OK_MASK) == 0U)
700 {
701 }
702 }
703 #else
704 else
705 {
706 /* Intentional empty. */
707 }
708 #endif /* FSL_CLOCK_DRIVER_COMPUTE */
709 }
710 else
711 {
712 /* Intentional empty. */
713 }
714
715 base->CSR.CLR = ((base->CSR.RW & FRO_CSR_CLKGATE_MASK) ^ divOutEnable) & FRO_CSR_CLKGATE_MASK;
716 base->CSR.SET = divOutEnable;
717 }
718
CLOCK_EnableFroAutoTuning(FRO_Type * base,const clock_fro_config_t * config,bool enable)719 status_t CLOCK_EnableFroAutoTuning(FRO_Type *base, const clock_fro_config_t *config, bool enable)
720 {
721 uint32_t refFreq = 0U;
722 uint32_t tempCnt = 0U;
723 uint32_t trim1Delay = 0U;
724 uint32_t trim2Delay = 0U;
725 uint32_t freqkHZ = 0U;
726 status_t ret = kStatus_Success;
727
728 if (enable)
729 {
730 /* Check parameter. FRO1 192MHz, FRO0,2 150MHz ~ 300MHz*/
731 if ((config->targetFreq < FRO_MIN_CLOCK_FREQ) || (config->targetFreq > FRO_MAX_CLOCK_FREQ) ||
732 (config->refDiv == 0U))
733 {
734 ret = kStatus_InvalidArgument;
735 }
736 #if defined(FSL_CLOCK_DRIVER_COMPUTE)
737 else if ((base == FRO1) && (config->targetFreq != FRO1_MAX_CLOCK_FREQ))
738 {
739 ret = kStatus_InvalidArgument;
740 }
741 #endif
742 else
743 {
744 /* Do nothing. */
745 }
746
747 if (ret == kStatus_Success)
748 {
749 /* Both FRO_PD in SLEEPCON and FROEN can power up FRO, clear FROEN for only using FRO_PD to control it's
750 * power. */
751 base->CSR.CLR = FRO_CSR_FROEN_MASK | FRO_CSR_TREN_MASK | FRO_CSR_TRUPEN_MASK;
752
753 refFreq = CLOCK_GetXtalInClkFreq() / (config->refDiv);
754 freqkHZ = config->targetFreq / 1000U;
755
756 tempCnt = (10U * refFreq + freqkHZ - 1U) /
757 freqkHZ; /* REFCLKCNT = 10000 * divided reference clock / FRO target frequency. */
758 base->CNFG1.RW =
759 config->enableInt | FRO_CNFG1_RFCLKCNT(tempCnt) | FRO_CNFG1_REFDIV((uint32_t)config->refDiv - 1UL);
760
761 /* TEXPCNT */
762 tempCnt = (uint32_t)((uint64_t)config->targetFreq * tempCnt / refFreq);
763 base->TEXPCNT.RW = FRO_TEXPCNT_TEXPCNT(tempCnt) | FRO_TEXPCNT_TEXPCNT_RANGE(config->range);
764
765 trim1Delay = refFreq / 1000000UL * (uint32_t)config->trim1DelayUs;
766 trim2Delay = refFreq / 1000000UL * (uint32_t)config->trim2DelayUs;
767 base->CNFG2.RW = FRO_CNFG2_TRIM1_DELAY(trim1Delay == 0U ? 1U : trim1Delay) |
768 FRO_CNFG2_TRIM2_DELAY(trim2Delay == 0U ? 1U : trim2Delay);
769
770 if (config->coarseTrimEn)
771 {
772 base->CSR.SET = FRO_CSR_COARSEN_MASK;
773 }
774 else
775 {
776 base->CSR.CLR = FRO_CSR_COARSEN_MASK;
777 }
778 /* Enable FRO close loop mode. */
779 base->CSR.SET = FRO_CSR_TREN_MASK | FRO_CSR_TRUPEN_MASK;
780 }
781 else
782 {
783 /* Do nothing. */
784 }
785
786 return ret;
787 }
788 else
789 {
790 base->CSR.CLR = FRO_CSR_TREN_MASK | FRO_CSR_TRUPEN_MASK;
791 ret = kStatus_Success;
792 }
793
794 return ret;
795 }
796
CLOCK_EnableFroClkFreq(FRO_Type * base,uint32_t targetFreq,uint32_t divOutEnable)797 void CLOCK_EnableFroClkFreq(FRO_Type *base, uint32_t targetFreq, uint32_t divOutEnable)
798 {
799 const clock_fro_config_t froAutotrimCfg = {
800 .targetFreq = targetFreq,
801 .range = 50U, /* For about 0.5% deviation. */
802 .trim1DelayUs = 15U,
803 .trim2DelayUs = 150U,
804 .refDiv = 1U,
805 .enableInt = 0U,
806 .coarseTrimEn = true,
807 };
808 (void)CLOCK_EnableFroClkFreqCloseLoop(base, &froAutotrimCfg, divOutEnable);
809 (void)CLOCK_EnableFroAutoTuning(base, &froAutotrimCfg, false);
810 }
811
CLOCK_ConfigFroTrim(FRO_Type * base,uint16_t trimVal)812 void CLOCK_ConfigFroTrim(FRO_Type *base, uint16_t trimVal)
813 {
814 base->FROTRIM.RW = (base->FROTRIM.RW & ~(FRO_FROTRIM_COARSE_TRIM_MASK | FRO_FROTRIM_FINE_TRIM_MASK)) |
815 FRO_FROTRIM_COARSE_TRIM(((uint32_t)trimVal & 0xF80U) >> 0x7U) |
816 FRO_FROTRIM_FINE_TRIM((uint32_t)trimVal & 0x7FU);
817 }
818
CLOCK_EnableFroClkFreqCloseLoop(FRO_Type * base,const clock_fro_config_t * config,uint32_t divOutEnable)819 status_t CLOCK_EnableFroClkFreqCloseLoop(FRO_Type *base, const clock_fro_config_t *config, uint32_t divOutEnable)
820 {
821 status_t ret = kStatus_Success;
822 uint32_t flags = 0U;
823
824 /*Power up FRO */
825 #if defined(FSL_CLOCK_DRIVER_COMPUTE)
826 SLEEPCON0->RUNCFG_CLR = (uint32_t)SLEEPCON0_RUNCFG_FRO0_PD_MASK << CLOCK_FroGetInstance(base);
827 #else
828 SLEEPCON1->RUNCFG_CLR = (uint32_t)SLEEPCON1_RUNCFG_FRO2_PD_MASK;
829 #endif
830
831 /* Disable output before changeing frequency. */
832 CLOCK_EnableFroClkOutput(base, 0U);
833 ret = CLOCK_EnableFroAutoTuning(base, config, true);
834
835 if (ret == kStatus_Success)
836 {
837 /* Polling wait tune finish. */
838 do
839 {
840 flags = CLOCK_GetFroFlags(base);
841
842 } while ((flags & FRO_CSR_TRIM_LOCK_MASK) == 0U);
843
844 if ((flags & (FRO_CSR_TUNE_ERR_MASK | FRO_CSR_LOL_ERR_MASK)) != 0U)
845 {
846 ret = kStatus_Fail; /* Error occures. */
847 }
848 else
849 {
850 ret = kStatus_Success;
851 /* Configure the FROTRIM with autotrim value. */
852 CLOCK_ConfigFroTrim(base, (uint16_t)(base->AUTOTRIM.RW & FRO_AUTOTRIM_AUTOTRIM_MASK));
853 }
854 }
855
856 /* Enable output */
857 CLOCK_EnableFroClkOutput(base, divOutEnable);
858
859 return ret;
860 }
861
CLOCK_DisableFro(FRO_Type * base)862 void CLOCK_DisableFro(FRO_Type *base)
863 {
864 CLOCK_EnableFroClkOutput(base, 0);
865 base->CSR.CLR = FRO_CSR_FROEN_MASK | FRO_CSR_TREN_MASK | FRO_CSR_TRUPEN_MASK;
866
867 /*Power down FRO */
868 #if defined(FSL_CLOCK_DRIVER_COMPUTE)
869 SLEEPCON0->RUNCFG_SET = (uint32_t)SLEEPCON0_RUNCFG_FRO0_PD_MASK << CLOCK_FroGetInstance(base);
870 #else
871 SLEEPCON1->RUNCFG_SET = SLEEPCON1_RUNCFG_FRO2_PD_MASK;
872 #endif
873 }
874
875 /* Initialize the SYSTEM PLL Clk */
876 /*! brief Initialize the System PLL.
877 * param config : Configuration to set to PLL.
878 */
CLOCK_InitMainPll(const clock_main_pll_config_t * config)879 void CLOCK_InitMainPll(const clock_main_pll_config_t *config)
880 {
881 /* Power down MAINPLL before change fractional settings */
882 #if defined(FSL_CLOCK_DRIVER_COMPUTE)
883 SLEEPCON0->RUNCFG_SET = SLEEPCON0_RUNCFG_PLLLDO_PD_MASK | SLEEPCON0_RUNCFG_PLLANA_PD_MASK;
884 #else
885 SLEEPCON1->RUNCFG_SET = SLEEPCON1_RUNCFG_PLLLDO_PD_MASK | SLEEPCON1_RUNCFG_PLLANA_PD_MASK;
886 #endif
887
888 CLKCTL2->MAINPLL0CLKSEL = (uint32_t)config->main_pll_src;
889 CLKCTL2->MAINPLL0NUM = config->numerator;
890 CLKCTL2->MAINPLL0DENOM = config->denominator;
891 CLKCTL2->MAINPLL0CTL0 = (CLKCTL2->MAINPLL0CTL0 & ~CLKCTL2_MAINPLL0CTL0_MULT_MASK) |
892 CLKCTL2_MAINPLL0CTL0_MULT((uint32_t)(config->main_pll_mult));
893
894 /* Clear System PLL reset*/
895 CLKCTL2->MAINPLL0CTL0 &= ~CLKCTL2_MAINPLL0CTL0_RESET_MASK;
896 /* Power up MAINPLL*/
897 #if defined(FSL_CLOCK_DRIVER_COMPUTE)
898 SLEEPCON0->RUNCFG_CLR = SLEEPCON0_RUNCFG_PLLLDO_PD_MASK | SLEEPCON0_RUNCFG_PLLANA_PD_MASK;
899 #else
900 SLEEPCON1->RUNCFG_CLR = SLEEPCON1_RUNCFG_PLLLDO_PD_MASK | SLEEPCON1_RUNCFG_PLLANA_PD_MASK;
901 #endif
902 SDK_DelayAtLeastUs((CLKCTL2->MAINPLL0LOCKTIMEDIV2 & CLKCTL2_MAINPLL0LOCKTIMEDIV2_LOCKTIMEDIV2_MASK) / 2UL,
903 SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
904 /* Set System PLL HOLD_RING_OFF_ENA */
905 CLKCTL2->MAINPLL0CTL0 |= CLKCTL2_MAINPLL0CTL0_HOLD_RING_OFF_ENA_MASK;
906 SDK_DelayAtLeastUs((CLKCTL2->MAINPLL0LOCKTIMEDIV2 & CLKCTL2_MAINPLL0LOCKTIMEDIV2_LOCKTIMEDIV2_MASK) / 6UL,
907 SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
908 /* Clear System PLL HOLD_RING_OFF_ENA*/
909 CLKCTL2->MAINPLL0CTL0 &= ~CLKCTL2_MAINPLL0CTL0_HOLD_RING_OFF_ENA_MASK;
910 SDK_DelayAtLeastUs((CLKCTL2->MAINPLL0LOCKTIMEDIV2 & CLKCTL2_MAINPLL0LOCKTIMEDIV2_LOCKTIMEDIV2_MASK) / 3UL,
911 SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
912 }
913
914 /* Initialize the Main PLL PFD */
915 /*! brief Initialize the Main PLL PFD.
916 * param pfd : Which PFD clock to enable.
917 * param divider : The PFD divider value.
918 * note It is recommended that PFD settings are kept between 12-35.
919 */
CLOCK_InitMainPfd(clock_pfd_t pfd,uint8_t divider)920 void CLOCK_InitMainPfd(clock_pfd_t pfd, uint8_t divider)
921 {
922 uint32_t pfdIndex = (uint32_t)pfd;
923 uint32_t syspfd;
924
925 syspfd = CLKCTL2->MAINPLL0PFD &
926 ~(((uint32_t)CLKCTL2_MAINPLL0PFD_PFD0_CLKGATE_MASK | (uint32_t)CLKCTL2_MAINPLL0PFD_PFD0_MASK)
927 << (8UL * pfdIndex));
928
929 /* Disable the clock output first. */
930 CLKCTL2->MAINPLL0PFD = syspfd | ((uint32_t)CLKCTL2_MAINPLL0PFD_PFD0_CLKGATE_MASK << (8UL * pfdIndex));
931
932 /* Set the new value and enable output. */
933 CLKCTL2->MAINPLL0PFD = syspfd | (CLKCTL2_MAINPLL0PFD_PFD0(divider) << (8UL * pfdIndex));
934 /* Wait for output becomes stable. */
935 while ((CLKCTL2->MAINPLL0PFD & ((uint32_t)CLKCTL2_MAINPLL0PFD_PFD0_CLKRDY_MASK << (8UL * pfdIndex))) == 0UL)
936 {
937 }
938 /* Clear ready status flag. */
939 CLKCTL2->MAINPLL0PFD |= ((uint32_t)CLKCTL2_MAINPLL0PFD_PFD0_CLKRDY_MASK << (8UL * pfdIndex));
940 }
941 /* Initialize the Audio PLL Clk */
942 /*! brief Initialize the audio PLL.
943 * param config : Configuration to set to PLL.
944 */
CLOCK_InitAudioPll(const clock_audio_pll_config_t * config)945 void CLOCK_InitAudioPll(const clock_audio_pll_config_t *config)
946 {
947 #if defined(FSL_CLOCK_DRIVER_COMPUTE)
948 /* Power down Audio PLL before change fractional settings */
949 SLEEPCON0->RUNCFG_SET = SLEEPCON0_RUNCFG_AUDPLLLDO_PD_MASK | SLEEPCON0_RUNCFG_AUDPLLANA_PD_MASK;
950 #else
951 SLEEPCON1->RUNCFG_SET = SLEEPCON1_RUNCFG_AUDPLLLDO_PD_MASK | SLEEPCON1_RUNCFG_AUDPLLANA_PD_MASK;
952 #endif
953
954 CLKCTL2->AUDIOPLL0CLKSEL = (uint32_t)(config->audio_pll_src);
955 CLKCTL2->AUDIOPLL0NUM = config->numerator;
956 CLKCTL2->AUDIOPLL0DENOM = config->denominator;
957 CLKCTL2->AUDIOPLL0CTL0 = (CLKCTL2->AUDIOPLL0CTL0 & ~CLKCTL2_AUDIOPLL0CTL0_MULT_MASK) |
958 CLKCTL2_AUDIOPLL0CTL0_MULT((uint32_t)(config->audio_pll_mult));
959
960 /* Clear Audio PLL reset*/
961 CLKCTL2->AUDIOPLL0CTL0 &= ~CLKCTL2_AUDIOPLL0CTL0_RESET_MASK;
962 /* Power up Audio PLL*/
963 #if defined(FSL_CLOCK_DRIVER_COMPUTE)
964 /* Power down Audio PLL before change fractional settings */
965 SLEEPCON0->RUNCFG_CLR = SLEEPCON0_RUNCFG_AUDPLLLDO_PD_MASK | SLEEPCON0_RUNCFG_AUDPLLANA_PD_MASK;
966 #else
967 SLEEPCON1->RUNCFG_CLR = SLEEPCON1_RUNCFG_AUDPLLLDO_PD_MASK | SLEEPCON1_RUNCFG_AUDPLLANA_PD_MASK;
968 #endif
969 SDK_DelayAtLeastUs((CLKCTL2->AUDIOPLL0LOCKTIMEDIV2 & CLKCTL2_AUDIOPLL0LOCKTIMEDIV2_LOCKTIMEDIV2_MASK) / 2UL,
970 SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
971 /* Set Audio PLL HOLD_RING_OFF_ENA */
972 CLKCTL2->AUDIOPLL0CTL0 |= CLKCTL2_AUDIOPLL0CTL0_HOLD_RING_OFF_ENA_MASK;
973 SDK_DelayAtLeastUs((CLKCTL2->AUDIOPLL0LOCKTIMEDIV2 & CLKCTL2_AUDIOPLL0LOCKTIMEDIV2_LOCKTIMEDIV2_MASK) / 6UL,
974 SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
975 /* Clear Audio PLL HOLD_RING_OFF_ENA*/
976 CLKCTL2->AUDIOPLL0CTL0 &= ~CLKCTL2_AUDIOPLL0CTL0_HOLD_RING_OFF_ENA_MASK;
977 SDK_DelayAtLeastUs((CLKCTL2->AUDIOPLL0LOCKTIMEDIV2 & CLKCTL2_AUDIOPLL0LOCKTIMEDIV2_LOCKTIMEDIV2_MASK) / 3UL,
978 SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
979
980 /* Each time after PLL power up, software needs to wait the whole PLL lock time the to enable VCO output .*/
981 if (config->enableVcoOut)
982 {
983 CLKCTL2->AUDIOPLL0CTL0 |= CLKCTL2_AUDIOPLL0CTL0_VCO_OUT_ENABLE_MASK;
984 }
985 else
986 {
987 CLKCTL2->AUDIOPLL0CTL0 &= ~CLKCTL2_AUDIOPLL0CTL0_VCO_OUT_ENABLE_MASK;
988 }
989 }
990
991 /* Initialize the Audio PLL PFD */
992 /*! brief Initialize the audio PLL PFD.
993 * param pfd : Which PFD clock to enable.
994 * param divider : The PFD divider value.
995 * note It is recommended that PFD settings are kept between 12-35.
996 */
CLOCK_InitAudioPfd(clock_pfd_t pfd,uint8_t divider)997 void CLOCK_InitAudioPfd(clock_pfd_t pfd, uint8_t divider)
998 {
999 uint32_t pfdIndex = (uint32_t)pfd;
1000 uint32_t syspfd;
1001
1002 syspfd = CLKCTL2->AUDIOPLL0PFD &
1003 ~(((uint32_t)CLKCTL2_AUDIOPLL0PFD_PFD0_CLKGATE_MASK | (uint32_t)CLKCTL2_AUDIOPLL0PFD_PFD0_MASK)
1004 << (8UL * pfdIndex));
1005
1006 /* Disable the clock output first. */
1007 CLKCTL2->AUDIOPLL0PFD = syspfd | ((uint32_t)CLKCTL2_AUDIOPLL0PFD_PFD0_CLKGATE_MASK << (8UL * pfdIndex));
1008
1009 /* Set the new value and enable output. */
1010 CLKCTL2->AUDIOPLL0PFD = syspfd | (CLKCTL2_AUDIOPLL0PFD_PFD0(divider) << (8UL * pfdIndex));
1011 /* Wait for output becomes stable. */
1012 while ((CLKCTL2->AUDIOPLL0PFD & ((uint32_t)CLKCTL2_AUDIOPLL0PFD_PFD0_CLKRDY_MASK << (8UL * pfdIndex))) == 0UL)
1013 {
1014 }
1015 /* Clear ready status flag. */
1016 CLKCTL2->AUDIOPLL0PFD |= ((uint32_t)CLKCTL2_AUDIOPLL0PFD_PFD0_CLKRDY_MASK << (8UL * pfdIndex));
1017 }
1018
1019 /*! @brief Enable/Disable sys osc clock from external crystal clock.
1020 * @param enable : true to enable system osc clock, false to bypass system osc.
1021 * @param enableLowPower : true to enable low power mode, false to enable high gain mode.
1022 * @param delay_us : Delay time after OSC power up.
1023 */
CLOCK_EnableSysOscClk(bool enable,bool enableLowPower,uint32_t delay_us)1024 void CLOCK_EnableSysOscClk(bool enable, bool enableLowPower, uint32_t delay_us)
1025 {
1026 uint32_t ctrl = enableLowPower ? CLKCTL2_SYSOSCCTL0_LP_ENABLE_MASK : 0U;
1027
1028 if (enable)
1029 {
1030 CLKCTL2->SYSOSCCTL0 = ctrl;
1031 CLKCTL2->SYSOSCBYPASS = 0U;
1032 SDK_DelayAtLeastUs(delay_us, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
1033 }
1034 else
1035 {
1036 CLKCTL2->SYSOSCCTL0 = ctrl | CLKCTL2_SYSOSCCTL0_BYPASS_ENABLE_MASK;
1037 }
1038 }
1039
CLOCK_EnableOsc32K(clock_osc32k_config_t * config)1040 void CLOCK_EnableOsc32K(clock_osc32k_config_t *config)
1041 {
1042 uint32_t ctrl = OSC32KNP->CTRL;
1043
1044 ctrl &= ~(OSC32KNP_CTRL_CAP_TRIM_MASK | OSC32KNP_CTRL_CLKMON_EN_MASK | OSC32KNP_CTRL_BYPASS_EN_MASK);
1045 OSC32KNP->CTRL = ctrl | OSC32KNP_CTRL_CAP_TRIM((uint32_t)config->cap) |
1046 OSC32KNP_CTRL_CLKMON_EN((uint32_t)config->monitorEnable) |
1047 OSC32KNP_CTRL_BYPASS_EN((uint32_t)config->bypass);
1048
1049 if (config->lowPowerMode)
1050 {
1051 /* Disables the output of an oscillator on the channel before changing the OSC32KNP power mode of the channel.*/
1052 OSC32KNP->CTRL |= OSC32KNP_CTRL_OSC_DIS_MASK;
1053 /* Low power mode. */
1054 OSC32KNP->CTRL &= ~OSC32KNP_CTRL_MODE_MASK;
1055 /* Wait Self-Charge Oscillator stable. */
1056 while ((OSC32KNP->STAT & OSC32KNP_STAT_SCXO_STABLE_MASK) == 0U)
1057 {
1058 }
1059 OSC32KNP->CTRL &= ~OSC32KNP_CTRL_OSC_DIS_MASK;
1060 }
1061 else
1062 {
1063 if ((OSC32KNP->CTRL & OSC32KNP_CTRL_MODE_MASK) == 0U)
1064 {
1065 /* Can only change from high power mode to low power mode. */
1066 assert(false);
1067 }
1068
1069 while ((OSC32KNP->STAT & OSC32KNP_STAT_TCXO_STABLE_MASK) == 0U)
1070 {
1071 }
1072 }
1073 }
1074
CLOCK_GetOsc32KFreq(void)1075 uint32_t CLOCK_GetOsc32KFreq(void)
1076 {
1077 uint32_t freq = 0U;
1078
1079 if ((OSC32KNP->CTRL & OSC32KNP_CTRL_OSC_DIS_MASK) == 0U)
1080 {
1081 freq = ((OSC32KNP->CTRL & OSC32KNP_CTRL_BYPASS_EN_MASK) != 0UL) ? g_32kClkinFreq : CLK_RTC_32K_CLK;
1082 }
1083 else /* OSC32KNP disabled. */
1084 {
1085 freq = 0U;
1086 }
1087
1088 return freq;
1089 }
1090
CLOCK_GetVddnComBaseClkFreq(void)1091 uint32_t CLOCK_GetVddnComBaseClkFreq(void)
1092 {
1093 uint32_t freq = 0U;
1094
1095 switch (CLKCTL2->COMNBASECLKSEL & CLKCTL2_COMNBASECLKSEL_SEL_MASK)
1096 {
1097 case CLKCTL2_COMNBASECLKSEL_SEL(0U):
1098 freq = CLOCK_GetFroClkFreq(1U) / 3U;
1099 break;
1100 case CLKCTL2_COMNBASECLKSEL_SEL(1U):
1101 freq = CLOCK_GetFroClkFreq(1U);
1102 break;
1103 case CLKCTL2_COMNBASECLKSEL_SEL(2U):
1104 freq = CLOCK_GetFroClkFreq(0U) / 3U;
1105 break;
1106 case CLKCTL2_COMNBASECLKSEL_SEL(3U):
1107 freq = CLOCK_GetLpOscFreq();
1108 break;
1109 default:
1110 freq = 0U;
1111 break;
1112 }
1113
1114 return freq;
1115 }
1116
1117 #if defined(FSL_CLOCK_DRIVER_COMPUTE)
1118 /*! @brief Enable/Disable FRO clock output. */
CLOCK_EnableFro0ClkForDomain(uint32_t domainEnable)1119 void CLOCK_EnableFro0ClkForDomain(uint32_t domainEnable)
1120 {
1121 if (domainEnable != 0U)
1122 {
1123 /* Wait FRO stable first in case FRO just get powered on. */
1124 while ((CLKCTL0->FRO01CLKSTATUS & CLKCTL0_FRO01CLKSTATUS_FRO0_CLK_OK_MASK) == 0U)
1125 {
1126 }
1127 }
1128 else
1129 {
1130 /* Do nothing */
1131 }
1132 CLKCTL0->FRO0MAXDOMAINEN = domainEnable & (uint32_t)kCLOCK_AllDomainEnable;
1133 }
1134
CLOCK_GetComputeBaseClkFreq(void)1135 uint32_t CLOCK_GetComputeBaseClkFreq(void)
1136 {
1137 uint32_t freq = 0U;
1138 uint32_t clkSel = 0U;
1139 clkSel = CLKCTL0->CMPTBASECLKSEL & CLKCTL0_CMPTBASECLKSEL_SEL_MASK;
1140
1141 switch (clkSel)
1142 {
1143 case CLKCTL0_CMPTBASECLKSEL_SEL(0U):
1144 freq = CLOCK_GetFroClkFreq(1U) / 3U;
1145 break;
1146 case CLKCTL0_CMPTBASECLKSEL_SEL(1U):
1147 freq = CLOCK_GetFroClkFreq(1U);
1148 break;
1149 case CLKCTL0_CMPTBASECLKSEL_SEL(2U):
1150 freq = CLOCK_GetFroClkFreq(0U) / 3U;
1151 break;
1152 case CLKCTL0_CMPTBASECLKSEL_SEL(3U):
1153 freq = CLOCK_GetLpOscFreq();
1154 break;
1155 default:
1156 freq = 0U;
1157 break;
1158 }
1159
1160 return freq;
1161 }
1162
CLOCK_GetComputeDspBaseClkFreq(void)1163 uint32_t CLOCK_GetComputeDspBaseClkFreq(void)
1164 {
1165 uint32_t freq = 0U;
1166 uint32_t clkSel = 0U;
1167 clkSel = CLKCTL0->DSPBASECLKSEL & CLKCTL0_DSPBASECLKSEL_SEL_MASK;
1168
1169 switch (clkSel)
1170 {
1171 case CLKCTL0_CMPTBASECLKSEL_SEL(0U):
1172 freq = CLOCK_GetFroClkFreq(1U) / 3U;
1173 break;
1174 case CLKCTL0_CMPTBASECLKSEL_SEL(1U):
1175 freq = CLOCK_GetFroClkFreq(1U);
1176 break;
1177 case CLKCTL0_CMPTBASECLKSEL_SEL(2U):
1178 freq = CLOCK_GetFroClkFreq(0U) / 3U;
1179 break;
1180 case CLKCTL0_CMPTBASECLKSEL_SEL(3U):
1181 freq = CLOCK_GetLpOscFreq();
1182 break;
1183 default:
1184 freq = 0U;
1185 break;
1186 }
1187
1188 return freq;
1189 }
1190
CLOCK_GetVdd2ComBaseClkFreq(void)1191 uint32_t CLOCK_GetVdd2ComBaseClkFreq(void)
1192 {
1193 uint32_t freq = 0U;
1194
1195 switch (CLKCTL0->VDD2COMBASECLKSEL & CLKCTL0_VDD2COMBASECLKSEL_SEL_MASK)
1196 {
1197 case CLKCTL0_VDD2COMBASECLKSEL_SEL(0U):
1198 freq = CLOCK_GetFroClkFreq(1U) / 3U;
1199 break;
1200 case CLKCTL0_VDD2COMBASECLKSEL_SEL(1U):
1201 freq = CLOCK_GetFroClkFreq(1U);
1202 break;
1203 case CLKCTL0_VDD2COMBASECLKSEL_SEL(2U):
1204 freq = CLOCK_GetFroClkFreq(0U) / 3U;
1205 break;
1206 case CLKCTL0_VDD2COMBASECLKSEL_SEL(3U):
1207 freq = CLOCK_GetLpOscFreq();
1208 break;
1209 default:
1210 freq = 0U;
1211 break;
1212 }
1213
1214 return freq;
1215 }
1216
CLOCK_GetComputeAudioClkFreq(void)1217 uint32_t CLOCK_GetComputeAudioClkFreq(void)
1218 {
1219 uint32_t freq = 0U;
1220
1221 switch (CLKCTL0->AUDIOVDD2CLKSEL & CLKCTL0_AUDIOVDD2CLKSEL_SEL_MASK)
1222 {
1223 case CLKCTL0_AUDIOVDD2CLKSEL_SEL(0U):
1224 freq = CLOCK_GetMclkInClkFreq();
1225 break;
1226 case CLKCTL0_AUDIOVDD2CLKSEL_SEL(1U):
1227 freq = CLOCK_GetXtalInClkFreq();
1228 break;
1229 case CLKCTL0_AUDIOVDD2CLKSEL_SEL(2U):
1230 freq = CLOCK_GetFroClkFreq(2U) / 8U;
1231 break;
1232 case CLKCTL0_AUDIOVDD2CLKSEL_SEL(3U):
1233 freq = CLOCK_GetAudioPfdFreq(kCLOCK_Pfd3);
1234 break;
1235 default:
1236 freq = 0U;
1237 break;
1238 }
1239
1240 return freq;
1241 }
1242
CLOCK_GetSenseAudioClkFreq(void)1243 uint32_t CLOCK_GetSenseAudioClkFreq(void)
1244 {
1245 return g_senseAudioClkFreq;
1246 }
1247
1248 /* Get FCCLK Clk frequency */
CLOCK_GetFCClkFreq(uint32_t id)1249 uint32_t CLOCK_GetFCClkFreq(uint32_t id)
1250 {
1251 uint32_t freq = 0U;
1252 uint32_t clkSel = 0U;
1253 uint32_t clkDiv = 0U;
1254 bool selEn = false;
1255
1256 assert(id <= 3U);
1257
1258 clkSel = CLKCTL0->FLEXCOMM[id].FCCLKSEL & CLKCTL0_FCCLKSEL_SEL_MASK;
1259 selEn = (CLKCTL0->FLEXCOMM[id].FCCLKSEL & CLKCTL0_FCCLKSEL_SEL_EN_MASK) == CLKCTL0_FCCLKSEL_SEL_EN_MASK;
1260 clkDiv = (CLKCTL0->FLEXCOMM[id].FCCLKDIV & CLKCTL0_FCCLKDIV_DIV_MASK) >> CLKCTL0_FCCLKDIV_DIV_SHIFT;
1261
1262 if (selEn)
1263 {
1264 switch (clkSel)
1265 {
1266 case CLKCTL0_FCCLKSEL_SEL(0):
1267 freq = CLOCK_GetComputeBaseClkFreq();
1268 break;
1269
1270 case CLKCTL0_FCCLKSEL_SEL(1):
1271 freq = CLOCK_GetFroClkFreq(0U);
1272 break;
1273
1274 case CLKCTL0_FCCLKSEL_SEL(2):
1275 freq = CLOCK_GetMainPfdFreq(kCLOCK_Pfd3);
1276 break;
1277
1278 case CLKCTL0_FCCLKSEL_SEL(3):
1279 freq = CLOCK_GetSysOscFreq();
1280 break;
1281 default:
1282 freq = 0U;
1283 break;
1284 }
1285 }
1286 else
1287 {
1288 freq = 0U;
1289 }
1290
1291 return (freq / (clkDiv + 1U));
1292 }
1293
CLOCK_GetComputeMainClkFreq(void)1294 uint32_t CLOCK_GetComputeMainClkFreq(void)
1295 {
1296 uint32_t freq = 0U;
1297
1298 switch ((CLKCTL0->MAINCLKSEL) & CLKCTL0_MAINCLKSEL_SEL_MASK)
1299 {
1300 case CLKCTL0_MAINCLKSEL_SEL(0):
1301 freq = CLOCK_GetComputeBaseClkFreq();
1302 break;
1303
1304 case CLKCTL0_MAINCLKSEL_SEL(1):
1305 freq = CLOCK_GetMainPfdFreq(kCLOCK_Pfd0);
1306 break;
1307
1308 case CLKCTL0_MAINCLKSEL_SEL(2):
1309 freq = CLOCK_GetFroClkFreq(0U);
1310 break;
1311
1312 case CLKCTL0_MAINCLKSEL_SEL(3):
1313 freq = CLOCK_GetAudioPfdFreq(kCLOCK_Pfd1);
1314 break;
1315
1316 default:
1317 freq = 0U;
1318 break;
1319 }
1320
1321 return freq / ((CLKCTL0->MAINCLKDIV & CLKCTL0_MAINCLKDIV_DIV_MASK) + 1U);
1322 }
1323
CLOCK_GetHifi4ClkFreq(void)1324 uint32_t CLOCK_GetHifi4ClkFreq(void)
1325 {
1326 uint32_t freq = 0U;
1327
1328 if ((CLKCTL0->DSPCPUCLKSEL & CLKCTL0_DSPCPUCLKSEL_SEL_EN_MASK) != 0U)
1329 {
1330 switch ((CLKCTL0->DSPCPUCLKSEL) & CLKCTL0_DSPCPUCLKSEL_SEL_MASK)
1331 {
1332 case CLKCTL0_DSPCPUCLKSEL_SEL(0):
1333 freq = CLOCK_GetComputeDspBaseClkFreq();
1334 break;
1335
1336 case CLKCTL0_DSPCPUCLKSEL_SEL(1):
1337 freq = CLOCK_GetMainPfdFreq(kCLOCK_Pfd0);
1338 break;
1339
1340 case CLKCTL0_DSPCPUCLKSEL_SEL(2):
1341 freq = CLOCK_GetFroClkFreq(0U);
1342 break;
1343
1344 case CLKCTL0_DSPCPUCLKSEL_SEL(3):
1345 freq = CLOCK_GetMainPfdFreq(kCLOCK_Pfd1);
1346 break;
1347
1348 default:
1349 freq = 0U;
1350 break;
1351 }
1352 }
1353
1354 return freq / ((CLKCTL0->DSPCPUCLKDIV & CLKCTL0_DSPCPUCLKDIV_DIV_MASK) + 1U);
1355 }
1356
CLOCK_GetSenseBaseClkFreq(void)1357 uint32_t CLOCK_GetSenseBaseClkFreq(void)
1358 {
1359 uint32_t freq = 0U;
1360 uint32_t clkSel = 0U;
1361 clkSel = CLKCTL3->SENSEBASECLKSEL & CLKCTL3_SENSEBASECLKSEL_SEL_MASK;
1362
1363 /* Read again to avoid glitch. */
1364 if (clkSel == (CLKCTL3->SENSEBASECLKSEL & CLKCTL3_SENSEBASECLKSEL_SEL_MASK))
1365 {
1366 switch (clkSel)
1367 {
1368 case CLKCTL3_SENSEBASECLKSEL_SEL(0U):
1369 freq = CLOCK_GetFroClkFreq(1U) / 3U;
1370 break;
1371 case CLKCTL3_SENSEBASECLKSEL_SEL(1U):
1372 freq = CLOCK_GetFroClkFreq(1U);
1373 break;
1374 case CLKCTL3_SENSEBASECLKSEL_SEL(2U):
1375 freq = CLOCK_GetFroClkFreq(2U) / 3U;
1376 break;
1377 case CLKCTL3_SENSEBASECLKSEL_SEL(3U):
1378 freq = CLOCK_GetLpOscFreq();
1379 break;
1380 default:
1381 freq = 0U;
1382 break;
1383 }
1384 }
1385
1386 return freq;
1387 }
1388
1389 #endif /* FSL_CLOCK_DRIVER_COMPUTE */
1390
1391 #if defined(FSL_CLOCK_DRIVER_SENSE)
1392 /*! @brief Get Sense base clock frequency. */
CLOCK_GetSenseBaseClkFreq(void)1393 uint32_t CLOCK_GetSenseBaseClkFreq(void)
1394 {
1395 uint32_t freq = 0U;
1396 uint32_t clkSel = 0U;
1397 clkSel = CLKCTL1->SENSEBASECLKSEL & CLKCTL1_SENSEBASECLKSEL_SEL_MASK;
1398
1399 switch (clkSel)
1400 {
1401 case CLKCTL1_SENSEBASECLKSEL_SEL(0U):
1402 freq = CLOCK_GetFroClkFreq(1U) / 3U;
1403 break;
1404 case CLKCTL1_SENSEBASECLKSEL_SEL(1U):
1405 freq = CLOCK_GetFroClkFreq(1U);
1406 break;
1407 case CLKCTL1_SENSEBASECLKSEL_SEL(2U):
1408 freq = CLOCK_GetFroClkFreq(2U) / 3U;
1409 break;
1410 case CLKCTL1_SENSEBASECLKSEL_SEL(3U):
1411 freq = CLOCK_GetLpOscFreq();
1412 break;
1413 default:
1414 freq = 0U;
1415 break;
1416 }
1417
1418 return freq;
1419 }
1420
CLOCK_GetHifi1ClkFreq(void)1421 uint32_t CLOCK_GetHifi1ClkFreq(void)
1422 {
1423 uint32_t freq = 0U;
1424
1425 if ((CLKCTL1->SENSEDSPCPUCLKSEL & CLKCTL1_SENSEDSPCPUCLKSEL_SEL_EN_MASK) != 0U)
1426 {
1427 switch ((CLKCTL1->SENSEDSPCPUCLKSEL) & CLKCTL1_SENSEDSPCPUCLKSEL_SEL_MASK)
1428 {
1429 case CLKCTL1_SENSEDSPCPUCLKSEL_SEL(0):
1430 freq = CLOCK_GetSenseBaseClkFreq();
1431 break;
1432
1433 case CLKCTL1_SENSEDSPCPUCLKSEL_SEL(1):
1434 freq = CLOCK_GetFroClkFreq(2U);
1435 break;
1436
1437 case CLKCTL1_SENSEDSPCPUCLKSEL_SEL(2):
1438 freq = CLOCK_GetAudioPfdFreq(kCLOCK_Pfd1);
1439 break;
1440
1441 case CLKCTL1_SENSEDSPCPUCLKSEL_SEL(3):
1442 freq = CLOCK_GetFroClkFreq(1U);
1443 break;
1444
1445 default:
1446 freq = 0U;
1447 break;
1448 }
1449 }
1450
1451 return freq / ((CLKCTL1->SENSEDSPCPUCLKDIV & CLKCTL1_SENSEDSPCPUCLKDIV_DIV_MASK) + 1U);
1452 }
1453
CLOCK_GetSenseAudioClkFreq(void)1454 uint32_t CLOCK_GetSenseAudioClkFreq(void)
1455 {
1456 uint32_t freq = 0U;
1457
1458 switch (CLKCTL1->AUDIOVDD1CLKSEL & CLKCTL1_AUDIOVDD1CLKSEL_SEL_MASK)
1459 {
1460 case CLKCTL1_AUDIOVDD1CLKSEL_SEL(0U):
1461 freq = CLOCK_GetMclkInClkFreq();
1462 break;
1463 case CLKCTL1_AUDIOVDD1CLKSEL_SEL(1U):
1464 freq = CLOCK_GetXtalInClkFreq();
1465 break;
1466 case CLKCTL1_AUDIOVDD1CLKSEL_SEL(2U):
1467 freq = CLOCK_GetFroClkFreq(2U) / 8U;
1468 break;
1469 case CLKCTL1_AUDIOVDD1CLKSEL_SEL(3U):
1470 freq = CLOCK_GetAudioPfdFreq(kCLOCK_Pfd3);
1471 break;
1472 default:
1473 freq = 0U;
1474 break;
1475 }
1476
1477 return freq;
1478 }
1479
1480 #endif /* FSL_CLOCK_DRIVER_SENSE */
1481
CLOCK_GetSenseMainClkFreq(void)1482 uint32_t CLOCK_GetSenseMainClkFreq(void)
1483 {
1484 uint32_t freq = 0U;
1485
1486 switch ((CLKCTL3->MAINCLKSEL) & CLKCTL3_MAINCLKSEL_SEL_MASK)
1487 {
1488 case CLKCTL3_MAINCLKSEL_SEL(0):
1489 freq = CLOCK_GetSenseBaseClkFreq();
1490 break;
1491
1492 case CLKCTL3_MAINCLKSEL_SEL(1):
1493 freq = CLOCK_GetFroClkFreq(2U);
1494 break;
1495
1496 case CLKCTL3_MAINCLKSEL_SEL(2):
1497 freq = CLOCK_GetAudioPfdFreq(kCLOCK_Pfd3);
1498 break;
1499
1500 case CLKCTL3_MAINCLKSEL_SEL(3):
1501 freq = CLOCK_GetFroClkFreq(1U);
1502 break;
1503
1504 default:
1505 freq = 0U;
1506 break;
1507 }
1508
1509 return freq / ((CLKCTL3->SENSEMAINCLKDIV & CLKCTL3_SENSEMAINCLKDIV_DIV_MASK) + 1U);
1510 }
1511
CLOCK_GetVdd2MediaBaseClkFreq(void)1512 uint32_t CLOCK_GetVdd2MediaBaseClkFreq(void)
1513 {
1514 uint32_t freq = 0U;
1515
1516 switch ((CLKCTL4->MD2BASECLKSEL) & CLKCTL4_MD2BASECLKSEL_SEL_MASK)
1517 {
1518 case CLKCTL4_MD2BASECLKSEL_SEL(0):
1519 freq = CLOCK_GetFroClkFreq(1U) / 3U;
1520 break;
1521
1522 case CLKCTL4_MD2BASECLKSEL_SEL(1):
1523 freq = CLOCK_GetFroClkFreq(1U);
1524 break;
1525
1526 case CLKCTL4_MD2BASECLKSEL_SEL(2):
1527 freq = CLOCK_GetFroClkFreq(0U) / 3U;
1528 break;
1529
1530 case CLKCTL4_MD2BASECLKSEL_SEL(3):
1531 freq = CLOCK_GetLpOscFreq();
1532 break;
1533
1534 default:
1535 freq = 0U;
1536 break;
1537 }
1538
1539 return freq;
1540 }
1541
CLOCK_GetVddnMediaBaseClkFreq(void)1542 uint32_t CLOCK_GetVddnMediaBaseClkFreq(void)
1543 {
1544 uint32_t freq = 0U;
1545
1546 switch ((CLKCTL4->MDNBASECLKSEL) & CLKCTL4_MDNBASECLKSEL_SEL_MASK)
1547 {
1548 case CLKCTL4_MDNBASECLKSEL_SEL(0):
1549 freq = CLOCK_GetFroClkFreq(1U) / 3U;
1550 break;
1551
1552 case CLKCTL4_MDNBASECLKSEL_SEL(1):
1553 freq = CLOCK_GetFroClkFreq(1U);
1554 break;
1555
1556 case CLKCTL4_MDNBASECLKSEL_SEL(2):
1557 freq = CLOCK_GetFroClkFreq(0U) / 3U;
1558 break;
1559
1560 case CLKCTL4_MDNBASECLKSEL_SEL(3):
1561 freq = CLOCK_GetLpOscFreq();
1562 break;
1563
1564 default:
1565 freq = 0U;
1566 break;
1567 }
1568
1569 return freq;
1570 }
1571
CLOCK_GetMediaMainClkFreq(void)1572 uint32_t CLOCK_GetMediaMainClkFreq(void)
1573 {
1574 uint32_t freq = 0U;
1575
1576 switch ((CLKCTL4->MEDIAMAINCLKSEL) & CLKCTL4_MEDIAMAINCLKSEL_SEL_MASK)
1577 {
1578 case CLKCTL4_MEDIAMAINCLKSEL_SEL(0):
1579 freq = CLOCK_GetVdd2MediaBaseClkFreq();
1580 break;
1581
1582 case CLKCTL4_MEDIAMAINCLKSEL_SEL(1):
1583 freq = CLOCK_GetMainPfdFreq(kCLOCK_Pfd0);
1584 break;
1585
1586 case CLKCTL4_MEDIAMAINCLKSEL_SEL(2):
1587 freq = CLOCK_GetFroClkFreq(0U);
1588 break;
1589
1590 case CLKCTL4_MEDIAMAINCLKSEL_SEL(3):
1591 freq = CLOCK_GetMainPfdFreq(kCLOCK_Pfd2);
1592 break;
1593
1594 default:
1595 freq = 0U;
1596 break;
1597 }
1598
1599 return freq / ((CLKCTL4->MEDIAMAINCLKDIV & CLKCTL4_MEDIAMAINCLKDIV_DIV_MASK) + 1U);
1600 }
1601
CLOCK_GetMediaVddnClkFreq(void)1602 uint32_t CLOCK_GetMediaVddnClkFreq(void)
1603 {
1604 uint32_t freq = 0U;
1605
1606 switch ((CLKCTL4->MEDIAVDDNCLKSEL) & CLKCTL4_MEDIAVDDNCLKSEL_SEL_MASK)
1607 {
1608 case CLKCTL4_MEDIAVDDNCLKSEL_SEL(0):
1609 freq = CLOCK_GetVddnMediaBaseClkFreq();
1610 break;
1611
1612 case CLKCTL4_MEDIAVDDNCLKSEL_SEL(1):
1613 freq = CLOCK_GetMainPfdFreq(kCLOCK_Pfd0);
1614 break;
1615
1616 case CLKCTL4_MEDIAVDDNCLKSEL_SEL(2):
1617 freq = CLOCK_GetFroClkFreq(0U);
1618 break;
1619
1620 case CLKCTL4_MEDIAVDDNCLKSEL_SEL(3):
1621 freq = CLOCK_GetMainPfdFreq(kCLOCK_Pfd2);
1622 break;
1623
1624 default:
1625 freq = 0U;
1626 break;
1627 }
1628
1629 return freq / ((CLKCTL4->MEDIAVDDNCLKDIV & CLKCTL4_MEDIAVDDNCLKDIV_DIV_MASK) + 1U);
1630 }
1631
1632 /*! @brief Enable/Disable FRO2 clock output. */
CLOCK_EnableFro2ClkForDomain(uint32_t domainEnable)1633 void CLOCK_EnableFro2ClkForDomain(uint32_t domainEnable)
1634 {
1635 if (domainEnable != 0U)
1636 {
1637 /* Wait FRO stable first in case FRO just get powered on. */
1638 while ((CLKCTL3->FRO2CLKSTATUS & CLKCTL3_FRO2CLKSTATUS_CLK_OK_MASK) == 0U)
1639 {
1640 }
1641 }
1642 else
1643 {
1644 /* Do nothing */
1645 }
1646 CLKCTL3->FRO2MAXDOMAINEN = domainEnable & (uint32_t)kCLOCK_AllDomainEnable;
1647 }
1648
CLOCK_EnableMainPllPfdClkForDomain(clock_pfd_t pfd,uint32_t domainEnable)1649 void CLOCK_EnableMainPllPfdClkForDomain(clock_pfd_t pfd, uint32_t domainEnable)
1650 {
1651 uint32_t pfdIndex = (uint32_t)pfd;
1652 uint32_t pfdValue;
1653
1654 pfdValue = CLKCTL2->MAINPLL0PFDDOMAINEN & (~(0x7FUL << (8UL * pfdIndex)));
1655
1656 CLKCTL2->MAINPLL0PFDDOMAINEN = pfdValue | ((domainEnable & (uint32_t)kCLOCK_AllDomainEnable) << (8UL * pfdIndex));
1657 }
1658
CLOCK_EnableAudioPllPfdClkForDomain(clock_pfd_t pfd,uint32_t domainEnable)1659 void CLOCK_EnableAudioPllPfdClkForDomain(clock_pfd_t pfd, uint32_t domainEnable)
1660 {
1661 uint32_t pfdIndex = (uint32_t)pfd;
1662 uint32_t pfdValue;
1663
1664 pfdValue = CLKCTL2->AUDIOPLL0PFDDOMAINEN & (~(0x7FUL << (8UL * pfdIndex)));
1665
1666 CLKCTL2->AUDIOPLL0PFDDOMAINEN = pfdValue | ((domainEnable & (uint32_t)kCLOCK_AllDomainEnable) << (8UL * pfdIndex));
1667 }
1668
CLOCK_EnableAudioPllVcoClkForDomain(uint32_t domainEnable)1669 void CLOCK_EnableAudioPllVcoClkForDomain(uint32_t domainEnable)
1670 {
1671 CLKCTL2->AUDIOPLL0VCODOMAINEN = domainEnable & (uint32_t)kCLOCK_AllDomainEnable;
1672 }
1673
1674 /* Get LP_FLEXCOMM Clk */
1675 /*! brief Return Frequency of LP_Flexcomm functional Clock
1676 * param id : flexcomm index to get frequency.
1677 * return Frequency of Flexcomm functional Clock
1678 */
CLOCK_GetLPFlexCommClkFreq(uint32_t id)1679 uint32_t CLOCK_GetLPFlexCommClkFreq(uint32_t id)
1680 {
1681 uint32_t freq = 0U;
1682 uint32_t fcFclkSel = 0U;
1683 uint32_t clkSel = 0U;
1684
1685 #if defined(FSL_CLOCK_DRIVER_COMPUTE)
1686 assert(id <= 13U);
1687
1688 fcFclkSel = CLKCTL0->FLEXCOMM[id].FCFCLKSEL;
1689
1690 if ((fcFclkSel & CLKCTL0_FCFCLKSEL_SEL_EN_MASK) == CLKCTL0_FCFCLKSEL_SEL_EN_MASK)
1691 {
1692 clkSel = (fcFclkSel & CLKCTL0_FCFCLKSEL_SEL_MASK) >> CLKCTL0_FCFCLKSEL_SEL_SHIFT;
1693 freq = CLOCK_GetFCClkFreq(clkSel);
1694 }
1695 else
1696 {
1697 freq = 0U;
1698 }
1699 #else
1700 assert((id <= 20U) && (id >= 17U));
1701
1702 fcFclkSel = CLKCTL1->FLEXCOMM[id - 17U].FCFCLKSEL;
1703 if ((fcFclkSel & CLKCTL1_FCFCLKSEL_SEL_EN_MASK) == CLKCTL1_FCFCLKSEL_SEL_EN_MASK)
1704 {
1705 clkSel = (fcFclkSel & CLKCTL1_FCFCLKSEL_SEL_MASK) >> CLKCTL1_FCFCLKSEL_SEL_SHIFT;
1706 switch (clkSel)
1707 {
1708 case 0U:
1709 freq = CLOCK_GetSenseBaseClkFreq() /
1710 ((CLKCTL1->FLEXCOMM[id - 17U].FCFCLKDIV & CLKCTL1_FCFCLKDIV_DIV_MASK) + 1U);
1711 break;
1712 case 1U:
1713 freq = CLOCK_GetFroClkFreq(2U) /
1714 ((CLKCTL1->FLEXCOMM[id - 17U].FCFCLKDIV & CLKCTL1_FCFCLKDIV_DIV_MASK) + 1U);
1715 break;
1716 case 2U:
1717 freq = CLOCK_GetFroClkFreq(1U) /
1718 ((CLKCTL1->FLEXCOMM[id - 17U].FCFCLKDIV & CLKCTL1_FCFCLKDIV_DIV_MASK) + 1U);
1719 break;
1720 case 3U:
1721 freq = CLOCK_GetWakeClk32KFreq() /
1722 ((CLKCTL1->FLEXCOMM[id - 17U].FCFCLKDIV & CLKCTL1_FCFCLKDIV_DIV_MASK) + 1U);
1723 break;
1724 default:
1725 freq = 0U;
1726 break;
1727 }
1728 }
1729 else
1730 {
1731 freq = 0U;
1732 }
1733 #endif /* FSL_CLOCK_DRIVER_COMPUTE */
1734 return freq;
1735 }
1736
CLOCK_GetMainPllFreq(void)1737 uint32_t CLOCK_GetMainPllFreq(void)
1738 {
1739 uint32_t freq = 0U;
1740 uint64_t freqTmp;
1741
1742 switch ((CLKCTL2->MAINPLL0CLKSEL) & CLKCTL2_MAINPLL0CLKSEL_SEL_MASK)
1743 {
1744 case CLKCTL2_MAINPLL0CLKSEL_SEL(0):
1745 freq = CLOCK_GetFroClkFreq(1U) / 8U;
1746 break;
1747 case CLKCTL2_MAINPLL0CLKSEL_SEL(1):
1748 freq = CLOCK_GetXtalInClkFreq();
1749 break;
1750 default:
1751 /* Added comments to prevent the violation of MISRA C-2012 rule. */
1752 break;
1753 }
1754
1755 if (((CLKCTL2->MAINPLL0CTL0) & CLKCTL2_MAINPLL0CTL0_BYPASS_MASK) == 0U)
1756 {
1757 /* PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM). */
1758 freqTmp = ((uint64_t)freq * ((uint64_t)(CLKCTL2->MAINPLL0NUM))) / ((uint64_t)(CLKCTL2->MAINPLL0DENOM));
1759 freq *= ((CLKCTL2->MAINPLL0CTL0) & CLKCTL2_MAINPLL0CTL0_MULT_MASK) >> CLKCTL2_MAINPLL0CTL0_MULT_SHIFT;
1760 freq += (uint32_t)freqTmp;
1761 }
1762 return freq;
1763 }
1764
CLOCK_GetMainPfdFreq(clock_pfd_t pfd)1765 uint32_t CLOCK_GetMainPfdFreq(clock_pfd_t pfd)
1766 {
1767 uint32_t freq = CLOCK_GetMainPllFreq();
1768
1769 if (((CLKCTL2->MAINPLL0CTL0) & CLKCTL2_MAINPLL0CTL0_BYPASS_MASK) == 0U)
1770 {
1771 switch (pfd)
1772 {
1773 case kCLOCK_Pfd0:
1774 freq = (uint32_t)((uint64_t)freq * 18ULL /
1775 ((CLKCTL2->MAINPLL0PFD & CLKCTL2_MAINPLL0PFD_PFD0_MASK) >>
1776 CLKCTL2_MAINPLL0PFD_PFD0_SHIFT));
1777 break;
1778
1779 case kCLOCK_Pfd1:
1780 freq = (uint32_t)((uint64_t)freq * 18ULL /
1781 ((CLKCTL2->MAINPLL0PFD & CLKCTL2_MAINPLL0PFD_PFD1_MASK) >>
1782 CLKCTL2_MAINPLL0PFD_PFD1_SHIFT));
1783 break;
1784
1785 case kCLOCK_Pfd2:
1786 freq = (uint32_t)((uint64_t)freq * 18ULL /
1787 ((CLKCTL2->MAINPLL0PFD & CLKCTL2_MAINPLL0PFD_PFD2_MASK) >>
1788 CLKCTL2_MAINPLL0PFD_PFD2_SHIFT));
1789 break;
1790
1791 case kCLOCK_Pfd3:
1792 freq = (uint32_t)((uint64_t)freq * 18ULL /
1793 ((CLKCTL2->MAINPLL0PFD & CLKCTL2_MAINPLL0PFD_PFD3_MASK) >>
1794 CLKCTL2_MAINPLL0PFD_PFD3_SHIFT));
1795 break;
1796
1797 default:
1798 freq = 0U;
1799 break;
1800 }
1801 }
1802
1803 return freq;
1804 }
1805
CLOCK_GetAudioPllFreq(void)1806 uint32_t CLOCK_GetAudioPllFreq(void)
1807 {
1808 uint32_t freq = 0U;
1809 uint64_t freqTmp;
1810
1811 switch ((CLKCTL2->AUDIOPLL0CLKSEL) & CLKCTL2_AUDIOPLL0CLKSEL_SEL_MASK)
1812 {
1813 case CLKCTL2_AUDIOPLL0CLKSEL_SEL(0):
1814 freq = CLOCK_GetFroClkFreq(1U) / 8U;
1815 break;
1816 case CLKCTL2_AUDIOPLL0CLKSEL_SEL(1):
1817 freq = CLOCK_GetXtalInClkFreq();
1818 break;
1819 default:
1820 freq = 0U;
1821 break;
1822 }
1823
1824 if (((CLKCTL2->AUDIOPLL0CTL0) & CLKCTL2_AUDIOPLL0CTL0_BYPASS_MASK) == 0UL)
1825 {
1826 /* PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM). */
1827 freqTmp = ((uint64_t)freq * ((uint64_t)(CLKCTL2->AUDIOPLL0NUM))) / ((uint64_t)(CLKCTL2->AUDIOPLL0DENOM));
1828 freq *= ((CLKCTL2->AUDIOPLL0CTL0) & CLKCTL2_AUDIOPLL0CTL0_MULT_MASK) >> CLKCTL2_AUDIOPLL0CTL0_MULT_SHIFT;
1829 freq += (uint32_t)freqTmp;
1830 }
1831 return freq;
1832 }
1833
CLOCK_GetAudioPfdFreq(clock_pfd_t pfd)1834 uint32_t CLOCK_GetAudioPfdFreq(clock_pfd_t pfd)
1835 {
1836 uint32_t freq = CLOCK_GetAudioPllFreq();
1837
1838 if (((CLKCTL2->AUDIOPLL0CTL0) & CLKCTL2_AUDIOPLL0CTL0_BYPASS_MASK) == 0UL)
1839 {
1840 switch (pfd)
1841 {
1842 case kCLOCK_Pfd0:
1843 freq = (uint32_t)((uint64_t)freq * 18ULL /
1844 ((CLKCTL2->AUDIOPLL0PFD & CLKCTL2_AUDIOPLL0PFD_PFD0_MASK) >>
1845 CLKCTL2_AUDIOPLL0PFD_PFD0_SHIFT));
1846 break;
1847
1848 case kCLOCK_Pfd1:
1849 freq = (uint32_t)((uint64_t)freq * 18ULL /
1850 ((CLKCTL2->AUDIOPLL0PFD & CLKCTL2_AUDIOPLL0PFD_PFD1_MASK) >>
1851 CLKCTL2_AUDIOPLL0PFD_PFD1_SHIFT));
1852 break;
1853
1854 case kCLOCK_Pfd2:
1855 freq = (uint32_t)((uint64_t)freq * 18ULL /
1856 ((CLKCTL2->AUDIOPLL0PFD & CLKCTL2_AUDIOPLL0PFD_PFD2_MASK) >>
1857 CLKCTL2_AUDIOPLL0PFD_PFD2_SHIFT));
1858 break;
1859
1860 case kCLOCK_Pfd3:
1861 freq = (uint32_t)((uint64_t)freq * 18ULL /
1862 ((CLKCTL2->AUDIOPLL0PFD & CLKCTL2_AUDIOPLL0PFD_PFD3_MASK) >>
1863 CLKCTL2_AUDIOPLL0PFD_PFD3_SHIFT));
1864 break;
1865
1866 default:
1867 freq = 0U;
1868 break;
1869 }
1870 }
1871
1872 return freq;
1873 }
1874
CLOCK_GetWakeClk32KFreq(void)1875 uint32_t CLOCK_GetWakeClk32KFreq(void)
1876 {
1877 uint32_t freq = 0U;
1878 switch (CLKCTL3->WAKE32KCLKSEL & CLKCTL3_WAKE32KCLKSEL_SEL_MASK)
1879 {
1880 case CLKCTL3_WAKE32KCLKSEL_SEL(0):
1881 freq = CLOCK_GetOsc32KFreq();
1882 break;
1883 case CLKCTL3_WAKE32KCLKSEL_SEL(1):
1884 freq = CLOCK_GetLpOscFreq();
1885 break;
1886 default:
1887 freq = 0U;
1888 break;
1889 }
1890 return freq / ((CLKCTL3->WAKE32KCLKDIV & CLKCTL3_WAKE32KCLKDIV_DIV_MASK) + 1U);
1891 }
1892
CLOCK_GetXspiClkFreq(uint32_t id)1893 uint32_t CLOCK_GetXspiClkFreq(uint32_t id)
1894 {
1895 uint32_t freq = 0U;
1896
1897 #if defined(FSL_CLOCK_DRIVER_COMPUTE)
1898 if (id == 0U)
1899 {
1900 if ((CLKCTL0->XSPI0FCLKSEL & CLKCTL0_XSPI0FCLKSEL_SEL_EN_MASK) != 0U)
1901 {
1902 switch (CLKCTL0->XSPI0FCLKSEL & CLKCTL0_XSPI0FCLKSEL_SEL_MASK)
1903 {
1904 case CLKCTL0_XSPI0FCLKSEL_SEL(0):
1905 freq = CLOCK_GetVddnComBaseClkFreq();
1906 break;
1907 case CLKCTL0_XSPI0FCLKSEL_SEL(1):
1908 freq = CLOCK_GetAudioPfdFreq(kCLOCK_Pfd0);
1909 break;
1910 case CLKCTL0_XSPI0FCLKSEL_SEL(2):
1911 freq = CLOCK_GetFroClkFreq(0U);
1912 break;
1913 case CLKCTL0_XSPI0FCLKSEL_SEL(3):
1914 freq = CLOCK_GetMainPfdFreq(kCLOCK_Pfd1);
1915 break;
1916 default:
1917 /* Added comments to prevent the violation of MISRA C-2012 rule. */
1918 break;
1919 }
1920 freq = freq / ((CLKCTL0->XSPI0FCLKDIV & CLKCTL0_XSPI0FCLKDIV_DIV_MASK) + 1U);
1921 }
1922 else
1923 {
1924 freq = 0U;
1925 }
1926 }
1927 else if (id == 1U)
1928 {
1929 if ((CLKCTL0->XSPI1FCLKSEL & CLKCTL0_XSPI1FCLKSEL_SEL_EN_MASK) != 0U)
1930 {
1931 switch (CLKCTL0->XSPI1FCLKSEL & CLKCTL0_XSPI1FCLKSEL_SEL_MASK)
1932 {
1933 case CLKCTL0_XSPI1FCLKSEL_SEL(0):
1934 freq = CLOCK_GetVddnComBaseClkFreq();
1935 break;
1936 case CLKCTL0_XSPI1FCLKSEL_SEL(1):
1937 freq = CLOCK_GetAudioPfdFreq(kCLOCK_Pfd1);
1938 break;
1939 case CLKCTL0_XSPI1FCLKSEL_SEL(2):
1940 freq = CLOCK_GetFroClkFreq(0U);
1941 break;
1942 case CLKCTL0_XSPI1FCLKSEL_SEL(3):
1943 freq = CLOCK_GetMainPfdFreq(kCLOCK_Pfd2);
1944 break;
1945 default:
1946 /* Added comments to prevent the violation of MISRA C-2012 rule. */
1947 break;
1948 }
1949 freq = freq / ((CLKCTL0->XSPI1FCLKDIV & CLKCTL0_XSPI1FCLKDIV_DIV_MASK) + 1U);
1950 }
1951 else
1952 {
1953 freq = 0U;
1954 }
1955 }
1956 else if (id == 2U)
1957 #else
1958 if (id == 2U)
1959 #endif /* FSL_CLOCK_DRIVER_COMPUTE */
1960 {
1961 if ((CLKCTL4->XSPI2FCLKSEL & CLKCTL4_XSPI2FCLKSEL_SEL_EN_MASK) != 0U)
1962 {
1963 switch (CLKCTL4->XSPI2FCLKSEL & CLKCTL4_XSPI2FCLKSEL_SEL_MASK)
1964 {
1965 case CLKCTL4_XSPI2FCLKSEL_SEL(0):
1966 freq = CLOCK_GetVddnComBaseClkFreq();
1967 break;
1968 case CLKCTL4_XSPI2FCLKSEL_SEL(1):
1969 freq = CLOCK_GetAudioPfdFreq(kCLOCK_Pfd1);
1970 break;
1971 case CLKCTL4_XSPI2FCLKSEL_SEL(2):
1972 freq = CLOCK_GetFroClkFreq(0U);
1973 break;
1974 case CLKCTL4_XSPI2FCLKSEL_SEL(3):
1975 freq = CLOCK_GetMainPfdFreq(kCLOCK_Pfd3);
1976 break;
1977 default:
1978 freq = 0U;
1979 break;
1980 }
1981 freq = freq / ((CLKCTL4->XSPI2FCLKDIV & CLKCTL4_XSPI2FCLKDIV_DIV_MASK) + 1U);
1982 }
1983 else
1984 {
1985 freq = 0U;
1986 }
1987 }
1988 else
1989 {
1990 freq = 0U;
1991 }
1992
1993 return freq;
1994 }
1995
1996 #if defined(FSL_CLOCK_DRIVER_COMPUTE)
CLOCK_GetSctClkFreq(void)1997 uint32_t CLOCK_GetSctClkFreq(void)
1998 {
1999 uint32_t freq = 0U;
2000 if ((CLKCTL0->SCTFCLKSEL & CLKCTL0_SCTFCLKSEL_SEL_EN_MASK) != 0U)
2001 {
2002 switch (CLKCTL0->SCTFCLKSEL & CLKCTL0_SCTFCLKSEL_SEL_MASK)
2003 {
2004 case CLKCTL0_SCTFCLKSEL_SEL(0):
2005 freq = CLOCK_GetComputeBaseClkFreq();
2006 break;
2007 case CLKCTL0_SCTFCLKSEL_SEL(1):
2008 freq = CLOCK_GetMainPfdFreq(kCLOCK_Pfd0);
2009 break;
2010 case CLKCTL0_SCTFCLKSEL_SEL(2):
2011 freq = CLOCK_GetFroClkFreq(0U);
2012 break;
2013 case CLKCTL0_SCTFCLKSEL_SEL(3):
2014 freq = CLOCK_GetFroClkFreq(0U) / 6U;
2015 break;
2016 default:
2017 freq = 0U;
2018 break;
2019 }
2020 }
2021 return freq / ((CLKCTL0->SCTFCLKDIV & CLKCTL0_SCTFCLKDIV_DIV_MASK) + 1U);
2022 }
2023
CLOCK_GetUtickClkFreq(void)2024 uint32_t CLOCK_GetUtickClkFreq(void)
2025 {
2026 uint32_t freq = 0U;
2027
2028 if ((CLKCTL0->UTICK0FCLKSEL & CLKCTL0_UTICK0FCLKSEL_SEL_EN_MASK) != 0U)
2029 {
2030 switch (CLKCTL0->UTICK0FCLKSEL & CLKCTL0_UTICK0FCLKSEL_SEL_MASK)
2031 {
2032 case CLKCTL0_UTICK0FCLKSEL_SEL(0):
2033 freq = CLOCK_GetComputeBaseClkFreq();
2034 break;
2035 case CLKCTL0_UTICK0FCLKSEL_SEL(1):
2036 freq = CLOCK_GetMainPfdFreq(kCLOCK_Pfd0);
2037 break;
2038 case CLKCTL0_UTICK0FCLKSEL_SEL(2):
2039 freq = CLOCK_GetFroClkFreq(0U);
2040 break;
2041 case CLKCTL0_UTICK0FCLKSEL_SEL(3):
2042 freq = CLOCK_GetFroClkFreq(1U) / 2U;
2043 break;
2044 default:
2045 freq = 0U;
2046 break;
2047 }
2048 }
2049 return freq / ((CLKCTL0->UTICK0FCLKDIV & CLKCTL0_UTICK0FCLKDIV_DIV_MASK) + 1U);
2050 }
2051
CLOCK_GetWdtClkFreq(uint32_t id)2052 uint32_t CLOCK_GetWdtClkFreq(uint32_t id)
2053 {
2054 uint32_t freq = 0U;
2055
2056 if (id == 0U)
2057 {
2058 if ((CLKCTL0->WWDT0FCLKSEL & CLKCTL0_WWDT0FCLKSEL_SEL_EN_MASK) != 0U)
2059 {
2060 switch (CLKCTL0->WWDT0FCLKSEL & CLKCTL0_WWDT0FCLKSEL_SEL_MASK)
2061 {
2062 case CLKCTL0_WWDT0FCLKSEL_SEL(0):
2063 freq = CLOCK_GetLpOscFreq();
2064 break;
2065 default:
2066 freq = 0U;
2067 break;
2068 }
2069 }
2070 }
2071 else if (id == 1U)
2072 {
2073 if ((CLKCTL0->WWDT1FCLKSEL & CLKCTL0_WWDT1FCLKSEL_SEL_EN_MASK) != 0U)
2074 {
2075 switch (CLKCTL0->WWDT1FCLKSEL & CLKCTL0_WWDT1FCLKSEL_SEL_MASK)
2076 {
2077 case CLKCTL0_WWDT1FCLKSEL_SEL(0):
2078 freq = CLOCK_GetLpOscFreq();
2079 break;
2080 default:
2081 freq = 0U;
2082 break;
2083 }
2084 }
2085 }
2086 else
2087 {
2088 freq = 0U;
2089 }
2090
2091 return freq;
2092 }
2093
CLOCK_GetSystickClkFreq(void)2094 uint32_t CLOCK_GetSystickClkFreq(void)
2095 {
2096 uint32_t freq = 0U;
2097
2098 if ((CLKCTL0->SYSTICKFCLKSEL & CLKCTL0_SYSTICKFCLKSEL_SEL_EN_MASK) != 0U)
2099 {
2100 switch (CLKCTL0->SYSTICKFCLKSEL & CLKCTL0_SYSTICKFCLKSEL_SEL_MASK)
2101 {
2102 case CLKCTL0_SYSTICKFCLKSEL_SEL(0):
2103 freq = CLOCK_GetComputeBaseClkFreq();
2104 break;
2105 case CLKCTL0_SYSTICKFCLKSEL_SEL(1):
2106 freq = CLOCK_GetLpOscFreq();
2107 break;
2108 case CLKCTL0_SYSTICKFCLKSEL_SEL(2):
2109 freq = CLOCK_GetWakeClk32KFreq();
2110 break;
2111 case CLKCTL0_SYSTICKFCLKSEL_SEL(3):
2112 freq = CLOCK_GetXtalInClkFreq();
2113 break;
2114 default:
2115 freq = 0U;
2116 break;
2117 }
2118 }
2119 return freq / ((CLKCTL0->SYSTICKFCLKDIV & CLKCTL0_SYSTICKFCLKDIV_DIV_MASK) + 1U);
2120 }
2121
CLOCK_GetCTimerClkFreq(uint32_t id)2122 uint32_t CLOCK_GetCTimerClkFreq(uint32_t id)
2123 {
2124 uint32_t freq = 0U;
2125
2126 if ((CLKCTL0->CTIMERFCLKSEL[id] & CLKCTL0_CTIMERFCLKSEL_SEL_EN_MASK) != 0U)
2127 {
2128 switch ((CLKCTL0->CTIMERFCLKSEL[id]) & CLKCTL0_CTIMERFCLKSEL_SEL_MASK)
2129 {
2130 case CLKCTL0_CTIMERFCLKSEL_SEL(0):
2131 freq = CLOCK_GetComputeBaseClkFreq();
2132 break;
2133
2134 case CLKCTL0_CTIMERFCLKSEL_SEL(1):
2135 freq = CLOCK_GetComputeAudioClkFreq();
2136 break;
2137
2138 case CLKCTL0_CTIMERFCLKSEL_SEL(2):
2139 freq = CLOCK_GetFroClkFreq(0U);
2140 break;
2141
2142 case CLKCTL0_CTIMERFCLKSEL_SEL(3):
2143 freq = CLOCK_GetWakeClk32KFreq();
2144 break;
2145
2146 default:
2147 freq = 0U;
2148 break;
2149 }
2150 }
2151
2152 return freq / ((CLKCTL0->CTIMERCLKDIV[id] & CLKCTL0_CTIMERCLKDIV_DIV_MASK) + 1U);
2153 }
2154
CLOCK_GetI3cClkFreq(void)2155 uint32_t CLOCK_GetI3cClkFreq(void)
2156 {
2157 uint32_t freq = 0U;
2158
2159 if ((CLKCTL0->I3C01FCLKSEL & CLKCTL0_I3C01FCLKSEL_SEL_EN_MASK) != 0U)
2160 {
2161 switch ((CLKCTL0->I3C01FCLKSEL) & CLKCTL0_I3C01FCLKSEL_SEL_MASK)
2162 {
2163 case CLKCTL0_I3C01FCLKSEL_SEL(0):
2164 freq = CLOCK_GetComputeBaseClkFreq();
2165 break;
2166
2167 case CLKCTL0_I3C01FCLKSEL_SEL(1):
2168 freq = CLOCK_GetFroClkFreq(0U);
2169 break;
2170
2171 case CLKCTL0_I3C01FCLKSEL_SEL(2):
2172 freq = CLOCK_GetFroClkFreq(1U) / 8U;
2173 break;
2174
2175 case CLKCTL0_I3C01FCLKSEL_SEL(3):
2176 freq = CLOCK_GetSysOscFreq();
2177 break;
2178
2179 default:
2180 freq = 0U;
2181 break;
2182 }
2183 }
2184
2185 return freq / ((CLKCTL0->I3C01FCLKDIV & CLKCTL0_I3C01FCLKDIV_DIV_MASK) + 1U);
2186 }
2187
CLOCK_GetTrngClkFreq(void)2188 uint32_t CLOCK_GetTrngClkFreq(void)
2189 {
2190 uint32_t freq = 0U;
2191
2192 if ((CLKCTL0->TRNGFCLKSEL & CLKCTL0_TRNGFCLKSEL_SEL_EN_MASK) != 0U)
2193 {
2194 switch ((CLKCTL0->TRNGFCLKSEL) & CLKCTL0_TRNGFCLKSEL_SEL_MASK)
2195 {
2196 case CLKCTL0_TRNGFCLKSEL_SEL(0):
2197 freq = CLOCK_GetComputeBaseClkFreq();
2198 break;
2199
2200 case CLKCTL0_TRNGFCLKSEL_SEL(1):
2201 freq = CLOCK_GetFroClkFreq(1U) / 2U;
2202 break;
2203
2204 case CLKCTL0_TRNGFCLKSEL_SEL(2):
2205 freq = CLOCK_GetFroClkFreq(1U) / 8U;
2206 break;
2207
2208 case CLKCTL0_TRNGFCLKSEL_SEL(3):
2209 freq = CLOCK_GetFroClkFreq(1U) / 3U;
2210 break;
2211
2212 default:
2213 freq = 0U;
2214 break;
2215 }
2216 }
2217
2218 return freq / ((CLKCTL0->TRNGFCLKDIV & CLKCTL0_TRNGFCLKDIV_DIV_MASK) + 1U);
2219 }
2220
CLOCK_GetTpiuClkFreq(void)2221 uint32_t CLOCK_GetTpiuClkFreq(void)
2222 {
2223 uint32_t freq = 0U;
2224
2225 if ((CLKCTL0->TPIUFCLKSEL & CLKCTL0_TPIUFCLKSEL_SEL_EN_MASK) != 0U)
2226 {
2227 switch ((CLKCTL0->TPIUFCLKSEL) & CLKCTL0_TPIUFCLKSEL_SEL_MASK)
2228 {
2229 case CLKCTL0_TPIUFCLKSEL_SEL(0):
2230 freq = CLOCK_GetComputeBaseClkFreq();
2231 break;
2232
2233 case CLKCTL0_TPIUFCLKSEL_SEL(1):
2234 freq = CLOCK_GetMainPfdFreq(kCLOCK_Pfd0);
2235 break;
2236
2237 case CLKCTL0_TPIUFCLKSEL_SEL(2):
2238 freq = CLOCK_GetFroClkFreq(0U);
2239 break;
2240
2241 case CLKCTL0_TPIUFCLKSEL_SEL(3):
2242 freq = CLOCK_GetFroClkFreq(0U) / 6U;
2243 break;
2244
2245 default:
2246 freq = 0U;
2247 break;
2248 }
2249 }
2250
2251 return freq / ((CLKCTL0->TPIUCLKDIV & CLKCTL0_TPIUCLKDIV_DIV_MASK) + 1U);
2252 }
2253
CLOCK_GetSaiClkFreq(void)2254 uint32_t CLOCK_GetSaiClkFreq(void)
2255 {
2256 uint32_t freq = 0U;
2257
2258 if ((CLKCTL0->SAI012FCLKSEL & CLKCTL0_SAI012FCLKSEL_SEL_EN_MASK) != 0U)
2259 {
2260 switch ((CLKCTL0->SAI012FCLKSEL) & CLKCTL0_SAI012FCLKSEL_SEL_MASK)
2261 {
2262 case CLKCTL0_SAI012FCLKSEL_SEL(0):
2263 freq = CLOCK_GetComputeBaseClkFreq();
2264 break;
2265
2266 case CLKCTL0_SAI012FCLKSEL_SEL(1):
2267 freq = CLOCK_GetFroClkFreq(2U) / 8U;
2268 break;
2269
2270 case CLKCTL0_SAI012FCLKSEL_SEL(2):
2271 freq = CLOCK_GetFroClkFreq(0U);
2272 break;
2273
2274 case CLKCTL0_SAI012FCLKSEL_SEL(3):
2275 freq = CLOCK_GetComputeAudioClkFreq();
2276 break;
2277
2278 default:
2279 freq = 0U;
2280 break;
2281 }
2282 }
2283
2284 return freq / ((CLKCTL0->SAI012CLKDIV & CLKCTL0_SAI012CLKDIV_DIV_MASK) + 1U);
2285 }
2286
CLOCK_GetClockOutClkFreq(void)2287 uint32_t CLOCK_GetClockOutClkFreq(void)
2288 {
2289 uint32_t freq = 0U;
2290
2291 if ((CLKCTL0->CLKOUTCLKSEL & CLKCTL0_CLKOUTCLKSEL_SEL_EN_MASK) != 0U)
2292 {
2293 switch ((CLKCTL0->CLKOUTCLKSEL) & CLKCTL0_CLKOUTCLKSEL_SEL_MASK)
2294 {
2295 case CLKCTL0_CLKOUTCLKSEL_SEL(0):
2296 freq = CLOCK_GetVdd2ComBaseClkFreq();
2297 break;
2298
2299 case CLKCTL0_CLKOUTCLKSEL_SEL(1):
2300 freq = CLOCK_GetMainPfdFreq(kCLOCK_Pfd0);
2301 break;
2302
2303 case CLKCTL0_CLKOUTCLKSEL_SEL(2):
2304 freq = CLOCK_GetFroClkFreq(0U);
2305 break;
2306
2307 case CLKCTL0_CLKOUTCLKSEL_SEL(3):
2308 freq = CLOCK_GetFroClkFreq(1U);
2309 break;
2310
2311 default:
2312 freq = 0U;
2313 break;
2314 }
2315 }
2316
2317 return freq / ((CLKCTL0->CLKOUTCLKDIV & CLKCTL0_CLKOUTCLKDIV_DIV_MASK) + 1U);
2318 }
2319 #else /* Sense domain. */
CLOCK_GetUtickClkFreq(void)2320 uint32_t CLOCK_GetUtickClkFreq(void)
2321 {
2322 uint32_t freq = 0U;
2323
2324 if ((CLKCTL1->UTICK1FCLKSEL & CLKCTL1_UTICK1FCLKSEL_SEL_EN_MASK) != 0U)
2325 {
2326 switch (CLKCTL1->UTICK1FCLKSEL & CLKCTL1_UTICK1FCLKSEL_SEL_MASK)
2327 {
2328 case CLKCTL1_UTICK1FCLKSEL_SEL(0):
2329 freq = CLOCK_GetSenseBaseClkFreq();
2330 break;
2331 case CLKCTL1_UTICK1FCLKSEL_SEL(1):
2332 freq = CLOCK_GetLpOscFreq();
2333 break;
2334 case CLKCTL1_UTICK1FCLKSEL_SEL(2):
2335 freq = CLOCK_GetFroClkFreq(0U);
2336 break;
2337 case CLKCTL1_UTICK1FCLKSEL_SEL(3):
2338 freq = CLOCK_GetFroClkFreq(1U) / 2U;
2339 break;
2340 default:
2341 freq = 0U;
2342 break;
2343 }
2344 }
2345 return freq / ((CLKCTL1->UTICK1CLKDIV & CLKCTL1_UTICK1CLKDIV_DIV_MASK) + 1U);
2346 }
2347
CLOCK_GetWdtClkFreq(uint32_t id)2348 uint32_t CLOCK_GetWdtClkFreq(uint32_t id)
2349 {
2350 uint32_t freq = 0U;
2351
2352 if (id == 2U)
2353 {
2354 if ((CLKCTL1->WWDT2FCLKSEL & CLKCTL1_WWDT2FCLKSEL_SEL_EN_MASK) != 0U)
2355 {
2356 switch (CLKCTL1->WWDT2FCLKSEL & CLKCTL1_WWDT2FCLKSEL_SEL_MASK)
2357 {
2358 case CLKCTL1_WWDT2FCLKSEL_SEL(0):
2359 freq = CLOCK_GetLpOscFreq();
2360 break;
2361 default:
2362 freq = 0U;
2363 break;
2364 }
2365 }
2366 }
2367 else if (id == 3U)
2368 {
2369 if ((CLKCTL1->WWDT3FCLKSEL & CLKCTL1_WWDT3FCLKSEL_SEL_EN_MASK) != 0U)
2370 {
2371 switch (CLKCTL1->WWDT3FCLKSEL & CLKCTL1_WWDT3FCLKSEL_SEL_MASK)
2372 {
2373 case CLKCTL1_WWDT3FCLKSEL_SEL(0):
2374 freq = CLOCK_GetLpOscFreq();
2375 break;
2376 default:
2377 freq = 0U;
2378 break;
2379 }
2380 }
2381 }
2382
2383 else
2384 {
2385 freq = 0U;
2386 }
2387
2388 return freq;
2389 }
2390
CLOCK_GetSystickClkFreq(void)2391 uint32_t CLOCK_GetSystickClkFreq(void)
2392 {
2393 uint32_t freq = 0U;
2394
2395 if ((CLKCTL1->SYSTICKFCLKSEL & CLKCTL1_SYSTICKFCLKSEL_SEL_EN_MASK) != 0U)
2396 {
2397 switch (CLKCTL1->SYSTICKFCLKSEL & CLKCTL1_SYSTICKFCLKSEL_SEL_MASK)
2398 {
2399 case CLKCTL1_SYSTICKFCLKSEL_SEL(0):
2400 freq = CLOCK_GetSenseBaseClkFreq();
2401 break;
2402 case CLKCTL1_SYSTICKFCLKSEL_SEL(1):
2403 freq = CLOCK_GetLpOscFreq();
2404 break;
2405 case CLKCTL1_SYSTICKFCLKSEL_SEL(2):
2406 freq = CLOCK_GetWakeClk32KFreq();
2407 break;
2408 case CLKCTL1_SYSTICKFCLKSEL_SEL(3):
2409 freq = CLOCK_GetXtalInClkFreq();
2410 break;
2411 default:
2412 freq = 0U;
2413 break;
2414 }
2415 }
2416 return freq / ((CLKCTL1->SYSTICKFCLKDIV & CLKCTL1_SYSTICKFCLKDIV_DIV_MASK) + 1U);
2417 }
2418
CLOCK_GetCTimerClkFreq(uint32_t id)2419 uint32_t CLOCK_GetCTimerClkFreq(uint32_t id)
2420 {
2421 uint32_t freq = 0U;
2422 assert(id >= 5U);
2423
2424 if ((CLKCTL1->CTIMERFCLKSEL[id - 5U] & CLKCTL1_CTIMERFCLKSEL_SEL_EN_MASK) != 0U)
2425 {
2426 switch ((CLKCTL1->CTIMERFCLKSEL[id - 5U]) & CLKCTL1_CTIMERFCLKSEL_SEL_MASK)
2427 {
2428 case CLKCTL1_CTIMERFCLKSEL_SEL(0):
2429 freq = CLOCK_GetSenseBaseClkFreq();
2430 break;
2431
2432 case CLKCTL1_CTIMERFCLKSEL_SEL(1):
2433 freq = CLOCK_GetSenseAudioClkFreq();
2434 break;
2435
2436 case CLKCTL1_CTIMERFCLKSEL_SEL(2):
2437 freq = CLOCK_GetFroClkFreq(2U);
2438 break;
2439
2440 case CLKCTL1_CTIMERFCLKSEL_SEL(3):
2441 freq = CLOCK_GetWakeClk32KFreq();
2442 break;
2443
2444 default:
2445 freq = 0U;
2446 break;
2447 }
2448 freq = freq / ((CLKCTL1->CTIMERCLKDIV[id - 5U] & CLKCTL1_CTIMERCLKDIV_DIV_MASK) + 1U);
2449 }
2450
2451 return freq;
2452 }
2453
CLOCK_GetI3cClkFreq(void)2454 uint32_t CLOCK_GetI3cClkFreq(void)
2455 {
2456 uint32_t freq = 0U;
2457
2458 if ((CLKCTL1->I3C23FCLKSEL & CLKCTL1_I3C23FCLKSEL_SEL_EN_MASK) != 0U)
2459 {
2460 switch ((CLKCTL1->I3C23FCLKSEL) & CLKCTL1_I3C23FCLKSEL_SEL_MASK)
2461 {
2462 case CLKCTL1_I3C23FCLKSEL_SEL(0):
2463 freq = CLOCK_GetSenseBaseClkFreq();
2464 break;
2465
2466 case CLKCTL1_I3C23FCLKSEL_SEL(1):
2467 freq = CLOCK_GetFroClkFreq(2U);
2468 break;
2469
2470 case CLKCTL1_I3C23FCLKSEL_SEL(2):
2471 freq = CLOCK_GetFroClkFreq(1U) / 8U;
2472 break;
2473
2474 case CLKCTL1_I3C23FCLKSEL_SEL(3):
2475 freq = CLOCK_GetXtalInClkFreq();
2476 break;
2477
2478 default:
2479 freq = 0U;
2480 break;
2481 }
2482 }
2483
2484 return freq / ((CLKCTL1->I3C23FCLKDIV & CLKCTL1_I3C23FCLKDIV_DIV_MASK) + 1U);
2485 }
2486
CLOCK_GetSaiClkFreq(void)2487 uint32_t CLOCK_GetSaiClkFreq(void)
2488 {
2489 uint32_t freq = 0U;
2490
2491 if ((CLKCTL1->SAI3FCLKSEL & CLKCTL1_SAI3FCLKSEL_SEL_EN_MASK) != 0U)
2492 {
2493 switch ((CLKCTL1->SAI3FCLKSEL) & CLKCTL1_SAI3FCLKSEL_SEL_MASK)
2494 {
2495 case CLKCTL1_SAI3FCLKSEL_SEL(0):
2496 freq = CLOCK_GetSenseBaseClkFreq();
2497 break;
2498
2499 case CLKCTL1_SAI3FCLKSEL_SEL(1):
2500 freq = CLOCK_GetFroClkFreq(2U) / 8U;
2501 break;
2502
2503 case CLKCTL1_SAI3FCLKSEL_SEL(2):
2504 freq = CLOCK_GetFroClkFreq(2U);
2505 break;
2506
2507 case CLKCTL1_SAI3FCLKSEL_SEL(3):
2508 freq = CLOCK_GetSenseAudioClkFreq();
2509 break;
2510
2511 default:
2512 freq = 0U;
2513 break;
2514 }
2515 }
2516
2517 return freq / ((CLKCTL1->SAI3CLKDIV & CLKCTL1_SAI3CLKDIV_DIV_MASK) + 1U);
2518 }
2519
2520 #endif /* FSL_CLOCK_DRIVER_COMPUTE */
CLOCK_GetVdd1ClockOutClkFreq(void)2521 uint32_t CLOCK_GetVdd1ClockOutClkFreq(void)
2522 {
2523 uint32_t freq = 0U;
2524
2525 if ((CLKCTL3->CLKOUTCLKSEL & CLKCTL3_CLKOUTCLKSEL_SEL_EN_MASK) != 0U)
2526 {
2527 switch ((CLKCTL3->CLKOUTCLKSEL) & CLKCTL3_CLKOUTCLKSEL_SEL_MASK)
2528 {
2529 case CLKCTL3_CLKOUTCLKSEL_SEL(0):
2530 freq = CLOCK_GetSenseBaseClkFreq();
2531 break;
2532
2533 case CLKCTL3_CLKOUTCLKSEL_SEL(1):
2534 freq = CLOCK_GetMainPfdFreq(kCLOCK_Pfd0);
2535 break;
2536
2537 case CLKCTL3_CLKOUTCLKSEL_SEL(2):
2538 freq = CLOCK_GetFroClkFreq(0U);
2539 break;
2540
2541 case CLKCTL3_CLKOUTCLKSEL_SEL(3):
2542 freq = CLOCK_GetFroClkFreq(1U);
2543 break;
2544
2545 default:
2546 freq = 0U;
2547 break;
2548 }
2549 }
2550
2551 return freq / ((CLKCTL3->CLKOUTCLKDIV & CLKCTL3_CLKOUTCLKDIV_DIV_MASK) + 1U);
2552 }
2553
CLOCK_GetAdcClkFreq(void)2554 uint32_t CLOCK_GetAdcClkFreq(void)
2555 {
2556 uint32_t freq = 0U;
2557
2558 if ((CLKCTL3->SARADCFCLKSEL & CLKCTL3_SARADCFCLKSEL_SEL_EN_MASK) != 0U)
2559 {
2560 switch ((CLKCTL3->SARADCFCLKSEL) & CLKCTL3_SARADCFCLKSEL_SEL_MASK)
2561 {
2562 case CLKCTL3_SARADCFCLKSEL_SEL(0):
2563 freq = CLOCK_GetSenseBaseClkFreq();
2564 break;
2565
2566 case CLKCTL3_SARADCFCLKSEL_SEL(1):
2567 freq = CLOCK_GetMainPfdFreq(kCLOCK_Pfd1);
2568 break;
2569
2570 case CLKCTL3_SARADCFCLKSEL_SEL(2):
2571 freq = CLOCK_GetFroClkFreq(2U);
2572 break;
2573
2574 case CLKCTL3_SARADCFCLKSEL_SEL(3):
2575 freq = CLOCK_GetXtalInClkFreq();
2576 break;
2577
2578 default:
2579 freq = 0U;
2580 break;
2581 }
2582 }
2583
2584 return freq / ((CLKCTL3->SARADCFCLKDIV & CLKCTL3_SARADCFCLKDIV_DIV_MASK) + 1U);
2585 }
2586
CLOCK_GetAcmpClkFreq(void)2587 uint32_t CLOCK_GetAcmpClkFreq(void)
2588 {
2589 return CLOCK_GetSenseMainClkFreq();
2590 }
2591
CLOCK_GetUsbClkFreq(void)2592 uint32_t CLOCK_GetUsbClkFreq(void)
2593 {
2594 return CLOCK_GetMediaVddnClkFreq();
2595 }
2596
CLOCK_GetSdAdcClkFreq(void)2597 uint32_t CLOCK_GetSdAdcClkFreq(void)
2598 {
2599 uint32_t freq = 0U;
2600
2601 if ((CLKCTL3->SDADCFCLKSEL & CLKCTL3_SDADCFCLKSEL_SEL_EN_MASK) != 0U)
2602 {
2603 switch ((CLKCTL3->SDADCFCLKSEL) & CLKCTL3_SDADCFCLKSEL_SEL_MASK)
2604 {
2605 case CLKCTL3_SDADCFCLKSEL_SEL(0):
2606 freq = CLOCK_GetSenseBaseClkFreq();
2607 break;
2608
2609 case CLKCTL3_SDADCFCLKSEL_SEL(1):
2610 freq = CLOCK_GetFroClkFreq(2) / 8U;
2611 break;
2612
2613 case CLKCTL3_SDADCFCLKSEL_SEL(2):
2614 freq = CLOCK_GetAudioPllFreq();
2615 break;
2616
2617 case CLKCTL3_SDADCFCLKSEL_SEL(3):
2618 freq = CLOCK_GetSenseAudioClkFreq();
2619 break;
2620
2621 default:
2622 freq = 0U;
2623 break;
2624 }
2625 }
2626
2627 return freq / ((CLKCTL3->SDADCFCLKDIV & CLKCTL3_SDADCFCLKDIV_DIV_MASK) + 1U);
2628 }
2629
CLOCK_GetOSTimerClkFreq(void)2630 uint32_t CLOCK_GetOSTimerClkFreq(void)
2631 {
2632 uint32_t freq = 0U;
2633
2634 if ((CLKCTL3->OSTIMERFCLKSEL & CLKCTL3_OSTIMERFCLKSEL_SEL_EN_MASK) != 0U)
2635 {
2636 switch ((CLKCTL3->OSTIMERFCLKSEL) & CLKCTL3_OSTIMERFCLKSEL_SEL_MASK)
2637 {
2638 case CLKCTL3_OSTIMERFCLKSEL_SEL(0):
2639 freq = CLOCK_GetSenseBaseClkFreq();
2640 break;
2641
2642 case CLKCTL3_OSTIMERFCLKSEL_SEL(1):
2643 freq = CLOCK_GetWakeClk32KFreq();
2644 break;
2645
2646 case CLKCTL3_OSTIMERFCLKSEL_SEL(2):
2647 freq = CLOCK_GetLpOscFreq();
2648 break;
2649
2650 case CLKCTL3_OSTIMERFCLKSEL_SEL(3):
2651 freq = CLOCK_GetXtalInClkFreq();
2652 break;
2653
2654 default:
2655 freq = 0U;
2656 break;
2657 }
2658 }
2659
2660 return freq / ((CLKCTL3->OSTIMERFCLKDIV & CLKCTL3_OSTIMERFCLKDIV_DIV_MASK) + 1U);
2661 }
2662
CLOCK_GetMicfilClkFreq(void)2663 uint32_t CLOCK_GetMicfilClkFreq(void)
2664 {
2665 uint32_t freq = 0U;
2666
2667 if ((CLKCTL3->MICFILFCLKSEL & CLKCTL3_MICFILFCLKSEL_SEL_EN_MASK) != 0U)
2668 {
2669 switch ((CLKCTL3->MICFILFCLKSEL) & CLKCTL3_MICFILFCLKSEL_SEL_MASK)
2670 {
2671 case CLKCTL3_MICFILFCLKSEL_SEL(0):
2672 freq = CLOCK_GetSenseBaseClkFreq();
2673 break;
2674
2675 case CLKCTL3_MICFILFCLKSEL_SEL(1):
2676 freq = CLOCK_GetAudioPfdFreq(kCLOCK_Pfd3);
2677 break;
2678
2679 case CLKCTL3_MICFILFCLKSEL_SEL(2):
2680 freq = CLOCK_GetFroClkFreq(2);
2681 break;
2682
2683 case CLKCTL3_MICFILFCLKSEL_SEL(3):
2684 freq = CLOCK_GetSenseAudioClkFreq();
2685 break;
2686
2687 default:
2688 freq = 0U;
2689 break;
2690 }
2691 }
2692
2693 return freq / ((CLKCTL3->MICFILFCLKDIV & CLKCTL3_MICFILFCLKDIV_DIV_MASK) + 1U);
2694 }
2695
CLOCK_GetFlexioClkFreq(void)2696 uint32_t CLOCK_GetFlexioClkFreq(void)
2697 {
2698 uint32_t freq = 0U;
2699
2700 if ((CLKCTL4->FLEXIOCLKSEL & CLKCTL4_FLEXIOCLKSEL_SEL_EN_MASK) != 0U)
2701 {
2702 switch ((CLKCTL4->FLEXIOCLKSEL) & CLKCTL4_FLEXIOCLKSEL_SEL_MASK)
2703 {
2704 case CLKCTL4_FLEXIOCLKSEL_SEL(0):
2705 freq = CLOCK_GetVdd2MediaBaseClkFreq();
2706 break;
2707
2708 case CLKCTL4_FLEXIOCLKSEL_SEL(1):
2709 freq = CLOCK_GetFroClkFreq(0);
2710 break;
2711
2712 case CLKCTL4_FLEXIOCLKSEL_SEL(2):
2713 freq = CLOCK_GetFroClkFreq(1);
2714 break;
2715
2716 case CLKCTL4_FLEXIOCLKSEL_SEL(3):
2717 freq = CLOCK_GetMainPfdFreq(kCLOCK_Pfd3);
2718 break;
2719
2720 default:
2721 freq = 0U;
2722 break;
2723 }
2724 }
2725
2726 return freq / ((CLKCTL4->FLEXIOCLKDIV & CLKCTL4_FLEXIOCLKDIV_DIV_MASK) + 1U);
2727 }
2728
CLOCK_GetLPSpiClkFreq(uint32_t id)2729 uint32_t CLOCK_GetLPSpiClkFreq(uint32_t id)
2730 {
2731 uint32_t freq = 0U;
2732
2733 if (id == 14U)
2734 {
2735 if ((CLKCTL4->LPSPI14CLKSEL & CLKCTL4_LPSPI14CLKSEL_SEL_EN_MASK) != 0U)
2736 {
2737 switch ((CLKCTL4->LPSPI14CLKSEL) & CLKCTL4_LPSPI14CLKSEL_SEL_MASK)
2738 {
2739 case CLKCTL4_LPSPI14CLKSEL_SEL(0):
2740 freq = CLOCK_GetVdd2MediaBaseClkFreq();
2741 break;
2742
2743 case CLKCTL4_LPSPI14CLKSEL_SEL(1):
2744 freq = CLOCK_GetFroClkFreq(0U);
2745 break;
2746
2747 case CLKCTL4_LPSPI14CLKSEL_SEL(2):
2748 freq = CLOCK_GetMainPfdFreq(kCLOCK_Pfd0);
2749 break;
2750
2751 case CLKCTL4_LPSPI14CLKSEL_SEL(3):
2752 freq = CLOCK_GetFroClkFreq(1U);
2753 break;
2754
2755 default:
2756 freq = 0U;
2757 break;
2758 }
2759 }
2760
2761 freq = freq / ((CLKCTL4->LPSPI14CLKDIV & CLKCTL4_LPSPI14CLKDIV_DIV_MASK) + 1U);
2762 }
2763 else if (id == 16U)
2764 {
2765 if ((CLKCTL4->LPSPI16CLKSEL & CLKCTL4_LPSPI16CLKSEL_SEL_EN_MASK) != 0U)
2766 {
2767 switch ((CLKCTL4->LPSPI16CLKSEL) & CLKCTL4_LPSPI16CLKSEL_SEL_MASK)
2768 {
2769 case CLKCTL4_LPSPI16CLKSEL_SEL(0):
2770 freq = CLOCK_GetVdd2MediaBaseClkFreq();
2771 break;
2772
2773 case CLKCTL4_LPSPI16CLKSEL_SEL(1):
2774 freq = CLOCK_GetFroClkFreq(0U);
2775 break;
2776
2777 case CLKCTL4_LPSPI16CLKSEL_SEL(2):
2778 freq = CLOCK_GetMainPfdFreq(kCLOCK_Pfd0);
2779 break;
2780
2781 case CLKCTL4_LPSPI16CLKSEL_SEL(3):
2782 freq = CLOCK_GetFroClkFreq(1U);
2783 break;
2784
2785 default:
2786 freq = 0U;
2787 break;
2788 }
2789 }
2790
2791 freq = freq / ((CLKCTL4->LPSPI16CLKDIV & CLKCTL4_LPSPI16CLKDIV_DIV_MASK) + 1U);
2792 }
2793 else
2794 {
2795 freq = CLOCK_GetLPFlexCommClkFreq(id);
2796 }
2797
2798 return freq;
2799 }
2800
CLOCK_GetLPI2cClkFreq(uint32_t id)2801 uint32_t CLOCK_GetLPI2cClkFreq(uint32_t id)
2802 {
2803 uint32_t freq = 0U;
2804
2805 if (id != 15U)
2806 {
2807 freq = CLOCK_GetLPFlexCommClkFreq(id);
2808 }
2809 else
2810 {
2811 if ((CLKCTL3->LPI2C15FCLKSEL & CLKCTL3_LPI2C15FCLKSEL_SEL_EN_MASK) != 0U)
2812 {
2813 switch ((CLKCTL3->LPI2C15FCLKSEL) & CLKCTL3_LPI2C15FCLKSEL_SEL_MASK)
2814 {
2815 case CLKCTL3_LPI2C15FCLKSEL_SEL(0):
2816 freq = CLOCK_GetSenseBaseClkFreq();
2817 break;
2818
2819 case CLKCTL3_LPI2C15FCLKSEL_SEL(1):
2820 freq = CLOCK_GetFroClkFreq(1U);
2821 break;
2822
2823 case CLKCTL3_LPI2C15FCLKSEL_SEL(2):
2824 freq = CLOCK_GetFroClkFreq(1U) / 2U;
2825 break;
2826
2827 case CLKCTL3_LPI2C15FCLKSEL_SEL(3):
2828 freq = CLOCK_GetFroClkFreq(2U);
2829 break;
2830
2831 default:
2832 freq = 0U;
2833 break;
2834 }
2835 }
2836 freq = freq / ((CLKCTL3->LPI2C15FCLKDIV & CLKCTL3_LPI2C15FCLKDIV_DIV_MASK) + 1U);
2837 }
2838
2839 return freq;
2840 }
2841
CLOCK_GetLcdifClkFreq(void)2842 uint32_t CLOCK_GetLcdifClkFreq(void)
2843 {
2844 uint32_t freq = 0U;
2845
2846 if ((CLKCTL4->LCDIFPIXELCLKSEL & CLKCTL4_LCDIFPIXELCLKSEL_SEL_EN_MASK) != 0U)
2847 {
2848 switch ((CLKCTL4->LCDIFPIXELCLKSEL) & CLKCTL4_LCDIFPIXELCLKSEL_SEL_MASK)
2849 {
2850 case CLKCTL4_LCDIFPIXELCLKSEL_SEL(0):
2851 freq = CLOCK_GetVdd2MediaBaseClkFreq();
2852 break;
2853
2854 case CLKCTL4_LCDIFPIXELCLKSEL_SEL(1):
2855 freq = CLOCK_GetMainPfdFreq(kCLOCK_Pfd2);
2856 break;
2857
2858 case CLKCTL4_LCDIFPIXELCLKSEL_SEL(2):
2859 freq = CLOCK_GetFroClkFreq(0U);
2860 break;
2861
2862 case CLKCTL4_LCDIFPIXELCLKSEL_SEL(3):
2863 freq = CLOCK_GetAudioPfdFreq(kCLOCK_Pfd1);
2864 break;
2865
2866 default:
2867 freq = 0U;
2868 break;
2869 }
2870 }
2871
2872 return freq / ((CLKCTL4->LCDIFPIXELCLKDIV & CLKCTL4_LCDIFPIXELCLKDIV_DIV_MASK) + 1U);
2873 }
2874
CLOCK_GetMipiDphyClkFreq(void)2875 uint32_t CLOCK_GetMipiDphyClkFreq(void)
2876 {
2877 uint32_t freq = 0U;
2878
2879 if ((CLKCTL4->DPHYCLKSEL & CLKCTL4_DPHYCLKSEL_SEL_EN_MASK) != 0U)
2880 {
2881 switch ((CLKCTL4->DPHYCLKSEL) & CLKCTL4_DPHYCLKSEL_SEL_MASK)
2882 {
2883 case CLKCTL4_DPHYCLKSEL_SEL(0):
2884 freq = CLOCK_GetVdd2MediaBaseClkFreq();
2885 break;
2886
2887 /*Source select 1 is internal. */
2888
2889 case CLKCTL4_DPHYCLKSEL_SEL(2):
2890 freq = CLOCK_GetFroClkFreq(0U);
2891 break;
2892
2893 case CLKCTL4_DPHYCLKSEL_SEL(3):
2894 freq = CLOCK_GetAudioPfdFreq(kCLOCK_Pfd2);
2895 break;
2896
2897 default:
2898 freq = 0U;
2899 break;
2900 }
2901 }
2902
2903 return freq / ((CLKCTL4->DPHYCLKDIV & CLKCTL4_DPHYCLKDIV_DIV_MASK) + 1U);
2904 }
2905
CLOCK_GetMipiDphyEscRxClkFreq(void)2906 uint32_t CLOCK_GetMipiDphyEscRxClkFreq(void)
2907 {
2908 uint32_t freq = 0U;
2909
2910 if ((CLKCTL4->DPHYESCCLKSEL & CLKCTL4_DPHYESCCLKSEL_SEL_EN_MASK) != 0U)
2911 {
2912 switch ((CLKCTL4->DPHYESCCLKSEL) & CLKCTL4_DPHYESCCLKSEL_SEL_MASK)
2913 {
2914 case CLKCTL4_DPHYESCCLKSEL_SEL(0):
2915 freq = CLOCK_GetVdd2MediaBaseClkFreq();
2916 break;
2917
2918 case CLKCTL4_DPHYESCCLKSEL_SEL(1):
2919 freq = CLOCK_GetMainPfdFreq(kCLOCK_Pfd1);
2920 break;
2921
2922 case CLKCTL4_DPHYESCCLKSEL_SEL(2):
2923 freq = CLOCK_GetFroClkFreq(0U);
2924 break;
2925
2926 case CLKCTL4_DPHYESCCLKSEL_SEL(3):
2927 freq = CLOCK_GetAudioPfdFreq(kCLOCK_Pfd2);
2928 break;
2929
2930 default:
2931 freq = 0U;
2932 break;
2933 }
2934 }
2935
2936 return freq / ((CLKCTL4->DPHYESCRXCLKDIV & CLKCTL4_DPHYESCRXCLKDIV_DIV_MASK) + 1U);
2937 }
2938
CLOCK_GetMipiDphyEscTxClkFreq(void)2939 uint32_t CLOCK_GetMipiDphyEscTxClkFreq(void)
2940 {
2941 return CLOCK_GetMipiDphyEscRxClkFreq() / ((CLKCTL4->DPHYESCTXCLKDIV & CLKCTL4_DPHYESCTXCLKDIV_DIV_MASK) + 1U);
2942 }
2943
CLOCK_GetUsdhcClkFreq(uint32_t id)2944 uint32_t CLOCK_GetUsdhcClkFreq(uint32_t id)
2945 {
2946 uint32_t freq = 0U;
2947
2948 if (id == 0U)
2949 {
2950 if ((CLKCTL4->SDIO0FCLKSEL & CLKCTL4_SDIO0FCLKSEL_SEL_EN_MASK) != 0U)
2951 {
2952 switch ((CLKCTL4->SDIO0FCLKSEL) & CLKCTL4_SDIO0FCLKSEL_SEL_MASK)
2953 {
2954 case CLKCTL4_SDIO0FCLKSEL_SEL(0):
2955 freq = CLOCK_GetVddnMediaBaseClkFreq();
2956 break;
2957
2958 case CLKCTL4_SDIO0FCLKSEL_SEL(1):
2959 freq = CLOCK_GetAudioPfdFreq(kCLOCK_Pfd0);
2960 break;
2961
2962 case CLKCTL4_SDIO0FCLKSEL_SEL(2):
2963 freq = CLOCK_GetFroClkFreq(0U);
2964 break;
2965
2966 case CLKCTL4_SDIO0FCLKSEL_SEL(3):
2967 freq = CLOCK_GetMainPfdFreq(kCLOCK_Pfd2);
2968 break;
2969
2970 default:
2971 freq = 0U;
2972 break;
2973 }
2974 freq = freq / ((CLKCTL4->SDIO0FCLKDIV & CLKCTL4_SDIO0FCLKDIV_DIV_MASK) + 1U);
2975 }
2976 }
2977 else if (id == 1U)
2978 {
2979 if ((CLKCTL4->SDIO1FCLKSEL & CLKCTL4_SDIO1FCLKSEL_SEL_EN_MASK) != 0U)
2980 {
2981 switch ((CLKCTL4->SDIO1FCLKSEL) & CLKCTL4_SDIO1FCLKSEL_SEL_MASK)
2982 {
2983 case CLKCTL4_SDIO1FCLKSEL_SEL(0):
2984 freq = CLOCK_GetVddnMediaBaseClkFreq();
2985 break;
2986
2987 case CLKCTL4_SDIO1FCLKSEL_SEL(1):
2988 freq = CLOCK_GetAudioPfdFreq(kCLOCK_Pfd0);
2989 break;
2990
2991 case CLKCTL4_SDIO1FCLKSEL_SEL(2):
2992 freq = CLOCK_GetFroClkFreq(0U);
2993 break;
2994
2995 case CLKCTL4_SDIO1FCLKSEL_SEL(3):
2996 freq = CLOCK_GetMainPfdFreq(kCLOCK_Pfd2);
2997 break;
2998
2999 default:
3000 freq = 0U;
3001 break;
3002 }
3003 freq = freq / ((CLKCTL4->SDIO1FCLKDIV & CLKCTL4_SDIO1FCLKDIV_DIV_MASK) + 1U);
3004 }
3005 }
3006 else
3007 {
3008 /* Nothing.*/
3009 }
3010
3011 return freq;
3012 }
3013
CLOCK_GetVgpuClkFreq(void)3014 uint32_t CLOCK_GetVgpuClkFreq(void)
3015 {
3016 uint32_t freq = 0U;
3017
3018 if ((CLKCTL4->VGPUCLKSEL & CLKCTL4_VGPUCLKSEL_SEL_EN_MASK) != 0U)
3019 {
3020 switch ((CLKCTL4->VGPUCLKSEL) & CLKCTL4_VGPUCLKSEL_SEL_MASK)
3021 {
3022 case CLKCTL4_VGPUCLKSEL_SEL(0):
3023 freq = CLOCK_GetVdd2MediaBaseClkFreq();
3024 break;
3025
3026 case CLKCTL4_VGPUCLKSEL_SEL(1):
3027 freq = CLOCK_GetMainPfdFreq(kCLOCK_Pfd0);
3028 break;
3029
3030 case CLKCTL4_VGPUCLKSEL_SEL(2):
3031 freq = CLOCK_GetFroClkFreq(0U);
3032 break;
3033
3034 case CLKCTL4_VGPUCLKSEL_SEL(3):
3035 freq = CLOCK_GetMainPfdFreq(kCLOCK_Pfd2);
3036 break;
3037
3038 default:
3039 freq = 0U;
3040 break;
3041 }
3042 freq = freq / ((CLKCTL4->VGPUCLKDIV & CLKCTL4_VGPUCLKDIV_DIV_MASK) + 1U);
3043 }
3044 return freq;
3045 }
3046
3047 /*! brief Enable USB HS clock.
3048 *
3049 * This function only enables the access to USB HS prepheral, upper layer
3050 * should first call the ref CLOCK_EnableUsbhs0PhyPllClock to enable the PHY
3051 * clock to use USB HS.
3052 *
3053 * param src USB HS does not care about the clock source, here must be ref kCLOCK_UsbSrcUnused.
3054 * param freq USB HS does not care about the clock source, so this parameter is ignored.
3055 * retval true The clock is set successfully.
3056 * retval false The clock source is invalid to get proper USB HS clock.
3057 */
CLOCK_EnableUsbhs0Clock(clock_usb_src_t src,uint32_t freq)3058 bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq)
3059 {
3060 return true;
3061 }
3062
3063 /*! brief Enable USB HS PHY PLL clock.
3064 *
3065 * This function enables the internal 480MHz USB PHY PLL clock.
3066 *
3067 * param src USB HS PHY PLL clock source.
3068 * param freq The frequency specified by src.
3069 * retval true The clock is set successfully.
3070 * retval false The clock source is invalid to get proper USB HS clock.
3071 */
CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src,uint32_t freq)3072 bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq)
3073 {
3074 uint32_t phyPllDiv = 0U;
3075 uint16_t multiplier = 0U;
3076 bool retVal = true;
3077 CLOCK_EnableClock(kCLOCK_Usb0);
3078
3079 USBPHY->CTRL_CLR = USBPHY_CTRL_SFTRST_MASK;
3080
3081 USBPHY->PLL_SIC_SET = (USBPHY_PLL_SIC_PLL_POWER(1) | USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK);
3082 if ((480000000UL % freq) != 0UL)
3083 {
3084 return false;
3085 }
3086 multiplier = (uint16_t)(480000000UL / freq);
3087
3088 switch (multiplier)
3089 {
3090 case 13:
3091 {
3092 phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(0U);
3093 break;
3094 }
3095 case 15:
3096 {
3097 phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(1U);
3098 break;
3099 }
3100 case 16:
3101 {
3102 phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(2U);
3103 break;
3104 }
3105 case 20:
3106 {
3107 phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(3U);
3108 break;
3109 }
3110 case 22:
3111 {
3112 phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(4U);
3113 break;
3114 }
3115 case 25:
3116 {
3117 phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(5U);
3118 break;
3119 }
3120 case 30:
3121 {
3122 phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(6U);
3123 break;
3124 }
3125 case 240:
3126 {
3127 phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(7U);
3128 break;
3129 }
3130 default:
3131 {
3132 retVal = false;
3133 break;
3134 }
3135 }
3136
3137 if (retVal)
3138 {
3139 USBPHY->PLL_SIC = (USBPHY->PLL_SIC & ~(USBPHY_PLL_SIC_PLL_DIV_SEL_MASK)) | phyPllDiv;
3140
3141 USBPHY->PLL_SIC_CLR = USBPHY_PLL_SIC_PLL_BYPASS_MASK;
3142 USBPHY->PLL_SIC_SET = (USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK);
3143
3144 USBPHY->CTRL_CLR = USBPHY_CTRL_CLR_CLKGATE_MASK;
3145
3146 while (0UL == (USBPHY->PLL_SIC & USBPHY_PLL_SIC_PLL_LOCK_MASK))
3147 {
3148 }
3149 }
3150
3151 return true;
3152 }
3153
3154 /*! brief Disable USB HS PHY PLL clock.
3155 *
3156 * This function disables USB HS PHY PLL clock.
3157 */
CLOCK_DisableUsbhs0PhyPllClock(void)3158 void CLOCK_DisableUsbhs0PhyPllClock(void)
3159 {
3160 USBPHY->PLL_SIC_CLR = (USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK);
3161 USBPHY->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* Set to 1U to gate clocks */
3162 }
3163
