Home
last modified time | relevance | path

Searched refs:CLK_CTL1_PSCCTL0 (Results 1 – 15 of 15) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/drivers/
Dfsl_clock.h309 #define CLK_CTL1_PSCCTL0 3 macro
349 kCLOCK_Flexcomm0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 8), /*!< Clock gate name: Flexcomm0*/
350 kCLOCK_Flexcomm1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 9), /*!< Clock gate name: Flexcomm1*/
351 kCLOCK_Flexcomm2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 10), /*!< Clock gate name: Flexcomm2*/
352 kCLOCK_Flexcomm3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 11), /*!< Clock gate name: Flexcomm3*/
353 kCLOCK_Flexcomm4 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 12), /*!< Clock gate name: Flexcomm4*/
354 kCLOCK_Flexcomm5 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 13), /*!< Clock gate name: Flexcomm5*/
355 kCLOCK_Flexcomm6 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 14), /*!< Clock gate name: Flexcomm6*/
356 kCLOCK_Flexcomm7 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 15), /*!< Clock gate name: Flexcomm7*/
357 kCLOCK_Flexcomm8 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 16), /*!< Clock gate name: Flexcomm8*/
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/drivers/
Dfsl_clock.h309 #define CLK_CTL1_PSCCTL0 3 macro
349 kCLOCK_Flexcomm0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 8), /*!< Clock gate name: Flexcomm0*/
350 kCLOCK_Flexcomm1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 9), /*!< Clock gate name: Flexcomm1*/
351 kCLOCK_Flexcomm2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 10), /*!< Clock gate name: Flexcomm2*/
352 kCLOCK_Flexcomm3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 11), /*!< Clock gate name: Flexcomm3*/
353 kCLOCK_Flexcomm4 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 12), /*!< Clock gate name: Flexcomm4*/
354 kCLOCK_Flexcomm5 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 13), /*!< Clock gate name: Flexcomm5*/
355 kCLOCK_Flexcomm6 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 14), /*!< Clock gate name: Flexcomm6*/
356 kCLOCK_Flexcomm7 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 15), /*!< Clock gate name: Flexcomm7*/
357 kCLOCK_Flexcomm8 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 16), /*!< Clock gate name: Flexcomm8*/
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/drivers/
Dfsl_clock.h309 #define CLK_CTL1_PSCCTL0 3 macro
349 kCLOCK_Flexcomm0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 8), /*!< Clock gate name: Flexcomm0*/
350 kCLOCK_Flexcomm1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 9), /*!< Clock gate name: Flexcomm1*/
351 kCLOCK_Flexcomm2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 10), /*!< Clock gate name: Flexcomm2*/
352 kCLOCK_Flexcomm3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 11), /*!< Clock gate name: Flexcomm3*/
353 kCLOCK_Flexcomm4 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 12), /*!< Clock gate name: Flexcomm4*/
354 kCLOCK_Flexcomm5 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 13), /*!< Clock gate name: Flexcomm5*/
355 kCLOCK_Flexcomm6 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 14), /*!< Clock gate name: Flexcomm6*/
356 kCLOCK_Flexcomm7 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 15), /*!< Clock gate name: Flexcomm7*/
357 kCLOCK_Flexcomm8 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 16), /*!< Clock gate name: Flexcomm8*/
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT633S/drivers/
Dfsl_clock.h261 #define CLK_CTL1_PSCCTL0 3 macro
292 kCLOCK_Flexcomm0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 8), /*!< Clock gate name: Flexcomm0*/
293 kCLOCK_Flexcomm1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 9), /*!< Clock gate name: Flexcomm1*/
294 kCLOCK_Flexcomm2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 10), /*!< Clock gate name: Flexcomm2*/
295 kCLOCK_Flexcomm3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 11), /*!< Clock gate name: Flexcomm3*/
296 kCLOCK_Flexcomm4 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 12), /*!< Clock gate name: Flexcomm4*/
297 kCLOCK_Flexcomm5 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 13), /*!< Clock gate name: Flexcomm5*/
298 kCLOCK_Flexcomm6 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 14), /*!< Clock gate name: Flexcomm6*/
299 kCLOCK_Flexcomm7 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 15), /*!< Clock gate name: Flexcomm7*/
300 kCLOCK_Flexcomm14 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 22), /*!< Clock gate name: Flexcomm14*/
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/drivers/
Dfsl_clock.h261 #define CLK_CTL1_PSCCTL0 3 macro
292 kCLOCK_Flexcomm0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 8), /*!< Clock gate name: Flexcomm0*/
293 kCLOCK_Flexcomm1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 9), /*!< Clock gate name: Flexcomm1*/
294 kCLOCK_Flexcomm2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 10), /*!< Clock gate name: Flexcomm2*/
295 kCLOCK_Flexcomm3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 11), /*!< Clock gate name: Flexcomm3*/
296 kCLOCK_Flexcomm4 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 12), /*!< Clock gate name: Flexcomm4*/
297 kCLOCK_Flexcomm5 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 13), /*!< Clock gate name: Flexcomm5*/
298 kCLOCK_Flexcomm6 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 14), /*!< Clock gate name: Flexcomm6*/
299 kCLOCK_Flexcomm7 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 15), /*!< Clock gate name: Flexcomm7*/
300 kCLOCK_Flexcomm14 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 22), /*!< Clock gate name: Flexcomm14*/
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/RW612/drivers/
Dfsl_clock.h222 #define CLK_CTL1_PSCCTL0 3 macro
310 kCLOCK_Flexcomm0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 8),
311 kCLOCK_Flexcomm1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 9),
312 kCLOCK_Flexcomm2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 10),
313 kCLOCK_Flexcomm3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 11),
314 kCLOCK_Flexcomm14 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 22),
315 kCLOCK_Dmic0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 24),
316 kCLOCK_OsEventTimer = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 27),
Dfsl_clock.c279 case CLK_CTL1_PSCCTL0: in CLOCK_EnableClock()
333 case CLK_CTL1_PSCCTL0: in CLOCK_DisableClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/RW610/drivers/
Dfsl_clock.h222 #define CLK_CTL1_PSCCTL0 3 macro
310 kCLOCK_Flexcomm0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 8),
311 kCLOCK_Flexcomm1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 9),
312 kCLOCK_Flexcomm2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 10),
313 kCLOCK_Flexcomm3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 11),
314 kCLOCK_Flexcomm14 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 22),
315 kCLOCK_Dmic0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 24),
316 kCLOCK_OsEventTimer = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 27),
Dfsl_clock.c279 case CLK_CTL1_PSCCTL0: in CLOCK_EnableClock()
333 case CLK_CTL1_PSCCTL0: in CLOCK_DisableClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/drivers/
Dfsl_clock.h451 #define CLK_CTL1_PSCCTL0 6 /* CLKCTL_VDD1_SENSE PSCCTL0 */ macro
614 …kCLOCK_Sleepcon1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 6), /*!< Clock gate name: SLEEPCONCPU1*/
615 …kCLOCK_Syscon1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 7), /*!< Clock gate name: SYSCONSENSE1*/
Dfsl_clock.c134 case CLK_CTL1_PSCCTL0: in CLOCK_EnableClock()
242 case CLK_CTL1_PSCCTL0: in CLOCK_DisableClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/drivers/
Dfsl_clock.h451 #define CLK_CTL1_PSCCTL0 6 /* CLKCTL_VDD1_SENSE PSCCTL0 */ macro
614 …kCLOCK_Sleepcon1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 6), /*!< Clock gate name: SLEEPCONCPU1*/
615 …kCLOCK_Syscon1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 7), /*!< Clock gate name: SYSCONSENSE1*/
Dfsl_clock.c134 case CLK_CTL1_PSCCTL0: in CLOCK_EnableClock()
242 case CLK_CTL1_PSCCTL0: in CLOCK_DisableClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/drivers/
Dfsl_clock.h451 #define CLK_CTL1_PSCCTL0 6 /* CLKCTL_VDD1_SENSE PSCCTL0 */ macro
614 …kCLOCK_Sleepcon1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 6), /*!< Clock gate name: SLEEPCONCPU1*/
615 …kCLOCK_Syscon1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 7), /*!< Clock gate name: SYSCONSENSE1*/
Dfsl_clock.c134 case CLK_CTL1_PSCCTL0: in CLOCK_EnableClock()
242 case CLK_CTL1_PSCCTL0: in CLOCK_DisableClock()