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Searched refs:CLK_CTL0_PSCCTL2 (Results 1 – 15 of 15) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/drivers/
Dfsl_clock.h447 #define CLK_CTL0_PSCCTL2 2 macro
527 …kCLOCK_LPFlexComm2 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 0), /*!< Clock gate name: LP_Flexcomm2*/
528 …kCLOCK_LPFlexComm3 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 1), /*!< Clock gate name: LP_Flexcomm3*/
529 …kCLOCK_LPFlexComm4 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 2), /*!< Clock gate name: LP_Flexcomm4*/
530 …kCLOCK_LPFlexComm5 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 3), /*!< Clock gate name: LP_Flexcomm5*/
531 …kCLOCK_LPFlexComm6 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 4), /*!< Clock gate name: LP_Flexcomm6*/
532 …kCLOCK_LPFlexComm7 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 5), /*!< Clock gate name: LP_Flexcomm7*/
533 …kCLOCK_LPFlexComm8 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 6), /*!< Clock gate name: LP_Flexcomm8*/
534 …kCLOCK_LPFlexComm9 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 7), /*!< Clock gate name: LP_Flexcomm9*/
535 …kCLOCK_LPFlexComm10 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 8), /*!< Clock gate name: LP_Flexcomm10…
[all …]
Dfsl_clock.c67 case CLK_CTL0_PSCCTL2: in CLOCK_EnableClock()
208 case CLK_CTL0_PSCCTL2: in CLOCK_DisableClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/drivers/
Dfsl_clock.h447 #define CLK_CTL0_PSCCTL2 2 macro
527 …kCLOCK_LPFlexComm2 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 0), /*!< Clock gate name: LP_Flexcomm2*/
528 …kCLOCK_LPFlexComm3 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 1), /*!< Clock gate name: LP_Flexcomm3*/
529 …kCLOCK_LPFlexComm4 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 2), /*!< Clock gate name: LP_Flexcomm4*/
530 …kCLOCK_LPFlexComm5 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 3), /*!< Clock gate name: LP_Flexcomm5*/
531 …kCLOCK_LPFlexComm6 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 4), /*!< Clock gate name: LP_Flexcomm6*/
532 …kCLOCK_LPFlexComm7 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 5), /*!< Clock gate name: LP_Flexcomm7*/
533 …kCLOCK_LPFlexComm8 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 6), /*!< Clock gate name: LP_Flexcomm8*/
534 …kCLOCK_LPFlexComm9 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 7), /*!< Clock gate name: LP_Flexcomm9*/
535 …kCLOCK_LPFlexComm10 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 8), /*!< Clock gate name: LP_Flexcomm10…
[all …]
Dfsl_clock.c67 case CLK_CTL0_PSCCTL2: in CLOCK_EnableClock()
208 case CLK_CTL0_PSCCTL2: in CLOCK_DisableClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/drivers/
Dfsl_clock.h447 #define CLK_CTL0_PSCCTL2 2 macro
527 …kCLOCK_LPFlexComm2 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 0), /*!< Clock gate name: LP_Flexcomm2*/
528 …kCLOCK_LPFlexComm3 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 1), /*!< Clock gate name: LP_Flexcomm3*/
529 …kCLOCK_LPFlexComm4 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 2), /*!< Clock gate name: LP_Flexcomm4*/
530 …kCLOCK_LPFlexComm5 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 3), /*!< Clock gate name: LP_Flexcomm5*/
531 …kCLOCK_LPFlexComm6 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 4), /*!< Clock gate name: LP_Flexcomm6*/
532 …kCLOCK_LPFlexComm7 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 5), /*!< Clock gate name: LP_Flexcomm7*/
533 …kCLOCK_LPFlexComm8 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 6), /*!< Clock gate name: LP_Flexcomm8*/
534 …kCLOCK_LPFlexComm9 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 7), /*!< Clock gate name: LP_Flexcomm9*/
535 …kCLOCK_LPFlexComm10 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 8), /*!< Clock gate name: LP_Flexcomm10…
[all …]
Dfsl_clock.c67 case CLK_CTL0_PSCCTL2: in CLOCK_EnableClock()
208 case CLK_CTL0_PSCCTL2: in CLOCK_DisableClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/RW612/drivers/
Dfsl_clock.h221 #define CLK_CTL0_PSCCTL2 2 macro
303 kCLOCK_Utick = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 0),
304 kCLOCK_Wwdt0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 1),
305 kCLOCK_Usim = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 2),
306 kCLOCK_Itrc = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 3),
307 kCLOCK_FreeMrt = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 26),
308 kCLOCK_Lcdic = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 27),
Dfsl_clock.c276 case CLK_CTL0_PSCCTL2: in CLOCK_EnableClock()
330 case CLK_CTL0_PSCCTL2: in CLOCK_DisableClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/RW610/drivers/
Dfsl_clock.h221 #define CLK_CTL0_PSCCTL2 2 macro
303 kCLOCK_Utick = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 0),
304 kCLOCK_Wwdt0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 1),
305 kCLOCK_Usim = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 2),
306 kCLOCK_Itrc = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 3),
307 kCLOCK_FreeMrt = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 26),
308 kCLOCK_Lcdic = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 27),
Dfsl_clock.c276 case CLK_CTL0_PSCCTL2: in CLOCK_EnableClock()
330 case CLK_CTL0_PSCCTL2: in CLOCK_DisableClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT633S/drivers/
Dfsl_clock.h260 #define CLK_CTL0_PSCCTL2 2 macro
289 kCLOCK_Utick0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 0), /*!< Clock gate name: Utick0*/
290 kCLOCK_Wwdt0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 1), /*!< Clock gate name: Wwdt0*/
897 case CLK_CTL0_PSCCTL2: in CLOCK_EnableClock()
926 case CLK_CTL0_PSCCTL2: in CLOCK_DisableClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/drivers/
Dfsl_clock.h260 #define CLK_CTL0_PSCCTL2 2 macro
289 kCLOCK_Utick0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 0), /*!< Clock gate name: Utick0*/
290 kCLOCK_Wwdt0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 1), /*!< Clock gate name: Wwdt0*/
897 case CLK_CTL0_PSCCTL2: in CLOCK_EnableClock()
926 case CLK_CTL0_PSCCTL2: in CLOCK_DisableClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/drivers/
Dfsl_clock.h308 #define CLK_CTL0_PSCCTL2 2 macro
345 kCLOCK_Utick0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 0), /*!< Clock gate name: Utick0*/
346 kCLOCK_Wwdt0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 1), /*!< Clock gate name: Wwdt0*/
347 kCLOCK_Pmc = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 29), /*!< Clock gate name: Pmc*/
1110 case CLK_CTL0_PSCCTL2: in CLOCK_EnableClock()
1139 case CLK_CTL0_PSCCTL2: in CLOCK_DisableClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/drivers/
Dfsl_clock.h308 #define CLK_CTL0_PSCCTL2 2 macro
345 kCLOCK_Utick0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 0), /*!< Clock gate name: Utick0*/
346 kCLOCK_Wwdt0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 1), /*!< Clock gate name: Wwdt0*/
347 kCLOCK_Pmc = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 29), /*!< Clock gate name: Pmc*/
1110 case CLK_CTL0_PSCCTL2: in CLOCK_EnableClock()
1139 case CLK_CTL0_PSCCTL2: in CLOCK_DisableClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/drivers/
Dfsl_clock.h308 #define CLK_CTL0_PSCCTL2 2 macro
345 kCLOCK_Utick0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 0), /*!< Clock gate name: Utick0*/
346 kCLOCK_Wwdt0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 1), /*!< Clock gate name: Wwdt0*/
347 kCLOCK_Pmc = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 29), /*!< Clock gate name: Pmc*/
1110 case CLK_CTL0_PSCCTL2: in CLOCK_EnableClock()
1139 case CLK_CTL0_PSCCTL2: in CLOCK_DisableClock()