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Searched refs:CLK_CTL0_PSCCTL0 (Results 1 – 15 of 15) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/RW612/drivers/
Dfsl_clock.h219 #define CLK_CTL0_PSCCTL0 0 macro
277 kCLOCK_Cpu = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 0),
278 kCLOCK_Matrix = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 1),
279 kCLOCK_Romcp = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 2),
280 kCLOCK_PowerQuad = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 8),
281 kCLOCK_Pkc = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 9),
282 kCLOCK_Els = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 10),
283 kCLOCK_Puf = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 11),
284 kCLOCK_Flexspi = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 16),
285 kCLOCK_Hpu = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 20),
[all …]
Dfsl_clock.c270 case CLK_CTL0_PSCCTL0: in CLOCK_EnableClock()
324 case CLK_CTL0_PSCCTL0: in CLOCK_DisableClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/RW610/drivers/
Dfsl_clock.h219 #define CLK_CTL0_PSCCTL0 0 macro
277 kCLOCK_Cpu = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 0),
278 kCLOCK_Matrix = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 1),
279 kCLOCK_Romcp = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 2),
280 kCLOCK_PowerQuad = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 8),
281 kCLOCK_Pkc = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 9),
282 kCLOCK_Els = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 10),
283 kCLOCK_Puf = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 11),
284 kCLOCK_Flexspi = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 16),
285 kCLOCK_Hpu = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 20),
[all …]
Dfsl_clock.c270 case CLK_CTL0_PSCCTL0: in CLOCK_EnableClock()
324 case CLK_CTL0_PSCCTL0: in CLOCK_DisableClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/drivers/
Dfsl_clock.h306 #define CLK_CTL0_PSCCTL0 0 macro
317 kCLOCK_Dsp = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 1), /*!< Clock gate name: Dsp*/
318 kCLOCK_RomCtrlr = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 2), /*!< Clock gate name: RomCtrlr*/
319 kCLOCK_AxiSwitch = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 3), /*!< Clock gate name: AxiSwitch*/
320 kCLOCK_AxiCtrl = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 4), /*!< Clock gate name: AxiCtrl*/
321 kCLOCK_PowerQuad = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 8), /*!< Clock gate name: PowerQuad*/
322 kCLOCK_Casper = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 9), /*!< Clock gate name: Casper*/
323 kCLOCK_HashCrypt = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 10), /*!< Clock gate name: HashCrypt*/
324 kCLOCK_Puf = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 11), /*!< Clock gate name: Puf*/
325 kCLOCK_Rng = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 12), /*!< Clock gate name: Rng*/
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/drivers/
Dfsl_clock.h306 #define CLK_CTL0_PSCCTL0 0 macro
317 kCLOCK_Dsp = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 1), /*!< Clock gate name: Dsp*/
318 kCLOCK_RomCtrlr = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 2), /*!< Clock gate name: RomCtrlr*/
319 kCLOCK_AxiSwitch = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 3), /*!< Clock gate name: AxiSwitch*/
320 kCLOCK_AxiCtrl = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 4), /*!< Clock gate name: AxiCtrl*/
321 kCLOCK_PowerQuad = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 8), /*!< Clock gate name: PowerQuad*/
322 kCLOCK_Casper = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 9), /*!< Clock gate name: Casper*/
323 kCLOCK_HashCrypt = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 10), /*!< Clock gate name: HashCrypt*/
324 kCLOCK_Puf = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 11), /*!< Clock gate name: Puf*/
325 kCLOCK_Rng = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 12), /*!< Clock gate name: Rng*/
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/drivers/
Dfsl_clock.h306 #define CLK_CTL0_PSCCTL0 0 macro
317 kCLOCK_Dsp = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 1), /*!< Clock gate name: Dsp*/
318 kCLOCK_RomCtrlr = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 2), /*!< Clock gate name: RomCtrlr*/
319 kCLOCK_AxiSwitch = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 3), /*!< Clock gate name: AxiSwitch*/
320 kCLOCK_AxiCtrl = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 4), /*!< Clock gate name: AxiCtrl*/
321 kCLOCK_PowerQuad = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 8), /*!< Clock gate name: PowerQuad*/
322 kCLOCK_Casper = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 9), /*!< Clock gate name: Casper*/
323 kCLOCK_HashCrypt = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 10), /*!< Clock gate name: HashCrypt*/
324 kCLOCK_Puf = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 11), /*!< Clock gate name: Puf*/
325 kCLOCK_Rng = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 12), /*!< Clock gate name: Rng*/
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT633S/drivers/
Dfsl_clock.h258 #define CLK_CTL0_PSCCTL0 0 macro
269 kCLOCK_RomCtrlr = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 2), /*!< Clock gate name: RomCtrlr*/
270 kCLOCK_PowerQuad = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 8), /*!< Clock gate name: PowerQuad*/
271 kCLOCK_Casper = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 9), /*!< Clock gate name: Casper*/
272 kCLOCK_HashCrypt = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 10), /*!< Clock gate name: HashCrypt*/
273 kCLOCK_Puf = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 11), /*!< Clock gate name: Puf*/
274 kCLOCK_Rng = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 12), /*!< Clock gate name: Rng*/
275 kCLOCK_Flexspi = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 16), /*!< Clock gate name: Flexspi*/
276 kCLOCK_OtpCtrl = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 17), /*!< Clock gate name: OtpCtrl*/
277 kCLOCK_UsbhsPhy = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 20), /*!< Clock gate name: UsbhsPhy*/
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/drivers/
Dfsl_clock.h258 #define CLK_CTL0_PSCCTL0 0 macro
269 kCLOCK_RomCtrlr = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 2), /*!< Clock gate name: RomCtrlr*/
270 kCLOCK_PowerQuad = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 8), /*!< Clock gate name: PowerQuad*/
271 kCLOCK_Casper = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 9), /*!< Clock gate name: Casper*/
272 kCLOCK_HashCrypt = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 10), /*!< Clock gate name: HashCrypt*/
273 kCLOCK_Puf = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 11), /*!< Clock gate name: Puf*/
274 kCLOCK_Rng = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 12), /*!< Clock gate name: Rng*/
275 kCLOCK_Flexspi = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 16), /*!< Clock gate name: Flexspi*/
276 kCLOCK_OtpCtrl = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 17), /*!< Clock gate name: OtpCtrl*/
277 kCLOCK_UsbhsPhy = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 20), /*!< Clock gate name: UsbhsPhy*/
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/drivers/
Dfsl_clock.h445 #define CLK_CTL0_PSCCTL0 0 /* CLKCTL_COM_VDD2 PSCCTL0 */ macro
484 … kCLOCK_Xcache1 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 1), /*!< Clock gate name: Code cache*/
485 …kCLOCK_Xcache0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 2), /*!< Clock gate name: System cache*/
486 kCLOCK_Ocotp0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 5), /*!< Clock gate name: VDD2 OTP0*/
487 …kCLOCK_Sleepcon0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 12), /*!< Clock gate name: SLEEPCON_CMPT…
488 … kCLOCK_Syscon0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 13), /*!< Clock gate name: SYSCON_CMPT*/
489 kCLOCK_Glikey0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 14), /*!< Clock gate name: GLIKEY0*/
490 kCLOCK_Glikey3 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 15), /*!< Clock gate name: GLIKEY3*/
Dfsl_clock.c55 case CLK_CTL0_PSCCTL0: in CLOCK_EnableClock()
202 case CLK_CTL0_PSCCTL0: in CLOCK_DisableClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/drivers/
Dfsl_clock.h445 #define CLK_CTL0_PSCCTL0 0 /* CLKCTL_COM_VDD2 PSCCTL0 */ macro
484 … kCLOCK_Xcache1 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 1), /*!< Clock gate name: Code cache*/
485 …kCLOCK_Xcache0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 2), /*!< Clock gate name: System cache*/
486 kCLOCK_Ocotp0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 5), /*!< Clock gate name: VDD2 OTP0*/
487 …kCLOCK_Sleepcon0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 12), /*!< Clock gate name: SLEEPCON_CMPT…
488 … kCLOCK_Syscon0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 13), /*!< Clock gate name: SYSCON_CMPT*/
489 kCLOCK_Glikey0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 14), /*!< Clock gate name: GLIKEY0*/
490 kCLOCK_Glikey3 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 15), /*!< Clock gate name: GLIKEY3*/
Dfsl_clock.c55 case CLK_CTL0_PSCCTL0: in CLOCK_EnableClock()
202 case CLK_CTL0_PSCCTL0: in CLOCK_DisableClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/drivers/
Dfsl_clock.h445 #define CLK_CTL0_PSCCTL0 0 /* CLKCTL_COM_VDD2 PSCCTL0 */ macro
484 … kCLOCK_Xcache1 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 1), /*!< Clock gate name: Code cache*/
485 …kCLOCK_Xcache0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 2), /*!< Clock gate name: System cache*/
486 kCLOCK_Ocotp0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 5), /*!< Clock gate name: VDD2 OTP0*/
487 …kCLOCK_Sleepcon0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 12), /*!< Clock gate name: SLEEPCON_CMPT…
488 … kCLOCK_Syscon0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 13), /*!< Clock gate name: SYSCON_CMPT*/
489 kCLOCK_Glikey0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 14), /*!< Clock gate name: GLIKEY0*/
490 kCLOCK_Glikey3 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 15), /*!< Clock gate name: GLIKEY3*/
Dfsl_clock.c55 case CLK_CTL0_PSCCTL0: in CLOCK_EnableClock()
202 case CLK_CTL0_PSCCTL0: in CLOCK_DisableClock()