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Searched refs:GCR (Results 1 – 25 of 58) sorted by relevance

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/hal_nxp-3.6.0/mcux/mcux-sdk/drivers/slcd/
Dfsl_slcd.c140 base->GCR = (base->GCR & ~gcrMsk) | gcrReg; in SLCD_Init()
163 base->GCR |= LCD_GCR_FDCIEN_MASK; in SLCD_Init()
289 uint32_t gcReg = base->GCR; in SLCD_EnableInterrupts()
296 base->GCR = gcReg; in SLCD_EnableInterrupts()
313 uint32_t gcrReg = base->GCR; in SLCD_DisableInterrupts()
328 base->GCR = gcrReg; in SLCD_DisableInterrupts()
Dfsl_slcd.h351 base->GCR |= LCD_GCR_LCDEN_MASK; in SLCD_StartDisplay()
362 base->GCR &= ~LCD_GCR_LCDEN_MASK; in SLCD_StopDisplay()
474 base->GCR |= LCD_GCR_PADSAFE_MASK; in SLCD_EnablePadSafeState()
478 base->GCR &= ~LCD_GCR_PADSAFE_MASK; in SLCD_EnablePadSafeState()
/hal_nxp-3.6.0/mcux/mcux-sdk/drivers/lpadc/
Dfsl_lpadc.c711 base->GCR[0] = LPADC_GetGainConvResult(GCRa); /* write A side GCALR. */ in LPADC_FinishAutoCalibration()
719 base->GCR[1] = LPADC_GetGainConvResult(GCRb); /* write B side GCALR. */ in LPADC_FinishAutoCalibration()
730 base->GCR[0] = ADC_GCR_GCALR(GCRa); in LPADC_FinishAutoCalibration()
731 base->GCR[1] = ADC_GCR_GCALR(GCRb); in LPADC_FinishAutoCalibration()
734 base->GCR[0] |= ADC_GCR_RDY_MASK; in LPADC_FinishAutoCalibration()
735 base->GCR[1] |= ADC_GCR_RDY_MASK; in LPADC_FinishAutoCalibration()
785 ptrCalibrationValue->gainCalibrationResultA = (uint16_t)(base->GCR[0] & ADC_GCR_GCALR_MASK); in LPADC_GetCalibrationValue()
786 ptrCalibrationValue->gainCalibrationResultB = (uint16_t)(base->GCR[1] & ADC_GCR_GCALR_MASK); in LPADC_GetCalibrationValue()
828 base->GCR[0] = ADC_GCR_GCALR(ptrCalibrationValue->gainCalibrationResultA) | ADC_GCR_RDY_MASK; in LPADC_SetCalibrationValue()
829 base->GCR[1] = ADC_GCR_GCALR(ptrCalibrationValue->gainCalibrationResultB) | ADC_GCR_RDY_MASK; in LPADC_SetCalibrationValue()
/hal_nxp-3.6.0/s32/drivers/s32ze/Uart/include/
DLinflexd_Uart_Ip_HwAccess.h566 RegValTemp = ((LINFLEXD_0IFCR_Type *)Base)->GCR; in Linflexd_Uart_Ip_SetTxStopBitsCount()
569 ((LINFLEXD_0IFCR_Type *)Base)->GCR = RegValTemp; in Linflexd_Uart_Ip_SetTxStopBitsCount()
573 RegValTemp = Base->GCR; in Linflexd_Uart_Ip_SetTxStopBitsCount()
576 Base->GCR = RegValTemp; in Linflexd_Uart_Ip_SetTxStopBitsCount()
580 RegValTemp = Base->GCR; in Linflexd_Uart_Ip_SetTxStopBitsCount()
583 Base->GCR = RegValTemp; in Linflexd_Uart_Ip_SetTxStopBitsCount()
/hal_nxp-3.6.0/s32/drivers/s32k1/Mcu/src/
DClock_Ip_Monitor.c240 if (CLOCK_IP_CMU_FREQUENCY_CHECK_ENABLED == (CmuFc->GCR & CMU_FC_GCR_FCE_MASK)) in Clock_Ip_DisableCmuFcFceRefCntLfrefHfref()
259 CmuFc->GCR &= ~CMU_FC_GCR_FCE_MASK; in Clock_Ip_DisableCmuFcFceRefCntLfrefHfref()
393 CmuFc->GCR |= CMU_FC_GCR_FCE_MASK; in Clock_Ip_EnableCmuFcFceRefCntLfrefHfref()
397 CmuFc->GCR &= ~CMU_FC_GCR_FCE_MASK; in Clock_Ip_EnableCmuFcFceRefCntLfrefHfref()
DClock_Ip_Specific.c657 …CmuConfiguration.Enable = (Clock_Ip_apxCmu[0U]->GCR & CMU_FC_GCR_FCE_MASK) >> CMU_FC_GCR_FCE_SHIFT; in getCmuFircConfig()
664 …CmuConfiguration.Enable = (Clock_Ip_apxCmu[1U]->GCR & CMU_FC_GCR_FCE_MASK) >> CMU_FC_GCR_FCE_SHIFT; in getCmuFircConfig()
/hal_nxp-3.6.0/s32/drivers/s32k3/Mcu/src/
DClock_Ip_Monitor.c272 if (CLOCK_IP_CMU_FREQUENCY_CHECK_ENABLED == (CmuFc->GCR & CMU_FC_GCR_FCE_MASK)) in Clock_Ip_DisableCmuFcFceRefCntLfrefHfref()
291 CmuFc->GCR &= ~CMU_FC_GCR_FCE_MASK; in Clock_Ip_DisableCmuFcFceRefCntLfrefHfref()
425 CmuFc->GCR |= CMU_FC_GCR_FCE_MASK; in Clock_Ip_EnableCmuFcFceRefCntLfrefHfref()
429 CmuFc->GCR &= ~CMU_FC_GCR_FCE_MASK; in Clock_Ip_EnableCmuFcFceRefCntLfrefHfref()
/hal_nxp-3.6.0/s32/drivers/s32ze/Mcu/src/
DClock_Ip_Monitor.c240 if (CLOCK_IP_CMU_FREQUENCY_CHECK_ENABLED == (CmuFc->GCR & CMU_FC_GCR_FCE_MASK)) in Clock_Ip_DisableCmuFcFceRefCntLfrefHfref()
259 CmuFc->GCR &= ~(uint8)(CMU_FC_GCR_FCE_MASK); in Clock_Ip_DisableCmuFcFceRefCntLfrefHfref()
413 CmuFc->GCR |= (uint8)(CMU_FC_GCR_FCE_MASK); in Clock_Ip_EnableCmuFcFceRefCntLfrefHfref()
417 CmuFc->GCR &= ~(uint8)(CMU_FC_GCR_FCE_MASK); in Clock_Ip_EnableCmuFcFceRefCntLfrefHfref()
/hal_nxp-3.6.0/mcux/mcux-sdk/drivers/dac_1/
Dfsl_dac.h288 base->GCR |= LPDAC_GCR_DACEN_MASK; in DAC_Enable()
292 base->GCR &= ~LPDAC_GCR_DACEN_MASK; in DAC_Enable()
Dfsl_dac.c147 base->GCR = tmp32; in DAC_Init()
/hal_nxp-3.6.0/s32/drivers/s32k3/BaseNXP/header/
DS32K344_CMU_FM.h73 …__IO uint32_t GCR; /**< Global Configuration Register, offset: 0x0 */ member
DS32K344_CMU_FC.h73 …__IO uint32_t GCR; /**< Global Configuration Register, offset: 0x0 */ member
DS32K344_MU.h89 __IO uint32_t GCR; /**< General Control Register, offset: 0x114 */ member
/hal_nxp-3.6.0/s32/drivers/s32k1/BaseNXP/header/
DS32K116_CMU.h73 …__IO uint32_t GCR; /**< Global Configuration Register, offset: 0x0 */ member
DS32K118_CMU.h73 …__IO uint32_t GCR; /**< Global Configuration Register, offset: 0x0 */ member
/hal_nxp-3.6.0/s32/drivers/s32ze/Mcu/include/
DClock_Ip_Specific.h248 uint8 GCR; /**< Global Configuration Register, offset: 0x0 */ member
/hal_nxp-3.6.0/s32/drivers/s32k1/Mcu/include/
DClock_Ip_Specific.h390 uint32 GCR; /**< Global Configuration Register, offset: 0x0 */ member
/hal_nxp-3.6.0/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_CMU_FC.h73 …__IO uint32_t GCR; /**< Global Configuration Register, offset: 0x0 */ member
DS32Z2_LINFLEXD.h90 __IO uint32_t GCR; /**< Global Control Register, offset: 0x4C */ member
DS32Z2_PSI5.h80 __IO uint16_t GCR; /**< Global Control Register, offset: 0x2 */ member
DS32Z2_MU.h89 …__IO uint32_t GCR; /**< General-purpose Control Register, offset: 0x… member
DS32Z2_PSI5_S.h92 …__I uint32_t GCR; /**< PSI5_S Global Control register, offset: 0x4C… member
/hal_nxp-3.6.0/s32/drivers/s32k3/Mcu/include/
DClock_Ip_Specific.h405 uint32 GCR; /**< Global Configuration Register, offset: 0x0 */ member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/K32L2B11A/
DK32L2B11A.h3259 __IO uint32_t GCR; /**< LCD General Control Register, offset: 0x0 */ member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/K32L2B31A/
DK32L2B31A.h3259 __IO uint32_t GCR; /**< LCD General Control Register, offset: 0x0 */ member

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