1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2023 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_PSI5_S.h 10 * @version 2.1 11 * @date 2023-07-20 12 * @brief Peripheral Access Layer for S32Z2_PSI5_S 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_PSI5_S_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_PSI5_S_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- PSI5_S Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup PSI5_S_Peripheral_Access_Layer PSI5_S Peripheral Access Layer 68 * @{ 69 */ 70 71 /** PSI5_S - Size of Registers Arrays */ 72 #define PSI5_S_IRQ_COUNT 8u 73 #define PSI5_S_CH_COUNT 7u 74 75 /** PSI5_S - Register Layout Typedef */ 76 typedef struct { 77 __IO uint32_t LINCR1; /**< PSI5_S LIN Control Register 1, offset: 0x0 */ 78 __IO uint32_t LINIER; /**< PSI5_S LIN Interrupt enable register, offset: 0x4 */ 79 __I uint32_t LINSR; /**< PSI5_S LIN Status Register, offset: 0x8 */ 80 uint8_t RESERVED_0[4]; 81 __IO uint32_t UARTCR; /**< PSI5_S UART Mode Control Register, offset: 0x10 */ 82 __IO uint32_t UARTSR; /**< PSI5_S UART Mode Status Register, offset: 0x14 */ 83 uint8_t RESERVED_1[12]; 84 __IO uint32_t LINFBRR; /**< PSI5_S LIN Fractional Baud Rate Register, offset: 0x24 */ 85 __IO uint32_t LINIBRR; /**< PSI5_S LIN Integer Baud Rate Register, offset: 0x28 */ 86 uint8_t RESERVED_2[4]; 87 __I uint32_t LINCR2; /**< PSI5_S LIN Control Register 2, offset: 0x30 */ 88 uint8_t RESERVED_3[4]; 89 __IO uint32_t BDRL; /**< PSI5_S Buffer Data Register Least Significant, offset: 0x38 */ 90 __IO uint32_t BDRM; /**< PSI5_S Buffer Data Register Most Significant, offset: 0x3C */ 91 uint8_t RESERVED_4[12]; 92 __I uint32_t GCR; /**< PSI5_S Global Control register, offset: 0x4C */ 93 __IO uint32_t UARTPTO; /**< PSI5_S UART Preset Timeout Register, offset: 0x50 */ 94 __I uint32_t UARTCTO; /**< PSI5_S UART Current Timeout register, offset: 0x54 */ 95 __IO uint32_t DMATXE; /**< DMA Tx Enable Register, offset: 0x58 */ 96 __IO uint32_t DMARXE; /**< DMA Rx Enable Register, offset: 0x5C */ 97 __IO uint32_t PTD; /**< PSI5_S UART Tx Idle Delay Time Register, offset: 0x60 */ 98 uint8_t RESERVED_5[80]; 99 __IO uint32_t GLCR; /**< PSI5_S Global Control Register, offset: 0xB4 */ 100 __IO uint32_t GLSR; /**< PSI5_S Global Status Register, offset: 0xB8 */ 101 __IO uint32_t CH_BASE_ADDR; /**< PSI5_S CHANNEL_BASE_ADDRESS, offset: 0xBC */ 102 __I uint32_t MRU_BUF2_REG0; /**< PSI5_S MRU OUTPUT BUFFER2 REGISTER0, offset: 0xC0 */ 103 __I uint32_t MRU_BUF2_REG1; /**< PSI5_S MRU OUTPUT BUFFER2 REGISTER1, offset: 0xC4 */ 104 __I uint32_t MRU_BUF2_REG2; /**< PSI5_S MRU OUTPUT BUFFER2 REGISTER2, offset: 0xC8 */ 105 __I uint32_t MRU_BUF2_REG3; /**< PSI5_S MRU OUTPUT BUFFER2 REGISTER3, offset: 0xCC */ 106 uint8_t RESERVED_6[16]; 107 __I uint32_t MBOX_SR_IRQ; /**< PSI5_S Mbox Status Irq, offset: 0xE0 */ 108 __IO uint32_t ERR_SR_IRQ; /**< PSI5_S Error Status IRQ, offset: 0xE4 */ 109 struct { /* offset: 0xE8, array step: 0x8 */ 110 __IO uint32_t MBOX_SEL_IRQ; /**< PSI5_S Mailbox select IRQ[irq_n], array offset: 0xE8, array step: 0x8 */ 111 __IO uint32_t ERR_SEL_IRQ; /**< PSI5_S Error Select IRQ[irq_n], array offset: 0xEC, array step: 0x8 */ 112 } IRQ[PSI5_S_IRQ_COUNT]; 113 __I uint32_t WDGTSSR; /**< PSI5_S Watchdog Error Status and Watchdog Timestamp status register, offset: 0x128 */ 114 __I uint32_t DIRCMD; /**< PSI5_S ECU to Sensor Direct Command Write register, offset: 0x12C */ 115 uint8_t RESERVED_7[60]; 116 __IO uint32_t CH0_MSGA; /**< PSI5_S channel 0 message configuration register A, offset: 0x16C */ 117 __IO uint32_t CH0_MSGB; /**< PSI5_S channel 0 message configuration register B, offset: 0x170 */ 118 uint8_t RESERVED_8[4]; 119 __IO uint32_t CH0_MBOX_SR; /**< PSI5_S Mailbox status register channel0, offset: 0x178 */ 120 uint8_t RESERVED_9[20]; 121 struct { /* offset: 0x190, array step: 0x3C */ 122 __IO uint32_t MSGA; /**< PSI5_S channel message configuration register A, array offset: 0x190, array step: 0x3C */ 123 __IO uint32_t MSGB; /**< PSI5_S channel message configuration register B, array offset: 0x194, array step: 0x3C */ 124 uint8_t RESERVED_0[4]; 125 __IO uint32_t MBOX_SR; /**< PSI5_S Mailbox status register channel, array offset: 0x19C, array step: 0x3C */ 126 __IO uint32_t WD_CFGR; /**< PSI5_S channel watchdog configuration register, array offset: 0x1A0, array step: 0x3C */ 127 __IO uint32_t DDTRIG_OFFR; /**< PSI5_S DDSR Trigger offset register channel, array offset: 0x1A4, array step: 0x3C */ 128 __IO uint32_t DDTRIG_PERR; /**< PSI5_S DDSR Trigger period register channel, array offset: 0x1A8, array step: 0x3C */ 129 __IO uint32_t E2SCR; /**< PSI5_S ECU to Sensor Control Register, array offset: 0x1AC, array step: 0x3C */ 130 __IO uint32_t E2SSR; /**< PSI5_S ECU to Sensor Status Register, array offset: 0x1B0, array step: 0x3C */ 131 __I uint32_t DDSR_H; /**< PSI5_S channel1 ECU to Sensor Downstream Data Shift Register High, array offset: 0x1B4, array step: 0x3C */ 132 __IO uint32_t DDSR_L; /**< PSI5_S channel1 ECU to Sensor Downstream Data Shift Register Low, array offset: 0x1B8, array step: 0x3C */ 133 uint8_t RESERVED_1[16]; 134 } CH[PSI5_S_CH_COUNT]; 135 } PSI5_S_Type, *PSI5_S_MemMapPtr; 136 137 /** Number of instances of the PSI5_S module. */ 138 #define PSI5_S_INSTANCE_COUNT (2u) 139 140 /* PSI5_S - Peripheral instance base addresses */ 141 /** Peripheral PSI5_S_0 base address */ 142 #define IP_PSI5_S_0_BASE (0x401F0000u) 143 /** Peripheral PSI5_S_0 base pointer */ 144 #define IP_PSI5_S_0 ((PSI5_S_Type *)IP_PSI5_S_0_BASE) 145 /** Peripheral PSI5_S_1 base address */ 146 #define IP_PSI5_S_1_BASE (0x421F0000u) 147 /** Peripheral PSI5_S_1 base pointer */ 148 #define IP_PSI5_S_1 ((PSI5_S_Type *)IP_PSI5_S_1_BASE) 149 /** Array initializer of PSI5_S peripheral base addresses */ 150 #define IP_PSI5_S_BASE_ADDRS { IP_PSI5_S_0_BASE, IP_PSI5_S_1_BASE } 151 /** Array initializer of PSI5_S peripheral base pointers */ 152 #define IP_PSI5_S_BASE_PTRS { IP_PSI5_S_0, IP_PSI5_S_1 } 153 154 /* ---------------------------------------------------------------------------- 155 -- PSI5_S Register Masks 156 ---------------------------------------------------------------------------- */ 157 158 /*! 159 * @addtogroup PSI5_S_Register_Masks PSI5_S Register Masks 160 * @{ 161 */ 162 163 /*! @name LINCR1 - PSI5_S LIN Control Register 1 */ 164 /*! @{ */ 165 166 #define PSI5_S_LINCR1_INIT_MASK (0x1U) 167 #define PSI5_S_LINCR1_INIT_SHIFT (0U) 168 #define PSI5_S_LINCR1_INIT_WIDTH (1U) 169 #define PSI5_S_LINCR1_INIT(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_LINCR1_INIT_SHIFT)) & PSI5_S_LINCR1_INIT_MASK) 170 171 #define PSI5_S_LINCR1_SLEEP_MASK (0x2U) 172 #define PSI5_S_LINCR1_SLEEP_SHIFT (1U) 173 #define PSI5_S_LINCR1_SLEEP_WIDTH (1U) 174 #define PSI5_S_LINCR1_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_LINCR1_SLEEP_SHIFT)) & PSI5_S_LINCR1_SLEEP_MASK) 175 176 #define PSI5_S_LINCR1_RBLM_MASK (0x4U) 177 #define PSI5_S_LINCR1_RBLM_SHIFT (2U) 178 #define PSI5_S_LINCR1_RBLM_WIDTH (1U) 179 #define PSI5_S_LINCR1_RBLM(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_LINCR1_RBLM_SHIFT)) & PSI5_S_LINCR1_RBLM_MASK) 180 181 #define PSI5_S_LINCR1_LBKM_MASK (0x20U) 182 #define PSI5_S_LINCR1_LBKM_SHIFT (5U) 183 #define PSI5_S_LINCR1_LBKM_WIDTH (1U) 184 #define PSI5_S_LINCR1_LBKM(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_LINCR1_LBKM_SHIFT)) & PSI5_S_LINCR1_LBKM_MASK) 185 186 #define PSI5_S_LINCR1_SLFM_MASK (0x40U) 187 #define PSI5_S_LINCR1_SLFM_SHIFT (6U) 188 #define PSI5_S_LINCR1_SLFM_WIDTH (1U) 189 #define PSI5_S_LINCR1_SLFM(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_LINCR1_SLFM_SHIFT)) & PSI5_S_LINCR1_SLFM_MASK) 190 191 #define PSI5_S_LINCR1_AUTOWU_MASK (0x1000U) 192 #define PSI5_S_LINCR1_AUTOWU_SHIFT (12U) 193 #define PSI5_S_LINCR1_AUTOWU_WIDTH (1U) 194 #define PSI5_S_LINCR1_AUTOWU(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_LINCR1_AUTOWU_SHIFT)) & PSI5_S_LINCR1_AUTOWU_MASK) 195 /*! @} */ 196 197 /*! @name LINIER - PSI5_S LIN Interrupt enable register */ 198 /*! @{ */ 199 200 #define PSI5_S_LINIER_DTIE_MASK (0x2U) 201 #define PSI5_S_LINIER_DTIE_SHIFT (1U) 202 #define PSI5_S_LINIER_DTIE_WIDTH (1U) 203 #define PSI5_S_LINIER_DTIE(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_LINIER_DTIE_SHIFT)) & PSI5_S_LINIER_DTIE_MASK) 204 205 #define PSI5_S_LINIER_DRIE_MASK (0x4U) 206 #define PSI5_S_LINIER_DRIE_SHIFT (2U) 207 #define PSI5_S_LINIER_DRIE_WIDTH (1U) 208 #define PSI5_S_LINIER_DRIE(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_LINIER_DRIE_SHIFT)) & PSI5_S_LINIER_DRIE_MASK) 209 210 #define PSI5_S_LINIER_TOIE_MASK (0x8U) 211 #define PSI5_S_LINIER_TOIE_SHIFT (3U) 212 #define PSI5_S_LINIER_TOIE_WIDTH (1U) 213 #define PSI5_S_LINIER_TOIE(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_LINIER_TOIE_SHIFT)) & PSI5_S_LINIER_TOIE_MASK) 214 215 #define PSI5_S_LINIER_WUIE_MASK (0x20U) 216 #define PSI5_S_LINIER_WUIE_SHIFT (5U) 217 #define PSI5_S_LINIER_WUIE_WIDTH (1U) 218 #define PSI5_S_LINIER_WUIE(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_LINIER_WUIE_SHIFT)) & PSI5_S_LINIER_WUIE_MASK) 219 220 #define PSI5_S_LINIER_BOIE_MASK (0x80U) 221 #define PSI5_S_LINIER_BOIE_SHIFT (7U) 222 #define PSI5_S_LINIER_BOIE_WIDTH (1U) 223 #define PSI5_S_LINIER_BOIE(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_LINIER_BOIE_SHIFT)) & PSI5_S_LINIER_BOIE_MASK) 224 225 #define PSI5_S_LINIER_FEIE_MASK (0x100U) 226 #define PSI5_S_LINIER_FEIE_SHIFT (8U) 227 #define PSI5_S_LINIER_FEIE_WIDTH (1U) 228 #define PSI5_S_LINIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_LINIER_FEIE_SHIFT)) & PSI5_S_LINIER_FEIE_MASK) 229 230 #define PSI5_S_LINIER_OCIE_MASK (0x4000U) 231 #define PSI5_S_LINIER_OCIE_SHIFT (14U) 232 #define PSI5_S_LINIER_OCIE_WIDTH (1U) 233 #define PSI5_S_LINIER_OCIE(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_LINIER_OCIE_SHIFT)) & PSI5_S_LINIER_OCIE_MASK) 234 235 #define PSI5_S_LINIER_SZIE_MASK (0x8000U) 236 #define PSI5_S_LINIER_SZIE_SHIFT (15U) 237 #define PSI5_S_LINIER_SZIE_WIDTH (1U) 238 #define PSI5_S_LINIER_SZIE(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_LINIER_SZIE_SHIFT)) & PSI5_S_LINIER_SZIE_MASK) 239 /*! @} */ 240 241 /*! @name LINSR - PSI5_S LIN Status Register */ 242 /*! @{ */ 243 244 #define PSI5_S_LINSR_LINS0_MASK (0x1000U) 245 #define PSI5_S_LINSR_LINS0_SHIFT (12U) 246 #define PSI5_S_LINSR_LINS0_WIDTH (1U) 247 #define PSI5_S_LINSR_LINS0(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_LINSR_LINS0_SHIFT)) & PSI5_S_LINSR_LINS0_MASK) 248 249 #define PSI5_S_LINSR_LINS1_MASK (0x2000U) 250 #define PSI5_S_LINSR_LINS1_SHIFT (13U) 251 #define PSI5_S_LINSR_LINS1_WIDTH (1U) 252 #define PSI5_S_LINSR_LINS1(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_LINSR_LINS1_SHIFT)) & PSI5_S_LINSR_LINS1_MASK) 253 254 #define PSI5_S_LINSR_LINS2_MASK (0x4000U) 255 #define PSI5_S_LINSR_LINS2_SHIFT (14U) 256 #define PSI5_S_LINSR_LINS2_WIDTH (1U) 257 #define PSI5_S_LINSR_LINS2(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_LINSR_LINS2_SHIFT)) & PSI5_S_LINSR_LINS2_MASK) 258 259 #define PSI5_S_LINSR_LINS3_MASK (0x8000U) 260 #define PSI5_S_LINSR_LINS3_SHIFT (15U) 261 #define PSI5_S_LINSR_LINS3_WIDTH (1U) 262 #define PSI5_S_LINSR_LINS3(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_LINSR_LINS3_SHIFT)) & PSI5_S_LINSR_LINS3_MASK) 263 /*! @} */ 264 265 /*! @name UARTCR - PSI5_S UART Mode Control Register */ 266 /*! @{ */ 267 268 #define PSI5_S_UARTCR_UART_MASK (0x1U) 269 #define PSI5_S_UARTCR_UART_SHIFT (0U) 270 #define PSI5_S_UARTCR_UART_WIDTH (1U) 271 #define PSI5_S_UARTCR_UART(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_UARTCR_UART_SHIFT)) & PSI5_S_UARTCR_UART_MASK) 272 273 #define PSI5_S_UARTCR_WL0_MASK (0x2U) 274 #define PSI5_S_UARTCR_WL0_SHIFT (1U) 275 #define PSI5_S_UARTCR_WL0_WIDTH (1U) 276 #define PSI5_S_UARTCR_WL0(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_UARTCR_WL0_SHIFT)) & PSI5_S_UARTCR_WL0_MASK) 277 278 #define PSI5_S_UARTCR_PCE_Rx_MASK (0x4U) 279 #define PSI5_S_UARTCR_PCE_Rx_SHIFT (2U) 280 #define PSI5_S_UARTCR_PCE_Rx_WIDTH (1U) 281 #define PSI5_S_UARTCR_PCE_Rx(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_UARTCR_PCE_Rx_SHIFT)) & PSI5_S_UARTCR_PCE_Rx_MASK) 282 283 #define PSI5_S_UARTCR_PC0_MASK (0x8U) 284 #define PSI5_S_UARTCR_PC0_SHIFT (3U) 285 #define PSI5_S_UARTCR_PC0_WIDTH (1U) 286 #define PSI5_S_UARTCR_PC0(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_UARTCR_PC0_SHIFT)) & PSI5_S_UARTCR_PC0_MASK) 287 288 #define PSI5_S_UARTCR_TxEn_MASK (0x10U) 289 #define PSI5_S_UARTCR_TxEn_SHIFT (4U) 290 #define PSI5_S_UARTCR_TxEn_WIDTH (1U) 291 #define PSI5_S_UARTCR_TxEn(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_UARTCR_TxEn_SHIFT)) & PSI5_S_UARTCR_TxEn_MASK) 292 293 #define PSI5_S_UARTCR_RxEn_MASK (0x20U) 294 #define PSI5_S_UARTCR_RxEn_SHIFT (5U) 295 #define PSI5_S_UARTCR_RxEn_WIDTH (1U) 296 #define PSI5_S_UARTCR_RxEn(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_UARTCR_RxEn_SHIFT)) & PSI5_S_UARTCR_RxEn_MASK) 297 298 #define PSI5_S_UARTCR_PC1_MASK (0x40U) 299 #define PSI5_S_UARTCR_PC1_SHIFT (6U) 300 #define PSI5_S_UARTCR_PC1_WIDTH (1U) 301 #define PSI5_S_UARTCR_PC1(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_UARTCR_PC1_SHIFT)) & PSI5_S_UARTCR_PC1_MASK) 302 303 #define PSI5_S_UARTCR_WL1_MASK (0x80U) 304 #define PSI5_S_UARTCR_WL1_SHIFT (7U) 305 #define PSI5_S_UARTCR_WL1_WIDTH (1U) 306 #define PSI5_S_UARTCR_WL1(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_UARTCR_WL1_SHIFT)) & PSI5_S_UARTCR_WL1_MASK) 307 308 #define PSI5_S_UARTCR_TFBM_MASK (0x100U) 309 #define PSI5_S_UARTCR_TFBM_SHIFT (8U) 310 #define PSI5_S_UARTCR_TFBM_WIDTH (1U) 311 #define PSI5_S_UARTCR_TFBM(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_UARTCR_TFBM_SHIFT)) & PSI5_S_UARTCR_TFBM_MASK) 312 313 #define PSI5_S_UARTCR_RFBM_MASK (0x200U) 314 #define PSI5_S_UARTCR_RFBM_SHIFT (9U) 315 #define PSI5_S_UARTCR_RFBM_WIDTH (1U) 316 #define PSI5_S_UARTCR_RFBM(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_UARTCR_RFBM_SHIFT)) & PSI5_S_UARTCR_RFBM_MASK) 317 318 #define PSI5_S_UARTCR_RDFLRFC_MASK (0x1C00U) 319 #define PSI5_S_UARTCR_RDFLRFC_SHIFT (10U) 320 #define PSI5_S_UARTCR_RDFLRFC_WIDTH (3U) 321 #define PSI5_S_UARTCR_RDFLRFC(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_UARTCR_RDFLRFC_SHIFT)) & PSI5_S_UARTCR_RDFLRFC_MASK) 322 323 #define PSI5_S_UARTCR_TDFLTFC_MASK (0xE000U) 324 #define PSI5_S_UARTCR_TDFLTFC_SHIFT (13U) 325 #define PSI5_S_UARTCR_TDFLTFC_WIDTH (3U) 326 #define PSI5_S_UARTCR_TDFLTFC(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_UARTCR_TDFLTFC_SHIFT)) & PSI5_S_UARTCR_TDFLTFC_MASK) 327 328 #define PSI5_S_UARTCR_WLS_MASK (0x10000U) 329 #define PSI5_S_UARTCR_WLS_SHIFT (16U) 330 #define PSI5_S_UARTCR_WLS_WIDTH (1U) 331 #define PSI5_S_UARTCR_WLS(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_UARTCR_WLS_SHIFT)) & PSI5_S_UARTCR_WLS_MASK) 332 333 #define PSI5_S_UARTCR_SBUR_MASK (0x60000U) 334 #define PSI5_S_UARTCR_SBUR_SHIFT (17U) 335 #define PSI5_S_UARTCR_SBUR_WIDTH (2U) 336 #define PSI5_S_UARTCR_SBUR(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_UARTCR_SBUR_SHIFT)) & PSI5_S_UARTCR_SBUR_MASK) 337 338 #define PSI5_S_UARTCR_PCE_TXDTU_MASK (0x80000U) 339 #define PSI5_S_UARTCR_PCE_TXDTU_SHIFT (19U) 340 #define PSI5_S_UARTCR_PCE_TXDTU_WIDTH (1U) 341 #define PSI5_S_UARTCR_PCE_TXDTU(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_UARTCR_PCE_TXDTU_SHIFT)) & PSI5_S_UARTCR_PCE_TXDTU_MASK) 342 343 #define PSI5_S_UARTCR_NEF_MASK (0x700000U) 344 #define PSI5_S_UARTCR_NEF_SHIFT (20U) 345 #define PSI5_S_UARTCR_NEF_WIDTH (3U) 346 #define PSI5_S_UARTCR_NEF(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_UARTCR_NEF_SHIFT)) & PSI5_S_UARTCR_NEF_MASK) 347 348 #define PSI5_S_UARTCR_ROSE_MASK (0x800000U) 349 #define PSI5_S_UARTCR_ROSE_SHIFT (23U) 350 #define PSI5_S_UARTCR_ROSE_WIDTH (1U) 351 #define PSI5_S_UARTCR_ROSE(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_UARTCR_ROSE_SHIFT)) & PSI5_S_UARTCR_ROSE_MASK) 352 353 #define PSI5_S_UARTCR_OSR_MASK (0xF000000U) 354 #define PSI5_S_UARTCR_OSR_SHIFT (24U) 355 #define PSI5_S_UARTCR_OSR_WIDTH (4U) 356 #define PSI5_S_UARTCR_OSR(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_UARTCR_OSR_SHIFT)) & PSI5_S_UARTCR_OSR_MASK) 357 358 #define PSI5_S_UARTCR_CSP_MASK (0x70000000U) 359 #define PSI5_S_UARTCR_CSP_SHIFT (28U) 360 #define PSI5_S_UARTCR_CSP_WIDTH (3U) 361 #define PSI5_S_UARTCR_CSP(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_UARTCR_CSP_SHIFT)) & PSI5_S_UARTCR_CSP_MASK) 362 363 #define PSI5_S_UARTCR_MIS_MASK (0x80000000U) 364 #define PSI5_S_UARTCR_MIS_SHIFT (31U) 365 #define PSI5_S_UARTCR_MIS_WIDTH (1U) 366 #define PSI5_S_UARTCR_MIS(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_UARTCR_MIS_SHIFT)) & PSI5_S_UARTCR_MIS_MASK) 367 /*! @} */ 368 369 /*! @name UARTSR - PSI5_S UART Mode Status Register */ 370 /*! @{ */ 371 372 #define PSI5_S_UARTSR_NF_MASK (0x1U) 373 #define PSI5_S_UARTSR_NF_SHIFT (0U) 374 #define PSI5_S_UARTSR_NF_WIDTH (1U) 375 #define PSI5_S_UARTSR_NF(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_UARTSR_NF_SHIFT)) & PSI5_S_UARTSR_NF_MASK) 376 377 #define PSI5_S_UARTSR_DTF_MASK (0x2U) 378 #define PSI5_S_UARTSR_DTF_SHIFT (1U) 379 #define PSI5_S_UARTSR_DTF_WIDTH (1U) 380 #define PSI5_S_UARTSR_DTF(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_UARTSR_DTF_SHIFT)) & PSI5_S_UARTSR_DTF_MASK) 381 382 #define PSI5_S_UARTSR_DRF_MASK (0x4U) 383 #define PSI5_S_UARTSR_DRF_SHIFT (2U) 384 #define PSI5_S_UARTSR_DRF_WIDTH (1U) 385 #define PSI5_S_UARTSR_DRF(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_UARTSR_DRF_SHIFT)) & PSI5_S_UARTSR_DRF_MASK) 386 387 #define PSI5_S_UARTSR_TO_MASK (0x8U) 388 #define PSI5_S_UARTSR_TO_SHIFT (3U) 389 #define PSI5_S_UARTSR_TO_WIDTH (1U) 390 #define PSI5_S_UARTSR_TO(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_UARTSR_TO_SHIFT)) & PSI5_S_UARTSR_TO_MASK) 391 392 #define PSI5_S_UARTSR_RFNE_MASK (0x10U) 393 #define PSI5_S_UARTSR_RFNE_SHIFT (4U) 394 #define PSI5_S_UARTSR_RFNE_WIDTH (1U) 395 #define PSI5_S_UARTSR_RFNE(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_UARTSR_RFNE_SHIFT)) & PSI5_S_UARTSR_RFNE_MASK) 396 397 #define PSI5_S_UARTSR_WUF_MASK (0x20U) 398 #define PSI5_S_UARTSR_WUF_SHIFT (5U) 399 #define PSI5_S_UARTSR_WUF_WIDTH (1U) 400 #define PSI5_S_UARTSR_WUF(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_UARTSR_WUF_SHIFT)) & PSI5_S_UARTSR_WUF_MASK) 401 402 #define PSI5_S_UARTSR_RDI_MASK (0x40U) 403 #define PSI5_S_UARTSR_RDI_SHIFT (6U) 404 #define PSI5_S_UARTSR_RDI_WIDTH (1U) 405 #define PSI5_S_UARTSR_RDI(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_UARTSR_RDI_SHIFT)) & PSI5_S_UARTSR_RDI_MASK) 406 407 #define PSI5_S_UARTSR_BOF_MASK (0x80U) 408 #define PSI5_S_UARTSR_BOF_SHIFT (7U) 409 #define PSI5_S_UARTSR_BOF_WIDTH (1U) 410 #define PSI5_S_UARTSR_BOF(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_UARTSR_BOF_SHIFT)) & PSI5_S_UARTSR_BOF_MASK) 411 412 #define PSI5_S_UARTSR_FEF_MASK (0x100U) 413 #define PSI5_S_UARTSR_FEF_SHIFT (8U) 414 #define PSI5_S_UARTSR_FEF_WIDTH (1U) 415 #define PSI5_S_UARTSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_UARTSR_FEF_SHIFT)) & PSI5_S_UARTSR_FEF_MASK) 416 417 #define PSI5_S_UARTSR_RMB_MASK (0x200U) 418 #define PSI5_S_UARTSR_RMB_SHIFT (9U) 419 #define PSI5_S_UARTSR_RMB_WIDTH (1U) 420 #define PSI5_S_UARTSR_RMB(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_UARTSR_RMB_SHIFT)) & PSI5_S_UARTSR_RMB_MASK) 421 422 #define PSI5_S_UARTSR_PE0_MASK (0x400U) 423 #define PSI5_S_UARTSR_PE0_SHIFT (10U) 424 #define PSI5_S_UARTSR_PE0_WIDTH (1U) 425 #define PSI5_S_UARTSR_PE0(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_UARTSR_PE0_SHIFT)) & PSI5_S_UARTSR_PE0_MASK) 426 427 #define PSI5_S_UARTSR_PE1_MASK (0x800U) 428 #define PSI5_S_UARTSR_PE1_SHIFT (11U) 429 #define PSI5_S_UARTSR_PE1_WIDTH (1U) 430 #define PSI5_S_UARTSR_PE1(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_UARTSR_PE1_SHIFT)) & PSI5_S_UARTSR_PE1_MASK) 431 432 #define PSI5_S_UARTSR_PE2_MASK (0x1000U) 433 #define PSI5_S_UARTSR_PE2_SHIFT (12U) 434 #define PSI5_S_UARTSR_PE2_WIDTH (1U) 435 #define PSI5_S_UARTSR_PE2(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_UARTSR_PE2_SHIFT)) & PSI5_S_UARTSR_PE2_MASK) 436 437 #define PSI5_S_UARTSR_PE3_MASK (0x2000U) 438 #define PSI5_S_UARTSR_PE3_SHIFT (13U) 439 #define PSI5_S_UARTSR_PE3_WIDTH (1U) 440 #define PSI5_S_UARTSR_PE3(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_UARTSR_PE3_SHIFT)) & PSI5_S_UARTSR_PE3_MASK) 441 442 #define PSI5_S_UARTSR_OCF_MASK (0x4000U) 443 #define PSI5_S_UARTSR_OCF_SHIFT (14U) 444 #define PSI5_S_UARTSR_OCF_WIDTH (1U) 445 #define PSI5_S_UARTSR_OCF(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_UARTSR_OCF_SHIFT)) & PSI5_S_UARTSR_OCF_MASK) 446 447 #define PSI5_S_UARTSR_SZF_MASK (0x8000U) 448 #define PSI5_S_UARTSR_SZF_SHIFT (15U) 449 #define PSI5_S_UARTSR_SZF_WIDTH (1U) 450 #define PSI5_S_UARTSR_SZF(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_UARTSR_SZF_SHIFT)) & PSI5_S_UARTSR_SZF_MASK) 451 /*! @} */ 452 453 /*! @name LINFBRR - PSI5_S LIN Fractional Baud Rate Register */ 454 /*! @{ */ 455 456 #define PSI5_S_LINFBRR_FBR_MASK (0xFU) 457 #define PSI5_S_LINFBRR_FBR_SHIFT (0U) 458 #define PSI5_S_LINFBRR_FBR_WIDTH (4U) 459 #define PSI5_S_LINFBRR_FBR(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_LINFBRR_FBR_SHIFT)) & PSI5_S_LINFBRR_FBR_MASK) 460 /*! @} */ 461 462 /*! @name LINIBRR - PSI5_S LIN Integer Baud Rate Register */ 463 /*! @{ */ 464 465 #define PSI5_S_LINIBRR_IBR_MASK (0xFFFFFU) 466 #define PSI5_S_LINIBRR_IBR_SHIFT (0U) 467 #define PSI5_S_LINIBRR_IBR_WIDTH (20U) 468 #define PSI5_S_LINIBRR_IBR(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_LINIBRR_IBR_SHIFT)) & PSI5_S_LINIBRR_IBR_MASK) 469 /*! @} */ 470 471 /*! @name LINCR2 - PSI5_S LIN Control Register 2 */ 472 /*! @{ */ 473 474 #define PSI5_S_LINCR2_ABRQ_MASK (0x200U) 475 #define PSI5_S_LINCR2_ABRQ_SHIFT (9U) 476 #define PSI5_S_LINCR2_ABRQ_WIDTH (1U) 477 #define PSI5_S_LINCR2_ABRQ(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_LINCR2_ABRQ_SHIFT)) & PSI5_S_LINCR2_ABRQ_MASK) 478 /*! @} */ 479 480 /*! @name BDRL - PSI5_S Buffer Data Register Least Significant */ 481 /*! @{ */ 482 483 #define PSI5_S_BDRL_DATA_TX0_MASK (0xFFU) 484 #define PSI5_S_BDRL_DATA_TX0_SHIFT (0U) 485 #define PSI5_S_BDRL_DATA_TX0_WIDTH (8U) 486 #define PSI5_S_BDRL_DATA_TX0(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_BDRL_DATA_TX0_SHIFT)) & PSI5_S_BDRL_DATA_TX0_MASK) 487 488 #define PSI5_S_BDRL_DATA_TX1_MASK (0xFF00U) 489 #define PSI5_S_BDRL_DATA_TX1_SHIFT (8U) 490 #define PSI5_S_BDRL_DATA_TX1_WIDTH (8U) 491 #define PSI5_S_BDRL_DATA_TX1(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_BDRL_DATA_TX1_SHIFT)) & PSI5_S_BDRL_DATA_TX1_MASK) 492 493 #define PSI5_S_BDRL_DATA_TX2_MASK (0xFF0000U) 494 #define PSI5_S_BDRL_DATA_TX2_SHIFT (16U) 495 #define PSI5_S_BDRL_DATA_TX2_WIDTH (8U) 496 #define PSI5_S_BDRL_DATA_TX2(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_BDRL_DATA_TX2_SHIFT)) & PSI5_S_BDRL_DATA_TX2_MASK) 497 498 #define PSI5_S_BDRL_DATA_TX3_MASK (0xFF000000U) 499 #define PSI5_S_BDRL_DATA_TX3_SHIFT (24U) 500 #define PSI5_S_BDRL_DATA_TX3_WIDTH (8U) 501 #define PSI5_S_BDRL_DATA_TX3(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_BDRL_DATA_TX3_SHIFT)) & PSI5_S_BDRL_DATA_TX3_MASK) 502 /*! @} */ 503 504 /*! @name BDRM - PSI5_S Buffer Data Register Most Significant */ 505 /*! @{ */ 506 507 #define PSI5_S_BDRM_DATA_RX0_MASK (0xFFU) 508 #define PSI5_S_BDRM_DATA_RX0_SHIFT (0U) 509 #define PSI5_S_BDRM_DATA_RX0_WIDTH (8U) 510 #define PSI5_S_BDRM_DATA_RX0(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_BDRM_DATA_RX0_SHIFT)) & PSI5_S_BDRM_DATA_RX0_MASK) 511 512 #define PSI5_S_BDRM_DATA_RX1_MASK (0xFF00U) 513 #define PSI5_S_BDRM_DATA_RX1_SHIFT (8U) 514 #define PSI5_S_BDRM_DATA_RX1_WIDTH (8U) 515 #define PSI5_S_BDRM_DATA_RX1(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_BDRM_DATA_RX1_SHIFT)) & PSI5_S_BDRM_DATA_RX1_MASK) 516 517 #define PSI5_S_BDRM_DATA_RX2_MASK (0xFF0000U) 518 #define PSI5_S_BDRM_DATA_RX2_SHIFT (16U) 519 #define PSI5_S_BDRM_DATA_RX2_WIDTH (8U) 520 #define PSI5_S_BDRM_DATA_RX2(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_BDRM_DATA_RX2_SHIFT)) & PSI5_S_BDRM_DATA_RX2_MASK) 521 522 #define PSI5_S_BDRM_DATA_RX3_MASK (0xFF000000U) 523 #define PSI5_S_BDRM_DATA_RX3_SHIFT (24U) 524 #define PSI5_S_BDRM_DATA_RX3_WIDTH (8U) 525 #define PSI5_S_BDRM_DATA_RX3(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_BDRM_DATA_RX3_SHIFT)) & PSI5_S_BDRM_DATA_RX3_MASK) 526 /*! @} */ 527 528 /*! @name GCR - PSI5_S Global Control register */ 529 /*! @{ */ 530 531 #define PSI5_S_GCR_SR_MASK (0x1U) 532 #define PSI5_S_GCR_SR_SHIFT (0U) 533 #define PSI5_S_GCR_SR_WIDTH (1U) 534 #define PSI5_S_GCR_SR(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_GCR_SR_SHIFT)) & PSI5_S_GCR_SR_MASK) 535 536 #define PSI5_S_GCR_STOP_MASK (0x2U) 537 #define PSI5_S_GCR_STOP_SHIFT (1U) 538 #define PSI5_S_GCR_STOP_WIDTH (1U) 539 #define PSI5_S_GCR_STOP(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_GCR_STOP_SHIFT)) & PSI5_S_GCR_STOP_MASK) 540 541 #define PSI5_S_GCR_RDLIS_MASK (0x4U) 542 #define PSI5_S_GCR_RDLIS_SHIFT (2U) 543 #define PSI5_S_GCR_RDLIS_WIDTH (1U) 544 #define PSI5_S_GCR_RDLIS(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_GCR_RDLIS_SHIFT)) & PSI5_S_GCR_RDLIS_MASK) 545 546 #define PSI5_S_GCR_TDLIS_MASK (0x8U) 547 #define PSI5_S_GCR_TDLIS_SHIFT (3U) 548 #define PSI5_S_GCR_TDLIS_WIDTH (1U) 549 #define PSI5_S_GCR_TDLIS(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_GCR_TDLIS_SHIFT)) & PSI5_S_GCR_TDLIS_MASK) 550 551 #define PSI5_S_GCR_RDFBM_MASK (0x10U) 552 #define PSI5_S_GCR_RDFBM_SHIFT (4U) 553 #define PSI5_S_GCR_RDFBM_WIDTH (1U) 554 #define PSI5_S_GCR_RDFBM(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_GCR_RDFBM_SHIFT)) & PSI5_S_GCR_RDFBM_MASK) 555 556 #define PSI5_S_GCR_TDFBM_MASK (0x20U) 557 #define PSI5_S_GCR_TDFBM_SHIFT (5U) 558 #define PSI5_S_GCR_TDFBM_WIDTH (1U) 559 #define PSI5_S_GCR_TDFBM(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_GCR_TDFBM_SHIFT)) & PSI5_S_GCR_TDFBM_MASK) 560 /*! @} */ 561 562 /*! @name UARTPTO - PSI5_S UART Preset Timeout Register */ 563 /*! @{ */ 564 565 #define PSI5_S_UARTPTO_PTO_MASK (0xFFFU) 566 #define PSI5_S_UARTPTO_PTO_SHIFT (0U) 567 #define PSI5_S_UARTPTO_PTO_WIDTH (12U) 568 #define PSI5_S_UARTPTO_PTO(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_UARTPTO_PTO_SHIFT)) & PSI5_S_UARTPTO_PTO_MASK) 569 /*! @} */ 570 571 /*! @name UARTCTO - PSI5_S UART Current Timeout register */ 572 /*! @{ */ 573 574 #define PSI5_S_UARTCTO_CTO_MASK (0xFFFU) 575 #define PSI5_S_UARTCTO_CTO_SHIFT (0U) 576 #define PSI5_S_UARTCTO_CTO_WIDTH (12U) 577 #define PSI5_S_UARTCTO_CTO(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_UARTCTO_CTO_SHIFT)) & PSI5_S_UARTCTO_CTO_MASK) 578 /*! @} */ 579 580 /*! @name DMATXE - DMA Tx Enable Register */ 581 /*! @{ */ 582 583 #define PSI5_S_DMATXE_DTE0_MASK (0x1U) 584 #define PSI5_S_DMATXE_DTE0_SHIFT (0U) 585 #define PSI5_S_DMATXE_DTE0_WIDTH (1U) 586 #define PSI5_S_DMATXE_DTE0(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_DMATXE_DTE0_SHIFT)) & PSI5_S_DMATXE_DTE0_MASK) 587 /*! @} */ 588 589 /*! @name DMARXE - DMA Rx Enable Register */ 590 /*! @{ */ 591 592 #define PSI5_S_DMARXE_DRE0_MASK (0x1U) 593 #define PSI5_S_DMARXE_DRE0_SHIFT (0U) 594 #define PSI5_S_DMARXE_DRE0_WIDTH (1U) 595 #define PSI5_S_DMARXE_DRE0(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_DMARXE_DRE0_SHIFT)) & PSI5_S_DMARXE_DRE0_MASK) 596 /*! @} */ 597 598 /*! @name PTD - PSI5_S UART Tx Idle Delay Time Register */ 599 /*! @{ */ 600 601 #define PSI5_S_PTD_EN_MASK (0x1U) 602 #define PSI5_S_PTD_EN_SHIFT (0U) 603 #define PSI5_S_PTD_EN_WIDTH (1U) 604 #define PSI5_S_PTD_EN(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_PTD_EN_SHIFT)) & PSI5_S_PTD_EN_MASK) 605 606 #define PSI5_S_PTD_IFD_MASK (0x1EU) 607 #define PSI5_S_PTD_IFD_SHIFT (1U) 608 #define PSI5_S_PTD_IFD_WIDTH (4U) 609 #define PSI5_S_PTD_IFD(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_PTD_IFD_SHIFT)) & PSI5_S_PTD_IFD_MASK) 610 /*! @} */ 611 612 /*! @name GLCR - PSI5_S Global Control Register */ 613 /*! @{ */ 614 615 #define PSI5_S_GLCR_GLOBAL_MODE_MASK (0x7U) 616 #define PSI5_S_GLCR_GLOBAL_MODE_SHIFT (0U) 617 #define PSI5_S_GLCR_GLOBAL_MODE_WIDTH (3U) 618 #define PSI5_S_GLCR_GLOBAL_MODE(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_GLCR_GLOBAL_MODE_SHIFT)) & PSI5_S_GLCR_GLOBAL_MODE_MASK) 619 620 #define PSI5_S_GLCR_TSCNTEN_G_L_MASK (0x8U) 621 #define PSI5_S_GLCR_TSCNTEN_G_L_SHIFT (3U) 622 #define PSI5_S_GLCR_TSCNTEN_G_L_WIDTH (1U) 623 #define PSI5_S_GLCR_TSCNTEN_G_L(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_GLCR_TSCNTEN_G_L_SHIFT)) & PSI5_S_GLCR_TSCNTEN_G_L_MASK) 624 625 #define PSI5_S_GLCR_TSCNTEN_G_MASK (0x10U) 626 #define PSI5_S_GLCR_TSCNTEN_G_SHIFT (4U) 627 #define PSI5_S_GLCR_TSCNTEN_G_WIDTH (1U) 628 #define PSI5_S_GLCR_TSCNTEN_G(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_GLCR_TSCNTEN_G_SHIFT)) & PSI5_S_GLCR_TSCNTEN_G_MASK) 629 630 #define PSI5_S_GLCR_TSCNT_EN_A_MASK (0x20U) 631 #define PSI5_S_GLCR_TSCNT_EN_A_SHIFT (5U) 632 #define PSI5_S_GLCR_TSCNT_EN_A_WIDTH (1U) 633 #define PSI5_S_GLCR_TSCNT_EN_A(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_GLCR_TSCNT_EN_A_SHIFT)) & PSI5_S_GLCR_TSCNT_EN_A_MASK) 634 635 #define PSI5_S_GLCR_TSCNT_EN_B_MASK (0x40U) 636 #define PSI5_S_GLCR_TSCNT_EN_B_SHIFT (6U) 637 #define PSI5_S_GLCR_TSCNT_EN_B_WIDTH (1U) 638 #define PSI5_S_GLCR_TSCNT_EN_B(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_GLCR_TSCNT_EN_B_SHIFT)) & PSI5_S_GLCR_TSCNT_EN_B_MASK) 639 640 #define PSI5_S_GLCR_CLRTSCNT_G_L_MASK (0x80U) 641 #define PSI5_S_GLCR_CLRTSCNT_G_L_SHIFT (7U) 642 #define PSI5_S_GLCR_CLRTSCNT_G_L_WIDTH (1U) 643 #define PSI5_S_GLCR_CLRTSCNT_G_L(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_GLCR_CLRTSCNT_G_L_SHIFT)) & PSI5_S_GLCR_CLRTSCNT_G_L_MASK) 644 645 #define PSI5_S_GLCR_CLRTSCNT_G_MASK (0x100U) 646 #define PSI5_S_GLCR_CLRTSCNT_G_SHIFT (8U) 647 #define PSI5_S_GLCR_CLRTSCNT_G_WIDTH (1U) 648 #define PSI5_S_GLCR_CLRTSCNT_G(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_GLCR_CLRTSCNT_G_SHIFT)) & PSI5_S_GLCR_CLRTSCNT_G_MASK) 649 650 #define PSI5_S_GLCR_CLR_CNTR_A_MASK (0x200U) 651 #define PSI5_S_GLCR_CLR_CNTR_A_SHIFT (9U) 652 #define PSI5_S_GLCR_CLR_CNTR_A_WIDTH (1U) 653 #define PSI5_S_GLCR_CLR_CNTR_A(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_GLCR_CLR_CNTR_A_SHIFT)) & PSI5_S_GLCR_CLR_CNTR_A_MASK) 654 655 #define PSI5_S_GLCR_CLR_CNTR_B_MASK (0x400U) 656 #define PSI5_S_GLCR_CLR_CNTR_B_SHIFT (10U) 657 #define PSI5_S_GLCR_CLR_CNTR_B_WIDTH (1U) 658 #define PSI5_S_GLCR_CLR_CNTR_B(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_GLCR_CLR_CNTR_B_SHIFT)) & PSI5_S_GLCR_CLR_CNTR_B_MASK) 659 660 #define PSI5_S_GLCR_TSCS_A_MASK (0x800U) 661 #define PSI5_S_GLCR_TSCS_A_SHIFT (11U) 662 #define PSI5_S_GLCR_TSCS_A_WIDTH (1U) 663 #define PSI5_S_GLCR_TSCS_A(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_GLCR_TSCS_A_SHIFT)) & PSI5_S_GLCR_TSCS_A_MASK) 664 665 #define PSI5_S_GLCR_TSCS_B_MASK (0x1000U) 666 #define PSI5_S_GLCR_TSCS_B_SHIFT (12U) 667 #define PSI5_S_GLCR_TSCS_B_WIDTH (1U) 668 #define PSI5_S_GLCR_TSCS_B(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_GLCR_TSCS_B_SHIFT)) & PSI5_S_GLCR_TSCS_B_MASK) 669 670 #define PSI5_S_GLCR_MRU_ERR_EN_MASK (0x2000U) 671 #define PSI5_S_GLCR_MRU_ERR_EN_SHIFT (13U) 672 #define PSI5_S_GLCR_MRU_ERR_EN_WIDTH (1U) 673 #define PSI5_S_GLCR_MRU_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_GLCR_MRU_ERR_EN_SHIFT)) & PSI5_S_GLCR_MRU_ERR_EN_MASK) 674 675 #define PSI5_S_GLCR_GL_DDSR_TRIG_MASK (0x8000U) 676 #define PSI5_S_GLCR_GL_DDSR_TRIG_SHIFT (15U) 677 #define PSI5_S_GLCR_GL_DDSR_TRIG_WIDTH (1U) 678 #define PSI5_S_GLCR_GL_DDSR_TRIG(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_GLCR_GL_DDSR_TRIG_SHIFT)) & PSI5_S_GLCR_GL_DDSR_TRIG_MASK) 679 680 #define PSI5_S_GLCR_GTM_TRIG_SEL_MASK (0x30000U) 681 #define PSI5_S_GLCR_GTM_TRIG_SEL_SHIFT (16U) 682 #define PSI5_S_GLCR_GTM_TRIG_SEL_WIDTH (2U) 683 #define PSI5_S_GLCR_GTM_TRIG_SEL(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_GLCR_GTM_TRIG_SEL_SHIFT)) & PSI5_S_GLCR_GTM_TRIG_SEL_MASK) 684 685 #define PSI5_S_GLCR_DEBUG_EN_MASK (0x40000U) 686 #define PSI5_S_GLCR_DEBUG_EN_SHIFT (18U) 687 #define PSI5_S_GLCR_DEBUG_EN_WIDTH (1U) 688 #define PSI5_S_GLCR_DEBUG_EN(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_GLCR_DEBUG_EN_SHIFT)) & PSI5_S_GLCR_DEBUG_EN_MASK) 689 690 #define PSI5_S_GLCR_IE_DIRCMD_RDY_MASK (0x100000U) 691 #define PSI5_S_GLCR_IE_DIRCMD_RDY_SHIFT (20U) 692 #define PSI5_S_GLCR_IE_DIRCMD_RDY_WIDTH (1U) 693 #define PSI5_S_GLCR_IE_DIRCMD_RDY(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_GLCR_IE_DIRCMD_RDY_SHIFT)) & PSI5_S_GLCR_IE_DIRCMD_RDY_MASK) 694 695 #define PSI5_S_GLCR_DIRCMD_LEN_MASK (0xC00000U) 696 #define PSI5_S_GLCR_DIRCMD_LEN_SHIFT (22U) 697 #define PSI5_S_GLCR_DIRCMD_LEN_WIDTH (2U) 698 #define PSI5_S_GLCR_DIRCMD_LEN(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_GLCR_DIRCMD_LEN_SHIFT)) & PSI5_S_GLCR_DIRCMD_LEN_MASK) 699 /*! @} */ 700 701 /*! @name GLSR - PSI5_S Global Status Register */ 702 /*! @{ */ 703 704 #define PSI5_S_GLSR_CHID_MASK (0x7U) 705 #define PSI5_S_GLSR_CHID_SHIFT (0U) 706 #define PSI5_S_GLSR_CHID_WIDTH (3U) 707 #define PSI5_S_GLSR_CHID(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_GLSR_CHID_SHIFT)) & PSI5_S_GLSR_CHID_MASK) 708 709 #define PSI5_S_GLSR_FID_MASK (0x38U) 710 #define PSI5_S_GLSR_FID_SHIFT (3U) 711 #define PSI5_S_GLSR_FID_WIDTH (3U) 712 #define PSI5_S_GLSR_FID(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_GLSR_FID_SHIFT)) & PSI5_S_GLSR_FID_MASK) 713 714 #define PSI5_S_GLSR_MRU_ERR_MASK (0x2000U) 715 #define PSI5_S_GLSR_MRU_ERR_SHIFT (13U) 716 #define PSI5_S_GLSR_MRU_ERR_WIDTH (1U) 717 #define PSI5_S_GLSR_MRU_ERR(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_GLSR_MRU_ERR_SHIFT)) & PSI5_S_GLSR_MRU_ERR_MASK) 718 719 #define PSI5_S_GLSR_GL_MODETR_DONE_MASK (0x4000U) 720 #define PSI5_S_GLSR_GL_MODETR_DONE_SHIFT (14U) 721 #define PSI5_S_GLSR_GL_MODETR_DONE_WIDTH (1U) 722 #define PSI5_S_GLSR_GL_MODETR_DONE(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_GLSR_GL_MODETR_DONE_SHIFT)) & PSI5_S_GLSR_GL_MODETR_DONE_MASK) 723 724 #define PSI5_S_GLSR_DIRCMD_RDY_MASK (0x100000U) 725 #define PSI5_S_GLSR_DIRCMD_RDY_SHIFT (20U) 726 #define PSI5_S_GLSR_DIRCMD_RDY_WIDTH (1U) 727 #define PSI5_S_GLSR_DIRCMD_RDY(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_GLSR_DIRCMD_RDY_SHIFT)) & PSI5_S_GLSR_DIRCMD_RDY_MASK) 728 /*! @} */ 729 730 /*! @name CH_BASE_ADDR - PSI5_S CHANNEL_BASE_ADDRESS */ 731 /*! @{ */ 732 733 #define PSI5_S_CH_BASE_ADDR_MAILBOX_BASE_ADDR_MASK (0xFFFFFFFFU) 734 #define PSI5_S_CH_BASE_ADDR_MAILBOX_BASE_ADDR_SHIFT (0U) 735 #define PSI5_S_CH_BASE_ADDR_MAILBOX_BASE_ADDR_WIDTH (32U) 736 #define PSI5_S_CH_BASE_ADDR_MAILBOX_BASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_CH_BASE_ADDR_MAILBOX_BASE_ADDR_SHIFT)) & PSI5_S_CH_BASE_ADDR_MAILBOX_BASE_ADDR_MASK) 737 /*! @} */ 738 739 /*! @name MRU_BUF2_REG0 - PSI5_S MRU OUTPUT BUFFER2 REGISTER0 */ 740 /*! @{ */ 741 742 #define PSI5_S_MRU_BUF2_REG0_CHANNEL_SPECIFIC_MAILBOX_ADDR_MASK (0xFFFFFFFFU) 743 #define PSI5_S_MRU_BUF2_REG0_CHANNEL_SPECIFIC_MAILBOX_ADDR_SHIFT (0U) 744 #define PSI5_S_MRU_BUF2_REG0_CHANNEL_SPECIFIC_MAILBOX_ADDR_WIDTH (32U) 745 #define PSI5_S_MRU_BUF2_REG0_CHANNEL_SPECIFIC_MAILBOX_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_MRU_BUF2_REG0_CHANNEL_SPECIFIC_MAILBOX_ADDR_SHIFT)) & PSI5_S_MRU_BUF2_REG0_CHANNEL_SPECIFIC_MAILBOX_ADDR_MASK) 746 /*! @} */ 747 748 /*! @name MRU_BUF2_REG1 - PSI5_S MRU OUTPUT BUFFER2 REGISTER1 */ 749 /*! @{ */ 750 751 #define PSI5_S_MRU_BUF2_REG1_XCRC_MASK (0x3FU) 752 #define PSI5_S_MRU_BUF2_REG1_XCRC_SHIFT (0U) 753 #define PSI5_S_MRU_BUF2_REG1_XCRC_WIDTH (6U) 754 #define PSI5_S_MRU_BUF2_REG1_XCRC(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_MRU_BUF2_REG1_XCRC_SHIFT)) & PSI5_S_MRU_BUF2_REG1_XCRC_MASK) 755 756 #define PSI5_S_MRU_BUF2_REG1_XCRC_ERR_MASK (0x40U) 757 #define PSI5_S_MRU_BUF2_REG1_XCRC_ERR_SHIFT (6U) 758 #define PSI5_S_MRU_BUF2_REG1_XCRC_ERR_WIDTH (1U) 759 #define PSI5_S_MRU_BUF2_REG1_XCRC_ERR(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_MRU_BUF2_REG1_XCRC_ERR_SHIFT)) & PSI5_S_MRU_BUF2_REG1_XCRC_ERR_MASK) 760 761 #define PSI5_S_MRU_BUF2_REG1_CRC_MASK (0x380U) 762 #define PSI5_S_MRU_BUF2_REG1_CRC_SHIFT (7U) 763 #define PSI5_S_MRU_BUF2_REG1_CRC_WIDTH (3U) 764 #define PSI5_S_MRU_BUF2_REG1_CRC(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_MRU_BUF2_REG1_CRC_SHIFT)) & PSI5_S_MRU_BUF2_REG1_CRC_MASK) 765 766 #define PSI5_S_MRU_BUF2_REG1_CRC_ERR_P_ERR_MASK (0x400U) 767 #define PSI5_S_MRU_BUF2_REG1_CRC_ERR_P_ERR_SHIFT (10U) 768 #define PSI5_S_MRU_BUF2_REG1_CRC_ERR_P_ERR_WIDTH (1U) 769 #define PSI5_S_MRU_BUF2_REG1_CRC_ERR_P_ERR(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_MRU_BUF2_REG1_CRC_ERR_P_ERR_SHIFT)) & PSI5_S_MRU_BUF2_REG1_CRC_ERR_P_ERR_MASK) 770 771 #define PSI5_S_MRU_BUF2_REG1_ERR_MASK (0x1800U) 772 #define PSI5_S_MRU_BUF2_REG1_ERR_SHIFT (11U) 773 #define PSI5_S_MRU_BUF2_REG1_ERR_WIDTH (2U) 774 #define PSI5_S_MRU_BUF2_REG1_ERR(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_MRU_BUF2_REG1_ERR_SHIFT)) & PSI5_S_MRU_BUF2_REG1_ERR_MASK) 775 776 #define PSI5_S_MRU_BUF2_REG1_HD_ERR_MASK (0x2000U) 777 #define PSI5_S_MRU_BUF2_REG1_HD_ERR_SHIFT (13U) 778 #define PSI5_S_MRU_BUF2_REG1_HD_ERR_WIDTH (1U) 779 #define PSI5_S_MRU_BUF2_REG1_HD_ERR(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_MRU_BUF2_REG1_HD_ERR_SHIFT)) & PSI5_S_MRU_BUF2_REG1_HD_ERR_MASK) 780 781 #define PSI5_S_MRU_BUF2_REG1_SCI_P_ERR_MASK (0x4000U) 782 #define PSI5_S_MRU_BUF2_REG1_SCI_P_ERR_SHIFT (14U) 783 #define PSI5_S_MRU_BUF2_REG1_SCI_P_ERR_WIDTH (1U) 784 #define PSI5_S_MRU_BUF2_REG1_SCI_P_ERR(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_MRU_BUF2_REG1_SCI_P_ERR_SHIFT)) & PSI5_S_MRU_BUF2_REG1_SCI_P_ERR_MASK) 785 786 #define PSI5_S_MRU_BUF2_REG1_SCI_F_ERR_MASK (0x8000U) 787 #define PSI5_S_MRU_BUF2_REG1_SCI_F_ERR_SHIFT (15U) 788 #define PSI5_S_MRU_BUF2_REG1_SCI_F_ERR_WIDTH (1U) 789 #define PSI5_S_MRU_BUF2_REG1_SCI_F_ERR(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_MRU_BUF2_REG1_SCI_F_ERR_SHIFT)) & PSI5_S_MRU_BUF2_REG1_SCI_F_ERR_MASK) 790 791 #define PSI5_S_MRU_BUF2_REG1_SCI_O_ERR_MASK (0x10000U) 792 #define PSI5_S_MRU_BUF2_REG1_SCI_O_ERR_SHIFT (16U) 793 #define PSI5_S_MRU_BUF2_REG1_SCI_O_ERR_WIDTH (1U) 794 #define PSI5_S_MRU_BUF2_REG1_SCI_O_ERR(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_MRU_BUF2_REG1_SCI_O_ERR_SHIFT)) & PSI5_S_MRU_BUF2_REG1_SCI_O_ERR_MASK) 795 796 #define PSI5_S_MRU_BUF2_REG1_F_WD_ERR_MASK (0x20000U) 797 #define PSI5_S_MRU_BUF2_REG1_F_WD_ERR_SHIFT (17U) 798 #define PSI5_S_MRU_BUF2_REG1_F_WD_ERR_WIDTH (1U) 799 #define PSI5_S_MRU_BUF2_REG1_F_WD_ERR(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_MRU_BUF2_REG1_F_WD_ERR_SHIFT)) & PSI5_S_MRU_BUF2_REG1_F_WD_ERR_MASK) 800 801 #define PSI5_S_MRU_BUF2_REG1_R_OVL_ERR_MASK (0x40000U) 802 #define PSI5_S_MRU_BUF2_REG1_R_OVL_ERR_SHIFT (18U) 803 #define PSI5_S_MRU_BUF2_REG1_R_OVL_ERR_WIDTH (1U) 804 #define PSI5_S_MRU_BUF2_REG1_R_OVL_ERR(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_MRU_BUF2_REG1_R_OVL_ERR_SHIFT)) & PSI5_S_MRU_BUF2_REG1_R_OVL_ERR_MASK) 805 806 #define PSI5_S_MRU_BUF2_REG1_FID_MASK (0x380000U) 807 #define PSI5_S_MRU_BUF2_REG1_FID_SHIFT (19U) 808 #define PSI5_S_MRU_BUF2_REG1_FID_WIDTH (3U) 809 #define PSI5_S_MRU_BUF2_REG1_FID(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_MRU_BUF2_REG1_FID_SHIFT)) & PSI5_S_MRU_BUF2_REG1_FID_MASK) 810 811 #define PSI5_S_MRU_BUF2_REG1_CHID_MASK (0x1C00000U) 812 #define PSI5_S_MRU_BUF2_REG1_CHID_SHIFT (22U) 813 #define PSI5_S_MRU_BUF2_REG1_CHID_WIDTH (3U) 814 #define PSI5_S_MRU_BUF2_REG1_CHID(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_MRU_BUF2_REG1_CHID_SHIFT)) & PSI5_S_MRU_BUF2_REG1_CHID_MASK) 815 816 #define PSI5_S_MRU_BUF2_REG1_N_ERR_MASK (0x2000000U) 817 #define PSI5_S_MRU_BUF2_REG1_N_ERR_SHIFT (25U) 818 #define PSI5_S_MRU_BUF2_REG1_N_ERR_WIDTH (1U) 819 #define PSI5_S_MRU_BUF2_REG1_N_ERR(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_MRU_BUF2_REG1_N_ERR_SHIFT)) & PSI5_S_MRU_BUF2_REG1_N_ERR_MASK) 820 821 #define PSI5_S_MRU_BUF2_REG1_R_UVL_ERR_MASK (0x4000000U) 822 #define PSI5_S_MRU_BUF2_REG1_R_UVL_ERR_SHIFT (26U) 823 #define PSI5_S_MRU_BUF2_REG1_R_UVL_ERR_WIDTH (1U) 824 #define PSI5_S_MRU_BUF2_REG1_R_UVL_ERR(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_MRU_BUF2_REG1_R_UVL_ERR_SHIFT)) & PSI5_S_MRU_BUF2_REG1_R_UVL_ERR_MASK) 825 826 #define PSI5_S_MRU_BUF2_REG1_DCI_MASK (0xF0000000U) 827 #define PSI5_S_MRU_BUF2_REG1_DCI_SHIFT (28U) 828 #define PSI5_S_MRU_BUF2_REG1_DCI_WIDTH (4U) 829 #define PSI5_S_MRU_BUF2_REG1_DCI(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_MRU_BUF2_REG1_DCI_SHIFT)) & PSI5_S_MRU_BUF2_REG1_DCI_MASK) 830 /*! @} */ 831 832 /*! @name MRU_BUF2_REG2 - PSI5_S MRU OUTPUT BUFFER2 REGISTER2 */ 833 /*! @{ */ 834 835 #define PSI5_S_MRU_BUF2_REG2_PS_DATA_MASK (0xFFFFFFFU) 836 #define PSI5_S_MRU_BUF2_REG2_PS_DATA_SHIFT (0U) 837 #define PSI5_S_MRU_BUF2_REG2_PS_DATA_WIDTH (28U) 838 #define PSI5_S_MRU_BUF2_REG2_PS_DATA(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_MRU_BUF2_REG2_PS_DATA_SHIFT)) & PSI5_S_MRU_BUF2_REG2_PS_DATA_MASK) 839 840 #define PSI5_S_MRU_BUF2_REG2_DCI_MASK (0xF0000000U) 841 #define PSI5_S_MRU_BUF2_REG2_DCI_SHIFT (28U) 842 #define PSI5_S_MRU_BUF2_REG2_DCI_WIDTH (4U) 843 #define PSI5_S_MRU_BUF2_REG2_DCI(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_MRU_BUF2_REG2_DCI_SHIFT)) & PSI5_S_MRU_BUF2_REG2_DCI_MASK) 844 /*! @} */ 845 846 /*! @name MRU_BUF2_REG3 - PSI5_S MRU OUTPUT BUFFER2 REGISTER3 */ 847 /*! @{ */ 848 849 #define PSI5_S_MRU_BUF2_REG3_TIMESTAMP_MASK (0xFFFFFFU) 850 #define PSI5_S_MRU_BUF2_REG3_TIMESTAMP_SHIFT (0U) 851 #define PSI5_S_MRU_BUF2_REG3_TIMESTAMP_WIDTH (24U) 852 #define PSI5_S_MRU_BUF2_REG3_TIMESTAMP(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_MRU_BUF2_REG3_TIMESTAMP_SHIFT)) & PSI5_S_MRU_BUF2_REG3_TIMESTAMP_MASK) 853 854 #define PSI5_S_MRU_BUF2_REG3_DCI_MASK (0xF0000000U) 855 #define PSI5_S_MRU_BUF2_REG3_DCI_SHIFT (28U) 856 #define PSI5_S_MRU_BUF2_REG3_DCI_WIDTH (4U) 857 #define PSI5_S_MRU_BUF2_REG3_DCI(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_MRU_BUF2_REG3_DCI_SHIFT)) & PSI5_S_MRU_BUF2_REG3_DCI_MASK) 858 /*! @} */ 859 860 /*! @name MBOX_SR_IRQ - PSI5_S Mbox Status Irq */ 861 /*! @{ */ 862 863 #define PSI5_S_MBOX_SR_IRQ_MBOX_CH0_MASK (0x1U) 864 #define PSI5_S_MBOX_SR_IRQ_MBOX_CH0_SHIFT (0U) 865 #define PSI5_S_MBOX_SR_IRQ_MBOX_CH0_WIDTH (1U) 866 #define PSI5_S_MBOX_SR_IRQ_MBOX_CH0(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_MBOX_SR_IRQ_MBOX_CH0_SHIFT)) & PSI5_S_MBOX_SR_IRQ_MBOX_CH0_MASK) 867 868 #define PSI5_S_MBOX_SR_IRQ_MBOX_CH1_MASK (0x2U) 869 #define PSI5_S_MBOX_SR_IRQ_MBOX_CH1_SHIFT (1U) 870 #define PSI5_S_MBOX_SR_IRQ_MBOX_CH1_WIDTH (1U) 871 #define PSI5_S_MBOX_SR_IRQ_MBOX_CH1(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_MBOX_SR_IRQ_MBOX_CH1_SHIFT)) & PSI5_S_MBOX_SR_IRQ_MBOX_CH1_MASK) 872 873 #define PSI5_S_MBOX_SR_IRQ_MBOX_CH2_MASK (0x4U) 874 #define PSI5_S_MBOX_SR_IRQ_MBOX_CH2_SHIFT (2U) 875 #define PSI5_S_MBOX_SR_IRQ_MBOX_CH2_WIDTH (1U) 876 #define PSI5_S_MBOX_SR_IRQ_MBOX_CH2(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_MBOX_SR_IRQ_MBOX_CH2_SHIFT)) & PSI5_S_MBOX_SR_IRQ_MBOX_CH2_MASK) 877 878 #define PSI5_S_MBOX_SR_IRQ_MBOX_CH3_MASK (0x8U) 879 #define PSI5_S_MBOX_SR_IRQ_MBOX_CH3_SHIFT (3U) 880 #define PSI5_S_MBOX_SR_IRQ_MBOX_CH3_WIDTH (1U) 881 #define PSI5_S_MBOX_SR_IRQ_MBOX_CH3(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_MBOX_SR_IRQ_MBOX_CH3_SHIFT)) & PSI5_S_MBOX_SR_IRQ_MBOX_CH3_MASK) 882 883 #define PSI5_S_MBOX_SR_IRQ_MBOX_CH4_MASK (0x10U) 884 #define PSI5_S_MBOX_SR_IRQ_MBOX_CH4_SHIFT (4U) 885 #define PSI5_S_MBOX_SR_IRQ_MBOX_CH4_WIDTH (1U) 886 #define PSI5_S_MBOX_SR_IRQ_MBOX_CH4(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_MBOX_SR_IRQ_MBOX_CH4_SHIFT)) & PSI5_S_MBOX_SR_IRQ_MBOX_CH4_MASK) 887 888 #define PSI5_S_MBOX_SR_IRQ_MBOX_CH5_MASK (0x20U) 889 #define PSI5_S_MBOX_SR_IRQ_MBOX_CH5_SHIFT (5U) 890 #define PSI5_S_MBOX_SR_IRQ_MBOX_CH5_WIDTH (1U) 891 #define PSI5_S_MBOX_SR_IRQ_MBOX_CH5(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_MBOX_SR_IRQ_MBOX_CH5_SHIFT)) & PSI5_S_MBOX_SR_IRQ_MBOX_CH5_MASK) 892 893 #define PSI5_S_MBOX_SR_IRQ_MBOX_CH6_MASK (0x40U) 894 #define PSI5_S_MBOX_SR_IRQ_MBOX_CH6_SHIFT (6U) 895 #define PSI5_S_MBOX_SR_IRQ_MBOX_CH6_WIDTH (1U) 896 #define PSI5_S_MBOX_SR_IRQ_MBOX_CH6(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_MBOX_SR_IRQ_MBOX_CH6_SHIFT)) & PSI5_S_MBOX_SR_IRQ_MBOX_CH6_MASK) 897 898 #define PSI5_S_MBOX_SR_IRQ_MBOX_CH7_MASK (0x80U) 899 #define PSI5_S_MBOX_SR_IRQ_MBOX_CH7_SHIFT (7U) 900 #define PSI5_S_MBOX_SR_IRQ_MBOX_CH7_WIDTH (1U) 901 #define PSI5_S_MBOX_SR_IRQ_MBOX_CH7(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_MBOX_SR_IRQ_MBOX_CH7_SHIFT)) & PSI5_S_MBOX_SR_IRQ_MBOX_CH7_MASK) 902 /*! @} */ 903 904 /*! @name ERR_SR_IRQ - PSI5_S Error Status IRQ */ 905 /*! @{ */ 906 907 #define PSI5_S_ERR_SR_IRQ_XCRC_ERR_MASK (0x1U) 908 #define PSI5_S_ERR_SR_IRQ_XCRC_ERR_SHIFT (0U) 909 #define PSI5_S_ERR_SR_IRQ_XCRC_ERR_WIDTH (1U) 910 #define PSI5_S_ERR_SR_IRQ_XCRC_ERR(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_ERR_SR_IRQ_XCRC_ERR_SHIFT)) & PSI5_S_ERR_SR_IRQ_XCRC_ERR_MASK) 911 912 #define PSI5_S_ERR_SR_IRQ_CRC_ERR_P_ERR_MASK (0x2U) 913 #define PSI5_S_ERR_SR_IRQ_CRC_ERR_P_ERR_SHIFT (1U) 914 #define PSI5_S_ERR_SR_IRQ_CRC_ERR_P_ERR_WIDTH (1U) 915 #define PSI5_S_ERR_SR_IRQ_CRC_ERR_P_ERR(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_ERR_SR_IRQ_CRC_ERR_P_ERR_SHIFT)) & PSI5_S_ERR_SR_IRQ_CRC_ERR_P_ERR_MASK) 916 917 #define PSI5_S_ERR_SR_IRQ_HD_ERR_MASK (0x4U) 918 #define PSI5_S_ERR_SR_IRQ_HD_ERR_SHIFT (2U) 919 #define PSI5_S_ERR_SR_IRQ_HD_ERR_WIDTH (1U) 920 #define PSI5_S_ERR_SR_IRQ_HD_ERR(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_ERR_SR_IRQ_HD_ERR_SHIFT)) & PSI5_S_ERR_SR_IRQ_HD_ERR_MASK) 921 922 #define PSI5_S_ERR_SR_IRQ_SCI_P_ERR_MASK (0x8U) 923 #define PSI5_S_ERR_SR_IRQ_SCI_P_ERR_SHIFT (3U) 924 #define PSI5_S_ERR_SR_IRQ_SCI_P_ERR_WIDTH (1U) 925 #define PSI5_S_ERR_SR_IRQ_SCI_P_ERR(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_ERR_SR_IRQ_SCI_P_ERR_SHIFT)) & PSI5_S_ERR_SR_IRQ_SCI_P_ERR_MASK) 926 927 #define PSI5_S_ERR_SR_IRQ_SCI_F_ERR_MASK (0x10U) 928 #define PSI5_S_ERR_SR_IRQ_SCI_F_ERR_SHIFT (4U) 929 #define PSI5_S_ERR_SR_IRQ_SCI_F_ERR_WIDTH (1U) 930 #define PSI5_S_ERR_SR_IRQ_SCI_F_ERR(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_ERR_SR_IRQ_SCI_F_ERR_SHIFT)) & PSI5_S_ERR_SR_IRQ_SCI_F_ERR_MASK) 931 932 #define PSI5_S_ERR_SR_IRQ_SCI_O_ERR_MASK (0x20U) 933 #define PSI5_S_ERR_SR_IRQ_SCI_O_ERR_SHIFT (5U) 934 #define PSI5_S_ERR_SR_IRQ_SCI_O_ERR_WIDTH (1U) 935 #define PSI5_S_ERR_SR_IRQ_SCI_O_ERR(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_ERR_SR_IRQ_SCI_O_ERR_SHIFT)) & PSI5_S_ERR_SR_IRQ_SCI_O_ERR_MASK) 936 937 #define PSI5_S_ERR_SR_IRQ_F_WD_ERR_MASK (0x40U) 938 #define PSI5_S_ERR_SR_IRQ_F_WD_ERR_SHIFT (6U) 939 #define PSI5_S_ERR_SR_IRQ_F_WD_ERR_WIDTH (1U) 940 #define PSI5_S_ERR_SR_IRQ_F_WD_ERR(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_ERR_SR_IRQ_F_WD_ERR_SHIFT)) & PSI5_S_ERR_SR_IRQ_F_WD_ERR_MASK) 941 942 #define PSI5_S_ERR_SR_IRQ_R_OVL_ERR_MASK (0x80U) 943 #define PSI5_S_ERR_SR_IRQ_R_OVL_ERR_SHIFT (7U) 944 #define PSI5_S_ERR_SR_IRQ_R_OVL_ERR_WIDTH (1U) 945 #define PSI5_S_ERR_SR_IRQ_R_OVL_ERR(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_ERR_SR_IRQ_R_OVL_ERR_SHIFT)) & PSI5_S_ERR_SR_IRQ_R_OVL_ERR_MASK) 946 947 #define PSI5_S_ERR_SR_IRQ_N_ERR_MASK (0x100U) 948 #define PSI5_S_ERR_SR_IRQ_N_ERR_SHIFT (8U) 949 #define PSI5_S_ERR_SR_IRQ_N_ERR_WIDTH (1U) 950 #define PSI5_S_ERR_SR_IRQ_N_ERR(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_ERR_SR_IRQ_N_ERR_SHIFT)) & PSI5_S_ERR_SR_IRQ_N_ERR_MASK) 951 952 #define PSI5_S_ERR_SR_IRQ_R_UVL_ERR_MASK (0x200U) 953 #define PSI5_S_ERR_SR_IRQ_R_UVL_ERR_SHIFT (9U) 954 #define PSI5_S_ERR_SR_IRQ_R_UVL_ERR_WIDTH (1U) 955 #define PSI5_S_ERR_SR_IRQ_R_UVL_ERR(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_ERR_SR_IRQ_R_UVL_ERR_SHIFT)) & PSI5_S_ERR_SR_IRQ_R_UVL_ERR_MASK) 956 /*! @} */ 957 958 /*! @name MBOX_SEL_IRQ - PSI5_S Mailbox select IRQ[irq_n] */ 959 /*! @{ */ 960 961 #define PSI5_S_MBOX_SEL_IRQ_MBOX_CH0_SEL_MASK (0x1U) 962 #define PSI5_S_MBOX_SEL_IRQ_MBOX_CH0_SEL_SHIFT (0U) 963 #define PSI5_S_MBOX_SEL_IRQ_MBOX_CH0_SEL_WIDTH (1U) 964 #define PSI5_S_MBOX_SEL_IRQ_MBOX_CH0_SEL(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_MBOX_SEL_IRQ_MBOX_CH0_SEL_SHIFT)) & PSI5_S_MBOX_SEL_IRQ_MBOX_CH0_SEL_MASK) 965 966 #define PSI5_S_MBOX_SEL_IRQ_MBOX_CH1_SEL_MASK (0x2U) 967 #define PSI5_S_MBOX_SEL_IRQ_MBOX_CH1_SEL_SHIFT (1U) 968 #define PSI5_S_MBOX_SEL_IRQ_MBOX_CH1_SEL_WIDTH (1U) 969 #define PSI5_S_MBOX_SEL_IRQ_MBOX_CH1_SEL(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_MBOX_SEL_IRQ_MBOX_CH1_SEL_SHIFT)) & PSI5_S_MBOX_SEL_IRQ_MBOX_CH1_SEL_MASK) 970 971 #define PSI5_S_MBOX_SEL_IRQ_MBOX_CH2_SEL_MASK (0x4U) 972 #define PSI5_S_MBOX_SEL_IRQ_MBOX_CH2_SEL_SHIFT (2U) 973 #define PSI5_S_MBOX_SEL_IRQ_MBOX_CH2_SEL_WIDTH (1U) 974 #define PSI5_S_MBOX_SEL_IRQ_MBOX_CH2_SEL(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_MBOX_SEL_IRQ_MBOX_CH2_SEL_SHIFT)) & PSI5_S_MBOX_SEL_IRQ_MBOX_CH2_SEL_MASK) 975 976 #define PSI5_S_MBOX_SEL_IRQ_MBOX_CH3_SEL_MASK (0x8U) 977 #define PSI5_S_MBOX_SEL_IRQ_MBOX_CH3_SEL_SHIFT (3U) 978 #define PSI5_S_MBOX_SEL_IRQ_MBOX_CH3_SEL_WIDTH (1U) 979 #define PSI5_S_MBOX_SEL_IRQ_MBOX_CH3_SEL(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_MBOX_SEL_IRQ_MBOX_CH3_SEL_SHIFT)) & PSI5_S_MBOX_SEL_IRQ_MBOX_CH3_SEL_MASK) 980 981 #define PSI5_S_MBOX_SEL_IRQ_MBOX_CH4_SEL_MASK (0x10U) 982 #define PSI5_S_MBOX_SEL_IRQ_MBOX_CH4_SEL_SHIFT (4U) 983 #define PSI5_S_MBOX_SEL_IRQ_MBOX_CH4_SEL_WIDTH (1U) 984 #define PSI5_S_MBOX_SEL_IRQ_MBOX_CH4_SEL(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_MBOX_SEL_IRQ_MBOX_CH4_SEL_SHIFT)) & PSI5_S_MBOX_SEL_IRQ_MBOX_CH4_SEL_MASK) 985 986 #define PSI5_S_MBOX_SEL_IRQ_MBOX_CH5_SEL_MASK (0x20U) 987 #define PSI5_S_MBOX_SEL_IRQ_MBOX_CH5_SEL_SHIFT (5U) 988 #define PSI5_S_MBOX_SEL_IRQ_MBOX_CH5_SEL_WIDTH (1U) 989 #define PSI5_S_MBOX_SEL_IRQ_MBOX_CH5_SEL(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_MBOX_SEL_IRQ_MBOX_CH5_SEL_SHIFT)) & PSI5_S_MBOX_SEL_IRQ_MBOX_CH5_SEL_MASK) 990 991 #define PSI5_S_MBOX_SEL_IRQ_MBOX_CH6_SEL_MASK (0x40U) 992 #define PSI5_S_MBOX_SEL_IRQ_MBOX_CH6_SEL_SHIFT (6U) 993 #define PSI5_S_MBOX_SEL_IRQ_MBOX_CH6_SEL_WIDTH (1U) 994 #define PSI5_S_MBOX_SEL_IRQ_MBOX_CH6_SEL(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_MBOX_SEL_IRQ_MBOX_CH6_SEL_SHIFT)) & PSI5_S_MBOX_SEL_IRQ_MBOX_CH6_SEL_MASK) 995 996 #define PSI5_S_MBOX_SEL_IRQ_MBOX_CH7_SEL_MASK (0x80U) 997 #define PSI5_S_MBOX_SEL_IRQ_MBOX_CH7_SEL_SHIFT (7U) 998 #define PSI5_S_MBOX_SEL_IRQ_MBOX_CH7_SEL_WIDTH (1U) 999 #define PSI5_S_MBOX_SEL_IRQ_MBOX_CH7_SEL(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_MBOX_SEL_IRQ_MBOX_CH7_SEL_SHIFT)) & PSI5_S_MBOX_SEL_IRQ_MBOX_CH7_SEL_MASK) 1000 /*! @} */ 1001 1002 /*! @name ERR_SEL_IRQ - PSI5_S Error Select IRQ[irq_n] */ 1003 /*! @{ */ 1004 1005 #define PSI5_S_ERR_SEL_IRQ_XCRC_ERR_SEL_MASK (0x1U) 1006 #define PSI5_S_ERR_SEL_IRQ_XCRC_ERR_SEL_SHIFT (0U) 1007 #define PSI5_S_ERR_SEL_IRQ_XCRC_ERR_SEL_WIDTH (1U) 1008 #define PSI5_S_ERR_SEL_IRQ_XCRC_ERR_SEL(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_ERR_SEL_IRQ_XCRC_ERR_SEL_SHIFT)) & PSI5_S_ERR_SEL_IRQ_XCRC_ERR_SEL_MASK) 1009 1010 #define PSI5_S_ERR_SEL_IRQ_CRC_ERR_SEL_MASK (0x2U) 1011 #define PSI5_S_ERR_SEL_IRQ_CRC_ERR_SEL_SHIFT (1U) 1012 #define PSI5_S_ERR_SEL_IRQ_CRC_ERR_SEL_WIDTH (1U) 1013 #define PSI5_S_ERR_SEL_IRQ_CRC_ERR_SEL(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_ERR_SEL_IRQ_CRC_ERR_SEL_SHIFT)) & PSI5_S_ERR_SEL_IRQ_CRC_ERR_SEL_MASK) 1014 1015 #define PSI5_S_ERR_SEL_IRQ_HD_ERR_SEL_MASK (0x4U) 1016 #define PSI5_S_ERR_SEL_IRQ_HD_ERR_SEL_SHIFT (2U) 1017 #define PSI5_S_ERR_SEL_IRQ_HD_ERR_SEL_WIDTH (1U) 1018 #define PSI5_S_ERR_SEL_IRQ_HD_ERR_SEL(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_ERR_SEL_IRQ_HD_ERR_SEL_SHIFT)) & PSI5_S_ERR_SEL_IRQ_HD_ERR_SEL_MASK) 1019 1020 #define PSI5_S_ERR_SEL_IRQ_SCI_P_ERR_SEL_MASK (0x8U) 1021 #define PSI5_S_ERR_SEL_IRQ_SCI_P_ERR_SEL_SHIFT (3U) 1022 #define PSI5_S_ERR_SEL_IRQ_SCI_P_ERR_SEL_WIDTH (1U) 1023 #define PSI5_S_ERR_SEL_IRQ_SCI_P_ERR_SEL(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_ERR_SEL_IRQ_SCI_P_ERR_SEL_SHIFT)) & PSI5_S_ERR_SEL_IRQ_SCI_P_ERR_SEL_MASK) 1024 1025 #define PSI5_S_ERR_SEL_IRQ_SCI_F_ERR_SEL_MASK (0x10U) 1026 #define PSI5_S_ERR_SEL_IRQ_SCI_F_ERR_SEL_SHIFT (4U) 1027 #define PSI5_S_ERR_SEL_IRQ_SCI_F_ERR_SEL_WIDTH (1U) 1028 #define PSI5_S_ERR_SEL_IRQ_SCI_F_ERR_SEL(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_ERR_SEL_IRQ_SCI_F_ERR_SEL_SHIFT)) & PSI5_S_ERR_SEL_IRQ_SCI_F_ERR_SEL_MASK) 1029 1030 #define PSI5_S_ERR_SEL_IRQ_SCI_O_ERR_SEL_MASK (0x20U) 1031 #define PSI5_S_ERR_SEL_IRQ_SCI_O_ERR_SEL_SHIFT (5U) 1032 #define PSI5_S_ERR_SEL_IRQ_SCI_O_ERR_SEL_WIDTH (1U) 1033 #define PSI5_S_ERR_SEL_IRQ_SCI_O_ERR_SEL(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_ERR_SEL_IRQ_SCI_O_ERR_SEL_SHIFT)) & PSI5_S_ERR_SEL_IRQ_SCI_O_ERR_SEL_MASK) 1034 1035 #define PSI5_S_ERR_SEL_IRQ_F_WD_ERR_SEL_MASK (0x40U) 1036 #define PSI5_S_ERR_SEL_IRQ_F_WD_ERR_SEL_SHIFT (6U) 1037 #define PSI5_S_ERR_SEL_IRQ_F_WD_ERR_SEL_WIDTH (1U) 1038 #define PSI5_S_ERR_SEL_IRQ_F_WD_ERR_SEL(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_ERR_SEL_IRQ_F_WD_ERR_SEL_SHIFT)) & PSI5_S_ERR_SEL_IRQ_F_WD_ERR_SEL_MASK) 1039 1040 #define PSI5_S_ERR_SEL_IRQ_R_OVL_ERR_SEL_MASK (0x80U) 1041 #define PSI5_S_ERR_SEL_IRQ_R_OVL_ERR_SEL_SHIFT (7U) 1042 #define PSI5_S_ERR_SEL_IRQ_R_OVL_ERR_SEL_WIDTH (1U) 1043 #define PSI5_S_ERR_SEL_IRQ_R_OVL_ERR_SEL(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_ERR_SEL_IRQ_R_OVL_ERR_SEL_SHIFT)) & PSI5_S_ERR_SEL_IRQ_R_OVL_ERR_SEL_MASK) 1044 1045 #define PSI5_S_ERR_SEL_IRQ_N_ERR_SEL_MASK (0x100U) 1046 #define PSI5_S_ERR_SEL_IRQ_N_ERR_SEL_SHIFT (8U) 1047 #define PSI5_S_ERR_SEL_IRQ_N_ERR_SEL_WIDTH (1U) 1048 #define PSI5_S_ERR_SEL_IRQ_N_ERR_SEL(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_ERR_SEL_IRQ_N_ERR_SEL_SHIFT)) & PSI5_S_ERR_SEL_IRQ_N_ERR_SEL_MASK) 1049 1050 #define PSI5_S_ERR_SEL_IRQ_R_UVL_ERR_SEL_MASK (0x200U) 1051 #define PSI5_S_ERR_SEL_IRQ_R_UVL_ERR_SEL_SHIFT (9U) 1052 #define PSI5_S_ERR_SEL_IRQ_R_UVL_ERR_SEL_WIDTH (1U) 1053 #define PSI5_S_ERR_SEL_IRQ_R_UVL_ERR_SEL(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_ERR_SEL_IRQ_R_UVL_ERR_SEL_SHIFT)) & PSI5_S_ERR_SEL_IRQ_R_UVL_ERR_SEL_MASK) 1054 /*! @} */ 1055 1056 /*! @name WDGTSSR - PSI5_S Watchdog Error Status and Watchdog Timestamp status register */ 1057 /*! @{ */ 1058 1059 #define PSI5_S_WDGTSSR_WDTS_STATUS_MASK (0xFFFFFFU) 1060 #define PSI5_S_WDGTSSR_WDTS_STATUS_SHIFT (0U) 1061 #define PSI5_S_WDGTSSR_WDTS_STATUS_WIDTH (24U) 1062 #define PSI5_S_WDGTSSR_WDTS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_WDGTSSR_WDTS_STATUS_SHIFT)) & PSI5_S_WDGTSSR_WDTS_STATUS_MASK) 1063 1064 #define PSI5_S_WDGTSSR_F_WD_ERR_STATUS_MASK (0xFE000000U) 1065 #define PSI5_S_WDGTSSR_F_WD_ERR_STATUS_SHIFT (25U) 1066 #define PSI5_S_WDGTSSR_F_WD_ERR_STATUS_WIDTH (7U) 1067 #define PSI5_S_WDGTSSR_F_WD_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_WDGTSSR_F_WD_ERR_STATUS_SHIFT)) & PSI5_S_WDGTSSR_F_WD_ERR_STATUS_MASK) 1068 /*! @} */ 1069 1070 /*! @name DIRCMD - PSI5_S ECU to Sensor Direct Command Write register */ 1071 /*! @{ */ 1072 1073 #define PSI5_S_DIRCMD_DIRCMD_BYTE0_MASK (0xFFU) 1074 #define PSI5_S_DIRCMD_DIRCMD_BYTE0_SHIFT (0U) 1075 #define PSI5_S_DIRCMD_DIRCMD_BYTE0_WIDTH (8U) 1076 #define PSI5_S_DIRCMD_DIRCMD_BYTE0(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_DIRCMD_DIRCMD_BYTE0_SHIFT)) & PSI5_S_DIRCMD_DIRCMD_BYTE0_MASK) 1077 1078 #define PSI5_S_DIRCMD_DIRCMD_BYTE1_MASK (0xFF00U) 1079 #define PSI5_S_DIRCMD_DIRCMD_BYTE1_SHIFT (8U) 1080 #define PSI5_S_DIRCMD_DIRCMD_BYTE1_WIDTH (8U) 1081 #define PSI5_S_DIRCMD_DIRCMD_BYTE1(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_DIRCMD_DIRCMD_BYTE1_SHIFT)) & PSI5_S_DIRCMD_DIRCMD_BYTE1_MASK) 1082 1083 #define PSI5_S_DIRCMD_DIRCMD_BYTE2_MASK (0xFF0000U) 1084 #define PSI5_S_DIRCMD_DIRCMD_BYTE2_SHIFT (16U) 1085 #define PSI5_S_DIRCMD_DIRCMD_BYTE2_WIDTH (8U) 1086 #define PSI5_S_DIRCMD_DIRCMD_BYTE2(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_DIRCMD_DIRCMD_BYTE2_SHIFT)) & PSI5_S_DIRCMD_DIRCMD_BYTE2_MASK) 1087 1088 #define PSI5_S_DIRCMD_DIRCMD_BYTE3_MASK (0xFF000000U) 1089 #define PSI5_S_DIRCMD_DIRCMD_BYTE3_SHIFT (24U) 1090 #define PSI5_S_DIRCMD_DIRCMD_BYTE3_WIDTH (8U) 1091 #define PSI5_S_DIRCMD_DIRCMD_BYTE3(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_DIRCMD_DIRCMD_BYTE3_SHIFT)) & PSI5_S_DIRCMD_DIRCMD_BYTE3_MASK) 1092 /*! @} */ 1093 1094 /*! @name CH0_MSGA - PSI5_S channel 0 message configuration register A */ 1095 /*! @{ */ 1096 1097 #define PSI5_S_CH0_MSGA_TSBUF_EN_MASK (0x4U) 1098 #define PSI5_S_CH0_MSGA_TSBUF_EN_SHIFT (2U) 1099 #define PSI5_S_CH0_MSGA_TSBUF_EN_WIDTH (1U) 1100 #define PSI5_S_CH0_MSGA_TSBUF_EN(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_CH0_MSGA_TSBUF_EN_SHIFT)) & PSI5_S_CH0_MSGA_TSBUF_EN_MASK) 1101 1102 #define PSI5_S_CH0_MSGA_TSBUF_CLR_MASK (0x8U) 1103 #define PSI5_S_CH0_MSGA_TSBUF_CLR_SHIFT (3U) 1104 #define PSI5_S_CH0_MSGA_TSBUF_CLR_WIDTH (1U) 1105 #define PSI5_S_CH0_MSGA_TSBUF_CLR(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_CH0_MSGA_TSBUF_CLR_SHIFT)) & PSI5_S_CH0_MSGA_TSBUF_CLR_MASK) 1106 1107 #define PSI5_S_CH0_MSGA_TIMESTAMP_A_B_SEL_MASK (0x20U) 1108 #define PSI5_S_CH0_MSGA_TIMESTAMP_A_B_SEL_SHIFT (5U) 1109 #define PSI5_S_CH0_MSGA_TIMESTAMP_A_B_SEL_WIDTH (1U) 1110 #define PSI5_S_CH0_MSGA_TIMESTAMP_A_B_SEL(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_CH0_MSGA_TIMESTAMP_A_B_SEL_SHIFT)) & PSI5_S_CH0_MSGA_TIMESTAMP_A_B_SEL_MASK) 1111 1112 #define PSI5_S_CH0_MSGA_F0_BYTE_MASK (0x700U) 1113 #define PSI5_S_CH0_MSGA_F0_BYTE_SHIFT (8U) 1114 #define PSI5_S_CH0_MSGA_F0_BYTE_WIDTH (3U) 1115 #define PSI5_S_CH0_MSGA_F0_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_CH0_MSGA_F0_BYTE_SHIFT)) & PSI5_S_CH0_MSGA_F0_BYTE_MASK) 1116 /*! @} */ 1117 1118 /*! @name CH0_MSGB - PSI5_S channel 0 message configuration register B */ 1119 /*! @{ */ 1120 1121 #define PSI5_S_CH0_MSGB_F0_payload_MASK (0x1FU) 1122 #define PSI5_S_CH0_MSGB_F0_payload_SHIFT (0U) 1123 #define PSI5_S_CH0_MSGB_F0_payload_WIDTH (5U) 1124 #define PSI5_S_CH0_MSGB_F0_payload(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_CH0_MSGB_F0_payload_SHIFT)) & PSI5_S_CH0_MSGB_F0_payload_MASK) 1125 /*! @} */ 1126 1127 /*! @name CH0_MBOX_SR - PSI5_S Mailbox status register channel0 */ 1128 /*! @{ */ 1129 1130 #define PSI5_S_CH0_MBOX_SR_F0_READ_MASK (0x1U) 1131 #define PSI5_S_CH0_MBOX_SR_F0_READ_SHIFT (0U) 1132 #define PSI5_S_CH0_MBOX_SR_F0_READ_WIDTH (1U) 1133 #define PSI5_S_CH0_MBOX_SR_F0_READ(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_CH0_MBOX_SR_F0_READ_SHIFT)) & PSI5_S_CH0_MBOX_SR_F0_READ_MASK) 1134 1135 #define PSI5_S_CH0_MBOX_SR_F0_OV_MASK (0x2U) 1136 #define PSI5_S_CH0_MBOX_SR_F0_OV_SHIFT (1U) 1137 #define PSI5_S_CH0_MBOX_SR_F0_OV_WIDTH (1U) 1138 #define PSI5_S_CH0_MBOX_SR_F0_OV(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_CH0_MBOX_SR_F0_OV_SHIFT)) & PSI5_S_CH0_MBOX_SR_F0_OV_MASK) 1139 1140 #define PSI5_S_CH0_MBOX_SR_F0_ERR_MASK (0x4U) 1141 #define PSI5_S_CH0_MBOX_SR_F0_ERR_SHIFT (2U) 1142 #define PSI5_S_CH0_MBOX_SR_F0_ERR_WIDTH (1U) 1143 #define PSI5_S_CH0_MBOX_SR_F0_ERR(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_CH0_MBOX_SR_F0_ERR_SHIFT)) & PSI5_S_CH0_MBOX_SR_F0_ERR_MASK) 1144 1145 #define PSI5_S_CH0_MBOX_SR_F1_READ_MASK (0x8U) 1146 #define PSI5_S_CH0_MBOX_SR_F1_READ_SHIFT (3U) 1147 #define PSI5_S_CH0_MBOX_SR_F1_READ_WIDTH (1U) 1148 #define PSI5_S_CH0_MBOX_SR_F1_READ(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_CH0_MBOX_SR_F1_READ_SHIFT)) & PSI5_S_CH0_MBOX_SR_F1_READ_MASK) 1149 1150 #define PSI5_S_CH0_MBOX_SR_F1_OV_MASK (0x10U) 1151 #define PSI5_S_CH0_MBOX_SR_F1_OV_SHIFT (4U) 1152 #define PSI5_S_CH0_MBOX_SR_F1_OV_WIDTH (1U) 1153 #define PSI5_S_CH0_MBOX_SR_F1_OV(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_CH0_MBOX_SR_F1_OV_SHIFT)) & PSI5_S_CH0_MBOX_SR_F1_OV_MASK) 1154 1155 #define PSI5_S_CH0_MBOX_SR_F1_ERR_MASK (0x20U) 1156 #define PSI5_S_CH0_MBOX_SR_F1_ERR_SHIFT (5U) 1157 #define PSI5_S_CH0_MBOX_SR_F1_ERR_WIDTH (1U) 1158 #define PSI5_S_CH0_MBOX_SR_F1_ERR(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_CH0_MBOX_SR_F1_ERR_SHIFT)) & PSI5_S_CH0_MBOX_SR_F1_ERR_MASK) 1159 /*! @} */ 1160 1161 /*! @name MSGA - PSI5_S channel message configuration register A */ 1162 /*! @{ */ 1163 1164 #define PSI5_S_MSGA_CH_EN_MASK (0x1U) 1165 #define PSI5_S_MSGA_CH_EN_SHIFT (0U) 1166 #define PSI5_S_MSGA_CH_EN_WIDTH (1U) 1167 #define PSI5_S_MSGA_CH_EN(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_MSGA_CH_EN_SHIFT)) & PSI5_S_MSGA_CH_EN_MASK) 1168 1169 #define PSI5_S_MSGA_G_PC_MASK (0x2U) 1170 #define PSI5_S_MSGA_G_PC_SHIFT (1U) 1171 #define PSI5_S_MSGA_G_PC_WIDTH (1U) 1172 #define PSI5_S_MSGA_G_PC(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_MSGA_G_PC_SHIFT)) & PSI5_S_MSGA_G_PC_MASK) 1173 1174 #define PSI5_S_MSGA_TSBUF_EN_MASK (0x4U) 1175 #define PSI5_S_MSGA_TSBUF_EN_SHIFT (2U) 1176 #define PSI5_S_MSGA_TSBUF_EN_WIDTH (1U) 1177 #define PSI5_S_MSGA_TSBUF_EN(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_MSGA_TSBUF_EN_SHIFT)) & PSI5_S_MSGA_TSBUF_EN_MASK) 1178 1179 #define PSI5_S_MSGA_TSBUF_CLR_MASK (0x8U) 1180 #define PSI5_S_MSGA_TSBUF_CLR_SHIFT (3U) 1181 #define PSI5_S_MSGA_TSBUF_CLR_WIDTH (1U) 1182 #define PSI5_S_MSGA_TSBUF_CLR(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_MSGA_TSBUF_CLR_SHIFT)) & PSI5_S_MSGA_TSBUF_CLR_MASK) 1183 1184 #define PSI5_S_MSGA_TMSG_TCMD_MASK (0x10U) 1185 #define PSI5_S_MSGA_TMSG_TCMD_SHIFT (4U) 1186 #define PSI5_S_MSGA_TMSG_TCMD_WIDTH (1U) 1187 #define PSI5_S_MSGA_TMSG_TCMD(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_MSGA_TMSG_TCMD_SHIFT)) & PSI5_S_MSGA_TMSG_TCMD_MASK) 1188 1189 #define PSI5_S_MSGA_TIME_STAMP_A_B_SEL_MASK (0x20U) 1190 #define PSI5_S_MSGA_TIME_STAMP_A_B_SEL_SHIFT (5U) 1191 #define PSI5_S_MSGA_TIME_STAMP_A_B_SEL_WIDTH (1U) 1192 #define PSI5_S_MSGA_TIME_STAMP_A_B_SEL(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_MSGA_TIME_STAMP_A_B_SEL_SHIFT)) & PSI5_S_MSGA_TIME_STAMP_A_B_SEL_MASK) 1193 1194 #define PSI5_S_MSGA_MODE_MASK (0x40U) 1195 #define PSI5_S_MSGA_MODE_SHIFT (6U) 1196 #define PSI5_S_MSGA_MODE_WIDTH (1U) 1197 #define PSI5_S_MSGA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_MSGA_MODE_SHIFT)) & PSI5_S_MSGA_MODE_MASK) 1198 1199 #define PSI5_S_MSGA_L_PC0_MASK (0x80U) 1200 #define PSI5_S_MSGA_L_PC0_SHIFT (7U) 1201 #define PSI5_S_MSGA_L_PC0_WIDTH (1U) 1202 #define PSI5_S_MSGA_L_PC0(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_MSGA_L_PC0_SHIFT)) & PSI5_S_MSGA_L_PC0_MASK) 1203 1204 #define PSI5_S_MSGA_F0_BYTE_MASK (0x700U) 1205 #define PSI5_S_MSGA_F0_BYTE_SHIFT (8U) 1206 #define PSI5_S_MSGA_F0_BYTE_WIDTH (3U) 1207 #define PSI5_S_MSGA_F0_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_MSGA_F0_BYTE_SHIFT)) & PSI5_S_MSGA_F0_BYTE_MASK) 1208 1209 #define PSI5_S_MSGA_L_PC1_MASK (0x800U) 1210 #define PSI5_S_MSGA_L_PC1_SHIFT (11U) 1211 #define PSI5_S_MSGA_L_PC1_WIDTH (1U) 1212 #define PSI5_S_MSGA_L_PC1(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_MSGA_L_PC1_SHIFT)) & PSI5_S_MSGA_L_PC1_MASK) 1213 1214 #define PSI5_S_MSGA_F1_BYTE_MASK (0x7000U) 1215 #define PSI5_S_MSGA_F1_BYTE_SHIFT (12U) 1216 #define PSI5_S_MSGA_F1_BYTE_WIDTH (3U) 1217 #define PSI5_S_MSGA_F1_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_MSGA_F1_BYTE_SHIFT)) & PSI5_S_MSGA_F1_BYTE_MASK) 1218 1219 #define PSI5_S_MSGA_L_PC2_MASK (0x8000U) 1220 #define PSI5_S_MSGA_L_PC2_SHIFT (15U) 1221 #define PSI5_S_MSGA_L_PC2_WIDTH (1U) 1222 #define PSI5_S_MSGA_L_PC2(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_MSGA_L_PC2_SHIFT)) & PSI5_S_MSGA_L_PC2_MASK) 1223 1224 #define PSI5_S_MSGA_F2_BYTE_MASK (0x70000U) 1225 #define PSI5_S_MSGA_F2_BYTE_SHIFT (16U) 1226 #define PSI5_S_MSGA_F2_BYTE_WIDTH (3U) 1227 #define PSI5_S_MSGA_F2_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_MSGA_F2_BYTE_SHIFT)) & PSI5_S_MSGA_F2_BYTE_MASK) 1228 1229 #define PSI5_S_MSGA_L_PC3_MASK (0x80000U) 1230 #define PSI5_S_MSGA_L_PC3_SHIFT (19U) 1231 #define PSI5_S_MSGA_L_PC3_WIDTH (1U) 1232 #define PSI5_S_MSGA_L_PC3(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_MSGA_L_PC3_SHIFT)) & PSI5_S_MSGA_L_PC3_MASK) 1233 1234 #define PSI5_S_MSGA_F3_BYTE_MASK (0x700000U) 1235 #define PSI5_S_MSGA_F3_BYTE_SHIFT (20U) 1236 #define PSI5_S_MSGA_F3_BYTE_WIDTH (3U) 1237 #define PSI5_S_MSGA_F3_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_MSGA_F3_BYTE_SHIFT)) & PSI5_S_MSGA_F3_BYTE_MASK) 1238 1239 #define PSI5_S_MSGA_L_PC4_MASK (0x800000U) 1240 #define PSI5_S_MSGA_L_PC4_SHIFT (23U) 1241 #define PSI5_S_MSGA_L_PC4_WIDTH (1U) 1242 #define PSI5_S_MSGA_L_PC4(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_MSGA_L_PC4_SHIFT)) & PSI5_S_MSGA_L_PC4_MASK) 1243 1244 #define PSI5_S_MSGA_F4_BYTE_MASK (0x7000000U) 1245 #define PSI5_S_MSGA_F4_BYTE_SHIFT (24U) 1246 #define PSI5_S_MSGA_F4_BYTE_WIDTH (3U) 1247 #define PSI5_S_MSGA_F4_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_MSGA_F4_BYTE_SHIFT)) & PSI5_S_MSGA_F4_BYTE_MASK) 1248 1249 #define PSI5_S_MSGA_L_PC5_MASK (0x8000000U) 1250 #define PSI5_S_MSGA_L_PC5_SHIFT (27U) 1251 #define PSI5_S_MSGA_L_PC5_WIDTH (1U) 1252 #define PSI5_S_MSGA_L_PC5(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_MSGA_L_PC5_SHIFT)) & PSI5_S_MSGA_L_PC5_MASK) 1253 1254 #define PSI5_S_MSGA_F5_BYTE_MASK (0x70000000U) 1255 #define PSI5_S_MSGA_F5_BYTE_SHIFT (28U) 1256 #define PSI5_S_MSGA_F5_BYTE_WIDTH (3U) 1257 #define PSI5_S_MSGA_F5_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_MSGA_F5_BYTE_SHIFT)) & PSI5_S_MSGA_F5_BYTE_MASK) 1258 1259 #define PSI5_S_MSGA_L_PC_EN_MASK (0x80000000U) 1260 #define PSI5_S_MSGA_L_PC_EN_SHIFT (31U) 1261 #define PSI5_S_MSGA_L_PC_EN_WIDTH (1U) 1262 #define PSI5_S_MSGA_L_PC_EN(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_MSGA_L_PC_EN_SHIFT)) & PSI5_S_MSGA_L_PC_EN_MASK) 1263 /*! @} */ 1264 1265 /*! @name MSGB - PSI5_S channel message configuration register B */ 1266 /*! @{ */ 1267 1268 #define PSI5_S_MSGB_F0_payload_MASK (0x1FU) 1269 #define PSI5_S_MSGB_F0_payload_SHIFT (0U) 1270 #define PSI5_S_MSGB_F0_payload_WIDTH (5U) 1271 #define PSI5_S_MSGB_F0_payload(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_MSGB_F0_payload_SHIFT)) & PSI5_S_MSGB_F0_payload_MASK) 1272 1273 #define PSI5_S_MSGB_F1_payload_MASK (0x3E0U) 1274 #define PSI5_S_MSGB_F1_payload_SHIFT (5U) 1275 #define PSI5_S_MSGB_F1_payload_WIDTH (5U) 1276 #define PSI5_S_MSGB_F1_payload(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_MSGB_F1_payload_SHIFT)) & PSI5_S_MSGB_F1_payload_MASK) 1277 1278 #define PSI5_S_MSGB_F2_payload_MASK (0x7C00U) 1279 #define PSI5_S_MSGB_F2_payload_SHIFT (10U) 1280 #define PSI5_S_MSGB_F2_payload_WIDTH (5U) 1281 #define PSI5_S_MSGB_F2_payload(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_MSGB_F2_payload_SHIFT)) & PSI5_S_MSGB_F2_payload_MASK) 1282 1283 #define PSI5_S_MSGB_F3_payload_MASK (0xF8000U) 1284 #define PSI5_S_MSGB_F3_payload_SHIFT (15U) 1285 #define PSI5_S_MSGB_F3_payload_WIDTH (5U) 1286 #define PSI5_S_MSGB_F3_payload(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_MSGB_F3_payload_SHIFT)) & PSI5_S_MSGB_F3_payload_MASK) 1287 1288 #define PSI5_S_MSGB_F4_payload_MASK (0x1F00000U) 1289 #define PSI5_S_MSGB_F4_payload_SHIFT (20U) 1290 #define PSI5_S_MSGB_F4_payload_WIDTH (5U) 1291 #define PSI5_S_MSGB_F4_payload(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_MSGB_F4_payload_SHIFT)) & PSI5_S_MSGB_F4_payload_MASK) 1292 1293 #define PSI5_S_MSGB_F5_payload_MASK (0x3E000000U) 1294 #define PSI5_S_MSGB_F5_payload_SHIFT (25U) 1295 #define PSI5_S_MSGB_F5_payload_WIDTH (5U) 1296 #define PSI5_S_MSGB_F5_payload(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_MSGB_F5_payload_SHIFT)) & PSI5_S_MSGB_F5_payload_MASK) 1297 /*! @} */ 1298 1299 /*! @name MBOX_SR - PSI5_S Mailbox status register channel */ 1300 /*! @{ */ 1301 1302 #define PSI5_S_MBOX_SR_F0_READ_MASK (0x1U) 1303 #define PSI5_S_MBOX_SR_F0_READ_SHIFT (0U) 1304 #define PSI5_S_MBOX_SR_F0_READ_WIDTH (1U) 1305 #define PSI5_S_MBOX_SR_F0_READ(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_MBOX_SR_F0_READ_SHIFT)) & PSI5_S_MBOX_SR_F0_READ_MASK) 1306 1307 #define PSI5_S_MBOX_SR_F0_OV_MASK (0x2U) 1308 #define PSI5_S_MBOX_SR_F0_OV_SHIFT (1U) 1309 #define PSI5_S_MBOX_SR_F0_OV_WIDTH (1U) 1310 #define PSI5_S_MBOX_SR_F0_OV(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_MBOX_SR_F0_OV_SHIFT)) & PSI5_S_MBOX_SR_F0_OV_MASK) 1311 1312 #define PSI5_S_MBOX_SR_F0_ERR_MASK (0x4U) 1313 #define PSI5_S_MBOX_SR_F0_ERR_SHIFT (2U) 1314 #define PSI5_S_MBOX_SR_F0_ERR_WIDTH (1U) 1315 #define PSI5_S_MBOX_SR_F0_ERR(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_MBOX_SR_F0_ERR_SHIFT)) & PSI5_S_MBOX_SR_F0_ERR_MASK) 1316 1317 #define PSI5_S_MBOX_SR_F1_READ_MASK (0x8U) 1318 #define PSI5_S_MBOX_SR_F1_READ_SHIFT (3U) 1319 #define PSI5_S_MBOX_SR_F1_READ_WIDTH (1U) 1320 #define PSI5_S_MBOX_SR_F1_READ(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_MBOX_SR_F1_READ_SHIFT)) & PSI5_S_MBOX_SR_F1_READ_MASK) 1321 1322 #define PSI5_S_MBOX_SR_F1_OV_MASK (0x10U) 1323 #define PSI5_S_MBOX_SR_F1_OV_SHIFT (4U) 1324 #define PSI5_S_MBOX_SR_F1_OV_WIDTH (1U) 1325 #define PSI5_S_MBOX_SR_F1_OV(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_MBOX_SR_F1_OV_SHIFT)) & PSI5_S_MBOX_SR_F1_OV_MASK) 1326 1327 #define PSI5_S_MBOX_SR_F1_ERR_MASK (0x20U) 1328 #define PSI5_S_MBOX_SR_F1_ERR_SHIFT (5U) 1329 #define PSI5_S_MBOX_SR_F1_ERR_WIDTH (1U) 1330 #define PSI5_S_MBOX_SR_F1_ERR(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_MBOX_SR_F1_ERR_SHIFT)) & PSI5_S_MBOX_SR_F1_ERR_MASK) 1331 1332 #define PSI5_S_MBOX_SR_F2_READ_MASK (0x40U) 1333 #define PSI5_S_MBOX_SR_F2_READ_SHIFT (6U) 1334 #define PSI5_S_MBOX_SR_F2_READ_WIDTH (1U) 1335 #define PSI5_S_MBOX_SR_F2_READ(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_MBOX_SR_F2_READ_SHIFT)) & PSI5_S_MBOX_SR_F2_READ_MASK) 1336 1337 #define PSI5_S_MBOX_SR_F2_OV_MASK (0x80U) 1338 #define PSI5_S_MBOX_SR_F2_OV_SHIFT (7U) 1339 #define PSI5_S_MBOX_SR_F2_OV_WIDTH (1U) 1340 #define PSI5_S_MBOX_SR_F2_OV(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_MBOX_SR_F2_OV_SHIFT)) & PSI5_S_MBOX_SR_F2_OV_MASK) 1341 1342 #define PSI5_S_MBOX_SR_F2_ERR_MASK (0x100U) 1343 #define PSI5_S_MBOX_SR_F2_ERR_SHIFT (8U) 1344 #define PSI5_S_MBOX_SR_F2_ERR_WIDTH (1U) 1345 #define PSI5_S_MBOX_SR_F2_ERR(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_MBOX_SR_F2_ERR_SHIFT)) & PSI5_S_MBOX_SR_F2_ERR_MASK) 1346 1347 #define PSI5_S_MBOX_SR_F3_READ_MASK (0x200U) 1348 #define PSI5_S_MBOX_SR_F3_READ_SHIFT (9U) 1349 #define PSI5_S_MBOX_SR_F3_READ_WIDTH (1U) 1350 #define PSI5_S_MBOX_SR_F3_READ(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_MBOX_SR_F3_READ_SHIFT)) & PSI5_S_MBOX_SR_F3_READ_MASK) 1351 1352 #define PSI5_S_MBOX_SR_F3_OV_MASK (0x400U) 1353 #define PSI5_S_MBOX_SR_F3_OV_SHIFT (10U) 1354 #define PSI5_S_MBOX_SR_F3_OV_WIDTH (1U) 1355 #define PSI5_S_MBOX_SR_F3_OV(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_MBOX_SR_F3_OV_SHIFT)) & PSI5_S_MBOX_SR_F3_OV_MASK) 1356 1357 #define PSI5_S_MBOX_SR_F3_ERR_MASK (0x800U) 1358 #define PSI5_S_MBOX_SR_F3_ERR_SHIFT (11U) 1359 #define PSI5_S_MBOX_SR_F3_ERR_WIDTH (1U) 1360 #define PSI5_S_MBOX_SR_F3_ERR(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_MBOX_SR_F3_ERR_SHIFT)) & PSI5_S_MBOX_SR_F3_ERR_MASK) 1361 1362 #define PSI5_S_MBOX_SR_F4_READ_MASK (0x1000U) 1363 #define PSI5_S_MBOX_SR_F4_READ_SHIFT (12U) 1364 #define PSI5_S_MBOX_SR_F4_READ_WIDTH (1U) 1365 #define PSI5_S_MBOX_SR_F4_READ(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_MBOX_SR_F4_READ_SHIFT)) & PSI5_S_MBOX_SR_F4_READ_MASK) 1366 1367 #define PSI5_S_MBOX_SR_F4_OV_MASK (0x2000U) 1368 #define PSI5_S_MBOX_SR_F4_OV_SHIFT (13U) 1369 #define PSI5_S_MBOX_SR_F4_OV_WIDTH (1U) 1370 #define PSI5_S_MBOX_SR_F4_OV(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_MBOX_SR_F4_OV_SHIFT)) & PSI5_S_MBOX_SR_F4_OV_MASK) 1371 1372 #define PSI5_S_MBOX_SR_F4_ERR_MASK (0x4000U) 1373 #define PSI5_S_MBOX_SR_F4_ERR_SHIFT (14U) 1374 #define PSI5_S_MBOX_SR_F4_ERR_WIDTH (1U) 1375 #define PSI5_S_MBOX_SR_F4_ERR(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_MBOX_SR_F4_ERR_SHIFT)) & PSI5_S_MBOX_SR_F4_ERR_MASK) 1376 1377 #define PSI5_S_MBOX_SR_F5_READ_MASK (0x8000U) 1378 #define PSI5_S_MBOX_SR_F5_READ_SHIFT (15U) 1379 #define PSI5_S_MBOX_SR_F5_READ_WIDTH (1U) 1380 #define PSI5_S_MBOX_SR_F5_READ(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_MBOX_SR_F5_READ_SHIFT)) & PSI5_S_MBOX_SR_F5_READ_MASK) 1381 1382 #define PSI5_S_MBOX_SR_F5_OV_MASK (0x10000U) 1383 #define PSI5_S_MBOX_SR_F5_OV_SHIFT (16U) 1384 #define PSI5_S_MBOX_SR_F5_OV_WIDTH (1U) 1385 #define PSI5_S_MBOX_SR_F5_OV(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_MBOX_SR_F5_OV_SHIFT)) & PSI5_S_MBOX_SR_F5_OV_MASK) 1386 1387 #define PSI5_S_MBOX_SR_F5_ERR_MASK (0x20000U) 1388 #define PSI5_S_MBOX_SR_F5_ERR_SHIFT (17U) 1389 #define PSI5_S_MBOX_SR_F5_ERR_WIDTH (1U) 1390 #define PSI5_S_MBOX_SR_F5_ERR(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_MBOX_SR_F5_ERR_SHIFT)) & PSI5_S_MBOX_SR_F5_ERR_MASK) 1391 /*! @} */ 1392 1393 /*! @name WD_CFGR - PSI5_S channel watchdog configuration register */ 1394 /*! @{ */ 1395 1396 #define PSI5_S_WD_CFGR_WD_TO_MASK (0xFFFFFFU) 1397 #define PSI5_S_WD_CFGR_WD_TO_SHIFT (0U) 1398 #define PSI5_S_WD_CFGR_WD_TO_WIDTH (24U) 1399 #define PSI5_S_WD_CFGR_WD_TO(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_WD_CFGR_WD_TO_SHIFT)) & PSI5_S_WD_CFGR_WD_TO_MASK) 1400 1401 #define PSI5_S_WD_CFGR_WDEN_MASK (0x2000000U) 1402 #define PSI5_S_WD_CFGR_WDEN_SHIFT (25U) 1403 #define PSI5_S_WD_CFGR_WDEN_WIDTH (1U) 1404 #define PSI5_S_WD_CFGR_WDEN(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_WD_CFGR_WDEN_SHIFT)) & PSI5_S_WD_CFGR_WDEN_MASK) 1405 1406 #define PSI5_S_WD_CFGR_WDCS_MASK (0x4000000U) 1407 #define PSI5_S_WD_CFGR_WDCS_SHIFT (26U) 1408 #define PSI5_S_WD_CFGR_WDCS_WIDTH (1U) 1409 #define PSI5_S_WD_CFGR_WDCS(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_WD_CFGR_WDCS_SHIFT)) & PSI5_S_WD_CFGR_WDCS_MASK) 1410 1411 #define PSI5_S_WD_CFGR_WDRST_MASK (0x8000000U) 1412 #define PSI5_S_WD_CFGR_WDRST_SHIFT (27U) 1413 #define PSI5_S_WD_CFGR_WDRST_WIDTH (1U) 1414 #define PSI5_S_WD_CFGR_WDRST(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_WD_CFGR_WDRST_SHIFT)) & PSI5_S_WD_CFGR_WDRST_MASK) 1415 /*! @} */ 1416 1417 /*! @name DDTRIG_OFFR - PSI5_S DDSR Trigger offset register channel */ 1418 /*! @{ */ 1419 1420 #define PSI5_S_DDTRIG_OFFR_DDTRIG_OFFR_MASK (0xFFFFU) 1421 #define PSI5_S_DDTRIG_OFFR_DDTRIG_OFFR_SHIFT (0U) 1422 #define PSI5_S_DDTRIG_OFFR_DDTRIG_OFFR_WIDTH (16U) 1423 #define PSI5_S_DDTRIG_OFFR_DDTRIG_OFFR(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_DDTRIG_OFFR_DDTRIG_OFFR_SHIFT)) & PSI5_S_DDTRIG_OFFR_DDTRIG_OFFR_MASK) 1424 /*! @} */ 1425 1426 /*! @name DDTRIG_PERR - PSI5_S DDSR Trigger period register channel */ 1427 /*! @{ */ 1428 1429 #define PSI5_S_DDTRIG_PERR_DDTRIG_PERR_MASK (0xFFFFU) 1430 #define PSI5_S_DDTRIG_PERR_DDTRIG_PERR_SHIFT (0U) 1431 #define PSI5_S_DDTRIG_PERR_DDTRIG_PERR_WIDTH (16U) 1432 #define PSI5_S_DDTRIG_PERR_DDTRIG_PERR(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_DDTRIG_PERR_DDTRIG_PERR_SHIFT)) & PSI5_S_DDTRIG_PERR_DDTRIG_PERR_MASK) 1433 /*! @} */ 1434 1435 /*! @name E2SCR - PSI5_S ECU to Sensor Control Register */ 1436 /*! @{ */ 1437 1438 #define PSI5_S_E2SCR_CMD_TYPE_MASK (0x7U) 1439 #define PSI5_S_E2SCR_CMD_TYPE_SHIFT (0U) 1440 #define PSI5_S_E2SCR_CMD_TYPE_WIDTH (3U) 1441 #define PSI5_S_E2SCR_CMD_TYPE(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_E2SCR_CMD_TYPE_SHIFT)) & PSI5_S_E2SCR_CMD_TYPE_MASK) 1442 1443 #define PSI5_S_E2SCR_DDSR_RDY_IE_MASK (0x20U) 1444 #define PSI5_S_E2SCR_DDSR_RDY_IE_SHIFT (5U) 1445 #define PSI5_S_E2SCR_DDSR_RDY_IE_WIDTH (1U) 1446 #define PSI5_S_E2SCR_DDSR_RDY_IE(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_E2SCR_DDSR_RDY_IE_SHIFT)) & PSI5_S_E2SCR_DDSR_RDY_IE_MASK) 1447 1448 #define PSI5_S_E2SCR_CMDPR_BZY_IE_MASK (0x40U) 1449 #define PSI5_S_E2SCR_CMDPR_BZY_IE_SHIFT (6U) 1450 #define PSI5_S_E2SCR_CMDPR_BZY_IE_WIDTH (1U) 1451 #define PSI5_S_E2SCR_CMDPR_BZY_IE(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_E2SCR_CMDPR_BZY_IE_SHIFT)) & PSI5_S_E2SCR_CMDPR_BZY_IE_MASK) 1452 1453 #define PSI5_S_E2SCR_CMDTR_NWRT_IE_MASK (0x80U) 1454 #define PSI5_S_E2SCR_CMDTR_NWRT_IE_SHIFT (7U) 1455 #define PSI5_S_E2SCR_CMDTR_NWRT_IE_WIDTH (1U) 1456 #define PSI5_S_E2SCR_CMDTR_NWRT_IE(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_E2SCR_CMDTR_NWRT_IE_SHIFT)) & PSI5_S_E2SCR_CMDTR_NWRT_IE_MASK) 1457 1458 #define PSI5_S_E2SCR_SYNCHRO_OVF_IE_MASK (0x200U) 1459 #define PSI5_S_E2SCR_SYNCHRO_OVF_IE_SHIFT (9U) 1460 #define PSI5_S_E2SCR_SYNCHRO_OVF_IE_WIDTH (1U) 1461 #define PSI5_S_E2SCR_SYNCHRO_OVF_IE(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_E2SCR_SYNCHRO_OVF_IE_SHIFT)) & PSI5_S_E2SCR_SYNCHRO_OVF_IE_MASK) 1462 1463 #define PSI5_S_E2SCR_CMDTR_SW_CTRL_MASK (0x800U) 1464 #define PSI5_S_E2SCR_CMDTR_SW_CTRL_SHIFT (11U) 1465 #define PSI5_S_E2SCR_CMDTR_SW_CTRL_WIDTH (1U) 1466 #define PSI5_S_E2SCR_CMDTR_SW_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_E2SCR_CMDTR_SW_CTRL_SHIFT)) & PSI5_S_E2SCR_CMDTR_SW_CTRL_MASK) 1467 1468 #define PSI5_S_E2SCR_DDSR_CLK_SEL_MASK (0x1000U) 1469 #define PSI5_S_E2SCR_DDSR_CLK_SEL_SHIFT (12U) 1470 #define PSI5_S_E2SCR_DDSR_CLK_SEL_WIDTH (1U) 1471 #define PSI5_S_E2SCR_DDSR_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_E2SCR_DDSR_CLK_SEL_SHIFT)) & PSI5_S_E2SCR_DDSR_CLK_SEL_MASK) 1472 1473 #define PSI5_S_E2SCR_DDSR_CLR_MASK (0x2000U) 1474 #define PSI5_S_E2SCR_DDSR_CLR_SHIFT (13U) 1475 #define PSI5_S_E2SCR_DDSR_CLR_WIDTH (1U) 1476 #define PSI5_S_E2SCR_DDSR_CLR(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_E2SCR_DDSR_CLR_SHIFT)) & PSI5_S_E2SCR_DDSR_CLR_MASK) 1477 1478 #define PSI5_S_E2SCR_DDSR_SHIFT_SEL_MASK (0x4000U) 1479 #define PSI5_S_E2SCR_DDSR_SHIFT_SEL_SHIFT (14U) 1480 #define PSI5_S_E2SCR_DDSR_SHIFT_SEL_WIDTH (1U) 1481 #define PSI5_S_E2SCR_DDSR_SHIFT_SEL(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_E2SCR_DDSR_SHIFT_SEL_SHIFT)) & PSI5_S_E2SCR_DDSR_SHIFT_SEL_MASK) 1482 1483 #define PSI5_S_E2SCR_DEFAULT_SYNC_MASK (0x8000U) 1484 #define PSI5_S_E2SCR_DEFAULT_SYNC_SHIFT (15U) 1485 #define PSI5_S_E2SCR_DEFAULT_SYNC_WIDTH (1U) 1486 #define PSI5_S_E2SCR_DEFAULT_SYNC(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_E2SCR_DEFAULT_SYNC_SHIFT)) & PSI5_S_E2SCR_DEFAULT_SYNC_MASK) 1487 1488 #define PSI5_S_E2SCR_GL_TRIG_SEL_MASK (0x10000U) 1489 #define PSI5_S_E2SCR_GL_TRIG_SEL_SHIFT (16U) 1490 #define PSI5_S_E2SCR_GL_TRIG_SEL_WIDTH (1U) 1491 #define PSI5_S_E2SCR_GL_TRIG_SEL(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_E2SCR_GL_TRIG_SEL_SHIFT)) & PSI5_S_E2SCR_GL_TRIG_SEL_MASK) 1492 1493 #define PSI5_S_E2SCR_CH_TRIG_MASK (0x20000U) 1494 #define PSI5_S_E2SCR_CH_TRIG_SHIFT (17U) 1495 #define PSI5_S_E2SCR_CH_TRIG_WIDTH (1U) 1496 #define PSI5_S_E2SCR_CH_TRIG(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_E2SCR_CH_TRIG_SHIFT)) & PSI5_S_E2SCR_CH_TRIG_MASK) 1497 1498 #define PSI5_S_E2SCR_ACMD_MASK (0x1F00000U) 1499 #define PSI5_S_E2SCR_ACMD_SHIFT (20U) 1500 #define PSI5_S_E2SCR_ACMD_WIDTH (5U) 1501 #define PSI5_S_E2SCR_ACMD(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_E2SCR_ACMD_SHIFT)) & PSI5_S_E2SCR_ACMD_MASK) 1502 1503 #define PSI5_S_E2SCR_CMD_MASK (0x7C000000U) 1504 #define PSI5_S_E2SCR_CMD_SHIFT (26U) 1505 #define PSI5_S_E2SCR_CMD_WIDTH (5U) 1506 #define PSI5_S_E2SCR_CMD(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_E2SCR_CMD_SHIFT)) & PSI5_S_E2SCR_CMD_MASK) 1507 /*! @} */ 1508 1509 /*! @name E2SSR - PSI5_S ECU to Sensor Status Register */ 1510 /*! @{ */ 1511 1512 #define PSI5_S_E2SSR_DDSR_RDY_MASK (0x20U) 1513 #define PSI5_S_E2SSR_DDSR_RDY_SHIFT (5U) 1514 #define PSI5_S_E2SSR_DDSR_RDY_WIDTH (1U) 1515 #define PSI5_S_E2SSR_DDSR_RDY(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_E2SSR_DDSR_RDY_SHIFT)) & PSI5_S_E2SSR_DDSR_RDY_MASK) 1516 1517 #define PSI5_S_E2SSR_CMDPR_BZY_MASK (0x40U) 1518 #define PSI5_S_E2SSR_CMDPR_BZY_SHIFT (6U) 1519 #define PSI5_S_E2SSR_CMDPR_BZY_WIDTH (1U) 1520 #define PSI5_S_E2SSR_CMDPR_BZY(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_E2SSR_CMDPR_BZY_SHIFT)) & PSI5_S_E2SSR_CMDPR_BZY_MASK) 1521 1522 #define PSI5_S_E2SSR_CMDTR_NWRT_MASK (0x80U) 1523 #define PSI5_S_E2SSR_CMDTR_NWRT_SHIFT (7U) 1524 #define PSI5_S_E2SSR_CMDTR_NWRT_WIDTH (1U) 1525 #define PSI5_S_E2SSR_CMDTR_NWRT(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_E2SSR_CMDTR_NWRT_SHIFT)) & PSI5_S_E2SSR_CMDTR_NWRT_MASK) 1526 1527 #define PSI5_S_E2SSR_SYCHRO_OVF_MASK (0x200U) 1528 #define PSI5_S_E2SSR_SYCHRO_OVF_SHIFT (9U) 1529 #define PSI5_S_E2SSR_SYCHRO_OVF_WIDTH (1U) 1530 #define PSI5_S_E2SSR_SYCHRO_OVF(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_E2SSR_SYCHRO_OVF_SHIFT)) & PSI5_S_E2SSR_SYCHRO_OVF_MASK) 1531 /*! @} */ 1532 1533 /*! @name DDSR_H - PSI5_S channel1 ECU to Sensor Downstream Data Shift Register High */ 1534 /*! @{ */ 1535 1536 #define PSI5_S_DDSR_H_DDSR_H_MASK (0x7FFU) 1537 #define PSI5_S_DDSR_H_DDSR_H_SHIFT (0U) 1538 #define PSI5_S_DDSR_H_DDSR_H_WIDTH (11U) 1539 #define PSI5_S_DDSR_H_DDSR_H(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_DDSR_H_DDSR_H_SHIFT)) & PSI5_S_DDSR_H_DDSR_H_MASK) 1540 /*! @} */ 1541 1542 /*! @name DDSR_L - PSI5_S channel1 ECU to Sensor Downstream Data Shift Register Low */ 1543 /*! @{ */ 1544 1545 #define PSI5_S_DDSR_L_DDSR_L2_MASK (0xFFFFFFU) 1546 #define PSI5_S_DDSR_L_DDSR_L2_SHIFT (0U) 1547 #define PSI5_S_DDSR_L_DDSR_L2_WIDTH (24U) 1548 #define PSI5_S_DDSR_L_DDSR_L2(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_DDSR_L_DDSR_L2_SHIFT)) & PSI5_S_DDSR_L_DDSR_L2_MASK) 1549 1550 #define PSI5_S_DDSR_L_DDSR_L1_MASK (0xFF000000U) 1551 #define PSI5_S_DDSR_L_DDSR_L1_SHIFT (24U) 1552 #define PSI5_S_DDSR_L_DDSR_L1_WIDTH (8U) 1553 #define PSI5_S_DDSR_L_DDSR_L1(x) (((uint32_t)(((uint32_t)(x)) << PSI5_S_DDSR_L_DDSR_L1_SHIFT)) & PSI5_S_DDSR_L_DDSR_L1_MASK) 1554 /*! @} */ 1555 1556 /*! 1557 * @} 1558 */ /* end of group PSI5_S_Register_Masks */ 1559 1560 /*! 1561 * @} 1562 */ /* end of group PSI5_S_Peripheral_Access_Layer */ 1563 1564 #endif /* #if !defined(S32Z2_PSI5_S_H_) */ 1565
