1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2022 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K116_CMU.h 10 * @version 1.1 11 * @date 2022-01-21 12 * @brief Peripheral Access Layer for S32K116_CMU 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K116_CMU_H_) /* Check if memory map has not been already included */ 58 #define S32K116_CMU_H_ 59 60 #include "S32K116_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- CMU Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup CMU_Peripheral_Access_Layer CMU Peripheral Access Layer 68 * @{ 69 */ 70 71 /** CMU - Register Layout Typedef */ 72 typedef struct { 73 __IO uint32_t GCR; /**< Global Configuration Register, offset: 0x0 */ 74 __IO uint32_t RCCR; /**< Reference Count Configuration Register, offset: 0x4 */ 75 __IO uint32_t HTCR; /**< High Threshold Configuration Register, offset: 0x8 */ 76 __IO uint32_t LTCR; /**< Low Threshold Configuration Register, offset: 0xC */ 77 __IO uint32_t SR; /**< Status Register, offset: 0x10 */ 78 __IO uint32_t IER; /**< Interrupt Enable Register, offset: 0x14 */ 79 } CMU_Type, *CMU_MemMapPtr; 80 81 /** Number of instances of the CMU module. */ 82 #define CMU_INSTANCE_COUNT (2u) 83 84 /* CMU - Peripheral instance base addresses */ 85 /** Peripheral CMU0 base address */ 86 #define IP_CMU0_BASE (0x4003E000u) 87 /** Peripheral CMU0 base pointer */ 88 #define IP_CMU0 ((CMU_Type *)IP_CMU0_BASE) 89 /** Peripheral CMU1 base address */ 90 #define IP_CMU1_BASE (0x4003F000u) 91 /** Peripheral CMU1 base pointer */ 92 #define IP_CMU1 ((CMU_Type *)IP_CMU1_BASE) 93 /** Array initializer of CMU peripheral base addresses */ 94 #define IP_CMU_BASE_ADDRS { IP_CMU0_BASE, IP_CMU1_BASE } 95 /** Array initializer of CMU peripheral base pointers */ 96 #define IP_CMU_BASE_PTRS { IP_CMU0, IP_CMU1 } 97 98 /* ---------------------------------------------------------------------------- 99 -- CMU Register Masks 100 ---------------------------------------------------------------------------- */ 101 102 /*! 103 * @addtogroup CMU_Register_Masks CMU Register Masks 104 * @{ 105 */ 106 107 /*! @name GCR - Global Configuration Register */ 108 /*! @{ */ 109 110 #define CMU_GCR_FCE_MASK (0x1U) 111 #define CMU_GCR_FCE_SHIFT (0U) 112 #define CMU_GCR_FCE_WIDTH (1U) 113 #define CMU_GCR_FCE(x) (((uint32_t)(((uint32_t)(x)) << CMU_GCR_FCE_SHIFT)) & CMU_GCR_FCE_MASK) 114 /*! @} */ 115 116 /*! @name RCCR - Reference Count Configuration Register */ 117 /*! @{ */ 118 119 #define CMU_RCCR_REF_CNT_MASK (0xFFFFU) 120 #define CMU_RCCR_REF_CNT_SHIFT (0U) 121 #define CMU_RCCR_REF_CNT_WIDTH (16U) 122 #define CMU_RCCR_REF_CNT(x) (((uint32_t)(((uint32_t)(x)) << CMU_RCCR_REF_CNT_SHIFT)) & CMU_RCCR_REF_CNT_MASK) 123 /*! @} */ 124 125 /*! @name HTCR - High Threshold Configuration Register */ 126 /*! @{ */ 127 128 #define CMU_HTCR_HFREF_MASK (0xFFFFFFU) 129 #define CMU_HTCR_HFREF_SHIFT (0U) 130 #define CMU_HTCR_HFREF_WIDTH (24U) 131 #define CMU_HTCR_HFREF(x) (((uint32_t)(((uint32_t)(x)) << CMU_HTCR_HFREF_SHIFT)) & CMU_HTCR_HFREF_MASK) 132 /*! @} */ 133 134 /*! @name LTCR - Low Threshold Configuration Register */ 135 /*! @{ */ 136 137 #define CMU_LTCR_LFREF_MASK (0xFFFFFFU) 138 #define CMU_LTCR_LFREF_SHIFT (0U) 139 #define CMU_LTCR_LFREF_WIDTH (24U) 140 #define CMU_LTCR_LFREF(x) (((uint32_t)(((uint32_t)(x)) << CMU_LTCR_LFREF_SHIFT)) & CMU_LTCR_LFREF_MASK) 141 /*! @} */ 142 143 /*! @name SR - Status Register */ 144 /*! @{ */ 145 146 #define CMU_SR_FLL_MASK (0x1U) 147 #define CMU_SR_FLL_SHIFT (0U) 148 #define CMU_SR_FLL_WIDTH (1U) 149 #define CMU_SR_FLL(x) (((uint32_t)(((uint32_t)(x)) << CMU_SR_FLL_SHIFT)) & CMU_SR_FLL_MASK) 150 151 #define CMU_SR_FHH_MASK (0x2U) 152 #define CMU_SR_FHH_SHIFT (1U) 153 #define CMU_SR_FHH_WIDTH (1U) 154 #define CMU_SR_FHH(x) (((uint32_t)(((uint32_t)(x)) << CMU_SR_FHH_SHIFT)) & CMU_SR_FHH_MASK) 155 156 #define CMU_SR_STATE_MASK (0xCU) 157 #define CMU_SR_STATE_SHIFT (2U) 158 #define CMU_SR_STATE_WIDTH (2U) 159 #define CMU_SR_STATE(x) (((uint32_t)(((uint32_t)(x)) << CMU_SR_STATE_SHIFT)) & CMU_SR_STATE_MASK) 160 161 #define CMU_SR_RS_MASK (0x10U) 162 #define CMU_SR_RS_SHIFT (4U) 163 #define CMU_SR_RS_WIDTH (1U) 164 #define CMU_SR_RS(x) (((uint32_t)(((uint32_t)(x)) << CMU_SR_RS_SHIFT)) & CMU_SR_RS_MASK) 165 /*! @} */ 166 167 /*! @name IER - Interrupt Enable Register */ 168 /*! @{ */ 169 170 #define CMU_IER_FLLIE_MASK (0x1U) 171 #define CMU_IER_FLLIE_SHIFT (0U) 172 #define CMU_IER_FLLIE_WIDTH (1U) 173 #define CMU_IER_FLLIE(x) (((uint32_t)(((uint32_t)(x)) << CMU_IER_FLLIE_SHIFT)) & CMU_IER_FLLIE_MASK) 174 175 #define CMU_IER_FHHIE_MASK (0x2U) 176 #define CMU_IER_FHHIE_SHIFT (1U) 177 #define CMU_IER_FHHIE_WIDTH (1U) 178 #define CMU_IER_FHHIE(x) (((uint32_t)(((uint32_t)(x)) << CMU_IER_FHHIE_SHIFT)) & CMU_IER_FHHIE_MASK) 179 180 #define CMU_IER_FLLAIE_MASK (0x4U) 181 #define CMU_IER_FLLAIE_SHIFT (2U) 182 #define CMU_IER_FLLAIE_WIDTH (1U) 183 #define CMU_IER_FLLAIE(x) (((uint32_t)(((uint32_t)(x)) << CMU_IER_FLLAIE_SHIFT)) & CMU_IER_FLLAIE_MASK) 184 185 #define CMU_IER_FHHAIE_MASK (0x8U) 186 #define CMU_IER_FHHAIE_SHIFT (3U) 187 #define CMU_IER_FHHAIE_WIDTH (1U) 188 #define CMU_IER_FHHAIE(x) (((uint32_t)(((uint32_t)(x)) << CMU_IER_FHHAIE_SHIFT)) & CMU_IER_FHHAIE_MASK) 189 /*! @} */ 190 191 /*! 192 * @} 193 */ /* end of group CMU_Register_Masks */ 194 195 /*! 196 * @} 197 */ /* end of group CMU_Peripheral_Access_Layer */ 198 199 #endif /* #if !defined(S32K116_CMU_H_) */ 200
