Searched refs:PLLFD (Results 1 – 7 of 7) sorted by relevance
210 Value = Clock_Ip_apxPll[Instance].PllInstance->PLLFD; in Clock_Ip_SetPlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize()214 Clock_Ip_apxPll[Instance].PllInstance->PLLFD = Value; in Clock_Ip_SetPlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize()320 Value = Clock_Ip_apxPll[Instance].PllInstance->PLLFD; in Clock_Ip_SetPlldigRdivMfiMfnSdmen()324 Clock_Ip_apxPll[Instance].PllInstance->PLLFD = Value; in Clock_Ip_SetPlldigRdivMfiMfnSdmen()
247 …IP_CORE_PLL->PLLFD &= ~(PLLDIG_PLLFD_MFN_MASK | PLLDIG_PLLFD_SDMEN_MASK); /* Disable modulati… in Clock_Ip_SpecificPlatformInitClock()255 …IP_PERIPH_PLL->PLLFD &= ~(PLLDIG_PLLFD_MFN_MASK | PLLDIG_PLLFD_SDMEN_MASK); /* Disable modula… in Clock_Ip_SpecificPlatformInitClock()285 …IP_CORE_PLL->PLLFD &= ~(PLLDIG_PLLFD_MFN_MASK | PLLDIG_PLLFD_SDMEN_MASK); /* Disable modulati… in Clock_Ip_SpecificPlatformInitClock()305 …IP_PERIPH_PLL->PLLFD &= ~(PLLDIG_PLLFD_MFN_MASK | PLLDIG_PLLFD_SDMEN_MASK); /* Disable modula… in Clock_Ip_SpecificPlatformInitClock()
1383 …(Clock_Ip_u32CorePllChecksum != (IP_CORE_PLL->PLLCLKMUX ^ IP_CORE_PLL->PLLDV ^ IP_CORE_PLL->PLLFD)) in Clock_Ip_Get_COREPLL_CLK_Frequency()1385 … Clock_Ip_u32CorePllChecksum = (IP_CORE_PLL->PLLCLKMUX ^ IP_CORE_PLL->PLLDV ^ IP_CORE_PLL->PLLFD); in Clock_Ip_Get_COREPLL_CLK_Frequency()1393 …p_u32PeriphPllChecksum != (IP_PERIPH_PLL->PLLCLKMUX ^ IP_PERIPH_PLL->PLLDV ^ IP_PERIPH_PLL->PLLFD)) in Clock_Ip_Get_PERIPHPLL_CLK_Frequency()1395 …Ip_u32PeriphPllChecksum = (IP_PERIPH_PLL->PLLCLKMUX ^ IP_PERIPH_PLL->PLLDV ^ IP_PERIPH_PLL->PLLFD); in Clock_Ip_Get_PERIPHPLL_CLK_Frequency()1403 … if (Clock_Ip_u32DdrPllChecksum != (IP_DDR_PLL->PLLCLKMUX ^ IP_DDR_PLL->PLLDV ^ IP_DDR_PLL->PLLFD)) in Clock_Ip_Get_DDRPLL_CLK_Frequency()1405 … Clock_Ip_u32DdrPllChecksum = (IP_DDR_PLL->PLLCLKMUX ^ IP_DDR_PLL->PLLDV ^ IP_DDR_PLL->PLLFD); in Clock_Ip_Get_DDRPLL_CLK_Frequency()1422 …s1Checksum != (IP_CORE_PLL->PLLCLKMUX ^ IP_CORE_PLL->PLLDV ^ IP_CORE_PLL->PLLFD ^ IP_CORE_PLL->PLL… in Clock_Ip_Get_COREPLL_DFS0_Frequency()1424 …fs1Checksum = (IP_CORE_PLL->PLLCLKMUX ^ IP_CORE_PLL->PLLDV ^ IP_CORE_PLL->PLLFD ^ IP_CORE_PLL->PLL… in Clock_Ip_Get_COREPLL_DFS0_Frequency()1432 …s2Checksum != (IP_CORE_PLL->PLLCLKMUX ^ IP_CORE_PLL->PLLDV ^ IP_CORE_PLL->PLLFD ^ IP_CORE_PLL->PLL… in Clock_Ip_Get_COREPLL_DFS1_Frequency()1434 …fs2Checksum = (IP_CORE_PLL->PLLCLKMUX ^ IP_CORE_PLL->PLLDV ^ IP_CORE_PLL->PLLFD ^ IP_CORE_PLL->PLL… in Clock_Ip_Get_COREPLL_DFS1_Frequency()[all …]
203 Value = Clock_Ip_apxPll[Instance].PllInstance->PLLFD; in Clock_Ip_SetPllRdivMfiMfnOdiv2SdmenSsscgbypSpreadctlStepnoStepsize()207 Clock_Ip_apxPll[Instance].PllInstance->PLLFD = Value; in Clock_Ip_SetPllRdivMfiMfnOdiv2SdmenSsscgbypSpreadctlStepnoStepsize()
1797 uint32 PLLFDBuffer = IP_PLL->PLLFD; in Clock_Ip_Get_PLL_CLK_Frequency()4009 Mfn = ((Base->PLLFD & PLL_PLLFD_MFN_MASK) >> PLL_PLLFD_MFN_SHIFT); /* Mfn */ in Clock_Ip_PLL_VCO()
80 __IO uint32_t PLLFD; /**< PLL Fractional Divider, offset: 0x10 */ member
