1 /*
2  * Copyright 2021-2022 NXP
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 /**
7 *   @file       Clock_Ip_Pll.c
8 *   @version    0.9.0
9 *
10 *   @brief   CLOCK driver implementations.
11 *   @details CLOCK driver implementations.
12 *
13 *   @addtogroup CLOCK_DRIVER Clock Ip Driver
14 *   @{
15 */
16 
17 #ifdef __cplusplus
18 extern "C"{
19 #endif
20 
21 
22 /*==================================================================================================
23 *                                          INCLUDE FILES
24 * 1) system and project includes
25 * 2) needed interfaces from external units
26 * 3) internal and external interfaces from this unit
27 ==================================================================================================*/
28 
29 #include "Clock_Ip_Private.h"
30 
31 /*==================================================================================================
32                                SOURCE FILE VERSION INFORMATION
33 ==================================================================================================*/
34 #define CLOCK_IP_PLL_VENDOR_ID_C                      43
35 #define CLOCK_IP_PLL_AR_RELEASE_MAJOR_VERSION_C       4
36 #define CLOCK_IP_PLL_AR_RELEASE_MINOR_VERSION_C       7
37 #define CLOCK_IP_PLL_AR_RELEASE_REVISION_VERSION_C    0
38 #define CLOCK_IP_PLL_SW_MAJOR_VERSION_C               0
39 #define CLOCK_IP_PLL_SW_MINOR_VERSION_C               9
40 #define CLOCK_IP_PLL_SW_PATCH_VERSION_C               0
41 
42 /*==================================================================================================
43 *                                     FILE VERSION CHECKS
44 ==================================================================================================*/
45 /* Check if Clock_Ip_Pll.c file and Clock_Ip_Private.h file are of the same vendor */
46 #if (CLOCK_IP_PLL_VENDOR_ID_C != CLOCK_IP_PRIVATE_VENDOR_ID)
47     #error "Clock_Ip_Pll.c and Clock_Ip_Private.h have different vendor ids"
48 #endif
49 
50 /* Check if Clock_Ip_Pll.c file and Clock_Ip_Private.h file are of the same Autosar version */
51 #if ((CLOCK_IP_PLL_AR_RELEASE_MAJOR_VERSION_C != CLOCK_IP_PRIVATE_AR_RELEASE_MAJOR_VERSION) || \
52      (CLOCK_IP_PLL_AR_RELEASE_MINOR_VERSION_C != CLOCK_IP_PRIVATE_AR_RELEASE_MINOR_VERSION) || \
53      (CLOCK_IP_PLL_AR_RELEASE_REVISION_VERSION_C != CLOCK_IP_PRIVATE_AR_RELEASE_REVISION_VERSION) \
54     )
55     #error "AutoSar Version Numbers of Clock_Ip_Pll.c and Clock_Ip_Private.h are different"
56 #endif
57 
58 /* Check if Clock_Ip_Pll.c file and Clock_Ip_Private.h file are of the same Software version */
59 #if ((CLOCK_IP_PLL_SW_MAJOR_VERSION_C != CLOCK_IP_PRIVATE_SW_MAJOR_VERSION) || \
60      (CLOCK_IP_PLL_SW_MINOR_VERSION_C != CLOCK_IP_PRIVATE_SW_MINOR_VERSION) || \
61      (CLOCK_IP_PLL_SW_PATCH_VERSION_C != CLOCK_IP_PRIVATE_SW_PATCH_VERSION) \
62     )
63     #error "Software Version Numbers of Clock_Ip_Pll.c and Clock_Ip_Private.h are different"
64 #endif
65 
66 /*==================================================================================================
67 *                           LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS)
68 ==================================================================================================*/
69 
70 /*==================================================================================================
71 *                                          LOCAL MACROS
72 ==================================================================================================*/
73 
74 /*==================================================================================================
75 *                                         LOCAL CONSTANTS
76 ==================================================================================================*/
77 
78 /*==================================================================================================
79 *                                         LOCAL VARIABLES
80 ==================================================================================================*/
81 
82 /*==================================================================================================
83 *                                        GLOBAL CONSTANTS
84 ==================================================================================================*/
85 
86 /*==================================================================================================
87 *                                        GLOBAL VARIABLES
88 ==================================================================================================*/
89 
90 /*==================================================================================================
91 *                                    GLOBAL FUNCTION PROTOTYPES
92 ==================================================================================================*/
93 /* Clock start section code */
94 #define MCU_START_SEC_CODE
95 
96 #include "Mcu_MemMap.h"
97 
98 /*==================================================================================================
99 *                                    LOCAL FUNCTION PROTOTYPES
100 ==================================================================================================*/
101 
102 
103 static void Clock_Ip_CallbackPllEmpty(Clock_Ip_PllConfigType const* Config);
104 static Clock_Ip_PllStatusReturnType Clock_Ip_CallbackPllEmptyComplete(Clock_Ip_NameType PllName);
105 static void Clock_Ip_CallbackPllEmptyDisable(Clock_Ip_NameType PllName);
106 
107 #ifdef CLOCK_IP_PLLDIG_RDIV_MFI_MFN_SDMEN_SSCGBYP_SPREADCTL_STEPNO_STEPSIZE
108 static void Clock_Ip_ResetPlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize(Clock_Ip_PllConfigType const* Config);
109 static void Clock_Ip_SetPlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize(Clock_Ip_PllConfigType const* Config);
110 static Clock_Ip_PllStatusReturnType Clock_Ip_CompletePlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize(Clock_Ip_NameType PllName);
111 static void Clock_Ip_EnablePlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize(Clock_Ip_PllConfigType const* Config);
112 #endif
113 #ifdef CLOCK_IP_PLLDIG_RDIV_MFI_MFN_SDMEN
114 static void Clock_Ip_ResetPlldigRdivMfiMfnSdmen(Clock_Ip_PllConfigType const* Config);
115 static void Clock_Ip_SetPlldigRdivMfiMfnSdmen(Clock_Ip_PllConfigType const* Config);
116 static Clock_Ip_PllStatusReturnType Clock_Ip_CompletePlldigRdivMfiMfnSdmen(Clock_Ip_NameType PllName);
117 static void Clock_Ip_EnablePlldigRdivMfiMfnSdmen(Clock_Ip_PllConfigType const* Config);
118 #endif
119 #ifdef CLOCK_IP_LFASTPLL_ENABLE
120 static void Clock_Ip_ResetLfastPLL(Clock_Ip_PllConfigType const* Config);
121 static void Clock_Ip_SetLfastPLL(Clock_Ip_PllConfigType const* Config);
122 static Clock_Ip_PllStatusReturnType Clock_Ip_CompleteLfastPLL(Clock_Ip_NameType PllName);
123 static void Clock_Ip_EnableLfastPLL(Clock_Ip_PllConfigType const* Config);
124 #endif
125 
126 
127 /* Clock stop section code */
128 #define MCU_STOP_SEC_CODE
129 
130 #include "Mcu_MemMap.h"
131 
132 /*==================================================================================================
133 *                                         LOCAL FUNCTIONS
134 ==================================================================================================*/
135 
136 #define MCU_START_SEC_CODE
137 /* Clock start section code */
138 
139 #include "Mcu_MemMap.h"
140 
141 
Clock_Ip_CallbackPllEmpty(Clock_Ip_PllConfigType const * Config)142 static void Clock_Ip_CallbackPllEmpty(Clock_Ip_PllConfigType const* Config)
143 {
144     (void)Config;
145     /* No implementation */
146 }
Clock_Ip_CallbackPllEmptyComplete(Clock_Ip_NameType PllName)147 static Clock_Ip_PllStatusReturnType Clock_Ip_CallbackPllEmptyComplete(Clock_Ip_NameType PllName)
148 {
149     (void)PllName;
150     /* No implementation */
151     return STATUS_PLL_NOT_ENABLED;
152 }
Clock_Ip_CallbackPllEmptyDisable(Clock_Ip_NameType PllName)153 static void Clock_Ip_CallbackPllEmptyDisable(Clock_Ip_NameType PllName)
154 {
155     (void)PllName;
156     /* No implementation */
157 }
158 
159 
160 /* Pll with frequency modulation */
161 #ifdef CLOCK_IP_PLLDIG_RDIV_MFI_MFN_SDMEN_SSCGBYP_SPREADCTL_STEPNO_STEPSIZE
162 #ifndef CLOCK_IP_FIRC_PLL_REFERENCE
163     #define CLOCK_IP_FIRC_PLL_REFERENCE 0U
164 #endif
165 #ifndef CLOCK_IP_FXOSC_PLL_REFERENCE
166     #define CLOCK_IP_FXOSC_PLL_REFERENCE 1U
167 #endif
Clock_Ip_ResetPlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize(Clock_Ip_PllConfigType const * Config)168 static void Clock_Ip_ResetPlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize(Clock_Ip_PllConfigType const* Config)
169 {
170     uint32 Instance = Clock_Ip_au8ClockFeatures[Config->Name][CLOCK_IP_MODULE_INSTANCE];
171     uint8 DividerIndex;
172 
173     /* Disable output dividers */
174     for (DividerIndex = 0U; DividerIndex < Clock_Ip_apxPll[Instance].DivsNo; DividerIndex++)
175     {
176         Clock_Ip_apxPll[Instance].PllInstance->PLLODIV[DividerIndex] &= ~PLLDIG_PLLODIV_DE_MASK;
177     }
178 
179     /* Power down PLL */
180     Clock_Ip_apxPll[Instance].PllInstance->PLLCR |= PLLDIG_PLLCR_PLLPD_MASK;
181 }
Clock_Ip_SetPlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize(Clock_Ip_PllConfigType const * Config)182 static void Clock_Ip_SetPlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize(Clock_Ip_PllConfigType const* Config)
183 {
184     uint32 Instance = Clock_Ip_au8ClockFeatures[Config->Name][CLOCK_IP_MODULE_INSTANCE];
185     uint32 Value;
186 
187     if (Config->Enable != 0U)
188     {
189         /* Name of the input reference clock */
190         switch(Config->InputReference)
191         {
192             case FIRC_CLK:
193                 /* Select input reference. */
194                 Clock_Ip_apxPll[Instance].PllInstance->PLLCLKMUX = PLLDIG_PLLCLKMUX_REFCLKSEL(CLOCK_IP_FIRC_PLL_REFERENCE);
195                 break;
196             case FXOSC_CLK:
197                 /* Select input reference. */
198                 Clock_Ip_apxPll[Instance].PllInstance->PLLCLKMUX = PLLDIG_PLLCLKMUX_REFCLKSEL(CLOCK_IP_FXOSC_PLL_REFERENCE);
199                 break;
200             default:
201                 /* Command is not implemented on this platform */
202                 break;
203         }
204 
205         /* Configure PLL: predivider and multiplier */
206         Value = (uint32) (PLLDIG_PLLDV_RDIV(Config->Predivider)   |
207                             PLLDIG_PLLDV_MFI(Config->MulFactorDiv));
208         Clock_Ip_apxPll[Instance].PllInstance->PLLDV = Value;
209         /* Set numerator fractional loop divider and sigma delta modulation */
210         Value = Clock_Ip_apxPll[Instance].PllInstance->PLLFD;
211         Value &= ~(PLLDIG_PLLFD_MFN_MASK | PLLDIG_PLLFD_SDMEN_MASK);
212         Value |=  PLLDIG_PLLFD_MFN(Config->NumeratorFracLoopDiv);
213         Value |= PLLDIG_PLLFD_SDMEN(Config->SigmaDelta);
214         Clock_Ip_apxPll[Instance].PllInstance->PLLFD = Value;
215         /* Configure modulation */
216         Value = (uint32) (PLLDIG_PLLFM_SSCGBYP(Config->FrequencyModulationBypass)               |
217                           PLLDIG_PLLFM_SPREADCTL(Config->ModulationType)                        |
218                           PLLDIG_PLLFM_STEPNO(Config->IncrementStep)                            |
219                           PLLDIG_PLLFM_STEPSIZE(Config->ModulationPeriod));
220         Clock_Ip_apxPll[Instance].PllInstance->PLLFM = Value;
221     }
222 }
223 
Clock_Ip_CompletePlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize(Clock_Ip_NameType PllName)224 static Clock_Ip_PllStatusReturnType Clock_Ip_CompletePlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize(Clock_Ip_NameType PllName)
225 {
226     Clock_Ip_PllStatusReturnType PllStatus = STATUS_PLL_LOCKED;
227 
228     boolean TimeoutOccurred = FALSE;
229     uint32 StartTime;
230     uint32 ElapsedTime;
231     uint32 TimeoutTicks;
232     uint32 PllLockStatus;
233     uint32 Instance = Clock_Ip_au8ClockFeatures[PllName][CLOCK_IP_MODULE_INSTANCE];
234 
235     if (0U == (Clock_Ip_apxPll[Instance].PllInstance->PLLCR & PLLDIG_PLLCR_PLLPD_MASK))
236     {
237         Clock_Ip_StartTimeout(&StartTime, &ElapsedTime, &TimeoutTicks, CLOCK_IP_TIMEOUT_VALUE_US);
238         /* Wait until this pll is locked */
239         do
240         {
241             PllLockStatus = ((Clock_Ip_apxPll[Instance].PllInstance->PLLSR & PLLDIG_PLLSR_LOCK_MASK) >> PLLDIG_PLLSR_LOCK_SHIFT);
242             TimeoutOccurred = Clock_Ip_TimeoutExpired(&StartTime, &ElapsedTime, TimeoutTicks);
243         }
244         while ((0U == PllLockStatus) && (FALSE == TimeoutOccurred));
245 
246         if (TRUE == TimeoutOccurred)
247         {
248             PllStatus = STATUS_PLL_UNLOCKED;
249         }
250     }
251     else
252     {
253         PllStatus = STATUS_PLL_NOT_ENABLED;
254     }
255     return PllStatus;
256 }
Clock_Ip_EnablePlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize(Clock_Ip_PllConfigType const * Config)257 static void Clock_Ip_EnablePlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize(Clock_Ip_PllConfigType const* Config)
258 {
259     uint32 Instance = Clock_Ip_au8ClockFeatures[Config->Name][CLOCK_IP_MODULE_INSTANCE];
260 
261     /* Configure PLL. */
262     if (1U == Config->Enable)
263     {
264         /* Send command to enable PLL device. */
265         Clock_Ip_apxPll[Instance].PllInstance->PLLCR &= ~PLLDIG_PLLCR_PLLPD_MASK;
266     }
267 }
268 #endif
269 
270 /* Pll without frequency modulation */
271 #ifdef CLOCK_IP_PLLDIG_RDIV_MFI_MFN_SDMEN
272 #ifndef CLOCK_IP_FIRC_PLL_REFERENCE
273     #define CLOCK_IP_FIRC_PLL_REFERENCE 0U
274 #endif
275 #ifndef CLOCK_IP_FXOSC_PLL_REFERENCE
276     #define CLOCK_IP_FXOSC_PLL_REFERENCE 1U
277 #endif
Clock_Ip_ResetPlldigRdivMfiMfnSdmen(Clock_Ip_PllConfigType const * Config)278 static void Clock_Ip_ResetPlldigRdivMfiMfnSdmen(Clock_Ip_PllConfigType const* Config)
279 {
280     uint32 Instance = Clock_Ip_au8ClockFeatures[Config->Name][CLOCK_IP_MODULE_INSTANCE];
281     uint8 DividerIndex;
282 
283     /* Disable output dividers */
284     for (DividerIndex = 0U; DividerIndex < Clock_Ip_apxPll[Instance].DivsNo; DividerIndex++)
285     {
286         Clock_Ip_apxPll[Instance].PllInstance->PLLODIV[DividerIndex] &= ~PLLDIG_PLLODIV_DE_MASK;
287     }
288 
289     /* Power down PLL */
290     Clock_Ip_apxPll[Instance].PllInstance->PLLCR |= PLLDIG_PLLCR_PLLPD_MASK;
291 }
Clock_Ip_SetPlldigRdivMfiMfnSdmen(Clock_Ip_PllConfigType const * Config)292 static void Clock_Ip_SetPlldigRdivMfiMfnSdmen(Clock_Ip_PllConfigType const* Config)
293 {
294     uint32 Instance = Clock_Ip_au8ClockFeatures[Config->Name][CLOCK_IP_MODULE_INSTANCE];
295     uint32 Value;
296 
297     if (Config->Enable != 0U)
298     {
299         /* Name of the input reference clock */
300         switch(Config->InputReference)
301         {
302             case FIRC_CLK:
303                 /* Select input reference. */
304                 Clock_Ip_apxPll[Instance].PllInstance->PLLCLKMUX = PLLDIG_PLLCLKMUX_REFCLKSEL(CLOCK_IP_FIRC_PLL_REFERENCE);
305                 break;
306             case FXOSC_CLK:
307                 /* Select input reference. */
308                 Clock_Ip_apxPll[Instance].PllInstance->PLLCLKMUX = PLLDIG_PLLCLKMUX_REFCLKSEL(CLOCK_IP_FXOSC_PLL_REFERENCE);
309                 break;
310             default:
311                 /* Command is not implemented on this platform */
312                 break;
313         }
314 
315         /* Configure PLL: predivider and multiplier */
316         Value = (uint32) (PLLDIG_PLLDV_RDIV(Config->Predivider)   |
317                             PLLDIG_PLLDV_MFI(Config->MulFactorDiv));
318         Clock_Ip_apxPll[Instance].PllInstance->PLLDV = Value;
319         /* Set numerator fractional loop divider and sigma delta modulation */
320         Value = Clock_Ip_apxPll[Instance].PllInstance->PLLFD;
321         Value &= ~(PLLDIG_PLLFD_MFN_MASK | PLLDIG_PLLFD_SDMEN_MASK);
322         Value |=  PLLDIG_PLLFD_MFN(Config->NumeratorFracLoopDiv);
323         Value |= PLLDIG_PLLFD_SDMEN(Config->SigmaDelta);
324         Clock_Ip_apxPll[Instance].PllInstance->PLLFD = Value;
325     }
326 }
Clock_Ip_CompletePlldigRdivMfiMfnSdmen(Clock_Ip_NameType PllName)327 static Clock_Ip_PllStatusReturnType Clock_Ip_CompletePlldigRdivMfiMfnSdmen(Clock_Ip_NameType PllName)
328 {
329     Clock_Ip_PllStatusReturnType PllStatus = STATUS_PLL_LOCKED;
330     boolean TimeoutOccurred = FALSE;
331     uint32 StartTime;
332     uint32 ElapsedTime;
333     uint32 TimeoutTicks;
334     uint32 PllLockStatus;
335     uint32 Instance = Clock_Ip_au8ClockFeatures[PllName][CLOCK_IP_MODULE_INSTANCE];
336 
337     if (0U == (Clock_Ip_apxPll[Instance].PllInstance->PLLCR & PLLDIG_PLLCR_PLLPD_MASK))
338     {
339         Clock_Ip_StartTimeout(&StartTime, &ElapsedTime, &TimeoutTicks, CLOCK_IP_TIMEOUT_VALUE_US);
340         /* Wait until this pll is locked */
341         do
342         {
343             PllLockStatus = ((Clock_Ip_apxPll[Instance].PllInstance->PLLSR & PLLDIG_PLLSR_LOCK_MASK) >> PLLDIG_PLLSR_LOCK_SHIFT);
344             TimeoutOccurred = Clock_Ip_TimeoutExpired(&StartTime, &ElapsedTime, TimeoutTicks);
345         }
346         while ((0U == PllLockStatus) && (FALSE == TimeoutOccurred));
347 
348         if(TRUE == TimeoutOccurred)
349         {
350             PllStatus = STATUS_PLL_UNLOCKED;
351         }
352     }
353     else
354     {
355         PllStatus = STATUS_PLL_NOT_ENABLED;
356     }
357     return PllStatus;
358 }
Clock_Ip_EnablePlldigRdivMfiMfnSdmen(Clock_Ip_PllConfigType const * Config)359 static void Clock_Ip_EnablePlldigRdivMfiMfnSdmen(Clock_Ip_PllConfigType const* Config)
360 {
361     uint32 Instance = Clock_Ip_au8ClockFeatures[Config->Name][CLOCK_IP_MODULE_INSTANCE];
362 
363     /* Configure PLL. */
364     if (1U == Config->Enable)
365     {
366         /* Send command to enable PLL device. */
367         Clock_Ip_apxPll[Instance].PllInstance->PLLCR &= ~PLLDIG_PLLCR_PLLPD_MASK;
368     }
369 }
370 #endif
371 
372 /*==================================================================================================
373 *                                        GLOBAL FUNCTIONS
374 ==================================================================================================*/
375 
376 
377 
378 
379 #ifdef CLOCK_IP_LFASTPLL_ENABLE
Clock_Ip_ResetLfastPLL(Clock_Ip_PllConfigType const * Config)380 static void Clock_Ip_ResetLfastPLL(Clock_Ip_PllConfigType const* Config)
381 {
382     (void)Config;
383     uint32 Instance = Clock_Ip_au8ClockFeatures[Config->Name][CLOCK_IP_MODULE_INSTANCE];
384 
385     /* Power down PLL */
386     Clock_Ip_apxLfastPll[Instance].PllInstance->PLLCR |= LFAST_PLLCR_SWPOFF(1);
387     /* Accept write register LFAST */
388     Clock_Ip_apxLfastPll[Instance].PllInstance->MCR &= (~((uint32)LFAST_MCR_DRFEN_MASK));
389     /* Clear FBDIV bit field */
390     Clock_Ip_apxLfastPll[Instance].PllInstance->PLLCR &= (~((uint32)LFAST_PLLCR_FBDIV_MASK));
391     /* Clear PREDIV bit field */
392     Clock_Ip_apxLfastPll[Instance].PllInstance->PLLCR &= (~((uint32)LFAST_PLLCR_PREDIV_MASK));
393     /* Clear FDIVEN bit field */
394     Clock_Ip_apxLfastPll[Instance].PllInstance->PLLCR &= (~((uint32)LFAST_PLLCR_FDIVEN_MASK));
395 }
Clock_Ip_SetLfastPLL(Clock_Ip_PllConfigType const * Config)396 static void Clock_Ip_SetLfastPLL(Clock_Ip_PllConfigType const* Config)
397 {
398     uint32 Instance = Clock_Ip_au8ClockFeatures[Config->Name][CLOCK_IP_MODULE_INSTANCE];
399 
400     /* Configure LFAST PLL. */
401     if (1U == Config->Enable)
402     {
403         /* Accept write register LFAST */
404         Clock_Ip_apxLfastPll[Instance].PllInstance->MCR &= (~((uint32)LFAST_MCR_DRFEN_MASK));
405 
406         Clock_Ip_apxLfastPll[Instance].PllInstance->PLLCR &= (~((uint32)LFAST_PLLCR_FBDIV_MASK));
407         Clock_Ip_apxLfastPll[Instance].PllInstance->PLLCR |= LFAST_PLLCR_FBDIV(Config->MulFactorDiv);
408 
409         Clock_Ip_apxLfastPll[Instance].PllInstance->PLLCR &= (~((uint32)LFAST_PLLCR_PREDIV_MASK));
410         Clock_Ip_apxLfastPll[Instance].PllInstance->PLLCR |= LFAST_PLLCR_PREDIV((uint8)(Config->Predivider - 1U));
411 
412         Clock_Ip_apxLfastPll[Instance].PllInstance->PLLCR &= (~((uint32)LFAST_PLLCR_FDIVEN_MASK));
413         Clock_Ip_apxLfastPll[Instance].PllInstance->PLLCR |= LFAST_PLLCR_FDIVEN(Config->SigmaDelta);
414 
415     }
416     else
417     {
418         (void)Instance;
419     }
420 }
Clock_Ip_CompleteLfastPLL(Clock_Ip_NameType PllName)421 static Clock_Ip_PllStatusReturnType Clock_Ip_CompleteLfastPLL(Clock_Ip_NameType PllName)
422 {
423     Clock_Ip_PllStatusReturnType PllStatus = STATUS_PLL_LOCKED;
424     boolean TimeoutOccurred = FALSE;
425     uint32 StartTime;
426     uint32 ElapsedTime;
427     uint32 TimeoutTicks;
428     uint32 PllLockStatus;
429     uint32 PllEnableStatus;
430     uint32 Instance = Clock_Ip_au8ClockFeatures[PllName][CLOCK_IP_MODULE_INSTANCE];
431 
432     Clock_Ip_StartTimeout(&StartTime, &ElapsedTime, &TimeoutTicks, CLOCK_IP_TIMEOUT_VALUE_US);
433     /* Wait until this pll is enable */
434     do
435     {
436         PllEnableStatus = ((Clock_Ip_apxLfastPll[Instance].PllInstance->PLLLSR & LFAST_PLLLSR_PLLDIS_MASK) >> LFAST_PLLLSR_PLLDIS_SHIFT);
437         TimeoutOccurred = Clock_Ip_TimeoutExpired(&StartTime, &ElapsedTime, TimeoutTicks);
438     }
439     while ((0U != PllEnableStatus) && (FALSE == TimeoutOccurred));
440     if(TRUE == TimeoutOccurred)
441     {
442         PllStatus = STATUS_PLL_NOT_ENABLED;
443     }
444     else
445     {
446         Clock_Ip_StartTimeout(&StartTime, &ElapsedTime, &TimeoutTicks, CLOCK_IP_TIMEOUT_VALUE_US);
447         /* Wait until this pll is locked */
448         do
449         {
450             PllLockStatus = ((Clock_Ip_apxLfastPll[Instance].PllInstance->PLLLSR & LFAST_PLLLSR_PLDCR_MASK) >> LFAST_PLLLSR_PLDCR_SHIFT);
451             TimeoutOccurred = Clock_Ip_TimeoutExpired(&StartTime, &ElapsedTime, TimeoutTicks);
452         }
453         while ((1U != PllLockStatus) && (FALSE == TimeoutOccurred));
454 
455         if(TRUE == TimeoutOccurred)
456         {
457             PllStatus = STATUS_PLL_UNLOCKED;
458         }
459     }
460 
461     return PllStatus;
462 }
Clock_Ip_EnableLfastPLL(Clock_Ip_PllConfigType const * Config)463 static void Clock_Ip_EnableLfastPLL(Clock_Ip_PllConfigType const* Config)
464 {
465     uint32 Instance = Clock_Ip_au8ClockFeatures[Config->Name][CLOCK_IP_MODULE_INSTANCE];
466 
467     /* Configure LFAST PLL. */
468     if (1U == Config->Enable)
469     {
470         /* Enable LFAST PLL */
471         Clock_Ip_apxLfastPll[Instance].PllInstance->PLLCR |= LFAST_PLLCR_SWPON(1);
472     }
473     else
474     {
475         (void)Instance;
476     }
477 }
478 #endif
479 
480 
481 
482 
483 
484 /* Clock stop section code */
485 #define MCU_STOP_SEC_CODE
486 
487 #include "Mcu_MemMap.h"
488 
489 /*==================================================================================================
490 *                                        GLOBAL CONSTANTS
491 ==================================================================================================*/
492 /* Clock start constant section data */
493 #define MCU_START_SEC_CONST_UNSPECIFIED
494 
495 #include "Mcu_MemMap.h"
496 const Clock_Ip_PllCallbackType Clock_Ip_axPllCallbacks[CLOCK_IP_PLL_CALLBACKS_COUNT] =
497 {
498     {
499         Clock_Ip_CallbackPllEmpty,            /* Reset */
500         Clock_Ip_CallbackPllEmpty,            /* Set */
501         Clock_Ip_CallbackPllEmptyComplete,    /* Complete */
502         Clock_Ip_CallbackPllEmpty,            /* Enable */
503         Clock_Ip_CallbackPllEmptyDisable,     /* Disable */
504     },
505     /* Pll with frequency modulation */
506 #ifdef CLOCK_IP_PLLDIG_RDIV_MFI_MFN_SDMEN_SSCGBYP_SPREADCTL_STEPNO_STEPSIZE
507     {
508         Clock_Ip_ResetPlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize,              /* Reset */
509         Clock_Ip_SetPlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize,                /* Set */
510         Clock_Ip_CompletePlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize,           /* Complete */
511         Clock_Ip_EnablePlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize,             /* Enable */
512         Clock_Ip_CallbackPllEmptyDisable,                                               /* Disable */
513     },
514 #endif
515     /* Pll without frequency modulation */
516 #ifdef CLOCK_IP_PLLDIG_RDIV_MFI_MFN_SDMEN
517     {
518         Clock_Ip_ResetPlldigRdivMfiMfnSdmen,          /* Reset */
519         Clock_Ip_SetPlldigRdivMfiMfnSdmen,            /* Set */
520         Clock_Ip_CompletePlldigRdivMfiMfnSdmen,       /* Complete */
521         Clock_Ip_EnablePlldigRdivMfiMfnSdmen,         /* Enable */
522         Clock_Ip_CallbackPllEmptyDisable,            /* Disable */
523     },
524 #endif
525 #ifdef CLOCK_IP_LFASTPLL_ENABLE
526     {
527         Clock_Ip_ResetLfastPLL,                                      /* Reset */
528         Clock_Ip_SetLfastPLL,                                        /* Set */
529         Clock_Ip_CompleteLfastPLL,                                   /* Complete */
530         Clock_Ip_EnableLfastPLL,                                     /* Enable */
531         Clock_Ip_CallbackPllEmptyDisable,                            /* Disable */
532     },
533 #endif
534 };
535 
536 
537 /* Clock stop constant section data */
538 #define MCU_STOP_SEC_CONST_UNSPECIFIED
539 
540 #include "Mcu_MemMap.h"
541 
542 #ifdef __cplusplus
543 }
544 #endif
545 
546 /** @} */
547 
548