1 /*
2  * Copyright 2021-2022 NXP
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 /**
7 *   @file       Clock_Ip_Specific.c
8 *   @version    0.9.0
9 *
10 *   @brief   CLOCK driver implementations.
11 *   @details CLOCK driver implementations.
12 *
13 *   @addtogroup CLOCK_DRIVER Clock Ip Driver
14 *   @{
15 */
16 
17 #ifdef __cplusplus
18 extern "C"{
19 #endif
20 
21 
22 /*==================================================================================================
23 *                                          INCLUDE FILES
24 * 1) system and project includes
25 * 2) needed interfaces from external units
26 * 3) internal and external interfaces from this unit
27 ==================================================================================================*/
28 
29 
30 
31 #include "Clock_Ip_Private.h"
32 
33 #if (defined(CLOCK_IP_ENABLE_USER_MODE_SUPPORT))
34   #if (STD_ON == CLOCK_IP_ENABLE_USER_MODE_SUPPORT)
35     #define USER_MODE_REG_PROT_ENABLED      (STD_ON)
36     #include "RegLockMacros.h"
37   #endif
38 #endif /* CLOCK_IP_ENABLE_USER_MODE_SUPPORT */
39 
40 /*==================================================================================================
41                                SOURCE FILE VERSION INFORMATION
42 ==================================================================================================*/
43 #define CLOCK_IP_SPECIFIC_VENDOR_ID_C                      43
44 #define CLOCK_IP_SPECIFIC_AR_RELEASE_MAJOR_VERSION_C       4
45 #define CLOCK_IP_SPECIFIC_AR_RELEASE_MINOR_VERSION_C       7
46 #define CLOCK_IP_SPECIFIC_AR_RELEASE_REVISION_VERSION_C    0
47 #define CLOCK_IP_SPECIFIC_SW_MAJOR_VERSION_C               0
48 #define CLOCK_IP_SPECIFIC_SW_MINOR_VERSION_C               9
49 #define CLOCK_IP_SPECIFIC_SW_PATCH_VERSION_C               0
50 
51 /*==================================================================================================
52 *                                     FILE VERSION CHECKS
53 ==================================================================================================*/
54 /* Check if Clock_Ip_Specific.c file and Clock_Ip_Private.h file are of the same vendor */
55 #if (CLOCK_IP_SPECIFIC_VENDOR_ID_C != CLOCK_IP_PRIVATE_VENDOR_ID)
56     #error "Clock_Ip_Specific.c and Clock_Ip_Private.h have different vendor ids"
57 #endif
58 
59 /* Check if Clock_Ip_Specific.c file and Clock_Ip_Private.h file are of the same Autosar version */
60 #if ((CLOCK_IP_SPECIFIC_AR_RELEASE_MAJOR_VERSION_C != CLOCK_IP_PRIVATE_AR_RELEASE_MAJOR_VERSION) || \
61      (CLOCK_IP_SPECIFIC_AR_RELEASE_MINOR_VERSION_C != CLOCK_IP_PRIVATE_AR_RELEASE_MINOR_VERSION) || \
62      (CLOCK_IP_SPECIFIC_AR_RELEASE_REVISION_VERSION_C != CLOCK_IP_PRIVATE_AR_RELEASE_REVISION_VERSION) \
63     )
64     #error "AutoSar Version Numbers of Clock_Ip_Specific.c and Clock_Ip_Private.h are different"
65 #endif
66 
67 /* Check if Clock_Ip_Specific.c file and Clock_Ip_Private.h file are of the same Software version */
68 #if ((CLOCK_IP_SPECIFIC_SW_MAJOR_VERSION_C != CLOCK_IP_PRIVATE_SW_MAJOR_VERSION) || \
69      (CLOCK_IP_SPECIFIC_SW_MINOR_VERSION_C != CLOCK_IP_PRIVATE_SW_MINOR_VERSION) || \
70      (CLOCK_IP_SPECIFIC_SW_PATCH_VERSION_C != CLOCK_IP_PRIVATE_SW_PATCH_VERSION) \
71     )
72     #error "Software Version Numbers of Clock_Ip_Specific.c and Clock_Ip_Private.h are different"
73 #endif
74 
75 #if (defined(CLOCK_IP_ENABLE_USER_MODE_SUPPORT))
76   #if (STD_ON == CLOCK_IP_ENABLE_USER_MODE_SUPPORT)
77     #ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
78     /* Check if Clock_Ip_Specific.c file and RegLockMacros.h file are of the same Autosar version */
79     #if ((CLOCK_IP_SPECIFIC_AR_RELEASE_MAJOR_VERSION    != REGLOCKMACROS_AR_RELEASE_MAJOR_VERSION) || \
80         (CLOCK_IP_SPECIFIC_AR_RELEASE_MINOR_VERSION    != REGLOCKMACROS_AR_RELEASE_MINOR_VERSION))
81         #error "AutoSar Version Numbers of Clock_Ip_Specific.c and RegLockMacros.h are different"
82     #endif
83     #endif
84   #endif
85 #endif /* CLOCK_IP_ENABLE_USER_MODE_SUPPORT */
86 
87 
88 /*==================================================================================================
89                           LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS)
90 ==================================================================================================*/
91 
92 /*==================================================================================================
93 *                                       LOCAL MACROS
94 ==================================================================================================*/
95 
96 #define DFS_DVPORT      (DFS_DVPORT_MFN(0u) | DFS_DVPORT_MFI(1U))
97 #define DFS_PORT_RESET  (DFS_PORTRESET_RESET0_MASK | DFS_PORTRESET_RESET1_MASK | DFS_PORTRESET_RESET2_MASK | DFS_PORTRESET_RESET3_MASK | DFS_PORTRESET_RESET4_MASK | DFS_PORTRESET_RESET5_MASK)
98 
99 #define RTU0_CORE_CLK_MAX_FREQUENCY 900000000U
100 #define RTU0_CORE_CLK_THRESHOLD0_FREQUENCY (RTU0_CORE_CLK_MAX_FREQUENCY>>2U)
101 #define RTU0_CORE_CLK_THRESHOLD1_FREQUENCY (RTU0_CORE_CLK_THRESHOLD0_FREQUENCY*(2U))
102 #define RTU0_CORE_CLK_THRESHOLD2_FREQUENCY (RTU0_CORE_CLK_THRESHOLD0_FREQUENCY*(3U))
103 
104 #define RTU1_CORE_CLK_MAX_FREQUENCY 900000000U
105 #define RTU1_CORE_CLK_THRESHOLD0_FREQUENCY (RTU1_CORE_CLK_MAX_FREQUENCY>>2U)
106 #define RTU1_CORE_CLK_THRESHOLD1_FREQUENCY (RTU1_CORE_CLK_THRESHOLD0_FREQUENCY*(2U))
107 #define RTU1_CORE_CLK_THRESHOLD2_FREQUENCY (RTU1_CORE_CLK_THRESHOLD0_FREQUENCY*(3U))
108 
109 #define SMU_M33_CORE_CLK_MAX_FREQUENCY 400000000U
110 #define SMU_M33_CORE_CLK_THRESHOLD0_FREQUENCY (SMU_M33_CORE_CLK_MAX_FREQUENCY>>2U)
111 #define SMU_M33_CORE_CLK_THRESHOLD1_FREQUENCY (SMU_M33_CORE_CLK_THRESHOLD0_FREQUENCY*(2U))
112 #define SMU_M33_CORE_CLK_THRESHOLD2_FREQUENCY (SMU_M33_CORE_CLK_THRESHOLD0_FREQUENCY*(3U))
113 
114 #define CE_M33_CORE_CLK_MAX_FREQUENCY 405000000U
115 #define CE_M33_CORE_CLK_THRESHOLD0_FREQUENCY (CE_M33_CORE_CLK_MAX_FREQUENCY>>2U)
116 #define CE_M33_CORE_CLK_THRESHOLD1_FREQUENCY (CE_M33_CORE_CLK_THRESHOLD0_FREQUENCY*(2U))
117 #define CE_M33_CORE_CLK_THRESHOLD2_FREQUENCY (CE_M33_CORE_CLK_THRESHOLD0_FREQUENCY*(3U))
118 
119 
120 /*==================================================================================================
121                                        LOCAL CONSTANTS
122 ==================================================================================================*/
123 
124 /*==================================================================================================
125                                        LOCAL VARIABLES
126 ==================================================================================================*/
127 
128 
129 /*==================================================================================================
130                                        GLOBAL CONSTANTS
131 ==================================================================================================*/
132 
133 
134 /*==================================================================================================
135                                        GLOBAL VARIABLES
136 ==================================================================================================*/
137 
138 
139 /* Clock start section code */
140 #define MCU_START_SEC_CODE
141 #include "Mcu_MemMap.h"
142 
143 #ifdef CLOCK_IP_HAS_RAM_WAIT_STATES
144 
145 void SRAMController_SetRamIWS(uint32 SmuM33CoreClk_IwsSetting, uint32 Rtu0CoreClk_IwsSetting, uint32 Rtu1CoreClk_IwsSetting, uint32 CeM33CoreClk_IwsSetting);
146 
147 /* Calculate ram wait states value */
Clock_Ip_GetIwsSetting(uint32 ConfiguredCoreClockFrequnecy,uint32 Threshold0,uint32 Threshold1,uint32 Threshold2)148 static uint32 Clock_Ip_GetIwsSetting(uint32 ConfiguredCoreClockFrequnecy, uint32 Threshold0, uint32 Threshold1, uint32 Threshold2)
149 {
150     uint32 IwsSetting = 0U;
151 
152     if (ConfiguredCoreClockFrequnecy >= Threshold2)
153     {
154         IwsSetting = 3U;
155     }
156     else if (ConfiguredCoreClockFrequnecy >= Threshold1)
157     {
158         IwsSetting = 2U;
159     }
160     else if (ConfiguredCoreClockFrequnecy >= Threshold0)
161     {
162         IwsSetting = 1U;
163     }
164     else
165     {
166         /* Nothing else to be done. */
167     }
168 
169     return IwsSetting;
170 }
171 
172 
173 /* Function set ram wait states */
Clock_Ip_SetRamWaitStates(void)174 void Clock_Ip_SetRamWaitStates(void)
175 {
176    /* Process configured frequency values */
177     uint32 Rtu0CoreClk_IwsSetting = 0U;
178     uint32 Rtu0CoreClk_ConfiguredFrequency = 0U;
179 
180     uint32 Rtu1CoreClk_IwsSetting = 0U;
181     uint32 Rtu1CoreClk_ConfiguredFrequency = 0U;
182 
183     uint32 SmuM33CoreClk_IwsSetting = 0U;
184     uint32 SmuM33CoreClk_ConfiguredFrequency = 0U;
185 
186     uint32 CeM33CoreClk_IwsSetting = 0U;
187     uint32 CeM33CoreClk_ConfiguredFrequency = 0U;
188 
189 #if defined(CLOCK_IP_HAS_RTU0_CORE_CLK)
190     Rtu0CoreClk_ConfiguredFrequency = Clock_Ip_pxConfig->ConfiguredFrequencies[Clock_Ip_FreqIds[RTU0_CORE_CLK]].ConfiguredFrequencyValue;
191 #endif
192 #if defined(CLOCK_IP_HAS_RTU1_CORE_CLK)
193     Rtu1CoreClk_ConfiguredFrequency = Clock_Ip_pxConfig->ConfiguredFrequencies[Clock_Ip_FreqIds[RTU1_CORE_CLK]].ConfiguredFrequencyValue;
194 #endif
195 #if defined(CLOCK_IP_HAS_SMU_M33_CORE_CLK)
196     SmuM33CoreClk_ConfiguredFrequency = Clock_Ip_pxConfig->ConfiguredFrequencies[Clock_Ip_FreqIds[SMU_M33_CORE_CLK]].ConfiguredFrequencyValue;
197 #endif
198 #if defined(CLOCK_IP_HAS_CE_M33_CORE_CLK)
199     CeM33CoreClk_ConfiguredFrequency = Clock_Ip_pxConfig->ConfiguredFrequencies[Clock_Ip_FreqIds[CE_M33_CORE_CLK]].ConfiguredFrequencyValue;
200 #endif
201 
202 #if (defined(CLOCK_IP_DEV_ERROR_DETECT) && (CLOCK_IP_DEV_ERROR_DETECT == STD_ON))
203 #if defined(CLOCK_IP_HAS_RTU0_CORE_CLK)
204     CLOCK_IP_DEV_ASSERT(Rtu0CoreClk_ConfiguredFrequency != 0U);
205 #endif
206 #if defined(CLOCK_IP_HAS_RTU1_CORE_CLK)
207     CLOCK_IP_DEV_ASSERT(Rtu1CoreClk_ConfiguredFrequency != 0U);
208 #endif
209 #if defined(CLOCK_IP_HAS_SMU_M33_CORE_CLK)
210     CLOCK_IP_DEV_ASSERT(SmuM33CoreClk_ConfiguredFrequency != 0U);
211 #endif
212 #if defined(CLOCK_IP_HAS_CE_M33_CORE_CLK)
213     CLOCK_IP_DEV_ASSERT(CeM33CoreClk_ConfiguredFrequency != 0U);
214 #endif
215 #endif
216 
217     SmuM33CoreClk_IwsSetting = Clock_Ip_GetIwsSetting(SmuM33CoreClk_ConfiguredFrequency, SMU_M33_CORE_CLK_THRESHOLD0_FREQUENCY, SMU_M33_CORE_CLK_THRESHOLD1_FREQUENCY, SMU_M33_CORE_CLK_THRESHOLD2_FREQUENCY);
218     Rtu0CoreClk_IwsSetting = Clock_Ip_GetIwsSetting(Rtu0CoreClk_ConfiguredFrequency, RTU0_CORE_CLK_THRESHOLD0_FREQUENCY, RTU0_CORE_CLK_THRESHOLD1_FREQUENCY, RTU0_CORE_CLK_THRESHOLD2_FREQUENCY);
219     Rtu1CoreClk_IwsSetting = Clock_Ip_GetIwsSetting(Rtu1CoreClk_ConfiguredFrequency, RTU1_CORE_CLK_THRESHOLD0_FREQUENCY, RTU1_CORE_CLK_THRESHOLD1_FREQUENCY, RTU1_CORE_CLK_THRESHOLD2_FREQUENCY);
220     CeM33CoreClk_IwsSetting = Clock_Ip_GetIwsSetting(CeM33CoreClk_ConfiguredFrequency, CE_M33_CORE_CLK_THRESHOLD0_FREQUENCY, CE_M33_CORE_CLK_THRESHOLD1_FREQUENCY, CE_M33_CORE_CLK_THRESHOLD2_FREQUENCY);
221 
222     #ifdef CLOCK_IP_ENABLE_USER_MODE_SUPPORT
223         #if (STD_ON == CLOCK_IP_ENABLE_USER_MODE_SUPPORT)
224             OsIf_Trusted_Call4params(SRAMController_SetRamIWS, (SmuM33CoreClk_IwsSetting), (Rtu0CoreClk_IwsSetting), (Rtu1CoreClk_IwsSetting), (CeM33CoreClk_IwsSetting));
225         #else
226             SRAMController_SetRamIWS(SmuM33CoreClk_IwsSetting, Rtu0CoreClk_IwsSetting, Rtu1CoreClk_IwsSetting, CeM33CoreClk_IwsSetting);
227         #endif
228     #else
229         SRAMController_SetRamIWS(SmuM33CoreClk_IwsSetting, Rtu0CoreClk_IwsSetting, Rtu1CoreClk_IwsSetting, CeM33CoreClk_IwsSetting);
230     #endif
231 }
232 #endif
233 
Clock_Ip_SpecificPlatformInitClock(Clock_Ip_ClockConfigType const * Config)234 static void Clock_Ip_SpecificPlatformInitClock(Clock_Ip_ClockConfigType const * Config)
235 {
236     (void)Config;
237 
238     uint32 CoreDfsIsInReset = IP_CORE_DFS->CTL & DFS_CTL_DFS_RESET_MASK;            /* if master core dfs is in reset */
239     uint32 PeriphDfsIsInReset = IP_PERIPH_DFS->CTL & DFS_CTL_DFS_RESET_MASK;        /* if master periph dfs is in reset */
240 
241     if ((CoreDfsIsInReset != 0U) && (PeriphDfsIsInReset != 0U))
242     {
243         if ((IP_CORE_PLL->PLLCR & PLLDIG_PLLCR_PLLPD_MASK) != 0U)   /* if CORE_PLL is not enabled */
244         {
245             IP_CORE_PLL->PLLCLKMUX = 0U;                                                   /* FIRC input reference 48 MHz */
246             IP_CORE_PLL->PLLDV = (PLLDIG_PLLDV_RDIV(1U) | PLLDIG_PLLDV_MFI(30U));          /* /1 * 30 */
247             IP_CORE_PLL->PLLFD &= ~(PLLDIG_PLLFD_MFN_MASK | PLLDIG_PLLFD_SDMEN_MASK);      /* Disable modulation */
248             IP_CORE_PLL->PLLCR &= ~PLLDIG_PLLCR_PLLPD_MASK;                                /* Start CORE_PLL */
249         }
250 
251         if ((IP_PERIPH_PLL->PLLCR & PLLDIG_PLLCR_PLLPD_MASK) != 0U)   /* if PERIPH_PLL is not enabled */
252         {
253             IP_PERIPH_PLL->PLLCLKMUX = 0U;                                                   /* FIRC input reference 48 MHz */
254             IP_PERIPH_PLL->PLLDV = (PLLDIG_PLLDV_RDIV(1U) | PLLDIG_PLLDV_MFI(30U));          /* /1 * 30 */
255             IP_PERIPH_PLL->PLLFD &= ~(PLLDIG_PLLFD_MFN_MASK | PLLDIG_PLLFD_SDMEN_MASK);      /* Disable modulation */
256             IP_PERIPH_PLL->PLLCR &= ~PLLDIG_PLLCR_PLLPD_MASK;                                /* Start PERIPH_PLL */
257         }
258 
259         IP_CORE_DFS->PORTRESET |= DFS_PORT_RESET;
260         IP_CORE_DFS->DVPORT[0U] = DFS_DVPORT;
261         IP_CORE_DFS->DVPORT[1U] = DFS_DVPORT;
262         IP_CORE_DFS->DVPORT[2U] = DFS_DVPORT;
263         IP_CORE_DFS->DVPORT[3U] = DFS_DVPORT;
264         IP_CORE_DFS->DVPORT[4U] = DFS_DVPORT;
265         IP_CORE_DFS->DVPORT[5U] = DFS_DVPORT;
266         IP_CORE_DFS->CTL &= ~DFS_CTL_DFS_RESET_MASK;
267         IP_CORE_DFS->PORTRESET &= ~DFS_PORT_RESET;
268 
269         IP_PERIPH_DFS->PORTRESET |= DFS_PORT_RESET;
270         IP_PERIPH_DFS->DVPORT[0U] = DFS_DVPORT;
271         IP_PERIPH_DFS->DVPORT[1U] = DFS_DVPORT;
272         IP_PERIPH_DFS->DVPORT[2U] = DFS_DVPORT;
273         IP_PERIPH_DFS->DVPORT[3U] = DFS_DVPORT;
274         IP_PERIPH_DFS->DVPORT[4U] = DFS_DVPORT;
275         IP_PERIPH_DFS->DVPORT[5U] = DFS_DVPORT;
276         IP_PERIPH_DFS->CTL &= ~DFS_CTL_DFS_RESET_MASK;
277         IP_PERIPH_DFS->PORTRESET &= ~DFS_PORT_RESET;
278     }
279     else if (CoreDfsIsInReset != 0U)
280     {
281         if ((IP_CORE_PLL->PLLCR & PLLDIG_PLLCR_PLLPD_MASK) != 0U)   /* if CORE_PLL is not enabled */
282         {
283             IP_CORE_PLL->PLLCLKMUX = 0U;                                                   /* FIRC input reference 48 MHz */
284             IP_CORE_PLL->PLLDV = (PLLDIG_PLLDV_RDIV(1U) | PLLDIG_PLLDV_MFI(30U));          /* /1 * 30 */
285             IP_CORE_PLL->PLLFD &= ~(PLLDIG_PLLFD_MFN_MASK | PLLDIG_PLLFD_SDMEN_MASK);      /* Disable modulation */
286             IP_CORE_PLL->PLLCR &= ~PLLDIG_PLLCR_PLLPD_MASK;                                /* Start CORE_PLL */
287         }
288 
289         IP_CORE_DFS->PORTRESET |= DFS_PORT_RESET;
290         IP_CORE_DFS->DVPORT[0U] = DFS_DVPORT;
291         IP_CORE_DFS->DVPORT[1U] = DFS_DVPORT;
292         IP_CORE_DFS->DVPORT[2U] = DFS_DVPORT;
293         IP_CORE_DFS->DVPORT[3U] = DFS_DVPORT;
294         IP_CORE_DFS->DVPORT[4U] = DFS_DVPORT;
295         IP_CORE_DFS->DVPORT[5U] = DFS_DVPORT;
296         IP_CORE_DFS->CTL &= ~DFS_CTL_DFS_RESET_MASK;
297         IP_CORE_DFS->PORTRESET &= ~DFS_PORT_RESET;
298     }
299     else if (PeriphDfsIsInReset != 0U)
300     {
301         if ((IP_PERIPH_PLL->PLLCR & PLLDIG_PLLCR_PLLPD_MASK) != 0U)   /* if PERIPH_PLL is not enabled */
302         {
303             IP_PERIPH_PLL->PLLCLKMUX = 0U;                                                   /* FIRC input reference 48 MHz */
304             IP_PERIPH_PLL->PLLDV = (PLLDIG_PLLDV_RDIV(1U) | PLLDIG_PLLDV_MFI(30U));          /* /1 * 30 */
305             IP_PERIPH_PLL->PLLFD &= ~(PLLDIG_PLLFD_MFN_MASK | PLLDIG_PLLFD_SDMEN_MASK);      /* Disable modulation */
306             IP_PERIPH_PLL->PLLCR &= ~PLLDIG_PLLCR_PLLPD_MASK;                                /* Start PERIPH_PLL */
307         }
308 
309         IP_PERIPH_DFS->PORTRESET |= DFS_PORT_RESET;
310         IP_PERIPH_DFS->DVPORT[0U] = DFS_DVPORT;
311         IP_PERIPH_DFS->DVPORT[1U] = DFS_DVPORT;
312         IP_PERIPH_DFS->DVPORT[2U] = DFS_DVPORT;
313         IP_PERIPH_DFS->DVPORT[3U] = DFS_DVPORT;
314         IP_PERIPH_DFS->DVPORT[4U] = DFS_DVPORT;
315         IP_PERIPH_DFS->DVPORT[5U] = DFS_DVPORT;
316         IP_PERIPH_DFS->CTL &= ~DFS_CTL_DFS_RESET_MASK;
317         IP_PERIPH_DFS->PORTRESET &= ~DFS_PORT_RESET;
318     }
319     else
320     {
321         /* periph Dfs and core Dfs are not in reset */
322     }
323     /* enable clock gate for DDR PLL PHI0 to input CLKOUT0 clock source */
324     IP_GPR0->CLKOUT0SEL |= GPR0_CLKOUT0SEL_CGEN(1U);
325 }
326 
327 
Clock_Ip_McMeEnterKey(void)328 void Clock_Ip_McMeEnterKey(void)
329 {
330     IP_MC_ME->CTL_KEY = 0x5AF0;                                         /* Enter key */
331 
332     IP_MC_ME->CTL_KEY = 0xA50F;                                         /* Enter inverted key */
333 }
334 
335 
336 #if (defined(CLOCK_IP_ENABLE_USER_MODE_SUPPORT))
337   #if (STD_ON == CLOCK_IP_ENABLE_USER_MODE_SUPPORT)
338     #if (defined(CLOCK_IP_HAS_SYSTEM_DIV2_CLK) || defined(CLOCK_IP_HAS_SYSTEM_DIV4_CLK))
Clock_Ip_SpecificSetUserAccessAllowed(void)339 void Clock_Ip_SpecificSetUserAccessAllowed(void)
340 {
341 
342 #if (defined(MCAL_CMU_AE_REG_PROT_AVAILABLE))
343   #if(STD_ON == MCAL_CMU_AE_REG_PROT_AVAILABLE)
344 
345     /* CMU_AE SetUserAccessAllowed */
346     #if (defined(IP_CMU_FC_AE_1_BASE))
347     /* Set user access allowed for CMU_FC_AE_1 */
348     #endif
349     #if (defined(IP_CMU_FC_AE_2_BASE))
350     /* Set user access allowed for CMU_FC_AE_2 */
351     #endif
352 
353 #endif
354 #endif /* MCAL_CMU_AE_REG_PROT_AVAILABLE */
355 
356 }
357 #endif /* (defined(CLOCK_IP_HAS_SYSTEM_DIV2_CLK) || defined(CLOCK_IP_HAS_SYSTEM_DIV4_CLK)) */
358 #endif
359 #endif /* CLOCK_IP_ENABLE_USER_MODE_SUPPORT */
360 
Clock_Ip_Command(Clock_Ip_ClockConfigType const * Config,Clock_Ip_CommandType Command)361 void Clock_Ip_Command(Clock_Ip_ClockConfigType const * Config, Clock_Ip_CommandType Command)
362 {
363     switch(Command)
364     {
365         case CLOCK_IP_INITIALIZE_PLATFORM_COMMAND:
366             Clock_Ip_SpecificPlatformInitClock(Config);
367             break;
368 #ifdef CLOCK_IP_ENABLE_USER_MODE_SUPPORT
369     #if (STD_ON == CLOCK_IP_ENABLE_USER_MODE_SUPPORT)
370         #if (defined(CLOCK_IP_HAS_SYSTEM_DIV2_CLK) || defined(CLOCK_IP_HAS_SYSTEM_DIV4_CLK))
371         case CLOCK_IP_SET_USER_ACCESS_ALLOWED_COMMAND:
372             OsIf_Trusted_Call(Clock_Ip_SpecificSetUserAccessAllowed);
373             break;
374         #endif
375     #endif
376 #endif
377         default:
378             /* Command is not implemented on this platform */
379             break;
380     }
381 }
382 
383 /* Clock stop section code */
384 #define MCU_STOP_SEC_CODE
385 #include "Mcu_MemMap.h"
386 
387 
388 #ifdef CLOCK_IP_HAS_RAM_WAIT_STATES
389 
390 
391 /* Clock start rom section code */
392 #define MCU_START_SEC_CODE_AC
393 #include "Mcu_MemMap.h"
394 
395 /* Set Ram IWS */
SRAMController_SetRamIWS(uint32 SmuM33CoreClk_IwsSetting,uint32 Rtu0CoreClk_IwsSetting,uint32 Rtu1CoreClk_IwsSetting,uint32 CeM33CoreClk_IwsSetting)396 void SRAMController_SetRamIWS(uint32 SmuM33CoreClk_IwsSetting, uint32 Rtu0CoreClk_IwsSetting, uint32 Rtu1CoreClk_IwsSetting, uint32 CeM33CoreClk_IwsSetting)
397 {
398 #if (1 == 1)
399     (void)SmuM33CoreClk_IwsSetting;
400     (void)Rtu0CoreClk_IwsSetting;
401     (void)Rtu1CoreClk_IwsSetting;
402     (void)CeM33CoreClk_IwsSetting;
403 #else
404     IP_SMU__SRAMCTL_0->RAMCR |= ((IP_SMU__SRAMCTL_0->RAMCR & ~SRAMCTL_RAMCR_IWS_MASK) | SRAMCTL_RAMCR_IWS(SmuM33CoreClk_IwsSetting));
405     IP_SMU__SRAMCTL_1->RAMCR |= ((IP_SMU__SRAMCTL_1->RAMCR & ~SRAMCTL_RAMCR_IWS_MASK) | SRAMCTL_RAMCR_IWS(SmuM33CoreClk_IwsSetting));
406     IP_SMU__SRAMCTL_2->RAMCR |= ((IP_SMU__SRAMCTL_2->RAMCR & ~SRAMCTL_RAMCR_IWS_MASK) | SRAMCTL_RAMCR_IWS(SmuM33CoreClk_IwsSetting));
407     IP_SMU__SRAMCTL_3->RAMCR |= ((IP_SMU__SRAMCTL_3->RAMCR & ~SRAMCTL_RAMCR_IWS_MASK) | SRAMCTL_RAMCR_IWS(SmuM33CoreClk_IwsSetting));
408 
409     IP_RTU0__SRAMCTL_C0->RAMCR |= ((IP_RTU0__SRAMCTL_C0->RAMCR & ~SRAMCTL_RAMCR_IWS_MASK) | SRAMCTL_RAMCR_IWS(Rtu0CoreClk_IwsSetting));
410     IP_RTU0__SRAMCTL_C1->RAMCR |= ((IP_RTU0__SRAMCTL_C1->RAMCR & ~SRAMCTL_RAMCR_IWS_MASK) | SRAMCTL_RAMCR_IWS(Rtu0CoreClk_IwsSetting));
411     IP_RTU0__SRAMCTL_C2->RAMCR |= ((IP_RTU0__SRAMCTL_C2->RAMCR & ~SRAMCTL_RAMCR_IWS_MASK) | SRAMCTL_RAMCR_IWS(Rtu0CoreClk_IwsSetting));
412     IP_RTU0__SRAMCTL_C3->RAMCR |= ((IP_RTU0__SRAMCTL_C3->RAMCR & ~SRAMCTL_RAMCR_IWS_MASK) | SRAMCTL_RAMCR_IWS(Rtu0CoreClk_IwsSetting));
413     IP_RTU0__SRAMCTL_C4->RAMCR |= ((IP_RTU0__SRAMCTL_C4->RAMCR & ~SRAMCTL_RAMCR_IWS_MASK) | SRAMCTL_RAMCR_IWS(Rtu0CoreClk_IwsSetting));
414     IP_RTU0__SRAMCTL_C5->RAMCR |= ((IP_RTU0__SRAMCTL_C5->RAMCR & ~SRAMCTL_RAMCR_IWS_MASK) | SRAMCTL_RAMCR_IWS(Rtu0CoreClk_IwsSetting));
415     IP_RTU0__SRAMCTL_C6->RAMCR |= ((IP_RTU0__SRAMCTL_C6->RAMCR & ~SRAMCTL_RAMCR_IWS_MASK) | SRAMCTL_RAMCR_IWS(Rtu0CoreClk_IwsSetting));
416     IP_RTU0__SRAMCTL_D0->RAMCR |= ((IP_RTU0__SRAMCTL_D0->RAMCR & ~SRAMCTL_RAMCR_IWS_MASK) | SRAMCTL_RAMCR_IWS(Rtu0CoreClk_IwsSetting));
417     IP_RTU0__SRAMCTL_D1->RAMCR |= ((IP_RTU0__SRAMCTL_D1->RAMCR & ~SRAMCTL_RAMCR_IWS_MASK) | SRAMCTL_RAMCR_IWS(Rtu0CoreClk_IwsSetting));
418     IP_RTU0__SRAMCTL_D2->RAMCR |= ((IP_RTU0__SRAMCTL_D2->RAMCR & ~SRAMCTL_RAMCR_IWS_MASK) | SRAMCTL_RAMCR_IWS(Rtu0CoreClk_IwsSetting));
419 
420     IP_RTU1__SRAMCTL_C0->RAMCR |= ((IP_RTU1__SRAMCTL_C0->RAMCR & ~SRAMCTL_RAMCR_IWS_MASK) | SRAMCTL_RAMCR_IWS(Rtu1CoreClk_IwsSetting));
421     IP_RTU1__SRAMCTL_C1->RAMCR |= ((IP_RTU1__SRAMCTL_C1->RAMCR & ~SRAMCTL_RAMCR_IWS_MASK) | SRAMCTL_RAMCR_IWS(Rtu1CoreClk_IwsSetting));
422     IP_RTU1__SRAMCTL_C2->RAMCR |= ((IP_RTU1__SRAMCTL_C2->RAMCR & ~SRAMCTL_RAMCR_IWS_MASK) | SRAMCTL_RAMCR_IWS(Rtu1CoreClk_IwsSetting));
423     IP_RTU1__SRAMCTL_C3->RAMCR |= ((IP_RTU1__SRAMCTL_C3->RAMCR & ~SRAMCTL_RAMCR_IWS_MASK) | SRAMCTL_RAMCR_IWS(Rtu1CoreClk_IwsSetting));
424     IP_RTU1__SRAMCTL_C4->RAMCR |= ((IP_RTU1__SRAMCTL_C4->RAMCR & ~SRAMCTL_RAMCR_IWS_MASK) | SRAMCTL_RAMCR_IWS(Rtu1CoreClk_IwsSetting));
425     IP_RTU1__SRAMCTL_C5->RAMCR |= ((IP_RTU1__SRAMCTL_C5->RAMCR & ~SRAMCTL_RAMCR_IWS_MASK) | SRAMCTL_RAMCR_IWS(Rtu1CoreClk_IwsSetting));
426     IP_RTU1__SRAMCTL_C6->RAMCR |= ((IP_RTU1__SRAMCTL_C6->RAMCR & ~SRAMCTL_RAMCR_IWS_MASK) | SRAMCTL_RAMCR_IWS(Rtu1CoreClk_IwsSetting));
427     IP_RTU1__SRAMCTL_D0->RAMCR |= ((IP_RTU1__SRAMCTL_D0->RAMCR & ~SRAMCTL_RAMCR_IWS_MASK) | SRAMCTL_RAMCR_IWS(Rtu1CoreClk_IwsSetting));
428     IP_RTU1__SRAMCTL_D1->RAMCR |= ((IP_RTU1__SRAMCTL_D1->RAMCR & ~SRAMCTL_RAMCR_IWS_MASK) | SRAMCTL_RAMCR_IWS(Rtu1CoreClk_IwsSetting));
429     IP_RTU1__SRAMCTL_D2->RAMCR |= ((IP_RTU1__SRAMCTL_D2->RAMCR & ~SRAMCTL_RAMCR_IWS_MASK) | SRAMCTL_RAMCR_IWS(Rtu1CoreClk_IwsSetting));
430 
431     IP_CE_SRAMCTL_0->RAMCR |= ((IP_CE_SRAMCTL_0->RAMCR & ~SRAMCTL_RAMCR_IWS_MASK) | SRAMCTL_RAMCR_IWS(CeM33CoreClk_IwsSetting));
432     IP_CE_SRAMCTL_1->RAMCR |= ((IP_CE_SRAMCTL_1->RAMCR & ~SRAMCTL_RAMCR_IWS_MASK) | SRAMCTL_RAMCR_IWS(CeM33CoreClk_IwsSetting));
433     IP_CE_SRAMCTL_2->RAMCR |= ((IP_CE_SRAMCTL_2->RAMCR & ~SRAMCTL_RAMCR_IWS_MASK) | SRAMCTL_RAMCR_IWS(CeM33CoreClk_IwsSetting));
434 #endif
435 }
436 
437 /* Clock stop rom section code */
438 #define MCU_STOP_SEC_CODE_AC
439 #include "Mcu_MemMap.h"
440 #endif
441 
442 
443 
444 #ifdef __cplusplus
445 }
446 #endif
447 
448 /** @} */
449 
450