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Searched refs:CTL (Results 1 – 25 of 188) sorted by relevance

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/hal_nuvoton-latest/m2l31x/StdDriver/inc/
Dacmp.h100 if (acmp == ACMP01) {(acmp)->CTL[u32ChNum] |= ACMP_CTL_ACMPOINV_Msk;}\
101 else if (acmp == ACMP2) {(acmp)->CTL[0] |= ACMP_CTL_ACMPOINV_Msk;}
112 if (acmp == ACMP01) {(acmp)->CTL[u32ChNum] &= ~ACMP_CTL_ACMPOINV_Msk);}\
113 else if (acmp == ACMP2) {(acmp)->CTL[0] &= ~ACMP_CTL_ACMPOINV_Msk);}
130 …if (acmp == ACMP01) {(acmp)->CTL[u32ChNum] = ((acmp)->CTL[u32ChNum] & ~ACMP_CTL_NEGSEL_Msk) | (u32…
131 else if (acmp == ACMP2) {(acmp)->CTL[0] = ((acmp)->CTL[0] & ~ACMP_CTL_NEGSEL_Msk) | (u32Src);}
141 …if (acmp == ACMP01) {(acmp)->CTL[u32ChNum] = ((acmp)->CTL[u32ChNum] & ~ACMP_CTL_HYSSEL_Msk) | (ACM…
142 …else if (acmp == ACMP2) {(acmp)->CTL[0] = ((acmp)->CTL[0] & ~ACMP_CTL_HYSSEL_Msk) | (ACMP_CTL_HYST…
153 …if (acmp == ACMP01) {(acmp)->CTL[u32ChNum] = ((acmp)->CTL[u32ChNum] & ~ACMP_CTL_HYSSEL_Msk) | (ACM…
154 …else if (acmp == ACMP2) {(acmp)->CTL[0] = ((acmp)->CTL[0] & ~ACMP_CTL_HYSSEL_Msk) | (ACMP_CTL_HYST…
[all …]
Deqei.h79 #define EQEI_DISABLE_CNT_CMP(eqei) ((eqei)->CTL &= (~EQEI_CTL_CMPEN_Msk))
88 #define EQEI_ENABLE_CNT_CMP(eqei) ((eqei)->CTL |= EQEI_CTL_CMPEN_Msk)
97 #define EQEI_DISABLE_INDEX_LATCH(eqei) ((eqei)->CTL &= (~EQEI_CTL_IDXLATEN_Msk))
106 #define EQEI_ENABLE_INDEX_LATCH(eqei) ((eqei)->CTL |= EQEI_CTL_IDXLATEN_Msk)
115 #define EQEI_DISABLE_INDEX_RELOAD(eqei) ((eqei)->CTL &= (~EQEI_CTL_IDXRLDEN_Msk))
124 #define EQEI_ENABLE_INDEX_RELOAD(eqei) ((eqei)->CTL |= EQEI_CTL_IDXRLDEN_Msk)
137 #define EQEI_DISABLE_INPUT(eqei, u32InputType) ((eqei)->CTL &= ~(u32InputType))
150 #define EQEI_ENABLE_INPUT(eqei, u32InputType) ((eqei)->CTL |= (u32InputType))
163 #define EQEI_DISABLE_INPUT_INV(eqei, u32InputType) ((eqei)->CTL &= ~(u32InputType))
176 #define EQEI_ENABLE_INPUT_INV(eqei, u32InputType) ((qei)->CTL |= (u32InputType))
[all …]
Dqspi.h91 #define QSPI_DISABLE_2BIT_MODE(qspi) ( (qspi)->CTL &= ~QSPI_CTL_TWOBIT_Msk )
109 #define QSPI_DISABLE_DUAL_MODE(qspi) ( (qspi)->CTL &= ~QSPI_CTL_DUALIOEN_Msk )
118 #define QSPI_DISABLE_QUAD_MODE(qspi) ( (qspi)->CTL &= ~QSPI_CTL_QUADIOEN_Msk )
127 #define QSPI_DISABLE_TXDTR_MODE(qspi) ( (qspi)->CTL &= ~QSPI_CTL_TXDTREN_Msk )
136 #define QSPI_ENABLE_2BIT_MODE(qspi) ( (qspi)->CTL |= QSPI_CTL_TWOBIT_Msk )
154 #define QSPI_ENABLE_DUAL_INPUT_MODE(qspi) ( (qspi)->CTL = ((qspi)->CTL & (~QSPI_CTL_DATDIR_Msk)) …
163 #define QSPI_ENABLE_DUAL_OUTPUT_MODE(qspi) ( (qspi)->CTL |= (QSPI_CTL_DATDIR_Msk | QSPI_CTL_DUALI…
172 #define QSPI_ENABLE_QUAD_INPUT_MODE(qspi) ( (qspi)->CTL = ((qspi)->CTL & (~QSPI_CTL_DATDIR_Msk)) …
181 #define QSPI_ENABLE_QUAD_OUTPUT_MODE(qspi) ( (qspi)->CTL |= (QSPI_CTL_DATDIR_Msk | QSPI_CTL_QUADI…
190 #define QSPI_ENABLE_TXDTR_MODE(qspi) ( (qspi)->CTL |= QSPI_CTL_TXDTREN_Msk )
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Dwdt.h79 #define WDT_CLEAR_RESET_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_IF_Msk | WDT_CTL_WKF_Msk)…
91 #define WDT_CLEAR_TIMEOUT_INT_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_RSTF_Msk | WDT_CTL_WKF_Ms…
103 #define WDT_CLEAR_TIMEOUT_WAKEUP_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_RSTF_Msk | WDT_CTL_IF_Msk…
116 #define WDT_GET_RESET_FLAG() ((WDT->CTL & WDT_CTL_RSTF_Msk)? 1UL : 0UL)
129 #define WDT_GET_TIMEOUT_INT_FLAG() ((WDT->CTL & WDT_CTL_IF_Msk)? 1UL : 0UL)
142 #define WDT_GET_TIMEOUT_WAKEUP_FLAG() ((WDT->CTL & WDT_CTL_WKF_Msk)? 1UL : 0UL)
181 WDT->CTL = 0UL; in WDT_Close()
182 while(WDT->CTL & WDT_CTL_SYNC_Msk) /* Wait disable WDTEN bit completed, it needs 2 * WDT_CLK. */ in WDT_Close()
199 WDT->CTL |= WDT_CTL_INTEN_Msk; in WDT_EnableInt()
214 WDT->CTL &= ~(WDT_CTL_INTEN_Msk | WDT_CTL_RSTF_Msk | WDT_CTL_IF_Msk | WDT_CTL_WKF_Msk); in WDT_DisableInt()
Dttmr.h78 #define TTMR_SET_PRESCALE_VALUE(ttmr, u32Value) ((ttmr)->CTL = ((ttmr)->CTL & ~TTMR_CTL_PSC_Msk…
91 #define TTMR_IS_ACTIVE(ttmr) (((ttmr)->CTL & TTMR_CTL_ACTSTS_Msk)? 1 : 0)
106 #define TTMR_SET_OPMODE(ttmr, u32OpMode) ((ttmr)->CTL = ((ttmr)->CTL & ~TTMR_CTL_OPMODE_Msk) | (…
132 ttmr->CTL |= TTMR_CTL_CNTEN_Msk; in TTMR_Start()
146 ttmr->CTL &= ~TTMR_CTL_CNTEN_Msk; in TTMR_Stop()
162 ttmr->CTL |= (TTMR_CTL_WKEN_Msk | TTMR_CTL_PDCLKEN_Msk); in TTMR_EnableWakeup()
176 ttmr->CTL &= ~TTMR_CTL_WKEN_Msk; in TTMR_DisableWakeup()
191 ttmr->CTL |= TTMR_CTL_INTEN_Msk; in TTMR_EnableInt()
205 ttmr->CTL &= ~TTMR_CTL_INTEN_Msk; in TTMR_DisableInt()
294 ttmr->CTL |= TTMR_CTL_PDCLKEN_Msk; in TTMR_EnablePDCLK()
[all …]
Ddac.h79 #define DAC_ENABLE_LEFT_ALIGN(dac) ((dac)->CTL |= DAC_CTL_LALIGN_Msk)
88 #define DAC_ENABLE_RIGHT_ALIGN(dac) ((dac)->CTL &= ~DAC_CTL_LALIGN_Msk)
98 #define DAC_ENABLE_BYPASS_BUFFER(dac) ((dac)->CTL |= DAC_CTL_BYPASS_Msk)
107 #define DAC_DISABLE_BYPASS_BUFFER(dac) ((dac)->CTL &= ~DAC_CTL_BYPASS_Msk)
117 #define DAC_ENABLE_INT(dac, u32Ch) ((dac)->CTL |= DAC_CTL_DACIEN_Msk)
127 #define DAC_DISABLE_INT(dac, u32Ch) ((dac)->CTL &= ~DAC_CTL_DACIEN_Msk)
136 #define DAC_ENABLE_DMAUDR_INT(dac) ((dac)->CTL |= DAC_CTL_DMAURIEN_Msk)
145 #define DAC_DISABLE_DMAUDR_INT(dac) ((dac)->CTL &= ~DAC_CTL_DMAURIEN_Msk)
154 #define DAC_ENABLE_PDMA(dac) ((dac)->CTL |= DAC_CTL_DMAEN_Msk)
163 #define DAC_DISABLE_PDMA(dac) ((dac)->CTL &= ~DAC_CTL_DMAEN_Msk)
[all …]
/hal_nuvoton-latest/m48x/StdDriver/inc/
Dacmp.h89 #define ACMP_ENABLE_OUTPUT_INVERSE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_ACMPOINV_Ms…
99 #define ACMP_DISABLE_OUTPUT_INVERSE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_ACMPOINV_…
114 #define ACMP_SET_NEG_SRC(acmp, u32ChNum, u32Src) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[(u32ChNum)…
123 #define ACMP_ENABLE_HYSTERESIS(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_HYSTERESIS_30MV)
133 #define ACMP_DISABLE_HYSTERESIS(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_HYSSEL_Msk)
147 #define ACMP_CONFIG_HYSTERESIS(acmp, u32ChNum, u32HysSel) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[(…
158 #define ACMP_ENABLE_INT(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_ACMPIE_Msk)
168 #define ACMP_DISABLE_INT(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_ACMPIE_Msk)
178 #define ACMP_ENABLE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_ACMPEN_Msk)
188 #define ACMP_DISABLE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_ACMPEN_Msk)
[all …]
Dqei.h65 #define QEI_DISABLE_CNT_CMP(qei) ((qei)->CTL &= (~QEI_CTL_CMPEN_Msk))
74 #define QEI_ENABLE_CNT_CMP(qei) ((qei)->CTL |= QEI_CTL_CMPEN_Msk)
83 #define QEI_DISABLE_INDEX_LATCH(qei) ((qei)->CTL &= (~QEI_CTL_IDXLATEN_Msk))
92 #define QEI_ENABLE_INDEX_LATCH(qei) ((qei)->CTL |= QEI_CTL_IDXLATEN_Msk)
101 #define QEI_DISABLE_INDEX_RELOAD(qei) ((qei)->CTL &= (~QEI_CTL_IDXRLDEN_Msk))
110 #define QEI_ENABLE_INDEX_RELOAD(qei) ((qei)->CTL |= QEI_CTL_IDXRLDEN_Msk)
123 #define QEI_DISABLE_INPUT(qei, u32InputType) ((qei)->CTL &= ~(u32InputType))
136 #define QEI_ENABLE_INPUT(qei, u32InputType) ((qei)->CTL |= (u32InputType))
149 #define QEI_DISABLE_INPUT_INV(qei, u32InputType) ((qei)->CTL &= ~(u32InputType))
162 #define QEI_ENABLE_INPUT_INV(qei, u32InputType) ((qei)->CTL |= (u32InputType))
[all …]
Dwdt.h71 #define WDT_CLEAR_RESET_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_IF_Msk | WDT_CTL_WKF_Msk)…
83 #define WDT_CLEAR_TIMEOUT_INT_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_RSTF_Msk | WDT_CTL_WKF_Ms…
95 #define WDT_CLEAR_TIMEOUT_WAKEUP_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_RSTF_Msk | WDT_CTL_IF_Msk…
108 #define WDT_GET_RESET_FLAG() ((WDT->CTL & WDT_CTL_RSTF_Msk)? 1UL : 0UL)
121 #define WDT_GET_TIMEOUT_INT_FLAG() ((WDT->CTL & WDT_CTL_IF_Msk)? 1UL : 0UL)
134 #define WDT_GET_TIMEOUT_WAKEUP_FLAG() ((WDT->CTL & WDT_CTL_WKF_Msk)? 1UL : 0UL)
167 WDT->CTL = 0UL; in WDT_Close()
182 WDT->CTL |= WDT_CTL_INTEN_Msk; in WDT_EnableInt()
198 WDT->CTL &= ~(WDT_CTL_INTEN_Msk | WDT_CTL_RSTF_Msk | WDT_CTL_IF_Msk | WDT_CTL_WKF_Msk); in WDT_DisableInt()
Dqspi.h199 #define QSPI_ENABLE_BYTE_REORDER(qspi) ((qspi)->CTL |= QSPI_CTL_REORDER_Msk)
208 #define QSPI_DISABLE_BYTE_REORDER(qspi) ((qspi)->CTL &= ~QSPI_CTL_REORDER_Msk)
219 #define QSPI_SET_SUSPEND_CYCLE(qspi, u32SuspCycle) ((qspi)->CTL = ((qspi)->CTL & ~QSPI_CTL_SUSPIT…
228 #define QSPI_SET_LSB_FIRST(qspi) ((qspi)->CTL |= QSPI_CTL_LSB_Msk)
237 #define QSPI_SET_MSB_FIRST(qspi) ((qspi)->CTL &= ~QSPI_CTL_LSB_Msk)
247 #define QSPI_SET_DATA_WIDTH(qspi, u32Width) ((qspi)->CTL = ((qspi)->CTL & ~QSPI_CTL_DWIDTH_Msk) |…
266 #define QSPI_ENABLE(qspi) ((qspi)->CTL |= QSPI_CTL_QSPIEN_Msk)
275 #define QSPI_DISABLE(qspi) ((qspi)->CTL &= ~QSPI_CTL_QSPIEN_Msk)
283 #define QSPI_DISABLE_DUAL_MODE(qspi) ( (qspi)->CTL &= ~QSPI_CTL_DUALIOEN_Msk )
291 #define QSPI_ENABLE_DUAL_INPUT_MODE(qspi) ( (qspi)->CTL = ((qspi)->CTL & ~QSPI_CTL_DATDIR_Msk) | QS…
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Ddac.h77 #define DAC_ENABLE_LEFT_ALIGN(dac) ((dac)->CTL |= DAC_CTL_LALIGN_Msk)
86 #define DAC_ENABLE_RIGHT_ALIGN(dac) ((dac)->CTL &= ~DAC_CTL_LALIGN_Msk)
96 #define DAC_ENABLE_BYPASS_BUFFER(dac) ((dac)->CTL |= DAC_CTL_BYPASS_Msk)
105 #define DAC_DISABLE_BYPASS_BUFFER(dac) ((dac)->CTL &= ~DAC_CTL_BYPASS_Msk)
115 #define DAC_ENABLE_INT(dac, u32Ch) ((dac)->CTL |= DAC_CTL_DACIEN_Msk)
125 #define DAC_DISABLE_INT(dac, u32Ch) ((dac)->CTL &= ~DAC_CTL_DACIEN_Msk)
134 #define DAC_ENABLE_DMAUDR_INT(dac) ((dac)->CTL |= DAC_CTL_DMAURIEN_Msk)
143 #define DAC_DISABLE_DMAUDR_INT(dac) ((dac)->CTL &= ~DAC_CTL_DMAURIEN_Msk)
152 #define DAC_ENABLE_PDMA(dac) ((dac)->CTL |= DAC_CTL_DMAEN_Msk)
161 #define DAC_DISABLE_PDMA(dac) ((dac)->CTL &= ~DAC_CTL_DMAEN_Msk)
[all …]
/hal_nuvoton-latest/m46x/StdDriver/inc/
Dbmc.h75 #define BMC_ENABLE() (BMC->CTL |= BMC_CTL_BMCEN_Msk)
83 #define BMC_DISABLE() (BMC->CTL &= ~BMC_CTL_BMCEN_Msk)
94 #define BMC_BITWIDTH_ADJUST(u32BitAdj) (BMC->CTL = (BMC->CTL & ~BMC_CTL_BWADJ_Msk) | (u32BitAdj))
105 #define BMC_PREAMBLE_BIT(u32PreamBit) (BMC->CTL = (BMC->CTL & ~BMC_CTL_PREAM32_Msk) | (u32PreamB…
116 #define BMC_DUMMY_LEVEL(u32DumLvl) (BMC->CTL = (BMC->CTL & ~BMC_CTL_DUMLVL_Msk) | (u32DumLvl))
124 #define BMC_ENABLE_DMA() (BMC->CTL |= BMC_CTL_DMAEN_Msk)
132 #define BMC_DISABLE_DMA() (BMC->CTL &= ~BMC_CTL_DMAEN_Msk)
140 #define BMC_ENABLE_GROUP0() (BMC->CTL |= BMC_CTL_G0CHEN_Msk)
148 #define BMC_ENABLE_GROUP1() (BMC->CTL |= BMC_CTL_G1CHEN_Msk)
156 #define BMC_ENABLE_GROUP2() (BMC->CTL |= BMC_CTL_G2CHEN_Msk)
[all …]
Dacmp.h95 #define ACMP_ENABLE_OUTPUT_INVERSE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_ACMPOINV_Ms…
105 #define ACMP_DISABLE_OUTPUT_INVERSE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_ACMPOINV_…
120 #define ACMP_SET_NEG_SRC(acmp, u32ChNum, u32Src) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[(u32ChNum)…
129 #define ACMP_ENABLE_HYSTERESIS(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_HYSTERESIS_30MV)
139 #define ACMP_DISABLE_HYSTERESIS(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_HYSSEL_Msk)
153 #define ACMP_CONFIG_HYSTERESIS(acmp, u32ChNum, u32HysSel) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[(…
164 #define ACMP_ENABLE_INT(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_ACMPIE_Msk)
174 #define ACMP_DISABLE_INT(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_ACMPIE_Msk)
184 #define ACMP_ENABLE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_ACMPEN_Msk)
194 #define ACMP_DISABLE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_ACMPEN_Msk)
[all …]
Deqei.h79 #define EQEI_DISABLE_CNT_CMP(eqei) ((eqei)->CTL &= (~EQEI_CTL_CMPEN_Msk))
88 #define EQEI_ENABLE_CNT_CMP(eqei) ((eqei)->CTL |= EQEI_CTL_CMPEN_Msk)
97 #define EQEI_DISABLE_INDEX_LATCH(eqei) ((eqei)->CTL &= (~EQEI_CTL_IDXLATEN_Msk))
106 #define EQEI_ENABLE_INDEX_LATCH(eqei) ((eqei)->CTL |= EQEI_CTL_IDXLATEN_Msk)
115 #define EQEI_DISABLE_INDEX_RELOAD(eqei) ((eqei)->CTL &= (~EQEI_CTL_IDXRLDEN_Msk))
124 #define EQEI_ENABLE_INDEX_RELOAD(eqei) ((eqei)->CTL |= EQEI_CTL_IDXRLDEN_Msk)
137 #define EQEI_DISABLE_INPUT(eqei, u32InputType) ((eqei)->CTL &= ~(u32InputType))
150 #define EQEI_ENABLE_INPUT(eqei, u32InputType) ((eqei)->CTL |= (u32InputType))
163 #define EQEI_DISABLE_INPUT_INV(eqei, u32InputType) ((eqei)->CTL &= ~(u32InputType))
176 #define EQEI_ENABLE_INPUT_INV(eqei, u32InputType) ((qei)->CTL |= (u32InputType))
[all …]
Dqspi.h91 #define QSPI_DISABLE_2BIT_MODE(qspi) ( (qspi)->CTL &= ~QSPI_CTL_TWOBIT_Msk )
109 #define QSPI_DISABLE_DUAL_MODE(qspi) ( (qspi)->CTL &= ~QSPI_CTL_DUALIOEN_Msk )
118 #define QSPI_DISABLE_QUAD_MODE(qspi) ( (qspi)->CTL &= ~QSPI_CTL_QUADIOEN_Msk )
127 #define QSPI_DISABLE_TXDTR_MODE(qspi) ( (qspi)->CTL &= ~QSPI_CTL_TXDTREN_Msk )
136 #define QSPI_ENABLE_2BIT_MODE(qspi) ( (qspi)->CTL |= QSPI_CTL_TWOBIT_Msk )
154 #define QSPI_ENABLE_DUAL_INPUT_MODE(qspi) ( (qspi)->CTL = ((qspi)->CTL & (~QSPI_CTL_DATDIR_Msk)) …
163 #define QSPI_ENABLE_DUAL_OUTPUT_MODE(qspi) ( (qspi)->CTL |= (QSPI_CTL_DATDIR_Msk | QSPI_CTL_DUALI…
172 #define QSPI_ENABLE_QUAD_INPUT_MODE(qspi) ( (qspi)->CTL = ((qspi)->CTL & (~QSPI_CTL_DATDIR_Msk)) …
181 #define QSPI_ENABLE_QUAD_OUTPUT_MODE(qspi) ( (qspi)->CTL |= (QSPI_CTL_DATDIR_Msk | QSPI_CTL_QUADI…
190 #define QSPI_ENABLE_TXDTR_MODE(qspi) ( (qspi)->CTL |= QSPI_CTL_TXDTREN_Msk )
[all …]
Dwdt.h79 #define WDT_CLEAR_RESET_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_IF_Msk | WDT_CTL_WKF_Msk)…
91 #define WDT_CLEAR_TIMEOUT_INT_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_RSTF_Msk | WDT_CTL_WKF_Ms…
103 #define WDT_CLEAR_TIMEOUT_WAKEUP_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_RSTF_Msk | WDT_CTL_IF_Msk…
116 #define WDT_GET_RESET_FLAG() ((WDT->CTL & WDT_CTL_RSTF_Msk)? 1UL : 0UL)
129 #define WDT_GET_TIMEOUT_INT_FLAG() ((WDT->CTL & WDT_CTL_IF_Msk)? 1UL : 0UL)
142 #define WDT_GET_TIMEOUT_WAKEUP_FLAG() ((WDT->CTL & WDT_CTL_WKF_Msk)? 1UL : 0UL)
181 WDT->CTL = 0UL; in WDT_Close()
182 while(WDT->CTL & WDT_CTL_SYNC_Msk) /* Wait disable WDTEN bit completed, it needs 2 * WDT_CLK. */ in WDT_Close()
199 WDT->CTL |= WDT_CTL_INTEN_Msk; in WDT_EnableInt()
214 WDT->CTL &= ~(WDT_CTL_INTEN_Msk | WDT_CTL_RSTF_Msk | WDT_CTL_IF_Msk | WDT_CTL_WKF_Msk); in WDT_DisableInt()
Ddac.h77 #define DAC_ENABLE_LEFT_ALIGN(dac) ((dac)->CTL |= DAC_CTL_LALIGN_Msk)
86 #define DAC_ENABLE_RIGHT_ALIGN(dac) ((dac)->CTL &= ~DAC_CTL_LALIGN_Msk)
95 #define DAC_ENABLE_BYPASS_BUFFER(dac) ((dac)->CTL |= DAC_CTL_BYPASS_Msk)
104 #define DAC_DISABLE_BYPASS_BUFFER(dac) ((dac)->CTL &= ~DAC_CTL_BYPASS_Msk)
114 #define DAC_ENABLE_INT(dac, u32Ch) ((dac)->CTL |= DAC_CTL_DACIEN_Msk)
124 #define DAC_DISABLE_INT(dac, u32Ch) ((dac)->CTL &= ~DAC_CTL_DACIEN_Msk)
133 #define DAC_ENABLE_DMAUDR_INT(dac) ((dac)->CTL |= DAC_CTL_DMAURIEN_Msk)
142 #define DAC_DISABLE_DMAUDR_INT(dac) ((dac)->CTL &= ~DAC_CTL_DMAURIEN_Msk)
151 #define DAC_ENABLE_PDMA(dac) ((dac)->CTL |= DAC_CTL_DMAEN_Msk)
160 #define DAC_DISABLE_PDMA(dac) ((dac)->CTL &= ~DAC_CTL_DMAEN_Msk)
[all …]
/hal_nuvoton-latest/m2l31x/StdDriver/src/
Dacmp.c63 acmp->CTL[0] |= ACMP_CTL_ACMPEN_Msk; in ACMP_Open()
67 acmp->CTL[0] = (acmp->CTL[0] & ~(ACMP_CTL_NEGSEL_Msk)) | in ACMP_Open()
82 acmp->CTL[1] |= ACMP_CTL_ACMPEN_Msk; in ACMP_Open()
86 acmp->CTL[1] = (acmp->CTL[1] & ~(ACMP_CTL_NEGSEL_Msk)) | in ACMP_Open()
100 …acmp->CTL[u32ChNum] = (acmp->CTL[u32ChNum] & (~(ACMP_CTL_NEGSEL_Msk | ACMP_CTL_HYSSEL_Msk))) | (u3… in ACMP_Open()
113 acmp->CTL[0] |= ACMP_CTL_ACMPEN_Msk; in ACMP_Open()
117 acmp->CTL[0] = (acmp->CTL[0] & ~(ACMP_CTL_NEGSEL_Msk)) | in ACMP_Open()
131 …acmp->CTL[0] = (acmp->CTL[u32ChNum] & (~(ACMP_CTL_NEGSEL_Msk | ACMP_CTL_HYSSEL_Msk))) | (u32NegSrc… in ACMP_Open()
149 acmp->CTL[u32ChNum] &= (~ACMP_CTL_ACMPEN_Msk); in ACMP_Close()
154 acmp->CTL[0] &= (~ACMP_CTL_ACMPEN_Msk); in ACMP_Close()
Dlppdma.c46 lppdma->LPDSCT[i].CTL = 0UL; in LPPDMA_Open()
85 lppdma->LPDSCT[u32Ch].CTL &= ~(LPPDMA_DSCT_CTL_TXCNT_Msk | LPPDMA_DSCT_CTL_TXWIDTH_Msk); in LPPDMA_SetTransferCnt()
86 lppdma->LPDSCT[u32Ch].CTL |= (u32Width | ((u32TransCount - 1UL) << LPPDMA_DSCT_CTL_TXCNT_Pos)); in LPPDMA_SetTransferCnt()
111 lppdma->LPDSCT[u32Ch].CTL &= ~(LPPDMA_DSCT_CTL_SAINC_Msk | LPPDMA_DSCT_CTL_DAINC_Msk); in LPPDMA_SetTransferAddr()
112 lppdma->LPDSCT[u32Ch].CTL |= (u32SrcCtrl | u32DstCtrl); in LPPDMA_SetTransferAddr()
166 …lppdma->LPDSCT[u32Ch].CTL = (lppdma->LPDSCT[u32Ch].CTL & ~LPPDMA_DSCT_CTL_OPMODE_Msk) | LPPDMA_OP_… in LPPDMA_SetTransferMode()
171 …lppdma->LPDSCT[u32Ch].CTL = (lppdma->LPDSCT[u32Ch].CTL & ~LPPDMA_DSCT_CTL_OPMODE_Msk) | LPPDMA_OP_… in LPPDMA_SetTransferMode()
199 lppdma->LPDSCT[u32Ch].CTL &= ~(LPPDMA_DSCT_CTL_TXTYPE_Msk | LPPDMA_DSCT_CTL_BURSIZE_Msk); in LPPDMA_SetBurstType()
200 lppdma->LPDSCT[u32Ch].CTL |= (u32BurstType | u32BurstSize); in LPPDMA_SetBurstType()
243 lppdma->LPDSCT[u32Ch].CTL &= ~LPPDMA_DSCT_CTL_TBINTDIS_Msk; in LPPDMA_EnableInt()
[all …]
Dtimer.c60 timer->CTL = u32Mode | u32Prescale; in TIMER_Open()
78 timer->CTL = 0UL; in TIMER_Close()
104 timer->CTL = 0UL; in TIMER_Delay()
145 timer->CTL = TIMER_CTL_CNTEN_Msk | TIMER_ONESHOT_MODE | u32Prescale; in TIMER_Delay()
161 while(timer->CTL & TIMER_CTL_ACTSTS_Msk) in TIMER_Delay()
241 timer->CTL |= TIMER_CTL_EXTCNTEN_Msk; in TIMER_EnableEventCounter()
256 timer->CTL &= ~TIMER_CTL_EXTCNTEN_Msk; in TIMER_DisableEventCounter()
336 timer->CTL = TIMER_CTL_INTRGEN_Msk | TIMER_CTL_CNTEN_Msk; in TIMER_EnableFreqCounter()
349 timer->CTL &= ~TIMER_CTL_INTRGEN_Msk; in TIMER_DisableFreqCounter()
408 timer->CTL = (timer->CTL & ~(TIMER_CTL_CAPSRC_Msk)) | in TIMER_CaptureSelect()
[all …]
/hal_nuvoton-latest/m48x/StdDriver/src/
Dsdh.c55 sdh->CTL |= SDH_CTL_CLK8OEN_Msk; in SDH_CheckRB()
56 while ((sdh->CTL & SDH_CTL_CLK8OEN_Msk) == SDH_CTL_CLK8OEN_Msk) in SDH_CheckRB()
82 buf = (sdh->CTL&(~SDH_CTL_CMDCODE_Msk))|(ucCmd << 8ul)|(SDH_CTL_COEN_Msk); in SDH_SDCommand()
83 sdh->CTL = buf; in SDH_SDCommand()
85 while ((sdh->CTL & SDH_CTL_COEN_Msk) == SDH_CTL_COEN_Msk) in SDH_SDCommand()
111 …buf = (sdh->CTL & (~SDH_CTL_CMDCODE_Msk)) | (ucCmd << 8ul) | (SDH_CTL_COEN_Msk | SDH_CTL_RIEN_Msk); in SDH_SDCmdAndRsp()
112 sdh->CTL = buf; in SDH_SDCmdAndRsp()
116 while ((sdh->CTL & SDH_CTL_RIEN_Msk) == SDH_CTL_RIEN_Msk) in SDH_SDCmdAndRsp()
120 sdh->CTL |= SDH_CTL_CTLRST_Msk; /* reset SD engine */ in SDH_SDCmdAndRsp()
131 while ((sdh->CTL & SDH_CTL_RIEN_Msk) == SDH_CTL_RIEN_Msk) in SDH_SDCmdAndRsp()
[all …]
Dtrng.c38 TRNG->CTL |= TRNG_CTL_TRNGEN_Msk; in TRNG_Open()
43 while ((TRNG->CTL & TRNG_CTL_READY_Msk) == 0); in TRNG_Open()
60 u32Reg = TRNG->CTL; in TRNG_GenWord()
64 TRNG->CTL = TRNG_CTL_TRNGEN_Msk | u32Reg; in TRNG_GenWord()
69 if (TRNG->CTL & TRNG_CTL_DVIF_Msk) in TRNG_GenWord()
95 u32Reg = TRNG->CTL; in TRNG_GenBignum()
99 TRNG->CTL = TRNG_CTL_TRNGEN_Msk | u32Reg; in TRNG_GenBignum()
104 if (TRNG->CTL & TRNG_CTL_DVIF_Msk) in TRNG_GenBignum()
130 u32Reg = TRNG->CTL; in TRNG_GenBignumHex()
134 TRNG->CTL = TRNG_CTL_TRNGEN_Msk | u32Reg; in TRNG_GenBignumHex()
[all …]
Dccap.c61 CCAP->CTL = (CCAP->CTL & ~(0x00000040UL)) | u32OutFormet; in CCAP_Open()
101 CCAP->CTL |= CCAP_CTL_UPDATE_Msk; in CCAP_SetPacketBuf()
111 CCAP->CTL &= ~CCAP_CTL_CCAPEN; in CCAP_Close()
167 CCAP->CTL = (CCAP->CTL & ~CCAP_CTL_MY8_MY4) | CCAP_CTL_MONO_Msk |u32Interface; in CCAP_EnableMono()
178 CCAP->CTL |= CCAP_CTL_MONO_Msk; in CCAP_DisableMono()
191 CCAP->CTL |= CCAP_CTL_Luma_Y_One_Msk; in CCAP_EnableLumaYOne()
203 CCAP->CTL &= ~CCAP_CTL_Luma_Y_One_Msk; in CCAP_DisableLumaYOne()
213 CCAP->CTL |= CCAP_CTL_CCAPEN; in CCAP_Start()
229 CCAP->CTL &= ~CCAP_CTL_CCAPEN; in CCAP_Stop()
232 CCAP->CTL |= CCAP_CTL_SHUTTER_Msk; in CCAP_Stop()
/hal_nuvoton-latest/m46x/StdDriver/src/
Dtrng.c42 TRNG->CTL |= TRNG_CTL_TRNGEN_Msk; in TRNG_Open()
47 while ((TRNG->CTL & TRNG_CTL_READY_Msk) == 0) in TRNG_Open()
69 u32Reg = TRNG->CTL; in TRNG_GenWord()
73 TRNG->CTL = TRNG_CTL_TRNGEN_Msk | u32Reg; in TRNG_GenWord()
78 if (TRNG->CTL & TRNG_CTL_DVIF_Msk) in TRNG_GenWord()
104 u32Reg = TRNG->CTL; in TRNG_GenBignum()
108 TRNG->CTL = TRNG_CTL_TRNGEN_Msk | u32Reg; in TRNG_GenBignum()
113 if (TRNG->CTL & TRNG_CTL_DVIF_Msk) in TRNG_GenBignum()
139 u32Reg = TRNG->CTL; in TRNG_GenBignumHex()
143 TRNG->CTL = TRNG_CTL_TRNGEN_Msk | u32Reg; in TRNG_GenBignumHex()
[all …]
Dccap.c56 CCAP->CTL = (CCAP->CTL & ~(0x00000040UL)) | u32OutFormat; in CCAP_Open()
92 CCAP->CTL |= CCAP_CTL_UPDATE_Msk; in CCAP_SetPacketBuf()
106 CCAP->CTL &= ~CCAP_CTL_CCAPEN; in CCAP_Close()
158 CCAP->CTL = (CCAP->CTL & ~CCAP_CTL_MY8_MY4_Msk) | CCAP_CTL_MONO_Msk |u32Interface; in CCAP_EnableMono()
172 CCAP->CTL &= ~CCAP_CTL_MONO_Msk; in CCAP_DisableMono()
186 CCAP->CTL |= CCAP_CTL_Luma_Y_One_Msk; in CCAP_EnableLumaYOne()
202 CCAP->CTL &= ~CCAP_CTL_Luma_Y_One_Msk; in CCAP_DisableLumaYOne()
216 CCAP->CTL |= CCAP_CTL_CCAPEN; in CCAP_Start()
236 CCAP->CTL &= ~CCAP_CTL_CCAPEN; in CCAP_Stop()
239 CCAP->CTL |= CCAP_CTL_SHUTTER_Msk; in CCAP_Stop()

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