1 /**************************************************************************//** 2 * @file dac.h 3 * @version V1.00 4 * @brief DAC driver header file 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __DAC_H__ 10 #define __DAC_H__ 11 12 #ifdef __cplusplus 13 extern "C" 14 { 15 #endif 16 17 18 /** @addtogroup Standard_Driver Standard Driver 19 @{ 20 */ 21 22 /** @addtogroup DAC_Driver DAC Driver 23 @{ 24 */ 25 26 27 /** @addtogroup DAC_EXPORTED_CONSTANTS DAC Exported Constants 28 @{ 29 */ 30 31 /*---------------------------------------------------------------------------------------------------------*/ 32 /* DAC_CTL Constant Definitions */ 33 /*---------------------------------------------------------------------------------------------------------*/ 34 #define DAC_CTL_LALIGN_RIGHT_ALIGN (0UL<<DAC_CTL_LALIGN_Pos) /*!< Right alignment. \hideinitializer */ 35 #define DAC_CTL_LALIGN_LEFT_ALIGN (1UL<<DAC_CTL_LALIGN_Pos) /*!< Left alignment \hideinitializer */ 36 37 #define DAC_WRITE_DAT_TRIGGER (0UL) /*!< Write DAC_DAT trigger \hideinitializer */ 38 #define DAC_SOFTWARE_TRIGGER (0UL|DAC_CTL_TRGEN_Msk) /*!< Software trigger \hideinitializer */ 39 #define DAC_LOW_LEVEL_TRIGGER ((0UL<<DAC_CTL_ETRGSEL_Pos)|(1UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< STDAC pin low level trigger \hideinitializer */ 40 #define DAC_HIGH_LEVEL_TRIGGER ((1UL<<DAC_CTL_ETRGSEL_Pos)|(1UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< STDAC pin high level trigger \hideinitializer */ 41 #define DAC_FALLING_EDGE_TRIGGER ((2UL<<DAC_CTL_ETRGSEL_Pos)|(1UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< STDAC pin falling edge trigger \hideinitializer */ 42 #define DAC_RISING_EDGE_TRIGGER ((3UL<<DAC_CTL_ETRGSEL_Pos)|(1UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< STDAC pin rising edge trigger \hideinitializer */ 43 #define DAC_TIMER0_TRIGGER ((2UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< Timer 0 trigger \hideinitializer */ 44 #define DAC_TIMER1_TRIGGER ((3UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< Timer 1 trigger \hideinitializer */ 45 #define DAC_TIMER2_TRIGGER ((4UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< Timer 2 trigger \hideinitializer */ 46 #define DAC_TIMER3_TRIGGER ((5UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< Timer 3 trigger \hideinitializer */ 47 #define DAC_EPWM0_TRIGGER ((6UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< EPWM0 trigger \hideinitializer */ 48 #define DAC_EPWM1_TRIGGER ((7UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< EPWM1 trigger \hideinitializer */ 49 #define DAC_PWM0_TRIGGER ((8UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< EPWM0 trigger \hideinitializer */ 50 #define DAC_PWM1_TRIGGER ((9UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< EPWM1 trigger \hideinitializer */ 51 52 #define DAC_TRIGGER_MODE_DISABLE (0UL<<DAC_CTL_TRGEN_Pos) /*!< Trigger mode disable \hideinitializer */ 53 #define DAC_TRIGGER_MODE_ENABLE (1UL<<DAC_CTL_TRGEN_Pos) /*!< Trigger mode enable \hideinitializer */ 54 55 56 /*@}*/ /* end of group DAC_EXPORTED_CONSTANTS */ 57 58 59 /** @addtogroup DAC_EXPORTED_FUNCTIONS DAC Exported Functions 60 @{ 61 */ 62 63 /** 64 * @brief Start the D/A conversion. 65 * @param[in] dac Base address of DAC module. 66 * @return None 67 * @details User writes SWTRG bit (DAC_SWTRG[0]) to generate one shot pulse and it is cleared to 0 by hardware automatically. 68 * \hideinitializer 69 */ 70 #define DAC_START_CONV(dac) ((dac)->SWTRG = DAC_SWTRG_SWTRG_Msk) 71 72 /** 73 * @brief Enable DAC data left-aligned. 74 * @param[in] dac Base address of DAC module. 75 * @return None 76 * @details User has to load data into DAC_DAT[15:4] bits. DAC_DAT[31:16] and DAC_DAT[3:0] are ignored in DAC conversion. 77 * \hideinitializer 78 */ 79 #define DAC_ENABLE_LEFT_ALIGN(dac) ((dac)->CTL |= DAC_CTL_LALIGN_Msk) 80 81 /** 82 * @brief Enable DAC data right-aligned. 83 * @param[in] dac Base address of DAC module. 84 * @return None 85 * @details User has to load data into DAC_DAT[11:0] bits, DAC_DAT[31:12] are ignored in DAC conversion. 86 * \hideinitializer 87 */ 88 #define DAC_ENABLE_RIGHT_ALIGN(dac) ((dac)->CTL &= ~DAC_CTL_LALIGN_Msk) 89 90 /** 91 * @brief Enable output voltage buffer. 92 * @param[in] dac Base address of DAC module. 93 * @return None 94 * @details The DAC integrates a voltage output buffer that can be used to reduce output impedance and 95 * drive external loads directly without having to add an external operational amplifier. 96 * \hideinitializer 97 */ 98 #define DAC_ENABLE_BYPASS_BUFFER(dac) ((dac)->CTL |= DAC_CTL_BYPASS_Msk) 99 100 /** 101 * @brief Disable output voltage buffer. 102 * @param[in] dac Base address of DAC module. 103 * @return None 104 * @details This macro is used to disable output voltage buffer. 105 * \hideinitializer 106 */ 107 #define DAC_DISABLE_BYPASS_BUFFER(dac) ((dac)->CTL &= ~DAC_CTL_BYPASS_Msk) 108 109 /** 110 * @brief Enable the interrupt. 111 * @param[in] dac Base address of DAC module. 112 * @param[in] u32Ch Not used. 113 * @return None 114 * @details This macro is used to enable DAC interrupt. 115 * \hideinitializer 116 */ 117 #define DAC_ENABLE_INT(dac, u32Ch) ((dac)->CTL |= DAC_CTL_DACIEN_Msk) 118 119 /** 120 * @brief Disable the interrupt. 121 * @param[in] dac Base address of DAC module. 122 * @param[in] u32Ch Not used. 123 * @return None 124 * @details This macro is used to disable DAC interrupt. 125 * \hideinitializer 126 */ 127 #define DAC_DISABLE_INT(dac, u32Ch) ((dac)->CTL &= ~DAC_CTL_DACIEN_Msk) 128 129 /** 130 * @brief Enable DMA under-run interrupt. 131 * @param[in] dac Base address of DAC module. 132 * @return None 133 * @details This macro is used to enable DMA under-run interrupt. 134 * \hideinitializer 135 */ 136 #define DAC_ENABLE_DMAUDR_INT(dac) ((dac)->CTL |= DAC_CTL_DMAURIEN_Msk) 137 138 /** 139 * @brief Disable DMA under-run interrupt. 140 * @param[in] dac Base address of DAC module. 141 * @return None 142 * @details This macro is used to disable DMA under-run interrupt. 143 * \hideinitializer 144 */ 145 #define DAC_DISABLE_DMAUDR_INT(dac) ((dac)->CTL &= ~DAC_CTL_DMAURIEN_Msk) 146 147 /** 148 * @brief Enable PDMA mode. 149 * @param[in] dac Base address of DAC module. 150 * @return None 151 * @details DAC DMA request is generated when a hardware trigger event occurs while DMAEN (DAC_CTL[2]) is set. 152 * \hideinitializer 153 */ 154 #define DAC_ENABLE_PDMA(dac) ((dac)->CTL |= DAC_CTL_DMAEN_Msk) 155 156 /** 157 * @brief Disable PDMA mode. 158 * @param[in] dac Base address of DAC module. 159 * @return None 160 * @details This macro is used to disable DMA mode. 161 * \hideinitializer 162 */ 163 #define DAC_DISABLE_PDMA(dac) ((dac)->CTL &= ~DAC_CTL_DMAEN_Msk) 164 165 /** 166 * @brief Write data for conversion. 167 * @param[in] dac Base address of DAC module. 168 * @param[in] u32Ch Not used. 169 * @param[in] u32Data Decides the data for conversion, valid range are between 0~0xFFF. 170 * @return None 171 * @details 12 bit left alignment: user has to load data into DAC_DAT[15:4] bits. 172 * 12 bit right alignment: user has to load data into DAC_DAT[11:0] bits. 173 * \hideinitializer 174 */ 175 #define DAC_WRITE_DATA(dac, u32Ch, u32Data) ((dac)->DAT = (u32Data)) 176 177 /** 178 * @brief Read DAC 12-bit holding data. 179 * @param[in] dac Base address of DAC module. 180 * @param[in] u32Ch Not used. 181 * @return Return DAC 12-bit holding data. 182 * @details This macro is used to read DAC_DAT register. 183 * \hideinitializer 184 */ 185 #define DAC_READ_DATA(dac, u32Ch) ((dac)->DAT) 186 187 /** 188 * @brief Get the busy state of DAC. 189 * @param[in] dac Base address of DAC module. 190 * @param[in] u32Ch Not used. 191 * @retval 0 Idle state. 192 * @retval 1 Busy state. 193 * @details This macro is used to read BUSY bit (DAC_STATUS[8]) to get busy state. 194 * \hideinitializer 195 */ 196 #define DAC_IS_BUSY(dac, u32Ch) (((dac)->STATUS & DAC_STATUS_BUSY_Msk) >> DAC_STATUS_BUSY_Pos) 197 198 /** 199 * @brief Get the interrupt flag. 200 * @param[in] dac Base address of DAC module. 201 * @param[in] u32Ch Not used. 202 * @retval 0 DAC is in conversion state. 203 * @retval 1 DAC conversion finish. 204 * @details This macro is used to read FINISH bit (DAC_STATUS[0]) to get DAC conversion complete finish flag. 205 * \hideinitializer 206 */ 207 #define DAC_GET_INT_FLAG(dac, u32Ch) ((dac)->STATUS & DAC_STATUS_FINISH_Msk) 208 209 /** 210 * @brief Get the DMA under-run flag. 211 * @param[in] dac Base address of DAC module. 212 * @retval 0 No DMA under-run error condition occurred. 213 * @retval 1 DMA under-run error condition occurred. 214 * @details This macro is used to read DMAUDR bit (DAC_STATUS[1]) to get DMA under-run state. 215 * \hideinitializer 216 */ 217 #define DAC_GET_DMAUDR_FLAG(dac) (((dac)->STATUS & DAC_STATUS_DMAUDR_Msk) >> DAC_STATUS_DMAUDR_Pos) 218 219 /** 220 * @brief This macro clear the interrupt status bit. 221 * @param[in] dac Base address of DAC module. 222 * @param[in] u32Ch Not used. 223 * @return None 224 * @details User writes FINISH bit (DAC_STATUS[0]) to clear DAC conversion complete finish flag. 225 * \hideinitializer 226 */ 227 #define DAC_CLR_INT_FLAG(dac, u32Ch) ((dac)->STATUS = DAC_STATUS_FINISH_Msk) 228 229 /** 230 * @brief This macro clear the DMA under-run flag. 231 * @param[in] dac Base address of DAC module. 232 * @return None 233 * @details User writes DMAUDR bit (DAC_STATUS[1]) to clear DMA under-run flag. 234 * \hideinitializer 235 */ 236 #define DAC_CLR_DMAUDR_FLAG(dac) ((dac)->STATUS = DAC_STATUS_DMAUDR_Msk) 237 238 /** 239 * @brief Enable DAC group mode 240 * @param[in] dac Base address of DAC module. 241 * @return None 242 * \hideinitializer 243 */ 244 #define DAC_ENABLE_GROUP_MODE(dac) (DAC0->CTL |= DAC_CTL_GRPEN_Msk) 245 246 /** 247 * @brief Disable DAC group mode 248 * @param[in] dac Base address of DAC module. 249 * @return None 250 * \hideinitializer 251 */ 252 #define DAC_DISABLE_GROUP_MODE(dac) (DAC0->CTL &= ~DAC_CTL_GRPEN_Msk) 253 254 void DAC_Open(DAC_T *dac, uint32_t u32Ch, uint32_t u32TrgSrc); 255 void DAC_Close(DAC_T *dac, uint32_t u32Ch); 256 uint32_t DAC_SetDelayTime(DAC_T *dac, uint32_t u32Delay); 257 258 /*@}*/ /* end of group DAC_EXPORTED_FUNCTIONS */ 259 260 /*@}*/ /* end of group DAC_Driver */ 261 262 /*@}*/ /* end of group Standard_Driver */ 263 264 #ifdef __cplusplus 265 } 266 #endif 267 268 #endif /* __DAC_H__ */ 269 270 /*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ 271
