1 /**************************************************************************//** 2 * @file dac.h 3 * @version V1.00 4 * @brief DAC driver header file 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 * @copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __DAC_H__ 10 #define __DAC_H__ 11 12 #ifdef __cplusplus 13 extern "C" 14 { 15 #endif 16 17 18 /** @addtogroup Standard_Driver Standard Driver 19 @{ 20 */ 21 22 /** @addtogroup DAC_Driver DAC Driver 23 @{ 24 */ 25 26 27 /** @addtogroup DAC_EXPORTED_CONSTANTS DAC Exported Constants 28 @{ 29 */ 30 31 /*---------------------------------------------------------------------------------------------------------*/ 32 /* DAC_CTL Constant Definitions */ 33 /*---------------------------------------------------------------------------------------------------------*/ 34 #define DAC_CTL_LALIGN_RIGHT_ALIGN (0UL<<DAC_CTL_LALIGN_Pos) /*!< Right alignment. \hideinitializer */ 35 #define DAC_CTL_LALIGN_LEFT_ALIGN (1UL<<DAC_CTL_LALIGN_Pos) /*!< Left alignment \hideinitializer */ 36 37 #define DAC_WRITE_DAT_TRIGGER (0UL) /*!< Write DAC_DAT trigger \hideinitializer */ 38 #define DAC_SOFTWARE_TRIGGER (0UL|DAC_CTL_TRGEN_Msk) /*!< Software trigger \hideinitializer */ 39 #define DAC_LOW_LEVEL_TRIGGER ((0UL<<DAC_CTL_ETRGSEL_Pos)|(1UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< STDAC pin low level trigger \hideinitializer */ 40 #define DAC_HIGH_LEVEL_TRIGGER ((1UL<<DAC_CTL_ETRGSEL_Pos)|(1UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< STDAC pin high level trigger \hideinitializer */ 41 #define DAC_FALLING_EDGE_TRIGGER ((2UL<<DAC_CTL_ETRGSEL_Pos)|(1UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< STDAC pin falling edge trigger \hideinitializer */ 42 #define DAC_RISING_EDGE_TRIGGER ((3UL<<DAC_CTL_ETRGSEL_Pos)|(1UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< STDAC pin rising edge trigger \hideinitializer */ 43 #define DAC_TIMER0_TRIGGER ((2UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< Timer 0 trigger \hideinitializer */ 44 #define DAC_TIMER1_TRIGGER ((3UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< Timer 1 trigger \hideinitializer */ 45 #define DAC_TIMER2_TRIGGER ((4UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< Timer 2 trigger \hideinitializer */ 46 #define DAC_TIMER3_TRIGGER ((5UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< Timer 3 trigger \hideinitializer */ 47 #define DAC_EPWM0_TRIGGER ((6UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< EPWM0 trigger \hideinitializer */ 48 #define DAC_EPWM1_TRIGGER ((7UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< EPWM1 trigger \hideinitializer */ 49 50 #define DAC_TRIGGER_MODE_DISABLE (0UL<<DAC_CTL_TRGEN_Pos) /*!< Trigger mode disable \hideinitializer */ 51 #define DAC_TRIGGER_MODE_ENABLE (1UL<<DAC_CTL_TRGEN_Pos) /*!< Trigger mode enable \hideinitializer */ 52 53 54 /*@}*/ /* end of group DAC_EXPORTED_CONSTANTS */ 55 56 57 /** @addtogroup DAC_EXPORTED_FUNCTIONS DAC Exported Functions 58 @{ 59 */ 60 61 /** 62 * @brief Start the D/A conversion. 63 * @param[in] dac The pointer of the specified DAC module. 64 * @return None 65 * @details User writes SWTRG bit (DAC_SWTRG[0]) to generate one shot pulse and it is cleared to 0 by hardware automatically. 66 * \hideinitializer 67 */ 68 #define DAC_START_CONV(dac) ((dac)->SWTRG = DAC_SWTRG_SWTRG_Msk) 69 70 /** 71 * @brief Enable DAC data left-aligned. 72 * @param[in] dac The pointer of the specified DAC module. 73 * @return None 74 * @details User has to load data into DAC_DAT[15:4] bits. DAC_DAT[31:16] and DAC_DAT[3:0] are ignored in DAC conversion. 75 * \hideinitializer 76 */ 77 #define DAC_ENABLE_LEFT_ALIGN(dac) ((dac)->CTL |= DAC_CTL_LALIGN_Msk) 78 79 /** 80 * @brief Enable DAC data right-aligned. 81 * @param[in] dac The pointer of the specified DAC module. 82 * @return None 83 * @details User has to load data into DAC_DAT[11:0] bits, DAC_DAT[31:12] are ignored in DAC conversion. 84 * \hideinitializer 85 */ 86 #define DAC_ENABLE_RIGHT_ALIGN(dac) ((dac)->CTL &= ~DAC_CTL_LALIGN_Msk) 87 88 /** 89 * @brief Enable bypass voltage output buffer mode. 90 * @param[in] dac The pointer of the specified DAC module. 91 * @return None 92 * @details This will make DAC output bypass the voltage output buffer. 93 * \hideinitializer 94 */ 95 #define DAC_ENABLE_BYPASS_BUFFER(dac) ((dac)->CTL |= DAC_CTL_BYPASS_Msk) 96 97 /** 98 * @brief Disable bypass voltage output buffer mode. 99 * @param[in] dac The pointer of the specified DAC module. 100 * @return None 101 * @details This will make DAC output through the voltage output buffer. 102 * \hideinitializer 103 */ 104 #define DAC_DISABLE_BYPASS_BUFFER(dac) ((dac)->CTL &= ~DAC_CTL_BYPASS_Msk) 105 106 /** 107 * @brief Enable the interrupt. 108 * @param[in] dac The pointer of the specified DAC module. 109 * @param[in] u32Ch Not used. 110 * @return None 111 * @details This macro is used to enable DAC interrupt. 112 * \hideinitializer 113 */ 114 #define DAC_ENABLE_INT(dac, u32Ch) ((dac)->CTL |= DAC_CTL_DACIEN_Msk) 115 116 /** 117 * @brief Disable the interrupt. 118 * @param[in] dac The pointer of the specified DAC module. 119 * @param[in] u32Ch Not used. 120 * @return None 121 * @details This macro is used to disable DAC interrupt. 122 * \hideinitializer 123 */ 124 #define DAC_DISABLE_INT(dac, u32Ch) ((dac)->CTL &= ~DAC_CTL_DACIEN_Msk) 125 126 /** 127 * @brief Enable DMA under-run interrupt. 128 * @param[in] dac The pointer of the specified DAC module. 129 * @return None 130 * @details This macro is used to enable DMA under-run interrupt. 131 * \hideinitializer 132 */ 133 #define DAC_ENABLE_DMAUDR_INT(dac) ((dac)->CTL |= DAC_CTL_DMAURIEN_Msk) 134 135 /** 136 * @brief Disable DMA under-run interrupt. 137 * @param[in] dac The pointer of the specified DAC module. 138 * @return None 139 * @details This macro is used to disable DMA under-run interrupt. 140 * \hideinitializer 141 */ 142 #define DAC_DISABLE_DMAUDR_INT(dac) ((dac)->CTL &= ~DAC_CTL_DMAURIEN_Msk) 143 144 /** 145 * @brief Enable PDMA mode. 146 * @param[in] dac The pointer of the specified DAC module. 147 * @return None 148 * @details DAC DMA request is generated when a hardware trigger event occurs while DMAEN (DAC_CTL[2]) is set. 149 * \hideinitializer 150 */ 151 #define DAC_ENABLE_PDMA(dac) ((dac)->CTL |= DAC_CTL_DMAEN_Msk) 152 153 /** 154 * @brief Disable PDMA mode. 155 * @param[in] dac The pointer of the specified DAC module. 156 * @return None 157 * @details This macro is used to disable DMA mode. 158 * \hideinitializer 159 */ 160 #define DAC_DISABLE_PDMA(dac) ((dac)->CTL &= ~DAC_CTL_DMAEN_Msk) 161 162 /** 163 * @brief Write data for conversion. 164 * @param[in] dac The pointer of the specified DAC module. 165 * @param[in] u32Ch Not used. 166 * @param[in] u32Data Decides the data for conversion, valid range are between 0~0xFFF. 167 * @return None 168 * @details 12 bit left alignment: user has to load data into DAC_DAT[15:4] bits. 169 * 12 bit right alignment: user has to load data into DAC_DAT[11:0] bits. 170 * \hideinitializer 171 */ 172 #define DAC_WRITE_DATA(dac, u32Ch, u32Data) ((dac)->DAT = (u32Data)) 173 174 /** 175 * @brief Read DAC 12-bit holding data. 176 * @param[in] dac The pointer of the specified DAC module. 177 * @param[in] u32Ch Not used. 178 * @return Return DAC 12-bit holding data. 179 * @details This macro is used to read DAC_DAT register. 180 * \hideinitializer 181 */ 182 #define DAC_READ_DATA(dac, u32Ch) ((dac)->DAT) 183 184 /** 185 * @brief Get the busy state of DAC. 186 * @param[in] dac The pointer of the specified DAC module. 187 * @param[in] u32Ch Not used. 188 * @retval 0 Idle state. 189 * @retval 1 Busy state. 190 * @details This macro is used to read BUSY bit (DAC_STATUS[8]) to get busy state. 191 * \hideinitializer 192 */ 193 #define DAC_IS_BUSY(dac, u32Ch) (((dac)->STATUS & DAC_STATUS_BUSY_Msk) >> DAC_STATUS_BUSY_Pos) 194 195 /** 196 * @brief Get the interrupt flag. 197 * @param[in] dac The pointer of the specified DAC module. 198 * @param[in] u32Ch Not used. 199 * @retval 0 DAC is in conversion state. 200 * @retval 1 DAC conversion finish. 201 * @details This macro is used to read FINISH bit (DAC_STATUS[0]) to get DAC conversion complete finish flag. 202 * \hideinitializer 203 */ 204 #define DAC_GET_INT_FLAG(dac, u32Ch) ((dac)->STATUS & DAC_STATUS_FINISH_Msk) 205 206 /** 207 * @brief Get the DMA under-run flag. 208 * @param[in] dac The pointer of the specified DAC module. 209 * @retval 0 No DMA under-run error condition occurred. 210 * @retval 1 DMA under-run error condition occurred. 211 * @details This macro is used to read DMAUDR bit (DAC_STATUS[1]) to get DMA under-run state. 212 * \hideinitializer 213 */ 214 #define DAC_GET_DMAUDR_FLAG(dac) (((dac)->STATUS & DAC_STATUS_DMAUDR_Msk) >> DAC_STATUS_DMAUDR_Pos) 215 216 /** 217 * @brief This macro clear the interrupt status bit. 218 * @param[in] dac The pointer of the specified DAC module. 219 * @param[in] u32Ch Not used. 220 * @return None 221 * @details User writes FINISH bit (DAC_STATUS[0]) to clear DAC conversion complete finish flag. 222 * \hideinitializer 223 */ 224 #define DAC_CLR_INT_FLAG(dac, u32Ch) ((dac)->STATUS = DAC_STATUS_FINISH_Msk) 225 226 /** 227 * @brief This macro clear the DMA under-run flag. 228 * @param[in] dac The pointer of the specified DAC module. 229 * @return None 230 * @details User writes DMAUDR bit (DAC_STATUS[1]) to clear DMA under-run flag. 231 * \hideinitializer 232 */ 233 #define DAC_CLR_DMAUDR_FLAG(dac) ((dac)->STATUS = DAC_STATUS_DMAUDR_Msk) 234 235 236 /** 237 * @brief Enable DAC group mode 238 * @param[in] dac The pointer of the specified DAC module. 239 * @return None 240 * @note Only DAC0 has this control bit. 241 * \hideinitializer 242 */ 243 #define DAC_ENABLE_GROUP_MODE(dac) ((dac)->CTL |= DAC_CTL_GRPEN_Msk) 244 245 /** 246 * @brief Disable DAC group mode 247 * @param[in] dac The pointer of the specified DAC module. 248 * @return None 249 * @note Only DAC0 has this control bit. 250 * \hideinitializer 251 */ 252 #define DAC_DISABLE_GROUP_MODE(dac) ((dac)->CTL &= ~DAC_CTL_GRPEN_Msk) 253 254 void DAC_Open(DAC_T *dac, uint32_t u32Ch, uint32_t u32TrgSrc); 255 void DAC_Close(DAC_T *dac, uint32_t u32Ch); 256 uint32_t DAC_SetDelayTime(DAC_T *dac, uint32_t u32Delay); 257 258 /*@}*/ /* end of group DAC_EXPORTED_FUNCTIONS */ 259 260 /*@}*/ /* end of group DAC_Driver */ 261 262 /*@}*/ /* end of group Standard_Driver */ 263 264 #ifdef __cplusplus 265 } 266 #endif 267 268 #endif /* __DAC_H__ */ 269 270
