1 /**************************************************************************//** 2 * @file dac.h 3 * @version V1.00 4 * @brief M480 series DAC driver header file 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __DAC_H__ 10 #define __DAC_H__ 11 12 #ifdef __cplusplus 13 extern "C" 14 { 15 #endif 16 17 18 /** @addtogroup Standard_Driver Standard Driver 19 @{ 20 */ 21 22 /** @addtogroup DAC_Driver DAC Driver 23 @{ 24 */ 25 26 27 /** @addtogroup DAC_EXPORTED_CONSTANTS DAC Exported Constants 28 @{ 29 */ 30 31 /*---------------------------------------------------------------------------------------------------------*/ 32 /* DAC_CTL Constant Definitions */ 33 /*---------------------------------------------------------------------------------------------------------*/ 34 #define DAC_CTL_LALIGN_RIGHT_ALIGN (0UL<<DAC_CTL_LALIGN_Pos) /*!< Right alignment. \hideinitializer */ 35 #define DAC_CTL_LALIGN_LEFT_ALIGN (1UL<<DAC_CTL_LALIGN_Pos) /*!< Left alignment \hideinitializer */ 36 37 #define DAC_WRITE_DAT_TRIGGER (0UL) /*!< Write DAC_DAT trigger \hideinitializer */ 38 #define DAC_SOFTWARE_TRIGGER (0UL|DAC_CTL_TRGEN_Msk) /*!< Software trigger \hideinitializer */ 39 #define DAC_LOW_LEVEL_TRIGGER ((0UL<<DAC_CTL_ETRGSEL_Pos)|(1UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< STDAC pin low level trigger \hideinitializer */ 40 #define DAC_HIGH_LEVEL_TRIGGER ((1UL<<DAC_CTL_ETRGSEL_Pos)|(1UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< STDAC pin high level trigger \hideinitializer */ 41 #define DAC_FALLING_EDGE_TRIGGER ((2UL<<DAC_CTL_ETRGSEL_Pos)|(1UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< STDAC pin falling edge trigger \hideinitializer */ 42 #define DAC_RISING_EDGE_TRIGGER ((3UL<<DAC_CTL_ETRGSEL_Pos)|(1UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< STDAC pin rising edge trigger \hideinitializer */ 43 #define DAC_TIMER0_TRIGGER ((2UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< Timer 0 trigger \hideinitializer */ 44 #define DAC_TIMER1_TRIGGER ((3UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< Timer 1 trigger \hideinitializer */ 45 #define DAC_TIMER2_TRIGGER ((4UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< Timer 2 trigger \hideinitializer */ 46 #define DAC_TIMER3_TRIGGER ((5UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< Timer 3 trigger \hideinitializer */ 47 #define DAC_EPWM0_TRIGGER ((6UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< EPWM0 trigger \hideinitializer */ 48 #define DAC_EPWM1_TRIGGER ((7UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< EPWM1 trigger \hideinitializer */ 49 50 #define DAC_TRIGGER_MODE_DISABLE (0UL<<DAC_CTL_TRGEN_Pos) /*!< Trigger mode disable \hideinitializer */ 51 #define DAC_TRIGGER_MODE_ENABLE (1UL<<DAC_CTL_TRGEN_Pos) /*!< Trigger mode enable \hideinitializer */ 52 53 54 /*@}*/ /* end of group DAC_EXPORTED_CONSTANTS */ 55 56 57 /** @addtogroup DAC_EXPORTED_FUNCTIONS DAC Exported Functions 58 @{ 59 */ 60 61 /** 62 * @brief Start the D/A conversion. 63 * @param[in] dac Base address of DAC module. 64 * @return None 65 * @details User writes SWTRG bit (DAC_SWTRG[0]) to generate one shot pulse and it is cleared to 0 by hardware automatically. 66 * \hideinitializer 67 */ 68 #define DAC_START_CONV(dac) ((dac)->SWTRG = DAC_SWTRG_SWTRG_Msk) 69 70 /** 71 * @brief Enable DAC data left-aligned. 72 * @param[in] dac Base address of DAC module. 73 * @return None 74 * @details User has to load data into DAC_DAT[15:4] bits. DAC_DAT[31:16] and DAC_DAT[3:0] are ignored in DAC conversion. 75 * \hideinitializer 76 */ 77 #define DAC_ENABLE_LEFT_ALIGN(dac) ((dac)->CTL |= DAC_CTL_LALIGN_Msk) 78 79 /** 80 * @brief Enable DAC data right-aligned. 81 * @param[in] dac Base address of DAC module. 82 * @return None 83 * @details User has to load data into DAC_DAT[11:0] bits, DAC_DAT[31:12] are ignored in DAC conversion. 84 * \hideinitializer 85 */ 86 #define DAC_ENABLE_RIGHT_ALIGN(dac) ((dac)->CTL &= ~DAC_CTL_LALIGN_Msk) 87 88 /** 89 * @brief Enable output voltage buffer. 90 * @param[in] dac Base address of DAC module. 91 * @return None 92 * @details The DAC integrates a voltage output buffer that can be used to reduce output impedance and 93 * drive external loads directly without having to add an external operational amplifier. 94 * \hideinitializer 95 */ 96 #define DAC_ENABLE_BYPASS_BUFFER(dac) ((dac)->CTL |= DAC_CTL_BYPASS_Msk) 97 98 /** 99 * @brief Disable output voltage buffer. 100 * @param[in] dac Base address of DAC module. 101 * @return None 102 * @details This macro is used to disable output voltage buffer. 103 * \hideinitializer 104 */ 105 #define DAC_DISABLE_BYPASS_BUFFER(dac) ((dac)->CTL &= ~DAC_CTL_BYPASS_Msk) 106 107 /** 108 * @brief Enable the interrupt. 109 * @param[in] dac Base address of DAC module. 110 * @param[in] u32Ch Not used in M480 DAC. 111 * @return None 112 * @details This macro is used to enable DAC interrupt. 113 * \hideinitializer 114 */ 115 #define DAC_ENABLE_INT(dac, u32Ch) ((dac)->CTL |= DAC_CTL_DACIEN_Msk) 116 117 /** 118 * @brief Disable the interrupt. 119 * @param[in] dac Base address of DAC module. 120 * @param[in] u32Ch Not used in M480 DAC. 121 * @return None 122 * @details This macro is used to disable DAC interrupt. 123 * \hideinitializer 124 */ 125 #define DAC_DISABLE_INT(dac, u32Ch) ((dac)->CTL &= ~DAC_CTL_DACIEN_Msk) 126 127 /** 128 * @brief Enable DMA under-run interrupt. 129 * @param[in] dac Base address of DAC module. 130 * @return None 131 * @details This macro is used to enable DMA under-run interrupt. 132 * \hideinitializer 133 */ 134 #define DAC_ENABLE_DMAUDR_INT(dac) ((dac)->CTL |= DAC_CTL_DMAURIEN_Msk) 135 136 /** 137 * @brief Disable DMA under-run interrupt. 138 * @param[in] dac Base address of DAC module. 139 * @return None 140 * @details This macro is used to disable DMA under-run interrupt. 141 * \hideinitializer 142 */ 143 #define DAC_DISABLE_DMAUDR_INT(dac) ((dac)->CTL &= ~DAC_CTL_DMAURIEN_Msk) 144 145 /** 146 * @brief Enable PDMA mode. 147 * @param[in] dac Base address of DAC module. 148 * @return None 149 * @details DAC DMA request is generated when a hardware trigger event occurs while DMAEN (DAC_CTL[2]) is set. 150 * \hideinitializer 151 */ 152 #define DAC_ENABLE_PDMA(dac) ((dac)->CTL |= DAC_CTL_DMAEN_Msk) 153 154 /** 155 * @brief Disable PDMA mode. 156 * @param[in] dac Base address of DAC module. 157 * @return None 158 * @details This macro is used to disable DMA mode. 159 * \hideinitializer 160 */ 161 #define DAC_DISABLE_PDMA(dac) ((dac)->CTL &= ~DAC_CTL_DMAEN_Msk) 162 163 /** 164 * @brief Write data for conversion. 165 * @param[in] dac Base address of DAC module. 166 * @param[in] u32Ch Not used in M480 DAC. 167 * @param[in] u32Data Decides the data for conversion, valid range are between 0~0xFFF. 168 * @return None 169 * @details 12 bit left alignment: user has to load data into DAC_DAT[15:4] bits. 170 * 12 bit right alignment: user has to load data into DAC_DAT[11:0] bits. 171 * \hideinitializer 172 */ 173 #define DAC_WRITE_DATA(dac, u32Ch, u32Data) ((dac)->DAT = (u32Data)) 174 175 /** 176 * @brief Read DAC 12-bit holding data. 177 * @param[in] dac Base address of DAC module. 178 * @param[in] u32Ch Not used in M480 DAC. 179 * @return Return DAC 12-bit holding data. 180 * @details This macro is used to read DAC_DAT register. 181 * \hideinitializer 182 */ 183 #define DAC_READ_DATA(dac, u32Ch) ((dac)->DAT) 184 185 /** 186 * @brief Get the busy state of DAC. 187 * @param[in] dac Base address of DAC module. 188 * @param[in] u32Ch Not used in M480 DAC. 189 * @retval 0 Idle state. 190 * @retval 1 Busy state. 191 * @details This macro is used to read BUSY bit (DAC_STATUS[8]) to get busy state. 192 * \hideinitializer 193 */ 194 #define DAC_IS_BUSY(dac, u32Ch) (((dac)->STATUS & DAC_STATUS_BUSY_Msk) >> DAC_STATUS_BUSY_Pos) 195 196 /** 197 * @brief Get the interrupt flag. 198 * @param[in] dac Base address of DAC module. 199 * @param[in] u32Ch Not used in M480 DAC. 200 * @retval 0 DAC is in conversion state. 201 * @retval 1 DAC conversion finish. 202 * @details This macro is used to read FINISH bit (DAC_STATUS[0]) to get DAC conversion complete finish flag. 203 * \hideinitializer 204 */ 205 #define DAC_GET_INT_FLAG(dac, u32Ch) ((dac)->STATUS & DAC_STATUS_FINISH_Msk) 206 207 /** 208 * @brief Get the DMA under-run flag. 209 * @param[in] dac Base address of DAC module. 210 * @retval 0 No DMA under-run error condition occurred. 211 * @retval 1 DMA under-run error condition occurred. 212 * @details This macro is used to read DMAUDR bit (DAC_STATUS[1]) to get DMA under-run state. 213 * \hideinitializer 214 */ 215 #define DAC_GET_DMAUDR_FLAG(dac) (((dac)->STATUS & DAC_STATUS_DMAUDR_Msk) >> DAC_STATUS_DMAUDR_Pos) 216 217 /** 218 * @brief This macro clear the interrupt status bit. 219 * @param[in] dac Base address of DAC module. 220 * @param[in] u32Ch Not used in M480 DAC. 221 * @return None 222 * @details User writes FINISH bit (DAC_STATUS[0]) to clear DAC conversion complete finish flag. 223 * \hideinitializer 224 */ 225 #define DAC_CLR_INT_FLAG(dac, u32Ch) ((dac)->STATUS = DAC_STATUS_FINISH_Msk) 226 227 /** 228 * @brief This macro clear the DMA under-run flag. 229 * @param[in] dac Base address of DAC module. 230 * @return None 231 * @details User writes DMAUDR bit (DAC_STATUS[1]) to clear DMA under-run flag. 232 * \hideinitializer 233 */ 234 #define DAC_CLR_DMAUDR_FLAG(dac) ((dac)->STATUS = DAC_STATUS_DMAUDR_Msk) 235 236 237 /** 238 * @brief Enable DAC group mode 239 * @param[in] dac Base address of DAC module. 240 * @return None 241 * \hideinitializer 242 */ 243 #define DAC_ENABLE_GROUP_MODE(dac) (DAC0->CTL |= DAC_CTL_GRPEN_Msk) 244 245 /** 246 * @brief Disable DAC group mode 247 * @param[in] dac Base address of DAC module. 248 * @return None 249 * \hideinitializer 250 */ 251 #define DAC_DISABLE_GROUP_MODE(dac) (DAC0->CTL &= ~DAC_CTL_GRPEN_Msk) 252 253 void DAC_Open(DAC_T *dac, uint32_t u32Ch, uint32_t u32TrgSrc); 254 void DAC_Close(DAC_T *dac, uint32_t u32Ch); 255 uint32_t DAC_SetDelayTime(DAC_T *dac, uint32_t u32Delay); 256 257 /*@}*/ /* end of group DAC_EXPORTED_FUNCTIONS */ 258 259 /*@}*/ /* end of group DAC_Driver */ 260 261 /*@}*/ /* end of group Standard_Driver */ 262 263 #ifdef __cplusplus 264 } 265 #endif 266 267 #endif /* __DAC_H__ */ 268 269 /*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ 270
