1 /**************************************************************************//** 2 * @file qspi.h 3 * @version V3.00 4 * @brief M460 series QSPI driver header file 5 * 6 * @copyright SPDX-License-Identifier: Apache-2.0 7 * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __QSPI_H__ 10 #define __QSPI_H__ 11 12 #ifdef __cplusplus 13 extern "C" 14 { 15 #endif 16 17 18 /** @addtogroup Standard_Driver Standard Driver 19 @{ 20 */ 21 22 /** @addtogroup QSPI_Driver QSPI Driver 23 @{ 24 */ 25 26 /** @addtogroup QSPI_EXPORTED_CONSTANTS QSPI Exported Constants 27 @{ 28 */ 29 30 #define QSPI_MODE_0 (QSPI_CTL_TXNEG_Msk) /*!< CLKPOL=0; RXNEG=0; TXNEG=1 \hideinitializer */ 31 #define QSPI_MODE_1 (QSPI_CTL_RXNEG_Msk) /*!< CLKPOL=0; RXNEG=1; TXNEG=0 \hideinitializer */ 32 #define QSPI_MODE_2 (QSPI_CTL_CLKPOL_Msk | QSPI_CTL_RXNEG_Msk) /*!< CLKPOL=1; RXNEG=1; TXNEG=0 \hideinitializer */ 33 #define QSPI_MODE_3 (QSPI_CTL_CLKPOL_Msk | QSPI_CTL_TXNEG_Msk) /*!< CLKPOL=1; RXNEG=0; TXNEG=1 \hideinitializer */ 34 35 #define QSPI_SLAVE (QSPI_CTL_SLAVE_Msk) /*!< Set as slave \hideinitializer */ 36 #define QSPI_MASTER (0x0U) /*!< Set as master \hideinitializer */ 37 38 #define QSPI_SS (QSPI_SSCTL_SS_Msk) /*!< Set SS \hideinitializer */ 39 #define QSPI_SS_ACTIVE_HIGH (QSPI_SSCTL_SSACTPOL_Msk) /*!< SS active high \hideinitializer */ 40 #define QSPI_SS_ACTIVE_LOW (0x0U) /*!< SS active low \hideinitializer */ 41 42 /* QSPI Interrupt Mask */ 43 #define QSPI_UNIT_INT_MASK (0x001U) /*!< Unit transfer interrupt mask \hideinitializer */ 44 #define QSPI_SSACT_INT_MASK (0x002U) /*!< Slave selection signal active interrupt mask \hideinitializer */ 45 #define QSPI_SSINACT_INT_MASK (0x004U) /*!< Slave selection signal inactive interrupt mask \hideinitializer */ 46 #define QSPI_SLVUR_INT_MASK (0x008U) /*!< Slave under run interrupt mask \hideinitializer */ 47 #define QSPI_SLVBE_INT_MASK (0x010U) /*!< Slave bit count error interrupt mask \hideinitializer */ 48 #define QSPI_SLVTO_INT_MASK (0x020U) /*!< Slave mode time-out interrupt mask \hideinitializer */ 49 #define QSPI_TXUF_INT_MASK (0x040U) /*!< Slave TX underflow interrupt mask \hideinitializer */ 50 #define QSPI_FIFO_TXTH_INT_MASK (0x080U) /*!< FIFO TX threshold interrupt mask \hideinitializer */ 51 #define QSPI_FIFO_RXTH_INT_MASK (0x100U) /*!< FIFO RX threshold interrupt mask \hideinitializer */ 52 #define QSPI_FIFO_RXOV_INT_MASK (0x200U) /*!< FIFO RX overrun interrupt mask \hideinitializer */ 53 #define QSPI_FIFO_RXTO_INT_MASK (0x400U) /*!< FIFO RX time-out interrupt mask \hideinitializer */ 54 55 /* QSPI Status Mask */ 56 #define QSPI_BUSY_MASK (0x01U) /*!< Busy status mask \hideinitializer */ 57 #define QSPI_RX_EMPTY_MASK (0x02U) /*!< RX empty status mask \hideinitializer */ 58 #define QSPI_RX_FULL_MASK (0x04U) /*!< RX full status mask \hideinitializer */ 59 #define QSPI_TX_EMPTY_MASK (0x08U) /*!< TX empty status mask \hideinitializer */ 60 #define QSPI_TX_FULL_MASK (0x10U) /*!< TX full status mask \hideinitializer */ 61 #define QSPI_TXRX_RESET_MASK (0x20U) /*!< TX or RX reset status mask \hideinitializer */ 62 #define QSPI_SPIEN_STS_MASK (0x40U) /*!< SPIEN status mask \hideinitializer */ 63 #define QSPI_SSLINE_STS_MASK (0x80U) /*!< QSPIx_SS line status mask \hideinitializer */ 64 65 /* QSPI Status2 Mask */ 66 #define QSPI_SLVBENUM_MASK (0x01U) /*!< Effective bit number of uncompleted RX data status mask \hideinitializer */ 67 68 /*@}*/ /* end of group QSPI_EXPORTED_CONSTANTS */ 69 70 71 /** @addtogroup QSPI_EXPORTED_FUNCTIONS QSPI Exported Functions 72 @{ 73 */ 74 75 /** 76 * @brief Clear the unit transfer interrupt flag. 77 * @param[in] qspi The pointer of the specified QSPI module. 78 * @return None. 79 * @details Write 1 to UNITIF bit of QSPI_STATUS register to clear the unit transfer interrupt flag. 80 * \hideinitializer 81 */ 82 #define QSPI_CLR_UNIT_TRANS_INT_FLAG(qspi) ( (qspi)->STATUS = QSPI_STATUS_UNITIF_Msk ) 83 84 /** 85 * @brief Disable 2-bit Transfer mode. 86 * @param[in] qspi The pointer of the specified QSPI module. 87 * @return None. 88 * @details Clear TWOBIT bit of QSPI_CTL register to disable 2-bit Transfer mode. 89 * \hideinitializer 90 */ 91 #define QSPI_DISABLE_2BIT_MODE(qspi) ( (qspi)->CTL &= ~QSPI_CTL_TWOBIT_Msk ) 92 93 /** 94 * @brief Disable Slave 3-wire mode. 95 * @param[in] qspi The pointer of the specified QSPI module. 96 * @return None. 97 * @details Clear SLV3WIRE bit of QSPI_SSCTL register to disable Slave 3-wire mode. 98 * \hideinitializer 99 */ 100 #define QSPI_DISABLE_3WIRE_MODE(qspi) ( (qspi)->SSCTL &= ~QSPI_SSCTL_SLV3WIRE_Msk ) 101 102 /** 103 * @brief Disable Dual I/O mode. 104 * @param[in] qspi The pointer of the specified QSPI module. 105 * @return None. 106 * @details Clear DUALIOEN bit of QSPI_CTL register to disable Dual I/O mode. 107 * \hideinitializer 108 */ 109 #define QSPI_DISABLE_DUAL_MODE(qspi) ( (qspi)->CTL &= ~QSPI_CTL_DUALIOEN_Msk ) 110 111 /** 112 * @brief Disable Quad I/O mode. 113 * @param[in] qspi The pointer of the specified QSPI module. 114 * @return None. 115 * @details Clear QUADIOEN bit of QSPI_CTL register to disable Quad I/O mode. 116 * \hideinitializer 117 */ 118 #define QSPI_DISABLE_QUAD_MODE(qspi) ( (qspi)->CTL &= ~QSPI_CTL_QUADIOEN_Msk ) 119 120 /** 121 * @brief Disable TX DTR mode. 122 * @param[in] qspi The pointer of the specified QSPI module. 123 * @return None. 124 * @details Clear TXDTREN bit of QSPI_CTL register to disable TX DTR mode. 125 * \hideinitializer 126 */ 127 #define QSPI_DISABLE_TXDTR_MODE(qspi) ( (qspi)->CTL &= ~QSPI_CTL_TXDTREN_Msk ) 128 129 /** 130 * @brief Enable 2-bit Transfer mode. 131 * @param[in] qspi The pointer of the specified QSPI module. 132 * @return None. 133 * @details Set TWOBIT bit of QSPI_CTL register to enable 2-bit Transfer mode. 134 * \hideinitializer 135 */ 136 #define QSPI_ENABLE_2BIT_MODE(qspi) ( (qspi)->CTL |= QSPI_CTL_TWOBIT_Msk ) 137 138 /** 139 * @brief Enable Slave 3-wire mode. 140 * @param[in] qspi The pointer of the specified QSPI module. 141 * @return None. 142 * @details Set SLV3WIRE bit of QSPI_SSCTL register to enable Slave 3-wire mode. 143 * \hideinitializer 144 */ 145 #define QSPI_ENABLE_3WIRE_MODE(qspi) ( (qspi)->SSCTL |= QSPI_SSCTL_SLV3WIRE_Msk ) 146 147 /** 148 * @brief Enable Dual input mode. 149 * @param[in] qspi The pointer of the specified QSPI module. 150 * @return None. 151 * @details Clear DATDIR bit and set DUALIOEN bit of QSPI_CTL register to enable Dual input mode. 152 * \hideinitializer 153 */ 154 #define QSPI_ENABLE_DUAL_INPUT_MODE(qspi) ( (qspi)->CTL = ((qspi)->CTL & (~QSPI_CTL_DATDIR_Msk)) | QSPI_CTL_DUALIOEN_Msk ) 155 156 /** 157 * @brief Enable Dual output mode. 158 * @param[in] qspi The pointer of the specified QSPI module. 159 * @return None. 160 * @details Set DATDIR bit and DUALIOEN bit of QSPI_CTL register to enable Dual output mode. 161 * \hideinitializer 162 */ 163 #define QSPI_ENABLE_DUAL_OUTPUT_MODE(qspi) ( (qspi)->CTL |= (QSPI_CTL_DATDIR_Msk | QSPI_CTL_DUALIOEN_Msk) ) 164 165 /** 166 * @brief Enable Quad input mode. 167 * @param[in] qspi The pointer of the specified QSPI module. 168 * @return None. 169 * @details Clear DATDIR bit and set QUADIOEN bit of QSPI_CTL register to enable Quad input mode. 170 * \hideinitializer 171 */ 172 #define QSPI_ENABLE_QUAD_INPUT_MODE(qspi) ( (qspi)->CTL = ((qspi)->CTL & (~QSPI_CTL_DATDIR_Msk)) | QSPI_CTL_QUADIOEN_Msk ) 173 174 /** 175 * @brief Enable Quad output mode. 176 * @param[in] qspi The pointer of the specified QSPI module. 177 * @return None. 178 * @details Set DATDIR bit and QUADIOEN bit of QSPI_CTL register to enable Quad output mode. 179 * \hideinitializer 180 */ 181 #define QSPI_ENABLE_QUAD_OUTPUT_MODE(qspi) ( (qspi)->CTL |= (QSPI_CTL_DATDIR_Msk | QSPI_CTL_QUADIOEN_Msk) ) 182 183 /** 184 * @brief Enable TX DTR mode. 185 * @param[in] qspi The pointer of the specified QSPI module. 186 * @return None. 187 * @details Set TXDTREN bit of QSPI_CTL register to enable TX DTR mode. 188 * \hideinitializer 189 */ 190 #define QSPI_ENABLE_TXDTR_MODE(qspi) ( (qspi)->CTL |= QSPI_CTL_TXDTREN_Msk ) 191 192 /** 193 * @brief Trigger RX PDMA function. 194 * @param[in] qspi The pointer of the specified QSPI module. 195 * @return None. 196 * @details Set RXPDMAEN bit of QSPI_PDMACTL register to enable RX PDMA transfer function. 197 * \hideinitializer 198 */ 199 #define QSPI_TRIGGER_RX_PDMA(qspi) ( (qspi)->PDMACTL |= QSPI_PDMACTL_RXPDMAEN_Msk ) 200 201 /** 202 * @brief Trigger TX PDMA function. 203 * @param[in] qspi The pointer of the specified QSPI module. 204 * @return None. 205 * @details Set TXPDMAEN bit of QSPI_PDMACTL register to enable TX PDMA transfer function. 206 * \hideinitializer 207 */ 208 #define QSPI_TRIGGER_TX_PDMA(qspi) ( (qspi)->PDMACTL |= QSPI_PDMACTL_TXPDMAEN_Msk ) 209 210 /** 211 * @brief Trigger TX and RX PDMA function. 212 * @param[in] qspi The pointer of the specified QSPI module. 213 * @return None. 214 * @details Set TXPDMAEN bit and RXPDMAEN bit of QSPI_PDMACTL register to enable TX and RX PDMA transfer function. 215 * \hideinitializer 216 */ 217 #define QSPI_TRIGGER_TX_RX_PDMA(qspi) ( (qspi)->PDMACTL |= (QSPI_PDMACTL_TXPDMAEN_Msk | QSPI_PDMACTL_RXPDMAEN_Msk) ) 218 219 /** 220 * @brief Disable RX PDMA transfer. 221 * @param[in] qspi The pointer of the specified QSPI module. 222 * @return None. 223 * @details Clear RXPDMAEN bit of QSPI_PDMACTL register to disable RX PDMA transfer function. 224 * \hideinitializer 225 */ 226 #define QSPI_DISABLE_RX_PDMA(qspi) ( (qspi)->PDMACTL &= ~QSPI_PDMACTL_RXPDMAEN_Msk ) 227 228 /** 229 * @brief Disable TX PDMA transfer. 230 * @param[in] qspi The pointer of the specified QSPI module. 231 * @return None. 232 * @details Clear TXPDMAEN bit of QSPI_PDMACTL register to disable TX PDMA transfer function. 233 * \hideinitializer 234 */ 235 #define QSPI_DISABLE_TX_PDMA(qspi) ( (qspi)->PDMACTL &= ~QSPI_PDMACTL_TXPDMAEN_Msk ) 236 237 /** 238 * @brief Disable TX and RX PDMA transfer. 239 * @param[in] qspi The pointer of the specified QSPI module. 240 * @return None. 241 * @details Clear TXPDMAEN bit and RXPDMAEN bit of QSPI_PDMACTL register to disable TX and RX PDMA transfer function. 242 * \hideinitializer 243 */ 244 #define QSPI_DISABLE_TX_RX_PDMA(qspi) ( (qspi)->PDMACTL &= ~(QSPI_PDMACTL_TXPDMAEN_Msk | QSPI_PDMACTL_RXPDMAEN_Msk) ) 245 246 /** 247 * @brief Get the count of available data in RX FIFO. 248 * @param[in] qspi The pointer of the specified QSPI module. 249 * @return The count of available data in RX FIFO. 250 * @details Read RXCNT (QSPI_STATUS[27:24]) to get the count of available data in RX FIFO. 251 * \hideinitializer 252 */ 253 #define QSPI_GET_RX_FIFO_COUNT(qspi) ( ((qspi)->STATUS & QSPI_STATUS_RXCNT_Msk) >> QSPI_STATUS_RXCNT_Pos ) 254 255 /** 256 * @brief Get the RX FIFO empty flag. 257 * @param[in] qspi The pointer of the specified QSPI module. 258 * @retval 0 RX FIFO is not empty. 259 * @retval 1 RX FIFO is empty. 260 * @details Read RXEMPTY bit of QSPI_STATUS register to get the RX FIFO empty flag. 261 * \hideinitializer 262 */ 263 #define QSPI_GET_RX_FIFO_EMPTY_FLAG(qspi) ( ((qspi)->STATUS & QSPI_STATUS_RXEMPTY_Msk) >> QSPI_STATUS_RXEMPTY_Pos ) 264 265 /** 266 * @brief Get the TX FIFO empty flag. 267 * @param[in] qspi The pointer of the specified QSPI module. 268 * @retval 0 TX FIFO is not empty. 269 * @retval 1 TX FIFO is empty. 270 * @details Read TXEMPTY bit of QSPI_STATUS register to get the TX FIFO empty flag. 271 * \hideinitializer 272 */ 273 #define QSPI_GET_TX_FIFO_EMPTY_FLAG(qspi) ( ((qspi)->STATUS & QSPI_STATUS_TXEMPTY_Msk) >> QSPI_STATUS_TXEMPTY_Pos ) 274 275 /** 276 * @brief Get the TX FIFO full flag. 277 * @param[in] qspi The pointer of the specified QSPI module. 278 * @retval 0 TX FIFO is not full. 279 * @retval 1 TX FIFO is full. 280 * @details Read TXFULL bit of QSPI_STATUS register to get the TX FIFO full flag. 281 * \hideinitializer 282 */ 283 #define QSPI_GET_TX_FIFO_FULL_FLAG(qspi) ( ((qspi)->STATUS & QSPI_STATUS_TXFULL_Msk) >> QSPI_STATUS_TXFULL_Pos ) 284 285 /** 286 * @brief Get the datum read from RX register. 287 * @param[in] qspi The pointer of the specified QSPI module. 288 * @return Data in RX register. 289 * @details Read QSPI_RX register to get the received datum. 290 * \hideinitializer 291 */ 292 #define QSPI_READ_RX(qspi) ( (qspi)->RX ) 293 294 /** 295 * @brief Write datum to TX register. 296 * @param[in] qspi The pointer of the specified QSPI module. 297 * @param[in] u32TxData The datum which user attempt to transfer through QSPI bus. 298 * @return None. 299 * @details Write u32TxData to QSPI_TX register. 300 * \hideinitializer 301 */ 302 #define QSPI_WRITE_TX(qspi, u32TxData) ( (qspi)->TX = (u32TxData) ) 303 304 /** 305 * @brief Set QSPIx_SS pin to high state. 306 * @param[in] qspi The pointer of the specified QSPI module. 307 * @return None. 308 * @details Disable automatic slave selection function and set QSPIx_SS pin to high state. 309 * \hideinitializer 310 */ 311 #define QSPI_SET_SS_HIGH(qspi) ( (qspi)->SSCTL = ((qspi)->SSCTL & (~QSPI_SSCTL_AUTOSS_Msk)) | (QSPI_SSCTL_SSACTPOL_Msk | QSPI_SSCTL_SS_Msk) ) 312 313 /** 314 * @brief Set QSPIx_SS pin to low state. 315 * @param[in] qspi The pointer of the specified QSPI module. 316 * @return None. 317 * @details Disable automatic slave selection function and set QSPIx_SS pin to low state. 318 * \hideinitializer 319 */ 320 #define QSPI_SET_SS_LOW(qspi) ( (qspi)->SSCTL = ((qspi)->SSCTL & (~(QSPI_SSCTL_AUTOSS_Msk | QSPI_SSCTL_SSACTPOL_Msk))) | QSPI_SSCTL_SS_Msk ) 321 322 /** 323 * @brief Enable Byte Reorder function. 324 * @param[in] qspi The pointer of the specified QSPI module. 325 * @return None. 326 * @details Enable Byte Reorder function. The suspend interval depends on the setting of SUSPITV (QSPI_CTL[7:4]). 327 * \hideinitializer 328 */ 329 #define QSPI_ENABLE_BYTE_REORDER(qspi) ( (qspi)->CTL |= QSPI_CTL_REORDER_Msk ) 330 331 /** 332 * @brief Disable Byte Reorder function. 333 * @param[in] qspi The pointer of the specified QSPI module. 334 * @return None. 335 * @details Clear REORDER bit field of QSPI_CTL register to disable Byte Reorder function. 336 * \hideinitializer 337 */ 338 #define QSPI_DISABLE_BYTE_REORDER(qspi) ( (qspi)->CTL &= ~QSPI_CTL_REORDER_Msk ) 339 340 /** 341 * @brief Set the length of suspend interval. 342 * @param[in] qspi The pointer of the specified QSPI module. 343 * @param[in] u32SuspCycle Decides the length of suspend interval. It could be 0 ~ 15. 344 * @return None. 345 * @details Set the length of suspend interval according to u32SuspCycle. 346 * The length of suspend interval is ((u32SuspCycle + 0.5) * the length of one QSPI bus clock cycle). 347 * \hideinitializer 348 */ 349 #define QSPI_SET_SUSPEND_CYCLE(qspi, u32SuspCycle) ( (qspi)->CTL = ((qspi)->CTL & ~QSPI_CTL_SUSPITV_Msk) | ((u32SuspCycle) << QSPI_CTL_SUSPITV_Pos) ) 350 351 /** 352 * @brief Set the QSPI transfer sequence with LSB first. 353 * @param[in] qspi The pointer of the specified QSPI module. 354 * @return None. 355 * @details Set LSB bit of QSPI_CTL register to set the QSPI transfer sequence with LSB first. 356 * \hideinitializer 357 */ 358 #define QSPI_SET_LSB_FIRST(qspi) ( (qspi)->CTL |= QSPI_CTL_LSB_Msk ) 359 360 /** 361 * @brief Set the QSPI transfer sequence with MSB first. 362 * @param[in] qspi The pointer of the specified QSPI module. 363 * @return None. 364 * @details Clear LSB bit of QSPI_CTL register to set the QSPI transfer sequence with MSB first. 365 * \hideinitializer 366 */ 367 #define QSPI_SET_MSB_FIRST(qspi) ( (qspi)->CTL &= ~QSPI_CTL_LSB_Msk ) 368 369 /** 370 * @brief Set the data width of a QSPI transaction. 371 * @param[in] qspi The pointer of the specified QSPI module. 372 * @param[in] u32Width The bit width of one transaction. 373 * @return None. 374 * @details The data width can be 8 ~ 32 bits. 375 * \hideinitializer 376 */ 377 #define QSPI_SET_DATA_WIDTH(qspi, u32Width) ( (qspi)->CTL = ((qspi)->CTL & ~QSPI_CTL_DWIDTH_Msk) | (((u32Width) & 0x1F) << QSPI_CTL_DWIDTH_Pos) ) 378 379 /** 380 * @brief Get the QSPI busy state. 381 * @param[in] qspi The pointer of the specified QSPI module. 382 * @retval 0 QSPI controller is not busy. 383 * @retval 1 QSPI controller is busy. 384 * @details This macro will return the busy state of QSPI controller. 385 * \hideinitializer 386 */ 387 #define QSPI_IS_BUSY(qspi) ( ((qspi)->STATUS & QSPI_STATUS_BUSY_Msk) >> QSPI_STATUS_BUSY_Pos ) 388 389 /** 390 * @brief Enable QSPI controller. 391 * @param[in] qspi The pointer of the specified QSPI module. 392 * @return None. 393 * @details Set SPIEN (QSPI_CTL[0]) to enable QSPI controller. 394 * \hideinitializer 395 */ 396 #define QSPI_ENABLE(qspi) ( (qspi)->CTL |= QSPI_CTL_SPIEN_Msk ) 397 398 /** 399 * @brief Disable QSPI controller. 400 * @param[in] qspi The pointer of the specified QSPI module. 401 * @return None. 402 * @details Clear SPIEN (QSPI_CTL[0]) to disable QSPI controller. 403 * \hideinitializer 404 */ 405 #define QSPI_DISABLE(qspi) ( (qspi)->CTL &= ~QSPI_CTL_SPIEN_Msk ) 406 407 408 409 /* Function prototype declaration */ 410 uint32_t QSPI_Open(QSPI_T *qspi, uint32_t u32MasterSlave, uint32_t u32QSPIMode, uint32_t u32DataWidth, uint32_t u32BusClock); 411 void QSPI_Close(QSPI_T *qspi); 412 void QSPI_ClearRxFIFO(QSPI_T *qspi); 413 void QSPI_ClearTxFIFO(QSPI_T *qspi); 414 void QSPI_DisableAutoSS(QSPI_T *qspi); 415 void QSPI_EnableAutoSS(QSPI_T *qspi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel); 416 uint32_t QSPI_SetBusClock(QSPI_T *qspi, uint32_t u32BusClock); 417 void QSPI_SetFIFO(QSPI_T *qspi, uint32_t u32TxThreshold, uint32_t u32RxThreshold); 418 uint32_t QSPI_GetBusClock(QSPI_T *qspi); 419 void QSPI_EnableInt(QSPI_T *qspi, uint32_t u32Mask); 420 void QSPI_DisableInt(QSPI_T *qspi, uint32_t u32Mask); 421 uint32_t QSPI_GetIntFlag(QSPI_T *qspi, uint32_t u32Mask); 422 void QSPI_ClearIntFlag(QSPI_T *qspi, uint32_t u32Mask); 423 uint32_t QSPI_GetStatus(QSPI_T *qspi, uint32_t u32Mask); 424 uint32_t QSPI_GetStatus2(QSPI_T *qspi, uint32_t u32Mask); 425 426 427 /*@}*/ /* end of group QSPI_EXPORTED_FUNCTIONS */ 428 429 /*@}*/ /* end of group QSPI_Driver */ 430 431 /*@}*/ /* end of group Standard_Driver */ 432 433 #ifdef __cplusplus 434 } 435 #endif 436 437 #endif /* __QSPI_H__ */ 438
