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Searched refs:uint32_t (Results 1 – 25 of 713) sorted by relevance

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/hal_infineon-latest/mtb-pdl-cat1/drivers/third_party/ethernet/include/
Demac_regs.h27 volatile uint32_t network_control; /* 0x0 - 0x4 */
28 volatile uint32_t network_config; /* 0x4 - 0x8 */
29 volatile uint32_t network_status; /* 0x8 - 0xc */
30 volatile uint32_t user_io_register; /* 0xc - 0x10 */
31 volatile uint32_t dma_config; /* 0x10 - 0x14 */
32 volatile uint32_t transmit_status; /* 0x14 - 0x18 */
33 volatile uint32_t receive_q_ptr; /* 0x18 - 0x1c */
34 volatile uint32_t transmit_q_ptr; /* 0x1c - 0x20 */
35 volatile uint32_t receive_status; /* 0x20 - 0x24 */
36 volatile uint32_t int_status; /* 0x24 - 0x28 */
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Demac_regs_macro.h33 ((uint32_t)(src)\
36 ((uint32_t)(src)\
40 ~0x00000001U) | ((uint32_t)(src) &\
43 (!(((uint32_t)(src)\
47 ~0x00000001U) | (uint32_t)(1)
50 ~0x00000001U) | (uint32_t)(0)
58 (((uint32_t)(src)\
61 (((uint32_t)(src)\
65 ~0x00000002U) | (((uint32_t)(src) <<\
68 (!((((uint32_t)(src)\
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Dcedi.h496 typedef void (*CEDI_CbTxEvent)(void* pD, uint32_t event, uint8_t queueNum);
505 typedef void (*CEDI_CbTxError)(void* pD, uint32_t error, uint8_t queueNum);
519 typedef void (*CEDI_CbRxError)(void* pD, uint32_t error, uint8_t queueNum);
554 typedef void (*CEDI_CbTsuEvent)(void* pD, uint32_t event);
562 typedef void (*CEDI_CbPauseEvent)(void* pD, uint32_t event);
572 typedef void (*CEDI_CbPtpPriFrameTx)(void* pD, uint32_t type, struct CEDI_1588TimerVal* time);
582 typedef void (*CEDI_CbPtpPeerFrameTx)(void* pD, uint32_t type, struct CEDI_1588TimerVal* time);
592 typedef void (*CEDI_CbPtpPriFrameRx)(void* pD, uint32_t type, struct CEDI_1588TimerVal* time);
602 typedef void (*CEDI_CbPtpPeerFrameRx)(void* pD, uint32_t type, struct CEDI_1588TimerVal* time);
661 uint32_t intrEnable;
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/hal_infineon-latest/wifi-host-driver/WiFi_Host_Driver/src/include/
Dwhd_wlioctl.h56 uint32_t packetId;
62 uint32_t channel;
73 uint32_t mactime;
74 uint32_t rate;
121 uint32_t cnt_rxundec;
122 uint32_t cnt_rxframe;
133 uint32_t SSID_len;
163 uint32_t version;
171 uint32_t buflen;
172 uint32_t version;
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/hal_infineon-latest/mtb-pdl-cat1/drivers/include/
Dcy_crypto_core_hw_vu.h83 #define CY_CRYPTO_VU_STATUS_CARRY_BIT (uint32_t)(((uint32_t)1u) << CY_CRYPTO_VU_STATUS_CARRY)
84 #define CY_CRYPTO_VU_STATUS_EVEN_BIT (uint32_t)(((uint32_t)1u) << CY_CRYPTO_VU_STATUS_EVEN)
85 #define CY_CRYPTO_VU_STATUS_ZERO_BIT (uint32_t)(((uint32_t)1u) << CY_CRYPTO_VU_STATUS_ZERO)
86 #define CY_CRYPTO_VU_STATUS_ONE_BIT (uint32_t)(((uint32_t)1u) << CY_CRYPTO_VU_STATUS_ONE)
87 #define CY_CRYPTO_VU_STATUS_MASK (uint32_t)(CY_CRYPTO_VU_STATUS_CARRY_BIT | CY_CRYPTO_VU_STA…
90 #define CY_CRYPTO_VU_REG_BIT(nreg) (((uint32_t)1u) << (nreg))
206 __STATIC_INLINE void CY_CRYPTO_VU_SAVE_REG (CRYPTO_Type *base, uint32_t rsrc, uint32_t *data);
207 __STATIC_INLINE void CY_CRYPTO_VU_RESTORE_REG (CRYPTO_Type *base, uint32_t rdst, uint32_t data);
208 …TIC_INLINE void CY_CRYPTO_VU_SET_REG (CRYPTO_Type *base, uint32_t rdst, uint32_t data, uint32_t si…
211 __STATIC_INLINE void CY_CRYPTO_VU_COND_MOV_REG_TO_STATUS (CRYPTO_Type *base, uint32_t cc, uint32_t … in CY_CRYPTO_VU_COND_MOV_REG_TO_STATUS()
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Dcy_flash_srom.h202 uint32_t : 8;
203 uint32_t IdType : 8;
204 uint32_t : 8;
205 uint32_t Opcode : 8;
211 uint32_t resv[3];
217 uint32_t FamilyIdLow : 8;
218 uint32_t FamilyIdHigh : 8;
219 uint32_t MinorRevisionID : 4;
220 uint32_t MajorRevisionId : 4;
221 uint32_t : 4;
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Dcy_tcpwm_quaddec.h122 uint32_t resolution;
124 uint32_t interruptSources;
126 uint32_t indexInputMode;
128 uint32_t indexInput;
130 uint32_t stopInputMode;
132 uint32_t stopInput;
134 uint32_t phiAInput;
136 uint32_t phiBInput;
139 uint32_t phiAInputMode;
141 uint32_t phiBInputMode;
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Dcy_usbfs_dev_drv_reg.h105 __STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetSieInterruptStatus(USBFS_Type const *base);
106 __STATIC_INLINE void Cy_USBFS_Dev_Drv_SetSieInterruptMask (USBFS_Type *base, uint32_t mask);
107 __STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetSieInterruptMask (USBFS_Type const *base);
108 __STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetSieInterruptStatusMasked(USBFS_Type const *base);
109 __STATIC_INLINE void Cy_USBFS_Dev_Drv_ClearSieInterrupt (USBFS_Type *base, uint32_t mask);
110 __STATIC_INLINE void Cy_USBFS_Dev_Drv_SetSieInterrupt (USBFS_Type *base, uint32_t mask);
119 __STATIC_INLINE void Cy_USBFS_Dev_Drv_WriteEp0Mode(USBFS_Type *base, uint32_t mode);
120 __STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_ReadEp0Mode(USBFS_Type const *base);
122 __STATIC_INLINE void Cy_USBFS_Dev_Drv_SetEp0Count(USBFS_Type *base, uint32_t count, uint32_t to…
123 __STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetEp0Count(USBFS_Type const *base);
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Dcy_gpio.h310 uint32_t out; /**< Initial output data for the IO pins in the port */
311 uint32_t intrMask; /**< Interrupt enable mask for the port interrupt */
312 uint32_t intrCfg; /**< Port pin interrupt edge detection configuration */
313 uint32_t cfg; /**< Port pin drive modes and input buffer enable configuration */
314 uint32_t cfgIn; /**< Port pin input buffer configuration */
315 uint32_t cfgOut; /**< Port pin output buffer configuration */
316 uint32_t cfgSIO; /**< Port SIO pins configuration */
317 uint32_t sel0Active; /**< HSIOM selection for port pins 0,1,2,3 */
318 uint32_t sel1Active; /**< HSIOM selection for port pins 4,5,6,7 */
324 uint32_t cfgSlew; /**< Port slew rate configuration */
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Dcy_tcpwm_counter.h137 uint32_t period; /**< Sets the period of the counter */
139 uint32_t clockPrescaler;
140 … uint32_t runMode; /**< Sets the run mode. See \ref group_tcpwm_counter_run_modes */
141 …uint32_t countDirection; /**< Sets the counter direction. See \ref group_tcpwm_counter_dire…
143 uint32_t compareOrCapture;
144 uint32_t compare0; /**< Sets the value for Compare0*/
145 uint32_t compare1; /**< Sets the value for Compare1*/
148 uint32_t interruptSources;
149 …uint32_t captureInputMode; /**< Configures how the capture input behaves. See \ref group_tcpw…
151 uint32_t captureInput;
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Dcy_sysclk.h1138 extern uint32_t cySysClkExtFreq;
1159 void Cy_SysClk_ExtClkSetFrequency(uint32_t freq);
1175 uint32_t Cy_SysClk_ExtClkGetFrequency(void);
1236 uint32_t praClkEcofreq; /**< freq */
1237 uint32_t praCsum; /**< cSum */
1238 uint32_t praEsr; /**< esr */
1239 uint32_t praDriveLevel; /**< drivelevel */
1253 uint32_t ecoClkfreq; /**< freq in Hz */
1254 uint32_t ecoCtrim; /**< ctrim */
1255 uint32_t ecoGtrim; /**< gtrim */
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Dcy_tcpwm_shiftreg.h119 uint32_t clockPrescaler; /**< Sets the clock prescaler inside the TCWPM block.*/
120 uint32_t tapsEnabled; /**< In shift register this sets the enabled taps. */
121 uint32_t compare0; /**< Sets the value for Compare 0. */
122 uint32_t compareBuf0; /**< Sets the value for the buffered Compare 0. */
124 uint32_t compare1; /**< Sets the value for Compare 1. */
125 uint32_t compareBuf1; /**< Sets the value for the buffered Compare 1. */
127 …uint32_t interruptSources; /**< Enables an interrupt on the terminal count, capture or compar…
128 uint32_t invertShiftRegOut; /**< Inverts the ShiftReg output.*/
129 uint32_t invertShiftRegOutN; /**< Inverts the ShiftReg compliment output.*/
130 uint32_t reloadInputMode; /**< Configures how the reload input behaves. */
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Dcy_cryptolite_vu.h48 void Cy_Cryptolite_Vu_lsl (uint8_t* p_z,uint32_t word_size_z,uint8_t* p_a, uint32_t word_size_a,uin…
49 void Cy_Cryptolite_Vu_clr (uint8_t* p_z,uint32_t word_size);
56 __STATIC_INLINE uint32_t Cy_Cryptolite_Vu_memcmp (void const *src0, void const *src1, uint32_t size) in Cy_Cryptolite_Vu_memcmp()
58 uint32_t i,diff; in Cy_Cryptolite_Vu_memcmp()
67 diff |= (uint32_t)s0[i] ^ (uint32_t)s1[i]; in Cy_Cryptolite_Vu_memcmp()
79 __STATIC_INLINE void Cy_Cryptolite_Vu_memcpy (void *dest, const void *src, uint32_t size) in Cy_Cryptolite_Vu_memcpy()
81 uint32_t i; in Cy_Cryptolite_Vu_memcpy()
93 __STATIC_INLINE void Cy_Cryptolite_Vu_memset (void *dest, uint8_t data, uint32_t size) in Cy_Cryptolite_Vu_memset()
95 uint32_t i; in Cy_Cryptolite_Vu_memset()
109 uint32_t* p_a_uint32 = (uint32_t *) p_a; in Cy_Cryptolite_Vu_test_even()
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/hal_infineon-latest/wifi-host-driver/WiFi_Host_Driver/src/bus_protocols/
Dwhd_sdio.h31 #define SDIO_CORE(wd) ( (uint32_t)(GET_C_VAR(wd, SDIOD_CORE_BASE_ADDRESS) + 0x00…
32 #define SDIO_INT_STATUS(wd) ( (uint32_t)(GET_C_VAR(wd, SDIOD_CORE_BASE_ADDRESS) + 0x20…
33 #define SDIO_TO_SB_MAILBOX(wd) ( (uint32_t)(GET_C_VAR(wd, SDIOD_CORE_BASE_ADDRESS) + 0x40…
34 #define SDIO_TO_SB_MAILBOX_DATA(wd) ( (uint32_t)(GET_C_VAR(wd, SDIOD_CORE_BASE_ADDRESS) + 0x48…
35 #define SDIO_TO_HOST_MAILBOX_DATA(wd) ( (uint32_t)(GET_C_VAR(wd, SDIOD_CORE_BASE_ADDRESS) + 0x4C…
36 #define SDIO_INT_HOST_MASK(wd) ( (uint32_t)(GET_C_VAR(wd, SDIOD_CORE_BASE_ADDRESS) + 0x24…
37 #define SDIO_FUNCTION_INT_MASK(wd) ( (uint32_t)(GET_C_VAR(wd, SDIOD_CORE_BASE_ADDRESS) + 0x34…
43 #define SDIOD_CCCR_REV ( (uint32_t)0x00 ) /* CCCR/SDIO Revision */
44 #define SDIOD_CCCR_SDREV ( (uint32_t)0x01 ) /* SD Revision */
45 #define SDIOD_CCCR_IOEN ( (uint32_t)0x02 ) /* I/O Enable */
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Dwhd_spi.h29 #define SPI_FRAME_CONTROL ( (uint32_t)0x1000D )
32 #define SPI_BUS_CONTROL ( (uint32_t)0x0000 )
33 #define SPI_RESPONSE_DELAY ( (uint32_t)0x0001 )
34 #define SPI_STATUS_ENABLE ( (uint32_t)0x0002 )
35 #define SPI_RESET_BP ( (uint32_t)0x0003 ) /* (corerev >= 1) */
36 #define SPI_INTERRUPT_REGISTER ( (uint32_t)0x0004 ) /* 16 bits - Interrupt status */
37 #define SPI_INTERRUPT_ENABLE_REGISTER ( (uint32_t)0x0006 ) /* 16 bits - Interrupt mask */
38 #define SPI_STATUS_REGISTER ( (uint32_t)0x0008 ) /* 32 bits */
39 #define SPI_FUNCTION1_INFO ( (uint32_t)0x000C ) /* 16 bits */
40 #define SPI_FUNCTION2_INFO ( (uint32_t)0x000E ) /* 16 bits */
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/hal_infineon-latest/XMCLib/drivers/src/
Dxmc_vadc.c166 COMPARATOR->ORCCTRL = (uint32_t)0xFF; in XMC_VADC_GLOBAL_EnableModule()
198 uint32_t reg; in XMC_VADC_GLOBAL_Init()
205 global_ptr->CLC = (uint32_t)(config->clc); in XMC_VADC_GLOBAL_Init()
210 …global_ptr->GLOBCFG = (uint32_t)(config->clock_config.globcfg | (uint32_t)(VADC_GLOBCFG_DIVWC_Msk… in XMC_VADC_GLOBAL_Init()
214 global_ptr->GLOBICLASS[0] = (uint32_t)(config->class0.globiclass); in XMC_VADC_GLOBAL_Init()
217 global_ptr->GLOBICLASS[1] = (uint32_t)(config->class1.globiclass); in XMC_VADC_GLOBAL_Init()
221 global_ptr->GLOBRCR = (uint32_t)(config->globrcr); in XMC_VADC_GLOBAL_Init()
226 global_ptr->GLOBBOUND = (uint32_t)(config->globbound); in XMC_VADC_GLOBAL_Init()
246 … const XMC_VADC_GROUP_CONV_t conv_type, const uint32_t set_num) in XMC_VADC_GLOBAL_InputClassInit()
259 … (uint32_t)(VADC_GLOBICLASS_CMS_Msk | VADC_GLOBICLASS_STCS_Msk); in XMC_VADC_GLOBAL_InputClassInit()
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Dxmc4_flash.c91 void XMC_FLASH_lLoadPageCommand(uint32_t low_word, uint32_t high_word);
92 void XMC_FLASH_lWritePageCommand(uint32_t *page_start_address);
93 void XMC_FLASH_lWriteUCBPageCommand(uint32_t *page_start_address);
94 void XMC_FLASH_lEraseSectorCommand(uint32_t *sector_start_address);
95 void XMC_FLASH_lDisableSectorWriteProtectionCommand(uint32_t user, uint32_t password_0, uint32_t pa…
96 void XMC_FLASH_lDisableReadProtectionCommand(uint32_t password_0, uint32_t password_1);
98 void XMC_FLASH_lErasePhysicalSectorCommand(uint32_t *sector_start_address);
106 volatile uint32_t *address; in XMC_FLASH_lEnterPageModeCommand()
108 address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x5554U); in XMC_FLASH_lEnterPageModeCommand()
109 *address = (uint32_t)0x50U; in XMC_FLASH_lEnterPageModeCommand()
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Dxmc4_scu.c199 __WEAK uint32_t OSCHP_GetFrequency(void) in OSCHP_GetFrequency()
206 static void XMC_SCU_lDelay(uint32_t cycles);
212 void XMC_SCU_lDelay(uint32_t delay) in XMC_SCU_lDelay()
214 uint32_t i; in XMC_SCU_lDelay()
217 delay = delay * (uint32_t)(SystemCoreClock / FREQ_1MHZ); in XMC_SCU_lDelay()
228 SCU_INTERRUPT->SRMSK |= (uint32_t)event; in XMC_SCU_INTERRUPT_EnableEvent()
234 SCU_INTERRUPT->SRMSK &= (uint32_t)~event; in XMC_SCU_INTERRUPT_DisableEvent()
240 SCU_INTERRUPT->SRSET |= (uint32_t)event; in XMC_SCU_INTERRUPT_TriggerEvent()
252 SCU_INTERRUPT->SRCLR = (uint32_t)event; in XMC_SCU_INTERRUPT_ClearEventStatus()
257 uint32_t XMC_SCU_GetBootMode(void) in XMC_SCU_GetBootMode()
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Dxmc_can.c93 __STATIC_INLINE uint32_t max(uint32_t a, uint32_t b) in max()
98 __STATIC_INLINE uint32_t min(uint32_t a, uint32_t b) in min()
127 uint32_t prescaler; in XMC_CAN_NODE_NominalBitTimeConfigureEx()
128 uint32_t div8 = 0; in XMC_CAN_NODE_NominalBitTimeConfigureEx()
131 uint32_t fcan_div = bit_time_config->can_frequency / bit_time_config->baudrate; in XMC_CAN_NODE_NominalBitTimeConfigureEx()
134 uint32_t ntq = XMC_CAN_NODE_MAX_NTQ; in XMC_CAN_NODE_NominalBitTimeConfigureEx()
135 uint32_t tseg1 = 0; in XMC_CAN_NODE_NominalBitTimeConfigureEx()
136 uint32_t tseg2 = 0; in XMC_CAN_NODE_NominalBitTimeConfigureEx()
182 … can_node->NBTR = (((tseg2 - 1u) << CAN_NODE_NBTR_TSEG2_Pos) & (uint32_t)CAN_NODE_NBTR_TSEG2_Msk) | in XMC_CAN_NODE_NominalBitTimeConfigureEx()
183 … (((bit_time_config->sjw - 1U) << CAN_NODE_NBTR_SJW_Pos) & (uint32_t)CAN_NODE_NBTR_SJW_Msk) | in XMC_CAN_NODE_NominalBitTimeConfigureEx()
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/hal_infineon-latest/XMCLib/drivers/inc/
Dxmc_vadc.h284 #define XMC_VADC_CONV_ENABLE_FOR_XMC11 (*(uint32_t*) 0x40010500UL) /* Defines the additional err…
806 …uint32_t conv_start_mode : 2; /**< One converter is shared between the queue and scan request so…
809 …uint32_t req_src_priority : 2; /**< Request source priority for the arbiter. If the Conversion st…
817 …uint32_t src_specific_result_reg : 4; /**< Use any one Group related result register as the desti…
821 uint32_t : 4;
823 uint32_t : 4;
824 …uint32_t trigger_signal : 4; /**< Select one of the 16 possibilities for trigger. Uses @…
826 uint32_t : 1;
827 uint32_t trigger_edge : 2; /**< Edge selection for trigger signal. Uses @ref
829 uint32_t : 1;
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Dxmc_bccu.h373 uint32_t trig_mode:1; /**< Selects trigger Mode. Use type @ref XMC_BCCU_TRIGMODE_t */
374 uint32_t : 1;
375 …uint32_t trig_delay:2; /**< Selects trigger delay between channel & module trigger. \n Use type @r…
377 uint32_t : 12;
378 uint32_t maxzero_at_output:12; /**< Configures maximum 0's allowed at modulator output */
380 uint32_t globcon; /* Not to use */
384 uint32_t fclk_ps:12; /**< Configures the ratio between fast clock and module clock */
385 uint32_t : 3;
386 uint32_t bclk_sel:1; /**< Selects the bit clock. Use type @ref XMC_BCCU_BCLK_MODE_t */
387 uint32_t dclk_ps:12; /**< Configures the ratio between dimmer clock and module clock */
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Dxmc_ebu.h506 uint32_t raw0;
509 uint32_t : 16;
510 uint32_t ebu_clk_mode : 1; /**< Clocking mode (::XMC_EBU_CLK_MODE_t) */
511 uint32_t ebu_div2_clk_mode : 1; /**< DIV2 clocking mode (::XMC_EBU_DIV2_CLK_MODE_t) */
512 … uint32_t ebu_clock_divide_ratio : 2; /**< Clock divide ratio (::XMC_EBU_CLOCK_DIVIDE_RATIO_t) */
513 uint32_t : 12;
530 uint32_t raw0;
533 uint32_t : 2;
534 uint32_t ebu_sdram_tristate : 1; /**< 0 - SDRAM cannot be shared; 1 - SDRAM can be shared */
535 uint32_t : 1;
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Dxmc_dma.h271 __IO uint32_t SAR;
272 __I uint32_t RESERVED0;
273 __IO uint32_t DAR;
274 __I uint32_t RESERVED1;
275 __IO uint32_t LLP;
276 __I uint32_t RESERVED2;
277 __IO uint32_t CTLL;
278 __IO uint32_t CTLH;
279 __IO uint32_t SSTAT;
280 __I uint32_t RESERVED3;
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/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/ip/
Dcyip_usbfs.h45 …__IOM uint32_t EP0_DR[8]; /*!< 0x00000000 Control End point EP0 Data Register …
46 __IOM uint32_t CR0; /*!< 0x00000020 USB control 0 Register */
47 __IOM uint32_t CR1; /*!< 0x00000024 USB control 1 Register */
48 …__IOM uint32_t SIE_EP_INT_EN; /*!< 0x00000028 USB SIE Data Endpoints Interrupt Ena…
49 …__IOM uint32_t SIE_EP_INT_SR; /*!< 0x0000002C USB SIE Data Endpoint Interrupt Stat…
50 …__IOM uint32_t SIE_EP1_CNT0; /*!< 0x00000030 Non-control endpoint count register …
51 …__IOM uint32_t SIE_EP1_CNT1; /*!< 0x00000034 Non-control endpoint count register …
52 …__IOM uint32_t SIE_EP1_CR0; /*!< 0x00000038 Non-control endpoint's control Regis…
53 __IM uint32_t RESERVED;
54 __IOM uint32_t USBIO_CR0; /*!< 0x00000040 USBIO Control 0 Register */
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Dcyip_ble.h46 __IOM uint32_t CTRL; /*!< 0x00000000 RCB LL control register. */
47 __IM uint32_t RESERVED[3];
48 …__IOM uint32_t INTR; /*!< 0x00000010 Master interrupt request register. */
49 …__IOM uint32_t INTR_SET; /*!< 0x00000014 Master interrupt set request registe…
50 __IOM uint32_t INTR_MASK; /*!< 0x00000018 Master interrupt mask register. */
51 …__IM uint32_t INTR_MASKED; /*!< 0x0000001C Master interrupt masked request regis…
52 …__IOM uint32_t RADIO_REG1_ADDR; /*!< 0x00000020 Address of Register#1 in Radio (MDO…
53 …__IOM uint32_t RADIO_REG2_ADDR; /*!< 0x00000024 Address of Register#2 in Radio (RSS…
54 …__IOM uint32_t RADIO_REG3_ADDR; /*!< 0x00000028 Address of Register#3 in Radio (ACC…
55 …__IOM uint32_t RADIO_REG4_ADDR; /*!< 0x0000002C Address of Register#4 in Radio (ACC…
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