Lines Matching refs:uint32_t
202 uint32_t : 8;
203 uint32_t IdType : 8;
204 uint32_t : 8;
205 uint32_t Opcode : 8;
211 uint32_t resv[3];
217 uint32_t FamilyIdLow : 8;
218 uint32_t FamilyIdHigh : 8;
219 uint32_t MinorRevisionID : 4;
220 uint32_t MajorRevisionId : 4;
221 uint32_t : 4;
222 uint32_t StatusCode : 4;
227 uint32_t SiliconIdLow : 8;
228 uint32_t SiliconIdHigh : 8;
229 uint32_t ProtectionState : 4;
230 uint32_t LifeCycleState : 4;
231 uint32_t : 4;
232 uint32_t StatusCode : 4;
260 uint32_t SROM_FW_MinorVersion : 8;
261 uint32_t SROM_FW_MajorVersion : 8;
262 uint32_t FlashBootMinorVersion : 8;
263 uint32_t FlashBootMajorVersion : 4;
264 uint32_t StatusCode : 4;
269 uint32_t u32;
278 uint32_t resv[3];
287 uint32_t : 24;
288 uint32_t Opcode : 8;
294 uint32_t resv[3];
300 uint32_t ErrorCode : 24;
301 uint32_t : 4;
302 uint32_t StatusCode : 4;
307 uint32_t DIE_ID0 : 32;
312 uint32_t DIE_ID1 : 32;
320 uint32_t resp3;
337 uint32_t : 8;
338 uint32_t eFuseAddr : 16;
339 uint32_t Opcode : 8;
345 uint32_t resv[3];
351 uint32_t ReadByte : 8;
352 uint32_t : 20;
353 uint32_t StatusCode : 4;
359 uint32_t resv[3];
400 uint32_t : 1;
401 uint32_t Mode : 1;
402 uint32_t : 6;
403 uint32_t SwitchTarget : 8;
404 uint32_t Blocking : 8;
405 uint32_t Opcode : 8;
412 uint32_t : 1;
413 uint32_t Mode : 1;
414 uint32_t EnablePolarity : 1;
415 uint32_t StatusAbnormalPolarity : 1;
416 uint32_t DeepSleep : 1;
417 uint32_t KeepIntRegEnabled : 1;
418 uint32_t : 2;
419 uint32_t VoltageAdjust : 4;
420 uint32_t : 12;
421 uint32_t Opcode : 8;
426 uint32_t : 1;
427 uint32_t Mode : 1;
428 uint32_t EnablePolarity : 1;
429 uint32_t StatusAbnormalPolarity : 1;
430 uint32_t DeepSleep : 1;
431 uint32_t UseLinReg : 1;
432 uint32_t UseRadj : 1;
433 uint32_t VadjOption : 1;
434 uint32_t VoltageAdjust : 5;
435 uint32_t RAdjust : 3;
436 uint32_t : 8;
437 uint32_t Opcode : 8;
443 uint32_t WaitCountIn1us : 10; // Wait count in 1us steps after PMIC status ok.
444 uint32_t : 22;
492 uint32_t rev0 : 8; // reserved
493 uint32_t blocking : 8; // Blocking. see \ref cy_en_programrow_blocking_t
494 uint32_t skipBlankCheck : 8; // Skip blank check. see \ref cy_en_programrow_skipblankcheck_t
495 uint32_t opcode : 8; // Opcode = 0x06
500 uint32_t dataSize : 8; // Data size. see \ref cy_en_programrow_datasize_t
501 uint32_t dataLoc : 8; // Data location. see \ref cy_en_programrow_location_t
502 uint32_t rev0 : 8; // reserved
503 …uint32_t interruptMask : 8; // Interrupt mask (Applicable only for eCT non-blocking). see \ref cy_…
508 uint32_t dstAddr : 32; // Flash address to be programmed
513 …uint32_t srcAddr : 32; // 32-bit aligned address of SRAM where data to be programmed will be stored
527 uint32_t Indication : 28; // indication
528 uint32_t statusCode : 4; // status code
534 uint32_t resv[3];
555 uint32_t rev0 : 8;
556 uint32_t blocking : 8; // see \ref cy_en_erase_blocking_t
557 uint32_t interruptMask : 8; // see \ref cy_en_erase_intrmask_t
558 uint32_t opcode : 8; // Opcode = 0x14
563 uint32_t address : 32;
570 uint32_t resv[2];
576 uint32_t indication : 28; // indication
577 uint32_t statusCode : 4; // status code
583 uint32_t resv[3];
592 uint32_t rev0 : 24;
593 uint32_t opcode : 8;
599 uint32_t resv[3];
605 uint32_t indication : 28; // indication
606 uint32_t statusCode : 4; // status code
612 uint32_t resv[3];
621 uint32_t rev0 : 24;
622 uint32_t opcode : 8; // Opcode = 0x07
628 uint32_t resv[3];
654 uint32_t status : 9; // FM status
655 uint32_t :19; // reserved
656 uint32_t statusCode : 4; // status code
662 uint32_t resv[3];
679 uint32_t : 8;
680 uint32_t option : 8; // options, see \ref cy_en_conf_fm_intr_option_t
681 uint32_t : 8;
682 uint32_t opcode : 8; // Opcode = 0x08
688 uint32_t resv[3];
694 uint32_t status : 28; // status
695 uint32_t statusCode : 4; // status code
701 uint32_t resv[3];
729 uint32_t : 7;
730 uint32_t bank : 1; // see \ref cy_en_checksum_bank_t
731 uint32_t row_id : 13; // Row id
732 uint32_t whole : 1; // see \ref cy_en_checksum_scope_t
733 uint32_t region : 2; // see \ref cy_en_checksum_region_t
734 uint32_t opcode : 8; // Opcode = 0x0B
739 uint32_t : 1;
740 uint32_t bank : 1; // see \ref cy_en_checksum_bank_t
741 uint32_t : 2;
742 uint32_t row_id : 17; // Row id
743 uint32_t whole : 1; // see \ref cy_en_checksum_scope_t
744 uint32_t region : 2; // see \ref cy_en_checksum_region_t
745 uint32_t opcode : 8; // Opcode = 0x0B
751 uint32_t resv[3];
757 uint32_t resv[3];
763 uint32_t : 28; // Nothing
764 uint32_t statusCode : 4; // status code
770 uint32_t resv[3];
785 uint32_t : 8;
786 uint32_t type : 8; // see \ref cy_en_computehash_type_t
787 uint32_t : 8;
788 uint32_t opcode : 8; // Opecde = 0x0D
793 uint32_t start_addr : 32;
798 uint32_t number_byte : 24; // Number of bytes (0: 1 byte,1: 2 bytes etc.)
799 uint32_t : 8;
807 uint32_t resv;
813 uint32_t hash_crc : 28; // Hash/CRC of the data
814 uint32_t statusCode : 4; // status code
820 uint32_t resv[3];
829 uint32_t rev0 : 24;
830 uint32_t opcode : 8; // Opcode = 0x22
836 uint32_t resv[3];
842 uint32_t errorCode : 28; // error code
843 uint32_t statusCode : 4; // status code
849 uint32_t resv[3];
858 uint32_t rev0 : 8;
859 uint32_t blocking : 8; // see \ref cy_en_erase_blocking_t
860 uint32_t intrmask : 1; // see \ref cy_en_erase_intrmask_t
861 uint32_t : 7;
862 uint32_t opcode : 8; // Opcode = 0x23
868 uint32_t resv[3];
874 uint32_t errorCode : 28; // error code
875 uint32_t statusCode : 4; // status code
881 uint32_t resv[3];
890 uint32_t : 24;
891 uint32_t opcode : 8; // Opcode = 0x2A
896 uint32_t addrToBeChecked : 32;
901 uint32_t numOfWordsToBeChecked : 16; // 0: 1 word, 1: 2 words etc.
902 uint32_t : 16;
910 uint32_t resv;
916 uint32_t errorCode : 8; // error code
917 uint32_t failedWordId : 16; // first failed word number
918 uint32_t : 4;
919 uint32_t statusCode : 4; // status code
925 uint32_t resv[3];
934 uint32_t arg[4];
957 uint32_t arg[4];
964 uint32_t resp[4];
982 uint32_t u32[4];
997 extern cy_en_srom_api_status_t Cy_Srom_ConvertRespToStatus(uint32_t resp0);