Lines Matching refs:uint32_t
506 uint32_t raw0;
509 uint32_t : 16;
510 uint32_t ebu_clk_mode : 1; /**< Clocking mode (::XMC_EBU_CLK_MODE_t) */
511 uint32_t ebu_div2_clk_mode : 1; /**< DIV2 clocking mode (::XMC_EBU_DIV2_CLK_MODE_t) */
512 … uint32_t ebu_clock_divide_ratio : 2; /**< Clock divide ratio (::XMC_EBU_CLOCK_DIVIDE_RATIO_t) */
513 uint32_t : 12;
530 uint32_t raw0;
533 uint32_t : 2;
534 uint32_t ebu_sdram_tristate : 1; /**< 0 - SDRAM cannot be shared; 1 - SDRAM can be shared */
535 uint32_t : 1;
536 …uint32_t ebu_extlock : 1; /**< 0 - ext bus is not locked after the EBU gains ownership; 1…
537 …uint32_t ebu_arbsync : 1; /**< 0 - arbitration inputs are sync; 1 - arbitration inputs ar…
538 uint32_t ebu_arbitration_mode : 2; /**< Arbitration mode selection (::XMC_EBU_ARB_MODE_t) */
539 …uint32_t bus_timeout_control : 8; /**< Determines num of inactive cycles leading to a bus timeout…
543 uint32_t : 15;
544 …uint32_t ebu_ale_mode : 1; /**< ALE mode. Switch the ADV output to be an active high ALE s…
559 uint32_t raw0;
562 uint32_t : 16;
563 …uint32_t address_pins_gpio : 9; /**< 0 - Address bit required for addressing memory; 1 - Address b…
564 uint32_t adv_pin_gpio : 1; /**< Adv pin to GPIO mode */
565 uint32_t : 6;
582 uint32_t raw0;
585 …uint32_t ebu_burst_length_sync : 3; /**< Burst length for synchronous burs…
586 …uint32_t ebu_burst_buffer_sync_mode : 1; /**< Burst buffer mode (::XMC_EBU_BURS…
587 …uint32_t ebu_read_stages_synch : 1; /**< Read single stage synchronization…
588 …uint32_t ebu_burst_flash_clock_feedback : 1; /**< Burst flash clock feedback enable…
589 …uint32_t ebu_burst_flash_clock_mode : 1; /**< Burst flash clock mode select (::…
590 …uint32_t ebu_flash_non_array_access : 1; /**< flash non-array access (::XMC_EBU…
591 uint32_t : 8;
592 …uint32_t ebu_early_chip_select_sync_burst : 1; /**< Early chip select for sync burst …
593 …uint32_t ebu_burst_signal_sync : 1; /**< Early burst signal enable for syn…
594 …uint32_t ebu_burst_address_wrapping : 1; /**< Burst address wrapping (::XMC_EBU…
595 …uint32_t ebu_wait_signal_polarity : 1; /**< Reversed polarity at WAIT (::XMC_…
596 …uint32_t ebu_byte_control : 2; /**< Byte control signal control (::XM…
597 …uint32_t ebu_device_addressing_mode : 2; /**< Device addressing mode (::XMC_EBU…
598 …uint32_t ebu_wait_control : 2; /**< External wait control (::XMC_EBU_…
599 …uint32_t ebu_asynchronous_address_phase : 1; /**< Asynchronous address phase (::XMC…
600 uint32_t : 1;
601 …uint32_t ebu_device_type : 4; /**< Device type for region (::XMC_EBU…
607 uint32_t raw1;
619 uint32_t ebu_recovery_cycles_between_different_regions : 4;
629 uint32_t ebu_recovery_cycles_after_read_accesses : 3;
640 uint32_t ebu_programmed_wait_states_for_read_accesses : 5;
645 uint32_t ebu_data_hold_cycles_for_read_accesses: 4;
649 uint32_t ebu_freq_ext_clk_pin : 2;
653 uint32_t ebu_ext_data : 2;
663 uint32_t command_delay_lines : 4;
673 uint32_t address_hold_cycles : 4;
683 uint32_t address_cycles : 4;
700 uint32_t raw0;
703 …uint32_t ebu_burst_length_sync : 3; /**< Burst length for synchronous bur…
704 …uint32_t ebu_burst_buffer_sync_mode : 1; /**< Burst buffer mode (::XMC_EBU_BUR…
705 uint32_t : 12;
706 …uint32_t ebu_early_chip_select_sync_burst : 1; /**< Early chip select for sync burst…
707 …uint32_t ebu_burst_signal_sync : 1; /**< Early burst signal enable for sy…
708 uint32_t : 1;
709 …uint32_t ebu_wait_signal_polarity : 1; /**< Reversed polarity at WAIT (::XMC…
710 …uint32_t ebu_byte_control : 2; /**< Byte control signal control (::X…
711 …uint32_t ebu_device_addressing_mode : 2; /**< Device addressing mode (::XMC_EB…
712 …uint32_t ebu_wait_control : 2; /**< External wait control (::XMC_EBU…
713 …uint32_t ebu_asynchronous_address_phase : 1; /**< Asynchronous address phase (::XM…
714 …uint32_t ebu_lock_chip_select : 1; /**< Lock chip select (::XMC_EBU_LOCK…
715 …uint32_t ebu_device_type : 4; /**< Device type for region (::XMC_EB…
721 uint32_t raw1;
733 uint32_t ebu_recovery_cycles_between_different_regions : 4;
744 uint32_t ebu_recovery_cycles_after_write_accesses : 3;
756 uint32_t ebu_programmed_wait_states_for_write_accesses : 5;
767 uint32_t ebu_data_hold_cycles_for_write_accesses : 4;
771 uint32_t ebu_freq_ext_clk_pin : 2;
775 uint32_t ebu_ext_data : 2;
785 uint32_t command_delay_lines : 4;
794 uint32_t address_hold_cycles : 4;
804 uint32_t address_cycles : 4;
822 uint32_t raw0;
829 uint32_t ebu_row_precharge_delay_counter : 4;
834 uint32_t ebu_init_refresh_commands_counter : 4;
839 uint32_t ebu_mode_register_set_up_time : 2;
844 uint32_t ebu_row_precharge_time_counter : 2;
848 uint32_t ebu_sdram_width_of_column_address : 2;
853 uint32_t ebu_sdram_row_to_column_delay_counter : 2;
857 uint32_t ebu_sdram_row_cycle_time_counter : 3;
861 uint32_t ebu_sdram_mask_for_row_tag : 3;
865 uint32_t ebu_sdram_mask_for_bank_tag : 3;
869 uint32_t ebu_sdram_row_cycle_time_counter_extension : 3;
873 uint32_t ebu_sdram_clk_output : 1;
877 uint32_t ebu_sdram_pwr_mode : 2;
881 uint32_t ebu_sdram_clk_mode : 1;
887 uint32_t raw1;
893 uint32_t ebu_sdram_burst_length : 3;
894 uint32_t : 1;
899 uint32_t ebu_sdram_casclk_mode : 3;
900 uint32_t : 8;
904 uint32_t ebu_sdram_cold_start: 1;
909 uint32_t ebu_sdram_extended_operation_mode : 12;
914 uint32_t ebu_sdram_extended_operation_bank_select : 4;
920 uint32_t raw2;
927 uint32_t ebu_sdram_num_refresh_counter_period : 6;
931 uint32_t ebu_sdram_num_refresh_cmnds : 3;
932 uint32_t : 1;
937 uint32_t ebu_sdram_self_refresh_exit : 1;
938 uint32_t : 1;
943 uint32_t ebu_sdram_self_refresh_entry : 1;
950 uint32_t ebu_sdram_auto_self_refresh : 1;
954 uint32_t ebu_sdram_extended_refresh_counter_period : 2;
959 uint32_t ebu_sdram_self_refresh_exit_delay : 8;
964 uint32_t ebu_sdram_auto_refresh : 1;
969 uint32_t ebu_sdram_delay_on_power_down_exit : 3;
970 uint32_t : 4;
991 const uint32_t ebu_region_no; /**< Number of region*/
1005 const uint32_t ebu_region_no; /**< Number of refresh counter period */
1047 __IO uint32_t CLC;
1048 __IO uint32_t MODCON;
1049 __I uint32_t ID;
1050 __IO uint32_t USERCON;
1051 __I uint32_t RESERVED0[2];
1052 __IO uint32_t ADDRSEL[4];
1055 __IO uint32_t RDCON;
1056 __IO uint32_t RDAPR;
1057 __IO uint32_t WRCON;
1058 __IO uint32_t WRAPR;
1060 __IO uint32_t SDRMCON;
1061 __IO uint32_t SDRMOD;
1062 __IO uint32_t SDRMREF;
1063 __I uint32_t SDRSTAT;
1188 __STATIC_INLINE uint32_t XMC_EBU_GetCLKStatus(XMC_EBU_t *const ebu, const XMC_EBU_CLK_STATUS_t clk_… in XMC_EBU_GetCLKStatus()
1191 return (uint32_t)(ebu->CLC & clk_status); in XMC_EBU_GetCLKStatus()
1422 uint32_t ebu_addr_select_en, in XMC_EBU_AddressSelectEnable()
1423 const uint32_t ebu_region_n) in XMC_EBU_AddressSelectEnable()
1451 uint32_t ebu_addr_select_dis, in XMC_EBU_AddressSelectDisable()
1452 const uint32_t ebu_region_n) in XMC_EBU_AddressSelectDisable()
1476 __STATIC_INLINE uint32_t XMC_EBU_GetBusWriteConfStatus(XMC_EBU_t *const ebu, in XMC_EBU_GetBusWriteConfStatus()
1478 const uint32_t ebu_region_n) in XMC_EBU_GetBusWriteConfStatus()
1501 __STATIC_INLINE uint32_t XMC_EBU_SdramGetStatus(XMC_EBU_t *const ebu) in XMC_EBU_SdramGetStatus()
1504 return (uint32_t)(ebu->SDRSTAT); in XMC_EBU_SdramGetStatus()
1524 __STATIC_INLINE uint32_t XMC_EBU_SdramGetRefreshStatus(XMC_EBU_t *const ebu, in XMC_EBU_SdramGetRefreshStatus()
1528 return (uint32_t)(ebu->SDRMREF & sdram_rfrsh_status); in XMC_EBU_SdramGetRefreshStatus()