Lines Matching refs:uint32_t
284 #define XMC_VADC_CONV_ENABLE_FOR_XMC11 (*(uint32_t*) 0x40010500UL) /* Defines the additional err…
806 …uint32_t conv_start_mode : 2; /**< One converter is shared between the queue and scan request so…
809 …uint32_t req_src_priority : 2; /**< Request source priority for the arbiter. If the Conversion st…
817 …uint32_t src_specific_result_reg : 4; /**< Use any one Group related result register as the desti…
821 uint32_t : 4;
823 uint32_t : 4;
824 …uint32_t trigger_signal : 4; /**< Select one of the 16 possibilities for trigger. Uses @…
826 uint32_t : 1;
827 uint32_t trigger_edge : 2; /**< Edge selection for trigger signal. Uses @ref
829 uint32_t : 1;
830 …uint32_t gate_signal : 4; /**< Select one of the 16 possibilities for gating. Uses @r…
832 uint32_t : 8;
833 …uint32_t timer_mode : 1; /**< Decides whether timer mode for equi-distant sampling s…
835 uint32_t : 3;
837 uint32_t asctrl;
843 uint32_t : 2;
844 … uint32_t external_trigger : 1; /**< Conversions be initiated by external hardware trigger */
845 …uint32_t req_src_interrupt : 1; /**< Request source event can be generated after a conversion se…
846 …uint32_t enable_auto_scan : 1; /**< Enables the continuous conversion mode. Conversion completi…
848 … uint32_t load_mode : 1; /**< Selects load event mode. Uses @ref XMC_VADC_SCAN_LOAD_t */
849 uint32_t : 26;
851 uint32_t asmr;
868 uint32_t input_class : 2; /**< Input conversion class selection.
870 uint32_t : 2;
871 … uint32_t lower_boundary_select : 2; /**< Which boundary register serves as lower bound?
873 … uint32_t upper_boundary_select : 2; /**< Which boundary register serves as upper bound?
875 uint32_t event_gen_criteria : 2; /**< When should an event be generated?
877 …uint32_t sync_conversion : 1; /**< Enables synchronous conversion for the configured c…
878 …uint32_t alternate_reference : 1; /**< Input reference voltage selection either VARef or C…
880 uint32_t : 4;
881 uint32_t result_reg_number : 4; /**< Group result register number */
882 …uint32_t use_global_result : 1; /**< Use global result register for background request s…
883 …uint32_t result_alignment : 1; /**< Alignment of the results read in the result registe…
885 uint32_t : 6;
886 …uint32_t broken_wire_detect_channel : 2; /**< Source to be used to charge the capacitor for BWD f…
888 …uint32_t broken_wire_detect : 1; /**< Configures extra phase before the capacitor is samp…
890 uint32_t chctr;
896 uint32_t : 8;
898 … uint32_t flag_output_condition_ch0 : 1; /**< Condition for which the boundary flag should change.
900 … uint32_t flag_output_condition_ch1 : 1; /**< Condition for which the boundary flag should change.
902 … uint32_t flag_output_condition_ch2 : 1; /**< Condition for which the boundary flag should change.
904 … uint32_t flag_output_condition_ch3 : 1; /**< Condition for which the boundary flag should change.
907 uint32_t : 4;
909 uint32_t : 4;
911 uint32_t invert_boundary_flag_ch0 : 1; /**< Inverts boundary flag output.*/
912 uint32_t invert_boundary_flag_ch1 : 1; /**< Inverts boundary flag output.*/
913 uint32_t invert_boundary_flag_ch2 : 1; /**< Inverts boundary flag output.*/
914 uint32_t invert_boundary_flag_ch3 : 1; /**< Inverts boundary flag output.*/
917 …uint32_t boundary_flag_output_ch0 : 1; /**< Enable the boundary flag output on the specific chann…
918 …uint32_t boundary_flag_output_ch1 : 1; /**< Enable the boundary flag output on the specific chann…
919 …uint32_t boundary_flag_output_ch2 : 1; /**< Enable the boundary flag output on the specific chann…
920 …uint32_t boundary_flag_output_ch3 : 1; /**< Enable the boundary flag output on the specific chann…
922 uint32_t : 12;
924 uint32_t bfl;
931 uint32_t boundary_flag_mode_ch0 : 4; /**< Specify the basic operation of boundary flag 0
933 uint32_t boundary_flag_mode_ch1 : 4; /**< Specify the basic operation of boundary flag 1
935 uint32_t boundary_flag_mode_ch2 : 4; /**< Specify the basic operation of boundary flag 2
937 uint32_t boundary_flag_mode_ch3 : 4; /**< Specify the basic operation of boundary flag 3
939 uint32_t : 16;
941 uint32_t bflc;
959 …uint32_t channel_num : 5; /**< Channel number associated with this queue entry.<BR>Range:[…
960 …uint32_t refill_needed : 1; /**< Conversion completed channel gets inserted back into the qu…
961 uint32_t generate_interrupt : 1; /**< Generates a queue request source event */
962 … uint32_t external_trigger : 1; /**< Conversion requests are raised on an external trigger. */
963 uint32_t : 24;
966 uint32_t qinr0;
975 …uint32_t conv_start_mode : 2; /**< One converter is shared between the queue and scan request so…
978 …uint32_t req_src_priority : 2; /**< Request source priority for the arbiter.Uses @ref XMC_VADC_GR…
984 …uint32_t src_specific_result_reg : 4; /**< Uses any one Group related result register as the dest…
988 uint32_t : 4;
990 uint32_t : 4;
991 … uint32_t trigger_signal : 4; /**< Select one of the 16 possibilities for trigger.
993 uint32_t : 1;
994 uint32_t trigger_edge : 2; /**< Edge selection for trigger signal.
996 uint32_t : 1;
997 uint32_t gate_signal : 4; /**< Select one of the 16 possibilities for gating.
999 uint32_t : 8;
1000 …uint32_t timer_mode : 1; /**< Timer mode for equi-distant sampling shall be activate…
1001 uint32_t : 3;
1003 uint32_t qctrl0;
1009 uint32_t : 2;
1010 uint32_t external_trigger : 1; /**< Are external triggers supported? */
1011 uint32_t : 29;
1013 uint32_t qmr0;
1028 …uint32_t sample_time_std_conv : 5; /**< Sample time for channels directly connected to…
1030 uint32_t : 3;
1031 …uint32_t conversion_mode_standard : 3; /**< Conversion mode for channels directly connecte…
1033 uint32_t : 5;
1035 … uint32_t sampling_phase_emux_channel : 5; /**< Sample time for channels connected via EMUX
1037 uint32_t : 3;
1038 …uint32_t conversion_mode_emux : 3; /**< Conversion mode for channels connected via EMU…
1040 uint32_t : 5;
1042 uint32_t : 16;
1045 uint32_t globiclass;
1060 … uint32_t analog_clock_divider : 5; /**< Clock for the converter. <BR>Range: [0x0 to 0x1F] */
1061 uint32_t : 2;
1062 … uint32_t msb_conversion_clock : 1; /**< Additional clock cycle for analog converter */
1063 …uint32_t arbiter_clock_divider : 2; /**< Request source arbiter clock divider. <BR>Range: [0x0…
1064 uint32_t : 5;
1065 uint32_t : 17;
1067 uint32_t globcfg;
1082 uint32_t boundary0 : 12; /**< Boundary value for results comparison*/
1083 uint32_t : 4;
1084 uint32_t boundary1 : 12; /**< Boundary value for results comparison*/
1085 uint32_t : 4;
1087 uint32_t globbound;
1098 uint32_t : 16;
1099 uint32_t data_reduction_control : 4; /**< Data reduction stages */
1100 uint32_t : 4;
1101 …uint32_t wait_for_read_mode : 1; /**< Results of the next conversion will not be overwritten…
1103 uint32_t : 6;
1104 … uint32_t event_gen_enable : 1; /**< Generates an event on availability of new result. */
1106 uint32_t globrcr;
1112 uint32_t module_disable : 1; /**< Disables the module clock.*/
1113 uint32_t : 2;
1114 …uint32_t disable_sleep_mode_control : 1; /**< Set it to true in order to disable the Sleep mode …
1115 uint32_t : 28;
1117 uint32_t clc;
1132 …uint32_t sample_time_std_conv : 5; /**< Sample time for channels directly connected to…
1134 uint32_t : 3;
1135 …uint32_t conversion_mode_standard : 3; /**< Conversion mode for channels directly connecte…
1137 uint32_t : 5;
1138 … uint32_t sampling_phase_emux_channel : 5; /**< Sample time for channels connected via EMUX
1140 uint32_t : 3;
1141 …uint32_t conversion_mode_emux : 3; /**< Conversion mode for channels connected via EMU…
1143 uint32_t : 5;
1145 uint32_t g_iclass0;
1159 … uint32_t starting_external_channel : 3; /**< External channel number to which the VADC will
1162 uint32_t : 13;
1164 … uint32_t connected_channel : 10; /**< The Channel to which the EMUX is connected. */
1166 … uint32_t connected_channel : 5; /**< The Channel to which the EMUX is connected. */
1167 uint32_t : 5;
1169 …uint32_t emux_mode : 2; /**< Selects the external multiplexer modes: Steady, Sing…
1171 …uint32_t emux_coding : 1; /**< Select Binary or Gray coding. Uses @ref XMC_VADC_GRO…
1172 …uint32_t stce_usage : 1; /**< Use STCE for each conversion of an external channel …
1174 …uint32_t emux_channel_select_style : 1; /**< Selects the style of configuring the \b connected_ch…
1176 uint32_t : 1;
1178 uint32_t : 2;
1181 uint32_t g_emuxctr;
1199 uint32_t boundary0 : 12; /**< Boundary value for results comparison*/
1200 uint32_t : 4;
1201 uint32_t boundary1 : 12; /**< Boundary value for results comparison*/
1202 uint32_t : 4;
1204 uint32_t g_bound;
1210 uint32_t : 4;
1211 uint32_t arbitration_round_length : 2; /**< Number of arbiter slots to be considered */
1212 uint32_t : 1;
1213 …uint32_t arbiter_mode : 1; /**< Arbiter mode - Select either Continuous mode or Deman…
1215 uint32_t : 24;
1217 uint32_t g_arbcfg;
1231 uint32_t : 16;
1232 uint32_t data_reduction_control : 4; /**< Configures the data reduction stages */
1233 … uint32_t post_processing_mode : 2; /**< Result data processing mode. Uses @ref XMC_VADC_DMM_t
1237 uint32_t : 2;
1238 …uint32_t wait_for_read_mode : 1; /**< Allow the conversion only after previous results are r…
1239 … uint32_t part_of_fifo : 2; /**< Make the result register a part of Result FIFO? */
1240 uint32_t : 4;
1241 … uint32_t event_gen_enable : 1; /**< Generates an event on availability of new result. */
1243 uint32_t g_rcr;
1258 …uint32_t sh_unit_step0 :3; /**< Select a Sample and hold unit for the stepper's step n…
1260 uint32_t enable_step0 :1; /**< Should the step be added to the sequence */
1261 …uint32_t sh_unit_step1 :3; /**< Select a Sample and hold unit for the stepper's step n…
1263 uint32_t enable_step1 :1; /**< Should the step be added to the sequence */
1264 …uint32_t sh_unit_step2 :3; /**< Select a Sample and hold unit for the stepper's step n…
1266 uint32_t enable_step2 :1; /**< Should the step be added to the sequence */
1267 …uint32_t sh_unit_step3 :3; /**< Select a Sample and hold unit for the stepper's step n…
1269 uint32_t enable_step3 :1; /**< Should the step be added to the sequence */
1270 …uint32_t sh_unit_step4 :3; /**< Select a Sample and hold unit for the stepper's step n…
1272 uint32_t enable_step4 :1; /**< Should the step be added to the sequence */
1273 …uint32_t sh_unit_step5 :3; /**< Select a Sample and hold unit for the stepper's step n…
1275 uint32_t enable_step5 :1; /**< Should the step be added to the sequence */
1276 …uint32_t sh_unit_step6 :3; /**< Select a Sample and hold unit for the stepper's step n…
1278 uint32_t enable_step6 :1; /**< Should the step be added to the sequence */
1279 …uint32_t sh_unit_step7 :3; /**< Select a Sample and hold unit for the stepper's step n…
1281 uint32_t enable_step7 :1; /**< Should the step be added to the sequence */
1284 uint32_t stepcfg;
1298 …uint32_t shs_clock_divider :4; /**< The divider value for the SHS clock. Range: [0x0 to 0xF…
1299 uint32_t :6;
1301 uint32_t :10;
1303 …uint32_t analog_reference_select :2; /**< It is possible to different reference voltage for the S…
1304 uint32_t :20;
1306 uint32_t shscfg;
1324 uint32_t result :16; /**< Result of the Analog to digital conversion*/
1325 …uint32_t group_number :4; /**< Indicates the group to which the channel_number refer…
1326 uint32_t channel_number :5; /**< Converted channel number*/
1327 uint32_t emux_channel_number :3; /**< Converted external multiplexer channel number.
1329 uint32_t converted_request_source :2; /**< Converted request source*/
1330 …uint32_t fast_compare_result :1; /**< Fast compare result if conversion mode is fast compar…
1331 … uint32_t vaild_result :1; /**< Valid flag is set when a new result is available*/
1333 uint32_t res;
1346 uint32_t result :16; /**< Result of the Analog to digital conversion*/
1347 uint32_t data_reduction_counter :4; /**< Results reduction counter value*/
1348 uint32_t channel_number :5; /**< Converted channel number*/
1349 uint32_t emux_channel_number :3; /**< Converted external multiplexer channel number.
1351 uint32_t converted_request_source :2; /**< Converted request source*/
1352 …uint32_t fast_compare_result :1; /**< Fast compare result if conversion mode is fast compar…
1353 … uint32_t vaild_result :1; /**< Valid flag is set when a new result is available*/
1355 uint32_t res;
1457 global_ptr->CLC &= ~((uint32_t)VADC_CLC_DISR_Msk); in XMC_VADC_GLOBAL_EnableModuleClock()
1477 global_ptr->CLC |= (uint32_t) ((uint32_t)1 << VADC_CLC_DISR_Pos); in XMC_VADC_GLOBAL_DisableModuleClock()
1496 global_ptr->CLC &= ~((uint32_t)VADC_CLC_EDIS_Msk); in XMC_VADC_GLOBAL_EnableSleepMode()
1516 global_ptr->CLC |= (uint32_t) ((uint32_t)1 << VADC_CLC_EDIS_Pos); in XMC_VADC_GLOBAL_DisableSleepMode()
1541 global_ptr->GLOBCFG = (uint32_t)(config->globcfg | (VADC_GLOBCFG_DIVWC_Msk)); in XMC_VADC_GLOBAL_ClockInit()
1566 … const XMC_VADC_GROUP_CONV_t conv_type, const uint32_t set_num);
1633 global_ptr->GLOBCFG &= ~((uint32_t)VADC_GLOBCFG_SUCAL_Msk); in XMC_VADC_GLOBAL_DisableStartupCalibration()
1658 … XMC_VADC_GLOBAL_DisablePostCalibration(XMC_VADC_GLOBAL_t *const global_ptr, uint32_t group_number) in XMC_VADC_GLOBAL_DisablePostCalibration()
1662 …global_ptr->GLOBCFG |= (uint32_t)((uint32_t)1 << ((uint32_t)VADC_GLOBCFG_DPCAL0_Pos + group_number… in XMC_VADC_GLOBAL_DisablePostCalibration()
1682 …d XMC_VADC_GLOBAL_EnablePostCalibration(XMC_VADC_GLOBAL_t *const global_ptr, uint32_t group_number) in XMC_VADC_GLOBAL_EnablePostCalibration()
1686 …global_ptr->GLOBCFG &= (~ (uint32_t)((uint32_t)1 << ((uint32_t)VADC_GLOBCFG_DPCAL0_Pos + group_num… in XMC_VADC_GLOBAL_EnablePostCalibration()
1710 …L_SetBoundaries(XMC_VADC_GLOBAL_t *const global_ptr, const uint32_t boundary0, const uint32_t boun…
1752 …L_BindGroupToEMux(XMC_VADC_GLOBAL_t *const global_ptr, const uint32_t emuxif, const uint32_t group…
1771 __STATIC_INLINE uint32_t XMC_VADC_GLOBAL_GetDetailedResult(XMC_VADC_GLOBAL_t *const global_ptr) in XMC_VADC_GLOBAL_GetDetailedResult()
1851 …E void XMC_VADC_GLOBAL_TriggerEvent(XMC_VADC_GLOBAL_t *const global_ptr, const uint32_t event_type) in XMC_VADC_GLOBAL_TriggerEvent()
1875 __STATIC_INLINE void XMC_VADC_GLOBAL_ClearEvent(XMC_VADC_GLOBAL_t *const global_ptr, const uint32_t… in XMC_VADC_GLOBAL_ClearEvent()
1881 global_ptr->GLOBEFLAG = ((uint32_t)(event_type << (uint32_t)16)); in XMC_VADC_GLOBAL_ClearEvent()
1952 …shs_ptr->SHSCFG |= (shs_ptr->SHSCFG & (uint32_t)~SHS_SHSCFG_AREF_Msk) | (uint32_t)aref | SHS_SHSC… in XMC_VADC_GLOBAL_SHS_SetAnalogReference()
1978 shs_ptr->STEPCFG = (uint32_t) config->stepcfg; in XMC_VADC_GLOBAL_SHS_SetStepperSequence()
1999 return((bool)((shs_ptr->SHSCFG >> (uint32_t)SHS_SHSCFG_ANRDY_Pos) & (uint32_t)0x1)); in XMC_VADC_GLOBAL_SHS_IsConverterReady()
2077 (divs_value < (uint32_t)0x10)) in XMC_VADC_GLOBAL_SHS_SetClockDivider()
2079 …shs_ptr->SHSCFG = (shs_ptr->SHSCFG & (~(uint32_t)SHS_SHSCFG_DIVS_Msk)) | (uint32_t)SHS_SHSCFG_SCW… in XMC_VADC_GLOBAL_SHS_SetClockDivider()
2080 shs_ptr->SHSCFG |= ((uint32_t)divs_value << SHS_SHSCFG_DIVS_Pos) | (uint32_t)SHS_SHSCFG_SCWC_Msk; in XMC_VADC_GLOBAL_SHS_SetClockDivider()
2120 uint32_t max_calibration_time) in XMC_VADC_GLOBAL_SHS_SetMaxCalTime()
2125 shs_ptr->CALCTR &= ~((uint32_t)SHS_CALCTR_CALMAX_Msk); in XMC_VADC_GLOBAL_SHS_SetMaxCalTime()
2126 shs_ptr->CALCTR |= ((uint32_t)max_calibration_time << SHS_CALCTR_CALMAX_Pos); in XMC_VADC_GLOBAL_SHS_SetMaxCalTime()
2240 shs_ptr->LOOP |= (uint32_t)SHS_LOOP_LPEN0_Msk << (uint32_t)loop_select; in XMC_VADC_GLOBAL_SHS_EnableSigmaDeltaLoop()
2264 shs_ptr->LOOP &= ~((uint32_t)SHS_LOOP_LPEN0_Msk << (uint32_t)loop_select); in XMC_VADC_GLOBAL_SHS_DisableSigmaDeltaLoop()
2313 const XMC_VADC_GROUP_CONV_t conv_type, const uint32_t set_num);
2337 void XMC_VADC_GROUP_SetSyncSlave(XMC_VADC_GROUP_t *const group_ptr, uint32_t master_grp, uint32_t s…
2392 void XMC_VADC_GROUP_CheckSlaveReadiness(XMC_VADC_GROUP_t *const group_ptr, uint32_t slave_group);
2411 void XMC_VADC_GROUP_IgnoreSlaveReadiness(XMC_VADC_GROUP_t *const group_ptr, uint32_t slave_group);
2430 uint32_t eval_waiting_group,
2431 uint32_t eval_origin_group);
2447 __STATIC_INLINE uint32_t XMC_VADC_GROUP_GetSyncReadySignal(XMC_VADC_GROUP_t *const group_ptr) in XMC_VADC_GROUP_GetSyncReadySignal()
2449 uint32_t eval_mask; in XMC_VADC_GROUP_GetSyncReadySignal()
2474 __STATIC_INLINE void XMC_VADC_GROUP_SetSyncReadySignal(XMC_VADC_GROUP_t *const group_ptr, uint32_t … in XMC_VADC_GROUP_SetSyncReadySignal()
2476 uint32_t eval_mask; in XMC_VADC_GROUP_SetSyncReadySignal()
2505 void XMC_VADC_GROUP_EnableChannelSyncRequest(XMC_VADC_GROUP_t *const group_ptr, const uint32_t ch_n…
2520 void XMC_VADC_GROUP_DisableChannelSyncRequest(XMC_VADC_GROUP_t *const group_ptr, const uint32_t ch_…
2559 const uint32_t boundary0,
2560 const uint32_t boundary1);
2597 const uint32_t sr_num,
2618 uint32_t emux_config; in XMC_VADC_GROUP_ExternalMuxControlInit()
2622 …emux_config = ((uint32_t)emux_cfg.starting_external_channel << (uint32_t)VADC_G_EMUXCTR_EMUXSET_Po… in XMC_VADC_GROUP_ExternalMuxControlInit()
2623 ((uint32_t)emux_cfg.connected_channel << (uint32_t)VADC_G_EMUXCTR_EMUXCH_Pos); in XMC_VADC_GROUP_ExternalMuxControlInit()
2626 emux_config = ((uint32_t)emux_cfg.emux_coding << (uint32_t)VADC_G_EMUXCTR_EMXCOD_Pos) | in XMC_VADC_GROUP_ExternalMuxControlInit()
2627 ((uint32_t)emux_cfg.emux_mode << (uint32_t)VADC_G_EMUXCTR_EMUXMODE_Pos)| in XMC_VADC_GROUP_ExternalMuxControlInit()
2628 ((uint32_t)emux_cfg.stce_usage << (uint32_t)VADC_G_EMUXCTR_EMXST_Pos); in XMC_VADC_GROUP_ExternalMuxControlInit()
2631 …emux_config |= ((uint32_t)emux_cfg.emux_channel_select_style << (uint32_t)VADC_G_EMUXCTR_EMXCSS_Po… in XMC_VADC_GROUP_ExternalMuxControlInit()
2633 group_ptr->EMUXCTR |= (emux_config | ((uint32_t)VADC_G_EMUXCTR_EMXWC_Msk)) ; in XMC_VADC_GROUP_ExternalMuxControlInit()
2671 __STATIC_INLINE uint32_t XMC_VADC_GROUP_GetAlias(XMC_VADC_GROUP_t *const group_ptr) in XMC_VADC_GROUP_GetAlias()
2699 input_value.g_iclass0 = (uint32_t) 0xFFFFFFFF; in XMC_VADC_GROUP_GetInputClass()
2702 input_value.g_iclass0 = group_ptr->ICLASS[(uint32_t)conv_class]; in XMC_VADC_GROUP_GetInputClass()
2748 group_ptr->ARBPR |= (uint32_t)VADC_G_ARBPR_ASEN1_Msk; in XMC_VADC_GROUP_ScanEnableArbitrationSlot()
2769 group_ptr->ARBPR &= ~((uint32_t)VADC_G_ARBPR_ASEN1_Msk); in XMC_VADC_GROUP_ScanDisableArbitrationSlot()
2791 return ((group_ptr->ARBPR & (uint32_t)VADC_G_ARBPR_ASEN1_Msk) >> VADC_G_ARBPR_ASEN1_Pos); in XMC_VADC_GROUP_ScanIsArbitrationSlotEnabled()
2871 group_ptr->ASMR &= (uint32_t) (~((uint32_t)VADC_G_ASMR_ENGT_Msk)); in XMC_VADC_GROUP_ScanSetGatingMode()
2873 group_ptr->ASMR |= (uint32_t)((uint32_t)mode_sel << VADC_G_ASMR_ENGT_Pos); in XMC_VADC_GROUP_ScanSetGatingMode()
2896 group_ptr->ASMR |= (uint32_t)VADC_G_ASMR_SCAN_Msk; in XMC_VADC_GROUP_ScanEnableContinuousMode()
2919 group_ptr->ASMR &= ~((uint32_t)VADC_G_ASMR_SCAN_Msk); in XMC_VADC_GROUP_ScanDisableContinuousMode()
2939 group_ptr->ASMR |= (uint32_t)VADC_G_ASMR_LDEV_Msk; in XMC_VADC_GROUP_ScanTriggerConversion()
2975 …d XMC_VADC_GROUP_ScanAddChannelToSequence(XMC_VADC_GROUP_t *const group_ptr, const uint32_t ch_num) in XMC_VADC_GROUP_ScanAddChannelToSequence()
2980 group_ptr->ASSEL |= (uint32_t)((uint32_t)1 << ch_num); in XMC_VADC_GROUP_ScanAddChannelToSequence()
3002 …d XMC_VADC_GROUP_ScanAddMultipleChannels(XMC_VADC_GROUP_t *const group_ptr, const uint32_t ch_mask) in XMC_VADC_GROUP_ScanAddMultipleChannels()
3025 … bool XMC_VADC_GROUP_ScanIsChannelPending(XMC_VADC_GROUP_t *const group_ptr, const uint32_t ch_num) in XMC_VADC_GROUP_ScanIsChannelPending()
3031 return( (bool)((uint32_t)(group_ptr->ASPND >> ch_num) & 1U)); in XMC_VADC_GROUP_ScanIsChannelPending()
3050 uint32_t XMC_VADC_GROUP_ScanGetNumChannelsPending(XMC_VADC_GROUP_t *const group_ptr);
3069 group_ptr->SEFLAG |= (uint32_t)VADC_G_SEFLAG_SEV1_Msk; in XMC_VADC_GROUP_ScanTriggerReqSrcEvent()
3088 group_ptr->SEFCLR |= (uint32_t)VADC_G_SEFCLR_SEV1_Msk; in XMC_VADC_GROUP_ScanClearReqSrcEvent()
3108 return( (bool)(group_ptr->SEFLAG & (uint32_t)VADC_G_SEFLAG_SEV1_Msk)); in XMC_VADC_GROUP_ScanGetReqSrcEventStatus()
3146 group_ptr->ASMR |= (uint32_t)VADC_G_ASMR_ENTR_Msk; in XMC_VADC_GROUP_ScanEnableExternalTrigger()
3168 group_ptr->ASMR &= ~((uint32_t)VADC_G_ASMR_ENTR_Msk); in XMC_VADC_GROUP_ScanDisableExternalTrigger()
3186 void XMC_VADC_GROUP_ScanRemoveChannel(XMC_VADC_GROUP_t *const group_ptr, const uint32_t channel_num…
3206 group_ptr->ASMR |= ((uint32_t)VADC_G_ASMR_ENSI_Msk); in XMC_VADC_GROUP_ScanEnableEvent()
3227 group_ptr->ASMR &= ~((uint32_t)VADC_G_ASMR_ENSI_Msk); in XMC_VADC_GROUP_ScanDisableEvent()
3269 group_ptr->ARBPR |= (uint32_t)VADC_G_ARBPR_ASEN2_Msk; in XMC_VADC_GROUP_BackgroundEnableArbitrationSlot()
3291 group_ptr->ARBPR &= ~((uint32_t)VADC_G_ARBPR_ASEN2_Msk); in XMC_VADC_GROUP_BackgroundDisableArbitrationSlot()
3313 void XMC_VADC_GLOBAL_BackgroundSelectTrigger(XMC_VADC_GLOBAL_t *const global_ptr, const uint32_t in…
3351 void XMC_VADC_GLOBAL_BackgroundSelectGating(XMC_VADC_GLOBAL_t *const global_ptr, const uint32_t inp…
3376 global_ptr->BRSMR &= (uint32_t)(~((uint32_t)VADC_BRSMR_ENGT_Msk)); in XMC_VADC_GLOBAL_BackgroundSetGatingMode()
3378 global_ptr->BRSMR |= (uint32_t)((uint32_t)mode_sel << VADC_BRSMR_ENGT_Pos); in XMC_VADC_GLOBAL_BackgroundSetGatingMode()
3402 global_ptr->BRSMR |= (uint32_t)VADC_BRSMR_SCAN_Msk; in XMC_VADC_GLOBAL_BackgroundEnableContinuousMode()
3425 global_ptr->BRSMR &= ~((uint32_t)VADC_BRSMR_SCAN_Msk); in XMC_VADC_GLOBAL_BackgroundDisableContinuousMode()
3445 global_ptr->BRSMR |= (uint32_t)VADC_BRSMR_LDEV_Msk; in XMC_VADC_GLOBAL_BackgroundTriggerConversion()
3485 const uint32_t grp_num, in XMC_VADC_GLOBAL_BackgroundAddChannelToSequence()
3486 const uint32_t ch_num) in XMC_VADC_GLOBAL_BackgroundAddChannelToSequence()
3493 global_ptr->BRSSEL[grp_num] |= (uint32_t)((uint32_t)1 << ch_num); in XMC_VADC_GLOBAL_BackgroundAddChannelToSequence()
3517 const uint32_t grp_num, in XMC_VADC_GLOBAL_BackgndAddMultipleChannels()
3518 const uint32_t ch_mask) in XMC_VADC_GLOBAL_BackgndAddMultipleChannels()
3544 const uint32_t grp_num, in XMC_VADC_GLOBAL_BackgroundRemoveChannelFromSequence()
3545 const uint32_t ch_num) in XMC_VADC_GLOBAL_BackgroundRemoveChannelFromSequence()
3552 global_ptr->BRSSEL[grp_num] &= (uint32_t)~((uint32_t)1 << ch_num); in XMC_VADC_GLOBAL_BackgroundRemoveChannelFromSequence()
3576 const uint32_t grp_num, in XMC_VADC_GLOBAL_BackgndRemoveMultipleChannels()
3577 const uint32_t ch_mask) in XMC_VADC_GLOBAL_BackgndRemoveMultipleChannels()
3581 global_ptr->BRSSEL[grp_num] &= (uint32_t)~ch_mask; in XMC_VADC_GLOBAL_BackgndRemoveMultipleChannels()
3603 const uint32_t grp_num, in XMC_VADC_GLOBAL_BackgroundIsChannelPending()
3604 const uint32_t ch_num) in XMC_VADC_GLOBAL_BackgroundIsChannelPending()
3611 return( (bool)(global_ptr->BRSPND[grp_num] & (uint32_t)((uint32_t)1 << ch_num))); in XMC_VADC_GLOBAL_BackgroundIsChannelPending()
3630 uint32_t XMC_VADC_GLOBAL_BackgroundGetNumChannelsPending(XMC_VADC_GLOBAL_t *const global_ptr);
3649 global_ptr->GLOBEFLAG |= (uint32_t)VADC_GLOBEFLAG_SEVGLB_Msk; in XMC_VADC_GLOBAL_BackgroundTriggerReqSrcEvent()
3668 global_ptr->GLOBEFLAG |= (uint32_t)VADC_GLOBEFLAG_SEVGLBCLR_Msk; in XMC_VADC_GLOBAL_BackgroundClearReqSrcEvent()
3689 return((bool)(global_ptr->GLOBEFLAG & (uint32_t)VADC_GLOBEFLAG_SEVGLB_Msk)); in XMC_VADC_GLOBAL_BackgroundGetReqSrcEventStatus()
3710 global_ptr->BRSMR |= (uint32_t)VADC_BRSMR_ENTR_Msk; in XMC_VADC_GLOBAL_BackgroundEnableExternalTrigger()
3732 global_ptr->BRSMR &= ~((uint32_t)VADC_BRSMR_ENTR_Msk); in XMC_VADC_GLOBAL_BackgroundDisableExternalTrigger()
3753 global_ptr->BRSMR |= ((uint32_t)VADC_BRSMR_ENSI_Msk); in XMC_VADC_GLOBAL_BackgroundEnableEvent()
3774 global_ptr->BRSMR &= ~((uint32_t)VADC_BRSMR_ENSI_Msk); in XMC_VADC_GLOBAL_BackgroundDisableEvent()
3818 group_ptr->ARBPR |= (uint32_t)((uint32_t)1 << VADC_G_ARBPR_ASEN0_Pos); in XMC_VADC_GROUP_QueueEnableArbitrationSlot()
3839 group_ptr->ARBPR &= ~((uint32_t)VADC_G_ARBPR_ASEN0_Msk); in XMC_VADC_GROUP_QueueDisableArbitrationSlot()
3862 return ((group_ptr->ARBPR & (uint32_t)VADC_G_ARBPR_ASEN0_Msk) >> VADC_G_ARBPR_ASEN0_Pos); in XMC_VADC_GROUP_QueueIsArbitrationSlotEnabled()
3944 group_ptr->QMR0 &= (uint32_t)(~((uint32_t) VADC_G_QMR0_ENGT_Msk)); in XMC_VADC_GROUP_QueueSetGatingMode()
3946 group_ptr->QMR0 |= (uint32_t)((uint32_t)mode_sel << VADC_G_QMR0_ENGT_Pos); in XMC_VADC_GROUP_QueueSetGatingMode()
3976 group_ptr->QMR0 |= (uint32_t)((uint32_t)1 << VADC_G_QMR0_TREV_Pos); in XMC_VADC_GROUP_QueueTriggerConversion()
3996 uint32_t XMC_VADC_GROUP_QueueGetLength(XMC_VADC_GROUP_t *const group_ptr);
4033 group_ptr->QMR0 |= (uint32_t)VADC_G_QMR0_FLUSH_Msk; in XMC_VADC_GROUP_QueueFlushEntries()
4035 while( !((group_ptr->QSR0)& (uint32_t)VADC_G_QSR0_EMPTY_Msk)) in XMC_VADC_GROUP_QueueFlushEntries()
4163 group_ptr->SEFCLR = (uint32_t)VADC_G_SEFCLR_SEV0_Msk; in XMC_VADC_GROUP_QueueClearReqSrcEvent()
4184 return(group_ptr->SEFLAG & (uint32_t)VADC_G_SEFLAG_SEV0_Msk); in XMC_VADC_GROUP_QueueGetReqSrcEventStatus()
4222 group_ptr->QMR0 |= (uint32_t)VADC_G_QMR0_ENTR_Msk; in XMC_VADC_GROUP_QueueEnableExternalTrigger()
4244 group_ptr->QMR0 &= ~((uint32_t)VADC_G_QMR0_ENTR_Msk); in XMC_VADC_GROUP_QueueDisableExternalTrigger()
4268 void XMC_VADC_GROUP_ChannelInit(XMC_VADC_GROUP_t *const group_ptr, const uint32_t ch_num,
4299 const uint32_t src_ch_num, in XMC_VADC_GROUP_SetChannelAlias()
4300 const uint32_t alias_ch_num) in XMC_VADC_GROUP_SetChannelAlias()
4306 …group_ptr->ALIAS |= (group_ptr->ALIAS & (uint32_t)~(VADC_G_ALIAS_ALIAS0_Msk << (VADC_G_ALIAS_ALIAS… in XMC_VADC_GROUP_SetChannelAlias()
4324 const uint32_t alias_ch_num) in XMC_VADC_GROUP_GetChannelAlias()
4351 bool XMC_VADC_GROUP_ChannelIsResultOutOfBounds(XMC_VADC_GROUP_t *const group_ptr, const uint32_t ch…
4369 void XMC_VADC_GROUP_ChannelSetInputReference(XMC_VADC_GROUP_t *const group_ptr, const uint32_t ch_n…
4390 const uint32_t ch_num,
4391 const uint32_t result_reg_num);
4411 const uint32_t ch_num,
4433 const uint32_t ch_num) in XMC_VADC_GROUP_ChannelGetResultAlignment()
4439 …return ((XMC_VADC_RESULT_ALIGN_t)((group_ptr->CHCTR[ch_num] & (uint32_t)VADC_G_CHCTR_RESPOS_Msk) >> in XMC_VADC_GROUP_ChannelGetResultAlignment()
4440 (uint32_t)VADC_G_CHCTR_RESPOS_Pos) ); in XMC_VADC_GROUP_ChannelGetResultAlignment()
4461 const uint32_t ch_num) in XMC_VADC_GROUP_ChannelGetInputClass()
4467 …return ((XMC_VADC_CHANNEL_CONV_t)((group_ptr->CHCTR[ch_num] & (uint32_t)VADC_G_CHCTR_ICLSEL_Msk) >> in XMC_VADC_GROUP_ChannelGetInputClass()
4468 (uint32_t)VADC_G_CHCTR_ICLSEL_Pos) ); in XMC_VADC_GROUP_ChannelGetInputClass()
4489 uint8_t XMC_VADC_GROUP_ChannelGetResultRegister(XMC_VADC_GROUP_t *const group_ptr, const uint32_t c…
4507 void XMC_VADC_GROUP_ChannelTriggerEvent(XMC_VADC_GROUP_t *const group_ptr, const uint32_t ch_num);
4522 __STATIC_INLINE uint32_t XMC_VADC_GROUP_ChannelGetAssertedEvents(XMC_VADC_GROUP_t *const group_ptr) in XMC_VADC_GROUP_ChannelGetAssertedEvents()
4544 …INE void XMC_VADC_GROUP_ChannelClearEvent(XMC_VADC_GROUP_t *const group_ptr, const uint32_t ch_num) in XMC_VADC_GROUP_ChannelClearEvent()
4549 group_ptr->CEFCLR = (uint32_t)((uint32_t)1 << ch_num); in XMC_VADC_GROUP_ChannelClearEvent()
4570 const uint32_t ch_num,
4591 const uint32_t ch_num,
4614 const uint32_t ch_num,
4640 const uint32_t res_reg_num, in XMC_VADC_GROUP_ResultInit()
4672 void XMC_VADC_GROUP_AddResultToFifo(XMC_VADC_GROUP_t *const group_ptr, const uint32_t res_reg);
4692 …NE void XMC_VADC_GROUP_EnableResultEvent(XMC_VADC_GROUP_t *const group_ptr, const uint32_t res_reg) in XMC_VADC_GROUP_EnableResultEvent()
4697 group_ptr->RCR[res_reg] |= (uint32_t)VADC_G_RCR_SRGEN_Msk; in XMC_VADC_GROUP_EnableResultEvent()
4715 …E void XMC_VADC_GROUP_DisableResultEvent(XMC_VADC_GROUP_t *const group_ptr, const uint32_t res_reg) in XMC_VADC_GROUP_DisableResultEvent()
4719 group_ptr->RCR[res_reg] &= ~((uint32_t)VADC_G_RCR_SRGEN_Msk); in XMC_VADC_GROUP_DisableResultEvent()
4741 __STATIC_INLINE uint32_t XMC_VADC_GROUP_GetDetailedResult(XMC_VADC_GROUP_t *const group_ptr, const … in XMC_VADC_GROUP_GetDetailedResult()
4765 const uint32_t res_reg) in XMC_VADC_GROUP_GetResult()
4797 const uint32_t res_reg,
4816 …E_t XMC_VADC_GROUP_GetFastCompareResult(XMC_VADC_GROUP_t *const group_ptr, const uint32_t res_reg);
4855 …E void XMC_VADC_GROUP_TriggerResultEvent(XMC_VADC_GROUP_t *const group_ptr, const uint32_t res_reg) in XMC_VADC_GROUP_TriggerResultEvent()
4859 group_ptr->REFLAG = (uint32_t)((uint32_t)1 << res_reg); in XMC_VADC_GROUP_TriggerResultEvent()
4875 __STATIC_INLINE uint32_t XMC_VADC_GROUP_GetAssertedResultEvents(XMC_VADC_GROUP_t *const group_ptr) in XMC_VADC_GROUP_GetAssertedResultEvents()
4897 …INE void XMC_VADC_GROUP_ClearResultEvent(XMC_VADC_GROUP_t *const group_ptr, const uint32_t res_reg) in XMC_VADC_GROUP_ClearResultEvent()
4901 group_ptr->REFCLR = (uint32_t)((uint32_t)1 << res_reg); in XMC_VADC_GROUP_ClearResultEvent()
4922 const uint32_t res_reg,
4942 uint32_t XMC_VADC_GROUP_GetResultFifoTail(XMC_VADC_GROUP_t *const group_ptr, uint32_t res_reg);
4961 uint32_t XMC_VADC_GROUP_GetResultFifoHead(XMC_VADC_GROUP_t *const group_ptr,const uint32_t res_reg);
4980 bool XMC_VADC_GROUP_IsResultRegisterFifoHead(XMC_VADC_GROUP_t *const group_ptr, const uint32_t res_…
4998 const uint32_t res_reg) in XMC_VADC_GROUP_IsResultRegisterInFifo()
5004 return( (bool)(group_ptr->RCR[res_reg] & (uint32_t)VADC_G_RCR_FEN_Msk)); in XMC_VADC_GROUP_IsResultRegisterInFifo()
5026 …oid XMC_VADC_GROUP_SetResultRegPriority(XMC_VADC_GROUP_t *const group_ptr, const uint32_t res_mask) in XMC_VADC_GROUP_SetResultRegPriority()
5029 group_ptr->RRASS = (uint32_t)res_mask; in XMC_VADC_GROUP_SetResultRegPriority()
5044 __STATIC_INLINE uint32_t XMC_VADC_GROUP_GetResultRegPriority(XMC_VADC_GROUP_t *const group_ptr) in XMC_VADC_GROUP_GetResultRegPriority()