Searched refs:RCU (Results 1 – 8 of 8) sorted by relevance
44 #define RCU RCU_BASE macro48 #define RCU_CTL REG32(RCU + 0x00000000U) /*!< control register */49 #define RCU_CFG0 REG32(RCU + 0x00000004U) /*!< clock configuration re…50 #define RCU_INT REG32(RCU + 0x00000008U) /*!< clock interrupt regist…51 #define RCU_APB2RST REG32(RCU + 0x0000000CU) /*!< APB2 reset register */52 #define RCU_APB1RST REG32(RCU + 0x00000010U) /*!< APB1 reset register */53 #define RCU_AHBEN REG32(RCU + 0x00000014U) /*!< AHB enable register */54 #define RCU_APB2EN REG32(RCU + 0x00000018U) /*!< APB2 enable register */55 #define RCU_APB1EN REG32(RCU + 0x0000001CU) /*!< APB1 enable register */56 #define RCU_BDCTL REG32(RCU + 0x00000020U) /*!< backup domain control …[all …]
44 #define RCU RCU_BASE macro47 #define RCU_CTL REG32(RCU + 0x00U) /*!< control register */48 #define RCU_PLL REG32(RCU + 0x04U) /*!< PLL register */49 #define RCU_CFG0 REG32(RCU + 0x08U) /*!< clock configuration register…50 #define RCU_INT REG32(RCU + 0x0CU) /*!< clock interrupt register */51 #define RCU_AHB1RST REG32(RCU + 0x10U) /*!< AHB1 reset register */52 #define RCU_AHB2RST REG32(RCU + 0x14U) /*!< AHB2 reset register */53 #define RCU_AHB3RST REG32(RCU + 0x18U) /*!< AHB3 reset register */54 #define RCU_APB1RST REG32(RCU + 0x20U) /*!< APB1 reset register */55 #define RCU_APB2RST REG32(RCU + 0x24U) /*!< APB2 reset register */[all …]
43 #define RCU RCU_BASE macro46 #define RCU_CTL0 REG32(RCU + 0x00000000U) /*!< control register 0 */47 #define RCU_CFG0 REG32(RCU + 0x00000004U) /*!< configuration register 0 */48 #define RCU_INT REG32(RCU + 0x00000008U) /*!< interrupt register */49 #define RCU_APB2RST REG32(RCU + 0x0000000CU) /*!< APB2 reset register */50 #define RCU_APB1RST REG32(RCU + 0x00000010U) /*!< APB1 reset register */51 #define RCU_AHBEN REG32(RCU + 0x00000014U) /*!< AHB enable register */52 #define RCU_APB2EN REG32(RCU + 0x00000018U) /*!< APB2 enable register */53 #define RCU_APB1EN REG32(RCU + 0x0000001CU) /*!< APB1 enable register */54 #define RCU_BDCTL REG32(RCU + 0x00000020U) /*!< backup domain control regi…[all …]
44 #define RCU RCU_BASE macro47 #define RCU_CTL REG32(RCU + 0x00U) /*!< control register */48 #define RCU_CFG0 REG32(RCU + 0x04U) /*!< clock configuration register…49 #define RCU_INT REG32(RCU + 0x08U) /*!< clock interrupt register */50 #define RCU_APB2RST REG32(RCU + 0x0CU) /*!< APB2 reset register */51 #define RCU_APB1RST REG32(RCU + 0x10U) /*!< APB1 reset register */52 #define RCU_AHBEN REG32(RCU + 0x14U) /*!< AHB1 enable register */53 #define RCU_APB2EN REG32(RCU + 0x18U) /*!< APB2 enable register */54 #define RCU_APB1EN REG32(RCU + 0x1CU) /*!< APB1 enable register */55 #define RCU_BDCTL REG32(RCU + 0x20U) /*!< backup domain control regist…[all …]
41 #define RCU RCU_BASE /*!< RCU base address… macro44 #define RCU_CTL REG32(RCU + 0x00000000U) /*!< control register…45 #define RCU_CFG0 REG32(RCU + 0x00000004U) /*!< clock configurat…46 #define RCU_INT REG32(RCU + 0x00000008U) /*!< clock interrupt …47 #define RCU_APB2RST REG32(RCU + 0x0000000CU) /*!< APB2 reset regis…48 #define RCU_APB1RST REG32(RCU + 0x00000010U) /*!< APB1 reset regis…49 #define RCU_AHBEN REG32(RCU + 0x00000014U) /*!< AHB1 enable regi…50 #define RCU_APB2EN REG32(RCU + 0x00000018U) /*!< APB2 enable regi…51 #define RCU_APB1EN REG32(RCU + 0x0000001CU) /*!< APB1 enable regi…52 #define RCU_BDCTL REG32(RCU + 0x00000020U) /*!< backup domain co…[all …]
43 #define RCU RCU_BASE macro46 #define RCU_CTL REG32(RCU + 0x00U) /*!< control register */47 #define RCU_CFG0 REG32(RCU + 0x04U) /*!< clock configuration register…48 #define RCU_INT REG32(RCU + 0x08U) /*!< clock interrupt register */49 #define RCU_APB2RST REG32(RCU + 0x0CU) /*!< APB2 reset register */50 #define RCU_APB1RST REG32(RCU + 0x10U) /*!< APB1 reset register */51 #define RCU_AHBEN REG32(RCU + 0x14U) /*!< AHB1 enable register */52 #define RCU_APB2EN REG32(RCU + 0x18U) /*!< APB2 enable register */53 #define RCU_APB1EN REG32(RCU + 0x1CU) /*!< APB1 enable register */54 #define RCU_BDCTL REG32(RCU + 0x20U) /*!< backup domain control regist…[all …]
41 #define RCU RCU_BASE macro44 #define RCU_CTL REG32(RCU + 0x00000000U) /*!< control register 0 */45 #define RCU_CFG0 REG32(RCU + 0x00000004U) /*!< configuration register 0 */46 #define RCU_INT REG32(RCU + 0x00000008U) /*!< interrupt register */47 #define RCU_APB2RST REG32(RCU + 0x0000000CU) /*!< APB2 reset register */48 #define RCU_APB1RST REG32(RCU + 0x00000010U) /*!< APB1 reset register */49 #define RCU_AHBEN REG32(RCU + 0x00000014U) /*!< AHB enable register */50 #define RCU_APB2EN REG32(RCU + 0x00000018U) /*!< APB2 enable register */51 #define RCU_APB1EN REG32(RCU + 0x0000001CU) /*!< APB1 enable register */52 #define RCU_BDCTL REG32(RCU + 0x00000020U) /*!< backup domain control regi…[all …]
42 #define RCU RCU_BASE macro46 #define RCU_CTL REG32(RCU + 0x00U) /*!< control register */47 #define RCU_CFG0 REG32(RCU + 0x04U) /*!< clock configuration register…48 #define RCU_INT REG32(RCU + 0x08U) /*!< clock interrupt register */49 #define RCU_APB2RST REG32(RCU + 0x0CU) /*!< APB2 reset register */50 #define RCU_APB1RST REG32(RCU + 0x10U) /*!< APB1 reset register */51 #define RCU_AHBEN REG32(RCU + 0x14U) /*!< AHB1 enable register */52 #define RCU_APB2EN REG32(RCU + 0x18U) /*!< APB2 enable register */53 #define RCU_APB1EN REG32(RCU + 0x1CU) /*!< APB1 enable register */54 #define RCU_BDCTL REG32(RCU + 0x20U) /*!< backup domain control regist…[all …]
