Lines Matching refs:RCU
44 #define RCU RCU_BASE macro
48 #define RCU_CTL REG32(RCU + 0x00000000U) /*!< control register */
49 #define RCU_CFG0 REG32(RCU + 0x00000004U) /*!< clock configuration re…
50 #define RCU_INT REG32(RCU + 0x00000008U) /*!< clock interrupt regist…
51 #define RCU_APB2RST REG32(RCU + 0x0000000CU) /*!< APB2 reset register */
52 #define RCU_APB1RST REG32(RCU + 0x00000010U) /*!< APB1 reset register */
53 #define RCU_AHBEN REG32(RCU + 0x00000014U) /*!< AHB enable register */
54 #define RCU_APB2EN REG32(RCU + 0x00000018U) /*!< APB2 enable register */
55 #define RCU_APB1EN REG32(RCU + 0x0000001CU) /*!< APB1 enable register */
56 #define RCU_BDCTL REG32(RCU + 0x00000020U) /*!< backup domain control …
57 #define RCU_RSTSCK REG32(RCU + 0x00000024U) /*!< reset source / clock r…
58 #define RCU_CFG1 REG32(RCU + 0x0000002CU) /*!< clock configuration re…
59 #define RCU_DSV REG32(RCU + 0x00000034U) /*!< deep-sleep mode voltag…
60 #define RCU_ADDCTL REG32(RCU + 0x000000C0U) /*!< Additional clock contr…
61 #define RCU_ADDINT REG32(RCU + 0x000000CCU) /*!< Additional clock inter…
62 #define RCU_ADDAPB1RST REG32(RCU + 0x000000E0U) /*!< APB1 additional reset …
63 #define RCU_ADDAPB1EN REG32(RCU + 0x000000E4U) /*!< APB1 additional enable…
64 #define RCU_CFG2 REG32(RCU + 0x000000D4U) /*!< clock configuration re…
65 #define RCU_ADDAPB1RST REG32(RCU + 0x000000E0U) /*!< APB1 additional reset …
66 #define RCU_ADDAPB1EN REG32(RCU + 0x000000E4U) /*!< APB1 additional enable…
68 #define RCU_CTL REG32(RCU + 0x00000000U) /*!< control register */
69 #define RCU_CFG0 REG32(RCU + 0x00000004U) /*!< clock configuration re…
70 #define RCU_INT REG32(RCU + 0x00000008U) /*!< clock interrupt regist…
71 #define RCU_APB2RST REG32(RCU + 0x0000000CU) /*!< APB2 reset register */
72 #define RCU_APB1RST REG32(RCU + 0x00000010U) /*!< APB1 reset register */
73 #define RCU_AHBEN REG32(RCU + 0x00000014U) /*!< AHB1 enable register */
74 #define RCU_APB2EN REG32(RCU + 0x00000018U) /*!< APB2 enable register */
75 #define RCU_APB1EN REG32(RCU + 0x0000001CU) /*!< APB1 enable register */
76 #define RCU_BDCTL REG32(RCU + 0x00000020U) /*!< backup domain control …
77 #define RCU_RSTSCK REG32(RCU + 0x00000024U) /*!< reset source / clock r…
78 #define RCU_AHBRST REG32(RCU + 0x00000028U) /*!< AHB reset register */
79 #define RCU_CFG1 REG32(RCU + 0x0000002CU) /*!< clock configuration re…
80 #define RCU_DSV REG32(RCU + 0x00000034U) /*!< deep-sleep mode voltag…
81 #define RCU_ADDCTL REG32(RCU + 0x000000C0U) /*!< Additional clock contr…
82 #define RCU_ADDCFG REG32(RCU + 0x000000C4U) /*!< Additional clock confi…
83 #define RCU_ADDINT REG32(RCU + 0x000000CCU) /*!< Additional clock inter…
84 #define RCU_PLLSSCTL REG32(RCU + 0x000000D0U) /*!< PLL clock spread spect…
85 #define RCU_CFG2 REG32(RCU + 0x000000D4U) /*!< clock configuration re…
86 #define RCU_ADDAPB1RST REG32(RCU + 0x000000E0U) /*!< APB1 additional reset …
87 #define RCU_ADDAPB1EN REG32(RCU + 0x000000E4U) /*!< APB1 additional enable…
89 #define RCU_CTL REG32(RCU + 0x00000000U) /*!< control register */
90 #define RCU_CFG0 REG32(RCU + 0x00000004U) /*!< clock configuration re…
91 #define RCU_INT REG32(RCU + 0x00000008U) /*!< clock interrupt regist…
92 #define RCU_APB2RST REG32(RCU + 0x0000000CU) /*!< APB2 reset register */
93 #define RCU_APB1RST REG32(RCU + 0x00000010U) /*!< APB1 reset register */
94 #define RCU_AHBEN REG32(RCU + 0x00000014U) /*!< AHB1 enable register */
95 #define RCU_APB2EN REG32(RCU + 0x00000018U) /*!< APB2 enable register */
96 #define RCU_APB1EN REG32(RCU + 0x0000001CU) /*!< APB1 enable register */
97 #define RCU_BDCTL REG32(RCU + 0x00000020U) /*!< backup domain control …
98 #define RCU_RSTSCK REG32(RCU + 0x00000024U) /*!< reset source / clock r…
99 #define RCU_AHBRST REG32(RCU + 0x00000028U) /*!< AHB reset register */
100 #define RCU_CFG1 REG32(RCU + 0x0000002CU) /*!< clock configuration re…
101 #define RCU_DSV REG32(RCU + 0x00000034U) /*!< deep-sleep mode voltag…
102 #define RCU_ADDCTL REG32(RCU + 0x000000C0U) /*!< Additional clock contr…
103 #define RCU_ADDINT REG32(RCU + 0x000000CCU) /*!< Additional clock inter…
104 #define RCU_PLLSSCTL REG32(RCU + 0x000000D0U) /*!< PLL clock spread spect…
105 #define RCU_CFG2 REG32(RCU + 0x000000D4U) /*!< clock configuration re…
106 #define RCU_ADDAPB1RST REG32(RCU + 0x000000E0U) /*!< APB1 additional reset …
107 #define RCU_ADDAPB1EN REG32(RCU + 0x000000E4U) /*!< APB1 additional enable…
497 #define RCU_REG_VAL(periph) (REG32(RCU + ((uint32_t)(periph) >> 6)))