Lines Matching refs:RCU
44 #define RCU RCU_BASE macro
47 #define RCU_CTL REG32(RCU + 0x00U) /*!< control register */
48 #define RCU_PLL REG32(RCU + 0x04U) /*!< PLL register */
49 #define RCU_CFG0 REG32(RCU + 0x08U) /*!< clock configuration register…
50 #define RCU_INT REG32(RCU + 0x0CU) /*!< clock interrupt register */
51 #define RCU_AHB1RST REG32(RCU + 0x10U) /*!< AHB1 reset register */
52 #define RCU_AHB2RST REG32(RCU + 0x14U) /*!< AHB2 reset register */
53 #define RCU_AHB3RST REG32(RCU + 0x18U) /*!< AHB3 reset register */
54 #define RCU_APB1RST REG32(RCU + 0x20U) /*!< APB1 reset register */
55 #define RCU_APB2RST REG32(RCU + 0x24U) /*!< APB2 reset register */
56 #define RCU_AHB1EN REG32(RCU + 0x30U) /*!< AHB1 enable register */
57 #define RCU_AHB2EN REG32(RCU + 0x34U) /*!< AHB2 enable register */
58 #define RCU_AHB3EN REG32(RCU + 0x38U) /*!< AHB3 enable register */
59 #define RCU_APB1EN REG32(RCU + 0x40U) /*!< APB1 enable register */
60 #define RCU_APB2EN REG32(RCU + 0x44U) /*!< APB2 enable register */
61 #define RCU_AHB1SPEN REG32(RCU + 0x50U) /*!< AHB1 sleep mode enable regis…
62 #define RCU_AHB2SPEN REG32(RCU + 0x54U) /*!< AHB2 sleep mode enable regis…
63 #define RCU_AHB3SPEN REG32(RCU + 0x58U) /*!< AHB3 sleep mode enable regis…
64 #define RCU_APB1SPEN REG32(RCU + 0x60U) /*!< APB1 sleep mode enable regis…
65 #define RCU_APB2SPEN REG32(RCU + 0x64U) /*!< APB2 sleep mode enable regis…
66 #define RCU_BDCTL REG32(RCU + 0x70U) /*!< backup domain control regist…
67 #define RCU_RSTSCK REG32(RCU + 0x74U) /*!< reset source / clock registe…
68 #define RCU_PLLSSCTL REG32(RCU + 0x80U) /*!< PLL clock spread spectrum co…
69 #define RCU_PLLI2S REG32(RCU + 0x84U) /*!< PLLI2S register */
70 #define RCU_PLLSAI REG32(RCU + 0x88U) /*!< PLLSAI register */
71 #define RCU_CFG1 REG32(RCU + 0x8CU) /*!< clock configuration register…
72 #define RCU_ADDCTL REG32(RCU + 0xC0U) /*!< Additional clock control reg…
73 #define RCU_ADDINT REG32(RCU + 0xCCU) /*!< Additional clock interrupt r…
74 #define RCU_ADDAPB1RST REG32(RCU + 0xE0U) /*!< APB1 additional reset regist…
75 #define RCU_ADDAPB1EN REG32(RCU + 0xE4U) /*!< APB1 additional enable regis…
76 #define RCU_ADDAPB1SPEN REG32(RCU + 0xE8U) /*!< APB1 additional sleep mode e…
77 #define RCU_VKEY REG32(RCU + 0x100U) /*!< voltage key register */
78 #define RCU_DSV REG32(RCU + 0x134U) /*!< deep-sleep mode voltage regi…
447 #define RCU_REG_VAL(periph) (REG32(RCU + ((uint32_t)(periph) >> 6)))