Lines Matching refs:RCU
43 #define RCU RCU_BASE macro
46 #define RCU_CTL0 REG32(RCU + 0x00000000U) /*!< control register 0 */
47 #define RCU_CFG0 REG32(RCU + 0x00000004U) /*!< configuration register 0 */
48 #define RCU_INT REG32(RCU + 0x00000008U) /*!< interrupt register */
49 #define RCU_APB2RST REG32(RCU + 0x0000000CU) /*!< APB2 reset register */
50 #define RCU_APB1RST REG32(RCU + 0x00000010U) /*!< APB1 reset register */
51 #define RCU_AHBEN REG32(RCU + 0x00000014U) /*!< AHB enable register */
52 #define RCU_APB2EN REG32(RCU + 0x00000018U) /*!< APB2 enable register */
53 #define RCU_APB1EN REG32(RCU + 0x0000001CU) /*!< APB1 enable register */
54 #define RCU_BDCTL REG32(RCU + 0x00000020U) /*!< backup domain control regi…
55 #define RCU_RSTSCK REG32(RCU + 0x00000024U) /*!< reset source /clock regist…
56 #define RCU_AHBRST REG32(RCU + 0x00000028U) /*!< AHB reset register */
57 #define RCU_CFG1 REG32(RCU + 0x0000002CU) /*!< configuration register 1 */
58 #define RCU_CFG2 REG32(RCU + 0x00000030U) /*!< configuration register 2 */
59 #define RCU_CTL1 REG32(RCU + 0x00000034U) /*!< control register 1 */
60 #define RCU_ADDCTL REG32(RCU + 0x000000C0U) /*!< additional clock control r…
61 #define RCU_ADDINT REG32(RCU + 0x000000CCU) /*!< additional clock interrupt…
62 #define RCU_ADDAPB1EN REG32(RCU + 0x000000F8U) /*!< APB1 additional enable reg…
63 #define RCU_ADDAPB1RST REG32(RCU + 0x000000FCU) /*!< APB1 additional reset regi…
64 #define RCU_VKEY REG32(RCU + 0x00000100U) /*!< voltage key register */
65 #define RCU_DSV REG32(RCU + 0x00000134U) /*!< deep-sleep mode voltage re…
255 #define RCU_REG_VAL(periph) (REG32(RCU + ((uint32_t)(periph)>>6)))