Lines Matching refs:RCU
44 #define RCU RCU_BASE macro
47 #define RCU_CTL REG32(RCU + 0x00U) /*!< control register */
48 #define RCU_CFG0 REG32(RCU + 0x04U) /*!< clock configuration register…
49 #define RCU_INT REG32(RCU + 0x08U) /*!< clock interrupt register */
50 #define RCU_APB2RST REG32(RCU + 0x0CU) /*!< APB2 reset register */
51 #define RCU_APB1RST REG32(RCU + 0x10U) /*!< APB1 reset register */
52 #define RCU_AHBEN REG32(RCU + 0x14U) /*!< AHB1 enable register */
53 #define RCU_APB2EN REG32(RCU + 0x18U) /*!< APB2 enable register */
54 #define RCU_APB1EN REG32(RCU + 0x1CU) /*!< APB1 enable register */
55 #define RCU_BDCTL REG32(RCU + 0x20U) /*!< backup domain control regist…
56 #define RCU_RSTSCK REG32(RCU + 0x24U) /*!< reset source / clock registe…
57 #define RCU_AHBRST REG32(RCU + 0x28U) /*!< AHB reset register */
58 #define RCU_CFG1 REG32(RCU + 0x2CU) /*!< clock configuration register…
59 #define RCU_DSV REG32(RCU + 0x34U) /*!< deep-sleep mode voltage regi…
60 #define RCU_ADDCTL REG32(RCU + 0xC0U) /*!< Additional clock control reg…
61 #define RCU_ADDINT REG32(RCU + 0xCCU) /*!< Additional clock interrupt r…
62 #define RCU_ADDAPB1RST REG32(RCU + 0xE0U) /*!< APB1 additional reset regist…
63 #define RCU_ADDAPB1EN REG32(RCU + 0xE4U) /*!< APB1 additional enable regis…
271 #define RCU_REG_VAL(periph) (REG32(RCU + ((uint32_t)(periph) >> 6)))