| /hal_espressif-latest/components/hal/ |
| D | rmt_hal.c | 12 hal->regs = &RMT; in rmt_hal_init()
13 rmt_ll_mem_power_by_pmu(hal->regs); in rmt_hal_init()
14 rmt_ll_enable_mem_access_nonfifo(hal->regs, true); // APB access the RMTMEM in nonfifo mode in rmt_hal_init()
15 rmt_ll_enable_interrupt(hal->regs, UINT32_MAX, false); // disable all interupt events in rmt_hal_init()
16 rmt_ll_clear_interrupt_status(hal->regs, UINT32_MAX); // clear all pending events in rmt_hal_init()
17 rmt_ll_enable_group_clock(hal->regs, true); // enable clock source in rmt_hal_init()
19 rmt_ll_tx_clear_sync_group(hal->regs); in rmt_hal_init()
25 rmt_ll_enable_interrupt(hal->regs, UINT32_MAX, false); // disable all interupt events in rmt_hal_deinit()
26 rmt_ll_clear_interrupt_status(hal->regs, UINT32_MAX); // clear all pending events in rmt_hal_deinit()
27 … rmt_ll_mem_force_power_off(hal->regs); // power off RMTMEM power domain forcefully in rmt_hal_deinit()
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| D | usb_dwc_hal.c | 278 chan_obj->regs = usb_dwc_ll_chan_get_regs(hal->dev, chan_idx); in usb_dwc_hal_chan_alloc()
282 …usb_dwc_ll_hcint_read_and_clear_intrs(chan_obj->regs); //Clear the interrupt bits for t… in usb_dwc_hal_chan_alloc()
284 …usb_dwc_ll_hcintmsk_set_intr_mask(chan_obj->regs, CHAN_INTRS_EN_MSK); //Unmask interrupts for thi… in usb_dwc_hal_chan_alloc()
285 usb_dwc_ll_hctsiz_set_pid(chan_obj->regs, 0); //Set the initial PID to zero in usb_dwc_hal_chan_alloc()
286 …usb_dwc_ll_hctsiz_init(chan_obj->regs); //Set the non changing parts of the HCTSIZ registers… in usb_dwc_hal_chan_alloc()
315 usb_dwc_ll_hcchar_init(chan_obj->regs, in usb_dwc_hal_chan_set_ep_char()
367 … usb_dwc_ll_hctsiz_set_sched_info(chan_obj->regs, tokens_per_frame, ep_char->periodic.offset); in usb_dwc_hal_chan_set_ep_char()
379 usb_dwc_ll_hcdma_set_qtd_list_addr(chan_obj->regs, xfer_desc_list, start_idx); in usb_dwc_hal_chan_activate()
380 usb_dwc_ll_hctsiz_set_qtd_list_len(chan_obj->regs, desc_list_len); in usb_dwc_hal_chan_activate()
381 usb_dwc_ll_hcchar_enable_chan(chan_obj->regs); //Start the channel in usb_dwc_hal_chan_activate()
[all …]
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| D | parlio_hal.c | 14 hal->regs = &PARL_IO; in parlio_hal_init()
19 hal->regs = NULL; in parlio_hal_deinit()
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| D | etm_hal.c | 13 hal->regs = &SOC_ETM; in etm_hal_init()
18 hal->regs = NULL; in etm_hal_deinit()
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| /hal_espressif-latest/components/driver/deprecated/ |
| D | rmt_legacy.c | 101 .hal.regs = &RMT,
151 … rmt_ll_rx_set_channel_clock_div(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), div_cnt); in rmt_set_clk_div()
153 rmt_ll_tx_set_channel_clock_div(rmt_contex.hal.regs, channel, div_cnt); in rmt_set_clk_div()
165 …*div_cnt = (uint8_t)rmt_ll_rx_get_channel_clock_div(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(cha… in rmt_get_clk_div()
167 *div_cnt = (uint8_t)rmt_ll_tx_get_channel_clock_div(rmt_contex.hal.regs, channel); in rmt_get_clk_div()
177 rmt_ll_rx_set_idle_thres(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), thresh); in rmt_set_rx_idle_thresh()
187 … *thresh = (uint16_t)rmt_ll_rx_get_idle_thres(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel)); in rmt_get_rx_idle_thresh()
198 rmt_ll_rx_set_mem_blocks(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), rmt_mem_num); in rmt_set_mem_block_num()
200 rmt_ll_tx_set_mem_blocks(rmt_contex.hal.regs, channel, rmt_mem_num); in rmt_set_mem_block_num()
212 …*rmt_mem_num = (uint8_t)rmt_ll_rx_get_mem_blocks(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channe… in rmt_get_mem_block_num()
[all …]
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| /hal_espressif-latest/components/esp_system/port/arch/riscv/ |
| D | panic_arch.c | 224 uint32_t *regs = (uint32_t *)f; in panic_print_registers() local
245 panic_print_hex(regs[x + y]); in panic_print_registers()
314 RvExcFrame *regs = (RvExcFrame *) frame; in panic_arch_fill_info() local
338 if (regs->mcause < (sizeof(reason) / sizeof(reason[0]))) { in panic_arch_fill_info()
339 if (reason[regs->mcause] != NULL) { in panic_arch_fill_info()
340 info->reason = (reason[regs->mcause]); in panic_arch_fill_info()
346 info->addr = (void *) regs->mepc; in panic_arch_fill_info()
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| /hal_espressif-latest/components/esp_hw_support/ |
| D | esp_etm.c | 213 etm_ll_channel_set_event(group->hal.regs, chan_id, 0); in esp_etm_del_channel()
214 etm_ll_channel_set_task(group->hal.regs, chan_id, 0); in esp_etm_del_channel()
227 etm_ll_enable_channel(group->hal.regs, chan->chan_id); in esp_etm_channel_enable()
237 etm_ll_disable_channel(group->hal.regs, chan->chan_id); in esp_etm_channel_disable()
256 etm_ll_channel_set_event(group->hal.regs, chan->chan_id, event_id); in esp_etm_channel_connect()
257 etm_ll_channel_set_task(group->hal.regs, chan->chan_id, task_id); in esp_etm_channel_connect()
293 if (etm_ll_is_channel_enabled(hal->regs, j)) { in esp_etm_dump()
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| /hal_espressif-latest/components/hal/include/hal/ |
| D | usb_dwc_hal.h | 164 usb_dwc_host_chan_regs_t *regs; /**< Pointer to the channel's register set */ member
587 usb_dwc_ll_hcchar_set_dir(chan_obj->regs, is_in); in usb_dwc_hal_chan_set_dir()
607 usb_dwc_ll_hctsiz_set_pid(chan_obj->regs, pid); in usb_dwc_hal_chan_set_pid()
623 return usb_dwc_ll_hctsiz_get_pid(chan_obj->regs); in usb_dwc_hal_chan_get_pid()
651 return usb_dwc_ll_hcdam_get_cur_qtd_idx(chan_obj->regs); in usb_dwc_hal_chan_get_qtd_idx()
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| D | etm_hal.h | 27 etm_soc_handle_t regs; /*!< ETM Register base address */ member
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| D | parlio_hal.h | 27 parlio_soc_handle_t regs; /*!< Parallel IO Register base address */ member
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| D | rmt_hal.h | 27 rmt_soc_handle_t regs; /*!< RMT Register base address */ member
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| /hal_espressif-latest/components/esp_system/port/arch/xtensa/ |
| D | panic_arch.c | 37 int *regs = (int *)frame; in panic_print_registers() local
38 (void)regs; in panic_print_registers()
59 panic_print_hex(regs[x + y + 1]); in panic_print_registers()
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| /hal_espressif-latest/components/hal/esp32s3/include/hal/ |
| D | mspi_timing_tuning_ll.h | 62 uint32_t regs[] = {IO_MUX_GPIO27_REG, IO_MUX_GPIO28_REG, in mspi_timing_ll_set_all_pin_drive() local
67 for (int i = 0; i < ARRAY_SIZE(regs); i++) { in mspi_timing_ll_set_all_pin_drive()
68 PIN_SET_DRV(regs[i], val); in mspi_timing_ll_set_all_pin_drive()
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