1 /*
2 * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6 #include <stdlib.h>
7 #include <string.h>
8 #include <sys/lock.h>
9 #include <sys/cdefs.h>
10 #include "esp_compiler.h"
11 #include "esp_intr_alloc.h"
12 #include "esp_log.h"
13 #include "esp_check.h"
14 #include "driver/gpio.h"
15 #include "esp_private/periph_ctrl.h"
16 #include "driver/rmt_types_legacy.h"
17 #include "freertos/FreeRTOS.h"
18 #include "freertos/task.h"
19 #include "freertos/semphr.h"
20 #include "freertos/ringbuf.h"
21 #include "soc/soc_memory_layout.h"
22 #include "soc/rmt_periph.h"
23 #include "soc/rmt_struct.h"
24 #include "esp_clk_tree.h"
25 #include "hal/rmt_hal.h"
26 #include "hal/rmt_ll.h"
27 #include "hal/gpio_hal.h"
28 #include "esp_rom_gpio.h"
29
30 #define RMT_CHANNEL_ERROR_STR "RMT CHANNEL ERR"
31 #define RMT_ADDR_ERROR_STR "RMT ADDRESS ERR"
32 #define RMT_MEM_CNT_ERROR_STR "RMT MEM BLOCK NUM ERR"
33 #define RMT_CARRIER_ERROR_STR "RMT CARRIER LEVEL ERR"
34 #define RMT_MEM_OWNER_ERROR_STR "RMT MEM OWNER_ERR"
35 #define RMT_BASECLK_ERROR_STR "RMT BASECLK ERR"
36 #define RMT_WR_MEM_OVF_ERROR_STR "RMT WR MEM OVERFLOW"
37 #define RMT_GPIO_ERROR_STR "RMT GPIO ERROR"
38 #define RMT_MODE_ERROR_STR "RMT MODE ERROR"
39 #define RMT_CLK_DIV_ERROR_STR "RMT CLK DIV ERR"
40 #define RMT_DRIVER_ERROR_STR "RMT DRIVER ERR"
41 #define RMT_DRIVER_LENGTH_ERROR_STR "RMT PARAM LEN ERROR"
42 #define RMT_PSRAM_BUFFER_WARN_STR "Using buffer allocated from psram"
43 #define RMT_TRANSLATOR_NULL_STR "RMT translator is null"
44 #define RMT_TRANSLATOR_UNINIT_STR "RMT translator not init"
45 #define RMT_PARAM_ERR_STR "RMT param error"
46
47 static const char *TAG = "rmt(legacy)";
48
49 // Spinlock for protecting concurrent register-level access only
50 #define RMT_ENTER_CRITICAL() portENTER_CRITICAL_SAFE(&(rmt_contex.rmt_spinlock))
51 #define RMT_EXIT_CRITICAL() portEXIT_CRITICAL_SAFE(&(rmt_contex.rmt_spinlock))
52
53 #define RMT_RX_CHANNEL_ENCODING_START (SOC_RMT_CHANNELS_PER_GROUP-SOC_RMT_TX_CANDIDATES_PER_GROUP)
54 #define RMT_TX_CHANNEL_ENCODING_END (SOC_RMT_TX_CANDIDATES_PER_GROUP-1)
55
56 #define RMT_IS_RX_CHANNEL(channel) ((channel) >= RMT_RX_CHANNEL_ENCODING_START)
57 #define RMT_IS_TX_CHANNEL(channel) ((channel) <= RMT_TX_CHANNEL_ENCODING_END)
58 #define RMT_DECODE_RX_CHANNEL(encode_chan) ((encode_chan - RMT_RX_CHANNEL_ENCODING_START))
59 #define RMT_ENCODE_RX_CHANNEL(decode_chan) ((decode_chan + RMT_RX_CHANNEL_ENCODING_START))
60
61 typedef struct {
62 rmt_hal_context_t hal;
63 _lock_t rmt_driver_isr_lock;
64 portMUX_TYPE rmt_spinlock; // Mutex lock for protecting concurrent register/unregister of RMT channels' ISR
65 rmt_isr_handle_t rmt_driver_intr_handle;
66 rmt_tx_end_callback_t rmt_tx_end_callback;// Event called when transmission is ended
67 uint8_t rmt_driver_channels; // Bitmask of installed drivers' channels, used to protect concurrent register/unregister of RMT channels' ISR
68 bool rmt_module_enabled;
69 uint32_t synchro_channel_mask; // Bitmap of channels already added in the synchronous group
70 } rmt_contex_t;
71
72 typedef struct {
73 size_t tx_offset;
74 size_t tx_len_rem;
75 size_t tx_sub_len;
76 bool translator;
77 bool wait_done; //Mark whether wait tx done.
78 bool loop_autostop; // mark whether loop auto-stop is enabled
79 rmt_channel_t channel;
80 const rmt_item32_t *tx_data;
81 SemaphoreHandle_t tx_sem;
82 #if CONFIG_SPIRAM_USE_MALLOC
83 int intr_alloc_flags;
84 StaticSemaphore_t tx_sem_buffer;
85 #endif
86 rmt_item32_t *tx_buf;
87 RingbufHandle_t rx_buf;
88 #if SOC_RMT_SUPPORT_RX_PINGPONG
89 rmt_item32_t *rx_item_buf;
90 uint32_t rx_item_buf_size;
91 uint32_t rx_item_len;
92 int rx_item_start_idx;
93 #endif
94 sample_to_rmt_t sample_to_rmt;
95 void *tx_context;
96 size_t sample_size_remain;
97 const uint8_t *sample_cur;
98 } rmt_obj_t;
99
100 static rmt_contex_t rmt_contex = {
101 .hal.regs = &RMT,
102 .rmt_spinlock = portMUX_INITIALIZER_UNLOCKED,
103 .rmt_driver_intr_handle = NULL,
104 .rmt_tx_end_callback = {
105 .function = NULL,
106 },
107 .rmt_driver_channels = 0,
108 .rmt_module_enabled = false,
109 .synchro_channel_mask = 0
110 };
111
112 static rmt_obj_t *p_rmt_obj[RMT_CHANNEL_MAX] = {0};
113
114 #if SOC_RMT_CHANNEL_CLK_INDEPENDENT
115 static uint32_t s_rmt_source_clock_hz[RMT_CHANNEL_MAX];
116 #else
117 static uint32_t s_rmt_source_clock_hz;
118 #endif
119
120 // RMTMEM address is declared in <target>.peripherals.ld
121 extern rmt_mem_t RMTMEM;
122
123 //Enable RMT module
rmt_module_enable(void)124 static void rmt_module_enable(void)
125 {
126 RMT_ENTER_CRITICAL();
127 if (rmt_contex.rmt_module_enabled == false) {
128 periph_module_reset(rmt_periph_signals.groups[0].module);
129 periph_module_enable(rmt_periph_signals.groups[0].module);
130 rmt_contex.rmt_module_enabled = true;
131 }
132 RMT_EXIT_CRITICAL();
133 }
134
135 //Disable RMT module
rmt_module_disable(void)136 static void rmt_module_disable(void)
137 {
138 RMT_ENTER_CRITICAL();
139 if (rmt_contex.rmt_module_enabled == true) {
140 periph_module_disable(rmt_periph_signals.groups[0].module);
141 rmt_contex.rmt_module_enabled = false;
142 }
143 RMT_EXIT_CRITICAL();
144 }
145
rmt_set_clk_div(rmt_channel_t channel,uint8_t div_cnt)146 esp_err_t rmt_set_clk_div(rmt_channel_t channel, uint8_t div_cnt)
147 {
148 ESP_RETURN_ON_FALSE(channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
149 RMT_ENTER_CRITICAL();
150 if (RMT_IS_RX_CHANNEL(channel)) {
151 rmt_ll_rx_set_channel_clock_div(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), div_cnt);
152 } else {
153 rmt_ll_tx_set_channel_clock_div(rmt_contex.hal.regs, channel, div_cnt);
154 }
155 RMT_EXIT_CRITICAL();
156 return ESP_OK;
157 }
158
rmt_get_clk_div(rmt_channel_t channel,uint8_t * div_cnt)159 esp_err_t rmt_get_clk_div(rmt_channel_t channel, uint8_t *div_cnt)
160 {
161 ESP_RETURN_ON_FALSE(channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
162 ESP_RETURN_ON_FALSE(div_cnt, ESP_ERR_INVALID_ARG, TAG, RMT_ADDR_ERROR_STR);
163 RMT_ENTER_CRITICAL();
164 if (RMT_IS_RX_CHANNEL(channel)) {
165 *div_cnt = (uint8_t)rmt_ll_rx_get_channel_clock_div(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel));
166 } else {
167 *div_cnt = (uint8_t)rmt_ll_tx_get_channel_clock_div(rmt_contex.hal.regs, channel);
168 }
169 RMT_EXIT_CRITICAL();
170 return ESP_OK;
171 }
172
rmt_set_rx_idle_thresh(rmt_channel_t channel,uint16_t thresh)173 esp_err_t rmt_set_rx_idle_thresh(rmt_channel_t channel, uint16_t thresh)
174 {
175 ESP_RETURN_ON_FALSE(RMT_IS_RX_CHANNEL(channel) && channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
176 RMT_ENTER_CRITICAL();
177 rmt_ll_rx_set_idle_thres(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), thresh);
178 RMT_EXIT_CRITICAL();
179 return ESP_OK;
180 }
181
rmt_get_rx_idle_thresh(rmt_channel_t channel,uint16_t * thresh)182 esp_err_t rmt_get_rx_idle_thresh(rmt_channel_t channel, uint16_t *thresh)
183 {
184 ESP_RETURN_ON_FALSE(RMT_IS_RX_CHANNEL(channel) && channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
185 ESP_RETURN_ON_FALSE(thresh, ESP_ERR_INVALID_ARG, TAG, RMT_ADDR_ERROR_STR);
186 RMT_ENTER_CRITICAL();
187 *thresh = (uint16_t)rmt_ll_rx_get_idle_thres(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel));
188 RMT_EXIT_CRITICAL();
189 return ESP_OK;
190 }
191
rmt_set_mem_block_num(rmt_channel_t channel,uint8_t rmt_mem_num)192 esp_err_t rmt_set_mem_block_num(rmt_channel_t channel, uint8_t rmt_mem_num)
193 {
194 ESP_RETURN_ON_FALSE(channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
195 ESP_RETURN_ON_FALSE(rmt_mem_num <= RMT_CHANNEL_MAX - channel, ESP_ERR_INVALID_ARG, TAG, RMT_MEM_CNT_ERROR_STR);
196 RMT_ENTER_CRITICAL();
197 if (RMT_IS_RX_CHANNEL(channel)) {
198 rmt_ll_rx_set_mem_blocks(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), rmt_mem_num);
199 } else {
200 rmt_ll_tx_set_mem_blocks(rmt_contex.hal.regs, channel, rmt_mem_num);
201 }
202 RMT_EXIT_CRITICAL();
203 return ESP_OK;
204 }
205
rmt_get_mem_block_num(rmt_channel_t channel,uint8_t * rmt_mem_num)206 esp_err_t rmt_get_mem_block_num(rmt_channel_t channel, uint8_t *rmt_mem_num)
207 {
208 ESP_RETURN_ON_FALSE(channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
209 ESP_RETURN_ON_FALSE(rmt_mem_num, ESP_ERR_INVALID_ARG, TAG, RMT_ADDR_ERROR_STR);
210 RMT_ENTER_CRITICAL();
211 if (RMT_IS_RX_CHANNEL(channel)) {
212 *rmt_mem_num = (uint8_t)rmt_ll_rx_get_mem_blocks(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel));
213 } else {
214 *rmt_mem_num = (uint8_t)rmt_ll_tx_get_mem_blocks(rmt_contex.hal.regs, channel);
215 }
216 RMT_EXIT_CRITICAL();
217 return ESP_OK;
218 }
219
rmt_set_tx_carrier(rmt_channel_t channel,bool carrier_en,uint16_t high_level,uint16_t low_level,rmt_carrier_level_t carrier_level)220 esp_err_t rmt_set_tx_carrier(rmt_channel_t channel, bool carrier_en, uint16_t high_level, uint16_t low_level,
221 rmt_carrier_level_t carrier_level)
222 {
223 ESP_RETURN_ON_FALSE(RMT_IS_TX_CHANNEL(channel), ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
224 ESP_RETURN_ON_FALSE(carrier_level < RMT_CARRIER_LEVEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CARRIER_ERROR_STR);
225 RMT_ENTER_CRITICAL();
226 rmt_ll_tx_set_carrier_high_low_ticks(rmt_contex.hal.regs, channel, high_level, low_level);
227 rmt_ll_tx_set_carrier_level(rmt_contex.hal.regs, channel, carrier_level);
228 rmt_ll_tx_enable_carrier_modulation(rmt_contex.hal.regs, channel, carrier_en);
229 RMT_EXIT_CRITICAL();
230 return ESP_OK;
231 }
232
rmt_set_mem_pd(rmt_channel_t channel,bool pd_en)233 esp_err_t rmt_set_mem_pd(rmt_channel_t channel, bool pd_en)
234 {
235 ESP_RETURN_ON_FALSE(channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
236 RMT_ENTER_CRITICAL();
237 rmt_ll_power_down_mem(rmt_contex.hal.regs, pd_en);
238 RMT_EXIT_CRITICAL();
239 return ESP_OK;
240 }
241
rmt_get_mem_pd(rmt_channel_t channel,bool * pd_en)242 esp_err_t rmt_get_mem_pd(rmt_channel_t channel, bool *pd_en)
243 {
244 ESP_RETURN_ON_FALSE(channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
245 RMT_ENTER_CRITICAL();
246 *pd_en = rmt_ll_is_mem_powered_down(rmt_contex.hal.regs);
247 RMT_EXIT_CRITICAL();
248 return ESP_OK;
249 }
250
rmt_tx_start(rmt_channel_t channel,bool tx_idx_rst)251 esp_err_t rmt_tx_start(rmt_channel_t channel, bool tx_idx_rst)
252 {
253 ESP_RETURN_ON_FALSE(RMT_IS_TX_CHANNEL(channel), ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
254 RMT_ENTER_CRITICAL();
255 if (tx_idx_rst) {
256 rmt_ll_tx_reset_pointer(rmt_contex.hal.regs, channel);
257 }
258 rmt_ll_clear_interrupt_status(rmt_contex.hal.regs, RMT_LL_EVENT_TX_DONE(channel));
259 // enable tx end interrupt in non-loop mode
260 if (!rmt_ll_tx_is_loop_enabled(rmt_contex.hal.regs, channel)) {
261 rmt_ll_enable_interrupt(rmt_contex.hal.regs, RMT_LL_EVENT_TX_DONE(channel), true);
262 } else {
263 #if SOC_RMT_SUPPORT_TX_LOOP_COUNT
264 rmt_ll_tx_reset_loop_count(rmt_contex.hal.regs, channel);
265 rmt_ll_tx_enable_loop_count(rmt_contex.hal.regs, channel, true);
266 rmt_ll_clear_interrupt_status(rmt_contex.hal.regs, RMT_LL_EVENT_TX_LOOP_END(channel));
267 rmt_ll_enable_interrupt(rmt_contex.hal.regs, RMT_LL_EVENT_TX_LOOP_END(channel), true);
268 #endif
269 }
270 rmt_ll_tx_start(rmt_contex.hal.regs, channel);
271 RMT_EXIT_CRITICAL();
272 return ESP_OK;
273 }
274
rmt_tx_stop(rmt_channel_t channel)275 esp_err_t rmt_tx_stop(rmt_channel_t channel)
276 {
277 ESP_RETURN_ON_FALSE(RMT_IS_TX_CHANNEL(channel), ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
278 RMT_ENTER_CRITICAL();
279 #if SOC_RMT_SUPPORT_TX_ASYNC_STOP
280 rmt_ll_tx_stop(rmt_contex.hal.regs, channel);
281 #else
282 // write ending marker to stop the TX channel
283 RMTMEM.chan[channel].data32[0].val = 0;
284 #endif
285 rmt_ll_tx_reset_pointer(rmt_contex.hal.regs, channel);
286 RMT_EXIT_CRITICAL();
287 return ESP_OK;
288 }
289
290 #if SOC_RMT_SUPPORT_RX_PINGPONG
rmt_set_rx_thr_intr_en(rmt_channel_t channel,bool en,uint16_t evt_thresh)291 esp_err_t rmt_set_rx_thr_intr_en(rmt_channel_t channel, bool en, uint16_t evt_thresh)
292 {
293 ESP_RETURN_ON_FALSE(RMT_IS_RX_CHANNEL(channel) && channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
294 if (en) {
295 uint32_t item_block_len = rmt_ll_rx_get_mem_blocks(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel)) * RMT_MEM_ITEM_NUM;
296 ESP_RETURN_ON_FALSE(evt_thresh <= item_block_len, ESP_ERR_INVALID_ARG, TAG, "RMT EVT THRESH ERR");
297 RMT_ENTER_CRITICAL();
298 rmt_ll_rx_set_limit(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), evt_thresh);
299 rmt_ll_enable_interrupt(rmt_contex.hal.regs, RMT_LL_EVENT_RX_THRES(RMT_DECODE_RX_CHANNEL(channel)), true);
300 RMT_EXIT_CRITICAL();
301 } else {
302 RMT_ENTER_CRITICAL();
303 rmt_ll_enable_interrupt(rmt_contex.hal.regs, RMT_LL_EVENT_RX_THRES(RMT_DECODE_RX_CHANNEL(channel)), false);
304 RMT_EXIT_CRITICAL();
305 }
306 return ESP_OK;
307 }
308 #endif
309
rmt_rx_start(rmt_channel_t channel,bool rx_idx_rst)310 esp_err_t rmt_rx_start(rmt_channel_t channel, bool rx_idx_rst)
311 {
312 ESP_RETURN_ON_FALSE(RMT_IS_RX_CHANNEL(channel) && channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
313 RMT_ENTER_CRITICAL();
314 rmt_ll_rx_enable(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), false);
315 if (rx_idx_rst) {
316 rmt_ll_rx_reset_pointer(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel));
317 }
318 rmt_ll_clear_interrupt_status(rmt_contex.hal.regs, RMT_LL_EVENT_RX_DONE(RMT_DECODE_RX_CHANNEL(channel)));
319 rmt_ll_enable_interrupt(rmt_contex.hal.regs, RMT_LL_EVENT_RX_DONE(RMT_DECODE_RX_CHANNEL(channel)), true);
320
321 #if SOC_RMT_SUPPORT_RX_PINGPONG
322 const uint32_t item_block_len = rmt_ll_rx_get_mem_blocks(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel)) * RMT_MEM_ITEM_NUM;
323 p_rmt_obj[channel]->rx_item_start_idx = 0;
324 p_rmt_obj[channel]->rx_item_len = 0;
325 rmt_set_rx_thr_intr_en(channel, true, item_block_len / 2);
326 #endif
327
328 rmt_ll_rx_enable(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), true);
329 RMT_EXIT_CRITICAL();
330 return ESP_OK;
331 }
332
rmt_rx_stop(rmt_channel_t channel)333 esp_err_t rmt_rx_stop(rmt_channel_t channel)
334 {
335 ESP_RETURN_ON_FALSE(RMT_IS_RX_CHANNEL(channel) && channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
336 RMT_ENTER_CRITICAL();
337 rmt_ll_enable_interrupt(rmt_contex.hal.regs, RMT_LL_EVENT_RX_DONE(RMT_DECODE_RX_CHANNEL(channel)), false);
338 rmt_ll_rx_enable(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), false);
339 rmt_ll_rx_reset_pointer(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel));
340 #if SOC_RMT_SUPPORT_RX_PINGPONG
341 rmt_ll_enable_interrupt(rmt_contex.hal.regs, RMT_LL_EVENT_RX_THRES(RMT_DECODE_RX_CHANNEL(channel)), false);
342 #endif
343 RMT_EXIT_CRITICAL();
344 return ESP_OK;
345 }
346
rmt_tx_memory_reset(rmt_channel_t channel)347 esp_err_t rmt_tx_memory_reset(rmt_channel_t channel)
348 {
349 ESP_RETURN_ON_FALSE(RMT_IS_TX_CHANNEL(channel), ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
350 RMT_ENTER_CRITICAL();
351 rmt_ll_tx_reset_pointer(rmt_contex.hal.regs, channel);
352 RMT_EXIT_CRITICAL();
353 return ESP_OK;
354 }
355
rmt_rx_memory_reset(rmt_channel_t channel)356 esp_err_t rmt_rx_memory_reset(rmt_channel_t channel)
357 {
358 ESP_RETURN_ON_FALSE(RMT_IS_RX_CHANNEL(channel) && channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
359 RMT_ENTER_CRITICAL();
360 rmt_ll_rx_reset_pointer(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel));
361 RMT_EXIT_CRITICAL();
362 return ESP_OK;
363 }
364
rmt_set_memory_owner(rmt_channel_t channel,rmt_mem_owner_t owner)365 esp_err_t rmt_set_memory_owner(rmt_channel_t channel, rmt_mem_owner_t owner)
366 {
367 ESP_RETURN_ON_FALSE(RMT_IS_RX_CHANNEL(channel) && channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
368 ESP_RETURN_ON_FALSE(owner < RMT_MEM_OWNER_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_MEM_OWNER_ERROR_STR);
369 RMT_ENTER_CRITICAL();
370 rmt_ll_rx_set_mem_owner(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), owner);
371 RMT_EXIT_CRITICAL();
372 return ESP_OK;
373 }
374
rmt_get_memory_owner(rmt_channel_t channel,rmt_mem_owner_t * owner)375 esp_err_t rmt_get_memory_owner(rmt_channel_t channel, rmt_mem_owner_t *owner)
376 {
377 ESP_RETURN_ON_FALSE(RMT_IS_RX_CHANNEL(channel) && channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
378 ESP_RETURN_ON_FALSE(owner, ESP_ERR_INVALID_ARG, TAG, RMT_MEM_OWNER_ERROR_STR);
379 RMT_ENTER_CRITICAL();
380 *owner = (rmt_mem_owner_t)rmt_ll_rx_get_mem_owner(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel));
381 RMT_EXIT_CRITICAL();
382 return ESP_OK;
383 }
384
rmt_set_tx_loop_mode(rmt_channel_t channel,bool loop_en)385 esp_err_t rmt_set_tx_loop_mode(rmt_channel_t channel, bool loop_en)
386 {
387 ESP_RETURN_ON_FALSE(RMT_IS_TX_CHANNEL(channel), ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
388 RMT_ENTER_CRITICAL();
389 rmt_ll_tx_enable_loop(rmt_contex.hal.regs, channel, loop_en);
390 RMT_EXIT_CRITICAL();
391 return ESP_OK;
392 }
393
rmt_get_tx_loop_mode(rmt_channel_t channel,bool * loop_en)394 esp_err_t rmt_get_tx_loop_mode(rmt_channel_t channel, bool *loop_en)
395 {
396 ESP_RETURN_ON_FALSE(RMT_IS_TX_CHANNEL(channel), ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
397 RMT_ENTER_CRITICAL();
398 *loop_en = rmt_ll_tx_is_loop_enabled(rmt_contex.hal.regs, channel);
399 RMT_EXIT_CRITICAL();
400 return ESP_OK;
401 }
402
rmt_set_rx_filter(rmt_channel_t channel,bool rx_filter_en,uint8_t thresh)403 esp_err_t rmt_set_rx_filter(rmt_channel_t channel, bool rx_filter_en, uint8_t thresh)
404 {
405 ESP_RETURN_ON_FALSE(RMT_IS_RX_CHANNEL(channel) && channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
406 RMT_ENTER_CRITICAL();
407 rmt_ll_rx_enable_filter(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), rx_filter_en);
408 rmt_ll_rx_set_filter_thres(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), thresh);
409 RMT_EXIT_CRITICAL();
410 return ESP_OK;
411 }
412
rmt_set_source_clk(rmt_channel_t channel,rmt_source_clk_t base_clk)413 esp_err_t rmt_set_source_clk(rmt_channel_t channel, rmt_source_clk_t base_clk)
414 {
415 ESP_RETURN_ON_FALSE(channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
416 RMT_ENTER_CRITICAL();
417 // `rmt_clock_source_t` and `rmt_source_clk_t` are binary compatible, as the underlying enum entries come from the same `soc_module_clk_t`
418 rmt_ll_set_group_clock_src(rmt_contex.hal.regs, channel, (rmt_clock_source_t)base_clk, 1, 0, 0);
419 RMT_EXIT_CRITICAL();
420 return ESP_OK;
421 }
422
rmt_get_source_clk(rmt_channel_t channel,rmt_source_clk_t * src_clk)423 esp_err_t rmt_get_source_clk(rmt_channel_t channel, rmt_source_clk_t *src_clk)
424 {
425 ESP_RETURN_ON_FALSE(channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
426 RMT_ENTER_CRITICAL();
427 // `rmt_clock_source_t` and `rmt_source_clk_t` are binary compatible, as the underlying enum entries come from the same `soc_module_clk_t`
428 *src_clk = (rmt_source_clk_t)rmt_ll_get_group_clock_src(rmt_contex.hal.regs, channel);
429 RMT_EXIT_CRITICAL();
430 return ESP_OK;
431 }
432
rmt_set_idle_level(rmt_channel_t channel,bool idle_out_en,rmt_idle_level_t level)433 esp_err_t rmt_set_idle_level(rmt_channel_t channel, bool idle_out_en, rmt_idle_level_t level)
434 {
435 ESP_RETURN_ON_FALSE(channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
436 ESP_RETURN_ON_FALSE(level < RMT_IDLE_LEVEL_MAX, ESP_ERR_INVALID_ARG, TAG, "RMT IDLE LEVEL ERR");
437 RMT_ENTER_CRITICAL();
438 rmt_ll_tx_fix_idle_level(rmt_contex.hal.regs, channel, level, idle_out_en);
439 RMT_EXIT_CRITICAL();
440 return ESP_OK;
441 }
442
rmt_get_idle_level(rmt_channel_t channel,bool * idle_out_en,rmt_idle_level_t * level)443 esp_err_t rmt_get_idle_level(rmt_channel_t channel, bool *idle_out_en, rmt_idle_level_t *level)
444 {
445 ESP_RETURN_ON_FALSE(channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
446 RMT_ENTER_CRITICAL();
447 *idle_out_en = rmt_ll_tx_is_idle_enabled(rmt_contex.hal.regs, channel);
448 *level = rmt_ll_tx_get_idle_level(rmt_contex.hal.regs, channel);
449 RMT_EXIT_CRITICAL();
450 return ESP_OK;
451 }
452
rmt_get_status(rmt_channel_t channel,uint32_t * status)453 esp_err_t rmt_get_status(rmt_channel_t channel, uint32_t *status)
454 {
455 ESP_RETURN_ON_FALSE(channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
456 RMT_ENTER_CRITICAL();
457 if (RMT_IS_RX_CHANNEL(channel)) {
458 *status = rmt_ll_rx_get_status_word(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel));
459 } else {
460 *status = rmt_ll_tx_get_status_word(rmt_contex.hal.regs, channel);
461 }
462 RMT_EXIT_CRITICAL();
463 return ESP_OK;
464 }
465
rmt_set_rx_intr_en(rmt_channel_t channel,bool en)466 esp_err_t rmt_set_rx_intr_en(rmt_channel_t channel, bool en)
467 {
468 ESP_RETURN_ON_FALSE(RMT_IS_RX_CHANNEL(channel) && channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
469 RMT_ENTER_CRITICAL();
470 rmt_ll_enable_interrupt(rmt_contex.hal.regs, RMT_LL_EVENT_RX_DONE(RMT_DECODE_RX_CHANNEL(channel)), en);
471 RMT_EXIT_CRITICAL();
472 return ESP_OK;
473 }
474
rmt_set_err_intr_en(rmt_channel_t channel,bool en)475 esp_err_t rmt_set_err_intr_en(rmt_channel_t channel, bool en)
476 {
477 ESP_RETURN_ON_FALSE(channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
478 RMT_ENTER_CRITICAL();
479 if (RMT_IS_RX_CHANNEL(channel)) {
480 rmt_ll_enable_interrupt(rmt_contex.hal.regs, RMT_LL_EVENT_RX_ERROR(RMT_DECODE_RX_CHANNEL(channel)), en);
481 } else {
482 rmt_ll_enable_interrupt(rmt_contex.hal.regs, RMT_LL_EVENT_TX_ERROR(channel), en);
483 }
484 RMT_EXIT_CRITICAL();
485 return ESP_OK;
486 }
487
rmt_set_tx_intr_en(rmt_channel_t channel,bool en)488 esp_err_t rmt_set_tx_intr_en(rmt_channel_t channel, bool en)
489 {
490 ESP_RETURN_ON_FALSE(RMT_IS_TX_CHANNEL(channel), ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
491 RMT_ENTER_CRITICAL();
492 rmt_ll_enable_interrupt(rmt_contex.hal.regs, RMT_LL_EVENT_TX_DONE(channel), en);
493 RMT_EXIT_CRITICAL();
494 return ESP_OK;
495 }
496
rmt_set_tx_thr_intr_en(rmt_channel_t channel,bool en,uint16_t evt_thresh)497 esp_err_t rmt_set_tx_thr_intr_en(rmt_channel_t channel, bool en, uint16_t evt_thresh)
498 {
499 ESP_RETURN_ON_FALSE(RMT_IS_TX_CHANNEL(channel), ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
500 if (en) {
501 uint32_t item_block_len = rmt_ll_tx_get_mem_blocks(rmt_contex.hal.regs, channel) * RMT_MEM_ITEM_NUM;
502 ESP_RETURN_ON_FALSE(evt_thresh <= item_block_len, ESP_ERR_INVALID_ARG, TAG, "RMT EVT THRESH ERR");
503 RMT_ENTER_CRITICAL();
504 rmt_ll_tx_set_limit(rmt_contex.hal.regs, channel, evt_thresh);
505 rmt_ll_enable_interrupt(rmt_contex.hal.regs, RMT_LL_EVENT_TX_THRES(channel), true);
506 RMT_EXIT_CRITICAL();
507 } else {
508 RMT_ENTER_CRITICAL();
509 rmt_ll_enable_interrupt(rmt_contex.hal.regs, RMT_LL_EVENT_TX_THRES(channel), false);
510 RMT_EXIT_CRITICAL();
511 }
512 return ESP_OK;
513 }
514
rmt_set_gpio(rmt_channel_t channel,rmt_mode_t mode,gpio_num_t gpio_num,bool invert_signal)515 esp_err_t rmt_set_gpio(rmt_channel_t channel, rmt_mode_t mode, gpio_num_t gpio_num, bool invert_signal)
516 {
517 ESP_RETURN_ON_FALSE(channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
518 ESP_RETURN_ON_FALSE(mode < RMT_MODE_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_MODE_ERROR_STR);
519 ESP_RETURN_ON_FALSE(((GPIO_IS_VALID_GPIO(gpio_num) && (mode == RMT_MODE_RX)) ||
520 (GPIO_IS_VALID_OUTPUT_GPIO(gpio_num) && (mode == RMT_MODE_TX))), ESP_ERR_INVALID_ARG, TAG, RMT_GPIO_ERROR_STR);
521
522 gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_num], PIN_FUNC_GPIO);
523 if (mode == RMT_MODE_TX) {
524 ESP_RETURN_ON_FALSE(RMT_IS_TX_CHANNEL(channel), ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
525 gpio_set_direction(gpio_num, GPIO_MODE_OUTPUT);
526 esp_rom_gpio_connect_out_signal(gpio_num, rmt_periph_signals.groups[0].channels[channel].tx_sig, invert_signal, 0);
527 } else {
528 ESP_RETURN_ON_FALSE(RMT_IS_RX_CHANNEL(channel), ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
529 gpio_set_direction(gpio_num, GPIO_MODE_INPUT);
530 esp_rom_gpio_connect_in_signal(gpio_num, rmt_periph_signals.groups[0].channels[channel].rx_sig, invert_signal);
531 }
532 return ESP_OK;
533 }
534
rmt_is_channel_number_valid(rmt_channel_t channel,uint8_t mode)535 static bool rmt_is_channel_number_valid(rmt_channel_t channel, uint8_t mode)
536 {
537 // RX mode
538 if (mode == RMT_MODE_RX) {
539 return RMT_IS_RX_CHANNEL(channel) && (channel < RMT_CHANNEL_MAX);
540 }
541 // TX mode
542 return (channel >= 0) && RMT_IS_TX_CHANNEL(channel);
543 }
544
rmt_internal_config(rmt_dev_t * dev,const rmt_config_t * rmt_param)545 static esp_err_t rmt_internal_config(rmt_dev_t *dev, const rmt_config_t *rmt_param)
546 {
547 uint8_t mode = rmt_param->rmt_mode;
548 uint8_t channel = rmt_param->channel;
549 uint8_t gpio_num = rmt_param->gpio_num;
550 uint8_t mem_cnt = rmt_param->mem_block_num;
551 uint8_t clk_div = rmt_param->clk_div;
552 uint32_t carrier_freq_hz = rmt_param->tx_config.carrier_freq_hz;
553 bool carrier_en = rmt_param->tx_config.carrier_en;
554 uint32_t rmt_source_clk_hz;
555
556 ESP_RETURN_ON_FALSE(rmt_is_channel_number_valid(channel, mode), ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
557 ESP_RETURN_ON_FALSE(mem_cnt + channel <= SOC_RMT_CHANNELS_PER_GROUP && mem_cnt > 0, ESP_ERR_INVALID_ARG, TAG, RMT_MEM_CNT_ERROR_STR);
558 ESP_RETURN_ON_FALSE(clk_div > 0, ESP_ERR_INVALID_ARG, TAG, RMT_CLK_DIV_ERROR_STR);
559
560 if (mode == RMT_MODE_TX) {
561 ESP_RETURN_ON_FALSE(!carrier_en || carrier_freq_hz > 0, ESP_ERR_INVALID_ARG, TAG, "RMT carrier frequency can't be zero");
562 }
563
564 RMT_ENTER_CRITICAL();
565 rmt_ll_enable_mem_access_nonfifo(dev, true);
566
567 if (rmt_param->flags & RMT_CHANNEL_FLAGS_AWARE_DFS) {
568 #if SOC_RMT_SUPPORT_XTAL
569 // clock src: XTAL_CLK
570 esp_clk_tree_src_get_freq_hz((soc_module_clk_t)RMT_BASECLK_XTAL, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &rmt_source_clk_hz);
571 rmt_ll_set_group_clock_src(dev, channel, (rmt_clock_source_t)RMT_BASECLK_XTAL, 1, 0, 0);
572 #elif SOC_RMT_SUPPORT_REF_TICK
573 // clock src: REF_CLK
574 esp_clk_tree_src_get_freq_hz((soc_module_clk_t)RMT_BASECLK_REF, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &rmt_source_clk_hz);
575 rmt_ll_set_group_clock_src(dev, channel, (rmt_clock_source_t)RMT_BASECLK_REF, 1, 0, 0);
576 #else
577 #error "No clock source is aware of DFS"
578 #endif
579 } else {
580 // fallback to use default clock source
581 esp_clk_tree_src_get_freq_hz((soc_module_clk_t)RMT_BASECLK_DEFAULT, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &rmt_source_clk_hz);
582 rmt_ll_set_group_clock_src(dev, channel, (rmt_clock_source_t)RMT_BASECLK_DEFAULT, 1, 0, 0);
583 }
584 RMT_EXIT_CRITICAL();
585
586 #if SOC_RMT_CHANNEL_CLK_INDEPENDENT
587 s_rmt_source_clock_hz[channel] = rmt_source_clk_hz;
588 #else
589 if (s_rmt_source_clock_hz && rmt_source_clk_hz != s_rmt_source_clock_hz) {
590 ESP_LOGW(TAG, "RMT clock source has been configured to %"PRIu32" by other channel, now reconfigure it to %"PRIu32, s_rmt_source_clock_hz, rmt_source_clk_hz);
591 }
592 s_rmt_source_clock_hz = rmt_source_clk_hz;
593 #endif
594 ESP_LOGD(TAG, "rmt_source_clk_hz: %"PRIu32, rmt_source_clk_hz);
595
596 if (mode == RMT_MODE_TX) {
597 uint16_t carrier_duty_percent = rmt_param->tx_config.carrier_duty_percent;
598 uint8_t carrier_level = rmt_param->tx_config.carrier_level;
599 uint8_t idle_level = rmt_param->tx_config.idle_level;
600
601 RMT_ENTER_CRITICAL();
602 rmt_ll_tx_set_channel_clock_div(dev, channel, clk_div);
603 rmt_ll_tx_set_mem_blocks(dev, channel, mem_cnt);
604 rmt_ll_tx_reset_pointer(dev, channel);
605 rmt_ll_tx_enable_loop(dev, channel, rmt_param->tx_config.loop_en);
606 #if SOC_RMT_SUPPORT_TX_LOOP_COUNT
607 if (rmt_param->tx_config.loop_en) {
608 rmt_ll_tx_set_loop_count(dev, channel, rmt_param->tx_config.loop_count);
609 }
610 #endif
611 /* always enable tx ping-pong */
612 rmt_ll_tx_enable_wrap(dev, channel, true);
613 /*Set idle level */
614 rmt_ll_tx_fix_idle_level(dev, channel, idle_level, rmt_param->tx_config.idle_output_en);
615 /*Set carrier*/
616 rmt_ll_tx_enable_carrier_modulation(dev, channel, carrier_en);
617 if (carrier_en) {
618 uint32_t duty_div, duty_h, duty_l;
619 duty_div = rmt_source_clk_hz / carrier_freq_hz;
620 duty_h = duty_div * carrier_duty_percent / 100;
621 duty_l = duty_div - duty_h;
622 rmt_ll_tx_set_carrier_level(dev, channel, carrier_level);
623 rmt_ll_tx_set_carrier_high_low_ticks(dev, channel, duty_h, duty_l);
624 } else {
625 rmt_ll_tx_set_carrier_level(dev, channel, 0);
626 }
627 RMT_EXIT_CRITICAL();
628
629 ESP_LOGD(TAG, "Rmt Tx Channel %u|Gpio %u|Sclk_Hz %"PRIu32"|Div %u|Carrier_Hz %"PRIu32"|Duty %u",
630 channel, gpio_num, rmt_source_clk_hz, clk_div, carrier_freq_hz, carrier_duty_percent);
631 } else if (RMT_MODE_RX == mode) {
632 uint8_t filter_cnt = rmt_param->rx_config.filter_ticks_thresh;
633 uint16_t threshold = rmt_param->rx_config.idle_threshold;
634
635 RMT_ENTER_CRITICAL();
636 rmt_ll_rx_set_channel_clock_div(dev, RMT_DECODE_RX_CHANNEL(channel), clk_div);
637 rmt_ll_rx_set_mem_blocks(dev, RMT_DECODE_RX_CHANNEL(channel), mem_cnt);
638 rmt_ll_rx_reset_pointer(dev, RMT_DECODE_RX_CHANNEL(channel));
639 rmt_ll_rx_set_mem_owner(dev, RMT_DECODE_RX_CHANNEL(channel), RMT_LL_MEM_OWNER_HW);
640 /*Set idle threshold*/
641 rmt_ll_rx_set_idle_thres(dev, RMT_DECODE_RX_CHANNEL(channel), threshold);
642 /* Set RX filter */
643 rmt_ll_rx_set_filter_thres(dev, RMT_DECODE_RX_CHANNEL(channel), filter_cnt);
644 rmt_ll_rx_enable_filter(dev, RMT_DECODE_RX_CHANNEL(channel), rmt_param->rx_config.filter_en);
645
646 #if SOC_RMT_SUPPORT_RX_PINGPONG
647 /* always enable rx ping-pong */
648 rmt_ll_rx_enable_wrap(dev, RMT_DECODE_RX_CHANNEL(channel), true);
649 #endif
650
651 #if SOC_RMT_SUPPORT_RX_DEMODULATION
652 rmt_ll_rx_enable_carrier_demodulation(dev, RMT_DECODE_RX_CHANNEL(channel), rmt_param->rx_config.rm_carrier);
653 if (rmt_param->rx_config.rm_carrier) {
654 uint32_t duty_total = rmt_source_clk_hz / rmt_ll_rx_get_channel_clock_div(dev, RMT_DECODE_RX_CHANNEL(channel)) / rmt_param->rx_config.carrier_freq_hz;
655 uint32_t duty_high = duty_total * rmt_param->rx_config.carrier_duty_percent / 100;
656 // there could be residual in timing the carrier pulse, so double enlarge the theoretical value
657 rmt_ll_rx_set_carrier_high_low_ticks(dev, RMT_DECODE_RX_CHANNEL(channel), duty_high * 2, (duty_total - duty_high) * 2);
658 rmt_ll_rx_set_carrier_level(dev, RMT_DECODE_RX_CHANNEL(channel), rmt_param->rx_config.carrier_level);
659 }
660 #endif
661 RMT_EXIT_CRITICAL();
662
663 ESP_LOGD(TAG, "Rmt Rx Channel %u|Gpio %u|Sclk_Hz %"PRIu32"|Div %u|Thresold %u|Filter %u",
664 channel, gpio_num, rmt_source_clk_hz, clk_div, threshold, filter_cnt);
665 }
666
667 return ESP_OK;
668 }
669
rmt_config(const rmt_config_t * rmt_param)670 esp_err_t rmt_config(const rmt_config_t *rmt_param)
671 {
672 rmt_module_enable();
673
674 ESP_RETURN_ON_ERROR(rmt_set_gpio(rmt_param->channel, rmt_param->rmt_mode, rmt_param->gpio_num, rmt_param->flags & RMT_CHANNEL_FLAGS_INVERT_SIG), TAG, "set gpio for RMT driver failed");
675 ESP_RETURN_ON_ERROR(rmt_internal_config(&RMT, rmt_param), TAG, "initialize RMT driver failed");
676
677 return ESP_OK;
678 }
679
rmt_fill_memory(rmt_channel_t channel,const rmt_item32_t * item,uint16_t item_num,uint16_t mem_offset)680 static void IRAM_ATTR rmt_fill_memory(rmt_channel_t channel, const rmt_item32_t *item,
681 uint16_t item_num, uint16_t mem_offset)
682 {
683 uint32_t *from = (uint32_t *)item;
684 volatile uint32_t *to = (volatile uint32_t *)&RMTMEM.chan[channel].data32[0].val;
685 to += mem_offset;
686 while (item_num--) {
687 *to++ = *from++;
688 }
689 }
690
rmt_fill_tx_items(rmt_channel_t channel,const rmt_item32_t * item,uint16_t item_num,uint16_t mem_offset)691 esp_err_t rmt_fill_tx_items(rmt_channel_t channel, const rmt_item32_t *item, uint16_t item_num, uint16_t mem_offset)
692 {
693 ESP_RETURN_ON_FALSE(RMT_IS_TX_CHANNEL(channel), (0), TAG, RMT_CHANNEL_ERROR_STR);
694 ESP_RETURN_ON_FALSE(item, ESP_ERR_INVALID_ARG, TAG, RMT_ADDR_ERROR_STR);
695 ESP_RETURN_ON_FALSE(item_num > 0, ESP_ERR_INVALID_ARG, TAG, RMT_DRIVER_LENGTH_ERROR_STR);
696
697 uint8_t mem_cnt = rmt_ll_tx_get_mem_blocks(rmt_contex.hal.regs, channel);
698 ESP_RETURN_ON_FALSE(mem_cnt * RMT_MEM_ITEM_NUM >= item_num, ESP_ERR_INVALID_ARG, TAG, RMT_WR_MEM_OVF_ERROR_STR);
699 rmt_fill_memory(channel, item, item_num, mem_offset);
700 return ESP_OK;
701 }
702
rmt_isr_register(void (* fn)(void *),void * arg,int intr_alloc_flags,rmt_isr_handle_t * handle)703 esp_err_t rmt_isr_register(void (*fn)(void *), void *arg, int intr_alloc_flags, rmt_isr_handle_t *handle)
704 {
705 ESP_RETURN_ON_FALSE(fn, ESP_ERR_INVALID_ARG, TAG, RMT_ADDR_ERROR_STR);
706 ESP_RETURN_ON_FALSE(rmt_contex.rmt_driver_channels == 0, ESP_FAIL, TAG, "RMT driver installed, can not install generic ISR handler");
707
708 return esp_intr_alloc(rmt_periph_signals.groups[0].irq, intr_alloc_flags, fn, arg, handle);
709 }
710
rmt_isr_deregister(rmt_isr_handle_t handle)711 esp_err_t rmt_isr_deregister(rmt_isr_handle_t handle)
712 {
713 return esp_intr_free(handle);
714 }
715
rmt_driver_isr_default(void * arg)716 static void IRAM_ATTR rmt_driver_isr_default(void *arg)
717 {
718 uint32_t status = 0;
719 rmt_item32_t *addr = NULL;
720 uint8_t channel = 0;
721 rmt_hal_context_t *hal = (rmt_hal_context_t *)arg;
722 portBASE_TYPE HPTaskAwoken = pdFALSE;
723
724 // Tx end interrupt
725 status = rmt_ll_get_tx_end_interrupt_status(hal->regs);
726 while (status) {
727 channel = __builtin_ffs(status) - 1;
728 status &= ~(1 << channel);
729 rmt_obj_t *p_rmt = p_rmt_obj[channel];
730 if (p_rmt) {
731 xSemaphoreGiveFromISR(p_rmt->tx_sem, &HPTaskAwoken);
732 rmt_ll_tx_reset_pointer(rmt_contex.hal.regs, channel);
733 p_rmt->tx_data = NULL;
734 p_rmt->tx_len_rem = 0;
735 p_rmt->tx_offset = 0;
736 p_rmt->tx_sub_len = 0;
737 p_rmt->sample_cur = NULL;
738 p_rmt->translator = false;
739 if (rmt_contex.rmt_tx_end_callback.function) {
740 rmt_contex.rmt_tx_end_callback.function(channel, rmt_contex.rmt_tx_end_callback.arg);
741 }
742 }
743 rmt_ll_clear_interrupt_status(hal->regs, RMT_LL_EVENT_TX_DONE(channel));
744 }
745
746 // Tx thres interrupt
747 status = rmt_ll_get_tx_thres_interrupt_status(hal->regs);
748 while (status) {
749 channel = __builtin_ffs(status) - 1;
750 status &= ~(1 << channel);
751 rmt_obj_t *p_rmt = p_rmt_obj[channel];
752 if (p_rmt) {
753 if (p_rmt->translator) {
754 if (p_rmt->sample_size_remain > 0) {
755 size_t translated_size = 0;
756 p_rmt->sample_to_rmt((void *)p_rmt->sample_cur,
757 p_rmt->tx_buf,
758 p_rmt->sample_size_remain,
759 p_rmt->tx_sub_len,
760 &translated_size,
761 &p_rmt->tx_len_rem);
762 p_rmt->sample_size_remain -= translated_size;
763 p_rmt->sample_cur += translated_size;
764 p_rmt->tx_data = p_rmt->tx_buf;
765 } else {
766 p_rmt->sample_cur = NULL;
767 p_rmt->translator = false;
768 }
769 }
770 const rmt_item32_t *pdata = p_rmt->tx_data;
771 size_t len_rem = p_rmt->tx_len_rem;
772 rmt_idle_level_t idle_level = rmt_ll_tx_get_idle_level(hal->regs, channel);
773 rmt_item32_t stop_data = (rmt_item32_t) {
774 .level0 = idle_level,
775 .duration0 = 0,
776 };
777 if (len_rem >= p_rmt->tx_sub_len) {
778 rmt_fill_memory(channel, pdata, p_rmt->tx_sub_len, p_rmt->tx_offset);
779 p_rmt->tx_data += p_rmt->tx_sub_len;
780 p_rmt->tx_len_rem -= p_rmt->tx_sub_len;
781 } else if (len_rem == 0) {
782 rmt_fill_memory(channel, &stop_data, 1, p_rmt->tx_offset);
783 } else {
784 rmt_fill_memory(channel, pdata, len_rem, p_rmt->tx_offset);
785 rmt_fill_memory(channel, &stop_data, 1, p_rmt->tx_offset + len_rem);
786 p_rmt->tx_data += len_rem;
787 p_rmt->tx_len_rem -= len_rem;
788 }
789 if (p_rmt->tx_offset == 0) {
790 p_rmt->tx_offset = p_rmt->tx_sub_len;
791 } else {
792 p_rmt->tx_offset = 0;
793 }
794 }
795 rmt_ll_clear_interrupt_status(hal->regs, RMT_LL_EVENT_TX_THRES(channel));
796 }
797
798 // Rx end interrupt
799 status = rmt_ll_get_rx_end_interrupt_status(hal->regs);
800 while (status) {
801 channel = __builtin_ffs(status) - 1;
802 status &= ~(1 << channel);
803 rmt_obj_t *p_rmt = p_rmt_obj[RMT_ENCODE_RX_CHANNEL(channel)];
804 if (p_rmt) {
805 rmt_ll_rx_enable(rmt_contex.hal.regs, channel, false);
806 int item_len = rmt_ll_rx_get_memory_writer_offset(rmt_contex.hal.regs, channel);
807 rmt_ll_rx_set_mem_owner(rmt_contex.hal.regs, channel, RMT_LL_MEM_OWNER_SW);
808 if (p_rmt->rx_buf) {
809 addr = (rmt_item32_t *)RMTMEM.chan[RMT_ENCODE_RX_CHANNEL(channel)].data32;
810 #if SOC_RMT_SUPPORT_RX_PINGPONG
811 if (item_len > p_rmt->rx_item_start_idx) {
812 item_len = item_len - p_rmt->rx_item_start_idx;
813 }
814 memcpy((void *)(p_rmt->rx_item_buf + p_rmt->rx_item_len), (void *)(addr + p_rmt->rx_item_start_idx), item_len * 4);
815 p_rmt->rx_item_len += item_len;
816 BaseType_t res = xRingbufferSendFromISR(p_rmt->rx_buf, (void *)(p_rmt->rx_item_buf), p_rmt->rx_item_len * 4, &HPTaskAwoken);
817 #else
818 BaseType_t res = xRingbufferSendFromISR(p_rmt->rx_buf, (void *)addr, item_len * 4, &HPTaskAwoken);
819 #endif
820 if (res == pdFALSE) {
821 ESP_DRAM_LOGE(TAG, "RMT RX BUFFER FULL");
822 }
823 } else {
824 ESP_DRAM_LOGE(TAG, "RMT RX BUFFER ERROR");
825 }
826
827 #if SOC_RMT_SUPPORT_RX_PINGPONG
828 p_rmt->rx_item_start_idx = 0;
829 p_rmt->rx_item_len = 0;
830 memset((void *)p_rmt->rx_item_buf, 0, p_rmt->rx_item_buf_size);
831 #endif
832 rmt_ll_rx_reset_pointer(rmt_contex.hal.regs, channel);
833 rmt_ll_rx_set_mem_owner(rmt_contex.hal.regs, channel, RMT_LL_MEM_OWNER_HW);
834 rmt_ll_rx_enable(rmt_contex.hal.regs, channel, true);
835 }
836 rmt_ll_clear_interrupt_status(hal->regs, RMT_LL_EVENT_RX_DONE(channel));
837 }
838
839 #if SOC_RMT_SUPPORT_RX_PINGPONG
840 // Rx thres interrupt
841 status = rmt_ll_get_rx_thres_interrupt_status(hal->regs);
842 while (status) {
843 channel = __builtin_ffs(status) - 1;
844 status &= ~(1 << channel);
845 rmt_obj_t *p_rmt = p_rmt_obj[RMT_ENCODE_RX_CHANNEL(channel)];
846 int mem_item_size = rmt_ll_rx_get_mem_blocks(rmt_contex.hal.regs, channel) * RMT_MEM_ITEM_NUM;
847 int rx_thres_lim = rmt_ll_rx_get_limit(rmt_contex.hal.regs, channel);
848 int item_len = (p_rmt->rx_item_start_idx == 0) ? rx_thres_lim : (mem_item_size - rx_thres_lim);
849 if ((p_rmt->rx_item_len + item_len) < (p_rmt->rx_item_buf_size / 4)) {
850 rmt_ll_rx_set_mem_owner(rmt_contex.hal.regs, channel, RMT_LL_MEM_OWNER_SW);
851 memcpy((void *)(p_rmt->rx_item_buf + p_rmt->rx_item_len), (void *)(RMTMEM.chan[RMT_ENCODE_RX_CHANNEL(channel)].data32 + p_rmt->rx_item_start_idx), item_len * 4);
852 rmt_ll_rx_set_mem_owner(rmt_contex.hal.regs, channel, RMT_LL_MEM_OWNER_HW);
853 p_rmt->rx_item_len += item_len;
854 p_rmt->rx_item_start_idx += item_len;
855 if (p_rmt->rx_item_start_idx >= mem_item_size) {
856 p_rmt->rx_item_start_idx = 0;
857 }
858 } else {
859 ESP_DRAM_LOGE(TAG, "---RX buffer too small: %d", sizeof(p_rmt->rx_item_buf));
860 }
861 rmt_ll_clear_interrupt_status(hal->regs, RMT_LL_EVENT_RX_THRES(channel));
862 }
863 #endif
864
865 #if SOC_RMT_SUPPORT_TX_LOOP_COUNT
866 // loop count interrupt
867 status = rmt_ll_get_tx_loop_interrupt_status(hal->regs);
868 while (status) {
869 channel = __builtin_ffs(status) - 1;
870 status &= ~(1 << channel);
871 rmt_obj_t *p_rmt = p_rmt_obj[channel];
872 if (p_rmt) {
873 if (p_rmt->loop_autostop) {
874 #ifndef SOC_RMT_SUPPORT_TX_LOOP_AUTO_STOP
875 // hardware doesn't support automatically stop output so driver should stop output here (possibility already overshotted several us)
876 rmt_ll_tx_stop(rmt_contex.hal.regs, channel);
877 rmt_ll_tx_reset_pointer(rmt_contex.hal.regs, channel);
878 #endif
879 }
880 xSemaphoreGiveFromISR(p_rmt->tx_sem, &HPTaskAwoken);
881 if (rmt_contex.rmt_tx_end_callback.function) {
882 rmt_contex.rmt_tx_end_callback.function(channel, rmt_contex.rmt_tx_end_callback.arg);
883 }
884 }
885 rmt_ll_clear_interrupt_status(hal->regs, RMT_LL_EVENT_TX_LOOP_END(channel));
886 }
887 #endif
888
889 // RX Err interrupt
890 status = rmt_ll_get_rx_err_interrupt_status(hal->regs);
891 while (status) {
892 channel = __builtin_ffs(status) - 1;
893 status &= ~(1 << channel);
894 rmt_obj_t *p_rmt = p_rmt_obj[RMT_ENCODE_RX_CHANNEL(channel)];
895 if (p_rmt) {
896 // Reset the receiver's write/read addresses to prevent endless err interrupts.
897 rmt_ll_rx_reset_pointer(rmt_contex.hal.regs, channel);
898 ESP_DRAM_LOGD(TAG, "RMT RX channel %d error", channel);
899 ESP_DRAM_LOGD(TAG, "status: 0x%08x", rmt_ll_rx_get_status_word(rmt_contex.hal.regs, channel));
900 }
901 rmt_ll_clear_interrupt_status(hal->regs, RMT_LL_EVENT_RX_ERROR(channel));
902 }
903
904 // TX Err interrupt
905 status = rmt_ll_get_tx_err_interrupt_status(hal->regs);
906 while (status) {
907 channel = __builtin_ffs(status) - 1;
908 status &= ~(1 << channel);
909 rmt_obj_t *p_rmt = p_rmt_obj[channel];
910 if (p_rmt) {
911 // Reset the transmitter's write/read addresses to prevent endless err interrupts.
912 rmt_ll_tx_reset_pointer(rmt_contex.hal.regs, channel);
913 ESP_DRAM_LOGD(TAG, "RMT TX channel %d error", channel);
914 ESP_DRAM_LOGD(TAG, "status: 0x%08x", rmt_ll_tx_get_status_word(rmt_contex.hal.regs, channel));
915 }
916 rmt_ll_clear_interrupt_status(hal->regs, RMT_LL_EVENT_TX_ERROR(channel));
917 }
918
919 if (HPTaskAwoken == pdTRUE) {
920 portYIELD_FROM_ISR();
921 }
922 }
923
rmt_driver_uninstall(rmt_channel_t channel)924 esp_err_t rmt_driver_uninstall(rmt_channel_t channel)
925 {
926 esp_err_t err = ESP_OK;
927 ESP_RETURN_ON_FALSE(channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
928 // we allow to call this uninstall function on the same channel for multiple times
929 if (p_rmt_obj[channel] == NULL) {
930 return ESP_OK;
931 }
932 //Avoid blocking here(when the interrupt is disabled and do not wait tx done).
933 if (p_rmt_obj[channel]->wait_done) {
934 xSemaphoreTake(p_rmt_obj[channel]->tx_sem, portMAX_DELAY);
935 }
936
937 RMT_ENTER_CRITICAL();
938 // check channel's working mode
939 if (p_rmt_obj[channel]->rx_buf) {
940 rmt_ll_enable_interrupt(rmt_contex.hal.regs, RMT_LL_EVENT_RX_MASK(RMT_DECODE_RX_CHANNEL(channel)) | RMT_LL_EVENT_RX_ERROR(RMT_DECODE_RX_CHANNEL(channel)), false);
941 } else {
942 rmt_ll_enable_interrupt(rmt_contex.hal.regs, RMT_LL_EVENT_TX_MASK(channel) | RMT_LL_EVENT_TX_ERROR(channel), false);
943 }
944 RMT_EXIT_CRITICAL();
945
946 _lock_acquire_recursive(&(rmt_contex.rmt_driver_isr_lock));
947 rmt_contex.rmt_driver_channels &= ~BIT(channel);
948 if (rmt_contex.rmt_driver_channels == 0 && rmt_contex.rmt_driver_intr_handle) {
949 rmt_module_disable();
950 // all channels have driver disabled
951 err = rmt_isr_deregister(rmt_contex.rmt_driver_intr_handle);
952 rmt_contex.rmt_driver_intr_handle = NULL;
953 }
954 _lock_release_recursive(&(rmt_contex.rmt_driver_isr_lock));
955
956 if (p_rmt_obj[channel]->tx_sem) {
957 vSemaphoreDelete(p_rmt_obj[channel]->tx_sem);
958 p_rmt_obj[channel]->tx_sem = NULL;
959 }
960 if (p_rmt_obj[channel]->rx_buf) {
961 vRingbufferDelete(p_rmt_obj[channel]->rx_buf);
962 p_rmt_obj[channel]->rx_buf = NULL;
963 }
964 if (p_rmt_obj[channel]->tx_buf) {
965 free(p_rmt_obj[channel]->tx_buf);
966 p_rmt_obj[channel]->tx_buf = NULL;
967 }
968 if (p_rmt_obj[channel]->sample_to_rmt) {
969 p_rmt_obj[channel]->sample_to_rmt = NULL;
970 }
971 #if SOC_RMT_SUPPORT_RX_PINGPONG
972 if (p_rmt_obj[channel]->rx_item_buf) {
973 free(p_rmt_obj[channel]->rx_item_buf);
974 p_rmt_obj[channel]->rx_item_buf = NULL;
975 p_rmt_obj[channel]->rx_item_buf_size = 0;
976 }
977 #endif
978
979 free(p_rmt_obj[channel]);
980 p_rmt_obj[channel] = NULL;
981 return err;
982 }
983
rmt_driver_install(rmt_channel_t channel,size_t rx_buf_size,int intr_alloc_flags)984 esp_err_t rmt_driver_install(rmt_channel_t channel, size_t rx_buf_size, int intr_alloc_flags)
985 {
986 ESP_RETURN_ON_FALSE(channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
987
988 esp_err_t err = ESP_OK;
989
990 if (p_rmt_obj[channel]) {
991 ESP_LOGD(TAG, "RMT driver already installed");
992 return ESP_ERR_INVALID_STATE;
993 }
994
995 #if CONFIG_RINGBUF_PLACE_ISR_FUNCTIONS_INTO_FLASH
996 if (intr_alloc_flags & ESP_INTR_FLAG_IRAM ) {
997 ESP_LOGE(TAG, "ringbuf ISR functions in flash, but used in IRAM interrupt");
998 return ESP_ERR_INVALID_ARG;
999 }
1000 #endif
1001
1002 #if !CONFIG_SPIRAM_USE_MALLOC
1003 p_rmt_obj[channel] = calloc(1, sizeof(rmt_obj_t));
1004 #else
1005 if (!(intr_alloc_flags & ESP_INTR_FLAG_IRAM)) {
1006 p_rmt_obj[channel] = calloc(1, sizeof(rmt_obj_t));
1007 } else {
1008 p_rmt_obj[channel] = heap_caps_calloc(1, sizeof(rmt_obj_t), MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
1009 }
1010 #endif
1011
1012 if (p_rmt_obj[channel] == NULL) {
1013 ESP_LOGE(TAG, "RMT driver malloc error");
1014 return ESP_ERR_NO_MEM;
1015 }
1016
1017 p_rmt_obj[channel]->tx_len_rem = 0;
1018 p_rmt_obj[channel]->tx_data = NULL;
1019 p_rmt_obj[channel]->channel = channel;
1020 p_rmt_obj[channel]->tx_offset = 0;
1021 p_rmt_obj[channel]->tx_sub_len = 0;
1022 p_rmt_obj[channel]->wait_done = false;
1023 p_rmt_obj[channel]->loop_autostop = false;
1024 p_rmt_obj[channel]->translator = false;
1025 p_rmt_obj[channel]->sample_to_rmt = NULL;
1026 if (p_rmt_obj[channel]->tx_sem == NULL) {
1027 #if !CONFIG_SPIRAM_USE_MALLOC
1028 p_rmt_obj[channel]->tx_sem = xSemaphoreCreateBinary();
1029 #else
1030 p_rmt_obj[channel]->intr_alloc_flags = intr_alloc_flags;
1031 if (!(intr_alloc_flags & ESP_INTR_FLAG_IRAM)) {
1032 p_rmt_obj[channel]->tx_sem = xSemaphoreCreateBinary();
1033 } else {
1034 p_rmt_obj[channel]->tx_sem = xSemaphoreCreateBinaryStatic(&p_rmt_obj[channel]->tx_sem_buffer);
1035 }
1036 #endif
1037 xSemaphoreGive(p_rmt_obj[channel]->tx_sem);
1038 }
1039 if (p_rmt_obj[channel]->rx_buf == NULL && rx_buf_size > 0) {
1040 p_rmt_obj[channel]->rx_buf = xRingbufferCreate(rx_buf_size, RINGBUF_TYPE_NOSPLIT);
1041 }
1042
1043 #if SOC_RMT_SUPPORT_RX_PINGPONG
1044 if (p_rmt_obj[channel]->rx_item_buf == NULL && rx_buf_size > 0) {
1045 #if !CONFIG_SPIRAM_USE_MALLOC
1046 p_rmt_obj[channel]->rx_item_buf = calloc(1, rx_buf_size);
1047 #else
1048 if (!(p_rmt_obj[channel]->intr_alloc_flags & ESP_INTR_FLAG_IRAM)) {
1049 p_rmt_obj[channel]->rx_item_buf = calloc(1, rx_buf_size);
1050 } else {
1051 p_rmt_obj[channel]->rx_item_buf = heap_caps_calloc(1, rx_buf_size, MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
1052 }
1053 #endif
1054 if (p_rmt_obj[channel]->rx_item_buf == NULL) {
1055 ESP_LOGE(TAG, "RMT malloc fail");
1056 return ESP_FAIL;
1057 }
1058 p_rmt_obj[channel]->rx_item_buf_size = rx_buf_size;
1059 }
1060 #endif
1061
1062 _lock_acquire_recursive(&(rmt_contex.rmt_driver_isr_lock));
1063
1064 if (rmt_contex.rmt_driver_channels == 0) {
1065 // first RMT channel using driver
1066 err = rmt_isr_register(rmt_driver_isr_default, &rmt_contex.hal, intr_alloc_flags, &(rmt_contex.rmt_driver_intr_handle));
1067 }
1068 if (err == ESP_OK) {
1069 rmt_contex.rmt_driver_channels |= BIT(channel);
1070 }
1071 _lock_release_recursive(&(rmt_contex.rmt_driver_isr_lock));
1072
1073 rmt_module_enable();
1074
1075 if (RMT_IS_RX_CHANNEL(channel)) {
1076 rmt_hal_rx_channel_reset(&rmt_contex.hal, RMT_DECODE_RX_CHANNEL(channel));
1077 } else {
1078 rmt_hal_tx_channel_reset(&rmt_contex.hal, channel);
1079 }
1080
1081 return err;
1082 }
1083
rmt_write_items(rmt_channel_t channel,const rmt_item32_t * rmt_item,int item_num,bool wait_tx_done)1084 esp_err_t rmt_write_items(rmt_channel_t channel, const rmt_item32_t *rmt_item, int item_num, bool wait_tx_done)
1085 {
1086 ESP_RETURN_ON_FALSE(RMT_IS_TX_CHANNEL(channel), ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
1087 ESP_RETURN_ON_FALSE(p_rmt_obj[channel], ESP_FAIL, TAG, RMT_DRIVER_ERROR_STR);
1088 ESP_RETURN_ON_FALSE(rmt_item, ESP_FAIL, TAG, RMT_ADDR_ERROR_STR);
1089 ESP_RETURN_ON_FALSE(item_num > 0, ESP_ERR_INVALID_ARG, TAG, RMT_DRIVER_LENGTH_ERROR_STR);
1090 uint32_t mem_blocks = rmt_ll_tx_get_mem_blocks(rmt_contex.hal.regs, channel);
1091 ESP_RETURN_ON_FALSE(mem_blocks + channel <= SOC_RMT_CHANNELS_PER_GROUP, ESP_ERR_INVALID_STATE, TAG, RMT_MEM_CNT_ERROR_STR);
1092 #if CONFIG_SPIRAM_USE_MALLOC
1093 if (p_rmt_obj[channel]->intr_alloc_flags & ESP_INTR_FLAG_IRAM) {
1094 if (!esp_ptr_internal(rmt_item)) {
1095 ESP_LOGE(TAG, RMT_PSRAM_BUFFER_WARN_STR);
1096 return ESP_ERR_INVALID_ARG;
1097 }
1098 }
1099 #endif
1100 rmt_obj_t *p_rmt = p_rmt_obj[channel];
1101 int item_block_len = mem_blocks * RMT_MEM_ITEM_NUM;
1102 int item_sub_len = mem_blocks * RMT_MEM_ITEM_NUM / 2;
1103 int len_rem = item_num;
1104 xSemaphoreTake(p_rmt->tx_sem, portMAX_DELAY);
1105 // fill the memory block first
1106 if (item_num >= item_block_len) {
1107 rmt_fill_memory(channel, rmt_item, item_block_len, 0);
1108 len_rem -= item_block_len;
1109 rmt_set_tx_loop_mode(channel, false);
1110 rmt_set_tx_thr_intr_en(channel, 1, item_sub_len);
1111 p_rmt->tx_data = rmt_item + item_block_len;
1112 p_rmt->tx_len_rem = len_rem;
1113 p_rmt->tx_offset = 0;
1114 p_rmt->tx_sub_len = item_sub_len;
1115 } else {
1116 rmt_fill_memory(channel, rmt_item, len_rem, 0);
1117 rmt_idle_level_t idle_level = rmt_ll_tx_get_idle_level(rmt_contex.hal.regs, channel);
1118 rmt_item32_t stop_data = (rmt_item32_t) {
1119 .level0 = idle_level,
1120 .duration0 = 0,
1121 };
1122 rmt_fill_memory(channel, &stop_data, 1, len_rem);
1123 p_rmt->tx_len_rem = 0;
1124 }
1125 rmt_tx_start(channel, true);
1126 p_rmt->wait_done = wait_tx_done;
1127 if (wait_tx_done) {
1128 // wait loop done
1129 if (rmt_ll_tx_is_loop_enabled(rmt_contex.hal.regs, channel)) {
1130 #if SOC_RMT_SUPPORT_TX_LOOP_COUNT
1131 xSemaphoreTake(p_rmt->tx_sem, portMAX_DELAY);
1132 xSemaphoreGive(p_rmt->tx_sem);
1133 #endif
1134 } else {
1135 // wait tx end
1136 xSemaphoreTake(p_rmt->tx_sem, portMAX_DELAY);
1137 xSemaphoreGive(p_rmt->tx_sem);
1138 }
1139 }
1140 return ESP_OK;
1141 }
1142
rmt_wait_tx_done(rmt_channel_t channel,TickType_t wait_time)1143 esp_err_t rmt_wait_tx_done(rmt_channel_t channel, TickType_t wait_time)
1144 {
1145 ESP_RETURN_ON_FALSE(RMT_IS_TX_CHANNEL(channel), ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
1146 ESP_RETURN_ON_FALSE(p_rmt_obj[channel], ESP_FAIL, TAG, RMT_DRIVER_ERROR_STR);
1147 if (xSemaphoreTake(p_rmt_obj[channel]->tx_sem, wait_time) == pdTRUE) {
1148 p_rmt_obj[channel]->wait_done = false;
1149 xSemaphoreGive(p_rmt_obj[channel]->tx_sem);
1150 return ESP_OK;
1151 } else {
1152 if (wait_time != 0) {
1153 // Don't emit error message if just polling.
1154 ESP_LOGE(TAG, "Timeout on wait_tx_done");
1155 }
1156 return ESP_ERR_TIMEOUT;
1157 }
1158 }
1159
rmt_get_ringbuf_handle(rmt_channel_t channel,RingbufHandle_t * buf_handle)1160 esp_err_t rmt_get_ringbuf_handle(rmt_channel_t channel, RingbufHandle_t *buf_handle)
1161 {
1162 ESP_RETURN_ON_FALSE(channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
1163 ESP_RETURN_ON_FALSE(p_rmt_obj[channel], ESP_FAIL, TAG, RMT_DRIVER_ERROR_STR);
1164 ESP_RETURN_ON_FALSE(buf_handle, ESP_ERR_INVALID_ARG, TAG, RMT_ADDR_ERROR_STR);
1165 *buf_handle = p_rmt_obj[channel]->rx_buf;
1166 return ESP_OK;
1167 }
1168
rmt_register_tx_end_callback(rmt_tx_end_fn_t function,void * arg)1169 rmt_tx_end_callback_t rmt_register_tx_end_callback(rmt_tx_end_fn_t function, void *arg)
1170 {
1171 rmt_tx_end_callback_t previous = rmt_contex.rmt_tx_end_callback;
1172 rmt_contex.rmt_tx_end_callback.function = function;
1173 rmt_contex.rmt_tx_end_callback.arg = arg;
1174 return previous;
1175 }
1176
rmt_translator_init(rmt_channel_t channel,sample_to_rmt_t fn)1177 esp_err_t rmt_translator_init(rmt_channel_t channel, sample_to_rmt_t fn)
1178 {
1179 ESP_RETURN_ON_FALSE(fn, ESP_ERR_INVALID_ARG, TAG, RMT_TRANSLATOR_NULL_STR);
1180 ESP_RETURN_ON_FALSE(RMT_IS_TX_CHANNEL(channel), ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
1181 ESP_RETURN_ON_FALSE(p_rmt_obj[channel], ESP_FAIL, TAG, RMT_DRIVER_ERROR_STR);
1182 uint32_t mem_blocks = rmt_ll_tx_get_mem_blocks(rmt_contex.hal.regs, channel);
1183 ESP_RETURN_ON_FALSE(mem_blocks + channel <= SOC_RMT_CHANNELS_PER_GROUP, ESP_ERR_INVALID_STATE, TAG, RMT_MEM_CNT_ERROR_STR);
1184 const uint32_t block_size = mem_blocks * RMT_MEM_ITEM_NUM * sizeof(rmt_item32_t);
1185 if (p_rmt_obj[channel]->tx_buf == NULL) {
1186 #if !CONFIG_SPIRAM_USE_MALLOC
1187 p_rmt_obj[channel]->tx_buf = (rmt_item32_t *)calloc(1, block_size);
1188 #else
1189 if (p_rmt_obj[channel]->intr_alloc_flags & ESP_INTR_FLAG_IRAM) {
1190 p_rmt_obj[channel]->tx_buf = (rmt_item32_t *)heap_caps_calloc(1, block_size, MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
1191 } else {
1192 p_rmt_obj[channel]->tx_buf = (rmt_item32_t *)calloc(1, block_size);
1193 }
1194 #endif
1195 if (p_rmt_obj[channel]->tx_buf == NULL) {
1196 ESP_LOGE(TAG, "RMT translator buffer create fail");
1197 return ESP_FAIL;
1198 }
1199 }
1200 p_rmt_obj[channel]->sample_to_rmt = fn;
1201 p_rmt_obj[channel]->tx_context = NULL;
1202 p_rmt_obj[channel]->sample_size_remain = 0;
1203 p_rmt_obj[channel]->sample_cur = NULL;
1204 ESP_LOGD(TAG, "RMT translator init done");
1205 return ESP_OK;
1206 }
1207
rmt_translator_set_context(rmt_channel_t channel,void * context)1208 esp_err_t rmt_translator_set_context(rmt_channel_t channel, void *context)
1209 {
1210 ESP_RETURN_ON_FALSE(channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
1211 ESP_RETURN_ON_FALSE(p_rmt_obj[channel], ESP_FAIL, TAG, RMT_DRIVER_ERROR_STR);
1212
1213 p_rmt_obj[channel]->tx_context = context;
1214 return ESP_OK;
1215 }
1216
rmt_translator_get_context(const size_t * item_num,void ** context)1217 esp_err_t rmt_translator_get_context(const size_t *item_num, void **context)
1218 {
1219 ESP_RETURN_ON_FALSE(item_num && context, ESP_ERR_INVALID_ARG, TAG, "invalid arguments");
1220
1221 // the address of tx_len_rem is directlly passed to the callback,
1222 // so it's possible to get the object address from that
1223 rmt_obj_t *obj = __containerof(item_num, rmt_obj_t, tx_len_rem);
1224 *context = obj->tx_context;
1225
1226 return ESP_OK;
1227 }
1228
rmt_write_sample(rmt_channel_t channel,const uint8_t * src,size_t src_size,bool wait_tx_done)1229 esp_err_t rmt_write_sample(rmt_channel_t channel, const uint8_t *src, size_t src_size, bool wait_tx_done)
1230 {
1231 ESP_RETURN_ON_FALSE(RMT_IS_TX_CHANNEL(channel), ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
1232 ESP_RETURN_ON_FALSE(p_rmt_obj[channel], ESP_FAIL, TAG, RMT_DRIVER_ERROR_STR);
1233 ESP_RETURN_ON_FALSE(p_rmt_obj[channel]->sample_to_rmt, ESP_FAIL, TAG, RMT_TRANSLATOR_UNINIT_STR);
1234 uint32_t mem_blocks = rmt_ll_tx_get_mem_blocks(rmt_contex.hal.regs, channel);
1235 ESP_RETURN_ON_FALSE(mem_blocks + channel <= SOC_RMT_CHANNELS_PER_GROUP, ESP_ERR_INVALID_STATE, TAG, RMT_MEM_CNT_ERROR_STR);
1236 #if CONFIG_SPIRAM_USE_MALLOC
1237 if (p_rmt_obj[channel]->intr_alloc_flags & ESP_INTR_FLAG_IRAM) {
1238 if (!esp_ptr_internal(src)) {
1239 ESP_LOGE(TAG, RMT_PSRAM_BUFFER_WARN_STR);
1240 return ESP_ERR_INVALID_ARG;
1241 }
1242 }
1243 #endif
1244 size_t translated_size = 0;
1245 rmt_obj_t *p_rmt = p_rmt_obj[channel];
1246 const uint32_t item_block_len = mem_blocks * RMT_MEM_ITEM_NUM;
1247 const uint32_t item_sub_len = item_block_len / 2;
1248 xSemaphoreTake(p_rmt->tx_sem, portMAX_DELAY);
1249 p_rmt->sample_to_rmt((void *)src, p_rmt->tx_buf, src_size, item_block_len, &translated_size, &p_rmt->tx_len_rem);
1250 p_rmt->sample_size_remain = src_size - translated_size;
1251 p_rmt->sample_cur = src + translated_size;
1252 rmt_fill_memory(channel, p_rmt->tx_buf, p_rmt->tx_len_rem, 0);
1253 if (p_rmt->tx_len_rem == item_block_len) {
1254 rmt_set_tx_thr_intr_en(channel, 1, item_sub_len);
1255 p_rmt->tx_data = p_rmt->tx_buf;
1256 p_rmt->tx_offset = 0;
1257 p_rmt->tx_sub_len = item_sub_len;
1258 p_rmt->translator = true;
1259 } else {
1260 rmt_idle_level_t idle_level = rmt_ll_tx_get_idle_level(rmt_contex.hal.regs, channel);
1261 rmt_item32_t stop_data = (rmt_item32_t) {
1262 .level0 = idle_level,
1263 .duration0 = 0,
1264 };
1265 rmt_fill_memory(channel, &stop_data, 1, p_rmt->tx_len_rem);
1266 p_rmt->tx_len_rem = 0;
1267 p_rmt->sample_cur = NULL;
1268 p_rmt->translator = false;
1269 }
1270 rmt_tx_start(channel, true);
1271 p_rmt->wait_done = wait_tx_done;
1272 if (wait_tx_done) {
1273 xSemaphoreTake(p_rmt->tx_sem, portMAX_DELAY);
1274 xSemaphoreGive(p_rmt->tx_sem);
1275 }
1276 return ESP_OK;
1277 }
1278
rmt_get_channel_status(rmt_channel_status_result_t * channel_status)1279 esp_err_t rmt_get_channel_status(rmt_channel_status_result_t *channel_status)
1280 {
1281 ESP_RETURN_ON_FALSE(channel_status, ESP_ERR_INVALID_ARG, TAG, RMT_PARAM_ERR_STR);
1282 for (int i = 0; i < RMT_CHANNEL_MAX; i++) {
1283 channel_status->status[i] = RMT_CHANNEL_UNINIT;
1284 if (p_rmt_obj[i]) {
1285 if (p_rmt_obj[i]->tx_sem) {
1286 if (xSemaphoreTake(p_rmt_obj[i]->tx_sem, (TickType_t)0) == pdTRUE) {
1287 channel_status->status[i] = RMT_CHANNEL_IDLE;
1288 xSemaphoreGive(p_rmt_obj[i]->tx_sem);
1289 } else {
1290 channel_status->status[i] = RMT_CHANNEL_BUSY;
1291 }
1292 }
1293 }
1294 }
1295 return ESP_OK;
1296 }
1297
rmt_get_counter_clock(rmt_channel_t channel,uint32_t * clock_hz)1298 esp_err_t rmt_get_counter_clock(rmt_channel_t channel, uint32_t *clock_hz)
1299 {
1300 ESP_RETURN_ON_FALSE(channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
1301 ESP_RETURN_ON_FALSE(clock_hz, ESP_ERR_INVALID_ARG, TAG, "parameter clock_hz can't be null");
1302 RMT_ENTER_CRITICAL();
1303 uint32_t rmt_source_clk_hz = 0;
1304 #if SOC_RMT_CHANNEL_CLK_INDEPENDENT
1305 rmt_source_clk_hz = s_rmt_source_clock_hz[channel];
1306 #else
1307 rmt_source_clk_hz = s_rmt_source_clock_hz;
1308 #endif
1309 if (RMT_IS_RX_CHANNEL(channel)) {
1310 *clock_hz = rmt_source_clk_hz / rmt_ll_rx_get_channel_clock_div(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel));
1311 } else {
1312 *clock_hz = rmt_source_clk_hz / rmt_ll_tx_get_channel_clock_div(rmt_contex.hal.regs, channel);
1313 }
1314 RMT_EXIT_CRITICAL();
1315 return ESP_OK;
1316 }
1317
1318 #if SOC_RMT_SUPPORT_TX_SYNCHRO
rmt_add_channel_to_group(rmt_channel_t channel)1319 esp_err_t rmt_add_channel_to_group(rmt_channel_t channel)
1320 {
1321 ESP_RETURN_ON_FALSE(RMT_IS_TX_CHANNEL(channel), ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
1322 RMT_ENTER_CRITICAL();
1323 rmt_ll_tx_enable_sync(rmt_contex.hal.regs, true);
1324 rmt_contex.synchro_channel_mask |= (1 << channel);
1325 rmt_ll_tx_sync_group_add_channels(rmt_contex.hal.regs, 1 << channel);
1326 rmt_ll_tx_reset_channels_clock_div(rmt_contex.hal.regs, rmt_contex.synchro_channel_mask);
1327 RMT_EXIT_CRITICAL();
1328 return ESP_OK;
1329 }
1330
rmt_remove_channel_from_group(rmt_channel_t channel)1331 esp_err_t rmt_remove_channel_from_group(rmt_channel_t channel)
1332 {
1333 ESP_RETURN_ON_FALSE(RMT_IS_TX_CHANNEL(channel), ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
1334 RMT_ENTER_CRITICAL();
1335 rmt_contex.synchro_channel_mask &= ~(1 << channel);
1336 rmt_ll_tx_sync_group_remove_channels(rmt_contex.hal.regs, 1 << channel);
1337 if (rmt_contex.synchro_channel_mask == 0) {
1338 rmt_ll_tx_enable_sync(rmt_contex.hal.regs, false);
1339 }
1340 RMT_EXIT_CRITICAL();
1341 return ESP_OK;
1342 }
1343 #endif
1344
1345 #if SOC_RMT_SUPPORT_TX_LOOP_COUNT
rmt_set_tx_loop_count(rmt_channel_t channel,uint32_t count)1346 esp_err_t rmt_set_tx_loop_count(rmt_channel_t channel, uint32_t count)
1347 {
1348 ESP_RETURN_ON_FALSE(RMT_IS_TX_CHANNEL(channel), ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
1349 ESP_RETURN_ON_FALSE(count <= RMT_LL_MAX_LOOP_COUNT_PER_BATCH, ESP_ERR_INVALID_ARG, TAG, "Invalid count value");
1350 RMT_ENTER_CRITICAL();
1351 rmt_ll_tx_set_loop_count(rmt_contex.hal.regs, channel, count);
1352 RMT_EXIT_CRITICAL();
1353 return ESP_OK;
1354 }
1355
rmt_enable_tx_loop_autostop(rmt_channel_t channel,bool en)1356 esp_err_t rmt_enable_tx_loop_autostop(rmt_channel_t channel, bool en)
1357 {
1358 ESP_RETURN_ON_FALSE(RMT_IS_TX_CHANNEL(channel), ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
1359 p_rmt_obj[channel]->loop_autostop = en;
1360 #if SOC_RMT_SUPPORT_TX_LOOP_AUTO_STOP
1361 RMT_ENTER_CRITICAL();
1362 rmt_ll_tx_enable_loop_autostop(rmt_contex.hal.regs, channel, en);
1363 RMT_EXIT_CRITICAL();
1364 #endif
1365 return ESP_OK;
1366 }
1367 #endif
1368
1369 /**
1370 * @brief This function will be called during start up, to check that this legacy RMT driver is not running along with the new driver
1371 */
1372 __attribute__((constructor))
check_rmt_legacy_driver_conflict(void)1373 static void check_rmt_legacy_driver_conflict(void)
1374 {
1375 // This function was declared as weak here. The new RMT driver has one implementation.
1376 // So if the new RMT driver is not linked in, then `rmt_acquire_group_handle()` should be NULL at runtime.
1377 extern __attribute__((weak)) void *rmt_acquire_group_handle(int group_id);
1378 if ((void *)rmt_acquire_group_handle != NULL) {
1379 ESP_EARLY_LOGE(TAG, "CONFLICT! driver_ng is not allowed to be used with the legacy driver");
1380 abort();
1381 }
1382 ESP_EARLY_LOGW(TAG, "legacy driver is deprecated, please migrate to `driver/rmt_tx.h` and/or `driver/rmt_rx.h`");
1383 }
1384