12     hal->regs = &RMT;  in rmt_hal_init()
13     rmt_ll_mem_power_by_pmu(hal->regs);  in rmt_hal_init()
14     rmt_ll_enable_mem_access_nonfifo(hal->regs, true);     // APB access the RMTMEM in nonfifo mode  in rmt_hal_init()
15     rmt_ll_enable_interrupt(hal->regs, UINT32_MAX, false); // disable all interupt events  in rmt_hal_init()
16     rmt_ll_clear_interrupt_status(hal->regs, UINT32_MAX);  // clear all pending events  in rmt_hal_init()
17     rmt_ll_enable_group_clock(hal->regs, true);            // enable clock source  in rmt_hal_init()
19     rmt_ll_tx_clear_sync_group(hal->regs);  in rmt_hal_init()
25     rmt_ll_enable_interrupt(hal->regs, UINT32_MAX, false); // disable all interupt events  in rmt_hal_deinit()
26     rmt_ll_clear_interrupt_status(hal->regs, UINT32_MAX);  // clear all pending events  in rmt_hal_deinit()
27 … rmt_ll_mem_force_power_off(hal->regs);                 // power off RMTMEM power domain forcefully  in rmt_hal_deinit()
28     rmt_ll_enable_group_clock(hal->regs, false);           // disable clock source  in rmt_hal_deinit()
29     hal->regs = NULL;  in rmt_hal_deinit()
34     rmt_ll_tx_reset_channels_clock_div(hal->regs, 1 << channel);  in rmt_hal_tx_channel_reset()
35     rmt_ll_tx_reset_pointer(hal->regs, channel);  in rmt_hal_tx_channel_reset()
37     rmt_ll_tx_reset_loop_count(hal->regs, channel);  in rmt_hal_tx_channel_reset()
39     rmt_ll_enable_interrupt(hal->regs, RMT_LL_EVENT_TX_MASK(channel), false);  in rmt_hal_tx_channel_reset()
40     rmt_ll_clear_interrupt_status(hal->regs, RMT_LL_EVENT_TX_MASK(channel));  in rmt_hal_tx_channel_reset()
45     rmt_ll_rx_reset_channels_clock_div(hal->regs, 1 << channel);  in rmt_hal_rx_channel_reset()
46     rmt_ll_rx_reset_pointer(hal->regs, channel);  in rmt_hal_rx_channel_reset()
47     rmt_ll_enable_interrupt(hal->regs, RMT_LL_EVENT_RX_MASK(channel), false);  in rmt_hal_rx_channel_reset()
48     rmt_ll_clear_interrupt_status(hal->regs, RMT_LL_EVENT_RX_MASK(channel));  in rmt_hal_rx_channel_reset()