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Searched refs:RTC_CNTL_SWD_CONF_REG (Results 1 – 22 of 22) sorted by relevance

/hal_espressif-latest/zephyr/esp32c2/src/
Dsoc_init.c24 REG_CLR_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST); in ana_super_wdt_reset_config()
26 REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST); in ana_super_wdt_reset_config()
50 REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_AUTO_FEED_EN); in super_wdt_auto_feed()
/hal_espressif-latest/zephyr/esp32c3/src/
Dsoc_init.c34 REG_CLR_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST); in ana_super_wdt_reset_config()
36 REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST); in ana_super_wdt_reset_config()
95 REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_AUTO_FEED_EN); in super_wdt_auto_feed()
/hal_espressif-latest/components/bootloader_support/src/esp32c2/
Dbootloader_soc.c15 REG_CLR_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST); in bootloader_ana_super_wdt_reset_config()
17 REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST); in bootloader_ana_super_wdt_reset_config()
Dbootloader_esp32c2.c81 REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_AUTO_FEED_EN); in bootloader_super_wdt_auto_feed()
/hal_espressif-latest/components/bootloader_support/src/esp32c3/
Dbootloader_soc.c15 REG_CLR_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST); in bootloader_ana_super_wdt_reset_config()
17 REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST); in bootloader_ana_super_wdt_reset_config()
Dbootloader_esp32c3.c86 REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_AUTO_FEED_EN); in bootloader_super_wdt_auto_feed()
/hal_espressif-latest/components/bootloader_support/src/esp32s3/
Dbootloader_soc.c15 REG_CLR_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST); in bootloader_ana_super_wdt_reset_config()
17 REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST); in bootloader_ana_super_wdt_reset_config()
Dbootloader_esp32s3.c129 REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_AUTO_FEED_EN); in bootloader_super_wdt_auto_feed()
/hal_espressif-latest/zephyr/esp32s3/src/
Dsoc_init.c23 REG_CLR_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST); in ana_super_wdt_reset_config()
25 REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST); in ana_super_wdt_reset_config()
61 REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_AUTO_FEED_EN); in super_wdt_auto_feed()
/hal_espressif-latest/tools/esptool_py/esptool/targets/
Desp32c3.py80 RTC_CNTL_SWD_CONF_REG = RTCCNTL_BASE_REG + 0x00AC variable in ESP32C3ROM
245 self.RTC_CNTL_SWD_CONF_REG,
246 self.read_reg(self.RTC_CNTL_SWD_CONF_REG)
Desp32s3.py88 RTC_CNTL_SWD_CONF_REG = RTCCNTL_BASE_REG + 0x00B4 variable in ESP32S3ROM
336 self.RTC_CNTL_SWD_CONF_REG,
337 self.read_reg(self.RTC_CNTL_SWD_CONF_REG)
Desp32h2.py23 RTC_CNTL_SWD_CONF_REG = DR_REG_LP_WDT_BASE + 0x0020 # LP_WDT_SWD_CONFIG_REG variable in ESP32H2ROM
Desp32c6.py77 RTC_CNTL_SWD_CONF_REG = DR_REG_LP_WDT_BASE + 0x001C # LP_WDT_SWD_CONFIG_REG variable in ESP32C6ROM
/hal_espressif-latest/tools/esptool_py/flasher_stub/include/
Dsoc_support.h391 #define RTC_CNTL_SWD_CONF_REG (RTCCNTL_BASE_REG + 0x00B4) macro
400 #define RTC_CNTL_SWD_CONF_REG (RTCCNTL_BASE_REG + 0x00AC) macro
409 #define RTC_CNTL_SWD_CONF_REG (DR_REG_LP_WDT_BASE + 0x001C) // LP_WDT_SWD_CONFIG_REG macro
418 #define RTC_CNTL_SWD_CONF_REG (DR_REG_LP_WDT_BASE + 0x0020) // LP_WDT_SWD_CONFIG_REG macro
/hal_espressif-latest/zephyr/esp32s2/src/
Dsoc_init.c20 REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_AUTO_FEED_EN); in super_wdt_auto_feed()
/hal_espressif-latest/components/bootloader_support/src/esp32s2/
Dbootloader_esp32s2.c109 REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_AUTO_FEED_EN); in bootloader_super_wdt_auto_feed()
/hal_espressif-latest/tools/esptool_py/flasher_stub/
Dstub_flasher.c120 REG_SET_MASK(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_AUTO_FEED_EN); // Autofeed super watchdog in disable_watchdogs()
/hal_espressif-latest/tools/esptool_py/test/
Dtest_esptool.py740 reg_mod.RTC_CNTL_SWD_CONF_REG, 0, mask=reg_mod.RTC_CNTL_SWD_AUTO_FEED_EN
760 output = reg_mod.read_reg(reg_mod.RTC_CNTL_SWD_CONF_REG)
/hal_espressif-latest/components/soc/esp32c2/include/soc/
Drtc_cntl_reg.h1155 #define RTC_CNTL_SWD_CONF_REG (DR_REG_RTCCNTL_BASE + 0xA0) macro
/hal_espressif-latest/components/soc/esp32c3/include/soc/
Drtc_cntl_reg.h1723 #define RTC_CNTL_SWD_CONF_REG (DR_REG_RTCCNTL_BASE + 0x00AC) macro
/hal_espressif-latest/components/soc/esp32s2/include/soc/
Drtc_cntl_reg.h2214 #define RTC_CNTL_SWD_CONF_REG (DR_REG_RTCCNTL_BASE + 0x00B0) macro
/hal_espressif-latest/components/soc/esp32s3/include/soc/
Drtc_cntl_reg.h2117 #define RTC_CNTL_SWD_CONF_REG (DR_REG_RTCCNTL_BASE + 0xB4) macro