1 /*
2 * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6 #include <stdbool.h>
7 #include "soc_init.h"
8 #include "soc/rtc_cntl_reg.h"
9 #include "esp_private/regi2c_ctrl.h"
10 #include "soc/regi2c_lp_bias.h"
11 #include "soc/regi2c_bias.h"
12 #include "hal/efuse_hal.h"
13 #include "soc/chip_revision.h"
14 #include "soc/system_reg.h"
15 #include "soc/assist_debug_reg.h"
16 #include "soc/reset_reasons.h"
17 #include "esp_log.h"
18
19 const static char *TAG = "soc_init";
20
soc_hw_init(void)21 void soc_hw_init(void)
22 {
23 if (!ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 3)) {
24 REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_XPD_IPH, 1);
25 REGI2C_WRITE_MASK(I2C_BIAS, I2C_BIAS_DREG_1P1_PVT, 12);
26 }
27 }
28
ana_super_wdt_reset_config(bool enable)29 void ana_super_wdt_reset_config(bool enable)
30 {
31 REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_SUPER_WDT_RST);
32
33 if (enable) {
34 REG_CLR_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST);
35 } else {
36 REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST);
37 }
38 }
39
ana_bod_reset_config(bool enable)40 void ana_bod_reset_config(bool enable)
41 {
42 REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_BOD_RST);
43
44 if (enable) {
45 REG_SET_BIT(RTC_CNTL_BROWN_OUT_REG, RTC_CNTL_BROWN_OUT_ANA_RST_EN);
46 } else {
47 REG_CLR_BIT(RTC_CNTL_BROWN_OUT_REG, RTC_CNTL_BROWN_OUT_ANA_RST_EN);
48 }
49 }
50
ana_clock_glitch_reset_config(bool enable)51 void ana_clock_glitch_reset_config(bool enable)
52 {
53 REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_GLITCH_RST);
54
55 if (enable) {
56 REG_SET_BIT(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_GLITCH_RST_EN);
57 } else {
58 REG_CLR_BIT(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_GLITCH_RST_EN);
59 }
60 }
61
ana_reset_config(void)62 void ana_reset_config(void)
63 {
64 ana_super_wdt_reset_config(true);
65
66 /* For origin chip & ECO1: brownout & clock glitch reset not available
67 * For ECO2: fix brownout reset bug
68 * For ECO3: fix clock glitch reset bug
69 */
70 switch (efuse_hal_chip_revision()) {
71 case 0:
72 case 1:
73 /* Disable BOD and GLITCH reset */
74 ana_bod_reset_config(false);
75 ana_clock_glitch_reset_config(false);
76 break;
77 case 2:
78 /* Enable BOD reset. Disable GLITCH reset */
79 ana_bod_reset_config(true);
80 ana_clock_glitch_reset_config(false);
81 break;
82 case 3:
83 default:
84 /* Enable BOD, and GLITCH reset */
85 ana_bod_reset_config(true);
86 ana_clock_glitch_reset_config(true);
87 break;
88 }
89 }
90
super_wdt_auto_feed(void)91 void super_wdt_auto_feed(void)
92
93 {
94 REG_WRITE(RTC_CNTL_SWD_WPROTECT_REG, RTC_CNTL_SWD_WKEY_VALUE);
95 REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_AUTO_FEED_EN);
96 REG_WRITE(RTC_CNTL_SWD_WPROTECT_REG, 0);
97 }
98
wdt_reset_cpu0_info_enable(void)99 void wdt_reset_cpu0_info_enable(void)
100 {
101 REG_SET_BIT(SYSTEM_CPU_PERI_CLK_EN_REG, SYSTEM_CLK_EN_ASSIST_DEBUG);
102 REG_CLR_BIT(SYSTEM_CPU_PERI_RST_EN_REG, SYSTEM_RST_EN_ASSIST_DEBUG);
103 REG_WRITE(ASSIST_DEBUG_CORE_0_RCD_EN_REG,
104 ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN | ASSIST_DEBUG_CORE_0_RCD_RECORDEN);
105 }
106
check_wdt_reset(void)107 void check_wdt_reset(void)
108 {
109 int wdt_rst = 0;
110 soc_reset_reason_t rst_reas;
111
112 rst_reas = esp_rom_get_reset_reason(0);
113 if (rst_reas == RESET_REASON_CORE_RTC_WDT || rst_reas == RESET_REASON_CORE_MWDT0 ||
114 rst_reas == RESET_REASON_CORE_MWDT1 || rst_reas == RESET_REASON_CPU0_MWDT0 ||
115 rst_reas == RESET_REASON_CPU0_MWDT1 || rst_reas == RESET_REASON_CPU0_RTC_WDT) {
116 ESP_EARLY_LOGW(TAG, "PRO CPU has been reset by WDT.");
117 wdt_rst = 1;
118 }
119
120 wdt_reset_cpu0_info_enable();
121 }
122
