1 /*
2  * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 #include <stdint.h>
7 #include "sdkconfig.h"
8 #include "esp_attr.h"
9 #include "esp_log.h"
10 #include "esp_image_format.h"
11 #include "flash_qio_mode.h"
12 #include "esp_rom_gpio.h"
13 #include "esp_rom_efuse.h"
14 #include "esp_rom_uart.h"
15 #include "esp_rom_sys.h"
16 #include "esp_rom_spiflash.h"
17 #include "soc/efuse_reg.h"
18 #include "soc/gpio_sig_map.h"
19 #include "soc/io_mux_reg.h"
20 #include "soc/assist_debug_reg.h"
21 #include "esp_cpu.h"
22 #include "soc/rtc.h"
23 #include "soc/rtc_cntl_reg.h"
24 #include "soc/spi_periph.h"
25 #include "soc/extmem_reg.h"
26 #include "soc/io_mux_reg.h"
27 #include "soc/system_reg.h"
28 #include "soc/chip_revision.h"
29 #include "esp32c3/rom/efuse.h"
30 #include "esp32c3/rom/ets_sys.h"
31 #include "bootloader_common.h"
32 #include "bootloader_init.h"
33 #include "bootloader_clock.h"
34 #include "bootloader_flash_config.h"
35 #include "bootloader_mem.h"
36 #include "esp_private/regi2c_ctrl.h"
37 #include "soc/regi2c_lp_bias.h"
38 #include "soc/regi2c_bias.h"
39 #include "bootloader_console.h"
40 #include "bootloader_flash_priv.h"
41 #include "esp_private/bootloader_flash_internal.h"
42 #include "bootloader_soc.h"
43 #include "esp_efuse.h"
44 #include "hal/mmu_hal.h"
45 #include "hal/cache_hal.h"
46 #include "hal/efuse_hal.h"
47 #if !defined(CONFIG_BOOTLOADER_MCUBOOT)
48 #include "esp_flash_internal.h"
49 #endif
50 
51 static const char *TAG = "boot.esp32c3";
52 
wdt_reset_cpu0_info_enable(void)53 static void wdt_reset_cpu0_info_enable(void)
54 {
55     REG_SET_BIT(SYSTEM_CPU_PERI_CLK_EN_REG, SYSTEM_CLK_EN_ASSIST_DEBUG);
56     REG_CLR_BIT(SYSTEM_CPU_PERI_RST_EN_REG, SYSTEM_RST_EN_ASSIST_DEBUG);
57     REG_WRITE(ASSIST_DEBUG_CORE_0_RCD_EN_REG, ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN | ASSIST_DEBUG_CORE_0_RCD_RECORDEN);
58 }
59 
wdt_reset_info_dump(int cpu)60 static void wdt_reset_info_dump(int cpu)
61 {
62     (void) cpu;
63     // saved PC was already printed by the ROM bootloader.
64     // nothing to do here.
65 }
66 
bootloader_check_wdt_reset(void)67 static void bootloader_check_wdt_reset(void)
68 {
69     int wdt_rst = 0;
70     soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0);
71     if (rst_reason == RESET_REASON_CORE_RTC_WDT || rst_reason == RESET_REASON_CORE_MWDT0 || rst_reason == RESET_REASON_CORE_MWDT1 ||
72         rst_reason == RESET_REASON_CPU0_MWDT0 || rst_reason == RESET_REASON_CPU0_MWDT1 || rst_reason == RESET_REASON_CPU0_RTC_WDT) {
73         ESP_EARLY_LOGW(TAG, "PRO CPU has been reset by WDT.");
74         wdt_rst = 1;
75     }
76     if (wdt_rst) {
77         // if reset by WDT dump info from trace port
78         wdt_reset_info_dump(0);
79     }
80     wdt_reset_cpu0_info_enable();
81 }
82 
bootloader_super_wdt_auto_feed(void)83 static void bootloader_super_wdt_auto_feed(void)
84 {
85     REG_WRITE(RTC_CNTL_SWD_WPROTECT_REG, RTC_CNTL_SWD_WKEY_VALUE);
86     REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_AUTO_FEED_EN);
87     REG_WRITE(RTC_CNTL_SWD_WPROTECT_REG, 0);
88 }
89 
bootloader_hardware_init(void)90 static inline void bootloader_hardware_init(void)
91 {
92     // This check is always included in the bootloader so it can
93     // print the minimum revision error message later in the boot
94     if (!ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 3)) {
95         REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_XPD_IPH, 1);
96         REGI2C_WRITE_MASK(I2C_BIAS, I2C_BIAS_DREG_1P1_PVT, 12);
97     }
98 }
99 
bootloader_ana_reset_config(void)100 static inline void bootloader_ana_reset_config(void)
101 {
102     //Enable super WDT reset.
103     bootloader_ana_super_wdt_reset_config(true);
104 
105     /*
106       For origin chip & ECO1: brownout & clock glitch reset not available
107       For ECO2: fix brownout reset bug
108       For ECO3: fix clock glitch reset bug
109     */
110     switch (efuse_hal_chip_revision()) {
111         case 0:
112         case 1:
113             //Disable BOD and GLITCH reset
114             bootloader_ana_bod_reset_config(false);
115             bootloader_ana_clock_glitch_reset_config(false);
116             break;
117         case 2:
118             //Enable BOD reset. Disable GLITCH reset
119             bootloader_ana_bod_reset_config(true);
120             bootloader_ana_clock_glitch_reset_config(false);
121             break;
122         case 3:
123         default:
124             //Enable BOD, and GLITCH reset
125             bootloader_ana_bod_reset_config(true);
126             bootloader_ana_clock_glitch_reset_config(true);
127             break;
128     }
129 }
130 
bootloader_init(void)131 esp_err_t bootloader_init(void)
132 {
133     esp_err_t ret = ESP_OK;
134 
135     bootloader_hardware_init();
136     bootloader_ana_reset_config();
137     bootloader_super_wdt_auto_feed();
138 
139 // In RAM_APP, memory will be initialized in `call_start_cpu0`
140 #if !CONFIG_APP_BUILD_TYPE_RAM
141     // protect memory region
142     bootloader_init_mem();
143     /* check that static RAM is after the stack */
144     assert(&_bss_start <= &_bss_end);
145     assert(&_data_start <= &_data_end);
146 #ifndef __ZEPHYR__
147     // clear bss section
148     bootloader_clear_bss_section();
149 #endif
150 #endif // !CONFIG_APP_BUILD_TYPE_RAM
151 
152     // init eFuse virtual mode (read eFuses to RAM)
153 #ifdef CONFIG_EFUSE_VIRTUAL
154     ESP_EARLY_LOGW(TAG, "eFuse virtual mode is enabled. If Secure boot or Flash encryption is enabled then it does not provide any security. FOR TESTING ONLY!");
155 #ifndef CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH
156     esp_efuse_init_virtual_mode_in_ram();
157 #endif
158 #endif
159     // config clock
160     bootloader_clock_configure();
161     // initialize console, from now on, we can use esp_log
162     bootloader_console_init();
163     /* print 2nd bootloader banner */
164     bootloader_print_banner();
165 
166 #ifndef CONFIG_BOOTLOADER_MCUBOOT
167     spi_flash_init_chip_state();
168     if ((ret = esp_flash_init_default_chip()) != ESP_OK) {
169         return ret;
170     }
171 #endif
172 
173 #if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
174     //init cache hal
175     cache_hal_init();
176     //init mmu
177     mmu_hal_init();
178     // update flash ID
179     bootloader_flash_update_id();
180     // Check and run XMC startup flow
181     if ((ret = bootloader_flash_xmc_startup()) != ESP_OK) {
182         ESP_EARLY_LOGE(TAG, "failed when running XMC startup flow, reboot!");
183         return ret;
184     }
185 #if !CONFIG_APP_BUILD_TYPE_RAM
186     // read bootloader header
187     if ((ret = bootloader_read_bootloader_header()) != ESP_OK) {
188         ESP_EARLY_LOGE(TAG, "failed to read flash!");
189         return ret;
190     }
191     // read chip revision and check if it's compatible to bootloader
192     if ((ret = bootloader_check_bootloader_validity()) != ESP_OK) {
193         ESP_EARLY_LOGE(TAG, "failed to vallidate!");
194         return ret;
195     }
196 #endif  //#if !CONFIG_APP_BUILD_TYPE_RAM
197     // initialize spi flash
198     if ((ret = bootloader_init_spi_flash()) != ESP_OK) {
199         ESP_EARLY_LOGE(TAG, "failed to init spi flash!");
200         return ret;
201     }
202 #endif // !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
203 
204     // check whether a WDT reset happend
205     bootloader_check_wdt_reset();
206     // config WDT
207     bootloader_config_wdt();
208     // enable RNG early entropy source
209     bootloader_enable_random();
210 
211     return ret;
212 }
213