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Searched refs:RTC_CNTL_INT_CLR_REG (Results 1 – 22 of 22) sorted by relevance

/hal_espressif-latest/components/hal/esp32s2/include/hal/
Drtc_cntl_ll.h24 SET_PERI_REG_MASK(RTC_CNTL_INT_CLR_REG, RTC_CNTL_MAIN_TIMER_INT_CLR_M); in rtc_cntl_ll_set_wakeup_timer()
64 REG_SET_BIT(RTC_CNTL_INT_CLR_REG, RTC_CNTL_ULP_CP_INT_CLR); in rtc_cntl_ll_ulp_int_clear()
65 REG_SET_BIT(RTC_CNTL_INT_CLR_REG, RTC_CNTL_COCPU_INT_CLR); in rtc_cntl_ll_ulp_int_clear()
66 REG_SET_BIT(RTC_CNTL_INT_CLR_REG, RTC_CNTL_COCPU_TRAP_INT_CLR); in rtc_cntl_ll_ulp_int_clear()
/hal_espressif-latest/components/hal/esp32s3/include/hal/
Drtc_cntl_ll.h28 SET_PERI_REG_MASK(RTC_CNTL_INT_CLR_REG, RTC_CNTL_MAIN_TIMER_INT_CLR_M); in rtc_cntl_ll_set_wakeup_timer()
144 REG_SET_BIT(RTC_CNTL_INT_CLR_REG, RTC_CNTL_ULP_CP_INT_CLR); in rtc_cntl_ll_ulp_int_clear()
145 REG_SET_BIT(RTC_CNTL_INT_CLR_REG, RTC_CNTL_COCPU_INT_CLR); in rtc_cntl_ll_ulp_int_clear()
146 REG_SET_BIT(RTC_CNTL_INT_CLR_REG, RTC_CNTL_COCPU_TRAP_INT_CLR); in rtc_cntl_ll_ulp_int_clear()
/hal_espressif-latest/components/hal/esp32/include/hal/
Drtc_cntl_ll.h67 REG_SET_BIT(RTC_CNTL_INT_CLR_REG, RTC_CNTL_SAR_INT_CLR); in rtc_cntl_ll_ulp_int_clear()
103 SET_PERI_REG_MASK(RTC_CNTL_INT_CLR_REG, RTC_CNTL_TIME_VALID_INT_CLR); in rtc_cntl_ll_get_rtc_time()
/hal_espressif-latest/components/esp_hw_support/
Drtc_module.c80 REG_WRITE(RTC_CNTL_INT_CLR_REG, status); in rtc_isr()
92 REG_WRITE(RTC_CNTL_INT_CLR_REG, UINT32_MAX); in rtc_isr_ensure_installed()
/hal_espressif-latest/components/esp_hw_support/port/esp32c3/
Drtc_sleep.c262 SET_PERI_REG_MASK(RTC_CNTL_INT_CLR_REG, in rtc_sleep_start()
284 SET_PERI_REG_MASK(RTC_CNTL_INT_CLR_REG, in rtc_deep_sleep_start()
359 SET_PERI_REG_MASK(RTC_CNTL_INT_CLR_REG, in rtc_sleep_finish()
Drtc_init.c164 REG_WRITE(RTC_CNTL_INT_CLR_REG, UINT32_MAX); in rtc_init()
/hal_espressif-latest/components/esp_hw_support/port/esp32s2/
Drtc_sleep.c271 SET_PERI_REG_MASK(RTC_CNTL_INT_CLR_REG, in rtc_sleep_start()
293 SET_PERI_REG_MASK(RTC_CNTL_INT_CLR_REG, in rtc_deep_sleep_start()
369 SET_PERI_REG_MASK(RTC_CNTL_INT_CLR_REG, in rtc_sleep_finish()
Drtc_init.c177 REG_WRITE(RTC_CNTL_INT_CLR_REG, UINT32_MAX); in rtc_init()
/hal_espressif-latest/components/esp_hw_support/port/esp32/
Drtc_sleep.c254 SET_PERI_REG_MASK(RTC_CNTL_INT_CLR_REG, in rtc_sleep_start()
276 SET_PERI_REG_MASK(RTC_CNTL_INT_CLR_REG, in rtc_deep_sleep_start()
352 SET_PERI_REG_MASK(RTC_CNTL_INT_CLR_REG, in rtc_sleep_finish()
Drtc_init.c110 REG_WRITE(RTC_CNTL_INT_CLR_REG, UINT32_MAX); in rtc_init()
/hal_espressif-latest/components/hal/esp32c2/include/hal/
Drtc_cntl_ll.h24 SET_PERI_REG_MASK(RTC_CNTL_INT_CLR_REG, RTC_CNTL_MAIN_TIMER_INT_CLR_M); in rtc_cntl_ll_set_wakeup_timer()
/hal_espressif-latest/components/esp_hw_support/port/esp32c2/
Drtc_sleep.c211 SET_PERI_REG_MASK(RTC_CNTL_INT_CLR_REG, in rtc_sleep_start()
229 SET_PERI_REG_MASK(RTC_CNTL_INT_CLR_REG, in rtc_sleep_finish()
Drtc_init.c123 REG_WRITE(RTC_CNTL_INT_CLR_REG, UINT32_MAX); in rtc_init()
/hal_espressif-latest/components/hal/esp32c3/include/hal/
Drtc_cntl_ll.h24 SET_PERI_REG_MASK(RTC_CNTL_INT_CLR_REG, RTC_CNTL_MAIN_TIMER_INT_CLR_M); in rtc_cntl_ll_set_wakeup_timer()
/hal_espressif-latest/components/bootloader_support/src/
Dbootloader_clock_init.c116 REG_WRITE(RTC_CNTL_INT_CLR_REG, UINT32_MAX); in bootloader_clock_configure()
/hal_espressif-latest/components/esp_hw_support/port/esp32s3/
Drtc_sleep.c274 SET_PERI_REG_MASK(RTC_CNTL_INT_CLR_REG, in rtc_sleep_start()
291 SET_PERI_REG_MASK(RTC_CNTL_INT_CLR_REG, in rtc_sleep_finish()
Drtc_init.c206 REG_WRITE(RTC_CNTL_INT_CLR_REG, UINT32_MAX); in rtc_init()
/hal_espressif-latest/components/soc/esp32c2/include/soc/
Drtc_cntl_reg.h523 #define RTC_CNTL_INT_CLR_REG (DR_REG_RTCCNTL_BASE + 0x44) macro
/hal_espressif-latest/components/soc/esp32/include/soc/
Drtc_cntl_reg.h706 #define RTC_CNTL_INT_CLR_REG (DR_REG_RTCCNTL_BASE + 0x48) macro
/hal_espressif-latest/components/soc/esp32c3/include/soc/
Drtc_cntl_reg.h746 #define RTC_CNTL_INT_CLR_REG (DR_REG_RTCCNTL_BASE + 0x004C) macro
/hal_espressif-latest/components/soc/esp32s2/include/soc/
Drtc_cntl_reg.h886 #define RTC_CNTL_INT_CLR_REG (DR_REG_RTCCNTL_BASE + 0x004C) macro
/hal_espressif-latest/components/soc/esp32s3/include/soc/
Drtc_cntl_reg.h963 #define RTC_CNTL_INT_CLR_REG (DR_REG_RTCCNTL_BASE + 0x4C) macro