1 /*
2  * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 #include <stdint.h>
8 
9 #include "soc/soc.h"
10 #include "soc/rtc.h"
11 #include "soc/rtc_periph.h"
12 #include "soc/dport_reg.h"
13 #include "hal/efuse_ll.h"
14 #include "soc/gpio_periph.h"
15 #ifndef BOOTLOADER_BUILD
16 #include "esp_private/sar_periph_ctrl.h"
17 #endif
18 
19 
rtc_init(rtc_config_t cfg)20 void rtc_init(rtc_config_t cfg)
21 {
22     /**
23      * When run rtc_init, it maybe deep sleep reset. Since we power down modem in deep sleep, after wakeup
24      * from deep sleep, these fields are changed and not reset. We will access two BB regs(BBPD_CTRL and
25      * NRXPD_CTRL) in rtc_sleep_pu. If PD modem and no iso, CPU will stuck when access these two BB regs
26      * and finally triggle RTC WDT. So need to clear modem Force PD.
27      *
28      * No worry about the power consumption, Because modem Force PD will be set at the end of this function.
29      */
30     CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PD);
31     CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_ISO);
32 
33     CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PVTMON_PU | RTC_CNTL_TXRF_I2C_PU |
34             RTC_CNTL_RFRX_PBUS_PU | RTC_CNTL_CKGEN_I2C_PU | RTC_CNTL_PLL_I2C_PU);
35 
36     REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, cfg.pll_wait);
37     REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_XTL_BUF_WAIT, cfg.xtal_wait);
38     REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, cfg.ck8m_wait);
39 
40     REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN, RTC_CNTL_DBG_ATTEN_DEFAULT);
41     SET_PERI_REG_MASK(RTC_CNTL_BIAS_CONF_REG,
42             RTC_CNTL_DEC_HEARTBEAT_WIDTH | RTC_CNTL_INC_HEARTBEAT_PERIOD);
43 
44     /* Reset RTC bias to default value (needed if waking up from deep sleep) */
45     REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DBIAS_WAK, RTC_CNTL_DBIAS_1V10);
46     REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DBIAS_SLP, RTC_CNTL_DBIAS_1V10);
47 
48     if (cfg.clkctl_init) {
49         //clear CMMU clock force on
50         DPORT_CLEAR_PERI_REG_MASK(DPORT_PRO_CACHE_CTRL1_REG, DPORT_PRO_CMMU_FORCE_ON);
51         DPORT_CLEAR_PERI_REG_MASK(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CMMU_FORCE_ON);
52         //clear rom clock force on
53         DPORT_SET_PERI_REG_BITS(DPORT_ROM_FO_CTRL_REG, DPORT_SHARE_ROM_FO, 0, DPORT_SHARE_ROM_FO_S);
54         DPORT_CLEAR_PERI_REG_MASK(DPORT_ROM_FO_CTRL_REG, DPORT_APP_ROM_FO);
55         DPORT_CLEAR_PERI_REG_MASK(DPORT_ROM_FO_CTRL_REG, DPORT_PRO_ROM_FO);
56         //clear sram clock force on
57         DPORT_CLEAR_PERI_REG_MASK(DPORT_SRAM_FO_CTRL_0_REG, DPORT_SRAM_FO_0);
58         DPORT_CLEAR_PERI_REG_MASK(DPORT_SRAM_FO_CTRL_1_REG, DPORT_SRAM_FO_1);
59         //clear tag clock force on
60         DPORT_CLEAR_PERI_REG_MASK(DPORT_TAG_FO_CTRL_REG, DPORT_APP_CACHE_TAG_FORCE_ON);
61         DPORT_CLEAR_PERI_REG_MASK(DPORT_TAG_FO_CTRL_REG, DPORT_PRO_CACHE_TAG_FORCE_ON);
62     }
63 
64     if (cfg.pwrctl_init) {
65         CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU);
66         //cancel xtal force pu
67         CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_XTL_FORCE_PU);
68         //cancel BIAS force pu
69         CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_CORE_FORCE_PU);
70         CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_I2C_FORCE_PU);
71         CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_FORCE_NOSLEEP);
72         // bias follow 8M
73         SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_CORE_FOLW_8M);
74         SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_I2C_FOLW_8M);
75         SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_SLEEP_FOLW_8M);
76         // CLEAR APLL close
77         CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PU);
78         SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PD);
79         CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BBPLL_FORCE_PU);
80         CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BBPLL_I2C_FORCE_PU);
81         //cancel RTC REG force PU
82         CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_FORCE_PU);
83         CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_DBOOST_FORCE_PU);
84         if (cfg.rtc_dboost_fpd) {
85             SET_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_DBOOST_FORCE_PD);
86         } else {
87             CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_DBOOST_FORCE_PD);
88         }
89         //cancel digital pu force
90         CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_LSLP_MEM_FORCE_PU);
91         CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_FORCE_PU);
92         CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PU);
93         CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_CPU_ROM_RAM_FORCE_PU);
94         CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_MEM_FORCE_PU);
95         CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_PWC_FORCE_PU);
96         CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_WRAP_FORCE_NOISO);
97         CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_NOISO);
98         CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_CPU_ROM_RAM_FORCE_NOISO);
99         CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_MEM_FORCE_NOISO);
100         CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_FORCE_NOISO);
101         //cancel digital PADS force no iso
102         CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD);
103         CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_NOISO);
104     }
105     /* force power down modem(wifi and btdm) power domain */
106     SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_ISO);
107     SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PD);
108 
109     REG_WRITE(RTC_CNTL_INT_ENA_REG, 0);
110     REG_WRITE(RTC_CNTL_INT_CLR_REG, UINT32_MAX);
111 
112 #ifndef BOOTLOADER_BUILD
113     //initialise SAR related peripheral register settings
114     sar_periph_ctrl_init();
115 #endif
116 }
117 
rtc_vddsdio_get_config(void)118 rtc_vddsdio_config_t rtc_vddsdio_get_config(void)
119 {
120     rtc_vddsdio_config_t result;
121     uint32_t sdio_conf_reg = REG_READ(RTC_CNTL_SDIO_CONF_REG);
122     result.drefh = (sdio_conf_reg & RTC_CNTL_DREFH_SDIO_M) >> RTC_CNTL_DREFH_SDIO_S;
123     result.drefm = (sdio_conf_reg & RTC_CNTL_DREFM_SDIO_M) >> RTC_CNTL_DREFM_SDIO_S;
124     result.drefl = (sdio_conf_reg & RTC_CNTL_DREFL_SDIO_M) >> RTC_CNTL_DREFL_SDIO_S;
125     if (sdio_conf_reg & RTC_CNTL_SDIO_FORCE) {
126         // Get configuration from RTC
127         result.force = 1;
128         result.enable = (sdio_conf_reg & RTC_CNTL_XPD_SDIO_REG_M) >> RTC_CNTL_XPD_SDIO_REG_S;
129         result.tieh = (sdio_conf_reg & RTC_CNTL_SDIO_TIEH_M) >> RTC_CNTL_SDIO_TIEH_S;
130         return result;
131     }
132     if (efuse_ll_get_sdio_force()) {
133         // Get configuration from EFUSE
134         result.force = 0;
135         result.enable = efuse_ll_get_xpd_sdio();
136         result.tieh = efuse_ll_get_sdio_tieh();
137         //DREFH/M/L eFuse are used for EFUSE_ADC_VREF instead. Therefore tuning
138         //will only be available on older chips that don't have EFUSE_ADC_VREF
139         if(efuse_ll_get_blk3_part_reserve() == 0){
140             //BLK3_PART_RESERVE indicates the presence of EFUSE_ADC_VREF
141             // in this case, DREFH/M/L are also set from EFUSE
142             result.drefh = efuse_ll_get_sdio_drefh();
143             result.drefm = efuse_ll_get_sdio_drefm();
144             result.drefl = efuse_ll_get_sdio_drefl();
145         }
146         return result;
147     }
148 
149     // Otherwise, VDD_SDIO is controlled by bootstrapping pin
150     uint32_t strap_reg = REG_READ(GPIO_STRAP_REG);
151     result.force = 0;
152     result.tieh = (strap_reg & BIT(5)) ? RTC_VDDSDIO_TIEH_1_8V : RTC_VDDSDIO_TIEH_3_3V;
153     result.enable = 1;
154     return result;
155 }
156 
rtc_vddsdio_set_config(rtc_vddsdio_config_t config)157 void rtc_vddsdio_set_config(rtc_vddsdio_config_t config)
158 {
159     uint32_t val = 0;
160     val |= (config.force << RTC_CNTL_SDIO_FORCE_S);
161     val |= (config.enable << RTC_CNTL_XPD_SDIO_REG_S);
162     val |= (config.drefh << RTC_CNTL_DREFH_SDIO_S);
163     val |= (config.drefm << RTC_CNTL_DREFM_SDIO_S);
164     val |= (config.drefl << RTC_CNTL_DREFL_SDIO_S);
165     val |= (config.tieh << RTC_CNTL_SDIO_TIEH_S);
166     val |= RTC_CNTL_SDIO_PD_EN;
167     REG_WRITE(RTC_CNTL_SDIO_CONF_REG, val);
168 }
169