1 /*
2 * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6 #include "sdkconfig.h"
7 #include "soc/soc.h"
8 #include "soc/rtc.h"
9 #include "soc/chip_revision.h"
10 #include "hal/efuse_hal.h"
11
12 #if !CONFIG_IDF_TARGET_ESP32C6 && !CONFIG_IDF_TARGET_ESP32H2 // TODO: IDF-5645
13 #include "soc/rtc_cntl_reg.h"
14 #else
15 #include "soc/lp_wdt_reg.h"
16 #include "soc/lp_timer_reg.h"
17 #include "soc/lp_analog_peri_reg.h"
18 #include "soc/pmu_reg.h"
19 #endif
20
21 #if CONFIG_IDF_TARGET_ESP32
22 #include "hal/clk_tree_ll.h"
23 #endif
24 #include "esp_rom_sys.h"
25 #include "esp_rom_uart.h"
26
bootloader_clock_configure(void)27 __attribute__((weak)) void bootloader_clock_configure(void)
28 {
29 // ROM bootloader may have put a lot of text into UART0 FIFO.
30 // Wait for it to be printed.
31 // This is not needed on power on reset, when ROM bootloader is running at
32 // 40 MHz. But in case of TG WDT reset, CPU may still be running at >80 MHZ,
33 // and will be done with the bootloader much earlier than UART FIFO is empty.
34 esp_rom_uart_tx_wait_idle(0);
35
36 /* Set CPU to a higher certain frequency. Keep other clocks unmodified. */
37 int cpu_freq_mhz = CPU_CLK_FREQ_MHZ_BTLD;
38
39 #if CONFIG_IDF_TARGET_ESP32
40 /* On ESP32 rev 0, switching to 80/160 MHz if clock was previously set to
41 * 240 MHz may cause the chip to lock up (see section 3.5 of the errata
42 * document). For rev. 0, switch to 240 instead if it has been enabled
43 * previously.
44 */
45 if (!ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 100) &&
46 clk_ll_cpu_get_freq_mhz_from_pll() == CLK_LL_PLL_240M_FREQ_MHZ) {
47 cpu_freq_mhz = 240;
48 }
49 #endif
50
51 rtc_clk_config_t clk_cfg = RTC_CLK_CONFIG_DEFAULT();
52
53 clk_cfg.cpu_freq_mhz = cpu_freq_mhz;
54
55 // Use RTC_SLOW clock source sel register field's default value, RC_SLOW, for 2nd stage bootloader
56 // RTC_SLOW clock source will be switched according to Kconfig selection at application startup
57 clk_cfg.slow_clk_src = rtc_clk_slow_src_get();
58 if (clk_cfg.slow_clk_src == SOC_RTC_SLOW_CLK_SRC_INVALID) {
59 clk_cfg.slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC_SLOW;
60 }
61
62 #if CONFIG_IDF_TARGET_ESP32C6
63 // TODO: IDF-5781 Some of esp32c6 SOC_RTC_FAST_CLK_SRC_XTAL_D2 rtc_fast clock has timing issue
64 // Force to use SOC_RTC_FAST_CLK_SRC_RC_FAST since 2nd stage bootloader
65 clk_cfg.fast_clk_src = SOC_RTC_FAST_CLK_SRC_RC_FAST;
66 #else
67 // Use RTC_FAST clock source sel register field's default value, XTAL_DIV, for 2nd stage bootloader
68 // RTC_FAST clock source will be switched to RC_FAST at application startup
69 clk_cfg.fast_clk_src = rtc_clk_fast_src_get();
70 if (clk_cfg.fast_clk_src == SOC_RTC_FAST_CLK_SRC_INVALID) {
71 clk_cfg.fast_clk_src = SOC_RTC_FAST_CLK_SRC_XTAL_DIV;
72 }
73 #endif
74 rtc_clk_init(clk_cfg);
75
76 /* As a slight optimization, if 32k XTAL was enabled in sdkconfig, we enable
77 * it here. Usually it needs some time to start up, so we amortize at least
78 * part of the start up time by enabling 32k XTAL early.
79 * App startup code will wait until the oscillator has started up.
80 */
81 #if CONFIG_ESP_SYSTEM_RTC_EXT_XTAL
82 if (!rtc_clk_32k_enabled()) {
83 rtc_clk_32k_bootstrap(CONFIG_ESP_SYSTEM_RTC_EXT_XTAL_BOOTSTRAP_CYCLES);
84 }
85 #endif // CONFIG_ESP_SYSTEM_RTC_EXT_XTAL
86
87 // TODO: IDF-5645
88 #if CONFIG_IDF_TARGET_ESP32C6
89 // CLR ENA
90 CLEAR_PERI_REG_MASK(LP_WDT_INT_ENA_REG, LP_WDT_SUPER_WDT_INT_ENA); /* SWD */
91 CLEAR_PERI_REG_MASK(LP_TIMER_LP_INT_ENA_REG, LP_TIMER_MAIN_TIMER_LP_INT_ENA); /* MAIN_TIMER */
92 CLEAR_PERI_REG_MASK(LP_ANALOG_PERI_LP_ANA_LP_INT_ENA_REG, LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_ENA); /* BROWN_OUT */
93 CLEAR_PERI_REG_MASK(LP_WDT_INT_ENA_REG, LP_WDT_LP_WDT_INT_ENA); /* WDT */
94 CLEAR_PERI_REG_MASK(PMU_HP_INT_ENA_REG, PMU_SOC_WAKEUP_INT_ENA); /* SLP_REJECT */
95 CLEAR_PERI_REG_MASK(PMU_HP_INT_ENA_REG, PMU_SOC_SLEEP_REJECT_INT_ENA); /* SLP_WAKEUP */
96 // SET CLR
97 SET_PERI_REG_MASK(LP_WDT_INT_CLR_REG, LP_WDT_SUPER_WDT_INT_CLR); /* SWD */
98 SET_PERI_REG_MASK(LP_TIMER_LP_INT_CLR_REG, LP_TIMER_MAIN_TIMER_LP_INT_CLR); /* MAIN_TIMER */
99 SET_PERI_REG_MASK(LP_ANALOG_PERI_LP_ANA_LP_INT_CLR_REG, LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_CLR); /* BROWN_OUT */
100 SET_PERI_REG_MASK(LP_WDT_INT_CLR_REG, LP_WDT_LP_WDT_INT_CLR); /* WDT */
101 #elif CONFIG_IDF_TARGET_ESP32H2
102 // CLR ENA
103 CLEAR_PERI_REG_MASK(LP_WDT_INT_ENA_REG, LP_WDT_SUPER_WDT_INT_ENA); /* SWD */
104 CLEAR_PERI_REG_MASK(LP_ANALOG_PERI_LP_ANA_LP_INT_ENA_REG, LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_ENA); /* BROWN_OUT */
105 CLEAR_PERI_REG_MASK(LP_WDT_INT_ENA_REG, LP_WDT_LP_WDT_INT_ENA); /* WDT */
106 CLEAR_PERI_REG_MASK(PMU_HP_INT_ENA_REG, PMU_SOC_WAKEUP_INT_ENA); /* SLP_REJECT */
107 CLEAR_PERI_REG_MASK(PMU_HP_INT_ENA_REG, PMU_SOC_SLEEP_REJECT_INT_ENA); /* SLP_WAKEUP */
108 // SET CLR
109 SET_PERI_REG_MASK(LP_WDT_INT_CLR_REG, LP_WDT_SUPER_WDT_INT_CLR); /* SWD */
110 SET_PERI_REG_MASK(LP_ANALOG_PERI_LP_ANA_LP_INT_CLR_REG, LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_CLR); /* BROWN_OUT */
111 SET_PERI_REG_MASK(LP_WDT_INT_CLR_REG, LP_WDT_LP_WDT_INT_CLR); /* WDT */
112 SET_PERI_REG_MASK(PMU_HP_INT_CLR_REG, PMU_SOC_WAKEUP_INT_CLR); /* SLP_REJECT */
113 SET_PERI_REG_MASK(PMU_HP_INT_CLR_REG, PMU_SOC_SLEEP_REJECT_INT_CLR); /* SLP_WAKEUP */
114 #else
115 REG_WRITE(RTC_CNTL_INT_ENA_REG, 0);
116 REG_WRITE(RTC_CNTL_INT_CLR_REG, UINT32_MAX);
117 #endif
118 }
119